Boot log: mt8192-asurada-spherion-r0
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 24
- Kernel Errors: 35
- Errors: 0
1 23:18:43.502290 lava-dispatcher, installed at version: 2023.10
2 23:18:43.502488 start: 0 validate
3 23:18:43.502618 Start time: 2023-12-03 23:18:43.502610+00:00 (UTC)
4 23:18:43.502736 Using caching service: 'http://localhost/cache/?uri=%s'
5 23:18:43.502871 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-libcamera%2F20230623.0%2Farm64%2Finitrd.cpio.gz exists
6 23:18:43.779498 Using caching service: 'http://localhost/cache/?uri=%s'
7 23:18:43.780244 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.64-cip10-rt5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 23:18:44.042514 Using caching service: 'http://localhost/cache/?uri=%s'
9 23:18:44.043327 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.64-cip10-rt5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 23:18:44.314606 Using caching service: 'http://localhost/cache/?uri=%s'
11 23:18:44.315368 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-libcamera%2F20230623.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 23:18:44.585213 Using caching service: 'http://localhost/cache/?uri=%s'
13 23:18:44.586367 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.64-cip10-rt5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 23:18:44.863763 validate duration: 1.36
16 23:18:44.865010 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 23:18:44.865599 start: 1.1 download-retry (timeout 00:10:00) [common]
18 23:18:44.866087 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 23:18:44.866710 Not decompressing ramdisk as can be used compressed.
20 23:18:44.867229 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-libcamera/20230623.0/arm64/initrd.cpio.gz
21 23:18:44.867601 saving as /var/lib/lava/dispatcher/tmp/12172422/tftp-deploy-gha09xov/ramdisk/initrd.cpio.gz
22 23:18:44.867955 total size: 4665398 (4 MB)
23 23:18:44.873280 progress 0 % (0 MB)
24 23:18:44.882143 progress 5 % (0 MB)
25 23:18:44.888977 progress 10 % (0 MB)
26 23:18:44.893697 progress 15 % (0 MB)
27 23:18:44.897331 progress 20 % (0 MB)
28 23:18:44.900359 progress 25 % (1 MB)
29 23:18:44.903205 progress 30 % (1 MB)
30 23:18:44.905571 progress 35 % (1 MB)
31 23:18:44.908059 progress 40 % (1 MB)
32 23:18:44.910382 progress 45 % (2 MB)
33 23:18:44.912392 progress 50 % (2 MB)
34 23:18:44.914260 progress 55 % (2 MB)
35 23:18:44.916042 progress 60 % (2 MB)
36 23:18:44.917819 progress 65 % (2 MB)
37 23:18:44.919412 progress 70 % (3 MB)
38 23:18:44.920989 progress 75 % (3 MB)
39 23:18:44.922557 progress 80 % (3 MB)
40 23:18:44.924222 progress 85 % (3 MB)
41 23:18:44.925648 progress 90 % (4 MB)
42 23:18:44.927050 progress 95 % (4 MB)
43 23:18:44.928435 progress 100 % (4 MB)
44 23:18:44.928593 4 MB downloaded in 0.06 s (73.35 MB/s)
45 23:18:44.928745 end: 1.1.1 http-download (duration 00:00:00) [common]
47 23:18:44.928990 end: 1.1 download-retry (duration 00:00:00) [common]
48 23:18:44.929078 start: 1.2 download-retry (timeout 00:10:00) [common]
49 23:18:44.929168 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 23:18:44.929307 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.64-cip10-rt5/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 23:18:44.929382 saving as /var/lib/lava/dispatcher/tmp/12172422/tftp-deploy-gha09xov/kernel/Image
52 23:18:44.929446 total size: 49172992 (46 MB)
53 23:18:44.929509 No compression specified
54 23:18:44.930628 progress 0 % (0 MB)
55 23:18:44.943399 progress 5 % (2 MB)
56 23:18:44.956047 progress 10 % (4 MB)
57 23:18:44.968655 progress 15 % (7 MB)
58 23:18:44.981242 progress 20 % (9 MB)
59 23:18:44.994042 progress 25 % (11 MB)
60 23:18:45.006749 progress 30 % (14 MB)
61 23:18:45.019623 progress 35 % (16 MB)
62 23:18:45.032202 progress 40 % (18 MB)
63 23:18:45.044812 progress 45 % (21 MB)
64 23:18:45.057276 progress 50 % (23 MB)
65 23:18:45.070074 progress 55 % (25 MB)
66 23:18:45.082681 progress 60 % (28 MB)
67 23:18:45.095332 progress 65 % (30 MB)
68 23:18:45.107938 progress 70 % (32 MB)
69 23:18:45.120523 progress 75 % (35 MB)
70 23:18:45.133269 progress 80 % (37 MB)
71 23:18:45.146125 progress 85 % (39 MB)
72 23:18:45.158601 progress 90 % (42 MB)
73 23:18:45.171077 progress 95 % (44 MB)
74 23:18:45.183606 progress 100 % (46 MB)
75 23:18:45.183818 46 MB downloaded in 0.25 s (184.36 MB/s)
76 23:18:45.183968 end: 1.2.1 http-download (duration 00:00:00) [common]
78 23:18:45.184194 end: 1.2 download-retry (duration 00:00:00) [common]
79 23:18:45.184283 start: 1.3 download-retry (timeout 00:10:00) [common]
80 23:18:45.184367 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 23:18:45.184505 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.64-cip10-rt5/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 23:18:45.184574 saving as /var/lib/lava/dispatcher/tmp/12172422/tftp-deploy-gha09xov/dtb/mt8192-asurada-spherion-r0.dtb
83 23:18:45.184633 total size: 47278 (0 MB)
84 23:18:45.184693 No compression specified
85 23:18:45.185821 progress 69 % (0 MB)
86 23:18:45.186089 progress 100 % (0 MB)
87 23:18:45.186240 0 MB downloaded in 0.00 s (28.11 MB/s)
88 23:18:45.186357 end: 1.3.1 http-download (duration 00:00:00) [common]
90 23:18:45.186570 end: 1.3 download-retry (duration 00:00:00) [common]
91 23:18:45.186656 start: 1.4 download-retry (timeout 00:10:00) [common]
92 23:18:45.186737 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 23:18:45.186846 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-libcamera/20230623.0/arm64/full.rootfs.tar.xz
94 23:18:45.186911 saving as /var/lib/lava/dispatcher/tmp/12172422/tftp-deploy-gha09xov/nfsrootfs/full.rootfs.tar
95 23:18:45.186969 total size: 89451516 (85 MB)
96 23:18:45.187027 Using unxz to decompress xz
97 23:18:45.191054 progress 0 % (0 MB)
98 23:18:45.398616 progress 5 % (4 MB)
99 23:18:45.612849 progress 10 % (8 MB)
100 23:18:45.862929 progress 15 % (12 MB)
101 23:18:46.054081 progress 20 % (17 MB)
102 23:18:46.147754 progress 25 % (21 MB)
103 23:18:46.390995 progress 30 % (25 MB)
104 23:18:46.673110 progress 35 % (29 MB)
105 23:18:46.933150 progress 40 % (34 MB)
106 23:18:47.193911 progress 45 % (38 MB)
107 23:18:47.437839 progress 50 % (42 MB)
108 23:18:47.697673 progress 55 % (46 MB)
109 23:18:47.946816 progress 60 % (51 MB)
110 23:18:48.210251 progress 65 % (55 MB)
111 23:18:48.502762 progress 70 % (59 MB)
112 23:18:48.800623 progress 75 % (64 MB)
113 23:18:49.091150 progress 80 % (68 MB)
114 23:18:49.341855 progress 85 % (72 MB)
115 23:18:49.564726 progress 90 % (76 MB)
116 23:18:49.818753 progress 95 % (81 MB)
117 23:18:50.076740 progress 100 % (85 MB)
118 23:18:50.082806 85 MB downloaded in 4.90 s (17.42 MB/s)
119 23:18:50.083059 end: 1.4.1 http-download (duration 00:00:05) [common]
121 23:18:50.083324 end: 1.4 download-retry (duration 00:00:05) [common]
122 23:18:50.083416 start: 1.5 download-retry (timeout 00:09:55) [common]
123 23:18:50.083503 start: 1.5.1 http-download (timeout 00:09:55) [common]
124 23:18:50.083665 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.64-cip10-rt5/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 23:18:50.083740 saving as /var/lib/lava/dispatcher/tmp/12172422/tftp-deploy-gha09xov/modules/modules.tar
126 23:18:50.083806 total size: 8614132 (8 MB)
127 23:18:50.083871 Using unxz to decompress xz
128 23:18:50.088044 progress 0 % (0 MB)
129 23:18:50.109080 progress 5 % (0 MB)
130 23:18:50.132715 progress 10 % (0 MB)
131 23:18:50.155940 progress 15 % (1 MB)
132 23:18:50.179019 progress 20 % (1 MB)
133 23:18:50.202915 progress 25 % (2 MB)
134 23:18:50.228208 progress 30 % (2 MB)
135 23:18:50.253922 progress 35 % (2 MB)
136 23:18:50.276917 progress 40 % (3 MB)
137 23:18:50.300943 progress 45 % (3 MB)
138 23:18:50.325867 progress 50 % (4 MB)
139 23:18:50.349866 progress 55 % (4 MB)
140 23:18:50.374536 progress 60 % (4 MB)
141 23:18:50.399872 progress 65 % (5 MB)
142 23:18:50.426465 progress 70 % (5 MB)
143 23:18:50.449475 progress 75 % (6 MB)
144 23:18:50.476440 progress 80 % (6 MB)
145 23:18:50.502266 progress 85 % (7 MB)
146 23:18:50.526850 progress 90 % (7 MB)
147 23:18:50.556051 progress 95 % (7 MB)
148 23:18:50.583571 progress 100 % (8 MB)
149 23:18:50.589827 8 MB downloaded in 0.51 s (16.23 MB/s)
150 23:18:50.590087 end: 1.5.1 http-download (duration 00:00:01) [common]
152 23:18:50.590352 end: 1.5 download-retry (duration 00:00:01) [common]
153 23:18:50.590448 start: 1.6 prepare-tftp-overlay (timeout 00:09:54) [common]
154 23:18:50.590542 start: 1.6.1 extract-nfsrootfs (timeout 00:09:54) [common]
155 23:18:52.317367 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/12172422/extract-nfsrootfs-n4u2o4m3
156 23:18:52.317565 end: 1.6.1 extract-nfsrootfs (duration 00:00:02) [common]
157 23:18:52.317730 start: 1.6.2 lava-overlay (timeout 00:09:53) [common]
158 23:18:52.317888 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12172422/lava-overlay-pjr_wu0s
159 23:18:52.318019 makedir: /var/lib/lava/dispatcher/tmp/12172422/lava-overlay-pjr_wu0s/lava-12172422/bin
160 23:18:52.318120 makedir: /var/lib/lava/dispatcher/tmp/12172422/lava-overlay-pjr_wu0s/lava-12172422/tests
161 23:18:52.318219 makedir: /var/lib/lava/dispatcher/tmp/12172422/lava-overlay-pjr_wu0s/lava-12172422/results
162 23:18:52.318318 Creating /var/lib/lava/dispatcher/tmp/12172422/lava-overlay-pjr_wu0s/lava-12172422/bin/lava-add-keys
163 23:18:52.318464 Creating /var/lib/lava/dispatcher/tmp/12172422/lava-overlay-pjr_wu0s/lava-12172422/bin/lava-add-sources
164 23:18:52.318638 Creating /var/lib/lava/dispatcher/tmp/12172422/lava-overlay-pjr_wu0s/lava-12172422/bin/lava-background-process-start
165 23:18:52.318808 Creating /var/lib/lava/dispatcher/tmp/12172422/lava-overlay-pjr_wu0s/lava-12172422/bin/lava-background-process-stop
166 23:18:52.318935 Creating /var/lib/lava/dispatcher/tmp/12172422/lava-overlay-pjr_wu0s/lava-12172422/bin/lava-common-functions
167 23:18:52.319058 Creating /var/lib/lava/dispatcher/tmp/12172422/lava-overlay-pjr_wu0s/lava-12172422/bin/lava-echo-ipv4
168 23:18:52.319181 Creating /var/lib/lava/dispatcher/tmp/12172422/lava-overlay-pjr_wu0s/lava-12172422/bin/lava-install-packages
169 23:18:52.319305 Creating /var/lib/lava/dispatcher/tmp/12172422/lava-overlay-pjr_wu0s/lava-12172422/bin/lava-installed-packages
170 23:18:52.319429 Creating /var/lib/lava/dispatcher/tmp/12172422/lava-overlay-pjr_wu0s/lava-12172422/bin/lava-os-build
171 23:18:52.319552 Creating /var/lib/lava/dispatcher/tmp/12172422/lava-overlay-pjr_wu0s/lava-12172422/bin/lava-probe-channel
172 23:18:52.319676 Creating /var/lib/lava/dispatcher/tmp/12172422/lava-overlay-pjr_wu0s/lava-12172422/bin/lava-probe-ip
173 23:18:52.319799 Creating /var/lib/lava/dispatcher/tmp/12172422/lava-overlay-pjr_wu0s/lava-12172422/bin/lava-target-ip
174 23:18:52.319924 Creating /var/lib/lava/dispatcher/tmp/12172422/lava-overlay-pjr_wu0s/lava-12172422/bin/lava-target-mac
175 23:18:52.320048 Creating /var/lib/lava/dispatcher/tmp/12172422/lava-overlay-pjr_wu0s/lava-12172422/bin/lava-target-storage
176 23:18:52.320174 Creating /var/lib/lava/dispatcher/tmp/12172422/lava-overlay-pjr_wu0s/lava-12172422/bin/lava-test-case
177 23:18:52.320300 Creating /var/lib/lava/dispatcher/tmp/12172422/lava-overlay-pjr_wu0s/lava-12172422/bin/lava-test-event
178 23:18:52.320424 Creating /var/lib/lava/dispatcher/tmp/12172422/lava-overlay-pjr_wu0s/lava-12172422/bin/lava-test-feedback
179 23:18:52.320549 Creating /var/lib/lava/dispatcher/tmp/12172422/lava-overlay-pjr_wu0s/lava-12172422/bin/lava-test-raise
180 23:18:52.320672 Creating /var/lib/lava/dispatcher/tmp/12172422/lava-overlay-pjr_wu0s/lava-12172422/bin/lava-test-reference
181 23:18:52.320795 Creating /var/lib/lava/dispatcher/tmp/12172422/lava-overlay-pjr_wu0s/lava-12172422/bin/lava-test-runner
182 23:18:52.320953 Creating /var/lib/lava/dispatcher/tmp/12172422/lava-overlay-pjr_wu0s/lava-12172422/bin/lava-test-set
183 23:18:52.321075 Creating /var/lib/lava/dispatcher/tmp/12172422/lava-overlay-pjr_wu0s/lava-12172422/bin/lava-test-shell
184 23:18:52.321201 Updating /var/lib/lava/dispatcher/tmp/12172422/lava-overlay-pjr_wu0s/lava-12172422/bin/lava-install-packages (oe)
185 23:18:52.321355 Updating /var/lib/lava/dispatcher/tmp/12172422/lava-overlay-pjr_wu0s/lava-12172422/bin/lava-installed-packages (oe)
186 23:18:52.321485 Creating /var/lib/lava/dispatcher/tmp/12172422/lava-overlay-pjr_wu0s/lava-12172422/environment
187 23:18:52.321727 LAVA metadata
188 23:18:52.321806 - LAVA_JOB_ID=12172422
189 23:18:52.321869 - LAVA_DISPATCHER_IP=192.168.201.1
190 23:18:52.321969 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:53) [common]
191 23:18:52.322036 skipped lava-vland-overlay
192 23:18:52.322109 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
193 23:18:52.322187 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:53) [common]
194 23:18:52.322248 skipped lava-multinode-overlay
195 23:18:52.322319 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
196 23:18:52.322394 start: 1.6.2.3 test-definition (timeout 00:09:53) [common]
197 23:18:52.322466 Loading test definitions
198 23:18:52.322555 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:53) [common]
199 23:18:52.322624 Using /lava-12172422 at stage 0
200 23:18:52.322920 uuid=12172422_1.6.2.3.1 testdef=None
201 23:18:52.323007 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
202 23:18:52.323090 start: 1.6.2.3.2 test-overlay (timeout 00:09:53) [common]
203 23:18:52.323568 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
205 23:18:52.323786 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:53) [common]
206 23:18:52.324379 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
208 23:18:52.324602 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:53) [common]
209 23:18:52.325181 runner path: /var/lib/lava/dispatcher/tmp/12172422/lava-overlay-pjr_wu0s/lava-12172422/0/tests/0_lc-compliance test_uuid 12172422_1.6.2.3.1
210 23:18:52.325336 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
212 23:18:52.325535 Creating lava-test-runner.conf files
213 23:18:52.325625 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12172422/lava-overlay-pjr_wu0s/lava-12172422/0 for stage 0
214 23:18:52.325736 - 0_lc-compliance
215 23:18:52.325832 end: 1.6.2.3 test-definition (duration 00:00:00) [common]
216 23:18:52.325915 start: 1.6.2.4 compress-overlay (timeout 00:09:53) [common]
217 23:18:52.331602 end: 1.6.2.4 compress-overlay (duration 00:00:00) [common]
218 23:18:52.331701 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:53) [common]
219 23:18:52.331785 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
220 23:18:52.331867 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
221 23:18:52.331950 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:53) [common]
222 23:18:52.451447 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
223 23:18:52.451829 start: 1.6.4 extract-modules (timeout 00:09:52) [common]
224 23:18:52.451948 extracting modules file /var/lib/lava/dispatcher/tmp/12172422/tftp-deploy-gha09xov/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12172422/extract-nfsrootfs-n4u2o4m3
225 23:18:52.669419 extracting modules file /var/lib/lava/dispatcher/tmp/12172422/tftp-deploy-gha09xov/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12172422/extract-overlay-ramdisk-rxblx41d/ramdisk
226 23:18:52.893203 end: 1.6.4 extract-modules (duration 00:00:00) [common]
227 23:18:52.893367 start: 1.6.5 apply-overlay-tftp (timeout 00:09:52) [common]
228 23:18:52.893473 [common] Applying overlay to NFS
229 23:18:52.893547 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12172422/compress-overlay-nizai6ke/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12172422/extract-nfsrootfs-n4u2o4m3
230 23:18:52.900713 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
231 23:18:52.900822 start: 1.6.6 configure-preseed-file (timeout 00:09:52) [common]
232 23:18:52.900909 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
233 23:18:52.900993 start: 1.6.7 compress-ramdisk (timeout 00:09:52) [common]
234 23:18:52.901072 Building ramdisk /var/lib/lava/dispatcher/tmp/12172422/extract-overlay-ramdisk-rxblx41d/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12172422/extract-overlay-ramdisk-rxblx41d/ramdisk
235 23:18:53.396305 >> 119416 blocks
236 23:18:55.309520 rename /var/lib/lava/dispatcher/tmp/12172422/extract-overlay-ramdisk-rxblx41d/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12172422/tftp-deploy-gha09xov/ramdisk/ramdisk.cpio.gz
237 23:18:55.310021 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
238 23:18:55.310141 start: 1.6.8 prepare-kernel (timeout 00:09:50) [common]
239 23:18:55.310248 start: 1.6.8.1 prepare-fit (timeout 00:09:50) [common]
240 23:18:55.310362 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12172422/tftp-deploy-gha09xov/kernel/Image'
241 23:19:07.149340 Returned 0 in 11 seconds
242 23:19:07.250331 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12172422/tftp-deploy-gha09xov/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12172422/tftp-deploy-gha09xov/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12172422/tftp-deploy-gha09xov/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12172422/tftp-deploy-gha09xov/kernel/image.itb
243 23:19:07.693036 output: FIT description: Kernel Image image with one or more FDT blobs
244 23:19:07.693417 output: Created: Sun Dec 3 23:19:07 2023
245 23:19:07.693494 output: Image 0 (kernel-1)
246 23:19:07.693558 output: Description:
247 23:19:07.693669 output: Created: Sun Dec 3 23:19:07 2023
248 23:19:07.693732 output: Type: Kernel Image
249 23:19:07.693793 output: Compression: lzma compressed
250 23:19:07.693865 output: Data Size: 11049348 Bytes = 10790.38 KiB = 10.54 MiB
251 23:19:07.693924 output: Architecture: AArch64
252 23:19:07.693983 output: OS: Linux
253 23:19:07.694043 output: Load Address: 0x00000000
254 23:19:07.694101 output: Entry Point: 0x00000000
255 23:19:07.694162 output: Hash algo: crc32
256 23:19:07.694222 output: Hash value: c85ea8f0
257 23:19:07.694282 output: Image 1 (fdt-1)
258 23:19:07.694335 output: Description: mt8192-asurada-spherion-r0
259 23:19:07.694389 output: Created: Sun Dec 3 23:19:07 2023
260 23:19:07.694443 output: Type: Flat Device Tree
261 23:19:07.694496 output: Compression: uncompressed
262 23:19:07.694549 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
263 23:19:07.694602 output: Architecture: AArch64
264 23:19:07.694654 output: Hash algo: crc32
265 23:19:07.694707 output: Hash value: cc4352de
266 23:19:07.694760 output: Image 2 (ramdisk-1)
267 23:19:07.694812 output: Description: unavailable
268 23:19:07.694865 output: Created: Sun Dec 3 23:19:07 2023
269 23:19:07.694918 output: Type: RAMDisk Image
270 23:19:07.694970 output: Compression: Unknown Compression
271 23:19:07.695023 output: Data Size: 17795503 Bytes = 17378.42 KiB = 16.97 MiB
272 23:19:07.695076 output: Architecture: AArch64
273 23:19:07.695128 output: OS: Linux
274 23:19:07.695181 output: Load Address: unavailable
275 23:19:07.695233 output: Entry Point: unavailable
276 23:19:07.695285 output: Hash algo: crc32
277 23:19:07.695338 output: Hash value: fdd816f9
278 23:19:07.695390 output: Default Configuration: 'conf-1'
279 23:19:07.695442 output: Configuration 0 (conf-1)
280 23:19:07.695494 output: Description: mt8192-asurada-spherion-r0
281 23:19:07.695546 output: Kernel: kernel-1
282 23:19:07.695598 output: Init Ramdisk: ramdisk-1
283 23:19:07.695651 output: FDT: fdt-1
284 23:19:07.695703 output: Loadables: kernel-1
285 23:19:07.695755 output:
286 23:19:07.695965 end: 1.6.8.1 prepare-fit (duration 00:00:12) [common]
287 23:19:07.696065 end: 1.6.8 prepare-kernel (duration 00:00:12) [common]
288 23:19:07.696173 end: 1.6 prepare-tftp-overlay (duration 00:00:17) [common]
289 23:19:07.696265 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:37) [common]
290 23:19:07.696344 No LXC device requested
291 23:19:07.696426 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
292 23:19:07.696510 start: 1.8 deploy-device-env (timeout 00:09:37) [common]
293 23:19:07.696588 end: 1.8 deploy-device-env (duration 00:00:00) [common]
294 23:19:07.696655 Checking files for TFTP limit of 4294967296 bytes.
295 23:19:07.697164 end: 1 tftp-deploy (duration 00:00:23) [common]
296 23:19:07.697265 start: 2 depthcharge-action (timeout 00:05:00) [common]
297 23:19:07.697361 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
298 23:19:07.697489 substitutions:
299 23:19:07.697555 - {DTB}: 12172422/tftp-deploy-gha09xov/dtb/mt8192-asurada-spherion-r0.dtb
300 23:19:07.697686 - {INITRD}: 12172422/tftp-deploy-gha09xov/ramdisk/ramdisk.cpio.gz
301 23:19:07.697750 - {KERNEL}: 12172422/tftp-deploy-gha09xov/kernel/Image
302 23:19:07.697808 - {LAVA_MAC}: None
303 23:19:07.697871 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/12172422/extract-nfsrootfs-n4u2o4m3
304 23:19:07.697929 - {NFS_SERVER_IP}: 192.168.201.1
305 23:19:07.697984 - {PRESEED_CONFIG}: None
306 23:19:07.698039 - {PRESEED_LOCAL}: None
307 23:19:07.698093 - {RAMDISK}: 12172422/tftp-deploy-gha09xov/ramdisk/ramdisk.cpio.gz
308 23:19:07.698148 - {ROOT_PART}: None
309 23:19:07.698202 - {ROOT}: None
310 23:19:07.698259 - {SERVER_IP}: 192.168.201.1
311 23:19:07.698314 - {TEE}: None
312 23:19:07.698369 Parsed boot commands:
313 23:19:07.698425 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
314 23:19:07.698615 Parsed boot commands: tftpboot 192.168.201.1 12172422/tftp-deploy-gha09xov/kernel/image.itb 12172422/tftp-deploy-gha09xov/kernel/cmdline
315 23:19:07.698704 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
316 23:19:07.698790 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
317 23:19:07.698883 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
318 23:19:07.698972 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
319 23:19:07.699045 Not connected, no need to disconnect.
320 23:19:07.699118 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
321 23:19:07.699199 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
322 23:19:07.699269 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-0'
323 23:19:07.703340 Setting prompt string to ['lava-test: # ']
324 23:19:07.703708 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
325 23:19:07.703817 end: 2.2.1 reset-connection (duration 00:00:00) [common]
326 23:19:07.703938 start: 2.2.2 reset-device (timeout 00:05:00) [common]
327 23:19:07.704110 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
328 23:19:07.704318 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=reboot'
329 23:19:12.854899 >> Command sent successfully.
330 23:19:12.866631 Returned 0 in 5 seconds
331 23:19:12.967954 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
333 23:19:12.969810 end: 2.2.2 reset-device (duration 00:00:05) [common]
334 23:19:12.970425 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
335 23:19:12.970942 Setting prompt string to 'Starting depthcharge on Spherion...'
336 23:19:12.971343 Changing prompt to 'Starting depthcharge on Spherion...'
337 23:19:12.971743 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
338 23:19:12.973316 [Enter `^Ec?' for help]
339 23:19:13.145139
340 23:19:13.145750
341 23:19:13.146151 F0: 102B 0000
342 23:19:13.146526
343 23:19:13.146878 F3: 1001 0000 [0200]
344 23:19:13.147217
345 23:19:13.148947 F3: 1001 0000
346 23:19:13.149381
347 23:19:13.149787 F7: 102D 0000
348 23:19:13.150164
349 23:19:13.150506 F1: 0000 0000
350 23:19:13.152518
351 23:19:13.152993 V0: 0000 0000 [0001]
352 23:19:13.153390
353 23:19:13.153827 00: 0007 8000
354 23:19:13.154208
355 23:19:13.155950 01: 0000 0000
356 23:19:13.156439
357 23:19:13.156819 BP: 0C00 0209 [0000]
358 23:19:13.157171
359 23:19:13.159743 G0: 1182 0000
360 23:19:13.160220
361 23:19:13.160624 EC: 0000 0021 [4000]
362 23:19:13.160997
363 23:19:13.163572 S7: 0000 0000 [0000]
364 23:19:13.164004
365 23:19:13.164350 CC: 0000 0000 [0001]
366 23:19:13.164695
367 23:19:13.167085 T0: 0000 0040 [010F]
368 23:19:13.167652
369 23:19:13.168013 Jump to BL
370 23:19:13.168366
371 23:19:13.191677
372 23:19:13.192298
373 23:19:13.192720
374 23:19:13.199158 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
375 23:19:13.202957 ARM64: Exception handlers installed.
376 23:19:13.207237 ARM64: Testing exception
377 23:19:13.207724 ARM64: Done test exception
378 23:19:13.214310 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
379 23:19:13.226015 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
380 23:19:13.233101 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
381 23:19:13.242985 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
382 23:19:13.249887 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
383 23:19:13.257254 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
384 23:19:13.268509 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
385 23:19:13.275173 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
386 23:19:13.294533 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
387 23:19:13.297816 WDT: Last reset was cold boot
388 23:19:13.301230 SPI1(PAD0) initialized at 2873684 Hz
389 23:19:13.304745 SPI5(PAD0) initialized at 992727 Hz
390 23:19:13.307910 VBOOT: Loading verstage.
391 23:19:13.314794 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
392 23:19:13.318158 FMAP: Found "FLASH" version 1.1 at 0x20000.
393 23:19:13.321528 FMAP: base = 0x0 size = 0x800000 #areas = 25
394 23:19:13.324149 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
395 23:19:13.332550 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
396 23:19:13.338169 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
397 23:19:13.349444 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
398 23:19:13.350045
399 23:19:13.350429
400 23:19:13.360289 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
401 23:19:13.363528 ARM64: Exception handlers installed.
402 23:19:13.366972 ARM64: Testing exception
403 23:19:13.367547 ARM64: Done test exception
404 23:19:13.373307 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
405 23:19:13.376838 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
406 23:19:13.390956 Probing TPM: . done!
407 23:19:13.391527 TPM ready after 0 ms
408 23:19:13.398261 Connected to device vid:did:rid of 1ae0:0028:00
409 23:19:13.404445 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
410 23:19:13.464328 Initialized TPM device CR50 revision 0
411 23:19:13.476297 tlcl_send_startup: Startup return code is 0
412 23:19:13.476890 TPM: setup succeeded
413 23:19:13.487678 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
414 23:19:13.496437 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
415 23:19:13.509269 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
416 23:19:13.518717 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
417 23:19:13.521674 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
418 23:19:13.526901 in-header: 03 07 00 00 08 00 00 00
419 23:19:13.530783 in-data: aa e4 47 04 13 02 00 00
420 23:19:13.534243 Chrome EC: UHEPI supported
421 23:19:13.541722 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
422 23:19:13.545646 in-header: 03 95 00 00 08 00 00 00
423 23:19:13.546126 in-data: 18 20 20 08 00 00 00 00
424 23:19:13.546509 Phase 1
425 23:19:13.553417 FMAP: area GBB found @ 3f5000 (12032 bytes)
426 23:19:13.556406 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
427 23:19:13.564456 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
428 23:19:13.564956 Recovery requested (1009000e)
429 23:19:13.576198 TPM: Extending digest for VBOOT: boot mode into PCR 0
430 23:19:13.580670 tlcl_extend: response is 0
431 23:19:13.590918 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
432 23:19:13.595565 tlcl_extend: response is 0
433 23:19:13.603066 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
434 23:19:13.622287 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
435 23:19:13.628885 BS: bootblock times (exec / console): total (unknown) / 148 ms
436 23:19:13.629463
437 23:19:13.629886
438 23:19:13.639024 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
439 23:19:13.642292 ARM64: Exception handlers installed.
440 23:19:13.645229 ARM64: Testing exception
441 23:19:13.645856 ARM64: Done test exception
442 23:19:13.668072 pmic_efuse_setting: Set efuses in 11 msecs
443 23:19:13.671751 pmwrap_interface_init: Select PMIF_VLD_RDY
444 23:19:13.678256 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
445 23:19:13.681276 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
446 23:19:13.688343 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
447 23:19:13.692250 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
448 23:19:13.695861 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
449 23:19:13.699732 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
450 23:19:13.707152 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
451 23:19:13.710583 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
452 23:19:13.714597 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
453 23:19:13.722405 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
454 23:19:13.725873 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
455 23:19:13.729683 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
456 23:19:13.733053 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
457 23:19:13.740941 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
458 23:19:13.745013 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
459 23:19:13.752521 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
460 23:19:13.756230 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
461 23:19:13.763571 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
462 23:19:13.767325 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
463 23:19:13.775198 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
464 23:19:13.778579 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
465 23:19:13.785983 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
466 23:19:13.790277 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
467 23:19:13.797659 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
468 23:19:13.800938 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
469 23:19:13.808178 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
470 23:19:13.811982 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
471 23:19:13.815371 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
472 23:19:13.823042 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
473 23:19:13.826825 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
474 23:19:13.830040 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
475 23:19:13.837387 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
476 23:19:13.841241 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
477 23:19:13.845304 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
478 23:19:13.852446 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
479 23:19:13.856483 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
480 23:19:13.860352 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
481 23:19:13.867419 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
482 23:19:13.871405 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
483 23:19:13.874700 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
484 23:19:13.878273 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
485 23:19:13.885671 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
486 23:19:13.889323 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
487 23:19:13.893181 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
488 23:19:13.896272 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
489 23:19:13.899839 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
490 23:19:13.908092 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
491 23:19:13.911690 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
492 23:19:13.914800 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
493 23:19:13.918850 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
494 23:19:13.922562 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
495 23:19:13.929727 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
496 23:19:13.941114 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
497 23:19:13.944077 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
498 23:19:13.951561 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
499 23:19:13.959152 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
500 23:19:13.966558 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
501 23:19:13.969621 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
502 23:19:13.973128 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
503 23:19:13.981660 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x1b
504 23:19:13.984994 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
505 23:19:13.993012 [RTC]rtc_osc_init,62: osc32con val = 0xde70
506 23:19:13.996154 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
507 23:19:14.005844 [RTC]rtc_get_frequency_meter,154: input=15, output=760
508 23:19:14.014974 [RTC]rtc_get_frequency_meter,154: input=23, output=942
509 23:19:14.024386 [RTC]rtc_get_frequency_meter,154: input=19, output=848
510 23:19:14.034013 [RTC]rtc_get_frequency_meter,154: input=17, output=805
511 23:19:14.043889 [RTC]rtc_get_frequency_meter,154: input=16, output=781
512 23:19:14.053164 [RTC]rtc_get_frequency_meter,154: input=16, output=782
513 23:19:14.063298 [RTC]rtc_get_frequency_meter,154: input=17, output=803
514 23:19:14.066378 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
515 23:19:14.070575 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
516 23:19:14.073955 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
517 23:19:14.081358 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
518 23:19:14.085216 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
519 23:19:14.089056 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
520 23:19:14.092653 ADC[4]: Raw value=906203 ID=7
521 23:19:14.093223 ADC[3]: Raw value=213441 ID=1
522 23:19:14.096624 RAM Code: 0x71
523 23:19:14.100311 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
524 23:19:14.103457 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
525 23:19:14.114936 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
526 23:19:14.118864 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
527 23:19:14.121744 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
528 23:19:14.126229 in-header: 03 07 00 00 08 00 00 00
529 23:19:14.129768 in-data: aa e4 47 04 13 02 00 00
530 23:19:14.133715 Chrome EC: UHEPI supported
531 23:19:14.140957 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
532 23:19:14.144911 in-header: 03 95 00 00 08 00 00 00
533 23:19:14.148768 in-data: 18 20 20 08 00 00 00 00
534 23:19:14.149339 MRC: failed to locate region type 0.
535 23:19:14.155907 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
536 23:19:14.159499 DRAM-K: Running full calibration
537 23:19:14.167294 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
538 23:19:14.167867 header.status = 0x0
539 23:19:14.170412 header.version = 0x6 (expected: 0x6)
540 23:19:14.174488 header.size = 0xd00 (expected: 0xd00)
541 23:19:14.177641 header.flags = 0x0
542 23:19:14.180904 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
543 23:19:14.200308 read SPI 0x72590 0x1c583: 12501 us, 9287 KB/s, 74.296 Mbps
544 23:19:14.207858 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
545 23:19:14.211749 dram_init: ddr_geometry: 2
546 23:19:14.212219 [EMI] MDL number = 2
547 23:19:14.215598 [EMI] Get MDL freq = 0
548 23:19:14.216176 dram_init: ddr_type: 0
549 23:19:14.219444 is_discrete_lpddr4: 1
550 23:19:14.219920 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
551 23:19:14.223865
552 23:19:14.224459
553 23:19:14.224837 [Bian_co] ETT version 0.0.0.1
554 23:19:14.230388 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
555 23:19:14.230864
556 23:19:14.233750 dramc_set_vcore_voltage set vcore to 650000
557 23:19:14.234223 Read voltage for 800, 4
558 23:19:14.234599 Vio18 = 0
559 23:19:14.237726 Vcore = 650000
560 23:19:14.238344 Vdram = 0
561 23:19:14.238723 Vddq = 0
562 23:19:14.241881 Vmddr = 0
563 23:19:14.242430 dram_init: config_dvfs: 1
564 23:19:14.245674 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
565 23:19:14.253351 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
566 23:19:14.257210 [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9
567 23:19:14.260639 freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9
568 23:19:14.263999 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
569 23:19:14.267925 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
570 23:19:14.271118 MEM_TYPE=3, freq_sel=18
571 23:19:14.273748 sv_algorithm_assistance_LP4_1600
572 23:19:14.277836 ============ PULL DRAM RESETB DOWN ============
573 23:19:14.280866 ========== PULL DRAM RESETB DOWN end =========
574 23:19:14.288127 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
575 23:19:14.288744 ===================================
576 23:19:14.292424 LPDDR4 DRAM CONFIGURATION
577 23:19:14.296110 ===================================
578 23:19:14.296705 EX_ROW_EN[0] = 0x0
579 23:19:14.299700 EX_ROW_EN[1] = 0x0
580 23:19:14.300170 LP4Y_EN = 0x0
581 23:19:14.303702 WORK_FSP = 0x0
582 23:19:14.304266 WL = 0x2
583 23:19:14.306589 RL = 0x2
584 23:19:14.307061 BL = 0x2
585 23:19:14.310472 RPST = 0x0
586 23:19:14.310940 RD_PRE = 0x0
587 23:19:14.313971 WR_PRE = 0x1
588 23:19:14.314440 WR_PST = 0x0
589 23:19:14.317005 DBI_WR = 0x0
590 23:19:14.317473 DBI_RD = 0x0
591 23:19:14.321410 OTF = 0x1
592 23:19:14.324635 ===================================
593 23:19:14.325200 ===================================
594 23:19:14.328168 ANA top config
595 23:19:14.331733 ===================================
596 23:19:14.332204 DLL_ASYNC_EN = 0
597 23:19:14.335391 ALL_SLAVE_EN = 1
598 23:19:14.338153 NEW_RANK_MODE = 1
599 23:19:14.342150 DLL_IDLE_MODE = 1
600 23:19:14.345278 LP45_APHY_COMB_EN = 1
601 23:19:14.345809 TX_ODT_DIS = 1
602 23:19:14.349227 NEW_8X_MODE = 1
603 23:19:14.352715 ===================================
604 23:19:14.355879 ===================================
605 23:19:14.359794 data_rate = 1600
606 23:19:14.362446 CKR = 1
607 23:19:14.363059 DQ_P2S_RATIO = 8
608 23:19:14.366029 ===================================
609 23:19:14.369418 CA_P2S_RATIO = 8
610 23:19:14.373024 DQ_CA_OPEN = 0
611 23:19:14.376223 DQ_SEMI_OPEN = 0
612 23:19:14.379705 CA_SEMI_OPEN = 0
613 23:19:14.380294 CA_FULL_RATE = 0
614 23:19:14.382964 DQ_CKDIV4_EN = 1
615 23:19:14.386242 CA_CKDIV4_EN = 1
616 23:19:14.389180 CA_PREDIV_EN = 0
617 23:19:14.393252 PH8_DLY = 0
618 23:19:14.396921 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
619 23:19:14.397494 DQ_AAMCK_DIV = 4
620 23:19:14.399399 CA_AAMCK_DIV = 4
621 23:19:14.402906 CA_ADMCK_DIV = 4
622 23:19:14.405963 DQ_TRACK_CA_EN = 0
623 23:19:14.409633 CA_PICK = 800
624 23:19:14.413493 CA_MCKIO = 800
625 23:19:14.414141 MCKIO_SEMI = 0
626 23:19:14.416886 PLL_FREQ = 3068
627 23:19:14.420683 DQ_UI_PI_RATIO = 32
628 23:19:14.424852 CA_UI_PI_RATIO = 0
629 23:19:14.428369 ===================================
630 23:19:14.428962 ===================================
631 23:19:14.432870 memory_type:LPDDR4
632 23:19:14.436198 GP_NUM : 10
633 23:19:14.436765 SRAM_EN : 1
634 23:19:14.439699 MD32_EN : 0
635 23:19:14.440168 ===================================
636 23:19:14.443644 [ANA_INIT] >>>>>>>>>>>>>>
637 23:19:14.447494 <<<<<< [CONFIGURE PHASE]: ANA_TX
638 23:19:14.451462 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
639 23:19:14.454387 ===================================
640 23:19:14.457296 data_rate = 1600,PCW = 0X7600
641 23:19:14.461075 ===================================
642 23:19:14.463985 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
643 23:19:14.467995 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
644 23:19:14.474319 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
645 23:19:14.477601 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
646 23:19:14.481659 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
647 23:19:14.484519 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
648 23:19:14.487510 [ANA_INIT] flow start
649 23:19:14.491299 [ANA_INIT] PLL >>>>>>>>
650 23:19:14.492067 [ANA_INIT] PLL <<<<<<<<
651 23:19:14.494224 [ANA_INIT] MIDPI >>>>>>>>
652 23:19:14.498183 [ANA_INIT] MIDPI <<<<<<<<
653 23:19:14.498755 [ANA_INIT] DLL >>>>>>>>
654 23:19:14.501074 [ANA_INIT] flow end
655 23:19:14.504565 ============ LP4 DIFF to SE enter ============
656 23:19:14.507681 ============ LP4 DIFF to SE exit ============
657 23:19:14.511040 [ANA_INIT] <<<<<<<<<<<<<
658 23:19:14.514505 [Flow] Enable top DCM control >>>>>
659 23:19:14.517644 [Flow] Enable top DCM control <<<<<
660 23:19:14.520955 Enable DLL master slave shuffle
661 23:19:14.527611 ==============================================================
662 23:19:14.528201 Gating Mode config
663 23:19:14.534301 ==============================================================
664 23:19:14.534884 Config description:
665 23:19:14.544391 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
666 23:19:14.550887 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
667 23:19:14.557734 SELPH_MODE 0: By rank 1: By Phase
668 23:19:14.561287 ==============================================================
669 23:19:14.564479 GAT_TRACK_EN = 1
670 23:19:14.567748 RX_GATING_MODE = 2
671 23:19:14.571135 RX_GATING_TRACK_MODE = 2
672 23:19:14.574465 SELPH_MODE = 1
673 23:19:14.577638 PICG_EARLY_EN = 1
674 23:19:14.580981 VALID_LAT_VALUE = 1
675 23:19:14.587676 ==============================================================
676 23:19:14.590649 Enter into Gating configuration >>>>
677 23:19:14.594300 Exit from Gating configuration <<<<
678 23:19:14.594868 Enter into DVFS_PRE_config >>>>>
679 23:19:14.607385 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
680 23:19:14.611026 Exit from DVFS_PRE_config <<<<<
681 23:19:14.614706 Enter into PICG configuration >>>>
682 23:19:14.618375 Exit from PICG configuration <<<<
683 23:19:14.618958 [RX_INPUT] configuration >>>>>
684 23:19:14.621223 [RX_INPUT] configuration <<<<<
685 23:19:14.627645 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
686 23:19:14.631821 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
687 23:19:14.638000 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
688 23:19:14.644814 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
689 23:19:14.651325 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
690 23:19:14.657685 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
691 23:19:14.660810 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
692 23:19:14.664499 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
693 23:19:14.668070 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
694 23:19:14.675053 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
695 23:19:14.677561 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
696 23:19:14.681199 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
697 23:19:14.684627 ===================================
698 23:19:14.687717 LPDDR4 DRAM CONFIGURATION
699 23:19:14.691055 ===================================
700 23:19:14.691532 EX_ROW_EN[0] = 0x0
701 23:19:14.694790 EX_ROW_EN[1] = 0x0
702 23:19:14.698153 LP4Y_EN = 0x0
703 23:19:14.698721 WORK_FSP = 0x0
704 23:19:14.701050 WL = 0x2
705 23:19:14.701608 RL = 0x2
706 23:19:14.704651 BL = 0x2
707 23:19:14.705312 RPST = 0x0
708 23:19:14.707692 RD_PRE = 0x0
709 23:19:14.708163 WR_PRE = 0x1
710 23:19:14.711454 WR_PST = 0x0
711 23:19:14.712023 DBI_WR = 0x0
712 23:19:14.714394 DBI_RD = 0x0
713 23:19:14.715010 OTF = 0x1
714 23:19:14.717832 ===================================
715 23:19:14.720896 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
716 23:19:14.727686 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
717 23:19:14.731177 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
718 23:19:14.734151 ===================================
719 23:19:14.737412 LPDDR4 DRAM CONFIGURATION
720 23:19:14.740603 ===================================
721 23:19:14.741066 EX_ROW_EN[0] = 0x10
722 23:19:14.744294 EX_ROW_EN[1] = 0x0
723 23:19:14.744722 LP4Y_EN = 0x0
724 23:19:14.747782 WORK_FSP = 0x0
725 23:19:14.751080 WL = 0x2
726 23:19:14.751620 RL = 0x2
727 23:19:14.754407 BL = 0x2
728 23:19:14.754833 RPST = 0x0
729 23:19:14.757630 RD_PRE = 0x0
730 23:19:14.758072 WR_PRE = 0x1
731 23:19:14.761261 WR_PST = 0x0
732 23:19:14.761821 DBI_WR = 0x0
733 23:19:14.764750 DBI_RD = 0x0
734 23:19:14.765174 OTF = 0x1
735 23:19:14.768072 ===================================
736 23:19:14.774907 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
737 23:19:14.778200 nWR fixed to 40
738 23:19:14.781758 [ModeRegInit_LP4] CH0 RK0
739 23:19:14.782279 [ModeRegInit_LP4] CH0 RK1
740 23:19:14.784926 [ModeRegInit_LP4] CH1 RK0
741 23:19:14.788488 [ModeRegInit_LP4] CH1 RK1
742 23:19:14.789106 match AC timing 13
743 23:19:14.795285 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
744 23:19:14.798603 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
745 23:19:14.802191 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
746 23:19:14.808427 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
747 23:19:14.811688 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
748 23:19:14.812264 [EMI DOE] emi_dcm 0
749 23:19:14.818505 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
750 23:19:14.819169 ==
751 23:19:14.821844 Dram Type= 6, Freq= 0, CH_0, rank 0
752 23:19:14.825153 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
753 23:19:14.825770 ==
754 23:19:14.831419 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
755 23:19:14.838045 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
756 23:19:14.846028 [CA 0] Center 36 (6~67) winsize 62
757 23:19:14.849436 [CA 1] Center 36 (6~67) winsize 62
758 23:19:14.852550 [CA 2] Center 34 (4~65) winsize 62
759 23:19:14.855474 [CA 3] Center 33 (3~64) winsize 62
760 23:19:14.858783 [CA 4] Center 33 (2~64) winsize 63
761 23:19:14.862444 [CA 5] Center 32 (3~62) winsize 60
762 23:19:14.862922
763 23:19:14.865677 [CmdBusTrainingLP45] Vref(ca) range 1: 34
764 23:19:14.866156
765 23:19:14.869159 [CATrainingPosCal] consider 1 rank data
766 23:19:14.872772 u2DelayCellTimex100 = 270/100 ps
767 23:19:14.875834 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
768 23:19:14.879519 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
769 23:19:14.886060 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
770 23:19:14.888985 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
771 23:19:14.892663 CA4 delay=33 (2~64),Diff = 1 PI (7 cell)
772 23:19:14.896228 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
773 23:19:14.896799
774 23:19:14.899587 CA PerBit enable=1, Macro0, CA PI delay=32
775 23:19:14.900161
776 23:19:14.902780 [CBTSetCACLKResult] CA Dly = 32
777 23:19:14.903254 CS Dly: 4 (0~35)
778 23:19:14.903626 ==
779 23:19:14.906401 Dram Type= 6, Freq= 0, CH_0, rank 1
780 23:19:14.912490 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
781 23:19:14.913063 ==
782 23:19:14.915972 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
783 23:19:14.922261 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
784 23:19:14.932276 [CA 0] Center 36 (6~67) winsize 62
785 23:19:14.934915 [CA 1] Center 36 (6~67) winsize 62
786 23:19:14.938410 [CA 2] Center 34 (3~65) winsize 63
787 23:19:14.942016 [CA 3] Center 33 (3~64) winsize 62
788 23:19:14.945200 [CA 4] Center 32 (2~63) winsize 62
789 23:19:14.948640 [CA 5] Center 32 (2~63) winsize 62
790 23:19:14.949212
791 23:19:14.951941 [CmdBusTrainingLP45] Vref(ca) range 1: 32
792 23:19:14.952507
793 23:19:14.955540 [CATrainingPosCal] consider 2 rank data
794 23:19:14.958725 u2DelayCellTimex100 = 270/100 ps
795 23:19:14.962097 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
796 23:19:14.965057 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
797 23:19:14.972426 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
798 23:19:14.975774 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
799 23:19:14.978480 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
800 23:19:14.981945 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
801 23:19:14.982436
802 23:19:14.985386 CA PerBit enable=1, Macro0, CA PI delay=32
803 23:19:14.985908
804 23:19:14.988637 [CBTSetCACLKResult] CA Dly = 32
805 23:19:14.989144 CS Dly: 4 (0~36)
806 23:19:14.989715
807 23:19:14.992191 ----->DramcWriteLeveling(PI) begin...
808 23:19:14.992685 ==
809 23:19:14.996330 Dram Type= 6, Freq= 0, CH_0, rank 0
810 23:19:14.999487 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
811 23:19:15.003813 ==
812 23:19:15.004387 Write leveling (Byte 0): 34 => 34
813 23:19:15.007616 Write leveling (Byte 1): 31 => 31
814 23:19:15.010175 DramcWriteLeveling(PI) end<-----
815 23:19:15.010650
816 23:19:15.011024 ==
817 23:19:15.013652 Dram Type= 6, Freq= 0, CH_0, rank 0
818 23:19:15.017082 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
819 23:19:15.017558 ==
820 23:19:15.020924 [Gating] SW mode calibration
821 23:19:15.028428 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
822 23:19:15.035382 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
823 23:19:15.038150 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
824 23:19:15.041781 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
825 23:19:15.044823 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
826 23:19:15.051727 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 23:19:15.055092 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 23:19:15.058007 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
829 23:19:15.064680 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
830 23:19:15.068110 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
831 23:19:15.071545 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
832 23:19:15.078352 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
833 23:19:15.081982 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
834 23:19:15.085325 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
835 23:19:15.091310 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
836 23:19:15.095380 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
837 23:19:15.098106 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
838 23:19:15.104964 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
839 23:19:15.108281 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
840 23:19:15.111348 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
841 23:19:15.118439 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
842 23:19:15.121336 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
843 23:19:15.125157 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
844 23:19:15.131615 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
845 23:19:15.135351 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
846 23:19:15.138530 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
847 23:19:15.142204 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
848 23:19:15.148035 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
849 23:19:15.151628 0 9 8 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
850 23:19:15.154680 0 9 12 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
851 23:19:15.161752 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
852 23:19:15.165019 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
853 23:19:15.168109 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
854 23:19:15.175152 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
855 23:19:15.178555 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
856 23:19:15.181423 0 10 4 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
857 23:19:15.188521 0 10 8 | B1->B0 | 3232 2323 | 0 0 | (0 1) (0 0)
858 23:19:15.191888 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
859 23:19:15.194883 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 23:19:15.201982 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 23:19:15.205269 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 23:19:15.208741 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 23:19:15.212203 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 23:19:15.218588 0 11 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
865 23:19:15.221827 0 11 8 | B1->B0 | 2d2d 3f3f | 0 0 | (0 0) (1 1)
866 23:19:15.225397 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
867 23:19:15.231994 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
868 23:19:15.235486 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
869 23:19:15.238367 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
870 23:19:15.245327 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
871 23:19:15.248411 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
872 23:19:15.252138 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
873 23:19:15.258309 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
874 23:19:15.261735 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
875 23:19:15.265337 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
876 23:19:15.271769 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
877 23:19:15.275231 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
878 23:19:15.278044 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
879 23:19:15.285107 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
880 23:19:15.288232 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
881 23:19:15.291435 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
882 23:19:15.298867 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
883 23:19:15.301395 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
884 23:19:15.305302 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
885 23:19:15.311653 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
886 23:19:15.314628 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
887 23:19:15.318365 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
888 23:19:15.321959 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
889 23:19:15.328115 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
890 23:19:15.331799 Total UI for P1: 0, mck2ui 16
891 23:19:15.335513 best dqsien dly found for B0: ( 0, 14, 6)
892 23:19:15.338606 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
893 23:19:15.342146 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
894 23:19:15.345104 Total UI for P1: 0, mck2ui 16
895 23:19:15.348931 best dqsien dly found for B1: ( 0, 14, 12)
896 23:19:15.352564 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
897 23:19:15.356037 best DQS1 dly(MCK, UI, PI) = (0, 14, 12)
898 23:19:15.356610
899 23:19:15.359127 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
900 23:19:15.365631 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 12)
901 23:19:15.366152 [Gating] SW calibration Done
902 23:19:15.366525 ==
903 23:19:15.369381 Dram Type= 6, Freq= 0, CH_0, rank 0
904 23:19:15.375935 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
905 23:19:15.376491 ==
906 23:19:15.376867 RX Vref Scan: 0
907 23:19:15.377216
908 23:19:15.379178 RX Vref 0 -> 0, step: 1
909 23:19:15.379739
910 23:19:15.382548 RX Delay -130 -> 252, step: 16
911 23:19:15.386045 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
912 23:19:15.389429 iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224
913 23:19:15.392440 iDelay=206, Bit 2, Center 93 (-18 ~ 205) 224
914 23:19:15.395570 iDelay=206, Bit 3, Center 93 (-18 ~ 205) 224
915 23:19:15.402288 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
916 23:19:15.405980 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
917 23:19:15.409054 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
918 23:19:15.412476 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
919 23:19:15.416202 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
920 23:19:15.422649 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
921 23:19:15.426072 iDelay=206, Bit 10, Center 85 (-18 ~ 189) 208
922 23:19:15.429683 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
923 23:19:15.433075 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
924 23:19:15.436460 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
925 23:19:15.443188 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
926 23:19:15.446208 iDelay=206, Bit 15, Center 93 (-18 ~ 205) 224
927 23:19:15.446801 ==
928 23:19:15.449303 Dram Type= 6, Freq= 0, CH_0, rank 0
929 23:19:15.452893 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
930 23:19:15.453463 ==
931 23:19:15.455968 DQS Delay:
932 23:19:15.456435 DQS0 = 0, DQS1 = 0
933 23:19:15.456802 DQM Delay:
934 23:19:15.459235 DQM0 = 91, DQM1 = 83
935 23:19:15.459709 DQ Delay:
936 23:19:15.462874 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =93
937 23:19:15.466078 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93
938 23:19:15.469768 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
939 23:19:15.472687 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
940 23:19:15.473157
941 23:19:15.473525
942 23:19:15.473936 ==
943 23:19:15.476371 Dram Type= 6, Freq= 0, CH_0, rank 0
944 23:19:15.482833 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
945 23:19:15.483406 ==
946 23:19:15.483780
947 23:19:15.484117
948 23:19:15.484440 TX Vref Scan disable
949 23:19:15.486148 == TX Byte 0 ==
950 23:19:15.489709 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
951 23:19:15.496157 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
952 23:19:15.496730 == TX Byte 1 ==
953 23:19:15.499554 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
954 23:19:15.506592 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
955 23:19:15.507164 ==
956 23:19:15.509733 Dram Type= 6, Freq= 0, CH_0, rank 0
957 23:19:15.512723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
958 23:19:15.513301 ==
959 23:19:15.525522 TX Vref=22, minBit 8, minWin=27, winSum=446
960 23:19:15.528669 TX Vref=24, minBit 9, minWin=27, winSum=450
961 23:19:15.532211 TX Vref=26, minBit 4, minWin=28, winSum=455
962 23:19:15.535731 TX Vref=28, minBit 8, minWin=28, winSum=458
963 23:19:15.539209 TX Vref=30, minBit 5, minWin=28, winSum=458
964 23:19:15.542255 TX Vref=32, minBit 5, minWin=28, winSum=457
965 23:19:15.549067 [TxChooseVref] Worse bit 8, Min win 28, Win sum 458, Final Vref 28
966 23:19:15.549550
967 23:19:15.552606 Final TX Range 1 Vref 28
968 23:19:15.553190
969 23:19:15.553564 ==
970 23:19:15.555697 Dram Type= 6, Freq= 0, CH_0, rank 0
971 23:19:15.558717 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
972 23:19:15.559190 ==
973 23:19:15.559561
974 23:19:15.559903
975 23:19:15.561929 TX Vref Scan disable
976 23:19:15.565550 == TX Byte 0 ==
977 23:19:15.569008 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
978 23:19:15.572206 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
979 23:19:15.575971 == TX Byte 1 ==
980 23:19:15.578501 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
981 23:19:15.582482 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
982 23:19:15.583050
983 23:19:15.585785 [DATLAT]
984 23:19:15.586351 Freq=800, CH0 RK0
985 23:19:15.586729
986 23:19:15.588904 DATLAT Default: 0xa
987 23:19:15.589367 0, 0xFFFF, sum = 0
988 23:19:15.592226 1, 0xFFFF, sum = 0
989 23:19:15.592702 2, 0xFFFF, sum = 0
990 23:19:15.595687 3, 0xFFFF, sum = 0
991 23:19:15.596262 4, 0xFFFF, sum = 0
992 23:19:15.599394 5, 0xFFFF, sum = 0
993 23:19:15.599968 6, 0xFFFF, sum = 0
994 23:19:15.602331 7, 0xFFFF, sum = 0
995 23:19:15.602803 8, 0xFFFF, sum = 0
996 23:19:15.606272 9, 0x0, sum = 1
997 23:19:15.606843 10, 0x0, sum = 2
998 23:19:15.608900 11, 0x0, sum = 3
999 23:19:15.609476 12, 0x0, sum = 4
1000 23:19:15.612028 best_step = 10
1001 23:19:15.612494
1002 23:19:15.612860 ==
1003 23:19:15.615420 Dram Type= 6, Freq= 0, CH_0, rank 0
1004 23:19:15.618843 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1005 23:19:15.619415 ==
1006 23:19:15.621703 RX Vref Scan: 1
1007 23:19:15.622171
1008 23:19:15.622541 Set Vref Range= 32 -> 127
1009 23:19:15.622890
1010 23:19:15.625376 RX Vref 32 -> 127, step: 1
1011 23:19:15.625996
1012 23:19:15.628799 RX Delay -95 -> 252, step: 8
1013 23:19:15.629368
1014 23:19:15.632319 Set Vref, RX VrefLevel [Byte0]: 32
1015 23:19:15.635319 [Byte1]: 32
1016 23:19:15.635791
1017 23:19:15.638959 Set Vref, RX VrefLevel [Byte0]: 33
1018 23:19:15.641983 [Byte1]: 33
1019 23:19:15.645914
1020 23:19:15.646379 Set Vref, RX VrefLevel [Byte0]: 34
1021 23:19:15.649042 [Byte1]: 34
1022 23:19:15.653259
1023 23:19:15.653874 Set Vref, RX VrefLevel [Byte0]: 35
1024 23:19:15.657043 [Byte1]: 35
1025 23:19:15.660939
1026 23:19:15.661423 Set Vref, RX VrefLevel [Byte0]: 36
1027 23:19:15.664883 [Byte1]: 36
1028 23:19:15.668678
1029 23:19:15.669138 Set Vref, RX VrefLevel [Byte0]: 37
1030 23:19:15.672353 [Byte1]: 37
1031 23:19:15.676525
1032 23:19:15.677078 Set Vref, RX VrefLevel [Byte0]: 38
1033 23:19:15.679941 [Byte1]: 38
1034 23:19:15.683861
1035 23:19:15.684332 Set Vref, RX VrefLevel [Byte0]: 39
1036 23:19:15.687965 [Byte1]: 39
1037 23:19:15.691559
1038 23:19:15.692115 Set Vref, RX VrefLevel [Byte0]: 40
1039 23:19:15.694597 [Byte1]: 40
1040 23:19:15.698764
1041 23:19:15.699318 Set Vref, RX VrefLevel [Byte0]: 41
1042 23:19:15.702069 [Byte1]: 41
1043 23:19:15.706781
1044 23:19:15.707340 Set Vref, RX VrefLevel [Byte0]: 42
1045 23:19:15.710206 [Byte1]: 42
1046 23:19:15.714017
1047 23:19:15.714573 Set Vref, RX VrefLevel [Byte0]: 43
1048 23:19:15.717489 [Byte1]: 43
1049 23:19:15.721761
1050 23:19:15.722312 Set Vref, RX VrefLevel [Byte0]: 44
1051 23:19:15.725095 [Byte1]: 44
1052 23:19:15.729632
1053 23:19:15.730200 Set Vref, RX VrefLevel [Byte0]: 45
1054 23:19:15.732884 [Byte1]: 45
1055 23:19:15.736988
1056 23:19:15.737536 Set Vref, RX VrefLevel [Byte0]: 46
1057 23:19:15.740300 [Byte1]: 46
1058 23:19:15.744966
1059 23:19:15.745526 Set Vref, RX VrefLevel [Byte0]: 47
1060 23:19:15.750991 [Byte1]: 47
1061 23:19:15.751454
1062 23:19:15.754142 Set Vref, RX VrefLevel [Byte0]: 48
1063 23:19:15.757372 [Byte1]: 48
1064 23:19:15.757885
1065 23:19:15.761028 Set Vref, RX VrefLevel [Byte0]: 49
1066 23:19:15.764263 [Byte1]: 49
1067 23:19:15.764968
1068 23:19:15.767685 Set Vref, RX VrefLevel [Byte0]: 50
1069 23:19:15.770597 [Byte1]: 50
1070 23:19:15.774761
1071 23:19:15.775217 Set Vref, RX VrefLevel [Byte0]: 51
1072 23:19:15.778189 [Byte1]: 51
1073 23:19:15.782634
1074 23:19:15.783045 Set Vref, RX VrefLevel [Byte0]: 52
1075 23:19:15.785461 [Byte1]: 52
1076 23:19:15.789936
1077 23:19:15.790458 Set Vref, RX VrefLevel [Byte0]: 53
1078 23:19:15.792956 [Byte1]: 53
1079 23:19:15.797988
1080 23:19:15.798500 Set Vref, RX VrefLevel [Byte0]: 54
1081 23:19:15.800791 [Byte1]: 54
1082 23:19:15.805404
1083 23:19:15.805988 Set Vref, RX VrefLevel [Byte0]: 55
1084 23:19:15.808896 [Byte1]: 55
1085 23:19:15.813265
1086 23:19:15.813823 Set Vref, RX VrefLevel [Byte0]: 56
1087 23:19:15.816126 [Byte1]: 56
1088 23:19:15.820802
1089 23:19:15.821324 Set Vref, RX VrefLevel [Byte0]: 57
1090 23:19:15.824036 [Byte1]: 57
1091 23:19:15.827823
1092 23:19:15.828239 Set Vref, RX VrefLevel [Byte0]: 58
1093 23:19:15.831359 [Byte1]: 58
1094 23:19:15.835428
1095 23:19:15.835953 Set Vref, RX VrefLevel [Byte0]: 59
1096 23:19:15.838781 [Byte1]: 59
1097 23:19:15.843365
1098 23:19:15.843883 Set Vref, RX VrefLevel [Byte0]: 60
1099 23:19:15.846360 [Byte1]: 60
1100 23:19:15.850677
1101 23:19:15.851091 Set Vref, RX VrefLevel [Byte0]: 61
1102 23:19:15.854263 [Byte1]: 61
1103 23:19:15.857995
1104 23:19:15.858410 Set Vref, RX VrefLevel [Byte0]: 62
1105 23:19:15.861720 [Byte1]: 62
1106 23:19:15.866231
1107 23:19:15.866669 Set Vref, RX VrefLevel [Byte0]: 63
1108 23:19:15.868887 [Byte1]: 63
1109 23:19:15.874148
1110 23:19:15.874662 Set Vref, RX VrefLevel [Byte0]: 64
1111 23:19:15.876771 [Byte1]: 64
1112 23:19:15.881372
1113 23:19:15.881954 Set Vref, RX VrefLevel [Byte0]: 65
1114 23:19:15.884592 [Byte1]: 65
1115 23:19:15.889097
1116 23:19:15.889650 Set Vref, RX VrefLevel [Byte0]: 66
1117 23:19:15.892264 [Byte1]: 66
1118 23:19:15.896471
1119 23:19:15.896988 Set Vref, RX VrefLevel [Byte0]: 67
1120 23:19:15.899979 [Byte1]: 67
1121 23:19:15.903975
1122 23:19:15.904435 Set Vref, RX VrefLevel [Byte0]: 68
1123 23:19:15.907651 [Byte1]: 68
1124 23:19:15.911539
1125 23:19:15.912000 Set Vref, RX VrefLevel [Byte0]: 69
1126 23:19:15.915281 [Byte1]: 69
1127 23:19:15.919387
1128 23:19:15.919942 Set Vref, RX VrefLevel [Byte0]: 70
1129 23:19:15.922637 [Byte1]: 70
1130 23:19:15.926692
1131 23:19:15.927243 Set Vref, RX VrefLevel [Byte0]: 71
1132 23:19:15.930188 [Byte1]: 71
1133 23:19:15.934690
1134 23:19:15.935246 Set Vref, RX VrefLevel [Byte0]: 72
1135 23:19:15.938185 [Byte1]: 72
1136 23:19:15.942181
1137 23:19:15.942755 Set Vref, RX VrefLevel [Byte0]: 73
1138 23:19:15.945327 [Byte1]: 73
1139 23:19:15.949818
1140 23:19:15.950389 Set Vref, RX VrefLevel [Byte0]: 74
1141 23:19:15.952835 [Byte1]: 74
1142 23:19:15.957566
1143 23:19:15.958199 Set Vref, RX VrefLevel [Byte0]: 75
1144 23:19:15.960527 [Byte1]: 75
1145 23:19:15.964822
1146 23:19:15.965280 Set Vref, RX VrefLevel [Byte0]: 76
1147 23:19:15.967839 [Byte1]: 76
1148 23:19:15.972575
1149 23:19:15.973127 Set Vref, RX VrefLevel [Byte0]: 77
1150 23:19:15.976000 [Byte1]: 77
1151 23:19:15.980247
1152 23:19:15.980800 Final RX Vref Byte 0 = 58 to rank0
1153 23:19:15.983163 Final RX Vref Byte 1 = 56 to rank0
1154 23:19:15.986434 Final RX Vref Byte 0 = 58 to rank1
1155 23:19:15.989892 Final RX Vref Byte 1 = 56 to rank1==
1156 23:19:15.993032 Dram Type= 6, Freq= 0, CH_0, rank 0
1157 23:19:16.000554 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1158 23:19:16.001112 ==
1159 23:19:16.001484 DQS Delay:
1160 23:19:16.001878 DQS0 = 0, DQS1 = 0
1161 23:19:16.003403 DQM Delay:
1162 23:19:16.003861 DQM0 = 92, DQM1 = 84
1163 23:19:16.007252 DQ Delay:
1164 23:19:16.009913 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1165 23:19:16.010371 DQ4 =96, DQ5 =80, DQ6 =96, DQ7 =100
1166 23:19:16.013932 DQ8 =72, DQ9 =76, DQ10 =84, DQ11 =76
1167 23:19:16.016710 DQ12 =92, DQ13 =92, DQ14 =92, DQ15 =92
1168 23:19:16.020120
1169 23:19:16.020677
1170 23:19:16.026963 [DQSOSCAuto] RK0, (LSB)MR18= 0x4c42, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 390 ps
1171 23:19:16.030619 CH0 RK0: MR19=606, MR18=4C42
1172 23:19:16.036780 CH0_RK0: MR19=0x606, MR18=0x4C42, DQSOSC=390, MR23=63, INC=97, DEC=64
1173 23:19:16.037342
1174 23:19:16.040282 ----->DramcWriteLeveling(PI) begin...
1175 23:19:16.040852 ==
1176 23:19:16.043492 Dram Type= 6, Freq= 0, CH_0, rank 1
1177 23:19:16.046757 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1178 23:19:16.047336 ==
1179 23:19:16.050357 Write leveling (Byte 0): 33 => 33
1180 23:19:16.053172 Write leveling (Byte 1): 30 => 30
1181 23:19:16.057132 DramcWriteLeveling(PI) end<-----
1182 23:19:16.057732
1183 23:19:16.058105 ==
1184 23:19:16.060619 Dram Type= 6, Freq= 0, CH_0, rank 1
1185 23:19:16.063675 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1186 23:19:16.064145 ==
1187 23:19:16.108198 [Gating] SW mode calibration
1188 23:19:16.109026 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1189 23:19:16.109923 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1190 23:19:16.110311 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1191 23:19:16.110655 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1192 23:19:16.110983 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1193 23:19:16.111298 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 23:19:16.111611 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 23:19:16.111919 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1196 23:19:16.152183 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1197 23:19:16.152837 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1198 23:19:16.153219 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1199 23:19:16.153564 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1200 23:19:16.154307 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1201 23:19:16.154663 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1202 23:19:16.154991 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1203 23:19:16.155306 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1204 23:19:16.155616 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1205 23:19:16.155922 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1206 23:19:16.195991 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1207 23:19:16.196578 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1208 23:19:16.197306 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 1)
1209 23:19:16.197706 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1210 23:19:16.198115 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1211 23:19:16.198457 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1212 23:19:16.198781 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1213 23:19:16.199153 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1214 23:19:16.199476 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1215 23:19:16.199786 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1216 23:19:16.209115 0 9 8 | B1->B0 | 2e2e 2d2c | 1 1 | (0 0) (0 0)
1217 23:19:16.209727 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1218 23:19:16.210106 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1219 23:19:16.212052 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1220 23:19:16.215992 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1221 23:19:16.219129 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1222 23:19:16.222594 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1223 23:19:16.229005 0 10 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
1224 23:19:16.232734 0 10 8 | B1->B0 | 2929 2525 | 0 1 | (0 0) (1 1)
1225 23:19:16.235801 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 23:19:16.243607 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 23:19:16.247488 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 23:19:16.251123 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 23:19:16.254413 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 23:19:16.257804 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 23:19:16.264683 0 11 4 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
1232 23:19:16.269087 0 11 8 | B1->B0 | 3a3a 3d3d | 1 0 | (0 0) (0 0)
1233 23:19:16.272176 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1234 23:19:16.275935 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1235 23:19:16.282048 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1236 23:19:16.285200 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1237 23:19:16.288696 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1238 23:19:16.295178 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1239 23:19:16.298827 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1240 23:19:16.302632 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1241 23:19:16.309106 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1242 23:19:16.312179 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1243 23:19:16.315758 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1244 23:19:16.322662 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1245 23:19:16.325765 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1246 23:19:16.328787 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1247 23:19:16.331994 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1248 23:19:16.338980 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1249 23:19:16.342407 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1250 23:19:16.346076 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1251 23:19:16.352767 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1252 23:19:16.356316 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1253 23:19:16.358837 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1254 23:19:16.366127 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1255 23:19:16.369078 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1256 23:19:16.372733 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1257 23:19:16.378916 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1258 23:19:16.379375 Total UI for P1: 0, mck2ui 16
1259 23:19:16.386093 best dqsien dly found for B0: ( 0, 14, 10)
1260 23:19:16.386552 Total UI for P1: 0, mck2ui 16
1261 23:19:16.389229 best dqsien dly found for B1: ( 0, 14, 10)
1262 23:19:16.396134 best DQS0 dly(MCK, UI, PI) = (0, 14, 10)
1263 23:19:16.399494 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1264 23:19:16.400052
1265 23:19:16.402919 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 10)
1266 23:19:16.405570 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1267 23:19:16.409663 [Gating] SW calibration Done
1268 23:19:16.410225 ==
1269 23:19:16.412823 Dram Type= 6, Freq= 0, CH_0, rank 1
1270 23:19:16.416423 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1271 23:19:16.416988 ==
1272 23:19:16.419311 RX Vref Scan: 0
1273 23:19:16.419869
1274 23:19:16.420240 RX Vref 0 -> 0, step: 1
1275 23:19:16.420589
1276 23:19:16.422379 RX Delay -130 -> 252, step: 16
1277 23:19:16.426568 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1278 23:19:16.432557 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1279 23:19:16.436201 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1280 23:19:16.439661 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1281 23:19:16.442605 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1282 23:19:16.445982 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1283 23:19:16.449935 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1284 23:19:16.456039 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1285 23:19:16.459449 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1286 23:19:16.462394 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1287 23:19:16.466022 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1288 23:19:16.469445 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1289 23:19:16.476059 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1290 23:19:16.479737 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1291 23:19:16.482876 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1292 23:19:16.485914 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1293 23:19:16.486508 ==
1294 23:19:16.489101 Dram Type= 6, Freq= 0, CH_0, rank 1
1295 23:19:16.495935 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1296 23:19:16.496398 ==
1297 23:19:16.496765 DQS Delay:
1298 23:19:16.499424 DQS0 = 0, DQS1 = 0
1299 23:19:16.499976 DQM Delay:
1300 23:19:16.500341 DQM0 = 90, DQM1 = 83
1301 23:19:16.502934 DQ Delay:
1302 23:19:16.506127 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
1303 23:19:16.509855 DQ4 =93, DQ5 =85, DQ6 =93, DQ7 =101
1304 23:19:16.512899 DQ8 =77, DQ9 =77, DQ10 =77, DQ11 =77
1305 23:19:16.516338 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =93
1306 23:19:16.516903
1307 23:19:16.517270
1308 23:19:16.517652 ==
1309 23:19:16.519296 Dram Type= 6, Freq= 0, CH_0, rank 1
1310 23:19:16.523191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1311 23:19:16.523729 ==
1312 23:19:16.524116
1313 23:19:16.524459
1314 23:19:16.526426 TX Vref Scan disable
1315 23:19:16.526925 == TX Byte 0 ==
1316 23:19:16.533274 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1317 23:19:16.536922 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1318 23:19:16.537473 == TX Byte 1 ==
1319 23:19:16.543151 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1320 23:19:16.546363 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1321 23:19:16.546967 ==
1322 23:19:16.550035 Dram Type= 6, Freq= 0, CH_0, rank 1
1323 23:19:16.552614 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1324 23:19:16.553076 ==
1325 23:19:16.566871 TX Vref=22, minBit 8, minWin=27, winSum=449
1326 23:19:16.570885 TX Vref=24, minBit 1, minWin=28, winSum=452
1327 23:19:16.574313 TX Vref=26, minBit 1, minWin=28, winSum=457
1328 23:19:16.577456 TX Vref=28, minBit 4, minWin=28, winSum=458
1329 23:19:16.580470 TX Vref=30, minBit 10, minWin=27, winSum=454
1330 23:19:16.586943 TX Vref=32, minBit 10, minWin=27, winSum=451
1331 23:19:16.590372 [TxChooseVref] Worse bit 4, Min win 28, Win sum 458, Final Vref 28
1332 23:19:16.590831
1333 23:19:16.593858 Final TX Range 1 Vref 28
1334 23:19:16.594311
1335 23:19:16.594643 ==
1336 23:19:16.596852 Dram Type= 6, Freq= 0, CH_0, rank 1
1337 23:19:16.600101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1338 23:19:16.600515 ==
1339 23:19:16.603556
1340 23:19:16.603995
1341 23:19:16.604320 TX Vref Scan disable
1342 23:19:16.606843 == TX Byte 0 ==
1343 23:19:16.610680 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1344 23:19:16.614557 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1345 23:19:16.617169 == TX Byte 1 ==
1346 23:19:16.620878 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1347 23:19:16.624372 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1348 23:19:16.627593
1349 23:19:16.628130 [DATLAT]
1350 23:19:16.628496 Freq=800, CH0 RK1
1351 23:19:16.628847
1352 23:19:16.630816 DATLAT Default: 0xa
1353 23:19:16.631367 0, 0xFFFF, sum = 0
1354 23:19:16.634059 1, 0xFFFF, sum = 0
1355 23:19:16.634579 2, 0xFFFF, sum = 0
1356 23:19:16.638040 3, 0xFFFF, sum = 0
1357 23:19:16.638562 4, 0xFFFF, sum = 0
1358 23:19:16.641256 5, 0xFFFF, sum = 0
1359 23:19:16.641728 6, 0xFFFF, sum = 0
1360 23:19:16.643859 7, 0xFFFF, sum = 0
1361 23:19:16.644275 8, 0xFFFF, sum = 0
1362 23:19:16.647888 9, 0x0, sum = 1
1363 23:19:16.648415 10, 0x0, sum = 2
1364 23:19:16.650636 11, 0x0, sum = 3
1365 23:19:16.651054 12, 0x0, sum = 4
1366 23:19:16.654415 best_step = 10
1367 23:19:16.654825
1368 23:19:16.655175 ==
1369 23:19:16.657256 Dram Type= 6, Freq= 0, CH_0, rank 1
1370 23:19:16.660693 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1371 23:19:16.661145 ==
1372 23:19:16.664187 RX Vref Scan: 0
1373 23:19:16.664698
1374 23:19:16.665035 RX Vref 0 -> 0, step: 1
1375 23:19:16.665342
1376 23:19:16.667193 RX Delay -79 -> 252, step: 8
1377 23:19:16.674024 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1378 23:19:16.677056 iDelay=209, Bit 1, Center 96 (-7 ~ 200) 208
1379 23:19:16.680929 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1380 23:19:16.684231 iDelay=209, Bit 3, Center 88 (-23 ~ 200) 224
1381 23:19:16.687752 iDelay=209, Bit 4, Center 96 (-15 ~ 208) 224
1382 23:19:16.691234 iDelay=209, Bit 5, Center 84 (-23 ~ 192) 216
1383 23:19:16.697972 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1384 23:19:16.701302 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1385 23:19:16.704637 iDelay=209, Bit 8, Center 72 (-39 ~ 184) 224
1386 23:19:16.708190 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1387 23:19:16.711117 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1388 23:19:16.718046 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1389 23:19:16.721423 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1390 23:19:16.724409 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
1391 23:19:16.727729 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1392 23:19:16.734329 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1393 23:19:16.734744 ==
1394 23:19:16.737487 Dram Type= 6, Freq= 0, CH_0, rank 1
1395 23:19:16.740645 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1396 23:19:16.741207 ==
1397 23:19:16.741739 DQS Delay:
1398 23:19:16.744307 DQS0 = 0, DQS1 = 0
1399 23:19:16.744715 DQM Delay:
1400 23:19:16.748000 DQM0 = 92, DQM1 = 81
1401 23:19:16.748512 DQ Delay:
1402 23:19:16.751020 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88
1403 23:19:16.754346 DQ4 =96, DQ5 =84, DQ6 =100, DQ7 =100
1404 23:19:16.757624 DQ8 =72, DQ9 =68, DQ10 =84, DQ11 =76
1405 23:19:16.761454 DQ12 =84, DQ13 =88, DQ14 =92, DQ15 =88
1406 23:19:16.762015
1407 23:19:16.762346
1408 23:19:16.767391 [DQSOSCAuto] RK1, (LSB)MR18= 0x4314, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 393 ps
1409 23:19:16.770809 CH0 RK1: MR19=606, MR18=4314
1410 23:19:16.777716 CH0_RK1: MR19=0x606, MR18=0x4314, DQSOSC=393, MR23=63, INC=95, DEC=63
1411 23:19:16.780584 [RxdqsGatingPostProcess] freq 800
1412 23:19:16.787605 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1413 23:19:16.788197 Pre-setting of DQS Precalculation
1414 23:19:16.794248 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1415 23:19:16.794721 ==
1416 23:19:16.797178 Dram Type= 6, Freq= 0, CH_1, rank 0
1417 23:19:16.800406 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1418 23:19:16.800820 ==
1419 23:19:16.807057 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1420 23:19:16.813983 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1421 23:19:16.822609 [CA 0] Center 36 (6~67) winsize 62
1422 23:19:16.825752 [CA 1] Center 36 (6~67) winsize 62
1423 23:19:16.829036 [CA 2] Center 34 (4~65) winsize 62
1424 23:19:16.832238 [CA 3] Center 34 (4~65) winsize 62
1425 23:19:16.835984 [CA 4] Center 35 (5~65) winsize 61
1426 23:19:16.839171 [CA 5] Center 34 (4~64) winsize 61
1427 23:19:16.839860
1428 23:19:16.842383 [CmdBusTrainingLP45] Vref(ca) range 1: 30
1429 23:19:16.842844
1430 23:19:16.846024 [CATrainingPosCal] consider 1 rank data
1431 23:19:16.848962 u2DelayCellTimex100 = 270/100 ps
1432 23:19:16.852540 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1433 23:19:16.856094 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1434 23:19:16.861916 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1435 23:19:16.865497 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1436 23:19:16.868503 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1437 23:19:16.872535 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1438 23:19:16.873177
1439 23:19:16.875832 CA PerBit enable=1, Macro0, CA PI delay=34
1440 23:19:16.876294
1441 23:19:16.879239 [CBTSetCACLKResult] CA Dly = 34
1442 23:19:16.879803 CS Dly: 5 (0~36)
1443 23:19:16.880174 ==
1444 23:19:16.882094 Dram Type= 6, Freq= 0, CH_1, rank 1
1445 23:19:16.889102 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1446 23:19:16.889567 ==
1447 23:19:16.892618 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1448 23:19:16.898830 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1449 23:19:16.909030 [CA 0] Center 36 (6~67) winsize 62
1450 23:19:16.912763 [CA 1] Center 36 (6~67) winsize 62
1451 23:19:16.916632 [CA 2] Center 35 (4~66) winsize 63
1452 23:19:16.920271 [CA 3] Center 34 (4~65) winsize 62
1453 23:19:16.923717 [CA 4] Center 35 (4~66) winsize 63
1454 23:19:16.924185 [CA 5] Center 34 (4~65) winsize 62
1455 23:19:16.924560
1456 23:19:16.927934 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1457 23:19:16.928509
1458 23:19:16.931834 [CATrainingPosCal] consider 2 rank data
1459 23:19:16.935228 u2DelayCellTimex100 = 270/100 ps
1460 23:19:16.938848 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1461 23:19:16.942037 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1462 23:19:16.945426 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1463 23:19:16.951909 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1464 23:19:16.955388 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1465 23:19:16.958801 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1466 23:19:16.959264
1467 23:19:16.962604 CA PerBit enable=1, Macro0, CA PI delay=34
1468 23:19:16.963164
1469 23:19:16.965046 [CBTSetCACLKResult] CA Dly = 34
1470 23:19:16.965508 CS Dly: 6 (0~38)
1471 23:19:16.966007
1472 23:19:16.968633 ----->DramcWriteLeveling(PI) begin...
1473 23:19:16.969105 ==
1474 23:19:16.972554 Dram Type= 6, Freq= 0, CH_1, rank 0
1475 23:19:16.978338 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1476 23:19:16.978805 ==
1477 23:19:16.982219 Write leveling (Byte 0): 27 => 27
1478 23:19:16.985252 Write leveling (Byte 1): 28 => 28
1479 23:19:16.985858 DramcWriteLeveling(PI) end<-----
1480 23:19:16.986235
1481 23:19:16.988842 ==
1482 23:19:16.992403 Dram Type= 6, Freq= 0, CH_1, rank 0
1483 23:19:16.995668 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1484 23:19:16.996134 ==
1485 23:19:16.998888 [Gating] SW mode calibration
1486 23:19:17.005822 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1487 23:19:17.008537 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1488 23:19:17.015439 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1489 23:19:17.018568 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1490 23:19:17.022538 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 23:19:17.028705 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 23:19:17.032201 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 23:19:17.035447 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1494 23:19:17.041789 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1495 23:19:17.045153 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1496 23:19:17.048615 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1497 23:19:17.055939 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1498 23:19:17.058248 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1499 23:19:17.061924 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1500 23:19:17.068919 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1501 23:19:17.072123 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1502 23:19:17.074980 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1503 23:19:17.078770 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1504 23:19:17.085130 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1505 23:19:17.088732 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1506 23:19:17.091771 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1507 23:19:17.098142 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1508 23:19:17.101832 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1509 23:19:17.105416 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1510 23:19:17.112161 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1511 23:19:17.115138 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1512 23:19:17.118808 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1513 23:19:17.125603 0 9 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 1)
1514 23:19:17.128542 0 9 8 | B1->B0 | 3030 3232 | 1 1 | (1 1) (1 1)
1515 23:19:17.132362 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1516 23:19:17.138547 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1517 23:19:17.142625 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1518 23:19:17.145218 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1519 23:19:17.152132 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1520 23:19:17.155910 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
1521 23:19:17.158574 0 10 4 | B1->B0 | 3232 2d2d | 0 0 | (1 1) (1 0)
1522 23:19:17.162443 0 10 8 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
1523 23:19:17.168799 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 23:19:17.172281 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 23:19:17.175461 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 23:19:17.182423 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 23:19:17.185349 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 23:19:17.189032 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 23:19:17.195345 0 11 4 | B1->B0 | 2727 3737 | 0 0 | (0 0) (0 0)
1530 23:19:17.199447 0 11 8 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
1531 23:19:17.202159 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1532 23:19:17.208871 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1533 23:19:17.212252 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1534 23:19:17.215868 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1535 23:19:17.222623 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1536 23:19:17.225712 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1537 23:19:17.229286 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1538 23:19:17.232645 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1539 23:19:17.239212 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1540 23:19:17.242193 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1541 23:19:17.245483 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1542 23:19:17.252438 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1543 23:19:17.255608 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1544 23:19:17.259147 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1545 23:19:17.265814 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1546 23:19:17.269104 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1547 23:19:17.272303 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1548 23:19:17.278646 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1549 23:19:17.282418 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1550 23:19:17.285323 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1551 23:19:17.292573 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1552 23:19:17.295319 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1553 23:19:17.299023 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1554 23:19:17.305763 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1555 23:19:17.306340 Total UI for P1: 0, mck2ui 16
1556 23:19:17.312315 best dqsien dly found for B0: ( 0, 14, 2)
1557 23:19:17.312946 Total UI for P1: 0, mck2ui 16
1558 23:19:17.316019 best dqsien dly found for B1: ( 0, 14, 2)
1559 23:19:17.322383 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1560 23:19:17.325680 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1561 23:19:17.326451
1562 23:19:17.328727 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1563 23:19:17.332241 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1564 23:19:17.335822 [Gating] SW calibration Done
1565 23:19:17.336382 ==
1566 23:19:17.339013 Dram Type= 6, Freq= 0, CH_1, rank 0
1567 23:19:17.342578 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1568 23:19:17.343138 ==
1569 23:19:17.345825 RX Vref Scan: 0
1570 23:19:17.346390
1571 23:19:17.346760 RX Vref 0 -> 0, step: 1
1572 23:19:17.347104
1573 23:19:17.348583 RX Delay -130 -> 252, step: 16
1574 23:19:17.352398 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1575 23:19:17.355964 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1576 23:19:17.362396 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1577 23:19:17.365681 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1578 23:19:17.369237 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1579 23:19:17.372365 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1580 23:19:17.375527 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1581 23:19:17.382338 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1582 23:19:17.385389 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1583 23:19:17.388690 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1584 23:19:17.392414 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1585 23:19:17.395272 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1586 23:19:17.402387 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1587 23:19:17.405741 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1588 23:19:17.408363 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1589 23:19:17.412815 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1590 23:19:17.413429 ==
1591 23:19:17.415241 Dram Type= 6, Freq= 0, CH_1, rank 0
1592 23:19:17.421904 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1593 23:19:17.422449 ==
1594 23:19:17.422816 DQS Delay:
1595 23:19:17.425827 DQS0 = 0, DQS1 = 0
1596 23:19:17.426409 DQM Delay:
1597 23:19:17.426794 DQM0 = 93, DQM1 = 87
1598 23:19:17.429200 DQ Delay:
1599 23:19:17.432406 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1600 23:19:17.435917 DQ4 =93, DQ5 =109, DQ6 =101, DQ7 =93
1601 23:19:17.438959 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =85
1602 23:19:17.441831 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1603 23:19:17.442289
1604 23:19:17.442650
1605 23:19:17.442986 ==
1606 23:19:17.445711 Dram Type= 6, Freq= 0, CH_1, rank 0
1607 23:19:17.449227 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1608 23:19:17.449852 ==
1609 23:19:17.450227
1610 23:19:17.450567
1611 23:19:17.452283 TX Vref Scan disable
1612 23:19:17.452738 == TX Byte 0 ==
1613 23:19:17.458816 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1614 23:19:17.462161 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1615 23:19:17.462624 == TX Byte 1 ==
1616 23:19:17.468951 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1617 23:19:17.472450 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1618 23:19:17.472925 ==
1619 23:19:17.475901 Dram Type= 6, Freq= 0, CH_1, rank 0
1620 23:19:17.479427 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1621 23:19:17.480005 ==
1622 23:19:17.492559 TX Vref=22, minBit 0, minWin=26, winSum=436
1623 23:19:17.496325 TX Vref=24, minBit 0, minWin=27, winSum=442
1624 23:19:17.499389 TX Vref=26, minBit 3, minWin=26, winSum=442
1625 23:19:17.503267 TX Vref=28, minBit 1, minWin=27, winSum=449
1626 23:19:17.505995 TX Vref=30, minBit 0, minWin=27, winSum=448
1627 23:19:17.509752 TX Vref=32, minBit 0, minWin=27, winSum=449
1628 23:19:17.516089 [TxChooseVref] Worse bit 1, Min win 27, Win sum 449, Final Vref 28
1629 23:19:17.516636
1630 23:19:17.519460 Final TX Range 1 Vref 28
1631 23:19:17.520014
1632 23:19:17.520381 ==
1633 23:19:17.522504 Dram Type= 6, Freq= 0, CH_1, rank 0
1634 23:19:17.525755 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1635 23:19:17.526219 ==
1636 23:19:17.526588
1637 23:19:17.529467
1638 23:19:17.530109 TX Vref Scan disable
1639 23:19:17.532788 == TX Byte 0 ==
1640 23:19:17.536550 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1641 23:19:17.539924 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1642 23:19:17.542584 == TX Byte 1 ==
1643 23:19:17.546197 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1644 23:19:17.549548 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1645 23:19:17.552873
1646 23:19:17.553326 [DATLAT]
1647 23:19:17.553731 Freq=800, CH1 RK0
1648 23:19:17.554081
1649 23:19:17.556426 DATLAT Default: 0xa
1650 23:19:17.556981 0, 0xFFFF, sum = 0
1651 23:19:17.559511 1, 0xFFFF, sum = 0
1652 23:19:17.560106 2, 0xFFFF, sum = 0
1653 23:19:17.563067 3, 0xFFFF, sum = 0
1654 23:19:17.563630 4, 0xFFFF, sum = 0
1655 23:19:17.566204 5, 0xFFFF, sum = 0
1656 23:19:17.566672 6, 0xFFFF, sum = 0
1657 23:19:17.569376 7, 0xFFFF, sum = 0
1658 23:19:17.573139 8, 0xFFFF, sum = 0
1659 23:19:17.573648 9, 0x0, sum = 1
1660 23:19:17.574029 10, 0x0, sum = 2
1661 23:19:17.575991 11, 0x0, sum = 3
1662 23:19:17.576456 12, 0x0, sum = 4
1663 23:19:17.579083 best_step = 10
1664 23:19:17.579542
1665 23:19:17.579907 ==
1666 23:19:17.583192 Dram Type= 6, Freq= 0, CH_1, rank 0
1667 23:19:17.586013 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1668 23:19:17.586510 ==
1669 23:19:17.589177 RX Vref Scan: 1
1670 23:19:17.589676
1671 23:19:17.590056 Set Vref Range= 32 -> 127
1672 23:19:17.590398
1673 23:19:17.592727 RX Vref 32 -> 127, step: 1
1674 23:19:17.593183
1675 23:19:17.595936 RX Delay -79 -> 252, step: 8
1676 23:19:17.596424
1677 23:19:17.599208 Set Vref, RX VrefLevel [Byte0]: 32
1678 23:19:17.602728 [Byte1]: 32
1679 23:19:17.603457
1680 23:19:17.606102 Set Vref, RX VrefLevel [Byte0]: 33
1681 23:19:17.609718 [Byte1]: 33
1682 23:19:17.613186
1683 23:19:17.613887 Set Vref, RX VrefLevel [Byte0]: 34
1684 23:19:17.616619 [Byte1]: 34
1685 23:19:17.620496
1686 23:19:17.621047 Set Vref, RX VrefLevel [Byte0]: 35
1687 23:19:17.623643 [Byte1]: 35
1688 23:19:17.628489
1689 23:19:17.629042 Set Vref, RX VrefLevel [Byte0]: 36
1690 23:19:17.631246 [Byte1]: 36
1691 23:19:17.635604
1692 23:19:17.636061 Set Vref, RX VrefLevel [Byte0]: 37
1693 23:19:17.638948 [Byte1]: 37
1694 23:19:17.643388
1695 23:19:17.643950 Set Vref, RX VrefLevel [Byte0]: 38
1696 23:19:17.646102 [Byte1]: 38
1697 23:19:17.650622
1698 23:19:17.651179 Set Vref, RX VrefLevel [Byte0]: 39
1699 23:19:17.654446 [Byte1]: 39
1700 23:19:17.658182
1701 23:19:17.658643 Set Vref, RX VrefLevel [Byte0]: 40
1702 23:19:17.661671 [Byte1]: 40
1703 23:19:17.665756
1704 23:19:17.666255 Set Vref, RX VrefLevel [Byte0]: 41
1705 23:19:17.669259 [Byte1]: 41
1706 23:19:17.673087
1707 23:19:17.673545 Set Vref, RX VrefLevel [Byte0]: 42
1708 23:19:17.676897 [Byte1]: 42
1709 23:19:17.680660
1710 23:19:17.681118 Set Vref, RX VrefLevel [Byte0]: 43
1711 23:19:17.683919 [Byte1]: 43
1712 23:19:17.688608
1713 23:19:17.689069 Set Vref, RX VrefLevel [Byte0]: 44
1714 23:19:17.691504 [Byte1]: 44
1715 23:19:17.696145
1716 23:19:17.696639 Set Vref, RX VrefLevel [Byte0]: 45
1717 23:19:17.699234 [Byte1]: 45
1718 23:19:17.703585
1719 23:19:17.704041 Set Vref, RX VrefLevel [Byte0]: 46
1720 23:19:17.706572 [Byte1]: 46
1721 23:19:17.711231
1722 23:19:17.711785 Set Vref, RX VrefLevel [Byte0]: 47
1723 23:19:17.714567 [Byte1]: 47
1724 23:19:17.718274
1725 23:19:17.718730 Set Vref, RX VrefLevel [Byte0]: 48
1726 23:19:17.721825 [Byte1]: 48
1727 23:19:17.726104
1728 23:19:17.726566 Set Vref, RX VrefLevel [Byte0]: 49
1729 23:19:17.729772 [Byte1]: 49
1730 23:19:17.734247
1731 23:19:17.734813 Set Vref, RX VrefLevel [Byte0]: 50
1732 23:19:17.736934 [Byte1]: 50
1733 23:19:17.741492
1734 23:19:17.742080 Set Vref, RX VrefLevel [Byte0]: 51
1735 23:19:17.744988 [Byte1]: 51
1736 23:19:17.749225
1737 23:19:17.749810 Set Vref, RX VrefLevel [Byte0]: 52
1738 23:19:17.752396 [Byte1]: 52
1739 23:19:17.756752
1740 23:19:17.757307 Set Vref, RX VrefLevel [Byte0]: 53
1741 23:19:17.759830 [Byte1]: 53
1742 23:19:17.764366
1743 23:19:17.764922 Set Vref, RX VrefLevel [Byte0]: 54
1744 23:19:17.767384 [Byte1]: 54
1745 23:19:17.771406
1746 23:19:17.771865 Set Vref, RX VrefLevel [Byte0]: 55
1747 23:19:17.774913 [Byte1]: 55
1748 23:19:17.778779
1749 23:19:17.779233 Set Vref, RX VrefLevel [Byte0]: 56
1750 23:19:17.782005 [Byte1]: 56
1751 23:19:17.786506
1752 23:19:17.787062 Set Vref, RX VrefLevel [Byte0]: 57
1753 23:19:17.789692 [Byte1]: 57
1754 23:19:17.794173
1755 23:19:17.794730 Set Vref, RX VrefLevel [Byte0]: 58
1756 23:19:17.797134 [Byte1]: 58
1757 23:19:17.801926
1758 23:19:17.802549 Set Vref, RX VrefLevel [Byte0]: 59
1759 23:19:17.805040 [Byte1]: 59
1760 23:19:17.809082
1761 23:19:17.809690 Set Vref, RX VrefLevel [Byte0]: 60
1762 23:19:17.812545 [Byte1]: 60
1763 23:19:17.816537
1764 23:19:17.817003 Set Vref, RX VrefLevel [Byte0]: 61
1765 23:19:17.819957 [Byte1]: 61
1766 23:19:17.823922
1767 23:19:17.824397 Set Vref, RX VrefLevel [Byte0]: 62
1768 23:19:17.827396 [Byte1]: 62
1769 23:19:17.831428
1770 23:19:17.831860 Set Vref, RX VrefLevel [Byte0]: 63
1771 23:19:17.834818 [Byte1]: 63
1772 23:19:17.839179
1773 23:19:17.839603 Set Vref, RX VrefLevel [Byte0]: 64
1774 23:19:17.842561 [Byte1]: 64
1775 23:19:17.847336
1776 23:19:17.847848 Set Vref, RX VrefLevel [Byte0]: 65
1777 23:19:17.849965 [Byte1]: 65
1778 23:19:17.854530
1779 23:19:17.855147 Set Vref, RX VrefLevel [Byte0]: 66
1780 23:19:17.857909 [Byte1]: 66
1781 23:19:17.861765
1782 23:19:17.862189 Set Vref, RX VrefLevel [Byte0]: 67
1783 23:19:17.865178 [Byte1]: 67
1784 23:19:17.869414
1785 23:19:17.870092 Set Vref, RX VrefLevel [Byte0]: 68
1786 23:19:17.872433 [Byte1]: 68
1787 23:19:17.877144
1788 23:19:17.877566 Set Vref, RX VrefLevel [Byte0]: 69
1789 23:19:17.880814 [Byte1]: 69
1790 23:19:17.884646
1791 23:19:17.885204 Set Vref, RX VrefLevel [Byte0]: 70
1792 23:19:17.887948 [Byte1]: 70
1793 23:19:17.892669
1794 23:19:17.893231 Set Vref, RX VrefLevel [Byte0]: 71
1795 23:19:17.895116 [Byte1]: 71
1796 23:19:17.899809
1797 23:19:17.900367 Set Vref, RX VrefLevel [Byte0]: 72
1798 23:19:17.903222 [Byte1]: 72
1799 23:19:17.906859
1800 23:19:17.907324 Final RX Vref Byte 0 = 57 to rank0
1801 23:19:17.910442 Final RX Vref Byte 1 = 56 to rank0
1802 23:19:17.913882 Final RX Vref Byte 0 = 57 to rank1
1803 23:19:17.917116 Final RX Vref Byte 1 = 56 to rank1==
1804 23:19:17.920701 Dram Type= 6, Freq= 0, CH_1, rank 0
1805 23:19:17.926904 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1806 23:19:17.927429 ==
1807 23:19:17.927771 DQS Delay:
1808 23:19:17.928084 DQS0 = 0, DQS1 = 0
1809 23:19:17.930516 DQM Delay:
1810 23:19:17.930941 DQM0 = 95, DQM1 = 90
1811 23:19:17.933435 DQ Delay:
1812 23:19:17.937168 DQ0 =96, DQ1 =88, DQ2 =88, DQ3 =92
1813 23:19:17.940701 DQ4 =92, DQ5 =108, DQ6 =108, DQ7 =92
1814 23:19:17.944081 DQ8 =80, DQ9 =84, DQ10 =88, DQ11 =84
1815 23:19:17.947168 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
1816 23:19:17.947684
1817 23:19:17.948022
1818 23:19:17.953635 [DQSOSCAuto] RK0, (LSB)MR18= 0x2e4b, (MSB)MR19= 0x606, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
1819 23:19:17.957303 CH1 RK0: MR19=606, MR18=2E4B
1820 23:19:17.963667 CH1_RK0: MR19=0x606, MR18=0x2E4B, DQSOSC=391, MR23=63, INC=96, DEC=64
1821 23:19:17.964175
1822 23:19:17.967520 ----->DramcWriteLeveling(PI) begin...
1823 23:19:17.968043 ==
1824 23:19:17.970656 Dram Type= 6, Freq= 0, CH_1, rank 1
1825 23:19:17.973871 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1826 23:19:17.974300 ==
1827 23:19:17.976910 Write leveling (Byte 0): 26 => 26
1828 23:19:17.980403 Write leveling (Byte 1): 26 => 26
1829 23:19:17.983608 DramcWriteLeveling(PI) end<-----
1830 23:19:17.984031
1831 23:19:17.984368 ==
1832 23:19:17.987164 Dram Type= 6, Freq= 0, CH_1, rank 1
1833 23:19:17.990328 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1834 23:19:17.990757 ==
1835 23:19:17.993639 [Gating] SW mode calibration
1836 23:19:18.000604 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1837 23:19:18.007451 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1838 23:19:18.010338 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1839 23:19:18.014278 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1840 23:19:18.020304 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 23:19:18.023485 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 23:19:18.026783 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 23:19:18.033999 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 23:19:18.037053 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 23:19:18.040656 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 23:19:18.047122 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 23:19:18.050714 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1848 23:19:18.053937 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 23:19:18.060606 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1850 23:19:18.064057 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1851 23:19:18.067165 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1852 23:19:18.073548 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1853 23:19:18.077270 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1854 23:19:18.080538 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1855 23:19:18.086782 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1856 23:19:18.090059 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1857 23:19:18.093533 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1858 23:19:18.097339 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1859 23:19:18.103995 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1860 23:19:18.107472 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1861 23:19:18.110608 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1862 23:19:18.117178 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1863 23:19:18.120582 0 9 4 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
1864 23:19:18.123937 0 9 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
1865 23:19:18.130621 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1866 23:19:18.134289 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1867 23:19:18.137338 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1868 23:19:18.143717 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1869 23:19:18.146969 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1870 23:19:18.150338 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
1871 23:19:18.157174 0 10 4 | B1->B0 | 2a2a 3030 | 0 0 | (0 0) (0 1)
1872 23:19:18.160375 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1873 23:19:18.164113 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 23:19:18.170514 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 23:19:18.173740 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 23:19:18.177001 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 23:19:18.180447 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 23:19:18.187479 0 11 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1879 23:19:18.190177 0 11 4 | B1->B0 | 3b3b 2c2c | 0 1 | (1 1) (0 0)
1880 23:19:18.193823 0 11 8 | B1->B0 | 4646 4343 | 0 0 | (0 0) (0 0)
1881 23:19:18.200170 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1882 23:19:18.203811 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1883 23:19:18.207090 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1884 23:19:18.213843 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1885 23:19:18.216969 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1886 23:19:18.220723 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1887 23:19:18.226988 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1888 23:19:18.230354 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1889 23:19:18.234149 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1890 23:19:18.240763 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1891 23:19:18.243688 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1892 23:19:18.247651 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1893 23:19:18.254157 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1894 23:19:18.257417 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1895 23:19:18.260464 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1896 23:19:18.267098 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1897 23:19:18.270535 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1898 23:19:18.273701 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1899 23:19:18.277658 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1900 23:19:18.283624 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1901 23:19:18.287305 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1902 23:19:18.290744 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1903 23:19:18.296857 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1904 23:19:18.300693 Total UI for P1: 0, mck2ui 16
1905 23:19:18.303754 best dqsien dly found for B1: ( 0, 14, 2)
1906 23:19:18.307322 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1907 23:19:18.310308 Total UI for P1: 0, mck2ui 16
1908 23:19:18.314088 best dqsien dly found for B0: ( 0, 14, 4)
1909 23:19:18.317256 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1910 23:19:18.320553 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1911 23:19:18.321019
1912 23:19:18.324002 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1913 23:19:18.327347 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1914 23:19:18.330885 [Gating] SW calibration Done
1915 23:19:18.331348 ==
1916 23:19:18.333903 Dram Type= 6, Freq= 0, CH_1, rank 1
1917 23:19:18.337421 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1918 23:19:18.338041 ==
1919 23:19:18.340672 RX Vref Scan: 0
1920 23:19:18.341228
1921 23:19:18.344065 RX Vref 0 -> 0, step: 1
1922 23:19:18.344623
1923 23:19:18.344993 RX Delay -130 -> 252, step: 16
1924 23:19:18.350686 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1925 23:19:18.354280 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1926 23:19:18.357379 iDelay=222, Bit 2, Center 85 (-18 ~ 189) 208
1927 23:19:18.360717 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1928 23:19:18.364722 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1929 23:19:18.371035 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1930 23:19:18.374011 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1931 23:19:18.377659 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1932 23:19:18.381066 iDelay=222, Bit 8, Center 85 (-18 ~ 189) 208
1933 23:19:18.384071 iDelay=222, Bit 9, Center 85 (-18 ~ 189) 208
1934 23:19:18.390684 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1935 23:19:18.394280 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1936 23:19:18.397202 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1937 23:19:18.401128 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1938 23:19:18.404596 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1939 23:19:18.410667 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1940 23:19:18.411214 ==
1941 23:19:18.413965 Dram Type= 6, Freq= 0, CH_1, rank 1
1942 23:19:18.417267 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1943 23:19:18.417820 ==
1944 23:19:18.418206 DQS Delay:
1945 23:19:18.420824 DQS0 = 0, DQS1 = 0
1946 23:19:18.421417 DQM Delay:
1947 23:19:18.424041 DQM0 = 92, DQM1 = 89
1948 23:19:18.424597 DQ Delay:
1949 23:19:18.427594 DQ0 =93, DQ1 =85, DQ2 =85, DQ3 =85
1950 23:19:18.430594 DQ4 =85, DQ5 =109, DQ6 =101, DQ7 =93
1951 23:19:18.433846 DQ8 =85, DQ9 =85, DQ10 =85, DQ11 =85
1952 23:19:18.437429 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1953 23:19:18.438077
1954 23:19:18.438456
1955 23:19:18.438800 ==
1956 23:19:18.441007 Dram Type= 6, Freq= 0, CH_1, rank 1
1957 23:19:18.444600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1958 23:19:18.445174 ==
1959 23:19:18.447738
1960 23:19:18.448294
1961 23:19:18.448661 TX Vref Scan disable
1962 23:19:18.451461 == TX Byte 0 ==
1963 23:19:18.454374 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1964 23:19:18.457779 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1965 23:19:18.461373 == TX Byte 1 ==
1966 23:19:18.464615 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1967 23:19:18.467895 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1968 23:19:18.468455 ==
1969 23:19:18.471283 Dram Type= 6, Freq= 0, CH_1, rank 1
1970 23:19:18.477648 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1971 23:19:18.478229 ==
1972 23:19:18.489273 TX Vref=22, minBit 1, minWin=26, winSum=439
1973 23:19:18.492768 TX Vref=24, minBit 1, minWin=26, winSum=434
1974 23:19:18.496068 TX Vref=26, minBit 0, minWin=27, winSum=442
1975 23:19:18.499722 TX Vref=28, minBit 2, minWin=27, winSum=449
1976 23:19:18.502907 TX Vref=30, minBit 2, minWin=27, winSum=447
1977 23:19:18.506219 TX Vref=32, minBit 0, minWin=27, winSum=445
1978 23:19:18.512721 [TxChooseVref] Worse bit 2, Min win 27, Win sum 449, Final Vref 28
1979 23:19:18.513384
1980 23:19:18.516034 Final TX Range 1 Vref 28
1981 23:19:18.516510
1982 23:19:18.516996 ==
1983 23:19:18.519463 Dram Type= 6, Freq= 0, CH_1, rank 1
1984 23:19:18.522929 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1985 23:19:18.523500 ==
1986 23:19:18.523991
1987 23:19:18.524448
1988 23:19:18.526112 TX Vref Scan disable
1989 23:19:18.529333 == TX Byte 0 ==
1990 23:19:18.532903 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1991 23:19:18.536354 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1992 23:19:18.540178 == TX Byte 1 ==
1993 23:19:18.543363 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1994 23:19:18.546430 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1995 23:19:18.546913
1996 23:19:18.550024 [DATLAT]
1997 23:19:18.550600 Freq=800, CH1 RK1
1998 23:19:18.551093
1999 23:19:18.552927 DATLAT Default: 0xa
2000 23:19:18.553404 0, 0xFFFF, sum = 0
2001 23:19:18.556429 1, 0xFFFF, sum = 0
2002 23:19:18.557011 2, 0xFFFF, sum = 0
2003 23:19:18.560257 3, 0xFFFF, sum = 0
2004 23:19:18.560830 4, 0xFFFF, sum = 0
2005 23:19:18.563735 5, 0xFFFF, sum = 0
2006 23:19:18.564316 6, 0xFFFF, sum = 0
2007 23:19:18.566278 7, 0xFFFF, sum = 0
2008 23:19:18.566925 8, 0xFFFF, sum = 0
2009 23:19:18.569813 9, 0x0, sum = 1
2010 23:19:18.570369 10, 0x0, sum = 2
2011 23:19:18.572961 11, 0x0, sum = 3
2012 23:19:18.573646 12, 0x0, sum = 4
2013 23:19:18.576521 best_step = 10
2014 23:19:18.577074
2015 23:19:18.577444 ==
2016 23:19:18.579739 Dram Type= 6, Freq= 0, CH_1, rank 1
2017 23:19:18.583089 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2018 23:19:18.583558 ==
2019 23:19:18.583931 RX Vref Scan: 0
2020 23:19:18.586643
2021 23:19:18.587104 RX Vref 0 -> 0, step: 1
2022 23:19:18.587473
2023 23:19:18.589824 RX Delay -63 -> 252, step: 8
2024 23:19:18.593275 iDelay=209, Bit 0, Center 104 (9 ~ 200) 192
2025 23:19:18.599957 iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200
2026 23:19:18.603384 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
2027 23:19:18.606423 iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200
2028 23:19:18.610017 iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200
2029 23:19:18.613511 iDelay=209, Bit 5, Center 112 (17 ~ 208) 192
2030 23:19:18.616605 iDelay=209, Bit 6, Center 108 (9 ~ 208) 200
2031 23:19:18.623302 iDelay=209, Bit 7, Center 96 (-7 ~ 200) 208
2032 23:19:18.626463 iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208
2033 23:19:18.629759 iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208
2034 23:19:18.633159 iDelay=209, Bit 10, Center 88 (-15 ~ 192) 208
2035 23:19:18.636367 iDelay=209, Bit 11, Center 84 (-23 ~ 192) 216
2036 23:19:18.643152 iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216
2037 23:19:18.646693 iDelay=209, Bit 13, Center 96 (-7 ~ 200) 208
2038 23:19:18.649779 iDelay=209, Bit 14, Center 96 (-7 ~ 200) 208
2039 23:19:18.653774 iDelay=209, Bit 15, Center 96 (-7 ~ 200) 208
2040 23:19:18.654382 ==
2041 23:19:18.656822 Dram Type= 6, Freq= 0, CH_1, rank 1
2042 23:19:18.663329 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2043 23:19:18.663891 ==
2044 23:19:18.664263 DQS Delay:
2045 23:19:18.664605 DQS0 = 0, DQS1 = 0
2046 23:19:18.666193 DQM Delay:
2047 23:19:18.666651 DQM0 = 97, DQM1 = 90
2048 23:19:18.669518 DQ Delay:
2049 23:19:18.673267 DQ0 =104, DQ1 =92, DQ2 =84, DQ3 =92
2050 23:19:18.676546 DQ4 =92, DQ5 =112, DQ6 =108, DQ7 =96
2051 23:19:18.679667 DQ8 =80, DQ9 =80, DQ10 =88, DQ11 =84
2052 23:19:18.683433 DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =96
2053 23:19:18.684002
2054 23:19:18.684370
2055 23:19:18.690215 [DQSOSCAuto] RK1, (LSB)MR18= 0x430c, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 393 ps
2056 23:19:18.693033 CH1 RK1: MR19=606, MR18=430C
2057 23:19:18.699938 CH1_RK1: MR19=0x606, MR18=0x430C, DQSOSC=393, MR23=63, INC=95, DEC=63
2058 23:19:18.703373 [RxdqsGatingPostProcess] freq 800
2059 23:19:18.706941 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2060 23:19:18.710140 Pre-setting of DQS Precalculation
2061 23:19:18.716369 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2062 23:19:18.723166 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2063 23:19:18.729719 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2064 23:19:18.730180
2065 23:19:18.730547
2066 23:19:18.733886 [Calibration Summary] 1600 Mbps
2067 23:19:18.734454 CH 0, Rank 0
2068 23:19:18.736660 SW Impedance : PASS
2069 23:19:18.740065 DUTY Scan : NO K
2070 23:19:18.740634 ZQ Calibration : PASS
2071 23:19:18.743340 Jitter Meter : NO K
2072 23:19:18.746532 CBT Training : PASS
2073 23:19:18.746991 Write leveling : PASS
2074 23:19:18.749974 RX DQS gating : PASS
2075 23:19:18.750435 RX DQ/DQS(RDDQC) : PASS
2076 23:19:18.753518 TX DQ/DQS : PASS
2077 23:19:18.756417 RX DATLAT : PASS
2078 23:19:18.756994 RX DQ/DQS(Engine): PASS
2079 23:19:18.759945 TX OE : NO K
2080 23:19:18.760504 All Pass.
2081 23:19:18.760870
2082 23:19:18.763158 CH 0, Rank 1
2083 23:19:18.763648 SW Impedance : PASS
2084 23:19:18.766210 DUTY Scan : NO K
2085 23:19:18.769485 ZQ Calibration : PASS
2086 23:19:18.770049 Jitter Meter : NO K
2087 23:19:18.772948 CBT Training : PASS
2088 23:19:18.776716 Write leveling : PASS
2089 23:19:18.777274 RX DQS gating : PASS
2090 23:19:18.779617 RX DQ/DQS(RDDQC) : PASS
2091 23:19:18.783844 TX DQ/DQS : PASS
2092 23:19:18.784445 RX DATLAT : PASS
2093 23:19:18.786196 RX DQ/DQS(Engine): PASS
2094 23:19:18.789898 TX OE : NO K
2095 23:19:18.790410 All Pass.
2096 23:19:18.790782
2097 23:19:18.791137 CH 1, Rank 0
2098 23:19:18.793036 SW Impedance : PASS
2099 23:19:18.796451 DUTY Scan : NO K
2100 23:19:18.796909 ZQ Calibration : PASS
2101 23:19:18.799738 Jitter Meter : NO K
2102 23:19:18.800220 CBT Training : PASS
2103 23:19:18.803357 Write leveling : PASS
2104 23:19:18.806389 RX DQS gating : PASS
2105 23:19:18.806850 RX DQ/DQS(RDDQC) : PASS
2106 23:19:18.809668 TX DQ/DQS : PASS
2107 23:19:18.812966 RX DATLAT : PASS
2108 23:19:18.813425 RX DQ/DQS(Engine): PASS
2109 23:19:18.816811 TX OE : NO K
2110 23:19:18.817373 All Pass.
2111 23:19:18.817842
2112 23:19:18.820394 CH 1, Rank 1
2113 23:19:18.820950 SW Impedance : PASS
2114 23:19:18.823447 DUTY Scan : NO K
2115 23:19:18.827046 ZQ Calibration : PASS
2116 23:19:18.827606 Jitter Meter : NO K
2117 23:19:18.829716 CBT Training : PASS
2118 23:19:18.833883 Write leveling : PASS
2119 23:19:18.834458 RX DQS gating : PASS
2120 23:19:18.837039 RX DQ/DQS(RDDQC) : PASS
2121 23:19:18.837648 TX DQ/DQS : PASS
2122 23:19:18.840430 RX DATLAT : PASS
2123 23:19:18.843478 RX DQ/DQS(Engine): PASS
2124 23:19:18.843961 TX OE : NO K
2125 23:19:18.846345 All Pass.
2126 23:19:18.846803
2127 23:19:18.847164 DramC Write-DBI off
2128 23:19:18.849911 PER_BANK_REFRESH: Hybrid Mode
2129 23:19:18.853064 TX_TRACKING: ON
2130 23:19:18.856457 [GetDramInforAfterCalByMRR] Vendor 6.
2131 23:19:18.859866 [GetDramInforAfterCalByMRR] Revision 606.
2132 23:19:18.863312 [GetDramInforAfterCalByMRR] Revision 2 0.
2133 23:19:18.863871 MR0 0x3b3b
2134 23:19:18.864245 MR8 0x5151
2135 23:19:18.866660 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2136 23:19:18.869993
2137 23:19:18.870486 MR0 0x3b3b
2138 23:19:18.870912 MR8 0x5151
2139 23:19:18.873142 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2140 23:19:18.873647
2141 23:19:18.882983 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2142 23:19:18.886260 [FAST_K] Save calibration result to emmc
2143 23:19:18.889689 [FAST_K] Save calibration result to emmc
2144 23:19:18.893328 dram_init: config_dvfs: 1
2145 23:19:18.896860 dramc_set_vcore_voltage set vcore to 662500
2146 23:19:18.899760 Read voltage for 1200, 2
2147 23:19:18.900195 Vio18 = 0
2148 23:19:18.900526 Vcore = 662500
2149 23:19:18.903117 Vdram = 0
2150 23:19:18.903547 Vddq = 0
2151 23:19:18.903878 Vmddr = 0
2152 23:19:18.909787 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2153 23:19:18.912793 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2154 23:19:18.916971 MEM_TYPE=3, freq_sel=15
2155 23:19:18.919569 sv_algorithm_assistance_LP4_1600
2156 23:19:18.923276 ============ PULL DRAM RESETB DOWN ============
2157 23:19:18.926696 ========== PULL DRAM RESETB DOWN end =========
2158 23:19:18.933015 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2159 23:19:18.936510 ===================================
2160 23:19:18.939559 LPDDR4 DRAM CONFIGURATION
2161 23:19:18.943234 ===================================
2162 23:19:18.943754 EX_ROW_EN[0] = 0x0
2163 23:19:18.946527 EX_ROW_EN[1] = 0x0
2164 23:19:18.947052 LP4Y_EN = 0x0
2165 23:19:18.949766 WORK_FSP = 0x0
2166 23:19:18.950178 WL = 0x4
2167 23:19:18.953229 RL = 0x4
2168 23:19:18.953796 BL = 0x2
2169 23:19:18.956507 RPST = 0x0
2170 23:19:18.957037 RD_PRE = 0x0
2171 23:19:18.959958 WR_PRE = 0x1
2172 23:19:18.960475 WR_PST = 0x0
2173 23:19:18.963389 DBI_WR = 0x0
2174 23:19:18.963903 DBI_RD = 0x0
2175 23:19:18.966336 OTF = 0x1
2176 23:19:18.970046 ===================================
2177 23:19:18.972513 ===================================
2178 23:19:18.972927 ANA top config
2179 23:19:18.976430 ===================================
2180 23:19:18.979430 DLL_ASYNC_EN = 0
2181 23:19:18.982788 ALL_SLAVE_EN = 0
2182 23:19:18.986033 NEW_RANK_MODE = 1
2183 23:19:18.986449 DLL_IDLE_MODE = 1
2184 23:19:18.989618 LP45_APHY_COMB_EN = 1
2185 23:19:18.992704 TX_ODT_DIS = 1
2186 23:19:18.996365 NEW_8X_MODE = 1
2187 23:19:18.999991 ===================================
2188 23:19:19.003608 ===================================
2189 23:19:19.006780 data_rate = 2400
2190 23:19:19.007451 CKR = 1
2191 23:19:19.009517 DQ_P2S_RATIO = 8
2192 23:19:19.012921 ===================================
2193 23:19:19.016169 CA_P2S_RATIO = 8
2194 23:19:19.020040 DQ_CA_OPEN = 0
2195 23:19:19.023221 DQ_SEMI_OPEN = 0
2196 23:19:19.026126 CA_SEMI_OPEN = 0
2197 23:19:19.026545 CA_FULL_RATE = 0
2198 23:19:19.029640 DQ_CKDIV4_EN = 0
2199 23:19:19.032896 CA_CKDIV4_EN = 0
2200 23:19:19.036356 CA_PREDIV_EN = 0
2201 23:19:19.039495 PH8_DLY = 17
2202 23:19:19.043251 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2203 23:19:19.043769 DQ_AAMCK_DIV = 4
2204 23:19:19.046611 CA_AAMCK_DIV = 4
2205 23:19:19.050189 CA_ADMCK_DIV = 4
2206 23:19:19.053420 DQ_TRACK_CA_EN = 0
2207 23:19:19.056247 CA_PICK = 1200
2208 23:19:19.059862 CA_MCKIO = 1200
2209 23:19:19.060384 MCKIO_SEMI = 0
2210 23:19:19.063401 PLL_FREQ = 2366
2211 23:19:19.066892 DQ_UI_PI_RATIO = 32
2212 23:19:19.069798 CA_UI_PI_RATIO = 0
2213 23:19:19.073372 ===================================
2214 23:19:19.076991 ===================================
2215 23:19:19.080551 memory_type:LPDDR4
2216 23:19:19.081070 GP_NUM : 10
2217 23:19:19.083811 SRAM_EN : 1
2218 23:19:19.084332 MD32_EN : 0
2219 23:19:19.086391 ===================================
2220 23:19:19.089880 [ANA_INIT] >>>>>>>>>>>>>>
2221 23:19:19.093340 <<<<<< [CONFIGURE PHASE]: ANA_TX
2222 23:19:19.096915 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2223 23:19:19.100199 ===================================
2224 23:19:19.103820 data_rate = 2400,PCW = 0X5b00
2225 23:19:19.106622 ===================================
2226 23:19:19.109753 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2227 23:19:19.116833 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2228 23:19:19.119939 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2229 23:19:19.126576 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2230 23:19:19.130239 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2231 23:19:19.133620 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2232 23:19:19.134088 [ANA_INIT] flow start
2233 23:19:19.136444 [ANA_INIT] PLL >>>>>>>>
2234 23:19:19.140370 [ANA_INIT] PLL <<<<<<<<
2235 23:19:19.140938 [ANA_INIT] MIDPI >>>>>>>>
2236 23:19:19.143637 [ANA_INIT] MIDPI <<<<<<<<
2237 23:19:19.146731 [ANA_INIT] DLL >>>>>>>>
2238 23:19:19.147192 [ANA_INIT] DLL <<<<<<<<
2239 23:19:19.150018 [ANA_INIT] flow end
2240 23:19:19.153242 ============ LP4 DIFF to SE enter ============
2241 23:19:19.156862 ============ LP4 DIFF to SE exit ============
2242 23:19:19.160529 [ANA_INIT] <<<<<<<<<<<<<
2243 23:19:19.163738 [Flow] Enable top DCM control >>>>>
2244 23:19:19.166746 [Flow] Enable top DCM control <<<<<
2245 23:19:19.170217 Enable DLL master slave shuffle
2246 23:19:19.176616 ==============================================================
2247 23:19:19.177079 Gating Mode config
2248 23:19:19.183501 ==============================================================
2249 23:19:19.184047 Config description:
2250 23:19:19.193928 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2251 23:19:19.200621 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2252 23:19:19.207305 SELPH_MODE 0: By rank 1: By Phase
2253 23:19:19.210339 ==============================================================
2254 23:19:19.213524 GAT_TRACK_EN = 1
2255 23:19:19.216882 RX_GATING_MODE = 2
2256 23:19:19.220323 RX_GATING_TRACK_MODE = 2
2257 23:19:19.223953 SELPH_MODE = 1
2258 23:19:19.226879 PICG_EARLY_EN = 1
2259 23:19:19.230145 VALID_LAT_VALUE = 1
2260 23:19:19.233687 ==============================================================
2261 23:19:19.237270 Enter into Gating configuration >>>>
2262 23:19:19.240268 Exit from Gating configuration <<<<
2263 23:19:19.243708 Enter into DVFS_PRE_config >>>>>
2264 23:19:19.257162 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2265 23:19:19.260347 Exit from DVFS_PRE_config <<<<<
2266 23:19:19.260881 Enter into PICG configuration >>>>
2267 23:19:19.264003 Exit from PICG configuration <<<<
2268 23:19:19.267330 [RX_INPUT] configuration >>>>>
2269 23:19:19.270239 [RX_INPUT] configuration <<<<<
2270 23:19:19.277371 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2271 23:19:19.279997 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2272 23:19:19.287521 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2273 23:19:19.293615 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2274 23:19:19.300817 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2275 23:19:19.307112 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2276 23:19:19.310509 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2277 23:19:19.314186 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2278 23:19:19.317067 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2279 23:19:19.324167 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2280 23:19:19.327076 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2281 23:19:19.330396 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2282 23:19:19.333963 ===================================
2283 23:19:19.337220 LPDDR4 DRAM CONFIGURATION
2284 23:19:19.340926 ===================================
2285 23:19:19.341479 EX_ROW_EN[0] = 0x0
2286 23:19:19.344011 EX_ROW_EN[1] = 0x0
2287 23:19:19.344563 LP4Y_EN = 0x0
2288 23:19:19.347446 WORK_FSP = 0x0
2289 23:19:19.350726 WL = 0x4
2290 23:19:19.351300 RL = 0x4
2291 23:19:19.353469 BL = 0x2
2292 23:19:19.353992 RPST = 0x0
2293 23:19:19.357307 RD_PRE = 0x0
2294 23:19:19.358012 WR_PRE = 0x1
2295 23:19:19.360153 WR_PST = 0x0
2296 23:19:19.360611 DBI_WR = 0x0
2297 23:19:19.364152 DBI_RD = 0x0
2298 23:19:19.364705 OTF = 0x1
2299 23:19:19.367130 ===================================
2300 23:19:19.370623 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2301 23:19:19.376973 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2302 23:19:19.380513 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2303 23:19:19.384173 ===================================
2304 23:19:19.387395 LPDDR4 DRAM CONFIGURATION
2305 23:19:19.390693 ===================================
2306 23:19:19.391156 EX_ROW_EN[0] = 0x10
2307 23:19:19.394095 EX_ROW_EN[1] = 0x0
2308 23:19:19.394556 LP4Y_EN = 0x0
2309 23:19:19.397500 WORK_FSP = 0x0
2310 23:19:19.398009 WL = 0x4
2311 23:19:19.400305 RL = 0x4
2312 23:19:19.400764 BL = 0x2
2313 23:19:19.403968 RPST = 0x0
2314 23:19:19.404685 RD_PRE = 0x0
2315 23:19:19.407651 WR_PRE = 0x1
2316 23:19:19.408109 WR_PST = 0x0
2317 23:19:19.410448 DBI_WR = 0x0
2318 23:19:19.414108 DBI_RD = 0x0
2319 23:19:19.414667 OTF = 0x1
2320 23:19:19.417275 ===================================
2321 23:19:19.424328 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2322 23:19:19.424895 ==
2323 23:19:19.427428 Dram Type= 6, Freq= 0, CH_0, rank 0
2324 23:19:19.430939 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2325 23:19:19.431403 ==
2326 23:19:19.433553 [Duty_Offset_Calibration]
2327 23:19:19.434044 B0:2 B1:1 CA:1
2328 23:19:19.434408
2329 23:19:19.440118 [DutyScan_Calibration_Flow] k_type=0
2330 23:19:19.448225
2331 23:19:19.448676 ==CLK 0==
2332 23:19:19.450981 Final CLK duty delay cell = 0
2333 23:19:19.454333 [0] MAX Duty = 5187%(X100), DQS PI = 24
2334 23:19:19.457998 [0] MIN Duty = 4875%(X100), DQS PI = 0
2335 23:19:19.458292 [0] AVG Duty = 5031%(X100)
2336 23:19:19.461073
2337 23:19:19.461366 CH0 CLK Duty spec in!! Max-Min= 312%
2338 23:19:19.467741 [DutyScan_Calibration_Flow] ====Done====
2339 23:19:19.468157
2340 23:19:19.470806 [DutyScan_Calibration_Flow] k_type=1
2341 23:19:19.485481
2342 23:19:19.485893 ==DQS 0 ==
2343 23:19:19.488690 Final DQS duty delay cell = -4
2344 23:19:19.492140 [-4] MAX Duty = 5124%(X100), DQS PI = 22
2345 23:19:19.495639 [-4] MIN Duty = 4751%(X100), DQS PI = 0
2346 23:19:19.499273 [-4] AVG Duty = 4937%(X100)
2347 23:19:19.499651
2348 23:19:19.499952 ==DQS 1 ==
2349 23:19:19.502150 Final DQS duty delay cell = -4
2350 23:19:19.505539 [-4] MAX Duty = 4969%(X100), DQS PI = 0
2351 23:19:19.509155 [-4] MIN Duty = 4844%(X100), DQS PI = 30
2352 23:19:19.512223 [-4] AVG Duty = 4906%(X100)
2353 23:19:19.512603
2354 23:19:19.515974 CH0 DQS 0 Duty spec in!! Max-Min= 373%
2355 23:19:19.516510
2356 23:19:19.519470 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2357 23:19:19.522481 [DutyScan_Calibration_Flow] ====Done====
2358 23:19:19.522961
2359 23:19:19.525994 [DutyScan_Calibration_Flow] k_type=3
2360 23:19:19.543042
2361 23:19:19.543593 ==DQM 0 ==
2362 23:19:19.546396 Final DQM duty delay cell = 0
2363 23:19:19.549800 [0] MAX Duty = 5125%(X100), DQS PI = 22
2364 23:19:19.552926 [0] MIN Duty = 4906%(X100), DQS PI = 58
2365 23:19:19.553383 [0] AVG Duty = 5015%(X100)
2366 23:19:19.556336
2367 23:19:19.556889 ==DQM 1 ==
2368 23:19:19.559761 Final DQM duty delay cell = 0
2369 23:19:19.563442 [0] MAX Duty = 5124%(X100), DQS PI = 6
2370 23:19:19.566510 [0] MIN Duty = 5031%(X100), DQS PI = 16
2371 23:19:19.567067 [0] AVG Duty = 5077%(X100)
2372 23:19:19.569984
2373 23:19:19.573132 CH0 DQM 0 Duty spec in!! Max-Min= 219%
2374 23:19:19.573746
2375 23:19:19.576667 CH0 DQM 1 Duty spec in!! Max-Min= 93%
2376 23:19:19.579884 [DutyScan_Calibration_Flow] ====Done====
2377 23:19:19.580340
2378 23:19:19.582917 [DutyScan_Calibration_Flow] k_type=2
2379 23:19:19.599354
2380 23:19:19.599930 ==DQ 0 ==
2381 23:19:19.602335 Final DQ duty delay cell = 0
2382 23:19:19.605817 [0] MAX Duty = 5031%(X100), DQS PI = 26
2383 23:19:19.609688 [0] MIN Duty = 4906%(X100), DQS PI = 0
2384 23:19:19.610160 [0] AVG Duty = 4968%(X100)
2385 23:19:19.610641
2386 23:19:19.612681 ==DQ 1 ==
2387 23:19:19.616262 Final DQ duty delay cell = 0
2388 23:19:19.619161 [0] MAX Duty = 5093%(X100), DQS PI = 24
2389 23:19:19.623228 [0] MIN Duty = 4907%(X100), DQS PI = 36
2390 23:19:19.623925 [0] AVG Duty = 5000%(X100)
2391 23:19:19.624415
2392 23:19:19.625851 CH0 DQ 0 Duty spec in!! Max-Min= 125%
2393 23:19:19.626323
2394 23:19:19.629488 CH0 DQ 1 Duty spec in!! Max-Min= 186%
2395 23:19:19.636185 [DutyScan_Calibration_Flow] ====Done====
2396 23:19:19.636732 ==
2397 23:19:19.639585 Dram Type= 6, Freq= 0, CH_1, rank 0
2398 23:19:19.643117 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2399 23:19:19.643684 ==
2400 23:19:19.645949 [Duty_Offset_Calibration]
2401 23:19:19.646409 B0:1 B1:0 CA:0
2402 23:19:19.646774
2403 23:19:19.649637 [DutyScan_Calibration_Flow] k_type=0
2404 23:19:19.659162
2405 23:19:19.659716 ==CLK 0==
2406 23:19:19.661956 Final CLK duty delay cell = -4
2407 23:19:19.665016 [-4] MAX Duty = 5031%(X100), DQS PI = 24
2408 23:19:19.668384 [-4] MIN Duty = 4875%(X100), DQS PI = 50
2409 23:19:19.672446 [-4] AVG Duty = 4953%(X100)
2410 23:19:19.673004
2411 23:19:19.674818 CH1 CLK Duty spec in!! Max-Min= 156%
2412 23:19:19.678545 [DutyScan_Calibration_Flow] ====Done====
2413 23:19:19.679012
2414 23:19:19.681562 [DutyScan_Calibration_Flow] k_type=1
2415 23:19:19.698582
2416 23:19:19.699279 ==DQS 0 ==
2417 23:19:19.701745 Final DQS duty delay cell = 0
2418 23:19:19.704833 [0] MAX Duty = 5094%(X100), DQS PI = 24
2419 23:19:19.708253 [0] MIN Duty = 4844%(X100), DQS PI = 0
2420 23:19:19.708815 [0] AVG Duty = 4969%(X100)
2421 23:19:19.711310
2422 23:19:19.711768 ==DQS 1 ==
2423 23:19:19.714526 Final DQS duty delay cell = 0
2424 23:19:19.718275 [0] MAX Duty = 5218%(X100), DQS PI = 20
2425 23:19:19.721492 [0] MIN Duty = 4969%(X100), DQS PI = 8
2426 23:19:19.722113 [0] AVG Duty = 5093%(X100)
2427 23:19:19.725070
2428 23:19:19.728481 CH1 DQS 0 Duty spec in!! Max-Min= 250%
2429 23:19:19.729037
2430 23:19:19.731624 CH1 DQS 1 Duty spec in!! Max-Min= 249%
2431 23:19:19.735047 [DutyScan_Calibration_Flow] ====Done====
2432 23:19:19.735646
2433 23:19:19.738434 [DutyScan_Calibration_Flow] k_type=3
2434 23:19:19.754758
2435 23:19:19.755314 ==DQM 0 ==
2436 23:19:19.758483 Final DQM duty delay cell = 0
2437 23:19:19.761686 [0] MAX Duty = 5156%(X100), DQS PI = 6
2438 23:19:19.764575 [0] MIN Duty = 5031%(X100), DQS PI = 0
2439 23:19:19.765132 [0] AVG Duty = 5093%(X100)
2440 23:19:19.767941
2441 23:19:19.768489 ==DQM 1 ==
2442 23:19:19.771291 Final DQM duty delay cell = 0
2443 23:19:19.774597 [0] MAX Duty = 5031%(X100), DQS PI = 16
2444 23:19:19.778079 [0] MIN Duty = 4907%(X100), DQS PI = 34
2445 23:19:19.778541 [0] AVG Duty = 4969%(X100)
2446 23:19:19.778907
2447 23:19:19.785004 CH1 DQM 0 Duty spec in!! Max-Min= 125%
2448 23:19:19.785562
2449 23:19:19.788749 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2450 23:19:19.791189 [DutyScan_Calibration_Flow] ====Done====
2451 23:19:19.791651
2452 23:19:19.794302 [DutyScan_Calibration_Flow] k_type=2
2453 23:19:19.810585
2454 23:19:19.811140 ==DQ 0 ==
2455 23:19:19.813748 Final DQ duty delay cell = -4
2456 23:19:19.817672 [-4] MAX Duty = 5062%(X100), DQS PI = 8
2457 23:19:19.820403 [-4] MIN Duty = 4938%(X100), DQS PI = 0
2458 23:19:19.820865 [-4] AVG Duty = 5000%(X100)
2459 23:19:19.823795
2460 23:19:19.824345 ==DQ 1 ==
2461 23:19:19.827509 Final DQ duty delay cell = 0
2462 23:19:19.830590 [0] MAX Duty = 5125%(X100), DQS PI = 20
2463 23:19:19.834386 [0] MIN Duty = 4969%(X100), DQS PI = 12
2464 23:19:19.834943 [0] AVG Duty = 5047%(X100)
2465 23:19:19.835316
2466 23:19:19.837346 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2467 23:19:19.840669
2468 23:19:19.843873 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2469 23:19:19.847609 [DutyScan_Calibration_Flow] ====Done====
2470 23:19:19.850913 nWR fixed to 30
2471 23:19:19.851469 [ModeRegInit_LP4] CH0 RK0
2472 23:19:19.853537 [ModeRegInit_LP4] CH0 RK1
2473 23:19:19.857036 [ModeRegInit_LP4] CH1 RK0
2474 23:19:19.857499 [ModeRegInit_LP4] CH1 RK1
2475 23:19:19.860675 match AC timing 7
2476 23:19:19.864499 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2477 23:19:19.868186 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2478 23:19:19.873715 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2479 23:19:19.877381 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2480 23:19:19.884301 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2481 23:19:19.884865 ==
2482 23:19:19.887159 Dram Type= 6, Freq= 0, CH_0, rank 0
2483 23:19:19.890488 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2484 23:19:19.890988 ==
2485 23:19:19.897537 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2486 23:19:19.900801 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2487 23:19:19.910531 [CA 0] Center 39 (8~70) winsize 63
2488 23:19:19.913869 [CA 1] Center 39 (8~70) winsize 63
2489 23:19:19.917185 [CA 2] Center 35 (4~66) winsize 63
2490 23:19:19.920499 [CA 3] Center 34 (4~65) winsize 62
2491 23:19:19.923891 [CA 4] Center 33 (3~64) winsize 62
2492 23:19:19.927812 [CA 5] Center 32 (3~62) winsize 60
2493 23:19:19.928331
2494 23:19:19.930733 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2495 23:19:19.931194
2496 23:19:19.933873 [CATrainingPosCal] consider 1 rank data
2497 23:19:19.937463 u2DelayCellTimex100 = 270/100 ps
2498 23:19:19.940823 CA0 delay=39 (8~70),Diff = 7 PI (33 cell)
2499 23:19:19.944186 CA1 delay=39 (8~70),Diff = 7 PI (33 cell)
2500 23:19:19.947929 CA2 delay=35 (4~66),Diff = 3 PI (14 cell)
2501 23:19:19.954157 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2502 23:19:19.957462 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2503 23:19:19.961046 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2504 23:19:19.961634
2505 23:19:19.964403 CA PerBit enable=1, Macro0, CA PI delay=32
2506 23:19:19.964993
2507 23:19:19.967808 [CBTSetCACLKResult] CA Dly = 32
2508 23:19:19.968454 CS Dly: 6 (0~37)
2509 23:19:19.968833 ==
2510 23:19:19.971009 Dram Type= 6, Freq= 0, CH_0, rank 1
2511 23:19:19.977690 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2512 23:19:19.978160 ==
2513 23:19:19.981455 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2514 23:19:19.987734 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2515 23:19:19.996331 [CA 0] Center 38 (8~69) winsize 62
2516 23:19:20.000074 [CA 1] Center 38 (8~69) winsize 62
2517 23:19:20.002846 [CA 2] Center 35 (4~66) winsize 63
2518 23:19:20.006332 [CA 3] Center 34 (4~65) winsize 62
2519 23:19:20.010006 [CA 4] Center 33 (3~64) winsize 62
2520 23:19:20.013327 [CA 5] Center 32 (3~62) winsize 60
2521 23:19:20.013860
2522 23:19:20.016376 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2523 23:19:20.016834
2524 23:19:20.019483 [CATrainingPosCal] consider 2 rank data
2525 23:19:20.023225 u2DelayCellTimex100 = 270/100 ps
2526 23:19:20.026982 CA0 delay=38 (8~69),Diff = 6 PI (28 cell)
2527 23:19:20.030198 CA1 delay=38 (8~69),Diff = 6 PI (28 cell)
2528 23:19:20.036392 CA2 delay=35 (4~66),Diff = 3 PI (14 cell)
2529 23:19:20.040042 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2530 23:19:20.043195 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2531 23:19:20.046594 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2532 23:19:20.047155
2533 23:19:20.049939 CA PerBit enable=1, Macro0, CA PI delay=32
2534 23:19:20.050499
2535 23:19:20.053469 [CBTSetCACLKResult] CA Dly = 32
2536 23:19:20.054064 CS Dly: 6 (0~38)
2537 23:19:20.054435
2538 23:19:20.056765 ----->DramcWriteLeveling(PI) begin...
2539 23:19:20.057386 ==
2540 23:19:20.060237 Dram Type= 6, Freq= 0, CH_0, rank 0
2541 23:19:20.066565 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2542 23:19:20.067128 ==
2543 23:19:20.069948 Write leveling (Byte 0): 33 => 33
2544 23:19:20.073464 Write leveling (Byte 1): 29 => 29
2545 23:19:20.076642 DramcWriteLeveling(PI) end<-----
2546 23:19:20.077103
2547 23:19:20.077465 ==
2548 23:19:20.080389 Dram Type= 6, Freq= 0, CH_0, rank 0
2549 23:19:20.083169 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2550 23:19:20.083736 ==
2551 23:19:20.086331 [Gating] SW mode calibration
2552 23:19:20.092897 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2553 23:19:20.099553 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2554 23:19:20.103004 0 15 0 | B1->B0 | 2323 3131 | 0 1 | (0 0) (1 1)
2555 23:19:20.106478 0 15 4 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
2556 23:19:20.109868 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2557 23:19:20.116340 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2558 23:19:20.119460 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2559 23:19:20.122936 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2560 23:19:20.130015 0 15 24 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
2561 23:19:20.132536 0 15 28 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
2562 23:19:20.136549 1 0 0 | B1->B0 | 2b2b 2323 | 0 0 | (1 0) (0 0)
2563 23:19:20.142934 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2564 23:19:20.146298 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2565 23:19:20.149848 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2566 23:19:20.156378 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2567 23:19:20.159689 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2568 23:19:20.163306 1 0 24 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
2569 23:19:20.170018 1 0 28 | B1->B0 | 2727 4545 | 0 0 | (0 0) (0 0)
2570 23:19:20.173222 1 1 0 | B1->B0 | 3333 4545 | 0 0 | (0 0) (0 0)
2571 23:19:20.175988 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2572 23:19:20.183142 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2573 23:19:20.186338 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2574 23:19:20.189568 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2575 23:19:20.193186 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2576 23:19:20.199558 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2577 23:19:20.203314 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2578 23:19:20.206247 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2579 23:19:20.212811 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2580 23:19:20.216625 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2581 23:19:20.219729 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2582 23:19:20.226286 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2583 23:19:20.229639 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2584 23:19:20.233364 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2585 23:19:20.240276 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2586 23:19:20.243452 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2587 23:19:20.246708 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2588 23:19:20.253538 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2589 23:19:20.256673 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2590 23:19:20.260467 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2591 23:19:20.262956 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2592 23:19:20.269776 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2593 23:19:20.273618 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2594 23:19:20.276912 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2595 23:19:20.279837 Total UI for P1: 0, mck2ui 16
2596 23:19:20.283547 best dqsien dly found for B0: ( 1, 3, 28)
2597 23:19:20.289895 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2598 23:19:20.290549 Total UI for P1: 0, mck2ui 16
2599 23:19:20.296853 best dqsien dly found for B1: ( 1, 3, 30)
2600 23:19:20.300078 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2601 23:19:20.303499 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2602 23:19:20.303962
2603 23:19:20.306863 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2604 23:19:20.310586 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2605 23:19:20.313391 [Gating] SW calibration Done
2606 23:19:20.313995 ==
2607 23:19:20.316586 Dram Type= 6, Freq= 0, CH_0, rank 0
2608 23:19:20.320511 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2609 23:19:20.321084 ==
2610 23:19:20.324035 RX Vref Scan: 0
2611 23:19:20.324595
2612 23:19:20.324959 RX Vref 0 -> 0, step: 1
2613 23:19:20.325299
2614 23:19:20.326512 RX Delay -40 -> 252, step: 8
2615 23:19:20.329916 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2616 23:19:20.336907 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2617 23:19:20.340424 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2618 23:19:20.343454 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2619 23:19:20.347281 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2620 23:19:20.350583 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2621 23:19:20.356738 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2622 23:19:20.360270 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2623 23:19:20.363790 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2624 23:19:20.367082 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
2625 23:19:20.370517 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2626 23:19:20.373747 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2627 23:19:20.380112 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2628 23:19:20.383631 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2629 23:19:20.387395 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2630 23:19:20.390241 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2631 23:19:20.390702 ==
2632 23:19:20.393309 Dram Type= 6, Freq= 0, CH_0, rank 0
2633 23:19:20.399872 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2634 23:19:20.400390 ==
2635 23:19:20.400768 DQS Delay:
2636 23:19:20.403612 DQS0 = 0, DQS1 = 0
2637 23:19:20.404125 DQM Delay:
2638 23:19:20.404497 DQM0 = 121, DQM1 = 113
2639 23:19:20.407221 DQ Delay:
2640 23:19:20.409871 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2641 23:19:20.414111 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2642 23:19:20.416674 DQ8 =99, DQ9 =107, DQ10 =111, DQ11 =107
2643 23:19:20.420365 DQ12 =119, DQ13 =123, DQ14 =123, DQ15 =119
2644 23:19:20.420827
2645 23:19:20.421194
2646 23:19:20.421534 ==
2647 23:19:20.423731 Dram Type= 6, Freq= 0, CH_0, rank 0
2648 23:19:20.427049 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2649 23:19:20.430272 ==
2650 23:19:20.430998
2651 23:19:20.431377
2652 23:19:20.431719 TX Vref Scan disable
2653 23:19:20.433699 == TX Byte 0 ==
2654 23:19:20.436901 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2655 23:19:20.440402 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2656 23:19:20.443386 == TX Byte 1 ==
2657 23:19:20.447417 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2658 23:19:20.450320 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2659 23:19:20.450787 ==
2660 23:19:20.453732 Dram Type= 6, Freq= 0, CH_0, rank 0
2661 23:19:20.460481 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2662 23:19:20.461055 ==
2663 23:19:20.471153 TX Vref=22, minBit 0, minWin=25, winSum=409
2664 23:19:20.474585 TX Vref=24, minBit 0, minWin=25, winSum=412
2665 23:19:20.477765 TX Vref=26, minBit 0, minWin=26, winSum=421
2666 23:19:20.481428 TX Vref=28, minBit 7, minWin=25, winSum=423
2667 23:19:20.484647 TX Vref=30, minBit 1, minWin=26, winSum=424
2668 23:19:20.491179 TX Vref=32, minBit 0, minWin=26, winSum=422
2669 23:19:20.494500 [TxChooseVref] Worse bit 1, Min win 26, Win sum 424, Final Vref 30
2670 23:19:20.494967
2671 23:19:20.497811 Final TX Range 1 Vref 30
2672 23:19:20.498275
2673 23:19:20.498639 ==
2674 23:19:20.501451 Dram Type= 6, Freq= 0, CH_0, rank 0
2675 23:19:20.504938 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2676 23:19:20.505504 ==
2677 23:19:20.505960
2678 23:19:20.508189
2679 23:19:20.508823 TX Vref Scan disable
2680 23:19:20.511096 == TX Byte 0 ==
2681 23:19:20.514390 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2682 23:19:20.517984 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2683 23:19:20.521376 == TX Byte 1 ==
2684 23:19:20.524777 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2685 23:19:20.527557 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2686 23:19:20.527972
2687 23:19:20.531279 [DATLAT]
2688 23:19:20.531691 Freq=1200, CH0 RK0
2689 23:19:20.532020
2690 23:19:20.534733 DATLAT Default: 0xd
2691 23:19:20.535251 0, 0xFFFF, sum = 0
2692 23:19:20.537721 1, 0xFFFF, sum = 0
2693 23:19:20.538237 2, 0xFFFF, sum = 0
2694 23:19:20.541481 3, 0xFFFF, sum = 0
2695 23:19:20.542060 4, 0xFFFF, sum = 0
2696 23:19:20.544647 5, 0xFFFF, sum = 0
2697 23:19:20.545173 6, 0xFFFF, sum = 0
2698 23:19:20.548183 7, 0xFFFF, sum = 0
2699 23:19:20.548708 8, 0xFFFF, sum = 0
2700 23:19:20.550900 9, 0xFFFF, sum = 0
2701 23:19:20.554723 10, 0xFFFF, sum = 0
2702 23:19:20.555250 11, 0xFFFF, sum = 0
2703 23:19:20.557869 12, 0x0, sum = 1
2704 23:19:20.558449 13, 0x0, sum = 2
2705 23:19:20.558802 14, 0x0, sum = 3
2706 23:19:20.561721 15, 0x0, sum = 4
2707 23:19:20.562245 best_step = 13
2708 23:19:20.562577
2709 23:19:20.562889 ==
2710 23:19:20.564597 Dram Type= 6, Freq= 0, CH_0, rank 0
2711 23:19:20.571327 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2712 23:19:20.571885 ==
2713 23:19:20.572230 RX Vref Scan: 1
2714 23:19:20.572539
2715 23:19:20.574905 Set Vref Range= 32 -> 127
2716 23:19:20.575422
2717 23:19:20.578369 RX Vref 32 -> 127, step: 1
2718 23:19:20.579016
2719 23:19:20.581345 RX Delay -13 -> 252, step: 4
2720 23:19:20.581906
2721 23:19:20.585194 Set Vref, RX VrefLevel [Byte0]: 32
2722 23:19:20.588001 [Byte1]: 32
2723 23:19:20.588517
2724 23:19:20.591098 Set Vref, RX VrefLevel [Byte0]: 33
2725 23:19:20.594970 [Byte1]: 33
2726 23:19:20.595489
2727 23:19:20.597760 Set Vref, RX VrefLevel [Byte0]: 34
2728 23:19:20.601483 [Byte1]: 34
2729 23:19:20.605192
2730 23:19:20.605760 Set Vref, RX VrefLevel [Byte0]: 35
2731 23:19:20.609348 [Byte1]: 35
2732 23:19:20.613647
2733 23:19:20.614165 Set Vref, RX VrefLevel [Byte0]: 36
2734 23:19:20.616412 [Byte1]: 36
2735 23:19:20.621227
2736 23:19:20.621792 Set Vref, RX VrefLevel [Byte0]: 37
2737 23:19:20.624796 [Byte1]: 37
2738 23:19:20.628863
2739 23:19:20.629376 Set Vref, RX VrefLevel [Byte0]: 38
2740 23:19:20.632072 [Byte1]: 38
2741 23:19:20.636949
2742 23:19:20.637456 Set Vref, RX VrefLevel [Byte0]: 39
2743 23:19:20.640538 [Byte1]: 39
2744 23:19:20.645086
2745 23:19:20.645644 Set Vref, RX VrefLevel [Byte0]: 40
2746 23:19:20.647960 [Byte1]: 40
2747 23:19:20.652774
2748 23:19:20.653285 Set Vref, RX VrefLevel [Byte0]: 41
2749 23:19:20.656501 [Byte1]: 41
2750 23:19:20.660759
2751 23:19:20.661276 Set Vref, RX VrefLevel [Byte0]: 42
2752 23:19:20.663879 [Byte1]: 42
2753 23:19:20.668222
2754 23:19:20.668732 Set Vref, RX VrefLevel [Byte0]: 43
2755 23:19:20.671682 [Byte1]: 43
2756 23:19:20.676396
2757 23:19:20.676905 Set Vref, RX VrefLevel [Byte0]: 44
2758 23:19:20.679271 [Byte1]: 44
2759 23:19:20.684214
2760 23:19:20.684755 Set Vref, RX VrefLevel [Byte0]: 45
2761 23:19:20.687701 [Byte1]: 45
2762 23:19:20.692167
2763 23:19:20.692605 Set Vref, RX VrefLevel [Byte0]: 46
2764 23:19:20.695684 [Byte1]: 46
2765 23:19:20.699969
2766 23:19:20.700445 Set Vref, RX VrefLevel [Byte0]: 47
2767 23:19:20.703583 [Byte1]: 47
2768 23:19:20.707877
2769 23:19:20.708435 Set Vref, RX VrefLevel [Byte0]: 48
2770 23:19:20.711945 [Byte1]: 48
2771 23:19:20.716005
2772 23:19:20.716567 Set Vref, RX VrefLevel [Byte0]: 49
2773 23:19:20.719155 [Byte1]: 49
2774 23:19:20.723887
2775 23:19:20.724448 Set Vref, RX VrefLevel [Byte0]: 50
2776 23:19:20.727385 [Byte1]: 50
2777 23:19:20.731706
2778 23:19:20.732261 Set Vref, RX VrefLevel [Byte0]: 51
2779 23:19:20.734537 [Byte1]: 51
2780 23:19:20.739212
2781 23:19:20.739769 Set Vref, RX VrefLevel [Byte0]: 52
2782 23:19:20.742552 [Byte1]: 52
2783 23:19:20.747163
2784 23:19:20.747714 Set Vref, RX VrefLevel [Byte0]: 53
2785 23:19:20.750494 [Byte1]: 53
2786 23:19:20.755211
2787 23:19:20.755777 Set Vref, RX VrefLevel [Byte0]: 54
2788 23:19:20.758585 [Byte1]: 54
2789 23:19:20.763301
2790 23:19:20.763889 Set Vref, RX VrefLevel [Byte0]: 55
2791 23:19:20.766782 [Byte1]: 55
2792 23:19:20.770859
2793 23:19:20.771477 Set Vref, RX VrefLevel [Byte0]: 56
2794 23:19:20.774271 [Byte1]: 56
2795 23:19:20.779055
2796 23:19:20.779805 Set Vref, RX VrefLevel [Byte0]: 57
2797 23:19:20.782033 [Byte1]: 57
2798 23:19:20.787070
2799 23:19:20.787636 Set Vref, RX VrefLevel [Byte0]: 58
2800 23:19:20.790363 [Byte1]: 58
2801 23:19:20.794282
2802 23:19:20.794745 Set Vref, RX VrefLevel [Byte0]: 59
2803 23:19:20.797874 [Byte1]: 59
2804 23:19:20.802308
2805 23:19:20.802870 Set Vref, RX VrefLevel [Byte0]: 60
2806 23:19:20.805641 [Byte1]: 60
2807 23:19:20.810475
2808 23:19:20.811045 Set Vref, RX VrefLevel [Byte0]: 61
2809 23:19:20.813730 [Byte1]: 61
2810 23:19:20.818300
2811 23:19:20.818872 Set Vref, RX VrefLevel [Byte0]: 62
2812 23:19:20.821871 [Byte1]: 62
2813 23:19:20.825963
2814 23:19:20.826430 Set Vref, RX VrefLevel [Byte0]: 63
2815 23:19:20.829743 [Byte1]: 63
2816 23:19:20.834363
2817 23:19:20.834930 Set Vref, RX VrefLevel [Byte0]: 64
2818 23:19:20.837555 [Byte1]: 64
2819 23:19:20.842071
2820 23:19:20.842636 Set Vref, RX VrefLevel [Byte0]: 65
2821 23:19:20.845620 [Byte1]: 65
2822 23:19:20.849782
2823 23:19:20.850345 Set Vref, RX VrefLevel [Byte0]: 66
2824 23:19:20.853130 [Byte1]: 66
2825 23:19:20.858092
2826 23:19:20.858659 Set Vref, RX VrefLevel [Byte0]: 67
2827 23:19:20.861534 [Byte1]: 67
2828 23:19:20.865874
2829 23:19:20.866451 Set Vref, RX VrefLevel [Byte0]: 68
2830 23:19:20.869742 [Byte1]: 68
2831 23:19:20.873543
2832 23:19:20.874046 Set Vref, RX VrefLevel [Byte0]: 69
2833 23:19:20.876956 [Byte1]: 69
2834 23:19:20.881499
2835 23:19:20.881999 Final RX Vref Byte 0 = 60 to rank0
2836 23:19:20.885047 Final RX Vref Byte 1 = 48 to rank0
2837 23:19:20.888252 Final RX Vref Byte 0 = 60 to rank1
2838 23:19:20.891496 Final RX Vref Byte 1 = 48 to rank1==
2839 23:19:20.894348 Dram Type= 6, Freq= 0, CH_0, rank 0
2840 23:19:20.901363 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2841 23:19:20.902061 ==
2842 23:19:20.902445 DQS Delay:
2843 23:19:20.902792 DQS0 = 0, DQS1 = 0
2844 23:19:20.905011 DQM Delay:
2845 23:19:20.905808 DQM0 = 121, DQM1 = 111
2846 23:19:20.908112 DQ Delay:
2847 23:19:20.911355 DQ0 =118, DQ1 =122, DQ2 =120, DQ3 =120
2848 23:19:20.914780 DQ4 =122, DQ5 =116, DQ6 =126, DQ7 =126
2849 23:19:20.918222 DQ8 =100, DQ9 =100, DQ10 =112, DQ11 =106
2850 23:19:20.921196 DQ12 =116, DQ13 =116, DQ14 =124, DQ15 =118
2851 23:19:20.922109
2852 23:19:20.922883
2853 23:19:20.927797 [DQSOSCAuto] RK0, (LSB)MR18= 0x130c, (MSB)MR19= 0x404, tDQSOscB0 = 405 ps tDQSOscB1 = 402 ps
2854 23:19:20.931317 CH0 RK0: MR19=404, MR18=130C
2855 23:19:20.938007 CH0_RK0: MR19=0x404, MR18=0x130C, DQSOSC=402, MR23=63, INC=40, DEC=27
2856 23:19:20.938577
2857 23:19:20.941556 ----->DramcWriteLeveling(PI) begin...
2858 23:19:20.942182 ==
2859 23:19:20.944973 Dram Type= 6, Freq= 0, CH_0, rank 1
2860 23:19:20.947588 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2861 23:19:20.951377 ==
2862 23:19:20.951622 Write leveling (Byte 0): 33 => 33
2863 23:19:20.954611 Write leveling (Byte 1): 29 => 29
2864 23:19:20.958068 DramcWriteLeveling(PI) end<-----
2865 23:19:20.958401
2866 23:19:20.958608 ==
2867 23:19:20.961417 Dram Type= 6, Freq= 0, CH_0, rank 1
2868 23:19:20.968428 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2869 23:19:20.968770 ==
2870 23:19:20.968981 [Gating] SW mode calibration
2871 23:19:20.977862 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2872 23:19:20.980978 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2873 23:19:20.984684 0 15 0 | B1->B0 | 3333 2f2f | 0 0 | (0 0) (0 0)
2874 23:19:20.991816 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2875 23:19:20.995245 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2876 23:19:20.998414 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2877 23:19:21.005155 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2878 23:19:21.008188 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2879 23:19:21.012004 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 0)
2880 23:19:21.018627 0 15 28 | B1->B0 | 3232 3131 | 1 1 | (1 0) (1 1)
2881 23:19:21.021991 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2882 23:19:21.025147 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2883 23:19:21.031808 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2884 23:19:21.034937 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2885 23:19:21.038529 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2886 23:19:21.045235 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2887 23:19:21.048432 1 0 24 | B1->B0 | 2626 2626 | 1 0 | (0 0) (0 0)
2888 23:19:21.052171 1 0 28 | B1->B0 | 3c3c 3c3c | 0 0 | (0 0) (1 1)
2889 23:19:21.058589 1 1 0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
2890 23:19:21.061745 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2891 23:19:21.065429 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2892 23:19:21.068953 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2893 23:19:21.075224 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2894 23:19:21.078429 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2895 23:19:21.081680 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
2896 23:19:21.088609 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2897 23:19:21.092017 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2898 23:19:21.095325 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2899 23:19:21.101849 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2900 23:19:21.104658 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2901 23:19:21.108040 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2902 23:19:21.115058 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2903 23:19:21.118178 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2904 23:19:21.121451 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2905 23:19:21.128218 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2906 23:19:21.131689 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2907 23:19:21.134896 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2908 23:19:21.141978 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2909 23:19:21.145424 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2910 23:19:21.148256 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2911 23:19:21.154915 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2912 23:19:21.158269 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2913 23:19:21.161527 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2914 23:19:21.164942 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2915 23:19:21.168430 Total UI for P1: 0, mck2ui 16
2916 23:19:21.171470 best dqsien dly found for B0: ( 1, 3, 30)
2917 23:19:21.175363 Total UI for P1: 0, mck2ui 16
2918 23:19:21.178855 best dqsien dly found for B1: ( 1, 3, 30)
2919 23:19:21.181655 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2920 23:19:21.184977 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2921 23:19:21.188220
2922 23:19:21.191980 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2923 23:19:21.195232 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2924 23:19:21.198061 [Gating] SW calibration Done
2925 23:19:21.198528 ==
2926 23:19:21.201378 Dram Type= 6, Freq= 0, CH_0, rank 1
2927 23:19:21.205004 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2928 23:19:21.205628 ==
2929 23:19:21.206031 RX Vref Scan: 0
2930 23:19:21.206384
2931 23:19:21.208159 RX Vref 0 -> 0, step: 1
2932 23:19:21.208624
2933 23:19:21.211746 RX Delay -40 -> 252, step: 8
2934 23:19:21.215065 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2935 23:19:21.218163 iDelay=200, Bit 1, Center 123 (56 ~ 191) 136
2936 23:19:21.225084 iDelay=200, Bit 2, Center 123 (56 ~ 191) 136
2937 23:19:21.228785 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2938 23:19:21.232043 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
2939 23:19:21.235097 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2940 23:19:21.238414 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2941 23:19:21.241667 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2942 23:19:21.248843 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2943 23:19:21.252458 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
2944 23:19:21.256206 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2945 23:19:21.258472 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2946 23:19:21.262338 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2947 23:19:21.268864 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2948 23:19:21.272298 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2949 23:19:21.275452 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
2950 23:19:21.275920 ==
2951 23:19:21.278942 Dram Type= 6, Freq= 0, CH_0, rank 1
2952 23:19:21.281656 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2953 23:19:21.282151 ==
2954 23:19:21.285164 DQS Delay:
2955 23:19:21.285785 DQS0 = 0, DQS1 = 0
2956 23:19:21.288890 DQM Delay:
2957 23:19:21.289471 DQM0 = 122, DQM1 = 112
2958 23:19:21.292154 DQ Delay:
2959 23:19:21.294838 DQ0 =119, DQ1 =123, DQ2 =123, DQ3 =119
2960 23:19:21.298587 DQ4 =123, DQ5 =115, DQ6 =127, DQ7 =127
2961 23:19:21.301763 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
2962 23:19:21.305421 DQ12 =115, DQ13 =119, DQ14 =123, DQ15 =123
2963 23:19:21.306065
2964 23:19:21.306459
2965 23:19:21.306804 ==
2966 23:19:21.308892 Dram Type= 6, Freq= 0, CH_0, rank 1
2967 23:19:21.312321 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2968 23:19:21.312969 ==
2969 23:19:21.313351
2970 23:19:21.313756
2971 23:19:21.314930 TX Vref Scan disable
2972 23:19:21.318576 == TX Byte 0 ==
2973 23:19:21.322036 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2974 23:19:21.325228 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2975 23:19:21.328903 == TX Byte 1 ==
2976 23:19:21.331876 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2977 23:19:21.335162 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2978 23:19:21.335683 ==
2979 23:19:21.338745 Dram Type= 6, Freq= 0, CH_0, rank 1
2980 23:19:21.342110 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2981 23:19:21.345610 ==
2982 23:19:21.355666 TX Vref=22, minBit 1, minWin=25, winSum=420
2983 23:19:21.359029 TX Vref=24, minBit 3, minWin=25, winSum=421
2984 23:19:21.362543 TX Vref=26, minBit 3, minWin=25, winSum=425
2985 23:19:21.366028 TX Vref=28, minBit 0, minWin=26, winSum=428
2986 23:19:21.369326 TX Vref=30, minBit 1, minWin=26, winSum=430
2987 23:19:21.372267 TX Vref=32, minBit 0, minWin=26, winSum=428
2988 23:19:21.378956 [TxChooseVref] Worse bit 1, Min win 26, Win sum 430, Final Vref 30
2989 23:19:21.379527
2990 23:19:21.382112 Final TX Range 1 Vref 30
2991 23:19:21.382583
2992 23:19:21.382956 ==
2993 23:19:21.385790 Dram Type= 6, Freq= 0, CH_0, rank 1
2994 23:19:21.389153 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2995 23:19:21.389773 ==
2996 23:19:21.390156
2997 23:19:21.390504
2998 23:19:21.392283 TX Vref Scan disable
2999 23:19:21.395578 == TX Byte 0 ==
3000 23:19:21.399368 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
3001 23:19:21.402575 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
3002 23:19:21.406236 == TX Byte 1 ==
3003 23:19:21.409194 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3004 23:19:21.412749 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3005 23:19:21.413344
3006 23:19:21.415677 [DATLAT]
3007 23:19:21.416140 Freq=1200, CH0 RK1
3008 23:19:21.416515
3009 23:19:21.419201 DATLAT Default: 0xd
3010 23:19:21.419669 0, 0xFFFF, sum = 0
3011 23:19:21.422329 1, 0xFFFF, sum = 0
3012 23:19:21.422810 2, 0xFFFF, sum = 0
3013 23:19:21.426466 3, 0xFFFF, sum = 0
3014 23:19:21.427041 4, 0xFFFF, sum = 0
3015 23:19:21.429333 5, 0xFFFF, sum = 0
3016 23:19:21.429971 6, 0xFFFF, sum = 0
3017 23:19:21.432777 7, 0xFFFF, sum = 0
3018 23:19:21.433385 8, 0xFFFF, sum = 0
3019 23:19:21.435929 9, 0xFFFF, sum = 0
3020 23:19:21.436403 10, 0xFFFF, sum = 0
3021 23:19:21.439444 11, 0xFFFF, sum = 0
3022 23:19:21.439918 12, 0x0, sum = 1
3023 23:19:21.442712 13, 0x0, sum = 2
3024 23:19:21.443311 14, 0x0, sum = 3
3025 23:19:21.446703 15, 0x0, sum = 4
3026 23:19:21.447286 best_step = 13
3027 23:19:21.447658
3028 23:19:21.448001 ==
3029 23:19:21.449175 Dram Type= 6, Freq= 0, CH_0, rank 1
3030 23:19:21.456018 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3031 23:19:21.456592 ==
3032 23:19:21.457041 RX Vref Scan: 0
3033 23:19:21.457519
3034 23:19:21.459472 RX Vref 0 -> 0, step: 1
3035 23:19:21.459958
3036 23:19:21.462542 RX Delay -13 -> 252, step: 4
3037 23:19:21.466619 iDelay=195, Bit 0, Center 122 (55 ~ 190) 136
3038 23:19:21.469500 iDelay=195, Bit 1, Center 122 (59 ~ 186) 128
3039 23:19:21.476208 iDelay=195, Bit 2, Center 116 (51 ~ 182) 132
3040 23:19:21.479574 iDelay=195, Bit 3, Center 118 (51 ~ 186) 136
3041 23:19:21.482789 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3042 23:19:21.485946 iDelay=195, Bit 5, Center 116 (51 ~ 182) 132
3043 23:19:21.489670 iDelay=195, Bit 6, Center 128 (63 ~ 194) 132
3044 23:19:21.492708 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3045 23:19:21.499836 iDelay=195, Bit 8, Center 100 (35 ~ 166) 132
3046 23:19:21.502903 iDelay=195, Bit 9, Center 96 (31 ~ 162) 132
3047 23:19:21.506184 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3048 23:19:21.510253 iDelay=195, Bit 11, Center 102 (39 ~ 166) 128
3049 23:19:21.512977 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3050 23:19:21.519466 iDelay=195, Bit 13, Center 116 (55 ~ 178) 124
3051 23:19:21.522721 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3052 23:19:21.526248 iDelay=195, Bit 15, Center 120 (55 ~ 186) 132
3053 23:19:21.526819 ==
3054 23:19:21.529885 Dram Type= 6, Freq= 0, CH_0, rank 1
3055 23:19:21.532972 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3056 23:19:21.533552 ==
3057 23:19:21.536591 DQS Delay:
3058 23:19:21.537161 DQS0 = 0, DQS1 = 0
3059 23:19:21.539889 DQM Delay:
3060 23:19:21.540456 DQM0 = 121, DQM1 = 110
3061 23:19:21.542482 DQ Delay:
3062 23:19:21.546238 DQ0 =122, DQ1 =122, DQ2 =116, DQ3 =118
3063 23:19:21.549789 DQ4 =122, DQ5 =116, DQ6 =128, DQ7 =126
3064 23:19:21.553211 DQ8 =100, DQ9 =96, DQ10 =110, DQ11 =102
3065 23:19:21.556247 DQ12 =114, DQ13 =116, DQ14 =122, DQ15 =120
3066 23:19:21.556818
3067 23:19:21.557189
3068 23:19:21.563393 [DQSOSCAuto] RK1, (LSB)MR18= 0xdee, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 405 ps
3069 23:19:21.566355 CH0 RK1: MR19=403, MR18=DEE
3070 23:19:21.573140 CH0_RK1: MR19=0x403, MR18=0xDEE, DQSOSC=405, MR23=63, INC=39, DEC=26
3071 23:19:21.576517 [RxdqsGatingPostProcess] freq 1200
3072 23:19:21.579368 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3073 23:19:21.583195 best DQS0 dly(2T, 0.5T) = (0, 11)
3074 23:19:21.585944 best DQS1 dly(2T, 0.5T) = (0, 11)
3075 23:19:21.589453 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3076 23:19:21.593074 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3077 23:19:21.596156 best DQS0 dly(2T, 0.5T) = (0, 11)
3078 23:19:21.599631 best DQS1 dly(2T, 0.5T) = (0, 11)
3079 23:19:21.602711 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3080 23:19:21.606013 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3081 23:19:21.609433 Pre-setting of DQS Precalculation
3082 23:19:21.613066 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3083 23:19:21.615884 ==
3084 23:19:21.616349 Dram Type= 6, Freq= 0, CH_1, rank 0
3085 23:19:21.622828 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3086 23:19:21.623335 ==
3087 23:19:21.626629 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3088 23:19:21.633010 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
3089 23:19:21.641887 [CA 0] Center 37 (7~68) winsize 62
3090 23:19:21.645513 [CA 1] Center 37 (7~68) winsize 62
3091 23:19:21.648860 [CA 2] Center 35 (5~65) winsize 61
3092 23:19:21.652206 [CA 3] Center 34 (4~64) winsize 61
3093 23:19:21.655375 [CA 4] Center 34 (5~64) winsize 60
3094 23:19:21.658732 [CA 5] Center 33 (3~63) winsize 61
3095 23:19:21.659318
3096 23:19:21.661782 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3097 23:19:21.662267
3098 23:19:21.665483 [CATrainingPosCal] consider 1 rank data
3099 23:19:21.669223 u2DelayCellTimex100 = 270/100 ps
3100 23:19:21.672093 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3101 23:19:21.675755 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3102 23:19:21.678804 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3103 23:19:21.685284 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3104 23:19:21.688812 CA4 delay=34 (5~64),Diff = 1 PI (4 cell)
3105 23:19:21.692095 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3106 23:19:21.692682
3107 23:19:21.695867 CA PerBit enable=1, Macro0, CA PI delay=33
3108 23:19:21.696450
3109 23:19:21.698364 [CBTSetCACLKResult] CA Dly = 33
3110 23:19:21.698849 CS Dly: 8 (0~39)
3111 23:19:21.699341 ==
3112 23:19:21.701712 Dram Type= 6, Freq= 0, CH_1, rank 1
3113 23:19:21.708197 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3114 23:19:21.708679 ==
3115 23:19:21.711969 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3116 23:19:21.718596 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3117 23:19:21.727293 [CA 0] Center 37 (7~68) winsize 62
3118 23:19:21.730887 [CA 1] Center 37 (7~68) winsize 62
3119 23:19:21.733781 [CA 2] Center 35 (5~65) winsize 61
3120 23:19:21.737402 [CA 3] Center 34 (4~65) winsize 62
3121 23:19:21.741023 [CA 4] Center 34 (4~65) winsize 62
3122 23:19:21.744165 [CA 5] Center 34 (4~64) winsize 61
3123 23:19:21.744627
3124 23:19:21.747914 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3125 23:19:21.748478
3126 23:19:21.751180 [CATrainingPosCal] consider 2 rank data
3127 23:19:21.754248 u2DelayCellTimex100 = 270/100 ps
3128 23:19:21.757439 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3129 23:19:21.760804 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3130 23:19:21.767539 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3131 23:19:21.770828 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3132 23:19:21.774406 CA4 delay=34 (5~64),Diff = 1 PI (4 cell)
3133 23:19:21.777702 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3134 23:19:21.778261
3135 23:19:21.780681 CA PerBit enable=1, Macro0, CA PI delay=33
3136 23:19:21.781144
3137 23:19:21.784615 [CBTSetCACLKResult] CA Dly = 33
3138 23:19:21.785211 CS Dly: 9 (0~41)
3139 23:19:21.785628
3140 23:19:21.787589 ----->DramcWriteLeveling(PI) begin...
3141 23:19:21.790958 ==
3142 23:19:21.791517 Dram Type= 6, Freq= 0, CH_1, rank 0
3143 23:19:21.797558 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3144 23:19:21.798217 ==
3145 23:19:21.800957 Write leveling (Byte 0): 25 => 25
3146 23:19:21.804203 Write leveling (Byte 1): 28 => 28
3147 23:19:21.804669 DramcWriteLeveling(PI) end<-----
3148 23:19:21.807548
3149 23:19:21.808080 ==
3150 23:19:21.811125 Dram Type= 6, Freq= 0, CH_1, rank 0
3151 23:19:21.814259 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3152 23:19:21.814728 ==
3153 23:19:21.817631 [Gating] SW mode calibration
3154 23:19:21.824112 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3155 23:19:21.827432 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3156 23:19:21.834361 0 15 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
3157 23:19:21.837753 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3158 23:19:21.840688 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3159 23:19:21.847679 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3160 23:19:21.851309 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3161 23:19:21.854491 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3162 23:19:21.861217 0 15 24 | B1->B0 | 3333 3131 | 0 0 | (0 0) (0 1)
3163 23:19:21.864558 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3164 23:19:21.867770 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3165 23:19:21.874393 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3166 23:19:21.877982 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3167 23:19:21.881290 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3168 23:19:21.884804 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3169 23:19:21.891377 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3170 23:19:21.894368 1 0 24 | B1->B0 | 3737 4242 | 0 0 | (0 0) (0 0)
3171 23:19:21.898189 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3172 23:19:21.904277 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3173 23:19:21.907838 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3174 23:19:21.910739 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3175 23:19:21.917511 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3176 23:19:21.921227 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3177 23:19:21.924214 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3178 23:19:21.930894 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3179 23:19:21.934520 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3180 23:19:21.937745 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3181 23:19:21.944504 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3182 23:19:21.948208 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3183 23:19:21.950497 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3184 23:19:21.957057 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3185 23:19:21.960872 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3186 23:19:21.964046 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3187 23:19:21.971160 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3188 23:19:21.973811 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3189 23:19:21.977352 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3190 23:19:21.983885 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3191 23:19:21.987295 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3192 23:19:21.990839 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3193 23:19:21.994289 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3194 23:19:22.001151 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3195 23:19:22.004567 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3196 23:19:22.008010 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3197 23:19:22.010814 Total UI for P1: 0, mck2ui 16
3198 23:19:22.014134 best dqsien dly found for B0: ( 1, 3, 26)
3199 23:19:22.017685 Total UI for P1: 0, mck2ui 16
3200 23:19:22.020910 best dqsien dly found for B1: ( 1, 3, 26)
3201 23:19:22.024105 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3202 23:19:22.027649 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3203 23:19:22.028174
3204 23:19:22.034555 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3205 23:19:22.038103 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3206 23:19:22.038666 [Gating] SW calibration Done
3207 23:19:22.041204 ==
3208 23:19:22.044224 Dram Type= 6, Freq= 0, CH_1, rank 0
3209 23:19:22.047867 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3210 23:19:22.048432 ==
3211 23:19:22.048807 RX Vref Scan: 0
3212 23:19:22.049149
3213 23:19:22.051399 RX Vref 0 -> 0, step: 1
3214 23:19:22.051956
3215 23:19:22.054587 RX Delay -40 -> 252, step: 8
3216 23:19:22.058179 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3217 23:19:22.061689 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3218 23:19:22.064507 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3219 23:19:22.071191 iDelay=200, Bit 3, Center 123 (56 ~ 191) 136
3220 23:19:22.074912 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3221 23:19:22.077752 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3222 23:19:22.080902 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3223 23:19:22.084560 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
3224 23:19:22.091212 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3225 23:19:22.094493 iDelay=200, Bit 9, Center 103 (40 ~ 167) 128
3226 23:19:22.097545 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3227 23:19:22.101289 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3228 23:19:22.104452 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3229 23:19:22.110916 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3230 23:19:22.114945 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3231 23:19:22.117898 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3232 23:19:22.118359 ==
3233 23:19:22.121140 Dram Type= 6, Freq= 0, CH_1, rank 0
3234 23:19:22.124193 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3235 23:19:22.124657 ==
3236 23:19:22.127994 DQS Delay:
3237 23:19:22.128684 DQS0 = 0, DQS1 = 0
3238 23:19:22.131633 DQM Delay:
3239 23:19:22.132190 DQM0 = 121, DQM1 = 116
3240 23:19:22.134300 DQ Delay:
3241 23:19:22.137876 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =123
3242 23:19:22.141699 DQ4 =119, DQ5 =127, DQ6 =131, DQ7 =123
3243 23:19:22.144491 DQ8 =103, DQ9 =103, DQ10 =115, DQ11 =111
3244 23:19:22.148291 DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123
3245 23:19:22.148907
3246 23:19:22.149279
3247 23:19:22.149657 ==
3248 23:19:22.151172 Dram Type= 6, Freq= 0, CH_1, rank 0
3249 23:19:22.154758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3250 23:19:22.155331 ==
3251 23:19:22.155707
3252 23:19:22.156047
3253 23:19:22.158171 TX Vref Scan disable
3254 23:19:22.160990 == TX Byte 0 ==
3255 23:19:22.165212 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3256 23:19:22.167887 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3257 23:19:22.171154 == TX Byte 1 ==
3258 23:19:22.174361 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3259 23:19:22.177664 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3260 23:19:22.178122 ==
3261 23:19:22.181450 Dram Type= 6, Freq= 0, CH_1, rank 0
3262 23:19:22.184796 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3263 23:19:22.187437 ==
3264 23:19:22.198227 TX Vref=22, minBit 9, minWin=24, winSum=412
3265 23:19:22.201047 TX Vref=24, minBit 9, minWin=25, winSum=421
3266 23:19:22.204162 TX Vref=26, minBit 9, minWin=25, winSum=420
3267 23:19:22.207389 TX Vref=28, minBit 1, minWin=26, winSum=430
3268 23:19:22.210809 TX Vref=30, minBit 9, minWin=25, winSum=432
3269 23:19:22.217539 TX Vref=32, minBit 10, minWin=26, winSum=432
3270 23:19:22.221383 [TxChooseVref] Worse bit 10, Min win 26, Win sum 432, Final Vref 32
3271 23:19:22.222012
3272 23:19:22.224291 Final TX Range 1 Vref 32
3273 23:19:22.224753
3274 23:19:22.225114 ==
3275 23:19:22.227652 Dram Type= 6, Freq= 0, CH_1, rank 0
3276 23:19:22.230916 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3277 23:19:22.234737 ==
3278 23:19:22.235296
3279 23:19:22.235660
3280 23:19:22.235994 TX Vref Scan disable
3281 23:19:22.237517 == TX Byte 0 ==
3282 23:19:22.241087 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3283 23:19:22.244063 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3284 23:19:22.247600 == TX Byte 1 ==
3285 23:19:22.251861 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3286 23:19:22.254592 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3287 23:19:22.257696
3288 23:19:22.258266 [DATLAT]
3289 23:19:22.258636 Freq=1200, CH1 RK0
3290 23:19:22.258976
3291 23:19:22.260933 DATLAT Default: 0xd
3292 23:19:22.261495 0, 0xFFFF, sum = 0
3293 23:19:22.265018 1, 0xFFFF, sum = 0
3294 23:19:22.265482 2, 0xFFFF, sum = 0
3295 23:19:22.267584 3, 0xFFFF, sum = 0
3296 23:19:22.270685 4, 0xFFFF, sum = 0
3297 23:19:22.271151 5, 0xFFFF, sum = 0
3298 23:19:22.274131 6, 0xFFFF, sum = 0
3299 23:19:22.274595 7, 0xFFFF, sum = 0
3300 23:19:22.277846 8, 0xFFFF, sum = 0
3301 23:19:22.278410 9, 0xFFFF, sum = 0
3302 23:19:22.280703 10, 0xFFFF, sum = 0
3303 23:19:22.281166 11, 0xFFFF, sum = 0
3304 23:19:22.284054 12, 0x0, sum = 1
3305 23:19:22.284523 13, 0x0, sum = 2
3306 23:19:22.288120 14, 0x0, sum = 3
3307 23:19:22.288695 15, 0x0, sum = 4
3308 23:19:22.289071 best_step = 13
3309 23:19:22.291428
3310 23:19:22.291984 ==
3311 23:19:22.294563 Dram Type= 6, Freq= 0, CH_1, rank 0
3312 23:19:22.297633 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3313 23:19:22.298196 ==
3314 23:19:22.298567 RX Vref Scan: 1
3315 23:19:22.298906
3316 23:19:22.300946 Set Vref Range= 32 -> 127
3317 23:19:22.301412
3318 23:19:22.304546 RX Vref 32 -> 127, step: 1
3319 23:19:22.305012
3320 23:19:22.307691 RX Delay -5 -> 252, step: 4
3321 23:19:22.308158
3322 23:19:22.310851 Set Vref, RX VrefLevel [Byte0]: 32
3323 23:19:22.314130 [Byte1]: 32
3324 23:19:22.314591
3325 23:19:22.317450 Set Vref, RX VrefLevel [Byte0]: 33
3326 23:19:22.320979 [Byte1]: 33
3327 23:19:22.321497
3328 23:19:22.323979 Set Vref, RX VrefLevel [Byte0]: 34
3329 23:19:22.327609 [Byte1]: 34
3330 23:19:22.331536
3331 23:19:22.331945 Set Vref, RX VrefLevel [Byte0]: 35
3332 23:19:22.334960 [Byte1]: 35
3333 23:19:22.339598
3334 23:19:22.340010 Set Vref, RX VrefLevel [Byte0]: 36
3335 23:19:22.342923 [Byte1]: 36
3336 23:19:22.347038
3337 23:19:22.347446 Set Vref, RX VrefLevel [Byte0]: 37
3338 23:19:22.351269 [Byte1]: 37
3339 23:19:22.356011
3340 23:19:22.356524 Set Vref, RX VrefLevel [Byte0]: 38
3341 23:19:22.358555 [Byte1]: 38
3342 23:19:22.363229
3343 23:19:22.363737 Set Vref, RX VrefLevel [Byte0]: 39
3344 23:19:22.366388 [Byte1]: 39
3345 23:19:22.371481
3346 23:19:22.371990 Set Vref, RX VrefLevel [Byte0]: 40
3347 23:19:22.374314 [Byte1]: 40
3348 23:19:22.378670
3349 23:19:22.379226 Set Vref, RX VrefLevel [Byte0]: 41
3350 23:19:22.381801 [Byte1]: 41
3351 23:19:22.386403
3352 23:19:22.386812 Set Vref, RX VrefLevel [Byte0]: 42
3353 23:19:22.389565 [Byte1]: 42
3354 23:19:22.394494
3355 23:19:22.395002 Set Vref, RX VrefLevel [Byte0]: 43
3356 23:19:22.397632 [Byte1]: 43
3357 23:19:22.402222
3358 23:19:22.402631 Set Vref, RX VrefLevel [Byte0]: 44
3359 23:19:22.405597 [Byte1]: 44
3360 23:19:22.410295
3361 23:19:22.410802 Set Vref, RX VrefLevel [Byte0]: 45
3362 23:19:22.413244 [Byte1]: 45
3363 23:19:22.418404
3364 23:19:22.418928 Set Vref, RX VrefLevel [Byte0]: 46
3365 23:19:22.421361 [Byte1]: 46
3366 23:19:22.425893
3367 23:19:22.426300 Set Vref, RX VrefLevel [Byte0]: 47
3368 23:19:22.429828 [Byte1]: 47
3369 23:19:22.434131
3370 23:19:22.434645 Set Vref, RX VrefLevel [Byte0]: 48
3371 23:19:22.437438 [Byte1]: 48
3372 23:19:22.441855
3373 23:19:22.442363 Set Vref, RX VrefLevel [Byte0]: 49
3374 23:19:22.444990 [Byte1]: 49
3375 23:19:22.449560
3376 23:19:22.450109 Set Vref, RX VrefLevel [Byte0]: 50
3377 23:19:22.452973 [Byte1]: 50
3378 23:19:22.457492
3379 23:19:22.458045 Set Vref, RX VrefLevel [Byte0]: 51
3380 23:19:22.460604 [Byte1]: 51
3381 23:19:22.465347
3382 23:19:22.465899 Set Vref, RX VrefLevel [Byte0]: 52
3383 23:19:22.468783 [Byte1]: 52
3384 23:19:22.473481
3385 23:19:22.474040 Set Vref, RX VrefLevel [Byte0]: 53
3386 23:19:22.476094 [Byte1]: 53
3387 23:19:22.481543
3388 23:19:22.482082 Set Vref, RX VrefLevel [Byte0]: 54
3389 23:19:22.483962 [Byte1]: 54
3390 23:19:22.488949
3391 23:19:22.489697 Set Vref, RX VrefLevel [Byte0]: 55
3392 23:19:22.492239 [Byte1]: 55
3393 23:19:22.496963
3394 23:19:22.497472 Set Vref, RX VrefLevel [Byte0]: 56
3395 23:19:22.500354 [Byte1]: 56
3396 23:19:22.504176
3397 23:19:22.504680 Set Vref, RX VrefLevel [Byte0]: 57
3398 23:19:22.507727 [Byte1]: 57
3399 23:19:22.512056
3400 23:19:22.512574 Set Vref, RX VrefLevel [Byte0]: 58
3401 23:19:22.515683 [Byte1]: 58
3402 23:19:22.519785
3403 23:19:22.520200 Set Vref, RX VrefLevel [Byte0]: 59
3404 23:19:22.523253 [Byte1]: 59
3405 23:19:22.528115
3406 23:19:22.528621 Set Vref, RX VrefLevel [Byte0]: 60
3407 23:19:22.531282 [Byte1]: 60
3408 23:19:22.535529
3409 23:19:22.535948 Set Vref, RX VrefLevel [Byte0]: 61
3410 23:19:22.538847 [Byte1]: 61
3411 23:19:22.543721
3412 23:19:22.544131 Set Vref, RX VrefLevel [Byte0]: 62
3413 23:19:22.547160 [Byte1]: 62
3414 23:19:22.551393
3415 23:19:22.551937 Set Vref, RX VrefLevel [Byte0]: 63
3416 23:19:22.554773 [Byte1]: 63
3417 23:19:22.559371
3418 23:19:22.560093 Set Vref, RX VrefLevel [Byte0]: 64
3419 23:19:22.562320 [Byte1]: 64
3420 23:19:22.567497
3421 23:19:22.568004 Set Vref, RX VrefLevel [Byte0]: 65
3422 23:19:22.570906 [Byte1]: 65
3423 23:19:22.575206
3424 23:19:22.575691 Set Vref, RX VrefLevel [Byte0]: 66
3425 23:19:22.578019 [Byte1]: 66
3426 23:19:22.583407
3427 23:19:22.583915 Set Vref, RX VrefLevel [Byte0]: 67
3428 23:19:22.585952 [Byte1]: 67
3429 23:19:22.590495
3430 23:19:22.591006 Set Vref, RX VrefLevel [Byte0]: 68
3431 23:19:22.594128 [Byte1]: 68
3432 23:19:22.598554
3433 23:19:22.599071 Set Vref, RX VrefLevel [Byte0]: 69
3434 23:19:22.601803 [Byte1]: 69
3435 23:19:22.606284
3436 23:19:22.606698 Final RX Vref Byte 0 = 54 to rank0
3437 23:19:22.609753 Final RX Vref Byte 1 = 51 to rank0
3438 23:19:22.613094 Final RX Vref Byte 0 = 54 to rank1
3439 23:19:22.616970 Final RX Vref Byte 1 = 51 to rank1==
3440 23:19:22.619781 Dram Type= 6, Freq= 0, CH_1, rank 0
3441 23:19:22.626635 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3442 23:19:22.627139 ==
3443 23:19:22.627471 DQS Delay:
3444 23:19:22.627773 DQS0 = 0, DQS1 = 0
3445 23:19:22.630077 DQM Delay:
3446 23:19:22.630493 DQM0 = 120, DQM1 = 117
3447 23:19:22.633169 DQ Delay:
3448 23:19:22.636485 DQ0 =124, DQ1 =114, DQ2 =110, DQ3 =116
3449 23:19:22.639568 DQ4 =118, DQ5 =128, DQ6 =130, DQ7 =120
3450 23:19:22.643069 DQ8 =104, DQ9 =106, DQ10 =118, DQ11 =110
3451 23:19:22.646894 DQ12 =124, DQ13 =124, DQ14 =124, DQ15 =126
3452 23:19:22.647415
3453 23:19:22.647742
3454 23:19:22.653131 [DQSOSCAuto] RK0, (LSB)MR18= 0x13, (MSB)MR19= 0x404, tDQSOscB0 = 402 ps tDQSOscB1 = 410 ps
3455 23:19:22.656493 CH1 RK0: MR19=404, MR18=13
3456 23:19:22.662917 CH1_RK0: MR19=0x404, MR18=0x13, DQSOSC=402, MR23=63, INC=40, DEC=27
3457 23:19:22.663335
3458 23:19:22.666300 ----->DramcWriteLeveling(PI) begin...
3459 23:19:22.666721 ==
3460 23:19:22.670073 Dram Type= 6, Freq= 0, CH_1, rank 1
3461 23:19:22.673538 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3462 23:19:22.674087 ==
3463 23:19:22.676829 Write leveling (Byte 0): 26 => 26
3464 23:19:22.680014 Write leveling (Byte 1): 28 => 28
3465 23:19:22.683338 DramcWriteLeveling(PI) end<-----
3466 23:19:22.683752
3467 23:19:22.684077 ==
3468 23:19:22.687186 Dram Type= 6, Freq= 0, CH_1, rank 1
3469 23:19:22.690124 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3470 23:19:22.690518 ==
3471 23:19:22.693943 [Gating] SW mode calibration
3472 23:19:22.700435 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3473 23:19:22.706536 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3474 23:19:22.710379 0 15 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
3475 23:19:22.717246 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3476 23:19:22.720481 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3477 23:19:22.723823 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3478 23:19:22.730453 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3479 23:19:22.733736 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
3480 23:19:22.737127 0 15 24 | B1->B0 | 2929 3434 | 1 1 | (1 0) (1 1)
3481 23:19:22.740166 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
3482 23:19:22.747230 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3483 23:19:22.750231 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3484 23:19:22.753560 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3485 23:19:22.760549 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3486 23:19:22.763936 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3487 23:19:22.767479 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3488 23:19:22.773847 1 0 24 | B1->B0 | 4141 2929 | 0 0 | (0 0) (0 0)
3489 23:19:22.776664 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3490 23:19:22.780168 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3491 23:19:22.787147 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3492 23:19:22.790099 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3493 23:19:22.793303 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3494 23:19:22.800100 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3495 23:19:22.803066 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3496 23:19:22.807033 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3497 23:19:22.813138 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3498 23:19:22.816446 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3499 23:19:22.819978 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3500 23:19:22.826485 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3501 23:19:22.829906 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3502 23:19:22.832846 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3503 23:19:22.839234 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3504 23:19:22.842871 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3505 23:19:22.846550 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3506 23:19:22.852945 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3507 23:19:22.856251 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3508 23:19:22.859924 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3509 23:19:22.866544 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3510 23:19:22.869491 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3511 23:19:22.872744 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3512 23:19:22.879619 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3513 23:19:22.882955 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3514 23:19:22.886066 Total UI for P1: 0, mck2ui 16
3515 23:19:22.889613 best dqsien dly found for B1: ( 1, 3, 22)
3516 23:19:22.892434 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3517 23:19:22.896253 Total UI for P1: 0, mck2ui 16
3518 23:19:22.899640 best dqsien dly found for B0: ( 1, 3, 26)
3519 23:19:22.902656 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3520 23:19:22.906037 best DQS1 dly(MCK, UI, PI) = (1, 3, 22)
3521 23:19:22.906496
3522 23:19:22.909127 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3523 23:19:22.915913 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 22)
3524 23:19:22.916475 [Gating] SW calibration Done
3525 23:19:22.916847 ==
3526 23:19:22.919002 Dram Type= 6, Freq= 0, CH_1, rank 1
3527 23:19:22.925348 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3528 23:19:22.925874 ==
3529 23:19:22.926252 RX Vref Scan: 0
3530 23:19:22.926595
3531 23:19:22.929037 RX Vref 0 -> 0, step: 1
3532 23:19:22.929451
3533 23:19:22.932456 RX Delay -40 -> 252, step: 8
3534 23:19:22.936532 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3535 23:19:22.938776 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3536 23:19:22.942313 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3537 23:19:22.948961 iDelay=200, Bit 3, Center 119 (56 ~ 183) 128
3538 23:19:22.952776 iDelay=200, Bit 4, Center 119 (56 ~ 183) 128
3539 23:19:22.955733 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3540 23:19:22.959207 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3541 23:19:22.962345 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
3542 23:19:22.968877 iDelay=200, Bit 8, Center 107 (40 ~ 175) 136
3543 23:19:22.972193 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3544 23:19:22.975699 iDelay=200, Bit 10, Center 119 (48 ~ 191) 144
3545 23:19:22.978520 iDelay=200, Bit 11, Center 115 (48 ~ 183) 136
3546 23:19:22.981879 iDelay=200, Bit 12, Center 127 (56 ~ 199) 144
3547 23:19:22.988602 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3548 23:19:22.992056 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3549 23:19:22.995849 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3550 23:19:22.996382 ==
3551 23:19:22.999077 Dram Type= 6, Freq= 0, CH_1, rank 1
3552 23:19:23.002094 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3553 23:19:23.002663 ==
3554 23:19:23.005365 DQS Delay:
3555 23:19:23.005849 DQS0 = 0, DQS1 = 0
3556 23:19:23.009124 DQM Delay:
3557 23:19:23.009712 DQM0 = 121, DQM1 = 118
3558 23:19:23.012431 DQ Delay:
3559 23:19:23.014982 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3560 23:19:23.018415 DQ4 =119, DQ5 =131, DQ6 =131, DQ7 =123
3561 23:19:23.021915 DQ8 =107, DQ9 =107, DQ10 =119, DQ11 =115
3562 23:19:23.025421 DQ12 =127, DQ13 =127, DQ14 =123, DQ15 =123
3563 23:19:23.026106
3564 23:19:23.026559
3565 23:19:23.026975 ==
3566 23:19:23.028747 Dram Type= 6, Freq= 0, CH_1, rank 1
3567 23:19:23.032127 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3568 23:19:23.032663 ==
3569 23:19:23.033113
3570 23:19:23.033529
3571 23:19:23.035609 TX Vref Scan disable
3572 23:19:23.038645 == TX Byte 0 ==
3573 23:19:23.042099 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3574 23:19:23.045372 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3575 23:19:23.048224 == TX Byte 1 ==
3576 23:19:23.051760 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3577 23:19:23.055615 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3578 23:19:23.056135 ==
3579 23:19:23.058345 Dram Type= 6, Freq= 0, CH_1, rank 1
3580 23:19:23.065694 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3581 23:19:23.066212 ==
3582 23:19:23.075170 TX Vref=22, minBit 0, minWin=25, winSum=416
3583 23:19:23.079567 TX Vref=24, minBit 8, minWin=26, winSum=427
3584 23:19:23.081796 TX Vref=26, minBit 2, minWin=26, winSum=428
3585 23:19:23.085476 TX Vref=28, minBit 9, minWin=26, winSum=437
3586 23:19:23.088778 TX Vref=30, minBit 9, minWin=26, winSum=436
3587 23:19:23.091773 TX Vref=32, minBit 11, minWin=26, winSum=435
3588 23:19:23.098448 [TxChooseVref] Worse bit 9, Min win 26, Win sum 437, Final Vref 28
3589 23:19:23.098993
3590 23:19:23.102276 Final TX Range 1 Vref 28
3591 23:19:23.102756
3592 23:19:23.103241 ==
3593 23:19:23.105097 Dram Type= 6, Freq= 0, CH_1, rank 1
3594 23:19:23.109112 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3595 23:19:23.109731 ==
3596 23:19:23.112246
3597 23:19:23.112676
3598 23:19:23.113108 TX Vref Scan disable
3599 23:19:23.115349 == TX Byte 0 ==
3600 23:19:23.118332 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3601 23:19:23.121769 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3602 23:19:23.125391 == TX Byte 1 ==
3603 23:19:23.128732 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3604 23:19:23.131951 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3605 23:19:23.135687
3606 23:19:23.136250 [DATLAT]
3607 23:19:23.136743 Freq=1200, CH1 RK1
3608 23:19:23.137205
3609 23:19:23.138090 DATLAT Default: 0xd
3610 23:19:23.138503 0, 0xFFFF, sum = 0
3611 23:19:23.142157 1, 0xFFFF, sum = 0
3612 23:19:23.142644 2, 0xFFFF, sum = 0
3613 23:19:23.145310 3, 0xFFFF, sum = 0
3614 23:19:23.148973 4, 0xFFFF, sum = 0
3615 23:19:23.149549 5, 0xFFFF, sum = 0
3616 23:19:23.151434 6, 0xFFFF, sum = 0
3617 23:19:23.151896 7, 0xFFFF, sum = 0
3618 23:19:23.155176 8, 0xFFFF, sum = 0
3619 23:19:23.155702 9, 0xFFFF, sum = 0
3620 23:19:23.158088 10, 0xFFFF, sum = 0
3621 23:19:23.158515 11, 0xFFFF, sum = 0
3622 23:19:23.161765 12, 0x0, sum = 1
3623 23:19:23.162296 13, 0x0, sum = 2
3624 23:19:23.165330 14, 0x0, sum = 3
3625 23:19:23.165917 15, 0x0, sum = 4
3626 23:19:23.166266 best_step = 13
3627 23:19:23.168200
3628 23:19:23.168712 ==
3629 23:19:23.171932 Dram Type= 6, Freq= 0, CH_1, rank 1
3630 23:19:23.175296 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3631 23:19:23.175864 ==
3632 23:19:23.176238 RX Vref Scan: 0
3633 23:19:23.176585
3634 23:19:23.178251 RX Vref 0 -> 0, step: 1
3635 23:19:23.178718
3636 23:19:23.181778 RX Delay -5 -> 252, step: 4
3637 23:19:23.184848 iDelay=195, Bit 0, Center 122 (59 ~ 186) 128
3638 23:19:23.191214 iDelay=195, Bit 1, Center 116 (55 ~ 178) 124
3639 23:19:23.194729 iDelay=195, Bit 2, Center 110 (51 ~ 170) 120
3640 23:19:23.198166 iDelay=195, Bit 3, Center 114 (55 ~ 174) 120
3641 23:19:23.201402 iDelay=195, Bit 4, Center 116 (55 ~ 178) 124
3642 23:19:23.204637 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3643 23:19:23.211085 iDelay=195, Bit 6, Center 130 (67 ~ 194) 128
3644 23:19:23.214364 iDelay=195, Bit 7, Center 120 (59 ~ 182) 124
3645 23:19:23.217628 iDelay=195, Bit 8, Center 106 (47 ~ 166) 120
3646 23:19:23.220872 iDelay=195, Bit 9, Center 108 (47 ~ 170) 124
3647 23:19:23.224658 iDelay=195, Bit 10, Center 116 (55 ~ 178) 124
3648 23:19:23.231378 iDelay=195, Bit 11, Center 112 (51 ~ 174) 124
3649 23:19:23.235130 iDelay=195, Bit 12, Center 126 (63 ~ 190) 128
3650 23:19:23.238228 iDelay=195, Bit 13, Center 124 (67 ~ 182) 116
3651 23:19:23.241222 iDelay=195, Bit 14, Center 124 (67 ~ 182) 116
3652 23:19:23.245202 iDelay=195, Bit 15, Center 128 (67 ~ 190) 124
3653 23:19:23.248623 ==
3654 23:19:23.249193 Dram Type= 6, Freq= 0, CH_1, rank 1
3655 23:19:23.254722 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3656 23:19:23.255300 ==
3657 23:19:23.255798 DQS Delay:
3658 23:19:23.258216 DQS0 = 0, DQS1 = 0
3659 23:19:23.258697 DQM Delay:
3660 23:19:23.262006 DQM0 = 119, DQM1 = 118
3661 23:19:23.262582 DQ Delay:
3662 23:19:23.264702 DQ0 =122, DQ1 =116, DQ2 =110, DQ3 =114
3663 23:19:23.267785 DQ4 =116, DQ5 =130, DQ6 =130, DQ7 =120
3664 23:19:23.271280 DQ8 =106, DQ9 =108, DQ10 =116, DQ11 =112
3665 23:19:23.274483 DQ12 =126, DQ13 =124, DQ14 =124, DQ15 =128
3666 23:19:23.275075
3667 23:19:23.275566
3668 23:19:23.284363 [DQSOSCAuto] RK1, (LSB)MR18= 0x10ee, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 403 ps
3669 23:19:23.288123 CH1 RK1: MR19=403, MR18=10EE
3670 23:19:23.291246 CH1_RK1: MR19=0x403, MR18=0x10EE, DQSOSC=403, MR23=63, INC=40, DEC=26
3671 23:19:23.294269 [RxdqsGatingPostProcess] freq 1200
3672 23:19:23.301234 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3673 23:19:23.304699 best DQS0 dly(2T, 0.5T) = (0, 11)
3674 23:19:23.307163 best DQS1 dly(2T, 0.5T) = (0, 11)
3675 23:19:23.310724 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3676 23:19:23.314059 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3677 23:19:23.318072 best DQS0 dly(2T, 0.5T) = (0, 11)
3678 23:19:23.320774 best DQS1 dly(2T, 0.5T) = (0, 11)
3679 23:19:23.324279 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3680 23:19:23.327538 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3681 23:19:23.330763 Pre-setting of DQS Precalculation
3682 23:19:23.333638 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3683 23:19:23.340599 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3684 23:19:23.346914 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3685 23:19:23.350176
3686 23:19:23.350635
3687 23:19:23.351001 [Calibration Summary] 2400 Mbps
3688 23:19:23.353851 CH 0, Rank 0
3689 23:19:23.354313 SW Impedance : PASS
3690 23:19:23.357201 DUTY Scan : NO K
3691 23:19:23.360487 ZQ Calibration : PASS
3692 23:19:23.361105 Jitter Meter : NO K
3693 23:19:23.363901 CBT Training : PASS
3694 23:19:23.367631 Write leveling : PASS
3695 23:19:23.368188 RX DQS gating : PASS
3696 23:19:23.370280 RX DQ/DQS(RDDQC) : PASS
3697 23:19:23.373688 TX DQ/DQS : PASS
3698 23:19:23.374260 RX DATLAT : PASS
3699 23:19:23.376983 RX DQ/DQS(Engine): PASS
3700 23:19:23.380406 TX OE : NO K
3701 23:19:23.380875 All Pass.
3702 23:19:23.381245
3703 23:19:23.381622 CH 0, Rank 1
3704 23:19:23.383726 SW Impedance : PASS
3705 23:19:23.386653 DUTY Scan : NO K
3706 23:19:23.387138 ZQ Calibration : PASS
3707 23:19:23.390225 Jitter Meter : NO K
3708 23:19:23.393557 CBT Training : PASS
3709 23:19:23.394165 Write leveling : PASS
3710 23:19:23.397133 RX DQS gating : PASS
3711 23:19:23.400716 RX DQ/DQS(RDDQC) : PASS
3712 23:19:23.401276 TX DQ/DQS : PASS
3713 23:19:23.403964 RX DATLAT : PASS
3714 23:19:23.404523 RX DQ/DQS(Engine): PASS
3715 23:19:23.406751 TX OE : NO K
3716 23:19:23.407223 All Pass.
3717 23:19:23.407594
3718 23:19:23.410323 CH 1, Rank 0
3719 23:19:23.410789 SW Impedance : PASS
3720 23:19:23.413411 DUTY Scan : NO K
3721 23:19:23.417055 ZQ Calibration : PASS
3722 23:19:23.417665 Jitter Meter : NO K
3723 23:19:23.420447 CBT Training : PASS
3724 23:19:23.423823 Write leveling : PASS
3725 23:19:23.424384 RX DQS gating : PASS
3726 23:19:23.427187 RX DQ/DQS(RDDQC) : PASS
3727 23:19:23.430087 TX DQ/DQS : PASS
3728 23:19:23.430556 RX DATLAT : PASS
3729 23:19:23.433805 RX DQ/DQS(Engine): PASS
3730 23:19:23.436921 TX OE : NO K
3731 23:19:23.437540 All Pass.
3732 23:19:23.437974
3733 23:19:23.438323 CH 1, Rank 1
3734 23:19:23.440551 SW Impedance : PASS
3735 23:19:23.443773 DUTY Scan : NO K
3736 23:19:23.444360 ZQ Calibration : PASS
3737 23:19:23.446521 Jitter Meter : NO K
3738 23:19:23.450092 CBT Training : PASS
3739 23:19:23.450669 Write leveling : PASS
3740 23:19:23.453203 RX DQS gating : PASS
3741 23:19:23.453733 RX DQ/DQS(RDDQC) : PASS
3742 23:19:23.456619 TX DQ/DQS : PASS
3743 23:19:23.459898 RX DATLAT : PASS
3744 23:19:23.460366 RX DQ/DQS(Engine): PASS
3745 23:19:23.463512 TX OE : NO K
3746 23:19:23.463990 All Pass.
3747 23:19:23.464357
3748 23:19:23.466737 DramC Write-DBI off
3749 23:19:23.470506 PER_BANK_REFRESH: Hybrid Mode
3750 23:19:23.471029 TX_TRACKING: ON
3751 23:19:23.480153 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3752 23:19:23.483188 [FAST_K] Save calibration result to emmc
3753 23:19:23.486622 dramc_set_vcore_voltage set vcore to 650000
3754 23:19:23.490283 Read voltage for 600, 5
3755 23:19:23.490831 Vio18 = 0
3756 23:19:23.491180 Vcore = 650000
3757 23:19:23.493854 Vdram = 0
3758 23:19:23.494370 Vddq = 0
3759 23:19:23.494708 Vmddr = 0
3760 23:19:23.500429 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3761 23:19:23.503404 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3762 23:19:23.506588 MEM_TYPE=3, freq_sel=19
3763 23:19:23.510119 sv_algorithm_assistance_LP4_1600
3764 23:19:23.513406 ============ PULL DRAM RESETB DOWN ============
3765 23:19:23.517051 ========== PULL DRAM RESETB DOWN end =========
3766 23:19:23.523720 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3767 23:19:23.526903 ===================================
3768 23:19:23.527493 LPDDR4 DRAM CONFIGURATION
3769 23:19:23.530174 ===================================
3770 23:19:23.533935 EX_ROW_EN[0] = 0x0
3771 23:19:23.536783 EX_ROW_EN[1] = 0x0
3772 23:19:23.537303 LP4Y_EN = 0x0
3773 23:19:23.540194 WORK_FSP = 0x0
3774 23:19:23.540706 WL = 0x2
3775 23:19:23.543979 RL = 0x2
3776 23:19:23.544498 BL = 0x2
3777 23:19:23.546485 RPST = 0x0
3778 23:19:23.546911 RD_PRE = 0x0
3779 23:19:23.549811 WR_PRE = 0x1
3780 23:19:23.550233 WR_PST = 0x0
3781 23:19:23.553323 DBI_WR = 0x0
3782 23:19:23.553908 DBI_RD = 0x0
3783 23:19:23.556923 OTF = 0x1
3784 23:19:23.559956 ===================================
3785 23:19:23.563702 ===================================
3786 23:19:23.564241 ANA top config
3787 23:19:23.566903 ===================================
3788 23:19:23.569885 DLL_ASYNC_EN = 0
3789 23:19:23.573268 ALL_SLAVE_EN = 1
3790 23:19:23.576414 NEW_RANK_MODE = 1
3791 23:19:23.576997 DLL_IDLE_MODE = 1
3792 23:19:23.579912 LP45_APHY_COMB_EN = 1
3793 23:19:23.583270 TX_ODT_DIS = 1
3794 23:19:23.586531 NEW_8X_MODE = 1
3795 23:19:23.589661 ===================================
3796 23:19:23.593555 ===================================
3797 23:19:23.596879 data_rate = 1200
3798 23:19:23.597437 CKR = 1
3799 23:19:23.599840 DQ_P2S_RATIO = 8
3800 23:19:23.602746 ===================================
3801 23:19:23.606416 CA_P2S_RATIO = 8
3802 23:19:23.609302 DQ_CA_OPEN = 0
3803 23:19:23.612844 DQ_SEMI_OPEN = 0
3804 23:19:23.616023 CA_SEMI_OPEN = 0
3805 23:19:23.616493 CA_FULL_RATE = 0
3806 23:19:23.619598 DQ_CKDIV4_EN = 1
3807 23:19:23.623082 CA_CKDIV4_EN = 1
3808 23:19:23.626001 CA_PREDIV_EN = 0
3809 23:19:23.629495 PH8_DLY = 0
3810 23:19:23.632981 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3811 23:19:23.633547 DQ_AAMCK_DIV = 4
3812 23:19:23.636264 CA_AAMCK_DIV = 4
3813 23:19:23.639700 CA_ADMCK_DIV = 4
3814 23:19:23.643328 DQ_TRACK_CA_EN = 0
3815 23:19:23.645993 CA_PICK = 600
3816 23:19:23.649986 CA_MCKIO = 600
3817 23:19:23.652915 MCKIO_SEMI = 0
3818 23:19:23.653475 PLL_FREQ = 2288
3819 23:19:23.656535 DQ_UI_PI_RATIO = 32
3820 23:19:23.659717 CA_UI_PI_RATIO = 0
3821 23:19:23.662565 ===================================
3822 23:19:23.666098 ===================================
3823 23:19:23.669328 memory_type:LPDDR4
3824 23:19:23.669954 GP_NUM : 10
3825 23:19:23.673321 SRAM_EN : 1
3826 23:19:23.675905 MD32_EN : 0
3827 23:19:23.679428 ===================================
3828 23:19:23.679993 [ANA_INIT] >>>>>>>>>>>>>>
3829 23:19:23.682687 <<<<<< [CONFIGURE PHASE]: ANA_TX
3830 23:19:23.686183 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3831 23:19:23.689469 ===================================
3832 23:19:23.692579 data_rate = 1200,PCW = 0X5800
3833 23:19:23.695449 ===================================
3834 23:19:23.698978 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3835 23:19:23.705454 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3836 23:19:23.712339 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3837 23:19:23.715442 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3838 23:19:23.718505 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3839 23:19:23.721765 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3840 23:19:23.725798 [ANA_INIT] flow start
3841 23:19:23.726386 [ANA_INIT] PLL >>>>>>>>
3842 23:19:23.728356 [ANA_INIT] PLL <<<<<<<<
3843 23:19:23.732044 [ANA_INIT] MIDPI >>>>>>>>
3844 23:19:23.732603 [ANA_INIT] MIDPI <<<<<<<<
3845 23:19:23.735436 [ANA_INIT] DLL >>>>>>>>
3846 23:19:23.738320 [ANA_INIT] flow end
3847 23:19:23.741946 ============ LP4 DIFF to SE enter ============
3848 23:19:23.745402 ============ LP4 DIFF to SE exit ============
3849 23:19:23.748930 [ANA_INIT] <<<<<<<<<<<<<
3850 23:19:23.752345 [Flow] Enable top DCM control >>>>>
3851 23:19:23.755802 [Flow] Enable top DCM control <<<<<
3852 23:19:23.758558 Enable DLL master slave shuffle
3853 23:19:23.762592 ==============================================================
3854 23:19:23.765275 Gating Mode config
3855 23:19:23.772208 ==============================================================
3856 23:19:23.772776 Config description:
3857 23:19:23.782004 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3858 23:19:23.788316 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3859 23:19:23.792226 SELPH_MODE 0: By rank 1: By Phase
3860 23:19:23.798865 ==============================================================
3861 23:19:23.802003 GAT_TRACK_EN = 1
3862 23:19:23.804976 RX_GATING_MODE = 2
3863 23:19:23.808261 RX_GATING_TRACK_MODE = 2
3864 23:19:23.812206 SELPH_MODE = 1
3865 23:19:23.815123 PICG_EARLY_EN = 1
3866 23:19:23.818294 VALID_LAT_VALUE = 1
3867 23:19:23.821415 ==============================================================
3868 23:19:23.825689 Enter into Gating configuration >>>>
3869 23:19:23.828245 Exit from Gating configuration <<<<
3870 23:19:23.832102 Enter into DVFS_PRE_config >>>>>
3871 23:19:23.844860 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3872 23:19:23.845432 Exit from DVFS_PRE_config <<<<<
3873 23:19:23.848202 Enter into PICG configuration >>>>
3874 23:19:23.851461 Exit from PICG configuration <<<<
3875 23:19:23.855121 [RX_INPUT] configuration >>>>>
3876 23:19:23.858566 [RX_INPUT] configuration <<<<<
3877 23:19:23.864657 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3878 23:19:23.868078 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3879 23:19:23.874381 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3880 23:19:23.881258 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3881 23:19:23.888204 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3882 23:19:23.894916 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3883 23:19:23.897691 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3884 23:19:23.901437 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3885 23:19:23.904871 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3886 23:19:23.911029 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3887 23:19:23.914291 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3888 23:19:23.918168 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3889 23:19:23.921567 ===================================
3890 23:19:23.924737 LPDDR4 DRAM CONFIGURATION
3891 23:19:23.928294 ===================================
3892 23:19:23.928960 EX_ROW_EN[0] = 0x0
3893 23:19:23.931619 EX_ROW_EN[1] = 0x0
3894 23:19:23.934359 LP4Y_EN = 0x0
3895 23:19:23.934826 WORK_FSP = 0x0
3896 23:19:23.938071 WL = 0x2
3897 23:19:23.938662 RL = 0x2
3898 23:19:23.941507 BL = 0x2
3899 23:19:23.942140 RPST = 0x0
3900 23:19:23.944713 RD_PRE = 0x0
3901 23:19:23.945265 WR_PRE = 0x1
3902 23:19:23.947846 WR_PST = 0x0
3903 23:19:23.948312 DBI_WR = 0x0
3904 23:19:23.951415 DBI_RD = 0x0
3905 23:19:23.951973 OTF = 0x1
3906 23:19:23.954599 ===================================
3907 23:19:23.957942 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3908 23:19:23.964859 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3909 23:19:23.967768 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3910 23:19:23.970830 ===================================
3911 23:19:23.974376 LPDDR4 DRAM CONFIGURATION
3912 23:19:23.978142 ===================================
3913 23:19:23.978714 EX_ROW_EN[0] = 0x10
3914 23:19:23.980765 EX_ROW_EN[1] = 0x0
3915 23:19:23.983964 LP4Y_EN = 0x0
3916 23:19:23.984452 WORK_FSP = 0x0
3917 23:19:23.987370 WL = 0x2
3918 23:19:23.987997 RL = 0x2
3919 23:19:23.990916 BL = 0x2
3920 23:19:23.991383 RPST = 0x0
3921 23:19:23.994486 RD_PRE = 0x0
3922 23:19:23.995041 WR_PRE = 0x1
3923 23:19:23.997443 WR_PST = 0x0
3924 23:19:23.997972 DBI_WR = 0x0
3925 23:19:24.000475 DBI_RD = 0x0
3926 23:19:24.000941 OTF = 0x1
3927 23:19:24.004248 ===================================
3928 23:19:24.012028 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3929 23:19:24.015236 nWR fixed to 30
3930 23:19:24.018356 [ModeRegInit_LP4] CH0 RK0
3931 23:19:24.018846 [ModeRegInit_LP4] CH0 RK1
3932 23:19:24.022066 [ModeRegInit_LP4] CH1 RK0
3933 23:19:24.025663 [ModeRegInit_LP4] CH1 RK1
3934 23:19:24.026227 match AC timing 17
3935 23:19:24.031259 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3936 23:19:24.035064 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3937 23:19:24.038345 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3938 23:19:24.045089 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3939 23:19:24.048528 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3940 23:19:24.048950 ==
3941 23:19:24.051504 Dram Type= 6, Freq= 0, CH_0, rank 0
3942 23:19:24.055156 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3943 23:19:24.055676 ==
3944 23:19:24.061739 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3945 23:19:24.068622 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3946 23:19:24.072139 [CA 0] Center 35 (5~66) winsize 62
3947 23:19:24.074515 [CA 1] Center 36 (5~67) winsize 63
3948 23:19:24.078508 [CA 2] Center 33 (3~64) winsize 62
3949 23:19:24.081612 [CA 3] Center 33 (2~64) winsize 63
3950 23:19:24.084926 [CA 4] Center 33 (2~64) winsize 63
3951 23:19:24.088073 [CA 5] Center 32 (2~63) winsize 62
3952 23:19:24.088631
3953 23:19:24.091798 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3954 23:19:24.092369
3955 23:19:24.095033 [CATrainingPosCal] consider 1 rank data
3956 23:19:24.097841 u2DelayCellTimex100 = 270/100 ps
3957 23:19:24.101135 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3958 23:19:24.104856 CA1 delay=36 (5~67),Diff = 4 PI (38 cell)
3959 23:19:24.108218 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3960 23:19:24.111315 CA3 delay=33 (2~64),Diff = 1 PI (9 cell)
3961 23:19:24.114782 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3962 23:19:24.121415 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3963 23:19:24.122051
3964 23:19:24.124550 CA PerBit enable=1, Macro0, CA PI delay=32
3965 23:19:24.125010
3966 23:19:24.127768 [CBTSetCACLKResult] CA Dly = 32
3967 23:19:24.128232 CS Dly: 4 (0~35)
3968 23:19:24.128664 ==
3969 23:19:24.130951 Dram Type= 6, Freq= 0, CH_0, rank 1
3970 23:19:24.134246 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3971 23:19:24.137557 ==
3972 23:19:24.141027 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3973 23:19:24.147822 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3974 23:19:24.150764 [CA 0] Center 35 (5~66) winsize 62
3975 23:19:24.154067 [CA 1] Center 35 (5~66) winsize 62
3976 23:19:24.157625 [CA 2] Center 34 (3~65) winsize 63
3977 23:19:24.161165 [CA 3] Center 33 (3~64) winsize 62
3978 23:19:24.164477 [CA 4] Center 32 (2~63) winsize 62
3979 23:19:24.167650 [CA 5] Center 32 (2~63) winsize 62
3980 23:19:24.168164
3981 23:19:24.171191 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3982 23:19:24.171708
3983 23:19:24.174592 [CATrainingPosCal] consider 2 rank data
3984 23:19:24.177567 u2DelayCellTimex100 = 270/100 ps
3985 23:19:24.180955 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3986 23:19:24.184573 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3987 23:19:24.186924 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3988 23:19:24.193854 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
3989 23:19:24.196942 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
3990 23:19:24.200241 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3991 23:19:24.200669
3992 23:19:24.203602 CA PerBit enable=1, Macro0, CA PI delay=32
3993 23:19:24.204119
3994 23:19:24.207036 [CBTSetCACLKResult] CA Dly = 32
3995 23:19:24.207494 CS Dly: 4 (0~36)
3996 23:19:24.207888
3997 23:19:24.210425 ----->DramcWriteLeveling(PI) begin...
3998 23:19:24.213679 ==
3999 23:19:24.214109 Dram Type= 6, Freq= 0, CH_0, rank 0
4000 23:19:24.220340 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4001 23:19:24.220864 ==
4002 23:19:24.223305 Write leveling (Byte 0): 35 => 35
4003 23:19:24.227121 Write leveling (Byte 1): 32 => 32
4004 23:19:24.229951 DramcWriteLeveling(PI) end<-----
4005 23:19:24.230375
4006 23:19:24.230704 ==
4007 23:19:24.233998 Dram Type= 6, Freq= 0, CH_0, rank 0
4008 23:19:24.236833 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4009 23:19:24.237343 ==
4010 23:19:24.240235 [Gating] SW mode calibration
4011 23:19:24.246783 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4012 23:19:24.249969 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4013 23:19:24.257196 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4014 23:19:24.260592 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4015 23:19:24.263683 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4016 23:19:24.270169 0 9 12 | B1->B0 | 3434 2d2d | 1 0 | (1 1) (1 1)
4017 23:19:24.273632 0 9 16 | B1->B0 | 2e2e 2323 | 0 0 | (1 0) (0 0)
4018 23:19:24.277492 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4019 23:19:24.283921 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4020 23:19:24.287091 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4021 23:19:24.289765 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4022 23:19:24.297240 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4023 23:19:24.299820 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4024 23:19:24.303470 0 10 12 | B1->B0 | 2323 3737 | 0 1 | (0 0) (0 0)
4025 23:19:24.309957 0 10 16 | B1->B0 | 3131 4646 | 0 0 | (0 0) (0 0)
4026 23:19:24.313527 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4027 23:19:24.316664 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4028 23:19:24.323643 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4029 23:19:24.326553 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4030 23:19:24.330202 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4031 23:19:24.337105 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4032 23:19:24.340522 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4033 23:19:24.344121 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4034 23:19:24.347082 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4035 23:19:24.353415 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4036 23:19:24.356666 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4037 23:19:24.360698 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4038 23:19:24.366536 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4039 23:19:24.370029 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4040 23:19:24.373759 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4041 23:19:24.380018 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4042 23:19:24.383292 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4043 23:19:24.386971 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4044 23:19:24.394034 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4045 23:19:24.396829 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4046 23:19:24.400085 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4047 23:19:24.407336 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4048 23:19:24.410323 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4049 23:19:24.413138 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4050 23:19:24.420360 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4051 23:19:24.420884 Total UI for P1: 0, mck2ui 16
4052 23:19:24.427031 best dqsien dly found for B0: ( 0, 13, 14)
4053 23:19:24.427530 Total UI for P1: 0, mck2ui 16
4054 23:19:24.429746 best dqsien dly found for B1: ( 0, 13, 18)
4055 23:19:24.436886 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4056 23:19:24.439784 best DQS1 dly(MCK, UI, PI) = (0, 13, 18)
4057 23:19:24.440306
4058 23:19:24.443556 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4059 23:19:24.447093 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)
4060 23:19:24.450140 [Gating] SW calibration Done
4061 23:19:24.450559 ==
4062 23:19:24.453275 Dram Type= 6, Freq= 0, CH_0, rank 0
4063 23:19:24.456434 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4064 23:19:24.456855 ==
4065 23:19:24.460021 RX Vref Scan: 0
4066 23:19:24.460537
4067 23:19:24.460924 RX Vref 0 -> 0, step: 1
4068 23:19:24.461245
4069 23:19:24.463313 RX Delay -230 -> 252, step: 16
4070 23:19:24.466794 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4071 23:19:24.473344 iDelay=218, Bit 1, Center 65 (-86 ~ 217) 304
4072 23:19:24.476456 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4073 23:19:24.480157 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4074 23:19:24.483388 iDelay=218, Bit 4, Center 65 (-86 ~ 217) 304
4075 23:19:24.490173 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4076 23:19:24.493461 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4077 23:19:24.496391 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4078 23:19:24.499748 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4079 23:19:24.503290 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4080 23:19:24.509362 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4081 23:19:24.512785 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4082 23:19:24.516187 iDelay=218, Bit 12, Center 57 (-86 ~ 201) 288
4083 23:19:24.519068 iDelay=218, Bit 13, Center 57 (-86 ~ 201) 288
4084 23:19:24.526332 iDelay=218, Bit 14, Center 65 (-86 ~ 217) 304
4085 23:19:24.529138 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4086 23:19:24.529621 ==
4087 23:19:24.532799 Dram Type= 6, Freq= 0, CH_0, rank 0
4088 23:19:24.535769 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4089 23:19:24.536195 ==
4090 23:19:24.539685 DQS Delay:
4091 23:19:24.540200 DQS0 = 0, DQS1 = 0
4092 23:19:24.540539 DQM Delay:
4093 23:19:24.542913 DQM0 = 55, DQM1 = 48
4094 23:19:24.543428 DQ Delay:
4095 23:19:24.545940 DQ0 =57, DQ1 =65, DQ2 =41, DQ3 =41
4096 23:19:24.549402 DQ4 =65, DQ5 =41, DQ6 =65, DQ7 =65
4097 23:19:24.552801 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =41
4098 23:19:24.556174 DQ12 =57, DQ13 =57, DQ14 =65, DQ15 =57
4099 23:19:24.556692
4100 23:19:24.557025
4101 23:19:24.557335 ==
4102 23:19:24.559550 Dram Type= 6, Freq= 0, CH_0, rank 0
4103 23:19:24.566030 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4104 23:19:24.566538 ==
4105 23:19:24.566881
4106 23:19:24.567195
4107 23:19:24.567492 TX Vref Scan disable
4108 23:19:24.569560 == TX Byte 0 ==
4109 23:19:24.572295 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4110 23:19:24.576123 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4111 23:19:24.579050 == TX Byte 1 ==
4112 23:19:24.582229 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4113 23:19:24.585741 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4114 23:19:24.589025 ==
4115 23:19:24.592329 Dram Type= 6, Freq= 0, CH_0, rank 0
4116 23:19:24.595684 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4117 23:19:24.595987 ==
4118 23:19:24.596226
4119 23:19:24.596450
4120 23:19:24.599160 TX Vref Scan disable
4121 23:19:24.599464 == TX Byte 0 ==
4122 23:19:24.605747 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4123 23:19:24.609013 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4124 23:19:24.611970 == TX Byte 1 ==
4125 23:19:24.615550 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4126 23:19:24.618485 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4127 23:19:24.618620
4128 23:19:24.618724 [DATLAT]
4129 23:19:24.621716 Freq=600, CH0 RK0
4130 23:19:24.621888
4131 23:19:24.621995 DATLAT Default: 0x9
4132 23:19:24.625131 0, 0xFFFF, sum = 0
4133 23:19:24.628582 1, 0xFFFF, sum = 0
4134 23:19:24.628687 2, 0xFFFF, sum = 0
4135 23:19:24.631766 3, 0xFFFF, sum = 0
4136 23:19:24.631873 4, 0xFFFF, sum = 0
4137 23:19:24.635198 5, 0xFFFF, sum = 0
4138 23:19:24.635305 6, 0xFFFF, sum = 0
4139 23:19:24.638284 7, 0xFFFF, sum = 0
4140 23:19:24.638392 8, 0x0, sum = 1
4141 23:19:24.641519 9, 0x0, sum = 2
4142 23:19:24.641640 10, 0x0, sum = 3
4143 23:19:24.641724 11, 0x0, sum = 4
4144 23:19:24.645161 best_step = 9
4145 23:19:24.645264
4146 23:19:24.645344 ==
4147 23:19:24.648861 Dram Type= 6, Freq= 0, CH_0, rank 0
4148 23:19:24.652082 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4149 23:19:24.652176 ==
4150 23:19:24.655363 RX Vref Scan: 1
4151 23:19:24.655454
4152 23:19:24.655526 RX Vref 0 -> 0, step: 1
4153 23:19:24.655594
4154 23:19:24.658784 RX Delay -163 -> 252, step: 8
4155 23:19:24.658876
4156 23:19:24.661890 Set Vref, RX VrefLevel [Byte0]: 60
4157 23:19:24.664892 [Byte1]: 48
4158 23:19:24.669337
4159 23:19:24.669429 Final RX Vref Byte 0 = 60 to rank0
4160 23:19:24.673035 Final RX Vref Byte 1 = 48 to rank0
4161 23:19:24.676014 Final RX Vref Byte 0 = 60 to rank1
4162 23:19:24.678999 Final RX Vref Byte 1 = 48 to rank1==
4163 23:19:24.682639 Dram Type= 6, Freq= 0, CH_0, rank 0
4164 23:19:24.689469 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4165 23:19:24.689632 ==
4166 23:19:24.689720 DQS Delay:
4167 23:19:24.689825 DQS0 = 0, DQS1 = 0
4168 23:19:24.692282 DQM Delay:
4169 23:19:24.692388 DQM0 = 53, DQM1 = 45
4170 23:19:24.695632 DQ Delay:
4171 23:19:24.699002 DQ0 =52, DQ1 =56, DQ2 =48, DQ3 =52
4172 23:19:24.702499 DQ4 =52, DQ5 =44, DQ6 =60, DQ7 =60
4173 23:19:24.705722 DQ8 =32, DQ9 =36, DQ10 =48, DQ11 =40
4174 23:19:24.709113 DQ12 =52, DQ13 =48, DQ14 =56, DQ15 =52
4175 23:19:24.709276
4176 23:19:24.709404
4177 23:19:24.727293 [DQSOSCAuto] RK0, (LSB)MR18= 0x6a5d, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 389 ps
4178 23:19:24.727573 CH0 RK0: MR19=808, MR18=6A5D
4179 23:19:24.727794 CH0_RK0: MR19=0x808, MR18=0x6A5D, DQSOSC=389, MR23=63, INC=173, DEC=115
4180 23:19:24.728048
4181 23:19:24.729364 ----->DramcWriteLeveling(PI) begin...
4182 23:19:24.729754 ==
4183 23:19:24.732246 Dram Type= 6, Freq= 0, CH_0, rank 1
4184 23:19:24.736073 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4185 23:19:24.736435 ==
4186 23:19:24.739228 Write leveling (Byte 0): 35 => 35
4187 23:19:24.742847 Write leveling (Byte 1): 31 => 31
4188 23:19:24.746075 DramcWriteLeveling(PI) end<-----
4189 23:19:24.746437
4190 23:19:24.746726 ==
4191 23:19:24.749390 Dram Type= 6, Freq= 0, CH_0, rank 1
4192 23:19:24.752556 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4193 23:19:24.752920 ==
4194 23:19:24.755777 [Gating] SW mode calibration
4195 23:19:24.762103 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4196 23:19:24.769239 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4197 23:19:24.772124 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4198 23:19:24.778423 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4199 23:19:24.782283 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4200 23:19:24.785523 0 9 12 | B1->B0 | 3434 3232 | 1 0 | (0 0) (0 0)
4201 23:19:24.791836 0 9 16 | B1->B0 | 2b2b 2a2a | 0 0 | (0 0) (0 0)
4202 23:19:24.795485 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4203 23:19:24.798817 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4204 23:19:24.805043 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4205 23:19:24.808476 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4206 23:19:24.811760 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4207 23:19:24.818690 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4208 23:19:24.821697 0 10 12 | B1->B0 | 2c2c 2424 | 0 0 | (1 1) (0 0)
4209 23:19:24.824793 0 10 16 | B1->B0 | 4141 4040 | 0 0 | (0 0) (0 0)
4210 23:19:24.828333 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4211 23:19:24.834641 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4212 23:19:24.838375 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4213 23:19:24.844810 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4214 23:19:24.847948 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4215 23:19:24.851285 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4216 23:19:24.855341 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4217 23:19:24.862023 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4218 23:19:24.865081 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4219 23:19:24.868541 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4220 23:19:24.874662 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4221 23:19:24.878469 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4222 23:19:24.881403 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4223 23:19:24.888035 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4224 23:19:24.891148 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4225 23:19:24.894544 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4226 23:19:24.901023 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4227 23:19:24.904360 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4228 23:19:24.907674 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4229 23:19:24.914552 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4230 23:19:24.917364 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4231 23:19:24.921042 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4232 23:19:24.927442 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4233 23:19:24.927545 Total UI for P1: 0, mck2ui 16
4234 23:19:24.934066 best dqsien dly found for B0: ( 0, 13, 10)
4235 23:19:24.934169 Total UI for P1: 0, mck2ui 16
4236 23:19:24.941022 best dqsien dly found for B1: ( 0, 13, 10)
4237 23:19:24.944638 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4238 23:19:24.947324 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4239 23:19:24.947557
4240 23:19:24.950535 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4241 23:19:24.953872 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4242 23:19:24.957318 [Gating] SW calibration Done
4243 23:19:24.957419 ==
4244 23:19:24.960718 Dram Type= 6, Freq= 0, CH_0, rank 1
4245 23:19:24.964060 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4246 23:19:24.964221 ==
4247 23:19:24.967486 RX Vref Scan: 0
4248 23:19:24.967581
4249 23:19:24.967659 RX Vref 0 -> 0, step: 1
4250 23:19:24.970459
4251 23:19:24.970576 RX Delay -230 -> 252, step: 16
4252 23:19:24.977112 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4253 23:19:24.980555 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4254 23:19:24.983928 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4255 23:19:24.987169 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4256 23:19:24.990999 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4257 23:19:24.997267 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4258 23:19:25.000604 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4259 23:19:25.004242 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4260 23:19:25.007354 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4261 23:19:25.014896 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4262 23:19:25.017330 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4263 23:19:25.020891 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4264 23:19:25.024495 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4265 23:19:25.030603 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4266 23:19:25.033850 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4267 23:19:25.037113 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4268 23:19:25.037543 ==
4269 23:19:25.040326 Dram Type= 6, Freq= 0, CH_0, rank 1
4270 23:19:25.043608 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4271 23:19:25.043988 ==
4272 23:19:25.047027 DQS Delay:
4273 23:19:25.047252 DQS0 = 0, DQS1 = 0
4274 23:19:25.050315 DQM Delay:
4275 23:19:25.050496 DQM0 = 47, DQM1 = 43
4276 23:19:25.050639 DQ Delay:
4277 23:19:25.053544 DQ0 =41, DQ1 =49, DQ2 =41, DQ3 =41
4278 23:19:25.057175 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4279 23:19:25.060323 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =33
4280 23:19:25.063671 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4281 23:19:25.063786
4282 23:19:25.063876
4283 23:19:25.067085 ==
4284 23:19:25.070429 Dram Type= 6, Freq= 0, CH_0, rank 1
4285 23:19:25.073365 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4286 23:19:25.073610 ==
4287 23:19:25.073749
4288 23:19:25.073838
4289 23:19:25.076559 TX Vref Scan disable
4290 23:19:25.076787 == TX Byte 0 ==
4291 23:19:25.083414 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4292 23:19:25.086695 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4293 23:19:25.086809 == TX Byte 1 ==
4294 23:19:25.093563 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4295 23:19:25.097096 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4296 23:19:25.097304 ==
4297 23:19:25.100044 Dram Type= 6, Freq= 0, CH_0, rank 1
4298 23:19:25.103592 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4299 23:19:25.103838 ==
4300 23:19:25.103979
4301 23:19:25.104105
4302 23:19:25.106832 TX Vref Scan disable
4303 23:19:25.109714 == TX Byte 0 ==
4304 23:19:25.113655 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4305 23:19:25.116344 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4306 23:19:25.119943 == TX Byte 1 ==
4307 23:19:25.123135 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4308 23:19:25.126849 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4309 23:19:25.129981
4310 23:19:25.130590 [DATLAT]
4311 23:19:25.130935 Freq=600, CH0 RK1
4312 23:19:25.131299
4313 23:19:25.133363 DATLAT Default: 0x9
4314 23:19:25.133845 0, 0xFFFF, sum = 0
4315 23:19:25.136782 1, 0xFFFF, sum = 0
4316 23:19:25.137311 2, 0xFFFF, sum = 0
4317 23:19:25.140493 3, 0xFFFF, sum = 0
4318 23:19:25.141048 4, 0xFFFF, sum = 0
4319 23:19:25.143370 5, 0xFFFF, sum = 0
4320 23:19:25.146676 6, 0xFFFF, sum = 0
4321 23:19:25.147155 7, 0xFFFF, sum = 0
4322 23:19:25.147501 8, 0x0, sum = 1
4323 23:19:25.149849 9, 0x0, sum = 2
4324 23:19:25.150311 10, 0x0, sum = 3
4325 23:19:25.153389 11, 0x0, sum = 4
4326 23:19:25.153866 best_step = 9
4327 23:19:25.154204
4328 23:19:25.154516 ==
4329 23:19:25.156397 Dram Type= 6, Freq= 0, CH_0, rank 1
4330 23:19:25.163250 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4331 23:19:25.163671 ==
4332 23:19:25.164001 RX Vref Scan: 0
4333 23:19:25.164309
4334 23:19:25.166294 RX Vref 0 -> 0, step: 1
4335 23:19:25.166706
4336 23:19:25.169644 RX Delay -163 -> 252, step: 8
4337 23:19:25.172905 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4338 23:19:25.180099 iDelay=205, Bit 1, Center 56 (-83 ~ 196) 280
4339 23:19:25.183358 iDelay=205, Bit 2, Center 52 (-91 ~ 196) 288
4340 23:19:25.186362 iDelay=205, Bit 3, Center 52 (-91 ~ 196) 288
4341 23:19:25.190218 iDelay=205, Bit 4, Center 56 (-83 ~ 196) 280
4342 23:19:25.193014 iDelay=205, Bit 5, Center 44 (-99 ~ 188) 288
4343 23:19:25.196602 iDelay=205, Bit 6, Center 60 (-75 ~ 196) 272
4344 23:19:25.203307 iDelay=205, Bit 7, Center 64 (-75 ~ 204) 280
4345 23:19:25.206338 iDelay=205, Bit 8, Center 36 (-107 ~ 180) 288
4346 23:19:25.209715 iDelay=205, Bit 9, Center 36 (-107 ~ 180) 288
4347 23:19:25.213191 iDelay=205, Bit 10, Center 48 (-91 ~ 188) 280
4348 23:19:25.219691 iDelay=205, Bit 11, Center 40 (-99 ~ 180) 280
4349 23:19:25.223093 iDelay=205, Bit 12, Center 52 (-83 ~ 188) 272
4350 23:19:25.226142 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4351 23:19:25.229384 iDelay=205, Bit 14, Center 56 (-83 ~ 196) 280
4352 23:19:25.232901 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4353 23:19:25.236686 ==
4354 23:19:25.237204 Dram Type= 6, Freq= 0, CH_0, rank 1
4355 23:19:25.243448 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4356 23:19:25.243977 ==
4357 23:19:25.244315 DQS Delay:
4358 23:19:25.246453 DQS0 = 0, DQS1 = 0
4359 23:19:25.246869 DQM Delay:
4360 23:19:25.249525 DQM0 = 54, DQM1 = 46
4361 23:19:25.249997 DQ Delay:
4362 23:19:25.252914 DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =52
4363 23:19:25.256080 DQ4 =56, DQ5 =44, DQ6 =60, DQ7 =64
4364 23:19:25.259826 DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =40
4365 23:19:25.262870 DQ12 =52, DQ13 =52, DQ14 =56, DQ15 =52
4366 23:19:25.263375
4367 23:19:25.263720
4368 23:19:25.269772 [DQSOSCAuto] RK1, (LSB)MR18= 0x5e1e, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 392 ps
4369 23:19:25.272921 CH0 RK1: MR19=808, MR18=5E1E
4370 23:19:25.279756 CH0_RK1: MR19=0x808, MR18=0x5E1E, DQSOSC=392, MR23=63, INC=170, DEC=113
4371 23:19:25.283140 [RxdqsGatingPostProcess] freq 600
4372 23:19:25.286564 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4373 23:19:25.289727 Pre-setting of DQS Precalculation
4374 23:19:25.296433 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4375 23:19:25.297005 ==
4376 23:19:25.300258 Dram Type= 6, Freq= 0, CH_1, rank 0
4377 23:19:25.303196 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4378 23:19:25.303660 ==
4379 23:19:25.310011 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4380 23:19:25.316254 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4381 23:19:25.319900 [CA 0] Center 36 (5~67) winsize 63
4382 23:19:25.323376 [CA 1] Center 36 (5~67) winsize 63
4383 23:19:25.326686 [CA 2] Center 34 (4~65) winsize 62
4384 23:19:25.329615 [CA 3] Center 34 (3~65) winsize 63
4385 23:19:25.332771 [CA 4] Center 34 (4~65) winsize 62
4386 23:19:25.336593 [CA 5] Center 34 (3~65) winsize 63
4387 23:19:25.337012
4388 23:19:25.339775 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4389 23:19:25.340298
4390 23:19:25.343101 [CATrainingPosCal] consider 1 rank data
4391 23:19:25.346431 u2DelayCellTimex100 = 270/100 ps
4392 23:19:25.349478 CA0 delay=36 (5~67),Diff = 2 PI (19 cell)
4393 23:19:25.353333 CA1 delay=36 (5~67),Diff = 2 PI (19 cell)
4394 23:19:25.356796 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4395 23:19:25.360241 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
4396 23:19:25.363358 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4397 23:19:25.366270 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4398 23:19:25.366695
4399 23:19:25.369570 CA PerBit enable=1, Macro0, CA PI delay=34
4400 23:19:25.372850
4401 23:19:25.373511 [CBTSetCACLKResult] CA Dly = 34
4402 23:19:25.376832 CS Dly: 5 (0~36)
4403 23:19:25.377352 ==
4404 23:19:25.379649 Dram Type= 6, Freq= 0, CH_1, rank 1
4405 23:19:25.383060 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4406 23:19:25.383589 ==
4407 23:19:25.389724 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4408 23:19:25.395855 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4409 23:19:25.399478 [CA 0] Center 36 (6~67) winsize 62
4410 23:19:25.402618 [CA 1] Center 36 (5~67) winsize 63
4411 23:19:25.405797 [CA 2] Center 34 (4~65) winsize 62
4412 23:19:25.409531 [CA 3] Center 34 (4~65) winsize 62
4413 23:19:25.412921 [CA 4] Center 34 (4~65) winsize 62
4414 23:19:25.415732 [CA 5] Center 34 (3~65) winsize 63
4415 23:19:25.416357
4416 23:19:25.419396 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4417 23:19:25.419815
4418 23:19:25.422847 [CATrainingPosCal] consider 2 rank data
4419 23:19:25.426098 u2DelayCellTimex100 = 270/100 ps
4420 23:19:25.429828 CA0 delay=36 (6~67),Diff = 2 PI (19 cell)
4421 23:19:25.432827 CA1 delay=36 (5~67),Diff = 2 PI (19 cell)
4422 23:19:25.436061 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4423 23:19:25.439295 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4424 23:19:25.442404 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4425 23:19:25.446052 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4426 23:19:25.446675
4427 23:19:25.452581 CA PerBit enable=1, Macro0, CA PI delay=34
4428 23:19:25.453106
4429 23:19:25.455950 [CBTSetCACLKResult] CA Dly = 34
4430 23:19:25.456474 CS Dly: 6 (0~38)
4431 23:19:25.456811
4432 23:19:25.459125 ----->DramcWriteLeveling(PI) begin...
4433 23:19:25.459662 ==
4434 23:19:25.462541 Dram Type= 6, Freq= 0, CH_1, rank 0
4435 23:19:25.466049 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4436 23:19:25.469074 ==
4437 23:19:25.469644 Write leveling (Byte 0): 32 => 32
4438 23:19:25.472123 Write leveling (Byte 1): 30 => 30
4439 23:19:25.476148 DramcWriteLeveling(PI) end<-----
4440 23:19:25.476674
4441 23:19:25.477014 ==
4442 23:19:25.479311 Dram Type= 6, Freq= 0, CH_1, rank 0
4443 23:19:25.486035 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4444 23:19:25.486565 ==
4445 23:19:25.486906 [Gating] SW mode calibration
4446 23:19:25.495647 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4447 23:19:25.499099 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4448 23:19:25.502330 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4449 23:19:25.508922 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4450 23:19:25.512231 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4451 23:19:25.515652 0 9 12 | B1->B0 | 2e2e 2c2c | 0 0 | (1 0) (0 0)
4452 23:19:25.522109 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4453 23:19:25.525759 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4454 23:19:25.529018 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4455 23:19:25.535600 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4456 23:19:25.538775 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4457 23:19:25.542161 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4458 23:19:25.549114 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4459 23:19:25.552052 0 10 12 | B1->B0 | 3434 3939 | 1 0 | (0 0) (0 0)
4460 23:19:25.555584 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4461 23:19:25.562028 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4462 23:19:25.565267 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4463 23:19:25.568639 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4464 23:19:25.574996 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4465 23:19:25.579173 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4466 23:19:25.582146 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4467 23:19:25.588637 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4468 23:19:25.591773 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4469 23:19:25.595429 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4470 23:19:25.601715 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4471 23:19:25.604951 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4472 23:19:25.608291 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4473 23:19:25.615325 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4474 23:19:25.618230 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4475 23:19:25.621217 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4476 23:19:25.628118 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4477 23:19:25.631209 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4478 23:19:25.634491 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4479 23:19:25.641641 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4480 23:19:25.644793 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4481 23:19:25.648562 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4482 23:19:25.651422 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4483 23:19:25.658533 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4484 23:19:25.661844 Total UI for P1: 0, mck2ui 16
4485 23:19:25.664836 best dqsien dly found for B0: ( 0, 13, 10)
4486 23:19:25.668151 Total UI for P1: 0, mck2ui 16
4487 23:19:25.671542 best dqsien dly found for B1: ( 0, 13, 10)
4488 23:19:25.674757 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4489 23:19:25.678161 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4490 23:19:25.678687
4491 23:19:25.681221 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4492 23:19:25.684480 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4493 23:19:25.688162 [Gating] SW calibration Done
4494 23:19:25.688700 ==
4495 23:19:25.690951 Dram Type= 6, Freq= 0, CH_1, rank 0
4496 23:19:25.695006 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4497 23:19:25.695569 ==
4498 23:19:25.698279 RX Vref Scan: 0
4499 23:19:25.698801
4500 23:19:25.701130 RX Vref 0 -> 0, step: 1
4501 23:19:25.701700
4502 23:19:25.702045 RX Delay -230 -> 252, step: 16
4503 23:19:25.707981 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4504 23:19:25.711001 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4505 23:19:25.714503 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4506 23:19:25.717945 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4507 23:19:25.724984 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4508 23:19:25.728243 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4509 23:19:25.730797 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4510 23:19:25.734267 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4511 23:19:25.737746 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4512 23:19:25.744242 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4513 23:19:25.747342 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4514 23:19:25.750959 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4515 23:19:25.754283 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4516 23:19:25.761280 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4517 23:19:25.764188 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4518 23:19:25.767875 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4519 23:19:25.768339 ==
4520 23:19:25.770817 Dram Type= 6, Freq= 0, CH_1, rank 0
4521 23:19:25.774274 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4522 23:19:25.777800 ==
4523 23:19:25.778369 DQS Delay:
4524 23:19:25.778737 DQS0 = 0, DQS1 = 0
4525 23:19:25.781226 DQM Delay:
4526 23:19:25.781721 DQM0 = 50, DQM1 = 46
4527 23:19:25.784346 DQ Delay:
4528 23:19:25.787780 DQ0 =57, DQ1 =41, DQ2 =41, DQ3 =49
4529 23:19:25.788256 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4530 23:19:25.790540 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4531 23:19:25.797421 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4532 23:19:25.798044
4533 23:19:25.798421
4534 23:19:25.798763 ==
4535 23:19:25.800708 Dram Type= 6, Freq= 0, CH_1, rank 0
4536 23:19:25.804184 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4537 23:19:25.804764 ==
4538 23:19:25.805142
4539 23:19:25.805483
4540 23:19:25.807874 TX Vref Scan disable
4541 23:19:25.808437 == TX Byte 0 ==
4542 23:19:25.814607 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4543 23:19:25.817443 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4544 23:19:25.818122 == TX Byte 1 ==
4545 23:19:25.824529 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4546 23:19:25.827825 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4547 23:19:25.828387 ==
4548 23:19:25.830879 Dram Type= 6, Freq= 0, CH_1, rank 0
4549 23:19:25.834682 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4550 23:19:25.835246 ==
4551 23:19:25.835620
4552 23:19:25.835961
4553 23:19:25.837094 TX Vref Scan disable
4554 23:19:25.840961 == TX Byte 0 ==
4555 23:19:25.843946 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4556 23:19:25.847262 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4557 23:19:25.850665 == TX Byte 1 ==
4558 23:19:25.854143 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4559 23:19:25.857572 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4560 23:19:25.860579
4561 23:19:25.861134 [DATLAT]
4562 23:19:25.861508 Freq=600, CH1 RK0
4563 23:19:25.861925
4564 23:19:25.863947 DATLAT Default: 0x9
4565 23:19:25.864406 0, 0xFFFF, sum = 0
4566 23:19:25.867146 1, 0xFFFF, sum = 0
4567 23:19:25.867613 2, 0xFFFF, sum = 0
4568 23:19:25.870243 3, 0xFFFF, sum = 0
4569 23:19:25.873525 4, 0xFFFF, sum = 0
4570 23:19:25.874133 5, 0xFFFF, sum = 0
4571 23:19:25.877030 6, 0xFFFF, sum = 0
4572 23:19:25.877647 7, 0xFFFF, sum = 0
4573 23:19:25.880701 8, 0x0, sum = 1
4574 23:19:25.881266 9, 0x0, sum = 2
4575 23:19:25.881700 10, 0x0, sum = 3
4576 23:19:25.883392 11, 0x0, sum = 4
4577 23:19:25.883873 best_step = 9
4578 23:19:25.884240
4579 23:19:25.884582 ==
4580 23:19:25.887050 Dram Type= 6, Freq= 0, CH_1, rank 0
4581 23:19:25.893448 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4582 23:19:25.894033 ==
4583 23:19:25.894407 RX Vref Scan: 1
4584 23:19:25.894750
4585 23:19:25.896905 RX Vref 0 -> 0, step: 1
4586 23:19:25.897324
4587 23:19:25.900121 RX Delay -163 -> 252, step: 8
4588 23:19:25.900682
4589 23:19:25.903477 Set Vref, RX VrefLevel [Byte0]: 54
4590 23:19:25.906757 [Byte1]: 51
4591 23:19:25.907400
4592 23:19:25.909780 Final RX Vref Byte 0 = 54 to rank0
4593 23:19:25.913162 Final RX Vref Byte 1 = 51 to rank0
4594 23:19:25.916881 Final RX Vref Byte 0 = 54 to rank1
4595 23:19:25.919837 Final RX Vref Byte 1 = 51 to rank1==
4596 23:19:25.923817 Dram Type= 6, Freq= 0, CH_1, rank 0
4597 23:19:25.926669 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4598 23:19:25.927188 ==
4599 23:19:25.930300 DQS Delay:
4600 23:19:25.930717 DQS0 = 0, DQS1 = 0
4601 23:19:25.933524 DQM Delay:
4602 23:19:25.934087 DQM0 = 48, DQM1 = 47
4603 23:19:25.934427 DQ Delay:
4604 23:19:25.936975 DQ0 =52, DQ1 =40, DQ2 =36, DQ3 =44
4605 23:19:25.939598 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4606 23:19:25.943354 DQ8 =36, DQ9 =36, DQ10 =44, DQ11 =36
4607 23:19:25.946422 DQ12 =56, DQ13 =52, DQ14 =56, DQ15 =60
4608 23:19:25.946986
4609 23:19:25.947330
4610 23:19:25.956594 [DQSOSCAuto] RK0, (LSB)MR18= 0x4166, (MSB)MR19= 0x808, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
4611 23:19:25.960324 CH1 RK0: MR19=808, MR18=4166
4612 23:19:25.963289 CH1_RK0: MR19=0x808, MR18=0x4166, DQSOSC=390, MR23=63, INC=172, DEC=114
4613 23:19:25.966948
4614 23:19:25.970067 ----->DramcWriteLeveling(PI) begin...
4615 23:19:25.970597 ==
4616 23:19:25.973090 Dram Type= 6, Freq= 0, CH_1, rank 1
4617 23:19:25.976387 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4618 23:19:25.976908 ==
4619 23:19:25.980039 Write leveling (Byte 0): 31 => 31
4620 23:19:25.982737 Write leveling (Byte 1): 31 => 31
4621 23:19:25.986674 DramcWriteLeveling(PI) end<-----
4622 23:19:25.987225
4623 23:19:25.987572 ==
4624 23:19:25.989988 Dram Type= 6, Freq= 0, CH_1, rank 1
4625 23:19:25.993181 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4626 23:19:25.993644 ==
4627 23:19:25.996586 [Gating] SW mode calibration
4628 23:19:26.002795 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4629 23:19:26.009970 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4630 23:19:26.012770 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4631 23:19:26.016299 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4632 23:19:26.023317 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
4633 23:19:26.025926 0 9 12 | B1->B0 | 2c2c 2f2f | 1 1 | (1 0) (1 0)
4634 23:19:26.029664 0 9 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4635 23:19:26.035775 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4636 23:19:26.039684 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4637 23:19:26.042995 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4638 23:19:26.049543 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4639 23:19:26.052548 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4640 23:19:26.056214 0 10 8 | B1->B0 | 2525 2626 | 1 0 | (0 0) (0 0)
4641 23:19:26.062980 0 10 12 | B1->B0 | 3838 3434 | 0 0 | (0 0) (0 0)
4642 23:19:26.066265 0 10 16 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
4643 23:19:26.069550 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4644 23:19:26.073144 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4645 23:19:26.079775 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4646 23:19:26.083043 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4647 23:19:26.086163 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4648 23:19:26.092396 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4649 23:19:26.095676 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4650 23:19:26.098801 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4651 23:19:26.105731 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4652 23:19:26.108908 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4653 23:19:26.112390 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4654 23:19:26.118744 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4655 23:19:26.122128 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4656 23:19:26.125724 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4657 23:19:26.132392 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4658 23:19:26.136052 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4659 23:19:26.139293 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4660 23:19:26.145930 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4661 23:19:26.148745 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4662 23:19:26.152236 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4663 23:19:26.158896 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4664 23:19:26.162343 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4665 23:19:26.165394 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4666 23:19:26.169263 Total UI for P1: 0, mck2ui 16
4667 23:19:26.172217 best dqsien dly found for B1: ( 0, 13, 10)
4668 23:19:26.179280 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4669 23:19:26.179849 Total UI for P1: 0, mck2ui 16
4670 23:19:26.185796 best dqsien dly found for B0: ( 0, 13, 12)
4671 23:19:26.189267 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4672 23:19:26.192012 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4673 23:19:26.192592
4674 23:19:26.195051 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4675 23:19:26.198943 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4676 23:19:26.202238 [Gating] SW calibration Done
4677 23:19:26.202834 ==
4678 23:19:26.205181 Dram Type= 6, Freq= 0, CH_1, rank 1
4679 23:19:26.208293 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4680 23:19:26.208860 ==
4681 23:19:26.212253 RX Vref Scan: 0
4682 23:19:26.212716
4683 23:19:26.213083 RX Vref 0 -> 0, step: 1
4684 23:19:26.213431
4685 23:19:26.214749 RX Delay -230 -> 252, step: 16
4686 23:19:26.221784 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4687 23:19:26.225394 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4688 23:19:26.228895 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4689 23:19:26.231627 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4690 23:19:26.235101 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4691 23:19:26.242193 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4692 23:19:26.245029 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4693 23:19:26.248235 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4694 23:19:26.251491 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4695 23:19:26.258598 iDelay=218, Bit 9, Center 41 (-118 ~ 201) 320
4696 23:19:26.261870 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4697 23:19:26.264996 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4698 23:19:26.268427 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4699 23:19:26.274880 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4700 23:19:26.277975 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4701 23:19:26.281693 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4702 23:19:26.282254 ==
4703 23:19:26.284586 Dram Type= 6, Freq= 0, CH_1, rank 1
4704 23:19:26.287645 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4705 23:19:26.288118 ==
4706 23:19:26.291872 DQS Delay:
4707 23:19:26.292442 DQS0 = 0, DQS1 = 0
4708 23:19:26.294231 DQM Delay:
4709 23:19:26.294698 DQM0 = 50, DQM1 = 48
4710 23:19:26.295066 DQ Delay:
4711 23:19:26.297948 DQ0 =49, DQ1 =49, DQ2 =33, DQ3 =49
4712 23:19:26.301554 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49
4713 23:19:26.305058 DQ8 =33, DQ9 =41, DQ10 =49, DQ11 =41
4714 23:19:26.308256 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =57
4715 23:19:26.308867
4716 23:19:26.310972
4717 23:19:26.311434 ==
4718 23:19:26.314189 Dram Type= 6, Freq= 0, CH_1, rank 1
4719 23:19:26.317783 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4720 23:19:26.318369 ==
4721 23:19:26.318749
4722 23:19:26.319092
4723 23:19:26.320888 TX Vref Scan disable
4724 23:19:26.321662 == TX Byte 0 ==
4725 23:19:26.327220 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4726 23:19:26.331000 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4727 23:19:26.331530 == TX Byte 1 ==
4728 23:19:26.337630 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4729 23:19:26.340816 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4730 23:19:26.341347 ==
4731 23:19:26.343884 Dram Type= 6, Freq= 0, CH_1, rank 1
4732 23:19:26.347263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4733 23:19:26.347797 ==
4734 23:19:26.348139
4735 23:19:26.348455
4736 23:19:26.350816 TX Vref Scan disable
4737 23:19:26.354152 == TX Byte 0 ==
4738 23:19:26.357822 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4739 23:19:26.360933 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4740 23:19:26.364376 == TX Byte 1 ==
4741 23:19:26.367835 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4742 23:19:26.370335 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4743 23:19:26.370761
4744 23:19:26.373727 [DATLAT]
4745 23:19:26.374255 Freq=600, CH1 RK1
4746 23:19:26.374597
4747 23:19:26.377375 DATLAT Default: 0x9
4748 23:19:26.377846 0, 0xFFFF, sum = 0
4749 23:19:26.381004 1, 0xFFFF, sum = 0
4750 23:19:26.381532 2, 0xFFFF, sum = 0
4751 23:19:26.383900 3, 0xFFFF, sum = 0
4752 23:19:26.384426 4, 0xFFFF, sum = 0
4753 23:19:26.387493 5, 0xFFFF, sum = 0
4754 23:19:26.388023 6, 0xFFFF, sum = 0
4755 23:19:26.390442 7, 0xFFFF, sum = 0
4756 23:19:26.390911 8, 0x0, sum = 1
4757 23:19:26.393845 9, 0x0, sum = 2
4758 23:19:26.394317 10, 0x0, sum = 3
4759 23:19:26.397340 11, 0x0, sum = 4
4760 23:19:26.397992 best_step = 9
4761 23:19:26.398369
4762 23:19:26.398711 ==
4763 23:19:26.400699 Dram Type= 6, Freq= 0, CH_1, rank 1
4764 23:19:26.407392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4765 23:19:26.407965 ==
4766 23:19:26.408340 RX Vref Scan: 0
4767 23:19:26.408681
4768 23:19:26.410208 RX Vref 0 -> 0, step: 1
4769 23:19:26.410673
4770 23:19:26.414050 RX Delay -163 -> 252, step: 8
4771 23:19:26.417295 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4772 23:19:26.420023 iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288
4773 23:19:26.426885 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4774 23:19:26.430231 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4775 23:19:26.433457 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4776 23:19:26.436961 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4777 23:19:26.440565 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4778 23:19:26.446953 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4779 23:19:26.450340 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4780 23:19:26.453889 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4781 23:19:26.456949 iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296
4782 23:19:26.463562 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4783 23:19:26.466844 iDelay=205, Bit 12, Center 52 (-99 ~ 204) 304
4784 23:19:26.470196 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4785 23:19:26.473979 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4786 23:19:26.476971 iDelay=205, Bit 15, Center 56 (-91 ~ 204) 296
4787 23:19:26.480511 ==
4788 23:19:26.481037 Dram Type= 6, Freq= 0, CH_1, rank 1
4789 23:19:26.487192 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4790 23:19:26.487720 ==
4791 23:19:26.488061 DQS Delay:
4792 23:19:26.490072 DQS0 = 0, DQS1 = 0
4793 23:19:26.490601 DQM Delay:
4794 23:19:26.493529 DQM0 = 49, DQM1 = 45
4795 23:19:26.494235 DQ Delay:
4796 23:19:26.496960 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4797 23:19:26.500482 DQ4 =48, DQ5 =60, DQ6 =60, DQ7 =48
4798 23:19:26.503285 DQ8 =32, DQ9 =32, DQ10 =48, DQ11 =40
4799 23:19:26.506510 DQ12 =52, DQ13 =52, DQ14 =48, DQ15 =56
4800 23:19:26.507040
4801 23:19:26.507377
4802 23:19:26.513469 [DQSOSCAuto] RK1, (LSB)MR18= 0x641b, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 391 ps
4803 23:19:26.516680 CH1 RK1: MR19=808, MR18=641B
4804 23:19:26.522861 CH1_RK1: MR19=0x808, MR18=0x641B, DQSOSC=391, MR23=63, INC=171, DEC=114
4805 23:19:26.526617 [RxdqsGatingPostProcess] freq 600
4806 23:19:26.533270 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4807 23:19:26.533918 Pre-setting of DQS Precalculation
4808 23:19:26.539812 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4809 23:19:26.546663 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4810 23:19:26.553510 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4811 23:19:26.554135
4812 23:19:26.554507
4813 23:19:26.556439 [Calibration Summary] 1200 Mbps
4814 23:19:26.559698 CH 0, Rank 0
4815 23:19:26.560259 SW Impedance : PASS
4816 23:19:26.563308 DUTY Scan : NO K
4817 23:19:26.566370 ZQ Calibration : PASS
4818 23:19:26.566939 Jitter Meter : NO K
4819 23:19:26.569808 CBT Training : PASS
4820 23:19:26.570446 Write leveling : PASS
4821 23:19:26.572983 RX DQS gating : PASS
4822 23:19:26.576612 RX DQ/DQS(RDDQC) : PASS
4823 23:19:26.577197 TX DQ/DQS : PASS
4824 23:19:26.579383 RX DATLAT : PASS
4825 23:19:26.582885 RX DQ/DQS(Engine): PASS
4826 23:19:26.583440 TX OE : NO K
4827 23:19:26.586078 All Pass.
4828 23:19:26.586624
4829 23:19:26.586996 CH 0, Rank 1
4830 23:19:26.589469 SW Impedance : PASS
4831 23:19:26.590066 DUTY Scan : NO K
4832 23:19:26.593009 ZQ Calibration : PASS
4833 23:19:26.596299 Jitter Meter : NO K
4834 23:19:26.596851 CBT Training : PASS
4835 23:19:26.599414 Write leveling : PASS
4836 23:19:26.602493 RX DQS gating : PASS
4837 23:19:26.602970 RX DQ/DQS(RDDQC) : PASS
4838 23:19:26.606539 TX DQ/DQS : PASS
4839 23:19:26.609256 RX DATLAT : PASS
4840 23:19:26.609845 RX DQ/DQS(Engine): PASS
4841 23:19:26.612356 TX OE : NO K
4842 23:19:26.612901 All Pass.
4843 23:19:26.613275
4844 23:19:26.615890 CH 1, Rank 0
4845 23:19:26.616401 SW Impedance : PASS
4846 23:19:26.619102 DUTY Scan : NO K
4847 23:19:26.622499 ZQ Calibration : PASS
4848 23:19:26.622924 Jitter Meter : NO K
4849 23:19:26.625870 CBT Training : PASS
4850 23:19:26.626291 Write leveling : PASS
4851 23:19:26.629234 RX DQS gating : PASS
4852 23:19:26.632344 RX DQ/DQS(RDDQC) : PASS
4853 23:19:26.632762 TX DQ/DQS : PASS
4854 23:19:26.636125 RX DATLAT : PASS
4855 23:19:26.638971 RX DQ/DQS(Engine): PASS
4856 23:19:26.639393 TX OE : NO K
4857 23:19:26.642259 All Pass.
4858 23:19:26.642677
4859 23:19:26.643010 CH 1, Rank 1
4860 23:19:26.645734 SW Impedance : PASS
4861 23:19:26.646159 DUTY Scan : NO K
4862 23:19:26.648921 ZQ Calibration : PASS
4863 23:19:26.652216 Jitter Meter : NO K
4864 23:19:26.652636 CBT Training : PASS
4865 23:19:26.656079 Write leveling : PASS
4866 23:19:26.659111 RX DQS gating : PASS
4867 23:19:26.659626 RX DQ/DQS(RDDQC) : PASS
4868 23:19:26.662287 TX DQ/DQS : PASS
4869 23:19:26.665942 RX DATLAT : PASS
4870 23:19:26.666453 RX DQ/DQS(Engine): PASS
4871 23:19:26.669290 TX OE : NO K
4872 23:19:26.669846 All Pass.
4873 23:19:26.670195
4874 23:19:26.672332 DramC Write-DBI off
4875 23:19:26.675759 PER_BANK_REFRESH: Hybrid Mode
4876 23:19:26.676273 TX_TRACKING: ON
4877 23:19:26.685524 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4878 23:19:26.689129 [FAST_K] Save calibration result to emmc
4879 23:19:26.692249 dramc_set_vcore_voltage set vcore to 662500
4880 23:19:26.695702 Read voltage for 933, 3
4881 23:19:26.696128 Vio18 = 0
4882 23:19:26.696465 Vcore = 662500
4883 23:19:26.699276 Vdram = 0
4884 23:19:26.699786 Vddq = 0
4885 23:19:26.700123 Vmddr = 0
4886 23:19:26.705817 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4887 23:19:26.708746 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4888 23:19:26.711938 MEM_TYPE=3, freq_sel=17
4889 23:19:26.715614 sv_algorithm_assistance_LP4_1600
4890 23:19:26.718853 ============ PULL DRAM RESETB DOWN ============
4891 23:19:26.721656 ========== PULL DRAM RESETB DOWN end =========
4892 23:19:26.728805 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4893 23:19:26.731828 ===================================
4894 23:19:26.732337 LPDDR4 DRAM CONFIGURATION
4895 23:19:26.735552 ===================================
4896 23:19:26.738486 EX_ROW_EN[0] = 0x0
4897 23:19:26.742043 EX_ROW_EN[1] = 0x0
4898 23:19:26.742551 LP4Y_EN = 0x0
4899 23:19:26.745025 WORK_FSP = 0x0
4900 23:19:26.745442 WL = 0x3
4901 23:19:26.748659 RL = 0x3
4902 23:19:26.749170 BL = 0x2
4903 23:19:26.751770 RPST = 0x0
4904 23:19:26.752278 RD_PRE = 0x0
4905 23:19:26.754694 WR_PRE = 0x1
4906 23:19:26.755200 WR_PST = 0x0
4907 23:19:26.758448 DBI_WR = 0x0
4908 23:19:26.758962 DBI_RD = 0x0
4909 23:19:26.762196 OTF = 0x1
4910 23:19:26.764957 ===================================
4911 23:19:26.768553 ===================================
4912 23:19:26.769060 ANA top config
4913 23:19:26.771785 ===================================
4914 23:19:26.775276 DLL_ASYNC_EN = 0
4915 23:19:26.778508 ALL_SLAVE_EN = 1
4916 23:19:26.781781 NEW_RANK_MODE = 1
4917 23:19:26.782310 DLL_IDLE_MODE = 1
4918 23:19:26.785424 LP45_APHY_COMB_EN = 1
4919 23:19:26.788805 TX_ODT_DIS = 1
4920 23:19:26.792006 NEW_8X_MODE = 1
4921 23:19:26.794965 ===================================
4922 23:19:26.798246 ===================================
4923 23:19:26.801780 data_rate = 1866
4924 23:19:26.802312 CKR = 1
4925 23:19:26.804937 DQ_P2S_RATIO = 8
4926 23:19:26.808552 ===================================
4927 23:19:26.811915 CA_P2S_RATIO = 8
4928 23:19:26.815255 DQ_CA_OPEN = 0
4929 23:19:26.818504 DQ_SEMI_OPEN = 0
4930 23:19:26.819026 CA_SEMI_OPEN = 0
4931 23:19:26.821899 CA_FULL_RATE = 0
4932 23:19:26.825097 DQ_CKDIV4_EN = 1
4933 23:19:26.828684 CA_CKDIV4_EN = 1
4934 23:19:26.831569 CA_PREDIV_EN = 0
4935 23:19:26.835511 PH8_DLY = 0
4936 23:19:26.836029 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4937 23:19:26.837925 DQ_AAMCK_DIV = 4
4938 23:19:26.841945 CA_AAMCK_DIV = 4
4939 23:19:26.845345 CA_ADMCK_DIV = 4
4940 23:19:26.848178 DQ_TRACK_CA_EN = 0
4941 23:19:26.851811 CA_PICK = 933
4942 23:19:26.854759 CA_MCKIO = 933
4943 23:19:26.855291 MCKIO_SEMI = 0
4944 23:19:26.858139 PLL_FREQ = 3732
4945 23:19:26.862163 DQ_UI_PI_RATIO = 32
4946 23:19:26.865272 CA_UI_PI_RATIO = 0
4947 23:19:26.868276 ===================================
4948 23:19:26.871719 ===================================
4949 23:19:26.874944 memory_type:LPDDR4
4950 23:19:26.875529 GP_NUM : 10
4951 23:19:26.878157 SRAM_EN : 1
4952 23:19:26.878714 MD32_EN : 0
4953 23:19:26.882240 ===================================
4954 23:19:26.885339 [ANA_INIT] >>>>>>>>>>>>>>
4955 23:19:26.888221 <<<<<< [CONFIGURE PHASE]: ANA_TX
4956 23:19:26.891847 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4957 23:19:26.894913 ===================================
4958 23:19:26.898338 data_rate = 1866,PCW = 0X8f00
4959 23:19:26.901638 ===================================
4960 23:19:26.905086 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4961 23:19:26.911586 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4962 23:19:26.915125 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4963 23:19:26.921714 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4964 23:19:26.925235 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4965 23:19:26.928182 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4966 23:19:26.928750 [ANA_INIT] flow start
4967 23:19:26.931374 [ANA_INIT] PLL >>>>>>>>
4968 23:19:26.935245 [ANA_INIT] PLL <<<<<<<<
4969 23:19:26.935811 [ANA_INIT] MIDPI >>>>>>>>
4970 23:19:26.938078 [ANA_INIT] MIDPI <<<<<<<<
4971 23:19:26.941634 [ANA_INIT] DLL >>>>>>>>
4972 23:19:26.942209 [ANA_INIT] flow end
4973 23:19:26.948491 ============ LP4 DIFF to SE enter ============
4974 23:19:26.952066 ============ LP4 DIFF to SE exit ============
4975 23:19:26.954647 [ANA_INIT] <<<<<<<<<<<<<
4976 23:19:26.955113 [Flow] Enable top DCM control >>>>>
4977 23:19:26.958447 [Flow] Enable top DCM control <<<<<
4978 23:19:26.961644 Enable DLL master slave shuffle
4979 23:19:26.968168 ==============================================================
4980 23:19:26.971283 Gating Mode config
4981 23:19:26.975060 ==============================================================
4982 23:19:26.977991 Config description:
4983 23:19:26.987526 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4984 23:19:26.994552 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4985 23:19:26.998258 SELPH_MODE 0: By rank 1: By Phase
4986 23:19:27.004426 ==============================================================
4987 23:19:27.008711 GAT_TRACK_EN = 1
4988 23:19:27.010986 RX_GATING_MODE = 2
4989 23:19:27.014820 RX_GATING_TRACK_MODE = 2
4990 23:19:27.015381 SELPH_MODE = 1
4991 23:19:27.018197 PICG_EARLY_EN = 1
4992 23:19:27.021268 VALID_LAT_VALUE = 1
4993 23:19:27.027728 ==============================================================
4994 23:19:27.031584 Enter into Gating configuration >>>>
4995 23:19:27.034154 Exit from Gating configuration <<<<
4996 23:19:27.037766 Enter into DVFS_PRE_config >>>>>
4997 23:19:27.048004 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4998 23:19:27.051400 Exit from DVFS_PRE_config <<<<<
4999 23:19:27.054660 Enter into PICG configuration >>>>
5000 23:19:27.058044 Exit from PICG configuration <<<<
5001 23:19:27.061326 [RX_INPUT] configuration >>>>>
5002 23:19:27.064300 [RX_INPUT] configuration <<<<<
5003 23:19:27.067717 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5004 23:19:27.074343 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5005 23:19:27.081399 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5006 23:19:27.087631 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5007 23:19:27.090782 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5008 23:19:27.097523 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5009 23:19:27.100953 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5010 23:19:27.107933 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5011 23:19:27.110841 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5012 23:19:27.114052 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5013 23:19:27.117542 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5014 23:19:27.123725 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5015 23:19:27.127208 ===================================
5016 23:19:27.130544 LPDDR4 DRAM CONFIGURATION
5017 23:19:27.133731 ===================================
5018 23:19:27.134167 EX_ROW_EN[0] = 0x0
5019 23:19:27.137344 EX_ROW_EN[1] = 0x0
5020 23:19:27.137805 LP4Y_EN = 0x0
5021 23:19:27.140480 WORK_FSP = 0x0
5022 23:19:27.141037 WL = 0x3
5023 23:19:27.143675 RL = 0x3
5024 23:19:27.144120 BL = 0x2
5025 23:19:27.147232 RPST = 0x0
5026 23:19:27.147650 RD_PRE = 0x0
5027 23:19:27.150661 WR_PRE = 0x1
5028 23:19:27.151078 WR_PST = 0x0
5029 23:19:27.153939 DBI_WR = 0x0
5030 23:19:27.154358 DBI_RD = 0x0
5031 23:19:27.156850 OTF = 0x1
5032 23:19:27.160558 ===================================
5033 23:19:27.163963 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5034 23:19:27.167314 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5035 23:19:27.174294 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5036 23:19:27.177320 ===================================
5037 23:19:27.177884 LPDDR4 DRAM CONFIGURATION
5038 23:19:27.180610 ===================================
5039 23:19:27.183655 EX_ROW_EN[0] = 0x10
5040 23:19:27.187388 EX_ROW_EN[1] = 0x0
5041 23:19:27.187948 LP4Y_EN = 0x0
5042 23:19:27.190235 WORK_FSP = 0x0
5043 23:19:27.190700 WL = 0x3
5044 23:19:27.193642 RL = 0x3
5045 23:19:27.194208 BL = 0x2
5046 23:19:27.196817 RPST = 0x0
5047 23:19:27.197298 RD_PRE = 0x0
5048 23:19:27.200510 WR_PRE = 0x1
5049 23:19:27.201066 WR_PST = 0x0
5050 23:19:27.203608 DBI_WR = 0x0
5051 23:19:27.204170 DBI_RD = 0x0
5052 23:19:27.207048 OTF = 0x1
5053 23:19:27.210535 ===================================
5054 23:19:27.217432 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5055 23:19:27.220890 nWR fixed to 30
5056 23:19:27.223952 [ModeRegInit_LP4] CH0 RK0
5057 23:19:27.224569 [ModeRegInit_LP4] CH0 RK1
5058 23:19:27.226880 [ModeRegInit_LP4] CH1 RK0
5059 23:19:27.230214 [ModeRegInit_LP4] CH1 RK1
5060 23:19:27.230786 match AC timing 9
5061 23:19:27.237019 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5062 23:19:27.240074 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5063 23:19:27.243624 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5064 23:19:27.250732 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5065 23:19:27.253209 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5066 23:19:27.253872 ==
5067 23:19:27.256581 Dram Type= 6, Freq= 0, CH_0, rank 0
5068 23:19:27.260135 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5069 23:19:27.260640 ==
5070 23:19:27.266921 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5071 23:19:27.273768 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5072 23:19:27.276689 [CA 0] Center 37 (6~68) winsize 63
5073 23:19:27.280046 [CA 1] Center 37 (7~68) winsize 62
5074 23:19:27.283174 [CA 2] Center 34 (4~65) winsize 62
5075 23:19:27.286976 [CA 3] Center 34 (3~65) winsize 63
5076 23:19:27.289865 [CA 4] Center 33 (3~64) winsize 62
5077 23:19:27.293248 [CA 5] Center 32 (2~63) winsize 62
5078 23:19:27.293755
5079 23:19:27.296345 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5080 23:19:27.296808
5081 23:19:27.300025 [CATrainingPosCal] consider 1 rank data
5082 23:19:27.303527 u2DelayCellTimex100 = 270/100 ps
5083 23:19:27.306443 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5084 23:19:27.309744 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5085 23:19:27.313153 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5086 23:19:27.316253 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5087 23:19:27.319678 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5088 23:19:27.326389 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5089 23:19:27.326981
5090 23:19:27.329613 CA PerBit enable=1, Macro0, CA PI delay=32
5091 23:19:27.330096
5092 23:19:27.332764 [CBTSetCACLKResult] CA Dly = 32
5093 23:19:27.333228 CS Dly: 5 (0~36)
5094 23:19:27.333638 ==
5095 23:19:27.336052 Dram Type= 6, Freq= 0, CH_0, rank 1
5096 23:19:27.339670 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5097 23:19:27.342996 ==
5098 23:19:27.346170 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5099 23:19:27.352460 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5100 23:19:27.355747 [CA 0] Center 37 (6~68) winsize 63
5101 23:19:27.359599 [CA 1] Center 37 (6~68) winsize 63
5102 23:19:27.362579 [CA 2] Center 34 (4~65) winsize 62
5103 23:19:27.366257 [CA 3] Center 34 (3~65) winsize 63
5104 23:19:27.368836 [CA 4] Center 32 (2~63) winsize 62
5105 23:19:27.372163 [CA 5] Center 32 (2~62) winsize 61
5106 23:19:27.372583
5107 23:19:27.375920 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5108 23:19:27.376458
5109 23:19:27.379606 [CATrainingPosCal] consider 2 rank data
5110 23:19:27.382844 u2DelayCellTimex100 = 270/100 ps
5111 23:19:27.385663 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5112 23:19:27.388975 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5113 23:19:27.392571 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5114 23:19:27.398928 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5115 23:19:27.402227 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5116 23:19:27.405861 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5117 23:19:27.406520
5118 23:19:27.408854 CA PerBit enable=1, Macro0, CA PI delay=32
5119 23:19:27.409400
5120 23:19:27.412220 [CBTSetCACLKResult] CA Dly = 32
5121 23:19:27.412749 CS Dly: 5 (0~37)
5122 23:19:27.413090
5123 23:19:27.415223 ----->DramcWriteLeveling(PI) begin...
5124 23:19:27.415650 ==
5125 23:19:27.418919 Dram Type= 6, Freq= 0, CH_0, rank 0
5126 23:19:27.425646 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5127 23:19:27.426169 ==
5128 23:19:27.428445 Write leveling (Byte 0): 34 => 34
5129 23:19:27.432238 Write leveling (Byte 1): 32 => 32
5130 23:19:27.435548 DramcWriteLeveling(PI) end<-----
5131 23:19:27.436012
5132 23:19:27.436380 ==
5133 23:19:27.438947 Dram Type= 6, Freq= 0, CH_0, rank 0
5134 23:19:27.442255 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5135 23:19:27.442838 ==
5136 23:19:27.445087 [Gating] SW mode calibration
5137 23:19:27.452234 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5138 23:19:27.454992 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5139 23:19:27.461918 0 14 0 | B1->B0 | 2727 3434 | 1 1 | (1 1) (1 1)
5140 23:19:27.465213 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5141 23:19:27.468349 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5142 23:19:27.475747 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5143 23:19:27.479067 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5144 23:19:27.481863 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5145 23:19:27.488686 0 14 24 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
5146 23:19:27.491950 0 14 28 | B1->B0 | 3232 2828 | 0 0 | (0 0) (1 1)
5147 23:19:27.494933 0 15 0 | B1->B0 | 2d2d 2323 | 0 0 | (0 1) (0 0)
5148 23:19:27.501497 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5149 23:19:27.505277 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5150 23:19:27.508468 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5151 23:19:27.514739 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5152 23:19:27.517751 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5153 23:19:27.521667 0 15 24 | B1->B0 | 2323 2424 | 0 1 | (0 0) (0 0)
5154 23:19:27.527955 0 15 28 | B1->B0 | 2525 3c3b | 0 1 | (0 0) (1 1)
5155 23:19:27.531843 1 0 0 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
5156 23:19:27.534733 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5157 23:19:27.542057 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5158 23:19:27.544566 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5159 23:19:27.548081 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5160 23:19:27.555209 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5161 23:19:27.558684 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5162 23:19:27.561988 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
5163 23:19:27.568359 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5164 23:19:27.571415 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5165 23:19:27.574947 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5166 23:19:27.581673 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5167 23:19:27.585283 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5168 23:19:27.588392 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5169 23:19:27.591740 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5170 23:19:27.598421 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5171 23:19:27.601718 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5172 23:19:27.604772 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5173 23:19:27.611640 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5174 23:19:27.614458 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5175 23:19:27.617656 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5176 23:19:27.624548 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5177 23:19:27.628158 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5178 23:19:27.631547 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5179 23:19:27.638048 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5180 23:19:27.641148 Total UI for P1: 0, mck2ui 16
5181 23:19:27.644444 best dqsien dly found for B0: ( 1, 2, 26)
5182 23:19:27.645005 Total UI for P1: 0, mck2ui 16
5183 23:19:27.651572 best dqsien dly found for B1: ( 1, 2, 30)
5184 23:19:27.654624 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5185 23:19:27.657967 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5186 23:19:27.658528
5187 23:19:27.661462 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5188 23:19:27.664868 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5189 23:19:27.668050 [Gating] SW calibration Done
5190 23:19:27.668607 ==
5191 23:19:27.671348 Dram Type= 6, Freq= 0, CH_0, rank 0
5192 23:19:27.674404 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5193 23:19:27.674872 ==
5194 23:19:27.677800 RX Vref Scan: 0
5195 23:19:27.678361
5196 23:19:27.678733 RX Vref 0 -> 0, step: 1
5197 23:19:27.679078
5198 23:19:27.681097 RX Delay -80 -> 252, step: 8
5199 23:19:27.684798 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5200 23:19:27.690877 iDelay=208, Bit 1, Center 103 (8 ~ 199) 192
5201 23:19:27.694550 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5202 23:19:27.697689 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5203 23:19:27.701476 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5204 23:19:27.704320 iDelay=208, Bit 5, Center 91 (0 ~ 183) 184
5205 23:19:27.707513 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5206 23:19:27.713939 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5207 23:19:27.717027 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5208 23:19:27.721222 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5209 23:19:27.724305 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5210 23:19:27.727752 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5211 23:19:27.730861 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5212 23:19:27.737325 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5213 23:19:27.740479 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5214 23:19:27.743955 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5215 23:19:27.744494 ==
5216 23:19:27.747118 Dram Type= 6, Freq= 0, CH_0, rank 0
5217 23:19:27.750558 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5218 23:19:27.751115 ==
5219 23:19:27.753987 DQS Delay:
5220 23:19:27.754443 DQS0 = 0, DQS1 = 0
5221 23:19:27.757156 DQM Delay:
5222 23:19:27.757759 DQM0 = 103, DQM1 = 95
5223 23:19:27.758136 DQ Delay:
5224 23:19:27.760990 DQ0 =103, DQ1 =103, DQ2 =99, DQ3 =99
5225 23:19:27.764225 DQ4 =103, DQ5 =91, DQ6 =111, DQ7 =115
5226 23:19:27.767564 DQ8 =87, DQ9 =87, DQ10 =95, DQ11 =91
5227 23:19:27.774322 DQ12 =99, DQ13 =103, DQ14 =103, DQ15 =99
5228 23:19:27.774866
5229 23:19:27.775233
5230 23:19:27.775573 ==
5231 23:19:27.777441 Dram Type= 6, Freq= 0, CH_0, rank 0
5232 23:19:27.780895 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5233 23:19:27.781456 ==
5234 23:19:27.781888
5235 23:19:27.782236
5236 23:19:27.783623 TX Vref Scan disable
5237 23:19:27.784079 == TX Byte 0 ==
5238 23:19:27.790872 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5239 23:19:27.793809 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5240 23:19:27.794367 == TX Byte 1 ==
5241 23:19:27.800721 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5242 23:19:27.803811 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5243 23:19:27.804373 ==
5244 23:19:27.807522 Dram Type= 6, Freq= 0, CH_0, rank 0
5245 23:19:27.810539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5246 23:19:27.811106 ==
5247 23:19:27.811476
5248 23:19:27.813688
5249 23:19:27.814146 TX Vref Scan disable
5250 23:19:27.816855 == TX Byte 0 ==
5251 23:19:27.820322 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5252 23:19:27.823286 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5253 23:19:27.827645 == TX Byte 1 ==
5254 23:19:27.830119 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5255 23:19:27.833974 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5256 23:19:27.834553
5257 23:19:27.837107 [DATLAT]
5258 23:19:27.837761 Freq=933, CH0 RK0
5259 23:19:27.838143
5260 23:19:27.840075 DATLAT Default: 0xd
5261 23:19:27.840534 0, 0xFFFF, sum = 0
5262 23:19:27.843137 1, 0xFFFF, sum = 0
5263 23:19:27.843615 2, 0xFFFF, sum = 0
5264 23:19:27.846495 3, 0xFFFF, sum = 0
5265 23:19:27.846964 4, 0xFFFF, sum = 0
5266 23:19:27.849889 5, 0xFFFF, sum = 0
5267 23:19:27.853237 6, 0xFFFF, sum = 0
5268 23:19:27.853820 7, 0xFFFF, sum = 0
5269 23:19:27.856426 8, 0xFFFF, sum = 0
5270 23:19:27.856959 9, 0xFFFF, sum = 0
5271 23:19:27.860135 10, 0x0, sum = 1
5272 23:19:27.860667 11, 0x0, sum = 2
5273 23:19:27.863017 12, 0x0, sum = 3
5274 23:19:27.863439 13, 0x0, sum = 4
5275 23:19:27.863905 best_step = 11
5276 23:19:27.864331
5277 23:19:27.866871 ==
5278 23:19:27.870227 Dram Type= 6, Freq= 0, CH_0, rank 0
5279 23:19:27.872903 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5280 23:19:27.873333 ==
5281 23:19:27.873712 RX Vref Scan: 1
5282 23:19:27.874032
5283 23:19:27.876507 RX Vref 0 -> 0, step: 1
5284 23:19:27.877013
5285 23:19:27.879207 RX Delay -45 -> 252, step: 4
5286 23:19:27.879622
5287 23:19:27.882703 Set Vref, RX VrefLevel [Byte0]: 60
5288 23:19:27.886334 [Byte1]: 48
5289 23:19:27.886852
5290 23:19:27.889844 Final RX Vref Byte 0 = 60 to rank0
5291 23:19:27.892599 Final RX Vref Byte 1 = 48 to rank0
5292 23:19:27.896779 Final RX Vref Byte 0 = 60 to rank1
5293 23:19:27.900089 Final RX Vref Byte 1 = 48 to rank1==
5294 23:19:27.903670 Dram Type= 6, Freq= 0, CH_0, rank 0
5295 23:19:27.906899 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5296 23:19:27.907414 ==
5297 23:19:27.909886 DQS Delay:
5298 23:19:27.910403 DQS0 = 0, DQS1 = 0
5299 23:19:27.913220 DQM Delay:
5300 23:19:27.913783 DQM0 = 104, DQM1 = 95
5301 23:19:27.916574 DQ Delay:
5302 23:19:27.920246 DQ0 =100, DQ1 =106, DQ2 =102, DQ3 =100
5303 23:19:27.922935 DQ4 =106, DQ5 =98, DQ6 =112, DQ7 =112
5304 23:19:27.926261 DQ8 =84, DQ9 =84, DQ10 =94, DQ11 =92
5305 23:19:27.929243 DQ12 =100, DQ13 =100, DQ14 =104, DQ15 =102
5306 23:19:27.929702
5307 23:19:27.930039
5308 23:19:27.936008 [DQSOSCAuto] RK0, (LSB)MR18= 0x3028, (MSB)MR19= 0x505, tDQSOscB0 = 409 ps tDQSOscB1 = 406 ps
5309 23:19:27.939885 CH0 RK0: MR19=505, MR18=3028
5310 23:19:27.946067 CH0_RK0: MR19=0x505, MR18=0x3028, DQSOSC=406, MR23=63, INC=65, DEC=43
5311 23:19:27.946484
5312 23:19:27.949509 ----->DramcWriteLeveling(PI) begin...
5313 23:19:27.950098 ==
5314 23:19:27.953097 Dram Type= 6, Freq= 0, CH_0, rank 1
5315 23:19:27.956142 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5316 23:19:27.956561 ==
5317 23:19:27.959568 Write leveling (Byte 0): 34 => 34
5318 23:19:27.962680 Write leveling (Byte 1): 27 => 27
5319 23:19:27.966526 DramcWriteLeveling(PI) end<-----
5320 23:19:27.967076
5321 23:19:27.967437 ==
5322 23:19:27.969739 Dram Type= 6, Freq= 0, CH_0, rank 1
5323 23:19:27.973123 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5324 23:19:27.973802 ==
5325 23:19:27.976195 [Gating] SW mode calibration
5326 23:19:27.982870 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5327 23:19:27.989762 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5328 23:19:27.992816 0 14 0 | B1->B0 | 3333 3232 | 1 1 | (0 0) (0 0)
5329 23:19:27.999788 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5330 23:19:28.002709 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5331 23:19:28.005894 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5332 23:19:28.012781 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5333 23:19:28.016031 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5334 23:19:28.019790 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5335 23:19:28.022984 0 14 28 | B1->B0 | 2323 2626 | 0 0 | (0 0) (1 0)
5336 23:19:28.029172 0 15 0 | B1->B0 | 2626 2727 | 1 0 | (1 0) (1 0)
5337 23:19:28.032937 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5338 23:19:28.036196 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5339 23:19:28.042796 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5340 23:19:28.045558 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5341 23:19:28.049245 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5342 23:19:28.055632 0 15 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5343 23:19:28.059389 0 15 28 | B1->B0 | 3b3b 3939 | 0 0 | (0 0) (0 0)
5344 23:19:28.062570 1 0 0 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
5345 23:19:28.068964 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5346 23:19:28.072520 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5347 23:19:28.076230 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5348 23:19:28.082571 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5349 23:19:28.086017 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5350 23:19:28.089405 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5351 23:19:28.095356 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5352 23:19:28.099543 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5353 23:19:28.102468 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5354 23:19:28.109161 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5355 23:19:28.112347 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5356 23:19:28.115596 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5357 23:19:28.122256 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5358 23:19:28.125711 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5359 23:19:28.128512 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5360 23:19:28.135182 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5361 23:19:28.138496 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5362 23:19:28.141704 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5363 23:19:28.148966 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5364 23:19:28.152196 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5365 23:19:28.154910 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5366 23:19:28.161924 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5367 23:19:28.165058 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5368 23:19:28.168787 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5369 23:19:28.171898 Total UI for P1: 0, mck2ui 16
5370 23:19:28.175141 best dqsien dly found for B1: ( 1, 2, 30)
5371 23:19:28.181571 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5372 23:19:28.182043 Total UI for P1: 0, mck2ui 16
5373 23:19:28.185032 best dqsien dly found for B0: ( 1, 2, 30)
5374 23:19:28.188921 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5375 23:19:28.195509 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5376 23:19:28.196031
5377 23:19:28.198606 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5378 23:19:28.201914 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5379 23:19:28.205406 [Gating] SW calibration Done
5380 23:19:28.206030 ==
5381 23:19:28.209105 Dram Type= 6, Freq= 0, CH_0, rank 1
5382 23:19:28.211785 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5383 23:19:28.212304 ==
5384 23:19:28.215054 RX Vref Scan: 0
5385 23:19:28.215512
5386 23:19:28.215859 RX Vref 0 -> 0, step: 1
5387 23:19:28.216167
5388 23:19:28.218598 RX Delay -80 -> 252, step: 8
5389 23:19:28.221940 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5390 23:19:28.228346 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5391 23:19:28.231619 iDelay=208, Bit 2, Center 107 (16 ~ 199) 184
5392 23:19:28.234928 iDelay=208, Bit 3, Center 103 (16 ~ 191) 176
5393 23:19:28.238117 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5394 23:19:28.241607 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5395 23:19:28.245169 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5396 23:19:28.251707 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5397 23:19:28.255016 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5398 23:19:28.257915 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5399 23:19:28.262057 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5400 23:19:28.264606 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5401 23:19:28.271502 iDelay=208, Bit 12, Center 99 (16 ~ 183) 168
5402 23:19:28.275529 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5403 23:19:28.278315 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5404 23:19:28.281665 iDelay=208, Bit 15, Center 103 (16 ~ 191) 176
5405 23:19:28.282227 ==
5406 23:19:28.285052 Dram Type= 6, Freq= 0, CH_0, rank 1
5407 23:19:28.288282 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5408 23:19:28.291413 ==
5409 23:19:28.291872 DQS Delay:
5410 23:19:28.292238 DQS0 = 0, DQS1 = 0
5411 23:19:28.294892 DQM Delay:
5412 23:19:28.295494 DQM0 = 106, DQM1 = 95
5413 23:19:28.297818 DQ Delay:
5414 23:19:28.301365 DQ0 =107, DQ1 =107, DQ2 =107, DQ3 =103
5415 23:19:28.304876 DQ4 =107, DQ5 =95, DQ6 =107, DQ7 =115
5416 23:19:28.308458 DQ8 =87, DQ9 =87, DQ10 =95, DQ11 =87
5417 23:19:28.311516 DQ12 =99, DQ13 =103, DQ14 =103, DQ15 =103
5418 23:19:28.312074
5419 23:19:28.312441
5420 23:19:28.312778 ==
5421 23:19:28.314896 Dram Type= 6, Freq= 0, CH_0, rank 1
5422 23:19:28.318152 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5423 23:19:28.318617 ==
5424 23:19:28.318982
5425 23:19:28.319369
5426 23:19:28.321675 TX Vref Scan disable
5427 23:19:28.324780 == TX Byte 0 ==
5428 23:19:28.328509 Update DQ dly =719 (2 ,6, 15) DQ OEN =(2 ,3)
5429 23:19:28.332061 Update DQM dly =719 (2 ,6, 15) DQM OEN =(2 ,3)
5430 23:19:28.334510 == TX Byte 1 ==
5431 23:19:28.338015 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5432 23:19:28.341567 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5433 23:19:28.342180 ==
5434 23:19:28.345151 Dram Type= 6, Freq= 0, CH_0, rank 1
5435 23:19:28.348312 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5436 23:19:28.351144 ==
5437 23:19:28.351609
5438 23:19:28.351972
5439 23:19:28.352306 TX Vref Scan disable
5440 23:19:28.354774 == TX Byte 0 ==
5441 23:19:28.358249 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5442 23:19:28.364786 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5443 23:19:28.365309 == TX Byte 1 ==
5444 23:19:28.368236 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5445 23:19:28.374689 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5446 23:19:28.375188
5447 23:19:28.375517 [DATLAT]
5448 23:19:28.375824 Freq=933, CH0 RK1
5449 23:19:28.376148
5450 23:19:28.378192 DATLAT Default: 0xb
5451 23:19:28.378864 0, 0xFFFF, sum = 0
5452 23:19:28.381462 1, 0xFFFF, sum = 0
5453 23:19:28.382039 2, 0xFFFF, sum = 0
5454 23:19:28.384882 3, 0xFFFF, sum = 0
5455 23:19:28.388349 4, 0xFFFF, sum = 0
5456 23:19:28.388887 5, 0xFFFF, sum = 0
5457 23:19:28.391909 6, 0xFFFF, sum = 0
5458 23:19:28.392433 7, 0xFFFF, sum = 0
5459 23:19:28.394509 8, 0xFFFF, sum = 0
5460 23:19:28.394977 9, 0xFFFF, sum = 0
5461 23:19:28.397824 10, 0x0, sum = 1
5462 23:19:28.398245 11, 0x0, sum = 2
5463 23:19:28.401184 12, 0x0, sum = 3
5464 23:19:28.401740 13, 0x0, sum = 4
5465 23:19:28.402089 best_step = 11
5466 23:19:28.402398
5467 23:19:28.404607 ==
5468 23:19:28.408436 Dram Type= 6, Freq= 0, CH_0, rank 1
5469 23:19:28.411719 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5470 23:19:28.412244 ==
5471 23:19:28.412579 RX Vref Scan: 0
5472 23:19:28.412888
5473 23:19:28.414999 RX Vref 0 -> 0, step: 1
5474 23:19:28.415563
5475 23:19:28.418080 RX Delay -45 -> 252, step: 4
5476 23:19:28.421402 iDelay=199, Bit 0, Center 104 (15 ~ 194) 180
5477 23:19:28.428610 iDelay=199, Bit 1, Center 106 (23 ~ 190) 168
5478 23:19:28.431385 iDelay=199, Bit 2, Center 102 (15 ~ 190) 176
5479 23:19:28.434555 iDelay=199, Bit 3, Center 102 (15 ~ 190) 176
5480 23:19:28.437734 iDelay=199, Bit 4, Center 106 (19 ~ 194) 176
5481 23:19:28.441744 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5482 23:19:28.448397 iDelay=199, Bit 6, Center 112 (27 ~ 198) 172
5483 23:19:28.451126 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5484 23:19:28.454624 iDelay=199, Bit 8, Center 86 (3 ~ 170) 168
5485 23:19:28.457873 iDelay=199, Bit 9, Center 82 (-1 ~ 166) 168
5486 23:19:28.461133 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5487 23:19:28.464933 iDelay=199, Bit 11, Center 88 (7 ~ 170) 164
5488 23:19:28.471324 iDelay=199, Bit 12, Center 100 (19 ~ 182) 164
5489 23:19:28.474456 iDelay=199, Bit 13, Center 98 (15 ~ 182) 168
5490 23:19:28.477983 iDelay=199, Bit 14, Center 102 (19 ~ 186) 168
5491 23:19:28.481321 iDelay=199, Bit 15, Center 102 (19 ~ 186) 168
5492 23:19:28.481931 ==
5493 23:19:28.485001 Dram Type= 6, Freq= 0, CH_0, rank 1
5494 23:19:28.491298 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5495 23:19:28.491860 ==
5496 23:19:28.492225 DQS Delay:
5497 23:19:28.494209 DQS0 = 0, DQS1 = 0
5498 23:19:28.494670 DQM Delay:
5499 23:19:28.495033 DQM0 = 105, DQM1 = 94
5500 23:19:28.497408 DQ Delay:
5501 23:19:28.501103 DQ0 =104, DQ1 =106, DQ2 =102, DQ3 =102
5502 23:19:28.504759 DQ4 =106, DQ5 =98, DQ6 =112, DQ7 =112
5503 23:19:28.507776 DQ8 =86, DQ9 =82, DQ10 =94, DQ11 =88
5504 23:19:28.511029 DQ12 =100, DQ13 =98, DQ14 =102, DQ15 =102
5505 23:19:28.511592
5506 23:19:28.511956
5507 23:19:28.517433 [DQSOSCAuto] RK1, (LSB)MR18= 0x2b04, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 408 ps
5508 23:19:28.521123 CH0 RK1: MR19=505, MR18=2B04
5509 23:19:28.527522 CH0_RK1: MR19=0x505, MR18=0x2B04, DQSOSC=408, MR23=63, INC=65, DEC=43
5510 23:19:28.531174 [RxdqsGatingPostProcess] freq 933
5511 23:19:28.537300 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5512 23:19:28.540902 best DQS0 dly(2T, 0.5T) = (0, 10)
5513 23:19:28.541529 best DQS1 dly(2T, 0.5T) = (0, 10)
5514 23:19:28.544288 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5515 23:19:28.547693 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5516 23:19:28.551115 best DQS0 dly(2T, 0.5T) = (0, 10)
5517 23:19:28.554540 best DQS1 dly(2T, 0.5T) = (0, 10)
5518 23:19:28.557645 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5519 23:19:28.560829 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5520 23:19:28.563900 Pre-setting of DQS Precalculation
5521 23:19:28.571296 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5522 23:19:28.571845 ==
5523 23:19:28.573828 Dram Type= 6, Freq= 0, CH_1, rank 0
5524 23:19:28.577683 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5525 23:19:28.578248 ==
5526 23:19:28.584560 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5527 23:19:28.587948 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5528 23:19:28.591813 [CA 0] Center 36 (6~67) winsize 62
5529 23:19:28.595255 [CA 1] Center 37 (6~68) winsize 63
5530 23:19:28.598018 [CA 2] Center 35 (5~65) winsize 61
5531 23:19:28.601617 [CA 3] Center 34 (4~65) winsize 62
5532 23:19:28.604780 [CA 4] Center 34 (4~65) winsize 62
5533 23:19:28.608637 [CA 5] Center 33 (3~64) winsize 62
5534 23:19:28.609192
5535 23:19:28.611571 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5536 23:19:28.612250
5537 23:19:28.614865 [CATrainingPosCal] consider 1 rank data
5538 23:19:28.617923 u2DelayCellTimex100 = 270/100 ps
5539 23:19:28.622004 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5540 23:19:28.624889 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5541 23:19:28.631087 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5542 23:19:28.634585 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5543 23:19:28.637937 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5544 23:19:28.641339 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5545 23:19:28.642008
5546 23:19:28.644803 CA PerBit enable=1, Macro0, CA PI delay=33
5547 23:19:28.645358
5548 23:19:28.647981 [CBTSetCACLKResult] CA Dly = 33
5549 23:19:28.648509 CS Dly: 6 (0~37)
5550 23:19:28.651878 ==
5551 23:19:28.652401 Dram Type= 6, Freq= 0, CH_1, rank 1
5552 23:19:28.658248 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5553 23:19:28.658787 ==
5554 23:19:28.661690 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5555 23:19:28.667939 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5556 23:19:28.671871 [CA 0] Center 36 (6~67) winsize 62
5557 23:19:28.674649 [CA 1] Center 37 (6~68) winsize 63
5558 23:19:28.678269 [CA 2] Center 35 (5~65) winsize 61
5559 23:19:28.681522 [CA 3] Center 34 (4~65) winsize 62
5560 23:19:28.685008 [CA 4] Center 34 (4~65) winsize 62
5561 23:19:28.688211 [CA 5] Center 33 (3~64) winsize 62
5562 23:19:28.688730
5563 23:19:28.691767 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5564 23:19:28.692286
5565 23:19:28.694961 [CATrainingPosCal] consider 2 rank data
5566 23:19:28.697831 u2DelayCellTimex100 = 270/100 ps
5567 23:19:28.702107 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5568 23:19:28.704541 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5569 23:19:28.711428 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5570 23:19:28.715089 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5571 23:19:28.717968 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5572 23:19:28.720923 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5573 23:19:28.721362
5574 23:19:28.724341 CA PerBit enable=1, Macro0, CA PI delay=33
5575 23:19:28.724817
5576 23:19:28.727796 [CBTSetCACLKResult] CA Dly = 33
5577 23:19:28.728212 CS Dly: 7 (0~40)
5578 23:19:28.731262
5579 23:19:28.731673 ----->DramcWriteLeveling(PI) begin...
5580 23:19:28.734544 ==
5581 23:19:28.738261 Dram Type= 6, Freq= 0, CH_1, rank 0
5582 23:19:28.741237 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5583 23:19:28.741788 ==
5584 23:19:28.744445 Write leveling (Byte 0): 27 => 27
5585 23:19:28.748329 Write leveling (Byte 1): 29 => 29
5586 23:19:28.751642 DramcWriteLeveling(PI) end<-----
5587 23:19:28.752158
5588 23:19:28.752492 ==
5589 23:19:28.754162 Dram Type= 6, Freq= 0, CH_1, rank 0
5590 23:19:28.757751 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5591 23:19:28.758440 ==
5592 23:19:28.761040 [Gating] SW mode calibration
5593 23:19:28.768149 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5594 23:19:28.774792 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5595 23:19:28.777945 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5596 23:19:28.781174 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5597 23:19:28.787935 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5598 23:19:28.790722 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5599 23:19:28.794595 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5600 23:19:28.801485 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5601 23:19:28.804874 0 14 24 | B1->B0 | 3434 2f2f | 1 1 | (1 0) (1 0)
5602 23:19:28.807656 0 14 28 | B1->B0 | 2e2e 2323 | 0 0 | (0 0) (0 0)
5603 23:19:28.814340 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5604 23:19:28.817734 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5605 23:19:28.821164 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5606 23:19:28.824104 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5607 23:19:28.830978 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5608 23:19:28.834325 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5609 23:19:28.837479 0 15 24 | B1->B0 | 2525 3030 | 0 0 | (0 0) (0 0)
5610 23:19:28.844307 0 15 28 | B1->B0 | 3b3b 4545 | 0 0 | (0 0) (0 0)
5611 23:19:28.847204 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5612 23:19:28.851068 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5613 23:19:28.857693 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5614 23:19:28.860887 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5615 23:19:28.864210 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5616 23:19:28.871002 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5617 23:19:28.874364 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5618 23:19:28.877158 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5619 23:19:28.884374 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5620 23:19:28.887705 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5621 23:19:28.891017 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5622 23:19:28.897742 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5623 23:19:28.900557 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5624 23:19:28.904492 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5625 23:19:28.910940 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5626 23:19:28.914400 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5627 23:19:28.917514 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5628 23:19:28.923654 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5629 23:19:28.927239 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5630 23:19:28.930930 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5631 23:19:28.936993 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5632 23:19:28.940567 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5633 23:19:28.944230 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5634 23:19:28.946908 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5635 23:19:28.954017 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5636 23:19:28.957710 Total UI for P1: 0, mck2ui 16
5637 23:19:28.960149 best dqsien dly found for B0: ( 1, 2, 26)
5638 23:19:28.964199 Total UI for P1: 0, mck2ui 16
5639 23:19:28.966869 best dqsien dly found for B1: ( 1, 2, 26)
5640 23:19:28.970414 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5641 23:19:28.973362 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5642 23:19:28.974007
5643 23:19:28.976947 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5644 23:19:28.980546 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5645 23:19:28.983563 [Gating] SW calibration Done
5646 23:19:28.984022 ==
5647 23:19:28.986976 Dram Type= 6, Freq= 0, CH_1, rank 0
5648 23:19:28.990078 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5649 23:19:28.990544 ==
5650 23:19:28.993446 RX Vref Scan: 0
5651 23:19:28.993929
5652 23:19:28.996740 RX Vref 0 -> 0, step: 1
5653 23:19:28.997400
5654 23:19:28.997904 RX Delay -80 -> 252, step: 8
5655 23:19:29.003517 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5656 23:19:29.006818 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5657 23:19:29.010497 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5658 23:19:29.013966 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5659 23:19:29.016702 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5660 23:19:29.020105 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5661 23:19:29.026262 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5662 23:19:29.029676 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5663 23:19:29.033768 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5664 23:19:29.036617 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5665 23:19:29.039884 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5666 23:19:29.045978 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5667 23:19:29.049810 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5668 23:19:29.052990 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5669 23:19:29.056024 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5670 23:19:29.059299 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5671 23:19:29.059863 ==
5672 23:19:29.063245 Dram Type= 6, Freq= 0, CH_1, rank 0
5673 23:19:29.069817 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5674 23:19:29.070374 ==
5675 23:19:29.070772 DQS Delay:
5676 23:19:29.073236 DQS0 = 0, DQS1 = 0
5677 23:19:29.073864 DQM Delay:
5678 23:19:29.076264 DQM0 = 102, DQM1 = 98
5679 23:19:29.076763 DQ Delay:
5680 23:19:29.079558 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
5681 23:19:29.083111 DQ4 =99, DQ5 =115, DQ6 =111, DQ7 =103
5682 23:19:29.086368 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =91
5683 23:19:29.089649 DQ12 =107, DQ13 =103, DQ14 =103, DQ15 =107
5684 23:19:29.090203
5685 23:19:29.090569
5686 23:19:29.090906 ==
5687 23:19:29.093130 Dram Type= 6, Freq= 0, CH_1, rank 0
5688 23:19:29.096606 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5689 23:19:29.097174 ==
5690 23:19:29.097687
5691 23:19:29.098049
5692 23:19:29.099405 TX Vref Scan disable
5693 23:19:29.103145 == TX Byte 0 ==
5694 23:19:29.106243 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5695 23:19:29.109427 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5696 23:19:29.112778 == TX Byte 1 ==
5697 23:19:29.116034 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5698 23:19:29.119304 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5699 23:19:29.119738 ==
5700 23:19:29.123070 Dram Type= 6, Freq= 0, CH_1, rank 0
5701 23:19:29.129980 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5702 23:19:29.130516 ==
5703 23:19:29.130963
5704 23:19:29.131481
5705 23:19:29.131888 TX Vref Scan disable
5706 23:19:29.133660 == TX Byte 0 ==
5707 23:19:29.137208 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5708 23:19:29.144045 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5709 23:19:29.144570 == TX Byte 1 ==
5710 23:19:29.146483 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5711 23:19:29.153687 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5712 23:19:29.154217
5713 23:19:29.154551 [DATLAT]
5714 23:19:29.154861 Freq=933, CH1 RK0
5715 23:19:29.155160
5716 23:19:29.156259 DATLAT Default: 0xd
5717 23:19:29.156676 0, 0xFFFF, sum = 0
5718 23:19:29.159447 1, 0xFFFF, sum = 0
5719 23:19:29.163226 2, 0xFFFF, sum = 0
5720 23:19:29.163649 3, 0xFFFF, sum = 0
5721 23:19:29.166750 4, 0xFFFF, sum = 0
5722 23:19:29.167293 5, 0xFFFF, sum = 0
5723 23:19:29.169621 6, 0xFFFF, sum = 0
5724 23:19:29.170136 7, 0xFFFF, sum = 0
5725 23:19:29.173158 8, 0xFFFF, sum = 0
5726 23:19:29.173730 9, 0xFFFF, sum = 0
5727 23:19:29.176461 10, 0x0, sum = 1
5728 23:19:29.176883 11, 0x0, sum = 2
5729 23:19:29.179964 12, 0x0, sum = 3
5730 23:19:29.180831 13, 0x0, sum = 4
5731 23:19:29.181256 best_step = 11
5732 23:19:29.181618
5733 23:19:29.182694 ==
5734 23:19:29.186112 Dram Type= 6, Freq= 0, CH_1, rank 0
5735 23:19:29.190060 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5736 23:19:29.190562 ==
5737 23:19:29.191038 RX Vref Scan: 1
5738 23:19:29.191651
5739 23:19:29.193201 RX Vref 0 -> 0, step: 1
5740 23:19:29.193921
5741 23:19:29.196396 RX Delay -45 -> 252, step: 4
5742 23:19:29.197082
5743 23:19:29.199167 Set Vref, RX VrefLevel [Byte0]: 54
5744 23:19:29.202615 [Byte1]: 51
5745 23:19:29.203247
5746 23:19:29.206158 Final RX Vref Byte 0 = 54 to rank0
5747 23:19:29.209614 Final RX Vref Byte 1 = 51 to rank0
5748 23:19:29.212949 Final RX Vref Byte 0 = 54 to rank1
5749 23:19:29.215908 Final RX Vref Byte 1 = 51 to rank1==
5750 23:19:29.219359 Dram Type= 6, Freq= 0, CH_1, rank 0
5751 23:19:29.222743 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5752 23:19:29.226152 ==
5753 23:19:29.226646 DQS Delay:
5754 23:19:29.226990 DQS0 = 0, DQS1 = 0
5755 23:19:29.229468 DQM Delay:
5756 23:19:29.229941 DQM0 = 103, DQM1 = 98
5757 23:19:29.232313 DQ Delay:
5758 23:19:29.236315 DQ0 =106, DQ1 =96, DQ2 =94, DQ3 =102
5759 23:19:29.239434 DQ4 =104, DQ5 =112, DQ6 =110, DQ7 =102
5760 23:19:29.242946 DQ8 =88, DQ9 =90, DQ10 =100, DQ11 =94
5761 23:19:29.246151 DQ12 =104, DQ13 =102, DQ14 =106, DQ15 =106
5762 23:19:29.246571
5763 23:19:29.246901
5764 23:19:29.252940 [DQSOSCAuto] RK0, (LSB)MR18= 0x1830, (MSB)MR19= 0x505, tDQSOscB0 = 406 ps tDQSOscB1 = 414 ps
5765 23:19:29.256316 CH1 RK0: MR19=505, MR18=1830
5766 23:19:29.262594 CH1_RK0: MR19=0x505, MR18=0x1830, DQSOSC=406, MR23=63, INC=65, DEC=43
5767 23:19:29.263018
5768 23:19:29.265829 ----->DramcWriteLeveling(PI) begin...
5769 23:19:29.266375 ==
5770 23:19:29.269194 Dram Type= 6, Freq= 0, CH_1, rank 1
5771 23:19:29.272991 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5772 23:19:29.273509 ==
5773 23:19:29.275990 Write leveling (Byte 0): 27 => 27
5774 23:19:29.279582 Write leveling (Byte 1): 26 => 26
5775 23:19:29.282719 DramcWriteLeveling(PI) end<-----
5776 23:19:29.283227
5777 23:19:29.283556 ==
5778 23:19:29.286287 Dram Type= 6, Freq= 0, CH_1, rank 1
5779 23:19:29.288802 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5780 23:19:29.292303 ==
5781 23:19:29.292765 [Gating] SW mode calibration
5782 23:19:29.302831 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5783 23:19:29.305714 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5784 23:19:29.308796 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5785 23:19:29.315546 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5786 23:19:29.319036 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5787 23:19:29.322134 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5788 23:19:29.328924 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5789 23:19:29.332313 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
5790 23:19:29.335625 0 14 24 | B1->B0 | 2e2e 3030 | 1 1 | (1 0) (1 1)
5791 23:19:29.342309 0 14 28 | B1->B0 | 2323 2424 | 0 1 | (1 0) (1 0)
5792 23:19:29.345170 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5793 23:19:29.348777 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5794 23:19:29.355452 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5795 23:19:29.358982 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5796 23:19:29.361865 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5797 23:19:29.369036 0 15 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5798 23:19:29.372308 0 15 24 | B1->B0 | 3535 2525 | 0 0 | (1 1) (0 0)
5799 23:19:29.375491 0 15 28 | B1->B0 | 4646 3e3e | 0 0 | (0 0) (1 1)
5800 23:19:29.382099 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5801 23:19:29.385222 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5802 23:19:29.388373 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5803 23:19:29.395395 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5804 23:19:29.398841 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5805 23:19:29.401835 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5806 23:19:29.408729 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5807 23:19:29.412111 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5808 23:19:29.415446 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5809 23:19:29.421563 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5810 23:19:29.425527 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5811 23:19:29.428385 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5812 23:19:29.435423 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5813 23:19:29.438055 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5814 23:19:29.441445 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5815 23:19:29.448653 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5816 23:19:29.451754 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5817 23:19:29.454696 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5818 23:19:29.461279 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5819 23:19:29.465064 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5820 23:19:29.468126 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5821 23:19:29.471306 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5822 23:19:29.478089 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5823 23:19:29.482189 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5824 23:19:29.484818 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5825 23:19:29.487806 Total UI for P1: 0, mck2ui 16
5826 23:19:29.491716 best dqsien dly found for B0: ( 1, 2, 26)
5827 23:19:29.494500 Total UI for P1: 0, mck2ui 16
5828 23:19:29.497955 best dqsien dly found for B1: ( 1, 2, 26)
5829 23:19:29.501027 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5830 23:19:29.504746 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5831 23:19:29.505303
5832 23:19:29.511031 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5833 23:19:29.514648 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5834 23:19:29.517888 [Gating] SW calibration Done
5835 23:19:29.518553 ==
5836 23:19:29.521037 Dram Type= 6, Freq= 0, CH_1, rank 1
5837 23:19:29.524619 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5838 23:19:29.525180 ==
5839 23:19:29.525548 RX Vref Scan: 0
5840 23:19:29.527705
5841 23:19:29.528160 RX Vref 0 -> 0, step: 1
5842 23:19:29.528526
5843 23:19:29.531032 RX Delay -80 -> 252, step: 8
5844 23:19:29.534568 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5845 23:19:29.538514 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5846 23:19:29.544600 iDelay=208, Bit 2, Center 95 (8 ~ 183) 176
5847 23:19:29.548224 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5848 23:19:29.550756 iDelay=208, Bit 4, Center 95 (8 ~ 183) 176
5849 23:19:29.554348 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5850 23:19:29.557457 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5851 23:19:29.560789 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5852 23:19:29.564761 iDelay=208, Bit 8, Center 91 (0 ~ 183) 184
5853 23:19:29.571205 iDelay=208, Bit 9, Center 91 (0 ~ 183) 184
5854 23:19:29.574351 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5855 23:19:29.577322 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5856 23:19:29.581080 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5857 23:19:29.584659 iDelay=208, Bit 13, Center 107 (16 ~ 199) 184
5858 23:19:29.590572 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5859 23:19:29.594028 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5860 23:19:29.594593 ==
5861 23:19:29.597323 Dram Type= 6, Freq= 0, CH_1, rank 1
5862 23:19:29.600561 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5863 23:19:29.601020 ==
5864 23:19:29.604090 DQS Delay:
5865 23:19:29.604548 DQS0 = 0, DQS1 = 0
5866 23:19:29.604914 DQM Delay:
5867 23:19:29.607161 DQM0 = 102, DQM1 = 99
5868 23:19:29.607623 DQ Delay:
5869 23:19:29.610442 DQ0 =107, DQ1 =99, DQ2 =95, DQ3 =99
5870 23:19:29.613935 DQ4 =95, DQ5 =115, DQ6 =111, DQ7 =99
5871 23:19:29.617186 DQ8 =91, DQ9 =91, DQ10 =99, DQ11 =91
5872 23:19:29.620550 DQ12 =107, DQ13 =107, DQ14 =103, DQ15 =107
5873 23:19:29.621007
5874 23:19:29.621371
5875 23:19:29.624330 ==
5876 23:19:29.627080 Dram Type= 6, Freq= 0, CH_1, rank 1
5877 23:19:29.630419 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5878 23:19:29.630881 ==
5879 23:19:29.631246
5880 23:19:29.631583
5881 23:19:29.633678 TX Vref Scan disable
5882 23:19:29.634158 == TX Byte 0 ==
5883 23:19:29.640433 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5884 23:19:29.643715 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5885 23:19:29.644339 == TX Byte 1 ==
5886 23:19:29.650298 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5887 23:19:29.654229 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5888 23:19:29.654792 ==
5889 23:19:29.657312 Dram Type= 6, Freq= 0, CH_1, rank 1
5890 23:19:29.660931 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5891 23:19:29.661554 ==
5892 23:19:29.661978
5893 23:19:29.662316
5894 23:19:29.663989 TX Vref Scan disable
5895 23:19:29.667459 == TX Byte 0 ==
5896 23:19:29.670898 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5897 23:19:29.674269 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5898 23:19:29.676945 == TX Byte 1 ==
5899 23:19:29.680795 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5900 23:19:29.683552 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5901 23:19:29.683993
5902 23:19:29.687393 [DATLAT]
5903 23:19:29.687906 Freq=933, CH1 RK1
5904 23:19:29.688238
5905 23:19:29.690158 DATLAT Default: 0xb
5906 23:19:29.690572 0, 0xFFFF, sum = 0
5907 23:19:29.694334 1, 0xFFFF, sum = 0
5908 23:19:29.694859 2, 0xFFFF, sum = 0
5909 23:19:29.697566 3, 0xFFFF, sum = 0
5910 23:19:29.698024 4, 0xFFFF, sum = 0
5911 23:19:29.700526 5, 0xFFFF, sum = 0
5912 23:19:29.701095 6, 0xFFFF, sum = 0
5913 23:19:29.704089 7, 0xFFFF, sum = 0
5914 23:19:29.704612 8, 0xFFFF, sum = 0
5915 23:19:29.707196 9, 0xFFFF, sum = 0
5916 23:19:29.707615 10, 0x0, sum = 1
5917 23:19:29.710878 11, 0x0, sum = 2
5918 23:19:29.711401 12, 0x0, sum = 3
5919 23:19:29.714172 13, 0x0, sum = 4
5920 23:19:29.714711 best_step = 11
5921 23:19:29.715047
5922 23:19:29.715354 ==
5923 23:19:29.716945 Dram Type= 6, Freq= 0, CH_1, rank 1
5924 23:19:29.720162 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5925 23:19:29.720597 ==
5926 23:19:29.723820 RX Vref Scan: 0
5927 23:19:29.724329
5928 23:19:29.726983 RX Vref 0 -> 0, step: 1
5929 23:19:29.727402
5930 23:19:29.727736 RX Delay -45 -> 252, step: 4
5931 23:19:29.735080 iDelay=203, Bit 0, Center 108 (27 ~ 190) 164
5932 23:19:29.738437 iDelay=203, Bit 1, Center 100 (19 ~ 182) 164
5933 23:19:29.741901 iDelay=203, Bit 2, Center 94 (11 ~ 178) 168
5934 23:19:29.744641 iDelay=203, Bit 3, Center 100 (19 ~ 182) 164
5935 23:19:29.748193 iDelay=203, Bit 4, Center 100 (19 ~ 182) 164
5936 23:19:29.754732 iDelay=203, Bit 5, Center 118 (35 ~ 202) 168
5937 23:19:29.758152 iDelay=203, Bit 6, Center 114 (31 ~ 198) 168
5938 23:19:29.761420 iDelay=203, Bit 7, Center 104 (19 ~ 190) 172
5939 23:19:29.764902 iDelay=203, Bit 8, Center 88 (3 ~ 174) 172
5940 23:19:29.768373 iDelay=203, Bit 9, Center 86 (-1 ~ 174) 176
5941 23:19:29.775292 iDelay=203, Bit 10, Center 102 (19 ~ 186) 168
5942 23:19:29.778010 iDelay=203, Bit 11, Center 92 (7 ~ 178) 172
5943 23:19:29.782213 iDelay=203, Bit 12, Center 108 (19 ~ 198) 180
5944 23:19:29.784716 iDelay=203, Bit 13, Center 104 (19 ~ 190) 172
5945 23:19:29.788234 iDelay=203, Bit 14, Center 102 (19 ~ 186) 168
5946 23:19:29.794704 iDelay=203, Bit 15, Center 108 (23 ~ 194) 172
5947 23:19:29.795261 ==
5948 23:19:29.798271 Dram Type= 6, Freq= 0, CH_1, rank 1
5949 23:19:29.801734 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5950 23:19:29.802320 ==
5951 23:19:29.802757 DQS Delay:
5952 23:19:29.804833 DQS0 = 0, DQS1 = 0
5953 23:19:29.805390 DQM Delay:
5954 23:19:29.808103 DQM0 = 104, DQM1 = 98
5955 23:19:29.808659 DQ Delay:
5956 23:19:29.811341 DQ0 =108, DQ1 =100, DQ2 =94, DQ3 =100
5957 23:19:29.814469 DQ4 =100, DQ5 =118, DQ6 =114, DQ7 =104
5958 23:19:29.818509 DQ8 =88, DQ9 =86, DQ10 =102, DQ11 =92
5959 23:19:29.821771 DQ12 =108, DQ13 =104, DQ14 =102, DQ15 =108
5960 23:19:29.822326
5961 23:19:29.822700
5962 23:19:29.831650 [DQSOSCAuto] RK1, (LSB)MR18= 0x29fc, (MSB)MR19= 0x504, tDQSOscB0 = 423 ps tDQSOscB1 = 408 ps
5963 23:19:29.835147 CH1 RK1: MR19=504, MR18=29FC
5964 23:19:29.838586 CH1_RK1: MR19=0x504, MR18=0x29FC, DQSOSC=408, MR23=63, INC=65, DEC=43
5965 23:19:29.841447 [RxdqsGatingPostProcess] freq 933
5966 23:19:29.848113 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5967 23:19:29.851720 best DQS0 dly(2T, 0.5T) = (0, 10)
5968 23:19:29.854505 best DQS1 dly(2T, 0.5T) = (0, 10)
5969 23:19:29.857958 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5970 23:19:29.861312 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5971 23:19:29.865101 best DQS0 dly(2T, 0.5T) = (0, 10)
5972 23:19:29.868063 best DQS1 dly(2T, 0.5T) = (0, 10)
5973 23:19:29.871193 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5974 23:19:29.874426 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5975 23:19:29.874905 Pre-setting of DQS Precalculation
5976 23:19:29.881613 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5977 23:19:29.888525 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5978 23:19:29.894885 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5979 23:19:29.895411
5980 23:19:29.895744
5981 23:19:29.897921 [Calibration Summary] 1866 Mbps
5982 23:19:29.900951 CH 0, Rank 0
5983 23:19:29.901368 SW Impedance : PASS
5984 23:19:29.904927 DUTY Scan : NO K
5985 23:19:29.908167 ZQ Calibration : PASS
5986 23:19:29.908681 Jitter Meter : NO K
5987 23:19:29.911404 CBT Training : PASS
5988 23:19:29.914749 Write leveling : PASS
5989 23:19:29.915193 RX DQS gating : PASS
5990 23:19:29.917675 RX DQ/DQS(RDDQC) : PASS
5991 23:19:29.918190 TX DQ/DQS : PASS
5992 23:19:29.920766 RX DATLAT : PASS
5993 23:19:29.924879 RX DQ/DQS(Engine): PASS
5994 23:19:29.925401 TX OE : NO K
5995 23:19:29.927879 All Pass.
5996 23:19:29.928292
5997 23:19:29.928642 CH 0, Rank 1
5998 23:19:29.931195 SW Impedance : PASS
5999 23:19:29.931711 DUTY Scan : NO K
6000 23:19:29.934185 ZQ Calibration : PASS
6001 23:19:29.937820 Jitter Meter : NO K
6002 23:19:29.938236 CBT Training : PASS
6003 23:19:29.940845 Write leveling : PASS
6004 23:19:29.943894 RX DQS gating : PASS
6005 23:19:29.944310 RX DQ/DQS(RDDQC) : PASS
6006 23:19:29.947546 TX DQ/DQS : PASS
6007 23:19:29.950461 RX DATLAT : PASS
6008 23:19:29.950881 RX DQ/DQS(Engine): PASS
6009 23:19:29.953926 TX OE : NO K
6010 23:19:29.954371 All Pass.
6011 23:19:29.954714
6012 23:19:29.957048 CH 1, Rank 0
6013 23:19:29.957466 SW Impedance : PASS
6014 23:19:29.960922 DUTY Scan : NO K
6015 23:19:29.963723 ZQ Calibration : PASS
6016 23:19:29.964142 Jitter Meter : NO K
6017 23:19:29.967373 CBT Training : PASS
6018 23:19:29.971079 Write leveling : PASS
6019 23:19:29.971607 RX DQS gating : PASS
6020 23:19:29.974319 RX DQ/DQS(RDDQC) : PASS
6021 23:19:29.974736 TX DQ/DQS : PASS
6022 23:19:29.977418 RX DATLAT : PASS
6023 23:19:29.980821 RX DQ/DQS(Engine): PASS
6024 23:19:29.981345 TX OE : NO K
6025 23:19:29.984248 All Pass.
6026 23:19:29.984772
6027 23:19:29.985107 CH 1, Rank 1
6028 23:19:29.987648 SW Impedance : PASS
6029 23:19:29.988172 DUTY Scan : NO K
6030 23:19:29.990826 ZQ Calibration : PASS
6031 23:19:29.993844 Jitter Meter : NO K
6032 23:19:29.994365 CBT Training : PASS
6033 23:19:29.997253 Write leveling : PASS
6034 23:19:30.000629 RX DQS gating : PASS
6035 23:19:30.001055 RX DQ/DQS(RDDQC) : PASS
6036 23:19:30.003426 TX DQ/DQS : PASS
6037 23:19:30.007391 RX DATLAT : PASS
6038 23:19:30.007939 RX DQ/DQS(Engine): PASS
6039 23:19:30.010377 TX OE : NO K
6040 23:19:30.010820 All Pass.
6041 23:19:30.011269
6042 23:19:30.013817 DramC Write-DBI off
6043 23:19:30.017156 PER_BANK_REFRESH: Hybrid Mode
6044 23:19:30.017730 TX_TRACKING: ON
6045 23:19:30.027041 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6046 23:19:30.030559 [FAST_K] Save calibration result to emmc
6047 23:19:30.033339 dramc_set_vcore_voltage set vcore to 650000
6048 23:19:30.036997 Read voltage for 400, 6
6049 23:19:30.037538 Vio18 = 0
6050 23:19:30.038043 Vcore = 650000
6051 23:19:30.040096 Vdram = 0
6052 23:19:30.040528 Vddq = 0
6053 23:19:30.040970 Vmddr = 0
6054 23:19:30.046908 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6055 23:19:30.050689 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6056 23:19:30.053972 MEM_TYPE=3, freq_sel=20
6057 23:19:30.056859 sv_algorithm_assistance_LP4_800
6058 23:19:30.060026 ============ PULL DRAM RESETB DOWN ============
6059 23:19:30.063197 ========== PULL DRAM RESETB DOWN end =========
6060 23:19:30.069929 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6061 23:19:30.073232 ===================================
6062 23:19:30.073687 LPDDR4 DRAM CONFIGURATION
6063 23:19:30.076548 ===================================
6064 23:19:30.080548 EX_ROW_EN[0] = 0x0
6065 23:19:30.083956 EX_ROW_EN[1] = 0x0
6066 23:19:30.084522 LP4Y_EN = 0x0
6067 23:19:30.086825 WORK_FSP = 0x0
6068 23:19:30.087347 WL = 0x2
6069 23:19:30.090211 RL = 0x2
6070 23:19:30.090732 BL = 0x2
6071 23:19:30.093747 RPST = 0x0
6072 23:19:30.094271 RD_PRE = 0x0
6073 23:19:30.096837 WR_PRE = 0x1
6074 23:19:30.097381 WR_PST = 0x0
6075 23:19:30.099571 DBI_WR = 0x0
6076 23:19:30.099985 DBI_RD = 0x0
6077 23:19:30.103321 OTF = 0x1
6078 23:19:30.106568 ===================================
6079 23:19:30.110011 ===================================
6080 23:19:30.110557 ANA top config
6081 23:19:30.113226 ===================================
6082 23:19:30.116676 DLL_ASYNC_EN = 0
6083 23:19:30.119934 ALL_SLAVE_EN = 1
6084 23:19:30.122993 NEW_RANK_MODE = 1
6085 23:19:30.123439 DLL_IDLE_MODE = 1
6086 23:19:30.126379 LP45_APHY_COMB_EN = 1
6087 23:19:30.129879 TX_ODT_DIS = 1
6088 23:19:30.133230 NEW_8X_MODE = 1
6089 23:19:30.136534 ===================================
6090 23:19:30.139898 ===================================
6091 23:19:30.143014 data_rate = 800
6092 23:19:30.143438 CKR = 1
6093 23:19:30.146734 DQ_P2S_RATIO = 4
6094 23:19:30.149717 ===================================
6095 23:19:30.153355 CA_P2S_RATIO = 4
6096 23:19:30.156430 DQ_CA_OPEN = 0
6097 23:19:30.159864 DQ_SEMI_OPEN = 1
6098 23:19:30.163186 CA_SEMI_OPEN = 1
6099 23:19:30.163858 CA_FULL_RATE = 0
6100 23:19:30.166582 DQ_CKDIV4_EN = 0
6101 23:19:30.170072 CA_CKDIV4_EN = 1
6102 23:19:30.173012 CA_PREDIV_EN = 0
6103 23:19:30.176477 PH8_DLY = 0
6104 23:19:30.179655 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6105 23:19:30.180248 DQ_AAMCK_DIV = 0
6106 23:19:30.183317 CA_AAMCK_DIV = 0
6107 23:19:30.186564 CA_ADMCK_DIV = 4
6108 23:19:30.189866 DQ_TRACK_CA_EN = 0
6109 23:19:30.193305 CA_PICK = 800
6110 23:19:30.196431 CA_MCKIO = 400
6111 23:19:30.196897 MCKIO_SEMI = 400
6112 23:19:30.199325 PLL_FREQ = 3016
6113 23:19:30.202815 DQ_UI_PI_RATIO = 32
6114 23:19:30.205984 CA_UI_PI_RATIO = 32
6115 23:19:30.209719 ===================================
6116 23:19:30.213459 ===================================
6117 23:19:30.217091 memory_type:LPDDR4
6118 23:19:30.217705 GP_NUM : 10
6119 23:19:30.219832 SRAM_EN : 1
6120 23:19:30.223241 MD32_EN : 0
6121 23:19:30.226013 ===================================
6122 23:19:30.226721 [ANA_INIT] >>>>>>>>>>>>>>
6123 23:19:30.229343 <<<<<< [CONFIGURE PHASE]: ANA_TX
6124 23:19:30.232767 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6125 23:19:30.236120 ===================================
6126 23:19:30.239789 data_rate = 800,PCW = 0X7400
6127 23:19:30.242745 ===================================
6128 23:19:30.245941 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6129 23:19:30.252600 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6130 23:19:30.262783 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6131 23:19:30.269732 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6132 23:19:30.273121 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6133 23:19:30.276576 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6134 23:19:30.277110 [ANA_INIT] flow start
6135 23:19:30.279850 [ANA_INIT] PLL >>>>>>>>
6136 23:19:30.283086 [ANA_INIT] PLL <<<<<<<<
6137 23:19:30.283643 [ANA_INIT] MIDPI >>>>>>>>
6138 23:19:30.286165 [ANA_INIT] MIDPI <<<<<<<<
6139 23:19:30.289726 [ANA_INIT] DLL >>>>>>>>
6140 23:19:30.290287 [ANA_INIT] flow end
6141 23:19:30.293045 ============ LP4 DIFF to SE enter ============
6142 23:19:30.299559 ============ LP4 DIFF to SE exit ============
6143 23:19:30.300127 [ANA_INIT] <<<<<<<<<<<<<
6144 23:19:30.302710 [Flow] Enable top DCM control >>>>>
6145 23:19:30.306167 [Flow] Enable top DCM control <<<<<
6146 23:19:30.309705 Enable DLL master slave shuffle
6147 23:19:30.315792 ==============================================================
6148 23:19:30.319502 Gating Mode config
6149 23:19:30.322478 ==============================================================
6150 23:19:30.325968 Config description:
6151 23:19:30.336311 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6152 23:19:30.342535 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6153 23:19:30.345868 SELPH_MODE 0: By rank 1: By Phase
6154 23:19:30.352692 ==============================================================
6155 23:19:30.355952 GAT_TRACK_EN = 0
6156 23:19:30.359294 RX_GATING_MODE = 2
6157 23:19:30.359759 RX_GATING_TRACK_MODE = 2
6158 23:19:30.362760 SELPH_MODE = 1
6159 23:19:30.365963 PICG_EARLY_EN = 1
6160 23:19:30.369446 VALID_LAT_VALUE = 1
6161 23:19:30.376436 ==============================================================
6162 23:19:30.379260 Enter into Gating configuration >>>>
6163 23:19:30.382585 Exit from Gating configuration <<<<
6164 23:19:30.385829 Enter into DVFS_PRE_config >>>>>
6165 23:19:30.396057 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6166 23:19:30.399331 Exit from DVFS_PRE_config <<<<<
6167 23:19:30.402681 Enter into PICG configuration >>>>
6168 23:19:30.405817 Exit from PICG configuration <<<<
6169 23:19:30.409111 [RX_INPUT] configuration >>>>>
6170 23:19:30.412685 [RX_INPUT] configuration <<<<<
6171 23:19:30.415887 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6172 23:19:30.422596 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6173 23:19:30.428707 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6174 23:19:30.435892 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6175 23:19:30.439232 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6176 23:19:30.445441 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6177 23:19:30.448679 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6178 23:19:30.455542 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6179 23:19:30.458516 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6180 23:19:30.462269 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6181 23:19:30.465762 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6182 23:19:30.472326 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6183 23:19:30.475644 ===================================
6184 23:19:30.476213 LPDDR4 DRAM CONFIGURATION
6185 23:19:30.478885 ===================================
6186 23:19:30.482436 EX_ROW_EN[0] = 0x0
6187 23:19:30.485797 EX_ROW_EN[1] = 0x0
6188 23:19:30.486573 LP4Y_EN = 0x0
6189 23:19:30.489322 WORK_FSP = 0x0
6190 23:19:30.489944 WL = 0x2
6191 23:19:30.492385 RL = 0x2
6192 23:19:30.492948 BL = 0x2
6193 23:19:30.495959 RPST = 0x0
6194 23:19:30.496519 RD_PRE = 0x0
6195 23:19:30.498904 WR_PRE = 0x1
6196 23:19:30.499472 WR_PST = 0x0
6197 23:19:30.502495 DBI_WR = 0x0
6198 23:19:30.503055 DBI_RD = 0x0
6199 23:19:30.505413 OTF = 0x1
6200 23:19:30.508988 ===================================
6201 23:19:30.512367 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6202 23:19:30.515097 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6203 23:19:30.521954 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6204 23:19:30.525993 ===================================
6205 23:19:30.526603 LPDDR4 DRAM CONFIGURATION
6206 23:19:30.528614 ===================================
6207 23:19:30.531745 EX_ROW_EN[0] = 0x10
6208 23:19:30.535341 EX_ROW_EN[1] = 0x0
6209 23:19:30.535866 LP4Y_EN = 0x0
6210 23:19:30.538271 WORK_FSP = 0x0
6211 23:19:30.538785 WL = 0x2
6212 23:19:30.541737 RL = 0x2
6213 23:19:30.542255 BL = 0x2
6214 23:19:30.545178 RPST = 0x0
6215 23:19:30.545945 RD_PRE = 0x0
6216 23:19:30.548425 WR_PRE = 0x1
6217 23:19:30.548840 WR_PST = 0x0
6218 23:19:30.551927 DBI_WR = 0x0
6219 23:19:30.552452 DBI_RD = 0x0
6220 23:19:30.555248 OTF = 0x1
6221 23:19:30.558299 ===================================
6222 23:19:30.565055 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6223 23:19:30.568237 nWR fixed to 30
6224 23:19:30.568765 [ModeRegInit_LP4] CH0 RK0
6225 23:19:30.571920 [ModeRegInit_LP4] CH0 RK1
6226 23:19:30.575171 [ModeRegInit_LP4] CH1 RK0
6227 23:19:30.578362 [ModeRegInit_LP4] CH1 RK1
6228 23:19:30.578874 match AC timing 19
6229 23:19:30.581649 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6230 23:19:30.588690 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6231 23:19:30.591914 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6232 23:19:30.598287 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6233 23:19:30.601653 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6234 23:19:30.602234 ==
6235 23:19:30.604636 Dram Type= 6, Freq= 0, CH_0, rank 0
6236 23:19:30.608258 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6237 23:19:30.608854 ==
6238 23:19:30.614464 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6239 23:19:30.621389 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6240 23:19:30.624921 [CA 0] Center 36 (8~64) winsize 57
6241 23:19:30.625493 [CA 1] Center 36 (8~64) winsize 57
6242 23:19:30.628521 [CA 2] Center 36 (8~64) winsize 57
6243 23:19:30.631180 [CA 3] Center 36 (8~64) winsize 57
6244 23:19:30.634769 [CA 4] Center 36 (8~64) winsize 57
6245 23:19:30.637806 [CA 5] Center 36 (8~64) winsize 57
6246 23:19:30.638270
6247 23:19:30.641397 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6248 23:19:30.642019
6249 23:19:30.644642 [CATrainingPosCal] consider 1 rank data
6250 23:19:30.647904 u2DelayCellTimex100 = 270/100 ps
6251 23:19:30.651611 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6252 23:19:30.658041 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6253 23:19:30.661534 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6254 23:19:30.664441 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6255 23:19:30.668215 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6256 23:19:30.671378 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6257 23:19:30.671936
6258 23:19:30.674435 CA PerBit enable=1, Macro0, CA PI delay=36
6259 23:19:30.674899
6260 23:19:30.678283 [CBTSetCACLKResult] CA Dly = 36
6261 23:19:30.678894 CS Dly: 1 (0~32)
6262 23:19:30.681150 ==
6263 23:19:30.684617 Dram Type= 6, Freq= 0, CH_0, rank 1
6264 23:19:30.687880 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6265 23:19:30.688443 ==
6266 23:19:30.691345 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6267 23:19:30.698003 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6268 23:19:30.701226 [CA 0] Center 36 (8~64) winsize 57
6269 23:19:30.704470 [CA 1] Center 36 (8~64) winsize 57
6270 23:19:30.708240 [CA 2] Center 36 (8~64) winsize 57
6271 23:19:30.711296 [CA 3] Center 36 (8~64) winsize 57
6272 23:19:30.714530 [CA 4] Center 36 (8~64) winsize 57
6273 23:19:30.717757 [CA 5] Center 36 (8~64) winsize 57
6274 23:19:30.718341
6275 23:19:30.720818 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6276 23:19:30.721280
6277 23:19:30.724648 [CATrainingPosCal] consider 2 rank data
6278 23:19:30.727755 u2DelayCellTimex100 = 270/100 ps
6279 23:19:30.730971 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6280 23:19:30.734142 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6281 23:19:30.737525 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6282 23:19:30.740987 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6283 23:19:30.747462 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6284 23:19:30.750865 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6285 23:19:30.751332
6286 23:19:30.754085 CA PerBit enable=1, Macro0, CA PI delay=36
6287 23:19:30.754754
6288 23:19:30.757313 [CBTSetCACLKResult] CA Dly = 36
6289 23:19:30.757917 CS Dly: 1 (0~32)
6290 23:19:30.758294
6291 23:19:30.760507 ----->DramcWriteLeveling(PI) begin...
6292 23:19:30.760976 ==
6293 23:19:30.764377 Dram Type= 6, Freq= 0, CH_0, rank 0
6294 23:19:30.770916 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6295 23:19:30.771477 ==
6296 23:19:30.774520 Write leveling (Byte 0): 40 => 8
6297 23:19:30.775077 Write leveling (Byte 1): 40 => 8
6298 23:19:30.777688 DramcWriteLeveling(PI) end<-----
6299 23:19:30.778244
6300 23:19:30.778682 ==
6301 23:19:30.780882 Dram Type= 6, Freq= 0, CH_0, rank 0
6302 23:19:30.787463 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6303 23:19:30.788019 ==
6304 23:19:30.791112 [Gating] SW mode calibration
6305 23:19:30.797781 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6306 23:19:30.800771 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6307 23:19:30.807384 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6308 23:19:30.810373 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6309 23:19:30.814106 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6310 23:19:30.821332 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6311 23:19:30.823726 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6312 23:19:30.827031 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6313 23:19:30.833533 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6314 23:19:30.837144 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6315 23:19:30.840465 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6316 23:19:30.843926 Total UI for P1: 0, mck2ui 16
6317 23:19:30.846920 best dqsien dly found for B0: ( 0, 14, 24)
6318 23:19:30.850186 Total UI for P1: 0, mck2ui 16
6319 23:19:30.853791 best dqsien dly found for B1: ( 0, 14, 24)
6320 23:19:30.857428 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6321 23:19:30.860447 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6322 23:19:30.861049
6323 23:19:30.864008 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6324 23:19:30.870940 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6325 23:19:30.871502 [Gating] SW calibration Done
6326 23:19:30.871878 ==
6327 23:19:30.873999 Dram Type= 6, Freq= 0, CH_0, rank 0
6328 23:19:30.880806 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6329 23:19:30.881369 ==
6330 23:19:30.881785 RX Vref Scan: 0
6331 23:19:30.882130
6332 23:19:30.884048 RX Vref 0 -> 0, step: 1
6333 23:19:30.884506
6334 23:19:30.886929 RX Delay -410 -> 252, step: 16
6335 23:19:30.890212 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6336 23:19:30.893995 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6337 23:19:30.900063 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6338 23:19:30.903434 iDelay=230, Bit 3, Center -27 (-266 ~ 213) 480
6339 23:19:30.907055 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6340 23:19:30.910560 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6341 23:19:30.917694 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6342 23:19:30.920253 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6343 23:19:30.923522 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6344 23:19:30.927208 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6345 23:19:30.933487 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6346 23:19:30.936913 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6347 23:19:30.940138 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6348 23:19:30.943438 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6349 23:19:30.949850 iDelay=230, Bit 14, Center -11 (-250 ~ 229) 480
6350 23:19:30.953620 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6351 23:19:30.954040 ==
6352 23:19:30.956695 Dram Type= 6, Freq= 0, CH_0, rank 0
6353 23:19:30.960132 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6354 23:19:30.960568 ==
6355 23:19:30.963371 DQS Delay:
6356 23:19:30.963780 DQS0 = 27, DQS1 = 35
6357 23:19:30.966641 DQM Delay:
6358 23:19:30.967057 DQM0 = 8, DQM1 = 12
6359 23:19:30.967388 DQ Delay:
6360 23:19:30.969656 DQ0 =8, DQ1 =16, DQ2 =0, DQ3 =0
6361 23:19:30.973732 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6362 23:19:30.976974 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6363 23:19:30.979742 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6364 23:19:30.980160
6365 23:19:30.980488
6366 23:19:30.980789 ==
6367 23:19:30.983388 Dram Type= 6, Freq= 0, CH_0, rank 0
6368 23:19:30.986748 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6369 23:19:30.990238 ==
6370 23:19:30.990753
6371 23:19:30.991087
6372 23:19:30.991395 TX Vref Scan disable
6373 23:19:30.993455 == TX Byte 0 ==
6374 23:19:30.996843 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6375 23:19:30.999451 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6376 23:19:31.003086 == TX Byte 1 ==
6377 23:19:31.006600 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6378 23:19:31.009880 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6379 23:19:31.010396 ==
6380 23:19:31.013247 Dram Type= 6, Freq= 0, CH_0, rank 0
6381 23:19:31.019994 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6382 23:19:31.020507 ==
6383 23:19:31.020837
6384 23:19:31.021142
6385 23:19:31.021440 TX Vref Scan disable
6386 23:19:31.022804 == TX Byte 0 ==
6387 23:19:31.026839 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6388 23:19:31.030184 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6389 23:19:31.032872 == TX Byte 1 ==
6390 23:19:31.036519 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6391 23:19:31.039705 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6392 23:19:31.040217
6393 23:19:31.042665 [DATLAT]
6394 23:19:31.043244 Freq=400, CH0 RK0
6395 23:19:31.043587
6396 23:19:31.046550 DATLAT Default: 0xf
6397 23:19:31.047062 0, 0xFFFF, sum = 0
6398 23:19:31.049867 1, 0xFFFF, sum = 0
6399 23:19:31.050405 2, 0xFFFF, sum = 0
6400 23:19:31.053066 3, 0xFFFF, sum = 0
6401 23:19:31.053620 4, 0xFFFF, sum = 0
6402 23:19:31.056104 5, 0xFFFF, sum = 0
6403 23:19:31.056563 6, 0xFFFF, sum = 0
6404 23:19:31.059423 7, 0xFFFF, sum = 0
6405 23:19:31.059850 8, 0xFFFF, sum = 0
6406 23:19:31.062938 9, 0xFFFF, sum = 0
6407 23:19:31.063361 10, 0xFFFF, sum = 0
6408 23:19:31.066275 11, 0xFFFF, sum = 0
6409 23:19:31.069529 12, 0xFFFF, sum = 0
6410 23:19:31.070100 13, 0x0, sum = 1
6411 23:19:31.070446 14, 0x0, sum = 2
6412 23:19:31.072823 15, 0x0, sum = 3
6413 23:19:31.073343 16, 0x0, sum = 4
6414 23:19:31.076246 best_step = 14
6415 23:19:31.076762
6416 23:19:31.077097 ==
6417 23:19:31.079226 Dram Type= 6, Freq= 0, CH_0, rank 0
6418 23:19:31.083184 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6419 23:19:31.083716 ==
6420 23:19:31.085861 RX Vref Scan: 1
6421 23:19:31.086281
6422 23:19:31.086612 RX Vref 0 -> 0, step: 1
6423 23:19:31.086922
6424 23:19:31.089557 RX Delay -311 -> 252, step: 8
6425 23:19:31.090019
6426 23:19:31.092646 Set Vref, RX VrefLevel [Byte0]: 60
6427 23:19:31.096367 [Byte1]: 48
6428 23:19:31.100932
6429 23:19:31.101450 Final RX Vref Byte 0 = 60 to rank0
6430 23:19:31.104214 Final RX Vref Byte 1 = 48 to rank0
6431 23:19:31.107649 Final RX Vref Byte 0 = 60 to rank1
6432 23:19:31.111339 Final RX Vref Byte 1 = 48 to rank1==
6433 23:19:31.114315 Dram Type= 6, Freq= 0, CH_0, rank 0
6434 23:19:31.120846 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6435 23:19:31.121351 ==
6436 23:19:31.121721 DQS Delay:
6437 23:19:31.122038 DQS0 = 28, DQS1 = 36
6438 23:19:31.124484 DQM Delay:
6439 23:19:31.124901 DQM0 = 10, DQM1 = 13
6440 23:19:31.127902 DQ Delay:
6441 23:19:31.131120 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =8
6442 23:19:31.131547 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =20
6443 23:19:31.134402 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6444 23:19:31.137801 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6445 23:19:31.138324
6446 23:19:31.138692
6447 23:19:31.147878 [DQSOSCAuto] RK0, (LSB)MR18= 0xc4b1, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 385 ps
6448 23:19:31.150506 CH0 RK0: MR19=C0C, MR18=C4B1
6449 23:19:31.157682 CH0_RK0: MR19=0xC0C, MR18=0xC4B1, DQSOSC=385, MR23=63, INC=398, DEC=265
6450 23:19:31.158206 ==
6451 23:19:31.160666 Dram Type= 6, Freq= 0, CH_0, rank 1
6452 23:19:31.164132 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6453 23:19:31.164651 ==
6454 23:19:31.167355 [Gating] SW mode calibration
6455 23:19:31.173869 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6456 23:19:31.177470 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6457 23:19:31.184143 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6458 23:19:31.187448 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6459 23:19:31.190467 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6460 23:19:31.197955 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6461 23:19:31.200420 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6462 23:19:31.203877 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6463 23:19:31.210687 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6464 23:19:31.213837 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6465 23:19:31.217356 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6466 23:19:31.220691 Total UI for P1: 0, mck2ui 16
6467 23:19:31.223974 best dqsien dly found for B0: ( 0, 14, 24)
6468 23:19:31.227395 Total UI for P1: 0, mck2ui 16
6469 23:19:31.231032 best dqsien dly found for B1: ( 0, 14, 24)
6470 23:19:31.233976 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6471 23:19:31.237565 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6472 23:19:31.238012
6473 23:19:31.244702 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6474 23:19:31.247239 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6475 23:19:31.250792 [Gating] SW calibration Done
6476 23:19:31.251337 ==
6477 23:19:31.253965 Dram Type= 6, Freq= 0, CH_0, rank 1
6478 23:19:31.257421 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6479 23:19:31.257978 ==
6480 23:19:31.258320 RX Vref Scan: 0
6481 23:19:31.258630
6482 23:19:31.260717 RX Vref 0 -> 0, step: 1
6483 23:19:31.261132
6484 23:19:31.264312 RX Delay -410 -> 252, step: 16
6485 23:19:31.267296 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6486 23:19:31.273515 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6487 23:19:31.277482 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6488 23:19:31.280496 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6489 23:19:31.283499 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6490 23:19:31.290159 iDelay=230, Bit 5, Center -19 (-250 ~ 213) 464
6491 23:19:31.293516 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6492 23:19:31.297060 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6493 23:19:31.299944 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6494 23:19:31.307061 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6495 23:19:31.310274 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6496 23:19:31.313638 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6497 23:19:31.316917 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6498 23:19:31.323519 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6499 23:19:31.326932 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6500 23:19:31.330184 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6501 23:19:31.330733 ==
6502 23:19:31.333080 Dram Type= 6, Freq= 0, CH_0, rank 1
6503 23:19:31.340461 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6504 23:19:31.340977 ==
6505 23:19:31.341315 DQS Delay:
6506 23:19:31.341676 DQS0 = 19, DQS1 = 35
6507 23:19:31.343799 DQM Delay:
6508 23:19:31.344316 DQM0 = 3, DQM1 = 11
6509 23:19:31.346459 DQ Delay:
6510 23:19:31.346874 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6511 23:19:31.349696 DQ4 =0, DQ5 =0, DQ6 =8, DQ7 =16
6512 23:19:31.353074 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6513 23:19:31.356689 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6514 23:19:31.357209
6515 23:19:31.357542
6516 23:19:31.360169 ==
6517 23:19:31.360806 Dram Type= 6, Freq= 0, CH_0, rank 1
6518 23:19:31.366763 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6519 23:19:31.367190 ==
6520 23:19:31.367519
6521 23:19:31.367824
6522 23:19:31.368117 TX Vref Scan disable
6523 23:19:31.370041 == TX Byte 0 ==
6524 23:19:31.373502 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6525 23:19:31.376621 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6526 23:19:31.379621 == TX Byte 1 ==
6527 23:19:31.383655 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6528 23:19:31.386729 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6529 23:19:31.390025 ==
6530 23:19:31.393100 Dram Type= 6, Freq= 0, CH_0, rank 1
6531 23:19:31.396697 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6532 23:19:31.397223 ==
6533 23:19:31.397561
6534 23:19:31.397918
6535 23:19:31.399637 TX Vref Scan disable
6536 23:19:31.400055 == TX Byte 0 ==
6537 23:19:31.403016 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6538 23:19:31.406375 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6539 23:19:31.409447 == TX Byte 1 ==
6540 23:19:31.413431 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6541 23:19:31.416658 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6542 23:19:31.417200
6543 23:19:31.420207 [DATLAT]
6544 23:19:31.420721 Freq=400, CH0 RK1
6545 23:19:31.421059
6546 23:19:31.423098 DATLAT Default: 0xe
6547 23:19:31.423513 0, 0xFFFF, sum = 0
6548 23:19:31.426525 1, 0xFFFF, sum = 0
6549 23:19:31.427044 2, 0xFFFF, sum = 0
6550 23:19:31.429602 3, 0xFFFF, sum = 0
6551 23:19:31.430144 4, 0xFFFF, sum = 0
6552 23:19:31.432903 5, 0xFFFF, sum = 0
6553 23:19:31.433325 6, 0xFFFF, sum = 0
6554 23:19:31.435963 7, 0xFFFF, sum = 0
6555 23:19:31.439800 8, 0xFFFF, sum = 0
6556 23:19:31.440314 9, 0xFFFF, sum = 0
6557 23:19:31.442555 10, 0xFFFF, sum = 0
6558 23:19:31.442981 11, 0xFFFF, sum = 0
6559 23:19:31.445892 12, 0xFFFF, sum = 0
6560 23:19:31.446315 13, 0x0, sum = 1
6561 23:19:31.449393 14, 0x0, sum = 2
6562 23:19:31.449960 15, 0x0, sum = 3
6563 23:19:31.452891 16, 0x0, sum = 4
6564 23:19:31.453413 best_step = 14
6565 23:19:31.453786
6566 23:19:31.454100 ==
6567 23:19:31.456072 Dram Type= 6, Freq= 0, CH_0, rank 1
6568 23:19:31.459706 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6569 23:19:31.460230 ==
6570 23:19:31.462803 RX Vref Scan: 0
6571 23:19:31.463224
6572 23:19:31.466087 RX Vref 0 -> 0, step: 1
6573 23:19:31.466505
6574 23:19:31.466832 RX Delay -311 -> 252, step: 8
6575 23:19:31.474915 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6576 23:19:31.478222 iDelay=217, Bit 1, Center -12 (-231 ~ 208) 440
6577 23:19:31.481108 iDelay=217, Bit 2, Center -20 (-247 ~ 208) 456
6578 23:19:31.484980 iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448
6579 23:19:31.491586 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6580 23:19:31.494793 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6581 23:19:31.498367 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6582 23:19:31.501478 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6583 23:19:31.508017 iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448
6584 23:19:31.511600 iDelay=217, Bit 9, Center -36 (-255 ~ 184) 440
6585 23:19:31.514892 iDelay=217, Bit 10, Center -20 (-239 ~ 200) 440
6586 23:19:31.518125 iDelay=217, Bit 11, Center -28 (-247 ~ 192) 440
6587 23:19:31.524660 iDelay=217, Bit 12, Center -16 (-231 ~ 200) 432
6588 23:19:31.528364 iDelay=217, Bit 13, Center -16 (-231 ~ 200) 432
6589 23:19:31.531390 iDelay=217, Bit 14, Center -12 (-231 ~ 208) 440
6590 23:19:31.534797 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6591 23:19:31.537956 ==
6592 23:19:31.541673 Dram Type= 6, Freq= 0, CH_0, rank 1
6593 23:19:31.544469 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6594 23:19:31.545121 ==
6595 23:19:31.545535 DQS Delay:
6596 23:19:31.547999 DQS0 = 24, DQS1 = 36
6597 23:19:31.548461 DQM Delay:
6598 23:19:31.551275 DQM0 = 9, DQM1 = 14
6599 23:19:31.551740 DQ Delay:
6600 23:19:31.554946 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =8
6601 23:19:31.557684 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6602 23:19:31.561228 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6603 23:19:31.564481 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6604 23:19:31.564943
6605 23:19:31.565309
6606 23:19:31.571393 [DQSOSCAuto] RK1, (LSB)MR18= 0xb556, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 387 ps
6607 23:19:31.574704 CH0 RK1: MR19=C0C, MR18=B556
6608 23:19:31.581506 CH0_RK1: MR19=0xC0C, MR18=0xB556, DQSOSC=387, MR23=63, INC=394, DEC=262
6609 23:19:31.584922 [RxdqsGatingPostProcess] freq 400
6610 23:19:31.588358 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6611 23:19:31.591139 best DQS0 dly(2T, 0.5T) = (0, 10)
6612 23:19:31.594594 best DQS1 dly(2T, 0.5T) = (0, 10)
6613 23:19:31.597764 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6614 23:19:31.600892 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6615 23:19:31.604101 best DQS0 dly(2T, 0.5T) = (0, 10)
6616 23:19:31.607556 best DQS1 dly(2T, 0.5T) = (0, 10)
6617 23:19:31.611485 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6618 23:19:31.614225 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6619 23:19:31.617783 Pre-setting of DQS Precalculation
6620 23:19:31.621123 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6621 23:19:31.624236 ==
6622 23:19:31.624660 Dram Type= 6, Freq= 0, CH_1, rank 0
6623 23:19:31.630952 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6624 23:19:31.631501 ==
6625 23:19:31.634175 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6626 23:19:31.640979 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6627 23:19:31.644037 [CA 0] Center 36 (8~64) winsize 57
6628 23:19:31.647724 [CA 1] Center 36 (8~64) winsize 57
6629 23:19:31.650893 [CA 2] Center 36 (8~64) winsize 57
6630 23:19:31.653896 [CA 3] Center 36 (8~64) winsize 57
6631 23:19:31.657512 [CA 4] Center 36 (8~64) winsize 57
6632 23:19:31.660894 [CA 5] Center 36 (8~64) winsize 57
6633 23:19:31.661457
6634 23:19:31.664093 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6635 23:19:31.664563
6636 23:19:31.667546 [CATrainingPosCal] consider 1 rank data
6637 23:19:31.670523 u2DelayCellTimex100 = 270/100 ps
6638 23:19:31.674076 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6639 23:19:31.677854 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6640 23:19:31.680528 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6641 23:19:31.684125 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6642 23:19:31.687496 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6643 23:19:31.693819 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6644 23:19:31.694376
6645 23:19:31.696966 CA PerBit enable=1, Macro0, CA PI delay=36
6646 23:19:31.697431
6647 23:19:31.700336 [CBTSetCACLKResult] CA Dly = 36
6648 23:19:31.700803 CS Dly: 1 (0~32)
6649 23:19:31.701174 ==
6650 23:19:31.704039 Dram Type= 6, Freq= 0, CH_1, rank 1
6651 23:19:31.707315 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6652 23:19:31.710976 ==
6653 23:19:31.714537 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6654 23:19:31.720494 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6655 23:19:31.724203 [CA 0] Center 36 (8~64) winsize 57
6656 23:19:31.727591 [CA 1] Center 36 (8~64) winsize 57
6657 23:19:31.730464 [CA 2] Center 36 (8~64) winsize 57
6658 23:19:31.733833 [CA 3] Center 36 (8~64) winsize 57
6659 23:19:31.737759 [CA 4] Center 36 (8~64) winsize 57
6660 23:19:31.738319 [CA 5] Center 36 (8~64) winsize 57
6661 23:19:31.741221
6662 23:19:31.743899 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6663 23:19:31.744369
6664 23:19:31.747574 [CATrainingPosCal] consider 2 rank data
6665 23:19:31.751115 u2DelayCellTimex100 = 270/100 ps
6666 23:19:31.753871 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6667 23:19:31.757023 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6668 23:19:31.761129 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6669 23:19:31.763899 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6670 23:19:31.767069 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6671 23:19:31.770537 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6672 23:19:31.771007
6673 23:19:31.773806 CA PerBit enable=1, Macro0, CA PI delay=36
6674 23:19:31.774372
6675 23:19:31.777367 [CBTSetCACLKResult] CA Dly = 36
6676 23:19:31.780501 CS Dly: 1 (0~32)
6677 23:19:31.780969
6678 23:19:31.783818 ----->DramcWriteLeveling(PI) begin...
6679 23:19:31.784381 ==
6680 23:19:31.787186 Dram Type= 6, Freq= 0, CH_1, rank 0
6681 23:19:31.790324 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6682 23:19:31.790886 ==
6683 23:19:31.793626 Write leveling (Byte 0): 40 => 8
6684 23:19:31.797123 Write leveling (Byte 1): 40 => 8
6685 23:19:31.800293 DramcWriteLeveling(PI) end<-----
6686 23:19:31.800766
6687 23:19:31.801135 ==
6688 23:19:31.803650 Dram Type= 6, Freq= 0, CH_1, rank 0
6689 23:19:31.807020 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6690 23:19:31.807586 ==
6691 23:19:31.810442 [Gating] SW mode calibration
6692 23:19:31.817174 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6693 23:19:31.823080 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6694 23:19:31.826305 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6695 23:19:31.833517 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6696 23:19:31.836774 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6697 23:19:31.839950 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6698 23:19:31.847258 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6699 23:19:31.850032 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6700 23:19:31.853251 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6701 23:19:31.860295 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6702 23:19:31.863191 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6703 23:19:31.866709 Total UI for P1: 0, mck2ui 16
6704 23:19:31.869886 best dqsien dly found for B0: ( 0, 14, 24)
6705 23:19:31.873286 Total UI for P1: 0, mck2ui 16
6706 23:19:31.876791 best dqsien dly found for B1: ( 0, 14, 24)
6707 23:19:31.880071 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6708 23:19:31.883257 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6709 23:19:31.883724
6710 23:19:31.886281 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6711 23:19:31.889744 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6712 23:19:31.893462 [Gating] SW calibration Done
6713 23:19:31.894069 ==
6714 23:19:31.896338 Dram Type= 6, Freq= 0, CH_1, rank 0
6715 23:19:31.899801 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6716 23:19:31.900273 ==
6717 23:19:31.902842 RX Vref Scan: 0
6718 23:19:31.903424
6719 23:19:31.906350 RX Vref 0 -> 0, step: 1
6720 23:19:31.906907
6721 23:19:31.909801 RX Delay -410 -> 252, step: 16
6722 23:19:31.912831 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6723 23:19:31.916583 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6724 23:19:31.919681 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6725 23:19:31.926375 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6726 23:19:31.929663 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6727 23:19:31.932572 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6728 23:19:31.935987 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6729 23:19:31.942657 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6730 23:19:31.945903 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6731 23:19:31.949455 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6732 23:19:31.952871 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6733 23:19:31.959657 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6734 23:19:31.962802 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6735 23:19:31.966079 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6736 23:19:31.969246 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6737 23:19:31.975869 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6738 23:19:31.976434 ==
6739 23:19:31.979334 Dram Type= 6, Freq= 0, CH_1, rank 0
6740 23:19:31.982843 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6741 23:19:31.983403 ==
6742 23:19:31.983777 DQS Delay:
6743 23:19:31.986222 DQS0 = 27, DQS1 = 35
6744 23:19:31.986786 DQM Delay:
6745 23:19:31.989741 DQM0 = 11, DQM1 = 13
6746 23:19:31.990303 DQ Delay:
6747 23:19:31.992950 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6748 23:19:31.995813 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6749 23:19:31.999560 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6750 23:19:32.002578 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6751 23:19:32.003137
6752 23:19:32.003505
6753 23:19:32.003848 ==
6754 23:19:32.005743 Dram Type= 6, Freq= 0, CH_1, rank 0
6755 23:19:32.009353 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6756 23:19:32.009877 ==
6757 23:19:32.010253
6758 23:19:32.010595
6759 23:19:32.012513 TX Vref Scan disable
6760 23:19:32.015723 == TX Byte 0 ==
6761 23:19:32.019115 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6762 23:19:32.022114 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6763 23:19:32.025748 == TX Byte 1 ==
6764 23:19:32.028897 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6765 23:19:32.032447 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6766 23:19:32.033009 ==
6767 23:19:32.035293 Dram Type= 6, Freq= 0, CH_1, rank 0
6768 23:19:32.039137 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6769 23:19:32.039696 ==
6770 23:19:32.040070
6771 23:19:32.042292
6772 23:19:32.042755 TX Vref Scan disable
6773 23:19:32.045814 == TX Byte 0 ==
6774 23:19:32.048881 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6775 23:19:32.052660 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6776 23:19:32.055615 == TX Byte 1 ==
6777 23:19:32.058968 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6778 23:19:32.062418 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6779 23:19:32.062976
6780 23:19:32.063374 [DATLAT]
6781 23:19:32.065263 Freq=400, CH1 RK0
6782 23:19:32.065844
6783 23:19:32.066226 DATLAT Default: 0xf
6784 23:19:32.068889 0, 0xFFFF, sum = 0
6785 23:19:32.069456 1, 0xFFFF, sum = 0
6786 23:19:32.072352 2, 0xFFFF, sum = 0
6787 23:19:32.075661 3, 0xFFFF, sum = 0
6788 23:19:32.076227 4, 0xFFFF, sum = 0
6789 23:19:32.079446 5, 0xFFFF, sum = 0
6790 23:19:32.080011 6, 0xFFFF, sum = 0
6791 23:19:32.082276 7, 0xFFFF, sum = 0
6792 23:19:32.082747 8, 0xFFFF, sum = 0
6793 23:19:32.085875 9, 0xFFFF, sum = 0
6794 23:19:32.086441 10, 0xFFFF, sum = 0
6795 23:19:32.088646 11, 0xFFFF, sum = 0
6796 23:19:32.089118 12, 0xFFFF, sum = 0
6797 23:19:32.092281 13, 0x0, sum = 1
6798 23:19:32.092842 14, 0x0, sum = 2
6799 23:19:32.095797 15, 0x0, sum = 3
6800 23:19:32.096363 16, 0x0, sum = 4
6801 23:19:32.099168 best_step = 14
6802 23:19:32.099728
6803 23:19:32.100097 ==
6804 23:19:32.102011 Dram Type= 6, Freq= 0, CH_1, rank 0
6805 23:19:32.105511 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6806 23:19:32.106015 ==
6807 23:19:32.106388 RX Vref Scan: 1
6808 23:19:32.108715
6809 23:19:32.109177 RX Vref 0 -> 0, step: 1
6810 23:19:32.109549
6811 23:19:32.112278 RX Delay -311 -> 252, step: 8
6812 23:19:32.112838
6813 23:19:32.115443 Set Vref, RX VrefLevel [Byte0]: 54
6814 23:19:32.118325 [Byte1]: 51
6815 23:19:32.122625
6816 23:19:32.123230 Final RX Vref Byte 0 = 54 to rank0
6817 23:19:32.125493 Final RX Vref Byte 1 = 51 to rank0
6818 23:19:32.129320 Final RX Vref Byte 0 = 54 to rank1
6819 23:19:32.132568 Final RX Vref Byte 1 = 51 to rank1==
6820 23:19:32.135471 Dram Type= 6, Freq= 0, CH_1, rank 0
6821 23:19:32.142723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6822 23:19:32.143449 ==
6823 23:19:32.143845 DQS Delay:
6824 23:19:32.145830 DQS0 = 32, DQS1 = 32
6825 23:19:32.146314 DQM Delay:
6826 23:19:32.146683 DQM0 = 13, DQM1 = 10
6827 23:19:32.149332 DQ Delay:
6828 23:19:32.152189 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6829 23:19:32.155936 DQ4 =12, DQ5 =24, DQ6 =20, DQ7 =12
6830 23:19:32.156414 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6831 23:19:32.159005 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =24
6832 23:19:32.162415
6833 23:19:32.162974
6834 23:19:32.169109 [DQSOSCAuto] RK0, (LSB)MR18= 0x91ca, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 391 ps
6835 23:19:32.172655 CH1 RK0: MR19=C0C, MR18=91CA
6836 23:19:32.179402 CH1_RK0: MR19=0xC0C, MR18=0x91CA, DQSOSC=384, MR23=63, INC=400, DEC=267
6837 23:19:32.180124 ==
6838 23:19:32.182182 Dram Type= 6, Freq= 0, CH_1, rank 1
6839 23:19:32.186079 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6840 23:19:32.186639 ==
6841 23:19:32.189148 [Gating] SW mode calibration
6842 23:19:32.195651 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6843 23:19:32.202267 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6844 23:19:32.205739 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6845 23:19:32.208843 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6846 23:19:32.215810 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6847 23:19:32.218525 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6848 23:19:32.222100 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6849 23:19:32.228548 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6850 23:19:32.232504 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6851 23:19:32.235153 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6852 23:19:32.242064 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6853 23:19:32.242648 Total UI for P1: 0, mck2ui 16
6854 23:19:32.245607 best dqsien dly found for B0: ( 0, 14, 24)
6855 23:19:32.248609 Total UI for P1: 0, mck2ui 16
6856 23:19:32.252262 best dqsien dly found for B1: ( 0, 14, 24)
6857 23:19:32.255134 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6858 23:19:32.261997 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6859 23:19:32.262668
6860 23:19:32.265272 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6861 23:19:32.268468 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6862 23:19:32.271976 [Gating] SW calibration Done
6863 23:19:32.272536 ==
6864 23:19:32.275321 Dram Type= 6, Freq= 0, CH_1, rank 1
6865 23:19:32.278325 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6866 23:19:32.278796 ==
6867 23:19:32.281754 RX Vref Scan: 0
6868 23:19:32.282221
6869 23:19:32.282591 RX Vref 0 -> 0, step: 1
6870 23:19:32.282937
6871 23:19:32.285005 RX Delay -410 -> 252, step: 16
6872 23:19:32.288541 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6873 23:19:32.295252 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6874 23:19:32.298359 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6875 23:19:32.301572 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6876 23:19:32.308023 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6877 23:19:32.311483 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6878 23:19:32.314702 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6879 23:19:32.317738 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6880 23:19:32.321164 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6881 23:19:32.327761 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6882 23:19:32.331342 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6883 23:19:32.334277 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6884 23:19:32.341198 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6885 23:19:32.344658 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6886 23:19:32.347923 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6887 23:19:32.351346 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6888 23:19:32.351869 ==
6889 23:19:32.354558 Dram Type= 6, Freq= 0, CH_1, rank 1
6890 23:19:32.361374 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6891 23:19:32.361965 ==
6892 23:19:32.362313 DQS Delay:
6893 23:19:32.364449 DQS0 = 35, DQS1 = 35
6894 23:19:32.365006 DQM Delay:
6895 23:19:32.367747 DQM0 = 18, DQM1 = 13
6896 23:19:32.368271 DQ Delay:
6897 23:19:32.371275 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6898 23:19:32.374542 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6899 23:19:32.377844 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6900 23:19:32.381096 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6901 23:19:32.381723
6902 23:19:32.382112
6903 23:19:32.382456 ==
6904 23:19:32.384727 Dram Type= 6, Freq= 0, CH_1, rank 1
6905 23:19:32.388012 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6906 23:19:32.388570 ==
6907 23:19:32.388939
6908 23:19:32.389277
6909 23:19:32.391325 TX Vref Scan disable
6910 23:19:32.391897 == TX Byte 0 ==
6911 23:19:32.397801 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6912 23:19:32.400697 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6913 23:19:32.401161 == TX Byte 1 ==
6914 23:19:32.407543 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6915 23:19:32.411278 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6916 23:19:32.411840 ==
6917 23:19:32.413955 Dram Type= 6, Freq= 0, CH_1, rank 1
6918 23:19:32.417383 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6919 23:19:32.417901 ==
6920 23:19:32.418276
6921 23:19:32.418614
6922 23:19:32.420875 TX Vref Scan disable
6923 23:19:32.421466 == TX Byte 0 ==
6924 23:19:32.427139 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6925 23:19:32.430752 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6926 23:19:32.431322 == TX Byte 1 ==
6927 23:19:32.437321 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6928 23:19:32.440479 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6929 23:19:32.441044
6930 23:19:32.441417 [DATLAT]
6931 23:19:32.443813 Freq=400, CH1 RK1
6932 23:19:32.444278
6933 23:19:32.444644 DATLAT Default: 0xe
6934 23:19:32.447269 0, 0xFFFF, sum = 0
6935 23:19:32.447841 1, 0xFFFF, sum = 0
6936 23:19:32.450593 2, 0xFFFF, sum = 0
6937 23:19:32.451159 3, 0xFFFF, sum = 0
6938 23:19:32.453750 4, 0xFFFF, sum = 0
6939 23:19:32.454220 5, 0xFFFF, sum = 0
6940 23:19:32.457182 6, 0xFFFF, sum = 0
6941 23:19:32.457703 7, 0xFFFF, sum = 0
6942 23:19:32.460713 8, 0xFFFF, sum = 0
6943 23:19:32.461277 9, 0xFFFF, sum = 0
6944 23:19:32.463878 10, 0xFFFF, sum = 0
6945 23:19:32.466712 11, 0xFFFF, sum = 0
6946 23:19:32.467188 12, 0xFFFF, sum = 0
6947 23:19:32.470238 13, 0x0, sum = 1
6948 23:19:32.470807 14, 0x0, sum = 2
6949 23:19:32.473880 15, 0x0, sum = 3
6950 23:19:32.474442 16, 0x0, sum = 4
6951 23:19:32.474823 best_step = 14
6952 23:19:32.475169
6953 23:19:32.477031 ==
6954 23:19:32.480551 Dram Type= 6, Freq= 0, CH_1, rank 1
6955 23:19:32.483654 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6956 23:19:32.484212 ==
6957 23:19:32.484584 RX Vref Scan: 0
6958 23:19:32.484926
6959 23:19:32.486891 RX Vref 0 -> 0, step: 1
6960 23:19:32.487357
6961 23:19:32.490280 RX Delay -311 -> 252, step: 8
6962 23:19:32.496893 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6963 23:19:32.500154 iDelay=217, Bit 1, Center -24 (-247 ~ 200) 448
6964 23:19:32.503964 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
6965 23:19:32.506925 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6966 23:19:32.513825 iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440
6967 23:19:32.517891 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
6968 23:19:32.520463 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6969 23:19:32.523666 iDelay=217, Bit 7, Center -24 (-247 ~ 200) 448
6970 23:19:32.530226 iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448
6971 23:19:32.533540 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6972 23:19:32.536595 iDelay=217, Bit 10, Center -16 (-239 ~ 208) 448
6973 23:19:32.540558 iDelay=217, Bit 11, Center -24 (-247 ~ 200) 448
6974 23:19:32.547162 iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456
6975 23:19:32.550077 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
6976 23:19:32.553491 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6977 23:19:32.560013 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
6978 23:19:32.560482 ==
6979 23:19:32.563254 Dram Type= 6, Freq= 0, CH_1, rank 1
6980 23:19:32.566536 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6981 23:19:32.567010 ==
6982 23:19:32.567382 DQS Delay:
6983 23:19:32.570265 DQS0 = 28, DQS1 = 32
6984 23:19:32.570822 DQM Delay:
6985 23:19:32.573738 DQM0 = 9, DQM1 = 12
6986 23:19:32.574296 DQ Delay:
6987 23:19:32.577162 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =4
6988 23:19:32.580472 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =4
6989 23:19:32.583982 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6990 23:19:32.587235 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =20
6991 23:19:32.587792
6992 23:19:32.588157
6993 23:19:32.593526 [DQSOSCAuto] RK1, (LSB)MR18= 0xc557, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 385 ps
6994 23:19:32.597073 CH1 RK1: MR19=C0C, MR18=C557
6995 23:19:32.603370 CH1_RK1: MR19=0xC0C, MR18=0xC557, DQSOSC=385, MR23=63, INC=398, DEC=265
6996 23:19:32.606937 [RxdqsGatingPostProcess] freq 400
6997 23:19:32.610251 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6998 23:19:32.613189 best DQS0 dly(2T, 0.5T) = (0, 10)
6999 23:19:32.616552 best DQS1 dly(2T, 0.5T) = (0, 10)
7000 23:19:32.619711 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7001 23:19:32.623426 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7002 23:19:32.626729 best DQS0 dly(2T, 0.5T) = (0, 10)
7003 23:19:32.629692 best DQS1 dly(2T, 0.5T) = (0, 10)
7004 23:19:32.633171 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7005 23:19:32.636727 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7006 23:19:32.639599 Pre-setting of DQS Precalculation
7007 23:19:32.643264 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7008 23:19:32.652693 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7009 23:19:32.659496 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7010 23:19:32.660171
7011 23:19:32.660557
7012 23:19:32.662430 [Calibration Summary] 800 Mbps
7013 23:19:32.662900 CH 0, Rank 0
7014 23:19:32.666160 SW Impedance : PASS
7015 23:19:32.666856 DUTY Scan : NO K
7016 23:19:32.669192 ZQ Calibration : PASS
7017 23:19:32.672869 Jitter Meter : NO K
7018 23:19:32.673427 CBT Training : PASS
7019 23:19:32.676106 Write leveling : PASS
7020 23:19:32.679632 RX DQS gating : PASS
7021 23:19:32.680190 RX DQ/DQS(RDDQC) : PASS
7022 23:19:32.682940 TX DQ/DQS : PASS
7023 23:19:32.686524 RX DATLAT : PASS
7024 23:19:32.687082 RX DQ/DQS(Engine): PASS
7025 23:19:32.690152 TX OE : NO K
7026 23:19:32.690712 All Pass.
7027 23:19:32.691082
7028 23:19:32.693308 CH 0, Rank 1
7029 23:19:32.693945 SW Impedance : PASS
7030 23:19:32.696326 DUTY Scan : NO K
7031 23:19:32.699681 ZQ Calibration : PASS
7032 23:19:32.700242 Jitter Meter : NO K
7033 23:19:32.702549 CBT Training : PASS
7034 23:19:32.705999 Write leveling : NO K
7035 23:19:32.706560 RX DQS gating : PASS
7036 23:19:32.709336 RX DQ/DQS(RDDQC) : PASS
7037 23:19:32.710137 TX DQ/DQS : PASS
7038 23:19:32.712342 RX DATLAT : PASS
7039 23:19:32.715701 RX DQ/DQS(Engine): PASS
7040 23:19:32.716338 TX OE : NO K
7041 23:19:32.719030 All Pass.
7042 23:19:32.719495
7043 23:19:32.719863 CH 1, Rank 0
7044 23:19:32.722556 SW Impedance : PASS
7045 23:19:32.723116 DUTY Scan : NO K
7046 23:19:32.725765 ZQ Calibration : PASS
7047 23:19:32.728687 Jitter Meter : NO K
7048 23:19:32.729154 CBT Training : PASS
7049 23:19:32.731968 Write leveling : PASS
7050 23:19:32.735724 RX DQS gating : PASS
7051 23:19:32.736192 RX DQ/DQS(RDDQC) : PASS
7052 23:19:32.739165 TX DQ/DQS : PASS
7053 23:19:32.742438 RX DATLAT : PASS
7054 23:19:32.742990 RX DQ/DQS(Engine): PASS
7055 23:19:32.745414 TX OE : NO K
7056 23:19:32.745937 All Pass.
7057 23:19:32.746311
7058 23:19:32.748705 CH 1, Rank 1
7059 23:19:32.749266 SW Impedance : PASS
7060 23:19:32.752335 DUTY Scan : NO K
7061 23:19:32.755706 ZQ Calibration : PASS
7062 23:19:32.756174 Jitter Meter : NO K
7063 23:19:32.758887 CBT Training : PASS
7064 23:19:32.761955 Write leveling : NO K
7065 23:19:32.762420 RX DQS gating : PASS
7066 23:19:32.765283 RX DQ/DQS(RDDQC) : PASS
7067 23:19:32.768574 TX DQ/DQS : PASS
7068 23:19:32.769135 RX DATLAT : PASS
7069 23:19:32.771942 RX DQ/DQS(Engine): PASS
7070 23:19:32.775456 TX OE : NO K
7071 23:19:32.776017 All Pass.
7072 23:19:32.776391
7073 23:19:32.776737 DramC Write-DBI off
7074 23:19:32.778213 PER_BANK_REFRESH: Hybrid Mode
7075 23:19:32.781834 TX_TRACKING: ON
7076 23:19:32.789013 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7077 23:19:32.792353 [FAST_K] Save calibration result to emmc
7078 23:19:32.798587 dramc_set_vcore_voltage set vcore to 725000
7079 23:19:32.799147 Read voltage for 1600, 0
7080 23:19:32.801991 Vio18 = 0
7081 23:19:32.802449 Vcore = 725000
7082 23:19:32.802812 Vdram = 0
7083 23:19:32.804812 Vddq = 0
7084 23:19:32.805268 Vmddr = 0
7085 23:19:32.808519 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7086 23:19:32.815351 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7087 23:19:32.818151 MEM_TYPE=3, freq_sel=13
7088 23:19:32.818609 sv_algorithm_assistance_LP4_3733
7089 23:19:32.824759 ============ PULL DRAM RESETB DOWN ============
7090 23:19:32.828314 ========== PULL DRAM RESETB DOWN end =========
7091 23:19:32.831391 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7092 23:19:32.834604 ===================================
7093 23:19:32.838096 LPDDR4 DRAM CONFIGURATION
7094 23:19:32.841652 ===================================
7095 23:19:32.844691 EX_ROW_EN[0] = 0x0
7096 23:19:32.845109 EX_ROW_EN[1] = 0x0
7097 23:19:32.847978 LP4Y_EN = 0x0
7098 23:19:32.848392 WORK_FSP = 0x1
7099 23:19:32.852021 WL = 0x5
7100 23:19:32.852537 RL = 0x5
7101 23:19:32.854769 BL = 0x2
7102 23:19:32.855186 RPST = 0x0
7103 23:19:32.857994 RD_PRE = 0x0
7104 23:19:32.858523 WR_PRE = 0x1
7105 23:19:32.861456 WR_PST = 0x1
7106 23:19:32.864855 DBI_WR = 0x0
7107 23:19:32.865388 DBI_RD = 0x0
7108 23:19:32.867911 OTF = 0x1
7109 23:19:32.871413 ===================================
7110 23:19:32.874552 ===================================
7111 23:19:32.874993 ANA top config
7112 23:19:32.877923 ===================================
7113 23:19:32.880978 DLL_ASYNC_EN = 0
7114 23:19:32.881401 ALL_SLAVE_EN = 0
7115 23:19:32.884702 NEW_RANK_MODE = 1
7116 23:19:32.887931 DLL_IDLE_MODE = 1
7117 23:19:32.891824 LP45_APHY_COMB_EN = 1
7118 23:19:32.894370 TX_ODT_DIS = 0
7119 23:19:32.894840 NEW_8X_MODE = 1
7120 23:19:32.897852 ===================================
7121 23:19:32.900918 ===================================
7122 23:19:32.904547 data_rate = 3200
7123 23:19:32.908371 CKR = 1
7124 23:19:32.911142 DQ_P2S_RATIO = 8
7125 23:19:32.914566 ===================================
7126 23:19:32.917949 CA_P2S_RATIO = 8
7127 23:19:32.921224 DQ_CA_OPEN = 0
7128 23:19:32.921828 DQ_SEMI_OPEN = 0
7129 23:19:32.924651 CA_SEMI_OPEN = 0
7130 23:19:32.928252 CA_FULL_RATE = 0
7131 23:19:32.931327 DQ_CKDIV4_EN = 0
7132 23:19:32.934175 CA_CKDIV4_EN = 0
7133 23:19:32.937968 CA_PREDIV_EN = 0
7134 23:19:32.938428 PH8_DLY = 12
7135 23:19:32.941168 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7136 23:19:32.944095 DQ_AAMCK_DIV = 4
7137 23:19:32.947831 CA_AAMCK_DIV = 4
7138 23:19:32.951228 CA_ADMCK_DIV = 4
7139 23:19:32.954413 DQ_TRACK_CA_EN = 0
7140 23:19:32.954869 CA_PICK = 1600
7141 23:19:32.957242 CA_MCKIO = 1600
7142 23:19:32.960617 MCKIO_SEMI = 0
7143 23:19:32.964383 PLL_FREQ = 3068
7144 23:19:32.967358 DQ_UI_PI_RATIO = 32
7145 23:19:32.971076 CA_UI_PI_RATIO = 0
7146 23:19:32.974246 ===================================
7147 23:19:32.977614 ===================================
7148 23:19:32.981231 memory_type:LPDDR4
7149 23:19:32.981899 GP_NUM : 10
7150 23:19:32.984031 SRAM_EN : 1
7151 23:19:32.984488 MD32_EN : 0
7152 23:19:32.987843 ===================================
7153 23:19:32.991265 [ANA_INIT] >>>>>>>>>>>>>>
7154 23:19:32.994062 <<<<<< [CONFIGURE PHASE]: ANA_TX
7155 23:19:32.997478 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7156 23:19:33.000857 ===================================
7157 23:19:33.004451 data_rate = 3200,PCW = 0X7600
7158 23:19:33.007803 ===================================
7159 23:19:33.010553 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7160 23:19:33.014288 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7161 23:19:33.021129 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7162 23:19:33.024571 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7163 23:19:33.030523 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7164 23:19:33.034309 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7165 23:19:33.034874 [ANA_INIT] flow start
7166 23:19:33.037144 [ANA_INIT] PLL >>>>>>>>
7167 23:19:33.040486 [ANA_INIT] PLL <<<<<<<<
7168 23:19:33.040947 [ANA_INIT] MIDPI >>>>>>>>
7169 23:19:33.044158 [ANA_INIT] MIDPI <<<<<<<<
7170 23:19:33.046873 [ANA_INIT] DLL >>>>>>>>
7171 23:19:33.047339 [ANA_INIT] DLL <<<<<<<<
7172 23:19:33.050512 [ANA_INIT] flow end
7173 23:19:33.053889 ============ LP4 DIFF to SE enter ============
7174 23:19:33.057071 ============ LP4 DIFF to SE exit ============
7175 23:19:33.060141 [ANA_INIT] <<<<<<<<<<<<<
7176 23:19:33.063755 [Flow] Enable top DCM control >>>>>
7177 23:19:33.066814 [Flow] Enable top DCM control <<<<<
7178 23:19:33.070254 Enable DLL master slave shuffle
7179 23:19:33.077223 ==============================================================
7180 23:19:33.077839 Gating Mode config
7181 23:19:33.083593 ==============================================================
7182 23:19:33.084056 Config description:
7183 23:19:33.093510 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7184 23:19:33.100710 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7185 23:19:33.106903 SELPH_MODE 0: By rank 1: By Phase
7186 23:19:33.110089 ==============================================================
7187 23:19:33.113502 GAT_TRACK_EN = 1
7188 23:19:33.117203 RX_GATING_MODE = 2
7189 23:19:33.120124 RX_GATING_TRACK_MODE = 2
7190 23:19:33.123271 SELPH_MODE = 1
7191 23:19:33.126563 PICG_EARLY_EN = 1
7192 23:19:33.130100 VALID_LAT_VALUE = 1
7193 23:19:33.136552 ==============================================================
7194 23:19:33.139978 Enter into Gating configuration >>>>
7195 23:19:33.143467 Exit from Gating configuration <<<<
7196 23:19:33.144024 Enter into DVFS_PRE_config >>>>>
7197 23:19:33.156993 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7198 23:19:33.159818 Exit from DVFS_PRE_config <<<<<
7199 23:19:33.163346 Enter into PICG configuration >>>>
7200 23:19:33.166688 Exit from PICG configuration <<<<
7201 23:19:33.167155 [RX_INPUT] configuration >>>>>
7202 23:19:33.169998 [RX_INPUT] configuration <<<<<
7203 23:19:33.176974 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7204 23:19:33.183485 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7205 23:19:33.186227 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7206 23:19:33.193308 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7207 23:19:33.199891 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7208 23:19:33.206620 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7209 23:19:33.209974 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7210 23:19:33.213272 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7211 23:19:33.219570 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7212 23:19:33.222890 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7213 23:19:33.226323 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7214 23:19:33.232918 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7215 23:19:33.236239 ===================================
7216 23:19:33.236721 LPDDR4 DRAM CONFIGURATION
7217 23:19:33.239543 ===================================
7218 23:19:33.242778 EX_ROW_EN[0] = 0x0
7219 23:19:33.243392 EX_ROW_EN[1] = 0x0
7220 23:19:33.246218 LP4Y_EN = 0x0
7221 23:19:33.246785 WORK_FSP = 0x1
7222 23:19:33.249407 WL = 0x5
7223 23:19:33.252531 RL = 0x5
7224 23:19:33.253086 BL = 0x2
7225 23:19:33.256257 RPST = 0x0
7226 23:19:33.256829 RD_PRE = 0x0
7227 23:19:33.259364 WR_PRE = 0x1
7228 23:19:33.260102 WR_PST = 0x1
7229 23:19:33.262810 DBI_WR = 0x0
7230 23:19:33.263291 DBI_RD = 0x0
7231 23:19:33.266385 OTF = 0x1
7232 23:19:33.269516 ===================================
7233 23:19:33.273065 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7234 23:19:33.276260 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7235 23:19:33.279582 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7236 23:19:33.282681 ===================================
7237 23:19:33.285821 LPDDR4 DRAM CONFIGURATION
7238 23:19:33.289266 ===================================
7239 23:19:33.292640 EX_ROW_EN[0] = 0x10
7240 23:19:33.293264 EX_ROW_EN[1] = 0x0
7241 23:19:33.295686 LP4Y_EN = 0x0
7242 23:19:33.296149 WORK_FSP = 0x1
7243 23:19:33.298899 WL = 0x5
7244 23:19:33.299359 RL = 0x5
7245 23:19:33.302084 BL = 0x2
7246 23:19:33.302542 RPST = 0x0
7247 23:19:33.305835 RD_PRE = 0x0
7248 23:19:33.309431 WR_PRE = 0x1
7249 23:19:33.310057 WR_PST = 0x1
7250 23:19:33.312416 DBI_WR = 0x0
7251 23:19:33.312873 DBI_RD = 0x0
7252 23:19:33.316063 OTF = 0x1
7253 23:19:33.319563 ===================================
7254 23:19:33.322785 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7255 23:19:33.325809 ==
7256 23:19:33.326447 Dram Type= 6, Freq= 0, CH_0, rank 0
7257 23:19:33.332101 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7258 23:19:33.332568 ==
7259 23:19:33.335550 [Duty_Offset_Calibration]
7260 23:19:33.336028 B0:2 B1:1 CA:1
7261 23:19:33.336400
7262 23:19:33.338703 [DutyScan_Calibration_Flow] k_type=0
7263 23:19:33.348596
7264 23:19:33.349016 ==CLK 0==
7265 23:19:33.352017 Final CLK duty delay cell = 0
7266 23:19:33.355541 [0] MAX Duty = 5156%(X100), DQS PI = 22
7267 23:19:33.358890 [0] MIN Duty = 4876%(X100), DQS PI = 48
7268 23:19:33.359309 [0] AVG Duty = 5016%(X100)
7269 23:19:33.361888
7270 23:19:33.365310 CH0 CLK Duty spec in!! Max-Min= 280%
7271 23:19:33.368277 [DutyScan_Calibration_Flow] ====Done====
7272 23:19:33.368694
7273 23:19:33.371886 [DutyScan_Calibration_Flow] k_type=1
7274 23:19:33.387941
7275 23:19:33.388493 ==DQS 0 ==
7276 23:19:33.391419 Final DQS duty delay cell = -4
7277 23:19:33.394622 [-4] MAX Duty = 5125%(X100), DQS PI = 24
7278 23:19:33.397752 [-4] MIN Duty = 4657%(X100), DQS PI = 0
7279 23:19:33.401094 [-4] AVG Duty = 4891%(X100)
7280 23:19:33.401511
7281 23:19:33.401887 ==DQS 1 ==
7282 23:19:33.404627 Final DQS duty delay cell = 0
7283 23:19:33.407836 [0] MAX Duty = 5187%(X100), DQS PI = 4
7284 23:19:33.411219 [0] MIN Duty = 5031%(X100), DQS PI = 52
7285 23:19:33.414724 [0] AVG Duty = 5109%(X100)
7286 23:19:33.415283
7287 23:19:33.418208 CH0 DQS 0 Duty spec in!! Max-Min= 468%
7288 23:19:33.418770
7289 23:19:33.420795 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7290 23:19:33.424464 [DutyScan_Calibration_Flow] ====Done====
7291 23:19:33.425023
7292 23:19:33.427773 [DutyScan_Calibration_Flow] k_type=3
7293 23:19:33.444900
7294 23:19:33.445455 ==DQM 0 ==
7295 23:19:33.448365 Final DQM duty delay cell = 0
7296 23:19:33.451278 [0] MAX Duty = 5187%(X100), DQS PI = 26
7297 23:19:33.454812 [0] MIN Duty = 4907%(X100), DQS PI = 54
7298 23:19:33.458205 [0] AVG Duty = 5047%(X100)
7299 23:19:33.458770
7300 23:19:33.459137 ==DQM 1 ==
7301 23:19:33.461490 Final DQM duty delay cell = -4
7302 23:19:33.465129 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7303 23:19:33.467467 [-4] MIN Duty = 4844%(X100), DQS PI = 12
7304 23:19:33.471283 [-4] AVG Duty = 4922%(X100)
7305 23:19:33.471849
7306 23:19:33.474326 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7307 23:19:33.474791
7308 23:19:33.478014 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7309 23:19:33.481342 [DutyScan_Calibration_Flow] ====Done====
7310 23:19:33.481971
7311 23:19:33.484258 [DutyScan_Calibration_Flow] k_type=2
7312 23:19:33.501947
7313 23:19:33.502529 ==DQ 0 ==
7314 23:19:33.505358 Final DQ duty delay cell = 0
7315 23:19:33.508725 [0] MAX Duty = 5062%(X100), DQS PI = 26
7316 23:19:33.512068 [0] MIN Duty = 4907%(X100), DQS PI = 0
7317 23:19:33.512587 [0] AVG Duty = 4984%(X100)
7318 23:19:33.512960
7319 23:19:33.515775 ==DQ 1 ==
7320 23:19:33.518875 Final DQ duty delay cell = 0
7321 23:19:33.522226 [0] MAX Duty = 5125%(X100), DQS PI = 6
7322 23:19:33.525544 [0] MIN Duty = 4907%(X100), DQS PI = 34
7323 23:19:33.526137 [0] AVG Duty = 5016%(X100)
7324 23:19:33.526582
7325 23:19:33.528309 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7326 23:19:33.528779
7327 23:19:33.535557 CH0 DQ 1 Duty spec in!! Max-Min= 218%
7328 23:19:33.538540 [DutyScan_Calibration_Flow] ====Done====
7329 23:19:33.539028 ==
7330 23:19:33.541517 Dram Type= 6, Freq= 0, CH_1, rank 0
7331 23:19:33.544919 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7332 23:19:33.545383 ==
7333 23:19:33.548110 [Duty_Offset_Calibration]
7334 23:19:33.548571 B0:1 B1:0 CA:0
7335 23:19:33.548940
7336 23:19:33.551721 [DutyScan_Calibration_Flow] k_type=0
7337 23:19:33.561170
7338 23:19:33.561822 ==CLK 0==
7339 23:19:33.564264 Final CLK duty delay cell = -4
7340 23:19:33.568196 [-4] MAX Duty = 4969%(X100), DQS PI = 28
7341 23:19:33.571676 [-4] MIN Duty = 4844%(X100), DQS PI = 2
7342 23:19:33.574718 [-4] AVG Duty = 4906%(X100)
7343 23:19:33.575246
7344 23:19:33.577785 CH1 CLK Duty spec in!! Max-Min= 125%
7345 23:19:33.581411 [DutyScan_Calibration_Flow] ====Done====
7346 23:19:33.582000
7347 23:19:33.584180 [DutyScan_Calibration_Flow] k_type=1
7348 23:19:33.601398
7349 23:19:33.602110 ==DQS 0 ==
7350 23:19:33.604571 Final DQS duty delay cell = 0
7351 23:19:33.607947 [0] MAX Duty = 5094%(X100), DQS PI = 24
7352 23:19:33.611030 [0] MIN Duty = 4844%(X100), DQS PI = 16
7353 23:19:33.614950 [0] AVG Duty = 4969%(X100)
7354 23:19:33.615514
7355 23:19:33.615886 ==DQS 1 ==
7356 23:19:33.617905 Final DQS duty delay cell = 0
7357 23:19:33.621154 [0] MAX Duty = 5249%(X100), DQS PI = 48
7358 23:19:33.624723 [0] MIN Duty = 4938%(X100), DQS PI = 40
7359 23:19:33.627592 [0] AVG Duty = 5093%(X100)
7360 23:19:33.628053
7361 23:19:33.631200 CH1 DQS 0 Duty spec in!! Max-Min= 250%
7362 23:19:33.631680
7363 23:19:33.634175 CH1 DQS 1 Duty spec in!! Max-Min= 311%
7364 23:19:33.637383 [DutyScan_Calibration_Flow] ====Done====
7365 23:19:33.637919
7366 23:19:33.640629 [DutyScan_Calibration_Flow] k_type=3
7367 23:19:33.658710
7368 23:19:33.659274 ==DQM 0 ==
7369 23:19:33.661530 Final DQM duty delay cell = 0
7370 23:19:33.665088 [0] MAX Duty = 5187%(X100), DQS PI = 42
7371 23:19:33.668552 [0] MIN Duty = 5000%(X100), DQS PI = 16
7372 23:19:33.671580 [0] AVG Duty = 5093%(X100)
7373 23:19:33.672189
7374 23:19:33.672724 ==DQM 1 ==
7375 23:19:33.674907 Final DQM duty delay cell = 0
7376 23:19:33.678246 [0] MAX Duty = 5093%(X100), DQS PI = 10
7377 23:19:33.681992 [0] MIN Duty = 4907%(X100), DQS PI = 0
7378 23:19:33.684826 [0] AVG Duty = 5000%(X100)
7379 23:19:33.685384
7380 23:19:33.688535 CH1 DQM 0 Duty spec in!! Max-Min= 187%
7381 23:19:33.689101
7382 23:19:33.691320 CH1 DQM 1 Duty spec in!! Max-Min= 186%
7383 23:19:33.694823 [DutyScan_Calibration_Flow] ====Done====
7384 23:19:33.695389
7385 23:19:33.698219 [DutyScan_Calibration_Flow] k_type=2
7386 23:19:33.714818
7387 23:19:33.715376 ==DQ 0 ==
7388 23:19:33.717656 Final DQ duty delay cell = -4
7389 23:19:33.721374 [-4] MAX Duty = 5062%(X100), DQS PI = 26
7390 23:19:33.724434 [-4] MIN Duty = 4875%(X100), DQS PI = 14
7391 23:19:33.727846 [-4] AVG Duty = 4968%(X100)
7392 23:19:33.728312
7393 23:19:33.728675 ==DQ 1 ==
7394 23:19:33.730691 Final DQ duty delay cell = 0
7395 23:19:33.734280 [0] MAX Duty = 5125%(X100), DQS PI = 10
7396 23:19:33.737828 [0] MIN Duty = 4907%(X100), DQS PI = 42
7397 23:19:33.740874 [0] AVG Duty = 5016%(X100)
7398 23:19:33.741337
7399 23:19:33.744374 CH1 DQ 0 Duty spec in!! Max-Min= 187%
7400 23:19:33.744937
7401 23:19:33.747561 CH1 DQ 1 Duty spec in!! Max-Min= 218%
7402 23:19:33.750687 [DutyScan_Calibration_Flow] ====Done====
7403 23:19:33.754107 nWR fixed to 30
7404 23:19:33.754566 [ModeRegInit_LP4] CH0 RK0
7405 23:19:33.757664 [ModeRegInit_LP4] CH0 RK1
7406 23:19:33.760929 [ModeRegInit_LP4] CH1 RK0
7407 23:19:33.764078 [ModeRegInit_LP4] CH1 RK1
7408 23:19:33.764609 match AC timing 5
7409 23:19:33.771271 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7410 23:19:33.774086 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7411 23:19:33.777540 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7412 23:19:33.784299 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7413 23:19:33.787992 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7414 23:19:33.788560 [MiockJmeterHQA]
7415 23:19:33.788928
7416 23:19:33.790805 [DramcMiockJmeter] u1RxGatingPI = 0
7417 23:19:33.794174 0 : 4253, 4026
7418 23:19:33.794744 4 : 4253, 4027
7419 23:19:33.797548 8 : 4363, 4137
7420 23:19:33.798194 12 : 4363, 4137
7421 23:19:33.798572 16 : 4363, 4138
7422 23:19:33.801088 20 : 4253, 4026
7423 23:19:33.801709 24 : 4363, 4138
7424 23:19:33.804241 28 : 4252, 4027
7425 23:19:33.804820 32 : 4252, 4026
7426 23:19:33.807272 36 : 4253, 4027
7427 23:19:33.807929 40 : 4258, 4029
7428 23:19:33.810778 44 : 4252, 4027
7429 23:19:33.811262 48 : 4255, 4029
7430 23:19:33.811703 52 : 4253, 4026
7431 23:19:33.813903 56 : 4257, 4030
7432 23:19:33.814405 60 : 4366, 4139
7433 23:19:33.817093 64 : 4252, 4027
7434 23:19:33.817553 68 : 4255, 4029
7435 23:19:33.821020 72 : 4250, 4026
7436 23:19:33.821633 76 : 4366, 4140
7437 23:19:33.824134 80 : 4250, 4027
7438 23:19:33.824708 84 : 4250, 4026
7439 23:19:33.825090 88 : 4252, 134
7440 23:19:33.827262 92 : 4250, 0
7441 23:19:33.827732 96 : 4363, 0
7442 23:19:33.828107 100 : 4252, 0
7443 23:19:33.830736 104 : 4250, 0
7444 23:19:33.831203 108 : 4250, 0
7445 23:19:33.834550 112 : 4249, 0
7446 23:19:33.835120 116 : 4249, 0
7447 23:19:33.835494 120 : 4363, 0
7448 23:19:33.837037 124 : 4250, 0
7449 23:19:33.837530 128 : 4360, 0
7450 23:19:33.840404 132 : 4255, 0
7451 23:19:33.840874 136 : 4250, 0
7452 23:19:33.841245 140 : 4250, 0
7453 23:19:33.843781 144 : 4252, 0
7454 23:19:33.844246 148 : 4360, 0
7455 23:19:33.847257 152 : 4250, 0
7456 23:19:33.847726 156 : 4250, 0
7457 23:19:33.848192 160 : 4250, 0
7458 23:19:33.850125 164 : 4363, 0
7459 23:19:33.850594 168 : 4249, 0
7460 23:19:33.853952 172 : 4361, 0
7461 23:19:33.854379 176 : 4250, 0
7462 23:19:33.854717 180 : 4360, 0
7463 23:19:33.857268 184 : 4250, 0
7464 23:19:33.857727 188 : 4250, 0
7465 23:19:33.858074 192 : 4250, 0
7466 23:19:33.860538 196 : 4250, 0
7467 23:19:33.860961 200 : 4360, 0
7468 23:19:33.863589 204 : 4250, 1322
7469 23:19:33.864118 208 : 4250, 3979
7470 23:19:33.866851 212 : 4361, 4138
7471 23:19:33.867275 216 : 4360, 4138
7472 23:19:33.870209 220 : 4247, 4024
7473 23:19:33.870633 224 : 4255, 4029
7474 23:19:33.873516 228 : 4250, 4026
7475 23:19:33.874096 232 : 4363, 4138
7476 23:19:33.874441 236 : 4250, 4027
7477 23:19:33.876823 240 : 4363, 4137
7478 23:19:33.877246 244 : 4250, 4026
7479 23:19:33.880364 248 : 4250, 4027
7480 23:19:33.880999 252 : 4249, 4027
7481 23:19:33.883598 256 : 4249, 4027
7482 23:19:33.884021 260 : 4250, 4026
7483 23:19:33.887073 264 : 4363, 4137
7484 23:19:33.887600 268 : 4250, 4027
7485 23:19:33.890275 272 : 4249, 4027
7486 23:19:33.890708 276 : 4250, 4027
7487 23:19:33.893322 280 : 4250, 4026
7488 23:19:33.893793 284 : 4360, 4138
7489 23:19:33.894138 288 : 4250, 4027
7490 23:19:33.897295 292 : 4360, 4137
7491 23:19:33.897887 296 : 4250, 4026
7492 23:19:33.900356 300 : 4250, 4027
7493 23:19:33.900940 304 : 4252, 4027
7494 23:19:33.903683 308 : 4249, 3980
7495 23:19:33.904216 312 : 4253, 2049
7496 23:19:33.904563
7497 23:19:33.907520 MIOCK jitter meter ch=0
7498 23:19:33.908047
7499 23:19:33.910140 1T = (312-88) = 224 dly cells
7500 23:19:33.917102 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7501 23:19:33.917710 ==
7502 23:19:33.921128 Dram Type= 6, Freq= 0, CH_0, rank 0
7503 23:19:33.923864 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7504 23:19:33.924425 ==
7505 23:19:33.930594 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7506 23:19:33.933758 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7507 23:19:33.936954 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7508 23:19:33.943824 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7509 23:19:33.952193 [CA 0] Center 43 (13~74) winsize 62
7510 23:19:33.955551 [CA 1] Center 43 (13~74) winsize 62
7511 23:19:33.958776 [CA 2] Center 38 (9~68) winsize 60
7512 23:19:33.962419 [CA 3] Center 38 (8~68) winsize 61
7513 23:19:33.965410 [CA 4] Center 37 (7~67) winsize 61
7514 23:19:33.968595 [CA 5] Center 36 (7~65) winsize 59
7515 23:19:33.969085
7516 23:19:33.972265 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7517 23:19:33.972833
7518 23:19:33.975439 [CATrainingPosCal] consider 1 rank data
7519 23:19:33.978855 u2DelayCellTimex100 = 290/100 ps
7520 23:19:33.982191 CA0 delay=43 (13~74),Diff = 7 PI (23 cell)
7521 23:19:33.989012 CA1 delay=43 (13~74),Diff = 7 PI (23 cell)
7522 23:19:33.991771 CA2 delay=38 (9~68),Diff = 2 PI (6 cell)
7523 23:19:33.995512 CA3 delay=38 (8~68),Diff = 2 PI (6 cell)
7524 23:19:33.998322 CA4 delay=37 (7~67),Diff = 1 PI (3 cell)
7525 23:19:34.001690 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
7526 23:19:34.002257
7527 23:19:34.004958 CA PerBit enable=1, Macro0, CA PI delay=36
7528 23:19:34.005424
7529 23:19:34.008489 [CBTSetCACLKResult] CA Dly = 36
7530 23:19:34.011603 CS Dly: 9 (0~40)
7531 23:19:34.015328 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7532 23:19:34.018210 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7533 23:19:34.018709 ==
7534 23:19:34.021551 Dram Type= 6, Freq= 0, CH_0, rank 1
7535 23:19:34.024961 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7536 23:19:34.028121 ==
7537 23:19:34.031776 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7538 23:19:34.035114 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7539 23:19:34.041401 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7540 23:19:34.045040 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7541 23:19:34.055251 [CA 0] Center 42 (12~73) winsize 62
7542 23:19:34.059148 [CA 1] Center 42 (12~73) winsize 62
7543 23:19:34.062162 [CA 2] Center 38 (8~68) winsize 61
7544 23:19:34.065745 [CA 3] Center 38 (8~68) winsize 61
7545 23:19:34.068466 [CA 4] Center 36 (6~66) winsize 61
7546 23:19:34.072234 [CA 5] Center 35 (5~65) winsize 61
7547 23:19:34.072803
7548 23:19:34.075215 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7549 23:19:34.075681
7550 23:19:34.078710 [CATrainingPosCal] consider 2 rank data
7551 23:19:34.082174 u2DelayCellTimex100 = 290/100 ps
7552 23:19:34.084919 CA0 delay=43 (13~73),Diff = 7 PI (23 cell)
7553 23:19:34.091794 CA1 delay=43 (13~73),Diff = 7 PI (23 cell)
7554 23:19:34.095604 CA2 delay=38 (9~68),Diff = 2 PI (6 cell)
7555 23:19:34.098856 CA3 delay=38 (8~68),Diff = 2 PI (6 cell)
7556 23:19:34.101906 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7557 23:19:34.105412 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
7558 23:19:34.106024
7559 23:19:34.108566 CA PerBit enable=1, Macro0, CA PI delay=36
7560 23:19:34.109128
7561 23:19:34.111852 [CBTSetCACLKResult] CA Dly = 36
7562 23:19:34.114865 CS Dly: 10 (0~42)
7563 23:19:34.118212 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7564 23:19:34.121944 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7565 23:19:34.122514
7566 23:19:34.125323 ----->DramcWriteLeveling(PI) begin...
7567 23:19:34.125825 ==
7568 23:19:34.128365 Dram Type= 6, Freq= 0, CH_0, rank 0
7569 23:19:34.135214 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7570 23:19:34.135789 ==
7571 23:19:34.138412 Write leveling (Byte 0): 37 => 37
7572 23:19:34.138877 Write leveling (Byte 1): 26 => 26
7573 23:19:34.141568 DramcWriteLeveling(PI) end<-----
7574 23:19:34.142076
7575 23:19:34.142443 ==
7576 23:19:34.144690 Dram Type= 6, Freq= 0, CH_0, rank 0
7577 23:19:34.151386 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7578 23:19:34.152052 ==
7579 23:19:34.154436 [Gating] SW mode calibration
7580 23:19:34.161529 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7581 23:19:34.164969 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7582 23:19:34.171796 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7583 23:19:34.174473 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7584 23:19:34.178192 1 4 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7585 23:19:34.185028 1 4 12 | B1->B0 | 2323 3635 | 0 1 | (0 0) (0 0)
7586 23:19:34.188038 1 4 16 | B1->B0 | 2323 3535 | 0 0 | (1 1) (1 1)
7587 23:19:34.191607 1 4 20 | B1->B0 | 3232 3636 | 1 0 | (1 1) (1 1)
7588 23:19:34.198305 1 4 24 | B1->B0 | 3434 3636 | 1 0 | (1 1) (0 0)
7589 23:19:34.201464 1 4 28 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7590 23:19:34.204684 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7591 23:19:34.211122 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7592 23:19:34.214326 1 5 8 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)
7593 23:19:34.217418 1 5 12 | B1->B0 | 3434 2b2b | 1 0 | (1 1) (0 0)
7594 23:19:34.224677 1 5 16 | B1->B0 | 3434 2424 | 1 0 | (1 0) (0 0)
7595 23:19:34.227749 1 5 20 | B1->B0 | 2b2b 2423 | 0 1 | (0 0) (0 0)
7596 23:19:34.230955 1 5 24 | B1->B0 | 2323 2524 | 0 1 | (0 0) (0 0)
7597 23:19:34.237634 1 5 28 | B1->B0 | 2323 2827 | 0 1 | (0 0) (0 0)
7598 23:19:34.240548 1 6 0 | B1->B0 | 2323 2626 | 0 1 | (0 0) (0 0)
7599 23:19:34.244279 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7600 23:19:34.248249 1 6 8 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
7601 23:19:34.254398 1 6 12 | B1->B0 | 2323 4645 | 0 1 | (0 0) (0 0)
7602 23:19:34.257715 1 6 16 | B1->B0 | 2a2a 4646 | 0 0 | (1 1) (0 0)
7603 23:19:34.260995 1 6 20 | B1->B0 | 4545 4645 | 0 1 | (0 0) (0 0)
7604 23:19:34.267087 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7605 23:19:34.270330 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7606 23:19:34.274419 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7607 23:19:34.281042 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7608 23:19:34.283953 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7609 23:19:34.287338 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7610 23:19:34.294184 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7611 23:19:34.297562 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7612 23:19:34.301087 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7613 23:19:34.307431 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7614 23:19:34.310510 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7615 23:19:34.314290 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7616 23:19:34.320640 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7617 23:19:34.324054 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7618 23:19:34.327164 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7619 23:19:34.333996 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7620 23:19:34.337453 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7621 23:19:34.340436 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7622 23:19:34.347753 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7623 23:19:34.350308 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7624 23:19:34.354073 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7625 23:19:34.360773 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7626 23:19:34.364049 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7627 23:19:34.366969 Total UI for P1: 0, mck2ui 16
7628 23:19:34.370160 best dqsien dly found for B0: ( 1, 9, 10)
7629 23:19:34.373537 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7630 23:19:34.376700 Total UI for P1: 0, mck2ui 16
7631 23:19:34.379931 best dqsien dly found for B1: ( 1, 9, 18)
7632 23:19:34.383592 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7633 23:19:34.386822 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7634 23:19:34.387436
7635 23:19:34.389903 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7636 23:19:34.396581 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7637 23:19:34.397010 [Gating] SW calibration Done
7638 23:19:34.400001 ==
7639 23:19:34.400423 Dram Type= 6, Freq= 0, CH_0, rank 0
7640 23:19:34.406967 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7641 23:19:34.407395 ==
7642 23:19:34.407728 RX Vref Scan: 0
7643 23:19:34.408041
7644 23:19:34.410334 RX Vref 0 -> 0, step: 1
7645 23:19:34.410757
7646 23:19:34.413462 RX Delay 0 -> 252, step: 8
7647 23:19:34.417011 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
7648 23:19:34.420381 iDelay=200, Bit 1, Center 143 (88 ~ 199) 112
7649 23:19:34.423758 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
7650 23:19:34.430437 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
7651 23:19:34.433445 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7652 23:19:34.436584 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7653 23:19:34.440117 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
7654 23:19:34.443770 iDelay=200, Bit 7, Center 143 (96 ~ 191) 96
7655 23:19:34.447252 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
7656 23:19:34.453751 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
7657 23:19:34.457157 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
7658 23:19:34.460571 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7659 23:19:34.463803 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7660 23:19:34.467040 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
7661 23:19:34.474254 iDelay=200, Bit 14, Center 143 (96 ~ 191) 96
7662 23:19:34.476703 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7663 23:19:34.477223 ==
7664 23:19:34.480192 Dram Type= 6, Freq= 0, CH_0, rank 0
7665 23:19:34.483460 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7666 23:19:34.483889 ==
7667 23:19:34.486477 DQS Delay:
7668 23:19:34.486990 DQS0 = 0, DQS1 = 0
7669 23:19:34.487329 DQM Delay:
7670 23:19:34.490108 DQM0 = 137, DQM1 = 130
7671 23:19:34.490529 DQ Delay:
7672 23:19:34.493235 DQ0 =135, DQ1 =143, DQ2 =135, DQ3 =135
7673 23:19:34.496842 DQ4 =139, DQ5 =123, DQ6 =143, DQ7 =143
7674 23:19:34.503424 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =123
7675 23:19:34.506900 DQ12 =131, DQ13 =139, DQ14 =143, DQ15 =135
7676 23:19:34.507412
7677 23:19:34.507795
7678 23:19:34.508113 ==
7679 23:19:34.509871 Dram Type= 6, Freq= 0, CH_0, rank 0
7680 23:19:34.513334 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7681 23:19:34.513913 ==
7682 23:19:34.514376
7683 23:19:34.514755
7684 23:19:34.516593 TX Vref Scan disable
7685 23:19:34.517046 == TX Byte 0 ==
7686 23:19:34.523136 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
7687 23:19:34.526491 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7688 23:19:34.527005 == TX Byte 1 ==
7689 23:19:34.533037 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7690 23:19:34.536649 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7691 23:19:34.537167 ==
7692 23:19:34.539527 Dram Type= 6, Freq= 0, CH_0, rank 0
7693 23:19:34.542916 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7694 23:19:34.543342 ==
7695 23:19:34.558106
7696 23:19:34.561649 TX Vref early break, caculate TX vref
7697 23:19:34.565338 TX Vref=16, minBit 1, minWin=22, winSum=375
7698 23:19:34.568519 TX Vref=18, minBit 0, minWin=23, winSum=386
7699 23:19:34.571644 TX Vref=20, minBit 3, minWin=23, winSum=394
7700 23:19:34.574706 TX Vref=22, minBit 2, minWin=24, winSum=404
7701 23:19:34.578616 TX Vref=24, minBit 0, minWin=25, winSum=416
7702 23:19:34.585459 TX Vref=26, minBit 2, minWin=25, winSum=426
7703 23:19:34.588631 TX Vref=28, minBit 1, minWin=24, winSum=420
7704 23:19:34.591704 TX Vref=30, minBit 4, minWin=24, winSum=414
7705 23:19:34.594918 TX Vref=32, minBit 1, minWin=24, winSum=405
7706 23:19:34.598368 TX Vref=34, minBit 6, minWin=23, winSum=397
7707 23:19:34.604877 [TxChooseVref] Worse bit 2, Min win 25, Win sum 426, Final Vref 26
7708 23:19:34.605440
7709 23:19:34.608336 Final TX Range 0 Vref 26
7710 23:19:34.608896
7711 23:19:34.609268 ==
7712 23:19:34.611597 Dram Type= 6, Freq= 0, CH_0, rank 0
7713 23:19:34.614772 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7714 23:19:34.615241 ==
7715 23:19:34.615621
7716 23:19:34.615964
7717 23:19:34.618194 TX Vref Scan disable
7718 23:19:34.624847 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7719 23:19:34.625405 == TX Byte 0 ==
7720 23:19:34.628427 u2DelayCellOfst[0]=13 cells (4 PI)
7721 23:19:34.631865 u2DelayCellOfst[1]=16 cells (5 PI)
7722 23:19:34.634833 u2DelayCellOfst[2]=13 cells (4 PI)
7723 23:19:34.638631 u2DelayCellOfst[3]=13 cells (4 PI)
7724 23:19:34.641676 u2DelayCellOfst[4]=10 cells (3 PI)
7725 23:19:34.644739 u2DelayCellOfst[5]=0 cells (0 PI)
7726 23:19:34.647949 u2DelayCellOfst[6]=16 cells (5 PI)
7727 23:19:34.651644 u2DelayCellOfst[7]=16 cells (5 PI)
7728 23:19:34.654974 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7729 23:19:34.657492 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7730 23:19:34.661061 == TX Byte 1 ==
7731 23:19:34.661530 u2DelayCellOfst[8]=3 cells (1 PI)
7732 23:19:34.664537 u2DelayCellOfst[9]=0 cells (0 PI)
7733 23:19:34.668156 u2DelayCellOfst[10]=6 cells (2 PI)
7734 23:19:34.671271 u2DelayCellOfst[11]=3 cells (1 PI)
7735 23:19:34.674737 u2DelayCellOfst[12]=10 cells (3 PI)
7736 23:19:34.677821 u2DelayCellOfst[13]=13 cells (4 PI)
7737 23:19:34.680972 u2DelayCellOfst[14]=16 cells (5 PI)
7738 23:19:34.684539 u2DelayCellOfst[15]=10 cells (3 PI)
7739 23:19:34.687855 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
7740 23:19:34.694231 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7741 23:19:34.694794 DramC Write-DBI on
7742 23:19:34.695166 ==
7743 23:19:34.697506 Dram Type= 6, Freq= 0, CH_0, rank 0
7744 23:19:34.704762 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7745 23:19:34.705327 ==
7746 23:19:34.705755
7747 23:19:34.706110
7748 23:19:34.706436 TX Vref Scan disable
7749 23:19:34.708279 == TX Byte 0 ==
7750 23:19:34.711254 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
7751 23:19:34.714409 == TX Byte 1 ==
7752 23:19:34.717937 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
7753 23:19:34.721033 DramC Write-DBI off
7754 23:19:34.721496
7755 23:19:34.721901 [DATLAT]
7756 23:19:34.722250 Freq=1600, CH0 RK0
7757 23:19:34.722589
7758 23:19:34.724518 DATLAT Default: 0xf
7759 23:19:34.727734 0, 0xFFFF, sum = 0
7760 23:19:34.728207 1, 0xFFFF, sum = 0
7761 23:19:34.731391 2, 0xFFFF, sum = 0
7762 23:19:34.731954 3, 0xFFFF, sum = 0
7763 23:19:34.734473 4, 0xFFFF, sum = 0
7764 23:19:34.734946 5, 0xFFFF, sum = 0
7765 23:19:34.737821 6, 0xFFFF, sum = 0
7766 23:19:34.738381 7, 0xFFFF, sum = 0
7767 23:19:34.740846 8, 0xFFFF, sum = 0
7768 23:19:34.741353 9, 0xFFFF, sum = 0
7769 23:19:34.745261 10, 0xFFFF, sum = 0
7770 23:19:34.745876 11, 0xFFFF, sum = 0
7771 23:19:34.747709 12, 0xFFFF, sum = 0
7772 23:19:34.748182 13, 0xFFFF, sum = 0
7773 23:19:34.751160 14, 0x0, sum = 1
7774 23:19:34.751634 15, 0x0, sum = 2
7775 23:19:34.754669 16, 0x0, sum = 3
7776 23:19:34.755234 17, 0x0, sum = 4
7777 23:19:34.757657 best_step = 15
7778 23:19:34.758127
7779 23:19:34.758498 ==
7780 23:19:34.761307 Dram Type= 6, Freq= 0, CH_0, rank 0
7781 23:19:34.764420 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7782 23:19:34.764981 ==
7783 23:19:34.768000 RX Vref Scan: 1
7784 23:19:34.768569
7785 23:19:34.768945 Set Vref Range= 24 -> 127
7786 23:19:34.769293
7787 23:19:34.771217 RX Vref 24 -> 127, step: 1
7788 23:19:34.771780
7789 23:19:34.774232 RX Delay 27 -> 252, step: 4
7790 23:19:34.774696
7791 23:19:34.777878 Set Vref, RX VrefLevel [Byte0]: 24
7792 23:19:34.781384 [Byte1]: 24
7793 23:19:34.782008
7794 23:19:34.784322 Set Vref, RX VrefLevel [Byte0]: 25
7795 23:19:34.788042 [Byte1]: 25
7796 23:19:34.788596
7797 23:19:34.791164 Set Vref, RX VrefLevel [Byte0]: 26
7798 23:19:34.793926 [Byte1]: 26
7799 23:19:34.798217
7800 23:19:34.798773 Set Vref, RX VrefLevel [Byte0]: 27
7801 23:19:34.801338 [Byte1]: 27
7802 23:19:34.806327
7803 23:19:34.806883 Set Vref, RX VrefLevel [Byte0]: 28
7804 23:19:34.809230 [Byte1]: 28
7805 23:19:34.813765
7806 23:19:34.814320 Set Vref, RX VrefLevel [Byte0]: 29
7807 23:19:34.816440 [Byte1]: 29
7808 23:19:34.821024
7809 23:19:34.821614 Set Vref, RX VrefLevel [Byte0]: 30
7810 23:19:34.824156 [Byte1]: 30
7811 23:19:34.828134
7812 23:19:34.828596 Set Vref, RX VrefLevel [Byte0]: 31
7813 23:19:34.831723 [Byte1]: 31
7814 23:19:34.836333
7815 23:19:34.836893 Set Vref, RX VrefLevel [Byte0]: 32
7816 23:19:34.839008 [Byte1]: 32
7817 23:19:34.843534
7818 23:19:34.844099 Set Vref, RX VrefLevel [Byte0]: 33
7819 23:19:34.846653 [Byte1]: 33
7820 23:19:34.851259
7821 23:19:34.851813 Set Vref, RX VrefLevel [Byte0]: 34
7822 23:19:34.854627 [Byte1]: 34
7823 23:19:34.858610
7824 23:19:34.859166 Set Vref, RX VrefLevel [Byte0]: 35
7825 23:19:34.861709 [Byte1]: 35
7826 23:19:34.865744
7827 23:19:34.866372 Set Vref, RX VrefLevel [Byte0]: 36
7828 23:19:34.869417 [Byte1]: 36
7829 23:19:34.873421
7830 23:19:34.873929 Set Vref, RX VrefLevel [Byte0]: 37
7831 23:19:34.876610 [Byte1]: 37
7832 23:19:34.880966
7833 23:19:34.881655 Set Vref, RX VrefLevel [Byte0]: 38
7834 23:19:34.884770 [Byte1]: 38
7835 23:19:34.888685
7836 23:19:34.889239 Set Vref, RX VrefLevel [Byte0]: 39
7837 23:19:34.891535 [Byte1]: 39
7838 23:19:34.896373
7839 23:19:34.896935 Set Vref, RX VrefLevel [Byte0]: 40
7840 23:19:34.899915 [Byte1]: 40
7841 23:19:34.904104
7842 23:19:34.904664 Set Vref, RX VrefLevel [Byte0]: 41
7843 23:19:34.907739 [Byte1]: 41
7844 23:19:34.911567
7845 23:19:34.912136 Set Vref, RX VrefLevel [Byte0]: 42
7846 23:19:34.914920 [Byte1]: 42
7847 23:19:34.918734
7848 23:19:34.919289 Set Vref, RX VrefLevel [Byte0]: 43
7849 23:19:34.922220 [Byte1]: 43
7850 23:19:34.926387
7851 23:19:34.926940 Set Vref, RX VrefLevel [Byte0]: 44
7852 23:19:34.929268 [Byte1]: 44
7853 23:19:34.933763
7854 23:19:34.934343 Set Vref, RX VrefLevel [Byte0]: 45
7855 23:19:34.936725 [Byte1]: 45
7856 23:19:34.941630
7857 23:19:34.942203 Set Vref, RX VrefLevel [Byte0]: 46
7858 23:19:34.944881 [Byte1]: 46
7859 23:19:34.948949
7860 23:19:34.949503 Set Vref, RX VrefLevel [Byte0]: 47
7861 23:19:34.952166 [Byte1]: 47
7862 23:19:34.956490
7863 23:19:34.957043 Set Vref, RX VrefLevel [Byte0]: 48
7864 23:19:34.959752 [Byte1]: 48
7865 23:19:34.964525
7866 23:19:34.965089 Set Vref, RX VrefLevel [Byte0]: 49
7867 23:19:34.967139 [Byte1]: 49
7868 23:19:34.971685
7869 23:19:34.972338 Set Vref, RX VrefLevel [Byte0]: 50
7870 23:19:34.974965 [Byte1]: 50
7871 23:19:34.978988
7872 23:19:34.979546 Set Vref, RX VrefLevel [Byte0]: 51
7873 23:19:34.982237 [Byte1]: 51
7874 23:19:34.986381
7875 23:19:34.986938 Set Vref, RX VrefLevel [Byte0]: 52
7876 23:19:34.989750 [Byte1]: 52
7877 23:19:34.993952
7878 23:19:34.994419 Set Vref, RX VrefLevel [Byte0]: 53
7879 23:19:34.997510 [Byte1]: 53
7880 23:19:35.001872
7881 23:19:35.002433 Set Vref, RX VrefLevel [Byte0]: 54
7882 23:19:35.005130 [Byte1]: 54
7883 23:19:35.009291
7884 23:19:35.009906 Set Vref, RX VrefLevel [Byte0]: 55
7885 23:19:35.012902 [Byte1]: 55
7886 23:19:35.016522
7887 23:19:35.016986 Set Vref, RX VrefLevel [Byte0]: 56
7888 23:19:35.020246 [Byte1]: 56
7889 23:19:35.024151
7890 23:19:35.024705 Set Vref, RX VrefLevel [Byte0]: 57
7891 23:19:35.027421 [Byte1]: 57
7892 23:19:35.031787
7893 23:19:35.032341 Set Vref, RX VrefLevel [Byte0]: 58
7894 23:19:35.035273 [Byte1]: 58
7895 23:19:35.039514
7896 23:19:35.040062 Set Vref, RX VrefLevel [Byte0]: 59
7897 23:19:35.042495 [Byte1]: 59
7898 23:19:35.046617
7899 23:19:35.047170 Set Vref, RX VrefLevel [Byte0]: 60
7900 23:19:35.049771 [Byte1]: 60
7901 23:19:35.054041
7902 23:19:35.054602 Set Vref, RX VrefLevel [Byte0]: 61
7903 23:19:35.057494 [Byte1]: 61
7904 23:19:35.061978
7905 23:19:35.062530 Set Vref, RX VrefLevel [Byte0]: 62
7906 23:19:35.065176 [Byte1]: 62
7907 23:19:35.069637
7908 23:19:35.070217 Set Vref, RX VrefLevel [Byte0]: 63
7909 23:19:35.072191 [Byte1]: 63
7910 23:19:35.077012
7911 23:19:35.077568 Set Vref, RX VrefLevel [Byte0]: 64
7912 23:19:35.080504 [Byte1]: 64
7913 23:19:35.084335
7914 23:19:35.084891 Set Vref, RX VrefLevel [Byte0]: 65
7915 23:19:35.087876 [Byte1]: 65
7916 23:19:35.091671
7917 23:19:35.092126 Set Vref, RX VrefLevel [Byte0]: 66
7918 23:19:35.095153 [Byte1]: 66
7919 23:19:35.099487
7920 23:19:35.100066 Set Vref, RX VrefLevel [Byte0]: 67
7921 23:19:35.103589 [Byte1]: 67
7922 23:19:35.106649
7923 23:19:35.107101 Set Vref, RX VrefLevel [Byte0]: 68
7924 23:19:35.110520 [Byte1]: 68
7925 23:19:35.114771
7926 23:19:35.115327 Set Vref, RX VrefLevel [Byte0]: 69
7927 23:19:35.118078 [Byte1]: 69
7928 23:19:35.122141
7929 23:19:35.122600 Set Vref, RX VrefLevel [Byte0]: 70
7930 23:19:35.124952 [Byte1]: 70
7931 23:19:35.129489
7932 23:19:35.130022 Set Vref, RX VrefLevel [Byte0]: 71
7933 23:19:35.133069 [Byte1]: 71
7934 23:19:35.137128
7935 23:19:35.137729 Set Vref, RX VrefLevel [Byte0]: 72
7936 23:19:35.140285 [Byte1]: 72
7937 23:19:35.144843
7938 23:19:35.145297 Set Vref, RX VrefLevel [Byte0]: 73
7939 23:19:35.148313 [Byte1]: 73
7940 23:19:35.152336
7941 23:19:35.152891 Set Vref, RX VrefLevel [Byte0]: 74
7942 23:19:35.155678 [Byte1]: 74
7943 23:19:35.159644
7944 23:19:35.160198 Final RX Vref Byte 0 = 58 to rank0
7945 23:19:35.163022 Final RX Vref Byte 1 = 63 to rank0
7946 23:19:35.166204 Final RX Vref Byte 0 = 58 to rank1
7947 23:19:35.169810 Final RX Vref Byte 1 = 63 to rank1==
7948 23:19:35.172849 Dram Type= 6, Freq= 0, CH_0, rank 0
7949 23:19:35.180205 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7950 23:19:35.180765 ==
7951 23:19:35.181135 DQS Delay:
7952 23:19:35.181474 DQS0 = 0, DQS1 = 0
7953 23:19:35.182575 DQM Delay:
7954 23:19:35.183028 DQM0 = 134, DQM1 = 127
7955 23:19:35.185962 DQ Delay:
7956 23:19:35.189430 DQ0 =134, DQ1 =138, DQ2 =134, DQ3 =134
7957 23:19:35.192941 DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =138
7958 23:19:35.196383 DQ8 =116, DQ9 =118, DQ10 =130, DQ11 =120
7959 23:19:35.199603 DQ12 =132, DQ13 =132, DQ14 =138, DQ15 =136
7960 23:19:35.200164
7961 23:19:35.200527
7962 23:19:35.200863
7963 23:19:35.203232 [DramC_TX_OE_Calibration] TA2
7964 23:19:35.206318 Original DQ_B0 (3 6) =30, OEN = 27
7965 23:19:35.209790 Original DQ_B1 (3 6) =30, OEN = 27
7966 23:19:35.212422 24, 0x0, End_B0=24 End_B1=24
7967 23:19:35.212885 25, 0x0, End_B0=25 End_B1=25
7968 23:19:35.216004 26, 0x0, End_B0=26 End_B1=26
7969 23:19:35.219035 27, 0x0, End_B0=27 End_B1=27
7970 23:19:35.222736 28, 0x0, End_B0=28 End_B1=28
7971 23:19:35.225702 29, 0x0, End_B0=29 End_B1=29
7972 23:19:35.226171 30, 0x0, End_B0=30 End_B1=30
7973 23:19:35.229497 31, 0x4141, End_B0=30 End_B1=30
7974 23:19:35.232408 Byte0 end_step=30 best_step=27
7975 23:19:35.235969 Byte1 end_step=30 best_step=27
7976 23:19:35.239508 Byte0 TX OE(2T, 0.5T) = (3, 3)
7977 23:19:35.242517 Byte1 TX OE(2T, 0.5T) = (3, 3)
7978 23:19:35.242979
7979 23:19:35.243347
7980 23:19:35.249107 [DQSOSCAuto] RK0, (LSB)MR18= 0x2521, (MSB)MR19= 0x303, tDQSOscB0 = 393 ps tDQSOscB1 = 391 ps
7981 23:19:35.253225 CH0 RK0: MR19=303, MR18=2521
7982 23:19:35.259032 CH0_RK0: MR19=0x303, MR18=0x2521, DQSOSC=391, MR23=63, INC=24, DEC=16
7983 23:19:35.259512
7984 23:19:35.262579 ----->DramcWriteLeveling(PI) begin...
7985 23:19:35.263046 ==
7986 23:19:35.265965 Dram Type= 6, Freq= 0, CH_0, rank 1
7987 23:19:35.269548 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7988 23:19:35.270157 ==
7989 23:19:35.272516 Write leveling (Byte 0): 36 => 36
7990 23:19:35.276517 Write leveling (Byte 1): 28 => 28
7991 23:19:35.279018 DramcWriteLeveling(PI) end<-----
7992 23:19:35.279572
7993 23:19:35.279932 ==
7994 23:19:35.282391 Dram Type= 6, Freq= 0, CH_0, rank 1
7995 23:19:35.286234 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7996 23:19:35.286796 ==
7997 23:19:35.289101 [Gating] SW mode calibration
7998 23:19:35.295888 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7999 23:19:35.303225 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8000 23:19:35.306117 1 4 0 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
8001 23:19:35.309418 1 4 4 | B1->B0 | 2323 2524 | 0 1 | (0 0) (0 0)
8002 23:19:35.315647 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8003 23:19:35.319508 1 4 12 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
8004 23:19:35.322069 1 4 16 | B1->B0 | 3030 3a39 | 1 1 | (1 1) (0 0)
8005 23:19:35.329008 1 4 20 | B1->B0 | 3434 3636 | 1 0 | (1 1) (0 0)
8006 23:19:35.332625 1 4 24 | B1->B0 | 3434 3837 | 1 1 | (1 1) (1 1)
8007 23:19:35.335970 1 4 28 | B1->B0 | 3434 3939 | 1 0 | (1 1) (0 0)
8008 23:19:35.342154 1 5 0 | B1->B0 | 3434 3636 | 1 0 | (1 1) (0 0)
8009 23:19:35.345365 1 5 4 | B1->B0 | 3434 3838 | 1 0 | (1 1) (1 1)
8010 23:19:35.349301 1 5 8 | B1->B0 | 3434 3636 | 1 1 | (1 1) (1 1)
8011 23:19:35.355601 1 5 12 | B1->B0 | 3434 3535 | 1 0 | (1 0) (0 1)
8012 23:19:35.358641 1 5 16 | B1->B0 | 3030 3030 | 0 0 | (0 1) (1 0)
8013 23:19:35.361938 1 5 20 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
8014 23:19:35.368967 1 5 24 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (1 1)
8015 23:19:35.371629 1 5 28 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (0 0)
8016 23:19:35.374914 1 6 0 | B1->B0 | 2323 2524 | 0 1 | (0 0) (0 0)
8017 23:19:35.382152 1 6 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
8018 23:19:35.385672 1 6 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8019 23:19:35.388656 1 6 12 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
8020 23:19:35.394944 1 6 16 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
8021 23:19:35.398426 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8022 23:19:35.401410 1 6 24 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
8023 23:19:35.408286 1 6 28 | B1->B0 | 4646 4645 | 0 1 | (0 0) (1 1)
8024 23:19:35.411555 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8025 23:19:35.414793 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8026 23:19:35.421433 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8027 23:19:35.424799 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8028 23:19:35.428188 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8029 23:19:35.435031 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8030 23:19:35.438429 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8031 23:19:35.441946 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8032 23:19:35.448144 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8033 23:19:35.451461 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8034 23:19:35.454639 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8035 23:19:35.461308 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8036 23:19:35.464245 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8037 23:19:35.467896 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8038 23:19:35.474238 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8039 23:19:35.477860 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8040 23:19:35.481224 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8041 23:19:35.487609 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8042 23:19:35.490834 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8043 23:19:35.494422 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8044 23:19:35.501228 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8045 23:19:35.504411 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8046 23:19:35.507776 Total UI for P1: 0, mck2ui 16
8047 23:19:35.510808 best dqsien dly found for B0: ( 1, 9, 14)
8048 23:19:35.514636 Total UI for P1: 0, mck2ui 16
8049 23:19:35.517461 best dqsien dly found for B1: ( 1, 9, 14)
8050 23:19:35.521237 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8051 23:19:35.524121 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8052 23:19:35.524752
8053 23:19:35.527866 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8054 23:19:35.530546 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8055 23:19:35.534130 [Gating] SW calibration Done
8056 23:19:35.534595 ==
8057 23:19:35.537462 Dram Type= 6, Freq= 0, CH_0, rank 1
8058 23:19:35.541023 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8059 23:19:35.541624 ==
8060 23:19:35.544263 RX Vref Scan: 0
8061 23:19:35.544730
8062 23:19:35.547372 RX Vref 0 -> 0, step: 1
8063 23:19:35.547927
8064 23:19:35.548298 RX Delay 0 -> 252, step: 8
8065 23:19:35.553796 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8066 23:19:35.557361 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8067 23:19:35.560480 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8068 23:19:35.563937 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8069 23:19:35.567706 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8070 23:19:35.573556 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8071 23:19:35.577169 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8072 23:19:35.580547 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8073 23:19:35.584063 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8074 23:19:35.587231 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8075 23:19:35.593880 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8076 23:19:35.597725 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8077 23:19:35.601148 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8078 23:19:35.603909 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8079 23:19:35.607053 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8080 23:19:35.614023 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8081 23:19:35.614580 ==
8082 23:19:35.616934 Dram Type= 6, Freq= 0, CH_0, rank 1
8083 23:19:35.620555 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8084 23:19:35.621118 ==
8085 23:19:35.621495 DQS Delay:
8086 23:19:35.624020 DQS0 = 0, DQS1 = 0
8087 23:19:35.624582 DQM Delay:
8088 23:19:35.627273 DQM0 = 137, DQM1 = 128
8089 23:19:35.627816 DQ Delay:
8090 23:19:35.630478 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
8091 23:19:35.633919 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8092 23:19:35.637534 DQ8 =119, DQ9 =119, DQ10 =127, DQ11 =119
8093 23:19:35.640130 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8094 23:19:35.643657
8095 23:19:35.644112
8096 23:19:35.644479 ==
8097 23:19:35.647375 Dram Type= 6, Freq= 0, CH_0, rank 1
8098 23:19:35.650495 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8099 23:19:35.650959 ==
8100 23:19:35.651321
8101 23:19:35.651654
8102 23:19:35.654026 TX Vref Scan disable
8103 23:19:35.654633 == TX Byte 0 ==
8104 23:19:35.660719 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
8105 23:19:35.664003 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8106 23:19:35.664464 == TX Byte 1 ==
8107 23:19:35.671001 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8108 23:19:35.674351 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8109 23:19:35.674930 ==
8110 23:19:35.677035 Dram Type= 6, Freq= 0, CH_0, rank 1
8111 23:19:35.680682 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8112 23:19:35.681247 ==
8113 23:19:35.695173
8114 23:19:35.698275 TX Vref early break, caculate TX vref
8115 23:19:35.701806 TX Vref=16, minBit 0, minWin=23, winSum=383
8116 23:19:35.705008 TX Vref=18, minBit 1, minWin=23, winSum=399
8117 23:19:35.708175 TX Vref=20, minBit 1, minWin=24, winSum=406
8118 23:19:35.711834 TX Vref=22, minBit 1, minWin=24, winSum=412
8119 23:19:35.715021 TX Vref=24, minBit 0, minWin=25, winSum=421
8120 23:19:35.721487 TX Vref=26, minBit 1, minWin=24, winSum=425
8121 23:19:35.725344 TX Vref=28, minBit 0, minWin=25, winSum=424
8122 23:19:35.728864 TX Vref=30, minBit 0, minWin=25, winSum=416
8123 23:19:35.731387 TX Vref=32, minBit 4, minWin=24, winSum=409
8124 23:19:35.735020 TX Vref=34, minBit 0, minWin=24, winSum=398
8125 23:19:35.741177 [TxChooseVref] Worse bit 0, Min win 25, Win sum 424, Final Vref 28
8126 23:19:35.741774
8127 23:19:35.744660 Final TX Range 0 Vref 28
8128 23:19:35.745117
8129 23:19:35.745477 ==
8130 23:19:35.747659 Dram Type= 6, Freq= 0, CH_0, rank 1
8131 23:19:35.751227 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8132 23:19:35.751692 ==
8133 23:19:35.752059
8134 23:19:35.752394
8135 23:19:35.754510 TX Vref Scan disable
8136 23:19:35.761140 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8137 23:19:35.761724 == TX Byte 0 ==
8138 23:19:35.764501 u2DelayCellOfst[0]=10 cells (3 PI)
8139 23:19:35.767786 u2DelayCellOfst[1]=16 cells (5 PI)
8140 23:19:35.771044 u2DelayCellOfst[2]=10 cells (3 PI)
8141 23:19:35.774320 u2DelayCellOfst[3]=6 cells (2 PI)
8142 23:19:35.778036 u2DelayCellOfst[4]=10 cells (3 PI)
8143 23:19:35.780887 u2DelayCellOfst[5]=0 cells (0 PI)
8144 23:19:35.784341 u2DelayCellOfst[6]=16 cells (5 PI)
8145 23:19:35.787805 u2DelayCellOfst[7]=13 cells (4 PI)
8146 23:19:35.791302 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8147 23:19:35.794188 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8148 23:19:35.797882 == TX Byte 1 ==
8149 23:19:35.798442 u2DelayCellOfst[8]=3 cells (1 PI)
8150 23:19:35.801171 u2DelayCellOfst[9]=0 cells (0 PI)
8151 23:19:35.804949 u2DelayCellOfst[10]=6 cells (2 PI)
8152 23:19:35.807738 u2DelayCellOfst[11]=3 cells (1 PI)
8153 23:19:35.811093 u2DelayCellOfst[12]=10 cells (3 PI)
8154 23:19:35.814180 u2DelayCellOfst[13]=10 cells (3 PI)
8155 23:19:35.817441 u2DelayCellOfst[14]=13 cells (4 PI)
8156 23:19:35.821164 u2DelayCellOfst[15]=10 cells (3 PI)
8157 23:19:35.824418 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8158 23:19:35.831036 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8159 23:19:35.831731 DramC Write-DBI on
8160 23:19:35.832108 ==
8161 23:19:35.834402 Dram Type= 6, Freq= 0, CH_0, rank 1
8162 23:19:35.837903 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8163 23:19:35.840551 ==
8164 23:19:35.841108
8165 23:19:35.841473
8166 23:19:35.841855 TX Vref Scan disable
8167 23:19:35.844451 == TX Byte 0 ==
8168 23:19:35.847332 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
8169 23:19:35.851208 == TX Byte 1 ==
8170 23:19:35.854024 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8171 23:19:35.857599 DramC Write-DBI off
8172 23:19:35.858163
8173 23:19:35.858529 [DATLAT]
8174 23:19:35.858862 Freq=1600, CH0 RK1
8175 23:19:35.859184
8176 23:19:35.860796 DATLAT Default: 0xf
8177 23:19:35.861252 0, 0xFFFF, sum = 0
8178 23:19:35.863939 1, 0xFFFF, sum = 0
8179 23:19:35.867226 2, 0xFFFF, sum = 0
8180 23:19:35.867690 3, 0xFFFF, sum = 0
8181 23:19:35.870799 4, 0xFFFF, sum = 0
8182 23:19:35.871264 5, 0xFFFF, sum = 0
8183 23:19:35.874008 6, 0xFFFF, sum = 0
8184 23:19:35.874471 7, 0xFFFF, sum = 0
8185 23:19:35.877317 8, 0xFFFF, sum = 0
8186 23:19:35.877888 9, 0xFFFF, sum = 0
8187 23:19:35.880867 10, 0xFFFF, sum = 0
8188 23:19:35.881331 11, 0xFFFF, sum = 0
8189 23:19:35.884322 12, 0xFFFF, sum = 0
8190 23:19:35.884883 13, 0xFFFF, sum = 0
8191 23:19:35.887528 14, 0x0, sum = 1
8192 23:19:35.888112 15, 0x0, sum = 2
8193 23:19:35.890730 16, 0x0, sum = 3
8194 23:19:35.891290 17, 0x0, sum = 4
8195 23:19:35.894123 best_step = 15
8196 23:19:35.894580
8197 23:19:35.894941 ==
8198 23:19:35.897066 Dram Type= 6, Freq= 0, CH_0, rank 1
8199 23:19:35.900944 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8200 23:19:35.901503 ==
8201 23:19:35.904182 RX Vref Scan: 0
8202 23:19:35.904736
8203 23:19:35.905102 RX Vref 0 -> 0, step: 1
8204 23:19:35.905438
8205 23:19:35.907582 RX Delay 19 -> 252, step: 4
8206 23:19:35.910204 iDelay=191, Bit 0, Center 134 (83 ~ 186) 104
8207 23:19:35.917310 iDelay=191, Bit 1, Center 138 (91 ~ 186) 96
8208 23:19:35.920300 iDelay=191, Bit 2, Center 132 (83 ~ 182) 100
8209 23:19:35.924088 iDelay=191, Bit 3, Center 134 (83 ~ 186) 104
8210 23:19:35.927423 iDelay=191, Bit 4, Center 136 (87 ~ 186) 100
8211 23:19:35.930649 iDelay=191, Bit 5, Center 126 (71 ~ 182) 112
8212 23:19:35.937255 iDelay=191, Bit 6, Center 138 (87 ~ 190) 104
8213 23:19:35.940608 iDelay=191, Bit 7, Center 140 (91 ~ 190) 100
8214 23:19:35.943833 iDelay=191, Bit 8, Center 118 (67 ~ 170) 104
8215 23:19:35.947387 iDelay=191, Bit 9, Center 116 (67 ~ 166) 100
8216 23:19:35.950349 iDelay=191, Bit 10, Center 128 (75 ~ 182) 108
8217 23:19:35.957006 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8218 23:19:35.960531 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
8219 23:19:35.963635 iDelay=191, Bit 13, Center 134 (83 ~ 186) 104
8220 23:19:35.967380 iDelay=191, Bit 14, Center 134 (83 ~ 186) 104
8221 23:19:35.970326 iDelay=191, Bit 15, Center 134 (87 ~ 182) 96
8222 23:19:35.973692 ==
8223 23:19:35.976954 Dram Type= 6, Freq= 0, CH_0, rank 1
8224 23:19:35.980510 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8225 23:19:35.981068 ==
8226 23:19:35.981437 DQS Delay:
8227 23:19:35.984054 DQS0 = 0, DQS1 = 0
8228 23:19:35.984609 DQM Delay:
8229 23:19:35.987149 DQM0 = 134, DQM1 = 127
8230 23:19:35.987704 DQ Delay:
8231 23:19:35.990325 DQ0 =134, DQ1 =138, DQ2 =132, DQ3 =134
8232 23:19:35.993536 DQ4 =136, DQ5 =126, DQ6 =138, DQ7 =140
8233 23:19:35.996731 DQ8 =118, DQ9 =116, DQ10 =128, DQ11 =118
8234 23:19:36.000348 DQ12 =134, DQ13 =134, DQ14 =134, DQ15 =134
8235 23:19:36.000903
8236 23:19:36.001265
8237 23:19:36.001652
8238 23:19:36.003642 [DramC_TX_OE_Calibration] TA2
8239 23:19:36.007361 Original DQ_B0 (3 6) =30, OEN = 27
8240 23:19:36.010174 Original DQ_B1 (3 6) =30, OEN = 27
8241 23:19:36.013872 24, 0x0, End_B0=24 End_B1=24
8242 23:19:36.016901 25, 0x0, End_B0=25 End_B1=25
8243 23:19:36.017482 26, 0x0, End_B0=26 End_B1=26
8244 23:19:36.020457 27, 0x0, End_B0=27 End_B1=27
8245 23:19:36.024082 28, 0x0, End_B0=28 End_B1=28
8246 23:19:36.026784 29, 0x0, End_B0=29 End_B1=29
8247 23:19:36.030148 30, 0x0, End_B0=30 End_B1=30
8248 23:19:36.030715 31, 0x4141, End_B0=30 End_B1=30
8249 23:19:36.033616 Byte0 end_step=30 best_step=27
8250 23:19:36.036600 Byte1 end_step=30 best_step=27
8251 23:19:36.040083 Byte0 TX OE(2T, 0.5T) = (3, 3)
8252 23:19:36.043585 Byte1 TX OE(2T, 0.5T) = (3, 3)
8253 23:19:36.044071
8254 23:19:36.044441
8255 23:19:36.049875 [DQSOSCAuto] RK1, (LSB)MR18= 0x2109, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 393 ps
8256 23:19:36.053566 CH0 RK1: MR19=303, MR18=2109
8257 23:19:36.059963 CH0_RK1: MR19=0x303, MR18=0x2109, DQSOSC=393, MR23=63, INC=23, DEC=15
8258 23:19:36.063181 [RxdqsGatingPostProcess] freq 1600
8259 23:19:36.069463 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8260 23:19:36.069968 best DQS0 dly(2T, 0.5T) = (1, 1)
8261 23:19:36.073438 best DQS1 dly(2T, 0.5T) = (1, 1)
8262 23:19:36.076709 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8263 23:19:36.080181 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8264 23:19:36.082819 best DQS0 dly(2T, 0.5T) = (1, 1)
8265 23:19:36.086113 best DQS1 dly(2T, 0.5T) = (1, 1)
8266 23:19:36.089414 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8267 23:19:36.093036 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8268 23:19:36.096330 Pre-setting of DQS Precalculation
8269 23:19:36.099412 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8270 23:19:36.103243 ==
8271 23:19:36.103803 Dram Type= 6, Freq= 0, CH_1, rank 0
8272 23:19:36.110162 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8273 23:19:36.110736 ==
8274 23:19:36.112796 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8275 23:19:36.119323 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8276 23:19:36.123100 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8277 23:19:36.129514 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8278 23:19:36.137128 [CA 0] Center 42 (13~72) winsize 60
8279 23:19:36.140776 [CA 1] Center 42 (12~72) winsize 61
8280 23:19:36.143605 [CA 2] Center 39 (10~69) winsize 60
8281 23:19:36.147288 [CA 3] Center 38 (9~67) winsize 59
8282 23:19:36.150847 [CA 4] Center 39 (10~68) winsize 59
8283 23:19:36.153712 [CA 5] Center 37 (8~67) winsize 60
8284 23:19:36.154182
8285 23:19:36.157516 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8286 23:19:36.158157
8287 23:19:36.163962 [CATrainingPosCal] consider 1 rank data
8288 23:19:36.164523 u2DelayCellTimex100 = 290/100 ps
8289 23:19:36.170786 CA0 delay=42 (13~72),Diff = 5 PI (16 cell)
8290 23:19:36.173558 CA1 delay=42 (12~72),Diff = 5 PI (16 cell)
8291 23:19:36.177173 CA2 delay=39 (10~69),Diff = 2 PI (6 cell)
8292 23:19:36.180182 CA3 delay=38 (9~67),Diff = 1 PI (3 cell)
8293 23:19:36.183781 CA4 delay=39 (10~68),Diff = 2 PI (6 cell)
8294 23:19:36.187379 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8295 23:19:36.187936
8296 23:19:36.190182 CA PerBit enable=1, Macro0, CA PI delay=37
8297 23:19:36.190640
8298 23:19:36.193956 [CBTSetCACLKResult] CA Dly = 37
8299 23:19:36.196946 CS Dly: 10 (0~41)
8300 23:19:36.200650 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8301 23:19:36.203987 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8302 23:19:36.204547 ==
8303 23:19:36.207469 Dram Type= 6, Freq= 0, CH_1, rank 1
8304 23:19:36.213686 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8305 23:19:36.214250 ==
8306 23:19:36.216750 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8307 23:19:36.220092 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8308 23:19:36.227202 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8309 23:19:36.233223 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8310 23:19:36.240706 [CA 0] Center 42 (12~72) winsize 61
8311 23:19:36.243837 [CA 1] Center 41 (12~71) winsize 60
8312 23:19:36.247380 [CA 2] Center 38 (9~68) winsize 60
8313 23:19:36.250929 [CA 3] Center 38 (9~67) winsize 59
8314 23:19:36.254271 [CA 4] Center 38 (9~68) winsize 60
8315 23:19:36.257557 [CA 5] Center 37 (8~67) winsize 60
8316 23:19:36.258171
8317 23:19:36.260495 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8318 23:19:36.261049
8319 23:19:36.264007 [CATrainingPosCal] consider 2 rank data
8320 23:19:36.267201 u2DelayCellTimex100 = 290/100 ps
8321 23:19:36.270918 CA0 delay=42 (13~72),Diff = 5 PI (16 cell)
8322 23:19:36.277259 CA1 delay=41 (12~71),Diff = 4 PI (13 cell)
8323 23:19:36.280761 CA2 delay=39 (10~68),Diff = 2 PI (6 cell)
8324 23:19:36.284363 CA3 delay=38 (9~67),Diff = 1 PI (3 cell)
8325 23:19:36.287639 CA4 delay=39 (10~68),Diff = 2 PI (6 cell)
8326 23:19:36.291038 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8327 23:19:36.291593
8328 23:19:36.293648 CA PerBit enable=1, Macro0, CA PI delay=37
8329 23:19:36.294121
8330 23:19:36.297075 [CBTSetCACLKResult] CA Dly = 37
8331 23:19:36.300590 CS Dly: 12 (0~45)
8332 23:19:36.303888 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8333 23:19:36.307258 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8334 23:19:36.307721
8335 23:19:36.310399 ----->DramcWriteLeveling(PI) begin...
8336 23:19:36.310869 ==
8337 23:19:36.313455 Dram Type= 6, Freq= 0, CH_1, rank 0
8338 23:19:36.320468 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8339 23:19:36.321001 ==
8340 23:19:36.323700 Write leveling (Byte 0): 25 => 25
8341 23:19:36.324216 Write leveling (Byte 1): 29 => 29
8342 23:19:36.327142 DramcWriteLeveling(PI) end<-----
8343 23:19:36.327802
8344 23:19:36.330319 ==
8345 23:19:36.330739 Dram Type= 6, Freq= 0, CH_1, rank 0
8346 23:19:36.336632 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8347 23:19:36.337153 ==
8348 23:19:36.340396 [Gating] SW mode calibration
8349 23:19:36.346467 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8350 23:19:36.350425 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8351 23:19:36.356887 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8352 23:19:36.360335 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8353 23:19:36.363470 1 4 8 | B1->B0 | 2323 2524 | 0 1 | (0 0) (0 0)
8354 23:19:36.370056 1 4 12 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
8355 23:19:36.373318 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8356 23:19:36.376720 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8357 23:19:36.383096 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8358 23:19:36.386198 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8359 23:19:36.389711 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8360 23:19:36.396540 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8361 23:19:36.399688 1 5 8 | B1->B0 | 3434 2f2f | 1 1 | (1 0) (1 0)
8362 23:19:36.403175 1 5 12 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
8363 23:19:36.409552 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8364 23:19:36.413080 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8365 23:19:36.416375 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8366 23:19:36.423288 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8367 23:19:36.426210 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8368 23:19:36.429511 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8369 23:19:36.436569 1 6 8 | B1->B0 | 2424 3535 | 0 0 | (0 0) (0 0)
8370 23:19:36.439229 1 6 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8371 23:19:36.442552 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8372 23:19:36.449128 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8373 23:19:36.452452 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8374 23:19:36.455816 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8375 23:19:36.462599 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8376 23:19:36.465932 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8377 23:19:36.469006 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8378 23:19:36.475481 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8379 23:19:36.479149 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8380 23:19:36.482269 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8381 23:19:36.489001 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8382 23:19:36.492509 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8383 23:19:36.496150 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8384 23:19:36.499231 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8385 23:19:36.506053 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8386 23:19:36.508887 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8387 23:19:36.512628 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8388 23:19:36.519172 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8389 23:19:36.522361 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8390 23:19:36.525685 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8391 23:19:36.532508 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8392 23:19:36.535961 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8393 23:19:36.539162 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8394 23:19:36.545965 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8395 23:19:36.549207 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8396 23:19:36.552184 Total UI for P1: 0, mck2ui 16
8397 23:19:36.555615 best dqsien dly found for B0: ( 1, 9, 10)
8398 23:19:36.559381 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8399 23:19:36.562158 Total UI for P1: 0, mck2ui 16
8400 23:19:36.565797 best dqsien dly found for B1: ( 1, 9, 12)
8401 23:19:36.568725 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8402 23:19:36.572359 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8403 23:19:36.572919
8404 23:19:36.578795 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8405 23:19:36.582349 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8406 23:19:36.585245 [Gating] SW calibration Done
8407 23:19:36.585851 ==
8408 23:19:36.588461 Dram Type= 6, Freq= 0, CH_1, rank 0
8409 23:19:36.592258 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8410 23:19:36.592845 ==
8411 23:19:36.593222 RX Vref Scan: 0
8412 23:19:36.593565
8413 23:19:36.595438 RX Vref 0 -> 0, step: 1
8414 23:19:36.596032
8415 23:19:36.598514 RX Delay 0 -> 252, step: 8
8416 23:19:36.602542 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8417 23:19:36.605344 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8418 23:19:36.609282 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8419 23:19:36.615771 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8420 23:19:36.618700 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8421 23:19:36.621692 iDelay=200, Bit 5, Center 151 (104 ~ 199) 96
8422 23:19:36.625018 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8423 23:19:36.629063 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8424 23:19:36.635315 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
8425 23:19:36.638840 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8426 23:19:36.642609 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8427 23:19:36.645164 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8428 23:19:36.649173 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8429 23:19:36.654878 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8430 23:19:36.658652 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8431 23:19:36.662596 iDelay=200, Bit 15, Center 143 (96 ~ 191) 96
8432 23:19:36.663160 ==
8433 23:19:36.664811 Dram Type= 6, Freq= 0, CH_1, rank 0
8434 23:19:36.668137 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8435 23:19:36.668609 ==
8436 23:19:36.671866 DQS Delay:
8437 23:19:36.672419 DQS0 = 0, DQS1 = 0
8438 23:19:36.674916 DQM Delay:
8439 23:19:36.675380 DQM0 = 137, DQM1 = 133
8440 23:19:36.678585 DQ Delay:
8441 23:19:36.681542 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8442 23:19:36.685452 DQ4 =131, DQ5 =151, DQ6 =147, DQ7 =135
8443 23:19:36.688808 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =127
8444 23:19:36.691803 DQ12 =139, DQ13 =143, DQ14 =139, DQ15 =143
8445 23:19:36.692359
8446 23:19:36.692727
8447 23:19:36.693066 ==
8448 23:19:36.695446 Dram Type= 6, Freq= 0, CH_1, rank 0
8449 23:19:36.698138 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8450 23:19:36.698610 ==
8451 23:19:36.698977
8452 23:19:36.699318
8453 23:19:36.702312 TX Vref Scan disable
8454 23:19:36.705439 == TX Byte 0 ==
8455 23:19:36.707934 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8456 23:19:36.711654 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8457 23:19:36.715194 == TX Byte 1 ==
8458 23:19:36.718119 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8459 23:19:36.721573 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8460 23:19:36.722079 ==
8461 23:19:36.725135 Dram Type= 6, Freq= 0, CH_1, rank 0
8462 23:19:36.731571 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8463 23:19:36.732132 ==
8464 23:19:36.744503
8465 23:19:36.747066 TX Vref early break, caculate TX vref
8466 23:19:36.750865 TX Vref=16, minBit 11, minWin=22, winSum=376
8467 23:19:36.754280 TX Vref=18, minBit 1, minWin=23, winSum=383
8468 23:19:36.757279 TX Vref=20, minBit 0, minWin=23, winSum=395
8469 23:19:36.760667 TX Vref=22, minBit 9, minWin=24, winSum=405
8470 23:19:36.763697 TX Vref=24, minBit 0, minWin=25, winSum=416
8471 23:19:36.770945 TX Vref=26, minBit 0, minWin=25, winSum=419
8472 23:19:36.773860 TX Vref=28, minBit 0, minWin=26, winSum=427
8473 23:19:36.777263 TX Vref=30, minBit 0, minWin=24, winSum=418
8474 23:19:36.780505 TX Vref=32, minBit 0, minWin=24, winSum=414
8475 23:19:36.784082 TX Vref=34, minBit 0, minWin=24, winSum=406
8476 23:19:36.787171 TX Vref=36, minBit 6, minWin=23, winSum=390
8477 23:19:36.794231 [TxChooseVref] Worse bit 0, Min win 26, Win sum 427, Final Vref 28
8478 23:19:36.794790
8479 23:19:36.797052 Final TX Range 0 Vref 28
8480 23:19:36.797661
8481 23:19:36.798056 ==
8482 23:19:36.800161 Dram Type= 6, Freq= 0, CH_1, rank 0
8483 23:19:36.804054 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8484 23:19:36.804629 ==
8485 23:19:36.805004
8486 23:19:36.807318
8487 23:19:36.807876 TX Vref Scan disable
8488 23:19:36.813789 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8489 23:19:36.814347 == TX Byte 0 ==
8490 23:19:36.817337 u2DelayCellOfst[0]=20 cells (6 PI)
8491 23:19:36.820439 u2DelayCellOfst[1]=13 cells (4 PI)
8492 23:19:36.823758 u2DelayCellOfst[2]=0 cells (0 PI)
8493 23:19:36.827125 u2DelayCellOfst[3]=10 cells (3 PI)
8494 23:19:36.829908 u2DelayCellOfst[4]=13 cells (4 PI)
8495 23:19:36.833332 u2DelayCellOfst[5]=20 cells (6 PI)
8496 23:19:36.836586 u2DelayCellOfst[6]=20 cells (6 PI)
8497 23:19:36.840386 u2DelayCellOfst[7]=10 cells (3 PI)
8498 23:19:36.843282 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8499 23:19:36.846753 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8500 23:19:36.850304 == TX Byte 1 ==
8501 23:19:36.853543 u2DelayCellOfst[8]=0 cells (0 PI)
8502 23:19:36.857045 u2DelayCellOfst[9]=3 cells (1 PI)
8503 23:19:36.860349 u2DelayCellOfst[10]=13 cells (4 PI)
8504 23:19:36.860908 u2DelayCellOfst[11]=6 cells (2 PI)
8505 23:19:36.863776 u2DelayCellOfst[12]=16 cells (5 PI)
8506 23:19:36.867335 u2DelayCellOfst[13]=16 cells (5 PI)
8507 23:19:36.869958 u2DelayCellOfst[14]=20 cells (6 PI)
8508 23:19:36.873346 u2DelayCellOfst[15]=16 cells (5 PI)
8509 23:19:36.880139 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8510 23:19:36.883456 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8511 23:19:36.883951 DramC Write-DBI on
8512 23:19:36.884316 ==
8513 23:19:36.886236 Dram Type= 6, Freq= 0, CH_1, rank 0
8514 23:19:36.893649 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8515 23:19:36.894258 ==
8516 23:19:36.894631
8517 23:19:36.894968
8518 23:19:36.895290 TX Vref Scan disable
8519 23:19:36.897715 == TX Byte 0 ==
8520 23:19:36.901396 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8521 23:19:36.904048 == TX Byte 1 ==
8522 23:19:36.907813 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8523 23:19:36.910612 DramC Write-DBI off
8524 23:19:36.911068
8525 23:19:36.911430 [DATLAT]
8526 23:19:36.911765 Freq=1600, CH1 RK0
8527 23:19:36.912090
8528 23:19:36.913754 DATLAT Default: 0xf
8529 23:19:36.914213 0, 0xFFFF, sum = 0
8530 23:19:36.917781 1, 0xFFFF, sum = 0
8531 23:19:36.920834 2, 0xFFFF, sum = 0
8532 23:19:36.921300 3, 0xFFFF, sum = 0
8533 23:19:36.924741 4, 0xFFFF, sum = 0
8534 23:19:36.925304 5, 0xFFFF, sum = 0
8535 23:19:36.927414 6, 0xFFFF, sum = 0
8536 23:19:36.927977 7, 0xFFFF, sum = 0
8537 23:19:36.930932 8, 0xFFFF, sum = 0
8538 23:19:36.931497 9, 0xFFFF, sum = 0
8539 23:19:36.934274 10, 0xFFFF, sum = 0
8540 23:19:36.934739 11, 0xFFFF, sum = 0
8541 23:19:36.937828 12, 0xFFFF, sum = 0
8542 23:19:36.938476 13, 0xFFFF, sum = 0
8543 23:19:36.940935 14, 0x0, sum = 1
8544 23:19:36.941398 15, 0x0, sum = 2
8545 23:19:36.944332 16, 0x0, sum = 3
8546 23:19:36.944896 17, 0x0, sum = 4
8547 23:19:36.947243 best_step = 15
8548 23:19:36.947705
8549 23:19:36.948078 ==
8550 23:19:36.950939 Dram Type= 6, Freq= 0, CH_1, rank 0
8551 23:19:36.953968 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8552 23:19:36.954445 ==
8553 23:19:36.954817 RX Vref Scan: 1
8554 23:19:36.957495
8555 23:19:36.958113 Set Vref Range= 24 -> 127
8556 23:19:36.958490
8557 23:19:36.960737 RX Vref 24 -> 127, step: 1
8558 23:19:36.961201
8559 23:19:36.963847 RX Delay 27 -> 252, step: 4
8560 23:19:36.964312
8561 23:19:36.967020 Set Vref, RX VrefLevel [Byte0]: 24
8562 23:19:36.971200 [Byte1]: 24
8563 23:19:36.971758
8564 23:19:36.973885 Set Vref, RX VrefLevel [Byte0]: 25
8565 23:19:36.977489 [Byte1]: 25
8566 23:19:36.977999
8567 23:19:36.980472 Set Vref, RX VrefLevel [Byte0]: 26
8568 23:19:36.983755 [Byte1]: 26
8569 23:19:36.987990
8570 23:19:36.988550 Set Vref, RX VrefLevel [Byte0]: 27
8571 23:19:36.990630 [Byte1]: 27
8572 23:19:36.994956
8573 23:19:36.995407 Set Vref, RX VrefLevel [Byte0]: 28
8574 23:19:36.998295 [Byte1]: 28
8575 23:19:37.002445
8576 23:19:37.002862 Set Vref, RX VrefLevel [Byte0]: 29
8577 23:19:37.005819 [Byte1]: 29
8578 23:19:37.010199
8579 23:19:37.010791 Set Vref, RX VrefLevel [Byte0]: 30
8580 23:19:37.013570 [Byte1]: 30
8581 23:19:37.017746
8582 23:19:37.018259 Set Vref, RX VrefLevel [Byte0]: 31
8583 23:19:37.020860 [Byte1]: 31
8584 23:19:37.025381
8585 23:19:37.025952 Set Vref, RX VrefLevel [Byte0]: 32
8586 23:19:37.028586 [Byte1]: 32
8587 23:19:37.033148
8588 23:19:37.033898 Set Vref, RX VrefLevel [Byte0]: 33
8589 23:19:37.036205 [Byte1]: 33
8590 23:19:37.040600
8591 23:19:37.041117 Set Vref, RX VrefLevel [Byte0]: 34
8592 23:19:37.044024 [Byte1]: 34
8593 23:19:37.047893
8594 23:19:37.048304 Set Vref, RX VrefLevel [Byte0]: 35
8595 23:19:37.051260 [Byte1]: 35
8596 23:19:37.055668
8597 23:19:37.056180 Set Vref, RX VrefLevel [Byte0]: 36
8598 23:19:37.061694 [Byte1]: 36
8599 23:19:37.062207
8600 23:19:37.065505 Set Vref, RX VrefLevel [Byte0]: 37
8601 23:19:37.068520 [Byte1]: 37
8602 23:19:37.069064
8603 23:19:37.072054 Set Vref, RX VrefLevel [Byte0]: 38
8604 23:19:37.075103 [Byte1]: 38
8605 23:19:37.075565
8606 23:19:37.078959 Set Vref, RX VrefLevel [Byte0]: 39
8607 23:19:37.081918 [Byte1]: 39
8608 23:19:37.085444
8609 23:19:37.085938 Set Vref, RX VrefLevel [Byte0]: 40
8610 23:19:37.088990 [Byte1]: 40
8611 23:19:37.093106
8612 23:19:37.093659 Set Vref, RX VrefLevel [Byte0]: 41
8613 23:19:37.096378 [Byte1]: 41
8614 23:19:37.101065
8615 23:19:37.101623 Set Vref, RX VrefLevel [Byte0]: 42
8616 23:19:37.103844 [Byte1]: 42
8617 23:19:37.108148
8618 23:19:37.108663 Set Vref, RX VrefLevel [Byte0]: 43
8619 23:19:37.111025 [Byte1]: 43
8620 23:19:37.115987
8621 23:19:37.116519 Set Vref, RX VrefLevel [Byte0]: 44
8622 23:19:37.119007 [Byte1]: 44
8623 23:19:37.123528
8624 23:19:37.124048 Set Vref, RX VrefLevel [Byte0]: 45
8625 23:19:37.126683 [Byte1]: 45
8626 23:19:37.131112
8627 23:19:37.131635 Set Vref, RX VrefLevel [Byte0]: 46
8628 23:19:37.134128 [Byte1]: 46
8629 23:19:37.138297
8630 23:19:37.138817 Set Vref, RX VrefLevel [Byte0]: 47
8631 23:19:37.141728 [Byte1]: 47
8632 23:19:37.146275
8633 23:19:37.146869 Set Vref, RX VrefLevel [Byte0]: 48
8634 23:19:37.149537 [Byte1]: 48
8635 23:19:37.153657
8636 23:19:37.154170 Set Vref, RX VrefLevel [Byte0]: 49
8637 23:19:37.156838 [Byte1]: 49
8638 23:19:37.161046
8639 23:19:37.161568 Set Vref, RX VrefLevel [Byte0]: 50
8640 23:19:37.164399 [Byte1]: 50
8641 23:19:37.168631
8642 23:19:37.169047 Set Vref, RX VrefLevel [Byte0]: 51
8643 23:19:37.172385 [Byte1]: 51
8644 23:19:37.175835
8645 23:19:37.176251 Set Vref, RX VrefLevel [Byte0]: 52
8646 23:19:37.179390 [Byte1]: 52
8647 23:19:37.183486
8648 23:19:37.183904 Set Vref, RX VrefLevel [Byte0]: 53
8649 23:19:37.187390 [Byte1]: 53
8650 23:19:37.191337
8651 23:19:37.191899 Set Vref, RX VrefLevel [Byte0]: 54
8652 23:19:37.194081 [Byte1]: 54
8653 23:19:37.198667
8654 23:19:37.199190 Set Vref, RX VrefLevel [Byte0]: 55
8655 23:19:37.201996 [Byte1]: 55
8656 23:19:37.206200
8657 23:19:37.206755 Set Vref, RX VrefLevel [Byte0]: 56
8658 23:19:37.209666 [Byte1]: 56
8659 23:19:37.213726
8660 23:19:37.214290 Set Vref, RX VrefLevel [Byte0]: 57
8661 23:19:37.216911 [Byte1]: 57
8662 23:19:37.221032
8663 23:19:37.221685 Set Vref, RX VrefLevel [Byte0]: 58
8664 23:19:37.224519 [Byte1]: 58
8665 23:19:37.228887
8666 23:19:37.229432 Set Vref, RX VrefLevel [Byte0]: 59
8667 23:19:37.232044 [Byte1]: 59
8668 23:19:37.236491
8669 23:19:37.237062 Set Vref, RX VrefLevel [Byte0]: 60
8670 23:19:37.239225 [Byte1]: 60
8671 23:19:37.243733
8672 23:19:37.244361 Set Vref, RX VrefLevel [Byte0]: 61
8673 23:19:37.246817 [Byte1]: 61
8674 23:19:37.251437
8675 23:19:37.251990 Set Vref, RX VrefLevel [Byte0]: 62
8676 23:19:37.254460 [Byte1]: 62
8677 23:19:37.258644
8678 23:19:37.259172 Set Vref, RX VrefLevel [Byte0]: 63
8679 23:19:37.262427 [Byte1]: 63
8680 23:19:37.266447
8681 23:19:37.267000 Set Vref, RX VrefLevel [Byte0]: 64
8682 23:19:37.269754 [Byte1]: 64
8683 23:19:37.274247
8684 23:19:37.274851 Set Vref, RX VrefLevel [Byte0]: 65
8685 23:19:37.277237 [Byte1]: 65
8686 23:19:37.281442
8687 23:19:37.282076 Set Vref, RX VrefLevel [Byte0]: 66
8688 23:19:37.285040 [Byte1]: 66
8689 23:19:37.289087
8690 23:19:37.289680 Set Vref, RX VrefLevel [Byte0]: 67
8691 23:19:37.292189 [Byte1]: 67
8692 23:19:37.296974
8693 23:19:37.297529 Set Vref, RX VrefLevel [Byte0]: 68
8694 23:19:37.300270 [Byte1]: 68
8695 23:19:37.304465
8696 23:19:37.305014 Set Vref, RX VrefLevel [Byte0]: 69
8697 23:19:37.307601 [Byte1]: 69
8698 23:19:37.311406
8699 23:19:37.311959 Set Vref, RX VrefLevel [Byte0]: 70
8700 23:19:37.314798 [Byte1]: 70
8701 23:19:37.319250
8702 23:19:37.319807 Set Vref, RX VrefLevel [Byte0]: 71
8703 23:19:37.322291 [Byte1]: 71
8704 23:19:37.326800
8705 23:19:37.327375 Set Vref, RX VrefLevel [Byte0]: 72
8706 23:19:37.330099 [Byte1]: 72
8707 23:19:37.333925
8708 23:19:37.334493 Set Vref, RX VrefLevel [Byte0]: 73
8709 23:19:37.337630 [Byte1]: 73
8710 23:19:37.341684
8711 23:19:37.342236 Set Vref, RX VrefLevel [Byte0]: 74
8712 23:19:37.344968 [Byte1]: 74
8713 23:19:37.348931
8714 23:19:37.349470 Set Vref, RX VrefLevel [Byte0]: 75
8715 23:19:37.352412 [Byte1]: 75
8716 23:19:37.356749
8717 23:19:37.357350 Set Vref, RX VrefLevel [Byte0]: 76
8718 23:19:37.360077 [Byte1]: 76
8719 23:19:37.363933
8720 23:19:37.364392 Set Vref, RX VrefLevel [Byte0]: 77
8721 23:19:37.367571 [Byte1]: 77
8722 23:19:37.371568
8723 23:19:37.372024 Final RX Vref Byte 0 = 60 to rank0
8724 23:19:37.375246 Final RX Vref Byte 1 = 57 to rank0
8725 23:19:37.378326 Final RX Vref Byte 0 = 60 to rank1
8726 23:19:37.381800 Final RX Vref Byte 1 = 57 to rank1==
8727 23:19:37.385160 Dram Type= 6, Freq= 0, CH_1, rank 0
8728 23:19:37.391374 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8729 23:19:37.391791 ==
8730 23:19:37.392175 DQS Delay:
8731 23:19:37.392514 DQS0 = 0, DQS1 = 0
8732 23:19:37.395377 DQM Delay:
8733 23:19:37.395939 DQM0 = 134, DQM1 = 131
8734 23:19:37.398324 DQ Delay:
8735 23:19:37.401573 DQ0 =140, DQ1 =130, DQ2 =122, DQ3 =130
8736 23:19:37.404731 DQ4 =134, DQ5 =144, DQ6 =142, DQ7 =132
8737 23:19:37.408202 DQ8 =116, DQ9 =122, DQ10 =132, DQ11 =124
8738 23:19:37.411577 DQ12 =138, DQ13 =140, DQ14 =138, DQ15 =140
8739 23:19:37.411993
8740 23:19:37.412321
8741 23:19:37.412623
8742 23:19:37.415372 [DramC_TX_OE_Calibration] TA2
8743 23:19:37.417968 Original DQ_B0 (3 6) =30, OEN = 27
8744 23:19:37.421416 Original DQ_B1 (3 6) =30, OEN = 27
8745 23:19:37.424866 24, 0x0, End_B0=24 End_B1=24
8746 23:19:37.425282 25, 0x0, End_B0=25 End_B1=25
8747 23:19:37.427873 26, 0x0, End_B0=26 End_B1=26
8748 23:19:37.431674 27, 0x0, End_B0=27 End_B1=27
8749 23:19:37.434730 28, 0x0, End_B0=28 End_B1=28
8750 23:19:37.438079 29, 0x0, End_B0=29 End_B1=29
8751 23:19:37.438503 30, 0x0, End_B0=30 End_B1=30
8752 23:19:37.441706 31, 0x4141, End_B0=30 End_B1=30
8753 23:19:37.444865 Byte0 end_step=30 best_step=27
8754 23:19:37.447870 Byte1 end_step=30 best_step=27
8755 23:19:37.451612 Byte0 TX OE(2T, 0.5T) = (3, 3)
8756 23:19:37.454671 Byte1 TX OE(2T, 0.5T) = (3, 3)
8757 23:19:37.455085
8758 23:19:37.455423
8759 23:19:37.461196 [DQSOSCAuto] RK0, (LSB)MR18= 0x1825, (MSB)MR19= 0x303, tDQSOscB0 = 391 ps tDQSOscB1 = 397 ps
8760 23:19:37.464362 CH1 RK0: MR19=303, MR18=1825
8761 23:19:37.471313 CH1_RK0: MR19=0x303, MR18=0x1825, DQSOSC=391, MR23=63, INC=24, DEC=16
8762 23:19:37.471839
8763 23:19:37.474629 ----->DramcWriteLeveling(PI) begin...
8764 23:19:37.475050 ==
8765 23:19:37.477490 Dram Type= 6, Freq= 0, CH_1, rank 1
8766 23:19:37.480845 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8767 23:19:37.481379 ==
8768 23:19:37.484295 Write leveling (Byte 0): 27 => 27
8769 23:19:37.487696 Write leveling (Byte 1): 30 => 30
8770 23:19:37.490991 DramcWriteLeveling(PI) end<-----
8771 23:19:37.491572
8772 23:19:37.492145 ==
8773 23:19:37.494099 Dram Type= 6, Freq= 0, CH_1, rank 1
8774 23:19:37.497556 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8775 23:19:37.498022 ==
8776 23:19:37.500935 [Gating] SW mode calibration
8777 23:19:37.507716 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8778 23:19:37.514910 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8779 23:19:37.517432 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8780 23:19:37.520999 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8781 23:19:37.527420 1 4 8 | B1->B0 | 2a29 2323 | 1 0 | (0 0) (0 0)
8782 23:19:37.530797 1 4 12 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
8783 23:19:37.534008 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8784 23:19:37.540754 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8785 23:19:37.544299 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8786 23:19:37.547691 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8787 23:19:37.553932 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8788 23:19:37.557812 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8789 23:19:37.560659 1 5 8 | B1->B0 | 3333 3434 | 0 1 | (0 1) (1 1)
8790 23:19:37.567262 1 5 12 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 1)
8791 23:19:37.571049 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8792 23:19:37.574273 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8793 23:19:37.580991 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8794 23:19:37.584015 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8795 23:19:37.587649 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8796 23:19:37.594432 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8797 23:19:37.597514 1 6 8 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
8798 23:19:37.600498 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8799 23:19:37.607371 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8800 23:19:37.611143 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8801 23:19:37.614178 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8802 23:19:37.620721 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8803 23:19:37.624292 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8804 23:19:37.626998 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8805 23:19:37.633993 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8806 23:19:37.637672 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8807 23:19:37.640275 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8808 23:19:37.647351 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8809 23:19:37.651228 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8810 23:19:37.654596 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8811 23:19:37.657391 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8812 23:19:37.664434 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8813 23:19:37.667391 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8814 23:19:37.670974 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8815 23:19:37.677481 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8816 23:19:37.680938 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8817 23:19:37.683608 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8818 23:19:37.690334 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8819 23:19:37.694192 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8820 23:19:37.696793 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8821 23:19:37.703865 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8822 23:19:37.707260 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8823 23:19:37.710345 Total UI for P1: 0, mck2ui 16
8824 23:19:37.713878 best dqsien dly found for B1: ( 1, 9, 6)
8825 23:19:37.716727 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8826 23:19:37.720023 Total UI for P1: 0, mck2ui 16
8827 23:19:37.723953 best dqsien dly found for B0: ( 1, 9, 12)
8828 23:19:37.726727 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8829 23:19:37.729928 best DQS1 dly(MCK, UI, PI) = (1, 9, 6)
8830 23:19:37.733623
8831 23:19:37.736373 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8832 23:19:37.739886 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 6)
8833 23:19:37.743513 [Gating] SW calibration Done
8834 23:19:37.744073 ==
8835 23:19:37.746677 Dram Type= 6, Freq= 0, CH_1, rank 1
8836 23:19:37.750609 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8837 23:19:37.751073 ==
8838 23:19:37.752826 RX Vref Scan: 0
8839 23:19:37.753285
8840 23:19:37.753696 RX Vref 0 -> 0, step: 1
8841 23:19:37.754048
8842 23:19:37.756207 RX Delay 0 -> 252, step: 8
8843 23:19:37.759535 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8844 23:19:37.763300 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8845 23:19:37.769671 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8846 23:19:37.772639 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8847 23:19:37.776615 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8848 23:19:37.779694 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8849 23:19:37.783280 iDelay=208, Bit 6, Center 143 (88 ~ 199) 112
8850 23:19:37.789509 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8851 23:19:37.792531 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8852 23:19:37.795937 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8853 23:19:37.799368 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8854 23:19:37.802617 iDelay=208, Bit 11, Center 127 (72 ~ 183) 112
8855 23:19:37.809683 iDelay=208, Bit 12, Center 143 (88 ~ 199) 112
8856 23:19:37.812625 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8857 23:19:37.815689 iDelay=208, Bit 14, Center 139 (88 ~ 191) 104
8858 23:19:37.819174 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8859 23:19:37.822366 ==
8860 23:19:37.822881 Dram Type= 6, Freq= 0, CH_1, rank 1
8861 23:19:37.829214 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8862 23:19:37.829856 ==
8863 23:19:37.830393 DQS Delay:
8864 23:19:37.832402 DQS0 = 0, DQS1 = 0
8865 23:19:37.832979 DQM Delay:
8866 23:19:37.835574 DQM0 = 136, DQM1 = 133
8867 23:19:37.836048 DQ Delay:
8868 23:19:37.838718 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =131
8869 23:19:37.842413 DQ4 =131, DQ5 =151, DQ6 =143, DQ7 =135
8870 23:19:37.845647 DQ8 =119, DQ9 =119, DQ10 =135, DQ11 =127
8871 23:19:37.848813 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8872 23:19:37.849282
8873 23:19:37.849846
8874 23:19:37.850302 ==
8875 23:19:37.851973 Dram Type= 6, Freq= 0, CH_1, rank 1
8876 23:19:37.858870 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8877 23:19:37.859439 ==
8878 23:19:37.859929
8879 23:19:37.860384
8880 23:19:37.860826 TX Vref Scan disable
8881 23:19:37.862134 == TX Byte 0 ==
8882 23:19:37.865678 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8883 23:19:37.872294 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8884 23:19:37.872872 == TX Byte 1 ==
8885 23:19:37.875830 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8886 23:19:37.882071 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8887 23:19:37.882683 ==
8888 23:19:37.885316 Dram Type= 6, Freq= 0, CH_1, rank 1
8889 23:19:37.888741 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8890 23:19:37.889219 ==
8891 23:19:37.901184
8892 23:19:37.904738 TX Vref early break, caculate TX vref
8893 23:19:37.908116 TX Vref=16, minBit 0, minWin=23, winSum=383
8894 23:19:37.911422 TX Vref=18, minBit 0, minWin=24, winSum=391
8895 23:19:37.914494 TX Vref=20, minBit 1, minWin=24, winSum=402
8896 23:19:37.918279 TX Vref=22, minBit 0, minWin=24, winSum=405
8897 23:19:37.921052 TX Vref=24, minBit 1, minWin=25, winSum=417
8898 23:19:37.927929 TX Vref=26, minBit 0, minWin=25, winSum=426
8899 23:19:37.931165 TX Vref=28, minBit 0, minWin=26, winSum=424
8900 23:19:37.934706 TX Vref=30, minBit 1, minWin=25, winSum=419
8901 23:19:37.937889 TX Vref=32, minBit 0, minWin=25, winSum=411
8902 23:19:37.941646 TX Vref=34, minBit 0, minWin=24, winSum=401
8903 23:19:37.947742 [TxChooseVref] Worse bit 0, Min win 26, Win sum 424, Final Vref 28
8904 23:19:37.948287
8905 23:19:37.951157 Final TX Range 0 Vref 28
8906 23:19:37.951620
8907 23:19:37.951988 ==
8908 23:19:37.954468 Dram Type= 6, Freq= 0, CH_1, rank 1
8909 23:19:37.957982 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8910 23:19:37.958451 ==
8911 23:19:37.958817
8912 23:19:37.959157
8913 23:19:37.961412 TX Vref Scan disable
8914 23:19:37.967779 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8915 23:19:37.968320 == TX Byte 0 ==
8916 23:19:37.971140 u2DelayCellOfst[0]=16 cells (5 PI)
8917 23:19:37.974278 u2DelayCellOfst[1]=13 cells (4 PI)
8918 23:19:37.977387 u2DelayCellOfst[2]=0 cells (0 PI)
8919 23:19:37.980806 u2DelayCellOfst[3]=6 cells (2 PI)
8920 23:19:37.984101 u2DelayCellOfst[4]=6 cells (2 PI)
8921 23:19:37.987299 u2DelayCellOfst[5]=16 cells (5 PI)
8922 23:19:37.990885 u2DelayCellOfst[6]=16 cells (5 PI)
8923 23:19:37.993953 u2DelayCellOfst[7]=6 cells (2 PI)
8924 23:19:37.997197 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8925 23:19:38.001012 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8926 23:19:38.004098 == TX Byte 1 ==
8927 23:19:38.004557 u2DelayCellOfst[8]=0 cells (0 PI)
8928 23:19:38.007652 u2DelayCellOfst[9]=3 cells (1 PI)
8929 23:19:38.011142 u2DelayCellOfst[10]=10 cells (3 PI)
8930 23:19:38.013834 u2DelayCellOfst[11]=6 cells (2 PI)
8931 23:19:38.017347 u2DelayCellOfst[12]=16 cells (5 PI)
8932 23:19:38.020546 u2DelayCellOfst[13]=16 cells (5 PI)
8933 23:19:38.023890 u2DelayCellOfst[14]=16 cells (5 PI)
8934 23:19:38.027355 u2DelayCellOfst[15]=16 cells (5 PI)
8935 23:19:38.030566 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8936 23:19:38.037352 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8937 23:19:38.037953 DramC Write-DBI on
8938 23:19:38.038319 ==
8939 23:19:38.040625 Dram Type= 6, Freq= 0, CH_1, rank 1
8940 23:19:38.044046 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8941 23:19:38.047096 ==
8942 23:19:38.047678
8943 23:19:38.048059
8944 23:19:38.048397 TX Vref Scan disable
8945 23:19:38.050396 == TX Byte 0 ==
8946 23:19:38.053797 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8947 23:19:38.057044 == TX Byte 1 ==
8948 23:19:38.061120 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8949 23:19:38.063756 DramC Write-DBI off
8950 23:19:38.064329
8951 23:19:38.064815 [DATLAT]
8952 23:19:38.065270 Freq=1600, CH1 RK1
8953 23:19:38.065863
8954 23:19:38.066836 DATLAT Default: 0xf
8955 23:19:38.067296 0, 0xFFFF, sum = 0
8956 23:19:38.070544 1, 0xFFFF, sum = 0
8957 23:19:38.071013 2, 0xFFFF, sum = 0
8958 23:19:38.074065 3, 0xFFFF, sum = 0
8959 23:19:38.077153 4, 0xFFFF, sum = 0
8960 23:19:38.077664 5, 0xFFFF, sum = 0
8961 23:19:38.080089 6, 0xFFFF, sum = 0
8962 23:19:38.080559 7, 0xFFFF, sum = 0
8963 23:19:38.083763 8, 0xFFFF, sum = 0
8964 23:19:38.084326 9, 0xFFFF, sum = 0
8965 23:19:38.087039 10, 0xFFFF, sum = 0
8966 23:19:38.087605 11, 0xFFFF, sum = 0
8967 23:19:38.090344 12, 0xFFFF, sum = 0
8968 23:19:38.090812 13, 0xFFFF, sum = 0
8969 23:19:38.093687 14, 0x0, sum = 1
8970 23:19:38.094159 15, 0x0, sum = 2
8971 23:19:38.097337 16, 0x0, sum = 3
8972 23:19:38.097965 17, 0x0, sum = 4
8973 23:19:38.100331 best_step = 15
8974 23:19:38.100892
8975 23:19:38.101263 ==
8976 23:19:38.104040 Dram Type= 6, Freq= 0, CH_1, rank 1
8977 23:19:38.107305 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8978 23:19:38.107864 ==
8979 23:19:38.110083 RX Vref Scan: 0
8980 23:19:38.110639
8981 23:19:38.111009 RX Vref 0 -> 0, step: 1
8982 23:19:38.111350
8983 23:19:38.113231 RX Delay 19 -> 252, step: 4
8984 23:19:38.117109 iDelay=195, Bit 0, Center 138 (91 ~ 186) 96
8985 23:19:38.123320 iDelay=195, Bit 1, Center 130 (79 ~ 182) 104
8986 23:19:38.126748 iDelay=195, Bit 2, Center 122 (71 ~ 174) 104
8987 23:19:38.130367 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
8988 23:19:38.133715 iDelay=195, Bit 4, Center 130 (83 ~ 178) 96
8989 23:19:38.136509 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
8990 23:19:38.143320 iDelay=195, Bit 6, Center 144 (95 ~ 194) 100
8991 23:19:38.146673 iDelay=195, Bit 7, Center 134 (83 ~ 186) 104
8992 23:19:38.149686 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8993 23:19:38.153302 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8994 23:19:38.156439 iDelay=195, Bit 10, Center 132 (83 ~ 182) 100
8995 23:19:38.163164 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
8996 23:19:38.166526 iDelay=195, Bit 12, Center 142 (91 ~ 194) 104
8997 23:19:38.169951 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
8998 23:19:38.173264 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
8999 23:19:38.176575 iDelay=195, Bit 15, Center 140 (91 ~ 190) 100
9000 23:19:38.179595 ==
9001 23:19:38.180053 Dram Type= 6, Freq= 0, CH_1, rank 1
9002 23:19:38.186551 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9003 23:19:38.187113 ==
9004 23:19:38.187479 DQS Delay:
9005 23:19:38.189769 DQS0 = 0, DQS1 = 0
9006 23:19:38.190232 DQM Delay:
9007 23:19:38.193501 DQM0 = 134, DQM1 = 130
9008 23:19:38.194141 DQ Delay:
9009 23:19:38.196407 DQ0 =138, DQ1 =130, DQ2 =122, DQ3 =130
9010 23:19:38.199720 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =134
9011 23:19:38.202843 DQ8 =116, DQ9 =118, DQ10 =132, DQ11 =124
9012 23:19:38.206392 DQ12 =142, DQ13 =138, DQ14 =136, DQ15 =140
9013 23:19:38.206945
9014 23:19:38.207311
9015 23:19:38.207649
9016 23:19:38.209341 [DramC_TX_OE_Calibration] TA2
9017 23:19:38.213302 Original DQ_B0 (3 6) =30, OEN = 27
9018 23:19:38.216253 Original DQ_B1 (3 6) =30, OEN = 27
9019 23:19:38.219294 24, 0x0, End_B0=24 End_B1=24
9020 23:19:38.222569 25, 0x0, End_B0=25 End_B1=25
9021 23:19:38.223049 26, 0x0, End_B0=26 End_B1=26
9022 23:19:38.226204 27, 0x0, End_B0=27 End_B1=27
9023 23:19:38.229632 28, 0x0, End_B0=28 End_B1=28
9024 23:19:38.233070 29, 0x0, End_B0=29 End_B1=29
9025 23:19:38.235923 30, 0x0, End_B0=30 End_B1=30
9026 23:19:38.236397 31, 0x4141, End_B0=30 End_B1=30
9027 23:19:38.239978 Byte0 end_step=30 best_step=27
9028 23:19:38.242720 Byte1 end_step=30 best_step=27
9029 23:19:38.245900 Byte0 TX OE(2T, 0.5T) = (3, 3)
9030 23:19:38.249281 Byte1 TX OE(2T, 0.5T) = (3, 3)
9031 23:19:38.249778
9032 23:19:38.250245
9033 23:19:38.255859 [DQSOSCAuto] RK1, (LSB)MR18= 0x2409, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 391 ps
9034 23:19:38.259460 CH1 RK1: MR19=303, MR18=2409
9035 23:19:38.265988 CH1_RK1: MR19=0x303, MR18=0x2409, DQSOSC=391, MR23=63, INC=24, DEC=16
9036 23:19:38.269632 [RxdqsGatingPostProcess] freq 1600
9037 23:19:38.275989 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9038 23:19:38.276606 best DQS0 dly(2T, 0.5T) = (1, 1)
9039 23:19:38.279109 best DQS1 dly(2T, 0.5T) = (1, 1)
9040 23:19:38.282403 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9041 23:19:38.285673 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9042 23:19:38.288976 best DQS0 dly(2T, 0.5T) = (1, 1)
9043 23:19:38.292359 best DQS1 dly(2T, 0.5T) = (1, 1)
9044 23:19:38.296116 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9045 23:19:38.299129 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9046 23:19:38.302706 Pre-setting of DQS Precalculation
9047 23:19:38.305698 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9048 23:19:38.316018 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9049 23:19:38.322643 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9050 23:19:38.323188
9051 23:19:38.323643
9052 23:19:38.325670 [Calibration Summary] 3200 Mbps
9053 23:19:38.326293 CH 0, Rank 0
9054 23:19:38.329445 SW Impedance : PASS
9055 23:19:38.330069 DUTY Scan : NO K
9056 23:19:38.332464 ZQ Calibration : PASS
9057 23:19:38.335971 Jitter Meter : NO K
9058 23:19:38.336537 CBT Training : PASS
9059 23:19:38.339478 Write leveling : PASS
9060 23:19:38.342756 RX DQS gating : PASS
9061 23:19:38.343318 RX DQ/DQS(RDDQC) : PASS
9062 23:19:38.346267 TX DQ/DQS : PASS
9063 23:19:38.346826 RX DATLAT : PASS
9064 23:19:38.349482 RX DQ/DQS(Engine): PASS
9065 23:19:38.352484 TX OE : PASS
9066 23:19:38.352953 All Pass.
9067 23:19:38.353319
9068 23:19:38.353712 CH 0, Rank 1
9069 23:19:38.356183 SW Impedance : PASS
9070 23:19:38.359699 DUTY Scan : NO K
9071 23:19:38.360257 ZQ Calibration : PASS
9072 23:19:38.362276 Jitter Meter : NO K
9073 23:19:38.366036 CBT Training : PASS
9074 23:19:38.366605 Write leveling : PASS
9075 23:19:38.369225 RX DQS gating : PASS
9076 23:19:38.372831 RX DQ/DQS(RDDQC) : PASS
9077 23:19:38.373386 TX DQ/DQS : PASS
9078 23:19:38.376039 RX DATLAT : PASS
9079 23:19:38.379117 RX DQ/DQS(Engine): PASS
9080 23:19:38.379581 TX OE : PASS
9081 23:19:38.379953 All Pass.
9082 23:19:38.382424
9083 23:19:38.382896 CH 1, Rank 0
9084 23:19:38.386030 SW Impedance : PASS
9085 23:19:38.386579 DUTY Scan : NO K
9086 23:19:38.388955 ZQ Calibration : PASS
9087 23:19:38.389413 Jitter Meter : NO K
9088 23:19:38.392770 CBT Training : PASS
9089 23:19:38.395469 Write leveling : PASS
9090 23:19:38.395932 RX DQS gating : PASS
9091 23:19:38.398878 RX DQ/DQS(RDDQC) : PASS
9092 23:19:38.402209 TX DQ/DQS : PASS
9093 23:19:38.402673 RX DATLAT : PASS
9094 23:19:38.405482 RX DQ/DQS(Engine): PASS
9095 23:19:38.409469 TX OE : PASS
9096 23:19:38.410268 All Pass.
9097 23:19:38.410664
9098 23:19:38.411016 CH 1, Rank 1
9099 23:19:38.412462 SW Impedance : PASS
9100 23:19:38.416221 DUTY Scan : NO K
9101 23:19:38.416775 ZQ Calibration : PASS
9102 23:19:38.419146 Jitter Meter : NO K
9103 23:19:38.422470 CBT Training : PASS
9104 23:19:38.423027 Write leveling : PASS
9105 23:19:38.425704 RX DQS gating : PASS
9106 23:19:38.429481 RX DQ/DQS(RDDQC) : PASS
9107 23:19:38.430090 TX DQ/DQS : PASS
9108 23:19:38.432890 RX DATLAT : PASS
9109 23:19:38.433444 RX DQ/DQS(Engine): PASS
9110 23:19:38.435450 TX OE : PASS
9111 23:19:38.435915 All Pass.
9112 23:19:38.436289
9113 23:19:38.439201 DramC Write-DBI on
9114 23:19:38.442394 PER_BANK_REFRESH: Hybrid Mode
9115 23:19:38.442858 TX_TRACKING: ON
9116 23:19:38.452635 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9117 23:19:38.459073 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9118 23:19:38.468561 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9119 23:19:38.472575 [FAST_K] Save calibration result to emmc
9120 23:19:38.473131 sync common calibartion params.
9121 23:19:38.475430 sync cbt_mode0:1, 1:1
9122 23:19:38.478596 dram_init: ddr_geometry: 2
9123 23:19:38.482394 dram_init: ddr_geometry: 2
9124 23:19:38.482950 dram_init: ddr_geometry: 2
9125 23:19:38.485528 0:dram_rank_size:100000000
9126 23:19:38.488853 1:dram_rank_size:100000000
9127 23:19:38.492006 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9128 23:19:38.495152 DFS_SHUFFLE_HW_MODE: ON
9129 23:19:38.498443 dramc_set_vcore_voltage set vcore to 725000
9130 23:19:38.501910 Read voltage for 1600, 0
9131 23:19:38.502370 Vio18 = 0
9132 23:19:38.505196 Vcore = 725000
9133 23:19:38.505707 Vdram = 0
9134 23:19:38.506089 Vddq = 0
9135 23:19:38.506553 Vmddr = 0
9136 23:19:38.508351 switch to 3200 Mbps bootup
9137 23:19:38.511619 [DramcRunTimeConfig]
9138 23:19:38.512140 PHYPLL
9139 23:19:38.515639 DPM_CONTROL_AFTERK: ON
9140 23:19:38.516092 PER_BANK_REFRESH: ON
9141 23:19:38.518810 REFRESH_OVERHEAD_REDUCTION: ON
9142 23:19:38.521568 CMD_PICG_NEW_MODE: OFF
9143 23:19:38.522036 XRTWTW_NEW_MODE: ON
9144 23:19:38.525233 XRTRTR_NEW_MODE: ON
9145 23:19:38.525684 TX_TRACKING: ON
9146 23:19:38.528166 RDSEL_TRACKING: OFF
9147 23:19:38.531900 DQS Precalculation for DVFS: ON
9148 23:19:38.532339 RX_TRACKING: OFF
9149 23:19:38.532722 HW_GATING DBG: ON
9150 23:19:38.534797 ZQCS_ENABLE_LP4: ON
9151 23:19:38.538074 RX_PICG_NEW_MODE: ON
9152 23:19:38.538487 TX_PICG_NEW_MODE: ON
9153 23:19:38.541945 ENABLE_RX_DCM_DPHY: ON
9154 23:19:38.545184 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9155 23:19:38.545624 DUMMY_READ_FOR_TRACKING: OFF
9156 23:19:38.548300 !!! SPM_CONTROL_AFTERK: OFF
9157 23:19:38.551807 !!! SPM could not control APHY
9158 23:19:38.555388 IMPEDANCE_TRACKING: ON
9159 23:19:38.555905 TEMP_SENSOR: ON
9160 23:19:38.558647 HW_SAVE_FOR_SR: OFF
9161 23:19:38.562027 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9162 23:19:38.564909 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9163 23:19:38.565324 Read ODT Tracking: ON
9164 23:19:38.568562 Refresh Rate DeBounce: ON
9165 23:19:38.571604 DFS_NO_QUEUE_FLUSH: ON
9166 23:19:38.575351 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9167 23:19:38.575860 ENABLE_DFS_RUNTIME_MRW: OFF
9168 23:19:38.578263 DDR_RESERVE_NEW_MODE: ON
9169 23:19:38.581808 MR_CBT_SWITCH_FREQ: ON
9170 23:19:38.582318 =========================
9171 23:19:38.601706 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9172 23:19:38.605308 dram_init: ddr_geometry: 2
9173 23:19:38.623459 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9174 23:19:38.627239 dram_init: dram init end (result: 0)
9175 23:19:38.633387 DRAM-K: Full calibration passed in 24461 msecs
9176 23:19:38.636601 MRC: failed to locate region type 0.
9177 23:19:38.637177 DRAM rank0 size:0x100000000,
9178 23:19:38.639855 DRAM rank1 size=0x100000000
9179 23:19:38.649446 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9180 23:19:38.656399 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9181 23:19:38.663057 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9182 23:19:38.670168 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9183 23:19:38.673332 DRAM rank0 size:0x100000000,
9184 23:19:38.676449 DRAM rank1 size=0x100000000
9185 23:19:38.676910 CBMEM:
9186 23:19:38.679346 IMD: root @ 0xfffff000 254 entries.
9187 23:19:38.682754 IMD: root @ 0xffffec00 62 entries.
9188 23:19:38.686001 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9189 23:19:38.689433 WARNING: RO_VPD is uninitialized or empty.
9190 23:19:38.696488 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9191 23:19:38.703063 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9192 23:19:38.715917 read SPI 0x42894 0xe01e: 6226 us, 9215 KB/s, 73.720 Mbps
9193 23:19:38.727417 BS: romstage times (exec / console): total (unknown) / 23992 ms
9194 23:19:38.727975
9195 23:19:38.728343
9196 23:19:38.737405 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9197 23:19:38.740942 ARM64: Exception handlers installed.
9198 23:19:38.743893 ARM64: Testing exception
9199 23:19:38.747687 ARM64: Done test exception
9200 23:19:38.748236 Enumerating buses...
9201 23:19:38.750815 Show all devs... Before device enumeration.
9202 23:19:38.754230 Root Device: enabled 1
9203 23:19:38.757351 CPU_CLUSTER: 0: enabled 1
9204 23:19:38.758020 CPU: 00: enabled 1
9205 23:19:38.760438 Compare with tree...
9206 23:19:38.760896 Root Device: enabled 1
9207 23:19:38.763860 CPU_CLUSTER: 0: enabled 1
9208 23:19:38.767361 CPU: 00: enabled 1
9209 23:19:38.767916 Root Device scanning...
9210 23:19:38.770345 scan_static_bus for Root Device
9211 23:19:38.774125 CPU_CLUSTER: 0 enabled
9212 23:19:38.777248 scan_static_bus for Root Device done
9213 23:19:38.780816 scan_bus: bus Root Device finished in 8 msecs
9214 23:19:38.781276 done
9215 23:19:38.787462 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9216 23:19:38.790480 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9217 23:19:38.797207 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9218 23:19:38.800336 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9219 23:19:38.803967 Allocating resources...
9220 23:19:38.807422 Reading resources...
9221 23:19:38.810164 Root Device read_resources bus 0 link: 0
9222 23:19:38.810624 DRAM rank0 size:0x100000000,
9223 23:19:38.814095 DRAM rank1 size=0x100000000
9224 23:19:38.817136 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9225 23:19:38.820769 CPU: 00 missing read_resources
9226 23:19:38.823634 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9227 23:19:38.830290 Root Device read_resources bus 0 link: 0 done
9228 23:19:38.830849 Done reading resources.
9229 23:19:38.837298 Show resources in subtree (Root Device)...After reading.
9230 23:19:38.840471 Root Device child on link 0 CPU_CLUSTER: 0
9231 23:19:38.843660 CPU_CLUSTER: 0 child on link 0 CPU: 00
9232 23:19:38.853440 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9233 23:19:38.854071 CPU: 00
9234 23:19:38.856841 Root Device assign_resources, bus 0 link: 0
9235 23:19:38.859977 CPU_CLUSTER: 0 missing set_resources
9236 23:19:38.863736 Root Device assign_resources, bus 0 link: 0 done
9237 23:19:38.866680 Done setting resources.
9238 23:19:38.873439 Show resources in subtree (Root Device)...After assigning values.
9239 23:19:38.876634 Root Device child on link 0 CPU_CLUSTER: 0
9240 23:19:38.879423 CPU_CLUSTER: 0 child on link 0 CPU: 00
9241 23:19:38.889948 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9242 23:19:38.890506 CPU: 00
9243 23:19:38.893121 Done allocating resources.
9244 23:19:38.896310 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9245 23:19:38.899982 Enabling resources...
9246 23:19:38.900542 done.
9247 23:19:38.906013 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9248 23:19:38.906600 Initializing devices...
9249 23:19:38.909246 Root Device init
9250 23:19:38.909755 init hardware done!
9251 23:19:38.912744 0x00000018: ctrlr->caps
9252 23:19:38.916056 52.000 MHz: ctrlr->f_max
9253 23:19:38.916862 0.400 MHz: ctrlr->f_min
9254 23:19:38.919660 0x40ff8080: ctrlr->voltages
9255 23:19:38.922862 sclk: 390625
9256 23:19:38.923317 Bus Width = 1
9257 23:19:38.923680 sclk: 390625
9258 23:19:38.925995 Bus Width = 1
9259 23:19:38.926454 Early init status = 3
9260 23:19:38.933059 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9261 23:19:38.936191 in-header: 03 fc 00 00 01 00 00 00
9262 23:19:38.939068 in-data: 00
9263 23:19:38.942562 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9264 23:19:38.946018 in-header: 03 fd 00 00 00 00 00 00
9265 23:19:38.949509 in-data:
9266 23:19:38.952900 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9267 23:19:38.956251 in-header: 03 fc 00 00 01 00 00 00
9268 23:19:38.959368 in-data: 00
9269 23:19:38.962849 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9270 23:19:38.967529 in-header: 03 fd 00 00 00 00 00 00
9271 23:19:38.970878 in-data:
9272 23:19:38.974217 [SSUSB] Setting up USB HOST controller...
9273 23:19:38.977425 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9274 23:19:38.980860 [SSUSB] phy power-on done.
9275 23:19:38.984108 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9276 23:19:38.990929 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9277 23:19:38.994254 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9278 23:19:39.001028 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9279 23:19:39.007326 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9280 23:19:39.013705 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9281 23:19:39.020854 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9282 23:19:39.027217 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9283 23:19:39.030758 SPM: binary array size = 0x9dc
9284 23:19:39.034133 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9285 23:19:39.040762 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9286 23:19:39.047509 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9287 23:19:39.050737 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9288 23:19:39.053865 configure_display: Starting display init
9289 23:19:39.090283 anx7625_power_on_init: Init interface.
9290 23:19:39.094228 anx7625_disable_pd_protocol: Disabled PD feature.
9291 23:19:39.097001 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9292 23:19:39.125211 anx7625_start_dp_work: Secure OCM version=00
9293 23:19:39.128636 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9294 23:19:39.143121 sp_tx_get_edid_block: EDID Block = 1
9295 23:19:39.246026 Extracted contents:
9296 23:19:39.249034 header: 00 ff ff ff ff ff ff 00
9297 23:19:39.252331 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9298 23:19:39.255652 version: 01 04
9299 23:19:39.258877 basic params: 95 1f 11 78 0a
9300 23:19:39.262003 chroma info: 76 90 94 55 54 90 27 21 50 54
9301 23:19:39.265401 established: 00 00 00
9302 23:19:39.271765 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9303 23:19:39.275826 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9304 23:19:39.282326 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9305 23:19:39.288541 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9306 23:19:39.295412 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9307 23:19:39.298272 extensions: 00
9308 23:19:39.298730 checksum: fb
9309 23:19:39.299231
9310 23:19:39.302123 Manufacturer: IVO Model 57d Serial Number 0
9311 23:19:39.305682 Made week 0 of 2020
9312 23:19:39.306236 EDID version: 1.4
9313 23:19:39.308791 Digital display
9314 23:19:39.312085 6 bits per primary color channel
9315 23:19:39.312648 DisplayPort interface
9316 23:19:39.315096 Maximum image size: 31 cm x 17 cm
9317 23:19:39.318264 Gamma: 220%
9318 23:19:39.318723 Check DPMS levels
9319 23:19:39.321978 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9320 23:19:39.328483 First detailed timing is preferred timing
9321 23:19:39.329044 Established timings supported:
9322 23:19:39.331862 Standard timings supported:
9323 23:19:39.335179 Detailed timings
9324 23:19:39.338374 Hex of detail: 383680a07038204018303c0035ae10000019
9325 23:19:39.341651 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9326 23:19:39.348581 0780 0798 07c8 0820 hborder 0
9327 23:19:39.351562 0438 043b 0447 0458 vborder 0
9328 23:19:39.355126 -hsync -vsync
9329 23:19:39.355684 Did detailed timing
9330 23:19:39.361519 Hex of detail: 000000000000000000000000000000000000
9331 23:19:39.362001 Manufacturer-specified data, tag 0
9332 23:19:39.368324 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9333 23:19:39.371541 ASCII string: InfoVision
9334 23:19:39.374588 Hex of detail: 000000fe00523134304e574635205248200a
9335 23:19:39.377903 ASCII string: R140NWF5 RH
9336 23:19:39.378338 Checksum
9337 23:19:39.381805 Checksum: 0xfb (valid)
9338 23:19:39.384952 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9339 23:19:39.388447 DSI data_rate: 832800000 bps
9340 23:19:39.394851 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9341 23:19:39.397973 anx7625_parse_edid: pixelclock(138800).
9342 23:19:39.401304 hactive(1920), hsync(48), hfp(24), hbp(88)
9343 23:19:39.405069 vactive(1080), vsync(12), vfp(3), vbp(17)
9344 23:19:39.408508 anx7625_dsi_config: config dsi.
9345 23:19:39.414925 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9346 23:19:39.427256 anx7625_dsi_config: success to config DSI
9347 23:19:39.430892 anx7625_dp_start: MIPI phy setup OK.
9348 23:19:39.434321 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9349 23:19:39.437354 mtk_ddp_mode_set invalid vrefresh 60
9350 23:19:39.440741 main_disp_path_setup
9351 23:19:39.441150 ovl_layer_smi_id_en
9352 23:19:39.444266 ovl_layer_smi_id_en
9353 23:19:39.444779 ccorr_config
9354 23:19:39.445108 aal_config
9355 23:19:39.448138 gamma_config
9356 23:19:39.448737 postmask_config
9357 23:19:39.450905 dither_config
9358 23:19:39.454111 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9359 23:19:39.460614 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9360 23:19:39.464262 Root Device init finished in 551 msecs
9361 23:19:39.467316 CPU_CLUSTER: 0 init
9362 23:19:39.474249 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9363 23:19:39.477448 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9364 23:19:39.480765 APU_MBOX 0x190000b0 = 0x10001
9365 23:19:39.483926 APU_MBOX 0x190001b0 = 0x10001
9366 23:19:39.487363 APU_MBOX 0x190005b0 = 0x10001
9367 23:19:39.490507 APU_MBOX 0x190006b0 = 0x10001
9368 23:19:39.494217 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9369 23:19:39.506573 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9370 23:19:39.519355 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9371 23:19:39.525493 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9372 23:19:39.537332 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9373 23:19:39.546680 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9374 23:19:39.549800 CPU_CLUSTER: 0 init finished in 81 msecs
9375 23:19:39.553223 Devices initialized
9376 23:19:39.556698 Show all devs... After init.
9377 23:19:39.557158 Root Device: enabled 1
9378 23:19:39.559801 CPU_CLUSTER: 0: enabled 1
9379 23:19:39.560363 CPU: 00: enabled 1
9380 23:19:39.567033 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9381 23:19:39.569887 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9382 23:19:39.573297 ELOG: NV offset 0x57f000 size 0x1000
9383 23:19:39.579625 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9384 23:19:39.587003 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9385 23:19:39.590076 ELOG: Event(17) added with size 13 at 2023-12-03 23:17:25 UTC
9386 23:19:39.593207 out: cmd=0x121: 03 db 21 01 00 00 00 00
9387 23:19:39.596765 in-header: 03 d7 00 00 2c 00 00 00
9388 23:19:39.609988 in-data: 88 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9389 23:19:39.616698 ELOG: Event(A1) added with size 10 at 2023-12-03 23:17:25 UTC
9390 23:19:39.623819 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9391 23:19:39.630234 ELOG: Event(A0) added with size 9 at 2023-12-03 23:17:25 UTC
9392 23:19:39.633722 elog_add_boot_reason: Logged dev mode boot
9393 23:19:39.636746 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9394 23:19:39.640292 Finalize devices...
9395 23:19:39.640904 Devices finalized
9396 23:19:39.646989 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9397 23:19:39.649561 Writing coreboot table at 0xffe64000
9398 23:19:39.652876 0. 000000000010a000-0000000000113fff: RAMSTAGE
9399 23:19:39.656719 1. 0000000040000000-00000000400fffff: RAM
9400 23:19:39.663574 2. 0000000040100000-000000004032afff: RAMSTAGE
9401 23:19:39.666572 3. 000000004032b000-00000000545fffff: RAM
9402 23:19:39.670282 4. 0000000054600000-000000005465ffff: BL31
9403 23:19:39.673265 5. 0000000054660000-00000000ffe63fff: RAM
9404 23:19:39.676707 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9405 23:19:39.683157 7. 0000000100000000-000000023fffffff: RAM
9406 23:19:39.683622 Passing 5 GPIOs to payload:
9407 23:19:39.690087 NAME | PORT | POLARITY | VALUE
9408 23:19:39.693291 EC in RW | 0x000000aa | low | undefined
9409 23:19:39.699570 EC interrupt | 0x00000005 | low | undefined
9410 23:19:39.703600 TPM interrupt | 0x000000ab | high | undefined
9411 23:19:39.707068 SD card detect | 0x00000011 | high | undefined
9412 23:19:39.713148 speaker enable | 0x00000093 | high | undefined
9413 23:19:39.716414 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9414 23:19:39.719520 in-header: 03 f9 00 00 02 00 00 00
9415 23:19:39.719986 in-data: 02 00
9416 23:19:39.723386 ADC[4]: Raw value=904357 ID=7
9417 23:19:39.726373 ADC[3]: Raw value=213441 ID=1
9418 23:19:39.726929 RAM Code: 0x71
9419 23:19:39.729716 ADC[6]: Raw value=75332 ID=0
9420 23:19:39.733067 ADC[5]: Raw value=212703 ID=1
9421 23:19:39.733723 SKU Code: 0x1
9422 23:19:39.740010 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 425c
9423 23:19:39.743299 coreboot table: 964 bytes.
9424 23:19:39.746515 IMD ROOT 0. 0xfffff000 0x00001000
9425 23:19:39.749836 IMD SMALL 1. 0xffffe000 0x00001000
9426 23:19:39.752874 RO MCACHE 2. 0xffffc000 0x00001104
9427 23:19:39.756135 CONSOLE 3. 0xfff7c000 0x00080000
9428 23:19:39.759558 FMAP 4. 0xfff7b000 0x00000452
9429 23:19:39.762632 TIME STAMP 5. 0xfff7a000 0x00000910
9430 23:19:39.766187 VBOOT WORK 6. 0xfff66000 0x00014000
9431 23:19:39.769664 RAMOOPS 7. 0xffe66000 0x00100000
9432 23:19:39.772687 COREBOOT 8. 0xffe64000 0x00002000
9433 23:19:39.773196 IMD small region:
9434 23:19:39.775994 IMD ROOT 0. 0xffffec00 0x00000400
9435 23:19:39.779144 VPD 1. 0xffffeb80 0x0000006c
9436 23:19:39.782968 MMC STATUS 2. 0xffffeb60 0x00000004
9437 23:19:39.789775 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9438 23:19:39.793258 Probing TPM: done!
9439 23:19:39.796439 Connected to device vid:did:rid of 1ae0:0028:00
9440 23:19:39.802816 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9441 23:19:39.810877 Initialized TPM device CR50 revision 0
9442 23:19:39.811401 Checking cr50 for pending updates
9443 23:19:39.816422 Reading cr50 TPM mode
9444 23:19:39.825163 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9445 23:19:39.831470 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9446 23:19:39.871426 read SPI 0x3990ec 0x4f1b0: 34851 us, 9297 KB/s, 74.376 Mbps
9447 23:19:39.874913 Checking segment from ROM address 0x40100000
9448 23:19:39.878521 Checking segment from ROM address 0x4010001c
9449 23:19:39.884672 Loading segment from ROM address 0x40100000
9450 23:19:39.885215 code (compression=0)
9451 23:19:39.894704 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9452 23:19:39.901340 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9453 23:19:39.901920 it's not compressed!
9454 23:19:39.908546 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9455 23:19:39.911990 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9456 23:19:39.932149 Loading segment from ROM address 0x4010001c
9457 23:19:39.932886 Entry Point 0x80000000
9458 23:19:39.935312 Loaded segments
9459 23:19:39.938624 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9460 23:19:39.944917 Jumping to boot code at 0x80000000(0xffe64000)
9461 23:19:39.951595 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9462 23:19:39.958663 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9463 23:19:39.966553 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9464 23:19:39.969619 Checking segment from ROM address 0x40100000
9465 23:19:39.973311 Checking segment from ROM address 0x4010001c
9466 23:19:39.979335 Loading segment from ROM address 0x40100000
9467 23:19:39.979752 code (compression=1)
9468 23:19:39.986562 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9469 23:19:39.995916 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9470 23:19:39.996465 using LZMA
9471 23:19:40.004834 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9472 23:19:40.011034 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9473 23:19:40.015090 Loading segment from ROM address 0x4010001c
9474 23:19:40.015586 Entry Point 0x54601000
9475 23:19:40.017712 Loaded segments
9476 23:19:40.020940 NOTICE: MT8192 bl31_setup
9477 23:19:40.028201 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9478 23:19:40.031520 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9479 23:19:40.034838 WARNING: region 0:
9480 23:19:40.038308 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9481 23:19:40.038729 WARNING: region 1:
9482 23:19:40.045261 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9483 23:19:40.045833 WARNING: region 2:
9484 23:19:40.051833 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9485 23:19:40.055141 WARNING: region 3:
9486 23:19:40.058412 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9487 23:19:40.061867 WARNING: region 4:
9488 23:19:40.065171 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9489 23:19:40.068672 WARNING: region 5:
9490 23:19:40.072209 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9491 23:19:40.075374 WARNING: region 6:
9492 23:19:40.078712 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9493 23:19:40.079237 WARNING: region 7:
9494 23:19:40.085147 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9495 23:19:40.091973 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9496 23:19:40.095565 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9497 23:19:40.098666 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9498 23:19:40.105636 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9499 23:19:40.108765 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9500 23:19:40.112245 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9501 23:19:40.118929 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9502 23:19:40.121963 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9503 23:19:40.125373 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9504 23:19:40.132132 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9505 23:19:40.135654 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9506 23:19:40.138525 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9507 23:19:40.145789 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9508 23:19:40.148979 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9509 23:19:40.155442 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9510 23:19:40.158647 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9511 23:19:40.162000 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9512 23:19:40.168525 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9513 23:19:40.172074 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9514 23:19:40.175474 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9515 23:19:40.182047 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9516 23:19:40.185203 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9517 23:19:40.192361 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9518 23:19:40.195610 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9519 23:19:40.198726 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9520 23:19:40.206091 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9521 23:19:40.209220 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9522 23:19:40.216220 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9523 23:19:40.218662 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9524 23:19:40.222372 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9525 23:19:40.228611 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9526 23:19:40.232128 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9527 23:19:40.235468 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9528 23:19:40.242225 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9529 23:19:40.245799 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9530 23:19:40.249252 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9531 23:19:40.252421 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9532 23:19:40.259003 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9533 23:19:40.262233 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9534 23:19:40.265691 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9535 23:19:40.268598 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9536 23:19:40.275228 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9537 23:19:40.278609 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9538 23:19:40.281985 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9539 23:19:40.285141 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9540 23:19:40.291556 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9541 23:19:40.295023 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9542 23:19:40.298501 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9543 23:19:40.305125 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9544 23:19:40.308752 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9545 23:19:40.314879 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9546 23:19:40.318174 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9547 23:19:40.321742 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9548 23:19:40.328197 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9549 23:19:40.332116 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9550 23:19:40.338419 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9551 23:19:40.341358 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9552 23:19:40.348382 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9553 23:19:40.351886 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9554 23:19:40.354827 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9555 23:19:40.361932 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9556 23:19:40.365124 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9557 23:19:40.371909 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9558 23:19:40.375424 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9559 23:19:40.382288 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9560 23:19:40.384955 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9561 23:19:40.388544 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9562 23:19:40.395550 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9563 23:19:40.398693 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9564 23:19:40.405036 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9565 23:19:40.408185 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9566 23:19:40.415100 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9567 23:19:40.418216 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9568 23:19:40.421796 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9569 23:19:40.428512 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9570 23:19:40.432250 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9571 23:19:40.438179 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9572 23:19:40.441718 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9573 23:19:40.448354 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9574 23:19:40.451936 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9575 23:19:40.455051 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9576 23:19:40.461621 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9577 23:19:40.465335 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9578 23:19:40.472109 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9579 23:19:40.475332 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9580 23:19:40.481912 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9581 23:19:40.485224 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9582 23:19:40.488708 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9583 23:19:40.495353 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9584 23:19:40.498577 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9585 23:19:40.505157 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9586 23:19:40.508721 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9587 23:19:40.515477 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9588 23:19:40.518585 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9589 23:19:40.522446 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9590 23:19:40.529159 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9591 23:19:40.532385 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9592 23:19:40.535964 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9593 23:19:40.542232 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9594 23:19:40.545916 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9595 23:19:40.548493 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9596 23:19:40.555294 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9597 23:19:40.558247 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9598 23:19:40.562079 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9599 23:19:40.569023 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9600 23:19:40.572155 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9601 23:19:40.575331 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9602 23:19:40.581682 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9603 23:19:40.585113 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9604 23:19:40.591687 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9605 23:19:40.595213 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9606 23:19:40.601669 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9607 23:19:40.604831 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9608 23:19:40.608622 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9609 23:19:40.615231 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9610 23:19:40.618298 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9611 23:19:40.621454 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9612 23:19:40.628938 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9613 23:19:40.632185 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9614 23:19:40.635620 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9615 23:19:40.638735 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9616 23:19:40.645422 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9617 23:19:40.648674 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9618 23:19:40.652277 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9619 23:19:40.658523 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9620 23:19:40.661841 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9621 23:19:40.665069 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9622 23:19:40.672035 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9623 23:19:40.675141 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9624 23:19:40.681853 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9625 23:19:40.685404 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9626 23:19:40.688570 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9627 23:19:40.695103 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9628 23:19:40.698652 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9629 23:19:40.705210 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9630 23:19:40.708933 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9631 23:19:40.712173 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9632 23:19:40.719023 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9633 23:19:40.722208 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9634 23:19:40.725498 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9635 23:19:40.731725 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9636 23:19:40.735201 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9637 23:19:40.741825 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9638 23:19:40.745215 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9639 23:19:40.748475 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9640 23:19:40.754956 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9641 23:19:40.758287 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9642 23:19:40.762075 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9643 23:19:40.768502 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9644 23:19:40.771878 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9645 23:19:40.778837 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9646 23:19:40.781960 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9647 23:19:40.785187 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9648 23:19:40.792164 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9649 23:19:40.795372 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9650 23:19:40.801688 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9651 23:19:40.805696 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9652 23:19:40.808412 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9653 23:19:40.815435 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9654 23:19:40.818653 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9655 23:19:40.822155 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9656 23:19:40.828677 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9657 23:19:40.832431 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9658 23:19:40.839105 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9659 23:19:40.841915 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9660 23:19:40.845121 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9661 23:19:40.851924 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9662 23:19:40.855272 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9663 23:19:40.861771 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9664 23:19:40.865249 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9665 23:19:40.868683 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9666 23:19:40.875101 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9667 23:19:40.878305 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9668 23:19:40.885199 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9669 23:19:40.887698 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9670 23:19:40.891443 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9671 23:19:40.897793 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9672 23:19:40.900995 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9673 23:19:40.908406 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9674 23:19:40.911395 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9675 23:19:40.914226 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9676 23:19:40.921813 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9677 23:19:40.924613 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9678 23:19:40.930941 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9679 23:19:40.934360 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9680 23:19:40.938080 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9681 23:19:40.944589 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9682 23:19:40.947827 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9683 23:19:40.954625 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9684 23:19:40.958217 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9685 23:19:40.961107 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9686 23:19:40.968041 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9687 23:19:40.970833 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9688 23:19:40.977779 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9689 23:19:40.981431 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9690 23:19:40.984220 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9691 23:19:40.990776 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9692 23:19:40.994360 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9693 23:19:41.000743 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9694 23:19:41.004305 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9695 23:19:41.010582 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9696 23:19:41.014460 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9697 23:19:41.017151 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9698 23:19:41.023801 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9699 23:19:41.027341 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9700 23:19:41.034094 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9701 23:19:41.037253 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9702 23:19:41.040361 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9703 23:19:41.047450 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9704 23:19:41.050415 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9705 23:19:41.056937 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9706 23:19:41.060411 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9707 23:19:41.067284 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9708 23:19:41.070514 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9709 23:19:41.073746 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9710 23:19:41.080267 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9711 23:19:41.083600 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9712 23:19:41.090455 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9713 23:19:41.093328 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9714 23:19:41.100493 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9715 23:19:41.103715 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9716 23:19:41.106648 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9717 23:19:41.113622 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9718 23:19:41.116699 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9719 23:19:41.123430 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9720 23:19:41.126428 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9721 23:19:41.133280 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9722 23:19:41.136393 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9723 23:19:41.139866 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9724 23:19:41.146543 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9725 23:19:41.149688 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9726 23:19:41.153323 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9727 23:19:41.156325 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9728 23:19:41.159467 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9729 23:19:41.166544 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9730 23:19:41.169663 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9731 23:19:41.176832 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9732 23:19:41.180177 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9733 23:19:41.182845 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9734 23:19:41.189477 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9735 23:19:41.192635 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9736 23:19:41.195949 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9737 23:19:41.202491 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9738 23:19:41.206562 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9739 23:19:41.212979 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9740 23:19:41.216380 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9741 23:19:41.219924 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9742 23:19:41.226309 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9743 23:19:41.229644 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9744 23:19:41.232471 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9745 23:19:41.238848 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9746 23:19:41.242160 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9747 23:19:41.248982 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9748 23:19:41.252252 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9749 23:19:41.255722 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9750 23:19:41.262293 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9751 23:19:41.265416 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9752 23:19:41.269173 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9753 23:19:41.275484 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9754 23:19:41.278812 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9755 23:19:41.282268 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9756 23:19:41.288701 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9757 23:19:41.292255 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9758 23:19:41.295437 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9759 23:19:41.302225 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9760 23:19:41.305496 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9761 23:19:41.312121 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9762 23:19:41.315340 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9763 23:19:41.318776 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9764 23:19:41.325688 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9765 23:19:41.329183 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9766 23:19:41.332161 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9767 23:19:41.335321 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9768 23:19:41.338730 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9769 23:19:41.345545 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9770 23:19:41.348756 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9771 23:19:41.352429 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9772 23:19:41.355330 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9773 23:19:41.362010 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9774 23:19:41.365176 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9775 23:19:41.368872 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9776 23:19:41.375566 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9777 23:19:41.378563 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9778 23:19:41.382022 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9779 23:19:41.388089 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9780 23:19:41.391872 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9781 23:19:41.398113 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9782 23:19:41.401682 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9783 23:19:41.408613 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9784 23:19:41.411863 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9785 23:19:41.414730 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9786 23:19:41.421365 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9787 23:19:41.424824 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9788 23:19:41.431051 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9789 23:19:41.434221 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9790 23:19:41.438065 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9791 23:19:41.444626 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9792 23:19:41.448099 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9793 23:19:41.454619 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9794 23:19:41.457872 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9795 23:19:41.461250 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9796 23:19:41.468101 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9797 23:19:41.471029 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9798 23:19:41.477478 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9799 23:19:41.481333 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9800 23:19:41.484299 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9801 23:19:41.491054 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9802 23:19:41.494158 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9803 23:19:41.501359 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9804 23:19:41.504201 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9805 23:19:41.510854 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9806 23:19:41.513726 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9807 23:19:41.517392 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9808 23:19:41.524214 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9809 23:19:41.527288 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9810 23:19:41.534115 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9811 23:19:41.537270 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9812 23:19:41.540720 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9813 23:19:41.547461 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9814 23:19:41.550731 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9815 23:19:41.556987 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9816 23:19:41.560871 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9817 23:19:41.563944 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9818 23:19:41.570544 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9819 23:19:41.574044 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9820 23:19:41.580560 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9821 23:19:41.583988 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9822 23:19:41.590338 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9823 23:19:41.593568 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9824 23:19:41.597028 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9825 23:19:41.604107 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9826 23:19:41.607110 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9827 23:19:41.613794 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9828 23:19:41.616726 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9829 23:19:41.620615 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9830 23:19:41.627323 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9831 23:19:41.629837 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9832 23:19:41.636676 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9833 23:19:41.640030 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9834 23:19:41.643387 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9835 23:19:41.649769 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9836 23:19:41.653317 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9837 23:19:41.659816 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9838 23:19:41.663453 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9839 23:19:41.670072 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9840 23:19:41.673475 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9841 23:19:41.676356 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9842 23:19:41.683612 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9843 23:19:41.686538 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9844 23:19:41.690329 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9845 23:19:41.696616 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9846 23:19:41.699761 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9847 23:19:41.706319 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9848 23:19:41.709621 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9849 23:19:41.716567 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9850 23:19:41.719883 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9851 23:19:41.723592 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9852 23:19:41.730022 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9853 23:19:41.733686 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9854 23:19:41.739973 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9855 23:19:41.743312 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9856 23:19:41.749774 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9857 23:19:41.753687 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9858 23:19:41.756538 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9859 23:19:41.762760 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9860 23:19:41.766290 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9861 23:19:41.773014 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9862 23:19:41.776007 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9863 23:19:41.783394 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9864 23:19:41.786267 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9865 23:19:41.789952 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9866 23:19:41.796000 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9867 23:19:41.799781 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9868 23:19:41.806640 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9869 23:19:41.809351 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9870 23:19:41.815866 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9871 23:19:41.819400 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9872 23:19:41.825780 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9873 23:19:41.829875 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9874 23:19:41.832900 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9875 23:19:41.839615 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9876 23:19:41.842981 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9877 23:19:41.849171 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9878 23:19:41.852912 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9879 23:19:41.858949 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9880 23:19:41.862861 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9881 23:19:41.865666 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9882 23:19:41.872778 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9883 23:19:41.876004 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9884 23:19:41.882527 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9885 23:19:41.885530 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9886 23:19:41.892666 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9887 23:19:41.895706 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9888 23:19:41.899310 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9889 23:19:41.906087 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9890 23:19:41.908803 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9891 23:19:41.915570 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9892 23:19:41.919363 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9893 23:19:41.925507 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9894 23:19:41.929205 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9895 23:19:41.935540 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9896 23:19:41.938908 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9897 23:19:41.942542 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9898 23:19:41.948877 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9899 23:19:41.952018 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9900 23:19:41.958449 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9901 23:19:41.962151 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9902 23:19:41.968435 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9903 23:19:41.972168 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9904 23:19:41.978579 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9905 23:19:41.982286 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9906 23:19:41.988724 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9907 23:19:41.992320 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9908 23:19:41.995416 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9909 23:19:42.002288 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9910 23:19:42.005460 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9911 23:19:42.011967 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9912 23:19:42.015218 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9913 23:19:42.022393 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9914 23:19:42.025168 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9915 23:19:42.031903 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9916 23:19:42.035283 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9917 23:19:42.041728 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9918 23:19:42.045066 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9919 23:19:42.051732 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9920 23:19:42.055596 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9921 23:19:42.061554 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9922 23:19:42.065180 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9923 23:19:42.071854 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9924 23:19:42.075100 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9925 23:19:42.081508 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9926 23:19:42.085249 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9927 23:19:42.091786 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9928 23:19:42.095027 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9929 23:19:42.101985 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9930 23:19:42.102549 INFO: [APUAPC] vio 0
9931 23:19:42.108629 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9932 23:19:42.111723 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9933 23:19:42.114778 INFO: [APUAPC] D0_APC_0: 0x400510
9934 23:19:42.118297 INFO: [APUAPC] D0_APC_1: 0x0
9935 23:19:42.121742 INFO: [APUAPC] D0_APC_2: 0x1540
9936 23:19:42.125116 INFO: [APUAPC] D0_APC_3: 0x0
9937 23:19:42.128148 INFO: [APUAPC] D1_APC_0: 0xffffffff
9938 23:19:42.131277 INFO: [APUAPC] D1_APC_1: 0xffffffff
9939 23:19:42.134437 INFO: [APUAPC] D1_APC_2: 0x3fffff
9940 23:19:42.138113 INFO: [APUAPC] D1_APC_3: 0x0
9941 23:19:42.141508 INFO: [APUAPC] D2_APC_0: 0xffffffff
9942 23:19:42.144721 INFO: [APUAPC] D2_APC_1: 0xffffffff
9943 23:19:42.148066 INFO: [APUAPC] D2_APC_2: 0x3fffff
9944 23:19:42.151367 INFO: [APUAPC] D2_APC_3: 0x0
9945 23:19:42.154819 INFO: [APUAPC] D3_APC_0: 0xffffffff
9946 23:19:42.157814 INFO: [APUAPC] D3_APC_1: 0xffffffff
9947 23:19:42.161236 INFO: [APUAPC] D3_APC_2: 0x3fffff
9948 23:19:42.164728 INFO: [APUAPC] D3_APC_3: 0x0
9949 23:19:42.168171 INFO: [APUAPC] D4_APC_0: 0xffffffff
9950 23:19:42.171411 INFO: [APUAPC] D4_APC_1: 0xffffffff
9951 23:19:42.174977 INFO: [APUAPC] D4_APC_2: 0x3fffff
9952 23:19:42.175637 INFO: [APUAPC] D4_APC_3: 0x0
9953 23:19:42.178143 INFO: [APUAPC] D5_APC_0: 0xffffffff
9954 23:19:42.185041 INFO: [APUAPC] D5_APC_1: 0xffffffff
9955 23:19:42.185651 INFO: [APUAPC] D5_APC_2: 0x3fffff
9956 23:19:42.187901 INFO: [APUAPC] D5_APC_3: 0x0
9957 23:19:42.191006 INFO: [APUAPC] D6_APC_0: 0xffffffff
9958 23:19:42.194968 INFO: [APUAPC] D6_APC_1: 0xffffffff
9959 23:19:42.198510 INFO: [APUAPC] D6_APC_2: 0x3fffff
9960 23:19:42.201769 INFO: [APUAPC] D6_APC_3: 0x0
9961 23:19:42.205087 INFO: [APUAPC] D7_APC_0: 0xffffffff
9962 23:19:42.208034 INFO: [APUAPC] D7_APC_1: 0xffffffff
9963 23:19:42.211734 INFO: [APUAPC] D7_APC_2: 0x3fffff
9964 23:19:42.214761 INFO: [APUAPC] D7_APC_3: 0x0
9965 23:19:42.217989 INFO: [APUAPC] D8_APC_0: 0xffffffff
9966 23:19:42.221127 INFO: [APUAPC] D8_APC_1: 0xffffffff
9967 23:19:42.224561 INFO: [APUAPC] D8_APC_2: 0x3fffff
9968 23:19:42.227875 INFO: [APUAPC] D8_APC_3: 0x0
9969 23:19:42.231289 INFO: [APUAPC] D9_APC_0: 0xffffffff
9970 23:19:42.233998 INFO: [APUAPC] D9_APC_1: 0xffffffff
9971 23:19:42.238079 INFO: [APUAPC] D9_APC_2: 0x3fffff
9972 23:19:42.241430 INFO: [APUAPC] D9_APC_3: 0x0
9973 23:19:42.244262 INFO: [APUAPC] D10_APC_0: 0xffffffff
9974 23:19:42.247814 INFO: [APUAPC] D10_APC_1: 0xffffffff
9975 23:19:42.251220 INFO: [APUAPC] D10_APC_2: 0x3fffff
9976 23:19:42.254202 INFO: [APUAPC] D10_APC_3: 0x0
9977 23:19:42.257879 INFO: [APUAPC] D11_APC_0: 0xffffffff
9978 23:19:42.260784 INFO: [APUAPC] D11_APC_1: 0xffffffff
9979 23:19:42.264170 INFO: [APUAPC] D11_APC_2: 0x3fffff
9980 23:19:42.267455 INFO: [APUAPC] D11_APC_3: 0x0
9981 23:19:42.271195 INFO: [APUAPC] D12_APC_0: 0xffffffff
9982 23:19:42.274271 INFO: [APUAPC] D12_APC_1: 0xffffffff
9983 23:19:42.277142 INFO: [APUAPC] D12_APC_2: 0x3fffff
9984 23:19:42.280985 INFO: [APUAPC] D12_APC_3: 0x0
9985 23:19:42.284283 INFO: [APUAPC] D13_APC_0: 0xffffffff
9986 23:19:42.287220 INFO: [APUAPC] D13_APC_1: 0xffffffff
9987 23:19:42.290696 INFO: [APUAPC] D13_APC_2: 0x3fffff
9988 23:19:42.294285 INFO: [APUAPC] D13_APC_3: 0x0
9989 23:19:42.296912 INFO: [APUAPC] D14_APC_0: 0xffffffff
9990 23:19:42.300478 INFO: [APUAPC] D14_APC_1: 0xffffffff
9991 23:19:42.304055 INFO: [APUAPC] D14_APC_2: 0x3fffff
9992 23:19:42.307669 INFO: [APUAPC] D14_APC_3: 0x0
9993 23:19:42.311102 INFO: [APUAPC] D15_APC_0: 0xffffffff
9994 23:19:42.313978 INFO: [APUAPC] D15_APC_1: 0xffffffff
9995 23:19:42.317341 INFO: [APUAPC] D15_APC_2: 0x3fffff
9996 23:19:42.320966 INFO: [APUAPC] D15_APC_3: 0x0
9997 23:19:42.323999 INFO: [APUAPC] APC_CON: 0x4
9998 23:19:42.327276 INFO: [NOCDAPC] D0_APC_0: 0x0
9999 23:19:42.330220 INFO: [NOCDAPC] D0_APC_1: 0x0
10000 23:19:42.333772 INFO: [NOCDAPC] D1_APC_0: 0x0
10001 23:19:42.336907 INFO: [NOCDAPC] D1_APC_1: 0xfff
10002 23:19:42.340543 INFO: [NOCDAPC] D2_APC_0: 0x0
10003 23:19:42.343708 INFO: [NOCDAPC] D2_APC_1: 0xfff
10004 23:19:42.344172 INFO: [NOCDAPC] D3_APC_0: 0x0
10005 23:19:42.346612 INFO: [NOCDAPC] D3_APC_1: 0xfff
10006 23:19:42.350316 INFO: [NOCDAPC] D4_APC_0: 0x0
10007 23:19:42.353326 INFO: [NOCDAPC] D4_APC_1: 0xfff
10008 23:19:42.356709 INFO: [NOCDAPC] D5_APC_0: 0x0
10009 23:19:42.360141 INFO: [NOCDAPC] D5_APC_1: 0xfff
10010 23:19:42.363096 INFO: [NOCDAPC] D6_APC_0: 0x0
10011 23:19:42.366310 INFO: [NOCDAPC] D6_APC_1: 0xfff
10012 23:19:42.370211 INFO: [NOCDAPC] D7_APC_0: 0x0
10013 23:19:42.373187 INFO: [NOCDAPC] D7_APC_1: 0xfff
10014 23:19:42.376750 INFO: [NOCDAPC] D8_APC_0: 0x0
10015 23:19:42.377238 INFO: [NOCDAPC] D8_APC_1: 0xfff
10016 23:19:42.380071 INFO: [NOCDAPC] D9_APC_0: 0x0
10017 23:19:42.383261 INFO: [NOCDAPC] D9_APC_1: 0xfff
10018 23:19:42.386623 INFO: [NOCDAPC] D10_APC_0: 0x0
10019 23:19:42.389642 INFO: [NOCDAPC] D10_APC_1: 0xfff
10020 23:19:42.393137 INFO: [NOCDAPC] D11_APC_0: 0x0
10021 23:19:42.396207 INFO: [NOCDAPC] D11_APC_1: 0xfff
10022 23:19:42.399820 INFO: [NOCDAPC] D12_APC_0: 0x0
10023 23:19:42.402721 INFO: [NOCDAPC] D12_APC_1: 0xfff
10024 23:19:42.406341 INFO: [NOCDAPC] D13_APC_0: 0x0
10025 23:19:42.410211 INFO: [NOCDAPC] D13_APC_1: 0xfff
10026 23:19:42.412931 INFO: [NOCDAPC] D14_APC_0: 0x0
10027 23:19:42.416198 INFO: [NOCDAPC] D14_APC_1: 0xfff
10028 23:19:42.419311 INFO: [NOCDAPC] D15_APC_0: 0x0
10029 23:19:42.422737 INFO: [NOCDAPC] D15_APC_1: 0xfff
10030 23:19:42.423307 INFO: [NOCDAPC] APC_CON: 0x4
10031 23:19:42.426252 INFO: [APUAPC] set_apusys_apc done
10032 23:19:42.429734 INFO: [DEVAPC] devapc_init done
10033 23:19:42.436385 INFO: GICv3 without legacy support detected.
10034 23:19:42.439803 INFO: ARM GICv3 driver initialized in EL3
10035 23:19:42.443076 INFO: Maximum SPI INTID supported: 639
10036 23:19:42.446413 INFO: BL31: Initializing runtime services
10037 23:19:42.452805 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10038 23:19:42.456194 INFO: SPM: enable CPC mode
10039 23:19:42.459423 INFO: mcdi ready for mcusys-off-idle and system suspend
10040 23:19:42.466173 INFO: BL31: Preparing for EL3 exit to normal world
10041 23:19:42.469272 INFO: Entry point address = 0x80000000
10042 23:19:42.469838 INFO: SPSR = 0x8
10043 23:19:42.476254
10044 23:19:42.476761
10045 23:19:42.477126
10046 23:19:42.479730 Starting depthcharge on Spherion...
10047 23:19:42.480251
10048 23:19:42.480587 Wipe memory regions:
10049 23:19:42.480896
10050 23:19:42.483551 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10051 23:19:42.484060 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10052 23:19:42.484490 Setting prompt string to ['asurada:']
10053 23:19:42.484896 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10054 23:19:42.485555 [0x00000040000000, 0x00000054600000)
10055 23:19:42.605484
10056 23:19:42.606098 [0x00000054660000, 0x00000080000000)
10057 23:19:42.866320
10058 23:19:42.866901 [0x000000821a7280, 0x000000ffe64000)
10059 23:19:43.610717
10060 23:19:43.611272 [0x00000100000000, 0x00000240000000)
10061 23:19:45.500836
10062 23:19:45.504158 Initializing XHCI USB controller at 0x11200000.
10063 23:19:46.542213
10064 23:19:46.545430 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10065 23:19:46.546184
10066 23:19:46.546568
10067 23:19:46.546909
10068 23:19:46.547844 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10070 23:19:46.649270 asurada: tftpboot 192.168.201.1 12172422/tftp-deploy-gha09xov/kernel/image.itb 12172422/tftp-deploy-gha09xov/kernel/cmdline
10071 23:19:46.649993 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10072 23:19:46.650586 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10073 23:19:46.655079 tftpboot 192.168.201.1 12172422/tftp-deploy-gha09xov/kernel/image.itp-deploy-gha09xov/kernel/cmdline
10074 23:19:46.655157
10075 23:19:46.655220 Waiting for link
10076 23:19:46.815975
10077 23:19:46.816533 R8152: Initializing
10078 23:19:46.816981
10079 23:19:46.819034 Version 9 (ocp_data = 6010)
10080 23:19:46.819600
10081 23:19:46.822135 R8152: Done initializing
10082 23:19:46.822704
10083 23:19:46.823073 Adding net device
10084 23:19:48.690253
10085 23:19:48.690832 done.
10086 23:19:48.691205
10087 23:19:48.691548 MAC: 00:e0:4c:78:7a:aa
10088 23:19:48.691881
10089 23:19:48.693408 Sending DHCP discover... done.
10090 23:19:48.693968
10091 23:19:48.696589 Waiting for reply... done.
10092 23:19:48.697381
10093 23:19:48.700122 Sending DHCP request... done.
10094 23:19:48.700688
10095 23:19:48.701057 Waiting for reply... done.
10096 23:19:48.703646
10097 23:19:48.704209 My ip is 192.168.201.12
10098 23:19:48.704610
10099 23:19:48.707035 The DHCP server ip is 192.168.201.1
10100 23:19:48.707627
10101 23:19:48.709960 TFTP server IP predefined by user: 192.168.201.1
10102 23:19:48.710427
10103 23:19:48.716743 Bootfile predefined by user: 12172422/tftp-deploy-gha09xov/kernel/image.itb
10104 23:19:48.717316
10105 23:19:48.719876 Sending tftp read request... done.
10106 23:19:48.720338
10107 23:19:48.728935 Waiting for the transfer...
10108 23:19:48.729427
10109 23:19:49.052192 00000000 ################################################################
10110 23:19:49.052337
10111 23:19:49.317787 00080000 ################################################################
10112 23:19:49.317930
10113 23:19:49.610691 00100000 ################################################################
10114 23:19:49.610834
10115 23:19:49.906448 00180000 ################################################################
10116 23:19:49.906590
10117 23:19:50.181526 00200000 ################################################################
10118 23:19:50.181712
10119 23:19:50.453095 00280000 ################################################################
10120 23:19:50.453260
10121 23:19:50.722365 00300000 ################################################################
10122 23:19:50.722505
10123 23:19:51.008153 00380000 ################################################################
10124 23:19:51.008301
10125 23:19:51.300771 00400000 ################################################################
10126 23:19:51.300918
10127 23:19:51.602184 00480000 ################################################################
10128 23:19:51.602329
10129 23:19:51.905670 00500000 ################################################################
10130 23:19:51.905806
10131 23:19:52.208949 00580000 ################################################################
10132 23:19:52.209269
10133 23:19:52.609737 00600000 ################################################################
10134 23:19:52.610326
10135 23:19:53.013621 00680000 ################################################################
10136 23:19:53.014138
10137 23:19:53.324866 00700000 ################################################################
10138 23:19:53.325034
10139 23:19:53.613214 00780000 ################################################################
10140 23:19:53.613351
10141 23:19:53.899707 00800000 ################################################################
10142 23:19:53.899847
10143 23:19:54.192341 00880000 ################################################################
10144 23:19:54.192486
10145 23:19:54.491825 00900000 ################################################################
10146 23:19:54.491971
10147 23:19:54.793359 00980000 ################################################################
10148 23:19:54.793501
10149 23:19:55.084239 00a00000 ################################################################
10150 23:19:55.084376
10151 23:19:55.375955 00a80000 ################################################################
10152 23:19:55.376102
10153 23:19:55.676759 00b00000 ################################################################
10154 23:19:55.676898
10155 23:19:55.970560 00b80000 ################################################################
10156 23:19:55.970703
10157 23:19:56.263526 00c00000 ################################################################
10158 23:19:56.263666
10159 23:19:56.563860 00c80000 ################################################################
10160 23:19:56.564027
10161 23:19:56.864693 00d00000 ################################################################
10162 23:19:56.864839
10163 23:19:57.166437 00d80000 ################################################################
10164 23:19:57.166579
10165 23:19:57.451896 00e00000 ################################################################
10166 23:19:57.452040
10167 23:19:57.716205 00e80000 ################################################################
10168 23:19:57.716343
10169 23:19:58.115186 00f00000 ################################################################
10170 23:19:58.115699
10171 23:19:58.512826 00f80000 ################################################################
10172 23:19:58.513339
10173 23:19:58.940812 01000000 ################################################################
10174 23:19:58.941329
10175 23:19:59.326492 01080000 ################################################################
10176 23:19:59.326998
10177 23:19:59.727572 01100000 ################################################################
10178 23:19:59.728141
10179 23:20:00.122158 01180000 ################################################################
10180 23:20:00.122665
10181 23:20:00.521414 01200000 ################################################################
10182 23:20:00.521991
10183 23:20:00.943214 01280000 ################################################################
10184 23:20:00.943886
10185 23:20:01.380830 01300000 ################################################################
10186 23:20:01.381348
10187 23:20:01.810153 01380000 ################################################################
10188 23:20:01.810731
10189 23:20:02.209133 01400000 ################################################################
10190 23:20:02.209880
10191 23:20:02.613048 01480000 ################################################################
10192 23:20:02.613568
10193 23:20:03.006834 01500000 ################################################################
10194 23:20:03.007342
10195 23:20:03.406349 01580000 ################################################################
10196 23:20:03.406882
10197 23:20:03.840700 01600000 ################################################################
10198 23:20:03.841213
10199 23:20:04.265398 01680000 ################################################################
10200 23:20:04.265990
10201 23:20:04.679674 01700000 ################################################################
10202 23:20:04.680209
10203 23:20:05.103136 01780000 ################################################################
10204 23:20:05.103663
10205 23:20:05.522428 01800000 ################################################################
10206 23:20:05.523042
10207 23:20:05.937952 01880000 ################################################################
10208 23:20:05.938498
10209 23:20:06.362648 01900000 ################################################################
10210 23:20:06.363187
10211 23:20:06.787270 01980000 ################################################################
10212 23:20:06.787802
10213 23:20:07.219233 01a00000 ################################################################
10214 23:20:07.219763
10215 23:20:07.646063 01a80000 ################################################################
10216 23:20:07.646703
10217 23:20:08.087357 01b00000 ################################################################
10218 23:20:08.087962
10219 23:20:08.135793 01b80000 ######## done.
10220 23:20:08.136238
10221 23:20:08.139016 The bootfile was 28894162 bytes long.
10222 23:20:08.139438
10223 23:20:08.142346 Sending tftp read request... done.
10224 23:20:08.142763
10225 23:20:08.145516 Waiting for the transfer...
10226 23:20:08.146169
10227 23:20:08.146520 00000000 # done.
10228 23:20:08.146847
10229 23:20:08.155737 Command line loaded dynamically from TFTP file: 12172422/tftp-deploy-gha09xov/kernel/cmdline
10230 23:20:08.156274
10231 23:20:08.175216 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12172422/extract-nfsrootfs-n4u2o4m3,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10232 23:20:08.175738
10233 23:20:08.178387 Loading FIT.
10234 23:20:08.178807
10235 23:20:08.182194 Image ramdisk-1 has 17795503 bytes.
10236 23:20:08.182747
10237 23:20:08.183084 Image fdt-1 has 47278 bytes.
10238 23:20:08.183392
10239 23:20:08.185034 Image kernel-1 has 11049348 bytes.
10240 23:20:08.185450
10241 23:20:08.195290 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10242 23:20:08.195818
10243 23:20:08.211849 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10244 23:20:08.212383
10245 23:20:08.219040 Choosing best match conf-1 for compat google,spherion-rev2.
10246 23:20:08.222334
10247 23:20:08.227621 Connected to device vid:did:rid of 1ae0:0028:00
10248 23:20:08.234216
10249 23:20:08.237006 tpm_get_response: command 0x17b, return code 0x0
10250 23:20:08.237434
10251 23:20:08.240913 ec_init: CrosEC protocol v3 supported (256, 248)
10252 23:20:08.245485
10253 23:20:08.248940 tpm_cleanup: add release locality here.
10254 23:20:08.249363
10255 23:20:08.249744 Shutting down all USB controllers.
10256 23:20:08.250065
10257 23:20:08.252496 Removing current net device
10258 23:20:08.253016
10259 23:20:08.259264 Exiting depthcharge with code 4 at timestamp: 55063133
10260 23:20:08.259788
10261 23:20:08.262294 LZMA decompressing kernel-1 to 0x821a6718
10262 23:20:08.262716
10263 23:20:08.265729 LZMA decompressing kernel-1 to 0x40000000
10264 23:20:09.653276
10265 23:20:09.653959 jumping to kernel
10266 23:20:09.657514 end: 2.2.4 bootloader-commands (duration 00:00:27) [common]
10267 23:20:09.658323 start: 2.2.5 auto-login-action (timeout 00:03:58) [common]
10268 23:20:09.658926 Setting prompt string to ['Linux version [0-9]']
10269 23:20:09.659487 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10270 23:20:09.660037 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10271 23:20:09.736004
10272 23:20:09.738611 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10273 23:20:09.742628 start: 2.2.5.1 login-action (timeout 00:03:58) [common]
10274 23:20:09.743202 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10275 23:20:09.743607 Setting prompt string to []
10276 23:20:09.744023 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10277 23:20:09.744426 Using line separator: #'\n'#
10278 23:20:09.744771 No login prompt set.
10279 23:20:09.745111 Parsing kernel messages
10280 23:20:09.745422 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10281 23:20:09.746063 [login-action] Waiting for messages, (timeout 00:03:58)
10282 23:20:09.762028 [ 0.000000] Linux version 6.1.64-cip10-rt5 (KernelCI@build-j33605-arm64-gcc-10-defconfig-arm64-chromebook-7778h) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sun Dec 3 22:38:18 UTC 2023
10283 23:20:09.765478 [ 0.000000] random: crng init done
10284 23:20:09.772116 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10285 23:20:09.775692 [ 0.000000] efi: UEFI not found.
10286 23:20:09.781745 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10287 23:20:09.791740 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10288 23:20:09.798425 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10289 23:20:09.808472 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10290 23:20:09.814957 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10291 23:20:09.821674 [ 0.000000] printk: bootconsole [mtk8250] enabled
10292 23:20:09.828151 [ 0.000000] NUMA: No NUMA configuration found
10293 23:20:09.835275 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10294 23:20:09.838131 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10295 23:20:09.841241 [ 0.000000] Zone ranges:
10296 23:20:09.847848 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10297 23:20:09.851451 [ 0.000000] DMA32 empty
10298 23:20:09.857947 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10299 23:20:09.861238 [ 0.000000] Movable zone start for each node
10300 23:20:09.864489 [ 0.000000] Early memory node ranges
10301 23:20:09.871481 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10302 23:20:09.878074 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10303 23:20:09.884739 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10304 23:20:09.890999 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10305 23:20:09.897499 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10306 23:20:09.904448 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10307 23:20:09.960416 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10308 23:20:09.967424 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10309 23:20:09.973454 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10310 23:20:09.976794 [ 0.000000] psci: probing for conduit method from DT.
10311 23:20:09.983541 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10312 23:20:09.986966 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10313 23:20:09.993194 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10314 23:20:09.997076 [ 0.000000] psci: SMC Calling Convention v1.2
10315 23:20:10.003987 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10316 23:20:10.006512 [ 0.000000] Detected VIPT I-cache on CPU0
10317 23:20:10.013470 [ 0.000000] CPU features: detected: GIC system register CPU interface
10318 23:20:10.019904 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10319 23:20:10.026889 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10320 23:20:10.032973 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10321 23:20:10.040082 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10322 23:20:10.046657 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10323 23:20:10.053148 [ 0.000000] alternatives: applying boot alternatives
10324 23:20:10.056439 [ 0.000000] Fallback order for Node 0: 0
10325 23:20:10.063176 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10326 23:20:10.066099 [ 0.000000] Policy zone: Normal
10327 23:20:10.089749 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12172422/extract-nfsrootfs-n4u2o4m3,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10328 23:20:10.103182 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10329 23:20:10.112425 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10330 23:20:10.122784 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10331 23:20:10.129197 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10332 23:20:10.132463 <6>[ 0.000000] software IO TLB: area num 8.
10333 23:20:10.188686 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10334 23:20:10.338291 <6>[ 0.000000] Memory: 7952180K/8385536K available (17984K kernel code, 4116K rwdata, 17316K rodata, 8448K init, 615K bss, 400588K reserved, 32768K cma-reserved)
10335 23:20:10.344247 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10336 23:20:10.351412 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10337 23:20:10.354040 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10338 23:20:10.361246 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10339 23:20:10.368100 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10340 23:20:10.371035 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10341 23:20:10.380952 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10342 23:20:10.387663 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10343 23:20:10.394313 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10344 23:20:10.400810 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10345 23:20:10.404196 <6>[ 0.000000] GICv3: 608 SPIs implemented
10346 23:20:10.407382 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10347 23:20:10.414178 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10348 23:20:10.417314 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10349 23:20:10.424499 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10350 23:20:10.437454 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10351 23:20:10.447421 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10352 23:20:10.456894 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10353 23:20:10.464429 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10354 23:20:10.477836 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10355 23:20:10.484111 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10356 23:20:10.491157 <6>[ 0.009236] Console: colour dummy device 80x25
10357 23:20:10.501245 <6>[ 0.013958] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10358 23:20:10.507573 <6>[ 0.024464] pid_max: default: 32768 minimum: 301
10359 23:20:10.511434 <6>[ 0.029330] LSM: Security Framework initializing
10360 23:20:10.517733 <6>[ 0.034267] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10361 23:20:10.527552 <6>[ 0.042080] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10362 23:20:10.534395 <6>[ 0.051480] cblist_init_generic: Setting adjustable number of callback queues.
10363 23:20:10.540553 <6>[ 0.058922] cblist_init_generic: Setting shift to 3 and lim to 1.
10364 23:20:10.550894 <6>[ 0.065299] cblist_init_generic: Setting adjustable number of callback queues.
10365 23:20:10.557226 <6>[ 0.072727] cblist_init_generic: Setting shift to 3 and lim to 1.
10366 23:20:10.560827 <6>[ 0.079166] rcu: Hierarchical SRCU implementation.
10367 23:20:10.567653 <6>[ 0.079168] rcu: Max phase no-delay instances is 1000.
10368 23:20:10.574175 <6>[ 0.079192] printk: bootconsole [mtk8250] printing thread started
10369 23:20:10.580827 <6>[ 0.097504] EFI services will not be available.
10370 23:20:10.583920 <6>[ 0.097706] smp: Bringing up secondary CPUs ...
10371 23:20:10.586995 <6>[ 0.098007] Detected VIPT I-cache on CPU1
10372 23:20:10.597321 <6>[ 0.098075] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10373 23:20:10.600884 <6>[ 0.098108] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10374 23:20:10.612719 <6>[ 0.125933] Detected VIPT I-cache on CPU2
10375 23:20:10.619483 <6>[ 0.125981] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10376 23:20:10.625923 <6>[ 0.125996] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10377 23:20:10.632516 <6>[ 0.126251] Detected VIPT I-cache on CPU3
10378 23:20:10.639434 <6>[ 0.126296] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10379 23:20:10.646163 <6>[ 0.126309] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10380 23:20:10.648989 <6>[ 0.126618] CPU features: detected: Spectre-v4
10381 23:20:10.655415 <6>[ 0.126624] CPU features: detected: Spectre-BHB
10382 23:20:10.658662 <6>[ 0.126628] Detected PIPT I-cache on CPU4
10383 23:20:10.665725 <6>[ 0.126687] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10384 23:20:10.671741 <6>[ 0.126704] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10385 23:20:10.678846 <6>[ 0.126997] Detected PIPT I-cache on CPU5
10386 23:20:10.685134 <6>[ 0.127057] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10387 23:20:10.691898 <6>[ 0.127074] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10388 23:20:10.694911 <6>[ 0.127350] Detected PIPT I-cache on CPU6
10389 23:20:10.705531 <6>[ 0.127413] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10390 23:20:10.712026 <6>[ 0.127429] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10391 23:20:10.715536 <6>[ 0.127720] Detected PIPT I-cache on CPU7
10392 23:20:10.721799 <6>[ 0.127785] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10393 23:20:10.728843 <6>[ 0.127802] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10394 23:20:10.732200 <6>[ 0.127848] smp: Brought up 1 node, 8 CPUs
10395 23:20:10.738748 <6>[ 0.127853] SMP: Total of 8 processors activated.
10396 23:20:10.742300 <6>[ 0.127856] CPU features: detected: 32-bit EL0 Support
10397 23:20:10.751662 <6>[ 0.127858] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10398 23:20:10.758704 <6>[ 0.127860] CPU features: detected: Common not Private translations
10399 23:20:10.765205 <6>[ 0.127862] CPU features: detected: CRC32 instructions
10400 23:20:10.768590 <6>[ 0.127865] CPU features: detected: RCpc load-acquire (LDAPR)
10401 23:20:10.775098 <6>[ 0.127866] CPU features: detected: LSE atomic instructions
10402 23:20:10.781801 <6>[ 0.127868] CPU features: detected: Privileged Access Never
10403 23:20:10.788899 <6>[ 0.127869] CPU features: detected: RAS Extension Support
10404 23:20:10.795282 <6>[ 0.127872] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10405 23:20:10.798191 <6>[ 0.127940] CPU: All CPU(s) started at EL2
10406 23:20:10.804745 <6>[ 0.127941] alternatives: applying system-wide alternatives
10407 23:20:10.808159 <6>[ 0.141068] devtmpfs: initialized
10408 23:20:10.818092 <6>[ 0.147273] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10409 23:20:10.846626 ���U���ѕɕ���}%9Q��ɽѽ����������5R�<6>[ < 0.364879] printk: console [ttyS0] printing thread started
10410 23:20:10.853444 6<6>[ 0.364923] printk: console [ttyS0] enabled
10411 23:20:10.859824 >[ 0.228689] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10412 23:20:10.867074 <6>[ 0.364927] printk: bootconsole [mtk8250] disabled
10413 23:20:10.873785 <6>[ 0.382989] printk: bootconsole [mtk8250] printing thread stopped
10414 23:20:10.877258 <6>[ 0.384002] SuperH (H)SCI(F) driver initialized
10415 23:20:10.883659 <6>[ 0.384478] msm_serial: driver initialized
10416 23:20:10.889984 <6>[ 0.389044] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10417 23:20:10.900203 <6>[ 0.389072] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10418 23:20:10.907011 <6>[ 0.389102] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10419 23:20:10.922574 <6>[ 0.389132] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10420 23:20:10.929243 <6>[ 0.389154] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10421 23:20:10.935023 <6>[ 0.389181] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10422 23:20:10.955090 <6>[ 0.389209] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10423 23:20:10.955661 <6>[ 0.389330] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10424 23:20:10.965665 <6>[ 0.389361] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10425 23:20:10.966251 <6>[ 0.400177] loop: module loaded
10426 23:20:10.974572 <6>[ 0.402838] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10427 23:20:10.977763 <4>[ 0.419475] mtk-pmic-keys: Failed to locate of_node [id: -1]
10428 23:20:10.981115 <6>[ 0.420296] megasas: 07.719.03.00-rc1
10429 23:20:10.987616 <6>[ 0.432688] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10430 23:20:10.990637 <6>[ 0.432787] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10431 23:20:10.997401 <6>[ 0.444647] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10432 23:20:11.007257 <6>[ 0.497747] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10433 23:20:11.487399 <6>[ 1.003828] Freeing initrd memory: 17372K
10434 23:20:11.495462 <6>[ 1.009980] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10435 23:20:11.501532 <6>[ 1.014625] tun: Universal TUN/TAP device driver, 1.6
10436 23:20:11.505538 <6>[ 1.015383] thunder_xcv, ver 1.0
10437 23:20:11.508298 <6>[ 1.015400] thunder_bgx, ver 1.0
10438 23:20:11.511792 <6>[ 1.015416] nicpf, ver 1.0
10439 23:20:11.518074 <6>[ 1.016457] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10440 23:20:11.524838 <6>[ 1.016460] hns3: Copyright (c) 2017 Huawei Corporation.
10441 23:20:11.528074 <6>[ 1.016485] hclge is initializing
10442 23:20:11.535020 <6>[ 1.016503] e1000: Intel(R) PRO/1000 Network Driver
10443 23:20:11.538273 <6>[ 1.016505] e1000: Copyright (c) 1999-2006 Intel Corporation.
10444 23:20:11.546064 <6>[ 1.016525] e1000e: Intel(R) PRO/1000 Network Driver
10445 23:20:11.549463 <6>[ 1.016526] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10446 23:20:11.556446 <6>[ 1.016542] igb: Intel(R) Gigabit Ethernet Network Driver
10447 23:20:11.563373 <6>[ 1.016544] igb: Copyright (c) 2007-2014 Intel Corporation.
10448 23:20:11.570090 <6>[ 1.016557] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10449 23:20:11.573616 <6>[ 1.016559] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10450 23:20:11.576801 <6>[ 1.016853] sky2: driver version 1.30
10451 23:20:11.583261 <6>[ 1.017918] VFIO - User Level meta-driver version: 0.3
10452 23:20:11.589917 <6>[ 1.020725] usbcore: registered new interface driver usb-storage
10453 23:20:11.596837 <6>[ 1.020902] usbcore: registered new device driver onboard-usb-hub
10454 23:20:11.603445 <6>[ 1.023657] mt6397-rtc mt6359-rtc: registered as rtc0
10455 23:20:11.609950 <6>[ 1.023809] mt6397-rtc mt6359-rtc: setting system clock to 2023-12-03T23:17:57 UTC (1701645477)
10456 23:20:11.616931 <6>[ 1.024417] i2c_dev: i2c /dev entries driver
10457 23:20:11.623398 <6>[ 1.031611] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10458 23:20:11.626308 <6>[ 1.047584] cpu cpu0: EM: created perf domain
10459 23:20:11.633237 <6>[ 1.047913] cpu cpu4: EM: created perf domain
10460 23:20:11.640146 <6>[ 1.051491] sdhci: Secure Digital Host Controller Interface driver
10461 23:20:11.643115 <6>[ 1.051493] sdhci: Copyright(c) Pierre Ossman
10462 23:20:11.649932 <6>[ 1.051839] Synopsys Designware Multimedia Card Interface Driver
10463 23:20:11.656291 <6>[ 1.052224] sdhci-pltfm: SDHCI platform and OF driver helper
10464 23:20:11.663111 <6>[ 1.056502] ledtrig-cpu: registered to indicate activity on CPUs
10465 23:20:11.666354 <6>[ 1.057180] mmc0: CQHCI version 5.10
10466 23:20:11.673443 <6>[ 1.057194] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10467 23:20:11.680096 <6>[ 1.057477] usbcore: registered new interface driver usbhid
10468 23:20:11.683478 <6>[ 1.057478] usbhid: USB HID core driver
10469 23:20:11.689954 <6>[ 1.057589] spi_master spi0: will run message pump with realtime priority
10470 23:20:11.703366 <6>[ 1.088855] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10471 23:20:11.716335 <6>[ 1.091011] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10472 23:20:11.719290 <6>[ 1.091867] cros-ec-spi spi0.0: Chrome EC device registered
10473 23:20:11.729262 <6>[ 1.108737] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10474 23:20:11.736044 <6>[ 1.111253] NET: Registered PF_PACKET protocol family
10475 23:20:11.739789 <6>[ 1.111347] 9pnet: Installing 9P2000 support
10476 23:20:11.746072 <5>[ 1.111387] Key type dns_resolver registered
10477 23:20:11.749819 <6>[ 1.111816] registered taskstats version 1
10478 23:20:11.753114 <5>[ 1.111835] Loading compiled-in X.509 certificates
10479 23:20:11.766425 <4>[ 1.134051] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10480 23:20:11.776871 <4>[ 1.134218] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10481 23:20:11.783689 <3>[ 1.134227] debugfs: File 'uA_load' in directory '/' already present!
10482 23:20:11.789864 <3>[ 1.134235] debugfs: File 'min_uV' in directory '/' already present!
10483 23:20:11.796235 <3>[ 1.134238] debugfs: File 'max_uV' in directory '/' already present!
10484 23:20:11.802783 <3>[ 1.134241] debugfs: File 'constraint_flags' in directory '/' already present!
10485 23:20:11.809648 <3>[ 1.136232] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10486 23:20:11.816624 <6>[ 1.143363] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10487 23:20:11.822874 <6>[ 1.144006] xhci-mtk 11200000.usb: xHCI Host Controller
10488 23:20:11.829505 <6>[ 1.144028] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10489 23:20:11.839405 <6>[ 1.144266] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10490 23:20:11.845966 <6>[ 1.144315] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10491 23:20:11.852882 <6>[ 1.144419] xhci-mtk 11200000.usb: xHCI Host Controller
10492 23:20:11.859866 <6>[ 1.144428] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10493 23:20:11.865970 <6>[ 1.144437] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10494 23:20:11.870188 <6>[ 1.145018] hub 1-0:1.0: USB hub found
10495 23:20:11.873069 <6>[ 1.145040] hub 1-0:1.0: 1 port detected
10496 23:20:11.882714 <6>[ 1.145212] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10497 23:20:11.885858 <6>[ 1.145575] hub 2-0:1.0: USB hub found
10498 23:20:11.889553 <6>[ 1.145658] hub 2-0:1.0: 1 port detected
10499 23:20:11.896369 <6>[ 1.149254] mtk-msdc 11f70000.mmc: Got CD GPIO
10500 23:20:11.899488 <6>[ 1.151495] mmc0: Command Queue Engine enabled
10501 23:20:11.906296 <6>[ 1.151518] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10502 23:20:11.912497 <6>[ 1.152074] mmcblk0: mmc0:0001 DA4128 116 GiB
10503 23:20:11.916150 <6>[ 1.156410] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10504 23:20:11.926811 <6>[ 1.157963] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10505 23:20:11.933135 <6>[ 1.157972] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10506 23:20:11.943137 <4>[ 1.158050] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10507 23:20:11.950271 <6>[ 1.158544] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10508 23:20:11.959926 <6>[ 1.158545] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10509 23:20:11.962941 <6>[ 1.158589] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10510 23:20:11.972848 <6>[ 1.158699] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10511 23:20:11.979210 <6>[ 1.158710] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10512 23:20:11.985828 <6>[ 1.158713] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10513 23:20:11.995841 <6>[ 1.158722] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10514 23:20:12.002310 <6>[ 1.160048] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10515 23:20:12.008947 <6>[ 1.160353] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10516 23:20:12.018622 <6>[ 1.160369] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10517 23:20:12.025217 <6>[ 1.160372] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10518 23:20:12.035302 <6>[ 1.160376] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10519 23:20:12.042128 <6>[ 1.160380] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10520 23:20:12.052030 <6>[ 1.160383] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10521 23:20:12.058337 <6>[ 1.160387] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10522 23:20:12.068672 <6>[ 1.160391] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10523 23:20:12.075286 <6>[ 1.160394] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10524 23:20:12.085025 <6>[ 1.160397] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10525 23:20:12.091895 <6>[ 1.160401] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10526 23:20:12.101166 <6>[ 1.160404] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10527 23:20:12.111112 <6>[ 1.160408] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10528 23:20:12.117726 <6>[ 1.160412] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10529 23:20:12.127904 <6>[ 1.160416] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10530 23:20:12.134336 <6>[ 1.160899] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10531 23:20:12.141021 <6>[ 1.161237] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10532 23:20:12.144112 <6>[ 1.161700] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10533 23:20:12.151324 <6>[ 1.161956] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10534 23:20:12.157731 <6>[ 1.162209] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10535 23:20:12.164266 <6>[ 1.162464] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10536 23:20:12.174534 <6>[ 1.162633] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10537 23:20:12.183934 <6>[ 1.162642] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10538 23:20:12.194359 <6>[ 1.162646] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10539 23:20:12.203964 <6>[ 1.162650] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10540 23:20:12.213815 <6>[ 1.162654] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10541 23:20:12.220258 <6>[ 1.162657] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10542 23:20:12.230489 <6>[ 1.162659] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10543 23:20:12.239911 <6>[ 1.162662] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10544 23:20:12.250070 <6>[ 1.162664] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10545 23:20:12.260111 <6>[ 1.162668] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10546 23:20:12.269842 <6>[ 1.162671] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10547 23:20:12.277021 <6>[ 1.163466] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10548 23:20:12.283486 <6>[ 1.188738] Trying to probe devices needed for running init ...
10549 23:20:12.289991 <6>[ 1.581435] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10550 23:20:12.293002 <6>[ 1.734144] hub 1-1:1.0: USB hub found
10551 23:20:12.299639 <6>[ 1.734550] hub 1-1:1.0: 4 ports detected
10552 23:20:12.303426 <6>[ 1.737773] hub 1-1:1.0: USB hub found
10553 23:20:12.306786 <6>[ 1.738047] hub 1-1:1.0: 4 ports detected
10554 23:20:12.350213 <6>[ 1.861744] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10555 23:20:12.370819 <6>[ 1.888406] hub 2-1:1.0: USB hub found
10556 23:20:12.374253 <6>[ 1.888791] hub 2-1:1.0: 3 ports detected
10557 23:20:12.377890 <6>[ 1.891933] hub 2-1:1.0: USB hub found
10558 23:20:12.380880 <6>[ 1.892282] hub 2-1:1.0: 3 ports detected
10559 23:20:12.538445 <6>[ 2.049604] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10560 23:20:12.658618 <6>[ 2.176563] hub 1-1.4:1.0: USB hub found
10561 23:20:12.661868 <6>[ 2.176900] hub 1-1.4:1.0: 2 ports detected
10562 23:20:12.665752 <6>[ 2.179695] hub 1-1.4:1.0: USB hub found
10563 23:20:12.672087 <6>[ 2.180019] hub 1-1.4:1.0: 2 ports detected
10564 23:20:12.742385 <6>[ 2.253814] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10565 23:20:12.957998 <6>[ 2.469577] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10566 23:20:13.142269 <6>[ 2.653582] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10567 23:20:23.954251 <6>[ 13.474580] ALSA device list:
10568 23:20:23.960886 <6>[ 13.474602] No soundcards found.
10569 23:20:23.964346 <6>[ 13.479052] Freeing unused kernel memory: 8448K
10570 23:20:23.967886 <6>[ 13.479217] Run /init as init process
10571 23:20:23.970553 Loading, please wait...
10572 23:20:23.995022 Starting version 247.3-7+deb11u2
10573 23:20:24.200702 <6>[ 13.715669] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10574 23:20:24.204550 <6>[ 13.721631] remoteproc remoteproc0: scp is available
10575 23:20:24.210632 <6>[ 13.721832] remoteproc remoteproc0: powering up scp
10576 23:20:24.217765 <6>[ 13.721846] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10577 23:20:24.225217 <6>[ 13.721911] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10578 23:20:24.248789 <6>[ 13.764491] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10579 23:20:24.255597 <6>[ 13.764534] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10580 23:20:24.265749 <6>[ 13.764546] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10581 23:20:24.272104 <4>[ 13.773673] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10582 23:20:24.278619 <4>[ 13.773868] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10583 23:20:24.285385 <6>[ 13.792315] mc: Linux media interface: v0.10
10584 23:20:24.292132 <3>[ 13.796343] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10585 23:20:24.301564 <3>[ 13.796373] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10586 23:20:24.308603 <3>[ 13.796381] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10587 23:20:24.318508 <3>[ 13.797392] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10588 23:20:24.325187 <3>[ 13.797405] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10589 23:20:24.332078 <3>[ 13.797412] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10590 23:20:24.342361 <3>[ 13.797421] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10591 23:20:24.349090 <3>[ 13.797428] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10592 23:20:24.356442 <3>[ 13.798135] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10593 23:20:24.365926 <3>[ 13.798256] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10594 23:20:24.372849 <3>[ 13.798265] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10595 23:20:24.382433 <3>[ 13.798272] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10596 23:20:24.389751 <3>[ 13.798367] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10597 23:20:24.399092 <3>[ 13.798374] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10598 23:20:24.405747 <3>[ 13.798383] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10599 23:20:24.412365 <3>[ 13.798393] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10600 23:20:24.421932 <3>[ 13.798405] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10601 23:20:24.428844 <3>[ 13.798455] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10602 23:20:24.439042 <6>[ 13.800182] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10603 23:20:24.441876 <6>[ 13.818548] usbcore: registered new interface driver r8152
10604 23:20:24.452259 <4>[ 13.830413] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10605 23:20:24.458542 <4>[ 13.830413] Fallback method does not support PEC.
10606 23:20:24.465416 <6>[ 13.847472] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10607 23:20:24.471860 <6>[ 13.847532] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10608 23:20:24.478466 <6>[ 13.847539] remoteproc remoteproc0: remote processor scp is now up
10609 23:20:24.488562 <3>[ 13.847784] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10610 23:20:24.495108 <6>[ 13.859187] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10611 23:20:24.505340 <6>[ 13.860753] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10612 23:20:24.511826 <3>[ 13.876524] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10613 23:20:24.521527 <6>[ 13.880035] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10614 23:20:24.528145 <6>[ 13.887518] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10615 23:20:24.534921 <6>[ 13.887526] pci_bus 0000:00: root bus resource [bus 00-ff]
10616 23:20:24.541349 <6>[ 13.887534] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10617 23:20:24.551540 <6>[ 13.887538] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10618 23:20:24.558230 <6>[ 13.887575] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10619 23:20:24.564713 <6>[ 13.887599] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10620 23:20:24.571333 <6>[ 13.887689] pci 0000:00:00.0: supports D1 D2
10621 23:20:24.578113 <6>[ 13.887692] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10622 23:20:24.585232 <6>[ 13.889378] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10623 23:20:24.591120 <6>[ 13.889506] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10624 23:20:24.598399 <6>[ 13.889538] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10625 23:20:24.607903 <6>[ 13.889562] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10626 23:20:24.614448 <6>[ 13.889580] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10627 23:20:24.617548 <6>[ 13.889711] pci 0000:01:00.0: supports D1 D2
10628 23:20:24.625106 <6>[ 13.889714] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10629 23:20:24.631043 <6>[ 13.897853] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10630 23:20:24.641631 <6>[ 13.905443] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10631 23:20:24.647864 <6>[ 13.905478] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10632 23:20:24.654582 <6>[ 13.905485] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10633 23:20:24.663992 <6>[ 13.905498] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10634 23:20:24.670594 <6>[ 13.905515] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10635 23:20:24.680758 <6>[ 13.905531] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10636 23:20:24.684371 <6>[ 13.905548] pci 0000:00:00.0: PCI bridge to [bus 01]
10637 23:20:24.694513 <6>[ 13.905556] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10638 23:20:24.701069 <6>[ 13.905691] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10639 23:20:24.704020 <6>[ 13.906739] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10640 23:20:24.710561 <6>[ 13.907162] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10641 23:20:24.720618 <6>[ 13.918303] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10642 23:20:24.730710 <6>[ 13.918691] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10643 23:20:24.741144 <4>[ 13.922034] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10644 23:20:24.747311 <4>[ 13.922060] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10645 23:20:24.753694 <6>[ 13.939986] videodev: Linux video capture interface: v2.00
10646 23:20:24.760510 <6>[ 13.940060] usbcore: registered new interface driver cdc_ether
10647 23:20:24.767179 <5>[ 13.942049] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10648 23:20:24.773796 <6>[ 13.947151] usbcore: registered new interface driver r8153_ecm
10649 23:20:24.780172 <5>[ 13.952421] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10650 23:20:24.790736 <4>[ 13.952498] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10651 23:20:24.793967 <6>[ 13.952507] cfg80211: failed to load regulatory.db
10652 23:20:24.797004 <6>[ 13.977617] r8152 2-1.3:1.0 eth0: v1.12.13
10653 23:20:24.800291 <6>[ 13.983402] Bluetooth: Core ver 2.22
10654 23:20:24.807467 <6>[ 13.983467] r8152 2-1.3:1.0 enx00e04c787aaa: renamed from eth0
10655 23:20:24.813819 <6>[ 13.983505] NET: Registered PF_BLUETOOTH protocol family
10656 23:20:24.820624 <6>[ 13.983508] Bluetooth: HCI device and connection manager initialized
10657 23:20:24.823920 <6>[ 13.983536] Bluetooth: HCI socket layer initialized
10658 23:20:24.830230 <6>[ 13.983553] Bluetooth: L2CAP socket layer initialized
10659 23:20:24.836691 <6>[ 13.983579] Bluetooth: SCO socket layer initialized
10660 23:20:24.843798 <6>[ 13.999222] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10661 23:20:24.853713 <6>[ 14.000417] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10662 23:20:24.859806 <6>[ 14.000500] usbcore: registered new interface driver uvcvideo
10663 23:20:24.867212 <6>[ 14.038561] usbcore: registered new interface driver btusb
10664 23:20:24.876874 <4>[ 14.039738] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10665 23:20:24.883328 <3>[ 14.039748] Bluetooth: hci0: Failed to load firmware file (-2)
10666 23:20:24.890491 <3>[ 14.039750] Bluetooth: hci0: Failed to set up firmware (-2)
10667 23:20:24.899887 <4>[ 14.039753] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10668 23:20:24.906515 <6>[ 14.047987] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10669 23:20:24.913760 <6>[ 14.311106] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10670 23:20:24.919389 <6>[ 14.311201] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10671 23:20:24.926071 <6>[ 14.329454] mt7921e 0000:01:00.0: ASIC revision: 79610010
10672 23:20:24.935824 <4>[ 14.428917] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10673 23:20:24.939266 Begin: Loading essential drivers ... done.
10674 23:20:24.946139 Begin: Running /scripts/init-premount ... done.
10675 23:20:24.953050 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10676 23:20:24.959687 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10677 23:20:24.966051 Device /sys/class/net/enx00e04c787aaa found
10678 23:20:24.966612 done.
10679 23:20:25.028540 <4>[ 14.539946] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10680 23:20:25.035608 IP-Config: enx00e04c787aaa hardware address 00:e0:4c:78:7a:aa mtu 1500 DHCP
10681 23:20:25.136415 <4>[ 14.646765] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10682 23:20:25.240235 <4>[ 14.750465] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10683 23:20:25.344731 <4>[ 14.854392] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10684 23:20:25.448465 <4>[ 14.958309] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10685 23:20:25.552225 <4>[ 15.062263] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10686 23:20:25.656620 <4>[ 15.166264] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10687 23:20:25.760685 <4>[ 15.270417] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10688 23:20:25.864112 <4>[ 15.374284] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10689 23:20:25.957744 <3>[ 15.476162] mt7921e 0000:01:00.0: hardware init failed
10690 23:20:26.161439 <6>[ 15.678249] r8152 2-1.3:1.0 enx00e04c787aaa: carrier on
10691 23:20:27.003898 IP-Config: no response after 2 secs - giving up
10692 23:20:27.044706 IP-Config: enx00e04c787aaa hardware address 00:e0:4c:78:7a:aa mtu 1500 DHCP
10693 23:20:27.048117 IP-Config: enx00e04c787aaa complete (dhcp from 192.168.201.1):
10694 23:20:27.055211 address: 192.168.201.12 broadcast: 192.168.201.255 netmask: 255.255.255.0
10695 23:20:27.061510 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10696 23:20:27.068051 host : mt8192-asurada-spherion-r0-cbg-0
10697 23:20:27.074976 domain : lava-rack
10698 23:20:27.080797 rootserver: 192.168.201.1 rootpath:
10699 23:20:27.081704 filename :
10700 23:20:27.213291 done.
10701 23:20:27.220876 Begin: Running /scripts/nfs-bottom ... done.
10702 23:20:27.241162 Begin: Running /scripts/init-bottom ... done.
10703 23:20:28.428936 <6>[ 17.947330] NET: Registered PF_INET6 protocol family
10704 23:20:28.431867 <6>[ 17.949221] Segment Routing with IPv6
10705 23:20:28.438848 <6>[ 17.949248] In-situ OAM (IOAM) with IPv6
10706 23:20:28.545774 <30>[ 18.047457] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10707 23:20:28.552328 <30>[ 18.048452] systemd[1]: Detected architecture arm64.
10708 23:20:28.552867
10709 23:20:28.559369 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10710 23:20:28.559876
10711 23:20:28.576770 <30>[ 18.096103] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10712 23:20:29.428355 <30>[ 18.944248] systemd[1]: Queued start job for default target Graphical Interface.
10713 23:20:29.475888 [[0;32m OK [<30>[ 18.991939] systemd[1]: Created slice system-getty.slice.
10714 23:20:29.478560 0m] Created slice [0;1;39msystem-getty.slice[0m.
10715 23:20:29.498470 [[0;32m OK [0m] Created slic<30>[ 19.014918] systemd[1]: Created slice system-modprobe.slice.
10716 23:20:29.500932 e [0;1;39msystem-modprobe.slice[0m.
10717 23:20:29.522252 [[0;32m OK [0m] Created slic<30>[ 19.038764] systemd[1]: Created slice system-serial\x2dgetty.slice.
10718 23:20:29.528467 e [0;1;39msystem-serial\x2dgetty.slice[0m.
10719 23:20:29.546603 [[0;32m OK [0m] Created slic<30>[ 19.063425] systemd[1]: Created slice User and Session Slice.
10720 23:20:29.549984 e [0;1;39mUser and Session Slice[0m.
10721 23:20:29.572697 [[0;32m OK [0m] Started [0;1;39mDispatch Pa<30>[ 19.085954] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10722 23:20:29.575859 ssword …ts to Console Directory Watch[0m.
10723 23:20:29.600283 [[0;32m OK [0m] Started [0;1;39mForward Pas<30>[ 19.113796] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10724 23:20:29.603313 sword R…uests to Wall Directory Watch[0m.
10725 23:20:29.627373 [[0;32m OK [0m] Reached target [0;1;39mLoca<30>[ 19.137703] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10726 23:20:29.634296 <30>[ 19.137887] systemd[1]: Reached target Local Encrypted Volumes.
10727 23:20:29.637510 l Encrypted Volumes[0m.
10728 23:20:29.656917 [[0;32m OK [0m] Reached target [0;1;39mPath<30>[ 19.173680] systemd[1]: Reached target Paths.
10729 23:20:29.657488 s[0m.
10730 23:20:29.680183 [[0;32m OK [0m] Reached target [0;1;39mRemo<30>[ 19.193584] systemd[1]: Reached target Remote File Systems.
10731 23:20:29.680752 te File Systems[0m.
10732 23:20:29.700502 [[0;32m OK [0m] Reached target [0;1;39mSlic<30>[ 19.217549] systemd[1]: Reached target Slices.
10733 23:20:29.701050 es[0m.
10734 23:20:29.720811 [[0;32m OK [0m] Reached target [0;1;39mSwap<30>[ 19.237575] systemd[1]: Reached target Swap.
10735 23:20:29.721367 [0m.
10736 23:20:29.744699 [[0;32m OK [0m] Listening on [0;1;39minitct<30>[ 19.257964] systemd[1]: Listening on initctl Compatibility Named Pipe.
10737 23:20:29.747450 l Compatibility Named Pipe[0m.
10738 23:20:29.757947 [[0;32m OK [0m] Listening on [0;1;39mJourna<30>[ 19.274005] systemd[1]: Listening on Journal Audit Socket.
10739 23:20:29.760792 l Audit Socket[0m.
10740 23:20:29.782340 [[0;32m OK [0m] Listening on<30>[ 19.298935] systemd[1]: Listening on Journal Socket (/dev/log).
10741 23:20:29.785785 [0;1;39mJournal Socket (/dev/log)[0m.
10742 23:20:29.806409 [[0;32m OK [0m] Listening on<30>[ 19.322894] systemd[1]: Listening on Journal Socket.
10743 23:20:29.809249 [0;1;39mJournal Socket[0m.
10744 23:20:29.826804 [[0;32m OK [0m] Listening on<30>[ 19.343426] systemd[1]: Listening on Network Service Netlink Socket.
10745 23:20:29.833215 [0;1;39mNetwork Service Netlink Socket[0m.
10746 23:20:29.852746 [[0;32m OK [0m] Listening on [0;1;39mudev C<30>[ 19.369558] systemd[1]: Listening on udev Control Socket.
10747 23:20:29.856152 ontrol Socket[0m.
10748 23:20:29.873452 [[0;32m OK [0m] Listening on [0;1;39mudev K<30>[ 19.390051] systemd[1]: Listening on udev Kernel Socket.
10749 23:20:29.876588 ernel Socket[0m.
10750 23:20:29.920860 Mounting [0;1;39mHuge Pages File Syste<30>[ 19.437928] systemd[1]: Mounting Huge Pages File System...
10751 23:20:29.923905 m[0m...
10752 23:20:29.945613 Mounting [0;1;39mPOSIX<30>[ 19.462914] systemd[1]: Mounting POSIX Message Queue File System...
10753 23:20:29.948528 Message Queue File System[0m...
10754 23:20:29.970958 Mountin<30>[ 19.488578] systemd[1]: Mounting Kernel Debug File System...
10755 23:20:29.974491 g [0;1;39mKernel Debug File System[0m...
10756 23:20:29.995685 <30>[ 19.510387] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10757 23:20:30.005854 <30>[ 19.518793] systemd[1]: Starting Create list of static device nodes for the current kernel...
10758 23:20:30.011979 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10759 23:20:30.040217 Starting [0;1;39mLoad Kernel Module co<30>[ 19.553852] systemd[1]: Starting Load Kernel Module configfs...
10760 23:20:30.040819 nfigfs[0m...
10761 23:20:30.061471 Starting [0;1;39mLoad <30>[ 19.578293] systemd[1]: Starting Load Kernel Module drm...
10762 23:20:30.064560 Kernel Module drm[0m...
10763 23:20:30.085712 Starting [0;1;39mLoad <30>[ 19.602248] systemd[1]: Starting Load Kernel Module fuse...
10764 23:20:30.088660 Kernel Module fuse[0m...
10765 23:20:30.120946 <6>[ 19.640523] fuse: init (API version 7.37)
10766 23:20:30.130800 <30>[ 19.641054] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10767 23:20:30.142198 Starting [0;1;39mJourn<30>[ 19.659076] systemd[1]: Starting Journal Service...
10768 23:20:30.142756 al Service[0m...
10769 23:20:30.172422 Startin<30>[ 19.689036] systemd[1]: Starting Load Kernel Modules...
10770 23:20:30.175944 g [0;1;39mLoad Kernel Modules[0m...
10771 23:20:30.199402 Startin<30>[ 19.716203] systemd[1]: Starting Remount Root and Kernel File Systems...
10772 23:20:30.205442 g [0;1;39mRemount Root and Kernel File Systems[0m...
10773 23:20:30.226184 Starting [0;1;39mColdp<30>[ 19.743174] systemd[1]: Starting Coldplug All udev Devices...
10774 23:20:30.229681 lug All udev Devices[0m...
10775 23:20:30.253572 [[0;32m OK [0m] Mounted [0;<30>[ 19.770731] systemd[1]: Mounted Huge Pages File System.
10776 23:20:30.256732 1;39mHuge Pages File System[0m.
10777 23:20:30.271541 <3>[ 19.786736] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10778 23:20:30.282634 [[0;32m OK [0m] Mounted [0;<30>[ 19.798875] systemd[1]: Mounted POSIX Message Queue File System.
10779 23:20:30.292324 1;39mPOSIX Messa<3>[ 19.807073] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10780 23:20:30.295645 ge Queue File System[0m.
10781 23:20:30.313324 [[0;32m OK [0m] Mounted [0;<30>[ 19.830635] systemd[1]: Mounted Kernel Debug File System.
10782 23:20:30.316469 1;39mKernel Debug File System[0m.
10783 23:20:30.331382 <3>[ 19.846019] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10784 23:20:30.351657 <3>[ 19.867544] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10785 23:20:30.365504 [[0;32m OK [0m] Finished [0;1;39mCreate lis<30>[ 19.878446] systemd[1]: Finished Create list of static device nodes for the current kernel.
10786 23:20:30.375584 t of st… nodes<3>[ 19.888218] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10787 23:20:30.378833 for the current kernel[0m.
10788 23:20:30.395915 <3>[ 19.909837] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10789 23:20:30.405308 <30>[ 19.924135] systemd[1]: modprobe@configfs.service: Succeeded.
10790 23:20:30.412119 <30>[ 19.925726] systemd[1]: Finished Load Kernel Module configfs.
10791 23:20:30.425688 [[0;32m OK [0m] Finished [0;1;39mLoad Kerne<3>[ 19.935031] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10792 23:20:30.428740 l Module configfs[0m.
10793 23:20:30.440589 <3>[ 19.956613] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10794 23:20:30.451776 [[0;32m OK [<30>[ 19.967331] systemd[1]: modprobe@drm.service: Succeeded.
10795 23:20:30.458142 0m] Finished [0<30>[ 19.968087] systemd[1]: Finished Load Kernel Module drm.
10796 23:20:30.467938 ;1;39mLoad Kerne<3>[ 19.977432] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10797 23:20:30.468487 l Module drm[0m.
10798 23:20:30.492540 <3>[ 20.007502] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10799 23:20:30.502913 [[0;32m OK [0m] Finished [0;1;39mLoad Kerne<30>[ 20.010533] systemd[1]: modprobe@fuse.service: Succeeded.
10800 23:20:30.509692 l Module fuse[0<30>[ 20.011305] systemd[1]: Finished Load Kernel Module fuse.
10801 23:20:30.510171 m.
10802 23:20:30.534618 [[0;32m OK [0m] Finished [0<30>[ 20.051149] systemd[1]: Finished Load Kernel Modules.
10803 23:20:30.537505 ;1;39mLoad Kernel Modules[0m.
10804 23:20:30.557250 [[0;32m OK [0m] Started [0;1;39mJournal Ser<30>[ 20.074090] systemd[1]: Started Journal Service.
10805 23:20:30.560529 vice[0m.
10806 23:20:30.584122 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10807 23:20:30.624222 Mounting [0;1;39mFUSE Control File System[0m...
10808 23:20:30.646603 Mounting [0;1;39mKernel Configuration File System[0m...
10809 23:20:30.672679 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10810 23:20:30.694599 Starting [0;1;39mLoad/Save Random Seed[0m...
10811 23:20:30.720588 Starting [0;1;39mApply<46>[ 20.237132] systemd-journald[310]: Received client request to flush runtime journal.
10812 23:20:30.720701 Kernel Variables[0m...
10813 23:20:30.742123 Starting [0;1;39mCreate System Users[0m...
10814 23:20:30.759649 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10815 23:20:30.783041 <4>[ 20.292726] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10816 23:20:30.793110 <3>[ 20.292750] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10817 23:20:30.799441 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10818 23:20:30.823477 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10819 23:20:30.840604 See 'systemctl status systemd-udev-trigger.service' for details.
10820 23:20:30.862898 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10821 23:20:30.882444 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10822 23:20:32.123987 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10823 23:20:32.150717 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10824 23:20:32.198046 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10825 23:20:32.270918 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10826 23:20:32.285427 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10827 23:20:32.305018 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10828 23:20:32.353922 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10829 23:20:32.380300 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10830 23:20:32.543576 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10831 23:20:32.599334 Starting [0;1;39mNetwork Service[0m...
10832 23:20:32.651559 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10833 23:20:32.681044 Starting [0;1;39mNetwork Time Synchronization[0m...
10834 23:20:32.700849 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10835 23:20:32.886967 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10836 23:20:32.964359 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10837 23:20:33.004267 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10838 23:20:33.067230 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10839 23:20:33.247463 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10840 23:20:33.267915 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10841 23:20:33.305301 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10842 23:20:33.321515 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10843 23:20:33.338019 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10844 23:20:33.353769 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10845 23:20:33.374494 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10846 23:20:33.404848 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10847 23:20:33.424312 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10848 23:20:33.437121 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10849 23:20:33.453117 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10850 23:20:33.479616 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10851 23:20:33.503933 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10852 23:20:33.551575 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10853 23:20:33.571323 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10854 23:20:33.585253 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10855 23:20:33.606732 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10856 23:20:33.620699 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10857 23:20:33.637087 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10858 23:20:33.685745 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10859 23:20:33.739939 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
10860 23:20:33.821669 Starting [0;1;39mUser Login Management[0m...
10861 23:20:33.957069 Starting [0;1;39mNetwork Name Resolution[0m...
10862 23:20:34.049743 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
10863 23:20:34.106174 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10864 23:20:34.587001 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10865 23:20:34.603702 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10866 23:20:34.625471 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10867 23:20:34.662838 Starting [0;1;39mPermit User Sessions[0m...
10868 23:20:34.700704 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10869 23:20:34.754964 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10870 23:20:34.776598 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10871 23:20:34.798412 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10872 23:20:34.813109 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10873 23:20:34.831517 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10874 23:20:34.884225 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10875 23:20:34.926534 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10876 23:20:34.984289
10877 23:20:34.984809
10878 23:20:34.987401 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10879 23:20:34.987825
10880 23:20:34.990218 debian-bullseye-arm64 login: root (automatic login)
10881 23:20:34.990644
10882 23:20:34.990980
10883 23:20:35.311247 Linux debian-bullseye-arm64 6.1.64-cip10-rt5 #1 SMP PREEMPT Sun Dec 3 22:38:18 UTC 2023 aarch64
10884 23:20:35.311397
10885 23:20:35.318145 The programs included with the Debian GNU/Linux system are free software;
10886 23:20:35.324413 the exact distribution terms for each program are described in the
10887 23:20:35.327772 individual files in /usr/share/doc/*/copyright.
10888 23:20:35.327870
10889 23:20:35.334579 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10890 23:20:35.337306 permitted by applicable law.
10891 23:20:35.406552 Matched prompt #10: / #
10893 23:20:35.407639 Setting prompt string to ['/ #']
10894 23:20:35.408083 end: 2.2.5.1 login-action (duration 00:00:26) [common]
10896 23:20:35.409077 end: 2.2.5 auto-login-action (duration 00:00:26) [common]
10897 23:20:35.409521 start: 2.2.6 expect-shell-connection (timeout 00:03:32) [common]
10898 23:20:35.409931 Setting prompt string to ['/ #']
10899 23:20:35.410248 Forcing a shell prompt, looking for ['/ #']
10901 23:20:35.461004 / #
10902 23:20:35.461735 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10903 23:20:35.462196 Waiting using forced prompt support (timeout 00:02:30)
10904 23:20:35.467236
10905 23:20:35.468070 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10906 23:20:35.468616 start: 2.2.7 export-device-env (timeout 00:03:32) [common]
10908 23:20:35.569952 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12172422/extract-nfsrootfs-n4u2o4m3'
10909 23:20:35.576456 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12172422/extract-nfsrootfs-n4u2o4m3'
10911 23:20:35.678211 / # export NFS_SERVER_IP='192.168.201.1'
10912 23:20:35.684946 export NFS_SERVER_IP='192.168.201.1'
10913 23:20:35.685916 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10914 23:20:35.686450 end: 2.2 depthcharge-retry (duration 00:01:28) [common]
10915 23:20:35.686942 end: 2 depthcharge-action (duration 00:01:28) [common]
10916 23:20:35.687438 start: 3 lava-test-retry (timeout 00:30:00) [common]
10917 23:20:35.687919 start: 3.1 lava-test-shell (timeout 00:30:00) [common]
10918 23:20:35.688345 Using namespace: common
10920 23:20:35.789686 / # #
10921 23:20:35.790378 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:30:00)
10922 23:20:35.796379 #
10923 23:20:35.797280 Using /lava-12172422
10925 23:20:35.898529 / # export SHELL=/bin/sh
10926 23:20:35.905405 export SHELL=/bin/sh
10928 23:20:36.007151 / # . /lava-12172422/environment
10929 23:20:36.014247 . /lava-12172422/environment
10931 23:20:36.122794 / # /lava-12172422/bin/lava-test-runner /lava-12172422/0
10932 23:20:36.123450 Test shell timeout: 10s (minimum of the action and connection timeout)
10933 23:20:36.129233 /lava-12172422/bin/lava-test-runner /lava-12172422/0
10934 23:20:36.352962 + export TESTRUN_ID=0_lc-compliance
10935 23:20:36.359287 + cd /lava-12172422/0/tests/0_lc-compliance
10936 23:20:36.359373 + cat uuid
10937 23:20:36.362892 + UUID=12172422_1.6.2.3.1
10938 23:20:36.362975 + set +x
10939 23:20:36.369961 <LAVA_SIGNAL_STARTRUN 0_lc-compliance 12172422_1.6.2.3.1>
10940 23:20:36.370223 Received signal: <STARTRUN> 0_lc-compliance 12172422_1.6.2.3.1
10941 23:20:36.370301 Starting test lava.0_lc-compliance (12172422_1.6.2.3.1)
10942 23:20:36.370388 Skipping test definition patterns.
10943 23:20:36.373228 + /usr/bin/lc-compliance-parser.sh
10944 23:20:37.571274 [0:00:27.083379391] [418] [1;32m INFO [1;37mCamera [1;34mcamera_manager.cpp:297 [0mlibcamera v0.0.0+1-1f607da9
10945 23:20:37.574530 Using camera /base/soc/usb@11200000-1.4.1:1.0-04f2:b741
10946 23:20:37.588214 [0:00:27.100741830] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
10947 23:20:37.651604 [0:00:27.165268677] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
10948 23:20:37.667902 [==========] Running 120 tests from 1 test suite.
10949 23:20:37.711475 [0:00:27.225181767] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
10950 23:20:37.740083 [----------] Global test environment set-up.
10951 23:20:37.765617 [0:00:27.279837442] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
10952 23:20:37.816458 [----------] 120 tests from CaptureTests/SingleStream
10953 23:20:37.886687 [ RUN ] CaptureTests/SingleStream.Capture/Raw_1
10954 23:20:37.942615 <LAVA_SIGNAL_TESTSET START CaptureTests/SingleStream>
10955 23:20:37.943519 Received signal: <TESTSET> START CaptureTests/SingleStream
10956 23:20:37.943923 Starting test_set CaptureTests/SingleStream
10957 23:20:37.945887 Camera needs 4 requests, can't test only 1
10958 23:20:38.017257 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
10959 23:20:38.093884
10960 23:20:38.169157 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_1 (65 ms)
10961 23:20:38.195779 [0:00:27.712819940] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
10962 23:20:38.259217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_1 RESULT=skip>
10963 23:20:38.259918 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_1 RESULT=skip
10965 23:20:38.271676 [ RUN ] CaptureTests/SingleStream.Capture/Raw_2
10966 23:20:38.323834 Camera needs 4 requests, can't test only 2
10967 23:20:38.391553 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
10968 23:20:38.459738
10969 23:20:38.537282 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_2 (60 ms)
10970 23:20:38.622081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_2 RESULT=skip>
10971 23:20:38.622801 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_2 RESULT=skip
10973 23:20:38.635530 [ RUN ] CaptureTests/SingleStream.Capture/Raw_3
10974 23:20:38.661500 [0:00:28.181837789] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
10975 23:20:38.686236 Camera needs 4 requests, can't test only 3
10976 23:20:38.751090 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
10977 23:20:38.816133
10978 23:20:38.889263 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_3 (54 ms)
10979 23:20:38.975855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_3 RESULT=skip>
10980 23:20:38.976144 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_3 RESULT=skip
10982 23:20:38.989973 [ RUN ] CaptureTests/SingleStream.Capture/Raw_5
10983 23:20:39.033075 [ OK ] CaptureTests/SingleStream.Capture/Raw_5 (433 ms)
10984 23:20:39.110741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_5 RESULT=pass>
10985 23:20:39.111501 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_5 RESULT=pass
10987 23:20:39.123281 [ RUN ] CaptureTests/SingleStream.Capture/Raw_8
10988 23:20:39.171265 [ OK ] CaptureTests/SingleStream.Capture/Raw_8 (469 ms)
10989 23:20:39.249525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_8 RESULT=pass>
10990 23:20:39.249839 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_8 RESULT=pass
10992 23:20:39.263428 [ RUN ] CaptureTests/SingleStream.Capture/Raw_13
10993 23:20:39.348642 [ OK ] CaptureTests/SingleStream.Capture/Raw_13 (700 ms)
10994 23:20:39.359045 [0:00:28.882136056] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
10995 23:20:39.440302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_13 RESULT=pass>
10996 23:20:39.440585 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_13 RESULT=pass
10998 23:20:39.452580 [ RUN ] CaptureTests/SingleStream.Capture/Raw_21
10999 23:20:40.345000 [ OK ] CaptureTests/SingleStream.Capture/Raw_21 (1002 ms)
11000 23:20:40.354603 [0:00:29.884014980] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11001 23:20:40.442000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_21 RESULT=pass>
11002 23:20:40.442715 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_21 RESULT=pass
11004 23:20:40.454891 [ RUN ] CaptureTests/SingleStream.Capture/Raw_34
11005 23:20:41.773224 [ OK ] CaptureTests/SingleStream.Capture/Raw_34 (1436 ms)
11006 23:20:41.783142 [0:00:31.319587225] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11007 23:20:41.875950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_34 RESULT=pass>
11008 23:20:41.876667 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_34 RESULT=pass
11010 23:20:41.892755 [ RUN ] CaptureTests/SingleStream.Capture/Raw_55
11011 23:20:43.868929 [ OK ] CaptureTests/SingleStream.Capture/Raw_55 (2103 ms)
11012 23:20:43.879017 [0:00:33.423779456] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11013 23:20:43.958866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_55 RESULT=pass>
11014 23:20:43.959148 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_55 RESULT=pass
11016 23:20:43.971648 [ RUN ] CaptureTests/SingleStream.Capture/Raw_89
11017 23:20:47.034243 [ OK ] CaptureTests/SingleStream.Capture/Raw_89 (3174 ms)
11018 23:20:47.044658 [0:00:36.598166519] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11019 23:20:47.098601 [0:00:36.653433354] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11020 23:20:47.140148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_89 RESULT=pass>
11021 23:20:47.140450 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_89 RESULT=pass
11023 23:20:47.153415 [0:00:36.708272238] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11024 23:20:47.156746 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_1
11025 23:20:47.206624 [0:00:36.761635340] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11026 23:20:47.213940 Camera needs 4 requests, can't test only 1
11027 23:20:47.295387 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11028 23:20:47.378073
11029 23:20:47.460445 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_1 (55 ms)
11030 23:20:47.548511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_1 RESULT=skip>
11031 23:20:47.549209 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_1 RESULT=skip
11033 23:20:47.569106 [0:00:37.125225353] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11034 23:20:47.572040 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_2
11035 23:20:47.609774 Camera needs 4 requests, can't test only 2
11036 23:20:47.675918 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11037 23:20:47.748352
11038 23:20:47.809512 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_2 (56 ms)
11039 23:20:47.895012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_2 RESULT=skip>
11040 23:20:47.895342 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_2 RESULT=skip
11042 23:20:47.909076 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_3
11043 23:20:47.955705 Camera needs 4 requests, can't test only 3
11044 23:20:48.034246 [0:00:37.591103364] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11045 23:20:48.037377 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11046 23:20:48.096102
11047 23:20:48.156924 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_3 (52 ms)
11048 23:20:48.222940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_3 RESULT=skip>
11049 23:20:48.223221 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_3 RESULT=skip
11051 23:20:48.234852 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_5
11052 23:20:48.272846 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_5 (364 ms)
11053 23:20:48.348867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_5 RESULT=pass>
11054 23:20:48.349147 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_5 RESULT=pass
11056 23:20:48.359786 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_8
11057 23:20:48.400784 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_8 (466 ms)
11058 23:20:48.486859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_8 RESULT=pass>
11059 23:20:48.487570 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_8 RESULT=pass
11061 23:20:48.501008 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_13
11062 23:20:48.722821 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_13 (698 ms)
11063 23:20:48.735823 [0:00:38.290805502] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11064 23:20:48.818460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_13 RESULT=pass>
11065 23:20:48.819231 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_13 RESULT=pass
11067 23:20:48.833193 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_21
11068 23:20:49.623291 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_21 (902 ms)
11069 23:20:49.635844 [0:00:39.192338199] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11070 23:20:49.723692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_21 RESULT=pass>
11071 23:20:49.723987 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_21 RESULT=pass
11073 23:20:49.738568 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_34
11074 23:20:51.020094 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_34 (1399 ms)
11075 23:20:51.033457 [0:00:40.592059748] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11076 23:20:51.118486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_34 RESULT=pass>
11077 23:20:51.119265 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_34 RESULT=pass
11079 23:20:51.134009 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_55
11080 23:20:53.117950 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_55 (2100 ms)
11081 23:20:53.131186 [0:00:42.692157901] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11082 23:20:53.200148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_55 RESULT=pass>
11083 23:20:53.200998 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_55 RESULT=pass
11085 23:20:53.215394 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_89
11086 23:20:54.425017 <6>[ 43.947213] vpu: disabling
11087 23:20:54.427617 <6>[ 43.947331] vproc2: disabling
11088 23:20:54.431157 <6>[ 43.947385] vproc1: disabling
11089 23:20:54.434277 <6>[ 43.947438] vaud18: disabling
11090 23:20:54.437829 <6>[ 43.947687] vsram_others: disabling
11091 23:20:54.441232 <6>[ 43.947863] va09: disabling
11092 23:20:54.444331 <6>[ 43.947941] vsram_md: disabling
11093 23:20:54.448041 <6>[ 43.948070] Vgpu: disabling
11094 23:20:56.347923 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_89 (3233 ms)
11095 23:20:56.360775 [0:00:45.924941680] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11096 23:20:56.413225 [0:00:45.980889148] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11097 23:20:56.444052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_89 RESULT=pass>
11098 23:20:56.444757 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_89 RESULT=pass
11100 23:20:56.466990 [0:00:46.034153121] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11101 23:20:56.469791 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_1
11102 23:20:56.515696 Camera needs 4 requests, can't test only 1
11103 23:20:56.525132 [0:00:46.089939183] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11104 23:20:56.587386 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11105 23:20:56.659470
11106 23:20:56.741962 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_1 (57 ms)
11107 23:20:56.817448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_1 RESULT=skip>
11108 23:20:56.817795 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_1 RESULT=skip
11110 23:20:56.831618 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_2
11111 23:20:56.877554 Camera needs 4 requests, can't test only 2
11112 23:20:56.887485 [0:00:46.455186320] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11113 23:20:56.942370 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11114 23:20:56.998353
11115 23:20:57.075271 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_2 (54 ms)
11116 23:20:57.155460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_2 RESULT=skip>
11117 23:20:57.155740 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_2 RESULT=skip
11119 23:20:57.167799 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_3
11120 23:20:57.211344 Camera needs 4 requests, can't test only 3
11121 23:20:57.282667 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11122 23:20:57.351030 [0:00:46.919074998] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11123 23:20:57.368002
11124 23:20:57.444960 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_3 (56 ms)
11125 23:20:57.529124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_3 RESULT=skip>
11126 23:20:57.529929 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_3 RESULT=skip
11128 23:20:57.544389 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_5
11129 23:20:57.596924 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_5 (364 ms)
11130 23:20:57.679247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_5 RESULT=pass>
11131 23:20:57.680009 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_5 RESULT=pass
11133 23:20:57.695512 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_8
11134 23:20:57.751577 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_8 (465 ms)
11135 23:20:57.836058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_8 RESULT=pass>
11136 23:20:57.836388 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_8 RESULT=pass
11138 23:20:57.849635 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_13
11139 23:20:58.039358 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_13 (696 ms)
11140 23:20:58.051509 [0:00:47.615971038] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11141 23:20:58.131514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_13 RESULT=pass>
11142 23:20:58.132226 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_13 RESULT=pass
11144 23:20:58.147076 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_21
11145 23:20:58.937749 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_21 (899 ms)
11146 23:20:58.950900 [0:00:48.515440150] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11147 23:20:59.024564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_21 RESULT=pass>
11148 23:20:59.025281 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_21 RESULT=pass
11150 23:20:59.039957 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_34
11151 23:21:00.271359 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_34 (1335 ms)
11152 23:21:00.284700 [0:00:49.851593586] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11153 23:21:00.359810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_34 RESULT=pass>
11154 23:21:00.360522 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_34 RESULT=pass
11156 23:21:00.374422 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_55
11157 23:21:02.402054 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_55 (2131 ms)
11158 23:21:02.414794 [0:00:51.983695967] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11159 23:21:02.497008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_55 RESULT=pass>
11160 23:21:02.497747 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_55 RESULT=pass
11162 23:21:02.513143 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_89
11163 23:21:05.632731 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_89 (3232 ms)
11164 23:21:05.646158 [0:00:55.215468789] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11165 23:21:05.700744 [0:00:55.272445523] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11166 23:21:05.733756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_89 RESULT=pass>
11167 23:21:05.734458 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_89 RESULT=pass
11169 23:21:05.755115 [0:00:55.326733259] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11170 23:21:05.758095 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_1
11171 23:21:05.802802 Camera needs 4 requests, can't test only 1
11172 23:21:05.812886 [0:00:55.386242810] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11173 23:21:05.882962 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11174 23:21:05.954016
11175 23:21:06.024674 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_1 (58 ms)
11176 23:21:06.110627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_1 RESULT=skip>
11177 23:21:06.110919 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_1 RESULT=skip
11179 23:21:06.124653 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_2
11180 23:21:06.177557 [0:00:55.749476466] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11181 23:21:06.180847 Camera needs 4 requests, can't test only 2
11182 23:21:06.255311 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11183 23:21:06.327824
11184 23:21:06.395636 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_2 (56 ms)
11185 23:21:06.469532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_2 RESULT=skip>
11186 23:21:06.469845 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_2 RESULT=skip
11188 23:21:06.482301 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_3
11189 23:21:06.533829 Camera needs 4 requests, can't test only 3
11190 23:21:06.606158 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11191 23:21:06.639029 [0:00:56.210774927] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11192 23:21:06.680110
11193 23:21:06.752709 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_3 (59 ms)
11194 23:21:06.828589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_3 RESULT=skip>
11195 23:21:06.829342 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_3 RESULT=skip
11197 23:21:06.839582 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_5
11198 23:21:06.891652 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_5 (365 ms)
11199 23:21:06.971328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_5 RESULT=pass>
11200 23:21:06.972035 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_5 RESULT=pass
11202 23:21:06.987100 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_8
11203 23:21:07.037344 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_8 (461 ms)
11204 23:21:07.125380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_8 RESULT=pass>
11205 23:21:07.125734 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_8 RESULT=pass
11207 23:21:07.137691 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_13
11208 23:21:07.326181 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_13 (694 ms)
11209 23:21:07.339147 [0:00:56.906163289] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11210 23:21:07.417859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_13 RESULT=pass>
11211 23:21:07.418247 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_13 RESULT=pass
11213 23:21:07.431635 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_21
11214 23:21:08.225259 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_21 (899 ms)
11215 23:21:08.238070 [0:00:57.805691910] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11216 23:21:08.317223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_21 RESULT=pass>
11217 23:21:08.317525 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_21 RESULT=pass
11219 23:21:08.331225 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_34
11220 23:21:09.621613 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_34 (1397 ms)
11221 23:21:09.634659 [0:00:59.204443122] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11222 23:21:09.711065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_34 RESULT=pass>
11223 23:21:09.711377 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_34 RESULT=pass
11225 23:21:09.724465 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_55
11226 23:21:11.720057 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_55 (2098 ms)
11227 23:21:11.733267 [0:01:01.302578629] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11228 23:21:11.812887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_55 RESULT=pass>
11229 23:21:11.813670 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_55 RESULT=pass
11231 23:21:11.827196 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_89
11232 23:21:14.950160 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_89 (3230 ms)
11233 23:21:14.963538 [0:01:04.533235656] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11234 23:21:15.018847 [0:01:04.590294417] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11235 23:21:15.056648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_89 RESULT=pass>
11236 23:21:15.057436 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_89 RESULT=pass
11238 23:21:15.073133 [0:01:04.644934056] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11239 23:21:15.076746 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_1
11240 23:21:15.128388 [0:01:04.699770988] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11241 23:21:15.131032 Camera needs 4 requests, can't test only 1
11242 23:21:15.208493 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11243 23:21:15.274125
11244 23:21:15.360966 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_1 (59 ms)
11245 23:21:15.445113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_1 RESULT=skip>
11246 23:21:15.445408 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_1 RESULT=skip
11248 23:21:15.459755 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_2
11249 23:21:15.512528 Camera needs 4 requests, can't test only 2
11250 23:21:15.586060 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11251 23:21:15.657180
11252 23:21:15.734320 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_2 (56 ms)
11253 23:21:15.814065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_2 RESULT=skip>
11254 23:21:15.814395 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_2 RESULT=skip
11256 23:21:15.827331 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_3
11257 23:21:15.879061 Camera needs 4 requests, can't test only 3
11258 23:21:15.968586 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11259 23:21:16.030322
11260 23:21:16.105353 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_3 (56 ms)
11261 23:21:16.200719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_3 RESULT=skip>
11262 23:21:16.201451 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_3 RESULT=skip
11264 23:21:16.218699 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_5
11265 23:21:16.269351 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_5 (1149 ms)
11266 23:21:16.282288 [0:01:05.848808920] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11267 23:21:16.362337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_5 RESULT=pass>
11268 23:21:16.362624 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_5 RESULT=pass
11270 23:21:16.376312 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_8
11271 23:21:17.657473 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_8 (1388 ms)
11272 23:21:17.670822 [0:01:07.240917903] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11273 23:21:17.746925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_8 RESULT=pass>
11274 23:21:17.747638 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_8 RESULT=pass
11276 23:21:17.761828 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_13
11277 23:21:19.773878 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_13 (2117 ms)
11278 23:21:19.786790 [0:01:09.356953658] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11279 23:21:19.865075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_13 RESULT=pass>
11280 23:21:19.865782 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_13 RESULT=pass
11282 23:21:19.881008 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_21
11283 23:21:22.459750 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_21 (2686 ms)
11284 23:21:22.472866 [0:01:12.042942956] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11285 23:21:22.550540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_21 RESULT=pass>
11286 23:21:22.551259 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_21 RESULT=pass
11288 23:21:22.564603 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_34
11289 23:21:26.673453 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_34 (4213 ms)
11290 23:21:26.687036 [0:01:16.257165910] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11291 23:21:26.764006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_34 RESULT=pass>
11292 23:21:26.764717 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_34 RESULT=pass
11294 23:21:26.777918 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_55
11295 23:21:32.954607 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_55 (6281 ms)
11296 23:21:32.967102 [0:01:22.538155240] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11297 23:21:33.047807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_55 RESULT=pass>
11298 23:21:33.048525 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_55 RESULT=pass
11300 23:21:33.062296 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_89
11301 23:21:42.666063 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_89 (9712 ms)
11302 23:21:42.678669 [0:01:32.250574413] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11303 23:21:42.732567 [0:01:32.306343091] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11304 23:21:42.764849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_89 RESULT=pass>
11305 23:21:42.765705 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_89 RESULT=pass
11307 23:21:42.780439 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_1
11308 23:21:42.793541 [0:01:32.363646808] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11309 23:21:42.836331 Camera needs 4 requests, can't test only 1
11310 23:21:42.846206 [0:01:32.419195492] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11311 23:21:42.916756 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11312 23:21:42.987679
11313 23:21:43.072207 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_1 (58 ms)
11314 23:21:43.156489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_1 RESULT=skip>
11315 23:21:43.156894 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_1 RESULT=skip
11317 23:21:43.168763 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_2
11318 23:21:43.233040 Camera needs 4 requests, can't test only 2
11319 23:21:43.304995 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11320 23:21:43.375270
11321 23:21:43.456492 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_2 (56 ms)
11322 23:21:43.545538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_2 RESULT=skip>
11323 23:21:43.546312 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_2 RESULT=skip
11325 23:21:43.557123 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_3
11326 23:21:43.612010 Camera needs 4 requests, can't test only 3
11327 23:21:43.702953 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11328 23:21:43.779868
11329 23:21:43.865891 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_3 (56 ms)
11330 23:21:43.958517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_3 RESULT=skip>
11331 23:21:43.959250 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_3 RESULT=skip
11333 23:21:43.971156 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_5
11334 23:21:44.027526 [0:01:33.601222764] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11335 23:21:44.034324 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_5 (1184 ms)
11336 23:21:44.118512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_5 RESULT=pass>
11337 23:21:44.119234 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_5 RESULT=pass
11339 23:21:44.131861 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_8
11340 23:21:45.568589 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_8 (1546 ms)
11341 23:21:45.578700 [0:01:35.150265614] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11342 23:21:45.659086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_8 RESULT=pass>
11343 23:21:45.659866 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_8 RESULT=pass
11345 23:21:45.671208 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_13
11346 23:21:47.651171 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_13 (2083 ms)
11347 23:21:47.660806 [0:01:37.233498019] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11348 23:21:47.741894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_13 RESULT=pass>
11349 23:21:47.742628 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_13 RESULT=pass
11351 23:21:47.755154 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_21
11352 23:21:50.437033 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_21 (2786 ms)
11353 23:21:50.446679 [0:01:40.018723841] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11354 23:21:50.520044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_21 RESULT=pass>
11355 23:21:50.520337 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_21 RESULT=pass
11357 23:21:50.528818 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_34
11358 23:21:54.650629 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_34 (4213 ms)
11359 23:21:54.659642 [0:01:44.233143813] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11360 23:21:54.748657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_34 RESULT=pass>
11361 23:21:54.748976 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_34 RESULT=pass
11363 23:21:54.759310 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_55
11364 23:22:00.964050 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_55 (6315 ms)
11365 23:22:00.973872 [0:01:50.547308237] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11366 23:22:01.066468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_55 RESULT=pass>
11367 23:22:01.067277 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_55 RESULT=pass
11369 23:22:01.079077 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_89
11370 23:22:10.642795 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_89 (9679 ms)
11371 23:22:10.652668 [0:02:00.226461574] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11372 23:22:10.705736 [0:02:00.281388518] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11373 23:22:10.750035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_89 RESULT=pass>
11374 23:22:10.750765 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_89 RESULT=pass
11376 23:22:10.759966 [0:02:00.337540247] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11377 23:22:10.766621 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_1
11378 23:22:10.813506 [0:02:00.389993398] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11379 23:22:10.817017 Camera needs 4 requests, can't test only 1
11380 23:22:10.878229 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11381 23:22:10.932147
11382 23:22:10.992883 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_1 (57 ms)
11383 23:22:11.056460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_1 RESULT=skip>
11384 23:22:11.056813 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_1 RESULT=skip
11386 23:22:11.065753 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_2
11387 23:22:11.105973 Camera needs 4 requests, can't test only 2
11388 23:22:11.170841 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11389 23:22:11.236734
11390 23:22:11.307234 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_2 (56 ms)
11391 23:22:11.381349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_2 RESULT=skip>
11392 23:22:11.381678 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_2 RESULT=skip
11394 23:22:11.391645 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_3
11395 23:22:11.427916 Camera needs 4 requests, can't test only 3
11396 23:22:11.504828 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11397 23:22:11.571658
11398 23:22:11.661072 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_3 (53 ms)
11399 23:22:11.735287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_3 RESULT=skip>
11400 23:22:11.736021 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_3 RESULT=skip
11402 23:22:11.749716 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_5
11403 23:22:11.989631 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_5 (1180 ms)
11404 23:22:11.999603 [0:02:01.571478016] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11405 23:22:12.075702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_5 RESULT=pass>
11406 23:22:12.076422 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_5 RESULT=pass
11408 23:22:12.088051 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_8
11409 23:22:13.376801 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_8 (1386 ms)
11410 23:22:13.386108 [0:02:02.959487448] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11411 23:22:13.465665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_8 RESULT=pass>
11412 23:22:13.466370 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_8 RESULT=pass
11414 23:22:13.477999 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_13
11415 23:22:15.426786 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_13 (2050 ms)
11416 23:22:15.436289 [0:02:05.010108480] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11417 23:22:15.524717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_13 RESULT=pass>
11418 23:22:15.525092 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_13 RESULT=pass
11420 23:22:15.536792 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_21
11421 23:22:18.113473 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_21 (2686 ms)
11422 23:22:18.123196 [0:02:07.696369093] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11423 23:22:18.202657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_21 RESULT=pass>
11424 23:22:18.203386 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_21 RESULT=pass
11426 23:22:18.216763 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_34
11427 23:22:22.328183 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_34 (4214 ms)
11428 23:22:22.337899 [0:02:11.910799580] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11429 23:22:22.430130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_34 RESULT=pass>
11430 23:22:22.430893 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_34 RESULT=pass
11432 23:22:22.444323 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_55
11433 23:22:28.640543 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_55 (6313 ms)
11434 23:22:28.650378 [0:02:18.223222612] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11435 23:22:28.733206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_55 RESULT=pass>
11436 23:22:28.733956 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_55 RESULT=pass
11438 23:22:28.747986 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_89
11439 23:22:38.256083 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_89 (9615 ms)
11440 23:22:38.265904 [0:02:27.837881805] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11441 23:22:38.318903 [0:02:27.893079419] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11442 23:22:38.349409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_89 RESULT=pass>
11443 23:22:38.350305 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_89 RESULT=pass
11445 23:22:38.359728 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_1
11446 23:22:38.369673 [0:02:27.946929273] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11447 23:22:38.417198 Camera needs 4 requests, can't test only 1
11448 23:22:38.426927 [0:02:28.001232379] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11449 23:22:38.498743 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11450 23:22:38.568738
11451 23:22:38.649739 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_1 (57 ms)
11452 23:22:38.737296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_1 RESULT=skip>
11453 23:22:38.737602 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_1 RESULT=skip
11455 23:22:38.748045 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_2
11456 23:22:38.809675 Camera needs 4 requests, can't test only 2
11457 23:22:38.883717 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11458 23:22:38.953470
11459 23:22:39.036864 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_2 (55 ms)
11460 23:22:39.127820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_2 RESULT=skip>
11461 23:22:39.128546 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_2 RESULT=skip
11463 23:22:39.150600 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_3
11464 23:22:39.207388 Camera needs 4 requests, can't test only 3
11465 23:22:39.283596 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11466 23:22:39.353563
11467 23:22:39.435315 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_3 (52 ms)
11468 23:22:39.511825 [0:02:29.086493750] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11469 23:22:39.519621 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_3 RESULT=skip
11471 23:22:39.522581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_3 RESULT=skip>
11472 23:22:39.533356 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_5
11473 23:22:39.584367 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_5 (1087 ms)
11474 23:22:39.671303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_5 RESULT=pass>
11475 23:22:39.672024 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_5 RESULT=pass
11477 23:22:39.681125 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_8
11478 23:22:40.891704 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_8 (1384 ms)
11479 23:22:40.901295 [0:02:30.474018250] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11480 23:22:40.985874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_8 RESULT=pass>
11481 23:22:40.986670 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_8 RESULT=pass
11483 23:22:40.999444 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_13
11484 23:22:42.943678 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_13 (2052 ms)
11485 23:22:42.953490 [0:02:32.525218947] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11486 23:22:43.038988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_13 RESULT=pass>
11487 23:22:43.039329 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_13 RESULT=pass
11489 23:22:43.051362 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_21
11490 23:22:45.628777 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_21 (2686 ms)
11491 23:22:45.638900 [0:02:35.211149687] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11492 23:22:45.724098 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_21 RESULT=pass
11494 23:22:45.727129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_21 RESULT=pass>
11495 23:22:45.740671 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_34
11496 23:22:49.842802 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_34 (4214 ms)
11497 23:22:49.852728 [0:02:39.425734569] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11498 23:22:49.932926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_34 RESULT=pass>
11499 23:22:49.933223 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_34 RESULT=pass
11501 23:22:49.943426 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_55
11502 23:22:56.156388 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_55 (6314 ms)
11503 23:22:56.166470 [0:02:45.739272265] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11504 23:22:56.254222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_55 RESULT=pass>
11505 23:22:56.254957 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_55 RESULT=pass
11507 23:22:56.268853 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_89
11508 23:23:05.771237 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_89 (9615 ms)
11509 23:23:05.780848 [0:02:55.354230432] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11510 23:23:05.869473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_89 RESULT=pass>
11511 23:23:05.870221 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_89 RESULT=pass
11513 23:23:05.883355 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_1
11514 23:23:06.101213 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_1 (333 ms)
11515 23:23:06.111211 [0:02:55.685064875] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11516 23:23:06.191217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_1 RESULT=pass>
11517 23:23:06.191971 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_1 RESULT=pass
11519 23:23:06.206794 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_2
11520 23:23:06.466532 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_2 (364 ms)
11521 23:23:06.475689 [0:02:56.049566088] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11522 23:23:06.565361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_2 RESULT=pass>
11523 23:23:06.566210 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_2 RESULT=pass
11525 23:23:06.579967 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_3
11526 23:23:06.766172 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_3 (300 ms)
11527 23:23:06.775778 [0:02:56.349279175] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11528 23:23:06.859382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_3 RESULT=pass>
11529 23:23:06.860225 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_3 RESULT=pass
11531 23:23:06.873738 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_5
11532 23:23:07.196551 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_5 (430 ms)
11533 23:23:07.209104 [0:02:56.779836268] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11534 23:23:07.285546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_5 RESULT=pass>
11535 23:23:07.285896 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_5 RESULT=pass
11537 23:23:07.299187 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_8
11538 23:23:07.662373 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_8 (466 ms)
11539 23:23:07.672367 [0:02:57.246461841] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11540 23:23:07.764883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_8 RESULT=pass>
11541 23:23:07.765635 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_8 RESULT=pass
11543 23:23:07.781432 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_13
11544 23:23:08.360489 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_13 (698 ms)
11545 23:23:08.373623 [0:02:57.944200672] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11546 23:23:08.461417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_13 RESULT=pass>
11547 23:23:08.461723 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_13 RESULT=pass
11549 23:23:08.476458 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_21
11550 23:23:09.259499 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_21 (899 ms)
11551 23:23:09.272771 [0:02:58.843655825] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11552 23:23:09.348536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_21 RESULT=pass>
11553 23:23:09.349246 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_21 RESULT=pass
11555 23:23:09.364664 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_34
11556 23:23:10.657045 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_34 (1397 ms)
11557 23:23:10.669549 [0:03:00.242956668] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11558 23:23:10.764525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_34 RESULT=pass>
11559 23:23:10.764822 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_34 RESULT=pass
11561 23:23:10.777541 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_55
11562 23:23:12.754878 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_55 (2099 ms)
11563 23:23:12.767639 [0:03:02.341459113] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11564 23:23:12.843348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_55 RESULT=pass>
11565 23:23:12.844066 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_55 RESULT=pass
11567 23:23:12.858175 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_89
11568 23:23:15.985986 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_89 (3231 ms)
11569 23:23:15.998701 [0:03:05.572305459] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11570 23:23:16.078337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_89 RESULT=pass>
11571 23:23:16.078857 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_89 RESULT=pass
11573 23:23:16.094627 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_1
11574 23:23:16.288826 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_1 (299 ms)
11575 23:23:16.298540 [0:03:05.869772291] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11576 23:23:16.377882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_1 RESULT=pass>
11577 23:23:16.378603 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_1 RESULT=pass
11579 23:23:16.387930 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_2
11580 23:23:16.620730 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_2 (332 ms)
11581 23:23:16.630773 [0:03:06.201625165] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11582 23:23:16.710056 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_2 RESULT=pass
11584 23:23:16.713042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_2 RESULT=pass>
11585 23:23:16.724141 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_3
11586 23:23:16.919994 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_3 (300 ms)
11587 23:23:16.929719 [0:03:06.501190411] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11588 23:23:17.018910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_3 RESULT=pass>
11589 23:23:17.019253 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_3 RESULT=pass
11591 23:23:17.031202 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_5
11592 23:23:17.384732 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_5 (464 ms)
11593 23:23:17.394518 [0:03:06.965507670] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11594 23:23:17.482890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_5 RESULT=pass>
11595 23:23:17.483615 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_5 RESULT=pass
11597 23:23:17.493897 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_8
11598 23:23:17.949095 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_8 (564 ms)
11599 23:23:17.957970 [0:03:07.529533055] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11600 23:23:18.046183 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_8 RESULT=pass
11602 23:23:18.049197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_8 RESULT=pass>
11603 23:23:18.061501 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_13
11604 23:23:18.646355 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_13 (698 ms)
11605 23:23:18.655984 [0:03:08.227184928] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11606 23:23:18.741906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_13 RESULT=pass>
11607 23:23:18.742238 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_13 RESULT=pass
11609 23:23:18.750607 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_21
11610 23:23:19.545417 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_21 (899 ms)
11611 23:23:19.555107 [0:03:09.126495498] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11612 23:23:19.638296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_21 RESULT=pass>
11613 23:23:19.639014 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_21 RESULT=pass
11615 23:23:19.651448 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_34
11616 23:23:20.942696 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_34 (1398 ms)
11617 23:23:20.952901 [0:03:10.526179863] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11618 23:23:21.037249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_34 RESULT=pass>
11619 23:23:21.038266 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_34 RESULT=pass
11621 23:23:21.048783 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_55
11622 23:23:23.073369 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_55 (2131 ms)
11623 23:23:23.083577 [0:03:12.657012618] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11624 23:23:23.164707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_55 RESULT=pass>
11625 23:23:23.165021 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_55 RESULT=pass
11627 23:23:23.174765 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_89
11628 23:23:26.241412 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_89 (3168 ms)
11629 23:23:26.250914 [0:03:15.825306644] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11630 23:23:26.330350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_89 RESULT=pass>
11631 23:23:26.331142 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_89 RESULT=pass
11633 23:23:26.342778 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_1
11634 23:23:26.574631 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_1 (332 ms)
11635 23:23:26.584395 [0:03:16.155857505] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11636 23:23:26.665461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_1 RESULT=pass>
11637 23:23:26.665792 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_1 RESULT=pass
11639 23:23:26.675871 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_2
11640 23:23:26.938585 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_2 (365 ms)
11641 23:23:26.948452 [0:03:16.520279906] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11642 23:23:27.030266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_2 RESULT=pass>
11643 23:23:27.030972 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_2 RESULT=pass
11645 23:23:27.042766 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_3
11646 23:23:27.240303 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_3 (302 ms)
11647 23:23:27.250281 [0:03:16.822102726] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11648 23:23:27.336704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_3 RESULT=pass>
11649 23:23:27.337011 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_3 RESULT=pass
11651 23:23:27.347610 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_5
11652 23:23:27.671676 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_5 (431 ms)
11653 23:23:27.681417 [0:03:17.253187024] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11654 23:23:27.764031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_5 RESULT=pass>
11655 23:23:27.764908 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_5 RESULT=pass
11657 23:23:27.773224 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_8
11658 23:23:28.138580 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_8 (466 ms)
11659 23:23:28.148343 [0:03:17.719715599] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11660 23:23:28.237851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_8 RESULT=pass>
11661 23:23:28.238567 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_8 RESULT=pass
11663 23:23:28.250386 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_13
11664 23:23:28.836558 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_13 (698 ms)
11665 23:23:28.845707 [0:03:18.417541921] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11666 23:23:28.924541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_13 RESULT=pass>
11667 23:23:28.924822 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_13 RESULT=pass
11669 23:23:28.935937 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_21
11670 23:23:29.770589 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_21 (935 ms)
11671 23:23:29.780795 [0:03:19.352217309] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11672 23:23:29.859364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_21 RESULT=pass>
11673 23:23:29.860090 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_21 RESULT=pass
11675 23:23:29.868451 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_34
11676 23:23:31.167922 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_34 (1397 ms)
11677 23:23:31.177852 [0:03:20.751555558] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11678 23:23:31.261886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_34 RESULT=pass>
11679 23:23:31.262667 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_34 RESULT=pass
11681 23:23:31.273335 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_55
11682 23:23:33.266053 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_55 (2099 ms)
11683 23:23:33.276040 [0:03:22.850012879] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11684 23:23:33.356807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_55 RESULT=pass>
11685 23:23:33.357197 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_55 RESULT=pass
11687 23:23:33.367579 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_89
11688 23:23:36.496990 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_89 (3230 ms)
11689 23:23:36.506621 [0:03:26.081490106] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11690 23:23:36.592052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_89 RESULT=pass>
11691 23:23:36.592815 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_89 RESULT=pass
11693 23:23:36.606209 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_1
11694 23:23:36.733921 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_1 (236 ms)
11695 23:23:36.743964 [0:03:26.315967198] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11696 23:23:36.826826 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_1 RESULT=pass
11698 23:23:36.829185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_1 RESULT=pass>
11699 23:23:36.841332 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_2
11700 23:23:37.001612 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_2 (267 ms)
11701 23:23:37.011237 [0:03:26.583493913] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11702 23:23:37.089968 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_2 RESULT=pass
11704 23:23:37.093030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_2 RESULT=pass>
11705 23:23:37.103479 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_3
11706 23:23:37.301377 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_3 (299 ms)
11707 23:23:37.310285 [0:03:26.882571146] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11708 23:23:37.388193 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_3 RESULT=pass
11710 23:23:37.391208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_3 RESULT=pass>
11711 23:23:37.403044 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_5
11712 23:23:37.732541 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_5 (431 ms)
11713 23:23:37.741894 [0:03:27.313808240] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11714 23:23:37.817082 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_5 RESULT=pass
11716 23:23:37.819748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_5 RESULT=pass>
11717 23:23:37.831673 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_8
11718 23:23:38.198280 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_8 (467 ms)
11719 23:23:38.208057 [0:03:27.780379237] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11720 23:23:38.289938 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_8 RESULT=pass
11722 23:23:38.293420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_8 RESULT=pass>
11723 23:23:38.302424 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_13
11724 23:23:38.896164 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_13 (698 ms)
11725 23:23:38.906566 [0:03:28.478495196] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11726 23:23:38.996342 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_13 RESULT=pass
11728 23:23:38.999470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_13 RESULT=pass>
11729 23:23:39.015401 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_21
11730 23:23:39.795312 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_21 (899 ms)
11731 23:23:39.804842 [0:03:29.377707717] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11732 23:23:39.886531 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_21 RESULT=pass
11734 23:23:39.889214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_21 RESULT=pass>
11735 23:23:39.903654 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_34
11736 23:23:41.192513 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_34 (1398 ms)
11737 23:23:41.202238 [0:03:30.777238350] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11738 23:23:41.281949 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_34 RESULT=pass
11740 23:23:41.284558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_34 RESULT=pass>
11741 23:23:41.295536 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_55
11742 23:23:43.290650 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_55 (2098 ms)
11743 23:23:43.300491 [0:03:32.875271903] [418] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11744 23:23:43.376452 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_55 RESULT=pass
11746 23:23:43.379334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_55 RESULT=pass>
11747 23:23:43.390194 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_89
11748 23:23:46.521726 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_89 (3231 ms)
11749 23:23:46.601347 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_89 RESULT=pass
11751 23:23:46.604880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_89 RESULT=pass>
11752 23:23:46.613984 [----------] 120 tests from CaptureTests/SingleStream (189003 ms total)
11753 23:23:46.680275
11754 23:23:46.748425 [----------] Global test environment tear-down
11755 23:23:46.811588 [==========] 120 tests from 1 test suite ran. (189004 ms total)
11756 23:23:46.884403 <LAVA_SIGNAL_TESTSET STOP>
11757 23:23:46.884791 Received signal: <TESTSET> STOP
11758 23:23:46.884904 Closing test_set CaptureTests/SingleStream
11759 23:23:46.894614 + set +x
11760 23:23:46.898022 <LAVA_SIGNAL_ENDRUN 0_lc-compliance 12172422_1.6.2.3.1>
11761 23:23:46.898700 Received signal: <ENDRUN> 0_lc-compliance 12172422_1.6.2.3.1
11762 23:23:46.899094 Ending use of test pattern.
11763 23:23:46.899418 Ending test lava.0_lc-compliance (12172422_1.6.2.3.1), duration 190.53
11765 23:23:46.901050 <LAVA_TEST_RUNNER EXIT>
11766 23:23:46.901689 ok: lava_test_shell seems to have completed
11767 23:23:46.905047 Capture/Raw_1:
result: skip
set: CaptureTests/SingleStream
Capture/Raw_13:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_2:
result: skip
set: CaptureTests/SingleStream
Capture/Raw_21:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_3:
result: skip
set: CaptureTests/SingleStream
Capture/Raw_34:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_5:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_55:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_8:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_89:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_1:
result: skip
set: CaptureTests/SingleStream
Capture/StillCapture_13:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_2:
result: skip
set: CaptureTests/SingleStream
Capture/StillCapture_21:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_3:
result: skip
set: CaptureTests/SingleStream
Capture/StillCapture_34:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_5:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_55:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_8:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_89:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_1:
result: skip
set: CaptureTests/SingleStream
Capture/VideoRecording_13:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_2:
result: skip
set: CaptureTests/SingleStream
Capture/VideoRecording_21:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_3:
result: skip
set: CaptureTests/SingleStream
Capture/VideoRecording_34:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_5:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_55:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_8:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_89:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_1:
result: skip
set: CaptureTests/SingleStream
Capture/Viewfinder_13:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_2:
result: skip
set: CaptureTests/SingleStream
Capture/Viewfinder_21:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_3:
result: skip
set: CaptureTests/SingleStream
Capture/Viewfinder_34:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_5:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_55:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_8:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Raw_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Raw_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Raw_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_89:
result: pass
set: CaptureTests/SingleStream
11768 23:23:46.905223 end: 3.1 lava-test-shell (duration 00:03:11) [common]
11769 23:23:46.905312 end: 3 lava-test-retry (duration 00:03:11) [common]
11770 23:23:46.905399 start: 4 finalize (timeout 00:10:00) [common]
11771 23:23:46.905491 start: 4.1 power-off (timeout 00:00:30) [common]
11772 23:23:46.905695 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=off'
11773 23:23:46.988992 >> Command sent successfully.
11774 23:23:46.999655 Returned 0 in 0 seconds
11775 23:23:47.100994 end: 4.1 power-off (duration 00:00:00) [common]
11777 23:23:47.102618 start: 4.2 read-feedback (timeout 00:10:00) [common]
11778 23:23:47.103964 Listened to connection for namespace 'common' for up to 1s
11779 23:23:48.103653 Finalising connection for namespace 'common'
11780 23:23:48.104338 Disconnecting from shell: Finalise
11781 23:23:48.104765 / #
11782 23:23:48.205850 end: 4.2 read-feedback (duration 00:00:01) [common]
11783 23:23:48.206567 end: 4 finalize (duration 00:00:01) [common]
11784 23:23:48.207180 Cleaning after the job
11785 23:23:48.207714 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12172422/tftp-deploy-gha09xov/ramdisk
11786 23:23:48.220315 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12172422/tftp-deploy-gha09xov/kernel
11787 23:23:48.256256 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12172422/tftp-deploy-gha09xov/dtb
11788 23:23:48.256545 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12172422/tftp-deploy-gha09xov/nfsrootfs
11789 23:23:48.318925 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12172422/tftp-deploy-gha09xov/modules
11790 23:23:48.326050 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12172422
11791 23:23:48.636076 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12172422
11792 23:23:48.636260 Job finished correctly