Boot log: mt8192-asurada-spherion-r0
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 22
- Kernel Errors: 133
- Errors: 0
1 23:08:43.038588 lava-dispatcher, installed at version: 2023.10
2 23:08:43.038808 start: 0 validate
3 23:08:43.038948 Start time: 2023-12-03 23:08:43.038940+00:00 (UTC)
4 23:08:43.039069 Using caching service: 'http://localhost/cache/?uri=%s'
5 23:08:43.039208 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 23:08:43.297869 Using caching service: 'http://localhost/cache/?uri=%s'
7 23:08:43.298044 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.64-cip10-rt5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 23:08:43.562983 Using caching service: 'http://localhost/cache/?uri=%s'
9 23:08:43.563194 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.64-cip10-rt5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 23:08:43.828033 Using caching service: 'http://localhost/cache/?uri=%s'
11 23:08:43.828204 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.64-cip10-rt5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 23:08:44.095691 validate duration: 1.06
14 23:08:44.095993 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 23:08:44.096124 start: 1.1 download-retry (timeout 00:10:00) [common]
16 23:08:44.096225 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 23:08:44.096371 Not decompressing ramdisk as can be used compressed.
18 23:08:44.096461 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230623.0/arm64/rootfs.cpio.gz
19 23:08:44.096531 saving as /var/lib/lava/dispatcher/tmp/12172398/tftp-deploy-iy98jilq/ramdisk/rootfs.cpio.gz
20 23:08:44.096600 total size: 84918747 (80 MB)
21 23:08:44.097709 progress 0 % (0 MB)
22 23:08:44.120481 progress 5 % (4 MB)
23 23:08:44.143180 progress 10 % (8 MB)
24 23:08:44.166018 progress 15 % (12 MB)
25 23:08:44.188802 progress 20 % (16 MB)
26 23:08:44.211514 progress 25 % (20 MB)
27 23:08:44.234237 progress 30 % (24 MB)
28 23:08:44.257105 progress 35 % (28 MB)
29 23:08:44.279927 progress 40 % (32 MB)
30 23:08:44.302661 progress 45 % (36 MB)
31 23:08:44.325347 progress 50 % (40 MB)
32 23:08:44.348480 progress 55 % (44 MB)
33 23:08:44.371302 progress 60 % (48 MB)
34 23:08:44.393905 progress 65 % (52 MB)
35 23:08:44.416646 progress 70 % (56 MB)
36 23:08:44.439205 progress 75 % (60 MB)
37 23:08:44.462458 progress 80 % (64 MB)
38 23:08:44.485048 progress 85 % (68 MB)
39 23:08:44.507662 progress 90 % (72 MB)
40 23:08:44.530149 progress 95 % (76 MB)
41 23:08:44.552850 progress 100 % (80 MB)
42 23:08:44.553075 80 MB downloaded in 0.46 s (177.41 MB/s)
43 23:08:44.553248 end: 1.1.1 http-download (duration 00:00:00) [common]
45 23:08:44.553494 end: 1.1 download-retry (duration 00:00:00) [common]
46 23:08:44.553605 start: 1.2 download-retry (timeout 00:10:00) [common]
47 23:08:44.553695 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 23:08:44.553840 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.64-cip10-rt5/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 23:08:44.553914 saving as /var/lib/lava/dispatcher/tmp/12172398/tftp-deploy-iy98jilq/kernel/Image
50 23:08:44.553975 total size: 49172992 (46 MB)
51 23:08:44.554042 No compression specified
52 23:08:44.555188 progress 0 % (0 MB)
53 23:08:44.568589 progress 5 % (2 MB)
54 23:08:44.581896 progress 10 % (4 MB)
55 23:08:44.595109 progress 15 % (7 MB)
56 23:08:44.608260 progress 20 % (9 MB)
57 23:08:44.621549 progress 25 % (11 MB)
58 23:08:44.634798 progress 30 % (14 MB)
59 23:08:44.648107 progress 35 % (16 MB)
60 23:08:44.661353 progress 40 % (18 MB)
61 23:08:44.674860 progress 45 % (21 MB)
62 23:08:44.688279 progress 50 % (23 MB)
63 23:08:44.701610 progress 55 % (25 MB)
64 23:08:44.714785 progress 60 % (28 MB)
65 23:08:44.727875 progress 65 % (30 MB)
66 23:08:44.741055 progress 70 % (32 MB)
67 23:08:44.754509 progress 75 % (35 MB)
68 23:08:44.767813 progress 80 % (37 MB)
69 23:08:44.781079 progress 85 % (39 MB)
70 23:08:44.794350 progress 90 % (42 MB)
71 23:08:44.807374 progress 95 % (44 MB)
72 23:08:44.820404 progress 100 % (46 MB)
73 23:08:44.820627 46 MB downloaded in 0.27 s (175.87 MB/s)
74 23:08:44.820786 end: 1.2.1 http-download (duration 00:00:00) [common]
76 23:08:44.821021 end: 1.2 download-retry (duration 00:00:00) [common]
77 23:08:44.821116 start: 1.3 download-retry (timeout 00:09:59) [common]
78 23:08:44.821200 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 23:08:44.821345 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.64-cip10-rt5/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 23:08:44.821414 saving as /var/lib/lava/dispatcher/tmp/12172398/tftp-deploy-iy98jilq/dtb/mt8192-asurada-spherion-r0.dtb
81 23:08:44.821474 total size: 47278 (0 MB)
82 23:08:44.821534 No compression specified
83 23:08:44.822701 progress 69 % (0 MB)
84 23:08:44.822984 progress 100 % (0 MB)
85 23:08:44.823141 0 MB downloaded in 0.00 s (27.08 MB/s)
86 23:08:44.823262 end: 1.3.1 http-download (duration 00:00:00) [common]
88 23:08:44.823490 end: 1.3 download-retry (duration 00:00:00) [common]
89 23:08:44.823582 start: 1.4 download-retry (timeout 00:09:59) [common]
90 23:08:44.823667 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 23:08:44.823783 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.64-cip10-rt5/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 23:08:44.823849 saving as /var/lib/lava/dispatcher/tmp/12172398/tftp-deploy-iy98jilq/modules/modules.tar
93 23:08:44.823917 total size: 8614132 (8 MB)
94 23:08:44.823981 Using unxz to decompress xz
95 23:08:44.828028 progress 0 % (0 MB)
96 23:08:44.848827 progress 5 % (0 MB)
97 23:08:44.872595 progress 10 % (0 MB)
98 23:08:44.895958 progress 15 % (1 MB)
99 23:08:44.919181 progress 20 % (1 MB)
100 23:08:44.943103 progress 25 % (2 MB)
101 23:08:44.969305 progress 30 % (2 MB)
102 23:08:44.997143 progress 35 % (2 MB)
103 23:08:45.020753 progress 40 % (3 MB)
104 23:08:45.045007 progress 45 % (3 MB)
105 23:08:45.070262 progress 50 % (4 MB)
106 23:08:45.094599 progress 55 % (4 MB)
107 23:08:45.120621 progress 60 % (4 MB)
108 23:08:45.146254 progress 65 % (5 MB)
109 23:08:45.173151 progress 70 % (5 MB)
110 23:08:45.196473 progress 75 % (6 MB)
111 23:08:45.223348 progress 80 % (6 MB)
112 23:08:45.248860 progress 85 % (7 MB)
113 23:08:45.273983 progress 90 % (7 MB)
114 23:08:45.303396 progress 95 % (7 MB)
115 23:08:45.331246 progress 100 % (8 MB)
116 23:08:45.337455 8 MB downloaded in 0.51 s (16.00 MB/s)
117 23:08:45.337757 end: 1.4.1 http-download (duration 00:00:01) [common]
119 23:08:45.338021 end: 1.4 download-retry (duration 00:00:01) [common]
120 23:08:45.338114 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 23:08:45.338208 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 23:08:45.338289 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 23:08:45.338376 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 23:08:45.338597 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12172398/lava-overlay-o87wb3lm
125 23:08:45.338731 makedir: /var/lib/lava/dispatcher/tmp/12172398/lava-overlay-o87wb3lm/lava-12172398/bin
126 23:08:45.338844 makedir: /var/lib/lava/dispatcher/tmp/12172398/lava-overlay-o87wb3lm/lava-12172398/tests
127 23:08:45.338942 makedir: /var/lib/lava/dispatcher/tmp/12172398/lava-overlay-o87wb3lm/lava-12172398/results
128 23:08:45.339062 Creating /var/lib/lava/dispatcher/tmp/12172398/lava-overlay-o87wb3lm/lava-12172398/bin/lava-add-keys
129 23:08:45.339210 Creating /var/lib/lava/dispatcher/tmp/12172398/lava-overlay-o87wb3lm/lava-12172398/bin/lava-add-sources
130 23:08:45.339343 Creating /var/lib/lava/dispatcher/tmp/12172398/lava-overlay-o87wb3lm/lava-12172398/bin/lava-background-process-start
131 23:08:45.339474 Creating /var/lib/lava/dispatcher/tmp/12172398/lava-overlay-o87wb3lm/lava-12172398/bin/lava-background-process-stop
132 23:08:45.339600 Creating /var/lib/lava/dispatcher/tmp/12172398/lava-overlay-o87wb3lm/lava-12172398/bin/lava-common-functions
133 23:08:45.339725 Creating /var/lib/lava/dispatcher/tmp/12172398/lava-overlay-o87wb3lm/lava-12172398/bin/lava-echo-ipv4
134 23:08:45.339850 Creating /var/lib/lava/dispatcher/tmp/12172398/lava-overlay-o87wb3lm/lava-12172398/bin/lava-install-packages
135 23:08:45.339976 Creating /var/lib/lava/dispatcher/tmp/12172398/lava-overlay-o87wb3lm/lava-12172398/bin/lava-installed-packages
136 23:08:45.340100 Creating /var/lib/lava/dispatcher/tmp/12172398/lava-overlay-o87wb3lm/lava-12172398/bin/lava-os-build
137 23:08:45.340225 Creating /var/lib/lava/dispatcher/tmp/12172398/lava-overlay-o87wb3lm/lava-12172398/bin/lava-probe-channel
138 23:08:45.340351 Creating /var/lib/lava/dispatcher/tmp/12172398/lava-overlay-o87wb3lm/lava-12172398/bin/lava-probe-ip
139 23:08:45.340476 Creating /var/lib/lava/dispatcher/tmp/12172398/lava-overlay-o87wb3lm/lava-12172398/bin/lava-target-ip
140 23:08:45.340603 Creating /var/lib/lava/dispatcher/tmp/12172398/lava-overlay-o87wb3lm/lava-12172398/bin/lava-target-mac
141 23:08:45.340727 Creating /var/lib/lava/dispatcher/tmp/12172398/lava-overlay-o87wb3lm/lava-12172398/bin/lava-target-storage
142 23:08:45.340856 Creating /var/lib/lava/dispatcher/tmp/12172398/lava-overlay-o87wb3lm/lava-12172398/bin/lava-test-case
143 23:08:45.340983 Creating /var/lib/lava/dispatcher/tmp/12172398/lava-overlay-o87wb3lm/lava-12172398/bin/lava-test-event
144 23:08:45.341109 Creating /var/lib/lava/dispatcher/tmp/12172398/lava-overlay-o87wb3lm/lava-12172398/bin/lava-test-feedback
145 23:08:45.341234 Creating /var/lib/lava/dispatcher/tmp/12172398/lava-overlay-o87wb3lm/lava-12172398/bin/lava-test-raise
146 23:08:45.341359 Creating /var/lib/lava/dispatcher/tmp/12172398/lava-overlay-o87wb3lm/lava-12172398/bin/lava-test-reference
147 23:08:45.341483 Creating /var/lib/lava/dispatcher/tmp/12172398/lava-overlay-o87wb3lm/lava-12172398/bin/lava-test-runner
148 23:08:45.341655 Creating /var/lib/lava/dispatcher/tmp/12172398/lava-overlay-o87wb3lm/lava-12172398/bin/lava-test-set
149 23:08:45.341785 Creating /var/lib/lava/dispatcher/tmp/12172398/lava-overlay-o87wb3lm/lava-12172398/bin/lava-test-shell
150 23:08:45.341918 Updating /var/lib/lava/dispatcher/tmp/12172398/lava-overlay-o87wb3lm/lava-12172398/bin/lava-install-packages (oe)
151 23:08:46.226914 Updating /var/lib/lava/dispatcher/tmp/12172398/lava-overlay-o87wb3lm/lava-12172398/bin/lava-installed-packages (oe)
152 23:08:46.227123 Creating /var/lib/lava/dispatcher/tmp/12172398/lava-overlay-o87wb3lm/lava-12172398/environment
153 23:08:46.227250 LAVA metadata
154 23:08:46.227331 - LAVA_JOB_ID=12172398
155 23:08:46.227399 - LAVA_DISPATCHER_IP=192.168.201.1
156 23:08:46.227522 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:58) [common]
157 23:08:46.227591 skipped lava-vland-overlay
158 23:08:46.227672 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 23:08:46.227759 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:58) [common]
160 23:08:46.227826 skipped lava-multinode-overlay
161 23:08:46.227903 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 23:08:46.227987 start: 1.5.2.3 test-definition (timeout 00:09:58) [common]
163 23:08:46.228067 Loading test definitions
164 23:08:46.228158 start: 1.5.2.3.1 git-repo-action (timeout 00:09:58) [common]
165 23:08:46.228232 Using /lava-12172398 at stage 0
166 23:08:46.228334 Fetching tests from https://github.com/kernelci/kernelci-core
167 23:08:46.228416 Running '/usr/bin/git clone -b kernelci.org --depth=1 https://github.com/kernelci/kernelci-core /var/lib/lava/dispatcher/tmp/12172398/lava-overlay-o87wb3lm/lava-12172398/0/tests/0_sleep'
168 23:08:46.959954 Removing '.git' directory in /var/lib/lava/dispatcher/tmp/12172398/lava-overlay-o87wb3lm/lava-12172398/0/tests/0_sleep
169 23:08:46.961265 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/12172398/lava-overlay-o87wb3lm/lava-12172398/0/tests/0_sleep/config/lava/sleep/sleep.yaml
170 23:08:46.961710 uuid=12172398_1.5.2.3.1 testdef=None
171 23:08:46.961853 end: 1.5.2.3.1 git-repo-action (duration 00:00:01) [common]
173 23:08:46.962101 start: 1.5.2.3.2 test-overlay (timeout 00:09:57) [common]
174 23:08:46.962676 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
176 23:08:46.962905 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:57) [common]
177 23:08:46.963642 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
179 23:08:46.963877 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:57) [common]
180 23:08:46.964550 runner path: /var/lib/lava/dispatcher/tmp/12172398/lava-overlay-o87wb3lm/lava-12172398/0/tests/0_sleep test_uuid 12172398_1.5.2.3.1
181 23:08:46.964634 sleep_params='mem freeze'
182 23:08:46.964832 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
184 23:08:46.965087 Creating lava-test-runner.conf files
185 23:08:46.965153 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12172398/lava-overlay-o87wb3lm/lava-12172398/0 for stage 0
186 23:08:46.965248 - 0_sleep
187 23:08:46.965350 end: 1.5.2.3 test-definition (duration 00:00:01) [common]
188 23:08:46.965437 start: 1.5.2.4 compress-overlay (timeout 00:09:57) [common]
189 23:08:47.100330 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
190 23:08:47.100486 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:57) [common]
191 23:08:47.100578 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
192 23:08:47.100674 end: 1.5.2 lava-overlay (duration 00:00:02) [common]
193 23:08:47.100761 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
194 23:08:49.620155 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:03) [common]
195 23:08:49.620529 start: 1.5.4 extract-modules (timeout 00:09:54) [common]
196 23:08:49.620653 extracting modules file /var/lib/lava/dispatcher/tmp/12172398/tftp-deploy-iy98jilq/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12172398/extract-overlay-ramdisk-ygpmtap0/ramdisk
197 23:08:49.855825 end: 1.5.4 extract-modules (duration 00:00:00) [common]
198 23:08:49.856004 start: 1.5.5 apply-overlay-tftp (timeout 00:09:54) [common]
199 23:08:49.856106 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12172398/compress-overlay-r0syjna6/overlay-1.5.2.4.tar.gz to ramdisk
200 23:08:49.856182 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12172398/compress-overlay-r0syjna6/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12172398/extract-overlay-ramdisk-ygpmtap0/ramdisk
201 23:08:49.954363 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
202 23:08:49.954523 start: 1.5.6 configure-preseed-file (timeout 00:09:54) [common]
203 23:08:49.954623 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
204 23:08:49.954711 start: 1.5.7 compress-ramdisk (timeout 00:09:54) [common]
205 23:08:49.954796 Building ramdisk /var/lib/lava/dispatcher/tmp/12172398/extract-overlay-ramdisk-ygpmtap0/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12172398/extract-overlay-ramdisk-ygpmtap0/ramdisk
206 23:08:51.580900 >> 563580 blocks
207 23:09:01.185027 rename /var/lib/lava/dispatcher/tmp/12172398/extract-overlay-ramdisk-ygpmtap0/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12172398/tftp-deploy-iy98jilq/ramdisk/ramdisk.cpio.gz
208 23:09:01.185466 end: 1.5.7 compress-ramdisk (duration 00:00:11) [common]
209 23:09:01.185615 start: 1.5.8 prepare-kernel (timeout 00:09:43) [common]
210 23:09:01.185758 start: 1.5.8.1 prepare-fit (timeout 00:09:43) [common]
211 23:09:01.185904 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12172398/tftp-deploy-iy98jilq/kernel/Image'
212 23:09:14.027232 Returned 0 in 12 seconds
213 23:09:14.127849 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12172398/tftp-deploy-iy98jilq/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12172398/tftp-deploy-iy98jilq/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12172398/tftp-deploy-iy98jilq/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12172398/tftp-deploy-iy98jilq/kernel/image.itb
214 23:09:15.560748 output: FIT description: Kernel Image image with one or more FDT blobs
215 23:09:15.561124 output: Created: Sun Dec 3 23:09:15 2023
216 23:09:15.561202 output: Image 0 (kernel-1)
217 23:09:15.561333 output: Description:
218 23:09:15.561426 output: Created: Sun Dec 3 23:09:15 2023
219 23:09:15.561494 output: Type: Kernel Image
220 23:09:15.561556 output: Compression: lzma compressed
221 23:09:15.561666 output: Data Size: 11049348 Bytes = 10790.38 KiB = 10.54 MiB
222 23:09:15.561729 output: Architecture: AArch64
223 23:09:15.561799 output: OS: Linux
224 23:09:15.561879 output: Load Address: 0x00000000
225 23:09:15.561986 output: Entry Point: 0x00000000
226 23:09:15.562069 output: Hash algo: crc32
227 23:09:15.562146 output: Hash value: c85ea8f0
228 23:09:15.562209 output: Image 1 (fdt-1)
229 23:09:15.562266 output: Description: mt8192-asurada-spherion-r0
230 23:09:15.562320 output: Created: Sun Dec 3 23:09:15 2023
231 23:09:15.562374 output: Type: Flat Device Tree
232 23:09:15.562430 output: Compression: uncompressed
233 23:09:15.562485 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
234 23:09:15.562542 output: Architecture: AArch64
235 23:09:15.562598 output: Hash algo: crc32
236 23:09:15.562654 output: Hash value: cc4352de
237 23:09:15.562709 output: Image 2 (ramdisk-1)
238 23:09:15.562766 output: Description: unavailable
239 23:09:15.562845 output: Created: Sun Dec 3 23:09:15 2023
240 23:09:15.562899 output: Type: RAMDisk Image
241 23:09:15.562967 output: Compression: Unknown Compression
242 23:09:15.563020 output: Data Size: 98342497 Bytes = 96037.59 KiB = 93.79 MiB
243 23:09:15.563073 output: Architecture: AArch64
244 23:09:15.563126 output: OS: Linux
245 23:09:15.563179 output: Load Address: unavailable
246 23:09:15.563232 output: Entry Point: unavailable
247 23:09:15.563285 output: Hash algo: crc32
248 23:09:15.563337 output: Hash value: 794022da
249 23:09:15.563390 output: Default Configuration: 'conf-1'
250 23:09:15.563442 output: Configuration 0 (conf-1)
251 23:09:15.563495 output: Description: mt8192-asurada-spherion-r0
252 23:09:15.563547 output: Kernel: kernel-1
253 23:09:15.563600 output: Init Ramdisk: ramdisk-1
254 23:09:15.563653 output: FDT: fdt-1
255 23:09:15.563705 output: Loadables: kernel-1
256 23:09:15.563757 output:
257 23:09:15.563961 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
258 23:09:15.564055 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
259 23:09:15.564160 end: 1.5 prepare-tftp-overlay (duration 00:00:30) [common]
260 23:09:15.564253 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:29) [common]
261 23:09:15.564336 No LXC device requested
262 23:09:15.564415 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
263 23:09:15.564500 start: 1.7 deploy-device-env (timeout 00:09:29) [common]
264 23:09:15.564575 end: 1.7 deploy-device-env (duration 00:00:00) [common]
265 23:09:15.564645 Checking files for TFTP limit of 4294967296 bytes.
266 23:09:15.565145 end: 1 tftp-deploy (duration 00:00:31) [common]
267 23:09:15.565248 start: 2 depthcharge-action (timeout 00:05:00) [common]
268 23:09:15.565342 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
269 23:09:15.565466 substitutions:
270 23:09:15.565535 - {DTB}: 12172398/tftp-deploy-iy98jilq/dtb/mt8192-asurada-spherion-r0.dtb
271 23:09:15.565629 - {INITRD}: 12172398/tftp-deploy-iy98jilq/ramdisk/ramdisk.cpio.gz
272 23:09:15.565704 - {KERNEL}: 12172398/tftp-deploy-iy98jilq/kernel/Image
273 23:09:15.565763 - {LAVA_MAC}: None
274 23:09:15.565821 - {PRESEED_CONFIG}: None
275 23:09:15.565876 - {PRESEED_LOCAL}: None
276 23:09:15.565932 - {RAMDISK}: 12172398/tftp-deploy-iy98jilq/ramdisk/ramdisk.cpio.gz
277 23:09:15.565986 - {ROOT_PART}: None
278 23:09:15.566041 - {ROOT}: None
279 23:09:15.566095 - {SERVER_IP}: 192.168.201.1
280 23:09:15.566149 - {TEE}: None
281 23:09:15.566203 Parsed boot commands:
282 23:09:15.566257 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
283 23:09:15.566434 Parsed boot commands: tftpboot 192.168.201.1 12172398/tftp-deploy-iy98jilq/kernel/image.itb 12172398/tftp-deploy-iy98jilq/kernel/cmdline
284 23:09:15.566524 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
285 23:09:15.566610 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
286 23:09:15.566702 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
287 23:09:15.566787 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
288 23:09:15.566858 Not connected, no need to disconnect.
289 23:09:15.566932 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
290 23:09:15.567011 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
291 23:09:15.567080 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-0'
292 23:09:15.571249 Setting prompt string to ['lava-test: # ']
293 23:09:15.571661 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
294 23:09:15.571773 end: 2.2.1 reset-connection (duration 00:00:00) [common]
295 23:09:15.571869 start: 2.2.2 reset-device (timeout 00:05:00) [common]
296 23:09:15.571963 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
297 23:09:15.572213 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=reboot'
298 23:09:20.711552 >> Command sent successfully.
299 23:09:20.714005 Returned 0 in 5 seconds
300 23:09:20.814417 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
302 23:09:20.814749 end: 2.2.2 reset-device (duration 00:00:05) [common]
303 23:09:20.814851 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
304 23:09:20.814941 Setting prompt string to 'Starting depthcharge on Spherion...'
305 23:09:20.815007 Changing prompt to 'Starting depthcharge on Spherion...'
306 23:09:20.815078 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
307 23:09:20.815351 [Enter `^Ec?' for help]
308 23:09:20.989126
309 23:09:20.989290
310 23:09:20.989364 F0: 102B 0000
311 23:09:20.989432
312 23:09:20.989493 F3: 1001 0000 [0200]
313 23:09:20.989551
314 23:09:20.992820 F3: 1001 0000
315 23:09:20.992903
316 23:09:20.992969 F7: 102D 0000
317 23:09:20.993031
318 23:09:20.993089 F1: 0000 0000
319 23:09:20.993148
320 23:09:20.995781 V0: 0000 0000 [0001]
321 23:09:20.995867
322 23:09:20.995933 00: 0007 8000
323 23:09:20.996000
324 23:09:20.999878 01: 0000 0000
325 23:09:20.999963
326 23:09:21.000029 BP: 0C00 0209 [0000]
327 23:09:21.000090
328 23:09:21.003373 G0: 1182 0000
329 23:09:21.003455
330 23:09:21.003522 EC: 0000 0021 [4000]
331 23:09:21.003583
332 23:09:21.006909 S7: 0000 0000 [0000]
333 23:09:21.006992
334 23:09:21.007057 CC: 0000 0000 [0001]
335 23:09:21.007118
336 23:09:21.010384 T0: 0000 0040 [010F]
337 23:09:21.010469
338 23:09:21.010535 Jump to BL
339 23:09:21.010597
340 23:09:21.035583
341 23:09:21.035678
342 23:09:21.035744
343 23:09:21.043078 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
344 23:09:21.046528 ARM64: Exception handlers installed.
345 23:09:21.050196 ARM64: Testing exception
346 23:09:21.054211 ARM64: Done test exception
347 23:09:21.061384 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
348 23:09:21.068237 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
349 23:09:21.075716 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
350 23:09:21.086016 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
351 23:09:21.092715 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
352 23:09:21.103145 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
353 23:09:21.114156 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
354 23:09:21.120422 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
355 23:09:21.138597 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
356 23:09:21.142069 WDT: Last reset was cold boot
357 23:09:21.144880 SPI1(PAD0) initialized at 2873684 Hz
358 23:09:21.148332 SPI5(PAD0) initialized at 992727 Hz
359 23:09:21.152167 VBOOT: Loading verstage.
360 23:09:21.158628 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
361 23:09:21.162798 FMAP: Found "FLASH" version 1.1 at 0x20000.
362 23:09:21.165773 FMAP: base = 0x0 size = 0x800000 #areas = 25
363 23:09:21.169368 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
364 23:09:21.176184 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
365 23:09:21.182520 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
366 23:09:21.193245 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
367 23:09:21.193329
368 23:09:21.193396
369 23:09:21.203933 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
370 23:09:21.207433 ARM64: Exception handlers installed.
371 23:09:21.210219 ARM64: Testing exception
372 23:09:21.210301 ARM64: Done test exception
373 23:09:21.217202 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
374 23:09:21.220548 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
375 23:09:21.234077 Probing TPM: . done!
376 23:09:21.234163 TPM ready after 0 ms
377 23:09:21.241897 Connected to device vid:did:rid of 1ae0:0028:00
378 23:09:21.248904 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
379 23:09:21.309748 Initialized TPM device CR50 revision 0
380 23:09:21.319359 tlcl_send_startup: Startup return code is 0
381 23:09:21.319459 TPM: setup succeeded
382 23:09:21.330999 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
383 23:09:21.339447 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
384 23:09:21.353239 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
385 23:09:21.360734 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
386 23:09:21.364118 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
387 23:09:21.367753 in-header: 03 07 00 00 08 00 00 00
388 23:09:21.371415 in-data: aa e4 47 04 13 02 00 00
389 23:09:21.375252 Chrome EC: UHEPI supported
390 23:09:21.382618 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
391 23:09:21.386287 in-header: 03 95 00 00 08 00 00 00
392 23:09:21.386374 in-data: 18 20 20 08 00 00 00 00
393 23:09:21.389791 Phase 1
394 23:09:21.393393 FMAP: area GBB found @ 3f5000 (12032 bytes)
395 23:09:21.397388 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
396 23:09:21.404355 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
397 23:09:21.408371 Recovery requested (1009000e)
398 23:09:21.416015 TPM: Extending digest for VBOOT: boot mode into PCR 0
399 23:09:21.421557 tlcl_extend: response is 0
400 23:09:21.430951 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
401 23:09:21.436585 tlcl_extend: response is 0
402 23:09:21.443938 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
403 23:09:21.463392 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
404 23:09:21.470754 BS: bootblock times (exec / console): total (unknown) / 148 ms
405 23:09:21.470866
406 23:09:21.470961
407 23:09:21.480137 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
408 23:09:21.483236 ARM64: Exception handlers installed.
409 23:09:21.486480 ARM64: Testing exception
410 23:09:21.486564 ARM64: Done test exception
411 23:09:21.508922 pmic_efuse_setting: Set efuses in 11 msecs
412 23:09:21.512354 pmwrap_interface_init: Select PMIF_VLD_RDY
413 23:09:21.519118 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
414 23:09:21.522100 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
415 23:09:21.529633 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
416 23:09:21.533215 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
417 23:09:21.537196 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
418 23:09:21.544585 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
419 23:09:21.548054 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
420 23:09:21.552054 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
421 23:09:21.555766 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
422 23:09:21.559827 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
423 23:09:21.567451 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
424 23:09:21.571520 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
425 23:09:21.575222 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
426 23:09:21.582489 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
427 23:09:21.585873 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
428 23:09:21.593696 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
429 23:09:21.597251 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
430 23:09:21.605115 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
431 23:09:21.608643 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
432 23:09:21.615798 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
433 23:09:21.619454 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
434 23:09:21.626492 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
435 23:09:21.630781 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
436 23:09:21.637572 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
437 23:09:21.641596 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
438 23:09:21.648995 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
439 23:09:21.653109 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
440 23:09:21.659626 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
441 23:09:21.663218 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
442 23:09:21.667408 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
443 23:09:21.674695 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
444 23:09:21.677748 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
445 23:09:21.681558 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
446 23:09:21.688985 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
447 23:09:21.692698 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
448 23:09:21.700069 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
449 23:09:21.703739 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
450 23:09:21.707852 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
451 23:09:21.711261 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
452 23:09:21.714977 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
453 23:09:21.722540 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
454 23:09:21.726088 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
455 23:09:21.729874 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
456 23:09:21.733499 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
457 23:09:21.737398 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
458 23:09:21.745869 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
459 23:09:21.748161 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
460 23:09:21.752150 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
461 23:09:21.755773 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
462 23:09:21.759375 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
463 23:09:21.763174 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
464 23:09:21.771018 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
465 23:09:21.781892 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
466 23:09:21.786105 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
467 23:09:21.793521 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
468 23:09:21.800552 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
469 23:09:21.808134 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
470 23:09:21.811659 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
471 23:09:21.815479 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
472 23:09:21.822997 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x0
473 23:09:21.826257 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
474 23:09:21.834137 [RTC]rtc_osc_init,62: osc32con val = 0xde70
475 23:09:21.837472 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
476 23:09:21.846709 [RTC]rtc_get_frequency_meter,154: input=15, output=760
477 23:09:21.855813 [RTC]rtc_get_frequency_meter,154: input=23, output=942
478 23:09:21.865547 [RTC]rtc_get_frequency_meter,154: input=19, output=849
479 23:09:21.874967 [RTC]rtc_get_frequency_meter,154: input=17, output=805
480 23:09:21.884518 [RTC]rtc_get_frequency_meter,154: input=16, output=782
481 23:09:21.894078 [RTC]rtc_get_frequency_meter,154: input=16, output=781
482 23:09:21.904105 [RTC]rtc_get_frequency_meter,154: input=17, output=805
483 23:09:21.906945 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
484 23:09:21.914121 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
485 23:09:21.918318 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
486 23:09:21.921800 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
487 23:09:21.925799 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
488 23:09:21.929389 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
489 23:09:21.932827 ADC[4]: Raw value=906573 ID=7
490 23:09:21.936528 ADC[3]: Raw value=213810 ID=1
491 23:09:21.936612 RAM Code: 0x71
492 23:09:21.940445 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
493 23:09:21.948032 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
494 23:09:21.955246 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
495 23:09:21.962838 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
496 23:09:21.966347 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
497 23:09:21.969903 in-header: 03 07 00 00 08 00 00 00
498 23:09:21.969988 in-data: aa e4 47 04 13 02 00 00
499 23:09:21.973944 Chrome EC: UHEPI supported
500 23:09:21.981541 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
501 23:09:21.985018 in-header: 03 95 00 00 08 00 00 00
502 23:09:21.989071 in-data: 18 20 20 08 00 00 00 00
503 23:09:21.992234 MRC: failed to locate region type 0.
504 23:09:21.996276 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
505 23:09:22.000065 DRAM-K: Running full calibration
506 23:09:22.006895 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
507 23:09:22.006980 header.status = 0x0
508 23:09:22.011253 header.version = 0x6 (expected: 0x6)
509 23:09:22.014824 header.size = 0xd00 (expected: 0xd00)
510 23:09:22.018629 header.flags = 0x0
511 23:09:22.021834 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
512 23:09:22.041291 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
513 23:09:22.048574 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
514 23:09:22.052654 dram_init: ddr_geometry: 2
515 23:09:22.052737 [EMI] MDL number = 2
516 23:09:22.056091 [EMI] Get MDL freq = 0
517 23:09:22.056173 dram_init: ddr_type: 0
518 23:09:22.060153 is_discrete_lpddr4: 1
519 23:09:22.063848 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
520 23:09:22.063930
521 23:09:22.063995
522 23:09:22.064055 [Bian_co] ETT version 0.0.0.1
523 23:09:22.067859 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
524 23:09:22.071534
525 23:09:22.075416 dramc_set_vcore_voltage set vcore to 650000
526 23:09:22.075499 Read voltage for 800, 4
527 23:09:22.075565 Vio18 = 0
528 23:09:22.079009 Vcore = 650000
529 23:09:22.079091 Vdram = 0
530 23:09:22.079157 Vddq = 0
531 23:09:22.082932 Vmddr = 0
532 23:09:22.083014 dram_init: config_dvfs: 1
533 23:09:22.086848 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
534 23:09:22.094376 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
535 23:09:22.097779 [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9
536 23:09:22.101213 freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9
537 23:09:22.105428 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
538 23:09:22.108223 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
539 23:09:22.111602 MEM_TYPE=3, freq_sel=18
540 23:09:22.115216 sv_algorithm_assistance_LP4_1600
541 23:09:22.118708 ============ PULL DRAM RESETB DOWN ============
542 23:09:22.121636 ========== PULL DRAM RESETB DOWN end =========
543 23:09:22.125164 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
544 23:09:22.129034 ===================================
545 23:09:22.133293 LPDDR4 DRAM CONFIGURATION
546 23:09:22.136646 ===================================
547 23:09:22.136729 EX_ROW_EN[0] = 0x0
548 23:09:22.140804 EX_ROW_EN[1] = 0x0
549 23:09:22.140886 LP4Y_EN = 0x0
550 23:09:22.144207 WORK_FSP = 0x0
551 23:09:22.144289 WL = 0x2
552 23:09:22.147627 RL = 0x2
553 23:09:22.147709 BL = 0x2
554 23:09:22.151501 RPST = 0x0
555 23:09:22.151585 RD_PRE = 0x0
556 23:09:22.154559 WR_PRE = 0x1
557 23:09:22.154643 WR_PST = 0x0
558 23:09:22.157541 DBI_WR = 0x0
559 23:09:22.157671 DBI_RD = 0x0
560 23:09:22.161013 OTF = 0x1
561 23:09:22.164403 ===================================
562 23:09:22.168207 ===================================
563 23:09:22.168291 ANA top config
564 23:09:22.172104 ===================================
565 23:09:22.175748 DLL_ASYNC_EN = 0
566 23:09:22.175833 ALL_SLAVE_EN = 1
567 23:09:22.179127 NEW_RANK_MODE = 1
568 23:09:22.182593 DLL_IDLE_MODE = 1
569 23:09:22.185781 LP45_APHY_COMB_EN = 1
570 23:09:22.185865 TX_ODT_DIS = 1
571 23:09:22.189112 NEW_8X_MODE = 1
572 23:09:22.193134 ===================================
573 23:09:22.196525 ===================================
574 23:09:22.200198 data_rate = 1600
575 23:09:22.203241 CKR = 1
576 23:09:22.203323 DQ_P2S_RATIO = 8
577 23:09:22.206739 ===================================
578 23:09:22.209877 CA_P2S_RATIO = 8
579 23:09:22.213286 DQ_CA_OPEN = 0
580 23:09:22.216574 DQ_SEMI_OPEN = 0
581 23:09:22.219918 CA_SEMI_OPEN = 0
582 23:09:22.223430 CA_FULL_RATE = 0
583 23:09:22.223512 DQ_CKDIV4_EN = 1
584 23:09:22.226488 CA_CKDIV4_EN = 1
585 23:09:22.230044 CA_PREDIV_EN = 0
586 23:09:22.233418 PH8_DLY = 0
587 23:09:22.236320 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
588 23:09:22.239806 DQ_AAMCK_DIV = 4
589 23:09:22.239888 CA_AAMCK_DIV = 4
590 23:09:22.243402 CA_ADMCK_DIV = 4
591 23:09:22.246641 DQ_TRACK_CA_EN = 0
592 23:09:22.250277 CA_PICK = 800
593 23:09:22.253184 CA_MCKIO = 800
594 23:09:22.256823 MCKIO_SEMI = 0
595 23:09:22.256904 PLL_FREQ = 3068
596 23:09:22.260417 DQ_UI_PI_RATIO = 32
597 23:09:22.264271 CA_UI_PI_RATIO = 0
598 23:09:22.268488 ===================================
599 23:09:22.271629 ===================================
600 23:09:22.271711 memory_type:LPDDR4
601 23:09:22.275613 GP_NUM : 10
602 23:09:22.275695 SRAM_EN : 1
603 23:09:22.279423 MD32_EN : 0
604 23:09:22.283451 ===================================
605 23:09:22.283533 [ANA_INIT] >>>>>>>>>>>>>>
606 23:09:22.287394 <<<<<< [CONFIGURE PHASE]: ANA_TX
607 23:09:22.291017 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
608 23:09:22.294470 ===================================
609 23:09:22.297764 data_rate = 1600,PCW = 0X7600
610 23:09:22.300912 ===================================
611 23:09:22.304676 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
612 23:09:22.307617 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
613 23:09:22.314437 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
614 23:09:22.317798 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
615 23:09:22.324213 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
616 23:09:22.328075 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
617 23:09:22.328157 [ANA_INIT] flow start
618 23:09:22.331038 [ANA_INIT] PLL >>>>>>>>
619 23:09:22.331119 [ANA_INIT] PLL <<<<<<<<
620 23:09:22.334525 [ANA_INIT] MIDPI >>>>>>>>
621 23:09:22.337562 [ANA_INIT] MIDPI <<<<<<<<
622 23:09:22.341492 [ANA_INIT] DLL >>>>>>>>
623 23:09:22.341594 [ANA_INIT] flow end
624 23:09:22.344446 ============ LP4 DIFF to SE enter ============
625 23:09:22.351429 ============ LP4 DIFF to SE exit ============
626 23:09:22.351512 [ANA_INIT] <<<<<<<<<<<<<
627 23:09:22.354827 [Flow] Enable top DCM control >>>>>
628 23:09:22.357691 [Flow] Enable top DCM control <<<<<
629 23:09:22.361226 Enable DLL master slave shuffle
630 23:09:22.367713 ==============================================================
631 23:09:22.367795 Gating Mode config
632 23:09:22.374553 ==============================================================
633 23:09:22.377983 Config description:
634 23:09:22.384677 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
635 23:09:22.391125 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
636 23:09:22.397669 SELPH_MODE 0: By rank 1: By Phase
637 23:09:22.404487 ==============================================================
638 23:09:22.404570 GAT_TRACK_EN = 1
639 23:09:22.407712 RX_GATING_MODE = 2
640 23:09:22.411241 RX_GATING_TRACK_MODE = 2
641 23:09:22.414358 SELPH_MODE = 1
642 23:09:22.418186 PICG_EARLY_EN = 1
643 23:09:22.421476 VALID_LAT_VALUE = 1
644 23:09:22.427834 ==============================================================
645 23:09:22.431390 Enter into Gating configuration >>>>
646 23:09:22.434423 Exit from Gating configuration <<<<
647 23:09:22.438225 Enter into DVFS_PRE_config >>>>>
648 23:09:22.448130 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
649 23:09:22.451191 Exit from DVFS_PRE_config <<<<<
650 23:09:22.454492 Enter into PICG configuration >>>>
651 23:09:22.457916 Exit from PICG configuration <<<<
652 23:09:22.461497 [RX_INPUT] configuration >>>>>
653 23:09:22.461638 [RX_INPUT] configuration <<<<<
654 23:09:22.467951 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
655 23:09:22.474866 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
656 23:09:22.478091 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
657 23:09:22.484500 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
658 23:09:22.491352 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
659 23:09:22.498046 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
660 23:09:22.501365 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
661 23:09:22.504476 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
662 23:09:22.511377 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
663 23:09:22.514661 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
664 23:09:22.518305 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
665 23:09:22.521845 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
666 23:09:22.525120 ===================================
667 23:09:22.528066 LPDDR4 DRAM CONFIGURATION
668 23:09:22.531654 ===================================
669 23:09:22.535147 EX_ROW_EN[0] = 0x0
670 23:09:22.535231 EX_ROW_EN[1] = 0x0
671 23:09:22.537965 LP4Y_EN = 0x0
672 23:09:22.538047 WORK_FSP = 0x0
673 23:09:22.541537 WL = 0x2
674 23:09:22.541667 RL = 0x2
675 23:09:22.544854 BL = 0x2
676 23:09:22.544936 RPST = 0x0
677 23:09:22.548360 RD_PRE = 0x0
678 23:09:22.548442 WR_PRE = 0x1
679 23:09:22.551576 WR_PST = 0x0
680 23:09:22.551658 DBI_WR = 0x0
681 23:09:22.554675 DBI_RD = 0x0
682 23:09:22.554756 OTF = 0x1
683 23:09:22.558357 ===================================
684 23:09:22.565091 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
685 23:09:22.568100 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
686 23:09:22.571323 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
687 23:09:22.574873 ===================================
688 23:09:22.578237 LPDDR4 DRAM CONFIGURATION
689 23:09:22.581518 ===================================
690 23:09:22.581656 EX_ROW_EN[0] = 0x10
691 23:09:22.584634 EX_ROW_EN[1] = 0x0
692 23:09:22.588039 LP4Y_EN = 0x0
693 23:09:22.588121 WORK_FSP = 0x0
694 23:09:22.591515 WL = 0x2
695 23:09:22.591597 RL = 0x2
696 23:09:22.594874 BL = 0x2
697 23:09:22.594957 RPST = 0x0
698 23:09:22.597870 RD_PRE = 0x0
699 23:09:22.597952 WR_PRE = 0x1
700 23:09:22.601480 WR_PST = 0x0
701 23:09:22.601613 DBI_WR = 0x0
702 23:09:22.604875 DBI_RD = 0x0
703 23:09:22.604957 OTF = 0x1
704 23:09:22.608200 ===================================
705 23:09:22.614656 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
706 23:09:22.619252 nWR fixed to 40
707 23:09:22.622789 [ModeRegInit_LP4] CH0 RK0
708 23:09:22.622871 [ModeRegInit_LP4] CH0 RK1
709 23:09:22.625739 [ModeRegInit_LP4] CH1 RK0
710 23:09:22.629176 [ModeRegInit_LP4] CH1 RK1
711 23:09:22.629285 match AC timing 13
712 23:09:22.635590 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
713 23:09:22.639208 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
714 23:09:22.642349 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
715 23:09:22.649411 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
716 23:09:22.652894 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
717 23:09:22.652976 [EMI DOE] emi_dcm 0
718 23:09:22.659269 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
719 23:09:22.659351 ==
720 23:09:22.662686 Dram Type= 6, Freq= 0, CH_0, rank 0
721 23:09:22.666177 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
722 23:09:22.666260 ==
723 23:09:22.672786 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
724 23:09:22.676153 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
725 23:09:22.686669 [CA 0] Center 36 (6~67) winsize 62
726 23:09:22.689851 [CA 1] Center 36 (6~67) winsize 62
727 23:09:22.692935 [CA 2] Center 34 (4~65) winsize 62
728 23:09:22.696342 [CA 3] Center 34 (4~64) winsize 61
729 23:09:22.699825 [CA 4] Center 33 (2~64) winsize 63
730 23:09:22.702959 [CA 5] Center 32 (2~63) winsize 62
731 23:09:22.703042
732 23:09:22.706915 [CmdBusTrainingLP45] Vref(ca) range 1: 34
733 23:09:22.707016
734 23:09:22.709659 [CATrainingPosCal] consider 1 rank data
735 23:09:22.713303 u2DelayCellTimex100 = 270/100 ps
736 23:09:22.716639 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
737 23:09:22.720141 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
738 23:09:22.726742 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
739 23:09:22.730202 CA3 delay=34 (4~64),Diff = 2 PI (14 cell)
740 23:09:22.733087 CA4 delay=33 (2~64),Diff = 1 PI (7 cell)
741 23:09:22.736772 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
742 23:09:22.736854
743 23:09:22.740282 CA PerBit enable=1, Macro0, CA PI delay=32
744 23:09:22.740364
745 23:09:22.743762 [CBTSetCACLKResult] CA Dly = 32
746 23:09:22.743844 CS Dly: 4 (0~35)
747 23:09:22.743909 ==
748 23:09:22.746829 Dram Type= 6, Freq= 0, CH_0, rank 1
749 23:09:22.753941 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
750 23:09:22.754023 ==
751 23:09:22.756785 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
752 23:09:22.763831 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
753 23:09:22.773148 [CA 0] Center 36 (6~67) winsize 62
754 23:09:22.776068 [CA 1] Center 36 (6~67) winsize 62
755 23:09:22.779409 [CA 2] Center 34 (3~65) winsize 63
756 23:09:22.782598 [CA 3] Center 33 (3~64) winsize 62
757 23:09:22.786126 [CA 4] Center 33 (3~63) winsize 61
758 23:09:22.789747 [CA 5] Center 32 (2~63) winsize 62
759 23:09:22.789828
760 23:09:22.792701 [CmdBusTrainingLP45] Vref(ca) range 1: 32
761 23:09:22.792782
762 23:09:22.796141 [CATrainingPosCal] consider 2 rank data
763 23:09:22.799470 u2DelayCellTimex100 = 270/100 ps
764 23:09:22.802891 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
765 23:09:22.806005 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
766 23:09:22.812487 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
767 23:09:22.815988 CA3 delay=34 (4~64),Diff = 2 PI (14 cell)
768 23:09:22.819668 CA4 delay=33 (3~63),Diff = 1 PI (7 cell)
769 23:09:22.822718 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
770 23:09:22.822839
771 23:09:22.826050 CA PerBit enable=1, Macro0, CA PI delay=32
772 23:09:22.826132
773 23:09:22.829127 [CBTSetCACLKResult] CA Dly = 32
774 23:09:22.829209 CS Dly: 4 (0~36)
775 23:09:22.829274
776 23:09:22.832654 ----->DramcWriteLeveling(PI) begin...
777 23:09:22.836372 ==
778 23:09:22.836454 Dram Type= 6, Freq= 0, CH_0, rank 0
779 23:09:22.843330 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
780 23:09:22.843414 ==
781 23:09:22.846969 Write leveling (Byte 0): 32 => 32
782 23:09:22.847130 Write leveling (Byte 1): 29 => 29
783 23:09:22.850467 DramcWriteLeveling(PI) end<-----
784 23:09:22.850549
785 23:09:22.850633 ==
786 23:09:22.854191 Dram Type= 6, Freq= 0, CH_0, rank 0
787 23:09:22.857502 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
788 23:09:22.861058 ==
789 23:09:22.861139 [Gating] SW mode calibration
790 23:09:22.867913 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
791 23:09:22.874935 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
792 23:09:22.878260 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
793 23:09:22.881779 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
794 23:09:22.888350 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
795 23:09:22.891887 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 23:09:22.894822 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 23:09:22.901843 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 23:09:22.905161 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 23:09:22.908691 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 23:09:22.914864 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 23:09:22.918501 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 23:09:22.921910 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 23:09:22.928733 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 23:09:22.931640 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 23:09:22.935217 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 23:09:22.942224 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 23:09:22.945291 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 23:09:22.948306 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 23:09:22.951873 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
810 23:09:22.958632 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
811 23:09:22.961560 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 23:09:22.965203 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
813 23:09:22.972020 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
814 23:09:22.975330 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
815 23:09:22.978793 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
816 23:09:22.985558 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
817 23:09:22.988559 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
818 23:09:22.991782 0 9 8 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (1 1)
819 23:09:22.998878 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
820 23:09:23.002326 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
821 23:09:23.005107 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
822 23:09:23.011991 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
823 23:09:23.015598 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
824 23:09:23.018458 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
825 23:09:23.025296 0 10 4 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
826 23:09:23.028634 0 10 8 | B1->B0 | 3131 2525 | 0 0 | (0 1) (0 0)
827 23:09:23.032047 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 23:09:23.035556 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
829 23:09:23.041896 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
830 23:09:23.045387 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
831 23:09:23.048918 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
832 23:09:23.055076 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
833 23:09:23.058440 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
834 23:09:23.061812 0 11 8 | B1->B0 | 2d2d 3e3e | 0 0 | (0 0) (0 0)
835 23:09:23.068793 0 11 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
836 23:09:23.072260 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
837 23:09:23.075282 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
838 23:09:23.081808 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
839 23:09:23.085457 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
840 23:09:23.088679 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
841 23:09:23.095449 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
842 23:09:23.098825 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
843 23:09:23.101990 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 23:09:23.108862 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 23:09:23.112258 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 23:09:23.115582 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 23:09:23.118661 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 23:09:23.125809 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 23:09:23.128806 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 23:09:23.132151 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 23:09:23.138925 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
852 23:09:23.142381 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
853 23:09:23.145513 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
854 23:09:23.152224 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
855 23:09:23.155754 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
856 23:09:23.159158 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
857 23:09:23.165564 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
858 23:09:23.169498 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
859 23:09:23.172132 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
860 23:09:23.175682 Total UI for P1: 0, mck2ui 16
861 23:09:23.179166 best dqsien dly found for B0: ( 0, 14, 8)
862 23:09:23.182658 Total UI for P1: 0, mck2ui 16
863 23:09:23.185924 best dqsien dly found for B1: ( 0, 14, 8)
864 23:09:23.189367 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
865 23:09:23.193521 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
866 23:09:23.193627
867 23:09:23.196578 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
868 23:09:23.199579 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
869 23:09:23.203275 [Gating] SW calibration Done
870 23:09:23.203357 ==
871 23:09:23.206241 Dram Type= 6, Freq= 0, CH_0, rank 0
872 23:09:23.209922 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
873 23:09:23.210021 ==
874 23:09:23.213182 RX Vref Scan: 0
875 23:09:23.213335
876 23:09:23.216497 RX Vref 0 -> 0, step: 1
877 23:09:23.216582
878 23:09:23.216661 RX Delay -130 -> 252, step: 16
879 23:09:23.223148 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
880 23:09:23.226049 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
881 23:09:23.229391 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
882 23:09:23.233069 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
883 23:09:23.236455 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
884 23:09:23.242591 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
885 23:09:23.246136 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
886 23:09:23.249725 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
887 23:09:23.253133 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
888 23:09:23.256024 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
889 23:09:23.263003 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
890 23:09:23.266173 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
891 23:09:23.269489 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
892 23:09:23.272758 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
893 23:09:23.279585 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
894 23:09:23.283182 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
895 23:09:23.283281 ==
896 23:09:23.286061 Dram Type= 6, Freq= 0, CH_0, rank 0
897 23:09:23.289352 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
898 23:09:23.289505 ==
899 23:09:23.289621 DQS Delay:
900 23:09:23.292929 DQS0 = 0, DQS1 = 0
901 23:09:23.293011 DQM Delay:
902 23:09:23.296402 DQM0 = 90, DQM1 = 83
903 23:09:23.296490 DQ Delay:
904 23:09:23.299412 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =85
905 23:09:23.302822 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =101
906 23:09:23.306223 DQ8 =77, DQ9 =69, DQ10 =77, DQ11 =77
907 23:09:23.309520 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =85
908 23:09:23.309676
909 23:09:23.309794
910 23:09:23.309862 ==
911 23:09:23.312800 Dram Type= 6, Freq= 0, CH_0, rank 0
912 23:09:23.316178 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
913 23:09:23.319829 ==
914 23:09:23.319912
915 23:09:23.319978
916 23:09:23.320039 TX Vref Scan disable
917 23:09:23.322787 == TX Byte 0 ==
918 23:09:23.326253 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
919 23:09:23.329697 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
920 23:09:23.333238 == TX Byte 1 ==
921 23:09:23.336616 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
922 23:09:23.339606 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
923 23:09:23.339690 ==
924 23:09:23.342901 Dram Type= 6, Freq= 0, CH_0, rank 0
925 23:09:23.349684 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
926 23:09:23.349793 ==
927 23:09:23.361565 TX Vref=22, minBit 8, minWin=27, winSum=446
928 23:09:23.365040 TX Vref=24, minBit 8, minWin=27, winSum=448
929 23:09:23.368556 TX Vref=26, minBit 0, minWin=28, winSum=455
930 23:09:23.372041 TX Vref=28, minBit 8, minWin=28, winSum=457
931 23:09:23.375177 TX Vref=30, minBit 0, minWin=28, winSum=456
932 23:09:23.381891 TX Vref=32, minBit 2, minWin=28, winSum=458
933 23:09:23.385277 [TxChooseVref] Worse bit 2, Min win 28, Win sum 458, Final Vref 32
934 23:09:23.385359
935 23:09:23.388685 Final TX Range 1 Vref 32
936 23:09:23.388767
937 23:09:23.388832 ==
938 23:09:23.391966 Dram Type= 6, Freq= 0, CH_0, rank 0
939 23:09:23.395391 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
940 23:09:23.395491 ==
941 23:09:23.395590
942 23:09:23.398814
943 23:09:23.398895 TX Vref Scan disable
944 23:09:23.401836 == TX Byte 0 ==
945 23:09:23.405283 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
946 23:09:23.408281 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
947 23:09:23.411767 == TX Byte 1 ==
948 23:09:23.415117 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
949 23:09:23.418626 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
950 23:09:23.421964
951 23:09:23.422056 [DATLAT]
952 23:09:23.422122 Freq=800, CH0 RK0
953 23:09:23.422183
954 23:09:23.425159 DATLAT Default: 0xa
955 23:09:23.425297 0, 0xFFFF, sum = 0
956 23:09:23.428422 1, 0xFFFF, sum = 0
957 23:09:23.428541 2, 0xFFFF, sum = 0
958 23:09:23.431675 3, 0xFFFF, sum = 0
959 23:09:23.431759 4, 0xFFFF, sum = 0
960 23:09:23.435024 5, 0xFFFF, sum = 0
961 23:09:23.438514 6, 0xFFFF, sum = 0
962 23:09:23.438655 7, 0xFFFF, sum = 0
963 23:09:23.441921 8, 0xFFFF, sum = 0
964 23:09:23.442008 9, 0x0, sum = 1
965 23:09:23.442077 10, 0x0, sum = 2
966 23:09:23.445451 11, 0x0, sum = 3
967 23:09:23.445562 12, 0x0, sum = 4
968 23:09:23.448595 best_step = 10
969 23:09:23.448677
970 23:09:23.448743 ==
971 23:09:23.451892 Dram Type= 6, Freq= 0, CH_0, rank 0
972 23:09:23.455145 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
973 23:09:23.455229 ==
974 23:09:23.458731 RX Vref Scan: 1
975 23:09:23.458814
976 23:09:23.458880 Set Vref Range= 32 -> 127
977 23:09:23.458941
978 23:09:23.462077 RX Vref 32 -> 127, step: 1
979 23:09:23.462160
980 23:09:23.465750 RX Delay -95 -> 252, step: 8
981 23:09:23.465833
982 23:09:23.468665 Set Vref, RX VrefLevel [Byte0]: 32
983 23:09:23.471995 [Byte1]: 32
984 23:09:23.472078
985 23:09:23.475441 Set Vref, RX VrefLevel [Byte0]: 33
986 23:09:23.478861 [Byte1]: 33
987 23:09:23.482470
988 23:09:23.482553 Set Vref, RX VrefLevel [Byte0]: 34
989 23:09:23.485511 [Byte1]: 34
990 23:09:23.489824
991 23:09:23.489953 Set Vref, RX VrefLevel [Byte0]: 35
992 23:09:23.493216 [Byte1]: 35
993 23:09:23.497290
994 23:09:23.497371 Set Vref, RX VrefLevel [Byte0]: 36
995 23:09:23.500641 [Byte1]: 36
996 23:09:23.505253
997 23:09:23.505336 Set Vref, RX VrefLevel [Byte0]: 37
998 23:09:23.508746 [Byte1]: 37
999 23:09:23.513436
1000 23:09:23.513548 Set Vref, RX VrefLevel [Byte0]: 38
1001 23:09:23.516349 [Byte1]: 38
1002 23:09:23.520478
1003 23:09:23.520559 Set Vref, RX VrefLevel [Byte0]: 39
1004 23:09:23.523789 [Byte1]: 39
1005 23:09:23.528018
1006 23:09:23.528098 Set Vref, RX VrefLevel [Byte0]: 40
1007 23:09:23.531511 [Byte1]: 40
1008 23:09:23.536287
1009 23:09:23.536371 Set Vref, RX VrefLevel [Byte0]: 41
1010 23:09:23.539173 [Byte1]: 41
1011 23:09:23.542908
1012 23:09:23.542991 Set Vref, RX VrefLevel [Byte0]: 42
1013 23:09:23.546592 [Byte1]: 42
1014 23:09:23.550751
1015 23:09:23.550833 Set Vref, RX VrefLevel [Byte0]: 43
1016 23:09:23.553996 [Byte1]: 43
1017 23:09:23.558198
1018 23:09:23.558281 Set Vref, RX VrefLevel [Byte0]: 44
1019 23:09:23.561404 [Byte1]: 44
1020 23:09:23.565844
1021 23:09:23.565926 Set Vref, RX VrefLevel [Byte0]: 45
1022 23:09:23.569446 [Byte1]: 45
1023 23:09:23.573278
1024 23:09:23.573361 Set Vref, RX VrefLevel [Byte0]: 46
1025 23:09:23.576491 [Byte1]: 46
1026 23:09:23.581157
1027 23:09:23.581237 Set Vref, RX VrefLevel [Byte0]: 47
1028 23:09:23.584429 [Byte1]: 47
1029 23:09:23.588432
1030 23:09:23.588513 Set Vref, RX VrefLevel [Byte0]: 48
1031 23:09:23.592044 [Byte1]: 48
1032 23:09:23.595943
1033 23:09:23.596023 Set Vref, RX VrefLevel [Byte0]: 49
1034 23:09:23.599892 [Byte1]: 49
1035 23:09:23.603724
1036 23:09:23.603804 Set Vref, RX VrefLevel [Byte0]: 50
1037 23:09:23.607408 [Byte1]: 50
1038 23:09:23.611440
1039 23:09:23.611547 Set Vref, RX VrefLevel [Byte0]: 51
1040 23:09:23.614908 [Byte1]: 51
1041 23:09:23.618972
1042 23:09:23.619053 Set Vref, RX VrefLevel [Byte0]: 52
1043 23:09:23.622546 [Byte1]: 52
1044 23:09:23.626607
1045 23:09:23.626687 Set Vref, RX VrefLevel [Byte0]: 53
1046 23:09:23.629749 [Byte1]: 53
1047 23:09:23.634008
1048 23:09:23.634089 Set Vref, RX VrefLevel [Byte0]: 54
1049 23:09:23.637415 [Byte1]: 54
1050 23:09:23.641701
1051 23:09:23.641781 Set Vref, RX VrefLevel [Byte0]: 55
1052 23:09:23.645380 [Byte1]: 55
1053 23:09:23.649790
1054 23:09:23.649900 Set Vref, RX VrefLevel [Byte0]: 56
1055 23:09:23.652737 [Byte1]: 56
1056 23:09:23.656759
1057 23:09:23.656840 Set Vref, RX VrefLevel [Byte0]: 57
1058 23:09:23.660172 [Byte1]: 57
1059 23:09:23.664939
1060 23:09:23.665030 Set Vref, RX VrefLevel [Byte0]: 58
1061 23:09:23.667652 [Byte1]: 58
1062 23:09:23.672331
1063 23:09:23.672411 Set Vref, RX VrefLevel [Byte0]: 59
1064 23:09:23.675564 [Byte1]: 59
1065 23:09:23.679929
1066 23:09:23.680008 Set Vref, RX VrefLevel [Byte0]: 60
1067 23:09:23.682854 [Byte1]: 60
1068 23:09:23.687640
1069 23:09:23.687720 Set Vref, RX VrefLevel [Byte0]: 61
1070 23:09:23.690653 [Byte1]: 61
1071 23:09:23.695135
1072 23:09:23.695215 Set Vref, RX VrefLevel [Byte0]: 62
1073 23:09:23.698341 [Byte1]: 62
1074 23:09:23.702342
1075 23:09:23.702422 Set Vref, RX VrefLevel [Byte0]: 63
1076 23:09:23.705805 [Byte1]: 63
1077 23:09:23.710127
1078 23:09:23.710207 Set Vref, RX VrefLevel [Byte0]: 64
1079 23:09:23.713317 [Byte1]: 64
1080 23:09:23.717611
1081 23:09:23.717706 Set Vref, RX VrefLevel [Byte0]: 65
1082 23:09:23.721090 [Byte1]: 65
1083 23:09:23.725312
1084 23:09:23.725392 Set Vref, RX VrefLevel [Byte0]: 66
1085 23:09:23.728949 [Byte1]: 66
1086 23:09:23.732821
1087 23:09:23.732901 Set Vref, RX VrefLevel [Byte0]: 67
1088 23:09:23.736096 [Byte1]: 67
1089 23:09:23.740399
1090 23:09:23.740479 Set Vref, RX VrefLevel [Byte0]: 68
1091 23:09:23.743849 [Byte1]: 68
1092 23:09:23.747886
1093 23:09:23.747966 Set Vref, RX VrefLevel [Byte0]: 69
1094 23:09:23.751524 [Byte1]: 69
1095 23:09:23.755547
1096 23:09:23.755627 Set Vref, RX VrefLevel [Byte0]: 70
1097 23:09:23.758957 [Byte1]: 70
1098 23:09:23.763579
1099 23:09:23.763658 Set Vref, RX VrefLevel [Byte0]: 71
1100 23:09:23.766783 [Byte1]: 71
1101 23:09:23.771004
1102 23:09:23.771083 Set Vref, RX VrefLevel [Byte0]: 72
1103 23:09:23.774424 [Byte1]: 72
1104 23:09:23.778694
1105 23:09:23.778774 Set Vref, RX VrefLevel [Byte0]: 73
1106 23:09:23.781544 [Byte1]: 73
1107 23:09:23.786224
1108 23:09:23.786303 Set Vref, RX VrefLevel [Byte0]: 74
1109 23:09:23.789713 [Byte1]: 74
1110 23:09:23.793565
1111 23:09:23.793682 Set Vref, RX VrefLevel [Byte0]: 75
1112 23:09:23.797067 [Byte1]: 75
1113 23:09:23.801089
1114 23:09:23.801168 Set Vref, RX VrefLevel [Byte0]: 76
1115 23:09:23.804612 [Byte1]: 76
1116 23:09:23.808808
1117 23:09:23.808887 Set Vref, RX VrefLevel [Byte0]: 77
1118 23:09:23.812353 [Byte1]: 77
1119 23:09:23.816474
1120 23:09:23.816579 Set Vref, RX VrefLevel [Byte0]: 78
1121 23:09:23.823027 [Byte1]: 78
1122 23:09:23.823109
1123 23:09:23.826125 Final RX Vref Byte 0 = 58 to rank0
1124 23:09:23.829542 Final RX Vref Byte 1 = 57 to rank0
1125 23:09:23.832892 Final RX Vref Byte 0 = 58 to rank1
1126 23:09:23.836476 Final RX Vref Byte 1 = 57 to rank1==
1127 23:09:23.839800 Dram Type= 6, Freq= 0, CH_0, rank 0
1128 23:09:23.842792 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1129 23:09:23.842874 ==
1130 23:09:23.842938 DQS Delay:
1131 23:09:23.846280 DQS0 = 0, DQS1 = 0
1132 23:09:23.846360 DQM Delay:
1133 23:09:23.849437 DQM0 = 92, DQM1 = 84
1134 23:09:23.849517 DQ Delay:
1135 23:09:23.852670 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88
1136 23:09:23.856166 DQ4 =96, DQ5 =80, DQ6 =100, DQ7 =100
1137 23:09:23.859684 DQ8 =72, DQ9 =76, DQ10 =84, DQ11 =76
1138 23:09:23.863190 DQ12 =92, DQ13 =92, DQ14 =92, DQ15 =92
1139 23:09:23.863271
1140 23:09:23.863334
1141 23:09:23.869609 [DQSOSCAuto] RK0, (LSB)MR18= 0x4e45, (MSB)MR19= 0x606, tDQSOscB0 = 392 ps tDQSOscB1 = 390 ps
1142 23:09:23.873063 CH0 RK0: MR19=606, MR18=4E45
1143 23:09:23.879671 CH0_RK0: MR19=0x606, MR18=0x4E45, DQSOSC=390, MR23=63, INC=97, DEC=64
1144 23:09:23.879754
1145 23:09:23.882683 ----->DramcWriteLeveling(PI) begin...
1146 23:09:23.882764 ==
1147 23:09:23.886174 Dram Type= 6, Freq= 0, CH_0, rank 1
1148 23:09:23.890024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1149 23:09:23.890105 ==
1150 23:09:23.893199 Write leveling (Byte 0): 34 => 34
1151 23:09:23.896163 Write leveling (Byte 1): 29 => 29
1152 23:09:23.899556 DramcWriteLeveling(PI) end<-----
1153 23:09:23.899637
1154 23:09:23.899700 ==
1155 23:09:23.903365 Dram Type= 6, Freq= 0, CH_0, rank 1
1156 23:09:23.906221 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1157 23:09:23.950387 ==
1158 23:09:23.950484 [Gating] SW mode calibration
1159 23:09:23.950734 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1160 23:09:23.950803 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1161 23:09:23.950873 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1162 23:09:23.951117 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1163 23:09:23.951180 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1164 23:09:23.951275 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1165 23:09:23.951340 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 23:09:23.951441 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 23:09:23.994443 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 23:09:23.995018 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 23:09:23.995100 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 23:09:23.995437 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 23:09:23.996018 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 23:09:23.996569 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 23:09:23.996845 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 23:09:23.996917 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 23:09:23.996991 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 23:09:23.997243 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 23:09:24.038838 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 23:09:24.039622 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1179 23:09:24.039713 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1180 23:09:24.039967 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1181 23:09:24.040044 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 23:09:24.040117 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1183 23:09:24.040205 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 23:09:24.040279 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 23:09:24.040386 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 23:09:24.040633 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 23:09:24.051855 0 9 8 | B1->B0 | 2f2f 2c2c | 1 0 | (1 1) (1 0)
1188 23:09:24.052124 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1189 23:09:24.052196 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1190 23:09:24.055152 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1191 23:09:24.058360 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1192 23:09:24.064956 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1193 23:09:24.068455 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1194 23:09:24.071569 0 10 4 | B1->B0 | 3131 3232 | 1 0 | (1 1) (0 0)
1195 23:09:24.078554 0 10 8 | B1->B0 | 2727 2929 | 0 0 | (0 0) (1 0)
1196 23:09:24.082218 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1197 23:09:24.085760 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1198 23:09:24.089249 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1199 23:09:24.093357 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1200 23:09:24.100018 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1201 23:09:24.103665 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1202 23:09:24.106659 0 11 4 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
1203 23:09:24.110338 0 11 8 | B1->B0 | 4141 3b3b | 0 0 | (0 0) (0 0)
1204 23:09:24.117420 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1205 23:09:24.120931 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1206 23:09:24.124120 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1207 23:09:24.130768 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1208 23:09:24.134478 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1209 23:09:24.137715 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1210 23:09:24.144085 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1211 23:09:24.147348 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1212 23:09:24.151144 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 23:09:24.157699 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 23:09:24.160647 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 23:09:24.164341 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 23:09:24.170618 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 23:09:24.174298 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 23:09:24.177689 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1219 23:09:24.184016 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1220 23:09:24.187407 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1221 23:09:24.190947 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1222 23:09:24.193967 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1223 23:09:24.200576 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1224 23:09:24.203837 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1225 23:09:24.207424 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1226 23:09:24.214100 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1227 23:09:24.217486 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1228 23:09:24.220612 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1229 23:09:24.224354 Total UI for P1: 0, mck2ui 16
1230 23:09:24.227525 best dqsien dly found for B1: ( 0, 14, 8)
1231 23:09:24.234226 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1232 23:09:24.234326 Total UI for P1: 0, mck2ui 16
1233 23:09:24.240614 best dqsien dly found for B0: ( 0, 14, 10)
1234 23:09:24.244149 best DQS0 dly(MCK, UI, PI) = (0, 14, 10)
1235 23:09:24.247454 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1236 23:09:24.247536
1237 23:09:24.250657 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 10)
1238 23:09:24.254009 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1239 23:09:24.257794 [Gating] SW calibration Done
1240 23:09:24.257875 ==
1241 23:09:24.260752 Dram Type= 6, Freq= 0, CH_0, rank 1
1242 23:09:24.264288 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1243 23:09:24.264369 ==
1244 23:09:24.267819 RX Vref Scan: 0
1245 23:09:24.267899
1246 23:09:24.267963 RX Vref 0 -> 0, step: 1
1247 23:09:24.268025
1248 23:09:24.270729 RX Delay -130 -> 252, step: 16
1249 23:09:24.274064 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1250 23:09:24.280680 iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224
1251 23:09:24.284502 iDelay=206, Bit 2, Center 85 (-34 ~ 205) 240
1252 23:09:24.287847 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1253 23:09:24.291239 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1254 23:09:24.294295 iDelay=206, Bit 5, Center 85 (-34 ~ 205) 240
1255 23:09:24.297814 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1256 23:09:24.304374 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1257 23:09:24.307776 iDelay=206, Bit 8, Center 77 (-34 ~ 189) 224
1258 23:09:24.311344 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1259 23:09:24.314214 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
1260 23:09:24.317803 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1261 23:09:24.324531 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1262 23:09:24.327922 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1263 23:09:24.331391 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
1264 23:09:24.334637 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1265 23:09:24.334717 ==
1266 23:09:24.337791 Dram Type= 6, Freq= 0, CH_0, rank 1
1267 23:09:24.344632 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1268 23:09:24.344714 ==
1269 23:09:24.344778 DQS Delay:
1270 23:09:24.348100 DQS0 = 0, DQS1 = 0
1271 23:09:24.348180 DQM Delay:
1272 23:09:24.348243 DQM0 = 90, DQM1 = 81
1273 23:09:24.351337 DQ Delay:
1274 23:09:24.354937 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =85
1275 23:09:24.355017 DQ4 =93, DQ5 =85, DQ6 =93, DQ7 =93
1276 23:09:24.357980 DQ8 =77, DQ9 =69, DQ10 =77, DQ11 =77
1277 23:09:24.364829 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85
1278 23:09:24.364908
1279 23:09:24.364971
1280 23:09:24.365029 ==
1281 23:09:24.367972 Dram Type= 6, Freq= 0, CH_0, rank 1
1282 23:09:24.371594 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1283 23:09:24.371674 ==
1284 23:09:24.371737
1285 23:09:24.371795
1286 23:09:24.374450 TX Vref Scan disable
1287 23:09:24.374529 == TX Byte 0 ==
1288 23:09:24.381489 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
1289 23:09:24.384354 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
1290 23:09:24.384435 == TX Byte 1 ==
1291 23:09:24.391310 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1292 23:09:24.394724 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1293 23:09:24.394805 ==
1294 23:09:24.398176 Dram Type= 6, Freq= 0, CH_0, rank 1
1295 23:09:24.401597 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1296 23:09:24.401693 ==
1297 23:09:24.416086 TX Vref=22, minBit 8, minWin=27, winSum=446
1298 23:09:24.418822 TX Vref=24, minBit 8, minWin=27, winSum=449
1299 23:09:24.422339 TX Vref=26, minBit 11, minWin=27, winSum=455
1300 23:09:24.425553 TX Vref=28, minBit 7, minWin=28, winSum=458
1301 23:09:24.428797 TX Vref=30, minBit 3, minWin=28, winSum=459
1302 23:09:24.432397 TX Vref=32, minBit 0, minWin=28, winSum=456
1303 23:09:24.439138 [TxChooseVref] Worse bit 3, Min win 28, Win sum 459, Final Vref 30
1304 23:09:24.439220
1305 23:09:24.442590 Final TX Range 1 Vref 30
1306 23:09:24.442672
1307 23:09:24.442735 ==
1308 23:09:24.445777 Dram Type= 6, Freq= 0, CH_0, rank 1
1309 23:09:24.449131 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1310 23:09:24.449211 ==
1311 23:09:24.449275
1312 23:09:24.452502
1313 23:09:24.452581 TX Vref Scan disable
1314 23:09:24.455844 == TX Byte 0 ==
1315 23:09:24.458791 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
1316 23:09:24.462355 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
1317 23:09:24.465621 == TX Byte 1 ==
1318 23:09:24.469098 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1319 23:09:24.472365 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1320 23:09:24.475610
1321 23:09:24.475689 [DATLAT]
1322 23:09:24.475752 Freq=800, CH0 RK1
1323 23:09:24.475810
1324 23:09:24.478959 DATLAT Default: 0xa
1325 23:09:24.479038 0, 0xFFFF, sum = 0
1326 23:09:24.482353 1, 0xFFFF, sum = 0
1327 23:09:24.482434 2, 0xFFFF, sum = 0
1328 23:09:24.485877 3, 0xFFFF, sum = 0
1329 23:09:24.485958 4, 0xFFFF, sum = 0
1330 23:09:24.489302 5, 0xFFFF, sum = 0
1331 23:09:24.492207 6, 0xFFFF, sum = 0
1332 23:09:24.492287 7, 0xFFFF, sum = 0
1333 23:09:24.495581 8, 0xFFFF, sum = 0
1334 23:09:24.495661 9, 0x0, sum = 1
1335 23:09:24.495726 10, 0x0, sum = 2
1336 23:09:24.498989 11, 0x0, sum = 3
1337 23:09:24.499070 12, 0x0, sum = 4
1338 23:09:24.502596 best_step = 10
1339 23:09:24.502675
1340 23:09:24.502737 ==
1341 23:09:24.505480 Dram Type= 6, Freq= 0, CH_0, rank 1
1342 23:09:24.508953 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1343 23:09:24.509033 ==
1344 23:09:24.512363 RX Vref Scan: 0
1345 23:09:24.512442
1346 23:09:24.512504 RX Vref 0 -> 0, step: 1
1347 23:09:24.512563
1348 23:09:24.515668 RX Delay -95 -> 252, step: 8
1349 23:09:24.522401 iDelay=209, Bit 0, Center 92 (-15 ~ 200) 216
1350 23:09:24.525820 iDelay=209, Bit 1, Center 96 (-7 ~ 200) 208
1351 23:09:24.529122 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1352 23:09:24.532197 iDelay=209, Bit 3, Center 88 (-23 ~ 200) 224
1353 23:09:24.535787 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1354 23:09:24.542477 iDelay=209, Bit 5, Center 88 (-23 ~ 200) 224
1355 23:09:24.545910 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1356 23:09:24.549204 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1357 23:09:24.552136 iDelay=209, Bit 8, Center 76 (-31 ~ 184) 216
1358 23:09:24.555516 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1359 23:09:24.562395 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1360 23:09:24.565789 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1361 23:09:24.569008 iDelay=209, Bit 12, Center 88 (-15 ~ 192) 208
1362 23:09:24.572278 iDelay=209, Bit 13, Center 92 (-15 ~ 200) 216
1363 23:09:24.575609 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1364 23:09:24.582407 iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216
1365 23:09:24.582488 ==
1366 23:09:24.585684 Dram Type= 6, Freq= 0, CH_0, rank 1
1367 23:09:24.589006 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1368 23:09:24.589087 ==
1369 23:09:24.589150 DQS Delay:
1370 23:09:24.592520 DQS0 = 0, DQS1 = 0
1371 23:09:24.592601 DQM Delay:
1372 23:09:24.595999 DQM0 = 93, DQM1 = 84
1373 23:09:24.596079 DQ Delay:
1374 23:09:24.599222 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1375 23:09:24.602743 DQ4 =92, DQ5 =88, DQ6 =100, DQ7 =100
1376 23:09:24.606180 DQ8 =76, DQ9 =72, DQ10 =84, DQ11 =76
1377 23:09:24.609227 DQ12 =88, DQ13 =92, DQ14 =92, DQ15 =92
1378 23:09:24.609307
1379 23:09:24.609370
1380 23:09:24.616143 [DQSOSCAuto] RK1, (LSB)MR18= 0x3f0f, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 393 ps
1381 23:09:24.619664 CH0 RK1: MR19=606, MR18=3F0F
1382 23:09:24.625828 CH0_RK1: MR19=0x606, MR18=0x3F0F, DQSOSC=393, MR23=63, INC=95, DEC=63
1383 23:09:24.629228 [RxdqsGatingPostProcess] freq 800
1384 23:09:24.635891 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1385 23:09:24.635972 Pre-setting of DQS Precalculation
1386 23:09:24.642512 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1387 23:09:24.642594 ==
1388 23:09:24.645778 Dram Type= 6, Freq= 0, CH_1, rank 0
1389 23:09:24.649418 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1390 23:09:24.649503 ==
1391 23:09:24.655878 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1392 23:09:24.662528 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1393 23:09:24.670937 [CA 0] Center 36 (6~67) winsize 62
1394 23:09:24.674334 [CA 1] Center 37 (6~68) winsize 63
1395 23:09:24.677698 [CA 2] Center 35 (4~66) winsize 63
1396 23:09:24.680890 [CA 3] Center 34 (4~65) winsize 62
1397 23:09:24.684268 [CA 4] Center 34 (4~65) winsize 62
1398 23:09:24.687760 [CA 5] Center 34 (4~64) winsize 61
1399 23:09:24.687841
1400 23:09:24.690662 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1401 23:09:24.690743
1402 23:09:24.694512 [CATrainingPosCal] consider 1 rank data
1403 23:09:24.697420 u2DelayCellTimex100 = 270/100 ps
1404 23:09:24.700685 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1405 23:09:24.704176 CA1 delay=37 (6~68),Diff = 3 PI (21 cell)
1406 23:09:24.710486 CA2 delay=35 (4~66),Diff = 1 PI (7 cell)
1407 23:09:24.713960 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1408 23:09:24.717538 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1409 23:09:24.720492 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1410 23:09:24.720573
1411 23:09:24.724029 CA PerBit enable=1, Macro0, CA PI delay=34
1412 23:09:24.724110
1413 23:09:24.727011 [CBTSetCACLKResult] CA Dly = 34
1414 23:09:24.727091 CS Dly: 6 (0~37)
1415 23:09:24.730506 ==
1416 23:09:24.730586 Dram Type= 6, Freq= 0, CH_1, rank 1
1417 23:09:24.737429 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1418 23:09:24.737536 ==
1419 23:09:24.740876 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1420 23:09:24.747466 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1421 23:09:24.757251 [CA 0] Center 36 (6~67) winsize 62
1422 23:09:24.760801 [CA 1] Center 36 (6~67) winsize 62
1423 23:09:24.765237 [CA 2] Center 35 (5~66) winsize 62
1424 23:09:24.768659 [CA 3] Center 34 (4~65) winsize 62
1425 23:09:24.772820 [CA 4] Center 35 (4~66) winsize 63
1426 23:09:24.772901 [CA 5] Center 34 (4~65) winsize 62
1427 23:09:24.772965
1428 23:09:24.776622 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1429 23:09:24.776703
1430 23:09:24.780377 [CATrainingPosCal] consider 2 rank data
1431 23:09:24.783720 u2DelayCellTimex100 = 270/100 ps
1432 23:09:24.787767 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1433 23:09:24.790624 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1434 23:09:24.794401 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
1435 23:09:24.797203 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1436 23:09:24.804053 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1437 23:09:24.807460 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1438 23:09:24.807541
1439 23:09:24.810848 CA PerBit enable=1, Macro0, CA PI delay=34
1440 23:09:24.810928
1441 23:09:24.814401 [CBTSetCACLKResult] CA Dly = 34
1442 23:09:24.814482 CS Dly: 7 (0~39)
1443 23:09:24.814546
1444 23:09:24.817785 ----->DramcWriteLeveling(PI) begin...
1445 23:09:24.817867 ==
1446 23:09:24.820750 Dram Type= 6, Freq= 0, CH_1, rank 0
1447 23:09:24.824124 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1448 23:09:24.827808 ==
1449 23:09:24.831254 Write leveling (Byte 0): 29 => 29
1450 23:09:24.831335 Write leveling (Byte 1): 29 => 29
1451 23:09:24.834171 DramcWriteLeveling(PI) end<-----
1452 23:09:24.834257
1453 23:09:24.834365 ==
1454 23:09:24.837637 Dram Type= 6, Freq= 0, CH_1, rank 0
1455 23:09:24.844364 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1456 23:09:24.844446 ==
1457 23:09:24.847690 [Gating] SW mode calibration
1458 23:09:24.854740 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1459 23:09:24.857615 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1460 23:09:24.861001 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1461 23:09:24.867896 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1462 23:09:24.870893 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 23:09:24.875045 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 23:09:24.881443 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 23:09:24.884446 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 23:09:24.887547 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 23:09:24.894498 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 23:09:24.897715 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 23:09:24.901173 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 23:09:24.907537 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 23:09:24.910884 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 23:09:24.914412 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 23:09:24.920784 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 23:09:24.924248 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 23:09:24.927844 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 23:09:24.934275 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1477 23:09:24.937869 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1478 23:09:24.941324 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1479 23:09:24.944450 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1480 23:09:24.951129 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1481 23:09:24.954562 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1482 23:09:24.958075 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 23:09:24.964547 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 23:09:24.967929 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 23:09:24.971422 0 9 4 | B1->B0 | 2323 2424 | 0 1 | (0 0) (1 1)
1486 23:09:24.977874 0 9 8 | B1->B0 | 2e2e 3434 | 1 1 | (1 1) (1 1)
1487 23:09:24.981212 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1488 23:09:24.984821 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1489 23:09:24.991595 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1490 23:09:24.994367 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1491 23:09:24.998006 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1492 23:09:25.004664 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
1493 23:09:25.008078 0 10 4 | B1->B0 | 3232 2f2f | 0 0 | (0 0) (1 1)
1494 23:09:25.011403 0 10 8 | B1->B0 | 2626 2323 | 0 0 | (0 0) (1 0)
1495 23:09:25.017719 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1496 23:09:25.021111 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1497 23:09:25.024868 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1498 23:09:25.031447 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1499 23:09:25.034484 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1500 23:09:25.038124 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1501 23:09:25.041488 0 11 4 | B1->B0 | 2929 3535 | 0 0 | (0 0) (1 1)
1502 23:09:25.047988 0 11 8 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
1503 23:09:25.051305 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1504 23:09:25.054632 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1505 23:09:25.061379 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1506 23:09:25.064891 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1507 23:09:25.067926 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1508 23:09:25.074872 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1509 23:09:25.078263 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1510 23:09:25.081862 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 23:09:25.088145 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 23:09:25.091665 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 23:09:25.094951 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 23:09:25.101379 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 23:09:25.104718 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 23:09:25.108086 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1517 23:09:25.111570 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1518 23:09:25.118350 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1519 23:09:25.121731 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1520 23:09:25.125241 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1521 23:09:25.131889 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1522 23:09:25.134845 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1523 23:09:25.138102 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1524 23:09:25.145083 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1525 23:09:25.148170 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1526 23:09:25.151678 Total UI for P1: 0, mck2ui 16
1527 23:09:25.154762 best dqsien dly found for B1: ( 0, 14, 2)
1528 23:09:25.158450 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1529 23:09:25.161539 Total UI for P1: 0, mck2ui 16
1530 23:09:25.165140 best dqsien dly found for B0: ( 0, 14, 4)
1531 23:09:25.168462 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1532 23:09:25.171737 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1533 23:09:25.171812
1534 23:09:25.175252 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1535 23:09:25.181919 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1536 23:09:25.181996 [Gating] SW calibration Done
1537 23:09:25.182063 ==
1538 23:09:25.185319 Dram Type= 6, Freq= 0, CH_1, rank 0
1539 23:09:25.191596 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1540 23:09:25.191672 ==
1541 23:09:25.191733 RX Vref Scan: 0
1542 23:09:25.191790
1543 23:09:25.195442 RX Vref 0 -> 0, step: 1
1544 23:09:25.195507
1545 23:09:25.198562 RX Delay -130 -> 252, step: 16
1546 23:09:25.201909 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1547 23:09:25.205305 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1548 23:09:25.208503 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1549 23:09:25.214982 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1550 23:09:25.218421 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1551 23:09:25.221840 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1552 23:09:25.225213 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1553 23:09:25.228326 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1554 23:09:25.232016 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1555 23:09:25.238211 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1556 23:09:25.241535 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1557 23:09:25.244914 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1558 23:09:25.248501 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1559 23:09:25.251960 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1560 23:09:25.258411 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1561 23:09:25.262057 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1562 23:09:25.262191 ==
1563 23:09:25.265384 Dram Type= 6, Freq= 0, CH_1, rank 0
1564 23:09:25.268655 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1565 23:09:25.268754 ==
1566 23:09:25.271980 DQS Delay:
1567 23:09:25.272067 DQS0 = 0, DQS1 = 0
1568 23:09:25.272130 DQM Delay:
1569 23:09:25.275094 DQM0 = 92, DQM1 = 87
1570 23:09:25.275169 DQ Delay:
1571 23:09:25.278529 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1572 23:09:25.281922 DQ4 =93, DQ5 =109, DQ6 =93, DQ7 =93
1573 23:09:25.285190 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =85
1574 23:09:25.288718 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1575 23:09:25.288820
1576 23:09:25.288882
1577 23:09:25.288940 ==
1578 23:09:25.292101 Dram Type= 6, Freq= 0, CH_1, rank 0
1579 23:09:25.298515 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1580 23:09:25.298593 ==
1581 23:09:25.298655
1582 23:09:25.298712
1583 23:09:25.298768 TX Vref Scan disable
1584 23:09:25.301965 == TX Byte 0 ==
1585 23:09:25.305043 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1586 23:09:25.312012 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1587 23:09:25.312092 == TX Byte 1 ==
1588 23:09:25.315381 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1589 23:09:25.322135 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1590 23:09:25.322217 ==
1591 23:09:25.325502 Dram Type= 6, Freq= 0, CH_1, rank 0
1592 23:09:25.329032 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1593 23:09:25.329110 ==
1594 23:09:25.341136 TX Vref=22, minBit 0, minWin=27, winSum=435
1595 23:09:25.344399 TX Vref=24, minBit 0, minWin=27, winSum=440
1596 23:09:25.347698 TX Vref=26, minBit 0, minWin=27, winSum=444
1597 23:09:25.351003 TX Vref=28, minBit 0, minWin=27, winSum=445
1598 23:09:25.354675 TX Vref=30, minBit 0, minWin=27, winSum=447
1599 23:09:25.357732 TX Vref=32, minBit 0, minWin=27, winSum=449
1600 23:09:25.364160 [TxChooseVref] Worse bit 0, Min win 27, Win sum 449, Final Vref 32
1601 23:09:25.364275
1602 23:09:25.368009 Final TX Range 1 Vref 32
1603 23:09:25.368078
1604 23:09:25.368136 ==
1605 23:09:25.370933 Dram Type= 6, Freq= 0, CH_1, rank 0
1606 23:09:25.374616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1607 23:09:25.374704 ==
1608 23:09:25.374764
1609 23:09:25.377784
1610 23:09:25.377851 TX Vref Scan disable
1611 23:09:25.381038 == TX Byte 0 ==
1612 23:09:25.384452 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1613 23:09:25.387529 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1614 23:09:25.391197 == TX Byte 1 ==
1615 23:09:25.394557 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1616 23:09:25.397810 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1617 23:09:25.401316
1618 23:09:25.401392 [DATLAT]
1619 23:09:25.401455 Freq=800, CH1 RK0
1620 23:09:25.401514
1621 23:09:25.404401 DATLAT Default: 0xa
1622 23:09:25.404508 0, 0xFFFF, sum = 0
1623 23:09:25.407716 1, 0xFFFF, sum = 0
1624 23:09:25.407808 2, 0xFFFF, sum = 0
1625 23:09:25.411300 3, 0xFFFF, sum = 0
1626 23:09:25.411380 4, 0xFFFF, sum = 0
1627 23:09:25.414404 5, 0xFFFF, sum = 0
1628 23:09:25.417655 6, 0xFFFF, sum = 0
1629 23:09:25.417727 7, 0xFFFF, sum = 0
1630 23:09:25.421033 8, 0xFFFF, sum = 0
1631 23:09:25.421103 9, 0x0, sum = 1
1632 23:09:25.421163 10, 0x0, sum = 2
1633 23:09:25.424373 11, 0x0, sum = 3
1634 23:09:25.424495 12, 0x0, sum = 4
1635 23:09:25.428189 best_step = 10
1636 23:09:25.428272
1637 23:09:25.428387 ==
1638 23:09:25.431039 Dram Type= 6, Freq= 0, CH_1, rank 0
1639 23:09:25.434443 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1640 23:09:25.434514 ==
1641 23:09:25.437525 RX Vref Scan: 1
1642 23:09:25.437687
1643 23:09:25.437748 Set Vref Range= 32 -> 127
1644 23:09:25.437805
1645 23:09:25.441488 RX Vref 32 -> 127, step: 1
1646 23:09:25.441605
1647 23:09:25.444188 RX Delay -79 -> 252, step: 8
1648 23:09:25.444255
1649 23:09:25.447774 Set Vref, RX VrefLevel [Byte0]: 32
1650 23:09:25.451375 [Byte1]: 32
1651 23:09:25.451442
1652 23:09:25.454820 Set Vref, RX VrefLevel [Byte0]: 33
1653 23:09:25.457481 [Byte1]: 33
1654 23:09:25.461453
1655 23:09:25.461548 Set Vref, RX VrefLevel [Byte0]: 34
1656 23:09:25.464554 [Byte1]: 34
1657 23:09:25.468928
1658 23:09:25.468996 Set Vref, RX VrefLevel [Byte0]: 35
1659 23:09:25.472111 [Byte1]: 35
1660 23:09:25.476183
1661 23:09:25.476268 Set Vref, RX VrefLevel [Byte0]: 36
1662 23:09:25.479611 [Byte1]: 36
1663 23:09:25.483837
1664 23:09:25.483947 Set Vref, RX VrefLevel [Byte0]: 37
1665 23:09:25.487359 [Byte1]: 37
1666 23:09:25.491659
1667 23:09:25.491739 Set Vref, RX VrefLevel [Byte0]: 38
1668 23:09:25.494597 [Byte1]: 38
1669 23:09:25.499079
1670 23:09:25.499181 Set Vref, RX VrefLevel [Byte0]: 39
1671 23:09:25.505496 [Byte1]: 39
1672 23:09:25.505618
1673 23:09:25.508991 Set Vref, RX VrefLevel [Byte0]: 40
1674 23:09:25.512059 [Byte1]: 40
1675 23:09:25.512129
1676 23:09:25.515382 Set Vref, RX VrefLevel [Byte0]: 41
1677 23:09:25.518986 [Byte1]: 41
1678 23:09:25.519062
1679 23:09:25.522344 Set Vref, RX VrefLevel [Byte0]: 42
1680 23:09:25.525297 [Byte1]: 42
1681 23:09:25.529414
1682 23:09:25.529513 Set Vref, RX VrefLevel [Byte0]: 43
1683 23:09:25.532806 [Byte1]: 43
1684 23:09:25.536558
1685 23:09:25.539901 Set Vref, RX VrefLevel [Byte0]: 44
1686 23:09:25.540028 [Byte1]: 44
1687 23:09:25.544509
1688 23:09:25.544583 Set Vref, RX VrefLevel [Byte0]: 45
1689 23:09:25.547844 [Byte1]: 45
1690 23:09:25.551870
1691 23:09:25.551938 Set Vref, RX VrefLevel [Byte0]: 46
1692 23:09:25.555434 [Byte1]: 46
1693 23:09:25.559521
1694 23:09:25.559594 Set Vref, RX VrefLevel [Byte0]: 47
1695 23:09:25.562862 [Byte1]: 47
1696 23:09:25.566803
1697 23:09:25.566870 Set Vref, RX VrefLevel [Byte0]: 48
1698 23:09:25.570297 [Byte1]: 48
1699 23:09:25.574644
1700 23:09:25.574714 Set Vref, RX VrefLevel [Byte0]: 49
1701 23:09:25.577678 [Byte1]: 49
1702 23:09:25.582277
1703 23:09:25.582388 Set Vref, RX VrefLevel [Byte0]: 50
1704 23:09:25.585125 [Byte1]: 50
1705 23:09:25.589521
1706 23:09:25.589668 Set Vref, RX VrefLevel [Byte0]: 51
1707 23:09:25.592838 [Byte1]: 51
1708 23:09:25.597274
1709 23:09:25.597383 Set Vref, RX VrefLevel [Byte0]: 52
1710 23:09:25.600233 [Byte1]: 52
1711 23:09:25.604822
1712 23:09:25.604929 Set Vref, RX VrefLevel [Byte0]: 53
1713 23:09:25.608019 [Byte1]: 53
1714 23:09:25.612360
1715 23:09:25.612465 Set Vref, RX VrefLevel [Byte0]: 54
1716 23:09:25.615590 [Byte1]: 54
1717 23:09:25.619620
1718 23:09:25.619729 Set Vref, RX VrefLevel [Byte0]: 55
1719 23:09:25.623238 [Byte1]: 55
1720 23:09:25.627387
1721 23:09:25.627496 Set Vref, RX VrefLevel [Byte0]: 56
1722 23:09:25.630428 [Byte1]: 56
1723 23:09:25.635290
1724 23:09:25.635397 Set Vref, RX VrefLevel [Byte0]: 57
1725 23:09:25.638073 [Byte1]: 57
1726 23:09:25.642251
1727 23:09:25.642358 Set Vref, RX VrefLevel [Byte0]: 58
1728 23:09:25.645497 [Byte1]: 58
1729 23:09:25.649863
1730 23:09:25.649971 Set Vref, RX VrefLevel [Byte0]: 59
1731 23:09:25.653307 [Byte1]: 59
1732 23:09:25.657343
1733 23:09:25.657450 Set Vref, RX VrefLevel [Byte0]: 60
1734 23:09:25.660747 [Byte1]: 60
1735 23:09:25.665369
1736 23:09:25.665476 Set Vref, RX VrefLevel [Byte0]: 61
1737 23:09:25.668583 [Byte1]: 61
1738 23:09:25.672685
1739 23:09:25.672792 Set Vref, RX VrefLevel [Byte0]: 62
1740 23:09:25.676145 [Byte1]: 62
1741 23:09:25.680020
1742 23:09:25.680126 Set Vref, RX VrefLevel [Byte0]: 63
1743 23:09:25.684110 [Byte1]: 63
1744 23:09:25.687984
1745 23:09:25.688091 Set Vref, RX VrefLevel [Byte0]: 64
1746 23:09:25.691001 [Byte1]: 64
1747 23:09:25.695147
1748 23:09:25.695256 Set Vref, RX VrefLevel [Byte0]: 65
1749 23:09:25.698643 [Byte1]: 65
1750 23:09:25.702981
1751 23:09:25.703094 Set Vref, RX VrefLevel [Byte0]: 66
1752 23:09:25.706332 [Byte1]: 66
1753 23:09:25.710227
1754 23:09:25.710334 Set Vref, RX VrefLevel [Byte0]: 67
1755 23:09:25.713755 [Byte1]: 67
1756 23:09:25.717815
1757 23:09:25.717917 Set Vref, RX VrefLevel [Byte0]: 68
1758 23:09:25.721176 [Byte1]: 68
1759 23:09:25.725860
1760 23:09:25.725969 Set Vref, RX VrefLevel [Byte0]: 69
1761 23:09:25.728666 [Byte1]: 69
1762 23:09:25.732777
1763 23:09:25.732885 Set Vref, RX VrefLevel [Byte0]: 70
1764 23:09:25.736266 [Byte1]: 70
1765 23:09:25.740233
1766 23:09:25.740342 Set Vref, RX VrefLevel [Byte0]: 71
1767 23:09:25.743759 [Byte1]: 71
1768 23:09:25.748116
1769 23:09:25.748224 Set Vref, RX VrefLevel [Byte0]: 72
1770 23:09:25.751136 [Byte1]: 72
1771 23:09:25.755476
1772 23:09:25.755585 Set Vref, RX VrefLevel [Byte0]: 73
1773 23:09:25.758737 [Byte1]: 73
1774 23:09:25.763263
1775 23:09:25.763370 Set Vref, RX VrefLevel [Byte0]: 74
1776 23:09:25.766516 [Byte1]: 74
1777 23:09:25.770612
1778 23:09:25.770713 Final RX Vref Byte 0 = 56 to rank0
1779 23:09:25.773877 Final RX Vref Byte 1 = 53 to rank0
1780 23:09:25.777206 Final RX Vref Byte 0 = 56 to rank1
1781 23:09:25.780904 Final RX Vref Byte 1 = 53 to rank1==
1782 23:09:25.784277 Dram Type= 6, Freq= 0, CH_1, rank 0
1783 23:09:25.790736 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1784 23:09:25.790848 ==
1785 23:09:25.790942 DQS Delay:
1786 23:09:25.791031 DQS0 = 0, DQS1 = 0
1787 23:09:25.794037 DQM Delay:
1788 23:09:25.794144 DQM0 = 95, DQM1 = 90
1789 23:09:25.797421 DQ Delay:
1790 23:09:25.800975 DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =88
1791 23:09:25.803872 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =92
1792 23:09:25.807482 DQ8 =76, DQ9 =80, DQ10 =92, DQ11 =84
1793 23:09:25.810922 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =100
1794 23:09:25.811030
1795 23:09:25.811122
1796 23:09:25.817590 [DQSOSCAuto] RK0, (LSB)MR18= 0x2b47, (MSB)MR19= 0x606, tDQSOscB0 = 392 ps tDQSOscB1 = 398 ps
1797 23:09:25.821054 CH1 RK0: MR19=606, MR18=2B47
1798 23:09:25.827363 CH1_RK0: MR19=0x606, MR18=0x2B47, DQSOSC=392, MR23=63, INC=96, DEC=64
1799 23:09:25.827474
1800 23:09:25.830856 ----->DramcWriteLeveling(PI) begin...
1801 23:09:25.830966 ==
1802 23:09:25.834467 Dram Type= 6, Freq= 0, CH_1, rank 1
1803 23:09:25.837913 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1804 23:09:25.838022 ==
1805 23:09:25.840782 Write leveling (Byte 0): 27 => 27
1806 23:09:25.844408 Write leveling (Byte 1): 30 => 30
1807 23:09:25.847767 DramcWriteLeveling(PI) end<-----
1808 23:09:25.847873
1809 23:09:25.847965 ==
1810 23:09:25.850806 Dram Type= 6, Freq= 0, CH_1, rank 1
1811 23:09:25.853935 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1812 23:09:25.854040 ==
1813 23:09:25.857236 [Gating] SW mode calibration
1814 23:09:25.864167 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1815 23:09:25.870439 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1816 23:09:25.873835 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1817 23:09:25.877517 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1818 23:09:25.884212 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 23:09:25.886989 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 23:09:25.890724 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 23:09:25.897025 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 23:09:25.900896 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 23:09:25.903710 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 23:09:25.910422 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 23:09:25.913804 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 23:09:25.917527 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 23:09:25.923822 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 23:09:25.927174 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 23:09:25.930584 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 23:09:25.937401 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 23:09:25.941041 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 23:09:25.943886 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1833 23:09:25.947473 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 1)
1834 23:09:25.954431 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 23:09:25.957326 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 23:09:25.960832 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 23:09:25.967501 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 23:09:25.970720 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 23:09:25.974026 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 23:09:25.980574 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 23:09:25.984085 0 9 4 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
1842 23:09:25.987518 0 9 8 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 1)
1843 23:09:25.993899 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1844 23:09:25.997532 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1845 23:09:26.000692 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1846 23:09:26.007613 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1847 23:09:26.010695 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1848 23:09:26.013757 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1849 23:09:26.020501 0 10 4 | B1->B0 | 2929 3030 | 0 0 | (0 0) (0 0)
1850 23:09:26.024112 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1851 23:09:26.027283 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1852 23:09:26.034075 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1853 23:09:26.037418 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1854 23:09:26.040769 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1855 23:09:26.043781 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1856 23:09:26.050762 0 11 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1857 23:09:26.054323 0 11 4 | B1->B0 | 3838 2f2f | 0 0 | (0 0) (0 0)
1858 23:09:26.057213 0 11 8 | B1->B0 | 4646 4343 | 0 0 | (0 0) (0 0)
1859 23:09:26.064487 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1860 23:09:26.067056 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1861 23:09:26.070443 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1862 23:09:26.077020 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1863 23:09:26.080560 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1864 23:09:26.083912 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1865 23:09:26.090874 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1866 23:09:26.094306 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 23:09:26.097287 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 23:09:26.104081 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 23:09:26.107348 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 23:09:26.110999 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 23:09:26.117201 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 23:09:26.120675 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 23:09:26.123936 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 23:09:26.130634 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 23:09:26.134158 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 23:09:26.137273 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 23:09:26.143978 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1878 23:09:26.147125 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1879 23:09:26.150383 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1880 23:09:26.154052 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1881 23:09:26.161018 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1882 23:09:26.163779 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1883 23:09:26.167275 Total UI for P1: 0, mck2ui 16
1884 23:09:26.170424 best dqsien dly found for B0: ( 0, 14, 2)
1885 23:09:26.173707 Total UI for P1: 0, mck2ui 16
1886 23:09:26.177164 best dqsien dly found for B1: ( 0, 14, 2)
1887 23:09:26.180371 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1888 23:09:26.183768 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1889 23:09:26.183875
1890 23:09:26.187458 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1891 23:09:26.190648 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1892 23:09:26.193756 [Gating] SW calibration Done
1893 23:09:26.193863 ==
1894 23:09:26.197202 Dram Type= 6, Freq= 0, CH_1, rank 1
1895 23:09:26.200761 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1896 23:09:26.204353 ==
1897 23:09:26.204459 RX Vref Scan: 0
1898 23:09:26.204552
1899 23:09:26.207192 RX Vref 0 -> 0, step: 1
1900 23:09:26.207297
1901 23:09:26.210734 RX Delay -130 -> 252, step: 16
1902 23:09:26.213985 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1903 23:09:26.217199 iDelay=222, Bit 1, Center 93 (-2 ~ 189) 192
1904 23:09:26.220395 iDelay=222, Bit 2, Center 85 (-18 ~ 189) 208
1905 23:09:26.224024 iDelay=222, Bit 3, Center 93 (-2 ~ 189) 192
1906 23:09:26.227311 iDelay=222, Bit 4, Center 93 (-2 ~ 189) 192
1907 23:09:26.234366 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1908 23:09:26.237432 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1909 23:09:26.240480 iDelay=222, Bit 7, Center 101 (-2 ~ 205) 208
1910 23:09:26.244207 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1911 23:09:26.247134 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1912 23:09:26.254022 iDelay=222, Bit 10, Center 101 (-2 ~ 205) 208
1913 23:09:26.257539 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1914 23:09:26.260814 iDelay=222, Bit 12, Center 101 (-2 ~ 205) 208
1915 23:09:26.264201 iDelay=222, Bit 13, Center 101 (-2 ~ 205) 208
1916 23:09:26.267561 iDelay=222, Bit 14, Center 101 (-2 ~ 205) 208
1917 23:09:26.274077 iDelay=222, Bit 15, Center 101 (-2 ~ 205) 208
1918 23:09:26.274161 ==
1919 23:09:26.277191 Dram Type= 6, Freq= 0, CH_1, rank 1
1920 23:09:26.280690 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1921 23:09:26.280775 ==
1922 23:09:26.280838 DQS Delay:
1923 23:09:26.284121 DQS0 = 0, DQS1 = 0
1924 23:09:26.284227 DQM Delay:
1925 23:09:26.287629 DQM0 = 97, DQM1 = 93
1926 23:09:26.287735 DQ Delay:
1927 23:09:26.290824 DQ0 =101, DQ1 =93, DQ2 =85, DQ3 =93
1928 23:09:26.294032 DQ4 =93, DQ5 =109, DQ6 =101, DQ7 =101
1929 23:09:26.297663 DQ8 =77, DQ9 =77, DQ10 =101, DQ11 =85
1930 23:09:26.300571 DQ12 =101, DQ13 =101, DQ14 =101, DQ15 =101
1931 23:09:26.300649
1932 23:09:26.300711
1933 23:09:26.300769 ==
1934 23:09:26.304098 Dram Type= 6, Freq= 0, CH_1, rank 1
1935 23:09:26.310565 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1936 23:09:26.310645 ==
1937 23:09:26.310707
1938 23:09:26.310764
1939 23:09:26.310820 TX Vref Scan disable
1940 23:09:26.314100 == TX Byte 0 ==
1941 23:09:26.317567 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1942 23:09:26.320864 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1943 23:09:26.324549 == TX Byte 1 ==
1944 23:09:26.327827 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1945 23:09:26.331334 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1946 23:09:26.334350 ==
1947 23:09:26.337905 Dram Type= 6, Freq= 0, CH_1, rank 1
1948 23:09:26.340930 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1949 23:09:26.341010 ==
1950 23:09:26.353687 TX Vref=22, minBit 3, minWin=26, winSum=443
1951 23:09:26.356669 TX Vref=24, minBit 3, minWin=25, winSum=441
1952 23:09:26.360067 TX Vref=26, minBit 1, minWin=27, winSum=444
1953 23:09:26.363284 TX Vref=28, minBit 3, minWin=26, winSum=448
1954 23:09:26.366808 TX Vref=30, minBit 0, minWin=27, winSum=450
1955 23:09:26.370340 TX Vref=32, minBit 0, minWin=27, winSum=447
1956 23:09:26.377134 [TxChooseVref] Worse bit 0, Min win 27, Win sum 450, Final Vref 30
1957 23:09:26.377217
1958 23:09:26.380485 Final TX Range 1 Vref 30
1959 23:09:26.380568
1960 23:09:26.380652 ==
1961 23:09:26.383880 Dram Type= 6, Freq= 0, CH_1, rank 1
1962 23:09:26.386770 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1963 23:09:26.386852 ==
1964 23:09:26.386936
1965 23:09:26.387014
1966 23:09:26.390555 TX Vref Scan disable
1967 23:09:26.393617 == TX Byte 0 ==
1968 23:09:26.397470 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1969 23:09:26.400785 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1970 23:09:26.403769 == TX Byte 1 ==
1971 23:09:26.407117 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1972 23:09:26.410502 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1973 23:09:26.410585
1974 23:09:26.414077 [DATLAT]
1975 23:09:26.414159 Freq=800, CH1 RK1
1976 23:09:26.414243
1977 23:09:26.417038 DATLAT Default: 0xa
1978 23:09:26.417120 0, 0xFFFF, sum = 0
1979 23:09:26.420459 1, 0xFFFF, sum = 0
1980 23:09:26.420574 2, 0xFFFF, sum = 0
1981 23:09:26.424105 3, 0xFFFF, sum = 0
1982 23:09:26.424187 4, 0xFFFF, sum = 0
1983 23:09:26.427008 5, 0xFFFF, sum = 0
1984 23:09:26.427089 6, 0xFFFF, sum = 0
1985 23:09:26.430449 7, 0xFFFF, sum = 0
1986 23:09:26.430529 8, 0xFFFF, sum = 0
1987 23:09:26.434014 9, 0x0, sum = 1
1988 23:09:26.434095 10, 0x0, sum = 2
1989 23:09:26.437429 11, 0x0, sum = 3
1990 23:09:26.437536 12, 0x0, sum = 4
1991 23:09:26.440405 best_step = 10
1992 23:09:26.440484
1993 23:09:26.440547 ==
1994 23:09:26.443916 Dram Type= 6, Freq= 0, CH_1, rank 1
1995 23:09:26.447513 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1996 23:09:26.447594 ==
1997 23:09:26.447672 RX Vref Scan: 0
1998 23:09:26.450703
1999 23:09:26.450781 RX Vref 0 -> 0, step: 1
2000 23:09:26.450845
2001 23:09:26.453913 RX Delay -79 -> 252, step: 8
2002 23:09:26.457515 iDelay=209, Bit 0, Center 104 (9 ~ 200) 192
2003 23:09:26.463964 iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200
2004 23:09:26.467405 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
2005 23:09:26.470774 iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200
2006 23:09:26.474341 iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200
2007 23:09:26.477300 iDelay=209, Bit 5, Center 112 (17 ~ 208) 192
2008 23:09:26.480720 iDelay=209, Bit 6, Center 108 (9 ~ 208) 200
2009 23:09:26.487795 iDelay=209, Bit 7, Center 96 (-7 ~ 200) 208
2010 23:09:26.490668 iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208
2011 23:09:26.493961 iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208
2012 23:09:26.497471 iDelay=209, Bit 10, Center 92 (-7 ~ 192) 200
2013 23:09:26.500858 iDelay=209, Bit 11, Center 84 (-15 ~ 184) 200
2014 23:09:26.507388 iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216
2015 23:09:26.510919 iDelay=209, Bit 13, Center 100 (1 ~ 200) 200
2016 23:09:26.514268 iDelay=209, Bit 14, Center 100 (1 ~ 200) 200
2017 23:09:26.517461 iDelay=209, Bit 15, Center 96 (-7 ~ 200) 208
2018 23:09:26.517567 ==
2019 23:09:26.520475 Dram Type= 6, Freq= 0, CH_1, rank 1
2020 23:09:26.523970 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2021 23:09:26.527575 ==
2022 23:09:26.527657 DQS Delay:
2023 23:09:26.527741 DQS0 = 0, DQS1 = 0
2024 23:09:26.531172 DQM Delay:
2025 23:09:26.531254 DQM0 = 97, DQM1 = 91
2026 23:09:26.534389 DQ Delay:
2027 23:09:26.534471 DQ0 =104, DQ1 =92, DQ2 =84, DQ3 =92
2028 23:09:26.537554 DQ4 =92, DQ5 =112, DQ6 =108, DQ7 =96
2029 23:09:26.540851 DQ8 =80, DQ9 =80, DQ10 =92, DQ11 =84
2030 23:09:26.547484 DQ12 =100, DQ13 =100, DQ14 =100, DQ15 =96
2031 23:09:26.547567
2032 23:09:26.547650
2033 23:09:26.554096 [DQSOSCAuto] RK1, (LSB)MR18= 0x4913, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 391 ps
2034 23:09:26.557485 CH1 RK1: MR19=606, MR18=4913
2035 23:09:26.564278 CH1_RK1: MR19=0x606, MR18=0x4913, DQSOSC=391, MR23=63, INC=96, DEC=64
2036 23:09:26.567496 [RxdqsGatingPostProcess] freq 800
2037 23:09:26.570851 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2038 23:09:26.574240 Pre-setting of DQS Precalculation
2039 23:09:26.581180 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2040 23:09:26.587597 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2041 23:09:26.594435 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2042 23:09:26.594517
2043 23:09:26.594600
2044 23:09:26.597404 [Calibration Summary] 1600 Mbps
2045 23:09:26.597485 CH 0, Rank 0
2046 23:09:26.600858 SW Impedance : PASS
2047 23:09:26.604168 DUTY Scan : NO K
2048 23:09:26.604250 ZQ Calibration : PASS
2049 23:09:26.607425 Jitter Meter : NO K
2050 23:09:26.607506 CBT Training : PASS
2051 23:09:26.611164 Write leveling : PASS
2052 23:09:26.614071 RX DQS gating : PASS
2053 23:09:26.614153 RX DQ/DQS(RDDQC) : PASS
2054 23:09:26.617461 TX DQ/DQS : PASS
2055 23:09:26.620982 RX DATLAT : PASS
2056 23:09:26.621087 RX DQ/DQS(Engine): PASS
2057 23:09:26.624774 TX OE : NO K
2058 23:09:26.624856 All Pass.
2059 23:09:26.624939
2060 23:09:26.627962 CH 0, Rank 1
2061 23:09:26.628044 SW Impedance : PASS
2062 23:09:26.630600 DUTY Scan : NO K
2063 23:09:26.634328 ZQ Calibration : PASS
2064 23:09:26.634410 Jitter Meter : NO K
2065 23:09:26.637558 CBT Training : PASS
2066 23:09:26.640617 Write leveling : PASS
2067 23:09:26.640699 RX DQS gating : PASS
2068 23:09:26.644219 RX DQ/DQS(RDDQC) : PASS
2069 23:09:26.647936 TX DQ/DQS : PASS
2070 23:09:26.648018 RX DATLAT : PASS
2071 23:09:26.650973 RX DQ/DQS(Engine): PASS
2072 23:09:26.651054 TX OE : NO K
2073 23:09:26.654291 All Pass.
2074 23:09:26.654372
2075 23:09:26.654455 CH 1, Rank 0
2076 23:09:26.657849 SW Impedance : PASS
2077 23:09:26.657932 DUTY Scan : NO K
2078 23:09:26.661383 ZQ Calibration : PASS
2079 23:09:26.664597 Jitter Meter : NO K
2080 23:09:26.664678 CBT Training : PASS
2081 23:09:26.667625 Write leveling : PASS
2082 23:09:26.670888 RX DQS gating : PASS
2083 23:09:26.670970 RX DQ/DQS(RDDQC) : PASS
2084 23:09:26.674571 TX DQ/DQS : PASS
2085 23:09:26.677599 RX DATLAT : PASS
2086 23:09:26.677695 RX DQ/DQS(Engine): PASS
2087 23:09:26.680847 TX OE : NO K
2088 23:09:26.680928 All Pass.
2089 23:09:26.681011
2090 23:09:26.684269 CH 1, Rank 1
2091 23:09:26.684351 SW Impedance : PASS
2092 23:09:26.687669 DUTY Scan : NO K
2093 23:09:26.691249 ZQ Calibration : PASS
2094 23:09:26.691331 Jitter Meter : NO K
2095 23:09:26.694215 CBT Training : PASS
2096 23:09:26.694297 Write leveling : PASS
2097 23:09:26.697636 RX DQS gating : PASS
2098 23:09:26.701219 RX DQ/DQS(RDDQC) : PASS
2099 23:09:26.701301 TX DQ/DQS : PASS
2100 23:09:26.704759 RX DATLAT : PASS
2101 23:09:26.707701 RX DQ/DQS(Engine): PASS
2102 23:09:26.707783 TX OE : NO K
2103 23:09:26.710975 All Pass.
2104 23:09:26.711057
2105 23:09:26.711139 DramC Write-DBI off
2106 23:09:26.714388 PER_BANK_REFRESH: Hybrid Mode
2107 23:09:26.714469 TX_TRACKING: ON
2108 23:09:26.717976 [GetDramInforAfterCalByMRR] Vendor 6.
2109 23:09:26.724367 [GetDramInforAfterCalByMRR] Revision 606.
2110 23:09:26.727924 [GetDramInforAfterCalByMRR] Revision 2 0.
2111 23:09:26.728006 MR0 0x3b3b
2112 23:09:26.728089 MR8 0x5151
2113 23:09:26.731432 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2114 23:09:26.731514
2115 23:09:26.734274 MR0 0x3b3b
2116 23:09:26.734355 MR8 0x5151
2117 23:09:26.738127 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2118 23:09:26.738209
2119 23:09:26.747744 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2120 23:09:26.751231 [FAST_K] Save calibration result to emmc
2121 23:09:26.754315 [FAST_K] Save calibration result to emmc
2122 23:09:26.757849 dram_init: config_dvfs: 1
2123 23:09:26.761256 dramc_set_vcore_voltage set vcore to 662500
2124 23:09:26.764571 Read voltage for 1200, 2
2125 23:09:26.764652 Vio18 = 0
2126 23:09:26.764735 Vcore = 662500
2127 23:09:26.768202 Vdram = 0
2128 23:09:26.768284 Vddq = 0
2129 23:09:26.768367 Vmddr = 0
2130 23:09:26.774507 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2131 23:09:26.777964 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2132 23:09:26.781295 MEM_TYPE=3, freq_sel=15
2133 23:09:26.784426 sv_algorithm_assistance_LP4_1600
2134 23:09:26.788081 ============ PULL DRAM RESETB DOWN ============
2135 23:09:26.791170 ========== PULL DRAM RESETB DOWN end =========
2136 23:09:26.797746 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2137 23:09:26.801227 ===================================
2138 23:09:26.801309 LPDDR4 DRAM CONFIGURATION
2139 23:09:26.804732 ===================================
2140 23:09:26.807699 EX_ROW_EN[0] = 0x0
2141 23:09:26.811254 EX_ROW_EN[1] = 0x0
2142 23:09:26.811335 LP4Y_EN = 0x0
2143 23:09:26.814512 WORK_FSP = 0x0
2144 23:09:26.814593 WL = 0x4
2145 23:09:26.817952 RL = 0x4
2146 23:09:26.818033 BL = 0x2
2147 23:09:26.821172 RPST = 0x0
2148 23:09:26.821261 RD_PRE = 0x0
2149 23:09:26.824847 WR_PRE = 0x1
2150 23:09:26.824926 WR_PST = 0x0
2151 23:09:26.828248 DBI_WR = 0x0
2152 23:09:26.828337 DBI_RD = 0x0
2153 23:09:26.831606 OTF = 0x1
2154 23:09:26.834629 ===================================
2155 23:09:26.837965 ===================================
2156 23:09:26.838047 ANA top config
2157 23:09:26.841610 ===================================
2158 23:09:26.844595 DLL_ASYNC_EN = 0
2159 23:09:26.848209 ALL_SLAVE_EN = 0
2160 23:09:26.848306 NEW_RANK_MODE = 1
2161 23:09:26.851436 DLL_IDLE_MODE = 1
2162 23:09:26.855102 LP45_APHY_COMB_EN = 1
2163 23:09:26.858482 TX_ODT_DIS = 1
2164 23:09:26.858561 NEW_8X_MODE = 1
2165 23:09:26.861763 ===================================
2166 23:09:26.865246 ===================================
2167 23:09:26.867920 data_rate = 2400
2168 23:09:26.871754 CKR = 1
2169 23:09:26.874818 DQ_P2S_RATIO = 8
2170 23:09:26.878263 ===================================
2171 23:09:26.881744 CA_P2S_RATIO = 8
2172 23:09:26.884994 DQ_CA_OPEN = 0
2173 23:09:26.885073 DQ_SEMI_OPEN = 0
2174 23:09:26.888463 CA_SEMI_OPEN = 0
2175 23:09:26.891755 CA_FULL_RATE = 0
2176 23:09:26.894887 DQ_CKDIV4_EN = 0
2177 23:09:26.898569 CA_CKDIV4_EN = 0
2178 23:09:26.898649 CA_PREDIV_EN = 0
2179 23:09:26.901505 PH8_DLY = 17
2180 23:09:26.905177 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2181 23:09:26.908573 DQ_AAMCK_DIV = 4
2182 23:09:26.911407 CA_AAMCK_DIV = 4
2183 23:09:26.914906 CA_ADMCK_DIV = 4
2184 23:09:26.914995 DQ_TRACK_CA_EN = 0
2185 23:09:26.918578 CA_PICK = 1200
2186 23:09:26.921377 CA_MCKIO = 1200
2187 23:09:26.924871 MCKIO_SEMI = 0
2188 23:09:26.928447 PLL_FREQ = 2366
2189 23:09:26.931749 DQ_UI_PI_RATIO = 32
2190 23:09:26.935018 CA_UI_PI_RATIO = 0
2191 23:09:26.938565 ===================================
2192 23:09:26.941547 ===================================
2193 23:09:26.941647 memory_type:LPDDR4
2194 23:09:26.945205 GP_NUM : 10
2195 23:09:26.948035 SRAM_EN : 1
2196 23:09:26.948115 MD32_EN : 0
2197 23:09:26.951976 ===================================
2198 23:09:26.955364 [ANA_INIT] >>>>>>>>>>>>>>
2199 23:09:26.958260 <<<<<< [CONFIGURE PHASE]: ANA_TX
2200 23:09:26.962010 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2201 23:09:26.964812 ===================================
2202 23:09:26.968324 data_rate = 2400,PCW = 0X5b00
2203 23:09:26.971790 ===================================
2204 23:09:26.975490 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2205 23:09:26.978283 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2206 23:09:26.984831 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2207 23:09:26.988376 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2208 23:09:26.991820 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2209 23:09:26.995044 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2210 23:09:26.998700 [ANA_INIT] flow start
2211 23:09:27.001474 [ANA_INIT] PLL >>>>>>>>
2212 23:09:27.001555 [ANA_INIT] PLL <<<<<<<<
2213 23:09:27.004789 [ANA_INIT] MIDPI >>>>>>>>
2214 23:09:27.008542 [ANA_INIT] MIDPI <<<<<<<<
2215 23:09:27.008622 [ANA_INIT] DLL >>>>>>>>
2216 23:09:27.011718 [ANA_INIT] DLL <<<<<<<<
2217 23:09:27.015348 [ANA_INIT] flow end
2218 23:09:27.018578 ============ LP4 DIFF to SE enter ============
2219 23:09:27.021426 ============ LP4 DIFF to SE exit ============
2220 23:09:27.025042 [ANA_INIT] <<<<<<<<<<<<<
2221 23:09:27.028183 [Flow] Enable top DCM control >>>>>
2222 23:09:27.031551 [Flow] Enable top DCM control <<<<<
2223 23:09:27.035017 Enable DLL master slave shuffle
2224 23:09:27.038522 ==============================================================
2225 23:09:27.041740 Gating Mode config
2226 23:09:27.048616 ==============================================================
2227 23:09:27.048706 Config description:
2228 23:09:27.058662 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2229 23:09:27.064792 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2230 23:09:27.068591 SELPH_MODE 0: By rank 1: By Phase
2231 23:09:27.075030 ==============================================================
2232 23:09:27.078539 GAT_TRACK_EN = 1
2233 23:09:27.082002 RX_GATING_MODE = 2
2234 23:09:27.085349 RX_GATING_TRACK_MODE = 2
2235 23:09:27.088753 SELPH_MODE = 1
2236 23:09:27.092042 PICG_EARLY_EN = 1
2237 23:09:27.095249 VALID_LAT_VALUE = 1
2238 23:09:27.098803 ==============================================================
2239 23:09:27.101791 Enter into Gating configuration >>>>
2240 23:09:27.105041 Exit from Gating configuration <<<<
2241 23:09:27.108691 Enter into DVFS_PRE_config >>>>>
2242 23:09:27.118701 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2243 23:09:27.121904 Exit from DVFS_PRE_config <<<<<
2244 23:09:27.125540 Enter into PICG configuration >>>>
2245 23:09:27.129007 Exit from PICG configuration <<<<
2246 23:09:27.132423 [RX_INPUT] configuration >>>>>
2247 23:09:27.135262 [RX_INPUT] configuration <<<<<
2248 23:09:27.138822 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2249 23:09:27.145734 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2250 23:09:27.152076 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2251 23:09:27.158804 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2252 23:09:27.165333 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2253 23:09:27.168700 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2254 23:09:27.175652 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2255 23:09:27.178837 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2256 23:09:27.181938 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2257 23:09:27.185596 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2258 23:09:27.192441 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2259 23:09:27.195402 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2260 23:09:27.198854 ===================================
2261 23:09:27.202481 LPDDR4 DRAM CONFIGURATION
2262 23:09:27.205552 ===================================
2263 23:09:27.205678 EX_ROW_EN[0] = 0x0
2264 23:09:27.209186 EX_ROW_EN[1] = 0x0
2265 23:09:27.209268 LP4Y_EN = 0x0
2266 23:09:27.212476 WORK_FSP = 0x0
2267 23:09:27.212559 WL = 0x4
2268 23:09:27.215740 RL = 0x4
2269 23:09:27.215822 BL = 0x2
2270 23:09:27.219036 RPST = 0x0
2271 23:09:27.219119 RD_PRE = 0x0
2272 23:09:27.222316 WR_PRE = 0x1
2273 23:09:27.222398 WR_PST = 0x0
2274 23:09:27.225563 DBI_WR = 0x0
2275 23:09:27.225683 DBI_RD = 0x0
2276 23:09:27.228943 OTF = 0x1
2277 23:09:27.232503 ===================================
2278 23:09:27.236031 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2279 23:09:27.239003 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2280 23:09:27.245751 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2281 23:09:27.248686 ===================================
2282 23:09:27.248771 LPDDR4 DRAM CONFIGURATION
2283 23:09:27.252598 ===================================
2284 23:09:27.256022 EX_ROW_EN[0] = 0x10
2285 23:09:27.258978 EX_ROW_EN[1] = 0x0
2286 23:09:27.259061 LP4Y_EN = 0x0
2287 23:09:27.262495 WORK_FSP = 0x0
2288 23:09:27.262577 WL = 0x4
2289 23:09:27.265392 RL = 0x4
2290 23:09:27.265498 BL = 0x2
2291 23:09:27.268845 RPST = 0x0
2292 23:09:27.268927 RD_PRE = 0x0
2293 23:09:27.272474 WR_PRE = 0x1
2294 23:09:27.272556 WR_PST = 0x0
2295 23:09:27.275986 DBI_WR = 0x0
2296 23:09:27.276068 DBI_RD = 0x0
2297 23:09:27.278911 OTF = 0x1
2298 23:09:27.282402 ===================================
2299 23:09:27.288924 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2300 23:09:27.289011 ==
2301 23:09:27.292484 Dram Type= 6, Freq= 0, CH_0, rank 0
2302 23:09:27.295336 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2303 23:09:27.295419 ==
2304 23:09:27.299100 [Duty_Offset_Calibration]
2305 23:09:27.299179 B0:2 B1:1 CA:1
2306 23:09:27.299241
2307 23:09:27.302565 [DutyScan_Calibration_Flow] k_type=0
2308 23:09:27.312286
2309 23:09:27.312380 ==CLK 0==
2310 23:09:27.315964 Final CLK duty delay cell = 0
2311 23:09:27.318659 [0] MAX Duty = 5156%(X100), DQS PI = 22
2312 23:09:27.322336 [0] MIN Duty = 4844%(X100), DQS PI = 48
2313 23:09:27.322418 [0] AVG Duty = 5000%(X100)
2314 23:09:27.325418
2315 23:09:27.325497 CH0 CLK Duty spec in!! Max-Min= 312%
2316 23:09:27.332497 [DutyScan_Calibration_Flow] ====Done====
2317 23:09:27.332579
2318 23:09:27.335325 [DutyScan_Calibration_Flow] k_type=1
2319 23:09:27.350637
2320 23:09:27.350730 ==DQS 0 ==
2321 23:09:27.354059 Final DQS duty delay cell = -4
2322 23:09:27.357553 [-4] MAX Duty = 5124%(X100), DQS PI = 24
2323 23:09:27.360882 [-4] MIN Duty = 4782%(X100), DQS PI = 0
2324 23:09:27.364442 [-4] AVG Duty = 4953%(X100)
2325 23:09:27.364522
2326 23:09:27.364584 ==DQS 1 ==
2327 23:09:27.367425 Final DQS duty delay cell = 0
2328 23:09:27.370918 [0] MAX Duty = 5156%(X100), DQS PI = 62
2329 23:09:27.374354 [0] MIN Duty = 5000%(X100), DQS PI = 34
2330 23:09:27.377885 [0] AVG Duty = 5078%(X100)
2331 23:09:27.377964
2332 23:09:27.380812 CH0 DQS 0 Duty spec in!! Max-Min= 342%
2333 23:09:27.380890
2334 23:09:27.384374 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2335 23:09:27.387851 [DutyScan_Calibration_Flow] ====Done====
2336 23:09:27.387931
2337 23:09:27.391320 [DutyScan_Calibration_Flow] k_type=3
2338 23:09:27.407553
2339 23:09:27.407643 ==DQM 0 ==
2340 23:09:27.410898 Final DQM duty delay cell = 0
2341 23:09:27.414591 [0] MAX Duty = 5156%(X100), DQS PI = 30
2342 23:09:27.417811 [0] MIN Duty = 4906%(X100), DQS PI = 52
2343 23:09:27.417893 [0] AVG Duty = 5031%(X100)
2344 23:09:27.421186
2345 23:09:27.421265 ==DQM 1 ==
2346 23:09:27.424728 Final DQM duty delay cell = 0
2347 23:09:27.428017 [0] MAX Duty = 5093%(X100), DQS PI = 0
2348 23:09:27.431432 [0] MIN Duty = 5031%(X100), DQS PI = 14
2349 23:09:27.431512 [0] AVG Duty = 5062%(X100)
2350 23:09:27.431574
2351 23:09:27.437820 CH0 DQM 0 Duty spec in!! Max-Min= 250%
2352 23:09:27.437900
2353 23:09:27.441100 CH0 DQM 1 Duty spec in!! Max-Min= 62%
2354 23:09:27.444429 [DutyScan_Calibration_Flow] ====Done====
2355 23:09:27.444523
2356 23:09:27.447489 [DutyScan_Calibration_Flow] k_type=2
2357 23:09:27.464388
2358 23:09:27.464493 ==DQ 0 ==
2359 23:09:27.467275 Final DQ duty delay cell = 0
2360 23:09:27.470581 [0] MAX Duty = 5031%(X100), DQS PI = 26
2361 23:09:27.474139 [0] MIN Duty = 4844%(X100), DQS PI = 62
2362 23:09:27.474218 [0] AVG Duty = 4937%(X100)
2363 23:09:27.474281
2364 23:09:27.477534 ==DQ 1 ==
2365 23:09:27.481228 Final DQ duty delay cell = 0
2366 23:09:27.483996 [0] MAX Duty = 5093%(X100), DQS PI = 24
2367 23:09:27.487587 [0] MIN Duty = 4938%(X100), DQS PI = 36
2368 23:09:27.487665 [0] AVG Duty = 5015%(X100)
2369 23:09:27.487728
2370 23:09:27.490930 CH0 DQ 0 Duty spec in!! Max-Min= 187%
2371 23:09:27.491009
2372 23:09:27.497381 CH0 DQ 1 Duty spec in!! Max-Min= 155%
2373 23:09:27.500716 [DutyScan_Calibration_Flow] ====Done====
2374 23:09:27.500795 ==
2375 23:09:27.503982 Dram Type= 6, Freq= 0, CH_1, rank 0
2376 23:09:27.507685 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2377 23:09:27.507765 ==
2378 23:09:27.511078 [Duty_Offset_Calibration]
2379 23:09:27.511195 B0:1 B1:0 CA:0
2380 23:09:27.511298
2381 23:09:27.514478 [DutyScan_Calibration_Flow] k_type=0
2382 23:09:27.523373
2383 23:09:27.523459 ==CLK 0==
2384 23:09:27.526427 Final CLK duty delay cell = -4
2385 23:09:27.530201 [-4] MAX Duty = 5031%(X100), DQS PI = 24
2386 23:09:27.533150 [-4] MIN Duty = 4875%(X100), DQS PI = 50
2387 23:09:27.536593 [-4] AVG Duty = 4953%(X100)
2388 23:09:27.536675
2389 23:09:27.540025 CH1 CLK Duty spec in!! Max-Min= 156%
2390 23:09:27.543574 [DutyScan_Calibration_Flow] ====Done====
2391 23:09:27.543656
2392 23:09:27.546872 [DutyScan_Calibration_Flow] k_type=1
2393 23:09:27.563022
2394 23:09:27.563106 ==DQS 0 ==
2395 23:09:27.566581 Final DQS duty delay cell = 0
2396 23:09:27.570092 [0] MAX Duty = 5094%(X100), DQS PI = 26
2397 23:09:27.573371 [0] MIN Duty = 4875%(X100), DQS PI = 0
2398 23:09:27.573454 [0] AVG Duty = 4984%(X100)
2399 23:09:27.576333
2400 23:09:27.576415 ==DQS 1 ==
2401 23:09:27.579881 Final DQS duty delay cell = 0
2402 23:09:27.583424 [0] MAX Duty = 5156%(X100), DQS PI = 18
2403 23:09:27.586375 [0] MIN Duty = 4969%(X100), DQS PI = 8
2404 23:09:27.586457 [0] AVG Duty = 5062%(X100)
2405 23:09:27.589730
2406 23:09:27.593284 CH1 DQS 0 Duty spec in!! Max-Min= 219%
2407 23:09:27.593369
2408 23:09:27.596625 CH1 DQS 1 Duty spec in!! Max-Min= 187%
2409 23:09:27.600079 [DutyScan_Calibration_Flow] ====Done====
2410 23:09:27.600161
2411 23:09:27.602819 [DutyScan_Calibration_Flow] k_type=3
2412 23:09:27.619733
2413 23:09:27.619822 ==DQM 0 ==
2414 23:09:27.623205 Final DQM duty delay cell = 0
2415 23:09:27.626466 [0] MAX Duty = 5156%(X100), DQS PI = 6
2416 23:09:27.629739 [0] MIN Duty = 5031%(X100), DQS PI = 0
2417 23:09:27.629823 [0] AVG Duty = 5093%(X100)
2418 23:09:27.632884
2419 23:09:27.632966 ==DQM 1 ==
2420 23:09:27.636161 Final DQM duty delay cell = 0
2421 23:09:27.639485 [0] MAX Duty = 5031%(X100), DQS PI = 16
2422 23:09:27.642832 [0] MIN Duty = 4907%(X100), DQS PI = 36
2423 23:09:27.642944 [0] AVG Duty = 4969%(X100)
2424 23:09:27.646797
2425 23:09:27.649744 CH1 DQM 0 Duty spec in!! Max-Min= 125%
2426 23:09:27.649831
2427 23:09:27.653022 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2428 23:09:27.656311 [DutyScan_Calibration_Flow] ====Done====
2429 23:09:27.656394
2430 23:09:27.659816 [DutyScan_Calibration_Flow] k_type=2
2431 23:09:27.675544
2432 23:09:27.675630 ==DQ 0 ==
2433 23:09:27.678875 Final DQ duty delay cell = -4
2434 23:09:27.681921 [-4] MAX Duty = 5062%(X100), DQS PI = 8
2435 23:09:27.685431 [-4] MIN Duty = 4938%(X100), DQS PI = 0
2436 23:09:27.685514 [-4] AVG Duty = 5000%(X100)
2437 23:09:27.689012
2438 23:09:27.689092 ==DQ 1 ==
2439 23:09:27.692530 Final DQ duty delay cell = 0
2440 23:09:27.695538 [0] MAX Duty = 5125%(X100), DQS PI = 20
2441 23:09:27.698799 [0] MIN Duty = 4969%(X100), DQS PI = 10
2442 23:09:27.698881 [0] AVG Duty = 5047%(X100)
2443 23:09:27.698965
2444 23:09:27.702230 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2445 23:09:27.705744
2446 23:09:27.708992 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2447 23:09:27.712591 [DutyScan_Calibration_Flow] ====Done====
2448 23:09:27.715309 nWR fixed to 30
2449 23:09:27.715392 [ModeRegInit_LP4] CH0 RK0
2450 23:09:27.718684 [ModeRegInit_LP4] CH0 RK1
2451 23:09:27.722630 [ModeRegInit_LP4] CH1 RK0
2452 23:09:27.722712 [ModeRegInit_LP4] CH1 RK1
2453 23:09:27.725519 match AC timing 7
2454 23:09:27.729098 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2455 23:09:27.732606 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2456 23:09:27.739164 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2457 23:09:27.742233 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2458 23:09:27.748821 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2459 23:09:27.748908 ==
2460 23:09:27.752480 Dram Type= 6, Freq= 0, CH_0, rank 0
2461 23:09:27.755583 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2462 23:09:27.755666 ==
2463 23:09:27.762526 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2464 23:09:27.765456 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2465 23:09:27.775665 [CA 0] Center 39 (8~70) winsize 63
2466 23:09:27.778975 [CA 1] Center 39 (8~70) winsize 63
2467 23:09:27.782323 [CA 2] Center 35 (5~66) winsize 62
2468 23:09:27.785735 [CA 3] Center 34 (4~65) winsize 62
2469 23:09:27.789095 [CA 4] Center 33 (3~64) winsize 62
2470 23:09:27.792731 [CA 5] Center 32 (3~62) winsize 60
2471 23:09:27.792812
2472 23:09:27.795569 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2473 23:09:27.795651
2474 23:09:27.799114 [CATrainingPosCal] consider 1 rank data
2475 23:09:27.802095 u2DelayCellTimex100 = 270/100 ps
2476 23:09:27.806099 CA0 delay=39 (8~70),Diff = 7 PI (33 cell)
2477 23:09:27.808833 CA1 delay=39 (8~70),Diff = 7 PI (33 cell)
2478 23:09:27.815449 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2479 23:09:27.818858 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2480 23:09:27.822604 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2481 23:09:27.825773 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2482 23:09:27.825862
2483 23:09:27.829190 CA PerBit enable=1, Macro0, CA PI delay=32
2484 23:09:27.829273
2485 23:09:27.832193 [CBTSetCACLKResult] CA Dly = 32
2486 23:09:27.832275 CS Dly: 6 (0~37)
2487 23:09:27.835493 ==
2488 23:09:27.835575 Dram Type= 6, Freq= 0, CH_0, rank 1
2489 23:09:27.842602 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2490 23:09:27.842689 ==
2491 23:09:27.846149 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2492 23:09:27.852662 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2493 23:09:27.861491 [CA 0] Center 38 (8~69) winsize 62
2494 23:09:27.864593 [CA 1] Center 38 (8~69) winsize 62
2495 23:09:27.867938 [CA 2] Center 35 (4~66) winsize 63
2496 23:09:27.871539 [CA 3] Center 34 (4~65) winsize 62
2497 23:09:27.874884 [CA 4] Center 33 (3~64) winsize 62
2498 23:09:27.878164 [CA 5] Center 32 (3~62) winsize 60
2499 23:09:27.878246
2500 23:09:27.881909 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2501 23:09:27.881991
2502 23:09:27.884782 [CATrainingPosCal] consider 2 rank data
2503 23:09:27.888376 u2DelayCellTimex100 = 270/100 ps
2504 23:09:27.891566 CA0 delay=38 (8~69),Diff = 6 PI (28 cell)
2505 23:09:27.894970 CA1 delay=38 (8~69),Diff = 6 PI (28 cell)
2506 23:09:27.898306 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2507 23:09:27.904822 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2508 23:09:27.908211 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2509 23:09:27.911700 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2510 23:09:27.911781
2511 23:09:27.915181 CA PerBit enable=1, Macro0, CA PI delay=32
2512 23:09:27.915261
2513 23:09:27.918828 [CBTSetCACLKResult] CA Dly = 32
2514 23:09:27.918909 CS Dly: 6 (0~38)
2515 23:09:27.918973
2516 23:09:27.921889 ----->DramcWriteLeveling(PI) begin...
2517 23:09:27.921970 ==
2518 23:09:27.925281 Dram Type= 6, Freq= 0, CH_0, rank 0
2519 23:09:27.931991 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2520 23:09:27.932072 ==
2521 23:09:27.934930 Write leveling (Byte 0): 33 => 33
2522 23:09:27.938512 Write leveling (Byte 1): 29 => 29
2523 23:09:27.938593 DramcWriteLeveling(PI) end<-----
2524 23:09:27.942001
2525 23:09:27.942086 ==
2526 23:09:27.944901 Dram Type= 6, Freq= 0, CH_0, rank 0
2527 23:09:27.948854 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2528 23:09:27.948935 ==
2529 23:09:27.951731 [Gating] SW mode calibration
2530 23:09:27.958076 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2531 23:09:27.962073 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2532 23:09:27.968229 0 15 0 | B1->B0 | 2322 3434 | 1 0 | (0 0) (0 0)
2533 23:09:27.971755 0 15 4 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
2534 23:09:27.974848 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2535 23:09:27.981889 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2536 23:09:27.985171 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2537 23:09:27.988374 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2538 23:09:27.994828 0 15 24 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
2539 23:09:27.998299 0 15 28 | B1->B0 | 3434 2525 | 1 0 | (1 1) (0 0)
2540 23:09:28.001665 1 0 0 | B1->B0 | 2a2a 2323 | 0 0 | (0 1) (0 0)
2541 23:09:28.008570 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2542 23:09:28.011994 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2543 23:09:28.015414 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2544 23:09:28.018346 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2545 23:09:28.025406 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2546 23:09:28.028501 1 0 24 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
2547 23:09:28.031903 1 0 28 | B1->B0 | 2727 4444 | 0 0 | (0 0) (0 0)
2548 23:09:28.038518 1 1 0 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
2549 23:09:28.041994 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2550 23:09:28.044983 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2551 23:09:28.051663 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2552 23:09:28.055157 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2553 23:09:28.058741 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2554 23:09:28.065431 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2555 23:09:28.068778 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2556 23:09:28.072092 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2557 23:09:28.078659 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2558 23:09:28.081700 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2559 23:09:28.085456 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 23:09:28.091776 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 23:09:28.095154 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2562 23:09:28.098914 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 23:09:28.102273 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 23:09:28.108572 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 23:09:28.112401 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 23:09:28.115702 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 23:09:28.122000 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2568 23:09:28.125445 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2569 23:09:28.128848 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2570 23:09:28.135190 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2571 23:09:28.138787 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2572 23:09:28.142220 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2573 23:09:28.145445 Total UI for P1: 0, mck2ui 16
2574 23:09:28.148307 best dqsien dly found for B0: ( 1, 3, 26)
2575 23:09:28.155334 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2576 23:09:28.155424 Total UI for P1: 0, mck2ui 16
2577 23:09:28.161854 best dqsien dly found for B1: ( 1, 4, 0)
2578 23:09:28.165298 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2579 23:09:28.168791 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2580 23:09:28.168932
2581 23:09:28.172251 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2582 23:09:28.175648 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2583 23:09:28.178467 [Gating] SW calibration Done
2584 23:09:28.178587 ==
2585 23:09:28.181960 Dram Type= 6, Freq= 0, CH_0, rank 0
2586 23:09:28.185502 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2587 23:09:28.185646 ==
2588 23:09:28.189038 RX Vref Scan: 0
2589 23:09:28.189117
2590 23:09:28.189180 RX Vref 0 -> 0, step: 1
2591 23:09:28.189239
2592 23:09:28.191747 RX Delay -40 -> 252, step: 8
2593 23:09:28.195707 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2594 23:09:28.201885 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2595 23:09:28.205573 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2596 23:09:28.208791 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2597 23:09:28.212199 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2598 23:09:28.215186 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2599 23:09:28.218459 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2600 23:09:28.225309 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2601 23:09:28.228682 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2602 23:09:28.231658 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
2603 23:09:28.235101 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2604 23:09:28.238588 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2605 23:09:28.245129 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2606 23:09:28.248616 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2607 23:09:28.252040 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2608 23:09:28.255590 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2609 23:09:28.255670 ==
2610 23:09:28.258406 Dram Type= 6, Freq= 0, CH_0, rank 0
2611 23:09:28.265818 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2612 23:09:28.265898 ==
2613 23:09:28.265961 DQS Delay:
2614 23:09:28.268528 DQS0 = 0, DQS1 = 0
2615 23:09:28.268607 DQM Delay:
2616 23:09:28.268669 DQM0 = 121, DQM1 = 113
2617 23:09:28.272251 DQ Delay:
2618 23:09:28.275170 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2619 23:09:28.278363 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2620 23:09:28.281937 DQ8 =99, DQ9 =107, DQ10 =111, DQ11 =107
2621 23:09:28.285205 DQ12 =115, DQ13 =123, DQ14 =123, DQ15 =119
2622 23:09:28.285285
2623 23:09:28.285347
2624 23:09:28.285404 ==
2625 23:09:28.288510 Dram Type= 6, Freq= 0, CH_0, rank 0
2626 23:09:28.292175 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2627 23:09:28.295562 ==
2628 23:09:28.295642
2629 23:09:28.295705
2630 23:09:28.295763 TX Vref Scan disable
2631 23:09:28.298353 == TX Byte 0 ==
2632 23:09:28.301734 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2633 23:09:28.305363 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2634 23:09:28.308942 == TX Byte 1 ==
2635 23:09:28.312385 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2636 23:09:28.315490 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2637 23:09:28.315572 ==
2638 23:09:28.318557 Dram Type= 6, Freq= 0, CH_0, rank 0
2639 23:09:28.325474 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2640 23:09:28.325618 ==
2641 23:09:28.336195 TX Vref=22, minBit 15, minWin=24, winSum=405
2642 23:09:28.339391 TX Vref=24, minBit 0, minWin=25, winSum=410
2643 23:09:28.343395 TX Vref=26, minBit 3, minWin=25, winSum=415
2644 23:09:28.346001 TX Vref=28, minBit 1, minWin=26, winSum=426
2645 23:09:28.349430 TX Vref=30, minBit 0, minWin=26, winSum=421
2646 23:09:28.353128 TX Vref=32, minBit 4, minWin=25, winSum=420
2647 23:09:28.359355 [TxChooseVref] Worse bit 1, Min win 26, Win sum 426, Final Vref 28
2648 23:09:28.359440
2649 23:09:28.362984 Final TX Range 1 Vref 28
2650 23:09:28.363066
2651 23:09:28.363129 ==
2652 23:09:28.366369 Dram Type= 6, Freq= 0, CH_0, rank 0
2653 23:09:28.369281 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2654 23:09:28.369388 ==
2655 23:09:28.369478
2656 23:09:28.373116
2657 23:09:28.373196 TX Vref Scan disable
2658 23:09:28.376123 == TX Byte 0 ==
2659 23:09:28.379467 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2660 23:09:28.383027 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2661 23:09:28.386010 == TX Byte 1 ==
2662 23:09:28.389480 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2663 23:09:28.392749 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2664 23:09:28.392830
2665 23:09:28.396298 [DATLAT]
2666 23:09:28.396378 Freq=1200, CH0 RK0
2667 23:09:28.396441
2668 23:09:28.399653 DATLAT Default: 0xd
2669 23:09:28.399734 0, 0xFFFF, sum = 0
2670 23:09:28.402604 1, 0xFFFF, sum = 0
2671 23:09:28.402687 2, 0xFFFF, sum = 0
2672 23:09:28.406491 3, 0xFFFF, sum = 0
2673 23:09:28.406573 4, 0xFFFF, sum = 0
2674 23:09:28.409385 5, 0xFFFF, sum = 0
2675 23:09:28.409468 6, 0xFFFF, sum = 0
2676 23:09:28.412788 7, 0xFFFF, sum = 0
2677 23:09:28.416491 8, 0xFFFF, sum = 0
2678 23:09:28.416573 9, 0xFFFF, sum = 0
2679 23:09:28.419360 10, 0xFFFF, sum = 0
2680 23:09:28.419442 11, 0xFFFF, sum = 0
2681 23:09:28.423011 12, 0x0, sum = 1
2682 23:09:28.423093 13, 0x0, sum = 2
2683 23:09:28.423158 14, 0x0, sum = 3
2684 23:09:28.426230 15, 0x0, sum = 4
2685 23:09:28.426312 best_step = 13
2686 23:09:28.426376
2687 23:09:28.429855 ==
2688 23:09:28.429935 Dram Type= 6, Freq= 0, CH_0, rank 0
2689 23:09:28.436302 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2690 23:09:28.436384 ==
2691 23:09:28.436449 RX Vref Scan: 1
2692 23:09:28.436512
2693 23:09:28.439836 Set Vref Range= 32 -> 127
2694 23:09:28.439917
2695 23:09:28.443088 RX Vref 32 -> 127, step: 1
2696 23:09:28.443170
2697 23:09:28.446231 RX Delay -13 -> 252, step: 4
2698 23:09:28.446312
2699 23:09:28.449421 Set Vref, RX VrefLevel [Byte0]: 32
2700 23:09:28.452778 [Byte1]: 32
2701 23:09:28.452858
2702 23:09:28.456297 Set Vref, RX VrefLevel [Byte0]: 33
2703 23:09:28.459895 [Byte1]: 33
2704 23:09:28.459976
2705 23:09:28.462696 Set Vref, RX VrefLevel [Byte0]: 34
2706 23:09:28.466147 [Byte1]: 34
2707 23:09:28.470160
2708 23:09:28.470239 Set Vref, RX VrefLevel [Byte0]: 35
2709 23:09:28.473799 [Byte1]: 35
2710 23:09:28.477991
2711 23:09:28.478071 Set Vref, RX VrefLevel [Byte0]: 36
2712 23:09:28.481563 [Byte1]: 36
2713 23:09:28.486520
2714 23:09:28.486600 Set Vref, RX VrefLevel [Byte0]: 37
2715 23:09:28.489451 [Byte1]: 37
2716 23:09:28.494045
2717 23:09:28.494124 Set Vref, RX VrefLevel [Byte0]: 38
2718 23:09:28.497556 [Byte1]: 38
2719 23:09:28.501565
2720 23:09:28.501655 Set Vref, RX VrefLevel [Byte0]: 39
2721 23:09:28.505113 [Byte1]: 39
2722 23:09:28.509516
2723 23:09:28.509653 Set Vref, RX VrefLevel [Byte0]: 40
2724 23:09:28.513159 [Byte1]: 40
2725 23:09:28.517729
2726 23:09:28.517834 Set Vref, RX VrefLevel [Byte0]: 41
2727 23:09:28.520753 [Byte1]: 41
2728 23:09:28.525470
2729 23:09:28.525583 Set Vref, RX VrefLevel [Byte0]: 42
2730 23:09:28.528493 [Byte1]: 42
2731 23:09:28.533091
2732 23:09:28.536578 Set Vref, RX VrefLevel [Byte0]: 43
2733 23:09:28.536659 [Byte1]: 43
2734 23:09:28.541257
2735 23:09:28.541336 Set Vref, RX VrefLevel [Byte0]: 44
2736 23:09:28.544476 [Byte1]: 44
2737 23:09:28.549246
2738 23:09:28.549354 Set Vref, RX VrefLevel [Byte0]: 45
2739 23:09:28.552353 [Byte1]: 45
2740 23:09:28.557283
2741 23:09:28.557392 Set Vref, RX VrefLevel [Byte0]: 46
2742 23:09:28.560156 [Byte1]: 46
2743 23:09:28.564650
2744 23:09:28.564779 Set Vref, RX VrefLevel [Byte0]: 47
2745 23:09:28.568206 [Byte1]: 47
2746 23:09:28.572786
2747 23:09:28.572867 Set Vref, RX VrefLevel [Byte0]: 48
2748 23:09:28.575995 [Byte1]: 48
2749 23:09:28.580725
2750 23:09:28.580807 Set Vref, RX VrefLevel [Byte0]: 49
2751 23:09:28.583906 [Byte1]: 49
2752 23:09:28.588758
2753 23:09:28.588838 Set Vref, RX VrefLevel [Byte0]: 50
2754 23:09:28.591781 [Byte1]: 50
2755 23:09:28.596263
2756 23:09:28.596345 Set Vref, RX VrefLevel [Byte0]: 51
2757 23:09:28.599929 [Byte1]: 51
2758 23:09:28.604501
2759 23:09:28.604584 Set Vref, RX VrefLevel [Byte0]: 52
2760 23:09:28.607829 [Byte1]: 52
2761 23:09:28.612111
2762 23:09:28.612192 Set Vref, RX VrefLevel [Byte0]: 53
2763 23:09:28.615260 [Byte1]: 53
2764 23:09:28.619863
2765 23:09:28.619945 Set Vref, RX VrefLevel [Byte0]: 54
2766 23:09:28.623718 [Byte1]: 54
2767 23:09:28.628229
2768 23:09:28.628335 Set Vref, RX VrefLevel [Byte0]: 55
2769 23:09:28.631257 [Byte1]: 55
2770 23:09:28.635835
2771 23:09:28.635916 Set Vref, RX VrefLevel [Byte0]: 56
2772 23:09:28.639466 [Byte1]: 56
2773 23:09:28.644073
2774 23:09:28.644153 Set Vref, RX VrefLevel [Byte0]: 57
2775 23:09:28.646880 [Byte1]: 57
2776 23:09:28.651942
2777 23:09:28.652022 Set Vref, RX VrefLevel [Byte0]: 58
2778 23:09:28.654990 [Byte1]: 58
2779 23:09:28.659909
2780 23:09:28.659989 Set Vref, RX VrefLevel [Byte0]: 59
2781 23:09:28.662738 [Byte1]: 59
2782 23:09:28.667371
2783 23:09:28.667453 Set Vref, RX VrefLevel [Byte0]: 60
2784 23:09:28.670745 [Byte1]: 60
2785 23:09:28.675306
2786 23:09:28.675386 Set Vref, RX VrefLevel [Byte0]: 61
2787 23:09:28.678926 [Byte1]: 61
2788 23:09:28.683460
2789 23:09:28.683542 Set Vref, RX VrefLevel [Byte0]: 62
2790 23:09:28.686652 [Byte1]: 62
2791 23:09:28.691149
2792 23:09:28.691229 Set Vref, RX VrefLevel [Byte0]: 63
2793 23:09:28.694739 [Byte1]: 63
2794 23:09:28.698823
2795 23:09:28.698903 Set Vref, RX VrefLevel [Byte0]: 64
2796 23:09:28.702100 [Byte1]: 64
2797 23:09:28.706856
2798 23:09:28.706936 Set Vref, RX VrefLevel [Byte0]: 65
2799 23:09:28.710439 [Byte1]: 65
2800 23:09:28.714830
2801 23:09:28.714943 Set Vref, RX VrefLevel [Byte0]: 66
2802 23:09:28.718192 [Byte1]: 66
2803 23:09:28.722439
2804 23:09:28.722523 Set Vref, RX VrefLevel [Byte0]: 67
2805 23:09:28.725855 [Byte1]: 67
2806 23:09:28.730405
2807 23:09:28.730485 Set Vref, RX VrefLevel [Byte0]: 68
2808 23:09:28.733982 [Byte1]: 68
2809 23:09:28.738589
2810 23:09:28.738669 Final RX Vref Byte 0 = 53 to rank0
2811 23:09:28.742197 Final RX Vref Byte 1 = 46 to rank0
2812 23:09:28.745038 Final RX Vref Byte 0 = 53 to rank1
2813 23:09:28.748418 Final RX Vref Byte 1 = 46 to rank1==
2814 23:09:28.751779 Dram Type= 6, Freq= 0, CH_0, rank 0
2815 23:09:28.758666 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2816 23:09:28.758749 ==
2817 23:09:28.758812 DQS Delay:
2818 23:09:28.758870 DQS0 = 0, DQS1 = 0
2819 23:09:28.761498 DQM Delay:
2820 23:09:28.761642 DQM0 = 120, DQM1 = 110
2821 23:09:28.764885 DQ Delay:
2822 23:09:28.768757 DQ0 =120, DQ1 =122, DQ2 =118, DQ3 =118
2823 23:09:28.771735 DQ4 =122, DQ5 =112, DQ6 =126, DQ7 =128
2824 23:09:28.775256 DQ8 =96, DQ9 =100, DQ10 =112, DQ11 =104
2825 23:09:28.778676 DQ12 =116, DQ13 =116, DQ14 =124, DQ15 =118
2826 23:09:28.778762
2827 23:09:28.778826
2828 23:09:28.785183 [DQSOSCAuto] RK0, (LSB)MR18= 0x160f, (MSB)MR19= 0x404, tDQSOscB0 = 404 ps tDQSOscB1 = 401 ps
2829 23:09:28.788342 CH0 RK0: MR19=404, MR18=160F
2830 23:09:28.795500 CH0_RK0: MR19=0x404, MR18=0x160F, DQSOSC=401, MR23=63, INC=40, DEC=27
2831 23:09:28.795583
2832 23:09:28.798389 ----->DramcWriteLeveling(PI) begin...
2833 23:09:28.798471 ==
2834 23:09:28.802096 Dram Type= 6, Freq= 0, CH_0, rank 1
2835 23:09:28.805175 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2836 23:09:28.805296 ==
2837 23:09:28.808739 Write leveling (Byte 0): 34 => 34
2838 23:09:28.811813 Write leveling (Byte 1): 26 => 26
2839 23:09:28.815133 DramcWriteLeveling(PI) end<-----
2840 23:09:28.815242
2841 23:09:28.815303 ==
2842 23:09:28.818661 Dram Type= 6, Freq= 0, CH_0, rank 1
2843 23:09:28.825026 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2844 23:09:28.825116 ==
2845 23:09:28.825181 [Gating] SW mode calibration
2846 23:09:28.835460 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2847 23:09:28.838699 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2848 23:09:28.842124 0 15 0 | B1->B0 | 3333 3030 | 0 0 | (0 0) (1 1)
2849 23:09:28.848515 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2850 23:09:28.851881 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2851 23:09:28.855225 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2852 23:09:28.862291 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2853 23:09:28.865054 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2854 23:09:28.868704 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2855 23:09:28.875358 0 15 28 | B1->B0 | 3232 3030 | 0 0 | (0 1) (0 1)
2856 23:09:28.878491 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
2857 23:09:28.882026 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2858 23:09:28.888430 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2859 23:09:28.892052 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2860 23:09:28.895286 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2861 23:09:28.902140 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2862 23:09:28.905516 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2863 23:09:28.909119 1 0 28 | B1->B0 | 3a3a 3939 | 1 0 | (0 0) (0 0)
2864 23:09:28.911978 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2865 23:09:28.918969 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2866 23:09:28.922583 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2867 23:09:28.925493 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2868 23:09:28.931894 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2869 23:09:28.935586 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2870 23:09:28.938510 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2871 23:09:28.945401 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2872 23:09:28.948636 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
2873 23:09:28.951862 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2874 23:09:28.958939 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2875 23:09:28.961660 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2876 23:09:28.965149 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2877 23:09:28.972253 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2878 23:09:28.975271 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2879 23:09:28.978871 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2880 23:09:28.985479 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2881 23:09:28.988466 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2882 23:09:28.991942 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2883 23:09:28.998414 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2884 23:09:29.002110 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2885 23:09:29.005543 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2886 23:09:29.008765 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2887 23:09:29.015421 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2888 23:09:29.018903 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2889 23:09:29.021842 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2890 23:09:29.025464 Total UI for P1: 0, mck2ui 16
2891 23:09:29.028421 best dqsien dly found for B0: ( 1, 3, 30)
2892 23:09:29.032050 Total UI for P1: 0, mck2ui 16
2893 23:09:29.035546 best dqsien dly found for B1: ( 1, 3, 30)
2894 23:09:29.038892 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2895 23:09:29.041996 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2896 23:09:29.042076
2897 23:09:29.048903 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2898 23:09:29.052171 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2899 23:09:29.055715 [Gating] SW calibration Done
2900 23:09:29.055794 ==
2901 23:09:29.058606 Dram Type= 6, Freq= 0, CH_0, rank 1
2902 23:09:29.062302 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2903 23:09:29.062381 ==
2904 23:09:29.062445 RX Vref Scan: 0
2905 23:09:29.062503
2906 23:09:29.065562 RX Vref 0 -> 0, step: 1
2907 23:09:29.065651
2908 23:09:29.069118 RX Delay -40 -> 252, step: 8
2909 23:09:29.072225 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2910 23:09:29.075526 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2911 23:09:29.079254 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2912 23:09:29.085675 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2913 23:09:29.088975 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2914 23:09:29.092391 iDelay=200, Bit 5, Center 119 (48 ~ 191) 144
2915 23:09:29.095588 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2916 23:09:29.099011 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2917 23:09:29.105506 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2918 23:09:29.109137 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
2919 23:09:29.112552 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2920 23:09:29.115734 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2921 23:09:29.119433 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2922 23:09:29.125846 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2923 23:09:29.129398 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2924 23:09:29.132943 iDelay=200, Bit 15, Center 119 (56 ~ 183) 128
2925 23:09:29.133022 ==
2926 23:09:29.135909 Dram Type= 6, Freq= 0, CH_0, rank 1
2927 23:09:29.139397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2928 23:09:29.139477 ==
2929 23:09:29.142748 DQS Delay:
2930 23:09:29.142827 DQS0 = 0, DQS1 = 0
2931 23:09:29.142890 DQM Delay:
2932 23:09:29.146462 DQM0 = 122, DQM1 = 112
2933 23:09:29.146541 DQ Delay:
2934 23:09:29.149272 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =119
2935 23:09:29.152746 DQ4 =127, DQ5 =119, DQ6 =127, DQ7 =127
2936 23:09:29.156073 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
2937 23:09:29.163180 DQ12 =115, DQ13 =119, DQ14 =123, DQ15 =119
2938 23:09:29.163258
2939 23:09:29.163321
2940 23:09:29.163379 ==
2941 23:09:29.166226 Dram Type= 6, Freq= 0, CH_0, rank 1
2942 23:09:29.169909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2943 23:09:29.169989 ==
2944 23:09:29.170051
2945 23:09:29.170109
2946 23:09:29.172751 TX Vref Scan disable
2947 23:09:29.172830 == TX Byte 0 ==
2948 23:09:29.179634 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
2949 23:09:29.183297 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
2950 23:09:29.183376 == TX Byte 1 ==
2951 23:09:29.189616 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
2952 23:09:29.192967 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
2953 23:09:29.193072 ==
2954 23:09:29.196260 Dram Type= 6, Freq= 0, CH_0, rank 1
2955 23:09:29.199422 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2956 23:09:29.199501 ==
2957 23:09:29.212865 TX Vref=22, minBit 3, minWin=25, winSum=416
2958 23:09:29.216568 TX Vref=24, minBit 13, minWin=25, winSum=420
2959 23:09:29.219970 TX Vref=26, minBit 13, minWin=25, winSum=422
2960 23:09:29.223282 TX Vref=28, minBit 5, minWin=25, winSum=422
2961 23:09:29.226250 TX Vref=30, minBit 1, minWin=26, winSum=428
2962 23:09:29.229954 TX Vref=32, minBit 0, minWin=26, winSum=424
2963 23:09:29.236439 [TxChooseVref] Worse bit 1, Min win 26, Win sum 428, Final Vref 30
2964 23:09:29.236519
2965 23:09:29.239819 Final TX Range 1 Vref 30
2966 23:09:29.239899
2967 23:09:29.239961 ==
2968 23:09:29.242877 Dram Type= 6, Freq= 0, CH_0, rank 1
2969 23:09:29.246353 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2970 23:09:29.246432 ==
2971 23:09:29.246494
2972 23:09:29.249882
2973 23:09:29.249961 TX Vref Scan disable
2974 23:09:29.253433 == TX Byte 0 ==
2975 23:09:29.256258 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
2976 23:09:29.259604 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
2977 23:09:29.262887 == TX Byte 1 ==
2978 23:09:29.266544 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
2979 23:09:29.269975 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
2980 23:09:29.270055
2981 23:09:29.273308 [DATLAT]
2982 23:09:29.273386 Freq=1200, CH0 RK1
2983 23:09:29.273449
2984 23:09:29.276207 DATLAT Default: 0xd
2985 23:09:29.276286 0, 0xFFFF, sum = 0
2986 23:09:29.279726 1, 0xFFFF, sum = 0
2987 23:09:29.279807 2, 0xFFFF, sum = 0
2988 23:09:29.283345 3, 0xFFFF, sum = 0
2989 23:09:29.283426 4, 0xFFFF, sum = 0
2990 23:09:29.286130 5, 0xFFFF, sum = 0
2991 23:09:29.289760 6, 0xFFFF, sum = 0
2992 23:09:29.289852 7, 0xFFFF, sum = 0
2993 23:09:29.292918 8, 0xFFFF, sum = 0
2994 23:09:29.292998 9, 0xFFFF, sum = 0
2995 23:09:29.296610 10, 0xFFFF, sum = 0
2996 23:09:29.296690 11, 0xFFFF, sum = 0
2997 23:09:29.299972 12, 0x0, sum = 1
2998 23:09:29.300053 13, 0x0, sum = 2
2999 23:09:29.302927 14, 0x0, sum = 3
3000 23:09:29.303007 15, 0x0, sum = 4
3001 23:09:29.303071 best_step = 13
3002 23:09:29.303128
3003 23:09:29.306370 ==
3004 23:09:29.309451 Dram Type= 6, Freq= 0, CH_0, rank 1
3005 23:09:29.313255 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3006 23:09:29.313335 ==
3007 23:09:29.313398 RX Vref Scan: 0
3008 23:09:29.313455
3009 23:09:29.316742 RX Vref 0 -> 0, step: 1
3010 23:09:29.316821
3011 23:09:29.320046 RX Delay -13 -> 252, step: 4
3012 23:09:29.322897 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3013 23:09:29.329538 iDelay=195, Bit 1, Center 122 (55 ~ 190) 136
3014 23:09:29.332870 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3015 23:09:29.336160 iDelay=195, Bit 3, Center 118 (51 ~ 186) 136
3016 23:09:29.339750 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3017 23:09:29.343217 iDelay=195, Bit 5, Center 116 (51 ~ 182) 132
3018 23:09:29.346473 iDelay=195, Bit 6, Center 128 (63 ~ 194) 132
3019 23:09:29.353080 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3020 23:09:29.356516 iDelay=195, Bit 8, Center 100 (35 ~ 166) 132
3021 23:09:29.359528 iDelay=195, Bit 9, Center 96 (31 ~ 162) 132
3022 23:09:29.363237 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3023 23:09:29.366746 iDelay=195, Bit 11, Center 100 (35 ~ 166) 132
3024 23:09:29.373041 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3025 23:09:29.376476 iDelay=195, Bit 13, Center 116 (55 ~ 178) 124
3026 23:09:29.379887 iDelay=195, Bit 14, Center 120 (59 ~ 182) 124
3027 23:09:29.383014 iDelay=195, Bit 15, Center 118 (55 ~ 182) 128
3028 23:09:29.383094 ==
3029 23:09:29.386344 Dram Type= 6, Freq= 0, CH_0, rank 1
3030 23:09:29.392907 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3031 23:09:29.392989 ==
3032 23:09:29.393053 DQS Delay:
3033 23:09:29.396310 DQS0 = 0, DQS1 = 0
3034 23:09:29.396391 DQM Delay:
3035 23:09:29.396454 DQM0 = 121, DQM1 = 109
3036 23:09:29.399921 DQ Delay:
3037 23:09:29.403419 DQ0 =118, DQ1 =122, DQ2 =118, DQ3 =118
3038 23:09:29.406153 DQ4 =122, DQ5 =116, DQ6 =128, DQ7 =126
3039 23:09:29.409547 DQ8 =100, DQ9 =96, DQ10 =110, DQ11 =100
3040 23:09:29.413217 DQ12 =114, DQ13 =116, DQ14 =120, DQ15 =118
3041 23:09:29.413297
3042 23:09:29.413360
3043 23:09:29.423291 [DQSOSCAuto] RK1, (LSB)MR18= 0x10f1, (MSB)MR19= 0x403, tDQSOscB0 = 416 ps tDQSOscB1 = 403 ps
3044 23:09:29.423373 CH0 RK1: MR19=403, MR18=10F1
3045 23:09:29.429474 CH0_RK1: MR19=0x403, MR18=0x10F1, DQSOSC=403, MR23=63, INC=40, DEC=26
3046 23:09:29.432970 [RxdqsGatingPostProcess] freq 1200
3047 23:09:29.439890 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3048 23:09:29.442715 best DQS0 dly(2T, 0.5T) = (0, 11)
3049 23:09:29.446202 best DQS1 dly(2T, 0.5T) = (0, 12)
3050 23:09:29.449651 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3051 23:09:29.453153 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3052 23:09:29.453235 best DQS0 dly(2T, 0.5T) = (0, 11)
3053 23:09:29.456483 best DQS1 dly(2T, 0.5T) = (0, 11)
3054 23:09:29.459757 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3055 23:09:29.462916 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3056 23:09:29.466550 Pre-setting of DQS Precalculation
3057 23:09:29.473290 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3058 23:09:29.473372 ==
3059 23:09:29.476751 Dram Type= 6, Freq= 0, CH_1, rank 0
3060 23:09:29.479985 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3061 23:09:29.480067 ==
3062 23:09:29.486430 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3063 23:09:29.489971 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3064 23:09:29.499702 [CA 0] Center 37 (7~68) winsize 62
3065 23:09:29.502752 [CA 1] Center 37 (7~68) winsize 62
3066 23:09:29.506186 [CA 2] Center 35 (5~65) winsize 61
3067 23:09:29.509768 [CA 3] Center 34 (5~64) winsize 60
3068 23:09:29.512754 [CA 4] Center 34 (4~64) winsize 61
3069 23:09:29.516143 [CA 5] Center 33 (3~63) winsize 61
3070 23:09:29.516225
3071 23:09:29.519681 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3072 23:09:29.519760
3073 23:09:29.523058 [CATrainingPosCal] consider 1 rank data
3074 23:09:29.526191 u2DelayCellTimex100 = 270/100 ps
3075 23:09:29.529489 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3076 23:09:29.533062 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3077 23:09:29.539322 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3078 23:09:29.542962 CA3 delay=34 (5~64),Diff = 1 PI (4 cell)
3079 23:09:29.546361 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3080 23:09:29.549600 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3081 23:09:29.549694
3082 23:09:29.553292 CA PerBit enable=1, Macro0, CA PI delay=33
3083 23:09:29.553396
3084 23:09:29.556109 [CBTSetCACLKResult] CA Dly = 33
3085 23:09:29.556189 CS Dly: 8 (0~39)
3086 23:09:29.556253 ==
3087 23:09:29.559628 Dram Type= 6, Freq= 0, CH_1, rank 1
3088 23:09:29.566290 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3089 23:09:29.566400 ==
3090 23:09:29.569347 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3091 23:09:29.576269 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3092 23:09:29.584995 [CA 0] Center 37 (7~68) winsize 62
3093 23:09:29.588418 [CA 1] Center 37 (7~68) winsize 62
3094 23:09:29.591740 [CA 2] Center 35 (5~65) winsize 61
3095 23:09:29.594962 [CA 3] Center 34 (4~65) winsize 62
3096 23:09:29.598826 [CA 4] Center 34 (4~65) winsize 62
3097 23:09:29.601929 [CA 5] Center 34 (4~64) winsize 61
3098 23:09:29.602023
3099 23:09:29.604974 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3100 23:09:29.605060
3101 23:09:29.608514 [CATrainingPosCal] consider 2 rank data
3102 23:09:29.612095 u2DelayCellTimex100 = 270/100 ps
3103 23:09:29.615589 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3104 23:09:29.618556 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3105 23:09:29.625067 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3106 23:09:29.628540 CA3 delay=34 (5~64),Diff = 1 PI (4 cell)
3107 23:09:29.631634 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3108 23:09:29.635489 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3109 23:09:29.635640
3110 23:09:29.638240 CA PerBit enable=1, Macro0, CA PI delay=33
3111 23:09:29.638412
3112 23:09:29.641939 [CBTSetCACLKResult] CA Dly = 33
3113 23:09:29.642138 CS Dly: 8 (0~40)
3114 23:09:29.642327
3115 23:09:29.645527 ----->DramcWriteLeveling(PI) begin...
3116 23:09:29.648500 ==
3117 23:09:29.652331 Dram Type= 6, Freq= 0, CH_1, rank 0
3118 23:09:29.655228 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3119 23:09:29.655642 ==
3120 23:09:29.658914 Write leveling (Byte 0): 24 => 24
3121 23:09:29.661987 Write leveling (Byte 1): 27 => 27
3122 23:09:29.665665 DramcWriteLeveling(PI) end<-----
3123 23:09:29.666140
3124 23:09:29.666524 ==
3125 23:09:29.668784 Dram Type= 6, Freq= 0, CH_1, rank 0
3126 23:09:29.672244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3127 23:09:29.672726 ==
3128 23:09:29.675324 [Gating] SW mode calibration
3129 23:09:29.682186 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3130 23:09:29.685960 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3131 23:09:29.692461 0 15 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3132 23:09:29.695483 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3133 23:09:29.699010 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3134 23:09:29.705858 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3135 23:09:29.708764 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3136 23:09:29.711792 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3137 23:09:29.718495 0 15 24 | B1->B0 | 3131 2424 | 0 0 | (0 1) (0 0)
3138 23:09:29.721930 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3139 23:09:29.725471 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3140 23:09:29.732202 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3141 23:09:29.735314 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3142 23:09:29.738574 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3143 23:09:29.745788 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3144 23:09:29.748669 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3145 23:09:29.752370 1 0 24 | B1->B0 | 3131 3e3d | 0 1 | (1 1) (0 0)
3146 23:09:29.758847 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3147 23:09:29.762425 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3148 23:09:29.765529 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3149 23:09:29.772678 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3150 23:09:29.775483 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3151 23:09:29.779223 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3152 23:09:29.782267 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3153 23:09:29.789465 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3154 23:09:29.792218 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3155 23:09:29.795511 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3156 23:09:29.802350 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3157 23:09:29.805464 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3158 23:09:29.808960 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3159 23:09:29.815645 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3160 23:09:29.819194 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3161 23:09:29.822273 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3162 23:09:29.829102 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3163 23:09:29.832634 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3164 23:09:29.835790 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3165 23:09:29.842207 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3166 23:09:29.846030 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3167 23:09:29.849489 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3168 23:09:29.856231 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3169 23:09:29.859713 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3170 23:09:29.862450 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3171 23:09:29.865838 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3172 23:09:29.869072 Total UI for P1: 0, mck2ui 16
3173 23:09:29.873036 best dqsien dly found for B0: ( 1, 3, 26)
3174 23:09:29.876342 Total UI for P1: 0, mck2ui 16
3175 23:09:29.879106 best dqsien dly found for B1: ( 1, 3, 26)
3176 23:09:29.882548 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3177 23:09:29.885742 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3178 23:09:29.886118
3179 23:09:29.892587 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3180 23:09:29.895859 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3181 23:09:29.899250 [Gating] SW calibration Done
3182 23:09:29.899621 ==
3183 23:09:29.902711 Dram Type= 6, Freq= 0, CH_1, rank 0
3184 23:09:29.905819 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3185 23:09:29.906198 ==
3186 23:09:29.906494 RX Vref Scan: 0
3187 23:09:29.906772
3188 23:09:29.909782 RX Vref 0 -> 0, step: 1
3189 23:09:29.910268
3190 23:09:29.912543 RX Delay -40 -> 252, step: 8
3191 23:09:29.915893 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3192 23:09:29.919071 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3193 23:09:29.922686 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3194 23:09:29.929389 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3195 23:09:29.932920 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3196 23:09:29.936638 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3197 23:09:29.939382 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3198 23:09:29.943015 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3199 23:09:29.949933 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3200 23:09:29.952790 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3201 23:09:29.956497 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3202 23:09:29.959527 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3203 23:09:29.963023 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3204 23:09:29.969497 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3205 23:09:29.972605 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3206 23:09:29.976248 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3207 23:09:29.976631 ==
3208 23:09:29.979563 Dram Type= 6, Freq= 0, CH_1, rank 0
3209 23:09:29.982695 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3210 23:09:29.983242 ==
3211 23:09:29.986252 DQS Delay:
3212 23:09:29.986629 DQS0 = 0, DQS1 = 0
3213 23:09:29.986932 DQM Delay:
3214 23:09:29.989389 DQM0 = 119, DQM1 = 116
3215 23:09:29.989811 DQ Delay:
3216 23:09:29.992585 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3217 23:09:29.996213 DQ4 =119, DQ5 =127, DQ6 =127, DQ7 =119
3218 23:09:30.002557 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =111
3219 23:09:30.006053 DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123
3220 23:09:30.006323
3221 23:09:30.006538
3222 23:09:30.006736 ==
3223 23:09:30.009464 Dram Type= 6, Freq= 0, CH_1, rank 0
3224 23:09:30.012456 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3225 23:09:30.012665 ==
3226 23:09:30.012833
3227 23:09:30.012957
3228 23:09:30.015842 TX Vref Scan disable
3229 23:09:30.019136 == TX Byte 0 ==
3230 23:09:30.022607 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3231 23:09:30.025844 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3232 23:09:30.029058 == TX Byte 1 ==
3233 23:09:30.032777 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3234 23:09:30.036240 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3235 23:09:30.036349 ==
3236 23:09:30.039327 Dram Type= 6, Freq= 0, CH_1, rank 0
3237 23:09:30.042810 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3238 23:09:30.042920 ==
3239 23:09:30.055515 TX Vref=22, minBit 9, minWin=24, winSum=408
3240 23:09:30.058505 TX Vref=24, minBit 9, minWin=25, winSum=417
3241 23:09:30.062044 TX Vref=26, minBit 1, minWin=26, winSum=423
3242 23:09:30.065218 TX Vref=28, minBit 9, minWin=25, winSum=423
3243 23:09:30.068702 TX Vref=30, minBit 9, minWin=26, winSum=430
3244 23:09:30.075208 TX Vref=32, minBit 10, minWin=25, winSum=428
3245 23:09:30.078427 [TxChooseVref] Worse bit 9, Min win 26, Win sum 430, Final Vref 30
3246 23:09:30.078547
3247 23:09:30.081958 Final TX Range 1 Vref 30
3248 23:09:30.082078
3249 23:09:30.082205 ==
3250 23:09:30.085746 Dram Type= 6, Freq= 0, CH_1, rank 0
3251 23:09:30.088583 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3252 23:09:30.091712 ==
3253 23:09:30.091832
3254 23:09:30.091926
3255 23:09:30.092012 TX Vref Scan disable
3256 23:09:30.095460 == TX Byte 0 ==
3257 23:09:30.098533 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3258 23:09:30.102152 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3259 23:09:30.105650 == TX Byte 1 ==
3260 23:09:30.108472 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3261 23:09:30.112081 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3262 23:09:30.115283
3263 23:09:30.115487 [DATLAT]
3264 23:09:30.115603 Freq=1200, CH1 RK0
3265 23:09:30.115705
3266 23:09:30.118480 DATLAT Default: 0xd
3267 23:09:30.118606 0, 0xFFFF, sum = 0
3268 23:09:30.122160 1, 0xFFFF, sum = 0
3269 23:09:30.122282 2, 0xFFFF, sum = 0
3270 23:09:30.125331 3, 0xFFFF, sum = 0
3271 23:09:30.125465 4, 0xFFFF, sum = 0
3272 23:09:30.128450 5, 0xFFFF, sum = 0
3273 23:09:30.132001 6, 0xFFFF, sum = 0
3274 23:09:30.132138 7, 0xFFFF, sum = 0
3275 23:09:30.135150 8, 0xFFFF, sum = 0
3276 23:09:30.135285 9, 0xFFFF, sum = 0
3277 23:09:30.138714 10, 0xFFFF, sum = 0
3278 23:09:30.138849 11, 0xFFFF, sum = 0
3279 23:09:30.141612 12, 0x0, sum = 1
3280 23:09:30.141746 13, 0x0, sum = 2
3281 23:09:30.145296 14, 0x0, sum = 3
3282 23:09:30.145429 15, 0x0, sum = 4
3283 23:09:30.145534 best_step = 13
3284 23:09:30.145650
3285 23:09:30.148887 ==
3286 23:09:30.151984 Dram Type= 6, Freq= 0, CH_1, rank 0
3287 23:09:30.155186 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3288 23:09:30.155320 ==
3289 23:09:30.155426 RX Vref Scan: 1
3290 23:09:30.155524
3291 23:09:30.158830 Set Vref Range= 32 -> 127
3292 23:09:30.158963
3293 23:09:30.166966 RX Vref 32 -> 127, step: 1
3294 23:09:30.167133
3295 23:09:30.167252 RX Delay -5 -> 252, step: 4
3296 23:09:30.167363
3297 23:09:30.169215 Set Vref, RX VrefLevel [Byte0]: 32
3298 23:09:30.171976 [Byte1]: 32
3299 23:09:30.172149
3300 23:09:30.175188 Set Vref, RX VrefLevel [Byte0]: 33
3301 23:09:30.178623 [Byte1]: 33
3302 23:09:30.178826
3303 23:09:30.181728 Set Vref, RX VrefLevel [Byte0]: 34
3304 23:09:30.185501 [Byte1]: 34
3305 23:09:30.189293
3306 23:09:30.189487 Set Vref, RX VrefLevel [Byte0]: 35
3307 23:09:30.192825 [Byte1]: 35
3308 23:09:30.197599
3309 23:09:30.197797 Set Vref, RX VrefLevel [Byte0]: 36
3310 23:09:30.200635 [Byte1]: 36
3311 23:09:30.205498
3312 23:09:30.205739 Set Vref, RX VrefLevel [Byte0]: 37
3313 23:09:30.208601 [Byte1]: 37
3314 23:09:30.212783
3315 23:09:30.212978 Set Vref, RX VrefLevel [Byte0]: 38
3316 23:09:30.216547 [Byte1]: 38
3317 23:09:30.220724
3318 23:09:30.220919 Set Vref, RX VrefLevel [Byte0]: 39
3319 23:09:30.223905 [Byte1]: 39
3320 23:09:30.228906
3321 23:09:30.229119 Set Vref, RX VrefLevel [Byte0]: 40
3322 23:09:30.231932 [Byte1]: 40
3323 23:09:30.236925
3324 23:09:30.237119 Set Vref, RX VrefLevel [Byte0]: 41
3325 23:09:30.239763 [Byte1]: 41
3326 23:09:30.244532
3327 23:09:30.244734 Set Vref, RX VrefLevel [Byte0]: 42
3328 23:09:30.247835 [Byte1]: 42
3329 23:09:30.252148
3330 23:09:30.252418 Set Vref, RX VrefLevel [Byte0]: 43
3331 23:09:30.255540 [Byte1]: 43
3332 23:09:30.260091
3333 23:09:30.260368 Set Vref, RX VrefLevel [Byte0]: 44
3334 23:09:30.263269 [Byte1]: 44
3335 23:09:30.268226
3336 23:09:30.268421 Set Vref, RX VrefLevel [Byte0]: 45
3337 23:09:30.271272 [Byte1]: 45
3338 23:09:30.275790
3339 23:09:30.276113 Set Vref, RX VrefLevel [Byte0]: 46
3340 23:09:30.279470 [Byte1]: 46
3341 23:09:30.284031
3342 23:09:30.284516 Set Vref, RX VrefLevel [Byte0]: 47
3343 23:09:30.287317 [Byte1]: 47
3344 23:09:30.292927
3345 23:09:30.293415 Set Vref, RX VrefLevel [Byte0]: 48
3346 23:09:30.295099 [Byte1]: 48
3347 23:09:30.299615
3348 23:09:30.299987 Set Vref, RX VrefLevel [Byte0]: 49
3349 23:09:30.303208 [Byte1]: 49
3350 23:09:30.307990
3351 23:09:30.308467 Set Vref, RX VrefLevel [Byte0]: 50
3352 23:09:30.310663 [Byte1]: 50
3353 23:09:30.315878
3354 23:09:30.316361 Set Vref, RX VrefLevel [Byte0]: 51
3355 23:09:30.318959 [Byte1]: 51
3356 23:09:30.323378
3357 23:09:30.323867 Set Vref, RX VrefLevel [Byte0]: 52
3358 23:09:30.326575 [Byte1]: 52
3359 23:09:30.331493
3360 23:09:30.331961 Set Vref, RX VrefLevel [Byte0]: 53
3361 23:09:30.334864 [Byte1]: 53
3362 23:09:30.338934
3363 23:09:30.339411 Set Vref, RX VrefLevel [Byte0]: 54
3364 23:09:30.342532 [Byte1]: 54
3365 23:09:30.347509
3366 23:09:30.348021 Set Vref, RX VrefLevel [Byte0]: 55
3367 23:09:30.350279 [Byte1]: 55
3368 23:09:30.354537
3369 23:09:30.355043 Set Vref, RX VrefLevel [Byte0]: 56
3370 23:09:30.358388 [Byte1]: 56
3371 23:09:30.362557
3372 23:09:30.363098 Set Vref, RX VrefLevel [Byte0]: 57
3373 23:09:30.365776 [Byte1]: 57
3374 23:09:30.370578
3375 23:09:30.371045 Set Vref, RX VrefLevel [Byte0]: 58
3376 23:09:30.374093 [Byte1]: 58
3377 23:09:30.378300
3378 23:09:30.379128 Set Vref, RX VrefLevel [Byte0]: 59
3379 23:09:30.381700 [Byte1]: 59
3380 23:09:30.385685
3381 23:09:30.386271 Set Vref, RX VrefLevel [Byte0]: 60
3382 23:09:30.389344 [Byte1]: 60
3383 23:09:30.393903
3384 23:09:30.394308 Set Vref, RX VrefLevel [Byte0]: 61
3385 23:09:30.397347 [Byte1]: 61
3386 23:09:30.401275
3387 23:09:30.402031 Set Vref, RX VrefLevel [Byte0]: 62
3388 23:09:30.404884 [Byte1]: 62
3389 23:09:30.409519
3390 23:09:30.409911 Set Vref, RX VrefLevel [Byte0]: 63
3391 23:09:30.412665 [Byte1]: 63
3392 23:09:30.417352
3393 23:09:30.417750 Set Vref, RX VrefLevel [Byte0]: 64
3394 23:09:30.420664 [Byte1]: 64
3395 23:09:30.425496
3396 23:09:30.426020 Set Vref, RX VrefLevel [Byte0]: 65
3397 23:09:30.428750 [Byte1]: 65
3398 23:09:30.433283
3399 23:09:30.433805 Set Vref, RX VrefLevel [Byte0]: 66
3400 23:09:30.436452 [Byte1]: 66
3401 23:09:30.441792
3402 23:09:30.442259 Set Vref, RX VrefLevel [Byte0]: 67
3403 23:09:30.444482 [Byte1]: 67
3404 23:09:30.449095
3405 23:09:30.449522 Set Vref, RX VrefLevel [Byte0]: 68
3406 23:09:30.452038 [Byte1]: 68
3407 23:09:30.457142
3408 23:09:30.457660 Final RX Vref Byte 0 = 53 to rank0
3409 23:09:30.460062 Final RX Vref Byte 1 = 47 to rank0
3410 23:09:30.463598 Final RX Vref Byte 0 = 53 to rank1
3411 23:09:30.466983 Final RX Vref Byte 1 = 47 to rank1==
3412 23:09:30.470225 Dram Type= 6, Freq= 0, CH_1, rank 0
3413 23:09:30.473939 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3414 23:09:30.477399 ==
3415 23:09:30.477921 DQS Delay:
3416 23:09:30.478228 DQS0 = 0, DQS1 = 0
3417 23:09:30.480580 DQM Delay:
3418 23:09:30.481058 DQM0 = 120, DQM1 = 116
3419 23:09:30.483829 DQ Delay:
3420 23:09:30.487557 DQ0 =124, DQ1 =114, DQ2 =110, DQ3 =116
3421 23:09:30.490272 DQ4 =120, DQ5 =128, DQ6 =130, DQ7 =120
3422 23:09:30.494057 DQ8 =102, DQ9 =106, DQ10 =116, DQ11 =108
3423 23:09:30.497220 DQ12 =122, DQ13 =124, DQ14 =124, DQ15 =126
3424 23:09:30.497785
3425 23:09:30.498115
3426 23:09:30.504224 [DQSOSCAuto] RK0, (LSB)MR18= 0xfd10, (MSB)MR19= 0x304, tDQSOscB0 = 403 ps tDQSOscB1 = 411 ps
3427 23:09:30.506824 CH1 RK0: MR19=304, MR18=FD10
3428 23:09:30.513508 CH1_RK0: MR19=0x304, MR18=0xFD10, DQSOSC=403, MR23=63, INC=40, DEC=26
3429 23:09:30.513994
3430 23:09:30.516638 ----->DramcWriteLeveling(PI) begin...
3431 23:09:30.517053 ==
3432 23:09:30.520202 Dram Type= 6, Freq= 0, CH_1, rank 1
3433 23:09:30.523933 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3434 23:09:30.524455 ==
3435 23:09:30.527085 Write leveling (Byte 0): 25 => 25
3436 23:09:30.530386 Write leveling (Byte 1): 29 => 29
3437 23:09:30.533821 DramcWriteLeveling(PI) end<-----
3438 23:09:30.534344
3439 23:09:30.534669 ==
3440 23:09:30.537168 Dram Type= 6, Freq= 0, CH_1, rank 1
3441 23:09:30.540230 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3442 23:09:30.543905 ==
3443 23:09:30.544511 [Gating] SW mode calibration
3444 23:09:30.553886 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3445 23:09:30.556812 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3446 23:09:30.560545 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3447 23:09:30.566852 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3448 23:09:30.570446 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3449 23:09:30.573673 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3450 23:09:30.580801 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3451 23:09:30.583372 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
3452 23:09:30.587195 0 15 24 | B1->B0 | 2828 3333 | 0 0 | (1 0) (0 1)
3453 23:09:30.593912 0 15 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3454 23:09:30.597210 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3455 23:09:30.600407 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3456 23:09:30.606869 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3457 23:09:30.610144 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3458 23:09:30.613135 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3459 23:09:30.619913 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3460 23:09:30.623235 1 0 24 | B1->B0 | 4040 2929 | 0 0 | (0 0) (0 0)
3461 23:09:30.627054 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3462 23:09:30.633055 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3463 23:09:30.636667 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3464 23:09:30.639634 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3465 23:09:30.646613 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3466 23:09:30.649537 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3467 23:09:30.653405 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3468 23:09:30.656505 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3469 23:09:30.662893 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3470 23:09:30.666506 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3471 23:09:30.669530 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3472 23:09:30.676108 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3473 23:09:30.679674 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3474 23:09:30.683038 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3475 23:09:30.689834 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3476 23:09:30.692675 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3477 23:09:30.696176 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3478 23:09:30.703000 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3479 23:09:30.706064 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3480 23:09:30.709303 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3481 23:09:30.716173 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3482 23:09:30.719560 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3483 23:09:30.722715 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3484 23:09:30.729649 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3485 23:09:30.733151 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3486 23:09:30.736132 Total UI for P1: 0, mck2ui 16
3487 23:09:30.739260 best dqsien dly found for B1: ( 1, 3, 22)
3488 23:09:30.742774 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3489 23:09:30.746370 Total UI for P1: 0, mck2ui 16
3490 23:09:30.749505 best dqsien dly found for B0: ( 1, 3, 26)
3491 23:09:30.752932 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3492 23:09:30.755963 best DQS1 dly(MCK, UI, PI) = (1, 3, 22)
3493 23:09:30.756044
3494 23:09:30.759740 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3495 23:09:30.765756 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 22)
3496 23:09:30.765837 [Gating] SW calibration Done
3497 23:09:30.765902 ==
3498 23:09:30.769251 Dram Type= 6, Freq= 0, CH_1, rank 1
3499 23:09:30.775975 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3500 23:09:30.776056 ==
3501 23:09:30.776120 RX Vref Scan: 0
3502 23:09:30.776179
3503 23:09:30.779293 RX Vref 0 -> 0, step: 1
3504 23:09:30.779376
3505 23:09:30.782319 RX Delay -40 -> 252, step: 8
3506 23:09:30.785529 iDelay=200, Bit 0, Center 127 (64 ~ 191) 128
3507 23:09:30.789117 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
3508 23:09:30.792750 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3509 23:09:30.799349 iDelay=200, Bit 3, Center 119 (56 ~ 183) 128
3510 23:09:30.802237 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3511 23:09:30.806257 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3512 23:09:30.809258 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3513 23:09:30.812348 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3514 23:09:30.819108 iDelay=200, Bit 8, Center 107 (40 ~ 175) 136
3515 23:09:30.822657 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3516 23:09:30.826437 iDelay=200, Bit 10, Center 119 (56 ~ 183) 128
3517 23:09:30.829496 iDelay=200, Bit 11, Center 115 (48 ~ 183) 136
3518 23:09:30.832492 iDelay=200, Bit 12, Center 127 (56 ~ 199) 144
3519 23:09:30.839257 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3520 23:09:30.842591 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3521 23:09:30.845511 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
3522 23:09:30.845730 ==
3523 23:09:30.848991 Dram Type= 6, Freq= 0, CH_1, rank 1
3524 23:09:30.852382 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3525 23:09:30.852579 ==
3526 23:09:30.855424 DQS Delay:
3527 23:09:30.855573 DQS0 = 0, DQS1 = 0
3528 23:09:30.859123 DQM Delay:
3529 23:09:30.859272 DQM0 = 121, DQM1 = 119
3530 23:09:30.862725 DQ Delay:
3531 23:09:30.865913 DQ0 =127, DQ1 =119, DQ2 =107, DQ3 =119
3532 23:09:30.868918 DQ4 =115, DQ5 =131, DQ6 =131, DQ7 =119
3533 23:09:30.872079 DQ8 =107, DQ9 =107, DQ10 =119, DQ11 =115
3534 23:09:30.875260 DQ12 =127, DQ13 =127, DQ14 =123, DQ15 =127
3535 23:09:30.875431
3536 23:09:30.875564
3537 23:09:30.875689 ==
3538 23:09:30.878819 Dram Type= 6, Freq= 0, CH_1, rank 1
3539 23:09:30.882296 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3540 23:09:30.882466 ==
3541 23:09:30.882601
3542 23:09:30.882724
3543 23:09:30.885788 TX Vref Scan disable
3544 23:09:30.888842 == TX Byte 0 ==
3545 23:09:30.892266 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3546 23:09:30.895318 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3547 23:09:30.899018 == TX Byte 1 ==
3548 23:09:30.902084 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3549 23:09:30.905439 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3550 23:09:30.905626 ==
3551 23:09:30.908647 Dram Type= 6, Freq= 0, CH_1, rank 1
3552 23:09:30.915122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3553 23:09:30.915292 ==
3554 23:09:30.926081 TX Vref=22, minBit 10, minWin=25, winSum=420
3555 23:09:30.929017 TX Vref=24, minBit 9, minWin=25, winSum=423
3556 23:09:30.932766 TX Vref=26, minBit 2, minWin=26, winSum=429
3557 23:09:30.935770 TX Vref=28, minBit 8, minWin=26, winSum=432
3558 23:09:30.939514 TX Vref=30, minBit 8, minWin=26, winSum=435
3559 23:09:30.946066 TX Vref=32, minBit 9, minWin=26, winSum=435
3560 23:09:30.949373 [TxChooseVref] Worse bit 8, Min win 26, Win sum 435, Final Vref 30
3561 23:09:30.949471
3562 23:09:30.952228 Final TX Range 1 Vref 30
3563 23:09:30.952317
3564 23:09:30.952385 ==
3565 23:09:30.955630 Dram Type= 6, Freq= 0, CH_1, rank 1
3566 23:09:30.959044 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3567 23:09:30.959133 ==
3568 23:09:30.962118
3569 23:09:30.962206
3570 23:09:30.962274 TX Vref Scan disable
3571 23:09:30.965738 == TX Byte 0 ==
3572 23:09:30.968877 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3573 23:09:30.972630 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3574 23:09:30.975711 == TX Byte 1 ==
3575 23:09:30.979683 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3576 23:09:30.982598 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3577 23:09:30.982687
3578 23:09:30.985571 [DATLAT]
3579 23:09:30.985668 Freq=1200, CH1 RK1
3580 23:09:30.985739
3581 23:09:30.989182 DATLAT Default: 0xd
3582 23:09:30.989269 0, 0xFFFF, sum = 0
3583 23:09:30.992370 1, 0xFFFF, sum = 0
3584 23:09:30.992459 2, 0xFFFF, sum = 0
3585 23:09:30.995699 3, 0xFFFF, sum = 0
3586 23:09:30.995789 4, 0xFFFF, sum = 0
3587 23:09:30.999058 5, 0xFFFF, sum = 0
3588 23:09:30.999149 6, 0xFFFF, sum = 0
3589 23:09:31.002484 7, 0xFFFF, sum = 0
3590 23:09:31.005478 8, 0xFFFF, sum = 0
3591 23:09:31.005568 9, 0xFFFF, sum = 0
3592 23:09:31.009250 10, 0xFFFF, sum = 0
3593 23:09:31.009339 11, 0xFFFF, sum = 0
3594 23:09:31.012109 12, 0x0, sum = 1
3595 23:09:31.012198 13, 0x0, sum = 2
3596 23:09:31.015660 14, 0x0, sum = 3
3597 23:09:31.015749 15, 0x0, sum = 4
3598 23:09:31.015820 best_step = 13
3599 23:09:31.015885
3600 23:09:31.019206 ==
3601 23:09:31.022553 Dram Type= 6, Freq= 0, CH_1, rank 1
3602 23:09:31.025907 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3603 23:09:31.025994 ==
3604 23:09:31.026063 RX Vref Scan: 0
3605 23:09:31.026127
3606 23:09:31.029133 RX Vref 0 -> 0, step: 1
3607 23:09:31.029219
3608 23:09:31.032595 RX Delay -5 -> 252, step: 4
3609 23:09:31.035704 iDelay=195, Bit 0, Center 122 (59 ~ 186) 128
3610 23:09:31.038870 iDelay=195, Bit 1, Center 116 (55 ~ 178) 124
3611 23:09:31.045925 iDelay=195, Bit 2, Center 110 (51 ~ 170) 120
3612 23:09:31.048906 iDelay=195, Bit 3, Center 116 (55 ~ 178) 124
3613 23:09:31.052561 iDelay=195, Bit 4, Center 116 (55 ~ 178) 124
3614 23:09:31.055752 iDelay=195, Bit 5, Center 132 (71 ~ 194) 124
3615 23:09:31.058886 iDelay=195, Bit 6, Center 130 (67 ~ 194) 128
3616 23:09:31.065427 iDelay=195, Bit 7, Center 118 (55 ~ 182) 128
3617 23:09:31.068738 iDelay=195, Bit 8, Center 104 (43 ~ 166) 124
3618 23:09:31.072247 iDelay=195, Bit 9, Center 106 (47 ~ 166) 120
3619 23:09:31.075285 iDelay=195, Bit 10, Center 116 (55 ~ 178) 124
3620 23:09:31.082113 iDelay=195, Bit 11, Center 110 (51 ~ 170) 120
3621 23:09:31.085285 iDelay=195, Bit 12, Center 126 (63 ~ 190) 128
3622 23:09:31.089030 iDelay=195, Bit 13, Center 124 (67 ~ 182) 116
3623 23:09:31.091963 iDelay=195, Bit 14, Center 122 (63 ~ 182) 120
3624 23:09:31.095663 iDelay=195, Bit 15, Center 124 (63 ~ 186) 124
3625 23:09:31.095750 ==
3626 23:09:31.098804 Dram Type= 6, Freq= 0, CH_1, rank 1
3627 23:09:31.106175 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3628 23:09:31.106267 ==
3629 23:09:31.106339 DQS Delay:
3630 23:09:31.108795 DQS0 = 0, DQS1 = 0
3631 23:09:31.108882 DQM Delay:
3632 23:09:31.108950 DQM0 = 120, DQM1 = 116
3633 23:09:31.112211 DQ Delay:
3634 23:09:31.115744 DQ0 =122, DQ1 =116, DQ2 =110, DQ3 =116
3635 23:09:31.118628 DQ4 =116, DQ5 =132, DQ6 =130, DQ7 =118
3636 23:09:31.122221 DQ8 =104, DQ9 =106, DQ10 =116, DQ11 =110
3637 23:09:31.125370 DQ12 =126, DQ13 =124, DQ14 =122, DQ15 =124
3638 23:09:31.125460
3639 23:09:31.125563
3640 23:09:31.135509 [DQSOSCAuto] RK1, (LSB)MR18= 0x11ef, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 403 ps
3641 23:09:31.135600 CH1 RK1: MR19=403, MR18=11EF
3642 23:09:31.142269 CH1_RK1: MR19=0x403, MR18=0x11EF, DQSOSC=403, MR23=63, INC=40, DEC=26
3643 23:09:31.145208 [RxdqsGatingPostProcess] freq 1200
3644 23:09:31.151763 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3645 23:09:31.155293 best DQS0 dly(2T, 0.5T) = (0, 11)
3646 23:09:31.158528 best DQS1 dly(2T, 0.5T) = (0, 11)
3647 23:09:31.162089 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3648 23:09:31.165419 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3649 23:09:31.168566 best DQS0 dly(2T, 0.5T) = (0, 11)
3650 23:09:31.171691 best DQS1 dly(2T, 0.5T) = (0, 11)
3651 23:09:31.175111 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3652 23:09:31.175199 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3653 23:09:31.178579 Pre-setting of DQS Precalculation
3654 23:09:31.185457 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3655 23:09:31.191677 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3656 23:09:31.198539 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3657 23:09:31.198627
3658 23:09:31.198698
3659 23:09:31.202153 [Calibration Summary] 2400 Mbps
3660 23:09:31.205173 CH 0, Rank 0
3661 23:09:31.205260 SW Impedance : PASS
3662 23:09:31.208326 DUTY Scan : NO K
3663 23:09:31.208413 ZQ Calibration : PASS
3664 23:09:31.211907 Jitter Meter : NO K
3665 23:09:31.214873 CBT Training : PASS
3666 23:09:31.214963 Write leveling : PASS
3667 23:09:31.218243 RX DQS gating : PASS
3668 23:09:31.221636 RX DQ/DQS(RDDQC) : PASS
3669 23:09:31.221723 TX DQ/DQS : PASS
3670 23:09:31.225245 RX DATLAT : PASS
3671 23:09:31.228209 RX DQ/DQS(Engine): PASS
3672 23:09:31.228297 TX OE : NO K
3673 23:09:31.231816 All Pass.
3674 23:09:31.231906
3675 23:09:31.232021 CH 0, Rank 1
3676 23:09:31.235216 SW Impedance : PASS
3677 23:09:31.235303 DUTY Scan : NO K
3678 23:09:31.238598 ZQ Calibration : PASS
3679 23:09:31.241581 Jitter Meter : NO K
3680 23:09:31.241668 CBT Training : PASS
3681 23:09:31.245310 Write leveling : PASS
3682 23:09:31.248684 RX DQS gating : PASS
3683 23:09:31.248867 RX DQ/DQS(RDDQC) : PASS
3684 23:09:31.251946 TX DQ/DQS : PASS
3685 23:09:31.255409 RX DATLAT : PASS
3686 23:09:31.255600 RX DQ/DQS(Engine): PASS
3687 23:09:31.258491 TX OE : NO K
3688 23:09:31.258695 All Pass.
3689 23:09:31.258809
3690 23:09:31.261909 CH 1, Rank 0
3691 23:09:31.262131 SW Impedance : PASS
3692 23:09:31.265140 DUTY Scan : NO K
3693 23:09:31.268320 ZQ Calibration : PASS
3694 23:09:31.268562 Jitter Meter : NO K
3695 23:09:31.271740 CBT Training : PASS
3696 23:09:31.271980 Write leveling : PASS
3697 23:09:31.274808 RX DQS gating : PASS
3698 23:09:31.278053 RX DQ/DQS(RDDQC) : PASS
3699 23:09:31.278262 TX DQ/DQS : PASS
3700 23:09:31.281931 RX DATLAT : PASS
3701 23:09:31.284935 RX DQ/DQS(Engine): PASS
3702 23:09:31.285205 TX OE : NO K
3703 23:09:31.288311 All Pass.
3704 23:09:31.288654
3705 23:09:31.288898 CH 1, Rank 1
3706 23:09:31.291721 SW Impedance : PASS
3707 23:09:31.292105 DUTY Scan : NO K
3708 23:09:31.295136 ZQ Calibration : PASS
3709 23:09:31.298450 Jitter Meter : NO K
3710 23:09:31.298965 CBT Training : PASS
3711 23:09:31.302063 Write leveling : PASS
3712 23:09:31.305324 RX DQS gating : PASS
3713 23:09:31.305760 RX DQ/DQS(RDDQC) : PASS
3714 23:09:31.308251 TX DQ/DQS : PASS
3715 23:09:31.312162 RX DATLAT : PASS
3716 23:09:31.312680 RX DQ/DQS(Engine): PASS
3717 23:09:31.314954 TX OE : NO K
3718 23:09:31.315368 All Pass.
3719 23:09:31.315699
3720 23:09:31.318145 DramC Write-DBI off
3721 23:09:31.321973 PER_BANK_REFRESH: Hybrid Mode
3722 23:09:31.322519 TX_TRACKING: ON
3723 23:09:31.332228 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3724 23:09:31.335196 [FAST_K] Save calibration result to emmc
3725 23:09:31.338123 dramc_set_vcore_voltage set vcore to 650000
3726 23:09:31.341340 Read voltage for 600, 5
3727 23:09:31.341803 Vio18 = 0
3728 23:09:31.342136 Vcore = 650000
3729 23:09:31.344916 Vdram = 0
3730 23:09:31.345421 Vddq = 0
3731 23:09:31.345806 Vmddr = 0
3732 23:09:31.352123 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3733 23:09:31.355331 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3734 23:09:31.358353 MEM_TYPE=3, freq_sel=19
3735 23:09:31.362216 sv_algorithm_assistance_LP4_1600
3736 23:09:31.364991 ============ PULL DRAM RESETB DOWN ============
3737 23:09:31.368725 ========== PULL DRAM RESETB DOWN end =========
3738 23:09:31.375403 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3739 23:09:31.378126 ===================================
3740 23:09:31.378542 LPDDR4 DRAM CONFIGURATION
3741 23:09:31.381962 ===================================
3742 23:09:31.384826 EX_ROW_EN[0] = 0x0
3743 23:09:31.388393 EX_ROW_EN[1] = 0x0
3744 23:09:31.388906 LP4Y_EN = 0x0
3745 23:09:31.391987 WORK_FSP = 0x0
3746 23:09:31.392513 WL = 0x2
3747 23:09:31.394692 RL = 0x2
3748 23:09:31.395175 BL = 0x2
3749 23:09:31.398266 RPST = 0x0
3750 23:09:31.398778 RD_PRE = 0x0
3751 23:09:31.401708 WR_PRE = 0x1
3752 23:09:31.402155 WR_PST = 0x0
3753 23:09:31.405223 DBI_WR = 0x0
3754 23:09:31.405771 DBI_RD = 0x0
3755 23:09:31.407866 OTF = 0x1
3756 23:09:31.411366 ===================================
3757 23:09:31.414878 ===================================
3758 23:09:31.415290 ANA top config
3759 23:09:31.417676 ===================================
3760 23:09:31.421413 DLL_ASYNC_EN = 0
3761 23:09:31.424782 ALL_SLAVE_EN = 1
3762 23:09:31.425189 NEW_RANK_MODE = 1
3763 23:09:31.428189 DLL_IDLE_MODE = 1
3764 23:09:31.431306 LP45_APHY_COMB_EN = 1
3765 23:09:31.434934 TX_ODT_DIS = 1
3766 23:09:31.437683 NEW_8X_MODE = 1
3767 23:09:31.441418 ===================================
3768 23:09:31.444550 ===================================
3769 23:09:31.444966 data_rate = 1200
3770 23:09:31.448243 CKR = 1
3771 23:09:31.451550 DQ_P2S_RATIO = 8
3772 23:09:31.454748 ===================================
3773 23:09:31.458073 CA_P2S_RATIO = 8
3774 23:09:31.461416 DQ_CA_OPEN = 0
3775 23:09:31.465161 DQ_SEMI_OPEN = 0
3776 23:09:31.465836 CA_SEMI_OPEN = 0
3777 23:09:31.468091 CA_FULL_RATE = 0
3778 23:09:31.471447 DQ_CKDIV4_EN = 1
3779 23:09:31.474858 CA_CKDIV4_EN = 1
3780 23:09:31.477661 CA_PREDIV_EN = 0
3781 23:09:31.481535 PH8_DLY = 0
3782 23:09:31.482086 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3783 23:09:31.485147 DQ_AAMCK_DIV = 4
3784 23:09:31.488294 CA_AAMCK_DIV = 4
3785 23:09:31.491826 CA_ADMCK_DIV = 4
3786 23:09:31.494966 DQ_TRACK_CA_EN = 0
3787 23:09:31.498050 CA_PICK = 600
3788 23:09:31.498570 CA_MCKIO = 600
3789 23:09:31.501644 MCKIO_SEMI = 0
3790 23:09:31.505195 PLL_FREQ = 2288
3791 23:09:31.507728 DQ_UI_PI_RATIO = 32
3792 23:09:31.510933 CA_UI_PI_RATIO = 0
3793 23:09:31.514826 ===================================
3794 23:09:31.517766 ===================================
3795 23:09:31.521658 memory_type:LPDDR4
3796 23:09:31.522073 GP_NUM : 10
3797 23:09:31.524484 SRAM_EN : 1
3798 23:09:31.525068 MD32_EN : 0
3799 23:09:31.528074 ===================================
3800 23:09:31.530969 [ANA_INIT] >>>>>>>>>>>>>>
3801 23:09:31.535157 <<<<<< [CONFIGURE PHASE]: ANA_TX
3802 23:09:31.537934 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3803 23:09:31.541367 ===================================
3804 23:09:31.544543 data_rate = 1200,PCW = 0X5800
3805 23:09:31.548450 ===================================
3806 23:09:31.551070 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3807 23:09:31.554608 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3808 23:09:31.561430 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3809 23:09:31.564924 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3810 23:09:31.567959 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3811 23:09:31.574493 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3812 23:09:31.574919 [ANA_INIT] flow start
3813 23:09:31.577757 [ANA_INIT] PLL >>>>>>>>
3814 23:09:31.578170 [ANA_INIT] PLL <<<<<<<<
3815 23:09:31.581105 [ANA_INIT] MIDPI >>>>>>>>
3816 23:09:31.584583 [ANA_INIT] MIDPI <<<<<<<<
3817 23:09:31.588134 [ANA_INIT] DLL >>>>>>>>
3818 23:09:31.588604 [ANA_INIT] flow end
3819 23:09:31.591108 ============ LP4 DIFF to SE enter ============
3820 23:09:31.597647 ============ LP4 DIFF to SE exit ============
3821 23:09:31.598069 [ANA_INIT] <<<<<<<<<<<<<
3822 23:09:31.600908 [Flow] Enable top DCM control >>>>>
3823 23:09:31.604576 [Flow] Enable top DCM control <<<<<
3824 23:09:31.607691 Enable DLL master slave shuffle
3825 23:09:31.614181 ==============================================================
3826 23:09:31.614597 Gating Mode config
3827 23:09:31.621359 ==============================================================
3828 23:09:31.624639 Config description:
3829 23:09:31.634259 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3830 23:09:31.641042 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3831 23:09:31.643997 SELPH_MODE 0: By rank 1: By Phase
3832 23:09:31.650624 ==============================================================
3833 23:09:31.653614 GAT_TRACK_EN = 1
3834 23:09:31.657162 RX_GATING_MODE = 2
3835 23:09:31.661032 RX_GATING_TRACK_MODE = 2
3836 23:09:31.661551 SELPH_MODE = 1
3837 23:09:31.664195 PICG_EARLY_EN = 1
3838 23:09:31.666805 VALID_LAT_VALUE = 1
3839 23:09:31.673908 ==============================================================
3840 23:09:31.677131 Enter into Gating configuration >>>>
3841 23:09:31.680438 Exit from Gating configuration <<<<
3842 23:09:31.683536 Enter into DVFS_PRE_config >>>>>
3843 23:09:31.693713 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3844 23:09:31.697501 Exit from DVFS_PRE_config <<<<<
3845 23:09:31.700294 Enter into PICG configuration >>>>
3846 23:09:31.703937 Exit from PICG configuration <<<<
3847 23:09:31.707610 [RX_INPUT] configuration >>>>>
3848 23:09:31.710342 [RX_INPUT] configuration <<<<<
3849 23:09:31.713742 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3850 23:09:31.720319 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3851 23:09:31.727453 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3852 23:09:31.734280 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3853 23:09:31.736994 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3854 23:09:31.743499 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3855 23:09:31.746994 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3856 23:09:31.753316 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3857 23:09:31.756896 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3858 23:09:31.760229 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3859 23:09:31.763889 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3860 23:09:31.770219 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3861 23:09:31.773484 ===================================
3862 23:09:31.776877 LPDDR4 DRAM CONFIGURATION
3863 23:09:31.780295 ===================================
3864 23:09:31.780811 EX_ROW_EN[0] = 0x0
3865 23:09:31.783610 EX_ROW_EN[1] = 0x0
3866 23:09:31.784018 LP4Y_EN = 0x0
3867 23:09:31.786839 WORK_FSP = 0x0
3868 23:09:31.787353 WL = 0x2
3869 23:09:31.790016 RL = 0x2
3870 23:09:31.790533 BL = 0x2
3871 23:09:31.793218 RPST = 0x0
3872 23:09:31.793660 RD_PRE = 0x0
3873 23:09:31.796993 WR_PRE = 0x1
3874 23:09:31.797400 WR_PST = 0x0
3875 23:09:31.799968 DBI_WR = 0x0
3876 23:09:31.800379 DBI_RD = 0x0
3877 23:09:31.803299 OTF = 0x1
3878 23:09:31.806726 ===================================
3879 23:09:31.809784 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3880 23:09:31.813236 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3881 23:09:31.820030 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3882 23:09:31.823589 ===================================
3883 23:09:31.824007 LPDDR4 DRAM CONFIGURATION
3884 23:09:31.826616 ===================================
3885 23:09:31.830342 EX_ROW_EN[0] = 0x10
3886 23:09:31.833372 EX_ROW_EN[1] = 0x0
3887 23:09:31.833950 LP4Y_EN = 0x0
3888 23:09:31.836650 WORK_FSP = 0x0
3889 23:09:31.837061 WL = 0x2
3890 23:09:31.840356 RL = 0x2
3891 23:09:31.840876 BL = 0x2
3892 23:09:31.843132 RPST = 0x0
3893 23:09:31.843544 RD_PRE = 0x0
3894 23:09:31.846668 WR_PRE = 0x1
3895 23:09:31.847078 WR_PST = 0x0
3896 23:09:31.850138 DBI_WR = 0x0
3897 23:09:31.850548 DBI_RD = 0x0
3898 23:09:31.852994 OTF = 0x1
3899 23:09:31.856828 ===================================
3900 23:09:31.863379 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3901 23:09:31.866173 nWR fixed to 30
3902 23:09:31.869665 [ModeRegInit_LP4] CH0 RK0
3903 23:09:31.870182 [ModeRegInit_LP4] CH0 RK1
3904 23:09:31.873212 [ModeRegInit_LP4] CH1 RK0
3905 23:09:31.876117 [ModeRegInit_LP4] CH1 RK1
3906 23:09:31.876525 match AC timing 17
3907 23:09:31.883480 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3908 23:09:31.886917 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3909 23:09:31.889562 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3910 23:09:31.896395 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3911 23:09:31.899257 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3912 23:09:31.899700 ==
3913 23:09:31.903010 Dram Type= 6, Freq= 0, CH_0, rank 0
3914 23:09:31.906057 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3915 23:09:31.906470 ==
3916 23:09:31.912485 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3917 23:09:31.919263 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3918 23:09:31.922937 [CA 0] Center 35 (5~66) winsize 62
3919 23:09:31.926239 [CA 1] Center 36 (5~67) winsize 63
3920 23:09:31.928978 [CA 2] Center 33 (3~64) winsize 62
3921 23:09:31.932636 [CA 3] Center 33 (2~64) winsize 63
3922 23:09:31.935978 [CA 4] Center 33 (2~64) winsize 63
3923 23:09:31.939104 [CA 5] Center 32 (2~63) winsize 62
3924 23:09:31.939512
3925 23:09:31.942630 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3926 23:09:31.943038
3927 23:09:31.945622 [CATrainingPosCal] consider 1 rank data
3928 23:09:31.949516 u2DelayCellTimex100 = 270/100 ps
3929 23:09:31.952368 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3930 23:09:31.956080 CA1 delay=36 (5~67),Diff = 4 PI (38 cell)
3931 23:09:31.959460 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3932 23:09:31.962323 CA3 delay=33 (2~64),Diff = 1 PI (9 cell)
3933 23:09:31.966085 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3934 23:09:31.972624 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3935 23:09:31.973139
3936 23:09:31.975551 CA PerBit enable=1, Macro0, CA PI delay=32
3937 23:09:31.976072
3938 23:09:31.978808 [CBTSetCACLKResult] CA Dly = 32
3939 23:09:31.979221 CS Dly: 4 (0~35)
3940 23:09:31.979549 ==
3941 23:09:31.981909 Dram Type= 6, Freq= 0, CH_0, rank 1
3942 23:09:31.985737 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3943 23:09:31.989336 ==
3944 23:09:31.992147 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3945 23:09:31.998710 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3946 23:09:32.001748 [CA 0] Center 35 (5~66) winsize 62
3947 23:09:32.005764 [CA 1] Center 35 (5~66) winsize 62
3948 23:09:32.008869 [CA 2] Center 34 (3~65) winsize 63
3949 23:09:32.012255 [CA 3] Center 33 (3~64) winsize 62
3950 23:09:32.015490 [CA 4] Center 33 (2~64) winsize 63
3951 23:09:32.018452 [CA 5] Center 32 (2~63) winsize 62
3952 23:09:32.018965
3953 23:09:32.021707 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3954 23:09:32.022117
3955 23:09:32.024942 [CATrainingPosCal] consider 2 rank data
3956 23:09:32.028272 u2DelayCellTimex100 = 270/100 ps
3957 23:09:32.031516 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3958 23:09:32.035208 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3959 23:09:32.038047 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3960 23:09:32.045300 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
3961 23:09:32.048248 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3962 23:09:32.051677 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3963 23:09:32.052090
3964 23:09:32.055284 CA PerBit enable=1, Macro0, CA PI delay=32
3965 23:09:32.055694
3966 23:09:32.058103 [CBTSetCACLKResult] CA Dly = 32
3967 23:09:32.058516 CS Dly: 4 (0~36)
3968 23:09:32.058842
3969 23:09:32.061658 ----->DramcWriteLeveling(PI) begin...
3970 23:09:32.062076 ==
3971 23:09:32.065004 Dram Type= 6, Freq= 0, CH_0, rank 0
3972 23:09:32.071499 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3973 23:09:32.072018 ==
3974 23:09:32.075151 Write leveling (Byte 0): 33 => 33
3975 23:09:32.078234 Write leveling (Byte 1): 31 => 31
3976 23:09:32.078747 DramcWriteLeveling(PI) end<-----
3977 23:09:32.081750
3978 23:09:32.082431 ==
3979 23:09:32.084909 Dram Type= 6, Freq= 0, CH_0, rank 0
3980 23:09:32.088796 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3981 23:09:32.089312 ==
3982 23:09:32.091870 [Gating] SW mode calibration
3983 23:09:32.098421 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3984 23:09:32.102241 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3985 23:09:32.108601 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3986 23:09:32.111609 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3987 23:09:32.114843 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3988 23:09:32.121645 0 9 12 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
3989 23:09:32.124631 0 9 16 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
3990 23:09:32.128156 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3991 23:09:32.134479 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3992 23:09:32.137930 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3993 23:09:32.141318 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3994 23:09:32.147999 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3995 23:09:32.151412 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3996 23:09:32.154405 0 10 12 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
3997 23:09:32.161261 0 10 16 | B1->B0 | 3232 4646 | 1 0 | (0 0) (0 0)
3998 23:09:32.164829 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3999 23:09:32.167808 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4000 23:09:32.175016 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4001 23:09:32.177737 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4002 23:09:32.181167 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4003 23:09:32.188188 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4004 23:09:32.191216 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4005 23:09:32.194065 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4006 23:09:32.200633 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4007 23:09:32.204423 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4008 23:09:32.207692 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4009 23:09:32.214237 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4010 23:09:32.217198 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4011 23:09:32.221077 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4012 23:09:32.227526 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4013 23:09:32.230923 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4014 23:09:32.233761 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4015 23:09:32.237278 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4016 23:09:32.244503 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4017 23:09:32.247590 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4018 23:09:32.251102 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4019 23:09:32.257621 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4020 23:09:32.260848 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4021 23:09:32.264541 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4022 23:09:32.267705 Total UI for P1: 0, mck2ui 16
4023 23:09:32.270832 best dqsien dly found for B0: ( 0, 13, 12)
4024 23:09:32.277159 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4025 23:09:32.277573 Total UI for P1: 0, mck2ui 16
4026 23:09:32.284032 best dqsien dly found for B1: ( 0, 13, 16)
4027 23:09:32.287199 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4028 23:09:32.290434 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4029 23:09:32.290904
4030 23:09:32.293806 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4031 23:09:32.297385 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4032 23:09:32.300477 [Gating] SW calibration Done
4033 23:09:32.300986 ==
4034 23:09:32.303920 Dram Type= 6, Freq= 0, CH_0, rank 0
4035 23:09:32.307491 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4036 23:09:32.308006 ==
4037 23:09:32.310879 RX Vref Scan: 0
4038 23:09:32.311393
4039 23:09:32.311720 RX Vref 0 -> 0, step: 1
4040 23:09:32.313680
4041 23:09:32.314090 RX Delay -230 -> 252, step: 16
4042 23:09:32.320443 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4043 23:09:32.323571 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4044 23:09:32.327342 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4045 23:09:32.330357 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4046 23:09:32.337025 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4047 23:09:32.340732 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4048 23:09:32.343480 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4049 23:09:32.346907 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4050 23:09:32.350403 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4051 23:09:32.357512 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4052 23:09:32.360193 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4053 23:09:32.364049 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4054 23:09:32.366801 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4055 23:09:32.373646 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4056 23:09:32.377462 iDelay=218, Bit 14, Center 65 (-86 ~ 217) 304
4057 23:09:32.380534 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4058 23:09:32.381049 ==
4059 23:09:32.383480 Dram Type= 6, Freq= 0, CH_0, rank 0
4060 23:09:32.386894 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4061 23:09:32.387309 ==
4062 23:09:32.390215 DQS Delay:
4063 23:09:32.390624 DQS0 = 0, DQS1 = 0
4064 23:09:32.393443 DQM Delay:
4065 23:09:32.393894 DQM0 = 52, DQM1 = 45
4066 23:09:32.394221 DQ Delay:
4067 23:09:32.396753 DQ0 =49, DQ1 =57, DQ2 =41, DQ3 =41
4068 23:09:32.400178 DQ4 =57, DQ5 =41, DQ6 =65, DQ7 =65
4069 23:09:32.403064 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =41
4070 23:09:32.406482 DQ12 =49, DQ13 =49, DQ14 =65, DQ15 =49
4071 23:09:32.406996
4072 23:09:32.407324
4073 23:09:32.409921 ==
4074 23:09:32.410329 Dram Type= 6, Freq= 0, CH_0, rank 0
4075 23:09:32.417057 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4076 23:09:32.417664 ==
4077 23:09:32.418178
4078 23:09:32.418505
4079 23:09:32.420262 TX Vref Scan disable
4080 23:09:32.420666 == TX Byte 0 ==
4081 23:09:32.423196 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4082 23:09:32.429887 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4083 23:09:32.430299 == TX Byte 1 ==
4084 23:09:32.433177 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4085 23:09:32.440053 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4086 23:09:32.440465 ==
4087 23:09:32.442933 Dram Type= 6, Freq= 0, CH_0, rank 0
4088 23:09:32.446343 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4089 23:09:32.446796 ==
4090 23:09:32.447123
4091 23:09:32.447421
4092 23:09:32.449952 TX Vref Scan disable
4093 23:09:32.453125 == TX Byte 0 ==
4094 23:09:32.456203 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4095 23:09:32.459521 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4096 23:09:32.463025 == TX Byte 1 ==
4097 23:09:32.466358 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4098 23:09:32.469432 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4099 23:09:32.469899
4100 23:09:32.472977 [DATLAT]
4101 23:09:32.473392 Freq=600, CH0 RK0
4102 23:09:32.473776
4103 23:09:32.476452 DATLAT Default: 0x9
4104 23:09:32.476867 0, 0xFFFF, sum = 0
4105 23:09:32.479412 1, 0xFFFF, sum = 0
4106 23:09:32.479832 2, 0xFFFF, sum = 0
4107 23:09:32.483356 3, 0xFFFF, sum = 0
4108 23:09:32.483888 4, 0xFFFF, sum = 0
4109 23:09:32.486098 5, 0xFFFF, sum = 0
4110 23:09:32.486518 6, 0xFFFF, sum = 0
4111 23:09:32.489878 7, 0xFFFF, sum = 0
4112 23:09:32.490406 8, 0x0, sum = 1
4113 23:09:32.493021 9, 0x0, sum = 2
4114 23:09:32.493548 10, 0x0, sum = 3
4115 23:09:32.496600 11, 0x0, sum = 4
4116 23:09:32.497129 best_step = 9
4117 23:09:32.497462
4118 23:09:32.497833 ==
4119 23:09:32.499591 Dram Type= 6, Freq= 0, CH_0, rank 0
4120 23:09:32.503161 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4121 23:09:32.506319 ==
4122 23:09:32.506844 RX Vref Scan: 1
4123 23:09:32.507176
4124 23:09:32.509634 RX Vref 0 -> 0, step: 1
4125 23:09:32.510061
4126 23:09:32.512874 RX Delay -163 -> 252, step: 8
4127 23:09:32.513360
4128 23:09:32.516392 Set Vref, RX VrefLevel [Byte0]: 53
4129 23:09:32.519601 [Byte1]: 46
4130 23:09:32.520135
4131 23:09:32.522842 Final RX Vref Byte 0 = 53 to rank0
4132 23:09:32.525796 Final RX Vref Byte 1 = 46 to rank0
4133 23:09:32.529305 Final RX Vref Byte 0 = 53 to rank1
4134 23:09:32.532860 Final RX Vref Byte 1 = 46 to rank1==
4135 23:09:32.536030 Dram Type= 6, Freq= 0, CH_0, rank 0
4136 23:09:32.539189 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4137 23:09:32.539610 ==
4138 23:09:32.540016 DQS Delay:
4139 23:09:32.542553 DQS0 = 0, DQS1 = 0
4140 23:09:32.542966 DQM Delay:
4141 23:09:32.545697 DQM0 = 52, DQM1 = 45
4142 23:09:32.546114 DQ Delay:
4143 23:09:32.549436 DQ0 =52, DQ1 =52, DQ2 =48, DQ3 =52
4144 23:09:32.553201 DQ4 =52, DQ5 =44, DQ6 =60, DQ7 =56
4145 23:09:32.556069 DQ8 =36, DQ9 =32, DQ10 =44, DQ11 =40
4146 23:09:32.559400 DQ12 =52, DQ13 =52, DQ14 =56, DQ15 =52
4147 23:09:32.559819
4148 23:09:32.560145
4149 23:09:32.569441 [DQSOSCAuto] RK0, (LSB)MR18= 0x6e61, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 389 ps
4150 23:09:32.570015 CH0 RK0: MR19=808, MR18=6E61
4151 23:09:32.576688 CH0_RK0: MR19=0x808, MR18=0x6E61, DQSOSC=389, MR23=63, INC=173, DEC=115
4152 23:09:32.577212
4153 23:09:32.579500 ----->DramcWriteLeveling(PI) begin...
4154 23:09:32.580028 ==
4155 23:09:32.583085 Dram Type= 6, Freq= 0, CH_0, rank 1
4156 23:09:32.589815 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4157 23:09:32.590337 ==
4158 23:09:32.592688 Write leveling (Byte 0): 34 => 34
4159 23:09:32.596751 Write leveling (Byte 1): 33 => 33
4160 23:09:32.597275 DramcWriteLeveling(PI) end<-----
4161 23:09:32.597654
4162 23:09:32.599482 ==
4163 23:09:32.602535 Dram Type= 6, Freq= 0, CH_0, rank 1
4164 23:09:32.606048 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4165 23:09:32.606466 ==
4166 23:09:32.609954 [Gating] SW mode calibration
4167 23:09:32.615978 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4168 23:09:32.619510 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4169 23:09:32.625796 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4170 23:09:32.629451 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4171 23:09:32.632380 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4172 23:09:32.638910 0 9 12 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 0)
4173 23:09:32.642379 0 9 16 | B1->B0 | 2525 2424 | 0 0 | (0 0) (0 0)
4174 23:09:32.645630 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4175 23:09:32.652604 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4176 23:09:32.656123 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4177 23:09:32.658969 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4178 23:09:32.666016 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4179 23:09:32.668989 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4180 23:09:32.672481 0 10 12 | B1->B0 | 2727 2a29 | 0 1 | (0 0) (0 0)
4181 23:09:32.679241 0 10 16 | B1->B0 | 4444 4141 | 0 0 | (0 0) (0 0)
4182 23:09:32.682254 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4183 23:09:32.685929 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4184 23:09:32.692257 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4185 23:09:32.695506 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4186 23:09:32.699033 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4187 23:09:32.705517 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4188 23:09:32.708722 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4189 23:09:32.712237 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4190 23:09:32.715497 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4191 23:09:32.721742 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4192 23:09:32.725344 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4193 23:09:32.728486 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4194 23:09:32.735393 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4195 23:09:32.738360 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4196 23:09:32.741960 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4197 23:09:32.748656 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4198 23:09:32.751900 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4199 23:09:32.755510 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4200 23:09:32.761730 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4201 23:09:32.765281 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4202 23:09:32.768812 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4203 23:09:32.775438 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4204 23:09:32.778936 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4205 23:09:32.781725 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4206 23:09:32.784764 Total UI for P1: 0, mck2ui 16
4207 23:09:32.788190 best dqsien dly found for B0: ( 0, 13, 12)
4208 23:09:32.791600 Total UI for P1: 0, mck2ui 16
4209 23:09:32.795446 best dqsien dly found for B1: ( 0, 13, 12)
4210 23:09:32.798486 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4211 23:09:32.801694 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4212 23:09:32.802210
4213 23:09:32.808353 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4214 23:09:32.811986 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4215 23:09:32.814622 [Gating] SW calibration Done
4216 23:09:32.815038 ==
4217 23:09:32.818269 Dram Type= 6, Freq= 0, CH_0, rank 1
4218 23:09:32.821687 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4219 23:09:32.822275 ==
4220 23:09:32.822632 RX Vref Scan: 0
4221 23:09:32.822944
4222 23:09:32.824830 RX Vref 0 -> 0, step: 1
4223 23:09:32.825244
4224 23:09:32.828654 RX Delay -230 -> 252, step: 16
4225 23:09:32.831678 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4226 23:09:32.835060 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4227 23:09:32.841625 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4228 23:09:32.844439 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4229 23:09:32.848484 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4230 23:09:32.851505 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4231 23:09:32.858224 iDelay=218, Bit 6, Center 73 (-70 ~ 217) 288
4232 23:09:32.861320 iDelay=218, Bit 7, Center 73 (-70 ~ 217) 288
4233 23:09:32.864906 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4234 23:09:32.868626 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4235 23:09:32.871577 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4236 23:09:32.878206 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4237 23:09:32.881678 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4238 23:09:32.884762 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4239 23:09:32.888289 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4240 23:09:32.894851 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4241 23:09:32.895361 ==
4242 23:09:32.898194 Dram Type= 6, Freq= 0, CH_0, rank 1
4243 23:09:32.901436 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4244 23:09:32.901946 ==
4245 23:09:32.902276 DQS Delay:
4246 23:09:32.904743 DQS0 = 0, DQS1 = 0
4247 23:09:32.905245 DQM Delay:
4248 23:09:32.908462 DQM0 = 52, DQM1 = 42
4249 23:09:32.908969 DQ Delay:
4250 23:09:32.911152 DQ0 =41, DQ1 =49, DQ2 =41, DQ3 =41
4251 23:09:32.914555 DQ4 =57, DQ5 =41, DQ6 =73, DQ7 =73
4252 23:09:32.917780 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =33
4253 23:09:32.920910 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4254 23:09:32.921375
4255 23:09:32.921812
4256 23:09:32.922341 ==
4257 23:09:32.924454 Dram Type= 6, Freq= 0, CH_0, rank 1
4258 23:09:32.928309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4259 23:09:32.928820 ==
4260 23:09:32.930886
4261 23:09:32.931296
4262 23:09:32.931620 TX Vref Scan disable
4263 23:09:32.934486 == TX Byte 0 ==
4264 23:09:32.937768 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4265 23:09:32.941104 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4266 23:09:32.944148 == TX Byte 1 ==
4267 23:09:32.947947 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4268 23:09:32.951051 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4269 23:09:32.951564 ==
4270 23:09:32.954989 Dram Type= 6, Freq= 0, CH_0, rank 1
4271 23:09:32.961733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4272 23:09:32.962248 ==
4273 23:09:32.962592
4274 23:09:32.962899
4275 23:09:32.963190 TX Vref Scan disable
4276 23:09:32.965963 == TX Byte 0 ==
4277 23:09:32.968879 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4278 23:09:32.975418 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4279 23:09:32.975924 == TX Byte 1 ==
4280 23:09:32.978792 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4281 23:09:32.985539 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4282 23:09:32.986102
4283 23:09:32.986436 [DATLAT]
4284 23:09:32.986737 Freq=600, CH0 RK1
4285 23:09:32.987028
4286 23:09:32.989247 DATLAT Default: 0x9
4287 23:09:32.989820 0, 0xFFFF, sum = 0
4288 23:09:32.992130 1, 0xFFFF, sum = 0
4289 23:09:32.992548 2, 0xFFFF, sum = 0
4290 23:09:32.995820 3, 0xFFFF, sum = 0
4291 23:09:32.996331 4, 0xFFFF, sum = 0
4292 23:09:32.998867 5, 0xFFFF, sum = 0
4293 23:09:33.002455 6, 0xFFFF, sum = 0
4294 23:09:33.002967 7, 0xFFFF, sum = 0
4295 23:09:33.003302 8, 0x0, sum = 1
4296 23:09:33.005710 9, 0x0, sum = 2
4297 23:09:33.006127 10, 0x0, sum = 3
4298 23:09:33.008385 11, 0x0, sum = 4
4299 23:09:33.008798 best_step = 9
4300 23:09:33.009120
4301 23:09:33.009421 ==
4302 23:09:33.011758 Dram Type= 6, Freq= 0, CH_0, rank 1
4303 23:09:33.018628 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4304 23:09:33.019040 ==
4305 23:09:33.019360 RX Vref Scan: 0
4306 23:09:33.019656
4307 23:09:33.022202 RX Vref 0 -> 0, step: 1
4308 23:09:33.022602
4309 23:09:33.025265 RX Delay -163 -> 252, step: 8
4310 23:09:33.028851 iDelay=197, Bit 0, Center 52 (-91 ~ 196) 288
4311 23:09:33.035336 iDelay=197, Bit 1, Center 56 (-83 ~ 196) 280
4312 23:09:33.038574 iDelay=197, Bit 2, Center 52 (-91 ~ 196) 288
4313 23:09:33.041693 iDelay=197, Bit 3, Center 52 (-91 ~ 196) 288
4314 23:09:33.045659 iDelay=197, Bit 4, Center 56 (-83 ~ 196) 280
4315 23:09:33.048737 iDelay=197, Bit 5, Center 44 (-99 ~ 188) 288
4316 23:09:33.055078 iDelay=197, Bit 6, Center 60 (-75 ~ 196) 272
4317 23:09:33.058484 iDelay=197, Bit 7, Center 60 (-75 ~ 196) 272
4318 23:09:33.061716 iDelay=197, Bit 8, Center 36 (-107 ~ 180) 288
4319 23:09:33.065210 iDelay=197, Bit 9, Center 32 (-107 ~ 172) 280
4320 23:09:33.068417 iDelay=197, Bit 10, Center 48 (-91 ~ 188) 280
4321 23:09:33.075333 iDelay=197, Bit 11, Center 40 (-99 ~ 180) 280
4322 23:09:33.078379 iDelay=197, Bit 12, Center 48 (-91 ~ 188) 280
4323 23:09:33.081686 iDelay=197, Bit 13, Center 48 (-91 ~ 188) 280
4324 23:09:33.085154 iDelay=197, Bit 14, Center 56 (-83 ~ 196) 280
4325 23:09:33.088789 iDelay=197, Bit 15, Center 52 (-91 ~ 196) 288
4326 23:09:33.092347 ==
4327 23:09:33.095040 Dram Type= 6, Freq= 0, CH_0, rank 1
4328 23:09:33.098973 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4329 23:09:33.099482 ==
4330 23:09:33.099802 DQS Delay:
4331 23:09:33.102155 DQS0 = 0, DQS1 = 0
4332 23:09:33.102680 DQM Delay:
4333 23:09:33.105315 DQM0 = 54, DQM1 = 45
4334 23:09:33.105885 DQ Delay:
4335 23:09:33.108426 DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =52
4336 23:09:33.111871 DQ4 =56, DQ5 =44, DQ6 =60, DQ7 =60
4337 23:09:33.115218 DQ8 =36, DQ9 =32, DQ10 =48, DQ11 =40
4338 23:09:33.118564 DQ12 =48, DQ13 =48, DQ14 =56, DQ15 =52
4339 23:09:33.119013
4340 23:09:33.119346
4341 23:09:33.124857 [DQSOSCAuto] RK1, (LSB)MR18= 0x6526, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 390 ps
4342 23:09:33.128481 CH0 RK1: MR19=808, MR18=6526
4343 23:09:33.135086 CH0_RK1: MR19=0x808, MR18=0x6526, DQSOSC=390, MR23=63, INC=172, DEC=114
4344 23:09:33.138581 [RxdqsGatingPostProcess] freq 600
4345 23:09:33.145116 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4346 23:09:33.145804 Pre-setting of DQS Precalculation
4347 23:09:33.151573 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4348 23:09:33.152032 ==
4349 23:09:33.155001 Dram Type= 6, Freq= 0, CH_1, rank 0
4350 23:09:33.157976 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4351 23:09:33.158442 ==
4352 23:09:33.164260 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4353 23:09:33.171439 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4354 23:09:33.174657 [CA 0] Center 36 (6~67) winsize 62
4355 23:09:33.178158 [CA 1] Center 36 (6~67) winsize 62
4356 23:09:33.181514 [CA 2] Center 35 (4~66) winsize 63
4357 23:09:33.184651 [CA 3] Center 34 (4~65) winsize 62
4358 23:09:33.187664 [CA 4] Center 34 (4~65) winsize 62
4359 23:09:33.191093 [CA 5] Center 34 (4~65) winsize 62
4360 23:09:33.191562
4361 23:09:33.194671 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4362 23:09:33.195374
4363 23:09:33.197705 [CATrainingPosCal] consider 1 rank data
4364 23:09:33.201061 u2DelayCellTimex100 = 270/100 ps
4365 23:09:33.204951 CA0 delay=36 (6~67),Diff = 2 PI (19 cell)
4366 23:09:33.207769 CA1 delay=36 (6~67),Diff = 2 PI (19 cell)
4367 23:09:33.211273 CA2 delay=35 (4~66),Diff = 1 PI (9 cell)
4368 23:09:33.214360 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4369 23:09:33.217859 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4370 23:09:33.221531 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4371 23:09:33.222005
4372 23:09:33.227960 CA PerBit enable=1, Macro0, CA PI delay=34
4373 23:09:33.228426
4374 23:09:33.228794 [CBTSetCACLKResult] CA Dly = 34
4375 23:09:33.231248 CS Dly: 5 (0~36)
4376 23:09:33.231705 ==
4377 23:09:33.234816 Dram Type= 6, Freq= 0, CH_1, rank 1
4378 23:09:33.237783 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4379 23:09:33.238250 ==
4380 23:09:33.244336 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4381 23:09:33.251605 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4382 23:09:33.254510 [CA 0] Center 36 (5~67) winsize 63
4383 23:09:33.257967 [CA 1] Center 36 (5~67) winsize 63
4384 23:09:33.261015 [CA 2] Center 35 (4~66) winsize 63
4385 23:09:33.264890 [CA 3] Center 34 (4~65) winsize 62
4386 23:09:33.268037 [CA 4] Center 34 (4~65) winsize 62
4387 23:09:33.271033 [CA 5] Center 34 (3~65) winsize 63
4388 23:09:33.271450
4389 23:09:33.274299 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4390 23:09:33.274718
4391 23:09:33.277967 [CATrainingPosCal] consider 2 rank data
4392 23:09:33.280960 u2DelayCellTimex100 = 270/100 ps
4393 23:09:33.284339 CA0 delay=36 (6~67),Diff = 2 PI (19 cell)
4394 23:09:33.287948 CA1 delay=36 (6~67),Diff = 2 PI (19 cell)
4395 23:09:33.291099 CA2 delay=35 (4~66),Diff = 1 PI (9 cell)
4396 23:09:33.294313 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4397 23:09:33.297849 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4398 23:09:33.304147 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4399 23:09:33.304569
4400 23:09:33.307138 CA PerBit enable=1, Macro0, CA PI delay=34
4401 23:09:33.307582
4402 23:09:33.310566 [CBTSetCACLKResult] CA Dly = 34
4403 23:09:33.310986 CS Dly: 5 (0~37)
4404 23:09:33.311318
4405 23:09:33.313863 ----->DramcWriteLeveling(PI) begin...
4406 23:09:33.314526 ==
4407 23:09:33.317523 Dram Type= 6, Freq= 0, CH_1, rank 0
4408 23:09:33.320664 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4409 23:09:33.324222 ==
4410 23:09:33.324641 Write leveling (Byte 0): 31 => 31
4411 23:09:33.327472 Write leveling (Byte 1): 31 => 31
4412 23:09:33.330915 DramcWriteLeveling(PI) end<-----
4413 23:09:33.331376
4414 23:09:33.331700 ==
4415 23:09:33.333835 Dram Type= 6, Freq= 0, CH_1, rank 0
4416 23:09:33.340824 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4417 23:09:33.341291 ==
4418 23:09:33.343757 [Gating] SW mode calibration
4419 23:09:33.350651 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4420 23:09:33.354298 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4421 23:09:33.360463 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4422 23:09:33.364007 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4423 23:09:33.367451 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4424 23:09:33.374248 0 9 12 | B1->B0 | 2f2f 2c2c | 0 0 | (1 1) (0 1)
4425 23:09:33.376999 0 9 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4426 23:09:33.380879 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4427 23:09:33.383771 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4428 23:09:33.390513 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4429 23:09:33.393465 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4430 23:09:33.397062 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4431 23:09:33.403561 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4432 23:09:33.407303 0 10 12 | B1->B0 | 3939 3b3b | 0 0 | (0 0) (0 0)
4433 23:09:33.410082 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4434 23:09:33.416810 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4435 23:09:33.420319 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4436 23:09:33.423464 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4437 23:09:33.430105 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4438 23:09:33.433351 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4439 23:09:33.437069 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4440 23:09:33.443203 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4441 23:09:33.446860 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4442 23:09:33.450064 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4443 23:09:33.456954 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4444 23:09:33.460199 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4445 23:09:33.463092 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4446 23:09:33.470174 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4447 23:09:33.473196 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4448 23:09:33.476786 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4449 23:09:33.483343 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4450 23:09:33.486155 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4451 23:09:33.489742 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4452 23:09:33.496205 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4453 23:09:33.500085 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4454 23:09:33.503008 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4455 23:09:33.509454 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4456 23:09:33.513055 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4457 23:09:33.516491 Total UI for P1: 0, mck2ui 16
4458 23:09:33.519559 best dqsien dly found for B0: ( 0, 13, 10)
4459 23:09:33.523128 Total UI for P1: 0, mck2ui 16
4460 23:09:33.526580 best dqsien dly found for B1: ( 0, 13, 10)
4461 23:09:33.529949 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4462 23:09:33.533232 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4463 23:09:33.533698
4464 23:09:33.536808 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4465 23:09:33.539734 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4466 23:09:33.543558 [Gating] SW calibration Done
4467 23:09:33.544073 ==
4468 23:09:33.546319 Dram Type= 6, Freq= 0, CH_1, rank 0
4469 23:09:33.550250 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4470 23:09:33.550787 ==
4471 23:09:33.553038 RX Vref Scan: 0
4472 23:09:33.553441
4473 23:09:33.556443 RX Vref 0 -> 0, step: 1
4474 23:09:33.556857
4475 23:09:33.559786 RX Delay -230 -> 252, step: 16
4476 23:09:33.563270 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4477 23:09:33.566278 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4478 23:09:33.569334 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4479 23:09:33.573019 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4480 23:09:33.579780 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4481 23:09:33.583048 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4482 23:09:33.585885 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4483 23:09:33.589509 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4484 23:09:33.596200 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4485 23:09:33.599960 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4486 23:09:33.602585 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4487 23:09:33.606163 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4488 23:09:33.613053 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4489 23:09:33.616022 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4490 23:09:33.619631 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4491 23:09:33.623246 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4492 23:09:33.623776 ==
4493 23:09:33.626099 Dram Type= 6, Freq= 0, CH_1, rank 0
4494 23:09:33.632515 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4495 23:09:33.632929 ==
4496 23:09:33.633256 DQS Delay:
4497 23:09:33.633556 DQS0 = 0, DQS1 = 0
4498 23:09:33.636087 DQM Delay:
4499 23:09:33.636607 DQM0 = 50, DQM1 = 46
4500 23:09:33.639235 DQ Delay:
4501 23:09:33.643060 DQ0 =57, DQ1 =41, DQ2 =41, DQ3 =49
4502 23:09:33.646282 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4503 23:09:33.646693 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4504 23:09:33.649775 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4505 23:09:33.652949
4506 23:09:33.653492
4507 23:09:33.653892 ==
4508 23:09:33.656449 Dram Type= 6, Freq= 0, CH_1, rank 0
4509 23:09:33.659516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4510 23:09:33.660040 ==
4511 23:09:33.660371
4512 23:09:33.660668
4513 23:09:33.663105 TX Vref Scan disable
4514 23:09:33.663625 == TX Byte 0 ==
4515 23:09:33.669641 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4516 23:09:33.673074 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4517 23:09:33.673487 == TX Byte 1 ==
4518 23:09:33.679761 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4519 23:09:33.682956 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4520 23:09:33.683374 ==
4521 23:09:33.686073 Dram Type= 6, Freq= 0, CH_1, rank 0
4522 23:09:33.689633 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4523 23:09:33.690161 ==
4524 23:09:33.690493
4525 23:09:33.690794
4526 23:09:33.692836 TX Vref Scan disable
4527 23:09:33.696489 == TX Byte 0 ==
4528 23:09:33.699314 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4529 23:09:33.702800 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4530 23:09:33.705903 == TX Byte 1 ==
4531 23:09:33.709269 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4532 23:09:33.712686 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4533 23:09:33.713146
4534 23:09:33.716039 [DATLAT]
4535 23:09:33.716555 Freq=600, CH1 RK0
4536 23:09:33.716892
4537 23:09:33.719209 DATLAT Default: 0x9
4538 23:09:33.719617 0, 0xFFFF, sum = 0
4539 23:09:33.722516 1, 0xFFFF, sum = 0
4540 23:09:33.723048 2, 0xFFFF, sum = 0
4541 23:09:33.725703 3, 0xFFFF, sum = 0
4542 23:09:33.726118 4, 0xFFFF, sum = 0
4543 23:09:33.729406 5, 0xFFFF, sum = 0
4544 23:09:33.729989 6, 0xFFFF, sum = 0
4545 23:09:33.732896 7, 0xFFFF, sum = 0
4546 23:09:33.733424 8, 0x0, sum = 1
4547 23:09:33.736003 9, 0x0, sum = 2
4548 23:09:33.736533 10, 0x0, sum = 3
4549 23:09:33.738888 11, 0x0, sum = 4
4550 23:09:33.739306 best_step = 9
4551 23:09:33.739632
4552 23:09:33.739929 ==
4553 23:09:33.742611 Dram Type= 6, Freq= 0, CH_1, rank 0
4554 23:09:33.748971 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4555 23:09:33.749508 ==
4556 23:09:33.749881 RX Vref Scan: 1
4557 23:09:33.750189
4558 23:09:33.752722 RX Vref 0 -> 0, step: 1
4559 23:09:33.753243
4560 23:09:33.755507 RX Delay -163 -> 252, step: 8
4561 23:09:33.755921
4562 23:09:33.759237 Set Vref, RX VrefLevel [Byte0]: 53
4563 23:09:33.762150 [Byte1]: 47
4564 23:09:33.762669
4565 23:09:33.765469 Final RX Vref Byte 0 = 53 to rank0
4566 23:09:33.769413 Final RX Vref Byte 1 = 47 to rank0
4567 23:09:33.772226 Final RX Vref Byte 0 = 53 to rank1
4568 23:09:33.775447 Final RX Vref Byte 1 = 47 to rank1==
4569 23:09:33.778919 Dram Type= 6, Freq= 0, CH_1, rank 0
4570 23:09:33.782251 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4571 23:09:33.782772 ==
4572 23:09:33.785277 DQS Delay:
4573 23:09:33.785848 DQS0 = 0, DQS1 = 0
4574 23:09:33.786190 DQM Delay:
4575 23:09:33.788782 DQM0 = 48, DQM1 = 45
4576 23:09:33.789316 DQ Delay:
4577 23:09:33.792413 DQ0 =52, DQ1 =40, DQ2 =36, DQ3 =44
4578 23:09:33.795262 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4579 23:09:33.798883 DQ8 =32, DQ9 =36, DQ10 =44, DQ11 =36
4580 23:09:33.802162 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =56
4581 23:09:33.802696
4582 23:09:33.803026
4583 23:09:33.812367 [DQSOSCAuto] RK0, (LSB)MR18= 0x486e, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
4584 23:09:33.814913 CH1 RK0: MR19=808, MR18=486E
4585 23:09:33.818698 CH1_RK0: MR19=0x808, MR18=0x486E, DQSOSC=389, MR23=63, INC=173, DEC=115
4586 23:09:33.821671
4587 23:09:33.824990 ----->DramcWriteLeveling(PI) begin...
4588 23:09:33.825429 ==
4589 23:09:33.828526 Dram Type= 6, Freq= 0, CH_1, rank 1
4590 23:09:33.831573 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4591 23:09:33.832007 ==
4592 23:09:33.834769 Write leveling (Byte 0): 30 => 30
4593 23:09:33.838407 Write leveling (Byte 1): 31 => 31
4594 23:09:33.841552 DramcWriteLeveling(PI) end<-----
4595 23:09:33.842018
4596 23:09:33.842456 ==
4597 23:09:33.844796 Dram Type= 6, Freq= 0, CH_1, rank 1
4598 23:09:33.848195 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4599 23:09:33.848630 ==
4600 23:09:33.851150 [Gating] SW mode calibration
4601 23:09:33.857885 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4602 23:09:33.864632 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4603 23:09:33.868300 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4604 23:09:33.871120 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4605 23:09:33.877494 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4606 23:09:33.881288 0 9 12 | B1->B0 | 2d2d 2f2f | 0 1 | (0 1) (1 0)
4607 23:09:33.884847 0 9 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4608 23:09:33.891435 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4609 23:09:33.894428 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4610 23:09:33.897402 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4611 23:09:33.904285 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4612 23:09:33.907493 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4613 23:09:33.910970 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4614 23:09:33.917480 0 10 12 | B1->B0 | 3939 3131 | 0 0 | (0 0) (0 0)
4615 23:09:33.921022 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4616 23:09:33.924112 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4617 23:09:33.930796 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4618 23:09:33.933727 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4619 23:09:33.937220 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4620 23:09:33.943629 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4621 23:09:33.947345 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4622 23:09:33.950472 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4623 23:09:33.957141 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4624 23:09:33.960447 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4625 23:09:33.963349 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4626 23:09:33.966988 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4627 23:09:33.973477 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4628 23:09:33.976836 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4629 23:09:33.980507 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4630 23:09:33.986940 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4631 23:09:33.990275 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4632 23:09:33.993359 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4633 23:09:33.999905 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4634 23:09:34.003506 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4635 23:09:34.006484 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4636 23:09:34.013202 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4637 23:09:34.016650 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4638 23:09:34.020175 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4639 23:09:34.026732 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4640 23:09:34.030144 Total UI for P1: 0, mck2ui 16
4641 23:09:34.033264 best dqsien dly found for B0: ( 0, 13, 12)
4642 23:09:34.033349 Total UI for P1: 0, mck2ui 16
4643 23:09:34.040054 best dqsien dly found for B1: ( 0, 13, 12)
4644 23:09:34.043288 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4645 23:09:34.046852 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4646 23:09:34.046935
4647 23:09:34.049964 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4648 23:09:34.053556 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4649 23:09:34.056554 [Gating] SW calibration Done
4650 23:09:34.056636 ==
4651 23:09:34.060083 Dram Type= 6, Freq= 0, CH_1, rank 1
4652 23:09:34.062975 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4653 23:09:34.063065 ==
4654 23:09:34.066670 RX Vref Scan: 0
4655 23:09:34.067161
4656 23:09:34.067596 RX Vref 0 -> 0, step: 1
4657 23:09:34.070191
4658 23:09:34.070646 RX Delay -230 -> 252, step: 16
4659 23:09:34.076962 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4660 23:09:34.080164 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4661 23:09:34.083345 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4662 23:09:34.086419 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4663 23:09:34.090107 iDelay=218, Bit 4, Center 57 (-86 ~ 201) 288
4664 23:09:34.096697 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4665 23:09:34.099740 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4666 23:09:34.103345 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4667 23:09:34.106870 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4668 23:09:34.110070 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4669 23:09:34.116574 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4670 23:09:34.120565 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4671 23:09:34.123362 iDelay=218, Bit 12, Center 65 (-86 ~ 217) 304
4672 23:09:34.126875 iDelay=218, Bit 13, Center 57 (-86 ~ 201) 288
4673 23:09:34.133326 iDelay=218, Bit 14, Center 57 (-86 ~ 201) 288
4674 23:09:34.136718 iDelay=218, Bit 15, Center 65 (-86 ~ 217) 304
4675 23:09:34.137230 ==
4676 23:09:34.139996 Dram Type= 6, Freq= 0, CH_1, rank 1
4677 23:09:34.142962 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4678 23:09:34.143381 ==
4679 23:09:34.146383 DQS Delay:
4680 23:09:34.146794 DQS0 = 0, DQS1 = 0
4681 23:09:34.147140 DQM Delay:
4682 23:09:34.149904 DQM0 = 53, DQM1 = 49
4683 23:09:34.150333 DQ Delay:
4684 23:09:34.153120 DQ0 =57, DQ1 =49, DQ2 =33, DQ3 =49
4685 23:09:34.156818 DQ4 =57, DQ5 =65, DQ6 =65, DQ7 =49
4686 23:09:34.159876 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =41
4687 23:09:34.163124 DQ12 =65, DQ13 =57, DQ14 =57, DQ15 =65
4688 23:09:34.163561
4689 23:09:34.163887
4690 23:09:34.164191 ==
4691 23:09:34.166630 Dram Type= 6, Freq= 0, CH_1, rank 1
4692 23:09:34.172997 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4693 23:09:34.173412 ==
4694 23:09:34.173787
4695 23:09:34.174092
4696 23:09:34.174386 TX Vref Scan disable
4697 23:09:34.177046 == TX Byte 0 ==
4698 23:09:34.180484 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4699 23:09:34.187120 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4700 23:09:34.187637 == TX Byte 1 ==
4701 23:09:34.190306 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4702 23:09:34.196328 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4703 23:09:34.196882 ==
4704 23:09:34.200054 Dram Type= 6, Freq= 0, CH_1, rank 1
4705 23:09:34.203086 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4706 23:09:34.203513 ==
4707 23:09:34.203843
4708 23:09:34.204144
4709 23:09:34.206899 TX Vref Scan disable
4710 23:09:34.207338 == TX Byte 0 ==
4711 23:09:34.213494 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4712 23:09:34.216777 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4713 23:09:34.217201 == TX Byte 1 ==
4714 23:09:34.223175 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4715 23:09:34.226305 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4716 23:09:34.226733
4717 23:09:34.227110 [DATLAT]
4718 23:09:34.230123 Freq=600, CH1 RK1
4719 23:09:34.230537
4720 23:09:34.230861 DATLAT Default: 0x9
4721 23:09:34.233052 0, 0xFFFF, sum = 0
4722 23:09:34.233472 1, 0xFFFF, sum = 0
4723 23:09:34.236720 2, 0xFFFF, sum = 0
4724 23:09:34.237268 3, 0xFFFF, sum = 0
4725 23:09:34.240183 4, 0xFFFF, sum = 0
4726 23:09:34.243083 5, 0xFFFF, sum = 0
4727 23:09:34.243681 6, 0xFFFF, sum = 0
4728 23:09:34.246238 7, 0xFFFF, sum = 0
4729 23:09:34.246666 8, 0x0, sum = 1
4730 23:09:34.247003 9, 0x0, sum = 2
4731 23:09:34.249703 10, 0x0, sum = 3
4732 23:09:34.250127 11, 0x0, sum = 4
4733 23:09:34.253318 best_step = 9
4734 23:09:34.253778
4735 23:09:34.254114 ==
4736 23:09:34.256644 Dram Type= 6, Freq= 0, CH_1, rank 1
4737 23:09:34.259788 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4738 23:09:34.260206 ==
4739 23:09:34.263351 RX Vref Scan: 0
4740 23:09:34.263781
4741 23:09:34.264113 RX Vref 0 -> 0, step: 1
4742 23:09:34.264419
4743 23:09:34.266447 RX Delay -163 -> 252, step: 8
4744 23:09:34.273568 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4745 23:09:34.276847 iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288
4746 23:09:34.280053 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4747 23:09:34.283466 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4748 23:09:34.290093 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4749 23:09:34.293191 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4750 23:09:34.296677 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4751 23:09:34.300242 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4752 23:09:34.303148 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4753 23:09:34.310344 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4754 23:09:34.313212 iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296
4755 23:09:34.316774 iDelay=205, Bit 11, Center 36 (-107 ~ 180) 288
4756 23:09:34.320184 iDelay=205, Bit 12, Center 56 (-91 ~ 204) 296
4757 23:09:34.323256 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4758 23:09:34.329996 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4759 23:09:34.333471 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4760 23:09:34.334083 ==
4761 23:09:34.336529 Dram Type= 6, Freq= 0, CH_1, rank 1
4762 23:09:34.340032 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4763 23:09:34.340486 ==
4764 23:09:34.343034 DQS Delay:
4765 23:09:34.343593 DQS0 = 0, DQS1 = 0
4766 23:09:34.343947 DQM Delay:
4767 23:09:34.346445 DQM0 = 49, DQM1 = 44
4768 23:09:34.346864 DQ Delay:
4769 23:09:34.350058 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4770 23:09:34.352973 DQ4 =48, DQ5 =60, DQ6 =60, DQ7 =48
4771 23:09:34.356837 DQ8 =32, DQ9 =32, DQ10 =48, DQ11 =36
4772 23:09:34.359673 DQ12 =56, DQ13 =52, DQ14 =48, DQ15 =52
4773 23:09:34.360086
4774 23:09:34.360409
4775 23:09:34.369681 [DQSOSCAuto] RK1, (LSB)MR18= 0x671f, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 390 ps
4776 23:09:34.370157 CH1 RK1: MR19=808, MR18=671F
4777 23:09:34.376919 CH1_RK1: MR19=0x808, MR18=0x671F, DQSOSC=390, MR23=63, INC=172, DEC=114
4778 23:09:34.379798 [RxdqsGatingPostProcess] freq 600
4779 23:09:34.386557 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4780 23:09:34.389873 Pre-setting of DQS Precalculation
4781 23:09:34.392792 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4782 23:09:34.399827 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4783 23:09:34.409736 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4784 23:09:34.410194
4785 23:09:34.410522
4786 23:09:34.412854 [Calibration Summary] 1200 Mbps
4787 23:09:34.413268 CH 0, Rank 0
4788 23:09:34.416262 SW Impedance : PASS
4789 23:09:34.416756 DUTY Scan : NO K
4790 23:09:34.419444 ZQ Calibration : PASS
4791 23:09:34.422782 Jitter Meter : NO K
4792 23:09:34.423196 CBT Training : PASS
4793 23:09:34.426356 Write leveling : PASS
4794 23:09:34.429441 RX DQS gating : PASS
4795 23:09:34.429890 RX DQ/DQS(RDDQC) : PASS
4796 23:09:34.432978 TX DQ/DQS : PASS
4797 23:09:34.433398 RX DATLAT : PASS
4798 23:09:34.436451 RX DQ/DQS(Engine): PASS
4799 23:09:34.439194 TX OE : NO K
4800 23:09:34.439611 All Pass.
4801 23:09:34.439942
4802 23:09:34.440246 CH 0, Rank 1
4803 23:09:34.442607 SW Impedance : PASS
4804 23:09:34.446151 DUTY Scan : NO K
4805 23:09:34.446637 ZQ Calibration : PASS
4806 23:09:34.449161 Jitter Meter : NO K
4807 23:09:34.452493 CBT Training : PASS
4808 23:09:34.452907 Write leveling : PASS
4809 23:09:34.456231 RX DQS gating : PASS
4810 23:09:34.459181 RX DQ/DQS(RDDQC) : PASS
4811 23:09:34.459635 TX DQ/DQS : PASS
4812 23:09:34.462343 RX DATLAT : PASS
4813 23:09:34.465847 RX DQ/DQS(Engine): PASS
4814 23:09:34.466263 TX OE : NO K
4815 23:09:34.469086 All Pass.
4816 23:09:34.469651
4817 23:09:34.470069 CH 1, Rank 0
4818 23:09:34.472761 SW Impedance : PASS
4819 23:09:34.473192 DUTY Scan : NO K
4820 23:09:34.475823 ZQ Calibration : PASS
4821 23:09:34.479056 Jitter Meter : NO K
4822 23:09:34.479472 CBT Training : PASS
4823 23:09:34.482955 Write leveling : PASS
4824 23:09:34.483368 RX DQS gating : PASS
4825 23:09:34.486046 RX DQ/DQS(RDDQC) : PASS
4826 23:09:34.489051 TX DQ/DQS : PASS
4827 23:09:34.489471 RX DATLAT : PASS
4828 23:09:34.492318 RX DQ/DQS(Engine): PASS
4829 23:09:34.495822 TX OE : NO K
4830 23:09:34.496239 All Pass.
4831 23:09:34.496570
4832 23:09:34.496878 CH 1, Rank 1
4833 23:09:34.498821 SW Impedance : PASS
4834 23:09:34.502375 DUTY Scan : NO K
4835 23:09:34.502790 ZQ Calibration : PASS
4836 23:09:34.505331 Jitter Meter : NO K
4837 23:09:34.508969 CBT Training : PASS
4838 23:09:34.509399 Write leveling : PASS
4839 23:09:34.512296 RX DQS gating : PASS
4840 23:09:34.515804 RX DQ/DQS(RDDQC) : PASS
4841 23:09:34.516230 TX DQ/DQS : PASS
4842 23:09:34.518809 RX DATLAT : PASS
4843 23:09:34.522504 RX DQ/DQS(Engine): PASS
4844 23:09:34.522924 TX OE : NO K
4845 23:09:34.525379 All Pass.
4846 23:09:34.525847
4847 23:09:34.526211 DramC Write-DBI off
4848 23:09:34.529026 PER_BANK_REFRESH: Hybrid Mode
4849 23:09:34.529452 TX_TRACKING: ON
4850 23:09:34.538578 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4851 23:09:34.542092 [FAST_K] Save calibration result to emmc
4852 23:09:34.545647 dramc_set_vcore_voltage set vcore to 662500
4853 23:09:34.548467 Read voltage for 933, 3
4854 23:09:34.548882 Vio18 = 0
4855 23:09:34.551935 Vcore = 662500
4856 23:09:34.552353 Vdram = 0
4857 23:09:34.552682 Vddq = 0
4858 23:09:34.552988 Vmddr = 0
4859 23:09:34.558879 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4860 23:09:34.565214 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4861 23:09:34.565661 MEM_TYPE=3, freq_sel=17
4862 23:09:34.568840 sv_algorithm_assistance_LP4_1600
4863 23:09:34.572032 ============ PULL DRAM RESETB DOWN ============
4864 23:09:34.578793 ========== PULL DRAM RESETB DOWN end =========
4865 23:09:34.581725 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4866 23:09:34.585416 ===================================
4867 23:09:34.588863 LPDDR4 DRAM CONFIGURATION
4868 23:09:34.591654 ===================================
4869 23:09:34.592177 EX_ROW_EN[0] = 0x0
4870 23:09:34.595285 EX_ROW_EN[1] = 0x0
4871 23:09:34.595774 LP4Y_EN = 0x0
4872 23:09:34.598370 WORK_FSP = 0x0
4873 23:09:34.601848 WL = 0x3
4874 23:09:34.602310 RL = 0x3
4875 23:09:34.605129 BL = 0x2
4876 23:09:34.605636 RPST = 0x0
4877 23:09:34.608718 RD_PRE = 0x0
4878 23:09:34.609216 WR_PRE = 0x1
4879 23:09:34.611684 WR_PST = 0x0
4880 23:09:34.612261 DBI_WR = 0x0
4881 23:09:34.615151 DBI_RD = 0x0
4882 23:09:34.615728 OTF = 0x1
4883 23:09:34.618461 ===================================
4884 23:09:34.621874 ===================================
4885 23:09:34.624853 ANA top config
4886 23:09:34.628517 ===================================
4887 23:09:34.628993 DLL_ASYNC_EN = 0
4888 23:09:34.631913 ALL_SLAVE_EN = 1
4889 23:09:34.634939 NEW_RANK_MODE = 1
4890 23:09:34.638449 DLL_IDLE_MODE = 1
4891 23:09:34.638936 LP45_APHY_COMB_EN = 1
4892 23:09:34.641520 TX_ODT_DIS = 1
4893 23:09:34.644939 NEW_8X_MODE = 1
4894 23:09:34.648262 ===================================
4895 23:09:34.651340 ===================================
4896 23:09:34.655036 data_rate = 1866
4897 23:09:34.658191 CKR = 1
4898 23:09:34.661798 DQ_P2S_RATIO = 8
4899 23:09:34.664773 ===================================
4900 23:09:34.665188 CA_P2S_RATIO = 8
4901 23:09:34.668461 DQ_CA_OPEN = 0
4902 23:09:34.671391 DQ_SEMI_OPEN = 0
4903 23:09:34.674798 CA_SEMI_OPEN = 0
4904 23:09:34.678122 CA_FULL_RATE = 0
4905 23:09:34.681687 DQ_CKDIV4_EN = 1
4906 23:09:34.682109 CA_CKDIV4_EN = 1
4907 23:09:34.685003 CA_PREDIV_EN = 0
4908 23:09:34.688109 PH8_DLY = 0
4909 23:09:34.691517 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4910 23:09:34.694513 DQ_AAMCK_DIV = 4
4911 23:09:34.698118 CA_AAMCK_DIV = 4
4912 23:09:34.698535 CA_ADMCK_DIV = 4
4913 23:09:34.701555 DQ_TRACK_CA_EN = 0
4914 23:09:34.704125 CA_PICK = 933
4915 23:09:34.708101 CA_MCKIO = 933
4916 23:09:34.711160 MCKIO_SEMI = 0
4917 23:09:34.714508 PLL_FREQ = 3732
4918 23:09:34.717671 DQ_UI_PI_RATIO = 32
4919 23:09:34.718096 CA_UI_PI_RATIO = 0
4920 23:09:34.720964 ===================================
4921 23:09:34.724606 ===================================
4922 23:09:34.727781 memory_type:LPDDR4
4923 23:09:34.731456 GP_NUM : 10
4924 23:09:34.731861 SRAM_EN : 1
4925 23:09:34.734365 MD32_EN : 0
4926 23:09:34.737867 ===================================
4927 23:09:34.741365 [ANA_INIT] >>>>>>>>>>>>>>
4928 23:09:34.744391 <<<<<< [CONFIGURE PHASE]: ANA_TX
4929 23:09:34.747929 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4930 23:09:34.751627 ===================================
4931 23:09:34.752038 data_rate = 1866,PCW = 0X8f00
4932 23:09:34.754593 ===================================
4933 23:09:34.758031 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4934 23:09:34.764396 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4935 23:09:34.771459 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4936 23:09:34.774338 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4937 23:09:34.778014 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4938 23:09:34.780954 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4939 23:09:34.784199 [ANA_INIT] flow start
4940 23:09:34.784605 [ANA_INIT] PLL >>>>>>>>
4941 23:09:34.787716 [ANA_INIT] PLL <<<<<<<<
4942 23:09:34.791508 [ANA_INIT] MIDPI >>>>>>>>
4943 23:09:34.794288 [ANA_INIT] MIDPI <<<<<<<<
4944 23:09:34.794695 [ANA_INIT] DLL >>>>>>>>
4945 23:09:34.797875 [ANA_INIT] flow end
4946 23:09:34.801321 ============ LP4 DIFF to SE enter ============
4947 23:09:34.804388 ============ LP4 DIFF to SE exit ============
4948 23:09:34.807804 [ANA_INIT] <<<<<<<<<<<<<
4949 23:09:34.810942 [Flow] Enable top DCM control >>>>>
4950 23:09:34.814431 [Flow] Enable top DCM control <<<<<
4951 23:09:34.817832 Enable DLL master slave shuffle
4952 23:09:34.824366 ==============================================================
4953 23:09:34.824777 Gating Mode config
4954 23:09:34.830911 ==============================================================
4955 23:09:34.831535 Config description:
4956 23:09:34.841036 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4957 23:09:34.847450 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4958 23:09:34.854056 SELPH_MODE 0: By rank 1: By Phase
4959 23:09:34.857262 ==============================================================
4960 23:09:34.860422 GAT_TRACK_EN = 1
4961 23:09:34.863556 RX_GATING_MODE = 2
4962 23:09:34.867171 RX_GATING_TRACK_MODE = 2
4963 23:09:34.870586 SELPH_MODE = 1
4964 23:09:34.873535 PICG_EARLY_EN = 1
4965 23:09:34.876922 VALID_LAT_VALUE = 1
4966 23:09:34.880042 ==============================================================
4967 23:09:34.883722 Enter into Gating configuration >>>>
4968 23:09:34.887290 Exit from Gating configuration <<<<
4969 23:09:34.890200 Enter into DVFS_PRE_config >>>>>
4970 23:09:34.903206 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4971 23:09:34.906687 Exit from DVFS_PRE_config <<<<<
4972 23:09:34.910091 Enter into PICG configuration >>>>
4973 23:09:34.913619 Exit from PICG configuration <<<<
4974 23:09:34.913699 [RX_INPUT] configuration >>>>>
4975 23:09:34.916570 [RX_INPUT] configuration <<<<<
4976 23:09:34.923099 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4977 23:09:34.926793 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4978 23:09:34.933282 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4979 23:09:34.939995 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4980 23:09:34.946770 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4981 23:09:34.953348 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4982 23:09:34.957144 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4983 23:09:34.960316 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4984 23:09:34.963347 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4985 23:09:34.970073 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4986 23:09:34.973207 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4987 23:09:34.976592 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4988 23:09:34.980254 ===================================
4989 23:09:34.983266 LPDDR4 DRAM CONFIGURATION
4990 23:09:34.986831 ===================================
4991 23:09:34.989794 EX_ROW_EN[0] = 0x0
4992 23:09:34.989872 EX_ROW_EN[1] = 0x0
4993 23:09:34.993337 LP4Y_EN = 0x0
4994 23:09:34.993416 WORK_FSP = 0x0
4995 23:09:34.996328 WL = 0x3
4996 23:09:34.996406 RL = 0x3
4997 23:09:34.999942 BL = 0x2
4998 23:09:35.000021 RPST = 0x0
4999 23:09:35.003239 RD_PRE = 0x0
5000 23:09:35.003317 WR_PRE = 0x1
5001 23:09:35.006744 WR_PST = 0x0
5002 23:09:35.006823 DBI_WR = 0x0
5003 23:09:35.009688 DBI_RD = 0x0
5004 23:09:35.009767 OTF = 0x1
5005 23:09:35.013356 ===================================
5006 23:09:35.020106 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5007 23:09:35.023077 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5008 23:09:35.026641 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5009 23:09:35.029765 ===================================
5010 23:09:35.033408 LPDDR4 DRAM CONFIGURATION
5011 23:09:35.036396 ===================================
5012 23:09:35.036476 EX_ROW_EN[0] = 0x10
5013 23:09:35.039889 EX_ROW_EN[1] = 0x0
5014 23:09:35.043402 LP4Y_EN = 0x0
5015 23:09:35.043481 WORK_FSP = 0x0
5016 23:09:35.046884 WL = 0x3
5017 23:09:35.046963 RL = 0x3
5018 23:09:35.049855 BL = 0x2
5019 23:09:35.049934 RPST = 0x0
5020 23:09:35.053353 RD_PRE = 0x0
5021 23:09:35.053432 WR_PRE = 0x1
5022 23:09:35.056269 WR_PST = 0x0
5023 23:09:35.056349 DBI_WR = 0x0
5024 23:09:35.059567 DBI_RD = 0x0
5025 23:09:35.059646 OTF = 0x1
5026 23:09:35.063045 ===================================
5027 23:09:35.069590 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5028 23:09:35.074218 nWR fixed to 30
5029 23:09:35.077814 [ModeRegInit_LP4] CH0 RK0
5030 23:09:35.077893 [ModeRegInit_LP4] CH0 RK1
5031 23:09:35.080858 [ModeRegInit_LP4] CH1 RK0
5032 23:09:35.083969 [ModeRegInit_LP4] CH1 RK1
5033 23:09:35.084048 match AC timing 9
5034 23:09:35.090671 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5035 23:09:35.094229 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5036 23:09:35.097243 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5037 23:09:35.103997 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5038 23:09:35.107434 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5039 23:09:35.107514 ==
5040 23:09:35.110864 Dram Type= 6, Freq= 0, CH_0, rank 0
5041 23:09:35.114243 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5042 23:09:35.114323 ==
5043 23:09:35.120552 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5044 23:09:35.127227 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5045 23:09:35.130617 [CA 0] Center 37 (6~68) winsize 63
5046 23:09:35.134077 [CA 1] Center 37 (6~68) winsize 63
5047 23:09:35.137747 [CA 2] Center 34 (4~65) winsize 62
5048 23:09:35.140646 [CA 3] Center 33 (3~64) winsize 62
5049 23:09:35.144352 [CA 4] Center 33 (3~64) winsize 62
5050 23:09:35.147113 [CA 5] Center 32 (2~62) winsize 61
5051 23:09:35.147192
5052 23:09:35.150545 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5053 23:09:35.150624
5054 23:09:35.153896 [CATrainingPosCal] consider 1 rank data
5055 23:09:35.157403 u2DelayCellTimex100 = 270/100 ps
5056 23:09:35.160443 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5057 23:09:35.163768 CA1 delay=37 (6~68),Diff = 5 PI (31 cell)
5058 23:09:35.167221 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5059 23:09:35.170816 CA3 delay=33 (3~64),Diff = 1 PI (6 cell)
5060 23:09:35.173839 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5061 23:09:35.177789 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5062 23:09:35.177869
5063 23:09:35.183753 CA PerBit enable=1, Macro0, CA PI delay=32
5064 23:09:35.183833
5065 23:09:35.187070 [CBTSetCACLKResult] CA Dly = 32
5066 23:09:35.187149 CS Dly: 5 (0~36)
5067 23:09:35.187212 ==
5068 23:09:35.190566 Dram Type= 6, Freq= 0, CH_0, rank 1
5069 23:09:35.193738 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5070 23:09:35.193818 ==
5071 23:09:35.200847 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5072 23:09:35.207404 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5073 23:09:35.210461 [CA 0] Center 37 (6~68) winsize 63
5074 23:09:35.213979 [CA 1] Center 37 (6~68) winsize 63
5075 23:09:35.216846 [CA 2] Center 34 (4~65) winsize 62
5076 23:09:35.220474 [CA 3] Center 34 (3~65) winsize 63
5077 23:09:35.224111 [CA 4] Center 32 (2~63) winsize 62
5078 23:09:35.226954 [CA 5] Center 32 (2~62) winsize 61
5079 23:09:35.227034
5080 23:09:35.230531 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5081 23:09:35.230641
5082 23:09:35.234047 [CATrainingPosCal] consider 2 rank data
5083 23:09:35.237439 u2DelayCellTimex100 = 270/100 ps
5084 23:09:35.240715 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5085 23:09:35.244222 CA1 delay=37 (6~68),Diff = 5 PI (31 cell)
5086 23:09:35.247244 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5087 23:09:35.250790 CA3 delay=33 (3~64),Diff = 1 PI (6 cell)
5088 23:09:35.254217 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5089 23:09:35.257249 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5090 23:09:35.260782
5091 23:09:35.264295 CA PerBit enable=1, Macro0, CA PI delay=32
5092 23:09:35.264443
5093 23:09:35.266923 [CBTSetCACLKResult] CA Dly = 32
5094 23:09:35.267071 CS Dly: 5 (0~37)
5095 23:09:35.267189
5096 23:09:35.270423 ----->DramcWriteLeveling(PI) begin...
5097 23:09:35.270595 ==
5098 23:09:35.273722 Dram Type= 6, Freq= 0, CH_0, rank 0
5099 23:09:35.277323 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5100 23:09:35.280904 ==
5101 23:09:35.281137 Write leveling (Byte 0): 32 => 32
5102 23:09:35.284119 Write leveling (Byte 1): 28 => 28
5103 23:09:35.287113 DramcWriteLeveling(PI) end<-----
5104 23:09:35.287401
5105 23:09:35.287631 ==
5106 23:09:35.290669 Dram Type= 6, Freq= 0, CH_0, rank 0
5107 23:09:35.297110 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5108 23:09:35.297519 ==
5109 23:09:35.297874 [Gating] SW mode calibration
5110 23:09:35.307204 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5111 23:09:35.310493 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5112 23:09:35.314108 0 14 0 | B1->B0 | 2b2b 3434 | 1 1 | (1 1) (1 1)
5113 23:09:35.320449 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5114 23:09:35.324171 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5115 23:09:35.330689 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5116 23:09:35.333563 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5117 23:09:35.337162 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5118 23:09:35.340509 0 14 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
5119 23:09:35.347261 0 14 28 | B1->B0 | 3333 2a2a | 1 0 | (1 1) (1 0)
5120 23:09:35.350431 0 15 0 | B1->B0 | 2d2d 2323 | 0 0 | (0 1) (1 0)
5121 23:09:35.356891 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5122 23:09:35.359873 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5123 23:09:35.363460 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5124 23:09:35.366827 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5125 23:09:35.373452 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5126 23:09:35.376619 0 15 24 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5127 23:09:35.379969 0 15 28 | B1->B0 | 2323 3c3c | 0 0 | (0 0) (0 0)
5128 23:09:35.386818 1 0 0 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
5129 23:09:35.390417 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5130 23:09:35.393872 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5131 23:09:35.400555 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5132 23:09:35.403024 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5133 23:09:35.406788 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5134 23:09:35.413363 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5135 23:09:35.416629 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5136 23:09:35.419630 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5137 23:09:35.426586 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5138 23:09:35.429550 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5139 23:09:35.433249 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5140 23:09:35.439816 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5141 23:09:35.443119 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5142 23:09:35.446479 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5143 23:09:35.452871 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5144 23:09:35.456686 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5145 23:09:35.460110 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5146 23:09:35.466442 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5147 23:09:35.469531 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5148 23:09:35.473027 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5149 23:09:35.479645 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5150 23:09:35.483125 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5151 23:09:35.486483 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5152 23:09:35.492940 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5153 23:09:35.493353 Total UI for P1: 0, mck2ui 16
5154 23:09:35.496340 best dqsien dly found for B0: ( 1, 2, 26)
5155 23:09:35.502901 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5156 23:09:35.506282 Total UI for P1: 0, mck2ui 16
5157 23:09:35.509496 best dqsien dly found for B1: ( 1, 3, 0)
5158 23:09:35.513130 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5159 23:09:35.515983 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5160 23:09:35.516391
5161 23:09:35.519485 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5162 23:09:35.523212 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5163 23:09:35.526099 [Gating] SW calibration Done
5164 23:09:35.526510 ==
5165 23:09:35.529760 Dram Type= 6, Freq= 0, CH_0, rank 0
5166 23:09:35.532531 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5167 23:09:35.533074 ==
5168 23:09:35.535901 RX Vref Scan: 0
5169 23:09:35.536564
5170 23:09:35.537044 RX Vref 0 -> 0, step: 1
5171 23:09:35.539141
5172 23:09:35.539621 RX Delay -80 -> 252, step: 8
5173 23:09:35.546091 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5174 23:09:35.549785 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5175 23:09:35.552782 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5176 23:09:35.556272 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5177 23:09:35.559712 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5178 23:09:35.563046 iDelay=208, Bit 5, Center 91 (0 ~ 183) 184
5179 23:09:35.569142 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5180 23:09:35.572801 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5181 23:09:35.575875 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5182 23:09:35.579059 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5183 23:09:35.582860 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5184 23:09:35.585828 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5185 23:09:35.592250 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5186 23:09:35.595930 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5187 23:09:35.598856 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5188 23:09:35.602183 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5189 23:09:35.602406 ==
5190 23:09:35.605886 Dram Type= 6, Freq= 0, CH_0, rank 0
5191 23:09:35.608823 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5192 23:09:35.612480 ==
5193 23:09:35.612789 DQS Delay:
5194 23:09:35.613060 DQS0 = 0, DQS1 = 0
5195 23:09:35.615966 DQM Delay:
5196 23:09:35.616185 DQM0 = 104, DQM1 = 95
5197 23:09:35.619156 DQ Delay:
5198 23:09:35.622029 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5199 23:09:35.625551 DQ4 =107, DQ5 =91, DQ6 =111, DQ7 =115
5200 23:09:35.629119 DQ8 =87, DQ9 =87, DQ10 =95, DQ11 =91
5201 23:09:35.632072 DQ12 =99, DQ13 =103, DQ14 =103, DQ15 =99
5202 23:09:35.632342
5203 23:09:35.632557
5204 23:09:35.632756 ==
5205 23:09:35.635826 Dram Type= 6, Freq= 0, CH_0, rank 0
5206 23:09:35.639791 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5207 23:09:35.640353 ==
5208 23:09:35.640728
5209 23:09:35.641037
5210 23:09:35.642353 TX Vref Scan disable
5211 23:09:35.642764 == TX Byte 0 ==
5212 23:09:35.648920 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5213 23:09:35.652236 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5214 23:09:35.655386 == TX Byte 1 ==
5215 23:09:35.659229 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5216 23:09:35.662561 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5217 23:09:35.662979 ==
5218 23:09:35.665981 Dram Type= 6, Freq= 0, CH_0, rank 0
5219 23:09:35.669045 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5220 23:09:35.669462 ==
5221 23:09:35.672552
5222 23:09:35.672959
5223 23:09:35.673285 TX Vref Scan disable
5224 23:09:35.675509 == TX Byte 0 ==
5225 23:09:35.678984 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5226 23:09:35.685824 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5227 23:09:35.686339 == TX Byte 1 ==
5228 23:09:35.689208 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5229 23:09:35.695841 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5230 23:09:35.696364
5231 23:09:35.696691 [DATLAT]
5232 23:09:35.696991 Freq=933, CH0 RK0
5233 23:09:35.697286
5234 23:09:35.698572 DATLAT Default: 0xd
5235 23:09:35.698982 0, 0xFFFF, sum = 0
5236 23:09:35.702277 1, 0xFFFF, sum = 0
5237 23:09:35.705395 2, 0xFFFF, sum = 0
5238 23:09:35.705978 3, 0xFFFF, sum = 0
5239 23:09:35.709178 4, 0xFFFF, sum = 0
5240 23:09:35.709776 5, 0xFFFF, sum = 0
5241 23:09:35.712302 6, 0xFFFF, sum = 0
5242 23:09:35.712717 7, 0xFFFF, sum = 0
5243 23:09:35.715033 8, 0xFFFF, sum = 0
5244 23:09:35.715449 9, 0xFFFF, sum = 0
5245 23:09:35.718814 10, 0x0, sum = 1
5246 23:09:35.719233 11, 0x0, sum = 2
5247 23:09:35.722058 12, 0x0, sum = 3
5248 23:09:35.722473 13, 0x0, sum = 4
5249 23:09:35.722803 best_step = 11
5250 23:09:35.725930
5251 23:09:35.726443 ==
5252 23:09:35.728788 Dram Type= 6, Freq= 0, CH_0, rank 0
5253 23:09:35.731682 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5254 23:09:35.732101 ==
5255 23:09:35.732432 RX Vref Scan: 1
5256 23:09:35.732736
5257 23:09:35.735633 RX Vref 0 -> 0, step: 1
5258 23:09:35.736150
5259 23:09:35.738313 RX Delay -45 -> 252, step: 4
5260 23:09:35.738723
5261 23:09:35.741866 Set Vref, RX VrefLevel [Byte0]: 53
5262 23:09:35.745368 [Byte1]: 46
5263 23:09:35.745832
5264 23:09:35.748381 Final RX Vref Byte 0 = 53 to rank0
5265 23:09:35.752213 Final RX Vref Byte 1 = 46 to rank0
5266 23:09:35.755587 Final RX Vref Byte 0 = 53 to rank1
5267 23:09:35.758547 Final RX Vref Byte 1 = 46 to rank1==
5268 23:09:35.761865 Dram Type= 6, Freq= 0, CH_0, rank 0
5269 23:09:35.765373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5270 23:09:35.768165 ==
5271 23:09:35.768582 DQS Delay:
5272 23:09:35.768910 DQS0 = 0, DQS1 = 0
5273 23:09:35.772056 DQM Delay:
5274 23:09:35.772499 DQM0 = 104, DQM1 = 95
5275 23:09:35.774804 DQ Delay:
5276 23:09:35.778518 DQ0 =104, DQ1 =106, DQ2 =102, DQ3 =104
5277 23:09:35.781373 DQ4 =104, DQ5 =96, DQ6 =110, DQ7 =110
5278 23:09:35.784781 DQ8 =84, DQ9 =84, DQ10 =94, DQ11 =90
5279 23:09:35.788068 DQ12 =100, DQ13 =98, DQ14 =108, DQ15 =102
5280 23:09:35.788478
5281 23:09:35.788801
5282 23:09:35.794769 [DQSOSCAuto] RK0, (LSB)MR18= 0x3027, (MSB)MR19= 0x505, tDQSOscB0 = 409 ps tDQSOscB1 = 406 ps
5283 23:09:35.798225 CH0 RK0: MR19=505, MR18=3027
5284 23:09:35.804745 CH0_RK0: MR19=0x505, MR18=0x3027, DQSOSC=406, MR23=63, INC=65, DEC=43
5285 23:09:35.805157
5286 23:09:35.808459 ----->DramcWriteLeveling(PI) begin...
5287 23:09:35.808876 ==
5288 23:09:35.811439 Dram Type= 6, Freq= 0, CH_0, rank 1
5289 23:09:35.814752 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5290 23:09:35.815162 ==
5291 23:09:35.818046 Write leveling (Byte 0): 33 => 33
5292 23:09:35.821000 Write leveling (Byte 1): 32 => 32
5293 23:09:35.824546 DramcWriteLeveling(PI) end<-----
5294 23:09:35.824956
5295 23:09:35.825278 ==
5296 23:09:35.828157 Dram Type= 6, Freq= 0, CH_0, rank 1
5297 23:09:35.831114 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5298 23:09:35.834544 ==
5299 23:09:35.834950 [Gating] SW mode calibration
5300 23:09:35.844388 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5301 23:09:35.847452 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5302 23:09:35.850812 0 14 0 | B1->B0 | 3333 3131 | 0 0 | (0 0) (0 0)
5303 23:09:35.857365 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5304 23:09:35.860519 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5305 23:09:35.863883 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5306 23:09:35.870871 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5307 23:09:35.874301 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5308 23:09:35.877281 0 14 24 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
5309 23:09:35.883992 0 14 28 | B1->B0 | 2e2e 2d2d | 0 0 | (0 0) (0 0)
5310 23:09:35.887378 0 15 0 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
5311 23:09:35.890762 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5312 23:09:35.897543 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5313 23:09:35.900768 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5314 23:09:35.903936 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5315 23:09:35.910605 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5316 23:09:35.914305 0 15 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5317 23:09:35.917680 0 15 28 | B1->B0 | 3e3e 3736 | 0 1 | (0 0) (0 0)
5318 23:09:35.924232 1 0 0 | B1->B0 | 4646 3f3f | 0 0 | (0 0) (0 0)
5319 23:09:35.927099 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5320 23:09:35.930743 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5321 23:09:35.937122 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5322 23:09:35.940969 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5323 23:09:35.944166 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5324 23:09:35.950999 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5325 23:09:35.954059 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5326 23:09:35.957219 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5327 23:09:35.960728 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5328 23:09:35.967231 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5329 23:09:35.970882 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5330 23:09:35.974228 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5331 23:09:35.980846 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5332 23:09:35.984442 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5333 23:09:35.987101 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5334 23:09:35.994130 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5335 23:09:35.997129 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5336 23:09:36.000612 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5337 23:09:36.007127 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5338 23:09:36.010672 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5339 23:09:36.013667 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5340 23:09:36.020400 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5341 23:09:36.024027 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5342 23:09:36.026991 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5343 23:09:36.034158 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5344 23:09:36.034679 Total UI for P1: 0, mck2ui 16
5345 23:09:36.040820 best dqsien dly found for B0: ( 1, 2, 30)
5346 23:09:36.041383 Total UI for P1: 0, mck2ui 16
5347 23:09:36.046874 best dqsien dly found for B1: ( 1, 2, 30)
5348 23:09:36.050224 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5349 23:09:36.053939 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5350 23:09:36.054354
5351 23:09:36.056713 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5352 23:09:36.060129 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5353 23:09:36.063484 [Gating] SW calibration Done
5354 23:09:36.063902 ==
5355 23:09:36.067090 Dram Type= 6, Freq= 0, CH_0, rank 1
5356 23:09:36.069964 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5357 23:09:36.070385 ==
5358 23:09:36.073621 RX Vref Scan: 0
5359 23:09:36.074039
5360 23:09:36.074367 RX Vref 0 -> 0, step: 1
5361 23:09:36.074676
5362 23:09:36.076572 RX Delay -80 -> 252, step: 8
5363 23:09:36.080322 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5364 23:09:36.086911 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5365 23:09:36.090284 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5366 23:09:36.093671 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5367 23:09:36.096664 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5368 23:09:36.100217 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5369 23:09:36.106448 iDelay=208, Bit 6, Center 111 (24 ~ 199) 176
5370 23:09:36.109841 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5371 23:09:36.112877 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5372 23:09:36.116344 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5373 23:09:36.119966 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5374 23:09:36.122845 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5375 23:09:36.130020 iDelay=208, Bit 12, Center 95 (8 ~ 183) 176
5376 23:09:36.133156 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5377 23:09:36.136381 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5378 23:09:36.139475 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5379 23:09:36.139915 ==
5380 23:09:36.142782 Dram Type= 6, Freq= 0, CH_0, rank 1
5381 23:09:36.146513 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5382 23:09:36.146933 ==
5383 23:09:36.149837 DQS Delay:
5384 23:09:36.150404 DQS0 = 0, DQS1 = 0
5385 23:09:36.152681 DQM Delay:
5386 23:09:36.153094 DQM0 = 104, DQM1 = 94
5387 23:09:36.156284 DQ Delay:
5388 23:09:36.156732 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5389 23:09:36.163285 DQ4 =107, DQ5 =95, DQ6 =111, DQ7 =115
5390 23:09:36.163818 DQ8 =87, DQ9 =87, DQ10 =95, DQ11 =87
5391 23:09:36.169376 DQ12 =95, DQ13 =99, DQ14 =103, DQ15 =99
5392 23:09:36.169883
5393 23:09:36.170321
5394 23:09:36.170734 ==
5395 23:09:36.172967 Dram Type= 6, Freq= 0, CH_0, rank 1
5396 23:09:36.176056 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5397 23:09:36.176723 ==
5398 23:09:36.177169
5399 23:09:36.177713
5400 23:09:36.179700 TX Vref Scan disable
5401 23:09:36.180130 == TX Byte 0 ==
5402 23:09:36.186101 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5403 23:09:36.189482 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5404 23:09:36.189967 == TX Byte 1 ==
5405 23:09:36.196129 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5406 23:09:36.199453 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5407 23:09:36.199977 ==
5408 23:09:36.203143 Dram Type= 6, Freq= 0, CH_0, rank 1
5409 23:09:36.205793 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5410 23:09:36.206213 ==
5411 23:09:36.206545
5412 23:09:36.206848
5413 23:09:36.209267 TX Vref Scan disable
5414 23:09:36.212828 == TX Byte 0 ==
5415 23:09:36.216407 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5416 23:09:36.219714 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5417 23:09:36.222480 == TX Byte 1 ==
5418 23:09:36.226444 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5419 23:09:36.229763 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5420 23:09:36.230197
5421 23:09:36.232720 [DATLAT]
5422 23:09:36.233242 Freq=933, CH0 RK1
5423 23:09:36.233619
5424 23:09:36.236335 DATLAT Default: 0xb
5425 23:09:36.236854 0, 0xFFFF, sum = 0
5426 23:09:36.239538 1, 0xFFFF, sum = 0
5427 23:09:36.239963 2, 0xFFFF, sum = 0
5428 23:09:36.242439 3, 0xFFFF, sum = 0
5429 23:09:36.242861 4, 0xFFFF, sum = 0
5430 23:09:36.245763 5, 0xFFFF, sum = 0
5431 23:09:36.246187 6, 0xFFFF, sum = 0
5432 23:09:36.249227 7, 0xFFFF, sum = 0
5433 23:09:36.249688 8, 0xFFFF, sum = 0
5434 23:09:36.252692 9, 0xFFFF, sum = 0
5435 23:09:36.253256 10, 0x0, sum = 1
5436 23:09:36.255772 11, 0x0, sum = 2
5437 23:09:36.256195 12, 0x0, sum = 3
5438 23:09:36.259002 13, 0x0, sum = 4
5439 23:09:36.259518 best_step = 11
5440 23:09:36.260028
5441 23:09:36.260457 ==
5442 23:09:36.262545 Dram Type= 6, Freq= 0, CH_0, rank 1
5443 23:09:36.269370 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5444 23:09:36.269841 ==
5445 23:09:36.270176 RX Vref Scan: 0
5446 23:09:36.270487
5447 23:09:36.272232 RX Vref 0 -> 0, step: 1
5448 23:09:36.272644
5449 23:09:36.275676 RX Delay -45 -> 252, step: 4
5450 23:09:36.279501 iDelay=199, Bit 0, Center 100 (11 ~ 190) 180
5451 23:09:36.283037 iDelay=199, Bit 1, Center 106 (19 ~ 194) 176
5452 23:09:36.289220 iDelay=199, Bit 2, Center 100 (11 ~ 190) 180
5453 23:09:36.292922 iDelay=199, Bit 3, Center 100 (11 ~ 190) 180
5454 23:09:36.295838 iDelay=199, Bit 4, Center 106 (19 ~ 194) 176
5455 23:09:36.299526 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5456 23:09:36.302743 iDelay=199, Bit 6, Center 108 (23 ~ 194) 172
5457 23:09:36.309282 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5458 23:09:36.312771 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5459 23:09:36.316073 iDelay=199, Bit 9, Center 82 (-1 ~ 166) 168
5460 23:09:36.319088 iDelay=199, Bit 10, Center 96 (15 ~ 178) 164
5461 23:09:36.322447 iDelay=199, Bit 11, Center 88 (7 ~ 170) 164
5462 23:09:36.328808 iDelay=199, Bit 12, Center 98 (19 ~ 178) 160
5463 23:09:36.332266 iDelay=199, Bit 13, Center 98 (15 ~ 182) 168
5464 23:09:36.335722 iDelay=199, Bit 14, Center 102 (19 ~ 186) 168
5465 23:09:36.339259 iDelay=199, Bit 15, Center 100 (15 ~ 186) 172
5466 23:09:36.339677 ==
5467 23:09:36.342049 Dram Type= 6, Freq= 0, CH_0, rank 1
5468 23:09:36.345668 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5469 23:09:36.349175 ==
5470 23:09:36.349645 DQS Delay:
5471 23:09:36.349991 DQS0 = 0, DQS1 = 0
5472 23:09:36.352417 DQM Delay:
5473 23:09:36.352943 DQM0 = 103, DQM1 = 93
5474 23:09:36.355791 DQ Delay:
5475 23:09:36.358911 DQ0 =100, DQ1 =106, DQ2 =100, DQ3 =100
5476 23:09:36.362155 DQ4 =106, DQ5 =98, DQ6 =108, DQ7 =112
5477 23:09:36.365186 DQ8 =84, DQ9 =82, DQ10 =96, DQ11 =88
5478 23:09:36.369003 DQ12 =98, DQ13 =98, DQ14 =102, DQ15 =100
5479 23:09:36.369422
5480 23:09:36.369810
5481 23:09:36.375799 [DQSOSCAuto] RK1, (LSB)MR18= 0x24fe, (MSB)MR19= 0x504, tDQSOscB0 = 422 ps tDQSOscB1 = 410 ps
5482 23:09:36.379352 CH0 RK1: MR19=504, MR18=24FE
5483 23:09:36.385415 CH0_RK1: MR19=0x504, MR18=0x24FE, DQSOSC=410, MR23=63, INC=64, DEC=42
5484 23:09:36.388882 [RxdqsGatingPostProcess] freq 933
5485 23:09:36.395316 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5486 23:09:36.395856 best DQS0 dly(2T, 0.5T) = (0, 10)
5487 23:09:36.398914 best DQS1 dly(2T, 0.5T) = (0, 11)
5488 23:09:36.402310 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5489 23:09:36.405275 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5490 23:09:36.408870 best DQS0 dly(2T, 0.5T) = (0, 10)
5491 23:09:36.411879 best DQS1 dly(2T, 0.5T) = (0, 10)
5492 23:09:36.415217 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5493 23:09:36.418573 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5494 23:09:36.422137 Pre-setting of DQS Precalculation
5495 23:09:36.424877 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5496 23:09:36.428883 ==
5497 23:09:36.431702 Dram Type= 6, Freq= 0, CH_1, rank 0
5498 23:09:36.435520 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5499 23:09:36.435941 ==
5500 23:09:36.438709 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5501 23:09:36.445201 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5502 23:09:36.448766 [CA 0] Center 36 (6~67) winsize 62
5503 23:09:36.452682 [CA 1] Center 37 (7~67) winsize 61
5504 23:09:36.455513 [CA 2] Center 34 (4~65) winsize 62
5505 23:09:36.458423 [CA 3] Center 34 (4~65) winsize 62
5506 23:09:36.462127 [CA 4] Center 34 (4~64) winsize 61
5507 23:09:36.465422 [CA 5] Center 33 (3~64) winsize 62
5508 23:09:36.465977
5509 23:09:36.468859 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5510 23:09:36.469276
5511 23:09:36.471704 [CATrainingPosCal] consider 1 rank data
5512 23:09:36.475001 u2DelayCellTimex100 = 270/100 ps
5513 23:09:36.478973 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5514 23:09:36.485416 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5515 23:09:36.488718 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5516 23:09:36.491591 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5517 23:09:36.495155 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5518 23:09:36.498321 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5519 23:09:36.498745
5520 23:09:36.501497 CA PerBit enable=1, Macro0, CA PI delay=33
5521 23:09:36.501983
5522 23:09:36.505283 [CBTSetCACLKResult] CA Dly = 33
5523 23:09:36.508204 CS Dly: 7 (0~38)
5524 23:09:36.508718 ==
5525 23:09:36.511635 Dram Type= 6, Freq= 0, CH_1, rank 1
5526 23:09:36.514570 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5527 23:09:36.515079 ==
5528 23:09:36.521291 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5529 23:09:36.524776 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5530 23:09:36.528959 [CA 0] Center 36 (6~67) winsize 62
5531 23:09:36.532104 [CA 1] Center 37 (6~68) winsize 63
5532 23:09:36.535161 [CA 2] Center 35 (5~66) winsize 62
5533 23:09:36.538854 [CA 3] Center 34 (4~65) winsize 62
5534 23:09:36.541849 [CA 4] Center 34 (4~65) winsize 62
5535 23:09:36.545159 [CA 5] Center 34 (4~64) winsize 61
5536 23:09:36.545776
5537 23:09:36.548463 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5538 23:09:36.549049
5539 23:09:36.551640 [CATrainingPosCal] consider 2 rank data
5540 23:09:36.555299 u2DelayCellTimex100 = 270/100 ps
5541 23:09:36.558603 CA0 delay=36 (6~67),Diff = 2 PI (12 cell)
5542 23:09:36.565317 CA1 delay=37 (7~67),Diff = 3 PI (18 cell)
5543 23:09:36.568386 CA2 delay=35 (5~65),Diff = 1 PI (6 cell)
5544 23:09:36.571739 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5545 23:09:36.575321 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5546 23:09:36.578239 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5547 23:09:36.578871
5548 23:09:36.581504 CA PerBit enable=1, Macro0, CA PI delay=34
5549 23:09:36.582087
5550 23:09:36.584966 [CBTSetCACLKResult] CA Dly = 34
5551 23:09:36.585614 CS Dly: 8 (0~40)
5552 23:09:36.588008
5553 23:09:36.591474 ----->DramcWriteLeveling(PI) begin...
5554 23:09:36.592113 ==
5555 23:09:36.595012 Dram Type= 6, Freq= 0, CH_1, rank 0
5556 23:09:36.598354 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5557 23:09:36.598907 ==
5558 23:09:36.601454 Write leveling (Byte 0): 29 => 29
5559 23:09:36.605156 Write leveling (Byte 1): 26 => 26
5560 23:09:36.608277 DramcWriteLeveling(PI) end<-----
5561 23:09:36.608804
5562 23:09:36.609287 ==
5563 23:09:36.611433 Dram Type= 6, Freq= 0, CH_1, rank 0
5564 23:09:36.614783 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5565 23:09:36.615199 ==
5566 23:09:36.618231 [Gating] SW mode calibration
5567 23:09:36.624705 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5568 23:09:36.631510 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5569 23:09:36.634788 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5570 23:09:36.638146 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5571 23:09:36.644486 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5572 23:09:36.647890 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5573 23:09:36.651285 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5574 23:09:36.658461 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5575 23:09:36.661237 0 14 24 | B1->B0 | 3434 2f2f | 1 1 | (1 0) (1 1)
5576 23:09:36.664334 0 14 28 | B1->B0 | 2e2e 2323 | 0 0 | (0 0) (0 0)
5577 23:09:36.670897 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5578 23:09:36.674494 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5579 23:09:36.677994 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5580 23:09:36.684495 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5581 23:09:36.687854 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5582 23:09:36.691665 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5583 23:09:36.697681 0 15 24 | B1->B0 | 2727 3333 | 0 1 | (0 0) (0 0)
5584 23:09:36.701176 0 15 28 | B1->B0 | 4343 4646 | 1 0 | (0 0) (0 0)
5585 23:09:36.704178 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5586 23:09:36.710928 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5587 23:09:36.714377 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5588 23:09:36.717380 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5589 23:09:36.724054 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5590 23:09:36.726909 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5591 23:09:36.730570 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5592 23:09:36.737084 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5593 23:09:36.740353 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5594 23:09:36.744010 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5595 23:09:36.750339 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5596 23:09:36.753911 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5597 23:09:36.756911 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5598 23:09:36.763623 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5599 23:09:36.766755 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5600 23:09:36.770254 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5601 23:09:36.777214 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5602 23:09:36.779772 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5603 23:09:36.783658 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5604 23:09:36.786801 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5605 23:09:36.793627 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5606 23:09:36.797024 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5607 23:09:36.800352 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5608 23:09:36.806815 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5609 23:09:36.810103 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5610 23:09:36.813637 Total UI for P1: 0, mck2ui 16
5611 23:09:36.816676 best dqsien dly found for B0: ( 1, 2, 26)
5612 23:09:36.819859 Total UI for P1: 0, mck2ui 16
5613 23:09:36.823479 best dqsien dly found for B1: ( 1, 2, 26)
5614 23:09:36.826971 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5615 23:09:36.830042 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5616 23:09:36.830451
5617 23:09:36.833325 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5618 23:09:36.836359 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5619 23:09:36.839715 [Gating] SW calibration Done
5620 23:09:36.840257 ==
5621 23:09:36.843336 Dram Type= 6, Freq= 0, CH_1, rank 0
5622 23:09:36.849741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5623 23:09:36.850165 ==
5624 23:09:36.850495 RX Vref Scan: 0
5625 23:09:36.850803
5626 23:09:36.853321 RX Vref 0 -> 0, step: 1
5627 23:09:36.853904
5628 23:09:36.856620 RX Delay -80 -> 252, step: 8
5629 23:09:36.859781 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5630 23:09:36.862912 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5631 23:09:36.866486 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5632 23:09:36.869502 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5633 23:09:36.873098 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5634 23:09:36.879356 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5635 23:09:36.883368 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5636 23:09:36.886095 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5637 23:09:36.889978 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5638 23:09:36.893069 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5639 23:09:36.899803 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5640 23:09:36.903210 iDelay=208, Bit 11, Center 95 (8 ~ 183) 176
5641 23:09:36.906748 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5642 23:09:36.909423 iDelay=208, Bit 13, Center 107 (16 ~ 199) 184
5643 23:09:36.912408 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5644 23:09:36.919662 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5645 23:09:36.920077 ==
5646 23:09:36.922396 Dram Type= 6, Freq= 0, CH_1, rank 0
5647 23:09:36.925767 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5648 23:09:36.926184 ==
5649 23:09:36.926513 DQS Delay:
5650 23:09:36.929365 DQS0 = 0, DQS1 = 0
5651 23:09:36.929891 DQM Delay:
5652 23:09:36.933054 DQM0 = 102, DQM1 = 99
5653 23:09:36.933463 DQ Delay:
5654 23:09:36.935828 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
5655 23:09:36.939393 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =103
5656 23:09:36.942602 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =95
5657 23:09:36.945976 DQ12 =107, DQ13 =107, DQ14 =103, DQ15 =107
5658 23:09:36.946389
5659 23:09:36.946711
5660 23:09:36.947009 ==
5661 23:09:36.949191 Dram Type= 6, Freq= 0, CH_1, rank 0
5662 23:09:36.955538 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5663 23:09:36.955970 ==
5664 23:09:36.956301
5665 23:09:36.956607
5666 23:09:36.956903 TX Vref Scan disable
5667 23:09:36.959170 == TX Byte 0 ==
5668 23:09:36.962515 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5669 23:09:36.969040 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5670 23:09:36.969457 == TX Byte 1 ==
5671 23:09:36.972196 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5672 23:09:36.979042 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5673 23:09:36.979462 ==
5674 23:09:36.982342 Dram Type= 6, Freq= 0, CH_1, rank 0
5675 23:09:36.985455 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5676 23:09:36.985781 ==
5677 23:09:36.985983
5678 23:09:36.986148
5679 23:09:36.989091 TX Vref Scan disable
5680 23:09:36.989313 == TX Byte 0 ==
5681 23:09:36.995766 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5682 23:09:36.999241 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5683 23:09:36.999533 == TX Byte 1 ==
5684 23:09:37.005656 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5685 23:09:37.008919 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5686 23:09:37.009189
5687 23:09:37.009349 [DATLAT]
5688 23:09:37.012780 Freq=933, CH1 RK0
5689 23:09:37.013046
5690 23:09:37.013211 DATLAT Default: 0xd
5691 23:09:37.015546 0, 0xFFFF, sum = 0
5692 23:09:37.015733 1, 0xFFFF, sum = 0
5693 23:09:37.019329 2, 0xFFFF, sum = 0
5694 23:09:37.019597 3, 0xFFFF, sum = 0
5695 23:09:37.021954 4, 0xFFFF, sum = 0
5696 23:09:37.022255 5, 0xFFFF, sum = 0
5697 23:09:37.025648 6, 0xFFFF, sum = 0
5698 23:09:37.028918 7, 0xFFFF, sum = 0
5699 23:09:37.029210 8, 0xFFFF, sum = 0
5700 23:09:37.032033 9, 0xFFFF, sum = 0
5701 23:09:37.032294 10, 0x0, sum = 1
5702 23:09:37.032502 11, 0x0, sum = 2
5703 23:09:37.035750 12, 0x0, sum = 3
5704 23:09:37.036011 13, 0x0, sum = 4
5705 23:09:37.038835 best_step = 11
5706 23:09:37.039088
5707 23:09:37.039291 ==
5708 23:09:37.041825 Dram Type= 6, Freq= 0, CH_1, rank 0
5709 23:09:37.045599 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5710 23:09:37.045856 ==
5711 23:09:37.048652 RX Vref Scan: 1
5712 23:09:37.048871
5713 23:09:37.049058 RX Vref 0 -> 0, step: 1
5714 23:09:37.049238
5715 23:09:37.052173 RX Delay -45 -> 252, step: 4
5716 23:09:37.052428
5717 23:09:37.055580 Set Vref, RX VrefLevel [Byte0]: 53
5718 23:09:37.058703 [Byte1]: 47
5719 23:09:37.062944
5720 23:09:37.063209 Final RX Vref Byte 0 = 53 to rank0
5721 23:09:37.065999 Final RX Vref Byte 1 = 47 to rank0
5722 23:09:37.069544 Final RX Vref Byte 0 = 53 to rank1
5723 23:09:37.072854 Final RX Vref Byte 1 = 47 to rank1==
5724 23:09:37.075868 Dram Type= 6, Freq= 0, CH_1, rank 0
5725 23:09:37.082642 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5726 23:09:37.083010 ==
5727 23:09:37.083269 DQS Delay:
5728 23:09:37.085832 DQS0 = 0, DQS1 = 0
5729 23:09:37.086091 DQM Delay:
5730 23:09:37.086295 DQM0 = 103, DQM1 = 98
5731 23:09:37.089277 DQ Delay:
5732 23:09:37.092389 DQ0 =106, DQ1 =98, DQ2 =94, DQ3 =100
5733 23:09:37.095741 DQ4 =104, DQ5 =112, DQ6 =110, DQ7 =102
5734 23:09:37.099558 DQ8 =88, DQ9 =90, DQ10 =98, DQ11 =92
5735 23:09:37.102315 DQ12 =106, DQ13 =104, DQ14 =102, DQ15 =106
5736 23:09:37.102585
5737 23:09:37.102788
5738 23:09:37.109472 [DQSOSCAuto] RK0, (LSB)MR18= 0x142b, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 415 ps
5739 23:09:37.112265 CH1 RK0: MR19=505, MR18=142B
5740 23:09:37.119402 CH1_RK0: MR19=0x505, MR18=0x142B, DQSOSC=408, MR23=63, INC=65, DEC=43
5741 23:09:37.119658
5742 23:09:37.122357 ----->DramcWriteLeveling(PI) begin...
5743 23:09:37.122613 ==
5744 23:09:37.125676 Dram Type= 6, Freq= 0, CH_1, rank 1
5745 23:09:37.128921 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5746 23:09:37.129174 ==
5747 23:09:37.132343 Write leveling (Byte 0): 26 => 26
5748 23:09:37.135396 Write leveling (Byte 1): 26 => 26
5749 23:09:37.138816 DramcWriteLeveling(PI) end<-----
5750 23:09:37.139150
5751 23:09:37.139439 ==
5752 23:09:37.141878 Dram Type= 6, Freq= 0, CH_1, rank 1
5753 23:09:37.148584 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5754 23:09:37.148841 ==
5755 23:09:37.149043 [Gating] SW mode calibration
5756 23:09:37.158723 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5757 23:09:37.161871 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5758 23:09:37.168649 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5759 23:09:37.172095 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5760 23:09:37.175635 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5761 23:09:37.181955 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5762 23:09:37.184982 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5763 23:09:37.188699 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5764 23:09:37.195373 0 14 24 | B1->B0 | 2e2e 3232 | 0 1 | (0 1) (0 0)
5765 23:09:37.198800 0 14 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
5766 23:09:37.201952 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5767 23:09:37.205003 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5768 23:09:37.211691 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5769 23:09:37.214980 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5770 23:09:37.218730 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5771 23:09:37.225245 0 15 20 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
5772 23:09:37.228217 0 15 24 | B1->B0 | 3636 2828 | 0 0 | (0 0) (0 0)
5773 23:09:37.231645 0 15 28 | B1->B0 | 4646 4242 | 0 0 | (0 0) (0 0)
5774 23:09:37.238129 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5775 23:09:37.241252 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5776 23:09:37.245122 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5777 23:09:37.251146 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5778 23:09:37.254393 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5779 23:09:37.257913 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5780 23:09:37.264161 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5781 23:09:37.267768 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5782 23:09:37.270954 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5783 23:09:37.277530 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5784 23:09:37.281014 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5785 23:09:37.284391 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5786 23:09:37.291544 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5787 23:09:37.294417 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5788 23:09:37.298342 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5789 23:09:37.304766 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5790 23:09:37.308016 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5791 23:09:37.311072 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5792 23:09:37.317746 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5793 23:09:37.321134 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5794 23:09:37.324326 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5795 23:09:37.331041 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5796 23:09:37.334450 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5797 23:09:37.338062 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5798 23:09:37.341026 Total UI for P1: 0, mck2ui 16
5799 23:09:37.344648 best dqsien dly found for B0: ( 1, 2, 26)
5800 23:09:37.348176 Total UI for P1: 0, mck2ui 16
5801 23:09:37.351055 best dqsien dly found for B1: ( 1, 2, 24)
5802 23:09:37.354281 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5803 23:09:37.357930 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5804 23:09:37.358362
5805 23:09:37.361137 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5806 23:09:37.367621 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5807 23:09:37.368203 [Gating] SW calibration Done
5808 23:09:37.368726 ==
5809 23:09:37.370790 Dram Type= 6, Freq= 0, CH_1, rank 1
5810 23:09:37.378001 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5811 23:09:37.378486 ==
5812 23:09:37.378877 RX Vref Scan: 0
5813 23:09:37.379363
5814 23:09:37.380791 RX Vref 0 -> 0, step: 1
5815 23:09:37.381220
5816 23:09:37.384106 RX Delay -80 -> 252, step: 8
5817 23:09:37.387653 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5818 23:09:37.390657 iDelay=208, Bit 1, Center 103 (16 ~ 191) 176
5819 23:09:37.394253 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5820 23:09:37.400920 iDelay=208, Bit 3, Center 103 (16 ~ 191) 176
5821 23:09:37.403789 iDelay=208, Bit 4, Center 99 (16 ~ 183) 168
5822 23:09:37.407438 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5823 23:09:37.410467 iDelay=208, Bit 6, Center 111 (24 ~ 199) 176
5824 23:09:37.414166 iDelay=208, Bit 7, Center 103 (16 ~ 191) 176
5825 23:09:37.420470 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5826 23:09:37.424217 iDelay=208, Bit 9, Center 91 (0 ~ 183) 184
5827 23:09:37.427049 iDelay=208, Bit 10, Center 103 (16 ~ 191) 176
5828 23:09:37.430418 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5829 23:09:37.434171 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5830 23:09:37.440586 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5831 23:09:37.443798 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5832 23:09:37.447304 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5833 23:09:37.447725 ==
5834 23:09:37.450111 Dram Type= 6, Freq= 0, CH_1, rank 1
5835 23:09:37.453557 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5836 23:09:37.454124 ==
5837 23:09:37.457332 DQS Delay:
5838 23:09:37.457929 DQS0 = 0, DQS1 = 0
5839 23:09:37.460219 DQM Delay:
5840 23:09:37.460633 DQM0 = 104, DQM1 = 98
5841 23:09:37.460964 DQ Delay:
5842 23:09:37.464037 DQ0 =107, DQ1 =103, DQ2 =91, DQ3 =103
5843 23:09:37.466937 DQ4 =99, DQ5 =115, DQ6 =111, DQ7 =103
5844 23:09:37.470427 DQ8 =83, DQ9 =91, DQ10 =103, DQ11 =91
5845 23:09:37.477231 DQ12 =107, DQ13 =103, DQ14 =103, DQ15 =107
5846 23:09:37.477784
5847 23:09:37.478126
5848 23:09:37.478431 ==
5849 23:09:37.480832 Dram Type= 6, Freq= 0, CH_1, rank 1
5850 23:09:37.483514 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5851 23:09:37.483940 ==
5852 23:09:37.484267
5853 23:09:37.484572
5854 23:09:37.487066 TX Vref Scan disable
5855 23:09:37.487577 == TX Byte 0 ==
5856 23:09:37.493249 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5857 23:09:37.496556 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5858 23:09:37.497113 == TX Byte 1 ==
5859 23:09:37.503878 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5860 23:09:37.506769 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5861 23:09:37.507189 ==
5862 23:09:37.510153 Dram Type= 6, Freq= 0, CH_1, rank 1
5863 23:09:37.513761 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5864 23:09:37.514180 ==
5865 23:09:37.514510
5866 23:09:37.516672
5867 23:09:37.517165 TX Vref Scan disable
5868 23:09:37.520549 == TX Byte 0 ==
5869 23:09:37.523183 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5870 23:09:37.526805 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5871 23:09:37.530045 == TX Byte 1 ==
5872 23:09:37.533373 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5873 23:09:37.536940 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5874 23:09:37.537498
5875 23:09:37.540198 [DATLAT]
5876 23:09:37.540611 Freq=933, CH1 RK1
5877 23:09:37.540942
5878 23:09:37.543424 DATLAT Default: 0xb
5879 23:09:37.543857 0, 0xFFFF, sum = 0
5880 23:09:37.546517 1, 0xFFFF, sum = 0
5881 23:09:37.546939 2, 0xFFFF, sum = 0
5882 23:09:37.549828 3, 0xFFFF, sum = 0
5883 23:09:37.550250 4, 0xFFFF, sum = 0
5884 23:09:37.553677 5, 0xFFFF, sum = 0
5885 23:09:37.554117 6, 0xFFFF, sum = 0
5886 23:09:37.556663 7, 0xFFFF, sum = 0
5887 23:09:37.559631 8, 0xFFFF, sum = 0
5888 23:09:37.560066 9, 0xFFFF, sum = 0
5889 23:09:37.560406 10, 0x0, sum = 1
5890 23:09:37.563502 11, 0x0, sum = 2
5891 23:09:37.563928 12, 0x0, sum = 3
5892 23:09:37.566805 13, 0x0, sum = 4
5893 23:09:37.567312 best_step = 11
5894 23:09:37.567770
5895 23:09:37.568089 ==
5896 23:09:37.569868 Dram Type= 6, Freq= 0, CH_1, rank 1
5897 23:09:37.576788 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5898 23:09:37.577205 ==
5899 23:09:37.577764 RX Vref Scan: 0
5900 23:09:37.578271
5901 23:09:37.580349 RX Vref 0 -> 0, step: 1
5902 23:09:37.580760
5903 23:09:37.583317 RX Delay -53 -> 252, step: 4
5904 23:09:37.586432 iDelay=203, Bit 0, Center 108 (27 ~ 190) 164
5905 23:09:37.593700 iDelay=203, Bit 1, Center 100 (19 ~ 182) 164
5906 23:09:37.596608 iDelay=203, Bit 2, Center 94 (11 ~ 178) 168
5907 23:09:37.600062 iDelay=203, Bit 3, Center 100 (19 ~ 182) 164
5908 23:09:37.603360 iDelay=203, Bit 4, Center 100 (19 ~ 182) 164
5909 23:09:37.606449 iDelay=203, Bit 5, Center 118 (35 ~ 202) 168
5910 23:09:37.610080 iDelay=203, Bit 6, Center 112 (27 ~ 198) 172
5911 23:09:37.616470 iDelay=203, Bit 7, Center 102 (19 ~ 186) 168
5912 23:09:37.619849 iDelay=203, Bit 8, Center 90 (7 ~ 174) 168
5913 23:09:37.623500 iDelay=203, Bit 9, Center 88 (3 ~ 174) 172
5914 23:09:37.626537 iDelay=203, Bit 10, Center 100 (15 ~ 186) 172
5915 23:09:37.630107 iDelay=203, Bit 11, Center 92 (7 ~ 178) 172
5916 23:09:37.636428 iDelay=203, Bit 12, Center 110 (23 ~ 198) 176
5917 23:09:37.640065 iDelay=203, Bit 13, Center 104 (23 ~ 186) 164
5918 23:09:37.642996 iDelay=203, Bit 14, Center 104 (23 ~ 186) 164
5919 23:09:37.646575 iDelay=203, Bit 15, Center 108 (23 ~ 194) 172
5920 23:09:37.647158 ==
5921 23:09:37.649420 Dram Type= 6, Freq= 0, CH_1, rank 1
5922 23:09:37.656108 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5923 23:09:37.656566 ==
5924 23:09:37.656898 DQS Delay:
5925 23:09:37.657416 DQS0 = 0, DQS1 = 0
5926 23:09:37.659521 DQM Delay:
5927 23:09:37.659985 DQM0 = 104, DQM1 = 99
5928 23:09:37.662995 DQ Delay:
5929 23:09:37.666007 DQ0 =108, DQ1 =100, DQ2 =94, DQ3 =100
5930 23:09:37.669329 DQ4 =100, DQ5 =118, DQ6 =112, DQ7 =102
5931 23:09:37.672687 DQ8 =90, DQ9 =88, DQ10 =100, DQ11 =92
5932 23:09:37.676177 DQ12 =110, DQ13 =104, DQ14 =104, DQ15 =108
5933 23:09:37.676688
5934 23:09:37.677177
5935 23:09:37.682808 [DQSOSCAuto] RK1, (LSB)MR18= 0x2bfe, (MSB)MR19= 0x504, tDQSOscB0 = 422 ps tDQSOscB1 = 408 ps
5936 23:09:37.686078 CH1 RK1: MR19=504, MR18=2BFE
5937 23:09:37.692628 CH1_RK1: MR19=0x504, MR18=0x2BFE, DQSOSC=408, MR23=63, INC=65, DEC=43
5938 23:09:37.695761 [RxdqsGatingPostProcess] freq 933
5939 23:09:37.702409 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5940 23:09:37.705856 best DQS0 dly(2T, 0.5T) = (0, 10)
5941 23:09:37.709189 best DQS1 dly(2T, 0.5T) = (0, 10)
5942 23:09:37.712554 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5943 23:09:37.716090 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5944 23:09:37.716726 best DQS0 dly(2T, 0.5T) = (0, 10)
5945 23:09:37.719082 best DQS1 dly(2T, 0.5T) = (0, 10)
5946 23:09:37.722480 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5947 23:09:37.726076 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5948 23:09:37.728925 Pre-setting of DQS Precalculation
5949 23:09:37.735658 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5950 23:09:37.742260 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5951 23:09:37.749243 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5952 23:09:37.749703
5953 23:09:37.750156
5954 23:09:37.752230 [Calibration Summary] 1866 Mbps
5955 23:09:37.752835 CH 0, Rank 0
5956 23:09:37.755644 SW Impedance : PASS
5957 23:09:37.758953 DUTY Scan : NO K
5958 23:09:37.759496 ZQ Calibration : PASS
5959 23:09:37.762513 Jitter Meter : NO K
5960 23:09:37.765701 CBT Training : PASS
5961 23:09:37.766181 Write leveling : PASS
5962 23:09:37.769014 RX DQS gating : PASS
5963 23:09:37.772076 RX DQ/DQS(RDDQC) : PASS
5964 23:09:37.772642 TX DQ/DQS : PASS
5965 23:09:37.775548 RX DATLAT : PASS
5966 23:09:37.776120 RX DQ/DQS(Engine): PASS
5967 23:09:37.779168 TX OE : NO K
5968 23:09:37.779746 All Pass.
5969 23:09:37.780240
5970 23:09:37.782080 CH 0, Rank 1
5971 23:09:37.782573 SW Impedance : PASS
5972 23:09:37.785616 DUTY Scan : NO K
5973 23:09:37.788717 ZQ Calibration : PASS
5974 23:09:37.789130 Jitter Meter : NO K
5975 23:09:37.792426 CBT Training : PASS
5976 23:09:37.795621 Write leveling : PASS
5977 23:09:37.796064 RX DQS gating : PASS
5978 23:09:37.798864 RX DQ/DQS(RDDQC) : PASS
5979 23:09:37.802080 TX DQ/DQS : PASS
5980 23:09:37.802674 RX DATLAT : PASS
5981 23:09:37.805617 RX DQ/DQS(Engine): PASS
5982 23:09:37.808738 TX OE : NO K
5983 23:09:37.809142 All Pass.
5984 23:09:37.809546
5985 23:09:37.809951 CH 1, Rank 0
5986 23:09:37.812348 SW Impedance : PASS
5987 23:09:37.815670 DUTY Scan : NO K
5988 23:09:37.816255 ZQ Calibration : PASS
5989 23:09:37.818962 Jitter Meter : NO K
5990 23:09:37.822040 CBT Training : PASS
5991 23:09:37.822636 Write leveling : PASS
5992 23:09:37.825898 RX DQS gating : PASS
5993 23:09:37.826349 RX DQ/DQS(RDDQC) : PASS
5994 23:09:37.829246 TX DQ/DQS : PASS
5995 23:09:37.832221 RX DATLAT : PASS
5996 23:09:37.832682 RX DQ/DQS(Engine): PASS
5997 23:09:37.835672 TX OE : NO K
5998 23:09:37.836245 All Pass.
5999 23:09:37.836741
6000 23:09:37.838678 CH 1, Rank 1
6001 23:09:37.839138 SW Impedance : PASS
6002 23:09:37.842178 DUTY Scan : NO K
6003 23:09:37.845226 ZQ Calibration : PASS
6004 23:09:37.845850 Jitter Meter : NO K
6005 23:09:37.848852 CBT Training : PASS
6006 23:09:37.852098 Write leveling : PASS
6007 23:09:37.852659 RX DQS gating : PASS
6008 23:09:37.855466 RX DQ/DQS(RDDQC) : PASS
6009 23:09:37.858443 TX DQ/DQS : PASS
6010 23:09:37.858861 RX DATLAT : PASS
6011 23:09:37.862088 RX DQ/DQS(Engine): PASS
6012 23:09:37.865109 TX OE : NO K
6013 23:09:37.865721 All Pass.
6014 23:09:37.866161
6015 23:09:37.866620 DramC Write-DBI off
6016 23:09:37.868740 PER_BANK_REFRESH: Hybrid Mode
6017 23:09:37.872426 TX_TRACKING: ON
6018 23:09:37.878807 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6019 23:09:37.882071 [FAST_K] Save calibration result to emmc
6020 23:09:37.888677 dramc_set_vcore_voltage set vcore to 650000
6021 23:09:37.889337 Read voltage for 400, 6
6022 23:09:37.891549 Vio18 = 0
6023 23:09:37.892105 Vcore = 650000
6024 23:09:37.892614 Vdram = 0
6025 23:09:37.895221 Vddq = 0
6026 23:09:37.895637 Vmddr = 0
6027 23:09:37.898410 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6028 23:09:37.905458 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6029 23:09:37.908489 MEM_TYPE=3, freq_sel=20
6030 23:09:37.909028 sv_algorithm_assistance_LP4_800
6031 23:09:37.915009 ============ PULL DRAM RESETB DOWN ============
6032 23:09:37.918292 ========== PULL DRAM RESETB DOWN end =========
6033 23:09:37.922038 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6034 23:09:37.924889 ===================================
6035 23:09:37.928438 LPDDR4 DRAM CONFIGURATION
6036 23:09:37.931508 ===================================
6037 23:09:37.935107 EX_ROW_EN[0] = 0x0
6038 23:09:37.935521 EX_ROW_EN[1] = 0x0
6039 23:09:37.938579 LP4Y_EN = 0x0
6040 23:09:37.938992 WORK_FSP = 0x0
6041 23:09:37.941561 WL = 0x2
6042 23:09:37.942005 RL = 0x2
6043 23:09:37.945527 BL = 0x2
6044 23:09:37.946108 RPST = 0x0
6045 23:09:37.949245 RD_PRE = 0x0
6046 23:09:37.949814 WR_PRE = 0x1
6047 23:09:37.951698 WR_PST = 0x0
6048 23:09:37.952114 DBI_WR = 0x0
6049 23:09:37.954964 DBI_RD = 0x0
6050 23:09:37.958689 OTF = 0x1
6051 23:09:37.959110 ===================================
6052 23:09:37.961515 ===================================
6053 23:09:37.964826 ANA top config
6054 23:09:37.968195 ===================================
6055 23:09:37.971713 DLL_ASYNC_EN = 0
6056 23:09:37.972229 ALL_SLAVE_EN = 1
6057 23:09:37.975135 NEW_RANK_MODE = 1
6058 23:09:37.977992 DLL_IDLE_MODE = 1
6059 23:09:37.981750 LP45_APHY_COMB_EN = 1
6060 23:09:37.984804 TX_ODT_DIS = 1
6061 23:09:37.985222 NEW_8X_MODE = 1
6062 23:09:37.988587 ===================================
6063 23:09:37.991481 ===================================
6064 23:09:37.994678 data_rate = 800
6065 23:09:37.998155 CKR = 1
6066 23:09:38.001877 DQ_P2S_RATIO = 4
6067 23:09:38.005343 ===================================
6068 23:09:38.008147 CA_P2S_RATIO = 4
6069 23:09:38.008628 DQ_CA_OPEN = 0
6070 23:09:38.011951 DQ_SEMI_OPEN = 1
6071 23:09:38.014765 CA_SEMI_OPEN = 1
6072 23:09:38.018279 CA_FULL_RATE = 0
6073 23:09:38.021695 DQ_CKDIV4_EN = 0
6074 23:09:38.024916 CA_CKDIV4_EN = 1
6075 23:09:38.025381 CA_PREDIV_EN = 0
6076 23:09:38.028387 PH8_DLY = 0
6077 23:09:38.032033 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6078 23:09:38.035075 DQ_AAMCK_DIV = 0
6079 23:09:38.038589 CA_AAMCK_DIV = 0
6080 23:09:38.041384 CA_ADMCK_DIV = 4
6081 23:09:38.041853 DQ_TRACK_CA_EN = 0
6082 23:09:38.045121 CA_PICK = 800
6083 23:09:38.048416 CA_MCKIO = 400
6084 23:09:38.052076 MCKIO_SEMI = 400
6085 23:09:38.054934 PLL_FREQ = 3016
6086 23:09:38.058183 DQ_UI_PI_RATIO = 32
6087 23:09:38.061666 CA_UI_PI_RATIO = 32
6088 23:09:38.064956 ===================================
6089 23:09:38.068074 ===================================
6090 23:09:38.068565 memory_type:LPDDR4
6091 23:09:38.071429 GP_NUM : 10
6092 23:09:38.074847 SRAM_EN : 1
6093 23:09:38.075265 MD32_EN : 0
6094 23:09:38.077965 ===================================
6095 23:09:38.081280 [ANA_INIT] >>>>>>>>>>>>>>
6096 23:09:38.084236 <<<<<< [CONFIGURE PHASE]: ANA_TX
6097 23:09:38.088046 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6098 23:09:38.091111 ===================================
6099 23:09:38.094232 data_rate = 800,PCW = 0X7400
6100 23:09:38.097718 ===================================
6101 23:09:38.101056 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6102 23:09:38.103987 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6103 23:09:38.117522 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6104 23:09:38.120377 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6105 23:09:38.123774 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6106 23:09:38.127242 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6107 23:09:38.130323 [ANA_INIT] flow start
6108 23:09:38.133832 [ANA_INIT] PLL >>>>>>>>
6109 23:09:38.134345 [ANA_INIT] PLL <<<<<<<<
6110 23:09:38.136902 [ANA_INIT] MIDPI >>>>>>>>
6111 23:09:38.140778 [ANA_INIT] MIDPI <<<<<<<<
6112 23:09:38.141229 [ANA_INIT] DLL >>>>>>>>
6113 23:09:38.143929 [ANA_INIT] flow end
6114 23:09:38.147201 ============ LP4 DIFF to SE enter ============
6115 23:09:38.153633 ============ LP4 DIFF to SE exit ============
6116 23:09:38.154088 [ANA_INIT] <<<<<<<<<<<<<
6117 23:09:38.156669 [Flow] Enable top DCM control >>>>>
6118 23:09:38.160182 [Flow] Enable top DCM control <<<<<
6119 23:09:38.163601 Enable DLL master slave shuffle
6120 23:09:38.170345 ==============================================================
6121 23:09:38.170842 Gating Mode config
6122 23:09:38.176773 ==============================================================
6123 23:09:38.179992 Config description:
6124 23:09:38.189956 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6125 23:09:38.196749 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6126 23:09:38.199897 SELPH_MODE 0: By rank 1: By Phase
6127 23:09:38.206295 ==============================================================
6128 23:09:38.210114 GAT_TRACK_EN = 0
6129 23:09:38.210531 RX_GATING_MODE = 2
6130 23:09:38.212957 RX_GATING_TRACK_MODE = 2
6131 23:09:38.216668 SELPH_MODE = 1
6132 23:09:38.220147 PICG_EARLY_EN = 1
6133 23:09:38.222974 VALID_LAT_VALUE = 1
6134 23:09:38.229878 ==============================================================
6135 23:09:38.233191 Enter into Gating configuration >>>>
6136 23:09:38.236601 Exit from Gating configuration <<<<
6137 23:09:38.239524 Enter into DVFS_PRE_config >>>>>
6138 23:09:38.249468 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6139 23:09:38.252918 Exit from DVFS_PRE_config <<<<<
6140 23:09:38.255707 Enter into PICG configuration >>>>
6141 23:09:38.259280 Exit from PICG configuration <<<<
6142 23:09:38.262666 [RX_INPUT] configuration >>>>>
6143 23:09:38.266023 [RX_INPUT] configuration <<<<<
6144 23:09:38.269294 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6145 23:09:38.275934 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6146 23:09:38.282601 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6147 23:09:38.289277 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6148 23:09:38.292202 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6149 23:09:38.299090 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6150 23:09:38.302756 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6151 23:09:38.309079 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6152 23:09:38.312408 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6153 23:09:38.315983 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6154 23:09:38.318812 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6155 23:09:38.325244 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6156 23:09:38.328787 ===================================
6157 23:09:38.328938 LPDDR4 DRAM CONFIGURATION
6158 23:09:38.332202 ===================================
6159 23:09:38.335528 EX_ROW_EN[0] = 0x0
6160 23:09:38.339068 EX_ROW_EN[1] = 0x0
6161 23:09:38.339215 LP4Y_EN = 0x0
6162 23:09:38.342355 WORK_FSP = 0x0
6163 23:09:38.342504 WL = 0x2
6164 23:09:38.345590 RL = 0x2
6165 23:09:38.345738 BL = 0x2
6166 23:09:38.348683 RPST = 0x0
6167 23:09:38.348830 RD_PRE = 0x0
6168 23:09:38.352339 WR_PRE = 0x1
6169 23:09:38.352487 WR_PST = 0x0
6170 23:09:38.355320 DBI_WR = 0x0
6171 23:09:38.355467 DBI_RD = 0x0
6172 23:09:38.358757 OTF = 0x1
6173 23:09:38.362242 ===================================
6174 23:09:38.365100 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6175 23:09:38.368699 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6176 23:09:38.374833 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6177 23:09:38.378450 ===================================
6178 23:09:38.378530 LPDDR4 DRAM CONFIGURATION
6179 23:09:38.381761 ===================================
6180 23:09:38.385398 EX_ROW_EN[0] = 0x10
6181 23:09:38.388301 EX_ROW_EN[1] = 0x0
6182 23:09:38.388381 LP4Y_EN = 0x0
6183 23:09:38.391830 WORK_FSP = 0x0
6184 23:09:38.391909 WL = 0x2
6185 23:09:38.395302 RL = 0x2
6186 23:09:38.395381 BL = 0x2
6187 23:09:38.398193 RPST = 0x0
6188 23:09:38.398272 RD_PRE = 0x0
6189 23:09:38.401766 WR_PRE = 0x1
6190 23:09:38.401845 WR_PST = 0x0
6191 23:09:38.405137 DBI_WR = 0x0
6192 23:09:38.405215 DBI_RD = 0x0
6193 23:09:38.408224 OTF = 0x1
6194 23:09:38.411717 ===================================
6195 23:09:38.418497 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6196 23:09:38.421419 nWR fixed to 30
6197 23:09:38.421498 [ModeRegInit_LP4] CH0 RK0
6198 23:09:38.425168 [ModeRegInit_LP4] CH0 RK1
6199 23:09:38.427945 [ModeRegInit_LP4] CH1 RK0
6200 23:09:38.431595 [ModeRegInit_LP4] CH1 RK1
6201 23:09:38.431674 match AC timing 19
6202 23:09:38.437912 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6203 23:09:38.441455 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6204 23:09:38.445099 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6205 23:09:38.451303 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6206 23:09:38.454592 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6207 23:09:38.454672 ==
6208 23:09:38.458216 Dram Type= 6, Freq= 0, CH_0, rank 0
6209 23:09:38.461097 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6210 23:09:38.461177 ==
6211 23:09:38.467979 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6212 23:09:38.474583 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6213 23:09:38.478256 [CA 0] Center 36 (8~64) winsize 57
6214 23:09:38.481016 [CA 1] Center 36 (8~64) winsize 57
6215 23:09:38.481096 [CA 2] Center 36 (8~64) winsize 57
6216 23:09:38.484879 [CA 3] Center 36 (8~64) winsize 57
6217 23:09:38.488216 [CA 4] Center 36 (8~64) winsize 57
6218 23:09:38.491029 [CA 5] Center 36 (8~64) winsize 57
6219 23:09:38.491109
6220 23:09:38.494470 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6221 23:09:38.494575
6222 23:09:38.501360 [CATrainingPosCal] consider 1 rank data
6223 23:09:38.501443 u2DelayCellTimex100 = 270/100 ps
6224 23:09:38.504743 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6225 23:09:38.510988 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6226 23:09:38.514521 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6227 23:09:38.517520 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6228 23:09:38.520972 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6229 23:09:38.524673 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6230 23:09:38.524753
6231 23:09:38.528304 CA PerBit enable=1, Macro0, CA PI delay=36
6232 23:09:38.528384
6233 23:09:38.531223 [CBTSetCACLKResult] CA Dly = 36
6234 23:09:38.531303 CS Dly: 1 (0~32)
6235 23:09:38.534785 ==
6236 23:09:38.537823 Dram Type= 6, Freq= 0, CH_0, rank 1
6237 23:09:38.541422 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6238 23:09:38.541502 ==
6239 23:09:38.547959 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6240 23:09:38.550847 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6241 23:09:38.554521 [CA 0] Center 36 (8~64) winsize 57
6242 23:09:38.557414 [CA 1] Center 36 (8~64) winsize 57
6243 23:09:38.561169 [CA 2] Center 36 (8~64) winsize 57
6244 23:09:38.564439 [CA 3] Center 36 (8~64) winsize 57
6245 23:09:38.567586 [CA 4] Center 36 (8~64) winsize 57
6246 23:09:38.570831 [CA 5] Center 36 (8~64) winsize 57
6247 23:09:38.570912
6248 23:09:38.574540 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6249 23:09:38.574620
6250 23:09:38.577536 [CATrainingPosCal] consider 2 rank data
6251 23:09:38.580947 u2DelayCellTimex100 = 270/100 ps
6252 23:09:38.584531 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6253 23:09:38.587352 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6254 23:09:38.590904 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6255 23:09:38.594381 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6256 23:09:38.601230 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6257 23:09:38.604533 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6258 23:09:38.604613
6259 23:09:38.607442 CA PerBit enable=1, Macro0, CA PI delay=36
6260 23:09:38.607520
6261 23:09:38.610683 [CBTSetCACLKResult] CA Dly = 36
6262 23:09:38.610762 CS Dly: 1 (0~32)
6263 23:09:38.610825
6264 23:09:38.614337 ----->DramcWriteLeveling(PI) begin...
6265 23:09:38.614417 ==
6266 23:09:38.617712 Dram Type= 6, Freq= 0, CH_0, rank 0
6267 23:09:38.624009 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6268 23:09:38.624089 ==
6269 23:09:38.627568 Write leveling (Byte 0): 40 => 8
6270 23:09:38.627648 Write leveling (Byte 1): 40 => 8
6271 23:09:38.630997 DramcWriteLeveling(PI) end<-----
6272 23:09:38.631078
6273 23:09:38.631141 ==
6274 23:09:38.633980 Dram Type= 6, Freq= 0, CH_0, rank 0
6275 23:09:38.640589 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6276 23:09:38.640670 ==
6277 23:09:38.644014 [Gating] SW mode calibration
6278 23:09:38.650519 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6279 23:09:38.654066 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6280 23:09:38.660658 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6281 23:09:38.664213 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6282 23:09:38.667160 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6283 23:09:38.674003 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6284 23:09:38.677186 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6285 23:09:38.680823 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6286 23:09:38.687323 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6287 23:09:38.690345 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6288 23:09:38.693749 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6289 23:09:38.697540 Total UI for P1: 0, mck2ui 16
6290 23:09:38.700377 best dqsien dly found for B0: ( 0, 14, 24)
6291 23:09:38.703943 Total UI for P1: 0, mck2ui 16
6292 23:09:38.706802 best dqsien dly found for B1: ( 0, 14, 24)
6293 23:09:38.710250 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6294 23:09:38.713347 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6295 23:09:38.713426
6296 23:09:38.720333 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6297 23:09:38.723685 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6298 23:09:38.723766 [Gating] SW calibration Done
6299 23:09:38.726930 ==
6300 23:09:38.730331 Dram Type= 6, Freq= 0, CH_0, rank 0
6301 23:09:38.733495 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6302 23:09:38.733582 ==
6303 23:09:38.733675 RX Vref Scan: 0
6304 23:09:38.733733
6305 23:09:38.736705 RX Vref 0 -> 0, step: 1
6306 23:09:38.736785
6307 23:09:38.740157 RX Delay -410 -> 252, step: 16
6308 23:09:38.743241 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6309 23:09:38.746948 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6310 23:09:38.753445 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6311 23:09:38.756874 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6312 23:09:38.759936 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6313 23:09:38.762971 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6314 23:09:38.770130 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6315 23:09:38.773038 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6316 23:09:38.776589 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6317 23:09:38.780075 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6318 23:09:38.786617 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6319 23:09:38.790124 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6320 23:09:38.793552 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6321 23:09:38.799827 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6322 23:09:38.803452 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6323 23:09:38.806224 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6324 23:09:38.806303 ==
6325 23:09:38.809704 Dram Type= 6, Freq= 0, CH_0, rank 0
6326 23:09:38.813244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6327 23:09:38.813324 ==
6328 23:09:38.816729 DQS Delay:
6329 23:09:38.816807 DQS0 = 27, DQS1 = 35
6330 23:09:38.819663 DQM Delay:
6331 23:09:38.819741 DQM0 = 10, DQM1 = 11
6332 23:09:38.823164 DQ Delay:
6333 23:09:38.823242 DQ0 =8, DQ1 =16, DQ2 =0, DQ3 =8
6334 23:09:38.826077 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =24
6335 23:09:38.829315 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6336 23:09:38.832844 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6337 23:09:38.832923
6338 23:09:38.832985
6339 23:09:38.833044 ==
6340 23:09:38.836338 Dram Type= 6, Freq= 0, CH_0, rank 0
6341 23:09:38.842661 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6342 23:09:38.842798 ==
6343 23:09:38.842890
6344 23:09:38.842977
6345 23:09:38.843061 TX Vref Scan disable
6346 23:09:38.845847 == TX Byte 0 ==
6347 23:09:38.849336 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6348 23:09:38.853092 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6349 23:09:38.855945 == TX Byte 1 ==
6350 23:09:38.859480 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6351 23:09:38.862938 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6352 23:09:38.863018 ==
6353 23:09:38.865986 Dram Type= 6, Freq= 0, CH_0, rank 0
6354 23:09:38.872599 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6355 23:09:38.872679 ==
6356 23:09:38.872742
6357 23:09:38.872799
6358 23:09:38.876026 TX Vref Scan disable
6359 23:09:38.876105 == TX Byte 0 ==
6360 23:09:38.879090 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6361 23:09:38.886069 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6362 23:09:38.886148 == TX Byte 1 ==
6363 23:09:38.888998 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6364 23:09:38.892512 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6365 23:09:38.896003
6366 23:09:38.896084 [DATLAT]
6367 23:09:38.896147 Freq=400, CH0 RK0
6368 23:09:38.896205
6369 23:09:38.898924 DATLAT Default: 0xf
6370 23:09:38.899003 0, 0xFFFF, sum = 0
6371 23:09:38.902345 1, 0xFFFF, sum = 0
6372 23:09:38.902426 2, 0xFFFF, sum = 0
6373 23:09:38.905936 3, 0xFFFF, sum = 0
6374 23:09:38.906016 4, 0xFFFF, sum = 0
6375 23:09:38.909453 5, 0xFFFF, sum = 0
6376 23:09:38.909533 6, 0xFFFF, sum = 0
6377 23:09:38.912604 7, 0xFFFF, sum = 0
6378 23:09:38.915724 8, 0xFFFF, sum = 0
6379 23:09:38.915805 9, 0xFFFF, sum = 0
6380 23:09:38.919101 10, 0xFFFF, sum = 0
6381 23:09:38.919181 11, 0xFFFF, sum = 0
6382 23:09:38.922395 12, 0xFFFF, sum = 0
6383 23:09:38.922476 13, 0x0, sum = 1
6384 23:09:38.925976 14, 0x0, sum = 2
6385 23:09:38.926060 15, 0x0, sum = 3
6386 23:09:38.929105 16, 0x0, sum = 4
6387 23:09:38.929187 best_step = 14
6388 23:09:38.929250
6389 23:09:38.929308 ==
6390 23:09:38.932588 Dram Type= 6, Freq= 0, CH_0, rank 0
6391 23:09:38.935846 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6392 23:09:38.935930 ==
6393 23:09:38.939118 RX Vref Scan: 1
6394 23:09:38.939197
6395 23:09:38.942623 RX Vref 0 -> 0, step: 1
6396 23:09:38.942703
6397 23:09:38.942765 RX Delay -311 -> 252, step: 8
6398 23:09:38.942823
6399 23:09:38.945567 Set Vref, RX VrefLevel [Byte0]: 53
6400 23:09:38.948982 [Byte1]: 46
6401 23:09:38.954699
6402 23:09:38.954778 Final RX Vref Byte 0 = 53 to rank0
6403 23:09:38.957533 Final RX Vref Byte 1 = 46 to rank0
6404 23:09:38.960982 Final RX Vref Byte 0 = 53 to rank1
6405 23:09:38.964584 Final RX Vref Byte 1 = 46 to rank1==
6406 23:09:38.967615 Dram Type= 6, Freq= 0, CH_0, rank 0
6407 23:09:38.974154 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6408 23:09:38.974311 ==
6409 23:09:38.974400 DQS Delay:
6410 23:09:38.977771 DQS0 = 28, DQS1 = 36
6411 23:09:38.977879 DQM Delay:
6412 23:09:38.977973 DQM0 = 10, DQM1 = 12
6413 23:09:38.980787 DQ Delay:
6414 23:09:38.984262 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =8
6415 23:09:38.984382 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6416 23:09:38.987830 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6417 23:09:38.990822 DQ12 =16, DQ13 =20, DQ14 =24, DQ15 =20
6418 23:09:38.990981
6419 23:09:38.994492
6420 23:09:39.000564 [DQSOSCAuto] RK0, (LSB)MR18= 0xc8b4, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 385 ps
6421 23:09:39.004118 CH0 RK0: MR19=C0C, MR18=C8B4
6422 23:09:39.010723 CH0_RK0: MR19=0xC0C, MR18=0xC8B4, DQSOSC=385, MR23=63, INC=398, DEC=265
6423 23:09:39.011027 ==
6424 23:09:39.014229 Dram Type= 6, Freq= 0, CH_0, rank 1
6425 23:09:39.017743 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6426 23:09:39.018062 ==
6427 23:09:39.020698 [Gating] SW mode calibration
6428 23:09:39.027447 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6429 23:09:39.034268 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6430 23:09:39.037348 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6431 23:09:39.040855 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6432 23:09:39.047487 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6433 23:09:39.050388 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6434 23:09:39.053825 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6435 23:09:39.057041 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6436 23:09:39.063771 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6437 23:09:39.067197 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6438 23:09:39.070390 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6439 23:09:39.073961 Total UI for P1: 0, mck2ui 16
6440 23:09:39.076908 best dqsien dly found for B0: ( 0, 14, 24)
6441 23:09:39.080421 Total UI for P1: 0, mck2ui 16
6442 23:09:39.083602 best dqsien dly found for B1: ( 0, 14, 24)
6443 23:09:39.087126 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6444 23:09:39.093879 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6445 23:09:39.093968
6446 23:09:39.096818 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6447 23:09:39.100272 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6448 23:09:39.103795 [Gating] SW calibration Done
6449 23:09:39.103871 ==
6450 23:09:39.106905 Dram Type= 6, Freq= 0, CH_0, rank 1
6451 23:09:39.110493 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6452 23:09:39.110573 ==
6453 23:09:39.113140 RX Vref Scan: 0
6454 23:09:39.113219
6455 23:09:39.113280 RX Vref 0 -> 0, step: 1
6456 23:09:39.113345
6457 23:09:39.116929 RX Delay -410 -> 252, step: 16
6458 23:09:39.120201 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6459 23:09:39.126922 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6460 23:09:39.130001 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6461 23:09:39.133384 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6462 23:09:39.136351 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6463 23:09:39.143505 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6464 23:09:39.146346 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6465 23:09:39.149733 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6466 23:09:39.153071 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6467 23:09:39.159631 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6468 23:09:39.163268 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6469 23:09:39.166479 iDelay=230, Bit 11, Center -27 (-250 ~ 197) 448
6470 23:09:39.169945 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6471 23:09:39.176586 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6472 23:09:39.179532 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6473 23:09:39.182836 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6474 23:09:39.182917 ==
6475 23:09:39.186145 Dram Type= 6, Freq= 0, CH_0, rank 1
6476 23:09:39.192812 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6477 23:09:39.192897 ==
6478 23:09:39.192961 DQS Delay:
6479 23:09:39.196452 DQS0 = 27, DQS1 = 35
6480 23:09:39.196531 DQM Delay:
6481 23:09:39.196595 DQM0 = 12, DQM1 = 12
6482 23:09:39.199346 DQ Delay:
6483 23:09:39.202999 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6484 23:09:39.205888 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6485 23:09:39.205968 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6486 23:09:39.209353 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6487 23:09:39.212479
6488 23:09:39.212564
6489 23:09:39.212628 ==
6490 23:09:39.216034 Dram Type= 6, Freq= 0, CH_0, rank 1
6491 23:09:39.219660 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6492 23:09:39.219744 ==
6493 23:09:39.219809
6494 23:09:39.219867
6495 23:09:39.222503 TX Vref Scan disable
6496 23:09:39.222584 == TX Byte 0 ==
6497 23:09:39.225874 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6498 23:09:39.232527 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6499 23:09:39.232615 == TX Byte 1 ==
6500 23:09:39.236103 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6501 23:09:39.242414 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6502 23:09:39.242503 ==
6503 23:09:39.246112 Dram Type= 6, Freq= 0, CH_0, rank 1
6504 23:09:39.249031 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6505 23:09:39.249117 ==
6506 23:09:39.249179
6507 23:09:39.249238
6508 23:09:39.252713 TX Vref Scan disable
6509 23:09:39.252788 == TX Byte 0 ==
6510 23:09:39.256165 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6511 23:09:39.262314 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6512 23:09:39.262406 == TX Byte 1 ==
6513 23:09:39.266050 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6514 23:09:39.272532 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6515 23:09:39.272611
6516 23:09:39.272699 [DATLAT]
6517 23:09:39.272775 Freq=400, CH0 RK1
6518 23:09:39.275905
6519 23:09:39.275977 DATLAT Default: 0xe
6520 23:09:39.278913 0, 0xFFFF, sum = 0
6521 23:09:39.278987 1, 0xFFFF, sum = 0
6522 23:09:39.282388 2, 0xFFFF, sum = 0
6523 23:09:39.282461 3, 0xFFFF, sum = 0
6524 23:09:39.285729 4, 0xFFFF, sum = 0
6525 23:09:39.285803 5, 0xFFFF, sum = 0
6526 23:09:39.289176 6, 0xFFFF, sum = 0
6527 23:09:39.289278 7, 0xFFFF, sum = 0
6528 23:09:39.292143 8, 0xFFFF, sum = 0
6529 23:09:39.292228 9, 0xFFFF, sum = 0
6530 23:09:39.295765 10, 0xFFFF, sum = 0
6531 23:09:39.295855 11, 0xFFFF, sum = 0
6532 23:09:39.299025 12, 0xFFFF, sum = 0
6533 23:09:39.299116 13, 0x0, sum = 1
6534 23:09:39.302172 14, 0x0, sum = 2
6535 23:09:39.302268 15, 0x0, sum = 3
6536 23:09:39.305694 16, 0x0, sum = 4
6537 23:09:39.305799 best_step = 14
6538 23:09:39.305903
6539 23:09:39.306002 ==
6540 23:09:39.308833 Dram Type= 6, Freq= 0, CH_0, rank 1
6541 23:09:39.315519 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6542 23:09:39.315645 ==
6543 23:09:39.315779 RX Vref Scan: 0
6544 23:09:39.315900
6545 23:09:39.319437 RX Vref 0 -> 0, step: 1
6546 23:09:39.319598
6547 23:09:39.322151 RX Delay -311 -> 252, step: 8
6548 23:09:39.328808 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6549 23:09:39.332105 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6550 23:09:39.335971 iDelay=217, Bit 2, Center -20 (-247 ~ 208) 456
6551 23:09:39.338902 iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448
6552 23:09:39.345992 iDelay=217, Bit 4, Center -12 (-239 ~ 216) 456
6553 23:09:39.348625 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6554 23:09:39.352605 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6555 23:09:39.355441 iDelay=217, Bit 7, Center -4 (-223 ~ 216) 440
6556 23:09:39.362483 iDelay=217, Bit 8, Center -36 (-255 ~ 184) 440
6557 23:09:39.365477 iDelay=217, Bit 9, Center -36 (-255 ~ 184) 440
6558 23:09:39.368661 iDelay=217, Bit 10, Center -20 (-239 ~ 200) 440
6559 23:09:39.372082 iDelay=217, Bit 11, Center -28 (-247 ~ 192) 440
6560 23:09:39.378540 iDelay=217, Bit 12, Center -20 (-239 ~ 200) 440
6561 23:09:39.381964 iDelay=217, Bit 13, Center -20 (-239 ~ 200) 440
6562 23:09:39.384908 iDelay=217, Bit 14, Center -12 (-231 ~ 208) 440
6563 23:09:39.388671 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6564 23:09:39.391712 ==
6565 23:09:39.391789 Dram Type= 6, Freq= 0, CH_0, rank 1
6566 23:09:39.398362 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6567 23:09:39.398446 ==
6568 23:09:39.398508 DQS Delay:
6569 23:09:39.401963 DQS0 = 24, DQS1 = 36
6570 23:09:39.402034 DQM Delay:
6571 23:09:39.405064 DQM0 = 9, DQM1 = 12
6572 23:09:39.405134 DQ Delay:
6573 23:09:39.408403 DQ0 =8, DQ1 =8, DQ2 =4, DQ3 =8
6574 23:09:39.412028 DQ4 =12, DQ5 =0, DQ6 =12, DQ7 =20
6575 23:09:39.412105 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6576 23:09:39.415613 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6577 23:09:39.418235
6578 23:09:39.418323
6579 23:09:39.425410 [DQSOSCAuto] RK1, (LSB)MR18= 0xb859, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 386 ps
6580 23:09:39.428807 CH0 RK1: MR19=C0C, MR18=B859
6581 23:09:39.435355 CH0_RK1: MR19=0xC0C, MR18=0xB859, DQSOSC=386, MR23=63, INC=396, DEC=264
6582 23:09:39.438403 [RxdqsGatingPostProcess] freq 400
6583 23:09:39.441491 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6584 23:09:39.444728 best DQS0 dly(2T, 0.5T) = (0, 10)
6585 23:09:39.447886 best DQS1 dly(2T, 0.5T) = (0, 10)
6586 23:09:39.451329 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6587 23:09:39.454794 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6588 23:09:39.458387 best DQS0 dly(2T, 0.5T) = (0, 10)
6589 23:09:39.461276 best DQS1 dly(2T, 0.5T) = (0, 10)
6590 23:09:39.464927 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6591 23:09:39.467844 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6592 23:09:39.471259 Pre-setting of DQS Precalculation
6593 23:09:39.474796 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6594 23:09:39.474864 ==
6595 23:09:39.478002 Dram Type= 6, Freq= 0, CH_1, rank 0
6596 23:09:39.484713 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6597 23:09:39.484787 ==
6598 23:09:39.488128 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6599 23:09:39.494946 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6600 23:09:39.497852 [CA 0] Center 36 (8~64) winsize 57
6601 23:09:39.501395 [CA 1] Center 36 (8~64) winsize 57
6602 23:09:39.504535 [CA 2] Center 36 (8~64) winsize 57
6603 23:09:39.507879 [CA 3] Center 36 (8~64) winsize 57
6604 23:09:39.511410 [CA 4] Center 36 (8~64) winsize 57
6605 23:09:39.514290 [CA 5] Center 36 (8~64) winsize 57
6606 23:09:39.514365
6607 23:09:39.518082 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6608 23:09:39.518156
6609 23:09:39.520971 [CATrainingPosCal] consider 1 rank data
6610 23:09:39.524412 u2DelayCellTimex100 = 270/100 ps
6611 23:09:39.527934 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6612 23:09:39.530982 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6613 23:09:39.534541 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6614 23:09:39.537818 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6615 23:09:39.541066 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6616 23:09:39.544712 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6617 23:09:39.547765
6618 23:09:39.551154 CA PerBit enable=1, Macro0, CA PI delay=36
6619 23:09:39.551230
6620 23:09:39.554353 [CBTSetCACLKResult] CA Dly = 36
6621 23:09:39.554436 CS Dly: 1 (0~32)
6622 23:09:39.554524 ==
6623 23:09:39.557903 Dram Type= 6, Freq= 0, CH_1, rank 1
6624 23:09:39.561493 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6625 23:09:39.561584 ==
6626 23:09:39.568042 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6627 23:09:39.574646 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6628 23:09:39.577651 [CA 0] Center 36 (8~64) winsize 57
6629 23:09:39.581263 [CA 1] Center 36 (8~64) winsize 57
6630 23:09:39.584077 [CA 2] Center 36 (8~64) winsize 57
6631 23:09:39.587938 [CA 3] Center 36 (8~64) winsize 57
6632 23:09:39.591325 [CA 4] Center 36 (8~64) winsize 57
6633 23:09:39.591402 [CA 5] Center 36 (8~64) winsize 57
6634 23:09:39.594403
6635 23:09:39.597314 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6636 23:09:39.597388
6637 23:09:39.601069 [CATrainingPosCal] consider 2 rank data
6638 23:09:39.604134 u2DelayCellTimex100 = 270/100 ps
6639 23:09:39.607879 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6640 23:09:39.610690 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6641 23:09:39.614383 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6642 23:09:39.617331 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6643 23:09:39.620956 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6644 23:09:39.623825 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6645 23:09:39.623912
6646 23:09:39.627348 CA PerBit enable=1, Macro0, CA PI delay=36
6647 23:09:39.627422
6648 23:09:39.630363 [CBTSetCACLKResult] CA Dly = 36
6649 23:09:39.633951 CS Dly: 1 (0~32)
6650 23:09:39.634021
6651 23:09:39.636932 ----->DramcWriteLeveling(PI) begin...
6652 23:09:39.637039 ==
6653 23:09:39.640480 Dram Type= 6, Freq= 0, CH_1, rank 0
6654 23:09:39.644056 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6655 23:09:39.644142 ==
6656 23:09:39.647264 Write leveling (Byte 0): 40 => 8
6657 23:09:39.650976 Write leveling (Byte 1): 40 => 8
6658 23:09:39.654369 DramcWriteLeveling(PI) end<-----
6659 23:09:39.654921
6660 23:09:39.655512 ==
6661 23:09:39.657805 Dram Type= 6, Freq= 0, CH_1, rank 0
6662 23:09:39.660909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6663 23:09:39.661643 ==
6664 23:09:39.664065 [Gating] SW mode calibration
6665 23:09:39.670681 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6666 23:09:39.677657 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6667 23:09:39.680500 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6668 23:09:39.687764 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6669 23:09:39.690764 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6670 23:09:39.693994 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6671 23:09:39.700692 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6672 23:09:39.703844 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6673 23:09:39.707328 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6674 23:09:39.710702 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6675 23:09:39.717226 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6676 23:09:39.720604 Total UI for P1: 0, mck2ui 16
6677 23:09:39.723648 best dqsien dly found for B0: ( 0, 14, 24)
6678 23:09:39.726944 Total UI for P1: 0, mck2ui 16
6679 23:09:39.730745 best dqsien dly found for B1: ( 0, 14, 24)
6680 23:09:39.733803 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6681 23:09:39.737132 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6682 23:09:39.737283
6683 23:09:39.740143 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6684 23:09:39.743642 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6685 23:09:39.746759 [Gating] SW calibration Done
6686 23:09:39.746874 ==
6687 23:09:39.750483 Dram Type= 6, Freq= 0, CH_1, rank 0
6688 23:09:39.753492 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6689 23:09:39.753607 ==
6690 23:09:39.756997 RX Vref Scan: 0
6691 23:09:39.757088
6692 23:09:39.759935 RX Vref 0 -> 0, step: 1
6693 23:09:39.760018
6694 23:09:39.760083 RX Delay -410 -> 252, step: 16
6695 23:09:39.766928 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6696 23:09:39.770447 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6697 23:09:39.773359 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6698 23:09:39.777023 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6699 23:09:39.783503 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6700 23:09:39.787048 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6701 23:09:39.789952 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6702 23:09:39.793509 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6703 23:09:39.800587 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6704 23:09:39.803358 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6705 23:09:39.806645 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6706 23:09:39.810325 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6707 23:09:39.817099 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6708 23:09:39.820059 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6709 23:09:39.823573 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6710 23:09:39.829939 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6711 23:09:39.830237 ==
6712 23:09:39.833704 Dram Type= 6, Freq= 0, CH_1, rank 0
6713 23:09:39.837271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6714 23:09:39.837696 ==
6715 23:09:39.838095 DQS Delay:
6716 23:09:39.840327 DQS0 = 35, DQS1 = 35
6717 23:09:39.840767 DQM Delay:
6718 23:09:39.844006 DQM0 = 17, DQM1 = 12
6719 23:09:39.844439 DQ Delay:
6720 23:09:39.846772 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =16
6721 23:09:39.850384 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6722 23:09:39.853979 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6723 23:09:39.856932 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =16
6724 23:09:39.857328
6725 23:09:39.857928
6726 23:09:39.858301 ==
6727 23:09:39.860295 Dram Type= 6, Freq= 0, CH_1, rank 0
6728 23:09:39.863508 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6729 23:09:39.863987 ==
6730 23:09:39.864506
6731 23:09:39.864903
6732 23:09:39.866993 TX Vref Scan disable
6733 23:09:39.867437 == TX Byte 0 ==
6734 23:09:39.873408 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6735 23:09:39.876634 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6736 23:09:39.877031 == TX Byte 1 ==
6737 23:09:39.883879 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6738 23:09:39.886857 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6739 23:09:39.887256 ==
6740 23:09:39.890486 Dram Type= 6, Freq= 0, CH_1, rank 0
6741 23:09:39.893345 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6742 23:09:39.893854 ==
6743 23:09:39.894261
6744 23:09:39.894639
6745 23:09:39.897164 TX Vref Scan disable
6746 23:09:39.897562 == TX Byte 0 ==
6747 23:09:39.903351 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6748 23:09:39.906337 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6749 23:09:39.906741 == TX Byte 1 ==
6750 23:09:39.913224 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6751 23:09:39.916660 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6752 23:09:39.917067
6753 23:09:39.917373 [DATLAT]
6754 23:09:39.919789 Freq=400, CH1 RK0
6755 23:09:39.920170
6756 23:09:39.920469 DATLAT Default: 0xf
6757 23:09:39.923352 0, 0xFFFF, sum = 0
6758 23:09:39.923901 1, 0xFFFF, sum = 0
6759 23:09:39.926471 2, 0xFFFF, sum = 0
6760 23:09:39.926805 3, 0xFFFF, sum = 0
6761 23:09:39.929483 4, 0xFFFF, sum = 0
6762 23:09:39.929885 5, 0xFFFF, sum = 0
6763 23:09:39.932889 6, 0xFFFF, sum = 0
6764 23:09:39.936432 7, 0xFFFF, sum = 0
6765 23:09:39.936652 8, 0xFFFF, sum = 0
6766 23:09:39.939895 9, 0xFFFF, sum = 0
6767 23:09:39.940040 10, 0xFFFF, sum = 0
6768 23:09:39.942797 11, 0xFFFF, sum = 0
6769 23:09:39.942991 12, 0xFFFF, sum = 0
6770 23:09:39.946294 13, 0x0, sum = 1
6771 23:09:39.946487 14, 0x0, sum = 2
6772 23:09:39.949190 15, 0x0, sum = 3
6773 23:09:39.949390 16, 0x0, sum = 4
6774 23:09:39.953013 best_step = 14
6775 23:09:39.953154
6776 23:09:39.953266 ==
6777 23:09:39.956141 Dram Type= 6, Freq= 0, CH_1, rank 0
6778 23:09:39.959668 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6779 23:09:39.959874 ==
6780 23:09:39.959992 RX Vref Scan: 1
6781 23:09:39.960096
6782 23:09:39.962658 RX Vref 0 -> 0, step: 1
6783 23:09:39.962855
6784 23:09:39.966405 RX Delay -311 -> 252, step: 8
6785 23:09:39.966614
6786 23:09:39.969181 Set Vref, RX VrefLevel [Byte0]: 53
6787 23:09:39.973050 [Byte1]: 47
6788 23:09:39.976406
6789 23:09:39.976634 Final RX Vref Byte 0 = 53 to rank0
6790 23:09:39.980082 Final RX Vref Byte 1 = 47 to rank0
6791 23:09:39.983425 Final RX Vref Byte 0 = 53 to rank1
6792 23:09:39.986623 Final RX Vref Byte 1 = 47 to rank1==
6793 23:09:39.989697 Dram Type= 6, Freq= 0, CH_1, rank 0
6794 23:09:39.996897 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6795 23:09:39.997316 ==
6796 23:09:39.997627 DQS Delay:
6797 23:09:40.000040 DQS0 = 32, DQS1 = 32
6798 23:09:40.000479 DQM Delay:
6799 23:09:40.000809 DQM0 = 14, DQM1 = 11
6800 23:09:40.003598 DQ Delay:
6801 23:09:40.006721 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =16
6802 23:09:40.010334 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =12
6803 23:09:40.010750 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6804 23:09:40.013030 DQ12 =20, DQ13 =20, DQ14 =16, DQ15 =20
6805 23:09:40.016627
6806 23:09:40.017115
6807 23:09:40.023399 [DQSOSCAuto] RK0, (LSB)MR18= 0x8bc4, (MSB)MR19= 0xc0c, tDQSOscB0 = 385 ps tDQSOscB1 = 392 ps
6808 23:09:40.026789 CH1 RK0: MR19=C0C, MR18=8BC4
6809 23:09:40.033051 CH1_RK0: MR19=0xC0C, MR18=0x8BC4, DQSOSC=385, MR23=63, INC=398, DEC=265
6810 23:09:40.033535 ==
6811 23:09:40.036391 Dram Type= 6, Freq= 0, CH_1, rank 1
6812 23:09:40.039463 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6813 23:09:40.040081 ==
6814 23:09:40.042881 [Gating] SW mode calibration
6815 23:09:40.049399 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6816 23:09:40.056393 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6817 23:09:40.060040 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6818 23:09:40.062832 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6819 23:09:40.069280 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6820 23:09:40.072848 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6821 23:09:40.076391 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6822 23:09:40.083024 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6823 23:09:40.086099 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6824 23:09:40.089759 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6825 23:09:40.095801 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6826 23:09:40.096282 Total UI for P1: 0, mck2ui 16
6827 23:09:40.102583 best dqsien dly found for B0: ( 0, 14, 24)
6828 23:09:40.103025 Total UI for P1: 0, mck2ui 16
6829 23:09:40.106380 best dqsien dly found for B1: ( 0, 14, 24)
6830 23:09:40.112739 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6831 23:09:40.115764 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6832 23:09:40.116268
6833 23:09:40.119280 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6834 23:09:40.122629 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6835 23:09:40.125644 [Gating] SW calibration Done
6836 23:09:40.126057 ==
6837 23:09:40.129107 Dram Type= 6, Freq= 0, CH_1, rank 1
6838 23:09:40.132377 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6839 23:09:40.132957 ==
6840 23:09:40.135618 RX Vref Scan: 0
6841 23:09:40.136205
6842 23:09:40.136807 RX Vref 0 -> 0, step: 1
6843 23:09:40.137217
6844 23:09:40.139067 RX Delay -410 -> 252, step: 16
6845 23:09:40.145752 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6846 23:09:40.149164 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6847 23:09:40.152383 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6848 23:09:40.155717 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6849 23:09:40.162183 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6850 23:09:40.165858 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6851 23:09:40.168769 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6852 23:09:40.172053 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6853 23:09:40.175394 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6854 23:09:40.182306 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6855 23:09:40.185374 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6856 23:09:40.188829 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6857 23:09:40.195432 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6858 23:09:40.198347 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6859 23:09:40.202028 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6860 23:09:40.205241 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6861 23:09:40.208662 ==
6862 23:09:40.209176 Dram Type= 6, Freq= 0, CH_1, rank 1
6863 23:09:40.215488 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6864 23:09:40.215904 ==
6865 23:09:40.216266 DQS Delay:
6866 23:09:40.218367 DQS0 = 35, DQS1 = 35
6867 23:09:40.218775 DQM Delay:
6868 23:09:40.221995 DQM0 = 18, DQM1 = 13
6869 23:09:40.222402 DQ Delay:
6870 23:09:40.225439 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6871 23:09:40.228980 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6872 23:09:40.231863 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6873 23:09:40.235063 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6874 23:09:40.235513
6875 23:09:40.235837
6876 23:09:40.236159 ==
6877 23:09:40.238563 Dram Type= 6, Freq= 0, CH_1, rank 1
6878 23:09:40.242049 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6879 23:09:40.242465 ==
6880 23:09:40.242808
6881 23:09:40.243117
6882 23:09:40.245013 TX Vref Scan disable
6883 23:09:40.245656 == TX Byte 0 ==
6884 23:09:40.251821 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6885 23:09:40.255347 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6886 23:09:40.255764 == TX Byte 1 ==
6887 23:09:40.262167 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6888 23:09:40.264679 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6889 23:09:40.265290 ==
6890 23:09:40.268366 Dram Type= 6, Freq= 0, CH_1, rank 1
6891 23:09:40.271757 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6892 23:09:40.272347 ==
6893 23:09:40.272828
6894 23:09:40.273381
6895 23:09:40.275128 TX Vref Scan disable
6896 23:09:40.275660 == TX Byte 0 ==
6897 23:09:40.281467 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6898 23:09:40.285083 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6899 23:09:40.285635 == TX Byte 1 ==
6900 23:09:40.291787 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6901 23:09:40.294681 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6902 23:09:40.295198
6903 23:09:40.295704 [DATLAT]
6904 23:09:40.298355 Freq=400, CH1 RK1
6905 23:09:40.298919
6906 23:09:40.299432 DATLAT Default: 0xe
6907 23:09:40.301303 0, 0xFFFF, sum = 0
6908 23:09:40.301932 1, 0xFFFF, sum = 0
6909 23:09:40.304965 2, 0xFFFF, sum = 0
6910 23:09:40.305504 3, 0xFFFF, sum = 0
6911 23:09:40.308568 4, 0xFFFF, sum = 0
6912 23:09:40.309022 5, 0xFFFF, sum = 0
6913 23:09:40.311421 6, 0xFFFF, sum = 0
6914 23:09:40.311990 7, 0xFFFF, sum = 0
6915 23:09:40.314745 8, 0xFFFF, sum = 0
6916 23:09:40.315315 9, 0xFFFF, sum = 0
6917 23:09:40.318156 10, 0xFFFF, sum = 0
6918 23:09:40.318728 11, 0xFFFF, sum = 0
6919 23:09:40.321678 12, 0xFFFF, sum = 0
6920 23:09:40.322245 13, 0x0, sum = 1
6921 23:09:40.324660 14, 0x0, sum = 2
6922 23:09:40.325226 15, 0x0, sum = 3
6923 23:09:40.328266 16, 0x0, sum = 4
6924 23:09:40.328834 best_step = 14
6925 23:09:40.329343
6926 23:09:40.329824 ==
6927 23:09:40.331943 Dram Type= 6, Freq= 0, CH_1, rank 1
6928 23:09:40.338125 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6929 23:09:40.338705 ==
6930 23:09:40.339214 RX Vref Scan: 0
6931 23:09:40.339713
6932 23:09:40.341785 RX Vref 0 -> 0, step: 1
6933 23:09:40.342276
6934 23:09:40.344869 RX Delay -311 -> 252, step: 8
6935 23:09:40.351815 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6936 23:09:40.354707 iDelay=217, Bit 1, Center -24 (-247 ~ 200) 448
6937 23:09:40.358200 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
6938 23:09:40.361707 iDelay=217, Bit 3, Center -20 (-239 ~ 200) 440
6939 23:09:40.367899 iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440
6940 23:09:40.371458 iDelay=217, Bit 5, Center -4 (-223 ~ 216) 440
6941 23:09:40.374813 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6942 23:09:40.378182 iDelay=217, Bit 7, Center -20 (-239 ~ 200) 440
6943 23:09:40.384790 iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448
6944 23:09:40.388061 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6945 23:09:40.391062 iDelay=217, Bit 10, Center -20 (-247 ~ 208) 456
6946 23:09:40.394364 iDelay=217, Bit 11, Center -24 (-247 ~ 200) 448
6947 23:09:40.401340 iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456
6948 23:09:40.404174 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
6949 23:09:40.407799 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6950 23:09:40.414257 iDelay=217, Bit 15, Center -12 (-231 ~ 208) 440
6951 23:09:40.414670 ==
6952 23:09:40.417905 Dram Type= 6, Freq= 0, CH_1, rank 1
6953 23:09:40.421138 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6954 23:09:40.421549 ==
6955 23:09:40.421924 DQS Delay:
6956 23:09:40.424202 DQS0 = 28, DQS1 = 32
6957 23:09:40.424608 DQM Delay:
6958 23:09:40.427632 DQM0 = 11, DQM1 = 11
6959 23:09:40.428041 DQ Delay:
6960 23:09:40.431356 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =8
6961 23:09:40.434367 DQ4 =8, DQ5 =24, DQ6 =20, DQ7 =8
6962 23:09:40.437838 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8
6963 23:09:40.440674 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =20
6964 23:09:40.441114
6965 23:09:40.441440
6966 23:09:40.447297 [DQSOSCAuto] RK1, (LSB)MR18= 0xc052, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 386 ps
6967 23:09:40.450806 CH1 RK1: MR19=C0C, MR18=C052
6968 23:09:40.457677 CH1_RK1: MR19=0xC0C, MR18=0xC052, DQSOSC=386, MR23=63, INC=396, DEC=264
6969 23:09:40.460738 [RxdqsGatingPostProcess] freq 400
6970 23:09:40.464179 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6971 23:09:40.467679 best DQS0 dly(2T, 0.5T) = (0, 10)
6972 23:09:40.471182 best DQS1 dly(2T, 0.5T) = (0, 10)
6973 23:09:40.474153 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6974 23:09:40.477692 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6975 23:09:40.480596 best DQS0 dly(2T, 0.5T) = (0, 10)
6976 23:09:40.484042 best DQS1 dly(2T, 0.5T) = (0, 10)
6977 23:09:40.487533 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6978 23:09:40.490712 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6979 23:09:40.493966 Pre-setting of DQS Precalculation
6980 23:09:40.497214 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6981 23:09:40.507383 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6982 23:09:40.514324 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6983 23:09:40.514783
6984 23:09:40.515183
6985 23:09:40.517335 [Calibration Summary] 800 Mbps
6986 23:09:40.517853 CH 0, Rank 0
6987 23:09:40.520872 SW Impedance : PASS
6988 23:09:40.521298 DUTY Scan : NO K
6989 23:09:40.523749 ZQ Calibration : PASS
6990 23:09:40.527228 Jitter Meter : NO K
6991 23:09:40.527699 CBT Training : PASS
6992 23:09:40.530762 Write leveling : PASS
6993 23:09:40.534006 RX DQS gating : PASS
6994 23:09:40.534418 RX DQ/DQS(RDDQC) : PASS
6995 23:09:40.536943 TX DQ/DQS : PASS
6996 23:09:40.540506 RX DATLAT : PASS
6997 23:09:40.540952 RX DQ/DQS(Engine): PASS
6998 23:09:40.543528 TX OE : NO K
6999 23:09:40.543966 All Pass.
7000 23:09:40.544321
7001 23:09:40.546985 CH 0, Rank 1
7002 23:09:40.547445 SW Impedance : PASS
7003 23:09:40.550289 DUTY Scan : NO K
7004 23:09:40.554002 ZQ Calibration : PASS
7005 23:09:40.554436 Jitter Meter : NO K
7006 23:09:40.557231 CBT Training : PASS
7007 23:09:40.557778 Write leveling : NO K
7008 23:09:40.560566 RX DQS gating : PASS
7009 23:09:40.564068 RX DQ/DQS(RDDQC) : PASS
7010 23:09:40.564504 TX DQ/DQS : PASS
7011 23:09:40.566994 RX DATLAT : PASS
7012 23:09:40.570453 RX DQ/DQS(Engine): PASS
7013 23:09:40.570941 TX OE : NO K
7014 23:09:40.573403 All Pass.
7015 23:09:40.573977
7016 23:09:40.574401 CH 1, Rank 0
7017 23:09:40.577206 SW Impedance : PASS
7018 23:09:40.577746 DUTY Scan : NO K
7019 23:09:40.580158 ZQ Calibration : PASS
7020 23:09:40.583544 Jitter Meter : NO K
7021 23:09:40.584067 CBT Training : PASS
7022 23:09:40.587158 Write leveling : PASS
7023 23:09:40.590827 RX DQS gating : PASS
7024 23:09:40.591329 RX DQ/DQS(RDDQC) : PASS
7025 23:09:40.593641 TX DQ/DQS : PASS
7026 23:09:40.597171 RX DATLAT : PASS
7027 23:09:40.597723 RX DQ/DQS(Engine): PASS
7028 23:09:40.600574 TX OE : NO K
7029 23:09:40.601057 All Pass.
7030 23:09:40.601490
7031 23:09:40.603854 CH 1, Rank 1
7032 23:09:40.604296 SW Impedance : PASS
7033 23:09:40.607368 DUTY Scan : NO K
7034 23:09:40.607889 ZQ Calibration : PASS
7035 23:09:40.610770 Jitter Meter : NO K
7036 23:09:40.613696 CBT Training : PASS
7037 23:09:40.614204 Write leveling : NO K
7038 23:09:40.617098 RX DQS gating : PASS
7039 23:09:40.619923 RX DQ/DQS(RDDQC) : PASS
7040 23:09:40.620359 TX DQ/DQS : PASS
7041 23:09:40.623918 RX DATLAT : PASS
7042 23:09:40.626761 RX DQ/DQS(Engine): PASS
7043 23:09:40.627244 TX OE : NO K
7044 23:09:40.630164 All Pass.
7045 23:09:40.630647
7046 23:09:40.631082 DramC Write-DBI off
7047 23:09:40.633740 PER_BANK_REFRESH: Hybrid Mode
7048 23:09:40.634267 TX_TRACKING: ON
7049 23:09:40.643438 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7050 23:09:40.646940 [FAST_K] Save calibration result to emmc
7051 23:09:40.650058 dramc_set_vcore_voltage set vcore to 725000
7052 23:09:40.653468 Read voltage for 1600, 0
7053 23:09:40.654065 Vio18 = 0
7054 23:09:40.656927 Vcore = 725000
7055 23:09:40.657482 Vdram = 0
7056 23:09:40.657963 Vddq = 0
7057 23:09:40.660462 Vmddr = 0
7058 23:09:40.663162 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7059 23:09:40.670102 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7060 23:09:40.670703 MEM_TYPE=3, freq_sel=13
7061 23:09:40.673830 sv_algorithm_assistance_LP4_3733
7062 23:09:40.680170 ============ PULL DRAM RESETB DOWN ============
7063 23:09:40.683605 ========== PULL DRAM RESETB DOWN end =========
7064 23:09:40.686532 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7065 23:09:40.690032 ===================================
7066 23:09:40.693477 LPDDR4 DRAM CONFIGURATION
7067 23:09:40.696323 ===================================
7068 23:09:40.696807 EX_ROW_EN[0] = 0x0
7069 23:09:40.699947 EX_ROW_EN[1] = 0x0
7070 23:09:40.703559 LP4Y_EN = 0x0
7071 23:09:40.704178 WORK_FSP = 0x1
7072 23:09:40.706955 WL = 0x5
7073 23:09:40.707861 RL = 0x5
7074 23:09:40.709852 BL = 0x2
7075 23:09:40.710306 RPST = 0x0
7076 23:09:40.713268 RD_PRE = 0x0
7077 23:09:40.713959 WR_PRE = 0x1
7078 23:09:40.716129 WR_PST = 0x1
7079 23:09:40.716625 DBI_WR = 0x0
7080 23:09:40.719665 DBI_RD = 0x0
7081 23:09:40.720170 OTF = 0x1
7082 23:09:40.723042 ===================================
7083 23:09:40.726579 ===================================
7084 23:09:40.730036 ANA top config
7085 23:09:40.733227 ===================================
7086 23:09:40.733975 DLL_ASYNC_EN = 0
7087 23:09:40.736224 ALL_SLAVE_EN = 0
7088 23:09:40.739355 NEW_RANK_MODE = 1
7089 23:09:40.742833 DLL_IDLE_MODE = 1
7090 23:09:40.746359 LP45_APHY_COMB_EN = 1
7091 23:09:40.746877 TX_ODT_DIS = 0
7092 23:09:40.749340 NEW_8X_MODE = 1
7093 23:09:40.753001 ===================================
7094 23:09:40.756619 ===================================
7095 23:09:40.759541 data_rate = 3200
7096 23:09:40.762967 CKR = 1
7097 23:09:40.766622 DQ_P2S_RATIO = 8
7098 23:09:40.769362 ===================================
7099 23:09:40.773057 CA_P2S_RATIO = 8
7100 23:09:40.773543 DQ_CA_OPEN = 0
7101 23:09:40.776046 DQ_SEMI_OPEN = 0
7102 23:09:40.779458 CA_SEMI_OPEN = 0
7103 23:09:40.783071 CA_FULL_RATE = 0
7104 23:09:40.786352 DQ_CKDIV4_EN = 0
7105 23:09:40.786772 CA_CKDIV4_EN = 0
7106 23:09:40.789416 CA_PREDIV_EN = 0
7107 23:09:40.792743 PH8_DLY = 12
7108 23:09:40.796294 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7109 23:09:40.799911 DQ_AAMCK_DIV = 4
7110 23:09:40.802648 CA_AAMCK_DIV = 4
7111 23:09:40.803074 CA_ADMCK_DIV = 4
7112 23:09:40.806300 DQ_TRACK_CA_EN = 0
7113 23:09:40.809400 CA_PICK = 1600
7114 23:09:40.812648 CA_MCKIO = 1600
7115 23:09:40.816394 MCKIO_SEMI = 0
7116 23:09:40.819338 PLL_FREQ = 3068
7117 23:09:40.822975 DQ_UI_PI_RATIO = 32
7118 23:09:40.825884 CA_UI_PI_RATIO = 0
7119 23:09:40.829332 ===================================
7120 23:09:40.832911 ===================================
7121 23:09:40.833335 memory_type:LPDDR4
7122 23:09:40.836233 GP_NUM : 10
7123 23:09:40.836669 SRAM_EN : 1
7124 23:09:40.839815 MD32_EN : 0
7125 23:09:40.843017 ===================================
7126 23:09:40.846124 [ANA_INIT] >>>>>>>>>>>>>>
7127 23:09:40.849634 <<<<<< [CONFIGURE PHASE]: ANA_TX
7128 23:09:40.853065 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7129 23:09:40.856295 ===================================
7130 23:09:40.856701 data_rate = 3200,PCW = 0X7600
7131 23:09:40.859283 ===================================
7132 23:09:40.865979 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7133 23:09:40.869430 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7134 23:09:40.876081 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7135 23:09:40.879128 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7136 23:09:40.882596 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7137 23:09:40.886208 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7138 23:09:40.889294 [ANA_INIT] flow start
7139 23:09:40.892783 [ANA_INIT] PLL >>>>>>>>
7140 23:09:40.893228 [ANA_INIT] PLL <<<<<<<<
7141 23:09:40.895688 [ANA_INIT] MIDPI >>>>>>>>
7142 23:09:40.899408 [ANA_INIT] MIDPI <<<<<<<<
7143 23:09:40.899863 [ANA_INIT] DLL >>>>>>>>
7144 23:09:40.902326 [ANA_INIT] DLL <<<<<<<<
7145 23:09:40.905550 [ANA_INIT] flow end
7146 23:09:40.909131 ============ LP4 DIFF to SE enter ============
7147 23:09:40.912666 ============ LP4 DIFF to SE exit ============
7148 23:09:40.916024 [ANA_INIT] <<<<<<<<<<<<<
7149 23:09:40.918907 [Flow] Enable top DCM control >>>>>
7150 23:09:40.922406 [Flow] Enable top DCM control <<<<<
7151 23:09:40.926280 Enable DLL master slave shuffle
7152 23:09:40.929144 ==============================================================
7153 23:09:40.932474 Gating Mode config
7154 23:09:40.939414 ==============================================================
7155 23:09:40.939842 Config description:
7156 23:09:40.949245 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7157 23:09:40.955824 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7158 23:09:40.958953 SELPH_MODE 0: By rank 1: By Phase
7159 23:09:40.965632 ==============================================================
7160 23:09:40.969126 GAT_TRACK_EN = 1
7161 23:09:40.972570 RX_GATING_MODE = 2
7162 23:09:40.976104 RX_GATING_TRACK_MODE = 2
7163 23:09:40.979406 SELPH_MODE = 1
7164 23:09:40.982661 PICG_EARLY_EN = 1
7165 23:09:40.986037 VALID_LAT_VALUE = 1
7166 23:09:40.989110 ==============================================================
7167 23:09:40.992555 Enter into Gating configuration >>>>
7168 23:09:40.995679 Exit from Gating configuration <<<<
7169 23:09:40.998749 Enter into DVFS_PRE_config >>>>>
7170 23:09:41.008960 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7171 23:09:41.012088 Exit from DVFS_PRE_config <<<<<
7172 23:09:41.015511 Enter into PICG configuration >>>>
7173 23:09:41.019023 Exit from PICG configuration <<<<
7174 23:09:41.022206 [RX_INPUT] configuration >>>>>
7175 23:09:41.025622 [RX_INPUT] configuration <<<<<
7176 23:09:41.032658 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7177 23:09:41.035898 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7178 23:09:41.042171 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7179 23:09:41.048810 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7180 23:09:41.055688 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7181 23:09:41.062369 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7182 23:09:41.065346 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7183 23:09:41.069063 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7184 23:09:41.072406 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7185 23:09:41.078973 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7186 23:09:41.082239 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7187 23:09:41.086002 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7188 23:09:41.089097 ===================================
7189 23:09:41.091915 LPDDR4 DRAM CONFIGURATION
7190 23:09:41.095480 ===================================
7191 23:09:41.095909 EX_ROW_EN[0] = 0x0
7192 23:09:41.098798 EX_ROW_EN[1] = 0x0
7193 23:09:41.099231 LP4Y_EN = 0x0
7194 23:09:41.102331 WORK_FSP = 0x1
7195 23:09:41.102760 WL = 0x5
7196 23:09:41.105181 RL = 0x5
7197 23:09:41.108472 BL = 0x2
7198 23:09:41.109032 RPST = 0x0
7199 23:09:41.112357 RD_PRE = 0x0
7200 23:09:41.112764 WR_PRE = 0x1
7201 23:09:41.115136 WR_PST = 0x1
7202 23:09:41.115578 DBI_WR = 0x0
7203 23:09:41.118897 DBI_RD = 0x0
7204 23:09:41.119337 OTF = 0x1
7205 23:09:41.121917 ===================================
7206 23:09:41.125411 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7207 23:09:41.131752 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7208 23:09:41.135271 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7209 23:09:41.138885 ===================================
7210 23:09:41.141981 LPDDR4 DRAM CONFIGURATION
7211 23:09:41.145512 ===================================
7212 23:09:41.146015 EX_ROW_EN[0] = 0x10
7213 23:09:41.148474 EX_ROW_EN[1] = 0x0
7214 23:09:41.149057 LP4Y_EN = 0x0
7215 23:09:41.151847 WORK_FSP = 0x1
7216 23:09:41.152264 WL = 0x5
7217 23:09:41.155374 RL = 0x5
7218 23:09:41.155789 BL = 0x2
7219 23:09:41.158857 RPST = 0x0
7220 23:09:41.159397 RD_PRE = 0x0
7221 23:09:41.161801 WR_PRE = 0x1
7222 23:09:41.165364 WR_PST = 0x1
7223 23:09:41.165974 DBI_WR = 0x0
7224 23:09:41.169109 DBI_RD = 0x0
7225 23:09:41.169758 OTF = 0x1
7226 23:09:41.172234 ===================================
7227 23:09:41.178538 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7228 23:09:41.179026 ==
7229 23:09:41.182057 Dram Type= 6, Freq= 0, CH_0, rank 0
7230 23:09:41.185081 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7231 23:09:41.185687 ==
7232 23:09:41.188689 [Duty_Offset_Calibration]
7233 23:09:41.189154 B0:2 B1:1 CA:1
7234 23:09:41.189554
7235 23:09:41.192245 [DutyScan_Calibration_Flow] k_type=0
7236 23:09:41.203038
7237 23:09:41.203716 ==CLK 0==
7238 23:09:41.206833 Final CLK duty delay cell = 0
7239 23:09:41.210023 [0] MAX Duty = 5156%(X100), DQS PI = 22
7240 23:09:41.213227 [0] MIN Duty = 4907%(X100), DQS PI = 0
7241 23:09:41.213672 [0] AVG Duty = 5031%(X100)
7242 23:09:41.216431
7243 23:09:41.219472 CH0 CLK Duty spec in!! Max-Min= 249%
7244 23:09:41.222966 [DutyScan_Calibration_Flow] ====Done====
7245 23:09:41.223376
7246 23:09:41.225944 [DutyScan_Calibration_Flow] k_type=1
7247 23:09:41.242207
7248 23:09:41.242723 ==DQS 0 ==
7249 23:09:41.245401 Final DQS duty delay cell = -4
7250 23:09:41.248819 [-4] MAX Duty = 5125%(X100), DQS PI = 24
7251 23:09:41.252119 [-4] MIN Duty = 4657%(X100), DQS PI = 0
7252 23:09:41.255676 [-4] AVG Duty = 4891%(X100)
7253 23:09:41.256110
7254 23:09:41.256497 ==DQS 1 ==
7255 23:09:41.258743 Final DQS duty delay cell = 0
7256 23:09:41.262214 [0] MAX Duty = 5187%(X100), DQS PI = 10
7257 23:09:41.265929 [0] MIN Duty = 5062%(X100), DQS PI = 32
7258 23:09:41.268834 [0] AVG Duty = 5124%(X100)
7259 23:09:41.269124
7260 23:09:41.271780 CH0 DQS 0 Duty spec in!! Max-Min= 468%
7261 23:09:41.272048
7262 23:09:41.275319 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7263 23:09:41.278840 [DutyScan_Calibration_Flow] ====Done====
7264 23:09:41.279130
7265 23:09:41.281749 [DutyScan_Calibration_Flow] k_type=3
7266 23:09:41.298906
7267 23:09:41.298990 ==DQM 0 ==
7268 23:09:41.301723 Final DQM duty delay cell = 0
7269 23:09:41.305482 [0] MAX Duty = 5218%(X100), DQS PI = 34
7270 23:09:41.308470 [0] MIN Duty = 4907%(X100), DQS PI = 56
7271 23:09:41.311847 [0] AVG Duty = 5062%(X100)
7272 23:09:41.311926
7273 23:09:41.311989 ==DQM 1 ==
7274 23:09:41.315245 Final DQM duty delay cell = -4
7275 23:09:41.318654 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7276 23:09:41.322113 [-4] MIN Duty = 4813%(X100), DQS PI = 50
7277 23:09:41.324863 [-4] AVG Duty = 4906%(X100)
7278 23:09:41.324943
7279 23:09:41.328239 CH0 DQM 0 Duty spec in!! Max-Min= 311%
7280 23:09:41.328318
7281 23:09:41.331604 CH0 DQM 1 Duty spec in!! Max-Min= 187%
7282 23:09:41.335011 [DutyScan_Calibration_Flow] ====Done====
7283 23:09:41.335092
7284 23:09:41.338141 [DutyScan_Calibration_Flow] k_type=2
7285 23:09:41.356445
7286 23:09:41.356528 ==DQ 0 ==
7287 23:09:41.359439 Final DQ duty delay cell = 0
7288 23:09:41.362869 [0] MAX Duty = 5062%(X100), DQS PI = 26
7289 23:09:41.366116 [0] MIN Duty = 4907%(X100), DQS PI = 0
7290 23:09:41.366196 [0] AVG Duty = 4984%(X100)
7291 23:09:41.366259
7292 23:09:41.369591 ==DQ 1 ==
7293 23:09:41.372498 Final DQ duty delay cell = 0
7294 23:09:41.376256 [0] MAX Duty = 5125%(X100), DQS PI = 6
7295 23:09:41.379270 [0] MIN Duty = 4907%(X100), DQS PI = 34
7296 23:09:41.379380 [0] AVG Duty = 5016%(X100)
7297 23:09:41.379471
7298 23:09:41.382651 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7299 23:09:41.382750
7300 23:09:41.386143 CH0 DQ 1 Duty spec in!! Max-Min= 218%
7301 23:09:41.392674 [DutyScan_Calibration_Flow] ====Done====
7302 23:09:41.392777 ==
7303 23:09:41.396159 Dram Type= 6, Freq= 0, CH_1, rank 0
7304 23:09:41.399716 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7305 23:09:41.399800 ==
7306 23:09:41.402685 [Duty_Offset_Calibration]
7307 23:09:41.402759 B0:1 B1:0 CA:0
7308 23:09:41.402844
7309 23:09:41.406201 [DutyScan_Calibration_Flow] k_type=0
7310 23:09:41.415173
7311 23:09:41.415273 ==CLK 0==
7312 23:09:41.418836 Final CLK duty delay cell = -4
7313 23:09:41.421854 [-4] MAX Duty = 4969%(X100), DQS PI = 22
7314 23:09:41.425250 [-4] MIN Duty = 4844%(X100), DQS PI = 50
7315 23:09:41.428609 [-4] AVG Duty = 4906%(X100)
7316 23:09:41.428702
7317 23:09:41.432054 CH1 CLK Duty spec in!! Max-Min= 125%
7318 23:09:41.435529 [DutyScan_Calibration_Flow] ====Done====
7319 23:09:41.435634
7320 23:09:41.438511 [DutyScan_Calibration_Flow] k_type=1
7321 23:09:41.455688
7322 23:09:41.455779 ==DQS 0 ==
7323 23:09:41.458737 Final DQS duty delay cell = 0
7324 23:09:41.462324 [0] MAX Duty = 5094%(X100), DQS PI = 16
7325 23:09:41.465499 [0] MIN Duty = 4875%(X100), DQS PI = 0
7326 23:09:41.465611 [0] AVG Duty = 4984%(X100)
7327 23:09:41.468845
7328 23:09:41.468953 ==DQS 1 ==
7329 23:09:41.472093 Final DQS duty delay cell = 0
7330 23:09:41.475395 [0] MAX Duty = 5249%(X100), DQS PI = 16
7331 23:09:41.478842 [0] MIN Duty = 4969%(X100), DQS PI = 6
7332 23:09:41.478957 [0] AVG Duty = 5109%(X100)
7333 23:09:41.481977
7334 23:09:41.485409 CH1 DQS 0 Duty spec in!! Max-Min= 219%
7335 23:09:41.485507
7336 23:09:41.488542 CH1 DQS 1 Duty spec in!! Max-Min= 280%
7337 23:09:41.492475 [DutyScan_Calibration_Flow] ====Done====
7338 23:09:41.492557
7339 23:09:41.495438 [DutyScan_Calibration_Flow] k_type=3
7340 23:09:41.512488
7341 23:09:41.512575 ==DQM 0 ==
7342 23:09:41.515641 Final DQM duty delay cell = 0
7343 23:09:41.518993 [0] MAX Duty = 5218%(X100), DQS PI = 18
7344 23:09:41.522080 [0] MIN Duty = 4969%(X100), DQS PI = 48
7345 23:09:41.525751 [0] AVG Duty = 5093%(X100)
7346 23:09:41.525830
7347 23:09:41.525892 ==DQM 1 ==
7348 23:09:41.529288 Final DQM duty delay cell = 0
7349 23:09:41.532150 [0] MAX Duty = 5093%(X100), DQS PI = 24
7350 23:09:41.535565 [0] MIN Duty = 4907%(X100), DQS PI = 32
7351 23:09:41.538708 [0] AVG Duty = 5000%(X100)
7352 23:09:41.538807
7353 23:09:41.542375 CH1 DQM 0 Duty spec in!! Max-Min= 249%
7354 23:09:41.542455
7355 23:09:41.545257 CH1 DQM 1 Duty spec in!! Max-Min= 186%
7356 23:09:41.548754 [DutyScan_Calibration_Flow] ====Done====
7357 23:09:41.548834
7358 23:09:41.552375 [DutyScan_Calibration_Flow] k_type=2
7359 23:09:41.568370
7360 23:09:41.568452 ==DQ 0 ==
7361 23:09:41.571789 Final DQ duty delay cell = -4
7362 23:09:41.575348 [-4] MAX Duty = 5031%(X100), DQS PI = 8
7363 23:09:41.578392 [-4] MIN Duty = 4875%(X100), DQS PI = 46
7364 23:09:41.581683 [-4] AVG Duty = 4953%(X100)
7365 23:09:41.581763
7366 23:09:41.581826 ==DQ 1 ==
7367 23:09:41.585369 Final DQ duty delay cell = 0
7368 23:09:41.588374 [0] MAX Duty = 5124%(X100), DQS PI = 18
7369 23:09:41.591603 [0] MIN Duty = 4938%(X100), DQS PI = 8
7370 23:09:41.591682 [0] AVG Duty = 5031%(X100)
7371 23:09:41.594927
7372 23:09:41.598099 CH1 DQ 0 Duty spec in!! Max-Min= 156%
7373 23:09:41.598183
7374 23:09:41.601593 CH1 DQ 1 Duty spec in!! Max-Min= 186%
7375 23:09:41.605093 [DutyScan_Calibration_Flow] ====Done====
7376 23:09:41.608165 nWR fixed to 30
7377 23:09:41.608250 [ModeRegInit_LP4] CH0 RK0
7378 23:09:41.611837 [ModeRegInit_LP4] CH0 RK1
7379 23:09:41.615337 [ModeRegInit_LP4] CH1 RK0
7380 23:09:41.618503 [ModeRegInit_LP4] CH1 RK1
7381 23:09:41.618585 match AC timing 5
7382 23:09:41.621906 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7383 23:09:41.628181 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7384 23:09:41.631538 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7385 23:09:41.638287 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7386 23:09:41.641609 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7387 23:09:41.641704 [MiockJmeterHQA]
7388 23:09:41.641769
7389 23:09:41.645001 [DramcMiockJmeter] u1RxGatingPI = 0
7390 23:09:41.647909 0 : 4253, 4027
7391 23:09:41.648007 4 : 4252, 4027
7392 23:09:41.651363 8 : 4254, 4029
7393 23:09:41.651446 12 : 4257, 4029
7394 23:09:41.651511 16 : 4252, 4027
7395 23:09:41.654900 20 : 4253, 4027
7396 23:09:41.654982 24 : 4252, 4027
7397 23:09:41.658511 28 : 4365, 4140
7398 23:09:41.658592 32 : 4253, 4026
7399 23:09:41.661491 36 : 4255, 4029
7400 23:09:41.661572 40 : 4252, 4027
7401 23:09:41.661674 44 : 4363, 4138
7402 23:09:41.665251 48 : 4252, 4027
7403 23:09:41.665333 52 : 4361, 4138
7404 23:09:41.668134 56 : 4252, 4027
7405 23:09:41.668216 60 : 4250, 4027
7406 23:09:41.671777 64 : 4250, 4026
7407 23:09:41.671859 68 : 4253, 4029
7408 23:09:41.674743 72 : 4361, 4138
7409 23:09:41.674825 76 : 4250, 4027
7410 23:09:41.674890 80 : 4361, 4137
7411 23:09:41.678045 84 : 4250, 4027
7412 23:09:41.678128 88 : 4250, 52
7413 23:09:41.681583 92 : 4250, 0
7414 23:09:41.681679 96 : 4363, 0
7415 23:09:41.681744 100 : 4250, 0
7416 23:09:41.684882 104 : 4250, 0
7417 23:09:41.684965 108 : 4252, 0
7418 23:09:41.688456 112 : 4250, 0
7419 23:09:41.688540 116 : 4250, 0
7420 23:09:41.688606 120 : 4253, 0
7421 23:09:41.691417 124 : 4361, 0
7422 23:09:41.691499 128 : 4361, 0
7423 23:09:41.691565 132 : 4250, 0
7424 23:09:41.695112 136 : 4363, 0
7425 23:09:41.695196 140 : 4250, 0
7426 23:09:41.698089 144 : 4250, 0
7427 23:09:41.698172 148 : 4250, 0
7428 23:09:41.698237 152 : 4250, 0
7429 23:09:41.701507 156 : 4250, 0
7430 23:09:41.701628 160 : 4250, 0
7431 23:09:41.705074 164 : 4250, 0
7432 23:09:41.705156 168 : 4250, 0
7433 23:09:41.705221 172 : 4250, 0
7434 23:09:41.708019 176 : 4361, 0
7435 23:09:41.708101 180 : 4250, 0
7436 23:09:41.711251 184 : 4250, 0
7437 23:09:41.711333 188 : 4363, 0
7438 23:09:41.711398 192 : 4360, 0
7439 23:09:41.714525 196 : 4250, 0
7440 23:09:41.714607 200 : 4250, 0
7441 23:09:41.717748 204 : 4250, 1516
7442 23:09:41.717831 208 : 4252, 4012
7443 23:09:41.721705 212 : 4361, 4138
7444 23:09:41.721788 216 : 4250, 4027
7445 23:09:41.721852 220 : 4250, 4027
7446 23:09:41.724404 224 : 4361, 4137
7447 23:09:41.724493 228 : 4361, 4138
7448 23:09:41.728108 232 : 4250, 4027
7449 23:09:41.728206 236 : 4363, 4140
7450 23:09:41.731251 240 : 4361, 4138
7451 23:09:41.731398 244 : 4250, 4026
7452 23:09:41.734548 248 : 4250, 4027
7453 23:09:41.734676 252 : 4252, 4029
7454 23:09:41.737805 256 : 4250, 4027
7455 23:09:41.737927 260 : 4250, 4026
7456 23:09:41.740929 264 : 4252, 4027
7457 23:09:41.741042 268 : 4252, 4029
7458 23:09:41.744492 272 : 4249, 4027
7459 23:09:41.744575 276 : 4361, 4138
7460 23:09:41.747425 280 : 4361, 4138
7461 23:09:41.747509 284 : 4250, 4027
7462 23:09:41.747573 288 : 4363, 4140
7463 23:09:41.750894 292 : 4361, 4138
7464 23:09:41.750977 296 : 4250, 4027
7465 23:09:41.754484 300 : 4250, 4027
7466 23:09:41.754575 304 : 4252, 4029
7467 23:09:41.757456 308 : 4250, 3988
7468 23:09:41.757529 312 : 4250, 2022
7469 23:09:41.757612
7470 23:09:41.760716 MIOCK jitter meter ch=0
7471 23:09:41.760796
7472 23:09:41.764527 1T = (312-88) = 224 dly cells
7473 23:09:41.770546 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7474 23:09:41.770629 ==
7475 23:09:41.774141 Dram Type= 6, Freq= 0, CH_0, rank 0
7476 23:09:41.777600 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7477 23:09:41.777697 ==
7478 23:09:41.784238 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7479 23:09:41.787626 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7480 23:09:41.790640 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7481 23:09:41.797209 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7482 23:09:41.806062 [CA 0] Center 43 (13~74) winsize 62
7483 23:09:41.809048 [CA 1] Center 43 (13~74) winsize 62
7484 23:09:41.812506 [CA 2] Center 38 (9~68) winsize 60
7485 23:09:41.815952 [CA 3] Center 38 (8~68) winsize 61
7486 23:09:41.818897 [CA 4] Center 37 (7~67) winsize 61
7487 23:09:41.822280 [CA 5] Center 36 (7~65) winsize 59
7488 23:09:41.822361
7489 23:09:41.825545 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7490 23:09:41.825671
7491 23:09:41.828995 [CATrainingPosCal] consider 1 rank data
7492 23:09:41.832688 u2DelayCellTimex100 = 290/100 ps
7493 23:09:41.835675 CA0 delay=43 (13~74),Diff = 7 PI (23 cell)
7494 23:09:41.842477 CA1 delay=43 (13~74),Diff = 7 PI (23 cell)
7495 23:09:41.845787 CA2 delay=38 (9~68),Diff = 2 PI (6 cell)
7496 23:09:41.849173 CA3 delay=38 (8~68),Diff = 2 PI (6 cell)
7497 23:09:41.852042 CA4 delay=37 (7~67),Diff = 1 PI (3 cell)
7498 23:09:41.855474 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
7499 23:09:41.855555
7500 23:09:41.859168 CA PerBit enable=1, Macro0, CA PI delay=36
7501 23:09:41.859247
7502 23:09:41.862225 [CBTSetCACLKResult] CA Dly = 36
7503 23:09:41.865570 CS Dly: 9 (0~40)
7504 23:09:41.868938 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7505 23:09:41.872294 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7506 23:09:41.872375 ==
7507 23:09:41.875824 Dram Type= 6, Freq= 0, CH_0, rank 1
7508 23:09:41.878853 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7509 23:09:41.878934 ==
7510 23:09:41.885930 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7511 23:09:41.889450 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7512 23:09:41.895607 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7513 23:09:41.898978 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7514 23:09:41.909429 [CA 0] Center 43 (13~73) winsize 61
7515 23:09:41.912524 [CA 1] Center 43 (13~73) winsize 61
7516 23:09:41.916159 [CA 2] Center 38 (8~68) winsize 61
7517 23:09:41.919422 [CA 3] Center 38 (8~68) winsize 61
7518 23:09:41.923046 [CA 4] Center 36 (6~66) winsize 61
7519 23:09:41.925914 [CA 5] Center 35 (6~65) winsize 60
7520 23:09:41.926320
7521 23:09:41.929394 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7522 23:09:41.929857
7523 23:09:41.932718 [CATrainingPosCal] consider 2 rank data
7524 23:09:41.935946 u2DelayCellTimex100 = 290/100 ps
7525 23:09:41.939040 CA0 delay=43 (13~73),Diff = 7 PI (23 cell)
7526 23:09:41.946139 CA1 delay=43 (13~73),Diff = 7 PI (23 cell)
7527 23:09:41.948992 CA2 delay=38 (9~68),Diff = 2 PI (6 cell)
7528 23:09:41.952464 CA3 delay=38 (8~68),Diff = 2 PI (6 cell)
7529 23:09:41.955756 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7530 23:09:41.959334 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
7531 23:09:41.959747
7532 23:09:41.962638 CA PerBit enable=1, Macro0, CA PI delay=36
7533 23:09:41.963051
7534 23:09:41.965941 [CBTSetCACLKResult] CA Dly = 36
7535 23:09:41.969102 CS Dly: 10 (0~42)
7536 23:09:41.972559 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7537 23:09:41.976078 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7538 23:09:41.976507
7539 23:09:41.979381 ----->DramcWriteLeveling(PI) begin...
7540 23:09:41.979823 ==
7541 23:09:41.982727 Dram Type= 6, Freq= 0, CH_0, rank 0
7542 23:09:41.985433 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7543 23:09:41.988964 ==
7544 23:09:41.989196 Write leveling (Byte 0): 35 => 35
7545 23:09:41.992564 Write leveling (Byte 1): 26 => 26
7546 23:09:41.995589 DramcWriteLeveling(PI) end<-----
7547 23:09:41.995744
7548 23:09:41.995902 ==
7549 23:09:41.999020 Dram Type= 6, Freq= 0, CH_0, rank 0
7550 23:09:42.005591 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7551 23:09:42.005754 ==
7552 23:09:42.005912 [Gating] SW mode calibration
7553 23:09:42.015300 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7554 23:09:42.018704 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7555 23:09:42.025180 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7556 23:09:42.028660 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7557 23:09:42.032303 1 4 8 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
7558 23:09:42.035237 1 4 12 | B1->B0 | 2323 3838 | 0 1 | (0 0) (1 1)
7559 23:09:42.041604 1 4 16 | B1->B0 | 2323 3636 | 0 0 | (0 0) (0 0)
7560 23:09:42.045205 1 4 20 | B1->B0 | 3434 3838 | 1 0 | (1 1) (0 0)
7561 23:09:42.048881 1 4 24 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
7562 23:09:42.055371 1 4 28 | B1->B0 | 3434 3737 | 1 0 | (1 1) (1 1)
7563 23:09:42.058435 1 5 0 | B1->B0 | 3434 3636 | 1 0 | (1 1) (1 1)
7564 23:09:42.061501 1 5 4 | B1->B0 | 3434 3636 | 1 0 | (1 1) (0 0)
7565 23:09:42.068334 1 5 8 | B1->B0 | 3434 3534 | 1 1 | (1 1) (0 0)
7566 23:09:42.071602 1 5 12 | B1->B0 | 3434 2828 | 1 0 | (1 1) (1 0)
7567 23:09:42.075306 1 5 16 | B1->B0 | 3434 2727 | 1 0 | (1 0) (1 1)
7568 23:09:42.081546 1 5 20 | B1->B0 | 2727 2726 | 0 1 | (0 0) (0 0)
7569 23:09:42.084745 1 5 24 | B1->B0 | 2323 2b2a | 0 1 | (0 0) (0 0)
7570 23:09:42.088087 1 5 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7571 23:09:42.095105 1 6 0 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
7572 23:09:42.098057 1 6 4 | B1->B0 | 2323 2625 | 0 1 | (0 0) (0 0)
7573 23:09:42.101475 1 6 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (0 0)
7574 23:09:42.107969 1 6 12 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
7575 23:09:42.111385 1 6 16 | B1->B0 | 2929 4646 | 0 0 | (1 1) (0 0)
7576 23:09:42.114710 1 6 20 | B1->B0 | 4444 4645 | 0 1 | (0 0) (1 1)
7577 23:09:42.121360 1 6 24 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
7578 23:09:42.124818 1 6 28 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
7579 23:09:42.128297 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7580 23:09:42.134718 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7581 23:09:42.138248 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7582 23:09:42.141362 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7583 23:09:42.148178 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7584 23:09:42.151626 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7585 23:09:42.155037 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7586 23:09:42.161817 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7587 23:09:42.164664 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7588 23:09:42.168175 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7589 23:09:42.174863 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7590 23:09:42.178333 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7591 23:09:42.181567 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7592 23:09:42.184822 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7593 23:09:42.191536 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7594 23:09:42.194595 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7595 23:09:42.197841 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7596 23:09:42.204417 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7597 23:09:42.207948 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7598 23:09:42.211471 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7599 23:09:42.217887 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7600 23:09:42.220880 Total UI for P1: 0, mck2ui 16
7601 23:09:42.224287 best dqsien dly found for B0: ( 1, 9, 10)
7602 23:09:42.227804 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7603 23:09:42.230811 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7604 23:09:42.234039 Total UI for P1: 0, mck2ui 16
7605 23:09:42.237598 best dqsien dly found for B1: ( 1, 9, 18)
7606 23:09:42.241262 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7607 23:09:42.247808 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7608 23:09:42.247889
7609 23:09:42.250888 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7610 23:09:42.254385 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7611 23:09:42.257767 [Gating] SW calibration Done
7612 23:09:42.257857 ==
7613 23:09:42.261014 Dram Type= 6, Freq= 0, CH_0, rank 0
7614 23:09:42.264263 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7615 23:09:42.264404 ==
7616 23:09:42.264525 RX Vref Scan: 0
7617 23:09:42.267640
7618 23:09:42.267745 RX Vref 0 -> 0, step: 1
7619 23:09:42.267857
7620 23:09:42.271225 RX Delay 0 -> 252, step: 8
7621 23:09:42.274297 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
7622 23:09:42.277749 iDelay=200, Bit 1, Center 143 (88 ~ 199) 112
7623 23:09:42.284279 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7624 23:09:42.287503 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7625 23:09:42.290805 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7626 23:09:42.294420 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7627 23:09:42.297656 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7628 23:09:42.301203 iDelay=200, Bit 7, Center 143 (96 ~ 191) 96
7629 23:09:42.307587 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
7630 23:09:42.311017 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
7631 23:09:42.314553 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
7632 23:09:42.317548 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7633 23:09:42.324202 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
7634 23:09:42.327705 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
7635 23:09:42.330908 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7636 23:09:42.334305 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7637 23:09:42.334617 ==
7638 23:09:42.337172 Dram Type= 6, Freq= 0, CH_0, rank 0
7639 23:09:42.340754 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7640 23:09:42.344221 ==
7641 23:09:42.344456 DQS Delay:
7642 23:09:42.344650 DQS0 = 0, DQS1 = 0
7643 23:09:42.347473 DQM Delay:
7644 23:09:42.347706 DQM0 = 136, DQM1 = 129
7645 23:09:42.351106 DQ Delay:
7646 23:09:42.354447 DQ0 =135, DQ1 =143, DQ2 =131, DQ3 =131
7647 23:09:42.357305 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =143
7648 23:09:42.360966 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =119
7649 23:09:42.363997 DQ12 =135, DQ13 =139, DQ14 =139, DQ15 =135
7650 23:09:42.364257
7651 23:09:42.364451
7652 23:09:42.364649 ==
7653 23:09:42.367376 Dram Type= 6, Freq= 0, CH_0, rank 0
7654 23:09:42.370539 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7655 23:09:42.370812 ==
7656 23:09:42.374092
7657 23:09:42.374358
7658 23:09:42.374570 TX Vref Scan disable
7659 23:09:42.377619 == TX Byte 0 ==
7660 23:09:42.380455 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7661 23:09:42.384364 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7662 23:09:42.387075 == TX Byte 1 ==
7663 23:09:42.390779 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7664 23:09:42.394305 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7665 23:09:42.394633 ==
7666 23:09:42.397335 Dram Type= 6, Freq= 0, CH_0, rank 0
7667 23:09:42.403634 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7668 23:09:42.403871 ==
7669 23:09:42.416700
7670 23:09:42.419974 TX Vref early break, caculate TX vref
7671 23:09:42.423683 TX Vref=16, minBit 0, minWin=23, winSum=378
7672 23:09:42.426673 TX Vref=18, minBit 0, minWin=23, winSum=387
7673 23:09:42.430154 TX Vref=20, minBit 7, minWin=23, winSum=399
7674 23:09:42.433146 TX Vref=22, minBit 7, minWin=24, winSum=410
7675 23:09:42.436631 TX Vref=24, minBit 3, minWin=25, winSum=417
7676 23:09:42.443242 TX Vref=26, minBit 6, minWin=25, winSum=424
7677 23:09:42.446391 TX Vref=28, minBit 1, minWin=25, winSum=424
7678 23:09:42.450006 TX Vref=30, minBit 6, minWin=24, winSum=414
7679 23:09:42.453013 TX Vref=32, minBit 6, minWin=23, winSum=403
7680 23:09:42.456724 TX Vref=34, minBit 0, minWin=23, winSum=395
7681 23:09:42.463402 [TxChooseVref] Worse bit 6, Min win 25, Win sum 424, Final Vref 26
7682 23:09:42.463884
7683 23:09:42.466415 Final TX Range 0 Vref 26
7684 23:09:42.466841
7685 23:09:42.467189 ==
7686 23:09:42.469918 Dram Type= 6, Freq= 0, CH_0, rank 0
7687 23:09:42.473309 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7688 23:09:42.473774 ==
7689 23:09:42.474155
7690 23:09:42.474485
7691 23:09:42.476728 TX Vref Scan disable
7692 23:09:42.483142 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7693 23:09:42.483542 == TX Byte 0 ==
7694 23:09:42.486510 u2DelayCellOfst[0]=10 cells (3 PI)
7695 23:09:42.489702 u2DelayCellOfst[1]=13 cells (4 PI)
7696 23:09:42.493126 u2DelayCellOfst[2]=10 cells (3 PI)
7697 23:09:42.496208 u2DelayCellOfst[3]=10 cells (3 PI)
7698 23:09:42.499780 u2DelayCellOfst[4]=6 cells (2 PI)
7699 23:09:42.502825 u2DelayCellOfst[5]=0 cells (0 PI)
7700 23:09:42.506384 u2DelayCellOfst[6]=16 cells (5 PI)
7701 23:09:42.509682 u2DelayCellOfst[7]=13 cells (4 PI)
7702 23:09:42.513089 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7703 23:09:42.516056 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7704 23:09:42.519498 == TX Byte 1 ==
7705 23:09:42.520186 u2DelayCellOfst[8]=3 cells (1 PI)
7706 23:09:42.522667 u2DelayCellOfst[9]=0 cells (0 PI)
7707 23:09:42.525862 u2DelayCellOfst[10]=6 cells (2 PI)
7708 23:09:42.529227 u2DelayCellOfst[11]=3 cells (1 PI)
7709 23:09:42.532402 u2DelayCellOfst[12]=10 cells (3 PI)
7710 23:09:42.536118 u2DelayCellOfst[13]=13 cells (4 PI)
7711 23:09:42.539789 u2DelayCellOfst[14]=16 cells (5 PI)
7712 23:09:42.542782 u2DelayCellOfst[15]=10 cells (3 PI)
7713 23:09:42.546288 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
7714 23:09:42.552705 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7715 23:09:42.553163 DramC Write-DBI on
7716 23:09:42.553492 ==
7717 23:09:42.555911 Dram Type= 6, Freq= 0, CH_0, rank 0
7718 23:09:42.562224 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7719 23:09:42.562717 ==
7720 23:09:42.563084
7721 23:09:42.563433
7722 23:09:42.563790 TX Vref Scan disable
7723 23:09:42.566311 == TX Byte 0 ==
7724 23:09:42.569732 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7725 23:09:42.572832 == TX Byte 1 ==
7726 23:09:42.576314 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
7727 23:09:42.579892 DramC Write-DBI off
7728 23:09:42.580316
7729 23:09:42.580642 [DATLAT]
7730 23:09:42.580943 Freq=1600, CH0 RK0
7731 23:09:42.581238
7732 23:09:42.582753 DATLAT Default: 0xf
7733 23:09:42.583097 0, 0xFFFF, sum = 0
7734 23:09:42.586481 1, 0xFFFF, sum = 0
7735 23:09:42.589715 2, 0xFFFF, sum = 0
7736 23:09:42.590135 3, 0xFFFF, sum = 0
7737 23:09:42.592661 4, 0xFFFF, sum = 0
7738 23:09:42.593186 5, 0xFFFF, sum = 0
7739 23:09:42.595918 6, 0xFFFF, sum = 0
7740 23:09:42.596336 7, 0xFFFF, sum = 0
7741 23:09:42.599471 8, 0xFFFF, sum = 0
7742 23:09:42.599897 9, 0xFFFF, sum = 0
7743 23:09:42.602636 10, 0xFFFF, sum = 0
7744 23:09:42.603054 11, 0xFFFF, sum = 0
7745 23:09:42.606540 12, 0xFFFF, sum = 0
7746 23:09:42.606972 13, 0xFFFF, sum = 0
7747 23:09:42.609457 14, 0x0, sum = 1
7748 23:09:42.610064 15, 0x0, sum = 2
7749 23:09:42.612623 16, 0x0, sum = 3
7750 23:09:42.613120 17, 0x0, sum = 4
7751 23:09:42.615889 best_step = 15
7752 23:09:42.616296
7753 23:09:42.616622 ==
7754 23:09:42.619323 Dram Type= 6, Freq= 0, CH_0, rank 0
7755 23:09:42.622514 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7756 23:09:42.622930 ==
7757 23:09:42.626362 RX Vref Scan: 1
7758 23:09:42.626773
7759 23:09:42.627099 Set Vref Range= 24 -> 127
7760 23:09:42.627401
7761 23:09:42.629111 RX Vref 24 -> 127, step: 1
7762 23:09:42.629521
7763 23:09:42.632765 RX Delay 19 -> 252, step: 4
7764 23:09:42.633174
7765 23:09:42.636085 Set Vref, RX VrefLevel [Byte0]: 24
7766 23:09:42.639240 [Byte1]: 24
7767 23:09:42.639651
7768 23:09:42.642479 Set Vref, RX VrefLevel [Byte0]: 25
7769 23:09:42.645754 [Byte1]: 25
7770 23:09:42.646305
7771 23:09:42.649360 Set Vref, RX VrefLevel [Byte0]: 26
7772 23:09:42.652444 [Byte1]: 26
7773 23:09:42.656611
7774 23:09:42.657077 Set Vref, RX VrefLevel [Byte0]: 27
7775 23:09:42.660291 [Byte1]: 27
7776 23:09:42.664219
7777 23:09:42.664626 Set Vref, RX VrefLevel [Byte0]: 28
7778 23:09:42.667473 [Byte1]: 28
7779 23:09:42.671509
7780 23:09:42.671955 Set Vref, RX VrefLevel [Byte0]: 29
7781 23:09:42.675152 [Byte1]: 29
7782 23:09:42.679251
7783 23:09:42.679791 Set Vref, RX VrefLevel [Byte0]: 30
7784 23:09:42.682751 [Byte1]: 30
7785 23:09:42.687040
7786 23:09:42.687449 Set Vref, RX VrefLevel [Byte0]: 31
7787 23:09:42.689954 [Byte1]: 31
7788 23:09:42.694801
7789 23:09:42.695208 Set Vref, RX VrefLevel [Byte0]: 32
7790 23:09:42.697683 [Byte1]: 32
7791 23:09:42.702166
7792 23:09:42.702708 Set Vref, RX VrefLevel [Byte0]: 33
7793 23:09:42.705205 [Byte1]: 33
7794 23:09:42.709975
7795 23:09:42.710479 Set Vref, RX VrefLevel [Byte0]: 34
7796 23:09:42.713154 [Byte1]: 34
7797 23:09:42.717369
7798 23:09:42.717862 Set Vref, RX VrefLevel [Byte0]: 35
7799 23:09:42.720258 [Byte1]: 35
7800 23:09:42.724778
7801 23:09:42.725199 Set Vref, RX VrefLevel [Byte0]: 36
7802 23:09:42.728041 [Byte1]: 36
7803 23:09:42.732380
7804 23:09:42.732810 Set Vref, RX VrefLevel [Byte0]: 37
7805 23:09:42.735987 [Byte1]: 37
7806 23:09:42.740039
7807 23:09:42.740447 Set Vref, RX VrefLevel [Byte0]: 38
7808 23:09:42.743109 [Byte1]: 38
7809 23:09:42.747174
7810 23:09:42.747596 Set Vref, RX VrefLevel [Byte0]: 39
7811 23:09:42.750652 [Byte1]: 39
7812 23:09:42.755026
7813 23:09:42.755608 Set Vref, RX VrefLevel [Byte0]: 40
7814 23:09:42.758297 [Byte1]: 40
7815 23:09:42.762349
7816 23:09:42.762766 Set Vref, RX VrefLevel [Byte0]: 41
7817 23:09:42.768897 [Byte1]: 41
7818 23:09:42.769379
7819 23:09:42.772681 Set Vref, RX VrefLevel [Byte0]: 42
7820 23:09:42.775451 [Byte1]: 42
7821 23:09:42.775869
7822 23:09:42.778927 Set Vref, RX VrefLevel [Byte0]: 43
7823 23:09:42.782298 [Byte1]: 43
7824 23:09:42.782730
7825 23:09:42.785691 Set Vref, RX VrefLevel [Byte0]: 44
7826 23:09:42.789013 [Byte1]: 44
7827 23:09:42.793123
7828 23:09:42.793540 Set Vref, RX VrefLevel [Byte0]: 45
7829 23:09:42.795974 [Byte1]: 45
7830 23:09:42.800191
7831 23:09:42.800599 Set Vref, RX VrefLevel [Byte0]: 46
7832 23:09:42.804021 [Byte1]: 46
7833 23:09:42.808007
7834 23:09:42.808417 Set Vref, RX VrefLevel [Byte0]: 47
7835 23:09:42.811615 [Byte1]: 47
7836 23:09:42.815960
7837 23:09:42.816389 Set Vref, RX VrefLevel [Byte0]: 48
7838 23:09:42.818776 [Byte1]: 48
7839 23:09:42.823145
7840 23:09:42.823668 Set Vref, RX VrefLevel [Byte0]: 49
7841 23:09:42.826474 [Byte1]: 49
7842 23:09:42.830655
7843 23:09:42.831088 Set Vref, RX VrefLevel [Byte0]: 50
7844 23:09:42.834169 [Byte1]: 50
7845 23:09:42.838480
7846 23:09:42.838891 Set Vref, RX VrefLevel [Byte0]: 51
7847 23:09:42.841877 [Byte1]: 51
7848 23:09:42.845914
7849 23:09:42.846319 Set Vref, RX VrefLevel [Byte0]: 52
7850 23:09:42.849379 [Byte1]: 52
7851 23:09:42.853536
7852 23:09:42.854194 Set Vref, RX VrefLevel [Byte0]: 53
7853 23:09:42.856700 [Byte1]: 53
7854 23:09:42.861146
7855 23:09:42.861566 Set Vref, RX VrefLevel [Byte0]: 54
7856 23:09:42.864293 [Byte1]: 54
7857 23:09:42.868945
7858 23:09:42.869358 Set Vref, RX VrefLevel [Byte0]: 55
7859 23:09:42.871716 [Byte1]: 55
7860 23:09:42.876658
7861 23:09:42.877112 Set Vref, RX VrefLevel [Byte0]: 56
7862 23:09:42.879624 [Byte1]: 56
7863 23:09:42.883528
7864 23:09:42.884053 Set Vref, RX VrefLevel [Byte0]: 57
7865 23:09:42.887207 [Byte1]: 57
7866 23:09:42.891185
7867 23:09:42.891886 Set Vref, RX VrefLevel [Byte0]: 58
7868 23:09:42.894828 [Byte1]: 58
7869 23:09:42.898720
7870 23:09:42.899177 Set Vref, RX VrefLevel [Byte0]: 59
7871 23:09:42.902160 [Byte1]: 59
7872 23:09:42.906927
7873 23:09:42.907627 Set Vref, RX VrefLevel [Byte0]: 60
7874 23:09:42.909713 [Byte1]: 60
7875 23:09:42.914111
7876 23:09:42.914524 Set Vref, RX VrefLevel [Byte0]: 61
7877 23:09:42.917828 [Byte1]: 61
7878 23:09:42.921878
7879 23:09:42.922289 Set Vref, RX VrefLevel [Byte0]: 62
7880 23:09:42.925113 [Byte1]: 62
7881 23:09:42.929232
7882 23:09:42.929748 Set Vref, RX VrefLevel [Byte0]: 63
7883 23:09:42.932417 [Byte1]: 63
7884 23:09:42.936675
7885 23:09:42.937248 Set Vref, RX VrefLevel [Byte0]: 64
7886 23:09:42.940103 [Byte1]: 64
7887 23:09:42.944184
7888 23:09:42.944634 Set Vref, RX VrefLevel [Byte0]: 65
7889 23:09:42.947498 [Byte1]: 65
7890 23:09:42.951957
7891 23:09:42.952400 Set Vref, RX VrefLevel [Byte0]: 66
7892 23:09:42.954997 [Byte1]: 66
7893 23:09:42.959815
7894 23:09:42.960230 Set Vref, RX VrefLevel [Byte0]: 67
7895 23:09:42.962737 [Byte1]: 67
7896 23:09:42.966980
7897 23:09:42.967405 Set Vref, RX VrefLevel [Byte0]: 68
7898 23:09:42.970483 [Byte1]: 68
7899 23:09:42.974379
7900 23:09:42.974948 Set Vref, RX VrefLevel [Byte0]: 69
7901 23:09:42.977879 [Byte1]: 69
7902 23:09:42.982514
7903 23:09:42.982942 Set Vref, RX VrefLevel [Byte0]: 70
7904 23:09:42.985334 [Byte1]: 70
7905 23:09:42.990210
7906 23:09:42.990622 Set Vref, RX VrefLevel [Byte0]: 71
7907 23:09:42.993131 [Byte1]: 71
7908 23:09:42.997342
7909 23:09:42.997917 Set Vref, RX VrefLevel [Byte0]: 72
7910 23:09:43.000466 [Byte1]: 72
7911 23:09:43.005152
7912 23:09:43.005567 Set Vref, RX VrefLevel [Byte0]: 73
7913 23:09:43.008228 [Byte1]: 73
7914 23:09:43.012300
7915 23:09:43.012734 Set Vref, RX VrefLevel [Byte0]: 74
7916 23:09:43.015688 [Byte1]: 74
7917 23:09:43.019902
7918 23:09:43.020329 Set Vref, RX VrefLevel [Byte0]: 75
7919 23:09:43.023539 [Byte1]: 75
7920 23:09:43.027880
7921 23:09:43.028317 Final RX Vref Byte 0 = 56 to rank0
7922 23:09:43.031037 Final RX Vref Byte 1 = 56 to rank0
7923 23:09:43.034055 Final RX Vref Byte 0 = 56 to rank1
7924 23:09:43.037626 Final RX Vref Byte 1 = 56 to rank1==
7925 23:09:43.041136 Dram Type= 6, Freq= 0, CH_0, rank 0
7926 23:09:43.047697 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7927 23:09:43.048122 ==
7928 23:09:43.048455 DQS Delay:
7929 23:09:43.048921 DQS0 = 0, DQS1 = 0
7930 23:09:43.051161 DQM Delay:
7931 23:09:43.051786 DQM0 = 134, DQM1 = 127
7932 23:09:43.054005 DQ Delay:
7933 23:09:43.057421 DQ0 =134, DQ1 =138, DQ2 =134, DQ3 =130
7934 23:09:43.060485 DQ4 =132, DQ5 =124, DQ6 =142, DQ7 =138
7935 23:09:43.064235 DQ8 =116, DQ9 =118, DQ10 =128, DQ11 =120
7936 23:09:43.067515 DQ12 =130, DQ13 =132, DQ14 =138, DQ15 =134
7937 23:09:43.067933
7938 23:09:43.068260
7939 23:09:43.068567
7940 23:09:43.070976 [DramC_TX_OE_Calibration] TA2
7941 23:09:43.074030 Original DQ_B0 (3 6) =30, OEN = 27
7942 23:09:43.077275 Original DQ_B1 (3 6) =30, OEN = 27
7943 23:09:43.080744 24, 0x0, End_B0=24 End_B1=24
7944 23:09:43.081169 25, 0x0, End_B0=25 End_B1=25
7945 23:09:43.084147 26, 0x0, End_B0=26 End_B1=26
7946 23:09:43.087654 27, 0x0, End_B0=27 End_B1=27
7947 23:09:43.090987 28, 0x0, End_B0=28 End_B1=28
7948 23:09:43.093928 29, 0x0, End_B0=29 End_B1=29
7949 23:09:43.094399 30, 0x0, End_B0=30 End_B1=30
7950 23:09:43.096964 31, 0x4141, End_B0=30 End_B1=30
7951 23:09:43.100738 Byte0 end_step=30 best_step=27
7952 23:09:43.103725 Byte1 end_step=30 best_step=27
7953 23:09:43.107285 Byte0 TX OE(2T, 0.5T) = (3, 3)
7954 23:09:43.110382 Byte1 TX OE(2T, 0.5T) = (3, 3)
7955 23:09:43.110800
7956 23:09:43.111127
7957 23:09:43.117159 [DQSOSCAuto] RK0, (LSB)MR18= 0x2521, (MSB)MR19= 0x303, tDQSOscB0 = 393 ps tDQSOscB1 = 391 ps
7958 23:09:43.120724 CH0 RK0: MR19=303, MR18=2521
7959 23:09:43.127401 CH0_RK0: MR19=0x303, MR18=0x2521, DQSOSC=391, MR23=63, INC=24, DEC=16
7960 23:09:43.127819
7961 23:09:43.130415 ----->DramcWriteLeveling(PI) begin...
7962 23:09:43.130838 ==
7963 23:09:43.133881 Dram Type= 6, Freq= 0, CH_0, rank 1
7964 23:09:43.137131 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7965 23:09:43.137551 ==
7966 23:09:43.140214 Write leveling (Byte 0): 34 => 34
7967 23:09:43.143898 Write leveling (Byte 1): 28 => 28
7968 23:09:43.146958 DramcWriteLeveling(PI) end<-----
7969 23:09:43.147380
7970 23:09:43.147722 ==
7971 23:09:43.150519 Dram Type= 6, Freq= 0, CH_0, rank 1
7972 23:09:43.154042 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7973 23:09:43.154462 ==
7974 23:09:43.157480 [Gating] SW mode calibration
7975 23:09:43.163797 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7976 23:09:43.170654 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7977 23:09:43.173768 1 4 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 1)
7978 23:09:43.176943 1 4 4 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
7979 23:09:43.183858 1 4 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7980 23:09:43.187194 1 4 12 | B1->B0 | 2323 2626 | 0 0 | (0 0) (1 1)
7981 23:09:43.190615 1 4 16 | B1->B0 | 3131 3434 | 1 0 | (1 1) (0 0)
7982 23:09:43.197206 1 4 20 | B1->B0 | 3434 3636 | 1 1 | (1 1) (1 1)
7983 23:09:43.200554 1 4 24 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7984 23:09:43.203896 1 4 28 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7985 23:09:43.210320 1 5 0 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7986 23:09:43.213872 1 5 4 | B1->B0 | 3434 3534 | 1 1 | (1 1) (0 0)
7987 23:09:43.216832 1 5 8 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
7988 23:09:43.223610 1 5 12 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (1 0)
7989 23:09:43.227147 1 5 16 | B1->B0 | 2e2e 2727 | 0 0 | (1 0) (0 0)
7990 23:09:43.230243 1 5 20 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
7991 23:09:43.236701 1 5 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7992 23:09:43.240275 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7993 23:09:43.243329 1 6 0 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
7994 23:09:43.250153 1 6 4 | B1->B0 | 2323 2625 | 0 1 | (0 0) (0 0)
7995 23:09:43.253943 1 6 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7996 23:09:43.256892 1 6 12 | B1->B0 | 2323 3030 | 0 1 | (0 0) (0 0)
7997 23:09:43.263377 1 6 16 | B1->B0 | 3535 4545 | 0 0 | (0 0) (0 0)
7998 23:09:43.266837 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7999 23:09:43.270111 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8000 23:09:43.276556 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8001 23:09:43.279926 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8002 23:09:43.283243 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8003 23:09:43.289991 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8004 23:09:43.293086 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8005 23:09:43.296716 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8006 23:09:43.303115 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8007 23:09:43.306558 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8008 23:09:43.310039 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8009 23:09:43.316096 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8010 23:09:43.319532 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8011 23:09:43.322596 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8012 23:09:43.326109 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8013 23:09:43.332937 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8014 23:09:43.335904 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8015 23:09:43.339179 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8016 23:09:43.345754 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8017 23:09:43.349135 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8018 23:09:43.352478 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8019 23:09:43.358824 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8020 23:09:43.362622 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8021 23:09:43.365868 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8022 23:09:43.372906 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8023 23:09:43.376438 Total UI for P1: 0, mck2ui 16
8024 23:09:43.379528 best dqsien dly found for B0: ( 1, 9, 12)
8025 23:09:43.382535 Total UI for P1: 0, mck2ui 16
8026 23:09:43.385902 best dqsien dly found for B1: ( 1, 9, 12)
8027 23:09:43.389383 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8028 23:09:43.392548 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8029 23:09:43.392962
8030 23:09:43.396222 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8031 23:09:43.399490 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8032 23:09:43.402802 [Gating] SW calibration Done
8033 23:09:43.403279 ==
8034 23:09:43.405942 Dram Type= 6, Freq= 0, CH_0, rank 1
8035 23:09:43.409332 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8036 23:09:43.409842 ==
8037 23:09:43.412381 RX Vref Scan: 0
8038 23:09:43.412847
8039 23:09:43.413328 RX Vref 0 -> 0, step: 1
8040 23:09:43.416040
8041 23:09:43.416582 RX Delay 0 -> 252, step: 8
8042 23:09:43.422712 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8043 23:09:43.425686 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8044 23:09:43.428990 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8045 23:09:43.432295 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8046 23:09:43.435874 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8047 23:09:43.439383 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8048 23:09:43.445567 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8049 23:09:43.449490 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8050 23:09:43.452758 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8051 23:09:43.455712 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8052 23:09:43.459265 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8053 23:09:43.466325 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8054 23:09:43.469084 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8055 23:09:43.472525 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8056 23:09:43.475943 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8057 23:09:43.482283 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8058 23:09:43.482702 ==
8059 23:09:43.485466 Dram Type= 6, Freq= 0, CH_0, rank 1
8060 23:09:43.488956 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8061 23:09:43.489374 ==
8062 23:09:43.489750 DQS Delay:
8063 23:09:43.492313 DQS0 = 0, DQS1 = 0
8064 23:09:43.492725 DQM Delay:
8065 23:09:43.495615 DQM0 = 137, DQM1 = 128
8066 23:09:43.496090 DQ Delay:
8067 23:09:43.498845 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
8068 23:09:43.502477 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8069 23:09:43.505399 DQ8 =119, DQ9 =119, DQ10 =127, DQ11 =119
8070 23:09:43.508994 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8071 23:09:43.509475
8072 23:09:43.509862
8073 23:09:43.511824 ==
8074 23:09:43.515102 Dram Type= 6, Freq= 0, CH_0, rank 1
8075 23:09:43.518663 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8076 23:09:43.519081 ==
8077 23:09:43.519410
8078 23:09:43.519782
8079 23:09:43.521933 TX Vref Scan disable
8080 23:09:43.522345 == TX Byte 0 ==
8081 23:09:43.528733 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8082 23:09:43.531598 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8083 23:09:43.532079 == TX Byte 1 ==
8084 23:09:43.538914 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8085 23:09:43.542271 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8086 23:09:43.542878 ==
8087 23:09:43.545028 Dram Type= 6, Freq= 0, CH_0, rank 1
8088 23:09:43.548502 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8089 23:09:43.548917 ==
8090 23:09:43.562161
8091 23:09:43.565851 TX Vref early break, caculate TX vref
8092 23:09:43.568569 TX Vref=16, minBit 1, minWin=23, winSum=392
8093 23:09:43.572208 TX Vref=18, minBit 1, minWin=23, winSum=394
8094 23:09:43.575836 TX Vref=20, minBit 1, minWin=24, winSum=406
8095 23:09:43.578744 TX Vref=22, minBit 1, minWin=24, winSum=409
8096 23:09:43.582395 TX Vref=24, minBit 7, minWin=24, winSum=420
8097 23:09:43.589113 TX Vref=26, minBit 4, minWin=25, winSum=427
8098 23:09:43.592130 TX Vref=28, minBit 2, minWin=25, winSum=422
8099 23:09:43.595892 TX Vref=30, minBit 0, minWin=25, winSum=420
8100 23:09:43.598962 TX Vref=32, minBit 0, minWin=25, winSum=410
8101 23:09:43.602008 TX Vref=34, minBit 0, minWin=24, winSum=401
8102 23:09:43.609033 [TxChooseVref] Worse bit 4, Min win 25, Win sum 427, Final Vref 26
8103 23:09:43.609468
8104 23:09:43.611944 Final TX Range 0 Vref 26
8105 23:09:43.612352
8106 23:09:43.612673 ==
8107 23:09:43.615698 Dram Type= 6, Freq= 0, CH_0, rank 1
8108 23:09:43.618686 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8109 23:09:43.619099 ==
8110 23:09:43.619422
8111 23:09:43.619723
8112 23:09:43.622300 TX Vref Scan disable
8113 23:09:43.628682 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8114 23:09:43.629092 == TX Byte 0 ==
8115 23:09:43.632378 u2DelayCellOfst[0]=13 cells (4 PI)
8116 23:09:43.635737 u2DelayCellOfst[1]=13 cells (4 PI)
8117 23:09:43.638552 u2DelayCellOfst[2]=10 cells (3 PI)
8118 23:09:43.642120 u2DelayCellOfst[3]=10 cells (3 PI)
8119 23:09:43.645256 u2DelayCellOfst[4]=6 cells (2 PI)
8120 23:09:43.648743 u2DelayCellOfst[5]=0 cells (0 PI)
8121 23:09:43.652180 u2DelayCellOfst[6]=13 cells (4 PI)
8122 23:09:43.652703 u2DelayCellOfst[7]=13 cells (4 PI)
8123 23:09:43.658866 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8124 23:09:43.661726 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8125 23:09:43.665337 == TX Byte 1 ==
8126 23:09:43.665792 u2DelayCellOfst[8]=0 cells (0 PI)
8127 23:09:43.669058 u2DelayCellOfst[9]=0 cells (0 PI)
8128 23:09:43.672062 u2DelayCellOfst[10]=3 cells (1 PI)
8129 23:09:43.675688 u2DelayCellOfst[11]=0 cells (0 PI)
8130 23:09:43.678704 u2DelayCellOfst[12]=6 cells (2 PI)
8131 23:09:43.681685 u2DelayCellOfst[13]=10 cells (3 PI)
8132 23:09:43.685350 u2DelayCellOfst[14]=13 cells (4 PI)
8133 23:09:43.688308 u2DelayCellOfst[15]=6 cells (2 PI)
8134 23:09:43.691777 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8135 23:09:43.698325 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8136 23:09:43.698716 DramC Write-DBI on
8137 23:09:43.699046 ==
8138 23:09:43.701746 Dram Type= 6, Freq= 0, CH_0, rank 1
8139 23:09:43.704928 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8140 23:09:43.708312 ==
8141 23:09:43.708736
8142 23:09:43.709056
8143 23:09:43.709353 TX Vref Scan disable
8144 23:09:43.711547 == TX Byte 0 ==
8145 23:09:43.715055 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
8146 23:09:43.718498 == TX Byte 1 ==
8147 23:09:43.721536 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8148 23:09:43.722001 DramC Write-DBI off
8149 23:09:43.725091
8150 23:09:43.725493 [DATLAT]
8151 23:09:43.725888 Freq=1600, CH0 RK1
8152 23:09:43.726200
8153 23:09:43.728217 DATLAT Default: 0xf
8154 23:09:43.728815 0, 0xFFFF, sum = 0
8155 23:09:43.731670 1, 0xFFFF, sum = 0
8156 23:09:43.732098 2, 0xFFFF, sum = 0
8157 23:09:43.735266 3, 0xFFFF, sum = 0
8158 23:09:43.738221 4, 0xFFFF, sum = 0
8159 23:09:43.738649 5, 0xFFFF, sum = 0
8160 23:09:43.741838 6, 0xFFFF, sum = 0
8161 23:09:43.742281 7, 0xFFFF, sum = 0
8162 23:09:43.744915 8, 0xFFFF, sum = 0
8163 23:09:43.745342 9, 0xFFFF, sum = 0
8164 23:09:43.748576 10, 0xFFFF, sum = 0
8165 23:09:43.749003 11, 0xFFFF, sum = 0
8166 23:09:43.751517 12, 0xFFFF, sum = 0
8167 23:09:43.751999 13, 0xFFFF, sum = 0
8168 23:09:43.755065 14, 0x0, sum = 1
8169 23:09:43.755519 15, 0x0, sum = 2
8170 23:09:43.758262 16, 0x0, sum = 3
8171 23:09:43.758683 17, 0x0, sum = 4
8172 23:09:43.761450 best_step = 15
8173 23:09:43.761954
8174 23:09:43.762382 ==
8175 23:09:43.764933 Dram Type= 6, Freq= 0, CH_0, rank 1
8176 23:09:43.768225 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8177 23:09:43.768651 ==
8178 23:09:43.769175 RX Vref Scan: 0
8179 23:09:43.771784
8180 23:09:43.772199 RX Vref 0 -> 0, step: 1
8181 23:09:43.772626
8182 23:09:43.774922 RX Delay 19 -> 252, step: 4
8183 23:09:43.778011 iDelay=191, Bit 0, Center 134 (83 ~ 186) 104
8184 23:09:43.784655 iDelay=191, Bit 1, Center 138 (91 ~ 186) 96
8185 23:09:43.788307 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8186 23:09:43.791148 iDelay=191, Bit 3, Center 134 (83 ~ 186) 104
8187 23:09:43.794832 iDelay=191, Bit 4, Center 136 (87 ~ 186) 100
8188 23:09:43.797785 iDelay=191, Bit 5, Center 126 (75 ~ 178) 104
8189 23:09:43.804344 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8190 23:09:43.808004 iDelay=191, Bit 7, Center 140 (91 ~ 190) 100
8191 23:09:43.811321 iDelay=191, Bit 8, Center 118 (67 ~ 170) 104
8192 23:09:43.814933 iDelay=191, Bit 9, Center 118 (67 ~ 170) 104
8193 23:09:43.817996 iDelay=191, Bit 10, Center 126 (75 ~ 178) 104
8194 23:09:43.824501 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8195 23:09:43.827721 iDelay=191, Bit 12, Center 132 (83 ~ 182) 100
8196 23:09:43.831064 iDelay=191, Bit 13, Center 134 (83 ~ 186) 104
8197 23:09:43.834433 iDelay=191, Bit 14, Center 136 (83 ~ 190) 108
8198 23:09:43.837713 iDelay=191, Bit 15, Center 134 (83 ~ 186) 104
8199 23:09:43.840985 ==
8200 23:09:43.844747 Dram Type= 6, Freq= 0, CH_0, rank 1
8201 23:09:43.847729 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8202 23:09:43.848148 ==
8203 23:09:43.848479 DQS Delay:
8204 23:09:43.851302 DQS0 = 0, DQS1 = 0
8205 23:09:43.851722 DQM Delay:
8206 23:09:43.854312 DQM0 = 134, DQM1 = 127
8207 23:09:43.854725 DQ Delay:
8208 23:09:43.858110 DQ0 =134, DQ1 =138, DQ2 =130, DQ3 =134
8209 23:09:43.861061 DQ4 =136, DQ5 =126, DQ6 =140, DQ7 =140
8210 23:09:43.864556 DQ8 =118, DQ9 =118, DQ10 =126, DQ11 =118
8211 23:09:43.867802 DQ12 =132, DQ13 =134, DQ14 =136, DQ15 =134
8212 23:09:43.868219
8213 23:09:43.868549
8214 23:09:43.868857
8215 23:09:43.871016 [DramC_TX_OE_Calibration] TA2
8216 23:09:43.874156 Original DQ_B0 (3 6) =30, OEN = 27
8217 23:09:43.877787 Original DQ_B1 (3 6) =30, OEN = 27
8218 23:09:43.881297 24, 0x0, End_B0=24 End_B1=24
8219 23:09:43.884127 25, 0x0, End_B0=25 End_B1=25
8220 23:09:43.884562 26, 0x0, End_B0=26 End_B1=26
8221 23:09:43.887587 27, 0x0, End_B0=27 End_B1=27
8222 23:09:43.891073 28, 0x0, End_B0=28 End_B1=28
8223 23:09:43.894239 29, 0x0, End_B0=29 End_B1=29
8224 23:09:43.897837 30, 0x0, End_B0=30 End_B1=30
8225 23:09:43.898274 31, 0x4141, End_B0=30 End_B1=30
8226 23:09:43.900837 Byte0 end_step=30 best_step=27
8227 23:09:43.904377 Byte1 end_step=30 best_step=27
8228 23:09:43.908034 Byte0 TX OE(2T, 0.5T) = (3, 3)
8229 23:09:43.911138 Byte1 TX OE(2T, 0.5T) = (3, 3)
8230 23:09:43.911594
8231 23:09:43.912113
8232 23:09:43.917463 [DQSOSCAuto] RK1, (LSB)MR18= 0x210a, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 393 ps
8233 23:09:43.921095 CH0 RK1: MR19=303, MR18=210A
8234 23:09:43.927812 CH0_RK1: MR19=0x303, MR18=0x210A, DQSOSC=393, MR23=63, INC=23, DEC=15
8235 23:09:43.930824 [RxdqsGatingPostProcess] freq 1600
8236 23:09:43.937367 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8237 23:09:43.937918 best DQS0 dly(2T, 0.5T) = (1, 1)
8238 23:09:43.940893 best DQS1 dly(2T, 0.5T) = (1, 1)
8239 23:09:43.944205 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8240 23:09:43.947532 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8241 23:09:43.950706 best DQS0 dly(2T, 0.5T) = (1, 1)
8242 23:09:43.953916 best DQS1 dly(2T, 0.5T) = (1, 1)
8243 23:09:43.957260 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8244 23:09:43.960781 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8245 23:09:43.964364 Pre-setting of DQS Precalculation
8246 23:09:43.967278 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8247 23:09:43.967703 ==
8248 23:09:43.970788 Dram Type= 6, Freq= 0, CH_1, rank 0
8249 23:09:43.977097 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8250 23:09:43.977679 ==
8251 23:09:43.980451 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8252 23:09:43.987526 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8253 23:09:43.990412 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8254 23:09:43.997461 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8255 23:09:44.004345 [CA 0] Center 42 (13~72) winsize 60
8256 23:09:44.007711 [CA 1] Center 42 (13~72) winsize 60
8257 23:09:44.011513 [CA 2] Center 38 (9~68) winsize 60
8258 23:09:44.014552 [CA 3] Center 38 (9~67) winsize 59
8259 23:09:44.017628 [CA 4] Center 39 (10~68) winsize 59
8260 23:09:44.021340 [CA 5] Center 37 (8~67) winsize 60
8261 23:09:44.021589
8262 23:09:44.024870 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8263 23:09:44.025048
8264 23:09:44.027821 [CATrainingPosCal] consider 1 rank data
8265 23:09:44.031296 u2DelayCellTimex100 = 290/100 ps
8266 23:09:44.034395 CA0 delay=42 (13~72),Diff = 5 PI (16 cell)
8267 23:09:44.041263 CA1 delay=42 (13~72),Diff = 5 PI (16 cell)
8268 23:09:44.044275 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8269 23:09:44.047957 CA3 delay=38 (9~67),Diff = 1 PI (3 cell)
8270 23:09:44.051468 CA4 delay=39 (10~68),Diff = 2 PI (6 cell)
8271 23:09:44.054319 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8272 23:09:44.054529
8273 23:09:44.057643 CA PerBit enable=1, Macro0, CA PI delay=37
8274 23:09:44.057898
8275 23:09:44.061358 [CBTSetCACLKResult] CA Dly = 37
8276 23:09:44.064299 CS Dly: 10 (0~41)
8277 23:09:44.068293 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8278 23:09:44.071445 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8279 23:09:44.071908 ==
8280 23:09:44.074331 Dram Type= 6, Freq= 0, CH_1, rank 1
8281 23:09:44.077823 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8282 23:09:44.081296 ==
8283 23:09:44.084551 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8284 23:09:44.087950 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8285 23:09:44.094166 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8286 23:09:44.101132 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8287 23:09:44.108244 [CA 0] Center 42 (12~72) winsize 61
8288 23:09:44.111336 [CA 1] Center 42 (12~72) winsize 61
8289 23:09:44.114882 [CA 2] Center 38 (9~68) winsize 60
8290 23:09:44.118071 [CA 3] Center 38 (8~68) winsize 61
8291 23:09:44.121411 [CA 4] Center 38 (8~68) winsize 61
8292 23:09:44.124357 [CA 5] Center 37 (7~67) winsize 61
8293 23:09:44.124774
8294 23:09:44.127875 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8295 23:09:44.128363
8296 23:09:44.131350 [CATrainingPosCal] consider 2 rank data
8297 23:09:44.134935 u2DelayCellTimex100 = 290/100 ps
8298 23:09:44.141366 CA0 delay=42 (13~72),Diff = 5 PI (16 cell)
8299 23:09:44.144577 CA1 delay=42 (13~72),Diff = 5 PI (16 cell)
8300 23:09:44.147671 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8301 23:09:44.151232 CA3 delay=38 (9~67),Diff = 1 PI (3 cell)
8302 23:09:44.154705 CA4 delay=39 (10~68),Diff = 2 PI (6 cell)
8303 23:09:44.158074 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8304 23:09:44.158373
8305 23:09:44.161059 CA PerBit enable=1, Macro0, CA PI delay=37
8306 23:09:44.161354
8307 23:09:44.164441 [CBTSetCACLKResult] CA Dly = 37
8308 23:09:44.168055 CS Dly: 12 (0~45)
8309 23:09:44.171060 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8310 23:09:44.174451 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8311 23:09:44.174773
8312 23:09:44.177716 ----->DramcWriteLeveling(PI) begin...
8313 23:09:44.178082 ==
8314 23:09:44.181143 Dram Type= 6, Freq= 0, CH_1, rank 0
8315 23:09:44.187896 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8316 23:09:44.188456 ==
8317 23:09:44.190963 Write leveling (Byte 0): 26 => 26
8318 23:09:44.191358 Write leveling (Byte 1): 28 => 28
8319 23:09:44.194376 DramcWriteLeveling(PI) end<-----
8320 23:09:44.194794
8321 23:09:44.195118 ==
8322 23:09:44.198014 Dram Type= 6, Freq= 0, CH_1, rank 0
8323 23:09:44.204575 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8324 23:09:44.204987 ==
8325 23:09:44.207855 [Gating] SW mode calibration
8326 23:09:44.214451 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8327 23:09:44.217910 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8328 23:09:44.224710 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8329 23:09:44.228069 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8330 23:09:44.231216 1 4 8 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (1 1)
8331 23:09:44.237801 1 4 12 | B1->B0 | 3131 3434 | 1 0 | (1 1) (0 0)
8332 23:09:44.241397 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8333 23:09:44.244379 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8334 23:09:44.250956 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8335 23:09:44.254494 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8336 23:09:44.257540 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8337 23:09:44.264171 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8338 23:09:44.267328 1 5 8 | B1->B0 | 3434 3030 | 1 0 | (1 0) (0 1)
8339 23:09:44.271162 1 5 12 | B1->B0 | 2626 2323 | 0 0 | (1 0) (1 0)
8340 23:09:44.277480 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8341 23:09:44.280505 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8342 23:09:44.284021 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8343 23:09:44.290741 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8344 23:09:44.293782 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8345 23:09:44.297346 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8346 23:09:44.300583 1 6 8 | B1->B0 | 2525 3636 | 0 0 | (0 0) (0 0)
8347 23:09:44.306859 1 6 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8348 23:09:44.310168 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8349 23:09:44.316818 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8350 23:09:44.320015 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8351 23:09:44.323687 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8352 23:09:44.326942 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8353 23:09:44.333503 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8354 23:09:44.337151 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8355 23:09:44.340149 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8356 23:09:44.347115 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8357 23:09:44.350244 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8358 23:09:44.353239 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8359 23:09:44.359829 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8360 23:09:44.363356 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8361 23:09:44.367114 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8362 23:09:44.373409 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8363 23:09:44.376878 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8364 23:09:44.380012 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8365 23:09:44.386616 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8366 23:09:44.390080 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8367 23:09:44.393772 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8368 23:09:44.400163 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8369 23:09:44.403106 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8370 23:09:44.406868 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8371 23:09:44.413294 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8372 23:09:44.416785 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8373 23:09:44.419997 Total UI for P1: 0, mck2ui 16
8374 23:09:44.423416 best dqsien dly found for B0: ( 1, 9, 10)
8375 23:09:44.426374 Total UI for P1: 0, mck2ui 16
8376 23:09:44.429784 best dqsien dly found for B1: ( 1, 9, 10)
8377 23:09:44.433303 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8378 23:09:44.436213 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8379 23:09:44.436642
8380 23:09:44.439807 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8381 23:09:44.442824 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8382 23:09:44.446407 [Gating] SW calibration Done
8383 23:09:44.446824 ==
8384 23:09:44.449502 Dram Type= 6, Freq= 0, CH_1, rank 0
8385 23:09:44.453085 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8386 23:09:44.456202 ==
8387 23:09:44.456641 RX Vref Scan: 0
8388 23:09:44.456983
8389 23:09:44.459711 RX Vref 0 -> 0, step: 1
8390 23:09:44.460124
8391 23:09:44.462823 RX Delay 0 -> 252, step: 8
8392 23:09:44.466361 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8393 23:09:44.469330 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8394 23:09:44.472768 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8395 23:09:44.476561 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8396 23:09:44.479127 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8397 23:09:44.485854 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8398 23:09:44.489383 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8399 23:09:44.492847 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8400 23:09:44.496228 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
8401 23:09:44.499354 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8402 23:09:44.505876 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8403 23:09:44.509562 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8404 23:09:44.512415 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8405 23:09:44.515763 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8406 23:09:44.522381 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8407 23:09:44.525697 iDelay=200, Bit 15, Center 147 (96 ~ 199) 104
8408 23:09:44.526134 ==
8409 23:09:44.529018 Dram Type= 6, Freq= 0, CH_1, rank 0
8410 23:09:44.533023 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8411 23:09:44.533710 ==
8412 23:09:44.534062 DQS Delay:
8413 23:09:44.535742 DQS0 = 0, DQS1 = 0
8414 23:09:44.536184 DQM Delay:
8415 23:09:44.539402 DQM0 = 136, DQM1 = 133
8416 23:09:44.539891 DQ Delay:
8417 23:09:44.542877 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8418 23:09:44.545619 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8419 23:09:44.549329 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =127
8420 23:09:44.552487 DQ12 =139, DQ13 =143, DQ14 =139, DQ15 =147
8421 23:09:44.556260
8422 23:09:44.556673
8423 23:09:44.557002 ==
8424 23:09:44.559075 Dram Type= 6, Freq= 0, CH_1, rank 0
8425 23:09:44.562484 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8426 23:09:44.562907 ==
8427 23:09:44.563237
8428 23:09:44.563600
8429 23:09:44.565873 TX Vref Scan disable
8430 23:09:44.566287 == TX Byte 0 ==
8431 23:09:44.572645 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8432 23:09:44.576029 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8433 23:09:44.576475 == TX Byte 1 ==
8434 23:09:44.582672 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8435 23:09:44.585638 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8436 23:09:44.586144 ==
8437 23:09:44.589138 Dram Type= 6, Freq= 0, CH_1, rank 0
8438 23:09:44.592528 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8439 23:09:44.592976 ==
8440 23:09:44.607208
8441 23:09:44.610190 TX Vref early break, caculate TX vref
8442 23:09:44.613731 TX Vref=16, minBit 3, minWin=22, winSum=374
8443 23:09:44.616702 TX Vref=18, minBit 0, minWin=23, winSum=382
8444 23:09:44.620327 TX Vref=20, minBit 1, minWin=24, winSum=397
8445 23:09:44.624081 TX Vref=22, minBit 0, minWin=24, winSum=405
8446 23:09:44.627063 TX Vref=24, minBit 0, minWin=25, winSum=414
8447 23:09:44.633447 TX Vref=26, minBit 0, minWin=25, winSum=424
8448 23:09:44.636958 TX Vref=28, minBit 0, minWin=25, winSum=425
8449 23:09:44.640072 TX Vref=30, minBit 0, minWin=24, winSum=417
8450 23:09:44.643618 TX Vref=32, minBit 6, minWin=24, winSum=413
8451 23:09:44.646717 TX Vref=34, minBit 0, minWin=24, winSum=404
8452 23:09:44.650296 TX Vref=36, minBit 0, minWin=23, winSum=389
8453 23:09:44.656613 [TxChooseVref] Worse bit 0, Min win 25, Win sum 425, Final Vref 28
8454 23:09:44.657032
8455 23:09:44.659855 Final TX Range 0 Vref 28
8456 23:09:44.660278
8457 23:09:44.660609 ==
8458 23:09:44.663059 Dram Type= 6, Freq= 0, CH_1, rank 0
8459 23:09:44.666711 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8460 23:09:44.667131 ==
8461 23:09:44.667462
8462 23:09:44.667765
8463 23:09:44.669670 TX Vref Scan disable
8464 23:09:44.676716 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8465 23:09:44.677269 == TX Byte 0 ==
8466 23:09:44.679332 u2DelayCellOfst[0]=20 cells (6 PI)
8467 23:09:44.682877 u2DelayCellOfst[1]=10 cells (3 PI)
8468 23:09:44.686360 u2DelayCellOfst[2]=0 cells (0 PI)
8469 23:09:44.689841 u2DelayCellOfst[3]=10 cells (3 PI)
8470 23:09:44.693157 u2DelayCellOfst[4]=10 cells (3 PI)
8471 23:09:44.696436 u2DelayCellOfst[5]=20 cells (6 PI)
8472 23:09:44.699558 u2DelayCellOfst[6]=20 cells (6 PI)
8473 23:09:44.703116 u2DelayCellOfst[7]=6 cells (2 PI)
8474 23:09:44.706245 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8475 23:09:44.709229 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8476 23:09:44.712817 == TX Byte 1 ==
8477 23:09:44.715832 u2DelayCellOfst[8]=0 cells (0 PI)
8478 23:09:44.719353 u2DelayCellOfst[9]=6 cells (2 PI)
8479 23:09:44.722990 u2DelayCellOfst[10]=13 cells (4 PI)
8480 23:09:44.723407 u2DelayCellOfst[11]=3 cells (1 PI)
8481 23:09:44.726070 u2DelayCellOfst[12]=16 cells (5 PI)
8482 23:09:44.729630 u2DelayCellOfst[13]=16 cells (5 PI)
8483 23:09:44.732966 u2DelayCellOfst[14]=20 cells (6 PI)
8484 23:09:44.736415 u2DelayCellOfst[15]=16 cells (5 PI)
8485 23:09:44.742433 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8486 23:09:44.745857 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8487 23:09:44.746277 DramC Write-DBI on
8488 23:09:44.746604 ==
8489 23:09:44.749044 Dram Type= 6, Freq= 0, CH_1, rank 0
8490 23:09:44.755854 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8491 23:09:44.756293 ==
8492 23:09:44.756671
8493 23:09:44.757028
8494 23:09:44.757346 TX Vref Scan disable
8495 23:09:44.760260 == TX Byte 0 ==
8496 23:09:44.763328 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8497 23:09:44.766804 == TX Byte 1 ==
8498 23:09:44.770114 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8499 23:09:44.773025 DramC Write-DBI off
8500 23:09:44.773440
8501 23:09:44.773821 [DATLAT]
8502 23:09:44.774128 Freq=1600, CH1 RK0
8503 23:09:44.774429
8504 23:09:44.776305 DATLAT Default: 0xf
8505 23:09:44.776721 0, 0xFFFF, sum = 0
8506 23:09:44.779961 1, 0xFFFF, sum = 0
8507 23:09:44.783675 2, 0xFFFF, sum = 0
8508 23:09:44.784103 3, 0xFFFF, sum = 0
8509 23:09:44.786433 4, 0xFFFF, sum = 0
8510 23:09:44.786854 5, 0xFFFF, sum = 0
8511 23:09:44.789924 6, 0xFFFF, sum = 0
8512 23:09:44.790347 7, 0xFFFF, sum = 0
8513 23:09:44.793389 8, 0xFFFF, sum = 0
8514 23:09:44.793869 9, 0xFFFF, sum = 0
8515 23:09:44.796732 10, 0xFFFF, sum = 0
8516 23:09:44.797157 11, 0xFFFF, sum = 0
8517 23:09:44.799816 12, 0xFFFF, sum = 0
8518 23:09:44.800239 13, 0xFFFF, sum = 0
8519 23:09:44.803092 14, 0x0, sum = 1
8520 23:09:44.803578 15, 0x0, sum = 2
8521 23:09:44.806616 16, 0x0, sum = 3
8522 23:09:44.807266 17, 0x0, sum = 4
8523 23:09:44.809864 best_step = 15
8524 23:09:44.810276
8525 23:09:44.810601 ==
8526 23:09:44.813080 Dram Type= 6, Freq= 0, CH_1, rank 0
8527 23:09:44.816563 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8528 23:09:44.817083 ==
8529 23:09:44.819514 RX Vref Scan: 1
8530 23:09:44.819986
8531 23:09:44.820390 Set Vref Range= 24 -> 127
8532 23:09:44.820739
8533 23:09:44.823071 RX Vref 24 -> 127, step: 1
8534 23:09:44.823504
8535 23:09:44.826161 RX Delay 27 -> 252, step: 4
8536 23:09:44.826626
8537 23:09:44.829954 Set Vref, RX VrefLevel [Byte0]: 24
8538 23:09:44.832989 [Byte1]: 24
8539 23:09:44.833525
8540 23:09:44.836052 Set Vref, RX VrefLevel [Byte0]: 25
8541 23:09:44.839380 [Byte1]: 25
8542 23:09:44.839923
8543 23:09:44.842994 Set Vref, RX VrefLevel [Byte0]: 26
8544 23:09:44.846276 [Byte1]: 26
8545 23:09:44.849913
8546 23:09:44.850356 Set Vref, RX VrefLevel [Byte0]: 27
8547 23:09:44.853331 [Byte1]: 27
8548 23:09:44.858066
8549 23:09:44.858493 Set Vref, RX VrefLevel [Byte0]: 28
8550 23:09:44.860895 [Byte1]: 28
8551 23:09:44.865141
8552 23:09:44.865562 Set Vref, RX VrefLevel [Byte0]: 29
8553 23:09:44.868741 [Byte1]: 29
8554 23:09:44.872801
8555 23:09:44.873226 Set Vref, RX VrefLevel [Byte0]: 30
8556 23:09:44.876089 [Byte1]: 30
8557 23:09:44.880466
8558 23:09:44.880901 Set Vref, RX VrefLevel [Byte0]: 31
8559 23:09:44.883753 [Byte1]: 31
8560 23:09:44.888005
8561 23:09:44.888460 Set Vref, RX VrefLevel [Byte0]: 32
8562 23:09:44.890953 [Byte1]: 32
8563 23:09:44.895681
8564 23:09:44.896093 Set Vref, RX VrefLevel [Byte0]: 33
8565 23:09:44.898299 [Byte1]: 33
8566 23:09:44.902896
8567 23:09:44.903307 Set Vref, RX VrefLevel [Byte0]: 34
8568 23:09:44.906230 [Byte1]: 34
8569 23:09:44.910549
8570 23:09:44.910955 Set Vref, RX VrefLevel [Byte0]: 35
8571 23:09:44.913512 [Byte1]: 35
8572 23:09:44.917706
8573 23:09:44.918179 Set Vref, RX VrefLevel [Byte0]: 36
8574 23:09:44.921207 [Byte1]: 36
8575 23:09:44.925741
8576 23:09:44.926174 Set Vref, RX VrefLevel [Byte0]: 37
8577 23:09:44.928852 [Byte1]: 37
8578 23:09:44.932903
8579 23:09:44.933328 Set Vref, RX VrefLevel [Byte0]: 38
8580 23:09:44.936137 [Byte1]: 38
8581 23:09:44.940168
8582 23:09:44.940593 Set Vref, RX VrefLevel [Byte0]: 39
8583 23:09:44.943570 [Byte1]: 39
8584 23:09:44.948019
8585 23:09:44.948445 Set Vref, RX VrefLevel [Byte0]: 40
8586 23:09:44.951311 [Byte1]: 40
8587 23:09:44.955407
8588 23:09:44.955856 Set Vref, RX VrefLevel [Byte0]: 41
8589 23:09:44.958846 [Byte1]: 41
8590 23:09:44.962873
8591 23:09:44.963301 Set Vref, RX VrefLevel [Byte0]: 42
8592 23:09:44.966395 [Byte1]: 42
8593 23:09:44.970561
8594 23:09:44.971113 Set Vref, RX VrefLevel [Byte0]: 43
8595 23:09:44.974259 [Byte1]: 43
8596 23:09:44.978355
8597 23:09:44.978806 Set Vref, RX VrefLevel [Byte0]: 44
8598 23:09:44.981298 [Byte1]: 44
8599 23:09:44.985981
8600 23:09:44.986394 Set Vref, RX VrefLevel [Byte0]: 45
8601 23:09:44.989193 [Byte1]: 45
8602 23:09:44.992934
8603 23:09:44.993320 Set Vref, RX VrefLevel [Byte0]: 46
8604 23:09:44.996541 [Byte1]: 46
8605 23:09:45.000387
8606 23:09:45.000885 Set Vref, RX VrefLevel [Byte0]: 47
8607 23:09:45.003828 [Byte1]: 47
8608 23:09:45.007885
8609 23:09:45.008224 Set Vref, RX VrefLevel [Byte0]: 48
8610 23:09:45.011089 [Byte1]: 48
8611 23:09:45.015899
8612 23:09:45.016056 Set Vref, RX VrefLevel [Byte0]: 49
8613 23:09:45.018904 [Byte1]: 49
8614 23:09:45.022745
8615 23:09:45.022881 Set Vref, RX VrefLevel [Byte0]: 50
8616 23:09:45.026370 [Byte1]: 50
8617 23:09:45.030333
8618 23:09:45.030458 Set Vref, RX VrefLevel [Byte0]: 51
8619 23:09:45.033841 [Byte1]: 51
8620 23:09:45.037910
8621 23:09:45.038040 Set Vref, RX VrefLevel [Byte0]: 52
8622 23:09:45.041401 [Byte1]: 52
8623 23:09:45.045677
8624 23:09:45.045769 Set Vref, RX VrefLevel [Byte0]: 53
8625 23:09:45.049146 [Byte1]: 53
8626 23:09:45.053096
8627 23:09:45.053173 Set Vref, RX VrefLevel [Byte0]: 54
8628 23:09:45.056490 [Byte1]: 54
8629 23:09:45.060803
8630 23:09:45.060880 Set Vref, RX VrefLevel [Byte0]: 55
8631 23:09:45.063659 [Byte1]: 55
8632 23:09:45.068377
8633 23:09:45.068455 Set Vref, RX VrefLevel [Byte0]: 56
8634 23:09:45.071159 [Byte1]: 56
8635 23:09:45.075425
8636 23:09:45.075502 Set Vref, RX VrefLevel [Byte0]: 57
8637 23:09:45.079102 [Byte1]: 57
8638 23:09:45.083375
8639 23:09:45.083456 Set Vref, RX VrefLevel [Byte0]: 58
8640 23:09:45.086552 [Byte1]: 58
8641 23:09:45.090508
8642 23:09:45.090586 Set Vref, RX VrefLevel [Byte0]: 59
8643 23:09:45.093839 [Byte1]: 59
8644 23:09:45.098389
8645 23:09:45.098522 Set Vref, RX VrefLevel [Byte0]: 60
8646 23:09:45.101327 [Byte1]: 60
8647 23:09:45.105951
8648 23:09:45.106047 Set Vref, RX VrefLevel [Byte0]: 61
8649 23:09:45.108903 [Byte1]: 61
8650 23:09:45.113142
8651 23:09:45.113264 Set Vref, RX VrefLevel [Byte0]: 62
8652 23:09:45.116282 [Byte1]: 62
8653 23:09:45.120975
8654 23:09:45.121064 Set Vref, RX VrefLevel [Byte0]: 63
8655 23:09:45.124487 [Byte1]: 63
8656 23:09:45.128256
8657 23:09:45.128344 Set Vref, RX VrefLevel [Byte0]: 64
8658 23:09:45.131590 [Byte1]: 64
8659 23:09:45.135655
8660 23:09:45.135747 Set Vref, RX VrefLevel [Byte0]: 65
8661 23:09:45.139093 [Byte1]: 65
8662 23:09:45.143292
8663 23:09:45.143384 Set Vref, RX VrefLevel [Byte0]: 66
8664 23:09:45.146461 [Byte1]: 66
8665 23:09:45.151283
8666 23:09:45.151395 Set Vref, RX VrefLevel [Byte0]: 67
8667 23:09:45.154264 [Byte1]: 67
8668 23:09:45.158270
8669 23:09:45.158353 Set Vref, RX VrefLevel [Byte0]: 68
8670 23:09:45.161724 [Byte1]: 68
8671 23:09:45.165774
8672 23:09:45.165885 Set Vref, RX VrefLevel [Byte0]: 69
8673 23:09:45.169213 [Byte1]: 69
8674 23:09:45.173571
8675 23:09:45.173700 Set Vref, RX VrefLevel [Byte0]: 70
8676 23:09:45.176934 [Byte1]: 70
8677 23:09:45.181260
8678 23:09:45.181360 Set Vref, RX VrefLevel [Byte0]: 71
8679 23:09:45.184386 [Byte1]: 71
8680 23:09:45.188529
8681 23:09:45.188638 Set Vref, RX VrefLevel [Byte0]: 72
8682 23:09:45.191590 [Byte1]: 72
8683 23:09:45.195926
8684 23:09:45.196037 Set Vref, RX VrefLevel [Byte0]: 73
8685 23:09:45.199485 [Byte1]: 73
8686 23:09:45.203924
8687 23:09:45.204066 Set Vref, RX VrefLevel [Byte0]: 74
8688 23:09:45.206924 [Byte1]: 74
8689 23:09:45.211004
8690 23:09:45.211088 Set Vref, RX VrefLevel [Byte0]: 75
8691 23:09:45.214531 [Byte1]: 75
8692 23:09:45.218687
8693 23:09:45.218772 Final RX Vref Byte 0 = 60 to rank0
8694 23:09:45.221814 Final RX Vref Byte 1 = 55 to rank0
8695 23:09:45.225455 Final RX Vref Byte 0 = 60 to rank1
8696 23:09:45.228961 Final RX Vref Byte 1 = 55 to rank1==
8697 23:09:45.231736 Dram Type= 6, Freq= 0, CH_1, rank 0
8698 23:09:45.235571 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8699 23:09:45.239264 ==
8700 23:09:45.239350 DQS Delay:
8701 23:09:45.239434 DQS0 = 0, DQS1 = 0
8702 23:09:45.242113 DQM Delay:
8703 23:09:45.242200 DQM0 = 134, DQM1 = 131
8704 23:09:45.245470 DQ Delay:
8705 23:09:45.248915 DQ0 =140, DQ1 =130, DQ2 =124, DQ3 =130
8706 23:09:45.252084 DQ4 =134, DQ5 =144, DQ6 =144, DQ7 =132
8707 23:09:45.255651 DQ8 =116, DQ9 =122, DQ10 =132, DQ11 =124
8708 23:09:45.258620 DQ12 =138, DQ13 =140, DQ14 =138, DQ15 =140
8709 23:09:45.258728
8710 23:09:45.258812
8711 23:09:45.258908
8712 23:09:45.262091 [DramC_TX_OE_Calibration] TA2
8713 23:09:45.265496 Original DQ_B0 (3 6) =30, OEN = 27
8714 23:09:45.268531 Original DQ_B1 (3 6) =30, OEN = 27
8715 23:09:45.272118 24, 0x0, End_B0=24 End_B1=24
8716 23:09:45.272255 25, 0x0, End_B0=25 End_B1=25
8717 23:09:45.275731 26, 0x0, End_B0=26 End_B1=26
8718 23:09:45.278641 27, 0x0, End_B0=27 End_B1=27
8719 23:09:45.282105 28, 0x0, End_B0=28 End_B1=28
8720 23:09:45.282217 29, 0x0, End_B0=29 End_B1=29
8721 23:09:45.285161 30, 0x0, End_B0=30 End_B1=30
8722 23:09:45.288671 31, 0x4545, End_B0=30 End_B1=30
8723 23:09:45.292456 Byte0 end_step=30 best_step=27
8724 23:09:45.295489 Byte1 end_step=30 best_step=27
8725 23:09:45.298425 Byte0 TX OE(2T, 0.5T) = (3, 3)
8726 23:09:45.298517 Byte1 TX OE(2T, 0.5T) = (3, 3)
8727 23:09:45.298601
8728 23:09:45.302087
8729 23:09:45.308530 [DQSOSCAuto] RK0, (LSB)MR18= 0x1725, (MSB)MR19= 0x303, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
8730 23:09:45.311975 CH1 RK0: MR19=303, MR18=1725
8731 23:09:45.318519 CH1_RK0: MR19=0x303, MR18=0x1725, DQSOSC=391, MR23=63, INC=24, DEC=16
8732 23:09:45.318622
8733 23:09:45.321510 ----->DramcWriteLeveling(PI) begin...
8734 23:09:45.321707 ==
8735 23:09:45.325336 Dram Type= 6, Freq= 0, CH_1, rank 1
8736 23:09:45.328456 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8737 23:09:45.328560 ==
8738 23:09:45.331900 Write leveling (Byte 0): 25 => 25
8739 23:09:45.334832 Write leveling (Byte 1): 29 => 29
8740 23:09:45.338154 DramcWriteLeveling(PI) end<-----
8741 23:09:45.338257
8742 23:09:45.338321 ==
8743 23:09:45.341547 Dram Type= 6, Freq= 0, CH_1, rank 1
8744 23:09:45.344764 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8745 23:09:45.344852 ==
8746 23:09:45.348235 [Gating] SW mode calibration
8747 23:09:45.354800 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8748 23:09:45.361330 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8749 23:09:45.364949 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8750 23:09:45.368387 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8751 23:09:45.374772 1 4 8 | B1->B0 | 3030 2323 | 0 0 | (0 0) (0 0)
8752 23:09:45.378341 1 4 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8753 23:09:45.381511 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8754 23:09:45.388122 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8755 23:09:45.391653 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8756 23:09:45.394825 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8757 23:09:45.401719 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8758 23:09:45.404638 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8759 23:09:45.407615 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8760 23:09:45.414819 1 5 12 | B1->B0 | 2323 3333 | 0 0 | (0 0) (1 0)
8761 23:09:45.418031 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
8762 23:09:45.420865 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8763 23:09:45.427796 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8764 23:09:45.430977 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8765 23:09:45.434699 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8766 23:09:45.441271 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8767 23:09:45.444153 1 6 8 | B1->B0 | 3636 2323 | 0 0 | (0 0) (0 0)
8768 23:09:45.447493 1 6 12 | B1->B0 | 4646 4242 | 0 0 | (0 0) (0 0)
8769 23:09:45.454370 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8770 23:09:45.457435 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8771 23:09:45.460927 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8772 23:09:45.467511 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8773 23:09:45.470973 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8774 23:09:45.474701 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8775 23:09:45.480795 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8776 23:09:45.484414 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8777 23:09:45.487486 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8778 23:09:45.494173 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8779 23:09:45.497485 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8780 23:09:45.500760 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8781 23:09:45.507591 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8782 23:09:45.511310 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8783 23:09:45.514220 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8784 23:09:45.517412 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8785 23:09:45.524173 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8786 23:09:45.527813 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8787 23:09:45.530676 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8788 23:09:45.537228 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8789 23:09:45.540990 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8790 23:09:45.543779 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8791 23:09:45.550631 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8792 23:09:45.553967 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8793 23:09:45.557432 Total UI for P1: 0, mck2ui 16
8794 23:09:45.560546 best dqsien dly found for B1: ( 1, 9, 6)
8795 23:09:45.563716 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8796 23:09:45.567067 Total UI for P1: 0, mck2ui 16
8797 23:09:45.570483 best dqsien dly found for B0: ( 1, 9, 12)
8798 23:09:45.573377 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8799 23:09:45.577006 best DQS1 dly(MCK, UI, PI) = (1, 9, 6)
8800 23:09:45.580308
8801 23:09:45.583347 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8802 23:09:45.586848 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 6)
8803 23:09:45.589938 [Gating] SW calibration Done
8804 23:09:45.590015 ==
8805 23:09:45.593630 Dram Type= 6, Freq= 0, CH_1, rank 1
8806 23:09:45.596755 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8807 23:09:45.596871 ==
8808 23:09:45.596964 RX Vref Scan: 0
8809 23:09:45.599984
8810 23:09:45.600091 RX Vref 0 -> 0, step: 1
8811 23:09:45.600184
8812 23:09:45.603795 RX Delay 0 -> 252, step: 8
8813 23:09:45.606841 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8814 23:09:45.610611 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8815 23:09:45.617387 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8816 23:09:45.620385 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8817 23:09:45.623539 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8818 23:09:45.627236 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8819 23:09:45.629985 iDelay=208, Bit 6, Center 143 (88 ~ 199) 112
8820 23:09:45.636614 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8821 23:09:45.640358 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8822 23:09:45.643158 iDelay=208, Bit 9, Center 123 (72 ~ 175) 104
8823 23:09:45.646968 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8824 23:09:45.649907 iDelay=208, Bit 11, Center 127 (72 ~ 183) 112
8825 23:09:45.656390 iDelay=208, Bit 12, Center 143 (88 ~ 199) 112
8826 23:09:45.659630 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8827 23:09:45.663532 iDelay=208, Bit 14, Center 139 (88 ~ 191) 104
8828 23:09:45.666329 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8829 23:09:45.666733 ==
8830 23:09:45.669775 Dram Type= 6, Freq= 0, CH_1, rank 1
8831 23:09:45.676289 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8832 23:09:45.676801 ==
8833 23:09:45.677177 DQS Delay:
8834 23:09:45.679653 DQS0 = 0, DQS1 = 0
8835 23:09:45.680023 DQM Delay:
8836 23:09:45.680392 DQM0 = 136, DQM1 = 134
8837 23:09:45.683145 DQ Delay:
8838 23:09:45.686421 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =131
8839 23:09:45.689497 DQ4 =131, DQ5 =151, DQ6 =143, DQ7 =135
8840 23:09:45.692931 DQ8 =119, DQ9 =123, DQ10 =135, DQ11 =127
8841 23:09:45.696564 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8842 23:09:45.696957
8843 23:09:45.697322
8844 23:09:45.697704 ==
8845 23:09:45.699828 Dram Type= 6, Freq= 0, CH_1, rank 1
8846 23:09:45.702957 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8847 23:09:45.706524 ==
8848 23:09:45.706836
8849 23:09:45.707019
8850 23:09:45.707183 TX Vref Scan disable
8851 23:09:45.709516 == TX Byte 0 ==
8852 23:09:45.712796 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8853 23:09:45.716634 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8854 23:09:45.719554 == TX Byte 1 ==
8855 23:09:45.722692 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8856 23:09:45.726334 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8857 23:09:45.729395 ==
8858 23:09:45.729488 Dram Type= 6, Freq= 0, CH_1, rank 1
8859 23:09:45.736063 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8860 23:09:45.736176 ==
8861 23:09:45.749103
8862 23:09:45.752634 TX Vref early break, caculate TX vref
8863 23:09:45.755709 TX Vref=16, minBit 0, minWin=23, winSum=383
8864 23:09:45.759384 TX Vref=18, minBit 0, minWin=23, winSum=393
8865 23:09:45.762430 TX Vref=20, minBit 0, minWin=24, winSum=398
8866 23:09:45.766118 TX Vref=22, minBit 1, minWin=24, winSum=410
8867 23:09:45.769002 TX Vref=24, minBit 0, minWin=25, winSum=415
8868 23:09:45.775767 TX Vref=26, minBit 0, minWin=25, winSum=424
8869 23:09:45.779323 TX Vref=28, minBit 1, minWin=25, winSum=424
8870 23:09:45.782295 TX Vref=30, minBit 0, minWin=25, winSum=418
8871 23:09:45.785768 TX Vref=32, minBit 0, minWin=25, winSum=412
8872 23:09:45.789214 TX Vref=34, minBit 1, minWin=24, winSum=405
8873 23:09:45.792597 TX Vref=36, minBit 0, minWin=23, winSum=396
8874 23:09:45.798903 [TxChooseVref] Worse bit 0, Min win 25, Win sum 424, Final Vref 26
8875 23:09:45.799061
8876 23:09:45.802590 Final TX Range 0 Vref 26
8877 23:09:45.802707
8878 23:09:45.802806 ==
8879 23:09:45.805355 Dram Type= 6, Freq= 0, CH_1, rank 1
8880 23:09:45.808752 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8881 23:09:45.808862 ==
8882 23:09:45.808955
8883 23:09:45.811899
8884 23:09:45.811982 TX Vref Scan disable
8885 23:09:45.818812 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8886 23:09:45.818900 == TX Byte 0 ==
8887 23:09:45.822535 u2DelayCellOfst[0]=16 cells (5 PI)
8888 23:09:45.825305 u2DelayCellOfst[1]=13 cells (4 PI)
8889 23:09:45.828943 u2DelayCellOfst[2]=0 cells (0 PI)
8890 23:09:45.832155 u2DelayCellOfst[3]=6 cells (2 PI)
8891 23:09:45.835546 u2DelayCellOfst[4]=6 cells (2 PI)
8892 23:09:45.838925 u2DelayCellOfst[5]=16 cells (5 PI)
8893 23:09:45.841735 u2DelayCellOfst[6]=20 cells (6 PI)
8894 23:09:45.845136 u2DelayCellOfst[7]=6 cells (2 PI)
8895 23:09:45.848668 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8896 23:09:45.852118 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8897 23:09:45.855590 == TX Byte 1 ==
8898 23:09:45.858653 u2DelayCellOfst[8]=0 cells (0 PI)
8899 23:09:45.862171 u2DelayCellOfst[9]=3 cells (1 PI)
8900 23:09:45.862388 u2DelayCellOfst[10]=10 cells (3 PI)
8901 23:09:45.865211 u2DelayCellOfst[11]=6 cells (2 PI)
8902 23:09:45.869047 u2DelayCellOfst[12]=13 cells (4 PI)
8903 23:09:45.872085 u2DelayCellOfst[13]=16 cells (5 PI)
8904 23:09:45.875178 u2DelayCellOfst[14]=16 cells (5 PI)
8905 23:09:45.878312 u2DelayCellOfst[15]=16 cells (5 PI)
8906 23:09:45.884912 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8907 23:09:45.888388 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8908 23:09:45.888477 DramC Write-DBI on
8909 23:09:45.888546 ==
8910 23:09:45.892010 Dram Type= 6, Freq= 0, CH_1, rank 1
8911 23:09:45.898496 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8912 23:09:45.898601 ==
8913 23:09:45.898683
8914 23:09:45.898758
8915 23:09:45.898832 TX Vref Scan disable
8916 23:09:45.902699 == TX Byte 0 ==
8917 23:09:45.905647 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8918 23:09:45.909243 == TX Byte 1 ==
8919 23:09:45.912197 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8920 23:09:45.915719 DramC Write-DBI off
8921 23:09:45.915891
8922 23:09:45.916014 [DATLAT]
8923 23:09:45.916129 Freq=1600, CH1 RK1
8924 23:09:45.916242
8925 23:09:45.919238 DATLAT Default: 0xf
8926 23:09:45.919392 0, 0xFFFF, sum = 0
8927 23:09:45.922438 1, 0xFFFF, sum = 0
8928 23:09:45.925778 2, 0xFFFF, sum = 0
8929 23:09:45.925989 3, 0xFFFF, sum = 0
8930 23:09:45.929213 4, 0xFFFF, sum = 0
8931 23:09:45.929509 5, 0xFFFF, sum = 0
8932 23:09:45.932482 6, 0xFFFF, sum = 0
8933 23:09:45.932752 7, 0xFFFF, sum = 0
8934 23:09:45.936249 8, 0xFFFF, sum = 0
8935 23:09:45.936701 9, 0xFFFF, sum = 0
8936 23:09:45.939044 10, 0xFFFF, sum = 0
8937 23:09:45.939395 11, 0xFFFF, sum = 0
8938 23:09:45.942357 12, 0xFFFF, sum = 0
8939 23:09:45.942782 13, 0xFFFF, sum = 0
8940 23:09:45.945986 14, 0x0, sum = 1
8941 23:09:45.946538 15, 0x0, sum = 2
8942 23:09:45.949240 16, 0x0, sum = 3
8943 23:09:45.949777 17, 0x0, sum = 4
8944 23:09:45.952318 best_step = 15
8945 23:09:45.952729
8946 23:09:45.953074 ==
8947 23:09:45.955930 Dram Type= 6, Freq= 0, CH_1, rank 1
8948 23:09:45.958983 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8949 23:09:45.959507 ==
8950 23:09:45.962403 RX Vref Scan: 0
8951 23:09:45.963017
8952 23:09:45.963550 RX Vref 0 -> 0, step: 1
8953 23:09:45.964051
8954 23:09:45.966147 RX Delay 19 -> 252, step: 4
8955 23:09:45.969323 iDelay=195, Bit 0, Center 138 (91 ~ 186) 96
8956 23:09:45.975867 iDelay=195, Bit 1, Center 130 (79 ~ 182) 104
8957 23:09:45.979257 iDelay=195, Bit 2, Center 122 (71 ~ 174) 104
8958 23:09:45.982498 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
8959 23:09:45.986127 iDelay=195, Bit 4, Center 130 (83 ~ 178) 96
8960 23:09:45.989275 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
8961 23:09:45.992842 iDelay=195, Bit 6, Center 144 (95 ~ 194) 100
8962 23:09:45.999057 iDelay=195, Bit 7, Center 134 (83 ~ 186) 104
8963 23:09:46.002785 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8964 23:09:46.005763 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8965 23:09:46.008775 iDelay=195, Bit 10, Center 132 (83 ~ 182) 100
8966 23:09:46.012381 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
8967 23:09:46.018778 iDelay=195, Bit 12, Center 140 (87 ~ 194) 108
8968 23:09:46.022069 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
8969 23:09:46.025972 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
8970 23:09:46.028805 iDelay=195, Bit 15, Center 140 (91 ~ 190) 100
8971 23:09:46.029270 ==
8972 23:09:46.032457 Dram Type= 6, Freq= 0, CH_1, rank 1
8973 23:09:46.038760 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8974 23:09:46.038989 ==
8975 23:09:46.039167 DQS Delay:
8976 23:09:46.042231 DQS0 = 0, DQS1 = 0
8977 23:09:46.042472 DQM Delay:
8978 23:09:46.045566 DQM0 = 134, DQM1 = 130
8979 23:09:46.045838 DQ Delay:
8980 23:09:46.048458 DQ0 =138, DQ1 =130, DQ2 =122, DQ3 =130
8981 23:09:46.052064 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =134
8982 23:09:46.055672 DQ8 =116, DQ9 =118, DQ10 =132, DQ11 =124
8983 23:09:46.058858 DQ12 =140, DQ13 =138, DQ14 =136, DQ15 =140
8984 23:09:46.059094
8985 23:09:46.059273
8986 23:09:46.059439
8987 23:09:46.061849 [DramC_TX_OE_Calibration] TA2
8988 23:09:46.065168 Original DQ_B0 (3 6) =30, OEN = 27
8989 23:09:46.068657 Original DQ_B1 (3 6) =30, OEN = 27
8990 23:09:46.071562 24, 0x0, End_B0=24 End_B1=24
8991 23:09:46.075186 25, 0x0, End_B0=25 End_B1=25
8992 23:09:46.075270 26, 0x0, End_B0=26 End_B1=26
8993 23:09:46.078416 27, 0x0, End_B0=27 End_B1=27
8994 23:09:46.082326 28, 0x0, End_B0=28 End_B1=28
8995 23:09:46.085337 29, 0x0, End_B0=29 End_B1=29
8996 23:09:46.085442 30, 0x0, End_B0=30 End_B1=30
8997 23:09:46.088422 31, 0x4545, End_B0=30 End_B1=30
8998 23:09:46.092149 Byte0 end_step=30 best_step=27
8999 23:09:46.095328 Byte1 end_step=30 best_step=27
9000 23:09:46.098613 Byte0 TX OE(2T, 0.5T) = (3, 3)
9001 23:09:46.101552 Byte1 TX OE(2T, 0.5T) = (3, 3)
9002 23:09:46.101653
9003 23:09:46.101723
9004 23:09:46.108304 [DQSOSCAuto] RK1, (LSB)MR18= 0x2107, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 393 ps
9005 23:09:46.112045 CH1 RK1: MR19=303, MR18=2107
9006 23:09:46.118388 CH1_RK1: MR19=0x303, MR18=0x2107, DQSOSC=393, MR23=63, INC=23, DEC=15
9007 23:09:46.121476 [RxdqsGatingPostProcess] freq 1600
9008 23:09:46.125108 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9009 23:09:46.128138 best DQS0 dly(2T, 0.5T) = (1, 1)
9010 23:09:46.131742 best DQS1 dly(2T, 0.5T) = (1, 1)
9011 23:09:46.135153 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9012 23:09:46.138132 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9013 23:09:46.141281 best DQS0 dly(2T, 0.5T) = (1, 1)
9014 23:09:46.144847 best DQS1 dly(2T, 0.5T) = (1, 1)
9015 23:09:46.147972 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9016 23:09:46.151519 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9017 23:09:46.154471 Pre-setting of DQS Precalculation
9018 23:09:46.157715 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9019 23:09:46.167959 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9020 23:09:46.174476 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9021 23:09:46.174578
9022 23:09:46.174698
9023 23:09:46.177448 [Calibration Summary] 3200 Mbps
9024 23:09:46.177528 CH 0, Rank 0
9025 23:09:46.181079 SW Impedance : PASS
9026 23:09:46.181159 DUTY Scan : NO K
9027 23:09:46.184555 ZQ Calibration : PASS
9028 23:09:46.187750 Jitter Meter : NO K
9029 23:09:46.187859 CBT Training : PASS
9030 23:09:46.190901 Write leveling : PASS
9031 23:09:46.194509 RX DQS gating : PASS
9032 23:09:46.194606 RX DQ/DQS(RDDQC) : PASS
9033 23:09:46.197566 TX DQ/DQS : PASS
9034 23:09:46.197690 RX DATLAT : PASS
9035 23:09:46.201075 RX DQ/DQS(Engine): PASS
9036 23:09:46.204111 TX OE : PASS
9037 23:09:46.204195 All Pass.
9038 23:09:46.204289
9039 23:09:46.204377 CH 0, Rank 1
9040 23:09:46.207581 SW Impedance : PASS
9041 23:09:46.210917 DUTY Scan : NO K
9042 23:09:46.211000 ZQ Calibration : PASS
9043 23:09:46.214067 Jitter Meter : NO K
9044 23:09:46.217757 CBT Training : PASS
9045 23:09:46.217843 Write leveling : PASS
9046 23:09:46.221000 RX DQS gating : PASS
9047 23:09:46.224335 RX DQ/DQS(RDDQC) : PASS
9048 23:09:46.224449 TX DQ/DQS : PASS
9049 23:09:46.227428 RX DATLAT : PASS
9050 23:09:46.230981 RX DQ/DQS(Engine): PASS
9051 23:09:46.231063 TX OE : PASS
9052 23:09:46.234264 All Pass.
9053 23:09:46.234344
9054 23:09:46.234409 CH 1, Rank 0
9055 23:09:46.237818 SW Impedance : PASS
9056 23:09:46.237913 DUTY Scan : NO K
9057 23:09:46.240883 ZQ Calibration : PASS
9058 23:09:46.244114 Jitter Meter : NO K
9059 23:09:46.244208 CBT Training : PASS
9060 23:09:46.247670 Write leveling : PASS
9061 23:09:46.251221 RX DQS gating : PASS
9062 23:09:46.251389 RX DQ/DQS(RDDQC) : PASS
9063 23:09:46.254245 TX DQ/DQS : PASS
9064 23:09:46.254416 RX DATLAT : PASS
9065 23:09:46.257848 RX DQ/DQS(Engine): PASS
9066 23:09:46.260983 TX OE : PASS
9067 23:09:46.261181 All Pass.
9068 23:09:46.261310
9069 23:09:46.261421 CH 1, Rank 1
9070 23:09:46.264180 SW Impedance : PASS
9071 23:09:46.267594 DUTY Scan : NO K
9072 23:09:46.267744 ZQ Calibration : PASS
9073 23:09:46.271413 Jitter Meter : NO K
9074 23:09:46.274283 CBT Training : PASS
9075 23:09:46.274453 Write leveling : PASS
9076 23:09:46.277277 RX DQS gating : PASS
9077 23:09:46.280864 RX DQ/DQS(RDDQC) : PASS
9078 23:09:46.281102 TX DQ/DQS : PASS
9079 23:09:46.284276 RX DATLAT : PASS
9080 23:09:46.287781 RX DQ/DQS(Engine): PASS
9081 23:09:46.288080 TX OE : PASS
9082 23:09:46.291170 All Pass.
9083 23:09:46.291590
9084 23:09:46.291895 DramC Write-DBI on
9085 23:09:46.294275 PER_BANK_REFRESH: Hybrid Mode
9086 23:09:46.294718 TX_TRACKING: ON
9087 23:09:46.304633 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9088 23:09:46.314096 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9089 23:09:46.321053 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9090 23:09:46.324335 [FAST_K] Save calibration result to emmc
9091 23:09:46.327711 sync common calibartion params.
9092 23:09:46.328233 sync cbt_mode0:1, 1:1
9093 23:09:46.331124 dram_init: ddr_geometry: 2
9094 23:09:46.334037 dram_init: ddr_geometry: 2
9095 23:09:46.334505 dram_init: ddr_geometry: 2
9096 23:09:46.337555 0:dram_rank_size:100000000
9097 23:09:46.340958 1:dram_rank_size:100000000
9098 23:09:46.347515 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9099 23:09:46.347958 DFS_SHUFFLE_HW_MODE: ON
9100 23:09:46.350533 dramc_set_vcore_voltage set vcore to 725000
9101 23:09:46.354078 Read voltage for 1600, 0
9102 23:09:46.354492 Vio18 = 0
9103 23:09:46.357755 Vcore = 725000
9104 23:09:46.358168 Vdram = 0
9105 23:09:46.358494 Vddq = 0
9106 23:09:46.360751 Vmddr = 0
9107 23:09:46.361161 switch to 3200 Mbps bootup
9108 23:09:46.363708 [DramcRunTimeConfig]
9109 23:09:46.364141 PHYPLL
9110 23:09:46.367303 DPM_CONTROL_AFTERK: ON
9111 23:09:46.367712 PER_BANK_REFRESH: ON
9112 23:09:46.370635 REFRESH_OVERHEAD_REDUCTION: ON
9113 23:09:46.374205 CMD_PICG_NEW_MODE: OFF
9114 23:09:46.374638 XRTWTW_NEW_MODE: ON
9115 23:09:46.377170 XRTRTR_NEW_MODE: ON
9116 23:09:46.377761 TX_TRACKING: ON
9117 23:09:46.380843 RDSEL_TRACKING: OFF
9118 23:09:46.383881 DQS Precalculation for DVFS: ON
9119 23:09:46.384295 RX_TRACKING: OFF
9120 23:09:46.387441 HW_GATING DBG: ON
9121 23:09:46.387897 ZQCS_ENABLE_LP4: ON
9122 23:09:46.390345 RX_PICG_NEW_MODE: ON
9123 23:09:46.390778 TX_PICG_NEW_MODE: ON
9124 23:09:46.393980 ENABLE_RX_DCM_DPHY: ON
9125 23:09:46.396928 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9126 23:09:46.400419 DUMMY_READ_FOR_TRACKING: OFF
9127 23:09:46.400866 !!! SPM_CONTROL_AFTERK: OFF
9128 23:09:46.403818 !!! SPM could not control APHY
9129 23:09:46.407161 IMPEDANCE_TRACKING: ON
9130 23:09:46.407611 TEMP_SENSOR: ON
9131 23:09:46.410402 HW_SAVE_FOR_SR: OFF
9132 23:09:46.413830 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9133 23:09:46.416759 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9134 23:09:46.417335 Read ODT Tracking: ON
9135 23:09:46.420143 Refresh Rate DeBounce: ON
9136 23:09:46.423464 DFS_NO_QUEUE_FLUSH: ON
9137 23:09:46.427173 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9138 23:09:46.427693 ENABLE_DFS_RUNTIME_MRW: OFF
9139 23:09:46.430362 DDR_RESERVE_NEW_MODE: ON
9140 23:09:46.433386 MR_CBT_SWITCH_FREQ: ON
9141 23:09:46.433897 =========================
9142 23:09:46.453923 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9143 23:09:46.456948 dram_init: ddr_geometry: 2
9144 23:09:46.475634 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9145 23:09:46.479078 dram_init: dram init end (result: 0)
9146 23:09:46.485557 DRAM-K: Full calibration passed in 24472 msecs
9147 23:09:46.489083 MRC: failed to locate region type 0.
9148 23:09:46.489505 DRAM rank0 size:0x100000000,
9149 23:09:46.492141 DRAM rank1 size=0x100000000
9150 23:09:46.502061 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9151 23:09:46.508910 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9152 23:09:46.515298 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9153 23:09:46.521747 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9154 23:09:46.525379 DRAM rank0 size:0x100000000,
9155 23:09:46.528382 DRAM rank1 size=0x100000000
9156 23:09:46.528817 CBMEM:
9157 23:09:46.531866 IMD: root @ 0xfffff000 254 entries.
9158 23:09:46.535371 IMD: root @ 0xffffec00 62 entries.
9159 23:09:46.538292 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9160 23:09:46.541853 WARNING: RO_VPD is uninitialized or empty.
9161 23:09:46.548627 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9162 23:09:46.555659 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9163 23:09:46.568486 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9164 23:09:46.579886 BS: romstage times (exec / console): total (unknown) / 24000 ms
9165 23:09:46.580478
9166 23:09:46.581122
9167 23:09:46.589465 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9168 23:09:46.593345 ARM64: Exception handlers installed.
9169 23:09:46.596276 ARM64: Testing exception
9170 23:09:46.599836 ARM64: Done test exception
9171 23:09:46.600416 Enumerating buses...
9172 23:09:46.603076 Show all devs... Before device enumeration.
9173 23:09:46.606517 Root Device: enabled 1
9174 23:09:46.609365 CPU_CLUSTER: 0: enabled 1
9175 23:09:46.609948 CPU: 00: enabled 1
9176 23:09:46.612994 Compare with tree...
9177 23:09:46.613682 Root Device: enabled 1
9178 23:09:46.615929 CPU_CLUSTER: 0: enabled 1
9179 23:09:46.619599 CPU: 00: enabled 1
9180 23:09:46.620013 Root Device scanning...
9181 23:09:46.622879 scan_static_bus for Root Device
9182 23:09:46.626319 CPU_CLUSTER: 0 enabled
9183 23:09:46.629497 scan_static_bus for Root Device done
9184 23:09:46.632729 scan_bus: bus Root Device finished in 8 msecs
9185 23:09:46.633186 done
9186 23:09:46.639965 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9187 23:09:46.642693 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9188 23:09:46.649733 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9189 23:09:46.652524 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9190 23:09:46.655953 Allocating resources...
9191 23:09:46.659488 Reading resources...
9192 23:09:46.663143 Root Device read_resources bus 0 link: 0
9193 23:09:46.663569 DRAM rank0 size:0x100000000,
9194 23:09:46.666104 DRAM rank1 size=0x100000000
9195 23:09:46.669424 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9196 23:09:46.672810 CPU: 00 missing read_resources
9197 23:09:46.676465 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9198 23:09:46.682780 Root Device read_resources bus 0 link: 0 done
9199 23:09:46.683197 Done reading resources.
9200 23:09:46.689057 Show resources in subtree (Root Device)...After reading.
9201 23:09:46.692353 Root Device child on link 0 CPU_CLUSTER: 0
9202 23:09:46.696150 CPU_CLUSTER: 0 child on link 0 CPU: 00
9203 23:09:46.705847 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9204 23:09:46.706400 CPU: 00
9205 23:09:46.709005 Root Device assign_resources, bus 0 link: 0
9206 23:09:46.712560 CPU_CLUSTER: 0 missing set_resources
9207 23:09:46.716252 Root Device assign_resources, bus 0 link: 0 done
9208 23:09:46.719290 Done setting resources.
9209 23:09:46.725772 Show resources in subtree (Root Device)...After assigning values.
9210 23:09:46.729083 Root Device child on link 0 CPU_CLUSTER: 0
9211 23:09:46.732607 CPU_CLUSTER: 0 child on link 0 CPU: 00
9212 23:09:46.742641 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9213 23:09:46.743161 CPU: 00
9214 23:09:46.746172 Done allocating resources.
9215 23:09:46.749019 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9216 23:09:46.752596 Enabling resources...
9217 23:09:46.753140 done.
9218 23:09:46.759100 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9219 23:09:46.759517 Initializing devices...
9220 23:09:46.762228 Root Device init
9221 23:09:46.762810 init hardware done!
9222 23:09:46.766104 0x00000018: ctrlr->caps
9223 23:09:46.768884 52.000 MHz: ctrlr->f_max
9224 23:09:46.769482 0.400 MHz: ctrlr->f_min
9225 23:09:46.772425 0x40ff8080: ctrlr->voltages
9226 23:09:46.773031 sclk: 390625
9227 23:09:46.775812 Bus Width = 1
9228 23:09:46.776221 sclk: 390625
9229 23:09:46.779248 Bus Width = 1
9230 23:09:46.779787 Early init status = 3
9231 23:09:46.785827 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9232 23:09:46.788727 in-header: 03 fc 00 00 01 00 00 00
9233 23:09:46.789272 in-data: 00
9234 23:09:46.795626 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9235 23:09:46.798803 in-header: 03 fd 00 00 00 00 00 00
9236 23:09:46.802287 in-data:
9237 23:09:46.805718 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9238 23:09:46.808604 in-header: 03 fc 00 00 01 00 00 00
9239 23:09:46.811933 in-data: 00
9240 23:09:46.815166 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9241 23:09:46.819635 in-header: 03 fd 00 00 00 00 00 00
9242 23:09:46.823002 in-data:
9243 23:09:46.826415 [SSUSB] Setting up USB HOST controller...
9244 23:09:46.830119 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9245 23:09:46.833014 [SSUSB] phy power-on done.
9246 23:09:46.836460 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9247 23:09:46.843023 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9248 23:09:46.846601 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9249 23:09:46.853044 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9250 23:09:46.859828 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9251 23:09:46.866492 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9252 23:09:46.872880 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9253 23:09:46.879502 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9254 23:09:46.882862 SPM: binary array size = 0x9dc
9255 23:09:46.886382 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9256 23:09:46.892913 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9257 23:09:46.899745 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9258 23:09:46.902818 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9259 23:09:46.909282 configure_display: Starting display init
9260 23:09:46.943086 anx7625_power_on_init: Init interface.
9261 23:09:46.946068 anx7625_disable_pd_protocol: Disabled PD feature.
9262 23:09:46.949746 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9263 23:09:46.977613 anx7625_start_dp_work: Secure OCM version=00
9264 23:09:46.981066 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9265 23:09:46.995819 sp_tx_get_edid_block: EDID Block = 1
9266 23:09:47.098171 Extracted contents:
9267 23:09:47.101334 header: 00 ff ff ff ff ff ff 00
9268 23:09:47.104818 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9269 23:09:47.108345 version: 01 04
9270 23:09:47.111244 basic params: 95 1f 11 78 0a
9271 23:09:47.114706 chroma info: 76 90 94 55 54 90 27 21 50 54
9272 23:09:47.117842 established: 00 00 00
9273 23:09:47.124730 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9274 23:09:47.127851 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9275 23:09:47.134174 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9276 23:09:47.140977 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9277 23:09:47.148183 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9278 23:09:47.151401 extensions: 00
9279 23:09:47.151817 checksum: fb
9280 23:09:47.152211
9281 23:09:47.154545 Manufacturer: IVO Model 57d Serial Number 0
9282 23:09:47.157598 Made week 0 of 2020
9283 23:09:47.158065 EDID version: 1.4
9284 23:09:47.161138 Digital display
9285 23:09:47.164521 6 bits per primary color channel
9286 23:09:47.165003 DisplayPort interface
9287 23:09:47.167853 Maximum image size: 31 cm x 17 cm
9288 23:09:47.171283 Gamma: 220%
9289 23:09:47.171785 Check DPMS levels
9290 23:09:47.174576 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9291 23:09:47.177836 First detailed timing is preferred timing
9292 23:09:47.181096 Established timings supported:
9293 23:09:47.184395 Standard timings supported:
9294 23:09:47.187696 Detailed timings
9295 23:09:47.191176 Hex of detail: 383680a07038204018303c0035ae10000019
9296 23:09:47.194458 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9297 23:09:47.200676 0780 0798 07c8 0820 hborder 0
9298 23:09:47.204138 0438 043b 0447 0458 vborder 0
9299 23:09:47.207754 -hsync -vsync
9300 23:09:47.208175 Did detailed timing
9301 23:09:47.211305 Hex of detail: 000000000000000000000000000000000000
9302 23:09:47.214329 Manufacturer-specified data, tag 0
9303 23:09:47.221007 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9304 23:09:47.221571 ASCII string: InfoVision
9305 23:09:47.227550 Hex of detail: 000000fe00523134304e574635205248200a
9306 23:09:47.231035 ASCII string: R140NWF5 RH
9307 23:09:47.231620 Checksum
9308 23:09:47.232131 Checksum: 0xfb (valid)
9309 23:09:47.237656 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9310 23:09:47.241228 DSI data_rate: 832800000 bps
9311 23:09:47.244127 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9312 23:09:47.247765 anx7625_parse_edid: pixelclock(138800).
9313 23:09:47.254232 hactive(1920), hsync(48), hfp(24), hbp(88)
9314 23:09:47.257831 vactive(1080), vsync(12), vfp(3), vbp(17)
9315 23:09:47.260975 anx7625_dsi_config: config dsi.
9316 23:09:47.267465 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9317 23:09:47.280262 anx7625_dsi_config: success to config DSI
9318 23:09:47.283321 anx7625_dp_start: MIPI phy setup OK.
9319 23:09:47.286978 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9320 23:09:47.289778 mtk_ddp_mode_set invalid vrefresh 60
9321 23:09:47.293501 main_disp_path_setup
9322 23:09:47.293946 ovl_layer_smi_id_en
9323 23:09:47.296496 ovl_layer_smi_id_en
9324 23:09:47.296898 ccorr_config
9325 23:09:47.297214 aal_config
9326 23:09:47.299847 gamma_config
9327 23:09:47.300255 postmask_config
9328 23:09:47.303170 dither_config
9329 23:09:47.306783 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9330 23:09:47.313537 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9331 23:09:47.316261 Root Device init finished in 551 msecs
9332 23:09:47.320052 CPU_CLUSTER: 0 init
9333 23:09:47.326493 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9334 23:09:47.329781 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9335 23:09:47.333461 APU_MBOX 0x190000b0 = 0x10001
9336 23:09:47.336924 APU_MBOX 0x190001b0 = 0x10001
9337 23:09:47.339947 APU_MBOX 0x190005b0 = 0x10001
9338 23:09:47.343535 APU_MBOX 0x190006b0 = 0x10001
9339 23:09:47.346510 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9340 23:09:47.359586 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9341 23:09:47.371523 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9342 23:09:47.378172 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9343 23:09:47.389656 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9344 23:09:47.399108 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9345 23:09:47.402286 CPU_CLUSTER: 0 init finished in 81 msecs
9346 23:09:47.405442 Devices initialized
9347 23:09:47.408970 Show all devs... After init.
9348 23:09:47.409436 Root Device: enabled 1
9349 23:09:47.412128 CPU_CLUSTER: 0: enabled 1
9350 23:09:47.415290 CPU: 00: enabled 1
9351 23:09:47.418651 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9352 23:09:47.421998 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9353 23:09:47.425304 ELOG: NV offset 0x57f000 size 0x1000
9354 23:09:47.431897 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9355 23:09:47.438872 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9356 23:09:47.442087 ELOG: Event(17) added with size 13 at 2023-12-03 23:07:33 UTC
9357 23:09:47.445050 out: cmd=0x121: 03 db 21 01 00 00 00 00
9358 23:09:47.448984 in-header: 03 ce 00 00 2c 00 00 00
9359 23:09:47.462203 in-data: 91 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9360 23:09:47.468825 ELOG: Event(A1) added with size 10 at 2023-12-03 23:07:33 UTC
9361 23:09:47.475649 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9362 23:09:47.482029 ELOG: Event(A0) added with size 9 at 2023-12-03 23:07:33 UTC
9363 23:09:47.485259 elog_add_boot_reason: Logged dev mode boot
9364 23:09:47.488375 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9365 23:09:47.492189 Finalize devices...
9366 23:09:47.492625 Devices finalized
9367 23:09:47.498514 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9368 23:09:47.502020 Writing coreboot table at 0xffe64000
9369 23:09:47.505498 0. 000000000010a000-0000000000113fff: RAMSTAGE
9370 23:09:47.508737 1. 0000000040000000-00000000400fffff: RAM
9371 23:09:47.515466 2. 0000000040100000-000000004032afff: RAMSTAGE
9372 23:09:47.518982 3. 000000004032b000-00000000545fffff: RAM
9373 23:09:47.521970 4. 0000000054600000-000000005465ffff: BL31
9374 23:09:47.525255 5. 0000000054660000-00000000ffe63fff: RAM
9375 23:09:47.531585 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9376 23:09:47.535116 7. 0000000100000000-000000023fffffff: RAM
9377 23:09:47.538470 Passing 5 GPIOs to payload:
9378 23:09:47.541910 NAME | PORT | POLARITY | VALUE
9379 23:09:47.545451 EC in RW | 0x000000aa | low | undefined
9380 23:09:47.551575 EC interrupt | 0x00000005 | low | undefined
9381 23:09:47.555194 TPM interrupt | 0x000000ab | high | undefined
9382 23:09:47.561785 SD card detect | 0x00000011 | high | undefined
9383 23:09:47.564729 speaker enable | 0x00000093 | high | undefined
9384 23:09:47.568243 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9385 23:09:47.571912 in-header: 03 f9 00 00 02 00 00 00
9386 23:09:47.574890 in-data: 02 00
9387 23:09:47.575303 ADC[4]: Raw value=904726 ID=7
9388 23:09:47.578452 ADC[3]: Raw value=213441 ID=1
9389 23:09:47.581345 RAM Code: 0x71
9390 23:09:47.581864 ADC[6]: Raw value=75332 ID=0
9391 23:09:47.585143 ADC[5]: Raw value=213441 ID=1
9392 23:09:47.587942 SKU Code: 0x1
9393 23:09:47.591419 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 425c
9394 23:09:47.594507 coreboot table: 964 bytes.
9395 23:09:47.598313 IMD ROOT 0. 0xfffff000 0x00001000
9396 23:09:47.601466 IMD SMALL 1. 0xffffe000 0x00001000
9397 23:09:47.604788 RO MCACHE 2. 0xffffc000 0x00001104
9398 23:09:47.608211 CONSOLE 3. 0xfff7c000 0x00080000
9399 23:09:47.611234 FMAP 4. 0xfff7b000 0x00000452
9400 23:09:47.614837 TIME STAMP 5. 0xfff7a000 0x00000910
9401 23:09:47.617784 VBOOT WORK 6. 0xfff66000 0x00014000
9402 23:09:47.621146 RAMOOPS 7. 0xffe66000 0x00100000
9403 23:09:47.624665 COREBOOT 8. 0xffe64000 0x00002000
9404 23:09:47.625072 IMD small region:
9405 23:09:47.628203 IMD ROOT 0. 0xffffec00 0x00000400
9406 23:09:47.631124 VPD 1. 0xffffeb80 0x0000006c
9407 23:09:47.635008 MMC STATUS 2. 0xffffeb60 0x00000004
9408 23:09:47.641066 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9409 23:09:47.644823 Probing TPM: done!
9410 23:09:47.648161 Connected to device vid:did:rid of 1ae0:0028:00
9411 23:09:47.658397 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9412 23:09:47.661669 Initialized TPM device CR50 revision 0
9413 23:09:47.665308 Checking cr50 for pending updates
9414 23:09:47.668709 Reading cr50 TPM mode
9415 23:09:47.677291 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9416 23:09:47.683784 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9417 23:09:47.724108 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9418 23:09:47.727355 Checking segment from ROM address 0x40100000
9419 23:09:47.730544 Checking segment from ROM address 0x4010001c
9420 23:09:47.737195 Loading segment from ROM address 0x40100000
9421 23:09:47.737643 code (compression=0)
9422 23:09:47.747213 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9423 23:09:47.753740 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9424 23:09:47.754162 it's not compressed!
9425 23:09:47.760551 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9426 23:09:47.767188 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9427 23:09:47.784736 Loading segment from ROM address 0x4010001c
9428 23:09:47.785223 Entry Point 0x80000000
9429 23:09:47.787738 Loaded segments
9430 23:09:47.791428 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9431 23:09:47.798075 Jumping to boot code at 0x80000000(0xffe64000)
9432 23:09:47.804457 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9433 23:09:47.810950 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9434 23:09:47.819081 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9435 23:09:47.822310 Checking segment from ROM address 0x40100000
9436 23:09:47.825671 Checking segment from ROM address 0x4010001c
9437 23:09:47.832267 Loading segment from ROM address 0x40100000
9438 23:09:47.832705 code (compression=1)
9439 23:09:47.839268 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9440 23:09:47.848994 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9441 23:09:47.849434 using LZMA
9442 23:09:47.857359 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9443 23:09:47.863931 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9444 23:09:47.867677 Loading segment from ROM address 0x4010001c
9445 23:09:47.868360 Entry Point 0x54601000
9446 23:09:47.871231 Loaded segments
9447 23:09:47.873982 NOTICE: MT8192 bl31_setup
9448 23:09:47.881089 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9449 23:09:47.884015 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9450 23:09:47.887867 WARNING: region 0:
9451 23:09:47.890788 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9452 23:09:47.891389 WARNING: region 1:
9453 23:09:47.897570 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9454 23:09:47.900467 WARNING: region 2:
9455 23:09:47.904044 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9456 23:09:47.907442 WARNING: region 3:
9457 23:09:47.910399 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9458 23:09:47.914082 WARNING: region 4:
9459 23:09:47.920417 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9460 23:09:47.920902 WARNING: region 5:
9461 23:09:47.924107 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9462 23:09:47.927492 WARNING: region 6:
9463 23:09:47.930733 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9464 23:09:47.933953 WARNING: region 7:
9465 23:09:47.937182 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9466 23:09:47.944293 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9467 23:09:47.947626 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9468 23:09:47.951180 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9469 23:09:47.957693 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9470 23:09:47.960695 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9471 23:09:47.964153 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9472 23:09:47.970788 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9473 23:09:47.974142 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9474 23:09:47.981177 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9475 23:09:47.984097 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9476 23:09:47.987958 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9477 23:09:47.994046 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9478 23:09:47.997863 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9479 23:09:48.000928 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9480 23:09:48.007674 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9481 23:09:48.010937 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9482 23:09:48.014223 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9483 23:09:48.020704 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9484 23:09:48.024355 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9485 23:09:48.031251 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9486 23:09:48.034041 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9487 23:09:48.037574 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9488 23:09:48.044740 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9489 23:09:48.047599 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9490 23:09:48.054230 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9491 23:09:48.057955 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9492 23:09:48.060667 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9493 23:09:48.067881 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9494 23:09:48.070871 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9495 23:09:48.074283 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9496 23:09:48.080904 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9497 23:09:48.084279 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9498 23:09:48.088339 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9499 23:09:48.094689 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9500 23:09:48.098120 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9501 23:09:48.101291 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9502 23:09:48.104788 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9503 23:09:48.111411 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9504 23:09:48.114842 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9505 23:09:48.118145 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9506 23:09:48.121123 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9507 23:09:48.128131 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9508 23:09:48.131788 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9509 23:09:48.134546 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9510 23:09:48.137749 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9511 23:09:48.144792 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9512 23:09:48.147489 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9513 23:09:48.151397 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9514 23:09:48.157969 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9515 23:09:48.161287 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9516 23:09:48.164712 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9517 23:09:48.170966 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9518 23:09:48.174530 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9519 23:09:48.181278 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9520 23:09:48.184544 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9521 23:09:48.191319 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9522 23:09:48.194836 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9523 23:09:48.197934 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9524 23:09:48.204255 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9525 23:09:48.208144 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9526 23:09:48.214427 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9527 23:09:48.218114 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9528 23:09:48.224546 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9529 23:09:48.227608 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9530 23:09:48.234884 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9531 23:09:48.237688 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9532 23:09:48.241202 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9533 23:09:48.248065 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9534 23:09:48.250955 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9535 23:09:48.257911 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9536 23:09:48.261254 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9537 23:09:48.264895 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9538 23:09:48.271356 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9539 23:09:48.274857 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9540 23:09:48.281407 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9541 23:09:48.284878 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9542 23:09:48.291487 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9543 23:09:48.294927 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9544 23:09:48.297958 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9545 23:09:48.304442 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9546 23:09:48.307920 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9547 23:09:48.314501 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9548 23:09:48.317969 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9549 23:09:48.324598 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9550 23:09:48.328146 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9551 23:09:48.334807 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9552 23:09:48.337766 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9553 23:09:48.341221 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9554 23:09:48.348240 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9555 23:09:48.351522 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9556 23:09:48.358042 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9557 23:09:48.361162 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9558 23:09:48.367765 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9559 23:09:48.371498 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9560 23:09:48.374476 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9561 23:09:48.381335 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9562 23:09:48.384846 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9563 23:09:48.388292 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9564 23:09:48.394976 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9565 23:09:48.397967 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9566 23:09:48.401377 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9567 23:09:48.407661 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9568 23:09:48.410976 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9569 23:09:48.414083 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9570 23:09:48.420978 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9571 23:09:48.424435 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9572 23:09:48.431094 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9573 23:09:48.434315 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9574 23:09:48.437881 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9575 23:09:48.444854 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9576 23:09:48.448057 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9577 23:09:48.451096 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9578 23:09:48.458078 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9579 23:09:48.461670 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9580 23:09:48.468012 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9581 23:09:48.471144 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9582 23:09:48.474839 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9583 23:09:48.481184 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9584 23:09:48.484393 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9585 23:09:48.488009 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9586 23:09:48.491115 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9587 23:09:48.498061 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9588 23:09:48.501500 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9589 23:09:48.504410 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9590 23:09:48.511557 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9591 23:09:48.514418 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9592 23:09:48.517922 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9593 23:09:48.524533 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9594 23:09:48.527873 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9595 23:09:48.531534 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9596 23:09:48.538339 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9597 23:09:48.541208 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9598 23:09:48.547904 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9599 23:09:48.551573 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9600 23:09:48.555119 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9601 23:09:48.561876 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9602 23:09:48.565287 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9603 23:09:48.568029 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9604 23:09:48.574654 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9605 23:09:48.578264 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9606 23:09:48.584672 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9607 23:09:48.588388 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9608 23:09:48.591609 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9609 23:09:48.598189 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9610 23:09:48.601814 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9611 23:09:48.607838 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9612 23:09:48.611267 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9613 23:09:48.614852 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9614 23:09:48.621068 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9615 23:09:48.624481 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9616 23:09:48.631042 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9617 23:09:48.634737 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9618 23:09:48.637835 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9619 23:09:48.644692 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9620 23:09:48.647785 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9621 23:09:48.651373 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9622 23:09:48.657835 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9623 23:09:48.661423 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9624 23:09:48.668190 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9625 23:09:48.671222 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9626 23:09:48.674816 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9627 23:09:48.681566 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9628 23:09:48.684856 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9629 23:09:48.691385 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9630 23:09:48.694236 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9631 23:09:48.697682 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9632 23:09:48.704607 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9633 23:09:48.707386 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9634 23:09:48.714469 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9635 23:09:48.717715 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9636 23:09:48.720982 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9637 23:09:48.727292 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9638 23:09:48.730634 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9639 23:09:48.737154 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9640 23:09:48.740277 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9641 23:09:48.743803 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9642 23:09:48.750428 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9643 23:09:48.754022 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9644 23:09:48.760359 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9645 23:09:48.763968 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9646 23:09:48.767069 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9647 23:09:48.773551 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9648 23:09:48.777081 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9649 23:09:48.783899 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9650 23:09:48.786910 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9651 23:09:48.790311 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9652 23:09:48.797088 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9653 23:09:48.800626 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9654 23:09:48.803931 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9655 23:09:48.810516 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9656 23:09:48.813491 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9657 23:09:48.820717 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9658 23:09:48.823557 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9659 23:09:48.826969 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9660 23:09:48.833506 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9661 23:09:48.836898 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9662 23:09:48.843493 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9663 23:09:48.846855 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9664 23:09:48.853425 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9665 23:09:48.857036 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9666 23:09:48.860685 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9667 23:09:48.867035 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9668 23:09:48.870429 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9669 23:09:48.876683 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9670 23:09:48.880310 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9671 23:09:48.886927 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9672 23:09:48.890426 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9673 23:09:48.893355 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9674 23:09:48.900120 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9675 23:09:48.903659 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9676 23:09:48.910198 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9677 23:09:48.913458 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9678 23:09:48.916912 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9679 23:09:48.923666 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9680 23:09:48.926583 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9681 23:09:48.933803 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9682 23:09:48.936727 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9683 23:09:48.940008 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9684 23:09:48.946761 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9685 23:09:48.949714 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9686 23:09:48.956448 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9687 23:09:48.960001 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9688 23:09:48.966694 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9689 23:09:48.969700 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9690 23:09:48.973184 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9691 23:09:48.979700 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9692 23:09:48.982977 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9693 23:09:48.989678 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9694 23:09:48.993217 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9695 23:09:48.996271 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9696 23:09:48.999797 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9697 23:09:49.006804 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9698 23:09:49.009715 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9699 23:09:49.012952 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9700 23:09:49.019697 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9701 23:09:49.023289 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9702 23:09:49.026225 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9703 23:09:49.033395 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9704 23:09:49.036226 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9705 23:09:49.039794 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9706 23:09:49.046213 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9707 23:09:49.049645 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9708 23:09:49.056472 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9709 23:09:49.059453 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9710 23:09:49.063053 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9711 23:09:49.069393 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9712 23:09:49.072572 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9713 23:09:49.075910 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9714 23:09:49.083242 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9715 23:09:49.086183 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9716 23:09:49.089626 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9717 23:09:49.096494 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9718 23:09:49.099475 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9719 23:09:49.102964 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9720 23:09:49.109441 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9721 23:09:49.112991 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9722 23:09:49.119557 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9723 23:09:49.122465 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9724 23:09:49.126193 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9725 23:09:49.132737 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9726 23:09:49.135873 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9727 23:09:49.139117 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9728 23:09:49.145899 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9729 23:09:49.149447 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9730 23:09:49.152295 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9731 23:09:49.159009 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9732 23:09:49.162687 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9733 23:09:49.169132 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9734 23:09:49.172839 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9735 23:09:49.175791 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9736 23:09:49.179193 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9737 23:09:49.185794 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9738 23:09:49.189116 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9739 23:09:49.192342 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9740 23:09:49.195965 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9741 23:09:49.202486 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9742 23:09:49.205438 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9743 23:09:49.208659 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9744 23:09:49.212023 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9745 23:09:49.219225 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9746 23:09:49.222360 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9747 23:09:49.225788 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9748 23:09:49.232293 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9749 23:09:49.235347 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9750 23:09:49.238457 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9751 23:09:49.245187 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9752 23:09:49.248319 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9753 23:09:49.254977 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9754 23:09:49.258589 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9755 23:09:49.262186 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9756 23:09:49.268340 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9757 23:09:49.272000 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9758 23:09:49.278679 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9759 23:09:49.282108 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9760 23:09:49.288798 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9761 23:09:49.291781 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9762 23:09:49.295097 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9763 23:09:49.302150 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9764 23:09:49.304974 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9765 23:09:49.311766 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9766 23:09:49.315345 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9767 23:09:49.318322 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9768 23:09:49.325109 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9769 23:09:49.328235 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9770 23:09:49.335008 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9771 23:09:49.338291 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9772 23:09:49.341738 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9773 23:09:49.348358 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9774 23:09:49.351816 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9775 23:09:49.358455 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9776 23:09:49.361680 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9777 23:09:49.365082 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9778 23:09:49.371942 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9779 23:09:49.374977 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9780 23:09:49.381954 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9781 23:09:49.384790 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9782 23:09:49.387914 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9783 23:09:49.395653 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9784 23:09:49.397880 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9785 23:09:49.405147 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9786 23:09:49.408408 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9787 23:09:49.411759 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9788 23:09:49.418585 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9789 23:09:49.421404 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9790 23:09:49.428116 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9791 23:09:49.431358 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9792 23:09:49.438236 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9793 23:09:49.441654 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9794 23:09:49.445175 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9795 23:09:49.451721 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9796 23:09:49.455116 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9797 23:09:49.458602 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9798 23:09:49.464971 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9799 23:09:49.468550 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9800 23:09:49.474773 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9801 23:09:49.478443 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9802 23:09:49.485043 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9803 23:09:49.488415 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9804 23:09:49.491419 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9805 23:09:49.497940 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9806 23:09:49.501511 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9807 23:09:49.508128 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9808 23:09:49.511202 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9809 23:09:49.514863 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9810 23:09:49.521143 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9811 23:09:49.524219 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9812 23:09:49.531375 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9813 23:09:49.534195 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9814 23:09:49.537962 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9815 23:09:49.544559 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9816 23:09:49.547580 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9817 23:09:49.554119 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9818 23:09:49.557830 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9819 23:09:49.564236 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9820 23:09:49.567673 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9821 23:09:49.570882 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9822 23:09:49.577412 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9823 23:09:49.580537 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9824 23:09:49.586889 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9825 23:09:49.590416 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9826 23:09:49.596977 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9827 23:09:49.600448 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9828 23:09:49.606979 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9829 23:09:49.610517 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9830 23:09:49.613461 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9831 23:09:49.620038 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9832 23:09:49.623801 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9833 23:09:49.630132 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9834 23:09:49.633558 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9835 23:09:49.639931 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9836 23:09:49.643689 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9837 23:09:49.646623 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9838 23:09:49.653807 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9839 23:09:49.656787 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9840 23:09:49.663339 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9841 23:09:49.666967 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9842 23:09:49.673527 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9843 23:09:49.676453 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9844 23:09:49.679731 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9845 23:09:49.686452 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9846 23:09:49.690105 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9847 23:09:49.696256 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9848 23:09:49.699556 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9849 23:09:49.706533 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9850 23:09:49.709769 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9851 23:09:49.716306 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9852 23:09:49.719490 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9853 23:09:49.722763 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9854 23:09:49.729247 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9855 23:09:49.733090 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9856 23:09:49.739554 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9857 23:09:49.743137 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9858 23:09:49.749690 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9859 23:09:49.753022 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9860 23:09:49.759503 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9861 23:09:49.762496 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9862 23:09:49.766176 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9863 23:09:49.772767 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9864 23:09:49.775308 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9865 23:09:49.781975 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9866 23:09:49.785423 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9867 23:09:49.792329 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9868 23:09:49.795232 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9869 23:09:49.798740 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9870 23:09:49.804984 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9871 23:09:49.808496 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9872 23:09:49.815006 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9873 23:09:49.818471 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9874 23:09:49.825239 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9875 23:09:49.828376 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9876 23:09:49.834856 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9877 23:09:49.838384 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9878 23:09:49.845041 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9879 23:09:49.848107 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9880 23:09:49.855295 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9881 23:09:49.858296 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9882 23:09:49.865004 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9883 23:09:49.868658 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9884 23:09:49.875306 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9885 23:09:49.878629 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9886 23:09:49.881539 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9887 23:09:49.888006 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9888 23:09:49.891629 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9889 23:09:49.897966 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9890 23:09:49.901324 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9891 23:09:49.907973 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9892 23:09:49.914896 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9893 23:09:49.917795 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9894 23:09:49.921267 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9895 23:09:49.928038 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9896 23:09:49.934732 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9897 23:09:49.938425 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9898 23:09:49.944616 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9899 23:09:49.947838 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9900 23:09:49.951388 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9901 23:09:49.954659 INFO: [APUAPC] vio 0
9902 23:09:49.957957 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9903 23:09:49.964610 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9904 23:09:49.968088 INFO: [APUAPC] D0_APC_0: 0x400510
9905 23:09:49.971052 INFO: [APUAPC] D0_APC_1: 0x0
9906 23:09:49.974509 INFO: [APUAPC] D0_APC_2: 0x1540
9907 23:09:49.974590 INFO: [APUAPC] D0_APC_3: 0x0
9908 23:09:49.977818 INFO: [APUAPC] D1_APC_0: 0xffffffff
9909 23:09:49.984560 INFO: [APUAPC] D1_APC_1: 0xffffffff
9910 23:09:49.987502 INFO: [APUAPC] D1_APC_2: 0x3fffff
9911 23:09:49.987585 INFO: [APUAPC] D1_APC_3: 0x0
9912 23:09:49.991235 INFO: [APUAPC] D2_APC_0: 0xffffffff
9913 23:09:49.994189 INFO: [APUAPC] D2_APC_1: 0xffffffff
9914 23:09:49.997704 INFO: [APUAPC] D2_APC_2: 0x3fffff
9915 23:09:50.001270 INFO: [APUAPC] D2_APC_3: 0x0
9916 23:09:50.004134 INFO: [APUAPC] D3_APC_0: 0xffffffff
9917 23:09:50.007892 INFO: [APUAPC] D3_APC_1: 0xffffffff
9918 23:09:50.011340 INFO: [APUAPC] D3_APC_2: 0x3fffff
9919 23:09:50.014268 INFO: [APUAPC] D3_APC_3: 0x0
9920 23:09:50.017710 INFO: [APUAPC] D4_APC_0: 0xffffffff
9921 23:09:50.020812 INFO: [APUAPC] D4_APC_1: 0xffffffff
9922 23:09:50.024436 INFO: [APUAPC] D4_APC_2: 0x3fffff
9923 23:09:50.027812 INFO: [APUAPC] D4_APC_3: 0x0
9924 23:09:50.030614 INFO: [APUAPC] D5_APC_0: 0xffffffff
9925 23:09:50.034046 INFO: [APUAPC] D5_APC_1: 0xffffffff
9926 23:09:50.037761 INFO: [APUAPC] D5_APC_2: 0x3fffff
9927 23:09:50.040588 INFO: [APUAPC] D5_APC_3: 0x0
9928 23:09:50.044240 INFO: [APUAPC] D6_APC_0: 0xffffffff
9929 23:09:50.047612 INFO: [APUAPC] D6_APC_1: 0xffffffff
9930 23:09:50.050708 INFO: [APUAPC] D6_APC_2: 0x3fffff
9931 23:09:50.054217 INFO: [APUAPC] D6_APC_3: 0x0
9932 23:09:50.057352 INFO: [APUAPC] D7_APC_0: 0xffffffff
9933 23:09:50.060901 INFO: [APUAPC] D7_APC_1: 0xffffffff
9934 23:09:50.063821 INFO: [APUAPC] D7_APC_2: 0x3fffff
9935 23:09:50.067629 INFO: [APUAPC] D7_APC_3: 0x0
9936 23:09:50.070840 INFO: [APUAPC] D8_APC_0: 0xffffffff
9937 23:09:50.073804 INFO: [APUAPC] D8_APC_1: 0xffffffff
9938 23:09:50.077672 INFO: [APUAPC] D8_APC_2: 0x3fffff
9939 23:09:50.080442 INFO: [APUAPC] D8_APC_3: 0x0
9940 23:09:50.084228 INFO: [APUAPC] D9_APC_0: 0xffffffff
9941 23:09:50.087234 INFO: [APUAPC] D9_APC_1: 0xffffffff
9942 23:09:50.090531 INFO: [APUAPC] D9_APC_2: 0x3fffff
9943 23:09:50.093880 INFO: [APUAPC] D9_APC_3: 0x0
9944 23:09:50.097056 INFO: [APUAPC] D10_APC_0: 0xffffffff
9945 23:09:50.100383 INFO: [APUAPC] D10_APC_1: 0xffffffff
9946 23:09:50.104025 INFO: [APUAPC] D10_APC_2: 0x3fffff
9947 23:09:50.107642 INFO: [APUAPC] D10_APC_3: 0x0
9948 23:09:50.110508 INFO: [APUAPC] D11_APC_0: 0xffffffff
9949 23:09:50.113864 INFO: [APUAPC] D11_APC_1: 0xffffffff
9950 23:09:50.117136 INFO: [APUAPC] D11_APC_2: 0x3fffff
9951 23:09:50.120517 INFO: [APUAPC] D11_APC_3: 0x0
9952 23:09:50.123452 INFO: [APUAPC] D12_APC_0: 0xffffffff
9953 23:09:50.127142 INFO: [APUAPC] D12_APC_1: 0xffffffff
9954 23:09:50.130244 INFO: [APUAPC] D12_APC_2: 0x3fffff
9955 23:09:50.133482 INFO: [APUAPC] D12_APC_3: 0x0
9956 23:09:50.136820 INFO: [APUAPC] D13_APC_0: 0xffffffff
9957 23:09:50.140437 INFO: [APUAPC] D13_APC_1: 0xffffffff
9958 23:09:50.143474 INFO: [APUAPC] D13_APC_2: 0x3fffff
9959 23:09:50.147048 INFO: [APUAPC] D13_APC_3: 0x0
9960 23:09:50.149917 INFO: [APUAPC] D14_APC_0: 0xffffffff
9961 23:09:50.153475 INFO: [APUAPC] D14_APC_1: 0xffffffff
9962 23:09:50.156344 INFO: [APUAPC] D14_APC_2: 0x3fffff
9963 23:09:50.159894 INFO: [APUAPC] D14_APC_3: 0x0
9964 23:09:50.163049 INFO: [APUAPC] D15_APC_0: 0xffffffff
9965 23:09:50.166584 INFO: [APUAPC] D15_APC_1: 0xffffffff
9966 23:09:50.169716 INFO: [APUAPC] D15_APC_2: 0x3fffff
9967 23:09:50.173329 INFO: [APUAPC] D15_APC_3: 0x0
9968 23:09:50.176229 INFO: [APUAPC] APC_CON: 0x4
9969 23:09:50.179896 INFO: [NOCDAPC] D0_APC_0: 0x0
9970 23:09:50.182715 INFO: [NOCDAPC] D0_APC_1: 0x0
9971 23:09:50.186263 INFO: [NOCDAPC] D1_APC_0: 0x0
9972 23:09:50.186344 INFO: [NOCDAPC] D1_APC_1: 0xfff
9973 23:09:50.189394 INFO: [NOCDAPC] D2_APC_0: 0x0
9974 23:09:50.192960 INFO: [NOCDAPC] D2_APC_1: 0xfff
9975 23:09:50.196109 INFO: [NOCDAPC] D3_APC_0: 0x0
9976 23:09:50.199505 INFO: [NOCDAPC] D3_APC_1: 0xfff
9977 23:09:50.202957 INFO: [NOCDAPC] D4_APC_0: 0x0
9978 23:09:50.206003 INFO: [NOCDAPC] D4_APC_1: 0xfff
9979 23:09:50.209410 INFO: [NOCDAPC] D5_APC_0: 0x0
9980 23:09:50.212878 INFO: [NOCDAPC] D5_APC_1: 0xfff
9981 23:09:50.215952 INFO: [NOCDAPC] D6_APC_0: 0x0
9982 23:09:50.219561 INFO: [NOCDAPC] D6_APC_1: 0xfff
9983 23:09:50.219643 INFO: [NOCDAPC] D7_APC_0: 0x0
9984 23:09:50.222726 INFO: [NOCDAPC] D7_APC_1: 0xfff
9985 23:09:50.225972 INFO: [NOCDAPC] D8_APC_0: 0x0
9986 23:09:50.229497 INFO: [NOCDAPC] D8_APC_1: 0xfff
9987 23:09:50.232829 INFO: [NOCDAPC] D9_APC_0: 0x0
9988 23:09:50.235874 INFO: [NOCDAPC] D9_APC_1: 0xfff
9989 23:09:50.239250 INFO: [NOCDAPC] D10_APC_0: 0x0
9990 23:09:50.242609 INFO: [NOCDAPC] D10_APC_1: 0xfff
9991 23:09:50.246029 INFO: [NOCDAPC] D11_APC_0: 0x0
9992 23:09:50.249637 INFO: [NOCDAPC] D11_APC_1: 0xfff
9993 23:09:50.252517 INFO: [NOCDAPC] D12_APC_0: 0x0
9994 23:09:50.256232 INFO: [NOCDAPC] D12_APC_1: 0xfff
9995 23:09:50.259222 INFO: [NOCDAPC] D13_APC_0: 0x0
9996 23:09:50.259300 INFO: [NOCDAPC] D13_APC_1: 0xfff
9997 23:09:50.262626 INFO: [NOCDAPC] D14_APC_0: 0x0
9998 23:09:50.266071 INFO: [NOCDAPC] D14_APC_1: 0xfff
9999 23:09:50.269173 INFO: [NOCDAPC] D15_APC_0: 0x0
10000 23:09:50.272299 INFO: [NOCDAPC] D15_APC_1: 0xfff
10001 23:09:50.275899 INFO: [NOCDAPC] APC_CON: 0x4
10002 23:09:50.278827 INFO: [APUAPC] set_apusys_apc done
10003 23:09:50.282608 INFO: [DEVAPC] devapc_init done
10004 23:09:50.286214 INFO: GICv3 without legacy support detected.
10005 23:09:50.292269 INFO: ARM GICv3 driver initialized in EL3
10006 23:09:50.295773 INFO: Maximum SPI INTID supported: 639
10007 23:09:50.298770 INFO: BL31: Initializing runtime services
10008 23:09:50.305757 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10009 23:09:50.305839 INFO: SPM: enable CPC mode
10010 23:09:50.312231 INFO: mcdi ready for mcusys-off-idle and system suspend
10011 23:09:50.315447 INFO: BL31: Preparing for EL3 exit to normal world
10012 23:09:50.318960 INFO: Entry point address = 0x80000000
10013 23:09:50.322315 INFO: SPSR = 0x8
10014 23:09:50.328367
10015 23:09:50.328447
10016 23:09:50.328511
10017 23:09:50.331490 Starting depthcharge on Spherion...
10018 23:09:50.331570
10019 23:09:50.331634 Wipe memory regions:
10020 23:09:50.331706
10021 23:09:50.332374 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10022 23:09:50.332474 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10023 23:09:50.332585 Setting prompt string to ['asurada:']
10024 23:09:50.332699 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10025 23:09:50.334821 [0x00000040000000, 0x00000054600000)
10026 23:09:50.457284
10027 23:09:50.457417 [0x00000054660000, 0x00000080000000)
10028 23:09:50.718048
10029 23:09:50.718179 [0x000000821a7280, 0x000000ffe64000)
10030 23:09:51.462509
10031 23:09:51.462640 [0x00000100000000, 0x00000240000000)
10032 23:09:53.352744
10033 23:09:53.356033 Initializing XHCI USB controller at 0x11200000.
10034 23:09:54.393710
10035 23:09:54.397267 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10036 23:09:54.397364
10037 23:09:54.397429
10038 23:09:54.397489
10039 23:09:54.397772 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10041 23:09:54.498144 asurada: tftpboot 192.168.201.1 12172398/tftp-deploy-iy98jilq/kernel/image.itb 12172398/tftp-deploy-iy98jilq/kernel/cmdline
10042 23:09:54.498278 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10043 23:09:54.498396 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10044 23:09:54.502619 tftpboot 192.168.201.1 12172398/tftp-deploy-iy98jilq/kernel/image.itp-deploy-iy98jilq/kernel/cmdline
10045 23:09:54.502702
10046 23:09:54.502766 Waiting for link
10047 23:09:54.663230
10048 23:09:54.663369 R8152: Initializing
10049 23:09:54.663470
10050 23:09:54.666079 Version 9 (ocp_data = 6010)
10051 23:09:54.666161
10052 23:09:54.669655 R8152: Done initializing
10053 23:09:54.669760
10054 23:09:54.669854 Adding net device
10055 23:09:56.615588
10056 23:09:56.615752 done.
10057 23:09:56.615849
10058 23:09:56.615944 MAC: 00:e0:4c:78:7a:aa
10059 23:09:56.616033
10060 23:09:56.619411 Sending DHCP discover... done.
10061 23:09:56.619514
10062 23:09:59.829918 Waiting for reply... done.
10063 23:09:59.830097
10064 23:09:59.830199 Sending DHCP request... done.
10065 23:09:59.833282
10066 23:09:59.833386 Waiting for reply... done.
10067 23:09:59.833487
10068 23:09:59.836399 My ip is 192.168.201.12
10069 23:09:59.836494
10070 23:09:59.839848 The DHCP server ip is 192.168.201.1
10071 23:09:59.839950
10072 23:09:59.843405 TFTP server IP predefined by user: 192.168.201.1
10073 23:09:59.843500
10074 23:09:59.850044 Bootfile predefined by user: 12172398/tftp-deploy-iy98jilq/kernel/image.itb
10075 23:09:59.850123
10076 23:09:59.853042 Sending tftp read request... done.
10077 23:09:59.853141
10078 23:09:59.856698 Waiting for the transfer...
10079 23:09:59.856795
10080 23:10:00.132632 00000000 ################################################################
10081 23:10:00.132768
10082 23:10:00.390143 00080000 ################################################################
10083 23:10:00.390311
10084 23:10:00.643390 00100000 ################################################################
10085 23:10:00.643523
10086 23:10:00.894153 00180000 ################################################################
10087 23:10:00.894286
10088 23:10:01.146002 00200000 ################################################################
10089 23:10:01.146137
10090 23:10:01.418317 00280000 ################################################################
10091 23:10:01.418488
10092 23:10:01.690043 00300000 ################################################################
10093 23:10:01.690221
10094 23:10:01.980858 00380000 ################################################################
10095 23:10:01.980997
10096 23:10:02.254428 00400000 ################################################################
10097 23:10:02.254567
10098 23:10:02.525057 00480000 ################################################################
10099 23:10:02.525192
10100 23:10:02.779928 00500000 ################################################################
10101 23:10:02.780062
10102 23:10:03.036023 00580000 ################################################################
10103 23:10:03.036155
10104 23:10:03.293502 00600000 ################################################################
10105 23:10:03.293705
10106 23:10:03.554101 00680000 ################################################################
10107 23:10:03.554241
10108 23:10:03.814340 00700000 ################################################################
10109 23:10:03.814471
10110 23:10:04.081876 00780000 ################################################################
10111 23:10:04.082009
10112 23:10:04.339794 00800000 ################################################################
10113 23:10:04.339924
10114 23:10:04.604316 00880000 ################################################################
10115 23:10:04.604451
10116 23:10:04.885898 00900000 ################################################################
10117 23:10:04.886033
10118 23:10:05.158841 00980000 ################################################################
10119 23:10:05.158977
10120 23:10:05.416088 00a00000 ################################################################
10121 23:10:05.416215
10122 23:10:05.673230 00a80000 ################################################################
10123 23:10:05.673366
10124 23:10:05.941365 00b00000 ################################################################
10125 23:10:05.941494
10126 23:10:06.212000 00b80000 ################################################################
10127 23:10:06.212144
10128 23:10:06.473355 00c00000 ################################################################
10129 23:10:06.473529
10130 23:10:06.728555 00c80000 ################################################################
10131 23:10:06.728700
10132 23:10:07.010815 00d00000 ################################################################
10133 23:10:07.010957
10134 23:10:07.281011 00d80000 ################################################################
10135 23:10:07.281148
10136 23:10:07.545791 00e00000 ################################################################
10137 23:10:07.545921
10138 23:10:07.832207 00e80000 ################################################################
10139 23:10:07.832350
10140 23:10:08.115860 00f00000 ################################################################
10141 23:10:08.115991
10142 23:10:08.393463 00f80000 ################################################################
10143 23:10:08.393624
10144 23:10:08.644711 01000000 ################################################################
10145 23:10:08.644847
10146 23:10:08.895727 01080000 ################################################################
10147 23:10:08.895858
10148 23:10:09.147616 01100000 ################################################################
10149 23:10:09.147761
10150 23:10:09.398518 01180000 ################################################################
10151 23:10:09.398651
10152 23:10:09.649063 01200000 ################################################################
10153 23:10:09.649221
10154 23:10:09.906326 01280000 ################################################################
10155 23:10:09.906476
10156 23:10:10.157739 01300000 ################################################################
10157 23:10:10.157897
10158 23:10:10.406312 01380000 ################################################################
10159 23:10:10.406452
10160 23:10:10.655070 01400000 ################################################################
10161 23:10:10.655205
10162 23:10:10.902914 01480000 ################################################################
10163 23:10:10.903051
10164 23:10:11.152271 01500000 ################################################################
10165 23:10:11.152408
10166 23:10:11.423770 01580000 ################################################################
10167 23:10:11.423929
10168 23:10:11.676253 01600000 ################################################################
10169 23:10:11.676413
10170 23:10:11.942959 01680000 ################################################################
10171 23:10:11.943095
10172 23:10:12.202365 01700000 ################################################################
10173 23:10:12.202499
10174 23:10:12.451020 01780000 ################################################################
10175 23:10:12.451172
10176 23:10:12.696519 01800000 ################################################################
10177 23:10:12.696706
10178 23:10:12.954508 01880000 ################################################################
10179 23:10:12.954664
10180 23:10:13.198978 01900000 ################################################################
10181 23:10:13.199127
10182 23:10:13.446704 01980000 ################################################################
10183 23:10:13.446837
10184 23:10:13.693801 01a00000 ################################################################
10185 23:10:13.693936
10186 23:10:13.944447 01a80000 ################################################################
10187 23:10:13.944580
10188 23:10:14.189415 01b00000 ################################################################
10189 23:10:14.189572
10190 23:10:14.437870 01b80000 ################################################################
10191 23:10:14.437998
10192 23:10:14.693191 01c00000 ################################################################
10193 23:10:14.693324
10194 23:10:14.947739 01c80000 ################################################################
10195 23:10:14.947874
10196 23:10:15.196549 01d00000 ################################################################
10197 23:10:15.196677
10198 23:10:15.449082 01d80000 ################################################################
10199 23:10:15.449208
10200 23:10:15.704708 01e00000 ################################################################
10201 23:10:15.704841
10202 23:10:15.953585 01e80000 ################################################################
10203 23:10:15.953750
10204 23:10:16.201258 01f00000 ################################################################
10205 23:10:16.201387
10206 23:10:16.454874 01f80000 ################################################################
10207 23:10:16.455007
10208 23:10:16.716226 02000000 ################################################################
10209 23:10:16.716351
10210 23:10:16.978743 02080000 ################################################################
10211 23:10:16.978909
10212 23:10:17.256912 02100000 ################################################################
10213 23:10:17.257069
10214 23:10:17.508645 02180000 ################################################################
10215 23:10:17.508803
10216 23:10:17.777907 02200000 ################################################################
10217 23:10:17.778076
10218 23:10:18.035146 02280000 ################################################################
10219 23:10:18.035312
10220 23:10:18.302721 02300000 ################################################################
10221 23:10:18.302886
10222 23:10:18.559896 02380000 ################################################################
10223 23:10:18.560064
10224 23:10:18.815921 02400000 ################################################################
10225 23:10:18.816078
10226 23:10:19.071937 02480000 ################################################################
10227 23:10:19.072102
10228 23:10:19.327052 02500000 ################################################################
10229 23:10:19.327189
10230 23:10:19.589659 02580000 ################################################################
10231 23:10:19.589792
10232 23:10:19.858567 02600000 ################################################################
10233 23:10:19.858710
10234 23:10:20.134209 02680000 ################################################################
10235 23:10:20.134367
10236 23:10:20.398988 02700000 ################################################################
10237 23:10:20.399126
10238 23:10:20.705858 02780000 ################################################################
10239 23:10:20.706002
10240 23:10:21.062879 02800000 ################################################################
10241 23:10:21.063022
10242 23:10:21.422090 02880000 ################################################################
10243 23:10:21.422242
10244 23:10:21.766617 02900000 ################################################################
10245 23:10:21.766764
10246 23:10:22.072424 02980000 ################################################################
10247 23:10:22.072559
10248 23:10:22.329495 02a00000 ################################################################
10249 23:10:22.329689
10250 23:10:22.582092 02a80000 ################################################################
10251 23:10:22.582244
10252 23:10:22.840751 02b00000 ################################################################
10253 23:10:22.840888
10254 23:10:23.102389 02b80000 ################################################################
10255 23:10:23.102521
10256 23:10:23.356082 02c00000 ################################################################
10257 23:10:23.356232
10258 23:10:23.631675 02c80000 ################################################################
10259 23:10:23.631835
10260 23:10:23.894526 02d00000 ################################################################
10261 23:10:23.894667
10262 23:10:24.154605 02d80000 ################################################################
10263 23:10:24.154742
10264 23:10:24.402453 02e00000 ################################################################
10265 23:10:24.402598
10266 23:10:24.668256 02e80000 ################################################################
10267 23:10:24.668404
10268 23:10:24.916773 02f00000 ################################################################
10269 23:10:24.916911
10270 23:10:25.163035 02f80000 ################################################################
10271 23:10:25.163170
10272 23:10:25.418811 03000000 ################################################################
10273 23:10:25.418939
10274 23:10:25.701924 03080000 ################################################################
10275 23:10:25.702072
10276 23:10:25.981863 03100000 ################################################################
10277 23:10:25.982000
10278 23:10:26.237798 03180000 ################################################################
10279 23:10:26.237932
10280 23:10:26.519699 03200000 ################################################################
10281 23:10:26.519833
10282 23:10:26.779096 03280000 ################################################################
10283 23:10:26.779225
10284 23:10:27.053745 03300000 ################################################################
10285 23:10:27.053879
10286 23:10:27.334759 03380000 ################################################################
10287 23:10:27.334909
10288 23:10:27.615174 03400000 ################################################################
10289 23:10:27.615337
10290 23:10:27.867846 03480000 ################################################################
10291 23:10:27.868028
10292 23:10:28.115418 03500000 ################################################################
10293 23:10:28.115559
10294 23:10:28.362385 03580000 ################################################################
10295 23:10:28.362544
10296 23:10:28.665313 03600000 ################################################################
10297 23:10:28.665496
10298 23:10:29.017061 03680000 ################################################################
10299 23:10:29.017199
10300 23:10:29.375755 03700000 ################################################################
10301 23:10:29.375908
10302 23:10:29.733169 03780000 ################################################################
10303 23:10:29.733322
10304 23:10:30.087572 03800000 ################################################################
10305 23:10:30.087719
10306 23:10:30.442783 03880000 ################################################################
10307 23:10:30.442929
10308 23:10:30.799227 03900000 ################################################################
10309 23:10:30.799376
10310 23:10:31.153993 03980000 ################################################################
10311 23:10:31.154128
10312 23:10:31.512835 03a00000 ################################################################
10313 23:10:31.512988
10314 23:10:31.868553 03a80000 ################################################################
10315 23:10:31.868687
10316 23:10:32.201113 03b00000 ################################################################
10317 23:10:32.201264
10318 23:10:32.509880 03b80000 ################################################################
10319 23:10:32.510017
10320 23:10:32.756933 03c00000 ################################################################
10321 23:10:32.757084
10322 23:10:33.019730 03c80000 ################################################################
10323 23:10:33.019879
10324 23:10:33.280950 03d00000 ################################################################
10325 23:10:33.281087
10326 23:10:33.580758 03d80000 ################################################################
10327 23:10:33.580908
10328 23:10:33.925442 03e00000 ################################################################
10329 23:10:33.925654
10330 23:10:34.286644 03e80000 ################################################################
10331 23:10:34.286779
10332 23:10:34.635614 03f00000 ################################################################
10333 23:10:34.635767
10334 23:10:34.996465 03f80000 ################################################################
10335 23:10:34.996600
10336 23:10:35.352786 04000000 ################################################################
10337 23:10:35.352973
10338 23:10:35.719736 04080000 ################################################################
10339 23:10:35.719887
10340 23:10:36.078074 04100000 ################################################################
10341 23:10:36.078230
10342 23:10:36.431350 04180000 ################################################################
10343 23:10:36.431499
10344 23:10:36.794341 04200000 ################################################################
10345 23:10:36.794478
10346 23:10:37.102870 04280000 ################################################################
10347 23:10:37.103023
10348 23:10:37.465670 04300000 ################################################################
10349 23:10:37.465808
10350 23:10:37.826488 04380000 ################################################################
10351 23:10:37.826632
10352 23:10:38.186694 04400000 ################################################################
10353 23:10:38.186829
10354 23:10:38.548165 04480000 ################################################################
10355 23:10:38.548336
10356 23:10:38.910483 04500000 ################################################################
10357 23:10:38.910648
10358 23:10:39.267550 04580000 ################################################################
10359 23:10:39.267717
10360 23:10:39.631665 04600000 ################################################################
10361 23:10:39.631866
10362 23:10:39.999595 04680000 ################################################################
10363 23:10:39.999745
10364 23:10:40.367614 04700000 ################################################################
10365 23:10:40.367771
10366 23:10:40.706069 04780000 ################################################################
10367 23:10:40.706212
10368 23:10:41.049124 04800000 ################################################################
10369 23:10:41.049282
10370 23:10:41.414237 04880000 ################################################################
10371 23:10:41.414433
10372 23:10:41.781010 04900000 ################################################################
10373 23:10:41.781162
10374 23:10:42.144891 04980000 ################################################################
10375 23:10:42.145046
10376 23:10:42.511876 04a00000 ################################################################
10377 23:10:42.512022
10378 23:10:42.877359 04a80000 ################################################################
10379 23:10:42.877508
10380 23:10:43.245970 04b00000 ################################################################
10381 23:10:43.246119
10382 23:10:43.611224 04b80000 ################################################################
10383 23:10:43.611367
10384 23:10:43.976682 04c00000 ################################################################
10385 23:10:43.976828
10386 23:10:44.334091 04c80000 ################################################################
10387 23:10:44.334227
10388 23:10:44.592151 04d00000 ################################################################
10389 23:10:44.592289
10390 23:10:44.876157 04d80000 ################################################################
10391 23:10:44.876291
10392 23:10:45.235487 04e00000 ################################################################
10393 23:10:45.235636
10394 23:10:45.592423 04e80000 ################################################################
10395 23:10:45.592569
10396 23:10:45.958643 04f00000 ################################################################
10397 23:10:45.958789
10398 23:10:46.319292 04f80000 ################################################################
10399 23:10:46.319423
10400 23:10:46.687735 05000000 ################################################################
10401 23:10:46.687879
10402 23:10:47.050086 05080000 ################################################################
10403 23:10:47.050224
10404 23:10:47.413794 05100000 ################################################################
10405 23:10:47.413937
10406 23:10:47.775788 05180000 ################################################################
10407 23:10:47.775934
10408 23:10:48.140273 05200000 ################################################################
10409 23:10:48.140408
10410 23:10:48.506632 05280000 ################################################################
10411 23:10:48.506776
10412 23:10:48.863583 05300000 ################################################################
10413 23:10:48.863733
10414 23:10:49.226945 05380000 ################################################################
10415 23:10:49.227094
10416 23:10:49.589316 05400000 ################################################################
10417 23:10:49.589493
10418 23:10:49.951958 05480000 ################################################################
10419 23:10:49.952097
10420 23:10:50.316591 05500000 ################################################################
10421 23:10:50.316745
10422 23:10:50.678909 05580000 ################################################################
10423 23:10:50.679038
10424 23:10:51.042037 05600000 ################################################################
10425 23:10:51.042180
10426 23:10:51.406897 05680000 ################################################################
10427 23:10:51.407042
10428 23:10:51.775031 05700000 ################################################################
10429 23:10:51.775209
10430 23:10:52.140092 05780000 ################################################################
10431 23:10:52.140237
10432 23:10:52.506137 05800000 ################################################################
10433 23:10:52.506313
10434 23:10:52.866291 05880000 ################################################################
10435 23:10:52.866468
10436 23:10:53.233303 05900000 ################################################################
10437 23:10:53.233468
10438 23:10:53.592925 05980000 ################################################################
10439 23:10:53.593103
10440 23:10:53.956504 05a00000 ################################################################
10441 23:10:53.956671
10442 23:10:54.321551 05a80000 ################################################################
10443 23:10:54.321769
10444 23:10:54.683729 05b00000 ################################################################
10445 23:10:54.683891
10446 23:10:55.046880 05b80000 ################################################################
10447 23:10:55.047059
10448 23:10:55.411592 05c00000 ################################################################
10449 23:10:55.411727
10450 23:10:55.775852 05c80000 ################################################################
10451 23:10:55.775994
10452 23:10:56.139809 05d00000 ################################################################
10453 23:10:56.139960
10454 23:10:56.504275 05d80000 ################################################################
10455 23:10:56.504448
10456 23:10:56.864581 05e00000 ################################################################
10457 23:10:56.864750
10458 23:10:57.228532 05e80000 ################################################################
10459 23:10:57.228700
10460 23:10:57.592935 05f00000 ################################################################
10461 23:10:57.593110
10462 23:10:57.954791 05f80000 ################################################################
10463 23:10:57.954963
10464 23:10:58.318518 06000000 ################################################################
10465 23:10:58.318684
10466 23:10:58.681622 06080000 ################################################################
10467 23:10:58.681794
10468 23:10:59.042235 06100000 ################################################################
10469 23:10:59.042381
10470 23:10:59.404266 06180000 ################################################################
10471 23:10:59.404416
10472 23:10:59.766922 06200000 ################################################################
10473 23:10:59.767063
10474 23:11:00.132734 06280000 ################################################################
10475 23:11:00.132887
10476 23:11:00.492729 06300000 ################################################################
10477 23:11:00.492878
10478 23:11:00.855083 06380000 ################################################################
10479 23:11:00.855225
10480 23:11:01.219968 06400000 ################################################################
10481 23:11:01.220146
10482 23:11:01.582898 06480000 ################################################################
10483 23:11:01.583037
10484 23:11:01.951134 06500000 ################################################################
10485 23:11:01.951280
10486 23:11:02.314312 06580000 ################################################################
10487 23:11:02.314448
10488 23:11:02.675879 06600000 ################################################################
10489 23:11:02.676021
10490 23:11:03.039076 06680000 ################################################################
10491 23:11:03.039219
10492 23:11:03.400250 06700000 ################################################################
10493 23:11:03.400399
10494 23:11:03.767701 06780000 ################################################################
10495 23:11:03.767886
10496 23:11:04.038529 06800000 ################################################ done.
10497 23:11:04.038703
10498 23:11:04.041618 The bootfile was 109441158 bytes long.
10499 23:11:04.041775
10500 23:11:04.045259 Sending tftp read request... done.
10501 23:11:04.045365
10502 23:11:04.045457 Waiting for the transfer...
10503 23:11:04.045551
10504 23:11:04.048745 00000000 # done.
10505 23:11:04.048827
10506 23:11:04.055135 Command line loaded dynamically from TFTP file: 12172398/tftp-deploy-iy98jilq/kernel/cmdline
10507 23:11:04.055239
10508 23:11:04.068483 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10509 23:11:04.068584
10510 23:11:04.071620 Loading FIT.
10511 23:11:04.071718
10512 23:11:04.075235 Image ramdisk-1 has 98342497 bytes.
10513 23:11:04.075331
10514 23:11:04.075431 Image fdt-1 has 47278 bytes.
10515 23:11:04.075517
10516 23:11:04.078571 Image kernel-1 has 11049348 bytes.
10517 23:11:04.078647
10518 23:11:04.088332 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10519 23:11:04.088407
10520 23:11:04.105239 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10521 23:11:04.105329
10522 23:11:04.111869 Choosing best match conf-1 for compat google,spherion-rev2.
10523 23:11:04.115201
10524 23:11:04.120211 Connected to device vid:did:rid of 1ae0:0028:00
10525 23:11:04.128314
10526 23:11:04.131084 tpm_get_response: command 0x17b, return code 0x0
10527 23:11:04.131169
10528 23:11:04.134689 ec_init: CrosEC protocol v3 supported (256, 248)
10529 23:11:04.138613
10530 23:11:04.141998 tpm_cleanup: add release locality here.
10531 23:11:04.142086
10532 23:11:04.142149 Shutting down all USB controllers.
10533 23:11:04.145468
10534 23:11:04.145547 Removing current net device
10535 23:11:04.145655
10536 23:11:04.151760 Exiting depthcharge with code 4 at timestamp: 103112633
10537 23:11:04.151848
10538 23:11:04.155410 LZMA decompressing kernel-1 to 0x821a6718
10539 23:11:04.155492
10540 23:11:04.158411 LZMA decompressing kernel-1 to 0x40000000
10541 23:11:05.547333
10542 23:11:05.547489 jumping to kernel
10543 23:11:05.548051 end: 2.2.4 bootloader-commands (duration 00:01:15) [common]
10544 23:11:05.548150 start: 2.2.5 auto-login-action (timeout 00:03:10) [common]
10545 23:11:05.548229 Setting prompt string to ['Linux version [0-9]']
10546 23:11:05.548299 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10547 23:11:05.548368 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10548 23:11:05.629278
10549 23:11:05.632533 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10550 23:11:05.636417 start: 2.2.5.1 login-action (timeout 00:03:10) [common]
10551 23:11:05.636525 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10552 23:11:05.636625 Setting prompt string to []
10553 23:11:05.636733 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10554 23:11:05.636834 Using line separator: #'\n'#
10555 23:11:05.636923 No login prompt set.
10556 23:11:05.636998 Parsing kernel messages
10557 23:11:05.637070 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10558 23:11:05.637173 [login-action] Waiting for messages, (timeout 00:03:10)
10559 23:11:05.655857 [ 0.000000] Linux version 6.1.64-cip10-rt5 (KernelCI@build-j33605-arm64-gcc-10-defconfig-arm64-chromebook-7778h) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sun Dec 3 22:38:18 UTC 2023
10560 23:11:05.659570 [ 0.000000] random: crng init done
10561 23:11:05.665748 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10562 23:11:05.669639 [ 0.000000] efi: UEFI not found.
10563 23:11:05.676035 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10564 23:11:05.683148 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10565 23:11:05.692442 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10566 23:11:05.702227 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10567 23:11:05.709129 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10568 23:11:05.715635 [ 0.000000] printk: bootconsole [mtk8250] enabled
10569 23:11:05.722056 [ 0.000000] NUMA: No NUMA configuration found
10570 23:11:05.728643 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10571 23:11:05.732005 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10572 23:11:05.735279 [ 0.000000] Zone ranges:
10573 23:11:05.742202 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10574 23:11:05.745120 [ 0.000000] DMA32 empty
10575 23:11:05.752044 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10576 23:11:05.755033 [ 0.000000] Movable zone start for each node
10577 23:11:05.758701 [ 0.000000] Early memory node ranges
10578 23:11:05.765344 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10579 23:11:05.771796 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10580 23:11:05.778428 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10581 23:11:05.785100 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10582 23:11:05.788614 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10583 23:11:05.798377 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10584 23:11:05.853863 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10585 23:11:05.860980 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10586 23:11:05.867055 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10587 23:11:05.870671 [ 0.000000] psci: probing for conduit method from DT.
10588 23:11:05.876948 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10589 23:11:05.880502 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10590 23:11:05.887020 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10591 23:11:05.890500 [ 0.000000] psci: SMC Calling Convention v1.2
10592 23:11:05.896805 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10593 23:11:05.900136 [ 0.000000] Detected VIPT I-cache on CPU0
10594 23:11:05.906882 [ 0.000000] CPU features: detected: GIC system register CPU interface
10595 23:11:05.913372 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10596 23:11:05.919942 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10597 23:11:05.926826 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10598 23:11:05.933488 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10599 23:11:05.943018 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10600 23:11:05.946453 [ 0.000000] alternatives: applying boot alternatives
10601 23:11:05.953170 [ 0.000000] Fallback order for Node 0: 0
10602 23:11:05.959817 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10603 23:11:05.963413 [ 0.000000] Policy zone: Normal
10604 23:11:05.976283 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10605 23:11:05.986289 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10606 23:11:05.998199 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10607 23:11:06.008478 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10608 23:11:06.015030 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10609 23:11:06.017951 <6>[ 0.000000] software IO TLB: area num 8.
10610 23:11:06.074554 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10611 23:11:06.223393 <6>[ 0.000000] Memory: 7873520K/8385536K available (17984K kernel code, 4116K rwdata, 17316K rodata, 8448K init, 615K bss, 479248K reserved, 32768K cma-reserved)
10612 23:11:06.230402 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10613 23:11:06.236757 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10614 23:11:06.239880 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10615 23:11:06.247033 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10616 23:11:06.253569 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10617 23:11:06.257018 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10618 23:11:06.266835 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10619 23:11:06.273168 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10620 23:11:06.280073 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10621 23:11:06.286534 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10622 23:11:06.289819 <6>[ 0.000000] GICv3: 608 SPIs implemented
10623 23:11:06.293340 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10624 23:11:06.299755 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10625 23:11:06.303109 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10626 23:11:06.309894 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10627 23:11:06.323384 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10628 23:11:06.333123 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10629 23:11:06.342743 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10630 23:11:06.350172 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10631 23:11:06.363362 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10632 23:11:06.370143 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10633 23:11:06.377018 <6>[ 0.009188] Console: colour dummy device 80x25
10634 23:11:06.386857 <6>[ 0.013910] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10635 23:11:06.389807 <6>[ 0.024352] pid_max: default: 32768 minimum: 301
10636 23:11:06.396529 <6>[ 0.029253] LSM: Security Framework initializing
10637 23:11:06.403128 <6>[ 0.034189] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10638 23:11:06.413140 <6>[ 0.042051] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10639 23:11:06.419654 <6>[ 0.051454] cblist_init_generic: Setting adjustable number of callback queues.
10640 23:11:06.426607 <6>[ 0.058943] cblist_init_generic: Setting shift to 3 and lim to 1.
10641 23:11:06.436907 <6>[ 0.065280] cblist_init_generic: Setting adjustable number of callback queues.
10642 23:11:06.443375 <6>[ 0.072708] cblist_init_generic: Setting shift to 3 and lim to 1.
10643 23:11:06.446184 <6>[ 0.079186] rcu: Hierarchical SRCU implementation.
10644 23:11:06.453359 <6>[ 0.079188] rcu: Max phase no-delay instances is 1000.
10645 23:11:06.459957 <6>[ 0.079212] printk: bootconsole [mtk8250] printing thread started
10646 23:11:06.466436 <6>[ 0.097533] EFI services will not be available.
10647 23:11:06.469854 <6>[ 0.097735] smp: Bringing up secondary CPUs ...
10648 23:11:06.472941 <6>[ 0.098042] Detected VIPT I-cache on CPU1
10649 23:11:06.482624 <6>[ 0.098110] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10650 23:11:06.489502 <6>[ 0.098141] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10651 23:11:06.498169 <6>[ 0.126016] Detected VIPT I-cache on CPU2
10652 23:11:06.505166 <6>[ 0.126062] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10653 23:11:06.514800 <6>[ 0.126077] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10654 23:11:06.518470 <6>[ 0.126332] Detected VIPT I-cache on CPU3
10655 23:11:06.524827 <6>[ 0.126378] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10656 23:11:06.531487 <6>[ 0.126392] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10657 23:11:06.534818 <6>[ 0.126699] CPU features: detected: Spectre-v4
10658 23:11:06.541376 <6>[ 0.126705] CPU features: detected: Spectre-BHB
10659 23:11:06.544518 <6>[ 0.126709] Detected PIPT I-cache on CPU4
10660 23:11:06.551000 <6>[ 0.126766] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10661 23:11:06.558051 <6>[ 0.126783] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10662 23:11:06.564674 <6>[ 0.127073] Detected PIPT I-cache on CPU5
10663 23:11:06.571603 <6>[ 0.127132] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10664 23:11:06.577917 <6>[ 0.127149] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10665 23:11:06.581343 <6>[ 0.127423] Detected PIPT I-cache on CPU6
10666 23:11:06.587709 <6>[ 0.127486] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10667 23:11:06.594864 <6>[ 0.127502] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10668 23:11:06.600961 <6>[ 0.127793] Detected PIPT I-cache on CPU7
10669 23:11:06.607915 <6>[ 0.127857] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10670 23:11:06.614473 <6>[ 0.127873] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10671 23:11:06.617440 <6>[ 0.127919] smp: Brought up 1 node, 8 CPUs
10672 23:11:06.624254 <6>[ 0.127924] SMP: Total of 8 processors activated.
10673 23:11:06.627636 <6>[ 0.127926] CPU features: detected: 32-bit EL0 Support
10674 23:11:06.637724 <6>[ 0.127928] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10675 23:11:06.644391 <6>[ 0.127931] CPU features: detected: Common not Private translations
10676 23:11:06.650947 <6>[ 0.127932] CPU features: detected: CRC32 instructions
10677 23:11:06.654041 <6>[ 0.127935] CPU features: detected: RCpc load-acquire (LDAPR)
10678 23:11:06.660865 <6>[ 0.127936] CPU features: detected: LSE atomic instructions
10679 23:11:06.667256 <6>[ 0.127938] CPU features: detected: Privileged Access Never
10680 23:11:06.673937 <6>[ 0.127940] CPU features: detected: RAS Extension Support
10681 23:11:06.680132 <6>[ 0.127943] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10682 23:11:06.683550 <6>[ 0.128010] CPU: All CPU(s) started at EL2
10683 23:11:06.689909 <6>[ 0.128011] alternatives: applying system-wide alternatives
10684 23:11:06.693485 <6>[ 0.141083] devtmpfs: initialized
10685 23:11:06.703759 <6>[ 0.147294] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10686 23:11:06.731619 �EYVkW��4*ԕʪ2.�������2�����5R�<6>[ 0.36<4394] printk: console [ttyS0] printing thread started
10687 23:11:06.738380 6<6>[ 0.364426] printk: console [ttyS0] enabled
10688 23:11:06.744765 >[ 0.228662] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10689 23:11:06.752858 <6>[ 0.364430] printk: bootconsole [mtk8250] disabled
10690 23:11:06.759557 <6>[ 0.382506] printk: bootconsole [mtk8250] printing thread stopped
10691 23:11:06.762954 <6>[ 0.383680] SuperH (H)SCI(F) driver initialized
10692 23:11:06.769543 <6>[ 0.384157] msm_serial: driver initialized
10693 23:11:06.776021 <6>[ 0.388742] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10694 23:11:06.785705 <6>[ 0.388771] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10695 23:11:06.792621 <6>[ 0.388803] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10696 23:11:06.804990 <6>[ 0.388833] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10697 23:11:06.810109 <6>[ 0.388854] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10698 23:11:06.828726 <6>[ 0.388882] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10699 23:11:06.844708 <6>[ 0.388910] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10700 23:11:06.844793 <6>[ 0.389015] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10701 23:11:06.850319 <6>[ 0.389044] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10702 23:11:06.850400 <6>[ 0.400506] loop: module loaded
10703 23:11:06.856073 <6>[ 0.403033] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10704 23:11:06.862512 <4>[ 0.420054] mtk-pmic-keys: Failed to locate of_node [id: -1]
10705 23:11:06.866566 <6>[ 0.420921] megasas: 07.719.03.00-rc1
10706 23:11:06.870496 <6>[ 0.432937] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10707 23:11:06.876428 <6>[ 0.440505] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10708 23:11:06.883777 <6>[ 0.452534] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10709 23:11:06.893362 <6>[ 0.505898] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10710 23:11:10.616345 <6>[ 4.248014] Freeing initrd memory: 96032K
10711 23:11:10.624582 <6>[ 4.254186] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10712 23:11:10.630763 <6>[ 4.259013] tun: Universal TUN/TAP device driver, 1.6
10713 23:11:10.634178 <6>[ 4.259757] thunder_xcv, ver 1.0
10714 23:11:10.637614 <6>[ 4.259773] thunder_bgx, ver 1.0
10715 23:11:10.641084 <6>[ 4.259789] nicpf, ver 1.0
10716 23:11:10.647606 <6>[ 4.260813] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10717 23:11:10.654050 <6>[ 4.260816] hns3: Copyright (c) 2017 Huawei Corporation.
10718 23:11:10.657418 <6>[ 4.260840] hclge is initializing
10719 23:11:10.664146 <6>[ 4.260857] e1000: Intel(R) PRO/1000 Network Driver
10720 23:11:10.668521 <6>[ 4.260859] e1000: Copyright (c) 1999-2006 Intel Corporation.
10721 23:11:10.675291 <6>[ 4.260878] e1000e: Intel(R) PRO/1000 Network Driver
10722 23:11:10.678637 <6>[ 4.260880] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10723 23:11:10.685494 <6>[ 4.260895] igb: Intel(R) Gigabit Ethernet Network Driver
10724 23:11:10.692040 <6>[ 4.260897] igb: Copyright (c) 2007-2014 Intel Corporation.
10725 23:11:10.699543 <6>[ 4.260910] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10726 23:11:10.703060 <6>[ 4.260912] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10727 23:11:10.709452 <6>[ 4.261207] sky2: driver version 1.30
10728 23:11:10.712673 <6>[ 4.262269] VFIO - User Level meta-driver version: 0.3
10729 23:11:10.719202 <6>[ 4.265089] usbcore: registered new interface driver usb-storage
10730 23:11:10.725921 <6>[ 4.265269] usbcore: registered new device driver onboard-usb-hub
10731 23:11:10.732398 <6>[ 4.268041] mt6397-rtc mt6359-rtc: registered as rtc0
10732 23:11:10.739385 <6>[ 4.268192] mt6397-rtc mt6359-rtc: setting system clock to 2023-12-03T23:08:56 UTC (1701644936)
10733 23:11:10.745454 <6>[ 4.268797] i2c_dev: i2c /dev entries driver
10734 23:11:10.752548 <6>[ 4.275896] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10735 23:11:10.759168 <6>[ 4.290876] cpu cpu0: EM: created perf domain
10736 23:11:10.762035 <6>[ 4.291202] cpu cpu4: EM: created perf domain
10737 23:11:10.768955 <6>[ 4.295607] sdhci: Secure Digital Host Controller Interface driver
10738 23:11:10.771894 <6>[ 4.295609] sdhci: Copyright(c) Pierre Ossman
10739 23:11:10.778987 <6>[ 4.295973] Synopsys Designware Multimedia Card Interface Driver
10740 23:11:10.785177 <6>[ 4.296360] sdhci-pltfm: SDHCI platform and OF driver helper
10741 23:11:10.792107 <6>[ 4.300578] ledtrig-cpu: registered to indicate activity on CPUs
10742 23:11:10.795173 <6>[ 4.301149] mmc0: CQHCI version 5.10
10743 23:11:10.801916 <6>[ 4.301211] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10744 23:11:10.808287 <6>[ 4.301510] usbcore: registered new interface driver usbhid
10745 23:11:10.811675 <6>[ 4.301511] usbhid: USB HID core driver
10746 23:11:10.818401 <6>[ 4.301637] spi_master spi0: will run message pump with realtime priority
10747 23:11:10.831796 <6>[ 4.331766] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10748 23:11:10.844537 <6>[ 4.333818] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10749 23:11:10.851288 <6>[ 4.334771] cros-ec-spi spi0.0: Chrome EC device registered
10750 23:11:10.861550 <6>[ 4.349487] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10751 23:11:10.864775 <6>[ 4.351725] NET: Registered PF_PACKET protocol family
10752 23:11:10.871309 <6>[ 4.351822] 9pnet: Installing 9P2000 support
10753 23:11:10.874626 <5>[ 4.351866] Key type dns_resolver registered
10754 23:11:10.877715 <6>[ 4.352156] registered taskstats version 1
10755 23:11:10.884683 <5>[ 4.352172] Loading compiled-in X.509 certificates
10756 23:11:10.894607 <4>[ 4.373261] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10757 23:11:10.904451 <4>[ 4.373456] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10758 23:11:10.910965 <3>[ 4.373483] debugfs: File 'uA_load' in directory '/' already present!
10759 23:11:10.917253 <3>[ 4.373501] debugfs: File 'min_uV' in directory '/' already present!
10760 23:11:10.924280 <3>[ 4.373507] debugfs: File 'max_uV' in directory '/' already present!
10761 23:11:10.930736 <3>[ 4.373510] debugfs: File 'constraint_flags' in directory '/' already present!
10762 23:11:10.940687 <3>[ 4.375382] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10763 23:11:10.947148 <6>[ 4.382309] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10764 23:11:10.953751 <6>[ 4.382970] xhci-mtk 11200000.usb: xHCI Host Controller
10765 23:11:10.960277 <6>[ 4.382993] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10766 23:11:10.970479 <6>[ 4.383220] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10767 23:11:10.973964 <6>[ 4.383263] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10768 23:11:10.980413 <6>[ 4.383365] xhci-mtk 11200000.usb: xHCI Host Controller
10769 23:11:10.986970 <6>[ 4.383373] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10770 23:11:10.997026 <6>[ 4.383380] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10771 23:11:11.000153 <6>[ 4.383851] hub 1-0:1.0: USB hub found
10772 23:11:11.003593 <6>[ 4.383895] hub 1-0:1.0: 1 port detected
10773 23:11:11.013439 <6>[ 4.384145] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10774 23:11:11.016975 <6>[ 4.384503] hub 2-0:1.0: USB hub found
10775 23:11:11.020397 <6>[ 4.384525] hub 2-0:1.0: 1 port detected
10776 23:11:11.023522 <6>[ 4.387663] mtk-msdc 11f70000.mmc: Got CD GPIO
10777 23:11:11.030390 <6>[ 4.395417] mmc0: Command Queue Engine enabled
10778 23:11:11.037003 <6>[ 4.395429] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10779 23:11:11.040149 <6>[ 4.396083] mmcblk0: mmc0:0001 DA4128 116 GiB
10780 23:11:11.046955 <6>[ 4.399235] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10781 23:11:11.053293 <6>[ 4.400267] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10782 23:11:11.056714 <6>[ 4.401038] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10783 23:11:11.063290 <6>[ 4.401794] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10784 23:11:11.073021 <6>[ 4.402413] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10785 23:11:11.079708 <6>[ 4.402418] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10786 23:11:11.089693 <4>[ 4.402582] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10787 23:11:11.096136 <6>[ 4.403212] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10788 23:11:11.106390 <6>[ 4.403216] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10789 23:11:11.112836 <6>[ 4.403324] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10790 23:11:11.119270 <6>[ 4.403339] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10791 23:11:11.129188 <6>[ 4.403343] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10792 23:11:11.136232 <6>[ 4.403348] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10793 23:11:11.145933 <6>[ 4.404982] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10794 23:11:11.152865 <6>[ 4.405000] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10795 23:11:11.162432 <6>[ 4.405006] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10796 23:11:11.168918 <6>[ 4.405013] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10797 23:11:11.179434 <6>[ 4.405019] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10798 23:11:11.185770 <6>[ 4.405025] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10799 23:11:11.195804 <6>[ 4.405032] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10800 23:11:11.202117 <6>[ 4.405038] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10801 23:11:11.212376 <6>[ 4.405044] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10802 23:11:11.218893 <6>[ 4.405051] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10803 23:11:11.229058 <6>[ 4.405057] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10804 23:11:11.235928 <6>[ 4.405063] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10805 23:11:11.245513 <6>[ 4.405070] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10806 23:11:11.255734 <6>[ 4.405076] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10807 23:11:11.262328 <6>[ 4.405083] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10808 23:11:11.269055 <6>[ 4.405701] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10809 23:11:11.275165 <6>[ 4.406553] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10810 23:11:11.282472 <6>[ 4.407095] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10811 23:11:11.289044 <6>[ 4.407706] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10812 23:11:11.295426 <6>[ 4.408341] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10813 23:11:11.305011 <6>[ 4.408532] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10814 23:11:11.311899 <6>[ 4.408546] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10815 23:11:11.321853 <6>[ 4.408555] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10816 23:11:11.331721 <6>[ 4.408560] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10817 23:11:11.341668 <6>[ 4.408566] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10818 23:11:11.351633 <6>[ 4.408572] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10819 23:11:11.361547 <6>[ 4.408577] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10820 23:11:11.368306 <6>[ 4.408582] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10821 23:11:11.378174 <6>[ 4.408587] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10822 23:11:11.387988 <6>[ 4.408593] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10823 23:11:11.397890 <6>[ 4.408598] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10824 23:11:11.407787 <6>[ 4.409135] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10825 23:11:11.414101 <6>[ 4.817552] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10826 23:11:11.417646 <6>[ 4.969363] hub 1-1:1.0: USB hub found
10827 23:11:11.421059 <6>[ 4.969733] hub 1-1:1.0: 4 ports detected
10828 23:11:11.427428 <6>[ 4.972862] hub 1-1:1.0: USB hub found
10829 23:11:11.430959 <6>[ 4.973119] hub 1-1:1.0: 4 ports detected
10830 23:11:11.467860 <6>[ 5.093652] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10831 23:11:11.488169 <6>[ 5.118679] hub 2-1:1.0: USB hub found
10832 23:11:11.491582 <6>[ 5.119107] hub 2-1:1.0: 3 ports detected
10833 23:11:11.494942 <6>[ 5.122302] hub 2-1:1.0: USB hub found
10834 23:11:11.498434 <6>[ 5.122689] hub 2-1:1.0: 3 ports detected
10835 23:11:11.659662 <6>[ 5.285650] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10836 23:11:11.784283 <6>[ 5.413559] hub 1-1.4:1.0: USB hub found
10837 23:11:11.787654 <6>[ 5.414010] hub 1-1.4:1.0: 2 ports detected
10838 23:11:11.790975 <6>[ 5.418215] hub 1-1.4:1.0: USB hub found
10839 23:11:11.797486 <6>[ 5.418594] hub 1-1.4:1.0: 2 ports detected
10840 23:11:11.863496 <6>[ 5.489878] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10841 23:11:12.079532 <6>[ 5.705634] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10842 23:11:12.263859 <6>[ 5.889723] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10843 23:11:23.071802 <6>[ 16.706583] ALSA device list:
10844 23:11:23.079019 <6>[ 16.706604] No soundcards found.
10845 23:11:23.082264 <6>[ 16.710948] Freeing unused kernel memory: 8448K
10846 23:11:23.085004 <6>[ 16.711116] Run /init as init process
10847 23:11:23.122923 <6>[ 16.754145] NET: Registered PF_INET6 protocol family
10848 23:11:23.126535 <6>[ 16.755210] Segment Routing with IPv6
10849 23:11:23.132952 <6>[ 16.755228] In-situ OAM (IOAM) with IPv6
10850 23:11:23.133072
10851 23:11:23.156403 Welcome to [1<30>[ 16.771137] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10852 23:11:23.163012 <30>[ 16.771741] systemd[1]: Detected architecture arm64.
10853 23:11:23.165988 mDebian GNU/Linux 11 (bullseye)[0m!
10854 23:11:23.166084
10855 23:11:23.183009 <30>[ 16.813823] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10856 23:11:23.330573 <30>[ 16.958174] systemd[1]: Queued start job for default target Graphical Interface.
10857 23:11:23.359474 [[0;32m OK [0m] Created slice [0;1;39msyste<30>[ 16.990413] systemd[1]: Created slice system-getty.slice.
10858 23:11:23.362736 m-getty.slice[0m.
10859 23:11:23.386385 [[0;32m OK [0m] Created slice [0;1;39msyste<30>[ 17.014103] systemd[1]: Created slice system-modprobe.slice.
10860 23:11:23.386490 m-modprobe.slice[0m.
10861 23:11:23.408223 [[0;32m OK [0m] Created slic<30>[ 17.039125] systemd[1]: Created slice system-serial\x2dgetty.slice.
10862 23:11:23.414908 e [0;1;39msystem-serial\x2dgetty.slice[0m.
10863 23:11:23.434562 [[0;32m OK [0m] Created slice [0;1;39mUser <30>[ 17.062376] systemd[1]: Created slice User and Session Slice.
10864 23:11:23.434650 and Session Slice[0m.
10865 23:11:23.459207 [[0;32m OK [0m] Started [0;1;39mDispatch Pa<30>[ 17.086410] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10866 23:11:23.462247 ssword …ts to Console Directory Watch[0m.
10867 23:11:23.486732 [[0;32m OK [0m] Started [0;1;39mForward Pas<30>[ 17.114392] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10868 23:11:23.490237 sword R…uests to Wall Directory Watch[0m.
10869 23:11:23.518134 [[0;32m OK [0m] Reached target [0;1;39mLoca<30>[ 17.142114] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10870 23:11:23.525016 <30>[ 17.142351] systemd[1]: Reached target Local Encrypted Volumes.
10871 23:11:23.527945 l Encrypted Volumes[0m.
10872 23:11:23.547511 [[0;32m OK [0m] Reached target [0;1;39mPath<30>[ 17.178118] systemd[1]: Reached target Paths.
10873 23:11:23.547596 s[0m.
10874 23:11:23.569740 [[0;32m OK [0m] Reached target [0;1;39mRemo<30>[ 17.197649] systemd[1]: Reached target Remote File Systems.
10875 23:11:23.569833 te File Systems[0m.
10876 23:11:23.591041 [[0;32m OK [0m] Reached target [0;1;39mSlic<30>[ 17.222011] systemd[1]: Reached target Slices.
10877 23:11:23.591132 es[0m.
10878 23:11:23.610488 [[0;32m OK [0m] Reached target [0;1;39mSwap<30>[ 17.241658] systemd[1]: Reached target Swap.
10879 23:11:23.610581 [0m.
10880 23:11:23.634142 [[0;32m OK [0m] Listening on [0;1;39minitct<30>[ 17.262078] systemd[1]: Listening on initctl Compatibility Named Pipe.
10881 23:11:23.637762 l Compatibility Named Pipe[0m.
10882 23:11:23.644183 <30>[ 17.277218] systemd[1]: Listening on Journal Audit Socket.
10883 23:11:23.650634 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10884 23:11:23.668078 [[0;32m OK [0m] Listening on<30>[ 17.298801] systemd[1]: Listening on Journal Socket (/dev/log).
10885 23:11:23.671033 [0;1;39mJournal Socket (/dev/log)[0m.
10886 23:11:23.691976 [[0;32m OK [0m] Listening on<30>[ 17.322817] systemd[1]: Listening on Journal Socket.
10887 23:11:23.695133 [0;1;39mJournal Socket[0m.
10888 23:11:23.711172 [[0;32m OK [0m] Listening on [0;1;39mudev C<30>[ 17.342221] systemd[1]: Listening on udev Control Socket.
10889 23:11:23.714635 ontrol Socket[0m.
10890 23:11:23.735754 [[0;32m OK [0m] Listening on<30>[ 17.366683] systemd[1]: Listening on udev Kernel Socket.
10891 23:11:23.739180 [0;1;39mudev Kernel Socket[0m.
10892 23:11:23.795354 Mounting [0;1;39mHuge Pages File Syste<30>[ 17.425984] systemd[1]: Mounting Huge Pages File System...
10893 23:11:23.798305 m[0m...
10894 23:11:23.816450 Mounting [0;1;39mPOSIX<30>[ 17.447545] systemd[1]: Mounting POSIX Message Queue File System...
10895 23:11:23.819988 Message Queue File System[0m...
10896 23:11:23.841490 Mountin<30>[ 17.472130] systemd[1]: Mounting Kernel Debug File System...
10897 23:11:23.844290 g [0;1;39mKernel Debug File System[0m...
10898 23:11:23.868940 Startin<30>[ 17.493881] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10899 23:11:23.875395 <30>[ 17.496490] systemd[1]: Starting Create list of static device nodes for the current kernel...
10900 23:11:23.882382 g [0;1;39mCreate list of st…odes for the current kernel[0m...
10901 23:11:23.907573 Starting [0;1;39mLoad <30>[ 17.538422] systemd[1]: Starting Load Kernel Module configfs...
10902 23:11:23.910890 Kernel Module configfs[0m...
10903 23:11:23.938873 Starting [0;1;39mLoad Kernel Module dr<30>[ 17.566266] systemd[1]: Starting Load Kernel Module drm...
10904 23:11:23.938982 m[0m...
10905 23:11:23.958388 <30>[ 17.586099] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10906 23:11:23.972062 Starting [0;1;39mJourn<30>[ 17.602892] systemd[1]: Starting Journal Service...
10907 23:11:23.972151 al Service[0m...
10908 23:11:23.995755 Starting [0;1;39mLoad <30>[ 17.626656] systemd[1]: Starting Load Kernel Modules...
10909 23:11:23.998887 Kernel Modules[0m...
10910 23:11:24.022512 Starting [0;1;39mRemount Root and Kern<30>[ 17.650101] systemd[1]: Starting Remount Root and Kernel File Systems...
10911 23:11:24.026191 el File Systems[0m...
10912 23:11:24.051149 Starting [0;1;39mColdplug All udev Dev<30>[ 17.678342] systemd[1]: Starting Coldplug All udev Devices...
10913 23:11:24.051237 ices[0m...
10914 23:11:24.069875 [[0;32m OK [<30>[ 17.703947] systemd[1]: Started Journal Service.
10915 23:11:24.076459 0m] Started [0;1;39mJournal Service[0m.
10916 23:11:24.095185 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10917 23:11:24.112232 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10918 23:11:24.129117 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10919 23:11:24.147448 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10920 23:11:24.166214 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10921 23:11:24.186409 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10922 23:11:24.205011 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10923 23:11:24.225094 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10924 23:11:24.239551 See 'systemctl status systemd-remount-fs.service' for details.
10925 23:11:24.289443 Mounting [0;1;39mKernel Configuration File System[0m...
10926 23:11:24.315546 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10927 23:11:24.342487 <46>[ 17.959953] systemd-journald[189]: Received client request to flush runtime journal.
10928 23:11:24.348706 Starting [0;1;39mLoad/Save Random Seed[0m...
10929 23:11:24.369241 Starting [0;1;39mApply Kernel Variables[0m...
10930 23:11:24.393020 Starting [0;1;39mCreate System Users[0m...
10931 23:11:24.412376 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10932 23:11:24.432499 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10933 23:11:24.452277 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10934 23:11:24.468851 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10935 23:11:24.485282 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10936 23:11:24.501023 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10937 23:11:24.556299 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10938 23:11:24.579407 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10939 23:11:24.591696 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10940 23:11:24.607100 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10941 23:11:24.639359 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10942 23:11:24.666794 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10943 23:11:24.687582 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10944 23:11:24.712104 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10945 23:11:24.773310 Starting [0;1;39mNetwork Time Synchronization[0m...
10946 23:11:24.794555 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10947 23:11:24.841213 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronizatio<6>[ 18.473201] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10948 23:11:24.844377 n[0m.
10949 23:11:24.848135 <6>[ 18.478739] remoteproc remoteproc0: scp is available
10950 23:11:24.854577 <6>[ 18.478955] remoteproc remoteproc0: powering up scp
10951 23:11:24.864467 <6>[ 18.478968] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10952 23:11:24.867406 <6>[ 18.479014] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10953 23:11:24.875020 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10954 23:11:24.886649 <6>[ 18.520364] mc: Linux media interface: v0.10
10955 23:11:24.900034 [[0;32m OK [0m] Reached target [0;1;39mSyst<6>[ 18.526874] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10956 23:11:24.910441 em Time Synchron<6>[ 18.526915] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10957 23:11:24.910542 ized[0m.
10958 23:11:24.920144 <6>[ 18.526925] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10959 23:11:24.923039 <6>[ 18.550157] videodev: Linux video capture interface: v2.00
10960 23:11:24.937246 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10961 23:11:24.947309 <3>[ 18.573556] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10962 23:11:24.954148 <3>[ 18.573578] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10963 23:11:24.960616 <3>[ 18.573583] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10964 23:11:24.970244 <6>[ 18.575379] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10965 23:11:24.976950 <3>[ 18.604172] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10966 23:11:24.990315 [[0;32m OK [0m] Found device [0;1;39m/dev/t<3>[ 18.604196] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10967 23:11:24.990453 tyS0[0m.
10968 23:11:25.000777 <3>[ 18.604207] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10969 23:11:25.007395 <3>[ 18.604217] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10970 23:11:25.017482 <3>[ 18.604234] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10971 23:11:25.023768 [[0;32m OK [<6>[ 18.604653] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10972 23:11:25.033824 0m] Created slic<6>[ 18.604729] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10973 23:11:25.040572 <6>[ 18.604741] remoteproc remoteproc0: remote processor scp is now up
10974 23:11:25.050218 e [0;1;39msyste<4>[ 18.606107] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10975 23:11:25.056782 <4>[ 18.606224] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10976 23:11:25.067971 m-systemd\x2dbac<3>[ 18.609668] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10977 23:11:25.074788 <3>[ 18.609772] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10978 23:11:25.081887 <3>[ 18.609781] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10979 23:11:25.091436 <3>[ 18.609789] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10980 23:11:25.101252 klight.slice[0m<3>[ 18.609860] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10981 23:11:25.101392 .
10982 23:11:25.108206 <3>[ 18.609869] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10983 23:11:25.118255 <3>[ 18.609875] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10984 23:11:25.124666 <3>[ 18.609883] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10985 23:11:25.131089 <3>[ 18.609890] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10986 23:11:25.141150 <3>[ 18.609936] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10987 23:11:25.147753 <6>[ 18.618003] usbcore: registered new interface driver r8152
10988 23:11:25.154591 <4>[ 18.619489] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10989 23:11:25.161234 <4>[ 18.619489] Fallback method does not support PEC.
10990 23:11:25.168261 <3>[ 18.639071] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10991 23:11:25.175535 <6>[ 18.648420] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10992 23:11:25.182217 <6>[ 18.648437] pci_bus 0000:00: root bus resource [bus 00-ff]
10993 23:11:25.189387 <6>[ 18.648445] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10994 23:11:25.199370 <6>[ 18.648448] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10995 23:11:25.206775 <6>[ 18.648516] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10996 23:11:25.213198 <6>[ 18.648536] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10997 23:11:25.216856 <6>[ 18.648617] pci 0000:00:00.0: supports D1 D2
10998 23:11:25.223098 <6>[ 18.648619] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10999 23:11:25.230708 <6>[ 18.650466] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
11000 23:11:25.240771 Startin<6>[ 18.650581] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
11001 23:11:25.247401 g [0;1;39mLoad/<6>[ 18.650607] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
11002 23:11:25.257909 Save Screen …o<6>[ 18.650625] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
11003 23:11:25.264534 <6>[ 18.650639] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
11004 23:11:25.271181 f leds:white:kbd<6>[ 18.650748] pci 0000:01:00.0: supports D1 D2
11005 23:11:25.278163 _backlight[0m..<6>[ 18.650751] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11006 23:11:25.278343 .
11007 23:11:25.285456 <6>[ 18.674333] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
11008 23:11:25.295260 <6>[ 18.674605] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
11009 23:11:25.302446 <6>[ 18.674621] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
11010 23:11:25.315674 [[0;32m OK [0m] Finished [0;1;39mLoad/Save <6>[ 18.674645] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
11011 23:11:25.322538 Screen …s of l<6>[ 18.674663] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
11012 23:11:25.332995 eds:white:kbd_ba<6>[ 18.674680] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
11013 23:11:25.333108 cklight[0m.
11014 23:11:25.340042 <6>[ 18.674700] pci 0000:00:00.0: PCI bridge to [bus 01]
11015 23:11:25.346487 <6>[ 18.674719] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
11016 23:11:25.353445 <6>[ 18.674943] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
11017 23:11:25.360088 <6>[ 18.677133] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
11018 23:11:25.367163 <6>[ 18.677622] pcieport 0000:00:00.0: AER: enabled with IRQ 282
11019 23:11:25.377451 <6>[ 18.689145] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
11020 23:11:25.384400 <6>[ 18.690569] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
11021 23:11:25.394537 <3>[ 18.709731] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11022 23:11:25.401124 <3>[ 18.710582] power_supply sbs-5-000b: driver failed to report `temp' property: -6
11023 23:11:25.407476 <6>[ 18.718006] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
11024 23:11:25.420792 [[0;32m OK [<6>[ 18.720671] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
11025 23:11:25.427249 <5>[ 18.755244] cfg80211: Loading compiled-in X.509 certificates for regulatory database
11026 23:11:25.434091 <6>[ 18.756621] usbcore: registered new interface driver cdc_ether
11027 23:11:25.440615 <6>[ 18.758445] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
11028 23:11:25.450797 <4>[ 18.759794] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
11029 23:11:25.457187 <4>[ 18.759805] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
11030 23:11:25.467436 <6>[ 18.763024] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
11031 23:11:25.473692 <6>[ 18.772953] usbcore: registered new interface driver r8153_ecm
11032 23:11:25.480648 <6>[ 18.780923] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
11033 23:11:25.493792 <6>[ 18.784086] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
11034 23:11:25.500439 <5>[ 18.784417] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
11035 23:11:25.507039 <4>[ 18.784593] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
11036 23:11:25.513487 <6>[ 18.784609] cfg80211: failed to load regulatory.db
11037 23:11:25.520422 <6>[ 18.784758] usbcore: registered new interface driver uvcvideo
11038 23:11:25.523482 <6>[ 18.800938] Bluetooth: Core ver 2.22
11039 23:11:25.530039 <6>[ 18.801104] NET: Registered PF_BLUETOOTH protocol family
11040 23:11:25.536878 <6>[ 18.801110] Bluetooth: HCI device and connection manager initialized
11041 23:11:25.540011 <6>[ 18.801140] Bluetooth: HCI socket layer initialized
11042 23:11:25.546454 <6>[ 18.801155] Bluetooth: L2CAP socket layer initialized
11043 23:11:25.549855 <6>[ 18.801175] Bluetooth: SCO socket layer initialized
11044 23:11:25.556696 <6>[ 18.821483] r8152 2-1.3:1.0 eth0: v1.12.13
11045 23:11:25.563688 <3>[ 18.821869] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
11046 23:11:25.570036 <6>[ 18.823569] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
11047 23:11:25.579997 <3>[ 18.824105] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11048 23:11:25.586257 <3>[ 18.824909] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11049 23:11:25.593224 <6>[ 18.831997] r8152 2-1.3:1.0 enx00e04c787aaa: renamed from eth0
11050 23:11:25.602926 <3>[ 18.845732] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11051 23:11:25.609293 <6>[ 18.864171] usbcore: registered new interface driver btusb
11052 23:11:25.619753 <4>[ 18.865411] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
11053 23:11:25.626061 <3>[ 18.865436] Bluetooth: hci0: Failed to load firmware file (-2)
11054 23:11:25.629581 <3>[ 18.865440] Bluetooth: hci0: Failed to set up firmware (-2)
11055 23:11:25.642582 <4>[ 18.865446] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
11056 23:11:25.649030 <3>[ 18.869607] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11057 23:11:25.659264 <6>[ 18.891415] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
11058 23:11:25.662559 <6>[ 18.891519] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
11059 23:11:25.672589 <3>[ 18.892024] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11060 23:11:25.678929 <6>[ 18.910456] mt7921e 0000:01:00.0: ASIC revision: 79610010
11061 23:11:25.685413 <3>[ 18.921711] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11062 23:11:25.699061 <4>[ 19.004085] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11063 23:11:25.708636 <4>[ 19.111147] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11064 23:11:25.722203 <4>[ 19.214882] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11065 23:11:25.732144 <4>[ 19.319033] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11066 23:11:25.735442 0m] Reached target [0;1;39mBluetooth[0m.
11067 23:11:25.751206 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
11068 23:11:25.775092 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
11069 23:11:25.798166 [[0;32m OK [0m] Started [0;1;39mDaily Clean<4>[ 19.423551] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11070 23:11:25.800874 up of Temporary Directories[0m.
11071 23:11:25.815161 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
11072 23:11:25.834840 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
11073 23:11:25.851021 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
11074 23:11:25.871209 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
11075 23:11:25.893291 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
11076 23:11:25.906162 <4>[ 19.532164] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11077 23:11:25.952391 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
11078 23:11:25.990264 Starting [0;1;39mUser Login Management[0m...
11079 23:11:26.013509 <4>[ 19.640659] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11080 23:11:26.020060 Starting [0;1;39mPermit User Sessions[0m...
11081 23:11:26.037888 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
11082 23:11:26.125173 <4>[ 19.752348] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11083 23:11:26.134128 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
11084 23:11:26.150014 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
11085 23:11:26.167392 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
11086 23:11:26.189655 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
11087 23:11:26.218633 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
11088 23:11:26.233115 <4>[ 19.860285] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11089 23:11:26.241387 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
11090 23:11:26.260910 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
11091 23:11:26.276161 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11092 23:11:26.329193 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11093 23:11:26.345201 <4>[ 19.973182] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11094 23:11:26.372003 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11095 23:11:26.388736
11096 23:11:26.388870
11097 23:11:26.392174 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11098 23:11:26.392254
11099 23:11:26.395135 debian-bullseye-arm64 login: root (automatic login)
11100 23:11:26.395220
11101 23:11:26.395302
11102 23:11:26.411909 Linux debian-bullseye-arm64 6.1.64-cip10-rt5 #1 SMP PREEMPT Sun Dec 3 22:38:18 UTC 2023 aarch64
11103 23:11:26.412010
11104 23:11:26.418796 The programs included with the Debian GNU/Linux system are free software;
11105 23:11:26.425268 the exact distribution terms for each program are described in the
11106 23:11:26.428659 individual files in /usr/share/doc/*/copyright.
11107 23:11:26.428771
11108 23:11:26.435517 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11109 23:11:26.438334 permitted by applicable law.
11110 23:11:26.438703 Matched prompt #10: / #
11112 23:11:26.438922 Setting prompt string to ['/ #']
11113 23:11:26.439022 end: 2.2.5.1 login-action (duration 00:00:21) [common]
11115 23:11:26.439232 end: 2.2.5 auto-login-action (duration 00:00:21) [common]
11116 23:11:26.439321 start: 2.2.6 expect-shell-connection (timeout 00:02:49) [common]
11117 23:11:26.439404 Setting prompt string to ['/ #']
11118 23:11:26.439469 Forcing a shell prompt, looking for ['/ #']
11120 23:11:26.489675 / #
11121 23:11:26.489825 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11122 23:11:26.489920 Waiting using forced prompt support (timeout 00:02:30)
11123 23:11:26.490023 <3>[ 20.078188] mt7921e 0000:01:00.0: hardware init failed
11124 23:11:26.494518
11125 23:11:26.494830 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11126 23:11:26.494922 start: 2.2.7 export-device-env (timeout 00:02:49) [common]
11127 23:11:26.495016 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11128 23:11:26.495101 end: 2.2 depthcharge-retry (duration 00:02:11) [common]
11129 23:11:26.495189 end: 2 depthcharge-action (duration 00:02:11) [common]
11130 23:11:26.495274 start: 3 lava-test-retry (timeout 00:05:00) [common]
11131 23:11:26.495357 start: 3.1 lava-test-shell (timeout 00:05:00) [common]
11132 23:11:26.495428 Using namespace: common
11134 23:11:26.595816 / # #
11135 23:11:26.595976 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:05:00)
11136 23:11:26.601289 #
11137 23:11:26.601562 Using /lava-12172398
11139 23:11:26.701970 / # export SHELL=/bin/sh
11140 23:11:26.707409 export SHELL=/bin/sh
11142 23:11:26.807938 / # . /lava-12172398/environment
11143 23:11:26.813486 . /lava-12172398/environment
11145 23:11:26.914055 / # /lava-12172398/bin/lava-test-runner /lava-12172398/0
11146 23:11:26.914208 Test shell timeout: 10s (minimum of the action and connection timeout)
11147 23:11:26.918952 /lava-12172398/bin/lava-test-runner /lava-12172398/0
11148 23:11:26.937818 + export TESTRUN_ID=0_sleep
11149 23:11:26.940997 + cd /lava-12172398/0/tests/0_sleep
11150 23:11:26.944212 + cat uuid
11151 23:11:26.944308 + UUID=12172398_1.5.2.3.1
11152 23:11:26.944374 + set +x
11153 23:11:26.950910 <LAVA_SIGNAL_STARTRUN 0_sleep 12172398_1.5.2.3.1>
11154 23:11:26.951166 Received signal: <STARTRUN> 0_sleep 12172398_1.5.2.3.1
11155 23:11:26.951242 Starting test lava.0_sleep (12172398_1.5.2.3.1)
11156 23:11:26.951325 Skipping test definition patterns.
11157 23:11:26.954528 + ./config/lava/sleep/sleep.sh mem freeze
11158 23:11:26.957515 Received signal: <TESTCASE> TEST_CASE_ID=rtc-exist RESULT=pass
11160 23:11:26.961020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc-exist RESULT=pass>
11161 23:11:26.964583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc-wakeup-enabled RESULT=pass>
11162 23:11:26.964836 Received signal: <TESTCASE> TEST_CASE_ID=rtc-wakeup-enabled RESULT=pass
11164 23:11:26.967286 rtcwake: assuming RTC uses UTC ...
11165 23:11:26.974321 rtcwake: wakeup from "mem" using rtc0 at Sun Dec 3 23:09:19 2023
11166 23:11:26.977207 <6>[ 20.610564] PM: suspend entry (deep)
11167 23:11:26.984334 <6>[ 20.610637] Filesystems sync: 0.000 seconds
11168 23:11:26.987259 <6>[ 20.613586] Freezing user space processes
11169 23:11:27.001850 <6>[ 20.629765] Freezing user space processes completed (elapsed 0.016 seconds)
11170 23:11:27.005325 <6>[ 20.629781] OOM killer disabled.
11171 23:11:27.008899 <6>[ 20.629784] Freezing remaining freezable tasks
11172 23:11:27.015460 <6>[ 20.631110] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11173 23:11:27.025315 <6>[ 20.631120] printk: Suspending console(s) (use no_console_suspend to debug)
11174 23:11:30.402387 <3>[ 23.809769] mt7921e 0000:01:00.0: Message 00020007 (seq 6) timeout
11175 23:11:30.412117 <3>[ 23.809806] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11176 23:11:30.422526 <3>[ 23.809851] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11177 23:11:30.428790 <3>[ 23.809892] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11178 23:11:30.435567 <3>[ 23.810199] PM: Some devices failed to suspend, or early wake event detected
11179 23:11:30.442269 <4>[ 23.825573] typec port0-partner: PM: parent port0 should not be sleeping
11180 23:11:30.510058 <6>[ 24.141757] OOM killer enabled.
11181 23:11:30.513879 rtcwake: write error
11182 23:11:30.517434 <6>[ 24.141769] Restarting tasks ... done.
11183 23:11:30.524191 <LAVA_SIGNAL_TES<5>[ 24.151582] random: crng reseeded on system resumption
11184 23:11:30.527586 Received signal: <TES<5>[> 24.151582] random: crng reseeded on system resumption
TCASE TEST_CASE_<6
11185 23:11:30.530916 TCASE TEST_CASE_<6>[ 24.152518] PM: suspend exit
11186 23:11:30.530993 ID=rtcwake-mem-1 RESULT=fail>
11187 23:11:30.534111 rtcwake: assuming RTC uses UTC ...
11188 23:11:30.540877 rtcwake: wakeup from "mem" using rtc0 at Sun Dec 3 23:09:22 2023
11189 23:11:30.558069 <6>[ 24.190143] PM: suspend entry (deep)
11190 23:11:30.561763 <6>[ 24.190185] Filesystems sync: 0.000 seconds
11191 23:11:30.564589 <6>[ 24.190716] Freezing user space processes
11192 23:11:30.571117 <6>[ 24.192357] Freezing user space processes completed (elapsed 0.001 seconds)
11193 23:11:30.578310 <6>[ 24.192364] OOM killer disabled.
11194 23:11:30.581320 <6>[ 24.192366] Freezing remaining freezable tasks
11195 23:11:30.587957 <6>[ 24.193389] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11196 23:11:30.594383 <6>[ 24.193393] printk: Suspending console(s) (use no_console_suspend to debug)
11197 23:11:33.990295 <3>[ 27.393692] mt7921e 0000:01:00.0: Message 00020007 (seq 7) timeout
11198 23:11:34.000196 <3>[ 27.393722] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11199 23:11:34.010018 <3>[ 27.393766] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11200 23:11:34.016554 <3>[ 27.393810] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11201 23:11:34.023328 <3>[ 27.394540] PM: Some devices failed to suspend, or early wake event detected
11202 23:11:34.097345 rtcwake: <6>[ 27.729707] OOM killer enabled.
11203 23:11:34.097517 write error
11204 23:11:34.100742 <6>[ 27.729717] Restarting tasks ... done.
11205 23:11:34.107152 <5>[ 27.731982] random: crng reseeded on system resumption
11206 23:11:34.110790 <6>[ 27.732796] PM: suspend exit
11207 23:11:34.117652 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-2 RESULT=fail>
11208 23:11:34.117950 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-2 RESULT=fail
11210 23:11:34.120681 rtcwake: assuming RTC uses UTC ...
11211 23:11:34.124132 rtcwake: wakeup from "mem" using rtc0 at Sun Dec 3 23:09:26 2023
11212 23:11:34.141850 <6>[ 27.774121] PM: suspend entry (deep)
11213 23:11:34.144983 <6>[ 27.774170] Filesystems sync: 0.000 seconds
11214 23:11:34.148548 <6>[ 27.774701] Freezing user space processes
11215 23:11:34.154964 <6>[ 27.776364] Freezing user space processes completed (elapsed 0.001 seconds)
11216 23:11:34.158137 <6>[ 27.776370] OOM killer disabled.
11217 23:11:34.165133 <6>[ 27.776371] Freezing remaining freezable tasks
11218 23:11:34.171606 <6>[ 27.777481] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11219 23:11:34.178407 <6>[ 27.777488] printk: Suspending console(s) (use no_console_suspend to debug)
11220 23:11:37.569298 <3>[ 30.977651] mt7921e 0000:01:00.0: Message 00020007 (seq 8) timeout
11221 23:11:37.579499 <3>[ 30.977678] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11222 23:11:37.589818 <3>[ 30.977717] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11223 23:11:37.596106 <3>[ 30.977752] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11224 23:11:37.602682 <3>[ 30.978029] PM: Some devices failed to suspend, or early wake event detected
11225 23:11:37.677355 <6>[ 31.309736] OOM killer enabled.
11226 23:11:37.680686 <6>[ 31.309748] Restarting tasks ... done.
11227 23:11:37.684185 rtcwake: write error
11228 23:11:37.690752 <5>[ 31.312670] random: crng reseeded on system resumption
11229 23:11:37.693680 <LAVA_SIGNAL_TES<6>[ 31.321437] PM: suspend exit
11230 23:11:37.697241 TCASE TEST_CASE_ID=rtcwake-mem-3 RESULT=fail>
11231 23:11:37.697496 Received signal: <TES<6>[> 31.321437] PM: suspend exit
TCASE TEST_CASE_ID=rtcwake-mem-3 RESULT=fail
11232 23:11:37.700700 rtcwake: assuming RTC uses UTC ...
11233 23:11:37.707296 rtcwake: wakeup from "mem" using rtc0 at Sun Dec 3 23:09:29 2023
11234 23:11:37.721329 <6>[ 31.356808] PM: suspend entry (deep)
11235 23:11:37.724561 <6>[ 31.356853] Filesystems sync: 0.000 seconds
11236 23:11:37.728121 <6>[ 31.357469] Freezing user space processes
11237 23:11:37.734930 <6>[ 31.361532] Freezing user space processes completed (elapsed 0.004 seconds)
11238 23:11:37.741385 <6>[ 31.361550] OOM killer disabled.
11239 23:11:37.744830 <6>[ 31.361553] Freezing remaining freezable tasks
11240 23:11:37.751096 <6>[ 31.362964] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11241 23:11:37.758220 <6>[ 31.362974] printk: Suspending console(s) (use no_console_suspend to debug)
11242 23:11:41.152881 <3>[ 34.561712] mt7921e 0000:01:00.0: Message 00020007 (seq 9) timeout
11243 23:11:41.163031 <3>[ 34.561741] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11244 23:11:41.173262 <3>[ 34.561786] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11245 23:11:41.180283 <3>[ 34.561827] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11246 23:11:41.186650 <3>[ 34.562125] PM: Some devices failed to suspend, or early wake event detected
11247 23:11:41.260852 rtcwake: <6>[ 34.893720] OOM killer enabled.
11248 23:11:41.260974 write error
11249 23:11:41.264437 <6>[ 34.893731] Restarting tasks ... done.
11250 23:11:41.270873 <5>[ 34.896005] random: crng reseeded on system resumption
11251 23:11:41.274234 <6>[ 34.897129] PM: suspend exit
11252 23:11:41.280882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-4 RESULT=fail>
11253 23:11:41.281148 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-4 RESULT=fail
11255 23:11:41.284630 rtcwake: assuming RTC uses UTC ...
11256 23:11:41.287478 rtcwake: wakeup from "mem" using rtc0 at Sun Dec 3 23:09:33 2023
11257 23:11:41.305084 <6>[ 34.938931] PM: suspend entry (deep)
11258 23:11:41.308025 <6>[ 34.938977] Filesystems sync: 0.000 seconds
11259 23:11:41.311532 <6>[ 34.939518] Freezing user space processes
11260 23:11:41.318652 <6>[ 34.941261] Freezing user space processes completed (elapsed 0.001 seconds)
11261 23:11:41.321481 <6>[ 34.941272] OOM killer disabled.
11262 23:11:41.328019 <6>[ 34.941274] Freezing remaining freezable tasks
11263 23:11:41.334828 <6>[ 34.942761] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11264 23:11:41.341412 <6>[ 34.942770] printk: Suspending console(s) (use no_console_suspend to debug)
11265 23:11:44.736453 <3>[ 38.145655] mt7921e 0000:01:00.0: Message 00020007 (seq 10) timeout
11266 23:11:44.746721 <3>[ 38.145692] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11267 23:11:44.756782 <3>[ 38.145729] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11268 23:11:44.763558 <3>[ 38.145765] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11269 23:11:44.769782 <3>[ 38.146034] PM: Some devices failed to suspend, or early wake event detected
11270 23:11:44.844049 rtcwake: <6>[ 38.477730] OOM killer enabled.
11271 23:11:44.847791 <6>[ 38.477742] Restarting tasks ... done.
11272 23:11:44.847882 write error
11273 23:11:44.854052 <LA<5>[ 38.479981] random: crng reseeded on system resumption
11274 23:11:44.857252 <6>[ 38.480818] PM: suspend exit
11275 23:11:44.864358 VA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-5 RESULT=fail>
11276 23:11:44.864441 rtcwake: assuming RTC uses UTC ...
11277 23:11:44.870649 rtcwake: wakeup from "mem" using rtc0 at Sun Dec 3 23:09:37 2023
11278 23:11:44.884929 <6>[ 38.519417] PM: suspend entry (deep)
11279 23:11:44.887811 <6>[ 38.519458] Filesystems sync: 0.000 seconds
11280 23:11:44.891406 <6>[ 38.520000] Freezing user space processes
11281 23:11:44.897732 <6>[ 38.521607] Freezing user space processes completed (elapsed 0.001 seconds)
11282 23:11:44.901386 <6>[ 38.521614] OOM killer disabled.
11283 23:11:44.907950 <6>[ 38.521616] Freezing remaining freezable tasks
11284 23:11:44.914954 <6>[ 38.523056] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11285 23:11:44.921277 <6>[ 38.523067] printk: Suspending console(s) (use no_console_suspend to debug)
11286 23:11:48.320051 <3>[ 41.729661] mt7921e 0000:01:00.0: Message 00020007 (seq 11) timeout
11287 23:11:48.330581 <3>[ 41.729691] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11288 23:11:48.340397 <3>[ 41.729735] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11289 23:11:48.347124 <3>[ 41.729776] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11290 23:11:48.353558 <3>[ 41.730079] PM: Some devices failed to suspend, or early wake event detected
11291 23:11:48.428286 <6>[ 42.061728] OOM killer enabled.
11292 23:11:48.431856 rtcwake: <6>[ 42.061740] Restarting tasks ... done.
11293 23:11:48.438339 <5>[ 42.063837] random: crng reseeded on system resumption
11294 23:11:48.441507 <6>[ 42.068925] PM: suspend exit
11295 23:11:48.441598 write error
11296 23:11:48.448429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-6 RESULT=fail>
11297 23:11:48.448512 rtcwake: assuming RTC uses UTC ...
11298 23:11:48.448754 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-6 RESULT=fail
11300 23:11:48.455063 rtcwake: wakeup from "mem" using rtc0 at Sun Dec 3 23:09:40 2023
11301 23:11:48.468387 <6>[ 42.103705] PM: suspend entry (deep)
11302 23:11:48.471915 <6>[ 42.103749] Filesystems sync: 0.000 seconds
11303 23:11:48.475000 <6>[ 42.104288] Freezing user space processes
11304 23:11:48.481692 <6>[ 42.105528] Freezing user space processes completed (elapsed 0.001 seconds)
11305 23:11:48.484607 <6>[ 42.105534] OOM killer disabled.
11306 23:11:48.491634 <6>[ 42.105535] Freezing remaining freezable tasks
11307 23:11:48.498068 <6>[ 42.106955] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11308 23:11:48.504972 <6>[ 42.106964] printk: Suspending console(s) (use no_console_suspend to debug)
11309 23:11:51.904177 <3>[ 45.313675] mt7921e 0000:01:00.0: Message 00020007 (seq 12) timeout
11310 23:11:51.914186 <3>[ 45.313708] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11311 23:11:51.924243 <3>[ 45.313744] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11312 23:11:51.930760 <3>[ 45.313777] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11313 23:11:51.940753 <3>[ 45.313953] PM: Some devices failed to suspend, or early wake event detected
11314 23:11:52.013298 <6>[ 45.645762] OOM killer enabled.
11315 23:11:52.015724 rtcwake: <6>[ 45.645774] Restarting tasks ... done.
11316 23:11:52.022922 write error<5>[ 45.647766] random: crng reseeded on system resumption
11317 23:11:52.023469
11318 23:11:52.025882 <6>[ 45.653382] PM: suspend exit
11319 23:11:52.032974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-7 RESULT=fail>
11320 23:11:52.033808 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-7 RESULT=fail
11322 23:11:52.036282 rtcwake: assuming RTC uses UTC ...
11323 23:11:52.042807 rtcwake: wakeup from "mem" using rtc0 at Sun Dec 3 23:09:44 2023
11324 23:11:52.056485 <6>[ 45.691375] PM: suspend entry (deep)
11325 23:11:52.059508 <6>[ 45.691418] Filesystems sync: 0.000 seconds
11326 23:11:52.062825 <6>[ 45.691932] Freezing user space processes
11327 23:11:52.069944 <6>[ 45.693536] Freezing user space processes completed (elapsed 0.001 seconds)
11328 23:11:52.073094 <6>[ 45.693541] OOM killer disabled.
11329 23:11:52.079534 <6>[ 45.693543] Freezing remaining freezable tasks
11330 23:11:52.086333 <6>[ 45.694910] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11331 23:11:52.093354 <6>[ 45.694919] printk: Suspending console(s) (use no_console_suspend to debug)
11332 23:11:55.489112 <6>[ 48.129762] vpu: disabling
11333 23:11:55.491907 <6>[ 48.129894] vproc2: disabling
11334 23:11:55.495216 <6>[ 48.129940] vproc1: disabling
11335 23:11:55.498742 <6>[ 48.129986] vaud18: disabling
11336 23:11:55.502270 <6>[ 48.130196] vsram_others: disabling
11337 23:11:55.505329 <6>[ 48.130363] va09: disabling
11338 23:11:55.508740 <6>[ 48.130428] vsram_md: disabling
11339 23:11:55.511581 <6>[ 48.130538] Vgpu: disabling
11340 23:11:55.518854 <3>[ 48.897646] mt7921e 0000:01:00.0: Message 00020007 (seq 13) timeout
11341 23:11:55.528694 <3>[ 48.897673] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11342 23:11:55.538844 <3>[ 48.897705] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11343 23:11:55.545181 <3>[ 48.897737] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11344 23:11:55.552605 <3>[ 48.898015] PM: Some devices failed to suspend, or early wake event detected
11345 23:11:55.600482 <6>[ 49.233698] OOM killer enabled.
11346 23:11:55.603391 rtcwake: <6>[ 49.233708] Restarting tasks ... done.
11347 23:11:55.609768 <5>[ 49.235556] random: crng reseeded on system resumption
11348 23:11:55.612815 <6>[ 49.236566] PM: suspend exit
11349 23:11:55.613307 write error
11350 23:11:55.619706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-8 RESULT=fail>
11351 23:11:55.620221 rtcwake: assuming RTC uses UTC ...
11352 23:11:55.620867 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-8 RESULT=fail
11354 23:11:55.626319 rtcwake: wakeup from "mem" using rtc0 at Sun Dec 3 23:09:47 2023
11355 23:11:55.640291 <6>[ 49.275503] PM: suspend entry (deep)
11356 23:11:55.642990 <6>[ 49.275552] Filesystems sync: 0.000 seconds
11357 23:11:55.646741 <6>[ 49.276088] Freezing user space processes
11358 23:11:55.653364 <6>[ 49.277494] Freezing user space processes completed (elapsed 0.001 seconds)
11359 23:11:55.656743 <6>[ 49.277499] OOM killer disabled.
11360 23:11:55.663258 <6>[ 49.277501] Freezing remaining freezable tasks
11361 23:11:55.669891 <6>[ 49.278932] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11362 23:11:55.677240 <6>[ 49.278942] printk: Suspending console(s) (use no_console_suspend to debug)
11363 23:11:59.079743 <3>[ 52.481627] mt7921e 0000:01:00.0: Message 00020007 (seq 14) timeout
11364 23:11:59.089617 <3>[ 52.481652] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11365 23:11:59.099599 <3>[ 52.481683] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11366 23:11:59.106129 <3>[ 52.481713] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11367 23:11:59.112721 <3>[ 52.481954] PM: Some devices failed to suspend, or early wake event detected
11368 23:11:59.187121 rtcwake: <6>[ 52.821714] OOM killer enabled.
11369 23:11:59.190103 <6>[ 52.821725] Restarting tasks ... done.
11370 23:11:59.196905 <5>[ 52.823751] random: crng reseeded on system resumption
11371 23:11:59.200647 <6>[ 52.824739] PM: suspend exit
11372 23:11:59.201025 write error
11373 23:11:59.203887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-9 RESULT=fail>
11374 23:11:59.204541 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-9 RESULT=fail
11376 23:11:59.206958 rtcwake: assuming RTC uses UTC ...
11377 23:11:59.213356 rtcwake: wakeup from "mem" using rtc0 at Sun Dec 3 23:09:51 2023
11378 23:11:59.227596 <6>[ 52.862034] PM: suspend entry (deep)
11379 23:11:59.230520 <6>[ 52.862082] Filesystems sync: 0.000 seconds
11380 23:11:59.234047 <6>[ 52.862624] Freezing user space processes
11381 23:11:59.240543 <6>[ 52.864361] Freezing user space processes completed (elapsed 0.001 seconds)
11382 23:11:59.247439 <6>[ 52.864372] OOM killer disabled.
11383 23:11:59.251029 <6>[ 52.864375] Freezing remaining freezable tasks
11384 23:11:59.257309 <6>[ 52.865402] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11385 23:11:59.264493 <6>[ 52.865406] printk: Suspending console(s) (use no_console_suspend to debug)
11386 23:12:02.654821 <3>[ 56.065645] mt7921e 0000:01:00.0: Message 00020007 (seq 15) timeout
11387 23:12:02.664920 <3>[ 56.065672] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11388 23:12:02.675336 <3>[ 56.065707] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11389 23:12:02.682004 <3>[ 56.065740] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11390 23:12:02.688397 <3>[ 56.065949] PM: Some devices failed to suspend, or early wake event detected
11391 23:12:02.758834 rtcwake: write error
11392 23:12:02.762174 <6>[ 56.397771] OOM killer enabled.
11393 23:12:02.765462 <6>[ 56.397783] Restarting tasks ... done.
11394 23:12:02.771903 <5>[ 56.399506] random: crng reseeded on system resumption
11395 23:12:02.775199 <6>[ 56.400355] PM: suspend exit
11396 23:12:02.782017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-10 RESULT=fail>
11397 23:12:02.782441 rtcwake: assuming RTC uses UTC ...
11398 23:12:02.783050 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-10 RESULT=fail
11400 23:12:02.788913 rtcwake: wakeup from "freeze" using rtc0 at Sun Dec 3 23:09:54 2023
11401 23:12:02.802968 <6>[ 56.439724] PM: suspend entry (s2idle)
11402 23:12:02.806159 <6>[ 56.439767] Filesystems sync: 0.000 seconds
11403 23:12:02.809898 <6>[ 56.440300] Freezing user space processes
11404 23:12:02.816398 <6>[ 56.441612] Freezing user space processes completed (elapsed 0.001 seconds)
11405 23:12:02.823452 <6>[ 56.441621] OOM killer disabled.
11406 23:12:02.826535 <6>[ 56.441624] Freezing remaining freezable tasks
11407 23:12:02.833060 <6>[ 56.443073] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11408 23:12:02.839542 <6>[ 56.443085] printk: Suspending console(s) (use no_console_suspend to debug)
11409 23:12:06.246661 <3>[ 59.649663] mt7921e 0000:01:00.0: Message 00020007 (seq 1) timeout
11410 23:12:06.256698 <3>[ 59.649692] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11411 23:12:06.266268 <3>[ 59.649736] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11412 23:12:06.273020 <3>[ 59.649777] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11413 23:12:06.280263 <3>[ 59.650024] PM: Some devices failed to suspend, or early wake event detected
11414 23:12:06.354836 <6>[ 59.989727] OOM killer enabled.
11415 23:12:06.357921 rtcwake: <6>[ 59.989739] Restarting tasks ... done.
11416 23:12:06.364931 <5>[ 59.995214] random: crng reseeded on system resumption
11417 23:12:06.368147 <6>[ 59.996918] PM: suspend exit
11418 23:12:06.368566 write error
11419 23:12:06.374989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-1 RESULT=fail>
11420 23:12:06.375679 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-1 RESULT=fail
11422 23:12:06.378064 rtcwake: assuming RTC uses UTC ...
11423 23:12:06.381409 rtcwake: wakeup from "freeze" using rtc0 at Sun Dec 3 23:09:58 2023
11424 23:12:06.394726 <6>[ 60.031727] PM: suspend entry (s2idle)
11425 23:12:06.397724 <6>[ 60.031768] Filesystems sync: 0.000 seconds
11426 23:12:06.401416 <6>[ 60.032299] Freezing user space processes
11427 23:12:06.407671 <6>[ 60.033476] Freezing user space processes completed (elapsed 0.001 seconds)
11428 23:12:06.414725 <6>[ 60.033481] OOM killer disabled.
11429 23:12:06.418356 <6>[ 60.033483] Freezing remaining freezable tasks
11430 23:12:06.424600 <6>[ 60.034878] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11431 23:12:06.431061 <6>[ 60.034889] printk: Suspending console(s) (use no_console_suspend to debug)
11432 23:12:09.821719 <3>[ 63.233659] mt7921e 0000:01:00.0: Message 00020007 (seq 2) timeout
11433 23:12:09.831734 <3>[ 63.233689] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11434 23:12:09.841753 <3>[ 63.233733] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11435 23:12:09.848858 <3>[ 63.233775] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11436 23:12:09.855216 <3>[ 63.234076] PM: Some devices failed to suspend, or early wake event detected
11437 23:12:09.929846 rtcwake: <6>[ 63.565725] OOM killer enabled.
11438 23:12:09.932369 <6>[ 63.565737] Restarting tasks ... done.
11439 23:12:09.939393 <5>[ 63.567902] random: crng reseeded on system resumption
11440 23:12:09.939477 write error
11441 23:12:09.942432 <6>[ 63.568795] PM: suspend exit
11442 23:12:09.949519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-2 RESULT=fail>
11443 23:12:09.949863 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-2 RESULT=fail
11445 23:12:09.952756 rtcwake: assuming RTC uses UTC ...
11446 23:12:09.955687 rtcwake: wakeup from "freeze" using rtc0 at Sun Dec 3 23:10:02 2023
11447 23:12:09.974170 <6>[ 63.609670] PM: suspend entry (s2idle)
11448 23:12:09.977301 <6>[ 63.609728] Filesystems sync: 0.000 seconds
11449 23:12:09.980722 <6>[ 63.610272] Freezing user space processes
11450 23:12:09.987239 <6>[ 63.611956] Freezing user space processes completed (elapsed 0.001 seconds)
11451 23:12:09.993847 <6>[ 63.611967] OOM killer disabled.
11452 23:12:09.997097 <6>[ 63.611969] Freezing remaining freezable tasks
11453 23:12:10.003674 <6>[ 63.613394] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11454 23:12:10.010567 <6>[ 63.613410] printk: Suspending console(s) (use no_console_suspend to debug)
11455 23:12:13.409541 <3>[ 66.817707] mt7921e 0000:01:00.0: Message 00020007 (seq 3) timeout
11456 23:12:13.419398 <3>[ 66.817740] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11457 23:12:13.429320 <3>[ 66.817778] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11458 23:12:13.436342 <3>[ 66.817812] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11459 23:12:13.442729 <3>[ 66.818058] PM: Some devices failed to suspend, or early wake event detected
11460 23:12:13.513184 rtcwake: write error
11461 23:12:13.516175 <6>[ 67.153585] OOM killer enabled.
11462 23:12:13.523409 <LAVA_SIGNAL_TES<6>[ 67.153597] Restarting tasks ... done.
11463 23:12:13.523663 Received signal: <TES<6>[> 67.153597] Restarting tasks ... done.
TCASE TEST_CASE_<5
11464 23:12:13.529545 TCASE TEST_CASE_<5>[ 67.155402] random: crng reseeded on system resumption
11465 23:12:13.533196 ID=rtcwake-freez<6>[ 67.156211] PM: suspend exit
11466 23:12:13.536648 e-3 RESULT=fail>
11467 23:12:13.536745 rtcwake: assuming RTC uses UTC ...
11468 23:12:13.542987 rtcwake: wakeup from "freeze" using rtc0 at Sun Dec 3 23:10:05 2023
11469 23:12:13.557670 <6>[ 67.194137] PM: suspend entry (s2idle)
11470 23:12:13.561014 <6>[ 67.194185] Filesystems sync: 0.000 seconds
11471 23:12:13.564029 <6>[ 67.194705] Freezing user space processes
11472 23:12:13.570908 <6>[ 67.196381] Freezing user space processes completed (elapsed 0.001 seconds)
11473 23:12:13.574516 <6>[ 67.196392] OOM killer disabled.
11474 23:12:13.580984 <6>[ 67.196395] Freezing remaining freezable tasks
11475 23:12:13.587806 <6>[ 67.197403] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11476 23:12:13.594304 <6>[ 67.197409] printk: Suspending console(s) (use no_console_suspend to debug)
11477 23:12:16.989177 <3>[ 70.401726] mt7921e 0000:01:00.0: Message 00020007 (seq 4) timeout
11478 23:12:16.999379 <3>[ 70.401763] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11479 23:12:17.009363 <3>[ 70.401808] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11480 23:12:17.015983 <3>[ 70.401852] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11481 23:12:17.022494 <3>[ 70.402094] PM: Some devices failed to suspend, or early wake event detected
11482 23:12:17.096160 rtcwake: write e<6>[ 70.733730] OOM killer enabled.
11483 23:12:17.096264 rror
11484 23:12:17.099440 <6>[ 70.733741] Restarting tasks ... done.
11485 23:12:17.106039 <LAVA_SIGNAL_TES<5>[ 70.735283] random: crng reseeded on system resumption
11486 23:12:17.109634 Received signal: <TES<5>[> 70.735283] random: crng reseeded on system resumption
TCASE TEST_CASE_<6
11487 23:12:17.112593 TCASE TEST_CASE_<6>[ 70.736230] PM: suspend exit
11488 23:12:17.115753 ID=rtcwake-freeze-4 RESULT=fail>
11489 23:12:17.119193 rtcwake: assuming RTC uses UTC ...
11490 23:12:17.122845 rtcwake: wakeup from "freeze" using rtc0 at Sun Dec 3 23:10:09 2023
11491 23:12:17.140789 <6>[ 70.778279] PM: suspend entry (s2idle)
11492 23:12:17.144377 <6>[ 70.778329] Filesystems sync: 0.000 seconds
11493 23:12:17.147813 <6>[ 70.778848] Freezing user space processes
11494 23:12:17.154312 <6>[ 70.780496] Freezing user space processes completed (elapsed 0.001 seconds)
11495 23:12:17.160924 <6>[ 70.780507] OOM killer disabled.
11496 23:12:17.164418 <6>[ 70.780509] Freezing remaining freezable tasks
11497 23:12:17.171372 <6>[ 70.781388] Freezing remaining freezable tasks completed (elapsed 0.000 seconds)
11498 23:12:17.177568 <6>[ 70.781393] printk: Suspending console(s) (use no_console_suspend to debug)
11499 23:12:20.581173 <3>[ 73.985691] mt7921e 0000:01:00.0: Message 00020007 (seq 5) timeout
11500 23:12:20.594222 <3>[ 73.985725] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11501 23:12:20.601364 <3>[ 73.985784] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11502 23:12:20.607732 <3>[ 73.985830] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11503 23:12:20.617765 <3>[ 73.986089] PM: Some devices failed to suspend, or early wake event detected
11504 23:12:20.688775 rtcwake: write e<6>[ 74.325724] OOM killer enabled.
11505 23:12:20.689333 rror
11506 23:12:20.692163 <6>[ 74.325736] Restarting tasks ... done.
11507 23:12:20.698563 <5>[ 74.327880] random: crng reseeded on system resumption
11508 23:12:20.702196 <LAVA_SIGNAL_TES<6>[ 74.328755] PM: suspend exit
11509 23:12:20.708863 TCASE TEST_CASE_ID=rtcwake-freeze-5 RESULT=fail>
11510 23:12:20.709429 rtcwake: assuming RTC uses UTC ...
11511 23:12:20.710145 Received signal: <TES<6>[> 74.328755] PM: suspend exit
TCASE TEST_CASE_ID=rtcwake-freeze-5 RESULT=fail
11512 23:12:20.715711 rtcwake: wakeup from "freeze" using rtc0 at Sun Dec 3 23:10:12 2023
11513 23:12:20.733152 <6>[ 74.369609] PM: suspend entry (s2idle)
11514 23:12:20.736630 <6>[ 74.369656] Filesystems sync: 0.000 seconds
11515 23:12:20.739742 <6>[ 74.370201] Freezing user space processes
11516 23:12:20.749707 <6>[ 74.371875] Freezing user space processes completed (elapsed 0.001 seconds)
11517 23:12:20.752877 <6>[ 74.371886] OOM killer disabled.
11518 23:12:20.756655 <6>[ 74.371888] Freezing remaining freezable tasks
11519 23:12:20.763031 <6>[ 74.373270] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11520 23:12:20.769764 <6>[ 74.373282] printk: Suspending console(s) (use no_console_suspend to debug)
11521 23:12:24.164415 <3>[ 77.569662] mt7921e 0000:01:00.0: Message 00020007 (seq 6) timeout
11522 23:12:24.174503 <3>[ 77.569692] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11523 23:12:24.184665 <3>[ 77.569735] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11524 23:12:24.191072 <3>[ 77.569776] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11525 23:12:24.197561 <3>[ 77.570082] PM: Some devices failed to suspend, or early wake event detected
11526 23:12:24.269693 <6>[ 77.909731] OOM killer enabled.
11527 23:12:24.276374 rtcwake: write e<6>[ 77.909744] Restarting tasks ... done.
11528 23:12:24.276799 rror
11529 23:12:24.283198 <5>[ 77.911781] random: crng reseeded on system resumption
11530 23:12:24.286942 <LAVA_SIGNAL_TES<6>[ 77.917074] PM: suspend exit
11531 23:12:24.290357 Received signal: <TES<6>[> 77.917074] PM: suspend exit
TCASE TEST_CASE_ID=rtcwake-freeze-6 RESULT=fail
11532 23:12:24.293325 TCASE TEST_CASE_ID=rtcwake-freeze-6 RESULT=fail>
11533 23:12:24.293924 rtcwake: assuming RTC uses UTC ...
11534 23:12:24.299523 rtcwake: wakeup from "freeze" using rtc0 at Sun Dec 3 23:10:16 2023
11535 23:12:24.316957 <6>[ 77.953625] PM: suspend entry (s2idle)
11536 23:12:24.320364 <6>[ 77.953682] Filesystems sync: 0.000 seconds
11537 23:12:24.323921 <6>[ 77.954231] Freezing user space processes
11538 23:12:24.330164 <6>[ 77.955914] Freezing user space processes completed (elapsed 0.001 seconds)
11539 23:12:24.337434 <6>[ 77.955926] OOM killer disabled.
11540 23:12:24.340219 <6>[ 77.955928] Freezing remaining freezable tasks
11541 23:12:24.347021 <6>[ 77.957366] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11542 23:12:24.353572 <6>[ 77.957381] printk: Suspending console(s) (use no_console_suspend to debug)
11543 23:12:27.748115 <3>[ 81.153690] mt7921e 0000:01:00.0: Message 00020007 (seq 7) timeout
11544 23:12:27.758011 <3>[ 81.153723] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11545 23:12:27.768246 <3>[ 81.153780] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11546 23:12:27.774628 <3>[ 81.153828] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11547 23:12:27.781765 <3>[ 81.154140] PM: Some devices failed to suspend, or early wake event detected
11548 23:12:27.856056 <6>[ 81.493729] OOM killer enabled.
11549 23:12:27.859086 <6>[ 81.493741] Restarting tasks ... done.
11550 23:12:27.862552 <5>[ 81.498455] random: crng reseeded on system resumption
11551 23:12:27.866024 <6>[ 81.505597] PM: suspend exit
11552 23:12:27.869067 rtcwake: write error
11553 23:12:27.877758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-7 RESULT=fail>
11554 23:12:27.878016 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-7 RESULT=fail
11556 23:12:27.880855 rtcwake: assuming RTC uses UTC ...
11557 23:12:27.887246 rtcwake: wakeup from "freeze" using rtc0 at Sun Dec 3 23:10:20 2023
11558 23:12:27.904248 <6>[ 81.541579] PM: suspend entry (s2idle)
11559 23:12:27.907167 <6>[ 81.541628] Filesystems sync: 0.000 seconds
11560 23:12:27.910547 <6>[ 81.542163] Freezing user space processes
11561 23:12:27.920538 <6>[ 81.543768] Freezing user space processes completed (elapsed 0.001 seconds)
11562 23:12:27.923819 <6>[ 81.543780] OOM killer disabled.
11563 23:12:27.927317 <6>[ 81.543782] Freezing remaining freezable tasks
11564 23:12:27.933812 <6>[ 81.545166] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11565 23:12:27.940525 <6>[ 81.545179] printk: Suspending console(s) (use no_console_suspend to debug)
11566 23:12:31.323583 <3>[ 84.737652] mt7921e 0000:01:00.0: Message 00020007 (seq 8) timeout
11567 23:12:31.333356 <3>[ 84.737680] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11568 23:12:31.343198 <3>[ 84.737721] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11569 23:12:31.350233 <3>[ 84.737762] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11570 23:12:31.356433 <3>[ 84.738012] PM: Some devices failed to suspend, or early wake event detected
11571 23:12:31.430807 rtcwake: <6>[ 85.069732] OOM killer enabled.
11572 23:12:31.434207 <6>[ 85.069744] Restarting tasks ... done.
11573 23:12:31.440818 <5>[ 85.071781] random: crng reseeded on system resumption
11574 23:12:31.444284 <6>[ 85.072802] PM: suspend exit
11575 23:12:31.444358 write error
11576 23:12:31.450633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-8 RESULT=fail>
11577 23:12:31.450887 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-8 RESULT=fail
11579 23:12:31.454196 rtcwake: assuming RTC uses UTC ...
11580 23:12:31.457484 rtcwake: wakeup from "freeze" using rtc0 at Sun Dec 3 23:10:23 2023
11581 23:12:31.471436 <6>[ 85.111005] PM: suspend entry (s2idle)
11582 23:12:31.474928 <6>[ 85.111056] Filesystems sync: 0.000 seconds
11583 23:12:31.478225 <6>[ 85.111585] Freezing user space processes
11584 23:12:31.488236 <6>[ 85.113167] Freezing user space processes completed (elapsed 0.001 seconds)
11585 23:12:31.491769 <6>[ 85.113177] OOM killer disabled.
11586 23:12:31.494819 <6>[ 85.113179] Freezing remaining freezable tasks
11587 23:12:31.501181 <6>[ 85.114492] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11588 23:12:31.508075 <6>[ 85.114502] printk: Suspending console(s) (use no_console_suspend to debug)
11589 23:12:34.907966 <3>[ 88.321656] mt7921e 0000:01:00.0: Message 00020007 (seq 9) timeout
11590 23:12:34.917220 <3>[ 88.321685] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11591 23:12:34.927350 <3>[ 88.321730] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11592 23:12:34.934189 <3>[ 88.321771] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11593 23:12:34.940833 <3>[ 88.322067] PM: Some devices failed to suspend, or early wake event detected
11594 23:12:35.011099 rtcwake: write error
11595 23:12:35.014555 <6>[ 88.653728] OOM killer enabled.
11596 23:12:35.017921 <6>[ 88.653739] Restarting tasks ... done.
11597 23:12:35.024805 <LAVA_SIGNAL_TES<5>[ 88.655281] random: crng reseeded on system resumption
11598 23:12:35.025498 Received signal: <TES<5>[> 88.655281] random: crng reseeded on system resumption
<6
11599 23:12:35.027666 <6>[ 88.656379] PM: suspend exit
11600 23:12:35.034748 TCASE TEST_CASE_ID=rtcwake-freeze-9 RESULT=fail>
11601 23:12:35.038185 rtcwake: assuming RTC uses UTC ...
11602 23:12:35.041105 rtcwake: wakeup from "freeze" using rtc0 at Sun Dec 3 23:10:27 2023
11603 23:12:35.055339 <6>[ 88.697113] PM: suspend entry (s2idle)
11604 23:12:35.058872 <6>[ 88.697160] Filesystems sync: 0.000 seconds
11605 23:12:35.062175 <6>[ 88.697814] Freezing user space processes
11606 23:12:35.072034 <6>[ 88.701655] Freezing user space processes completed (elapsed 0.003 seconds)
11607 23:12:35.075731 <6>[ 88.701665] OOM killer disabled.
11608 23:12:35.078605 <6>[ 88.701666] Freezing remaining freezable tasks
11609 23:12:35.085157 <6>[ 88.702980] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11610 23:12:35.092180 <6>[ 88.702990] printk: Suspending console(s) (use no_console_suspend to debug)
11611 23:12:38.491388 <3>[ 91.905673] mt7921e 0000:01:00.0: Message 00020007 (seq 10) timeout
11612 23:12:38.501636 <3>[ 91.905699] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11613 23:12:38.510817 <3>[ 91.905733] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11614 23:12:38.517921 <3>[ 91.905764] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11615 23:12:38.524641 <3>[ 91.905973] PM: Some devices failed to suspend, or early wake event detected
11616 23:12:38.599156 <6>[ 92.237736] OOM killer enabled.
11617 23:12:38.602677 rtcwake: write e<6>[ 92.237747] Restarting tasks ... done.
11618 23:12:38.609335 <5>[ 92.239600] random: crng reseeded on system resumption
11619 23:12:38.609803 rror
11620 23:12:38.612320 <LAVA_SIGN<6>[ 92.241412] PM: suspend exit
11621 23:12:38.619294 AL_TESTCASE TEST_CASE_ID=rtcwake-freeze-10 RESULT=fail>
11622 23:12:38.619711 + set +x
11623 23:12:38.622876 <LAVA_SIGNAL_ENDRUN 0_sleep 12172398_1.5.2.3.1>
11624 23:12:38.623654 Received signal: <ENDRUN> 0_sleep 12172398_1.5.2.3.1
11625 23:12:38.624145 Ending use of test pattern.
11626 23:12:38.624474 Ending test lava.0_sleep (12172398_1.5.2.3.1), duration 71.67
11628 23:12:38.625752 <LAVA_TEST_RUNNER EXIT>
11629 23:12:38.626377 ok: lava_test_shell seems to have completed
11630 23:12:38.627136 rtc-exist: pass
rtc-wakeup-enabled: pass
rtcwake-freeze-1: fail
rtcwake-freeze-2: fail
rtcwake-freeze-7: fail
rtcwake-freeze-8: fail
rtcwake-mem-10: fail
rtcwake-mem-2: fail
rtcwake-mem-4: fail
rtcwake-mem-6: fail
rtcwake-mem-7: fail
rtcwake-mem-8: fail
rtcwake-mem-9: fail
11631 23:12:38.627577 end: 3.1 lava-test-shell (duration 00:01:12) [common]
11632 23:12:38.627997 end: 3 lava-test-retry (duration 00:01:12) [common]
11633 23:12:38.628431 start: 4 finalize (timeout 00:06:05) [common]
11634 23:12:38.628875 start: 4.1 power-off (timeout 00:00:30) [common]
11635 23:12:38.629647 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=off'
11636 23:12:38.714944 >> Command sent successfully.
11637 23:12:38.719696 Returned 0 in 0 seconds
11638 23:12:38.820662 end: 4.1 power-off (duration 00:00:00) [common]
11640 23:12:38.822197 start: 4.2 read-feedback (timeout 00:06:05) [common]
11641 23:12:38.823374 Listened to connection for namespace 'common' for up to 1s
11642 23:12:39.823874 Finalising connection for namespace 'common'
11643 23:12:39.824046 Disconnecting from shell: Finalise
11644 23:12:39.824127 / #
11645 23:12:39.924737 end: 4.2 read-feedback (duration 00:00:01) [common]
11646 23:12:39.925370 end: 4 finalize (duration 00:00:01) [common]
11647 23:12:39.925988 Cleaning after the job
11648 23:12:39.926474 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12172398/tftp-deploy-iy98jilq/ramdisk
11649 23:12:39.972123 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12172398/tftp-deploy-iy98jilq/kernel
11650 23:12:40.000668 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12172398/tftp-deploy-iy98jilq/dtb
11651 23:12:40.000902 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12172398/tftp-deploy-iy98jilq/modules
11652 23:12:40.008155 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12172398
11653 23:12:40.180369 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12172398
11654 23:12:40.180548 Job finished correctly