Boot log: mt8192-asurada-spherion-r0
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 21
- Kernel Errors: 31
- Errors: 1
1 23:13:23.298125 lava-dispatcher, installed at version: 2023.10
2 23:13:23.298344 start: 0 validate
3 23:13:23.298482 Start time: 2023-12-03 23:13:23.298474+00:00 (UTC)
4 23:13:23.298608 Using caching service: 'http://localhost/cache/?uri=%s'
5 23:13:23.298742 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-v4l2%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 23:13:23.574130 Using caching service: 'http://localhost/cache/?uri=%s'
7 23:13:23.574812 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.64-cip10-rt5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 23:13:23.844920 Using caching service: 'http://localhost/cache/?uri=%s'
9 23:13:23.845893 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.64-cip10-rt5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 23:13:24.118878 Using caching service: 'http://localhost/cache/?uri=%s'
11 23:13:24.119715 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.64-cip10-rt5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 23:13:24.395272 validate duration: 1.10
14 23:13:24.395567 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 23:13:24.395665 start: 1.1 download-retry (timeout 00:10:00) [common]
16 23:13:24.395751 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 23:13:24.395882 Not decompressing ramdisk as can be used compressed.
18 23:13:24.395969 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-v4l2/20230623.0/arm64/rootfs.cpio.gz
19 23:13:24.396036 saving as /var/lib/lava/dispatcher/tmp/12172417/tftp-deploy-syndytqy/ramdisk/rootfs.cpio.gz
20 23:13:24.396100 total size: 26246609 (25 MB)
21 23:13:24.397174 progress 0 % (0 MB)
22 23:13:24.404704 progress 5 % (1 MB)
23 23:13:24.412092 progress 10 % (2 MB)
24 23:13:24.419379 progress 15 % (3 MB)
25 23:13:24.426442 progress 20 % (5 MB)
26 23:13:24.433262 progress 25 % (6 MB)
27 23:13:24.440104 progress 30 % (7 MB)
28 23:13:24.446973 progress 35 % (8 MB)
29 23:13:24.453851 progress 40 % (10 MB)
30 23:13:24.460696 progress 45 % (11 MB)
31 23:13:24.467614 progress 50 % (12 MB)
32 23:13:24.474576 progress 55 % (13 MB)
33 23:13:24.481463 progress 60 % (15 MB)
34 23:13:24.488473 progress 65 % (16 MB)
35 23:13:24.495320 progress 70 % (17 MB)
36 23:13:24.502151 progress 75 % (18 MB)
37 23:13:24.508985 progress 80 % (20 MB)
38 23:13:24.515898 progress 85 % (21 MB)
39 23:13:24.522717 progress 90 % (22 MB)
40 23:13:24.529395 progress 95 % (23 MB)
41 23:13:24.536102 progress 100 % (25 MB)
42 23:13:24.536349 25 MB downloaded in 0.14 s (178.47 MB/s)
43 23:13:24.536509 end: 1.1.1 http-download (duration 00:00:00) [common]
45 23:13:24.536753 end: 1.1 download-retry (duration 00:00:00) [common]
46 23:13:24.536839 start: 1.2 download-retry (timeout 00:10:00) [common]
47 23:13:24.536922 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 23:13:24.537062 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.64-cip10-rt5/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 23:13:24.537135 saving as /var/lib/lava/dispatcher/tmp/12172417/tftp-deploy-syndytqy/kernel/Image
50 23:13:24.537196 total size: 49172992 (46 MB)
51 23:13:24.537258 No compression specified
52 23:13:24.538433 progress 0 % (0 MB)
53 23:13:24.551326 progress 5 % (2 MB)
54 23:13:24.564193 progress 10 % (4 MB)
55 23:13:24.577102 progress 15 % (7 MB)
56 23:13:24.589967 progress 20 % (9 MB)
57 23:13:24.602870 progress 25 % (11 MB)
58 23:13:24.615704 progress 30 % (14 MB)
59 23:13:24.628602 progress 35 % (16 MB)
60 23:13:24.641443 progress 40 % (18 MB)
61 23:13:24.654273 progress 45 % (21 MB)
62 23:13:24.667102 progress 50 % (23 MB)
63 23:13:24.679976 progress 55 % (25 MB)
64 23:13:24.692744 progress 60 % (28 MB)
65 23:13:24.705541 progress 65 % (30 MB)
66 23:13:24.718530 progress 70 % (32 MB)
67 23:13:24.731737 progress 75 % (35 MB)
68 23:13:24.744657 progress 80 % (37 MB)
69 23:13:24.757471 progress 85 % (39 MB)
70 23:13:24.770935 progress 90 % (42 MB)
71 23:13:24.784400 progress 95 % (44 MB)
72 23:13:24.797061 progress 100 % (46 MB)
73 23:13:24.797295 46 MB downloaded in 0.26 s (180.30 MB/s)
74 23:13:24.797452 end: 1.2.1 http-download (duration 00:00:00) [common]
76 23:13:24.797724 end: 1.2 download-retry (duration 00:00:00) [common]
77 23:13:24.797816 start: 1.3 download-retry (timeout 00:10:00) [common]
78 23:13:24.797901 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 23:13:24.798046 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.64-cip10-rt5/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 23:13:24.798117 saving as /var/lib/lava/dispatcher/tmp/12172417/tftp-deploy-syndytqy/dtb/mt8192-asurada-spherion-r0.dtb
81 23:13:24.798179 total size: 47278 (0 MB)
82 23:13:24.798241 No compression specified
83 23:13:24.799388 progress 69 % (0 MB)
84 23:13:24.799666 progress 100 % (0 MB)
85 23:13:24.799823 0 MB downloaded in 0.00 s (27.48 MB/s)
86 23:13:24.799944 end: 1.3.1 http-download (duration 00:00:00) [common]
88 23:13:24.800165 end: 1.3 download-retry (duration 00:00:00) [common]
89 23:13:24.800250 start: 1.4 download-retry (timeout 00:10:00) [common]
90 23:13:24.800333 start: 1.4.1 http-download (timeout 00:10:00) [common]
91 23:13:24.800452 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.64-cip10-rt5/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 23:13:24.800520 saving as /var/lib/lava/dispatcher/tmp/12172417/tftp-deploy-syndytqy/modules/modules.tar
93 23:13:24.800581 total size: 8614132 (8 MB)
94 23:13:24.800642 Using unxz to decompress xz
95 23:13:24.804868 progress 0 % (0 MB)
96 23:13:24.825820 progress 5 % (0 MB)
97 23:13:24.849932 progress 10 % (0 MB)
98 23:13:24.874073 progress 15 % (1 MB)
99 23:13:24.898169 progress 20 % (1 MB)
100 23:13:24.922147 progress 25 % (2 MB)
101 23:13:24.947712 progress 30 % (2 MB)
102 23:13:24.973966 progress 35 % (2 MB)
103 23:13:24.997339 progress 40 % (3 MB)
104 23:13:25.022292 progress 45 % (3 MB)
105 23:13:25.047399 progress 50 % (4 MB)
106 23:13:25.071795 progress 55 % (4 MB)
107 23:13:25.096609 progress 60 % (4 MB)
108 23:13:25.122100 progress 65 % (5 MB)
109 23:13:25.150717 progress 70 % (5 MB)
110 23:13:25.174188 progress 75 % (6 MB)
111 23:13:25.201081 progress 80 % (6 MB)
112 23:13:25.226666 progress 85 % (7 MB)
113 23:13:25.251795 progress 90 % (7 MB)
114 23:13:25.283981 progress 95 % (7 MB)
115 23:13:25.313469 progress 100 % (8 MB)
116 23:13:25.320053 8 MB downloaded in 0.52 s (15.81 MB/s)
117 23:13:25.320305 end: 1.4.1 http-download (duration 00:00:01) [common]
119 23:13:25.320570 end: 1.4 download-retry (duration 00:00:01) [common]
120 23:13:25.320665 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 23:13:25.320759 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 23:13:25.320842 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 23:13:25.320926 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 23:13:25.321156 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12172417/lava-overlay-dfsz5tf2
125 23:13:25.321293 makedir: /var/lib/lava/dispatcher/tmp/12172417/lava-overlay-dfsz5tf2/lava-12172417/bin
126 23:13:25.321401 makedir: /var/lib/lava/dispatcher/tmp/12172417/lava-overlay-dfsz5tf2/lava-12172417/tests
127 23:13:25.321502 makedir: /var/lib/lava/dispatcher/tmp/12172417/lava-overlay-dfsz5tf2/lava-12172417/results
128 23:13:25.321663 Creating /var/lib/lava/dispatcher/tmp/12172417/lava-overlay-dfsz5tf2/lava-12172417/bin/lava-add-keys
129 23:13:25.321816 Creating /var/lib/lava/dispatcher/tmp/12172417/lava-overlay-dfsz5tf2/lava-12172417/bin/lava-add-sources
130 23:13:25.321951 Creating /var/lib/lava/dispatcher/tmp/12172417/lava-overlay-dfsz5tf2/lava-12172417/bin/lava-background-process-start
131 23:13:25.322086 Creating /var/lib/lava/dispatcher/tmp/12172417/lava-overlay-dfsz5tf2/lava-12172417/bin/lava-background-process-stop
132 23:13:25.322216 Creating /var/lib/lava/dispatcher/tmp/12172417/lava-overlay-dfsz5tf2/lava-12172417/bin/lava-common-functions
133 23:13:25.322343 Creating /var/lib/lava/dispatcher/tmp/12172417/lava-overlay-dfsz5tf2/lava-12172417/bin/lava-echo-ipv4
134 23:13:25.322470 Creating /var/lib/lava/dispatcher/tmp/12172417/lava-overlay-dfsz5tf2/lava-12172417/bin/lava-install-packages
135 23:13:25.322600 Creating /var/lib/lava/dispatcher/tmp/12172417/lava-overlay-dfsz5tf2/lava-12172417/bin/lava-installed-packages
136 23:13:25.322725 Creating /var/lib/lava/dispatcher/tmp/12172417/lava-overlay-dfsz5tf2/lava-12172417/bin/lava-os-build
137 23:13:25.322852 Creating /var/lib/lava/dispatcher/tmp/12172417/lava-overlay-dfsz5tf2/lava-12172417/bin/lava-probe-channel
138 23:13:25.322982 Creating /var/lib/lava/dispatcher/tmp/12172417/lava-overlay-dfsz5tf2/lava-12172417/bin/lava-probe-ip
139 23:13:25.323115 Creating /var/lib/lava/dispatcher/tmp/12172417/lava-overlay-dfsz5tf2/lava-12172417/bin/lava-target-ip
140 23:13:25.323242 Creating /var/lib/lava/dispatcher/tmp/12172417/lava-overlay-dfsz5tf2/lava-12172417/bin/lava-target-mac
141 23:13:25.323368 Creating /var/lib/lava/dispatcher/tmp/12172417/lava-overlay-dfsz5tf2/lava-12172417/bin/lava-target-storage
142 23:13:25.323500 Creating /var/lib/lava/dispatcher/tmp/12172417/lava-overlay-dfsz5tf2/lava-12172417/bin/lava-test-case
143 23:13:25.323628 Creating /var/lib/lava/dispatcher/tmp/12172417/lava-overlay-dfsz5tf2/lava-12172417/bin/lava-test-event
144 23:13:25.323754 Creating /var/lib/lava/dispatcher/tmp/12172417/lava-overlay-dfsz5tf2/lava-12172417/bin/lava-test-feedback
145 23:13:25.323881 Creating /var/lib/lava/dispatcher/tmp/12172417/lava-overlay-dfsz5tf2/lava-12172417/bin/lava-test-raise
146 23:13:25.324011 Creating /var/lib/lava/dispatcher/tmp/12172417/lava-overlay-dfsz5tf2/lava-12172417/bin/lava-test-reference
147 23:13:25.324138 Creating /var/lib/lava/dispatcher/tmp/12172417/lava-overlay-dfsz5tf2/lava-12172417/bin/lava-test-runner
148 23:13:25.324264 Creating /var/lib/lava/dispatcher/tmp/12172417/lava-overlay-dfsz5tf2/lava-12172417/bin/lava-test-set
149 23:13:25.324392 Creating /var/lib/lava/dispatcher/tmp/12172417/lava-overlay-dfsz5tf2/lava-12172417/bin/lava-test-shell
150 23:13:25.324525 Updating /var/lib/lava/dispatcher/tmp/12172417/lava-overlay-dfsz5tf2/lava-12172417/bin/lava-install-packages (oe)
151 23:13:25.324682 Updating /var/lib/lava/dispatcher/tmp/12172417/lava-overlay-dfsz5tf2/lava-12172417/bin/lava-installed-packages (oe)
152 23:13:25.324806 Creating /var/lib/lava/dispatcher/tmp/12172417/lava-overlay-dfsz5tf2/lava-12172417/environment
153 23:13:25.324908 LAVA metadata
154 23:13:25.324983 - LAVA_JOB_ID=12172417
155 23:13:25.325047 - LAVA_DISPATCHER_IP=192.168.201.1
156 23:13:25.325152 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 23:13:25.325221 skipped lava-vland-overlay
158 23:13:25.325296 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 23:13:25.325375 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 23:13:25.325443 skipped lava-multinode-overlay
161 23:13:25.325521 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 23:13:25.325645 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 23:13:25.325723 Loading test definitions
164 23:13:25.325814 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 23:13:25.325890 Using /lava-12172417 at stage 0
166 23:13:25.326198 uuid=12172417_1.5.2.3.1 testdef=None
167 23:13:25.326286 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 23:13:25.326371 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 23:13:25.326890 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 23:13:25.327113 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 23:13:25.327732 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 23:13:25.327968 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 23:13:25.328706 runner path: /var/lib/lava/dispatcher/tmp/12172417/lava-overlay-dfsz5tf2/lava-12172417/0/tests/0_v4l2-compliance-mtk-vcodec-enc test_uuid 12172417_1.5.2.3.1
176 23:13:25.328862 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 23:13:25.329072 Creating lava-test-runner.conf files
179 23:13:25.329135 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12172417/lava-overlay-dfsz5tf2/lava-12172417/0 for stage 0
180 23:13:25.329226 - 0_v4l2-compliance-mtk-vcodec-enc
181 23:13:25.329323 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 23:13:25.329413 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 23:13:25.336311 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 23:13:25.336420 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 23:13:25.336506 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 23:13:25.336591 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 23:13:25.336683 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 23:13:26.058477 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 23:13:26.058864 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 23:13:26.058986 extracting modules file /var/lib/lava/dispatcher/tmp/12172417/tftp-deploy-syndytqy/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12172417/extract-overlay-ramdisk-rx4dvxh9/ramdisk
191 23:13:26.293362 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 23:13:26.293521 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 23:13:26.293661 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12172417/compress-overlay-p1z04p2s/overlay-1.5.2.4.tar.gz to ramdisk
194 23:13:26.293735 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12172417/compress-overlay-p1z04p2s/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12172417/extract-overlay-ramdisk-rx4dvxh9/ramdisk
195 23:13:26.300479 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 23:13:26.300597 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 23:13:26.300688 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 23:13:26.300778 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 23:13:26.300858 Building ramdisk /var/lib/lava/dispatcher/tmp/12172417/extract-overlay-ramdisk-rx4dvxh9/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12172417/extract-overlay-ramdisk-rx4dvxh9/ramdisk
200 23:13:26.941373 >> 228445 blocks
201 23:13:30.847554 rename /var/lib/lava/dispatcher/tmp/12172417/extract-overlay-ramdisk-rx4dvxh9/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12172417/tftp-deploy-syndytqy/ramdisk/ramdisk.cpio.gz
202 23:13:30.847994 end: 1.5.7 compress-ramdisk (duration 00:00:05) [common]
203 23:13:30.848125 start: 1.5.8 prepare-kernel (timeout 00:09:54) [common]
204 23:13:30.848229 start: 1.5.8.1 prepare-fit (timeout 00:09:54) [common]
205 23:13:30.848337 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12172417/tftp-deploy-syndytqy/kernel/Image'
206 23:13:43.346419 Returned 0 in 12 seconds
207 23:13:43.447071 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12172417/tftp-deploy-syndytqy/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12172417/tftp-deploy-syndytqy/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12172417/tftp-deploy-syndytqy/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12172417/tftp-deploy-syndytqy/kernel/image.itb
208 23:13:44.082698 output: FIT description: Kernel Image image with one or more FDT blobs
209 23:13:44.083079 output: Created: Sun Dec 3 23:13:43 2023
210 23:13:44.083160 output: Image 0 (kernel-1)
211 23:13:44.083228 output: Description:
212 23:13:44.083292 output: Created: Sun Dec 3 23:13:43 2023
213 23:13:44.083356 output: Type: Kernel Image
214 23:13:44.083420 output: Compression: lzma compressed
215 23:13:44.083479 output: Data Size: 11049348 Bytes = 10790.38 KiB = 10.54 MiB
216 23:13:44.083539 output: Architecture: AArch64
217 23:13:44.083595 output: OS: Linux
218 23:13:44.083654 output: Load Address: 0x00000000
219 23:13:44.083709 output: Entry Point: 0x00000000
220 23:13:44.083763 output: Hash algo: crc32
221 23:13:44.083818 output: Hash value: c85ea8f0
222 23:13:44.083877 output: Image 1 (fdt-1)
223 23:13:44.083932 output: Description: mt8192-asurada-spherion-r0
224 23:13:44.083986 output: Created: Sun Dec 3 23:13:43 2023
225 23:13:44.084040 output: Type: Flat Device Tree
226 23:13:44.084093 output: Compression: uncompressed
227 23:13:44.084147 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
228 23:13:44.084200 output: Architecture: AArch64
229 23:13:44.084253 output: Hash algo: crc32
230 23:13:44.084306 output: Hash value: cc4352de
231 23:13:44.084360 output: Image 2 (ramdisk-1)
232 23:13:44.084412 output: Description: unavailable
233 23:13:44.084465 output: Created: Sun Dec 3 23:13:43 2023
234 23:13:44.084520 output: Type: RAMDisk Image
235 23:13:44.084573 output: Compression: Unknown Compression
236 23:13:44.084626 output: Data Size: 39354778 Bytes = 38432.40 KiB = 37.53 MiB
237 23:13:44.084679 output: Architecture: AArch64
238 23:13:44.084732 output: OS: Linux
239 23:13:44.084785 output: Load Address: unavailable
240 23:13:44.084838 output: Entry Point: unavailable
241 23:13:44.084891 output: Hash algo: crc32
242 23:13:44.084943 output: Hash value: aa1615f5
243 23:13:44.084996 output: Default Configuration: 'conf-1'
244 23:13:44.085049 output: Configuration 0 (conf-1)
245 23:13:44.085102 output: Description: mt8192-asurada-spherion-r0
246 23:13:44.085155 output: Kernel: kernel-1
247 23:13:44.085208 output: Init Ramdisk: ramdisk-1
248 23:13:44.085262 output: FDT: fdt-1
249 23:13:44.085315 output: Loadables: kernel-1
250 23:13:44.085367 output:
251 23:13:44.085571 end: 1.5.8.1 prepare-fit (duration 00:00:13) [common]
252 23:13:44.085713 end: 1.5.8 prepare-kernel (duration 00:00:13) [common]
253 23:13:44.085867 end: 1.5 prepare-tftp-overlay (duration 00:00:19) [common]
254 23:13:44.085970 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:40) [common]
255 23:13:44.086053 No LXC device requested
256 23:13:44.086138 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 23:13:44.086223 start: 1.7 deploy-device-env (timeout 00:09:40) [common]
258 23:13:44.086302 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 23:13:44.086373 Checking files for TFTP limit of 4294967296 bytes.
260 23:13:44.086879 end: 1 tftp-deploy (duration 00:00:20) [common]
261 23:13:44.086984 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 23:13:44.087074 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 23:13:44.087197 substitutions:
264 23:13:44.087264 - {DTB}: 12172417/tftp-deploy-syndytqy/dtb/mt8192-asurada-spherion-r0.dtb
265 23:13:44.087330 - {INITRD}: 12172417/tftp-deploy-syndytqy/ramdisk/ramdisk.cpio.gz
266 23:13:44.087389 - {KERNEL}: 12172417/tftp-deploy-syndytqy/kernel/Image
267 23:13:44.087447 - {LAVA_MAC}: None
268 23:13:44.087504 - {PRESEED_CONFIG}: None
269 23:13:44.087560 - {PRESEED_LOCAL}: None
270 23:13:44.087615 - {RAMDISK}: 12172417/tftp-deploy-syndytqy/ramdisk/ramdisk.cpio.gz
271 23:13:44.087670 - {ROOT_PART}: None
272 23:13:44.087724 - {ROOT}: None
273 23:13:44.087779 - {SERVER_IP}: 192.168.201.1
274 23:13:44.087837 - {TEE}: None
275 23:13:44.087900 Parsed boot commands:
276 23:13:44.087954 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 23:13:44.088136 Parsed boot commands: tftpboot 192.168.201.1 12172417/tftp-deploy-syndytqy/kernel/image.itb 12172417/tftp-deploy-syndytqy/kernel/cmdline
278 23:13:44.088226 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 23:13:44.088311 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 23:13:44.088414 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 23:13:44.088496 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 23:13:44.088568 Not connected, no need to disconnect.
283 23:13:44.088642 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 23:13:44.088725 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 23:13:44.088789 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-0'
286 23:13:44.092818 Setting prompt string to ['lava-test: # ']
287 23:13:44.093185 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 23:13:44.093330 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 23:13:44.093433 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 23:13:44.093525 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 23:13:44.093795 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=reboot'
292 23:13:49.228875 >> Command sent successfully.
293 23:13:49.231297 Returned 0 in 5 seconds
294 23:13:49.331685 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 23:13:49.331993 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 23:13:49.332090 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 23:13:49.332176 Setting prompt string to 'Starting depthcharge on Spherion...'
299 23:13:49.332241 Changing prompt to 'Starting depthcharge on Spherion...'
300 23:13:49.332323 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 23:13:49.332602 [Enter `^Ec?' for help]
302 23:13:49.505146
303 23:13:49.505287
304 23:13:49.505361 F0: 102B 0000
305 23:13:49.505428
306 23:13:49.505489 F3: 1001 0000 [0200]
307 23:13:49.505549
308 23:13:49.508597 F3: 1001 0000
309 23:13:49.508681
310 23:13:49.508747 F7: 102D 0000
311 23:13:49.508810
312 23:13:49.508869 F1: 0000 0000
313 23:13:49.508929
314 23:13:49.512719 V0: 0000 0000 [0001]
315 23:13:49.512806
316 23:13:49.512872 00: 0007 8000
317 23:13:49.512939
318 23:13:49.516179 01: 0000 0000
319 23:13:49.516295
320 23:13:49.516367 BP: 0C00 0209 [0000]
321 23:13:49.516430
322 23:13:49.516490 G0: 1182 0000
323 23:13:49.516550
324 23:13:49.520190 EC: 0000 0021 [4000]
325 23:13:49.520284
326 23:13:49.520367 S7: 0000 0000 [0000]
327 23:13:49.520445
328 23:13:49.523912 CC: 0000 0000 [0001]
329 23:13:49.523997
330 23:13:49.524103 T0: 0000 0040 [010F]
331 23:13:49.524169
332 23:13:49.527124 Jump to BL
333 23:13:49.527209
334 23:13:49.551930
335 23:13:49.552028
336 23:13:49.552096
337 23:13:49.559582 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 23:13:49.563196 ARM64: Exception handlers installed.
339 23:13:49.566857 ARM64: Testing exception
340 23:13:49.570677 ARM64: Done test exception
341 23:13:49.577939 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 23:13:49.584995 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 23:13:49.592208 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 23:13:49.602764 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 23:13:49.609514 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 23:13:49.619137 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 23:13:49.630102 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 23:13:49.636527 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 23:13:49.654845 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 23:13:49.658100 WDT: Last reset was cold boot
351 23:13:49.661470 SPI1(PAD0) initialized at 2873684 Hz
352 23:13:49.665294 SPI5(PAD0) initialized at 992727 Hz
353 23:13:49.668141 VBOOT: Loading verstage.
354 23:13:49.675000 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 23:13:49.678377 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 23:13:49.681866 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 23:13:49.684834 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 23:13:49.691752 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 23:13:49.698833 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 23:13:49.709556 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
361 23:13:49.709699
362 23:13:49.709769
363 23:13:49.720016 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 23:13:49.723421 ARM64: Exception handlers installed.
365 23:13:49.723512 ARM64: Testing exception
366 23:13:49.726940 ARM64: Done test exception
367 23:13:49.730309 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 23:13:49.736794 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 23:13:49.750671 Probing TPM: . done!
370 23:13:49.750778 TPM ready after 0 ms
371 23:13:49.758027 Connected to device vid:did:rid of 1ae0:0028:00
372 23:13:49.765090 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
373 23:13:49.824012 Initialized TPM device CR50 revision 0
374 23:13:49.836503 tlcl_send_startup: Startup return code is 0
375 23:13:49.836611 TPM: setup succeeded
376 23:13:49.847646 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 23:13:49.856527 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 23:13:49.869571 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 23:13:49.877742 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 23:13:49.881211 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 23:13:49.885158 in-header: 03 07 00 00 08 00 00 00
382 23:13:49.888538 in-data: aa e4 47 04 13 02 00 00
383 23:13:49.892644 Chrome EC: UHEPI supported
384 23:13:49.896049 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 23:13:49.900014 in-header: 03 95 00 00 08 00 00 00
386 23:13:49.903686 in-data: 18 20 20 08 00 00 00 00
387 23:13:49.903775 Phase 1
388 23:13:49.910897 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 23:13:49.914717 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 23:13:49.922370 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 23:13:49.922462 Recovery requested (1009000e)
392 23:13:49.933157 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 23:13:49.938219 tlcl_extend: response is 0
394 23:13:49.949818 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 23:13:49.954008 tlcl_extend: response is 0
396 23:13:49.960574 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 23:13:49.979768 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
398 23:13:49.986805 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 23:13:49.986898
400 23:13:49.986966
401 23:13:49.996934 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 23:13:49.999714 ARM64: Exception handlers installed.
403 23:13:50.003268 ARM64: Testing exception
404 23:13:50.003353 ARM64: Done test exception
405 23:13:50.025456 pmic_efuse_setting: Set efuses in 11 msecs
406 23:13:50.028966 pmwrap_interface_init: Select PMIF_VLD_RDY
407 23:13:50.035924 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 23:13:50.038768 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 23:13:50.046225 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 23:13:50.050281 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 23:13:50.054019 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 23:13:50.060498 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 23:13:50.064494 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 23:13:50.067917 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 23:13:50.071834 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 23:13:50.078938 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 23:13:50.082323 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 23:13:50.086405 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 23:13:50.089932 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 23:13:50.097610 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 23:13:50.104407 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 23:13:50.108499 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 23:13:50.115335 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 23:13:50.119335 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 23:13:50.126302 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 23:13:50.133558 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 23:13:50.137093 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 23:13:50.144635 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 23:13:50.148720 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 23:13:50.152046 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 23:13:50.159800 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 23:13:50.163748 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 23:13:50.170800 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 23:13:50.175018 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 23:13:50.178155 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 23:13:50.185822 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 23:13:50.189432 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 23:13:50.193065 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 23:13:50.200210 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 23:13:50.203925 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 23:13:50.207617 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 23:13:50.215313 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 23:13:50.218615 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 23:13:50.226124 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 23:13:50.230055 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 23:13:50.233379 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 23:13:50.237346 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 23:13:50.240975 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 23:13:50.248156 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 23:13:50.251491 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 23:13:50.256172 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 23:13:50.259697 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 23:13:50.263648 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 23:13:50.267644 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 23:13:50.271003 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 23:13:50.275144 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 23:13:50.281990 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 23:13:50.289892 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 23:13:50.297389 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 23:13:50.300515 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 23:13:50.311783 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 23:13:50.318958 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 23:13:50.322261 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 23:13:50.326339 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 23:13:50.329934 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 23:13:50.339068 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x1b
467 23:13:50.342530 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 23:13:50.347533 [RTC]rtc_osc_init,62: osc32con val = 0xde70
469 23:13:50.354838 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 23:13:50.363308 [RTC]rtc_get_frequency_meter,154: input=15, output=759
471 23:13:50.373221 [RTC]rtc_get_frequency_meter,154: input=23, output=942
472 23:13:50.382384 [RTC]rtc_get_frequency_meter,154: input=19, output=852
473 23:13:50.392238 [RTC]rtc_get_frequency_meter,154: input=17, output=805
474 23:13:50.400792 [RTC]rtc_get_frequency_meter,154: input=16, output=781
475 23:13:50.410923 [RTC]rtc_get_frequency_meter,154: input=16, output=782
476 23:13:50.420826 [RTC]rtc_get_frequency_meter,154: input=17, output=804
477 23:13:50.424203 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
478 23:13:50.428104 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
479 23:13:50.432033 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 23:13:50.439613 [RTC]rtc_boot_common,220: irqsta=1, bbpu=81, con=486
481 23:13:50.443884 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 23:13:50.447771 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
483 23:13:50.447855 ADC[4]: Raw value=906203 ID=7
484 23:13:50.451234 ADC[3]: Raw value=213810 ID=1
485 23:13:50.455009 RAM Code: 0x71
486 23:13:50.459033 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 23:13:50.462727 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 23:13:50.469905 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
489 23:13:50.477469 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
490 23:13:50.480746 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 23:13:50.485243 in-header: 03 07 00 00 08 00 00 00
492 23:13:50.488847 in-data: aa e4 47 04 13 02 00 00
493 23:13:50.492742 Chrome EC: UHEPI supported
494 23:13:50.499514 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 23:13:50.503015 in-header: 03 95 00 00 08 00 00 00
496 23:13:50.507362 in-data: 18 20 20 08 00 00 00 00
497 23:13:50.507447 MRC: failed to locate region type 0.
498 23:13:50.514724 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 23:13:50.518415 DRAM-K: Running full calibration
500 23:13:50.525601 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
501 23:13:50.525701 header.status = 0x0
502 23:13:50.528958 header.version = 0x6 (expected: 0x6)
503 23:13:50.532937 header.size = 0xd00 (expected: 0xd00)
504 23:13:50.533021 header.flags = 0x0
505 23:13:50.540090 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 23:13:50.558991 read SPI 0x72590 0x1c583: 12497 us, 9290 KB/s, 74.320 Mbps
507 23:13:50.565571 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 23:13:50.569046 dram_init: ddr_geometry: 2
509 23:13:50.569153 [EMI] MDL number = 2
510 23:13:50.573442 [EMI] Get MDL freq = 0
511 23:13:50.573526 dram_init: ddr_type: 0
512 23:13:50.576954 is_discrete_lpddr4: 1
513 23:13:50.580411 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 23:13:50.580495
515 23:13:50.580579
516 23:13:50.584149 [Bian_co] ETT version 0.0.0.1
517 23:13:50.587398 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
518 23:13:50.587482
519 23:13:50.591359 dramc_set_vcore_voltage set vcore to 650000
520 23:13:50.591443 Read voltage for 800, 4
521 23:13:50.595359 Vio18 = 0
522 23:13:50.595443 Vcore = 650000
523 23:13:50.595510 Vdram = 0
524 23:13:50.599065 Vddq = 0
525 23:13:50.599148 Vmddr = 0
526 23:13:50.599215 dram_init: config_dvfs: 1
527 23:13:50.606365 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 23:13:50.610240 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 23:13:50.613613 [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9
530 23:13:50.617693 freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9
531 23:13:50.621227 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
532 23:13:50.624838 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
533 23:13:50.628044 MEM_TYPE=3, freq_sel=18
534 23:13:50.631459 sv_algorithm_assistance_LP4_1600
535 23:13:50.634664 ============ PULL DRAM RESETB DOWN ============
536 23:13:50.642090 ========== PULL DRAM RESETB DOWN end =========
537 23:13:50.645277 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 23:13:50.649206 ===================================
539 23:13:50.649290 LPDDR4 DRAM CONFIGURATION
540 23:13:50.652865 ===================================
541 23:13:50.656287 EX_ROW_EN[0] = 0x0
542 23:13:50.656425 EX_ROW_EN[1] = 0x0
543 23:13:50.660310 LP4Y_EN = 0x0
544 23:13:50.660393 WORK_FSP = 0x0
545 23:13:50.663857 WL = 0x2
546 23:13:50.663941 RL = 0x2
547 23:13:50.667559 BL = 0x2
548 23:13:50.667642 RPST = 0x0
549 23:13:50.670744 RD_PRE = 0x0
550 23:13:50.670827 WR_PRE = 0x1
551 23:13:50.674061 WR_PST = 0x0
552 23:13:50.674145 DBI_WR = 0x0
553 23:13:50.677491 DBI_RD = 0x0
554 23:13:50.677639 OTF = 0x1
555 23:13:50.680697 ===================================
556 23:13:50.683972 ===================================
557 23:13:50.687715 ANA top config
558 23:13:50.687798 ===================================
559 23:13:50.691314 DLL_ASYNC_EN = 0
560 23:13:50.694935 ALL_SLAVE_EN = 1
561 23:13:50.697843 NEW_RANK_MODE = 1
562 23:13:50.697932 DLL_IDLE_MODE = 1
563 23:13:50.701253 LP45_APHY_COMB_EN = 1
564 23:13:50.704823 TX_ODT_DIS = 1
565 23:13:50.708247 NEW_8X_MODE = 1
566 23:13:50.712427 ===================================
567 23:13:50.715589 ===================================
568 23:13:50.715673 data_rate = 1600
569 23:13:50.718543 CKR = 1
570 23:13:50.721885 DQ_P2S_RATIO = 8
571 23:13:50.725356 ===================================
572 23:13:50.728822 CA_P2S_RATIO = 8
573 23:13:50.732340 DQ_CA_OPEN = 0
574 23:13:50.735212 DQ_SEMI_OPEN = 0
575 23:13:50.735295 CA_SEMI_OPEN = 0
576 23:13:50.738672 CA_FULL_RATE = 0
577 23:13:50.742294 DQ_CKDIV4_EN = 1
578 23:13:50.745337 CA_CKDIV4_EN = 1
579 23:13:50.749119 CA_PREDIV_EN = 0
580 23:13:50.749203 PH8_DLY = 0
581 23:13:50.752069 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 23:13:50.755532 DQ_AAMCK_DIV = 4
583 23:13:50.758857 CA_AAMCK_DIV = 4
584 23:13:50.761955 CA_ADMCK_DIV = 4
585 23:13:50.765688 DQ_TRACK_CA_EN = 0
586 23:13:50.769031 CA_PICK = 800
587 23:13:50.769114 CA_MCKIO = 800
588 23:13:50.772492 MCKIO_SEMI = 0
589 23:13:50.776456 PLL_FREQ = 3068
590 23:13:50.779919 DQ_UI_PI_RATIO = 32
591 23:13:50.780003 CA_UI_PI_RATIO = 0
592 23:13:50.783358 ===================================
593 23:13:50.787141 ===================================
594 23:13:50.791125 memory_type:LPDDR4
595 23:13:50.791208 GP_NUM : 10
596 23:13:50.795371 SRAM_EN : 1
597 23:13:50.795454 MD32_EN : 0
598 23:13:50.798999 ===================================
599 23:13:50.802587 [ANA_INIT] >>>>>>>>>>>>>>
600 23:13:50.806206 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 23:13:50.809940 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 23:13:50.812743 ===================================
603 23:13:50.816099 data_rate = 1600,PCW = 0X7600
604 23:13:50.816183 ===================================
605 23:13:50.823033 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 23:13:50.826080 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 23:13:50.833066 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 23:13:50.836619 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 23:13:50.839966 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 23:13:50.842890 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 23:13:50.846173 [ANA_INIT] flow start
612 23:13:50.846275 [ANA_INIT] PLL >>>>>>>>
613 23:13:50.849949 [ANA_INIT] PLL <<<<<<<<
614 23:13:50.852585 [ANA_INIT] MIDPI >>>>>>>>
615 23:13:50.856260 [ANA_INIT] MIDPI <<<<<<<<
616 23:13:50.856344 [ANA_INIT] DLL >>>>>>>>
617 23:13:50.859418 [ANA_INIT] flow end
618 23:13:50.862933 ============ LP4 DIFF to SE enter ============
619 23:13:50.866455 ============ LP4 DIFF to SE exit ============
620 23:13:50.869389 [ANA_INIT] <<<<<<<<<<<<<
621 23:13:50.873004 [Flow] Enable top DCM control >>>>>
622 23:13:50.876459 [Flow] Enable top DCM control <<<<<
623 23:13:50.879842 Enable DLL master slave shuffle
624 23:13:50.886344 ==============================================================
625 23:13:50.886450 Gating Mode config
626 23:13:50.893340 ==============================================================
627 23:13:50.893447 Config description:
628 23:13:50.902829 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 23:13:50.909832 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 23:13:50.916323 SELPH_MODE 0: By rank 1: By Phase
631 23:13:50.919937 ==============================================================
632 23:13:50.923276 GAT_TRACK_EN = 1
633 23:13:50.926409 RX_GATING_MODE = 2
634 23:13:50.929929 RX_GATING_TRACK_MODE = 2
635 23:13:50.933403 SELPH_MODE = 1
636 23:13:50.936688 PICG_EARLY_EN = 1
637 23:13:50.939621 VALID_LAT_VALUE = 1
638 23:13:50.943291 ==============================================================
639 23:13:50.946330 Enter into Gating configuration >>>>
640 23:13:50.949857 Exit from Gating configuration <<<<
641 23:13:50.953114 Enter into DVFS_PRE_config >>>>>
642 23:13:50.967013 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 23:13:50.969905 Exit from DVFS_PRE_config <<<<<
644 23:13:50.973543 Enter into PICG configuration >>>>
645 23:13:50.973946 Exit from PICG configuration <<<<
646 23:13:50.976948 [RX_INPUT] configuration >>>>>
647 23:13:50.979973 [RX_INPUT] configuration <<<<<
648 23:13:50.986993 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 23:13:50.990368 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 23:13:50.996782 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 23:13:51.003793 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 23:13:51.010001 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 23:13:51.016731 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 23:13:51.020267 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 23:13:51.023815 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 23:13:51.027552 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 23:13:51.033832 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 23:13:51.036872 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 23:13:51.040340 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 23:13:51.043794 ===================================
661 23:13:51.046847 LPDDR4 DRAM CONFIGURATION
662 23:13:51.050628 ===================================
663 23:13:51.051024 EX_ROW_EN[0] = 0x0
664 23:13:51.053996 EX_ROW_EN[1] = 0x0
665 23:13:51.054415 LP4Y_EN = 0x0
666 23:13:51.057461 WORK_FSP = 0x0
667 23:13:51.060486 WL = 0x2
668 23:13:51.060976 RL = 0x2
669 23:13:51.063926 BL = 0x2
670 23:13:51.064322 RPST = 0x0
671 23:13:51.067185 RD_PRE = 0x0
672 23:13:51.067686 WR_PRE = 0x1
673 23:13:51.070037 WR_PST = 0x0
674 23:13:51.070432 DBI_WR = 0x0
675 23:13:51.073803 DBI_RD = 0x0
676 23:13:51.074202 OTF = 0x1
677 23:13:51.077006 ===================================
678 23:13:51.080365 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 23:13:51.086825 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 23:13:51.090403 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 23:13:51.093269 ===================================
682 23:13:51.096972 LPDDR4 DRAM CONFIGURATION
683 23:13:51.100359 ===================================
684 23:13:51.100729 EX_ROW_EN[0] = 0x10
685 23:13:51.103217 EX_ROW_EN[1] = 0x0
686 23:13:51.103625 LP4Y_EN = 0x0
687 23:13:51.107016 WORK_FSP = 0x0
688 23:13:51.107381 WL = 0x2
689 23:13:51.110380 RL = 0x2
690 23:13:51.110746 BL = 0x2
691 23:13:51.113559 RPST = 0x0
692 23:13:51.113964 RD_PRE = 0x0
693 23:13:51.116847 WR_PRE = 0x1
694 23:13:51.120201 WR_PST = 0x0
695 23:13:51.120571 DBI_WR = 0x0
696 23:13:51.123552 DBI_RD = 0x0
697 23:13:51.123922 OTF = 0x1
698 23:13:51.127302 ===================================
699 23:13:51.133682 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 23:13:51.137441 nWR fixed to 40
701 23:13:51.140489 [ModeRegInit_LP4] CH0 RK0
702 23:13:51.140955 [ModeRegInit_LP4] CH0 RK1
703 23:13:51.143986 [ModeRegInit_LP4] CH1 RK0
704 23:13:51.147366 [ModeRegInit_LP4] CH1 RK1
705 23:13:51.147737 match AC timing 13
706 23:13:51.153725 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
707 23:13:51.157135 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 23:13:51.160519 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 23:13:51.167429 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 23:13:51.170488 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 23:13:51.170890 [EMI DOE] emi_dcm 0
712 23:13:51.176949 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 23:13:51.177348 ==
714 23:13:51.180219 Dram Type= 6, Freq= 0, CH_0, rank 0
715 23:13:51.184002 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
716 23:13:51.184499 ==
717 23:13:51.190436 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 23:13:51.197309 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 23:13:51.204470 [CA 0] Center 36 (6~67) winsize 62
720 23:13:51.207641 [CA 1] Center 36 (6~67) winsize 62
721 23:13:51.211651 [CA 2] Center 34 (4~65) winsize 62
722 23:13:51.214949 [CA 3] Center 33 (3~64) winsize 62
723 23:13:51.218197 [CA 4] Center 33 (3~64) winsize 62
724 23:13:51.221468 [CA 5] Center 32 (3~62) winsize 60
725 23:13:51.222016
726 23:13:51.224699 [CmdBusTrainingLP45] Vref(ca) range 1: 32
727 23:13:51.225226
728 23:13:51.227649 [CATrainingPosCal] consider 1 rank data
729 23:13:51.231129 u2DelayCellTimex100 = 270/100 ps
730 23:13:51.234502 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
731 23:13:51.238111 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
732 23:13:51.244851 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
733 23:13:51.248230 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
734 23:13:51.251210 CA4 delay=33 (3~64),Diff = 1 PI (7 cell)
735 23:13:51.254854 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
736 23:13:51.255274
737 23:13:51.257845 CA PerBit enable=1, Macro0, CA PI delay=32
738 23:13:51.258305
739 23:13:51.261172 [CBTSetCACLKResult] CA Dly = 32
740 23:13:51.261539 CS Dly: 4 (0~35)
741 23:13:51.261880 ==
742 23:13:51.264834 Dram Type= 6, Freq= 0, CH_0, rank 1
743 23:13:51.271446 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
744 23:13:51.271928 ==
745 23:13:51.274534 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 23:13:51.281570 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 23:13:51.291058 [CA 0] Center 36 (6~67) winsize 62
748 23:13:51.294235 [CA 1] Center 36 (6~67) winsize 62
749 23:13:51.297221 [CA 2] Center 34 (3~65) winsize 63
750 23:13:51.300765 [CA 3] Center 33 (3~64) winsize 62
751 23:13:51.304215 [CA 4] Center 33 (3~63) winsize 61
752 23:13:51.307814 [CA 5] Center 32 (2~63) winsize 62
753 23:13:51.308206
754 23:13:51.311225 [CmdBusTrainingLP45] Vref(ca) range 1: 32
755 23:13:51.311728
756 23:13:51.314298 [CATrainingPosCal] consider 2 rank data
757 23:13:51.317442 u2DelayCellTimex100 = 270/100 ps
758 23:13:51.321068 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
759 23:13:51.324662 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
760 23:13:51.327179 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
761 23:13:51.334304 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
762 23:13:51.337638 CA4 delay=33 (3~63),Diff = 1 PI (7 cell)
763 23:13:51.340987 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
764 23:13:51.341479
765 23:13:51.344283 CA PerBit enable=1, Macro0, CA PI delay=32
766 23:13:51.344771
767 23:13:51.347839 [CBTSetCACLKResult] CA Dly = 32
768 23:13:51.348236 CS Dly: 4 (0~36)
769 23:13:51.348554
770 23:13:51.351232 ----->DramcWriteLeveling(PI) begin...
771 23:13:51.351636 ==
772 23:13:51.354788 Dram Type= 6, Freq= 0, CH_0, rank 0
773 23:13:51.358237 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 23:13:51.361911 ==
775 23:13:51.362310 Write leveling (Byte 0): 33 => 33
776 23:13:51.365396 Write leveling (Byte 1): 29 => 29
777 23:13:51.369742 DramcWriteLeveling(PI) end<-----
778 23:13:51.370225
779 23:13:51.370542 ==
780 23:13:51.373093 Dram Type= 6, Freq= 0, CH_0, rank 0
781 23:13:51.376319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 23:13:51.376834 ==
783 23:13:51.379652 [Gating] SW mode calibration
784 23:13:51.386962 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 23:13:51.393807 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 23:13:51.396908 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 23:13:51.400023 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
788 23:13:51.403708 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
789 23:13:51.410510 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 23:13:51.413755 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 23:13:51.416795 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 23:13:51.423950 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 23:13:51.426937 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 23:13:51.430213 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 23:13:51.436798 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 23:13:51.440351 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 23:13:51.443832 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 23:13:51.450841 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 23:13:51.453511 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 23:13:51.456983 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 23:13:51.463567 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 23:13:51.466936 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 23:13:51.470784 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
804 23:13:51.477268 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
805 23:13:51.480598 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
806 23:13:51.483526 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 23:13:51.490472 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 23:13:51.494092 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 23:13:51.497550 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 23:13:51.500359 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 23:13:51.507196 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 23:13:51.510258 0 9 8 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
813 23:13:51.513442 0 9 12 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
814 23:13:51.520571 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 23:13:51.523929 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 23:13:51.527512 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 23:13:51.534034 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 23:13:51.537624 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 23:13:51.541108 0 10 4 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
820 23:13:51.547263 0 10 8 | B1->B0 | 3030 2323 | 0 0 | (0 0) (0 0)
821 23:13:51.550748 0 10 12 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
822 23:13:51.554115 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 23:13:51.560497 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 23:13:51.564103 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 23:13:51.567639 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 23:13:51.573677 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 23:13:51.577165 0 11 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
828 23:13:51.580411 0 11 8 | B1->B0 | 2b2b 3d3d | 0 1 | (0 0) (0 0)
829 23:13:51.584039 0 11 12 | B1->B0 | 4444 4646 | 1 0 | (1 1) (0 0)
830 23:13:51.590312 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 23:13:51.593940 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 23:13:51.596991 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 23:13:51.603870 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 23:13:51.607389 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 23:13:51.610734 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
836 23:13:51.617511 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
837 23:13:51.620921 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
838 23:13:51.623719 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 23:13:51.630809 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 23:13:51.634039 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 23:13:51.637750 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 23:13:51.643865 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 23:13:51.647125 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 23:13:51.650651 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 23:13:51.657629 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 23:13:51.660804 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 23:13:51.664600 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 23:13:51.667721 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 23:13:51.674636 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 23:13:51.677774 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 23:13:51.680936 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
852 23:13:51.687718 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
853 23:13:51.691375 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
854 23:13:51.694621 Total UI for P1: 0, mck2ui 16
855 23:13:51.697520 best dqsien dly found for B0: ( 0, 14, 6)
856 23:13:51.701186 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
857 23:13:51.704480 Total UI for P1: 0, mck2ui 16
858 23:13:51.708174 best dqsien dly found for B1: ( 0, 14, 10)
859 23:13:51.711448 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
860 23:13:51.714803 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
861 23:13:51.715232
862 23:13:51.718233 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
863 23:13:51.721658 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
864 23:13:51.725092 [Gating] SW calibration Done
865 23:13:51.725651 ==
866 23:13:51.728877 Dram Type= 6, Freq= 0, CH_0, rank 0
867 23:13:51.731583 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
868 23:13:51.734989 ==
869 23:13:51.735397 RX Vref Scan: 0
870 23:13:51.735716
871 23:13:51.738398 RX Vref 0 -> 0, step: 1
872 23:13:51.738814
873 23:13:51.741925 RX Delay -130 -> 252, step: 16
874 23:13:51.745420 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
875 23:13:51.748836 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
876 23:13:51.751887 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
877 23:13:51.755844 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
878 23:13:51.761805 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
879 23:13:51.765601 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
880 23:13:51.768766 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
881 23:13:51.771954 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
882 23:13:51.775431 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
883 23:13:51.778485 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
884 23:13:51.785657 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
885 23:13:51.788769 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
886 23:13:51.791952 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
887 23:13:51.795421 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
888 23:13:51.802224 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
889 23:13:51.805572 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
890 23:13:51.806049 ==
891 23:13:51.808344 Dram Type= 6, Freq= 0, CH_0, rank 0
892 23:13:51.811970 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
893 23:13:51.812404 ==
894 23:13:51.815407 DQS Delay:
895 23:13:51.815839 DQS0 = 0, DQS1 = 0
896 23:13:51.816184 DQM Delay:
897 23:13:51.818452 DQM0 = 91, DQM1 = 84
898 23:13:51.818880 DQ Delay:
899 23:13:51.822200 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =93
900 23:13:51.825705 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =101
901 23:13:51.828496 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
902 23:13:51.832353 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
903 23:13:51.832896
904 23:13:51.833240
905 23:13:51.833557 ==
906 23:13:51.835291 Dram Type= 6, Freq= 0, CH_0, rank 0
907 23:13:51.838580 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
908 23:13:51.841699 ==
909 23:13:51.842129
910 23:13:51.842474
911 23:13:51.842792 TX Vref Scan disable
912 23:13:51.845714 == TX Byte 0 ==
913 23:13:51.848615 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
914 23:13:51.855327 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
915 23:13:51.855761 == TX Byte 1 ==
916 23:13:51.858387 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
917 23:13:51.865291 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
918 23:13:51.865853 ==
919 23:13:51.868464 Dram Type= 6, Freq= 0, CH_0, rank 0
920 23:13:51.871820 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
921 23:13:51.872280 ==
922 23:13:51.884471 TX Vref=22, minBit 10, minWin=27, winSum=448
923 23:13:51.888388 TX Vref=24, minBit 9, minWin=27, winSum=451
924 23:13:51.891311 TX Vref=26, minBit 5, minWin=28, winSum=456
925 23:13:51.894737 TX Vref=28, minBit 0, minWin=28, winSum=459
926 23:13:51.898104 TX Vref=30, minBit 5, minWin=28, winSum=457
927 23:13:51.901285 TX Vref=32, minBit 6, minWin=28, winSum=455
928 23:13:51.908189 [TxChooseVref] Worse bit 0, Min win 28, Win sum 459, Final Vref 28
929 23:13:51.908624
930 23:13:51.911998 Final TX Range 1 Vref 28
931 23:13:51.912684
932 23:13:51.913041 ==
933 23:13:51.914766 Dram Type= 6, Freq= 0, CH_0, rank 0
934 23:13:51.918147 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
935 23:13:51.918576 ==
936 23:13:51.918918
937 23:13:51.919237
938 23:13:51.921742 TX Vref Scan disable
939 23:13:51.925167 == TX Byte 0 ==
940 23:13:51.928901 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
941 23:13:51.931646 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
942 23:13:51.935362 == TX Byte 1 ==
943 23:13:51.937970 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
944 23:13:51.941329 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
945 23:13:51.941805
946 23:13:51.944905 [DATLAT]
947 23:13:51.945517 Freq=800, CH0 RK0
948 23:13:51.945920
949 23:13:51.948403 DATLAT Default: 0xa
950 23:13:51.948947 0, 0xFFFF, sum = 0
951 23:13:51.951928 1, 0xFFFF, sum = 0
952 23:13:51.952477 2, 0xFFFF, sum = 0
953 23:13:51.955023 3, 0xFFFF, sum = 0
954 23:13:51.955451 4, 0xFFFF, sum = 0
955 23:13:51.958098 5, 0xFFFF, sum = 0
956 23:13:51.958533 6, 0xFFFF, sum = 0
957 23:13:51.961639 7, 0xFFFF, sum = 0
958 23:13:51.962075 8, 0xFFFF, sum = 0
959 23:13:51.964702 9, 0x0, sum = 1
960 23:13:51.965245 10, 0x0, sum = 2
961 23:13:51.968335 11, 0x0, sum = 3
962 23:13:51.968885 12, 0x0, sum = 4
963 23:13:51.971550 best_step = 10
964 23:13:51.971980
965 23:13:51.972426 ==
966 23:13:51.975024 Dram Type= 6, Freq= 0, CH_0, rank 0
967 23:13:51.978860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
968 23:13:51.979463 ==
969 23:13:51.981340 RX Vref Scan: 1
970 23:13:51.981861
971 23:13:51.982209 Set Vref Range= 32 -> 127
972 23:13:51.982529
973 23:13:51.985010 RX Vref 32 -> 127, step: 1
974 23:13:51.985435
975 23:13:51.988481 RX Delay -95 -> 252, step: 8
976 23:13:51.989012
977 23:13:51.991810 Set Vref, RX VrefLevel [Byte0]: 32
978 23:13:51.995296 [Byte1]: 32
979 23:13:51.995846
980 23:13:51.998111 Set Vref, RX VrefLevel [Byte0]: 33
981 23:13:52.001802 [Byte1]: 33
982 23:13:52.004833
983 23:13:52.005255 Set Vref, RX VrefLevel [Byte0]: 34
984 23:13:52.008404 [Byte1]: 34
985 23:13:52.012937
986 23:13:52.013436 Set Vref, RX VrefLevel [Byte0]: 35
987 23:13:52.015758 [Byte1]: 35
988 23:13:52.020521
989 23:13:52.021049 Set Vref, RX VrefLevel [Byte0]: 36
990 23:13:52.024312 [Byte1]: 36
991 23:13:52.028424
992 23:13:52.028850 Set Vref, RX VrefLevel [Byte0]: 37
993 23:13:52.031991 [Byte1]: 37
994 23:13:52.035957
995 23:13:52.036637 Set Vref, RX VrefLevel [Byte0]: 38
996 23:13:52.039079 [Byte1]: 38
997 23:13:52.043671
998 23:13:52.044225 Set Vref, RX VrefLevel [Byte0]: 39
999 23:13:52.046754 [Byte1]: 39
1000 23:13:52.051169
1001 23:13:52.051616 Set Vref, RX VrefLevel [Byte0]: 40
1002 23:13:52.054030 [Byte1]: 40
1003 23:13:52.058139
1004 23:13:52.058562 Set Vref, RX VrefLevel [Byte0]: 41
1005 23:13:52.061461 [Byte1]: 41
1006 23:13:52.065427
1007 23:13:52.065966 Set Vref, RX VrefLevel [Byte0]: 42
1008 23:13:52.068914 [Byte1]: 42
1009 23:13:52.073130
1010 23:13:52.073555 Set Vref, RX VrefLevel [Byte0]: 43
1011 23:13:52.076533 [Byte1]: 43
1012 23:13:52.081142
1013 23:13:52.081706 Set Vref, RX VrefLevel [Byte0]: 44
1014 23:13:52.084555 [Byte1]: 44
1015 23:13:52.088551
1016 23:13:52.088973 Set Vref, RX VrefLevel [Byte0]: 45
1017 23:13:52.092079 [Byte1]: 45
1018 23:13:52.096007
1019 23:13:52.096574 Set Vref, RX VrefLevel [Byte0]: 46
1020 23:13:52.099163 [Byte1]: 46
1021 23:13:52.103865
1022 23:13:52.104290 Set Vref, RX VrefLevel [Byte0]: 47
1023 23:13:52.106796 [Byte1]: 47
1024 23:13:52.111608
1025 23:13:52.112146 Set Vref, RX VrefLevel [Byte0]: 48
1026 23:13:52.114854 [Byte1]: 48
1027 23:13:52.119258
1028 23:13:52.119782 Set Vref, RX VrefLevel [Byte0]: 49
1029 23:13:52.122098 [Byte1]: 49
1030 23:13:52.126648
1031 23:13:52.127064 Set Vref, RX VrefLevel [Byte0]: 50
1032 23:13:52.129651 [Byte1]: 50
1033 23:13:52.134097
1034 23:13:52.134534 Set Vref, RX VrefLevel [Byte0]: 51
1035 23:13:52.137347 [Byte1]: 51
1036 23:13:52.141907
1037 23:13:52.142324 Set Vref, RX VrefLevel [Byte0]: 52
1038 23:13:52.144815 [Byte1]: 52
1039 23:13:52.149705
1040 23:13:52.150253 Set Vref, RX VrefLevel [Byte0]: 53
1041 23:13:52.152929 [Byte1]: 53
1042 23:13:52.157273
1043 23:13:52.157847 Set Vref, RX VrefLevel [Byte0]: 54
1044 23:13:52.160136 [Byte1]: 54
1045 23:13:52.164713
1046 23:13:52.165215 Set Vref, RX VrefLevel [Byte0]: 55
1047 23:13:52.167824 [Byte1]: 55
1048 23:13:52.171953
1049 23:13:52.172371 Set Vref, RX VrefLevel [Byte0]: 56
1050 23:13:52.175481 [Byte1]: 56
1051 23:13:52.179585
1052 23:13:52.180002 Set Vref, RX VrefLevel [Byte0]: 57
1053 23:13:52.183058 [Byte1]: 57
1054 23:13:52.187687
1055 23:13:52.188199 Set Vref, RX VrefLevel [Byte0]: 58
1056 23:13:52.190409 [Byte1]: 58
1057 23:13:52.194992
1058 23:13:52.195516 Set Vref, RX VrefLevel [Byte0]: 59
1059 23:13:52.198290 [Byte1]: 59
1060 23:13:52.202509
1061 23:13:52.203034 Set Vref, RX VrefLevel [Byte0]: 60
1062 23:13:52.205493 [Byte1]: 60
1063 23:13:52.209939
1064 23:13:52.210356 Set Vref, RX VrefLevel [Byte0]: 61
1065 23:13:52.213939 [Byte1]: 61
1066 23:13:52.217627
1067 23:13:52.218067 Set Vref, RX VrefLevel [Byte0]: 62
1068 23:13:52.221517 [Byte1]: 62
1069 23:13:52.225469
1070 23:13:52.226062 Set Vref, RX VrefLevel [Byte0]: 63
1071 23:13:52.228632 [Byte1]: 63
1072 23:13:52.232870
1073 23:13:52.233324 Set Vref, RX VrefLevel [Byte0]: 64
1074 23:13:52.236135 [Byte1]: 64
1075 23:13:52.240276
1076 23:13:52.240703 Set Vref, RX VrefLevel [Byte0]: 65
1077 23:13:52.243873 [Byte1]: 65
1078 23:13:52.248060
1079 23:13:52.248599 Set Vref, RX VrefLevel [Byte0]: 66
1080 23:13:52.251677 [Byte1]: 66
1081 23:13:52.256060
1082 23:13:52.256595 Set Vref, RX VrefLevel [Byte0]: 67
1083 23:13:52.258860 [Byte1]: 67
1084 23:13:52.263682
1085 23:13:52.264192 Set Vref, RX VrefLevel [Byte0]: 68
1086 23:13:52.266665 [Byte1]: 68
1087 23:13:52.270905
1088 23:13:52.271486 Set Vref, RX VrefLevel [Byte0]: 69
1089 23:13:52.274298 [Byte1]: 69
1090 23:13:52.278419
1091 23:13:52.278833 Set Vref, RX VrefLevel [Byte0]: 70
1092 23:13:52.282004 [Byte1]: 70
1093 23:13:52.285882
1094 23:13:52.286309 Set Vref, RX VrefLevel [Byte0]: 71
1095 23:13:52.289738 [Byte1]: 71
1096 23:13:52.294238
1097 23:13:52.294841 Set Vref, RX VrefLevel [Byte0]: 72
1098 23:13:52.296892 [Byte1]: 72
1099 23:13:52.301204
1100 23:13:52.301651 Set Vref, RX VrefLevel [Byte0]: 73
1101 23:13:52.304721 [Byte1]: 73
1102 23:13:52.308924
1103 23:13:52.309351 Set Vref, RX VrefLevel [Byte0]: 74
1104 23:13:52.312354 [Byte1]: 74
1105 23:13:52.316242
1106 23:13:52.316663 Set Vref, RX VrefLevel [Byte0]: 75
1107 23:13:52.320213 [Byte1]: 75
1108 23:13:52.324306
1109 23:13:52.324820 Set Vref, RX VrefLevel [Byte0]: 76
1110 23:13:52.327275 [Byte1]: 76
1111 23:13:52.331694
1112 23:13:52.332215 Final RX Vref Byte 0 = 55 to rank0
1113 23:13:52.334911 Final RX Vref Byte 1 = 56 to rank0
1114 23:13:52.338613 Final RX Vref Byte 0 = 55 to rank1
1115 23:13:52.342020 Final RX Vref Byte 1 = 56 to rank1==
1116 23:13:52.344990 Dram Type= 6, Freq= 0, CH_0, rank 0
1117 23:13:52.351741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1118 23:13:52.352164 ==
1119 23:13:52.352501 DQS Delay:
1120 23:13:52.352811 DQS0 = 0, DQS1 = 0
1121 23:13:52.354845 DQM Delay:
1122 23:13:52.355263 DQM0 = 91, DQM1 = 85
1123 23:13:52.358398 DQ Delay:
1124 23:13:52.361498 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88
1125 23:13:52.365016 DQ4 =92, DQ5 =80, DQ6 =100, DQ7 =100
1126 23:13:52.368351 DQ8 =72, DQ9 =76, DQ10 =84, DQ11 =76
1127 23:13:52.371620 DQ12 =92, DQ13 =92, DQ14 =96, DQ15 =92
1128 23:13:52.372033
1129 23:13:52.372441
1130 23:13:52.378494 [DQSOSCAuto] RK0, (LSB)MR18= 0x493f, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 391 ps
1131 23:13:52.381979 CH0 RK0: MR19=606, MR18=493F
1132 23:13:52.388658 CH0_RK0: MR19=0x606, MR18=0x493F, DQSOSC=391, MR23=63, INC=96, DEC=64
1133 23:13:52.389211
1134 23:13:52.392325 ----->DramcWriteLeveling(PI) begin...
1135 23:13:52.392843 ==
1136 23:13:52.395615 Dram Type= 6, Freq= 0, CH_0, rank 1
1137 23:13:52.398249 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1138 23:13:52.398667 ==
1139 23:13:52.401770 Write leveling (Byte 0): 33 => 33
1140 23:13:52.405551 Write leveling (Byte 1): 28 => 28
1141 23:13:52.408453 DramcWriteLeveling(PI) end<-----
1142 23:13:52.408916
1143 23:13:52.409250 ==
1144 23:13:52.412168 Dram Type= 6, Freq= 0, CH_0, rank 1
1145 23:13:52.415315 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1146 23:13:52.415739 ==
1147 23:13:52.418230 [Gating] SW mode calibration
1148 23:13:52.425090 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1149 23:13:52.469048 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1150 23:13:52.469570 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1151 23:13:52.469980 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1152 23:13:52.470645 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1153 23:13:52.470989 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1154 23:13:52.471289 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 23:13:52.471580 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 23:13:52.471954 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 23:13:52.472324 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 23:13:52.472683 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 23:13:52.513380 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 23:13:52.513977 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 23:13:52.514654 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 23:13:52.514992 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 23:13:52.515313 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 23:13:52.515683 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 23:13:52.515998 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 23:13:52.516344 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 23:13:52.516645 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1168 23:13:52.516927 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1169 23:13:52.557396 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1170 23:13:52.558329 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 23:13:52.558689 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 23:13:52.559002 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 23:13:52.559301 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 23:13:52.559645 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 23:13:52.559946 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 23:13:52.560228 0 9 8 | B1->B0 | 2e2e 2c2b | 0 1 | (0 0) (0 0)
1177 23:13:52.560564 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1178 23:13:52.560853 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1179 23:13:52.569441 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1180 23:13:52.570011 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1181 23:13:52.572434 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1182 23:13:52.575622 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1183 23:13:52.578832 0 10 4 | B1->B0 | 3434 3434 | 0 0 | (0 0) (0 0)
1184 23:13:52.585411 0 10 8 | B1->B0 | 2929 2828 | 0 0 | (1 0) (1 0)
1185 23:13:52.589203 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 23:13:52.592293 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 23:13:52.599446 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 23:13:52.602782 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 23:13:52.606809 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 23:13:52.610096 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 23:13:52.613514 0 11 4 | B1->B0 | 2626 2727 | 0 0 | (0 0) (0 0)
1192 23:13:52.620344 0 11 8 | B1->B0 | 3b3b 3a3a | 0 0 | (0 0) (0 0)
1193 23:13:52.623972 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1194 23:13:52.627859 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1195 23:13:52.634547 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1196 23:13:52.637733 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1197 23:13:52.641274 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1198 23:13:52.644643 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1199 23:13:52.651517 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1200 23:13:52.654829 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1201 23:13:52.657743 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1202 23:13:52.665036 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 23:13:52.668743 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 23:13:52.671278 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 23:13:52.678536 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 23:13:52.681781 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 23:13:52.685175 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 23:13:52.691911 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 23:13:52.695042 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 23:13:52.698319 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 23:13:52.701642 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 23:13:52.708386 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 23:13:52.711823 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 23:13:52.714778 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 23:13:52.721694 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 23:13:52.725326 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1217 23:13:52.728174 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1218 23:13:52.731568 Total UI for P1: 0, mck2ui 16
1219 23:13:52.735193 best dqsien dly found for B0: ( 0, 14, 8)
1220 23:13:52.738418 Total UI for P1: 0, mck2ui 16
1221 23:13:52.742064 best dqsien dly found for B1: ( 0, 14, 8)
1222 23:13:52.745402 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1223 23:13:52.748472 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1224 23:13:52.748881
1225 23:13:52.751961 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1226 23:13:52.758759 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1227 23:13:52.759239 [Gating] SW calibration Done
1228 23:13:52.759567 ==
1229 23:13:52.761707 Dram Type= 6, Freq= 0, CH_0, rank 1
1230 23:13:52.768993 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1231 23:13:52.769514 ==
1232 23:13:52.769903 RX Vref Scan: 0
1233 23:13:52.770214
1234 23:13:52.772538 RX Vref 0 -> 0, step: 1
1235 23:13:52.773038
1236 23:13:52.775262 RX Delay -130 -> 252, step: 16
1237 23:13:52.778881 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1238 23:13:52.782631 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1239 23:13:52.785335 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
1240 23:13:52.788755 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1241 23:13:52.795510 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1242 23:13:52.798923 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1243 23:13:52.802334 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1244 23:13:52.805562 iDelay=222, Bit 7, Center 109 (-2 ~ 221) 224
1245 23:13:52.809009 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1246 23:13:52.815828 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1247 23:13:52.819361 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1248 23:13:52.822075 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1249 23:13:52.825497 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1250 23:13:52.831959 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1251 23:13:52.835180 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1252 23:13:52.838330 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1253 23:13:52.838743 ==
1254 23:13:52.841915 Dram Type= 6, Freq= 0, CH_0, rank 1
1255 23:13:52.845264 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1256 23:13:52.845716 ==
1257 23:13:52.848807 DQS Delay:
1258 23:13:52.849324 DQS0 = 0, DQS1 = 0
1259 23:13:52.852069 DQM Delay:
1260 23:13:52.852607 DQM0 = 95, DQM1 = 83
1261 23:13:52.853030 DQ Delay:
1262 23:13:52.855438 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =93
1263 23:13:52.859008 DQ4 =93, DQ5 =85, DQ6 =101, DQ7 =109
1264 23:13:52.861987 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =77
1265 23:13:52.865084 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1266 23:13:52.865496
1267 23:13:52.865887
1268 23:13:52.866198 ==
1269 23:13:52.868998 Dram Type= 6, Freq= 0, CH_0, rank 1
1270 23:13:52.875298 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1271 23:13:52.875732 ==
1272 23:13:52.876061
1273 23:13:52.876367
1274 23:13:52.876658 TX Vref Scan disable
1275 23:13:52.879186 == TX Byte 0 ==
1276 23:13:52.882657 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1277 23:13:52.885613 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1278 23:13:52.888947 == TX Byte 1 ==
1279 23:13:52.892377 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1280 23:13:52.895764 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1281 23:13:52.899202 ==
1282 23:13:52.902826 Dram Type= 6, Freq= 0, CH_0, rank 1
1283 23:13:52.905617 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1284 23:13:52.906050 ==
1285 23:13:52.919402 TX Vref=22, minBit 13, minWin=27, winSum=449
1286 23:13:52.922305 TX Vref=24, minBit 12, minWin=27, winSum=454
1287 23:13:52.925698 TX Vref=26, minBit 1, minWin=28, winSum=455
1288 23:13:52.928893 TX Vref=28, minBit 5, minWin=28, winSum=458
1289 23:13:52.932283 TX Vref=30, minBit 7, minWin=28, winSum=459
1290 23:13:52.938694 TX Vref=32, minBit 2, minWin=28, winSum=457
1291 23:13:52.942129 [TxChooseVref] Worse bit 7, Min win 28, Win sum 459, Final Vref 30
1292 23:13:52.942605
1293 23:13:52.945320 Final TX Range 1 Vref 30
1294 23:13:52.945893
1295 23:13:52.946227 ==
1296 23:13:52.948536 Dram Type= 6, Freq= 0, CH_0, rank 1
1297 23:13:52.951786 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1298 23:13:52.955482 ==
1299 23:13:52.955895
1300 23:13:52.956214
1301 23:13:52.956578 TX Vref Scan disable
1302 23:13:52.958709 == TX Byte 0 ==
1303 23:13:52.962209 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1304 23:13:52.968698 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1305 23:13:52.969112 == TX Byte 1 ==
1306 23:13:52.972013 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1307 23:13:52.975349 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1308 23:13:52.978667
1309 23:13:52.978992 [DATLAT]
1310 23:13:52.979227 Freq=800, CH0 RK1
1311 23:13:52.979450
1312 23:13:52.982230 DATLAT Default: 0xa
1313 23:13:52.982695 0, 0xFFFF, sum = 0
1314 23:13:52.985533 1, 0xFFFF, sum = 0
1315 23:13:52.985855 2, 0xFFFF, sum = 0
1316 23:13:52.988739 3, 0xFFFF, sum = 0
1317 23:13:52.989036 4, 0xFFFF, sum = 0
1318 23:13:52.992348 5, 0xFFFF, sum = 0
1319 23:13:52.995504 6, 0xFFFF, sum = 0
1320 23:13:52.995896 7, 0xFFFF, sum = 0
1321 23:13:52.998944 8, 0xFFFF, sum = 0
1322 23:13:52.999315 9, 0x0, sum = 1
1323 23:13:52.999561 10, 0x0, sum = 2
1324 23:13:53.002002 11, 0x0, sum = 3
1325 23:13:53.002300 12, 0x0, sum = 4
1326 23:13:53.005722 best_step = 10
1327 23:13:53.006096
1328 23:13:53.006336 ==
1329 23:13:53.009039 Dram Type= 6, Freq= 0, CH_0, rank 1
1330 23:13:53.012299 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1331 23:13:53.012684 ==
1332 23:13:53.015810 RX Vref Scan: 0
1333 23:13:53.016222
1334 23:13:53.016549 RX Vref 0 -> 0, step: 1
1335 23:13:53.016855
1336 23:13:53.019209 RX Delay -95 -> 252, step: 8
1337 23:13:53.025876 iDelay=209, Bit 0, Center 92 (-15 ~ 200) 216
1338 23:13:53.029684 iDelay=209, Bit 1, Center 96 (-7 ~ 200) 208
1339 23:13:53.032651 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1340 23:13:53.036247 iDelay=209, Bit 3, Center 88 (-23 ~ 200) 224
1341 23:13:53.038934 iDelay=209, Bit 4, Center 96 (-15 ~ 208) 224
1342 23:13:53.046138 iDelay=209, Bit 5, Center 84 (-23 ~ 192) 216
1343 23:13:53.049505 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1344 23:13:53.052893 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1345 23:13:53.055813 iDelay=209, Bit 8, Center 76 (-31 ~ 184) 216
1346 23:13:53.058885 iDelay=209, Bit 9, Center 76 (-31 ~ 184) 216
1347 23:13:53.066073 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1348 23:13:53.068831 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1349 23:13:53.072693 iDelay=209, Bit 12, Center 88 (-15 ~ 192) 208
1350 23:13:53.075433 iDelay=209, Bit 13, Center 92 (-15 ~ 200) 216
1351 23:13:53.079136 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1352 23:13:53.086011 iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216
1353 23:13:53.086429 ==
1354 23:13:53.088977 Dram Type= 6, Freq= 0, CH_0, rank 1
1355 23:13:53.092712 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1356 23:13:53.093232 ==
1357 23:13:53.093625 DQS Delay:
1358 23:13:53.095997 DQS0 = 0, DQS1 = 0
1359 23:13:53.096409 DQM Delay:
1360 23:13:53.098900 DQM0 = 93, DQM1 = 84
1361 23:13:53.099313 DQ Delay:
1362 23:13:53.102894 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1363 23:13:53.106156 DQ4 =96, DQ5 =84, DQ6 =100, DQ7 =100
1364 23:13:53.108846 DQ8 =76, DQ9 =76, DQ10 =84, DQ11 =76
1365 23:13:53.112502 DQ12 =88, DQ13 =92, DQ14 =92, DQ15 =92
1366 23:13:53.112998
1367 23:13:53.113401
1368 23:13:53.118934 [DQSOSCAuto] RK1, (LSB)MR18= 0x4112, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 393 ps
1369 23:13:53.122439 CH0 RK1: MR19=606, MR18=4112
1370 23:13:53.129290 CH0_RK1: MR19=0x606, MR18=0x4112, DQSOSC=393, MR23=63, INC=95, DEC=63
1371 23:13:53.132420 [RxdqsGatingPostProcess] freq 800
1372 23:13:53.139182 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1373 23:13:53.142475 Pre-setting of DQS Precalculation
1374 23:13:53.146184 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1375 23:13:53.146604 ==
1376 23:13:53.149427 Dram Type= 6, Freq= 0, CH_1, rank 0
1377 23:13:53.152647 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1378 23:13:53.153091 ==
1379 23:13:53.159953 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1380 23:13:53.165879 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1381 23:13:53.173930 [CA 0] Center 36 (6~67) winsize 62
1382 23:13:53.177380 [CA 1] Center 36 (6~67) winsize 62
1383 23:13:53.181163 [CA 2] Center 35 (4~66) winsize 63
1384 23:13:53.183880 [CA 3] Center 34 (4~65) winsize 62
1385 23:13:53.187354 [CA 4] Center 35 (5~65) winsize 61
1386 23:13:53.190917 [CA 5] Center 34 (4~65) winsize 62
1387 23:13:53.191380
1388 23:13:53.194238 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1389 23:13:53.194928
1390 23:13:53.197804 [CATrainingPosCal] consider 1 rank data
1391 23:13:53.201198 u2DelayCellTimex100 = 270/100 ps
1392 23:13:53.204393 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1393 23:13:53.207463 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1394 23:13:53.215128 CA2 delay=35 (4~66),Diff = 1 PI (7 cell)
1395 23:13:53.217339 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1396 23:13:53.221154 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1397 23:13:53.224497 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1398 23:13:53.225015
1399 23:13:53.228035 CA PerBit enable=1, Macro0, CA PI delay=34
1400 23:13:53.228543
1401 23:13:53.231212 [CBTSetCACLKResult] CA Dly = 34
1402 23:13:53.231622 CS Dly: 6 (0~37)
1403 23:13:53.231951 ==
1404 23:13:53.234988 Dram Type= 6, Freq= 0, CH_1, rank 1
1405 23:13:53.241041 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1406 23:13:53.241456 ==
1407 23:13:53.244516 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1408 23:13:53.250752 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1409 23:13:53.260880 [CA 0] Center 36 (6~67) winsize 62
1410 23:13:53.264353 [CA 1] Center 37 (6~68) winsize 63
1411 23:13:53.268207 [CA 2] Center 35 (4~66) winsize 63
1412 23:13:53.272367 [CA 3] Center 34 (4~65) winsize 62
1413 23:13:53.275717 [CA 4] Center 35 (5~66) winsize 62
1414 23:13:53.276129 [CA 5] Center 34 (4~65) winsize 62
1415 23:13:53.276459
1416 23:13:53.279620 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1417 23:13:53.280036
1418 23:13:53.283570 [CATrainingPosCal] consider 2 rank data
1419 23:13:53.287801 u2DelayCellTimex100 = 270/100 ps
1420 23:13:53.291181 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1421 23:13:53.295466 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1422 23:13:53.298987 CA2 delay=35 (4~66),Diff = 1 PI (7 cell)
1423 23:13:53.301974 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1424 23:13:53.305942 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1425 23:13:53.308521 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1426 23:13:53.308937
1427 23:13:53.312117 CA PerBit enable=1, Macro0, CA PI delay=34
1428 23:13:53.312530
1429 23:13:53.315604 [CBTSetCACLKResult] CA Dly = 34
1430 23:13:53.319021 CS Dly: 6 (0~38)
1431 23:13:53.319434
1432 23:13:53.322014 ----->DramcWriteLeveling(PI) begin...
1433 23:13:53.322436 ==
1434 23:13:53.325463 Dram Type= 6, Freq= 0, CH_1, rank 0
1435 23:13:53.328895 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1436 23:13:53.329312 ==
1437 23:13:53.332296 Write leveling (Byte 0): 28 => 28
1438 23:13:53.335264 Write leveling (Byte 1): 28 => 28
1439 23:13:53.338767 DramcWriteLeveling(PI) end<-----
1440 23:13:53.339182
1441 23:13:53.339512 ==
1442 23:13:53.341684 Dram Type= 6, Freq= 0, CH_1, rank 0
1443 23:13:53.345193 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1444 23:13:53.345684 ==
1445 23:13:53.348307 [Gating] SW mode calibration
1446 23:13:53.355462 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1447 23:13:53.362198 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1448 23:13:53.365399 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1449 23:13:53.372119 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1450 23:13:53.375181 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1451 23:13:53.378619 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1452 23:13:53.382054 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 23:13:53.388980 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 23:13:53.391970 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 23:13:53.395630 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 23:13:53.402088 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 23:13:53.405485 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 23:13:53.408847 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 23:13:53.416124 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 23:13:53.418725 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 23:13:53.421936 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 23:13:53.428911 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 23:13:53.431919 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 23:13:53.435864 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1465 23:13:53.442018 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1466 23:13:53.445615 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 23:13:53.448878 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 23:13:53.455852 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 23:13:53.459195 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 23:13:53.462508 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 23:13:53.465364 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 23:13:53.472517 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 23:13:53.475433 0 9 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1474 23:13:53.479160 0 9 8 | B1->B0 | 2f2f 3434 | 0 0 | (0 0) (1 1)
1475 23:13:53.485504 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1476 23:13:53.488939 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1477 23:13:53.491947 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1478 23:13:53.498974 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1479 23:13:53.502019 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1480 23:13:53.505694 0 10 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
1481 23:13:53.511979 0 10 4 | B1->B0 | 3333 2d2d | 0 0 | (0 0) (1 0)
1482 23:13:53.515381 0 10 8 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
1483 23:13:53.519098 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 23:13:53.525800 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 23:13:53.528907 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 23:13:53.532319 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 23:13:53.539203 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 23:13:53.542106 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 23:13:53.545609 0 11 4 | B1->B0 | 2b2b 3a3a | 0 0 | (0 0) (0 0)
1490 23:13:53.549160 0 11 8 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
1491 23:13:53.555489 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1492 23:13:53.558405 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1493 23:13:53.565466 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1494 23:13:53.568393 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1495 23:13:53.571888 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1496 23:13:53.575474 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1497 23:13:53.581826 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1498 23:13:53.585244 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1499 23:13:53.588759 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1500 23:13:53.595191 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 23:13:53.598153 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 23:13:53.601666 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 23:13:53.608462 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 23:13:53.612023 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 23:13:53.615138 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 23:13:53.621620 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 23:13:53.625234 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 23:13:53.628701 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 23:13:53.635657 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 23:13:53.639037 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 23:13:53.642224 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 23:13:53.648771 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1513 23:13:53.652157 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1514 23:13:53.655601 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1515 23:13:53.658766 Total UI for P1: 0, mck2ui 16
1516 23:13:53.662331 best dqsien dly found for B0: ( 0, 14, 4)
1517 23:13:53.665207 Total UI for P1: 0, mck2ui 16
1518 23:13:53.668441 best dqsien dly found for B1: ( 0, 14, 2)
1519 23:13:53.672363 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1520 23:13:53.675369 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1521 23:13:53.675908
1522 23:13:53.678890 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1523 23:13:53.682550 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1524 23:13:53.685459 [Gating] SW calibration Done
1525 23:13:53.685991 ==
1526 23:13:53.689158 Dram Type= 6, Freq= 0, CH_1, rank 0
1527 23:13:53.695949 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1528 23:13:53.696508 ==
1529 23:13:53.696851 RX Vref Scan: 0
1530 23:13:53.697165
1531 23:13:53.698855 RX Vref 0 -> 0, step: 1
1532 23:13:53.699274
1533 23:13:53.701914 RX Delay -130 -> 252, step: 16
1534 23:13:53.705405 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1535 23:13:53.708896 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1536 23:13:53.712406 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1537 23:13:53.715233 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1538 23:13:53.722373 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1539 23:13:53.725881 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1540 23:13:53.728942 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1541 23:13:53.732143 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1542 23:13:53.735513 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1543 23:13:53.741966 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1544 23:13:53.745433 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1545 23:13:53.748839 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1546 23:13:53.752453 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1547 23:13:53.755225 iDelay=222, Bit 13, Center 101 (-2 ~ 205) 208
1548 23:13:53.762371 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1549 23:13:53.765317 iDelay=222, Bit 15, Center 101 (-2 ~ 205) 208
1550 23:13:53.765771 ==
1551 23:13:53.768936 Dram Type= 6, Freq= 0, CH_1, rank 0
1552 23:13:53.772134 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1553 23:13:53.772593 ==
1554 23:13:53.775256 DQS Delay:
1555 23:13:53.775696 DQS0 = 0, DQS1 = 0
1556 23:13:53.776042 DQM Delay:
1557 23:13:53.779613 DQM0 = 93, DQM1 = 89
1558 23:13:53.780128 DQ Delay:
1559 23:13:53.782477 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1560 23:13:53.785305 DQ4 =93, DQ5 =109, DQ6 =101, DQ7 =93
1561 23:13:53.788692 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =85
1562 23:13:53.792244 DQ12 =93, DQ13 =101, DQ14 =93, DQ15 =101
1563 23:13:53.792667
1564 23:13:53.792999
1565 23:13:53.793312 ==
1566 23:13:53.795262 Dram Type= 6, Freq= 0, CH_1, rank 0
1567 23:13:53.801811 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1568 23:13:53.802237 ==
1569 23:13:53.802597
1570 23:13:53.802917
1571 23:13:53.803222 TX Vref Scan disable
1572 23:13:53.806004 == TX Byte 0 ==
1573 23:13:53.808891 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1574 23:13:53.812596 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1575 23:13:53.815628 == TX Byte 1 ==
1576 23:13:53.819107 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1577 23:13:53.822792 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1578 23:13:53.825821 ==
1579 23:13:53.829322 Dram Type= 6, Freq= 0, CH_1, rank 0
1580 23:13:53.833160 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1581 23:13:53.833735 ==
1582 23:13:53.845264 TX Vref=22, minBit 5, minWin=26, winSum=441
1583 23:13:53.849208 TX Vref=24, minBit 1, minWin=27, winSum=441
1584 23:13:53.852352 TX Vref=26, minBit 1, minWin=27, winSum=447
1585 23:13:53.855377 TX Vref=28, minBit 1, minWin=27, winSum=450
1586 23:13:53.859247 TX Vref=30, minBit 1, minWin=27, winSum=450
1587 23:13:53.862880 TX Vref=32, minBit 1, minWin=27, winSum=451
1588 23:13:53.869631 [TxChooseVref] Worse bit 1, Min win 27, Win sum 451, Final Vref 32
1589 23:13:53.870154
1590 23:13:53.872409 Final TX Range 1 Vref 32
1591 23:13:53.872830
1592 23:13:53.873205 ==
1593 23:13:53.875850 Dram Type= 6, Freq= 0, CH_1, rank 0
1594 23:13:53.878644 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1595 23:13:53.879074 ==
1596 23:13:53.879412
1597 23:13:53.879724
1598 23:13:53.882411 TX Vref Scan disable
1599 23:13:53.885334 == TX Byte 0 ==
1600 23:13:53.888821 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1601 23:13:53.892536 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1602 23:13:53.895552 == TX Byte 1 ==
1603 23:13:53.898663 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1604 23:13:53.902164 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1605 23:13:53.902593
1606 23:13:53.905795 [DATLAT]
1607 23:13:53.906317 Freq=800, CH1 RK0
1608 23:13:53.906659
1609 23:13:53.908892 DATLAT Default: 0xa
1610 23:13:53.909314 0, 0xFFFF, sum = 0
1611 23:13:53.912331 1, 0xFFFF, sum = 0
1612 23:13:53.912759 2, 0xFFFF, sum = 0
1613 23:13:53.915535 3, 0xFFFF, sum = 0
1614 23:13:53.916114 4, 0xFFFF, sum = 0
1615 23:13:53.918745 5, 0xFFFF, sum = 0
1616 23:13:53.919169 6, 0xFFFF, sum = 0
1617 23:13:53.922488 7, 0xFFFF, sum = 0
1618 23:13:53.922914 8, 0xFFFF, sum = 0
1619 23:13:53.925495 9, 0x0, sum = 1
1620 23:13:53.926006 10, 0x0, sum = 2
1621 23:13:53.928763 11, 0x0, sum = 3
1622 23:13:53.929186 12, 0x0, sum = 4
1623 23:13:53.932065 best_step = 10
1624 23:13:53.932514
1625 23:13:53.932851 ==
1626 23:13:53.935840 Dram Type= 6, Freq= 0, CH_1, rank 0
1627 23:13:53.938398 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1628 23:13:53.938820 ==
1629 23:13:53.939157 RX Vref Scan: 1
1630 23:13:53.941964
1631 23:13:53.942398 Set Vref Range= 32 -> 127
1632 23:13:53.942738
1633 23:13:53.945461 RX Vref 32 -> 127, step: 1
1634 23:13:53.945930
1635 23:13:53.949009 RX Delay -79 -> 252, step: 8
1636 23:13:53.949429
1637 23:13:53.952080 Set Vref, RX VrefLevel [Byte0]: 32
1638 23:13:53.955472 [Byte1]: 32
1639 23:13:53.955896
1640 23:13:53.958897 Set Vref, RX VrefLevel [Byte0]: 33
1641 23:13:53.962034 [Byte1]: 33
1642 23:13:53.962551
1643 23:13:53.965703 Set Vref, RX VrefLevel [Byte0]: 34
1644 23:13:53.968937 [Byte1]: 34
1645 23:13:53.972614
1646 23:13:53.973147 Set Vref, RX VrefLevel [Byte0]: 35
1647 23:13:53.975524 [Byte1]: 35
1648 23:13:53.979953
1649 23:13:53.980551 Set Vref, RX VrefLevel [Byte0]: 36
1650 23:13:53.983668 [Byte1]: 36
1651 23:13:53.987497
1652 23:13:53.990522 Set Vref, RX VrefLevel [Byte0]: 37
1653 23:13:53.990938 [Byte1]: 37
1654 23:13:53.995288
1655 23:13:53.995796 Set Vref, RX VrefLevel [Byte0]: 38
1656 23:13:53.998034 [Byte1]: 38
1657 23:13:54.002807
1658 23:13:54.003231 Set Vref, RX VrefLevel [Byte0]: 39
1659 23:13:54.006109 [Byte1]: 39
1660 23:13:54.009961
1661 23:13:54.010377 Set Vref, RX VrefLevel [Byte0]: 40
1662 23:13:54.013421 [Byte1]: 40
1663 23:13:54.018186
1664 23:13:54.018696 Set Vref, RX VrefLevel [Byte0]: 41
1665 23:13:54.020995 [Byte1]: 41
1666 23:13:54.025030
1667 23:13:54.025444 Set Vref, RX VrefLevel [Byte0]: 42
1668 23:13:54.028856 [Byte1]: 42
1669 23:13:54.032639
1670 23:13:54.033079 Set Vref, RX VrefLevel [Byte0]: 43
1671 23:13:54.036411 [Byte1]: 43
1672 23:13:54.040397
1673 23:13:54.040977 Set Vref, RX VrefLevel [Byte0]: 44
1674 23:13:54.043527 [Byte1]: 44
1675 23:13:54.047848
1676 23:13:54.048283 Set Vref, RX VrefLevel [Byte0]: 45
1677 23:13:54.051375 [Byte1]: 45
1678 23:13:54.055473
1679 23:13:54.055887 Set Vref, RX VrefLevel [Byte0]: 46
1680 23:13:54.058556 [Byte1]: 46
1681 23:13:54.063288
1682 23:13:54.063811 Set Vref, RX VrefLevel [Byte0]: 47
1683 23:13:54.065957 [Byte1]: 47
1684 23:13:54.070757
1685 23:13:54.071297 Set Vref, RX VrefLevel [Byte0]: 48
1686 23:13:54.073793 [Byte1]: 48
1687 23:13:54.078209
1688 23:13:54.078620 Set Vref, RX VrefLevel [Byte0]: 49
1689 23:13:54.081401 [Byte1]: 49
1690 23:13:54.085458
1691 23:13:54.086015 Set Vref, RX VrefLevel [Byte0]: 50
1692 23:13:54.089049 [Byte1]: 50
1693 23:13:54.093562
1694 23:13:54.094129 Set Vref, RX VrefLevel [Byte0]: 51
1695 23:13:54.096314 [Byte1]: 51
1696 23:13:54.100375
1697 23:13:54.100787 Set Vref, RX VrefLevel [Byte0]: 52
1698 23:13:54.103823 [Byte1]: 52
1699 23:13:54.108533
1700 23:13:54.109075 Set Vref, RX VrefLevel [Byte0]: 53
1701 23:13:54.111506 [Byte1]: 53
1702 23:13:54.115801
1703 23:13:54.116213 Set Vref, RX VrefLevel [Byte0]: 54
1704 23:13:54.119232 [Byte1]: 54
1705 23:13:54.123168
1706 23:13:54.123619 Set Vref, RX VrefLevel [Byte0]: 55
1707 23:13:54.126457 [Byte1]: 55
1708 23:13:54.131245
1709 23:13:54.131840 Set Vref, RX VrefLevel [Byte0]: 56
1710 23:13:54.133975 [Byte1]: 56
1711 23:13:54.138944
1712 23:13:54.139459 Set Vref, RX VrefLevel [Byte0]: 57
1713 23:13:54.141558 [Byte1]: 57
1714 23:13:54.146174
1715 23:13:54.146589 Set Vref, RX VrefLevel [Byte0]: 58
1716 23:13:54.148968 [Byte1]: 58
1717 23:13:54.153790
1718 23:13:54.154296 Set Vref, RX VrefLevel [Byte0]: 59
1719 23:13:54.157143 [Byte1]: 59
1720 23:13:54.161190
1721 23:13:54.161753 Set Vref, RX VrefLevel [Byte0]: 60
1722 23:13:54.164666 [Byte1]: 60
1723 23:13:54.168837
1724 23:13:54.169259 Set Vref, RX VrefLevel [Byte0]: 61
1725 23:13:54.171993 [Byte1]: 61
1726 23:13:54.176481
1727 23:13:54.177000 Set Vref, RX VrefLevel [Byte0]: 62
1728 23:13:54.179556 [Byte1]: 62
1729 23:13:54.183693
1730 23:13:54.184112 Set Vref, RX VrefLevel [Byte0]: 63
1731 23:13:54.187255 [Byte1]: 63
1732 23:13:54.191622
1733 23:13:54.192134 Set Vref, RX VrefLevel [Byte0]: 64
1734 23:13:54.194718 [Byte1]: 64
1735 23:13:54.198607
1736 23:13:54.199021 Set Vref, RX VrefLevel [Byte0]: 65
1737 23:13:54.202065 [Byte1]: 65
1738 23:13:54.206399
1739 23:13:54.206839 Set Vref, RX VrefLevel [Byte0]: 66
1740 23:13:54.209786 [Byte1]: 66
1741 23:13:54.214158
1742 23:13:54.214694 Set Vref, RX VrefLevel [Byte0]: 67
1743 23:13:54.217456 [Byte1]: 67
1744 23:13:54.221358
1745 23:13:54.221826 Set Vref, RX VrefLevel [Byte0]: 68
1746 23:13:54.224889 [Byte1]: 68
1747 23:13:54.229068
1748 23:13:54.229645 Set Vref, RX VrefLevel [Byte0]: 69
1749 23:13:54.232654 [Byte1]: 69
1750 23:13:54.236564
1751 23:13:54.237068 Set Vref, RX VrefLevel [Byte0]: 70
1752 23:13:54.240050 [Byte1]: 70
1753 23:13:54.244169
1754 23:13:54.244595 Set Vref, RX VrefLevel [Byte0]: 71
1755 23:13:54.247910 [Byte1]: 71
1756 23:13:54.251537
1757 23:13:54.251954 Set Vref, RX VrefLevel [Byte0]: 72
1758 23:13:54.255379 [Byte1]: 72
1759 23:13:54.259037
1760 23:13:54.259452 Set Vref, RX VrefLevel [Byte0]: 73
1761 23:13:54.262464 [Byte1]: 73
1762 23:13:54.266697
1763 23:13:54.267110 Final RX Vref Byte 0 = 61 to rank0
1764 23:13:54.270024 Final RX Vref Byte 1 = 55 to rank0
1765 23:13:54.273676 Final RX Vref Byte 0 = 61 to rank1
1766 23:13:54.276375 Final RX Vref Byte 1 = 55 to rank1==
1767 23:13:54.280111 Dram Type= 6, Freq= 0, CH_1, rank 0
1768 23:13:54.283606 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1769 23:13:54.286974 ==
1770 23:13:54.287391 DQS Delay:
1771 23:13:54.287816 DQS0 = 0, DQS1 = 0
1772 23:13:54.290305 DQM Delay:
1773 23:13:54.290718 DQM0 = 95, DQM1 = 90
1774 23:13:54.293718 DQ Delay:
1775 23:13:54.296860 DQ0 =100, DQ1 =88, DQ2 =84, DQ3 =88
1776 23:13:54.300452 DQ4 =96, DQ5 =104, DQ6 =104, DQ7 =96
1777 23:13:54.303269 DQ8 =80, DQ9 =80, DQ10 =92, DQ11 =84
1778 23:13:54.307046 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
1779 23:13:54.307564
1780 23:13:54.307897
1781 23:13:54.313803 [DQSOSCAuto] RK0, (LSB)MR18= 0x2945, (MSB)MR19= 0x606, tDQSOscB0 = 392 ps tDQSOscB1 = 399 ps
1782 23:13:54.316363 CH1 RK0: MR19=606, MR18=2945
1783 23:13:54.323317 CH1_RK0: MR19=0x606, MR18=0x2945, DQSOSC=392, MR23=63, INC=96, DEC=64
1784 23:13:54.323800
1785 23:13:54.326705 ----->DramcWriteLeveling(PI) begin...
1786 23:13:54.327126 ==
1787 23:13:54.329920 Dram Type= 6, Freq= 0, CH_1, rank 1
1788 23:13:54.333338 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1789 23:13:54.333794 ==
1790 23:13:54.337146 Write leveling (Byte 0): 26 => 26
1791 23:13:54.340289 Write leveling (Byte 1): 27 => 27
1792 23:13:54.343845 DramcWriteLeveling(PI) end<-----
1793 23:13:54.344409
1794 23:13:54.344749 ==
1795 23:13:54.347274 Dram Type= 6, Freq= 0, CH_1, rank 1
1796 23:13:54.350159 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1797 23:13:54.350584 ==
1798 23:13:54.353685 [Gating] SW mode calibration
1799 23:13:54.360427 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1800 23:13:54.366648 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1801 23:13:54.370372 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1802 23:13:54.373715 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1803 23:13:54.380088 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1804 23:13:54.383768 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1805 23:13:54.387084 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1806 23:13:54.394044 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1807 23:13:54.397219 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1808 23:13:54.400499 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1809 23:13:54.407108 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1810 23:13:54.410222 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1811 23:13:54.413947 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1812 23:13:54.416749 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1813 23:13:54.423992 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1814 23:13:54.427117 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 23:13:54.430323 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 23:13:54.437140 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 23:13:54.441060 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 23:13:54.443693 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1819 23:13:54.450532 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 23:13:54.453640 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 23:13:54.457329 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 23:13:54.464150 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 23:13:54.466857 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 23:13:54.470377 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 23:13:54.477120 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 23:13:54.480249 0 9 4 | B1->B0 | 2b2b 2323 | 1 1 | (1 1) (1 1)
1827 23:13:54.484056 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
1828 23:13:54.490434 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1829 23:13:54.493999 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1830 23:13:54.497142 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1831 23:13:54.503845 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1832 23:13:54.507611 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1833 23:13:54.510219 0 10 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
1834 23:13:54.513678 0 10 4 | B1->B0 | 2727 2f2f | 0 0 | (0 0) (0 0)
1835 23:13:54.520562 0 10 8 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 0)
1836 23:13:54.524097 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 23:13:54.527127 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 23:13:54.533846 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 23:13:54.537113 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 23:13:54.540537 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 23:13:54.547067 0 11 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1842 23:13:54.550938 0 11 4 | B1->B0 | 3a3a 2a2a | 1 0 | (0 0) (0 0)
1843 23:13:54.553665 0 11 8 | B1->B0 | 4646 4343 | 0 0 | (0 0) (0 0)
1844 23:13:54.560413 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1845 23:13:54.564034 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1846 23:13:54.567377 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1847 23:13:54.574312 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1848 23:13:54.577249 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1849 23:13:54.580629 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1850 23:13:54.584100 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1851 23:13:54.591077 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1852 23:13:54.593882 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1853 23:13:54.597861 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1854 23:13:54.604480 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1855 23:13:54.607519 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1856 23:13:54.610616 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1857 23:13:54.617651 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1858 23:13:54.620712 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1859 23:13:54.624226 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1860 23:13:54.630730 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1861 23:13:54.633901 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1862 23:13:54.637143 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1863 23:13:54.644601 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 23:13:54.647994 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 23:13:54.650666 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1866 23:13:54.654417 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1867 23:13:54.657933 Total UI for P1: 0, mck2ui 16
1868 23:13:54.661400 best dqsien dly found for B0: ( 0, 14, 0)
1869 23:13:54.664880 Total UI for P1: 0, mck2ui 16
1870 23:13:54.667499 best dqsien dly found for B1: ( 0, 14, 0)
1871 23:13:54.670923 best DQS0 dly(MCK, UI, PI) = (0, 14, 0)
1872 23:13:54.674573 best DQS1 dly(MCK, UI, PI) = (0, 14, 0)
1873 23:13:54.675138
1874 23:13:54.681179 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 0)
1875 23:13:54.684575 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 0)
1876 23:13:54.685170 [Gating] SW calibration Done
1877 23:13:54.687588 ==
1878 23:13:54.691085 Dram Type= 6, Freq= 0, CH_1, rank 1
1879 23:13:54.694309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1880 23:13:54.694729 ==
1881 23:13:54.695064 RX Vref Scan: 0
1882 23:13:54.695374
1883 23:13:54.697798 RX Vref 0 -> 0, step: 1
1884 23:13:54.698352
1885 23:13:54.701111 RX Delay -130 -> 252, step: 16
1886 23:13:54.704099 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1887 23:13:54.708002 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1888 23:13:54.714440 iDelay=222, Bit 2, Center 85 (-18 ~ 189) 208
1889 23:13:54.717414 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1890 23:13:54.721008 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1891 23:13:54.724631 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1892 23:13:54.727503 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1893 23:13:54.731168 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1894 23:13:54.737754 iDelay=222, Bit 8, Center 85 (-18 ~ 189) 208
1895 23:13:54.741230 iDelay=222, Bit 9, Center 85 (-18 ~ 189) 208
1896 23:13:54.744300 iDelay=222, Bit 10, Center 93 (-18 ~ 205) 224
1897 23:13:54.747595 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1898 23:13:54.750746 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1899 23:13:54.757822 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1900 23:13:54.760938 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1901 23:13:54.764643 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1902 23:13:54.765160 ==
1903 23:13:54.767980 Dram Type= 6, Freq= 0, CH_1, rank 1
1904 23:13:54.770908 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1905 23:13:54.774363 ==
1906 23:13:54.774802 DQS Delay:
1907 23:13:54.775235 DQS0 = 0, DQS1 = 0
1908 23:13:54.777716 DQM Delay:
1909 23:13:54.778155 DQM0 = 93, DQM1 = 90
1910 23:13:54.778586 DQ Delay:
1911 23:13:54.781262 DQ0 =101, DQ1 =85, DQ2 =85, DQ3 =85
1912 23:13:54.784520 DQ4 =85, DQ5 =109, DQ6 =101, DQ7 =93
1913 23:13:54.787660 DQ8 =85, DQ9 =85, DQ10 =93, DQ11 =85
1914 23:13:54.791393 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1915 23:13:54.791821
1916 23:13:54.794688
1917 23:13:54.795102 ==
1918 23:13:54.797724 Dram Type= 6, Freq= 0, CH_1, rank 1
1919 23:13:54.801080 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1920 23:13:54.801619 ==
1921 23:13:54.802100
1922 23:13:54.802422
1923 23:13:54.804492 TX Vref Scan disable
1924 23:13:54.804905 == TX Byte 0 ==
1925 23:13:54.810928 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1926 23:13:54.814337 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1927 23:13:54.814757 == TX Byte 1 ==
1928 23:13:54.821008 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1929 23:13:54.824528 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1930 23:13:54.825035 ==
1931 23:13:54.827685 Dram Type= 6, Freq= 0, CH_1, rank 1
1932 23:13:54.831543 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1933 23:13:54.832068 ==
1934 23:13:54.844519 TX Vref=22, minBit 1, minWin=26, winSum=440
1935 23:13:54.848117 TX Vref=24, minBit 0, minWin=27, winSum=443
1936 23:13:54.851764 TX Vref=26, minBit 0, minWin=27, winSum=445
1937 23:13:54.855144 TX Vref=28, minBit 0, minWin=27, winSum=446
1938 23:13:54.858245 TX Vref=30, minBit 0, minWin=27, winSum=448
1939 23:13:54.861574 TX Vref=32, minBit 0, minWin=27, winSum=445
1940 23:13:54.868495 [TxChooseVref] Worse bit 0, Min win 27, Win sum 448, Final Vref 30
1941 23:13:54.868914
1942 23:13:54.871433 Final TX Range 1 Vref 30
1943 23:13:54.871850
1944 23:13:54.872178 ==
1945 23:13:54.874936 Dram Type= 6, Freq= 0, CH_1, rank 1
1946 23:13:54.877788 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1947 23:13:54.878255 ==
1948 23:13:54.878597
1949 23:13:54.878910
1950 23:13:54.881388 TX Vref Scan disable
1951 23:13:54.885273 == TX Byte 0 ==
1952 23:13:54.888040 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1953 23:13:54.891392 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1954 23:13:54.895013 == TX Byte 1 ==
1955 23:13:54.898083 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1956 23:13:54.901172 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1957 23:13:54.901628
1958 23:13:54.904820 [DATLAT]
1959 23:13:54.905237 Freq=800, CH1 RK1
1960 23:13:54.905568
1961 23:13:54.907806 DATLAT Default: 0xa
1962 23:13:54.908219 0, 0xFFFF, sum = 0
1963 23:13:54.911475 1, 0xFFFF, sum = 0
1964 23:13:54.911894 2, 0xFFFF, sum = 0
1965 23:13:54.914709 3, 0xFFFF, sum = 0
1966 23:13:54.915131 4, 0xFFFF, sum = 0
1967 23:13:54.918162 5, 0xFFFF, sum = 0
1968 23:13:54.918614 6, 0xFFFF, sum = 0
1969 23:13:54.921547 7, 0xFFFF, sum = 0
1970 23:13:54.922025 8, 0xFFFF, sum = 0
1971 23:13:54.924870 9, 0x0, sum = 1
1972 23:13:54.925286 10, 0x0, sum = 2
1973 23:13:54.928174 11, 0x0, sum = 3
1974 23:13:54.928803 12, 0x0, sum = 4
1975 23:13:54.931698 best_step = 10
1976 23:13:54.932141
1977 23:13:54.932482 ==
1978 23:13:54.935090 Dram Type= 6, Freq= 0, CH_1, rank 1
1979 23:13:54.938020 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1980 23:13:54.938435 ==
1981 23:13:54.941795 RX Vref Scan: 0
1982 23:13:54.942302
1983 23:13:54.942638 RX Vref 0 -> 0, step: 1
1984 23:13:54.942943
1985 23:13:54.944730 RX Delay -63 -> 252, step: 8
1986 23:13:54.948279 iDelay=209, Bit 0, Center 100 (1 ~ 200) 200
1987 23:13:54.954676 iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200
1988 23:13:54.958345 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
1989 23:13:54.962022 iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200
1990 23:13:54.964998 iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200
1991 23:13:54.968090 iDelay=209, Bit 5, Center 112 (17 ~ 208) 192
1992 23:13:54.975030 iDelay=209, Bit 6, Center 108 (9 ~ 208) 200
1993 23:13:54.978149 iDelay=209, Bit 7, Center 96 (-7 ~ 200) 208
1994 23:13:54.981470 iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208
1995 23:13:54.984908 iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208
1996 23:13:54.988387 iDelay=209, Bit 10, Center 96 (-7 ~ 200) 208
1997 23:13:54.992035 iDelay=209, Bit 11, Center 84 (-23 ~ 192) 216
1998 23:13:54.998180 iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216
1999 23:13:55.001517 iDelay=209, Bit 13, Center 96 (-7 ~ 200) 208
2000 23:13:55.004828 iDelay=209, Bit 14, Center 96 (-7 ~ 200) 208
2001 23:13:55.008519 iDelay=209, Bit 15, Center 96 (-7 ~ 200) 208
2002 23:13:55.008934 ==
2003 23:13:55.011660 Dram Type= 6, Freq= 0, CH_1, rank 1
2004 23:13:55.014945 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2005 23:13:55.018108 ==
2006 23:13:55.018521 DQS Delay:
2007 23:13:55.018898 DQS0 = 0, DQS1 = 0
2008 23:13:55.021502 DQM Delay:
2009 23:13:55.021983 DQM0 = 97, DQM1 = 91
2010 23:13:55.025295 DQ Delay:
2011 23:13:55.028105 DQ0 =100, DQ1 =92, DQ2 =84, DQ3 =92
2012 23:13:55.032377 DQ4 =92, DQ5 =112, DQ6 =108, DQ7 =96
2013 23:13:55.032898 DQ8 =80, DQ9 =80, DQ10 =96, DQ11 =84
2014 23:13:55.038716 DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =96
2015 23:13:55.039200
2016 23:13:55.039531
2017 23:13:55.045401 [DQSOSCAuto] RK1, (LSB)MR18= 0x440f, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 392 ps
2018 23:13:55.048187 CH1 RK1: MR19=606, MR18=440F
2019 23:13:55.055061 CH1_RK1: MR19=0x606, MR18=0x440F, DQSOSC=392, MR23=63, INC=96, DEC=64
2020 23:13:55.058272 [RxdqsGatingPostProcess] freq 800
2021 23:13:55.061408 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2022 23:13:55.065346 Pre-setting of DQS Precalculation
2023 23:13:55.072112 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2024 23:13:55.078425 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2025 23:13:55.085176 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2026 23:13:55.085778
2027 23:13:55.086157
2028 23:13:55.088516 [Calibration Summary] 1600 Mbps
2029 23:13:55.088969 CH 0, Rank 0
2030 23:13:55.091719 SW Impedance : PASS
2031 23:13:55.094881 DUTY Scan : NO K
2032 23:13:55.095294 ZQ Calibration : PASS
2033 23:13:55.098327 Jitter Meter : NO K
2034 23:13:55.101788 CBT Training : PASS
2035 23:13:55.102205 Write leveling : PASS
2036 23:13:55.104776 RX DQS gating : PASS
2037 23:13:55.105192 RX DQ/DQS(RDDQC) : PASS
2038 23:13:55.108679 TX DQ/DQS : PASS
2039 23:13:55.111844 RX DATLAT : PASS
2040 23:13:55.112259 RX DQ/DQS(Engine): PASS
2041 23:13:55.115252 TX OE : NO K
2042 23:13:55.115707 All Pass.
2043 23:13:55.116040
2044 23:13:55.118334 CH 0, Rank 1
2045 23:13:55.118748 SW Impedance : PASS
2046 23:13:55.121545 DUTY Scan : NO K
2047 23:13:55.125008 ZQ Calibration : PASS
2048 23:13:55.125466 Jitter Meter : NO K
2049 23:13:55.128471 CBT Training : PASS
2050 23:13:55.131836 Write leveling : PASS
2051 23:13:55.132561 RX DQS gating : PASS
2052 23:13:55.134879 RX DQ/DQS(RDDQC) : PASS
2053 23:13:55.138158 TX DQ/DQS : PASS
2054 23:13:55.138579 RX DATLAT : PASS
2055 23:13:55.141517 RX DQ/DQS(Engine): PASS
2056 23:13:55.145095 TX OE : NO K
2057 23:13:55.145680 All Pass.
2058 23:13:55.146047
2059 23:13:55.146360 CH 1, Rank 0
2060 23:13:55.147992 SW Impedance : PASS
2061 23:13:55.151224 DUTY Scan : NO K
2062 23:13:55.151639 ZQ Calibration : PASS
2063 23:13:55.154541 Jitter Meter : NO K
2064 23:13:55.158141 CBT Training : PASS
2065 23:13:55.158554 Write leveling : PASS
2066 23:13:55.161898 RX DQS gating : PASS
2067 23:13:55.162313 RX DQ/DQS(RDDQC) : PASS
2068 23:13:55.165084 TX DQ/DQS : PASS
2069 23:13:55.168584 RX DATLAT : PASS
2070 23:13:55.169097 RX DQ/DQS(Engine): PASS
2071 23:13:55.171410 TX OE : NO K
2072 23:13:55.171825 All Pass.
2073 23:13:55.172157
2074 23:13:55.174811 CH 1, Rank 1
2075 23:13:55.175242 SW Impedance : PASS
2076 23:13:55.178425 DUTY Scan : NO K
2077 23:13:55.181538 ZQ Calibration : PASS
2078 23:13:55.182000 Jitter Meter : NO K
2079 23:13:55.185224 CBT Training : PASS
2080 23:13:55.188505 Write leveling : PASS
2081 23:13:55.188923 RX DQS gating : PASS
2082 23:13:55.191880 RX DQ/DQS(RDDQC) : PASS
2083 23:13:55.195211 TX DQ/DQS : PASS
2084 23:13:55.195740 RX DATLAT : PASS
2085 23:13:55.198449 RX DQ/DQS(Engine): PASS
2086 23:13:55.198983 TX OE : NO K
2087 23:13:55.201968 All Pass.
2088 23:13:55.202483
2089 23:13:55.202818 DramC Write-DBI off
2090 23:13:55.204702 PER_BANK_REFRESH: Hybrid Mode
2091 23:13:55.208687 TX_TRACKING: ON
2092 23:13:55.211504 [GetDramInforAfterCalByMRR] Vendor 6.
2093 23:13:55.214693 [GetDramInforAfterCalByMRR] Revision 606.
2094 23:13:55.217953 [GetDramInforAfterCalByMRR] Revision 2 0.
2095 23:13:55.218370 MR0 0x3b3b
2096 23:13:55.218702 MR8 0x5151
2097 23:13:55.225000 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2098 23:13:55.225511
2099 23:13:55.225904 MR0 0x3b3b
2100 23:13:55.226221 MR8 0x5151
2101 23:13:55.228108 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2102 23:13:55.228522
2103 23:13:55.238288 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2104 23:13:55.241663 [FAST_K] Save calibration result to emmc
2105 23:13:55.245127 [FAST_K] Save calibration result to emmc
2106 23:13:55.248095 dram_init: config_dvfs: 1
2107 23:13:55.252029 dramc_set_vcore_voltage set vcore to 662500
2108 23:13:55.255289 Read voltage for 1200, 2
2109 23:13:55.255716 Vio18 = 0
2110 23:13:55.256049 Vcore = 662500
2111 23:13:55.258548 Vdram = 0
2112 23:13:55.258959 Vddq = 0
2113 23:13:55.259290 Vmddr = 0
2114 23:13:55.265428 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2115 23:13:55.268706 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2116 23:13:55.271783 MEM_TYPE=3, freq_sel=15
2117 23:13:55.275125 sv_algorithm_assistance_LP4_1600
2118 23:13:55.278159 ============ PULL DRAM RESETB DOWN ============
2119 23:13:55.281325 ========== PULL DRAM RESETB DOWN end =========
2120 23:13:55.288769 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2121 23:13:55.291569 ===================================
2122 23:13:55.295161 LPDDR4 DRAM CONFIGURATION
2123 23:13:55.295577 ===================================
2124 23:13:55.298149 EX_ROW_EN[0] = 0x0
2125 23:13:55.302026 EX_ROW_EN[1] = 0x0
2126 23:13:55.302538 LP4Y_EN = 0x0
2127 23:13:55.305209 WORK_FSP = 0x0
2128 23:13:55.305663 WL = 0x4
2129 23:13:55.308485 RL = 0x4
2130 23:13:55.309002 BL = 0x2
2131 23:13:55.311663 RPST = 0x0
2132 23:13:55.312110 RD_PRE = 0x0
2133 23:13:55.315008 WR_PRE = 0x1
2134 23:13:55.315423 WR_PST = 0x0
2135 23:13:55.318574 DBI_WR = 0x0
2136 23:13:55.319004 DBI_RD = 0x0
2137 23:13:55.321909 OTF = 0x1
2138 23:13:55.325306 ===================================
2139 23:13:55.328662 ===================================
2140 23:13:55.329187 ANA top config
2141 23:13:55.331558 ===================================
2142 23:13:55.334806 DLL_ASYNC_EN = 0
2143 23:13:55.338108 ALL_SLAVE_EN = 0
2144 23:13:55.341454 NEW_RANK_MODE = 1
2145 23:13:55.341924 DLL_IDLE_MODE = 1
2146 23:13:55.344975 LP45_APHY_COMB_EN = 1
2147 23:13:55.348499 TX_ODT_DIS = 1
2148 23:13:55.351910 NEW_8X_MODE = 1
2149 23:13:55.355343 ===================================
2150 23:13:55.358127 ===================================
2151 23:13:55.361969 data_rate = 2400
2152 23:13:55.362460 CKR = 1
2153 23:13:55.365269 DQ_P2S_RATIO = 8
2154 23:13:55.368511 ===================================
2155 23:13:55.371974 CA_P2S_RATIO = 8
2156 23:13:55.374776 DQ_CA_OPEN = 0
2157 23:13:55.378374 DQ_SEMI_OPEN = 0
2158 23:13:55.378792 CA_SEMI_OPEN = 0
2159 23:13:55.381845 CA_FULL_RATE = 0
2160 23:13:55.384824 DQ_CKDIV4_EN = 0
2161 23:13:55.388341 CA_CKDIV4_EN = 0
2162 23:13:55.391931 CA_PREDIV_EN = 0
2163 23:13:55.395640 PH8_DLY = 17
2164 23:13:55.396153 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2165 23:13:55.398335 DQ_AAMCK_DIV = 4
2166 23:13:55.402098 CA_AAMCK_DIV = 4
2167 23:13:55.405364 CA_ADMCK_DIV = 4
2168 23:13:55.408416 DQ_TRACK_CA_EN = 0
2169 23:13:55.411763 CA_PICK = 1200
2170 23:13:55.414697 CA_MCKIO = 1200
2171 23:13:55.415137 MCKIO_SEMI = 0
2172 23:13:55.418242 PLL_FREQ = 2366
2173 23:13:55.421795 DQ_UI_PI_RATIO = 32
2174 23:13:55.425363 CA_UI_PI_RATIO = 0
2175 23:13:55.428414 ===================================
2176 23:13:55.431648 ===================================
2177 23:13:55.435427 memory_type:LPDDR4
2178 23:13:55.435983 GP_NUM : 10
2179 23:13:55.438285 SRAM_EN : 1
2180 23:13:55.438711 MD32_EN : 0
2181 23:13:55.441922 ===================================
2182 23:13:55.445150 [ANA_INIT] >>>>>>>>>>>>>>
2183 23:13:55.448316 <<<<<< [CONFIGURE PHASE]: ANA_TX
2184 23:13:55.452132 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2185 23:13:55.455090 ===================================
2186 23:13:55.458172 data_rate = 2400,PCW = 0X5b00
2187 23:13:55.461837 ===================================
2188 23:13:55.465044 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2189 23:13:55.471745 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2190 23:13:55.474672 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2191 23:13:55.481863 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2192 23:13:55.485320 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2193 23:13:55.488609 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2194 23:13:55.489024 [ANA_INIT] flow start
2195 23:13:55.491740 [ANA_INIT] PLL >>>>>>>>
2196 23:13:55.495608 [ANA_INIT] PLL <<<<<<<<
2197 23:13:55.496193 [ANA_INIT] MIDPI >>>>>>>>
2198 23:13:55.498974 [ANA_INIT] MIDPI <<<<<<<<
2199 23:13:55.501783 [ANA_INIT] DLL >>>>>>>>
2200 23:13:55.502196 [ANA_INIT] DLL <<<<<<<<
2201 23:13:55.505297 [ANA_INIT] flow end
2202 23:13:55.508912 ============ LP4 DIFF to SE enter ============
2203 23:13:55.511775 ============ LP4 DIFF to SE exit ============
2204 23:13:55.515467 [ANA_INIT] <<<<<<<<<<<<<
2205 23:13:55.518954 [Flow] Enable top DCM control >>>>>
2206 23:13:55.521860 [Flow] Enable top DCM control <<<<<
2207 23:13:55.525310 Enable DLL master slave shuffle
2208 23:13:55.532413 ==============================================================
2209 23:13:55.532832 Gating Mode config
2210 23:13:55.538966 ==============================================================
2211 23:13:55.539483 Config description:
2212 23:13:55.549022 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2213 23:13:55.555545 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2214 23:13:55.562606 SELPH_MODE 0: By rank 1: By Phase
2215 23:13:55.565448 ==============================================================
2216 23:13:55.569330 GAT_TRACK_EN = 1
2217 23:13:55.572596 RX_GATING_MODE = 2
2218 23:13:55.575494 RX_GATING_TRACK_MODE = 2
2219 23:13:55.578618 SELPH_MODE = 1
2220 23:13:55.582145 PICG_EARLY_EN = 1
2221 23:13:55.585344 VALID_LAT_VALUE = 1
2222 23:13:55.588879 ==============================================================
2223 23:13:55.592347 Enter into Gating configuration >>>>
2224 23:13:55.595666 Exit from Gating configuration <<<<
2225 23:13:55.598964 Enter into DVFS_PRE_config >>>>>
2226 23:13:55.612204 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2227 23:13:55.615374 Exit from DVFS_PRE_config <<<<<
2228 23:13:55.615790 Enter into PICG configuration >>>>
2229 23:13:55.619009 Exit from PICG configuration <<<<
2230 23:13:55.621894 [RX_INPUT] configuration >>>>>
2231 23:13:55.625310 [RX_INPUT] configuration <<<<<
2232 23:13:55.631912 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2233 23:13:55.635438 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2234 23:13:55.642396 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2235 23:13:55.648815 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2236 23:13:55.655645 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2237 23:13:55.662425 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2238 23:13:55.665671 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2239 23:13:55.668843 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2240 23:13:55.671884 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2241 23:13:55.678812 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2242 23:13:55.682184 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2243 23:13:55.685732 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2244 23:13:55.688623 ===================================
2245 23:13:55.691967 LPDDR4 DRAM CONFIGURATION
2246 23:13:55.695565 ===================================
2247 23:13:55.696087 EX_ROW_EN[0] = 0x0
2248 23:13:55.698726 EX_ROW_EN[1] = 0x0
2249 23:13:55.702107 LP4Y_EN = 0x0
2250 23:13:55.702521 WORK_FSP = 0x0
2251 23:13:55.705435 WL = 0x4
2252 23:13:55.706021 RL = 0x4
2253 23:13:55.708640 BL = 0x2
2254 23:13:55.709069 RPST = 0x0
2255 23:13:55.711847 RD_PRE = 0x0
2256 23:13:55.712263 WR_PRE = 0x1
2257 23:13:55.715346 WR_PST = 0x0
2258 23:13:55.715760 DBI_WR = 0x0
2259 23:13:55.718454 DBI_RD = 0x0
2260 23:13:55.718868 OTF = 0x1
2261 23:13:55.721884 ===================================
2262 23:13:55.725289 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2263 23:13:55.732057 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2264 23:13:55.734995 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2265 23:13:55.738611 ===================================
2266 23:13:55.742224 LPDDR4 DRAM CONFIGURATION
2267 23:13:55.745217 ===================================
2268 23:13:55.745966 EX_ROW_EN[0] = 0x10
2269 23:13:55.748539 EX_ROW_EN[1] = 0x0
2270 23:13:55.748963 LP4Y_EN = 0x0
2271 23:13:55.752169 WORK_FSP = 0x0
2272 23:13:55.752583 WL = 0x4
2273 23:13:55.755154 RL = 0x4
2274 23:13:55.758845 BL = 0x2
2275 23:13:55.759364 RPST = 0x0
2276 23:13:55.762202 RD_PRE = 0x0
2277 23:13:55.762708 WR_PRE = 0x1
2278 23:13:55.765455 WR_PST = 0x0
2279 23:13:55.766011 DBI_WR = 0x0
2280 23:13:55.769362 DBI_RD = 0x0
2281 23:13:55.769935 OTF = 0x1
2282 23:13:55.772217 ===================================
2283 23:13:55.778492 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2284 23:13:55.778912 ==
2285 23:13:55.782065 Dram Type= 6, Freq= 0, CH_0, rank 0
2286 23:13:55.785468 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2287 23:13:55.785930 ==
2288 23:13:55.788910 [Duty_Offset_Calibration]
2289 23:13:55.791833 B0:2 B1:1 CA:1
2290 23:13:55.792290
2291 23:13:55.795660 [DutyScan_Calibration_Flow] k_type=0
2292 23:13:55.803103
2293 23:13:55.803518 ==CLK 0==
2294 23:13:55.806572 Final CLK duty delay cell = 0
2295 23:13:55.809815 [0] MAX Duty = 5187%(X100), DQS PI = 24
2296 23:13:55.813223 [0] MIN Duty = 4844%(X100), DQS PI = 48
2297 23:13:55.813673 [0] AVG Duty = 5015%(X100)
2298 23:13:55.816798
2299 23:13:55.820045 CH0 CLK Duty spec in!! Max-Min= 343%
2300 23:13:55.823203 [DutyScan_Calibration_Flow] ====Done====
2301 23:13:55.823500
2302 23:13:55.826002 [DutyScan_Calibration_Flow] k_type=1
2303 23:13:55.841337
2304 23:13:55.841660 ==DQS 0 ==
2305 23:13:55.845136 Final DQS duty delay cell = -4
2306 23:13:55.848685 [-4] MAX Duty = 5156%(X100), DQS PI = 24
2307 23:13:55.851786 [-4] MIN Duty = 4782%(X100), DQS PI = 62
2308 23:13:55.854795 [-4] AVG Duty = 4969%(X100)
2309 23:13:55.855091
2310 23:13:55.855326 ==DQS 1 ==
2311 23:13:55.858084 Final DQS duty delay cell = 0
2312 23:13:55.861721 [0] MAX Duty = 5156%(X100), DQS PI = 62
2313 23:13:55.864808 [0] MIN Duty = 5000%(X100), DQS PI = 34
2314 23:13:55.868267 [0] AVG Duty = 5078%(X100)
2315 23:13:55.868589
2316 23:13:55.871788 CH0 DQS 0 Duty spec in!! Max-Min= 374%
2317 23:13:55.872202
2318 23:13:55.875375 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2319 23:13:55.878768 [DutyScan_Calibration_Flow] ====Done====
2320 23:13:55.879145
2321 23:13:55.881605 [DutyScan_Calibration_Flow] k_type=3
2322 23:13:55.898525
2323 23:13:55.899029 ==DQM 0 ==
2324 23:13:55.902038 Final DQM duty delay cell = 0
2325 23:13:55.905647 [0] MAX Duty = 5125%(X100), DQS PI = 22
2326 23:13:55.908740 [0] MIN Duty = 4906%(X100), DQS PI = 52
2327 23:13:55.909149 [0] AVG Duty = 5015%(X100)
2328 23:13:55.911982
2329 23:13:55.912390 ==DQM 1 ==
2330 23:13:55.915314 Final DQM duty delay cell = 0
2331 23:13:55.919105 [0] MAX Duty = 5093%(X100), DQS PI = 0
2332 23:13:55.922296 [0] MIN Duty = 5031%(X100), DQS PI = 14
2333 23:13:55.922812 [0] AVG Duty = 5062%(X100)
2334 23:13:55.925226
2335 23:13:55.929201 CH0 DQM 0 Duty spec in!! Max-Min= 219%
2336 23:13:55.929790
2337 23:13:55.932359 CH0 DQM 1 Duty spec in!! Max-Min= 62%
2338 23:13:55.935412 [DutyScan_Calibration_Flow] ====Done====
2339 23:13:55.935834
2340 23:13:55.938961 [DutyScan_Calibration_Flow] k_type=2
2341 23:13:55.955469
2342 23:13:55.955943 ==DQ 0 ==
2343 23:13:55.958266 Final DQ duty delay cell = 0
2344 23:13:55.961825 [0] MAX Duty = 5062%(X100), DQS PI = 32
2345 23:13:55.964761 [0] MIN Duty = 4906%(X100), DQS PI = 0
2346 23:13:55.965208 [0] AVG Duty = 4984%(X100)
2347 23:13:55.965542
2348 23:13:55.968448 ==DQ 1 ==
2349 23:13:55.971461 Final DQ duty delay cell = 0
2350 23:13:55.975501 [0] MAX Duty = 5093%(X100), DQS PI = 24
2351 23:13:55.978638 [0] MIN Duty = 4969%(X100), DQS PI = 2
2352 23:13:55.979059 [0] AVG Duty = 5031%(X100)
2353 23:13:55.979393
2354 23:13:55.981621 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2355 23:13:55.982052
2356 23:13:55.985001 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2357 23:13:55.991620 [DutyScan_Calibration_Flow] ====Done====
2358 23:13:55.992054 ==
2359 23:13:55.994861 Dram Type= 6, Freq= 0, CH_1, rank 0
2360 23:13:55.998530 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2361 23:13:55.998950 ==
2362 23:13:56.001938 [Duty_Offset_Calibration]
2363 23:13:56.002461 B0:1 B1:0 CA:0
2364 23:13:56.002923
2365 23:13:56.005440 [DutyScan_Calibration_Flow] k_type=0
2366 23:13:56.014278
2367 23:13:56.014755 ==CLK 0==
2368 23:13:56.017530 Final CLK duty delay cell = -4
2369 23:13:56.021000 [-4] MAX Duty = 5000%(X100), DQS PI = 18
2370 23:13:56.023855 [-4] MIN Duty = 4875%(X100), DQS PI = 50
2371 23:13:56.027740 [-4] AVG Duty = 4937%(X100)
2372 23:13:56.028252
2373 23:13:56.031198 CH1 CLK Duty spec in!! Max-Min= 125%
2374 23:13:56.033901 [DutyScan_Calibration_Flow] ====Done====
2375 23:13:56.034345
2376 23:13:56.037696 [DutyScan_Calibration_Flow] k_type=1
2377 23:13:56.053898
2378 23:13:56.054409 ==DQS 0 ==
2379 23:13:56.057180 Final DQS duty delay cell = 0
2380 23:13:56.060939 [0] MAX Duty = 5094%(X100), DQS PI = 24
2381 23:13:56.063798 [0] MIN Duty = 4875%(X100), DQS PI = 0
2382 23:13:56.064310 [0] AVG Duty = 4984%(X100)
2383 23:13:56.067715
2384 23:13:56.068249 ==DQS 1 ==
2385 23:13:56.070483 Final DQS duty delay cell = 0
2386 23:13:56.073949 [0] MAX Duty = 5187%(X100), DQS PI = 18
2387 23:13:56.077705 [0] MIN Duty = 4969%(X100), DQS PI = 10
2388 23:13:56.078250 [0] AVG Duty = 5078%(X100)
2389 23:13:56.080594
2390 23:13:56.083979 CH1 DQS 0 Duty spec in!! Max-Min= 219%
2391 23:13:56.084402
2392 23:13:56.087472 CH1 DQS 1 Duty spec in!! Max-Min= 218%
2393 23:13:56.090912 [DutyScan_Calibration_Flow] ====Done====
2394 23:13:56.091339
2395 23:13:56.093740 [DutyScan_Calibration_Flow] k_type=3
2396 23:13:56.110823
2397 23:13:56.111331 ==DQM 0 ==
2398 23:13:56.113996 Final DQM duty delay cell = 0
2399 23:13:56.117326 [0] MAX Duty = 5156%(X100), DQS PI = 8
2400 23:13:56.120614 [0] MIN Duty = 5031%(X100), DQS PI = 0
2401 23:13:56.121048 [0] AVG Duty = 5093%(X100)
2402 23:13:56.123656
2403 23:13:56.124075 ==DQM 1 ==
2404 23:13:56.127493 Final DQM duty delay cell = 0
2405 23:13:56.131187 [0] MAX Duty = 5031%(X100), DQS PI = 16
2406 23:13:56.133902 [0] MIN Duty = 4907%(X100), DQS PI = 36
2407 23:13:56.134418 [0] AVG Duty = 4969%(X100)
2408 23:13:56.134918
2409 23:13:56.140619 CH1 DQM 0 Duty spec in!! Max-Min= 125%
2410 23:13:56.141040
2411 23:13:56.144058 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2412 23:13:56.147243 [DutyScan_Calibration_Flow] ====Done====
2413 23:13:56.147666
2414 23:13:56.150700 [DutyScan_Calibration_Flow] k_type=2
2415 23:13:56.166601
2416 23:13:56.167024 ==DQ 0 ==
2417 23:13:56.169508 Final DQ duty delay cell = -4
2418 23:13:56.173339 [-4] MAX Duty = 5062%(X100), DQS PI = 8
2419 23:13:56.176412 [-4] MIN Duty = 4906%(X100), DQS PI = 44
2420 23:13:56.179771 [-4] AVG Duty = 4984%(X100)
2421 23:13:56.180289
2422 23:13:56.180627 ==DQ 1 ==
2423 23:13:56.183275 Final DQ duty delay cell = 0
2424 23:13:56.186231 [0] MAX Duty = 5125%(X100), DQS PI = 20
2425 23:13:56.189776 [0] MIN Duty = 4969%(X100), DQS PI = 12
2426 23:13:56.190324 [0] AVG Duty = 5047%(X100)
2427 23:13:56.193132
2428 23:13:56.196643 CH1 DQ 0 Duty spec in!! Max-Min= 156%
2429 23:13:56.197165
2430 23:13:56.199758 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2431 23:13:56.202858 [DutyScan_Calibration_Flow] ====Done====
2432 23:13:56.206709 nWR fixed to 30
2433 23:13:56.207136 [ModeRegInit_LP4] CH0 RK0
2434 23:13:56.209498 [ModeRegInit_LP4] CH0 RK1
2435 23:13:56.212930 [ModeRegInit_LP4] CH1 RK0
2436 23:13:56.216663 [ModeRegInit_LP4] CH1 RK1
2437 23:13:56.217083 match AC timing 7
2438 23:13:56.219469 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2439 23:13:56.226271 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2440 23:13:56.230110 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2441 23:13:56.232943 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2442 23:13:56.240024 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2443 23:13:56.240545 ==
2444 23:13:56.243599 Dram Type= 6, Freq= 0, CH_0, rank 0
2445 23:13:56.246277 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2446 23:13:56.246707 ==
2447 23:13:56.253165 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2448 23:13:56.259782 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2449 23:13:56.266908 [CA 0] Center 39 (8~70) winsize 63
2450 23:13:56.269879 [CA 1] Center 39 (8~70) winsize 63
2451 23:13:56.273356 [CA 2] Center 35 (5~66) winsize 62
2452 23:13:56.276520 [CA 3] Center 34 (4~65) winsize 62
2453 23:13:56.279756 [CA 4] Center 33 (3~64) winsize 62
2454 23:13:56.283452 [CA 5] Center 32 (3~62) winsize 60
2455 23:13:56.283957
2456 23:13:56.287105 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2457 23:13:56.287661
2458 23:13:56.289827 [CATrainingPosCal] consider 1 rank data
2459 23:13:56.293505 u2DelayCellTimex100 = 270/100 ps
2460 23:13:56.296922 CA0 delay=39 (8~70),Diff = 7 PI (33 cell)
2461 23:13:56.300655 CA1 delay=39 (8~70),Diff = 7 PI (33 cell)
2462 23:13:56.307031 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2463 23:13:56.310097 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2464 23:13:56.313238 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2465 23:13:56.316964 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2466 23:13:56.317494
2467 23:13:56.320103 CA PerBit enable=1, Macro0, CA PI delay=32
2468 23:13:56.320525
2469 23:13:56.323245 [CBTSetCACLKResult] CA Dly = 32
2470 23:13:56.323667 CS Dly: 6 (0~37)
2471 23:13:56.324006 ==
2472 23:13:56.326467 Dram Type= 6, Freq= 0, CH_0, rank 1
2473 23:13:56.333491 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2474 23:13:56.333958 ==
2475 23:13:56.336826 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2476 23:13:56.342962 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2477 23:13:56.352670 [CA 0] Center 38 (8~69) winsize 62
2478 23:13:56.355530 [CA 1] Center 38 (8~69) winsize 62
2479 23:13:56.359727 [CA 2] Center 35 (5~66) winsize 62
2480 23:13:56.362350 [CA 3] Center 34 (4~65) winsize 62
2481 23:13:56.365945 [CA 4] Center 33 (3~64) winsize 62
2482 23:13:56.369061 [CA 5] Center 32 (3~62) winsize 60
2483 23:13:56.369484
2484 23:13:56.372624 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2485 23:13:56.373047
2486 23:13:56.376405 [CATrainingPosCal] consider 2 rank data
2487 23:13:56.379093 u2DelayCellTimex100 = 270/100 ps
2488 23:13:56.382579 CA0 delay=38 (8~69),Diff = 6 PI (28 cell)
2489 23:13:56.386023 CA1 delay=38 (8~69),Diff = 6 PI (28 cell)
2490 23:13:56.389227 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2491 23:13:56.396111 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2492 23:13:56.399107 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2493 23:13:56.402816 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2494 23:13:56.403235
2495 23:13:56.406103 CA PerBit enable=1, Macro0, CA PI delay=32
2496 23:13:56.406548
2497 23:13:56.409236 [CBTSetCACLKResult] CA Dly = 32
2498 23:13:56.409708 CS Dly: 6 (0~38)
2499 23:13:56.410056
2500 23:13:56.412844 ----->DramcWriteLeveling(PI) begin...
2501 23:13:56.413364 ==
2502 23:13:56.415742 Dram Type= 6, Freq= 0, CH_0, rank 0
2503 23:13:56.422769 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2504 23:13:56.423253 ==
2505 23:13:56.425680 Write leveling (Byte 0): 33 => 33
2506 23:13:56.429015 Write leveling (Byte 1): 28 => 28
2507 23:13:56.429439 DramcWriteLeveling(PI) end<-----
2508 23:13:56.432732
2509 23:13:56.433153 ==
2510 23:13:56.435776 Dram Type= 6, Freq= 0, CH_0, rank 0
2511 23:13:56.439900 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2512 23:13:56.440394 ==
2513 23:13:56.442472 [Gating] SW mode calibration
2514 23:13:56.449512 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2515 23:13:56.452521 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2516 23:13:56.459453 0 15 0 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
2517 23:13:56.462481 0 15 4 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
2518 23:13:56.465958 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2519 23:13:56.473091 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2520 23:13:56.475811 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2521 23:13:56.479634 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2522 23:13:56.485959 0 15 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
2523 23:13:56.489463 0 15 28 | B1->B0 | 3434 2424 | 0 0 | (0 0) (0 0)
2524 23:13:56.492762 1 0 0 | B1->B0 | 2c2c 2323 | 1 0 | (1 0) (0 0)
2525 23:13:56.499325 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2526 23:13:56.502865 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2527 23:13:56.506319 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2528 23:13:56.509159 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2529 23:13:56.516317 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2530 23:13:56.519349 1 0 24 | B1->B0 | 2323 2929 | 0 0 | (0 0) (1 1)
2531 23:13:56.522737 1 0 28 | B1->B0 | 2a2a 4646 | 0 0 | (0 0) (0 0)
2532 23:13:56.529356 1 1 0 | B1->B0 | 3636 4646 | 0 0 | (0 0) (0 0)
2533 23:13:56.532828 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2534 23:13:56.536405 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2535 23:13:56.543296 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2536 23:13:56.546417 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2537 23:13:56.549563 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2538 23:13:56.556116 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2539 23:13:56.560065 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2540 23:13:56.562875 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2541 23:13:56.569976 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2542 23:13:56.573235 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2543 23:13:56.576355 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2544 23:13:56.579680 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2545 23:13:56.586262 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2546 23:13:56.589762 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2547 23:13:56.593136 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2548 23:13:56.600053 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2549 23:13:56.603252 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2550 23:13:56.606707 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2551 23:13:56.613617 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2552 23:13:56.616532 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2553 23:13:56.620029 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2554 23:13:56.626874 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2555 23:13:56.629711 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2556 23:13:56.633716 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2557 23:13:56.636946 Total UI for P1: 0, mck2ui 16
2558 23:13:56.639701 best dqsien dly found for B0: ( 1, 3, 26)
2559 23:13:56.643309 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2560 23:13:56.646573 Total UI for P1: 0, mck2ui 16
2561 23:13:56.650116 best dqsien dly found for B1: ( 1, 4, 0)
2562 23:13:56.653183 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2563 23:13:56.660494 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2564 23:13:56.661069
2565 23:13:56.663637 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2566 23:13:56.666896 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2567 23:13:56.670064 [Gating] SW calibration Done
2568 23:13:56.670483 ==
2569 23:13:56.673141 Dram Type= 6, Freq= 0, CH_0, rank 0
2570 23:13:56.676820 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2571 23:13:56.677244 ==
2572 23:13:56.677607 RX Vref Scan: 0
2573 23:13:56.677942
2574 23:13:56.680096 RX Vref 0 -> 0, step: 1
2575 23:13:56.680517
2576 23:13:56.683123 RX Delay -40 -> 252, step: 8
2577 23:13:56.686568 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2578 23:13:56.690045 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2579 23:13:56.696714 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2580 23:13:56.700504 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2581 23:13:56.703615 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2582 23:13:56.706861 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2583 23:13:56.710696 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2584 23:13:56.713729 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2585 23:13:56.720265 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2586 23:13:56.723431 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
2587 23:13:56.726677 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
2588 23:13:56.729887 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2589 23:13:56.733496 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2590 23:13:56.740524 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2591 23:13:56.744051 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2592 23:13:56.747190 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2593 23:13:56.747620 ==
2594 23:13:56.750631 Dram Type= 6, Freq= 0, CH_0, rank 0
2595 23:13:56.753959 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2596 23:13:56.754499 ==
2597 23:13:56.757387 DQS Delay:
2598 23:13:56.757962 DQS0 = 0, DQS1 = 0
2599 23:13:56.760866 DQM Delay:
2600 23:13:56.761402 DQM0 = 121, DQM1 = 114
2601 23:13:56.761801 DQ Delay:
2602 23:13:56.767265 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2603 23:13:56.770127 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2604 23:13:56.773747 DQ8 =99, DQ9 =107, DQ10 =115, DQ11 =107
2605 23:13:56.777248 DQ12 =119, DQ13 =123, DQ14 =123, DQ15 =119
2606 23:13:56.777700
2607 23:13:56.778043
2608 23:13:56.778355 ==
2609 23:13:56.780103 Dram Type= 6, Freq= 0, CH_0, rank 0
2610 23:13:56.783454 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2611 23:13:56.783948 ==
2612 23:13:56.784297
2613 23:13:56.784610
2614 23:13:56.786757 TX Vref Scan disable
2615 23:13:56.790660 == TX Byte 0 ==
2616 23:13:56.793761 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2617 23:13:56.797287 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2618 23:13:56.800392 == TX Byte 1 ==
2619 23:13:56.803790 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2620 23:13:56.806869 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2621 23:13:56.807292 ==
2622 23:13:56.810187 Dram Type= 6, Freq= 0, CH_0, rank 0
2623 23:13:56.813975 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2624 23:13:56.816831 ==
2625 23:13:56.827518 TX Vref=22, minBit 0, minWin=25, winSum=410
2626 23:13:56.830544 TX Vref=24, minBit 1, minWin=25, winSum=413
2627 23:13:56.834110 TX Vref=26, minBit 4, minWin=25, winSum=420
2628 23:13:56.837308 TX Vref=28, minBit 0, minWin=26, winSum=423
2629 23:13:56.840630 TX Vref=30, minBit 0, minWin=26, winSum=425
2630 23:13:56.844558 TX Vref=32, minBit 0, minWin=26, winSum=425
2631 23:13:56.850836 [TxChooseVref] Worse bit 0, Min win 26, Win sum 425, Final Vref 30
2632 23:13:56.851354
2633 23:13:56.853903 Final TX Range 1 Vref 30
2634 23:13:56.854323
2635 23:13:56.854658 ==
2636 23:13:56.857862 Dram Type= 6, Freq= 0, CH_0, rank 0
2637 23:13:56.861271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2638 23:13:56.861849 ==
2639 23:13:56.862195
2640 23:13:56.862506
2641 23:13:56.864139 TX Vref Scan disable
2642 23:13:56.867783 == TX Byte 0 ==
2643 23:13:56.870639 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2644 23:13:56.874131 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2645 23:13:56.877617 == TX Byte 1 ==
2646 23:13:56.880570 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2647 23:13:56.884022 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2648 23:13:56.884512
2649 23:13:56.887095 [DATLAT]
2650 23:13:56.887512 Freq=1200, CH0 RK0
2651 23:13:56.887879
2652 23:13:56.890357 DATLAT Default: 0xd
2653 23:13:56.890778 0, 0xFFFF, sum = 0
2654 23:13:56.893938 1, 0xFFFF, sum = 0
2655 23:13:56.894368 2, 0xFFFF, sum = 0
2656 23:13:56.897089 3, 0xFFFF, sum = 0
2657 23:13:56.897517 4, 0xFFFF, sum = 0
2658 23:13:56.900690 5, 0xFFFF, sum = 0
2659 23:13:56.901122 6, 0xFFFF, sum = 0
2660 23:13:56.904288 7, 0xFFFF, sum = 0
2661 23:13:56.904815 8, 0xFFFF, sum = 0
2662 23:13:56.907759 9, 0xFFFF, sum = 0
2663 23:13:56.911039 10, 0xFFFF, sum = 0
2664 23:13:56.911590 11, 0xFFFF, sum = 0
2665 23:13:56.911945 12, 0x0, sum = 1
2666 23:13:56.914202 13, 0x0, sum = 2
2667 23:13:56.914793 14, 0x0, sum = 3
2668 23:13:56.917536 15, 0x0, sum = 4
2669 23:13:56.918014 best_step = 13
2670 23:13:56.918355
2671 23:13:56.918670 ==
2672 23:13:56.920775 Dram Type= 6, Freq= 0, CH_0, rank 0
2673 23:13:56.927301 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2674 23:13:56.927724 ==
2675 23:13:56.928065 RX Vref Scan: 1
2676 23:13:56.928455
2677 23:13:56.930711 Set Vref Range= 32 -> 127
2678 23:13:56.931269
2679 23:13:56.934207 RX Vref 32 -> 127, step: 1
2680 23:13:56.934629
2681 23:13:56.937813 RX Delay -13 -> 252, step: 4
2682 23:13:56.938235
2683 23:13:56.940780 Set Vref, RX VrefLevel [Byte0]: 32
2684 23:13:56.941202 [Byte1]: 32
2685 23:13:56.945895
2686 23:13:56.946381 Set Vref, RX VrefLevel [Byte0]: 33
2687 23:13:56.949071 [Byte1]: 33
2688 23:13:56.953331
2689 23:13:56.953777 Set Vref, RX VrefLevel [Byte0]: 34
2690 23:13:56.956558 [Byte1]: 34
2691 23:13:56.961721
2692 23:13:56.962220 Set Vref, RX VrefLevel [Byte0]: 35
2693 23:13:56.964757 [Byte1]: 35
2694 23:13:56.969545
2695 23:13:56.970114 Set Vref, RX VrefLevel [Byte0]: 36
2696 23:13:56.972885 [Byte1]: 36
2697 23:13:56.976828
2698 23:13:56.977310 Set Vref, RX VrefLevel [Byte0]: 37
2699 23:13:56.980321 [Byte1]: 37
2700 23:13:56.985151
2701 23:13:56.985752 Set Vref, RX VrefLevel [Byte0]: 38
2702 23:13:56.988949 [Byte1]: 38
2703 23:13:56.992823
2704 23:13:56.993331 Set Vref, RX VrefLevel [Byte0]: 39
2705 23:13:56.996692 [Byte1]: 39
2706 23:13:57.000906
2707 23:13:57.001466 Set Vref, RX VrefLevel [Byte0]: 40
2708 23:13:57.004384 [Byte1]: 40
2709 23:13:57.008926
2710 23:13:57.009480 Set Vref, RX VrefLevel [Byte0]: 41
2711 23:13:57.012253 [Byte1]: 41
2712 23:13:57.016784
2713 23:13:57.017261 Set Vref, RX VrefLevel [Byte0]: 42
2714 23:13:57.019703 [Byte1]: 42
2715 23:13:57.024464
2716 23:13:57.024926 Set Vref, RX VrefLevel [Byte0]: 43
2717 23:13:57.027743 [Byte1]: 43
2718 23:13:57.032706
2719 23:13:57.033277 Set Vref, RX VrefLevel [Byte0]: 44
2720 23:13:57.036095 [Byte1]: 44
2721 23:13:57.040472
2722 23:13:57.040935 Set Vref, RX VrefLevel [Byte0]: 45
2723 23:13:57.043564 [Byte1]: 45
2724 23:13:57.048104
2725 23:13:57.048564 Set Vref, RX VrefLevel [Byte0]: 46
2726 23:13:57.051355 [Byte1]: 46
2727 23:13:57.055877
2728 23:13:57.056398 Set Vref, RX VrefLevel [Byte0]: 47
2729 23:13:57.059347 [Byte1]: 47
2730 23:13:57.063501
2731 23:13:57.063933 Set Vref, RX VrefLevel [Byte0]: 48
2732 23:13:57.067607 [Byte1]: 48
2733 23:13:57.071702
2734 23:13:57.072164 Set Vref, RX VrefLevel [Byte0]: 49
2735 23:13:57.075301 [Byte1]: 49
2736 23:13:57.079891
2737 23:13:57.080446 Set Vref, RX VrefLevel [Byte0]: 50
2738 23:13:57.083055 [Byte1]: 50
2739 23:13:57.087604
2740 23:13:57.088012 Set Vref, RX VrefLevel [Byte0]: 51
2741 23:13:57.090787 [Byte1]: 51
2742 23:13:57.095751
2743 23:13:57.096303 Set Vref, RX VrefLevel [Byte0]: 52
2744 23:13:57.098894 [Byte1]: 52
2745 23:13:57.103308
2746 23:13:57.103833 Set Vref, RX VrefLevel [Byte0]: 53
2747 23:13:57.106846 [Byte1]: 53
2748 23:13:57.111437
2749 23:13:57.111900 Set Vref, RX VrefLevel [Byte0]: 54
2750 23:13:57.114361 [Byte1]: 54
2751 23:13:57.119101
2752 23:13:57.119634 Set Vref, RX VrefLevel [Byte0]: 55
2753 23:13:57.122290 [Byte1]: 55
2754 23:13:57.127393
2755 23:13:57.127811 Set Vref, RX VrefLevel [Byte0]: 56
2756 23:13:57.130165 [Byte1]: 56
2757 23:13:57.135225
2758 23:13:57.135665 Set Vref, RX VrefLevel [Byte0]: 57
2759 23:13:57.138319 [Byte1]: 57
2760 23:13:57.142983
2761 23:13:57.143408 Set Vref, RX VrefLevel [Byte0]: 58
2762 23:13:57.145881 [Byte1]: 58
2763 23:13:57.150642
2764 23:13:57.151059 Set Vref, RX VrefLevel [Byte0]: 59
2765 23:13:57.154026 [Byte1]: 59
2766 23:13:57.158824
2767 23:13:57.159426 Set Vref, RX VrefLevel [Byte0]: 60
2768 23:13:57.162062 [Byte1]: 60
2769 23:13:57.166339
2770 23:13:57.166756 Set Vref, RX VrefLevel [Byte0]: 61
2771 23:13:57.169855 [Byte1]: 61
2772 23:13:57.174172
2773 23:13:57.174719 Set Vref, RX VrefLevel [Byte0]: 62
2774 23:13:57.177464 [Byte1]: 62
2775 23:13:57.182315
2776 23:13:57.182874 Set Vref, RX VrefLevel [Byte0]: 63
2777 23:13:57.185357 [Byte1]: 63
2778 23:13:57.190427
2779 23:13:57.190859 Set Vref, RX VrefLevel [Byte0]: 64
2780 23:13:57.193163 [Byte1]: 64
2781 23:13:57.197827
2782 23:13:57.198255 Set Vref, RX VrefLevel [Byte0]: 65
2783 23:13:57.201504 [Byte1]: 65
2784 23:13:57.206365
2785 23:13:57.206908 Set Vref, RX VrefLevel [Byte0]: 66
2786 23:13:57.209106 [Byte1]: 66
2787 23:13:57.213711
2788 23:13:57.214211 Set Vref, RX VrefLevel [Byte0]: 67
2789 23:13:57.216776 [Byte1]: 67
2790 23:13:57.221788
2791 23:13:57.222345 Set Vref, RX VrefLevel [Byte0]: 68
2792 23:13:57.225248 [Byte1]: 68
2793 23:13:57.229360
2794 23:13:57.229941 Set Vref, RX VrefLevel [Byte0]: 69
2795 23:13:57.232785 [Byte1]: 69
2796 23:13:57.237663
2797 23:13:57.238099 Final RX Vref Byte 0 = 56 to rank0
2798 23:13:57.240829 Final RX Vref Byte 1 = 54 to rank0
2799 23:13:57.244480 Final RX Vref Byte 0 = 56 to rank1
2800 23:13:57.247514 Final RX Vref Byte 1 = 54 to rank1==
2801 23:13:57.250856 Dram Type= 6, Freq= 0, CH_0, rank 0
2802 23:13:57.254302 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2803 23:13:57.257695 ==
2804 23:13:57.258237 DQS Delay:
2805 23:13:57.258688 DQS0 = 0, DQS1 = 0
2806 23:13:57.261231 DQM Delay:
2807 23:13:57.261704 DQM0 = 120, DQM1 = 113
2808 23:13:57.264005 DQ Delay:
2809 23:13:57.267810 DQ0 =120, DQ1 =120, DQ2 =118, DQ3 =118
2810 23:13:57.271476 DQ4 =122, DQ5 =112, DQ6 =126, DQ7 =126
2811 23:13:57.274049 DQ8 =100, DQ9 =102, DQ10 =116, DQ11 =106
2812 23:13:57.277598 DQ12 =120, DQ13 =116, DQ14 =126, DQ15 =122
2813 23:13:57.278154
2814 23:13:57.278606
2815 23:13:57.284217 [DQSOSCAuto] RK0, (LSB)MR18= 0x160f, (MSB)MR19= 0x404, tDQSOscB0 = 404 ps tDQSOscB1 = 401 ps
2816 23:13:57.287354 CH0 RK0: MR19=404, MR18=160F
2817 23:13:57.293927 CH0_RK0: MR19=0x404, MR18=0x160F, DQSOSC=401, MR23=63, INC=40, DEC=27
2818 23:13:57.294365
2819 23:13:57.297394 ----->DramcWriteLeveling(PI) begin...
2820 23:13:57.297958 ==
2821 23:13:57.301098 Dram Type= 6, Freq= 0, CH_0, rank 1
2822 23:13:57.304282 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2823 23:13:57.307295 ==
2824 23:13:57.307732 Write leveling (Byte 0): 33 => 33
2825 23:13:57.310556 Write leveling (Byte 1): 28 => 28
2826 23:13:57.314475 DramcWriteLeveling(PI) end<-----
2827 23:13:57.314946
2828 23:13:57.315392 ==
2829 23:13:57.317510 Dram Type= 6, Freq= 0, CH_0, rank 1
2830 23:13:57.324633 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2831 23:13:57.325177 ==
2832 23:13:57.325670 [Gating] SW mode calibration
2833 23:13:57.334156 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2834 23:13:57.337741 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2835 23:13:57.341197 0 15 0 | B1->B0 | 3232 2f2f | 1 1 | (0 0) (0 0)
2836 23:13:57.347688 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2837 23:13:57.350893 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2838 23:13:57.354390 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2839 23:13:57.361476 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2840 23:13:57.364648 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2841 23:13:57.367687 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2842 23:13:57.374594 0 15 28 | B1->B0 | 3333 3232 | 1 1 | (1 0) (1 0)
2843 23:13:57.378194 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2844 23:13:57.381391 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2845 23:13:57.388112 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2846 23:13:57.390839 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2847 23:13:57.394315 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2848 23:13:57.401273 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2849 23:13:57.404628 1 0 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
2850 23:13:57.407691 1 0 28 | B1->B0 | 3939 3c3c | 0 1 | (0 0) (0 0)
2851 23:13:57.410919 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2852 23:13:57.417827 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2853 23:13:57.421062 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2854 23:13:57.424729 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2855 23:13:57.431015 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2856 23:13:57.434821 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2857 23:13:57.437534 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2858 23:13:57.444831 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2859 23:13:57.447650 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2860 23:13:57.451191 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2861 23:13:57.457945 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2862 23:13:57.461011 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2863 23:13:57.464581 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2864 23:13:57.471508 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2865 23:13:57.474726 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2866 23:13:57.477967 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2867 23:13:57.484536 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2868 23:13:57.487747 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2869 23:13:57.491235 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2870 23:13:57.497813 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2871 23:13:57.501339 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2872 23:13:57.504780 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2873 23:13:57.507940 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2874 23:13:57.514444 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2875 23:13:57.518111 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
2876 23:13:57.521171 Total UI for P1: 0, mck2ui 16
2877 23:13:57.524405 best dqsien dly found for B1: ( 1, 3, 28)
2878 23:13:57.528125 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2879 23:13:57.531280 Total UI for P1: 0, mck2ui 16
2880 23:13:57.535211 best dqsien dly found for B0: ( 1, 3, 30)
2881 23:13:57.538137 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2882 23:13:57.541119 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2883 23:13:57.541625
2884 23:13:57.548294 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2885 23:13:57.551157 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2886 23:13:57.551575 [Gating] SW calibration Done
2887 23:13:57.554578 ==
2888 23:13:57.554996 Dram Type= 6, Freq= 0, CH_0, rank 1
2889 23:13:57.561606 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2890 23:13:57.562055 ==
2891 23:13:57.562400 RX Vref Scan: 0
2892 23:13:57.562716
2893 23:13:57.564549 RX Vref 0 -> 0, step: 1
2894 23:13:57.564967
2895 23:13:57.568281 RX Delay -40 -> 252, step: 8
2896 23:13:57.571080 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2897 23:13:57.574549 iDelay=200, Bit 1, Center 123 (56 ~ 191) 136
2898 23:13:57.581358 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2899 23:13:57.584898 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2900 23:13:57.587583 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2901 23:13:57.591126 iDelay=200, Bit 5, Center 119 (48 ~ 191) 144
2902 23:13:57.594675 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2903 23:13:57.597809 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2904 23:13:57.605068 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
2905 23:13:57.608006 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
2906 23:13:57.611864 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
2907 23:13:57.614622 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2908 23:13:57.618124 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2909 23:13:57.624542 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2910 23:13:57.627658 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2911 23:13:57.631419 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
2912 23:13:57.631838 ==
2913 23:13:57.634843 Dram Type= 6, Freq= 0, CH_0, rank 1
2914 23:13:57.637682 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2915 23:13:57.638110 ==
2916 23:13:57.641307 DQS Delay:
2917 23:13:57.641891 DQS0 = 0, DQS1 = 0
2918 23:13:57.644487 DQM Delay:
2919 23:13:57.645048 DQM0 = 122, DQM1 = 114
2920 23:13:57.647700 DQ Delay:
2921 23:13:57.651616 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2922 23:13:57.655015 DQ4 =127, DQ5 =119, DQ6 =127, DQ7 =127
2923 23:13:57.658265 DQ8 =103, DQ9 =103, DQ10 =115, DQ11 =107
2924 23:13:57.661496 DQ12 =115, DQ13 =123, DQ14 =123, DQ15 =123
2925 23:13:57.662008
2926 23:13:57.662348
2927 23:13:57.662701 ==
2928 23:13:57.664555 Dram Type= 6, Freq= 0, CH_0, rank 1
2929 23:13:57.667962 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2930 23:13:57.668704 ==
2931 23:13:57.669076
2932 23:13:57.669388
2933 23:13:57.671595 TX Vref Scan disable
2934 23:13:57.674799 == TX Byte 0 ==
2935 23:13:57.677671 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2936 23:13:57.681306 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2937 23:13:57.684969 == TX Byte 1 ==
2938 23:13:57.687719 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2939 23:13:57.691639 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2940 23:13:57.692153 ==
2941 23:13:57.694756 Dram Type= 6, Freq= 0, CH_0, rank 1
2942 23:13:57.698405 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2943 23:13:57.701186 ==
2944 23:13:57.711860 TX Vref=22, minBit 1, minWin=25, winSum=410
2945 23:13:57.715089 TX Vref=24, minBit 3, minWin=25, winSum=417
2946 23:13:57.718720 TX Vref=26, minBit 0, minWin=26, winSum=421
2947 23:13:57.721784 TX Vref=28, minBit 1, minWin=26, winSum=422
2948 23:13:57.725462 TX Vref=30, minBit 1, minWin=26, winSum=428
2949 23:13:57.728568 TX Vref=32, minBit 0, minWin=26, winSum=422
2950 23:13:57.735405 [TxChooseVref] Worse bit 1, Min win 26, Win sum 428, Final Vref 30
2951 23:13:57.735956
2952 23:13:57.738644 Final TX Range 1 Vref 30
2953 23:13:57.739070
2954 23:13:57.739403 ==
2955 23:13:57.741827 Dram Type= 6, Freq= 0, CH_0, rank 1
2956 23:13:57.744971 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2957 23:13:57.745394 ==
2958 23:13:57.745810
2959 23:13:57.748730
2960 23:13:57.749148 TX Vref Scan disable
2961 23:13:57.751611 == TX Byte 0 ==
2962 23:13:57.755026 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2963 23:13:57.758300 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2964 23:13:57.762075 == TX Byte 1 ==
2965 23:13:57.765780 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2966 23:13:57.768455 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2967 23:13:57.768881
2968 23:13:57.771734 [DATLAT]
2969 23:13:57.772194 Freq=1200, CH0 RK1
2970 23:13:57.772536
2971 23:13:57.775063 DATLAT Default: 0xd
2972 23:13:57.775480 0, 0xFFFF, sum = 0
2973 23:13:57.779096 1, 0xFFFF, sum = 0
2974 23:13:57.779639 2, 0xFFFF, sum = 0
2975 23:13:57.782060 3, 0xFFFF, sum = 0
2976 23:13:57.782489 4, 0xFFFF, sum = 0
2977 23:13:57.785661 5, 0xFFFF, sum = 0
2978 23:13:57.786089 6, 0xFFFF, sum = 0
2979 23:13:57.788486 7, 0xFFFF, sum = 0
2980 23:13:57.788933 8, 0xFFFF, sum = 0
2981 23:13:57.792136 9, 0xFFFF, sum = 0
2982 23:13:57.792673 10, 0xFFFF, sum = 0
2983 23:13:57.795552 11, 0xFFFF, sum = 0
2984 23:13:57.796183 12, 0x0, sum = 1
2985 23:13:57.799022 13, 0x0, sum = 2
2986 23:13:57.799476 14, 0x0, sum = 3
2987 23:13:57.802120 15, 0x0, sum = 4
2988 23:13:57.802550 best_step = 13
2989 23:13:57.802888
2990 23:13:57.803201 ==
2991 23:13:57.805398 Dram Type= 6, Freq= 0, CH_0, rank 1
2992 23:13:57.812056 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2993 23:13:57.812481 ==
2994 23:13:57.812823 RX Vref Scan: 0
2995 23:13:57.813203
2996 23:13:57.815432 RX Vref 0 -> 0, step: 1
2997 23:13:57.815859
2998 23:13:57.818760 RX Delay -13 -> 252, step: 4
2999 23:13:57.821942 iDelay=195, Bit 0, Center 120 (51 ~ 190) 140
3000 23:13:57.825442 iDelay=195, Bit 1, Center 120 (55 ~ 186) 132
3001 23:13:57.832280 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3002 23:13:57.835423 iDelay=195, Bit 3, Center 118 (51 ~ 186) 136
3003 23:13:57.839238 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3004 23:13:57.842489 iDelay=195, Bit 5, Center 116 (51 ~ 182) 132
3005 23:13:57.845330 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3006 23:13:57.852428 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3007 23:13:57.855692 iDelay=195, Bit 8, Center 100 (35 ~ 166) 132
3008 23:13:57.858619 iDelay=195, Bit 9, Center 100 (35 ~ 166) 132
3009 23:13:57.862041 iDelay=195, Bit 10, Center 112 (47 ~ 178) 132
3010 23:13:57.865753 iDelay=195, Bit 11, Center 104 (39 ~ 170) 132
3011 23:13:57.872599 iDelay=195, Bit 12, Center 116 (55 ~ 178) 124
3012 23:13:57.875497 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3013 23:13:57.879096 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3014 23:13:57.882541 iDelay=195, Bit 15, Center 118 (55 ~ 182) 128
3015 23:13:57.882961 ==
3016 23:13:57.885921 Dram Type= 6, Freq= 0, CH_0, rank 1
3017 23:13:57.889159 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3018 23:13:57.892398 ==
3019 23:13:57.892948 DQS Delay:
3020 23:13:57.893283 DQS0 = 0, DQS1 = 0
3021 23:13:57.895879 DQM Delay:
3022 23:13:57.896392 DQM0 = 120, DQM1 = 111
3023 23:13:57.899308 DQ Delay:
3024 23:13:57.902670 DQ0 =120, DQ1 =120, DQ2 =118, DQ3 =118
3025 23:13:57.905537 DQ4 =122, DQ5 =116, DQ6 =126, DQ7 =126
3026 23:13:57.909645 DQ8 =100, DQ9 =100, DQ10 =112, DQ11 =104
3027 23:13:57.913083 DQ12 =116, DQ13 =118, DQ14 =122, DQ15 =118
3028 23:13:57.913653
3029 23:13:57.914001
3030 23:13:57.919278 [DQSOSCAuto] RK1, (LSB)MR18= 0x10f2, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 403 ps
3031 23:13:57.922941 CH0 RK1: MR19=403, MR18=10F2
3032 23:13:57.929091 CH0_RK1: MR19=0x403, MR18=0x10F2, DQSOSC=403, MR23=63, INC=40, DEC=26
3033 23:13:57.932801 [RxdqsGatingPostProcess] freq 1200
3034 23:13:57.939447 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3035 23:13:57.940041 best DQS0 dly(2T, 0.5T) = (0, 11)
3036 23:13:57.942950 best DQS1 dly(2T, 0.5T) = (0, 12)
3037 23:13:57.945808 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3038 23:13:57.949418 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3039 23:13:57.952904 best DQS0 dly(2T, 0.5T) = (0, 11)
3040 23:13:57.956763 best DQS1 dly(2T, 0.5T) = (0, 11)
3041 23:13:57.959370 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3042 23:13:57.962780 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3043 23:13:57.965802 Pre-setting of DQS Precalculation
3044 23:13:57.969829 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3045 23:13:57.970390 ==
3046 23:13:57.973074 Dram Type= 6, Freq= 0, CH_1, rank 0
3047 23:13:57.980202 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3048 23:13:57.980916 ==
3049 23:13:57.982819 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3050 23:13:57.989297 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3051 23:13:57.998075 [CA 0] Center 37 (7~68) winsize 62
3052 23:13:58.001987 [CA 1] Center 37 (7~68) winsize 62
3053 23:13:58.005155 [CA 2] Center 35 (5~65) winsize 61
3054 23:13:58.008184 [CA 3] Center 34 (4~64) winsize 61
3055 23:13:58.011449 [CA 4] Center 34 (4~64) winsize 61
3056 23:13:58.015116 [CA 5] Center 33 (3~63) winsize 61
3057 23:13:58.015578
3058 23:13:58.018700 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3059 23:13:58.019121
3060 23:13:58.021672 [CATrainingPosCal] consider 1 rank data
3061 23:13:58.025499 u2DelayCellTimex100 = 270/100 ps
3062 23:13:58.028211 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3063 23:13:58.031832 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3064 23:13:58.038682 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3065 23:13:58.041761 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3066 23:13:58.045224 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3067 23:13:58.048471 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3068 23:13:58.048997
3069 23:13:58.051608 CA PerBit enable=1, Macro0, CA PI delay=33
3070 23:13:58.052157
3071 23:13:58.054854 [CBTSetCACLKResult] CA Dly = 33
3072 23:13:58.055318 CS Dly: 7 (0~38)
3073 23:13:58.055691 ==
3074 23:13:58.058764 Dram Type= 6, Freq= 0, CH_1, rank 1
3075 23:13:58.065219 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3076 23:13:58.065856 ==
3077 23:13:58.068671 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3078 23:13:58.075016 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3079 23:13:58.083930 [CA 0] Center 37 (7~68) winsize 62
3080 23:13:58.087287 [CA 1] Center 37 (7~68) winsize 62
3081 23:13:58.090376 [CA 2] Center 35 (5~65) winsize 61
3082 23:13:58.094017 [CA 3] Center 34 (4~65) winsize 62
3083 23:13:58.097141 [CA 4] Center 34 (4~65) winsize 62
3084 23:13:58.100679 [CA 5] Center 34 (4~64) winsize 61
3085 23:13:58.101100
3086 23:13:58.103895 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3087 23:13:58.104316
3088 23:13:58.107355 [CATrainingPosCal] consider 2 rank data
3089 23:13:58.110591 u2DelayCellTimex100 = 270/100 ps
3090 23:13:58.113726 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3091 23:13:58.117208 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3092 23:13:58.123940 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3093 23:13:58.127203 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3094 23:13:58.130801 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3095 23:13:58.133814 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3096 23:13:58.134320
3097 23:13:58.137350 CA PerBit enable=1, Macro0, CA PI delay=33
3098 23:13:58.137819
3099 23:13:58.141001 [CBTSetCACLKResult] CA Dly = 33
3100 23:13:58.141520 CS Dly: 8 (0~40)
3101 23:13:58.141936
3102 23:13:58.143913 ----->DramcWriteLeveling(PI) begin...
3103 23:13:58.147382 ==
3104 23:13:58.147896 Dram Type= 6, Freq= 0, CH_1, rank 0
3105 23:13:58.154251 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3106 23:13:58.154775 ==
3107 23:13:58.157371 Write leveling (Byte 0): 26 => 26
3108 23:13:58.161127 Write leveling (Byte 1): 27 => 27
3109 23:13:58.161702 DramcWriteLeveling(PI) end<-----
3110 23:13:58.164101
3111 23:13:58.164615 ==
3112 23:13:58.167431 Dram Type= 6, Freq= 0, CH_1, rank 0
3113 23:13:58.170806 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3114 23:13:58.171321 ==
3115 23:13:58.174215 [Gating] SW mode calibration
3116 23:13:58.180861 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3117 23:13:58.184290 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3118 23:13:58.190698 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3119 23:13:58.194613 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3120 23:13:58.197507 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3121 23:13:58.204465 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3122 23:13:58.207540 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3123 23:13:58.210731 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3124 23:13:58.217695 0 15 24 | B1->B0 | 3333 2727 | 1 1 | (1 0) (1 0)
3125 23:13:58.221166 0 15 28 | B1->B0 | 2424 2323 | 0 0 | (1 0) (1 0)
3126 23:13:58.224252 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3127 23:13:58.227950 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3128 23:13:58.234281 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3129 23:13:58.237749 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3130 23:13:58.241497 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3131 23:13:58.248148 1 0 20 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
3132 23:13:58.251068 1 0 24 | B1->B0 | 3535 3f3f | 0 1 | (0 0) (0 0)
3133 23:13:58.254387 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3134 23:13:58.261250 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3135 23:13:58.264217 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3136 23:13:58.267736 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3137 23:13:58.274157 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3138 23:13:58.277891 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3139 23:13:58.281399 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3140 23:13:58.287802 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3141 23:13:58.290949 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3142 23:13:58.294181 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3143 23:13:58.301014 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3144 23:13:58.304593 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3145 23:13:58.308204 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3146 23:13:58.314302 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3147 23:13:58.317717 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3148 23:13:58.321196 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3149 23:13:58.324322 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3150 23:13:58.331399 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3151 23:13:58.334672 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3152 23:13:58.337560 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3153 23:13:58.344638 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3154 23:13:58.348225 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3155 23:13:58.351626 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3156 23:13:58.357986 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3157 23:13:58.361029 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3158 23:13:58.364926 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3159 23:13:58.367904 Total UI for P1: 0, mck2ui 16
3160 23:13:58.371546 best dqsien dly found for B0: ( 1, 3, 26)
3161 23:13:58.375073 Total UI for P1: 0, mck2ui 16
3162 23:13:58.377993 best dqsien dly found for B1: ( 1, 3, 28)
3163 23:13:58.381698 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3164 23:13:58.385028 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3165 23:13:58.385638
3166 23:13:58.387885 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3167 23:13:58.394444 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3168 23:13:58.394968 [Gating] SW calibration Done
3169 23:13:58.395345 ==
3170 23:13:58.397667 Dram Type= 6, Freq= 0, CH_1, rank 0
3171 23:13:58.404609 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3172 23:13:58.405154 ==
3173 23:13:58.405527 RX Vref Scan: 0
3174 23:13:58.405990
3175 23:13:58.408170 RX Vref 0 -> 0, step: 1
3176 23:13:58.408632
3177 23:13:58.411150 RX Delay -40 -> 252, step: 8
3178 23:13:58.415022 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3179 23:13:58.418207 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3180 23:13:58.421655 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3181 23:13:58.427976 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3182 23:13:58.431784 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3183 23:13:58.435196 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3184 23:13:58.437888 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3185 23:13:58.441636 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3186 23:13:58.447887 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3187 23:13:58.451001 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3188 23:13:58.454388 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3189 23:13:58.458097 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3190 23:13:58.461200 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3191 23:13:58.468078 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3192 23:13:58.471289 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3193 23:13:58.474600 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
3194 23:13:58.475022 ==
3195 23:13:58.477562 Dram Type= 6, Freq= 0, CH_1, rank 0
3196 23:13:58.481010 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3197 23:13:58.481521 ==
3198 23:13:58.484452 DQS Delay:
3199 23:13:58.484935 DQS0 = 0, DQS1 = 0
3200 23:13:58.487895 DQM Delay:
3201 23:13:58.488318 DQM0 = 119, DQM1 = 117
3202 23:13:58.488654 DQ Delay:
3203 23:13:58.491066 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3204 23:13:58.498219 DQ4 =119, DQ5 =127, DQ6 =127, DQ7 =119
3205 23:13:58.501517 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =111
3206 23:13:58.504269 DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =127
3207 23:13:58.504778
3208 23:13:58.505114
3209 23:13:58.505430 ==
3210 23:13:58.507681 Dram Type= 6, Freq= 0, CH_1, rank 0
3211 23:13:58.511299 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3212 23:13:58.511724 ==
3213 23:13:58.512064
3214 23:13:58.512373
3215 23:13:58.514303 TX Vref Scan disable
3216 23:13:58.517621 == TX Byte 0 ==
3217 23:13:58.521508 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3218 23:13:58.524356 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3219 23:13:58.527866 == TX Byte 1 ==
3220 23:13:58.530797 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3221 23:13:58.534256 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3222 23:13:58.534678 ==
3223 23:13:58.537757 Dram Type= 6, Freq= 0, CH_1, rank 0
3224 23:13:58.540922 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3225 23:13:58.541370 ==
3226 23:13:58.554259 TX Vref=22, minBit 11, minWin=24, winSum=410
3227 23:13:58.557723 TX Vref=24, minBit 9, minWin=25, winSum=419
3228 23:13:58.560560 TX Vref=26, minBit 9, minWin=25, winSum=423
3229 23:13:58.564348 TX Vref=28, minBit 2, minWin=26, winSum=426
3230 23:13:58.567442 TX Vref=30, minBit 9, minWin=26, winSum=429
3231 23:13:58.571061 TX Vref=32, minBit 10, minWin=25, winSum=432
3232 23:13:58.577413 [TxChooseVref] Worse bit 9, Min win 26, Win sum 429, Final Vref 30
3233 23:13:58.577957
3234 23:13:58.581083 Final TX Range 1 Vref 30
3235 23:13:58.581643
3236 23:13:58.581995 ==
3237 23:13:58.584439 Dram Type= 6, Freq= 0, CH_1, rank 0
3238 23:13:58.588024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3239 23:13:58.588451 ==
3240 23:13:58.588790
3241 23:13:58.589103
3242 23:13:58.591027 TX Vref Scan disable
3243 23:13:58.594744 == TX Byte 0 ==
3244 23:13:58.597820 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3245 23:13:58.601509 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3246 23:13:58.604430 == TX Byte 1 ==
3247 23:13:58.607666 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3248 23:13:58.611337 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3249 23:13:58.611863
3250 23:13:58.614832 [DATLAT]
3251 23:13:58.615349 Freq=1200, CH1 RK0
3252 23:13:58.615690
3253 23:13:58.618112 DATLAT Default: 0xd
3254 23:13:58.618525 0, 0xFFFF, sum = 0
3255 23:13:58.621101 1, 0xFFFF, sum = 0
3256 23:13:58.621523 2, 0xFFFF, sum = 0
3257 23:13:58.624942 3, 0xFFFF, sum = 0
3258 23:13:58.625475 4, 0xFFFF, sum = 0
3259 23:13:58.627597 5, 0xFFFF, sum = 0
3260 23:13:58.628059 6, 0xFFFF, sum = 0
3261 23:13:58.631442 7, 0xFFFF, sum = 0
3262 23:13:58.632074 8, 0xFFFF, sum = 0
3263 23:13:58.635002 9, 0xFFFF, sum = 0
3264 23:13:58.635565 10, 0xFFFF, sum = 0
3265 23:13:58.637895 11, 0xFFFF, sum = 0
3266 23:13:58.638553 12, 0x0, sum = 1
3267 23:13:58.641325 13, 0x0, sum = 2
3268 23:13:58.641876 14, 0x0, sum = 3
3269 23:13:58.644708 15, 0x0, sum = 4
3270 23:13:58.645177 best_step = 13
3271 23:13:58.645544
3272 23:13:58.645965 ==
3273 23:13:58.647737 Dram Type= 6, Freq= 0, CH_1, rank 0
3274 23:13:58.654560 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3275 23:13:58.655091 ==
3276 23:13:58.655466 RX Vref Scan: 1
3277 23:13:58.655905
3278 23:13:58.657683 Set Vref Range= 32 -> 127
3279 23:13:58.658150
3280 23:13:58.661395 RX Vref 32 -> 127, step: 1
3281 23:13:58.661902
3282 23:13:58.662245 RX Delay -5 -> 252, step: 4
3283 23:13:58.664461
3284 23:13:58.664876 Set Vref, RX VrefLevel [Byte0]: 32
3285 23:13:58.667547 [Byte1]: 32
3286 23:13:58.672445
3287 23:13:58.672965 Set Vref, RX VrefLevel [Byte0]: 33
3288 23:13:58.675981 [Byte1]: 33
3289 23:13:58.680237
3290 23:13:58.680752 Set Vref, RX VrefLevel [Byte0]: 34
3291 23:13:58.683455 [Byte1]: 34
3292 23:13:58.687913
3293 23:13:58.688335 Set Vref, RX VrefLevel [Byte0]: 35
3294 23:13:58.691374 [Byte1]: 35
3295 23:13:58.695424
3296 23:13:58.695839 Set Vref, RX VrefLevel [Byte0]: 36
3297 23:13:58.698928 [Byte1]: 36
3298 23:13:58.703610
3299 23:13:58.704028 Set Vref, RX VrefLevel [Byte0]: 37
3300 23:13:58.706698 [Byte1]: 37
3301 23:13:58.711306
3302 23:13:58.711603 Set Vref, RX VrefLevel [Byte0]: 38
3303 23:13:58.714806 [Byte1]: 38
3304 23:13:58.718830
3305 23:13:58.719055 Set Vref, RX VrefLevel [Byte0]: 39
3306 23:13:58.722425 [Byte1]: 39
3307 23:13:58.726874
3308 23:13:58.727023 Set Vref, RX VrefLevel [Byte0]: 40
3309 23:13:58.730501 [Byte1]: 40
3310 23:13:58.734540
3311 23:13:58.734690 Set Vref, RX VrefLevel [Byte0]: 41
3312 23:13:58.738111 [Byte1]: 41
3313 23:13:58.742575
3314 23:13:58.742727 Set Vref, RX VrefLevel [Byte0]: 42
3315 23:13:58.746285 [Byte1]: 42
3316 23:13:58.750417
3317 23:13:58.750567 Set Vref, RX VrefLevel [Byte0]: 43
3318 23:13:58.753887 [Byte1]: 43
3319 23:13:58.758547
3320 23:13:58.758697 Set Vref, RX VrefLevel [Byte0]: 44
3321 23:13:58.761648 [Byte1]: 44
3322 23:13:58.766264
3323 23:13:58.766415 Set Vref, RX VrefLevel [Byte0]: 45
3324 23:13:58.769777 [Byte1]: 45
3325 23:13:58.774114
3326 23:13:58.774263 Set Vref, RX VrefLevel [Byte0]: 46
3327 23:13:58.777138 [Byte1]: 46
3328 23:13:58.781639
3329 23:13:58.781790 Set Vref, RX VrefLevel [Byte0]: 47
3330 23:13:58.785067 [Byte1]: 47
3331 23:13:58.789653
3332 23:13:58.789803 Set Vref, RX VrefLevel [Byte0]: 48
3333 23:13:58.792902 [Byte1]: 48
3334 23:13:58.797644
3335 23:13:58.797795 Set Vref, RX VrefLevel [Byte0]: 49
3336 23:13:58.800773 [Byte1]: 49
3337 23:13:58.805588
3338 23:13:58.805739 Set Vref, RX VrefLevel [Byte0]: 50
3339 23:13:58.808727 [Byte1]: 50
3340 23:13:58.813377
3341 23:13:58.813525 Set Vref, RX VrefLevel [Byte0]: 51
3342 23:13:58.816865 [Byte1]: 51
3343 23:13:58.820850
3344 23:13:58.821006 Set Vref, RX VrefLevel [Byte0]: 52
3345 23:13:58.824642 [Byte1]: 52
3346 23:13:58.829263
3347 23:13:58.829413 Set Vref, RX VrefLevel [Byte0]: 53
3348 23:13:58.832274 [Byte1]: 53
3349 23:13:58.837013
3350 23:13:58.837092 Set Vref, RX VrefLevel [Byte0]: 54
3351 23:13:58.839801 [Byte1]: 54
3352 23:13:58.844549
3353 23:13:58.844634 Set Vref, RX VrefLevel [Byte0]: 55
3354 23:13:58.847889 [Byte1]: 55
3355 23:13:58.852098
3356 23:13:58.852183 Set Vref, RX VrefLevel [Byte0]: 56
3357 23:13:58.855544 [Byte1]: 56
3358 23:13:58.860182
3359 23:13:58.860266 Set Vref, RX VrefLevel [Byte0]: 57
3360 23:13:58.863379 [Byte1]: 57
3361 23:13:58.867992
3362 23:13:58.868081 Set Vref, RX VrefLevel [Byte0]: 58
3363 23:13:58.871303 [Byte1]: 58
3364 23:13:58.876162
3365 23:13:58.876266 Set Vref, RX VrefLevel [Byte0]: 59
3366 23:13:58.879300 [Byte1]: 59
3367 23:13:58.883673
3368 23:13:58.883778 Set Vref, RX VrefLevel [Byte0]: 60
3369 23:13:58.887181 [Byte1]: 60
3370 23:13:58.891576
3371 23:13:58.891682 Set Vref, RX VrefLevel [Byte0]: 61
3372 23:13:58.894891 [Byte1]: 61
3373 23:13:58.899379
3374 23:13:58.899505 Set Vref, RX VrefLevel [Byte0]: 62
3375 23:13:58.902804 [Byte1]: 62
3376 23:13:58.907415
3377 23:13:58.907519 Set Vref, RX VrefLevel [Byte0]: 63
3378 23:13:58.910390 [Byte1]: 63
3379 23:13:58.915049
3380 23:13:58.915157 Set Vref, RX VrefLevel [Byte0]: 64
3381 23:13:58.918324 [Byte1]: 64
3382 23:13:58.923129
3383 23:13:58.923237 Set Vref, RX VrefLevel [Byte0]: 65
3384 23:13:58.926132 [Byte1]: 65
3385 23:13:58.930670
3386 23:13:58.930774 Set Vref, RX VrefLevel [Byte0]: 66
3387 23:13:58.934307 [Byte1]: 66
3388 23:13:58.939001
3389 23:13:58.939105 Set Vref, RX VrefLevel [Byte0]: 67
3390 23:13:58.942013 [Byte1]: 67
3391 23:13:58.946915
3392 23:13:58.947019 Final RX Vref Byte 0 = 54 to rank0
3393 23:13:58.949858 Final RX Vref Byte 1 = 46 to rank0
3394 23:13:58.953269 Final RX Vref Byte 0 = 54 to rank1
3395 23:13:58.956527 Final RX Vref Byte 1 = 46 to rank1==
3396 23:13:58.960246 Dram Type= 6, Freq= 0, CH_1, rank 0
3397 23:13:58.966529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3398 23:13:58.966634 ==
3399 23:13:58.966717 DQS Delay:
3400 23:13:58.966792 DQS0 = 0, DQS1 = 0
3401 23:13:58.970038 DQM Delay:
3402 23:13:58.970139 DQM0 = 120, DQM1 = 116
3403 23:13:58.973461 DQ Delay:
3404 23:13:58.976952 DQ0 =124, DQ1 =114, DQ2 =110, DQ3 =116
3405 23:13:58.980295 DQ4 =120, DQ5 =128, DQ6 =128, DQ7 =120
3406 23:13:58.983610 DQ8 =102, DQ9 =106, DQ10 =116, DQ11 =108
3407 23:13:58.986992 DQ12 =122, DQ13 =124, DQ14 =124, DQ15 =126
3408 23:13:58.987402
3409 23:13:58.987729
3410 23:13:58.996562 [DQSOSCAuto] RK0, (LSB)MR18= 0xfd10, (MSB)MR19= 0x304, tDQSOscB0 = 403 ps tDQSOscB1 = 411 ps
3411 23:13:58.996940 CH1 RK0: MR19=304, MR18=FD10
3412 23:13:59.003236 CH1_RK0: MR19=0x304, MR18=0xFD10, DQSOSC=403, MR23=63, INC=40, DEC=26
3413 23:13:59.003462
3414 23:13:59.006296 ----->DramcWriteLeveling(PI) begin...
3415 23:13:59.006479 ==
3416 23:13:59.009795 Dram Type= 6, Freq= 0, CH_1, rank 1
3417 23:13:59.013379 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3418 23:13:59.016796 ==
3419 23:13:59.016925 Write leveling (Byte 0): 27 => 27
3420 23:13:59.019904 Write leveling (Byte 1): 29 => 29
3421 23:13:59.023282 DramcWriteLeveling(PI) end<-----
3422 23:13:59.023396
3423 23:13:59.023485 ==
3424 23:13:59.026337 Dram Type= 6, Freq= 0, CH_1, rank 1
3425 23:13:59.033453 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3426 23:13:59.033595 ==
3427 23:13:59.036577 [Gating] SW mode calibration
3428 23:13:59.042953 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3429 23:13:59.046662 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3430 23:13:59.052931 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3431 23:13:59.056549 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3432 23:13:59.059428 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3433 23:13:59.066460 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3434 23:13:59.069944 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3435 23:13:59.072974 0 15 20 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3436 23:13:59.080102 0 15 24 | B1->B0 | 2c2c 3333 | 0 0 | (0 1) (0 1)
3437 23:13:59.082741 0 15 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
3438 23:13:59.086340 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3439 23:13:59.089490 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3440 23:13:59.095899 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3441 23:13:59.099675 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3442 23:13:59.102799 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3443 23:13:59.109602 1 0 20 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
3444 23:13:59.113155 1 0 24 | B1->B0 | 4545 2929 | 0 0 | (0 0) (0 0)
3445 23:13:59.116029 1 0 28 | B1->B0 | 4646 4040 | 0 0 | (0 0) (0 0)
3446 23:13:59.122568 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3447 23:13:59.126017 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3448 23:13:59.129241 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3449 23:13:59.136149 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3450 23:13:59.139505 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3451 23:13:59.142881 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3452 23:13:59.149765 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3453 23:13:59.152808 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3454 23:13:59.156144 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3455 23:13:59.163260 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3456 23:13:59.166094 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3457 23:13:59.169452 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3458 23:13:59.176142 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3459 23:13:59.179713 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3460 23:13:59.183164 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3461 23:13:59.189411 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3462 23:13:59.192810 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3463 23:13:59.196387 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3464 23:13:59.202755 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3465 23:13:59.206336 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3466 23:13:59.209559 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3467 23:13:59.212573 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3468 23:13:59.219070 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3469 23:13:59.222442 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3470 23:13:59.226023 Total UI for P1: 0, mck2ui 16
3471 23:13:59.229179 best dqsien dly found for B1: ( 1, 3, 22)
3472 23:13:59.232602 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3473 23:13:59.235939 Total UI for P1: 0, mck2ui 16
3474 23:13:59.239095 best dqsien dly found for B0: ( 1, 3, 28)
3475 23:13:59.242715 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3476 23:13:59.245572 best DQS1 dly(MCK, UI, PI) = (1, 3, 22)
3477 23:13:59.245693
3478 23:13:59.252839 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3479 23:13:59.256199 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 22)
3480 23:13:59.259523 [Gating] SW calibration Done
3481 23:13:59.260066 ==
3482 23:13:59.263167 Dram Type= 6, Freq= 0, CH_1, rank 1
3483 23:13:59.266084 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3484 23:13:59.266530 ==
3485 23:13:59.266907 RX Vref Scan: 0
3486 23:13:59.267384
3487 23:13:59.269493 RX Vref 0 -> 0, step: 1
3488 23:13:59.270048
3489 23:13:59.272916 RX Delay -40 -> 252, step: 8
3490 23:13:59.276429 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3491 23:13:59.279479 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3492 23:13:59.286480 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3493 23:13:59.289135 iDelay=200, Bit 3, Center 119 (56 ~ 183) 128
3494 23:13:59.292661 iDelay=200, Bit 4, Center 119 (56 ~ 183) 128
3495 23:13:59.296174 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3496 23:13:59.299147 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3497 23:13:59.306019 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
3498 23:13:59.308941 iDelay=200, Bit 8, Center 107 (40 ~ 175) 136
3499 23:13:59.312765 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3500 23:13:59.315607 iDelay=200, Bit 10, Center 119 (56 ~ 183) 128
3501 23:13:59.319350 iDelay=200, Bit 11, Center 115 (48 ~ 183) 136
3502 23:13:59.325443 iDelay=200, Bit 12, Center 127 (56 ~ 199) 144
3503 23:13:59.329157 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
3504 23:13:59.332035 iDelay=200, Bit 14, Center 119 (56 ~ 183) 128
3505 23:13:59.335544 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3506 23:13:59.335803 ==
3507 23:13:59.338692 Dram Type= 6, Freq= 0, CH_1, rank 1
3508 23:13:59.345422 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3509 23:13:59.345605 ==
3510 23:13:59.345731 DQS Delay:
3511 23:13:59.348706 DQS0 = 0, DQS1 = 0
3512 23:13:59.348812 DQM Delay:
3513 23:13:59.348899 DQM0 = 121, DQM1 = 117
3514 23:13:59.351847 DQ Delay:
3515 23:13:59.355450 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3516 23:13:59.358758 DQ4 =119, DQ5 =131, DQ6 =131, DQ7 =123
3517 23:13:59.362317 DQ8 =107, DQ9 =107, DQ10 =119, DQ11 =115
3518 23:13:59.365848 DQ12 =127, DQ13 =123, DQ14 =119, DQ15 =123
3519 23:13:59.365964
3520 23:13:59.366056
3521 23:13:59.366142 ==
3522 23:13:59.368741 Dram Type= 6, Freq= 0, CH_1, rank 1
3523 23:13:59.372018 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3524 23:13:59.375704 ==
3525 23:13:59.375891
3526 23:13:59.375994
3527 23:13:59.376087 TX Vref Scan disable
3528 23:13:59.379173 == TX Byte 0 ==
3529 23:13:59.381818 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3530 23:13:59.385605 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3531 23:13:59.389246 == TX Byte 1 ==
3532 23:13:59.392214 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3533 23:13:59.395644 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3534 23:13:59.395903 ==
3535 23:13:59.399093 Dram Type= 6, Freq= 0, CH_1, rank 1
3536 23:13:59.405621 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3537 23:13:59.405945 ==
3538 23:13:59.416539 TX Vref=22, minBit 10, minWin=25, winSum=420
3539 23:13:59.419322 TX Vref=24, minBit 1, minWin=26, winSum=425
3540 23:13:59.423046 TX Vref=26, minBit 4, minWin=26, winSum=431
3541 23:13:59.426465 TX Vref=28, minBit 9, minWin=26, winSum=432
3542 23:13:59.429541 TX Vref=30, minBit 9, minWin=26, winSum=434
3543 23:13:59.436363 TX Vref=32, minBit 10, minWin=26, winSum=433
3544 23:13:59.439939 [TxChooseVref] Worse bit 9, Min win 26, Win sum 434, Final Vref 30
3545 23:13:59.440658
3546 23:13:59.443270 Final TX Range 1 Vref 30
3547 23:13:59.443727
3548 23:13:59.444083 ==
3549 23:13:59.446218 Dram Type= 6, Freq= 0, CH_1, rank 1
3550 23:13:59.449524 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3551 23:13:59.453113 ==
3552 23:13:59.453608
3553 23:13:59.453996
3554 23:13:59.454339 TX Vref Scan disable
3555 23:13:59.456344 == TX Byte 0 ==
3556 23:13:59.460091 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3557 23:13:59.463494 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3558 23:13:59.466171 == TX Byte 1 ==
3559 23:13:59.469939 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3560 23:13:59.473093 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3561 23:13:59.476920
3562 23:13:59.477472 [DATLAT]
3563 23:13:59.477903 Freq=1200, CH1 RK1
3564 23:13:59.478255
3565 23:13:59.479609 DATLAT Default: 0xd
3566 23:13:59.480069 0, 0xFFFF, sum = 0
3567 23:13:59.483151 1, 0xFFFF, sum = 0
3568 23:13:59.483706 2, 0xFFFF, sum = 0
3569 23:13:59.486599 3, 0xFFFF, sum = 0
3570 23:13:59.487087 4, 0xFFFF, sum = 0
3571 23:13:59.489512 5, 0xFFFF, sum = 0
3572 23:13:59.493263 6, 0xFFFF, sum = 0
3573 23:13:59.493789 7, 0xFFFF, sum = 0
3574 23:13:59.496181 8, 0xFFFF, sum = 0
3575 23:13:59.496652 9, 0xFFFF, sum = 0
3576 23:13:59.499527 10, 0xFFFF, sum = 0
3577 23:13:59.500007 11, 0xFFFF, sum = 0
3578 23:13:59.503196 12, 0x0, sum = 1
3579 23:13:59.503683 13, 0x0, sum = 2
3580 23:13:59.506502 14, 0x0, sum = 3
3581 23:13:59.506943 15, 0x0, sum = 4
3582 23:13:59.507290 best_step = 13
3583 23:13:59.509629
3584 23:13:59.510051 ==
3585 23:13:59.513173 Dram Type= 6, Freq= 0, CH_1, rank 1
3586 23:13:59.516608 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3587 23:13:59.517131 ==
3588 23:13:59.517466 RX Vref Scan: 0
3589 23:13:59.517846
3590 23:13:59.519406 RX Vref 0 -> 0, step: 1
3591 23:13:59.519819
3592 23:13:59.522866 RX Delay -5 -> 252, step: 4
3593 23:13:59.526217 iDelay=195, Bit 0, Center 122 (59 ~ 186) 128
3594 23:13:59.533185 iDelay=195, Bit 1, Center 116 (55 ~ 178) 124
3595 23:13:59.536192 iDelay=195, Bit 2, Center 110 (51 ~ 170) 120
3596 23:13:59.539581 iDelay=195, Bit 3, Center 118 (59 ~ 178) 120
3597 23:13:59.542933 iDelay=195, Bit 4, Center 116 (55 ~ 178) 124
3598 23:13:59.545914 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3599 23:13:59.552735 iDelay=195, Bit 6, Center 130 (67 ~ 194) 128
3600 23:13:59.556581 iDelay=195, Bit 7, Center 120 (59 ~ 182) 124
3601 23:13:59.559548 iDelay=195, Bit 8, Center 104 (43 ~ 166) 124
3602 23:13:59.563073 iDelay=195, Bit 9, Center 104 (43 ~ 166) 124
3603 23:13:59.566255 iDelay=195, Bit 10, Center 116 (55 ~ 178) 124
3604 23:13:59.573009 iDelay=195, Bit 11, Center 110 (51 ~ 170) 120
3605 23:13:59.576000 iDelay=195, Bit 12, Center 126 (63 ~ 190) 128
3606 23:13:59.579286 iDelay=195, Bit 13, Center 122 (63 ~ 182) 120
3607 23:13:59.582611 iDelay=195, Bit 14, Center 120 (63 ~ 178) 116
3608 23:13:59.586446 iDelay=195, Bit 15, Center 124 (63 ~ 186) 124
3609 23:13:59.589018 ==
3610 23:13:59.589440 Dram Type= 6, Freq= 0, CH_1, rank 1
3611 23:13:59.596211 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3612 23:13:59.596720 ==
3613 23:13:59.597064 DQS Delay:
3614 23:13:59.599528 DQS0 = 0, DQS1 = 0
3615 23:13:59.599965 DQM Delay:
3616 23:13:59.602710 DQM0 = 120, DQM1 = 115
3617 23:13:59.603162 DQ Delay:
3618 23:13:59.605679 DQ0 =122, DQ1 =116, DQ2 =110, DQ3 =118
3619 23:13:59.609167 DQ4 =116, DQ5 =130, DQ6 =130, DQ7 =120
3620 23:13:59.612684 DQ8 =104, DQ9 =104, DQ10 =116, DQ11 =110
3621 23:13:59.615882 DQ12 =126, DQ13 =122, DQ14 =120, DQ15 =124
3622 23:13:59.616301
3623 23:13:59.616638
3624 23:13:59.625669 [DQSOSCAuto] RK1, (LSB)MR18= 0x10ee, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 403 ps
3625 23:13:59.629095 CH1 RK1: MR19=403, MR18=10EE
3626 23:13:59.632841 CH1_RK1: MR19=0x403, MR18=0x10EE, DQSOSC=403, MR23=63, INC=40, DEC=26
3627 23:13:59.635744 [RxdqsGatingPostProcess] freq 1200
3628 23:13:59.642332 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3629 23:13:59.645978 best DQS0 dly(2T, 0.5T) = (0, 11)
3630 23:13:59.649197 best DQS1 dly(2T, 0.5T) = (0, 11)
3631 23:13:59.652370 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3632 23:13:59.655991 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3633 23:13:59.658644 best DQS0 dly(2T, 0.5T) = (0, 11)
3634 23:13:59.662078 best DQS1 dly(2T, 0.5T) = (0, 11)
3635 23:13:59.665900 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3636 23:13:59.669570 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3637 23:13:59.670198 Pre-setting of DQS Precalculation
3638 23:13:59.675721 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3639 23:13:59.682130 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3640 23:13:59.689048 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3641 23:13:59.689672
3642 23:13:59.690056
3643 23:13:59.692625 [Calibration Summary] 2400 Mbps
3644 23:13:59.695584 CH 0, Rank 0
3645 23:13:59.696143 SW Impedance : PASS
3646 23:13:59.699020 DUTY Scan : NO K
3647 23:13:59.702436 ZQ Calibration : PASS
3648 23:13:59.702899 Jitter Meter : NO K
3649 23:13:59.705486 CBT Training : PASS
3650 23:13:59.709218 Write leveling : PASS
3651 23:13:59.709827 RX DQS gating : PASS
3652 23:13:59.711918 RX DQ/DQS(RDDQC) : PASS
3653 23:13:59.712383 TX DQ/DQS : PASS
3654 23:13:59.715449 RX DATLAT : PASS
3655 23:13:59.718711 RX DQ/DQS(Engine): PASS
3656 23:13:59.719190 TX OE : NO K
3657 23:13:59.721730 All Pass.
3658 23:13:59.722192
3659 23:13:59.722608 CH 0, Rank 1
3660 23:13:59.725020 SW Impedance : PASS
3661 23:13:59.725482 DUTY Scan : NO K
3662 23:13:59.728655 ZQ Calibration : PASS
3663 23:13:59.732109 Jitter Meter : NO K
3664 23:13:59.732532 CBT Training : PASS
3665 23:13:59.735296 Write leveling : PASS
3666 23:13:59.738637 RX DQS gating : PASS
3667 23:13:59.739059 RX DQ/DQS(RDDQC) : PASS
3668 23:13:59.741732 TX DQ/DQS : PASS
3669 23:13:59.745276 RX DATLAT : PASS
3670 23:13:59.745736 RX DQ/DQS(Engine): PASS
3671 23:13:59.748688 TX OE : NO K
3672 23:13:59.749233 All Pass.
3673 23:13:59.749614
3674 23:13:59.752118 CH 1, Rank 0
3675 23:13:59.752539 SW Impedance : PASS
3676 23:13:59.755330 DUTY Scan : NO K
3677 23:13:59.758184 ZQ Calibration : PASS
3678 23:13:59.758667 Jitter Meter : NO K
3679 23:13:59.761993 CBT Training : PASS
3680 23:13:59.764888 Write leveling : PASS
3681 23:13:59.765308 RX DQS gating : PASS
3682 23:13:59.768368 RX DQ/DQS(RDDQC) : PASS
3683 23:13:59.771868 TX DQ/DQS : PASS
3684 23:13:59.772388 RX DATLAT : PASS
3685 23:13:59.775064 RX DQ/DQS(Engine): PASS
3686 23:13:59.775583 TX OE : NO K
3687 23:13:59.778539 All Pass.
3688 23:13:59.779085
3689 23:13:59.779424 CH 1, Rank 1
3690 23:13:59.781320 SW Impedance : PASS
3691 23:13:59.781778 DUTY Scan : NO K
3692 23:13:59.784699 ZQ Calibration : PASS
3693 23:13:59.788146 Jitter Meter : NO K
3694 23:13:59.788607 CBT Training : PASS
3695 23:13:59.791534 Write leveling : PASS
3696 23:13:59.795092 RX DQS gating : PASS
3697 23:13:59.795555 RX DQ/DQS(RDDQC) : PASS
3698 23:13:59.798326 TX DQ/DQS : PASS
3699 23:13:59.801527 RX DATLAT : PASS
3700 23:13:59.802006 RX DQ/DQS(Engine): PASS
3701 23:13:59.804851 TX OE : NO K
3702 23:13:59.805367 All Pass.
3703 23:13:59.805762
3704 23:13:59.808001 DramC Write-DBI off
3705 23:13:59.811681 PER_BANK_REFRESH: Hybrid Mode
3706 23:13:59.812204 TX_TRACKING: ON
3707 23:13:59.821250 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3708 23:13:59.824526 [FAST_K] Save calibration result to emmc
3709 23:13:59.827550 dramc_set_vcore_voltage set vcore to 650000
3710 23:13:59.830928 Read voltage for 600, 5
3711 23:13:59.831434 Vio18 = 0
3712 23:13:59.831800 Vcore = 650000
3713 23:13:59.834308 Vdram = 0
3714 23:13:59.834717 Vddq = 0
3715 23:13:59.835077 Vmddr = 0
3716 23:13:59.841420 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3717 23:13:59.844089 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3718 23:13:59.847588 MEM_TYPE=3, freq_sel=19
3719 23:13:59.851265 sv_algorithm_assistance_LP4_1600
3720 23:13:59.854220 ============ PULL DRAM RESETB DOWN ============
3721 23:13:59.857682 ========== PULL DRAM RESETB DOWN end =========
3722 23:13:59.864210 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3723 23:13:59.867873 ===================================
3724 23:13:59.870857 LPDDR4 DRAM CONFIGURATION
3725 23:13:59.874343 ===================================
3726 23:13:59.874775 EX_ROW_EN[0] = 0x0
3727 23:13:59.877366 EX_ROW_EN[1] = 0x0
3728 23:13:59.877830 LP4Y_EN = 0x0
3729 23:13:59.881080 WORK_FSP = 0x0
3730 23:13:59.881662 WL = 0x2
3731 23:13:59.884350 RL = 0x2
3732 23:13:59.884763 BL = 0x2
3733 23:13:59.887334 RPST = 0x0
3734 23:13:59.887745 RD_PRE = 0x0
3735 23:13:59.890712 WR_PRE = 0x1
3736 23:13:59.891123 WR_PST = 0x0
3737 23:13:59.893876 DBI_WR = 0x0
3738 23:13:59.894305 DBI_RD = 0x0
3739 23:13:59.897424 OTF = 0x1
3740 23:13:59.900702 ===================================
3741 23:13:59.903929 ===================================
3742 23:13:59.904470 ANA top config
3743 23:13:59.907434 ===================================
3744 23:13:59.910607 DLL_ASYNC_EN = 0
3745 23:13:59.914189 ALL_SLAVE_EN = 1
3746 23:13:59.917655 NEW_RANK_MODE = 1
3747 23:13:59.918077 DLL_IDLE_MODE = 1
3748 23:13:59.920741 LP45_APHY_COMB_EN = 1
3749 23:13:59.924433 TX_ODT_DIS = 1
3750 23:13:59.927334 NEW_8X_MODE = 1
3751 23:13:59.930634 ===================================
3752 23:13:59.934198 ===================================
3753 23:13:59.937746 data_rate = 1200
3754 23:13:59.938421 CKR = 1
3755 23:13:59.940604 DQ_P2S_RATIO = 8
3756 23:13:59.944127 ===================================
3757 23:13:59.948012 CA_P2S_RATIO = 8
3758 23:13:59.950446 DQ_CA_OPEN = 0
3759 23:13:59.953761 DQ_SEMI_OPEN = 0
3760 23:13:59.957212 CA_SEMI_OPEN = 0
3761 23:13:59.957675 CA_FULL_RATE = 0
3762 23:13:59.960439 DQ_CKDIV4_EN = 1
3763 23:13:59.964019 CA_CKDIV4_EN = 1
3764 23:13:59.967211 CA_PREDIV_EN = 0
3765 23:13:59.970908 PH8_DLY = 0
3766 23:13:59.974043 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3767 23:13:59.974466 DQ_AAMCK_DIV = 4
3768 23:13:59.976905 CA_AAMCK_DIV = 4
3769 23:13:59.980671 CA_ADMCK_DIV = 4
3770 23:13:59.984252 DQ_TRACK_CA_EN = 0
3771 23:13:59.986906 CA_PICK = 600
3772 23:13:59.990358 CA_MCKIO = 600
3773 23:13:59.993705 MCKIO_SEMI = 0
3774 23:13:59.994129 PLL_FREQ = 2288
3775 23:13:59.997107 DQ_UI_PI_RATIO = 32
3776 23:14:00.000438 CA_UI_PI_RATIO = 0
3777 23:14:00.003501 ===================================
3778 23:14:00.006842 ===================================
3779 23:14:00.010505 memory_type:LPDDR4
3780 23:14:00.013736 GP_NUM : 10
3781 23:14:00.014316 SRAM_EN : 1
3782 23:14:00.017123 MD32_EN : 0
3783 23:14:00.020285 ===================================
3784 23:14:00.020873 [ANA_INIT] >>>>>>>>>>>>>>
3785 23:14:00.023777 <<<<<< [CONFIGURE PHASE]: ANA_TX
3786 23:14:00.026557 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3787 23:14:00.030047 ===================================
3788 23:14:00.033677 data_rate = 1200,PCW = 0X5800
3789 23:14:00.036873 ===================================
3790 23:14:00.040435 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3791 23:14:00.046671 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3792 23:14:00.053492 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3793 23:14:00.056545 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3794 23:14:00.059947 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3795 23:14:00.063526 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3796 23:14:00.066450 [ANA_INIT] flow start
3797 23:14:00.066856 [ANA_INIT] PLL >>>>>>>>
3798 23:14:00.069830 [ANA_INIT] PLL <<<<<<<<
3799 23:14:00.073276 [ANA_INIT] MIDPI >>>>>>>>
3800 23:14:00.073707 [ANA_INIT] MIDPI <<<<<<<<
3801 23:14:00.076532 [ANA_INIT] DLL >>>>>>>>
3802 23:14:00.079645 [ANA_INIT] flow end
3803 23:14:00.083151 ============ LP4 DIFF to SE enter ============
3804 23:14:00.086262 ============ LP4 DIFF to SE exit ============
3805 23:14:00.089689 [ANA_INIT] <<<<<<<<<<<<<
3806 23:14:00.093169 [Flow] Enable top DCM control >>>>>
3807 23:14:00.096395 [Flow] Enable top DCM control <<<<<
3808 23:14:00.099642 Enable DLL master slave shuffle
3809 23:14:00.102986 ==============================================================
3810 23:14:00.106771 Gating Mode config
3811 23:14:00.112804 ==============================================================
3812 23:14:00.113230 Config description:
3813 23:14:00.123160 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3814 23:14:00.129470 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3815 23:14:00.132979 SELPH_MODE 0: By rank 1: By Phase
3816 23:14:00.139371 ==============================================================
3817 23:14:00.142926 GAT_TRACK_EN = 1
3818 23:14:00.146411 RX_GATING_MODE = 2
3819 23:14:00.149188 RX_GATING_TRACK_MODE = 2
3820 23:14:00.152533 SELPH_MODE = 1
3821 23:14:00.155919 PICG_EARLY_EN = 1
3822 23:14:00.159367 VALID_LAT_VALUE = 1
3823 23:14:00.162703 ==============================================================
3824 23:14:00.166418 Enter into Gating configuration >>>>
3825 23:14:00.169373 Exit from Gating configuration <<<<
3826 23:14:00.172565 Enter into DVFS_PRE_config >>>>>
3827 23:14:00.183288 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3828 23:14:00.186564 Exit from DVFS_PRE_config <<<<<
3829 23:14:00.189369 Enter into PICG configuration >>>>
3830 23:14:00.192948 Exit from PICG configuration <<<<
3831 23:14:00.196296 [RX_INPUT] configuration >>>>>
3832 23:14:00.199673 [RX_INPUT] configuration <<<<<
3833 23:14:00.206364 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3834 23:14:00.209359 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3835 23:14:00.215876 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3836 23:14:00.222912 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3837 23:14:00.229357 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3838 23:14:00.236594 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3839 23:14:00.239949 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3840 23:14:00.243019 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3841 23:14:00.246396 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3842 23:14:00.252743 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3843 23:14:00.256236 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3844 23:14:00.259073 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3845 23:14:00.262502 ===================================
3846 23:14:00.265970 LPDDR4 DRAM CONFIGURATION
3847 23:14:00.269396 ===================================
3848 23:14:00.269861 EX_ROW_EN[0] = 0x0
3849 23:14:00.272315 EX_ROW_EN[1] = 0x0
3850 23:14:00.275649 LP4Y_EN = 0x0
3851 23:14:00.276076 WORK_FSP = 0x0
3852 23:14:00.279218 WL = 0x2
3853 23:14:00.279741 RL = 0x2
3854 23:14:00.282514 BL = 0x2
3855 23:14:00.282936 RPST = 0x0
3856 23:14:00.286131 RD_PRE = 0x0
3857 23:14:00.286553 WR_PRE = 0x1
3858 23:14:00.289082 WR_PST = 0x0
3859 23:14:00.289505 DBI_WR = 0x0
3860 23:14:00.292468 DBI_RD = 0x0
3861 23:14:00.292924 OTF = 0x1
3862 23:14:00.295906 ===================================
3863 23:14:00.299002 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3864 23:14:00.305941 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3865 23:14:00.308620 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3866 23:14:00.312481 ===================================
3867 23:14:00.315597 LPDDR4 DRAM CONFIGURATION
3868 23:14:00.319187 ===================================
3869 23:14:00.319724 EX_ROW_EN[0] = 0x10
3870 23:14:00.322192 EX_ROW_EN[1] = 0x0
3871 23:14:00.325355 LP4Y_EN = 0x0
3872 23:14:00.325822 WORK_FSP = 0x0
3873 23:14:00.328901 WL = 0x2
3874 23:14:00.329423 RL = 0x2
3875 23:14:00.332220 BL = 0x2
3876 23:14:00.332676 RPST = 0x0
3877 23:14:00.335709 RD_PRE = 0x0
3878 23:14:00.336237 WR_PRE = 0x1
3879 23:14:00.338752 WR_PST = 0x0
3880 23:14:00.339236 DBI_WR = 0x0
3881 23:14:00.342555 DBI_RD = 0x0
3882 23:14:00.342970 OTF = 0x1
3883 23:14:00.345207 ===================================
3884 23:14:00.352354 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3885 23:14:00.356368 nWR fixed to 30
3886 23:14:00.359364 [ModeRegInit_LP4] CH0 RK0
3887 23:14:00.359797 [ModeRegInit_LP4] CH0 RK1
3888 23:14:00.362775 [ModeRegInit_LP4] CH1 RK0
3889 23:14:00.366133 [ModeRegInit_LP4] CH1 RK1
3890 23:14:00.366545 match AC timing 17
3891 23:14:00.373133 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3892 23:14:00.376086 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3893 23:14:00.379738 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3894 23:14:00.386011 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3895 23:14:00.389340 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3896 23:14:00.390013 ==
3897 23:14:00.392918 Dram Type= 6, Freq= 0, CH_0, rank 0
3898 23:14:00.395877 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3899 23:14:00.396483 ==
3900 23:14:00.402805 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3901 23:14:00.409417 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3902 23:14:00.412913 [CA 0] Center 35 (5~66) winsize 62
3903 23:14:00.415673 [CA 1] Center 35 (5~66) winsize 62
3904 23:14:00.419961 [CA 2] Center 34 (3~65) winsize 63
3905 23:14:00.422577 [CA 3] Center 33 (2~64) winsize 63
3906 23:14:00.426179 [CA 4] Center 33 (2~64) winsize 63
3907 23:14:00.429271 [CA 5] Center 32 (2~63) winsize 62
3908 23:14:00.429870
3909 23:14:00.432524 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3910 23:14:00.432940
3911 23:14:00.435785 [CATrainingPosCal] consider 1 rank data
3912 23:14:00.439276 u2DelayCellTimex100 = 270/100 ps
3913 23:14:00.442769 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3914 23:14:00.445627 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3915 23:14:00.448955 CA2 delay=34 (3~65),Diff = 2 PI (19 cell)
3916 23:14:00.452377 CA3 delay=33 (2~64),Diff = 1 PI (9 cell)
3917 23:14:00.455628 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3918 23:14:00.462243 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3919 23:14:00.462742
3920 23:14:00.465882 CA PerBit enable=1, Macro0, CA PI delay=32
3921 23:14:00.466350
3922 23:14:00.469363 [CBTSetCACLKResult] CA Dly = 32
3923 23:14:00.469928 CS Dly: 4 (0~35)
3924 23:14:00.470274 ==
3925 23:14:00.472031 Dram Type= 6, Freq= 0, CH_0, rank 1
3926 23:14:00.475659 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3927 23:14:00.479143 ==
3928 23:14:00.482109 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3929 23:14:00.489336 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3930 23:14:00.492275 [CA 0] Center 35 (5~66) winsize 62
3931 23:14:00.495753 [CA 1] Center 35 (5~66) winsize 62
3932 23:14:00.499040 [CA 2] Center 34 (3~65) winsize 63
3933 23:14:00.502290 [CA 3] Center 33 (3~64) winsize 62
3934 23:14:00.505851 [CA 4] Center 32 (2~63) winsize 62
3935 23:14:00.509348 [CA 5] Center 32 (2~63) winsize 62
3936 23:14:00.509907
3937 23:14:00.512167 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3938 23:14:00.512588
3939 23:14:00.515746 [CATrainingPosCal] consider 2 rank data
3940 23:14:00.518688 u2DelayCellTimex100 = 270/100 ps
3941 23:14:00.521898 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3942 23:14:00.525532 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3943 23:14:00.528623 CA2 delay=34 (3~65),Diff = 2 PI (19 cell)
3944 23:14:00.532137 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
3945 23:14:00.538910 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
3946 23:14:00.541943 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3947 23:14:00.542369
3948 23:14:00.545379 CA PerBit enable=1, Macro0, CA PI delay=32
3949 23:14:00.545963
3950 23:14:00.548751 [CBTSetCACLKResult] CA Dly = 32
3951 23:14:00.549177 CS Dly: 5 (0~37)
3952 23:14:00.549514
3953 23:14:00.552342 ----->DramcWriteLeveling(PI) begin...
3954 23:14:00.552766 ==
3955 23:14:00.555117 Dram Type= 6, Freq= 0, CH_0, rank 0
3956 23:14:00.561900 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3957 23:14:00.562326 ==
3958 23:14:00.565272 Write leveling (Byte 0): 33 => 33
3959 23:14:00.568554 Write leveling (Byte 1): 28 => 28
3960 23:14:00.569088 DramcWriteLeveling(PI) end<-----
3961 23:14:00.572187
3962 23:14:00.572698 ==
3963 23:14:00.575599 Dram Type= 6, Freq= 0, CH_0, rank 0
3964 23:14:00.578211 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3965 23:14:00.578702 ==
3966 23:14:00.581914 [Gating] SW mode calibration
3967 23:14:00.588298 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3968 23:14:00.591342 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3969 23:14:00.598738 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3970 23:14:00.601437 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3971 23:14:00.605570 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3972 23:14:00.611569 0 9 12 | B1->B0 | 3434 2c2c | 1 0 | (1 1) (0 1)
3973 23:14:00.614683 0 9 16 | B1->B0 | 3030 2323 | 0 0 | (0 0) (0 0)
3974 23:14:00.617996 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3975 23:14:00.624894 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3976 23:14:00.627843 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3977 23:14:00.631035 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3978 23:14:00.637695 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3979 23:14:00.641477 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
3980 23:14:00.644983 0 10 12 | B1->B0 | 2323 3636 | 0 0 | (0 0) (0 0)
3981 23:14:00.651010 0 10 16 | B1->B0 | 3232 4646 | 1 0 | (0 0) (0 0)
3982 23:14:00.654353 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3983 23:14:00.658105 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3984 23:14:00.664774 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3985 23:14:00.668291 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3986 23:14:00.671394 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3987 23:14:00.677689 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3988 23:14:00.681228 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3989 23:14:00.684365 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3990 23:14:00.691318 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3991 23:14:00.694554 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3992 23:14:00.697468 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3993 23:14:00.704169 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3994 23:14:00.707647 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3995 23:14:00.711134 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3996 23:14:00.717381 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3997 23:14:00.721059 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3998 23:14:00.724297 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3999 23:14:00.730699 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4000 23:14:00.733995 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4001 23:14:00.737555 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4002 23:14:00.744130 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4003 23:14:00.747432 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4004 23:14:00.750979 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4005 23:14:00.753968 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4006 23:14:00.757457 Total UI for P1: 0, mck2ui 16
4007 23:14:00.760866 best dqsien dly found for B0: ( 0, 13, 12)
4008 23:14:00.767507 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4009 23:14:00.770968 Total UI for P1: 0, mck2ui 16
4010 23:14:00.773813 best dqsien dly found for B1: ( 0, 13, 14)
4011 23:14:00.777406 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4012 23:14:00.780551 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4013 23:14:00.781016
4014 23:14:00.784083 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4015 23:14:00.787813 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4016 23:14:00.790544 [Gating] SW calibration Done
4017 23:14:00.791005 ==
4018 23:14:00.794104 Dram Type= 6, Freq= 0, CH_0, rank 0
4019 23:14:00.797083 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4020 23:14:00.797540 ==
4021 23:14:00.800947 RX Vref Scan: 0
4022 23:14:00.801469
4023 23:14:00.801910 RX Vref 0 -> 0, step: 1
4024 23:14:00.803900
4025 23:14:00.804359 RX Delay -230 -> 252, step: 16
4026 23:14:00.810675 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4027 23:14:00.814011 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4028 23:14:00.817289 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4029 23:14:00.820873 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4030 23:14:00.826887 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4031 23:14:00.830221 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4032 23:14:00.833957 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4033 23:14:00.837093 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4034 23:14:00.840320 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4035 23:14:00.847194 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4036 23:14:00.850558 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4037 23:14:00.854047 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4038 23:14:00.857227 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4039 23:14:00.864185 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4040 23:14:00.867116 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4041 23:14:00.870636 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4042 23:14:00.871056 ==
4043 23:14:00.874190 Dram Type= 6, Freq= 0, CH_0, rank 0
4044 23:14:00.877296 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4045 23:14:00.880710 ==
4046 23:14:00.881216 DQS Delay:
4047 23:14:00.881548 DQS0 = 0, DQS1 = 0
4048 23:14:00.883715 DQM Delay:
4049 23:14:00.884258 DQM0 = 48, DQM1 = 46
4050 23:14:00.886778 DQ Delay:
4051 23:14:00.887195 DQ0 =41, DQ1 =57, DQ2 =41, DQ3 =41
4052 23:14:00.890266 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4053 23:14:00.893467 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4054 23:14:00.896865 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =57
4055 23:14:00.897287
4056 23:14:00.900525
4057 23:14:00.901044 ==
4058 23:14:00.903794 Dram Type= 6, Freq= 0, CH_0, rank 0
4059 23:14:00.906719 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4060 23:14:00.907137 ==
4061 23:14:00.907477
4062 23:14:00.907784
4063 23:14:00.910148 TX Vref Scan disable
4064 23:14:00.910561 == TX Byte 0 ==
4065 23:14:00.916751 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4066 23:14:00.920504 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4067 23:14:00.920926 == TX Byte 1 ==
4068 23:14:00.927033 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4069 23:14:00.930331 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4070 23:14:00.930847 ==
4071 23:14:00.933661 Dram Type= 6, Freq= 0, CH_0, rank 0
4072 23:14:00.936521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4073 23:14:00.936940 ==
4074 23:14:00.937270
4075 23:14:00.937669
4076 23:14:00.940043 TX Vref Scan disable
4077 23:14:00.943584 == TX Byte 0 ==
4078 23:14:00.946634 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4079 23:14:00.949825 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4080 23:14:00.953190 == TX Byte 1 ==
4081 23:14:00.957034 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4082 23:14:00.959711 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4083 23:14:00.960359
4084 23:14:00.963176 [DATLAT]
4085 23:14:00.963593 Freq=600, CH0 RK0
4086 23:14:00.963931
4087 23:14:00.966802 DATLAT Default: 0x9
4088 23:14:00.967280 0, 0xFFFF, sum = 0
4089 23:14:00.970419 1, 0xFFFF, sum = 0
4090 23:14:00.971150 2, 0xFFFF, sum = 0
4091 23:14:00.973447 3, 0xFFFF, sum = 0
4092 23:14:00.973916 4, 0xFFFF, sum = 0
4093 23:14:00.976873 5, 0xFFFF, sum = 0
4094 23:14:00.977297 6, 0xFFFF, sum = 0
4095 23:14:00.980405 7, 0xFFFF, sum = 0
4096 23:14:00.980825 8, 0x0, sum = 1
4097 23:14:00.983335 9, 0x0, sum = 2
4098 23:14:00.984017 10, 0x0, sum = 3
4099 23:14:00.986772 11, 0x0, sum = 4
4100 23:14:00.987195 best_step = 9
4101 23:14:00.987528
4102 23:14:00.987837 ==
4103 23:14:00.990308 Dram Type= 6, Freq= 0, CH_0, rank 0
4104 23:14:00.993815 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4105 23:14:00.996605 ==
4106 23:14:00.997021 RX Vref Scan: 1
4107 23:14:00.997352
4108 23:14:01.000132 RX Vref 0 -> 0, step: 1
4109 23:14:01.000549
4110 23:14:01.003808 RX Delay -163 -> 252, step: 8
4111 23:14:01.004349
4112 23:14:01.006705 Set Vref, RX VrefLevel [Byte0]: 56
4113 23:14:01.010486 [Byte1]: 54
4114 23:14:01.011043
4115 23:14:01.013147 Final RX Vref Byte 0 = 56 to rank0
4116 23:14:01.016571 Final RX Vref Byte 1 = 54 to rank0
4117 23:14:01.020221 Final RX Vref Byte 0 = 56 to rank1
4118 23:14:01.023702 Final RX Vref Byte 1 = 54 to rank1==
4119 23:14:01.026704 Dram Type= 6, Freq= 0, CH_0, rank 0
4120 23:14:01.030384 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4121 23:14:01.030805 ==
4122 23:14:01.031138 DQS Delay:
4123 23:14:01.033189 DQS0 = 0, DQS1 = 0
4124 23:14:01.033637 DQM Delay:
4125 23:14:01.036889 DQM0 = 53, DQM1 = 46
4126 23:14:01.037458 DQ Delay:
4127 23:14:01.040292 DQ0 =52, DQ1 =56, DQ2 =48, DQ3 =52
4128 23:14:01.043780 DQ4 =52, DQ5 =44, DQ6 =60, DQ7 =64
4129 23:14:01.046394 DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =36
4130 23:14:01.049840 DQ12 =52, DQ13 =52, DQ14 =56, DQ15 =52
4131 23:14:01.050258
4132 23:14:01.050586
4133 23:14:01.060423 [DQSOSCAuto] RK0, (LSB)MR18= 0x7165, (MSB)MR19= 0x808, tDQSOscB0 = 390 ps tDQSOscB1 = 388 ps
4134 23:14:01.060950 CH0 RK0: MR19=808, MR18=7165
4135 23:14:01.066455 CH0_RK0: MR19=0x808, MR18=0x7165, DQSOSC=388, MR23=63, INC=174, DEC=116
4136 23:14:01.066960
4137 23:14:01.070115 ----->DramcWriteLeveling(PI) begin...
4138 23:14:01.070551 ==
4139 23:14:01.073227 Dram Type= 6, Freq= 0, CH_0, rank 1
4140 23:14:01.080047 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4141 23:14:01.080471 ==
4142 23:14:01.083004 Write leveling (Byte 0): 35 => 35
4143 23:14:01.086806 Write leveling (Byte 1): 30 => 30
4144 23:14:01.087323 DramcWriteLeveling(PI) end<-----
4145 23:14:01.089415
4146 23:14:01.089877 ==
4147 23:14:01.092997 Dram Type= 6, Freq= 0, CH_0, rank 1
4148 23:14:01.096044 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4149 23:14:01.096529 ==
4150 23:14:01.099611 [Gating] SW mode calibration
4151 23:14:01.106351 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4152 23:14:01.109834 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4153 23:14:01.116221 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4154 23:14:01.119672 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4155 23:14:01.123202 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4156 23:14:01.129850 0 9 12 | B1->B0 | 3434 3333 | 1 1 | (1 0) (1 0)
4157 23:14:01.132998 0 9 16 | B1->B0 | 2828 2727 | 0 0 | (0 0) (0 0)
4158 23:14:01.136477 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4159 23:14:01.142495 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4160 23:14:01.145822 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4161 23:14:01.149289 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4162 23:14:01.155822 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4163 23:14:01.159028 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4164 23:14:01.162542 0 10 12 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
4165 23:14:01.169069 0 10 16 | B1->B0 | 4343 4040 | 0 0 | (0 0) (0 0)
4166 23:14:01.172830 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4167 23:14:01.175776 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4168 23:14:01.182072 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4169 23:14:01.185536 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4170 23:14:01.189112 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4171 23:14:01.195555 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4172 23:14:01.199329 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4173 23:14:01.202662 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4174 23:14:01.209308 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4175 23:14:01.212412 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4176 23:14:01.215670 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4177 23:14:01.222701 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4178 23:14:01.225718 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4179 23:14:01.229345 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4180 23:14:01.232096 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4181 23:14:01.239197 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4182 23:14:01.242174 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4183 23:14:01.245454 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4184 23:14:01.252257 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4185 23:14:01.255481 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4186 23:14:01.258942 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4187 23:14:01.265792 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4188 23:14:01.268992 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4189 23:14:01.272312 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4190 23:14:01.275334 Total UI for P1: 0, mck2ui 16
4191 23:14:01.278574 best dqsien dly found for B0: ( 0, 13, 12)
4192 23:14:01.282039 Total UI for P1: 0, mck2ui 16
4193 23:14:01.285347 best dqsien dly found for B1: ( 0, 13, 14)
4194 23:14:01.288734 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4195 23:14:01.294968 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4196 23:14:01.295470
4197 23:14:01.298988 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4198 23:14:01.301992 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4199 23:14:01.305235 [Gating] SW calibration Done
4200 23:14:01.305968 ==
4201 23:14:01.308662 Dram Type= 6, Freq= 0, CH_0, rank 1
4202 23:14:01.311711 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4203 23:14:01.312182 ==
4204 23:14:01.312554 RX Vref Scan: 0
4205 23:14:01.315368
4206 23:14:01.315824 RX Vref 0 -> 0, step: 1
4207 23:14:01.316194
4208 23:14:01.318739 RX Delay -230 -> 252, step: 16
4209 23:14:01.321784 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4210 23:14:01.328594 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4211 23:14:01.331357 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4212 23:14:01.334856 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4213 23:14:01.338330 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4214 23:14:01.345168 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4215 23:14:01.348669 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4216 23:14:01.351394 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4217 23:14:01.355059 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4218 23:14:01.358085 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4219 23:14:01.364714 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4220 23:14:01.368672 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4221 23:14:01.371405 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4222 23:14:01.374867 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4223 23:14:01.381639 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4224 23:14:01.384622 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4225 23:14:01.385083 ==
4226 23:14:01.388327 Dram Type= 6, Freq= 0, CH_0, rank 1
4227 23:14:01.391667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4228 23:14:01.392146 ==
4229 23:14:01.394508 DQS Delay:
4230 23:14:01.394966 DQS0 = 0, DQS1 = 0
4231 23:14:01.395336 DQM Delay:
4232 23:14:01.398112 DQM0 = 51, DQM1 = 43
4233 23:14:01.398573 DQ Delay:
4234 23:14:01.401945 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =49
4235 23:14:01.404729 DQ4 =57, DQ5 =41, DQ6 =57, DQ7 =57
4236 23:14:01.408262 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =33
4237 23:14:01.411512 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =49
4238 23:14:01.412075
4239 23:14:01.412456
4240 23:14:01.412834 ==
4241 23:14:01.414408 Dram Type= 6, Freq= 0, CH_0, rank 1
4242 23:14:01.421094 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4243 23:14:01.421555 ==
4244 23:14:01.421987
4245 23:14:01.422333
4246 23:14:01.422661 TX Vref Scan disable
4247 23:14:01.424830 == TX Byte 0 ==
4248 23:14:01.428388 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4249 23:14:01.434799 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4250 23:14:01.435341 == TX Byte 1 ==
4251 23:14:01.438253 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4252 23:14:01.444765 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4253 23:14:01.445288 ==
4254 23:14:01.448230 Dram Type= 6, Freq= 0, CH_0, rank 1
4255 23:14:01.451097 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4256 23:14:01.451700 ==
4257 23:14:01.452043
4258 23:14:01.452351
4259 23:14:01.454731 TX Vref Scan disable
4260 23:14:01.457930 == TX Byte 0 ==
4261 23:14:01.461240 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4262 23:14:01.464651 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4263 23:14:01.468192 == TX Byte 1 ==
4264 23:14:01.471212 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4265 23:14:01.474360 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4266 23:14:01.474798
4267 23:14:01.475128 [DATLAT]
4268 23:14:01.478060 Freq=600, CH0 RK1
4269 23:14:01.478583
4270 23:14:01.481013 DATLAT Default: 0x9
4271 23:14:01.481428 0, 0xFFFF, sum = 0
4272 23:14:01.484425 1, 0xFFFF, sum = 0
4273 23:14:01.484849 2, 0xFFFF, sum = 0
4274 23:14:01.487831 3, 0xFFFF, sum = 0
4275 23:14:01.488357 4, 0xFFFF, sum = 0
4276 23:14:01.490847 5, 0xFFFF, sum = 0
4277 23:14:01.491274 6, 0xFFFF, sum = 0
4278 23:14:01.494494 7, 0xFFFF, sum = 0
4279 23:14:01.494934 8, 0x0, sum = 1
4280 23:14:01.497688 9, 0x0, sum = 2
4281 23:14:01.498127 10, 0x0, sum = 3
4282 23:14:01.501196 11, 0x0, sum = 4
4283 23:14:01.501655 best_step = 9
4284 23:14:01.501997
4285 23:14:01.502311 ==
4286 23:14:01.504193 Dram Type= 6, Freq= 0, CH_0, rank 1
4287 23:14:01.507808 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4288 23:14:01.508340 ==
4289 23:14:01.510836 RX Vref Scan: 0
4290 23:14:01.511299
4291 23:14:01.514135 RX Vref 0 -> 0, step: 1
4292 23:14:01.514680
4293 23:14:01.515201 RX Delay -163 -> 252, step: 8
4294 23:14:01.522201 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4295 23:14:01.525653 iDelay=205, Bit 1, Center 56 (-83 ~ 196) 280
4296 23:14:01.528552 iDelay=205, Bit 2, Center 52 (-91 ~ 196) 288
4297 23:14:01.531960 iDelay=205, Bit 3, Center 52 (-91 ~ 196) 288
4298 23:14:01.535336 iDelay=205, Bit 4, Center 56 (-83 ~ 196) 280
4299 23:14:01.541828 iDelay=205, Bit 5, Center 44 (-99 ~ 188) 288
4300 23:14:01.545212 iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280
4301 23:14:01.548642 iDelay=205, Bit 7, Center 64 (-75 ~ 204) 280
4302 23:14:01.551706 iDelay=205, Bit 8, Center 36 (-107 ~ 180) 288
4303 23:14:01.555297 iDelay=205, Bit 9, Center 36 (-107 ~ 180) 288
4304 23:14:01.561655 iDelay=205, Bit 10, Center 48 (-91 ~ 188) 280
4305 23:14:01.565390 iDelay=205, Bit 11, Center 40 (-99 ~ 180) 280
4306 23:14:01.568718 iDelay=205, Bit 12, Center 52 (-91 ~ 196) 288
4307 23:14:01.571875 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4308 23:14:01.578134 iDelay=205, Bit 14, Center 56 (-83 ~ 196) 280
4309 23:14:01.581899 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4310 23:14:01.582358 ==
4311 23:14:01.584958 Dram Type= 6, Freq= 0, CH_0, rank 1
4312 23:14:01.588580 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4313 23:14:01.589139 ==
4314 23:14:01.591986 DQS Delay:
4315 23:14:01.592536 DQS0 = 0, DQS1 = 0
4316 23:14:01.592906 DQM Delay:
4317 23:14:01.595127 DQM0 = 54, DQM1 = 46
4318 23:14:01.595587 DQ Delay:
4319 23:14:01.598426 DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =52
4320 23:14:01.601735 DQ4 =56, DQ5 =44, DQ6 =56, DQ7 =64
4321 23:14:01.605052 DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =40
4322 23:14:01.608065 DQ12 =52, DQ13 =52, DQ14 =56, DQ15 =52
4323 23:14:01.608533
4324 23:14:01.608895
4325 23:14:01.618360 [DQSOSCAuto] RK1, (LSB)MR18= 0x6224, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 391 ps
4326 23:14:01.618824 CH0 RK1: MR19=808, MR18=6224
4327 23:14:01.624947 CH0_RK1: MR19=0x808, MR18=0x6224, DQSOSC=391, MR23=63, INC=171, DEC=114
4328 23:14:01.628519 [RxdqsGatingPostProcess] freq 600
4329 23:14:01.634809 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4330 23:14:01.638407 Pre-setting of DQS Precalculation
4331 23:14:01.641789 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4332 23:14:01.642335 ==
4333 23:14:01.645508 Dram Type= 6, Freq= 0, CH_1, rank 0
4334 23:14:01.648719 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4335 23:14:01.651500 ==
4336 23:14:01.654988 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4337 23:14:01.661465 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4338 23:14:01.665181 [CA 0] Center 35 (5~66) winsize 62
4339 23:14:01.668591 [CA 1] Center 35 (5~66) winsize 62
4340 23:14:01.671477 [CA 2] Center 34 (4~65) winsize 62
4341 23:14:01.674935 [CA 3] Center 34 (3~65) winsize 63
4342 23:14:01.678714 [CA 4] Center 34 (4~65) winsize 62
4343 23:14:01.681943 [CA 5] Center 33 (3~64) winsize 62
4344 23:14:01.682453
4345 23:14:01.685115 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4346 23:14:01.685525
4347 23:14:01.688560 [CATrainingPosCal] consider 1 rank data
4348 23:14:01.692058 u2DelayCellTimex100 = 270/100 ps
4349 23:14:01.695001 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4350 23:14:01.698436 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4351 23:14:01.701878 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4352 23:14:01.705324 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4353 23:14:01.708960 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4354 23:14:01.715268 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4355 23:14:01.715843
4356 23:14:01.718378 CA PerBit enable=1, Macro0, CA PI delay=33
4357 23:14:01.718834
4358 23:14:01.722074 [CBTSetCACLKResult] CA Dly = 33
4359 23:14:01.722534 CS Dly: 6 (0~37)
4360 23:14:01.722969 ==
4361 23:14:01.725357 Dram Type= 6, Freq= 0, CH_1, rank 1
4362 23:14:01.728531 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4363 23:14:01.728992 ==
4364 23:14:01.735403 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4365 23:14:01.741824 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4366 23:14:01.745180 [CA 0] Center 36 (5~67) winsize 63
4367 23:14:01.748494 [CA 1] Center 36 (5~67) winsize 63
4368 23:14:01.752305 [CA 2] Center 34 (4~65) winsize 62
4369 23:14:01.755107 [CA 3] Center 34 (4~65) winsize 62
4370 23:14:01.758786 [CA 4] Center 35 (4~66) winsize 63
4371 23:14:01.761549 [CA 5] Center 34 (3~65) winsize 63
4372 23:14:01.762093
4373 23:14:01.764893 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4374 23:14:01.765308
4375 23:14:01.768172 [CATrainingPosCal] consider 2 rank data
4376 23:14:01.771721 u2DelayCellTimex100 = 270/100 ps
4377 23:14:01.774826 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4378 23:14:01.778608 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4379 23:14:01.782056 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4380 23:14:01.785112 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4381 23:14:01.791697 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4382 23:14:01.794908 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4383 23:14:01.795373
4384 23:14:01.798576 CA PerBit enable=1, Macro0, CA PI delay=33
4385 23:14:01.799043
4386 23:14:01.801767 [CBTSetCACLKResult] CA Dly = 33
4387 23:14:01.802230 CS Dly: 6 (0~38)
4388 23:14:01.802599
4389 23:14:01.805031 ----->DramcWriteLeveling(PI) begin...
4390 23:14:01.805646 ==
4391 23:14:01.808406 Dram Type= 6, Freq= 0, CH_1, rank 0
4392 23:14:01.815039 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4393 23:14:01.815604 ==
4394 23:14:01.818774 Write leveling (Byte 0): 30 => 30
4395 23:14:01.819238 Write leveling (Byte 1): 30 => 30
4396 23:14:01.821385 DramcWriteLeveling(PI) end<-----
4397 23:14:01.821885
4398 23:14:01.824923 ==
4399 23:14:01.828263 Dram Type= 6, Freq= 0, CH_1, rank 0
4400 23:14:01.831596 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4401 23:14:01.832061 ==
4402 23:14:01.834806 [Gating] SW mode calibration
4403 23:14:01.841489 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4404 23:14:01.845340 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4405 23:14:01.852071 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4406 23:14:01.855076 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4407 23:14:01.858080 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
4408 23:14:01.865063 0 9 12 | B1->B0 | 3030 3030 | 0 0 | (0 1) (1 1)
4409 23:14:01.868180 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4410 23:14:01.871817 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4411 23:14:01.878182 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4412 23:14:01.881726 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4413 23:14:01.884703 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4414 23:14:01.891229 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4415 23:14:01.894707 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4416 23:14:01.898187 0 10 12 | B1->B0 | 3737 3d3d | 0 1 | (1 1) (0 0)
4417 23:14:01.901660 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4418 23:14:01.908534 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4419 23:14:01.911880 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4420 23:14:01.914487 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4421 23:14:01.921774 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4422 23:14:01.924919 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4423 23:14:01.928511 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4424 23:14:01.934306 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4425 23:14:01.938001 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4426 23:14:01.941408 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4427 23:14:01.947966 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4428 23:14:01.951663 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4429 23:14:01.954204 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4430 23:14:01.960983 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4431 23:14:01.964537 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4432 23:14:01.968033 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4433 23:14:01.974308 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4434 23:14:01.977543 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4435 23:14:01.981513 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4436 23:14:01.987864 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4437 23:14:01.990723 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4438 23:14:01.994222 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4439 23:14:02.000908 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4440 23:14:02.003879 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4441 23:14:02.007229 Total UI for P1: 0, mck2ui 16
4442 23:14:02.010562 best dqsien dly found for B0: ( 0, 13, 10)
4443 23:14:02.014158 Total UI for P1: 0, mck2ui 16
4444 23:14:02.017019 best dqsien dly found for B1: ( 0, 13, 10)
4445 23:14:02.020880 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4446 23:14:02.023856 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4447 23:14:02.024420
4448 23:14:02.027404 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4449 23:14:02.030819 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4450 23:14:02.034121 [Gating] SW calibration Done
4451 23:14:02.034542 ==
4452 23:14:02.037430 Dram Type= 6, Freq= 0, CH_1, rank 0
4453 23:14:02.040740 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4454 23:14:02.044322 ==
4455 23:14:02.044829 RX Vref Scan: 0
4456 23:14:02.045165
4457 23:14:02.047491 RX Vref 0 -> 0, step: 1
4458 23:14:02.047912
4459 23:14:02.050917 RX Delay -230 -> 252, step: 16
4460 23:14:02.054109 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4461 23:14:02.057623 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4462 23:14:02.061290 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4463 23:14:02.064121 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4464 23:14:02.071063 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4465 23:14:02.074278 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4466 23:14:02.077408 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4467 23:14:02.080691 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4468 23:14:02.087480 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4469 23:14:02.090450 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4470 23:14:02.093997 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4471 23:14:02.097499 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4472 23:14:02.103979 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4473 23:14:02.107493 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4474 23:14:02.110374 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4475 23:14:02.113761 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4476 23:14:02.114227 ==
4477 23:14:02.117204 Dram Type= 6, Freq= 0, CH_1, rank 0
4478 23:14:02.123584 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4479 23:14:02.124060 ==
4480 23:14:02.124424 DQS Delay:
4481 23:14:02.127007 DQS0 = 0, DQS1 = 0
4482 23:14:02.127625 DQM Delay:
4483 23:14:02.128001 DQM0 = 50, DQM1 = 46
4484 23:14:02.130128 DQ Delay:
4485 23:14:02.133563 DQ0 =57, DQ1 =41, DQ2 =41, DQ3 =49
4486 23:14:02.136665 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4487 23:14:02.140149 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4488 23:14:02.143743 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4489 23:14:02.144428
4490 23:14:02.144797
4491 23:14:02.145291 ==
4492 23:14:02.146946 Dram Type= 6, Freq= 0, CH_1, rank 0
4493 23:14:02.149973 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4494 23:14:02.150468 ==
4495 23:14:02.150843
4496 23:14:02.151182
4497 23:14:02.153392 TX Vref Scan disable
4498 23:14:02.153941 == TX Byte 0 ==
4499 23:14:02.160054 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4500 23:14:02.163556 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4501 23:14:02.166283 == TX Byte 1 ==
4502 23:14:02.169950 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4503 23:14:02.173405 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4504 23:14:02.173913 ==
4505 23:14:02.176467 Dram Type= 6, Freq= 0, CH_1, rank 0
4506 23:14:02.180024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4507 23:14:02.180541 ==
4508 23:14:02.183417
4509 23:14:02.183930
4510 23:14:02.184261 TX Vref Scan disable
4511 23:14:02.186868 == TX Byte 0 ==
4512 23:14:02.190757 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4513 23:14:02.196728 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4514 23:14:02.197174 == TX Byte 1 ==
4515 23:14:02.200683 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4516 23:14:02.203912 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4517 23:14:02.207261
4518 23:14:02.207672 [DATLAT]
4519 23:14:02.208000 Freq=600, CH1 RK0
4520 23:14:02.208311
4521 23:14:02.210097 DATLAT Default: 0x9
4522 23:14:02.210504 0, 0xFFFF, sum = 0
4523 23:14:02.213538 1, 0xFFFF, sum = 0
4524 23:14:02.214124 2, 0xFFFF, sum = 0
4525 23:14:02.217439 3, 0xFFFF, sum = 0
4526 23:14:02.218029 4, 0xFFFF, sum = 0
4527 23:14:02.220213 5, 0xFFFF, sum = 0
4528 23:14:02.220629 6, 0xFFFF, sum = 0
4529 23:14:02.223828 7, 0xFFFF, sum = 0
4530 23:14:02.224403 8, 0x0, sum = 1
4531 23:14:02.227168 9, 0x0, sum = 2
4532 23:14:02.227638 10, 0x0, sum = 3
4533 23:14:02.230079 11, 0x0, sum = 4
4534 23:14:02.230518 best_step = 9
4535 23:14:02.231055
4536 23:14:02.231460 ==
4537 23:14:02.233488 Dram Type= 6, Freq= 0, CH_1, rank 0
4538 23:14:02.240146 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4539 23:14:02.240722 ==
4540 23:14:02.241077 RX Vref Scan: 1
4541 23:14:02.241393
4542 23:14:02.243268 RX Vref 0 -> 0, step: 1
4543 23:14:02.243712
4544 23:14:02.246787 RX Delay -163 -> 252, step: 8
4545 23:14:02.247202
4546 23:14:02.250128 Set Vref, RX VrefLevel [Byte0]: 54
4547 23:14:02.253375 [Byte1]: 46
4548 23:14:02.253973
4549 23:14:02.256524 Final RX Vref Byte 0 = 54 to rank0
4550 23:14:02.259922 Final RX Vref Byte 1 = 46 to rank0
4551 23:14:02.263694 Final RX Vref Byte 0 = 54 to rank1
4552 23:14:02.266702 Final RX Vref Byte 1 = 46 to rank1==
4553 23:14:02.269546 Dram Type= 6, Freq= 0, CH_1, rank 0
4554 23:14:02.272979 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4555 23:14:02.273481 ==
4556 23:14:02.276574 DQS Delay:
4557 23:14:02.277094 DQS0 = 0, DQS1 = 0
4558 23:14:02.277658 DQM Delay:
4559 23:14:02.280297 DQM0 = 48, DQM1 = 45
4560 23:14:02.280808 DQ Delay:
4561 23:14:02.283215 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =48
4562 23:14:02.286400 DQ4 =48, DQ5 =56, DQ6 =56, DQ7 =48
4563 23:14:02.289839 DQ8 =32, DQ9 =36, DQ10 =44, DQ11 =40
4564 23:14:02.293465 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =52
4565 23:14:02.294089
4566 23:14:02.294456
4567 23:14:02.303204 [DQSOSCAuto] RK0, (LSB)MR18= 0x466c, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
4568 23:14:02.306538 CH1 RK0: MR19=808, MR18=466C
4569 23:14:02.309545 CH1_RK0: MR19=0x808, MR18=0x466C, DQSOSC=389, MR23=63, INC=173, DEC=115
4570 23:14:02.310082
4571 23:14:02.316374 ----->DramcWriteLeveling(PI) begin...
4572 23:14:02.316902 ==
4573 23:14:02.319878 Dram Type= 6, Freq= 0, CH_1, rank 1
4574 23:14:02.323252 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4575 23:14:02.323776 ==
4576 23:14:02.326383 Write leveling (Byte 0): 29 => 29
4577 23:14:02.329887 Write leveling (Byte 1): 30 => 30
4578 23:14:02.332849 DramcWriteLeveling(PI) end<-----
4579 23:14:02.333411
4580 23:14:02.333849 ==
4581 23:14:02.336243 Dram Type= 6, Freq= 0, CH_1, rank 1
4582 23:14:02.339881 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4583 23:14:02.340466 ==
4584 23:14:02.342850 [Gating] SW mode calibration
4585 23:14:02.349791 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4586 23:14:02.356391 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4587 23:14:02.359802 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4588 23:14:02.363029 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4589 23:14:02.369437 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4590 23:14:02.372477 0 9 12 | B1->B0 | 2f2f 3030 | 0 0 | (1 1) (0 0)
4591 23:14:02.376231 0 9 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4592 23:14:02.382347 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4593 23:14:02.386176 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4594 23:14:02.389170 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4595 23:14:02.395957 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4596 23:14:02.399465 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4597 23:14:02.402213 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4598 23:14:02.409086 0 10 12 | B1->B0 | 3737 3333 | 0 0 | (0 0) (0 0)
4599 23:14:02.412590 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4600 23:14:02.416270 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4601 23:14:02.418965 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4602 23:14:02.425968 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4603 23:14:02.428964 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4604 23:14:02.432505 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4605 23:14:02.439439 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4606 23:14:02.442647 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4607 23:14:02.445873 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4608 23:14:02.452544 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4609 23:14:02.455986 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4610 23:14:02.459095 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4611 23:14:02.465472 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4612 23:14:02.469062 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4613 23:14:02.472247 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4614 23:14:02.478782 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4615 23:14:02.482040 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4616 23:14:02.485474 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4617 23:14:02.492423 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4618 23:14:02.495525 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4619 23:14:02.498533 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4620 23:14:02.505514 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4621 23:14:02.508498 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4622 23:14:02.511978 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4623 23:14:02.515478 Total UI for P1: 0, mck2ui 16
4624 23:14:02.518833 best dqsien dly found for B1: ( 0, 13, 10)
4625 23:14:02.525200 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4626 23:14:02.525699 Total UI for P1: 0, mck2ui 16
4627 23:14:02.528512 best dqsien dly found for B0: ( 0, 13, 12)
4628 23:14:02.535638 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4629 23:14:02.538497 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4630 23:14:02.539026
4631 23:14:02.541949 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4632 23:14:02.545442 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4633 23:14:02.548674 [Gating] SW calibration Done
4634 23:14:02.549198 ==
4635 23:14:02.551731 Dram Type= 6, Freq= 0, CH_1, rank 1
4636 23:14:02.555075 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4637 23:14:02.555501 ==
4638 23:14:02.558379 RX Vref Scan: 0
4639 23:14:02.558799
4640 23:14:02.559132 RX Vref 0 -> 0, step: 1
4641 23:14:02.559446
4642 23:14:02.561786 RX Delay -230 -> 252, step: 16
4643 23:14:02.568264 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4644 23:14:02.572191 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4645 23:14:02.575099 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4646 23:14:02.578421 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4647 23:14:02.581653 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4648 23:14:02.588662 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4649 23:14:02.591949 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4650 23:14:02.595218 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4651 23:14:02.598700 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4652 23:14:02.601663 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4653 23:14:02.608657 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4654 23:14:02.611722 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4655 23:14:02.614958 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4656 23:14:02.618250 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4657 23:14:02.624666 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4658 23:14:02.628984 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4659 23:14:02.629452 ==
4660 23:14:02.631745 Dram Type= 6, Freq= 0, CH_1, rank 1
4661 23:14:02.634922 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4662 23:14:02.635346 ==
4663 23:14:02.638127 DQS Delay:
4664 23:14:02.638537 DQS0 = 0, DQS1 = 0
4665 23:14:02.638871 DQM Delay:
4666 23:14:02.641436 DQM0 = 49, DQM1 = 47
4667 23:14:02.641887 DQ Delay:
4668 23:14:02.644496 DQ0 =57, DQ1 =41, DQ2 =33, DQ3 =49
4669 23:14:02.647859 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4670 23:14:02.652004 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4671 23:14:02.655316 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =57
4672 23:14:02.655836
4673 23:14:02.656201
4674 23:14:02.656642 ==
4675 23:14:02.657918 Dram Type= 6, Freq= 0, CH_1, rank 1
4676 23:14:02.665159 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4677 23:14:02.665746 ==
4678 23:14:02.666089
4679 23:14:02.666398
4680 23:14:02.666693 TX Vref Scan disable
4681 23:14:02.668461 == TX Byte 0 ==
4682 23:14:02.671936 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4683 23:14:02.678362 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4684 23:14:02.678906 == TX Byte 1 ==
4685 23:14:02.682015 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4686 23:14:02.688709 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4687 23:14:02.689410 ==
4688 23:14:02.691667 Dram Type= 6, Freq= 0, CH_1, rank 1
4689 23:14:02.695261 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4690 23:14:02.695722 ==
4691 23:14:02.696092
4692 23:14:02.696432
4693 23:14:02.698545 TX Vref Scan disable
4694 23:14:02.699082 == TX Byte 0 ==
4695 23:14:02.704973 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4696 23:14:02.708556 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4697 23:14:02.712041 == TX Byte 1 ==
4698 23:14:02.714806 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4699 23:14:02.718427 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4700 23:14:02.718992
4701 23:14:02.719364 [DATLAT]
4702 23:14:02.721770 Freq=600, CH1 RK1
4703 23:14:02.722242
4704 23:14:02.722607 DATLAT Default: 0x9
4705 23:14:02.724892 0, 0xFFFF, sum = 0
4706 23:14:02.725363 1, 0xFFFF, sum = 0
4707 23:14:02.728199 2, 0xFFFF, sum = 0
4708 23:14:02.731720 3, 0xFFFF, sum = 0
4709 23:14:02.732290 4, 0xFFFF, sum = 0
4710 23:14:02.735273 5, 0xFFFF, sum = 0
4711 23:14:02.735746 6, 0xFFFF, sum = 0
4712 23:14:02.738190 7, 0xFFFF, sum = 0
4713 23:14:02.738678 8, 0x0, sum = 1
4714 23:14:02.739084 9, 0x0, sum = 2
4715 23:14:02.741545 10, 0x0, sum = 3
4716 23:14:02.742088 11, 0x0, sum = 4
4717 23:14:02.745112 best_step = 9
4718 23:14:02.745774
4719 23:14:02.746268 ==
4720 23:14:02.748037 Dram Type= 6, Freq= 0, CH_1, rank 1
4721 23:14:02.751247 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4722 23:14:02.751714 ==
4723 23:14:02.755373 RX Vref Scan: 0
4724 23:14:02.755948
4725 23:14:02.756321 RX Vref 0 -> 0, step: 1
4726 23:14:02.756668
4727 23:14:02.757844 RX Delay -163 -> 252, step: 8
4728 23:14:02.765388 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4729 23:14:02.768509 iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288
4730 23:14:02.772304 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4731 23:14:02.776006 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4732 23:14:02.778999 iDelay=205, Bit 4, Center 44 (-99 ~ 188) 288
4733 23:14:02.785347 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4734 23:14:02.788823 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4735 23:14:02.792603 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4736 23:14:02.795361 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4737 23:14:02.799018 iDelay=205, Bit 9, Center 36 (-107 ~ 180) 288
4738 23:14:02.805307 iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296
4739 23:14:02.808686 iDelay=205, Bit 11, Center 36 (-107 ~ 180) 288
4740 23:14:02.812245 iDelay=205, Bit 12, Center 56 (-91 ~ 204) 296
4741 23:14:02.815556 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4742 23:14:02.822048 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4743 23:14:02.825538 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4744 23:14:02.826006 ==
4745 23:14:02.828390 Dram Type= 6, Freq= 0, CH_1, rank 1
4746 23:14:02.831802 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4747 23:14:02.832226 ==
4748 23:14:02.835314 DQS Delay:
4749 23:14:02.835737 DQS0 = 0, DQS1 = 0
4750 23:14:02.836072 DQM Delay:
4751 23:14:02.838721 DQM0 = 48, DQM1 = 45
4752 23:14:02.839141 DQ Delay:
4753 23:14:02.842223 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4754 23:14:02.845222 DQ4 =44, DQ5 =60, DQ6 =60, DQ7 =48
4755 23:14:02.848471 DQ8 =32, DQ9 =36, DQ10 =48, DQ11 =36
4756 23:14:02.852131 DQ12 =56, DQ13 =52, DQ14 =48, DQ15 =52
4757 23:14:02.852651
4758 23:14:02.852987
4759 23:14:02.861647 [DQSOSCAuto] RK1, (LSB)MR18= 0x6c23, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 389 ps
4760 23:14:02.862091 CH1 RK1: MR19=808, MR18=6C23
4761 23:14:02.868848 CH1_RK1: MR19=0x808, MR18=0x6C23, DQSOSC=389, MR23=63, INC=173, DEC=115
4762 23:14:02.872256 [RxdqsGatingPostProcess] freq 600
4763 23:14:02.878455 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4764 23:14:02.881794 Pre-setting of DQS Precalculation
4765 23:14:02.885341 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4766 23:14:02.892039 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4767 23:14:02.901926 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4768 23:14:02.902364
4769 23:14:02.902894
4770 23:14:02.904963 [Calibration Summary] 1200 Mbps
4771 23:14:02.905485 CH 0, Rank 0
4772 23:14:02.908651 SW Impedance : PASS
4773 23:14:02.909083 DUTY Scan : NO K
4774 23:14:02.912131 ZQ Calibration : PASS
4775 23:14:02.912643 Jitter Meter : NO K
4776 23:14:02.915558 CBT Training : PASS
4777 23:14:02.918178 Write leveling : PASS
4778 23:14:02.918595 RX DQS gating : PASS
4779 23:14:02.921699 RX DQ/DQS(RDDQC) : PASS
4780 23:14:02.925146 TX DQ/DQS : PASS
4781 23:14:02.925648 RX DATLAT : PASS
4782 23:14:02.928739 RX DQ/DQS(Engine): PASS
4783 23:14:02.931537 TX OE : NO K
4784 23:14:02.931952 All Pass.
4785 23:14:02.932383
4786 23:14:02.932762 CH 0, Rank 1
4787 23:14:02.934947 SW Impedance : PASS
4788 23:14:02.938168 DUTY Scan : NO K
4789 23:14:02.938585 ZQ Calibration : PASS
4790 23:14:02.942101 Jitter Meter : NO K
4791 23:14:02.944911 CBT Training : PASS
4792 23:14:02.945414 Write leveling : PASS
4793 23:14:02.948465 RX DQS gating : PASS
4794 23:14:02.951959 RX DQ/DQS(RDDQC) : PASS
4795 23:14:02.952494 TX DQ/DQS : PASS
4796 23:14:02.955283 RX DATLAT : PASS
4797 23:14:02.955703 RX DQ/DQS(Engine): PASS
4798 23:14:02.958504 TX OE : NO K
4799 23:14:02.958994 All Pass.
4800 23:14:02.959356
4801 23:14:02.961940 CH 1, Rank 0
4802 23:14:02.962360 SW Impedance : PASS
4803 23:14:02.964724 DUTY Scan : NO K
4804 23:14:02.968463 ZQ Calibration : PASS
4805 23:14:02.968933 Jitter Meter : NO K
4806 23:14:02.971716 CBT Training : PASS
4807 23:14:02.975016 Write leveling : PASS
4808 23:14:02.975745 RX DQS gating : PASS
4809 23:14:02.978638 RX DQ/DQS(RDDQC) : PASS
4810 23:14:02.981472 TX DQ/DQS : PASS
4811 23:14:02.981972 RX DATLAT : PASS
4812 23:14:02.985331 RX DQ/DQS(Engine): PASS
4813 23:14:02.988081 TX OE : NO K
4814 23:14:02.988546 All Pass.
4815 23:14:02.988913
4816 23:14:02.989222 CH 1, Rank 1
4817 23:14:02.991374 SW Impedance : PASS
4818 23:14:02.995219 DUTY Scan : NO K
4819 23:14:02.995633 ZQ Calibration : PASS
4820 23:14:02.998254 Jitter Meter : NO K
4821 23:14:03.001741 CBT Training : PASS
4822 23:14:03.002151 Write leveling : PASS
4823 23:14:03.004969 RX DQS gating : PASS
4824 23:14:03.005380 RX DQ/DQS(RDDQC) : PASS
4825 23:14:03.008796 TX DQ/DQS : PASS
4826 23:14:03.011678 RX DATLAT : PASS
4827 23:14:03.012090 RX DQ/DQS(Engine): PASS
4828 23:14:03.015188 TX OE : NO K
4829 23:14:03.015604 All Pass.
4830 23:14:03.015931
4831 23:14:03.018177 DramC Write-DBI off
4832 23:14:03.021503 PER_BANK_REFRESH: Hybrid Mode
4833 23:14:03.021954 TX_TRACKING: ON
4834 23:14:03.031664 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4835 23:14:03.034957 [FAST_K] Save calibration result to emmc
4836 23:14:03.038070 dramc_set_vcore_voltage set vcore to 662500
4837 23:14:03.041290 Read voltage for 933, 3
4838 23:14:03.041776 Vio18 = 0
4839 23:14:03.042116 Vcore = 662500
4840 23:14:03.044767 Vdram = 0
4841 23:14:03.045180 Vddq = 0
4842 23:14:03.045507 Vmddr = 0
4843 23:14:03.051460 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4844 23:14:03.054984 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4845 23:14:03.058525 MEM_TYPE=3, freq_sel=17
4846 23:14:03.061412 sv_algorithm_assistance_LP4_1600
4847 23:14:03.064990 ============ PULL DRAM RESETB DOWN ============
4848 23:14:03.068299 ========== PULL DRAM RESETB DOWN end =========
4849 23:14:03.074810 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4850 23:14:03.077806 ===================================
4851 23:14:03.081329 LPDDR4 DRAM CONFIGURATION
4852 23:14:03.081783 ===================================
4853 23:14:03.084766 EX_ROW_EN[0] = 0x0
4854 23:14:03.087784 EX_ROW_EN[1] = 0x0
4855 23:14:03.088201 LP4Y_EN = 0x0
4856 23:14:03.091195 WORK_FSP = 0x0
4857 23:14:03.091609 WL = 0x3
4858 23:14:03.094964 RL = 0x3
4859 23:14:03.095378 BL = 0x2
4860 23:14:03.098168 RPST = 0x0
4861 23:14:03.098580 RD_PRE = 0x0
4862 23:14:03.101230 WR_PRE = 0x1
4863 23:14:03.101848 WR_PST = 0x0
4864 23:14:03.104630 DBI_WR = 0x0
4865 23:14:03.105153 DBI_RD = 0x0
4866 23:14:03.107878 OTF = 0x1
4867 23:14:03.111231 ===================================
4868 23:14:03.114509 ===================================
4869 23:14:03.114925 ANA top config
4870 23:14:03.117734 ===================================
4871 23:14:03.121324 DLL_ASYNC_EN = 0
4872 23:14:03.124352 ALL_SLAVE_EN = 1
4873 23:14:03.127699 NEW_RANK_MODE = 1
4874 23:14:03.128163 DLL_IDLE_MODE = 1
4875 23:14:03.131378 LP45_APHY_COMB_EN = 1
4876 23:14:03.134589 TX_ODT_DIS = 1
4877 23:14:03.138163 NEW_8X_MODE = 1
4878 23:14:03.141133 ===================================
4879 23:14:03.144601 ===================================
4880 23:14:03.148006 data_rate = 1866
4881 23:14:03.148456 CKR = 1
4882 23:14:03.151149 DQ_P2S_RATIO = 8
4883 23:14:03.154658 ===================================
4884 23:14:03.158285 CA_P2S_RATIO = 8
4885 23:14:03.161039 DQ_CA_OPEN = 0
4886 23:14:03.164694 DQ_SEMI_OPEN = 0
4887 23:14:03.168029 CA_SEMI_OPEN = 0
4888 23:14:03.168547 CA_FULL_RATE = 0
4889 23:14:03.171175 DQ_CKDIV4_EN = 1
4890 23:14:03.174270 CA_CKDIV4_EN = 1
4891 23:14:03.177675 CA_PREDIV_EN = 0
4892 23:14:03.181524 PH8_DLY = 0
4893 23:14:03.184479 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4894 23:14:03.184999 DQ_AAMCK_DIV = 4
4895 23:14:03.187384 CA_AAMCK_DIV = 4
4896 23:14:03.190630 CA_ADMCK_DIV = 4
4897 23:14:03.194511 DQ_TRACK_CA_EN = 0
4898 23:14:03.197518 CA_PICK = 933
4899 23:14:03.200911 CA_MCKIO = 933
4900 23:14:03.204464 MCKIO_SEMI = 0
4901 23:14:03.205026 PLL_FREQ = 3732
4902 23:14:03.207449 DQ_UI_PI_RATIO = 32
4903 23:14:03.210760 CA_UI_PI_RATIO = 0
4904 23:14:03.213977 ===================================
4905 23:14:03.217285 ===================================
4906 23:14:03.220318 memory_type:LPDDR4
4907 23:14:03.223712 GP_NUM : 10
4908 23:14:03.224160 SRAM_EN : 1
4909 23:14:03.226955 MD32_EN : 0
4910 23:14:03.230435 ===================================
4911 23:14:03.230858 [ANA_INIT] >>>>>>>>>>>>>>
4912 23:14:03.233924 <<<<<< [CONFIGURE PHASE]: ANA_TX
4913 23:14:03.236966 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4914 23:14:03.240365 ===================================
4915 23:14:03.243945 data_rate = 1866,PCW = 0X8f00
4916 23:14:03.247074 ===================================
4917 23:14:03.250239 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4918 23:14:03.257384 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4919 23:14:03.260687 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4920 23:14:03.267320 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4921 23:14:03.270429 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4922 23:14:03.273854 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4923 23:14:03.277729 [ANA_INIT] flow start
4924 23:14:03.278250 [ANA_INIT] PLL >>>>>>>>
4925 23:14:03.280737 [ANA_INIT] PLL <<<<<<<<
4926 23:14:03.284072 [ANA_INIT] MIDPI >>>>>>>>
4927 23:14:03.284620 [ANA_INIT] MIDPI <<<<<<<<
4928 23:14:03.286861 [ANA_INIT] DLL >>>>>>>>
4929 23:14:03.290534 [ANA_INIT] flow end
4930 23:14:03.294209 ============ LP4 DIFF to SE enter ============
4931 23:14:03.296792 ============ LP4 DIFF to SE exit ============
4932 23:14:03.300225 [ANA_INIT] <<<<<<<<<<<<<
4933 23:14:03.303367 [Flow] Enable top DCM control >>>>>
4934 23:14:03.307025 [Flow] Enable top DCM control <<<<<
4935 23:14:03.310154 Enable DLL master slave shuffle
4936 23:14:03.314243 ==============================================================
4937 23:14:03.317654 Gating Mode config
4938 23:14:03.320557 ==============================================================
4939 23:14:03.323543 Config description:
4940 23:14:03.333763 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4941 23:14:03.340605 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4942 23:14:03.343877 SELPH_MODE 0: By rank 1: By Phase
4943 23:14:03.350166 ==============================================================
4944 23:14:03.353570 GAT_TRACK_EN = 1
4945 23:14:03.357427 RX_GATING_MODE = 2
4946 23:14:03.360154 RX_GATING_TRACK_MODE = 2
4947 23:14:03.363962 SELPH_MODE = 1
4948 23:14:03.367238 PICG_EARLY_EN = 1
4949 23:14:03.367734 VALID_LAT_VALUE = 1
4950 23:14:03.373858 ==============================================================
4951 23:14:03.377553 Enter into Gating configuration >>>>
4952 23:14:03.380499 Exit from Gating configuration <<<<
4953 23:14:03.383846 Enter into DVFS_PRE_config >>>>>
4954 23:14:03.393743 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4955 23:14:03.396841 Exit from DVFS_PRE_config <<<<<
4956 23:14:03.400419 Enter into PICG configuration >>>>
4957 23:14:03.403572 Exit from PICG configuration <<<<
4958 23:14:03.406879 [RX_INPUT] configuration >>>>>
4959 23:14:03.410050 [RX_INPUT] configuration <<<<<
4960 23:14:03.413944 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4961 23:14:03.420376 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4962 23:14:03.426781 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4963 23:14:03.433802 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4964 23:14:03.440618 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4965 23:14:03.447103 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4966 23:14:03.449903 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4967 23:14:03.453421 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4968 23:14:03.456795 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4969 23:14:03.459938 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4970 23:14:03.466699 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4971 23:14:03.470257 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4972 23:14:03.473391 ===================================
4973 23:14:03.476660 LPDDR4 DRAM CONFIGURATION
4974 23:14:03.480248 ===================================
4975 23:14:03.480664 EX_ROW_EN[0] = 0x0
4976 23:14:03.483073 EX_ROW_EN[1] = 0x0
4977 23:14:03.483487 LP4Y_EN = 0x0
4978 23:14:03.486680 WORK_FSP = 0x0
4979 23:14:03.487093 WL = 0x3
4980 23:14:03.489705 RL = 0x3
4981 23:14:03.490136 BL = 0x2
4982 23:14:03.493370 RPST = 0x0
4983 23:14:03.496360 RD_PRE = 0x0
4984 23:14:03.496769 WR_PRE = 0x1
4985 23:14:03.499939 WR_PST = 0x0
4986 23:14:03.500393 DBI_WR = 0x0
4987 23:14:03.503512 DBI_RD = 0x0
4988 23:14:03.503921 OTF = 0x1
4989 23:14:03.506368 ===================================
4990 23:14:03.510104 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4991 23:14:03.516321 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4992 23:14:03.520345 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4993 23:14:03.523419 ===================================
4994 23:14:03.526296 LPDDR4 DRAM CONFIGURATION
4995 23:14:03.529705 ===================================
4996 23:14:03.530178 EX_ROW_EN[0] = 0x10
4997 23:14:03.532744 EX_ROW_EN[1] = 0x0
4998 23:14:03.533173 LP4Y_EN = 0x0
4999 23:14:03.536098 WORK_FSP = 0x0
5000 23:14:03.536555 WL = 0x3
5001 23:14:03.539748 RL = 0x3
5002 23:14:03.540174 BL = 0x2
5003 23:14:03.543105 RPST = 0x0
5004 23:14:03.543528 RD_PRE = 0x0
5005 23:14:03.546400 WR_PRE = 0x1
5006 23:14:03.549872 WR_PST = 0x0
5007 23:14:03.550299 DBI_WR = 0x0
5008 23:14:03.552982 DBI_RD = 0x0
5009 23:14:03.553517 OTF = 0x1
5010 23:14:03.556394 ===================================
5011 23:14:03.562778 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5012 23:14:03.566430 nWR fixed to 30
5013 23:14:03.569944 [ModeRegInit_LP4] CH0 RK0
5014 23:14:03.570357 [ModeRegInit_LP4] CH0 RK1
5015 23:14:03.572773 [ModeRegInit_LP4] CH1 RK0
5016 23:14:03.576451 [ModeRegInit_LP4] CH1 RK1
5017 23:14:03.576895 match AC timing 9
5018 23:14:03.583480 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5019 23:14:03.586468 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5020 23:14:03.589474 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5021 23:14:03.596334 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5022 23:14:03.599858 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5023 23:14:03.600311 ==
5024 23:14:03.602633 Dram Type= 6, Freq= 0, CH_0, rank 0
5025 23:14:03.606284 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5026 23:14:03.606699 ==
5027 23:14:03.612734 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5028 23:14:03.619194 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5029 23:14:03.622602 [CA 0] Center 37 (6~68) winsize 63
5030 23:14:03.626288 [CA 1] Center 37 (7~68) winsize 62
5031 23:14:03.629539 [CA 2] Center 34 (4~65) winsize 62
5032 23:14:03.632807 [CA 3] Center 34 (3~65) winsize 63
5033 23:14:03.635736 [CA 4] Center 33 (3~64) winsize 62
5034 23:14:03.638948 [CA 5] Center 32 (2~62) winsize 61
5035 23:14:03.639362
5036 23:14:03.642756 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5037 23:14:03.643192
5038 23:14:03.645889 [CATrainingPosCal] consider 1 rank data
5039 23:14:03.648948 u2DelayCellTimex100 = 270/100 ps
5040 23:14:03.652558 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5041 23:14:03.655997 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5042 23:14:03.659402 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5043 23:14:03.662276 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5044 23:14:03.668832 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5045 23:14:03.672234 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5046 23:14:03.672650
5047 23:14:03.675973 CA PerBit enable=1, Macro0, CA PI delay=32
5048 23:14:03.676460
5049 23:14:03.678911 [CBTSetCACLKResult] CA Dly = 32
5050 23:14:03.679326 CS Dly: 5 (0~36)
5051 23:14:03.679661 ==
5052 23:14:03.682260 Dram Type= 6, Freq= 0, CH_0, rank 1
5053 23:14:03.688889 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5054 23:14:03.689369 ==
5055 23:14:03.692000 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5056 23:14:03.698605 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5057 23:14:03.702210 [CA 0] Center 37 (6~68) winsize 63
5058 23:14:03.705317 [CA 1] Center 37 (6~68) winsize 63
5059 23:14:03.708443 [CA 2] Center 34 (4~65) winsize 62
5060 23:14:03.712009 [CA 3] Center 34 (3~65) winsize 63
5061 23:14:03.715277 [CA 4] Center 33 (3~64) winsize 62
5062 23:14:03.718308 [CA 5] Center 32 (2~62) winsize 61
5063 23:14:03.718724
5064 23:14:03.721819 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5065 23:14:03.722240
5066 23:14:03.725245 [CATrainingPosCal] consider 2 rank data
5067 23:14:03.728770 u2DelayCellTimex100 = 270/100 ps
5068 23:14:03.731894 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5069 23:14:03.735180 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5070 23:14:03.738556 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5071 23:14:03.745466 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5072 23:14:03.748577 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5073 23:14:03.751984 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5074 23:14:03.752402
5075 23:14:03.755121 CA PerBit enable=1, Macro0, CA PI delay=32
5076 23:14:03.755539
5077 23:14:03.758378 [CBTSetCACLKResult] CA Dly = 32
5078 23:14:03.758794 CS Dly: 5 (0~37)
5079 23:14:03.759149
5080 23:14:03.761934 ----->DramcWriteLeveling(PI) begin...
5081 23:14:03.765096 ==
5082 23:14:03.768409 Dram Type= 6, Freq= 0, CH_0, rank 0
5083 23:14:03.771499 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5084 23:14:03.771916 ==
5085 23:14:03.775382 Write leveling (Byte 0): 30 => 30
5086 23:14:03.778678 Write leveling (Byte 1): 28 => 28
5087 23:14:03.781987 DramcWriteLeveling(PI) end<-----
5088 23:14:03.782443
5089 23:14:03.782812 ==
5090 23:14:03.784842 Dram Type= 6, Freq= 0, CH_0, rank 0
5091 23:14:03.788699 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5092 23:14:03.789188 ==
5093 23:14:03.791987 [Gating] SW mode calibration
5094 23:14:03.798678 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5095 23:14:03.801848 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5096 23:14:03.808397 0 14 0 | B1->B0 | 2626 3434 | 1 1 | (0 0) (1 1)
5097 23:14:03.811544 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5098 23:14:03.815274 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5099 23:14:03.821440 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5100 23:14:03.825167 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5101 23:14:03.828204 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5102 23:14:03.835077 0 14 24 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 0)
5103 23:14:03.838686 0 14 28 | B1->B0 | 3333 2727 | 1 0 | (1 1) (1 0)
5104 23:14:03.841436 0 15 0 | B1->B0 | 2f2f 2323 | 0 0 | (0 1) (0 0)
5105 23:14:03.848378 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5106 23:14:03.852161 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5107 23:14:03.855364 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5108 23:14:03.861811 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5109 23:14:03.864911 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5110 23:14:03.868242 0 15 24 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5111 23:14:03.875050 0 15 28 | B1->B0 | 2424 3939 | 0 0 | (0 0) (0 0)
5112 23:14:03.878483 1 0 0 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
5113 23:14:03.881717 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5114 23:14:03.888511 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5115 23:14:03.892136 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5116 23:14:03.895094 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5117 23:14:03.901685 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5118 23:14:03.905166 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5119 23:14:03.908237 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5120 23:14:03.911899 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5121 23:14:03.918325 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5122 23:14:03.921453 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5123 23:14:03.924857 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5124 23:14:03.931891 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5125 23:14:03.934643 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5126 23:14:03.937905 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5127 23:14:03.944644 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5128 23:14:03.948110 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5129 23:14:03.951717 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5130 23:14:03.957866 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5131 23:14:03.961216 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5132 23:14:03.964808 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5133 23:14:03.971518 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5134 23:14:03.974433 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5135 23:14:03.978151 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5136 23:14:03.981481 Total UI for P1: 0, mck2ui 16
5137 23:14:03.984474 best dqsien dly found for B0: ( 1, 2, 24)
5138 23:14:03.991159 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5139 23:14:03.991656 Total UI for P1: 0, mck2ui 16
5140 23:14:03.997749 best dqsien dly found for B1: ( 1, 2, 28)
5141 23:14:04.001141 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5142 23:14:04.004755 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5143 23:14:04.005181
5144 23:14:04.007725 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5145 23:14:04.011096 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5146 23:14:04.014324 [Gating] SW calibration Done
5147 23:14:04.014762 ==
5148 23:14:04.017869 Dram Type= 6, Freq= 0, CH_0, rank 0
5149 23:14:04.021280 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5150 23:14:04.021738 ==
5151 23:14:04.024813 RX Vref Scan: 0
5152 23:14:04.025231
5153 23:14:04.025566 RX Vref 0 -> 0, step: 1
5154 23:14:04.025940
5155 23:14:04.027643 RX Delay -80 -> 252, step: 8
5156 23:14:04.030840 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5157 23:14:04.037400 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5158 23:14:04.040949 iDelay=208, Bit 2, Center 103 (16 ~ 191) 176
5159 23:14:04.044344 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5160 23:14:04.047925 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5161 23:14:04.051137 iDelay=208, Bit 5, Center 91 (0 ~ 183) 184
5162 23:14:04.057564 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5163 23:14:04.060902 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5164 23:14:04.064284 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5165 23:14:04.067120 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5166 23:14:04.070535 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5167 23:14:04.074254 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5168 23:14:04.080642 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5169 23:14:04.083943 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5170 23:14:04.087594 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5171 23:14:04.090799 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5172 23:14:04.091237 ==
5173 23:14:04.094111 Dram Type= 6, Freq= 0, CH_0, rank 0
5174 23:14:04.097290 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5175 23:14:04.097777 ==
5176 23:14:04.100941 DQS Delay:
5177 23:14:04.101360 DQS0 = 0, DQS1 = 0
5178 23:14:04.103800 DQM Delay:
5179 23:14:04.104223 DQM0 = 105, DQM1 = 95
5180 23:14:04.104557 DQ Delay:
5181 23:14:04.107375 DQ0 =107, DQ1 =107, DQ2 =103, DQ3 =99
5182 23:14:04.113992 DQ4 =107, DQ5 =91, DQ6 =115, DQ7 =115
5183 23:14:04.114431 DQ8 =87, DQ9 =87, DQ10 =95, DQ11 =91
5184 23:14:04.120622 DQ12 =99, DQ13 =99, DQ14 =103, DQ15 =99
5185 23:14:04.121063
5186 23:14:04.121397
5187 23:14:04.121779 ==
5188 23:14:04.124299 Dram Type= 6, Freq= 0, CH_0, rank 0
5189 23:14:04.127423 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5190 23:14:04.127850 ==
5191 23:14:04.128190
5192 23:14:04.128499
5193 23:14:04.130816 TX Vref Scan disable
5194 23:14:04.131284 == TX Byte 0 ==
5195 23:14:04.137515 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5196 23:14:04.140344 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5197 23:14:04.140768 == TX Byte 1 ==
5198 23:14:04.147206 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5199 23:14:04.150095 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5200 23:14:04.150568 ==
5201 23:14:04.153839 Dram Type= 6, Freq= 0, CH_0, rank 0
5202 23:14:04.157079 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5203 23:14:04.157685 ==
5204 23:14:04.158038
5205 23:14:04.160445
5206 23:14:04.160934 TX Vref Scan disable
5207 23:14:04.163728 == TX Byte 0 ==
5208 23:14:04.167238 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5209 23:14:04.170031 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5210 23:14:04.173536 == TX Byte 1 ==
5211 23:14:04.176578 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5212 23:14:04.183312 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5213 23:14:04.183854
5214 23:14:04.184192 [DATLAT]
5215 23:14:04.184524 Freq=933, CH0 RK0
5216 23:14:04.184834
5217 23:14:04.186398 DATLAT Default: 0xd
5218 23:14:04.186816 0, 0xFFFF, sum = 0
5219 23:14:04.190216 1, 0xFFFF, sum = 0
5220 23:14:04.190663 2, 0xFFFF, sum = 0
5221 23:14:04.194284 3, 0xFFFF, sum = 0
5222 23:14:04.196511 4, 0xFFFF, sum = 0
5223 23:14:04.196992 5, 0xFFFF, sum = 0
5224 23:14:04.200043 6, 0xFFFF, sum = 0
5225 23:14:04.200472 7, 0xFFFF, sum = 0
5226 23:14:04.202966 8, 0xFFFF, sum = 0
5227 23:14:04.203390 9, 0xFFFF, sum = 0
5228 23:14:04.206913 10, 0x0, sum = 1
5229 23:14:04.207355 11, 0x0, sum = 2
5230 23:14:04.207696 12, 0x0, sum = 3
5231 23:14:04.209673 13, 0x0, sum = 4
5232 23:14:04.210093 best_step = 11
5233 23:14:04.210424
5234 23:14:04.213368 ==
5235 23:14:04.213828 Dram Type= 6, Freq= 0, CH_0, rank 0
5236 23:14:04.219854 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5237 23:14:04.220340 ==
5238 23:14:04.220682 RX Vref Scan: 1
5239 23:14:04.221120
5240 23:14:04.223314 RX Vref 0 -> 0, step: 1
5241 23:14:04.223753
5242 23:14:04.226543 RX Delay -45 -> 252, step: 4
5243 23:14:04.226967
5244 23:14:04.230028 Set Vref, RX VrefLevel [Byte0]: 56
5245 23:14:04.233362 [Byte1]: 54
5246 23:14:04.233820
5247 23:14:04.236388 Final RX Vref Byte 0 = 56 to rank0
5248 23:14:04.239831 Final RX Vref Byte 1 = 54 to rank0
5249 23:14:04.243816 Final RX Vref Byte 0 = 56 to rank1
5250 23:14:04.246522 Final RX Vref Byte 1 = 54 to rank1==
5251 23:14:04.249896 Dram Type= 6, Freq= 0, CH_0, rank 0
5252 23:14:04.253439 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5253 23:14:04.253914 ==
5254 23:14:04.256866 DQS Delay:
5255 23:14:04.257388 DQS0 = 0, DQS1 = 0
5256 23:14:04.260076 DQM Delay:
5257 23:14:04.260494 DQM0 = 104, DQM1 = 97
5258 23:14:04.260830 DQ Delay:
5259 23:14:04.262904 DQ0 =104, DQ1 =106, DQ2 =104, DQ3 =102
5260 23:14:04.266443 DQ4 =104, DQ5 =96, DQ6 =112, DQ7 =110
5261 23:14:04.269916 DQ8 =86, DQ9 =88, DQ10 =96, DQ11 =92
5262 23:14:04.276472 DQ12 =102, DQ13 =102, DQ14 =106, DQ15 =106
5263 23:14:04.276899
5264 23:14:04.277235
5265 23:14:04.283309 [DQSOSCAuto] RK0, (LSB)MR18= 0x3129, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 406 ps
5266 23:14:04.286766 CH0 RK0: MR19=505, MR18=3129
5267 23:14:04.293047 CH0_RK0: MR19=0x505, MR18=0x3129, DQSOSC=406, MR23=63, INC=65, DEC=43
5268 23:14:04.293539
5269 23:14:04.296722 ----->DramcWriteLeveling(PI) begin...
5270 23:14:04.297150 ==
5271 23:14:04.300209 Dram Type= 6, Freq= 0, CH_0, rank 1
5272 23:14:04.303172 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5273 23:14:04.303600 ==
5274 23:14:04.306193 Write leveling (Byte 0): 33 => 33
5275 23:14:04.309659 Write leveling (Byte 1): 28 => 28
5276 23:14:04.312819 DramcWriteLeveling(PI) end<-----
5277 23:14:04.313243
5278 23:14:04.313621 ==
5279 23:14:04.315961 Dram Type= 6, Freq= 0, CH_0, rank 1
5280 23:14:04.319471 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5281 23:14:04.319900 ==
5282 23:14:04.322910 [Gating] SW mode calibration
5283 23:14:04.329638 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5284 23:14:04.336316 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5285 23:14:04.339482 0 14 0 | B1->B0 | 3232 3333 | 1 1 | (1 1) (1 1)
5286 23:14:04.346364 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5287 23:14:04.349605 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5288 23:14:04.352844 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5289 23:14:04.359130 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5290 23:14:04.362949 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5291 23:14:04.365971 0 14 24 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
5292 23:14:04.369715 0 14 28 | B1->B0 | 2b2b 2d2d | 0 0 | (0 0) (0 0)
5293 23:14:04.376065 0 15 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (1 0)
5294 23:14:04.378993 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5295 23:14:04.382562 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5296 23:14:04.389020 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5297 23:14:04.392631 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5298 23:14:04.396063 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5299 23:14:04.402452 0 15 24 | B1->B0 | 2727 2525 | 0 0 | (0 0) (0 0)
5300 23:14:04.406107 0 15 28 | B1->B0 | 3939 3333 | 0 0 | (0 0) (0 0)
5301 23:14:04.409097 1 0 0 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
5302 23:14:04.416097 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5303 23:14:04.418901 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5304 23:14:04.422566 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5305 23:14:04.428990 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5306 23:14:04.432477 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5307 23:14:04.436069 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5308 23:14:04.442374 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5309 23:14:04.445679 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5310 23:14:04.448960 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5311 23:14:04.455945 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5312 23:14:04.459186 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5313 23:14:04.462238 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5314 23:14:04.468717 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5315 23:14:04.472502 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5316 23:14:04.475774 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5317 23:14:04.482545 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5318 23:14:04.485265 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5319 23:14:04.488579 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5320 23:14:04.495364 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5321 23:14:04.498943 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5322 23:14:04.502485 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5323 23:14:04.509019 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5324 23:14:04.511866 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5325 23:14:04.515245 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5326 23:14:04.518843 Total UI for P1: 0, mck2ui 16
5327 23:14:04.522414 best dqsien dly found for B0: ( 1, 2, 26)
5328 23:14:04.525441 Total UI for P1: 0, mck2ui 16
5329 23:14:04.528986 best dqsien dly found for B1: ( 1, 2, 28)
5330 23:14:04.531879 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5331 23:14:04.535278 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5332 23:14:04.535692
5333 23:14:04.538806 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5334 23:14:04.545550 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5335 23:14:04.546013 [Gating] SW calibration Done
5336 23:14:04.546345 ==
5337 23:14:04.548376 Dram Type= 6, Freq= 0, CH_0, rank 1
5338 23:14:04.555443 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5339 23:14:04.555860 ==
5340 23:14:04.556187 RX Vref Scan: 0
5341 23:14:04.556496
5342 23:14:04.558424 RX Vref 0 -> 0, step: 1
5343 23:14:04.558907
5344 23:14:04.561961 RX Delay -80 -> 252, step: 8
5345 23:14:04.565552 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5346 23:14:04.568373 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5347 23:14:04.571819 iDelay=208, Bit 2, Center 103 (8 ~ 199) 192
5348 23:14:04.575142 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5349 23:14:04.581767 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5350 23:14:04.585144 iDelay=208, Bit 5, Center 99 (8 ~ 191) 184
5351 23:14:04.588704 iDelay=208, Bit 6, Center 111 (24 ~ 199) 176
5352 23:14:04.592121 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5353 23:14:04.595010 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5354 23:14:04.598072 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5355 23:14:04.604932 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5356 23:14:04.608511 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5357 23:14:04.611503 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5358 23:14:04.614937 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5359 23:14:04.618155 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5360 23:14:04.625187 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5361 23:14:04.625657 ==
5362 23:14:04.628218 Dram Type= 6, Freq= 0, CH_0, rank 1
5363 23:14:04.631783 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5364 23:14:04.632205 ==
5365 23:14:04.632542 DQS Delay:
5366 23:14:04.634775 DQS0 = 0, DQS1 = 0
5367 23:14:04.635197 DQM Delay:
5368 23:14:04.638368 DQM0 = 105, DQM1 = 94
5369 23:14:04.638814 DQ Delay:
5370 23:14:04.641280 DQ0 =103, DQ1 =107, DQ2 =103, DQ3 =99
5371 23:14:04.644809 DQ4 =107, DQ5 =99, DQ6 =111, DQ7 =115
5372 23:14:04.648248 DQ8 =87, DQ9 =87, DQ10 =95, DQ11 =87
5373 23:14:04.651873 DQ12 =99, DQ13 =99, DQ14 =103, DQ15 =99
5374 23:14:04.652296
5375 23:14:04.652633
5376 23:14:04.652962 ==
5377 23:14:04.654621 Dram Type= 6, Freq= 0, CH_0, rank 1
5378 23:14:04.658202 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5379 23:14:04.661633 ==
5380 23:14:04.662057
5381 23:14:04.662392
5382 23:14:04.662702 TX Vref Scan disable
5383 23:14:04.664658 == TX Byte 0 ==
5384 23:14:04.668328 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5385 23:14:04.671213 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5386 23:14:04.674673 == TX Byte 1 ==
5387 23:14:04.678416 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5388 23:14:04.681299 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5389 23:14:04.684361 ==
5390 23:14:04.687718 Dram Type= 6, Freq= 0, CH_0, rank 1
5391 23:14:04.691083 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5392 23:14:04.691508 ==
5393 23:14:04.691845
5394 23:14:04.692154
5395 23:14:04.694419 TX Vref Scan disable
5396 23:14:04.694842 == TX Byte 0 ==
5397 23:14:04.700769 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5398 23:14:04.704267 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5399 23:14:04.704694 == TX Byte 1 ==
5400 23:14:04.710884 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5401 23:14:04.714064 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5402 23:14:04.714491
5403 23:14:04.714831 [DATLAT]
5404 23:14:04.717678 Freq=933, CH0 RK1
5405 23:14:04.718107
5406 23:14:04.718446 DATLAT Default: 0xb
5407 23:14:04.720849 0, 0xFFFF, sum = 0
5408 23:14:04.721280 1, 0xFFFF, sum = 0
5409 23:14:04.724263 2, 0xFFFF, sum = 0
5410 23:14:04.724693 3, 0xFFFF, sum = 0
5411 23:14:04.727820 4, 0xFFFF, sum = 0
5412 23:14:04.728295 5, 0xFFFF, sum = 0
5413 23:14:04.731048 6, 0xFFFF, sum = 0
5414 23:14:04.734373 7, 0xFFFF, sum = 0
5415 23:14:04.734802 8, 0xFFFF, sum = 0
5416 23:14:04.737641 9, 0xFFFF, sum = 0
5417 23:14:04.738071 10, 0x0, sum = 1
5418 23:14:04.738413 11, 0x0, sum = 2
5419 23:14:04.740717 12, 0x0, sum = 3
5420 23:14:04.741166 13, 0x0, sum = 4
5421 23:14:04.744751 best_step = 11
5422 23:14:04.745234
5423 23:14:04.745605 ==
5424 23:14:04.747902 Dram Type= 6, Freq= 0, CH_0, rank 1
5425 23:14:04.750781 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5426 23:14:04.751209 ==
5427 23:14:04.754361 RX Vref Scan: 0
5428 23:14:04.754785
5429 23:14:04.755123 RX Vref 0 -> 0, step: 1
5430 23:14:04.755439
5431 23:14:04.757315 RX Delay -45 -> 252, step: 4
5432 23:14:04.765095 iDelay=199, Bit 0, Center 104 (15 ~ 194) 180
5433 23:14:04.768667 iDelay=199, Bit 1, Center 106 (19 ~ 194) 176
5434 23:14:04.771497 iDelay=199, Bit 2, Center 102 (15 ~ 190) 176
5435 23:14:04.775341 iDelay=199, Bit 3, Center 100 (11 ~ 190) 180
5436 23:14:04.778218 iDelay=199, Bit 4, Center 106 (19 ~ 194) 176
5437 23:14:04.784759 iDelay=199, Bit 5, Center 96 (7 ~ 186) 180
5438 23:14:04.788427 iDelay=199, Bit 6, Center 108 (23 ~ 194) 172
5439 23:14:04.791423 iDelay=199, Bit 7, Center 110 (23 ~ 198) 176
5440 23:14:04.794824 iDelay=199, Bit 8, Center 86 (3 ~ 170) 168
5441 23:14:04.798131 iDelay=199, Bit 9, Center 86 (3 ~ 170) 168
5442 23:14:04.804595 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5443 23:14:04.808126 iDelay=199, Bit 11, Center 90 (11 ~ 170) 160
5444 23:14:04.811389 iDelay=199, Bit 12, Center 102 (19 ~ 186) 168
5445 23:14:04.814322 iDelay=199, Bit 13, Center 100 (15 ~ 186) 172
5446 23:14:04.817708 iDelay=199, Bit 14, Center 104 (19 ~ 190) 172
5447 23:14:04.824462 iDelay=199, Bit 15, Center 102 (19 ~ 186) 168
5448 23:14:04.824926 ==
5449 23:14:04.827850 Dram Type= 6, Freq= 0, CH_0, rank 1
5450 23:14:04.831196 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5451 23:14:04.831680 ==
5452 23:14:04.832015 DQS Delay:
5453 23:14:04.834613 DQS0 = 0, DQS1 = 0
5454 23:14:04.835034 DQM Delay:
5455 23:14:04.838007 DQM0 = 104, DQM1 = 95
5456 23:14:04.838427 DQ Delay:
5457 23:14:04.841015 DQ0 =104, DQ1 =106, DQ2 =102, DQ3 =100
5458 23:14:04.844629 DQ4 =106, DQ5 =96, DQ6 =108, DQ7 =110
5459 23:14:04.847856 DQ8 =86, DQ9 =86, DQ10 =94, DQ11 =90
5460 23:14:04.851316 DQ12 =102, DQ13 =100, DQ14 =104, DQ15 =102
5461 23:14:04.851763
5462 23:14:04.852141
5463 23:14:04.861147 [DQSOSCAuto] RK1, (LSB)MR18= 0x2902, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 408 ps
5464 23:14:04.864700 CH0 RK1: MR19=505, MR18=2902
5465 23:14:04.868018 CH0_RK1: MR19=0x505, MR18=0x2902, DQSOSC=408, MR23=63, INC=65, DEC=43
5466 23:14:04.871249 [RxdqsGatingPostProcess] freq 933
5467 23:14:04.877885 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5468 23:14:04.880858 best DQS0 dly(2T, 0.5T) = (0, 10)
5469 23:14:04.884395 best DQS1 dly(2T, 0.5T) = (0, 10)
5470 23:14:04.888063 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5471 23:14:04.890889 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5472 23:14:04.894330 best DQS0 dly(2T, 0.5T) = (0, 10)
5473 23:14:04.897906 best DQS1 dly(2T, 0.5T) = (0, 10)
5474 23:14:04.901349 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5475 23:14:04.901868 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5476 23:14:04.904238 Pre-setting of DQS Precalculation
5477 23:14:04.911322 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5478 23:14:04.911854 ==
5479 23:14:04.914424 Dram Type= 6, Freq= 0, CH_1, rank 0
5480 23:14:04.917733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5481 23:14:04.918202 ==
5482 23:14:04.924365 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5483 23:14:04.931159 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5484 23:14:04.934437 [CA 0] Center 36 (6~67) winsize 62
5485 23:14:04.937556 [CA 1] Center 36 (6~67) winsize 62
5486 23:14:04.940736 [CA 2] Center 34 (4~65) winsize 62
5487 23:14:04.944306 [CA 3] Center 34 (4~64) winsize 61
5488 23:14:04.947645 [CA 4] Center 34 (4~65) winsize 62
5489 23:14:04.950707 [CA 5] Center 33 (3~64) winsize 62
5490 23:14:04.951247
5491 23:14:04.954065 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5492 23:14:04.954559
5493 23:14:04.957971 [CATrainingPosCal] consider 1 rank data
5494 23:14:04.960743 u2DelayCellTimex100 = 270/100 ps
5495 23:14:04.964490 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5496 23:14:04.967539 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5497 23:14:04.970775 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5498 23:14:04.974541 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5499 23:14:04.977439 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5500 23:14:04.980631 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5501 23:14:04.981097
5502 23:14:04.987333 CA PerBit enable=1, Macro0, CA PI delay=33
5503 23:14:04.987777
5504 23:14:04.988142 [CBTSetCACLKResult] CA Dly = 33
5505 23:14:04.990757 CS Dly: 6 (0~37)
5506 23:14:04.991168 ==
5507 23:14:04.994286 Dram Type= 6, Freq= 0, CH_1, rank 1
5508 23:14:04.997444 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5509 23:14:04.997913 ==
5510 23:14:05.004435 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5511 23:14:05.010800 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5512 23:14:05.014149 [CA 0] Center 36 (6~67) winsize 62
5513 23:14:05.017381 [CA 1] Center 37 (7~68) winsize 62
5514 23:14:05.020613 [CA 2] Center 35 (5~66) winsize 62
5515 23:14:05.024243 [CA 3] Center 34 (4~65) winsize 62
5516 23:14:05.027083 [CA 4] Center 34 (4~65) winsize 62
5517 23:14:05.030936 [CA 5] Center 34 (4~64) winsize 61
5518 23:14:05.031366
5519 23:14:05.034147 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5520 23:14:05.034567
5521 23:14:05.037041 [CATrainingPosCal] consider 2 rank data
5522 23:14:05.040787 u2DelayCellTimex100 = 270/100 ps
5523 23:14:05.044389 CA0 delay=36 (6~67),Diff = 2 PI (12 cell)
5524 23:14:05.047729 CA1 delay=37 (7~67),Diff = 3 PI (18 cell)
5525 23:14:05.050455 CA2 delay=35 (5~65),Diff = 1 PI (6 cell)
5526 23:14:05.054178 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
5527 23:14:05.057694 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5528 23:14:05.060927 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5529 23:14:05.061492
5530 23:14:05.067455 CA PerBit enable=1, Macro0, CA PI delay=34
5531 23:14:05.068089
5532 23:14:05.070751 [CBTSetCACLKResult] CA Dly = 34
5533 23:14:05.071450 CS Dly: 7 (0~40)
5534 23:14:05.071844
5535 23:14:05.073767 ----->DramcWriteLeveling(PI) begin...
5536 23:14:05.074238 ==
5537 23:14:05.077558 Dram Type= 6, Freq= 0, CH_1, rank 0
5538 23:14:05.080751 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5539 23:14:05.081219 ==
5540 23:14:05.083616 Write leveling (Byte 0): 27 => 27
5541 23:14:05.087185 Write leveling (Byte 1): 27 => 27
5542 23:14:05.090514 DramcWriteLeveling(PI) end<-----
5543 23:14:05.090995
5544 23:14:05.091422 ==
5545 23:14:05.093982 Dram Type= 6, Freq= 0, CH_1, rank 0
5546 23:14:05.100519 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5547 23:14:05.101116 ==
5548 23:14:05.101488 [Gating] SW mode calibration
5549 23:14:05.110190 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5550 23:14:05.113551 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5551 23:14:05.116907 0 14 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5552 23:14:05.123384 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5553 23:14:05.127100 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5554 23:14:05.129942 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5555 23:14:05.136967 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5556 23:14:05.140148 0 14 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5557 23:14:05.143415 0 14 24 | B1->B0 | 3434 2c2c | 1 1 | (1 0) (1 0)
5558 23:14:05.150318 0 14 28 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (0 0)
5559 23:14:05.153735 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5560 23:14:05.157255 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5561 23:14:05.163573 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5562 23:14:05.166768 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5563 23:14:05.170081 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5564 23:14:05.176506 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5565 23:14:05.179885 0 15 24 | B1->B0 | 2424 3333 | 0 0 | (0 0) (0 0)
5566 23:14:05.183434 0 15 28 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
5567 23:14:05.189559 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5568 23:14:05.193339 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5569 23:14:05.196336 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5570 23:14:05.202947 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5571 23:14:05.206534 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5572 23:14:05.209969 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5573 23:14:05.216489 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5574 23:14:05.219792 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5575 23:14:05.222722 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5576 23:14:05.229398 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5577 23:14:05.233216 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5578 23:14:05.236429 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5579 23:14:05.243003 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5580 23:14:05.246331 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5581 23:14:05.249275 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5582 23:14:05.256516 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5583 23:14:05.259376 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5584 23:14:05.262709 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5585 23:14:05.269489 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5586 23:14:05.272797 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5587 23:14:05.276284 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5588 23:14:05.282655 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5589 23:14:05.285942 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5590 23:14:05.288995 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5591 23:14:05.292759 Total UI for P1: 0, mck2ui 16
5592 23:14:05.295892 best dqsien dly found for B0: ( 1, 2, 26)
5593 23:14:05.299372 Total UI for P1: 0, mck2ui 16
5594 23:14:05.302602 best dqsien dly found for B1: ( 1, 2, 24)
5595 23:14:05.306157 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5596 23:14:05.309209 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5597 23:14:05.309794
5598 23:14:05.312593 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5599 23:14:05.319438 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5600 23:14:05.319862 [Gating] SW calibration Done
5601 23:14:05.320200 ==
5602 23:14:05.322971 Dram Type= 6, Freq= 0, CH_1, rank 0
5603 23:14:05.329015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5604 23:14:05.329438 ==
5605 23:14:05.329910 RX Vref Scan: 0
5606 23:14:05.330243
5607 23:14:05.332564 RX Vref 0 -> 0, step: 1
5608 23:14:05.332976
5609 23:14:05.335580 RX Delay -80 -> 252, step: 8
5610 23:14:05.339396 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5611 23:14:05.342557 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5612 23:14:05.346148 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5613 23:14:05.349507 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5614 23:14:05.356177 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5615 23:14:05.359322 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5616 23:14:05.362131 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5617 23:14:05.365742 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5618 23:14:05.368866 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5619 23:14:05.372243 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5620 23:14:05.378884 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5621 23:14:05.382237 iDelay=208, Bit 11, Center 95 (8 ~ 183) 176
5622 23:14:05.385209 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5623 23:14:05.388915 iDelay=208, Bit 13, Center 107 (16 ~ 199) 184
5624 23:14:05.392350 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5625 23:14:05.398742 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5626 23:14:05.399187 ==
5627 23:14:05.401914 Dram Type= 6, Freq= 0, CH_1, rank 0
5628 23:14:05.405447 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5629 23:14:05.406015 ==
5630 23:14:05.406413 DQS Delay:
5631 23:14:05.408904 DQS0 = 0, DQS1 = 0
5632 23:14:05.409319 DQM Delay:
5633 23:14:05.411782 DQM0 = 102, DQM1 = 99
5634 23:14:05.412277 DQ Delay:
5635 23:14:05.415173 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
5636 23:14:05.418493 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =103
5637 23:14:05.422189 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =95
5638 23:14:05.425057 DQ12 =107, DQ13 =107, DQ14 =103, DQ15 =107
5639 23:14:05.425547
5640 23:14:05.425953
5641 23:14:05.426274 ==
5642 23:14:05.428566 Dram Type= 6, Freq= 0, CH_1, rank 0
5643 23:14:05.435151 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5644 23:14:05.435580 ==
5645 23:14:05.435926
5646 23:14:05.436239
5647 23:14:05.436543 TX Vref Scan disable
5648 23:14:05.438753 == TX Byte 0 ==
5649 23:14:05.442150 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5650 23:14:05.448544 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5651 23:14:05.449192 == TX Byte 1 ==
5652 23:14:05.451980 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5653 23:14:05.458312 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5654 23:14:05.458740 ==
5655 23:14:05.461861 Dram Type= 6, Freq= 0, CH_1, rank 0
5656 23:14:05.465672 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5657 23:14:05.466196 ==
5658 23:14:05.466539
5659 23:14:05.466865
5660 23:14:05.468775 TX Vref Scan disable
5661 23:14:05.469346 == TX Byte 0 ==
5662 23:14:05.474938 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5663 23:14:05.478202 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5664 23:14:05.478671 == TX Byte 1 ==
5665 23:14:05.485379 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5666 23:14:05.488287 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5667 23:14:05.488718
5668 23:14:05.489151 [DATLAT]
5669 23:14:05.491709 Freq=933, CH1 RK0
5670 23:14:05.492172
5671 23:14:05.492723 DATLAT Default: 0xd
5672 23:14:05.495346 0, 0xFFFF, sum = 0
5673 23:14:05.495783 1, 0xFFFF, sum = 0
5674 23:14:05.498180 2, 0xFFFF, sum = 0
5675 23:14:05.498619 3, 0xFFFF, sum = 0
5676 23:14:05.501516 4, 0xFFFF, sum = 0
5677 23:14:05.501983 5, 0xFFFF, sum = 0
5678 23:14:05.505158 6, 0xFFFF, sum = 0
5679 23:14:05.508211 7, 0xFFFF, sum = 0
5680 23:14:05.508753 8, 0xFFFF, sum = 0
5681 23:14:05.511420 9, 0xFFFF, sum = 0
5682 23:14:05.511857 10, 0x0, sum = 1
5683 23:14:05.514907 11, 0x0, sum = 2
5684 23:14:05.515330 12, 0x0, sum = 3
5685 23:14:05.515673 13, 0x0, sum = 4
5686 23:14:05.517940 best_step = 11
5687 23:14:05.518354
5688 23:14:05.518679 ==
5689 23:14:05.521445 Dram Type= 6, Freq= 0, CH_1, rank 0
5690 23:14:05.524626 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5691 23:14:05.525096 ==
5692 23:14:05.528179 RX Vref Scan: 1
5693 23:14:05.528597
5694 23:14:05.529100 RX Vref 0 -> 0, step: 1
5695 23:14:05.531610
5696 23:14:05.532183 RX Delay -45 -> 252, step: 4
5697 23:14:05.532724
5698 23:14:05.534839 Set Vref, RX VrefLevel [Byte0]: 54
5699 23:14:05.538066 [Byte1]: 46
5700 23:14:05.542350
5701 23:14:05.542878 Final RX Vref Byte 0 = 54 to rank0
5702 23:14:05.545822 Final RX Vref Byte 1 = 46 to rank0
5703 23:14:05.548959 Final RX Vref Byte 0 = 54 to rank1
5704 23:14:05.552420 Final RX Vref Byte 1 = 46 to rank1==
5705 23:14:05.556057 Dram Type= 6, Freq= 0, CH_1, rank 0
5706 23:14:05.562185 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5707 23:14:05.562775 ==
5708 23:14:05.563125 DQS Delay:
5709 23:14:05.565409 DQS0 = 0, DQS1 = 0
5710 23:14:05.565976 DQM Delay:
5711 23:14:05.566310 DQM0 = 104, DQM1 = 98
5712 23:14:05.568675 DQ Delay:
5713 23:14:05.572202 DQ0 =106, DQ1 =98, DQ2 =94, DQ3 =102
5714 23:14:05.575674 DQ4 =104, DQ5 =112, DQ6 =114, DQ7 =104
5715 23:14:05.578983 DQ8 =86, DQ9 =88, DQ10 =98, DQ11 =92
5716 23:14:05.582077 DQ12 =106, DQ13 =104, DQ14 =106, DQ15 =106
5717 23:14:05.582602
5718 23:14:05.583044
5719 23:14:05.589209 [DQSOSCAuto] RK0, (LSB)MR18= 0x152d, (MSB)MR19= 0x505, tDQSOscB0 = 407 ps tDQSOscB1 = 415 ps
5720 23:14:05.591997 CH1 RK0: MR19=505, MR18=152D
5721 23:14:05.598503 CH1_RK0: MR19=0x505, MR18=0x152D, DQSOSC=407, MR23=63, INC=65, DEC=43
5722 23:14:05.598935
5723 23:14:05.601935 ----->DramcWriteLeveling(PI) begin...
5724 23:14:05.602428 ==
5725 23:14:05.605520 Dram Type= 6, Freq= 0, CH_1, rank 1
5726 23:14:05.609253 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5727 23:14:05.612074 ==
5728 23:14:05.612610 Write leveling (Byte 0): 26 => 26
5729 23:14:05.615416 Write leveling (Byte 1): 28 => 28
5730 23:14:05.618683 DramcWriteLeveling(PI) end<-----
5731 23:14:05.619139
5732 23:14:05.619571 ==
5733 23:14:05.622102 Dram Type= 6, Freq= 0, CH_1, rank 1
5734 23:14:05.628693 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5735 23:14:05.629218 ==
5736 23:14:05.629557 [Gating] SW mode calibration
5737 23:14:05.638751 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5738 23:14:05.641709 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5739 23:14:05.648842 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5740 23:14:05.652423 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5741 23:14:05.655572 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5742 23:14:05.658489 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5743 23:14:05.664943 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5744 23:14:05.668770 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5745 23:14:05.671984 0 14 24 | B1->B0 | 2525 3232 | 0 0 | (0 1) (0 1)
5746 23:14:05.678852 0 14 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5747 23:14:05.682159 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5748 23:14:05.685304 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5749 23:14:05.691867 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5750 23:14:05.695109 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5751 23:14:05.698554 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5752 23:14:05.705061 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5753 23:14:05.708298 0 15 24 | B1->B0 | 3333 2c2c | 0 1 | (0 0) (0 0)
5754 23:14:05.712225 0 15 28 | B1->B0 | 4646 4342 | 0 1 | (0 0) (0 0)
5755 23:14:05.718364 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5756 23:14:05.721861 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5757 23:14:05.724676 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5758 23:14:05.731429 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5759 23:14:05.734942 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5760 23:14:05.738587 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5761 23:14:05.745145 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5762 23:14:05.748037 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5763 23:14:05.751693 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5764 23:14:05.758052 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5765 23:14:05.761096 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5766 23:14:05.764584 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5767 23:14:05.771302 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5768 23:14:05.775008 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5769 23:14:05.778302 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5770 23:14:05.781648 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5771 23:14:05.787980 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5772 23:14:05.791453 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5773 23:14:05.794979 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5774 23:14:05.801448 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5775 23:14:05.804503 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5776 23:14:05.807865 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5777 23:14:05.814395 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5778 23:14:05.817550 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5779 23:14:05.821198 Total UI for P1: 0, mck2ui 16
5780 23:14:05.824648 best dqsien dly found for B1: ( 1, 2, 26)
5781 23:14:05.828002 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5782 23:14:05.831232 Total UI for P1: 0, mck2ui 16
5783 23:14:05.834202 best dqsien dly found for B0: ( 1, 2, 26)
5784 23:14:05.837962 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5785 23:14:05.841073 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5786 23:14:05.841533
5787 23:14:05.848172 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5788 23:14:05.851293 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5789 23:14:05.855097 [Gating] SW calibration Done
5790 23:14:05.855626 ==
5791 23:14:05.857768 Dram Type= 6, Freq= 0, CH_1, rank 1
5792 23:14:05.861686 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5793 23:14:05.862216 ==
5794 23:14:05.862582 RX Vref Scan: 0
5795 23:14:05.862926
5796 23:14:05.864287 RX Vref 0 -> 0, step: 1
5797 23:14:05.864846
5798 23:14:05.867799 RX Delay -80 -> 252, step: 8
5799 23:14:05.871521 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5800 23:14:05.874157 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5801 23:14:05.877797 iDelay=208, Bit 2, Center 95 (8 ~ 183) 176
5802 23:14:05.884740 iDelay=208, Bit 3, Center 95 (8 ~ 183) 176
5803 23:14:05.887914 iDelay=208, Bit 4, Center 95 (8 ~ 183) 176
5804 23:14:05.891230 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5805 23:14:05.894556 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5806 23:14:05.897918 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5807 23:14:05.901339 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5808 23:14:05.907613 iDelay=208, Bit 9, Center 91 (0 ~ 183) 184
5809 23:14:05.911267 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5810 23:14:05.914078 iDelay=208, Bit 11, Center 95 (8 ~ 183) 176
5811 23:14:05.917761 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5812 23:14:05.920978 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5813 23:14:05.927629 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5814 23:14:05.930980 iDelay=208, Bit 15, Center 103 (16 ~ 191) 176
5815 23:14:05.931473 ==
5816 23:14:05.934406 Dram Type= 6, Freq= 0, CH_1, rank 1
5817 23:14:05.937469 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5818 23:14:05.937977 ==
5819 23:14:05.938484 DQS Delay:
5820 23:14:05.941135 DQS0 = 0, DQS1 = 0
5821 23:14:05.941737 DQM Delay:
5822 23:14:05.944618 DQM0 = 102, DQM1 = 98
5823 23:14:05.945032 DQ Delay:
5824 23:14:05.947781 DQ0 =107, DQ1 =99, DQ2 =95, DQ3 =95
5825 23:14:05.951087 DQ4 =95, DQ5 =115, DQ6 =115, DQ7 =99
5826 23:14:05.954475 DQ8 =87, DQ9 =91, DQ10 =99, DQ11 =95
5827 23:14:05.957453 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =103
5828 23:14:05.957905
5829 23:14:05.958233
5830 23:14:05.958541 ==
5831 23:14:05.960948 Dram Type= 6, Freq= 0, CH_1, rank 1
5832 23:14:05.967363 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5833 23:14:05.967784 ==
5834 23:14:05.968226
5835 23:14:05.968545
5836 23:14:05.968841 TX Vref Scan disable
5837 23:14:05.970860 == TX Byte 0 ==
5838 23:14:05.974305 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5839 23:14:05.977992 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5840 23:14:05.981392 == TX Byte 1 ==
5841 23:14:05.984354 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5842 23:14:05.987909 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5843 23:14:05.991159 ==
5844 23:14:05.994356 Dram Type= 6, Freq= 0, CH_1, rank 1
5845 23:14:05.997947 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5846 23:14:05.998365 ==
5847 23:14:05.998695
5848 23:14:05.999055
5849 23:14:06.001197 TX Vref Scan disable
5850 23:14:06.001773 == TX Byte 0 ==
5851 23:14:06.007684 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5852 23:14:06.011072 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5853 23:14:06.011492 == TX Byte 1 ==
5854 23:14:06.017472 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5855 23:14:06.020938 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5856 23:14:06.021352
5857 23:14:06.021730 [DATLAT]
5858 23:14:06.024446 Freq=933, CH1 RK1
5859 23:14:06.024864
5860 23:14:06.025193 DATLAT Default: 0xb
5861 23:14:06.027473 0, 0xFFFF, sum = 0
5862 23:14:06.027938 1, 0xFFFF, sum = 0
5863 23:14:06.031100 2, 0xFFFF, sum = 0
5864 23:14:06.031598 3, 0xFFFF, sum = 0
5865 23:14:06.034410 4, 0xFFFF, sum = 0
5866 23:14:06.034833 5, 0xFFFF, sum = 0
5867 23:14:06.037628 6, 0xFFFF, sum = 0
5868 23:14:06.038036 7, 0xFFFF, sum = 0
5869 23:14:06.040812 8, 0xFFFF, sum = 0
5870 23:14:06.043843 9, 0xFFFF, sum = 0
5871 23:14:06.044265 10, 0x0, sum = 1
5872 23:14:06.044644 11, 0x0, sum = 2
5873 23:14:06.047223 12, 0x0, sum = 3
5874 23:14:06.047645 13, 0x0, sum = 4
5875 23:14:06.050856 best_step = 11
5876 23:14:06.051359
5877 23:14:06.051695 ==
5878 23:14:06.053800 Dram Type= 6, Freq= 0, CH_1, rank 1
5879 23:14:06.057701 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5880 23:14:06.058125 ==
5881 23:14:06.060468 RX Vref Scan: 0
5882 23:14:06.061053
5883 23:14:06.061630 RX Vref 0 -> 0, step: 1
5884 23:14:06.063817
5885 23:14:06.064234 RX Delay -45 -> 252, step: 4
5886 23:14:06.071846 iDelay=203, Bit 0, Center 108 (27 ~ 190) 164
5887 23:14:06.074687 iDelay=203, Bit 1, Center 100 (15 ~ 186) 172
5888 23:14:06.078121 iDelay=203, Bit 2, Center 94 (11 ~ 178) 168
5889 23:14:06.081564 iDelay=203, Bit 3, Center 100 (19 ~ 182) 164
5890 23:14:06.084492 iDelay=203, Bit 4, Center 100 (19 ~ 182) 164
5891 23:14:06.091170 iDelay=203, Bit 5, Center 118 (35 ~ 202) 168
5892 23:14:06.094567 iDelay=203, Bit 6, Center 112 (27 ~ 198) 172
5893 23:14:06.098235 iDelay=203, Bit 7, Center 104 (19 ~ 190) 172
5894 23:14:06.101452 iDelay=203, Bit 8, Center 90 (7 ~ 174) 168
5895 23:14:06.104352 iDelay=203, Bit 9, Center 90 (7 ~ 174) 168
5896 23:14:06.111051 iDelay=203, Bit 10, Center 102 (19 ~ 186) 168
5897 23:14:06.114394 iDelay=203, Bit 11, Center 92 (7 ~ 178) 172
5898 23:14:06.117723 iDelay=203, Bit 12, Center 106 (19 ~ 194) 176
5899 23:14:06.121413 iDelay=203, Bit 13, Center 102 (19 ~ 186) 168
5900 23:14:06.124798 iDelay=203, Bit 14, Center 102 (19 ~ 186) 168
5901 23:14:06.131322 iDelay=203, Bit 15, Center 106 (23 ~ 190) 168
5902 23:14:06.131800 ==
5903 23:14:06.134309 Dram Type= 6, Freq= 0, CH_1, rank 1
5904 23:14:06.137858 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5905 23:14:06.138276 ==
5906 23:14:06.138658 DQS Delay:
5907 23:14:06.141364 DQS0 = 0, DQS1 = 0
5908 23:14:06.141815 DQM Delay:
5909 23:14:06.144274 DQM0 = 104, DQM1 = 98
5910 23:14:06.144684 DQ Delay:
5911 23:14:06.147616 DQ0 =108, DQ1 =100, DQ2 =94, DQ3 =100
5912 23:14:06.151287 DQ4 =100, DQ5 =118, DQ6 =112, DQ7 =104
5913 23:14:06.154490 DQ8 =90, DQ9 =90, DQ10 =102, DQ11 =92
5914 23:14:06.157456 DQ12 =106, DQ13 =102, DQ14 =102, DQ15 =106
5915 23:14:06.158050
5916 23:14:06.158524
5917 23:14:06.167348 [DQSOSCAuto] RK1, (LSB)MR18= 0x2aff, (MSB)MR19= 0x504, tDQSOscB0 = 422 ps tDQSOscB1 = 408 ps
5918 23:14:06.171094 CH1 RK1: MR19=504, MR18=2AFF
5919 23:14:06.174093 CH1_RK1: MR19=0x504, MR18=0x2AFF, DQSOSC=408, MR23=63, INC=65, DEC=43
5920 23:14:06.180404 [RxdqsGatingPostProcess] freq 933
5921 23:14:06.183954 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5922 23:14:06.187673 best DQS0 dly(2T, 0.5T) = (0, 10)
5923 23:14:06.190527 best DQS1 dly(2T, 0.5T) = (0, 10)
5924 23:14:06.194061 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5925 23:14:06.197614 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5926 23:14:06.200697 best DQS0 dly(2T, 0.5T) = (0, 10)
5927 23:14:06.204078 best DQS1 dly(2T, 0.5T) = (0, 10)
5928 23:14:06.207421 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5929 23:14:06.210742 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5930 23:14:06.214088 Pre-setting of DQS Precalculation
5931 23:14:06.217375 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5932 23:14:06.224115 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5933 23:14:06.230367 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5934 23:14:06.230780
5935 23:14:06.231121
5936 23:14:06.233497 [Calibration Summary] 1866 Mbps
5937 23:14:06.237125 CH 0, Rank 0
5938 23:14:06.237535 SW Impedance : PASS
5939 23:14:06.240528 DUTY Scan : NO K
5940 23:14:06.244046 ZQ Calibration : PASS
5941 23:14:06.244594 Jitter Meter : NO K
5942 23:14:06.246891 CBT Training : PASS
5943 23:14:06.250283 Write leveling : PASS
5944 23:14:06.250694 RX DQS gating : PASS
5945 23:14:06.253306 RX DQ/DQS(RDDQC) : PASS
5946 23:14:06.256738 TX DQ/DQS : PASS
5947 23:14:06.257320 RX DATLAT : PASS
5948 23:14:06.260648 RX DQ/DQS(Engine): PASS
5949 23:14:06.263309 TX OE : NO K
5950 23:14:06.263727 All Pass.
5951 23:14:06.264057
5952 23:14:06.264359 CH 0, Rank 1
5953 23:14:06.266679 SW Impedance : PASS
5954 23:14:06.270154 DUTY Scan : NO K
5955 23:14:06.270638 ZQ Calibration : PASS
5956 23:14:06.273657 Jitter Meter : NO K
5957 23:14:06.274071 CBT Training : PASS
5958 23:14:06.276690 Write leveling : PASS
5959 23:14:06.280151 RX DQS gating : PASS
5960 23:14:06.280565 RX DQ/DQS(RDDQC) : PASS
5961 23:14:06.283686 TX DQ/DQS : PASS
5962 23:14:06.286535 RX DATLAT : PASS
5963 23:14:06.286974 RX DQ/DQS(Engine): PASS
5964 23:14:06.289778 TX OE : NO K
5965 23:14:06.290197 All Pass.
5966 23:14:06.290714
5967 23:14:06.293159 CH 1, Rank 0
5968 23:14:06.293566 SW Impedance : PASS
5969 23:14:06.296515 DUTY Scan : NO K
5970 23:14:06.300147 ZQ Calibration : PASS
5971 23:14:06.300579 Jitter Meter : NO K
5972 23:14:06.303645 CBT Training : PASS
5973 23:14:06.306669 Write leveling : PASS
5974 23:14:06.307217 RX DQS gating : PASS
5975 23:14:06.309689 RX DQ/DQS(RDDQC) : PASS
5976 23:14:06.313164 TX DQ/DQS : PASS
5977 23:14:06.313860 RX DATLAT : PASS
5978 23:14:06.316755 RX DQ/DQS(Engine): PASS
5979 23:14:06.319989 TX OE : NO K
5980 23:14:06.320407 All Pass.
5981 23:14:06.320740
5982 23:14:06.321046 CH 1, Rank 1
5983 23:14:06.323143 SW Impedance : PASS
5984 23:14:06.326567 DUTY Scan : NO K
5985 23:14:06.327030 ZQ Calibration : PASS
5986 23:14:06.329745 Jitter Meter : NO K
5987 23:14:06.330178 CBT Training : PASS
5988 23:14:06.333272 Write leveling : PASS
5989 23:14:06.336703 RX DQS gating : PASS
5990 23:14:06.337117 RX DQ/DQS(RDDQC) : PASS
5991 23:14:06.339698 TX DQ/DQS : PASS
5992 23:14:06.343250 RX DATLAT : PASS
5993 23:14:06.343670 RX DQ/DQS(Engine): PASS
5994 23:14:06.346589 TX OE : NO K
5995 23:14:06.347010 All Pass.
5996 23:14:06.347340
5997 23:14:06.349667 DramC Write-DBI off
5998 23:14:06.352950 PER_BANK_REFRESH: Hybrid Mode
5999 23:14:06.353435 TX_TRACKING: ON
6000 23:14:06.362750 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6001 23:14:06.366197 [FAST_K] Save calibration result to emmc
6002 23:14:06.369440 dramc_set_vcore_voltage set vcore to 650000
6003 23:14:06.373117 Read voltage for 400, 6
6004 23:14:06.373620 Vio18 = 0
6005 23:14:06.373960 Vcore = 650000
6006 23:14:06.376358 Vdram = 0
6007 23:14:06.376773 Vddq = 0
6008 23:14:06.377106 Vmddr = 0
6009 23:14:06.382834 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6010 23:14:06.386549 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6011 23:14:06.389394 MEM_TYPE=3, freq_sel=20
6012 23:14:06.392972 sv_algorithm_assistance_LP4_800
6013 23:14:06.396522 ============ PULL DRAM RESETB DOWN ============
6014 23:14:06.399473 ========== PULL DRAM RESETB DOWN end =========
6015 23:14:06.406442 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6016 23:14:06.409354 ===================================
6017 23:14:06.412659 LPDDR4 DRAM CONFIGURATION
6018 23:14:06.416199 ===================================
6019 23:14:06.416620 EX_ROW_EN[0] = 0x0
6020 23:14:06.419005 EX_ROW_EN[1] = 0x0
6021 23:14:06.419426 LP4Y_EN = 0x0
6022 23:14:06.422747 WORK_FSP = 0x0
6023 23:14:06.423166 WL = 0x2
6024 23:14:06.426068 RL = 0x2
6025 23:14:06.426576 BL = 0x2
6026 23:14:06.429347 RPST = 0x0
6027 23:14:06.429835 RD_PRE = 0x0
6028 23:14:06.432393 WR_PRE = 0x1
6029 23:14:06.432853 WR_PST = 0x0
6030 23:14:06.435809 DBI_WR = 0x0
6031 23:14:06.436315 DBI_RD = 0x0
6032 23:14:06.439020 OTF = 0x1
6033 23:14:06.442109 ===================================
6034 23:14:06.445488 ===================================
6035 23:14:06.445959 ANA top config
6036 23:14:06.449390 ===================================
6037 23:14:06.452510 DLL_ASYNC_EN = 0
6038 23:14:06.455839 ALL_SLAVE_EN = 1
6039 23:14:06.458927 NEW_RANK_MODE = 1
6040 23:14:06.462379 DLL_IDLE_MODE = 1
6041 23:14:06.462822 LP45_APHY_COMB_EN = 1
6042 23:14:06.465372 TX_ODT_DIS = 1
6043 23:14:06.468897 NEW_8X_MODE = 1
6044 23:14:06.471997 ===================================
6045 23:14:06.476006 ===================================
6046 23:14:06.479041 data_rate = 800
6047 23:14:06.482141 CKR = 1
6048 23:14:06.482553 DQ_P2S_RATIO = 4
6049 23:14:06.485543 ===================================
6050 23:14:06.489080 CA_P2S_RATIO = 4
6051 23:14:06.492161 DQ_CA_OPEN = 0
6052 23:14:06.495589 DQ_SEMI_OPEN = 1
6053 23:14:06.498994 CA_SEMI_OPEN = 1
6054 23:14:06.499404 CA_FULL_RATE = 0
6055 23:14:06.502506 DQ_CKDIV4_EN = 0
6056 23:14:06.505644 CA_CKDIV4_EN = 1
6057 23:14:06.509212 CA_PREDIV_EN = 0
6058 23:14:06.512247 PH8_DLY = 0
6059 23:14:06.516232 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6060 23:14:06.516640 DQ_AAMCK_DIV = 0
6061 23:14:06.518913 CA_AAMCK_DIV = 0
6062 23:14:06.522505 CA_ADMCK_DIV = 4
6063 23:14:06.525290 DQ_TRACK_CA_EN = 0
6064 23:14:06.529108 CA_PICK = 800
6065 23:14:06.531973 CA_MCKIO = 400
6066 23:14:06.536058 MCKIO_SEMI = 400
6067 23:14:06.536478 PLL_FREQ = 3016
6068 23:14:06.539225 DQ_UI_PI_RATIO = 32
6069 23:14:06.542119 CA_UI_PI_RATIO = 32
6070 23:14:06.545304 ===================================
6071 23:14:06.549128 ===================================
6072 23:14:06.551814 memory_type:LPDDR4
6073 23:14:06.555642 GP_NUM : 10
6074 23:14:06.556059 SRAM_EN : 1
6075 23:14:06.558980 MD32_EN : 0
6076 23:14:06.562060 ===================================
6077 23:14:06.562550 [ANA_INIT] >>>>>>>>>>>>>>
6078 23:14:06.565476 <<<<<< [CONFIGURE PHASE]: ANA_TX
6079 23:14:06.568413 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6080 23:14:06.571934 ===================================
6081 23:14:06.575616 data_rate = 800,PCW = 0X7400
6082 23:14:06.578397 ===================================
6083 23:14:06.581991 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6084 23:14:06.588801 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6085 23:14:06.598749 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6086 23:14:06.605114 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6087 23:14:06.608747 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6088 23:14:06.612319 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6089 23:14:06.612833 [ANA_INIT] flow start
6090 23:14:06.615363 [ANA_INIT] PLL >>>>>>>>
6091 23:14:06.619291 [ANA_INIT] PLL <<<<<<<<
6092 23:14:06.619816 [ANA_INIT] MIDPI >>>>>>>>
6093 23:14:06.622026 [ANA_INIT] MIDPI <<<<<<<<
6094 23:14:06.625273 [ANA_INIT] DLL >>>>>>>>
6095 23:14:06.625783 [ANA_INIT] flow end
6096 23:14:06.631817 ============ LP4 DIFF to SE enter ============
6097 23:14:06.635320 ============ LP4 DIFF to SE exit ============
6098 23:14:06.638815 [ANA_INIT] <<<<<<<<<<<<<
6099 23:14:06.641879 [Flow] Enable top DCM control >>>>>
6100 23:14:06.645153 [Flow] Enable top DCM control <<<<<
6101 23:14:06.645572 Enable DLL master slave shuffle
6102 23:14:06.652024 ==============================================================
6103 23:14:06.655467 Gating Mode config
6104 23:14:06.658361 ==============================================================
6105 23:14:06.661723 Config description:
6106 23:14:06.671583 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6107 23:14:06.678440 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6108 23:14:06.681567 SELPH_MODE 0: By rank 1: By Phase
6109 23:14:06.688376 ==============================================================
6110 23:14:06.691415 GAT_TRACK_EN = 0
6111 23:14:06.695348 RX_GATING_MODE = 2
6112 23:14:06.698245 RX_GATING_TRACK_MODE = 2
6113 23:14:06.701493 SELPH_MODE = 1
6114 23:14:06.701950 PICG_EARLY_EN = 1
6115 23:14:06.705047 VALID_LAT_VALUE = 1
6116 23:14:06.711668 ==============================================================
6117 23:14:06.715069 Enter into Gating configuration >>>>
6118 23:14:06.718697 Exit from Gating configuration <<<<
6119 23:14:06.721501 Enter into DVFS_PRE_config >>>>>
6120 23:14:06.731591 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6121 23:14:06.734973 Exit from DVFS_PRE_config <<<<<
6122 23:14:06.737903 Enter into PICG configuration >>>>
6123 23:14:06.741478 Exit from PICG configuration <<<<
6124 23:14:06.744733 [RX_INPUT] configuration >>>>>
6125 23:14:06.747958 [RX_INPUT] configuration <<<<<
6126 23:14:06.751485 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6127 23:14:06.757945 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6128 23:14:06.764865 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6129 23:14:06.771211 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6130 23:14:06.778710 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6131 23:14:06.781242 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6132 23:14:06.788312 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6133 23:14:06.791464 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6134 23:14:06.794902 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6135 23:14:06.797847 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6136 23:14:06.804663 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6137 23:14:06.807822 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6138 23:14:06.811309 ===================================
6139 23:14:06.814487 LPDDR4 DRAM CONFIGURATION
6140 23:14:06.817653 ===================================
6141 23:14:06.818077 EX_ROW_EN[0] = 0x0
6142 23:14:06.820972 EX_ROW_EN[1] = 0x0
6143 23:14:06.821391 LP4Y_EN = 0x0
6144 23:14:06.824422 WORK_FSP = 0x0
6145 23:14:06.824838 WL = 0x2
6146 23:14:06.827852 RL = 0x2
6147 23:14:06.828267 BL = 0x2
6148 23:14:06.831433 RPST = 0x0
6149 23:14:06.831850 RD_PRE = 0x0
6150 23:14:06.834456 WR_PRE = 0x1
6151 23:14:06.834873 WR_PST = 0x0
6152 23:14:06.837494 DBI_WR = 0x0
6153 23:14:06.840984 DBI_RD = 0x0
6154 23:14:06.841398 OTF = 0x1
6155 23:14:06.844224 ===================================
6156 23:14:06.847944 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6157 23:14:06.850804 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6158 23:14:06.857560 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6159 23:14:06.861024 ===================================
6160 23:14:06.861532 LPDDR4 DRAM CONFIGURATION
6161 23:14:06.864593 ===================================
6162 23:14:06.867581 EX_ROW_EN[0] = 0x10
6163 23:14:06.871193 EX_ROW_EN[1] = 0x0
6164 23:14:06.871672 LP4Y_EN = 0x0
6165 23:14:06.874087 WORK_FSP = 0x0
6166 23:14:06.874502 WL = 0x2
6167 23:14:06.877691 RL = 0x2
6168 23:14:06.878106 BL = 0x2
6169 23:14:06.881089 RPST = 0x0
6170 23:14:06.881548 RD_PRE = 0x0
6171 23:14:06.883965 WR_PRE = 0x1
6172 23:14:06.884429 WR_PST = 0x0
6173 23:14:06.887784 DBI_WR = 0x0
6174 23:14:06.888240 DBI_RD = 0x0
6175 23:14:06.890938 OTF = 0x1
6176 23:14:06.894534 ===================================
6177 23:14:06.900433 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6178 23:14:06.904105 nWR fixed to 30
6179 23:14:06.907821 [ModeRegInit_LP4] CH0 RK0
6180 23:14:06.908418 [ModeRegInit_LP4] CH0 RK1
6181 23:14:06.910514 [ModeRegInit_LP4] CH1 RK0
6182 23:14:06.913920 [ModeRegInit_LP4] CH1 RK1
6183 23:14:06.914338 match AC timing 19
6184 23:14:06.920483 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6185 23:14:06.924068 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6186 23:14:06.927353 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6187 23:14:06.933837 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6188 23:14:06.937408 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6189 23:14:06.937879 ==
6190 23:14:06.940715 Dram Type= 6, Freq= 0, CH_0, rank 0
6191 23:14:06.943982 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6192 23:14:06.944405 ==
6193 23:14:06.950959 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6194 23:14:06.957164 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6195 23:14:06.960721 [CA 0] Center 36 (8~64) winsize 57
6196 23:14:06.963700 [CA 1] Center 36 (8~64) winsize 57
6197 23:14:06.967113 [CA 2] Center 36 (8~64) winsize 57
6198 23:14:06.970667 [CA 3] Center 36 (8~64) winsize 57
6199 23:14:06.971174 [CA 4] Center 36 (8~64) winsize 57
6200 23:14:06.973784 [CA 5] Center 36 (8~64) winsize 57
6201 23:14:06.974203
6202 23:14:06.980168 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6203 23:14:06.980678
6204 23:14:06.984061 [CATrainingPosCal] consider 1 rank data
6205 23:14:06.986870 u2DelayCellTimex100 = 270/100 ps
6206 23:14:06.990239 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6207 23:14:06.993700 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6208 23:14:06.997251 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6209 23:14:07.000492 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6210 23:14:07.003964 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6211 23:14:07.007172 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6212 23:14:07.007587
6213 23:14:07.010704 CA PerBit enable=1, Macro0, CA PI delay=36
6214 23:14:07.011127
6215 23:14:07.013608 [CBTSetCACLKResult] CA Dly = 36
6216 23:14:07.017074 CS Dly: 1 (0~32)
6217 23:14:07.017487 ==
6218 23:14:07.020219 Dram Type= 6, Freq= 0, CH_0, rank 1
6219 23:14:07.023611 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6220 23:14:07.024031 ==
6221 23:14:07.030162 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6222 23:14:07.033974 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6223 23:14:07.037273 [CA 0] Center 36 (8~64) winsize 57
6224 23:14:07.040242 [CA 1] Center 36 (8~64) winsize 57
6225 23:14:07.043479 [CA 2] Center 36 (8~64) winsize 57
6226 23:14:07.047074 [CA 3] Center 36 (8~64) winsize 57
6227 23:14:07.050237 [CA 4] Center 36 (8~64) winsize 57
6228 23:14:07.053483 [CA 5] Center 36 (8~64) winsize 57
6229 23:14:07.053985
6230 23:14:07.056994 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6231 23:14:07.057411
6232 23:14:07.060398 [CATrainingPosCal] consider 2 rank data
6233 23:14:07.063643 u2DelayCellTimex100 = 270/100 ps
6234 23:14:07.067201 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6235 23:14:07.070208 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6236 23:14:07.073993 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6237 23:14:07.080344 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6238 23:14:07.083783 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6239 23:14:07.086744 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6240 23:14:07.087162
6241 23:14:07.090185 CA PerBit enable=1, Macro0, CA PI delay=36
6242 23:14:07.090601
6243 23:14:07.093353 [CBTSetCACLKResult] CA Dly = 36
6244 23:14:07.093806 CS Dly: 1 (0~32)
6245 23:14:07.094142
6246 23:14:07.096898 ----->DramcWriteLeveling(PI) begin...
6247 23:14:07.097322 ==
6248 23:14:07.100494 Dram Type= 6, Freq= 0, CH_0, rank 0
6249 23:14:07.106824 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6250 23:14:07.107244 ==
6251 23:14:07.110028 Write leveling (Byte 0): 40 => 8
6252 23:14:07.113409 Write leveling (Byte 1): 40 => 8
6253 23:14:07.113926 DramcWriteLeveling(PI) end<-----
6254 23:14:07.114261
6255 23:14:07.116604 ==
6256 23:14:07.120124 Dram Type= 6, Freq= 0, CH_0, rank 0
6257 23:14:07.123915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6258 23:14:07.124432 ==
6259 23:14:07.126638 [Gating] SW mode calibration
6260 23:14:07.132932 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6261 23:14:07.136564 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6262 23:14:07.143358 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6263 23:14:07.146487 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6264 23:14:07.149883 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6265 23:14:07.156632 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6266 23:14:07.160074 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6267 23:14:07.162854 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6268 23:14:07.169934 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6269 23:14:07.172944 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6270 23:14:07.176483 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6271 23:14:07.179651 Total UI for P1: 0, mck2ui 16
6272 23:14:07.182997 best dqsien dly found for B0: ( 0, 14, 24)
6273 23:14:07.186335 Total UI for P1: 0, mck2ui 16
6274 23:14:07.190069 best dqsien dly found for B1: ( 0, 14, 24)
6275 23:14:07.193248 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6276 23:14:07.196557 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6277 23:14:07.196974
6278 23:14:07.203073 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6279 23:14:07.206573 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6280 23:14:07.206993 [Gating] SW calibration Done
6281 23:14:07.209412 ==
6282 23:14:07.213031 Dram Type= 6, Freq= 0, CH_0, rank 0
6283 23:14:07.216108 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6284 23:14:07.216524 ==
6285 23:14:07.216860 RX Vref Scan: 0
6286 23:14:07.217169
6287 23:14:07.219669 RX Vref 0 -> 0, step: 1
6288 23:14:07.220083
6289 23:14:07.223123 RX Delay -410 -> 252, step: 16
6290 23:14:07.226439 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6291 23:14:07.232899 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6292 23:14:07.236320 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6293 23:14:07.239413 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6294 23:14:07.243116 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6295 23:14:07.249305 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6296 23:14:07.252754 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6297 23:14:07.255869 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6298 23:14:07.259219 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6299 23:14:07.265630 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6300 23:14:07.269092 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6301 23:14:07.272701 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6302 23:14:07.275774 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6303 23:14:07.282603 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6304 23:14:07.285805 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6305 23:14:07.288734 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6306 23:14:07.289227 ==
6307 23:14:07.292191 Dram Type= 6, Freq= 0, CH_0, rank 0
6308 23:14:07.295633 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6309 23:14:07.298640 ==
6310 23:14:07.299051 DQS Delay:
6311 23:14:07.299383 DQS0 = 27, DQS1 = 35
6312 23:14:07.302060 DQM Delay:
6313 23:14:07.302474 DQM0 = 10, DQM1 = 11
6314 23:14:07.305396 DQ Delay:
6315 23:14:07.305850 DQ0 =8, DQ1 =16, DQ2 =0, DQ3 =8
6316 23:14:07.308786 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =24
6317 23:14:07.311995 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6318 23:14:07.315444 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6319 23:14:07.315860
6320 23:14:07.316185
6321 23:14:07.318929 ==
6322 23:14:07.319341 Dram Type= 6, Freq= 0, CH_0, rank 0
6323 23:14:07.325610 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6324 23:14:07.326093 ==
6325 23:14:07.326429
6326 23:14:07.326736
6327 23:14:07.328741 TX Vref Scan disable
6328 23:14:07.329150 == TX Byte 0 ==
6329 23:14:07.332045 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6330 23:14:07.338424 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6331 23:14:07.338914 == TX Byte 1 ==
6332 23:14:07.341941 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6333 23:14:07.348450 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6334 23:14:07.348931 ==
6335 23:14:07.351799 Dram Type= 6, Freq= 0, CH_0, rank 0
6336 23:14:07.355358 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6337 23:14:07.355857 ==
6338 23:14:07.356240
6339 23:14:07.356584
6340 23:14:07.358195 TX Vref Scan disable
6341 23:14:07.358623 == TX Byte 0 ==
6342 23:14:07.361662 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6343 23:14:07.368169 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6344 23:14:07.368655 == TX Byte 1 ==
6345 23:14:07.371670 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6346 23:14:07.378297 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6347 23:14:07.378714
6348 23:14:07.379039 [DATLAT]
6349 23:14:07.379347 Freq=400, CH0 RK0
6350 23:14:07.379648
6351 23:14:07.381723 DATLAT Default: 0xf
6352 23:14:07.384708 0, 0xFFFF, sum = 0
6353 23:14:07.385129 1, 0xFFFF, sum = 0
6354 23:14:07.388132 2, 0xFFFF, sum = 0
6355 23:14:07.388622 3, 0xFFFF, sum = 0
6356 23:14:07.391736 4, 0xFFFF, sum = 0
6357 23:14:07.392233 5, 0xFFFF, sum = 0
6358 23:14:07.394598 6, 0xFFFF, sum = 0
6359 23:14:07.395019 7, 0xFFFF, sum = 0
6360 23:14:07.398214 8, 0xFFFF, sum = 0
6361 23:14:07.398633 9, 0xFFFF, sum = 0
6362 23:14:07.401033 10, 0xFFFF, sum = 0
6363 23:14:07.401457 11, 0xFFFF, sum = 0
6364 23:14:07.404674 12, 0xFFFF, sum = 0
6365 23:14:07.405183 13, 0x0, sum = 1
6366 23:14:07.407891 14, 0x0, sum = 2
6367 23:14:07.408310 15, 0x0, sum = 3
6368 23:14:07.411146 16, 0x0, sum = 4
6369 23:14:07.411569 best_step = 14
6370 23:14:07.411897
6371 23:14:07.412201 ==
6372 23:14:07.414947 Dram Type= 6, Freq= 0, CH_0, rank 0
6373 23:14:07.421425 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6374 23:14:07.421999 ==
6375 23:14:07.422340 RX Vref Scan: 1
6376 23:14:07.422652
6377 23:14:07.424328 RX Vref 0 -> 0, step: 1
6378 23:14:07.424743
6379 23:14:07.427560 RX Delay -311 -> 252, step: 8
6380 23:14:07.427972
6381 23:14:07.430875 Set Vref, RX VrefLevel [Byte0]: 56
6382 23:14:07.434132 [Byte1]: 54
6383 23:14:07.434697
6384 23:14:07.438093 Final RX Vref Byte 0 = 56 to rank0
6385 23:14:07.441172 Final RX Vref Byte 1 = 54 to rank0
6386 23:14:07.444594 Final RX Vref Byte 0 = 56 to rank1
6387 23:14:07.447802 Final RX Vref Byte 1 = 54 to rank1==
6388 23:14:07.451139 Dram Type= 6, Freq= 0, CH_0, rank 0
6389 23:14:07.454745 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6390 23:14:07.455163 ==
6391 23:14:07.457643 DQS Delay:
6392 23:14:07.458057 DQS0 = 28, DQS1 = 36
6393 23:14:07.461238 DQM Delay:
6394 23:14:07.461869 DQM0 = 11, DQM1 = 13
6395 23:14:07.464317 DQ Delay:
6396 23:14:07.464824 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6397 23:14:07.467586 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6398 23:14:07.471040 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =4
6399 23:14:07.474486 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6400 23:14:07.474901
6401 23:14:07.475227
6402 23:14:07.484113 [DQSOSCAuto] RK0, (LSB)MR18= 0xcab7, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 384 ps
6403 23:14:07.487388 CH0 RK0: MR19=C0C, MR18=CAB7
6404 23:14:07.491013 CH0_RK0: MR19=0xC0C, MR18=0xCAB7, DQSOSC=384, MR23=63, INC=400, DEC=267
6405 23:14:07.493884 ==
6406 23:14:07.497566 Dram Type= 6, Freq= 0, CH_0, rank 1
6407 23:14:07.501135 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6408 23:14:07.501694 ==
6409 23:14:07.504411 [Gating] SW mode calibration
6410 23:14:07.510553 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6411 23:14:07.514357 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6412 23:14:07.521290 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6413 23:14:07.524166 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6414 23:14:07.527314 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6415 23:14:07.533999 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6416 23:14:07.537410 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6417 23:14:07.540947 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6418 23:14:07.547631 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6419 23:14:07.550723 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6420 23:14:07.554084 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6421 23:14:07.557400 Total UI for P1: 0, mck2ui 16
6422 23:14:07.560765 best dqsien dly found for B0: ( 0, 14, 24)
6423 23:14:07.564253 Total UI for P1: 0, mck2ui 16
6424 23:14:07.567067 best dqsien dly found for B1: ( 0, 14, 24)
6425 23:14:07.570454 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6426 23:14:07.574175 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6427 23:14:07.574700
6428 23:14:07.580641 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6429 23:14:07.583838 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6430 23:14:07.584324 [Gating] SW calibration Done
6431 23:14:07.587220 ==
6432 23:14:07.590638 Dram Type= 6, Freq= 0, CH_0, rank 1
6433 23:14:07.593875 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6434 23:14:07.594309 ==
6435 23:14:07.594647 RX Vref Scan: 0
6436 23:14:07.594958
6437 23:14:07.597178 RX Vref 0 -> 0, step: 1
6438 23:14:07.597633
6439 23:14:07.600661 RX Delay -410 -> 252, step: 16
6440 23:14:07.604001 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6441 23:14:07.607160 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6442 23:14:07.613757 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6443 23:14:07.617332 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6444 23:14:07.620257 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6445 23:14:07.623685 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6446 23:14:07.630493 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6447 23:14:07.633772 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6448 23:14:07.636773 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6449 23:14:07.640229 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6450 23:14:07.646957 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6451 23:14:07.650115 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6452 23:14:07.653442 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6453 23:14:07.659847 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6454 23:14:07.662988 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6455 23:14:07.666581 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6456 23:14:07.667001 ==
6457 23:14:07.670032 Dram Type= 6, Freq= 0, CH_0, rank 1
6458 23:14:07.673254 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6459 23:14:07.676600 ==
6460 23:14:07.677118 DQS Delay:
6461 23:14:07.677463 DQS0 = 27, DQS1 = 35
6462 23:14:07.680096 DQM Delay:
6463 23:14:07.680527 DQM0 = 12, DQM1 = 10
6464 23:14:07.683391 DQ Delay:
6465 23:14:07.683804 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6466 23:14:07.686962 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6467 23:14:07.690101 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6468 23:14:07.693065 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6469 23:14:07.693480
6470 23:14:07.693898
6471 23:14:07.694217 ==
6472 23:14:07.696509 Dram Type= 6, Freq= 0, CH_0, rank 1
6473 23:14:07.703246 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6474 23:14:07.703763 ==
6475 23:14:07.704102
6476 23:14:07.704408
6477 23:14:07.704699 TX Vref Scan disable
6478 23:14:07.706487 == TX Byte 0 ==
6479 23:14:07.709714 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6480 23:14:07.713407 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6481 23:14:07.716898 == TX Byte 1 ==
6482 23:14:07.719905 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6483 23:14:07.723333 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6484 23:14:07.723748 ==
6485 23:14:07.726257 Dram Type= 6, Freq= 0, CH_0, rank 1
6486 23:14:07.732900 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6487 23:14:07.733319 ==
6488 23:14:07.733706
6489 23:14:07.734030
6490 23:14:07.734326 TX Vref Scan disable
6491 23:14:07.736330 == TX Byte 0 ==
6492 23:14:07.739881 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6493 23:14:07.742938 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6494 23:14:07.746455 == TX Byte 1 ==
6495 23:14:07.749435 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6496 23:14:07.752902 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6497 23:14:07.753319
6498 23:14:07.756408 [DATLAT]
6499 23:14:07.756827 Freq=400, CH0 RK1
6500 23:14:07.757164
6501 23:14:07.759726 DATLAT Default: 0xe
6502 23:14:07.760262 0, 0xFFFF, sum = 0
6503 23:14:07.763014 1, 0xFFFF, sum = 0
6504 23:14:07.763438 2, 0xFFFF, sum = 0
6505 23:14:07.765885 3, 0xFFFF, sum = 0
6506 23:14:07.766310 4, 0xFFFF, sum = 0
6507 23:14:07.769338 5, 0xFFFF, sum = 0
6508 23:14:07.772603 6, 0xFFFF, sum = 0
6509 23:14:07.773224 7, 0xFFFF, sum = 0
6510 23:14:07.775956 8, 0xFFFF, sum = 0
6511 23:14:07.776407 9, 0xFFFF, sum = 0
6512 23:14:07.779145 10, 0xFFFF, sum = 0
6513 23:14:07.779574 11, 0xFFFF, sum = 0
6514 23:14:07.782470 12, 0xFFFF, sum = 0
6515 23:14:07.782897 13, 0x0, sum = 1
6516 23:14:07.785715 14, 0x0, sum = 2
6517 23:14:07.786223 15, 0x0, sum = 3
6518 23:14:07.789387 16, 0x0, sum = 4
6519 23:14:07.789820 best_step = 14
6520 23:14:07.790059
6521 23:14:07.790280 ==
6522 23:14:07.792664 Dram Type= 6, Freq= 0, CH_0, rank 1
6523 23:14:07.795886 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6524 23:14:07.796181 ==
6525 23:14:07.798920 RX Vref Scan: 0
6526 23:14:07.799212
6527 23:14:07.802350 RX Vref 0 -> 0, step: 1
6528 23:14:07.802642
6529 23:14:07.802974 RX Delay -311 -> 252, step: 8
6530 23:14:07.811035 iDelay=217, Bit 0, Center -20 (-247 ~ 208) 456
6531 23:14:07.814158 iDelay=217, Bit 1, Center -12 (-231 ~ 208) 440
6532 23:14:07.817700 iDelay=217, Bit 2, Center -20 (-247 ~ 208) 456
6533 23:14:07.820920 iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448
6534 23:14:07.827383 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6535 23:14:07.831227 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6536 23:14:07.834207 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6537 23:14:07.837814 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6538 23:14:07.844006 iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448
6539 23:14:07.847667 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6540 23:14:07.850960 iDelay=217, Bit 10, Center -20 (-239 ~ 200) 440
6541 23:14:07.858054 iDelay=217, Bit 11, Center -28 (-247 ~ 192) 440
6542 23:14:07.860926 iDelay=217, Bit 12, Center -20 (-239 ~ 200) 440
6543 23:14:07.864648 iDelay=217, Bit 13, Center -20 (-239 ~ 200) 440
6544 23:14:07.867619 iDelay=217, Bit 14, Center -12 (-231 ~ 208) 440
6545 23:14:07.874080 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6546 23:14:07.874602 ==
6547 23:14:07.877784 Dram Type= 6, Freq= 0, CH_0, rank 1
6548 23:14:07.881358 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6549 23:14:07.882022 ==
6550 23:14:07.882405 DQS Delay:
6551 23:14:07.884273 DQS0 = 24, DQS1 = 32
6552 23:14:07.884731 DQM Delay:
6553 23:14:07.887282 DQM0 = 8, DQM1 = 9
6554 23:14:07.887741 DQ Delay:
6555 23:14:07.890982 DQ0 =4, DQ1 =12, DQ2 =4, DQ3 =8
6556 23:14:07.893846 DQ4 =8, DQ5 =0, DQ6 =12, DQ7 =16
6557 23:14:07.897351 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6558 23:14:07.900683 DQ12 =12, DQ13 =12, DQ14 =20, DQ15 =16
6559 23:14:07.901129
6560 23:14:07.901461
6561 23:14:07.907517 [DQSOSCAuto] RK1, (LSB)MR18= 0xb657, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 387 ps
6562 23:14:07.911100 CH0 RK1: MR19=C0C, MR18=B657
6563 23:14:07.917286 CH0_RK1: MR19=0xC0C, MR18=0xB657, DQSOSC=387, MR23=63, INC=394, DEC=262
6564 23:14:07.920661 [RxdqsGatingPostProcess] freq 400
6565 23:14:07.927255 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6566 23:14:07.927675 best DQS0 dly(2T, 0.5T) = (0, 10)
6567 23:14:07.930847 best DQS1 dly(2T, 0.5T) = (0, 10)
6568 23:14:07.933706 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6569 23:14:07.937439 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6570 23:14:07.940875 best DQS0 dly(2T, 0.5T) = (0, 10)
6571 23:14:07.944359 best DQS1 dly(2T, 0.5T) = (0, 10)
6572 23:14:07.947161 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6573 23:14:07.950744 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6574 23:14:07.954242 Pre-setting of DQS Precalculation
6575 23:14:07.957118 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6576 23:14:07.960726 ==
6577 23:14:07.961206 Dram Type= 6, Freq= 0, CH_1, rank 0
6578 23:14:07.967223 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6579 23:14:07.967708 ==
6580 23:14:07.970874 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6581 23:14:07.977076 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6582 23:14:07.980725 [CA 0] Center 36 (8~64) winsize 57
6583 23:14:07.984332 [CA 1] Center 36 (8~64) winsize 57
6584 23:14:07.986978 [CA 2] Center 36 (8~64) winsize 57
6585 23:14:07.990524 [CA 3] Center 36 (8~64) winsize 57
6586 23:14:07.993960 [CA 4] Center 36 (8~64) winsize 57
6587 23:14:07.997401 [CA 5] Center 36 (8~64) winsize 57
6588 23:14:07.997896
6589 23:14:08.000345 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6590 23:14:08.000758
6591 23:14:08.003759 [CATrainingPosCal] consider 1 rank data
6592 23:14:08.007130 u2DelayCellTimex100 = 270/100 ps
6593 23:14:08.010621 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6594 23:14:08.013674 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6595 23:14:08.017040 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6596 23:14:08.020445 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6597 23:14:08.026762 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6598 23:14:08.030399 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6599 23:14:08.030818
6600 23:14:08.033737 CA PerBit enable=1, Macro0, CA PI delay=36
6601 23:14:08.034158
6602 23:14:08.036958 [CBTSetCACLKResult] CA Dly = 36
6603 23:14:08.037377 CS Dly: 1 (0~32)
6604 23:14:08.037759 ==
6605 23:14:08.040410 Dram Type= 6, Freq= 0, CH_1, rank 1
6606 23:14:08.043579 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6607 23:14:08.046958 ==
6608 23:14:08.050269 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6609 23:14:08.057014 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6610 23:14:08.059901 [CA 0] Center 36 (8~64) winsize 57
6611 23:14:08.063315 [CA 1] Center 36 (8~64) winsize 57
6612 23:14:08.066875 [CA 2] Center 36 (8~64) winsize 57
6613 23:14:08.070236 [CA 3] Center 36 (8~64) winsize 57
6614 23:14:08.073702 [CA 4] Center 36 (8~64) winsize 57
6615 23:14:08.076990 [CA 5] Center 36 (8~64) winsize 57
6616 23:14:08.077449
6617 23:14:08.080046 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6618 23:14:08.080500
6619 23:14:08.083516 [CATrainingPosCal] consider 2 rank data
6620 23:14:08.086544 u2DelayCellTimex100 = 270/100 ps
6621 23:14:08.090108 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6622 23:14:08.093123 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6623 23:14:08.096573 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6624 23:14:08.099719 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6625 23:14:08.103089 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6626 23:14:08.106492 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6627 23:14:08.106904
6628 23:14:08.110053 CA PerBit enable=1, Macro0, CA PI delay=36
6629 23:14:08.113530
6630 23:14:08.113991 [CBTSetCACLKResult] CA Dly = 36
6631 23:14:08.116503 CS Dly: 1 (0~32)
6632 23:14:08.116911
6633 23:14:08.119798 ----->DramcWriteLeveling(PI) begin...
6634 23:14:08.120242 ==
6635 23:14:08.123123 Dram Type= 6, Freq= 0, CH_1, rank 0
6636 23:14:08.126580 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6637 23:14:08.127015 ==
6638 23:14:08.130144 Write leveling (Byte 0): 40 => 8
6639 23:14:08.133380 Write leveling (Byte 1): 40 => 8
6640 23:14:08.136497 DramcWriteLeveling(PI) end<-----
6641 23:14:08.136913
6642 23:14:08.137240 ==
6643 23:14:08.139765 Dram Type= 6, Freq= 0, CH_1, rank 0
6644 23:14:08.143325 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6645 23:14:08.143778 ==
6646 23:14:08.146564 [Gating] SW mode calibration
6647 23:14:08.153222 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6648 23:14:08.159659 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6649 23:14:08.163410 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6650 23:14:08.169817 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6651 23:14:08.173761 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6652 23:14:08.176676 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6653 23:14:08.183392 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6654 23:14:08.186181 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6655 23:14:08.189768 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6656 23:14:08.196182 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6657 23:14:08.199646 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6658 23:14:08.203005 Total UI for P1: 0, mck2ui 16
6659 23:14:08.206258 best dqsien dly found for B0: ( 0, 14, 24)
6660 23:14:08.209751 Total UI for P1: 0, mck2ui 16
6661 23:14:08.212792 best dqsien dly found for B1: ( 0, 14, 24)
6662 23:14:08.216099 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6663 23:14:08.219636 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6664 23:14:08.220084
6665 23:14:08.223074 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6666 23:14:08.226257 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6667 23:14:08.229555 [Gating] SW calibration Done
6668 23:14:08.230039 ==
6669 23:14:08.232653 Dram Type= 6, Freq= 0, CH_1, rank 0
6670 23:14:08.236061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6671 23:14:08.236495 ==
6672 23:14:08.239570 RX Vref Scan: 0
6673 23:14:08.240001
6674 23:14:08.243014 RX Vref 0 -> 0, step: 1
6675 23:14:08.243447
6676 23:14:08.243886 RX Delay -410 -> 252, step: 16
6677 23:14:08.249661 iDelay=230, Bit 0, Center -3 (-234 ~ 229) 464
6678 23:14:08.252933 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6679 23:14:08.256177 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6680 23:14:08.259568 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6681 23:14:08.266215 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6682 23:14:08.269679 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6683 23:14:08.273260 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6684 23:14:08.276669 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6685 23:14:08.282960 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6686 23:14:08.286149 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6687 23:14:08.289885 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6688 23:14:08.293222 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6689 23:14:08.299760 iDelay=230, Bit 12, Center -3 (-234 ~ 229) 464
6690 23:14:08.302785 iDelay=230, Bit 13, Center -11 (-234 ~ 213) 448
6691 23:14:08.306256 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6692 23:14:08.309870 iDelay=230, Bit 15, Center -3 (-234 ~ 229) 464
6693 23:14:08.312783 ==
6694 23:14:08.313199 Dram Type= 6, Freq= 0, CH_1, rank 0
6695 23:14:08.319409 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6696 23:14:08.319899 ==
6697 23:14:08.320239 DQS Delay:
6698 23:14:08.323171 DQS0 = 27, DQS1 = 35
6699 23:14:08.323725 DQM Delay:
6700 23:14:08.325951 DQM0 = 12, DQM1 = 17
6701 23:14:08.326374 DQ Delay:
6702 23:14:08.329430 DQ0 =24, DQ1 =0, DQ2 =0, DQ3 =8
6703 23:14:08.333125 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6704 23:14:08.333681 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6705 23:14:08.339379 DQ12 =32, DQ13 =24, DQ14 =24, DQ15 =32
6706 23:14:08.339834
6707 23:14:08.340171
6708 23:14:08.340481 ==
6709 23:14:08.342691 Dram Type= 6, Freq= 0, CH_1, rank 0
6710 23:14:08.345851 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6711 23:14:08.346278 ==
6712 23:14:08.346613
6713 23:14:08.346926
6714 23:14:08.349386 TX Vref Scan disable
6715 23:14:08.349930 == TX Byte 0 ==
6716 23:14:08.355958 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6717 23:14:08.359011 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6718 23:14:08.359433 == TX Byte 1 ==
6719 23:14:08.362977 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6720 23:14:08.369057 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6721 23:14:08.369478 ==
6722 23:14:08.372923 Dram Type= 6, Freq= 0, CH_1, rank 0
6723 23:14:08.376104 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6724 23:14:08.376598 ==
6725 23:14:08.376936
6726 23:14:08.377249
6727 23:14:08.378976 TX Vref Scan disable
6728 23:14:08.379415 == TX Byte 0 ==
6729 23:14:08.385936 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6730 23:14:08.388985 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6731 23:14:08.389405 == TX Byte 1 ==
6732 23:14:08.395864 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6733 23:14:08.399338 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6734 23:14:08.399763
6735 23:14:08.400102 [DATLAT]
6736 23:14:08.402462 Freq=400, CH1 RK0
6737 23:14:08.402884
6738 23:14:08.403218 DATLAT Default: 0xf
6739 23:14:08.405886 0, 0xFFFF, sum = 0
6740 23:14:08.406316 1, 0xFFFF, sum = 0
6741 23:14:08.408968 2, 0xFFFF, sum = 0
6742 23:14:08.409394 3, 0xFFFF, sum = 0
6743 23:14:08.412430 4, 0xFFFF, sum = 0
6744 23:14:08.412852 5, 0xFFFF, sum = 0
6745 23:14:08.415581 6, 0xFFFF, sum = 0
6746 23:14:08.416008 7, 0xFFFF, sum = 0
6747 23:14:08.418932 8, 0xFFFF, sum = 0
6748 23:14:08.419359 9, 0xFFFF, sum = 0
6749 23:14:08.422313 10, 0xFFFF, sum = 0
6750 23:14:08.422744 11, 0xFFFF, sum = 0
6751 23:14:08.425844 12, 0xFFFF, sum = 0
6752 23:14:08.428891 13, 0x0, sum = 1
6753 23:14:08.429323 14, 0x0, sum = 2
6754 23:14:08.429731 15, 0x0, sum = 3
6755 23:14:08.432629 16, 0x0, sum = 4
6756 23:14:08.433159 best_step = 14
6757 23:14:08.433501
6758 23:14:08.433882 ==
6759 23:14:08.435267 Dram Type= 6, Freq= 0, CH_1, rank 0
6760 23:14:08.442683 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6761 23:14:08.443218 ==
6762 23:14:08.443670 RX Vref Scan: 1
6763 23:14:08.444085
6764 23:14:08.445318 RX Vref 0 -> 0, step: 1
6765 23:14:08.445947
6766 23:14:08.448817 RX Delay -311 -> 252, step: 8
6767 23:14:08.449283
6768 23:14:08.452487 Set Vref, RX VrefLevel [Byte0]: 54
6769 23:14:08.455650 [Byte1]: 46
6770 23:14:08.456080
6771 23:14:08.458943 Final RX Vref Byte 0 = 54 to rank0
6772 23:14:08.462177 Final RX Vref Byte 1 = 46 to rank0
6773 23:14:08.465883 Final RX Vref Byte 0 = 54 to rank1
6774 23:14:08.468729 Final RX Vref Byte 1 = 46 to rank1==
6775 23:14:08.472291 Dram Type= 6, Freq= 0, CH_1, rank 0
6776 23:14:08.475337 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6777 23:14:08.478875 ==
6778 23:14:08.479378 DQS Delay:
6779 23:14:08.479760 DQS0 = 28, DQS1 = 32
6780 23:14:08.482217 DQM Delay:
6781 23:14:08.482629 DQM0 = 10, DQM1 = 12
6782 23:14:08.485018 DQ Delay:
6783 23:14:08.488456 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =12
6784 23:14:08.488902 DQ4 =8, DQ5 =20, DQ6 =16, DQ7 =8
6785 23:14:08.491839 DQ8 =0, DQ9 =4, DQ10 =12, DQ11 =4
6786 23:14:08.495320 DQ12 =20, DQ13 =20, DQ14 =16, DQ15 =20
6787 23:14:08.495731
6788 23:14:08.496055
6789 23:14:08.504855 [DQSOSCAuto] RK0, (LSB)MR18= 0x8cc5, (MSB)MR19= 0xc0c, tDQSOscB0 = 385 ps tDQSOscB1 = 392 ps
6790 23:14:08.508503 CH1 RK0: MR19=C0C, MR18=8CC5
6791 23:14:08.515225 CH1_RK0: MR19=0xC0C, MR18=0x8CC5, DQSOSC=385, MR23=63, INC=398, DEC=265
6792 23:14:08.515721 ==
6793 23:14:08.518565 Dram Type= 6, Freq= 0, CH_1, rank 1
6794 23:14:08.521663 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6795 23:14:08.522107 ==
6796 23:14:08.525144 [Gating] SW mode calibration
6797 23:14:08.531800 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6798 23:14:08.538108 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6799 23:14:08.541284 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6800 23:14:08.544806 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6801 23:14:08.551509 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6802 23:14:08.554653 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6803 23:14:08.557555 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6804 23:14:08.564622 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6805 23:14:08.567883 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6806 23:14:08.571562 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6807 23:14:08.577656 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6808 23:14:08.578074 Total UI for P1: 0, mck2ui 16
6809 23:14:08.581401 best dqsien dly found for B0: ( 0, 14, 24)
6810 23:14:08.584727 Total UI for P1: 0, mck2ui 16
6811 23:14:08.588052 best dqsien dly found for B1: ( 0, 14, 24)
6812 23:14:08.594587 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6813 23:14:08.597488 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6814 23:14:08.597958
6815 23:14:08.601175 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6816 23:14:08.604602 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6817 23:14:08.607604 [Gating] SW calibration Done
6818 23:14:08.608154 ==
6819 23:14:08.611130 Dram Type= 6, Freq= 0, CH_1, rank 1
6820 23:14:08.614551 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6821 23:14:08.615040 ==
6822 23:14:08.617693 RX Vref Scan: 0
6823 23:14:08.618167
6824 23:14:08.618501 RX Vref 0 -> 0, step: 1
6825 23:14:08.618812
6826 23:14:08.620920 RX Delay -410 -> 252, step: 16
6827 23:14:08.624570 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6828 23:14:08.630824 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6829 23:14:08.634572 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6830 23:14:08.637526 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6831 23:14:08.641174 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6832 23:14:08.647573 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6833 23:14:08.651486 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6834 23:14:08.654288 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6835 23:14:08.657515 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6836 23:14:08.664406 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6837 23:14:08.668024 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6838 23:14:08.671155 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6839 23:14:08.674083 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6840 23:14:08.681214 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6841 23:14:08.684772 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6842 23:14:08.687640 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6843 23:14:08.688055 ==
6844 23:14:08.691322 Dram Type= 6, Freq= 0, CH_1, rank 1
6845 23:14:08.697371 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6846 23:14:08.697834 ==
6847 23:14:08.698170 DQS Delay:
6848 23:14:08.700799 DQS0 = 35, DQS1 = 35
6849 23:14:08.701226 DQM Delay:
6850 23:14:08.701553 DQM0 = 18, DQM1 = 13
6851 23:14:08.704283 DQ Delay:
6852 23:14:08.707490 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6853 23:14:08.710950 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6854 23:14:08.711362 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6855 23:14:08.713838 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6856 23:14:08.717374
6857 23:14:08.717879
6858 23:14:08.718210 ==
6859 23:14:08.720760 Dram Type= 6, Freq= 0, CH_1, rank 1
6860 23:14:08.724067 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6861 23:14:08.724483 ==
6862 23:14:08.724812
6863 23:14:08.725195
6864 23:14:08.727380 TX Vref Scan disable
6865 23:14:08.727794 == TX Byte 0 ==
6866 23:14:08.730773 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6867 23:14:08.737518 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6868 23:14:08.737986 == TX Byte 1 ==
6869 23:14:08.740909 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6870 23:14:08.747454 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6871 23:14:08.747950 ==
6872 23:14:08.750595 Dram Type= 6, Freq= 0, CH_1, rank 1
6873 23:14:08.754280 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6874 23:14:08.754793 ==
6875 23:14:08.755129
6876 23:14:08.755435
6877 23:14:08.757492 TX Vref Scan disable
6878 23:14:08.757950 == TX Byte 0 ==
6879 23:14:08.760926 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6880 23:14:08.767637 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6881 23:14:08.768147 == TX Byte 1 ==
6882 23:14:08.770860 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6883 23:14:08.777467 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6884 23:14:08.778128
6885 23:14:08.778568 [DATLAT]
6886 23:14:08.778894 Freq=400, CH1 RK1
6887 23:14:08.779201
6888 23:14:08.780654 DATLAT Default: 0xe
6889 23:14:08.781096 0, 0xFFFF, sum = 0
6890 23:14:08.784058 1, 0xFFFF, sum = 0
6891 23:14:08.787593 2, 0xFFFF, sum = 0
6892 23:14:08.788016 3, 0xFFFF, sum = 0
6893 23:14:08.790938 4, 0xFFFF, sum = 0
6894 23:14:08.791487 5, 0xFFFF, sum = 0
6895 23:14:08.793892 6, 0xFFFF, sum = 0
6896 23:14:08.794311 7, 0xFFFF, sum = 0
6897 23:14:08.797247 8, 0xFFFF, sum = 0
6898 23:14:08.797709 9, 0xFFFF, sum = 0
6899 23:14:08.800589 10, 0xFFFF, sum = 0
6900 23:14:08.801010 11, 0xFFFF, sum = 0
6901 23:14:08.804261 12, 0xFFFF, sum = 0
6902 23:14:08.804685 13, 0x0, sum = 1
6903 23:14:08.807331 14, 0x0, sum = 2
6904 23:14:08.807753 15, 0x0, sum = 3
6905 23:14:08.810714 16, 0x0, sum = 4
6906 23:14:08.811229 best_step = 14
6907 23:14:08.811570
6908 23:14:08.811880 ==
6909 23:14:08.813841 Dram Type= 6, Freq= 0, CH_1, rank 1
6910 23:14:08.817288 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6911 23:14:08.821031 ==
6912 23:14:08.821447 RX Vref Scan: 0
6913 23:14:08.821860
6914 23:14:08.824143 RX Vref 0 -> 0, step: 1
6915 23:14:08.824565
6916 23:14:08.824897 RX Delay -311 -> 252, step: 8
6917 23:14:08.832883 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6918 23:14:08.836612 iDelay=217, Bit 1, Center -24 (-247 ~ 200) 448
6919 23:14:08.839394 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
6920 23:14:08.843108 iDelay=217, Bit 3, Center -20 (-239 ~ 200) 440
6921 23:14:08.849519 iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440
6922 23:14:08.852794 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
6923 23:14:08.856326 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6924 23:14:08.859226 iDelay=217, Bit 7, Center -16 (-239 ~ 208) 448
6925 23:14:08.866339 iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448
6926 23:14:08.869376 iDelay=217, Bit 9, Center -28 (-247 ~ 192) 440
6927 23:14:08.872536 iDelay=217, Bit 10, Center -20 (-247 ~ 208) 456
6928 23:14:08.876240 iDelay=217, Bit 11, Center -24 (-247 ~ 200) 448
6929 23:14:08.882817 iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456
6930 23:14:08.885742 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
6931 23:14:08.889235 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6932 23:14:08.896040 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6933 23:14:08.896468 ==
6934 23:14:08.899018 Dram Type= 6, Freq= 0, CH_1, rank 1
6935 23:14:08.902716 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6936 23:14:08.903144 ==
6937 23:14:08.903496 DQS Delay:
6938 23:14:08.905672 DQS0 = 28, DQS1 = 32
6939 23:14:08.906095 DQM Delay:
6940 23:14:08.909175 DQM0 = 10, DQM1 = 11
6941 23:14:08.909643 DQ Delay:
6942 23:14:08.912655 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =8
6943 23:14:08.916343 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =12
6944 23:14:08.919183 DQ8 =0, DQ9 =4, DQ10 =12, DQ11 =8
6945 23:14:08.922350 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =16
6946 23:14:08.922770
6947 23:14:08.923104
6948 23:14:08.929419 [DQSOSCAuto] RK1, (LSB)MR18= 0xbe50, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 386 ps
6949 23:14:08.932727 CH1 RK1: MR19=C0C, MR18=BE50
6950 23:14:08.939366 CH1_RK1: MR19=0xC0C, MR18=0xBE50, DQSOSC=386, MR23=63, INC=396, DEC=264
6951 23:14:08.942630 [RxdqsGatingPostProcess] freq 400
6952 23:14:08.949098 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6953 23:14:08.949522 best DQS0 dly(2T, 0.5T) = (0, 10)
6954 23:14:08.952525 best DQS1 dly(2T, 0.5T) = (0, 10)
6955 23:14:08.955470 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6956 23:14:08.958988 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6957 23:14:08.962090 best DQS0 dly(2T, 0.5T) = (0, 10)
6958 23:14:08.965876 best DQS1 dly(2T, 0.5T) = (0, 10)
6959 23:14:08.968737 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6960 23:14:08.972815 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6961 23:14:08.975398 Pre-setting of DQS Precalculation
6962 23:14:08.982282 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6963 23:14:08.988720 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6964 23:14:08.995538 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6965 23:14:08.996062
6966 23:14:08.996400
6967 23:14:08.998484 [Calibration Summary] 800 Mbps
6968 23:14:08.998903 CH 0, Rank 0
6969 23:14:09.001850 SW Impedance : PASS
6970 23:14:09.005246 DUTY Scan : NO K
6971 23:14:09.005822 ZQ Calibration : PASS
6972 23:14:09.008646 Jitter Meter : NO K
6973 23:14:09.011519 CBT Training : PASS
6974 23:14:09.011942 Write leveling : PASS
6975 23:14:09.015026 RX DQS gating : PASS
6976 23:14:09.015445 RX DQ/DQS(RDDQC) : PASS
6977 23:14:09.018926 TX DQ/DQS : PASS
6978 23:14:09.021649 RX DATLAT : PASS
6979 23:14:09.022078 RX DQ/DQS(Engine): PASS
6980 23:14:09.025151 TX OE : NO K
6981 23:14:09.025565 All Pass.
6982 23:14:09.025945
6983 23:14:09.028344 CH 0, Rank 1
6984 23:14:09.028756 SW Impedance : PASS
6985 23:14:09.031744 DUTY Scan : NO K
6986 23:14:09.034737 ZQ Calibration : PASS
6987 23:14:09.035149 Jitter Meter : NO K
6988 23:14:09.038132 CBT Training : PASS
6989 23:14:09.041780 Write leveling : NO K
6990 23:14:09.042194 RX DQS gating : PASS
6991 23:14:09.045082 RX DQ/DQS(RDDQC) : PASS
6992 23:14:09.048441 TX DQ/DQS : PASS
6993 23:14:09.048868 RX DATLAT : PASS
6994 23:14:09.051521 RX DQ/DQS(Engine): PASS
6995 23:14:09.054990 TX OE : NO K
6996 23:14:09.055527 All Pass.
6997 23:14:09.055867
6998 23:14:09.056181 CH 1, Rank 0
6999 23:14:09.058191 SW Impedance : PASS
7000 23:14:09.061556 DUTY Scan : NO K
7001 23:14:09.062013 ZQ Calibration : PASS
7002 23:14:09.065024 Jitter Meter : NO K
7003 23:14:09.068118 CBT Training : PASS
7004 23:14:09.068538 Write leveling : PASS
7005 23:14:09.071351 RX DQS gating : PASS
7006 23:14:09.071771 RX DQ/DQS(RDDQC) : PASS
7007 23:14:09.074469 TX DQ/DQS : PASS
7008 23:14:09.078095 RX DATLAT : PASS
7009 23:14:09.078612 RX DQ/DQS(Engine): PASS
7010 23:14:09.081461 TX OE : NO K
7011 23:14:09.081922 All Pass.
7012 23:14:09.082258
7013 23:14:09.084757 CH 1, Rank 1
7014 23:14:09.085175 SW Impedance : PASS
7015 23:14:09.088450 DUTY Scan : NO K
7016 23:14:09.091285 ZQ Calibration : PASS
7017 23:14:09.091890 Jitter Meter : NO K
7018 23:14:09.094712 CBT Training : PASS
7019 23:14:09.098284 Write leveling : NO K
7020 23:14:09.098704 RX DQS gating : PASS
7021 23:14:09.101727 RX DQ/DQS(RDDQC) : PASS
7022 23:14:09.104771 TX DQ/DQS : PASS
7023 23:14:09.105193 RX DATLAT : PASS
7024 23:14:09.108371 RX DQ/DQS(Engine): PASS
7025 23:14:09.108890 TX OE : NO K
7026 23:14:09.111428 All Pass.
7027 23:14:09.111849
7028 23:14:09.112181 DramC Write-DBI off
7029 23:14:09.114966 PER_BANK_REFRESH: Hybrid Mode
7030 23:14:09.117992 TX_TRACKING: ON
7031 23:14:09.125306 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7032 23:14:09.127905 [FAST_K] Save calibration result to emmc
7033 23:14:09.134481 dramc_set_vcore_voltage set vcore to 725000
7034 23:14:09.134906 Read voltage for 1600, 0
7035 23:14:09.137924 Vio18 = 0
7036 23:14:09.138346 Vcore = 725000
7037 23:14:09.138716 Vdram = 0
7038 23:14:09.139047 Vddq = 0
7039 23:14:09.141444 Vmddr = 0
7040 23:14:09.144726 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7041 23:14:09.151575 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7042 23:14:09.154860 MEM_TYPE=3, freq_sel=13
7043 23:14:09.155282 sv_algorithm_assistance_LP4_3733
7044 23:14:09.161076 ============ PULL DRAM RESETB DOWN ============
7045 23:14:09.164644 ========== PULL DRAM RESETB DOWN end =========
7046 23:14:09.168019 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7047 23:14:09.171615 ===================================
7048 23:14:09.174713 LPDDR4 DRAM CONFIGURATION
7049 23:14:09.177663 ===================================
7050 23:14:09.181151 EX_ROW_EN[0] = 0x0
7051 23:14:09.181573 EX_ROW_EN[1] = 0x0
7052 23:14:09.184745 LP4Y_EN = 0x0
7053 23:14:09.185163 WORK_FSP = 0x1
7054 23:14:09.187815 WL = 0x5
7055 23:14:09.188236 RL = 0x5
7056 23:14:09.190996 BL = 0x2
7057 23:14:09.191417 RPST = 0x0
7058 23:14:09.194462 RD_PRE = 0x0
7059 23:14:09.195029 WR_PRE = 0x1
7060 23:14:09.198066 WR_PST = 0x1
7061 23:14:09.198524 DBI_WR = 0x0
7062 23:14:09.201047 DBI_RD = 0x0
7063 23:14:09.201467 OTF = 0x1
7064 23:14:09.204475 ===================================
7065 23:14:09.207836 ===================================
7066 23:14:09.211342 ANA top config
7067 23:14:09.214286 ===================================
7068 23:14:09.217700 DLL_ASYNC_EN = 0
7069 23:14:09.218121 ALL_SLAVE_EN = 0
7070 23:14:09.220777 NEW_RANK_MODE = 1
7071 23:14:09.224283 DLL_IDLE_MODE = 1
7072 23:14:09.227693 LP45_APHY_COMB_EN = 1
7073 23:14:09.230584 TX_ODT_DIS = 0
7074 23:14:09.230996 NEW_8X_MODE = 1
7075 23:14:09.234405 ===================================
7076 23:14:09.237628 ===================================
7077 23:14:09.240906 data_rate = 3200
7078 23:14:09.244267 CKR = 1
7079 23:14:09.247715 DQ_P2S_RATIO = 8
7080 23:14:09.250772 ===================================
7081 23:14:09.254402 CA_P2S_RATIO = 8
7082 23:14:09.257213 DQ_CA_OPEN = 0
7083 23:14:09.257680 DQ_SEMI_OPEN = 0
7084 23:14:09.260378 CA_SEMI_OPEN = 0
7085 23:14:09.263838 CA_FULL_RATE = 0
7086 23:14:09.267568 DQ_CKDIV4_EN = 0
7087 23:14:09.270774 CA_CKDIV4_EN = 0
7088 23:14:09.271196 CA_PREDIV_EN = 0
7089 23:14:09.274238 PH8_DLY = 12
7090 23:14:09.277287 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7091 23:14:09.280591 DQ_AAMCK_DIV = 4
7092 23:14:09.284342 CA_AAMCK_DIV = 4
7093 23:14:09.287420 CA_ADMCK_DIV = 4
7094 23:14:09.287955 DQ_TRACK_CA_EN = 0
7095 23:14:09.290625 CA_PICK = 1600
7096 23:14:09.294371 CA_MCKIO = 1600
7097 23:14:09.297703 MCKIO_SEMI = 0
7098 23:14:09.301119 PLL_FREQ = 3068
7099 23:14:09.304286 DQ_UI_PI_RATIO = 32
7100 23:14:09.307188 CA_UI_PI_RATIO = 0
7101 23:14:09.310887 ===================================
7102 23:14:09.313997 ===================================
7103 23:14:09.314421 memory_type:LPDDR4
7104 23:14:09.317486 GP_NUM : 10
7105 23:14:09.320590 SRAM_EN : 1
7106 23:14:09.321006 MD32_EN : 0
7107 23:14:09.324117 ===================================
7108 23:14:09.327078 [ANA_INIT] >>>>>>>>>>>>>>
7109 23:14:09.330589 <<<<<< [CONFIGURE PHASE]: ANA_TX
7110 23:14:09.333786 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7111 23:14:09.337253 ===================================
7112 23:14:09.340895 data_rate = 3200,PCW = 0X7600
7113 23:14:09.343939 ===================================
7114 23:14:09.347081 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7115 23:14:09.350417 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7116 23:14:09.357065 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7117 23:14:09.360382 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7118 23:14:09.364260 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7119 23:14:09.367295 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7120 23:14:09.370405 [ANA_INIT] flow start
7121 23:14:09.373529 [ANA_INIT] PLL >>>>>>>>
7122 23:14:09.373982 [ANA_INIT] PLL <<<<<<<<
7123 23:14:09.376914 [ANA_INIT] MIDPI >>>>>>>>
7124 23:14:09.380373 [ANA_INIT] MIDPI <<<<<<<<
7125 23:14:09.383883 [ANA_INIT] DLL >>>>>>>>
7126 23:14:09.384296 [ANA_INIT] DLL <<<<<<<<
7127 23:14:09.386855 [ANA_INIT] flow end
7128 23:14:09.390581 ============ LP4 DIFF to SE enter ============
7129 23:14:09.393892 ============ LP4 DIFF to SE exit ============
7130 23:14:09.397114 [ANA_INIT] <<<<<<<<<<<<<
7131 23:14:09.400482 [Flow] Enable top DCM control >>>>>
7132 23:14:09.403302 [Flow] Enable top DCM control <<<<<
7133 23:14:09.407128 Enable DLL master slave shuffle
7134 23:14:09.413378 ==============================================================
7135 23:14:09.413839 Gating Mode config
7136 23:14:09.420077 ==============================================================
7137 23:14:09.420563 Config description:
7138 23:14:09.430349 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7139 23:14:09.436607 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7140 23:14:09.442889 SELPH_MODE 0: By rank 1: By Phase
7141 23:14:09.446444 ==============================================================
7142 23:14:09.449980 GAT_TRACK_EN = 1
7143 23:14:09.453100 RX_GATING_MODE = 2
7144 23:14:09.456279 RX_GATING_TRACK_MODE = 2
7145 23:14:09.459575 SELPH_MODE = 1
7146 23:14:09.462872 PICG_EARLY_EN = 1
7147 23:14:09.466367 VALID_LAT_VALUE = 1
7148 23:14:09.473210 ==============================================================
7149 23:14:09.476495 Enter into Gating configuration >>>>
7150 23:14:09.480038 Exit from Gating configuration <<<<
7151 23:14:09.480452 Enter into DVFS_PRE_config >>>>>
7152 23:14:09.492630 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7153 23:14:09.496165 Exit from DVFS_PRE_config <<<<<
7154 23:14:09.499641 Enter into PICG configuration >>>>
7155 23:14:09.502697 Exit from PICG configuration <<<<
7156 23:14:09.503110 [RX_INPUT] configuration >>>>>
7157 23:14:09.506355 [RX_INPUT] configuration <<<<<
7158 23:14:09.512821 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7159 23:14:09.519335 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7160 23:14:09.522925 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7161 23:14:09.529490 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7162 23:14:09.535764 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7163 23:14:09.542293 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7164 23:14:09.545858 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7165 23:14:09.549146 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7166 23:14:09.556157 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7167 23:14:09.559060 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7168 23:14:09.562385 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7169 23:14:09.569073 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7170 23:14:09.572346 ===================================
7171 23:14:09.572837 LPDDR4 DRAM CONFIGURATION
7172 23:14:09.575531 ===================================
7173 23:14:09.578946 EX_ROW_EN[0] = 0x0
7174 23:14:09.579399 EX_ROW_EN[1] = 0x0
7175 23:14:09.582347 LP4Y_EN = 0x0
7176 23:14:09.582800 WORK_FSP = 0x1
7177 23:14:09.585992 WL = 0x5
7178 23:14:09.586442 RL = 0x5
7179 23:14:09.588698 BL = 0x2
7180 23:14:09.592430 RPST = 0x0
7181 23:14:09.592959 RD_PRE = 0x0
7182 23:14:09.595662 WR_PRE = 0x1
7183 23:14:09.596072 WR_PST = 0x1
7184 23:14:09.598732 DBI_WR = 0x0
7185 23:14:09.599157 DBI_RD = 0x0
7186 23:14:09.602183 OTF = 0x1
7187 23:14:09.605394 ===================================
7188 23:14:09.609023 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7189 23:14:09.611842 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7190 23:14:09.615421 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7191 23:14:09.618381 ===================================
7192 23:14:09.621825 LPDDR4 DRAM CONFIGURATION
7193 23:14:09.625427 ===================================
7194 23:14:09.628837 EX_ROW_EN[0] = 0x10
7195 23:14:09.629268 EX_ROW_EN[1] = 0x0
7196 23:14:09.631822 LP4Y_EN = 0x0
7197 23:14:09.632250 WORK_FSP = 0x1
7198 23:14:09.635257 WL = 0x5
7199 23:14:09.635684 RL = 0x5
7200 23:14:09.638282 BL = 0x2
7201 23:14:09.642039 RPST = 0x0
7202 23:14:09.642484 RD_PRE = 0x0
7203 23:14:09.645228 WR_PRE = 0x1
7204 23:14:09.645692 WR_PST = 0x1
7205 23:14:09.648737 DBI_WR = 0x0
7206 23:14:09.649174 DBI_RD = 0x0
7207 23:14:09.651877 OTF = 0x1
7208 23:14:09.655271 ===================================
7209 23:14:09.658603 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7210 23:14:09.661693 ==
7211 23:14:09.665121 Dram Type= 6, Freq= 0, CH_0, rank 0
7212 23:14:09.668654 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7213 23:14:09.669181 ==
7214 23:14:09.671742 [Duty_Offset_Calibration]
7215 23:14:09.672172 B0:2 B1:1 CA:1
7216 23:14:09.672635
7217 23:14:09.675173 [DutyScan_Calibration_Flow] k_type=0
7218 23:14:09.684759
7219 23:14:09.685212 ==CLK 0==
7220 23:14:09.688224 Final CLK duty delay cell = 0
7221 23:14:09.691390 [0] MAX Duty = 5156%(X100), DQS PI = 22
7222 23:14:09.694787 [0] MIN Duty = 4907%(X100), DQS PI = 0
7223 23:14:09.695095 [0] AVG Duty = 5031%(X100)
7224 23:14:09.698152
7225 23:14:09.701171 CH0 CLK Duty spec in!! Max-Min= 249%
7226 23:14:09.704410 [DutyScan_Calibration_Flow] ====Done====
7227 23:14:09.704691
7228 23:14:09.707905 [DutyScan_Calibration_Flow] k_type=1
7229 23:14:09.723651
7230 23:14:09.723804 ==DQS 0 ==
7231 23:14:09.727032 Final DQS duty delay cell = -4
7232 23:14:09.730012 [-4] MAX Duty = 5125%(X100), DQS PI = 26
7233 23:14:09.733422 [-4] MIN Duty = 4657%(X100), DQS PI = 0
7234 23:14:09.736906 [-4] AVG Duty = 4891%(X100)
7235 23:14:09.737036
7236 23:14:09.737146 ==DQS 1 ==
7237 23:14:09.740150 Final DQS duty delay cell = 0
7238 23:14:09.743509 [0] MAX Duty = 5187%(X100), DQS PI = 4
7239 23:14:09.746971 [0] MIN Duty = 5031%(X100), DQS PI = 52
7240 23:14:09.750523 [0] AVG Duty = 5109%(X100)
7241 23:14:09.750626
7242 23:14:09.753405 CH0 DQS 0 Duty spec in!! Max-Min= 468%
7243 23:14:09.753504
7244 23:14:09.757055 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7245 23:14:09.760445 [DutyScan_Calibration_Flow] ====Done====
7246 23:14:09.760543
7247 23:14:09.763470 [DutyScan_Calibration_Flow] k_type=3
7248 23:14:09.780264
7249 23:14:09.780383 ==DQM 0 ==
7250 23:14:09.783314 Final DQM duty delay cell = 0
7251 23:14:09.787038 [0] MAX Duty = 5218%(X100), DQS PI = 34
7252 23:14:09.790438 [0] MIN Duty = 4907%(X100), DQS PI = 54
7253 23:14:09.790875 [0] AVG Duty = 5062%(X100)
7254 23:14:09.793718
7255 23:14:09.794140 ==DQM 1 ==
7256 23:14:09.796895 Final DQM duty delay cell = -4
7257 23:14:09.800634 [-4] MAX Duty = 4969%(X100), DQS PI = 22
7258 23:14:09.803420 [-4] MIN Duty = 4813%(X100), DQS PI = 14
7259 23:14:09.806736 [-4] AVG Duty = 4891%(X100)
7260 23:14:09.806922
7261 23:14:09.810099 CH0 DQM 0 Duty spec in!! Max-Min= 311%
7262 23:14:09.810253
7263 23:14:09.813318 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7264 23:14:09.816808 [DutyScan_Calibration_Flow] ====Done====
7265 23:14:09.816941
7266 23:14:09.819985 [DutyScan_Calibration_Flow] k_type=2
7267 23:14:09.838029
7268 23:14:09.838159 ==DQ 0 ==
7269 23:14:09.841035 Final DQ duty delay cell = 0
7270 23:14:09.844448 [0] MAX Duty = 5062%(X100), DQS PI = 26
7271 23:14:09.847540 [0] MIN Duty = 4907%(X100), DQS PI = 0
7272 23:14:09.847623 [0] AVG Duty = 4984%(X100)
7273 23:14:09.847689
7274 23:14:09.851039 ==DQ 1 ==
7275 23:14:09.854385 Final DQ duty delay cell = 0
7276 23:14:09.857466 [0] MAX Duty = 5156%(X100), DQS PI = 22
7277 23:14:09.861066 [0] MIN Duty = 4907%(X100), DQS PI = 34
7278 23:14:09.861148 [0] AVG Duty = 5031%(X100)
7279 23:14:09.861214
7280 23:14:09.867340 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7281 23:14:09.867423
7282 23:14:09.870959 CH0 DQ 1 Duty spec in!! Max-Min= 249%
7283 23:14:09.873827 [DutyScan_Calibration_Flow] ====Done====
7284 23:14:09.873909 ==
7285 23:14:09.877272 Dram Type= 6, Freq= 0, CH_1, rank 0
7286 23:14:09.880694 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7287 23:14:09.880777 ==
7288 23:14:09.883702 [Duty_Offset_Calibration]
7289 23:14:09.883784 B0:1 B1:0 CA:0
7290 23:14:09.883849
7291 23:14:09.887076 [DutyScan_Calibration_Flow] k_type=0
7292 23:14:09.896991
7293 23:14:09.897115 ==CLK 0==
7294 23:14:09.900249 Final CLK duty delay cell = -4
7295 23:14:09.903582 [-4] MAX Duty = 4969%(X100), DQS PI = 28
7296 23:14:09.906897 [-4] MIN Duty = 4844%(X100), DQS PI = 2
7297 23:14:09.910538 [-4] AVG Duty = 4906%(X100)
7298 23:14:09.910622
7299 23:14:09.914109 CH1 CLK Duty spec in!! Max-Min= 125%
7300 23:14:09.916932 [DutyScan_Calibration_Flow] ====Done====
7301 23:14:09.917016
7302 23:14:09.920189 [DutyScan_Calibration_Flow] k_type=1
7303 23:14:09.937340
7304 23:14:09.937443 ==DQS 0 ==
7305 23:14:09.940435 Final DQS duty delay cell = 0
7306 23:14:09.943600 [0] MAX Duty = 5094%(X100), DQS PI = 46
7307 23:14:09.946888 [0] MIN Duty = 4844%(X100), DQS PI = 14
7308 23:14:09.950215 [0] AVG Duty = 4969%(X100)
7309 23:14:09.950300
7310 23:14:09.950366 ==DQS 1 ==
7311 23:14:09.953710 Final DQS duty delay cell = 0
7312 23:14:09.957462 [0] MAX Duty = 5249%(X100), DQS PI = 48
7313 23:14:09.960980 [0] MIN Duty = 4907%(X100), DQS PI = 40
7314 23:14:09.963874 [0] AVG Duty = 5078%(X100)
7315 23:14:09.964294
7316 23:14:09.967601 CH1 DQS 0 Duty spec in!! Max-Min= 250%
7317 23:14:09.968019
7318 23:14:09.970447 CH1 DQS 1 Duty spec in!! Max-Min= 342%
7319 23:14:09.973736 [DutyScan_Calibration_Flow] ====Done====
7320 23:14:09.974152
7321 23:14:09.977352 [DutyScan_Calibration_Flow] k_type=3
7322 23:14:09.994579
7323 23:14:09.994990 ==DQM 0 ==
7324 23:14:09.997891 Final DQM duty delay cell = 0
7325 23:14:10.000811 [0] MAX Duty = 5187%(X100), DQS PI = 40
7326 23:14:10.004259 [0] MIN Duty = 5000%(X100), DQS PI = 16
7327 23:14:10.007361 [0] AVG Duty = 5093%(X100)
7328 23:14:10.007603
7329 23:14:10.007796 ==DQM 1 ==
7330 23:14:10.010588 Final DQM duty delay cell = 0
7331 23:14:10.013828 [0] MAX Duty = 5125%(X100), DQS PI = 10
7332 23:14:10.017412 [0] MIN Duty = 4907%(X100), DQS PI = 0
7333 23:14:10.021008 [0] AVG Duty = 5016%(X100)
7334 23:14:10.021165
7335 23:14:10.023841 CH1 DQM 0 Duty spec in!! Max-Min= 187%
7336 23:14:10.024007
7337 23:14:10.027466 CH1 DQM 1 Duty spec in!! Max-Min= 218%
7338 23:14:10.030368 [DutyScan_Calibration_Flow] ====Done====
7339 23:14:10.030526
7340 23:14:10.033644 [DutyScan_Calibration_Flow] k_type=2
7341 23:14:10.050884
7342 23:14:10.051307 ==DQ 0 ==
7343 23:14:10.054035 Final DQ duty delay cell = -4
7344 23:14:10.057214 [-4] MAX Duty = 5031%(X100), DQS PI = 24
7345 23:14:10.060724 [-4] MIN Duty = 4875%(X100), DQS PI = 6
7346 23:14:10.063688 [-4] AVG Duty = 4953%(X100)
7347 23:14:10.064109
7348 23:14:10.064441 ==DQ 1 ==
7349 23:14:10.067095 Final DQ duty delay cell = 0
7350 23:14:10.070284 [0] MAX Duty = 5125%(X100), DQS PI = 10
7351 23:14:10.073402 [0] MIN Duty = 4938%(X100), DQS PI = 0
7352 23:14:10.076891 [0] AVG Duty = 5031%(X100)
7353 23:14:10.077193
7354 23:14:10.080468 CH1 DQ 0 Duty spec in!! Max-Min= 156%
7355 23:14:10.080693
7356 23:14:10.083396 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7357 23:14:10.086603 [DutyScan_Calibration_Flow] ====Done====
7358 23:14:10.090195 nWR fixed to 30
7359 23:14:10.090438 [ModeRegInit_LP4] CH0 RK0
7360 23:14:10.093113 [ModeRegInit_LP4] CH0 RK1
7361 23:14:10.096596 [ModeRegInit_LP4] CH1 RK0
7362 23:14:10.100159 [ModeRegInit_LP4] CH1 RK1
7363 23:14:10.100290 match AC timing 5
7364 23:14:10.106938 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7365 23:14:10.109802 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7366 23:14:10.113118 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7367 23:14:10.119866 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7368 23:14:10.123131 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7369 23:14:10.123223 [MiockJmeterHQA]
7370 23:14:10.123295
7371 23:14:10.126709 [DramcMiockJmeter] u1RxGatingPI = 0
7372 23:14:10.130296 0 : 4252, 4027
7373 23:14:10.130390 4 : 4363, 4138
7374 23:14:10.133188 8 : 4252, 4027
7375 23:14:10.133281 12 : 4252, 4027
7376 23:14:10.133356 16 : 4252, 4027
7377 23:14:10.136714 20 : 4252, 4027
7378 23:14:10.136806 24 : 4255, 4030
7379 23:14:10.140004 28 : 4252, 4027
7380 23:14:10.140095 32 : 4252, 4027
7381 23:14:10.143003 36 : 4365, 4140
7382 23:14:10.143095 40 : 4253, 4026
7383 23:14:10.146696 44 : 4255, 4029
7384 23:14:10.146787 48 : 4252, 4027
7385 23:14:10.146861 52 : 4363, 4137
7386 23:14:10.149572 56 : 4253, 4027
7387 23:14:10.149679 60 : 4360, 4137
7388 23:14:10.153120 64 : 4252, 4027
7389 23:14:10.153223 68 : 4249, 4027
7390 23:14:10.156568 72 : 4250, 4026
7391 23:14:10.156660 76 : 4252, 4030
7392 23:14:10.156734 80 : 4361, 4138
7393 23:14:10.159564 84 : 4250, 4027
7394 23:14:10.159656 88 : 4360, 47
7395 23:14:10.163033 92 : 4250, 0
7396 23:14:10.163125 96 : 4252, 0
7397 23:14:10.163199 100 : 4360, 0
7398 23:14:10.166106 104 : 4363, 0
7399 23:14:10.166205 108 : 4252, 0
7400 23:14:10.169409 112 : 4250, 0
7401 23:14:10.169508 116 : 4249, 0
7402 23:14:10.169599 120 : 4250, 0
7403 23:14:10.172855 124 : 4250, 0
7404 23:14:10.172962 128 : 4250, 0
7405 23:14:10.176065 132 : 4253, 0
7406 23:14:10.176196 136 : 4360, 0
7407 23:14:10.176292 140 : 4361, 0
7408 23:14:10.179691 144 : 4363, 0
7409 23:14:10.179811 148 : 4250, 0
7410 23:14:10.182766 152 : 4361, 0
7411 23:14:10.182885 156 : 4250, 0
7412 23:14:10.182980 160 : 4250, 0
7413 23:14:10.186285 164 : 4250, 0
7414 23:14:10.186409 168 : 4250, 0
7415 23:14:10.186505 172 : 4253, 0
7416 23:14:10.189226 176 : 4250, 0
7417 23:14:10.189384 180 : 4250, 0
7418 23:14:10.193015 184 : 4253, 0
7419 23:14:10.193134 188 : 4360, 0
7420 23:14:10.193227 192 : 4360, 0
7421 23:14:10.196080 196 : 4250, 0
7422 23:14:10.196199 200 : 4250, 0
7423 23:14:10.199336 204 : 4361, 1444
7424 23:14:10.199454 208 : 4250, 3995
7425 23:14:10.202749 212 : 4250, 4027
7426 23:14:10.202879 216 : 4250, 4027
7427 23:14:10.206245 220 : 4361, 4137
7428 23:14:10.206371 224 : 4361, 4137
7429 23:14:10.206473 228 : 4250, 4027
7430 23:14:10.209105 232 : 4363, 4140
7431 23:14:10.209225 236 : 4361, 4137
7432 23:14:10.212475 240 : 4250, 4026
7433 23:14:10.212601 244 : 4250, 4027
7434 23:14:10.215950 248 : 4252, 4029
7435 23:14:10.216096 252 : 4250, 4027
7436 23:14:10.219355 256 : 4250, 4026
7437 23:14:10.219475 260 : 4250, 4027
7438 23:14:10.222660 264 : 4252, 4029
7439 23:14:10.222767 268 : 4249, 4027
7440 23:14:10.225887 272 : 4360, 4137
7441 23:14:10.225985 276 : 4361, 4137
7442 23:14:10.229599 280 : 4250, 4027
7443 23:14:10.229705 284 : 4363, 4140
7444 23:14:10.229774 288 : 4249, 4027
7445 23:14:10.232548 292 : 4250, 4026
7446 23:14:10.232633 296 : 4250, 4027
7447 23:14:10.235922 300 : 4252, 4030
7448 23:14:10.236008 304 : 4249, 4027
7449 23:14:10.239427 308 : 4250, 3954
7450 23:14:10.239538 312 : 4250, 1954
7451 23:14:10.239608
7452 23:14:10.242405 MIOCK jitter meter ch=0
7453 23:14:10.242490
7454 23:14:10.245782 1T = (312-88) = 224 dly cells
7455 23:14:10.252669 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7456 23:14:10.252753 ==
7457 23:14:10.255682 Dram Type= 6, Freq= 0, CH_0, rank 0
7458 23:14:10.259041 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7459 23:14:10.259127 ==
7460 23:14:10.265762 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7461 23:14:10.269181 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7462 23:14:10.272583 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7463 23:14:10.279572 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7464 23:14:10.287614 [CA 0] Center 42 (12~73) winsize 62
7465 23:14:10.291183 [CA 1] Center 42 (12~73) winsize 62
7466 23:14:10.294493 [CA 2] Center 37 (8~67) winsize 60
7467 23:14:10.297905 [CA 3] Center 37 (7~67) winsize 61
7468 23:14:10.300935 [CA 4] Center 36 (6~66) winsize 61
7469 23:14:10.304200 [CA 5] Center 35 (6~64) winsize 59
7470 23:14:10.304439
7471 23:14:10.307757 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7472 23:14:10.308030
7473 23:14:10.310931 [CATrainingPosCal] consider 1 rank data
7474 23:14:10.314582 u2DelayCellTimex100 = 290/100 ps
7475 23:14:10.317737 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7476 23:14:10.324629 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7477 23:14:10.327866 CA2 delay=37 (8~67),Diff = 2 PI (6 cell)
7478 23:14:10.331096 CA3 delay=37 (7~67),Diff = 2 PI (6 cell)
7479 23:14:10.334362 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7480 23:14:10.337532 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7481 23:14:10.338063
7482 23:14:10.340803 CA PerBit enable=1, Macro0, CA PI delay=35
7483 23:14:10.341224
7484 23:14:10.344221 [CBTSetCACLKResult] CA Dly = 35
7485 23:14:10.347717 CS Dly: 9 (0~40)
7486 23:14:10.351226 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7487 23:14:10.354108 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7488 23:14:10.354521 ==
7489 23:14:10.357692 Dram Type= 6, Freq= 0, CH_0, rank 1
7490 23:14:10.360790 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7491 23:14:10.364481 ==
7492 23:14:10.368100 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7493 23:14:10.370640 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7494 23:14:10.378106 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7495 23:14:10.380840 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7496 23:14:10.391763 [CA 0] Center 42 (12~73) winsize 62
7497 23:14:10.394523 [CA 1] Center 42 (12~73) winsize 62
7498 23:14:10.397910 [CA 2] Center 38 (8~68) winsize 61
7499 23:14:10.401414 [CA 3] Center 38 (8~68) winsize 61
7500 23:14:10.404424 [CA 4] Center 36 (6~66) winsize 61
7501 23:14:10.407889 [CA 5] Center 35 (5~65) winsize 61
7502 23:14:10.408309
7503 23:14:10.411430 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7504 23:14:10.411851
7505 23:14:10.414699 [CATrainingPosCal] consider 2 rank data
7506 23:14:10.417712 u2DelayCellTimex100 = 290/100 ps
7507 23:14:10.421031 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7508 23:14:10.428072 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7509 23:14:10.431122 CA2 delay=37 (8~67),Diff = 2 PI (6 cell)
7510 23:14:10.434204 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7511 23:14:10.437540 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7512 23:14:10.441216 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7513 23:14:10.441675
7514 23:14:10.444398 CA PerBit enable=1, Macro0, CA PI delay=35
7515 23:14:10.444838
7516 23:14:10.447446 [CBTSetCACLKResult] CA Dly = 35
7517 23:14:10.450879 CS Dly: 10 (0~42)
7518 23:14:10.454421 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7519 23:14:10.457499 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7520 23:14:10.458005
7521 23:14:10.460915 ----->DramcWriteLeveling(PI) begin...
7522 23:14:10.461559 ==
7523 23:14:10.464080 Dram Type= 6, Freq= 0, CH_0, rank 0
7524 23:14:10.470926 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7525 23:14:10.471573 ==
7526 23:14:10.474014 Write leveling (Byte 0): 36 => 36
7527 23:14:10.474496 Write leveling (Byte 1): 27 => 27
7528 23:14:10.477381 DramcWriteLeveling(PI) end<-----
7529 23:14:10.477917
7530 23:14:10.478417 ==
7531 23:14:10.480985 Dram Type= 6, Freq= 0, CH_0, rank 0
7532 23:14:10.487427 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7533 23:14:10.487846 ==
7534 23:14:10.490303 [Gating] SW mode calibration
7535 23:14:10.497069 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7536 23:14:10.500563 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7537 23:14:10.506956 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7538 23:14:10.510621 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7539 23:14:10.514081 1 4 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7540 23:14:10.520759 1 4 12 | B1->B0 | 2323 3535 | 0 0 | (0 0) (0 0)
7541 23:14:10.524267 1 4 16 | B1->B0 | 2323 3535 | 0 1 | (0 0) (1 1)
7542 23:14:10.527435 1 4 20 | B1->B0 | 3333 3636 | 1 0 | (1 1) (0 0)
7543 23:14:10.533996 1 4 24 | B1->B0 | 3434 3534 | 1 1 | (1 1) (1 1)
7544 23:14:10.536937 1 4 28 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
7545 23:14:10.540038 1 5 0 | B1->B0 | 3434 3534 | 1 1 | (1 1) (0 0)
7546 23:14:10.546923 1 5 4 | B1->B0 | 3434 3535 | 1 0 | (1 1) (1 1)
7547 23:14:10.550205 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7548 23:14:10.553514 1 5 12 | B1->B0 | 3434 2827 | 1 1 | (1 1) (1 0)
7549 23:14:10.560604 1 5 16 | B1->B0 | 3333 2626 | 1 0 | (1 0) (0 0)
7550 23:14:10.563749 1 5 20 | B1->B0 | 2424 2626 | 0 0 | (0 0) (0 0)
7551 23:14:10.566976 1 5 24 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7552 23:14:10.573115 1 5 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7553 23:14:10.577194 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7554 23:14:10.580459 1 6 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7555 23:14:10.583686 1 6 8 | B1->B0 | 2323 3636 | 0 1 | (0 0) (0 0)
7556 23:14:10.590407 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7557 23:14:10.593424 1 6 16 | B1->B0 | 2e2e 4646 | 0 0 | (0 0) (0 0)
7558 23:14:10.596915 1 6 20 | B1->B0 | 4242 4645 | 0 1 | (0 0) (0 0)
7559 23:14:10.603399 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7560 23:14:10.606613 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7561 23:14:10.610156 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7562 23:14:10.617250 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7563 23:14:10.619924 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7564 23:14:10.623657 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7565 23:14:10.630101 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7566 23:14:10.633282 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7567 23:14:10.637133 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7568 23:14:10.643724 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7569 23:14:10.646726 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7570 23:14:10.649973 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7571 23:14:10.656607 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7572 23:14:10.659976 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7573 23:14:10.663032 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7574 23:14:10.670244 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7575 23:14:10.673163 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7576 23:14:10.676713 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7577 23:14:10.683164 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7578 23:14:10.686196 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7579 23:14:10.689466 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7580 23:14:10.696295 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7581 23:14:10.699614 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7582 23:14:10.703114 Total UI for P1: 0, mck2ui 16
7583 23:14:10.706116 best dqsien dly found for B0: ( 1, 9, 10)
7584 23:14:10.709322 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7585 23:14:10.712686 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7586 23:14:10.716222 Total UI for P1: 0, mck2ui 16
7587 23:14:10.719790 best dqsien dly found for B1: ( 1, 9, 18)
7588 23:14:10.722958 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7589 23:14:10.729736 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7590 23:14:10.730234
7591 23:14:10.733556 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7592 23:14:10.736372 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7593 23:14:10.739458 [Gating] SW calibration Done
7594 23:14:10.739872 ==
7595 23:14:10.742767 Dram Type= 6, Freq= 0, CH_0, rank 0
7596 23:14:10.746182 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7597 23:14:10.746599 ==
7598 23:14:10.749301 RX Vref Scan: 0
7599 23:14:10.749918
7600 23:14:10.750255 RX Vref 0 -> 0, step: 1
7601 23:14:10.750568
7602 23:14:10.752802 RX Delay 0 -> 252, step: 8
7603 23:14:10.756789 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
7604 23:14:10.759761 iDelay=200, Bit 1, Center 143 (88 ~ 199) 112
7605 23:14:10.766307 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
7606 23:14:10.769618 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7607 23:14:10.772744 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7608 23:14:10.776194 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7609 23:14:10.779998 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7610 23:14:10.786259 iDelay=200, Bit 7, Center 143 (96 ~ 191) 96
7611 23:14:10.790187 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
7612 23:14:10.792780 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
7613 23:14:10.796464 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
7614 23:14:10.799687 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7615 23:14:10.806266 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
7616 23:14:10.809671 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
7617 23:14:10.813454 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7618 23:14:10.816284 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7619 23:14:10.816702 ==
7620 23:14:10.820175 Dram Type= 6, Freq= 0, CH_0, rank 0
7621 23:14:10.826207 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7622 23:14:10.826627 ==
7623 23:14:10.827045 DQS Delay:
7624 23:14:10.827485 DQS0 = 0, DQS1 = 0
7625 23:14:10.829332 DQM Delay:
7626 23:14:10.829958 DQM0 = 137, DQM1 = 130
7627 23:14:10.832688 DQ Delay:
7628 23:14:10.836361 DQ0 =135, DQ1 =143, DQ2 =135, DQ3 =131
7629 23:14:10.839520 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =143
7630 23:14:10.843052 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
7631 23:14:10.845820 DQ12 =139, DQ13 =139, DQ14 =139, DQ15 =135
7632 23:14:10.846235
7633 23:14:10.846567
7634 23:14:10.846872 ==
7635 23:14:10.849241 Dram Type= 6, Freq= 0, CH_0, rank 0
7636 23:14:10.852464 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7637 23:14:10.856127 ==
7638 23:14:10.856640
7639 23:14:10.856968
7640 23:14:10.857269 TX Vref Scan disable
7641 23:14:10.859889 == TX Byte 0 ==
7642 23:14:10.862599 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7643 23:14:10.866020 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7644 23:14:10.869673 == TX Byte 1 ==
7645 23:14:10.872765 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7646 23:14:10.876188 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7647 23:14:10.879485 ==
7648 23:14:10.880022 Dram Type= 6, Freq= 0, CH_0, rank 0
7649 23:14:10.885529 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7650 23:14:10.886077 ==
7651 23:14:10.897657
7652 23:14:10.900830 TX Vref early break, caculate TX vref
7653 23:14:10.904155 TX Vref=16, minBit 9, minWin=22, winSum=377
7654 23:14:10.907339 TX Vref=18, minBit 3, minWin=22, winSum=384
7655 23:14:10.910861 TX Vref=20, minBit 7, minWin=23, winSum=400
7656 23:14:10.914172 TX Vref=22, minBit 8, minWin=24, winSum=405
7657 23:14:10.917264 TX Vref=24, minBit 7, minWin=24, winSum=411
7658 23:14:10.924328 TX Vref=26, minBit 2, minWin=25, winSum=425
7659 23:14:10.927583 TX Vref=28, minBit 2, minWin=24, winSum=422
7660 23:14:10.930762 TX Vref=30, minBit 1, minWin=24, winSum=416
7661 23:14:10.933980 TX Vref=32, minBit 0, minWin=24, winSum=401
7662 23:14:10.940566 [TxChooseVref] Worse bit 2, Min win 25, Win sum 425, Final Vref 26
7663 23:14:10.941167
7664 23:14:10.943951 Final TX Range 0 Vref 26
7665 23:14:10.944557
7666 23:14:10.945027 ==
7667 23:14:10.947385 Dram Type= 6, Freq= 0, CH_0, rank 0
7668 23:14:10.950659 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7669 23:14:10.951119 ==
7670 23:14:10.951547
7671 23:14:10.951897
7672 23:14:10.954056 TX Vref Scan disable
7673 23:14:10.957321 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7674 23:14:10.960514 == TX Byte 0 ==
7675 23:14:10.964170 u2DelayCellOfst[0]=10 cells (3 PI)
7676 23:14:10.967304 u2DelayCellOfst[1]=13 cells (4 PI)
7677 23:14:10.970836 u2DelayCellOfst[2]=10 cells (3 PI)
7678 23:14:10.973840 u2DelayCellOfst[3]=6 cells (2 PI)
7679 23:14:10.977268 u2DelayCellOfst[4]=6 cells (2 PI)
7680 23:14:10.977870 u2DelayCellOfst[5]=0 cells (0 PI)
7681 23:14:10.980699 u2DelayCellOfst[6]=13 cells (4 PI)
7682 23:14:10.983933 u2DelayCellOfst[7]=16 cells (5 PI)
7683 23:14:10.990588 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7684 23:14:10.993612 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7685 23:14:10.994074 == TX Byte 1 ==
7686 23:14:10.997418 u2DelayCellOfst[8]=0 cells (0 PI)
7687 23:14:11.000620 u2DelayCellOfst[9]=3 cells (1 PI)
7688 23:14:11.004114 u2DelayCellOfst[10]=6 cells (2 PI)
7689 23:14:11.006903 u2DelayCellOfst[11]=3 cells (1 PI)
7690 23:14:11.010447 u2DelayCellOfst[12]=13 cells (4 PI)
7691 23:14:11.013720 u2DelayCellOfst[13]=13 cells (4 PI)
7692 23:14:11.016942 u2DelayCellOfst[14]=13 cells (4 PI)
7693 23:14:11.020765 u2DelayCellOfst[15]=10 cells (3 PI)
7694 23:14:11.024286 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7695 23:14:11.026897 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7696 23:14:11.030517 DramC Write-DBI on
7697 23:14:11.031155 ==
7698 23:14:11.033807 Dram Type= 6, Freq= 0, CH_0, rank 0
7699 23:14:11.037044 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7700 23:14:11.037532 ==
7701 23:14:11.037965
7702 23:14:11.038370
7703 23:14:11.040146 TX Vref Scan disable
7704 23:14:11.043786 == TX Byte 0 ==
7705 23:14:11.046698 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7706 23:14:11.050088 == TX Byte 1 ==
7707 23:14:11.053282 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
7708 23:14:11.053736 DramC Write-DBI off
7709 23:14:11.054080
7710 23:14:11.056891 [DATLAT]
7711 23:14:11.057326 Freq=1600, CH0 RK0
7712 23:14:11.057745
7713 23:14:11.059856 DATLAT Default: 0xf
7714 23:14:11.060274 0, 0xFFFF, sum = 0
7715 23:14:11.063318 1, 0xFFFF, sum = 0
7716 23:14:11.063742 2, 0xFFFF, sum = 0
7717 23:14:11.067119 3, 0xFFFF, sum = 0
7718 23:14:11.067571 4, 0xFFFF, sum = 0
7719 23:14:11.070394 5, 0xFFFF, sum = 0
7720 23:14:11.070835 6, 0xFFFF, sum = 0
7721 23:14:11.073462 7, 0xFFFF, sum = 0
7722 23:14:11.074039 8, 0xFFFF, sum = 0
7723 23:14:11.076824 9, 0xFFFF, sum = 0
7724 23:14:11.077261 10, 0xFFFF, sum = 0
7725 23:14:11.080524 11, 0xFFFF, sum = 0
7726 23:14:11.083535 12, 0xFFFF, sum = 0
7727 23:14:11.084045 13, 0xFFFF, sum = 0
7728 23:14:11.086995 14, 0x0, sum = 1
7729 23:14:11.087482 15, 0x0, sum = 2
7730 23:14:11.090397 16, 0x0, sum = 3
7731 23:14:11.090838 17, 0x0, sum = 4
7732 23:14:11.091212 best_step = 15
7733 23:14:11.091636
7734 23:14:11.093339 ==
7735 23:14:11.096986 Dram Type= 6, Freq= 0, CH_0, rank 0
7736 23:14:11.099782 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7737 23:14:11.100315 ==
7738 23:14:11.100885 RX Vref Scan: 1
7739 23:14:11.101403
7740 23:14:11.103217 Set Vref Range= 24 -> 127
7741 23:14:11.103772
7742 23:14:11.106578 RX Vref 24 -> 127, step: 1
7743 23:14:11.107137
7744 23:14:11.109987 RX Delay 19 -> 252, step: 4
7745 23:14:11.110505
7746 23:14:11.113176 Set Vref, RX VrefLevel [Byte0]: 24
7747 23:14:11.116468 [Byte1]: 24
7748 23:14:11.116964
7749 23:14:11.120104 Set Vref, RX VrefLevel [Byte0]: 25
7750 23:14:11.122954 [Byte1]: 25
7751 23:14:11.123414
7752 23:14:11.126805 Set Vref, RX VrefLevel [Byte0]: 26
7753 23:14:11.129864 [Byte1]: 26
7754 23:14:11.133498
7755 23:14:11.133985 Set Vref, RX VrefLevel [Byte0]: 27
7756 23:14:11.136593 [Byte1]: 27
7757 23:14:11.141083
7758 23:14:11.141515 Set Vref, RX VrefLevel [Byte0]: 28
7759 23:14:11.144071 [Byte1]: 28
7760 23:14:11.148466
7761 23:14:11.148910 Set Vref, RX VrefLevel [Byte0]: 29
7762 23:14:11.151626 [Byte1]: 29
7763 23:14:11.155787
7764 23:14:11.156311 Set Vref, RX VrefLevel [Byte0]: 30
7765 23:14:11.159203 [Byte1]: 30
7766 23:14:11.163294
7767 23:14:11.163711 Set Vref, RX VrefLevel [Byte0]: 31
7768 23:14:11.166636 [Byte1]: 31
7769 23:14:11.171180
7770 23:14:11.171597 Set Vref, RX VrefLevel [Byte0]: 32
7771 23:14:11.174264 [Byte1]: 32
7772 23:14:11.178630
7773 23:14:11.179066 Set Vref, RX VrefLevel [Byte0]: 33
7774 23:14:11.181999 [Byte1]: 33
7775 23:14:11.186042
7776 23:14:11.186528 Set Vref, RX VrefLevel [Byte0]: 34
7777 23:14:11.189619 [Byte1]: 34
7778 23:14:11.193636
7779 23:14:11.194018 Set Vref, RX VrefLevel [Byte0]: 35
7780 23:14:11.196959 [Byte1]: 35
7781 23:14:11.201318
7782 23:14:11.201863 Set Vref, RX VrefLevel [Byte0]: 36
7783 23:14:11.204471 [Byte1]: 36
7784 23:14:11.208816
7785 23:14:11.209410 Set Vref, RX VrefLevel [Byte0]: 37
7786 23:14:11.212244 [Byte1]: 37
7787 23:14:11.216335
7788 23:14:11.216900 Set Vref, RX VrefLevel [Byte0]: 38
7789 23:14:11.219622 [Byte1]: 38
7790 23:14:11.224060
7791 23:14:11.224663 Set Vref, RX VrefLevel [Byte0]: 39
7792 23:14:11.227638 [Byte1]: 39
7793 23:14:11.231748
7794 23:14:11.232304 Set Vref, RX VrefLevel [Byte0]: 40
7795 23:14:11.234753 [Byte1]: 40
7796 23:14:11.239363
7797 23:14:11.239920 Set Vref, RX VrefLevel [Byte0]: 41
7798 23:14:11.242365 [Byte1]: 41
7799 23:14:11.246473
7800 23:14:11.246920 Set Vref, RX VrefLevel [Byte0]: 42
7801 23:14:11.249922 [Byte1]: 42
7802 23:14:11.254494
7803 23:14:11.254924 Set Vref, RX VrefLevel [Byte0]: 43
7804 23:14:11.257684 [Byte1]: 43
7805 23:14:11.261897
7806 23:14:11.262326 Set Vref, RX VrefLevel [Byte0]: 44
7807 23:14:11.264985 [Byte1]: 44
7808 23:14:11.269566
7809 23:14:11.270050 Set Vref, RX VrefLevel [Byte0]: 45
7810 23:14:11.272530 [Byte1]: 45
7811 23:14:11.277303
7812 23:14:11.277893 Set Vref, RX VrefLevel [Byte0]: 46
7813 23:14:11.283321 [Byte1]: 46
7814 23:14:11.283886
7815 23:14:11.286941 Set Vref, RX VrefLevel [Byte0]: 47
7816 23:14:11.290224 [Byte1]: 47
7817 23:14:11.290748
7818 23:14:11.293612 Set Vref, RX VrefLevel [Byte0]: 48
7819 23:14:11.296624 [Byte1]: 48
7820 23:14:11.297162
7821 23:14:11.300061 Set Vref, RX VrefLevel [Byte0]: 49
7822 23:14:11.303170 [Byte1]: 49
7823 23:14:11.307742
7824 23:14:11.308436 Set Vref, RX VrefLevel [Byte0]: 50
7825 23:14:11.310516 [Byte1]: 50
7826 23:14:11.315160
7827 23:14:11.315843 Set Vref, RX VrefLevel [Byte0]: 51
7828 23:14:11.318061 [Byte1]: 51
7829 23:14:11.322658
7830 23:14:11.323200 Set Vref, RX VrefLevel [Byte0]: 52
7831 23:14:11.325688 [Byte1]: 52
7832 23:14:11.330170
7833 23:14:11.330720 Set Vref, RX VrefLevel [Byte0]: 53
7834 23:14:11.333492 [Byte1]: 53
7835 23:14:11.337770
7836 23:14:11.338398 Set Vref, RX VrefLevel [Byte0]: 54
7837 23:14:11.340786 [Byte1]: 54
7838 23:14:11.344788
7839 23:14:11.345101 Set Vref, RX VrefLevel [Byte0]: 55
7840 23:14:11.348514 [Byte1]: 55
7841 23:14:11.352507
7842 23:14:11.352772 Set Vref, RX VrefLevel [Byte0]: 56
7843 23:14:11.356128 [Byte1]: 56
7844 23:14:11.360232
7845 23:14:11.360451 Set Vref, RX VrefLevel [Byte0]: 57
7846 23:14:11.363291 [Byte1]: 57
7847 23:14:11.367584
7848 23:14:11.367803 Set Vref, RX VrefLevel [Byte0]: 58
7849 23:14:11.371097 [Byte1]: 58
7850 23:14:11.375270
7851 23:14:11.375479 Set Vref, RX VrefLevel [Byte0]: 59
7852 23:14:11.378774 [Byte1]: 59
7853 23:14:11.382622
7854 23:14:11.382784 Set Vref, RX VrefLevel [Byte0]: 60
7855 23:14:11.385974 [Byte1]: 60
7856 23:14:11.390104
7857 23:14:11.390178 Set Vref, RX VrefLevel [Byte0]: 61
7858 23:14:11.393789 [Byte1]: 61
7859 23:14:11.397687
7860 23:14:11.397763 Set Vref, RX VrefLevel [Byte0]: 62
7861 23:14:11.401367 [Byte1]: 62
7862 23:14:11.405264
7863 23:14:11.405352 Set Vref, RX VrefLevel [Byte0]: 63
7864 23:14:11.409023 [Byte1]: 63
7865 23:14:11.413061
7866 23:14:11.413133 Set Vref, RX VrefLevel [Byte0]: 64
7867 23:14:11.416349 [Byte1]: 64
7868 23:14:11.420322
7869 23:14:11.420396 Set Vref, RX VrefLevel [Byte0]: 65
7870 23:14:11.423949 [Byte1]: 65
7871 23:14:11.428224
7872 23:14:11.428298 Set Vref, RX VrefLevel [Byte0]: 66
7873 23:14:11.431674 [Byte1]: 66
7874 23:14:11.435453
7875 23:14:11.435531 Set Vref, RX VrefLevel [Byte0]: 67
7876 23:14:11.438971 [Byte1]: 67
7877 23:14:11.443454
7878 23:14:11.443528 Set Vref, RX VrefLevel [Byte0]: 68
7879 23:14:11.446778 [Byte1]: 68
7880 23:14:11.450966
7881 23:14:11.451041 Set Vref, RX VrefLevel [Byte0]: 69
7882 23:14:11.454338 [Byte1]: 69
7883 23:14:11.458529
7884 23:14:11.458626 Set Vref, RX VrefLevel [Byte0]: 70
7885 23:14:11.461525 [Byte1]: 70
7886 23:14:11.465740
7887 23:14:11.465811 Set Vref, RX VrefLevel [Byte0]: 71
7888 23:14:11.469223 [Byte1]: 71
7889 23:14:11.473856
7890 23:14:11.473926 Set Vref, RX VrefLevel [Byte0]: 72
7891 23:14:11.477042 [Byte1]: 72
7892 23:14:11.481004
7893 23:14:11.481100 Set Vref, RX VrefLevel [Byte0]: 73
7894 23:14:11.484383 [Byte1]: 73
7895 23:14:11.488955
7896 23:14:11.489027 Final RX Vref Byte 0 = 56 to rank0
7897 23:14:11.491827 Final RX Vref Byte 1 = 62 to rank0
7898 23:14:11.495278 Final RX Vref Byte 0 = 56 to rank1
7899 23:14:11.498620 Final RX Vref Byte 1 = 62 to rank1==
7900 23:14:11.501814 Dram Type= 6, Freq= 0, CH_0, rank 0
7901 23:14:11.508302 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7902 23:14:11.508381 ==
7903 23:14:11.508449 DQS Delay:
7904 23:14:11.508510 DQS0 = 0, DQS1 = 0
7905 23:14:11.511835 DQM Delay:
7906 23:14:11.511908 DQM0 = 133, DQM1 = 127
7907 23:14:11.514952 DQ Delay:
7908 23:14:11.518390 DQ0 =134, DQ1 =136, DQ2 =134, DQ3 =132
7909 23:14:11.521873 DQ4 =132, DQ5 =124, DQ6 =140, DQ7 =138
7910 23:14:11.524868 DQ8 =116, DQ9 =118, DQ10 =130, DQ11 =120
7911 23:14:11.528449 DQ12 =132, DQ13 =132, DQ14 =138, DQ15 =136
7912 23:14:11.528525
7913 23:14:11.528586
7914 23:14:11.528642
7915 23:14:11.531926 [DramC_TX_OE_Calibration] TA2
7916 23:14:11.535108 Original DQ_B0 (3 6) =30, OEN = 27
7917 23:14:11.538184 Original DQ_B1 (3 6) =30, OEN = 27
7918 23:14:11.541866 24, 0x0, End_B0=24 End_B1=24
7919 23:14:11.541969 25, 0x0, End_B0=25 End_B1=25
7920 23:14:11.545110 26, 0x0, End_B0=26 End_B1=26
7921 23:14:11.548549 27, 0x0, End_B0=27 End_B1=27
7922 23:14:11.551671 28, 0x0, End_B0=28 End_B1=28
7923 23:14:11.554760 29, 0x0, End_B0=29 End_B1=29
7924 23:14:11.554839 30, 0x0, End_B0=30 End_B1=30
7925 23:14:11.558095 31, 0x4141, End_B0=30 End_B1=30
7926 23:14:11.561807 Byte0 end_step=30 best_step=27
7927 23:14:11.565009 Byte1 end_step=30 best_step=27
7928 23:14:11.568706 Byte0 TX OE(2T, 0.5T) = (3, 3)
7929 23:14:11.571670 Byte1 TX OE(2T, 0.5T) = (3, 3)
7930 23:14:11.571751
7931 23:14:11.571815
7932 23:14:11.578226 [DQSOSCAuto] RK0, (LSB)MR18= 0x2521, (MSB)MR19= 0x303, tDQSOscB0 = 393 ps tDQSOscB1 = 391 ps
7933 23:14:11.581726 CH0 RK0: MR19=303, MR18=2521
7934 23:14:11.588299 CH0_RK0: MR19=0x303, MR18=0x2521, DQSOSC=391, MR23=63, INC=24, DEC=16
7935 23:14:11.588379
7936 23:14:11.591147 ----->DramcWriteLeveling(PI) begin...
7937 23:14:11.591220 ==
7938 23:14:11.594649 Dram Type= 6, Freq= 0, CH_0, rank 1
7939 23:14:11.598174 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7940 23:14:11.598246 ==
7941 23:14:11.601135 Write leveling (Byte 0): 35 => 35
7942 23:14:11.604530 Write leveling (Byte 1): 30 => 30
7943 23:14:11.608269 DramcWriteLeveling(PI) end<-----
7944 23:14:11.608344
7945 23:14:11.608405 ==
7946 23:14:11.611188 Dram Type= 6, Freq= 0, CH_0, rank 1
7947 23:14:11.614661 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7948 23:14:11.614732 ==
7949 23:14:11.617845 [Gating] SW mode calibration
7950 23:14:11.624737 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7951 23:14:11.631096 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7952 23:14:11.634645 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7953 23:14:11.641265 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7954 23:14:11.644653 1 4 8 | B1->B0 | 2323 2524 | 0 1 | (0 0) (0 0)
7955 23:14:11.647620 1 4 12 | B1->B0 | 2323 2827 | 0 1 | (0 0) (0 0)
7956 23:14:11.654534 1 4 16 | B1->B0 | 3434 3535 | 0 1 | (0 0) (1 1)
7957 23:14:11.657698 1 4 20 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
7958 23:14:11.661232 1 4 24 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7959 23:14:11.664493 1 4 28 | B1->B0 | 3434 3838 | 1 1 | (1 1) (1 1)
7960 23:14:11.671104 1 5 0 | B1->B0 | 3434 3635 | 1 1 | (1 1) (1 1)
7961 23:14:11.674469 1 5 4 | B1->B0 | 3434 3636 | 1 0 | (1 1) (0 0)
7962 23:14:11.677468 1 5 8 | B1->B0 | 3434 3736 | 1 1 | (1 1) (0 0)
7963 23:14:11.684171 1 5 12 | B1->B0 | 3434 3433 | 1 1 | (1 0) (0 1)
7964 23:14:11.687690 1 5 16 | B1->B0 | 2f2f 2525 | 1 0 | (1 0) (1 0)
7965 23:14:11.690750 1 5 20 | B1->B0 | 2323 2a29 | 0 1 | (0 0) (0 0)
7966 23:14:11.697562 1 5 24 | B1->B0 | 2323 2726 | 0 1 | (0 0) (0 0)
7967 23:14:11.701277 1 5 28 | B1->B0 | 2323 2626 | 0 1 | (0 0) (0 0)
7968 23:14:11.704311 1 6 0 | B1->B0 | 2323 2827 | 0 1 | (0 0) (1 1)
7969 23:14:11.710637 1 6 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7970 23:14:11.714314 1 6 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7971 23:14:11.717646 1 6 12 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
7972 23:14:11.723961 1 6 16 | B1->B0 | 3b3b 4645 | 0 1 | (0 0) (0 0)
7973 23:14:11.727681 1 6 20 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
7974 23:14:11.730704 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7975 23:14:11.737144 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7976 23:14:11.740712 1 7 0 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
7977 23:14:11.744032 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7978 23:14:11.750466 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7979 23:14:11.753848 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7980 23:14:11.757292 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7981 23:14:11.763856 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7982 23:14:11.767177 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7983 23:14:11.770489 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7984 23:14:11.777148 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7985 23:14:11.780610 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7986 23:14:11.783500 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7987 23:14:11.790273 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7988 23:14:11.794125 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7989 23:14:11.797455 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7990 23:14:11.803914 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7991 23:14:11.806860 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7992 23:14:11.810394 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7993 23:14:11.816825 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7994 23:14:11.820208 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7995 23:14:11.823872 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7996 23:14:11.830417 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7997 23:14:11.833260 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7998 23:14:11.836988 Total UI for P1: 0, mck2ui 16
7999 23:14:11.840381 best dqsien dly found for B0: ( 1, 9, 14)
8000 23:14:11.843630 Total UI for P1: 0, mck2ui 16
8001 23:14:11.846599 best dqsien dly found for B1: ( 1, 9, 14)
8002 23:14:11.849990 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8003 23:14:11.853293 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8004 23:14:11.853369
8005 23:14:11.856795 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8006 23:14:11.860409 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8007 23:14:11.863318 [Gating] SW calibration Done
8008 23:14:11.863402 ==
8009 23:14:11.866819 Dram Type= 6, Freq= 0, CH_0, rank 1
8010 23:14:11.869854 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8011 23:14:11.869938 ==
8012 23:14:11.873533 RX Vref Scan: 0
8013 23:14:11.873642
8014 23:14:11.876461 RX Vref 0 -> 0, step: 1
8015 23:14:11.876543
8016 23:14:11.876607 RX Delay 0 -> 252, step: 8
8017 23:14:11.883569 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8018 23:14:11.886493 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8019 23:14:11.889967 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8020 23:14:11.892988 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8021 23:14:11.896968 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8022 23:14:11.903066 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8023 23:14:11.906822 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8024 23:14:11.910123 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8025 23:14:11.912910 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8026 23:14:11.916595 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8027 23:14:11.922830 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8028 23:14:11.926626 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8029 23:14:11.930081 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8030 23:14:11.933000 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8031 23:14:11.936502 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8032 23:14:11.942991 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8033 23:14:11.943076 ==
8034 23:14:11.946568 Dram Type= 6, Freq= 0, CH_0, rank 1
8035 23:14:11.949602 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8036 23:14:11.949688 ==
8037 23:14:11.949751 DQS Delay:
8038 23:14:11.953306 DQS0 = 0, DQS1 = 0
8039 23:14:11.953401 DQM Delay:
8040 23:14:11.956707 DQM0 = 137, DQM1 = 128
8041 23:14:11.956778 DQ Delay:
8042 23:14:11.959550 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
8043 23:14:11.963245 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8044 23:14:11.966393 DQ8 =119, DQ9 =119, DQ10 =127, DQ11 =119
8045 23:14:11.969636 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8046 23:14:11.969733
8047 23:14:11.969816
8048 23:14:11.972921 ==
8049 23:14:11.976423 Dram Type= 6, Freq= 0, CH_0, rank 1
8050 23:14:11.979447 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8051 23:14:11.979520 ==
8052 23:14:11.979582
8053 23:14:11.979639
8054 23:14:11.982803 TX Vref Scan disable
8055 23:14:11.982875 == TX Byte 0 ==
8056 23:14:11.986370 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8057 23:14:11.993079 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8058 23:14:11.993162 == TX Byte 1 ==
8059 23:14:11.996391 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8060 23:14:12.002873 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8061 23:14:12.002954 ==
8062 23:14:12.006306 Dram Type= 6, Freq= 0, CH_0, rank 1
8063 23:14:12.009847 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8064 23:14:12.009928 ==
8065 23:14:12.023456
8066 23:14:12.026442 TX Vref early break, caculate TX vref
8067 23:14:12.030110 TX Vref=16, minBit 3, minWin=23, winSum=386
8068 23:14:12.032988 TX Vref=18, minBit 1, minWin=23, winSum=396
8069 23:14:12.036577 TX Vref=20, minBit 1, minWin=24, winSum=405
8070 23:14:12.040099 TX Vref=22, minBit 1, minWin=24, winSum=412
8071 23:14:12.043749 TX Vref=24, minBit 3, minWin=25, winSum=422
8072 23:14:12.050211 TX Vref=26, minBit 1, minWin=25, winSum=426
8073 23:14:12.053173 TX Vref=28, minBit 0, minWin=25, winSum=422
8074 23:14:12.056694 TX Vref=30, minBit 0, minWin=25, winSum=414
8075 23:14:12.059724 TX Vref=32, minBit 4, minWin=24, winSum=409
8076 23:14:12.063148 TX Vref=34, minBit 0, minWin=24, winSum=398
8077 23:14:12.069806 [TxChooseVref] Worse bit 1, Min win 25, Win sum 426, Final Vref 26
8078 23:14:12.069888
8079 23:14:12.073356 Final TX Range 0 Vref 26
8080 23:14:12.073437
8081 23:14:12.073501 ==
8082 23:14:12.076723 Dram Type= 6, Freq= 0, CH_0, rank 1
8083 23:14:12.079529 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8084 23:14:12.079609 ==
8085 23:14:12.079708
8086 23:14:12.079767
8087 23:14:12.083134 TX Vref Scan disable
8088 23:14:12.089798 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8089 23:14:12.089879 == TX Byte 0 ==
8090 23:14:12.093208 u2DelayCellOfst[0]=13 cells (4 PI)
8091 23:14:12.096334 u2DelayCellOfst[1]=13 cells (4 PI)
8092 23:14:12.099857 u2DelayCellOfst[2]=10 cells (3 PI)
8093 23:14:12.103170 u2DelayCellOfst[3]=6 cells (2 PI)
8094 23:14:12.106651 u2DelayCellOfst[4]=6 cells (2 PI)
8095 23:14:12.109617 u2DelayCellOfst[5]=0 cells (0 PI)
8096 23:14:12.109712 u2DelayCellOfst[6]=13 cells (4 PI)
8097 23:14:12.113005 u2DelayCellOfst[7]=13 cells (4 PI)
8098 23:14:12.119506 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8099 23:14:12.123080 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8100 23:14:12.123182 == TX Byte 1 ==
8101 23:14:12.126392 u2DelayCellOfst[8]=0 cells (0 PI)
8102 23:14:12.129714 u2DelayCellOfst[9]=0 cells (0 PI)
8103 23:14:12.132983 u2DelayCellOfst[10]=6 cells (2 PI)
8104 23:14:12.136144 u2DelayCellOfst[11]=3 cells (1 PI)
8105 23:14:12.139631 u2DelayCellOfst[12]=10 cells (3 PI)
8106 23:14:12.142711 u2DelayCellOfst[13]=13 cells (4 PI)
8107 23:14:12.146127 u2DelayCellOfst[14]=16 cells (5 PI)
8108 23:14:12.149256 u2DelayCellOfst[15]=10 cells (3 PI)
8109 23:14:12.152726 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8110 23:14:12.159524 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8111 23:14:12.159607 DramC Write-DBI on
8112 23:14:12.159671 ==
8113 23:14:12.162533 Dram Type= 6, Freq= 0, CH_0, rank 1
8114 23:14:12.165946 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8115 23:14:12.168925 ==
8116 23:14:12.169003
8117 23:14:12.169065
8118 23:14:12.169125 TX Vref Scan disable
8119 23:14:12.172747 == TX Byte 0 ==
8120 23:14:12.176330 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
8121 23:14:12.179100 == TX Byte 1 ==
8122 23:14:12.182544 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8123 23:14:12.186070 DramC Write-DBI off
8124 23:14:12.186170
8125 23:14:12.186261 [DATLAT]
8126 23:14:12.186323 Freq=1600, CH0 RK1
8127 23:14:12.186402
8128 23:14:12.189751 DATLAT Default: 0xf
8129 23:14:12.189850 0, 0xFFFF, sum = 0
8130 23:14:12.192573 1, 0xFFFF, sum = 0
8131 23:14:12.192649 2, 0xFFFF, sum = 0
8132 23:14:12.196045 3, 0xFFFF, sum = 0
8133 23:14:12.199455 4, 0xFFFF, sum = 0
8134 23:14:12.199531 5, 0xFFFF, sum = 0
8135 23:14:12.202992 6, 0xFFFF, sum = 0
8136 23:14:12.203068 7, 0xFFFF, sum = 0
8137 23:14:12.205929 8, 0xFFFF, sum = 0
8138 23:14:12.206003 9, 0xFFFF, sum = 0
8139 23:14:12.209246 10, 0xFFFF, sum = 0
8140 23:14:12.209348 11, 0xFFFF, sum = 0
8141 23:14:12.212445 12, 0xFFFF, sum = 0
8142 23:14:12.212538 13, 0xFFFF, sum = 0
8143 23:14:12.215961 14, 0x0, sum = 1
8144 23:14:12.216064 15, 0x0, sum = 2
8145 23:14:12.219119 16, 0x0, sum = 3
8146 23:14:12.219202 17, 0x0, sum = 4
8147 23:14:12.223113 best_step = 15
8148 23:14:12.223189
8149 23:14:12.223260 ==
8150 23:14:12.225891 Dram Type= 6, Freq= 0, CH_0, rank 1
8151 23:14:12.229353 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8152 23:14:12.229434 ==
8153 23:14:12.229498 RX Vref Scan: 0
8154 23:14:12.232420
8155 23:14:12.232511 RX Vref 0 -> 0, step: 1
8156 23:14:12.232578
8157 23:14:12.235870 RX Delay 19 -> 252, step: 4
8158 23:14:12.239566 iDelay=191, Bit 0, Center 134 (83 ~ 186) 104
8159 23:14:12.246122 iDelay=191, Bit 1, Center 138 (91 ~ 186) 96
8160 23:14:12.249293 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8161 23:14:12.252581 iDelay=191, Bit 3, Center 134 (83 ~ 186) 104
8162 23:14:12.255680 iDelay=191, Bit 4, Center 136 (87 ~ 186) 100
8163 23:14:12.259320 iDelay=191, Bit 5, Center 124 (71 ~ 178) 108
8164 23:14:12.265625 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8165 23:14:12.269217 iDelay=191, Bit 7, Center 140 (91 ~ 190) 100
8166 23:14:12.272132 iDelay=191, Bit 8, Center 120 (71 ~ 170) 100
8167 23:14:12.276111 iDelay=191, Bit 9, Center 116 (67 ~ 166) 100
8168 23:14:12.278820 iDelay=191, Bit 10, Center 128 (75 ~ 182) 108
8169 23:14:12.285406 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8170 23:14:12.288871 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
8171 23:14:12.292480 iDelay=191, Bit 13, Center 134 (83 ~ 186) 104
8172 23:14:12.295418 iDelay=191, Bit 14, Center 134 (83 ~ 186) 104
8173 23:14:12.298716 iDelay=191, Bit 15, Center 134 (87 ~ 182) 96
8174 23:14:12.302356 ==
8175 23:14:12.302437 Dram Type= 6, Freq= 0, CH_0, rank 1
8176 23:14:12.308928 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8177 23:14:12.309011 ==
8178 23:14:12.309075 DQS Delay:
8179 23:14:12.312322 DQS0 = 0, DQS1 = 0
8180 23:14:12.312403 DQM Delay:
8181 23:14:12.315314 DQM0 = 134, DQM1 = 127
8182 23:14:12.315394 DQ Delay:
8183 23:14:12.318719 DQ0 =134, DQ1 =138, DQ2 =130, DQ3 =134
8184 23:14:12.322287 DQ4 =136, DQ5 =124, DQ6 =140, DQ7 =140
8185 23:14:12.325109 DQ8 =120, DQ9 =116, DQ10 =128, DQ11 =118
8186 23:14:12.328739 DQ12 =134, DQ13 =134, DQ14 =134, DQ15 =134
8187 23:14:12.328819
8188 23:14:12.328899
8189 23:14:12.328973
8190 23:14:12.331808 [DramC_TX_OE_Calibration] TA2
8191 23:14:12.335316 Original DQ_B0 (3 6) =30, OEN = 27
8192 23:14:12.338468 Original DQ_B1 (3 6) =30, OEN = 27
8193 23:14:12.342110 24, 0x0, End_B0=24 End_B1=24
8194 23:14:12.345249 25, 0x0, End_B0=25 End_B1=25
8195 23:14:12.345332 26, 0x0, End_B0=26 End_B1=26
8196 23:14:12.348935 27, 0x0, End_B0=27 End_B1=27
8197 23:14:12.351778 28, 0x0, End_B0=28 End_B1=28
8198 23:14:12.355304 29, 0x0, End_B0=29 End_B1=29
8199 23:14:12.355387 30, 0x0, End_B0=30 End_B1=30
8200 23:14:12.358380 31, 0x4545, End_B0=30 End_B1=30
8201 23:14:12.361748 Byte0 end_step=30 best_step=27
8202 23:14:12.364887 Byte1 end_step=30 best_step=27
8203 23:14:12.368694 Byte0 TX OE(2T, 0.5T) = (3, 3)
8204 23:14:12.371789 Byte1 TX OE(2T, 0.5T) = (3, 3)
8205 23:14:12.371871
8206 23:14:12.371934
8207 23:14:12.378494 [DQSOSCAuto] RK1, (LSB)MR18= 0x210a, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 393 ps
8208 23:14:12.381868 CH0 RK1: MR19=303, MR18=210A
8209 23:14:12.388188 CH0_RK1: MR19=0x303, MR18=0x210A, DQSOSC=393, MR23=63, INC=23, DEC=15
8210 23:14:12.391713 [RxdqsGatingPostProcess] freq 1600
8211 23:14:12.398112 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8212 23:14:12.398193 best DQS0 dly(2T, 0.5T) = (1, 1)
8213 23:14:12.401600 best DQS1 dly(2T, 0.5T) = (1, 1)
8214 23:14:12.405220 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8215 23:14:12.408161 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8216 23:14:12.411573 best DQS0 dly(2T, 0.5T) = (1, 1)
8217 23:14:12.415209 best DQS1 dly(2T, 0.5T) = (1, 1)
8218 23:14:12.418698 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8219 23:14:12.421748 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8220 23:14:12.424855 Pre-setting of DQS Precalculation
8221 23:14:12.428383 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8222 23:14:12.428463 ==
8223 23:14:12.431750 Dram Type= 6, Freq= 0, CH_1, rank 0
8224 23:14:12.438364 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8225 23:14:12.438446 ==
8226 23:14:12.441895 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8227 23:14:12.444859 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8228 23:14:12.451860 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8229 23:14:12.458402 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8230 23:14:12.465523 [CA 0] Center 42 (13~72) winsize 60
8231 23:14:12.468512 [CA 1] Center 42 (12~72) winsize 61
8232 23:14:12.471925 [CA 2] Center 39 (9~69) winsize 61
8233 23:14:12.475700 [CA 3] Center 38 (10~67) winsize 58
8234 23:14:12.478778 [CA 4] Center 38 (9~68) winsize 60
8235 23:14:12.481964 [CA 5] Center 37 (8~67) winsize 60
8236 23:14:12.482045
8237 23:14:12.485157 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8238 23:14:12.485238
8239 23:14:12.488633 [CATrainingPosCal] consider 1 rank data
8240 23:14:12.492243 u2DelayCellTimex100 = 290/100 ps
8241 23:14:12.498426 CA0 delay=42 (13~72),Diff = 5 PI (16 cell)
8242 23:14:12.502103 CA1 delay=42 (12~72),Diff = 5 PI (16 cell)
8243 23:14:12.505082 CA2 delay=39 (9~69),Diff = 2 PI (6 cell)
8244 23:14:12.508497 CA3 delay=38 (10~67),Diff = 1 PI (3 cell)
8245 23:14:12.511995 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8246 23:14:12.515034 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8247 23:14:12.515115
8248 23:14:12.518406 CA PerBit enable=1, Macro0, CA PI delay=37
8249 23:14:12.518487
8250 23:14:12.521904 [CBTSetCACLKResult] CA Dly = 37
8251 23:14:12.525554 CS Dly: 11 (0~42)
8252 23:14:12.528414 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8253 23:14:12.531909 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8254 23:14:12.531989 ==
8255 23:14:12.535390 Dram Type= 6, Freq= 0, CH_1, rank 1
8256 23:14:12.541791 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8257 23:14:12.541884 ==
8258 23:14:12.545262 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8259 23:14:12.548180 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8260 23:14:12.555233 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8261 23:14:12.561402 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8262 23:14:12.569144 [CA 0] Center 42 (13~72) winsize 60
8263 23:14:12.572303 [CA 1] Center 42 (13~72) winsize 60
8264 23:14:12.575680 [CA 2] Center 39 (10~69) winsize 60
8265 23:14:12.579248 [CA 3] Center 38 (9~68) winsize 60
8266 23:14:12.582191 [CA 4] Center 39 (9~69) winsize 61
8267 23:14:12.585517 [CA 5] Center 38 (9~68) winsize 60
8268 23:14:12.585639
8269 23:14:12.588764 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8270 23:14:12.588844
8271 23:14:12.592225 [CATrainingPosCal] consider 2 rank data
8272 23:14:12.595628 u2DelayCellTimex100 = 290/100 ps
8273 23:14:12.598924 CA0 delay=42 (13~72),Diff = 4 PI (13 cell)
8274 23:14:12.605834 CA1 delay=42 (13~72),Diff = 4 PI (13 cell)
8275 23:14:12.608849 CA2 delay=39 (10~69),Diff = 1 PI (3 cell)
8276 23:14:12.612393 CA3 delay=38 (10~67),Diff = 0 PI (0 cell)
8277 23:14:12.615850 CA4 delay=38 (9~68),Diff = 0 PI (0 cell)
8278 23:14:12.618694 CA5 delay=38 (9~67),Diff = 0 PI (0 cell)
8279 23:14:12.618774
8280 23:14:12.622236 CA PerBit enable=1, Macro0, CA PI delay=38
8281 23:14:12.622318
8282 23:14:12.625842 [CBTSetCACLKResult] CA Dly = 38
8283 23:14:12.629277 CS Dly: 12 (0~44)
8284 23:14:12.632117 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8285 23:14:12.635683 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8286 23:14:12.635764
8287 23:14:12.639044 ----->DramcWriteLeveling(PI) begin...
8288 23:14:12.639126 ==
8289 23:14:12.642500 Dram Type= 6, Freq= 0, CH_1, rank 0
8290 23:14:12.645468 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8291 23:14:12.648888 ==
8292 23:14:12.652292 Write leveling (Byte 0): 26 => 26
8293 23:14:12.652372 Write leveling (Byte 1): 27 => 27
8294 23:14:12.655353 DramcWriteLeveling(PI) end<-----
8295 23:14:12.655434
8296 23:14:12.655496 ==
8297 23:14:12.658893 Dram Type= 6, Freq= 0, CH_1, rank 0
8298 23:14:12.665525 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8299 23:14:12.665645 ==
8300 23:14:12.669129 [Gating] SW mode calibration
8301 23:14:12.675328 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8302 23:14:12.678628 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8303 23:14:12.685541 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8304 23:14:12.688595 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8305 23:14:12.692242 1 4 8 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
8306 23:14:12.698524 1 4 12 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
8307 23:14:12.701888 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8308 23:14:12.705487 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8309 23:14:12.712282 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8310 23:14:12.715061 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8311 23:14:12.718422 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8312 23:14:12.721874 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8313 23:14:12.728814 1 5 8 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
8314 23:14:12.731996 1 5 12 | B1->B0 | 2a2a 2323 | 1 0 | (1 0) (1 0)
8315 23:14:12.735410 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
8316 23:14:12.741714 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8317 23:14:12.745401 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8318 23:14:12.748583 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8319 23:14:12.755150 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8320 23:14:12.758650 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8321 23:14:12.761682 1 6 8 | B1->B0 | 2929 3f3f | 0 0 | (0 0) (0 0)
8322 23:14:12.768795 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8323 23:14:12.771736 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8324 23:14:12.775451 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8325 23:14:12.782255 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8326 23:14:12.785462 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8327 23:14:12.788617 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8328 23:14:12.795194 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8329 23:14:12.798152 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8330 23:14:12.801720 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8331 23:14:12.808444 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8332 23:14:12.811874 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8333 23:14:12.814861 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8334 23:14:12.821585 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8335 23:14:12.825039 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8336 23:14:12.828515 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8337 23:14:12.831691 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8338 23:14:12.838324 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8339 23:14:12.841867 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8340 23:14:12.844843 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8341 23:14:12.851531 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8342 23:14:12.854728 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8343 23:14:12.858033 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8344 23:14:12.864942 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8345 23:14:12.868537 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8346 23:14:12.871534 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8347 23:14:12.878285 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8348 23:14:12.881511 Total UI for P1: 0, mck2ui 16
8349 23:14:12.885004 best dqsien dly found for B0: ( 1, 9, 10)
8350 23:14:12.885111 Total UI for P1: 0, mck2ui 16
8351 23:14:12.891149 best dqsien dly found for B1: ( 1, 9, 10)
8352 23:14:12.894656 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8353 23:14:12.898105 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8354 23:14:12.898181
8355 23:14:12.901172 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8356 23:14:12.904314 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8357 23:14:12.907635 [Gating] SW calibration Done
8358 23:14:12.907713 ==
8359 23:14:12.911165 Dram Type= 6, Freq= 0, CH_1, rank 0
8360 23:14:12.914666 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8361 23:14:12.914744 ==
8362 23:14:12.917551 RX Vref Scan: 0
8363 23:14:12.917694
8364 23:14:12.921240 RX Vref 0 -> 0, step: 1
8365 23:14:12.921340
8366 23:14:12.921429 RX Delay 0 -> 252, step: 8
8367 23:14:12.927978 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8368 23:14:12.931027 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8369 23:14:12.934358 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8370 23:14:12.937582 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8371 23:14:12.940832 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8372 23:14:12.944487 iDelay=200, Bit 5, Center 151 (104 ~ 199) 96
8373 23:14:12.951152 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8374 23:14:12.954771 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8375 23:14:12.957509 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
8376 23:14:12.960919 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8377 23:14:12.964245 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8378 23:14:12.971041 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8379 23:14:12.974000 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8380 23:14:12.977502 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8381 23:14:12.980961 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8382 23:14:12.987329 iDelay=200, Bit 15, Center 147 (96 ~ 199) 104
8383 23:14:12.987433 ==
8384 23:14:12.991295 Dram Type= 6, Freq= 0, CH_1, rank 0
8385 23:14:12.994243 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8386 23:14:12.994318 ==
8387 23:14:12.994380 DQS Delay:
8388 23:14:12.997718 DQS0 = 0, DQS1 = 0
8389 23:14:12.997820 DQM Delay:
8390 23:14:13.000681 DQM0 = 137, DQM1 = 133
8391 23:14:13.000779 DQ Delay:
8392 23:14:13.004209 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8393 23:14:13.007669 DQ4 =131, DQ5 =151, DQ6 =147, DQ7 =135
8394 23:14:13.010666 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =127
8395 23:14:13.014117 DQ12 =139, DQ13 =143, DQ14 =139, DQ15 =147
8396 23:14:13.014220
8397 23:14:13.014311
8398 23:14:13.017250 ==
8399 23:14:13.017360 Dram Type= 6, Freq= 0, CH_1, rank 0
8400 23:14:13.023986 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8401 23:14:13.024096 ==
8402 23:14:13.024188
8403 23:14:13.024275
8404 23:14:13.027434 TX Vref Scan disable
8405 23:14:13.027532 == TX Byte 0 ==
8406 23:14:13.031025 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8407 23:14:13.037466 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8408 23:14:13.037570 == TX Byte 1 ==
8409 23:14:13.040449 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8410 23:14:13.047330 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8411 23:14:13.047445 ==
8412 23:14:13.050627 Dram Type= 6, Freq= 0, CH_1, rank 0
8413 23:14:13.053876 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8414 23:14:13.053957 ==
8415 23:14:13.067254
8416 23:14:13.070738 TX Vref early break, caculate TX vref
8417 23:14:13.074171 TX Vref=16, minBit 6, minWin=22, winSum=378
8418 23:14:13.077504 TX Vref=18, minBit 0, minWin=23, winSum=389
8419 23:14:13.080908 TX Vref=20, minBit 0, minWin=24, winSum=400
8420 23:14:13.083872 TX Vref=22, minBit 1, minWin=24, winSum=405
8421 23:14:13.087482 TX Vref=24, minBit 0, minWin=25, winSum=415
8422 23:14:13.093870 TX Vref=26, minBit 0, minWin=26, winSum=425
8423 23:14:13.097110 TX Vref=28, minBit 0, minWin=25, winSum=425
8424 23:14:13.100553 TX Vref=30, minBit 0, minWin=25, winSum=423
8425 23:14:13.104058 TX Vref=32, minBit 6, minWin=24, winSum=413
8426 23:14:13.107623 TX Vref=34, minBit 0, minWin=24, winSum=405
8427 23:14:13.110651 TX Vref=36, minBit 0, minWin=23, winSum=391
8428 23:14:13.116913 [TxChooseVref] Worse bit 0, Min win 26, Win sum 425, Final Vref 26
8429 23:14:13.117019
8430 23:14:13.120617 Final TX Range 0 Vref 26
8431 23:14:13.120719
8432 23:14:13.120812 ==
8433 23:14:13.123600 Dram Type= 6, Freq= 0, CH_1, rank 0
8434 23:14:13.126969 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8435 23:14:13.127070 ==
8436 23:14:13.127162
8437 23:14:13.127248
8438 23:14:13.130572 TX Vref Scan disable
8439 23:14:13.136938 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8440 23:14:13.137020 == TX Byte 0 ==
8441 23:14:13.140382 u2DelayCellOfst[0]=13 cells (4 PI)
8442 23:14:13.143923 u2DelayCellOfst[1]=10 cells (3 PI)
8443 23:14:13.146936 u2DelayCellOfst[2]=0 cells (0 PI)
8444 23:14:13.150446 u2DelayCellOfst[3]=6 cells (2 PI)
8445 23:14:13.154067 u2DelayCellOfst[4]=6 cells (2 PI)
8446 23:14:13.157363 u2DelayCellOfst[5]=16 cells (5 PI)
8447 23:14:13.160842 u2DelayCellOfst[6]=16 cells (5 PI)
8448 23:14:13.163552 u2DelayCellOfst[7]=3 cells (1 PI)
8449 23:14:13.167289 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8450 23:14:13.170603 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8451 23:14:13.173883 == TX Byte 1 ==
8452 23:14:13.173989 u2DelayCellOfst[8]=0 cells (0 PI)
8453 23:14:13.176911 u2DelayCellOfst[9]=3 cells (1 PI)
8454 23:14:13.180322 u2DelayCellOfst[10]=13 cells (4 PI)
8455 23:14:13.183817 u2DelayCellOfst[11]=3 cells (1 PI)
8456 23:14:13.186754 u2DelayCellOfst[12]=13 cells (4 PI)
8457 23:14:13.190244 u2DelayCellOfst[13]=16 cells (5 PI)
8458 23:14:13.193821 u2DelayCellOfst[14]=16 cells (5 PI)
8459 23:14:13.196688 u2DelayCellOfst[15]=16 cells (5 PI)
8460 23:14:13.200258 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8461 23:14:13.206913 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8462 23:14:13.206994 DramC Write-DBI on
8463 23:14:13.207058 ==
8464 23:14:13.210529 Dram Type= 6, Freq= 0, CH_1, rank 0
8465 23:14:13.217039 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8466 23:14:13.217142 ==
8467 23:14:13.217232
8468 23:14:13.217322
8469 23:14:13.217407 TX Vref Scan disable
8470 23:14:13.220668 == TX Byte 0 ==
8471 23:14:13.223502 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8472 23:14:13.227000 == TX Byte 1 ==
8473 23:14:13.230485 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8474 23:14:13.233831 DramC Write-DBI off
8475 23:14:13.233938
8476 23:14:13.234048 [DATLAT]
8477 23:14:13.234144 Freq=1600, CH1 RK0
8478 23:14:13.234235
8479 23:14:13.237359 DATLAT Default: 0xf
8480 23:14:13.237436 0, 0xFFFF, sum = 0
8481 23:14:13.240574 1, 0xFFFF, sum = 0
8482 23:14:13.243781 2, 0xFFFF, sum = 0
8483 23:14:13.243857 3, 0xFFFF, sum = 0
8484 23:14:13.246906 4, 0xFFFF, sum = 0
8485 23:14:13.246980 5, 0xFFFF, sum = 0
8486 23:14:13.250424 6, 0xFFFF, sum = 0
8487 23:14:13.250501 7, 0xFFFF, sum = 0
8488 23:14:13.253394 8, 0xFFFF, sum = 0
8489 23:14:13.253499 9, 0xFFFF, sum = 0
8490 23:14:13.257141 10, 0xFFFF, sum = 0
8491 23:14:13.257217 11, 0xFFFF, sum = 0
8492 23:14:13.260482 12, 0xFFFF, sum = 0
8493 23:14:13.260584 13, 0xFFFF, sum = 0
8494 23:14:13.263853 14, 0x0, sum = 1
8495 23:14:13.263951 15, 0x0, sum = 2
8496 23:14:13.266832 16, 0x0, sum = 3
8497 23:14:13.266907 17, 0x0, sum = 4
8498 23:14:13.270283 best_step = 15
8499 23:14:13.270358
8500 23:14:13.270425 ==
8501 23:14:13.273534 Dram Type= 6, Freq= 0, CH_1, rank 0
8502 23:14:13.276787 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8503 23:14:13.276862 ==
8504 23:14:13.280100 RX Vref Scan: 1
8505 23:14:13.280201
8506 23:14:13.280292 Set Vref Range= 24 -> 127
8507 23:14:13.280378
8508 23:14:13.283216 RX Vref 24 -> 127, step: 1
8509 23:14:13.283321
8510 23:14:13.286576 RX Delay 27 -> 252, step: 4
8511 23:14:13.286678
8512 23:14:13.290331 Set Vref, RX VrefLevel [Byte0]: 24
8513 23:14:13.293193 [Byte1]: 24
8514 23:14:13.293292
8515 23:14:13.296496 Set Vref, RX VrefLevel [Byte0]: 25
8516 23:14:13.300184 [Byte1]: 25
8517 23:14:13.300286
8518 23:14:13.303664 Set Vref, RX VrefLevel [Byte0]: 26
8519 23:14:13.306402 [Byte1]: 26
8520 23:14:13.310571
8521 23:14:13.310670 Set Vref, RX VrefLevel [Byte0]: 27
8522 23:14:13.313871 [Byte1]: 27
8523 23:14:13.317968
8524 23:14:13.318067 Set Vref, RX VrefLevel [Byte0]: 28
8525 23:14:13.321342 [Byte1]: 28
8526 23:14:13.325483
8527 23:14:13.325588 Set Vref, RX VrefLevel [Byte0]: 29
8528 23:14:13.329007 [Byte1]: 29
8529 23:14:13.333032
8530 23:14:13.333136 Set Vref, RX VrefLevel [Byte0]: 30
8531 23:14:13.336851 [Byte1]: 30
8532 23:14:13.340814
8533 23:14:13.340915 Set Vref, RX VrefLevel [Byte0]: 31
8534 23:14:13.343855 [Byte1]: 31
8535 23:14:13.348342
8536 23:14:13.348419 Set Vref, RX VrefLevel [Byte0]: 32
8537 23:14:13.351780 [Byte1]: 32
8538 23:14:13.356003
8539 23:14:13.356106 Set Vref, RX VrefLevel [Byte0]: 33
8540 23:14:13.359279 [Byte1]: 33
8541 23:14:13.363227
8542 23:14:13.363302 Set Vref, RX VrefLevel [Byte0]: 34
8543 23:14:13.366626 [Byte1]: 34
8544 23:14:13.370905
8545 23:14:13.370978 Set Vref, RX VrefLevel [Byte0]: 35
8546 23:14:13.374218 [Byte1]: 35
8547 23:14:13.378386
8548 23:14:13.378461 Set Vref, RX VrefLevel [Byte0]: 36
8549 23:14:13.381985 [Byte1]: 36
8550 23:14:13.386279
8551 23:14:13.386356 Set Vref, RX VrefLevel [Byte0]: 37
8552 23:14:13.389464 [Byte1]: 37
8553 23:14:13.393531
8554 23:14:13.393660 Set Vref, RX VrefLevel [Byte0]: 38
8555 23:14:13.396921 [Byte1]: 38
8556 23:14:13.401240
8557 23:14:13.401342 Set Vref, RX VrefLevel [Byte0]: 39
8558 23:14:13.404438 [Byte1]: 39
8559 23:14:13.408328
8560 23:14:13.408439 Set Vref, RX VrefLevel [Byte0]: 40
8561 23:14:13.411892 [Byte1]: 40
8562 23:14:13.416061
8563 23:14:13.416160 Set Vref, RX VrefLevel [Byte0]: 41
8564 23:14:13.419495 [Byte1]: 41
8565 23:14:13.423947
8566 23:14:13.424053 Set Vref, RX VrefLevel [Byte0]: 42
8567 23:14:13.426812 [Byte1]: 42
8568 23:14:13.430921
8569 23:14:13.430994 Set Vref, RX VrefLevel [Byte0]: 43
8570 23:14:13.434407 [Byte1]: 43
8571 23:14:13.438407
8572 23:14:13.438495 Set Vref, RX VrefLevel [Byte0]: 44
8573 23:14:13.441814 [Byte1]: 44
8574 23:14:13.446256
8575 23:14:13.446336 Set Vref, RX VrefLevel [Byte0]: 45
8576 23:14:13.449745 [Byte1]: 45
8577 23:14:13.453958
8578 23:14:13.454043 Set Vref, RX VrefLevel [Byte0]: 46
8579 23:14:13.456852 [Byte1]: 46
8580 23:14:13.461261
8581 23:14:13.461359 Set Vref, RX VrefLevel [Byte0]: 47
8582 23:14:13.464474 [Byte1]: 47
8583 23:14:13.468990
8584 23:14:13.469063 Set Vref, RX VrefLevel [Byte0]: 48
8585 23:14:13.472229 [Byte1]: 48
8586 23:14:13.476651
8587 23:14:13.476764 Set Vref, RX VrefLevel [Byte0]: 49
8588 23:14:13.479650 [Byte1]: 49
8589 23:14:13.483933
8590 23:14:13.484035 Set Vref, RX VrefLevel [Byte0]: 50
8591 23:14:13.487210 [Byte1]: 50
8592 23:14:13.491440
8593 23:14:13.491519 Set Vref, RX VrefLevel [Byte0]: 51
8594 23:14:13.494817 [Byte1]: 51
8595 23:14:13.498817
8596 23:14:13.498889 Set Vref, RX VrefLevel [Byte0]: 52
8597 23:14:13.502367 [Byte1]: 52
8598 23:14:13.506396
8599 23:14:13.506498 Set Vref, RX VrefLevel [Byte0]: 53
8600 23:14:13.509870 [Byte1]: 53
8601 23:14:13.514162
8602 23:14:13.514235 Set Vref, RX VrefLevel [Byte0]: 54
8603 23:14:13.517543 [Byte1]: 54
8604 23:14:13.521750
8605 23:14:13.521828 Set Vref, RX VrefLevel [Byte0]: 55
8606 23:14:13.525474 [Byte1]: 55
8607 23:14:13.529138
8608 23:14:13.529236 Set Vref, RX VrefLevel [Byte0]: 56
8609 23:14:13.532508 [Byte1]: 56
8610 23:14:13.536702
8611 23:14:13.536801 Set Vref, RX VrefLevel [Byte0]: 57
8612 23:14:13.539783 [Byte1]: 57
8613 23:14:13.543916
8614 23:14:13.544020 Set Vref, RX VrefLevel [Byte0]: 58
8615 23:14:13.547505 [Byte1]: 58
8616 23:14:13.551769
8617 23:14:13.551871 Set Vref, RX VrefLevel [Byte0]: 59
8618 23:14:13.555171 [Byte1]: 59
8619 23:14:13.559174
8620 23:14:13.559247 Set Vref, RX VrefLevel [Byte0]: 60
8621 23:14:13.562473 [Byte1]: 60
8622 23:14:13.566621
8623 23:14:13.566720 Set Vref, RX VrefLevel [Byte0]: 61
8624 23:14:13.570236 [Byte1]: 61
8625 23:14:13.574197
8626 23:14:13.574271 Set Vref, RX VrefLevel [Byte0]: 62
8627 23:14:13.577721 [Byte1]: 62
8628 23:14:13.581539
8629 23:14:13.581677 Set Vref, RX VrefLevel [Byte0]: 63
8630 23:14:13.585349 [Byte1]: 63
8631 23:14:13.589547
8632 23:14:13.589689 Set Vref, RX VrefLevel [Byte0]: 64
8633 23:14:13.592420 [Byte1]: 64
8634 23:14:13.597103
8635 23:14:13.597203 Set Vref, RX VrefLevel [Byte0]: 65
8636 23:14:13.599947 [Byte1]: 65
8637 23:14:13.604660
8638 23:14:13.604761 Set Vref, RX VrefLevel [Byte0]: 66
8639 23:14:13.607501 [Byte1]: 66
8640 23:14:13.611684
8641 23:14:13.611794 Set Vref, RX VrefLevel [Byte0]: 67
8642 23:14:13.615071 [Byte1]: 67
8643 23:14:13.619979
8644 23:14:13.620054 Set Vref, RX VrefLevel [Byte0]: 68
8645 23:14:13.622755 [Byte1]: 68
8646 23:14:13.627094
8647 23:14:13.627171 Set Vref, RX VrefLevel [Byte0]: 69
8648 23:14:13.630200 [Byte1]: 69
8649 23:14:13.634704
8650 23:14:13.634785 Set Vref, RX VrefLevel [Byte0]: 70
8651 23:14:13.637882 [Byte1]: 70
8652 23:14:13.641945
8653 23:14:13.642052 Set Vref, RX VrefLevel [Byte0]: 71
8654 23:14:13.645593 [Byte1]: 71
8655 23:14:13.649663
8656 23:14:13.649740 Set Vref, RX VrefLevel [Byte0]: 72
8657 23:14:13.652733 [Byte1]: 72
8658 23:14:13.657405
8659 23:14:13.657506 Set Vref, RX VrefLevel [Byte0]: 73
8660 23:14:13.660301 [Byte1]: 73
8661 23:14:13.664837
8662 23:14:13.664943 Set Vref, RX VrefLevel [Byte0]: 74
8663 23:14:13.667836 [Byte1]: 74
8664 23:14:13.672413
8665 23:14:13.672490 Set Vref, RX VrefLevel [Byte0]: 75
8666 23:14:13.675396 [Byte1]: 75
8667 23:14:13.679534
8668 23:14:13.679624 Set Vref, RX VrefLevel [Byte0]: 76
8669 23:14:13.682794 [Byte1]: 76
8670 23:14:13.687322
8671 23:14:13.687398 Final RX Vref Byte 0 = 56 to rank0
8672 23:14:13.690853 Final RX Vref Byte 1 = 56 to rank0
8673 23:14:13.693983 Final RX Vref Byte 0 = 56 to rank1
8674 23:14:13.697181 Final RX Vref Byte 1 = 56 to rank1==
8675 23:14:13.700653 Dram Type= 6, Freq= 0, CH_1, rank 0
8676 23:14:13.707133 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8677 23:14:13.707236 ==
8678 23:14:13.707326 DQS Delay:
8679 23:14:13.707416 DQS0 = 0, DQS1 = 0
8680 23:14:13.710673 DQM Delay:
8681 23:14:13.710769 DQM0 = 134, DQM1 = 131
8682 23:14:13.714176 DQ Delay:
8683 23:14:13.717076 DQ0 =140, DQ1 =128, DQ2 =124, DQ3 =130
8684 23:14:13.720112 DQ4 =132, DQ5 =144, DQ6 =142, DQ7 =132
8685 23:14:13.723599 DQ8 =116, DQ9 =122, DQ10 =132, DQ11 =122
8686 23:14:13.727096 DQ12 =140, DQ13 =140, DQ14 =140, DQ15 =140
8687 23:14:13.727194
8688 23:14:13.727291
8689 23:14:13.727379
8690 23:14:13.730435 [DramC_TX_OE_Calibration] TA2
8691 23:14:13.733866 Original DQ_B0 (3 6) =30, OEN = 27
8692 23:14:13.736846 Original DQ_B1 (3 6) =30, OEN = 27
8693 23:14:13.740285 24, 0x0, End_B0=24 End_B1=24
8694 23:14:13.740391 25, 0x0, End_B0=25 End_B1=25
8695 23:14:13.743704 26, 0x0, End_B0=26 End_B1=26
8696 23:14:13.747007 27, 0x0, End_B0=27 End_B1=27
8697 23:14:13.750435 28, 0x0, End_B0=28 End_B1=28
8698 23:14:13.753998 29, 0x0, End_B0=29 End_B1=29
8699 23:14:13.754073 30, 0x0, End_B0=30 End_B1=30
8700 23:14:13.756881 31, 0x4545, End_B0=30 End_B1=30
8701 23:14:13.760470 Byte0 end_step=30 best_step=27
8702 23:14:13.763926 Byte1 end_step=30 best_step=27
8703 23:14:13.767196 Byte0 TX OE(2T, 0.5T) = (3, 3)
8704 23:14:13.767304 Byte1 TX OE(2T, 0.5T) = (3, 3)
8705 23:14:13.770466
8706 23:14:13.770570
8707 23:14:13.777309 [DQSOSCAuto] RK0, (LSB)MR18= 0x1623, (MSB)MR19= 0x303, tDQSOscB0 = 392 ps tDQSOscB1 = 398 ps
8708 23:14:13.780122 CH1 RK0: MR19=303, MR18=1623
8709 23:14:13.786931 CH1_RK0: MR19=0x303, MR18=0x1623, DQSOSC=392, MR23=63, INC=24, DEC=16
8710 23:14:13.787007
8711 23:14:13.790467 ----->DramcWriteLeveling(PI) begin...
8712 23:14:13.790541 ==
8713 23:14:13.793405 Dram Type= 6, Freq= 0, CH_1, rank 1
8714 23:14:13.796923 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8715 23:14:13.797024 ==
8716 23:14:13.800410 Write leveling (Byte 0): 24 => 24
8717 23:14:13.803798 Write leveling (Byte 1): 29 => 29
8718 23:14:13.806798 DramcWriteLeveling(PI) end<-----
8719 23:14:13.806902
8720 23:14:13.806994 ==
8721 23:14:13.809996 Dram Type= 6, Freq= 0, CH_1, rank 1
8722 23:14:13.813152 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8723 23:14:13.813251 ==
8724 23:14:13.816485 [Gating] SW mode calibration
8725 23:14:13.823494 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8726 23:14:13.830003 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8727 23:14:13.832937 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8728 23:14:13.836512 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8729 23:14:13.842983 1 4 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8730 23:14:13.846266 1 4 12 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
8731 23:14:13.849959 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8732 23:14:13.856252 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8733 23:14:13.859716 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8734 23:14:13.863218 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8735 23:14:13.869703 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8736 23:14:13.873247 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8737 23:14:13.876412 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8738 23:14:13.883148 1 5 12 | B1->B0 | 2323 2c2c | 0 0 | (1 0) (1 0)
8739 23:14:13.886040 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8740 23:14:13.889374 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8741 23:14:13.896004 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8742 23:14:13.899520 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8743 23:14:13.903073 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8744 23:14:13.909183 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8745 23:14:13.912523 1 6 8 | B1->B0 | 3f3f 2323 | 0 0 | (0 0) (0 0)
8746 23:14:13.915828 1 6 12 | B1->B0 | 4545 3a3a | 0 0 | (0 0) (0 0)
8747 23:14:13.922574 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8748 23:14:13.926227 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8749 23:14:13.929169 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8750 23:14:13.936212 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8751 23:14:13.939215 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8752 23:14:13.942937 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8753 23:14:13.949241 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8754 23:14:13.952634 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8755 23:14:13.956335 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8756 23:14:13.962461 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8757 23:14:13.966239 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8758 23:14:13.969203 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8759 23:14:13.975782 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8760 23:14:13.979313 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8761 23:14:13.982683 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8762 23:14:13.985798 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8763 23:14:13.992690 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8764 23:14:13.996248 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8765 23:14:13.999158 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8766 23:14:14.005581 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8767 23:14:14.009096 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8768 23:14:14.012586 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8769 23:14:14.019016 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8770 23:14:14.022527 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8771 23:14:14.025967 Total UI for P1: 0, mck2ui 16
8772 23:14:14.028989 best dqsien dly found for B1: ( 1, 9, 6)
8773 23:14:14.032222 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8774 23:14:14.035781 Total UI for P1: 0, mck2ui 16
8775 23:14:14.039181 best dqsien dly found for B0: ( 1, 9, 10)
8776 23:14:14.042284 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8777 23:14:14.045841 best DQS1 dly(MCK, UI, PI) = (1, 9, 6)
8778 23:14:14.045926
8779 23:14:14.052405 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8780 23:14:14.055403 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 6)
8781 23:14:14.058835 [Gating] SW calibration Done
8782 23:14:14.058920 ==
8783 23:14:14.062321 Dram Type= 6, Freq= 0, CH_1, rank 1
8784 23:14:14.065326 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8785 23:14:14.065421 ==
8786 23:14:14.065519 RX Vref Scan: 0
8787 23:14:14.065664
8788 23:14:14.068701 RX Vref 0 -> 0, step: 1
8789 23:14:14.068801
8790 23:14:14.072228 RX Delay 0 -> 252, step: 8
8791 23:14:14.075747 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8792 23:14:14.079072 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8793 23:14:14.085493 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8794 23:14:14.088975 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8795 23:14:14.092477 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8796 23:14:14.095314 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8797 23:14:14.098854 iDelay=208, Bit 6, Center 143 (88 ~ 199) 112
8798 23:14:14.102057 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8799 23:14:14.108495 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8800 23:14:14.112257 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8801 23:14:14.115319 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8802 23:14:14.118490 iDelay=208, Bit 11, Center 127 (72 ~ 183) 112
8803 23:14:14.125404 iDelay=208, Bit 12, Center 143 (88 ~ 199) 112
8804 23:14:14.128977 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8805 23:14:14.132246 iDelay=208, Bit 14, Center 139 (88 ~ 191) 104
8806 23:14:14.135259 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8807 23:14:14.135333 ==
8808 23:14:14.138574 Dram Type= 6, Freq= 0, CH_1, rank 1
8809 23:14:14.141869 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8810 23:14:14.145240 ==
8811 23:14:14.145340 DQS Delay:
8812 23:14:14.145430 DQS0 = 0, DQS1 = 0
8813 23:14:14.148584 DQM Delay:
8814 23:14:14.148657 DQM0 = 136, DQM1 = 133
8815 23:14:14.152385 DQ Delay:
8816 23:14:14.155845 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =131
8817 23:14:14.158745 DQ4 =131, DQ5 =151, DQ6 =143, DQ7 =135
8818 23:14:14.162268 DQ8 =119, DQ9 =119, DQ10 =135, DQ11 =127
8819 23:14:14.165697 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8820 23:14:14.165786
8821 23:14:14.165849
8822 23:14:14.165907 ==
8823 23:14:14.168821 Dram Type= 6, Freq= 0, CH_1, rank 1
8824 23:14:14.172112 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8825 23:14:14.172211 ==
8826 23:14:14.172300
8827 23:14:14.172396
8828 23:14:14.175213 TX Vref Scan disable
8829 23:14:14.178624 == TX Byte 0 ==
8830 23:14:14.182291 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8831 23:14:14.185247 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8832 23:14:14.188658 == TX Byte 1 ==
8833 23:14:14.192214 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8834 23:14:14.195473 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8835 23:14:14.195549 ==
8836 23:14:14.199163 Dram Type= 6, Freq= 0, CH_1, rank 1
8837 23:14:14.205501 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8838 23:14:14.205645 ==
8839 23:14:14.217108
8840 23:14:14.220425 TX Vref early break, caculate TX vref
8841 23:14:14.223482 TX Vref=16, minBit 0, minWin=23, winSum=384
8842 23:14:14.226785 TX Vref=18, minBit 0, minWin=23, winSum=393
8843 23:14:14.230230 TX Vref=20, minBit 0, minWin=24, winSum=400
8844 23:14:14.233653 TX Vref=22, minBit 0, minWin=24, winSum=410
8845 23:14:14.236705 TX Vref=24, minBit 0, minWin=25, winSum=423
8846 23:14:14.243764 TX Vref=26, minBit 0, minWin=25, winSum=422
8847 23:14:14.246691 TX Vref=28, minBit 6, minWin=25, winSum=431
8848 23:14:14.250103 TX Vref=30, minBit 1, minWin=25, winSum=420
8849 23:14:14.253562 TX Vref=32, minBit 0, minWin=25, winSum=415
8850 23:14:14.256549 TX Vref=34, minBit 1, minWin=24, winSum=404
8851 23:14:14.263601 [TxChooseVref] Worse bit 6, Min win 25, Win sum 431, Final Vref 28
8852 23:14:14.263679
8853 23:14:14.266571 Final TX Range 0 Vref 28
8854 23:14:14.266654
8855 23:14:14.266719 ==
8856 23:14:14.270021 Dram Type= 6, Freq= 0, CH_1, rank 1
8857 23:14:14.273507 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8858 23:14:14.273644 ==
8859 23:14:14.273717
8860 23:14:14.273777
8861 23:14:14.277085 TX Vref Scan disable
8862 23:14:14.283529 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8863 23:14:14.283634 == TX Byte 0 ==
8864 23:14:14.286920 u2DelayCellOfst[0]=16 cells (5 PI)
8865 23:14:14.289844 u2DelayCellOfst[1]=13 cells (4 PI)
8866 23:14:14.293444 u2DelayCellOfst[2]=0 cells (0 PI)
8867 23:14:14.296875 u2DelayCellOfst[3]=6 cells (2 PI)
8868 23:14:14.300304 u2DelayCellOfst[4]=10 cells (3 PI)
8869 23:14:14.303251 u2DelayCellOfst[5]=16 cells (5 PI)
8870 23:14:14.306621 u2DelayCellOfst[6]=16 cells (5 PI)
8871 23:14:14.306694 u2DelayCellOfst[7]=6 cells (2 PI)
8872 23:14:14.313177 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8873 23:14:14.316959 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8874 23:14:14.317060 == TX Byte 1 ==
8875 23:14:14.319885 u2DelayCellOfst[8]=0 cells (0 PI)
8876 23:14:14.323404 u2DelayCellOfst[9]=3 cells (1 PI)
8877 23:14:14.326383 u2DelayCellOfst[10]=10 cells (3 PI)
8878 23:14:14.330173 u2DelayCellOfst[11]=6 cells (2 PI)
8879 23:14:14.333063 u2DelayCellOfst[12]=13 cells (4 PI)
8880 23:14:14.336482 u2DelayCellOfst[13]=16 cells (5 PI)
8881 23:14:14.339929 u2DelayCellOfst[14]=16 cells (5 PI)
8882 23:14:14.343278 u2DelayCellOfst[15]=16 cells (5 PI)
8883 23:14:14.346919 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8884 23:14:14.352876 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8885 23:14:14.352956 DramC Write-DBI on
8886 23:14:14.353038 ==
8887 23:14:14.356347 Dram Type= 6, Freq= 0, CH_1, rank 1
8888 23:14:14.359702 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8889 23:14:14.359789 ==
8890 23:14:14.362930
8891 23:14:14.363003
8892 23:14:14.363076 TX Vref Scan disable
8893 23:14:14.366231 == TX Byte 0 ==
8894 23:14:14.369810 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8895 23:14:14.373181 == TX Byte 1 ==
8896 23:14:14.376564 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8897 23:14:14.376725 DramC Write-DBI off
8898 23:14:14.379581
8899 23:14:14.379668 [DATLAT]
8900 23:14:14.379742 Freq=1600, CH1 RK1
8901 23:14:14.379803
8902 23:14:14.383142 DATLAT Default: 0xf
8903 23:14:14.383230 0, 0xFFFF, sum = 0
8904 23:14:14.386267 1, 0xFFFF, sum = 0
8905 23:14:14.386368 2, 0xFFFF, sum = 0
8906 23:14:14.389748 3, 0xFFFF, sum = 0
8907 23:14:14.389857 4, 0xFFFF, sum = 0
8908 23:14:14.393242 5, 0xFFFF, sum = 0
8909 23:14:14.396220 6, 0xFFFF, sum = 0
8910 23:14:14.396321 7, 0xFFFF, sum = 0
8911 23:14:14.399692 8, 0xFFFF, sum = 0
8912 23:14:14.399792 9, 0xFFFF, sum = 0
8913 23:14:14.403019 10, 0xFFFF, sum = 0
8914 23:14:14.403120 11, 0xFFFF, sum = 0
8915 23:14:14.406599 12, 0xFFFF, sum = 0
8916 23:14:14.406705 13, 0xFFFF, sum = 0
8917 23:14:14.410124 14, 0x0, sum = 1
8918 23:14:14.410231 15, 0x0, sum = 2
8919 23:14:14.413047 16, 0x0, sum = 3
8920 23:14:14.413151 17, 0x0, sum = 4
8921 23:14:14.416583 best_step = 15
8922 23:14:14.416671
8923 23:14:14.416735 ==
8924 23:14:14.419514 Dram Type= 6, Freq= 0, CH_1, rank 1
8925 23:14:14.422841 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8926 23:14:14.422946 ==
8927 23:14:14.423037 RX Vref Scan: 0
8928 23:14:14.425965
8929 23:14:14.426074 RX Vref 0 -> 0, step: 1
8930 23:14:14.426165
8931 23:14:14.429544 RX Delay 19 -> 252, step: 4
8932 23:14:14.433018 iDelay=195, Bit 0, Center 138 (91 ~ 186) 96
8933 23:14:14.439753 iDelay=195, Bit 1, Center 130 (83 ~ 178) 96
8934 23:14:14.443171 iDelay=195, Bit 2, Center 122 (71 ~ 174) 104
8935 23:14:14.446103 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
8936 23:14:14.449561 iDelay=195, Bit 4, Center 130 (83 ~ 178) 96
8937 23:14:14.452931 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
8938 23:14:14.455908 iDelay=195, Bit 6, Center 144 (95 ~ 194) 100
8939 23:14:14.462528 iDelay=195, Bit 7, Center 132 (83 ~ 182) 100
8940 23:14:14.465963 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8941 23:14:14.469520 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8942 23:14:14.472630 iDelay=195, Bit 10, Center 132 (83 ~ 182) 100
8943 23:14:14.476133 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
8944 23:14:14.482796 iDelay=195, Bit 12, Center 140 (87 ~ 194) 108
8945 23:14:14.486055 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
8946 23:14:14.489035 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
8947 23:14:14.492215 iDelay=195, Bit 15, Center 140 (91 ~ 190) 100
8948 23:14:14.492319 ==
8949 23:14:14.495971 Dram Type= 6, Freq= 0, CH_1, rank 1
8950 23:14:14.502237 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8951 23:14:14.502317 ==
8952 23:14:14.502414 DQS Delay:
8953 23:14:14.505568 DQS0 = 0, DQS1 = 0
8954 23:14:14.505691 DQM Delay:
8955 23:14:14.508954 DQM0 = 134, DQM1 = 130
8956 23:14:14.509029 DQ Delay:
8957 23:14:14.512508 DQ0 =138, DQ1 =130, DQ2 =122, DQ3 =130
8958 23:14:14.515947 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =132
8959 23:14:14.519080 DQ8 =116, DQ9 =118, DQ10 =132, DQ11 =124
8960 23:14:14.522549 DQ12 =140, DQ13 =138, DQ14 =136, DQ15 =140
8961 23:14:14.522648
8962 23:14:14.522737
8963 23:14:14.522826
8964 23:14:14.525529 [DramC_TX_OE_Calibration] TA2
8965 23:14:14.529261 Original DQ_B0 (3 6) =30, OEN = 27
8966 23:14:14.532214 Original DQ_B1 (3 6) =30, OEN = 27
8967 23:14:14.535694 24, 0x0, End_B0=24 End_B1=24
8968 23:14:14.535797 25, 0x0, End_B0=25 End_B1=25
8969 23:14:14.539277 26, 0x0, End_B0=26 End_B1=26
8970 23:14:14.542136 27, 0x0, End_B0=27 End_B1=27
8971 23:14:14.545696 28, 0x0, End_B0=28 End_B1=28
8972 23:14:14.548945 29, 0x0, End_B0=29 End_B1=29
8973 23:14:14.549029 30, 0x0, End_B0=30 End_B1=30
8974 23:14:14.552721 31, 0x4141, End_B0=30 End_B1=30
8975 23:14:14.555477 Byte0 end_step=30 best_step=27
8976 23:14:14.559078 Byte1 end_step=30 best_step=27
8977 23:14:14.562592 Byte0 TX OE(2T, 0.5T) = (3, 3)
8978 23:14:14.565709 Byte1 TX OE(2T, 0.5T) = (3, 3)
8979 23:14:14.565782
8980 23:14:14.565860
8981 23:14:14.572451 [DQSOSCAuto] RK1, (LSB)MR18= 0x2106, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 393 ps
8982 23:14:14.575514 CH1 RK1: MR19=303, MR18=2106
8983 23:14:14.582394 CH1_RK1: MR19=0x303, MR18=0x2106, DQSOSC=393, MR23=63, INC=23, DEC=15
8984 23:14:14.585750 [RxdqsGatingPostProcess] freq 1600
8985 23:14:14.588797 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8986 23:14:14.592212 best DQS0 dly(2T, 0.5T) = (1, 1)
8987 23:14:14.595572 best DQS1 dly(2T, 0.5T) = (1, 1)
8988 23:14:14.599171 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8989 23:14:14.602545 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8990 23:14:14.605302 best DQS0 dly(2T, 0.5T) = (1, 1)
8991 23:14:14.608929 best DQS1 dly(2T, 0.5T) = (1, 1)
8992 23:14:14.612030 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8993 23:14:14.615742 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8994 23:14:14.619222 Pre-setting of DQS Precalculation
8995 23:14:14.622082 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8996 23:14:14.629026 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
8997 23:14:14.635392 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8998 23:14:14.638970
8999 23:14:14.639045
9000 23:14:14.639111 [Calibration Summary] 3200 Mbps
9001 23:14:14.642482 CH 0, Rank 0
9002 23:14:14.642581 SW Impedance : PASS
9003 23:14:14.645444 DUTY Scan : NO K
9004 23:14:14.649145 ZQ Calibration : PASS
9005 23:14:14.649226 Jitter Meter : NO K
9006 23:14:14.652207 CBT Training : PASS
9007 23:14:14.655516 Write leveling : PASS
9008 23:14:14.655594 RX DQS gating : PASS
9009 23:14:14.658684 RX DQ/DQS(RDDQC) : PASS
9010 23:14:14.662183 TX DQ/DQS : PASS
9011 23:14:14.662260 RX DATLAT : PASS
9012 23:14:14.665680 RX DQ/DQS(Engine): PASS
9013 23:14:14.668645 TX OE : PASS
9014 23:14:14.668743 All Pass.
9015 23:14:14.668832
9016 23:14:14.668921 CH 0, Rank 1
9017 23:14:14.672192 SW Impedance : PASS
9018 23:14:14.675142 DUTY Scan : NO K
9019 23:14:14.675242 ZQ Calibration : PASS
9020 23:14:14.678610 Jitter Meter : NO K
9021 23:14:14.682150 CBT Training : PASS
9022 23:14:14.682226 Write leveling : PASS
9023 23:14:14.685555 RX DQS gating : PASS
9024 23:14:14.685672 RX DQ/DQS(RDDQC) : PASS
9025 23:14:14.688683 TX DQ/DQS : PASS
9026 23:14:14.691648 RX DATLAT : PASS
9027 23:14:14.691746 RX DQ/DQS(Engine): PASS
9028 23:14:14.694885 TX OE : PASS
9029 23:14:14.694985 All Pass.
9030 23:14:14.695080
9031 23:14:14.698510 CH 1, Rank 0
9032 23:14:14.698584 SW Impedance : PASS
9033 23:14:14.701811 DUTY Scan : NO K
9034 23:14:14.704855 ZQ Calibration : PASS
9035 23:14:14.704965 Jitter Meter : NO K
9036 23:14:14.708232 CBT Training : PASS
9037 23:14:14.711891 Write leveling : PASS
9038 23:14:14.711968 RX DQS gating : PASS
9039 23:14:14.714924 RX DQ/DQS(RDDQC) : PASS
9040 23:14:14.718352 TX DQ/DQS : PASS
9041 23:14:14.718428 RX DATLAT : PASS
9042 23:14:14.721881 RX DQ/DQS(Engine): PASS
9043 23:14:14.724837 TX OE : PASS
9044 23:14:14.724944 All Pass.
9045 23:14:14.725036
9046 23:14:14.725126 CH 1, Rank 1
9047 23:14:14.728242 SW Impedance : PASS
9048 23:14:14.731585 DUTY Scan : NO K
9049 23:14:14.731695 ZQ Calibration : PASS
9050 23:14:14.734925 Jitter Meter : NO K
9051 23:14:14.738368 CBT Training : PASS
9052 23:14:14.738467 Write leveling : PASS
9053 23:14:14.741399 RX DQS gating : PASS
9054 23:14:14.741502 RX DQ/DQS(RDDQC) : PASS
9055 23:14:14.744861 TX DQ/DQS : PASS
9056 23:14:14.748412 RX DATLAT : PASS
9057 23:14:14.748520 RX DQ/DQS(Engine): PASS
9058 23:14:14.751294 TX OE : PASS
9059 23:14:14.751378 All Pass.
9060 23:14:14.751440
9061 23:14:14.754838 DramC Write-DBI on
9062 23:14:14.758447 PER_BANK_REFRESH: Hybrid Mode
9063 23:14:14.758523 TX_TRACKING: ON
9064 23:14:14.768270 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9065 23:14:14.774667 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9066 23:14:14.784836 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9067 23:14:14.787987 [FAST_K] Save calibration result to emmc
9068 23:14:14.788067 sync common calibartion params.
9069 23:14:14.791577 sync cbt_mode0:1, 1:1
9070 23:14:14.794899 dram_init: ddr_geometry: 2
9071 23:14:14.797802 dram_init: ddr_geometry: 2
9072 23:14:14.797879 dram_init: ddr_geometry: 2
9073 23:14:14.801319 0:dram_rank_size:100000000
9074 23:14:14.804813 1:dram_rank_size:100000000
9075 23:14:14.807920 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9076 23:14:14.811176 DFS_SHUFFLE_HW_MODE: ON
9077 23:14:14.814577 dramc_set_vcore_voltage set vcore to 725000
9078 23:14:14.817615 Read voltage for 1600, 0
9079 23:14:14.817717 Vio18 = 0
9080 23:14:14.821154 Vcore = 725000
9081 23:14:14.821267 Vdram = 0
9082 23:14:14.821358 Vddq = 0
9083 23:14:14.821449 Vmddr = 0
9084 23:14:14.824648 switch to 3200 Mbps bootup
9085 23:14:14.827803 [DramcRunTimeConfig]
9086 23:14:14.827905 PHYPLL
9087 23:14:14.831308 DPM_CONTROL_AFTERK: ON
9088 23:14:14.831408 PER_BANK_REFRESH: ON
9089 23:14:14.834221 REFRESH_OVERHEAD_REDUCTION: ON
9090 23:14:14.837537 CMD_PICG_NEW_MODE: OFF
9091 23:14:14.837629 XRTWTW_NEW_MODE: ON
9092 23:14:14.840964 XRTRTR_NEW_MODE: ON
9093 23:14:14.841063 TX_TRACKING: ON
9094 23:14:14.844208 RDSEL_TRACKING: OFF
9095 23:14:14.844310 DQS Precalculation for DVFS: ON
9096 23:14:14.847777 RX_TRACKING: OFF
9097 23:14:14.847855 HW_GATING DBG: ON
9098 23:14:14.850970 ZQCS_ENABLE_LP4: ON
9099 23:14:14.854447 RX_PICG_NEW_MODE: ON
9100 23:14:14.854522 TX_PICG_NEW_MODE: ON
9101 23:14:14.857444 ENABLE_RX_DCM_DPHY: ON
9102 23:14:14.860967 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9103 23:14:14.861043 DUMMY_READ_FOR_TRACKING: OFF
9104 23:14:14.864604 !!! SPM_CONTROL_AFTERK: OFF
9105 23:14:14.867466 !!! SPM could not control APHY
9106 23:14:14.870954 IMPEDANCE_TRACKING: ON
9107 23:14:14.871029 TEMP_SENSOR: ON
9108 23:14:14.874543 HW_SAVE_FOR_SR: OFF
9109 23:14:14.877468 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9110 23:14:14.881161 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9111 23:14:14.881240 Read ODT Tracking: ON
9112 23:14:14.884280 Refresh Rate DeBounce: ON
9113 23:14:14.887897 DFS_NO_QUEUE_FLUSH: ON
9114 23:14:14.890814 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9115 23:14:14.890892 ENABLE_DFS_RUNTIME_MRW: OFF
9116 23:14:14.894387 DDR_RESERVE_NEW_MODE: ON
9117 23:14:14.897398 MR_CBT_SWITCH_FREQ: ON
9118 23:14:14.897507 =========================
9119 23:14:14.917503 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9120 23:14:14.920812 dram_init: ddr_geometry: 2
9121 23:14:14.938947 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9122 23:14:14.942589 dram_init: dram init end (result: 0)
9123 23:14:14.949226 DRAM-K: Full calibration passed in 24419 msecs
9124 23:14:14.951938 MRC: failed to locate region type 0.
9125 23:14:14.952017 DRAM rank0 size:0x100000000,
9126 23:14:14.955508 DRAM rank1 size=0x100000000
9127 23:14:14.965515 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9128 23:14:14.971899 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9129 23:14:14.978500 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9130 23:14:14.985497 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9131 23:14:14.988782 DRAM rank0 size:0x100000000,
9132 23:14:14.991992 DRAM rank1 size=0x100000000
9133 23:14:14.992067 CBMEM:
9134 23:14:14.995484 IMD: root @ 0xfffff000 254 entries.
9135 23:14:14.998520 IMD: root @ 0xffffec00 62 entries.
9136 23:14:15.001968 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9137 23:14:15.008459 WARNING: RO_VPD is uninitialized or empty.
9138 23:14:15.011931 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9139 23:14:15.018681 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9140 23:14:15.031869 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9141 23:14:15.042900 BS: romstage times (exec / console): total (unknown) / 23954 ms
9142 23:14:15.043004
9143 23:14:15.043098
9144 23:14:15.052883 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9145 23:14:15.056378 ARM64: Exception handlers installed.
9146 23:14:15.059464 ARM64: Testing exception
9147 23:14:15.063105 ARM64: Done test exception
9148 23:14:15.063206 Enumerating buses...
9149 23:14:15.066482 Show all devs... Before device enumeration.
9150 23:14:15.069826 Root Device: enabled 1
9151 23:14:15.073088 CPU_CLUSTER: 0: enabled 1
9152 23:14:15.073164 CPU: 00: enabled 1
9153 23:14:15.076428 Compare with tree...
9154 23:14:15.076502 Root Device: enabled 1
9155 23:14:15.079735 CPU_CLUSTER: 0: enabled 1
9156 23:14:15.082770 CPU: 00: enabled 1
9157 23:14:15.082873 Root Device scanning...
9158 23:14:15.086191 scan_static_bus for Root Device
9159 23:14:15.089256 CPU_CLUSTER: 0 enabled
9160 23:14:15.092594 scan_static_bus for Root Device done
9161 23:14:15.096102 scan_bus: bus Root Device finished in 8 msecs
9162 23:14:15.096203 done
9163 23:14:15.102733 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9164 23:14:15.106229 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9165 23:14:15.112827 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9166 23:14:15.116258 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9167 23:14:15.119704 Allocating resources...
9168 23:14:15.122845 Reading resources...
9169 23:14:15.126244 Root Device read_resources bus 0 link: 0
9170 23:14:15.126341 DRAM rank0 size:0x100000000,
9171 23:14:15.129490 DRAM rank1 size=0x100000000
9172 23:14:15.132727 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9173 23:14:15.135884 CPU: 00 missing read_resources
9174 23:14:15.139358 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9175 23:14:15.145896 Root Device read_resources bus 0 link: 0 done
9176 23:14:15.145999 Done reading resources.
9177 23:14:15.152890 Show resources in subtree (Root Device)...After reading.
9178 23:14:15.155846 Root Device child on link 0 CPU_CLUSTER: 0
9179 23:14:15.159320 CPU_CLUSTER: 0 child on link 0 CPU: 00
9180 23:14:15.169225 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9181 23:14:15.169333 CPU: 00
9182 23:14:15.172746 Root Device assign_resources, bus 0 link: 0
9183 23:14:15.176228 CPU_CLUSTER: 0 missing set_resources
9184 23:14:15.179224 Root Device assign_resources, bus 0 link: 0 done
9185 23:14:15.182982 Done setting resources.
9186 23:14:15.189503 Show resources in subtree (Root Device)...After assigning values.
9187 23:14:15.192913 Root Device child on link 0 CPU_CLUSTER: 0
9188 23:14:15.195799 CPU_CLUSTER: 0 child on link 0 CPU: 00
9189 23:14:15.205880 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9190 23:14:15.205958 CPU: 00
9191 23:14:15.209421 Done allocating resources.
9192 23:14:15.212533 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9193 23:14:15.216068 Enabling resources...
9194 23:14:15.216168 done.
9195 23:14:15.222306 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9196 23:14:15.222413 Initializing devices...
9197 23:14:15.225835 Root Device init
9198 23:14:15.225913 init hardware done!
9199 23:14:15.228901 0x00000018: ctrlr->caps
9200 23:14:15.232341 52.000 MHz: ctrlr->f_max
9201 23:14:15.232439 0.400 MHz: ctrlr->f_min
9202 23:14:15.235742 0x40ff8080: ctrlr->voltages
9203 23:14:15.235844 sclk: 390625
9204 23:14:15.238829 Bus Width = 1
9205 23:14:15.238928 sclk: 390625
9206 23:14:15.241910 Bus Width = 1
9207 23:14:15.242007 Early init status = 3
9208 23:14:15.248605 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9209 23:14:15.251655 in-header: 03 fc 00 00 01 00 00 00
9210 23:14:15.251758 in-data: 00
9211 23:14:15.258311 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9212 23:14:15.261727 in-header: 03 fd 00 00 00 00 00 00
9213 23:14:15.265163 in-data:
9214 23:14:15.268115 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9215 23:14:15.272251 in-header: 03 fc 00 00 01 00 00 00
9216 23:14:15.275265 in-data: 00
9217 23:14:15.278105 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9218 23:14:15.283559 in-header: 03 fd 00 00 00 00 00 00
9219 23:14:15.286440 in-data:
9220 23:14:15.290029 [SSUSB] Setting up USB HOST controller...
9221 23:14:15.293438 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9222 23:14:15.296887 [SSUSB] phy power-on done.
9223 23:14:15.299844 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9224 23:14:15.306831 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9225 23:14:15.310258 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9226 23:14:15.316537 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9227 23:14:15.323221 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9228 23:14:15.330245 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9229 23:14:15.336672 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9230 23:14:15.343061 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9231 23:14:15.346280 SPM: binary array size = 0x9dc
9232 23:14:15.349824 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9233 23:14:15.356240 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9234 23:14:15.363184 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9235 23:14:15.366626 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9236 23:14:15.372735 configure_display: Starting display init
9237 23:14:15.406865 anx7625_power_on_init: Init interface.
9238 23:14:15.410233 anx7625_disable_pd_protocol: Disabled PD feature.
9239 23:14:15.413018 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9240 23:14:15.440975 anx7625_start_dp_work: Secure OCM version=00
9241 23:14:15.444450 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9242 23:14:15.459398 sp_tx_get_edid_block: EDID Block = 1
9243 23:14:15.561678 Extracted contents:
9244 23:14:15.565245 header: 00 ff ff ff ff ff ff 00
9245 23:14:15.568011 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9246 23:14:15.571796 version: 01 04
9247 23:14:15.575089 basic params: 95 1f 11 78 0a
9248 23:14:15.578355 chroma info: 76 90 94 55 54 90 27 21 50 54
9249 23:14:15.581510 established: 00 00 00
9250 23:14:15.588271 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9251 23:14:15.591668 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9252 23:14:15.598213 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9253 23:14:15.604675 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9254 23:14:15.611197 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9255 23:14:15.614727 extensions: 00
9256 23:14:15.614804 checksum: fb
9257 23:14:15.614868
9258 23:14:15.618242 Manufacturer: IVO Model 57d Serial Number 0
9259 23:14:15.621215 Made week 0 of 2020
9260 23:14:15.621325 EDID version: 1.4
9261 23:14:15.624854 Digital display
9262 23:14:15.628172 6 bits per primary color channel
9263 23:14:15.628250 DisplayPort interface
9264 23:14:15.631831 Maximum image size: 31 cm x 17 cm
9265 23:14:15.634829 Gamma: 220%
9266 23:14:15.634923 Check DPMS levels
9267 23:14:15.638409 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9268 23:14:15.641287 First detailed timing is preferred timing
9269 23:14:15.645028 Established timings supported:
9270 23:14:15.648322 Standard timings supported:
9271 23:14:15.648424 Detailed timings
9272 23:14:15.654540 Hex of detail: 383680a07038204018303c0035ae10000019
9273 23:14:15.657957 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9274 23:14:15.664751 0780 0798 07c8 0820 hborder 0
9275 23:14:15.668443 0438 043b 0447 0458 vborder 0
9276 23:14:15.668520 -hsync -vsync
9277 23:14:15.671448 Did detailed timing
9278 23:14:15.674611 Hex of detail: 000000000000000000000000000000000000
9279 23:14:15.678154 Manufacturer-specified data, tag 0
9280 23:14:15.684735 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9281 23:14:15.684824 ASCII string: InfoVision
9282 23:14:15.691681 Hex of detail: 000000fe00523134304e574635205248200a
9283 23:14:15.695121 ASCII string: R140NWF5 RH
9284 23:14:15.695222 Checksum
9285 23:14:15.695313 Checksum: 0xfb (valid)
9286 23:14:15.701586 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9287 23:14:15.704936 DSI data_rate: 832800000 bps
9288 23:14:15.708074 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9289 23:14:15.711506 anx7625_parse_edid: pixelclock(138800).
9290 23:14:15.717975 hactive(1920), hsync(48), hfp(24), hbp(88)
9291 23:14:15.721376 vactive(1080), vsync(12), vfp(3), vbp(17)
9292 23:14:15.724316 anx7625_dsi_config: config dsi.
9293 23:14:15.730842 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9294 23:14:15.744007 anx7625_dsi_config: success to config DSI
9295 23:14:15.746969 anx7625_dp_start: MIPI phy setup OK.
9296 23:14:15.750312 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9297 23:14:15.753773 mtk_ddp_mode_set invalid vrefresh 60
9298 23:14:15.757293 main_disp_path_setup
9299 23:14:15.757397 ovl_layer_smi_id_en
9300 23:14:15.760278 ovl_layer_smi_id_en
9301 23:14:15.760369 ccorr_config
9302 23:14:15.760432 aal_config
9303 23:14:15.763452 gamma_config
9304 23:14:15.763558 postmask_config
9305 23:14:15.767468 dither_config
9306 23:14:15.770081 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9307 23:14:15.777222 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9308 23:14:15.780476 Root Device init finished in 551 msecs
9309 23:14:15.780576 CPU_CLUSTER: 0 init
9310 23:14:15.790318 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9311 23:14:15.794038 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9312 23:14:15.797010 APU_MBOX 0x190000b0 = 0x10001
9313 23:14:15.800088 APU_MBOX 0x190001b0 = 0x10001
9314 23:14:15.803634 APU_MBOX 0x190005b0 = 0x10001
9315 23:14:15.806978 APU_MBOX 0x190006b0 = 0x10001
9316 23:14:15.810208 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9317 23:14:15.822680 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9318 23:14:15.835617 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9319 23:14:15.841981 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9320 23:14:15.853303 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9321 23:14:15.862614 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9322 23:14:15.865494 CPU_CLUSTER: 0 init finished in 81 msecs
9323 23:14:15.868792 Devices initialized
9324 23:14:15.872490 Show all devs... After init.
9325 23:14:15.872594 Root Device: enabled 1
9326 23:14:15.875979 CPU_CLUSTER: 0: enabled 1
9327 23:14:15.879197 CPU: 00: enabled 1
9328 23:14:15.882247 BS: BS_DEV_INIT run times (exec / console): 210 / 447 ms
9329 23:14:15.885541 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9330 23:14:15.889025 ELOG: NV offset 0x57f000 size 0x1000
9331 23:14:15.895691 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9332 23:14:15.902610 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9333 23:14:15.905369 ELOG: Event(17) added with size 13 at 2023-12-03 23:12:02 UTC
9334 23:14:15.908904 out: cmd=0x121: 03 db 21 01 00 00 00 00
9335 23:14:15.913027 in-header: 03 03 00 00 2c 00 00 00
9336 23:14:15.926021 in-data: 5c 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9337 23:14:15.933013 ELOG: Event(A1) added with size 10 at 2023-12-03 23:12:02 UTC
9338 23:14:15.939530 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9339 23:14:15.945943 ELOG: Event(A0) added with size 9 at 2023-12-03 23:12:02 UTC
9340 23:14:15.949464 elog_add_boot_reason: Logged dev mode boot
9341 23:14:15.952968 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9342 23:14:15.955987 Finalize devices...
9343 23:14:15.956090 Devices finalized
9344 23:14:15.963003 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9345 23:14:15.966427 Writing coreboot table at 0xffe64000
9346 23:14:15.969382 0. 000000000010a000-0000000000113fff: RAMSTAGE
9347 23:14:15.972687 1. 0000000040000000-00000000400fffff: RAM
9348 23:14:15.976289 2. 0000000040100000-000000004032afff: RAMSTAGE
9349 23:14:15.982875 3. 000000004032b000-00000000545fffff: RAM
9350 23:14:15.986259 4. 0000000054600000-000000005465ffff: BL31
9351 23:14:15.989333 5. 0000000054660000-00000000ffe63fff: RAM
9352 23:14:15.995638 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9353 23:14:15.999436 7. 0000000100000000-000000023fffffff: RAM
9354 23:14:15.999542 Passing 5 GPIOs to payload:
9355 23:14:16.006063 NAME | PORT | POLARITY | VALUE
9356 23:14:16.009328 EC in RW | 0x000000aa | low | undefined
9357 23:14:16.015826 EC interrupt | 0x00000005 | low | undefined
9358 23:14:16.019187 TPM interrupt | 0x000000ab | high | undefined
9359 23:14:16.022597 SD card detect | 0x00000011 | high | undefined
9360 23:14:16.028750 speaker enable | 0x00000093 | high | undefined
9361 23:14:16.032459 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9362 23:14:16.035697 in-header: 03 f9 00 00 02 00 00 00
9363 23:14:16.035799 in-data: 02 00
9364 23:14:16.038800 ADC[4]: Raw value=904726 ID=7
9365 23:14:16.042405 ADC[3]: Raw value=213810 ID=1
9366 23:14:16.042510 RAM Code: 0x71
9367 23:14:16.045573 ADC[6]: Raw value=75332 ID=0
9368 23:14:16.049226 ADC[5]: Raw value=213072 ID=1
9369 23:14:16.049330 SKU Code: 0x1
9370 23:14:16.055697 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 425c
9371 23:14:16.058730 coreboot table: 964 bytes.
9372 23:14:16.062290 IMD ROOT 0. 0xfffff000 0x00001000
9373 23:14:16.065309 IMD SMALL 1. 0xffffe000 0x00001000
9374 23:14:16.068725 RO MCACHE 2. 0xffffc000 0x00001104
9375 23:14:16.072029 CONSOLE 3. 0xfff7c000 0x00080000
9376 23:14:16.075577 FMAP 4. 0xfff7b000 0x00000452
9377 23:14:16.079076 TIME STAMP 5. 0xfff7a000 0x00000910
9378 23:14:16.082032 VBOOT WORK 6. 0xfff66000 0x00014000
9379 23:14:16.085470 RAMOOPS 7. 0xffe66000 0x00100000
9380 23:14:16.088894 COREBOOT 8. 0xffe64000 0x00002000
9381 23:14:16.088993 IMD small region:
9382 23:14:16.092169 IMD ROOT 0. 0xffffec00 0x00000400
9383 23:14:16.095755 VPD 1. 0xffffeb80 0x0000006c
9384 23:14:16.098640 MMC STATUS 2. 0xffffeb60 0x00000004
9385 23:14:16.105847 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9386 23:14:16.105923 Probing TPM: done!
9387 23:14:16.112450 Connected to device vid:did:rid of 1ae0:0028:00
9388 23:14:16.119157 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9389 23:14:16.127032 Initialized TPM device CR50 revision 0
9390 23:14:16.127139 Checking cr50 for pending updates
9391 23:14:16.132158 Reading cr50 TPM mode
9392 23:14:16.140792 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9393 23:14:16.147595 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9394 23:14:16.187423 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9395 23:14:16.191065 Checking segment from ROM address 0x40100000
9396 23:14:16.194409 Checking segment from ROM address 0x4010001c
9397 23:14:16.201302 Loading segment from ROM address 0x40100000
9398 23:14:16.201405 code (compression=0)
9399 23:14:16.207530 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9400 23:14:16.217466 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9401 23:14:16.217571 it's not compressed!
9402 23:14:16.224542 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9403 23:14:16.227738 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9404 23:14:16.248363 Loading segment from ROM address 0x4010001c
9405 23:14:16.248448 Entry Point 0x80000000
9406 23:14:16.251371 Loaded segments
9407 23:14:16.254809 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9408 23:14:16.261254 Jumping to boot code at 0x80000000(0xffe64000)
9409 23:14:16.268302 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9410 23:14:16.274717 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9411 23:14:16.282815 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9412 23:14:16.286149 Checking segment from ROM address 0x40100000
9413 23:14:16.289059 Checking segment from ROM address 0x4010001c
9414 23:14:16.296081 Loading segment from ROM address 0x40100000
9415 23:14:16.296191 code (compression=1)
9416 23:14:16.302434 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9417 23:14:16.312311 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9418 23:14:16.312392 using LZMA
9419 23:14:16.320572 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9420 23:14:16.327504 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9421 23:14:16.330842 Loading segment from ROM address 0x4010001c
9422 23:14:16.330969 Entry Point 0x54601000
9423 23:14:16.334074 Loaded segments
9424 23:14:16.337562 NOTICE: MT8192 bl31_setup
9425 23:14:16.344607 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9426 23:14:16.348114 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9427 23:14:16.351015 WARNING: region 0:
9428 23:14:16.354372 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9429 23:14:16.354449 WARNING: region 1:
9430 23:14:16.360875 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9431 23:14:16.364628 WARNING: region 2:
9432 23:14:16.368079 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9433 23:14:16.371123 WARNING: region 3:
9434 23:14:16.374595 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9435 23:14:16.377868 WARNING: region 4:
9436 23:14:16.384906 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9437 23:14:16.384983 WARNING: region 5:
9438 23:14:16.388007 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9439 23:14:16.391226 WARNING: region 6:
9440 23:14:16.394496 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9441 23:14:16.394600 WARNING: region 7:
9442 23:14:16.401118 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9443 23:14:16.407789 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9444 23:14:16.411290 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9445 23:14:16.414572 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9446 23:14:16.421231 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9447 23:14:16.424569 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9448 23:14:16.428246 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9449 23:14:16.434643 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9450 23:14:16.438115 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9451 23:14:16.441399 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9452 23:14:16.448348 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9453 23:14:16.451253 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9454 23:14:16.454811 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9455 23:14:16.461357 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9456 23:14:16.464796 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9457 23:14:16.471401 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9458 23:14:16.474889 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9459 23:14:16.478164 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9460 23:14:16.484833 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9461 23:14:16.488106 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9462 23:14:16.491835 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9463 23:14:16.498155 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9464 23:14:16.501594 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9465 23:14:16.508061 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9466 23:14:16.511589 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9467 23:14:16.515149 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9468 23:14:16.521453 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9469 23:14:16.525037 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9470 23:14:16.531763 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9471 23:14:16.535119 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9472 23:14:16.538560 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9473 23:14:16.544983 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9474 23:14:16.548443 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9475 23:14:16.551526 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9476 23:14:16.558146 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9477 23:14:16.561653 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9478 23:14:16.565136 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9479 23:14:16.568711 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9480 23:14:16.575082 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9481 23:14:16.578579 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9482 23:14:16.582049 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9483 23:14:16.584975 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9484 23:14:16.588668 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9485 23:14:16.594934 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9486 23:14:16.598600 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9487 23:14:16.602141 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9488 23:14:16.608413 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9489 23:14:16.612020 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9490 23:14:16.615402 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9491 23:14:16.618818 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9492 23:14:16.625241 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9493 23:14:16.628985 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9494 23:14:16.635156 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9495 23:14:16.638936 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9496 23:14:16.645270 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9497 23:14:16.648640 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9498 23:14:16.652187 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9499 23:14:16.658933 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9500 23:14:16.662156 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9501 23:14:16.668481 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9502 23:14:16.671893 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9503 23:14:16.678817 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9504 23:14:16.681936 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9505 23:14:16.685318 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9506 23:14:16.692108 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9507 23:14:16.695406 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9508 23:14:16.702079 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9509 23:14:16.705511 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9510 23:14:16.711816 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9511 23:14:16.715363 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9512 23:14:16.718907 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9513 23:14:16.725298 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9514 23:14:16.728913 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9515 23:14:16.735422 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9516 23:14:16.738870 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9517 23:14:16.745790 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9518 23:14:16.748964 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9519 23:14:16.752416 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9520 23:14:16.758824 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9521 23:14:16.762480 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9522 23:14:16.769172 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9523 23:14:16.772538 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9524 23:14:16.779260 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9525 23:14:16.782660 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9526 23:14:16.785500 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9527 23:14:16.792613 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9528 23:14:16.795554 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9529 23:14:16.802716 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9530 23:14:16.805529 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9531 23:14:16.809251 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9532 23:14:16.815834 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9533 23:14:16.819215 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9534 23:14:16.825713 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9535 23:14:16.829247 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9536 23:14:16.835616 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9537 23:14:16.839069 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9538 23:14:16.846052 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9539 23:14:16.849462 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9540 23:14:16.852848 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9541 23:14:16.856277 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9542 23:14:16.859531 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9543 23:14:16.865949 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9544 23:14:16.869127 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9545 23:14:16.875935 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9546 23:14:16.879092 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9547 23:14:16.882414 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9548 23:14:16.889501 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9549 23:14:16.893015 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9550 23:14:16.899605 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9551 23:14:16.902595 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9552 23:14:16.906114 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9553 23:14:16.912607 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9554 23:14:16.916172 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9555 23:14:16.919696 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9556 23:14:16.926513 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9557 23:14:16.929884 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9558 23:14:16.936566 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9559 23:14:16.939954 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9560 23:14:16.942685 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9561 23:14:16.949802 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9562 23:14:16.952813 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9563 23:14:16.956024 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9564 23:14:16.959716 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9565 23:14:16.963138 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9566 23:14:16.969297 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9567 23:14:16.972621 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9568 23:14:16.979666 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9569 23:14:16.982859 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9570 23:14:16.986251 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9571 23:14:16.992763 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9572 23:14:16.996138 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9573 23:14:16.999655 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9574 23:14:17.006020 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9575 23:14:17.009656 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9576 23:14:17.016094 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9577 23:14:17.019847 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9578 23:14:17.022846 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9579 23:14:17.029911 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9580 23:14:17.032726 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9581 23:14:17.036135 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9582 23:14:17.043135 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9583 23:14:17.046625 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9584 23:14:17.053005 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9585 23:14:17.056492 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9586 23:14:17.059452 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9587 23:14:17.066478 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9588 23:14:17.069433 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9589 23:14:17.076246 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9590 23:14:17.079696 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9591 23:14:17.083074 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9592 23:14:17.089474 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9593 23:14:17.092931 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9594 23:14:17.096258 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9595 23:14:17.103161 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9596 23:14:17.106431 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9597 23:14:17.113193 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9598 23:14:17.116413 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9599 23:14:17.119880 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9600 23:14:17.126492 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9601 23:14:17.129911 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9602 23:14:17.133488 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9603 23:14:17.140075 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9604 23:14:17.143270 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9605 23:14:17.149759 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9606 23:14:17.152993 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9607 23:14:17.156544 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9608 23:14:17.163077 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9609 23:14:17.166541 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9610 23:14:17.172900 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9611 23:14:17.176312 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9612 23:14:17.179843 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9613 23:14:17.186295 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9614 23:14:17.189696 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9615 23:14:17.196441 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9616 23:14:17.199754 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9617 23:14:17.202954 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9618 23:14:17.209922 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9619 23:14:17.212876 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9620 23:14:17.219739 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9621 23:14:17.222915 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9622 23:14:17.226066 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9623 23:14:17.232758 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9624 23:14:17.236315 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9625 23:14:17.239387 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9626 23:14:17.246355 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9627 23:14:17.249505 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9628 23:14:17.256059 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9629 23:14:17.259480 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9630 23:14:17.263032 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9631 23:14:17.269354 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9632 23:14:17.272839 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9633 23:14:17.279745 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9634 23:14:17.283173 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9635 23:14:17.289340 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9636 23:14:17.292972 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9637 23:14:17.296447 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9638 23:14:17.302560 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9639 23:14:17.306387 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9640 23:14:17.312750 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9641 23:14:17.316294 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9642 23:14:17.319219 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9643 23:14:17.326293 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9644 23:14:17.329232 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9645 23:14:17.336089 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9646 23:14:17.339498 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9647 23:14:17.342630 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9648 23:14:17.349333 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9649 23:14:17.352851 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9650 23:14:17.359194 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9651 23:14:17.362518 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9652 23:14:17.369061 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9653 23:14:17.372719 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9654 23:14:17.375692 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9655 23:14:17.382471 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9656 23:14:17.386094 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9657 23:14:17.392271 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9658 23:14:17.395717 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9659 23:14:17.399346 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9660 23:14:17.405828 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9661 23:14:17.409218 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9662 23:14:17.416181 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9663 23:14:17.419277 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9664 23:14:17.422552 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9665 23:14:17.429253 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9666 23:14:17.432884 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9667 23:14:17.438843 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9668 23:14:17.442299 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9669 23:14:17.448747 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9670 23:14:17.452153 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9671 23:14:17.455664 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9672 23:14:17.462216 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9673 23:14:17.465455 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9674 23:14:17.468839 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9675 23:14:17.472092 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9676 23:14:17.475443 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9677 23:14:17.481965 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9678 23:14:17.485492 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9679 23:14:17.492523 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9680 23:14:17.495116 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9681 23:14:17.498804 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9682 23:14:17.505307 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9683 23:14:17.508709 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9684 23:14:17.515220 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9685 23:14:17.518752 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9686 23:14:17.522000 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9687 23:14:17.528466 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9688 23:14:17.531775 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9689 23:14:17.535185 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9690 23:14:17.541551 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9691 23:14:17.545374 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9692 23:14:17.548276 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9693 23:14:17.554859 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9694 23:14:17.558314 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9695 23:14:17.564948 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9696 23:14:17.568473 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9697 23:14:17.571746 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9698 23:14:17.578412 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9699 23:14:17.581500 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9700 23:14:17.584838 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9701 23:14:17.591781 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9702 23:14:17.594970 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9703 23:14:17.598024 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9704 23:14:17.604860 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9705 23:14:17.608180 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9706 23:14:17.614551 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9707 23:14:17.618048 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9708 23:14:17.621089 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9709 23:14:17.628260 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9710 23:14:17.631584 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9711 23:14:17.634848 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9712 23:14:17.641248 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9713 23:14:17.644626 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9714 23:14:17.647732 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9715 23:14:17.651281 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9716 23:14:17.654701 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9717 23:14:17.661240 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9718 23:14:17.664715 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9719 23:14:17.667552 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9720 23:14:17.671227 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9721 23:14:17.677592 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9722 23:14:17.681217 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9723 23:14:17.684272 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9724 23:14:17.691096 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9725 23:14:17.694210 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9726 23:14:17.697492 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9727 23:14:17.704223 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9728 23:14:17.707628 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9729 23:14:17.714246 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9730 23:14:17.717515 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9731 23:14:17.724341 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9732 23:14:17.727409 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9733 23:14:17.730882 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9734 23:14:17.737510 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9735 23:14:17.740721 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9736 23:14:17.747219 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9737 23:14:17.750802 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9738 23:14:17.753759 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9739 23:14:17.760649 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9740 23:14:17.764093 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9741 23:14:17.770550 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9742 23:14:17.773532 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9743 23:14:17.777225 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9744 23:14:17.783571 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9745 23:14:17.787107 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9746 23:14:17.793738 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9747 23:14:17.797261 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9748 23:14:17.800571 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9749 23:14:17.806938 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9750 23:14:17.810392 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9751 23:14:17.817122 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9752 23:14:17.820225 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9753 23:14:17.827073 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9754 23:14:17.830165 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9755 23:14:17.833461 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9756 23:14:17.840494 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9757 23:14:17.843593 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9758 23:14:17.850541 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9759 23:14:17.853393 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9760 23:14:17.856879 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9761 23:14:17.863345 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9762 23:14:17.866528 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9763 23:14:17.873249 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9764 23:14:17.876387 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9765 23:14:17.879739 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9766 23:14:17.886688 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9767 23:14:17.890315 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9768 23:14:17.896603 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9769 23:14:17.899570 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9770 23:14:17.906435 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9771 23:14:17.909499 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9772 23:14:17.913097 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9773 23:14:17.919513 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9774 23:14:17.922983 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9775 23:14:17.929467 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9776 23:14:17.932588 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9777 23:14:17.935980 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9778 23:14:17.942556 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9779 23:14:17.946031 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9780 23:14:17.952398 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9781 23:14:17.955881 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9782 23:14:17.959487 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9783 23:14:17.965778 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9784 23:14:17.969293 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9785 23:14:17.975667 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9786 23:14:17.979297 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9787 23:14:17.985983 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9788 23:14:17.988915 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9789 23:14:17.992500 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9790 23:14:17.998903 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9791 23:14:18.002187 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9792 23:14:18.008938 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9793 23:14:18.011752 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9794 23:14:18.018650 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9795 23:14:18.021758 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9796 23:14:18.025046 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9797 23:14:18.032139 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9798 23:14:18.035436 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9799 23:14:18.042072 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9800 23:14:18.045180 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9801 23:14:18.051879 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9802 23:14:18.054992 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9803 23:14:18.058349 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9804 23:14:18.064860 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9805 23:14:18.068435 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9806 23:14:18.074930 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9807 23:14:18.078492 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9808 23:14:18.085329 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9809 23:14:18.088332 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9810 23:14:18.091789 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9811 23:14:18.098405 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9812 23:14:18.101484 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9813 23:14:18.108286 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9814 23:14:18.111371 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9815 23:14:18.118247 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9816 23:14:18.121789 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9817 23:14:18.124705 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9818 23:14:18.131540 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9819 23:14:18.134703 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9820 23:14:18.141400 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9821 23:14:18.144979 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9822 23:14:18.151565 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9823 23:14:18.154664 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9824 23:14:18.158203 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9825 23:14:18.164538 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9826 23:14:18.168275 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9827 23:14:18.175209 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9828 23:14:18.178000 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9829 23:14:18.184409 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9830 23:14:18.187615 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9831 23:14:18.194565 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9832 23:14:18.197652 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9833 23:14:18.201143 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9834 23:14:18.207458 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9835 23:14:18.210875 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9836 23:14:18.217713 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9837 23:14:18.220813 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9838 23:14:18.227296 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9839 23:14:18.230971 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9840 23:14:18.234187 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9841 23:14:18.240679 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9842 23:14:18.244227 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9843 23:14:18.250561 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9844 23:14:18.254036 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9845 23:14:18.257072 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9846 23:14:18.264051 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9847 23:14:18.266968 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9848 23:14:18.273957 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9849 23:14:18.277393 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9850 23:14:18.283851 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9851 23:14:18.287051 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9852 23:14:18.293796 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9853 23:14:18.297209 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9854 23:14:18.303884 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9855 23:14:18.306958 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9856 23:14:18.313864 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9857 23:14:18.317459 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9858 23:14:18.323980 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9859 23:14:18.327080 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9860 23:14:18.333727 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9861 23:14:18.337388 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9862 23:14:18.343661 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9863 23:14:18.346761 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9864 23:14:18.353515 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9865 23:14:18.357109 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9866 23:14:18.363381 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9867 23:14:18.366895 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9868 23:14:18.373256 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9869 23:14:18.376798 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9870 23:14:18.383863 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9871 23:14:18.386861 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9872 23:14:18.393308 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9873 23:14:18.396935 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9874 23:14:18.403325 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9875 23:14:18.407026 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9876 23:14:18.413759 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9877 23:14:18.416514 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9878 23:14:18.416617 INFO: [APUAPC] vio 0
9879 23:14:18.424033 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9880 23:14:18.427495 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9881 23:14:18.431188 INFO: [APUAPC] D0_APC_0: 0x400510
9882 23:14:18.434082 INFO: [APUAPC] D0_APC_1: 0x0
9883 23:14:18.437385 INFO: [APUAPC] D0_APC_2: 0x1540
9884 23:14:18.440645 INFO: [APUAPC] D0_APC_3: 0x0
9885 23:14:18.443957 INFO: [APUAPC] D1_APC_0: 0xffffffff
9886 23:14:18.447526 INFO: [APUAPC] D1_APC_1: 0xffffffff
9887 23:14:18.450606 INFO: [APUAPC] D1_APC_2: 0x3fffff
9888 23:14:18.454037 INFO: [APUAPC] D1_APC_3: 0x0
9889 23:14:18.457717 INFO: [APUAPC] D2_APC_0: 0xffffffff
9890 23:14:18.461023 INFO: [APUAPC] D2_APC_1: 0xffffffff
9891 23:14:18.464106 INFO: [APUAPC] D2_APC_2: 0x3fffff
9892 23:14:18.467579 INFO: [APUAPC] D2_APC_3: 0x0
9893 23:14:18.470981 INFO: [APUAPC] D3_APC_0: 0xffffffff
9894 23:14:18.473906 INFO: [APUAPC] D3_APC_1: 0xffffffff
9895 23:14:18.477196 INFO: [APUAPC] D3_APC_2: 0x3fffff
9896 23:14:18.477294 INFO: [APUAPC] D3_APC_3: 0x0
9897 23:14:18.483838 INFO: [APUAPC] D4_APC_0: 0xffffffff
9898 23:14:18.487217 INFO: [APUAPC] D4_APC_1: 0xffffffff
9899 23:14:18.490730 INFO: [APUAPC] D4_APC_2: 0x3fffff
9900 23:14:18.490807 INFO: [APUAPC] D4_APC_3: 0x0
9901 23:14:18.493848 INFO: [APUAPC] D5_APC_0: 0xffffffff
9902 23:14:18.500465 INFO: [APUAPC] D5_APC_1: 0xffffffff
9903 23:14:18.503923 INFO: [APUAPC] D5_APC_2: 0x3fffff
9904 23:14:18.503995 INFO: [APUAPC] D5_APC_3: 0x0
9905 23:14:18.507447 INFO: [APUAPC] D6_APC_0: 0xffffffff
9906 23:14:18.510382 INFO: [APUAPC] D6_APC_1: 0xffffffff
9907 23:14:18.513990 INFO: [APUAPC] D6_APC_2: 0x3fffff
9908 23:14:18.517367 INFO: [APUAPC] D6_APC_3: 0x0
9909 23:14:18.520794 INFO: [APUAPC] D7_APC_0: 0xffffffff
9910 23:14:18.523552 INFO: [APUAPC] D7_APC_1: 0xffffffff
9911 23:14:18.526992 INFO: [APUAPC] D7_APC_2: 0x3fffff
9912 23:14:18.530546 INFO: [APUAPC] D7_APC_3: 0x0
9913 23:14:18.534025 INFO: [APUAPC] D8_APC_0: 0xffffffff
9914 23:14:18.536956 INFO: [APUAPC] D8_APC_1: 0xffffffff
9915 23:14:18.540371 INFO: [APUAPC] D8_APC_2: 0x3fffff
9916 23:14:18.543669 INFO: [APUAPC] D8_APC_3: 0x0
9917 23:14:18.546719 INFO: [APUAPC] D9_APC_0: 0xffffffff
9918 23:14:18.550155 INFO: [APUAPC] D9_APC_1: 0xffffffff
9919 23:14:18.553887 INFO: [APUAPC] D9_APC_2: 0x3fffff
9920 23:14:18.557332 INFO: [APUAPC] D9_APC_3: 0x0
9921 23:14:18.560117 INFO: [APUAPC] D10_APC_0: 0xffffffff
9922 23:14:18.563287 INFO: [APUAPC] D10_APC_1: 0xffffffff
9923 23:14:18.567183 INFO: [APUAPC] D10_APC_2: 0x3fffff
9924 23:14:18.570146 INFO: [APUAPC] D10_APC_3: 0x0
9925 23:14:18.573685 INFO: [APUAPC] D11_APC_0: 0xffffffff
9926 23:14:18.577008 INFO: [APUAPC] D11_APC_1: 0xffffffff
9927 23:14:18.580253 INFO: [APUAPC] D11_APC_2: 0x3fffff
9928 23:14:18.583248 INFO: [APUAPC] D11_APC_3: 0x0
9929 23:14:18.586475 INFO: [APUAPC] D12_APC_0: 0xffffffff
9930 23:14:18.590115 INFO: [APUAPC] D12_APC_1: 0xffffffff
9931 23:14:18.593176 INFO: [APUAPC] D12_APC_2: 0x3fffff
9932 23:14:18.596787 INFO: [APUAPC] D12_APC_3: 0x0
9933 23:14:18.600235 INFO: [APUAPC] D13_APC_0: 0xffffffff
9934 23:14:18.603110 INFO: [APUAPC] D13_APC_1: 0xffffffff
9935 23:14:18.606701 INFO: [APUAPC] D13_APC_2: 0x3fffff
9936 23:14:18.609731 INFO: [APUAPC] D13_APC_3: 0x0
9937 23:14:18.613023 INFO: [APUAPC] D14_APC_0: 0xffffffff
9938 23:14:18.616511 INFO: [APUAPC] D14_APC_1: 0xffffffff
9939 23:14:18.620334 INFO: [APUAPC] D14_APC_2: 0x3fffff
9940 23:14:18.623173 INFO: [APUAPC] D14_APC_3: 0x0
9941 23:14:18.626695 INFO: [APUAPC] D15_APC_0: 0xffffffff
9942 23:14:18.630098 INFO: [APUAPC] D15_APC_1: 0xffffffff
9943 23:14:18.632836 INFO: [APUAPC] D15_APC_2: 0x3fffff
9944 23:14:18.636305 INFO: [APUAPC] D15_APC_3: 0x0
9945 23:14:18.639641 INFO: [APUAPC] APC_CON: 0x4
9946 23:14:18.643308 INFO: [NOCDAPC] D0_APC_0: 0x0
9947 23:14:18.646590 INFO: [NOCDAPC] D0_APC_1: 0x0
9948 23:14:18.650035 INFO: [NOCDAPC] D1_APC_0: 0x0
9949 23:14:18.652984 INFO: [NOCDAPC] D1_APC_1: 0xfff
9950 23:14:18.656583 INFO: [NOCDAPC] D2_APC_0: 0x0
9951 23:14:18.656683 INFO: [NOCDAPC] D2_APC_1: 0xfff
9952 23:14:18.659670 INFO: [NOCDAPC] D3_APC_0: 0x0
9953 23:14:18.663333 INFO: [NOCDAPC] D3_APC_1: 0xfff
9954 23:14:18.666122 INFO: [NOCDAPC] D4_APC_0: 0x0
9955 23:14:18.669727 INFO: [NOCDAPC] D4_APC_1: 0xfff
9956 23:14:18.673160 INFO: [NOCDAPC] D5_APC_0: 0x0
9957 23:14:18.676214 INFO: [NOCDAPC] D5_APC_1: 0xfff
9958 23:14:18.679507 INFO: [NOCDAPC] D6_APC_0: 0x0
9959 23:14:18.682833 INFO: [NOCDAPC] D6_APC_1: 0xfff
9960 23:14:18.686064 INFO: [NOCDAPC] D7_APC_0: 0x0
9961 23:14:18.689832 INFO: [NOCDAPC] D7_APC_1: 0xfff
9962 23:14:18.689909 INFO: [NOCDAPC] D8_APC_0: 0x0
9963 23:14:18.693006 INFO: [NOCDAPC] D8_APC_1: 0xfff
9964 23:14:18.695922 INFO: [NOCDAPC] D9_APC_0: 0x0
9965 23:14:18.699316 INFO: [NOCDAPC] D9_APC_1: 0xfff
9966 23:14:18.702636 INFO: [NOCDAPC] D10_APC_0: 0x0
9967 23:14:18.706087 INFO: [NOCDAPC] D10_APC_1: 0xfff
9968 23:14:18.709669 INFO: [NOCDAPC] D11_APC_0: 0x0
9969 23:14:18.712466 INFO: [NOCDAPC] D11_APC_1: 0xfff
9970 23:14:18.715839 INFO: [NOCDAPC] D12_APC_0: 0x0
9971 23:14:18.719220 INFO: [NOCDAPC] D12_APC_1: 0xfff
9972 23:14:18.722746 INFO: [NOCDAPC] D13_APC_0: 0x0
9973 23:14:18.726220 INFO: [NOCDAPC] D13_APC_1: 0xfff
9974 23:14:18.729311 INFO: [NOCDAPC] D14_APC_0: 0x0
9975 23:14:18.732853 INFO: [NOCDAPC] D14_APC_1: 0xfff
9976 23:14:18.732953 INFO: [NOCDAPC] D15_APC_0: 0x0
9977 23:14:18.736430 INFO: [NOCDAPC] D15_APC_1: 0xfff
9978 23:14:18.739273 INFO: [NOCDAPC] APC_CON: 0x4
9979 23:14:18.742633 INFO: [APUAPC] set_apusys_apc done
9980 23:14:18.746046 INFO: [DEVAPC] devapc_init done
9981 23:14:18.749427 INFO: GICv3 without legacy support detected.
9982 23:14:18.756026 INFO: ARM GICv3 driver initialized in EL3
9983 23:14:18.759185 INFO: Maximum SPI INTID supported: 639
9984 23:14:18.762557 INFO: BL31: Initializing runtime services
9985 23:14:18.769140 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9986 23:14:18.772525 INFO: SPM: enable CPC mode
9987 23:14:18.775560 INFO: mcdi ready for mcusys-off-idle and system suspend
9988 23:14:18.782488 INFO: BL31: Preparing for EL3 exit to normal world
9989 23:14:18.785377 INFO: Entry point address = 0x80000000
9990 23:14:18.785476 INFO: SPSR = 0x8
9991 23:14:18.792190
9992 23:14:18.792288
9993 23:14:18.792380
9994 23:14:18.795956 Starting depthcharge on Spherion...
9995 23:14:18.796052
9996 23:14:18.796142 Wipe memory regions:
9997 23:14:18.796228
9998 23:14:18.796937 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
9999 23:14:18.797039 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10000 23:14:18.797138 Setting prompt string to ['asurada:']
10001 23:14:18.797243 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10002 23:14:18.798861 [0x00000040000000, 0x00000054600000)
10003 23:14:18.921509
10004 23:14:18.921687 [0x00000054660000, 0x00000080000000)
10005 23:14:19.181993
10006 23:14:19.182121 [0x000000821a7280, 0x000000ffe64000)
10007 23:14:19.926723
10008 23:14:19.926887 [0x00000100000000, 0x00000240000000)
10009 23:14:21.817022
10010 23:14:21.820316 Initializing XHCI USB controller at 0x11200000.
10011 23:14:22.858518
10012 23:14:22.862223 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10013 23:14:22.862385
10014 23:14:22.862505
10015 23:14:22.862615
10016 23:14:22.862991 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10018 23:14:22.963498 asurada: tftpboot 192.168.201.1 12172417/tftp-deploy-syndytqy/kernel/image.itb 12172417/tftp-deploy-syndytqy/kernel/cmdline
10019 23:14:22.963659 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10020 23:14:22.963751 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10021 23:14:22.967714 tftpboot 192.168.201.1 12172417/tftp-deploy-syndytqy/kernel/image.ittp-deploy-syndytqy/kernel/cmdline
10022 23:14:22.967801
10023 23:14:22.967866 Waiting for link
10024 23:14:23.128243
10025 23:14:23.128380 R8152: Initializing
10026 23:14:23.128450
10027 23:14:23.131646 Version 9 (ocp_data = 6010)
10028 23:14:23.131730
10029 23:14:23.135190 R8152: Done initializing
10030 23:14:23.135274
10031 23:14:23.135338 Adding net device
10032 23:14:25.080019
10033 23:14:25.080508 done.
10034 23:14:25.080905
10035 23:14:25.081226 MAC: 00:e0:4c:78:7a:aa
10036 23:14:25.081531
10037 23:14:25.083578 Sending DHCP discover... done.
10038 23:14:25.084000
10039 23:14:25.090004 Waiting for reply... done.
10040 23:14:25.090448
10041 23:14:25.091104 Sending DHCP request... done.
10042 23:14:25.091452
10043 23:14:25.112750 Waiting for reply... done.
10044 23:14:25.113057
10045 23:14:25.113275 My ip is 192.168.201.12
10046 23:14:25.113462
10047 23:14:25.116122 The DHCP server ip is 192.168.201.1
10048 23:14:25.116368
10049 23:14:25.122525 TFTP server IP predefined by user: 192.168.201.1
10050 23:14:25.122814
10051 23:14:25.129114 Bootfile predefined by user: 12172417/tftp-deploy-syndytqy/kernel/image.itb
10052 23:14:25.129367
10053 23:14:25.132534 Sending tftp read request... done.
10054 23:14:25.132827
10055 23:14:25.137524 Waiting for the transfer...
10056 23:14:25.137795
10057 23:14:25.453617 00000000 ################################################################
10058 23:14:25.454051
10059 23:14:25.758055 00080000 ################################################################
10060 23:14:25.758193
10061 23:14:26.054101 00100000 ################################################################
10062 23:14:26.054233
10063 23:14:26.330344 00180000 ################################################################
10064 23:14:26.330510
10065 23:14:26.612404 00200000 ################################################################
10066 23:14:26.612562
10067 23:14:26.893565 00280000 ################################################################
10068 23:14:26.893733
10069 23:14:27.175914 00300000 ################################################################
10070 23:14:27.176046
10071 23:14:27.451321 00380000 ################################################################
10072 23:14:27.451466
10073 23:14:27.726826 00400000 ################################################################
10074 23:14:27.726977
10075 23:14:27.994165 00480000 ################################################################
10076 23:14:27.994297
10077 23:14:28.244148 00500000 ################################################################
10078 23:14:28.244278
10079 23:14:28.517827 00580000 ################################################################
10080 23:14:28.517957
10081 23:14:28.804580 00600000 ################################################################
10082 23:14:28.804739
10083 23:14:29.081202 00680000 ################################################################
10084 23:14:29.081369
10085 23:14:29.372909 00700000 ################################################################
10086 23:14:29.373066
10087 23:14:29.645974 00780000 ################################################################
10088 23:14:29.646134
10089 23:14:29.919823 00800000 ################################################################
10090 23:14:29.919955
10091 23:14:30.187423 00880000 ################################################################
10092 23:14:30.187556
10093 23:14:30.459356 00900000 ################################################################
10094 23:14:30.459517
10095 23:14:30.723215 00980000 ################################################################
10096 23:14:30.723377
10097 23:14:30.978727 00a00000 ################################################################
10098 23:14:30.978882
10099 23:14:31.256394 00a80000 ################################################################
10100 23:14:31.256548
10101 23:14:31.539073 00b00000 ################################################################
10102 23:14:31.539200
10103 23:14:31.827844 00b80000 ################################################################
10104 23:14:31.828006
10105 23:14:32.117164 00c00000 ################################################################
10106 23:14:32.117308
10107 23:14:32.471651 00c80000 ################################################################
10108 23:14:32.471815
10109 23:14:32.821607 00d00000 ################################################################
10110 23:14:32.821787
10111 23:14:33.159971 00d80000 ################################################################
10112 23:14:33.160142
10113 23:14:33.492760 00e00000 ################################################################
10114 23:14:33.492926
10115 23:14:33.757036 00e80000 ################################################################
10116 23:14:33.757205
10117 23:14:34.028563 00f00000 ################################################################
10118 23:14:34.028733
10119 23:14:34.309762 00f80000 ################################################################
10120 23:14:34.309931
10121 23:14:34.590690 01000000 ################################################################
10122 23:14:34.590822
10123 23:14:34.880854 01080000 ################################################################
10124 23:14:34.880993
10125 23:14:35.180757 01100000 ################################################################
10126 23:14:35.180917
10127 23:14:35.486951 01180000 ################################################################
10128 23:14:35.487152
10129 23:14:35.792415 01200000 ################################################################
10130 23:14:35.792576
10131 23:14:36.090709 01280000 ################################################################
10132 23:14:36.090872
10133 23:14:36.373227 01300000 ################################################################
10134 23:14:36.373389
10135 23:14:36.676240 01380000 ################################################################
10136 23:14:36.676402
10137 23:14:36.941295 01400000 ################################################################
10138 23:14:36.941452
10139 23:14:37.217533 01480000 ################################################################
10140 23:14:37.217678
10141 23:14:37.517860 01500000 ################################################################
10142 23:14:37.518017
10143 23:14:37.786611 01580000 ################################################################
10144 23:14:37.786768
10145 23:14:38.087112 01600000 ################################################################
10146 23:14:38.087265
10147 23:14:38.364718 01680000 ################################################################
10148 23:14:38.364875
10149 23:14:38.634954 01700000 ################################################################
10150 23:14:38.635121
10151 23:14:38.898814 01780000 ################################################################
10152 23:14:38.898975
10153 23:14:39.164937 01800000 ################################################################
10154 23:14:39.165096
10155 23:14:39.452355 01880000 ################################################################
10156 23:14:39.452515
10157 23:14:39.701534 01900000 ################################################################
10158 23:14:39.701675
10159 23:14:39.974231 01980000 ################################################################
10160 23:14:39.974387
10161 23:14:40.248692 01a00000 ################################################################
10162 23:14:40.248822
10163 23:14:40.517476 01a80000 ################################################################
10164 23:14:40.517628
10165 23:14:40.770047 01b00000 ################################################################
10166 23:14:40.770179
10167 23:14:41.029543 01b80000 ################################################################
10168 23:14:41.029703
10169 23:14:41.283750 01c00000 ################################################################
10170 23:14:41.283884
10171 23:14:41.540652 01c80000 ################################################################
10172 23:14:41.540779
10173 23:14:41.808183 01d00000 ################################################################
10174 23:14:41.808336
10175 23:14:42.160359 01d80000 ################################################################
10176 23:14:42.160499
10177 23:14:42.490803 01e00000 ################################################################
10178 23:14:42.490940
10179 23:14:42.771047 01e80000 ################################################################
10180 23:14:42.771180
10181 23:14:43.065845 01f00000 ################################################################
10182 23:14:43.065984
10183 23:14:43.342205 01f80000 ################################################################
10184 23:14:43.342344
10185 23:14:43.628499 02000000 ################################################################
10186 23:14:43.628632
10187 23:14:43.925501 02080000 ################################################################
10188 23:14:43.925644
10189 23:14:44.215411 02100000 ################################################################
10190 23:14:44.215545
10191 23:14:44.488044 02180000 ################################################################
10192 23:14:44.488177
10193 23:14:44.761597 02200000 ################################################################
10194 23:14:44.761727
10195 23:14:45.079574 02280000 ################################################################
10196 23:14:45.079713
10197 23:14:45.406439 02300000 ################################################################
10198 23:14:45.406575
10199 23:14:45.722081 02380000 ################################################################
10200 23:14:45.722220
10201 23:14:46.049209 02400000 ################################################################
10202 23:14:46.049345
10203 23:14:46.380479 02480000 ################################################################
10204 23:14:46.380616
10205 23:14:46.705281 02500000 ################################################################
10206 23:14:46.705425
10207 23:14:47.022059 02580000 ################################################################
10208 23:14:47.022190
10209 23:14:47.363919 02600000 ################################################################
10210 23:14:47.364063
10211 23:14:47.700516 02680000 ################################################################
10212 23:14:47.700655
10213 23:14:48.015731 02700000 ################################################################
10214 23:14:48.015865
10215 23:14:48.351993 02780000 ################################################################
10216 23:14:48.352127
10217 23:14:48.674009 02800000 ################################################################
10218 23:14:48.674148
10219 23:14:48.995587 02880000 ################################################################
10220 23:14:48.995724
10221 23:14:49.328441 02900000 ################################################################
10222 23:14:49.328573
10223 23:14:49.658344 02980000 ################################################################
10224 23:14:49.658509
10225 23:14:49.990609 02a00000 ################################################################
10226 23:14:49.990745
10227 23:14:50.318663 02a80000 ################################################################
10228 23:14:50.318800
10229 23:14:50.649635 02b00000 ################################################################
10230 23:14:50.649776
10231 23:14:50.984527 02b80000 ################################################################
10232 23:14:50.984668
10233 23:14:51.264419 02c00000 ################################################################
10234 23:14:51.264556
10235 23:14:51.544202 02c80000 ################################################################
10236 23:14:51.544339
10237 23:14:51.847873 02d00000 ################################################################
10238 23:14:51.848006
10239 23:14:52.136746 02d80000 ################################################################
10240 23:14:52.136880
10241 23:14:52.499086 02e00000 ################################################################
10242 23:14:52.499224
10243 23:14:52.780007 02e80000 ################################################################
10244 23:14:52.780175
10245 23:14:53.055056 02f00000 ################################################################
10246 23:14:53.055191
10247 23:14:53.413692 02f80000 ################################################################
10248 23:14:53.413829
10249 23:14:53.493637 03000000 ############### done.
10250 23:14:53.493764
10251 23:14:53.497047 The bootfile was 50453438 bytes long.
10252 23:14:53.497133
10253 23:14:53.500574 Sending tftp read request... done.
10254 23:14:53.500701
10255 23:14:53.500801 Waiting for the transfer...
10256 23:14:53.500907
10257 23:14:53.503448 00000000 # done.
10258 23:14:53.503572
10259 23:14:53.510464 Command line loaded dynamically from TFTP file: 12172417/tftp-deploy-syndytqy/kernel/cmdline
10260 23:14:53.510593
10261 23:14:53.523521 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10262 23:14:53.523648
10263 23:14:53.526819 Loading FIT.
10264 23:14:53.526941
10265 23:14:53.530436 Image ramdisk-1 has 39354778 bytes.
10266 23:14:53.530559
10267 23:14:53.530671 Image fdt-1 has 47278 bytes.
10268 23:14:53.533359
10269 23:14:53.533459 Image kernel-1 has 11049348 bytes.
10270 23:14:53.533573
10271 23:14:53.543862 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10272 23:14:53.543976
10273 23:14:53.559729 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10274 23:14:53.562928
10275 23:14:53.566424 Choosing best match conf-1 for compat google,spherion-rev2.
10276 23:14:53.570764
10277 23:14:53.575616 Connected to device vid:did:rid of 1ae0:0028:00
10278 23:14:53.583495
10279 23:14:53.587480 tpm_get_response: command 0x17b, return code 0x0
10280 23:14:53.587582
10281 23:14:53.590244 ec_init: CrosEC protocol v3 supported (256, 248)
10282 23:14:53.594182
10283 23:14:53.597460 tpm_cleanup: add release locality here.
10284 23:14:53.597565
10285 23:14:53.597683 Shutting down all USB controllers.
10286 23:14:53.600924
10287 23:14:53.601041 Removing current net device
10288 23:14:53.601139
10289 23:14:53.607779 Exiting depthcharge with code 4 at timestamp: 64052063
10290 23:14:53.607903
10291 23:14:53.611250 LZMA decompressing kernel-1 to 0x821a6718
10292 23:14:53.611372
10293 23:14:53.614125 LZMA decompressing kernel-1 to 0x40000000
10294 23:14:55.002045
10295 23:14:55.002180 jumping to kernel
10296 23:14:55.002708 end: 2.2.4 bootloader-commands (duration 00:00:36) [common]
10297 23:14:55.002816 start: 2.2.5 auto-login-action (timeout 00:03:49) [common]
10298 23:14:55.002895 Setting prompt string to ['Linux version [0-9]']
10299 23:14:55.002974 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10300 23:14:55.003045 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10301 23:14:55.083629
10302 23:14:55.086814 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10303 23:14:55.090564 start: 2.2.5.1 login-action (timeout 00:03:49) [common]
10304 23:14:55.090657 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10305 23:14:55.090738 Setting prompt string to []
10306 23:14:55.090820 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10307 23:14:55.090901 Using line separator: #'\n'#
10308 23:14:55.090962 No login prompt set.
10309 23:14:55.091025 Parsing kernel messages
10310 23:14:55.091088 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10311 23:14:55.091191 [login-action] Waiting for messages, (timeout 00:03:49)
10312 23:14:55.110244 [ 0.000000] Linux version 6.1.64-cip10-rt5 (KernelCI@build-j33605-arm64-gcc-10-defconfig-arm64-chromebook-7778h) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sun Dec 3 22:38:18 UTC 2023
10313 23:14:55.113629 [ 0.000000] random: crng init done
10314 23:14:55.120100 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10315 23:14:55.123665 [ 0.000000] efi: UEFI not found.
10316 23:14:55.130224 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10317 23:14:55.140352 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10318 23:14:55.146906 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10319 23:14:55.156640 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10320 23:14:55.163516 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10321 23:14:55.169936 [ 0.000000] printk: bootconsole [mtk8250] enabled
10322 23:14:55.176104 [ 0.000000] NUMA: No NUMA configuration found
10323 23:14:55.183258 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10324 23:14:55.186663 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10325 23:14:55.190115 [ 0.000000] Zone ranges:
10326 23:14:55.196583 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10327 23:14:55.200049 [ 0.000000] DMA32 empty
10328 23:14:55.206362 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10329 23:14:55.209855 [ 0.000000] Movable zone start for each node
10330 23:14:55.212972 [ 0.000000] Early memory node ranges
10331 23:14:55.219402 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10332 23:14:55.226330 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10333 23:14:55.232692 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10334 23:14:55.239577 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10335 23:14:55.245991 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10336 23:14:55.252574 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10337 23:14:55.308383 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10338 23:14:55.315249 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10339 23:14:55.321647 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10340 23:14:55.325041 [ 0.000000] psci: probing for conduit method from DT.
10341 23:14:55.331775 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10342 23:14:55.335228 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10343 23:14:55.341528 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10344 23:14:55.345234 [ 0.000000] psci: SMC Calling Convention v1.2
10345 23:14:55.351450 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10346 23:14:55.354990 [ 0.000000] Detected VIPT I-cache on CPU0
10347 23:14:55.361388 [ 0.000000] CPU features: detected: GIC system register CPU interface
10348 23:14:55.368298 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10349 23:14:55.374648 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10350 23:14:55.381165 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10351 23:14:55.388182 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10352 23:14:55.395113 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10353 23:14:55.401805 [ 0.000000] alternatives: applying boot alternatives
10354 23:14:55.405162 [ 0.000000] Fallback order for Node 0: 0
10355 23:14:55.415139 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10356 23:14:55.415270 [ 0.000000] Policy zone: Normal
10357 23:14:55.431430 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10358 23:14:55.441402 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10359 23:14:55.452828 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10360 23:14:55.462917 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10361 23:14:55.469271 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10362 23:14:55.472662 <6>[ 0.000000] software IO TLB: area num 8.
10363 23:14:55.529082 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10364 23:14:55.678122 <6>[ 0.000000] Memory: 7931124K/8385536K available (17984K kernel code, 4116K rwdata, 17316K rodata, 8448K init, 615K bss, 421644K reserved, 32768K cma-reserved)
10365 23:14:55.685118 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10366 23:14:55.691942 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10367 23:14:55.694961 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10368 23:14:55.701309 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10369 23:14:55.708152 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10370 23:14:55.711561 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10371 23:14:55.721548 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10372 23:14:55.727832 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10373 23:14:55.734685 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10374 23:14:55.741555 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10375 23:14:55.744597 <6>[ 0.000000] GICv3: 608 SPIs implemented
10376 23:14:55.747715 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10377 23:14:55.754584 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10378 23:14:55.758140 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10379 23:14:55.764809 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10380 23:14:55.777752 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10381 23:14:55.788148 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10382 23:14:55.798008 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10383 23:14:55.805198 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10384 23:14:55.818736 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10385 23:14:55.824859 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10386 23:14:55.831337 <6>[ 0.009187] Console: colour dummy device 80x25
10387 23:14:55.841816 <6>[ 0.013933] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10388 23:14:55.844979 <6>[ 0.024376] pid_max: default: 32768 minimum: 301
10389 23:14:55.851616 <6>[ 0.029277] LSM: Security Framework initializing
10390 23:14:55.858325 <6>[ 0.034244] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10391 23:14:55.868685 <6>[ 0.042059] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10392 23:14:55.874723 <6>[ 0.051462] cblist_init_generic: Setting adjustable number of callback queues.
10393 23:14:55.881594 <6>[ 0.058904] cblist_init_generic: Setting shift to 3 and lim to 1.
10394 23:14:55.891349 <6>[ 0.065241] cblist_init_generic: Setting adjustable number of callback queues.
10395 23:14:55.895026 <6>[ 0.072715] cblist_init_generic: Setting shift to 3 and lim to 1.
10396 23:14:55.901511 <6>[ 0.079192] rcu: Hierarchical SRCU implementation.
10397 23:14:55.908322 <6>[ 0.079194] rcu: Max phase no-delay instances is 1000.
10398 23:14:55.914468 <6>[ 0.079218] printk: bootconsole [mtk8250] printing thread started
10399 23:14:55.921194 <6>[ 0.097540] EFI services will not be available.
10400 23:14:55.925005 <6>[ 0.097743] smp: Bringing up secondary CPUs ...
10401 23:14:55.927767 <6>[ 0.098052] Detected VIPT I-cache on CPU1
10402 23:14:55.938125 <6>[ 0.098121] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10403 23:14:55.944783 <6>[ 0.098152] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10404 23:14:55.953786 <6>[ 0.126026] Detected VIPT I-cache on CPU2
10405 23:14:55.960137 <6>[ 0.126073] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10406 23:14:55.966955 <6>[ 0.126089] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10407 23:14:55.973678 <6>[ 0.126347] Detected VIPT I-cache on CPU3
10408 23:14:55.980358 <6>[ 0.126393] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10409 23:14:55.986762 <6>[ 0.126406] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10410 23:14:55.989932 <6>[ 0.126717] CPU features: detected: Spectre-v4
10411 23:14:55.996796 <6>[ 0.126723] CPU features: detected: Spectre-BHB
10412 23:14:56.000062 <6>[ 0.126727] Detected PIPT I-cache on CPU4
10413 23:14:56.006624 <6>[ 0.126785] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10414 23:14:56.013220 <6>[ 0.126802] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10415 23:14:56.020224 <6>[ 0.127096] Detected PIPT I-cache on CPU5
10416 23:14:56.026766 <6>[ 0.127159] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10417 23:14:56.033286 <6>[ 0.127175] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10418 23:14:56.036776 <6>[ 0.127460] Detected PIPT I-cache on CPU6
10419 23:14:56.043321 <6>[ 0.127523] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10420 23:14:56.049787 <6>[ 0.127540] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10421 23:14:56.056712 <6>[ 0.127832] Detected PIPT I-cache on CPU7
10422 23:14:56.063349 <6>[ 0.127895] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10423 23:14:56.069923 <6>[ 0.127911] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10424 23:14:56.072787 <6>[ 0.127958] smp: Brought up 1 node, 8 CPUs
10425 23:14:56.079812 <6>[ 0.127963] SMP: Total of 8 processors activated.
10426 23:14:56.083275 <6>[ 0.127966] CPU features: detected: 32-bit EL0 Support
10427 23:14:56.093081 <6>[ 0.127968] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10428 23:14:56.099379 <6>[ 0.127970] CPU features: detected: Common not Private translations
10429 23:14:56.106092 <6>[ 0.127972] CPU features: detected: CRC32 instructions
10430 23:14:56.109561 <6>[ 0.127975] CPU features: detected: RCpc load-acquire (LDAPR)
10431 23:14:56.116026 <6>[ 0.127976] CPU features: detected: LSE atomic instructions
10432 23:14:56.122796 <6>[ 0.127978] CPU features: detected: Privileged Access Never
10433 23:14:56.128975 <6>[ 0.127980] CPU features: detected: RAS Extension Support
10434 23:14:56.135669 <6>[ 0.127983] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10435 23:14:56.138826 <6>[ 0.128049] CPU: All CPU(s) started at EL2
10436 23:14:56.145239 <6>[ 0.128050] alternatives: applying system-wide alternatives
10437 23:14:56.148808 <6>[ 0.141090] devtmpfs: initialized
10438 23:14:56.158797 <6>[ 0.147358] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10439 23:14:56.186952 �@��ѕɕ���}%9Q��ɽѽ����2�����5R�<6>[ 0.3642<99] printk: console [ttyS0] printing thread started
10440 23:14:56.193462 6<6>[ 0.364318] printk: console [ttyS0] enabled
10441 23:14:56.200221 >[ 0.228768] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10442 23:14:56.208359 <6>[ 0.364322] printk: bootconsole [mtk8250] disabled
10443 23:14:56.214975 <6>[ 0.382413] printk: bootconsole [mtk8250] printing thread stopped
10444 23:14:56.217772 <6>[ 0.383400] SuperH (H)SCI(F) driver initialized
10445 23:14:56.224680 <6>[ 0.383879] msm_serial: driver initialized
10446 23:14:56.231076 <6>[ 0.388405] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10447 23:14:56.241319 <6>[ 0.388432] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10448 23:14:56.247993 <6>[ 0.388462] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10449 23:14:56.263840 <6>[ 0.388491] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10450 23:14:56.276603 <6>[ 0.388512] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10451 23:14:56.277104 <6>[ 0.388540] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10452 23:14:56.292062 <6>[ 0.388568] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10453 23:14:56.293171 <6>[ 0.388668] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10454 23:14:56.306623 <6>[ 0.388698] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10455 23:14:56.307047 <6>[ 0.400347] loop: module loaded
10456 23:14:56.312921 <6>[ 0.402902] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10457 23:14:56.319933 <4>[ 0.419410] mtk-pmic-keys: Failed to locate of_node [id: -1]
10458 23:14:56.320365 <6>[ 0.420222] megasas: 07.719.03.00-rc1
10459 23:14:56.326822 <6>[ 0.432805] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10460 23:14:56.333295 <6>[ 0.432921] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10461 23:14:56.339678 <6>[ 0.444532] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10462 23:14:56.349528 <6>[ 0.498503] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10463 23:14:57.647679 <6>[ 1.824763] Freeing initrd memory: 38428K
10464 23:14:57.655527 <6>[ 1.830728] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10465 23:14:57.662198 <6>[ 1.835269] tun: Universal TUN/TAP device driver, 1.6
10466 23:14:57.665262 <6>[ 1.836015] thunder_xcv, ver 1.0
10467 23:14:57.669113 <6>[ 1.836035] thunder_bgx, ver 1.0
10468 23:14:57.672004 <6>[ 1.836049] nicpf, ver 1.0
10469 23:14:57.678911 <6>[ 1.837093] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10470 23:14:57.685300 <6>[ 1.837096] hns3: Copyright (c) 2017 Huawei Corporation.
10471 23:14:57.688369 <6>[ 1.837119] hclge is initializing
10472 23:14:57.695359 <6>[ 1.837133] e1000: Intel(R) PRO/1000 Network Driver
10473 23:14:57.698777 <6>[ 1.837135] e1000: Copyright (c) 1999-2006 Intel Corporation.
10474 23:14:57.706427 <6>[ 1.837152] e1000e: Intel(R) PRO/1000 Network Driver
10475 23:14:57.713442 <6>[ 1.837154] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10476 23:14:57.716557 <6>[ 1.837169] igb: Intel(R) Gigabit Ethernet Network Driver
10477 23:14:57.723442 <6>[ 1.837171] igb: Copyright (c) 2007-2014 Intel Corporation.
10478 23:14:57.729590 <6>[ 1.837186] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10479 23:14:57.737095 <6>[ 1.837188] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10480 23:14:57.740103 <6>[ 1.837489] sky2: driver version 1.30
10481 23:14:57.743693 <6>[ 1.838556] VFIO - User Level meta-driver version: 0.3
10482 23:14:57.750556 <6>[ 1.841364] usbcore: registered new interface driver usb-storage
10483 23:14:57.756855 <6>[ 1.841554] usbcore: registered new device driver onboard-usb-hub
10484 23:14:57.763260 <6>[ 1.844300] mt6397-rtc mt6359-rtc: registered as rtc0
10485 23:14:57.770234 <6>[ 1.844452] mt6397-rtc mt6359-rtc: setting system clock to 2023-12-03T23:12:43 UTC (1701645163)
10486 23:14:57.777096 <6>[ 1.845059] i2c_dev: i2c /dev entries driver
10487 23:14:57.783712 <6>[ 1.852106] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10488 23:14:57.789845 <6>[ 1.867090] cpu cpu0: EM: created perf domain
10489 23:14:57.793286 <6>[ 1.867402] cpu cpu4: EM: created perf domain
10490 23:14:57.799948 <6>[ 1.871597] sdhci: Secure Digital Host Controller Interface driver
10491 23:14:57.802865 <6>[ 1.871598] sdhci: Copyright(c) Pierre Ossman
10492 23:14:57.810133 <6>[ 1.871955] Synopsys Designware Multimedia Card Interface Driver
10493 23:14:57.816548 <6>[ 1.872341] sdhci-pltfm: SDHCI platform and OF driver helper
10494 23:14:57.822921 <6>[ 1.876605] ledtrig-cpu: registered to indicate activity on CPUs
10495 23:14:57.826393 <6>[ 1.877235] mmc0: CQHCI version 5.10
10496 23:14:57.832752 <6>[ 1.877268] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10497 23:14:57.839593 <6>[ 1.877557] usbcore: registered new interface driver usbhid
10498 23:14:57.843143 <6>[ 1.877558] usbhid: USB HID core driver
10499 23:14:57.850061 <6>[ 1.877669] spi_master spi0: will run message pump with realtime priority
10500 23:14:57.863488 <6>[ 1.912210] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10501 23:14:57.876724 <6>[ 1.914477] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10502 23:14:57.882994 <6>[ 1.915809] cros-ec-spi spi0.0: Chrome EC device registered
10503 23:14:57.892998 <6>[ 1.937038] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10504 23:14:57.896438 <6>[ 1.939941] NET: Registered PF_PACKET protocol family
10505 23:14:57.903220 <6>[ 1.940051] 9pnet: Installing 9P2000 support
10506 23:14:57.906404 <5>[ 1.940119] Key type dns_resolver registered
10507 23:14:57.909518 <6>[ 1.940649] registered taskstats version 1
10508 23:14:57.915861 <5>[ 1.940668] Loading compiled-in X.509 certificates
10509 23:14:57.926142 <4>[ 1.956053] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10510 23:14:57.935821 <4>[ 1.956226] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10511 23:14:57.942453 <3>[ 1.956238] debugfs: File 'uA_load' in directory '/' already present!
10512 23:14:57.949469 <3>[ 1.956248] debugfs: File 'min_uV' in directory '/' already present!
10513 23:14:57.955799 <3>[ 1.956252] debugfs: File 'max_uV' in directory '/' already present!
10514 23:14:57.962643 <3>[ 1.956256] debugfs: File 'constraint_flags' in directory '/' already present!
10515 23:14:57.972406 <3>[ 1.958805] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10516 23:14:57.979400 <6>[ 1.970933] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10517 23:14:57.982242 <6>[ 1.971494] mmc0: Command Queue Engine enabled
10518 23:14:57.989126 <6>[ 1.971512] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10519 23:14:57.995929 <6>[ 1.971537] xhci-mtk 11200000.usb: xHCI Host Controller
10520 23:14:58.002187 <6>[ 1.971561] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10521 23:14:58.012250 <6>[ 1.971823] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10522 23:14:58.018834 <6>[ 1.971928] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10523 23:14:58.022185 <6>[ 1.972098] xhci-mtk 11200000.usb: xHCI Host Controller
10524 23:14:58.032332 <6>[ 1.972121] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10525 23:14:58.038924 <6>[ 1.972132] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10526 23:14:58.041983 <6>[ 1.972243] mmcblk0: mmc0:0001 DA4128 116 GiB
10527 23:14:58.048931 <6>[ 1.972911] hub 1-0:1.0: USB hub found
10528 23:14:58.052026 <6>[ 1.972952] hub 1-0:1.0: 1 port detected
10529 23:14:58.058816 <6>[ 1.973247] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10530 23:14:58.065149 <6>[ 1.973872] hub 2-0:1.0: USB hub found
10531 23:14:58.068381 <6>[ 1.973890] hub 2-0:1.0: 1 port detected
10532 23:14:58.075346 <6>[ 1.976013] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10533 23:14:58.078602 <6>[ 1.977169] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10534 23:14:58.085261 <6>[ 1.978127] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10535 23:14:58.088388 <6>[ 1.978291] mtk-msdc 11f70000.mmc: Got CD GPIO
10536 23:14:58.095348 <6>[ 1.978753] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10537 23:14:58.104617 <6>[ 1.992829] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10538 23:14:58.111347 <6>[ 1.992837] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10539 23:14:58.121727 <4>[ 1.992998] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10540 23:14:58.127903 <6>[ 1.993685] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10541 23:14:58.137640 <6>[ 1.993690] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10542 23:14:58.144446 <6>[ 1.993840] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10543 23:14:58.151290 <6>[ 1.993854] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10544 23:14:58.161081 <6>[ 1.993858] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10545 23:14:58.167519 <6>[ 1.993863] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10546 23:14:58.177674 <6>[ 1.995318] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10547 23:14:58.184284 <6>[ 1.995336] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10548 23:14:58.193658 <6>[ 1.995342] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10549 23:14:58.200920 <6>[ 1.995349] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10550 23:14:58.210516 <6>[ 1.995355] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10551 23:14:58.220566 <6>[ 1.995362] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10552 23:14:58.226901 <6>[ 1.995368] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10553 23:14:58.236684 <6>[ 1.995374] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10554 23:14:58.243423 <6>[ 1.995381] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10555 23:14:58.253291 <6>[ 1.995387] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10556 23:14:58.259836 <6>[ 1.995393] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10557 23:14:58.270203 <6>[ 1.995399] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10558 23:14:58.276381 <6>[ 1.995405] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10559 23:14:58.286615 <6>[ 1.995412] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10560 23:14:58.292817 <6>[ 1.995418] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10561 23:14:58.299776 <6>[ 1.995913] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10562 23:14:58.306251 <6>[ 1.996740] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10563 23:14:58.313044 <6>[ 1.997276] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10564 23:14:58.319488 <6>[ 1.997906] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10565 23:14:58.325932 <6>[ 1.998532] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10566 23:14:58.335904 <6>[ 1.998725] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10567 23:14:58.345971 <6>[ 1.998739] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10568 23:14:58.355974 <6>[ 1.998744] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10569 23:14:58.362250 <6>[ 1.998749] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10570 23:14:58.372597 <6>[ 1.998755] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10571 23:14:58.382366 <6>[ 1.998761] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10572 23:14:58.392522 <6>[ 1.998766] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10573 23:14:58.401816 <6>[ 1.998771] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10574 23:14:58.408670 <6>[ 1.998775] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10575 23:14:58.422371 <6>[ 1.998782] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10576 23:14:58.432121 <6>[ 1.998787] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10577 23:14:58.438462 <6>[ 1.999715] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10578 23:14:58.445292 <6>[ 2.393522] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10579 23:14:58.448627 <6>[ 2.546437] hub 1-1:1.0: USB hub found
10580 23:14:58.455055 <6>[ 2.546800] hub 1-1:1.0: 4 ports detected
10581 23:14:58.458200 <6>[ 2.550734] hub 1-1:1.0: USB hub found
10582 23:14:58.461535 <6>[ 2.551082] hub 1-1:1.0: 4 ports detected
10583 23:14:58.503551 <6>[ 2.673722] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10584 23:14:58.523656 <6>[ 2.698856] hub 2-1:1.0: USB hub found
10585 23:14:58.527391 <6>[ 2.699276] hub 2-1:1.0: 3 ports detected
10586 23:14:58.530547 <6>[ 2.702276] hub 2-1:1.0: USB hub found
10587 23:14:58.533985 <6>[ 2.702676] hub 2-1:1.0: 3 ports detected
10588 23:14:58.690923 <6>[ 2.861726] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10589 23:14:58.812250 <6>[ 2.988983] hub 1-1.4:1.0: USB hub found
10590 23:14:58.815167 <6>[ 2.989340] hub 1-1.4:1.0: 2 ports detected
10591 23:14:58.818700 <6>[ 2.992569] hub 1-1.4:1.0: USB hub found
10592 23:14:58.825231 <6>[ 2.992860] hub 1-1.4:1.0: 2 ports detected
10593 23:14:58.895160 <6>[ 3.065839] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10594 23:14:59.111092 <6>[ 3.281691] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10595 23:14:59.295297 <6>[ 3.465696] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10596 23:15:10.127326 <6>[ 14.306679] ALSA device list:
10597 23:15:10.134102 <6>[ 14.306701] No soundcards found.
10598 23:15:10.137568 <6>[ 14.311136] Freeing unused kernel memory: 8448K
10599 23:15:10.140455 <6>[ 14.311221] Run /init as init process
10600 23:15:10.162680 <6>[ 14.339701] NET: Registered PF_INET6 protocol family
10601 23:15:10.165442 <6>[ 14.340579] Segment Routing with IPv6
10602 23:15:10.168660 <6>[ 14.340593] In-situ OAM (IOAM) with IPv6
10603 23:15:10.176144
10604 23:15:10.199455 Welcome to [1mDebian GNU/Linu<30>[ 14.358094] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10605 23:15:10.206544 x 11 (bullseye)<30>[ 14.358570] systemd[1]: Detected architecture arm64.
10606 23:15:10.209702 [0m!
10607 23:15:10.210123
10608 23:15:10.226927 <30>[ 14.401753] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10609 23:15:10.385888 <30>[ 14.558200] systemd[1]: Queued start job for default target Graphical Interface.
10610 23:15:10.431127 [[0;32m OK [0m] Created slic<30>[ 14.606696] systemd[1]: Created slice system-getty.slice.
10611 23:15:10.434179 e [0;1;39msystem-getty.slice[0m.
10612 23:15:10.458435 [[0;32m OK [0m] Created slice [0;1;39msyste<30>[ 14.630574] systemd[1]: Created slice system-modprobe.slice.
10613 23:15:10.458553 m-modprobe.slice[0m.
10614 23:15:10.479776 [[0;32m OK [0m] Created slic<30>[ 14.655150] systemd[1]: Created slice system-serial\x2dgetty.slice.
10615 23:15:10.486198 e [0;1;39msystem-serial\x2dgetty.slice[0m.
10616 23:15:10.504365 [[0;32m OK [0m] Created slic<30>[ 14.679394] systemd[1]: Created slice User and Session Slice.
10617 23:15:10.507645 e [0;1;39mUser and Session Slice[0m.
10618 23:15:10.530327 [[0;32m OK [0m] Started [0;1;39mDispatch Pa<30>[ 14.702458] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10619 23:15:10.533371 ssword …ts to Console Directory Watch[0m.
10620 23:15:10.558632 [[0;32m OK [0m] Started [0;1;39mForward Pas<30>[ 14.730411] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10621 23:15:10.561517 sword R…uests to Wall Directory Watch[0m.
10622 23:15:10.589830 [[0;32m OK [0m] Reached target [0;1;39mLoca<30>[ 14.758140] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10623 23:15:10.596287 <30>[ 14.758435] systemd[1]: Reached target Local Encrypted Volumes.
10624 23:15:10.599569 l Encrypted Volumes[0m.
10625 23:15:10.618879 [[0;32m OK [0m] Reached target [0;1;39mPath<30>[ 14.794198] systemd[1]: Reached target Paths.
10626 23:15:10.619387 s[0m.
10627 23:15:10.641485 [[0;32m OK [0m] Reached target [0;1;39mRemo<30>[ 14.813674] systemd[1]: Reached target Remote File Systems.
10628 23:15:10.642034 te File Systems[0m.
10629 23:15:10.658294 [[0;32m OK [0m] Reached target [0;1;39mSlic<30>[ 14.833633] systemd[1]: Reached target Slices.
10630 23:15:10.658700 es[0m.
10631 23:15:10.678307 [[0;32m OK [0m] Reached target [0;1;39mSwap<30>[ 14.853661] systemd[1]: Reached target Swap.
10632 23:15:10.678763 [0m.
10633 23:15:10.701907 [[0;32m OK [0m] Listening on [0;1;39minitct<30>[ 14.874142] systemd[1]: Listening on initctl Compatibility Named Pipe.
10634 23:15:10.705074 l Compatibility Named Pipe[0m.
10635 23:15:10.723706 [[0;32m OK [0m] Listening on<30>[ 14.899030] systemd[1]: Listening on Journal Audit Socket.
10636 23:15:10.726790 [0;1;39mJournal Audit Socket[0m.
10637 23:15:10.747364 [[0;32m OK [0m] Listening on<30>[ 14.922810] systemd[1]: Listening on Journal Socket (/dev/log).
10638 23:15:10.750780 [0;1;39mJournal Socket (/dev/log)[0m.
10639 23:15:10.771269 [[0;32m OK [0m] Listening on<30>[ 14.946856] systemd[1]: Listening on Journal Socket.
10640 23:15:10.774527 [0;1;39mJournal Socket[0m.
10641 23:15:10.794126 [[0;32m OK [0m] Listening on [0;1;39mNetwor<30>[ 14.966319] systemd[1]: Listening on Network Service Netlink Socket.
10642 23:15:10.797427 k Service Netlink Socket[0m.
10643 23:15:10.815515 [[0;32m OK [0m] Listening on<30>[ 14.990883] systemd[1]: Listening on udev Control Socket.
10644 23:15:10.818452 [0;1;39mudev Control Socket[0m.
10645 23:15:10.838957 [[0;32m OK [0m] Listening on<30>[ 15.014698] systemd[1]: Listening on udev Kernel Socket.
10646 23:15:10.842235 [0;1;39mudev Kernel Socket[0m.
10647 23:15:10.889700 Mounting [0;1;39mHuge Pages File Syste<30>[ 15.061768] systemd[1]: Mounting Huge Pages File System...
10648 23:15:10.890184 m[0m...
10649 23:15:10.913605 Mounting [0;1;39mPOSIX Message Queue F<30>[ 15.085525] systemd[1]: Mounting POSIX Message Queue File System...
10650 23:15:10.914192 ile System[0m...
10651 23:15:10.934570 <30>[ 15.113337] systemd[1]: Mounting Kernel Debug File System...
10652 23:15:10.941026 Mounting [0;1;39mKernel Debug File System[0m...
10653 23:15:10.961944 <30>[ 15.134093] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10654 23:15:10.974928 Starting [0;1;39mCreate list of st…o<30>[ 15.138303] systemd[1]: Starting Create list of static device nodes for the current kernel...
10655 23:15:10.978176 des for the current kernel[0m...
10656 23:15:11.005426 Starting [0;1;39mLoad Kernel Module co<30>[ 15.177720] systemd[1]: Starting Load Kernel Module configfs...
10657 23:15:11.005932 nfigfs[0m...
10658 23:15:11.029776 Starting [0;1;39mLoad Kernel Module dr<30>[ 15.201720] systemd[1]: Starting Load Kernel Module drm...
10659 23:15:11.030261 m[0m...
10660 23:15:11.050146 <30>[ 15.221798] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10661 23:15:11.059579 Starting [0;1;39mJourn<30>[ 15.227142] systemd[1]: Starting Journal Service...
10662 23:15:11.060194 al Service[0m...
10663 23:15:11.080901 Startin<30>[ 15.256095] systemd[1]: Starting Load Kernel Modules...
10664 23:15:11.083558 g [0;1;39mLoad Kernel Modules[0m...
10665 23:15:11.107622 Starting [0;1;39mRemou<30>[ 15.282997] systemd[1]: Starting Remount Root and Kernel File Systems...
10666 23:15:11.113866 nt Root and Kernel File Systems[0m...
10667 23:15:11.130677 <30>[ 15.308981] systemd[1]: Starting Coldplug All udev Devices...
10668 23:15:11.137538 Starting [0;1;39mColdplug All udev Devices[0m...
10669 23:15:11.159989 [[0;32m OK [0m] Started [0;<30>[ 15.335347] systemd[1]: Started Journal Service.
10670 23:15:11.163317 1;39mJournal Service[0m.
10671 23:15:11.179330 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10672 23:15:11.195764 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10673 23:15:11.212555 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10674 23:15:11.231266 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10675 23:15:11.248249 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10676 23:15:11.264726 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10677 23:15:11.279932 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10678 23:15:11.300717 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10679 23:15:11.318920 See 'systemctl status systemd-remount-fs.service' for details.
10680 23:15:11.382047 Mounting [0;1;39mKernel Configuration File System[0m...
10681 23:15:11.401745 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10682 23:15:11.417749 <46>[ 15.591410] systemd-journald[190]: Received client request to flush runtime journal.
10683 23:15:11.425880 Starting [0;1;39mLoad/Save Random Seed[0m...
10684 23:15:11.448176 Starting [0;1;39mApply Kernel Variables[0m...
10685 23:15:11.468968 Starting [0;1;39mCreate System Users[0m...
10686 23:15:11.486970 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10687 23:15:11.505289 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10688 23:15:11.528066 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10689 23:15:11.544364 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10690 23:15:11.560790 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10691 23:15:11.576125 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10692 23:15:11.615574 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10693 23:15:11.643571 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10694 23:15:11.655401 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10695 23:15:11.670626 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10696 23:15:11.711746 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10697 23:15:11.735626 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10698 23:15:11.756587 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10699 23:15:11.778835 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10700 23:15:11.841902 Starting [0;1;39mNetwork Service[0m...
10701 23:15:11.867200 Starting [0;1;39mNetwork Time Synchronization[0m...
10702 23:15:11.892772 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10703 23:15:11.903106 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10704 23:15:11.918060 <6>[ 16.090402] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10705 23:15:11.924292 <6>[ 16.090472] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10706 23:15:11.934758 <6>[ 16.090486] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10707 23:15:11.949489 <6>[ 16.124436] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10708 23:15:11.953030 <6>[ 16.128398] remoteproc remoteproc0: scp is available
10709 23:15:11.959850 <6>[ 16.128505] remoteproc remoteproc0: powering up scp
10710 23:15:11.969686 <6>[ 16.128511] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10711 23:15:11.972875 <6>[ 16.128526] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10712 23:15:11.979802 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10713 23:15:11.997570 <3>[ 16.172976] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10714 23:15:12.004486 <3>[ 16.173002] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10715 23:15:12.014098 <3>[ 16.173013] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10716 23:15:12.027327 [[0;32m OK [0m] Started [0;1;39mNetwork Tim<3>[ 16.185024] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10717 23:15:12.034454 e Synchronizatio<3>[ 16.185054] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10718 23:15:12.037953 n[0m.
10719 23:15:12.044018 <3>[ 16.185062] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10720 23:15:12.054187 <3>[ 16.185075] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10721 23:15:12.060616 <3>[ 16.185082] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10722 23:15:12.067589 <4>[ 16.189525] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10723 23:15:12.077537 <3>[ 16.194278] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10724 23:15:12.084025 <4>[ 16.194325] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10725 23:15:12.090713 <3>[ 16.211721] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10726 23:15:12.100885 [[0;32m OK [<3>[ 16.211765] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10727 23:15:12.110340 0m] Found device<3>[ 16.211777] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10728 23:15:12.120724 [0;1;39m/dev/t<6>[ 16.212829] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10729 23:15:12.121342 tyS0[0m.
10730 23:15:12.127565 <6>[ 16.212875] pci_bus 0000:00: root bus resource [bus 00-ff]
10731 23:15:12.134187 <6>[ 16.212889] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10732 23:15:12.143944 <6>[ 16.212897] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10733 23:15:12.150622 <6>[ 16.212973] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10734 23:15:12.157268 <6>[ 16.213006] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10735 23:15:12.163971 <6>[ 16.213121] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10736 23:15:12.170476 <6>[ 16.213143] pci 0000:00:00.0: supports D1 D2
10737 23:15:12.177322 <6>[ 16.213148] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10738 23:15:12.187324 <6>[ 16.216109] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10739 23:15:12.193899 <3>[ 16.216934] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10740 23:15:12.200460 <3>[ 16.216969] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10741 23:15:12.210269 <3>[ 16.216981] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10742 23:15:12.216660 <3>[ 16.216987] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10743 23:15:12.226621 <3>[ 16.216991] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10744 23:15:12.233391 <3>[ 16.221293] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10745 23:15:12.240004 <6>[ 16.221529] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10746 23:15:12.249906 [[0;32m OK [<6>[ 16.221557] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10747 23:15:12.260105 0m] Created slic<6>[ 16.221576] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10748 23:15:12.266160 <6>[ 16.221590] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10749 23:15:12.269709 <6>[ 16.221701] pci 0000:01:00.0: supports D1 D2
10750 23:15:12.279300 e [0;1;39msyste<6>[ 16.221703] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10751 23:15:12.283048 <6>[ 16.222931] mc: Linux media interface: v0.10
10752 23:15:12.292489 <6>[ 16.257914] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10753 23:15:12.299546 <6>[ 16.257929] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10754 23:15:12.306183 m-systemd\x2dbac<6>[ 16.257930] remoteproc remoteproc0: remote processor scp is now up
10755 23:15:12.315798 klight.slice[0m<6>[ 16.259757] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10756 23:15:12.322685 <6>[ 16.259811] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10757 23:15:12.332244 <6>[ 16.259818] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10758 23:15:12.338975 <6>[ 16.259832] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10759 23:15:12.339404 .
10760 23:15:12.345373 <6>[ 16.259848] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10761 23:15:12.355570 <6>[ 16.259864] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10762 23:15:12.358931 <6>[ 16.259880] pci 0000:00:00.0: PCI bridge to [bus 01]
10763 23:15:12.369190 <6>[ 16.259888] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10764 23:15:12.375204 <6>[ 16.260353] videodev: Linux video capture interface: v2.00
10765 23:15:12.381939 <6>[ 16.260393] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10766 23:15:12.385414 <6>[ 16.264717] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10767 23:15:12.395470 [[0;32m OK [<6>[ 16.270673] usbcore: registered new interface driver r8152
10768 23:15:12.401905 0m] Reached targ<6>[ 16.271178] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10769 23:15:12.411958 <6>[ 16.306048] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10770 23:15:12.421939 <6>[ 16.338114] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10771 23:15:12.428213 <6>[ 16.340409] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10772 23:15:12.438734 et [0;1;39mSyst<6>[ 16.354384] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10773 23:15:12.444964 <6>[ 16.356019] usbcore: registered new interface driver cdc_ether
10774 23:15:12.451459 <6>[ 16.380349] usbcore: registered new interface driver r8153_ecm
10775 23:15:12.454898 <6>[ 16.387226] Bluetooth: Core ver 2.22
10776 23:15:12.461418 <4>[ 16.387343] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10777 23:15:12.471673 <4>[ 16.387350] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10778 23:15:12.478502 <6>[ 16.387946] NET: Registered PF_BLUETOOTH protocol family
10779 23:15:12.484646 <6>[ 16.387951] Bluetooth: HCI device and connection manager initialized
10780 23:15:12.487955 <6>[ 16.387979] Bluetooth: HCI socket layer initialized
10781 23:15:12.494400 <6>[ 16.387985] Bluetooth: L2CAP socket layer initialized
10782 23:15:12.497813 <6>[ 16.388001] Bluetooth: SCO socket layer initialized
10783 23:15:12.507618 <5>[ 16.389616] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10784 23:15:12.514791 <5>[ 16.400872] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10785 23:15:12.521344 <4>[ 16.400949] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10786 23:15:12.527890 <6>[ 16.400957] cfg80211: failed to load regulatory.db
10787 23:15:12.534629 <6>[ 16.405039] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10788 23:15:12.544255 <6>[ 16.419570] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10789 23:15:12.554492 <6>[ 16.420783] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10790 23:15:12.560991 <6>[ 16.421000] usbcore: registered new interface driver uvcvideo
10791 23:15:12.571211 <6>[ 16.421267] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10792 23:15:12.577262 <6>[ 16.446314] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10793 23:15:12.580889 <6>[ 16.451353] usbcore: registered new interface driver btusb
10794 23:15:12.594229 <4>[ 16.452037] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10795 23:15:12.597420 <3>[ 16.452063] Bluetooth: hci0: Failed to load firmware file (-2)
10796 23:15:12.604135 <3>[ 16.452068] Bluetooth: hci0: Failed to set up firmware (-2)
10797 23:15:12.613666 <4>[ 16.452076] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10798 23:15:12.620505 <6>[ 16.474256] r8152 2-1.3:1.0 eth0: v1.12.13
10799 23:15:12.623909 <6>[ 16.493539] r8152 2-1.3:1.0 enx00e04c787aaa: renamed from eth0
10800 23:15:12.633730 <6>[ 16.495718] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10801 23:15:12.640623 <6>[ 16.495825] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10802 23:15:12.646888 em Time Set[0m.<6>[ 16.516203] mt7921e 0000:01:00.0: ASIC revision: 79610010
10803 23:15:12.657213 <4>[ 16.612295] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10804 23:15:12.670052 <4>[ 16.719193] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10805 23:15:12.679870 <4>[ 16.823689] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10806 23:15:12.680301
10807 23:15:12.701448 [[0;32m OK [0m] Reached target [0;1;39mSyst<4>[ 16.875211] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10808 23:15:12.708012 <4>[ 16.875211] Fallback method does not support PEC.
10809 23:15:12.711430 em Time Synchronized[0m.
10810 23:15:12.726059 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10811 23:15:12.765739 <4>[ 16.933612] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10812 23:15:12.772372 <3>[ 16.939299] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10813 23:15:12.782439 <3>[ 16.940673] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10814 23:15:12.792338 <3>[ 16.946275] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10815 23:15:12.813424 <3>[ 16.987005] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10816 23:15:12.823649 <3>[ 16.988078] power_supply sbs-5-000b: driver failed to report `capacity_error_margin' property: -6
10817 23:15:12.837982 <3>[ 17.010389] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10818 23:15:12.843935 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10819 23:15:12.869606 <3>[ 17.045162] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10820 23:15:12.880094 <4>[ 17.045193] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10821 23:15:12.887136 Starting [0;1;39mNetwork Name Resolution[0m...
10822 23:15:12.897190 <3>[ 17.069763] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10823 23:15:12.919059 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of l<3>[ 17.091625] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10824 23:15:12.919202 eds:white:kbd_backlight[0m.
10825 23:15:12.937557 <3>[ 17.112754] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10826 23:15:12.944447 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10827 23:15:12.984774 <4>[ 17.157165] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10828 23:15:13.005230 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10829 23:15:13.018967 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10830 23:15:13.038267 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10831 23:15:13.050546 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10832 23:15:13.074757 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10833 23:15:13.096771 [[0;32m OK [0m] Started [0;1;39mDaily Clean<4>[ 17.267572] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10834 23:15:13.100243 up of Temporary Directories[0m.
10835 23:15:13.119425 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10836 23:15:13.143191 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10837 23:15:13.159013 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10838 23:15:13.178858 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10839 23:15:13.204825 <4>[ 17.375990] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10840 23:15:13.220350 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10841 23:15:13.253034 Starting [0;1;39mUser Login Management[0m...
10842 23:15:13.275581 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10843 23:15:13.305986 Starting [0;1;39mPermit User Sessions[0m...
10844 23:15:13.321341 <4>[ 17.488460] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10845 23:15:13.329537 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10846 23:15:13.349048 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10847 23:15:13.428952 [[0;32m OK [0m] Started [0;1;39mGetty on tt<4>[ 17.599978] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10848 23:15:13.429517 y1[0m.
10849 23:15:13.452076 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10850 23:15:13.467187 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10851 23:15:13.484025 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10852 23:15:13.501097 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10853 23:15:13.524621 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10854 23:15:13.531332 <3>[ 17.706612] mt7921e 0000:01:00.0: hardware init failed
10855 23:15:13.581307 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10856 23:15:13.616412 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10857 23:15:13.657301
10858 23:15:13.657906
10859 23:15:13.660983 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10860 23:15:13.661536
10861 23:15:13.663924 debian-bullseye-arm64 login: root (automatic login)
10862 23:15:13.664537
10863 23:15:13.664907
10864 23:15:13.691340 Linux debian-bullseye-arm64 6.1.64-cip10-rt5 #1 SMP PREEMPT Sun Dec 3 22:38:18 UTC 2023 aarch64
10865 23:15:13.691902
10866 23:15:13.697846 The programs included with the Debian GNU/Linux system are free software;
10867 23:15:13.704337 the exact distribution terms for each program are described in the
10868 23:15:13.707827 individual files in /usr/share/doc/*/copyright.
10869 23:15:13.708289
10870 23:15:13.714605 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10871 23:15:13.717726 permitted by applicable law.
10872 23:15:13.719063 Matched prompt #10: / #
10874 23:15:13.720148 Setting prompt string to ['/ #']
10875 23:15:13.720615 end: 2.2.5.1 login-action (duration 00:00:19) [common]
10877 23:15:13.721711 end: 2.2.5 auto-login-action (duration 00:00:19) [common]
10878 23:15:13.722190 start: 2.2.6 expect-shell-connection (timeout 00:03:30) [common]
10879 23:15:13.722568 Setting prompt string to ['/ #']
10880 23:15:13.722910 Forcing a shell prompt, looking for ['/ #']
10882 23:15:13.773774 / #
10883 23:15:13.774422 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10884 23:15:13.775022 Waiting using forced prompt support (timeout 00:02:30)
10885 23:15:13.779945
10886 23:15:13.780881 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10887 23:15:13.781392 start: 2.2.7 export-device-env (timeout 00:03:30) [common]
10888 23:15:13.781941 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10889 23:15:13.782433 end: 2.2 depthcharge-retry (duration 00:01:30) [common]
10890 23:15:13.782905 end: 2 depthcharge-action (duration 00:01:30) [common]
10891 23:15:13.783388 start: 3 lava-test-retry (timeout 00:08:11) [common]
10892 23:15:13.783859 start: 3.1 lava-test-shell (timeout 00:08:11) [common]
10893 23:15:13.784259 Using namespace: common
10895 23:15:13.885420 / # #
10896 23:15:13.886123 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
10897 23:15:13.891928 #
10898 23:15:13.892809 Using /lava-12172417
10900 23:15:13.994067 / # export SHELL=/bin/sh
10901 23:15:13.994893 <6>[ 18.106036] IPv6: ADDRCONF(NETDEV_CHANGE): enx00e04c787aaa: link becomes ready
10902 23:15:13.995472 <6>[ 18.106540] r8152 2-1.3:1.0 enx00e04c787aaa: carrier on
10903 23:15:14.001045 export SHELL=/bin/sh
10905 23:15:14.102844 / # . /lava-12172417/environment
10906 23:15:14.109750 . /lava-12172417/environment
10908 23:15:14.211526 / # /lava-12172417/bin/lava-test-runner /lava-12172417/0
10909 23:15:14.212127 Test shell timeout: 10s (minimum of the action and connection timeout)
10910 23:15:14.218291 /lava-12172417/bin/lava-test-runner /lava-12172417/0
10911 23:15:14.243517 + export TESTRUN_ID=0_v4l2-compliance-mtk-vcodec-enc
10912 23:15:14.250539 + cd /lava-12172417/0/tests/0_v4l2-compliance-mtk-vcodec-enc
10913 23:15:14.250680 + cat uuid
10914 23:15:14.253845 + UUID=12172417_1.5.2.3.1
10915 23:15:14.253980 + set +x
10916 23:15:14.260347 <LAVA_SIGNAL_STARTRUN 0_v4l2-compliance-mtk-vcodec-enc 12172417_1.5.2.3.1>
10917 23:15:14.260633 Received signal: <STARTRUN> 0_v4l2-compliance-mtk-vcodec-enc 12172417_1.5.2.3.1
10918 23:15:14.260730 Starting test lava.0_v4l2-compliance-mtk-vcodec-enc (12172417_1.5.2.3.1)
10919 23:15:14.260839 Skipping test definition patterns.
10920 23:15:14.263817 + /usr/bin/v4l2-parser.sh -d mtk-vcodec-enc
10921 23:15:14.270021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=device-presence RESULT=pass>
10922 23:15:14.270278 Received signal: <TESTCASE> TEST_CASE_ID=device-presence RESULT=pass
10924 23:15:14.276985 device: /dev/vide<4>[ 18.451516] use of bytesused == 0 is deprecated and will be removed in the future,
10925 23:15:14.283321 <4>[ 18.451526] use the actual size instead.
10926 23:15:14.283405 o2
10927 23:15:14.286669 v4l2-compliance 1.25.0-1, 64 bits, 64-bit time_t
10928 23:15:14.293526 v4l2-compliance SHA: 16e70e28584c 2023-06-22 09:47:27
10929 23:15:14.300606
10930 23:15:14.313144 Compliance test for mtk-vcodec-enc device /dev/video2:
10931 23:15:14.319025
10932 23:15:14.329019 Driver Info:
10933 23:15:14.339482 Driver name : mtk-vcodec-enc
10934 23:15:14.353932 Card type : MT8192 video encoder
10935 23:15:14.366195 Bus info : platform:17020000.vcodec
10936 23:15:14.374102 Driver version : 6.1.64
10937 23:15:14.385560 Capabilities : 0x84204000
10938 23:15:14.395111 Video Memory-to-Memory Multiplanar
10939 23:15:14.406539 Streaming
10940 23:15:14.416827 Extended Pix Format
10941 23:15:14.425553 Device Capabilities
10942 23:15:14.435889 Device Caps : 0x04204000
10943 23:15:14.447489 Video Memory-to-Memory Multiplanar
10944 23:15:14.459375 Streaming
10945 23:15:14.475119 Extended Pix Format
10946 23:15:14.487004 Detected Stateful Encoder
10947 23:15:14.500206
10948 23:15:14.511515 Required ioctls:
10949 23:15:14.530898 <LAVA_SIGNAL_TESTSET START Required-ioctls>
10950 23:15:14.531056 test VIDIOC_QUERYCAP: OK
10951 23:15:14.531372 Received signal: <TESTSET> START Required-ioctls
10952 23:15:14.531514 Starting test_set Required-ioctls
10953 23:15:14.553525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
10954 23:15:14.553815 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
10956 23:15:14.556657 test invalid ioctls: OK
10957 23:15:14.577517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-ioctls RESULT=pass>
10958 23:15:14.577657
10959 23:15:14.577903 Received signal: <TESTCASE> TEST_CASE_ID=invalid-ioctls RESULT=pass
10961 23:15:14.588584 Allow for multiple opens:
10962 23:15:14.597478 <LAVA_SIGNAL_TESTSET STOP>
10963 23:15:14.597791 Received signal: <TESTSET> STOP
10964 23:15:14.597869 Closing test_set Required-ioctls
10965 23:15:14.609446 <LAVA_SIGNAL_TESTSET START Allow-for-multiple-opens>
10966 23:15:14.609700 Received signal: <TESTSET> START Allow-for-multiple-opens
10967 23:15:14.609772 Starting test_set Allow-for-multiple-opens
10968 23:15:14.612422 test second /dev/video2 open: OK
10969 23:15:14.633335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=second-/dev/video2-open RESULT=pass>
10970 23:15:14.633634 Received signal: <TESTCASE> TEST_CASE_ID=second-/dev/video2-open RESULT=pass
10972 23:15:14.636398 test VIDIOC_QUERYCAP: OK
10973 23:15:14.658929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
10974 23:15:14.659206 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
10976 23:15:14.662463 test VIDIOC_G/S_PRIORITY: OK
10977 23:15:14.683305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass>
10978 23:15:14.683588 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass
10980 23:15:14.686875 test for unlimited opens: OK
10981 23:15:14.708984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=for-unlimited-opens RESULT=pass>
10982 23:15:14.709079
10983 23:15:14.709315 Received signal: <TESTCASE> TEST_CASE_ID=for-unlimited-opens RESULT=pass
10985 23:15:14.718692 Debug ioctls:
10986 23:15:14.725748 <LAVA_SIGNAL_TESTSET STOP>
10987 23:15:14.726000 Received signal: <TESTSET> STOP
10988 23:15:14.726084 Closing test_set Allow-for-multiple-opens
10989 23:15:14.735294 <LAVA_SIGNAL_TESTSET START Debug-ioctls>
10990 23:15:14.735547 Received signal: <TESTSET> START Debug-ioctls
10991 23:15:14.735615 Starting test_set Debug-ioctls
10992 23:15:14.738283 test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
10993 23:15:14.760250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass>
10994 23:15:14.760516 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass
10996 23:15:14.766608 test VIDIOC_LOG_STATUS: OK (Not Supported)
10997 23:15:14.786236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass>
10998 23:15:14.786336
10999 23:15:14.786573 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass
11001 23:15:14.796502 Input ioctls:
11002 23:15:14.803963 <LAVA_SIGNAL_TESTSET STOP>
11003 23:15:14.804218 Received signal: <TESTSET> STOP
11004 23:15:14.804288 Closing test_set Debug-ioctls
11005 23:15:14.813023 <LAVA_SIGNAL_TESTSET START Input-ioctls>
11006 23:15:14.813275 Received signal: <TESTSET> START Input-ioctls
11007 23:15:14.813346 Starting test_set Input-ioctls
11008 23:15:14.816241 test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
11009 23:15:14.841468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass>
11010 23:15:14.841782 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass
11012 23:15:14.844562 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11013 23:15:14.864057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11014 23:15:14.864392 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11016 23:15:14.870119 test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
11017 23:15:14.888440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass>
11018 23:15:14.888724 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass
11020 23:15:14.894823 test VIDIOC_ENUMAUDIO: OK (Not Supported)
11021 23:15:14.913886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass>
11022 23:15:14.914157 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass
11024 23:15:14.917159 test VIDIOC_G/S/ENUMINPUT: OK (Not Supported)
11025 23:15:14.942751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass>
11026 23:15:14.943093 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass
11028 23:15:14.946397 test VIDIOC_G/S_AUDIO: OK (Not Supported)
11029 23:15:14.968524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass>
11030 23:15:14.968861 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass
11032 23:15:14.971939 Inputs: 0 Audio Inputs: 0 Tuners: 0
11033 23:15:14.979451
11034 23:15:14.997256 test VIDIOC_G/S_MODULATOR: OK (Not Supported)
11035 23:15:15.021245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass>
11036 23:15:15.021843 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass
11038 23:15:15.028179 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11039 23:15:15.047160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11040 23:15:15.047956 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11042 23:15:15.054079 test VIDIOC_ENUMAUDOUT: OK (Not Supported)
11043 23:15:15.071750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass>
11044 23:15:15.072500 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass
11046 23:15:15.078199 test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
11047 23:15:15.098328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass>
11048 23:15:15.099156 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass
11050 23:15:15.105049 test VIDIOC_G/S_AUDOUT: OK (Not Supported)
11051 23:15:15.122191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass>
11052 23:15:15.122715
11053 23:15:15.123313 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass
11055 23:15:15.141618 test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
11056 23:15:15.168080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass>
11057 23:15:15.168447 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass
11059 23:15:15.174544 test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
11060 23:15:15.195442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass>
11061 23:15:15.195936 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass
11063 23:15:15.198846 test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
11064 23:15:15.221858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass>
11065 23:15:15.222677 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass
11067 23:15:15.224944 test VIDIOC_G/S_EDID: OK (Not Supported)
11068 23:15:15.246934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass>
11069 23:15:15.247092
11070 23:15:15.247354 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass
11072 23:15:15.257021 Control ioctls:
11073 23:15:15.264797 <LAVA_SIGNAL_TESTSET STOP>
11074 23:15:15.265149 Received signal: <TESTSET> STOP
11075 23:15:15.265236 Closing test_set Input-ioctls
11076 23:15:15.274112 <LAVA_SIGNAL_TESTSET START Control-ioctls>
11077 23:15:15.274477 Received signal: <TESTSET> START Control-ioctls
11078 23:15:15.274597 Starting test_set Control-ioctls
11079 23:15:15.277278 test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
11080 23:15:15.307715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass>
11081 23:15:15.307917 test VIDIOC_QUERYCTRL: OK
11082 23:15:15.308215 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass
11084 23:15:15.334706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass>
11085 23:15:15.335362 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass
11087 23:15:15.337847 test VIDIOC_G/S_CTRL: OK
11088 23:15:15.358489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass>
11089 23:15:15.359272 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass
11091 23:15:15.361856 test VIDIOC_G/S/TRY_EXT_CTRLS: OK
11092 23:15:15.382774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass>
11093 23:15:15.383598 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass
11095 23:15:15.392608 fail: ../utils/v4l2-compliance/v4l2-test-controls.cpp(1167): node->codec_mask & STATEFUL_ENCODER
11096 23:15:15.395920 test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: FAIL
11097 23:15:15.425520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=fail>
11098 23:15:15.426516 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=fail
11100 23:15:15.428127 test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
11101 23:15:15.447286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass>
11102 23:15:15.447982 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass
11104 23:15:15.450511 Standard Controls: 16 Private Controls: 0
11105 23:15:15.460418
11106 23:15:15.471603 Format ioctls:
11107 23:15:15.479253 <LAVA_SIGNAL_TESTSET STOP>
11108 23:15:15.480050 Received signal: <TESTSET> STOP
11109 23:15:15.480456 Closing test_set Control-ioctls
11110 23:15:15.491140 <LAVA_SIGNAL_TESTSET START Format-ioctls>
11111 23:15:15.491979 Received signal: <TESTSET> START Format-ioctls
11112 23:15:15.492374 Starting test_set Format-ioctls
11113 23:15:15.493931 test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
11114 23:15:15.520882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass>
11115 23:15:15.521723 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass
11117 23:15:15.523381 test VIDIOC_G/S_PARM: OK
11118 23:15:15.546915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass>
11119 23:15:15.547743 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass
11121 23:15:15.549672 test VIDIOC_G_FBUF: OK (Not Supported)
11122 23:15:15.577108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass>
11123 23:15:15.577966 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass
11125 23:15:15.580451 test VIDIOC_G_FMT: OK
11126 23:15:15.605812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass>
11127 23:15:15.606636 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass
11129 23:15:15.608583 test VIDIOC_TRY_FMT: OK
11130 23:15:15.630223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass>
11131 23:15:15.631077 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass
11133 23:15:15.640329 fail: ../utils/v4l2-compliance/v4l2-test-formats.cpp(924): sel.r.width != fmt.g_width()
11134 23:15:15.643504 test VIDIOC_S_FMT: FAIL
11135 23:15:15.671540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_FMT RESULT=fail>
11136 23:15:15.672529 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_FMT RESULT=fail
11138 23:15:15.674118 test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
11139 23:15:15.695133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass>
11140 23:15:15.695972 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass
11142 23:15:15.698532 test Cropping: OK
11143 23:15:15.723152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Cropping RESULT=pass>
11144 23:15:15.723991 Received signal: <TESTCASE> TEST_CASE_ID=Cropping RESULT=pass
11146 23:15:15.726116 test Composing: OK (Not Supported)
11147 23:15:15.748673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Composing RESULT=pass>
11148 23:15:15.749547 Received signal: <TESTCASE> TEST_CASE_ID=Composing RESULT=pass
11150 23:15:15.751728 test Scaling: OK (Not Supported)
11151 23:15:15.773407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Scaling RESULT=pass>
11152 23:15:15.774021
11153 23:15:15.774669 Received signal: <TESTCASE> TEST_CASE_ID=Scaling RESULT=pass
11155 23:15:15.783860 Codec ioctls:
11156 23:15:15.791970 <LAVA_SIGNAL_TESTSET STOP>
11157 23:15:15.792797 Received signal: <TESTSET> STOP
11158 23:15:15.793247 Closing test_set Format-ioctls
11159 23:15:15.801266 <LAVA_SIGNAL_TESTSET START Codec-ioctls>
11160 23:15:15.802127 Received signal: <TESTSET> START Codec-ioctls
11161 23:15:15.802533 Starting test_set Codec-ioctls
11162 23:15:15.804883 test VIDIOC_(TRY_)ENCODER_CMD: OK
11163 23:15:15.826828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass>
11164 23:15:15.827667 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass
11166 23:15:15.833095 test VIDIOC_G_ENC_INDEX: OK (Not Supported)
11167 23:15:15.852196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass>
11168 23:15:15.853041 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass
11170 23:15:15.859389 test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
11171 23:15:15.880912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass>
11172 23:15:15.881470
11173 23:15:15.882183 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass
11175 23:15:15.890558 Buffer ioctls:
11176 23:15:15.900329 <LAVA_SIGNAL_TESTSET STOP>
11177 23:15:15.901209 Received signal: <TESTSET> STOP
11178 23:15:15.901630 Closing test_set Codec-ioctls
11179 23:15:15.911930 <LAVA_SIGNAL_TESTSET START Buffer-ioctls>
11180 23:15:15.912758 Received signal: <TESTSET> START Buffer-ioctls
11181 23:15:15.913150 Starting test_set Buffer-ioctls
11182 23:15:15.915238 test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
11183 23:15:15.938745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass>
11184 23:15:15.939293 test VIDIOC_EXPBUF: OK
11185 23:15:15.939933 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass
11187 23:15:15.959916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass>
11188 23:15:15.960758 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass
11190 23:15:15.962718 test Requests: OK (Not Supported)
11191 23:15:15.985390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Requests RESULT=pass>
11192 23:15:15.986033
11193 23:15:15.986681 Received signal: <TESTCASE> TEST_CASE_ID=Requests RESULT=pass
11195 23:15:15.996537 Test input 0:
11196 23:15:16.005351
11197 23:15:16.016160 Streaming ioctls:
11198 23:15:16.023733 <LAVA_SIGNAL_TESTSET STOP>
11199 23:15:16.024591 Received signal: <TESTSET> STOP
11200 23:15:16.024973 Closing test_set Buffer-ioctls
11201 23:15:16.037104 <LAVA_SIGNAL_TESTSET START Streaming-ioctls_Test-input-0>
11202 23:15:16.037785 Received signal: <TESTSET> START Streaming-ioctls_Test-input-0
11203 23:15:16.038202 Starting test_set Streaming-ioctls_Test-input-0
11204 23:15:16.040203 test read/write: OK (Not Supported)
11205 23:15:16.062915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=read/write RESULT=pass>
11206 23:15:16.063748 Received signal: <TESTCASE> TEST_CASE_ID=read/write RESULT=pass
11208 23:15:16.069330 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(2798): node->streamon(q.g_type())
11209 23:15:16.079385 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(2845): testBlockingDQBuf(node, q)
11210 23:15:16.082700 test blocking wait: FAIL
11211 23:15:16.107198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blocking-wait RESULT=fail>
11212 23:15:16.108015 Received signal: <TESTCASE> TEST_CASE_ID=blocking-wait RESULT=fail
11214 23:15:16.116740 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1430): node->streamon(q.g_type())
11215 23:15:16.117447 test MMAP (select): FAIL
11216 23:15:16.140912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-select RESULT=fail>
11217 23:15:16.141731 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-select RESULT=fail
11219 23:15:16.147848 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1430): node->streamon(q.g_type())
11220 23:15:16.153114 test MMAP (epoll): FAIL
11221 23:15:16.183775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-epoll RESULT=fail>
11222 23:15:16.184595 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-epoll RESULT=fail
11224 23:15:16.193763 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1602): ret && ret != ENOTTY (got 22)
11225 23:15:16.200304 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1733): setupUserPtr(node, q)
11226 23:15:16.205878 test USERPTR (select): FAIL
11227 23:15:16.236450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-select RESULT=fail>
11228 23:15:16.237344 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-select RESULT=fail
11230 23:15:16.243438 test DMABUF: Cannot test, specify --expbuf-device
11231 23:15:16.247744
11232 23:15:16.266607 Total for mtk-vcodec-enc device /dev/video2: 50, Succeeded: 44, Failed: 6, Warnings: 0
11233 23:15:16.271213 <LAVA_TEST_RUNNER EXIT>
11234 23:15:16.272052 ok: lava_test_shell seems to have completed
11235 23:15:16.272462 Marking unfinished test run as failed
11237 23:15:16.277939 Composing:
result: pass
set: Format-ioctls
Cropping:
result: pass
set: Format-ioctls
MMAP-epoll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-select:
result: fail
set: Streaming-ioctls_Test-input-0
Requests:
result: pass
set: Buffer-ioctls
Scaling:
result: pass
set: Format-ioctls
USERPTR-select:
result: fail
set: Streaming-ioctls_Test-input-0
VIDIOC_DBG_G/S_REGISTER:
result: pass
set: Debug-ioctls
VIDIOC_DV_TIMINGS_CAP:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_STD:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDIO:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDOUT:
result: pass
set: Input-ioctls
VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS:
result: pass
set: Format-ioctls
VIDIOC_EXPBUF:
result: pass
set: Buffer-ioctls
VIDIOC_G/S/ENUMINPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/ENUMOUTPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/TRY_EXT_CTRLS:
result: pass
set: Control-ioctls
VIDIOC_G/S_AUDIO:
result: pass
set: Input-ioctls
VIDIOC_G/S_AUDOUT:
result: pass
set: Input-ioctls
VIDIOC_G/S_CTRL:
result: pass
set: Control-ioctls
VIDIOC_G/S_EDID:
result: pass
set: Input-ioctls
VIDIOC_G/S_FREQUENCY:
result: pass
set: Input-ioctls
VIDIOC_G/S_JPEGCOMP:
result: pass
set: Control-ioctls
VIDIOC_G/S_MODULATOR:
result: pass
set: Input-ioctls
VIDIOC_G/S_PARM:
result: pass
set: Format-ioctls
VIDIOC_G/S_PRIORITY:
result: pass
set: Allow-for-multiple-opens
VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS:
result: pass
set: Input-ioctls
VIDIOC_G_ENC_INDEX:
result: pass
set: Codec-ioctls
VIDIOC_G_FBUF:
result: pass
set: Format-ioctls
VIDIOC_G_FMT:
result: pass
set: Format-ioctls
VIDIOC_G_SLICED_VBI_CAP:
result: pass
set: Format-ioctls
VIDIOC_LOG_STATUS:
result: pass
set: Debug-ioctls
VIDIOC_QUERYCAP:
result: pass
set: Allow-for-multiple-opens
VIDIOC_QUERYCTRL:
result: pass
set: Control-ioctls
VIDIOC_QUERY_EXT_CTRL/QUERYMENU:
result: pass
set: Control-ioctls
VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF:
result: pass
set: Buffer-ioctls
VIDIOC_S_FMT:
result: fail
set: Format-ioctls
VIDIOC_S_HW_FREQ_SEEK:
result: pass
set: Input-ioctls
VIDIOC_TRY_DECODER_CMD:
result: pass
set: Codec-ioctls
VIDIOC_TRY_ENCODER_CMD:
result: pass
set: Codec-ioctls
VIDIOC_TRY_FMT:
result: pass
set: Format-ioctls
VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT:
result: fail
set: Control-ioctls
blocking-wait:
result: fail
set: Streaming-ioctls_Test-input-0
device-presence: pass
for-unlimited-opens:
result: pass
set: Allow-for-multiple-opens
invalid-ioctls:
result: pass
set: Required-ioctls
read/write:
result: pass
set: Streaming-ioctls_Test-input-0
second-/dev/video2-open:
result: pass
set: Allow-for-multiple-opens
11238 23:15:16.278602 end: 3.1 lava-test-shell (duration 00:00:02) [common]
11239 23:15:16.279074 end: 3 lava-test-retry (duration 00:00:02) [common]
11240 23:15:16.279564 start: 4 finalize (timeout 00:08:08) [common]
11241 23:15:16.280046 start: 4.1 power-off (timeout 00:00:30) [common]
11242 23:15:16.280795 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=off'
11243 23:15:16.372814 >> Command sent successfully.
11244 23:15:16.383257 Returned 0 in 0 seconds
11245 23:15:16.484583 end: 4.1 power-off (duration 00:00:00) [common]
11247 23:15:16.486044 start: 4.2 read-feedback (timeout 00:08:08) [common]
11248 23:15:16.487253 Listened to connection for namespace 'common' for up to 1s
11249 23:15:17.487915 Finalising connection for namespace 'common'
11250 23:15:17.488552 Disconnecting from shell: Finalise
11251 23:15:17.488935 / #
11252 23:15:17.589944 end: 4.2 read-feedback (duration 00:00:01) [common]
11253 23:15:17.590647 end: 4 finalize (duration 00:00:01) [common]
11254 23:15:17.591196 Cleaning after the job
11255 23:15:17.591670 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12172417/tftp-deploy-syndytqy/ramdisk
11256 23:15:17.616210 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12172417/tftp-deploy-syndytqy/kernel
11257 23:15:17.637542 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12172417/tftp-deploy-syndytqy/dtb
11258 23:15:17.637875 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12172417/tftp-deploy-syndytqy/modules
11259 23:15:17.648512 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12172417
11260 23:15:17.717471 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12172417
11261 23:15:17.717960 Job finished correctly