Boot log: mt8192-asurada-spherion-r0
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 22
- Kernel Errors: 33
- Errors: 0
1 23:30:43.867413 lava-dispatcher, installed at version: 2023.10
2 23:30:43.867631 start: 0 validate
3 23:30:43.867769 Start time: 2023-12-03 23:30:43.867760+00:00 (UTC)
4 23:30:43.867891 Using caching service: 'http://localhost/cache/?uri=%s'
5 23:30:43.868024 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20230623.0%2Farm64%2Finitrd.cpio.gz exists
6 23:30:44.155447 Using caching service: 'http://localhost/cache/?uri=%s'
7 23:30:44.155628 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.64-cip10-rt5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 23:30:44.421408 Using caching service: 'http://localhost/cache/?uri=%s'
9 23:30:44.421623 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.64-cip10-rt5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 23:30:44.679530 Using caching service: 'http://localhost/cache/?uri=%s'
11 23:30:44.679733 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20230623.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 23:30:44.945054 Using caching service: 'http://localhost/cache/?uri=%s'
13 23:30:44.945241 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.64-cip10-rt5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 23:30:45.211954 validate duration: 1.34
16 23:30:45.212220 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 23:30:45.212321 start: 1.1 download-retry (timeout 00:10:00) [common]
18 23:30:45.212410 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 23:30:45.212541 Not decompressing ramdisk as can be used compressed.
20 23:30:45.212627 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20230623.0/arm64/initrd.cpio.gz
21 23:30:45.212693 saving as /var/lib/lava/dispatcher/tmp/12172439/tftp-deploy-5nfpohkk/ramdisk/initrd.cpio.gz
22 23:30:45.212763 total size: 5625687 (5 MB)
23 23:30:45.213815 progress 0 % (0 MB)
24 23:30:45.215551 progress 5 % (0 MB)
25 23:30:45.217210 progress 10 % (0 MB)
26 23:30:45.218854 progress 15 % (0 MB)
27 23:30:45.220538 progress 20 % (1 MB)
28 23:30:45.222169 progress 25 % (1 MB)
29 23:30:45.223901 progress 30 % (1 MB)
30 23:30:45.225608 progress 35 % (1 MB)
31 23:30:45.227294 progress 40 % (2 MB)
32 23:30:45.228967 progress 45 % (2 MB)
33 23:30:45.230578 progress 50 % (2 MB)
34 23:30:45.232284 progress 55 % (2 MB)
35 23:30:45.234074 progress 60 % (3 MB)
36 23:30:45.235615 progress 65 % (3 MB)
37 23:30:45.237329 progress 70 % (3 MB)
38 23:30:45.238898 progress 75 % (4 MB)
39 23:30:45.240543 progress 80 % (4 MB)
40 23:30:45.242130 progress 85 % (4 MB)
41 23:30:45.243897 progress 90 % (4 MB)
42 23:30:45.245532 progress 95 % (5 MB)
43 23:30:45.247225 progress 100 % (5 MB)
44 23:30:45.247450 5 MB downloaded in 0.03 s (154.67 MB/s)
45 23:30:45.247627 end: 1.1.1 http-download (duration 00:00:00) [common]
47 23:30:45.247886 end: 1.1 download-retry (duration 00:00:00) [common]
48 23:30:45.247973 start: 1.2 download-retry (timeout 00:10:00) [common]
49 23:30:45.248057 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 23:30:45.248191 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.64-cip10-rt5/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 23:30:45.248264 saving as /var/lib/lava/dispatcher/tmp/12172439/tftp-deploy-5nfpohkk/kernel/Image
52 23:30:45.248325 total size: 49172992 (46 MB)
53 23:30:45.248387 No compression specified
54 23:30:45.249491 progress 0 % (0 MB)
55 23:30:45.263263 progress 5 % (2 MB)
56 23:30:45.277179 progress 10 % (4 MB)
57 23:30:45.291044 progress 15 % (7 MB)
58 23:30:45.304503 progress 20 % (9 MB)
59 23:30:45.317413 progress 25 % (11 MB)
60 23:30:45.330325 progress 30 % (14 MB)
61 23:30:45.343235 progress 35 % (16 MB)
62 23:30:45.356124 progress 40 % (18 MB)
63 23:30:45.369026 progress 45 % (21 MB)
64 23:30:45.382172 progress 50 % (23 MB)
65 23:30:45.395084 progress 55 % (25 MB)
66 23:30:45.408117 progress 60 % (28 MB)
67 23:30:45.421061 progress 65 % (30 MB)
68 23:30:45.434068 progress 70 % (32 MB)
69 23:30:45.446924 progress 75 % (35 MB)
70 23:30:45.459791 progress 80 % (37 MB)
71 23:30:45.473028 progress 85 % (39 MB)
72 23:30:45.486418 progress 90 % (42 MB)
73 23:30:45.499678 progress 95 % (44 MB)
74 23:30:45.512540 progress 100 % (46 MB)
75 23:30:45.512767 46 MB downloaded in 0.26 s (177.34 MB/s)
76 23:30:45.512921 end: 1.2.1 http-download (duration 00:00:00) [common]
78 23:30:45.513154 end: 1.2 download-retry (duration 00:00:00) [common]
79 23:30:45.513247 start: 1.3 download-retry (timeout 00:10:00) [common]
80 23:30:45.513334 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 23:30:45.513474 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.64-cip10-rt5/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 23:30:45.513545 saving as /var/lib/lava/dispatcher/tmp/12172439/tftp-deploy-5nfpohkk/dtb/mt8192-asurada-spherion-r0.dtb
83 23:30:45.513653 total size: 47278 (0 MB)
84 23:30:45.513718 No compression specified
85 23:30:45.514851 progress 69 % (0 MB)
86 23:30:45.515131 progress 100 % (0 MB)
87 23:30:45.515287 0 MB downloaded in 0.00 s (27.63 MB/s)
88 23:30:45.515411 end: 1.3.1 http-download (duration 00:00:00) [common]
90 23:30:45.515642 end: 1.3 download-retry (duration 00:00:00) [common]
91 23:30:45.515730 start: 1.4 download-retry (timeout 00:10:00) [common]
92 23:30:45.515815 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 23:30:45.515932 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20230623.0/arm64/full.rootfs.tar.xz
94 23:30:45.516001 saving as /var/lib/lava/dispatcher/tmp/12172439/tftp-deploy-5nfpohkk/nfsrootfs/full.rootfs.tar
95 23:30:45.516062 total size: 195204440 (186 MB)
96 23:30:45.516125 Using unxz to decompress xz
97 23:30:45.520244 progress 0 % (0 MB)
98 23:30:46.095732 progress 5 % (9 MB)
99 23:30:46.592763 progress 10 % (18 MB)
100 23:30:47.195080 progress 15 % (27 MB)
101 23:30:47.473597 progress 20 % (37 MB)
102 23:30:47.929349 progress 25 % (46 MB)
103 23:30:48.499251 progress 30 % (55 MB)
104 23:30:49.066631 progress 35 % (65 MB)
105 23:30:49.619681 progress 40 % (74 MB)
106 23:30:50.180201 progress 45 % (83 MB)
107 23:30:50.783654 progress 50 % (93 MB)
108 23:30:51.382820 progress 55 % (102 MB)
109 23:30:52.023613 progress 60 % (111 MB)
110 23:30:52.397884 progress 65 % (121 MB)
111 23:30:52.478606 progress 70 % (130 MB)
112 23:30:52.618246 progress 75 % (139 MB)
113 23:30:52.697858 progress 80 % (148 MB)
114 23:30:52.746896 progress 85 % (158 MB)
115 23:30:52.836801 progress 90 % (167 MB)
116 23:30:53.204252 progress 95 % (176 MB)
117 23:30:53.774099 progress 100 % (186 MB)
118 23:30:53.779092 186 MB downloaded in 8.26 s (22.53 MB/s)
119 23:30:53.779374 end: 1.4.1 http-download (duration 00:00:08) [common]
121 23:30:53.779683 end: 1.4 download-retry (duration 00:00:08) [common]
122 23:30:53.779800 start: 1.5 download-retry (timeout 00:09:51) [common]
123 23:30:53.779914 start: 1.5.1 http-download (timeout 00:09:51) [common]
124 23:30:53.780098 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.64-cip10-rt5/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 23:30:53.780225 saving as /var/lib/lava/dispatcher/tmp/12172439/tftp-deploy-5nfpohkk/modules/modules.tar
126 23:30:53.780300 total size: 8614132 (8 MB)
127 23:30:53.780403 Using unxz to decompress xz
128 23:30:53.784677 progress 0 % (0 MB)
129 23:30:53.805715 progress 5 % (0 MB)
130 23:30:53.829582 progress 10 % (0 MB)
131 23:30:53.853082 progress 15 % (1 MB)
132 23:30:53.876364 progress 20 % (1 MB)
133 23:30:53.900431 progress 25 % (2 MB)
134 23:30:53.925897 progress 30 % (2 MB)
135 23:30:53.952057 progress 35 % (2 MB)
136 23:30:53.975151 progress 40 % (3 MB)
137 23:30:53.999634 progress 45 % (3 MB)
138 23:30:54.024897 progress 50 % (4 MB)
139 23:30:54.049217 progress 55 % (4 MB)
140 23:30:54.073977 progress 60 % (4 MB)
141 23:30:54.099163 progress 65 % (5 MB)
142 23:30:54.125933 progress 70 % (5 MB)
143 23:30:54.149189 progress 75 % (6 MB)
144 23:30:54.176060 progress 80 % (6 MB)
145 23:30:54.201438 progress 85 % (7 MB)
146 23:30:54.226120 progress 90 % (7 MB)
147 23:30:54.255579 progress 95 % (7 MB)
148 23:30:54.283165 progress 100 % (8 MB)
149 23:30:54.289341 8 MB downloaded in 0.51 s (16.14 MB/s)
150 23:30:54.289593 end: 1.5.1 http-download (duration 00:00:01) [common]
152 23:30:54.289876 end: 1.5 download-retry (duration 00:00:01) [common]
153 23:30:54.289971 start: 1.6 prepare-tftp-overlay (timeout 00:09:51) [common]
154 23:30:54.290064 start: 1.6.1 extract-nfsrootfs (timeout 00:09:51) [common]
155 23:30:57.856760 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/12172439/extract-nfsrootfs-awh02hkz
156 23:30:57.856965 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 23:30:57.857064 start: 1.6.2 lava-overlay (timeout 00:09:47) [common]
158 23:30:57.857236 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12172439/lava-overlay-nxf13uu9
159 23:30:57.857367 makedir: /var/lib/lava/dispatcher/tmp/12172439/lava-overlay-nxf13uu9/lava-12172439/bin
160 23:30:57.857469 makedir: /var/lib/lava/dispatcher/tmp/12172439/lava-overlay-nxf13uu9/lava-12172439/tests
161 23:30:57.857568 makedir: /var/lib/lava/dispatcher/tmp/12172439/lava-overlay-nxf13uu9/lava-12172439/results
162 23:30:57.857735 Creating /var/lib/lava/dispatcher/tmp/12172439/lava-overlay-nxf13uu9/lava-12172439/bin/lava-add-keys
163 23:30:57.857883 Creating /var/lib/lava/dispatcher/tmp/12172439/lava-overlay-nxf13uu9/lava-12172439/bin/lava-add-sources
164 23:30:57.858017 Creating /var/lib/lava/dispatcher/tmp/12172439/lava-overlay-nxf13uu9/lava-12172439/bin/lava-background-process-start
165 23:30:57.858146 Creating /var/lib/lava/dispatcher/tmp/12172439/lava-overlay-nxf13uu9/lava-12172439/bin/lava-background-process-stop
166 23:30:57.858274 Creating /var/lib/lava/dispatcher/tmp/12172439/lava-overlay-nxf13uu9/lava-12172439/bin/lava-common-functions
167 23:30:57.858400 Creating /var/lib/lava/dispatcher/tmp/12172439/lava-overlay-nxf13uu9/lava-12172439/bin/lava-echo-ipv4
168 23:30:57.858527 Creating /var/lib/lava/dispatcher/tmp/12172439/lava-overlay-nxf13uu9/lava-12172439/bin/lava-install-packages
169 23:30:57.858653 Creating /var/lib/lava/dispatcher/tmp/12172439/lava-overlay-nxf13uu9/lava-12172439/bin/lava-installed-packages
170 23:30:57.858777 Creating /var/lib/lava/dispatcher/tmp/12172439/lava-overlay-nxf13uu9/lava-12172439/bin/lava-os-build
171 23:30:57.858903 Creating /var/lib/lava/dispatcher/tmp/12172439/lava-overlay-nxf13uu9/lava-12172439/bin/lava-probe-channel
172 23:30:57.859029 Creating /var/lib/lava/dispatcher/tmp/12172439/lava-overlay-nxf13uu9/lava-12172439/bin/lava-probe-ip
173 23:30:57.859155 Creating /var/lib/lava/dispatcher/tmp/12172439/lava-overlay-nxf13uu9/lava-12172439/bin/lava-target-ip
174 23:30:57.859281 Creating /var/lib/lava/dispatcher/tmp/12172439/lava-overlay-nxf13uu9/lava-12172439/bin/lava-target-mac
175 23:30:57.859407 Creating /var/lib/lava/dispatcher/tmp/12172439/lava-overlay-nxf13uu9/lava-12172439/bin/lava-target-storage
176 23:30:57.859535 Creating /var/lib/lava/dispatcher/tmp/12172439/lava-overlay-nxf13uu9/lava-12172439/bin/lava-test-case
177 23:30:57.859663 Creating /var/lib/lava/dispatcher/tmp/12172439/lava-overlay-nxf13uu9/lava-12172439/bin/lava-test-event
178 23:30:57.859788 Creating /var/lib/lava/dispatcher/tmp/12172439/lava-overlay-nxf13uu9/lava-12172439/bin/lava-test-feedback
179 23:30:57.859913 Creating /var/lib/lava/dispatcher/tmp/12172439/lava-overlay-nxf13uu9/lava-12172439/bin/lava-test-raise
180 23:30:57.860039 Creating /var/lib/lava/dispatcher/tmp/12172439/lava-overlay-nxf13uu9/lava-12172439/bin/lava-test-reference
181 23:30:57.860165 Creating /var/lib/lava/dispatcher/tmp/12172439/lava-overlay-nxf13uu9/lava-12172439/bin/lava-test-runner
182 23:30:57.860305 Creating /var/lib/lava/dispatcher/tmp/12172439/lava-overlay-nxf13uu9/lava-12172439/bin/lava-test-set
183 23:30:57.860436 Creating /var/lib/lava/dispatcher/tmp/12172439/lava-overlay-nxf13uu9/lava-12172439/bin/lava-test-shell
184 23:30:57.860564 Updating /var/lib/lava/dispatcher/tmp/12172439/lava-overlay-nxf13uu9/lava-12172439/bin/lava-add-keys (debian)
185 23:30:57.860717 Updating /var/lib/lava/dispatcher/tmp/12172439/lava-overlay-nxf13uu9/lava-12172439/bin/lava-add-sources (debian)
186 23:30:57.860858 Updating /var/lib/lava/dispatcher/tmp/12172439/lava-overlay-nxf13uu9/lava-12172439/bin/lava-install-packages (debian)
187 23:30:57.860997 Updating /var/lib/lava/dispatcher/tmp/12172439/lava-overlay-nxf13uu9/lava-12172439/bin/lava-installed-packages (debian)
188 23:30:57.861135 Updating /var/lib/lava/dispatcher/tmp/12172439/lava-overlay-nxf13uu9/lava-12172439/bin/lava-os-build (debian)
189 23:30:57.861256 Creating /var/lib/lava/dispatcher/tmp/12172439/lava-overlay-nxf13uu9/lava-12172439/environment
190 23:30:57.861352 LAVA metadata
191 23:30:57.861422 - LAVA_JOB_ID=12172439
192 23:30:57.861484 - LAVA_DISPATCHER_IP=192.168.201.1
193 23:30:57.861615 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:47) [common]
194 23:30:57.861710 skipped lava-vland-overlay
195 23:30:57.861785 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 23:30:57.861864 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:47) [common]
197 23:30:57.861924 skipped lava-multinode-overlay
198 23:30:57.861997 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 23:30:57.862075 start: 1.6.2.3 test-definition (timeout 00:09:47) [common]
200 23:30:57.862147 Loading test definitions
201 23:30:57.862236 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:47) [common]
202 23:30:57.862319 Using /lava-12172439 at stage 0
203 23:30:57.862606 uuid=12172439_1.6.2.3.1 testdef=None
204 23:30:57.862693 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 23:30:57.862777 start: 1.6.2.3.2 test-overlay (timeout 00:09:47) [common]
206 23:30:57.863227 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 23:30:57.863448 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:47) [common]
209 23:30:57.864004 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 23:30:57.864233 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:47) [common]
212 23:30:57.864772 runner path: /var/lib/lava/dispatcher/tmp/12172439/lava-overlay-nxf13uu9/lava-12172439/0/tests/0_timesync-off test_uuid 12172439_1.6.2.3.1
213 23:30:57.864927 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 23:30:57.865154 start: 1.6.2.3.5 git-repo-action (timeout 00:09:47) [common]
216 23:30:57.865226 Using /lava-12172439 at stage 0
217 23:30:57.865324 Fetching tests from https://github.com/kernelci/test-definitions.git
218 23:30:57.865402 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/12172439/lava-overlay-nxf13uu9/lava-12172439/0/tests/1_kselftest-alsa'
219 23:31:01.192446 Running '/usr/bin/git checkout kernelci.org
220 23:31:01.316041 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/12172439/lava-overlay-nxf13uu9/lava-12172439/0/tests/1_kselftest-alsa/automated/linux/kselftest/kselftest.yaml
221 23:31:01.316810 uuid=12172439_1.6.2.3.5 testdef=None
222 23:31:01.316983 end: 1.6.2.3.5 git-repo-action (duration 00:00:03) [common]
224 23:31:01.317260 start: 1.6.2.3.6 test-overlay (timeout 00:09:44) [common]
225 23:31:01.318128 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 23:31:01.318375 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:44) [common]
228 23:31:01.319504 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 23:31:01.319760 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:44) [common]
231 23:31:01.320758 runner path: /var/lib/lava/dispatcher/tmp/12172439/lava-overlay-nxf13uu9/lava-12172439/0/tests/1_kselftest-alsa test_uuid 12172439_1.6.2.3.5
232 23:31:01.320861 BOARD='mt8192-asurada-spherion-r0'
233 23:31:01.320927 BRANCH='cip-gitlab'
234 23:31:01.320988 SKIPFILE='/dev/null'
235 23:31:01.321056 SKIP_INSTALL='True'
236 23:31:01.321115 TESTPROG_URL='http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.64-cip10-rt5/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 23:31:01.321175 TST_CASENAME=''
238 23:31:01.321232 TST_CMDFILES='alsa'
239 23:31:01.321386 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 23:31:01.321626 Creating lava-test-runner.conf files
242 23:31:01.321693 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12172439/lava-overlay-nxf13uu9/lava-12172439/0 for stage 0
243 23:31:01.321798 - 0_timesync-off
244 23:31:01.321870 - 1_kselftest-alsa
245 23:31:01.321972 end: 1.6.2.3 test-definition (duration 00:00:03) [common]
246 23:31:01.322069 start: 1.6.2.4 compress-overlay (timeout 00:09:44) [common]
247 23:31:08.829097 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 23:31:08.829271 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:36) [common]
249 23:31:08.829370 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 23:31:08.829483 end: 1.6.2 lava-overlay (duration 00:00:11) [common]
251 23:31:08.829583 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:36) [common]
252 23:31:09.000396 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 23:31:09.000801 start: 1.6.4 extract-modules (timeout 00:09:36) [common]
254 23:31:09.000924 extracting modules file /var/lib/lava/dispatcher/tmp/12172439/tftp-deploy-5nfpohkk/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12172439/extract-nfsrootfs-awh02hkz
255 23:31:09.225176 extracting modules file /var/lib/lava/dispatcher/tmp/12172439/tftp-deploy-5nfpohkk/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12172439/extract-overlay-ramdisk-j1c3xpyr/ramdisk
256 23:31:09.453483 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 23:31:09.453736 start: 1.6.5 apply-overlay-tftp (timeout 00:09:36) [common]
258 23:31:09.453842 [common] Applying overlay to NFS
259 23:31:09.453915 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12172439/compress-overlay-xcp_20wu/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12172439/extract-nfsrootfs-awh02hkz
260 23:31:10.379555 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 23:31:10.379726 start: 1.6.6 configure-preseed-file (timeout 00:09:35) [common]
262 23:31:10.379819 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 23:31:10.379907 start: 1.6.7 compress-ramdisk (timeout 00:09:35) [common]
264 23:31:10.379988 Building ramdisk /var/lib/lava/dispatcher/tmp/12172439/extract-overlay-ramdisk-j1c3xpyr/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12172439/extract-overlay-ramdisk-j1c3xpyr/ramdisk
265 23:31:10.749449 >> 130538 blocks
266 23:31:12.756432 rename /var/lib/lava/dispatcher/tmp/12172439/extract-overlay-ramdisk-j1c3xpyr/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12172439/tftp-deploy-5nfpohkk/ramdisk/ramdisk.cpio.gz
267 23:31:12.756880 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 23:31:12.757003 start: 1.6.8 prepare-kernel (timeout 00:09:32) [common]
269 23:31:12.757105 start: 1.6.8.1 prepare-fit (timeout 00:09:32) [common]
270 23:31:12.757214 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12172439/tftp-deploy-5nfpohkk/kernel/Image'
271 23:31:24.625619 Returned 0 in 11 seconds
272 23:31:24.726753 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12172439/tftp-deploy-5nfpohkk/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12172439/tftp-deploy-5nfpohkk/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12172439/tftp-deploy-5nfpohkk/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12172439/tftp-deploy-5nfpohkk/kernel/image.itb
273 23:31:25.117327 output: FIT description: Kernel Image image with one or more FDT blobs
274 23:31:25.117726 output: Created: Sun Dec 3 23:31:25 2023
275 23:31:25.117805 output: Image 0 (kernel-1)
276 23:31:25.117871 output: Description:
277 23:31:25.117935 output: Created: Sun Dec 3 23:31:25 2023
278 23:31:25.117997 output: Type: Kernel Image
279 23:31:25.118057 output: Compression: lzma compressed
280 23:31:25.118117 output: Data Size: 11049348 Bytes = 10790.38 KiB = 10.54 MiB
281 23:31:25.118178 output: Architecture: AArch64
282 23:31:25.118258 output: OS: Linux
283 23:31:25.118327 output: Load Address: 0x00000000
284 23:31:25.118387 output: Entry Point: 0x00000000
285 23:31:25.118447 output: Hash algo: crc32
286 23:31:25.118506 output: Hash value: c85ea8f0
287 23:31:25.118568 output: Image 1 (fdt-1)
288 23:31:25.118622 output: Description: mt8192-asurada-spherion-r0
289 23:31:25.118677 output: Created: Sun Dec 3 23:31:25 2023
290 23:31:25.118732 output: Type: Flat Device Tree
291 23:31:25.118787 output: Compression: uncompressed
292 23:31:25.118841 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
293 23:31:25.118896 output: Architecture: AArch64
294 23:31:25.118950 output: Hash algo: crc32
295 23:31:25.119004 output: Hash value: cc4352de
296 23:31:25.119058 output: Image 2 (ramdisk-1)
297 23:31:25.119113 output: Description: unavailable
298 23:31:25.119167 output: Created: Sun Dec 3 23:31:25 2023
299 23:31:25.119221 output: Type: RAMDisk Image
300 23:31:25.119276 output: Compression: Unknown Compression
301 23:31:25.119330 output: Data Size: 18760935 Bytes = 18321.23 KiB = 17.89 MiB
302 23:31:25.119385 output: Architecture: AArch64
303 23:31:25.119439 output: OS: Linux
304 23:31:25.119493 output: Load Address: unavailable
305 23:31:25.119547 output: Entry Point: unavailable
306 23:31:25.119601 output: Hash algo: crc32
307 23:31:25.119654 output: Hash value: 06e3c1ad
308 23:31:25.119708 output: Default Configuration: 'conf-1'
309 23:31:25.119762 output: Configuration 0 (conf-1)
310 23:31:25.119815 output: Description: mt8192-asurada-spherion-r0
311 23:31:25.119869 output: Kernel: kernel-1
312 23:31:25.119923 output: Init Ramdisk: ramdisk-1
313 23:31:25.119977 output: FDT: fdt-1
314 23:31:25.120031 output: Loadables: kernel-1
315 23:31:25.120084 output:
316 23:31:25.120292 end: 1.6.8.1 prepare-fit (duration 00:00:12) [common]
317 23:31:25.120394 end: 1.6.8 prepare-kernel (duration 00:00:12) [common]
318 23:31:25.120500 end: 1.6 prepare-tftp-overlay (duration 00:00:31) [common]
319 23:31:25.120601 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:20) [common]
320 23:31:25.120679 No LXC device requested
321 23:31:25.120759 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 23:31:25.120842 start: 1.8 deploy-device-env (timeout 00:09:20) [common]
323 23:31:25.120921 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 23:31:25.120990 Checking files for TFTP limit of 4294967296 bytes.
325 23:31:25.121493 end: 1 tftp-deploy (duration 00:00:40) [common]
326 23:31:25.121632 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 23:31:25.121743 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 23:31:25.121875 substitutions:
329 23:31:25.121945 - {DTB}: 12172439/tftp-deploy-5nfpohkk/dtb/mt8192-asurada-spherion-r0.dtb
330 23:31:25.122011 - {INITRD}: 12172439/tftp-deploy-5nfpohkk/ramdisk/ramdisk.cpio.gz
331 23:31:25.122072 - {KERNEL}: 12172439/tftp-deploy-5nfpohkk/kernel/Image
332 23:31:25.122132 - {LAVA_MAC}: None
333 23:31:25.122189 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/12172439/extract-nfsrootfs-awh02hkz
334 23:31:25.122246 - {NFS_SERVER_IP}: 192.168.201.1
335 23:31:25.122301 - {PRESEED_CONFIG}: None
336 23:31:25.122357 - {PRESEED_LOCAL}: None
337 23:31:25.122412 - {RAMDISK}: 12172439/tftp-deploy-5nfpohkk/ramdisk/ramdisk.cpio.gz
338 23:31:25.122468 - {ROOT_PART}: None
339 23:31:25.122524 - {ROOT}: None
340 23:31:25.122580 - {SERVER_IP}: 192.168.201.1
341 23:31:25.122634 - {TEE}: None
342 23:31:25.122690 Parsed boot commands:
343 23:31:25.122745 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 23:31:25.122935 Parsed boot commands: tftpboot 192.168.201.1 12172439/tftp-deploy-5nfpohkk/kernel/image.itb 12172439/tftp-deploy-5nfpohkk/kernel/cmdline
345 23:31:25.123029 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 23:31:25.123115 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 23:31:25.123219 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 23:31:25.123314 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 23:31:25.123388 Not connected, no need to disconnect.
350 23:31:25.123464 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 23:31:25.123550 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 23:31:25.123622 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-0'
353 23:31:25.127680 Setting prompt string to ['lava-test: # ']
354 23:31:25.128060 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 23:31:25.128170 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 23:31:25.128276 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 23:31:25.128365 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 23:31:25.128600 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=reboot'
359 23:31:30.267997 >> Command sent successfully.
360 23:31:30.270566 Returned 0 in 5 seconds
361 23:31:30.370984 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 23:31:30.371342 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 23:31:30.371446 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 23:31:30.371543 Setting prompt string to 'Starting depthcharge on Spherion...'
366 23:31:30.371615 Changing prompt to 'Starting depthcharge on Spherion...'
367 23:31:30.371701 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 23:31:30.371982 [Enter `^Ec?' for help]
369 23:31:30.542524
370 23:31:30.542754
371 23:31:30.542871 F0: 102B 0000
372 23:31:30.542979
373 23:31:30.545742 F3: 1001 0000 [0200]
374 23:31:30.545877
375 23:31:30.545989 F3: 1001 0000
376 23:31:30.546079
377 23:31:30.546163 F7: 102D 0000
378 23:31:30.546247
379 23:31:30.549078 F1: 0000 0000
380 23:31:30.549196
381 23:31:30.549290 V0: 0000 0000 [0001]
382 23:31:30.549382
383 23:31:30.551928 00: 0007 8000
384 23:31:30.552039
385 23:31:30.552122 01: 0000 0000
386 23:31:30.552202
387 23:31:30.555232 BP: 0C00 0209 [0000]
388 23:31:30.555340
389 23:31:30.555424 G0: 1182 0000
390 23:31:30.555503
391 23:31:30.559449 EC: 0000 0021 [4000]
392 23:31:30.559552
393 23:31:30.559628 S7: 0000 0000 [0000]
394 23:31:30.559699
395 23:31:30.562879 CC: 0000 0000 [0001]
396 23:31:30.562967
397 23:31:30.563037 T0: 0000 0040 [010F]
398 23:31:30.563103
399 23:31:30.565805 Jump to BL
400 23:31:30.565904
401 23:31:30.590100
402 23:31:30.590209
403 23:31:30.590277
404 23:31:30.597513 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 23:31:30.601017 ARM64: Exception handlers installed.
406 23:31:30.604898 ARM64: Testing exception
407 23:31:30.604984 ARM64: Done test exception
408 23:31:30.614995 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 23:31:30.625757 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 23:31:30.632272 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 23:31:30.642055 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 23:31:30.648636 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 23:31:30.655418 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 23:31:30.667169 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 23:31:30.674156 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 23:31:30.692924 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 23:31:30.696070 WDT: Last reset was cold boot
418 23:31:30.699098 SPI1(PAD0) initialized at 2873684 Hz
419 23:31:30.703009 SPI5(PAD0) initialized at 992727 Hz
420 23:31:30.706569 VBOOT: Loading verstage.
421 23:31:30.712667 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 23:31:30.716438 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 23:31:30.719809 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 23:31:30.723007 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 23:31:30.730613 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 23:31:30.737239 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 23:31:30.747584 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
428 23:31:30.748156
429 23:31:30.748540
430 23:31:30.758278 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 23:31:30.762088 ARM64: Exception handlers installed.
432 23:31:30.762675 ARM64: Testing exception
433 23:31:30.765524 ARM64: Done test exception
434 23:31:30.768382 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 23:31:30.775621 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 23:31:30.788867 Probing TPM: . done!
437 23:31:30.789451 TPM ready after 0 ms
438 23:31:30.796882 Connected to device vid:did:rid of 1ae0:0028:00
439 23:31:30.802807 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
440 23:31:30.863134 Initialized TPM device CR50 revision 0
441 23:31:30.874088 tlcl_send_startup: Startup return code is 0
442 23:31:30.874680 TPM: setup succeeded
443 23:31:30.885984 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 23:31:30.894312 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 23:31:30.909448 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 23:31:30.915973 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 23:31:30.919975 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 23:31:30.923411 in-header: 03 07 00 00 08 00 00 00
449 23:31:30.926725 in-data: aa e4 47 04 13 02 00 00
450 23:31:30.930668 Chrome EC: UHEPI supported
451 23:31:30.934361 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 23:31:30.938131 in-header: 03 95 00 00 08 00 00 00
453 23:31:30.941890 in-data: 18 20 20 08 00 00 00 00
454 23:31:30.942389 Phase 1
455 23:31:30.949334 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 23:31:30.952501 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 23:31:30.960185 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 23:31:30.963958 Recovery requested (1009000e)
459 23:31:30.973606 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 23:31:30.977296 tlcl_extend: response is 0
461 23:31:30.985819 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 23:31:30.991444 tlcl_extend: response is 0
463 23:31:30.998268 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 23:31:31.018058 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
465 23:31:31.025167 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 23:31:31.025760
467 23:31:31.026115
468 23:31:31.034790 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 23:31:31.038102 ARM64: Exception handlers installed.
470 23:31:31.041887 ARM64: Testing exception
471 23:31:31.042514 ARM64: Done test exception
472 23:31:31.064129 pmic_efuse_setting: Set efuses in 11 msecs
473 23:31:31.067484 pmwrap_interface_init: Select PMIF_VLD_RDY
474 23:31:31.074228 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 23:31:31.077633 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 23:31:31.084480 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 23:31:31.088000 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 23:31:31.091787 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 23:31:31.098682 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 23:31:31.102480 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 23:31:31.106080 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 23:31:31.109709 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 23:31:31.116771 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 23:31:31.120801 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 23:31:31.124153 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 23:31:31.128044 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 23:31:31.136725 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 23:31:31.140149 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 23:31:31.147629 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 23:31:31.155451 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 23:31:31.159318 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 23:31:31.166357 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 23:31:31.170254 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 23:31:31.173953 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 23:31:31.181745 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 23:31:31.185857 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 23:31:31.192711 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 23:31:31.196944 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 23:31:31.203891 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 23:31:31.207643 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 23:31:31.211967 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 23:31:31.218938 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 23:31:31.222123 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 23:31:31.229527 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 23:31:31.233332 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 23:31:31.236588 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 23:31:31.244142 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 23:31:31.247837 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 23:31:31.251269 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 23:31:31.258919 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 23:31:31.262579 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 23:31:31.265765 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 23:31:31.273279 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 23:31:31.277072 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 23:31:31.280706 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 23:31:31.284439 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 23:31:31.287963 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 23:31:31.295192 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 23:31:31.298679 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 23:31:31.302971 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 23:31:31.306062 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 23:31:31.309786 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 23:31:31.313949 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 23:31:31.316998 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 23:31:31.328105 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 23:31:31.335881 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 23:31:31.339423 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 23:31:31.346083 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 23:31:31.357488 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 23:31:31.361016 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 23:31:31.364984 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 23:31:31.368734 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 23:31:31.377128 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde71, sec=0x1b
534 23:31:31.384076 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 23:31:31.388427 [RTC]rtc_osc_init,62: osc32con val = 0xde71
536 23:31:31.391035 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 23:31:31.401541 [RTC]rtc_get_frequency_meter,154: input=15, output=757
538 23:31:31.411135 [RTC]rtc_get_frequency_meter,154: input=23, output=941
539 23:31:31.420456 [RTC]rtc_get_frequency_meter,154: input=19, output=851
540 23:31:31.430279 [RTC]rtc_get_frequency_meter,154: input=17, output=805
541 23:31:31.439478 [RTC]rtc_get_frequency_meter,154: input=16, output=782
542 23:31:31.449729 [RTC]rtc_get_frequency_meter,154: input=16, output=781
543 23:31:31.459320 [RTC]rtc_get_frequency_meter,154: input=17, output=804
544 23:31:31.462946 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
545 23:31:31.466862 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
546 23:31:31.471071 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
547 23:31:31.474447 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
548 23:31:31.482602 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
549 23:31:31.486705 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
550 23:31:31.487287 ADC[4]: Raw value=906942 ID=7
551 23:31:31.490114 ADC[3]: Raw value=213441 ID=1
552 23:31:31.490690 RAM Code: 0x71
553 23:31:31.497544 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
554 23:31:31.501345 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
555 23:31:31.509023 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
556 23:31:31.516638 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
557 23:31:31.519991 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
558 23:31:31.523426 in-header: 03 07 00 00 08 00 00 00
559 23:31:31.527234 in-data: aa e4 47 04 13 02 00 00
560 23:31:31.527689 Chrome EC: UHEPI supported
561 23:31:31.534974 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
562 23:31:31.538270 in-header: 03 95 00 00 08 00 00 00
563 23:31:31.542447 in-data: 18 20 20 08 00 00 00 00
564 23:31:31.545837 MRC: failed to locate region type 0.
565 23:31:31.553953 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
566 23:31:31.554477 DRAM-K: Running full calibration
567 23:31:31.560657 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
568 23:31:31.564640 header.status = 0x0
569 23:31:31.568312 header.version = 0x6 (expected: 0x6)
570 23:31:31.568740 header.size = 0xd00 (expected: 0xd00)
571 23:31:31.572122 header.flags = 0x0
572 23:31:31.578714 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
573 23:31:31.596630 read SPI 0x72590 0x1c583: 12500 us, 9287 KB/s, 74.296 Mbps
574 23:31:31.603557 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
575 23:31:31.604142 dram_init: ddr_geometry: 2
576 23:31:31.607560 [EMI] MDL number = 2
577 23:31:31.610909 [EMI] Get MDL freq = 0
578 23:31:31.611334 dram_init: ddr_type: 0
579 23:31:31.614464 is_discrete_lpddr4: 1
580 23:31:31.614889 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
581 23:31:31.618396
582 23:31:31.618819
583 23:31:31.619153 [Bian_co] ETT version 0.0.0.1
584 23:31:31.625720 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
585 23:31:31.626178
586 23:31:31.629629 dramc_set_vcore_voltage set vcore to 650000
587 23:31:31.630192 Read voltage for 800, 4
588 23:31:31.630652 Vio18 = 0
589 23:31:31.633459 Vcore = 650000
590 23:31:31.633925 Vdram = 0
591 23:31:31.634267 Vddq = 0
592 23:31:31.637038 Vmddr = 0
593 23:31:31.637463 dram_init: config_dvfs: 1
594 23:31:31.640984 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
595 23:31:31.648495 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
596 23:31:31.652586 [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9
597 23:31:31.656025 freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9
598 23:31:31.659922 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
599 23:31:31.663636 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
600 23:31:31.664064 MEM_TYPE=3, freq_sel=18
601 23:31:31.667358 sv_algorithm_assistance_LP4_1600
602 23:31:31.670941 ============ PULL DRAM RESETB DOWN ============
603 23:31:31.677807 ========== PULL DRAM RESETB DOWN end =========
604 23:31:31.681167 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
605 23:31:31.684532 ===================================
606 23:31:31.688401 LPDDR4 DRAM CONFIGURATION
607 23:31:31.691901 ===================================
608 23:31:31.692424 EX_ROW_EN[0] = 0x0
609 23:31:31.695177 EX_ROW_EN[1] = 0x0
610 23:31:31.695601 LP4Y_EN = 0x0
611 23:31:31.698770 WORK_FSP = 0x0
612 23:31:31.699266 WL = 0x2
613 23:31:31.702106 RL = 0x2
614 23:31:31.702529 BL = 0x2
615 23:31:31.706159 RPST = 0x0
616 23:31:31.706610 RD_PRE = 0x0
617 23:31:31.709894 WR_PRE = 0x1
618 23:31:31.710326 WR_PST = 0x0
619 23:31:31.712889 DBI_WR = 0x0
620 23:31:31.713321 DBI_RD = 0x0
621 23:31:31.716401 OTF = 0x1
622 23:31:31.719627 ===================================
623 23:31:31.722855 ===================================
624 23:31:31.723278 ANA top config
625 23:31:31.726550 ===================================
626 23:31:31.729700 DLL_ASYNC_EN = 0
627 23:31:31.730131 ALL_SLAVE_EN = 1
628 23:31:31.733294 NEW_RANK_MODE = 1
629 23:31:31.736603 DLL_IDLE_MODE = 1
630 23:31:31.739923 LP45_APHY_COMB_EN = 1
631 23:31:31.743481 TX_ODT_DIS = 1
632 23:31:31.744027 NEW_8X_MODE = 1
633 23:31:31.747171 ===================================
634 23:31:31.750631 ===================================
635 23:31:31.753901 data_rate = 1600
636 23:31:31.757676 CKR = 1
637 23:31:31.760927 DQ_P2S_RATIO = 8
638 23:31:31.764170 ===================================
639 23:31:31.764702 CA_P2S_RATIO = 8
640 23:31:31.767243 DQ_CA_OPEN = 0
641 23:31:31.770306 DQ_SEMI_OPEN = 0
642 23:31:31.774111 CA_SEMI_OPEN = 0
643 23:31:31.777142 CA_FULL_RATE = 0
644 23:31:31.780443 DQ_CKDIV4_EN = 1
645 23:31:31.780873 CA_CKDIV4_EN = 1
646 23:31:31.783869 CA_PREDIV_EN = 0
647 23:31:31.787455 PH8_DLY = 0
648 23:31:31.790993 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
649 23:31:31.794003 DQ_AAMCK_DIV = 4
650 23:31:31.797087 CA_AAMCK_DIV = 4
651 23:31:31.797668 CA_ADMCK_DIV = 4
652 23:31:31.800646 DQ_TRACK_CA_EN = 0
653 23:31:31.804198 CA_PICK = 800
654 23:31:31.806944 CA_MCKIO = 800
655 23:31:31.810717 MCKIO_SEMI = 0
656 23:31:31.814322 PLL_FREQ = 3068
657 23:31:31.814770 DQ_UI_PI_RATIO = 32
658 23:31:31.817941 CA_UI_PI_RATIO = 0
659 23:31:31.821680 ===================================
660 23:31:31.825119 ===================================
661 23:31:31.829087 memory_type:LPDDR4
662 23:31:31.829511 GP_NUM : 10
663 23:31:31.832579 SRAM_EN : 1
664 23:31:31.833004 MD32_EN : 0
665 23:31:31.835875 ===================================
666 23:31:31.839750 [ANA_INIT] >>>>>>>>>>>>>>
667 23:31:31.843074 <<<<<< [CONFIGURE PHASE]: ANA_TX
668 23:31:31.846592 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
669 23:31:31.850161 ===================================
670 23:31:31.850588 data_rate = 1600,PCW = 0X7600
671 23:31:31.853906 ===================================
672 23:31:31.857018 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
673 23:31:31.863641 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 23:31:31.870363 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
675 23:31:31.873992 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
676 23:31:31.876793 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
677 23:31:31.879815 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
678 23:31:31.883467 [ANA_INIT] flow start
679 23:31:31.884059 [ANA_INIT] PLL >>>>>>>>
680 23:31:31.887043 [ANA_INIT] PLL <<<<<<<<
681 23:31:31.890025 [ANA_INIT] MIDPI >>>>>>>>
682 23:31:31.893611 [ANA_INIT] MIDPI <<<<<<<<
683 23:31:31.894158 [ANA_INIT] DLL >>>>>>>>
684 23:31:31.896603 [ANA_INIT] flow end
685 23:31:31.899963 ============ LP4 DIFF to SE enter ============
686 23:31:31.904015 ============ LP4 DIFF to SE exit ============
687 23:31:31.906890 [ANA_INIT] <<<<<<<<<<<<<
688 23:31:31.910203 [Flow] Enable top DCM control >>>>>
689 23:31:31.913953 [Flow] Enable top DCM control <<<<<
690 23:31:31.917370 Enable DLL master slave shuffle
691 23:31:31.920657 ==============================================================
692 23:31:31.923890 Gating Mode config
693 23:31:31.930264 ==============================================================
694 23:31:31.930797 Config description:
695 23:31:31.940584 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
696 23:31:31.947241 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
697 23:31:31.950551 SELPH_MODE 0: By rank 1: By Phase
698 23:31:31.957472 ==============================================================
699 23:31:31.960829 GAT_TRACK_EN = 1
700 23:31:31.963984 RX_GATING_MODE = 2
701 23:31:31.967379 RX_GATING_TRACK_MODE = 2
702 23:31:31.970897 SELPH_MODE = 1
703 23:31:31.973917 PICG_EARLY_EN = 1
704 23:31:31.977121 VALID_LAT_VALUE = 1
705 23:31:31.980330 ==============================================================
706 23:31:31.983604 Enter into Gating configuration >>>>
707 23:31:31.987582 Exit from Gating configuration <<<<
708 23:31:31.990699 Enter into DVFS_PRE_config >>>>>
709 23:31:32.000753 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
710 23:31:32.003735 Exit from DVFS_PRE_config <<<<<
711 23:31:32.006914 Enter into PICG configuration >>>>
712 23:31:32.010288 Exit from PICG configuration <<<<
713 23:31:32.014251 [RX_INPUT] configuration >>>>>
714 23:31:32.017125 [RX_INPUT] configuration <<<<<
715 23:31:32.024327 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
716 23:31:32.027881 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
717 23:31:32.034574 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
718 23:31:32.040673 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
719 23:31:32.047726 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
720 23:31:32.054167 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
721 23:31:32.057344 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
722 23:31:32.060548 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
723 23:31:32.064070 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
724 23:31:32.067196 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
725 23:31:32.073911 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
726 23:31:32.077687 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
727 23:31:32.080597 ===================================
728 23:31:32.084125 LPDDR4 DRAM CONFIGURATION
729 23:31:32.087538 ===================================
730 23:31:32.088071 EX_ROW_EN[0] = 0x0
731 23:31:32.091125 EX_ROW_EN[1] = 0x0
732 23:31:32.091698 LP4Y_EN = 0x0
733 23:31:32.094226 WORK_FSP = 0x0
734 23:31:32.094697 WL = 0x2
735 23:31:32.097412 RL = 0x2
736 23:31:32.098046 BL = 0x2
737 23:31:32.100529 RPST = 0x0
738 23:31:32.101022 RD_PRE = 0x0
739 23:31:32.104243 WR_PRE = 0x1
740 23:31:32.104721 WR_PST = 0x0
741 23:31:32.107748 DBI_WR = 0x0
742 23:31:32.110487 DBI_RD = 0x0
743 23:31:32.110925 OTF = 0x1
744 23:31:32.114093 ===================================
745 23:31:32.117499 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
746 23:31:32.120841 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
747 23:31:32.127341 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
748 23:31:32.130801 ===================================
749 23:31:32.131238 LPDDR4 DRAM CONFIGURATION
750 23:31:32.134183 ===================================
751 23:31:32.137931 EX_ROW_EN[0] = 0x10
752 23:31:32.141049 EX_ROW_EN[1] = 0x0
753 23:31:32.141483 LP4Y_EN = 0x0
754 23:31:32.144875 WORK_FSP = 0x0
755 23:31:32.145310 WL = 0x2
756 23:31:32.147550 RL = 0x2
757 23:31:32.148105 BL = 0x2
758 23:31:32.151104 RPST = 0x0
759 23:31:32.151536 RD_PRE = 0x0
760 23:31:32.154364 WR_PRE = 0x1
761 23:31:32.154903 WR_PST = 0x0
762 23:31:32.157684 DBI_WR = 0x0
763 23:31:32.158229 DBI_RD = 0x0
764 23:31:32.161117 OTF = 0x1
765 23:31:32.164569 ===================================
766 23:31:32.170652 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
767 23:31:32.174237 nWR fixed to 40
768 23:31:32.174799 [ModeRegInit_LP4] CH0 RK0
769 23:31:32.177363 [ModeRegInit_LP4] CH0 RK1
770 23:31:32.180909 [ModeRegInit_LP4] CH1 RK0
771 23:31:32.184111 [ModeRegInit_LP4] CH1 RK1
772 23:31:32.184757 match AC timing 13
773 23:31:32.187853 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
774 23:31:32.194295 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
775 23:31:32.198097 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
776 23:31:32.201463 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
777 23:31:32.207830 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
778 23:31:32.208434 [EMI DOE] emi_dcm 0
779 23:31:32.214524 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
780 23:31:32.215110 ==
781 23:31:32.217811 Dram Type= 6, Freq= 0, CH_0, rank 0
782 23:31:32.221134 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
783 23:31:32.221672 ==
784 23:31:32.227512 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
785 23:31:32.230674 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
786 23:31:32.241436 [CA 0] Center 36 (6~67) winsize 62
787 23:31:32.244875 [CA 1] Center 36 (6~67) winsize 62
788 23:31:32.247751 [CA 2] Center 34 (4~65) winsize 62
789 23:31:32.251130 [CA 3] Center 33 (3~64) winsize 62
790 23:31:32.254605 [CA 4] Center 33 (3~63) winsize 61
791 23:31:32.258003 [CA 5] Center 32 (3~62) winsize 60
792 23:31:32.258590
793 23:31:32.261367 [CmdBusTrainingLP45] Vref(ca) range 1: 32
794 23:31:32.262005
795 23:31:32.264747 [CATrainingPosCal] consider 1 rank data
796 23:31:32.267382 u2DelayCellTimex100 = 270/100 ps
797 23:31:32.271533 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
798 23:31:32.274523 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
799 23:31:32.280827 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
800 23:31:32.284545 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
801 23:31:32.287830 CA4 delay=33 (3~63),Diff = 1 PI (7 cell)
802 23:31:32.291505 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
803 23:31:32.292087
804 23:31:32.294659 CA PerBit enable=1, Macro0, CA PI delay=32
805 23:31:32.295135
806 23:31:32.297520 [CBTSetCACLKResult] CA Dly = 32
807 23:31:32.298073 CS Dly: 5 (0~36)
808 23:31:32.298453 ==
809 23:31:32.301030 Dram Type= 6, Freq= 0, CH_0, rank 1
810 23:31:32.307999 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
811 23:31:32.308581 ==
812 23:31:32.311084 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
813 23:31:32.317963 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
814 23:31:32.327884 [CA 0] Center 36 (6~67) winsize 62
815 23:31:32.331052 [CA 1] Center 36 (6~67) winsize 62
816 23:31:32.333946 [CA 2] Center 34 (4~65) winsize 62
817 23:31:32.337350 [CA 3] Center 33 (3~64) winsize 62
818 23:31:32.340784 [CA 4] Center 33 (3~63) winsize 61
819 23:31:32.344049 [CA 5] Center 32 (2~63) winsize 62
820 23:31:32.344546
821 23:31:32.347569 [CmdBusTrainingLP45] Vref(ca) range 1: 32
822 23:31:32.348157
823 23:31:32.351117 [CATrainingPosCal] consider 2 rank data
824 23:31:32.354263 u2DelayCellTimex100 = 270/100 ps
825 23:31:32.357623 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
826 23:31:32.360857 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
827 23:31:32.364389 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
828 23:31:32.371272 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
829 23:31:32.374388 CA4 delay=33 (3~63),Diff = 1 PI (7 cell)
830 23:31:32.377254 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
831 23:31:32.377782
832 23:31:32.380853 CA PerBit enable=1, Macro0, CA PI delay=32
833 23:31:32.381329
834 23:31:32.384341 [CBTSetCACLKResult] CA Dly = 32
835 23:31:32.384958 CS Dly: 5 (0~36)
836 23:31:32.385344
837 23:31:32.388160 ----->DramcWriteLeveling(PI) begin...
838 23:31:32.388750 ==
839 23:31:32.391573 Dram Type= 6, Freq= 0, CH_0, rank 0
840 23:31:32.394812 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
841 23:31:32.395296 ==
842 23:31:32.399187 Write leveling (Byte 0): 33 => 33
843 23:31:32.402761 Write leveling (Byte 1): 29 => 29
844 23:31:32.406484 DramcWriteLeveling(PI) end<-----
845 23:31:32.406996
846 23:31:32.407395 ==
847 23:31:32.410025 Dram Type= 6, Freq= 0, CH_0, rank 0
848 23:31:32.412945 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
849 23:31:32.413424 ==
850 23:31:32.416894 [Gating] SW mode calibration
851 23:31:32.423953 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
852 23:31:32.427620 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
853 23:31:32.433914 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
854 23:31:32.437487 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
855 23:31:32.441135 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
856 23:31:32.447547 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
857 23:31:32.450747 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 23:31:32.454550 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 23:31:32.461121 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 23:31:32.464562 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 23:31:32.467366 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 23:31:32.474292 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 23:31:32.477945 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 23:31:32.480705 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 23:31:32.484692 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 23:31:32.491188 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 23:31:32.494499 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 23:31:32.497622 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 23:31:32.504160 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 23:31:32.507626 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
871 23:31:32.510822 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
872 23:31:32.517758 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
873 23:31:32.521050 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 23:31:32.524270 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 23:31:32.531228 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 23:31:32.534396 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 23:31:32.537800 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 23:31:32.544378 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
879 23:31:32.548148 0 9 8 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
880 23:31:32.551677 0 9 12 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
881 23:31:32.554928 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 23:31:32.561260 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 23:31:32.564745 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
884 23:31:32.568141 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
885 23:31:32.574930 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
886 23:31:32.577811 0 10 4 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
887 23:31:32.581105 0 10 8 | B1->B0 | 2f2f 2626 | 0 0 | (0 1) (0 0)
888 23:31:32.588081 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
889 23:31:32.591501 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 23:31:32.594340 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 23:31:32.601803 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
892 23:31:32.605035 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
893 23:31:32.607997 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
894 23:31:32.614854 0 11 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
895 23:31:32.617942 0 11 8 | B1->B0 | 2f2f 4040 | 0 0 | (0 0) (0 0)
896 23:31:32.621345 0 11 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
897 23:31:32.628073 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 23:31:32.631219 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 23:31:32.635242 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
900 23:31:32.638338 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
901 23:31:32.645075 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
902 23:31:32.647986 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
903 23:31:32.651227 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
904 23:31:32.657972 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
905 23:31:32.661373 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 23:31:32.664962 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 23:31:32.672008 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 23:31:32.674551 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 23:31:32.677958 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 23:31:32.684978 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 23:31:32.688072 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 23:31:32.691823 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 23:31:32.698213 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 23:31:32.701325 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 23:31:32.704486 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
916 23:31:32.711459 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
917 23:31:32.715062 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
918 23:31:32.718514 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
919 23:31:32.721913 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
920 23:31:32.725138 Total UI for P1: 0, mck2ui 16
921 23:31:32.728496 best dqsien dly found for B0: ( 0, 14, 4)
922 23:31:32.735083 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
923 23:31:32.738190 Total UI for P1: 0, mck2ui 16
924 23:31:32.741893 best dqsien dly found for B1: ( 0, 14, 8)
925 23:31:32.745864 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
926 23:31:32.749273 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
927 23:31:32.749910
928 23:31:32.752276 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
929 23:31:32.755333 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
930 23:31:32.758640 [Gating] SW calibration Done
931 23:31:32.759217 ==
932 23:31:32.762357 Dram Type= 6, Freq= 0, CH_0, rank 0
933 23:31:32.765566 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 23:31:32.766193 ==
935 23:31:32.766572 RX Vref Scan: 0
936 23:31:32.768740
937 23:31:32.769231 RX Vref 0 -> 0, step: 1
938 23:31:32.769653
939 23:31:32.772105 RX Delay -130 -> 252, step: 16
940 23:31:32.775511 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
941 23:31:32.778923 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
942 23:31:32.785487 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
943 23:31:32.789200 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
944 23:31:32.792524 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
945 23:31:32.795784 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
946 23:31:32.798852 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
947 23:31:32.805521 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
948 23:31:32.809041 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
949 23:31:32.812509 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
950 23:31:32.815835 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
951 23:31:32.818878 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
952 23:31:32.825357 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
953 23:31:32.828963 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
954 23:31:32.831999 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
955 23:31:32.835342 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
956 23:31:32.835817 ==
957 23:31:32.839322 Dram Type= 6, Freq= 0, CH_0, rank 0
958 23:31:32.845633 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
959 23:31:32.846212 ==
960 23:31:32.846591 DQS Delay:
961 23:31:32.846942 DQS0 = 0, DQS1 = 0
962 23:31:32.848989 DQM Delay:
963 23:31:32.849622 DQM0 = 92, DQM1 = 86
964 23:31:32.852219 DQ Delay:
965 23:31:32.855497 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =93
966 23:31:32.858961 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =101
967 23:31:32.859543 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =77
968 23:31:32.865848 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
969 23:31:32.866430
970 23:31:32.866811
971 23:31:32.867164 ==
972 23:31:32.869300 Dram Type= 6, Freq= 0, CH_0, rank 0
973 23:31:32.872999 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
974 23:31:32.873613 ==
975 23:31:32.874019
976 23:31:32.874376
977 23:31:32.875579 TX Vref Scan disable
978 23:31:32.876169 == TX Byte 0 ==
979 23:31:32.882517 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
980 23:31:32.885960 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
981 23:31:32.886541 == TX Byte 1 ==
982 23:31:32.892405 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
983 23:31:32.896107 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
984 23:31:32.896685 ==
985 23:31:32.899248 Dram Type= 6, Freq= 0, CH_0, rank 0
986 23:31:32.902436 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
987 23:31:32.902913 ==
988 23:31:32.916487 TX Vref=22, minBit 8, minWin=27, winSum=449
989 23:31:32.919656 TX Vref=24, minBit 5, minWin=27, winSum=450
990 23:31:32.923467 TX Vref=26, minBit 0, minWin=28, winSum=456
991 23:31:32.926388 TX Vref=28, minBit 8, minWin=28, winSum=457
992 23:31:32.930191 TX Vref=30, minBit 8, minWin=28, winSum=458
993 23:31:32.933613 TX Vref=32, minBit 0, minWin=28, winSum=453
994 23:31:32.939987 [TxChooseVref] Worse bit 8, Min win 28, Win sum 458, Final Vref 30
995 23:31:32.940571
996 23:31:32.943524 Final TX Range 1 Vref 30
997 23:31:32.944296
998 23:31:32.944695 ==
999 23:31:32.946471 Dram Type= 6, Freq= 0, CH_0, rank 0
1000 23:31:32.950039 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1001 23:31:32.950623 ==
1002 23:31:32.951009
1003 23:31:32.951361
1004 23:31:32.953181 TX Vref Scan disable
1005 23:31:32.956671 == TX Byte 0 ==
1006 23:31:32.960013 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1007 23:31:32.963543 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1008 23:31:32.966564 == TX Byte 1 ==
1009 23:31:32.970095 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1010 23:31:32.973192 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1011 23:31:32.973811
1012 23:31:32.976709 [DATLAT]
1013 23:31:32.977180 Freq=800, CH0 RK0
1014 23:31:32.977565
1015 23:31:32.980318 DATLAT Default: 0xa
1016 23:31:32.980884 0, 0xFFFF, sum = 0
1017 23:31:32.983998 1, 0xFFFF, sum = 0
1018 23:31:32.984605 2, 0xFFFF, sum = 0
1019 23:31:32.986384 3, 0xFFFF, sum = 0
1020 23:31:32.986910 4, 0xFFFF, sum = 0
1021 23:31:32.990200 5, 0xFFFF, sum = 0
1022 23:31:32.990788 6, 0xFFFF, sum = 0
1023 23:31:32.993492 7, 0xFFFF, sum = 0
1024 23:31:32.994133 8, 0xFFFF, sum = 0
1025 23:31:32.996804 9, 0x0, sum = 1
1026 23:31:32.997387 10, 0x0, sum = 2
1027 23:31:33.000210 11, 0x0, sum = 3
1028 23:31:33.000789 12, 0x0, sum = 4
1029 23:31:33.003532 best_step = 10
1030 23:31:33.004137
1031 23:31:33.004522 ==
1032 23:31:33.006635 Dram Type= 6, Freq= 0, CH_0, rank 0
1033 23:31:33.010401 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1034 23:31:33.010872 ==
1035 23:31:33.013651 RX Vref Scan: 1
1036 23:31:33.014122
1037 23:31:33.014490 Set Vref Range= 32 -> 127
1038 23:31:33.014833
1039 23:31:33.017032 RX Vref 32 -> 127, step: 1
1040 23:31:33.017765
1041 23:31:33.019993 RX Delay -79 -> 252, step: 8
1042 23:31:33.020475
1043 23:31:33.023361 Set Vref, RX VrefLevel [Byte0]: 32
1044 23:31:33.026683 [Byte1]: 32
1045 23:31:33.027266
1046 23:31:33.029927 Set Vref, RX VrefLevel [Byte0]: 33
1047 23:31:33.033304 [Byte1]: 33
1048 23:31:33.033972
1049 23:31:33.037105 Set Vref, RX VrefLevel [Byte0]: 34
1050 23:31:33.040253 [Byte1]: 34
1051 23:31:33.044147
1052 23:31:33.044572 Set Vref, RX VrefLevel [Byte0]: 35
1053 23:31:33.047626 [Byte1]: 35
1054 23:31:33.052049
1055 23:31:33.052613 Set Vref, RX VrefLevel [Byte0]: 36
1056 23:31:33.055326 [Byte1]: 36
1057 23:31:33.059733
1058 23:31:33.060269 Set Vref, RX VrefLevel [Byte0]: 37
1059 23:31:33.062926 [Byte1]: 37
1060 23:31:33.067344
1061 23:31:33.067766 Set Vref, RX VrefLevel [Byte0]: 38
1062 23:31:33.070168 [Byte1]: 38
1063 23:31:33.074755
1064 23:31:33.075265 Set Vref, RX VrefLevel [Byte0]: 39
1065 23:31:33.078067 [Byte1]: 39
1066 23:31:33.082521
1067 23:31:33.082948 Set Vref, RX VrefLevel [Byte0]: 40
1068 23:31:33.085473 [Byte1]: 40
1069 23:31:33.089650
1070 23:31:33.090072 Set Vref, RX VrefLevel [Byte0]: 41
1071 23:31:33.092949 [Byte1]: 41
1072 23:31:33.097083
1073 23:31:33.097659 Set Vref, RX VrefLevel [Byte0]: 42
1074 23:31:33.100473 [Byte1]: 42
1075 23:31:33.105061
1076 23:31:33.105615 Set Vref, RX VrefLevel [Byte0]: 43
1077 23:31:33.107644 [Byte1]: 43
1078 23:31:33.112646
1079 23:31:33.113162 Set Vref, RX VrefLevel [Byte0]: 44
1080 23:31:33.116047 [Byte1]: 44
1081 23:31:33.119849
1082 23:31:33.120310 Set Vref, RX VrefLevel [Byte0]: 45
1083 23:31:33.122986 [Byte1]: 45
1084 23:31:33.127316
1085 23:31:33.127738 Set Vref, RX VrefLevel [Byte0]: 46
1086 23:31:33.130305 [Byte1]: 46
1087 23:31:33.135006
1088 23:31:33.135523 Set Vref, RX VrefLevel [Byte0]: 47
1089 23:31:33.138427 [Byte1]: 47
1090 23:31:33.143012
1091 23:31:33.143575 Set Vref, RX VrefLevel [Byte0]: 48
1092 23:31:33.146053 [Byte1]: 48
1093 23:31:33.150386
1094 23:31:33.150944 Set Vref, RX VrefLevel [Byte0]: 49
1095 23:31:33.153697 [Byte1]: 49
1096 23:31:33.158044
1097 23:31:33.158602 Set Vref, RX VrefLevel [Byte0]: 50
1098 23:31:33.161381 [Byte1]: 50
1099 23:31:33.165701
1100 23:31:33.166268 Set Vref, RX VrefLevel [Byte0]: 51
1101 23:31:33.168280 [Byte1]: 51
1102 23:31:33.172980
1103 23:31:33.173547 Set Vref, RX VrefLevel [Byte0]: 52
1104 23:31:33.176035 [Byte1]: 52
1105 23:31:33.180527
1106 23:31:33.181133 Set Vref, RX VrefLevel [Byte0]: 53
1107 23:31:33.183302 [Byte1]: 53
1108 23:31:33.187475
1109 23:31:33.187940 Set Vref, RX VrefLevel [Byte0]: 54
1110 23:31:33.191404 [Byte1]: 54
1111 23:31:33.195173
1112 23:31:33.195639 Set Vref, RX VrefLevel [Byte0]: 55
1113 23:31:33.198683 [Byte1]: 55
1114 23:31:33.202840
1115 23:31:33.203402 Set Vref, RX VrefLevel [Byte0]: 56
1116 23:31:33.205993 [Byte1]: 56
1117 23:31:33.210076
1118 23:31:33.210541 Set Vref, RX VrefLevel [Byte0]: 57
1119 23:31:33.213444 [Byte1]: 57
1120 23:31:33.217850
1121 23:31:33.218420 Set Vref, RX VrefLevel [Byte0]: 58
1122 23:31:33.221147 [Byte1]: 58
1123 23:31:33.225752
1124 23:31:33.226318 Set Vref, RX VrefLevel [Byte0]: 59
1125 23:31:33.229003 [Byte1]: 59
1126 23:31:33.232932
1127 23:31:33.233493 Set Vref, RX VrefLevel [Byte0]: 60
1128 23:31:33.236641 [Byte1]: 60
1129 23:31:33.240884
1130 23:31:33.241451 Set Vref, RX VrefLevel [Byte0]: 61
1131 23:31:33.243791 [Byte1]: 61
1132 23:31:33.248274
1133 23:31:33.248737 Set Vref, RX VrefLevel [Byte0]: 62
1134 23:31:33.251169 [Byte1]: 62
1135 23:31:33.255914
1136 23:31:33.256477 Set Vref, RX VrefLevel [Byte0]: 63
1137 23:31:33.258973 [Byte1]: 63
1138 23:31:33.263126
1139 23:31:33.263695 Set Vref, RX VrefLevel [Byte0]: 64
1140 23:31:33.266551 [Byte1]: 64
1141 23:31:33.271132
1142 23:31:33.271595 Set Vref, RX VrefLevel [Byte0]: 65
1143 23:31:33.274510 [Byte1]: 65
1144 23:31:33.278541
1145 23:31:33.279102 Set Vref, RX VrefLevel [Byte0]: 66
1146 23:31:33.281978 [Byte1]: 66
1147 23:31:33.285967
1148 23:31:33.286531 Set Vref, RX VrefLevel [Byte0]: 67
1149 23:31:33.289259 [Byte1]: 67
1150 23:31:33.293786
1151 23:31:33.294349 Set Vref, RX VrefLevel [Byte0]: 68
1152 23:31:33.296914 [Byte1]: 68
1153 23:31:33.301557
1154 23:31:33.302171 Set Vref, RX VrefLevel [Byte0]: 69
1155 23:31:33.304275 [Byte1]: 69
1156 23:31:33.308589
1157 23:31:33.309122 Set Vref, RX VrefLevel [Byte0]: 70
1158 23:31:33.312282 [Byte1]: 70
1159 23:31:33.315843
1160 23:31:33.316310 Set Vref, RX VrefLevel [Byte0]: 71
1161 23:31:33.319385 [Byte1]: 71
1162 23:31:33.323423
1163 23:31:33.323889 Set Vref, RX VrefLevel [Byte0]: 72
1164 23:31:33.326903 [Byte1]: 72
1165 23:31:33.331012
1166 23:31:33.331688 Set Vref, RX VrefLevel [Byte0]: 73
1167 23:31:33.334679 [Byte1]: 73
1168 23:31:33.338376
1169 23:31:33.338840 Set Vref, RX VrefLevel [Byte0]: 74
1170 23:31:33.341906 [Byte1]: 74
1171 23:31:33.346472
1172 23:31:33.347109 Set Vref, RX VrefLevel [Byte0]: 75
1173 23:31:33.349850 [Byte1]: 75
1174 23:31:33.353955
1175 23:31:33.354526 Final RX Vref Byte 0 = 61 to rank0
1176 23:31:33.357011 Final RX Vref Byte 1 = 59 to rank0
1177 23:31:33.361144 Final RX Vref Byte 0 = 61 to rank1
1178 23:31:33.363928 Final RX Vref Byte 1 = 59 to rank1==
1179 23:31:33.367072 Dram Type= 6, Freq= 0, CH_0, rank 0
1180 23:31:33.370308 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1181 23:31:33.373870 ==
1182 23:31:33.374433 DQS Delay:
1183 23:31:33.374806 DQS0 = 0, DQS1 = 0
1184 23:31:33.377184 DQM Delay:
1185 23:31:33.377691 DQM0 = 91, DQM1 = 85
1186 23:31:33.380819 DQ Delay:
1187 23:31:33.384164 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88
1188 23:31:33.384726 DQ4 =96, DQ5 =80, DQ6 =96, DQ7 =96
1189 23:31:33.387293 DQ8 =76, DQ9 =76, DQ10 =84, DQ11 =80
1190 23:31:33.390640 DQ12 =92, DQ13 =92, DQ14 =92, DQ15 =92
1191 23:31:33.394297
1192 23:31:33.394853
1193 23:31:33.400748 [DQSOSCAuto] RK0, (LSB)MR18= 0x493f, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 391 ps
1194 23:31:33.404113 CH0 RK0: MR19=606, MR18=493F
1195 23:31:33.411025 CH0_RK0: MR19=0x606, MR18=0x493F, DQSOSC=391, MR23=63, INC=96, DEC=64
1196 23:31:33.411592
1197 23:31:33.413886 ----->DramcWriteLeveling(PI) begin...
1198 23:31:33.414363 ==
1199 23:31:33.417363 Dram Type= 6, Freq= 0, CH_0, rank 1
1200 23:31:33.421036 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1201 23:31:33.421649 ==
1202 23:31:33.424377 Write leveling (Byte 0): 33 => 33
1203 23:31:33.427543 Write leveling (Byte 1): 30 => 30
1204 23:31:33.430640 DramcWriteLeveling(PI) end<-----
1205 23:31:33.431107
1206 23:31:33.431478 ==
1207 23:31:33.434100 Dram Type= 6, Freq= 0, CH_0, rank 1
1208 23:31:33.437250 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1209 23:31:33.437878 ==
1210 23:31:33.440719 [Gating] SW mode calibration
1211 23:31:33.447473 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1212 23:31:33.454026 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1213 23:31:33.456962 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1214 23:31:33.460503 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1215 23:31:33.478677 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1216 23:31:33.479697 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1217 23:31:33.480242 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1218 23:31:33.489418 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1219 23:31:33.490041 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1220 23:31:33.490422 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 23:31:33.500479 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 23:31:33.501092 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 23:31:33.518010 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 23:31:33.518606 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 23:31:33.519354 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 23:31:33.519735 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 23:31:33.532140 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 23:31:33.533270 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 23:31:33.533742 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 23:31:33.540513 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1231 23:31:33.541085 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1232 23:31:33.546134 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 23:31:33.554235 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 23:31:33.554811 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 23:31:33.584708 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 23:31:33.585279 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 23:31:33.586063 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 23:31:33.586448 0 9 4 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
1239 23:31:33.586798 0 9 8 | B1->B0 | 2d2d 2929 | 0 1 | (0 0) (0 0)
1240 23:31:33.587131 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1241 23:31:33.587454 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1242 23:31:33.615956 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1243 23:31:33.616669 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1244 23:31:33.617206 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1245 23:31:33.618095 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1246 23:31:33.618481 0 10 4 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
1247 23:31:33.618824 0 10 8 | B1->B0 | 2525 2b2b | 0 0 | (1 0) (1 0)
1248 23:31:33.619154 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1249 23:31:33.619476 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1250 23:31:33.659526 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1251 23:31:33.660105 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1252 23:31:33.660480 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1253 23:31:33.660828 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1254 23:31:33.661529 0 11 4 | B1->B0 | 2626 2827 | 0 1 | (0 0) (0 0)
1255 23:31:33.661965 0 11 8 | B1->B0 | 4141 3737 | 1 0 | (0 0) (0 0)
1256 23:31:33.662304 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1257 23:31:33.662634 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1258 23:31:33.662954 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1259 23:31:33.663338 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1260 23:31:33.705154 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1261 23:31:33.705792 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1262 23:31:33.706211 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1263 23:31:33.706571 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1264 23:31:33.706908 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1265 23:31:33.707605 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1266 23:31:33.707983 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1267 23:31:33.708312 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1268 23:31:33.708634 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1269 23:31:33.708950 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1270 23:31:33.746992 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1271 23:31:33.747973 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1272 23:31:33.748381 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1273 23:31:33.748739 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1274 23:31:33.749076 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 23:31:33.749406 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1276 23:31:33.749921 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1277 23:31:33.750428 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1278 23:31:33.750783 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1279 23:31:33.751110 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1280 23:31:33.751514 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1281 23:31:33.755176 Total UI for P1: 0, mck2ui 16
1282 23:31:33.759003 best dqsien dly found for B0: ( 0, 14, 8)
1283 23:31:33.761790 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1284 23:31:33.765031 Total UI for P1: 0, mck2ui 16
1285 23:31:33.769009 best dqsien dly found for B1: ( 0, 14, 10)
1286 23:31:33.771505 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1287 23:31:33.775043 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1288 23:31:33.775512
1289 23:31:33.778724 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1290 23:31:33.785165 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1291 23:31:33.785836 [Gating] SW calibration Done
1292 23:31:33.786227 ==
1293 23:31:33.788821 Dram Type= 6, Freq= 0, CH_0, rank 1
1294 23:31:33.795695 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1295 23:31:33.796270 ==
1296 23:31:33.796647 RX Vref Scan: 0
1297 23:31:33.796997
1298 23:31:33.798642 RX Vref 0 -> 0, step: 1
1299 23:31:33.799106
1300 23:31:33.801871 RX Delay -130 -> 252, step: 16
1301 23:31:33.805079 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1302 23:31:33.808674 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1303 23:31:33.811457 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
1304 23:31:33.815663 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1305 23:31:33.821867 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1306 23:31:33.825729 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1307 23:31:33.828545 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1308 23:31:33.832282 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1309 23:31:33.835354 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1310 23:31:33.841884 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1311 23:31:33.845790 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1312 23:31:33.849001 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1313 23:31:33.852338 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1314 23:31:33.855442 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1315 23:31:33.862186 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1316 23:31:33.865438 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1317 23:31:33.866111 ==
1318 23:31:33.868724 Dram Type= 6, Freq= 0, CH_0, rank 1
1319 23:31:33.872224 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1320 23:31:33.872692 ==
1321 23:31:33.875842 DQS Delay:
1322 23:31:33.876375 DQS0 = 0, DQS1 = 0
1323 23:31:33.876719 DQM Delay:
1324 23:31:33.878856 DQM0 = 93, DQM1 = 83
1325 23:31:33.879276 DQ Delay:
1326 23:31:33.882029 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =93
1327 23:31:33.885028 DQ4 =93, DQ5 =85, DQ6 =93, DQ7 =101
1328 23:31:33.888684 DQ8 =77, DQ9 =77, DQ10 =77, DQ11 =77
1329 23:31:33.892203 DQ12 =85, DQ13 =93, DQ14 =93, DQ15 =85
1330 23:31:33.892629
1331 23:31:33.892963
1332 23:31:33.893275 ==
1333 23:31:33.895311 Dram Type= 6, Freq= 0, CH_0, rank 1
1334 23:31:33.902003 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1335 23:31:33.902434 ==
1336 23:31:33.902773
1337 23:31:33.903087
1338 23:31:33.903385 TX Vref Scan disable
1339 23:31:33.905644 == TX Byte 0 ==
1340 23:31:33.909161 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1341 23:31:33.912022 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1342 23:31:33.915457 == TX Byte 1 ==
1343 23:31:33.919032 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1344 23:31:33.922748 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1345 23:31:33.925809 ==
1346 23:31:33.928922 Dram Type= 6, Freq= 0, CH_0, rank 1
1347 23:31:33.932669 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1348 23:31:33.933206 ==
1349 23:31:33.945299 TX Vref=22, minBit 8, minWin=27, winSum=447
1350 23:31:33.948524 TX Vref=24, minBit 9, minWin=27, winSum=449
1351 23:31:33.951992 TX Vref=26, minBit 4, minWin=28, winSum=455
1352 23:31:33.954758 TX Vref=28, minBit 1, minWin=28, winSum=458
1353 23:31:33.958740 TX Vref=30, minBit 2, minWin=28, winSum=457
1354 23:31:33.962166 TX Vref=32, minBit 2, minWin=28, winSum=453
1355 23:31:33.968774 [TxChooseVref] Worse bit 1, Min win 28, Win sum 458, Final Vref 28
1356 23:31:33.969345
1357 23:31:33.971882 Final TX Range 1 Vref 28
1358 23:31:33.972350
1359 23:31:33.972721 ==
1360 23:31:33.975074 Dram Type= 6, Freq= 0, CH_0, rank 1
1361 23:31:33.978167 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1362 23:31:33.978680 ==
1363 23:31:33.979083
1364 23:31:33.981466
1365 23:31:33.981991 TX Vref Scan disable
1366 23:31:33.984774 == TX Byte 0 ==
1367 23:31:33.988212 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1368 23:31:33.991510 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1369 23:31:33.995044 == TX Byte 1 ==
1370 23:31:33.998448 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1371 23:31:34.001991 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1372 23:31:34.002418
1373 23:31:34.005272 [DATLAT]
1374 23:31:34.005727 Freq=800, CH0 RK1
1375 23:31:34.005997
1376 23:31:34.008439 DATLAT Default: 0xa
1377 23:31:34.008844 0, 0xFFFF, sum = 0
1378 23:31:34.011486 1, 0xFFFF, sum = 0
1379 23:31:34.011791 2, 0xFFFF, sum = 0
1380 23:31:34.015011 3, 0xFFFF, sum = 0
1381 23:31:34.015315 4, 0xFFFF, sum = 0
1382 23:31:34.018210 5, 0xFFFF, sum = 0
1383 23:31:34.018514 6, 0xFFFF, sum = 0
1384 23:31:34.021227 7, 0xFFFF, sum = 0
1385 23:31:34.021530 8, 0x0, sum = 1
1386 23:31:34.024736 9, 0x0, sum = 2
1387 23:31:34.025038 10, 0x0, sum = 3
1388 23:31:34.028327 11, 0x0, sum = 4
1389 23:31:34.028645 best_step = 9
1390 23:31:34.028883
1391 23:31:34.029105 ==
1392 23:31:34.031768 Dram Type= 6, Freq= 0, CH_0, rank 1
1393 23:31:34.038067 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1394 23:31:34.038368 ==
1395 23:31:34.038603 RX Vref Scan: 0
1396 23:31:34.038825
1397 23:31:34.041421 RX Vref 0 -> 0, step: 1
1398 23:31:34.041766
1399 23:31:34.044800 RX Delay -79 -> 252, step: 8
1400 23:31:34.048003 iDelay=209, Bit 0, Center 92 (-15 ~ 200) 216
1401 23:31:34.051345 iDelay=209, Bit 1, Center 96 (-7 ~ 200) 208
1402 23:31:34.054726 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1403 23:31:34.062051 iDelay=209, Bit 3, Center 92 (-15 ~ 200) 216
1404 23:31:34.064746 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1405 23:31:34.068054 iDelay=209, Bit 5, Center 88 (-23 ~ 200) 224
1406 23:31:34.071393 iDelay=209, Bit 6, Center 104 (1 ~ 208) 208
1407 23:31:34.075059 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1408 23:31:34.078260 iDelay=209, Bit 8, Center 76 (-31 ~ 184) 216
1409 23:31:34.085659 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1410 23:31:34.088367 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1411 23:31:34.092200 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1412 23:31:34.094999 iDelay=209, Bit 12, Center 88 (-15 ~ 192) 208
1413 23:31:34.102113 iDelay=209, Bit 13, Center 92 (-15 ~ 200) 216
1414 23:31:34.105560 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1415 23:31:34.108754 iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216
1416 23:31:34.109317 ==
1417 23:31:34.111716 Dram Type= 6, Freq= 0, CH_0, rank 1
1418 23:31:34.115654 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1419 23:31:34.116229 ==
1420 23:31:34.118553 DQS Delay:
1421 23:31:34.119071 DQS0 = 0, DQS1 = 0
1422 23:31:34.119633 DQM Delay:
1423 23:31:34.121720 DQM0 = 94, DQM1 = 84
1424 23:31:34.122184 DQ Delay:
1425 23:31:34.125701 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =92
1426 23:31:34.128724 DQ4 =92, DQ5 =88, DQ6 =104, DQ7 =100
1427 23:31:34.131890 DQ8 =76, DQ9 =72, DQ10 =84, DQ11 =76
1428 23:31:34.135346 DQ12 =88, DQ13 =92, DQ14 =92, DQ15 =92
1429 23:31:34.135847
1430 23:31:34.136456
1431 23:31:34.145678 [DQSOSCAuto] RK1, (LSB)MR18= 0x4011, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 393 ps
1432 23:31:34.148521 CH0 RK1: MR19=606, MR18=4011
1433 23:31:34.152411 CH0_RK1: MR19=0x606, MR18=0x4011, DQSOSC=393, MR23=63, INC=95, DEC=63
1434 23:31:34.155075 [RxdqsGatingPostProcess] freq 800
1435 23:31:34.161953 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1436 23:31:34.165389 Pre-setting of DQS Precalculation
1437 23:31:34.169166 [DualRankRxdatlatCal] RK0: 10, RK1: 9, Final_Datlat 10
1438 23:31:34.169789 ==
1439 23:31:34.172116 Dram Type= 6, Freq= 0, CH_1, rank 0
1440 23:31:34.178555 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1441 23:31:34.179178 ==
1442 23:31:34.182582 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1443 23:31:34.188621 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1444 23:31:34.198079 [CA 0] Center 36 (6~67) winsize 62
1445 23:31:34.201229 [CA 1] Center 36 (6~67) winsize 62
1446 23:31:34.204904 [CA 2] Center 35 (5~66) winsize 62
1447 23:31:34.208575 [CA 3] Center 34 (4~65) winsize 62
1448 23:31:34.211501 [CA 4] Center 34 (4~65) winsize 62
1449 23:31:34.214811 [CA 5] Center 34 (3~65) winsize 63
1450 23:31:34.215378
1451 23:31:34.217698 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1452 23:31:34.218161
1453 23:31:34.221352 [CATrainingPosCal] consider 1 rank data
1454 23:31:34.225222 u2DelayCellTimex100 = 270/100 ps
1455 23:31:34.227985 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1456 23:31:34.231445 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1457 23:31:34.238363 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
1458 23:31:34.241864 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1459 23:31:34.244957 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1460 23:31:34.248335 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1461 23:31:34.248908
1462 23:31:34.251350 CA PerBit enable=1, Macro0, CA PI delay=34
1463 23:31:34.251815
1464 23:31:34.254802 [CBTSetCACLKResult] CA Dly = 34
1465 23:31:34.255390 CS Dly: 6 (0~37)
1466 23:31:34.255773 ==
1467 23:31:34.257958 Dram Type= 6, Freq= 0, CH_1, rank 1
1468 23:31:34.264651 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1469 23:31:34.265220 ==
1470 23:31:34.268537 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1471 23:31:34.274529 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1472 23:31:34.284033 [CA 0] Center 36 (6~67) winsize 62
1473 23:31:34.287215 [CA 1] Center 37 (6~68) winsize 63
1474 23:31:34.290934 [CA 2] Center 35 (5~66) winsize 62
1475 23:31:34.294402 [CA 3] Center 34 (4~65) winsize 62
1476 23:31:34.297664 [CA 4] Center 34 (4~65) winsize 62
1477 23:31:34.301405 [CA 5] Center 34 (4~65) winsize 62
1478 23:31:34.302097
1479 23:31:34.305060 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1480 23:31:34.305704
1481 23:31:34.309020 [CATrainingPosCal] consider 2 rank data
1482 23:31:34.312506 u2DelayCellTimex100 = 270/100 ps
1483 23:31:34.316706 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1484 23:31:34.319768 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1485 23:31:34.323734 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
1486 23:31:34.328134 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1487 23:31:34.330918 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1488 23:31:34.334601 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1489 23:31:34.335073
1490 23:31:34.338066 CA PerBit enable=1, Macro0, CA PI delay=34
1491 23:31:34.338560
1492 23:31:34.341538 [CBTSetCACLKResult] CA Dly = 34
1493 23:31:34.342149 CS Dly: 6 (0~38)
1494 23:31:34.342560
1495 23:31:34.345101 ----->DramcWriteLeveling(PI) begin...
1496 23:31:34.345721 ==
1497 23:31:34.348068 Dram Type= 6, Freq= 0, CH_1, rank 0
1498 23:31:34.351550 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1499 23:31:34.355053 ==
1500 23:31:34.355579 Write leveling (Byte 0): 26 => 26
1501 23:31:34.358304 Write leveling (Byte 1): 26 => 26
1502 23:31:34.361945 DramcWriteLeveling(PI) end<-----
1503 23:31:34.362489
1504 23:31:34.362828 ==
1505 23:31:34.364729 Dram Type= 6, Freq= 0, CH_1, rank 0
1506 23:31:34.371605 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1507 23:31:34.372092 ==
1508 23:31:34.375084 [Gating] SW mode calibration
1509 23:31:34.381763 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1510 23:31:34.384857 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1511 23:31:34.388056 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1512 23:31:34.395396 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1513 23:31:34.398027 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1514 23:31:34.401890 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1515 23:31:34.408910 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1516 23:31:34.412336 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1517 23:31:34.415368 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1518 23:31:34.421614 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 23:31:34.424983 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 23:31:34.429051 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 23:31:34.435411 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 23:31:34.438383 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 23:31:34.441618 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 23:31:34.448998 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 23:31:34.451630 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 23:31:34.454897 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 23:31:34.461919 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1528 23:31:34.465452 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1529 23:31:34.468523 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1530 23:31:34.471710 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 23:31:34.478595 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 23:31:34.482200 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 23:31:34.485539 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 23:31:34.491913 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 23:31:34.495210 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 23:31:34.498541 0 9 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1537 23:31:34.505456 0 9 8 | B1->B0 | 2f2f 3434 | 1 1 | (0 0) (1 1)
1538 23:31:34.508444 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1539 23:31:34.511717 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1540 23:31:34.518488 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1541 23:31:34.522061 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1542 23:31:34.525555 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1543 23:31:34.532067 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1544 23:31:34.535313 0 10 4 | B1->B0 | 3434 2f2f | 0 0 | (0 1) (0 0)
1545 23:31:34.538576 0 10 8 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
1546 23:31:34.541970 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1547 23:31:34.548798 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1548 23:31:34.552072 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1549 23:31:34.555291 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1550 23:31:34.562555 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1551 23:31:34.565966 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1552 23:31:34.568993 0 11 4 | B1->B0 | 2525 3737 | 0 0 | (0 0) (0 0)
1553 23:31:34.575665 0 11 8 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
1554 23:31:34.578823 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1555 23:31:34.582096 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1556 23:31:34.588695 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1557 23:31:34.592562 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1558 23:31:34.595543 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1559 23:31:34.602153 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1560 23:31:34.605488 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1561 23:31:34.608782 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1562 23:31:34.615307 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1563 23:31:34.618740 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1564 23:31:34.622003 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1565 23:31:34.628585 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1566 23:31:34.632251 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1567 23:31:34.635782 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1568 23:31:34.638997 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1569 23:31:34.645549 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1570 23:31:34.648711 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 23:31:34.652187 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 23:31:34.658646 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 23:31:34.662352 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1574 23:31:34.665783 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1575 23:31:34.672746 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1576 23:31:34.675931 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1577 23:31:34.679315 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1578 23:31:34.682544 Total UI for P1: 0, mck2ui 16
1579 23:31:34.685765 best dqsien dly found for B0: ( 0, 14, 4)
1580 23:31:34.688787 Total UI for P1: 0, mck2ui 16
1581 23:31:34.692845 best dqsien dly found for B1: ( 0, 14, 2)
1582 23:31:34.695284 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1583 23:31:34.698847 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1584 23:31:34.699416
1585 23:31:34.702587 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1586 23:31:34.709138 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1587 23:31:34.709742 [Gating] SW calibration Done
1588 23:31:34.710121 ==
1589 23:31:34.712037 Dram Type= 6, Freq= 0, CH_1, rank 0
1590 23:31:34.719109 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1591 23:31:34.719877 ==
1592 23:31:34.720273 RX Vref Scan: 0
1593 23:31:34.720623
1594 23:31:34.722483 RX Vref 0 -> 0, step: 1
1595 23:31:34.722948
1596 23:31:34.726169 RX Delay -130 -> 252, step: 16
1597 23:31:34.729283 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1598 23:31:34.732703 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1599 23:31:34.735601 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1600 23:31:34.742431 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1601 23:31:34.745939 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1602 23:31:34.748905 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1603 23:31:34.752482 iDelay=222, Bit 6, Center 109 (-2 ~ 221) 224
1604 23:31:34.755603 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1605 23:31:34.759092 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1606 23:31:34.765615 iDelay=222, Bit 9, Center 85 (-18 ~ 189) 208
1607 23:31:34.769257 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1608 23:31:34.772393 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1609 23:31:34.776018 iDelay=222, Bit 12, Center 101 (-2 ~ 205) 208
1610 23:31:34.779231 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1611 23:31:34.786206 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1612 23:31:34.789672 iDelay=222, Bit 15, Center 101 (-2 ~ 205) 208
1613 23:31:34.790243 ==
1614 23:31:34.793243 Dram Type= 6, Freq= 0, CH_1, rank 0
1615 23:31:34.795934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1616 23:31:34.796499 ==
1617 23:31:34.799113 DQS Delay:
1618 23:31:34.799670 DQS0 = 0, DQS1 = 0
1619 23:31:34.800041 DQM Delay:
1620 23:31:34.802296 DQM0 = 94, DQM1 = 90
1621 23:31:34.802764 DQ Delay:
1622 23:31:34.806257 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1623 23:31:34.809641 DQ4 =93, DQ5 =109, DQ6 =109, DQ7 =93
1624 23:31:34.812707 DQ8 =77, DQ9 =85, DQ10 =85, DQ11 =85
1625 23:31:34.815583 DQ12 =101, DQ13 =93, DQ14 =93, DQ15 =101
1626 23:31:34.816047
1627 23:31:34.816412
1628 23:31:34.816753 ==
1629 23:31:34.819291 Dram Type= 6, Freq= 0, CH_1, rank 0
1630 23:31:34.825899 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1631 23:31:34.826370 ==
1632 23:31:34.826737
1633 23:31:34.827078
1634 23:31:34.827406 TX Vref Scan disable
1635 23:31:34.829789 == TX Byte 0 ==
1636 23:31:34.832733 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1637 23:31:34.836072 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1638 23:31:34.839764 == TX Byte 1 ==
1639 23:31:34.842935 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1640 23:31:34.846208 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1641 23:31:34.849513 ==
1642 23:31:34.853117 Dram Type= 6, Freq= 0, CH_1, rank 0
1643 23:31:34.856139 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1644 23:31:34.856570 ==
1645 23:31:34.868991 TX Vref=22, minBit 3, minWin=26, winSum=434
1646 23:31:34.872085 TX Vref=24, minBit 3, minWin=26, winSum=440
1647 23:31:34.875505 TX Vref=26, minBit 3, minWin=26, winSum=439
1648 23:31:34.878849 TX Vref=28, minBit 3, minWin=26, winSum=442
1649 23:31:34.882139 TX Vref=30, minBit 3, minWin=26, winSum=443
1650 23:31:34.885553 TX Vref=32, minBit 0, minWin=26, winSum=444
1651 23:31:34.892099 [TxChooseVref] Worse bit 0, Min win 26, Win sum 444, Final Vref 32
1652 23:31:34.892648
1653 23:31:34.895703 Final TX Range 1 Vref 32
1654 23:31:34.896264
1655 23:31:34.896632 ==
1656 23:31:34.898989 Dram Type= 6, Freq= 0, CH_1, rank 0
1657 23:31:34.902586 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1658 23:31:34.903161 ==
1659 23:31:34.903536
1660 23:31:34.903879
1661 23:31:34.905746 TX Vref Scan disable
1662 23:31:34.909287 == TX Byte 0 ==
1663 23:31:34.912478 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1664 23:31:34.915862 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1665 23:31:34.919561 == TX Byte 1 ==
1666 23:31:34.923144 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1667 23:31:34.925644 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1668 23:31:34.926114
1669 23:31:34.929310 [DATLAT]
1670 23:31:34.929935 Freq=800, CH1 RK0
1671 23:31:34.930319
1672 23:31:34.932607 DATLAT Default: 0xa
1673 23:31:34.933162 0, 0xFFFF, sum = 0
1674 23:31:34.935679 1, 0xFFFF, sum = 0
1675 23:31:34.936251 2, 0xFFFF, sum = 0
1676 23:31:34.938867 3, 0xFFFF, sum = 0
1677 23:31:34.939352 4, 0xFFFF, sum = 0
1678 23:31:34.942856 5, 0xFFFF, sum = 0
1679 23:31:34.943424 6, 0xFFFF, sum = 0
1680 23:31:34.945570 7, 0xFFFF, sum = 0
1681 23:31:34.946079 8, 0xFFFF, sum = 0
1682 23:31:34.949405 9, 0x0, sum = 1
1683 23:31:34.950044 10, 0x0, sum = 2
1684 23:31:34.952201 11, 0x0, sum = 3
1685 23:31:34.952674 12, 0x0, sum = 4
1686 23:31:34.955831 best_step = 10
1687 23:31:34.956293
1688 23:31:34.956661 ==
1689 23:31:34.958994 Dram Type= 6, Freq= 0, CH_1, rank 0
1690 23:31:34.962445 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1691 23:31:34.963011 ==
1692 23:31:34.965649 RX Vref Scan: 1
1693 23:31:34.966216
1694 23:31:34.966585 Set Vref Range= 32 -> 127
1695 23:31:34.967035
1696 23:31:34.969012 RX Vref 32 -> 127, step: 1
1697 23:31:34.969474
1698 23:31:34.972064 RX Delay -79 -> 252, step: 8
1699 23:31:34.972526
1700 23:31:34.976116 Set Vref, RX VrefLevel [Byte0]: 32
1701 23:31:34.978685 [Byte1]: 32
1702 23:31:34.979162
1703 23:31:34.982640 Set Vref, RX VrefLevel [Byte0]: 33
1704 23:31:34.985483 [Byte1]: 33
1705 23:31:34.986101
1706 23:31:34.989356 Set Vref, RX VrefLevel [Byte0]: 34
1707 23:31:34.992111 [Byte1]: 34
1708 23:31:34.996339
1709 23:31:34.996896 Set Vref, RX VrefLevel [Byte0]: 35
1710 23:31:34.999479 [Byte1]: 35
1711 23:31:35.003611
1712 23:31:35.004095 Set Vref, RX VrefLevel [Byte0]: 36
1713 23:31:35.006748 [Byte1]: 36
1714 23:31:35.011800
1715 23:31:35.012362 Set Vref, RX VrefLevel [Byte0]: 37
1716 23:31:35.014323 [Byte1]: 37
1717 23:31:35.019257
1718 23:31:35.019810 Set Vref, RX VrefLevel [Byte0]: 38
1719 23:31:35.022209 [Byte1]: 38
1720 23:31:35.026898
1721 23:31:35.027453 Set Vref, RX VrefLevel [Byte0]: 39
1722 23:31:35.029446 [Byte1]: 39
1723 23:31:35.034343
1724 23:31:35.034924 Set Vref, RX VrefLevel [Byte0]: 40
1725 23:31:35.037394 [Byte1]: 40
1726 23:31:35.041653
1727 23:31:35.042214 Set Vref, RX VrefLevel [Byte0]: 41
1728 23:31:35.044765 [Byte1]: 41
1729 23:31:35.049569
1730 23:31:35.050185 Set Vref, RX VrefLevel [Byte0]: 42
1731 23:31:35.052479 [Byte1]: 42
1732 23:31:35.057160
1733 23:31:35.057798 Set Vref, RX VrefLevel [Byte0]: 43
1734 23:31:35.059569 [Byte1]: 43
1735 23:31:35.064598
1736 23:31:35.065155 Set Vref, RX VrefLevel [Byte0]: 44
1737 23:31:35.067314 [Byte1]: 44
1738 23:31:35.071996
1739 23:31:35.072552 Set Vref, RX VrefLevel [Byte0]: 45
1740 23:31:35.074848 [Byte1]: 45
1741 23:31:35.079185
1742 23:31:35.079653 Set Vref, RX VrefLevel [Byte0]: 46
1743 23:31:35.082534 [Byte1]: 46
1744 23:31:35.086694
1745 23:31:35.087162 Set Vref, RX VrefLevel [Byte0]: 47
1746 23:31:35.090194 [Byte1]: 47
1747 23:31:35.094197
1748 23:31:35.094622 Set Vref, RX VrefLevel [Byte0]: 48
1749 23:31:35.097855 [Byte1]: 48
1750 23:31:35.101539
1751 23:31:35.102054 Set Vref, RX VrefLevel [Byte0]: 49
1752 23:31:35.104729 [Byte1]: 49
1753 23:31:35.109364
1754 23:31:35.109877 Set Vref, RX VrefLevel [Byte0]: 50
1755 23:31:35.112863 [Byte1]: 50
1756 23:31:35.116969
1757 23:31:35.117386 Set Vref, RX VrefLevel [Byte0]: 51
1758 23:31:35.120280 [Byte1]: 51
1759 23:31:35.124158
1760 23:31:35.124575 Set Vref, RX VrefLevel [Byte0]: 52
1761 23:31:35.128000 [Byte1]: 52
1762 23:31:35.132279
1763 23:31:35.132703 Set Vref, RX VrefLevel [Byte0]: 53
1764 23:31:35.135428 [Byte1]: 53
1765 23:31:35.139633
1766 23:31:35.140152 Set Vref, RX VrefLevel [Byte0]: 54
1767 23:31:35.143365 [Byte1]: 54
1768 23:31:35.147206
1769 23:31:35.147728 Set Vref, RX VrefLevel [Byte0]: 55
1770 23:31:35.150699 [Byte1]: 55
1771 23:31:35.154888
1772 23:31:35.155308 Set Vref, RX VrefLevel [Byte0]: 56
1773 23:31:35.158247 [Byte1]: 56
1774 23:31:35.162323
1775 23:31:35.162743 Set Vref, RX VrefLevel [Byte0]: 57
1776 23:31:35.165823 [Byte1]: 57
1777 23:31:35.170269
1778 23:31:35.170861 Set Vref, RX VrefLevel [Byte0]: 58
1779 23:31:35.173324 [Byte1]: 58
1780 23:31:35.177521
1781 23:31:35.178149 Set Vref, RX VrefLevel [Byte0]: 59
1782 23:31:35.180744 [Byte1]: 59
1783 23:31:35.185354
1784 23:31:35.186082 Set Vref, RX VrefLevel [Byte0]: 60
1785 23:31:35.188430 [Byte1]: 60
1786 23:31:35.192549
1787 23:31:35.193015 Set Vref, RX VrefLevel [Byte0]: 61
1788 23:31:35.195637 [Byte1]: 61
1789 23:31:35.200235
1790 23:31:35.200816 Set Vref, RX VrefLevel [Byte0]: 62
1791 23:31:35.203661 [Byte1]: 62
1792 23:31:35.208003
1793 23:31:35.208469 Set Vref, RX VrefLevel [Byte0]: 63
1794 23:31:35.210917 [Byte1]: 63
1795 23:31:35.215094
1796 23:31:35.215720 Set Vref, RX VrefLevel [Byte0]: 64
1797 23:31:35.218346 [Byte1]: 64
1798 23:31:35.222914
1799 23:31:35.223377 Set Vref, RX VrefLevel [Byte0]: 65
1800 23:31:35.225705 [Byte1]: 65
1801 23:31:35.229976
1802 23:31:35.230544 Set Vref, RX VrefLevel [Byte0]: 66
1803 23:31:35.233902 [Byte1]: 66
1804 23:31:35.237529
1805 23:31:35.238044 Set Vref, RX VrefLevel [Byte0]: 67
1806 23:31:35.241503 [Byte1]: 67
1807 23:31:35.245340
1808 23:31:35.245975 Set Vref, RX VrefLevel [Byte0]: 68
1809 23:31:35.248590 [Byte1]: 68
1810 23:31:35.253273
1811 23:31:35.254007 Set Vref, RX VrefLevel [Byte0]: 69
1812 23:31:35.255925 [Byte1]: 69
1813 23:31:35.260719
1814 23:31:35.261288 Set Vref, RX VrefLevel [Byte0]: 70
1815 23:31:35.263425 [Byte1]: 70
1816 23:31:35.268315
1817 23:31:35.268878 Set Vref, RX VrefLevel [Byte0]: 71
1818 23:31:35.271070 [Byte1]: 71
1819 23:31:35.275117
1820 23:31:35.275579 Final RX Vref Byte 0 = 57 to rank0
1821 23:31:35.278608 Final RX Vref Byte 1 = 58 to rank0
1822 23:31:35.282084 Final RX Vref Byte 0 = 57 to rank1
1823 23:31:35.285752 Final RX Vref Byte 1 = 58 to rank1==
1824 23:31:35.289124 Dram Type= 6, Freq= 0, CH_1, rank 0
1825 23:31:35.295883 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1826 23:31:35.296457 ==
1827 23:31:35.296830 DQS Delay:
1828 23:31:35.297175 DQS0 = 0, DQS1 = 0
1829 23:31:35.299416 DQM Delay:
1830 23:31:35.299987 DQM0 = 95, DQM1 = 90
1831 23:31:35.302322 DQ Delay:
1832 23:31:35.302789 DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =92
1833 23:31:35.305859 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =92
1834 23:31:35.308807 DQ8 =80, DQ9 =80, DQ10 =92, DQ11 =84
1835 23:31:35.312907 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
1836 23:31:35.315971
1837 23:31:35.316536
1838 23:31:35.322171 [DQSOSCAuto] RK0, (LSB)MR18= 0x2c49, (MSB)MR19= 0x606, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
1839 23:31:35.325565 CH1 RK0: MR19=606, MR18=2C49
1840 23:31:35.332591 CH1_RK0: MR19=0x606, MR18=0x2C49, DQSOSC=391, MR23=63, INC=96, DEC=64
1841 23:31:35.333162
1842 23:31:35.335610 ----->DramcWriteLeveling(PI) begin...
1843 23:31:35.336100 ==
1844 23:31:35.339033 Dram Type= 6, Freq= 0, CH_1, rank 1
1845 23:31:35.342375 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1846 23:31:35.342857 ==
1847 23:31:35.345868 Write leveling (Byte 0): 27 => 27
1848 23:31:35.348869 Write leveling (Byte 1): 27 => 27
1849 23:31:35.352700 DramcWriteLeveling(PI) end<-----
1850 23:31:35.353285
1851 23:31:35.353719 ==
1852 23:31:35.355799 Dram Type= 6, Freq= 0, CH_1, rank 1
1853 23:31:35.358611 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1854 23:31:35.359079 ==
1855 23:31:35.362095 [Gating] SW mode calibration
1856 23:31:35.369335 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1857 23:31:35.375527 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1858 23:31:35.378813 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1859 23:31:35.382452 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1860 23:31:35.388935 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1861 23:31:35.392382 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1862 23:31:35.395410 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1863 23:31:35.402303 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1864 23:31:35.405317 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1865 23:31:35.409147 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1866 23:31:35.416026 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1867 23:31:35.418753 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1868 23:31:35.422121 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1869 23:31:35.425459 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1870 23:31:35.432220 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1871 23:31:35.435938 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1872 23:31:35.438905 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1873 23:31:35.446160 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 23:31:35.449239 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 23:31:35.452650 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
1876 23:31:35.458920 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 23:31:35.462092 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 23:31:35.465524 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 23:31:35.472565 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 23:31:35.475344 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 23:31:35.478985 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 23:31:35.485217 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 23:31:35.489345 0 9 4 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
1884 23:31:35.492578 0 9 8 | B1->B0 | 3434 3131 | 1 0 | (1 1) (1 1)
1885 23:31:35.499097 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1886 23:31:35.502054 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1887 23:31:35.505572 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1888 23:31:35.512654 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1889 23:31:35.515903 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1890 23:31:35.519041 0 10 0 | B1->B0 | 3434 3434 | 0 1 | (0 1) (1 0)
1891 23:31:35.522625 0 10 4 | B1->B0 | 2929 3131 | 1 0 | (1 0) (0 1)
1892 23:31:35.529419 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 23:31:35.532600 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1894 23:31:35.535923 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 23:31:35.542440 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 23:31:35.545826 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1897 23:31:35.549817 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1898 23:31:35.555894 0 11 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1899 23:31:35.559129 0 11 4 | B1->B0 | 3535 2525 | 0 0 | (0 0) (0 0)
1900 23:31:35.562649 0 11 8 | B1->B0 | 4646 3b3b | 0 0 | (0 0) (0 0)
1901 23:31:35.569554 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1902 23:31:35.572910 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1903 23:31:35.575864 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1904 23:31:35.582663 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1905 23:31:35.585916 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1906 23:31:35.589381 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1907 23:31:35.595993 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1908 23:31:35.599410 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1909 23:31:35.602355 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1910 23:31:35.605761 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1911 23:31:35.613056 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1912 23:31:35.616200 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1913 23:31:35.619276 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1914 23:31:35.625651 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1915 23:31:35.629382 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1916 23:31:35.632172 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1917 23:31:35.638938 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1918 23:31:35.642484 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1919 23:31:35.645782 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1920 23:31:35.652321 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1921 23:31:35.655922 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1922 23:31:35.659033 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1923 23:31:35.665901 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1924 23:31:35.668802 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1925 23:31:35.672473 Total UI for P1: 0, mck2ui 16
1926 23:31:35.675804 best dqsien dly found for B0: ( 0, 14, 4)
1927 23:31:35.679147 Total UI for P1: 0, mck2ui 16
1928 23:31:35.682579 best dqsien dly found for B1: ( 0, 14, 4)
1929 23:31:35.686115 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1930 23:31:35.688880 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1931 23:31:35.689308
1932 23:31:35.692127 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1933 23:31:35.696336 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1934 23:31:35.699007 [Gating] SW calibration Done
1935 23:31:35.699431 ==
1936 23:31:35.702263 Dram Type= 6, Freq= 0, CH_1, rank 1
1937 23:31:35.705416 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1938 23:31:35.706001 ==
1939 23:31:35.708889 RX Vref Scan: 0
1940 23:31:35.709312
1941 23:31:35.712099 RX Vref 0 -> 0, step: 1
1942 23:31:35.712520
1943 23:31:35.712859 RX Delay -130 -> 252, step: 16
1944 23:31:35.718892 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1945 23:31:35.722268 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1946 23:31:35.725866 iDelay=222, Bit 2, Center 85 (-18 ~ 189) 208
1947 23:31:35.729302 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1948 23:31:35.732410 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1949 23:31:35.739302 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1950 23:31:35.742385 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1951 23:31:35.745486 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1952 23:31:35.748917 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1953 23:31:35.752129 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1954 23:31:35.758705 iDelay=222, Bit 10, Center 93 (-18 ~ 205) 224
1955 23:31:35.762182 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1956 23:31:35.765713 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1957 23:31:35.768912 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1958 23:31:35.771977 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1959 23:31:35.779041 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1960 23:31:35.779163 ==
1961 23:31:35.782485 Dram Type= 6, Freq= 0, CH_1, rank 1
1962 23:31:35.785260 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1963 23:31:35.785353 ==
1964 23:31:35.785427 DQS Delay:
1965 23:31:35.789109 DQS0 = 0, DQS1 = 0
1966 23:31:35.789201 DQM Delay:
1967 23:31:35.792226 DQM0 = 93, DQM1 = 88
1968 23:31:35.792319 DQ Delay:
1969 23:31:35.796082 DQ0 =101, DQ1 =85, DQ2 =85, DQ3 =85
1970 23:31:35.799469 DQ4 =85, DQ5 =109, DQ6 =101, DQ7 =93
1971 23:31:35.802117 DQ8 =77, DQ9 =77, DQ10 =93, DQ11 =85
1972 23:31:35.805746 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1973 23:31:35.805910
1974 23:31:35.806011
1975 23:31:35.806101 ==
1976 23:31:35.808884 Dram Type= 6, Freq= 0, CH_1, rank 1
1977 23:31:35.812114 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1978 23:31:35.812288 ==
1979 23:31:35.812398
1980 23:31:35.815804
1981 23:31:35.815993 TX Vref Scan disable
1982 23:31:35.818921 == TX Byte 0 ==
1983 23:31:35.822455 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1984 23:31:35.825875 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1985 23:31:35.829072 == TX Byte 1 ==
1986 23:31:35.832732 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1987 23:31:35.835521 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1988 23:31:35.835814 ==
1989 23:31:35.838900 Dram Type= 6, Freq= 0, CH_1, rank 1
1990 23:31:35.846549 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1991 23:31:35.847023 ==
1992 23:31:35.857647 TX Vref=22, minBit 3, minWin=26, winSum=441
1993 23:31:35.860717 TX Vref=24, minBit 2, minWin=26, winSum=442
1994 23:31:35.864475 TX Vref=26, minBit 3, minWin=26, winSum=444
1995 23:31:35.868425 TX Vref=28, minBit 1, minWin=27, winSum=451
1996 23:31:35.870911 TX Vref=30, minBit 1, minWin=27, winSum=451
1997 23:31:35.874532 TX Vref=32, minBit 0, minWin=27, winSum=448
1998 23:31:35.881017 [TxChooseVref] Worse bit 1, Min win 27, Win sum 451, Final Vref 28
1999 23:31:35.881610
2000 23:31:35.884020 Final TX Range 1 Vref 28
2001 23:31:35.884486
2002 23:31:35.884853 ==
2003 23:31:35.887935 Dram Type= 6, Freq= 0, CH_1, rank 1
2004 23:31:35.890918 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2005 23:31:35.891547 ==
2006 23:31:35.892116
2007 23:31:35.894293
2008 23:31:35.894756 TX Vref Scan disable
2009 23:31:35.897855 == TX Byte 0 ==
2010 23:31:35.900983 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2011 23:31:35.904253 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2012 23:31:35.907845 == TX Byte 1 ==
2013 23:31:35.910888 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
2014 23:31:35.914124 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
2015 23:31:35.917352
2016 23:31:35.917869 [DATLAT]
2017 23:31:35.918245 Freq=800, CH1 RK1
2018 23:31:35.918594
2019 23:31:35.921097 DATLAT Default: 0xa
2020 23:31:35.921537 0, 0xFFFF, sum = 0
2021 23:31:35.924038 1, 0xFFFF, sum = 0
2022 23:31:35.924469 2, 0xFFFF, sum = 0
2023 23:31:35.927556 3, 0xFFFF, sum = 0
2024 23:31:35.927984 4, 0xFFFF, sum = 0
2025 23:31:35.930781 5, 0xFFFF, sum = 0
2026 23:31:35.934271 6, 0xFFFF, sum = 0
2027 23:31:35.934699 7, 0xFFFF, sum = 0
2028 23:31:35.937676 8, 0xFFFF, sum = 0
2029 23:31:35.938109 9, 0x0, sum = 1
2030 23:31:35.938453 10, 0x0, sum = 2
2031 23:31:35.940998 11, 0x0, sum = 3
2032 23:31:35.941427 12, 0x0, sum = 4
2033 23:31:35.944234 best_step = 10
2034 23:31:35.944762
2035 23:31:35.945163 ==
2036 23:31:35.947334 Dram Type= 6, Freq= 0, CH_1, rank 1
2037 23:31:35.951114 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2038 23:31:35.951719 ==
2039 23:31:35.954260 RX Vref Scan: 0
2040 23:31:35.954680
2041 23:31:35.955017 RX Vref 0 -> 0, step: 1
2042 23:31:35.955331
2043 23:31:35.957534 RX Delay -79 -> 252, step: 8
2044 23:31:35.964291 iDelay=209, Bit 0, Center 104 (9 ~ 200) 192
2045 23:31:35.968272 iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200
2046 23:31:35.971658 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
2047 23:31:35.974667 iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200
2048 23:31:35.978174 iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200
2049 23:31:35.981018 iDelay=209, Bit 5, Center 112 (17 ~ 208) 192
2050 23:31:35.987633 iDelay=209, Bit 6, Center 108 (9 ~ 208) 200
2051 23:31:35.991671 iDelay=209, Bit 7, Center 96 (-7 ~ 200) 208
2052 23:31:35.994588 iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208
2053 23:31:35.997785 iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208
2054 23:31:36.001637 iDelay=209, Bit 10, Center 92 (-7 ~ 192) 200
2055 23:31:36.007978 iDelay=209, Bit 11, Center 88 (-15 ~ 192) 208
2056 23:31:36.010960 iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216
2057 23:31:36.014513 iDelay=209, Bit 13, Center 96 (-7 ~ 200) 208
2058 23:31:36.017549 iDelay=209, Bit 14, Center 96 (-7 ~ 200) 208
2059 23:31:36.020966 iDelay=209, Bit 15, Center 96 (-7 ~ 200) 208
2060 23:31:36.021492 ==
2061 23:31:36.024687 Dram Type= 6, Freq= 0, CH_1, rank 1
2062 23:31:36.031360 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2063 23:31:36.031914 ==
2064 23:31:36.032333 DQS Delay:
2065 23:31:36.035168 DQS0 = 0, DQS1 = 0
2066 23:31:36.035699 DQM Delay:
2067 23:31:36.036038 DQM0 = 97, DQM1 = 91
2068 23:31:36.037822 DQ Delay:
2069 23:31:36.041027 DQ0 =104, DQ1 =92, DQ2 =84, DQ3 =92
2070 23:31:36.044704 DQ4 =92, DQ5 =112, DQ6 =108, DQ7 =96
2071 23:31:36.047876 DQ8 =80, DQ9 =80, DQ10 =92, DQ11 =88
2072 23:31:36.051024 DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =96
2073 23:31:36.051447
2074 23:31:36.051847
2075 23:31:36.057864 [DQSOSCAuto] RK1, (LSB)MR18= 0x430c, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 393 ps
2076 23:31:36.061573 CH1 RK1: MR19=606, MR18=430C
2077 23:31:36.068319 CH1_RK1: MR19=0x606, MR18=0x430C, DQSOSC=393, MR23=63, INC=95, DEC=63
2078 23:31:36.071175 [RxdqsGatingPostProcess] freq 800
2079 23:31:36.075010 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2080 23:31:36.077964 Pre-setting of DQS Precalculation
2081 23:31:36.084892 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2082 23:31:36.091619 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2083 23:31:36.098536 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2084 23:31:36.099068
2085 23:31:36.099404
2086 23:31:36.101812 [Calibration Summary] 1600 Mbps
2087 23:31:36.102343 CH 0, Rank 0
2088 23:31:36.105422 SW Impedance : PASS
2089 23:31:36.108327 DUTY Scan : NO K
2090 23:31:36.108857 ZQ Calibration : PASS
2091 23:31:36.111333 Jitter Meter : NO K
2092 23:31:36.114806 CBT Training : PASS
2093 23:31:36.115228 Write leveling : PASS
2094 23:31:36.118154 RX DQS gating : PASS
2095 23:31:36.118579 RX DQ/DQS(RDDQC) : PASS
2096 23:31:36.121374 TX DQ/DQS : PASS
2097 23:31:36.124757 RX DATLAT : PASS
2098 23:31:36.125180 RX DQ/DQS(Engine): PASS
2099 23:31:36.128186 TX OE : NO K
2100 23:31:36.128613 All Pass.
2101 23:31:36.128951
2102 23:31:36.131439 CH 0, Rank 1
2103 23:31:36.131862 SW Impedance : PASS
2104 23:31:36.134735 DUTY Scan : NO K
2105 23:31:36.137928 ZQ Calibration : PASS
2106 23:31:36.138354 Jitter Meter : NO K
2107 23:31:36.141649 CBT Training : PASS
2108 23:31:36.144798 Write leveling : PASS
2109 23:31:36.145226 RX DQS gating : PASS
2110 23:31:36.147995 RX DQ/DQS(RDDQC) : PASS
2111 23:31:36.151487 TX DQ/DQS : PASS
2112 23:31:36.151916 RX DATLAT : PASS
2113 23:31:36.154726 RX DQ/DQS(Engine): PASS
2114 23:31:36.158179 TX OE : NO K
2115 23:31:36.158602 All Pass.
2116 23:31:36.158934
2117 23:31:36.159244 CH 1, Rank 0
2118 23:31:36.161646 SW Impedance : PASS
2119 23:31:36.165195 DUTY Scan : NO K
2120 23:31:36.165777 ZQ Calibration : PASS
2121 23:31:36.168767 Jitter Meter : NO K
2122 23:31:36.169340 CBT Training : PASS
2123 23:31:36.171678 Write leveling : PASS
2124 23:31:36.174985 RX DQS gating : PASS
2125 23:31:36.175443 RX DQ/DQS(RDDQC) : PASS
2126 23:31:36.178299 TX DQ/DQS : PASS
2127 23:31:36.181511 RX DATLAT : PASS
2128 23:31:36.181962 RX DQ/DQS(Engine): PASS
2129 23:31:36.184679 TX OE : NO K
2130 23:31:36.185203 All Pass.
2131 23:31:36.185764
2132 23:31:36.188220 CH 1, Rank 1
2133 23:31:36.188640 SW Impedance : PASS
2134 23:31:36.192057 DUTY Scan : NO K
2135 23:31:36.195397 ZQ Calibration : PASS
2136 23:31:36.195820 Jitter Meter : NO K
2137 23:31:36.198141 CBT Training : PASS
2138 23:31:36.201738 Write leveling : PASS
2139 23:31:36.202262 RX DQS gating : PASS
2140 23:31:36.205009 RX DQ/DQS(RDDQC) : PASS
2141 23:31:36.205542 TX DQ/DQS : PASS
2142 23:31:36.208376 RX DATLAT : PASS
2143 23:31:36.211823 RX DQ/DQS(Engine): PASS
2144 23:31:36.212348 TX OE : NO K
2145 23:31:36.214971 All Pass.
2146 23:31:36.215389
2147 23:31:36.215722 DramC Write-DBI off
2148 23:31:36.218313 PER_BANK_REFRESH: Hybrid Mode
2149 23:31:36.221862 TX_TRACKING: ON
2150 23:31:36.222391 [GetDramInforAfterCalByMRR] Vendor 6.
2151 23:31:36.228208 [GetDramInforAfterCalByMRR] Revision 606.
2152 23:31:36.231683 [GetDramInforAfterCalByMRR] Revision 2 0.
2153 23:31:36.232110 MR0 0x3b3b
2154 23:31:36.232450 MR8 0x5151
2155 23:31:36.234859 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2156 23:31:36.235282
2157 23:31:36.238733 MR0 0x3b3b
2158 23:31:36.239156 MR8 0x5151
2159 23:31:36.241956 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2160 23:31:36.242379
2161 23:31:36.251992 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2162 23:31:36.255144 [FAST_K] Save calibration result to emmc
2163 23:31:36.258953 [FAST_K] Save calibration result to emmc
2164 23:31:36.262156 dram_init: config_dvfs: 1
2165 23:31:36.265615 dramc_set_vcore_voltage set vcore to 662500
2166 23:31:36.268825 Read voltage for 1200, 2
2167 23:31:36.269246 Vio18 = 0
2168 23:31:36.269720 Vcore = 662500
2169 23:31:36.271721 Vdram = 0
2170 23:31:36.272139 Vddq = 0
2171 23:31:36.272474 Vmddr = 0
2172 23:31:36.278820 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2173 23:31:36.281803 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2174 23:31:36.285516 MEM_TYPE=3, freq_sel=15
2175 23:31:36.288710 sv_algorithm_assistance_LP4_1600
2176 23:31:36.292527 ============ PULL DRAM RESETB DOWN ============
2177 23:31:36.295242 ========== PULL DRAM RESETB DOWN end =========
2178 23:31:36.302505 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2179 23:31:36.305155 ===================================
2180 23:31:36.305603 LPDDR4 DRAM CONFIGURATION
2181 23:31:36.308894 ===================================
2182 23:31:36.312235 EX_ROW_EN[0] = 0x0
2183 23:31:36.312765 EX_ROW_EN[1] = 0x0
2184 23:31:36.315767 LP4Y_EN = 0x0
2185 23:31:36.318793 WORK_FSP = 0x0
2186 23:31:36.319327 WL = 0x4
2187 23:31:36.322549 RL = 0x4
2188 23:31:36.323081 BL = 0x2
2189 23:31:36.325468 RPST = 0x0
2190 23:31:36.325921 RD_PRE = 0x0
2191 23:31:36.329219 WR_PRE = 0x1
2192 23:31:36.329787 WR_PST = 0x0
2193 23:31:36.332252 DBI_WR = 0x0
2194 23:31:36.332674 DBI_RD = 0x0
2195 23:31:36.335207 OTF = 0x1
2196 23:31:36.339068 ===================================
2197 23:31:36.341889 ===================================
2198 23:31:36.342313 ANA top config
2199 23:31:36.345940 ===================================
2200 23:31:36.349057 DLL_ASYNC_EN = 0
2201 23:31:36.352121 ALL_SLAVE_EN = 0
2202 23:31:36.352551 NEW_RANK_MODE = 1
2203 23:31:36.355504 DLL_IDLE_MODE = 1
2204 23:31:36.358635 LP45_APHY_COMB_EN = 1
2205 23:31:36.362239 TX_ODT_DIS = 1
2206 23:31:36.365356 NEW_8X_MODE = 1
2207 23:31:36.368748 ===================================
2208 23:31:36.369300 ===================================
2209 23:31:36.371975 data_rate = 2400
2210 23:31:36.375311 CKR = 1
2211 23:31:36.378786 DQ_P2S_RATIO = 8
2212 23:31:36.381850 ===================================
2213 23:31:36.385100 CA_P2S_RATIO = 8
2214 23:31:36.388881 DQ_CA_OPEN = 0
2215 23:31:36.392541 DQ_SEMI_OPEN = 0
2216 23:31:36.393082 CA_SEMI_OPEN = 0
2217 23:31:36.395647 CA_FULL_RATE = 0
2218 23:31:36.398207 DQ_CKDIV4_EN = 0
2219 23:31:36.402182 CA_CKDIV4_EN = 0
2220 23:31:36.405493 CA_PREDIV_EN = 0
2221 23:31:36.406082 PH8_DLY = 17
2222 23:31:36.408924 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2223 23:31:36.411818 DQ_AAMCK_DIV = 4
2224 23:31:36.415017 CA_AAMCK_DIV = 4
2225 23:31:36.418853 CA_ADMCK_DIV = 4
2226 23:31:36.421948 DQ_TRACK_CA_EN = 0
2227 23:31:36.425539 CA_PICK = 1200
2228 23:31:36.426167 CA_MCKIO = 1200
2229 23:31:36.428507 MCKIO_SEMI = 0
2230 23:31:36.432352 PLL_FREQ = 2366
2231 23:31:36.435776 DQ_UI_PI_RATIO = 32
2232 23:31:36.438571 CA_UI_PI_RATIO = 0
2233 23:31:36.442145 ===================================
2234 23:31:36.446011 ===================================
2235 23:31:36.448567 memory_type:LPDDR4
2236 23:31:36.449093 GP_NUM : 10
2237 23:31:36.452143 SRAM_EN : 1
2238 23:31:36.452565 MD32_EN : 0
2239 23:31:36.455720 ===================================
2240 23:31:36.458845 [ANA_INIT] >>>>>>>>>>>>>>
2241 23:31:36.461712 <<<<<< [CONFIGURE PHASE]: ANA_TX
2242 23:31:36.465426 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2243 23:31:36.469161 ===================================
2244 23:31:36.471995 data_rate = 2400,PCW = 0X5b00
2245 23:31:36.475612 ===================================
2246 23:31:36.478662 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2247 23:31:36.482083 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2248 23:31:36.488700 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2249 23:31:36.491984 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2250 23:31:36.495216 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2251 23:31:36.502012 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2252 23:31:36.502585 [ANA_INIT] flow start
2253 23:31:36.505710 [ANA_INIT] PLL >>>>>>>>
2254 23:31:36.506270 [ANA_INIT] PLL <<<<<<<<
2255 23:31:36.509289 [ANA_INIT] MIDPI >>>>>>>>
2256 23:31:36.512546 [ANA_INIT] MIDPI <<<<<<<<
2257 23:31:36.515674 [ANA_INIT] DLL >>>>>>>>
2258 23:31:36.516141 [ANA_INIT] DLL <<<<<<<<
2259 23:31:36.518759 [ANA_INIT] flow end
2260 23:31:36.522020 ============ LP4 DIFF to SE enter ============
2261 23:31:36.525740 ============ LP4 DIFF to SE exit ============
2262 23:31:36.528930 [ANA_INIT] <<<<<<<<<<<<<
2263 23:31:36.532246 [Flow] Enable top DCM control >>>>>
2264 23:31:36.535554 [Flow] Enable top DCM control <<<<<
2265 23:31:36.538642 Enable DLL master slave shuffle
2266 23:31:36.545922 ==============================================================
2267 23:31:36.546497 Gating Mode config
2268 23:31:36.552558 ==============================================================
2269 23:31:36.553130 Config description:
2270 23:31:36.562203 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2271 23:31:36.569068 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2272 23:31:36.575781 SELPH_MODE 0: By rank 1: By Phase
2273 23:31:36.578930 ==============================================================
2274 23:31:36.582636 GAT_TRACK_EN = 1
2275 23:31:36.585796 RX_GATING_MODE = 2
2276 23:31:36.588821 RX_GATING_TRACK_MODE = 2
2277 23:31:36.592191 SELPH_MODE = 1
2278 23:31:36.595378 PICG_EARLY_EN = 1
2279 23:31:36.599213 VALID_LAT_VALUE = 1
2280 23:31:36.602436 ==============================================================
2281 23:31:36.605518 Enter into Gating configuration >>>>
2282 23:31:36.609109 Exit from Gating configuration <<<<
2283 23:31:36.612396 Enter into DVFS_PRE_config >>>>>
2284 23:31:36.626059 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2285 23:31:36.626636 Exit from DVFS_PRE_config <<<<<
2286 23:31:36.629035 Enter into PICG configuration >>>>
2287 23:31:36.632766 Exit from PICG configuration <<<<
2288 23:31:36.635588 [RX_INPUT] configuration >>>>>
2289 23:31:36.638953 [RX_INPUT] configuration <<<<<
2290 23:31:36.645754 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2291 23:31:36.649226 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2292 23:31:36.656116 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2293 23:31:36.662522 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2294 23:31:36.669522 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2295 23:31:36.675601 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2296 23:31:36.679254 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2297 23:31:36.682447 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2298 23:31:36.686274 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2299 23:31:36.689776 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2300 23:31:36.695786 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2301 23:31:36.699775 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2302 23:31:36.703082 ===================================
2303 23:31:36.706249 LPDDR4 DRAM CONFIGURATION
2304 23:31:36.709147 ===================================
2305 23:31:36.709647 EX_ROW_EN[0] = 0x0
2306 23:31:36.712695 EX_ROW_EN[1] = 0x0
2307 23:31:36.713315 LP4Y_EN = 0x0
2308 23:31:36.715872 WORK_FSP = 0x0
2309 23:31:36.716341 WL = 0x4
2310 23:31:36.719424 RL = 0x4
2311 23:31:36.719891 BL = 0x2
2312 23:31:36.722978 RPST = 0x0
2313 23:31:36.723549 RD_PRE = 0x0
2314 23:31:36.725778 WR_PRE = 0x1
2315 23:31:36.729008 WR_PST = 0x0
2316 23:31:36.729514 DBI_WR = 0x0
2317 23:31:36.732717 DBI_RD = 0x0
2318 23:31:36.733287 OTF = 0x1
2319 23:31:36.735597 ===================================
2320 23:31:36.739419 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2321 23:31:36.742670 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2322 23:31:36.749471 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2323 23:31:36.752682 ===================================
2324 23:31:36.756159 LPDDR4 DRAM CONFIGURATION
2325 23:31:36.759160 ===================================
2326 23:31:36.759629 EX_ROW_EN[0] = 0x10
2327 23:31:36.762764 EX_ROW_EN[1] = 0x0
2328 23:31:36.763229 LP4Y_EN = 0x0
2329 23:31:36.766139 WORK_FSP = 0x0
2330 23:31:36.766707 WL = 0x4
2331 23:31:36.769410 RL = 0x4
2332 23:31:36.770057 BL = 0x2
2333 23:31:36.772616 RPST = 0x0
2334 23:31:36.773180 RD_PRE = 0x0
2335 23:31:36.776316 WR_PRE = 0x1
2336 23:31:36.776892 WR_PST = 0x0
2337 23:31:36.778930 DBI_WR = 0x0
2338 23:31:36.779396 DBI_RD = 0x0
2339 23:31:36.782383 OTF = 0x1
2340 23:31:36.785908 ===================================
2341 23:31:36.793004 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2342 23:31:36.793699 ==
2343 23:31:36.795774 Dram Type= 6, Freq= 0, CH_0, rank 0
2344 23:31:36.799136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2345 23:31:36.799719 ==
2346 23:31:36.802540 [Duty_Offset_Calibration]
2347 23:31:36.803003 B0:2 B1:1 CA:1
2348 23:31:36.803374
2349 23:31:36.805753 [DutyScan_Calibration_Flow] k_type=0
2350 23:31:36.816608
2351 23:31:36.817167 ==CLK 0==
2352 23:31:36.820224 Final CLK duty delay cell = 0
2353 23:31:36.822941 [0] MAX Duty = 5187%(X100), DQS PI = 24
2354 23:31:36.826264 [0] MIN Duty = 4875%(X100), DQS PI = 0
2355 23:31:36.826773 [0] AVG Duty = 5031%(X100)
2356 23:31:36.829839
2357 23:31:36.833244 CH0 CLK Duty spec in!! Max-Min= 312%
2358 23:31:36.836496 [DutyScan_Calibration_Flow] ====Done====
2359 23:31:36.837066
2360 23:31:36.840020 [DutyScan_Calibration_Flow] k_type=1
2361 23:31:36.854285
2362 23:31:36.854746 ==DQS 0 ==
2363 23:31:36.857826 Final DQS duty delay cell = -4
2364 23:31:36.860724 [-4] MAX Duty = 5124%(X100), DQS PI = 22
2365 23:31:36.863960 [-4] MIN Duty = 4751%(X100), DQS PI = 0
2366 23:31:36.867319 [-4] AVG Duty = 4937%(X100)
2367 23:31:36.867739
2368 23:31:36.868163 ==DQS 1 ==
2369 23:31:36.870501 Final DQS duty delay cell = -4
2370 23:31:36.873977 [-4] MAX Duty = 4969%(X100), DQS PI = 0
2371 23:31:36.877595 [-4] MIN Duty = 4844%(X100), DQS PI = 30
2372 23:31:36.880917 [-4] AVG Duty = 4906%(X100)
2373 23:31:36.881336
2374 23:31:36.884309 CH0 DQS 0 Duty spec in!! Max-Min= 373%
2375 23:31:36.884727
2376 23:31:36.887139 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2377 23:31:36.890423 [DutyScan_Calibration_Flow] ====Done====
2378 23:31:36.890842
2379 23:31:36.893878 [DutyScan_Calibration_Flow] k_type=3
2380 23:31:36.911311
2381 23:31:36.911879 ==DQM 0 ==
2382 23:31:36.914905 Final DQM duty delay cell = 0
2383 23:31:36.917972 [0] MAX Duty = 5156%(X100), DQS PI = 30
2384 23:31:36.921512 [0] MIN Duty = 4906%(X100), DQS PI = 50
2385 23:31:36.924676 [0] AVG Duty = 5031%(X100)
2386 23:31:36.925131
2387 23:31:36.925494 ==DQM 1 ==
2388 23:31:36.927642 Final DQM duty delay cell = 0
2389 23:31:36.931048 [0] MAX Duty = 5124%(X100), DQS PI = 8
2390 23:31:36.934155 [0] MIN Duty = 5031%(X100), DQS PI = 14
2391 23:31:36.934576 [0] AVG Duty = 5077%(X100)
2392 23:31:36.937646
2393 23:31:36.941048 CH0 DQM 0 Duty spec in!! Max-Min= 250%
2394 23:31:36.941466
2395 23:31:36.944842 CH0 DQM 1 Duty spec in!! Max-Min= 93%
2396 23:31:36.947931 [DutyScan_Calibration_Flow] ====Done====
2397 23:31:36.948486
2398 23:31:36.951331 [DutyScan_Calibration_Flow] k_type=2
2399 23:31:36.968011
2400 23:31:36.968796 ==DQ 0 ==
2401 23:31:36.971091 Final DQ duty delay cell = 0
2402 23:31:36.974403 [0] MAX Duty = 5031%(X100), DQS PI = 24
2403 23:31:36.977619 [0] MIN Duty = 4875%(X100), DQS PI = 62
2404 23:31:36.978096 [0] AVG Duty = 4953%(X100)
2405 23:31:36.978465
2406 23:31:36.981006 ==DQ 1 ==
2407 23:31:36.984470 Final DQ duty delay cell = 0
2408 23:31:36.987713 [0] MAX Duty = 5093%(X100), DQS PI = 10
2409 23:31:36.990653 [0] MIN Duty = 4938%(X100), DQS PI = 36
2410 23:31:36.991116 [0] AVG Duty = 5015%(X100)
2411 23:31:36.991483
2412 23:31:36.994740 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2413 23:31:36.997465
2414 23:31:37.001004 CH0 DQ 1 Duty spec in!! Max-Min= 155%
2415 23:31:37.004530 [DutyScan_Calibration_Flow] ====Done====
2416 23:31:37.005091 ==
2417 23:31:37.007488 Dram Type= 6, Freq= 0, CH_1, rank 0
2418 23:31:37.010938 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2419 23:31:37.011507 ==
2420 23:31:37.014917 [Duty_Offset_Calibration]
2421 23:31:37.015479 B0:1 B1:0 CA:0
2422 23:31:37.015847
2423 23:31:37.017247 [DutyScan_Calibration_Flow] k_type=0
2424 23:31:37.026971
2425 23:31:37.027575 ==CLK 0==
2426 23:31:37.030110 Final CLK duty delay cell = -4
2427 23:31:37.034259 [-4] MAX Duty = 5031%(X100), DQS PI = 24
2428 23:31:37.037172 [-4] MIN Duty = 4875%(X100), DQS PI = 50
2429 23:31:37.040236 [-4] AVG Duty = 4953%(X100)
2430 23:31:37.040801
2431 23:31:37.043578 CH1 CLK Duty spec in!! Max-Min= 156%
2432 23:31:37.046973 [DutyScan_Calibration_Flow] ====Done====
2433 23:31:37.047536
2434 23:31:37.050269 [DutyScan_Calibration_Flow] k_type=1
2435 23:31:37.067086
2436 23:31:37.067654 ==DQS 0 ==
2437 23:31:37.070297 Final DQS duty delay cell = 0
2438 23:31:37.073569 [0] MAX Duty = 5094%(X100), DQS PI = 24
2439 23:31:37.076684 [0] MIN Duty = 4844%(X100), DQS PI = 0
2440 23:31:37.077247 [0] AVG Duty = 4969%(X100)
2441 23:31:37.080018
2442 23:31:37.080579 ==DQS 1 ==
2443 23:31:37.083216 Final DQS duty delay cell = 0
2444 23:31:37.086612 [0] MAX Duty = 5187%(X100), DQS PI = 18
2445 23:31:37.089640 [0] MIN Duty = 4969%(X100), DQS PI = 8
2446 23:31:37.090127 [0] AVG Duty = 5078%(X100)
2447 23:31:37.093221
2448 23:31:37.096960 CH1 DQS 0 Duty spec in!! Max-Min= 250%
2449 23:31:37.097534
2450 23:31:37.100230 CH1 DQS 1 Duty spec in!! Max-Min= 218%
2451 23:31:37.103071 [DutyScan_Calibration_Flow] ====Done====
2452 23:31:37.103541
2453 23:31:37.106594 [DutyScan_Calibration_Flow] k_type=3
2454 23:31:37.123393
2455 23:31:37.123956 ==DQM 0 ==
2456 23:31:37.126943 Final DQM duty delay cell = 0
2457 23:31:37.130385 [0] MAX Duty = 5156%(X100), DQS PI = 6
2458 23:31:37.133425 [0] MIN Duty = 5031%(X100), DQS PI = 0
2459 23:31:37.134036 [0] AVG Duty = 5093%(X100)
2460 23:31:37.136706
2461 23:31:37.137223 ==DQM 1 ==
2462 23:31:37.139768 Final DQM duty delay cell = 0
2463 23:31:37.142954 [0] MAX Duty = 5031%(X100), DQS PI = 16
2464 23:31:37.146215 [0] MIN Duty = 4907%(X100), DQS PI = 34
2465 23:31:37.146682 [0] AVG Duty = 4969%(X100)
2466 23:31:37.147055
2467 23:31:37.153104 CH1 DQM 0 Duty spec in!! Max-Min= 125%
2468 23:31:37.153767
2469 23:31:37.156469 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2470 23:31:37.159730 [DutyScan_Calibration_Flow] ====Done====
2471 23:31:37.160200
2472 23:31:37.163344 [DutyScan_Calibration_Flow] k_type=2
2473 23:31:37.178647
2474 23:31:37.179070 ==DQ 0 ==
2475 23:31:37.182091 Final DQ duty delay cell = -4
2476 23:31:37.185631 [-4] MAX Duty = 5062%(X100), DQS PI = 8
2477 23:31:37.188863 [-4] MIN Duty = 4906%(X100), DQS PI = 44
2478 23:31:37.189387 [-4] AVG Duty = 4984%(X100)
2479 23:31:37.192399
2480 23:31:37.192821 ==DQ 1 ==
2481 23:31:37.195475 Final DQ duty delay cell = 0
2482 23:31:37.199129 [0] MAX Duty = 5125%(X100), DQS PI = 20
2483 23:31:37.202305 [0] MIN Duty = 4938%(X100), DQS PI = 34
2484 23:31:37.202732 [0] AVG Duty = 5031%(X100)
2485 23:31:37.203072
2486 23:31:37.206036 CH1 DQ 0 Duty spec in!! Max-Min= 156%
2487 23:31:37.206461
2488 23:31:37.209468 CH1 DQ 1 Duty spec in!! Max-Min= 187%
2489 23:31:37.216431 [DutyScan_Calibration_Flow] ====Done====
2490 23:31:37.219416 nWR fixed to 30
2491 23:31:37.219889 [ModeRegInit_LP4] CH0 RK0
2492 23:31:37.223082 [ModeRegInit_LP4] CH0 RK1
2493 23:31:37.226078 [ModeRegInit_LP4] CH1 RK0
2494 23:31:37.226508 [ModeRegInit_LP4] CH1 RK1
2495 23:31:37.229399 match AC timing 7
2496 23:31:37.232745 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2497 23:31:37.236151 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2498 23:31:37.242727 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2499 23:31:37.246066 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2500 23:31:37.252972 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2501 23:31:37.253396 ==
2502 23:31:37.255917 Dram Type= 6, Freq= 0, CH_0, rank 0
2503 23:31:37.260000 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2504 23:31:37.260528 ==
2505 23:31:37.266300 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2506 23:31:37.269857 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2507 23:31:37.279699 [CA 0] Center 39 (8~70) winsize 63
2508 23:31:37.282332 [CA 1] Center 39 (8~70) winsize 63
2509 23:31:37.286057 [CA 2] Center 35 (4~66) winsize 63
2510 23:31:37.289732 [CA 3] Center 34 (4~65) winsize 62
2511 23:31:37.292481 [CA 4] Center 33 (3~64) winsize 62
2512 23:31:37.295679 [CA 5] Center 32 (3~62) winsize 60
2513 23:31:37.296104
2514 23:31:37.299365 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2515 23:31:37.299788
2516 23:31:37.302268 [CATrainingPosCal] consider 1 rank data
2517 23:31:37.305639 u2DelayCellTimex100 = 270/100 ps
2518 23:31:37.309342 CA0 delay=39 (8~70),Diff = 7 PI (33 cell)
2519 23:31:37.312317 CA1 delay=39 (8~70),Diff = 7 PI (33 cell)
2520 23:31:37.319255 CA2 delay=35 (4~66),Diff = 3 PI (14 cell)
2521 23:31:37.322804 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2522 23:31:37.325892 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2523 23:31:37.329220 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2524 23:31:37.329826
2525 23:31:37.332479 CA PerBit enable=1, Macro0, CA PI delay=32
2526 23:31:37.332901
2527 23:31:37.336047 [CBTSetCACLKResult] CA Dly = 32
2528 23:31:37.336467 CS Dly: 6 (0~37)
2529 23:31:37.336803 ==
2530 23:31:37.339206 Dram Type= 6, Freq= 0, CH_0, rank 1
2531 23:31:37.346208 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2532 23:31:37.346732 ==
2533 23:31:37.349531 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2534 23:31:37.356178 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2535 23:31:37.364794 [CA 0] Center 38 (8~69) winsize 62
2536 23:31:37.368324 [CA 1] Center 38 (8~69) winsize 62
2537 23:31:37.371489 [CA 2] Center 35 (4~66) winsize 63
2538 23:31:37.374947 [CA 3] Center 34 (4~65) winsize 62
2539 23:31:37.378563 [CA 4] Center 33 (3~64) winsize 62
2540 23:31:37.382067 [CA 5] Center 32 (3~62) winsize 60
2541 23:31:37.382668
2542 23:31:37.384969 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2543 23:31:37.385536
2544 23:31:37.388283 [CATrainingPosCal] consider 2 rank data
2545 23:31:37.391409 u2DelayCellTimex100 = 270/100 ps
2546 23:31:37.394754 CA0 delay=38 (8~69),Diff = 6 PI (28 cell)
2547 23:31:37.398190 CA1 delay=38 (8~69),Diff = 6 PI (28 cell)
2548 23:31:37.404897 CA2 delay=35 (4~66),Diff = 3 PI (14 cell)
2549 23:31:37.408286 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2550 23:31:37.411776 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2551 23:31:37.414838 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2552 23:31:37.415411
2553 23:31:37.418354 CA PerBit enable=1, Macro0, CA PI delay=32
2554 23:31:37.418928
2555 23:31:37.421692 [CBTSetCACLKResult] CA Dly = 32
2556 23:31:37.422304 CS Dly: 6 (0~38)
2557 23:31:37.422693
2558 23:31:37.425191 ----->DramcWriteLeveling(PI) begin...
2559 23:31:37.427955 ==
2560 23:31:37.431570 Dram Type= 6, Freq= 0, CH_0, rank 0
2561 23:31:37.434744 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2562 23:31:37.435214 ==
2563 23:31:37.438309 Write leveling (Byte 0): 34 => 34
2564 23:31:37.441446 Write leveling (Byte 1): 31 => 31
2565 23:31:37.444859 DramcWriteLeveling(PI) end<-----
2566 23:31:37.445421
2567 23:31:37.445911 ==
2568 23:31:37.448382 Dram Type= 6, Freq= 0, CH_0, rank 0
2569 23:31:37.451794 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2570 23:31:37.452366 ==
2571 23:31:37.454828 [Gating] SW mode calibration
2572 23:31:37.461988 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2573 23:31:37.465166 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2574 23:31:37.471574 0 15 0 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
2575 23:31:37.475692 0 15 4 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
2576 23:31:37.478107 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2577 23:31:37.485335 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2578 23:31:37.488643 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2579 23:31:37.491648 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2580 23:31:37.498638 0 15 24 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
2581 23:31:37.501927 0 15 28 | B1->B0 | 3434 2626 | 1 0 | (1 1) (0 0)
2582 23:31:37.505119 1 0 0 | B1->B0 | 2d2d 2323 | 1 0 | (1 0) (0 0)
2583 23:31:37.511947 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2584 23:31:37.515095 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2585 23:31:37.518537 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2586 23:31:37.525069 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2587 23:31:37.528751 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2588 23:31:37.531428 1 0 24 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
2589 23:31:37.535088 1 0 28 | B1->B0 | 2626 4646 | 0 0 | (0 0) (0 0)
2590 23:31:37.541698 1 1 0 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
2591 23:31:37.545309 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2592 23:31:37.548685 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2593 23:31:37.555161 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2594 23:31:37.558401 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2595 23:31:37.562024 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2596 23:31:37.568435 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2597 23:31:37.572200 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2598 23:31:37.575082 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2599 23:31:37.581919 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2600 23:31:37.585434 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2601 23:31:37.588614 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2602 23:31:37.594952 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2603 23:31:37.598287 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2604 23:31:37.601877 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2605 23:31:37.608849 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2606 23:31:37.611846 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2607 23:31:37.614755 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2608 23:31:37.621453 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2609 23:31:37.625246 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2610 23:31:37.628166 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2611 23:31:37.634729 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2612 23:31:37.638127 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2613 23:31:37.642235 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2614 23:31:37.648408 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2615 23:31:37.648988 Total UI for P1: 0, mck2ui 16
2616 23:31:37.651864 best dqsien dly found for B0: ( 1, 3, 28)
2617 23:31:37.658461 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2618 23:31:37.661469 Total UI for P1: 0, mck2ui 16
2619 23:31:37.665110 best dqsien dly found for B1: ( 1, 3, 30)
2620 23:31:37.668450 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2621 23:31:37.671373 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2622 23:31:37.671839
2623 23:31:37.675028 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2624 23:31:37.678137 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2625 23:31:37.681538 [Gating] SW calibration Done
2626 23:31:37.682040 ==
2627 23:31:37.685028 Dram Type= 6, Freq= 0, CH_0, rank 0
2628 23:31:37.688286 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2629 23:31:37.688754 ==
2630 23:31:37.691634 RX Vref Scan: 0
2631 23:31:37.692096
2632 23:31:37.692460 RX Vref 0 -> 0, step: 1
2633 23:31:37.694703
2634 23:31:37.695229 RX Delay -40 -> 252, step: 8
2635 23:31:37.701945 iDelay=200, Bit 0, Center 123 (48 ~ 199) 152
2636 23:31:37.705008 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2637 23:31:37.708127 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2638 23:31:37.711644 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2639 23:31:37.715303 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2640 23:31:37.718200 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2641 23:31:37.725411 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2642 23:31:37.728604 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2643 23:31:37.731784 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2644 23:31:37.734969 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
2645 23:31:37.738202 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2646 23:31:37.745146 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2647 23:31:37.748604 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2648 23:31:37.751909 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2649 23:31:37.755385 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2650 23:31:37.758644 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2651 23:31:37.762211 ==
2652 23:31:37.762790 Dram Type= 6, Freq= 0, CH_0, rank 0
2653 23:31:37.769343 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2654 23:31:37.770015 ==
2655 23:31:37.770397 DQS Delay:
2656 23:31:37.772024 DQS0 = 0, DQS1 = 0
2657 23:31:37.772489 DQM Delay:
2658 23:31:37.775384 DQM0 = 121, DQM1 = 112
2659 23:31:37.775867 DQ Delay:
2660 23:31:37.778544 DQ0 =123, DQ1 =123, DQ2 =119, DQ3 =119
2661 23:31:37.782170 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2662 23:31:37.784810 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
2663 23:31:37.788685 DQ12 =115, DQ13 =123, DQ14 =123, DQ15 =119
2664 23:31:37.789151
2665 23:31:37.789515
2666 23:31:37.789927 ==
2667 23:31:37.791854 Dram Type= 6, Freq= 0, CH_0, rank 0
2668 23:31:37.798688 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2669 23:31:37.799280 ==
2670 23:31:37.799780
2671 23:31:37.800251
2672 23:31:37.800709 TX Vref Scan disable
2673 23:31:37.801822 == TX Byte 0 ==
2674 23:31:37.805195 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2675 23:31:37.811485 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2676 23:31:37.811950 == TX Byte 1 ==
2677 23:31:37.814920 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2678 23:31:37.822184 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2679 23:31:37.822763 ==
2680 23:31:37.825090 Dram Type= 6, Freq= 0, CH_0, rank 0
2681 23:31:37.828509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2682 23:31:37.828995 ==
2683 23:31:37.839969 TX Vref=22, minBit 4, minWin=24, winSum=403
2684 23:31:37.843331 TX Vref=24, minBit 3, minWin=25, winSum=415
2685 23:31:37.846230 TX Vref=26, minBit 12, minWin=25, winSum=422
2686 23:31:37.850159 TX Vref=28, minBit 0, minWin=26, winSum=423
2687 23:31:37.852969 TX Vref=30, minBit 0, minWin=26, winSum=421
2688 23:31:37.859832 TX Vref=32, minBit 4, minWin=25, winSum=419
2689 23:31:37.863168 [TxChooseVref] Worse bit 0, Min win 26, Win sum 423, Final Vref 28
2690 23:31:37.863636
2691 23:31:37.866140 Final TX Range 1 Vref 28
2692 23:31:37.866607
2693 23:31:37.866975 ==
2694 23:31:37.869967 Dram Type= 6, Freq= 0, CH_0, rank 0
2695 23:31:37.873178 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2696 23:31:37.873840 ==
2697 23:31:37.876569
2698 23:31:37.877135
2699 23:31:37.877505 TX Vref Scan disable
2700 23:31:37.880306 == TX Byte 0 ==
2701 23:31:37.883189 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2702 23:31:37.886446 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2703 23:31:37.889914 == TX Byte 1 ==
2704 23:31:37.893404 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2705 23:31:37.896108 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2706 23:31:37.899464
2707 23:31:37.899926 [DATLAT]
2708 23:31:37.900293 Freq=1200, CH0 RK0
2709 23:31:37.900637
2710 23:31:37.903176 DATLAT Default: 0xd
2711 23:31:37.903757 0, 0xFFFF, sum = 0
2712 23:31:37.906053 1, 0xFFFF, sum = 0
2713 23:31:37.906528 2, 0xFFFF, sum = 0
2714 23:31:37.909620 3, 0xFFFF, sum = 0
2715 23:31:37.910206 4, 0xFFFF, sum = 0
2716 23:31:37.913703 5, 0xFFFF, sum = 0
2717 23:31:37.914273 6, 0xFFFF, sum = 0
2718 23:31:37.916753 7, 0xFFFF, sum = 0
2719 23:31:37.919408 8, 0xFFFF, sum = 0
2720 23:31:37.919849 9, 0xFFFF, sum = 0
2721 23:31:37.922751 10, 0xFFFF, sum = 0
2722 23:31:37.923240 11, 0xFFFF, sum = 0
2723 23:31:37.926293 12, 0x0, sum = 1
2724 23:31:37.926877 13, 0x0, sum = 2
2725 23:31:37.929997 14, 0x0, sum = 3
2726 23:31:37.930468 15, 0x0, sum = 4
2727 23:31:37.930845 best_step = 13
2728 23:31:37.931190
2729 23:31:37.932846 ==
2730 23:31:37.933448 Dram Type= 6, Freq= 0, CH_0, rank 0
2731 23:31:37.939500 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2732 23:31:37.939973 ==
2733 23:31:37.940343 RX Vref Scan: 1
2734 23:31:37.940687
2735 23:31:37.942866 Set Vref Range= 32 -> 127
2736 23:31:37.943331
2737 23:31:37.946604 RX Vref 32 -> 127, step: 1
2738 23:31:37.947172
2739 23:31:37.950062 RX Delay -13 -> 252, step: 4
2740 23:31:37.950653
2741 23:31:37.953416 Set Vref, RX VrefLevel [Byte0]: 32
2742 23:31:37.956378 [Byte1]: 32
2743 23:31:37.956846
2744 23:31:37.959384 Set Vref, RX VrefLevel [Byte0]: 33
2745 23:31:37.963088 [Byte1]: 33
2746 23:31:37.963661
2747 23:31:37.966271 Set Vref, RX VrefLevel [Byte0]: 34
2748 23:31:37.969360 [Byte1]: 34
2749 23:31:37.973839
2750 23:31:37.974411 Set Vref, RX VrefLevel [Byte0]: 35
2751 23:31:37.976851 [Byte1]: 35
2752 23:31:37.982366
2753 23:31:37.982939 Set Vref, RX VrefLevel [Byte0]: 36
2754 23:31:37.985051 [Byte1]: 36
2755 23:31:37.989504
2756 23:31:37.990145 Set Vref, RX VrefLevel [Byte0]: 37
2757 23:31:37.993365 [Byte1]: 37
2758 23:31:37.997929
2759 23:31:37.998493 Set Vref, RX VrefLevel [Byte0]: 38
2760 23:31:38.001349 [Byte1]: 38
2761 23:31:38.005395
2762 23:31:38.006034 Set Vref, RX VrefLevel [Byte0]: 39
2763 23:31:38.008675 [Byte1]: 39
2764 23:31:38.013501
2765 23:31:38.014126 Set Vref, RX VrefLevel [Byte0]: 40
2766 23:31:38.016661 [Byte1]: 40
2767 23:31:38.021361
2768 23:31:38.021966 Set Vref, RX VrefLevel [Byte0]: 41
2769 23:31:38.024556 [Byte1]: 41
2770 23:31:38.028979
2771 23:31:38.032671 Set Vref, RX VrefLevel [Byte0]: 42
2772 23:31:38.033244 [Byte1]: 42
2773 23:31:38.037010
2774 23:31:38.037474 Set Vref, RX VrefLevel [Byte0]: 43
2775 23:31:38.040635 [Byte1]: 43
2776 23:31:38.044858
2777 23:31:38.045417 Set Vref, RX VrefLevel [Byte0]: 44
2778 23:31:38.048429 [Byte1]: 44
2779 23:31:38.053143
2780 23:31:38.053752 Set Vref, RX VrefLevel [Byte0]: 45
2781 23:31:38.056272 [Byte1]: 45
2782 23:31:38.061420
2783 23:31:38.062029 Set Vref, RX VrefLevel [Byte0]: 46
2784 23:31:38.063696 [Byte1]: 46
2785 23:31:38.069286
2786 23:31:38.069878 Set Vref, RX VrefLevel [Byte0]: 47
2787 23:31:38.071798 [Byte1]: 47
2788 23:31:38.076289
2789 23:31:38.076840 Set Vref, RX VrefLevel [Byte0]: 48
2790 23:31:38.079907 [Byte1]: 48
2791 23:31:38.084564
2792 23:31:38.085019 Set Vref, RX VrefLevel [Byte0]: 49
2793 23:31:38.087866 [Byte1]: 49
2794 23:31:38.092091
2795 23:31:38.092549 Set Vref, RX VrefLevel [Byte0]: 50
2796 23:31:38.095425 [Byte1]: 50
2797 23:31:38.100116
2798 23:31:38.100669 Set Vref, RX VrefLevel [Byte0]: 51
2799 23:31:38.104032 [Byte1]: 51
2800 23:31:38.108055
2801 23:31:38.108633 Set Vref, RX VrefLevel [Byte0]: 52
2802 23:31:38.111047 [Byte1]: 52
2803 23:31:38.116180
2804 23:31:38.116823 Set Vref, RX VrefLevel [Byte0]: 53
2805 23:31:38.119433 [Byte1]: 53
2806 23:31:38.123813
2807 23:31:38.124395 Set Vref, RX VrefLevel [Byte0]: 54
2808 23:31:38.127205 [Byte1]: 54
2809 23:31:38.132144
2810 23:31:38.132711 Set Vref, RX VrefLevel [Byte0]: 55
2811 23:31:38.135126 [Byte1]: 55
2812 23:31:38.139274
2813 23:31:38.139731 Set Vref, RX VrefLevel [Byte0]: 56
2814 23:31:38.143143 [Byte1]: 56
2815 23:31:38.147850
2816 23:31:38.148422 Set Vref, RX VrefLevel [Byte0]: 57
2817 23:31:38.150922 [Byte1]: 57
2818 23:31:38.155123
2819 23:31:38.155535 Set Vref, RX VrefLevel [Byte0]: 58
2820 23:31:38.158399 [Byte1]: 58
2821 23:31:38.163263
2822 23:31:38.163691 Set Vref, RX VrefLevel [Byte0]: 59
2823 23:31:38.166766 [Byte1]: 59
2824 23:31:38.170829
2825 23:31:38.171244 Set Vref, RX VrefLevel [Byte0]: 60
2826 23:31:38.175216 [Byte1]: 60
2827 23:31:38.179158
2828 23:31:38.179583 Set Vref, RX VrefLevel [Byte0]: 61
2829 23:31:38.182539 [Byte1]: 61
2830 23:31:38.186884
2831 23:31:38.187406 Set Vref, RX VrefLevel [Byte0]: 62
2832 23:31:38.190386 [Byte1]: 62
2833 23:31:38.194822
2834 23:31:38.195335 Set Vref, RX VrefLevel [Byte0]: 63
2835 23:31:38.198036 [Byte1]: 63
2836 23:31:38.202319
2837 23:31:38.203003 Set Vref, RX VrefLevel [Byte0]: 64
2838 23:31:38.205555 [Byte1]: 64
2839 23:31:38.210605
2840 23:31:38.211161 Set Vref, RX VrefLevel [Byte0]: 65
2841 23:31:38.213727 [Byte1]: 65
2842 23:31:38.218245
2843 23:31:38.218709 Set Vref, RX VrefLevel [Byte0]: 66
2844 23:31:38.221969 [Byte1]: 66
2845 23:31:38.226799
2846 23:31:38.227213 Set Vref, RX VrefLevel [Byte0]: 67
2847 23:31:38.229762 [Byte1]: 67
2848 23:31:38.234466
2849 23:31:38.234900 Set Vref, RX VrefLevel [Byte0]: 68
2850 23:31:38.237404 [Byte1]: 68
2851 23:31:38.242355
2852 23:31:38.242883 Set Vref, RX VrefLevel [Byte0]: 69
2853 23:31:38.245452 [Byte1]: 69
2854 23:31:38.250203
2855 23:31:38.250724 Set Vref, RX VrefLevel [Byte0]: 70
2856 23:31:38.253402 [Byte1]: 70
2857 23:31:38.257842
2858 23:31:38.258467 Final RX Vref Byte 0 = 54 to rank0
2859 23:31:38.261077 Final RX Vref Byte 1 = 54 to rank0
2860 23:31:38.264291 Final RX Vref Byte 0 = 54 to rank1
2861 23:31:38.267564 Final RX Vref Byte 1 = 54 to rank1==
2862 23:31:38.271291 Dram Type= 6, Freq= 0, CH_0, rank 0
2863 23:31:38.277764 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2864 23:31:38.278383 ==
2865 23:31:38.278759 DQS Delay:
2866 23:31:38.279099 DQS0 = 0, DQS1 = 0
2867 23:31:38.281361 DQM Delay:
2868 23:31:38.281856 DQM0 = 120, DQM1 = 112
2869 23:31:38.285124 DQ Delay:
2870 23:31:38.287764 DQ0 =120, DQ1 =122, DQ2 =118, DQ3 =118
2871 23:31:38.291466 DQ4 =122, DQ5 =112, DQ6 =126, DQ7 =128
2872 23:31:38.294506 DQ8 =100, DQ9 =102, DQ10 =114, DQ11 =106
2873 23:31:38.298202 DQ12 =118, DQ13 =118, DQ14 =124, DQ15 =120
2874 23:31:38.298756
2875 23:31:38.299119
2876 23:31:38.304698 [DQSOSCAuto] RK0, (LSB)MR18= 0x110a, (MSB)MR19= 0x404, tDQSOscB0 = 406 ps tDQSOscB1 = 403 ps
2877 23:31:38.308154 CH0 RK0: MR19=404, MR18=110A
2878 23:31:38.314288 CH0_RK0: MR19=0x404, MR18=0x110A, DQSOSC=403, MR23=63, INC=40, DEC=26
2879 23:31:38.314845
2880 23:31:38.317740 ----->DramcWriteLeveling(PI) begin...
2881 23:31:38.318163 ==
2882 23:31:38.321089 Dram Type= 6, Freq= 0, CH_0, rank 1
2883 23:31:38.324962 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2884 23:31:38.327805 ==
2885 23:31:38.328231 Write leveling (Byte 0): 34 => 34
2886 23:31:38.331315 Write leveling (Byte 1): 28 => 28
2887 23:31:38.334728 DramcWriteLeveling(PI) end<-----
2888 23:31:38.335247
2889 23:31:38.335578 ==
2890 23:31:38.338027 Dram Type= 6, Freq= 0, CH_0, rank 1
2891 23:31:38.345033 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2892 23:31:38.345561 ==
2893 23:31:38.345964 [Gating] SW mode calibration
2894 23:31:38.354780 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2895 23:31:38.357670 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2896 23:31:38.364265 0 15 0 | B1->B0 | 3434 3131 | 0 0 | (0 0) (1 1)
2897 23:31:38.367522 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2898 23:31:38.370892 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2899 23:31:38.374287 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2900 23:31:38.381073 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2901 23:31:38.384266 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2902 23:31:38.387865 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2903 23:31:38.394346 0 15 28 | B1->B0 | 3131 3131 | 0 0 | (0 0) (0 1)
2904 23:31:38.398156 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
2905 23:31:38.401801 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2906 23:31:38.407995 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2907 23:31:38.411488 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2908 23:31:38.415073 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2909 23:31:38.421375 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2910 23:31:38.424967 1 0 24 | B1->B0 | 2828 2424 | 0 0 | (0 0) (0 0)
2911 23:31:38.428273 1 0 28 | B1->B0 | 3838 3333 | 0 1 | (0 0) (1 1)
2912 23:31:38.431419 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2913 23:31:38.438387 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2914 23:31:38.441314 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2915 23:31:38.444514 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2916 23:31:38.452005 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2917 23:31:38.454870 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2918 23:31:38.458202 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2919 23:31:38.464969 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2920 23:31:38.467898 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2921 23:31:38.471363 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2922 23:31:38.477900 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2923 23:31:38.481333 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2924 23:31:38.484721 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2925 23:31:38.491369 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2926 23:31:38.494710 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2927 23:31:38.498359 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2928 23:31:38.504898 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2929 23:31:38.508599 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2930 23:31:38.511641 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2931 23:31:38.518678 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2932 23:31:38.521999 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2933 23:31:38.525014 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2934 23:31:38.528143 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2935 23:31:38.535268 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2936 23:31:38.537939 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2937 23:31:38.541548 Total UI for P1: 0, mck2ui 16
2938 23:31:38.545016 best dqsien dly found for B0: ( 1, 3, 26)
2939 23:31:38.548523 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2940 23:31:38.551807 Total UI for P1: 0, mck2ui 16
2941 23:31:38.555091 best dqsien dly found for B1: ( 1, 3, 28)
2942 23:31:38.558531 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2943 23:31:38.561660 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2944 23:31:38.562130
2945 23:31:38.568366 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2946 23:31:38.571393 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2947 23:31:38.571898 [Gating] SW calibration Done
2948 23:31:38.575939 ==
2949 23:31:38.578028 Dram Type= 6, Freq= 0, CH_0, rank 1
2950 23:31:38.581622 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2951 23:31:38.582193 ==
2952 23:31:38.582562 RX Vref Scan: 0
2953 23:31:38.582904
2954 23:31:38.584804 RX Vref 0 -> 0, step: 1
2955 23:31:38.585274
2956 23:31:38.588641 RX Delay -40 -> 252, step: 8
2957 23:31:38.591514 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2958 23:31:38.594964 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2959 23:31:38.598378 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2960 23:31:38.605444 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2961 23:31:38.608623 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2962 23:31:38.611691 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2963 23:31:38.615344 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2964 23:31:38.618283 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2965 23:31:38.624982 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
2966 23:31:38.628852 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
2967 23:31:38.631862 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
2968 23:31:38.635475 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2969 23:31:38.638667 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2970 23:31:38.645185 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2971 23:31:38.648497 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2972 23:31:38.651790 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
2973 23:31:38.652353 ==
2974 23:31:38.655418 Dram Type= 6, Freq= 0, CH_0, rank 1
2975 23:31:38.658250 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2976 23:31:38.658710 ==
2977 23:31:38.661901 DQS Delay:
2978 23:31:38.662425 DQS0 = 0, DQS1 = 0
2979 23:31:38.665339 DQM Delay:
2980 23:31:38.665993 DQM0 = 121, DQM1 = 113
2981 23:31:38.666368 DQ Delay:
2982 23:31:38.671829 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =119
2983 23:31:38.675377 DQ4 =127, DQ5 =115, DQ6 =127, DQ7 =127
2984 23:31:38.678525 DQ8 =103, DQ9 =99, DQ10 =115, DQ11 =107
2985 23:31:38.681841 DQ12 =115, DQ13 =123, DQ14 =123, DQ15 =123
2986 23:31:38.682304
2987 23:31:38.682664
2988 23:31:38.683004 ==
2989 23:31:38.685309 Dram Type= 6, Freq= 0, CH_0, rank 1
2990 23:31:38.688623 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2991 23:31:38.689083 ==
2992 23:31:38.689451
2993 23:31:38.689923
2994 23:31:38.692211 TX Vref Scan disable
2995 23:31:38.694979 == TX Byte 0 ==
2996 23:31:38.698458 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
2997 23:31:38.701727 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
2998 23:31:38.705569 == TX Byte 1 ==
2999 23:31:38.708607 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3000 23:31:38.712025 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3001 23:31:38.712445 ==
3002 23:31:38.715843 Dram Type= 6, Freq= 0, CH_0, rank 1
3003 23:31:38.719064 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3004 23:31:38.719527 ==
3005 23:31:38.732209 TX Vref=22, minBit 3, minWin=25, winSum=420
3006 23:31:38.735582 TX Vref=24, minBit 1, minWin=24, winSum=423
3007 23:31:38.738775 TX Vref=26, minBit 0, minWin=26, winSum=427
3008 23:31:38.742286 TX Vref=28, minBit 0, minWin=26, winSum=431
3009 23:31:38.745651 TX Vref=30, minBit 5, minWin=25, winSum=430
3010 23:31:38.749134 TX Vref=32, minBit 5, minWin=25, winSum=427
3011 23:31:38.755437 [TxChooseVref] Worse bit 0, Min win 26, Win sum 431, Final Vref 28
3012 23:31:38.755897
3013 23:31:38.759210 Final TX Range 1 Vref 28
3014 23:31:38.759774
3015 23:31:38.760131 ==
3016 23:31:38.762277 Dram Type= 6, Freq= 0, CH_0, rank 1
3017 23:31:38.765720 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3018 23:31:38.766186 ==
3019 23:31:38.766548
3020 23:31:38.766884
3021 23:31:38.769072 TX Vref Scan disable
3022 23:31:38.772753 == TX Byte 0 ==
3023 23:31:38.775963 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
3024 23:31:38.779369 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
3025 23:31:38.782437 == TX Byte 1 ==
3026 23:31:38.785904 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3027 23:31:38.788923 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3028 23:31:38.789490
3029 23:31:38.792274 [DATLAT]
3030 23:31:38.792726 Freq=1200, CH0 RK1
3031 23:31:38.793048
3032 23:31:38.795669 DATLAT Default: 0xd
3033 23:31:38.796182 0, 0xFFFF, sum = 0
3034 23:31:38.798790 1, 0xFFFF, sum = 0
3035 23:31:38.799208 2, 0xFFFF, sum = 0
3036 23:31:38.802736 3, 0xFFFF, sum = 0
3037 23:31:38.803260 4, 0xFFFF, sum = 0
3038 23:31:38.805753 5, 0xFFFF, sum = 0
3039 23:31:38.806270 6, 0xFFFF, sum = 0
3040 23:31:38.809224 7, 0xFFFF, sum = 0
3041 23:31:38.809799 8, 0xFFFF, sum = 0
3042 23:31:38.812664 9, 0xFFFF, sum = 0
3043 23:31:38.813084 10, 0xFFFF, sum = 0
3044 23:31:38.815600 11, 0xFFFF, sum = 0
3045 23:31:38.816018 12, 0x0, sum = 1
3046 23:31:38.819428 13, 0x0, sum = 2
3047 23:31:38.819850 14, 0x0, sum = 3
3048 23:31:38.822463 15, 0x0, sum = 4
3049 23:31:38.822884 best_step = 13
3050 23:31:38.823213
3051 23:31:38.825390 ==
3052 23:31:38.825840 Dram Type= 6, Freq= 0, CH_0, rank 1
3053 23:31:38.832074 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3054 23:31:38.832536 ==
3055 23:31:38.832866 RX Vref Scan: 0
3056 23:31:38.833169
3057 23:31:38.835364 RX Vref 0 -> 0, step: 1
3058 23:31:38.835775
3059 23:31:38.838674 RX Delay -13 -> 252, step: 4
3060 23:31:38.842456 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3061 23:31:38.845378 iDelay=195, Bit 1, Center 120 (55 ~ 186) 132
3062 23:31:38.852479 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3063 23:31:38.855927 iDelay=195, Bit 3, Center 118 (51 ~ 186) 136
3064 23:31:38.858711 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3065 23:31:38.862136 iDelay=195, Bit 5, Center 116 (51 ~ 182) 132
3066 23:31:38.865703 iDelay=195, Bit 6, Center 128 (63 ~ 194) 132
3067 23:31:38.872291 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3068 23:31:38.875700 iDelay=195, Bit 8, Center 100 (35 ~ 166) 132
3069 23:31:38.879005 iDelay=195, Bit 9, Center 100 (35 ~ 166) 132
3070 23:31:38.882319 iDelay=195, Bit 10, Center 112 (47 ~ 178) 132
3071 23:31:38.885530 iDelay=195, Bit 11, Center 104 (39 ~ 170) 132
3072 23:31:38.892147 iDelay=195, Bit 12, Center 118 (55 ~ 182) 128
3073 23:31:38.895692 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3074 23:31:38.898898 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3075 23:31:38.902236 iDelay=195, Bit 15, Center 118 (55 ~ 182) 128
3076 23:31:38.902695 ==
3077 23:31:38.906150 Dram Type= 6, Freq= 0, CH_0, rank 1
3078 23:31:38.912198 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3079 23:31:38.912741 ==
3080 23:31:38.913075 DQS Delay:
3081 23:31:38.913451 DQS0 = 0, DQS1 = 0
3082 23:31:38.915836 DQM Delay:
3083 23:31:38.916351 DQM0 = 120, DQM1 = 111
3084 23:31:38.919037 DQ Delay:
3085 23:31:38.922518 DQ0 =118, DQ1 =120, DQ2 =118, DQ3 =118
3086 23:31:38.925806 DQ4 =122, DQ5 =116, DQ6 =128, DQ7 =126
3087 23:31:38.928792 DQ8 =100, DQ9 =100, DQ10 =112, DQ11 =104
3088 23:31:38.932201 DQ12 =118, DQ13 =118, DQ14 =122, DQ15 =118
3089 23:31:38.932660
3090 23:31:38.933040
3091 23:31:38.939026 [DQSOSCAuto] RK1, (LSB)MR18= 0x10f0, (MSB)MR19= 0x403, tDQSOscB0 = 416 ps tDQSOscB1 = 403 ps
3092 23:31:38.942612 CH0 RK1: MR19=403, MR18=10F0
3093 23:31:38.949534 CH0_RK1: MR19=0x403, MR18=0x10F0, DQSOSC=403, MR23=63, INC=40, DEC=26
3094 23:31:38.952868 [RxdqsGatingPostProcess] freq 1200
3095 23:31:38.959407 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3096 23:31:38.962254 best DQS0 dly(2T, 0.5T) = (0, 11)
3097 23:31:38.965803 best DQS1 dly(2T, 0.5T) = (0, 11)
3098 23:31:38.969363 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3099 23:31:38.969995 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3100 23:31:38.972532 best DQS0 dly(2T, 0.5T) = (0, 11)
3101 23:31:38.976173 best DQS1 dly(2T, 0.5T) = (0, 11)
3102 23:31:38.979651 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3103 23:31:38.982916 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3104 23:31:38.985974 Pre-setting of DQS Precalculation
3105 23:31:38.992206 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3106 23:31:38.992753 ==
3107 23:31:38.996137 Dram Type= 6, Freq= 0, CH_1, rank 0
3108 23:31:38.999014 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3109 23:31:38.999478 ==
3110 23:31:39.006249 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3111 23:31:39.009047 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3112 23:31:39.019073 [CA 0] Center 37 (7~68) winsize 62
3113 23:31:39.022338 [CA 1] Center 37 (7~68) winsize 62
3114 23:31:39.025691 [CA 2] Center 34 (4~65) winsize 62
3115 23:31:39.029083 [CA 3] Center 34 (4~64) winsize 61
3116 23:31:39.031923 [CA 4] Center 34 (4~64) winsize 61
3117 23:31:39.035719 [CA 5] Center 33 (4~63) winsize 60
3118 23:31:39.036177
3119 23:31:39.039058 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3120 23:31:39.039512
3121 23:31:39.042096 [CATrainingPosCal] consider 1 rank data
3122 23:31:39.045633 u2DelayCellTimex100 = 270/100 ps
3123 23:31:39.048849 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3124 23:31:39.052724 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3125 23:31:39.059527 CA2 delay=34 (4~65),Diff = 1 PI (4 cell)
3126 23:31:39.062314 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3127 23:31:39.065993 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3128 23:31:39.068898 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3129 23:31:39.069457
3130 23:31:39.072294 CA PerBit enable=1, Macro0, CA PI delay=33
3131 23:31:39.072850
3132 23:31:39.075805 [CBTSetCACLKResult] CA Dly = 33
3133 23:31:39.076366 CS Dly: 8 (0~39)
3134 23:31:39.076795 ==
3135 23:31:39.078867 Dram Type= 6, Freq= 0, CH_1, rank 1
3136 23:31:39.085759 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3137 23:31:39.086221 ==
3138 23:31:39.089108 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3139 23:31:39.095542 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3140 23:31:39.104544 [CA 0] Center 37 (7~68) winsize 62
3141 23:31:39.108030 [CA 1] Center 38 (7~69) winsize 63
3142 23:31:39.111772 [CA 2] Center 35 (5~65) winsize 61
3143 23:31:39.114427 [CA 3] Center 34 (4~65) winsize 62
3144 23:31:39.117710 [CA 4] Center 34 (4~65) winsize 62
3145 23:31:39.121280 [CA 5] Center 34 (4~64) winsize 61
3146 23:31:39.121778
3147 23:31:39.124592 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3148 23:31:39.125153
3149 23:31:39.128131 [CATrainingPosCal] consider 2 rank data
3150 23:31:39.131471 u2DelayCellTimex100 = 270/100 ps
3151 23:31:39.134336 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3152 23:31:39.137775 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3153 23:31:39.144304 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3154 23:31:39.148659 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3155 23:31:39.151353 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3156 23:31:39.154702 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3157 23:31:39.155159
3158 23:31:39.158229 CA PerBit enable=1, Macro0, CA PI delay=33
3159 23:31:39.158800
3160 23:31:39.161708 [CBTSetCACLKResult] CA Dly = 33
3161 23:31:39.162264 CS Dly: 8 (0~40)
3162 23:31:39.162634
3163 23:31:39.165453 ----->DramcWriteLeveling(PI) begin...
3164 23:31:39.166152 ==
3165 23:31:39.167889 Dram Type= 6, Freq= 0, CH_1, rank 0
3166 23:31:39.174859 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3167 23:31:39.175458 ==
3168 23:31:39.178138 Write leveling (Byte 0): 26 => 26
3169 23:31:39.181278 Write leveling (Byte 1): 28 => 28
3170 23:31:39.181940 DramcWriteLeveling(PI) end<-----
3171 23:31:39.184925
3172 23:31:39.185495 ==
3173 23:31:39.188322 Dram Type= 6, Freq= 0, CH_1, rank 0
3174 23:31:39.191297 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3175 23:31:39.191762 ==
3176 23:31:39.194367 [Gating] SW mode calibration
3177 23:31:39.201525 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3178 23:31:39.204612 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3179 23:31:39.211441 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3180 23:31:39.214384 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3181 23:31:39.217625 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3182 23:31:39.224803 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3183 23:31:39.228310 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3184 23:31:39.231390 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3185 23:31:39.238547 0 15 24 | B1->B0 | 3232 2a2a | 1 0 | (1 0) (0 1)
3186 23:31:39.241146 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3187 23:31:39.244742 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3188 23:31:39.251153 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3189 23:31:39.254797 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3190 23:31:39.258123 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3191 23:31:39.264955 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3192 23:31:39.268497 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3193 23:31:39.271315 1 0 24 | B1->B0 | 3030 4141 | 1 0 | (0 0) (0 0)
3194 23:31:39.275180 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3195 23:31:39.281892 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3196 23:31:39.284690 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3197 23:31:39.288452 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3198 23:31:39.294972 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3199 23:31:39.297934 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3200 23:31:39.301445 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3201 23:31:39.308389 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3202 23:31:39.311269 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3203 23:31:39.314607 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3204 23:31:39.321684 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3205 23:31:39.324888 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3206 23:31:39.328671 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3207 23:31:39.335039 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3208 23:31:39.338267 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3209 23:31:39.341401 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3210 23:31:39.344854 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3211 23:31:39.351621 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3212 23:31:39.355061 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3213 23:31:39.358340 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3214 23:31:39.364859 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3215 23:31:39.368220 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3216 23:31:39.371374 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3217 23:31:39.378377 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3218 23:31:39.381483 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3219 23:31:39.385365 Total UI for P1: 0, mck2ui 16
3220 23:31:39.388429 best dqsien dly found for B1: ( 1, 3, 24)
3221 23:31:39.391998 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3222 23:31:39.395014 Total UI for P1: 0, mck2ui 16
3223 23:31:39.398624 best dqsien dly found for B0: ( 1, 3, 26)
3224 23:31:39.401999 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3225 23:31:39.405103 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3226 23:31:39.405734
3227 23:31:39.411416 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3228 23:31:39.414890 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3229 23:31:39.415350 [Gating] SW calibration Done
3230 23:31:39.418070 ==
3231 23:31:39.421703 Dram Type= 6, Freq= 0, CH_1, rank 0
3232 23:31:39.424810 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3233 23:31:39.425395 ==
3234 23:31:39.425809 RX Vref Scan: 0
3235 23:31:39.426153
3236 23:31:39.427997 RX Vref 0 -> 0, step: 1
3237 23:31:39.428452
3238 23:31:39.431527 RX Delay -40 -> 252, step: 8
3239 23:31:39.435114 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3240 23:31:39.438466 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3241 23:31:39.441900 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3242 23:31:39.448673 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3243 23:31:39.451897 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3244 23:31:39.455435 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3245 23:31:39.458561 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3246 23:31:39.461706 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3247 23:31:39.468572 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3248 23:31:39.471780 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3249 23:31:39.475054 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3250 23:31:39.478722 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3251 23:31:39.482035 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3252 23:31:39.488566 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3253 23:31:39.492171 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3254 23:31:39.495363 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3255 23:31:39.495825 ==
3256 23:31:39.498735 Dram Type= 6, Freq= 0, CH_1, rank 0
3257 23:31:39.502053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3258 23:31:39.502512 ==
3259 23:31:39.505783 DQS Delay:
3260 23:31:39.506343 DQS0 = 0, DQS1 = 0
3261 23:31:39.506713 DQM Delay:
3262 23:31:39.508827 DQM0 = 119, DQM1 = 116
3263 23:31:39.509383 DQ Delay:
3264 23:31:39.512002 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3265 23:31:39.515385 DQ4 =119, DQ5 =127, DQ6 =127, DQ7 =119
3266 23:31:39.521856 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =111
3267 23:31:39.525361 DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123
3268 23:31:39.525967
3269 23:31:39.526335
3270 23:31:39.526671 ==
3271 23:31:39.528774 Dram Type= 6, Freq= 0, CH_1, rank 0
3272 23:31:39.531815 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3273 23:31:39.532384 ==
3274 23:31:39.532754
3275 23:31:39.533107
3276 23:31:39.535294 TX Vref Scan disable
3277 23:31:39.535858 == TX Byte 0 ==
3278 23:31:39.542042 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3279 23:31:39.545164 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3280 23:31:39.545659 == TX Byte 1 ==
3281 23:31:39.552836 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3282 23:31:39.555310 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3283 23:31:39.555931 ==
3284 23:31:39.558519 Dram Type= 6, Freq= 0, CH_1, rank 0
3285 23:31:39.561641 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3286 23:31:39.562107 ==
3287 23:31:39.574722 TX Vref=22, minBit 9, minWin=24, winSum=410
3288 23:31:39.578444 TX Vref=24, minBit 9, minWin=24, winSum=416
3289 23:31:39.581739 TX Vref=26, minBit 9, minWin=24, winSum=421
3290 23:31:39.584917 TX Vref=28, minBit 2, minWin=26, winSum=429
3291 23:31:39.587981 TX Vref=30, minBit 2, minWin=26, winSum=427
3292 23:31:39.591521 TX Vref=32, minBit 10, minWin=25, winSum=433
3293 23:31:39.598576 [TxChooseVref] Worse bit 2, Min win 26, Win sum 429, Final Vref 28
3294 23:31:39.599144
3295 23:31:39.601770 Final TX Range 1 Vref 28
3296 23:31:39.602328
3297 23:31:39.602693 ==
3298 23:31:39.604779 Dram Type= 6, Freq= 0, CH_1, rank 0
3299 23:31:39.610422 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3300 23:31:39.610889 ==
3301 23:31:39.611255
3302 23:31:39.611942
3303 23:31:39.612302 TX Vref Scan disable
3304 23:31:39.614597 == TX Byte 0 ==
3305 23:31:39.618566 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3306 23:31:39.621382 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3307 23:31:39.625219 == TX Byte 1 ==
3308 23:31:39.628291 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3309 23:31:39.631775 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3310 23:31:39.632357
3311 23:31:39.635128 [DATLAT]
3312 23:31:39.635685 Freq=1200, CH1 RK0
3313 23:31:39.636056
3314 23:31:39.638430 DATLAT Default: 0xd
3315 23:31:39.638984 0, 0xFFFF, sum = 0
3316 23:31:39.641410 1, 0xFFFF, sum = 0
3317 23:31:39.641956 2, 0xFFFF, sum = 0
3318 23:31:39.644883 3, 0xFFFF, sum = 0
3319 23:31:39.645343 4, 0xFFFF, sum = 0
3320 23:31:39.648287 5, 0xFFFF, sum = 0
3321 23:31:39.648751 6, 0xFFFF, sum = 0
3322 23:31:39.651729 7, 0xFFFF, sum = 0
3323 23:31:39.652301 8, 0xFFFF, sum = 0
3324 23:31:39.654726 9, 0xFFFF, sum = 0
3325 23:31:39.655188 10, 0xFFFF, sum = 0
3326 23:31:39.658338 11, 0xFFFF, sum = 0
3327 23:31:39.658802 12, 0x0, sum = 1
3328 23:31:39.661720 13, 0x0, sum = 2
3329 23:31:39.662184 14, 0x0, sum = 3
3330 23:31:39.665018 15, 0x0, sum = 4
3331 23:31:39.665481 best_step = 13
3332 23:31:39.665901
3333 23:31:39.666250 ==
3334 23:31:39.668231 Dram Type= 6, Freq= 0, CH_1, rank 0
3335 23:31:39.674909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3336 23:31:39.675356 ==
3337 23:31:39.675685 RX Vref Scan: 1
3338 23:31:39.675992
3339 23:31:39.678092 Set Vref Range= 32 -> 127
3340 23:31:39.678503
3341 23:31:39.681785 RX Vref 32 -> 127, step: 1
3342 23:31:39.682305
3343 23:31:39.685006 RX Delay -5 -> 252, step: 4
3344 23:31:39.685519
3345 23:31:39.685904 Set Vref, RX VrefLevel [Byte0]: 32
3346 23:31:39.688339 [Byte1]: 32
3347 23:31:39.692820
3348 23:31:39.693233 Set Vref, RX VrefLevel [Byte0]: 33
3349 23:31:39.696569 [Byte1]: 33
3350 23:31:39.700803
3351 23:31:39.701330 Set Vref, RX VrefLevel [Byte0]: 34
3352 23:31:39.704048 [Byte1]: 34
3353 23:31:39.708731
3354 23:31:39.709250 Set Vref, RX VrefLevel [Byte0]: 35
3355 23:31:39.711702 [Byte1]: 35
3356 23:31:39.716443
3357 23:31:39.716959 Set Vref, RX VrefLevel [Byte0]: 36
3358 23:31:39.719699 [Byte1]: 36
3359 23:31:39.724604
3360 23:31:39.725057 Set Vref, RX VrefLevel [Byte0]: 37
3361 23:31:39.727614 [Byte1]: 37
3362 23:31:39.732134
3363 23:31:39.732587 Set Vref, RX VrefLevel [Byte0]: 38
3364 23:31:39.735201 [Byte1]: 38
3365 23:31:39.739710
3366 23:31:39.740141 Set Vref, RX VrefLevel [Byte0]: 39
3367 23:31:39.743027 [Byte1]: 39
3368 23:31:39.748033
3369 23:31:39.748544 Set Vref, RX VrefLevel [Byte0]: 40
3370 23:31:39.751474 [Byte1]: 40
3371 23:31:39.755890
3372 23:31:39.756406 Set Vref, RX VrefLevel [Byte0]: 41
3373 23:31:39.759330 [Byte1]: 41
3374 23:31:39.764110
3375 23:31:39.764623 Set Vref, RX VrefLevel [Byte0]: 42
3376 23:31:39.767079 [Byte1]: 42
3377 23:31:39.771865
3378 23:31:39.772366 Set Vref, RX VrefLevel [Byte0]: 43
3379 23:31:39.774818 [Byte1]: 43
3380 23:31:39.779060
3381 23:31:39.779469 Set Vref, RX VrefLevel [Byte0]: 44
3382 23:31:39.782894 [Byte1]: 44
3383 23:31:39.787288
3384 23:31:39.787716 Set Vref, RX VrefLevel [Byte0]: 45
3385 23:31:39.790172 [Byte1]: 45
3386 23:31:39.794785
3387 23:31:39.795243 Set Vref, RX VrefLevel [Byte0]: 46
3388 23:31:39.798335 [Byte1]: 46
3389 23:31:39.803140
3390 23:31:39.803654 Set Vref, RX VrefLevel [Byte0]: 47
3391 23:31:39.806420 [Byte1]: 47
3392 23:31:39.810406
3393 23:31:39.810872 Set Vref, RX VrefLevel [Byte0]: 48
3394 23:31:39.813686 [Byte1]: 48
3395 23:31:39.818822
3396 23:31:39.819333 Set Vref, RX VrefLevel [Byte0]: 49
3397 23:31:39.822329 [Byte1]: 49
3398 23:31:39.826415
3399 23:31:39.826825 Set Vref, RX VrefLevel [Byte0]: 50
3400 23:31:39.829624 [Byte1]: 50
3401 23:31:39.834466
3402 23:31:39.835013 Set Vref, RX VrefLevel [Byte0]: 51
3403 23:31:39.837750 [Byte1]: 51
3404 23:31:39.842334
3405 23:31:39.842786 Set Vref, RX VrefLevel [Byte0]: 52
3406 23:31:39.845005 [Byte1]: 52
3407 23:31:39.850247
3408 23:31:39.850816 Set Vref, RX VrefLevel [Byte0]: 53
3409 23:31:39.853518 [Byte1]: 53
3410 23:31:39.858032
3411 23:31:39.858583 Set Vref, RX VrefLevel [Byte0]: 54
3412 23:31:39.860921 [Byte1]: 54
3413 23:31:39.865745
3414 23:31:39.866295 Set Vref, RX VrefLevel [Byte0]: 55
3415 23:31:39.869078 [Byte1]: 55
3416 23:31:39.873529
3417 23:31:39.874132 Set Vref, RX VrefLevel [Byte0]: 56
3418 23:31:39.876641 [Byte1]: 56
3419 23:31:39.881046
3420 23:31:39.881500 Set Vref, RX VrefLevel [Byte0]: 57
3421 23:31:39.884675 [Byte1]: 57
3422 23:31:39.889209
3423 23:31:39.889699 Set Vref, RX VrefLevel [Byte0]: 58
3424 23:31:39.892407 [Byte1]: 58
3425 23:31:39.897412
3426 23:31:39.898011 Set Vref, RX VrefLevel [Byte0]: 59
3427 23:31:39.900030 [Byte1]: 59
3428 23:31:39.904826
3429 23:31:39.905385 Set Vref, RX VrefLevel [Byte0]: 60
3430 23:31:39.908133 [Byte1]: 60
3431 23:31:39.912639
3432 23:31:39.913095 Set Vref, RX VrefLevel [Byte0]: 61
3433 23:31:39.915971 [Byte1]: 61
3434 23:31:39.920885
3435 23:31:39.921440 Set Vref, RX VrefLevel [Byte0]: 62
3436 23:31:39.924235 [Byte1]: 62
3437 23:31:39.928290
3438 23:31:39.928746 Set Vref, RX VrefLevel [Byte0]: 63
3439 23:31:39.931994 [Byte1]: 63
3440 23:31:39.936395
3441 23:31:39.936947 Set Vref, RX VrefLevel [Byte0]: 64
3442 23:31:39.939326 [Byte1]: 64
3443 23:31:39.944163
3444 23:31:39.944714 Set Vref, RX VrefLevel [Byte0]: 65
3445 23:31:39.947301 [Byte1]: 65
3446 23:31:39.951956
3447 23:31:39.952425 Set Vref, RX VrefLevel [Byte0]: 66
3448 23:31:39.955517 [Byte1]: 66
3449 23:31:39.960238
3450 23:31:39.960794 Set Vref, RX VrefLevel [Byte0]: 67
3451 23:31:39.963194 [Byte1]: 67
3452 23:31:39.968023
3453 23:31:39.968666 Final RX Vref Byte 0 = 55 to rank0
3454 23:31:39.971021 Final RX Vref Byte 1 = 52 to rank0
3455 23:31:39.974583 Final RX Vref Byte 0 = 55 to rank1
3456 23:31:39.978006 Final RX Vref Byte 1 = 52 to rank1==
3457 23:31:39.981203 Dram Type= 6, Freq= 0, CH_1, rank 0
3458 23:31:39.987828 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3459 23:31:39.988380 ==
3460 23:31:39.988748 DQS Delay:
3461 23:31:39.989088 DQS0 = 0, DQS1 = 0
3462 23:31:39.991238 DQM Delay:
3463 23:31:39.991798 DQM0 = 120, DQM1 = 117
3464 23:31:39.994461 DQ Delay:
3465 23:31:39.997758 DQ0 =124, DQ1 =114, DQ2 =112, DQ3 =118
3466 23:31:40.001560 DQ4 =120, DQ5 =128, DQ6 =128, DQ7 =120
3467 23:31:40.004952 DQ8 =104, DQ9 =106, DQ10 =118, DQ11 =112
3468 23:31:40.008481 DQ12 =124, DQ13 =124, DQ14 =124, DQ15 =126
3469 23:31:40.009039
3470 23:31:40.009407
3471 23:31:40.014572 [DQSOSCAuto] RK0, (LSB)MR18= 0xfe11, (MSB)MR19= 0x304, tDQSOscB0 = 403 ps tDQSOscB1 = 410 ps
3472 23:31:40.017770 CH1 RK0: MR19=304, MR18=FE11
3473 23:31:40.024721 CH1_RK0: MR19=0x304, MR18=0xFE11, DQSOSC=403, MR23=63, INC=40, DEC=26
3474 23:31:40.025264
3475 23:31:40.027859 ----->DramcWriteLeveling(PI) begin...
3476 23:31:40.028323 ==
3477 23:31:40.031125 Dram Type= 6, Freq= 0, CH_1, rank 1
3478 23:31:40.034791 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3479 23:31:40.035262 ==
3480 23:31:40.037974 Write leveling (Byte 0): 25 => 25
3481 23:31:40.040992 Write leveling (Byte 1): 27 => 27
3482 23:31:40.044287 DramcWriteLeveling(PI) end<-----
3483 23:31:40.044749
3484 23:31:40.045111 ==
3485 23:31:40.048399 Dram Type= 6, Freq= 0, CH_1, rank 1
3486 23:31:40.054421 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3487 23:31:40.054885 ==
3488 23:31:40.055246 [Gating] SW mode calibration
3489 23:31:40.064807 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3490 23:31:40.068297 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3491 23:31:40.070827 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3492 23:31:40.077897 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3493 23:31:40.081095 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3494 23:31:40.084685 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3495 23:31:40.091236 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3496 23:31:40.094661 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
3497 23:31:40.098120 0 15 24 | B1->B0 | 2b2b 3333 | 1 1 | (1 0) (1 1)
3498 23:31:40.104674 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3499 23:31:40.108144 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3500 23:31:40.111530 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3501 23:31:40.118608 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3502 23:31:40.122202 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3503 23:31:40.125260 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3504 23:31:40.131134 1 0 20 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
3505 23:31:40.134480 1 0 24 | B1->B0 | 4343 2b2b | 0 0 | (0 0) (0 0)
3506 23:31:40.138004 1 0 28 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
3507 23:31:40.141380 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3508 23:31:40.147979 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3509 23:31:40.151402 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3510 23:31:40.154413 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3511 23:31:40.161398 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3512 23:31:40.164768 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3513 23:31:40.167835 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3514 23:31:40.174353 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3515 23:31:40.177940 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3516 23:31:40.181239 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3517 23:31:40.187841 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3518 23:31:40.190920 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3519 23:31:40.194302 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3520 23:31:40.200883 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3521 23:31:40.204692 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3522 23:31:40.208041 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3523 23:31:40.214206 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3524 23:31:40.218062 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3525 23:31:40.221377 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3526 23:31:40.227202 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3527 23:31:40.230691 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3528 23:31:40.234062 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3529 23:31:40.240897 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3530 23:31:40.241458 Total UI for P1: 0, mck2ui 16
3531 23:31:40.247136 best dqsien dly found for B1: ( 1, 3, 20)
3532 23:31:40.250449 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3533 23:31:40.254083 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3534 23:31:40.257301 Total UI for P1: 0, mck2ui 16
3535 23:31:40.260471 best dqsien dly found for B0: ( 1, 3, 26)
3536 23:31:40.263927 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3537 23:31:40.267485 best DQS1 dly(MCK, UI, PI) = (1, 3, 20)
3538 23:31:40.267943
3539 23:31:40.273922 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3540 23:31:40.277286 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 20)
3541 23:31:40.277761 [Gating] SW calibration Done
3542 23:31:40.280629 ==
3543 23:31:40.284123 Dram Type= 6, Freq= 0, CH_1, rank 1
3544 23:31:40.287366 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3545 23:31:40.287785 ==
3546 23:31:40.288127 RX Vref Scan: 0
3547 23:31:40.288498
3548 23:31:40.290655 RX Vref 0 -> 0, step: 1
3549 23:31:40.291068
3550 23:31:40.293909 RX Delay -40 -> 252, step: 8
3551 23:31:40.297140 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3552 23:31:40.300670 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3553 23:31:40.304303 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3554 23:31:40.310541 iDelay=200, Bit 3, Center 119 (56 ~ 183) 128
3555 23:31:40.314177 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3556 23:31:40.316912 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3557 23:31:40.320736 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3558 23:31:40.323958 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
3559 23:31:40.330735 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3560 23:31:40.334344 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3561 23:31:40.337088 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3562 23:31:40.340493 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3563 23:31:40.343565 iDelay=200, Bit 12, Center 127 (56 ~ 199) 144
3564 23:31:40.350652 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3565 23:31:40.353737 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3566 23:31:40.357446 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3567 23:31:40.358021 ==
3568 23:31:40.360292 Dram Type= 6, Freq= 0, CH_1, rank 1
3569 23:31:40.363606 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3570 23:31:40.366869 ==
3571 23:31:40.367282 DQS Delay:
3572 23:31:40.367610 DQS0 = 0, DQS1 = 0
3573 23:31:40.370312 DQM Delay:
3574 23:31:40.370728 DQM0 = 120, DQM1 = 117
3575 23:31:40.373407 DQ Delay:
3576 23:31:40.377331 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3577 23:31:40.380675 DQ4 =115, DQ5 =131, DQ6 =131, DQ7 =123
3578 23:31:40.384153 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =111
3579 23:31:40.386896 DQ12 =127, DQ13 =127, DQ14 =123, DQ15 =123
3580 23:31:40.387416
3581 23:31:40.387747
3582 23:31:40.388053 ==
3583 23:31:40.390118 Dram Type= 6, Freq= 0, CH_1, rank 1
3584 23:31:40.393745 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3585 23:31:40.394261 ==
3586 23:31:40.394594
3587 23:31:40.396750
3588 23:31:40.397197 TX Vref Scan disable
3589 23:31:40.400485 == TX Byte 0 ==
3590 23:31:40.403686 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3591 23:31:40.406961 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3592 23:31:40.410510 == TX Byte 1 ==
3593 23:31:40.413119 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3594 23:31:40.416725 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3595 23:31:40.417285 ==
3596 23:31:40.419934 Dram Type= 6, Freq= 0, CH_1, rank 1
3597 23:31:40.426770 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3598 23:31:40.427188 ==
3599 23:31:40.437055 TX Vref=22, minBit 10, minWin=25, winSum=420
3600 23:31:40.440484 TX Vref=24, minBit 1, minWin=26, winSum=426
3601 23:31:40.443845 TX Vref=26, minBit 8, minWin=26, winSum=429
3602 23:31:40.447464 TX Vref=28, minBit 9, minWin=26, winSum=432
3603 23:31:40.450128 TX Vref=30, minBit 9, minWin=26, winSum=433
3604 23:31:40.457685 TX Vref=32, minBit 9, minWin=26, winSum=432
3605 23:31:40.460413 [TxChooseVref] Worse bit 9, Min win 26, Win sum 433, Final Vref 30
3606 23:31:40.460935
3607 23:31:40.464320 Final TX Range 1 Vref 30
3608 23:31:40.464842
3609 23:31:40.465172 ==
3610 23:31:40.466784 Dram Type= 6, Freq= 0, CH_1, rank 1
3611 23:31:40.470460 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3612 23:31:40.470876 ==
3613 23:31:40.473429
3614 23:31:40.473885
3615 23:31:40.474214 TX Vref Scan disable
3616 23:31:40.477138 == TX Byte 0 ==
3617 23:31:40.480237 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3618 23:31:40.483778 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3619 23:31:40.487150 == TX Byte 1 ==
3620 23:31:40.490433 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3621 23:31:40.493819 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3622 23:31:40.494236
3623 23:31:40.496600 [DATLAT]
3624 23:31:40.497046 Freq=1200, CH1 RK1
3625 23:31:40.497392
3626 23:31:40.500619 DATLAT Default: 0xd
3627 23:31:40.501140 0, 0xFFFF, sum = 0
3628 23:31:40.503487 1, 0xFFFF, sum = 0
3629 23:31:40.503908 2, 0xFFFF, sum = 0
3630 23:31:40.507094 3, 0xFFFF, sum = 0
3631 23:31:40.507617 4, 0xFFFF, sum = 0
3632 23:31:40.510259 5, 0xFFFF, sum = 0
3633 23:31:40.513347 6, 0xFFFF, sum = 0
3634 23:31:40.513791 7, 0xFFFF, sum = 0
3635 23:31:40.517405 8, 0xFFFF, sum = 0
3636 23:31:40.517996 9, 0xFFFF, sum = 0
3637 23:31:40.520153 10, 0xFFFF, sum = 0
3638 23:31:40.520676 11, 0xFFFF, sum = 0
3639 23:31:40.523289 12, 0x0, sum = 1
3640 23:31:40.523796 13, 0x0, sum = 2
3641 23:31:40.527054 14, 0x0, sum = 3
3642 23:31:40.527594 15, 0x0, sum = 4
3643 23:31:40.527938 best_step = 13
3644 23:31:40.528243
3645 23:31:40.530187 ==
3646 23:31:40.533730 Dram Type= 6, Freq= 0, CH_1, rank 1
3647 23:31:40.536747 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3648 23:31:40.537269 ==
3649 23:31:40.537644 RX Vref Scan: 0
3650 23:31:40.537973
3651 23:31:40.540522 RX Vref 0 -> 0, step: 1
3652 23:31:40.540934
3653 23:31:40.543594 RX Delay -5 -> 252, step: 4
3654 23:31:40.546990 iDelay=195, Bit 0, Center 122 (59 ~ 186) 128
3655 23:31:40.549868 iDelay=195, Bit 1, Center 116 (55 ~ 178) 124
3656 23:31:40.556856 iDelay=195, Bit 2, Center 110 (51 ~ 170) 120
3657 23:31:40.560107 iDelay=195, Bit 3, Center 116 (59 ~ 174) 116
3658 23:31:40.563306 iDelay=195, Bit 4, Center 116 (55 ~ 178) 124
3659 23:31:40.566638 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3660 23:31:40.570146 iDelay=195, Bit 6, Center 130 (67 ~ 194) 128
3661 23:31:40.576663 iDelay=195, Bit 7, Center 120 (59 ~ 182) 124
3662 23:31:40.580181 iDelay=195, Bit 8, Center 106 (47 ~ 166) 120
3663 23:31:40.583633 iDelay=195, Bit 9, Center 108 (47 ~ 170) 124
3664 23:31:40.587248 iDelay=195, Bit 10, Center 118 (55 ~ 182) 128
3665 23:31:40.590179 iDelay=195, Bit 11, Center 112 (51 ~ 174) 124
3666 23:31:40.597091 iDelay=195, Bit 12, Center 126 (63 ~ 190) 128
3667 23:31:40.600591 iDelay=195, Bit 13, Center 124 (67 ~ 182) 116
3668 23:31:40.603429 iDelay=195, Bit 14, Center 124 (67 ~ 182) 116
3669 23:31:40.606708 iDelay=195, Bit 15, Center 128 (67 ~ 190) 124
3670 23:31:40.607276 ==
3671 23:31:40.610358 Dram Type= 6, Freq= 0, CH_1, rank 1
3672 23:31:40.616788 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3673 23:31:40.617388 ==
3674 23:31:40.617904 DQS Delay:
3675 23:31:40.619900 DQS0 = 0, DQS1 = 0
3676 23:31:40.620354 DQM Delay:
3677 23:31:40.623461 DQM0 = 120, DQM1 = 118
3678 23:31:40.624109 DQ Delay:
3679 23:31:40.626690 DQ0 =122, DQ1 =116, DQ2 =110, DQ3 =116
3680 23:31:40.630431 DQ4 =116, DQ5 =130, DQ6 =130, DQ7 =120
3681 23:31:40.634012 DQ8 =106, DQ9 =108, DQ10 =118, DQ11 =112
3682 23:31:40.636691 DQ12 =126, DQ13 =124, DQ14 =124, DQ15 =128
3683 23:31:40.637150
3684 23:31:40.637508
3685 23:31:40.646646 [DQSOSCAuto] RK1, (LSB)MR18= 0x13f0, (MSB)MR19= 0x403, tDQSOscB0 = 416 ps tDQSOscB1 = 402 ps
3686 23:31:40.647211 CH1 RK1: MR19=403, MR18=13F0
3687 23:31:40.653412 CH1_RK1: MR19=0x403, MR18=0x13F0, DQSOSC=402, MR23=63, INC=40, DEC=27
3688 23:31:40.656657 [RxdqsGatingPostProcess] freq 1200
3689 23:31:40.663121 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3690 23:31:40.666410 best DQS0 dly(2T, 0.5T) = (0, 11)
3691 23:31:40.669904 best DQS1 dly(2T, 0.5T) = (0, 11)
3692 23:31:40.673248 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3693 23:31:40.677210 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3694 23:31:40.680019 best DQS0 dly(2T, 0.5T) = (0, 11)
3695 23:31:40.680580 best DQS1 dly(2T, 0.5T) = (0, 11)
3696 23:31:40.683436 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3697 23:31:40.686784 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3698 23:31:40.689682 Pre-setting of DQS Precalculation
3699 23:31:40.696945 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3700 23:31:40.703264 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3701 23:31:40.709755 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3702 23:31:40.710329
3703 23:31:40.710697
3704 23:31:40.713321 [Calibration Summary] 2400 Mbps
3705 23:31:40.716677 CH 0, Rank 0
3706 23:31:40.717235 SW Impedance : PASS
3707 23:31:40.719938 DUTY Scan : NO K
3708 23:31:40.720504 ZQ Calibration : PASS
3709 23:31:40.723280 Jitter Meter : NO K
3710 23:31:40.726363 CBT Training : PASS
3711 23:31:40.726925 Write leveling : PASS
3712 23:31:40.729640 RX DQS gating : PASS
3713 23:31:40.732748 RX DQ/DQS(RDDQC) : PASS
3714 23:31:40.733206 TX DQ/DQS : PASS
3715 23:31:40.736540 RX DATLAT : PASS
3716 23:31:40.740270 RX DQ/DQS(Engine): PASS
3717 23:31:40.740826 TX OE : NO K
3718 23:31:40.743350 All Pass.
3719 23:31:40.743807
3720 23:31:40.744268 CH 0, Rank 1
3721 23:31:40.746549 SW Impedance : PASS
3722 23:31:40.747006 DUTY Scan : NO K
3723 23:31:40.750058 ZQ Calibration : PASS
3724 23:31:40.753437 Jitter Meter : NO K
3725 23:31:40.754046 CBT Training : PASS
3726 23:31:40.756742 Write leveling : PASS
3727 23:31:40.759587 RX DQS gating : PASS
3728 23:31:40.760045 RX DQ/DQS(RDDQC) : PASS
3729 23:31:40.763096 TX DQ/DQS : PASS
3730 23:31:40.763657 RX DATLAT : PASS
3731 23:31:40.766623 RX DQ/DQS(Engine): PASS
3732 23:31:40.769573 TX OE : NO K
3733 23:31:40.770269 All Pass.
3734 23:31:40.770655
3735 23:31:40.771011 CH 1, Rank 0
3736 23:31:40.772647 SW Impedance : PASS
3737 23:31:40.776624 DUTY Scan : NO K
3738 23:31:40.777184 ZQ Calibration : PASS
3739 23:31:40.779331 Jitter Meter : NO K
3740 23:31:40.782818 CBT Training : PASS
3741 23:31:40.783279 Write leveling : PASS
3742 23:31:40.786071 RX DQS gating : PASS
3743 23:31:40.789183 RX DQ/DQS(RDDQC) : PASS
3744 23:31:40.789688 TX DQ/DQS : PASS
3745 23:31:40.793070 RX DATLAT : PASS
3746 23:31:40.796246 RX DQ/DQS(Engine): PASS
3747 23:31:40.796806 TX OE : NO K
3748 23:31:40.799861 All Pass.
3749 23:31:40.800478
3750 23:31:40.800850 CH 1, Rank 1
3751 23:31:40.802563 SW Impedance : PASS
3752 23:31:40.803059 DUTY Scan : NO K
3753 23:31:40.806204 ZQ Calibration : PASS
3754 23:31:40.809849 Jitter Meter : NO K
3755 23:31:40.810411 CBT Training : PASS
3756 23:31:40.813043 Write leveling : PASS
3757 23:31:40.816165 RX DQS gating : PASS
3758 23:31:40.816625 RX DQ/DQS(RDDQC) : PASS
3759 23:31:40.819381 TX DQ/DQS : PASS
3760 23:31:40.819843 RX DATLAT : PASS
3761 23:31:40.822384 RX DQ/DQS(Engine): PASS
3762 23:31:40.826297 TX OE : NO K
3763 23:31:40.826762 All Pass.
3764 23:31:40.827124
3765 23:31:40.829324 DramC Write-DBI off
3766 23:31:40.829816 PER_BANK_REFRESH: Hybrid Mode
3767 23:31:40.832240 TX_TRACKING: ON
3768 23:31:40.842092 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3769 23:31:40.845351 [FAST_K] Save calibration result to emmc
3770 23:31:40.848750 dramc_set_vcore_voltage set vcore to 650000
3771 23:31:40.851848 Read voltage for 600, 5
3772 23:31:40.852143 Vio18 = 0
3773 23:31:40.852378 Vcore = 650000
3774 23:31:40.855432 Vdram = 0
3775 23:31:40.855654 Vddq = 0
3776 23:31:40.855915 Vmddr = 0
3777 23:31:40.861995 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3778 23:31:40.865129 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3779 23:31:40.868662 MEM_TYPE=3, freq_sel=19
3780 23:31:40.871495 sv_algorithm_assistance_LP4_1600
3781 23:31:40.874919 ============ PULL DRAM RESETB DOWN ============
3782 23:31:40.878353 ========== PULL DRAM RESETB DOWN end =========
3783 23:31:40.884989 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3784 23:31:40.888029 ===================================
3785 23:31:40.888163 LPDDR4 DRAM CONFIGURATION
3786 23:31:40.892150 ===================================
3787 23:31:40.895039 EX_ROW_EN[0] = 0x0
3788 23:31:40.898201 EX_ROW_EN[1] = 0x0
3789 23:31:40.898302 LP4Y_EN = 0x0
3790 23:31:40.901551 WORK_FSP = 0x0
3791 23:31:40.901660 WL = 0x2
3792 23:31:40.904777 RL = 0x2
3793 23:31:40.904877 BL = 0x2
3794 23:31:40.908062 RPST = 0x0
3795 23:31:40.908162 RD_PRE = 0x0
3796 23:31:40.911608 WR_PRE = 0x1
3797 23:31:40.911708 WR_PST = 0x0
3798 23:31:40.914963 DBI_WR = 0x0
3799 23:31:40.915063 DBI_RD = 0x0
3800 23:31:40.918030 OTF = 0x1
3801 23:31:40.921353 ===================================
3802 23:31:40.924560 ===================================
3803 23:31:40.924661 ANA top config
3804 23:31:40.928153 ===================================
3805 23:31:40.931530 DLL_ASYNC_EN = 0
3806 23:31:40.934769 ALL_SLAVE_EN = 1
3807 23:31:40.934940 NEW_RANK_MODE = 1
3808 23:31:40.938021 DLL_IDLE_MODE = 1
3809 23:31:40.941804 LP45_APHY_COMB_EN = 1
3810 23:31:40.944863 TX_ODT_DIS = 1
3811 23:31:40.947881 NEW_8X_MODE = 1
3812 23:31:40.951442 ===================================
3813 23:31:40.954882 ===================================
3814 23:31:40.955094 data_rate = 1200
3815 23:31:40.958146 CKR = 1
3816 23:31:40.961379 DQ_P2S_RATIO = 8
3817 23:31:40.965090 ===================================
3818 23:31:40.968320 CA_P2S_RATIO = 8
3819 23:31:40.971664 DQ_CA_OPEN = 0
3820 23:31:40.975078 DQ_SEMI_OPEN = 0
3821 23:31:40.975738 CA_SEMI_OPEN = 0
3822 23:31:40.978285 CA_FULL_RATE = 0
3823 23:31:40.981267 DQ_CKDIV4_EN = 1
3824 23:31:40.984657 CA_CKDIV4_EN = 1
3825 23:31:40.988028 CA_PREDIV_EN = 0
3826 23:31:40.991430 PH8_DLY = 0
3827 23:31:40.991723 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3828 23:31:40.994454 DQ_AAMCK_DIV = 4
3829 23:31:40.997792 CA_AAMCK_DIV = 4
3830 23:31:41.001276 CA_ADMCK_DIV = 4
3831 23:31:41.004288 DQ_TRACK_CA_EN = 0
3832 23:31:41.007701 CA_PICK = 600
3833 23:31:41.011076 CA_MCKIO = 600
3834 23:31:41.011255 MCKIO_SEMI = 0
3835 23:31:41.014284 PLL_FREQ = 2288
3836 23:31:41.017633 DQ_UI_PI_RATIO = 32
3837 23:31:41.020872 CA_UI_PI_RATIO = 0
3838 23:31:41.024240 ===================================
3839 23:31:41.027782 ===================================
3840 23:31:41.031069 memory_type:LPDDR4
3841 23:31:41.031247 GP_NUM : 10
3842 23:31:41.034238 SRAM_EN : 1
3843 23:31:41.037701 MD32_EN : 0
3844 23:31:41.037879 ===================================
3845 23:31:41.040907 [ANA_INIT] >>>>>>>>>>>>>>
3846 23:31:41.044449 <<<<<< [CONFIGURE PHASE]: ANA_TX
3847 23:31:41.047889 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3848 23:31:41.051266 ===================================
3849 23:31:41.054604 data_rate = 1200,PCW = 0X5800
3850 23:31:41.057777 ===================================
3851 23:31:41.061458 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3852 23:31:41.068628 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3853 23:31:41.071527 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3854 23:31:41.078235 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3855 23:31:41.081704 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3856 23:31:41.085110 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3857 23:31:41.085719 [ANA_INIT] flow start
3858 23:31:41.088650 [ANA_INIT] PLL >>>>>>>>
3859 23:31:41.091284 [ANA_INIT] PLL <<<<<<<<
3860 23:31:41.091848 [ANA_INIT] MIDPI >>>>>>>>
3861 23:31:41.094790 [ANA_INIT] MIDPI <<<<<<<<
3862 23:31:41.098085 [ANA_INIT] DLL >>>>>>>>
3863 23:31:41.098707 [ANA_INIT] flow end
3864 23:31:41.104548 ============ LP4 DIFF to SE enter ============
3865 23:31:41.108247 ============ LP4 DIFF to SE exit ============
3866 23:31:41.111622 [ANA_INIT] <<<<<<<<<<<<<
3867 23:31:41.114897 [Flow] Enable top DCM control >>>>>
3868 23:31:41.118431 [Flow] Enable top DCM control <<<<<
3869 23:31:41.119021 Enable DLL master slave shuffle
3870 23:31:41.124809 ==============================================================
3871 23:31:41.127899 Gating Mode config
3872 23:31:41.131350 ==============================================================
3873 23:31:41.134505 Config description:
3874 23:31:41.144437 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3875 23:31:41.151076 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3876 23:31:41.154565 SELPH_MODE 0: By rank 1: By Phase
3877 23:31:41.160950 ==============================================================
3878 23:31:41.164136 GAT_TRACK_EN = 1
3879 23:31:41.167960 RX_GATING_MODE = 2
3880 23:31:41.170782 RX_GATING_TRACK_MODE = 2
3881 23:31:41.174276 SELPH_MODE = 1
3882 23:31:41.174733 PICG_EARLY_EN = 1
3883 23:31:41.177861 VALID_LAT_VALUE = 1
3884 23:31:41.184041 ==============================================================
3885 23:31:41.188004 Enter into Gating configuration >>>>
3886 23:31:41.190644 Exit from Gating configuration <<<<
3887 23:31:41.194282 Enter into DVFS_PRE_config >>>>>
3888 23:31:41.204358 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3889 23:31:41.207378 Exit from DVFS_PRE_config <<<<<
3890 23:31:41.210852 Enter into PICG configuration >>>>
3891 23:31:41.213812 Exit from PICG configuration <<<<
3892 23:31:41.217520 [RX_INPUT] configuration >>>>>
3893 23:31:41.220558 [RX_INPUT] configuration <<<<<
3894 23:31:41.224071 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3895 23:31:41.230727 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3896 23:31:41.237510 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3897 23:31:41.244272 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3898 23:31:41.250675 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3899 23:31:41.253819 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3900 23:31:41.260851 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3901 23:31:41.264059 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3902 23:31:41.267714 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3903 23:31:41.270474 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3904 23:31:41.277377 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3905 23:31:41.280822 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3906 23:31:41.283864 ===================================
3907 23:31:41.287356 LPDDR4 DRAM CONFIGURATION
3908 23:31:41.290471 ===================================
3909 23:31:41.290941 EX_ROW_EN[0] = 0x0
3910 23:31:41.293863 EX_ROW_EN[1] = 0x0
3911 23:31:41.294323 LP4Y_EN = 0x0
3912 23:31:41.297005 WORK_FSP = 0x0
3913 23:31:41.297473 WL = 0x2
3914 23:31:41.300951 RL = 0x2
3915 23:31:41.301506 BL = 0x2
3916 23:31:41.303849 RPST = 0x0
3917 23:31:41.304303 RD_PRE = 0x0
3918 23:31:41.306722 WR_PRE = 0x1
3919 23:31:41.307189 WR_PST = 0x0
3920 23:31:41.310293 DBI_WR = 0x0
3921 23:31:41.313675 DBI_RD = 0x0
3922 23:31:41.314444 OTF = 0x1
3923 23:31:41.317091 ===================================
3924 23:31:41.320585 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3925 23:31:41.323506 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3926 23:31:41.330748 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3927 23:31:41.333962 ===================================
3928 23:31:41.336633 LPDDR4 DRAM CONFIGURATION
3929 23:31:41.340213 ===================================
3930 23:31:41.340631 EX_ROW_EN[0] = 0x10
3931 23:31:41.343436 EX_ROW_EN[1] = 0x0
3932 23:31:41.343849 LP4Y_EN = 0x0
3933 23:31:41.347068 WORK_FSP = 0x0
3934 23:31:41.347481 WL = 0x2
3935 23:31:41.350225 RL = 0x2
3936 23:31:41.350638 BL = 0x2
3937 23:31:41.353755 RPST = 0x0
3938 23:31:41.354173 RD_PRE = 0x0
3939 23:31:41.356752 WR_PRE = 0x1
3940 23:31:41.357164 WR_PST = 0x0
3941 23:31:41.360419 DBI_WR = 0x0
3942 23:31:41.360834 DBI_RD = 0x0
3943 23:31:41.363417 OTF = 0x1
3944 23:31:41.366686 ===================================
3945 23:31:41.373645 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3946 23:31:41.376832 nWR fixed to 30
3947 23:31:41.380069 [ModeRegInit_LP4] CH0 RK0
3948 23:31:41.380482 [ModeRegInit_LP4] CH0 RK1
3949 23:31:41.383741 [ModeRegInit_LP4] CH1 RK0
3950 23:31:41.386765 [ModeRegInit_LP4] CH1 RK1
3951 23:31:41.387178 match AC timing 17
3952 23:31:41.393526 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3953 23:31:41.397126 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3954 23:31:41.400176 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3955 23:31:41.407118 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3956 23:31:41.410109 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3957 23:31:41.410570 ==
3958 23:31:41.413551 Dram Type= 6, Freq= 0, CH_0, rank 0
3959 23:31:41.417142 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3960 23:31:41.417757 ==
3961 23:31:41.423347 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3962 23:31:41.430138 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3963 23:31:41.433565 [CA 0] Center 35 (5~66) winsize 62
3964 23:31:41.437071 [CA 1] Center 36 (5~67) winsize 63
3965 23:31:41.440048 [CA 2] Center 33 (3~64) winsize 62
3966 23:31:41.443156 [CA 3] Center 33 (2~64) winsize 63
3967 23:31:41.446654 [CA 4] Center 33 (2~64) winsize 63
3968 23:31:41.450200 [CA 5] Center 32 (2~63) winsize 62
3969 23:31:41.450760
3970 23:31:41.453468 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3971 23:31:41.454118
3972 23:31:41.456889 [CATrainingPosCal] consider 1 rank data
3973 23:31:41.460317 u2DelayCellTimex100 = 270/100 ps
3974 23:31:41.463741 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3975 23:31:41.467123 CA1 delay=36 (5~67),Diff = 4 PI (38 cell)
3976 23:31:41.470111 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3977 23:31:41.473726 CA3 delay=33 (2~64),Diff = 1 PI (9 cell)
3978 23:31:41.477162 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3979 23:31:41.480199 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3980 23:31:41.480754
3981 23:31:41.486251 CA PerBit enable=1, Macro0, CA PI delay=32
3982 23:31:41.486710
3983 23:31:41.487072 [CBTSetCACLKResult] CA Dly = 32
3984 23:31:41.490533 CS Dly: 4 (0~35)
3985 23:31:41.491091 ==
3986 23:31:41.493016 Dram Type= 6, Freq= 0, CH_0, rank 1
3987 23:31:41.496919 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3988 23:31:41.497377 ==
3989 23:31:41.503217 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3990 23:31:41.510029 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3991 23:31:41.513378 [CA 0] Center 35 (5~66) winsize 62
3992 23:31:41.516486 [CA 1] Center 35 (5~66) winsize 62
3993 23:31:41.519703 [CA 2] Center 34 (3~65) winsize 63
3994 23:31:41.523108 [CA 3] Center 33 (3~64) winsize 62
3995 23:31:41.526301 [CA 4] Center 32 (2~63) winsize 62
3996 23:31:41.529648 [CA 5] Center 32 (2~63) winsize 62
3997 23:31:41.530209
3998 23:31:41.532952 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3999 23:31:41.533509
4000 23:31:41.536511 [CATrainingPosCal] consider 2 rank data
4001 23:31:41.539696 u2DelayCellTimex100 = 270/100 ps
4002 23:31:41.542994 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
4003 23:31:41.546086 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
4004 23:31:41.549842 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
4005 23:31:41.553381 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
4006 23:31:41.556010 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
4007 23:31:41.562963 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
4008 23:31:41.563524
4009 23:31:41.566671 CA PerBit enable=1, Macro0, CA PI delay=32
4010 23:31:41.567230
4011 23:31:41.569670 [CBTSetCACLKResult] CA Dly = 32
4012 23:31:41.570134 CS Dly: 4 (0~36)
4013 23:31:41.570502
4014 23:31:41.572993 ----->DramcWriteLeveling(PI) begin...
4015 23:31:41.573457 ==
4016 23:31:41.576205 Dram Type= 6, Freq= 0, CH_0, rank 0
4017 23:31:41.582443 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4018 23:31:41.582989 ==
4019 23:31:41.586333 Write leveling (Byte 0): 34 => 34
4020 23:31:41.586890 Write leveling (Byte 1): 33 => 33
4021 23:31:41.589520 DramcWriteLeveling(PI) end<-----
4022 23:31:41.590122
4023 23:31:41.590487 ==
4024 23:31:41.592946 Dram Type= 6, Freq= 0, CH_0, rank 0
4025 23:31:41.599357 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4026 23:31:41.599913 ==
4027 23:31:41.602854 [Gating] SW mode calibration
4028 23:31:41.609445 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4029 23:31:41.612997 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4030 23:31:41.619348 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4031 23:31:41.623025 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4032 23:31:41.625872 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4033 23:31:41.632800 0 9 12 | B1->B0 | 3434 2d2d | 1 0 | (1 1) (0 0)
4034 23:31:41.636163 0 9 16 | B1->B0 | 2f2f 2323 | 1 0 | (0 0) (0 0)
4035 23:31:41.639290 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4036 23:31:41.645976 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4037 23:31:41.649479 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4038 23:31:41.652592 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4039 23:31:41.655511 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4040 23:31:41.662515 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4041 23:31:41.666161 0 10 12 | B1->B0 | 2323 3434 | 0 0 | (0 0) (1 1)
4042 23:31:41.669219 0 10 16 | B1->B0 | 3333 4646 | 0 0 | (1 1) (0 0)
4043 23:31:41.675699 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4044 23:31:41.679135 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4045 23:31:41.682241 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4046 23:31:41.689425 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4047 23:31:41.692703 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4048 23:31:41.695905 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4049 23:31:41.702710 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4050 23:31:41.706200 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4051 23:31:41.709130 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4052 23:31:41.716051 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4053 23:31:41.719191 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4054 23:31:41.722264 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4055 23:31:41.728900 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4056 23:31:41.732449 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4057 23:31:41.735942 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4058 23:31:41.742734 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4059 23:31:41.746117 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4060 23:31:41.748866 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4061 23:31:41.755429 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4062 23:31:41.758951 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4063 23:31:41.762471 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4064 23:31:41.769171 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4065 23:31:41.771973 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4066 23:31:41.776196 Total UI for P1: 0, mck2ui 16
4067 23:31:41.778846 best dqsien dly found for B0: ( 0, 13, 10)
4068 23:31:41.782216 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4069 23:31:41.785646 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4070 23:31:41.789533 Total UI for P1: 0, mck2ui 16
4071 23:31:41.792790 best dqsien dly found for B1: ( 0, 13, 18)
4072 23:31:41.795951 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4073 23:31:41.802599 best DQS1 dly(MCK, UI, PI) = (0, 13, 18)
4074 23:31:41.803159
4075 23:31:41.805569 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4076 23:31:41.809120 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)
4077 23:31:41.812279 [Gating] SW calibration Done
4078 23:31:41.812832 ==
4079 23:31:41.815309 Dram Type= 6, Freq= 0, CH_0, rank 0
4080 23:31:41.819374 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4081 23:31:41.819934 ==
4082 23:31:41.820386 RX Vref Scan: 0
4083 23:31:41.821789
4084 23:31:41.822280 RX Vref 0 -> 0, step: 1
4085 23:31:41.822677
4086 23:31:41.825629 RX Delay -230 -> 252, step: 16
4087 23:31:41.828858 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4088 23:31:41.835159 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4089 23:31:41.838556 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4090 23:31:41.841663 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4091 23:31:41.845117 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4092 23:31:41.848540 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4093 23:31:41.855804 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4094 23:31:41.858797 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4095 23:31:41.862230 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4096 23:31:41.865191 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4097 23:31:41.871951 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4098 23:31:41.875259 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4099 23:31:41.879360 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4100 23:31:41.882206 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4101 23:31:41.889064 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4102 23:31:41.892333 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4103 23:31:41.892955 ==
4104 23:31:41.895973 Dram Type= 6, Freq= 0, CH_0, rank 0
4105 23:31:41.898736 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4106 23:31:41.899238 ==
4107 23:31:41.899614 DQS Delay:
4108 23:31:41.902141 DQS0 = 0, DQS1 = 0
4109 23:31:41.902595 DQM Delay:
4110 23:31:41.905118 DQM0 = 50, DQM1 = 45
4111 23:31:41.905628 DQ Delay:
4112 23:31:41.908643 DQ0 =49, DQ1 =57, DQ2 =41, DQ3 =41
4113 23:31:41.912070 DQ4 =57, DQ5 =41, DQ6 =57, DQ7 =57
4114 23:31:41.915146 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =41
4115 23:31:41.918545 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =57
4116 23:31:41.919110
4117 23:31:41.919476
4118 23:31:41.919814 ==
4119 23:31:41.921743 Dram Type= 6, Freq= 0, CH_0, rank 0
4120 23:31:41.925160 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4121 23:31:41.928739 ==
4122 23:31:41.929305
4123 23:31:41.929738
4124 23:31:41.930089 TX Vref Scan disable
4125 23:31:41.931460 == TX Byte 0 ==
4126 23:31:41.935035 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4127 23:31:41.938687 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4128 23:31:41.941673 == TX Byte 1 ==
4129 23:31:41.944784 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4130 23:31:41.951579 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4131 23:31:41.952061 ==
4132 23:31:41.955313 Dram Type= 6, Freq= 0, CH_0, rank 0
4133 23:31:41.957939 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4134 23:31:41.958402 ==
4135 23:31:41.958770
4136 23:31:41.959108
4137 23:31:41.961280 TX Vref Scan disable
4138 23:31:41.964747 == TX Byte 0 ==
4139 23:31:41.968213 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4140 23:31:41.971831 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4141 23:31:41.975075 == TX Byte 1 ==
4142 23:31:41.978151 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4143 23:31:41.981509 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4144 23:31:41.982139
4145 23:31:41.982510 [DATLAT]
4146 23:31:41.984820 Freq=600, CH0 RK0
4147 23:31:41.985385
4148 23:31:41.985801 DATLAT Default: 0x9
4149 23:31:41.987985 0, 0xFFFF, sum = 0
4150 23:31:41.991412 1, 0xFFFF, sum = 0
4151 23:31:41.991987 2, 0xFFFF, sum = 0
4152 23:31:41.994756 3, 0xFFFF, sum = 0
4153 23:31:41.995226 4, 0xFFFF, sum = 0
4154 23:31:41.998062 5, 0xFFFF, sum = 0
4155 23:31:41.998639 6, 0xFFFF, sum = 0
4156 23:31:42.001403 7, 0xFFFF, sum = 0
4157 23:31:42.001955 8, 0x0, sum = 1
4158 23:31:42.002332 9, 0x0, sum = 2
4159 23:31:42.004447 10, 0x0, sum = 3
4160 23:31:42.005006 11, 0x0, sum = 4
4161 23:31:42.008232 best_step = 9
4162 23:31:42.008794
4163 23:31:42.009158 ==
4164 23:31:42.011506 Dram Type= 6, Freq= 0, CH_0, rank 0
4165 23:31:42.014995 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4166 23:31:42.015560 ==
4167 23:31:42.017951 RX Vref Scan: 1
4168 23:31:42.018410
4169 23:31:42.018775 RX Vref 0 -> 0, step: 1
4170 23:31:42.019118
4171 23:31:42.021783 RX Delay -163 -> 252, step: 8
4172 23:31:42.022246
4173 23:31:42.024483 Set Vref, RX VrefLevel [Byte0]: 54
4174 23:31:42.027895 [Byte1]: 54
4175 23:31:42.032284
4176 23:31:42.032841 Final RX Vref Byte 0 = 54 to rank0
4177 23:31:42.035113 Final RX Vref Byte 1 = 54 to rank0
4178 23:31:42.039458 Final RX Vref Byte 0 = 54 to rank1
4179 23:31:42.041792 Final RX Vref Byte 1 = 54 to rank1==
4180 23:31:42.045484 Dram Type= 6, Freq= 0, CH_0, rank 0
4181 23:31:42.052068 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4182 23:31:42.052632 ==
4183 23:31:42.053036 DQS Delay:
4184 23:31:42.053383 DQS0 = 0, DQS1 = 0
4185 23:31:42.055463 DQM Delay:
4186 23:31:42.056090 DQM0 = 52, DQM1 = 46
4187 23:31:42.058524 DQ Delay:
4188 23:31:42.062289 DQ0 =52, DQ1 =56, DQ2 =48, DQ3 =52
4189 23:31:42.062851 DQ4 =52, DQ5 =44, DQ6 =60, DQ7 =56
4190 23:31:42.065429 DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =40
4191 23:31:42.069068 DQ12 =52, DQ13 =52, DQ14 =56, DQ15 =52
4192 23:31:42.072650
4193 23:31:42.073247
4194 23:31:42.078563 [DQSOSCAuto] RK0, (LSB)MR18= 0x6a5d, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 389 ps
4195 23:31:42.082099 CH0 RK0: MR19=808, MR18=6A5D
4196 23:31:42.088760 CH0_RK0: MR19=0x808, MR18=0x6A5D, DQSOSC=389, MR23=63, INC=173, DEC=115
4197 23:31:42.089327
4198 23:31:42.092136 ----->DramcWriteLeveling(PI) begin...
4199 23:31:42.092707 ==
4200 23:31:42.095268 Dram Type= 6, Freq= 0, CH_0, rank 1
4201 23:31:42.098799 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4202 23:31:42.099391 ==
4203 23:31:42.102125 Write leveling (Byte 0): 34 => 34
4204 23:31:42.105123 Write leveling (Byte 1): 31 => 31
4205 23:31:42.108487 DramcWriteLeveling(PI) end<-----
4206 23:31:42.109046
4207 23:31:42.109421 ==
4208 23:31:42.112252 Dram Type= 6, Freq= 0, CH_0, rank 1
4209 23:31:42.115137 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4210 23:31:42.115705 ==
4211 23:31:42.118716 [Gating] SW mode calibration
4212 23:31:42.125016 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4213 23:31:42.132287 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4214 23:31:42.134876 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4215 23:31:42.141697 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4216 23:31:42.145173 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4217 23:31:42.148260 0 9 12 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
4218 23:31:42.151514 0 9 16 | B1->B0 | 2c2c 2828 | 0 0 | (0 0) (0 0)
4219 23:31:42.157883 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4220 23:31:42.161487 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4221 23:31:42.164468 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4222 23:31:42.171147 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4223 23:31:42.175065 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4224 23:31:42.178289 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4225 23:31:42.185122 0 10 12 | B1->B0 | 2323 2e2d | 0 1 | (0 0) (0 0)
4226 23:31:42.188456 0 10 16 | B1->B0 | 3f3f 3c3c | 0 1 | (1 1) (0 0)
4227 23:31:42.191993 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4228 23:31:42.198274 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4229 23:31:42.201348 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4230 23:31:42.204868 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4231 23:31:42.211229 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4232 23:31:42.214987 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4233 23:31:42.218242 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4234 23:31:42.224991 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4235 23:31:42.227968 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4236 23:31:42.231133 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4237 23:31:42.238013 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4238 23:31:42.240835 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4239 23:31:42.244104 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4240 23:31:42.250596 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4241 23:31:42.254561 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4242 23:31:42.258298 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4243 23:31:42.263957 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4244 23:31:42.267418 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4245 23:31:42.270749 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4246 23:31:42.277116 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4247 23:31:42.280805 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4248 23:31:42.283661 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4249 23:31:42.290567 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4250 23:31:42.291131 Total UI for P1: 0, mck2ui 16
4251 23:31:42.297660 best dqsien dly found for B0: ( 0, 13, 10)
4252 23:31:42.300355 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4253 23:31:42.303795 Total UI for P1: 0, mck2ui 16
4254 23:31:42.307177 best dqsien dly found for B1: ( 0, 13, 12)
4255 23:31:42.310440 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4256 23:31:42.313886 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4257 23:31:42.314445
4258 23:31:42.317113 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4259 23:31:42.320643 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4260 23:31:42.324031 [Gating] SW calibration Done
4261 23:31:42.324809 ==
4262 23:31:42.326833 Dram Type= 6, Freq= 0, CH_0, rank 1
4263 23:31:42.330054 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4264 23:31:42.333524 ==
4265 23:31:42.334046 RX Vref Scan: 0
4266 23:31:42.334444
4267 23:31:42.336751 RX Vref 0 -> 0, step: 1
4268 23:31:42.337413
4269 23:31:42.339857 RX Delay -230 -> 252, step: 16
4270 23:31:42.343206 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4271 23:31:42.346728 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4272 23:31:42.350049 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4273 23:31:42.356695 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4274 23:31:42.359837 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4275 23:31:42.363246 iDelay=218, Bit 5, Center 49 (-102 ~ 201) 304
4276 23:31:42.366432 iDelay=218, Bit 6, Center 57 (-86 ~ 201) 288
4277 23:31:42.369828 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4278 23:31:42.377012 iDelay=218, Bit 8, Center 41 (-102 ~ 185) 288
4279 23:31:42.380043 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4280 23:31:42.383599 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4281 23:31:42.387133 iDelay=218, Bit 11, Center 41 (-102 ~ 185) 288
4282 23:31:42.393312 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4283 23:31:42.396817 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4284 23:31:42.400318 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4285 23:31:42.403387 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4286 23:31:42.403962 ==
4287 23:31:42.406887 Dram Type= 6, Freq= 0, CH_0, rank 1
4288 23:31:42.413702 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4289 23:31:42.414281 ==
4290 23:31:42.414654 DQS Delay:
4291 23:31:42.415001 DQS0 = 0, DQS1 = 0
4292 23:31:42.416933 DQM Delay:
4293 23:31:42.417401 DQM0 = 53, DQM1 = 45
4294 23:31:42.420246 DQ Delay:
4295 23:31:42.423389 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =49
4296 23:31:42.426737 DQ4 =57, DQ5 =49, DQ6 =57, DQ7 =65
4297 23:31:42.427346 DQ8 =41, DQ9 =25, DQ10 =49, DQ11 =41
4298 23:31:42.433412 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =49
4299 23:31:42.434010
4300 23:31:42.434385
4301 23:31:42.434727 ==
4302 23:31:42.436839 Dram Type= 6, Freq= 0, CH_0, rank 1
4303 23:31:42.440291 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4304 23:31:42.440866 ==
4305 23:31:42.441241
4306 23:31:42.441618
4307 23:31:42.443789 TX Vref Scan disable
4308 23:31:42.444361 == TX Byte 0 ==
4309 23:31:42.450269 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4310 23:31:42.453349 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4311 23:31:42.454028 == TX Byte 1 ==
4312 23:31:42.460155 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4313 23:31:42.463239 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4314 23:31:42.463773 ==
4315 23:31:42.467107 Dram Type= 6, Freq= 0, CH_0, rank 1
4316 23:31:42.469914 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4317 23:31:42.470386 ==
4318 23:31:42.470757
4319 23:31:42.473359
4320 23:31:42.473880 TX Vref Scan disable
4321 23:31:42.476370 == TX Byte 0 ==
4322 23:31:42.480167 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4323 23:31:42.486478 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4324 23:31:42.486948 == TX Byte 1 ==
4325 23:31:42.489915 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4326 23:31:42.496323 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4327 23:31:42.496879
4328 23:31:42.497248 [DATLAT]
4329 23:31:42.497639 Freq=600, CH0 RK1
4330 23:31:42.497989
4331 23:31:42.499611 DATLAT Default: 0x9
4332 23:31:42.500075 0, 0xFFFF, sum = 0
4333 23:31:42.503087 1, 0xFFFF, sum = 0
4334 23:31:42.506192 2, 0xFFFF, sum = 0
4335 23:31:42.506667 3, 0xFFFF, sum = 0
4336 23:31:42.509472 4, 0xFFFF, sum = 0
4337 23:31:42.510008 5, 0xFFFF, sum = 0
4338 23:31:42.513037 6, 0xFFFF, sum = 0
4339 23:31:42.513659 7, 0xFFFF, sum = 0
4340 23:31:42.516274 8, 0x0, sum = 1
4341 23:31:42.516875 9, 0x0, sum = 2
4342 23:31:42.517256 10, 0x0, sum = 3
4343 23:31:42.519620 11, 0x0, sum = 4
4344 23:31:42.520094 best_step = 9
4345 23:31:42.520463
4346 23:31:42.520802 ==
4347 23:31:42.523342 Dram Type= 6, Freq= 0, CH_0, rank 1
4348 23:31:42.529728 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4349 23:31:42.530201 ==
4350 23:31:42.530574 RX Vref Scan: 0
4351 23:31:42.530925
4352 23:31:42.533365 RX Vref 0 -> 0, step: 1
4353 23:31:42.533983
4354 23:31:42.536072 RX Delay -179 -> 252, step: 8
4355 23:31:42.539530 iDelay=197, Bit 0, Center 52 (-91 ~ 196) 288
4356 23:31:42.546171 iDelay=197, Bit 1, Center 56 (-83 ~ 196) 280
4357 23:31:42.549572 iDelay=197, Bit 2, Center 52 (-91 ~ 196) 288
4358 23:31:42.552873 iDelay=197, Bit 3, Center 52 (-91 ~ 196) 288
4359 23:31:42.555973 iDelay=197, Bit 4, Center 56 (-83 ~ 196) 280
4360 23:31:42.559254 iDelay=197, Bit 5, Center 44 (-99 ~ 188) 288
4361 23:31:42.565931 iDelay=197, Bit 6, Center 56 (-83 ~ 196) 280
4362 23:31:42.569044 iDelay=197, Bit 7, Center 56 (-83 ~ 196) 280
4363 23:31:42.572384 iDelay=197, Bit 8, Center 36 (-107 ~ 180) 288
4364 23:31:42.575876 iDelay=197, Bit 9, Center 36 (-107 ~ 180) 288
4365 23:31:42.579666 iDelay=197, Bit 10, Center 48 (-91 ~ 188) 280
4366 23:31:42.585875 iDelay=197, Bit 11, Center 40 (-99 ~ 180) 280
4367 23:31:42.589328 iDelay=197, Bit 12, Center 56 (-83 ~ 196) 280
4368 23:31:42.592698 iDelay=197, Bit 13, Center 52 (-91 ~ 196) 288
4369 23:31:42.596103 iDelay=197, Bit 14, Center 56 (-83 ~ 196) 280
4370 23:31:42.602335 iDelay=197, Bit 15, Center 52 (-91 ~ 196) 288
4371 23:31:42.602800 ==
4372 23:31:42.605626 Dram Type= 6, Freq= 0, CH_0, rank 1
4373 23:31:42.609212 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4374 23:31:42.610006 ==
4375 23:31:42.610833 DQS Delay:
4376 23:31:42.612257 DQS0 = 0, DQS1 = 0
4377 23:31:42.612666 DQM Delay:
4378 23:31:42.616664 DQM0 = 53, DQM1 = 47
4379 23:31:42.617192 DQ Delay:
4380 23:31:42.619303 DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =52
4381 23:31:42.622282 DQ4 =56, DQ5 =44, DQ6 =56, DQ7 =56
4382 23:31:42.625789 DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =40
4383 23:31:42.629122 DQ12 =56, DQ13 =52, DQ14 =56, DQ15 =52
4384 23:31:42.629542
4385 23:31:42.629926
4386 23:31:42.636389 [DQSOSCAuto] RK1, (LSB)MR18= 0x6121, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 391 ps
4387 23:31:42.638734 CH0 RK1: MR19=808, MR18=6121
4388 23:31:42.646131 CH0_RK1: MR19=0x808, MR18=0x6121, DQSOSC=391, MR23=63, INC=171, DEC=114
4389 23:31:42.648955 [RxdqsGatingPostProcess] freq 600
4390 23:31:42.655740 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4391 23:31:42.658887 Pre-setting of DQS Precalculation
4392 23:31:42.662261 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4393 23:31:42.662686 ==
4394 23:31:42.665428 Dram Type= 6, Freq= 0, CH_1, rank 0
4395 23:31:42.669247 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4396 23:31:42.669825 ==
4397 23:31:42.675277 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4398 23:31:42.682230 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4399 23:31:42.685450 [CA 0] Center 36 (5~67) winsize 63
4400 23:31:42.688626 [CA 1] Center 36 (6~67) winsize 62
4401 23:31:42.691944 [CA 2] Center 34 (4~65) winsize 62
4402 23:31:42.695463 [CA 3] Center 34 (4~65) winsize 62
4403 23:31:42.699300 [CA 4] Center 34 (4~65) winsize 62
4404 23:31:42.702501 [CA 5] Center 34 (4~65) winsize 62
4405 23:31:42.703048
4406 23:31:42.705309 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4407 23:31:42.705808
4408 23:31:42.708984 [CATrainingPosCal] consider 1 rank data
4409 23:31:42.711912 u2DelayCellTimex100 = 270/100 ps
4410 23:31:42.715743 CA0 delay=36 (5~67),Diff = 2 PI (19 cell)
4411 23:31:42.718493 CA1 delay=36 (6~67),Diff = 2 PI (19 cell)
4412 23:31:42.722206 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4413 23:31:42.725927 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4414 23:31:42.729288 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4415 23:31:42.735332 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4416 23:31:42.735913
4417 23:31:42.738743 CA PerBit enable=1, Macro0, CA PI delay=34
4418 23:31:42.739212
4419 23:31:42.742228 [CBTSetCACLKResult] CA Dly = 34
4420 23:31:42.742809 CS Dly: 6 (0~37)
4421 23:31:42.743184 ==
4422 23:31:42.745459 Dram Type= 6, Freq= 0, CH_1, rank 1
4423 23:31:42.748851 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4424 23:31:42.751955 ==
4425 23:31:42.755384 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4426 23:31:42.761744 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4427 23:31:42.765211 [CA 0] Center 36 (5~67) winsize 63
4428 23:31:42.768586 [CA 1] Center 36 (5~67) winsize 63
4429 23:31:42.771904 [CA 2] Center 34 (4~65) winsize 62
4430 23:31:42.774636 [CA 3] Center 34 (4~65) winsize 62
4431 23:31:42.778179 [CA 4] Center 34 (4~65) winsize 62
4432 23:31:42.781681 [CA 5] Center 34 (4~64) winsize 61
4433 23:31:42.782241
4434 23:31:42.784776 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4435 23:31:42.785333
4436 23:31:42.787791 [CATrainingPosCal] consider 2 rank data
4437 23:31:42.791436 u2DelayCellTimex100 = 270/100 ps
4438 23:31:42.794647 CA0 delay=36 (5~67),Diff = 2 PI (19 cell)
4439 23:31:42.798129 CA1 delay=36 (6~67),Diff = 2 PI (19 cell)
4440 23:31:42.801175 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4441 23:31:42.807953 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4442 23:31:42.811032 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4443 23:31:42.814568 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4444 23:31:42.815142
4445 23:31:42.817823 CA PerBit enable=1, Macro0, CA PI delay=34
4446 23:31:42.818290
4447 23:31:42.821018 [CBTSetCACLKResult] CA Dly = 34
4448 23:31:42.821627 CS Dly: 6 (0~38)
4449 23:31:42.822020
4450 23:31:42.824789 ----->DramcWriteLeveling(PI) begin...
4451 23:31:42.828034 ==
4452 23:31:42.828611 Dram Type= 6, Freq= 0, CH_1, rank 0
4453 23:31:42.834915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4454 23:31:42.835495 ==
4455 23:31:42.837983 Write leveling (Byte 0): 29 => 29
4456 23:31:42.841191 Write leveling (Byte 1): 31 => 31
4457 23:31:42.844482 DramcWriteLeveling(PI) end<-----
4458 23:31:42.845052
4459 23:31:42.845424 ==
4460 23:31:42.848124 Dram Type= 6, Freq= 0, CH_1, rank 0
4461 23:31:42.850974 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4462 23:31:42.851446 ==
4463 23:31:42.854514 [Gating] SW mode calibration
4464 23:31:42.861258 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4465 23:31:42.864410 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4466 23:31:42.871202 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4467 23:31:42.874299 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4468 23:31:42.877777 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4469 23:31:42.884997 0 9 12 | B1->B0 | 3232 2e2e | 0 1 | (0 1) (1 1)
4470 23:31:42.887345 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4471 23:31:42.891205 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4472 23:31:42.898013 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4473 23:31:42.901092 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4474 23:31:42.903987 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4475 23:31:42.911646 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4476 23:31:42.913997 0 10 8 | B1->B0 | 2323 2626 | 0 1 | (0 0) (0 0)
4477 23:31:42.917809 0 10 12 | B1->B0 | 3434 3a3a | 0 0 | (1 1) (0 0)
4478 23:31:42.924241 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4479 23:31:42.927659 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4480 23:31:42.931073 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4481 23:31:42.937359 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4482 23:31:42.940557 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4483 23:31:42.944081 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4484 23:31:42.950709 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4485 23:31:42.954265 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4486 23:31:42.957747 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4487 23:31:42.963896 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4488 23:31:42.967037 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4489 23:31:42.970855 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4490 23:31:42.974062 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4491 23:31:42.980706 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4492 23:31:42.984244 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4493 23:31:42.987353 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4494 23:31:42.994223 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4495 23:31:42.997486 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4496 23:31:43.001258 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4497 23:31:43.007973 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4498 23:31:43.010924 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4499 23:31:43.014304 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4500 23:31:43.020784 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4501 23:31:43.024708 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4502 23:31:43.027606 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4503 23:31:43.031024 Total UI for P1: 0, mck2ui 16
4504 23:31:43.034352 best dqsien dly found for B0: ( 0, 13, 10)
4505 23:31:43.037461 Total UI for P1: 0, mck2ui 16
4506 23:31:43.040639 best dqsien dly found for B1: ( 0, 13, 12)
4507 23:31:43.043934 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4508 23:31:43.047662 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4509 23:31:43.048225
4510 23:31:43.054172 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4511 23:31:43.057421 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4512 23:31:43.058030 [Gating] SW calibration Done
4513 23:31:43.060925 ==
4514 23:31:43.063896 Dram Type= 6, Freq= 0, CH_1, rank 0
4515 23:31:43.067540 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4516 23:31:43.068304 ==
4517 23:31:43.068683 RX Vref Scan: 0
4518 23:31:43.069029
4519 23:31:43.070505 RX Vref 0 -> 0, step: 1
4520 23:31:43.070963
4521 23:31:43.073738 RX Delay -230 -> 252, step: 16
4522 23:31:43.077700 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4523 23:31:43.080409 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4524 23:31:43.087041 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4525 23:31:43.090722 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4526 23:31:43.094074 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4527 23:31:43.097140 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4528 23:31:43.103983 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4529 23:31:43.107081 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4530 23:31:43.110199 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4531 23:31:43.113744 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4532 23:31:43.116915 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4533 23:31:43.123600 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4534 23:31:43.127245 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4535 23:31:43.130322 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4536 23:31:43.133498 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4537 23:31:43.140454 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4538 23:31:43.141041 ==
4539 23:31:43.143522 Dram Type= 6, Freq= 0, CH_1, rank 0
4540 23:31:43.147256 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4541 23:31:43.147820 ==
4542 23:31:43.148190 DQS Delay:
4543 23:31:43.150301 DQS0 = 0, DQS1 = 0
4544 23:31:43.150757 DQM Delay:
4545 23:31:43.153486 DQM0 = 48, DQM1 = 46
4546 23:31:43.153968 DQ Delay:
4547 23:31:43.157239 DQ0 =57, DQ1 =41, DQ2 =41, DQ3 =41
4548 23:31:43.160541 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =41
4549 23:31:43.163626 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4550 23:31:43.167320 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4551 23:31:43.167877
4552 23:31:43.168426
4553 23:31:43.168897 ==
4554 23:31:43.169794 Dram Type= 6, Freq= 0, CH_1, rank 0
4555 23:31:43.173519 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4556 23:31:43.174029 ==
4557 23:31:43.174425
4558 23:31:43.176609
4559 23:31:43.177240 TX Vref Scan disable
4560 23:31:43.179997 == TX Byte 0 ==
4561 23:31:43.183597 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4562 23:31:43.187000 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4563 23:31:43.190141 == TX Byte 1 ==
4564 23:31:43.193666 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4565 23:31:43.197113 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4566 23:31:43.197608 ==
4567 23:31:43.200258 Dram Type= 6, Freq= 0, CH_1, rank 0
4568 23:31:43.206735 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4569 23:31:43.207199 ==
4570 23:31:43.207611
4571 23:31:43.207958
4572 23:31:43.208286 TX Vref Scan disable
4573 23:31:43.211863 == TX Byte 0 ==
4574 23:31:43.214541 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4575 23:31:43.221746 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4576 23:31:43.222423 == TX Byte 1 ==
4577 23:31:43.224475 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4578 23:31:43.231009 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4579 23:31:43.231565
4580 23:31:43.231932 [DATLAT]
4581 23:31:43.232272 Freq=600, CH1 RK0
4582 23:31:43.232604
4583 23:31:43.234714 DATLAT Default: 0x9
4584 23:31:43.235172 0, 0xFFFF, sum = 0
4585 23:31:43.237933 1, 0xFFFF, sum = 0
4586 23:31:43.238407 2, 0xFFFF, sum = 0
4587 23:31:43.241070 3, 0xFFFF, sum = 0
4588 23:31:43.244804 4, 0xFFFF, sum = 0
4589 23:31:43.245536 5, 0xFFFF, sum = 0
4590 23:31:43.247859 6, 0xFFFF, sum = 0
4591 23:31:43.248329 7, 0xFFFF, sum = 0
4592 23:31:43.251027 8, 0x0, sum = 1
4593 23:31:43.251499 9, 0x0, sum = 2
4594 23:31:43.251878 10, 0x0, sum = 3
4595 23:31:43.254494 11, 0x0, sum = 4
4596 23:31:43.255069 best_step = 9
4597 23:31:43.255439
4598 23:31:43.255781 ==
4599 23:31:43.258130 Dram Type= 6, Freq= 0, CH_1, rank 0
4600 23:31:43.264309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4601 23:31:43.264872 ==
4602 23:31:43.265246 RX Vref Scan: 1
4603 23:31:43.265629
4604 23:31:43.267918 RX Vref 0 -> 0, step: 1
4605 23:31:43.268490
4606 23:31:43.271189 RX Delay -163 -> 252, step: 8
4607 23:31:43.271654
4608 23:31:43.274800 Set Vref, RX VrefLevel [Byte0]: 55
4609 23:31:43.277953 [Byte1]: 52
4610 23:31:43.278419
4611 23:31:43.281369 Final RX Vref Byte 0 = 55 to rank0
4612 23:31:43.284420 Final RX Vref Byte 1 = 52 to rank0
4613 23:31:43.287941 Final RX Vref Byte 0 = 55 to rank1
4614 23:31:43.291275 Final RX Vref Byte 1 = 52 to rank1==
4615 23:31:43.294298 Dram Type= 6, Freq= 0, CH_1, rank 0
4616 23:31:43.297920 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4617 23:31:43.298390 ==
4618 23:31:43.301143 DQS Delay:
4619 23:31:43.301755 DQS0 = 0, DQS1 = 0
4620 23:31:43.304376 DQM Delay:
4621 23:31:43.304950 DQM0 = 48, DQM1 = 45
4622 23:31:43.305341 DQ Delay:
4623 23:31:43.307646 DQ0 =48, DQ1 =40, DQ2 =40, DQ3 =48
4624 23:31:43.310995 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4625 23:31:43.314273 DQ8 =36, DQ9 =36, DQ10 =44, DQ11 =36
4626 23:31:43.317723 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =56
4627 23:31:43.318296
4628 23:31:43.318667
4629 23:31:43.327519 [DQSOSCAuto] RK0, (LSB)MR18= 0x456a, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
4630 23:31:43.331217 CH1 RK0: MR19=808, MR18=456A
4631 23:31:43.334176 CH1_RK0: MR19=0x808, MR18=0x456A, DQSOSC=389, MR23=63, INC=173, DEC=115
4632 23:31:43.337572
4633 23:31:43.340545 ----->DramcWriteLeveling(PI) begin...
4634 23:31:43.341128 ==
4635 23:31:43.344211 Dram Type= 6, Freq= 0, CH_1, rank 1
4636 23:31:43.347101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4637 23:31:43.347569 ==
4638 23:31:43.350477 Write leveling (Byte 0): 29 => 29
4639 23:31:43.354065 Write leveling (Byte 1): 32 => 32
4640 23:31:43.357311 DramcWriteLeveling(PI) end<-----
4641 23:31:43.357821
4642 23:31:43.358193 ==
4643 23:31:43.360701 Dram Type= 6, Freq= 0, CH_1, rank 1
4644 23:31:43.363706 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4645 23:31:43.364172 ==
4646 23:31:43.367256 [Gating] SW mode calibration
4647 23:31:43.373977 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4648 23:31:43.380199 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4649 23:31:43.383653 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4650 23:31:43.386877 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4651 23:31:43.393773 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
4652 23:31:43.396705 0 9 12 | B1->B0 | 3030 2f2f | 1 0 | (1 0) (0 1)
4653 23:31:43.400148 0 9 16 | B1->B0 | 2323 2525 | 0 0 | (0 0) (1 0)
4654 23:31:43.406846 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4655 23:31:43.410529 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4656 23:31:43.413635 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4657 23:31:43.420486 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4658 23:31:43.423879 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4659 23:31:43.427068 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4660 23:31:43.433253 0 10 12 | B1->B0 | 3737 3b3b | 0 1 | (0 0) (0 0)
4661 23:31:43.436734 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4662 23:31:43.440168 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4663 23:31:43.443707 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4664 23:31:43.450225 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4665 23:31:43.453243 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4666 23:31:43.456751 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4667 23:31:43.463150 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4668 23:31:43.466877 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4669 23:31:43.470078 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4670 23:31:43.476361 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4671 23:31:43.480408 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4672 23:31:43.483163 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4673 23:31:43.490064 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4674 23:31:43.493562 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4675 23:31:43.496480 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4676 23:31:43.503441 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4677 23:31:43.506888 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4678 23:31:43.509789 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4679 23:31:43.516604 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4680 23:31:43.520531 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4681 23:31:43.523511 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4682 23:31:43.530082 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4683 23:31:43.533460 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4684 23:31:43.537339 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4685 23:31:43.540183 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4686 23:31:43.543500 Total UI for P1: 0, mck2ui 16
4687 23:31:43.546830 best dqsien dly found for B0: ( 0, 13, 12)
4688 23:31:43.550009 Total UI for P1: 0, mck2ui 16
4689 23:31:43.553640 best dqsien dly found for B1: ( 0, 13, 10)
4690 23:31:43.556968 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4691 23:31:43.563308 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4692 23:31:43.563851
4693 23:31:43.566413 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4694 23:31:43.570064 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4695 23:31:43.573119 [Gating] SW calibration Done
4696 23:31:43.573607 ==
4697 23:31:43.576530 Dram Type= 6, Freq= 0, CH_1, rank 1
4698 23:31:43.580285 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4699 23:31:43.580869 ==
4700 23:31:43.583668 RX Vref Scan: 0
4701 23:31:43.584236
4702 23:31:43.584611 RX Vref 0 -> 0, step: 1
4703 23:31:43.584956
4704 23:31:43.586798 RX Delay -230 -> 252, step: 16
4705 23:31:43.590020 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4706 23:31:43.596881 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4707 23:31:43.599768 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4708 23:31:43.603094 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4709 23:31:43.606437 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4710 23:31:43.610156 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4711 23:31:43.616674 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4712 23:31:43.619656 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4713 23:31:43.623475 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4714 23:31:43.626369 iDelay=218, Bit 9, Center 41 (-118 ~ 201) 320
4715 23:31:43.633030 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4716 23:31:43.636857 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4717 23:31:43.640248 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4718 23:31:43.643297 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4719 23:31:43.646633 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4720 23:31:43.653532 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4721 23:31:43.654211 ==
4722 23:31:43.656939 Dram Type= 6, Freq= 0, CH_1, rank 1
4723 23:31:43.660401 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4724 23:31:43.660974 ==
4725 23:31:43.661347 DQS Delay:
4726 23:31:43.663182 DQS0 = 0, DQS1 = 0
4727 23:31:43.663745 DQM Delay:
4728 23:31:43.666403 DQM0 = 47, DQM1 = 48
4729 23:31:43.666865 DQ Delay:
4730 23:31:43.669690 DQ0 =57, DQ1 =41, DQ2 =33, DQ3 =41
4731 23:31:43.673410 DQ4 =41, DQ5 =65, DQ6 =57, DQ7 =41
4732 23:31:43.676831 DQ8 =33, DQ9 =41, DQ10 =49, DQ11 =41
4733 23:31:43.679873 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =57
4734 23:31:43.680431
4735 23:31:43.680990
4736 23:31:43.681353 ==
4737 23:31:43.683258 Dram Type= 6, Freq= 0, CH_1, rank 1
4738 23:31:43.686333 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4739 23:31:43.689770 ==
4740 23:31:43.690232
4741 23:31:43.690598
4742 23:31:43.690955 TX Vref Scan disable
4743 23:31:43.693183 == TX Byte 0 ==
4744 23:31:43.697102 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4745 23:31:43.700051 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4746 23:31:43.703679 == TX Byte 1 ==
4747 23:31:43.706723 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4748 23:31:43.710136 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4749 23:31:43.713286 ==
4750 23:31:43.713788 Dram Type= 6, Freq= 0, CH_1, rank 1
4751 23:31:43.719631 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4752 23:31:43.720189 ==
4753 23:31:43.720562
4754 23:31:43.720902
4755 23:31:43.722776 TX Vref Scan disable
4756 23:31:43.723237 == TX Byte 0 ==
4757 23:31:43.729380 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4758 23:31:43.732984 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4759 23:31:43.733403 == TX Byte 1 ==
4760 23:31:43.740033 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4761 23:31:43.743512 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4762 23:31:43.744043
4763 23:31:43.744382 [DATLAT]
4764 23:31:43.746208 Freq=600, CH1 RK1
4765 23:31:43.746637
4766 23:31:43.746966 DATLAT Default: 0x9
4767 23:31:43.749642 0, 0xFFFF, sum = 0
4768 23:31:43.750079 1, 0xFFFF, sum = 0
4769 23:31:43.752974 2, 0xFFFF, sum = 0
4770 23:31:43.753553 3, 0xFFFF, sum = 0
4771 23:31:43.756175 4, 0xFFFF, sum = 0
4772 23:31:43.756639 5, 0xFFFF, sum = 0
4773 23:31:43.759498 6, 0xFFFF, sum = 0
4774 23:31:43.762754 7, 0xFFFF, sum = 0
4775 23:31:43.763332 8, 0x0, sum = 1
4776 23:31:43.763711 9, 0x0, sum = 2
4777 23:31:43.766564 10, 0x0, sum = 3
4778 23:31:43.767074 11, 0x0, sum = 4
4779 23:31:43.769374 best_step = 9
4780 23:31:43.769864
4781 23:31:43.770232 ==
4782 23:31:43.772880 Dram Type= 6, Freq= 0, CH_1, rank 1
4783 23:31:43.776202 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4784 23:31:43.776672 ==
4785 23:31:43.779469 RX Vref Scan: 0
4786 23:31:43.779933
4787 23:31:43.780300 RX Vref 0 -> 0, step: 1
4788 23:31:43.780663
4789 23:31:43.782915 RX Delay -163 -> 252, step: 8
4790 23:31:43.789638 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4791 23:31:43.793194 iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288
4792 23:31:43.796981 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4793 23:31:43.799946 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4794 23:31:43.803224 iDelay=205, Bit 4, Center 44 (-99 ~ 188) 288
4795 23:31:43.809785 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4796 23:31:43.813210 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4797 23:31:43.816778 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4798 23:31:43.819779 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4799 23:31:43.823191 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4800 23:31:43.830003 iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296
4801 23:31:43.833387 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4802 23:31:43.836286 iDelay=205, Bit 12, Center 56 (-91 ~ 204) 296
4803 23:31:43.840118 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4804 23:31:43.846461 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4805 23:31:43.849830 iDelay=205, Bit 15, Center 56 (-91 ~ 204) 296
4806 23:31:43.850297 ==
4807 23:31:43.852912 Dram Type= 6, Freq= 0, CH_1, rank 1
4808 23:31:43.856206 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4809 23:31:43.856802 ==
4810 23:31:43.860039 DQS Delay:
4811 23:31:43.860611 DQS0 = 0, DQS1 = 0
4812 23:31:43.860985 DQM Delay:
4813 23:31:43.862690 DQM0 = 48, DQM1 = 46
4814 23:31:43.863157 DQ Delay:
4815 23:31:43.866412 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4816 23:31:43.869702 DQ4 =44, DQ5 =60, DQ6 =60, DQ7 =48
4817 23:31:43.873064 DQ8 =32, DQ9 =32, DQ10 =48, DQ11 =40
4818 23:31:43.876397 DQ12 =56, DQ13 =52, DQ14 =52, DQ15 =56
4819 23:31:43.876980
4820 23:31:43.877354
4821 23:31:43.885923 [DQSOSCAuto] RK1, (LSB)MR18= 0x661e, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 390 ps
4822 23:31:43.889428 CH1 RK1: MR19=808, MR18=661E
4823 23:31:43.892680 CH1_RK1: MR19=0x808, MR18=0x661E, DQSOSC=390, MR23=63, INC=172, DEC=114
4824 23:31:43.896297 [RxdqsGatingPostProcess] freq 600
4825 23:31:43.902501 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4826 23:31:43.905904 Pre-setting of DQS Precalculation
4827 23:31:43.909722 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4828 23:31:43.919143 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4829 23:31:43.925888 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4830 23:31:43.926451
4831 23:31:43.926823
4832 23:31:43.929006 [Calibration Summary] 1200 Mbps
4833 23:31:43.929470 CH 0, Rank 0
4834 23:31:43.932623 SW Impedance : PASS
4835 23:31:43.933195 DUTY Scan : NO K
4836 23:31:43.936156 ZQ Calibration : PASS
4837 23:31:43.939140 Jitter Meter : NO K
4838 23:31:43.939604 CBT Training : PASS
4839 23:31:43.942677 Write leveling : PASS
4840 23:31:43.945995 RX DQS gating : PASS
4841 23:31:43.946569 RX DQ/DQS(RDDQC) : PASS
4842 23:31:43.949281 TX DQ/DQS : PASS
4843 23:31:43.949886 RX DATLAT : PASS
4844 23:31:43.952840 RX DQ/DQS(Engine): PASS
4845 23:31:43.955810 TX OE : NO K
4846 23:31:43.956278 All Pass.
4847 23:31:43.956646
4848 23:31:43.956984 CH 0, Rank 1
4849 23:31:43.959426 SW Impedance : PASS
4850 23:31:43.962354 DUTY Scan : NO K
4851 23:31:43.962936 ZQ Calibration : PASS
4852 23:31:43.966325 Jitter Meter : NO K
4853 23:31:43.969120 CBT Training : PASS
4854 23:31:43.969609 Write leveling : PASS
4855 23:31:43.972704 RX DQS gating : PASS
4856 23:31:43.975935 RX DQ/DQS(RDDQC) : PASS
4857 23:31:43.976509 TX DQ/DQS : PASS
4858 23:31:43.979461 RX DATLAT : PASS
4859 23:31:43.982900 RX DQ/DQS(Engine): PASS
4860 23:31:43.983537 TX OE : NO K
4861 23:31:43.983919 All Pass.
4862 23:31:43.985991
4863 23:31:43.986456 CH 1, Rank 0
4864 23:31:43.989162 SW Impedance : PASS
4865 23:31:43.989673 DUTY Scan : NO K
4866 23:31:43.992665 ZQ Calibration : PASS
4867 23:31:43.993186 Jitter Meter : NO K
4868 23:31:43.995856 CBT Training : PASS
4869 23:31:43.999055 Write leveling : PASS
4870 23:31:43.999554 RX DQS gating : PASS
4871 23:31:44.002251 RX DQ/DQS(RDDQC) : PASS
4872 23:31:44.005900 TX DQ/DQS : PASS
4873 23:31:44.006368 RX DATLAT : PASS
4874 23:31:44.009108 RX DQ/DQS(Engine): PASS
4875 23:31:44.012454 TX OE : NO K
4876 23:31:44.012945 All Pass.
4877 23:31:44.013337
4878 23:31:44.013829 CH 1, Rank 1
4879 23:31:44.015900 SW Impedance : PASS
4880 23:31:44.019039 DUTY Scan : NO K
4881 23:31:44.019540 ZQ Calibration : PASS
4882 23:31:44.022580 Jitter Meter : NO K
4883 23:31:44.026000 CBT Training : PASS
4884 23:31:44.026450 Write leveling : PASS
4885 23:31:44.029395 RX DQS gating : PASS
4886 23:31:44.032709 RX DQ/DQS(RDDQC) : PASS
4887 23:31:44.033172 TX DQ/DQS : PASS
4888 23:31:44.035947 RX DATLAT : PASS
4889 23:31:44.036518 RX DQ/DQS(Engine): PASS
4890 23:31:44.039093 TX OE : NO K
4891 23:31:44.039557 All Pass.
4892 23:31:44.039924
4893 23:31:44.042202 DramC Write-DBI off
4894 23:31:44.045547 PER_BANK_REFRESH: Hybrid Mode
4895 23:31:44.046136 TX_TRACKING: ON
4896 23:31:44.055669 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4897 23:31:44.059663 [FAST_K] Save calibration result to emmc
4898 23:31:44.062760 dramc_set_vcore_voltage set vcore to 662500
4899 23:31:44.066132 Read voltage for 933, 3
4900 23:31:44.066703 Vio18 = 0
4901 23:31:44.067077 Vcore = 662500
4902 23:31:44.068859 Vdram = 0
4903 23:31:44.069320 Vddq = 0
4904 23:31:44.069735 Vmddr = 0
4905 23:31:44.075720 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4906 23:31:44.079396 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4907 23:31:44.082629 MEM_TYPE=3, freq_sel=17
4908 23:31:44.085897 sv_algorithm_assistance_LP4_1600
4909 23:31:44.088947 ============ PULL DRAM RESETB DOWN ============
4910 23:31:44.095730 ========== PULL DRAM RESETB DOWN end =========
4911 23:31:44.098877 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4912 23:31:44.102378 ===================================
4913 23:31:44.105541 LPDDR4 DRAM CONFIGURATION
4914 23:31:44.108879 ===================================
4915 23:31:44.109440 EX_ROW_EN[0] = 0x0
4916 23:31:44.112450 EX_ROW_EN[1] = 0x0
4917 23:31:44.113020 LP4Y_EN = 0x0
4918 23:31:44.115520 WORK_FSP = 0x0
4919 23:31:44.116111 WL = 0x3
4920 23:31:44.118895 RL = 0x3
4921 23:31:44.119466 BL = 0x2
4922 23:31:44.122267 RPST = 0x0
4923 23:31:44.122738 RD_PRE = 0x0
4924 23:31:44.125550 WR_PRE = 0x1
4925 23:31:44.126082 WR_PST = 0x0
4926 23:31:44.128628 DBI_WR = 0x0
4927 23:31:44.132217 DBI_RD = 0x0
4928 23:31:44.132683 OTF = 0x1
4929 23:31:44.135039 ===================================
4930 23:31:44.139094 ===================================
4931 23:31:44.139667 ANA top config
4932 23:31:44.141722 ===================================
4933 23:31:44.145385 DLL_ASYNC_EN = 0
4934 23:31:44.148379 ALL_SLAVE_EN = 1
4935 23:31:44.151574 NEW_RANK_MODE = 1
4936 23:31:44.154851 DLL_IDLE_MODE = 1
4937 23:31:44.155319 LP45_APHY_COMB_EN = 1
4938 23:31:44.158358 TX_ODT_DIS = 1
4939 23:31:44.162040 NEW_8X_MODE = 1
4940 23:31:44.165004 ===================================
4941 23:31:44.168827 ===================================
4942 23:31:44.171746 data_rate = 1866
4943 23:31:44.175077 CKR = 1
4944 23:31:44.175542 DQ_P2S_RATIO = 8
4945 23:31:44.178508 ===================================
4946 23:31:44.181840 CA_P2S_RATIO = 8
4947 23:31:44.185812 DQ_CA_OPEN = 0
4948 23:31:44.189033 DQ_SEMI_OPEN = 0
4949 23:31:44.191753 CA_SEMI_OPEN = 0
4950 23:31:44.194846 CA_FULL_RATE = 0
4951 23:31:44.195307 DQ_CKDIV4_EN = 1
4952 23:31:44.198162 CA_CKDIV4_EN = 1
4953 23:31:44.201426 CA_PREDIV_EN = 0
4954 23:31:44.204693 PH8_DLY = 0
4955 23:31:44.208565 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4956 23:31:44.211261 DQ_AAMCK_DIV = 4
4957 23:31:44.211785 CA_AAMCK_DIV = 4
4958 23:31:44.215117 CA_ADMCK_DIV = 4
4959 23:31:44.218265 DQ_TRACK_CA_EN = 0
4960 23:31:44.221905 CA_PICK = 933
4961 23:31:44.225033 CA_MCKIO = 933
4962 23:31:44.228770 MCKIO_SEMI = 0
4963 23:31:44.231610 PLL_FREQ = 3732
4964 23:31:44.232168 DQ_UI_PI_RATIO = 32
4965 23:31:44.234794 CA_UI_PI_RATIO = 0
4966 23:31:44.238135 ===================================
4967 23:31:44.241226 ===================================
4968 23:31:44.245075 memory_type:LPDDR4
4969 23:31:44.248076 GP_NUM : 10
4970 23:31:44.248640 SRAM_EN : 1
4971 23:31:44.251287 MD32_EN : 0
4972 23:31:44.254558 ===================================
4973 23:31:44.258030 [ANA_INIT] >>>>>>>>>>>>>>
4974 23:31:44.258596 <<<<<< [CONFIGURE PHASE]: ANA_TX
4975 23:31:44.264781 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4976 23:31:44.265346 ===================================
4977 23:31:44.268341 data_rate = 1866,PCW = 0X8f00
4978 23:31:44.271072 ===================================
4979 23:31:44.274228 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4980 23:31:44.281164 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4981 23:31:44.287883 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4982 23:31:44.290971 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4983 23:31:44.294140 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4984 23:31:44.297416 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4985 23:31:44.300959 [ANA_INIT] flow start
4986 23:31:44.301422 [ANA_INIT] PLL >>>>>>>>
4987 23:31:44.304229 [ANA_INIT] PLL <<<<<<<<
4988 23:31:44.307743 [ANA_INIT] MIDPI >>>>>>>>
4989 23:31:44.311140 [ANA_INIT] MIDPI <<<<<<<<
4990 23:31:44.311678 [ANA_INIT] DLL >>>>>>>>
4991 23:31:44.314747 [ANA_INIT] flow end
4992 23:31:44.317975 ============ LP4 DIFF to SE enter ============
4993 23:31:44.321087 ============ LP4 DIFF to SE exit ============
4994 23:31:44.324484 [ANA_INIT] <<<<<<<<<<<<<
4995 23:31:44.328181 [Flow] Enable top DCM control >>>>>
4996 23:31:44.331169 [Flow] Enable top DCM control <<<<<
4997 23:31:44.334180 Enable DLL master slave shuffle
4998 23:31:44.340885 ==============================================================
4999 23:31:44.341452 Gating Mode config
5000 23:31:44.347386 ==============================================================
5001 23:31:44.347946 Config description:
5002 23:31:44.357431 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5003 23:31:44.364192 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5004 23:31:44.370695 SELPH_MODE 0: By rank 1: By Phase
5005 23:31:44.374285 ==============================================================
5006 23:31:44.377389 GAT_TRACK_EN = 1
5007 23:31:44.380434 RX_GATING_MODE = 2
5008 23:31:44.384093 RX_GATING_TRACK_MODE = 2
5009 23:31:44.387623 SELPH_MODE = 1
5010 23:31:44.390347 PICG_EARLY_EN = 1
5011 23:31:44.393541 VALID_LAT_VALUE = 1
5012 23:31:44.397528 ==============================================================
5013 23:31:44.400257 Enter into Gating configuration >>>>
5014 23:31:44.403407 Exit from Gating configuration <<<<
5015 23:31:44.406783 Enter into DVFS_PRE_config >>>>>
5016 23:31:44.420087 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5017 23:31:44.423411 Exit from DVFS_PRE_config <<<<<
5018 23:31:44.426809 Enter into PICG configuration >>>>
5019 23:31:44.430144 Exit from PICG configuration <<<<
5020 23:31:44.430628 [RX_INPUT] configuration >>>>>
5021 23:31:44.433747 [RX_INPUT] configuration <<<<<
5022 23:31:44.440051 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5023 23:31:44.443237 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5024 23:31:44.450088 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5025 23:31:44.457490 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5026 23:31:44.463748 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5027 23:31:44.469675 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5028 23:31:44.473354 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5029 23:31:44.476419 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5030 23:31:44.483058 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5031 23:31:44.486366 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5032 23:31:44.490179 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5033 23:31:44.493570 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5034 23:31:44.496674 ===================================
5035 23:31:44.500064 LPDDR4 DRAM CONFIGURATION
5036 23:31:44.503120 ===================================
5037 23:31:44.506330 EX_ROW_EN[0] = 0x0
5038 23:31:44.506795 EX_ROW_EN[1] = 0x0
5039 23:31:44.509506 LP4Y_EN = 0x0
5040 23:31:44.510099 WORK_FSP = 0x0
5041 23:31:44.513212 WL = 0x3
5042 23:31:44.513720 RL = 0x3
5043 23:31:44.517068 BL = 0x2
5044 23:31:44.517691 RPST = 0x0
5045 23:31:44.519959 RD_PRE = 0x0
5046 23:31:44.520419 WR_PRE = 0x1
5047 23:31:44.522725 WR_PST = 0x0
5048 23:31:44.526591 DBI_WR = 0x0
5049 23:31:44.527051 DBI_RD = 0x0
5050 23:31:44.529689 OTF = 0x1
5051 23:31:44.532722 ===================================
5052 23:31:44.536113 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5053 23:31:44.539372 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5054 23:31:44.542536 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5055 23:31:44.546129 ===================================
5056 23:31:44.549295 LPDDR4 DRAM CONFIGURATION
5057 23:31:44.552867 ===================================
5058 23:31:44.555970 EX_ROW_EN[0] = 0x10
5059 23:31:44.556439 EX_ROW_EN[1] = 0x0
5060 23:31:44.559772 LP4Y_EN = 0x0
5061 23:31:44.560327 WORK_FSP = 0x0
5062 23:31:44.562364 WL = 0x3
5063 23:31:44.562997 RL = 0x3
5064 23:31:44.565894 BL = 0x2
5065 23:31:44.566359 RPST = 0x0
5066 23:31:44.569447 RD_PRE = 0x0
5067 23:31:44.570094 WR_PRE = 0x1
5068 23:31:44.572741 WR_PST = 0x0
5069 23:31:44.573315 DBI_WR = 0x0
5070 23:31:44.575987 DBI_RD = 0x0
5071 23:31:44.579084 OTF = 0x1
5072 23:31:44.582975 ===================================
5073 23:31:44.586138 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5074 23:31:44.590759 nWR fixed to 30
5075 23:31:44.594168 [ModeRegInit_LP4] CH0 RK0
5076 23:31:44.594626 [ModeRegInit_LP4] CH0 RK1
5077 23:31:44.597780 [ModeRegInit_LP4] CH1 RK0
5078 23:31:44.601447 [ModeRegInit_LP4] CH1 RK1
5079 23:31:44.602145 match AC timing 9
5080 23:31:44.607160 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5081 23:31:44.612805 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5082 23:31:44.613805 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5083 23:31:44.620868 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5084 23:31:44.624217 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5085 23:31:44.624799 ==
5086 23:31:44.627438 Dram Type= 6, Freq= 0, CH_0, rank 0
5087 23:31:44.630879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5088 23:31:44.631441 ==
5089 23:31:44.637629 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5090 23:31:44.644063 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5091 23:31:44.647325 [CA 0] Center 37 (6~68) winsize 63
5092 23:31:44.650514 [CA 1] Center 37 (7~68) winsize 62
5093 23:31:44.654215 [CA 2] Center 34 (4~65) winsize 62
5094 23:31:44.657188 [CA 3] Center 34 (3~65) winsize 63
5095 23:31:44.660911 [CA 4] Center 33 (3~64) winsize 62
5096 23:31:44.663963 [CA 5] Center 32 (2~62) winsize 61
5097 23:31:44.664429
5098 23:31:44.667553 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5099 23:31:44.668118
5100 23:31:44.670656 [CATrainingPosCal] consider 1 rank data
5101 23:31:44.673622 u2DelayCellTimex100 = 270/100 ps
5102 23:31:44.677103 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5103 23:31:44.680362 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5104 23:31:44.684620 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5105 23:31:44.687203 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5106 23:31:44.690156 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5107 23:31:44.697178 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5108 23:31:44.697754
5109 23:31:44.700386 CA PerBit enable=1, Macro0, CA PI delay=32
5110 23:31:44.700812
5111 23:31:44.703748 [CBTSetCACLKResult] CA Dly = 32
5112 23:31:44.704260 CS Dly: 5 (0~36)
5113 23:31:44.704602 ==
5114 23:31:44.707405 Dram Type= 6, Freq= 0, CH_0, rank 1
5115 23:31:44.710585 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5116 23:31:44.713844 ==
5117 23:31:44.717127 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5118 23:31:44.723476 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5119 23:31:44.726785 [CA 0] Center 37 (6~68) winsize 63
5120 23:31:44.730327 [CA 1] Center 37 (6~68) winsize 63
5121 23:31:44.733648 [CA 2] Center 34 (4~65) winsize 62
5122 23:31:44.736999 [CA 3] Center 34 (3~65) winsize 63
5123 23:31:44.740404 [CA 4] Center 32 (2~63) winsize 62
5124 23:31:44.743506 [CA 5] Center 32 (2~62) winsize 61
5125 23:31:44.743975
5126 23:31:44.747357 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5127 23:31:44.747907
5128 23:31:44.750477 [CATrainingPosCal] consider 2 rank data
5129 23:31:44.753491 u2DelayCellTimex100 = 270/100 ps
5130 23:31:44.756576 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5131 23:31:44.760124 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5132 23:31:44.763175 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5133 23:31:44.770190 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5134 23:31:44.773241 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5135 23:31:44.776882 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5136 23:31:44.777466
5137 23:31:44.780241 CA PerBit enable=1, Macro0, CA PI delay=32
5138 23:31:44.780709
5139 23:31:44.783139 [CBTSetCACLKResult] CA Dly = 32
5140 23:31:44.783693 CS Dly: 5 (0~37)
5141 23:31:44.784069
5142 23:31:44.786588 ----->DramcWriteLeveling(PI) begin...
5143 23:31:44.787061 ==
5144 23:31:44.789798 Dram Type= 6, Freq= 0, CH_0, rank 0
5145 23:31:44.797045 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5146 23:31:44.797659 ==
5147 23:31:44.800308 Write leveling (Byte 0): 34 => 34
5148 23:31:44.802967 Write leveling (Byte 1): 26 => 26
5149 23:31:44.803434 DramcWriteLeveling(PI) end<-----
5150 23:31:44.803807
5151 23:31:44.806349 ==
5152 23:31:44.809676 Dram Type= 6, Freq= 0, CH_0, rank 0
5153 23:31:44.813441 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5154 23:31:44.814091 ==
5155 23:31:44.816604 [Gating] SW mode calibration
5156 23:31:44.823293 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5157 23:31:44.826359 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5158 23:31:44.833320 0 14 0 | B1->B0 | 2828 3434 | 0 1 | (0 0) (1 1)
5159 23:31:44.836815 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5160 23:31:44.839673 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5161 23:31:44.846559 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5162 23:31:44.849852 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5163 23:31:44.853112 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5164 23:31:44.859741 0 14 24 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
5165 23:31:44.863013 0 14 28 | B1->B0 | 3333 2929 | 1 1 | (0 0) (1 1)
5166 23:31:44.866461 0 15 0 | B1->B0 | 2d2d 2323 | 0 0 | (1 0) (0 0)
5167 23:31:44.872828 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5168 23:31:44.876514 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5169 23:31:44.879671 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5170 23:31:44.886518 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5171 23:31:44.889481 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5172 23:31:44.893068 0 15 24 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
5173 23:31:44.899615 0 15 28 | B1->B0 | 2323 3737 | 0 0 | (0 0) (0 0)
5174 23:31:44.902728 1 0 0 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
5175 23:31:44.905690 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5176 23:31:44.912933 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5177 23:31:44.915581 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5178 23:31:44.918841 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5179 23:31:44.925775 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5180 23:31:44.928839 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5181 23:31:44.932986 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
5182 23:31:44.939079 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5183 23:31:44.942071 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5184 23:31:44.946196 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5185 23:31:44.952439 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5186 23:31:44.955884 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5187 23:31:44.959400 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5188 23:31:44.965506 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5189 23:31:44.968849 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5190 23:31:44.972401 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5191 23:31:44.975371 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5192 23:31:44.982114 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5193 23:31:44.985515 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5194 23:31:44.988988 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5195 23:31:44.995770 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5196 23:31:44.999003 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5197 23:31:45.002027 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5198 23:31:45.005456 Total UI for P1: 0, mck2ui 16
5199 23:31:45.008860 best dqsien dly found for B0: ( 1, 2, 24)
5200 23:31:45.015089 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5201 23:31:45.018760 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5202 23:31:45.022252 Total UI for P1: 0, mck2ui 16
5203 23:31:45.025215 best dqsien dly found for B1: ( 1, 2, 30)
5204 23:31:45.028458 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5205 23:31:45.032235 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5206 23:31:45.032717
5207 23:31:45.034948 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5208 23:31:45.038235 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5209 23:31:45.041947 [Gating] SW calibration Done
5210 23:31:45.042511 ==
5211 23:31:45.044985 Dram Type= 6, Freq= 0, CH_0, rank 0
5212 23:31:45.051624 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5213 23:31:45.052178 ==
5214 23:31:45.052551 RX Vref Scan: 0
5215 23:31:45.052892
5216 23:31:45.055018 RX Vref 0 -> 0, step: 1
5217 23:31:45.055477
5218 23:31:45.058922 RX Delay -80 -> 252, step: 8
5219 23:31:45.061715 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5220 23:31:45.064997 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5221 23:31:45.069136 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5222 23:31:45.071770 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5223 23:31:45.074909 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5224 23:31:45.081868 iDelay=208, Bit 5, Center 91 (0 ~ 183) 184
5225 23:31:45.085041 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5226 23:31:45.088574 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5227 23:31:45.091427 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5228 23:31:45.094761 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5229 23:31:45.101868 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5230 23:31:45.104960 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5231 23:31:45.108483 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5232 23:31:45.111566 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5233 23:31:45.115027 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5234 23:31:45.118065 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5235 23:31:45.121648 ==
5236 23:31:45.124744 Dram Type= 6, Freq= 0, CH_0, rank 0
5237 23:31:45.128509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5238 23:31:45.129087 ==
5239 23:31:45.129461 DQS Delay:
5240 23:31:45.131802 DQS0 = 0, DQS1 = 0
5241 23:31:45.132262 DQM Delay:
5242 23:31:45.135559 DQM0 = 104, DQM1 = 95
5243 23:31:45.136127 DQ Delay:
5244 23:31:45.138258 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5245 23:31:45.141520 DQ4 =107, DQ5 =91, DQ6 =115, DQ7 =115
5246 23:31:45.145082 DQ8 =87, DQ9 =87, DQ10 =95, DQ11 =87
5247 23:31:45.148145 DQ12 =99, DQ13 =103, DQ14 =103, DQ15 =99
5248 23:31:45.148622
5249 23:31:45.148986
5250 23:31:45.149323 ==
5251 23:31:45.151679 Dram Type= 6, Freq= 0, CH_0, rank 0
5252 23:31:45.155555 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5253 23:31:45.156121 ==
5254 23:31:45.156488
5255 23:31:45.157937
5256 23:31:45.158417 TX Vref Scan disable
5257 23:31:45.161913 == TX Byte 0 ==
5258 23:31:45.164795 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5259 23:31:45.168194 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5260 23:31:45.171288 == TX Byte 1 ==
5261 23:31:45.175000 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5262 23:31:45.177937 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5263 23:31:45.178404 ==
5264 23:31:45.181626 Dram Type= 6, Freq= 0, CH_0, rank 0
5265 23:31:45.187828 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5266 23:31:45.188397 ==
5267 23:31:45.188768
5268 23:31:45.189106
5269 23:31:45.189431 TX Vref Scan disable
5270 23:31:45.192816 == TX Byte 0 ==
5271 23:31:45.195809 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5272 23:31:45.198908 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5273 23:31:45.202213 == TX Byte 1 ==
5274 23:31:45.205902 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5275 23:31:45.212614 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5276 23:31:45.213195
5277 23:31:45.213562 [DATLAT]
5278 23:31:45.213963 Freq=933, CH0 RK0
5279 23:31:45.214300
5280 23:31:45.215607 DATLAT Default: 0xd
5281 23:31:45.216069 0, 0xFFFF, sum = 0
5282 23:31:45.219060 1, 0xFFFF, sum = 0
5283 23:31:45.222496 2, 0xFFFF, sum = 0
5284 23:31:45.223070 3, 0xFFFF, sum = 0
5285 23:31:45.225357 4, 0xFFFF, sum = 0
5286 23:31:45.225891 5, 0xFFFF, sum = 0
5287 23:31:45.229002 6, 0xFFFF, sum = 0
5288 23:31:45.229651 7, 0xFFFF, sum = 0
5289 23:31:45.232259 8, 0xFFFF, sum = 0
5290 23:31:45.232822 9, 0xFFFF, sum = 0
5291 23:31:45.235565 10, 0x0, sum = 1
5292 23:31:45.236148 11, 0x0, sum = 2
5293 23:31:45.239116 12, 0x0, sum = 3
5294 23:31:45.239583 13, 0x0, sum = 4
5295 23:31:45.239953 best_step = 11
5296 23:31:45.240292
5297 23:31:45.242320 ==
5298 23:31:45.246092 Dram Type= 6, Freq= 0, CH_0, rank 0
5299 23:31:45.249186 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5300 23:31:45.249684 ==
5301 23:31:45.250061 RX Vref Scan: 1
5302 23:31:45.250409
5303 23:31:45.251950 RX Vref 0 -> 0, step: 1
5304 23:31:45.252411
5305 23:31:45.255560 RX Delay -45 -> 252, step: 4
5306 23:31:45.256115
5307 23:31:45.259094 Set Vref, RX VrefLevel [Byte0]: 54
5308 23:31:45.262065 [Byte1]: 54
5309 23:31:45.262623
5310 23:31:45.265644 Final RX Vref Byte 0 = 54 to rank0
5311 23:31:45.268905 Final RX Vref Byte 1 = 54 to rank0
5312 23:31:45.272332 Final RX Vref Byte 0 = 54 to rank1
5313 23:31:45.275474 Final RX Vref Byte 1 = 54 to rank1==
5314 23:31:45.278915 Dram Type= 6, Freq= 0, CH_0, rank 0
5315 23:31:45.281943 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5316 23:31:45.282404 ==
5317 23:31:45.285309 DQS Delay:
5318 23:31:45.285807 DQS0 = 0, DQS1 = 0
5319 23:31:45.288689 DQM Delay:
5320 23:31:45.289245 DQM0 = 105, DQM1 = 97
5321 23:31:45.289673 DQ Delay:
5322 23:31:45.295148 DQ0 =104, DQ1 =106, DQ2 =102, DQ3 =102
5323 23:31:45.298338 DQ4 =106, DQ5 =96, DQ6 =112, DQ7 =112
5324 23:31:45.301651 DQ8 =88, DQ9 =90, DQ10 =98, DQ11 =92
5325 23:31:45.305554 DQ12 =100, DQ13 =102, DQ14 =108, DQ15 =104
5326 23:31:45.306185
5327 23:31:45.306566
5328 23:31:45.312587 [DQSOSCAuto] RK0, (LSB)MR18= 0x2d24, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 407 ps
5329 23:31:45.315089 CH0 RK0: MR19=505, MR18=2D24
5330 23:31:45.321697 CH0_RK0: MR19=0x505, MR18=0x2D24, DQSOSC=407, MR23=63, INC=65, DEC=43
5331 23:31:45.322257
5332 23:31:45.325216 ----->DramcWriteLeveling(PI) begin...
5333 23:31:45.325732 ==
5334 23:31:45.329062 Dram Type= 6, Freq= 0, CH_0, rank 1
5335 23:31:45.332200 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5336 23:31:45.332775 ==
5337 23:31:45.335391 Write leveling (Byte 0): 31 => 31
5338 23:31:45.338526 Write leveling (Byte 1): 29 => 29
5339 23:31:45.341697 DramcWriteLeveling(PI) end<-----
5340 23:31:45.342160
5341 23:31:45.342526 ==
5342 23:31:45.344746 Dram Type= 6, Freq= 0, CH_0, rank 1
5343 23:31:45.348791 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5344 23:31:45.349362 ==
5345 23:31:45.351650 [Gating] SW mode calibration
5346 23:31:45.358435 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5347 23:31:45.365483 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5348 23:31:45.368901 0 14 0 | B1->B0 | 3333 3232 | 0 0 | (0 0) (0 0)
5349 23:31:45.375209 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5350 23:31:45.378379 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5351 23:31:45.381545 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5352 23:31:45.388513 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5353 23:31:45.391493 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5354 23:31:45.395011 0 14 24 | B1->B0 | 3333 3434 | 0 0 | (0 0) (0 0)
5355 23:31:45.401753 0 14 28 | B1->B0 | 2626 2929 | 0 0 | (0 0) (0 1)
5356 23:31:45.404504 0 15 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5357 23:31:45.407700 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5358 23:31:45.414691 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5359 23:31:45.417673 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5360 23:31:45.421222 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5361 23:31:45.427950 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5362 23:31:45.431270 0 15 24 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
5363 23:31:45.434670 0 15 28 | B1->B0 | 3a3a 3939 | 0 1 | (0 0) (0 0)
5364 23:31:45.441422 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5365 23:31:45.444366 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5366 23:31:45.447786 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5367 23:31:45.453994 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5368 23:31:45.457746 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5369 23:31:45.460946 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5370 23:31:45.467477 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5371 23:31:45.470560 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5372 23:31:45.474241 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5373 23:31:45.477715 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5374 23:31:45.484554 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5375 23:31:45.488190 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5376 23:31:45.491008 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5377 23:31:45.497708 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5378 23:31:45.501204 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5379 23:31:45.504534 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5380 23:31:45.510873 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5381 23:31:45.514150 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5382 23:31:45.517822 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5383 23:31:45.524078 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5384 23:31:45.527611 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5385 23:31:45.531061 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5386 23:31:45.537447 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5387 23:31:45.540619 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5388 23:31:45.544346 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5389 23:31:45.547450 Total UI for P1: 0, mck2ui 16
5390 23:31:45.550554 best dqsien dly found for B0: ( 1, 2, 28)
5391 23:31:45.554205 Total UI for P1: 0, mck2ui 16
5392 23:31:45.557511 best dqsien dly found for B1: ( 1, 2, 28)
5393 23:31:45.560793 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5394 23:31:45.564000 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5395 23:31:45.564575
5396 23:31:45.570669 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5397 23:31:45.573794 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5398 23:31:45.574259 [Gating] SW calibration Done
5399 23:31:45.577364 ==
5400 23:31:45.580389 Dram Type= 6, Freq= 0, CH_0, rank 1
5401 23:31:45.584236 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5402 23:31:45.584796 ==
5403 23:31:45.585166 RX Vref Scan: 0
5404 23:31:45.585707
5405 23:31:45.587174 RX Vref 0 -> 0, step: 1
5406 23:31:45.587635
5407 23:31:45.590578 RX Delay -80 -> 252, step: 8
5408 23:31:45.593627 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5409 23:31:45.597530 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5410 23:31:45.600533 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5411 23:31:45.607310 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5412 23:31:45.610272 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5413 23:31:45.614133 iDelay=208, Bit 5, Center 99 (8 ~ 191) 184
5414 23:31:45.616873 iDelay=208, Bit 6, Center 111 (24 ~ 199) 176
5415 23:31:45.620288 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5416 23:31:45.623672 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5417 23:31:45.630183 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5418 23:31:45.633713 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5419 23:31:45.637028 iDelay=208, Bit 11, Center 91 (8 ~ 175) 168
5420 23:31:45.640546 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5421 23:31:45.644201 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5422 23:31:45.647043 iDelay=208, Bit 14, Center 107 (24 ~ 191) 168
5423 23:31:45.653933 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5424 23:31:45.654479 ==
5425 23:31:45.656973 Dram Type= 6, Freq= 0, CH_0, rank 1
5426 23:31:45.660205 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5427 23:31:45.660672 ==
5428 23:31:45.661041 DQS Delay:
5429 23:31:45.663329 DQS0 = 0, DQS1 = 0
5430 23:31:45.663749 DQM Delay:
5431 23:31:45.666908 DQM0 = 105, DQM1 = 95
5432 23:31:45.667422 DQ Delay:
5433 23:31:45.670536 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5434 23:31:45.673930 DQ4 =107, DQ5 =99, DQ6 =111, DQ7 =115
5435 23:31:45.677210 DQ8 =87, DQ9 =87, DQ10 =95, DQ11 =91
5436 23:31:45.679982 DQ12 =99, DQ13 =99, DQ14 =107, DQ15 =99
5437 23:31:45.680399
5438 23:31:45.680728
5439 23:31:45.681037 ==
5440 23:31:45.683790 Dram Type= 6, Freq= 0, CH_0, rank 1
5441 23:31:45.690045 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5442 23:31:45.690563 ==
5443 23:31:45.690902
5444 23:31:45.691213
5445 23:31:45.691513 TX Vref Scan disable
5446 23:31:45.693270 == TX Byte 0 ==
5447 23:31:45.697134 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5448 23:31:45.699859 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5449 23:31:45.703375 == TX Byte 1 ==
5450 23:31:45.707079 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5451 23:31:45.713629 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5452 23:31:45.714162 ==
5453 23:31:45.717098 Dram Type= 6, Freq= 0, CH_0, rank 1
5454 23:31:45.720249 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5455 23:31:45.720778 ==
5456 23:31:45.721119
5457 23:31:45.721429
5458 23:31:45.723358 TX Vref Scan disable
5459 23:31:45.723907 == TX Byte 0 ==
5460 23:31:45.730134 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5461 23:31:45.733326 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5462 23:31:45.733960 == TX Byte 1 ==
5463 23:31:45.739926 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5464 23:31:45.743318 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5465 23:31:45.743738
5466 23:31:45.744070 [DATLAT]
5467 23:31:45.746664 Freq=933, CH0 RK1
5468 23:31:45.747086
5469 23:31:45.747419 DATLAT Default: 0xb
5470 23:31:45.749763 0, 0xFFFF, sum = 0
5471 23:31:45.750196 1, 0xFFFF, sum = 0
5472 23:31:45.753342 2, 0xFFFF, sum = 0
5473 23:31:45.753866 3, 0xFFFF, sum = 0
5474 23:31:45.756808 4, 0xFFFF, sum = 0
5475 23:31:45.757336 5, 0xFFFF, sum = 0
5476 23:31:45.759741 6, 0xFFFF, sum = 0
5477 23:31:45.760264 7, 0xFFFF, sum = 0
5478 23:31:45.763521 8, 0xFFFF, sum = 0
5479 23:31:45.766538 9, 0xFFFF, sum = 0
5480 23:31:45.767059 10, 0x0, sum = 1
5481 23:31:45.767405 11, 0x0, sum = 2
5482 23:31:45.769968 12, 0x0, sum = 3
5483 23:31:45.770489 13, 0x0, sum = 4
5484 23:31:45.773185 best_step = 11
5485 23:31:45.773629
5486 23:31:45.773969 ==
5487 23:31:45.776532 Dram Type= 6, Freq= 0, CH_0, rank 1
5488 23:31:45.779738 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5489 23:31:45.780156 ==
5490 23:31:45.782853 RX Vref Scan: 0
5491 23:31:45.783267
5492 23:31:45.783600 RX Vref 0 -> 0, step: 1
5493 23:31:45.783908
5494 23:31:45.786036 RX Delay -45 -> 252, step: 4
5495 23:31:45.794087 iDelay=199, Bit 0, Center 102 (15 ~ 190) 176
5496 23:31:45.797515 iDelay=199, Bit 1, Center 108 (23 ~ 194) 172
5497 23:31:45.800816 iDelay=199, Bit 2, Center 102 (15 ~ 190) 176
5498 23:31:45.804428 iDelay=199, Bit 3, Center 102 (15 ~ 190) 176
5499 23:31:45.807322 iDelay=199, Bit 4, Center 106 (19 ~ 194) 176
5500 23:31:45.813986 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5501 23:31:45.817153 iDelay=199, Bit 6, Center 108 (23 ~ 194) 172
5502 23:31:45.820370 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5503 23:31:45.824005 iDelay=199, Bit 8, Center 86 (3 ~ 170) 168
5504 23:31:45.827196 iDelay=199, Bit 9, Center 86 (3 ~ 170) 168
5505 23:31:45.830564 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5506 23:31:45.836840 iDelay=199, Bit 11, Center 88 (7 ~ 170) 164
5507 23:31:45.840092 iDelay=199, Bit 12, Center 100 (19 ~ 182) 164
5508 23:31:45.843951 iDelay=199, Bit 13, Center 100 (15 ~ 186) 172
5509 23:31:45.847182 iDelay=199, Bit 14, Center 104 (19 ~ 190) 172
5510 23:31:45.854071 iDelay=199, Bit 15, Center 104 (23 ~ 186) 164
5511 23:31:45.854627 ==
5512 23:31:45.856788 Dram Type= 6, Freq= 0, CH_0, rank 1
5513 23:31:45.860462 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5514 23:31:45.861026 ==
5515 23:31:45.861391 DQS Delay:
5516 23:31:45.863633 DQS0 = 0, DQS1 = 0
5517 23:31:45.864191 DQM Delay:
5518 23:31:45.867173 DQM0 = 104, DQM1 = 95
5519 23:31:45.867737 DQ Delay:
5520 23:31:45.870417 DQ0 =102, DQ1 =108, DQ2 =102, DQ3 =102
5521 23:31:45.873659 DQ4 =106, DQ5 =98, DQ6 =108, DQ7 =112
5522 23:31:45.876968 DQ8 =86, DQ9 =86, DQ10 =94, DQ11 =88
5523 23:31:45.880128 DQ12 =100, DQ13 =100, DQ14 =104, DQ15 =104
5524 23:31:45.880594
5525 23:31:45.880957
5526 23:31:45.890153 [DQSOSCAuto] RK1, (LSB)MR18= 0x2801, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 409 ps
5527 23:31:45.890740 CH0 RK1: MR19=505, MR18=2801
5528 23:31:45.897110 CH0_RK1: MR19=0x505, MR18=0x2801, DQSOSC=409, MR23=63, INC=64, DEC=43
5529 23:31:45.900563 [RxdqsGatingPostProcess] freq 933
5530 23:31:45.906728 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5531 23:31:45.910290 best DQS0 dly(2T, 0.5T) = (0, 10)
5532 23:31:45.913893 best DQS1 dly(2T, 0.5T) = (0, 10)
5533 23:31:45.917264 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5534 23:31:45.919923 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5535 23:31:45.923944 best DQS0 dly(2T, 0.5T) = (0, 10)
5536 23:31:45.924503 best DQS1 dly(2T, 0.5T) = (0, 10)
5537 23:31:45.926875 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5538 23:31:45.930381 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5539 23:31:45.933693 Pre-setting of DQS Precalculation
5540 23:31:45.940179 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5541 23:31:45.940721 ==
5542 23:31:45.943348 Dram Type= 6, Freq= 0, CH_1, rank 0
5543 23:31:45.946786 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5544 23:31:45.947348 ==
5545 23:31:45.953297 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5546 23:31:45.959876 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5547 23:31:45.963894 [CA 0] Center 36 (6~67) winsize 62
5548 23:31:45.966493 [CA 1] Center 36 (6~67) winsize 62
5549 23:31:45.970351 [CA 2] Center 34 (4~65) winsize 62
5550 23:31:45.973358 [CA 3] Center 34 (4~65) winsize 62
5551 23:31:45.977081 [CA 4] Center 34 (4~64) winsize 61
5552 23:31:45.979842 [CA 5] Center 33 (3~64) winsize 62
5553 23:31:45.980310
5554 23:31:45.983945 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5555 23:31:45.984411
5556 23:31:45.986857 [CATrainingPosCal] consider 1 rank data
5557 23:31:45.990093 u2DelayCellTimex100 = 270/100 ps
5558 23:31:45.993425 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5559 23:31:45.996455 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5560 23:31:46.000118 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5561 23:31:46.003264 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5562 23:31:46.006486 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5563 23:31:46.010250 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5564 23:31:46.010717
5565 23:31:46.013456 CA PerBit enable=1, Macro0, CA PI delay=33
5566 23:31:46.014068
5567 23:31:46.016804 [CBTSetCACLKResult] CA Dly = 33
5568 23:31:46.020013 CS Dly: 7 (0~38)
5569 23:31:46.020477 ==
5570 23:31:46.023529 Dram Type= 6, Freq= 0, CH_1, rank 1
5571 23:31:46.026884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5572 23:31:46.027447 ==
5573 23:31:46.033178 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5574 23:31:46.040009 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5575 23:31:46.043187 [CA 0] Center 36 (6~67) winsize 62
5576 23:31:46.046365 [CA 1] Center 37 (6~68) winsize 63
5577 23:31:46.050285 [CA 2] Center 35 (5~65) winsize 61
5578 23:31:46.053404 [CA 3] Center 34 (4~65) winsize 62
5579 23:31:46.056765 [CA 4] Center 34 (4~65) winsize 62
5580 23:31:46.060499 [CA 5] Center 33 (3~64) winsize 62
5581 23:31:46.061052
5582 23:31:46.062747 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5583 23:31:46.063215
5584 23:31:46.066346 [CATrainingPosCal] consider 2 rank data
5585 23:31:46.069779 u2DelayCellTimex100 = 270/100 ps
5586 23:31:46.072777 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5587 23:31:46.076200 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5588 23:31:46.079285 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5589 23:31:46.082641 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5590 23:31:46.086203 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5591 23:31:46.089616 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5592 23:31:46.090042
5593 23:31:46.096104 CA PerBit enable=1, Macro0, CA PI delay=33
5594 23:31:46.096606
5595 23:31:46.096937 [CBTSetCACLKResult] CA Dly = 33
5596 23:31:46.099534 CS Dly: 8 (0~40)
5597 23:31:46.099949
5598 23:31:46.102589 ----->DramcWriteLeveling(PI) begin...
5599 23:31:46.103013 ==
5600 23:31:46.106018 Dram Type= 6, Freq= 0, CH_1, rank 0
5601 23:31:46.109570 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5602 23:31:46.110022 ==
5603 23:31:46.112753 Write leveling (Byte 0): 23 => 23
5604 23:31:46.116202 Write leveling (Byte 1): 29 => 29
5605 23:31:46.119228 DramcWriteLeveling(PI) end<-----
5606 23:31:46.119644
5607 23:31:46.119971 ==
5608 23:31:46.122589 Dram Type= 6, Freq= 0, CH_1, rank 0
5609 23:31:46.129286 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5610 23:31:46.129752 ==
5611 23:31:46.130092 [Gating] SW mode calibration
5612 23:31:46.139749 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5613 23:31:46.142347 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5614 23:31:46.146062 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5615 23:31:46.152664 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5616 23:31:46.155943 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5617 23:31:46.159330 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5618 23:31:46.166267 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5619 23:31:46.169494 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5620 23:31:46.172186 0 14 24 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (0 0)
5621 23:31:46.179069 0 14 28 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
5622 23:31:46.182193 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5623 23:31:46.185497 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5624 23:31:46.192283 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5625 23:31:46.195486 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5626 23:31:46.198745 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5627 23:31:46.205381 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5628 23:31:46.208584 0 15 24 | B1->B0 | 2424 3333 | 0 0 | (0 0) (0 0)
5629 23:31:46.212182 0 15 28 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
5630 23:31:46.218647 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5631 23:31:46.221818 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5632 23:31:46.225562 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5633 23:31:46.232222 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5634 23:31:46.235120 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5635 23:31:46.238520 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5636 23:31:46.244995 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5637 23:31:46.248697 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5638 23:31:46.251787 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5639 23:31:46.258375 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5640 23:31:46.261561 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5641 23:31:46.265358 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5642 23:31:46.271726 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5643 23:31:46.275171 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5644 23:31:46.278179 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5645 23:31:46.284898 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5646 23:31:46.288516 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5647 23:31:46.291640 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5648 23:31:46.298367 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5649 23:31:46.301814 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5650 23:31:46.304862 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5651 23:31:46.311401 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5652 23:31:46.314866 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5653 23:31:46.317792 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5654 23:31:46.321475 Total UI for P1: 0, mck2ui 16
5655 23:31:46.324726 best dqsien dly found for B0: ( 1, 2, 26)
5656 23:31:46.328259 Total UI for P1: 0, mck2ui 16
5657 23:31:46.331328 best dqsien dly found for B1: ( 1, 2, 24)
5658 23:31:46.334818 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5659 23:31:46.338213 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5660 23:31:46.338776
5661 23:31:46.341327 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5662 23:31:46.348133 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5663 23:31:46.348743 [Gating] SW calibration Done
5664 23:31:46.349276 ==
5665 23:31:46.351051 Dram Type= 6, Freq= 0, CH_1, rank 0
5666 23:31:46.357871 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5667 23:31:46.358432 ==
5668 23:31:46.358968 RX Vref Scan: 0
5669 23:31:46.359460
5670 23:31:46.361276 RX Vref 0 -> 0, step: 1
5671 23:31:46.361816
5672 23:31:46.364525 RX Delay -80 -> 252, step: 8
5673 23:31:46.368079 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5674 23:31:46.371007 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5675 23:31:46.374795 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5676 23:31:46.378090 iDelay=208, Bit 3, Center 103 (16 ~ 191) 176
5677 23:31:46.384446 iDelay=208, Bit 4, Center 103 (16 ~ 191) 176
5678 23:31:46.387666 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5679 23:31:46.390751 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5680 23:31:46.394559 iDelay=208, Bit 7, Center 107 (16 ~ 199) 184
5681 23:31:46.397609 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5682 23:31:46.404427 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5683 23:31:46.407741 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5684 23:31:46.411081 iDelay=208, Bit 11, Center 95 (8 ~ 183) 176
5685 23:31:46.414402 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5686 23:31:46.417544 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5687 23:31:46.421084 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5688 23:31:46.427768 iDelay=208, Bit 15, Center 103 (16 ~ 191) 176
5689 23:31:46.428323 ==
5690 23:31:46.431028 Dram Type= 6, Freq= 0, CH_1, rank 0
5691 23:31:46.434789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5692 23:31:46.435354 ==
5693 23:31:46.435731 DQS Delay:
5694 23:31:46.438212 DQS0 = 0, DQS1 = 0
5695 23:31:46.438766 DQM Delay:
5696 23:31:46.440970 DQM0 = 103, DQM1 = 98
5697 23:31:46.441444 DQ Delay:
5698 23:31:46.444549 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =103
5699 23:31:46.447919 DQ4 =103, DQ5 =111, DQ6 =111, DQ7 =107
5700 23:31:46.451291 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =95
5701 23:31:46.454497 DQ12 =107, DQ13 =103, DQ14 =103, DQ15 =103
5702 23:31:46.454963
5703 23:31:46.455329
5704 23:31:46.457867 ==
5705 23:31:46.458438 Dram Type= 6, Freq= 0, CH_1, rank 0
5706 23:31:46.464121 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5707 23:31:46.464678 ==
5708 23:31:46.465048
5709 23:31:46.465436
5710 23:31:46.467633 TX Vref Scan disable
5711 23:31:46.468187 == TX Byte 0 ==
5712 23:31:46.470807 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5713 23:31:46.477741 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5714 23:31:46.478215 == TX Byte 1 ==
5715 23:31:46.480641 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5716 23:31:46.487102 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5717 23:31:46.487653 ==
5718 23:31:46.490773 Dram Type= 6, Freq= 0, CH_1, rank 0
5719 23:31:46.494012 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5720 23:31:46.494429 ==
5721 23:31:46.494871
5722 23:31:46.495265
5723 23:31:46.497177 TX Vref Scan disable
5724 23:31:46.500720 == TX Byte 0 ==
5725 23:31:46.504135 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5726 23:31:46.507367 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5727 23:31:46.510972 == TX Byte 1 ==
5728 23:31:46.513870 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5729 23:31:46.517161 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5730 23:31:46.517616
5731 23:31:46.517967 [DATLAT]
5732 23:31:46.520272 Freq=933, CH1 RK0
5733 23:31:46.520689
5734 23:31:46.523964 DATLAT Default: 0xd
5735 23:31:46.524380 0, 0xFFFF, sum = 0
5736 23:31:46.527041 1, 0xFFFF, sum = 0
5737 23:31:46.527462 2, 0xFFFF, sum = 0
5738 23:31:46.530353 3, 0xFFFF, sum = 0
5739 23:31:46.530790 4, 0xFFFF, sum = 0
5740 23:31:46.534146 5, 0xFFFF, sum = 0
5741 23:31:46.534576 6, 0xFFFF, sum = 0
5742 23:31:46.537274 7, 0xFFFF, sum = 0
5743 23:31:46.537849 8, 0xFFFF, sum = 0
5744 23:31:46.541009 9, 0xFFFF, sum = 0
5745 23:31:46.541542 10, 0x0, sum = 1
5746 23:31:46.544371 11, 0x0, sum = 2
5747 23:31:46.544933 12, 0x0, sum = 3
5748 23:31:46.546981 13, 0x0, sum = 4
5749 23:31:46.547409 best_step = 11
5750 23:31:46.547740
5751 23:31:46.548053 ==
5752 23:31:46.550300 Dram Type= 6, Freq= 0, CH_1, rank 0
5753 23:31:46.553669 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5754 23:31:46.554092 ==
5755 23:31:46.557411 RX Vref Scan: 1
5756 23:31:46.557974
5757 23:31:46.560646 RX Vref 0 -> 0, step: 1
5758 23:31:46.561157
5759 23:31:46.561493 RX Delay -45 -> 252, step: 4
5760 23:31:46.564236
5761 23:31:46.564745 Set Vref, RX VrefLevel [Byte0]: 55
5762 23:31:46.567098 [Byte1]: 52
5763 23:31:46.571991
5764 23:31:46.572510 Final RX Vref Byte 0 = 55 to rank0
5765 23:31:46.575261 Final RX Vref Byte 1 = 52 to rank0
5766 23:31:46.578541 Final RX Vref Byte 0 = 55 to rank1
5767 23:31:46.581862 Final RX Vref Byte 1 = 52 to rank1==
5768 23:31:46.585016 Dram Type= 6, Freq= 0, CH_1, rank 0
5769 23:31:46.592165 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5770 23:31:46.592687 ==
5771 23:31:46.593025 DQS Delay:
5772 23:31:46.593339 DQS0 = 0, DQS1 = 0
5773 23:31:46.595315 DQM Delay:
5774 23:31:46.595729 DQM0 = 103, DQM1 = 99
5775 23:31:46.598601 DQ Delay:
5776 23:31:46.601853 DQ0 =106, DQ1 =98, DQ2 =94, DQ3 =102
5777 23:31:46.605693 DQ4 =102, DQ5 =112, DQ6 =112, DQ7 =104
5778 23:31:46.608880 DQ8 =90, DQ9 =92, DQ10 =100, DQ11 =92
5779 23:31:46.611771 DQ12 =106, DQ13 =102, DQ14 =106, DQ15 =106
5780 23:31:46.612189
5781 23:31:46.612520
5782 23:31:46.618870 [DQSOSCAuto] RK0, (LSB)MR18= 0x172e, (MSB)MR19= 0x505, tDQSOscB0 = 407 ps tDQSOscB1 = 414 ps
5783 23:31:46.622523 CH1 RK0: MR19=505, MR18=172E
5784 23:31:46.628831 CH1_RK0: MR19=0x505, MR18=0x172E, DQSOSC=407, MR23=63, INC=65, DEC=43
5785 23:31:46.629252
5786 23:31:46.631820 ----->DramcWriteLeveling(PI) begin...
5787 23:31:46.632241 ==
5788 23:31:46.635631 Dram Type= 6, Freq= 0, CH_1, rank 1
5789 23:31:46.638622 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5790 23:31:46.639046 ==
5791 23:31:46.641833 Write leveling (Byte 0): 27 => 27
5792 23:31:46.645573 Write leveling (Byte 1): 27 => 27
5793 23:31:46.648897 DramcWriteLeveling(PI) end<-----
5794 23:31:46.649447
5795 23:31:46.649863 ==
5796 23:31:46.652264 Dram Type= 6, Freq= 0, CH_1, rank 1
5797 23:31:46.655126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5798 23:31:46.658553 ==
5799 23:31:46.659043 [Gating] SW mode calibration
5800 23:31:46.665628 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5801 23:31:46.672445 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5802 23:31:46.675739 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5803 23:31:46.681987 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5804 23:31:46.684899 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5805 23:31:46.688278 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5806 23:31:46.695322 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5807 23:31:46.698529 0 14 20 | B1->B0 | 3333 3434 | 1 1 | (1 0) (1 1)
5808 23:31:46.702001 0 14 24 | B1->B0 | 2b2b 3232 | 1 1 | (1 0) (1 1)
5809 23:31:46.708494 0 14 28 | B1->B0 | 2323 2828 | 0 0 | (0 0) (1 0)
5810 23:31:46.712051 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5811 23:31:46.715277 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5812 23:31:46.721968 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5813 23:31:46.725328 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5814 23:31:46.728609 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5815 23:31:46.735245 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5816 23:31:46.738106 0 15 24 | B1->B0 | 3434 2929 | 0 0 | (0 0) (1 1)
5817 23:31:46.741449 0 15 28 | B1->B0 | 4646 4242 | 0 0 | (0 0) (0 0)
5818 23:31:46.748431 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5819 23:31:46.751404 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5820 23:31:46.754521 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5821 23:31:46.761672 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5822 23:31:46.765058 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5823 23:31:46.768172 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5824 23:31:46.774615 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5825 23:31:46.778144 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5826 23:31:46.781544 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5827 23:31:46.788006 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5828 23:31:46.791386 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5829 23:31:46.794611 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5830 23:31:46.798017 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5831 23:31:46.805020 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5832 23:31:46.808205 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5833 23:31:46.811596 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5834 23:31:46.818005 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5835 23:31:46.821299 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5836 23:31:46.824468 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5837 23:31:46.830838 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5838 23:31:46.834801 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5839 23:31:46.838059 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5840 23:31:46.844554 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5841 23:31:46.847768 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5842 23:31:46.851100 Total UI for P1: 0, mck2ui 16
5843 23:31:46.854294 best dqsien dly found for B0: ( 1, 2, 24)
5844 23:31:46.857796 Total UI for P1: 0, mck2ui 16
5845 23:31:46.861368 best dqsien dly found for B1: ( 1, 2, 24)
5846 23:31:46.864270 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5847 23:31:46.867495 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5848 23:31:46.868055
5849 23:31:46.870989 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5850 23:31:46.874598 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5851 23:31:46.878055 [Gating] SW calibration Done
5852 23:31:46.878613 ==
5853 23:31:46.880999 Dram Type= 6, Freq= 0, CH_1, rank 1
5854 23:31:46.887569 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5855 23:31:46.888135 ==
5856 23:31:46.888508 RX Vref Scan: 0
5857 23:31:46.888848
5858 23:31:46.890804 RX Vref 0 -> 0, step: 1
5859 23:31:46.891344
5860 23:31:46.894059 RX Delay -80 -> 252, step: 8
5861 23:31:46.897723 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5862 23:31:46.900604 iDelay=208, Bit 1, Center 103 (16 ~ 191) 176
5863 23:31:46.904155 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5864 23:31:46.906850 iDelay=208, Bit 3, Center 103 (16 ~ 191) 176
5865 23:31:46.914515 iDelay=208, Bit 4, Center 99 (16 ~ 183) 168
5866 23:31:46.917232 iDelay=208, Bit 5, Center 119 (32 ~ 207) 176
5867 23:31:46.920692 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5868 23:31:46.924061 iDelay=208, Bit 7, Center 103 (16 ~ 191) 176
5869 23:31:46.927372 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5870 23:31:46.930476 iDelay=208, Bit 9, Center 91 (0 ~ 183) 184
5871 23:31:46.937076 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5872 23:31:46.940219 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5873 23:31:46.943700 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5874 23:31:46.946824 iDelay=208, Bit 13, Center 107 (16 ~ 199) 184
5875 23:31:46.953545 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5876 23:31:46.957239 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5877 23:31:46.957844 ==
5878 23:31:46.960189 Dram Type= 6, Freq= 0, CH_1, rank 1
5879 23:31:46.963322 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5880 23:31:46.963787 ==
5881 23:31:46.964155 DQS Delay:
5882 23:31:46.967567 DQS0 = 0, DQS1 = 0
5883 23:31:46.968123 DQM Delay:
5884 23:31:46.970180 DQM0 = 105, DQM1 = 99
5885 23:31:46.970639 DQ Delay:
5886 23:31:46.973497 DQ0 =107, DQ1 =103, DQ2 =91, DQ3 =103
5887 23:31:46.977055 DQ4 =99, DQ5 =119, DQ6 =115, DQ7 =103
5888 23:31:46.980401 DQ8 =87, DQ9 =91, DQ10 =99, DQ11 =91
5889 23:31:46.983646 DQ12 =107, DQ13 =107, DQ14 =103, DQ15 =107
5890 23:31:46.984105
5891 23:31:46.984469
5892 23:31:46.984807 ==
5893 23:31:46.986957 Dram Type= 6, Freq= 0, CH_1, rank 1
5894 23:31:46.993500 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5895 23:31:46.994115 ==
5896 23:31:46.994485
5897 23:31:46.994823
5898 23:31:46.996917 TX Vref Scan disable
5899 23:31:46.997469 == TX Byte 0 ==
5900 23:31:47.000453 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5901 23:31:47.006883 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5902 23:31:47.007529 == TX Byte 1 ==
5903 23:31:47.010279 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5904 23:31:47.016675 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5905 23:31:47.017234 ==
5906 23:31:47.020161 Dram Type= 6, Freq= 0, CH_1, rank 1
5907 23:31:47.023166 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5908 23:31:47.023671 ==
5909 23:31:47.024040
5910 23:31:47.024379
5911 23:31:47.026488 TX Vref Scan disable
5912 23:31:47.030339 == TX Byte 0 ==
5913 23:31:47.033532 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5914 23:31:47.037152 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5915 23:31:47.040226 == TX Byte 1 ==
5916 23:31:47.043402 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5917 23:31:47.046524 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5918 23:31:47.047082
5919 23:31:47.047485 [DATLAT]
5920 23:31:47.049739 Freq=933, CH1 RK1
5921 23:31:47.050300
5922 23:31:47.053147 DATLAT Default: 0xb
5923 23:31:47.053743 0, 0xFFFF, sum = 0
5924 23:31:47.056341 1, 0xFFFF, sum = 0
5925 23:31:47.056804 2, 0xFFFF, sum = 0
5926 23:31:47.059900 3, 0xFFFF, sum = 0
5927 23:31:47.060379 4, 0xFFFF, sum = 0
5928 23:31:47.062848 5, 0xFFFF, sum = 0
5929 23:31:47.063340 6, 0xFFFF, sum = 0
5930 23:31:47.066748 7, 0xFFFF, sum = 0
5931 23:31:47.067384 8, 0xFFFF, sum = 0
5932 23:31:47.069685 9, 0xFFFF, sum = 0
5933 23:31:47.070152 10, 0x0, sum = 1
5934 23:31:47.073294 11, 0x0, sum = 2
5935 23:31:47.073908 12, 0x0, sum = 3
5936 23:31:47.076579 13, 0x0, sum = 4
5937 23:31:47.077140 best_step = 11
5938 23:31:47.077506
5939 23:31:47.077911 ==
5940 23:31:47.079662 Dram Type= 6, Freq= 0, CH_1, rank 1
5941 23:31:47.083251 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5942 23:31:47.083816 ==
5943 23:31:47.086223 RX Vref Scan: 0
5944 23:31:47.086680
5945 23:31:47.089770 RX Vref 0 -> 0, step: 1
5946 23:31:47.090228
5947 23:31:47.090589 RX Delay -45 -> 252, step: 4
5948 23:31:47.097474 iDelay=203, Bit 0, Center 110 (27 ~ 194) 168
5949 23:31:47.101147 iDelay=203, Bit 1, Center 100 (15 ~ 186) 172
5950 23:31:47.104537 iDelay=203, Bit 2, Center 94 (11 ~ 178) 168
5951 23:31:47.108034 iDelay=203, Bit 3, Center 100 (19 ~ 182) 164
5952 23:31:47.111444 iDelay=203, Bit 4, Center 100 (19 ~ 182) 164
5953 23:31:47.118412 iDelay=203, Bit 5, Center 118 (35 ~ 202) 168
5954 23:31:47.121187 iDelay=203, Bit 6, Center 114 (31 ~ 198) 168
5955 23:31:47.124549 iDelay=203, Bit 7, Center 104 (19 ~ 190) 172
5956 23:31:47.127307 iDelay=203, Bit 8, Center 88 (3 ~ 174) 172
5957 23:31:47.131158 iDelay=203, Bit 9, Center 90 (3 ~ 178) 176
5958 23:31:47.134233 iDelay=203, Bit 10, Center 98 (11 ~ 186) 176
5959 23:31:47.141273 iDelay=203, Bit 11, Center 92 (7 ~ 178) 172
5960 23:31:47.144120 iDelay=203, Bit 12, Center 108 (19 ~ 198) 180
5961 23:31:47.147741 iDelay=203, Bit 13, Center 104 (19 ~ 190) 172
5962 23:31:47.151098 iDelay=203, Bit 14, Center 102 (19 ~ 186) 168
5963 23:31:47.157802 iDelay=203, Bit 15, Center 106 (19 ~ 194) 176
5964 23:31:47.158381 ==
5965 23:31:47.161220 Dram Type= 6, Freq= 0, CH_1, rank 1
5966 23:31:47.164085 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5967 23:31:47.164651 ==
5968 23:31:47.165022 DQS Delay:
5969 23:31:47.167698 DQS0 = 0, DQS1 = 0
5970 23:31:47.168273 DQM Delay:
5971 23:31:47.170535 DQM0 = 105, DQM1 = 98
5972 23:31:47.170996 DQ Delay:
5973 23:31:47.174140 DQ0 =110, DQ1 =100, DQ2 =94, DQ3 =100
5974 23:31:47.177242 DQ4 =100, DQ5 =118, DQ6 =114, DQ7 =104
5975 23:31:47.181184 DQ8 =88, DQ9 =90, DQ10 =98, DQ11 =92
5976 23:31:47.183814 DQ12 =108, DQ13 =104, DQ14 =102, DQ15 =106
5977 23:31:47.184290
5978 23:31:47.184649
5979 23:31:47.194109 [DQSOSCAuto] RK1, (LSB)MR18= 0x29fc, (MSB)MR19= 0x504, tDQSOscB0 = 423 ps tDQSOscB1 = 408 ps
5980 23:31:47.194841 CH1 RK1: MR19=504, MR18=29FC
5981 23:31:47.200698 CH1_RK1: MR19=0x504, MR18=0x29FC, DQSOSC=408, MR23=63, INC=65, DEC=43
5982 23:31:47.203951 [RxdqsGatingPostProcess] freq 933
5983 23:31:47.210381 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5984 23:31:47.214265 best DQS0 dly(2T, 0.5T) = (0, 10)
5985 23:31:47.217259 best DQS1 dly(2T, 0.5T) = (0, 10)
5986 23:31:47.220878 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5987 23:31:47.224002 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5988 23:31:47.227191 best DQS0 dly(2T, 0.5T) = (0, 10)
5989 23:31:47.230156 best DQS1 dly(2T, 0.5T) = (0, 10)
5990 23:31:47.233474 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5991 23:31:47.236924 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5992 23:31:47.237400 Pre-setting of DQS Precalculation
5993 23:31:47.243405 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5994 23:31:47.250352 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5995 23:31:47.257053 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5996 23:31:47.257644
5997 23:31:47.258016
5998 23:31:47.260210 [Calibration Summary] 1866 Mbps
5999 23:31:47.263532 CH 0, Rank 0
6000 23:31:47.263989 SW Impedance : PASS
6001 23:31:47.266916 DUTY Scan : NO K
6002 23:31:47.270114 ZQ Calibration : PASS
6003 23:31:47.270575 Jitter Meter : NO K
6004 23:31:47.273787 CBT Training : PASS
6005 23:31:47.274351 Write leveling : PASS
6006 23:31:47.276776 RX DQS gating : PASS
6007 23:31:47.279939 RX DQ/DQS(RDDQC) : PASS
6008 23:31:47.280380 TX DQ/DQS : PASS
6009 23:31:47.283655 RX DATLAT : PASS
6010 23:31:47.286739 RX DQ/DQS(Engine): PASS
6011 23:31:47.287172 TX OE : NO K
6012 23:31:47.290135 All Pass.
6013 23:31:47.290564
6014 23:31:47.290893 CH 0, Rank 1
6015 23:31:47.292994 SW Impedance : PASS
6016 23:31:47.293407 DUTY Scan : NO K
6017 23:31:47.296327 ZQ Calibration : PASS
6018 23:31:47.299956 Jitter Meter : NO K
6019 23:31:47.300479 CBT Training : PASS
6020 23:31:47.302947 Write leveling : PASS
6021 23:31:47.306460 RX DQS gating : PASS
6022 23:31:47.306985 RX DQ/DQS(RDDQC) : PASS
6023 23:31:47.309926 TX DQ/DQS : PASS
6024 23:31:47.312982 RX DATLAT : PASS
6025 23:31:47.313398 RX DQ/DQS(Engine): PASS
6026 23:31:47.316796 TX OE : NO K
6027 23:31:47.317320 All Pass.
6028 23:31:47.317713
6029 23:31:47.319948 CH 1, Rank 0
6030 23:31:47.320497 SW Impedance : PASS
6031 23:31:47.323150 DUTY Scan : NO K
6032 23:31:47.326443 ZQ Calibration : PASS
6033 23:31:47.326866 Jitter Meter : NO K
6034 23:31:47.329941 CBT Training : PASS
6035 23:31:47.333312 Write leveling : PASS
6036 23:31:47.333904 RX DQS gating : PASS
6037 23:31:47.336564 RX DQ/DQS(RDDQC) : PASS
6038 23:31:47.337118 TX DQ/DQS : PASS
6039 23:31:47.340300 RX DATLAT : PASS
6040 23:31:47.343201 RX DQ/DQS(Engine): PASS
6041 23:31:47.343619 TX OE : NO K
6042 23:31:47.346656 All Pass.
6043 23:31:47.347076
6044 23:31:47.347408 CH 1, Rank 1
6045 23:31:47.349383 SW Impedance : PASS
6046 23:31:47.349827 DUTY Scan : NO K
6047 23:31:47.353235 ZQ Calibration : PASS
6048 23:31:47.356029 Jitter Meter : NO K
6049 23:31:47.356447 CBT Training : PASS
6050 23:31:47.359588 Write leveling : PASS
6051 23:31:47.362968 RX DQS gating : PASS
6052 23:31:47.363384 RX DQ/DQS(RDDQC) : PASS
6053 23:31:47.366047 TX DQ/DQS : PASS
6054 23:31:47.369941 RX DATLAT : PASS
6055 23:31:47.370357 RX DQ/DQS(Engine): PASS
6056 23:31:47.373188 TX OE : NO K
6057 23:31:47.373632 All Pass.
6058 23:31:47.373969
6059 23:31:47.375898 DramC Write-DBI off
6060 23:31:47.379640 PER_BANK_REFRESH: Hybrid Mode
6061 23:31:47.380167 TX_TRACKING: ON
6062 23:31:47.389698 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6063 23:31:47.392690 [FAST_K] Save calibration result to emmc
6064 23:31:47.396153 dramc_set_vcore_voltage set vcore to 650000
6065 23:31:47.399050 Read voltage for 400, 6
6066 23:31:47.399509 Vio18 = 0
6067 23:31:47.399874 Vcore = 650000
6068 23:31:47.402565 Vdram = 0
6069 23:31:47.403153 Vddq = 0
6070 23:31:47.403522 Vmddr = 0
6071 23:31:47.409463 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6072 23:31:47.412974 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6073 23:31:47.416178 MEM_TYPE=3, freq_sel=20
6074 23:31:47.419699 sv_algorithm_assistance_LP4_800
6075 23:31:47.422426 ============ PULL DRAM RESETB DOWN ============
6076 23:31:47.425776 ========== PULL DRAM RESETB DOWN end =========
6077 23:31:47.432312 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6078 23:31:47.436049 ===================================
6079 23:31:47.436467 LPDDR4 DRAM CONFIGURATION
6080 23:31:47.439468 ===================================
6081 23:31:47.442268 EX_ROW_EN[0] = 0x0
6082 23:31:47.445804 EX_ROW_EN[1] = 0x0
6083 23:31:47.446343 LP4Y_EN = 0x0
6084 23:31:47.449229 WORK_FSP = 0x0
6085 23:31:47.449691 WL = 0x2
6086 23:31:47.452436 RL = 0x2
6087 23:31:47.452959 BL = 0x2
6088 23:31:47.456120 RPST = 0x0
6089 23:31:47.456691 RD_PRE = 0x0
6090 23:31:47.458733 WR_PRE = 0x1
6091 23:31:47.459206 WR_PST = 0x0
6092 23:31:47.462433 DBI_WR = 0x0
6093 23:31:47.462851 DBI_RD = 0x0
6094 23:31:47.465791 OTF = 0x1
6095 23:31:47.469407 ===================================
6096 23:31:47.472735 ===================================
6097 23:31:47.473261 ANA top config
6098 23:31:47.475969 ===================================
6099 23:31:47.479101 DLL_ASYNC_EN = 0
6100 23:31:47.482829 ALL_SLAVE_EN = 1
6101 23:31:47.485762 NEW_RANK_MODE = 1
6102 23:31:47.486180 DLL_IDLE_MODE = 1
6103 23:31:47.488920 LP45_APHY_COMB_EN = 1
6104 23:31:47.492086 TX_ODT_DIS = 1
6105 23:31:47.495761 NEW_8X_MODE = 1
6106 23:31:47.498685 ===================================
6107 23:31:47.502209 ===================================
6108 23:31:47.506198 data_rate = 800
6109 23:31:47.506762 CKR = 1
6110 23:31:47.508682 DQ_P2S_RATIO = 4
6111 23:31:47.512686 ===================================
6112 23:31:47.515361 CA_P2S_RATIO = 4
6113 23:31:47.519042 DQ_CA_OPEN = 0
6114 23:31:47.522187 DQ_SEMI_OPEN = 1
6115 23:31:47.525791 CA_SEMI_OPEN = 1
6116 23:31:47.526252 CA_FULL_RATE = 0
6117 23:31:47.529149 DQ_CKDIV4_EN = 0
6118 23:31:47.531928 CA_CKDIV4_EN = 1
6119 23:31:47.535370 CA_PREDIV_EN = 0
6120 23:31:47.538737 PH8_DLY = 0
6121 23:31:47.541918 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6122 23:31:47.542338 DQ_AAMCK_DIV = 0
6123 23:31:47.545084 CA_AAMCK_DIV = 0
6124 23:31:47.548212 CA_ADMCK_DIV = 4
6125 23:31:47.551987 DQ_TRACK_CA_EN = 0
6126 23:31:47.555057 CA_PICK = 800
6127 23:31:47.558448 CA_MCKIO = 400
6128 23:31:47.558864 MCKIO_SEMI = 400
6129 23:31:47.561747 PLL_FREQ = 3016
6130 23:31:47.565311 DQ_UI_PI_RATIO = 32
6131 23:31:47.569104 CA_UI_PI_RATIO = 32
6132 23:31:47.572257 ===================================
6133 23:31:47.575206 ===================================
6134 23:31:47.578507 memory_type:LPDDR4
6135 23:31:47.578923 GP_NUM : 10
6136 23:31:47.582171 SRAM_EN : 1
6137 23:31:47.585348 MD32_EN : 0
6138 23:31:47.588793 ===================================
6139 23:31:47.589245 [ANA_INIT] >>>>>>>>>>>>>>
6140 23:31:47.591492 <<<<<< [CONFIGURE PHASE]: ANA_TX
6141 23:31:47.595005 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6142 23:31:47.598027 ===================================
6143 23:31:47.602025 data_rate = 800,PCW = 0X7400
6144 23:31:47.605243 ===================================
6145 23:31:47.608259 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6146 23:31:47.615004 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6147 23:31:47.625205 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6148 23:31:47.632013 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6149 23:31:47.635174 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6150 23:31:47.638071 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6151 23:31:47.638601 [ANA_INIT] flow start
6152 23:31:47.641451 [ANA_INIT] PLL >>>>>>>>
6153 23:31:47.644707 [ANA_INIT] PLL <<<<<<<<
6154 23:31:47.645268 [ANA_INIT] MIDPI >>>>>>>>
6155 23:31:47.647937 [ANA_INIT] MIDPI <<<<<<<<
6156 23:31:47.651748 [ANA_INIT] DLL >>>>>>>>
6157 23:31:47.652333 [ANA_INIT] flow end
6158 23:31:47.658386 ============ LP4 DIFF to SE enter ============
6159 23:31:47.661732 ============ LP4 DIFF to SE exit ============
6160 23:31:47.664996 [ANA_INIT] <<<<<<<<<<<<<
6161 23:31:47.668185 [Flow] Enable top DCM control >>>>>
6162 23:31:47.671627 [Flow] Enable top DCM control <<<<<
6163 23:31:47.672200 Enable DLL master slave shuffle
6164 23:31:47.678012 ==============================================================
6165 23:31:47.681265 Gating Mode config
6166 23:31:47.684689 ==============================================================
6167 23:31:47.687721 Config description:
6168 23:31:47.698414 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6169 23:31:47.704908 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6170 23:31:47.708664 SELPH_MODE 0: By rank 1: By Phase
6171 23:31:47.714744 ==============================================================
6172 23:31:47.717916 GAT_TRACK_EN = 0
6173 23:31:47.721506 RX_GATING_MODE = 2
6174 23:31:47.725091 RX_GATING_TRACK_MODE = 2
6175 23:31:47.725729 SELPH_MODE = 1
6176 23:31:47.728331 PICG_EARLY_EN = 1
6177 23:31:47.731002 VALID_LAT_VALUE = 1
6178 23:31:47.738040 ==============================================================
6179 23:31:47.741260 Enter into Gating configuration >>>>
6180 23:31:47.744336 Exit from Gating configuration <<<<
6181 23:31:47.747973 Enter into DVFS_PRE_config >>>>>
6182 23:31:47.758032 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6183 23:31:47.761562 Exit from DVFS_PRE_config <<<<<
6184 23:31:47.764613 Enter into PICG configuration >>>>
6185 23:31:47.768046 Exit from PICG configuration <<<<
6186 23:31:47.771593 [RX_INPUT] configuration >>>>>
6187 23:31:47.774362 [RX_INPUT] configuration <<<<<
6188 23:31:47.777988 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6189 23:31:47.784776 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6190 23:31:47.791774 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6191 23:31:47.797971 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6192 23:31:47.800804 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6193 23:31:47.807828 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6194 23:31:47.814364 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6195 23:31:47.817290 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6196 23:31:47.821171 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6197 23:31:47.824138 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6198 23:31:47.827803 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6199 23:31:47.834185 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6200 23:31:47.837631 ===================================
6201 23:31:47.841471 LPDDR4 DRAM CONFIGURATION
6202 23:31:47.843998 ===================================
6203 23:31:47.844525 EX_ROW_EN[0] = 0x0
6204 23:31:47.847357 EX_ROW_EN[1] = 0x0
6205 23:31:47.847819 LP4Y_EN = 0x0
6206 23:31:47.850971 WORK_FSP = 0x0
6207 23:31:47.851536 WL = 0x2
6208 23:31:47.854227 RL = 0x2
6209 23:31:47.854813 BL = 0x2
6210 23:31:47.857024 RPST = 0x0
6211 23:31:47.857490 RD_PRE = 0x0
6212 23:31:47.860664 WR_PRE = 0x1
6213 23:31:47.861231 WR_PST = 0x0
6214 23:31:47.864100 DBI_WR = 0x0
6215 23:31:47.864668 DBI_RD = 0x0
6216 23:31:47.867213 OTF = 0x1
6217 23:31:47.870857 ===================================
6218 23:31:47.873825 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6219 23:31:47.877010 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6220 23:31:47.883677 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6221 23:31:47.886951 ===================================
6222 23:31:47.890505 LPDDR4 DRAM CONFIGURATION
6223 23:31:47.893539 ===================================
6224 23:31:47.894046 EX_ROW_EN[0] = 0x10
6225 23:31:47.896968 EX_ROW_EN[1] = 0x0
6226 23:31:47.897484 LP4Y_EN = 0x0
6227 23:31:47.900657 WORK_FSP = 0x0
6228 23:31:47.901216 WL = 0x2
6229 23:31:47.903490 RL = 0x2
6230 23:31:47.903944 BL = 0x2
6231 23:31:47.906804 RPST = 0x0
6232 23:31:47.907262 RD_PRE = 0x0
6233 23:31:47.910200 WR_PRE = 0x1
6234 23:31:47.910658 WR_PST = 0x0
6235 23:31:47.913796 DBI_WR = 0x0
6236 23:31:47.917001 DBI_RD = 0x0
6237 23:31:47.917458 OTF = 0x1
6238 23:31:47.920359 ===================================
6239 23:31:47.926518 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6240 23:31:47.929924 nWR fixed to 30
6241 23:31:47.933242 [ModeRegInit_LP4] CH0 RK0
6242 23:31:47.933745 [ModeRegInit_LP4] CH0 RK1
6243 23:31:47.936726 [ModeRegInit_LP4] CH1 RK0
6244 23:31:47.940033 [ModeRegInit_LP4] CH1 RK1
6245 23:31:47.940544 match AC timing 19
6246 23:31:47.946802 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6247 23:31:47.950214 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6248 23:31:47.953452 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6249 23:31:47.960146 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6250 23:31:47.963597 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6251 23:31:47.964115 ==
6252 23:31:47.966786 Dram Type= 6, Freq= 0, CH_0, rank 0
6253 23:31:47.970439 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6254 23:31:47.970956 ==
6255 23:31:47.977117 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6256 23:31:47.983235 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6257 23:31:47.986664 [CA 0] Center 36 (8~64) winsize 57
6258 23:31:47.990005 [CA 1] Center 36 (8~64) winsize 57
6259 23:31:47.993515 [CA 2] Center 36 (8~64) winsize 57
6260 23:31:47.993978 [CA 3] Center 36 (8~64) winsize 57
6261 23:31:47.996628 [CA 4] Center 36 (8~64) winsize 57
6262 23:31:47.999731 [CA 5] Center 36 (8~64) winsize 57
6263 23:31:48.000163
6264 23:31:48.006080 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6265 23:31:48.006774
6266 23:31:48.009485 [CATrainingPosCal] consider 1 rank data
6267 23:31:48.013024 u2DelayCellTimex100 = 270/100 ps
6268 23:31:48.016413 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6269 23:31:48.019774 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6270 23:31:48.022957 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6271 23:31:48.026468 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6272 23:31:48.029438 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6273 23:31:48.033160 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6274 23:31:48.033717
6275 23:31:48.036513 CA PerBit enable=1, Macro0, CA PI delay=36
6276 23:31:48.036925
6277 23:31:48.039754 [CBTSetCACLKResult] CA Dly = 36
6278 23:31:48.043224 CS Dly: 1 (0~32)
6279 23:31:48.043821 ==
6280 23:31:48.046227 Dram Type= 6, Freq= 0, CH_0, rank 1
6281 23:31:48.049742 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6282 23:31:48.050160 ==
6283 23:31:48.056296 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6284 23:31:48.059813 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6285 23:31:48.062847 [CA 0] Center 36 (8~64) winsize 57
6286 23:31:48.066167 [CA 1] Center 36 (8~64) winsize 57
6287 23:31:48.069554 [CA 2] Center 36 (8~64) winsize 57
6288 23:31:48.073020 [CA 3] Center 36 (8~64) winsize 57
6289 23:31:48.076613 [CA 4] Center 36 (8~64) winsize 57
6290 23:31:48.079738 [CA 5] Center 36 (8~64) winsize 57
6291 23:31:48.080254
6292 23:31:48.083189 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6293 23:31:48.083703
6294 23:31:48.086181 [CATrainingPosCal] consider 2 rank data
6295 23:31:48.089406 u2DelayCellTimex100 = 270/100 ps
6296 23:31:48.092507 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6297 23:31:48.096203 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6298 23:31:48.102796 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6299 23:31:48.106097 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6300 23:31:48.109703 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6301 23:31:48.112438 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6302 23:31:48.112854
6303 23:31:48.116119 CA PerBit enable=1, Macro0, CA PI delay=36
6304 23:31:48.116668
6305 23:31:48.119473 [CBTSetCACLKResult] CA Dly = 36
6306 23:31:48.120011 CS Dly: 1 (0~32)
6307 23:31:48.120347
6308 23:31:48.122567 ----->DramcWriteLeveling(PI) begin...
6309 23:31:48.126054 ==
6310 23:31:48.126574 Dram Type= 6, Freq= 0, CH_0, rank 0
6311 23:31:48.132601 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6312 23:31:48.133020 ==
6313 23:31:48.136084 Write leveling (Byte 0): 40 => 8
6314 23:31:48.140001 Write leveling (Byte 1): 40 => 8
6315 23:31:48.140591 DramcWriteLeveling(PI) end<-----
6316 23:31:48.143004
6317 23:31:48.143416 ==
6318 23:31:48.146277 Dram Type= 6, Freq= 0, CH_0, rank 0
6319 23:31:48.149560 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6320 23:31:48.150131 ==
6321 23:31:48.152972 [Gating] SW mode calibration
6322 23:31:48.159173 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6323 23:31:48.162789 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6324 23:31:48.169378 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6325 23:31:48.172713 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6326 23:31:48.175577 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6327 23:31:48.182274 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6328 23:31:48.185690 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6329 23:31:48.188925 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6330 23:31:48.195471 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6331 23:31:48.199369 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6332 23:31:48.202542 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6333 23:31:48.205724 Total UI for P1: 0, mck2ui 16
6334 23:31:48.209239 best dqsien dly found for B0: ( 0, 14, 24)
6335 23:31:48.212445 Total UI for P1: 0, mck2ui 16
6336 23:31:48.216120 best dqsien dly found for B1: ( 0, 14, 24)
6337 23:31:48.219086 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6338 23:31:48.222173 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6339 23:31:48.222760
6340 23:31:48.228533 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6341 23:31:48.232237 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6342 23:31:48.235352 [Gating] SW calibration Done
6343 23:31:48.235885 ==
6344 23:31:48.238936 Dram Type= 6, Freq= 0, CH_0, rank 0
6345 23:31:48.242159 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6346 23:31:48.242794 ==
6347 23:31:48.243228 RX Vref Scan: 0
6348 23:31:48.243575
6349 23:31:48.245306 RX Vref 0 -> 0, step: 1
6350 23:31:48.245882
6351 23:31:48.248509 RX Delay -410 -> 252, step: 16
6352 23:31:48.252137 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6353 23:31:48.258878 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6354 23:31:48.262209 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6355 23:31:48.265641 iDelay=230, Bit 3, Center -27 (-266 ~ 213) 480
6356 23:31:48.269648 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6357 23:31:48.272726 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6358 23:31:48.279588 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6359 23:31:48.282181 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6360 23:31:48.285316 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6361 23:31:48.288940 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6362 23:31:48.295510 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6363 23:31:48.299167 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6364 23:31:48.301924 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6365 23:31:48.308558 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6366 23:31:48.311843 iDelay=230, Bit 14, Center -3 (-234 ~ 229) 464
6367 23:31:48.315173 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6368 23:31:48.315732 ==
6369 23:31:48.318228 Dram Type= 6, Freq= 0, CH_0, rank 0
6370 23:31:48.322318 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6371 23:31:48.322876 ==
6372 23:31:48.325023 DQS Delay:
6373 23:31:48.325625 DQS0 = 27, DQS1 = 35
6374 23:31:48.328116 DQM Delay:
6375 23:31:48.328566 DQM0 = 11, DQM1 = 13
6376 23:31:48.331417 DQ Delay:
6377 23:31:48.331869 DQ0 =8, DQ1 =16, DQ2 =0, DQ3 =0
6378 23:31:48.334734 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6379 23:31:48.337997 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6380 23:31:48.341434 DQ12 =16, DQ13 =16, DQ14 =32, DQ15 =16
6381 23:31:48.341885
6382 23:31:48.342212
6383 23:31:48.345024 ==
6384 23:31:48.345546 Dram Type= 6, Freq= 0, CH_0, rank 0
6385 23:31:48.351514 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6386 23:31:48.351931 ==
6387 23:31:48.352259
6388 23:31:48.352562
6389 23:31:48.354540 TX Vref Scan disable
6390 23:31:48.354948 == TX Byte 0 ==
6391 23:31:48.358112 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6392 23:31:48.364758 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6393 23:31:48.365272 == TX Byte 1 ==
6394 23:31:48.368158 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6395 23:31:48.371265 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6396 23:31:48.374336 ==
6397 23:31:48.377748 Dram Type= 6, Freq= 0, CH_0, rank 0
6398 23:31:48.381440 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6399 23:31:48.382017 ==
6400 23:31:48.382349
6401 23:31:48.382661
6402 23:31:48.384774 TX Vref Scan disable
6403 23:31:48.385288 == TX Byte 0 ==
6404 23:31:48.388127 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6405 23:31:48.394390 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6406 23:31:48.394893 == TX Byte 1 ==
6407 23:31:48.397812 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6408 23:31:48.404623 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6409 23:31:48.405134
6410 23:31:48.405461 [DATLAT]
6411 23:31:48.405811 Freq=400, CH0 RK0
6412 23:31:48.406105
6413 23:31:48.407821 DATLAT Default: 0xf
6414 23:31:48.408228 0, 0xFFFF, sum = 0
6415 23:31:48.410831 1, 0xFFFF, sum = 0
6416 23:31:48.414194 2, 0xFFFF, sum = 0
6417 23:31:48.414612 3, 0xFFFF, sum = 0
6418 23:31:48.417713 4, 0xFFFF, sum = 0
6419 23:31:48.418258 5, 0xFFFF, sum = 0
6420 23:31:48.421017 6, 0xFFFF, sum = 0
6421 23:31:48.421571 7, 0xFFFF, sum = 0
6422 23:31:48.424255 8, 0xFFFF, sum = 0
6423 23:31:48.424815 9, 0xFFFF, sum = 0
6424 23:31:48.427546 10, 0xFFFF, sum = 0
6425 23:31:48.428004 11, 0xFFFF, sum = 0
6426 23:31:48.431009 12, 0xFFFF, sum = 0
6427 23:31:48.431469 13, 0x0, sum = 1
6428 23:31:48.434500 14, 0x0, sum = 2
6429 23:31:48.435063 15, 0x0, sum = 3
6430 23:31:48.437728 16, 0x0, sum = 4
6431 23:31:48.438190 best_step = 14
6432 23:31:48.438549
6433 23:31:48.438886 ==
6434 23:31:48.440859 Dram Type= 6, Freq= 0, CH_0, rank 0
6435 23:31:48.444235 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6436 23:31:48.447854 ==
6437 23:31:48.448409 RX Vref Scan: 1
6438 23:31:48.448770
6439 23:31:48.450899 RX Vref 0 -> 0, step: 1
6440 23:31:48.451350
6441 23:31:48.454433 RX Delay -311 -> 252, step: 8
6442 23:31:48.454985
6443 23:31:48.457628 Set Vref, RX VrefLevel [Byte0]: 54
6444 23:31:48.460700 [Byte1]: 54
6445 23:31:48.461256
6446 23:31:48.463915 Final RX Vref Byte 0 = 54 to rank0
6447 23:31:48.467742 Final RX Vref Byte 1 = 54 to rank0
6448 23:31:48.471238 Final RX Vref Byte 0 = 54 to rank1
6449 23:31:48.474019 Final RX Vref Byte 1 = 54 to rank1==
6450 23:31:48.477536 Dram Type= 6, Freq= 0, CH_0, rank 0
6451 23:31:48.481258 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6452 23:31:48.481858 ==
6453 23:31:48.484406 DQS Delay:
6454 23:31:48.484949 DQS0 = 28, DQS1 = 36
6455 23:31:48.487116 DQM Delay:
6456 23:31:48.487568 DQM0 = 11, DQM1 = 13
6457 23:31:48.487924 DQ Delay:
6458 23:31:48.490580 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6459 23:31:48.493966 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6460 23:31:48.497663 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =4
6461 23:31:48.500563 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6462 23:31:48.501149
6463 23:31:48.501637
6464 23:31:48.510795 [DQSOSCAuto] RK0, (LSB)MR18= 0xcab7, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 384 ps
6465 23:31:48.511341 CH0 RK0: MR19=C0C, MR18=CAB7
6466 23:31:48.517367 CH0_RK0: MR19=0xC0C, MR18=0xCAB7, DQSOSC=384, MR23=63, INC=400, DEC=267
6467 23:31:48.517995 ==
6468 23:31:48.520871 Dram Type= 6, Freq= 0, CH_0, rank 1
6469 23:31:48.527165 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6470 23:31:48.527724 ==
6471 23:31:48.530381 [Gating] SW mode calibration
6472 23:31:48.536839 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6473 23:31:48.540767 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6474 23:31:48.547672 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6475 23:31:48.550529 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6476 23:31:48.553431 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6477 23:31:48.560408 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6478 23:31:48.563523 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6479 23:31:48.566761 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6480 23:31:48.573797 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6481 23:31:48.576957 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6482 23:31:48.580156 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6483 23:31:48.583333 Total UI for P1: 0, mck2ui 16
6484 23:31:48.586361 best dqsien dly found for B0: ( 0, 14, 24)
6485 23:31:48.590091 Total UI for P1: 0, mck2ui 16
6486 23:31:48.593240 best dqsien dly found for B1: ( 0, 14, 24)
6487 23:31:48.596922 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6488 23:31:48.600336 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6489 23:31:48.600849
6490 23:31:48.603384 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6491 23:31:48.609964 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6492 23:31:48.610454 [Gating] SW calibration Done
6493 23:31:48.613676 ==
6494 23:31:48.614095 Dram Type= 6, Freq= 0, CH_0, rank 1
6495 23:31:48.619838 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6496 23:31:48.620254 ==
6497 23:31:48.620583 RX Vref Scan: 0
6498 23:31:48.620888
6499 23:31:48.623297 RX Vref 0 -> 0, step: 1
6500 23:31:48.623710
6501 23:31:48.626524 RX Delay -410 -> 252, step: 16
6502 23:31:48.629563 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6503 23:31:48.633222 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6504 23:31:48.640115 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6505 23:31:48.643006 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6506 23:31:48.646218 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6507 23:31:48.649681 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6508 23:31:48.656724 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6509 23:31:48.659501 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6510 23:31:48.663093 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6511 23:31:48.666583 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6512 23:31:48.673450 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6513 23:31:48.676689 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6514 23:31:48.680052 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6515 23:31:48.682861 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6516 23:31:48.689845 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6517 23:31:48.693075 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6518 23:31:48.693674 ==
6519 23:31:48.696310 Dram Type= 6, Freq= 0, CH_0, rank 1
6520 23:31:48.699598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6521 23:31:48.700065 ==
6522 23:31:48.703214 DQS Delay:
6523 23:31:48.703776 DQS0 = 27, DQS1 = 35
6524 23:31:48.706097 DQM Delay:
6525 23:31:48.706559 DQM0 = 12, DQM1 = 10
6526 23:31:48.706929 DQ Delay:
6527 23:31:48.709391 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6528 23:31:48.712712 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6529 23:31:48.716391 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6530 23:31:48.719728 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6531 23:31:48.720310
6532 23:31:48.720673
6533 23:31:48.721007 ==
6534 23:31:48.722614 Dram Type= 6, Freq= 0, CH_0, rank 1
6535 23:31:48.729621 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6536 23:31:48.730189 ==
6537 23:31:48.730559
6538 23:31:48.730957
6539 23:31:48.731294 TX Vref Scan disable
6540 23:31:48.732846 == TX Byte 0 ==
6541 23:31:48.736151 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6542 23:31:48.739561 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6543 23:31:48.742868 == TX Byte 1 ==
6544 23:31:48.745967 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6545 23:31:48.749440 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6546 23:31:48.749956 ==
6547 23:31:48.752934 Dram Type= 6, Freq= 0, CH_0, rank 1
6548 23:31:48.759145 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6549 23:31:48.759690 ==
6550 23:31:48.760058
6551 23:31:48.760401
6552 23:31:48.760729 TX Vref Scan disable
6553 23:31:48.762714 == TX Byte 0 ==
6554 23:31:48.766202 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6555 23:31:48.769384 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6556 23:31:48.773063 == TX Byte 1 ==
6557 23:31:48.776173 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6558 23:31:48.779481 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6559 23:31:48.780042
6560 23:31:48.782348 [DATLAT]
6561 23:31:48.782813 Freq=400, CH0 RK1
6562 23:31:48.783183
6563 23:31:48.785829 DATLAT Default: 0xe
6564 23:31:48.786385 0, 0xFFFF, sum = 0
6565 23:31:48.788995 1, 0xFFFF, sum = 0
6566 23:31:48.789561 2, 0xFFFF, sum = 0
6567 23:31:48.792483 3, 0xFFFF, sum = 0
6568 23:31:48.792954 4, 0xFFFF, sum = 0
6569 23:31:48.795986 5, 0xFFFF, sum = 0
6570 23:31:48.796455 6, 0xFFFF, sum = 0
6571 23:31:48.799243 7, 0xFFFF, sum = 0
6572 23:31:48.799719 8, 0xFFFF, sum = 0
6573 23:31:48.802524 9, 0xFFFF, sum = 0
6574 23:31:48.805701 10, 0xFFFF, sum = 0
6575 23:31:48.806260 11, 0xFFFF, sum = 0
6576 23:31:48.808846 12, 0xFFFF, sum = 0
6577 23:31:48.809318 13, 0x0, sum = 1
6578 23:31:48.812148 14, 0x0, sum = 2
6579 23:31:48.812621 15, 0x0, sum = 3
6580 23:31:48.812995 16, 0x0, sum = 4
6581 23:31:48.815746 best_step = 14
6582 23:31:48.816318
6583 23:31:48.816691 ==
6584 23:31:48.819203 Dram Type= 6, Freq= 0, CH_0, rank 1
6585 23:31:48.822340 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6586 23:31:48.822810 ==
6587 23:31:48.825702 RX Vref Scan: 0
6588 23:31:48.826169
6589 23:31:48.826541 RX Vref 0 -> 0, step: 1
6590 23:31:48.828784
6591 23:31:48.829244 RX Delay -311 -> 252, step: 8
6592 23:31:48.837676 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6593 23:31:48.840747 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6594 23:31:48.844257 iDelay=217, Bit 2, Center -20 (-247 ~ 208) 456
6595 23:31:48.847234 iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448
6596 23:31:48.854566 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6597 23:31:48.857400 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6598 23:31:48.860798 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6599 23:31:48.863852 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6600 23:31:48.870771 iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448
6601 23:31:48.874000 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6602 23:31:48.877675 iDelay=217, Bit 10, Center -20 (-239 ~ 200) 440
6603 23:31:48.880626 iDelay=217, Bit 11, Center -28 (-247 ~ 192) 440
6604 23:31:48.887186 iDelay=217, Bit 12, Center -16 (-239 ~ 208) 448
6605 23:31:48.890564 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
6606 23:31:48.893795 iDelay=217, Bit 14, Center -12 (-231 ~ 208) 440
6607 23:31:48.900484 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6608 23:31:48.901079 ==
6609 23:31:48.904132 Dram Type= 6, Freq= 0, CH_0, rank 1
6610 23:31:48.907524 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6611 23:31:48.908091 ==
6612 23:31:48.908465 DQS Delay:
6613 23:31:48.910362 DQS0 = 24, DQS1 = 32
6614 23:31:48.910827 DQM Delay:
6615 23:31:48.913415 DQM0 = 8, DQM1 = 10
6616 23:31:48.913923 DQ Delay:
6617 23:31:48.917232 DQ0 =8, DQ1 =8, DQ2 =4, DQ3 =8
6618 23:31:48.920588 DQ4 =8, DQ5 =0, DQ6 =12, DQ7 =16
6619 23:31:48.923833 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6620 23:31:48.927411 DQ12 =16, DQ13 =16, DQ14 =20, DQ15 =16
6621 23:31:48.927986
6622 23:31:48.928361
6623 23:31:48.933753 [DQSOSCAuto] RK1, (LSB)MR18= 0xb455, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 387 ps
6624 23:31:48.937109 CH0 RK1: MR19=C0C, MR18=B455
6625 23:31:48.943600 CH0_RK1: MR19=0xC0C, MR18=0xB455, DQSOSC=387, MR23=63, INC=394, DEC=262
6626 23:31:48.946828 [RxdqsGatingPostProcess] freq 400
6627 23:31:48.949741 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6628 23:31:48.953430 best DQS0 dly(2T, 0.5T) = (0, 10)
6629 23:31:48.956929 best DQS1 dly(2T, 0.5T) = (0, 10)
6630 23:31:48.960055 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6631 23:31:48.963403 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6632 23:31:48.966836 best DQS0 dly(2T, 0.5T) = (0, 10)
6633 23:31:48.969899 best DQS1 dly(2T, 0.5T) = (0, 10)
6634 23:31:48.973665 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6635 23:31:48.976771 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6636 23:31:48.980411 Pre-setting of DQS Precalculation
6637 23:31:48.983498 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6638 23:31:48.986576 ==
6639 23:31:48.987134 Dram Type= 6, Freq= 0, CH_1, rank 0
6640 23:31:48.993781 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6641 23:31:48.994339 ==
6642 23:31:48.996899 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6643 23:31:49.003474 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6644 23:31:49.006948 [CA 0] Center 36 (8~64) winsize 57
6645 23:31:49.010126 [CA 1] Center 36 (8~64) winsize 57
6646 23:31:49.013076 [CA 2] Center 36 (8~64) winsize 57
6647 23:31:49.016909 [CA 3] Center 36 (8~64) winsize 57
6648 23:31:49.020311 [CA 4] Center 36 (8~64) winsize 57
6649 23:31:49.023601 [CA 5] Center 36 (8~64) winsize 57
6650 23:31:49.024070
6651 23:31:49.026787 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6652 23:31:49.027347
6653 23:31:49.029963 [CATrainingPosCal] consider 1 rank data
6654 23:31:49.033168 u2DelayCellTimex100 = 270/100 ps
6655 23:31:49.037160 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6656 23:31:49.039706 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6657 23:31:49.043225 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6658 23:31:49.046466 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6659 23:31:49.049717 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6660 23:31:49.057366 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6661 23:31:49.057986
6662 23:31:49.060147 CA PerBit enable=1, Macro0, CA PI delay=36
6663 23:31:49.060703
6664 23:31:49.063185 [CBTSetCACLKResult] CA Dly = 36
6665 23:31:49.063651 CS Dly: 1 (0~32)
6666 23:31:49.064019 ==
6667 23:31:49.066643 Dram Type= 6, Freq= 0, CH_1, rank 1
6668 23:31:49.070198 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6669 23:31:49.072831 ==
6670 23:31:49.076396 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6671 23:31:49.083139 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6672 23:31:49.086269 [CA 0] Center 36 (8~64) winsize 57
6673 23:31:49.090369 [CA 1] Center 36 (8~64) winsize 57
6674 23:31:49.092806 [CA 2] Center 36 (8~64) winsize 57
6675 23:31:49.096363 [CA 3] Center 36 (8~64) winsize 57
6676 23:31:49.099740 [CA 4] Center 36 (8~64) winsize 57
6677 23:31:49.103225 [CA 5] Center 36 (8~64) winsize 57
6678 23:31:49.103680
6679 23:31:49.106385 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6680 23:31:49.106841
6681 23:31:49.109784 [CATrainingPosCal] consider 2 rank data
6682 23:31:49.113001 u2DelayCellTimex100 = 270/100 ps
6683 23:31:49.116453 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6684 23:31:49.119389 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6685 23:31:49.123117 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6686 23:31:49.126388 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6687 23:31:49.129488 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6688 23:31:49.132742 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6689 23:31:49.133199
6690 23:31:49.135990 CA PerBit enable=1, Macro0, CA PI delay=36
6691 23:31:49.136448
6692 23:31:49.139289 [CBTSetCACLKResult] CA Dly = 36
6693 23:31:49.142763 CS Dly: 1 (0~32)
6694 23:31:49.143321
6695 23:31:49.146077 ----->DramcWriteLeveling(PI) begin...
6696 23:31:49.146716 ==
6697 23:31:49.149239 Dram Type= 6, Freq= 0, CH_1, rank 0
6698 23:31:49.153095 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6699 23:31:49.153720 ==
6700 23:31:49.156329 Write leveling (Byte 0): 40 => 8
6701 23:31:49.159391 Write leveling (Byte 1): 40 => 8
6702 23:31:49.162742 DramcWriteLeveling(PI) end<-----
6703 23:31:49.163214
6704 23:31:49.163696 ==
6705 23:31:49.166176 Dram Type= 6, Freq= 0, CH_1, rank 0
6706 23:31:49.169936 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6707 23:31:49.170511 ==
6708 23:31:49.172871 [Gating] SW mode calibration
6709 23:31:49.178977 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6710 23:31:49.185887 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6711 23:31:49.188973 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6712 23:31:49.195870 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6713 23:31:49.199214 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6714 23:31:49.202306 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6715 23:31:49.209562 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6716 23:31:49.212247 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6717 23:31:49.215892 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6718 23:31:49.222453 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6719 23:31:49.226132 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6720 23:31:49.229327 Total UI for P1: 0, mck2ui 16
6721 23:31:49.232551 best dqsien dly found for B0: ( 0, 14, 24)
6722 23:31:49.235701 Total UI for P1: 0, mck2ui 16
6723 23:31:49.238561 best dqsien dly found for B1: ( 0, 14, 24)
6724 23:31:49.242135 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6725 23:31:49.245742 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6726 23:31:49.246314
6727 23:31:49.248743 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6728 23:31:49.252587 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6729 23:31:49.256114 [Gating] SW calibration Done
6730 23:31:49.256678 ==
6731 23:31:49.259088 Dram Type= 6, Freq= 0, CH_1, rank 0
6732 23:31:49.262608 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6733 23:31:49.263191 ==
6734 23:31:49.265698 RX Vref Scan: 0
6735 23:31:49.266272
6736 23:31:49.269114 RX Vref 0 -> 0, step: 1
6737 23:31:49.269714
6738 23:31:49.270086 RX Delay -410 -> 252, step: 16
6739 23:31:49.276148 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6740 23:31:49.278755 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6741 23:31:49.282280 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6742 23:31:49.285863 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6743 23:31:49.292601 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6744 23:31:49.295376 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6745 23:31:49.298857 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6746 23:31:49.302277 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6747 23:31:49.309158 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6748 23:31:49.312615 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6749 23:31:49.315555 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6750 23:31:49.318694 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6751 23:31:49.325386 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6752 23:31:49.328889 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6753 23:31:49.332317 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6754 23:31:49.338902 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6755 23:31:49.339478 ==
6756 23:31:49.342100 Dram Type= 6, Freq= 0, CH_1, rank 0
6757 23:31:49.345431 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6758 23:31:49.346041 ==
6759 23:31:49.346409 DQS Delay:
6760 23:31:49.348643 DQS0 = 35, DQS1 = 35
6761 23:31:49.349095 DQM Delay:
6762 23:31:49.351631 DQM0 = 18, DQM1 = 13
6763 23:31:49.352143 DQ Delay:
6764 23:31:49.355570 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6765 23:31:49.358863 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6766 23:31:49.361977 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6767 23:31:49.365681 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6768 23:31:49.366243
6769 23:31:49.366607
6770 23:31:49.366939 ==
6771 23:31:49.369029 Dram Type= 6, Freq= 0, CH_1, rank 0
6772 23:31:49.371952 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6773 23:31:49.372515 ==
6774 23:31:49.372878
6775 23:31:49.373211
6776 23:31:49.375493 TX Vref Scan disable
6777 23:31:49.378488 == TX Byte 0 ==
6778 23:31:49.382192 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6779 23:31:49.385165 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6780 23:31:49.388766 == TX Byte 1 ==
6781 23:31:49.391987 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6782 23:31:49.395527 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6783 23:31:49.395987 ==
6784 23:31:49.398325 Dram Type= 6, Freq= 0, CH_1, rank 0
6785 23:31:49.401626 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6786 23:31:49.402096 ==
6787 23:31:49.402463
6788 23:31:49.405692
6789 23:31:49.406254 TX Vref Scan disable
6790 23:31:49.408562 == TX Byte 0 ==
6791 23:31:49.411757 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6792 23:31:49.415017 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6793 23:31:49.418333 == TX Byte 1 ==
6794 23:31:49.421715 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6795 23:31:49.424991 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6796 23:31:49.425556
6797 23:31:49.425968 [DATLAT]
6798 23:31:49.428527 Freq=400, CH1 RK0
6799 23:31:49.429088
6800 23:31:49.429452 DATLAT Default: 0xf
6801 23:31:49.431626 0, 0xFFFF, sum = 0
6802 23:31:49.435113 1, 0xFFFF, sum = 0
6803 23:31:49.435710 2, 0xFFFF, sum = 0
6804 23:31:49.438057 3, 0xFFFF, sum = 0
6805 23:31:49.438524 4, 0xFFFF, sum = 0
6806 23:31:49.441486 5, 0xFFFF, sum = 0
6807 23:31:49.442153 6, 0xFFFF, sum = 0
6808 23:31:49.444997 7, 0xFFFF, sum = 0
6809 23:31:49.445562 8, 0xFFFF, sum = 0
6810 23:31:49.448169 9, 0xFFFF, sum = 0
6811 23:31:49.448735 10, 0xFFFF, sum = 0
6812 23:31:49.451377 11, 0xFFFF, sum = 0
6813 23:31:49.451851 12, 0xFFFF, sum = 0
6814 23:31:49.455039 13, 0x0, sum = 1
6815 23:31:49.455602 14, 0x0, sum = 2
6816 23:31:49.458308 15, 0x0, sum = 3
6817 23:31:49.458784 16, 0x0, sum = 4
6818 23:31:49.461465 best_step = 14
6819 23:31:49.462086
6820 23:31:49.462452 ==
6821 23:31:49.464561 Dram Type= 6, Freq= 0, CH_1, rank 0
6822 23:31:49.467909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6823 23:31:49.468476 ==
6824 23:31:49.471261 RX Vref Scan: 1
6825 23:31:49.471825
6826 23:31:49.472192 RX Vref 0 -> 0, step: 1
6827 23:31:49.472532
6828 23:31:49.474432 RX Delay -311 -> 252, step: 8
6829 23:31:49.474891
6830 23:31:49.478009 Set Vref, RX VrefLevel [Byte0]: 55
6831 23:31:49.481178 [Byte1]: 52
6832 23:31:49.485306
6833 23:31:49.485927 Final RX Vref Byte 0 = 55 to rank0
6834 23:31:49.488735 Final RX Vref Byte 1 = 52 to rank0
6835 23:31:49.491769 Final RX Vref Byte 0 = 55 to rank1
6836 23:31:49.495630 Final RX Vref Byte 1 = 52 to rank1==
6837 23:31:49.498436 Dram Type= 6, Freq= 0, CH_1, rank 0
6838 23:31:49.505565 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6839 23:31:49.506186 ==
6840 23:31:49.506555 DQS Delay:
6841 23:31:49.508810 DQS0 = 28, DQS1 = 32
6842 23:31:49.509429 DQM Delay:
6843 23:31:49.509866 DQM0 = 10, DQM1 = 11
6844 23:31:49.512343 DQ Delay:
6845 23:31:49.515237 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =8
6846 23:31:49.515699 DQ4 =12, DQ5 =20, DQ6 =16, DQ7 =8
6847 23:31:49.518400 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
6848 23:31:49.522728 DQ12 =20, DQ13 =20, DQ14 =16, DQ15 =24
6849 23:31:49.523292
6850 23:31:49.523657
6851 23:31:49.532150 [DQSOSCAuto] RK0, (LSB)MR18= 0x92ca, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 391 ps
6852 23:31:49.534900 CH1 RK0: MR19=C0C, MR18=92CA
6853 23:31:49.541956 CH1_RK0: MR19=0xC0C, MR18=0x92CA, DQSOSC=384, MR23=63, INC=400, DEC=267
6854 23:31:49.542448 ==
6855 23:31:49.545456 Dram Type= 6, Freq= 0, CH_1, rank 1
6856 23:31:49.548647 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6857 23:31:49.549110 ==
6858 23:31:49.551812 [Gating] SW mode calibration
6859 23:31:49.558582 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6860 23:31:49.561861 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6861 23:31:49.568637 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6862 23:31:49.571982 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6863 23:31:49.575038 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6864 23:31:49.581627 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6865 23:31:49.585211 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6866 23:31:49.588267 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6867 23:31:49.594483 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6868 23:31:49.603015 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6869 23:31:49.603851 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6870 23:31:49.604907 Total UI for P1: 0, mck2ui 16
6871 23:31:49.607669 best dqsien dly found for B0: ( 0, 14, 24)
6872 23:31:49.611258 Total UI for P1: 0, mck2ui 16
6873 23:31:49.614738 best dqsien dly found for B1: ( 0, 14, 24)
6874 23:31:49.618159 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6875 23:31:49.624738 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6876 23:31:49.625434
6877 23:31:49.628361 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6878 23:31:49.631460 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6879 23:31:49.634319 [Gating] SW calibration Done
6880 23:31:49.634810 ==
6881 23:31:49.638020 Dram Type= 6, Freq= 0, CH_1, rank 1
6882 23:31:49.641070 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6883 23:31:49.641634 ==
6884 23:31:49.642116 RX Vref Scan: 0
6885 23:31:49.644189
6886 23:31:49.644689 RX Vref 0 -> 0, step: 1
6887 23:31:49.645141
6888 23:31:49.647658 RX Delay -410 -> 252, step: 16
6889 23:31:49.651519 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6890 23:31:49.658091 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6891 23:31:49.661499 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6892 23:31:49.664910 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6893 23:31:49.667759 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6894 23:31:49.674854 iDelay=230, Bit 5, Center 5 (-218 ~ 229) 448
6895 23:31:49.678163 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6896 23:31:49.681132 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6897 23:31:49.684608 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6898 23:31:49.691130 iDelay=230, Bit 9, Center -27 (-266 ~ 213) 480
6899 23:31:49.694857 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6900 23:31:49.697897 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6901 23:31:49.700843 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6902 23:31:49.707494 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6903 23:31:49.710932 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6904 23:31:49.714487 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6905 23:31:49.714907 ==
6906 23:31:49.717506 Dram Type= 6, Freq= 0, CH_1, rank 1
6907 23:31:49.720768 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6908 23:31:49.724402 ==
6909 23:31:49.724841 DQS Delay:
6910 23:31:49.725172 DQS0 = 35, DQS1 = 35
6911 23:31:49.727569 DQM Delay:
6912 23:31:49.727981 DQM0 = 19, DQM1 = 14
6913 23:31:49.731087 DQ Delay:
6914 23:31:49.734025 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6915 23:31:49.734436 DQ4 =16, DQ5 =40, DQ6 =32, DQ7 =16
6916 23:31:49.737530 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6917 23:31:49.740614 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6918 23:31:49.741023
6919 23:31:49.744004
6920 23:31:49.744411 ==
6921 23:31:49.747287 Dram Type= 6, Freq= 0, CH_1, rank 1
6922 23:31:49.750629 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6923 23:31:49.751057 ==
6924 23:31:49.751395
6925 23:31:49.751703
6926 23:31:49.754144 TX Vref Scan disable
6927 23:31:49.754565 == TX Byte 0 ==
6928 23:31:49.757454 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6929 23:31:49.764201 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6930 23:31:49.764778 == TX Byte 1 ==
6931 23:31:49.767096 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6932 23:31:49.774184 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6933 23:31:49.774745 ==
6934 23:31:49.777140 Dram Type= 6, Freq= 0, CH_1, rank 1
6935 23:31:49.780628 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6936 23:31:49.781185 ==
6937 23:31:49.781556
6938 23:31:49.781997
6939 23:31:49.784019 TX Vref Scan disable
6940 23:31:49.784577 == TX Byte 0 ==
6941 23:31:49.787273 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6942 23:31:49.794009 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6943 23:31:49.794576 == TX Byte 1 ==
6944 23:31:49.797376 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6945 23:31:49.803828 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6946 23:31:49.804295
6947 23:31:49.804667 [DATLAT]
6948 23:31:49.805009 Freq=400, CH1 RK1
6949 23:31:49.806913
6950 23:31:49.807373 DATLAT Default: 0xe
6951 23:31:49.810254 0, 0xFFFF, sum = 0
6952 23:31:49.810726 1, 0xFFFF, sum = 0
6953 23:31:49.813918 2, 0xFFFF, sum = 0
6954 23:31:49.814444 3, 0xFFFF, sum = 0
6955 23:31:49.817067 4, 0xFFFF, sum = 0
6956 23:31:49.817494 5, 0xFFFF, sum = 0
6957 23:31:49.820799 6, 0xFFFF, sum = 0
6958 23:31:49.821321 7, 0xFFFF, sum = 0
6959 23:31:49.824128 8, 0xFFFF, sum = 0
6960 23:31:49.824647 9, 0xFFFF, sum = 0
6961 23:31:49.826730 10, 0xFFFF, sum = 0
6962 23:31:49.827161 11, 0xFFFF, sum = 0
6963 23:31:49.830001 12, 0xFFFF, sum = 0
6964 23:31:49.830428 13, 0x0, sum = 1
6965 23:31:49.833458 14, 0x0, sum = 2
6966 23:31:49.833928 15, 0x0, sum = 3
6967 23:31:49.836616 16, 0x0, sum = 4
6968 23:31:49.837041 best_step = 14
6969 23:31:49.837375
6970 23:31:49.837737 ==
6971 23:31:49.840181 Dram Type= 6, Freq= 0, CH_1, rank 1
6972 23:31:49.847177 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6973 23:31:49.847730 ==
6974 23:31:49.848079 RX Vref Scan: 0
6975 23:31:49.848389
6976 23:31:49.849926 RX Vref 0 -> 0, step: 1
6977 23:31:49.850340
6978 23:31:49.853618 RX Delay -311 -> 252, step: 8
6979 23:31:49.860224 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6980 23:31:49.863651 iDelay=217, Bit 1, Center -24 (-247 ~ 200) 448
6981 23:31:49.866816 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
6982 23:31:49.870230 iDelay=217, Bit 3, Center -20 (-239 ~ 200) 440
6983 23:31:49.877115 iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440
6984 23:31:49.880185 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
6985 23:31:49.884142 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6986 23:31:49.886781 iDelay=217, Bit 7, Center -16 (-239 ~ 208) 448
6987 23:31:49.890622 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6988 23:31:49.897340 iDelay=217, Bit 9, Center -36 (-263 ~ 192) 456
6989 23:31:49.900144 iDelay=217, Bit 10, Center -20 (-247 ~ 208) 456
6990 23:31:49.903562 iDelay=217, Bit 11, Center -28 (-255 ~ 200) 456
6991 23:31:49.910082 iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456
6992 23:31:49.913803 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
6993 23:31:49.916395 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6994 23:31:49.919978 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
6995 23:31:49.920443 ==
6996 23:31:49.923463 Dram Type= 6, Freq= 0, CH_1, rank 1
6997 23:31:49.930310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6998 23:31:49.930868 ==
6999 23:31:49.931238 DQS Delay:
7000 23:31:49.933410 DQS0 = 28, DQS1 = 36
7001 23:31:49.933915 DQM Delay:
7002 23:31:49.934292 DQM0 = 11, DQM1 = 14
7003 23:31:49.936964 DQ Delay:
7004 23:31:49.940312 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =8
7005 23:31:49.943323 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =12
7006 23:31:49.943802 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
7007 23:31:49.946887 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =24
7008 23:31:49.949843
7009 23:31:49.950396
7010 23:31:49.957271 [DQSOSCAuto] RK1, (LSB)MR18= 0xc052, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 386 ps
7011 23:31:49.960223 CH1 RK1: MR19=C0C, MR18=C052
7012 23:31:49.966393 CH1_RK1: MR19=0xC0C, MR18=0xC052, DQSOSC=386, MR23=63, INC=396, DEC=264
7013 23:31:49.969781 [RxdqsGatingPostProcess] freq 400
7014 23:31:49.973469 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7015 23:31:49.976486 best DQS0 dly(2T, 0.5T) = (0, 10)
7016 23:31:49.979827 best DQS1 dly(2T, 0.5T) = (0, 10)
7017 23:31:49.982917 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7018 23:31:49.986954 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7019 23:31:49.989875 best DQS0 dly(2T, 0.5T) = (0, 10)
7020 23:31:49.992777 best DQS1 dly(2T, 0.5T) = (0, 10)
7021 23:31:49.996604 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7022 23:31:49.999836 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7023 23:31:50.003025 Pre-setting of DQS Precalculation
7024 23:31:50.006590 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7025 23:31:50.012826 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7026 23:31:50.023201 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7027 23:31:50.023762
7028 23:31:50.024120
7029 23:31:50.026451 [Calibration Summary] 800 Mbps
7030 23:31:50.026911 CH 0, Rank 0
7031 23:31:50.029937 SW Impedance : PASS
7032 23:31:50.030393 DUTY Scan : NO K
7033 23:31:50.032806 ZQ Calibration : PASS
7034 23:31:50.033261 Jitter Meter : NO K
7035 23:31:50.036619 CBT Training : PASS
7036 23:31:50.039691 Write leveling : PASS
7037 23:31:50.040248 RX DQS gating : PASS
7038 23:31:50.042877 RX DQ/DQS(RDDQC) : PASS
7039 23:31:50.046283 TX DQ/DQS : PASS
7040 23:31:50.046698 RX DATLAT : PASS
7041 23:31:50.049517 RX DQ/DQS(Engine): PASS
7042 23:31:50.053534 TX OE : NO K
7043 23:31:50.054150 All Pass.
7044 23:31:50.054516
7045 23:31:50.054921 CH 0, Rank 1
7046 23:31:50.056046 SW Impedance : PASS
7047 23:31:50.060109 DUTY Scan : NO K
7048 23:31:50.060667 ZQ Calibration : PASS
7049 23:31:50.063440 Jitter Meter : NO K
7050 23:31:50.066104 CBT Training : PASS
7051 23:31:50.066563 Write leveling : NO K
7052 23:31:50.069803 RX DQS gating : PASS
7053 23:31:50.073257 RX DQ/DQS(RDDQC) : PASS
7054 23:31:50.073864 TX DQ/DQS : PASS
7055 23:31:50.076546 RX DATLAT : PASS
7056 23:31:50.079318 RX DQ/DQS(Engine): PASS
7057 23:31:50.079880 TX OE : NO K
7058 23:31:50.080248 All Pass.
7059 23:31:50.080584
7060 23:31:50.083049 CH 1, Rank 0
7061 23:31:50.083503 SW Impedance : PASS
7062 23:31:50.086473 DUTY Scan : NO K
7063 23:31:50.089834 ZQ Calibration : PASS
7064 23:31:50.090387 Jitter Meter : NO K
7065 23:31:50.093120 CBT Training : PASS
7066 23:31:50.096122 Write leveling : PASS
7067 23:31:50.096682 RX DQS gating : PASS
7068 23:31:50.099337 RX DQ/DQS(RDDQC) : PASS
7069 23:31:50.102699 TX DQ/DQS : PASS
7070 23:31:50.103156 RX DATLAT : PASS
7071 23:31:50.106050 RX DQ/DQS(Engine): PASS
7072 23:31:50.109410 TX OE : NO K
7073 23:31:50.110043 All Pass.
7074 23:31:50.110453
7075 23:31:50.110794 CH 1, Rank 1
7076 23:31:50.112807 SW Impedance : PASS
7077 23:31:50.115888 DUTY Scan : NO K
7078 23:31:50.116375 ZQ Calibration : PASS
7079 23:31:50.119448 Jitter Meter : NO K
7080 23:31:50.122747 CBT Training : PASS
7081 23:31:50.123207 Write leveling : NO K
7082 23:31:50.126034 RX DQS gating : PASS
7083 23:31:50.126509 RX DQ/DQS(RDDQC) : PASS
7084 23:31:50.129209 TX DQ/DQS : PASS
7085 23:31:50.132776 RX DATLAT : PASS
7086 23:31:50.133320 RX DQ/DQS(Engine): PASS
7087 23:31:50.136335 TX OE : NO K
7088 23:31:50.136860 All Pass.
7089 23:31:50.137199
7090 23:31:50.139391 DramC Write-DBI off
7091 23:31:50.142528 PER_BANK_REFRESH: Hybrid Mode
7092 23:31:50.142951 TX_TRACKING: ON
7093 23:31:50.152747 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7094 23:31:50.156368 [FAST_K] Save calibration result to emmc
7095 23:31:50.159698 dramc_set_vcore_voltage set vcore to 725000
7096 23:31:50.162531 Read voltage for 1600, 0
7097 23:31:50.162984 Vio18 = 0
7098 23:31:50.166172 Vcore = 725000
7099 23:31:50.166730 Vdram = 0
7100 23:31:50.167096 Vddq = 0
7101 23:31:50.167434 Vmddr = 0
7102 23:31:50.172612 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7103 23:31:50.176229 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7104 23:31:50.179274 MEM_TYPE=3, freq_sel=13
7105 23:31:50.182898 sv_algorithm_assistance_LP4_3733
7106 23:31:50.186152 ============ PULL DRAM RESETB DOWN ============
7107 23:31:50.192346 ========== PULL DRAM RESETB DOWN end =========
7108 23:31:50.195776 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7109 23:31:50.199162 ===================================
7110 23:31:50.202684 LPDDR4 DRAM CONFIGURATION
7111 23:31:50.205513 ===================================
7112 23:31:50.206023 EX_ROW_EN[0] = 0x0
7113 23:31:50.208816 EX_ROW_EN[1] = 0x0
7114 23:31:50.209270 LP4Y_EN = 0x0
7115 23:31:50.212475 WORK_FSP = 0x1
7116 23:31:50.213033 WL = 0x5
7117 23:31:50.215740 RL = 0x5
7118 23:31:50.216200 BL = 0x2
7119 23:31:50.219129 RPST = 0x0
7120 23:31:50.219623 RD_PRE = 0x0
7121 23:31:50.222409 WR_PRE = 0x1
7122 23:31:50.222870 WR_PST = 0x1
7123 23:31:50.225819 DBI_WR = 0x0
7124 23:31:50.229155 DBI_RD = 0x0
7125 23:31:50.229604 OTF = 0x1
7126 23:31:50.232253 ===================================
7127 23:31:50.235986 ===================================
7128 23:31:50.236555 ANA top config
7129 23:31:50.238733 ===================================
7130 23:31:50.242330 DLL_ASYNC_EN = 0
7131 23:31:50.245453 ALL_SLAVE_EN = 0
7132 23:31:50.248805 NEW_RANK_MODE = 1
7133 23:31:50.249329 DLL_IDLE_MODE = 1
7134 23:31:50.252289 LP45_APHY_COMB_EN = 1
7135 23:31:50.255437 TX_ODT_DIS = 0
7136 23:31:50.259444 NEW_8X_MODE = 1
7137 23:31:50.262525 ===================================
7138 23:31:50.265551 ===================================
7139 23:31:50.269073 data_rate = 3200
7140 23:31:50.272283 CKR = 1
7141 23:31:50.272751 DQ_P2S_RATIO = 8
7142 23:31:50.275715 ===================================
7143 23:31:50.279303 CA_P2S_RATIO = 8
7144 23:31:50.282380 DQ_CA_OPEN = 0
7145 23:31:50.285785 DQ_SEMI_OPEN = 0
7146 23:31:50.289037 CA_SEMI_OPEN = 0
7147 23:31:50.289566 CA_FULL_RATE = 0
7148 23:31:50.292506 DQ_CKDIV4_EN = 0
7149 23:31:50.295533 CA_CKDIV4_EN = 0
7150 23:31:50.299310 CA_PREDIV_EN = 0
7151 23:31:50.302507 PH8_DLY = 12
7152 23:31:50.305506 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7153 23:31:50.305965 DQ_AAMCK_DIV = 4
7154 23:31:50.309346 CA_AAMCK_DIV = 4
7155 23:31:50.312632 CA_ADMCK_DIV = 4
7156 23:31:50.315659 DQ_TRACK_CA_EN = 0
7157 23:31:50.318903 CA_PICK = 1600
7158 23:31:50.322326 CA_MCKIO = 1600
7159 23:31:50.325324 MCKIO_SEMI = 0
7160 23:31:50.328926 PLL_FREQ = 3068
7161 23:31:50.329459 DQ_UI_PI_RATIO = 32
7162 23:31:50.332102 CA_UI_PI_RATIO = 0
7163 23:31:50.335505 ===================================
7164 23:31:50.338712 ===================================
7165 23:31:50.341985 memory_type:LPDDR4
7166 23:31:50.345481 GP_NUM : 10
7167 23:31:50.346087 SRAM_EN : 1
7168 23:31:50.348528 MD32_EN : 0
7169 23:31:50.352161 ===================================
7170 23:31:50.355092 [ANA_INIT] >>>>>>>>>>>>>>
7171 23:31:50.355557 <<<<<< [CONFIGURE PHASE]: ANA_TX
7172 23:31:50.359064 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7173 23:31:50.362097 ===================================
7174 23:31:50.365387 data_rate = 3200,PCW = 0X7600
7175 23:31:50.368620 ===================================
7176 23:31:50.372175 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7177 23:31:50.378785 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7178 23:31:50.385360 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7179 23:31:50.388381 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7180 23:31:50.391833 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7181 23:31:50.394881 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7182 23:31:50.398258 [ANA_INIT] flow start
7183 23:31:50.398718 [ANA_INIT] PLL >>>>>>>>
7184 23:31:50.401831 [ANA_INIT] PLL <<<<<<<<
7185 23:31:50.405650 [ANA_INIT] MIDPI >>>>>>>>
7186 23:31:50.406215 [ANA_INIT] MIDPI <<<<<<<<
7187 23:31:50.408762 [ANA_INIT] DLL >>>>>>>>
7188 23:31:50.411718 [ANA_INIT] DLL <<<<<<<<
7189 23:31:50.412177 [ANA_INIT] flow end
7190 23:31:50.418560 ============ LP4 DIFF to SE enter ============
7191 23:31:50.421820 ============ LP4 DIFF to SE exit ============
7192 23:31:50.422284 [ANA_INIT] <<<<<<<<<<<<<
7193 23:31:50.425341 [Flow] Enable top DCM control >>>>>
7194 23:31:50.429055 [Flow] Enable top DCM control <<<<<
7195 23:31:50.432469 Enable DLL master slave shuffle
7196 23:31:50.438456 ==============================================================
7197 23:31:50.442224 Gating Mode config
7198 23:31:50.445372 ==============================================================
7199 23:31:50.448596 Config description:
7200 23:31:50.458496 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7201 23:31:50.465080 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7202 23:31:50.468515 SELPH_MODE 0: By rank 1: By Phase
7203 23:31:50.475737 ==============================================================
7204 23:31:50.478575 GAT_TRACK_EN = 1
7205 23:31:50.482056 RX_GATING_MODE = 2
7206 23:31:50.482624 RX_GATING_TRACK_MODE = 2
7207 23:31:50.485464 SELPH_MODE = 1
7208 23:31:50.489141 PICG_EARLY_EN = 1
7209 23:31:50.491850 VALID_LAT_VALUE = 1
7210 23:31:50.498489 ==============================================================
7211 23:31:50.502025 Enter into Gating configuration >>>>
7212 23:31:50.505409 Exit from Gating configuration <<<<
7213 23:31:50.508237 Enter into DVFS_PRE_config >>>>>
7214 23:31:50.518220 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7215 23:31:50.521840 Exit from DVFS_PRE_config <<<<<
7216 23:31:50.524961 Enter into PICG configuration >>>>
7217 23:31:50.528425 Exit from PICG configuration <<<<
7218 23:31:50.532122 [RX_INPUT] configuration >>>>>
7219 23:31:50.534722 [RX_INPUT] configuration <<<<<
7220 23:31:50.538641 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7221 23:31:50.544659 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7222 23:31:50.551646 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7223 23:31:50.558333 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7224 23:31:50.561721 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7225 23:31:50.568761 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7226 23:31:50.571816 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7227 23:31:50.578895 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7228 23:31:50.581957 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7229 23:31:50.585225 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7230 23:31:50.588664 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7231 23:31:50.594783 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7232 23:31:50.598258 ===================================
7233 23:31:50.598829 LPDDR4 DRAM CONFIGURATION
7234 23:31:50.601642 ===================================
7235 23:31:50.605163 EX_ROW_EN[0] = 0x0
7236 23:31:50.608138 EX_ROW_EN[1] = 0x0
7237 23:31:50.608600 LP4Y_EN = 0x0
7238 23:31:50.611380 WORK_FSP = 0x1
7239 23:31:50.611857 WL = 0x5
7240 23:31:50.615074 RL = 0x5
7241 23:31:50.615640 BL = 0x2
7242 23:31:50.618002 RPST = 0x0
7243 23:31:50.618464 RD_PRE = 0x0
7244 23:31:50.621194 WR_PRE = 0x1
7245 23:31:50.621700 WR_PST = 0x1
7246 23:31:50.624552 DBI_WR = 0x0
7247 23:31:50.625007 DBI_RD = 0x0
7248 23:31:50.627824 OTF = 0x1
7249 23:31:50.631938 ===================================
7250 23:31:50.634449 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7251 23:31:50.638318 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7252 23:31:50.644527 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7253 23:31:50.647961 ===================================
7254 23:31:50.648633 LPDDR4 DRAM CONFIGURATION
7255 23:31:50.651109 ===================================
7256 23:31:50.654518 EX_ROW_EN[0] = 0x10
7257 23:31:50.657813 EX_ROW_EN[1] = 0x0
7258 23:31:50.658481 LP4Y_EN = 0x0
7259 23:31:50.660941 WORK_FSP = 0x1
7260 23:31:50.661351 WL = 0x5
7261 23:31:50.664138 RL = 0x5
7262 23:31:50.664562 BL = 0x2
7263 23:31:50.667928 RPST = 0x0
7264 23:31:50.668629 RD_PRE = 0x0
7265 23:31:50.671022 WR_PRE = 0x1
7266 23:31:50.671442 WR_PST = 0x1
7267 23:31:50.674033 DBI_WR = 0x0
7268 23:31:50.674466 DBI_RD = 0x0
7269 23:31:50.677408 OTF = 0x1
7270 23:31:50.681128 ===================================
7271 23:31:50.687893 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7272 23:31:50.688427 ==
7273 23:31:50.690822 Dram Type= 6, Freq= 0, CH_0, rank 0
7274 23:31:50.694693 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7275 23:31:50.695115 ==
7276 23:31:50.697687 [Duty_Offset_Calibration]
7277 23:31:50.698104 B0:2 B1:1 CA:1
7278 23:31:50.698435
7279 23:31:50.701192 [DutyScan_Calibration_Flow] k_type=0
7280 23:31:50.711852
7281 23:31:50.712377 ==CLK 0==
7282 23:31:50.715185 Final CLK duty delay cell = 0
7283 23:31:50.718299 [0] MAX Duty = 5156%(X100), DQS PI = 22
7284 23:31:50.721081 [0] MIN Duty = 4907%(X100), DQS PI = 0
7285 23:31:50.721512 [0] AVG Duty = 5031%(X100)
7286 23:31:50.724818
7287 23:31:50.728095 CH0 CLK Duty spec in!! Max-Min= 249%
7288 23:31:50.731049 [DutyScan_Calibration_Flow] ====Done====
7289 23:31:50.731516
7290 23:31:50.734705 [DutyScan_Calibration_Flow] k_type=1
7291 23:31:50.750500
7292 23:31:50.751059 ==DQS 0 ==
7293 23:31:50.753844 Final DQS duty delay cell = -4
7294 23:31:50.756993 [-4] MAX Duty = 5125%(X100), DQS PI = 24
7295 23:31:50.760372 [-4] MIN Duty = 4688%(X100), DQS PI = 0
7296 23:31:50.763724 [-4] AVG Duty = 4906%(X100)
7297 23:31:50.764210
7298 23:31:50.764579 ==DQS 1 ==
7299 23:31:50.766691 Final DQS duty delay cell = 0
7300 23:31:50.770660 [0] MAX Duty = 5187%(X100), DQS PI = 4
7301 23:31:50.773532 [0] MIN Duty = 5062%(X100), DQS PI = 30
7302 23:31:50.776702 [0] AVG Duty = 5124%(X100)
7303 23:31:50.777165
7304 23:31:50.779853 CH0 DQS 0 Duty spec in!! Max-Min= 437%
7305 23:31:50.780263
7306 23:31:50.783654 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7307 23:31:50.786874 [DutyScan_Calibration_Flow] ====Done====
7308 23:31:50.787604
7309 23:31:50.790098 [DutyScan_Calibration_Flow] k_type=3
7310 23:31:50.806976
7311 23:31:50.807532 ==DQM 0 ==
7312 23:31:50.811043 Final DQM duty delay cell = 0
7313 23:31:50.813990 [0] MAX Duty = 5187%(X100), DQS PI = 30
7314 23:31:50.816808 [0] MIN Duty = 4907%(X100), DQS PI = 0
7315 23:31:50.817371 [0] AVG Duty = 5047%(X100)
7316 23:31:50.821053
7317 23:31:50.821666 ==DQM 1 ==
7318 23:31:50.823741 Final DQM duty delay cell = -4
7319 23:31:50.827032 [-4] MAX Duty = 4969%(X100), DQS PI = 20
7320 23:31:50.830496 [-4] MIN Duty = 4844%(X100), DQS PI = 12
7321 23:31:50.834123 [-4] AVG Duty = 4906%(X100)
7322 23:31:50.834696
7323 23:31:50.837340 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7324 23:31:50.837966
7325 23:31:50.840795 CH0 DQM 1 Duty spec in!! Max-Min= 125%
7326 23:31:50.843903 [DutyScan_Calibration_Flow] ====Done====
7327 23:31:50.844363
7328 23:31:50.847276 [DutyScan_Calibration_Flow] k_type=2
7329 23:31:50.864684
7330 23:31:50.865245 ==DQ 0 ==
7331 23:31:50.867657 Final DQ duty delay cell = 0
7332 23:31:50.871715 [0] MAX Duty = 5062%(X100), DQS PI = 24
7333 23:31:50.874731 [0] MIN Duty = 4907%(X100), DQS PI = 0
7334 23:31:50.875296 [0] AVG Duty = 4984%(X100)
7335 23:31:50.875665
7336 23:31:50.877902 ==DQ 1 ==
7337 23:31:50.881844 Final DQ duty delay cell = 0
7338 23:31:50.884877 [0] MAX Duty = 5125%(X100), DQS PI = 6
7339 23:31:50.888278 [0] MIN Duty = 4938%(X100), DQS PI = 34
7340 23:31:50.888842 [0] AVG Duty = 5031%(X100)
7341 23:31:50.889209
7342 23:31:50.891436 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7343 23:31:50.894314
7344 23:31:50.897873 CH0 DQ 1 Duty spec in!! Max-Min= 187%
7345 23:31:50.901005 [DutyScan_Calibration_Flow] ====Done====
7346 23:31:50.901464 ==
7347 23:31:50.904684 Dram Type= 6, Freq= 0, CH_1, rank 0
7348 23:31:50.907641 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7349 23:31:50.908110 ==
7350 23:31:50.911077 [Duty_Offset_Calibration]
7351 23:31:50.911537 B0:1 B1:0 CA:0
7352 23:31:50.911901
7353 23:31:50.914162 [DutyScan_Calibration_Flow] k_type=0
7354 23:31:50.924128
7355 23:31:50.924689 ==CLK 0==
7356 23:31:50.927512 Final CLK duty delay cell = -4
7357 23:31:50.930432 [-4] MAX Duty = 4969%(X100), DQS PI = 22
7358 23:31:50.933764 [-4] MIN Duty = 4844%(X100), DQS PI = 50
7359 23:31:50.937140 [-4] AVG Duty = 4906%(X100)
7360 23:31:50.937634
7361 23:31:50.940438 CH1 CLK Duty spec in!! Max-Min= 125%
7362 23:31:50.943865 [DutyScan_Calibration_Flow] ====Done====
7363 23:31:50.944325
7364 23:31:50.947273 [DutyScan_Calibration_Flow] k_type=1
7365 23:31:50.964285
7366 23:31:50.964806 ==DQS 0 ==
7367 23:31:50.967654 Final DQS duty delay cell = 0
7368 23:31:50.970390 [0] MAX Duty = 5094%(X100), DQS PI = 18
7369 23:31:50.973986 [0] MIN Duty = 4844%(X100), DQS PI = 48
7370 23:31:50.977280 [0] AVG Duty = 4969%(X100)
7371 23:31:50.977877
7372 23:31:50.978220 ==DQS 1 ==
7373 23:31:50.980682 Final DQS duty delay cell = 0
7374 23:31:50.984209 [0] MAX Duty = 5249%(X100), DQS PI = 18
7375 23:31:50.987149 [0] MIN Duty = 4938%(X100), DQS PI = 8
7376 23:31:50.990423 [0] AVG Duty = 5093%(X100)
7377 23:31:50.990990
7378 23:31:50.993541 CH1 DQS 0 Duty spec in!! Max-Min= 250%
7379 23:31:50.994054
7380 23:31:50.997145 CH1 DQS 1 Duty spec in!! Max-Min= 311%
7381 23:31:51.000338 [DutyScan_Calibration_Flow] ====Done====
7382 23:31:51.000800
7383 23:31:51.003500 [DutyScan_Calibration_Flow] k_type=3
7384 23:31:51.021122
7385 23:31:51.021947 ==DQM 0 ==
7386 23:31:51.024117 Final DQM duty delay cell = 0
7387 23:31:51.027910 [0] MAX Duty = 5218%(X100), DQS PI = 20
7388 23:31:51.030656 [0] MIN Duty = 4969%(X100), DQS PI = 48
7389 23:31:51.031119 [0] AVG Duty = 5093%(X100)
7390 23:31:51.034201
7391 23:31:51.034657 ==DQM 1 ==
7392 23:31:51.037340 Final DQM duty delay cell = 0
7393 23:31:51.041098 [0] MAX Duty = 5062%(X100), DQS PI = 14
7394 23:31:51.044377 [0] MIN Duty = 4907%(X100), DQS PI = 34
7395 23:31:51.044910 [0] AVG Duty = 4984%(X100)
7396 23:31:51.047857
7397 23:31:51.050818 CH1 DQM 0 Duty spec in!! Max-Min= 249%
7398 23:31:51.051354
7399 23:31:51.054215 CH1 DQM 1 Duty spec in!! Max-Min= 155%
7400 23:31:51.057948 [DutyScan_Calibration_Flow] ====Done====
7401 23:31:51.058501
7402 23:31:51.061098 [DutyScan_Calibration_Flow] k_type=2
7403 23:31:51.077496
7404 23:31:51.078108 ==DQ 0 ==
7405 23:31:51.080759 Final DQ duty delay cell = -4
7406 23:31:51.084176 [-4] MAX Duty = 5062%(X100), DQS PI = 10
7407 23:31:51.086974 [-4] MIN Duty = 4875%(X100), DQS PI = 46
7408 23:31:51.090380 [-4] AVG Duty = 4968%(X100)
7409 23:31:51.090932
7410 23:31:51.091295 ==DQ 1 ==
7411 23:31:51.093647 Final DQ duty delay cell = 0
7412 23:31:51.097232 [0] MAX Duty = 5124%(X100), DQS PI = 18
7413 23:31:51.100389 [0] MIN Duty = 4938%(X100), DQS PI = 8
7414 23:31:51.103179 [0] AVG Duty = 5031%(X100)
7415 23:31:51.103639
7416 23:31:51.106891 CH1 DQ 0 Duty spec in!! Max-Min= 187%
7417 23:31:51.107353
7418 23:31:51.110548 CH1 DQ 1 Duty spec in!! Max-Min= 186%
7419 23:31:51.113787 [DutyScan_Calibration_Flow] ====Done====
7420 23:31:51.116580 nWR fixed to 30
7421 23:31:51.120642 [ModeRegInit_LP4] CH0 RK0
7422 23:31:51.121198 [ModeRegInit_LP4] CH0 RK1
7423 23:31:51.123492 [ModeRegInit_LP4] CH1 RK0
7424 23:31:51.126746 [ModeRegInit_LP4] CH1 RK1
7425 23:31:51.127217 match AC timing 5
7426 23:31:51.133323 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7427 23:31:51.136646 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7428 23:31:51.140353 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7429 23:31:51.147003 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7430 23:31:51.150173 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7431 23:31:51.150646 [MiockJmeterHQA]
7432 23:31:51.151035
7433 23:31:51.153192 [DramcMiockJmeter] u1RxGatingPI = 0
7434 23:31:51.156908 0 : 4252, 4027
7435 23:31:51.157381 4 : 4363, 4137
7436 23:31:51.159847 8 : 4255, 4027
7437 23:31:51.160339 12 : 4252, 4027
7438 23:31:51.160717 16 : 4252, 4027
7439 23:31:51.163058 20 : 4252, 4027
7440 23:31:51.163529 24 : 4255, 4029
7441 23:31:51.166605 28 : 4253, 4026
7442 23:31:51.167077 32 : 4252, 4027
7443 23:31:51.170486 36 : 4365, 4140
7444 23:31:51.170951 40 : 4252, 4027
7445 23:31:51.172918 44 : 4255, 4029
7446 23:31:51.173358 48 : 4252, 4027
7447 23:31:51.173740 52 : 4363, 4137
7448 23:31:51.176628 56 : 4253, 4026
7449 23:31:51.177155 60 : 4360, 4138
7450 23:31:51.180465 64 : 4250, 4027
7451 23:31:51.180993 68 : 4250, 4027
7452 23:31:51.183128 72 : 4252, 4027
7453 23:31:51.183554 76 : 4252, 4029
7454 23:31:51.186943 80 : 4360, 4138
7455 23:31:51.187467 84 : 4250, 4027
7456 23:31:51.187811 88 : 4361, 113
7457 23:31:51.190111 92 : 4360, 0
7458 23:31:51.190634 96 : 4361, 0
7459 23:31:51.190974 100 : 4250, 0
7460 23:31:51.193285 104 : 4250, 0
7461 23:31:51.193744 108 : 4250, 0
7462 23:31:51.197102 112 : 4361, 0
7463 23:31:51.197677 116 : 4361, 0
7464 23:31:51.198030 120 : 4250, 0
7465 23:31:51.199700 124 : 4250, 0
7466 23:31:51.200124 128 : 4363, 0
7467 23:31:51.202959 132 : 4250, 0
7468 23:31:51.203383 136 : 4249, 0
7469 23:31:51.203721 140 : 4250, 0
7470 23:31:51.206265 144 : 4252, 0
7471 23:31:51.206693 148 : 4360, 0
7472 23:31:51.209827 152 : 4250, 0
7473 23:31:51.210361 156 : 4250, 0
7474 23:31:51.210704 160 : 4360, 0
7475 23:31:51.212890 164 : 4361, 0
7476 23:31:51.213309 168 : 4363, 0
7477 23:31:51.216717 172 : 4250, 0
7478 23:31:51.217238 176 : 4361, 0
7479 23:31:51.217618 180 : 4361, 0
7480 23:31:51.219621 184 : 4250, 0
7481 23:31:51.220042 188 : 4250, 0
7482 23:31:51.220376 192 : 4250, 0
7483 23:31:51.223040 196 : 4250, 0
7484 23:31:51.223459 200 : 4361, 0
7485 23:31:51.226965 204 : 4250, 1105
7486 23:31:51.227530 208 : 4250, 3999
7487 23:31:51.229648 212 : 4249, 4027
7488 23:31:51.230119 216 : 4250, 4027
7489 23:31:51.233151 220 : 4250, 4026
7490 23:31:51.233657 224 : 4252, 4027
7491 23:31:51.234039 228 : 4249, 4027
7492 23:31:51.236599 232 : 4252, 4029
7493 23:31:51.237192 236 : 4250, 4026
7494 23:31:51.239470 240 : 4361, 4137
7495 23:31:51.240032 244 : 4361, 4138
7496 23:31:51.243108 248 : 4250, 4027
7497 23:31:51.243575 252 : 4363, 4140
7498 23:31:51.246629 256 : 4250, 4026
7499 23:31:51.247093 260 : 4250, 4027
7500 23:31:51.249789 264 : 4250, 4027
7501 23:31:51.250354 268 : 4252, 4029
7502 23:31:51.252718 272 : 4250, 4027
7503 23:31:51.253184 276 : 4250, 4027
7504 23:31:51.256149 280 : 4250, 4027
7505 23:31:51.256614 284 : 4252, 4029
7506 23:31:51.259504 288 : 4250, 4026
7507 23:31:51.260071 292 : 4361, 4137
7508 23:31:51.260446 296 : 4361, 4138
7509 23:31:51.262931 300 : 4250, 4027
7510 23:31:51.263396 304 : 4363, 4140
7511 23:31:51.265770 308 : 4250, 3974
7512 23:31:51.266238 312 : 4250, 2151
7513 23:31:51.269353 316 : 4250, 8
7514 23:31:51.269800
7515 23:31:51.270162 MIOCK jitter meter ch=0
7516 23:31:51.272831
7517 23:31:51.273284 1T = (316-88) = 228 dly cells
7518 23:31:51.279431 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 285/100 ps
7519 23:31:51.279965 ==
7520 23:31:51.282549 Dram Type= 6, Freq= 0, CH_0, rank 0
7521 23:31:51.286003 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7522 23:31:51.286578 ==
7523 23:31:51.292242 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7524 23:31:51.295847 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7525 23:31:51.302839 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7526 23:31:51.305453 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7527 23:31:51.316351 [CA 0] Center 42 (12~73) winsize 62
7528 23:31:51.319032 [CA 1] Center 42 (12~73) winsize 62
7529 23:31:51.322560 [CA 2] Center 38 (8~68) winsize 61
7530 23:31:51.325928 [CA 3] Center 37 (8~67) winsize 60
7531 23:31:51.329676 [CA 4] Center 36 (6~66) winsize 61
7532 23:31:51.332764 [CA 5] Center 35 (6~64) winsize 59
7533 23:31:51.333328
7534 23:31:51.335901 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7535 23:31:51.336368
7536 23:31:51.339660 [CATrainingPosCal] consider 1 rank data
7537 23:31:51.343003 u2DelayCellTimex100 = 285/100 ps
7538 23:31:51.345694 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7539 23:31:51.352737 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7540 23:31:51.355976 CA2 delay=38 (8~68),Diff = 3 PI (10 cell)
7541 23:31:51.359162 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7542 23:31:51.362940 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7543 23:31:51.365791 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7544 23:31:51.366259
7545 23:31:51.369496 CA PerBit enable=1, Macro0, CA PI delay=35
7546 23:31:51.370127
7547 23:31:51.372779 [CBTSetCACLKResult] CA Dly = 35
7548 23:31:51.376022 CS Dly: 8 (0~39)
7549 23:31:51.379326 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7550 23:31:51.382361 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7551 23:31:51.382825 ==
7552 23:31:51.386042 Dram Type= 6, Freq= 0, CH_0, rank 1
7553 23:31:51.389316 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7554 23:31:51.392655 ==
7555 23:31:51.396149 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7556 23:31:51.398975 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7557 23:31:51.405698 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7558 23:31:51.409108 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7559 23:31:51.419544 [CA 0] Center 42 (12~73) winsize 62
7560 23:31:51.422480 [CA 1] Center 42 (12~73) winsize 62
7561 23:31:51.425847 [CA 2] Center 38 (8~68) winsize 61
7562 23:31:51.429192 [CA 3] Center 37 (8~67) winsize 60
7563 23:31:51.432802 [CA 4] Center 36 (6~66) winsize 61
7564 23:31:51.435730 [CA 5] Center 35 (5~65) winsize 61
7565 23:31:51.436196
7566 23:31:51.439833 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7567 23:31:51.440404
7568 23:31:51.442396 [CATrainingPosCal] consider 2 rank data
7569 23:31:51.445812 u2DelayCellTimex100 = 285/100 ps
7570 23:31:51.449493 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7571 23:31:51.455716 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7572 23:31:51.458893 CA2 delay=38 (8~68),Diff = 3 PI (10 cell)
7573 23:31:51.462228 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7574 23:31:51.465972 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7575 23:31:51.469171 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7576 23:31:51.469719
7577 23:31:51.472188 CA PerBit enable=1, Macro0, CA PI delay=35
7578 23:31:51.472663
7579 23:31:51.475868 [CBTSetCACLKResult] CA Dly = 35
7580 23:31:51.479085 CS Dly: 9 (0~42)
7581 23:31:51.482570 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7582 23:31:51.485538 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7583 23:31:51.486039
7584 23:31:51.489151 ----->DramcWriteLeveling(PI) begin...
7585 23:31:51.489775 ==
7586 23:31:51.492430 Dram Type= 6, Freq= 0, CH_0, rank 0
7587 23:31:51.499214 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7588 23:31:51.499787 ==
7589 23:31:51.502356 Write leveling (Byte 0): 37 => 37
7590 23:31:51.502835 Write leveling (Byte 1): 29 => 29
7591 23:31:51.505889 DramcWriteLeveling(PI) end<-----
7592 23:31:51.506460
7593 23:31:51.506834 ==
7594 23:31:51.509134 Dram Type= 6, Freq= 0, CH_0, rank 0
7595 23:31:51.515975 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7596 23:31:51.516547 ==
7597 23:31:51.518637 [Gating] SW mode calibration
7598 23:31:51.525692 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7599 23:31:51.528952 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7600 23:31:51.535138 1 4 0 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
7601 23:31:51.538608 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7602 23:31:51.542085 1 4 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7603 23:31:51.548620 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7604 23:31:51.551580 1 4 16 | B1->B0 | 2323 3737 | 0 1 | (0 0) (1 1)
7605 23:31:51.555417 1 4 20 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
7606 23:31:51.561669 1 4 24 | B1->B0 | 3434 3636 | 1 1 | (1 1) (1 1)
7607 23:31:51.565193 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7608 23:31:51.568429 1 5 0 | B1->B0 | 3434 3535 | 1 1 | (1 1) (0 0)
7609 23:31:51.571905 1 5 4 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
7610 23:31:51.578593 1 5 8 | B1->B0 | 3434 3535 | 1 0 | (1 1) (1 1)
7611 23:31:51.581538 1 5 12 | B1->B0 | 3434 2424 | 1 0 | (1 1) (1 0)
7612 23:31:51.585310 1 5 16 | B1->B0 | 3434 2424 | 1 0 | (1 1) (0 0)
7613 23:31:51.591985 1 5 20 | B1->B0 | 2727 2424 | 0 0 | (1 0) (0 0)
7614 23:31:51.595271 1 5 24 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7615 23:31:51.598845 1 5 28 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
7616 23:31:51.605545 1 6 0 | B1->B0 | 2323 2424 | 0 1 | (0 0) (0 0)
7617 23:31:51.608977 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7618 23:31:51.612108 1 6 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7619 23:31:51.618822 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7620 23:31:51.622393 1 6 16 | B1->B0 | 2727 4646 | 0 0 | (0 0) (0 0)
7621 23:31:51.625831 1 6 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
7622 23:31:51.631849 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7623 23:31:51.635152 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7624 23:31:51.638621 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7625 23:31:51.645282 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7626 23:31:51.648628 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7627 23:31:51.651756 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7628 23:31:51.658497 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7629 23:31:51.661747 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7630 23:31:51.664974 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7631 23:31:51.671419 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7632 23:31:51.675032 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7633 23:31:51.678032 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7634 23:31:51.685137 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7635 23:31:51.688312 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7636 23:31:51.691374 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7637 23:31:51.698306 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7638 23:31:51.701017 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7639 23:31:51.705229 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7640 23:31:51.711267 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7641 23:31:51.714402 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7642 23:31:51.717915 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7643 23:31:51.721330 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7644 23:31:51.727878 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7645 23:31:51.731497 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7646 23:31:51.734957 Total UI for P1: 0, mck2ui 16
7647 23:31:51.738201 best dqsien dly found for B0: ( 1, 9, 14)
7648 23:31:51.741251 Total UI for P1: 0, mck2ui 16
7649 23:31:51.744385 best dqsien dly found for B1: ( 1, 9, 18)
7650 23:31:51.747937 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
7651 23:31:51.751420 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7652 23:31:51.752028
7653 23:31:51.754448 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
7654 23:31:51.760844 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7655 23:31:51.761414 [Gating] SW calibration Done
7656 23:31:51.761903 ==
7657 23:31:51.764092 Dram Type= 6, Freq= 0, CH_0, rank 0
7658 23:31:51.771158 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7659 23:31:51.771743 ==
7660 23:31:51.772116 RX Vref Scan: 0
7661 23:31:51.772464
7662 23:31:51.774362 RX Vref 0 -> 0, step: 1
7663 23:31:51.774826
7664 23:31:51.777367 RX Delay 0 -> 252, step: 8
7665 23:31:51.780885 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
7666 23:31:51.784045 iDelay=200, Bit 1, Center 143 (88 ~ 199) 112
7667 23:31:51.788055 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
7668 23:31:51.794419 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7669 23:31:51.797714 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7670 23:31:51.800570 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7671 23:31:51.804445 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7672 23:31:51.808090 iDelay=200, Bit 7, Center 143 (96 ~ 191) 96
7673 23:31:51.810463 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
7674 23:31:51.817275 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
7675 23:31:51.820456 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
7676 23:31:51.823812 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7677 23:31:51.827194 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
7678 23:31:51.833791 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7679 23:31:51.836940 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7680 23:31:51.840472 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7681 23:31:51.841044 ==
7682 23:31:51.843779 Dram Type= 6, Freq= 0, CH_0, rank 0
7683 23:31:51.847263 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7684 23:31:51.847737 ==
7685 23:31:51.850356 DQS Delay:
7686 23:31:51.850817 DQS0 = 0, DQS1 = 0
7687 23:31:51.853917 DQM Delay:
7688 23:31:51.854436 DQM0 = 137, DQM1 = 129
7689 23:31:51.854831 DQ Delay:
7690 23:31:51.860889 DQ0 =135, DQ1 =143, DQ2 =135, DQ3 =131
7691 23:31:51.863705 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =143
7692 23:31:51.867193 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
7693 23:31:51.870268 DQ12 =135, DQ13 =135, DQ14 =139, DQ15 =135
7694 23:31:51.870836
7695 23:31:51.871203
7696 23:31:51.871545 ==
7697 23:31:51.873881 Dram Type= 6, Freq= 0, CH_0, rank 0
7698 23:31:51.877089 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7699 23:31:51.877720 ==
7700 23:31:51.878104
7701 23:31:51.878451
7702 23:31:51.880321 TX Vref Scan disable
7703 23:31:51.884093 == TX Byte 0 ==
7704 23:31:51.886703 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
7705 23:31:51.889836 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7706 23:31:51.893556 == TX Byte 1 ==
7707 23:31:51.897075 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7708 23:31:51.899653 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7709 23:31:51.900118 ==
7710 23:31:51.903135 Dram Type= 6, Freq= 0, CH_0, rank 0
7711 23:31:51.910025 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7712 23:31:51.910602 ==
7713 23:31:51.922328
7714 23:31:51.925436 TX Vref early break, caculate TX vref
7715 23:31:51.928759 TX Vref=16, minBit 0, minWin=23, winSum=379
7716 23:31:51.931827 TX Vref=18, minBit 7, minWin=22, winSum=382
7717 23:31:51.935166 TX Vref=20, minBit 0, minWin=23, winSum=396
7718 23:31:51.938895 TX Vref=22, minBit 0, minWin=23, winSum=403
7719 23:31:51.942334 TX Vref=24, minBit 0, minWin=25, winSum=415
7720 23:31:51.948633 TX Vref=26, minBit 2, minWin=25, winSum=420
7721 23:31:51.951858 TX Vref=28, minBit 0, minWin=25, winSum=423
7722 23:31:51.954737 TX Vref=30, minBit 2, minWin=24, winSum=413
7723 23:31:51.958453 TX Vref=32, minBit 0, minWin=24, winSum=402
7724 23:31:51.961869 TX Vref=34, minBit 0, minWin=24, winSum=398
7725 23:31:51.968510 [TxChooseVref] Worse bit 0, Min win 25, Win sum 423, Final Vref 28
7726 23:31:51.969080
7727 23:31:51.971794 Final TX Range 0 Vref 28
7728 23:31:51.972366
7729 23:31:51.972734 ==
7730 23:31:51.974847 Dram Type= 6, Freq= 0, CH_0, rank 0
7731 23:31:51.977879 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7732 23:31:51.978349 ==
7733 23:31:51.978722
7734 23:31:51.979064
7735 23:31:51.981244 TX Vref Scan disable
7736 23:31:51.988382 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
7737 23:31:51.988954 == TX Byte 0 ==
7738 23:31:51.991489 u2DelayCellOfst[0]=10 cells (3 PI)
7739 23:31:51.995025 u2DelayCellOfst[1]=13 cells (4 PI)
7740 23:31:51.998376 u2DelayCellOfst[2]=10 cells (3 PI)
7741 23:31:52.001641 u2DelayCellOfst[3]=6 cells (2 PI)
7742 23:31:52.004872 u2DelayCellOfst[4]=6 cells (2 PI)
7743 23:31:52.008485 u2DelayCellOfst[5]=0 cells (0 PI)
7744 23:31:52.011275 u2DelayCellOfst[6]=17 cells (5 PI)
7745 23:31:52.014981 u2DelayCellOfst[7]=13 cells (4 PI)
7746 23:31:52.018161 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7747 23:31:52.021402 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7748 23:31:52.025026 == TX Byte 1 ==
7749 23:31:52.028249 u2DelayCellOfst[8]=0 cells (0 PI)
7750 23:31:52.028822 u2DelayCellOfst[9]=0 cells (0 PI)
7751 23:31:52.031843 u2DelayCellOfst[10]=6 cells (2 PI)
7752 23:31:52.034840 u2DelayCellOfst[11]=3 cells (1 PI)
7753 23:31:52.037746 u2DelayCellOfst[12]=10 cells (3 PI)
7754 23:31:52.041181 u2DelayCellOfst[13]=13 cells (4 PI)
7755 23:31:52.044979 u2DelayCellOfst[14]=13 cells (4 PI)
7756 23:31:52.048069 u2DelayCellOfst[15]=10 cells (3 PI)
7757 23:31:52.051253 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7758 23:31:52.057820 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7759 23:31:52.058288 DramC Write-DBI on
7760 23:31:52.058658 ==
7761 23:31:52.061282 Dram Type= 6, Freq= 0, CH_0, rank 0
7762 23:31:52.064922 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7763 23:31:52.068076 ==
7764 23:31:52.068646
7765 23:31:52.069014
7766 23:31:52.069357 TX Vref Scan disable
7767 23:31:52.071354 == TX Byte 0 ==
7768 23:31:52.075034 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
7769 23:31:52.078636 == TX Byte 1 ==
7770 23:31:52.081763 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7771 23:31:52.084766 DramC Write-DBI off
7772 23:31:52.085231
7773 23:31:52.085641 [DATLAT]
7774 23:31:52.085997 Freq=1600, CH0 RK0
7775 23:31:52.086336
7776 23:31:52.088361 DATLAT Default: 0xf
7777 23:31:52.088926 0, 0xFFFF, sum = 0
7778 23:31:52.091997 1, 0xFFFF, sum = 0
7779 23:31:52.092573 2, 0xFFFF, sum = 0
7780 23:31:52.094950 3, 0xFFFF, sum = 0
7781 23:31:52.098458 4, 0xFFFF, sum = 0
7782 23:31:52.099040 5, 0xFFFF, sum = 0
7783 23:31:52.101372 6, 0xFFFF, sum = 0
7784 23:31:52.101886 7, 0xFFFF, sum = 0
7785 23:31:52.104879 8, 0xFFFF, sum = 0
7786 23:31:52.105454 9, 0xFFFF, sum = 0
7787 23:31:52.108219 10, 0xFFFF, sum = 0
7788 23:31:52.108798 11, 0xFFFF, sum = 0
7789 23:31:52.111368 12, 0xFFFF, sum = 0
7790 23:31:52.111948 13, 0xFFFF, sum = 0
7791 23:31:52.114919 14, 0x0, sum = 1
7792 23:31:52.115497 15, 0x0, sum = 2
7793 23:31:52.117707 16, 0x0, sum = 3
7794 23:31:52.118179 17, 0x0, sum = 4
7795 23:31:52.121066 best_step = 15
7796 23:31:52.121530
7797 23:31:52.121935 ==
7798 23:31:52.124809 Dram Type= 6, Freq= 0, CH_0, rank 0
7799 23:31:52.128175 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7800 23:31:52.128921 ==
7801 23:31:52.131073 RX Vref Scan: 1
7802 23:31:52.131536
7803 23:31:52.131907 Set Vref Range= 24 -> 127
7804 23:31:52.132252
7805 23:31:52.134929 RX Vref 24 -> 127, step: 1
7806 23:31:52.135496
7807 23:31:52.137905 RX Delay 19 -> 252, step: 4
7808 23:31:52.138425
7809 23:31:52.141614 Set Vref, RX VrefLevel [Byte0]: 24
7810 23:31:52.144242 [Byte1]: 24
7811 23:31:52.144706
7812 23:31:52.148183 Set Vref, RX VrefLevel [Byte0]: 25
7813 23:31:52.151284 [Byte1]: 25
7814 23:31:52.154477
7815 23:31:52.154942 Set Vref, RX VrefLevel [Byte0]: 26
7816 23:31:52.157505 [Byte1]: 26
7817 23:31:52.161629
7818 23:31:52.162210 Set Vref, RX VrefLevel [Byte0]: 27
7819 23:31:52.164940 [Byte1]: 27
7820 23:31:52.169670
7821 23:31:52.170257 Set Vref, RX VrefLevel [Byte0]: 28
7822 23:31:52.172822 [Byte1]: 28
7823 23:31:52.176930
7824 23:31:52.177497 Set Vref, RX VrefLevel [Byte0]: 29
7825 23:31:52.179961 [Byte1]: 29
7826 23:31:52.184873
7827 23:31:52.185447 Set Vref, RX VrefLevel [Byte0]: 30
7828 23:31:52.187674 [Byte1]: 30
7829 23:31:52.192049
7830 23:31:52.195158 Set Vref, RX VrefLevel [Byte0]: 31
7831 23:31:52.195627 [Byte1]: 31
7832 23:31:52.199547
7833 23:31:52.200112 Set Vref, RX VrefLevel [Byte0]: 32
7834 23:31:52.202836 [Byte1]: 32
7835 23:31:52.207517
7836 23:31:52.208087 Set Vref, RX VrefLevel [Byte0]: 33
7837 23:31:52.210927 [Byte1]: 33
7838 23:31:52.214762
7839 23:31:52.215228 Set Vref, RX VrefLevel [Byte0]: 34
7840 23:31:52.218276 [Byte1]: 34
7841 23:31:52.222184
7842 23:31:52.222646 Set Vref, RX VrefLevel [Byte0]: 35
7843 23:31:52.225489 [Byte1]: 35
7844 23:31:52.230076
7845 23:31:52.230671 Set Vref, RX VrefLevel [Byte0]: 36
7846 23:31:52.233520 [Byte1]: 36
7847 23:31:52.237796
7848 23:31:52.238357 Set Vref, RX VrefLevel [Byte0]: 37
7849 23:31:52.240950 [Byte1]: 37
7850 23:31:52.245454
7851 23:31:52.246081 Set Vref, RX VrefLevel [Byte0]: 38
7852 23:31:52.248543 [Byte1]: 38
7853 23:31:52.253087
7854 23:31:52.253720 Set Vref, RX VrefLevel [Byte0]: 39
7855 23:31:52.255727 [Byte1]: 39
7856 23:31:52.260513
7857 23:31:52.261062 Set Vref, RX VrefLevel [Byte0]: 40
7858 23:31:52.264018 [Byte1]: 40
7859 23:31:52.268147
7860 23:31:52.268715 Set Vref, RX VrefLevel [Byte0]: 41
7861 23:31:52.271403 [Byte1]: 41
7862 23:31:52.275463
7863 23:31:52.276217 Set Vref, RX VrefLevel [Byte0]: 42
7864 23:31:52.278850 [Byte1]: 42
7865 23:31:52.283281
7866 23:31:52.283849 Set Vref, RX VrefLevel [Byte0]: 43
7867 23:31:52.286983 [Byte1]: 43
7868 23:31:52.290808
7869 23:31:52.291382 Set Vref, RX VrefLevel [Byte0]: 44
7870 23:31:52.294001 [Byte1]: 44
7871 23:31:52.298372
7872 23:31:52.298834 Set Vref, RX VrefLevel [Byte0]: 45
7873 23:31:52.301141 [Byte1]: 45
7874 23:31:52.306075
7875 23:31:52.306646 Set Vref, RX VrefLevel [Byte0]: 46
7876 23:31:52.309617 [Byte1]: 46
7877 23:31:52.314177
7878 23:31:52.314745 Set Vref, RX VrefLevel [Byte0]: 47
7879 23:31:52.316591 [Byte1]: 47
7880 23:31:52.320915
7881 23:31:52.321381 Set Vref, RX VrefLevel [Byte0]: 48
7882 23:31:52.327415 [Byte1]: 48
7883 23:31:52.327998
7884 23:31:52.330755 Set Vref, RX VrefLevel [Byte0]: 49
7885 23:31:52.333790 [Byte1]: 49
7886 23:31:52.334253
7887 23:31:52.337134 Set Vref, RX VrefLevel [Byte0]: 50
7888 23:31:52.340860 [Byte1]: 50
7889 23:31:52.341427
7890 23:31:52.343948 Set Vref, RX VrefLevel [Byte0]: 51
7891 23:31:52.347264 [Byte1]: 51
7892 23:31:52.351514
7893 23:31:52.352088 Set Vref, RX VrefLevel [Byte0]: 52
7894 23:31:52.354420 [Byte1]: 52
7895 23:31:52.358773
7896 23:31:52.359238 Set Vref, RX VrefLevel [Byte0]: 53
7897 23:31:52.362201 [Byte1]: 53
7898 23:31:52.366477
7899 23:31:52.367149 Set Vref, RX VrefLevel [Byte0]: 54
7900 23:31:52.369890 [Byte1]: 54
7901 23:31:52.373766
7902 23:31:52.374345 Set Vref, RX VrefLevel [Byte0]: 55
7903 23:31:52.377307 [Byte1]: 55
7904 23:31:52.381723
7905 23:31:52.382340 Set Vref, RX VrefLevel [Byte0]: 56
7906 23:31:52.384932 [Byte1]: 56
7907 23:31:52.388921
7908 23:31:52.389560 Set Vref, RX VrefLevel [Byte0]: 57
7909 23:31:52.392377 [Byte1]: 57
7910 23:31:52.396549
7911 23:31:52.397145 Set Vref, RX VrefLevel [Byte0]: 58
7912 23:31:52.399666 [Byte1]: 58
7913 23:31:52.404520
7914 23:31:52.405089 Set Vref, RX VrefLevel [Byte0]: 59
7915 23:31:52.407741 [Byte1]: 59
7916 23:31:52.412035
7917 23:31:52.412600 Set Vref, RX VrefLevel [Byte0]: 60
7918 23:31:52.415015 [Byte1]: 60
7919 23:31:52.419241
7920 23:31:52.419749 Set Vref, RX VrefLevel [Byte0]: 61
7921 23:31:52.425941 [Byte1]: 61
7922 23:31:52.426497
7923 23:31:52.429213 Set Vref, RX VrefLevel [Byte0]: 62
7924 23:31:52.432556 [Byte1]: 62
7925 23:31:52.433020
7926 23:31:52.435796 Set Vref, RX VrefLevel [Byte0]: 63
7927 23:31:52.438773 [Byte1]: 63
7928 23:31:52.439239
7929 23:31:52.442169 Set Vref, RX VrefLevel [Byte0]: 64
7930 23:31:52.445493 [Byte1]: 64
7931 23:31:52.449416
7932 23:31:52.449917 Set Vref, RX VrefLevel [Byte0]: 65
7933 23:31:52.452787 [Byte1]: 65
7934 23:31:52.457193
7935 23:31:52.457698 Set Vref, RX VrefLevel [Byte0]: 66
7936 23:31:52.460683 [Byte1]: 66
7937 23:31:52.464793
7938 23:31:52.465362 Set Vref, RX VrefLevel [Byte0]: 67
7939 23:31:52.467964 [Byte1]: 67
7940 23:31:52.472294
7941 23:31:52.472858 Set Vref, RX VrefLevel [Byte0]: 68
7942 23:31:52.475574 [Byte1]: 68
7943 23:31:52.480376
7944 23:31:52.480951 Set Vref, RX VrefLevel [Byte0]: 69
7945 23:31:52.482802 [Byte1]: 69
7946 23:31:52.487867
7947 23:31:52.488433 Set Vref, RX VrefLevel [Byte0]: 70
7948 23:31:52.490677 [Byte1]: 70
7949 23:31:52.495115
7950 23:31:52.495713 Set Vref, RX VrefLevel [Byte0]: 71
7951 23:31:52.498302 [Byte1]: 71
7952 23:31:52.502722
7953 23:31:52.503281 Set Vref, RX VrefLevel [Byte0]: 72
7954 23:31:52.505986 [Byte1]: 72
7955 23:31:52.510460
7956 23:31:52.511020 Set Vref, RX VrefLevel [Byte0]: 73
7957 23:31:52.513153 [Byte1]: 73
7958 23:31:52.518006
7959 23:31:52.518610 Set Vref, RX VrefLevel [Byte0]: 74
7960 23:31:52.521305 [Byte1]: 74
7961 23:31:52.525119
7962 23:31:52.525739 Set Vref, RX VrefLevel [Byte0]: 75
7963 23:31:52.528956 [Byte1]: 75
7964 23:31:52.532860
7965 23:31:52.533428 Final RX Vref Byte 0 = 60 to rank0
7966 23:31:52.536286 Final RX Vref Byte 1 = 59 to rank0
7967 23:31:52.539116 Final RX Vref Byte 0 = 60 to rank1
7968 23:31:52.543054 Final RX Vref Byte 1 = 59 to rank1==
7969 23:31:52.546828 Dram Type= 6, Freq= 0, CH_0, rank 0
7970 23:31:52.552657 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7971 23:31:52.553131 ==
7972 23:31:52.553560 DQS Delay:
7973 23:31:52.553986 DQS0 = 0, DQS1 = 0
7974 23:31:52.556183 DQM Delay:
7975 23:31:52.556649 DQM0 = 134, DQM1 = 127
7976 23:31:52.559388 DQ Delay:
7977 23:31:52.563012 DQ0 =134, DQ1 =138, DQ2 =134, DQ3 =132
7978 23:31:52.566174 DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =140
7979 23:31:52.569360 DQ8 =116, DQ9 =118, DQ10 =130, DQ11 =120
7980 23:31:52.573029 DQ12 =134, DQ13 =132, DQ14 =138, DQ15 =134
7981 23:31:52.573645
7982 23:31:52.574035
7983 23:31:52.574380
7984 23:31:52.576703 [DramC_TX_OE_Calibration] TA2
7985 23:31:52.579309 Original DQ_B0 (3 6) =30, OEN = 27
7986 23:31:52.583201 Original DQ_B1 (3 6) =30, OEN = 27
7987 23:31:52.586037 24, 0x0, End_B0=24 End_B1=24
7988 23:31:52.586616 25, 0x0, End_B0=25 End_B1=25
7989 23:31:52.589419 26, 0x0, End_B0=26 End_B1=26
7990 23:31:52.592614 27, 0x0, End_B0=27 End_B1=27
7991 23:31:52.595997 28, 0x0, End_B0=28 End_B1=28
7992 23:31:52.596573 29, 0x0, End_B0=29 End_B1=29
7993 23:31:52.599143 30, 0x0, End_B0=30 End_B1=30
7994 23:31:52.602601 31, 0x4141, End_B0=30 End_B1=30
7995 23:31:52.605871 Byte0 end_step=30 best_step=27
7996 23:31:52.609409 Byte1 end_step=30 best_step=27
7997 23:31:52.612667 Byte0 TX OE(2T, 0.5T) = (3, 3)
7998 23:31:52.613244 Byte1 TX OE(2T, 0.5T) = (3, 3)
7999 23:31:52.615849
8000 23:31:52.616311
8001 23:31:52.622610 [DQSOSCAuto] RK0, (LSB)MR18= 0x221d, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 392 ps
8002 23:31:52.626042 CH0 RK0: MR19=303, MR18=221D
8003 23:31:52.632800 CH0_RK0: MR19=0x303, MR18=0x221D, DQSOSC=392, MR23=63, INC=24, DEC=16
8004 23:31:52.633357
8005 23:31:52.636447 ----->DramcWriteLeveling(PI) begin...
8006 23:31:52.637022 ==
8007 23:31:52.639327 Dram Type= 6, Freq= 0, CH_0, rank 1
8008 23:31:52.642462 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8009 23:31:52.642932 ==
8010 23:31:52.645937 Write leveling (Byte 0): 36 => 36
8011 23:31:52.649266 Write leveling (Byte 1): 28 => 28
8012 23:31:52.652607 DramcWriteLeveling(PI) end<-----
8013 23:31:52.653217
8014 23:31:52.653662 ==
8015 23:31:52.655578 Dram Type= 6, Freq= 0, CH_0, rank 1
8016 23:31:52.658786 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8017 23:31:52.659290 ==
8018 23:31:52.662170 [Gating] SW mode calibration
8019 23:31:52.669140 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8020 23:31:52.676007 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8021 23:31:52.679395 1 4 0 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
8022 23:31:52.682355 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8023 23:31:52.689321 1 4 8 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
8024 23:31:52.692870 1 4 12 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
8025 23:31:52.696258 1 4 16 | B1->B0 | 3333 3636 | 1 1 | (1 1) (1 1)
8026 23:31:52.702556 1 4 20 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
8027 23:31:52.705691 1 4 24 | B1->B0 | 3434 3939 | 1 0 | (1 1) (1 1)
8028 23:31:52.709057 1 4 28 | B1->B0 | 3434 3736 | 1 1 | (1 1) (0 0)
8029 23:31:52.715337 1 5 0 | B1->B0 | 3434 3737 | 1 0 | (1 1) (1 1)
8030 23:31:52.718555 1 5 4 | B1->B0 | 3434 3838 | 1 1 | (1 1) (0 0)
8031 23:31:52.721909 1 5 8 | B1->B0 | 3434 3636 | 1 1 | (1 1) (1 1)
8032 23:31:52.728496 1 5 12 | B1->B0 | 3434 3332 | 1 1 | (1 1) (0 1)
8033 23:31:52.731515 1 5 16 | B1->B0 | 2f2f 2929 | 0 0 | (0 0) (0 0)
8034 23:31:52.735611 1 5 20 | B1->B0 | 2323 2626 | 0 0 | (0 0) (1 1)
8035 23:31:52.741765 1 5 24 | B1->B0 | 2323 2b2a | 0 1 | (0 0) (1 1)
8036 23:31:52.745134 1 5 28 | B1->B0 | 2323 2c2b | 0 1 | (0 0) (0 0)
8037 23:31:52.748529 1 6 0 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
8038 23:31:52.755115 1 6 4 | B1->B0 | 2323 2726 | 0 1 | (0 0) (0 0)
8039 23:31:52.758649 1 6 8 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
8040 23:31:52.762108 1 6 12 | B1->B0 | 2424 3a39 | 0 1 | (0 0) (0 0)
8041 23:31:52.768520 1 6 16 | B1->B0 | 3838 4545 | 0 0 | (0 0) (0 0)
8042 23:31:52.771984 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8043 23:31:52.775152 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8044 23:31:52.781996 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8045 23:31:52.785835 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8046 23:31:52.788581 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8047 23:31:52.795242 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8048 23:31:52.798282 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8049 23:31:52.801859 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8050 23:31:52.809033 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8051 23:31:52.812151 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8052 23:31:52.815285 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8053 23:31:52.818483 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8054 23:31:52.824675 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8055 23:31:52.828193 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8056 23:31:52.831739 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8057 23:31:52.837878 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8058 23:31:52.841849 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8059 23:31:52.844777 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8060 23:31:52.851728 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8061 23:31:52.854644 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8062 23:31:52.858033 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8063 23:31:52.864882 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8064 23:31:52.867936 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8065 23:31:52.871373 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8066 23:31:52.874921 Total UI for P1: 0, mck2ui 16
8067 23:31:52.878414 best dqsien dly found for B0: ( 1, 9, 12)
8068 23:31:52.881805 Total UI for P1: 0, mck2ui 16
8069 23:31:52.885168 best dqsien dly found for B1: ( 1, 9, 12)
8070 23:31:52.888578 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8071 23:31:52.891595 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8072 23:31:52.892167
8073 23:31:52.897841 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8074 23:31:52.901358 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8075 23:31:52.904757 [Gating] SW calibration Done
8076 23:31:52.905397 ==
8077 23:31:52.908450 Dram Type= 6, Freq= 0, CH_0, rank 1
8078 23:31:52.911460 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8079 23:31:52.911934 ==
8080 23:31:52.912308 RX Vref Scan: 0
8081 23:31:52.912660
8082 23:31:52.914805 RX Vref 0 -> 0, step: 1
8083 23:31:52.915376
8084 23:31:52.917794 RX Delay 0 -> 252, step: 8
8085 23:31:52.920997 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8086 23:31:52.924331 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8087 23:31:52.931137 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8088 23:31:52.934414 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8089 23:31:52.938178 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8090 23:31:52.941240 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8091 23:31:52.944723 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8092 23:31:52.948093 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8093 23:31:52.954734 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8094 23:31:52.958332 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8095 23:31:52.960694 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8096 23:31:52.964098 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8097 23:31:52.971409 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8098 23:31:52.974125 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8099 23:31:52.977489 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8100 23:31:52.981213 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8101 23:31:52.981829 ==
8102 23:31:52.984543 Dram Type= 6, Freq= 0, CH_0, rank 1
8103 23:31:52.987925 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8104 23:31:52.991429 ==
8105 23:31:52.991991 DQS Delay:
8106 23:31:52.992364 DQS0 = 0, DQS1 = 0
8107 23:31:52.994195 DQM Delay:
8108 23:31:52.994658 DQM0 = 137, DQM1 = 128
8109 23:31:52.997493 DQ Delay:
8110 23:31:53.001073 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
8111 23:31:53.004220 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8112 23:31:53.007463 DQ8 =119, DQ9 =119, DQ10 =127, DQ11 =119
8113 23:31:53.010880 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8114 23:31:53.011348
8115 23:31:53.011718
8116 23:31:53.012058 ==
8117 23:31:53.014696 Dram Type= 6, Freq= 0, CH_0, rank 1
8118 23:31:53.017602 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8119 23:31:53.018189 ==
8120 23:31:53.020724
8121 23:31:53.021235
8122 23:31:53.021647 TX Vref Scan disable
8123 23:31:53.024401 == TX Byte 0 ==
8124 23:31:53.027541 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
8125 23:31:53.031148 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8126 23:31:53.034190 == TX Byte 1 ==
8127 23:31:53.037570 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8128 23:31:53.040679 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8129 23:31:53.041150 ==
8130 23:31:53.044162 Dram Type= 6, Freq= 0, CH_0, rank 1
8131 23:31:53.051200 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8132 23:31:53.051775 ==
8133 23:31:53.063323
8134 23:31:53.066783 TX Vref early break, caculate TX vref
8135 23:31:53.070284 TX Vref=16, minBit 0, minWin=22, winSum=379
8136 23:31:53.073245 TX Vref=18, minBit 1, minWin=23, winSum=400
8137 23:31:53.077106 TX Vref=20, minBit 1, minWin=24, winSum=406
8138 23:31:53.080459 TX Vref=22, minBit 1, minWin=25, winSum=414
8139 23:31:53.083677 TX Vref=24, minBit 4, minWin=24, winSum=420
8140 23:31:53.090330 TX Vref=26, minBit 1, minWin=25, winSum=428
8141 23:31:53.093274 TX Vref=28, minBit 0, minWin=25, winSum=421
8142 23:31:53.096618 TX Vref=30, minBit 0, minWin=25, winSum=416
8143 23:31:53.100014 TX Vref=32, minBit 7, minWin=24, winSum=408
8144 23:31:53.103481 TX Vref=34, minBit 1, minWin=24, winSum=400
8145 23:31:53.109801 [TxChooseVref] Worse bit 1, Min win 25, Win sum 428, Final Vref 26
8146 23:31:53.110363
8147 23:31:53.113757 Final TX Range 0 Vref 26
8148 23:31:53.114324
8149 23:31:53.114695 ==
8150 23:31:53.116735 Dram Type= 6, Freq= 0, CH_0, rank 1
8151 23:31:53.120179 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8152 23:31:53.120655 ==
8153 23:31:53.121077
8154 23:31:53.121442
8155 23:31:53.123260 TX Vref Scan disable
8156 23:31:53.130077 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8157 23:31:53.130637 == TX Byte 0 ==
8158 23:31:53.133408 u2DelayCellOfst[0]=10 cells (3 PI)
8159 23:31:53.136836 u2DelayCellOfst[1]=13 cells (4 PI)
8160 23:31:53.139731 u2DelayCellOfst[2]=6 cells (2 PI)
8161 23:31:53.143179 u2DelayCellOfst[3]=10 cells (3 PI)
8162 23:31:53.146999 u2DelayCellOfst[4]=6 cells (2 PI)
8163 23:31:53.149979 u2DelayCellOfst[5]=0 cells (0 PI)
8164 23:31:53.153132 u2DelayCellOfst[6]=13 cells (4 PI)
8165 23:31:53.153753 u2DelayCellOfst[7]=13 cells (4 PI)
8166 23:31:53.159933 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8167 23:31:53.162849 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8168 23:31:53.163531 == TX Byte 1 ==
8169 23:31:53.166602 u2DelayCellOfst[8]=0 cells (0 PI)
8170 23:31:53.169708 u2DelayCellOfst[9]=0 cells (0 PI)
8171 23:31:53.173413 u2DelayCellOfst[10]=6 cells (2 PI)
8172 23:31:53.176652 u2DelayCellOfst[11]=3 cells (1 PI)
8173 23:31:53.179778 u2DelayCellOfst[12]=10 cells (3 PI)
8174 23:31:53.183192 u2DelayCellOfst[13]=10 cells (3 PI)
8175 23:31:53.186625 u2DelayCellOfst[14]=13 cells (4 PI)
8176 23:31:53.189383 u2DelayCellOfst[15]=10 cells (3 PI)
8177 23:31:53.192712 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8178 23:31:53.199724 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8179 23:31:53.200281 DramC Write-DBI on
8180 23:31:53.200651 ==
8181 23:31:53.203221 Dram Type= 6, Freq= 0, CH_0, rank 1
8182 23:31:53.206114 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8183 23:31:53.206587 ==
8184 23:31:53.209535
8185 23:31:53.210154
8186 23:31:53.210527 TX Vref Scan disable
8187 23:31:53.212963 == TX Byte 0 ==
8188 23:31:53.215897 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
8189 23:31:53.219265 == TX Byte 1 ==
8190 23:31:53.222825 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8191 23:31:53.226072 DramC Write-DBI off
8192 23:31:53.226535
8193 23:31:53.226904 [DATLAT]
8194 23:31:53.227248 Freq=1600, CH0 RK1
8195 23:31:53.227582
8196 23:31:53.229112 DATLAT Default: 0xf
8197 23:31:53.232604 0, 0xFFFF, sum = 0
8198 23:31:53.233082 1, 0xFFFF, sum = 0
8199 23:31:53.235708 2, 0xFFFF, sum = 0
8200 23:31:53.236179 3, 0xFFFF, sum = 0
8201 23:31:53.239259 4, 0xFFFF, sum = 0
8202 23:31:53.239914 5, 0xFFFF, sum = 0
8203 23:31:53.242405 6, 0xFFFF, sum = 0
8204 23:31:53.242877 7, 0xFFFF, sum = 0
8205 23:31:53.245905 8, 0xFFFF, sum = 0
8206 23:31:53.246375 9, 0xFFFF, sum = 0
8207 23:31:53.249509 10, 0xFFFF, sum = 0
8208 23:31:53.250187 11, 0xFFFF, sum = 0
8209 23:31:53.252433 12, 0xFFFF, sum = 0
8210 23:31:53.253012 13, 0xFFFF, sum = 0
8211 23:31:53.255435 14, 0x0, sum = 1
8212 23:31:53.255908 15, 0x0, sum = 2
8213 23:31:53.258706 16, 0x0, sum = 3
8214 23:31:53.259178 17, 0x0, sum = 4
8215 23:31:53.262184 best_step = 15
8216 23:31:53.262703
8217 23:31:53.263075 ==
8218 23:31:53.265918 Dram Type= 6, Freq= 0, CH_0, rank 1
8219 23:31:53.268719 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8220 23:31:53.269193 ==
8221 23:31:53.272144 RX Vref Scan: 0
8222 23:31:53.272609
8223 23:31:53.272980 RX Vref 0 -> 0, step: 1
8224 23:31:53.273327
8225 23:31:53.275307 RX Delay 19 -> 252, step: 4
8226 23:31:53.282147 iDelay=195, Bit 0, Center 134 (83 ~ 186) 104
8227 23:31:53.285780 iDelay=195, Bit 1, Center 138 (91 ~ 186) 96
8228 23:31:53.288814 iDelay=195, Bit 2, Center 130 (79 ~ 182) 104
8229 23:31:53.292514 iDelay=195, Bit 3, Center 134 (83 ~ 186) 104
8230 23:31:53.295696 iDelay=195, Bit 4, Center 136 (87 ~ 186) 100
8231 23:31:53.302497 iDelay=195, Bit 5, Center 124 (71 ~ 178) 108
8232 23:31:53.305508 iDelay=195, Bit 6, Center 138 (87 ~ 190) 104
8233 23:31:53.308396 iDelay=195, Bit 7, Center 142 (91 ~ 194) 104
8234 23:31:53.311983 iDelay=195, Bit 8, Center 118 (67 ~ 170) 104
8235 23:31:53.315368 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8236 23:31:53.321731 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8237 23:31:53.325189 iDelay=195, Bit 11, Center 118 (67 ~ 170) 104
8238 23:31:53.328593 iDelay=195, Bit 12, Center 134 (83 ~ 186) 104
8239 23:31:53.332453 iDelay=195, Bit 13, Center 134 (83 ~ 186) 104
8240 23:31:53.334805 iDelay=195, Bit 14, Center 136 (83 ~ 190) 108
8241 23:31:53.341540 iDelay=195, Bit 15, Center 134 (83 ~ 186) 104
8242 23:31:53.342054 ==
8243 23:31:53.344769 Dram Type= 6, Freq= 0, CH_0, rank 1
8244 23:31:53.348499 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8245 23:31:53.349068 ==
8246 23:31:53.349442 DQS Delay:
8247 23:31:53.351769 DQS0 = 0, DQS1 = 0
8248 23:31:53.352339 DQM Delay:
8249 23:31:53.355031 DQM0 = 134, DQM1 = 127
8250 23:31:53.355501 DQ Delay:
8251 23:31:53.357975 DQ0 =134, DQ1 =138, DQ2 =130, DQ3 =134
8252 23:31:53.361344 DQ4 =136, DQ5 =124, DQ6 =138, DQ7 =142
8253 23:31:53.364837 DQ8 =118, DQ9 =118, DQ10 =128, DQ11 =118
8254 23:31:53.371564 DQ12 =134, DQ13 =134, DQ14 =136, DQ15 =134
8255 23:31:53.372136
8256 23:31:53.372506
8257 23:31:53.372847
8258 23:31:53.373216 [DramC_TX_OE_Calibration] TA2
8259 23:31:53.374893 Original DQ_B0 (3 6) =30, OEN = 27
8260 23:31:53.377867 Original DQ_B1 (3 6) =30, OEN = 27
8261 23:31:53.381164 24, 0x0, End_B0=24 End_B1=24
8262 23:31:53.384508 25, 0x0, End_B0=25 End_B1=25
8263 23:31:53.387694 26, 0x0, End_B0=26 End_B1=26
8264 23:31:53.390882 27, 0x0, End_B0=27 End_B1=27
8265 23:31:53.391459 28, 0x0, End_B0=28 End_B1=28
8266 23:31:53.394468 29, 0x0, End_B0=29 End_B1=29
8267 23:31:53.397534 30, 0x0, End_B0=30 End_B1=30
8268 23:31:53.401067 31, 0x4141, End_B0=30 End_B1=30
8269 23:31:53.404332 Byte0 end_step=30 best_step=27
8270 23:31:53.404796 Byte1 end_step=30 best_step=27
8271 23:31:53.407951 Byte0 TX OE(2T, 0.5T) = (3, 3)
8272 23:31:53.411277 Byte1 TX OE(2T, 0.5T) = (3, 3)
8273 23:31:53.411861
8274 23:31:53.412238
8275 23:31:53.421160 [DQSOSCAuto] RK1, (LSB)MR18= 0x1d07, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 395 ps
8276 23:31:53.421804 CH0 RK1: MR19=303, MR18=1D07
8277 23:31:53.427596 CH0_RK1: MR19=0x303, MR18=0x1D07, DQSOSC=395, MR23=63, INC=23, DEC=15
8278 23:31:53.430577 [RxdqsGatingPostProcess] freq 1600
8279 23:31:53.437252 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8280 23:31:53.440902 best DQS0 dly(2T, 0.5T) = (1, 1)
8281 23:31:53.444284 best DQS1 dly(2T, 0.5T) = (1, 1)
8282 23:31:53.447748 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8283 23:31:53.450629 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8284 23:31:53.451100 best DQS0 dly(2T, 0.5T) = (1, 1)
8285 23:31:53.453658 best DQS1 dly(2T, 0.5T) = (1, 1)
8286 23:31:53.457676 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8287 23:31:53.460633 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8288 23:31:53.464030 Pre-setting of DQS Precalculation
8289 23:31:53.470568 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8290 23:31:53.471140 ==
8291 23:31:53.474456 Dram Type= 6, Freq= 0, CH_1, rank 0
8292 23:31:53.477771 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8293 23:31:53.478337 ==
8294 23:31:53.483962 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8295 23:31:53.487216 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8296 23:31:53.490630 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8297 23:31:53.497487 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8298 23:31:53.506139 [CA 0] Center 42 (13~72) winsize 60
8299 23:31:53.509443 [CA 1] Center 42 (13~72) winsize 60
8300 23:31:53.512668 [CA 2] Center 38 (9~68) winsize 60
8301 23:31:53.516279 [CA 3] Center 38 (9~68) winsize 60
8302 23:31:53.519733 [CA 4] Center 39 (10~68) winsize 59
8303 23:31:53.522365 [CA 5] Center 37 (8~67) winsize 60
8304 23:31:53.522835
8305 23:31:53.526112 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8306 23:31:53.526579
8307 23:31:53.529261 [CATrainingPosCal] consider 1 rank data
8308 23:31:53.533041 u2DelayCellTimex100 = 285/100 ps
8309 23:31:53.536463 CA0 delay=42 (13~72),Diff = 5 PI (17 cell)
8310 23:31:53.542322 CA1 delay=42 (13~72),Diff = 5 PI (17 cell)
8311 23:31:53.545753 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8312 23:31:53.549141 CA3 delay=38 (9~68),Diff = 1 PI (3 cell)
8313 23:31:53.552636 CA4 delay=39 (10~68),Diff = 2 PI (6 cell)
8314 23:31:53.555274 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8315 23:31:53.555784
8316 23:31:53.558417 CA PerBit enable=1, Macro0, CA PI delay=37
8317 23:31:53.558896
8318 23:31:53.562198 [CBTSetCACLKResult] CA Dly = 37
8319 23:31:53.565274 CS Dly: 10 (0~41)
8320 23:31:53.568785 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8321 23:31:53.572232 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8322 23:31:53.572809 ==
8323 23:31:53.575301 Dram Type= 6, Freq= 0, CH_1, rank 1
8324 23:31:53.582214 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8325 23:31:53.582789 ==
8326 23:31:53.585531 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8327 23:31:53.592047 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8328 23:31:53.594773 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8329 23:31:53.601370 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8330 23:31:53.609415 [CA 0] Center 42 (12~72) winsize 61
8331 23:31:53.612366 [CA 1] Center 42 (12~72) winsize 61
8332 23:31:53.615957 [CA 2] Center 38 (9~68) winsize 60
8333 23:31:53.619348 [CA 3] Center 37 (8~67) winsize 60
8334 23:31:53.622394 [CA 4] Center 38 (8~69) winsize 62
8335 23:31:53.625835 [CA 5] Center 37 (7~67) winsize 61
8336 23:31:53.626331
8337 23:31:53.629055 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8338 23:31:53.629667
8339 23:31:53.632664 [CATrainingPosCal] consider 2 rank data
8340 23:31:53.636253 u2DelayCellTimex100 = 285/100 ps
8341 23:31:53.639331 CA0 delay=42 (13~72),Diff = 5 PI (17 cell)
8342 23:31:53.646265 CA1 delay=42 (13~72),Diff = 5 PI (17 cell)
8343 23:31:53.648753 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8344 23:31:53.652527 CA3 delay=38 (9~67),Diff = 1 PI (3 cell)
8345 23:31:53.655719 CA4 delay=39 (10~68),Diff = 2 PI (6 cell)
8346 23:31:53.658726 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8347 23:31:53.659192
8348 23:31:53.662461 CA PerBit enable=1, Macro0, CA PI delay=37
8349 23:31:53.663037
8350 23:31:53.665709 [CBTSetCACLKResult] CA Dly = 37
8351 23:31:53.668996 CS Dly: 11 (0~44)
8352 23:31:53.672366 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8353 23:31:53.675621 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8354 23:31:53.676191
8355 23:31:53.678662 ----->DramcWriteLeveling(PI) begin...
8356 23:31:53.679156 ==
8357 23:31:53.682265 Dram Type= 6, Freq= 0, CH_1, rank 0
8358 23:31:53.688953 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8359 23:31:53.689423 ==
8360 23:31:53.692379 Write leveling (Byte 0): 24 => 24
8361 23:31:53.692842 Write leveling (Byte 1): 28 => 28
8362 23:31:53.695775 DramcWriteLeveling(PI) end<-----
8363 23:31:53.696237
8364 23:31:53.696604 ==
8365 23:31:53.699143 Dram Type= 6, Freq= 0, CH_1, rank 0
8366 23:31:53.705683 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8367 23:31:53.706151 ==
8368 23:31:53.708725 [Gating] SW mode calibration
8369 23:31:53.715044 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8370 23:31:53.718819 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8371 23:31:53.725246 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8372 23:31:53.728567 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8373 23:31:53.732084 1 4 8 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (1 1)
8374 23:31:53.738710 1 4 12 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
8375 23:31:53.741677 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8376 23:31:53.745516 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8377 23:31:53.751566 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8378 23:31:53.755089 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8379 23:31:53.758455 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8380 23:31:53.764981 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8381 23:31:53.768310 1 5 8 | B1->B0 | 3434 3232 | 0 0 | (0 0) (0 1)
8382 23:31:53.771894 1 5 12 | B1->B0 | 2525 2323 | 0 0 | (1 0) (1 0)
8383 23:31:53.774918 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8384 23:31:53.781703 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8385 23:31:53.785094 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8386 23:31:53.788283 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8387 23:31:53.795365 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8388 23:31:53.798617 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8389 23:31:53.801645 1 6 8 | B1->B0 | 2424 3131 | 0 0 | (0 0) (0 0)
8390 23:31:53.808596 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8391 23:31:53.812054 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8392 23:31:53.815016 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8393 23:31:53.821689 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8394 23:31:53.824719 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8395 23:31:53.828190 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8396 23:31:53.835484 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8397 23:31:53.838451 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8398 23:31:53.841730 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8399 23:31:53.848508 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8400 23:31:53.851546 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8401 23:31:53.855264 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8402 23:31:53.861912 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8403 23:31:53.864936 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8404 23:31:53.868196 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8405 23:31:53.874879 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8406 23:31:53.878529 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8407 23:31:53.881873 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8408 23:31:53.885191 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8409 23:31:53.891572 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8410 23:31:53.895095 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8411 23:31:53.898560 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8412 23:31:53.905052 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8413 23:31:53.908480 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8414 23:31:53.911474 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8415 23:31:53.917993 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8416 23:31:53.921325 Total UI for P1: 0, mck2ui 16
8417 23:31:53.924980 best dqsien dly found for B0: ( 1, 9, 10)
8418 23:31:53.928002 Total UI for P1: 0, mck2ui 16
8419 23:31:53.931399 best dqsien dly found for B1: ( 1, 9, 10)
8420 23:31:53.935073 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8421 23:31:53.937705 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8422 23:31:53.938163
8423 23:31:53.941444 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8424 23:31:53.944402 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8425 23:31:53.947774 [Gating] SW calibration Done
8426 23:31:53.948225 ==
8427 23:31:53.951314 Dram Type= 6, Freq= 0, CH_1, rank 0
8428 23:31:53.954304 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8429 23:31:53.954763 ==
8430 23:31:53.957649 RX Vref Scan: 0
8431 23:31:53.958250
8432 23:31:53.961226 RX Vref 0 -> 0, step: 1
8433 23:31:53.961736
8434 23:31:53.962108 RX Delay 0 -> 252, step: 8
8435 23:31:53.968480 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8436 23:31:53.971443 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8437 23:31:53.974816 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8438 23:31:53.978143 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8439 23:31:53.981254 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8440 23:31:53.984525 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8441 23:31:53.991562 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8442 23:31:53.994446 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8443 23:31:53.998120 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
8444 23:31:54.001471 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8445 23:31:54.004941 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8446 23:31:54.011023 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8447 23:31:54.014463 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8448 23:31:54.017742 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8449 23:31:54.021396 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8450 23:31:54.027604 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8451 23:31:54.028067 ==
8452 23:31:54.031173 Dram Type= 6, Freq= 0, CH_1, rank 0
8453 23:31:54.034560 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8454 23:31:54.035020 ==
8455 23:31:54.035382 DQS Delay:
8456 23:31:54.037353 DQS0 = 0, DQS1 = 0
8457 23:31:54.037831 DQM Delay:
8458 23:31:54.040544 DQM0 = 136, DQM1 = 132
8459 23:31:54.040999 DQ Delay:
8460 23:31:54.043867 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8461 23:31:54.047606 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8462 23:31:54.050503 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =127
8463 23:31:54.053923 DQ12 =139, DQ13 =143, DQ14 =139, DQ15 =139
8464 23:31:54.054403
8465 23:31:54.054766
8466 23:31:54.057204 ==
8467 23:31:54.057711 Dram Type= 6, Freq= 0, CH_1, rank 0
8468 23:31:54.064618 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8469 23:31:54.065180 ==
8470 23:31:54.065548
8471 23:31:54.065947
8472 23:31:54.067010 TX Vref Scan disable
8473 23:31:54.067466 == TX Byte 0 ==
8474 23:31:54.070630 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8475 23:31:54.077530 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8476 23:31:54.078137 == TX Byte 1 ==
8477 23:31:54.081106 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8478 23:31:54.087826 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8479 23:31:54.088391 ==
8480 23:31:54.090479 Dram Type= 6, Freq= 0, CH_1, rank 0
8481 23:31:54.093992 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8482 23:31:54.094709 ==
8483 23:31:54.107296
8484 23:31:54.110621 TX Vref early break, caculate TX vref
8485 23:31:54.113709 TX Vref=16, minBit 0, minWin=22, winSum=377
8486 23:31:54.117168 TX Vref=18, minBit 0, minWin=23, winSum=381
8487 23:31:54.120628 TX Vref=20, minBit 1, minWin=24, winSum=399
8488 23:31:54.123954 TX Vref=22, minBit 0, minWin=25, winSum=407
8489 23:31:54.126768 TX Vref=24, minBit 0, minWin=25, winSum=416
8490 23:31:54.133837 TX Vref=26, minBit 1, minWin=25, winSum=426
8491 23:31:54.136898 TX Vref=28, minBit 0, minWin=25, winSum=424
8492 23:31:54.140520 TX Vref=30, minBit 0, minWin=24, winSum=419
8493 23:31:54.143218 TX Vref=32, minBit 0, minWin=24, winSum=412
8494 23:31:54.146789 TX Vref=34, minBit 0, minWin=24, winSum=401
8495 23:31:54.153336 [TxChooseVref] Worse bit 1, Min win 25, Win sum 426, Final Vref 26
8496 23:31:54.154062
8497 23:31:54.156494 Final TX Range 0 Vref 26
8498 23:31:54.157093
8499 23:31:54.157465 ==
8500 23:31:54.159822 Dram Type= 6, Freq= 0, CH_1, rank 0
8501 23:31:54.163551 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8502 23:31:54.164127 ==
8503 23:31:54.164500
8504 23:31:54.164903
8505 23:31:54.166357 TX Vref Scan disable
8506 23:31:54.173516 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8507 23:31:54.174133 == TX Byte 0 ==
8508 23:31:54.176344 u2DelayCellOfst[0]=17 cells (5 PI)
8509 23:31:54.180113 u2DelayCellOfst[1]=10 cells (3 PI)
8510 23:31:54.183589 u2DelayCellOfst[2]=0 cells (0 PI)
8511 23:31:54.186566 u2DelayCellOfst[3]=6 cells (2 PI)
8512 23:31:54.189761 u2DelayCellOfst[4]=10 cells (3 PI)
8513 23:31:54.193212 u2DelayCellOfst[5]=17 cells (5 PI)
8514 23:31:54.196335 u2DelayCellOfst[6]=17 cells (5 PI)
8515 23:31:54.199360 u2DelayCellOfst[7]=3 cells (1 PI)
8516 23:31:54.202676 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8517 23:31:54.205971 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8518 23:31:54.209888 == TX Byte 1 ==
8519 23:31:54.210367 u2DelayCellOfst[8]=0 cells (0 PI)
8520 23:31:54.213175 u2DelayCellOfst[9]=3 cells (1 PI)
8521 23:31:54.216283 u2DelayCellOfst[10]=13 cells (4 PI)
8522 23:31:54.219514 u2DelayCellOfst[11]=6 cells (2 PI)
8523 23:31:54.223023 u2DelayCellOfst[12]=17 cells (5 PI)
8524 23:31:54.226233 u2DelayCellOfst[13]=17 cells (5 PI)
8525 23:31:54.229565 u2DelayCellOfst[14]=17 cells (5 PI)
8526 23:31:54.233188 u2DelayCellOfst[15]=17 cells (5 PI)
8527 23:31:54.236544 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8528 23:31:54.242934 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8529 23:31:54.243510 DramC Write-DBI on
8530 23:31:54.244000 ==
8531 23:31:54.246323 Dram Type= 6, Freq= 0, CH_1, rank 0
8532 23:31:54.249823 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8533 23:31:54.252947 ==
8534 23:31:54.253572
8535 23:31:54.254091
8536 23:31:54.254551 TX Vref Scan disable
8537 23:31:54.256301 == TX Byte 0 ==
8538 23:31:54.259815 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8539 23:31:54.263662 == TX Byte 1 ==
8540 23:31:54.266544 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8541 23:31:54.267029 DramC Write-DBI off
8542 23:31:54.269762
8543 23:31:54.270257 [DATLAT]
8544 23:31:54.270742 Freq=1600, CH1 RK0
8545 23:31:54.271202
8546 23:31:54.272946 DATLAT Default: 0xf
8547 23:31:54.273471 0, 0xFFFF, sum = 0
8548 23:31:54.276728 1, 0xFFFF, sum = 0
8549 23:31:54.277297 2, 0xFFFF, sum = 0
8550 23:31:54.280306 3, 0xFFFF, sum = 0
8551 23:31:54.280873 4, 0xFFFF, sum = 0
8552 23:31:54.282989 5, 0xFFFF, sum = 0
8553 23:31:54.286640 6, 0xFFFF, sum = 0
8554 23:31:54.287116 7, 0xFFFF, sum = 0
8555 23:31:54.289682 8, 0xFFFF, sum = 0
8556 23:31:54.290250 9, 0xFFFF, sum = 0
8557 23:31:54.293503 10, 0xFFFF, sum = 0
8558 23:31:54.294153 11, 0xFFFF, sum = 0
8559 23:31:54.296404 12, 0xFFFF, sum = 0
8560 23:31:54.296969 13, 0xFFFF, sum = 0
8561 23:31:54.299473 14, 0x0, sum = 1
8562 23:31:54.299945 15, 0x0, sum = 2
8563 23:31:54.302798 16, 0x0, sum = 3
8564 23:31:54.303273 17, 0x0, sum = 4
8565 23:31:54.306316 best_step = 15
8566 23:31:54.306872
8567 23:31:54.307239 ==
8568 23:31:54.309439 Dram Type= 6, Freq= 0, CH_1, rank 0
8569 23:31:54.312859 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8570 23:31:54.313491 ==
8571 23:31:54.313911 RX Vref Scan: 1
8572 23:31:54.316448
8573 23:31:54.317006 Set Vref Range= 24 -> 127
8574 23:31:54.317378
8575 23:31:54.319354 RX Vref 24 -> 127, step: 1
8576 23:31:54.319818
8577 23:31:54.323023 RX Delay 27 -> 252, step: 4
8578 23:31:54.323580
8579 23:31:54.326191 Set Vref, RX VrefLevel [Byte0]: 24
8580 23:31:54.329518 [Byte1]: 24
8581 23:31:54.330033
8582 23:31:54.333297 Set Vref, RX VrefLevel [Byte0]: 25
8583 23:31:54.335740 [Byte1]: 25
8584 23:31:54.336207
8585 23:31:54.339287 Set Vref, RX VrefLevel [Byte0]: 26
8586 23:31:54.342625 [Byte1]: 26
8587 23:31:54.346436
8588 23:31:54.346988 Set Vref, RX VrefLevel [Byte0]: 27
8589 23:31:54.350600 [Byte1]: 27
8590 23:31:54.354332
8591 23:31:54.354890 Set Vref, RX VrefLevel [Byte0]: 28
8592 23:31:54.357808 [Byte1]: 28
8593 23:31:54.361522
8594 23:31:54.362017 Set Vref, RX VrefLevel [Byte0]: 29
8595 23:31:54.365021 [Byte1]: 29
8596 23:31:54.369120
8597 23:31:54.369732 Set Vref, RX VrefLevel [Byte0]: 30
8598 23:31:54.372588 [Byte1]: 30
8599 23:31:54.376927
8600 23:31:54.377480 Set Vref, RX VrefLevel [Byte0]: 31
8601 23:31:54.380234 [Byte1]: 31
8602 23:31:54.384090
8603 23:31:54.384686 Set Vref, RX VrefLevel [Byte0]: 32
8604 23:31:54.387545 [Byte1]: 32
8605 23:31:54.391645
8606 23:31:54.392217 Set Vref, RX VrefLevel [Byte0]: 33
8607 23:31:54.394951 [Byte1]: 33
8608 23:31:54.399212
8609 23:31:54.399674 Set Vref, RX VrefLevel [Byte0]: 34
8610 23:31:54.402554 [Byte1]: 34
8611 23:31:54.406849
8612 23:31:54.407429 Set Vref, RX VrefLevel [Byte0]: 35
8613 23:31:54.409765 [Byte1]: 35
8614 23:31:54.414152
8615 23:31:54.414646 Set Vref, RX VrefLevel [Byte0]: 36
8616 23:31:54.417798 [Byte1]: 36
8617 23:31:54.421662
8618 23:31:54.422229 Set Vref, RX VrefLevel [Byte0]: 37
8619 23:31:54.424854 [Byte1]: 37
8620 23:31:54.429235
8621 23:31:54.429774 Set Vref, RX VrefLevel [Byte0]: 38
8622 23:31:54.433029 [Byte1]: 38
8623 23:31:54.437009
8624 23:31:54.437623 Set Vref, RX VrefLevel [Byte0]: 39
8625 23:31:54.440368 [Byte1]: 39
8626 23:31:54.444318
8627 23:31:54.444886 Set Vref, RX VrefLevel [Byte0]: 40
8628 23:31:54.447721 [Byte1]: 40
8629 23:31:54.452228
8630 23:31:54.452903 Set Vref, RX VrefLevel [Byte0]: 41
8631 23:31:54.455352 [Byte1]: 41
8632 23:31:54.459644
8633 23:31:54.460126 Set Vref, RX VrefLevel [Byte0]: 42
8634 23:31:54.462487 [Byte1]: 42
8635 23:31:54.467406
8636 23:31:54.467974 Set Vref, RX VrefLevel [Byte0]: 43
8637 23:31:54.470557 [Byte1]: 43
8638 23:31:54.474338
8639 23:31:54.474801 Set Vref, RX VrefLevel [Byte0]: 44
8640 23:31:54.477906 [Byte1]: 44
8641 23:31:54.482566
8642 23:31:54.483200 Set Vref, RX VrefLevel [Byte0]: 45
8643 23:31:54.485847 [Byte1]: 45
8644 23:31:54.490313
8645 23:31:54.490884 Set Vref, RX VrefLevel [Byte0]: 46
8646 23:31:54.493410 [Byte1]: 46
8647 23:31:54.497299
8648 23:31:54.500700 Set Vref, RX VrefLevel [Byte0]: 47
8649 23:31:54.503723 [Byte1]: 47
8650 23:31:54.504288
8651 23:31:54.507052 Set Vref, RX VrefLevel [Byte0]: 48
8652 23:31:54.510174 [Byte1]: 48
8653 23:31:54.510741
8654 23:31:54.513353 Set Vref, RX VrefLevel [Byte0]: 49
8655 23:31:54.516996 [Byte1]: 49
8656 23:31:54.517620
8657 23:31:54.520170 Set Vref, RX VrefLevel [Byte0]: 50
8658 23:31:54.523707 [Byte1]: 50
8659 23:31:54.527201
8660 23:31:54.527769 Set Vref, RX VrefLevel [Byte0]: 51
8661 23:31:54.530334 [Byte1]: 51
8662 23:31:54.534806
8663 23:31:54.535445 Set Vref, RX VrefLevel [Byte0]: 52
8664 23:31:54.538016 [Byte1]: 52
8665 23:31:54.542085
8666 23:31:54.542552 Set Vref, RX VrefLevel [Byte0]: 53
8667 23:31:54.545721 [Byte1]: 53
8668 23:31:54.550032
8669 23:31:54.550594 Set Vref, RX VrefLevel [Byte0]: 54
8670 23:31:54.553668 [Byte1]: 54
8671 23:31:54.557197
8672 23:31:54.557746 Set Vref, RX VrefLevel [Byte0]: 55
8673 23:31:54.560753 [Byte1]: 55
8674 23:31:54.565199
8675 23:31:54.565747 Set Vref, RX VrefLevel [Byte0]: 56
8676 23:31:54.568577 [Byte1]: 56
8677 23:31:54.572517
8678 23:31:54.573080 Set Vref, RX VrefLevel [Byte0]: 57
8679 23:31:54.575989 [Byte1]: 57
8680 23:31:54.579908
8681 23:31:54.580475 Set Vref, RX VrefLevel [Byte0]: 58
8682 23:31:54.583575 [Byte1]: 58
8683 23:31:54.587463
8684 23:31:54.588030 Set Vref, RX VrefLevel [Byte0]: 59
8685 23:31:54.590887 [Byte1]: 59
8686 23:31:54.595556
8687 23:31:54.596145 Set Vref, RX VrefLevel [Byte0]: 60
8688 23:31:54.598154 [Byte1]: 60
8689 23:31:54.602524
8690 23:31:54.603011 Set Vref, RX VrefLevel [Byte0]: 61
8691 23:31:54.606123 [Byte1]: 61
8692 23:31:54.610058
8693 23:31:54.610687 Set Vref, RX VrefLevel [Byte0]: 62
8694 23:31:54.613567 [Byte1]: 62
8695 23:31:54.617535
8696 23:31:54.618144 Set Vref, RX VrefLevel [Byte0]: 63
8697 23:31:54.621035 [Byte1]: 63
8698 23:31:54.624844
8699 23:31:54.625321 Set Vref, RX VrefLevel [Byte0]: 64
8700 23:31:54.628630 [Byte1]: 64
8701 23:31:54.633124
8702 23:31:54.633730 Set Vref, RX VrefLevel [Byte0]: 65
8703 23:31:54.635763 [Byte1]: 65
8704 23:31:54.640709
8705 23:31:54.641169 Set Vref, RX VrefLevel [Byte0]: 66
8706 23:31:54.643263 [Byte1]: 66
8707 23:31:54.647679
8708 23:31:54.648243 Set Vref, RX VrefLevel [Byte0]: 67
8709 23:31:54.650961 [Byte1]: 67
8710 23:31:54.655403
8711 23:31:54.655865 Set Vref, RX VrefLevel [Byte0]: 68
8712 23:31:54.658325 [Byte1]: 68
8713 23:31:54.662967
8714 23:31:54.663431 Set Vref, RX VrefLevel [Byte0]: 69
8715 23:31:54.666262 [Byte1]: 69
8716 23:31:54.670235
8717 23:31:54.670698 Set Vref, RX VrefLevel [Byte0]: 70
8718 23:31:54.673644 [Byte1]: 70
8719 23:31:54.678175
8720 23:31:54.678765 Set Vref, RX VrefLevel [Byte0]: 71
8721 23:31:54.681241 [Byte1]: 71
8722 23:31:54.685383
8723 23:31:54.686004 Set Vref, RX VrefLevel [Byte0]: 72
8724 23:31:54.688880 [Byte1]: 72
8725 23:31:54.693305
8726 23:31:54.693930 Set Vref, RX VrefLevel [Byte0]: 73
8727 23:31:54.696868 [Byte1]: 73
8728 23:31:54.700722
8729 23:31:54.701285 Set Vref, RX VrefLevel [Byte0]: 74
8730 23:31:54.703807 [Byte1]: 74
8731 23:31:54.708439
8732 23:31:54.709005 Set Vref, RX VrefLevel [Byte0]: 75
8733 23:31:54.711335 [Byte1]: 75
8734 23:31:54.715695
8735 23:31:54.716257 Final RX Vref Byte 0 = 58 to rank0
8736 23:31:54.719272 Final RX Vref Byte 1 = 55 to rank0
8737 23:31:54.722514 Final RX Vref Byte 0 = 58 to rank1
8738 23:31:54.725485 Final RX Vref Byte 1 = 55 to rank1==
8739 23:31:54.728965 Dram Type= 6, Freq= 0, CH_1, rank 0
8740 23:31:54.735580 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8741 23:31:54.736153 ==
8742 23:31:54.736527 DQS Delay:
8743 23:31:54.736875 DQS0 = 0, DQS1 = 0
8744 23:31:54.738866 DQM Delay:
8745 23:31:54.739333 DQM0 = 134, DQM1 = 131
8746 23:31:54.742205 DQ Delay:
8747 23:31:54.745404 DQ0 =140, DQ1 =128, DQ2 =124, DQ3 =130
8748 23:31:54.749225 DQ4 =134, DQ5 =144, DQ6 =142, DQ7 =132
8749 23:31:54.752643 DQ8 =116, DQ9 =122, DQ10 =132, DQ11 =124
8750 23:31:54.755764 DQ12 =140, DQ13 =140, DQ14 =140, DQ15 =140
8751 23:31:54.756232
8752 23:31:54.756601
8753 23:31:54.756943
8754 23:31:54.758474 [DramC_TX_OE_Calibration] TA2
8755 23:31:54.762057 Original DQ_B0 (3 6) =30, OEN = 27
8756 23:31:54.766000 Original DQ_B1 (3 6) =30, OEN = 27
8757 23:31:54.769035 24, 0x0, End_B0=24 End_B1=24
8758 23:31:54.769655 25, 0x0, End_B0=25 End_B1=25
8759 23:31:54.772270 26, 0x0, End_B0=26 End_B1=26
8760 23:31:54.775787 27, 0x0, End_B0=27 End_B1=27
8761 23:31:54.779110 28, 0x0, End_B0=28 End_B1=28
8762 23:31:54.779585 29, 0x0, End_B0=29 End_B1=29
8763 23:31:54.781841 30, 0x0, End_B0=30 End_B1=30
8764 23:31:54.785777 31, 0x4141, End_B0=30 End_B1=30
8765 23:31:54.788919 Byte0 end_step=30 best_step=27
8766 23:31:54.792078 Byte1 end_step=30 best_step=27
8767 23:31:54.795111 Byte0 TX OE(2T, 0.5T) = (3, 3)
8768 23:31:54.795580 Byte1 TX OE(2T, 0.5T) = (3, 3)
8769 23:31:54.798320
8770 23:31:54.798781
8771 23:31:54.805255 [DQSOSCAuto] RK0, (LSB)MR18= 0x1825, (MSB)MR19= 0x303, tDQSOscB0 = 391 ps tDQSOscB1 = 397 ps
8772 23:31:54.808621 CH1 RK0: MR19=303, MR18=1825
8773 23:31:54.815289 CH1_RK0: MR19=0x303, MR18=0x1825, DQSOSC=391, MR23=63, INC=24, DEC=16
8774 23:31:54.815714
8775 23:31:54.818209 ----->DramcWriteLeveling(PI) begin...
8776 23:31:54.818633 ==
8777 23:31:54.821932 Dram Type= 6, Freq= 0, CH_1, rank 1
8778 23:31:54.824627 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8779 23:31:54.825050 ==
8780 23:31:54.828018 Write leveling (Byte 0): 27 => 27
8781 23:31:54.831718 Write leveling (Byte 1): 31 => 31
8782 23:31:54.835121 DramcWriteLeveling(PI) end<-----
8783 23:31:54.835648
8784 23:31:54.836030 ==
8785 23:31:54.838338 Dram Type= 6, Freq= 0, CH_1, rank 1
8786 23:31:54.841750 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8787 23:31:54.842396 ==
8788 23:31:54.845056 [Gating] SW mode calibration
8789 23:31:54.851735 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8790 23:31:54.858546 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8791 23:31:54.862063 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8792 23:31:54.865024 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8793 23:31:54.871586 1 4 8 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
8794 23:31:54.875154 1 4 12 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 1)
8795 23:31:54.878043 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8796 23:31:54.884820 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8797 23:31:54.888512 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8798 23:31:54.891823 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8799 23:31:54.898517 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8800 23:31:54.902100 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8801 23:31:54.905280 1 5 8 | B1->B0 | 3434 3434 | 0 1 | (0 1) (1 1)
8802 23:31:54.911561 1 5 12 | B1->B0 | 2424 3030 | 0 1 | (0 0) (1 0)
8803 23:31:54.914932 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8804 23:31:54.918123 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8805 23:31:54.925028 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8806 23:31:54.928380 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8807 23:31:54.931566 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8808 23:31:54.935389 1 6 4 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
8809 23:31:54.942010 1 6 8 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (0 0)
8810 23:31:54.944852 1 6 12 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
8811 23:31:54.948760 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8812 23:31:54.955128 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8813 23:31:54.958135 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8814 23:31:54.961257 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8815 23:31:54.968262 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8816 23:31:54.971510 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8817 23:31:54.974920 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8818 23:31:54.981737 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8819 23:31:54.984696 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8820 23:31:54.987894 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8821 23:31:54.994529 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8822 23:31:54.997895 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8823 23:31:55.001529 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8824 23:31:55.008032 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8825 23:31:55.011520 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8826 23:31:55.014320 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8827 23:31:55.021546 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8828 23:31:55.024545 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8829 23:31:55.028178 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8830 23:31:55.035247 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8831 23:31:55.037637 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8832 23:31:55.041361 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8833 23:31:55.047969 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8834 23:31:55.051145 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8835 23:31:55.054190 Total UI for P1: 0, mck2ui 16
8836 23:31:55.057667 best dqsien dly found for B1: ( 1, 9, 6)
8837 23:31:55.061305 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8838 23:31:55.067879 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8839 23:31:55.068410 Total UI for P1: 0, mck2ui 16
8840 23:31:55.074325 best dqsien dly found for B0: ( 1, 9, 14)
8841 23:31:55.078022 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8842 23:31:55.081264 best DQS1 dly(MCK, UI, PI) = (1, 9, 6)
8843 23:31:55.081843
8844 23:31:55.084878 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8845 23:31:55.087287 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 6)
8846 23:31:55.090853 [Gating] SW calibration Done
8847 23:31:55.091381 ==
8848 23:31:55.094237 Dram Type= 6, Freq= 0, CH_1, rank 1
8849 23:31:55.097649 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8850 23:31:55.098176 ==
8851 23:31:55.101118 RX Vref Scan: 0
8852 23:31:55.101535
8853 23:31:55.101920 RX Vref 0 -> 0, step: 1
8854 23:31:55.102236
8855 23:31:55.103843 RX Delay 0 -> 252, step: 8
8856 23:31:55.107330 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8857 23:31:55.114245 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8858 23:31:55.117661 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8859 23:31:55.120922 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8860 23:31:55.124420 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8861 23:31:55.127808 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8862 23:31:55.133910 iDelay=208, Bit 6, Center 143 (88 ~ 199) 112
8863 23:31:55.137289 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8864 23:31:55.140582 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8865 23:31:55.143931 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8866 23:31:55.147422 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8867 23:31:55.153916 iDelay=208, Bit 11, Center 127 (72 ~ 183) 112
8868 23:31:55.157888 iDelay=208, Bit 12, Center 143 (88 ~ 199) 112
8869 23:31:55.161090 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8870 23:31:55.163866 iDelay=208, Bit 14, Center 139 (88 ~ 191) 104
8871 23:31:55.167605 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8872 23:31:55.170762 ==
8873 23:31:55.171190 Dram Type= 6, Freq= 0, CH_1, rank 1
8874 23:31:55.177343 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8875 23:31:55.177933 ==
8876 23:31:55.178281 DQS Delay:
8877 23:31:55.180229 DQS0 = 0, DQS1 = 0
8878 23:31:55.180694 DQM Delay:
8879 23:31:55.184051 DQM0 = 136, DQM1 = 133
8880 23:31:55.184601 DQ Delay:
8881 23:31:55.187205 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =131
8882 23:31:55.190512 DQ4 =131, DQ5 =151, DQ6 =143, DQ7 =135
8883 23:31:55.193874 DQ8 =119, DQ9 =119, DQ10 =135, DQ11 =127
8884 23:31:55.197493 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8885 23:31:55.198069
8886 23:31:55.198405
8887 23:31:55.198716 ==
8888 23:31:55.200929 Dram Type= 6, Freq= 0, CH_1, rank 1
8889 23:31:55.206920 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8890 23:31:55.207453 ==
8891 23:31:55.207792
8892 23:31:55.208105
8893 23:31:55.208406 TX Vref Scan disable
8894 23:31:55.210446 == TX Byte 0 ==
8895 23:31:55.214107 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8896 23:31:55.217628 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8897 23:31:55.220895 == TX Byte 1 ==
8898 23:31:55.224191 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
8899 23:31:55.226870 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
8900 23:31:55.230498 ==
8901 23:31:55.233663 Dram Type= 6, Freq= 0, CH_1, rank 1
8902 23:31:55.237063 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8903 23:31:55.237630 ==
8904 23:31:55.249803
8905 23:31:55.252982 TX Vref early break, caculate TX vref
8906 23:31:55.256330 TX Vref=16, minBit 2, minWin=22, winSum=382
8907 23:31:55.259789 TX Vref=18, minBit 2, minWin=23, winSum=391
8908 23:31:55.262542 TX Vref=20, minBit 0, minWin=24, winSum=399
8909 23:31:55.265732 TX Vref=22, minBit 0, minWin=24, winSum=410
8910 23:31:55.269448 TX Vref=24, minBit 0, minWin=25, winSum=418
8911 23:31:55.276222 TX Vref=26, minBit 0, minWin=25, winSum=421
8912 23:31:55.279407 TX Vref=28, minBit 0, minWin=25, winSum=425
8913 23:31:55.282266 TX Vref=30, minBit 1, minWin=25, winSum=419
8914 23:31:55.285689 TX Vref=32, minBit 0, minWin=25, winSum=408
8915 23:31:55.289232 TX Vref=34, minBit 1, minWin=24, winSum=401
8916 23:31:55.295781 [TxChooseVref] Worse bit 0, Min win 25, Win sum 425, Final Vref 28
8917 23:31:55.296248
8918 23:31:55.299372 Final TX Range 0 Vref 28
8919 23:31:55.299961
8920 23:31:55.300334 ==
8921 23:31:55.302378 Dram Type= 6, Freq= 0, CH_1, rank 1
8922 23:31:55.305987 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8923 23:31:55.306562 ==
8924 23:31:55.306939
8925 23:31:55.307280
8926 23:31:55.309042 TX Vref Scan disable
8927 23:31:55.316076 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8928 23:31:55.316651 == TX Byte 0 ==
8929 23:31:55.319478 u2DelayCellOfst[0]=17 cells (5 PI)
8930 23:31:55.322476 u2DelayCellOfst[1]=10 cells (3 PI)
8931 23:31:55.325744 u2DelayCellOfst[2]=0 cells (0 PI)
8932 23:31:55.328858 u2DelayCellOfst[3]=6 cells (2 PI)
8933 23:31:55.332250 u2DelayCellOfst[4]=10 cells (3 PI)
8934 23:31:55.336079 u2DelayCellOfst[5]=17 cells (5 PI)
8935 23:31:55.339499 u2DelayCellOfst[6]=20 cells (6 PI)
8936 23:31:55.340064 u2DelayCellOfst[7]=6 cells (2 PI)
8937 23:31:55.346181 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8938 23:31:55.349065 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8939 23:31:55.349551 == TX Byte 1 ==
8940 23:31:55.352695 u2DelayCellOfst[8]=0 cells (0 PI)
8941 23:31:55.355819 u2DelayCellOfst[9]=3 cells (1 PI)
8942 23:31:55.359489 u2DelayCellOfst[10]=10 cells (3 PI)
8943 23:31:55.362842 u2DelayCellOfst[11]=3 cells (1 PI)
8944 23:31:55.365543 u2DelayCellOfst[12]=17 cells (5 PI)
8945 23:31:55.369640 u2DelayCellOfst[13]=17 cells (5 PI)
8946 23:31:55.372369 u2DelayCellOfst[14]=17 cells (5 PI)
8947 23:31:55.376080 u2DelayCellOfst[15]=20 cells (6 PI)
8948 23:31:55.379347 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8949 23:31:55.385760 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
8950 23:31:55.386324 DramC Write-DBI on
8951 23:31:55.386697 ==
8952 23:31:55.390055 Dram Type= 6, Freq= 0, CH_1, rank 1
8953 23:31:55.392331 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8954 23:31:55.392798 ==
8955 23:31:55.395787
8956 23:31:55.396250
8957 23:31:55.396615 TX Vref Scan disable
8958 23:31:55.398968 == TX Byte 0 ==
8959 23:31:55.402454 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8960 23:31:55.405515 == TX Byte 1 ==
8961 23:31:55.408890 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8962 23:31:55.409358 DramC Write-DBI off
8963 23:31:55.412135
8964 23:31:55.412705 [DATLAT]
8965 23:31:55.413074 Freq=1600, CH1 RK1
8966 23:31:55.413421
8967 23:31:55.415626 DATLAT Default: 0xf
8968 23:31:55.416194 0, 0xFFFF, sum = 0
8969 23:31:55.418657 1, 0xFFFF, sum = 0
8970 23:31:55.419130 2, 0xFFFF, sum = 0
8971 23:31:55.422337 3, 0xFFFF, sum = 0
8972 23:31:55.425653 4, 0xFFFF, sum = 0
8973 23:31:55.426309 5, 0xFFFF, sum = 0
8974 23:31:55.429291 6, 0xFFFF, sum = 0
8975 23:31:55.429904 7, 0xFFFF, sum = 0
8976 23:31:55.432061 8, 0xFFFF, sum = 0
8977 23:31:55.432530 9, 0xFFFF, sum = 0
8978 23:31:55.435567 10, 0xFFFF, sum = 0
8979 23:31:55.436145 11, 0xFFFF, sum = 0
8980 23:31:55.438658 12, 0xFFFF, sum = 0
8981 23:31:55.439131 13, 0xFFFF, sum = 0
8982 23:31:55.442161 14, 0x0, sum = 1
8983 23:31:55.442735 15, 0x0, sum = 2
8984 23:31:55.445680 16, 0x0, sum = 3
8985 23:31:55.446257 17, 0x0, sum = 4
8986 23:31:55.448741 best_step = 15
8987 23:31:55.449201
8988 23:31:55.449572 ==
8989 23:31:55.452165 Dram Type= 6, Freq= 0, CH_1, rank 1
8990 23:31:55.455396 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8991 23:31:55.456035 ==
8992 23:31:55.456422 RX Vref Scan: 0
8993 23:31:55.456775
8994 23:31:55.458989 RX Vref 0 -> 0, step: 1
8995 23:31:55.459495
8996 23:31:55.462163 RX Delay 19 -> 252, step: 4
8997 23:31:55.465562 iDelay=195, Bit 0, Center 138 (91 ~ 186) 96
8998 23:31:55.472515 iDelay=195, Bit 1, Center 130 (79 ~ 182) 104
8999 23:31:55.475444 iDelay=195, Bit 2, Center 122 (71 ~ 174) 104
9000 23:31:55.478972 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
9001 23:31:55.482314 iDelay=195, Bit 4, Center 130 (83 ~ 178) 96
9002 23:31:55.485525 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
9003 23:31:55.488660 iDelay=195, Bit 6, Center 144 (95 ~ 194) 100
9004 23:31:55.495510 iDelay=195, Bit 7, Center 132 (79 ~ 186) 108
9005 23:31:55.498807 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
9006 23:31:55.502330 iDelay=195, Bit 9, Center 120 (67 ~ 174) 108
9007 23:31:55.505186 iDelay=195, Bit 10, Center 132 (83 ~ 182) 100
9008 23:31:55.512177 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
9009 23:31:55.515267 iDelay=195, Bit 12, Center 140 (87 ~ 194) 108
9010 23:31:55.518492 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
9011 23:31:55.521869 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
9012 23:31:55.525511 iDelay=195, Bit 15, Center 140 (87 ~ 194) 108
9013 23:31:55.526171 ==
9014 23:31:55.528267 Dram Type= 6, Freq= 0, CH_1, rank 1
9015 23:31:55.534727 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9016 23:31:55.535196 ==
9017 23:31:55.535563 DQS Delay:
9018 23:31:55.538024 DQS0 = 0, DQS1 = 0
9019 23:31:55.538497 DQM Delay:
9020 23:31:55.541560 DQM0 = 134, DQM1 = 130
9021 23:31:55.542074 DQ Delay:
9022 23:31:55.544737 DQ0 =138, DQ1 =130, DQ2 =122, DQ3 =130
9023 23:31:55.548350 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =132
9024 23:31:55.551803 DQ8 =116, DQ9 =120, DQ10 =132, DQ11 =124
9025 23:31:55.554886 DQ12 =140, DQ13 =138, DQ14 =136, DQ15 =140
9026 23:31:55.555362
9027 23:31:55.555814
9028 23:31:55.556165
9029 23:31:55.558331 [DramC_TX_OE_Calibration] TA2
9030 23:31:55.561612 Original DQ_B0 (3 6) =30, OEN = 27
9031 23:31:55.564915 Original DQ_B1 (3 6) =30, OEN = 27
9032 23:31:55.568650 24, 0x0, End_B0=24 End_B1=24
9033 23:31:55.571292 25, 0x0, End_B0=25 End_B1=25
9034 23:31:55.571872 26, 0x0, End_B0=26 End_B1=26
9035 23:31:55.575230 27, 0x0, End_B0=27 End_B1=27
9036 23:31:55.578317 28, 0x0, End_B0=28 End_B1=28
9037 23:31:55.581965 29, 0x0, End_B0=29 End_B1=29
9038 23:31:55.582536 30, 0x0, End_B0=30 End_B1=30
9039 23:31:55.584652 31, 0x4545, End_B0=30 End_B1=30
9040 23:31:55.588465 Byte0 end_step=30 best_step=27
9041 23:31:55.591577 Byte1 end_step=30 best_step=27
9042 23:31:55.594783 Byte0 TX OE(2T, 0.5T) = (3, 3)
9043 23:31:55.597689 Byte1 TX OE(2T, 0.5T) = (3, 3)
9044 23:31:55.598161
9045 23:31:55.598530
9046 23:31:55.605128 [DQSOSCAuto] RK1, (LSB)MR18= 0x2308, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 392 ps
9047 23:31:55.608325 CH1 RK1: MR19=303, MR18=2308
9048 23:31:55.615122 CH1_RK1: MR19=0x303, MR18=0x2308, DQSOSC=392, MR23=63, INC=24, DEC=16
9049 23:31:55.617547 [RxdqsGatingPostProcess] freq 1600
9050 23:31:55.621005 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9051 23:31:55.624607 best DQS0 dly(2T, 0.5T) = (1, 1)
9052 23:31:55.628267 best DQS1 dly(2T, 0.5T) = (1, 1)
9053 23:31:55.630916 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9054 23:31:55.634373 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9055 23:31:55.637657 best DQS0 dly(2T, 0.5T) = (1, 1)
9056 23:31:55.641166 best DQS1 dly(2T, 0.5T) = (1, 1)
9057 23:31:55.644962 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9058 23:31:55.648194 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9059 23:31:55.651029 Pre-setting of DQS Precalculation
9060 23:31:55.654121 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9061 23:31:55.664194 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9062 23:31:55.670830 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9063 23:31:55.671414
9064 23:31:55.671910
9065 23:31:55.673772 [Calibration Summary] 3200 Mbps
9066 23:31:55.674254 CH 0, Rank 0
9067 23:31:55.677455 SW Impedance : PASS
9068 23:31:55.678157 DUTY Scan : NO K
9069 23:31:55.680738 ZQ Calibration : PASS
9070 23:31:55.684197 Jitter Meter : NO K
9071 23:31:55.684820 CBT Training : PASS
9072 23:31:55.687213 Write leveling : PASS
9073 23:31:55.690450 RX DQS gating : PASS
9074 23:31:55.690931 RX DQ/DQS(RDDQC) : PASS
9075 23:31:55.693914 TX DQ/DQS : PASS
9076 23:31:55.697095 RX DATLAT : PASS
9077 23:31:55.697715 RX DQ/DQS(Engine): PASS
9078 23:31:55.700853 TX OE : PASS
9079 23:31:55.701451 All Pass.
9080 23:31:55.701996
9081 23:31:55.703930 CH 0, Rank 1
9082 23:31:55.704505 SW Impedance : PASS
9083 23:31:55.707558 DUTY Scan : NO K
9084 23:31:55.708126 ZQ Calibration : PASS
9085 23:31:55.710534 Jitter Meter : NO K
9086 23:31:55.714107 CBT Training : PASS
9087 23:31:55.714679 Write leveling : PASS
9088 23:31:55.717538 RX DQS gating : PASS
9089 23:31:55.721022 RX DQ/DQS(RDDQC) : PASS
9090 23:31:55.721629 TX DQ/DQS : PASS
9091 23:31:55.724183 RX DATLAT : PASS
9092 23:31:55.726961 RX DQ/DQS(Engine): PASS
9093 23:31:55.727444 TX OE : PASS
9094 23:31:55.730619 All Pass.
9095 23:31:55.731237
9096 23:31:55.731662 CH 1, Rank 0
9097 23:31:55.733772 SW Impedance : PASS
9098 23:31:55.734238 DUTY Scan : NO K
9099 23:31:55.737220 ZQ Calibration : PASS
9100 23:31:55.740920 Jitter Meter : NO K
9101 23:31:55.741488 CBT Training : PASS
9102 23:31:55.744235 Write leveling : PASS
9103 23:31:55.747696 RX DQS gating : PASS
9104 23:31:55.748163 RX DQ/DQS(RDDQC) : PASS
9105 23:31:55.750292 TX DQ/DQS : PASS
9106 23:31:55.750757 RX DATLAT : PASS
9107 23:31:55.753673 RX DQ/DQS(Engine): PASS
9108 23:31:55.757325 TX OE : PASS
9109 23:31:55.757997 All Pass.
9110 23:31:55.758380
9111 23:31:55.758730 CH 1, Rank 1
9112 23:31:55.760711 SW Impedance : PASS
9113 23:31:55.763800 DUTY Scan : NO K
9114 23:31:55.764268 ZQ Calibration : PASS
9115 23:31:55.767652 Jitter Meter : NO K
9116 23:31:55.770497 CBT Training : PASS
9117 23:31:55.770961 Write leveling : PASS
9118 23:31:55.774024 RX DQS gating : PASS
9119 23:31:55.777086 RX DQ/DQS(RDDQC) : PASS
9120 23:31:55.777712 TX DQ/DQS : PASS
9121 23:31:55.780700 RX DATLAT : PASS
9122 23:31:55.784068 RX DQ/DQS(Engine): PASS
9123 23:31:55.784658 TX OE : PASS
9124 23:31:55.785041 All Pass.
9125 23:31:55.786997
9126 23:31:55.787459 DramC Write-DBI on
9127 23:31:55.790666 PER_BANK_REFRESH: Hybrid Mode
9128 23:31:55.791231 TX_TRACKING: ON
9129 23:31:55.800674 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9130 23:31:55.807311 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9131 23:31:55.816797 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9132 23:31:55.820571 [FAST_K] Save calibration result to emmc
9133 23:31:55.823769 sync common calibartion params.
9134 23:31:55.824235 sync cbt_mode0:1, 1:1
9135 23:31:55.826564 dram_init: ddr_geometry: 2
9136 23:31:55.830198 dram_init: ddr_geometry: 2
9137 23:31:55.830923 dram_init: ddr_geometry: 2
9138 23:31:55.833328 0:dram_rank_size:100000000
9139 23:31:55.837232 1:dram_rank_size:100000000
9140 23:31:55.840167 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9141 23:31:55.843599 DFS_SHUFFLE_HW_MODE: ON
9142 23:31:55.846938 dramc_set_vcore_voltage set vcore to 725000
9143 23:31:55.849813 Read voltage for 1600, 0
9144 23:31:55.850295 Vio18 = 0
9145 23:31:55.853229 Vcore = 725000
9146 23:31:55.853717 Vdram = 0
9147 23:31:55.854222 Vddq = 0
9148 23:31:55.856523 Vmddr = 0
9149 23:31:55.857113 switch to 3200 Mbps bootup
9150 23:31:55.859772 [DramcRunTimeConfig]
9151 23:31:55.860327 PHYPLL
9152 23:31:55.863177 DPM_CONTROL_AFTERK: ON
9153 23:31:55.863620 PER_BANK_REFRESH: ON
9154 23:31:55.866523 REFRESH_OVERHEAD_REDUCTION: ON
9155 23:31:55.869696 CMD_PICG_NEW_MODE: OFF
9156 23:31:55.870215 XRTWTW_NEW_MODE: ON
9157 23:31:55.872978 XRTRTR_NEW_MODE: ON
9158 23:31:55.873653 TX_TRACKING: ON
9159 23:31:55.876391 RDSEL_TRACKING: OFF
9160 23:31:55.880068 DQS Precalculation for DVFS: ON
9161 23:31:55.880619 RX_TRACKING: OFF
9162 23:31:55.883419 HW_GATING DBG: ON
9163 23:31:55.884035 ZQCS_ENABLE_LP4: ON
9164 23:31:55.886381 RX_PICG_NEW_MODE: ON
9165 23:31:55.886798 TX_PICG_NEW_MODE: ON
9166 23:31:55.889823 ENABLE_RX_DCM_DPHY: ON
9167 23:31:55.893549 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9168 23:31:55.896586 DUMMY_READ_FOR_TRACKING: OFF
9169 23:31:55.897102 !!! SPM_CONTROL_AFTERK: OFF
9170 23:31:55.899727 !!! SPM could not control APHY
9171 23:31:55.903308 IMPEDANCE_TRACKING: ON
9172 23:31:55.903724 TEMP_SENSOR: ON
9173 23:31:55.906623 HW_SAVE_FOR_SR: OFF
9174 23:31:55.910180 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9175 23:31:55.912747 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9176 23:31:55.913165 Read ODT Tracking: ON
9177 23:31:55.916385 Refresh Rate DeBounce: ON
9178 23:31:55.919881 DFS_NO_QUEUE_FLUSH: ON
9179 23:31:55.922811 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9180 23:31:55.923261 ENABLE_DFS_RUNTIME_MRW: OFF
9181 23:31:55.926215 DDR_RESERVE_NEW_MODE: ON
9182 23:31:55.929857 MR_CBT_SWITCH_FREQ: ON
9183 23:31:55.930453 =========================
9184 23:31:55.950104 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9185 23:31:55.953229 dram_init: ddr_geometry: 2
9186 23:31:55.971845 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9187 23:31:55.975264 dram_init: dram init end (result: 0)
9188 23:31:55.981479 DRAM-K: Full calibration passed in 24414 msecs
9189 23:31:55.984873 MRC: failed to locate region type 0.
9190 23:31:55.985433 DRAM rank0 size:0x100000000,
9191 23:31:55.988602 DRAM rank1 size=0x100000000
9192 23:31:55.998379 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9193 23:31:56.005132 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9194 23:31:56.011694 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9195 23:31:56.018805 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9196 23:31:56.021459 DRAM rank0 size:0x100000000,
9197 23:31:56.025118 DRAM rank1 size=0x100000000
9198 23:31:56.025730 CBMEM:
9199 23:31:56.027862 IMD: root @ 0xfffff000 254 entries.
9200 23:31:56.031402 IMD: root @ 0xffffec00 62 entries.
9201 23:31:56.034312 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9202 23:31:56.037661 WARNING: RO_VPD is uninitialized or empty.
9203 23:31:56.044559 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9204 23:31:56.051727 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9205 23:31:56.064311 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9206 23:31:56.075476 BS: romstage times (exec / console): total (unknown) / 23953 ms
9207 23:31:56.076036
9208 23:31:56.076407
9209 23:31:56.085696 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9210 23:31:56.088995 ARM64: Exception handlers installed.
9211 23:31:56.092521 ARM64: Testing exception
9212 23:31:56.095733 ARM64: Done test exception
9213 23:31:56.096285 Enumerating buses...
9214 23:31:56.099290 Show all devs... Before device enumeration.
9215 23:31:56.102546 Root Device: enabled 1
9216 23:31:56.105741 CPU_CLUSTER: 0: enabled 1
9217 23:31:56.106294 CPU: 00: enabled 1
9218 23:31:56.109015 Compare with tree...
9219 23:31:56.109568 Root Device: enabled 1
9220 23:31:56.112320 CPU_CLUSTER: 0: enabled 1
9221 23:31:56.115611 CPU: 00: enabled 1
9222 23:31:56.116170 Root Device scanning...
9223 23:31:56.118860 scan_static_bus for Root Device
9224 23:31:56.122435 CPU_CLUSTER: 0 enabled
9225 23:31:56.125837 scan_static_bus for Root Device done
9226 23:31:56.128701 scan_bus: bus Root Device finished in 8 msecs
9227 23:31:56.129163 done
9228 23:31:56.135896 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9229 23:31:56.138585 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9230 23:31:56.145760 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9231 23:31:56.149195 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9232 23:31:56.151864 Allocating resources...
9233 23:31:56.156145 Reading resources...
9234 23:31:56.158427 Root Device read_resources bus 0 link: 0
9235 23:31:56.158891 DRAM rank0 size:0x100000000,
9236 23:31:56.162556 DRAM rank1 size=0x100000000
9237 23:31:56.165499 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9238 23:31:56.168960 CPU: 00 missing read_resources
9239 23:31:56.172124 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9240 23:31:56.178860 Root Device read_resources bus 0 link: 0 done
9241 23:31:56.179429 Done reading resources.
9242 23:31:56.185324 Show resources in subtree (Root Device)...After reading.
9243 23:31:56.189268 Root Device child on link 0 CPU_CLUSTER: 0
9244 23:31:56.191947 CPU_CLUSTER: 0 child on link 0 CPU: 00
9245 23:31:56.201669 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9246 23:31:56.202248 CPU: 00
9247 23:31:56.205066 Root Device assign_resources, bus 0 link: 0
9248 23:31:56.208595 CPU_CLUSTER: 0 missing set_resources
9249 23:31:56.215135 Root Device assign_resources, bus 0 link: 0 done
9250 23:31:56.215731 Done setting resources.
9251 23:31:56.221979 Show resources in subtree (Root Device)...After assigning values.
9252 23:31:56.225372 Root Device child on link 0 CPU_CLUSTER: 0
9253 23:31:56.228275 CPU_CLUSTER: 0 child on link 0 CPU: 00
9254 23:31:56.238182 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9255 23:31:56.238733 CPU: 00
9256 23:31:56.241651 Done allocating resources.
9257 23:31:56.244689 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9258 23:31:56.248465 Enabling resources...
9259 23:31:56.248987 done.
9260 23:31:56.254982 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9261 23:31:56.255544 Initializing devices...
9262 23:31:56.258144 Root Device init
9263 23:31:56.258602 init hardware done!
9264 23:31:56.261690 0x00000018: ctrlr->caps
9265 23:31:56.264746 52.000 MHz: ctrlr->f_max
9266 23:31:56.265215 0.400 MHz: ctrlr->f_min
9267 23:31:56.268464 0x40ff8080: ctrlr->voltages
9268 23:31:56.269057 sclk: 390625
9269 23:31:56.271459 Bus Width = 1
9270 23:31:56.271939 sclk: 390625
9271 23:31:56.274647 Bus Width = 1
9272 23:31:56.275103 Early init status = 3
9273 23:31:56.281537 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9274 23:31:56.285247 in-header: 03 fc 00 00 01 00 00 00
9275 23:31:56.285868 in-data: 00
9276 23:31:56.291337 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9277 23:31:56.294802 in-header: 03 fd 00 00 00 00 00 00
9278 23:31:56.298017 in-data:
9279 23:31:56.301364 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9280 23:31:56.304664 in-header: 03 fc 00 00 01 00 00 00
9281 23:31:56.307998 in-data: 00
9282 23:31:56.311055 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9283 23:31:56.315576 in-header: 03 fd 00 00 00 00 00 00
9284 23:31:56.319076 in-data:
9285 23:31:56.322558 [SSUSB] Setting up USB HOST controller...
9286 23:31:56.326238 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9287 23:31:56.329258 [SSUSB] phy power-on done.
9288 23:31:56.332474 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9289 23:31:56.338753 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9290 23:31:56.341856 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9291 23:31:56.349326 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9292 23:31:56.355436 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9293 23:31:56.361725 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9294 23:31:56.368772 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9295 23:31:56.375310 read SPI 0x705bc 0x1f6a: 925 us, 8694 KB/s, 69.552 Mbps
9296 23:31:56.378565 SPM: binary array size = 0x9dc
9297 23:31:56.382266 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9298 23:31:56.389057 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9299 23:31:56.395271 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9300 23:31:56.402304 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9301 23:31:56.405163 configure_display: Starting display init
9302 23:31:56.438984 anx7625_power_on_init: Init interface.
9303 23:31:56.442179 anx7625_disable_pd_protocol: Disabled PD feature.
9304 23:31:56.445371 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9305 23:31:56.473155 anx7625_start_dp_work: Secure OCM version=00
9306 23:31:56.476680 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9307 23:31:56.491316 sp_tx_get_edid_block: EDID Block = 1
9308 23:31:56.594240 Extracted contents:
9309 23:31:56.597494 header: 00 ff ff ff ff ff ff 00
9310 23:31:56.600711 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9311 23:31:56.604446 version: 01 04
9312 23:31:56.607468 basic params: 95 1f 11 78 0a
9313 23:31:56.610902 chroma info: 76 90 94 55 54 90 27 21 50 54
9314 23:31:56.613827 established: 00 00 00
9315 23:31:56.620335 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9316 23:31:56.624225 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9317 23:31:56.630661 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9318 23:31:56.637687 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9319 23:31:56.644020 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9320 23:31:56.647236 extensions: 00
9321 23:31:56.647702 checksum: fb
9322 23:31:56.648073
9323 23:31:56.650719 Manufacturer: IVO Model 57d Serial Number 0
9324 23:31:56.653413 Made week 0 of 2020
9325 23:31:56.653954 EDID version: 1.4
9326 23:31:56.657212 Digital display
9327 23:31:56.660082 6 bits per primary color channel
9328 23:31:56.660553 DisplayPort interface
9329 23:31:56.663661 Maximum image size: 31 cm x 17 cm
9330 23:31:56.666887 Gamma: 220%
9331 23:31:56.667354 Check DPMS levels
9332 23:31:56.670264 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9333 23:31:56.673476 First detailed timing is preferred timing
9334 23:31:56.677016 Established timings supported:
9335 23:31:56.680449 Standard timings supported:
9336 23:31:56.684271 Detailed timings
9337 23:31:56.687497 Hex of detail: 383680a07038204018303c0035ae10000019
9338 23:31:56.690506 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9339 23:31:56.696977 0780 0798 07c8 0820 hborder 0
9340 23:31:56.700570 0438 043b 0447 0458 vborder 0
9341 23:31:56.703645 -hsync -vsync
9342 23:31:56.704208 Did detailed timing
9343 23:31:56.709931 Hex of detail: 000000000000000000000000000000000000
9344 23:31:56.710478 Manufacturer-specified data, tag 0
9345 23:31:56.717012 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9346 23:31:56.720370 ASCII string: InfoVision
9347 23:31:56.723566 Hex of detail: 000000fe00523134304e574635205248200a
9348 23:31:56.726871 ASCII string: R140NWF5 RH
9349 23:31:56.727438 Checksum
9350 23:31:56.727814 Checksum: 0xfb (valid)
9351 23:31:56.733651 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9352 23:31:56.736414 DSI data_rate: 832800000 bps
9353 23:31:56.743499 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9354 23:31:56.746937 anx7625_parse_edid: pixelclock(138800).
9355 23:31:56.749833 hactive(1920), hsync(48), hfp(24), hbp(88)
9356 23:31:56.753693 vactive(1080), vsync(12), vfp(3), vbp(17)
9357 23:31:56.756499 anx7625_dsi_config: config dsi.
9358 23:31:56.763266 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9359 23:31:56.776221 anx7625_dsi_config: success to config DSI
9360 23:31:56.779506 anx7625_dp_start: MIPI phy setup OK.
9361 23:31:56.782366 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9362 23:31:56.785733 mtk_ddp_mode_set invalid vrefresh 60
9363 23:31:56.789545 main_disp_path_setup
9364 23:31:56.790004 ovl_layer_smi_id_en
9365 23:31:56.792717 ovl_layer_smi_id_en
9366 23:31:56.793229 ccorr_config
9367 23:31:56.793567 aal_config
9368 23:31:56.796011 gamma_config
9369 23:31:56.796526 postmask_config
9370 23:31:56.799414 dither_config
9371 23:31:56.802907 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9372 23:31:56.808989 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9373 23:31:56.812263 Root Device init finished in 551 msecs
9374 23:31:56.816023 CPU_CLUSTER: 0 init
9375 23:31:56.822768 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9376 23:31:56.826254 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9377 23:31:56.829335 APU_MBOX 0x190000b0 = 0x10001
9378 23:31:56.832308 APU_MBOX 0x190001b0 = 0x10001
9379 23:31:56.835532 APU_MBOX 0x190005b0 = 0x10001
9380 23:31:56.838951 APU_MBOX 0x190006b0 = 0x10001
9381 23:31:56.841983 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9382 23:31:56.855560 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9383 23:31:56.867759 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9384 23:31:56.874450 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9385 23:31:56.885872 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9386 23:31:56.895160 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9387 23:31:56.897919 CPU_CLUSTER: 0 init finished in 81 msecs
9388 23:31:56.901627 Devices initialized
9389 23:31:56.905124 Show all devs... After init.
9390 23:31:56.905727 Root Device: enabled 1
9391 23:31:56.908364 CPU_CLUSTER: 0: enabled 1
9392 23:31:56.911306 CPU: 00: enabled 1
9393 23:31:56.914736 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9394 23:31:56.918490 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9395 23:31:56.921282 ELOG: NV offset 0x57f000 size 0x1000
9396 23:31:56.927878 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9397 23:31:56.934335 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9398 23:31:56.937761 ELOG: Event(17) added with size 13 at 2023-12-03 23:29:43 UTC
9399 23:31:56.941242 out: cmd=0x121: 03 db 21 01 00 00 00 00
9400 23:31:56.945899 in-header: 03 0a 00 00 2c 00 00 00
9401 23:31:56.958801 in-data: 55 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9402 23:31:56.965067 ELOG: Event(A1) added with size 10 at 2023-12-03 23:29:43 UTC
9403 23:31:56.971481 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9404 23:31:56.978558 ELOG: Event(A0) added with size 9 at 2023-12-03 23:29:43 UTC
9405 23:31:56.981846 elog_add_boot_reason: Logged dev mode boot
9406 23:31:56.985360 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9407 23:31:56.988663 Finalize devices...
9408 23:31:56.989127 Devices finalized
9409 23:31:56.995265 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9410 23:31:56.999068 Writing coreboot table at 0xffe64000
9411 23:31:57.001697 0. 000000000010a000-0000000000113fff: RAMSTAGE
9412 23:31:57.005071 1. 0000000040000000-00000000400fffff: RAM
9413 23:31:57.008990 2. 0000000040100000-000000004032afff: RAMSTAGE
9414 23:31:57.014952 3. 000000004032b000-00000000545fffff: RAM
9415 23:31:57.018485 4. 0000000054600000-000000005465ffff: BL31
9416 23:31:57.021392 5. 0000000054660000-00000000ffe63fff: RAM
9417 23:31:57.027938 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9418 23:31:57.031154 7. 0000000100000000-000000023fffffff: RAM
9419 23:31:57.031611 Passing 5 GPIOs to payload:
9420 23:31:57.037957 NAME | PORT | POLARITY | VALUE
9421 23:31:57.041471 EC in RW | 0x000000aa | low | undefined
9422 23:31:57.048402 EC interrupt | 0x00000005 | low | undefined
9423 23:31:57.050977 TPM interrupt | 0x000000ab | high | undefined
9424 23:31:57.054541 SD card detect | 0x00000011 | high | undefined
9425 23:31:57.061446 speaker enable | 0x00000093 | high | undefined
9426 23:31:57.064789 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9427 23:31:57.067877 in-header: 03 f9 00 00 02 00 00 00
9428 23:31:57.068335 in-data: 02 00
9429 23:31:57.071204 ADC[4]: Raw value=904357 ID=7
9430 23:31:57.074749 ADC[3]: Raw value=213441 ID=1
9431 23:31:57.075305 RAM Code: 0x71
9432 23:31:57.077655 ADC[6]: Raw value=75701 ID=0
9433 23:31:57.081629 ADC[5]: Raw value=213072 ID=1
9434 23:31:57.082194 SKU Code: 0x1
9435 23:31:57.087600 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 425c
9436 23:31:57.091057 coreboot table: 964 bytes.
9437 23:31:57.094624 IMD ROOT 0. 0xfffff000 0x00001000
9438 23:31:57.097805 IMD SMALL 1. 0xffffe000 0x00001000
9439 23:31:57.101297 RO MCACHE 2. 0xffffc000 0x00001104
9440 23:31:57.104794 CONSOLE 3. 0xfff7c000 0x00080000
9441 23:31:57.108226 FMAP 4. 0xfff7b000 0x00000452
9442 23:31:57.110845 TIME STAMP 5. 0xfff7a000 0x00000910
9443 23:31:57.114866 VBOOT WORK 6. 0xfff66000 0x00014000
9444 23:31:57.117851 RAMOOPS 7. 0xffe66000 0x00100000
9445 23:31:57.121548 COREBOOT 8. 0xffe64000 0x00002000
9446 23:31:57.122168 IMD small region:
9447 23:31:57.125018 IMD ROOT 0. 0xffffec00 0x00000400
9448 23:31:57.127585 VPD 1. 0xffffeb80 0x0000006c
9449 23:31:57.131090 MMC STATUS 2. 0xffffeb60 0x00000004
9450 23:31:57.137648 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9451 23:31:57.140929 Probing TPM: done!
9452 23:31:57.144202 Connected to device vid:did:rid of 1ae0:0028:00
9453 23:31:57.154556 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9454 23:31:57.158020 Initialized TPM device CR50 revision 0
9455 23:31:57.161334 Checking cr50 for pending updates
9456 23:31:57.165113 Reading cr50 TPM mode
9457 23:31:57.173436 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9458 23:31:57.180357 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9459 23:31:57.220173 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9460 23:31:57.223733 Checking segment from ROM address 0x40100000
9461 23:31:57.226795 Checking segment from ROM address 0x4010001c
9462 23:31:57.233692 Loading segment from ROM address 0x40100000
9463 23:31:57.234274 code (compression=0)
9464 23:31:57.240400 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9465 23:31:57.250097 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9466 23:31:57.250650 it's not compressed!
9467 23:31:57.257269 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9468 23:31:57.259980 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9469 23:31:57.280636 Loading segment from ROM address 0x4010001c
9470 23:31:57.281208 Entry Point 0x80000000
9471 23:31:57.283715 Loaded segments
9472 23:31:57.287695 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9473 23:31:57.294019 Jumping to boot code at 0x80000000(0xffe64000)
9474 23:31:57.300783 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9475 23:31:57.307031 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9476 23:31:57.314426 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9477 23:31:57.318162 Checking segment from ROM address 0x40100000
9478 23:31:57.321855 Checking segment from ROM address 0x4010001c
9479 23:31:57.327948 Loading segment from ROM address 0x40100000
9480 23:31:57.328495 code (compression=1)
9481 23:31:57.334964 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9482 23:31:57.344990 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9483 23:31:57.345614 using LZMA
9484 23:31:57.353264 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9485 23:31:57.360050 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9486 23:31:57.363461 Loading segment from ROM address 0x4010001c
9487 23:31:57.363928 Entry Point 0x54601000
9488 23:31:57.366779 Loaded segments
9489 23:31:57.369934 NOTICE: MT8192 bl31_setup
9490 23:31:57.377169 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9491 23:31:57.380235 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9492 23:31:57.383728 WARNING: region 0:
9493 23:31:57.387306 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9494 23:31:57.387872 WARNING: region 1:
9495 23:31:57.393879 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9496 23:31:57.396607 WARNING: region 2:
9497 23:31:57.399869 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9498 23:31:57.403509 WARNING: region 3:
9499 23:31:57.407117 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9500 23:31:57.410331 WARNING: region 4:
9501 23:31:57.416827 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9502 23:31:57.417375 WARNING: region 5:
9503 23:31:57.420332 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9504 23:31:57.423604 WARNING: region 6:
9505 23:31:57.427089 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9506 23:31:57.427553 WARNING: region 7:
9507 23:31:57.433688 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9508 23:31:57.440508 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9509 23:31:57.443944 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9510 23:31:57.446918 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9511 23:31:57.453367 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9512 23:31:57.456581 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9513 23:31:57.459884 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9514 23:31:57.466715 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9515 23:31:57.470252 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9516 23:31:57.477394 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9517 23:31:57.480613 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9518 23:31:57.483382 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9519 23:31:57.490209 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9520 23:31:57.493211 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9521 23:31:57.496512 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9522 23:31:57.503395 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9523 23:31:57.506612 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9524 23:31:57.513518 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9525 23:31:57.516533 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9526 23:31:57.519961 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9527 23:31:57.526698 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9528 23:31:57.530067 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9529 23:31:57.533489 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9530 23:31:57.540032 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9531 23:31:57.543346 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9532 23:31:57.550803 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9533 23:31:57.554019 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9534 23:31:57.557094 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9535 23:31:57.563493 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9536 23:31:57.567188 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9537 23:31:57.573555 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9538 23:31:57.577204 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9539 23:31:57.580593 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9540 23:31:57.586889 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9541 23:31:57.590358 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9542 23:31:57.593450 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9543 23:31:57.596702 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9544 23:31:57.603847 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9545 23:31:57.606909 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9546 23:31:57.610602 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9547 23:31:57.613470 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9548 23:31:57.617101 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9549 23:31:57.624005 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9550 23:31:57.626457 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9551 23:31:57.630318 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9552 23:31:57.637029 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9553 23:31:57.640426 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9554 23:31:57.643261 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9555 23:31:57.647173 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9556 23:31:57.653251 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9557 23:31:57.656778 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9558 23:31:57.663007 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9559 23:31:57.666871 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9560 23:31:57.670055 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9561 23:31:57.676487 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9562 23:31:57.680337 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9563 23:31:57.686550 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9564 23:31:57.690123 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9565 23:31:57.696742 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9566 23:31:57.700492 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9567 23:31:57.703620 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9568 23:31:57.710505 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9569 23:31:57.713531 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9570 23:31:57.720398 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9571 23:31:57.723452 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9572 23:31:57.730222 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9573 23:31:57.733623 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9574 23:31:57.737496 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9575 23:31:57.743633 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9576 23:31:57.747346 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9577 23:31:57.753916 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9578 23:31:57.757143 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9579 23:31:57.763614 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9580 23:31:57.767037 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9581 23:31:57.770272 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9582 23:31:57.777283 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9583 23:31:57.780569 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9584 23:31:57.787326 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9585 23:31:57.790301 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9586 23:31:57.797562 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9587 23:31:57.800384 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9588 23:31:57.804043 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9589 23:31:57.810358 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9590 23:31:57.813449 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9591 23:31:57.820447 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9592 23:31:57.824068 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9593 23:31:57.830739 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9594 23:31:57.833993 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9595 23:31:57.837366 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9596 23:31:57.844176 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9597 23:31:57.847404 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9598 23:31:57.853799 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9599 23:31:57.857077 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9600 23:31:57.864283 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9601 23:31:57.867414 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9602 23:31:57.870219 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9603 23:31:57.877156 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9604 23:31:57.880498 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9605 23:31:57.883670 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9606 23:31:57.891203 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9607 23:31:57.894228 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9608 23:31:57.897531 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9609 23:31:57.900957 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9610 23:31:57.907081 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9611 23:31:57.910428 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9612 23:31:57.917490 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9613 23:31:57.921121 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9614 23:31:57.924100 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9615 23:31:57.930918 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9616 23:31:57.933849 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9617 23:31:57.940566 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9618 23:31:57.944880 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9619 23:31:57.947235 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9620 23:31:57.954076 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9621 23:31:57.957667 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9622 23:31:57.964095 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9623 23:31:57.967502 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9624 23:31:57.970881 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9625 23:31:57.974367 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9626 23:31:57.981388 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9627 23:31:57.984720 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9628 23:31:57.987988 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9629 23:31:57.991120 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9630 23:31:57.998157 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9631 23:31:58.001117 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9632 23:31:58.004760 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9633 23:31:58.011526 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9634 23:31:58.014325 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9635 23:31:58.021653 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9636 23:31:58.025237 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9637 23:31:58.028277 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9638 23:31:58.034793 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9639 23:31:58.037677 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9640 23:31:58.041628 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9641 23:31:58.048357 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9642 23:31:58.051909 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9643 23:31:58.057668 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9644 23:31:58.061288 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9645 23:31:58.064178 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9646 23:31:58.070842 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9647 23:31:58.074378 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9648 23:31:58.081069 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9649 23:31:58.084293 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9650 23:31:58.087994 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9651 23:31:58.094868 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9652 23:31:58.097441 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9653 23:31:58.101204 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9654 23:31:58.107785 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9655 23:31:58.111263 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9656 23:31:58.117972 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9657 23:31:58.121624 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9658 23:31:58.125028 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9659 23:31:58.131647 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9660 23:31:58.135102 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9661 23:31:58.138472 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9662 23:31:58.145133 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9663 23:31:58.148224 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9664 23:31:58.154884 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9665 23:31:58.158181 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9666 23:31:58.161563 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9667 23:31:58.168229 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9668 23:31:58.171240 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9669 23:31:58.178201 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9670 23:31:58.181381 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9671 23:31:58.184776 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9672 23:31:58.191022 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9673 23:31:58.194396 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9674 23:31:58.197896 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9675 23:31:58.204425 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9676 23:31:58.208006 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9677 23:31:58.214361 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9678 23:31:58.217644 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9679 23:31:58.224460 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9680 23:31:58.227536 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9681 23:31:58.231027 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9682 23:31:58.237707 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9683 23:31:58.241686 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9684 23:31:58.244397 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9685 23:31:58.251334 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9686 23:31:58.254564 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9687 23:31:58.261014 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9688 23:31:58.264244 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9689 23:31:58.267650 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9690 23:31:58.274335 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9691 23:31:58.277787 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9692 23:31:58.284696 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9693 23:31:58.287593 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9694 23:31:58.290758 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9695 23:31:58.297994 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9696 23:31:58.301199 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9697 23:31:58.307551 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9698 23:31:58.310608 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9699 23:31:58.313947 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9700 23:31:58.321106 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9701 23:31:58.324331 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9702 23:31:58.331179 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9703 23:31:58.334084 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9704 23:31:58.337303 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9705 23:31:58.344245 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9706 23:31:58.348040 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9707 23:31:58.354230 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9708 23:31:58.357393 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9709 23:31:58.360509 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9710 23:31:58.367903 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9711 23:31:58.370686 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9712 23:31:58.377451 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9713 23:31:58.380843 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9714 23:31:58.387796 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9715 23:31:58.390898 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9716 23:31:58.393999 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9717 23:31:58.400847 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9718 23:31:58.404269 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9719 23:31:58.411062 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9720 23:31:58.414281 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9721 23:31:58.420725 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9722 23:31:58.423803 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9723 23:31:58.427387 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9724 23:31:58.434014 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9725 23:31:58.437187 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9726 23:31:58.444077 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9727 23:31:58.447453 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9728 23:31:58.450107 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9729 23:31:58.457098 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9730 23:31:58.460376 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9731 23:31:58.466731 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9732 23:31:58.470128 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9733 23:31:58.476846 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9734 23:31:58.480500 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9735 23:31:58.483471 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9736 23:31:58.490601 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9737 23:31:58.493306 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9738 23:31:58.496739 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9739 23:31:58.500138 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9740 23:31:58.506722 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9741 23:31:58.510339 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9742 23:31:58.513767 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9743 23:31:58.519901 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9744 23:31:58.523773 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9745 23:31:58.526899 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9746 23:31:58.533661 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9747 23:31:58.537121 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9748 23:31:58.540046 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9749 23:31:58.547234 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9750 23:31:58.550133 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9751 23:31:58.553501 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9752 23:31:58.560431 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9753 23:31:58.563242 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9754 23:31:58.570153 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9755 23:31:58.573645 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9756 23:31:58.576718 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9757 23:31:58.583222 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9758 23:31:58.586548 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9759 23:31:58.590117 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9760 23:31:58.596552 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9761 23:31:58.600091 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9762 23:31:58.603218 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9763 23:31:58.609784 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9764 23:31:58.613528 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9765 23:31:58.619935 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9766 23:31:58.623694 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9767 23:31:58.626937 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9768 23:31:58.633223 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9769 23:31:58.636433 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9770 23:31:58.639764 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9771 23:31:58.646940 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9772 23:31:58.649938 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9773 23:31:58.653070 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9774 23:31:58.659906 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9775 23:31:58.663031 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9776 23:31:58.666350 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9777 23:31:58.673288 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9778 23:31:58.676649 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9779 23:31:58.679716 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9780 23:31:58.683492 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9781 23:31:58.686276 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9782 23:31:58.693235 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9783 23:31:58.696499 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9784 23:31:58.699754 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9785 23:31:58.706412 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9786 23:31:58.710053 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9787 23:31:58.713043 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9788 23:31:58.716396 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9789 23:31:58.722645 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9790 23:31:58.726044 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9791 23:31:58.732722 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9792 23:31:58.736618 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9793 23:31:58.739959 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9794 23:31:58.746088 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9795 23:31:58.749897 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9796 23:31:58.756212 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9797 23:31:58.759300 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9798 23:31:58.763342 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9799 23:31:58.769817 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9800 23:31:58.772884 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9801 23:31:58.779422 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9802 23:31:58.782307 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9803 23:31:58.789211 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9804 23:31:58.792862 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9805 23:31:58.795795 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9806 23:31:58.802364 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9807 23:31:58.805802 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9808 23:31:58.812341 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9809 23:31:58.816065 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9810 23:31:58.818901 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9811 23:31:58.825486 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9812 23:31:58.829060 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9813 23:31:58.835252 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9814 23:31:58.838981 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9815 23:31:58.842195 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9816 23:31:58.848676 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9817 23:31:58.851980 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9818 23:31:58.858708 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9819 23:31:58.861805 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9820 23:31:58.868313 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9821 23:31:58.872199 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9822 23:31:58.875311 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9823 23:31:58.882491 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9824 23:31:58.885347 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9825 23:31:58.891888 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9826 23:31:58.894738 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9827 23:31:58.898416 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9828 23:31:58.905747 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9829 23:31:58.908330 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9830 23:31:58.915200 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9831 23:31:58.917969 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9832 23:31:58.921496 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9833 23:31:58.928406 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9834 23:31:58.931776 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9835 23:31:58.938322 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9836 23:31:58.941741 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9837 23:31:58.944989 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9838 23:31:58.951425 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9839 23:31:58.954640 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9840 23:31:58.961229 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9841 23:31:58.964615 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9842 23:31:58.971200 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9843 23:31:58.974278 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9844 23:31:58.977751 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9845 23:31:58.984788 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9846 23:31:58.987504 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9847 23:31:58.994374 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9848 23:31:58.997973 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9849 23:31:59.004304 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9850 23:31:59.007581 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9851 23:31:59.011176 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9852 23:31:59.017318 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9853 23:31:59.021397 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9854 23:31:59.024151 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9855 23:31:59.031243 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9856 23:31:59.034502 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9857 23:31:59.040969 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9858 23:31:59.043990 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9859 23:31:59.050929 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9860 23:31:59.054081 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9861 23:31:59.057496 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9862 23:31:59.064364 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9863 23:31:59.067491 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9864 23:31:59.074233 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9865 23:31:59.077319 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9866 23:31:59.084052 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9867 23:31:59.087599 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9868 23:31:59.090389 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9869 23:31:59.097323 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9870 23:31:59.101043 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9871 23:31:59.107114 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9872 23:31:59.110714 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9873 23:31:59.117198 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9874 23:31:59.120622 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9875 23:31:59.127349 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9876 23:31:59.130248 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9877 23:31:59.133707 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9878 23:31:59.140694 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9879 23:31:59.143735 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9880 23:31:59.150490 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9881 23:31:59.153514 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9882 23:31:59.160167 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9883 23:31:59.163416 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9884 23:31:59.169894 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9885 23:31:59.173168 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9886 23:31:59.176717 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9887 23:31:59.183431 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9888 23:31:59.187306 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9889 23:31:59.193713 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9890 23:31:59.196491 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9891 23:31:59.203597 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9892 23:31:59.206249 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9893 23:31:59.209809 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9894 23:31:59.216571 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9895 23:31:59.219842 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9896 23:31:59.226189 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9897 23:31:59.230067 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9898 23:31:59.236321 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9899 23:31:59.239757 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9900 23:31:59.247078 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9901 23:31:59.249348 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9902 23:31:59.252955 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9903 23:31:59.259765 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9904 23:31:59.262533 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9905 23:31:59.269547 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9906 23:31:59.272572 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9907 23:31:59.279157 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9908 23:31:59.283059 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9909 23:31:59.285797 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9910 23:31:59.292569 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9911 23:31:59.295689 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9912 23:31:59.302506 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9913 23:31:59.305761 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9914 23:31:59.312642 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9915 23:31:59.315678 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9916 23:31:59.318948 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9917 23:31:59.325777 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9918 23:31:59.329300 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9919 23:31:59.335663 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9920 23:31:59.339063 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9921 23:31:59.345884 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9922 23:31:59.349102 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9923 23:31:59.355451 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9924 23:31:59.359023 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9925 23:31:59.365691 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9926 23:31:59.369477 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9927 23:31:59.375656 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9928 23:31:59.378955 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9929 23:31:59.385806 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9930 23:31:59.389157 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9931 23:31:59.395820 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9932 23:31:59.399126 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9933 23:31:59.405371 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9934 23:31:59.408770 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9935 23:31:59.415418 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9936 23:31:59.418563 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9937 23:31:59.425513 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9938 23:31:59.429093 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9939 23:31:59.435069 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9940 23:31:59.439028 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9941 23:31:59.445570 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9942 23:31:59.448943 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9943 23:31:59.451931 INFO: [APUAPC] vio 0
9944 23:31:59.455310 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9945 23:31:59.462491 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9946 23:31:59.463051 INFO: [APUAPC] D0_APC_0: 0x400510
9947 23:31:59.465104 INFO: [APUAPC] D0_APC_1: 0x0
9948 23:31:59.468692 INFO: [APUAPC] D0_APC_2: 0x1540
9949 23:31:59.471731 INFO: [APUAPC] D0_APC_3: 0x0
9950 23:31:59.475138 INFO: [APUAPC] D1_APC_0: 0xffffffff
9951 23:31:59.478359 INFO: [APUAPC] D1_APC_1: 0xffffffff
9952 23:31:59.482208 INFO: [APUAPC] D1_APC_2: 0x3fffff
9953 23:31:59.485341 INFO: [APUAPC] D1_APC_3: 0x0
9954 23:31:59.488633 INFO: [APUAPC] D2_APC_0: 0xffffffff
9955 23:31:59.492146 INFO: [APUAPC] D2_APC_1: 0xffffffff
9956 23:31:59.495471 INFO: [APUAPC] D2_APC_2: 0x3fffff
9957 23:31:59.498729 INFO: [APUAPC] D2_APC_3: 0x0
9958 23:31:59.502402 INFO: [APUAPC] D3_APC_0: 0xffffffff
9959 23:31:59.505188 INFO: [APUAPC] D3_APC_1: 0xffffffff
9960 23:31:59.508813 INFO: [APUAPC] D3_APC_2: 0x3fffff
9961 23:31:59.511573 INFO: [APUAPC] D3_APC_3: 0x0
9962 23:31:59.514678 INFO: [APUAPC] D4_APC_0: 0xffffffff
9963 23:31:59.518346 INFO: [APUAPC] D4_APC_1: 0xffffffff
9964 23:31:59.521477 INFO: [APUAPC] D4_APC_2: 0x3fffff
9965 23:31:59.525064 INFO: [APUAPC] D4_APC_3: 0x0
9966 23:31:59.528762 INFO: [APUAPC] D5_APC_0: 0xffffffff
9967 23:31:59.531591 INFO: [APUAPC] D5_APC_1: 0xffffffff
9968 23:31:59.535108 INFO: [APUAPC] D5_APC_2: 0x3fffff
9969 23:31:59.538367 INFO: [APUAPC] D5_APC_3: 0x0
9970 23:31:59.541832 INFO: [APUAPC] D6_APC_0: 0xffffffff
9971 23:31:59.545363 INFO: [APUAPC] D6_APC_1: 0xffffffff
9972 23:31:59.548372 INFO: [APUAPC] D6_APC_2: 0x3fffff
9973 23:31:59.552043 INFO: [APUAPC] D6_APC_3: 0x0
9974 23:31:59.555086 INFO: [APUAPC] D7_APC_0: 0xffffffff
9975 23:31:59.558365 INFO: [APUAPC] D7_APC_1: 0xffffffff
9976 23:31:59.562079 INFO: [APUAPC] D7_APC_2: 0x3fffff
9977 23:31:59.565169 INFO: [APUAPC] D7_APC_3: 0x0
9978 23:31:59.568597 INFO: [APUAPC] D8_APC_0: 0xffffffff
9979 23:31:59.571494 INFO: [APUAPC] D8_APC_1: 0xffffffff
9980 23:31:59.575026 INFO: [APUAPC] D8_APC_2: 0x3fffff
9981 23:31:59.575492 INFO: [APUAPC] D8_APC_3: 0x0
9982 23:31:59.578266 INFO: [APUAPC] D9_APC_0: 0xffffffff
9983 23:31:59.585069 INFO: [APUAPC] D9_APC_1: 0xffffffff
9984 23:31:59.588526 INFO: [APUAPC] D9_APC_2: 0x3fffff
9985 23:31:59.588991 INFO: [APUAPC] D9_APC_3: 0x0
9986 23:31:59.591602 INFO: [APUAPC] D10_APC_0: 0xffffffff
9987 23:31:59.594785 INFO: [APUAPC] D10_APC_1: 0xffffffff
9988 23:31:59.601341 INFO: [APUAPC] D10_APC_2: 0x3fffff
9989 23:31:59.601842 INFO: [APUAPC] D10_APC_3: 0x0
9990 23:31:59.604996 INFO: [APUAPC] D11_APC_0: 0xffffffff
9991 23:31:59.611631 INFO: [APUAPC] D11_APC_1: 0xffffffff
9992 23:31:59.615034 INFO: [APUAPC] D11_APC_2: 0x3fffff
9993 23:31:59.615608 INFO: [APUAPC] D11_APC_3: 0x0
9994 23:31:59.621915 INFO: [APUAPC] D12_APC_0: 0xffffffff
9995 23:31:59.624763 INFO: [APUAPC] D12_APC_1: 0xffffffff
9996 23:31:59.628218 INFO: [APUAPC] D12_APC_2: 0x3fffff
9997 23:31:59.628780 INFO: [APUAPC] D12_APC_3: 0x0
9998 23:31:59.634492 INFO: [APUAPC] D13_APC_0: 0xffffffff
9999 23:31:59.638320 INFO: [APUAPC] D13_APC_1: 0xffffffff
10000 23:31:59.642483 INFO: [APUAPC] D13_APC_2: 0x3fffff
10001 23:31:59.642954 INFO: [APUAPC] D13_APC_3: 0x0
10002 23:31:59.647890 INFO: [APUAPC] D14_APC_0: 0xffffffff
10003 23:31:59.651217 INFO: [APUAPC] D14_APC_1: 0xffffffff
10004 23:31:59.654884 INFO: [APUAPC] D14_APC_2: 0x3fffff
10005 23:31:59.657702 INFO: [APUAPC] D14_APC_3: 0x0
10006 23:31:59.661309 INFO: [APUAPC] D15_APC_0: 0xffffffff
10007 23:31:59.664438 INFO: [APUAPC] D15_APC_1: 0xffffffff
10008 23:31:59.668203 INFO: [APUAPC] D15_APC_2: 0x3fffff
10009 23:31:59.671010 INFO: [APUAPC] D15_APC_3: 0x0
10010 23:31:59.671473 INFO: [APUAPC] APC_CON: 0x4
10011 23:31:59.674502 INFO: [NOCDAPC] D0_APC_0: 0x0
10012 23:31:59.678164 INFO: [NOCDAPC] D0_APC_1: 0x0
10013 23:31:59.681406 INFO: [NOCDAPC] D1_APC_0: 0x0
10014 23:31:59.684979 INFO: [NOCDAPC] D1_APC_1: 0xfff
10015 23:31:59.688393 INFO: [NOCDAPC] D2_APC_0: 0x0
10016 23:31:59.690882 INFO: [NOCDAPC] D2_APC_1: 0xfff
10017 23:31:59.694958 INFO: [NOCDAPC] D3_APC_0: 0x0
10018 23:31:59.697695 INFO: [NOCDAPC] D3_APC_1: 0xfff
10019 23:31:59.698163 INFO: [NOCDAPC] D4_APC_0: 0x0
10020 23:31:59.701149 INFO: [NOCDAPC] D4_APC_1: 0xfff
10021 23:31:59.704592 INFO: [NOCDAPC] D5_APC_0: 0x0
10022 23:31:59.707739 INFO: [NOCDAPC] D5_APC_1: 0xfff
10023 23:31:59.711479 INFO: [NOCDAPC] D6_APC_0: 0x0
10024 23:31:59.714225 INFO: [NOCDAPC] D6_APC_1: 0xfff
10025 23:31:59.717506 INFO: [NOCDAPC] D7_APC_0: 0x0
10026 23:31:59.721387 INFO: [NOCDAPC] D7_APC_1: 0xfff
10027 23:31:59.724449 INFO: [NOCDAPC] D8_APC_0: 0x0
10028 23:31:59.727810 INFO: [NOCDAPC] D8_APC_1: 0xfff
10029 23:31:59.728381 INFO: [NOCDAPC] D9_APC_0: 0x0
10030 23:31:59.731219 INFO: [NOCDAPC] D9_APC_1: 0xfff
10031 23:31:59.734389 INFO: [NOCDAPC] D10_APC_0: 0x0
10032 23:31:59.737444 INFO: [NOCDAPC] D10_APC_1: 0xfff
10033 23:31:59.741181 INFO: [NOCDAPC] D11_APC_0: 0x0
10034 23:31:59.744322 INFO: [NOCDAPC] D11_APC_1: 0xfff
10035 23:31:59.747837 INFO: [NOCDAPC] D12_APC_0: 0x0
10036 23:31:59.751069 INFO: [NOCDAPC] D12_APC_1: 0xfff
10037 23:31:59.754273 INFO: [NOCDAPC] D13_APC_0: 0x0
10038 23:31:59.757682 INFO: [NOCDAPC] D13_APC_1: 0xfff
10039 23:31:59.761051 INFO: [NOCDAPC] D14_APC_0: 0x0
10040 23:31:59.764409 INFO: [NOCDAPC] D14_APC_1: 0xfff
10041 23:31:59.767662 INFO: [NOCDAPC] D15_APC_0: 0x0
10042 23:31:59.771114 INFO: [NOCDAPC] D15_APC_1: 0xfff
10043 23:31:59.773924 INFO: [NOCDAPC] APC_CON: 0x4
10044 23:31:59.777735 INFO: [APUAPC] set_apusys_apc done
10045 23:31:59.778305 INFO: [DEVAPC] devapc_init done
10046 23:31:59.784352 INFO: GICv3 without legacy support detected.
10047 23:31:59.787330 INFO: ARM GICv3 driver initialized in EL3
10048 23:31:59.791118 INFO: Maximum SPI INTID supported: 639
10049 23:31:59.794573 INFO: BL31: Initializing runtime services
10050 23:31:59.800952 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10051 23:31:59.804157 INFO: SPM: enable CPC mode
10052 23:31:59.807193 INFO: mcdi ready for mcusys-off-idle and system suspend
10053 23:31:59.813977 INFO: BL31: Preparing for EL3 exit to normal world
10054 23:31:59.817175 INFO: Entry point address = 0x80000000
10055 23:31:59.817800 INFO: SPSR = 0x8
10056 23:31:59.824980
10057 23:31:59.825542
10058 23:31:59.825961
10059 23:31:59.827825 Starting depthcharge on Spherion...
10060 23:31:59.828286
10061 23:31:59.828656 Wipe memory regions:
10062 23:31:59.828999
10063 23:31:59.831926 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
10064 23:31:59.832471 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10065 23:31:59.832914 Setting prompt string to ['asurada:']
10066 23:31:59.833370 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10067 23:31:59.834146 [0x00000040000000, 0x00000054600000)
10068 23:31:59.953706
10069 23:31:59.954269 [0x00000054660000, 0x00000080000000)
10070 23:32:00.214191
10071 23:32:00.214756 [0x000000821a7280, 0x000000ffe64000)
10072 23:32:00.959043
10073 23:32:00.959622 [0x00000100000000, 0x00000240000000)
10074 23:32:02.849443
10075 23:32:02.852297 Initializing XHCI USB controller at 0x11200000.
10076 23:32:03.890915
10077 23:32:03.893738 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10078 23:32:03.894304
10079 23:32:03.894675
10080 23:32:03.895018
10081 23:32:03.895837 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10083 23:32:03.997067 asurada: tftpboot 192.168.201.1 12172439/tftp-deploy-5nfpohkk/kernel/image.itb 12172439/tftp-deploy-5nfpohkk/kernel/cmdline
10084 23:32:03.997765 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10085 23:32:03.998335 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10086 23:32:04.003394 tftpboot 192.168.201.1 12172439/tftp-deploy-5nfpohkk/kernel/image.ittp-deploy-5nfpohkk/kernel/cmdline
10087 23:32:04.003963
10088 23:32:04.004331 Waiting for link
10089 23:32:04.162883
10090 23:32:04.163042 R8152: Initializing
10091 23:32:04.163119
10092 23:32:04.166673 Version 9 (ocp_data = 6010)
10093 23:32:04.166775
10094 23:32:04.169414 R8152: Done initializing
10095 23:32:04.169505
10096 23:32:04.169625 Adding net device
10097 23:32:06.112110
10098 23:32:06.112661 done.
10099 23:32:06.113030
10100 23:32:06.113372 MAC: 00:e0:4c:78:7a:aa
10101 23:32:06.113764
10102 23:32:06.114926 Sending DHCP discover... done.
10103 23:32:06.115388
10104 23:32:18.492155 Waiting for reply... R8152: Bulk read error 0xffffffbf
10105 23:32:18.492790
10106 23:32:18.495037 Receive failed.
10107 23:32:18.495540
10108 23:32:18.495941 done.
10109 23:32:18.496305
10110 23:32:18.498325 Sending DHCP request... done.
10111 23:32:18.498819
10112 23:32:18.501725 Waiting for reply... done.
10113 23:32:18.502188
10114 23:32:18.505144 My ip is 192.168.201.12
10115 23:32:18.505626
10116 23:32:18.508823 The DHCP server ip is 192.168.201.1
10117 23:32:18.509454
10118 23:32:18.511726 TFTP server IP predefined by user: 192.168.201.1
10119 23:32:18.512294
10120 23:32:18.518139 Bootfile predefined by user: 12172439/tftp-deploy-5nfpohkk/kernel/image.itb
10121 23:32:18.518642
10122 23:32:18.521649 Sending tftp read request... done.
10123 23:32:18.522109
10124 23:32:18.529397 Waiting for the transfer...
10125 23:32:18.529896
10126 23:32:18.927862 00000000 ################################################################
10127 23:32:18.928435
10128 23:32:19.326127 00080000 ################################################################
10129 23:32:19.326275
10130 23:32:19.626980 00100000 ################################################################
10131 23:32:19.627120
10132 23:32:19.916261 00180000 ################################################################
10133 23:32:19.916426
10134 23:32:20.208491 00200000 ################################################################
10135 23:32:20.208637
10136 23:32:20.506737 00280000 ################################################################
10137 23:32:20.506876
10138 23:32:20.841345 00300000 ################################################################
10139 23:32:20.842081
10140 23:32:21.246630 00380000 ################################################################
10141 23:32:21.247136
10142 23:32:21.630329 00400000 ################################################################
10143 23:32:21.630840
10144 23:32:21.977936 00480000 ################################################################
10145 23:32:21.978450
10146 23:32:22.371111 00500000 ################################################################
10147 23:32:22.371640
10148 23:32:22.764831 00580000 ################################################################
10149 23:32:22.765346
10150 23:32:23.173410 00600000 ################################################################
10151 23:32:23.173969
10152 23:32:23.575392 00680000 ################################################################
10153 23:32:23.575937
10154 23:32:23.957114 00700000 ################################################################
10155 23:32:23.957676
10156 23:32:24.351556 00780000 ################################################################
10157 23:32:24.352071
10158 23:32:24.740983 00800000 ################################################################
10159 23:32:24.741498
10160 23:32:25.136311 00880000 ################################################################
10161 23:32:25.136848
10162 23:32:25.542371 00900000 ################################################################
10163 23:32:25.542884
10164 23:32:25.937255 00980000 ################################################################
10165 23:32:25.937839
10166 23:32:26.362437 00a00000 ################################################################
10167 23:32:26.362965
10168 23:32:26.752359 00a80000 ################################################################
10169 23:32:26.752874
10170 23:32:27.151515 00b00000 ################################################################
10171 23:32:27.152264
10172 23:32:27.477209 00b80000 ################################################################
10173 23:32:27.477357
10174 23:32:27.780613 00c00000 ################################################################
10175 23:32:27.780755
10176 23:32:28.062700 00c80000 ################################################################
10177 23:32:28.062841
10178 23:32:28.359136 00d00000 ################################################################
10179 23:32:28.359280
10180 23:32:28.620282 00d80000 ################################################################
10181 23:32:28.620423
10182 23:32:28.901401 00e00000 ################################################################
10183 23:32:28.901565
10184 23:32:29.170213 00e80000 ################################################################
10185 23:32:29.170355
10186 23:32:29.468025 00f00000 ################################################################
10187 23:32:29.468166
10188 23:32:29.768127 00f80000 ################################################################
10189 23:32:29.768266
10190 23:32:30.053858 01000000 ################################################################
10191 23:32:30.054009
10192 23:32:30.351762 01080000 ################################################################
10193 23:32:30.351907
10194 23:32:30.650748 01100000 ################################################################
10195 23:32:30.650889
10196 23:32:30.946909 01180000 ################################################################
10197 23:32:30.947051
10198 23:32:31.233663 01200000 ################################################################
10199 23:32:31.233834
10200 23:32:31.507349 01280000 ################################################################
10201 23:32:31.507529
10202 23:32:31.799264 01300000 ################################################################
10203 23:32:31.799404
10204 23:32:32.084609 01380000 ################################################################
10205 23:32:32.084749
10206 23:32:32.380772 01400000 ################################################################
10207 23:32:32.380937
10208 23:32:32.682493 01480000 ################################################################
10209 23:32:32.682672
10210 23:32:32.981744 01500000 ################################################################
10211 23:32:32.981907
10212 23:32:33.253891 01580000 ################################################################
10213 23:32:33.254031
10214 23:32:33.527768 01600000 ################################################################
10215 23:32:33.527932
10216 23:32:33.818674 01680000 ################################################################
10217 23:32:33.818834
10218 23:32:34.152454 01700000 ################################################################
10219 23:32:34.152671
10220 23:32:34.548182 01780000 ################################################################
10221 23:32:34.548774
10222 23:32:34.969283 01800000 ################################################################
10223 23:32:34.969966
10224 23:32:35.373240 01880000 ################################################################
10225 23:32:35.373993
10226 23:32:35.761739 01900000 ################################################################
10227 23:32:35.762242
10228 23:32:36.147467 01980000 ################################################################
10229 23:32:36.147608
10230 23:32:36.443175 01a00000 ################################################################
10231 23:32:36.443320
10232 23:32:36.746597 01a80000 ################################################################
10233 23:32:36.746739
10234 23:32:37.047857 01b00000 ################################################################
10235 23:32:37.048020
10236 23:32:37.347912 01b80000 ################################################################
10237 23:32:37.348081
10238 23:32:37.694144 01c00000 ############################################################# done.
10239 23:32:37.694649
10240 23:32:37.697556 The bootfile was 29859594 bytes long.
10241 23:32:37.698029
10242 23:32:37.700733 Sending tftp read request... done.
10243 23:32:37.701156
10244 23:32:37.704316 Waiting for the transfer...
10245 23:32:37.704819
10246 23:32:37.705165 00000000 # done.
10247 23:32:37.705553
10248 23:32:37.710920 Command line loaded dynamically from TFTP file: 12172439/tftp-deploy-5nfpohkk/kernel/cmdline
10249 23:32:37.714173
10250 23:32:37.734082 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12172439/extract-nfsrootfs-awh02hkz,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10251 23:32:37.734606
10252 23:32:37.734951 Loading FIT.
10253 23:32:37.735271
10254 23:32:37.737786 Image ramdisk-1 has 18760935 bytes.
10255 23:32:37.738211
10256 23:32:37.740904 Image fdt-1 has 47278 bytes.
10257 23:32:37.741328
10258 23:32:37.743823 Image kernel-1 has 11049348 bytes.
10259 23:32:37.744298
10260 23:32:37.754110 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10261 23:32:37.754534
10262 23:32:37.770643 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10263 23:32:37.771196
10264 23:32:37.777336 Choosing best match conf-1 for compat google,spherion-rev2.
10265 23:32:37.777917
10266 23:32:37.784913 Connected to device vid:did:rid of 1ae0:0028:00
10267 23:32:37.793443
10268 23:32:37.796793 tpm_get_response: command 0x17b, return code 0x0
10269 23:32:37.797314
10270 23:32:37.799725 ec_init: CrosEC protocol v3 supported (256, 248)
10271 23:32:37.803882
10272 23:32:37.807153 tpm_cleanup: add release locality here.
10273 23:32:37.807716
10274 23:32:37.808070 Shutting down all USB controllers.
10275 23:32:37.808390
10276 23:32:37.810630 Removing current net device
10277 23:32:37.811055
10278 23:32:37.817791 Exiting depthcharge with code 4 at timestamp: 67223259
10279 23:32:37.818309
10280 23:32:37.821233 LZMA decompressing kernel-1 to 0x821a6718
10281 23:32:37.821808
10282 23:32:37.823786 LZMA decompressing kernel-1 to 0x40000000
10283 23:32:39.212108
10284 23:32:39.212674 jumping to kernel
10285 23:32:39.214955 end: 2.2.4 bootloader-commands (duration 00:00:39) [common]
10286 23:32:39.215558 start: 2.2.5 auto-login-action (timeout 00:03:46) [common]
10287 23:32:39.215982 Setting prompt string to ['Linux version [0-9]']
10288 23:32:39.216363 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10289 23:32:39.216802 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10290 23:32:39.293443
10291 23:32:39.296885 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10292 23:32:39.300642 start: 2.2.5.1 login-action (timeout 00:03:46) [common]
10293 23:32:39.301231 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10294 23:32:39.301675 Setting prompt string to []
10295 23:32:39.302120 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10296 23:32:39.302529 Using line separator: #'\n'#
10297 23:32:39.302919 No login prompt set.
10298 23:32:39.303483 Parsing kernel messages
10299 23:32:39.303835 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10300 23:32:39.304429 [login-action] Waiting for messages, (timeout 00:03:46)
10301 23:32:39.320279 [ 0.000000] Linux version 6.1.64-cip10-rt5 (KernelCI@build-j33605-arm64-gcc-10-defconfig-arm64-chromebook-7778h) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sun Dec 3 22:38:18 UTC 2023
10302 23:32:39.323747 [ 0.000000] random: crng init done
10303 23:32:39.330330 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10304 23:32:39.333433 [ 0.000000] efi: UEFI not found.
10305 23:32:39.339839 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10306 23:32:39.346787 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10307 23:32:39.356893 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10308 23:32:39.366400 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10309 23:32:39.373139 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10310 23:32:39.380305 [ 0.000000] printk: bootconsole [mtk8250] enabled
10311 23:32:39.386882 [ 0.000000] NUMA: No NUMA configuration found
10312 23:32:39.393270 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10313 23:32:39.396534 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10314 23:32:39.400054 [ 0.000000] Zone ranges:
10315 23:32:39.406305 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10316 23:32:39.409749 [ 0.000000] DMA32 empty
10317 23:32:39.416655 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10318 23:32:39.419855 [ 0.000000] Movable zone start for each node
10319 23:32:39.423210 [ 0.000000] Early memory node ranges
10320 23:32:39.429943 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10321 23:32:39.436846 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10322 23:32:39.443158 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10323 23:32:39.446581 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10324 23:32:39.453207 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10325 23:32:39.460061 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10326 23:32:39.518119 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10327 23:32:39.524980 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10328 23:32:39.531295 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10329 23:32:39.534728 [ 0.000000] psci: probing for conduit method from DT.
10330 23:32:39.541187 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10331 23:32:39.544680 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10332 23:32:39.551208 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10333 23:32:39.554460 [ 0.000000] psci: SMC Calling Convention v1.2
10334 23:32:39.561326 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10335 23:32:39.564566 [ 0.000000] Detected VIPT I-cache on CPU0
10336 23:32:39.571658 [ 0.000000] CPU features: detected: GIC system register CPU interface
10337 23:32:39.577804 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10338 23:32:39.584866 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10339 23:32:39.591210 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10340 23:32:39.598072 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10341 23:32:39.604878 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10342 23:32:39.611404 [ 0.000000] alternatives: applying boot alternatives
10343 23:32:39.614605 [ 0.000000] Fallback order for Node 0: 0
10344 23:32:39.621514 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10345 23:32:39.624866 [ 0.000000] Policy zone: Normal
10346 23:32:39.647481 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12172439/extract-nfsrootfs-awh02hkz,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10347 23:32:39.661117 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10348 23:32:39.671280 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10349 23:32:39.681403 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10350 23:32:39.687629 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10351 23:32:39.691176 <6>[ 0.000000] software IO TLB: area num 8.
10352 23:32:39.747501 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10353 23:32:39.896471 <6>[ 0.000000] Memory: 7951236K/8385536K available (17984K kernel code, 4116K rwdata, 17316K rodata, 8448K init, 615K bss, 401532K reserved, 32768K cma-reserved)
10354 23:32:39.903047 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10355 23:32:39.909646 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10356 23:32:39.913173 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10357 23:32:39.919397 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10358 23:32:39.926616 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10359 23:32:39.929414 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10360 23:32:39.939748 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10361 23:32:39.945776 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10362 23:32:39.953031 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10363 23:32:39.959139 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10364 23:32:39.962552 <6>[ 0.000000] GICv3: 608 SPIs implemented
10365 23:32:39.965876 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10366 23:32:39.972518 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10367 23:32:39.975801 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10368 23:32:39.982450 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10369 23:32:39.995608 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10370 23:32:40.005460 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10371 23:32:40.015157 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10372 23:32:40.023032 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10373 23:32:40.036528 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10374 23:32:40.042592 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10375 23:32:40.049329 <6>[ 0.009234] Console: colour dummy device 80x25
10376 23:32:40.059507 <6>[ 0.013959] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10377 23:32:40.063243 <6>[ 0.024401] pid_max: default: 32768 minimum: 301
10378 23:32:40.069376 <6>[ 0.029273] LSM: Security Framework initializing
10379 23:32:40.076329 <6>[ 0.034208] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10380 23:32:40.086326 <6>[ 0.042022] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10381 23:32:40.092710 <6>[ 0.051421] cblist_init_generic: Setting adjustable number of callback queues.
10382 23:32:40.099582 <6>[ 0.058863] cblist_init_generic: Setting shift to 3 and lim to 1.
10383 23:32:40.106302 <6>[ 0.065201] cblist_init_generic: Setting adjustable number of callback queues.
10384 23:32:40.112401 <6>[ 0.072629] cblist_init_generic: Setting shift to 3 and lim to 1.
10385 23:32:40.119139 <6>[ 0.079066] rcu: Hierarchical SRCU implementation.
10386 23:32:40.125937 <6>[ 0.079068] rcu: Max phase no-delay instances is 1000.
10387 23:32:40.129306 <6>[ 0.079092] printk: bootconsole [mtk8250] printing thread started
10388 23:32:40.138528 <6>[ 0.097429] EFI services will not be available.
10389 23:32:40.140965 <6>[ 0.097627] smp: Bringing up secondary CPUs ...
10390 23:32:40.148170 <6>[ 0.097928] Detected VIPT I-cache on CPU1
10391 23:32:40.154343 <6>[ 0.097995] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10392 23:32:40.160881 <6>[ 0.098030] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10393 23:32:40.170767 <6>[ 0.125923] Detected VIPT I-cache on CPU2
10394 23:32:40.180796 <6>[ 0.125974] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10395 23:32:40.187908 <6>[ 0.125992] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10396 23:32:40.191363 <6>[ 0.126252] Detected VIPT I-cache on CPU3
10397 23:32:40.198145 <6>[ 0.126299] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10398 23:32:40.204163 <6>[ 0.126312] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10399 23:32:40.207929 <6>[ 0.126620] CPU features: detected: Spectre-v4
10400 23:32:40.213687 <6>[ 0.126626] CPU features: detected: Spectre-BHB
10401 23:32:40.217526 <6>[ 0.126630] Detected PIPT I-cache on CPU4
10402 23:32:40.224128 <6>[ 0.126689] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10403 23:32:40.230819 <6>[ 0.126705] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10404 23:32:40.237315 <6>[ 0.127002] Detected PIPT I-cache on CPU5
10405 23:32:40.244130 <6>[ 0.127062] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10406 23:32:40.250829 <6>[ 0.127079] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10407 23:32:40.254370 <6>[ 0.127352] Detected PIPT I-cache on CPU6
10408 23:32:40.260408 <6>[ 0.127417] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10409 23:32:40.267182 <6>[ 0.127432] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10410 23:32:40.273759 <6>[ 0.127722] Detected PIPT I-cache on CPU7
10411 23:32:40.280206 <6>[ 0.127786] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10412 23:32:40.286784 <6>[ 0.127803] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10413 23:32:40.290076 <6>[ 0.127849] smp: Brought up 1 node, 8 CPUs
10414 23:32:40.297022 <6>[ 0.127853] SMP: Total of 8 processors activated.
10415 23:32:40.300350 <6>[ 0.127856] CPU features: detected: 32-bit EL0 Support
10416 23:32:40.310211 <6>[ 0.127858] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10417 23:32:40.316390 <6>[ 0.127860] CPU features: detected: Common not Private translations
10418 23:32:40.323460 <6>[ 0.127862] CPU features: detected: CRC32 instructions
10419 23:32:40.326965 <6>[ 0.127864] CPU features: detected: RCpc load-acquire (LDAPR)
10420 23:32:40.333452 <6>[ 0.127866] CPU features: detected: LSE atomic instructions
10421 23:32:40.339482 <6>[ 0.127868] CPU features: detected: Privileged Access Never
10422 23:32:40.346218 <6>[ 0.127869] CPU features: detected: RAS Extension Support
10423 23:32:40.352952 <6>[ 0.127872] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10424 23:32:40.356614 <6>[ 0.127940] CPU: All CPU(s) started at EL2
10425 23:32:40.381963 x6>[ 0.127941] alternatives: applying system-wide alternatives
10426 23:32:40.388299 <6>[ 0.347770] pr<intk: console [ttyS0] printing thread started
10427 23:32:40.395281 6>[ <6>[ 0.347798] printk: console [ttyS0] enabled
10428 23:32:40.395882 0.140956] devtmpfs: initialized
10429 23:32:40.405929 <6>[ 0.347802] printk: bootconsole [mtk8250] disabled
10430 23:32:40.412312 <6>[ 0.361607] printk: bootconsole [mtk8250] printing thread stopped
10431 23:32:40.415672 <6>[ 0.362643] SuperH (H)SCI(F) driver initialized
10432 23:32:40.422005 <6>[ 0.363133] msm_serial: driver initialized
10433 23:32:40.428952 <6>[ 0.367638] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10434 23:32:40.438592 <6>[ 0.367666] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10435 23:32:40.445151 <6>[ 0.367695] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10436 23:32:40.454912 <6>[ 0.367724] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10437 23:32:40.466850 <6>[ 0.367745] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10438 23:32:40.473736 <6>[ 0.367773] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10439 23:32:40.490381 <6>[ 0.367801] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10440 23:32:40.490953 <6>[ 0.367912] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10441 23:32:40.500911 <6>[ 0.367942] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10442 23:32:40.504489 <6>[ 0.380410] loop: module loaded
10443 23:32:40.512776 <6>[ 0.383006] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10444 23:32:40.515310 <4>[ 0.399736] mtk-pmic-keys: Failed to locate of_node [id: -1]
10445 23:32:40.519212 <6>[ 0.400550] megasas: 07.719.03.00-rc1
10446 23:32:40.525668 <6>[ 0.412785] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10447 23:32:40.528982 <6>[ 0.412883] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10448 23:32:40.536002 <6>[ 0.424863] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10449 23:32:40.546073 <6>[ 0.478769] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10450 23:32:41.109651 <6>[ 1.066027] Freeing initrd memory: 18316K
10451 23:32:41.115987 <6>[ 1.073450] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10452 23:32:41.119619 <6>[ 1.078070] tun: Universal TUN/TAP device driver, 1.6
10453 23:32:41.122994 <6>[ 1.078818] thunder_xcv, ver 1.0
10454 23:32:41.126222 <6>[ 1.078838] thunder_bgx, ver 1.0
10455 23:32:41.129165 <6>[ 1.078851] nicpf, ver 1.0
10456 23:32:41.136031 <6>[ 1.079884] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10457 23:32:41.142293 <6>[ 1.079887] hns3: Copyright (c) 2017 Huawei Corporation.
10458 23:32:41.146322 <6>[ 1.079913] hclge is initializing
10459 23:32:41.152504 <6>[ 1.079929] e1000: Intel(R) PRO/1000 Network Driver
10460 23:32:41.160032 <6>[ 1.079931] e1000: Copyright (c) 1999-2006 Intel Corporation.
10461 23:32:41.163426 <6>[ 1.079947] e1000e: Intel(R) PRO/1000 Network Driver
10462 23:32:41.170273 <6>[ 1.079949] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10463 23:32:41.174223 <6>[ 1.079965] igb: Intel(R) Gigabit Ethernet Network Driver
10464 23:32:41.181339 <6>[ 1.079967] igb: Copyright (c) 2007-2014 Intel Corporation.
10465 23:32:41.187583 <6>[ 1.079980] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10466 23:32:41.194969 <6>[ 1.079982] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10467 23:32:41.197951 <6>[ 1.080272] sky2: driver version 1.30
10468 23:32:41.201730 <6>[ 1.081326] VFIO - User Level meta-driver version: 0.3
10469 23:32:41.208452 <6>[ 1.084141] usbcore: registered new interface driver usb-storage
10470 23:32:41.214845 <6>[ 1.084323] usbcore: registered new device driver onboard-usb-hub
10471 23:32:41.222089 <6>[ 1.087096] mt6397-rtc mt6359-rtc: registered as rtc0
10472 23:32:41.228533 <6>[ 1.087247] mt6397-rtc mt6359-rtc: setting system clock to 2023-12-03T23:30:27 UTC (1701646227)
10473 23:32:41.235574 <6>[ 1.087853] i2c_dev: i2c /dev entries driver
10474 23:32:41.241736 <6>[ 1.094894] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10475 23:32:41.245393 <6>[ 1.110864] cpu cpu0: EM: created perf domain
10476 23:32:41.251403 <6>[ 1.111179] cpu cpu4: EM: created perf domain
10477 23:32:41.258325 <6>[ 1.116980] sdhci: Secure Digital Host Controller Interface driver
10478 23:32:41.262359 <6>[ 1.116981] sdhci: Copyright(c) Pierre Ossman
10479 23:32:41.268681 <6>[ 1.117338] Synopsys Designware Multimedia Card Interface Driver
10480 23:32:41.275472 <6>[ 1.117723] sdhci-pltfm: SDHCI platform and OF driver helper
10481 23:32:41.282068 <6>[ 1.122958] ledtrig-cpu: registered to indicate activity on CPUs
10482 23:32:41.285674 <6>[ 1.123370] mmc0: CQHCI version 5.10
10483 23:32:41.292186 <6>[ 1.123769] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10484 23:32:41.298573 <6>[ 1.124045] usbcore: registered new interface driver usbhid
10485 23:32:41.302286 <6>[ 1.124047] usbhid: USB HID core driver
10486 23:32:41.308141 <6>[ 1.124137] spi_master spi0: will run message pump with realtime priority
10487 23:32:41.321528 <6>[ 1.152268] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10488 23:32:41.334649 <6>[ 1.155189] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10489 23:32:41.341460 <6>[ 1.156014] cros-ec-spi spi0.0: Chrome EC device registered
10490 23:32:41.348063 <6>[ 1.167486] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10491 23:32:41.354801 <6>[ 1.168430] NET: Registered PF_PACKET protocol family
10492 23:32:41.358015 <6>[ 1.168492] 9pnet: Installing 9P2000 support
10493 23:32:41.364790 <5>[ 1.168527] Key type dns_resolver registered
10494 23:32:41.368385 <6>[ 1.168915] registered taskstats version 1
10495 23:32:41.371632 <5>[ 1.168928] Loading compiled-in X.509 certificates
10496 23:32:41.385058 <4>[ 1.187375] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10497 23:32:41.395445 <4>[ 1.187615] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10498 23:32:41.401649 <3>[ 1.187634] debugfs: File 'uA_load' in directory '/' already present!
10499 23:32:41.408323 <3>[ 1.187648] debugfs: File 'min_uV' in directory '/' already present!
10500 23:32:41.414831 <3>[ 1.187654] debugfs: File 'max_uV' in directory '/' already present!
10501 23:32:41.421742 <3>[ 1.187661] debugfs: File 'constraint_flags' in directory '/' already present!
10502 23:32:41.429184 <3>[ 1.190894] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10503 23:32:41.435064 <6>[ 1.199130] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10504 23:32:41.441767 <6>[ 1.199712] xhci-mtk 11200000.usb: xHCI Host Controller
10505 23:32:41.448421 <6>[ 1.199732] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10506 23:32:41.458304 <6>[ 1.199970] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10507 23:32:41.464906 <6>[ 1.200025] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10508 23:32:41.471401 <6>[ 1.200128] xhci-mtk 11200000.usb: xHCI Host Controller
10509 23:32:41.478778 <6>[ 1.200135] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10510 23:32:41.484909 <6>[ 1.200142] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10511 23:32:41.488465 <6>[ 1.200543] hub 1-0:1.0: USB hub found
10512 23:32:41.492242 <6>[ 1.200561] hub 1-0:1.0: 1 port detected
10513 23:32:41.501409 <6>[ 1.200732] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10514 23:32:41.504940 <6>[ 1.200955] hub 2-0:1.0: USB hub found
10515 23:32:41.508300 <6>[ 1.200972] hub 2-0:1.0: 1 port detected
10516 23:32:41.514479 <6>[ 1.203925] mtk-msdc 11f70000.mmc: Got CD GPIO
10517 23:32:41.521362 <6>[ 1.218646] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10518 23:32:41.531546 <6>[ 1.218656] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10519 23:32:41.538167 <4>[ 1.218801] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10520 23:32:41.547709 <6>[ 1.219435] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10521 23:32:41.554626 <6>[ 1.219439] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10522 23:32:41.564368 <6>[ 1.219557] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10523 23:32:41.571069 <6>[ 1.219572] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10524 23:32:41.578018 <6>[ 1.219575] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10525 23:32:41.587482 <6>[ 1.219581] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10526 23:32:41.597662 <6>[ 1.221008] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10527 23:32:41.604041 <6>[ 1.221027] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10528 23:32:41.614067 <6>[ 1.221034] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10529 23:32:41.620915 <6>[ 1.221040] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10530 23:32:41.631191 <6>[ 1.221046] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10531 23:32:41.637338 <6>[ 1.221052] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10532 23:32:41.647484 <6>[ 1.221059] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10533 23:32:41.653834 <6>[ 1.221065] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10534 23:32:41.663879 <6>[ 1.221071] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10535 23:32:41.670636 <6>[ 1.221077] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10536 23:32:41.680555 <6>[ 1.221083] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10537 23:32:41.686681 <6>[ 1.221089] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10538 23:32:41.696934 <6>[ 1.221096] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10539 23:32:41.703581 <6>[ 1.221102] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10540 23:32:41.713382 <6>[ 1.221108] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10541 23:32:41.720037 <6>[ 1.221685] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10542 23:32:41.727019 <6>[ 1.222561] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10543 23:32:41.730439 <6>[ 1.222775] mmc0: Command Queue Engine enabled
10544 23:32:41.737200 <6>[ 1.222785] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10545 23:32:41.743516 <6>[ 1.223392] mmcblk0: mmc0:0001 DA4128 116 GiB
10546 23:32:41.750020 <6>[ 1.224318] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10547 23:32:41.756492 <6>[ 1.225162] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10548 23:32:41.763515 <6>[ 1.225951] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10549 23:32:41.769768 <6>[ 1.226197] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10550 23:32:41.779793 <6>[ 1.226216] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10551 23:32:41.789717 <6>[ 1.226222] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10552 23:32:41.799053 <6>[ 1.226227] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10553 23:32:41.809374 <6>[ 1.226233] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10554 23:32:41.816039 <6>[ 1.226239] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10555 23:32:41.825378 <6>[ 1.226245] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10556 23:32:41.835797 <6>[ 1.226251] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10557 23:32:41.845434 <6>[ 1.226255] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10558 23:32:41.855375 <6>[ 1.226263] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10559 23:32:41.865418 <6>[ 1.226268] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10560 23:32:41.871901 <6>[ 1.226721] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10561 23:32:41.878898 <6>[ 1.226875] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10562 23:32:41.885233 <6>[ 1.228568] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10563 23:32:41.892194 <6>[ 1.229158] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10564 23:32:41.895661 <6>[ 1.229756] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10565 23:32:41.902018 <6>[ 1.238124] Trying to probe devices needed for running init ...
10566 23:32:41.908052 <6>[ 1.581747] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10567 23:32:41.915040 <6>[ 1.608470] hub 2-1:1.0: USB hub found
10568 23:32:41.918110 <6>[ 1.608814] hub 2-1:1.0: 3 ports detected
10569 23:32:41.921442 <6>[ 1.611553] hub 2-1:1.0: USB hub found
10570 23:32:41.924958 <6>[ 1.611888] hub 2-1:1.0: 3 ports detected
10571 23:32:41.931646 <6>[ 1.729459] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10572 23:32:41.938397 <6>[ 1.882307] hub 1-1:1.0: USB hub found
10573 23:32:41.941425 <6>[ 1.882710] hub 1-1:1.0: 4 ports detected
10574 23:32:41.944511 <6>[ 1.886486] hub 1-1:1.0: USB hub found
10575 23:32:41.948468 <6>[ 1.886830] hub 1-1:1.0: 4 ports detected
10576 23:32:42.007874 <6>[ 1.961701] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10577 23:32:42.244606 <6>[ 2.197675] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10578 23:32:42.369355 <6>[ 2.325663] hub 1-1.4:1.0: USB hub found
10579 23:32:42.372617 <6>[ 2.326116] hub 1-1.4:1.0: 2 ports detected
10580 23:32:42.376249 <6>[ 2.330249] hub 1-1.4:1.0: USB hub found
10581 23:32:42.382071 <6>[ 2.330617] hub 1-1.4:1.0: 2 ports detected
10582 23:32:42.664405 <6>[ 2.617666] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10583 23:32:42.848560 <6>[ 2.801654] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10584 23:32:53.577246 <6>[ 13.538734] ALSA device list:
10585 23:32:53.583344 <6>[ 13.538756] No soundcards found.
10586 23:32:53.587035 <6>[ 13.543097] Freeing unused kernel memory: 8448K
10587 23:32:53.590096 <6>[ 13.543243] Run /init as init process
10588 23:32:53.593741 Loading, please wait...
10589 23:32:53.622110 Starting systemd-udevd version 252.6-1
10590 23:32:53.860091 <6>[ 13.815183] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10591 23:32:53.866202 <6>[ 13.815232] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10592 23:32:53.876462 <6>[ 13.815239] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10593 23:32:53.883608 <6>[ 13.823792] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10594 23:32:53.889700 <6>[ 13.827909] remoteproc remoteproc0: scp is available
10595 23:32:53.896440 <6>[ 13.828054] remoteproc remoteproc0: powering up scp
10596 23:32:53.902687 <6>[ 13.828071] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10597 23:32:53.909852 <6>[ 13.828102] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10598 23:32:53.916369 <3>[ 13.832275] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10599 23:32:53.926272 <3>[ 13.832292] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10600 23:32:53.933176 <3>[ 13.832300] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10601 23:32:53.942580 <3>[ 13.832365] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10602 23:32:53.949076 <3>[ 13.832372] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10603 23:32:53.959846 <3>[ 13.832381] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10604 23:32:53.966717 <3>[ 13.832389] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10605 23:32:53.973017 <3>[ 13.832395] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10606 23:32:53.983069 <3>[ 13.832429] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10607 23:32:53.989838 <3>[ 13.832464] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10608 23:32:53.999932 <3>[ 13.832471] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10609 23:32:54.006130 <3>[ 13.832477] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10610 23:32:54.012960 <3>[ 13.832525] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10611 23:32:54.023122 <3>[ 13.832533] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10612 23:32:54.029475 <3>[ 13.832539] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10613 23:32:54.039558 <3>[ 13.832546] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10614 23:32:54.046113 <3>[ 13.832553] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10615 23:32:54.056025 <3>[ 13.832578] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10616 23:32:54.062835 <6>[ 13.886163] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10617 23:32:54.068939 <6>[ 13.894496] usbcore: registered new interface driver r8152
10618 23:32:54.072660 <6>[ 13.900668] mc: Linux media interface: v0.10
10619 23:32:54.078716 <4>[ 13.901068] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10620 23:32:54.089318 <4>[ 13.901166] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10621 23:32:54.095480 <4>[ 13.912537] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10622 23:32:54.102236 <4>[ 13.912537] Fallback method does not support PEC.
10623 23:32:54.105398 <6>[ 13.918045] videodev: Linux video capture interface: v2.00
10624 23:32:54.115369 <3>[ 13.929337] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10625 23:32:54.122003 <6>[ 13.938505] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10626 23:32:54.128572 <6>[ 13.938574] pci_bus 0000:00: root bus resource [bus 00-ff]
10627 23:32:54.135625 <6>[ 13.938622] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10628 23:32:54.145267 <6>[ 13.938636] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10629 23:32:54.152036 <6>[ 13.938810] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10630 23:32:54.158348 <6>[ 13.938884] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10631 23:32:54.165548 <6>[ 13.939048] pci 0000:00:00.0: supports D1 D2
10632 23:32:54.172318 <6>[ 13.939054] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10633 23:32:54.178023 <6>[ 13.941100] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10634 23:32:54.185085 <6>[ 13.941347] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10635 23:32:54.191444 <6>[ 13.941425] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10636 23:32:54.198066 <6>[ 13.941457] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10637 23:32:54.208256 <6>[ 13.941477] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10638 23:32:54.211829 <6>[ 13.941614] pci 0000:01:00.0: supports D1 D2
10639 23:32:54.218262 <6>[ 13.941617] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10640 23:32:54.228235 <3>[ 13.952206] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10641 23:32:54.234517 <6>[ 13.957654] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10642 23:32:54.241002 <6>[ 13.957691] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10643 23:32:54.251042 <6>[ 13.957694] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10644 23:32:54.258195 <6>[ 13.957702] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10645 23:32:54.268216 <6>[ 13.957714] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10646 23:32:54.275091 <6>[ 13.957727] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10647 23:32:54.281028 <6>[ 13.957738] pci 0000:00:00.0: PCI bridge to [bus 01]
10648 23:32:54.287462 <6>[ 13.957743] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10649 23:32:54.294197 <6>[ 13.957958] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10650 23:32:54.301327 <6>[ 13.958612] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10651 23:32:54.304578 <6>[ 13.959009] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10652 23:32:54.314342 <6>[ 13.959325] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10653 23:32:54.320739 <6>[ 13.959330] remoteproc remoteproc0: remote processor scp is now up
10654 23:32:54.327508 <6>[ 13.959337] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10655 23:32:54.337381 <6>[ 13.974113] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10656 23:32:54.343642 <6>[ 13.975370] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10657 23:32:54.350151 <6>[ 13.981803] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10658 23:32:54.360961 <4>[ 14.005284] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10659 23:32:54.367027 <4>[ 14.005291] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10660 23:32:54.377317 <6>[ 14.006522] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10661 23:32:54.387174 <6>[ 14.006944] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10662 23:32:54.396732 <6>[ 14.009826] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10663 23:32:54.403741 <6>[ 14.030139] usbcore: registered new interface driver cdc_ether
10664 23:32:54.410376 <5>[ 14.031681] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10665 23:32:54.417257 <6>[ 14.035342] usbcore: registered new interface driver r8153_ecm
10666 23:32:54.423536 <5>[ 14.052706] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10667 23:32:54.433944 <4>[ 14.052791] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10668 23:32:54.436878 <6>[ 14.052800] cfg80211: failed to load regulatory.db
10669 23:32:54.439936 <6>[ 14.054805] Bluetooth: Core ver 2.22
10670 23:32:54.447235 <6>[ 14.054890] NET: Registered PF_BLUETOOTH protocol family
10671 23:32:54.453216 <6>[ 14.054891] Bluetooth: HCI device and connection manager initialized
10672 23:32:54.459710 <6>[ 14.054905] Bluetooth: HCI socket layer initialized
10673 23:32:54.463087 <6>[ 14.054909] Bluetooth: L2CAP socket layer initialized
10674 23:32:54.469796 <6>[ 14.054917] Bluetooth: SCO socket layer initialized
10675 23:32:54.476367 <6>[ 14.075689] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10676 23:32:54.489286 <6>[ 14.076756] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10677 23:32:54.496388 <6>[ 14.076855] usbcore: registered new interface driver uvcvideo
10678 23:32:54.499367 <6>[ 14.082230] r8152 2-1.3:1.0 eth0: v1.12.13
10679 23:32:54.505854 <6>[ 14.087780] r8152 2-1.3:1.0 enx00e04c787aaa: renamed from eth0
10680 23:32:54.512763 <6>[ 14.112643] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10681 23:32:54.515476 <6>[ 14.125935] usbcore: registered new interface driver btusb
10682 23:32:54.528875 <4>[ 14.126954] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10683 23:32:54.532720 <3>[ 14.126974] Bluetooth: hci0: Failed to load firmware file (-2)
10684 23:32:54.539232 <3>[ 14.126978] Bluetooth: hci0: Failed to set up firmware (-2)
10685 23:32:54.549471 <4>[ 14.126981] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10686 23:32:54.558998 <6>[ 14.157410] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10687 23:32:54.562562 <6>[ 14.157542] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10688 23:32:54.568627 <6>[ 14.177509] mt7921e 0000:01:00.0: ASIC revision: 79610010
10689 23:32:54.582267 <4>[ 14.272944] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10690 23:32:54.592298 <4>[ 14.379290] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10691 23:32:54.602140 <4>[ 14.487258] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10692 23:32:54.608754 Begin: Loading essential drivers ... done.
10693 23:32:54.611985 Begin: Running /scripts/init-premount ... done.
10694 23:32:54.618499 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10695 23:32:54.628506 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10696 23:32:54.638579 Device /sys/cl<4>[ 14.592345] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10697 23:32:54.641564 ass/net/enx00e04c787aaa found
10698 23:32:54.642137 done.
10699 23:32:54.676080 Begin: Waiting up to 180 secs for any network device to become available ... done.
10700 23:32:54.746802 <4>[ 14.699972] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10701 23:32:54.753790 IP-Config: enx00e04c787aaa hardware address 00:e0:4c:78:7a:aa mtu 1500 DHCP
10702 23:32:54.866739 <4>[ 14.817467] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10703 23:32:54.982706 <4>[ 14.933436] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10704 23:32:55.086642 <4>[ 15.038653] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10705 23:32:55.190719 <4>[ 15.142524] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10706 23:32:55.294249 <4>[ 15.246492] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10707 23:32:55.387548 <3>[ 15.348356] mt7921e 0000:01:00.0: hardware init failed
10708 23:32:55.776230 <6>[ 15.733986] r8152 2-1.3:1.0 enx00e04c787aaa: carrier on
10709 23:32:56.625567 IP-Config: no response after 2 secs - giving up
10710 23:32:56.679338 IP-Config: enx00e04c787aaa hardware address 00:e0:4c:78:7a:aa mtu 1500 DHCP
10711 23:32:56.682452 IP-Config: enx00e04c787aaa complete (dhcp from 192.168.201.1):
10712 23:32:56.689258 address: 192.168.201.12 broadcast: 192.168.201.255 netmask: 255.255.255.0
10713 23:32:56.698732 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10714 23:32:56.705393 host : mt8192-asurada-spherion-r0-cbg-0
10715 23:32:56.712235 domain : lava-rack
10716 23:32:56.715467 rootserver: 192.168.201.1 rootpath:
10717 23:32:56.715934 filename :
10718 23:32:56.848113 done.
10719 23:32:56.854838 Begin: Running /scripts/nfs-bottom ... done.
10720 23:32:56.875132 Begin: Running /scripts/init-bottom ... done.
10721 23:32:58.190909 <6>[ 18.149964] NET: Registered PF_INET6 protocol family
10722 23:32:58.194224 <6>[ 18.151664] Segment Routing with IPv6
10723 23:32:58.200820 <6>[ 18.151698] In-situ OAM (IOAM) with IPv6
10724 23:32:58.365949 <30>[ 18.298890] systemd[1]: systemd 252.6-1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10725 23:32:58.372556 <30>[ 18.298931] systemd[1]: Detected architecture arm64.
10726 23:32:58.376437
10727 23:32:58.379593 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10728 23:32:58.380077
10729 23:32:58.407555 <30>[ 18.367372] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10730 23:32:59.506742 <30>[ 19.465101] systemd[1]: Queued start job for default target graphical.target.
10731 23:32:59.567398 [[0;32m OK [0m] Created slic<30>[ 19.522437] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10732 23:32:59.571120 e [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10733 23:32:59.596683 [[0;32m OK [0m] Created slic<30>[ 19.551450] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10734 23:32:59.599776 e [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10735 23:32:59.625027 [[0;32m OK [<30>[ 19.580387] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10736 23:32:59.631925 0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10737 23:32:59.651714 [[0;32m OK [0m] Created slic<30>[ 19.606998] systemd[1]: Created slice user.slice - User and Session Slice.
10738 23:32:59.654893 e [0;1;39muser.slice[0m - User and Session Slice.
10739 23:32:59.682905 [[0;32m OK [0m] Started [0;<30>[ 19.634558] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10740 23:32:59.685836 1;39msystemd-ask-passwo…quests to Console Directory Watch.
10741 23:32:59.710179 [[0;32m OK [0m] Started [0;1;39msystemd-ask<30>[ 19.661904] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10742 23:32:59.713743 -passwo… Requests to Wall Directory Watch.
10743 23:32:59.747803 [[0;32m OK [0m] Reached target [0;1;39mcryp<30>[ 19.689865] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10744 23:32:59.754469 <30>[ 19.690100] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10745 23:32:59.757914 tsetup.…get[0m - Local Encrypted Volumes.
10746 23:32:59.782092 [[0;32m OK [0m] Reached target [0;1;39minte<30>[ 19.734032] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10747 23:32:59.785653 grityse…Local Integrity Protected Volumes.
10748 23:32:59.807483 [[0;32m OK [0m] Reached target [0;1;39mpath<30>[ 19.762213] systemd[1]: Reached target paths.target - Path Units.
10749 23:32:59.808079 s.target[0m - Path Units.
10750 23:32:59.831371 [[0;32m OK [0m] Reached target [0;1;39mremo<30>[ 19.786133] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10751 23:32:59.834321 te-fs.target[0m - Remote File Systems.
10752 23:32:59.854468 [[0;32m OK [0m] Reached target [0;1;39mslic<30>[ 19.809658] systemd[1]: Reached target slices.target - Slice Units.
10753 23:32:59.857632 es.target[0m - Slice Units.
10754 23:32:59.879307 [[0;32m OK [0m] Reached target [0;1;39mswap<30>[ 19.834166] systemd[1]: Reached target swap.target - Swaps.
10755 23:32:59.879949 .target[0m - Swaps.
10756 23:32:59.902446 [[0;32m OK [0m] Reached target [0;1;39mveri<30>[ 19.857821] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10757 23:32:59.909159 tysetup… - Local Verity Protected Volumes.
10758 23:32:59.931727 [[0;32m OK [0m] Listening on<30>[ 19.886615] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10759 23:32:59.938579 [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10760 23:32:59.962222 [[0;32m OK [<30>[ 19.917075] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10761 23:32:59.968887 0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10762 23:32:59.988630 [[0;32m OK [0m] Listening on<30>[ 19.943273] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10763 23:32:59.994635 [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10764 23:33:00.016136 [[0;32m OK [0m] Listening on<30>[ 19.971172] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10765 23:33:00.019299 [0;1;39msystemd-journald.socket[0m - Journal Socket.
10766 23:33:00.043972 [[0;32m OK [0m] Listening on<30>[ 19.999451] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10767 23:33:00.050646 [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10768 23:33:00.074397 [[0;32m OK [0m] Listening on [0;1;39msystem<30>[ 20.029797] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10769 23:33:00.081348 d-udevd….socket[0m - udev Control Socket.
10770 23:33:00.102629 [[0;32m OK [0m] Listening on [0;1;39msystem<30>[ 20.058156] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10771 23:33:00.106137 d-udevd…l.socket[0m - udev Kernel Socket.
10772 23:33:00.163278 Mounting [0;1;39mdev-hugepages.mount[<30>[ 20.118170] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10773 23:33:00.166284 0m - Huge Pages File System...
10774 23:33:00.185666 Mountin<30>[ 20.144324] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10775 23:33:00.192276 g [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10776 23:33:00.214430 <30>[ 20.173313] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10777 23:33:00.221250 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10778 23:33:00.249381 <30>[ 20.198302] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10779 23:33:00.259067 <30>[ 20.210854] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10780 23:33:00.265768 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10781 23:33:00.295998 Starting [0;1;39mmodpr<30>[ 20.251309] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10782 23:33:00.299298 obe@configfs…m - Load Kernel Module configfs...
10783 23:33:00.328450 Starting [0;1;39mmodpr<30>[ 20.283619] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10784 23:33:00.331838 obe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10785 23:33:00.360412 Starting [0;1;39mmodpr<30>[ 20.315565] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10786 23:33:00.363793 obe@drm.service[0m - Load Kernel Module drm...
10787 23:33:00.375125 <6>[ 20.329795] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10788 23:33:00.384548 <30>[ 20.337818] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10789 23:33:00.391270 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10790 23:33:00.419764 Starting [0;1;39mmodpr<30>[ 20.375234] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10791 23:33:00.423309 obe@fuse.ser…e[0m - Load Kernel Module fuse...
10792 23:33:00.452219 Starting [0;1;39mmodpr<30>[ 20.407732] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10793 23:33:00.455670 obe@loop.ser…e[0m - Load Kernel Module loop...
10794 23:33:00.463199 <6>[ 20.425357] fuse: init (API version 7.37)
10795 23:33:00.488055 Starting [0;1;39msyste<30>[ 20.443378] systemd[1]: Starting systemd-journald.service - Journal Service...
10796 23:33:00.491498 md-journald.service[0m - Journal Service...
10797 23:33:00.526554 Starting [0;1;39msystemd-modules-l…r<30>[ 20.481881] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10798 23:33:00.529512 vice[0m - Load Kernel Modules...
10799 23:33:00.590667 Starting [0;1;39msyste<30>[ 20.542747] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10800 23:33:00.593798 md-network-g… units from Kernel command line...
10801 23:33:00.619570 Starting [0;1;39msyste<30>[ 20.574585] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10802 23:33:00.625886 md-remount-f…nt Root and Kernel File Systems...
10803 23:33:00.646877 Startin<30>[ 20.604952] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10804 23:33:00.657083 g [0;1;39msyste<3>[ 20.607919] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10805 23:33:00.663456 md-udev-trig…[0m - Coldplug All udev Devices...
10806 23:33:00.683530 <3>[ 20.639621] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10807 23:33:00.701000 [[0;32m OK [<30>[ 20.660078] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10808 23:33:00.707595 0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10809 23:33:00.731450 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.<30>[ 20.686093] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
10810 23:33:00.742102 mount[…- POSI<3>[ 20.692611] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10811 23:33:00.744688 X Message Queue File System.
10812 23:33:00.758317 <3>[ 20.715706] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10813 23:33:00.769219 [[0;32m OK [0m] Mounted [0;<30>[ 20.726805] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
10814 23:33:00.779138 1;39msys-kernel-<3>[ 20.737606] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10815 23:33:00.785723 debug.m…nt[0m - Kernel Debug File System.
10816 23:33:00.812642 [[0;32m OK [0m] Finished [0<30>[ 20.767228] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
10817 23:33:00.822552 <3>[ 20.774203] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10818 23:33:00.825646 ;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10819 23:33:00.838998 <3>[ 20.796393] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10820 23:33:00.850598 [[0;32m OK [<30>[ 20.808258] systemd[1]: modprobe@configfs.service: Deactivated successfully.
10821 23:33:00.860386 0m] Finished [0<30>[ 20.808727] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
10822 23:33:00.870101 ;1;39mmodprobe@c<3>[ 20.816668] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10823 23:33:00.873499 onfigfs…[0m - Load Kernel Module configfs.
10824 23:33:00.890635 <3>[ 20.846034] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10825 23:33:00.902147 [[0;32m OK [<30>[ 20.859610] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
10826 23:33:00.911931 0m] Finished [0<30>[ 20.860106] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
10827 23:33:00.925413 ;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Mo<3>[ 20.880107] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10828 23:33:00.926037 dule dm_mod.
10829 23:33:00.945620 [[0;32m OK [0m] Finished [0<30>[ 20.903344] systemd[1]: modprobe@drm.service: Deactivated successfully.
10830 23:33:00.955442 ;1;39mmodprobe@d<30>[ 20.903846] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
10831 23:33:00.958517 rm.service[0m - Load Kernel Module drm.
10832 23:33:00.983441 [[0;32m OK [0m] Started [0;1;39msystemd-jou<30>[ 20.938344] systemd[1]: Started systemd-journald.service - Journal Service.
10833 23:33:00.986729 rnald.service[0m - Journal Service.
10834 23:33:01.009468 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10835 23:33:01.030139 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
10836 23:33:01.056812 [[0;32m OK [<4>[ 21.009409] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10837 23:33:01.066949 0m] Finished [0<3>[ 21.009432] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10838 23:33:01.073547 ;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10839 23:33:01.092811 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10840 23:33:01.112377 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10841 23:33:01.132151 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
10842 23:33:01.152420 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10843 23:33:01.173924 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10844 23:33:01.218853 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
10845 23:33:01.240445 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10846 23:33:01.263738 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10847 23:33:01.328546 Starting [0;1;39msyste<46>[ 21.284793] systemd-journald[316]: Received client request to flush runtime journal.
10848 23:33:01.332100 md-random-se…ice[0m - Load/Save Random Seed...
10849 23:33:01.362083 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10850 23:33:01.587674 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10851 23:33:01.919396 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
10852 23:33:01.943179 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10853 23:33:01.964135 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10854 23:33:02.453489 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10855 23:33:02.780172 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10856 23:33:02.800382 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10857 23:33:02.844155 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10858 23:33:02.929760 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10859 23:33:02.947690 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10860 23:33:02.962630 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10861 23:33:03.007023 Starting [0;1;39msystemd-binfmt.se…et Up Additional Binary Formats...
10862 23:33:03.027325 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10863 23:33:03.059199 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10864 23:33:03.094694 [[0;1;31mFAILED[0m] Failed to start [0;1;39msystemd-bi… Set Up Additional Binary Formats.
10865 23:33:03.110955 See 'systemctl status systemd-binfmt.service' for details.
10866 23:33:03.332452 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10867 23:33:03.390514 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
10868 23:33:03.426947 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10869 23:33:03.559798 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10870 23:33:03.687963 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10871 23:33:03.713632 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10872 23:33:03.825521 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
10873 23:33:03.887351 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
10874 23:33:03.929680 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
10875 23:33:03.970781 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10876 23:33:04.018470 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
10877 23:33:04.038835 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10878 23:33:04.055116 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
10879 23:33:04.074144 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
10880 23:33:04.098394 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10881 23:33:04.114876 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10882 23:33:04.130183 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10883 23:33:04.154539 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
10884 23:33:04.173332 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
10885 23:33:04.190146 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
10886 23:33:04.209892 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
10887 23:33:04.229372 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
10888 23:33:04.246298 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
10889 23:33:04.264482 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
10890 23:33:04.283095 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
10891 23:33:04.298370 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
10892 23:33:04.314100 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
10893 23:33:04.355639 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
10894 23:33:04.420976 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
10895 23:33:04.556996 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
10896 23:33:04.584669 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
10897 23:33:04.639573 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
10898 23:33:04.745363 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
10899 23:33:04.769514 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
10900 23:33:04.788426 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
10901 23:33:04.823652 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
10902 23:33:04.884447 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
10903 23:33:04.908603 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
10904 23:33:04.924972 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
10905 23:33:04.943351 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
10906 23:33:04.974794 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
10907 23:33:04.992213 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
10908 23:33:05.051485 Starting [0;1;39msystemd-hostnamed.service[0m - Hostname Service...
10909 23:33:05.073097 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
10910 23:33:05.120558 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
10911 23:33:05.163791 [[0;32m OK [0m] Started [0;1;39msystemd-hostnamed.service[0m - Hostname Service.
10912 23:33:05.240943
10913 23:33:05.241122
10914 23:33:05.243732 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
10915 23:33:05.243819
10916 23:33:05.247133 debian-bookworm-arm64 login: root (automatic login)
10917 23:33:05.247214
10918 23:33:05.247279
10919 23:33:05.510219 Linux debian-bookworm-arm64 6.1.64-cip10-rt5 #1 SMP PREEMPT Sun Dec 3 22:38:18 UTC 2023 aarch64
10920 23:33:05.510364
10921 23:33:05.517116 The programs included with the Debian GNU/Linux system are free software;
10922 23:33:05.523698 the exact distribution terms for each program are described in the
10923 23:33:05.527136 individual files in /usr/share/doc/*/copyright.
10924 23:33:05.527210
10925 23:33:05.533731 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10926 23:33:05.536567 permitted by applicable law.
10927 23:33:06.550777 Matched prompt #10: / #
10929 23:33:06.551963 Setting prompt string to ['/ #']
10930 23:33:06.552396 end: 2.2.5.1 login-action (duration 00:00:27) [common]
10932 23:33:06.553379 end: 2.2.5 auto-login-action (duration 00:00:27) [common]
10933 23:33:06.553911 start: 2.2.6 expect-shell-connection (timeout 00:03:19) [common]
10934 23:33:06.554271 Setting prompt string to ['/ #']
10935 23:33:06.554585 Forcing a shell prompt, looking for ['/ #']
10937 23:33:06.605351 / #
10938 23:33:06.606056 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10939 23:33:06.606502 Waiting using forced prompt support (timeout 00:02:30)
10940 23:33:06.612226
10941 23:33:06.613183 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10942 23:33:06.613728 start: 2.2.7 export-device-env (timeout 00:03:19) [common]
10944 23:33:06.715063 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12172439/extract-nfsrootfs-awh02hkz'
10945 23:33:06.721745 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12172439/extract-nfsrootfs-awh02hkz'
10947 23:33:06.823531 / # export NFS_SERVER_IP='192.168.201.1'
10948 23:33:06.830760 export NFS_SERVER_IP='192.168.201.1'
10949 23:33:06.831709 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10950 23:33:06.832305 end: 2.2 depthcharge-retry (duration 00:01:42) [common]
10951 23:33:06.832818 end: 2 depthcharge-action (duration 00:01:42) [common]
10952 23:33:06.833308 start: 3 lava-test-retry (timeout 00:07:38) [common]
10953 23:33:06.833831 start: 3.1 lava-test-shell (timeout 00:07:38) [common]
10954 23:33:06.834309 Using namespace: common
10956 23:33:06.935539 / # #
10957 23:33:06.936282 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
10958 23:33:06.942424 #
10959 23:33:06.943435 Using /lava-12172439
10961 23:33:07.044908 / # export SHELL=/bin/bash
10962 23:33:07.051726 export SHELL=/bin/bash
10964 23:33:07.153440 / # . /lava-12172439/environment
10965 23:33:07.160192 . /lava-12172439/environment
10967 23:33:07.268163 / # /lava-12172439/bin/lava-test-runner /lava-12172439/0
10968 23:33:07.268818 Test shell timeout: 10s (minimum of the action and connection timeout)
10969 23:33:07.274812 /lava-12172439/bin/lava-test-runner /lava-12172439/0
10970 23:33:07.530442 + export TESTRUN_ID=0_timesync-off
10971 23:33:07.533639 + TESTRUN_ID=0_timesync-off
10972 23:33:07.536831 + cd /lava-12172439/0/tests/0_timesync-off
10973 23:33:07.540552 ++ cat uuid
10974 23:33:07.544024 + UUID=12172439_1.6.2.3.1
10975 23:33:07.544414 + set +x
10976 23:33:07.550411 <LAVA_SIGNAL_STARTRUN 0_timesync-off 12172439_1.6.2.3.1>
10977 23:33:07.550676 Received signal: <STARTRUN> 0_timesync-off 12172439_1.6.2.3.1
10978 23:33:07.550753 Starting test lava.0_timesync-off (12172439_1.6.2.3.1)
10979 23:33:07.550841 Skipping test definition patterns.
10980 23:33:07.553378 + systemctl stop systemd-timesyncd
10981 23:33:07.616079 + set +x
10982 23:33:07.619142 <LAVA_SIGNAL_ENDRUN 0_timesync-off 12172439_1.6.2.3.1>
10983 23:33:07.619824 Received signal: <ENDRUN> 0_timesync-off 12172439_1.6.2.3.1
10984 23:33:07.620240 Ending use of test pattern.
10985 23:33:07.620568 Ending test lava.0_timesync-off (12172439_1.6.2.3.1), duration 0.07
10987 23:33:07.684565 + export TESTRUN_ID=1_kselftest-alsa
10988 23:33:07.687945 + TESTRUN_ID=1_kselftest-alsa
10989 23:33:07.694676 + cd /lava-12172439/0/tests/1_kselftest-alsa
10990 23:33:07.694761 ++ cat uuid
10991 23:33:07.698183 + UUID=12172439_1.6.2.3.5
10992 23:33:07.698265 + set +x
10993 23:33:07.700962 <LAVA_SIGNAL_STARTRUN 1_kselftest-alsa 12172439_1.6.2.3.5>
10994 23:33:07.701217 Received signal: <STARTRUN> 1_kselftest-alsa 12172439_1.6.2.3.5
10995 23:33:07.701287 Starting test lava.1_kselftest-alsa (12172439_1.6.2.3.5)
10996 23:33:07.701368 Skipping test definition patterns.
10997 23:33:07.704384 + cd ./automated/linux/kselftest/
10998 23:33:07.730913 + ./kselftest.sh -c alsa -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.64-cip10-rt5/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip-gitlab -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
10999 23:33:07.757267 INFO: install_deps skipped
11000 23:33:08.254138 --2023-12-03 23:30:54-- http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.64-cip10-rt5/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11001 23:33:08.268875 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11002 23:33:08.398259 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11003 23:33:08.529815 HTTP request sent, awaiting response... 200 OK
11004 23:33:08.533051 Length: 2966880 (2.8M) [application/octet-stream]
11005 23:33:08.536079 Saving to: 'kselftest.tar.xz'
11006 23:33:08.536636
11007 23:33:08.537002
11008 23:33:08.787492 kselftest.tar.xz 0%[ ] 0 --.-KB/s
11009 23:33:09.045849 kselftest.tar.xz 1%[ ] 46.39K 185KB/s
11010 23:33:09.352295 kselftest.tar.xz 7%[> ] 217.50K 432KB/s
11011 23:33:09.619917 kselftest.tar.xz 28%[====> ] 818.47K 1019KB/s
11012 23:33:09.748770 kselftest.tar.xz 67%[============> ] 1.90M 1.78MB/s
11013 23:33:09.755429 kselftest.tar.xz 100%[===================>] 2.83M 2.37MB/s in 1.2s
11014 23:33:09.755519
11015 23:33:10.013122 2023-12-03 23:30:56 (2.37 MB/s) - 'kselftest.tar.xz' saved [2966880/2966880]
11016 23:33:10.013286
11017 23:33:16.397232 skiplist:
11018 23:33:16.400049 ========================================
11019 23:33:16.403661 ========================================
11020 23:33:16.449767 alsa:mixer-test
11021 23:33:16.469467 ============== Tests to run ===============
11022 23:33:16.469553 alsa:mixer-test
11023 23:33:16.472738 ===========End Tests to run ===============
11024 23:33:16.477489 shardfile-alsa pass
11025 23:33:16.586016 <12>[ 36.547940] kselftest: Running tests in alsa
11026 23:33:16.591540 TAP version 13
11027 23:33:16.606304 1..1
11028 23:33:16.621912 # selftests: alsa: mixer-test
11029 23:33:17.124216 # TAP version 13
11030 23:33:17.124738 # 1..0
11031 23:33:17.130830 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:0 error:0
11032 23:33:17.133561 ok 1 selftests: alsa: mixer-test
11033 23:33:17.868521 alsa_mixer-test pass
11034 23:33:17.914791 + ../../utils/send-to-lava.sh ./output/result.txt
11035 23:33:17.974887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-alsa RESULT=pass>
11036 23:33:17.975182 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-alsa RESULT=pass
11038 23:33:18.015777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test RESULT=pass>
11039 23:33:18.016216 + set +x
11040 23:33:18.016818 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test RESULT=pass
11042 23:33:18.022672 <LAVA_SIGNAL_ENDRUN 1_kselftest-alsa 12172439_1.6.2.3.5>
11043 23:33:18.023492 Received signal: <ENDRUN> 1_kselftest-alsa 12172439_1.6.2.3.5
11044 23:33:18.023878 Ending use of test pattern.
11045 23:33:18.024208 Ending test lava.1_kselftest-alsa (12172439_1.6.2.3.5), duration 10.32
11047 23:33:18.025474 <LAVA_TEST_RUNNER EXIT>
11048 23:33:18.026255 ok: lava_test_shell seems to have completed
11049 23:33:18.026766 alsa_mixer-test: pass
shardfile-alsa: pass
11050 23:33:18.027181 end: 3.1 lava-test-shell (duration 00:00:11) [common]
11051 23:33:18.027597 end: 3 lava-test-retry (duration 00:00:11) [common]
11052 23:33:18.028034 start: 4 finalize (timeout 00:07:27) [common]
11053 23:33:18.028502 start: 4.1 power-off (timeout 00:00:30) [common]
11054 23:33:18.029255 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=off'
11055 23:33:18.116041 >> Command sent successfully.
11056 23:33:18.120484 Returned 0 in 0 seconds
11057 23:33:18.221461 end: 4.1 power-off (duration 00:00:00) [common]
11059 23:33:18.223188 start: 4.2 read-feedback (timeout 00:07:27) [common]
11060 23:33:18.224506 Listened to connection for namespace 'common' for up to 1s
11061 23:33:19.225173 Finalising connection for namespace 'common'
11062 23:33:19.226022 Disconnecting from shell: Finalise
11063 23:33:19.226553 / #
11064 23:33:19.327676 end: 4.2 read-feedback (duration 00:00:01) [common]
11065 23:33:19.328462 end: 4 finalize (duration 00:00:01) [common]
11066 23:33:19.329087 Cleaning after the job
11067 23:33:19.329677 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12172439/tftp-deploy-5nfpohkk/ramdisk
11068 23:33:19.344106 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12172439/tftp-deploy-5nfpohkk/kernel
11069 23:33:19.377615 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12172439/tftp-deploy-5nfpohkk/dtb
11070 23:33:19.377892 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12172439/tftp-deploy-5nfpohkk/nfsrootfs
11071 23:33:19.477036 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12172439/tftp-deploy-5nfpohkk/modules
11072 23:33:19.484270 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12172439
11073 23:33:20.131915 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12172439
11074 23:33:20.132101 Job finished correctly