Boot log: mt8192-asurada-spherion-r0
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 24
- Kernel Errors: 35
- Errors: 0
1 23:38:04.114716 lava-dispatcher, installed at version: 2023.10
2 23:38:04.114925 start: 0 validate
3 23:38:04.115064 Start time: 2023-12-03 23:38:04.115056+00:00 (UTC)
4 23:38:04.115181 Using caching service: 'http://localhost/cache/?uri=%s'
5 23:38:04.115318 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230623.0%2Farm64%2Finitrd.cpio.gz exists
6 23:38:04.398532 Using caching service: 'http://localhost/cache/?uri=%s'
7 23:38:04.399261 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.64-cip10-rt5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 23:38:04.669659 Using caching service: 'http://localhost/cache/?uri=%s'
9 23:38:04.670480 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.64-cip10-rt5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 23:38:04.941863 Using caching service: 'http://localhost/cache/?uri=%s'
11 23:38:04.942636 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230623.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 23:38:05.211639 Using caching service: 'http://localhost/cache/?uri=%s'
13 23:38:05.212422 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.64-cip10-rt5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 23:38:05.489651 validate duration: 1.37
16 23:38:05.490912 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 23:38:05.491473 start: 1.1 download-retry (timeout 00:10:00) [common]
18 23:38:05.491985 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 23:38:05.492677 Not decompressing ramdisk as can be used compressed.
20 23:38:05.493169 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230623.0/arm64/initrd.cpio.gz
21 23:38:05.493545 saving as /var/lib/lava/dispatcher/tmp/12172444/tftp-deploy-t846xybh/ramdisk/initrd.cpio.gz
22 23:38:05.493997 total size: 4665395 (4 MB)
23 23:38:05.499577 progress 0 % (0 MB)
24 23:38:05.507717 progress 5 % (0 MB)
25 23:38:05.514612 progress 10 % (0 MB)
26 23:38:05.516097 progress 15 % (0 MB)
27 23:38:05.517341 progress 20 % (0 MB)
28 23:38:05.518616 progress 25 % (1 MB)
29 23:38:05.519873 progress 30 % (1 MB)
30 23:38:05.521109 progress 35 % (1 MB)
31 23:38:05.522395 progress 40 % (1 MB)
32 23:38:05.523874 progress 45 % (2 MB)
33 23:38:05.525109 progress 50 % (2 MB)
34 23:38:05.526401 progress 55 % (2 MB)
35 23:38:05.527629 progress 60 % (2 MB)
36 23:38:05.528853 progress 65 % (2 MB)
37 23:38:05.530131 progress 70 % (3 MB)
38 23:38:05.531417 progress 75 % (3 MB)
39 23:38:05.532646 progress 80 % (3 MB)
40 23:38:05.534102 progress 85 % (3 MB)
41 23:38:05.535333 progress 90 % (4 MB)
42 23:38:05.536557 progress 95 % (4 MB)
43 23:38:05.537853 progress 100 % (4 MB)
44 23:38:05.538006 4 MB downloaded in 0.04 s (101.03 MB/s)
45 23:38:05.538155 end: 1.1.1 http-download (duration 00:00:00) [common]
47 23:38:05.538397 end: 1.1 download-retry (duration 00:00:00) [common]
48 23:38:05.538483 start: 1.2 download-retry (timeout 00:10:00) [common]
49 23:38:05.538566 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 23:38:05.538699 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.64-cip10-rt5/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 23:38:05.538773 saving as /var/lib/lava/dispatcher/tmp/12172444/tftp-deploy-t846xybh/kernel/Image
52 23:38:05.538834 total size: 49172992 (46 MB)
53 23:38:05.538895 No compression specified
54 23:38:05.539970 progress 0 % (0 MB)
55 23:38:05.552799 progress 5 % (2 MB)
56 23:38:05.565567 progress 10 % (4 MB)
57 23:38:05.578428 progress 15 % (7 MB)
58 23:38:05.591427 progress 20 % (9 MB)
59 23:38:05.604212 progress 25 % (11 MB)
60 23:38:05.616913 progress 30 % (14 MB)
61 23:38:05.629656 progress 35 % (16 MB)
62 23:38:05.642311 progress 40 % (18 MB)
63 23:38:05.655100 progress 45 % (21 MB)
64 23:38:05.667756 progress 50 % (23 MB)
65 23:38:05.680421 progress 55 % (25 MB)
66 23:38:05.693231 progress 60 % (28 MB)
67 23:38:05.706016 progress 65 % (30 MB)
68 23:38:05.718873 progress 70 % (32 MB)
69 23:38:05.731485 progress 75 % (35 MB)
70 23:38:05.743968 progress 80 % (37 MB)
71 23:38:05.756583 progress 85 % (39 MB)
72 23:38:05.769294 progress 90 % (42 MB)
73 23:38:05.781675 progress 95 % (44 MB)
74 23:38:05.794074 progress 100 % (46 MB)
75 23:38:05.794279 46 MB downloaded in 0.26 s (183.58 MB/s)
76 23:38:05.794426 end: 1.2.1 http-download (duration 00:00:00) [common]
78 23:38:05.794654 end: 1.2 download-retry (duration 00:00:00) [common]
79 23:38:05.794745 start: 1.3 download-retry (timeout 00:10:00) [common]
80 23:38:05.794847 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 23:38:05.795034 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.64-cip10-rt5/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 23:38:05.795110 saving as /var/lib/lava/dispatcher/tmp/12172444/tftp-deploy-t846xybh/dtb/mt8192-asurada-spherion-r0.dtb
83 23:38:05.795172 total size: 47278 (0 MB)
84 23:38:05.795234 No compression specified
85 23:38:05.796349 progress 69 % (0 MB)
86 23:38:05.796622 progress 100 % (0 MB)
87 23:38:05.796776 0 MB downloaded in 0.00 s (28.15 MB/s)
88 23:38:05.796896 end: 1.3.1 http-download (duration 00:00:00) [common]
90 23:38:05.797116 end: 1.3 download-retry (duration 00:00:00) [common]
91 23:38:05.797202 start: 1.4 download-retry (timeout 00:10:00) [common]
92 23:38:05.797283 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 23:38:05.797395 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230623.0/arm64/full.rootfs.tar.xz
94 23:38:05.797461 saving as /var/lib/lava/dispatcher/tmp/12172444/tftp-deploy-t846xybh/nfsrootfs/full.rootfs.tar
95 23:38:05.797520 total size: 200813988 (191 MB)
96 23:38:05.797613 Using unxz to decompress xz
97 23:38:05.801633 progress 0 % (0 MB)
98 23:38:06.323899 progress 5 % (9 MB)
99 23:38:06.834875 progress 10 % (19 MB)
100 23:38:07.413438 progress 15 % (28 MB)
101 23:38:07.782812 progress 20 % (38 MB)
102 23:38:08.102973 progress 25 % (47 MB)
103 23:38:08.682871 progress 30 % (57 MB)
104 23:38:09.223800 progress 35 % (67 MB)
105 23:38:09.808890 progress 40 % (76 MB)
106 23:38:10.359846 progress 45 % (86 MB)
107 23:38:10.937379 progress 50 % (95 MB)
108 23:38:11.578325 progress 55 % (105 MB)
109 23:38:12.256266 progress 60 % (114 MB)
110 23:38:12.381440 progress 65 % (124 MB)
111 23:38:12.530330 progress 70 % (134 MB)
112 23:38:12.634957 progress 75 % (143 MB)
113 23:38:12.713318 progress 80 % (153 MB)
114 23:38:12.789394 progress 85 % (162 MB)
115 23:38:12.898709 progress 90 % (172 MB)
116 23:38:13.188999 progress 95 % (181 MB)
117 23:38:13.779488 progress 100 % (191 MB)
118 23:38:13.785015 191 MB downloaded in 7.99 s (23.98 MB/s)
119 23:38:13.785323 end: 1.4.1 http-download (duration 00:00:08) [common]
121 23:38:13.785795 end: 1.4 download-retry (duration 00:00:08) [common]
122 23:38:13.785929 start: 1.5 download-retry (timeout 00:09:52) [common]
123 23:38:13.786140 start: 1.5.1 http-download (timeout 00:09:52) [common]
124 23:38:13.786365 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.64-cip10-rt5/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 23:38:13.786469 saving as /var/lib/lava/dispatcher/tmp/12172444/tftp-deploy-t846xybh/modules/modules.tar
126 23:38:13.786564 total size: 8614132 (8 MB)
127 23:38:13.786662 Using unxz to decompress xz
128 23:38:13.790985 progress 0 % (0 MB)
129 23:38:13.812048 progress 5 % (0 MB)
130 23:38:13.835808 progress 10 % (0 MB)
131 23:38:13.858969 progress 15 % (1 MB)
132 23:38:13.882054 progress 20 % (1 MB)
133 23:38:13.906246 progress 25 % (2 MB)
134 23:38:13.935842 progress 30 % (2 MB)
135 23:38:13.961668 progress 35 % (2 MB)
136 23:38:13.984686 progress 40 % (3 MB)
137 23:38:14.008971 progress 45 % (3 MB)
138 23:38:14.034214 progress 50 % (4 MB)
139 23:38:14.058338 progress 55 % (4 MB)
140 23:38:14.083024 progress 60 % (4 MB)
141 23:38:14.108628 progress 65 % (5 MB)
142 23:38:14.135591 progress 70 % (5 MB)
143 23:38:14.158805 progress 75 % (6 MB)
144 23:38:14.186112 progress 80 % (6 MB)
145 23:38:14.211927 progress 85 % (7 MB)
146 23:38:14.236766 progress 90 % (7 MB)
147 23:38:14.266349 progress 95 % (7 MB)
148 23:38:14.294273 progress 100 % (8 MB)
149 23:38:14.300558 8 MB downloaded in 0.51 s (15.98 MB/s)
150 23:38:14.300815 end: 1.5.1 http-download (duration 00:00:01) [common]
152 23:38:14.301077 end: 1.5 download-retry (duration 00:00:01) [common]
153 23:38:14.301170 start: 1.6 prepare-tftp-overlay (timeout 00:09:51) [common]
154 23:38:14.301267 start: 1.6.1 extract-nfsrootfs (timeout 00:09:51) [common]
155 23:38:17.847849 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/12172444/extract-nfsrootfs-7o9ql60f
156 23:38:17.848056 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 23:38:17.848164 start: 1.6.2 lava-overlay (timeout 00:09:48) [common]
158 23:38:17.848335 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12172444/lava-overlay-zkv3z600
159 23:38:17.848469 makedir: /var/lib/lava/dispatcher/tmp/12172444/lava-overlay-zkv3z600/lava-12172444/bin
160 23:38:17.848572 makedir: /var/lib/lava/dispatcher/tmp/12172444/lava-overlay-zkv3z600/lava-12172444/tests
161 23:38:17.848672 makedir: /var/lib/lava/dispatcher/tmp/12172444/lava-overlay-zkv3z600/lava-12172444/results
162 23:38:17.848774 Creating /var/lib/lava/dispatcher/tmp/12172444/lava-overlay-zkv3z600/lava-12172444/bin/lava-add-keys
163 23:38:17.848924 Creating /var/lib/lava/dispatcher/tmp/12172444/lava-overlay-zkv3z600/lava-12172444/bin/lava-add-sources
164 23:38:17.849057 Creating /var/lib/lava/dispatcher/tmp/12172444/lava-overlay-zkv3z600/lava-12172444/bin/lava-background-process-start
165 23:38:17.849186 Creating /var/lib/lava/dispatcher/tmp/12172444/lava-overlay-zkv3z600/lava-12172444/bin/lava-background-process-stop
166 23:38:17.849314 Creating /var/lib/lava/dispatcher/tmp/12172444/lava-overlay-zkv3z600/lava-12172444/bin/lava-common-functions
167 23:38:17.849440 Creating /var/lib/lava/dispatcher/tmp/12172444/lava-overlay-zkv3z600/lava-12172444/bin/lava-echo-ipv4
168 23:38:17.849567 Creating /var/lib/lava/dispatcher/tmp/12172444/lava-overlay-zkv3z600/lava-12172444/bin/lava-install-packages
169 23:38:17.849857 Creating /var/lib/lava/dispatcher/tmp/12172444/lava-overlay-zkv3z600/lava-12172444/bin/lava-installed-packages
170 23:38:17.849985 Creating /var/lib/lava/dispatcher/tmp/12172444/lava-overlay-zkv3z600/lava-12172444/bin/lava-os-build
171 23:38:17.850112 Creating /var/lib/lava/dispatcher/tmp/12172444/lava-overlay-zkv3z600/lava-12172444/bin/lava-probe-channel
172 23:38:17.850238 Creating /var/lib/lava/dispatcher/tmp/12172444/lava-overlay-zkv3z600/lava-12172444/bin/lava-probe-ip
173 23:38:17.850364 Creating /var/lib/lava/dispatcher/tmp/12172444/lava-overlay-zkv3z600/lava-12172444/bin/lava-target-ip
174 23:38:17.850491 Creating /var/lib/lava/dispatcher/tmp/12172444/lava-overlay-zkv3z600/lava-12172444/bin/lava-target-mac
175 23:38:17.850618 Creating /var/lib/lava/dispatcher/tmp/12172444/lava-overlay-zkv3z600/lava-12172444/bin/lava-target-storage
176 23:38:17.850747 Creating /var/lib/lava/dispatcher/tmp/12172444/lava-overlay-zkv3z600/lava-12172444/bin/lava-test-case
177 23:38:17.850876 Creating /var/lib/lava/dispatcher/tmp/12172444/lava-overlay-zkv3z600/lava-12172444/bin/lava-test-event
178 23:38:17.851002 Creating /var/lib/lava/dispatcher/tmp/12172444/lava-overlay-zkv3z600/lava-12172444/bin/lava-test-feedback
179 23:38:17.851127 Creating /var/lib/lava/dispatcher/tmp/12172444/lava-overlay-zkv3z600/lava-12172444/bin/lava-test-raise
180 23:38:17.851254 Creating /var/lib/lava/dispatcher/tmp/12172444/lava-overlay-zkv3z600/lava-12172444/bin/lava-test-reference
181 23:38:17.851379 Creating /var/lib/lava/dispatcher/tmp/12172444/lava-overlay-zkv3z600/lava-12172444/bin/lava-test-runner
182 23:38:17.851506 Creating /var/lib/lava/dispatcher/tmp/12172444/lava-overlay-zkv3z600/lava-12172444/bin/lava-test-set
183 23:38:17.851635 Creating /var/lib/lava/dispatcher/tmp/12172444/lava-overlay-zkv3z600/lava-12172444/bin/lava-test-shell
184 23:38:17.851763 Updating /var/lib/lava/dispatcher/tmp/12172444/lava-overlay-zkv3z600/lava-12172444/bin/lava-add-keys (debian)
185 23:38:17.851918 Updating /var/lib/lava/dispatcher/tmp/12172444/lava-overlay-zkv3z600/lava-12172444/bin/lava-add-sources (debian)
186 23:38:17.852062 Updating /var/lib/lava/dispatcher/tmp/12172444/lava-overlay-zkv3z600/lava-12172444/bin/lava-install-packages (debian)
187 23:38:17.852204 Updating /var/lib/lava/dispatcher/tmp/12172444/lava-overlay-zkv3z600/lava-12172444/bin/lava-installed-packages (debian)
188 23:38:17.852345 Updating /var/lib/lava/dispatcher/tmp/12172444/lava-overlay-zkv3z600/lava-12172444/bin/lava-os-build (debian)
189 23:38:17.852468 Creating /var/lib/lava/dispatcher/tmp/12172444/lava-overlay-zkv3z600/lava-12172444/environment
190 23:38:17.852566 LAVA metadata
191 23:38:17.852638 - LAVA_JOB_ID=12172444
192 23:38:17.852703 - LAVA_DISPATCHER_IP=192.168.201.1
193 23:38:17.852805 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:48) [common]
194 23:38:17.852871 skipped lava-vland-overlay
195 23:38:17.852946 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 23:38:17.853037 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:48) [common]
197 23:38:17.853101 skipped lava-multinode-overlay
198 23:38:17.853175 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 23:38:17.853254 start: 1.6.2.3 test-definition (timeout 00:09:48) [common]
200 23:38:17.853328 Loading test definitions
201 23:38:17.853418 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:48) [common]
202 23:38:17.853489 Using /lava-12172444 at stage 0
203 23:38:17.853824 uuid=12172444_1.6.2.3.1 testdef=None
204 23:38:17.853914 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 23:38:17.854000 start: 1.6.2.3.2 test-overlay (timeout 00:09:48) [common]
206 23:38:17.854457 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 23:38:17.854675 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:48) [common]
209 23:38:17.855236 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 23:38:17.855465 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:48) [common]
212 23:38:17.856008 runner path: /var/lib/lava/dispatcher/tmp/12172444/lava-overlay-zkv3z600/lava-12172444/0/tests/0_timesync-off test_uuid 12172444_1.6.2.3.1
213 23:38:17.856167 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 23:38:17.856393 start: 1.6.2.3.5 git-repo-action (timeout 00:09:48) [common]
216 23:38:17.856465 Using /lava-12172444 at stage 0
217 23:38:17.856563 Fetching tests from https://github.com/kernelci/test-definitions.git
218 23:38:17.856641 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/12172444/lava-overlay-zkv3z600/lava-12172444/0/tests/1_kselftest-arm64'
219 23:38:20.410907 Running '/usr/bin/git checkout kernelci.org
220 23:38:20.558396 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/12172444/lava-overlay-zkv3z600/lava-12172444/0/tests/1_kselftest-arm64/automated/linux/kselftest/kselftest.yaml
221 23:38:20.559132 uuid=12172444_1.6.2.3.5 testdef=None
222 23:38:20.559279 end: 1.6.2.3.5 git-repo-action (duration 00:00:03) [common]
224 23:38:20.559542 start: 1.6.2.3.6 test-overlay (timeout 00:09:45) [common]
225 23:38:20.560295 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 23:38:20.560523 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:45) [common]
228 23:38:20.561497 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 23:38:20.561777 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:45) [common]
231 23:38:20.562682 runner path: /var/lib/lava/dispatcher/tmp/12172444/lava-overlay-zkv3z600/lava-12172444/0/tests/1_kselftest-arm64 test_uuid 12172444_1.6.2.3.5
232 23:38:20.562774 BOARD='mt8192-asurada-spherion-r0'
233 23:38:20.562837 BRANCH='cip-gitlab'
234 23:38:20.562895 SKIPFILE='/dev/null'
235 23:38:20.562951 SKIP_INSTALL='True'
236 23:38:20.563005 TESTPROG_URL='http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.64-cip10-rt5/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 23:38:20.563061 TST_CASENAME=''
238 23:38:20.563114 TST_CMDFILES='arm64'
239 23:38:20.563253 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 23:38:20.563469 Creating lava-test-runner.conf files
242 23:38:20.563578 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12172444/lava-overlay-zkv3z600/lava-12172444/0 for stage 0
243 23:38:20.563670 - 0_timesync-off
244 23:38:20.563740 - 1_kselftest-arm64
245 23:38:20.563835 end: 1.6.2.3 test-definition (duration 00:00:03) [common]
246 23:38:20.563921 start: 1.6.2.4 compress-overlay (timeout 00:09:45) [common]
247 23:38:27.948622 end: 1.6.2.4 compress-overlay (duration 00:00:07) [common]
248 23:38:27.948777 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:38) [common]
249 23:38:27.948867 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 23:38:27.948962 end: 1.6.2 lava-overlay (duration 00:00:10) [common]
251 23:38:27.949050 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:38) [common]
252 23:38:28.068291 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 23:38:28.068693 start: 1.6.4 extract-modules (timeout 00:09:37) [common]
254 23:38:28.068811 extracting modules file /var/lib/lava/dispatcher/tmp/12172444/tftp-deploy-t846xybh/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12172444/extract-nfsrootfs-7o9ql60f
255 23:38:28.289913 extracting modules file /var/lib/lava/dispatcher/tmp/12172444/tftp-deploy-t846xybh/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12172444/extract-overlay-ramdisk-sg4v6dlh/ramdisk
256 23:38:28.517805 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 23:38:28.517973 start: 1.6.5 apply-overlay-tftp (timeout 00:09:37) [common]
258 23:38:28.518068 [common] Applying overlay to NFS
259 23:38:28.518138 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12172444/compress-overlay-88udq81z/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12172444/extract-nfsrootfs-7o9ql60f
260 23:38:29.433496 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 23:38:29.433717 start: 1.6.6 configure-preseed-file (timeout 00:09:36) [common]
262 23:38:29.433814 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 23:38:29.433904 start: 1.6.7 compress-ramdisk (timeout 00:09:36) [common]
264 23:38:29.433988 Building ramdisk /var/lib/lava/dispatcher/tmp/12172444/extract-overlay-ramdisk-sg4v6dlh/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12172444/extract-overlay-ramdisk-sg4v6dlh/ramdisk
265 23:38:29.762524 >> 119416 blocks
266 23:38:31.693153 rename /var/lib/lava/dispatcher/tmp/12172444/extract-overlay-ramdisk-sg4v6dlh/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12172444/tftp-deploy-t846xybh/ramdisk/ramdisk.cpio.gz
267 23:38:31.693655 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 23:38:31.693775 start: 1.6.8 prepare-kernel (timeout 00:09:34) [common]
269 23:38:31.693877 start: 1.6.8.1 prepare-fit (timeout 00:09:34) [common]
270 23:38:31.693985 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12172444/tftp-deploy-t846xybh/kernel/Image'
271 23:38:43.547355 Returned 0 in 11 seconds
272 23:38:43.648387 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12172444/tftp-deploy-t846xybh/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12172444/tftp-deploy-t846xybh/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12172444/tftp-deploy-t846xybh/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12172444/tftp-deploy-t846xybh/kernel/image.itb
273 23:38:44.029841 output: FIT description: Kernel Image image with one or more FDT blobs
274 23:38:44.030281 output: Created: Sun Dec 3 23:38:43 2023
275 23:38:44.030359 output: Image 0 (kernel-1)
276 23:38:44.030426 output: Description:
277 23:38:44.030491 output: Created: Sun Dec 3 23:38:43 2023
278 23:38:44.030552 output: Type: Kernel Image
279 23:38:44.030612 output: Compression: lzma compressed
280 23:38:44.030669 output: Data Size: 11049348 Bytes = 10790.38 KiB = 10.54 MiB
281 23:38:44.030730 output: Architecture: AArch64
282 23:38:44.030788 output: OS: Linux
283 23:38:44.030841 output: Load Address: 0x00000000
284 23:38:44.030898 output: Entry Point: 0x00000000
285 23:38:44.030955 output: Hash algo: crc32
286 23:38:44.031011 output: Hash value: c85ea8f0
287 23:38:44.031067 output: Image 1 (fdt-1)
288 23:38:44.031120 output: Description: mt8192-asurada-spherion-r0
289 23:38:44.031172 output: Created: Sun Dec 3 23:38:43 2023
290 23:38:44.031225 output: Type: Flat Device Tree
291 23:38:44.031277 output: Compression: uncompressed
292 23:38:44.031330 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
293 23:38:44.031381 output: Architecture: AArch64
294 23:38:44.031433 output: Hash algo: crc32
295 23:38:44.031485 output: Hash value: cc4352de
296 23:38:44.031538 output: Image 2 (ramdisk-1)
297 23:38:44.031590 output: Description: unavailable
298 23:38:44.031642 output: Created: Sun Dec 3 23:38:43 2023
299 23:38:44.031694 output: Type: RAMDisk Image
300 23:38:44.031746 output: Compression: Unknown Compression
301 23:38:44.031798 output: Data Size: 17795439 Bytes = 17378.36 KiB = 16.97 MiB
302 23:38:44.031850 output: Architecture: AArch64
303 23:38:44.031902 output: OS: Linux
304 23:38:44.031954 output: Load Address: unavailable
305 23:38:44.032005 output: Entry Point: unavailable
306 23:38:44.032057 output: Hash algo: crc32
307 23:38:44.032108 output: Hash value: 78f1ee23
308 23:38:44.032159 output: Default Configuration: 'conf-1'
309 23:38:44.032211 output: Configuration 0 (conf-1)
310 23:38:44.032264 output: Description: mt8192-asurada-spherion-r0
311 23:38:44.032315 output: Kernel: kernel-1
312 23:38:44.032367 output: Init Ramdisk: ramdisk-1
313 23:38:44.032417 output: FDT: fdt-1
314 23:38:44.032469 output: Loadables: kernel-1
315 23:38:44.032519 output:
316 23:38:44.032720 end: 1.6.8.1 prepare-fit (duration 00:00:12) [common]
317 23:38:44.032821 end: 1.6.8 prepare-kernel (duration 00:00:12) [common]
318 23:38:44.032924 end: 1.6 prepare-tftp-overlay (duration 00:00:30) [common]
319 23:38:44.033014 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:21) [common]
320 23:38:44.033095 No LXC device requested
321 23:38:44.033173 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 23:38:44.033254 start: 1.8 deploy-device-env (timeout 00:09:21) [common]
323 23:38:44.033330 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 23:38:44.033398 Checking files for TFTP limit of 4294967296 bytes.
325 23:38:44.033966 end: 1 tftp-deploy (duration 00:00:39) [common]
326 23:38:44.034118 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 23:38:44.034258 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 23:38:44.034397 substitutions:
329 23:38:44.034469 - {DTB}: 12172444/tftp-deploy-t846xybh/dtb/mt8192-asurada-spherion-r0.dtb
330 23:38:44.034552 - {INITRD}: 12172444/tftp-deploy-t846xybh/ramdisk/ramdisk.cpio.gz
331 23:38:44.034632 - {KERNEL}: 12172444/tftp-deploy-t846xybh/kernel/Image
332 23:38:44.034710 - {LAVA_MAC}: None
333 23:38:44.034807 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/12172444/extract-nfsrootfs-7o9ql60f
334 23:38:44.034903 - {NFS_SERVER_IP}: 192.168.201.1
335 23:38:44.034997 - {PRESEED_CONFIG}: None
336 23:38:44.035093 - {PRESEED_LOCAL}: None
337 23:38:44.035187 - {RAMDISK}: 12172444/tftp-deploy-t846xybh/ramdisk/ramdisk.cpio.gz
338 23:38:44.035281 - {ROOT_PART}: None
339 23:38:44.035374 - {ROOT}: None
340 23:38:44.035467 - {SERVER_IP}: 192.168.201.1
341 23:38:44.035560 - {TEE}: None
342 23:38:44.035656 Parsed boot commands:
343 23:38:44.035748 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 23:38:44.035989 Parsed boot commands: tftpboot 192.168.201.1 12172444/tftp-deploy-t846xybh/kernel/image.itb 12172444/tftp-deploy-t846xybh/kernel/cmdline
345 23:38:44.036112 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 23:38:44.036234 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 23:38:44.036370 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 23:38:44.036498 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 23:38:44.036603 Not connected, no need to disconnect.
350 23:38:44.036718 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 23:38:44.036844 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 23:38:44.036947 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-0'
353 23:38:44.041259 Setting prompt string to ['lava-test: # ']
354 23:38:44.041704 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 23:38:44.041833 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 23:38:44.041953 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 23:38:44.042077 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 23:38:44.042426 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=reboot'
359 23:38:49.191399 >> Command sent successfully.
360 23:38:49.202235 Returned 0 in 5 seconds
361 23:38:49.303500 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 23:38:49.305251 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 23:38:49.306076 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 23:38:49.306653 Setting prompt string to 'Starting depthcharge on Spherion...'
366 23:38:49.307125 Changing prompt to 'Starting depthcharge on Spherion...'
367 23:38:49.307626 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 23:38:49.309307 [Enter `^Ec?' for help]
369 23:38:49.469297
370 23:38:49.469906
371 23:38:49.470374 F0: 102B 0000
372 23:38:49.470807
373 23:38:49.471218 F3: 1001 0000 [0200]
374 23:38:49.471955
375 23:38:49.472315 F3: 1001 0000
376 23:38:49.472723
377 23:38:49.473119 F7: 102D 0000
378 23:38:49.473515
379 23:38:49.475285 F1: 0000 0000
380 23:38:49.475724
381 23:38:49.476168 V0: 0000 0000 [0001]
382 23:38:49.476697
383 23:38:49.478552 00: 0007 8000
384 23:38:49.479010
385 23:38:49.479454 01: 0000 0000
386 23:38:49.479882
387 23:38:49.482050 BP: 0C00 0209 [0000]
388 23:38:49.482516
389 23:38:49.482959 G0: 1182 0000
390 23:38:49.483379
391 23:38:49.486003 EC: 0000 0021 [4000]
392 23:38:49.486439
393 23:38:49.486880 S7: 0000 0000 [0000]
394 23:38:49.487302
395 23:38:49.489227 CC: 0000 0000 [0001]
396 23:38:49.489913
397 23:38:49.490356 T0: 0000 0040 [010F]
398 23:38:49.490772
399 23:38:49.491279 Jump to BL
400 23:38:49.491686
401 23:38:49.516242
402 23:38:49.516812
403 23:38:49.517262
404 23:38:49.523260 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 23:38:49.527252 ARM64: Exception handlers installed.
406 23:38:49.530552 ARM64: Testing exception
407 23:38:49.534446 ARM64: Done test exception
408 23:38:49.541092 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 23:38:49.551849 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 23:38:49.557987 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 23:38:49.567751 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 23:38:49.574605 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 23:38:49.580951 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 23:38:49.593062 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 23:38:49.600059 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 23:38:49.618535 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 23:38:49.622277 WDT: Last reset was cold boot
418 23:38:49.625745 SPI1(PAD0) initialized at 2873684 Hz
419 23:38:49.628734 SPI5(PAD0) initialized at 992727 Hz
420 23:38:49.631918 VBOOT: Loading verstage.
421 23:38:49.638689 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 23:38:49.642190 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 23:38:49.645610 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 23:38:49.648455 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 23:38:49.656497 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 23:38:49.662890 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 23:38:49.674153 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
428 23:38:49.674758
429 23:38:49.675147
430 23:38:49.684111 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 23:38:49.687588 ARM64: Exception handlers installed.
432 23:38:49.690814 ARM64: Testing exception
433 23:38:49.691284 ARM64: Done test exception
434 23:38:49.697568 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 23:38:49.700826 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 23:38:49.714933 Probing TPM: . done!
437 23:38:49.715512 TPM ready after 0 ms
438 23:38:49.722317 Connected to device vid:did:rid of 1ae0:0028:00
439 23:38:49.728796 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
440 23:38:49.787612 Initialized TPM device CR50 revision 0
441 23:38:49.799125 tlcl_send_startup: Startup return code is 0
442 23:38:49.799874 TPM: setup succeeded
443 23:38:49.810756 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 23:38:49.819844 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 23:38:49.833465 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 23:38:49.840877 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 23:38:49.844469 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 23:38:49.848082 in-header: 03 07 00 00 08 00 00 00
449 23:38:49.851383 in-data: aa e4 47 04 13 02 00 00
450 23:38:49.851866 Chrome EC: UHEPI supported
451 23:38:49.858454 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 23:38:49.863648 in-header: 03 95 00 00 08 00 00 00
453 23:38:49.866981 in-data: 18 20 20 08 00 00 00 00
454 23:38:49.867524 Phase 1
455 23:38:49.871069 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 23:38:49.878471 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 23:38:49.885414 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 23:38:49.885908 Recovery requested (1009000e)
459 23:38:49.898359 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 23:38:49.901946 tlcl_extend: response is 0
461 23:38:49.911636 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 23:38:49.916654 tlcl_extend: response is 0
463 23:38:49.923629 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 23:38:49.943841 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
465 23:38:49.950318 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 23:38:49.950897
467 23:38:49.951280
468 23:38:49.960866 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 23:38:49.963532 ARM64: Exception handlers installed.
470 23:38:49.966809 ARM64: Testing exception
471 23:38:49.967288 ARM64: Done test exception
472 23:38:49.989180 pmic_efuse_setting: Set efuses in 11 msecs
473 23:38:49.992355 pmwrap_interface_init: Select PMIF_VLD_RDY
474 23:38:49.999320 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 23:38:50.002909 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 23:38:50.006274 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 23:38:50.014052 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 23:38:50.017546 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 23:38:50.020965 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 23:38:50.028179 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 23:38:50.032237 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 23:38:50.035844 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 23:38:50.043857 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 23:38:50.047234 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 23:38:50.050651 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 23:38:50.054887 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 23:38:50.061809 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 23:38:50.065392 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 23:38:50.073016 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 23:38:50.077040 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 23:38:50.084264 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 23:38:50.088197 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 23:38:50.095245 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 23:38:50.099015 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 23:38:50.106794 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 23:38:50.110444 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 23:38:50.118087 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 23:38:50.122115 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 23:38:50.129410 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 23:38:50.133443 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 23:38:50.136541 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 23:38:50.144223 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 23:38:50.147830 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 23:38:50.151319 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 23:38:50.158830 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 23:38:50.161955 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 23:38:50.169474 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 23:38:50.172930 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 23:38:50.176818 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 23:38:50.184026 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 23:38:50.187871 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 23:38:50.191321 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 23:38:50.195122 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 23:38:50.202450 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 23:38:50.206405 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 23:38:50.209992 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 23:38:50.213503 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 23:38:50.217574 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 23:38:50.224946 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 23:38:50.227843 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 23:38:50.231938 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 23:38:50.235596 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 23:38:50.238739 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 23:38:50.242691 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 23:38:50.253720 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 23:38:50.261121 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 23:38:50.264848 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 23:38:50.272398 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 23:38:50.283696 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 23:38:50.287225 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 23:38:50.290531 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 23:38:50.294119 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 23:38:50.302215 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x0
534 23:38:50.305792 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 23:38:50.313832 [RTC]rtc_osc_init,62: osc32con val = 0xde70
536 23:38:50.317011 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 23:38:50.326431 [RTC]rtc_get_frequency_meter,154: input=15, output=759
538 23:38:50.336527 [RTC]rtc_get_frequency_meter,154: input=23, output=942
539 23:38:50.345699 [RTC]rtc_get_frequency_meter,154: input=19, output=850
540 23:38:50.354822 [RTC]rtc_get_frequency_meter,154: input=17, output=805
541 23:38:50.366961 [RTC]rtc_get_frequency_meter,154: input=16, output=782
542 23:38:50.374233 [RTC]rtc_get_frequency_meter,154: input=16, output=782
543 23:38:50.384097 [RTC]rtc_get_frequency_meter,154: input=17, output=805
544 23:38:50.387621 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
545 23:38:50.394328 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
546 23:38:50.398309 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
547 23:38:50.402089 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
548 23:38:50.405673 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
549 23:38:50.409092 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
550 23:38:50.413339 ADC[4]: Raw value=906203 ID=7
551 23:38:50.416540 ADC[3]: Raw value=213441 ID=1
552 23:38:50.416854 RAM Code: 0x71
553 23:38:50.420763 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
554 23:38:50.427757 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
555 23:38:50.434741 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
556 23:38:50.442178 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
557 23:38:50.445639 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
558 23:38:50.449796 in-header: 03 07 00 00 08 00 00 00
559 23:38:50.449898 in-data: aa e4 47 04 13 02 00 00
560 23:38:50.453260 Chrome EC: UHEPI supported
561 23:38:50.460850 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
562 23:38:50.464382 in-header: 03 95 00 00 08 00 00 00
563 23:38:50.468063 in-data: 18 20 20 08 00 00 00 00
564 23:38:50.471674 MRC: failed to locate region type 0.
565 23:38:50.476158 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
566 23:38:50.479326 DRAM-K: Running full calibration
567 23:38:50.486711 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
568 23:38:50.486842 header.status = 0x0
569 23:38:50.490572 header.version = 0x6 (expected: 0x6)
570 23:38:50.494314 header.size = 0xd00 (expected: 0xd00)
571 23:38:50.494414 header.flags = 0x0
572 23:38:50.501255 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
573 23:38:50.520978 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
574 23:38:50.528557 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
575 23:38:50.528665 dram_init: ddr_geometry: 2
576 23:38:50.532304 [EMI] MDL number = 2
577 23:38:50.532394 [EMI] Get MDL freq = 0
578 23:38:50.536799 dram_init: ddr_type: 0
579 23:38:50.536886 is_discrete_lpddr4: 1
580 23:38:50.540005 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
581 23:38:50.540093
582 23:38:50.540179
583 23:38:50.543839 [Bian_co] ETT version 0.0.0.1
584 23:38:50.547847 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
585 23:38:50.547935
586 23:38:50.551217 dramc_set_vcore_voltage set vcore to 650000
587 23:38:50.554748 Read voltage for 800, 4
588 23:38:50.554835 Vio18 = 0
589 23:38:50.558969 Vcore = 650000
590 23:38:50.559055 Vdram = 0
591 23:38:50.559141 Vddq = 0
592 23:38:50.559226 Vmddr = 0
593 23:38:50.562541 dram_init: config_dvfs: 1
594 23:38:50.565921 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
595 23:38:50.573650 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
596 23:38:50.577566 [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9
597 23:38:50.581228 freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9
598 23:38:50.584566 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
599 23:38:50.589265 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
600 23:38:50.589358 MEM_TYPE=3, freq_sel=18
601 23:38:50.592085 sv_algorithm_assistance_LP4_1600
602 23:38:50.598913 ============ PULL DRAM RESETB DOWN ============
603 23:38:50.601774 ========== PULL DRAM RESETB DOWN end =========
604 23:38:50.605445 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
605 23:38:50.608552 ===================================
606 23:38:50.612184 LPDDR4 DRAM CONFIGURATION
607 23:38:50.616633 ===================================
608 23:38:50.616723 EX_ROW_EN[0] = 0x0
609 23:38:50.620063 EX_ROW_EN[1] = 0x0
610 23:38:50.620149 LP4Y_EN = 0x0
611 23:38:50.624208 WORK_FSP = 0x0
612 23:38:50.624293 WL = 0x2
613 23:38:50.627856 RL = 0x2
614 23:38:50.627942 BL = 0x2
615 23:38:50.628029 RPST = 0x0
616 23:38:50.630970 RD_PRE = 0x0
617 23:38:50.631056 WR_PRE = 0x1
618 23:38:50.634368 WR_PST = 0x0
619 23:38:50.634453 DBI_WR = 0x0
620 23:38:50.637700 DBI_RD = 0x0
621 23:38:50.637785 OTF = 0x1
622 23:38:50.641146 ===================================
623 23:38:50.644550 ===================================
624 23:38:50.647821 ANA top config
625 23:38:50.651072 ===================================
626 23:38:50.654926 DLL_ASYNC_EN = 0
627 23:38:50.655013 ALL_SLAVE_EN = 1
628 23:38:50.657967 NEW_RANK_MODE = 1
629 23:38:50.661423 DLL_IDLE_MODE = 1
630 23:38:50.664719 LP45_APHY_COMB_EN = 1
631 23:38:50.668237 TX_ODT_DIS = 1
632 23:38:50.668328 NEW_8X_MODE = 1
633 23:38:50.671629 ===================================
634 23:38:50.675171 ===================================
635 23:38:50.678443 data_rate = 1600
636 23:38:50.681716 CKR = 1
637 23:38:50.685166 DQ_P2S_RATIO = 8
638 23:38:50.688484 ===================================
639 23:38:50.688586 CA_P2S_RATIO = 8
640 23:38:50.691562 DQ_CA_OPEN = 0
641 23:38:50.695118 DQ_SEMI_OPEN = 0
642 23:38:50.698566 CA_SEMI_OPEN = 0
643 23:38:50.702038 CA_FULL_RATE = 0
644 23:38:50.705378 DQ_CKDIV4_EN = 1
645 23:38:50.705871 CA_CKDIV4_EN = 1
646 23:38:50.709239 CA_PREDIV_EN = 0
647 23:38:50.712085 PH8_DLY = 0
648 23:38:50.715297 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
649 23:38:50.718386 DQ_AAMCK_DIV = 4
650 23:38:50.721706 CA_AAMCK_DIV = 4
651 23:38:50.722144 CA_ADMCK_DIV = 4
652 23:38:50.725569 DQ_TRACK_CA_EN = 0
653 23:38:50.728547 CA_PICK = 800
654 23:38:50.732300 CA_MCKIO = 800
655 23:38:50.735927 MCKIO_SEMI = 0
656 23:38:50.739762 PLL_FREQ = 3068
657 23:38:50.739998 DQ_UI_PI_RATIO = 32
658 23:38:50.743691 CA_UI_PI_RATIO = 0
659 23:38:50.747238 ===================================
660 23:38:50.750847 ===================================
661 23:38:50.751010 memory_type:LPDDR4
662 23:38:50.754436 GP_NUM : 10
663 23:38:50.758756 SRAM_EN : 1
664 23:38:50.758877 MD32_EN : 0
665 23:38:50.761957 ===================================
666 23:38:50.765681 [ANA_INIT] >>>>>>>>>>>>>>
667 23:38:50.765789 <<<<<< [CONFIGURE PHASE]: ANA_TX
668 23:38:50.769057 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
669 23:38:50.772324 ===================================
670 23:38:50.775736 data_rate = 1600,PCW = 0X7600
671 23:38:50.779204 ===================================
672 23:38:50.782433 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
673 23:38:50.789446 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 23:38:50.792588 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
675 23:38:50.799622 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
676 23:38:50.802565 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
677 23:38:50.806346 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
678 23:38:50.806429 [ANA_INIT] flow start
679 23:38:50.809819 [ANA_INIT] PLL >>>>>>>>
680 23:38:50.813451 [ANA_INIT] PLL <<<<<<<<
681 23:38:50.814012 [ANA_INIT] MIDPI >>>>>>>>
682 23:38:50.816539 [ANA_INIT] MIDPI <<<<<<<<
683 23:38:50.819988 [ANA_INIT] DLL >>>>>>>>
684 23:38:50.820411 [ANA_INIT] flow end
685 23:38:50.826151 ============ LP4 DIFF to SE enter ============
686 23:38:50.829514 ============ LP4 DIFF to SE exit ============
687 23:38:50.833372 [ANA_INIT] <<<<<<<<<<<<<
688 23:38:50.836618 [Flow] Enable top DCM control >>>>>
689 23:38:50.839888 [Flow] Enable top DCM control <<<<<
690 23:38:50.840348 Enable DLL master slave shuffle
691 23:38:50.846426 ==============================================================
692 23:38:50.849939 Gating Mode config
693 23:38:50.853753 ==============================================================
694 23:38:50.856390 Config description:
695 23:38:50.866779 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
696 23:38:50.873118 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
697 23:38:50.876298 SELPH_MODE 0: By rank 1: By Phase
698 23:38:50.883129 ==============================================================
699 23:38:50.886515 GAT_TRACK_EN = 1
700 23:38:50.889755 RX_GATING_MODE = 2
701 23:38:50.889888 RX_GATING_TRACK_MODE = 2
702 23:38:50.893083 SELPH_MODE = 1
703 23:38:50.896417 PICG_EARLY_EN = 1
704 23:38:50.899691 VALID_LAT_VALUE = 1
705 23:38:50.906385 ==============================================================
706 23:38:50.909719 Enter into Gating configuration >>>>
707 23:38:50.912847 Exit from Gating configuration <<<<
708 23:38:50.916366 Enter into DVFS_PRE_config >>>>>
709 23:38:50.926299 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
710 23:38:50.929450 Exit from DVFS_PRE_config <<<<<
711 23:38:50.932775 Enter into PICG configuration >>>>
712 23:38:50.936389 Exit from PICG configuration <<<<
713 23:38:50.940045 [RX_INPUT] configuration >>>>>
714 23:38:50.942965 [RX_INPUT] configuration <<<<<
715 23:38:50.946281 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
716 23:38:50.952730 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
717 23:38:50.959632 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
718 23:38:50.962934 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
719 23:38:50.970061 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
720 23:38:50.976333 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
721 23:38:50.979660 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
722 23:38:50.983090 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
723 23:38:50.990009 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
724 23:38:50.993180 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
725 23:38:50.996711 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
726 23:38:51.003482 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
727 23:38:51.006766 ===================================
728 23:38:51.006970 LPDDR4 DRAM CONFIGURATION
729 23:38:51.009900 ===================================
730 23:38:51.013677 EX_ROW_EN[0] = 0x0
731 23:38:51.013998 EX_ROW_EN[1] = 0x0
732 23:38:51.016924 LP4Y_EN = 0x0
733 23:38:51.017224 WORK_FSP = 0x0
734 23:38:51.020215 WL = 0x2
735 23:38:51.023416 RL = 0x2
736 23:38:51.023840 BL = 0x2
737 23:38:51.026750 RPST = 0x0
738 23:38:51.027173 RD_PRE = 0x0
739 23:38:51.030146 WR_PRE = 0x1
740 23:38:51.030569 WR_PST = 0x0
741 23:38:51.033621 DBI_WR = 0x0
742 23:38:51.034045 DBI_RD = 0x0
743 23:38:51.036853 OTF = 0x1
744 23:38:51.040197 ===================================
745 23:38:51.043644 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
746 23:38:51.047436 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
747 23:38:51.050029 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
748 23:38:51.053556 ===================================
749 23:38:51.056712 LPDDR4 DRAM CONFIGURATION
750 23:38:51.060686 ===================================
751 23:38:51.064016 EX_ROW_EN[0] = 0x10
752 23:38:51.064856 EX_ROW_EN[1] = 0x0
753 23:38:51.067009 LP4Y_EN = 0x0
754 23:38:51.067481 WORK_FSP = 0x0
755 23:38:51.070433 WL = 0x2
756 23:38:51.070904 RL = 0x2
757 23:38:51.073616 BL = 0x2
758 23:38:51.074298 RPST = 0x0
759 23:38:51.077115 RD_PRE = 0x0
760 23:38:51.077620 WR_PRE = 0x1
761 23:38:51.080169 WR_PST = 0x0
762 23:38:51.080734 DBI_WR = 0x0
763 23:38:51.083639 DBI_RD = 0x0
764 23:38:51.087172 OTF = 0x1
765 23:38:51.090110 ===================================
766 23:38:51.093346 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
767 23:38:51.098575 nWR fixed to 40
768 23:38:51.101639 [ModeRegInit_LP4] CH0 RK0
769 23:38:51.102087 [ModeRegInit_LP4] CH0 RK1
770 23:38:51.105563 [ModeRegInit_LP4] CH1 RK0
771 23:38:51.109084 [ModeRegInit_LP4] CH1 RK1
772 23:38:51.109504 match AC timing 13
773 23:38:51.115957 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
774 23:38:51.118908 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
775 23:38:51.122352 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
776 23:38:51.128622 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
777 23:38:51.132319 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
778 23:38:51.132852 [EMI DOE] emi_dcm 0
779 23:38:51.139359 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
780 23:38:51.139890 ==
781 23:38:51.142321 Dram Type= 6, Freq= 0, CH_0, rank 0
782 23:38:51.145881 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
783 23:38:51.146306 ==
784 23:38:51.152417 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
785 23:38:51.155631 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
786 23:38:51.166328 [CA 0] Center 36 (6~67) winsize 62
787 23:38:51.169999 [CA 1] Center 36 (6~67) winsize 62
788 23:38:51.172870 [CA 2] Center 34 (3~65) winsize 63
789 23:38:51.176406 [CA 3] Center 33 (3~64) winsize 62
790 23:38:51.179501 [CA 4] Center 33 (3~64) winsize 62
791 23:38:51.183168 [CA 5] Center 32 (2~62) winsize 61
792 23:38:51.183745
793 23:38:51.186138 [CmdBusTrainingLP45] Vref(ca) range 1: 34
794 23:38:51.186711
795 23:38:51.189522 [CATrainingPosCal] consider 1 rank data
796 23:38:51.192743 u2DelayCellTimex100 = 270/100 ps
797 23:38:51.196195 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
798 23:38:51.199421 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
799 23:38:51.206437 CA2 delay=34 (3~65),Diff = 2 PI (14 cell)
800 23:38:51.209502 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
801 23:38:51.213252 CA4 delay=33 (3~64),Diff = 1 PI (7 cell)
802 23:38:51.216222 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
803 23:38:51.216810
804 23:38:51.219723 CA PerBit enable=1, Macro0, CA PI delay=32
805 23:38:51.220309
806 23:38:51.223047 [CBTSetCACLKResult] CA Dly = 32
807 23:38:51.223637 CS Dly: 5 (0~36)
808 23:38:51.224144 ==
809 23:38:51.226246 Dram Type= 6, Freq= 0, CH_0, rank 1
810 23:38:51.233106 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
811 23:38:51.233781 ==
812 23:38:51.236702 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
813 23:38:51.242853 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
814 23:38:51.252420 [CA 0] Center 36 (6~67) winsize 62
815 23:38:51.255636 [CA 1] Center 36 (6~67) winsize 62
816 23:38:51.258860 [CA 2] Center 34 (4~65) winsize 62
817 23:38:51.262914 [CA 3] Center 33 (3~64) winsize 62
818 23:38:51.265760 [CA 4] Center 32 (2~63) winsize 62
819 23:38:51.269429 [CA 5] Center 32 (2~63) winsize 62
820 23:38:51.270090
821 23:38:51.272596 [CmdBusTrainingLP45] Vref(ca) range 1: 32
822 23:38:51.273182
823 23:38:51.275563 [CATrainingPosCal] consider 2 rank data
824 23:38:51.279455 u2DelayCellTimex100 = 270/100 ps
825 23:38:51.282589 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
826 23:38:51.286348 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
827 23:38:51.292326 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
828 23:38:51.296177 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
829 23:38:51.299074 CA4 delay=33 (3~63),Diff = 1 PI (7 cell)
830 23:38:51.302454 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
831 23:38:51.302933
832 23:38:51.306015 CA PerBit enable=1, Macro0, CA PI delay=32
833 23:38:51.306492
834 23:38:51.308977 [CBTSetCACLKResult] CA Dly = 32
835 23:38:51.309453 CS Dly: 5 (0~37)
836 23:38:51.309886
837 23:38:51.312720 ----->DramcWriteLeveling(PI) begin...
838 23:38:51.313320 ==
839 23:38:51.316411 Dram Type= 6, Freq= 0, CH_0, rank 0
840 23:38:51.320185 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
841 23:38:51.324156 ==
842 23:38:51.324636 Write leveling (Byte 0): 34 => 34
843 23:38:51.327460 Write leveling (Byte 1): 30 => 30
844 23:38:51.331011 DramcWriteLeveling(PI) end<-----
845 23:38:51.331551
846 23:38:51.331927 ==
847 23:38:51.333690 Dram Type= 6, Freq= 0, CH_0, rank 0
848 23:38:51.337253 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
849 23:38:51.337777 ==
850 23:38:51.340839 [Gating] SW mode calibration
851 23:38:51.348135 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
852 23:38:51.354738 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
853 23:38:51.358083 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
854 23:38:51.361550 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
855 23:38:51.368922 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
856 23:38:51.371723 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 23:38:51.375216 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 23:38:51.379097 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 23:38:51.385524 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 23:38:51.388470 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 23:38:51.392113 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 23:38:51.398659 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 23:38:51.401719 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 23:38:51.405681 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 23:38:51.412430 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 23:38:51.415668 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 23:38:51.418968 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 23:38:51.425494 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 23:38:51.428928 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 23:38:51.432142 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
871 23:38:51.438467 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
872 23:38:51.441912 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 23:38:51.445707 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 23:38:51.452020 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 23:38:51.455795 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 23:38:51.458686 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 23:38:51.461809 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 23:38:51.468812 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
879 23:38:51.472372 0 9 8 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
880 23:38:51.475347 0 9 12 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
881 23:38:51.482040 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 23:38:51.485122 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 23:38:51.488841 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
884 23:38:51.495699 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
885 23:38:51.498843 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
886 23:38:51.502409 0 10 4 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
887 23:38:51.508578 0 10 8 | B1->B0 | 3131 2727 | 1 0 | (1 1) (1 0)
888 23:38:51.512504 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
889 23:38:51.515474 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 23:38:51.522067 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 23:38:51.525545 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
892 23:38:51.528787 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
893 23:38:51.535336 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
894 23:38:51.539329 0 11 4 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
895 23:38:51.542351 0 11 8 | B1->B0 | 2828 4545 | 0 0 | (1 1) (0 0)
896 23:38:51.549100 0 11 12 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
897 23:38:51.551898 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 23:38:51.555290 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 23:38:51.562081 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
900 23:38:51.565073 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
901 23:38:51.568870 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
902 23:38:51.571956 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
903 23:38:51.578890 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
904 23:38:51.582028 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
905 23:38:51.585214 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 23:38:51.591909 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 23:38:51.595418 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 23:38:51.598987 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 23:38:51.605326 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 23:38:51.608669 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 23:38:51.611613 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 23:38:51.618245 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 23:38:51.622124 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 23:38:51.625352 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 23:38:51.632370 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
916 23:38:51.635456 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
917 23:38:51.638539 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
918 23:38:51.645400 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
919 23:38:51.648766 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
920 23:38:51.651886 Total UI for P1: 0, mck2ui 16
921 23:38:51.655661 best dqsien dly found for B0: ( 0, 14, 4)
922 23:38:51.658996 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
923 23:38:51.662105 Total UI for P1: 0, mck2ui 16
924 23:38:51.666143 best dqsien dly found for B1: ( 0, 14, 8)
925 23:38:51.669107 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
926 23:38:51.672325 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
927 23:38:51.672792
928 23:38:51.676384 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
929 23:38:51.679380 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
930 23:38:51.682573 [Gating] SW calibration Done
931 23:38:51.683151 ==
932 23:38:51.686380 Dram Type= 6, Freq= 0, CH_0, rank 0
933 23:38:51.689709 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 23:38:51.690291 ==
935 23:38:51.692691 RX Vref Scan: 0
936 23:38:51.693159
937 23:38:51.696336 RX Vref 0 -> 0, step: 1
938 23:38:51.696904
939 23:38:51.697278 RX Delay -130 -> 252, step: 16
940 23:38:51.702573 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
941 23:38:51.705931 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
942 23:38:51.709343 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
943 23:38:51.712467 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
944 23:38:51.716036 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
945 23:38:51.722902 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
946 23:38:51.725791 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
947 23:38:51.729111 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
948 23:38:51.732664 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
949 23:38:51.735662 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
950 23:38:51.742893 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
951 23:38:51.746198 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
952 23:38:51.749361 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
953 23:38:51.752660 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
954 23:38:51.759250 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
955 23:38:51.762666 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
956 23:38:51.763155 ==
957 23:38:51.765784 Dram Type= 6, Freq= 0, CH_0, rank 0
958 23:38:51.769299 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
959 23:38:51.769934 ==
960 23:38:51.770338 DQS Delay:
961 23:38:51.772658 DQS0 = 0, DQS1 = 0
962 23:38:51.773124 DQM Delay:
963 23:38:51.775922 DQM0 = 89, DQM1 = 80
964 23:38:51.776492 DQ Delay:
965 23:38:51.779609 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
966 23:38:51.782607 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =101
967 23:38:51.786271 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =77
968 23:38:51.789014 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85
969 23:38:51.789484
970 23:38:51.789971
971 23:38:51.790325 ==
972 23:38:51.792991 Dram Type= 6, Freq= 0, CH_0, rank 0
973 23:38:51.796472 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
974 23:38:51.797052 ==
975 23:38:51.799180
976 23:38:51.799642
977 23:38:51.800008 TX Vref Scan disable
978 23:38:51.803280 == TX Byte 0 ==
979 23:38:51.806086 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
980 23:38:51.809244 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
981 23:38:51.812510 == TX Byte 1 ==
982 23:38:51.816676 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
983 23:38:51.819792 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
984 23:38:51.820385 ==
985 23:38:51.822605 Dram Type= 6, Freq= 0, CH_0, rank 0
986 23:38:51.829099 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
987 23:38:51.829619 ==
988 23:38:51.841436 TX Vref=22, minBit 8, minWin=27, winSum=447
989 23:38:51.845024 TX Vref=24, minBit 8, minWin=27, winSum=448
990 23:38:51.848441 TX Vref=26, minBit 0, minWin=28, winSum=453
991 23:38:51.851360 TX Vref=28, minBit 8, minWin=27, winSum=455
992 23:38:51.855049 TX Vref=30, minBit 8, minWin=28, winSum=458
993 23:38:51.858321 TX Vref=32, minBit 4, minWin=28, winSum=454
994 23:38:51.865155 [TxChooseVref] Worse bit 8, Min win 28, Win sum 458, Final Vref 30
995 23:38:51.865782
996 23:38:51.868128 Final TX Range 1 Vref 30
997 23:38:51.868596
998 23:38:51.868961 ==
999 23:38:51.872013 Dram Type= 6, Freq= 0, CH_0, rank 0
1000 23:38:51.874966 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1001 23:38:51.875437 ==
1002 23:38:51.875807
1003 23:38:51.878527
1004 23:38:51.879040 TX Vref Scan disable
1005 23:38:51.881560 == TX Byte 0 ==
1006 23:38:51.885118 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
1007 23:38:51.888855 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
1008 23:38:51.891805 == TX Byte 1 ==
1009 23:38:51.894700 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1010 23:38:51.898581 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1011 23:38:51.901705
1012 23:38:51.902185 [DATLAT]
1013 23:38:51.902565 Freq=800, CH0 RK0
1014 23:38:51.902921
1015 23:38:51.905640 DATLAT Default: 0xa
1016 23:38:51.906213 0, 0xFFFF, sum = 0
1017 23:38:51.908326 1, 0xFFFF, sum = 0
1018 23:38:51.908842 2, 0xFFFF, sum = 0
1019 23:38:51.911916 3, 0xFFFF, sum = 0
1020 23:38:51.912496 4, 0xFFFF, sum = 0
1021 23:38:51.915683 5, 0xFFFF, sum = 0
1022 23:38:51.916261 6, 0xFFFF, sum = 0
1023 23:38:51.918489 7, 0xFFFF, sum = 0
1024 23:38:51.918974 8, 0xFFFF, sum = 0
1025 23:38:51.921945 9, 0x0, sum = 1
1026 23:38:51.922421 10, 0x0, sum = 2
1027 23:38:51.925432 11, 0x0, sum = 3
1028 23:38:51.926073 12, 0x0, sum = 4
1029 23:38:51.928551 best_step = 10
1030 23:38:51.929111
1031 23:38:51.929483 ==
1032 23:38:51.931893 Dram Type= 6, Freq= 0, CH_0, rank 0
1033 23:38:51.934873 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1034 23:38:51.935351 ==
1035 23:38:51.938464 RX Vref Scan: 1
1036 23:38:51.938933
1037 23:38:51.939307 Set Vref Range= 32 -> 127
1038 23:38:51.939656
1039 23:38:51.942210 RX Vref 32 -> 127, step: 1
1040 23:38:51.942769
1041 23:38:51.945501 RX Delay -95 -> 252, step: 8
1042 23:38:51.946106
1043 23:38:51.948896 Set Vref, RX VrefLevel [Byte0]: 32
1044 23:38:51.951730 [Byte1]: 32
1045 23:38:51.952200
1046 23:38:51.955152 Set Vref, RX VrefLevel [Byte0]: 33
1047 23:38:51.958350 [Byte1]: 33
1048 23:38:51.962408
1049 23:38:51.962973 Set Vref, RX VrefLevel [Byte0]: 34
1050 23:38:51.965640 [Byte1]: 34
1051 23:38:51.969996
1052 23:38:51.970561 Set Vref, RX VrefLevel [Byte0]: 35
1053 23:38:51.972759 [Byte1]: 35
1054 23:38:51.977524
1055 23:38:51.978172 Set Vref, RX VrefLevel [Byte0]: 36
1056 23:38:51.980745 [Byte1]: 36
1057 23:38:51.985139
1058 23:38:51.985754 Set Vref, RX VrefLevel [Byte0]: 37
1059 23:38:51.988422 [Byte1]: 37
1060 23:38:51.992627
1061 23:38:51.993095 Set Vref, RX VrefLevel [Byte0]: 38
1062 23:38:51.996292 [Byte1]: 38
1063 23:38:52.000009
1064 23:38:52.000490 Set Vref, RX VrefLevel [Byte0]: 39
1065 23:38:52.004212 [Byte1]: 39
1066 23:38:52.008430
1067 23:38:52.009007 Set Vref, RX VrefLevel [Byte0]: 40
1068 23:38:52.011453 [Byte1]: 40
1069 23:38:52.015235
1070 23:38:52.015803 Set Vref, RX VrefLevel [Byte0]: 41
1071 23:38:52.018486 [Byte1]: 41
1072 23:38:52.023122
1073 23:38:52.023691 Set Vref, RX VrefLevel [Byte0]: 42
1074 23:38:52.026346 [Byte1]: 42
1075 23:38:52.030234
1076 23:38:52.030700 Set Vref, RX VrefLevel [Byte0]: 43
1077 23:38:52.034399 [Byte1]: 43
1078 23:38:52.037604
1079 23:38:52.041450 Set Vref, RX VrefLevel [Byte0]: 44
1080 23:38:52.044626 [Byte1]: 44
1081 23:38:52.045186
1082 23:38:52.048455 Set Vref, RX VrefLevel [Byte0]: 45
1083 23:38:52.050982 [Byte1]: 45
1084 23:38:52.051454
1085 23:38:52.054640 Set Vref, RX VrefLevel [Byte0]: 46
1086 23:38:52.057709 [Byte1]: 46
1087 23:38:52.058274
1088 23:38:52.061437 Set Vref, RX VrefLevel [Byte0]: 47
1089 23:38:52.064640 [Byte1]: 47
1090 23:38:52.068303
1091 23:38:52.068772 Set Vref, RX VrefLevel [Byte0]: 48
1092 23:38:52.071281 [Byte1]: 48
1093 23:38:52.075968
1094 23:38:52.076535 Set Vref, RX VrefLevel [Byte0]: 49
1095 23:38:52.079518 [Byte1]: 49
1096 23:38:52.084046
1097 23:38:52.084609 Set Vref, RX VrefLevel [Byte0]: 50
1098 23:38:52.086680 [Byte1]: 50
1099 23:38:52.091258
1100 23:38:52.091815 Set Vref, RX VrefLevel [Byte0]: 51
1101 23:38:52.094653 [Byte1]: 51
1102 23:38:52.099100
1103 23:38:52.099667 Set Vref, RX VrefLevel [Byte0]: 52
1104 23:38:52.102207 [Byte1]: 52
1105 23:38:52.106390
1106 23:38:52.107181 Set Vref, RX VrefLevel [Byte0]: 53
1107 23:38:52.109443 [Byte1]: 53
1108 23:38:52.113625
1109 23:38:52.114199 Set Vref, RX VrefLevel [Byte0]: 54
1110 23:38:52.116973 [Byte1]: 54
1111 23:38:52.121371
1112 23:38:52.121894 Set Vref, RX VrefLevel [Byte0]: 55
1113 23:38:52.124531 [Byte1]: 55
1114 23:38:52.128768
1115 23:38:52.129431 Set Vref, RX VrefLevel [Byte0]: 56
1116 23:38:52.132405 [Byte1]: 56
1117 23:38:52.136395
1118 23:38:52.136935 Set Vref, RX VrefLevel [Byte0]: 57
1119 23:38:52.139952 [Byte1]: 57
1120 23:38:52.143852
1121 23:38:52.144363 Set Vref, RX VrefLevel [Byte0]: 58
1122 23:38:52.147678 [Byte1]: 58
1123 23:38:52.151797
1124 23:38:52.152296 Set Vref, RX VrefLevel [Byte0]: 59
1125 23:38:52.155025 [Byte1]: 59
1126 23:38:52.159307
1127 23:38:52.159722 Set Vref, RX VrefLevel [Byte0]: 60
1128 23:38:52.162829 [Byte1]: 60
1129 23:38:52.167351
1130 23:38:52.167942 Set Vref, RX VrefLevel [Byte0]: 61
1131 23:38:52.170711 [Byte1]: 61
1132 23:38:52.175111
1133 23:38:52.175721 Set Vref, RX VrefLevel [Byte0]: 62
1134 23:38:52.177939 [Byte1]: 62
1135 23:38:52.182297
1136 23:38:52.182826 Set Vref, RX VrefLevel [Byte0]: 63
1137 23:38:52.185371 [Byte1]: 63
1138 23:38:52.189866
1139 23:38:52.190403 Set Vref, RX VrefLevel [Byte0]: 64
1140 23:38:52.192994 [Byte1]: 64
1141 23:38:52.198214
1142 23:38:52.198735 Set Vref, RX VrefLevel [Byte0]: 65
1143 23:38:52.200605 [Byte1]: 65
1144 23:38:52.205211
1145 23:38:52.205766 Set Vref, RX VrefLevel [Byte0]: 66
1146 23:38:52.208777 [Byte1]: 66
1147 23:38:52.213202
1148 23:38:52.213758 Set Vref, RX VrefLevel [Byte0]: 67
1149 23:38:52.216356 [Byte1]: 67
1150 23:38:52.220335
1151 23:38:52.220866 Set Vref, RX VrefLevel [Byte0]: 68
1152 23:38:52.223789 [Byte1]: 68
1153 23:38:52.227845
1154 23:38:52.228369 Set Vref, RX VrefLevel [Byte0]: 69
1155 23:38:52.231049 [Byte1]: 69
1156 23:38:52.235562
1157 23:38:52.239212 Set Vref, RX VrefLevel [Byte0]: 70
1158 23:38:52.239630 [Byte1]: 70
1159 23:38:52.243471
1160 23:38:52.243886 Set Vref, RX VrefLevel [Byte0]: 71
1161 23:38:52.246492 [Byte1]: 71
1162 23:38:52.250703
1163 23:38:52.251224 Set Vref, RX VrefLevel [Byte0]: 72
1164 23:38:52.253685 [Byte1]: 72
1165 23:38:52.258239
1166 23:38:52.258756 Set Vref, RX VrefLevel [Byte0]: 73
1167 23:38:52.261241 [Byte1]: 73
1168 23:38:52.266104
1169 23:38:52.266649 Set Vref, RX VrefLevel [Byte0]: 74
1170 23:38:52.269259 [Byte1]: 74
1171 23:38:52.273509
1172 23:38:52.274090 Set Vref, RX VrefLevel [Byte0]: 75
1173 23:38:52.277054 [Byte1]: 75
1174 23:38:52.281041
1175 23:38:52.281553 Set Vref, RX VrefLevel [Byte0]: 76
1176 23:38:52.284305 [Byte1]: 76
1177 23:38:52.288589
1178 23:38:52.289003 Set Vref, RX VrefLevel [Byte0]: 77
1179 23:38:52.292100 [Byte1]: 77
1180 23:38:52.296099
1181 23:38:52.296517 Set Vref, RX VrefLevel [Byte0]: 78
1182 23:38:52.299616 [Byte1]: 78
1183 23:38:52.304092
1184 23:38:52.304613 Set Vref, RX VrefLevel [Byte0]: 79
1185 23:38:52.306956 [Byte1]: 79
1186 23:38:52.311399
1187 23:38:52.312025 Final RX Vref Byte 0 = 54 to rank0
1188 23:38:52.315016 Final RX Vref Byte 1 = 62 to rank0
1189 23:38:52.318228 Final RX Vref Byte 0 = 54 to rank1
1190 23:38:52.321945 Final RX Vref Byte 1 = 62 to rank1==
1191 23:38:52.325243 Dram Type= 6, Freq= 0, CH_0, rank 0
1192 23:38:52.331237 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1193 23:38:52.331678 ==
1194 23:38:52.332013 DQS Delay:
1195 23:38:52.332322 DQS0 = 0, DQS1 = 0
1196 23:38:52.334421 DQM Delay:
1197 23:38:52.334834 DQM0 = 91, DQM1 = 85
1198 23:38:52.337871 DQ Delay:
1199 23:38:52.341254 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88
1200 23:38:52.344834 DQ4 =92, DQ5 =80, DQ6 =100, DQ7 =100
1201 23:38:52.348289 DQ8 =76, DQ9 =76, DQ10 =88, DQ11 =76
1202 23:38:52.351138 DQ12 =92, DQ13 =92, DQ14 =92, DQ15 =92
1203 23:38:52.351557
1204 23:38:52.351890
1205 23:38:52.357981 [DQSOSCAuto] RK0, (LSB)MR18= 0x4d44, (MSB)MR19= 0x606, tDQSOscB0 = 392 ps tDQSOscB1 = 390 ps
1206 23:38:52.361674 CH0 RK0: MR19=606, MR18=4D44
1207 23:38:52.367824 CH0_RK0: MR19=0x606, MR18=0x4D44, DQSOSC=390, MR23=63, INC=97, DEC=64
1208 23:38:52.368319
1209 23:38:52.371510 ----->DramcWriteLeveling(PI) begin...
1210 23:38:52.372090 ==
1211 23:38:52.374374 Dram Type= 6, Freq= 0, CH_0, rank 1
1212 23:38:52.377906 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1213 23:38:52.378328 ==
1214 23:38:52.381567 Write leveling (Byte 0): 32 => 32
1215 23:38:52.384712 Write leveling (Byte 1): 32 => 32
1216 23:38:52.388346 DramcWriteLeveling(PI) end<-----
1217 23:38:52.388872
1218 23:38:52.389212 ==
1219 23:38:52.429011 Dram Type= 6, Freq= 0, CH_0, rank 1
1220 23:38:52.430285 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1221 23:38:52.430731 ==
1222 23:38:52.431098 [Gating] SW mode calibration
1223 23:38:52.431450 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1224 23:38:52.431786 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1225 23:38:52.432111 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1226 23:38:52.432505 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1227 23:38:52.432842 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1228 23:38:52.433158 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 23:38:52.433666 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 23:38:52.437067 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 23:38:52.440357 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 23:38:52.446938 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 23:38:52.450519 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 23:38:52.454161 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 23:38:52.460610 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 23:38:52.463645 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 23:38:52.467259 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 23:38:52.470373 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 23:38:52.477176 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1240 23:38:52.480932 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1241 23:38:52.483875 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 23:38:52.490684 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1243 23:38:52.493853 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1244 23:38:52.497052 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1245 23:38:52.503633 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1246 23:38:52.506847 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1247 23:38:52.510523 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1248 23:38:52.517687 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1249 23:38:52.520779 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1250 23:38:52.524131 0 9 4 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
1251 23:38:52.530415 0 9 8 | B1->B0 | 2d2d 2e2e | 1 1 | (1 1) (1 1)
1252 23:38:52.533923 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1253 23:38:52.537512 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1254 23:38:52.544240 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1255 23:38:52.547484 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1256 23:38:52.550826 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1257 23:38:52.557553 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1258 23:38:52.560643 0 10 4 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
1259 23:38:52.564285 0 10 8 | B1->B0 | 2828 2c2c | 1 0 | (1 1) (0 0)
1260 23:38:52.568170 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1261 23:38:52.572047 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1262 23:38:52.579083 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1263 23:38:52.582079 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1264 23:38:52.585984 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1265 23:38:52.589237 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1266 23:38:52.595912 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1267 23:38:52.599829 0 11 8 | B1->B0 | 4444 3e3e | 0 0 | (0 0) (0 0)
1268 23:38:52.602379 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1269 23:38:52.609316 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1270 23:38:52.612256 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1271 23:38:52.616300 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1272 23:38:52.623202 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1273 23:38:52.625927 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1274 23:38:52.629190 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1275 23:38:52.635993 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1276 23:38:52.639630 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1277 23:38:52.642684 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1278 23:38:52.649739 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1279 23:38:52.652978 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1280 23:38:52.656149 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1281 23:38:52.659817 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1282 23:38:52.666198 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1283 23:38:52.669737 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1284 23:38:52.672818 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1285 23:38:52.679531 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1286 23:38:52.683182 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1287 23:38:52.686732 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1288 23:38:52.692854 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1289 23:38:52.696358 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1290 23:38:52.700241 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1291 23:38:52.706115 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1292 23:38:52.709770 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1293 23:38:52.713086 Total UI for P1: 0, mck2ui 16
1294 23:38:52.716609 best dqsien dly found for B0: ( 0, 14, 8)
1295 23:38:52.720200 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1296 23:38:52.723544 Total UI for P1: 0, mck2ui 16
1297 23:38:52.726364 best dqsien dly found for B1: ( 0, 14, 10)
1298 23:38:52.729774 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1299 23:38:52.733296 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1300 23:38:52.733912
1301 23:38:52.736454 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1302 23:38:52.743049 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1303 23:38:52.743625 [Gating] SW calibration Done
1304 23:38:52.744006 ==
1305 23:38:52.746197 Dram Type= 6, Freq= 0, CH_0, rank 1
1306 23:38:52.753370 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1307 23:38:52.753961 ==
1308 23:38:52.754332 RX Vref Scan: 0
1309 23:38:52.754680
1310 23:38:52.757403 RX Vref 0 -> 0, step: 1
1311 23:38:52.757967
1312 23:38:52.760170 RX Delay -130 -> 252, step: 16
1313 23:38:52.763577 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1314 23:38:52.767496 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1315 23:38:52.770079 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
1316 23:38:52.773078 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1317 23:38:52.780067 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1318 23:38:52.783437 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1319 23:38:52.786641 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1320 23:38:52.789800 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1321 23:38:52.793725 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1322 23:38:52.800249 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1323 23:38:52.803461 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1324 23:38:52.806736 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1325 23:38:52.810107 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1326 23:38:52.814246 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1327 23:38:52.820550 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1328 23:38:52.823932 iDelay=222, Bit 15, Center 85 (-18 ~ 189) 208
1329 23:38:52.824495 ==
1330 23:38:52.827041 Dram Type= 6, Freq= 0, CH_0, rank 1
1331 23:38:52.830051 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1332 23:38:52.830519 ==
1333 23:38:52.833484 DQS Delay:
1334 23:38:52.833998 DQS0 = 0, DQS1 = 0
1335 23:38:52.834459 DQM Delay:
1336 23:38:52.836779 DQM0 = 93, DQM1 = 82
1337 23:38:52.837235 DQ Delay:
1338 23:38:52.840075 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =93
1339 23:38:52.843773 DQ4 =93, DQ5 =85, DQ6 =93, DQ7 =101
1340 23:38:52.847061 DQ8 =77, DQ9 =69, DQ10 =77, DQ11 =77
1341 23:38:52.850960 DQ12 =85, DQ13 =93, DQ14 =93, DQ15 =85
1342 23:38:52.851526
1343 23:38:52.851892
1344 23:38:52.852231 ==
1345 23:38:52.853688 Dram Type= 6, Freq= 0, CH_0, rank 1
1346 23:38:52.860576 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1347 23:38:52.861157 ==
1348 23:38:52.861529
1349 23:38:52.861918
1350 23:38:52.862246 TX Vref Scan disable
1351 23:38:52.863363 == TX Byte 0 ==
1352 23:38:52.867035 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1353 23:38:52.870445 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1354 23:38:52.873627 == TX Byte 1 ==
1355 23:38:52.876683 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1356 23:38:52.880796 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1357 23:38:52.883590 ==
1358 23:38:52.886825 Dram Type= 6, Freq= 0, CH_0, rank 1
1359 23:38:52.890013 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1360 23:38:52.890477 ==
1361 23:38:52.902353 TX Vref=22, minBit 9, minWin=27, winSum=447
1362 23:38:52.906106 TX Vref=24, minBit 8, minWin=27, winSum=450
1363 23:38:52.909156 TX Vref=26, minBit 5, minWin=28, winSum=455
1364 23:38:52.912423 TX Vref=28, minBit 4, minWin=28, winSum=456
1365 23:38:52.916019 TX Vref=30, minBit 8, minWin=28, winSum=458
1366 23:38:52.919201 TX Vref=32, minBit 10, minWin=27, winSum=454
1367 23:38:52.925797 [TxChooseVref] Worse bit 8, Min win 28, Win sum 458, Final Vref 30
1368 23:38:52.926124
1369 23:38:52.929514 Final TX Range 1 Vref 30
1370 23:38:52.929862
1371 23:38:52.930056 ==
1372 23:38:52.932678 Dram Type= 6, Freq= 0, CH_0, rank 1
1373 23:38:52.935770 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1374 23:38:52.936017 ==
1375 23:38:52.936198
1376 23:38:52.939060
1377 23:38:52.939286 TX Vref Scan disable
1378 23:38:52.942209 == TX Byte 0 ==
1379 23:38:52.945393 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1380 23:38:52.948886 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1381 23:38:52.952706 == TX Byte 1 ==
1382 23:38:52.955783 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1383 23:38:52.959091 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1384 23:38:52.959527
1385 23:38:52.963281 [DATLAT]
1386 23:38:52.963838 Freq=800, CH0 RK1
1387 23:38:52.964208
1388 23:38:52.966506 DATLAT Default: 0xa
1389 23:38:52.966968 0, 0xFFFF, sum = 0
1390 23:38:52.969749 1, 0xFFFF, sum = 0
1391 23:38:52.970315 2, 0xFFFF, sum = 0
1392 23:38:52.972980 3, 0xFFFF, sum = 0
1393 23:38:52.973543 4, 0xFFFF, sum = 0
1394 23:38:52.976182 5, 0xFFFF, sum = 0
1395 23:38:52.976742 6, 0xFFFF, sum = 0
1396 23:38:52.979350 7, 0xFFFF, sum = 0
1397 23:38:52.979821 8, 0xFFFF, sum = 0
1398 23:38:52.983035 9, 0x0, sum = 1
1399 23:38:52.983606 10, 0x0, sum = 2
1400 23:38:52.985995 11, 0x0, sum = 3
1401 23:38:52.986462 12, 0x0, sum = 4
1402 23:38:52.990031 best_step = 10
1403 23:38:52.990610
1404 23:38:52.990985 ==
1405 23:38:52.992457 Dram Type= 6, Freq= 0, CH_0, rank 1
1406 23:38:52.996244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1407 23:38:52.996709 ==
1408 23:38:52.999326 RX Vref Scan: 0
1409 23:38:52.999887
1410 23:38:53.000260 RX Vref 0 -> 0, step: 1
1411 23:38:53.000605
1412 23:38:53.003050 RX Delay -95 -> 252, step: 8
1413 23:38:53.009286 iDelay=209, Bit 0, Center 92 (-15 ~ 200) 216
1414 23:38:53.012992 iDelay=209, Bit 1, Center 96 (-7 ~ 200) 208
1415 23:38:53.015872 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1416 23:38:53.019800 iDelay=209, Bit 3, Center 88 (-23 ~ 200) 224
1417 23:38:53.022463 iDelay=209, Bit 4, Center 96 (-15 ~ 208) 224
1418 23:38:53.029633 iDelay=209, Bit 5, Center 84 (-23 ~ 192) 216
1419 23:38:53.032455 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1420 23:38:53.036541 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1421 23:38:53.039531 iDelay=209, Bit 8, Center 76 (-31 ~ 184) 216
1422 23:38:53.043019 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1423 23:38:53.046333 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1424 23:38:53.053005 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1425 23:38:53.056297 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
1426 23:38:53.059700 iDelay=209, Bit 13, Center 88 (-15 ~ 192) 208
1427 23:38:53.063125 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1428 23:38:53.066089 iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216
1429 23:38:53.070171 ==
1430 23:38:53.073399 Dram Type= 6, Freq= 0, CH_0, rank 1
1431 23:38:53.076384 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1432 23:38:53.076950 ==
1433 23:38:53.077321 DQS Delay:
1434 23:38:53.080233 DQS0 = 0, DQS1 = 0
1435 23:38:53.080790 DQM Delay:
1436 23:38:53.083057 DQM0 = 93, DQM1 = 84
1437 23:38:53.083617 DQ Delay:
1438 23:38:53.086632 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1439 23:38:53.089900 DQ4 =96, DQ5 =84, DQ6 =100, DQ7 =100
1440 23:38:53.093789 DQ8 =76, DQ9 =72, DQ10 =84, DQ11 =76
1441 23:38:53.096276 DQ12 =92, DQ13 =88, DQ14 =92, DQ15 =92
1442 23:38:53.096741
1443 23:38:53.097112
1444 23:38:53.103529 [DQSOSCAuto] RK1, (LSB)MR18= 0x4112, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 393 ps
1445 23:38:53.106837 CH0 RK1: MR19=606, MR18=4112
1446 23:38:53.113245 CH0_RK1: MR19=0x606, MR18=0x4112, DQSOSC=393, MR23=63, INC=95, DEC=63
1447 23:38:53.116403 [RxdqsGatingPostProcess] freq 800
1448 23:38:53.119524 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1449 23:38:53.123432 Pre-setting of DQS Precalculation
1450 23:38:53.130345 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1451 23:38:53.130900 ==
1452 23:38:53.133396 Dram Type= 6, Freq= 0, CH_1, rank 0
1453 23:38:53.136720 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1454 23:38:53.137286 ==
1455 23:38:53.142576 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1456 23:38:53.149547 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1457 23:38:53.157121 [CA 0] Center 36 (6~67) winsize 62
1458 23:38:53.160796 [CA 1] Center 36 (6~67) winsize 62
1459 23:38:53.164093 [CA 2] Center 35 (4~66) winsize 63
1460 23:38:53.167383 [CA 3] Center 34 (4~65) winsize 62
1461 23:38:53.170860 [CA 4] Center 34 (4~65) winsize 62
1462 23:38:53.173792 [CA 5] Center 34 (4~65) winsize 62
1463 23:38:53.174156
1464 23:38:53.177687 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1465 23:38:53.178208
1466 23:38:53.180830 [CATrainingPosCal] consider 1 rank data
1467 23:38:53.183860 u2DelayCellTimex100 = 270/100 ps
1468 23:38:53.187780 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1469 23:38:53.191003 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1470 23:38:53.197895 CA2 delay=35 (4~66),Diff = 1 PI (7 cell)
1471 23:38:53.201088 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1472 23:38:53.204112 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1473 23:38:53.207788 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1474 23:38:53.208210
1475 23:38:53.211118 CA PerBit enable=1, Macro0, CA PI delay=34
1476 23:38:53.211540
1477 23:38:53.214434 [CBTSetCACLKResult] CA Dly = 34
1478 23:38:53.214915 CS Dly: 5 (0~36)
1479 23:38:53.215414 ==
1480 23:38:53.217607 Dram Type= 6, Freq= 0, CH_1, rank 1
1481 23:38:53.224958 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1482 23:38:53.225497 ==
1483 23:38:53.229134 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1484 23:38:53.235560 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1485 23:38:53.244076 [CA 0] Center 36 (6~67) winsize 62
1486 23:38:53.247719 [CA 1] Center 37 (6~68) winsize 63
1487 23:38:53.251662 [CA 2] Center 35 (5~66) winsize 62
1488 23:38:53.255941 [CA 3] Center 34 (4~65) winsize 62
1489 23:38:53.256413 [CA 4] Center 35 (5~66) winsize 62
1490 23:38:53.259278 [CA 5] Center 34 (4~65) winsize 62
1491 23:38:53.259744
1492 23:38:53.266216 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1493 23:38:53.266826
1494 23:38:53.269774 [CATrainingPosCal] consider 2 rank data
1495 23:38:53.272678 u2DelayCellTimex100 = 270/100 ps
1496 23:38:53.275857 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1497 23:38:53.279880 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1498 23:38:53.283589 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
1499 23:38:53.286317 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1500 23:38:53.289645 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1501 23:38:53.292851 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1502 23:38:53.293420
1503 23:38:53.296151 CA PerBit enable=1, Macro0, CA PI delay=34
1504 23:38:53.296775
1505 23:38:53.299325 [CBTSetCACLKResult] CA Dly = 34
1506 23:38:53.302609 CS Dly: 6 (0~39)
1507 23:38:53.303069
1508 23:38:53.306195 ----->DramcWriteLeveling(PI) begin...
1509 23:38:53.306772 ==
1510 23:38:53.309123 Dram Type= 6, Freq= 0, CH_1, rank 0
1511 23:38:53.312999 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1512 23:38:53.313562 ==
1513 23:38:53.316090 Write leveling (Byte 0): 30 => 30
1514 23:38:53.319752 Write leveling (Byte 1): 27 => 27
1515 23:38:53.322491 DramcWriteLeveling(PI) end<-----
1516 23:38:53.322980
1517 23:38:53.323350 ==
1518 23:38:53.326080 Dram Type= 6, Freq= 0, CH_1, rank 0
1519 23:38:53.329483 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1520 23:38:53.330150 ==
1521 23:38:53.332763 [Gating] SW mode calibration
1522 23:38:53.339909 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1523 23:38:53.346075 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1524 23:38:53.349834 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1525 23:38:53.352674 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1526 23:38:53.359767 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 23:38:53.362606 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 23:38:53.366392 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 23:38:53.373105 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 23:38:53.376568 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 23:38:53.379485 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 23:38:53.386339 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 23:38:53.389735 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 23:38:53.393074 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 23:38:53.399573 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 23:38:53.403115 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 23:38:53.406336 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 23:38:53.409316 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 23:38:53.416416 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 23:38:53.419385 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1541 23:38:53.423265 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1542 23:38:53.429518 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1543 23:38:53.432978 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1544 23:38:53.436448 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1545 23:38:53.442689 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1546 23:38:53.446347 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1547 23:38:53.450004 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1548 23:38:53.456377 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1549 23:38:53.459536 0 9 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
1550 23:38:53.462572 0 9 8 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
1551 23:38:53.469815 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1552 23:38:53.473022 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1553 23:38:53.476129 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1554 23:38:53.482848 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1555 23:38:53.485670 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1556 23:38:53.489136 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1557 23:38:53.495947 0 10 4 | B1->B0 | 3232 2d2d | 0 1 | (0 1) (1 0)
1558 23:38:53.499150 0 10 8 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
1559 23:38:53.502230 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1560 23:38:53.509631 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1561 23:38:53.512572 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1562 23:38:53.516278 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1563 23:38:53.522522 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1564 23:38:53.525475 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1565 23:38:53.529761 0 11 4 | B1->B0 | 2a2a 3636 | 0 0 | (0 0) (0 0)
1566 23:38:53.532287 0 11 8 | B1->B0 | 4343 4646 | 0 0 | (1 1) (0 0)
1567 23:38:53.539104 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1568 23:38:53.542213 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1569 23:38:53.546069 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1570 23:38:53.552959 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1571 23:38:53.555965 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1572 23:38:53.559884 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1573 23:38:53.565784 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1574 23:38:53.569819 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1575 23:38:53.572293 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1576 23:38:53.579298 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1577 23:38:53.582592 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1578 23:38:53.585931 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1579 23:38:53.592557 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1580 23:38:53.596018 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1581 23:38:53.599181 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1582 23:38:53.606558 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1583 23:38:53.609496 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1584 23:38:53.613349 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1585 23:38:53.616296 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1586 23:38:53.622772 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1587 23:38:53.626194 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1588 23:38:53.629825 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1589 23:38:53.635798 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1590 23:38:53.639226 Total UI for P1: 0, mck2ui 16
1591 23:38:53.642976 best dqsien dly found for B0: ( 0, 14, 2)
1592 23:38:53.643541 Total UI for P1: 0, mck2ui 16
1593 23:38:53.649344 best dqsien dly found for B1: ( 0, 14, 0)
1594 23:38:53.653324 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1595 23:38:53.656288 best DQS1 dly(MCK, UI, PI) = (0, 14, 0)
1596 23:38:53.656756
1597 23:38:53.659602 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1598 23:38:53.662808 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 0)
1599 23:38:53.666280 [Gating] SW calibration Done
1600 23:38:53.666855 ==
1601 23:38:53.669778 Dram Type= 6, Freq= 0, CH_1, rank 0
1602 23:38:53.673056 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1603 23:38:53.673520 ==
1604 23:38:53.676007 RX Vref Scan: 0
1605 23:38:53.676464
1606 23:38:53.676825 RX Vref 0 -> 0, step: 1
1607 23:38:53.677161
1608 23:38:53.679617 RX Delay -130 -> 252, step: 16
1609 23:38:53.682896 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1610 23:38:53.686149 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1611 23:38:53.693524 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1612 23:38:53.696264 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1613 23:38:53.699463 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1614 23:38:53.703184 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1615 23:38:53.706257 iDelay=222, Bit 6, Center 109 (-2 ~ 221) 224
1616 23:38:53.713198 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1617 23:38:53.716509 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1618 23:38:53.719472 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1619 23:38:53.723192 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1620 23:38:53.726421 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1621 23:38:53.733184 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1622 23:38:53.736569 iDelay=222, Bit 13, Center 101 (-2 ~ 205) 208
1623 23:38:53.739515 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1624 23:38:53.743241 iDelay=222, Bit 15, Center 101 (-2 ~ 205) 208
1625 23:38:53.743807 ==
1626 23:38:53.746345 Dram Type= 6, Freq= 0, CH_1, rank 0
1627 23:38:53.752836 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1628 23:38:53.753389 ==
1629 23:38:53.753802 DQS Delay:
1630 23:38:53.754146 DQS0 = 0, DQS1 = 0
1631 23:38:53.756564 DQM Delay:
1632 23:38:53.757018 DQM0 = 94, DQM1 = 89
1633 23:38:53.759773 DQ Delay:
1634 23:38:53.763301 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1635 23:38:53.766624 DQ4 =93, DQ5 =109, DQ6 =109, DQ7 =93
1636 23:38:53.770090 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =85
1637 23:38:53.773337 DQ12 =93, DQ13 =101, DQ14 =93, DQ15 =101
1638 23:38:53.773822
1639 23:38:53.774186
1640 23:38:53.774518 ==
1641 23:38:53.776861 Dram Type= 6, Freq= 0, CH_1, rank 0
1642 23:38:53.779865 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1643 23:38:53.780432 ==
1644 23:38:53.780797
1645 23:38:53.781135
1646 23:38:53.783556 TX Vref Scan disable
1647 23:38:53.784119 == TX Byte 0 ==
1648 23:38:53.789550 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1649 23:38:53.793144 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1650 23:38:53.793744 == TX Byte 1 ==
1651 23:38:53.799840 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1652 23:38:53.804451 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1653 23:38:53.805019 ==
1654 23:38:53.807139 Dram Type= 6, Freq= 0, CH_1, rank 0
1655 23:38:53.810307 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1656 23:38:53.810831 ==
1657 23:38:53.824196 TX Vref=22, minBit 4, minWin=26, winSum=437
1658 23:38:53.827783 TX Vref=24, minBit 0, minWin=26, winSum=442
1659 23:38:53.830799 TX Vref=26, minBit 1, minWin=27, winSum=446
1660 23:38:53.834258 TX Vref=28, minBit 1, minWin=27, winSum=450
1661 23:38:53.837455 TX Vref=30, minBit 0, minWin=27, winSum=451
1662 23:38:53.844130 TX Vref=32, minBit 5, minWin=27, winSum=451
1663 23:38:53.847711 [TxChooseVref] Worse bit 0, Min win 27, Win sum 451, Final Vref 30
1664 23:38:53.848270
1665 23:38:53.850961 Final TX Range 1 Vref 30
1666 23:38:53.851520
1667 23:38:53.851891 ==
1668 23:38:53.853904 Dram Type= 6, Freq= 0, CH_1, rank 0
1669 23:38:53.857267 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1670 23:38:53.857772 ==
1671 23:38:53.860756
1672 23:38:53.861321
1673 23:38:53.861733 TX Vref Scan disable
1674 23:38:53.864081 == TX Byte 0 ==
1675 23:38:53.867383 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1676 23:38:53.870792 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1677 23:38:53.874616 == TX Byte 1 ==
1678 23:38:53.877716 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1679 23:38:53.881228 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1680 23:38:53.884475
1681 23:38:53.885029 [DATLAT]
1682 23:38:53.885397 Freq=800, CH1 RK0
1683 23:38:53.885788
1684 23:38:53.887542 DATLAT Default: 0xa
1685 23:38:53.888006 0, 0xFFFF, sum = 0
1686 23:38:53.891181 1, 0xFFFF, sum = 0
1687 23:38:53.891652 2, 0xFFFF, sum = 0
1688 23:38:53.894070 3, 0xFFFF, sum = 0
1689 23:38:53.894542 4, 0xFFFF, sum = 0
1690 23:38:53.897519 5, 0xFFFF, sum = 0
1691 23:38:53.898118 6, 0xFFFF, sum = 0
1692 23:38:53.900886 7, 0xFFFF, sum = 0
1693 23:38:53.904412 8, 0xFFFF, sum = 0
1694 23:38:53.904983 9, 0x0, sum = 1
1695 23:38:53.905360 10, 0x0, sum = 2
1696 23:38:53.907901 11, 0x0, sum = 3
1697 23:38:53.908468 12, 0x0, sum = 4
1698 23:38:53.910836 best_step = 10
1699 23:38:53.911349
1700 23:38:53.911722 ==
1701 23:38:53.914151 Dram Type= 6, Freq= 0, CH_1, rank 0
1702 23:38:53.917653 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1703 23:38:53.918223 ==
1704 23:38:53.920604 RX Vref Scan: 1
1705 23:38:53.921070
1706 23:38:53.921440 Set Vref Range= 32 -> 127
1707 23:38:53.921827
1708 23:38:53.923890 RX Vref 32 -> 127, step: 1
1709 23:38:53.924354
1710 23:38:53.927827 RX Delay -79 -> 252, step: 8
1711 23:38:53.928389
1712 23:38:53.931309 Set Vref, RX VrefLevel [Byte0]: 32
1713 23:38:53.934549 [Byte1]: 32
1714 23:38:53.935118
1715 23:38:53.937203 Set Vref, RX VrefLevel [Byte0]: 33
1716 23:38:53.940662 [Byte1]: 33
1717 23:38:53.944860
1718 23:38:53.945431 Set Vref, RX VrefLevel [Byte0]: 34
1719 23:38:53.947917 [Byte1]: 34
1720 23:38:53.951910
1721 23:38:53.952470 Set Vref, RX VrefLevel [Byte0]: 35
1722 23:38:53.954766 [Byte1]: 35
1723 23:38:53.959736
1724 23:38:53.960495 Set Vref, RX VrefLevel [Byte0]: 36
1725 23:38:53.962963 [Byte1]: 36
1726 23:38:53.967418
1727 23:38:53.967980 Set Vref, RX VrefLevel [Byte0]: 37
1728 23:38:53.970018 [Byte1]: 37
1729 23:38:53.974605
1730 23:38:53.975121 Set Vref, RX VrefLevel [Byte0]: 38
1731 23:38:53.977780 [Byte1]: 38
1732 23:38:53.981969
1733 23:38:53.982736 Set Vref, RX VrefLevel [Byte0]: 39
1734 23:38:53.985641 [Byte1]: 39
1735 23:38:53.989610
1736 23:38:53.990088 Set Vref, RX VrefLevel [Byte0]: 40
1737 23:38:53.992916 [Byte1]: 40
1738 23:38:53.996739
1739 23:38:53.997149 Set Vref, RX VrefLevel [Byte0]: 41
1740 23:38:54.000151 [Byte1]: 41
1741 23:38:54.004778
1742 23:38:54.005338 Set Vref, RX VrefLevel [Byte0]: 42
1743 23:38:54.007789 [Byte1]: 42
1744 23:38:54.012223
1745 23:38:54.012812 Set Vref, RX VrefLevel [Byte0]: 43
1746 23:38:54.015886 [Byte1]: 43
1747 23:38:54.019832
1748 23:38:54.020402 Set Vref, RX VrefLevel [Byte0]: 44
1749 23:38:54.023505 [Byte1]: 44
1750 23:38:54.027608
1751 23:38:54.028169 Set Vref, RX VrefLevel [Byte0]: 45
1752 23:38:54.030549 [Byte1]: 45
1753 23:38:54.034933
1754 23:38:54.035494 Set Vref, RX VrefLevel [Byte0]: 46
1755 23:38:54.038220 [Byte1]: 46
1756 23:38:54.042425
1757 23:38:54.042983 Set Vref, RX VrefLevel [Byte0]: 47
1758 23:38:54.045662 [Byte1]: 47
1759 23:38:54.050197
1760 23:38:54.050760 Set Vref, RX VrefLevel [Byte0]: 48
1761 23:38:54.053039 [Byte1]: 48
1762 23:38:54.057273
1763 23:38:54.057763 Set Vref, RX VrefLevel [Byte0]: 49
1764 23:38:54.060724 [Byte1]: 49
1765 23:38:54.065697
1766 23:38:54.066275 Set Vref, RX VrefLevel [Byte0]: 50
1767 23:38:54.068807 [Byte1]: 50
1768 23:38:54.072693
1769 23:38:54.073159 Set Vref, RX VrefLevel [Byte0]: 51
1770 23:38:54.075892 [Byte1]: 51
1771 23:38:54.080041
1772 23:38:54.080601 Set Vref, RX VrefLevel [Byte0]: 52
1773 23:38:54.083442 [Byte1]: 52
1774 23:38:54.087703
1775 23:38:54.088287 Set Vref, RX VrefLevel [Byte0]: 53
1776 23:38:54.091026 [Byte1]: 53
1777 23:38:54.095045
1778 23:38:54.095507 Set Vref, RX VrefLevel [Byte0]: 54
1779 23:38:54.098599 [Byte1]: 54
1780 23:38:54.103150
1781 23:38:54.103717 Set Vref, RX VrefLevel [Byte0]: 55
1782 23:38:54.106488 [Byte1]: 55
1783 23:38:54.110528
1784 23:38:54.110998 Set Vref, RX VrefLevel [Byte0]: 56
1785 23:38:54.113881 [Byte1]: 56
1786 23:38:54.117689
1787 23:38:54.118117 Set Vref, RX VrefLevel [Byte0]: 57
1788 23:38:54.121158 [Byte1]: 57
1789 23:38:54.125427
1790 23:38:54.125932 Set Vref, RX VrefLevel [Byte0]: 58
1791 23:38:54.128642 [Byte1]: 58
1792 23:38:54.133027
1793 23:38:54.133488 Set Vref, RX VrefLevel [Byte0]: 59
1794 23:38:54.136211 [Byte1]: 59
1795 23:38:54.140929
1796 23:38:54.141502 Set Vref, RX VrefLevel [Byte0]: 60
1797 23:38:54.143913 [Byte1]: 60
1798 23:38:54.147811
1799 23:38:54.148274 Set Vref, RX VrefLevel [Byte0]: 61
1800 23:38:54.151865 [Byte1]: 61
1801 23:38:54.155481
1802 23:38:54.155938 Set Vref, RX VrefLevel [Byte0]: 62
1803 23:38:54.158722 [Byte1]: 62
1804 23:38:54.163469
1805 23:38:54.164057 Set Vref, RX VrefLevel [Byte0]: 63
1806 23:38:54.166546 [Byte1]: 63
1807 23:38:54.170493
1808 23:38:54.171074 Set Vref, RX VrefLevel [Byte0]: 64
1809 23:38:54.173904 [Byte1]: 64
1810 23:38:54.178352
1811 23:38:54.178928 Set Vref, RX VrefLevel [Byte0]: 65
1812 23:38:54.181555 [Byte1]: 65
1813 23:38:54.185751
1814 23:38:54.186398 Set Vref, RX VrefLevel [Byte0]: 66
1815 23:38:54.189179 [Byte1]: 66
1816 23:38:54.193042
1817 23:38:54.193709 Set Vref, RX VrefLevel [Byte0]: 67
1818 23:38:54.196473 [Byte1]: 67
1819 23:38:54.200908
1820 23:38:54.201432 Set Vref, RX VrefLevel [Byte0]: 68
1821 23:38:54.204158 [Byte1]: 68
1822 23:38:54.208586
1823 23:38:54.209120 Set Vref, RX VrefLevel [Byte0]: 69
1824 23:38:54.211710 [Byte1]: 69
1825 23:38:54.215639
1826 23:38:54.216122 Set Vref, RX VrefLevel [Byte0]: 70
1827 23:38:54.219066 [Byte1]: 70
1828 23:38:54.223301
1829 23:38:54.223777 Final RX Vref Byte 0 = 58 to rank0
1830 23:38:54.226987 Final RX Vref Byte 1 = 54 to rank0
1831 23:38:54.230119 Final RX Vref Byte 0 = 58 to rank1
1832 23:38:54.233323 Final RX Vref Byte 1 = 54 to rank1==
1833 23:38:54.236854 Dram Type= 6, Freq= 0, CH_1, rank 0
1834 23:38:54.243228 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1835 23:38:54.243737 ==
1836 23:38:54.244076 DQS Delay:
1837 23:38:54.244388 DQS0 = 0, DQS1 = 0
1838 23:38:54.246964 DQM Delay:
1839 23:38:54.247482 DQM0 = 95, DQM1 = 90
1840 23:38:54.250052 DQ Delay:
1841 23:38:54.253547 DQ0 =100, DQ1 =88, DQ2 =84, DQ3 =92
1842 23:38:54.256349 DQ4 =96, DQ5 =108, DQ6 =100, DQ7 =92
1843 23:38:54.260145 DQ8 =80, DQ9 =80, DQ10 =88, DQ11 =84
1844 23:38:54.263490 DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =100
1845 23:38:54.264025
1846 23:38:54.264370
1847 23:38:54.270002 [DQSOSCAuto] RK0, (LSB)MR18= 0x2744, (MSB)MR19= 0x606, tDQSOscB0 = 392 ps tDQSOscB1 = 400 ps
1848 23:38:54.273273 CH1 RK0: MR19=606, MR18=2744
1849 23:38:54.279988 CH1_RK0: MR19=0x606, MR18=0x2744, DQSOSC=392, MR23=63, INC=96, DEC=64
1850 23:38:54.280512
1851 23:38:54.283497 ----->DramcWriteLeveling(PI) begin...
1852 23:38:54.284022 ==
1853 23:38:54.286806 Dram Type= 6, Freq= 0, CH_1, rank 1
1854 23:38:54.290360 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1855 23:38:54.290883 ==
1856 23:38:54.293754 Write leveling (Byte 0): 26 => 26
1857 23:38:54.296934 Write leveling (Byte 1): 29 => 29
1858 23:38:54.300008 DramcWriteLeveling(PI) end<-----
1859 23:38:54.300428
1860 23:38:54.300758 ==
1861 23:38:54.303407 Dram Type= 6, Freq= 0, CH_1, rank 1
1862 23:38:54.306789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1863 23:38:54.307284 ==
1864 23:38:54.310191 [Gating] SW mode calibration
1865 23:38:54.317201 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1866 23:38:54.323549 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1867 23:38:54.326713 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1868 23:38:54.330252 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1869 23:38:54.337057 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1870 23:38:54.340468 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1871 23:38:54.343554 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1872 23:38:54.350182 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1873 23:38:54.353444 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 23:38:54.357197 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 23:38:54.363784 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 23:38:54.366938 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 23:38:54.370360 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 23:38:54.376836 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 23:38:54.380707 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 23:38:54.384055 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 23:38:54.390540 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 23:38:54.393464 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 23:38:54.397336 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1884 23:38:54.403468 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1885 23:38:54.406717 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 23:38:54.409951 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 23:38:54.416608 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 23:38:54.419973 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 23:38:54.423344 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 23:38:54.426802 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 23:38:54.433685 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 23:38:54.437108 0 9 4 | B1->B0 | 2c2c 2323 | 1 0 | (1 1) (1 1)
1893 23:38:54.440100 0 9 8 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
1894 23:38:54.446861 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1895 23:38:54.449775 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1896 23:38:54.453675 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1897 23:38:54.460143 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1898 23:38:54.463341 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1899 23:38:54.466588 0 10 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
1900 23:38:54.473282 0 10 4 | B1->B0 | 2b2b 3131 | 0 1 | (0 0) (1 0)
1901 23:38:54.477021 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1902 23:38:54.480011 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1903 23:38:54.486636 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1904 23:38:54.489860 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1905 23:38:54.493374 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1906 23:38:54.500040 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1907 23:38:54.503604 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1908 23:38:54.507508 0 11 4 | B1->B0 | 3838 3030 | 1 0 | (0 0) (0 0)
1909 23:38:54.510644 0 11 8 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
1910 23:38:54.517351 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1911 23:38:54.520498 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1912 23:38:54.523612 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1913 23:38:54.530586 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1914 23:38:54.533842 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1915 23:38:54.537192 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1916 23:38:54.543791 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1917 23:38:54.547018 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1918 23:38:54.550209 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1919 23:38:54.557120 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1920 23:38:54.560041 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1921 23:38:54.563717 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1922 23:38:54.569996 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1923 23:38:54.573541 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1924 23:38:54.577391 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1925 23:38:54.584366 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1926 23:38:54.586899 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1927 23:38:54.590225 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1928 23:38:54.596829 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1929 23:38:54.600228 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1930 23:38:54.603766 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1931 23:38:54.606838 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1932 23:38:54.613775 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1933 23:38:54.617031 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1934 23:38:54.621220 Total UI for P1: 0, mck2ui 16
1935 23:38:54.623693 best dqsien dly found for B1: ( 0, 14, 4)
1936 23:38:54.627038 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1937 23:38:54.630641 Total UI for P1: 0, mck2ui 16
1938 23:38:54.633894 best dqsien dly found for B0: ( 0, 14, 8)
1939 23:38:54.637193 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1940 23:38:54.640606 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1941 23:38:54.641171
1942 23:38:54.647381 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1943 23:38:54.650385 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1944 23:38:54.650950 [Gating] SW calibration Done
1945 23:38:54.654054 ==
1946 23:38:54.654624 Dram Type= 6, Freq= 0, CH_1, rank 1
1947 23:38:54.660582 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1948 23:38:54.661154 ==
1949 23:38:54.661526 RX Vref Scan: 0
1950 23:38:54.661916
1951 23:38:54.664115 RX Vref 0 -> 0, step: 1
1952 23:38:54.664689
1953 23:38:54.666905 RX Delay -130 -> 252, step: 16
1954 23:38:54.670475 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1955 23:38:54.674287 iDelay=222, Bit 1, Center 93 (-2 ~ 189) 192
1956 23:38:54.677237 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1957 23:38:54.683937 iDelay=222, Bit 3, Center 93 (-2 ~ 189) 192
1958 23:38:54.687464 iDelay=222, Bit 4, Center 93 (-2 ~ 189) 192
1959 23:38:54.690788 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1960 23:38:54.693668 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1961 23:38:54.697037 iDelay=222, Bit 7, Center 101 (-2 ~ 205) 208
1962 23:38:54.700951 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1963 23:38:54.707255 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1964 23:38:54.710320 iDelay=222, Bit 10, Center 101 (-2 ~ 205) 208
1965 23:38:54.713938 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1966 23:38:54.717223 iDelay=222, Bit 12, Center 101 (-2 ~ 205) 208
1967 23:38:54.720850 iDelay=222, Bit 13, Center 101 (-2 ~ 205) 208
1968 23:38:54.727593 iDelay=222, Bit 14, Center 101 (-2 ~ 205) 208
1969 23:38:54.730315 iDelay=222, Bit 15, Center 101 (-2 ~ 205) 208
1970 23:38:54.730774 ==
1971 23:38:54.734565 Dram Type= 6, Freq= 0, CH_1, rank 1
1972 23:38:54.737195 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1973 23:38:54.737712 ==
1974 23:38:54.740773 DQS Delay:
1975 23:38:54.741241 DQS0 = 0, DQS1 = 0
1976 23:38:54.741656 DQM Delay:
1977 23:38:54.743694 DQM0 = 96, DQM1 = 92
1978 23:38:54.744148 DQ Delay:
1979 23:38:54.747442 DQ0 =101, DQ1 =93, DQ2 =77, DQ3 =93
1980 23:38:54.751177 DQ4 =93, DQ5 =109, DQ6 =101, DQ7 =101
1981 23:38:54.753938 DQ8 =77, DQ9 =77, DQ10 =101, DQ11 =77
1982 23:38:54.757223 DQ12 =101, DQ13 =101, DQ14 =101, DQ15 =101
1983 23:38:54.757840
1984 23:38:54.760965
1985 23:38:54.761525 ==
1986 23:38:54.764361 Dram Type= 6, Freq= 0, CH_1, rank 1
1987 23:38:54.767325 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1988 23:38:54.767788 ==
1989 23:38:54.768154
1990 23:38:54.768492
1991 23:38:54.770574 TX Vref Scan disable
1992 23:38:54.771069 == TX Byte 0 ==
1993 23:38:54.777281 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1994 23:38:54.780605 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1995 23:38:54.781204 == TX Byte 1 ==
1996 23:38:54.787267 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1997 23:38:54.790880 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1998 23:38:54.791446 ==
1999 23:38:54.794010 Dram Type= 6, Freq= 0, CH_1, rank 1
2000 23:38:54.797266 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2001 23:38:54.797796 ==
2002 23:38:54.810993 TX Vref=22, minBit 1, minWin=26, winSum=442
2003 23:38:54.814539 TX Vref=24, minBit 0, minWin=27, winSum=446
2004 23:38:54.818399 TX Vref=26, minBit 1, minWin=26, winSum=448
2005 23:38:54.820605 TX Vref=28, minBit 0, minWin=27, winSum=450
2006 23:38:54.824782 TX Vref=30, minBit 1, minWin=27, winSum=451
2007 23:38:54.827692 TX Vref=32, minBit 2, minWin=27, winSum=450
2008 23:38:54.834253 [TxChooseVref] Worse bit 1, Min win 27, Win sum 451, Final Vref 30
2009 23:38:54.834814
2010 23:38:54.837441 Final TX Range 1 Vref 30
2011 23:38:54.838119
2012 23:38:54.838496 ==
2013 23:38:54.841122 Dram Type= 6, Freq= 0, CH_1, rank 1
2014 23:38:54.844209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2015 23:38:54.844673 ==
2016 23:38:54.845040
2017 23:38:54.845372
2018 23:38:54.847628 TX Vref Scan disable
2019 23:38:54.850998 == TX Byte 0 ==
2020 23:38:54.854652 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2021 23:38:54.857627 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2022 23:38:54.861370 == TX Byte 1 ==
2023 23:38:54.864700 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2024 23:38:54.867382 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2025 23:38:54.867843
2026 23:38:54.871201 [DATLAT]
2027 23:38:54.871699 Freq=800, CH1 RK1
2028 23:38:54.872072
2029 23:38:54.874043 DATLAT Default: 0xa
2030 23:38:54.874544 0, 0xFFFF, sum = 0
2031 23:38:54.877640 1, 0xFFFF, sum = 0
2032 23:38:54.878206 2, 0xFFFF, sum = 0
2033 23:38:54.881130 3, 0xFFFF, sum = 0
2034 23:38:54.881748 4, 0xFFFF, sum = 0
2035 23:38:54.884359 5, 0xFFFF, sum = 0
2036 23:38:54.884931 6, 0xFFFF, sum = 0
2037 23:38:54.887861 7, 0xFFFF, sum = 0
2038 23:38:54.888459 8, 0xFFFF, sum = 0
2039 23:38:54.890872 9, 0x0, sum = 1
2040 23:38:54.891337 10, 0x0, sum = 2
2041 23:38:54.894561 11, 0x0, sum = 3
2042 23:38:54.895126 12, 0x0, sum = 4
2043 23:38:54.898030 best_step = 10
2044 23:38:54.898615
2045 23:38:54.898987 ==
2046 23:38:54.900856 Dram Type= 6, Freq= 0, CH_1, rank 1
2047 23:38:54.904826 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2048 23:38:54.905614 ==
2049 23:38:54.907960 RX Vref Scan: 0
2050 23:38:54.908424
2051 23:38:54.908797 RX Vref 0 -> 0, step: 1
2052 23:38:54.909141
2053 23:38:54.910934 RX Delay -79 -> 252, step: 8
2054 23:38:54.918285 iDelay=209, Bit 0, Center 104 (9 ~ 200) 192
2055 23:38:54.921028 iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200
2056 23:38:54.924468 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
2057 23:38:54.927988 iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200
2058 23:38:54.931293 iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200
2059 23:38:54.934894 iDelay=209, Bit 5, Center 112 (17 ~ 208) 192
2060 23:38:54.941322 iDelay=209, Bit 6, Center 108 (9 ~ 208) 200
2061 23:38:54.944554 iDelay=209, Bit 7, Center 96 (-7 ~ 200) 208
2062 23:38:54.947688 iDelay=209, Bit 8, Center 76 (-31 ~ 184) 216
2063 23:38:54.951137 iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208
2064 23:38:54.954569 iDelay=209, Bit 10, Center 92 (-15 ~ 200) 216
2065 23:38:54.961266 iDelay=209, Bit 11, Center 80 (-23 ~ 184) 208
2066 23:38:54.965267 iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216
2067 23:38:54.968286 iDelay=209, Bit 13, Center 96 (-7 ~ 200) 208
2068 23:38:54.971031 iDelay=209, Bit 14, Center 96 (-7 ~ 200) 208
2069 23:38:54.974995 iDelay=209, Bit 15, Center 96 (-7 ~ 200) 208
2070 23:38:54.975573 ==
2071 23:38:54.977723 Dram Type= 6, Freq= 0, CH_1, rank 1
2072 23:38:54.984439 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2073 23:38:54.985007 ==
2074 23:38:54.985375 DQS Delay:
2075 23:38:54.987799 DQS0 = 0, DQS1 = 0
2076 23:38:54.988258 DQM Delay:
2077 23:38:54.988620 DQM0 = 97, DQM1 = 89
2078 23:38:54.991525 DQ Delay:
2079 23:38:54.994591 DQ0 =104, DQ1 =92, DQ2 =84, DQ3 =92
2080 23:38:54.998020 DQ4 =92, DQ5 =112, DQ6 =108, DQ7 =96
2081 23:38:55.001421 DQ8 =76, DQ9 =80, DQ10 =92, DQ11 =80
2082 23:38:55.004407 DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =96
2083 23:38:55.004967
2084 23:38:55.005443
2085 23:38:55.011152 [DQSOSCAuto] RK1, (LSB)MR18= 0x440d, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 392 ps
2086 23:38:55.014643 CH1 RK1: MR19=606, MR18=440D
2087 23:38:55.021635 CH1_RK1: MR19=0x606, MR18=0x440D, DQSOSC=392, MR23=63, INC=96, DEC=64
2088 23:38:55.024777 [RxdqsGatingPostProcess] freq 800
2089 23:38:55.028327 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2090 23:38:55.031113 Pre-setting of DQS Precalculation
2091 23:38:55.038026 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2092 23:38:55.044253 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2093 23:38:55.050909 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2094 23:38:55.051467
2095 23:38:55.051837
2096 23:38:55.054586 [Calibration Summary] 1600 Mbps
2097 23:38:55.055367 CH 0, Rank 0
2098 23:38:55.057879 SW Impedance : PASS
2099 23:38:55.061809 DUTY Scan : NO K
2100 23:38:55.062361 ZQ Calibration : PASS
2101 23:38:55.064432 Jitter Meter : NO K
2102 23:38:55.067956 CBT Training : PASS
2103 23:38:55.068521 Write leveling : PASS
2104 23:38:55.070836 RX DQS gating : PASS
2105 23:38:55.074432 RX DQ/DQS(RDDQC) : PASS
2106 23:38:55.074893 TX DQ/DQS : PASS
2107 23:38:55.077487 RX DATLAT : PASS
2108 23:38:55.081022 RX DQ/DQS(Engine): PASS
2109 23:38:55.081720 TX OE : NO K
2110 23:38:55.082106 All Pass.
2111 23:38:55.084156
2112 23:38:55.084738 CH 0, Rank 1
2113 23:38:55.087755 SW Impedance : PASS
2114 23:38:55.088317 DUTY Scan : NO K
2115 23:38:55.091193 ZQ Calibration : PASS
2116 23:38:55.091975 Jitter Meter : NO K
2117 23:38:55.094095 CBT Training : PASS
2118 23:38:55.098063 Write leveling : PASS
2119 23:38:55.098644 RX DQS gating : PASS
2120 23:38:55.101160 RX DQ/DQS(RDDQC) : PASS
2121 23:38:55.104334 TX DQ/DQS : PASS
2122 23:38:55.104922 RX DATLAT : PASS
2123 23:38:55.107613 RX DQ/DQS(Engine): PASS
2124 23:38:55.111094 TX OE : NO K
2125 23:38:55.111553 All Pass.
2126 23:38:55.111962
2127 23:38:55.112348 CH 1, Rank 0
2128 23:38:55.114343 SW Impedance : PASS
2129 23:38:55.117561 DUTY Scan : NO K
2130 23:38:55.118207 ZQ Calibration : PASS
2131 23:38:55.120794 Jitter Meter : NO K
2132 23:38:55.124528 CBT Training : PASS
2133 23:38:55.125112 Write leveling : PASS
2134 23:38:55.127827 RX DQS gating : PASS
2135 23:38:55.128287 RX DQ/DQS(RDDQC) : PASS
2136 23:38:55.131224 TX DQ/DQS : PASS
2137 23:38:55.134053 RX DATLAT : PASS
2138 23:38:55.134510 RX DQ/DQS(Engine): PASS
2139 23:38:55.137979 TX OE : NO K
2140 23:38:55.138394 All Pass.
2141 23:38:55.138722
2142 23:38:55.141080 CH 1, Rank 1
2143 23:38:55.141495 SW Impedance : PASS
2144 23:38:55.144417 DUTY Scan : NO K
2145 23:38:55.147888 ZQ Calibration : PASS
2146 23:38:55.148407 Jitter Meter : NO K
2147 23:38:55.151209 CBT Training : PASS
2148 23:38:55.154218 Write leveling : PASS
2149 23:38:55.154635 RX DQS gating : PASS
2150 23:38:55.158176 RX DQ/DQS(RDDQC) : PASS
2151 23:38:55.161055 TX DQ/DQS : PASS
2152 23:38:55.161624 RX DATLAT : PASS
2153 23:38:55.164987 RX DQ/DQS(Engine): PASS
2154 23:38:55.165500 TX OE : NO K
2155 23:38:55.168134 All Pass.
2156 23:38:55.168664
2157 23:38:55.169004 DramC Write-DBI off
2158 23:38:55.170843 PER_BANK_REFRESH: Hybrid Mode
2159 23:38:55.174691 TX_TRACKING: ON
2160 23:38:55.178354 [GetDramInforAfterCalByMRR] Vendor 6.
2161 23:38:55.181278 [GetDramInforAfterCalByMRR] Revision 606.
2162 23:38:55.184867 [GetDramInforAfterCalByMRR] Revision 2 0.
2163 23:38:55.185426 MR0 0x3b3b
2164 23:38:55.185885 MR8 0x5151
2165 23:38:55.191319 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2166 23:38:55.191884
2167 23:38:55.192257 MR0 0x3b3b
2168 23:38:55.192605 MR8 0x5151
2169 23:38:55.194493 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2170 23:38:55.194960
2171 23:38:55.204919 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2172 23:38:55.207653 [FAST_K] Save calibration result to emmc
2173 23:38:55.211314 [FAST_K] Save calibration result to emmc
2174 23:38:55.214387 dram_init: config_dvfs: 1
2175 23:38:55.217902 dramc_set_vcore_voltage set vcore to 662500
2176 23:38:55.221332 Read voltage for 1200, 2
2177 23:38:55.221973 Vio18 = 0
2178 23:38:55.222346 Vcore = 662500
2179 23:38:55.224476 Vdram = 0
2180 23:38:55.224939 Vddq = 0
2181 23:38:55.225341 Vmddr = 0
2182 23:38:55.231007 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2183 23:38:55.235331 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2184 23:38:55.237763 MEM_TYPE=3, freq_sel=15
2185 23:38:55.241172 sv_algorithm_assistance_LP4_1600
2186 23:38:55.244907 ============ PULL DRAM RESETB DOWN ============
2187 23:38:55.248428 ========== PULL DRAM RESETB DOWN end =========
2188 23:38:55.254850 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2189 23:38:55.257968 ===================================
2190 23:38:55.258394 LPDDR4 DRAM CONFIGURATION
2191 23:38:55.261153 ===================================
2192 23:38:55.264744 EX_ROW_EN[0] = 0x0
2193 23:38:55.267858 EX_ROW_EN[1] = 0x0
2194 23:38:55.268350 LP4Y_EN = 0x0
2195 23:38:55.271235 WORK_FSP = 0x0
2196 23:38:55.271658 WL = 0x4
2197 23:38:55.274905 RL = 0x4
2198 23:38:55.275327 BL = 0x2
2199 23:38:55.277967 RPST = 0x0
2200 23:38:55.278388 RD_PRE = 0x0
2201 23:38:55.281466 WR_PRE = 0x1
2202 23:38:55.281925 WR_PST = 0x0
2203 23:38:55.284428 DBI_WR = 0x0
2204 23:38:55.284850 DBI_RD = 0x0
2205 23:38:55.287830 OTF = 0x1
2206 23:38:55.291333 ===================================
2207 23:38:55.294473 ===================================
2208 23:38:55.295008 ANA top config
2209 23:38:55.297818 ===================================
2210 23:38:55.301097 DLL_ASYNC_EN = 0
2211 23:38:55.305208 ALL_SLAVE_EN = 0
2212 23:38:55.307942 NEW_RANK_MODE = 1
2213 23:38:55.308422 DLL_IDLE_MODE = 1
2214 23:38:55.311443 LP45_APHY_COMB_EN = 1
2215 23:38:55.314305 TX_ODT_DIS = 1
2216 23:38:55.318483 NEW_8X_MODE = 1
2217 23:38:55.321059 ===================================
2218 23:38:55.324678 ===================================
2219 23:38:55.327930 data_rate = 2400
2220 23:38:55.328661 CKR = 1
2221 23:38:55.331046 DQ_P2S_RATIO = 8
2222 23:38:55.334735 ===================================
2223 23:38:55.338231 CA_P2S_RATIO = 8
2224 23:38:55.341054 DQ_CA_OPEN = 0
2225 23:38:55.344927 DQ_SEMI_OPEN = 0
2226 23:38:55.348075 CA_SEMI_OPEN = 0
2227 23:38:55.348648 CA_FULL_RATE = 0
2228 23:38:55.351432 DQ_CKDIV4_EN = 0
2229 23:38:55.354289 CA_CKDIV4_EN = 0
2230 23:38:55.357795 CA_PREDIV_EN = 0
2231 23:38:55.361402 PH8_DLY = 17
2232 23:38:55.364854 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2233 23:38:55.365424 DQ_AAMCK_DIV = 4
2234 23:38:55.368144 CA_AAMCK_DIV = 4
2235 23:38:55.371006 CA_ADMCK_DIV = 4
2236 23:38:55.375195 DQ_TRACK_CA_EN = 0
2237 23:38:55.378069 CA_PICK = 1200
2238 23:38:55.381382 CA_MCKIO = 1200
2239 23:38:55.381970 MCKIO_SEMI = 0
2240 23:38:55.385281 PLL_FREQ = 2366
2241 23:38:55.388210 DQ_UI_PI_RATIO = 32
2242 23:38:55.391642 CA_UI_PI_RATIO = 0
2243 23:38:55.394869 ===================================
2244 23:38:55.398178 ===================================
2245 23:38:55.401209 memory_type:LPDDR4
2246 23:38:55.401760 GP_NUM : 10
2247 23:38:55.405224 SRAM_EN : 1
2248 23:38:55.407909 MD32_EN : 0
2249 23:38:55.408391 ===================================
2250 23:38:55.411503 [ANA_INIT] >>>>>>>>>>>>>>
2251 23:38:55.414629 <<<<<< [CONFIGURE PHASE]: ANA_TX
2252 23:38:55.418240 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2253 23:38:55.421934 ===================================
2254 23:38:55.425110 data_rate = 2400,PCW = 0X5b00
2255 23:38:55.428274 ===================================
2256 23:38:55.431519 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2257 23:38:55.438486 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2258 23:38:55.441329 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2259 23:38:55.448543 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2260 23:38:55.451489 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2261 23:38:55.454867 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2262 23:38:55.455434 [ANA_INIT] flow start
2263 23:38:55.457821 [ANA_INIT] PLL >>>>>>>>
2264 23:38:55.461411 [ANA_INIT] PLL <<<<<<<<
2265 23:38:55.461928 [ANA_INIT] MIDPI >>>>>>>>
2266 23:38:55.465111 [ANA_INIT] MIDPI <<<<<<<<
2267 23:38:55.467948 [ANA_INIT] DLL >>>>>>>>
2268 23:38:55.468534 [ANA_INIT] DLL <<<<<<<<
2269 23:38:55.471235 [ANA_INIT] flow end
2270 23:38:55.475039 ============ LP4 DIFF to SE enter ============
2271 23:38:55.477875 ============ LP4 DIFF to SE exit ============
2272 23:38:55.481496 [ANA_INIT] <<<<<<<<<<<<<
2273 23:38:55.484630 [Flow] Enable top DCM control >>>>>
2274 23:38:55.488429 [Flow] Enable top DCM control <<<<<
2275 23:38:55.491181 Enable DLL master slave shuffle
2276 23:38:55.498580 ==============================================================
2277 23:38:55.499138 Gating Mode config
2278 23:38:55.504911 ==============================================================
2279 23:38:55.505474 Config description:
2280 23:38:55.514726 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2281 23:38:55.522115 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2282 23:38:55.528660 SELPH_MODE 0: By rank 1: By Phase
2283 23:38:55.531549 ==============================================================
2284 23:38:55.535063 GAT_TRACK_EN = 1
2285 23:38:55.538246 RX_GATING_MODE = 2
2286 23:38:55.541783 RX_GATING_TRACK_MODE = 2
2287 23:38:55.545016 SELPH_MODE = 1
2288 23:38:55.548275 PICG_EARLY_EN = 1
2289 23:38:55.551850 VALID_LAT_VALUE = 1
2290 23:38:55.558641 ==============================================================
2291 23:38:55.561497 Enter into Gating configuration >>>>
2292 23:38:55.565247 Exit from Gating configuration <<<<
2293 23:38:55.565867 Enter into DVFS_PRE_config >>>>>
2294 23:38:55.578465 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2295 23:38:55.581476 Exit from DVFS_PRE_config <<<<<
2296 23:38:55.585019 Enter into PICG configuration >>>>
2297 23:38:55.588132 Exit from PICG configuration <<<<
2298 23:38:55.588696 [RX_INPUT] configuration >>>>>
2299 23:38:55.591508 [RX_INPUT] configuration <<<<<
2300 23:38:55.598398 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2301 23:38:55.601556 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2302 23:38:55.607929 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2303 23:38:55.614559 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2304 23:38:55.621647 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2305 23:38:55.627817 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2306 23:38:55.631634 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2307 23:38:55.634742 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2308 23:38:55.638050 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2309 23:38:55.644806 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2310 23:38:55.648780 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2311 23:38:55.651409 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2312 23:38:55.654858 ===================================
2313 23:38:55.658157 LPDDR4 DRAM CONFIGURATION
2314 23:38:55.661649 ===================================
2315 23:38:55.665257 EX_ROW_EN[0] = 0x0
2316 23:38:55.665862 EX_ROW_EN[1] = 0x0
2317 23:38:55.668537 LP4Y_EN = 0x0
2318 23:38:55.669066 WORK_FSP = 0x0
2319 23:38:55.671732 WL = 0x4
2320 23:38:55.672292 RL = 0x4
2321 23:38:55.674623 BL = 0x2
2322 23:38:55.675101 RPST = 0x0
2323 23:38:55.678001 RD_PRE = 0x0
2324 23:38:55.678467 WR_PRE = 0x1
2325 23:38:55.681495 WR_PST = 0x0
2326 23:38:55.682010 DBI_WR = 0x0
2327 23:38:55.684722 DBI_RD = 0x0
2328 23:38:55.685274 OTF = 0x1
2329 23:38:55.688164 ===================================
2330 23:38:55.695121 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2331 23:38:55.698164 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2332 23:38:55.701192 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2333 23:38:55.704389 ===================================
2334 23:38:55.708071 LPDDR4 DRAM CONFIGURATION
2335 23:38:55.711297 ===================================
2336 23:38:55.711769 EX_ROW_EN[0] = 0x10
2337 23:38:55.715006 EX_ROW_EN[1] = 0x0
2338 23:38:55.718368 LP4Y_EN = 0x0
2339 23:38:55.718928 WORK_FSP = 0x0
2340 23:38:55.721813 WL = 0x4
2341 23:38:55.722378 RL = 0x4
2342 23:38:55.724747 BL = 0x2
2343 23:38:55.725317 RPST = 0x0
2344 23:38:55.728473 RD_PRE = 0x0
2345 23:38:55.729037 WR_PRE = 0x1
2346 23:38:55.731462 WR_PST = 0x0
2347 23:38:55.731927 DBI_WR = 0x0
2348 23:38:55.734999 DBI_RD = 0x0
2349 23:38:55.735463 OTF = 0x1
2350 23:38:55.738201 ===================================
2351 23:38:55.744915 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2352 23:38:55.745742 ==
2353 23:38:55.748275 Dram Type= 6, Freq= 0, CH_0, rank 0
2354 23:38:55.751420 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2355 23:38:55.751984 ==
2356 23:38:55.755388 [Duty_Offset_Calibration]
2357 23:38:55.758138 B0:2 B1:1 CA:1
2358 23:38:55.758604
2359 23:38:55.761225 [DutyScan_Calibration_Flow] k_type=0
2360 23:38:55.769486
2361 23:38:55.769985 ==CLK 0==
2362 23:38:55.772567 Final CLK duty delay cell = 0
2363 23:38:55.776142 [0] MAX Duty = 5187%(X100), DQS PI = 24
2364 23:38:55.779620 [0] MIN Duty = 4875%(X100), DQS PI = 0
2365 23:38:55.780139 [0] AVG Duty = 5031%(X100)
2366 23:38:55.782805
2367 23:38:55.783264 CH0 CLK Duty spec in!! Max-Min= 312%
2368 23:38:55.790046 [DutyScan_Calibration_Flow] ====Done====
2369 23:38:55.790461
2370 23:38:55.792914 [DutyScan_Calibration_Flow] k_type=1
2371 23:38:55.807822
2372 23:38:55.808246 ==DQS 0 ==
2373 23:38:55.811171 Final DQS duty delay cell = -4
2374 23:38:55.814791 [-4] MAX Duty = 5124%(X100), DQS PI = 22
2375 23:38:55.817703 [-4] MIN Duty = 4751%(X100), DQS PI = 0
2376 23:38:55.821181 [-4] AVG Duty = 4937%(X100)
2377 23:38:55.821789
2378 23:38:55.822171 ==DQS 1 ==
2379 23:38:55.824818 Final DQS duty delay cell = 0
2380 23:38:55.828604 [0] MAX Duty = 5156%(X100), DQS PI = 62
2381 23:38:55.831316 [0] MIN Duty = 5000%(X100), DQS PI = 34
2382 23:38:55.834910 [0] AVG Duty = 5078%(X100)
2383 23:38:55.835469
2384 23:38:55.838267 CH0 DQS 0 Duty spec in!! Max-Min= 373%
2385 23:38:55.838803
2386 23:38:55.841560 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2387 23:38:55.845332 [DutyScan_Calibration_Flow] ====Done====
2388 23:38:55.845956
2389 23:38:55.848025 [DutyScan_Calibration_Flow] k_type=3
2390 23:38:55.864952
2391 23:38:55.865527 ==DQM 0 ==
2392 23:38:55.868308 Final DQM duty delay cell = 0
2393 23:38:55.871441 [0] MAX Duty = 5156%(X100), DQS PI = 30
2394 23:38:55.874883 [0] MIN Duty = 4906%(X100), DQS PI = 50
2395 23:38:55.878272 [0] AVG Duty = 5031%(X100)
2396 23:38:55.878734
2397 23:38:55.879097 ==DQM 1 ==
2398 23:38:55.881726 Final DQM duty delay cell = 0
2399 23:38:55.885090 [0] MAX Duty = 5093%(X100), DQS PI = 0
2400 23:38:55.888688 [0] MIN Duty = 5031%(X100), DQS PI = 14
2401 23:38:55.891494 [0] AVG Duty = 5062%(X100)
2402 23:38:55.892061
2403 23:38:55.895100 CH0 DQM 0 Duty spec in!! Max-Min= 250%
2404 23:38:55.895660
2405 23:38:55.898508 CH0 DQM 1 Duty spec in!! Max-Min= 62%
2406 23:38:55.901937 [DutyScan_Calibration_Flow] ====Done====
2407 23:38:55.902566
2408 23:38:55.904540 [DutyScan_Calibration_Flow] k_type=2
2409 23:38:55.921483
2410 23:38:55.922090 ==DQ 0 ==
2411 23:38:55.924642 Final DQ duty delay cell = 0
2412 23:38:55.927828 [0] MAX Duty = 5062%(X100), DQS PI = 32
2413 23:38:55.931897 [0] MIN Duty = 4875%(X100), DQS PI = 62
2414 23:38:55.932469 [0] AVG Duty = 4968%(X100)
2415 23:38:55.932843
2416 23:38:55.935293 ==DQ 1 ==
2417 23:38:55.938357 Final DQ duty delay cell = 0
2418 23:38:55.941313 [0] MAX Duty = 5093%(X100), DQS PI = 10
2419 23:38:55.944991 [0] MIN Duty = 4969%(X100), DQS PI = 2
2420 23:38:55.945564 [0] AVG Duty = 5031%(X100)
2421 23:38:55.945985
2422 23:38:55.948159 CH0 DQ 0 Duty spec in!! Max-Min= 187%
2423 23:38:55.948651
2424 23:38:55.952026 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2425 23:38:55.958360 [DutyScan_Calibration_Flow] ====Done====
2426 23:38:55.958927 ==
2427 23:38:55.961712 Dram Type= 6, Freq= 0, CH_1, rank 0
2428 23:38:55.965085 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2429 23:38:55.965704 ==
2430 23:38:55.968129 [Duty_Offset_Calibration]
2431 23:38:55.968601 B0:1 B1:0 CA:0
2432 23:38:55.968974
2433 23:38:55.971848 [DutyScan_Calibration_Flow] k_type=0
2434 23:38:55.980352
2435 23:38:55.980913 ==CLK 0==
2436 23:38:55.984097 Final CLK duty delay cell = -4
2437 23:38:55.987026 [-4] MAX Duty = 5000%(X100), DQS PI = 8
2438 23:38:55.990233 [-4] MIN Duty = 4938%(X100), DQS PI = 0
2439 23:38:55.993953 [-4] AVG Duty = 4969%(X100)
2440 23:38:55.994535
2441 23:38:55.996947 CH1 CLK Duty spec in!! Max-Min= 62%
2442 23:38:56.000273 [DutyScan_Calibration_Flow] ====Done====
2443 23:38:56.000851
2444 23:38:56.003364 [DutyScan_Calibration_Flow] k_type=1
2445 23:38:56.019836
2446 23:38:56.020396 ==DQS 0 ==
2447 23:38:56.023290 Final DQS duty delay cell = 0
2448 23:38:56.027172 [0] MAX Duty = 5094%(X100), DQS PI = 56
2449 23:38:56.030305 [0] MIN Duty = 4875%(X100), DQS PI = 32
2450 23:38:56.033147 [0] AVG Duty = 4984%(X100)
2451 23:38:56.033647
2452 23:38:56.034029 ==DQS 1 ==
2453 23:38:56.036893 Final DQS duty delay cell = 0
2454 23:38:56.039756 [0] MAX Duty = 5156%(X100), DQS PI = 50
2455 23:38:56.043599 [0] MIN Duty = 4938%(X100), DQS PI = 44
2456 23:38:56.044167 [0] AVG Duty = 5047%(X100)
2457 23:38:56.046789
2458 23:38:56.049817 CH1 DQS 0 Duty spec in!! Max-Min= 219%
2459 23:38:56.050283
2460 23:38:56.053235 CH1 DQS 1 Duty spec in!! Max-Min= 218%
2461 23:38:56.056677 [DutyScan_Calibration_Flow] ====Done====
2462 23:38:56.057239
2463 23:38:56.060678 [DutyScan_Calibration_Flow] k_type=3
2464 23:38:56.076896
2465 23:38:56.077481 ==DQM 0 ==
2466 23:38:56.079723 Final DQM duty delay cell = 0
2467 23:38:56.083260 [0] MAX Duty = 5156%(X100), DQS PI = 2
2468 23:38:56.086680 [0] MIN Duty = 5031%(X100), DQS PI = 30
2469 23:38:56.087243 [0] AVG Duty = 5093%(X100)
2470 23:38:56.087616
2471 23:38:56.090238 ==DQM 1 ==
2472 23:38:56.093082 Final DQM duty delay cell = 0
2473 23:38:56.096846 [0] MAX Duty = 5031%(X100), DQS PI = 10
2474 23:38:56.099818 [0] MIN Duty = 4875%(X100), DQS PI = 4
2475 23:38:56.100431 [0] AVG Duty = 4953%(X100)
2476 23:38:56.100810
2477 23:38:56.106543 CH1 DQM 0 Duty spec in!! Max-Min= 125%
2478 23:38:56.107120
2479 23:38:56.110068 CH1 DQM 1 Duty spec in!! Max-Min= 156%
2480 23:38:56.112940 [DutyScan_Calibration_Flow] ====Done====
2481 23:38:56.113409
2482 23:38:56.116560 [DutyScan_Calibration_Flow] k_type=2
2483 23:38:56.132374
2484 23:38:56.132960 ==DQ 0 ==
2485 23:38:56.135484 Final DQ duty delay cell = -4
2486 23:38:56.139214 [-4] MAX Duty = 5062%(X100), DQS PI = 22
2487 23:38:56.142090 [-4] MIN Duty = 4938%(X100), DQS PI = 6
2488 23:38:56.146014 [-4] AVG Duty = 5000%(X100)
2489 23:38:56.146576
2490 23:38:56.146953 ==DQ 1 ==
2491 23:38:56.149621 Final DQ duty delay cell = 0
2492 23:38:56.152220 [0] MAX Duty = 5093%(X100), DQS PI = 10
2493 23:38:56.155806 [0] MIN Duty = 4938%(X100), DQS PI = 2
2494 23:38:56.156371 [0] AVG Duty = 5015%(X100)
2495 23:38:56.159317
2496 23:38:56.162429 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2497 23:38:56.162898
2498 23:38:56.165748 CH1 DQ 1 Duty spec in!! Max-Min= 155%
2499 23:38:56.169556 [DutyScan_Calibration_Flow] ====Done====
2500 23:38:56.172311 nWR fixed to 30
2501 23:38:56.172876 [ModeRegInit_LP4] CH0 RK0
2502 23:38:56.175966 [ModeRegInit_LP4] CH0 RK1
2503 23:38:56.178906 [ModeRegInit_LP4] CH1 RK0
2504 23:38:56.182199 [ModeRegInit_LP4] CH1 RK1
2505 23:38:56.182758 match AC timing 7
2506 23:38:56.185687 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2507 23:38:56.189117 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2508 23:38:56.195774 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2509 23:38:56.198974 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2510 23:38:56.206129 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2511 23:38:56.206692 ==
2512 23:38:56.209196 Dram Type= 6, Freq= 0, CH_0, rank 0
2513 23:38:56.212467 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2514 23:38:56.213191 ==
2515 23:38:56.219303 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2516 23:38:56.222488 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2517 23:38:56.232741 [CA 0] Center 39 (8~70) winsize 63
2518 23:38:56.236447 [CA 1] Center 39 (8~70) winsize 63
2519 23:38:56.239409 [CA 2] Center 35 (5~66) winsize 62
2520 23:38:56.242161 [CA 3] Center 34 (4~65) winsize 62
2521 23:38:56.246092 [CA 4] Center 33 (3~64) winsize 62
2522 23:38:56.249666 [CA 5] Center 32 (3~62) winsize 60
2523 23:38:56.250244
2524 23:38:56.252756 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2525 23:38:56.253322
2526 23:38:56.255717 [CATrainingPosCal] consider 1 rank data
2527 23:38:56.258926 u2DelayCellTimex100 = 270/100 ps
2528 23:38:56.262566 CA0 delay=39 (8~70),Diff = 7 PI (33 cell)
2529 23:38:56.265888 CA1 delay=39 (8~70),Diff = 7 PI (33 cell)
2530 23:38:56.268870 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2531 23:38:56.276291 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2532 23:38:56.279329 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2533 23:38:56.282301 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2534 23:38:56.282727
2535 23:38:56.286103 CA PerBit enable=1, Macro0, CA PI delay=32
2536 23:38:56.286531
2537 23:38:56.289011 [CBTSetCACLKResult] CA Dly = 32
2538 23:38:56.289434 CS Dly: 6 (0~37)
2539 23:38:56.289825 ==
2540 23:38:56.292517 Dram Type= 6, Freq= 0, CH_0, rank 1
2541 23:38:56.299392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2542 23:38:56.299922 ==
2543 23:38:56.302729 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2544 23:38:56.309387 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2545 23:38:56.318024 [CA 0] Center 38 (8~69) winsize 62
2546 23:38:56.321564 [CA 1] Center 38 (8~69) winsize 62
2547 23:38:56.324901 [CA 2] Center 35 (4~66) winsize 63
2548 23:38:56.328249 [CA 3] Center 34 (4~65) winsize 62
2549 23:38:56.331517 [CA 4] Center 33 (3~64) winsize 62
2550 23:38:56.334759 [CA 5] Center 32 (3~62) winsize 60
2551 23:38:56.335185
2552 23:38:56.338421 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2553 23:38:56.338954
2554 23:38:56.341264 [CATrainingPosCal] consider 2 rank data
2555 23:38:56.344878 u2DelayCellTimex100 = 270/100 ps
2556 23:38:56.347887 CA0 delay=38 (8~69),Diff = 6 PI (28 cell)
2557 23:38:56.351451 CA1 delay=38 (8~69),Diff = 6 PI (28 cell)
2558 23:38:56.358175 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2559 23:38:56.362067 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2560 23:38:56.364931 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2561 23:38:56.368414 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2562 23:38:56.368972
2563 23:38:56.371325 CA PerBit enable=1, Macro0, CA PI delay=32
2564 23:38:56.371750
2565 23:38:56.374741 [CBTSetCACLKResult] CA Dly = 32
2566 23:38:56.375210 CS Dly: 6 (0~38)
2567 23:38:56.375579
2568 23:38:56.378136 ----->DramcWriteLeveling(PI) begin...
2569 23:38:56.381489 ==
2570 23:38:56.381964 Dram Type= 6, Freq= 0, CH_0, rank 0
2571 23:38:56.388552 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2572 23:38:56.389124 ==
2573 23:38:56.391648 Write leveling (Byte 0): 34 => 34
2574 23:38:56.394827 Write leveling (Byte 1): 30 => 30
2575 23:38:56.395296 DramcWriteLeveling(PI) end<-----
2576 23:38:56.398333
2577 23:38:56.398902 ==
2578 23:38:56.401814 Dram Type= 6, Freq= 0, CH_0, rank 0
2579 23:38:56.405475 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2580 23:38:56.406081 ==
2581 23:38:56.409066 [Gating] SW mode calibration
2582 23:38:56.415599 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2583 23:38:56.418275 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2584 23:38:56.425249 0 15 0 | B1->B0 | 2424 3232 | 0 0 | (0 0) (0 0)
2585 23:38:56.428489 0 15 4 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
2586 23:38:56.431886 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2587 23:38:56.438956 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2588 23:38:56.442137 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2589 23:38:56.445360 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2590 23:38:56.451947 0 15 24 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)
2591 23:38:56.455294 0 15 28 | B1->B0 | 3434 2323 | 0 0 | (0 0) (0 0)
2592 23:38:56.458997 1 0 0 | B1->B0 | 2b2b 2323 | 0 0 | (1 0) (0 0)
2593 23:38:56.461929 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2594 23:38:56.468858 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2595 23:38:56.471795 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2596 23:38:56.475183 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2597 23:38:56.482250 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2598 23:38:56.485816 1 0 24 | B1->B0 | 2323 2a2a | 0 1 | (0 0) (0 0)
2599 23:38:56.488433 1 0 28 | B1->B0 | 2828 4646 | 0 0 | (0 0) (0 0)
2600 23:38:56.495254 1 1 0 | B1->B0 | 3333 4646 | 0 0 | (0 0) (0 0)
2601 23:38:56.498739 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2602 23:38:56.502213 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2603 23:38:56.508942 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2604 23:38:56.512118 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2605 23:38:56.515562 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2606 23:38:56.522143 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2607 23:38:56.525710 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2608 23:38:56.528808 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2609 23:38:56.535899 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2610 23:38:56.538852 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2611 23:38:56.542388 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2612 23:38:56.545490 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2613 23:38:56.552548 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2614 23:38:56.555958 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2615 23:38:56.559048 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2616 23:38:56.565427 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2617 23:38:56.569299 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2618 23:38:56.572116 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2619 23:38:56.579064 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2620 23:38:56.582232 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2621 23:38:56.585810 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2622 23:38:56.592405 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2623 23:38:56.595539 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2624 23:38:56.598951 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2625 23:38:56.602350 Total UI for P1: 0, mck2ui 16
2626 23:38:56.605549 best dqsien dly found for B0: ( 1, 3, 26)
2627 23:38:56.612920 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2628 23:38:56.613494 Total UI for P1: 0, mck2ui 16
2629 23:38:56.616182 best dqsien dly found for B1: ( 1, 4, 0)
2630 23:38:56.618799 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2631 23:38:56.626255 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2632 23:38:56.626829
2633 23:38:56.629416 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2634 23:38:56.632989 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2635 23:38:56.635505 [Gating] SW calibration Done
2636 23:38:56.636002 ==
2637 23:38:56.639573 Dram Type= 6, Freq= 0, CH_0, rank 0
2638 23:38:56.642958 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2639 23:38:56.643431 ==
2640 23:38:56.643802 RX Vref Scan: 0
2641 23:38:56.644147
2642 23:38:56.645630 RX Vref 0 -> 0, step: 1
2643 23:38:56.646101
2644 23:38:56.649339 RX Delay -40 -> 252, step: 8
2645 23:38:56.652735 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2646 23:38:56.655896 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2647 23:38:56.662697 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2648 23:38:56.665997 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2649 23:38:56.669145 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2650 23:38:56.672161 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2651 23:38:56.676174 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2652 23:38:56.683036 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2653 23:38:56.686027 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2654 23:38:56.689236 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
2655 23:38:56.692951 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2656 23:38:56.695663 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2657 23:38:56.702570 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2658 23:38:56.706325 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2659 23:38:56.709679 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2660 23:38:56.712697 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2661 23:38:56.713267 ==
2662 23:38:56.715508 Dram Type= 6, Freq= 0, CH_0, rank 0
2663 23:38:56.719275 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2664 23:38:56.722460 ==
2665 23:38:56.723029 DQS Delay:
2666 23:38:56.723401 DQS0 = 0, DQS1 = 0
2667 23:38:56.725482 DQM Delay:
2668 23:38:56.726001 DQM0 = 121, DQM1 = 113
2669 23:38:56.729073 DQ Delay:
2670 23:38:56.732848 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2671 23:38:56.735662 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2672 23:38:56.739060 DQ8 =99, DQ9 =107, DQ10 =111, DQ11 =107
2673 23:38:56.742933 DQ12 =119, DQ13 =123, DQ14 =123, DQ15 =119
2674 23:38:56.743504
2675 23:38:56.743877
2676 23:38:56.744221 ==
2677 23:38:56.745765 Dram Type= 6, Freq= 0, CH_0, rank 0
2678 23:38:56.748995 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2679 23:38:56.749626 ==
2680 23:38:56.750011
2681 23:38:56.750355
2682 23:38:56.752648 TX Vref Scan disable
2683 23:38:56.755924 == TX Byte 0 ==
2684 23:38:56.759294 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2685 23:38:56.762585 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2686 23:38:56.766070 == TX Byte 1 ==
2687 23:38:56.769123 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2688 23:38:56.772355 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2689 23:38:56.772931 ==
2690 23:38:56.776347 Dram Type= 6, Freq= 0, CH_0, rank 0
2691 23:38:56.782801 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2692 23:38:56.783379 ==
2693 23:38:56.793193 TX Vref=22, minBit 0, minWin=24, winSum=401
2694 23:38:56.796125 TX Vref=24, minBit 2, minWin=25, winSum=409
2695 23:38:56.800285 TX Vref=26, minBit 7, minWin=25, winSum=416
2696 23:38:56.803123 TX Vref=28, minBit 15, minWin=25, winSum=420
2697 23:38:56.806696 TX Vref=30, minBit 0, minWin=26, winSum=424
2698 23:38:56.813156 TX Vref=32, minBit 10, minWin=25, winSum=421
2699 23:38:56.816529 [TxChooseVref] Worse bit 0, Min win 26, Win sum 424, Final Vref 30
2700 23:38:56.817112
2701 23:38:56.819553 Final TX Range 1 Vref 30
2702 23:38:56.820021
2703 23:38:56.820388 ==
2704 23:38:56.823073 Dram Type= 6, Freq= 0, CH_0, rank 0
2705 23:38:56.826777 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2706 23:38:56.827358 ==
2707 23:38:56.829394
2708 23:38:56.829905
2709 23:38:56.830275 TX Vref Scan disable
2710 23:38:56.832755 == TX Byte 0 ==
2711 23:38:56.836716 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2712 23:38:56.839941 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2713 23:38:56.842931 == TX Byte 1 ==
2714 23:38:56.846078 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2715 23:38:56.849754 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2716 23:38:56.853082
2717 23:38:56.853716 [DATLAT]
2718 23:38:56.854114 Freq=1200, CH0 RK0
2719 23:38:56.854466
2720 23:38:56.856118 DATLAT Default: 0xd
2721 23:38:56.856584 0, 0xFFFF, sum = 0
2722 23:38:56.859865 1, 0xFFFF, sum = 0
2723 23:38:56.860439 2, 0xFFFF, sum = 0
2724 23:38:56.863217 3, 0xFFFF, sum = 0
2725 23:38:56.863691 4, 0xFFFF, sum = 0
2726 23:38:56.866066 5, 0xFFFF, sum = 0
2727 23:38:56.869722 6, 0xFFFF, sum = 0
2728 23:38:56.870290 7, 0xFFFF, sum = 0
2729 23:38:56.872809 8, 0xFFFF, sum = 0
2730 23:38:56.873296 9, 0xFFFF, sum = 0
2731 23:38:56.875980 10, 0xFFFF, sum = 0
2732 23:38:56.876454 11, 0xFFFF, sum = 0
2733 23:38:56.879395 12, 0x0, sum = 1
2734 23:38:56.879839 13, 0x0, sum = 2
2735 23:38:56.883070 14, 0x0, sum = 3
2736 23:38:56.883637 15, 0x0, sum = 4
2737 23:38:56.884016 best_step = 13
2738 23:38:56.884360
2739 23:38:56.886044 ==
2740 23:38:56.889636 Dram Type= 6, Freq= 0, CH_0, rank 0
2741 23:38:56.893136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2742 23:38:56.893742 ==
2743 23:38:56.894097 RX Vref Scan: 1
2744 23:38:56.894416
2745 23:38:56.895785 Set Vref Range= 32 -> 127
2746 23:38:56.896206
2747 23:38:56.899474 RX Vref 32 -> 127, step: 1
2748 23:38:56.900064
2749 23:38:56.903101 RX Delay -13 -> 252, step: 4
2750 23:38:56.903564
2751 23:38:56.906533 Set Vref, RX VrefLevel [Byte0]: 32
2752 23:38:56.909835 [Byte1]: 32
2753 23:38:56.910361
2754 23:38:56.913549 Set Vref, RX VrefLevel [Byte0]: 33
2755 23:38:56.916922 [Byte1]: 33
2756 23:38:56.917511
2757 23:38:56.919399 Set Vref, RX VrefLevel [Byte0]: 34
2758 23:38:56.922912 [Byte1]: 34
2759 23:38:56.927017
2760 23:38:56.927592 Set Vref, RX VrefLevel [Byte0]: 35
2761 23:38:56.930625 [Byte1]: 35
2762 23:38:56.935381
2763 23:38:56.935951 Set Vref, RX VrefLevel [Byte0]: 36
2764 23:38:56.938090 [Byte1]: 36
2765 23:38:56.942922
2766 23:38:56.943493 Set Vref, RX VrefLevel [Byte0]: 37
2767 23:38:56.945849 [Byte1]: 37
2768 23:38:56.951231
2769 23:38:56.951803 Set Vref, RX VrefLevel [Byte0]: 38
2770 23:38:56.954641 [Byte1]: 38
2771 23:38:56.958966
2772 23:38:56.959721 Set Vref, RX VrefLevel [Byte0]: 39
2773 23:38:56.961771 [Byte1]: 39
2774 23:38:56.966482
2775 23:38:56.966944 Set Vref, RX VrefLevel [Byte0]: 40
2776 23:38:56.969918 [Byte1]: 40
2777 23:38:56.974585
2778 23:38:56.977757 Set Vref, RX VrefLevel [Byte0]: 41
2779 23:38:56.978331 [Byte1]: 41
2780 23:38:56.982473
2781 23:38:56.982939 Set Vref, RX VrefLevel [Byte0]: 42
2782 23:38:56.985894 [Byte1]: 42
2783 23:38:56.990621
2784 23:38:56.991190 Set Vref, RX VrefLevel [Byte0]: 43
2785 23:38:56.993750 [Byte1]: 43
2786 23:38:56.997973
2787 23:38:56.998503 Set Vref, RX VrefLevel [Byte0]: 44
2788 23:38:57.001412 [Byte1]: 44
2789 23:38:57.005875
2790 23:38:57.006295 Set Vref, RX VrefLevel [Byte0]: 45
2791 23:38:57.009206 [Byte1]: 45
2792 23:38:57.013968
2793 23:38:57.014525 Set Vref, RX VrefLevel [Byte0]: 46
2794 23:38:57.017404 [Byte1]: 46
2795 23:38:57.022025
2796 23:38:57.022554 Set Vref, RX VrefLevel [Byte0]: 47
2797 23:38:57.025368 [Byte1]: 47
2798 23:38:57.029542
2799 23:38:57.030106 Set Vref, RX VrefLevel [Byte0]: 48
2800 23:38:57.032645 [Byte1]: 48
2801 23:38:57.037620
2802 23:38:57.038226 Set Vref, RX VrefLevel [Byte0]: 49
2803 23:38:57.040834 [Byte1]: 49
2804 23:38:57.045385
2805 23:38:57.046025 Set Vref, RX VrefLevel [Byte0]: 50
2806 23:38:57.049035 [Byte1]: 50
2807 23:38:57.053738
2808 23:38:57.054314 Set Vref, RX VrefLevel [Byte0]: 51
2809 23:38:57.056775 [Byte1]: 51
2810 23:38:57.061494
2811 23:38:57.062124 Set Vref, RX VrefLevel [Byte0]: 52
2812 23:38:57.064333 [Byte1]: 52
2813 23:38:57.069062
2814 23:38:57.069655 Set Vref, RX VrefLevel [Byte0]: 53
2815 23:38:57.072711 [Byte1]: 53
2816 23:38:57.076746
2817 23:38:57.077216 Set Vref, RX VrefLevel [Byte0]: 54
2818 23:38:57.080025 [Byte1]: 54
2819 23:38:57.085199
2820 23:38:57.085889 Set Vref, RX VrefLevel [Byte0]: 55
2821 23:38:57.088337 [Byte1]: 55
2822 23:38:57.092950
2823 23:38:57.093518 Set Vref, RX VrefLevel [Byte0]: 56
2824 23:38:57.096045 [Byte1]: 56
2825 23:38:57.100749
2826 23:38:57.101320 Set Vref, RX VrefLevel [Byte0]: 57
2827 23:38:57.104243 [Byte1]: 57
2828 23:38:57.108700
2829 23:38:57.109266 Set Vref, RX VrefLevel [Byte0]: 58
2830 23:38:57.112088 [Byte1]: 58
2831 23:38:57.116427
2832 23:38:57.116994 Set Vref, RX VrefLevel [Byte0]: 59
2833 23:38:57.119554 [Byte1]: 59
2834 23:38:57.124482
2835 23:38:57.125046 Set Vref, RX VrefLevel [Byte0]: 60
2836 23:38:57.127904 [Byte1]: 60
2837 23:38:57.132429
2838 23:38:57.133007 Set Vref, RX VrefLevel [Byte0]: 61
2839 23:38:57.135844 [Byte1]: 61
2840 23:38:57.139854
2841 23:38:57.140316 Set Vref, RX VrefLevel [Byte0]: 62
2842 23:38:57.143796 [Byte1]: 62
2843 23:38:57.148269
2844 23:38:57.148840 Set Vref, RX VrefLevel [Byte0]: 63
2845 23:38:57.151610 [Byte1]: 63
2846 23:38:57.155946
2847 23:38:57.156516 Set Vref, RX VrefLevel [Byte0]: 64
2848 23:38:57.159497 [Byte1]: 64
2849 23:38:57.163613
2850 23:38:57.164144 Set Vref, RX VrefLevel [Byte0]: 65
2851 23:38:57.167294 [Byte1]: 65
2852 23:38:57.171540
2853 23:38:57.174819 Set Vref, RX VrefLevel [Byte0]: 66
2854 23:38:57.175288 [Byte1]: 66
2855 23:38:57.179804
2856 23:38:57.180451 Set Vref, RX VrefLevel [Byte0]: 67
2857 23:38:57.182632 [Byte1]: 67
2858 23:38:57.187533
2859 23:38:57.188105 Set Vref, RX VrefLevel [Byte0]: 68
2860 23:38:57.190840 [Byte1]: 68
2861 23:38:57.195133
2862 23:38:57.195738 Set Vref, RX VrefLevel [Byte0]: 69
2863 23:38:57.198404 [Byte1]: 69
2864 23:38:57.203944
2865 23:38:57.204519 Final RX Vref Byte 0 = 54 to rank0
2866 23:38:57.206791 Final RX Vref Byte 1 = 55 to rank0
2867 23:38:57.209832 Final RX Vref Byte 0 = 54 to rank1
2868 23:38:57.213288 Final RX Vref Byte 1 = 55 to rank1==
2869 23:38:57.216745 Dram Type= 6, Freq= 0, CH_0, rank 0
2870 23:38:57.220324 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2871 23:38:57.223698 ==
2872 23:38:57.224268 DQS Delay:
2873 23:38:57.224872 DQS0 = 0, DQS1 = 0
2874 23:38:57.226460 DQM Delay:
2875 23:38:57.226925 DQM0 = 120, DQM1 = 113
2876 23:38:57.230002 DQ Delay:
2877 23:38:57.233786 DQ0 =120, DQ1 =120, DQ2 =118, DQ3 =118
2878 23:38:57.236348 DQ4 =122, DQ5 =112, DQ6 =126, DQ7 =126
2879 23:38:57.239760 DQ8 =100, DQ9 =102, DQ10 =116, DQ11 =106
2880 23:38:57.243357 DQ12 =120, DQ13 =118, DQ14 =126, DQ15 =122
2881 23:38:57.244122
2882 23:38:57.244556
2883 23:38:57.249667 [DQSOSCAuto] RK0, (LSB)MR18= 0x130c, (MSB)MR19= 0x404, tDQSOscB0 = 405 ps tDQSOscB1 = 402 ps
2884 23:38:57.253693 CH0 RK0: MR19=404, MR18=130C
2885 23:38:57.260555 CH0_RK0: MR19=0x404, MR18=0x130C, DQSOSC=402, MR23=63, INC=40, DEC=27
2886 23:38:57.261131
2887 23:38:57.263220 ----->DramcWriteLeveling(PI) begin...
2888 23:38:57.263692 ==
2889 23:38:57.266377 Dram Type= 6, Freq= 0, CH_0, rank 1
2890 23:38:57.270216 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2891 23:38:57.273796 ==
2892 23:38:57.274367 Write leveling (Byte 0): 36 => 36
2893 23:38:57.276644 Write leveling (Byte 1): 29 => 29
2894 23:38:57.280193 DramcWriteLeveling(PI) end<-----
2895 23:38:57.280676
2896 23:38:57.281279 ==
2897 23:38:57.283716 Dram Type= 6, Freq= 0, CH_0, rank 1
2898 23:38:57.289992 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2899 23:38:57.290569 ==
2900 23:38:57.290943 [Gating] SW mode calibration
2901 23:38:57.300055 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2902 23:38:57.303105 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2903 23:38:57.306400 0 15 0 | B1->B0 | 3131 2e2e | 1 1 | (1 1) (1 1)
2904 23:38:57.313250 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2905 23:38:57.316612 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2906 23:38:57.320037 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2907 23:38:57.326868 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2908 23:38:57.329795 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2909 23:38:57.333414 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2910 23:38:57.339542 0 15 28 | B1->B0 | 3131 2e2e | 0 0 | (0 1) (0 0)
2911 23:38:57.342762 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2912 23:38:57.346276 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2913 23:38:57.353041 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2914 23:38:57.356639 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2915 23:38:57.359805 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2916 23:38:57.366191 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2917 23:38:57.369955 1 0 24 | B1->B0 | 2525 2726 | 0 1 | (0 0) (0 0)
2918 23:38:57.373168 1 0 28 | B1->B0 | 3636 3434 | 1 1 | (0 0) (1 1)
2919 23:38:57.379753 1 1 0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
2920 23:38:57.383843 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2921 23:38:57.386657 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2922 23:38:57.393620 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2923 23:38:57.396595 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2924 23:38:57.400211 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2925 23:38:57.403486 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2926 23:38:57.409861 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2927 23:38:57.413719 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
2928 23:38:57.416793 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2929 23:38:57.423351 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2930 23:38:57.426717 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2931 23:38:57.430067 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2932 23:38:57.436553 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2933 23:38:57.439977 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2934 23:38:57.443640 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2935 23:38:57.449946 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2936 23:38:57.453482 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2937 23:38:57.456932 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2938 23:38:57.462912 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2939 23:38:57.466583 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2940 23:38:57.469977 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2941 23:38:57.476889 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2942 23:38:57.480131 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2943 23:38:57.483675 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2944 23:38:57.486774 Total UI for P1: 0, mck2ui 16
2945 23:38:57.489688 best dqsien dly found for B0: ( 1, 3, 28)
2946 23:38:57.493065 Total UI for P1: 0, mck2ui 16
2947 23:38:57.496435 best dqsien dly found for B1: ( 1, 3, 28)
2948 23:38:57.500342 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2949 23:38:57.503352 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2950 23:38:57.503926
2951 23:38:57.507210 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2952 23:38:57.513337 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2953 23:38:57.513962 [Gating] SW calibration Done
2954 23:38:57.514462 ==
2955 23:38:57.516909 Dram Type= 6, Freq= 0, CH_0, rank 1
2956 23:38:57.523271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2957 23:38:57.523810 ==
2958 23:38:57.524183 RX Vref Scan: 0
2959 23:38:57.524526
2960 23:38:57.526962 RX Vref 0 -> 0, step: 1
2961 23:38:57.527523
2962 23:38:57.529648 RX Delay -40 -> 252, step: 8
2963 23:38:57.533267 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2964 23:38:57.537058 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2965 23:38:57.539684 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2966 23:38:57.546514 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2967 23:38:57.549543 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2968 23:38:57.552975 iDelay=200, Bit 5, Center 119 (48 ~ 191) 144
2969 23:38:57.556333 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2970 23:38:57.560069 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2971 23:38:57.563197 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2972 23:38:57.570069 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
2973 23:38:57.573813 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2974 23:38:57.576737 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2975 23:38:57.579981 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2976 23:38:57.583409 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2977 23:38:57.590283 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2978 23:38:57.593475 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
2979 23:38:57.594095 ==
2980 23:38:57.596997 Dram Type= 6, Freq= 0, CH_0, rank 1
2981 23:38:57.600105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2982 23:38:57.600663 ==
2983 23:38:57.603164 DQS Delay:
2984 23:38:57.603567 DQS0 = 0, DQS1 = 0
2985 23:38:57.603935 DQM Delay:
2986 23:38:57.606382 DQM0 = 122, DQM1 = 112
2987 23:38:57.606842 DQ Delay:
2988 23:38:57.610135 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =119
2989 23:38:57.613410 DQ4 =127, DQ5 =119, DQ6 =127, DQ7 =127
2990 23:38:57.616372 DQ8 =99, DQ9 =99, DQ10 =111, DQ11 =107
2991 23:38:57.619746 DQ12 =115, DQ13 =123, DQ14 =123, DQ15 =123
2992 23:38:57.623617
2993 23:38:57.624081
2994 23:38:57.624447 ==
2995 23:38:57.626619 Dram Type= 6, Freq= 0, CH_0, rank 1
2996 23:38:57.630504 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2997 23:38:57.631078 ==
2998 23:38:57.631453
2999 23:38:57.631795
3000 23:38:57.633460 TX Vref Scan disable
3001 23:38:57.633973 == TX Byte 0 ==
3002 23:38:57.640016 Update DQ dly =856 (3 ,2, 24) DQ OEN =(2 ,7)
3003 23:38:57.643295 Update DQM dly =856 (3 ,2, 24) DQM OEN =(2 ,7)
3004 23:38:57.643865 == TX Byte 1 ==
3005 23:38:57.650048 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3006 23:38:57.653486 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3007 23:38:57.654113 ==
3008 23:38:57.657006 Dram Type= 6, Freq= 0, CH_0, rank 1
3009 23:38:57.660286 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3010 23:38:57.661027 ==
3011 23:38:57.673336 TX Vref=22, minBit 12, minWin=24, winSum=411
3012 23:38:57.676500 TX Vref=24, minBit 0, minWin=25, winSum=414
3013 23:38:57.679979 TX Vref=26, minBit 1, minWin=26, winSum=423
3014 23:38:57.683604 TX Vref=28, minBit 10, minWin=25, winSum=422
3015 23:38:57.686535 TX Vref=30, minBit 5, minWin=25, winSum=425
3016 23:38:57.693122 TX Vref=32, minBit 0, minWin=26, winSum=424
3017 23:38:57.696580 [TxChooseVref] Worse bit 0, Min win 26, Win sum 424, Final Vref 32
3018 23:38:57.697158
3019 23:38:57.699924 Final TX Range 1 Vref 32
3020 23:38:57.700494
3021 23:38:57.700864 ==
3022 23:38:57.703358 Dram Type= 6, Freq= 0, CH_0, rank 1
3023 23:38:57.706275 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3024 23:38:57.706788 ==
3025 23:38:57.709731
3026 23:38:57.710196
3027 23:38:57.710563 TX Vref Scan disable
3028 23:38:57.713684 == TX Byte 0 ==
3029 23:38:57.716739 Update DQ dly =856 (3 ,2, 24) DQ OEN =(2 ,7)
3030 23:38:57.719914 Update DQM dly =856 (3 ,2, 24) DQM OEN =(2 ,7)
3031 23:38:57.722875 == TX Byte 1 ==
3032 23:38:57.727056 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3033 23:38:57.729719 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3034 23:38:57.733731
3035 23:38:57.734309 [DATLAT]
3036 23:38:57.734685 Freq=1200, CH0 RK1
3037 23:38:57.735033
3038 23:38:57.736355 DATLAT Default: 0xd
3039 23:38:57.736820 0, 0xFFFF, sum = 0
3040 23:38:57.739982 1, 0xFFFF, sum = 0
3041 23:38:57.740578 2, 0xFFFF, sum = 0
3042 23:38:57.742854 3, 0xFFFF, sum = 0
3043 23:38:57.743478 4, 0xFFFF, sum = 0
3044 23:38:57.746324 5, 0xFFFF, sum = 0
3045 23:38:57.750436 6, 0xFFFF, sum = 0
3046 23:38:57.750909 7, 0xFFFF, sum = 0
3047 23:38:57.753176 8, 0xFFFF, sum = 0
3048 23:38:57.753683 9, 0xFFFF, sum = 0
3049 23:38:57.756671 10, 0xFFFF, sum = 0
3050 23:38:57.757248 11, 0xFFFF, sum = 0
3051 23:38:57.759848 12, 0x0, sum = 1
3052 23:38:57.760425 13, 0x0, sum = 2
3053 23:38:57.762973 14, 0x0, sum = 3
3054 23:38:57.763490 15, 0x0, sum = 4
3055 23:38:57.763893 best_step = 13
3056 23:38:57.764281
3057 23:38:57.766221 ==
3058 23:38:57.769657 Dram Type= 6, Freq= 0, CH_0, rank 1
3059 23:38:57.773344 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3060 23:38:57.773976 ==
3061 23:38:57.774358 RX Vref Scan: 0
3062 23:38:57.774807
3063 23:38:57.776660 RX Vref 0 -> 0, step: 1
3064 23:38:57.777231
3065 23:38:57.779924 RX Delay -13 -> 252, step: 4
3066 23:38:57.783796 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3067 23:38:57.786955 iDelay=195, Bit 1, Center 122 (55 ~ 190) 136
3068 23:38:57.793691 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3069 23:38:57.797295 iDelay=195, Bit 3, Center 118 (51 ~ 186) 136
3070 23:38:57.800423 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3071 23:38:57.803353 iDelay=195, Bit 5, Center 116 (51 ~ 182) 132
3072 23:38:57.807083 iDelay=195, Bit 6, Center 128 (63 ~ 194) 132
3073 23:38:57.813853 iDelay=195, Bit 7, Center 128 (63 ~ 194) 132
3074 23:38:57.816566 iDelay=195, Bit 8, Center 100 (35 ~ 166) 132
3075 23:38:57.819738 iDelay=195, Bit 9, Center 100 (35 ~ 166) 132
3076 23:38:57.823102 iDelay=195, Bit 10, Center 112 (47 ~ 178) 132
3077 23:38:57.826464 iDelay=195, Bit 11, Center 104 (39 ~ 170) 132
3078 23:38:57.833786 iDelay=195, Bit 12, Center 118 (55 ~ 182) 128
3079 23:38:57.836879 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3080 23:38:57.840295 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3081 23:38:57.843408 iDelay=195, Bit 15, Center 118 (55 ~ 182) 128
3082 23:38:57.844040 ==
3083 23:38:57.847011 Dram Type= 6, Freq= 0, CH_0, rank 1
3084 23:38:57.850147 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3085 23:38:57.853530 ==
3086 23:38:57.854042 DQS Delay:
3087 23:38:57.854413 DQS0 = 0, DQS1 = 0
3088 23:38:57.857088 DQM Delay:
3089 23:38:57.857549 DQM0 = 121, DQM1 = 111
3090 23:38:57.860195 DQ Delay:
3091 23:38:57.863816 DQ0 =118, DQ1 =122, DQ2 =118, DQ3 =118
3092 23:38:57.866787 DQ4 =122, DQ5 =116, DQ6 =128, DQ7 =128
3093 23:38:57.870496 DQ8 =100, DQ9 =100, DQ10 =112, DQ11 =104
3094 23:38:57.873452 DQ12 =118, DQ13 =118, DQ14 =122, DQ15 =118
3095 23:38:57.874066
3096 23:38:57.874442
3097 23:38:57.880898 [DQSOSCAuto] RK1, (LSB)MR18= 0xdef, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 405 ps
3098 23:38:57.883467 CH0 RK1: MR19=403, MR18=DEF
3099 23:38:57.890605 CH0_RK1: MR19=0x403, MR18=0xDEF, DQSOSC=405, MR23=63, INC=39, DEC=26
3100 23:38:57.893750 [RxdqsGatingPostProcess] freq 1200
3101 23:38:57.900399 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3102 23:38:57.904375 best DQS0 dly(2T, 0.5T) = (0, 11)
3103 23:38:57.904937 best DQS1 dly(2T, 0.5T) = (0, 12)
3104 23:38:57.906647 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3105 23:38:57.910240 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3106 23:38:57.913767 best DQS0 dly(2T, 0.5T) = (0, 11)
3107 23:38:57.916879 best DQS1 dly(2T, 0.5T) = (0, 11)
3108 23:38:57.920297 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3109 23:38:57.923444 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3110 23:38:57.926866 Pre-setting of DQS Precalculation
3111 23:38:57.933265 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3112 23:38:57.933845 ==
3113 23:38:57.936521 Dram Type= 6, Freq= 0, CH_1, rank 0
3114 23:38:57.940129 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3115 23:38:57.940721 ==
3116 23:38:57.947048 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3117 23:38:57.949688 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3118 23:38:57.959735 [CA 0] Center 37 (7~68) winsize 62
3119 23:38:57.962731 [CA 1] Center 37 (7~68) winsize 62
3120 23:38:57.966602 [CA 2] Center 35 (5~65) winsize 61
3121 23:38:57.969746 [CA 3] Center 34 (4~65) winsize 62
3122 23:38:57.973077 [CA 4] Center 34 (5~64) winsize 60
3123 23:38:57.976101 [CA 5] Center 33 (3~63) winsize 61
3124 23:38:57.976666
3125 23:38:57.979355 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3126 23:38:57.979816
3127 23:38:57.983215 [CATrainingPosCal] consider 1 rank data
3128 23:38:57.986370 u2DelayCellTimex100 = 270/100 ps
3129 23:38:57.989439 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3130 23:38:57.992882 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3131 23:38:57.999530 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3132 23:38:58.003037 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3133 23:38:58.006227 CA4 delay=34 (5~64),Diff = 1 PI (4 cell)
3134 23:38:58.009769 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3135 23:38:58.010335
3136 23:38:58.012989 CA PerBit enable=1, Macro0, CA PI delay=33
3137 23:38:58.013553
3138 23:38:58.015932 [CBTSetCACLKResult] CA Dly = 33
3139 23:38:58.016486 CS Dly: 7 (0~38)
3140 23:38:58.019445 ==
3141 23:38:58.019905 Dram Type= 6, Freq= 0, CH_1, rank 1
3142 23:38:58.025907 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3143 23:38:58.026370 ==
3144 23:38:58.030164 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3145 23:38:58.035704 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3146 23:38:58.045392 [CA 0] Center 37 (7~68) winsize 62
3147 23:38:58.048919 [CA 1] Center 37 (7~68) winsize 62
3148 23:38:58.051675 [CA 2] Center 35 (5~66) winsize 62
3149 23:38:58.054864 [CA 3] Center 34 (4~65) winsize 62
3150 23:38:58.058356 [CA 4] Center 34 (4~65) winsize 62
3151 23:38:58.062042 [CA 5] Center 34 (4~64) winsize 61
3152 23:38:58.062604
3153 23:38:58.065099 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3154 23:38:58.065558
3155 23:38:58.068344 [CATrainingPosCal] consider 2 rank data
3156 23:38:58.072412 u2DelayCellTimex100 = 270/100 ps
3157 23:38:58.074919 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3158 23:38:58.078631 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3159 23:38:58.085750 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3160 23:38:58.088865 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3161 23:38:58.092727 CA4 delay=34 (5~64),Diff = 1 PI (4 cell)
3162 23:38:58.095670 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3163 23:38:58.096230
3164 23:38:58.098818 CA PerBit enable=1, Macro0, CA PI delay=33
3165 23:38:58.099383
3166 23:38:58.102316 [CBTSetCACLKResult] CA Dly = 33
3167 23:38:58.102888 CS Dly: 8 (0~40)
3168 23:38:58.103254
3169 23:38:58.105307 ----->DramcWriteLeveling(PI) begin...
3170 23:38:58.108358 ==
3171 23:38:58.108818 Dram Type= 6, Freq= 0, CH_1, rank 0
3172 23:38:58.115059 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3173 23:38:58.115628 ==
3174 23:38:58.119117 Write leveling (Byte 0): 27 => 27
3175 23:38:58.122041 Write leveling (Byte 1): 27 => 27
3176 23:38:58.125206 DramcWriteLeveling(PI) end<-----
3177 23:38:58.125820
3178 23:38:58.126187 ==
3179 23:38:58.128360 Dram Type= 6, Freq= 0, CH_1, rank 0
3180 23:38:58.131829 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3181 23:38:58.132391 ==
3182 23:38:58.134807 [Gating] SW mode calibration
3183 23:38:58.141510 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3184 23:38:58.145434 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3185 23:38:58.151735 0 15 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
3186 23:38:58.155482 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3187 23:38:58.158567 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3188 23:38:58.165099 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3189 23:38:58.168622 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3190 23:38:58.171771 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3191 23:38:58.178341 0 15 24 | B1->B0 | 3434 2f2f | 0 0 | (0 1) (0 0)
3192 23:38:58.181553 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
3193 23:38:58.184854 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3194 23:38:58.191820 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3195 23:38:58.195416 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3196 23:38:58.198853 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3197 23:38:58.205297 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3198 23:38:58.208525 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3199 23:38:58.212019 1 0 24 | B1->B0 | 3131 4242 | 1 0 | (0 0) (0 0)
3200 23:38:58.218727 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3201 23:38:58.222134 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3202 23:38:58.225856 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3203 23:38:58.229166 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3204 23:38:58.235909 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3205 23:38:58.239267 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3206 23:38:58.241902 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3207 23:38:58.248752 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3208 23:38:58.252369 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3209 23:38:58.256331 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3210 23:38:58.262103 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3211 23:38:58.265662 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3212 23:38:58.268948 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3213 23:38:58.275542 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3214 23:38:58.278948 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3215 23:38:58.282117 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3216 23:38:58.288892 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3217 23:38:58.292095 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3218 23:38:58.295410 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3219 23:38:58.301776 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3220 23:38:58.305491 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3221 23:38:58.308661 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3222 23:38:58.311865 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3223 23:38:58.318322 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3224 23:38:58.322168 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3225 23:38:58.325537 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3226 23:38:58.328799 Total UI for P1: 0, mck2ui 16
3227 23:38:58.331739 best dqsien dly found for B0: ( 1, 3, 26)
3228 23:38:58.335239 Total UI for P1: 0, mck2ui 16
3229 23:38:58.338497 best dqsien dly found for B1: ( 1, 3, 26)
3230 23:38:58.341723 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3231 23:38:58.345167 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3232 23:38:58.345640
3233 23:38:58.351744 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3234 23:38:58.355320 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3235 23:38:58.358658 [Gating] SW calibration Done
3236 23:38:58.359074 ==
3237 23:38:58.361922 Dram Type= 6, Freq= 0, CH_1, rank 0
3238 23:38:58.365073 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3239 23:38:58.365491 ==
3240 23:38:58.365874 RX Vref Scan: 0
3241 23:38:58.366187
3242 23:38:58.368754 RX Vref 0 -> 0, step: 1
3243 23:38:58.369168
3244 23:38:58.372288 RX Delay -40 -> 252, step: 8
3245 23:38:58.375170 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3246 23:38:58.378229 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3247 23:38:58.385570 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3248 23:38:58.388801 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3249 23:38:58.392131 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3250 23:38:58.395340 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3251 23:38:58.398826 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3252 23:38:58.402087 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3253 23:38:58.409120 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3254 23:38:58.412014 iDelay=200, Bit 9, Center 103 (40 ~ 167) 128
3255 23:38:58.415488 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3256 23:38:58.418947 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3257 23:38:58.422057 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3258 23:38:58.428907 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3259 23:38:58.432036 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3260 23:38:58.435677 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3261 23:38:58.436190 ==
3262 23:38:58.438932 Dram Type= 6, Freq= 0, CH_1, rank 0
3263 23:38:58.442478 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3264 23:38:58.442997 ==
3265 23:38:58.446087 DQS Delay:
3266 23:38:58.446601 DQS0 = 0, DQS1 = 0
3267 23:38:58.448468 DQM Delay:
3268 23:38:58.448882 DQM0 = 119, DQM1 = 116
3269 23:38:58.452719 DQ Delay:
3270 23:38:58.455891 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3271 23:38:58.459190 DQ4 =119, DQ5 =127, DQ6 =127, DQ7 =119
3272 23:38:58.462500 DQ8 =103, DQ9 =103, DQ10 =115, DQ11 =111
3273 23:38:58.465658 DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123
3274 23:38:58.466185
3275 23:38:58.466520
3276 23:38:58.466831 ==
3277 23:38:58.468707 Dram Type= 6, Freq= 0, CH_1, rank 0
3278 23:38:58.472233 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3279 23:38:58.472759 ==
3280 23:38:58.473094
3281 23:38:58.473402
3282 23:38:58.475674 TX Vref Scan disable
3283 23:38:58.478701 == TX Byte 0 ==
3284 23:38:58.482396 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3285 23:38:58.485361 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3286 23:38:58.489227 == TX Byte 1 ==
3287 23:38:58.492100 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3288 23:38:58.495509 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3289 23:38:58.496029 ==
3290 23:38:58.498929 Dram Type= 6, Freq= 0, CH_1, rank 0
3291 23:38:58.502318 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3292 23:38:58.505535 ==
3293 23:38:58.515242 TX Vref=22, minBit 9, minWin=24, winSum=410
3294 23:38:58.518431 TX Vref=24, minBit 1, minWin=24, winSum=415
3295 23:38:58.521944 TX Vref=26, minBit 1, minWin=26, winSum=421
3296 23:38:58.525197 TX Vref=28, minBit 10, minWin=25, winSum=424
3297 23:38:58.528265 TX Vref=30, minBit 2, minWin=26, winSum=428
3298 23:38:58.535148 TX Vref=32, minBit 0, minWin=26, winSum=427
3299 23:38:58.538227 [TxChooseVref] Worse bit 2, Min win 26, Win sum 428, Final Vref 30
3300 23:38:58.538647
3301 23:38:58.541690 Final TX Range 1 Vref 30
3302 23:38:58.542109
3303 23:38:58.542442 ==
3304 23:38:58.544851 Dram Type= 6, Freq= 0, CH_1, rank 0
3305 23:38:58.548604 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3306 23:38:58.549025 ==
3307 23:38:58.551621
3308 23:38:58.552033
3309 23:38:58.552361 TX Vref Scan disable
3310 23:38:58.555569 == TX Byte 0 ==
3311 23:38:58.558668 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3312 23:38:58.561658 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3313 23:38:58.565807 == TX Byte 1 ==
3314 23:38:58.568895 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3315 23:38:58.571979 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3316 23:38:58.572503
3317 23:38:58.576134 [DATLAT]
3318 23:38:58.576662 Freq=1200, CH1 RK0
3319 23:38:58.577000
3320 23:38:58.578428 DATLAT Default: 0xd
3321 23:38:58.578844 0, 0xFFFF, sum = 0
3322 23:38:58.581817 1, 0xFFFF, sum = 0
3323 23:38:58.582239 2, 0xFFFF, sum = 0
3324 23:38:58.585207 3, 0xFFFF, sum = 0
3325 23:38:58.585656 4, 0xFFFF, sum = 0
3326 23:38:58.588694 5, 0xFFFF, sum = 0
3327 23:38:58.589219 6, 0xFFFF, sum = 0
3328 23:38:58.592230 7, 0xFFFF, sum = 0
3329 23:38:58.592649 8, 0xFFFF, sum = 0
3330 23:38:58.595749 9, 0xFFFF, sum = 0
3331 23:38:58.598777 10, 0xFFFF, sum = 0
3332 23:38:58.599199 11, 0xFFFF, sum = 0
3333 23:38:58.602357 12, 0x0, sum = 1
3334 23:38:58.602879 13, 0x0, sum = 2
3335 23:38:58.603219 14, 0x0, sum = 3
3336 23:38:58.605836 15, 0x0, sum = 4
3337 23:38:58.606256 best_step = 13
3338 23:38:58.606582
3339 23:38:58.606884 ==
3340 23:38:58.608718 Dram Type= 6, Freq= 0, CH_1, rank 0
3341 23:38:58.615683 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3342 23:38:58.616204 ==
3343 23:38:58.616541 RX Vref Scan: 1
3344 23:38:58.616848
3345 23:38:58.618390 Set Vref Range= 32 -> 127
3346 23:38:58.618864
3347 23:38:58.622274 RX Vref 32 -> 127, step: 1
3348 23:38:58.622685
3349 23:38:58.625331 RX Delay -5 -> 252, step: 4
3350 23:38:58.625779
3351 23:38:58.628977 Set Vref, RX VrefLevel [Byte0]: 32
3352 23:38:58.629397 [Byte1]: 32
3353 23:38:58.633466
3354 23:38:58.633910 Set Vref, RX VrefLevel [Byte0]: 33
3355 23:38:58.637185 [Byte1]: 33
3356 23:38:58.641065
3357 23:38:58.641617 Set Vref, RX VrefLevel [Byte0]: 34
3358 23:38:58.644291 [Byte1]: 34
3359 23:38:58.649364
3360 23:38:58.649826 Set Vref, RX VrefLevel [Byte0]: 35
3361 23:38:58.652117 [Byte1]: 35
3362 23:38:58.656895
3363 23:38:58.657304 Set Vref, RX VrefLevel [Byte0]: 36
3364 23:38:58.659870 [Byte1]: 36
3365 23:38:58.664516
3366 23:38:58.664926 Set Vref, RX VrefLevel [Byte0]: 37
3367 23:38:58.668295 [Byte1]: 37
3368 23:38:58.673115
3369 23:38:58.673655 Set Vref, RX VrefLevel [Byte0]: 38
3370 23:38:58.676576 [Byte1]: 38
3371 23:38:58.680564
3372 23:38:58.681094 Set Vref, RX VrefLevel [Byte0]: 39
3373 23:38:58.683927 [Byte1]: 39
3374 23:38:58.688380
3375 23:38:58.688891 Set Vref, RX VrefLevel [Byte0]: 40
3376 23:38:58.691690 [Byte1]: 40
3377 23:38:58.696102
3378 23:38:58.696613 Set Vref, RX VrefLevel [Byte0]: 41
3379 23:38:58.699619 [Byte1]: 41
3380 23:38:58.704116
3381 23:38:58.704645 Set Vref, RX VrefLevel [Byte0]: 42
3382 23:38:58.707185 [Byte1]: 42
3383 23:38:58.712549
3384 23:38:58.713102 Set Vref, RX VrefLevel [Byte0]: 43
3385 23:38:58.715741 [Byte1]: 43
3386 23:38:58.719525
3387 23:38:58.719980 Set Vref, RX VrefLevel [Byte0]: 44
3388 23:38:58.723065 [Byte1]: 44
3389 23:38:58.727535
3390 23:38:58.728096 Set Vref, RX VrefLevel [Byte0]: 45
3391 23:38:58.730615 [Byte1]: 45
3392 23:38:58.735657
3393 23:38:58.736215 Set Vref, RX VrefLevel [Byte0]: 46
3394 23:38:58.738733 [Byte1]: 46
3395 23:38:58.743533
3396 23:38:58.744089 Set Vref, RX VrefLevel [Byte0]: 47
3397 23:38:58.746565 [Byte1]: 47
3398 23:38:58.751452
3399 23:38:58.751946 Set Vref, RX VrefLevel [Byte0]: 48
3400 23:38:58.754714 [Byte1]: 48
3401 23:38:58.759179
3402 23:38:58.759725 Set Vref, RX VrefLevel [Byte0]: 49
3403 23:38:58.762246 [Byte1]: 49
3404 23:38:58.766817
3405 23:38:58.767269 Set Vref, RX VrefLevel [Byte0]: 50
3406 23:38:58.770247 [Byte1]: 50
3407 23:38:58.775367
3408 23:38:58.775919 Set Vref, RX VrefLevel [Byte0]: 51
3409 23:38:58.778033 [Byte1]: 51
3410 23:38:58.782575
3411 23:38:58.783153 Set Vref, RX VrefLevel [Byte0]: 52
3412 23:38:58.786115 [Byte1]: 52
3413 23:38:58.790105
3414 23:38:58.790556 Set Vref, RX VrefLevel [Byte0]: 53
3415 23:38:58.794002 [Byte1]: 53
3416 23:38:58.798397
3417 23:38:58.798951 Set Vref, RX VrefLevel [Byte0]: 54
3418 23:38:58.801754 [Byte1]: 54
3419 23:38:58.806501
3420 23:38:58.807053 Set Vref, RX VrefLevel [Byte0]: 55
3421 23:38:58.809387 [Byte1]: 55
3422 23:38:58.814323
3423 23:38:58.814877 Set Vref, RX VrefLevel [Byte0]: 56
3424 23:38:58.818014 [Byte1]: 56
3425 23:38:58.822238
3426 23:38:58.822798 Set Vref, RX VrefLevel [Byte0]: 57
3427 23:38:58.825191 [Byte1]: 57
3428 23:38:58.829971
3429 23:38:58.830521 Set Vref, RX VrefLevel [Byte0]: 58
3430 23:38:58.833085 [Byte1]: 58
3431 23:38:58.837690
3432 23:38:58.838249 Set Vref, RX VrefLevel [Byte0]: 59
3433 23:38:58.841283 [Byte1]: 59
3434 23:38:58.845507
3435 23:38:58.846117 Set Vref, RX VrefLevel [Byte0]: 60
3436 23:38:58.848775 [Byte1]: 60
3437 23:38:58.853346
3438 23:38:58.853906 Set Vref, RX VrefLevel [Byte0]: 61
3439 23:38:58.856726 [Byte1]: 61
3440 23:38:58.861090
3441 23:38:58.861748 Set Vref, RX VrefLevel [Byte0]: 62
3442 23:38:58.864531 [Byte1]: 62
3443 23:38:58.868950
3444 23:38:58.869527 Set Vref, RX VrefLevel [Byte0]: 63
3445 23:38:58.872489 [Byte1]: 63
3446 23:38:58.876796
3447 23:38:58.877351 Set Vref, RX VrefLevel [Byte0]: 64
3448 23:38:58.880292 [Byte1]: 64
3449 23:38:58.884603
3450 23:38:58.885059 Set Vref, RX VrefLevel [Byte0]: 65
3451 23:38:58.888071 [Byte1]: 65
3452 23:38:58.892619
3453 23:38:58.893175 Set Vref, RX VrefLevel [Byte0]: 66
3454 23:38:58.896189 [Byte1]: 66
3455 23:38:58.900182
3456 23:38:58.900637 Set Vref, RX VrefLevel [Byte0]: 67
3457 23:38:58.903880 [Byte1]: 67
3458 23:38:58.908429
3459 23:38:58.908989 Final RX Vref Byte 0 = 55 to rank0
3460 23:38:58.911290 Final RX Vref Byte 1 = 53 to rank0
3461 23:38:58.914742 Final RX Vref Byte 0 = 55 to rank1
3462 23:38:58.918342 Final RX Vref Byte 1 = 53 to rank1==
3463 23:38:58.921888 Dram Type= 6, Freq= 0, CH_1, rank 0
3464 23:38:58.928431 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3465 23:38:58.929007 ==
3466 23:38:58.929376 DQS Delay:
3467 23:38:58.929743 DQS0 = 0, DQS1 = 0
3468 23:38:58.932297 DQM Delay:
3469 23:38:58.932850 DQM0 = 120, DQM1 = 117
3470 23:38:58.935277 DQ Delay:
3471 23:38:58.938572 DQ0 =124, DQ1 =114, DQ2 =110, DQ3 =116
3472 23:38:58.942195 DQ4 =120, DQ5 =128, DQ6 =128, DQ7 =120
3473 23:38:58.945273 DQ8 =104, DQ9 =108, DQ10 =118, DQ11 =112
3474 23:38:58.948607 DQ12 =126, DQ13 =124, DQ14 =124, DQ15 =126
3475 23:38:58.949192
3476 23:38:58.949633
3477 23:38:58.954973 [DQSOSCAuto] RK0, (LSB)MR18= 0xfe11, (MSB)MR19= 0x304, tDQSOscB0 = 403 ps tDQSOscB1 = 410 ps
3478 23:38:58.958359 CH1 RK0: MR19=304, MR18=FE11
3479 23:38:58.965124 CH1_RK0: MR19=0x304, MR18=0xFE11, DQSOSC=403, MR23=63, INC=40, DEC=26
3480 23:38:58.965774
3481 23:38:58.968077 ----->DramcWriteLeveling(PI) begin...
3482 23:38:58.968539 ==
3483 23:38:58.972276 Dram Type= 6, Freq= 0, CH_1, rank 1
3484 23:38:58.975085 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3485 23:38:58.978665 ==
3486 23:38:58.979129 Write leveling (Byte 0): 25 => 25
3487 23:38:58.981709 Write leveling (Byte 1): 28 => 28
3488 23:38:58.985045 DramcWriteLeveling(PI) end<-----
3489 23:38:58.985501
3490 23:38:58.985889 ==
3491 23:38:58.988433 Dram Type= 6, Freq= 0, CH_1, rank 1
3492 23:38:58.995096 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3493 23:38:58.995658 ==
3494 23:38:58.996030 [Gating] SW mode calibration
3495 23:38:59.005363 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3496 23:38:59.008296 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3497 23:38:59.011645 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3498 23:38:59.018710 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3499 23:38:59.022047 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3500 23:38:59.025349 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3501 23:38:59.032365 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3502 23:38:59.035695 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
3503 23:38:59.038889 0 15 24 | B1->B0 | 2e2e 3434 | 0 1 | (0 1) (1 1)
3504 23:38:59.045809 0 15 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 0)
3505 23:38:59.048795 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3506 23:38:59.051941 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3507 23:38:59.058651 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3508 23:38:59.062561 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3509 23:38:59.065538 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3510 23:38:59.072253 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3511 23:38:59.075569 1 0 24 | B1->B0 | 4040 2b2a | 1 1 | (0 0) (0 0)
3512 23:38:59.078397 1 0 28 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
3513 23:38:59.081619 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3514 23:38:59.088656 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3515 23:38:59.091822 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3516 23:38:59.094948 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3517 23:38:59.101985 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3518 23:38:59.105645 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3519 23:38:59.108397 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3520 23:38:59.115515 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3521 23:38:59.118544 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3522 23:38:59.121782 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3523 23:38:59.128491 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3524 23:38:59.131799 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3525 23:38:59.135204 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3526 23:38:59.141258 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3527 23:38:59.144955 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3528 23:38:59.148331 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3529 23:38:59.154705 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3530 23:38:59.158147 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3531 23:38:59.161555 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3532 23:38:59.168391 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3533 23:38:59.171386 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3534 23:38:59.175141 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3535 23:38:59.181703 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3536 23:38:59.184785 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3537 23:38:59.188531 Total UI for P1: 0, mck2ui 16
3538 23:38:59.191345 best dqsien dly found for B1: ( 1, 3, 24)
3539 23:38:59.194632 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3540 23:38:59.198307 Total UI for P1: 0, mck2ui 16
3541 23:38:59.201118 best dqsien dly found for B0: ( 1, 3, 26)
3542 23:38:59.204499 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3543 23:38:59.207750 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3544 23:38:59.208213
3545 23:38:59.211365 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3546 23:38:59.218290 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3547 23:38:59.218845 [Gating] SW calibration Done
3548 23:38:59.221059 ==
3549 23:38:59.221515 Dram Type= 6, Freq= 0, CH_1, rank 1
3550 23:38:59.227799 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3551 23:38:59.228361 ==
3552 23:38:59.228730 RX Vref Scan: 0
3553 23:38:59.229075
3554 23:38:59.231069 RX Vref 0 -> 0, step: 1
3555 23:38:59.231530
3556 23:38:59.234184 RX Delay -40 -> 252, step: 8
3557 23:38:59.238012 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3558 23:38:59.241200 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3559 23:38:59.244420 iDelay=200, Bit 2, Center 111 (48 ~ 175) 128
3560 23:38:59.250917 iDelay=200, Bit 3, Center 119 (56 ~ 183) 128
3561 23:38:59.255017 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3562 23:38:59.257784 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3563 23:38:59.261390 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3564 23:38:59.264366 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3565 23:38:59.271311 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3566 23:38:59.274360 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3567 23:38:59.278253 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3568 23:38:59.280866 iDelay=200, Bit 11, Center 115 (48 ~ 183) 136
3569 23:38:59.284868 iDelay=200, Bit 12, Center 127 (56 ~ 199) 144
3570 23:38:59.291562 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3571 23:38:59.294400 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3572 23:38:59.297842 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3573 23:38:59.298408 ==
3574 23:38:59.301443 Dram Type= 6, Freq= 0, CH_1, rank 1
3575 23:38:59.305000 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3576 23:38:59.305568 ==
3577 23:38:59.308205 DQS Delay:
3578 23:38:59.308798 DQS0 = 0, DQS1 = 0
3579 23:38:59.311206 DQM Delay:
3580 23:38:59.311662 DQM0 = 120, DQM1 = 117
3581 23:38:59.314305 DQ Delay:
3582 23:38:59.317953 DQ0 =123, DQ1 =115, DQ2 =111, DQ3 =119
3583 23:38:59.320816 DQ4 =115, DQ5 =131, DQ6 =131, DQ7 =119
3584 23:38:59.324253 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =115
3585 23:38:59.327858 DQ12 =127, DQ13 =127, DQ14 =123, DQ15 =123
3586 23:38:59.328422
3587 23:38:59.328784
3588 23:38:59.329166 ==
3589 23:38:59.330702 Dram Type= 6, Freq= 0, CH_1, rank 1
3590 23:38:59.334338 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3591 23:38:59.334801 ==
3592 23:38:59.335164
3593 23:38:59.335502
3594 23:38:59.337507 TX Vref Scan disable
3595 23:38:59.341178 == TX Byte 0 ==
3596 23:38:59.344380 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3597 23:38:59.347637 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3598 23:38:59.350728 == TX Byte 1 ==
3599 23:38:59.354252 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3600 23:38:59.357640 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3601 23:38:59.358105 ==
3602 23:38:59.361205 Dram Type= 6, Freq= 0, CH_1, rank 1
3603 23:38:59.367029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3604 23:38:59.367646 ==
3605 23:38:59.377675 TX Vref=22, minBit 9, minWin=25, winSum=415
3606 23:38:59.381063 TX Vref=24, minBit 1, minWin=26, winSum=425
3607 23:38:59.383903 TX Vref=26, minBit 10, minWin=25, winSum=423
3608 23:38:59.387477 TX Vref=28, minBit 10, minWin=25, winSum=428
3609 23:38:59.390695 TX Vref=30, minBit 2, minWin=26, winSum=430
3610 23:38:59.397553 TX Vref=32, minBit 1, minWin=26, winSum=428
3611 23:38:59.400976 [TxChooseVref] Worse bit 2, Min win 26, Win sum 430, Final Vref 30
3612 23:38:59.401407
3613 23:38:59.404956 Final TX Range 1 Vref 30
3614 23:38:59.405489
3615 23:38:59.405977 ==
3616 23:38:59.408294 Dram Type= 6, Freq= 0, CH_1, rank 1
3617 23:38:59.411095 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3618 23:38:59.411532 ==
3619 23:38:59.414353
3620 23:38:59.414786
3621 23:38:59.415225 TX Vref Scan disable
3622 23:38:59.418282 == TX Byte 0 ==
3623 23:38:59.421116 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3624 23:38:59.424592 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3625 23:38:59.427939 == TX Byte 1 ==
3626 23:38:59.431416 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3627 23:38:59.434633 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3628 23:38:59.435162
3629 23:38:59.437348 [DATLAT]
3630 23:38:59.437832 Freq=1200, CH1 RK1
3631 23:38:59.438274
3632 23:38:59.441092 DATLAT Default: 0xd
3633 23:38:59.441658 0, 0xFFFF, sum = 0
3634 23:38:59.444354 1, 0xFFFF, sum = 0
3635 23:38:59.444891 2, 0xFFFF, sum = 0
3636 23:38:59.447512 3, 0xFFFF, sum = 0
3637 23:38:59.448053 4, 0xFFFF, sum = 0
3638 23:38:59.450957 5, 0xFFFF, sum = 0
3639 23:38:59.453933 6, 0xFFFF, sum = 0
3640 23:38:59.454372 7, 0xFFFF, sum = 0
3641 23:38:59.457467 8, 0xFFFF, sum = 0
3642 23:38:59.457953 9, 0xFFFF, sum = 0
3643 23:38:59.460959 10, 0xFFFF, sum = 0
3644 23:38:59.461487 11, 0xFFFF, sum = 0
3645 23:38:59.464256 12, 0x0, sum = 1
3646 23:38:59.464703 13, 0x0, sum = 2
3647 23:38:59.467603 14, 0x0, sum = 3
3648 23:38:59.468024 15, 0x0, sum = 4
3649 23:38:59.468396 best_step = 13
3650 23:38:59.468705
3651 23:38:59.470577 ==
3652 23:38:59.473875 Dram Type= 6, Freq= 0, CH_1, rank 1
3653 23:38:59.477345 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3654 23:38:59.477924 ==
3655 23:38:59.478267 RX Vref Scan: 0
3656 23:38:59.478576
3657 23:38:59.480561 RX Vref 0 -> 0, step: 1
3658 23:38:59.480975
3659 23:38:59.483831 RX Delay -5 -> 252, step: 4
3660 23:38:59.487285 iDelay=195, Bit 0, Center 122 (59 ~ 186) 128
3661 23:38:59.493654 iDelay=195, Bit 1, Center 116 (55 ~ 178) 124
3662 23:38:59.496962 iDelay=195, Bit 2, Center 110 (51 ~ 170) 120
3663 23:38:59.501118 iDelay=195, Bit 3, Center 116 (59 ~ 174) 116
3664 23:38:59.503796 iDelay=195, Bit 4, Center 116 (55 ~ 178) 124
3665 23:38:59.507586 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3666 23:38:59.514247 iDelay=195, Bit 6, Center 130 (67 ~ 194) 128
3667 23:38:59.517381 iDelay=195, Bit 7, Center 120 (59 ~ 182) 124
3668 23:38:59.520873 iDelay=195, Bit 8, Center 106 (47 ~ 166) 120
3669 23:38:59.524001 iDelay=195, Bit 9, Center 108 (47 ~ 170) 124
3670 23:38:59.526861 iDelay=195, Bit 10, Center 118 (55 ~ 182) 128
3671 23:38:59.534017 iDelay=195, Bit 11, Center 112 (51 ~ 174) 124
3672 23:38:59.537224 iDelay=195, Bit 12, Center 126 (63 ~ 190) 128
3673 23:38:59.540745 iDelay=195, Bit 13, Center 124 (67 ~ 182) 116
3674 23:38:59.543805 iDelay=195, Bit 14, Center 122 (63 ~ 182) 120
3675 23:38:59.547853 iDelay=195, Bit 15, Center 128 (67 ~ 190) 124
3676 23:38:59.550690 ==
3677 23:38:59.553643 Dram Type= 6, Freq= 0, CH_1, rank 1
3678 23:38:59.556962 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3679 23:38:59.557544 ==
3680 23:38:59.557970 DQS Delay:
3681 23:38:59.559990 DQS0 = 0, DQS1 = 0
3682 23:38:59.560445 DQM Delay:
3683 23:38:59.564030 DQM0 = 120, DQM1 = 118
3684 23:38:59.564591 DQ Delay:
3685 23:38:59.566738 DQ0 =122, DQ1 =116, DQ2 =110, DQ3 =116
3686 23:38:59.569961 DQ4 =116, DQ5 =130, DQ6 =130, DQ7 =120
3687 23:38:59.574181 DQ8 =106, DQ9 =108, DQ10 =118, DQ11 =112
3688 23:38:59.577365 DQ12 =126, DQ13 =124, DQ14 =122, DQ15 =128
3689 23:38:59.577983
3690 23:38:59.578353
3691 23:38:59.586631 [DQSOSCAuto] RK1, (LSB)MR18= 0xeea, (MSB)MR19= 0x403, tDQSOscB0 = 419 ps tDQSOscB1 = 404 ps
3692 23:38:59.587187 CH1 RK1: MR19=403, MR18=EEA
3693 23:38:59.593751 CH1_RK1: MR19=0x403, MR18=0xEEA, DQSOSC=404, MR23=63, INC=40, DEC=26
3694 23:38:59.597129 [RxdqsGatingPostProcess] freq 1200
3695 23:38:59.603571 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3696 23:38:59.606883 best DQS0 dly(2T, 0.5T) = (0, 11)
3697 23:38:59.610113 best DQS1 dly(2T, 0.5T) = (0, 11)
3698 23:38:59.613529 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3699 23:38:59.617097 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3700 23:38:59.620241 best DQS0 dly(2T, 0.5T) = (0, 11)
3701 23:38:59.623208 best DQS1 dly(2T, 0.5T) = (0, 11)
3702 23:38:59.626484 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3703 23:38:59.630162 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3704 23:38:59.630729 Pre-setting of DQS Precalculation
3705 23:38:59.637300 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3706 23:38:59.643616 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3707 23:38:59.649879 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3708 23:38:59.650457
3709 23:38:59.650824
3710 23:38:59.652948 [Calibration Summary] 2400 Mbps
3711 23:38:59.656430 CH 0, Rank 0
3712 23:38:59.656889 SW Impedance : PASS
3713 23:38:59.659621 DUTY Scan : NO K
3714 23:38:59.663487 ZQ Calibration : PASS
3715 23:38:59.664063 Jitter Meter : NO K
3716 23:38:59.666569 CBT Training : PASS
3717 23:38:59.669729 Write leveling : PASS
3718 23:38:59.670416 RX DQS gating : PASS
3719 23:38:59.673230 RX DQ/DQS(RDDQC) : PASS
3720 23:38:59.673913 TX DQ/DQS : PASS
3721 23:38:59.676364 RX DATLAT : PASS
3722 23:38:59.679391 RX DQ/DQS(Engine): PASS
3723 23:38:59.679851 TX OE : NO K
3724 23:38:59.683056 All Pass.
3725 23:38:59.683515
3726 23:38:59.684030 CH 0, Rank 1
3727 23:38:59.686135 SW Impedance : PASS
3728 23:38:59.686589 DUTY Scan : NO K
3729 23:38:59.690153 ZQ Calibration : PASS
3730 23:38:59.693072 Jitter Meter : NO K
3731 23:38:59.693675 CBT Training : PASS
3732 23:38:59.696471 Write leveling : PASS
3733 23:38:59.699842 RX DQS gating : PASS
3734 23:38:59.700404 RX DQ/DQS(RDDQC) : PASS
3735 23:38:59.702976 TX DQ/DQS : PASS
3736 23:38:59.706600 RX DATLAT : PASS
3737 23:38:59.707169 RX DQ/DQS(Engine): PASS
3738 23:38:59.709550 TX OE : NO K
3739 23:38:59.710123 All Pass.
3740 23:38:59.710493
3741 23:38:59.712756 CH 1, Rank 0
3742 23:38:59.713213 SW Impedance : PASS
3743 23:38:59.716281 DUTY Scan : NO K
3744 23:38:59.719589 ZQ Calibration : PASS
3745 23:38:59.720047 Jitter Meter : NO K
3746 23:38:59.723625 CBT Training : PASS
3747 23:38:59.724154 Write leveling : PASS
3748 23:38:59.725988 RX DQS gating : PASS
3749 23:38:59.729711 RX DQ/DQS(RDDQC) : PASS
3750 23:38:59.730228 TX DQ/DQS : PASS
3751 23:38:59.732847 RX DATLAT : PASS
3752 23:38:59.736425 RX DQ/DQS(Engine): PASS
3753 23:38:59.736954 TX OE : NO K
3754 23:38:59.739626 All Pass.
3755 23:38:59.740042
3756 23:38:59.740369 CH 1, Rank 1
3757 23:38:59.742968 SW Impedance : PASS
3758 23:38:59.743491 DUTY Scan : NO K
3759 23:38:59.746084 ZQ Calibration : PASS
3760 23:38:59.749386 Jitter Meter : NO K
3761 23:38:59.749957 CBT Training : PASS
3762 23:38:59.753125 Write leveling : PASS
3763 23:38:59.756326 RX DQS gating : PASS
3764 23:38:59.756747 RX DQ/DQS(RDDQC) : PASS
3765 23:38:59.759720 TX DQ/DQS : PASS
3766 23:38:59.762911 RX DATLAT : PASS
3767 23:38:59.763436 RX DQ/DQS(Engine): PASS
3768 23:38:59.766281 TX OE : NO K
3769 23:38:59.766804 All Pass.
3770 23:38:59.767138
3771 23:38:59.769035 DramC Write-DBI off
3772 23:38:59.773027 PER_BANK_REFRESH: Hybrid Mode
3773 23:38:59.773540 TX_TRACKING: ON
3774 23:38:59.782888 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3775 23:38:59.785907 [FAST_K] Save calibration result to emmc
3776 23:38:59.789314 dramc_set_vcore_voltage set vcore to 650000
3777 23:38:59.792854 Read voltage for 600, 5
3778 23:38:59.793368 Vio18 = 0
3779 23:38:59.793746 Vcore = 650000
3780 23:38:59.795901 Vdram = 0
3781 23:38:59.796420 Vddq = 0
3782 23:38:59.796751 Vmddr = 0
3783 23:38:59.802834 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3784 23:38:59.806204 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3785 23:38:59.809329 MEM_TYPE=3, freq_sel=19
3786 23:38:59.812768 sv_algorithm_assistance_LP4_1600
3787 23:38:59.815560 ============ PULL DRAM RESETB DOWN ============
3788 23:38:59.819793 ========== PULL DRAM RESETB DOWN end =========
3789 23:38:59.826120 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3790 23:38:59.829886 ===================================
3791 23:38:59.830452 LPDDR4 DRAM CONFIGURATION
3792 23:38:59.832635 ===================================
3793 23:38:59.835781 EX_ROW_EN[0] = 0x0
3794 23:38:59.839680 EX_ROW_EN[1] = 0x0
3795 23:38:59.840249 LP4Y_EN = 0x0
3796 23:38:59.842910 WORK_FSP = 0x0
3797 23:38:59.843471 WL = 0x2
3798 23:38:59.845703 RL = 0x2
3799 23:38:59.846162 BL = 0x2
3800 23:38:59.848987 RPST = 0x0
3801 23:38:59.849561 RD_PRE = 0x0
3802 23:38:59.852419 WR_PRE = 0x1
3803 23:38:59.852878 WR_PST = 0x0
3804 23:38:59.855631 DBI_WR = 0x0
3805 23:38:59.856165 DBI_RD = 0x0
3806 23:38:59.859293 OTF = 0x1
3807 23:38:59.862198 ===================================
3808 23:38:59.865945 ===================================
3809 23:38:59.866503 ANA top config
3810 23:38:59.869156 ===================================
3811 23:38:59.872702 DLL_ASYNC_EN = 0
3812 23:38:59.875563 ALL_SLAVE_EN = 1
3813 23:38:59.879210 NEW_RANK_MODE = 1
3814 23:38:59.879772 DLL_IDLE_MODE = 1
3815 23:38:59.882666 LP45_APHY_COMB_EN = 1
3816 23:38:59.886094 TX_ODT_DIS = 1
3817 23:38:59.888872 NEW_8X_MODE = 1
3818 23:38:59.892130 ===================================
3819 23:38:59.896029 ===================================
3820 23:38:59.896595 data_rate = 1200
3821 23:38:59.899146 CKR = 1
3822 23:38:59.902441 DQ_P2S_RATIO = 8
3823 23:38:59.905497 ===================================
3824 23:38:59.909054 CA_P2S_RATIO = 8
3825 23:38:59.912138 DQ_CA_OPEN = 0
3826 23:38:59.915839 DQ_SEMI_OPEN = 0
3827 23:38:59.916374 CA_SEMI_OPEN = 0
3828 23:38:59.919590 CA_FULL_RATE = 0
3829 23:38:59.922279 DQ_CKDIV4_EN = 1
3830 23:38:59.925700 CA_CKDIV4_EN = 1
3831 23:38:59.929495 CA_PREDIV_EN = 0
3832 23:38:59.932542 PH8_DLY = 0
3833 23:38:59.933101 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3834 23:38:59.935578 DQ_AAMCK_DIV = 4
3835 23:38:59.939229 CA_AAMCK_DIV = 4
3836 23:38:59.942923 CA_ADMCK_DIV = 4
3837 23:38:59.945716 DQ_TRACK_CA_EN = 0
3838 23:38:59.948918 CA_PICK = 600
3839 23:38:59.949376 CA_MCKIO = 600
3840 23:38:59.952788 MCKIO_SEMI = 0
3841 23:38:59.955091 PLL_FREQ = 2288
3842 23:38:59.958481 DQ_UI_PI_RATIO = 32
3843 23:38:59.962164 CA_UI_PI_RATIO = 0
3844 23:38:59.965270 ===================================
3845 23:38:59.968994 ===================================
3846 23:38:59.971930 memory_type:LPDDR4
3847 23:38:59.972386 GP_NUM : 10
3848 23:38:59.975723 SRAM_EN : 1
3849 23:38:59.976285 MD32_EN : 0
3850 23:38:59.979651 ===================================
3851 23:38:59.981988 [ANA_INIT] >>>>>>>>>>>>>>
3852 23:38:59.985485 <<<<<< [CONFIGURE PHASE]: ANA_TX
3853 23:38:59.988405 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3854 23:38:59.992432 ===================================
3855 23:38:59.995602 data_rate = 1200,PCW = 0X5800
3856 23:38:59.998443 ===================================
3857 23:39:00.002079 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3858 23:39:00.008943 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3859 23:39:00.011917 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3860 23:39:00.018974 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3861 23:39:00.021868 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3862 23:39:00.024866 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3863 23:39:00.025329 [ANA_INIT] flow start
3864 23:39:00.028600 [ANA_INIT] PLL >>>>>>>>
3865 23:39:00.031966 [ANA_INIT] PLL <<<<<<<<
3866 23:39:00.032528 [ANA_INIT] MIDPI >>>>>>>>
3867 23:39:00.034959 [ANA_INIT] MIDPI <<<<<<<<
3868 23:39:00.038159 [ANA_INIT] DLL >>>>>>>>
3869 23:39:00.038616 [ANA_INIT] flow end
3870 23:39:00.044891 ============ LP4 DIFF to SE enter ============
3871 23:39:00.048378 ============ LP4 DIFF to SE exit ============
3872 23:39:00.051476 [ANA_INIT] <<<<<<<<<<<<<
3873 23:39:00.054866 [Flow] Enable top DCM control >>>>>
3874 23:39:00.058559 [Flow] Enable top DCM control <<<<<
3875 23:39:00.059036 Enable DLL master slave shuffle
3876 23:39:00.065652 ==============================================================
3877 23:39:00.069000 Gating Mode config
3878 23:39:00.072141 ==============================================================
3879 23:39:00.075121 Config description:
3880 23:39:00.084935 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3881 23:39:00.091649 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3882 23:39:00.094780 SELPH_MODE 0: By rank 1: By Phase
3883 23:39:00.101309 ==============================================================
3884 23:39:00.105264 GAT_TRACK_EN = 1
3885 23:39:00.108773 RX_GATING_MODE = 2
3886 23:39:00.111404 RX_GATING_TRACK_MODE = 2
3887 23:39:00.115216 SELPH_MODE = 1
3888 23:39:00.115975 PICG_EARLY_EN = 1
3889 23:39:00.118213 VALID_LAT_VALUE = 1
3890 23:39:00.124594 ==============================================================
3891 23:39:00.128377 Enter into Gating configuration >>>>
3892 23:39:00.131419 Exit from Gating configuration <<<<
3893 23:39:00.134694 Enter into DVFS_PRE_config >>>>>
3894 23:39:00.145376 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3895 23:39:00.147994 Exit from DVFS_PRE_config <<<<<
3896 23:39:00.151972 Enter into PICG configuration >>>>
3897 23:39:00.154385 Exit from PICG configuration <<<<
3898 23:39:00.157779 [RX_INPUT] configuration >>>>>
3899 23:39:00.161396 [RX_INPUT] configuration <<<<<
3900 23:39:00.164675 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3901 23:39:00.171651 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3902 23:39:00.178079 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3903 23:39:00.184711 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3904 23:39:00.191246 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3905 23:39:00.194774 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3906 23:39:00.201220 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3907 23:39:00.204680 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3908 23:39:00.207636 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3909 23:39:00.211203 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3910 23:39:00.214965 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3911 23:39:00.221322 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3912 23:39:00.224560 ===================================
3913 23:39:00.227850 LPDDR4 DRAM CONFIGURATION
3914 23:39:00.231379 ===================================
3915 23:39:00.231942 EX_ROW_EN[0] = 0x0
3916 23:39:00.234051 EX_ROW_EN[1] = 0x0
3917 23:39:00.234510 LP4Y_EN = 0x0
3918 23:39:00.237385 WORK_FSP = 0x0
3919 23:39:00.237894 WL = 0x2
3920 23:39:00.240784 RL = 0x2
3921 23:39:00.241242 BL = 0x2
3922 23:39:00.244148 RPST = 0x0
3923 23:39:00.244605 RD_PRE = 0x0
3924 23:39:00.247272 WR_PRE = 0x1
3925 23:39:00.247736 WR_PST = 0x0
3926 23:39:00.251192 DBI_WR = 0x0
3927 23:39:00.254303 DBI_RD = 0x0
3928 23:39:00.254895 OTF = 0x1
3929 23:39:00.257605 ===================================
3930 23:39:00.261619 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3931 23:39:00.264672 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3932 23:39:00.271555 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3933 23:39:00.275362 ===================================
3934 23:39:00.275928 LPDDR4 DRAM CONFIGURATION
3935 23:39:00.277416 ===================================
3936 23:39:00.280995 EX_ROW_EN[0] = 0x10
3937 23:39:00.284371 EX_ROW_EN[1] = 0x0
3938 23:39:00.284849 LP4Y_EN = 0x0
3939 23:39:00.287748 WORK_FSP = 0x0
3940 23:39:00.288312 WL = 0x2
3941 23:39:00.291025 RL = 0x2
3942 23:39:00.291588 BL = 0x2
3943 23:39:00.294054 RPST = 0x0
3944 23:39:00.294610 RD_PRE = 0x0
3945 23:39:00.297309 WR_PRE = 0x1
3946 23:39:00.297928 WR_PST = 0x0
3947 23:39:00.300579 DBI_WR = 0x0
3948 23:39:00.301142 DBI_RD = 0x0
3949 23:39:00.303909 OTF = 0x1
3950 23:39:00.307069 ===================================
3951 23:39:00.314247 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3952 23:39:00.317720 nWR fixed to 30
3953 23:39:00.320708 [ModeRegInit_LP4] CH0 RK0
3954 23:39:00.321165 [ModeRegInit_LP4] CH0 RK1
3955 23:39:00.323812 [ModeRegInit_LP4] CH1 RK0
3956 23:39:00.327456 [ModeRegInit_LP4] CH1 RK1
3957 23:39:00.328022 match AC timing 17
3958 23:39:00.333707 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3959 23:39:00.337442 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3960 23:39:00.340451 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3961 23:39:00.347352 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3962 23:39:00.350443 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3963 23:39:00.350921 ==
3964 23:39:00.353947 Dram Type= 6, Freq= 0, CH_0, rank 0
3965 23:39:00.357144 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3966 23:39:00.357790 ==
3967 23:39:00.364206 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3968 23:39:00.370634 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3969 23:39:00.373848 [CA 0] Center 35 (5~66) winsize 62
3970 23:39:00.377250 [CA 1] Center 35 (5~66) winsize 62
3971 23:39:00.380621 [CA 2] Center 33 (3~64) winsize 62
3972 23:39:00.384278 [CA 3] Center 33 (2~64) winsize 63
3973 23:39:00.387673 [CA 4] Center 33 (2~64) winsize 63
3974 23:39:00.390328 [CA 5] Center 32 (2~63) winsize 62
3975 23:39:00.390787
3976 23:39:00.393757 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3977 23:39:00.394320
3978 23:39:00.397045 [CATrainingPosCal] consider 1 rank data
3979 23:39:00.400038 u2DelayCellTimex100 = 270/100 ps
3980 23:39:00.403618 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3981 23:39:00.407067 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3982 23:39:00.410530 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3983 23:39:00.413363 CA3 delay=33 (2~64),Diff = 1 PI (9 cell)
3984 23:39:00.416679 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3985 23:39:00.420289 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3986 23:39:00.423362
3987 23:39:00.426755 CA PerBit enable=1, Macro0, CA PI delay=32
3988 23:39:00.427176
3989 23:39:00.429751 [CBTSetCACLKResult] CA Dly = 32
3990 23:39:00.430340 CS Dly: 4 (0~35)
3991 23:39:00.430696 ==
3992 23:39:00.433370 Dram Type= 6, Freq= 0, CH_0, rank 1
3993 23:39:00.436948 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3994 23:39:00.437490 ==
3995 23:39:00.443927 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3996 23:39:00.449709 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3997 23:39:00.453670 [CA 0] Center 35 (5~66) winsize 62
3998 23:39:00.456275 [CA 1] Center 35 (5~66) winsize 62
3999 23:39:00.459583 [CA 2] Center 34 (3~65) winsize 63
4000 23:39:00.463270 [CA 3] Center 33 (3~64) winsize 62
4001 23:39:00.466574 [CA 4] Center 33 (2~64) winsize 63
4002 23:39:00.469804 [CA 5] Center 32 (2~63) winsize 62
4003 23:39:00.470270
4004 23:39:00.473478 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4005 23:39:00.474131
4006 23:39:00.476633 [CATrainingPosCal] consider 2 rank data
4007 23:39:00.479922 u2DelayCellTimex100 = 270/100 ps
4008 23:39:00.483524 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
4009 23:39:00.486423 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
4010 23:39:00.490068 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
4011 23:39:00.493473 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
4012 23:39:00.499764 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
4013 23:39:00.503049 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
4014 23:39:00.503511
4015 23:39:00.507173 CA PerBit enable=1, Macro0, CA PI delay=32
4016 23:39:00.507732
4017 23:39:00.510121 [CBTSetCACLKResult] CA Dly = 32
4018 23:39:00.510679 CS Dly: 4 (0~36)
4019 23:39:00.511099
4020 23:39:00.513161 ----->DramcWriteLeveling(PI) begin...
4021 23:39:00.513671 ==
4022 23:39:00.516569 Dram Type= 6, Freq= 0, CH_0, rank 0
4023 23:39:00.523277 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4024 23:39:00.523825 ==
4025 23:39:00.526098 Write leveling (Byte 0): 34 => 34
4026 23:39:00.526581 Write leveling (Byte 1): 30 => 30
4027 23:39:00.529757 DramcWriteLeveling(PI) end<-----
4028 23:39:00.530316
4029 23:39:00.533039 ==
4030 23:39:00.533707 Dram Type= 6, Freq= 0, CH_0, rank 0
4031 23:39:00.539640 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4032 23:39:00.540204 ==
4033 23:39:00.543450 [Gating] SW mode calibration
4034 23:39:00.549644 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4035 23:39:00.553000 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4036 23:39:00.559304 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4037 23:39:00.562904 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4038 23:39:00.565904 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4039 23:39:00.572779 0 9 12 | B1->B0 | 3434 2d2d | 1 1 | (1 1) (1 0)
4040 23:39:00.576027 0 9 16 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
4041 23:39:00.579762 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4042 23:39:00.586008 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4043 23:39:00.589405 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4044 23:39:00.592690 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4045 23:39:00.599643 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4046 23:39:00.602531 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4047 23:39:00.606038 0 10 12 | B1->B0 | 2323 3939 | 0 0 | (0 0) (0 0)
4048 23:39:00.613038 0 10 16 | B1->B0 | 2f2f 4646 | 0 0 | (0 0) (0 0)
4049 23:39:00.616187 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4050 23:39:00.619209 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4051 23:39:00.622584 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4052 23:39:00.629639 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4053 23:39:00.632846 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4054 23:39:00.636180 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4055 23:39:00.642792 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4056 23:39:00.646020 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4057 23:39:00.649213 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4058 23:39:00.655742 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4059 23:39:00.658933 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4060 23:39:00.662468 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4061 23:39:00.669301 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4062 23:39:00.672681 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4063 23:39:00.675666 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4064 23:39:00.682345 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4065 23:39:00.685491 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4066 23:39:00.689488 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4067 23:39:00.695655 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4068 23:39:00.699250 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4069 23:39:00.702955 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4070 23:39:00.709042 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4071 23:39:00.712346 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4072 23:39:00.715487 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4073 23:39:00.719563 Total UI for P1: 0, mck2ui 16
4074 23:39:00.722522 best dqsien dly found for B0: ( 0, 13, 12)
4075 23:39:00.725678 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4076 23:39:00.728774 Total UI for P1: 0, mck2ui 16
4077 23:39:00.732501 best dqsien dly found for B1: ( 0, 13, 18)
4078 23:39:00.738906 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4079 23:39:00.742057 best DQS1 dly(MCK, UI, PI) = (0, 13, 18)
4080 23:39:00.742520
4081 23:39:00.745735 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4082 23:39:00.748527 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)
4083 23:39:00.752377 [Gating] SW calibration Done
4084 23:39:00.752944 ==
4085 23:39:00.755152 Dram Type= 6, Freq= 0, CH_0, rank 0
4086 23:39:00.758677 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4087 23:39:00.759213 ==
4088 23:39:00.762122 RX Vref Scan: 0
4089 23:39:00.762579
4090 23:39:00.762941 RX Vref 0 -> 0, step: 1
4091 23:39:00.763282
4092 23:39:00.765283 RX Delay -230 -> 252, step: 16
4093 23:39:00.769254 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4094 23:39:00.775500 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4095 23:39:00.778541 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4096 23:39:00.782487 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4097 23:39:00.785349 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4098 23:39:00.791668 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4099 23:39:00.795690 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4100 23:39:00.798892 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4101 23:39:00.801857 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4102 23:39:00.805280 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4103 23:39:00.811583 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4104 23:39:00.815439 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4105 23:39:00.818124 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4106 23:39:00.821918 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4107 23:39:00.828378 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4108 23:39:00.831701 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4109 23:39:00.832265 ==
4110 23:39:00.835204 Dram Type= 6, Freq= 0, CH_0, rank 0
4111 23:39:00.838331 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4112 23:39:00.838895 ==
4113 23:39:00.841701 DQS Delay:
4114 23:39:00.842112 DQS0 = 0, DQS1 = 0
4115 23:39:00.842463 DQM Delay:
4116 23:39:00.845204 DQM0 = 52, DQM1 = 46
4117 23:39:00.845803 DQ Delay:
4118 23:39:00.848351 DQ0 =49, DQ1 =57, DQ2 =41, DQ3 =41
4119 23:39:00.851359 DQ4 =57, DQ5 =41, DQ6 =65, DQ7 =65
4120 23:39:00.855402 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4121 23:39:00.858539 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =57
4122 23:39:00.859111
4123 23:39:00.859480
4124 23:39:00.859971 ==
4125 23:39:00.861991 Dram Type= 6, Freq= 0, CH_0, rank 0
4126 23:39:00.868460 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4127 23:39:00.869036 ==
4128 23:39:00.869404
4129 23:39:00.869807
4130 23:39:00.870140 TX Vref Scan disable
4131 23:39:00.871795 == TX Byte 0 ==
4132 23:39:00.875453 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4133 23:39:00.882115 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4134 23:39:00.882678 == TX Byte 1 ==
4135 23:39:00.885076 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4136 23:39:00.892317 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4137 23:39:00.892880 ==
4138 23:39:00.895174 Dram Type= 6, Freq= 0, CH_0, rank 0
4139 23:39:00.898853 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4140 23:39:00.899416 ==
4141 23:39:00.899779
4142 23:39:00.900117
4143 23:39:00.901919 TX Vref Scan disable
4144 23:39:00.905140 == TX Byte 0 ==
4145 23:39:00.908377 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4146 23:39:00.911844 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4147 23:39:00.915219 == TX Byte 1 ==
4148 23:39:00.918200 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4149 23:39:00.922386 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4150 23:39:00.922948
4151 23:39:00.923314 [DATLAT]
4152 23:39:00.924724 Freq=600, CH0 RK0
4153 23:39:00.925187
4154 23:39:00.925550 DATLAT Default: 0x9
4155 23:39:00.928232 0, 0xFFFF, sum = 0
4156 23:39:00.931515 1, 0xFFFF, sum = 0
4157 23:39:00.931981 2, 0xFFFF, sum = 0
4158 23:39:00.935154 3, 0xFFFF, sum = 0
4159 23:39:00.935725 4, 0xFFFF, sum = 0
4160 23:39:00.938471 5, 0xFFFF, sum = 0
4161 23:39:00.939041 6, 0xFFFF, sum = 0
4162 23:39:00.941922 7, 0xFFFF, sum = 0
4163 23:39:00.942390 8, 0x0, sum = 1
4164 23:39:00.944865 9, 0x0, sum = 2
4165 23:39:00.945331 10, 0x0, sum = 3
4166 23:39:00.945753 11, 0x0, sum = 4
4167 23:39:00.947931 best_step = 9
4168 23:39:00.948385
4169 23:39:00.948747 ==
4170 23:39:00.951934 Dram Type= 6, Freq= 0, CH_0, rank 0
4171 23:39:00.955261 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4172 23:39:00.955740 ==
4173 23:39:00.958520 RX Vref Scan: 1
4174 23:39:00.958977
4175 23:39:00.959341 RX Vref 0 -> 0, step: 1
4176 23:39:00.961356
4177 23:39:00.961859 RX Delay -163 -> 252, step: 8
4178 23:39:00.962225
4179 23:39:00.964552 Set Vref, RX VrefLevel [Byte0]: 54
4180 23:39:00.968344 [Byte1]: 55
4181 23:39:00.972614
4182 23:39:00.973175 Final RX Vref Byte 0 = 54 to rank0
4183 23:39:00.975849 Final RX Vref Byte 1 = 55 to rank0
4184 23:39:00.979154 Final RX Vref Byte 0 = 54 to rank1
4185 23:39:00.982317 Final RX Vref Byte 1 = 55 to rank1==
4186 23:39:00.986058 Dram Type= 6, Freq= 0, CH_0, rank 0
4187 23:39:00.992241 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4188 23:39:00.992776 ==
4189 23:39:00.993145 DQS Delay:
4190 23:39:00.993549 DQS0 = 0, DQS1 = 0
4191 23:39:00.995402 DQM Delay:
4192 23:39:00.995859 DQM0 = 52, DQM1 = 46
4193 23:39:00.999220 DQ Delay:
4194 23:39:01.002592 DQ0 =52, DQ1 =56, DQ2 =48, DQ3 =48
4195 23:39:01.005541 DQ4 =56, DQ5 =44, DQ6 =60, DQ7 =56
4196 23:39:01.008958 DQ8 =36, DQ9 =36, DQ10 =44, DQ11 =40
4197 23:39:01.011790 DQ12 =52, DQ13 =52, DQ14 =60, DQ15 =52
4198 23:39:01.012310
4199 23:39:01.012677
4200 23:39:01.018471 [DQSOSCAuto] RK0, (LSB)MR18= 0x6d60, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 389 ps
4201 23:39:01.022398 CH0 RK0: MR19=808, MR18=6D60
4202 23:39:01.028529 CH0_RK0: MR19=0x808, MR18=0x6D60, DQSOSC=389, MR23=63, INC=173, DEC=115
4203 23:39:01.028992
4204 23:39:01.032114 ----->DramcWriteLeveling(PI) begin...
4205 23:39:01.032679 ==
4206 23:39:01.035169 Dram Type= 6, Freq= 0, CH_0, rank 1
4207 23:39:01.038492 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4208 23:39:01.038967 ==
4209 23:39:01.041612 Write leveling (Byte 0): 35 => 35
4210 23:39:01.044865 Write leveling (Byte 1): 32 => 32
4211 23:39:01.048259 DramcWriteLeveling(PI) end<-----
4212 23:39:01.048837
4213 23:39:01.049212 ==
4214 23:39:01.051307 Dram Type= 6, Freq= 0, CH_0, rank 1
4215 23:39:01.055087 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4216 23:39:01.058118 ==
4217 23:39:01.058576 [Gating] SW mode calibration
4218 23:39:01.064717 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4219 23:39:01.071734 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4220 23:39:01.075383 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4221 23:39:01.081770 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4222 23:39:01.084998 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4223 23:39:01.088325 0 9 12 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 0)
4224 23:39:01.094945 0 9 16 | B1->B0 | 2e2e 2b2b | 1 0 | (1 0) (0 0)
4225 23:39:01.098313 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4226 23:39:01.101299 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4227 23:39:01.108242 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4228 23:39:01.111483 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4229 23:39:01.114597 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4230 23:39:01.121313 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4231 23:39:01.124691 0 10 12 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4232 23:39:01.127562 0 10 16 | B1->B0 | 4545 4545 | 0 0 | (0 0) (0 0)
4233 23:39:01.134218 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4234 23:39:01.138040 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4235 23:39:01.140781 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4236 23:39:01.147383 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4237 23:39:01.150833 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4238 23:39:01.153993 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4239 23:39:01.160804 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4240 23:39:01.164318 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4241 23:39:01.167698 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4242 23:39:01.174526 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4243 23:39:01.177652 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4244 23:39:01.181140 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4245 23:39:01.187802 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4246 23:39:01.190792 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4247 23:39:01.194360 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4248 23:39:01.197474 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4249 23:39:01.204321 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4250 23:39:01.207039 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4251 23:39:01.211200 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4252 23:39:01.217686 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4253 23:39:01.220511 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4254 23:39:01.224339 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4255 23:39:01.230858 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4256 23:39:01.234016 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4257 23:39:01.237322 Total UI for P1: 0, mck2ui 16
4258 23:39:01.241273 best dqsien dly found for B0: ( 0, 13, 12)
4259 23:39:01.243599 Total UI for P1: 0, mck2ui 16
4260 23:39:01.247383 best dqsien dly found for B1: ( 0, 13, 14)
4261 23:39:01.250288 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4262 23:39:01.253547 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4263 23:39:01.254059
4264 23:39:01.256961 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4265 23:39:01.260088 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4266 23:39:01.263645 [Gating] SW calibration Done
4267 23:39:01.264103 ==
4268 23:39:01.267323 Dram Type= 6, Freq= 0, CH_0, rank 1
4269 23:39:01.273503 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4270 23:39:01.274013 ==
4271 23:39:01.274383 RX Vref Scan: 0
4272 23:39:01.274722
4273 23:39:01.277726 RX Vref 0 -> 0, step: 1
4274 23:39:01.278291
4275 23:39:01.280318 RX Delay -230 -> 252, step: 16
4276 23:39:01.284227 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4277 23:39:01.286795 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4278 23:39:01.290503 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4279 23:39:01.296577 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4280 23:39:01.300321 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4281 23:39:01.303542 iDelay=218, Bit 5, Center 49 (-102 ~ 201) 304
4282 23:39:01.306758 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4283 23:39:01.313264 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4284 23:39:01.316729 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4285 23:39:01.320527 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4286 23:39:01.323460 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4287 23:39:01.326555 iDelay=218, Bit 11, Center 41 (-102 ~ 185) 288
4288 23:39:01.333386 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4289 23:39:01.336479 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4290 23:39:01.340290 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4291 23:39:01.342988 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4292 23:39:01.346539 ==
4293 23:39:01.350071 Dram Type= 6, Freq= 0, CH_0, rank 1
4294 23:39:01.353506 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4295 23:39:01.354145 ==
4296 23:39:01.354522 DQS Delay:
4297 23:39:01.356299 DQS0 = 0, DQS1 = 0
4298 23:39:01.356756 DQM Delay:
4299 23:39:01.359921 DQM0 = 52, DQM1 = 44
4300 23:39:01.360486 DQ Delay:
4301 23:39:01.362941 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =49
4302 23:39:01.366511 DQ4 =57, DQ5 =49, DQ6 =57, DQ7 =57
4303 23:39:01.369785 DQ8 =33, DQ9 =25, DQ10 =49, DQ11 =41
4304 23:39:01.372891 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =49
4305 23:39:01.373316
4306 23:39:01.373721
4307 23:39:01.374063 ==
4308 23:39:01.376816 Dram Type= 6, Freq= 0, CH_0, rank 1
4309 23:39:01.380206 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4310 23:39:01.380773 ==
4311 23:39:01.381147
4312 23:39:01.381484
4313 23:39:01.382856 TX Vref Scan disable
4314 23:39:01.386384 == TX Byte 0 ==
4315 23:39:01.389842 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4316 23:39:01.392654 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4317 23:39:01.396191 == TX Byte 1 ==
4318 23:39:01.399539 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4319 23:39:01.403319 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4320 23:39:01.403784 ==
4321 23:39:01.406309 Dram Type= 6, Freq= 0, CH_0, rank 1
4322 23:39:01.412849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4323 23:39:01.413369 ==
4324 23:39:01.413784
4325 23:39:01.414132
4326 23:39:01.414460 TX Vref Scan disable
4327 23:39:01.417122 == TX Byte 0 ==
4328 23:39:01.420545 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4329 23:39:01.423436 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4330 23:39:01.427201 == TX Byte 1 ==
4331 23:39:01.430082 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4332 23:39:01.436781 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4333 23:39:01.437009
4334 23:39:01.437188 [DATLAT]
4335 23:39:01.437355 Freq=600, CH0 RK1
4336 23:39:01.437517
4337 23:39:01.440139 DATLAT Default: 0x9
4338 23:39:01.440320 0, 0xFFFF, sum = 0
4339 23:39:01.443476 1, 0xFFFF, sum = 0
4340 23:39:01.443661 2, 0xFFFF, sum = 0
4341 23:39:01.446382 3, 0xFFFF, sum = 0
4342 23:39:01.446568 4, 0xFFFF, sum = 0
4343 23:39:01.449706 5, 0xFFFF, sum = 0
4344 23:39:01.453459 6, 0xFFFF, sum = 0
4345 23:39:01.453665 7, 0xFFFF, sum = 0
4346 23:39:01.457008 8, 0x0, sum = 1
4347 23:39:01.457192 9, 0x0, sum = 2
4348 23:39:01.457339 10, 0x0, sum = 3
4349 23:39:01.459948 11, 0x0, sum = 4
4350 23:39:01.460134 best_step = 9
4351 23:39:01.460279
4352 23:39:01.460412 ==
4353 23:39:01.463196 Dram Type= 6, Freq= 0, CH_0, rank 1
4354 23:39:01.469647 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4355 23:39:01.469831 ==
4356 23:39:01.469976 RX Vref Scan: 0
4357 23:39:01.470110
4358 23:39:01.472997 RX Vref 0 -> 0, step: 1
4359 23:39:01.473148
4360 23:39:01.476305 RX Delay -179 -> 252, step: 8
4361 23:39:01.479565 iDelay=197, Bit 0, Center 52 (-91 ~ 196) 288
4362 23:39:01.486394 iDelay=197, Bit 1, Center 56 (-83 ~ 196) 280
4363 23:39:01.489353 iDelay=197, Bit 2, Center 52 (-91 ~ 196) 288
4364 23:39:01.492706 iDelay=197, Bit 3, Center 52 (-91 ~ 196) 288
4365 23:39:01.496338 iDelay=197, Bit 4, Center 56 (-83 ~ 196) 280
4366 23:39:01.499633 iDelay=197, Bit 5, Center 44 (-99 ~ 188) 288
4367 23:39:01.505989 iDelay=197, Bit 6, Center 56 (-83 ~ 196) 280
4368 23:39:01.509333 iDelay=197, Bit 7, Center 56 (-83 ~ 196) 280
4369 23:39:01.512549 iDelay=197, Bit 8, Center 36 (-107 ~ 180) 288
4370 23:39:01.516103 iDelay=197, Bit 9, Center 36 (-107 ~ 180) 288
4371 23:39:01.519569 iDelay=197, Bit 10, Center 48 (-91 ~ 188) 280
4372 23:39:01.526042 iDelay=197, Bit 11, Center 36 (-107 ~ 180) 288
4373 23:39:01.529566 iDelay=197, Bit 12, Center 52 (-91 ~ 196) 288
4374 23:39:01.532503 iDelay=197, Bit 13, Center 52 (-91 ~ 196) 288
4375 23:39:01.536383 iDelay=197, Bit 14, Center 56 (-83 ~ 196) 280
4376 23:39:01.542582 iDelay=197, Bit 15, Center 52 (-91 ~ 196) 288
4377 23:39:01.542696 ==
4378 23:39:01.545796 Dram Type= 6, Freq= 0, CH_0, rank 1
4379 23:39:01.549530 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4380 23:39:01.549657 ==
4381 23:39:01.549748 DQS Delay:
4382 23:39:01.552715 DQS0 = 0, DQS1 = 0
4383 23:39:01.552828 DQM Delay:
4384 23:39:01.555954 DQM0 = 53, DQM1 = 46
4385 23:39:01.556067 DQ Delay:
4386 23:39:01.559315 DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =52
4387 23:39:01.562962 DQ4 =56, DQ5 =44, DQ6 =56, DQ7 =56
4388 23:39:01.566005 DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =36
4389 23:39:01.569330 DQ12 =52, DQ13 =52, DQ14 =56, DQ15 =52
4390 23:39:01.569444
4391 23:39:01.569533
4392 23:39:01.576046 [DQSOSCAuto] RK1, (LSB)MR18= 0x6425, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 391 ps
4393 23:39:01.579877 CH0 RK1: MR19=808, MR18=6425
4394 23:39:01.586190 CH0_RK1: MR19=0x808, MR18=0x6425, DQSOSC=391, MR23=63, INC=171, DEC=114
4395 23:39:01.589451 [RxdqsGatingPostProcess] freq 600
4396 23:39:01.596294 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4397 23:39:01.599587 Pre-setting of DQS Precalculation
4398 23:39:01.602900 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4399 23:39:01.603143 ==
4400 23:39:01.606352 Dram Type= 6, Freq= 0, CH_1, rank 0
4401 23:39:01.609310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4402 23:39:01.609544 ==
4403 23:39:01.615790 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4404 23:39:01.622767 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4405 23:39:01.625910 [CA 0] Center 36 (5~67) winsize 63
4406 23:39:01.629489 [CA 1] Center 36 (5~67) winsize 63
4407 23:39:01.632607 [CA 2] Center 34 (4~65) winsize 62
4408 23:39:01.636617 [CA 3] Center 34 (4~65) winsize 62
4409 23:39:01.639233 [CA 4] Center 34 (4~65) winsize 62
4410 23:39:01.642540 [CA 5] Center 34 (3~65) winsize 63
4411 23:39:01.643013
4412 23:39:01.646113 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4413 23:39:01.646577
4414 23:39:01.649472 [CATrainingPosCal] consider 1 rank data
4415 23:39:01.652803 u2DelayCellTimex100 = 270/100 ps
4416 23:39:01.656435 CA0 delay=36 (5~67),Diff = 2 PI (19 cell)
4417 23:39:01.659244 CA1 delay=36 (5~67),Diff = 2 PI (19 cell)
4418 23:39:01.662545 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4419 23:39:01.665919 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4420 23:39:01.669793 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4421 23:39:01.672556 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4422 23:39:01.676100
4423 23:39:01.679511 CA PerBit enable=1, Macro0, CA PI delay=34
4424 23:39:01.680073
4425 23:39:01.683003 [CBTSetCACLKResult] CA Dly = 34
4426 23:39:01.683564 CS Dly: 5 (0~36)
4427 23:39:01.683945 ==
4428 23:39:01.685774 Dram Type= 6, Freq= 0, CH_1, rank 1
4429 23:39:01.689325 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4430 23:39:01.689962 ==
4431 23:39:01.696085 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4432 23:39:01.703002 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4433 23:39:01.705766 [CA 0] Center 36 (5~67) winsize 63
4434 23:39:01.709819 [CA 1] Center 36 (5~67) winsize 63
4435 23:39:01.712700 [CA 2] Center 34 (4~65) winsize 62
4436 23:39:01.715994 [CA 3] Center 34 (4~65) winsize 62
4437 23:39:01.719390 [CA 4] Center 34 (4~65) winsize 62
4438 23:39:01.722688 [CA 5] Center 34 (3~65) winsize 63
4439 23:39:01.723254
4440 23:39:01.725776 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4441 23:39:01.726244
4442 23:39:01.728981 [CATrainingPosCal] consider 2 rank data
4443 23:39:01.732323 u2DelayCellTimex100 = 270/100 ps
4444 23:39:01.736024 CA0 delay=36 (5~67),Diff = 2 PI (19 cell)
4445 23:39:01.738987 CA1 delay=36 (5~67),Diff = 2 PI (19 cell)
4446 23:39:01.742192 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4447 23:39:01.745684 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4448 23:39:01.752317 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4449 23:39:01.755400 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4450 23:39:01.755963
4451 23:39:01.759246 CA PerBit enable=1, Macro0, CA PI delay=34
4452 23:39:01.759875
4453 23:39:01.762540 [CBTSetCACLKResult] CA Dly = 34
4454 23:39:01.763005 CS Dly: 6 (0~38)
4455 23:39:01.763370
4456 23:39:01.765624 ----->DramcWriteLeveling(PI) begin...
4457 23:39:01.766097 ==
4458 23:39:01.769147 Dram Type= 6, Freq= 0, CH_1, rank 0
4459 23:39:01.775656 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4460 23:39:01.776217 ==
4461 23:39:01.779375 Write leveling (Byte 0): 31 => 31
4462 23:39:01.779960 Write leveling (Byte 1): 32 => 32
4463 23:39:01.782281 DramcWriteLeveling(PI) end<-----
4464 23:39:01.782744
4465 23:39:01.783109 ==
4466 23:39:01.785671 Dram Type= 6, Freq= 0, CH_1, rank 0
4467 23:39:01.792303 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4468 23:39:01.792771 ==
4469 23:39:01.795872 [Gating] SW mode calibration
4470 23:39:01.802545 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4471 23:39:01.806007 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4472 23:39:01.812342 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4473 23:39:01.815771 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4474 23:39:01.819508 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4475 23:39:01.825520 0 9 12 | B1->B0 | 2e2e 2d2d | 1 0 | (1 0) (1 0)
4476 23:39:01.828847 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4477 23:39:01.832214 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4478 23:39:01.839090 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4479 23:39:01.842124 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4480 23:39:01.845229 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4481 23:39:01.852223 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4482 23:39:01.855536 0 10 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
4483 23:39:01.858528 0 10 12 | B1->B0 | 3232 3939 | 0 0 | (0 0) (0 0)
4484 23:39:01.865413 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4485 23:39:01.869277 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4486 23:39:01.871737 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4487 23:39:01.878471 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4488 23:39:01.881850 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4489 23:39:01.885780 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4490 23:39:01.888743 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4491 23:39:01.895647 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4492 23:39:01.898170 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4493 23:39:01.901751 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4494 23:39:01.908106 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4495 23:39:01.911532 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4496 23:39:01.914922 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4497 23:39:01.921701 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4498 23:39:01.925333 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4499 23:39:01.928305 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4500 23:39:01.934974 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4501 23:39:01.938516 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4502 23:39:01.941748 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4503 23:39:01.948067 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4504 23:39:01.951134 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4505 23:39:01.954268 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4506 23:39:01.961811 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4507 23:39:01.964641 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4508 23:39:01.967868 Total UI for P1: 0, mck2ui 16
4509 23:39:01.971144 best dqsien dly found for B0: ( 0, 13, 10)
4510 23:39:01.974195 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4511 23:39:01.978023 Total UI for P1: 0, mck2ui 16
4512 23:39:01.980822 best dqsien dly found for B1: ( 0, 13, 12)
4513 23:39:01.984943 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4514 23:39:01.988034 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4515 23:39:01.990907
4516 23:39:01.994375 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4517 23:39:01.997664 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4518 23:39:02.000932 [Gating] SW calibration Done
4519 23:39:02.001489 ==
4520 23:39:02.004028 Dram Type= 6, Freq= 0, CH_1, rank 0
4521 23:39:02.007696 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4522 23:39:02.008262 ==
4523 23:39:02.008634 RX Vref Scan: 0
4524 23:39:02.011122
4525 23:39:02.011583 RX Vref 0 -> 0, step: 1
4526 23:39:02.011954
4527 23:39:02.014191 RX Delay -230 -> 252, step: 16
4528 23:39:02.017508 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4529 23:39:02.024138 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4530 23:39:02.027074 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4531 23:39:02.030460 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4532 23:39:02.034487 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4533 23:39:02.037450 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4534 23:39:02.044060 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4535 23:39:02.046892 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4536 23:39:02.050309 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4537 23:39:02.054277 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4538 23:39:02.060677 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4539 23:39:02.063699 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4540 23:39:02.067270 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4541 23:39:02.070965 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4542 23:39:02.077096 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4543 23:39:02.080676 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4544 23:39:02.081231 ==
4545 23:39:02.083915 Dram Type= 6, Freq= 0, CH_1, rank 0
4546 23:39:02.087208 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4547 23:39:02.087732 ==
4548 23:39:02.088101 DQS Delay:
4549 23:39:02.090898 DQS0 = 0, DQS1 = 0
4550 23:39:02.091489 DQM Delay:
4551 23:39:02.093691 DQM0 = 46, DQM1 = 46
4552 23:39:02.094158 DQ Delay:
4553 23:39:02.097365 DQ0 =49, DQ1 =41, DQ2 =41, DQ3 =41
4554 23:39:02.100835 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4555 23:39:02.104222 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4556 23:39:02.107420 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4557 23:39:02.107885
4558 23:39:02.108248
4559 23:39:02.108586 ==
4560 23:39:02.110552 Dram Type= 6, Freq= 0, CH_1, rank 0
4561 23:39:02.114114 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4562 23:39:02.117717 ==
4563 23:39:02.118278
4564 23:39:02.118641
4565 23:39:02.118977 TX Vref Scan disable
4566 23:39:02.121073 == TX Byte 0 ==
4567 23:39:02.124382 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4568 23:39:02.127065 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4569 23:39:02.130214 == TX Byte 1 ==
4570 23:39:02.133758 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4571 23:39:02.137174 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4572 23:39:02.140794 ==
4573 23:39:02.143816 Dram Type= 6, Freq= 0, CH_1, rank 0
4574 23:39:02.146744 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4575 23:39:02.147206 ==
4576 23:39:02.147569
4577 23:39:02.147907
4578 23:39:02.150459 TX Vref Scan disable
4579 23:39:02.150918 == TX Byte 0 ==
4580 23:39:02.157002 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4581 23:39:02.160109 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4582 23:39:02.160668 == TX Byte 1 ==
4583 23:39:02.166766 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4584 23:39:02.170094 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4585 23:39:02.170556
4586 23:39:02.170922 [DATLAT]
4587 23:39:02.173377 Freq=600, CH1 RK0
4588 23:39:02.174033
4589 23:39:02.174482 DATLAT Default: 0x9
4590 23:39:02.176932 0, 0xFFFF, sum = 0
4591 23:39:02.177399 1, 0xFFFF, sum = 0
4592 23:39:02.180062 2, 0xFFFF, sum = 0
4593 23:39:02.180545 3, 0xFFFF, sum = 0
4594 23:39:02.184084 4, 0xFFFF, sum = 0
4595 23:39:02.186689 5, 0xFFFF, sum = 0
4596 23:39:02.187154 6, 0xFFFF, sum = 0
4597 23:39:02.190286 7, 0xFFFF, sum = 0
4598 23:39:02.190753 8, 0x0, sum = 1
4599 23:39:02.191165 9, 0x0, sum = 2
4600 23:39:02.193493 10, 0x0, sum = 3
4601 23:39:02.194005 11, 0x0, sum = 4
4602 23:39:02.197133 best_step = 9
4603 23:39:02.197744
4604 23:39:02.198121 ==
4605 23:39:02.200313 Dram Type= 6, Freq= 0, CH_1, rank 0
4606 23:39:02.203680 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4607 23:39:02.204243 ==
4608 23:39:02.206863 RX Vref Scan: 1
4609 23:39:02.207321
4610 23:39:02.207689 RX Vref 0 -> 0, step: 1
4611 23:39:02.208031
4612 23:39:02.210293 RX Delay -163 -> 252, step: 8
4613 23:39:02.210755
4614 23:39:02.213405 Set Vref, RX VrefLevel [Byte0]: 55
4615 23:39:02.217096 [Byte1]: 53
4616 23:39:02.220510
4617 23:39:02.220964 Final RX Vref Byte 0 = 55 to rank0
4618 23:39:02.224079 Final RX Vref Byte 1 = 53 to rank0
4619 23:39:02.227704 Final RX Vref Byte 0 = 55 to rank1
4620 23:39:02.230980 Final RX Vref Byte 1 = 53 to rank1==
4621 23:39:02.234002 Dram Type= 6, Freq= 0, CH_1, rank 0
4622 23:39:02.240819 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4623 23:39:02.241383 ==
4624 23:39:02.241789 DQS Delay:
4625 23:39:02.242131 DQS0 = 0, DQS1 = 0
4626 23:39:02.244168 DQM Delay:
4627 23:39:02.244728 DQM0 = 48, DQM1 = 45
4628 23:39:02.247226 DQ Delay:
4629 23:39:02.250985 DQ0 =52, DQ1 =40, DQ2 =40, DQ3 =44
4630 23:39:02.254054 DQ4 =48, DQ5 =56, DQ6 =56, DQ7 =48
4631 23:39:02.254628 DQ8 =36, DQ9 =36, DQ10 =44, DQ11 =36
4632 23:39:02.260400 DQ12 =52, DQ13 =52, DQ14 =56, DQ15 =52
4633 23:39:02.260950
4634 23:39:02.261313
4635 23:39:02.267097 [DQSOSCAuto] RK0, (LSB)MR18= 0x446a, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
4636 23:39:02.270197 CH1 RK0: MR19=808, MR18=446A
4637 23:39:02.277442 CH1_RK0: MR19=0x808, MR18=0x446A, DQSOSC=389, MR23=63, INC=173, DEC=115
4638 23:39:02.278057
4639 23:39:02.280992 ----->DramcWriteLeveling(PI) begin...
4640 23:39:02.281558 ==
4641 23:39:02.284351 Dram Type= 6, Freq= 0, CH_1, rank 1
4642 23:39:02.287448 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4643 23:39:02.287912 ==
4644 23:39:02.290673 Write leveling (Byte 0): 28 => 28
4645 23:39:02.293832 Write leveling (Byte 1): 31 => 31
4646 23:39:02.297763 DramcWriteLeveling(PI) end<-----
4647 23:39:02.298317
4648 23:39:02.298680 ==
4649 23:39:02.300285 Dram Type= 6, Freq= 0, CH_1, rank 1
4650 23:39:02.304377 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4651 23:39:02.304942 ==
4652 23:39:02.307051 [Gating] SW mode calibration
4653 23:39:02.313648 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4654 23:39:02.320797 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4655 23:39:02.323889 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4656 23:39:02.327087 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4657 23:39:02.333572 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4658 23:39:02.337374 0 9 12 | B1->B0 | 2f2f 2f2f | 1 1 | (0 0) (0 0)
4659 23:39:02.340420 0 9 16 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4660 23:39:02.347231 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4661 23:39:02.350320 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4662 23:39:02.354075 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4663 23:39:02.360103 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4664 23:39:02.364179 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4665 23:39:02.367078 0 10 8 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
4666 23:39:02.373647 0 10 12 | B1->B0 | 3a3a 3434 | 0 0 | (1 1) (0 0)
4667 23:39:02.377327 0 10 16 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
4668 23:39:02.380062 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4669 23:39:02.387255 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4670 23:39:02.390142 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4671 23:39:02.393304 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4672 23:39:02.400655 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4673 23:39:02.403780 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4674 23:39:02.406854 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4675 23:39:02.414156 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4676 23:39:02.417007 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4677 23:39:02.420385 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4678 23:39:02.427004 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4679 23:39:02.430266 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4680 23:39:02.433661 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4681 23:39:02.436539 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4682 23:39:02.443560 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4683 23:39:02.447067 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4684 23:39:02.449724 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4685 23:39:02.456473 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4686 23:39:02.460161 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4687 23:39:02.463333 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4688 23:39:02.470126 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4689 23:39:02.473462 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4690 23:39:02.476395 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4691 23:39:02.483122 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4692 23:39:02.486544 Total UI for P1: 0, mck2ui 16
4693 23:39:02.490307 best dqsien dly found for B0: ( 0, 13, 10)
4694 23:39:02.490778 Total UI for P1: 0, mck2ui 16
4695 23:39:02.496570 best dqsien dly found for B1: ( 0, 13, 10)
4696 23:39:02.499891 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4697 23:39:02.503315 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4698 23:39:02.503892
4699 23:39:02.506870 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4700 23:39:02.510106 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4701 23:39:02.513437 [Gating] SW calibration Done
4702 23:39:02.514129 ==
4703 23:39:02.516466 Dram Type= 6, Freq= 0, CH_1, rank 1
4704 23:39:02.519611 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4705 23:39:02.520085 ==
4706 23:39:02.523597 RX Vref Scan: 0
4707 23:39:02.524130
4708 23:39:02.524473 RX Vref 0 -> 0, step: 1
4709 23:39:02.524789
4710 23:39:02.526397 RX Delay -230 -> 252, step: 16
4711 23:39:02.533383 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4712 23:39:02.536152 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4713 23:39:02.539778 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4714 23:39:02.543311 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4715 23:39:02.546571 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4716 23:39:02.552785 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4717 23:39:02.556235 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4718 23:39:02.559798 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4719 23:39:02.563310 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4720 23:39:02.569893 iDelay=218, Bit 9, Center 41 (-118 ~ 201) 320
4721 23:39:02.573231 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4722 23:39:02.577040 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4723 23:39:02.579660 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4724 23:39:02.583325 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4725 23:39:02.589453 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4726 23:39:02.592807 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4727 23:39:02.593270 ==
4728 23:39:02.596595 Dram Type= 6, Freq= 0, CH_1, rank 1
4729 23:39:02.600247 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4730 23:39:02.600820 ==
4731 23:39:02.603203 DQS Delay:
4732 23:39:02.603764 DQS0 = 0, DQS1 = 0
4733 23:39:02.606409 DQM Delay:
4734 23:39:02.606873 DQM0 = 51, DQM1 = 48
4735 23:39:02.607243 DQ Delay:
4736 23:39:02.610272 DQ0 =57, DQ1 =49, DQ2 =33, DQ3 =49
4737 23:39:02.613189 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49
4738 23:39:02.616524 DQ8 =33, DQ9 =41, DQ10 =49, DQ11 =41
4739 23:39:02.620125 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =57
4740 23:39:02.620700
4741 23:39:02.621072
4742 23:39:02.621421 ==
4743 23:39:02.622835 Dram Type= 6, Freq= 0, CH_1, rank 1
4744 23:39:02.629499 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4745 23:39:02.630088 ==
4746 23:39:02.630462
4747 23:39:02.630861
4748 23:39:02.631194 TX Vref Scan disable
4749 23:39:02.633664 == TX Byte 0 ==
4750 23:39:02.637063 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4751 23:39:02.643660 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4752 23:39:02.644234 == TX Byte 1 ==
4753 23:39:02.646751 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4754 23:39:02.653437 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4755 23:39:02.654068 ==
4756 23:39:02.657012 Dram Type= 6, Freq= 0, CH_1, rank 1
4757 23:39:02.660159 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4758 23:39:02.660626 ==
4759 23:39:02.661261
4760 23:39:02.661695
4761 23:39:02.663411 TX Vref Scan disable
4762 23:39:02.666935 == TX Byte 0 ==
4763 23:39:02.670035 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4764 23:39:02.673614 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4765 23:39:02.677061 == TX Byte 1 ==
4766 23:39:02.679922 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4767 23:39:02.683729 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4768 23:39:02.684314
4769 23:39:02.684685 [DATLAT]
4770 23:39:02.687000 Freq=600, CH1 RK1
4771 23:39:02.687467
4772 23:39:02.687848 DATLAT Default: 0x9
4773 23:39:02.690191 0, 0xFFFF, sum = 0
4774 23:39:02.690663 1, 0xFFFF, sum = 0
4775 23:39:02.693240 2, 0xFFFF, sum = 0
4776 23:39:02.696476 3, 0xFFFF, sum = 0
4777 23:39:02.696938 4, 0xFFFF, sum = 0
4778 23:39:02.700288 5, 0xFFFF, sum = 0
4779 23:39:02.700876 6, 0xFFFF, sum = 0
4780 23:39:02.703403 7, 0xFFFF, sum = 0
4781 23:39:02.704201 8, 0x0, sum = 1
4782 23:39:02.704625 9, 0x0, sum = 2
4783 23:39:02.706635 10, 0x0, sum = 3
4784 23:39:02.707139 11, 0x0, sum = 4
4785 23:39:02.710152 best_step = 9
4786 23:39:02.710611
4787 23:39:02.710975 ==
4788 23:39:02.713250 Dram Type= 6, Freq= 0, CH_1, rank 1
4789 23:39:02.716689 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4790 23:39:02.717152 ==
4791 23:39:02.719939 RX Vref Scan: 0
4792 23:39:02.720394
4793 23:39:02.720799 RX Vref 0 -> 0, step: 1
4794 23:39:02.721137
4795 23:39:02.723446 RX Delay -163 -> 252, step: 8
4796 23:39:02.730620 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4797 23:39:02.734398 iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288
4798 23:39:02.737741 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4799 23:39:02.740757 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4800 23:39:02.747305 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4801 23:39:02.750213 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4802 23:39:02.753439 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4803 23:39:02.757236 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4804 23:39:02.760132 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4805 23:39:02.767310 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4806 23:39:02.770522 iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296
4807 23:39:02.773394 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4808 23:39:02.777067 iDelay=205, Bit 12, Center 56 (-91 ~ 204) 296
4809 23:39:02.780129 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4810 23:39:02.786834 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4811 23:39:02.790305 iDelay=205, Bit 15, Center 56 (-91 ~ 204) 296
4812 23:39:02.790721 ==
4813 23:39:02.793215 Dram Type= 6, Freq= 0, CH_1, rank 1
4814 23:39:02.796765 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4815 23:39:02.797185 ==
4816 23:39:02.799961 DQS Delay:
4817 23:39:02.800373 DQS0 = 0, DQS1 = 0
4818 23:39:02.800701 DQM Delay:
4819 23:39:02.803670 DQM0 = 49, DQM1 = 46
4820 23:39:02.804207 DQ Delay:
4821 23:39:02.806882 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4822 23:39:02.810206 DQ4 =48, DQ5 =60, DQ6 =60, DQ7 =48
4823 23:39:02.813410 DQ8 =32, DQ9 =32, DQ10 =48, DQ11 =40
4824 23:39:02.816341 DQ12 =56, DQ13 =52, DQ14 =52, DQ15 =56
4825 23:39:02.816773
4826 23:39:02.817207
4827 23:39:02.826809 [DQSOSCAuto] RK1, (LSB)MR18= 0x6c24, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 389 ps
4828 23:39:02.829967 CH1 RK1: MR19=808, MR18=6C24
4829 23:39:02.833267 CH1_RK1: MR19=0x808, MR18=0x6C24, DQSOSC=389, MR23=63, INC=173, DEC=115
4830 23:39:02.836470 [RxdqsGatingPostProcess] freq 600
4831 23:39:02.843318 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4832 23:39:02.846578 Pre-setting of DQS Precalculation
4833 23:39:02.849897 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4834 23:39:02.859904 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4835 23:39:02.866120 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4836 23:39:02.866617
4837 23:39:02.866956
4838 23:39:02.870195 [Calibration Summary] 1200 Mbps
4839 23:39:02.870742 CH 0, Rank 0
4840 23:39:02.873794 SW Impedance : PASS
4841 23:39:02.874414 DUTY Scan : NO K
4842 23:39:02.876889 ZQ Calibration : PASS
4843 23:39:02.879837 Jitter Meter : NO K
4844 23:39:02.880302 CBT Training : PASS
4845 23:39:02.883342 Write leveling : PASS
4846 23:39:02.886456 RX DQS gating : PASS
4847 23:39:02.886919 RX DQ/DQS(RDDQC) : PASS
4848 23:39:02.889631 TX DQ/DQS : PASS
4849 23:39:02.890100 RX DATLAT : PASS
4850 23:39:02.892918 RX DQ/DQS(Engine): PASS
4851 23:39:02.896220 TX OE : NO K
4852 23:39:02.896682 All Pass.
4853 23:39:02.897050
4854 23:39:02.897390 CH 0, Rank 1
4855 23:39:02.900093 SW Impedance : PASS
4856 23:39:02.902913 DUTY Scan : NO K
4857 23:39:02.903372 ZQ Calibration : PASS
4858 23:39:02.906379 Jitter Meter : NO K
4859 23:39:02.909339 CBT Training : PASS
4860 23:39:02.909883 Write leveling : PASS
4861 23:39:02.912609 RX DQS gating : PASS
4862 23:39:02.915928 RX DQ/DQS(RDDQC) : PASS
4863 23:39:02.916426 TX DQ/DQS : PASS
4864 23:39:02.919566 RX DATLAT : PASS
4865 23:39:02.922880 RX DQ/DQS(Engine): PASS
4866 23:39:02.923341 TX OE : NO K
4867 23:39:02.926707 All Pass.
4868 23:39:02.927239
4869 23:39:02.927685 CH 1, Rank 0
4870 23:39:02.929681 SW Impedance : PASS
4871 23:39:02.930117 DUTY Scan : NO K
4872 23:39:02.933009 ZQ Calibration : PASS
4873 23:39:02.936443 Jitter Meter : NO K
4874 23:39:02.936979 CBT Training : PASS
4875 23:39:02.939611 Write leveling : PASS
4876 23:39:02.943160 RX DQS gating : PASS
4877 23:39:02.943699 RX DQ/DQS(RDDQC) : PASS
4878 23:39:02.946097 TX DQ/DQS : PASS
4879 23:39:02.946514 RX DATLAT : PASS
4880 23:39:02.949255 RX DQ/DQS(Engine): PASS
4881 23:39:02.953340 TX OE : NO K
4882 23:39:02.953920 All Pass.
4883 23:39:02.954260
4884 23:39:02.954566 CH 1, Rank 1
4885 23:39:02.956062 SW Impedance : PASS
4886 23:39:02.959327 DUTY Scan : NO K
4887 23:39:02.959739 ZQ Calibration : PASS
4888 23:39:02.962785 Jitter Meter : NO K
4889 23:39:02.965783 CBT Training : PASS
4890 23:39:02.966211 Write leveling : PASS
4891 23:39:02.969180 RX DQS gating : PASS
4892 23:39:02.972720 RX DQ/DQS(RDDQC) : PASS
4893 23:39:02.973257 TX DQ/DQS : PASS
4894 23:39:02.976339 RX DATLAT : PASS
4895 23:39:02.979121 RX DQ/DQS(Engine): PASS
4896 23:39:02.979535 TX OE : NO K
4897 23:39:02.982959 All Pass.
4898 23:39:02.983482
4899 23:39:02.983816 DramC Write-DBI off
4900 23:39:02.985979 PER_BANK_REFRESH: Hybrid Mode
4901 23:39:02.986398 TX_TRACKING: ON
4902 23:39:02.996245 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4903 23:39:02.999879 [FAST_K] Save calibration result to emmc
4904 23:39:03.002894 dramc_set_vcore_voltage set vcore to 662500
4905 23:39:03.005996 Read voltage for 933, 3
4906 23:39:03.006570 Vio18 = 0
4907 23:39:03.009698 Vcore = 662500
4908 23:39:03.010115 Vdram = 0
4909 23:39:03.010509 Vddq = 0
4910 23:39:03.010819 Vmddr = 0
4911 23:39:03.016009 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4912 23:39:03.022659 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4913 23:39:03.023183 MEM_TYPE=3, freq_sel=17
4914 23:39:03.025786 sv_algorithm_assistance_LP4_1600
4915 23:39:03.029260 ============ PULL DRAM RESETB DOWN ============
4916 23:39:03.035902 ========== PULL DRAM RESETB DOWN end =========
4917 23:39:03.039131 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4918 23:39:03.042384 ===================================
4919 23:39:03.045739 LPDDR4 DRAM CONFIGURATION
4920 23:39:03.049633 ===================================
4921 23:39:03.050200 EX_ROW_EN[0] = 0x0
4922 23:39:03.052496 EX_ROW_EN[1] = 0x0
4923 23:39:03.052956 LP4Y_EN = 0x0
4924 23:39:03.055853 WORK_FSP = 0x0
4925 23:39:03.056405 WL = 0x3
4926 23:39:03.059326 RL = 0x3
4927 23:39:03.059802 BL = 0x2
4928 23:39:03.062650 RPST = 0x0
4929 23:39:03.065862 RD_PRE = 0x0
4930 23:39:03.066419 WR_PRE = 0x1
4931 23:39:03.069135 WR_PST = 0x0
4932 23:39:03.069744 DBI_WR = 0x0
4933 23:39:03.072034 DBI_RD = 0x0
4934 23:39:03.072495 OTF = 0x1
4935 23:39:03.075758 ===================================
4936 23:39:03.078783 ===================================
4937 23:39:03.082471 ANA top config
4938 23:39:03.085708 ===================================
4939 23:39:03.086268 DLL_ASYNC_EN = 0
4940 23:39:03.089053 ALL_SLAVE_EN = 1
4941 23:39:03.092051 NEW_RANK_MODE = 1
4942 23:39:03.096000 DLL_IDLE_MODE = 1
4943 23:39:03.096573 LP45_APHY_COMB_EN = 1
4944 23:39:03.098797 TX_ODT_DIS = 1
4945 23:39:03.102952 NEW_8X_MODE = 1
4946 23:39:03.105733 ===================================
4947 23:39:03.109243 ===================================
4948 23:39:03.112419 data_rate = 1866
4949 23:39:03.115795 CKR = 1
4950 23:39:03.118913 DQ_P2S_RATIO = 8
4951 23:39:03.119477 ===================================
4952 23:39:03.121923 CA_P2S_RATIO = 8
4953 23:39:03.125993 DQ_CA_OPEN = 0
4954 23:39:03.128932 DQ_SEMI_OPEN = 0
4955 23:39:03.132608 CA_SEMI_OPEN = 0
4956 23:39:03.135610 CA_FULL_RATE = 0
4957 23:39:03.136075 DQ_CKDIV4_EN = 1
4958 23:39:03.138839 CA_CKDIV4_EN = 1
4959 23:39:03.142496 CA_PREDIV_EN = 0
4960 23:39:03.145470 PH8_DLY = 0
4961 23:39:03.149057 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4962 23:39:03.152092 DQ_AAMCK_DIV = 4
4963 23:39:03.152658 CA_AAMCK_DIV = 4
4964 23:39:03.155268 CA_ADMCK_DIV = 4
4965 23:39:03.158794 DQ_TRACK_CA_EN = 0
4966 23:39:03.161790 CA_PICK = 933
4967 23:39:03.165372 CA_MCKIO = 933
4968 23:39:03.169014 MCKIO_SEMI = 0
4969 23:39:03.172048 PLL_FREQ = 3732
4970 23:39:03.172641 DQ_UI_PI_RATIO = 32
4971 23:39:03.175315 CA_UI_PI_RATIO = 0
4972 23:39:03.178945 ===================================
4973 23:39:03.181977 ===================================
4974 23:39:03.185179 memory_type:LPDDR4
4975 23:39:03.188802 GP_NUM : 10
4976 23:39:03.189365 SRAM_EN : 1
4977 23:39:03.192093 MD32_EN : 0
4978 23:39:03.195096 ===================================
4979 23:39:03.198316 [ANA_INIT] >>>>>>>>>>>>>>
4980 23:39:03.198778 <<<<<< [CONFIGURE PHASE]: ANA_TX
4981 23:39:03.202524 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4982 23:39:03.205674 ===================================
4983 23:39:03.208561 data_rate = 1866,PCW = 0X8f00
4984 23:39:03.212231 ===================================
4985 23:39:03.215507 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4986 23:39:03.221903 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4987 23:39:03.229077 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4988 23:39:03.231530 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4989 23:39:03.235190 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4990 23:39:03.238627 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4991 23:39:03.241906 [ANA_INIT] flow start
4992 23:39:03.242370 [ANA_INIT] PLL >>>>>>>>
4993 23:39:03.245006 [ANA_INIT] PLL <<<<<<<<
4994 23:39:03.248722 [ANA_INIT] MIDPI >>>>>>>>
4995 23:39:03.249281 [ANA_INIT] MIDPI <<<<<<<<
4996 23:39:03.251956 [ANA_INIT] DLL >>>>>>>>
4997 23:39:03.255362 [ANA_INIT] flow end
4998 23:39:03.258371 ============ LP4 DIFF to SE enter ============
4999 23:39:03.261808 ============ LP4 DIFF to SE exit ============
5000 23:39:03.265016 [ANA_INIT] <<<<<<<<<<<<<
5001 23:39:03.268369 [Flow] Enable top DCM control >>>>>
5002 23:39:03.271984 [Flow] Enable top DCM control <<<<<
5003 23:39:03.274861 Enable DLL master slave shuffle
5004 23:39:03.278473 ==============================================================
5005 23:39:03.281200 Gating Mode config
5006 23:39:03.288639 ==============================================================
5007 23:39:03.289200 Config description:
5008 23:39:03.299039 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5009 23:39:03.304629 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5010 23:39:03.311221 SELPH_MODE 0: By rank 1: By Phase
5011 23:39:03.314725 ==============================================================
5012 23:39:03.318234 GAT_TRACK_EN = 1
5013 23:39:03.321376 RX_GATING_MODE = 2
5014 23:39:03.324964 RX_GATING_TRACK_MODE = 2
5015 23:39:03.328024 SELPH_MODE = 1
5016 23:39:03.331400 PICG_EARLY_EN = 1
5017 23:39:03.334569 VALID_LAT_VALUE = 1
5018 23:39:03.337827 ==============================================================
5019 23:39:03.341384 Enter into Gating configuration >>>>
5020 23:39:03.344411 Exit from Gating configuration <<<<
5021 23:39:03.348017 Enter into DVFS_PRE_config >>>>>
5022 23:39:03.361320 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5023 23:39:03.364557 Exit from DVFS_PRE_config <<<<<
5024 23:39:03.367820 Enter into PICG configuration >>>>
5025 23:39:03.368381 Exit from PICG configuration <<<<
5026 23:39:03.371449 [RX_INPUT] configuration >>>>>
5027 23:39:03.374419 [RX_INPUT] configuration <<<<<
5028 23:39:03.380811 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5029 23:39:03.384485 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5030 23:39:03.390994 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5031 23:39:03.397866 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5032 23:39:03.404916 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5033 23:39:03.411127 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5034 23:39:03.413814 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5035 23:39:03.417356 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5036 23:39:03.420636 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5037 23:39:03.427694 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5038 23:39:03.430455 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5039 23:39:03.433930 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5040 23:39:03.437256 ===================================
5041 23:39:03.440553 LPDDR4 DRAM CONFIGURATION
5042 23:39:03.444125 ===================================
5043 23:39:03.447080 EX_ROW_EN[0] = 0x0
5044 23:39:03.447543 EX_ROW_EN[1] = 0x0
5045 23:39:03.450497 LP4Y_EN = 0x0
5046 23:39:03.450958 WORK_FSP = 0x0
5047 23:39:03.454249 WL = 0x3
5048 23:39:03.454818 RL = 0x3
5049 23:39:03.457776 BL = 0x2
5050 23:39:03.458331 RPST = 0x0
5051 23:39:03.460536 RD_PRE = 0x0
5052 23:39:03.461096 WR_PRE = 0x1
5053 23:39:03.464065 WR_PST = 0x0
5054 23:39:03.464628 DBI_WR = 0x0
5055 23:39:03.467582 DBI_RD = 0x0
5056 23:39:03.468149 OTF = 0x1
5057 23:39:03.470371 ===================================
5058 23:39:03.477157 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5059 23:39:03.480571 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5060 23:39:03.484331 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5061 23:39:03.487217 ===================================
5062 23:39:03.490803 LPDDR4 DRAM CONFIGURATION
5063 23:39:03.494229 ===================================
5064 23:39:03.497116 EX_ROW_EN[0] = 0x10
5065 23:39:03.497674 EX_ROW_EN[1] = 0x0
5066 23:39:03.500041 LP4Y_EN = 0x0
5067 23:39:03.500502 WORK_FSP = 0x0
5068 23:39:03.503611 WL = 0x3
5069 23:39:03.504070 RL = 0x3
5070 23:39:03.507017 BL = 0x2
5071 23:39:03.507669 RPST = 0x0
5072 23:39:03.510153 RD_PRE = 0x0
5073 23:39:03.510799 WR_PRE = 0x1
5074 23:39:03.513477 WR_PST = 0x0
5075 23:39:03.513941 DBI_WR = 0x0
5076 23:39:03.516907 DBI_RD = 0x0
5077 23:39:03.517328 OTF = 0x1
5078 23:39:03.520140 ===================================
5079 23:39:03.526969 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5080 23:39:03.531530 nWR fixed to 30
5081 23:39:03.534953 [ModeRegInit_LP4] CH0 RK0
5082 23:39:03.535475 [ModeRegInit_LP4] CH0 RK1
5083 23:39:03.537975 [ModeRegInit_LP4] CH1 RK0
5084 23:39:03.541722 [ModeRegInit_LP4] CH1 RK1
5085 23:39:03.542329 match AC timing 9
5086 23:39:03.548552 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5087 23:39:03.551397 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5088 23:39:03.554598 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5089 23:39:03.562072 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5090 23:39:03.564923 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5091 23:39:03.565348 ==
5092 23:39:03.568259 Dram Type= 6, Freq= 0, CH_0, rank 0
5093 23:39:03.571900 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5094 23:39:03.572516 ==
5095 23:39:03.578098 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5096 23:39:03.585146 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5097 23:39:03.588232 [CA 0] Center 37 (6~68) winsize 63
5098 23:39:03.591334 [CA 1] Center 37 (6~68) winsize 63
5099 23:39:03.594389 [CA 2] Center 34 (4~65) winsize 62
5100 23:39:03.598195 [CA 3] Center 34 (3~65) winsize 63
5101 23:39:03.601567 [CA 4] Center 33 (3~64) winsize 62
5102 23:39:03.604749 [CA 5] Center 32 (2~62) winsize 61
5103 23:39:03.605265
5104 23:39:03.608329 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5105 23:39:03.608850
5106 23:39:03.611503 [CATrainingPosCal] consider 1 rank data
5107 23:39:03.614770 u2DelayCellTimex100 = 270/100 ps
5108 23:39:03.617689 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5109 23:39:03.621943 CA1 delay=37 (6~68),Diff = 5 PI (31 cell)
5110 23:39:03.625002 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5111 23:39:03.627871 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5112 23:39:03.631310 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5113 23:39:03.634814 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5114 23:39:03.637953
5115 23:39:03.641117 CA PerBit enable=1, Macro0, CA PI delay=32
5116 23:39:03.641672
5117 23:39:03.645153 [CBTSetCACLKResult] CA Dly = 32
5118 23:39:03.645712 CS Dly: 5 (0~36)
5119 23:39:03.646050 ==
5120 23:39:03.647969 Dram Type= 6, Freq= 0, CH_0, rank 1
5121 23:39:03.651218 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5122 23:39:03.651743 ==
5123 23:39:03.657668 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5124 23:39:03.664051 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5125 23:39:03.667805 [CA 0] Center 37 (6~68) winsize 63
5126 23:39:03.671229 [CA 1] Center 37 (7~68) winsize 62
5127 23:39:03.674184 [CA 2] Center 34 (4~65) winsize 62
5128 23:39:03.677326 [CA 3] Center 34 (3~65) winsize 63
5129 23:39:03.681050 [CA 4] Center 33 (3~63) winsize 61
5130 23:39:03.684332 [CA 5] Center 32 (2~62) winsize 61
5131 23:39:03.684855
5132 23:39:03.687054 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5133 23:39:03.687472
5134 23:39:03.690653 [CATrainingPosCal] consider 2 rank data
5135 23:39:03.693821 u2DelayCellTimex100 = 270/100 ps
5136 23:39:03.697182 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5137 23:39:03.701011 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5138 23:39:03.703841 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5139 23:39:03.711082 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5140 23:39:03.714009 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5141 23:39:03.717474 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5142 23:39:03.717925
5143 23:39:03.720670 CA PerBit enable=1, Macro0, CA PI delay=32
5144 23:39:03.721088
5145 23:39:03.723720 [CBTSetCACLKResult] CA Dly = 32
5146 23:39:03.724239 CS Dly: 6 (0~38)
5147 23:39:03.724576
5148 23:39:03.727272 ----->DramcWriteLeveling(PI) begin...
5149 23:39:03.727798 ==
5150 23:39:03.730524 Dram Type= 6, Freq= 0, CH_0, rank 0
5151 23:39:03.737498 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5152 23:39:03.738065 ==
5153 23:39:03.740571 Write leveling (Byte 0): 32 => 32
5154 23:39:03.743908 Write leveling (Byte 1): 31 => 31
5155 23:39:03.744428 DramcWriteLeveling(PI) end<-----
5156 23:39:03.747010
5157 23:39:03.747528 ==
5158 23:39:03.750249 Dram Type= 6, Freq= 0, CH_0, rank 0
5159 23:39:03.754459 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5160 23:39:03.754980 ==
5161 23:39:03.757864 [Gating] SW mode calibration
5162 23:39:03.763362 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5163 23:39:03.767101 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5164 23:39:03.773744 0 14 0 | B1->B0 | 2b2b 3434 | 1 1 | (1 1) (1 1)
5165 23:39:03.776959 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5166 23:39:03.780201 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5167 23:39:03.787301 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5168 23:39:03.790151 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5169 23:39:03.793960 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5170 23:39:03.800357 0 14 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
5171 23:39:03.803593 0 14 28 | B1->B0 | 3434 2d2d | 1 0 | (1 1) (1 0)
5172 23:39:03.806567 0 15 0 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
5173 23:39:03.813432 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5174 23:39:03.816643 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5175 23:39:03.820289 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5176 23:39:03.826658 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5177 23:39:03.830315 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5178 23:39:03.834063 0 15 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5179 23:39:03.840145 0 15 28 | B1->B0 | 2828 3b3b | 0 1 | (0 0) (0 0)
5180 23:39:03.843674 1 0 0 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
5181 23:39:03.847110 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5182 23:39:03.853836 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5183 23:39:03.856741 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5184 23:39:03.859971 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5185 23:39:03.866564 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5186 23:39:03.870082 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5187 23:39:03.873664 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5188 23:39:03.880039 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5189 23:39:03.883289 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5190 23:39:03.886532 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5191 23:39:03.890321 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5192 23:39:03.896671 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5193 23:39:03.899807 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5194 23:39:03.903509 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5195 23:39:03.909833 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5196 23:39:03.913066 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5197 23:39:03.916749 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5198 23:39:03.923042 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5199 23:39:03.925974 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5200 23:39:03.929508 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5201 23:39:03.936183 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5202 23:39:03.939536 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5203 23:39:03.942831 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5204 23:39:03.949670 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5205 23:39:03.952764 Total UI for P1: 0, mck2ui 16
5206 23:39:03.956281 best dqsien dly found for B0: ( 1, 2, 26)
5207 23:39:03.959299 Total UI for P1: 0, mck2ui 16
5208 23:39:03.962513 best dqsien dly found for B1: ( 1, 2, 28)
5209 23:39:03.966260 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5210 23:39:03.969495 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5211 23:39:03.970132
5212 23:39:03.972552 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5213 23:39:03.975847 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5214 23:39:03.979197 [Gating] SW calibration Done
5215 23:39:03.979768 ==
5216 23:39:03.982347 Dram Type= 6, Freq= 0, CH_0, rank 0
5217 23:39:03.986066 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5218 23:39:03.986641 ==
5219 23:39:03.989193 RX Vref Scan: 0
5220 23:39:03.989691
5221 23:39:03.990062 RX Vref 0 -> 0, step: 1
5222 23:39:03.992835
5223 23:39:03.993484 RX Delay -80 -> 252, step: 8
5224 23:39:03.999327 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5225 23:39:04.002818 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5226 23:39:04.005528 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5227 23:39:04.009736 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5228 23:39:04.012889 iDelay=208, Bit 4, Center 111 (24 ~ 199) 176
5229 23:39:04.016522 iDelay=208, Bit 5, Center 95 (8 ~ 183) 176
5230 23:39:04.019516 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5231 23:39:04.026058 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5232 23:39:04.029423 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5233 23:39:04.032430 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5234 23:39:04.036313 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5235 23:39:04.039048 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5236 23:39:04.045786 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5237 23:39:04.049204 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5238 23:39:04.052617 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5239 23:39:04.056147 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5240 23:39:04.056710 ==
5241 23:39:04.059095 Dram Type= 6, Freq= 0, CH_0, rank 0
5242 23:39:04.062405 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5243 23:39:04.065468 ==
5244 23:39:04.066109 DQS Delay:
5245 23:39:04.066485 DQS0 = 0, DQS1 = 0
5246 23:39:04.068786 DQM Delay:
5247 23:39:04.069246 DQM0 = 105, DQM1 = 94
5248 23:39:04.072682 DQ Delay:
5249 23:39:04.075328 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5250 23:39:04.079044 DQ4 =111, DQ5 =95, DQ6 =115, DQ7 =115
5251 23:39:04.081984 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =91
5252 23:39:04.085392 DQ12 =99, DQ13 =103, DQ14 =103, DQ15 =99
5253 23:39:04.085904
5254 23:39:04.086273
5255 23:39:04.086617 ==
5256 23:39:04.088846 Dram Type= 6, Freq= 0, CH_0, rank 0
5257 23:39:04.092576 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5258 23:39:04.093154 ==
5259 23:39:04.093524
5260 23:39:04.093929
5261 23:39:04.096083 TX Vref Scan disable
5262 23:39:04.096714 == TX Byte 0 ==
5263 23:39:04.102094 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5264 23:39:04.105799 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5265 23:39:04.106408 == TX Byte 1 ==
5266 23:39:04.112626 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5267 23:39:04.115549 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5268 23:39:04.116013 ==
5269 23:39:04.119042 Dram Type= 6, Freq= 0, CH_0, rank 0
5270 23:39:04.122176 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5271 23:39:04.122640 ==
5272 23:39:04.123005
5273 23:39:04.125791
5274 23:39:04.126353 TX Vref Scan disable
5275 23:39:04.128911 == TX Byte 0 ==
5276 23:39:04.132291 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5277 23:39:04.135405 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5278 23:39:04.138774 == TX Byte 1 ==
5279 23:39:04.142321 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5280 23:39:04.148815 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5281 23:39:04.149388
5282 23:39:04.149860 [DATLAT]
5283 23:39:04.150220 Freq=933, CH0 RK0
5284 23:39:04.150557
5285 23:39:04.151694 DATLAT Default: 0xd
5286 23:39:04.152158 0, 0xFFFF, sum = 0
5287 23:39:04.155609 1, 0xFFFF, sum = 0
5288 23:39:04.156191 2, 0xFFFF, sum = 0
5289 23:39:04.158607 3, 0xFFFF, sum = 0
5290 23:39:04.159079 4, 0xFFFF, sum = 0
5291 23:39:04.162021 5, 0xFFFF, sum = 0
5292 23:39:04.165249 6, 0xFFFF, sum = 0
5293 23:39:04.165886 7, 0xFFFF, sum = 0
5294 23:39:04.168989 8, 0xFFFF, sum = 0
5295 23:39:04.169617 9, 0xFFFF, sum = 0
5296 23:39:04.171925 10, 0x0, sum = 1
5297 23:39:04.172508 11, 0x0, sum = 2
5298 23:39:04.172892 12, 0x0, sum = 3
5299 23:39:04.175517 13, 0x0, sum = 4
5300 23:39:04.176090 best_step = 11
5301 23:39:04.176479
5302 23:39:04.178279 ==
5303 23:39:04.178749 Dram Type= 6, Freq= 0, CH_0, rank 0
5304 23:39:04.185446 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5305 23:39:04.186046 ==
5306 23:39:04.186417 RX Vref Scan: 1
5307 23:39:04.186761
5308 23:39:04.188532 RX Vref 0 -> 0, step: 1
5309 23:39:04.189014
5310 23:39:04.192429 RX Delay -53 -> 252, step: 4
5311 23:39:04.193021
5312 23:39:04.194820 Set Vref, RX VrefLevel [Byte0]: 54
5313 23:39:04.198298 [Byte1]: 55
5314 23:39:04.198773
5315 23:39:04.201397 Final RX Vref Byte 0 = 54 to rank0
5316 23:39:04.204813 Final RX Vref Byte 1 = 55 to rank0
5317 23:39:04.208868 Final RX Vref Byte 0 = 54 to rank1
5318 23:39:04.212221 Final RX Vref Byte 1 = 55 to rank1==
5319 23:39:04.214983 Dram Type= 6, Freq= 0, CH_0, rank 0
5320 23:39:04.218175 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5321 23:39:04.218674 ==
5322 23:39:04.221984 DQS Delay:
5323 23:39:04.222504 DQS0 = 0, DQS1 = 0
5324 23:39:04.225333 DQM Delay:
5325 23:39:04.225908 DQM0 = 104, DQM1 = 98
5326 23:39:04.226257 DQ Delay:
5327 23:39:04.228432 DQ0 =104, DQ1 =106, DQ2 =102, DQ3 =104
5328 23:39:04.235665 DQ4 =104, DQ5 =96, DQ6 =112, DQ7 =110
5329 23:39:04.236187 DQ8 =86, DQ9 =88, DQ10 =96, DQ11 =92
5330 23:39:04.242162 DQ12 =104, DQ13 =104, DQ14 =108, DQ15 =106
5331 23:39:04.242735
5332 23:39:04.243109
5333 23:39:04.248413 [DQSOSCAuto] RK0, (LSB)MR18= 0x322a, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 406 ps
5334 23:39:04.251625 CH0 RK0: MR19=505, MR18=322A
5335 23:39:04.258203 CH0_RK0: MR19=0x505, MR18=0x322A, DQSOSC=406, MR23=63, INC=65, DEC=43
5336 23:39:04.258979
5337 23:39:04.261971 ----->DramcWriteLeveling(PI) begin...
5338 23:39:04.262557 ==
5339 23:39:04.265331 Dram Type= 6, Freq= 0, CH_0, rank 1
5340 23:39:04.268642 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5341 23:39:04.269208 ==
5342 23:39:04.272059 Write leveling (Byte 0): 32 => 32
5343 23:39:04.274785 Write leveling (Byte 1): 29 => 29
5344 23:39:04.278278 DramcWriteLeveling(PI) end<-----
5345 23:39:04.278971
5346 23:39:04.279364 ==
5347 23:39:04.281510 Dram Type= 6, Freq= 0, CH_0, rank 1
5348 23:39:04.284867 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5349 23:39:04.288023 ==
5350 23:39:04.288588 [Gating] SW mode calibration
5351 23:39:04.294745 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5352 23:39:04.301256 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5353 23:39:04.305015 0 14 0 | B1->B0 | 3434 3434 | 1 0 | (0 0) (0 0)
5354 23:39:04.311200 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5355 23:39:04.314323 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5356 23:39:04.317918 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5357 23:39:04.324388 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5358 23:39:04.327780 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5359 23:39:04.331059 0 14 24 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
5360 23:39:04.337425 0 14 28 | B1->B0 | 2f2f 2f2f | 0 0 | (0 1) (0 1)
5361 23:39:04.340960 0 15 0 | B1->B0 | 2424 2929 | 0 0 | (0 0) (0 0)
5362 23:39:04.344153 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5363 23:39:04.350641 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5364 23:39:04.354350 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5365 23:39:04.357393 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5366 23:39:04.364491 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5367 23:39:04.367955 0 15 24 | B1->B0 | 2828 2424 | 0 0 | (0 0) (0 0)
5368 23:39:04.370703 0 15 28 | B1->B0 | 3c3c 3737 | 0 0 | (0 0) (0 0)
5369 23:39:04.373898 1 0 0 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
5370 23:39:04.381169 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5371 23:39:04.383982 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5372 23:39:04.387496 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5373 23:39:04.394095 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5374 23:39:04.397145 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5375 23:39:04.401007 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5376 23:39:04.407877 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5377 23:39:04.410871 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5378 23:39:04.414262 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5379 23:39:04.421058 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5380 23:39:04.424119 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5381 23:39:04.427461 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5382 23:39:04.433657 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5383 23:39:04.437447 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5384 23:39:04.440737 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5385 23:39:04.447162 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5386 23:39:04.450351 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5387 23:39:04.453778 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5388 23:39:04.460416 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5389 23:39:04.463530 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5390 23:39:04.466992 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5391 23:39:04.473865 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5392 23:39:04.477090 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5393 23:39:04.479962 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5394 23:39:04.483265 Total UI for P1: 0, mck2ui 16
5395 23:39:04.487096 best dqsien dly found for B1: ( 1, 2, 30)
5396 23:39:04.493717 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5397 23:39:04.494184 Total UI for P1: 0, mck2ui 16
5398 23:39:04.500127 best dqsien dly found for B0: ( 1, 2, 30)
5399 23:39:04.503971 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5400 23:39:04.507479 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5401 23:39:04.508039
5402 23:39:04.510333 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5403 23:39:04.514171 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5404 23:39:04.517258 [Gating] SW calibration Done
5405 23:39:04.517843 ==
5406 23:39:04.520724 Dram Type= 6, Freq= 0, CH_0, rank 1
5407 23:39:04.523222 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5408 23:39:04.523870 ==
5409 23:39:04.526285 RX Vref Scan: 0
5410 23:39:04.526859
5411 23:39:04.527380 RX Vref 0 -> 0, step: 1
5412 23:39:04.527738
5413 23:39:04.529953 RX Delay -80 -> 252, step: 8
5414 23:39:04.533469 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5415 23:39:04.539761 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5416 23:39:04.543047 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5417 23:39:04.546428 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5418 23:39:04.549956 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5419 23:39:04.553622 iDelay=208, Bit 5, Center 99 (8 ~ 191) 184
5420 23:39:04.557135 iDelay=208, Bit 6, Center 111 (24 ~ 199) 176
5421 23:39:04.563315 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5422 23:39:04.566327 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5423 23:39:04.570107 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5424 23:39:04.573141 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5425 23:39:04.576963 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5426 23:39:04.579735 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5427 23:39:04.586811 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5428 23:39:04.590024 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5429 23:39:04.593384 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5430 23:39:04.593995 ==
5431 23:39:04.596730 Dram Type= 6, Freq= 0, CH_0, rank 1
5432 23:39:04.599964 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5433 23:39:04.600482 ==
5434 23:39:04.603459 DQS Delay:
5435 23:39:04.603977 DQS0 = 0, DQS1 = 0
5436 23:39:04.604317 DQM Delay:
5437 23:39:04.606401 DQM0 = 104, DQM1 = 94
5438 23:39:04.606823 DQ Delay:
5439 23:39:04.609713 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5440 23:39:04.613095 DQ4 =103, DQ5 =99, DQ6 =111, DQ7 =115
5441 23:39:04.616326 DQ8 =87, DQ9 =87, DQ10 =95, DQ11 =87
5442 23:39:04.619819 DQ12 =99, DQ13 =99, DQ14 =103, DQ15 =99
5443 23:39:04.620241
5444 23:39:04.620577
5445 23:39:04.623351 ==
5446 23:39:04.626265 Dram Type= 6, Freq= 0, CH_0, rank 1
5447 23:39:04.630003 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5448 23:39:04.630527 ==
5449 23:39:04.630869
5450 23:39:04.631182
5451 23:39:04.633070 TX Vref Scan disable
5452 23:39:04.633510 == TX Byte 0 ==
5453 23:39:04.636504 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5454 23:39:04.643603 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5455 23:39:04.644126 == TX Byte 1 ==
5456 23:39:04.650122 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5457 23:39:04.652765 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5458 23:39:04.653234 ==
5459 23:39:04.656318 Dram Type= 6, Freq= 0, CH_0, rank 1
5460 23:39:04.659849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5461 23:39:04.660416 ==
5462 23:39:04.660789
5463 23:39:04.661133
5464 23:39:04.662637 TX Vref Scan disable
5465 23:39:04.666032 == TX Byte 0 ==
5466 23:39:04.669621 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5467 23:39:04.672626 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5468 23:39:04.676473 == TX Byte 1 ==
5469 23:39:04.679574 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5470 23:39:04.682470 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5471 23:39:04.682969
5472 23:39:04.686327 [DATLAT]
5473 23:39:04.686790 Freq=933, CH0 RK1
5474 23:39:04.687161
5475 23:39:04.689335 DATLAT Default: 0xb
5476 23:39:04.689844 0, 0xFFFF, sum = 0
5477 23:39:04.692487 1, 0xFFFF, sum = 0
5478 23:39:04.692962 2, 0xFFFF, sum = 0
5479 23:39:04.695697 3, 0xFFFF, sum = 0
5480 23:39:04.696128 4, 0xFFFF, sum = 0
5481 23:39:04.700004 5, 0xFFFF, sum = 0
5482 23:39:04.700646 6, 0xFFFF, sum = 0
5483 23:39:04.703134 7, 0xFFFF, sum = 0
5484 23:39:04.703662 8, 0xFFFF, sum = 0
5485 23:39:04.705952 9, 0xFFFF, sum = 0
5486 23:39:04.706384 10, 0x0, sum = 1
5487 23:39:04.709223 11, 0x0, sum = 2
5488 23:39:04.709695 12, 0x0, sum = 3
5489 23:39:04.712534 13, 0x0, sum = 4
5490 23:39:04.712962 best_step = 11
5491 23:39:04.713297
5492 23:39:04.713651 ==
5493 23:39:04.716193 Dram Type= 6, Freq= 0, CH_0, rank 1
5494 23:39:04.722596 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5495 23:39:04.723291 ==
5496 23:39:04.723888 RX Vref Scan: 0
5497 23:39:04.724463
5498 23:39:04.725862 RX Vref 0 -> 0, step: 1
5499 23:39:04.726262
5500 23:39:04.729469 RX Delay -45 -> 252, step: 4
5501 23:39:04.732388 iDelay=199, Bit 0, Center 102 (15 ~ 190) 176
5502 23:39:04.735857 iDelay=199, Bit 1, Center 108 (23 ~ 194) 172
5503 23:39:04.742535 iDelay=199, Bit 2, Center 102 (15 ~ 190) 176
5504 23:39:04.745934 iDelay=199, Bit 3, Center 102 (15 ~ 190) 176
5505 23:39:04.749205 iDelay=199, Bit 4, Center 106 (19 ~ 194) 176
5506 23:39:04.752432 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5507 23:39:04.755755 iDelay=199, Bit 6, Center 108 (23 ~ 194) 172
5508 23:39:04.762457 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5509 23:39:04.765791 iDelay=199, Bit 8, Center 88 (7 ~ 170) 164
5510 23:39:04.769135 iDelay=199, Bit 9, Center 86 (3 ~ 170) 168
5511 23:39:04.772209 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5512 23:39:04.775817 iDelay=199, Bit 11, Center 88 (7 ~ 170) 164
5513 23:39:04.779406 iDelay=199, Bit 12, Center 102 (19 ~ 186) 168
5514 23:39:04.785716 iDelay=199, Bit 13, Center 100 (15 ~ 186) 172
5515 23:39:04.789173 iDelay=199, Bit 14, Center 104 (19 ~ 190) 172
5516 23:39:04.792418 iDelay=199, Bit 15, Center 102 (19 ~ 186) 168
5517 23:39:04.792933 ==
5518 23:39:04.795659 Dram Type= 6, Freq= 0, CH_0, rank 1
5519 23:39:04.798735 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5520 23:39:04.801963 ==
5521 23:39:04.802378 DQS Delay:
5522 23:39:04.802705 DQS0 = 0, DQS1 = 0
5523 23:39:04.805833 DQM Delay:
5524 23:39:04.806402 DQM0 = 104, DQM1 = 95
5525 23:39:04.809083 DQ Delay:
5526 23:39:04.812340 DQ0 =102, DQ1 =108, DQ2 =102, DQ3 =102
5527 23:39:04.815574 DQ4 =106, DQ5 =98, DQ6 =108, DQ7 =112
5528 23:39:04.819300 DQ8 =88, DQ9 =86, DQ10 =94, DQ11 =88
5529 23:39:04.822162 DQ12 =102, DQ13 =100, DQ14 =104, DQ15 =102
5530 23:39:04.822585
5531 23:39:04.822914
5532 23:39:04.829068 [DQSOSCAuto] RK1, (LSB)MR18= 0x2a04, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 408 ps
5533 23:39:04.832207 CH0 RK1: MR19=505, MR18=2A04
5534 23:39:04.839004 CH0_RK1: MR19=0x505, MR18=0x2A04, DQSOSC=408, MR23=63, INC=65, DEC=43
5535 23:39:04.842313 [RxdqsGatingPostProcess] freq 933
5536 23:39:04.845613 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5537 23:39:04.848766 best DQS0 dly(2T, 0.5T) = (0, 10)
5538 23:39:04.852552 best DQS1 dly(2T, 0.5T) = (0, 10)
5539 23:39:04.855345 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5540 23:39:04.858787 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5541 23:39:04.861825 best DQS0 dly(2T, 0.5T) = (0, 10)
5542 23:39:04.865334 best DQS1 dly(2T, 0.5T) = (0, 10)
5543 23:39:04.868541 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5544 23:39:04.871892 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5545 23:39:04.875372 Pre-setting of DQS Precalculation
5546 23:39:04.878547 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5547 23:39:04.882140 ==
5548 23:39:04.885226 Dram Type= 6, Freq= 0, CH_1, rank 0
5549 23:39:04.888759 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5550 23:39:04.889280 ==
5551 23:39:04.892082 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5552 23:39:04.898368 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5553 23:39:04.902463 [CA 0] Center 36 (6~67) winsize 62
5554 23:39:04.905024 [CA 1] Center 36 (6~67) winsize 62
5555 23:39:04.909523 [CA 2] Center 35 (5~65) winsize 61
5556 23:39:04.912361 [CA 3] Center 34 (4~65) winsize 62
5557 23:39:04.915931 [CA 4] Center 34 (4~65) winsize 62
5558 23:39:04.918819 [CA 5] Center 33 (3~64) winsize 62
5559 23:39:04.919384
5560 23:39:04.922116 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5561 23:39:04.922585
5562 23:39:04.925480 [CATrainingPosCal] consider 1 rank data
5563 23:39:04.928721 u2DelayCellTimex100 = 270/100 ps
5564 23:39:04.932316 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5565 23:39:04.935555 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5566 23:39:04.942356 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5567 23:39:04.945242 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5568 23:39:04.948850 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5569 23:39:04.951919 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5570 23:39:04.952489
5571 23:39:04.955610 CA PerBit enable=1, Macro0, CA PI delay=33
5572 23:39:04.956175
5573 23:39:04.958913 [CBTSetCACLKResult] CA Dly = 33
5574 23:39:04.959474 CS Dly: 6 (0~37)
5575 23:39:04.962068 ==
5576 23:39:04.965712 Dram Type= 6, Freq= 0, CH_1, rank 1
5577 23:39:04.968919 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5578 23:39:04.969491 ==
5579 23:39:04.971526 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5580 23:39:04.978285 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5581 23:39:04.982316 [CA 0] Center 36 (6~67) winsize 62
5582 23:39:04.985671 [CA 1] Center 37 (6~68) winsize 63
5583 23:39:04.988808 [CA 2] Center 35 (5~65) winsize 61
5584 23:39:04.991861 [CA 3] Center 34 (4~65) winsize 62
5585 23:39:04.995669 [CA 4] Center 34 (4~65) winsize 62
5586 23:39:04.998763 [CA 5] Center 33 (3~64) winsize 62
5587 23:39:04.999230
5588 23:39:05.001671 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5589 23:39:05.002139
5590 23:39:05.005358 [CATrainingPosCal] consider 2 rank data
5591 23:39:05.009159 u2DelayCellTimex100 = 270/100 ps
5592 23:39:05.012061 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5593 23:39:05.015542 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5594 23:39:05.022392 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5595 23:39:05.025505 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5596 23:39:05.028782 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5597 23:39:05.032093 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5598 23:39:05.032556
5599 23:39:05.035810 CA PerBit enable=1, Macro0, CA PI delay=33
5600 23:39:05.036373
5601 23:39:05.038719 [CBTSetCACLKResult] CA Dly = 33
5602 23:39:05.039278 CS Dly: 7 (0~39)
5603 23:39:05.039642
5604 23:39:05.041844 ----->DramcWriteLeveling(PI) begin...
5605 23:39:05.045969 ==
5606 23:39:05.048946 Dram Type= 6, Freq= 0, CH_1, rank 0
5607 23:39:05.052526 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5608 23:39:05.053089 ==
5609 23:39:05.055340 Write leveling (Byte 0): 26 => 26
5610 23:39:05.058651 Write leveling (Byte 1): 26 => 26
5611 23:39:05.062292 DramcWriteLeveling(PI) end<-----
5612 23:39:05.062854
5613 23:39:05.063222 ==
5614 23:39:05.065018 Dram Type= 6, Freq= 0, CH_1, rank 0
5615 23:39:05.069027 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5616 23:39:05.069643 ==
5617 23:39:05.072108 [Gating] SW mode calibration
5618 23:39:05.078609 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5619 23:39:05.085313 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5620 23:39:05.088075 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5621 23:39:05.091711 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5622 23:39:05.098303 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5623 23:39:05.102009 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5624 23:39:05.105236 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5625 23:39:05.111638 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5626 23:39:05.115327 0 14 24 | B1->B0 | 3131 2b2b | 1 1 | (1 1) (1 1)
5627 23:39:05.118286 0 14 28 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
5628 23:39:05.125148 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5629 23:39:05.128079 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5630 23:39:05.131763 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5631 23:39:05.134658 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5632 23:39:05.141858 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5633 23:39:05.145007 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5634 23:39:05.148924 0 15 24 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
5635 23:39:05.155019 0 15 28 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
5636 23:39:05.158608 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5637 23:39:05.161779 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5638 23:39:05.168693 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5639 23:39:05.171425 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5640 23:39:05.174974 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5641 23:39:05.181950 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5642 23:39:05.185209 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5643 23:39:05.188360 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5644 23:39:05.194956 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5645 23:39:05.198508 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5646 23:39:05.201119 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5647 23:39:05.208165 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5648 23:39:05.211714 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5649 23:39:05.214782 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5650 23:39:05.221236 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5651 23:39:05.224641 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5652 23:39:05.227762 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5653 23:39:05.234522 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5654 23:39:05.238297 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5655 23:39:05.241200 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5656 23:39:05.244789 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5657 23:39:05.251460 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5658 23:39:05.254620 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5659 23:39:05.257730 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5660 23:39:05.261200 Total UI for P1: 0, mck2ui 16
5661 23:39:05.264271 best dqsien dly found for B0: ( 1, 2, 24)
5662 23:39:05.267820 Total UI for P1: 0, mck2ui 16
5663 23:39:05.271184 best dqsien dly found for B1: ( 1, 2, 22)
5664 23:39:05.274254 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5665 23:39:05.281160 best DQS1 dly(MCK, UI, PI) = (1, 2, 22)
5666 23:39:05.281647
5667 23:39:05.284170 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5668 23:39:05.287545 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 22)
5669 23:39:05.291032 [Gating] SW calibration Done
5670 23:39:05.291597 ==
5671 23:39:05.294008 Dram Type= 6, Freq= 0, CH_1, rank 0
5672 23:39:05.297787 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5673 23:39:05.298365 ==
5674 23:39:05.298739 RX Vref Scan: 0
5675 23:39:05.300927
5676 23:39:05.301496 RX Vref 0 -> 0, step: 1
5677 23:39:05.302051
5678 23:39:05.304591 RX Delay -80 -> 252, step: 8
5679 23:39:05.307777 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5680 23:39:05.310361 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5681 23:39:05.317463 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5682 23:39:05.320994 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5683 23:39:05.324804 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5684 23:39:05.327181 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5685 23:39:05.330595 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5686 23:39:05.334211 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5687 23:39:05.340866 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5688 23:39:05.344149 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5689 23:39:05.347410 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5690 23:39:05.351013 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5691 23:39:05.354312 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5692 23:39:05.357208 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5693 23:39:05.364139 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5694 23:39:05.367103 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5695 23:39:05.367576 ==
5696 23:39:05.370675 Dram Type= 6, Freq= 0, CH_1, rank 0
5697 23:39:05.373992 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5698 23:39:05.374461 ==
5699 23:39:05.376932 DQS Delay:
5700 23:39:05.377397 DQS0 = 0, DQS1 = 0
5701 23:39:05.380136 DQM Delay:
5702 23:39:05.380600 DQM0 = 102, DQM1 = 98
5703 23:39:05.380973 DQ Delay:
5704 23:39:05.383439 DQ0 =103, DQ1 =95, DQ2 =91, DQ3 =99
5705 23:39:05.386995 DQ4 =99, DQ5 =115, DQ6 =115, DQ7 =103
5706 23:39:05.390213 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =91
5707 23:39:05.393341 DQ12 =107, DQ13 =103, DQ14 =103, DQ15 =107
5708 23:39:05.396746
5709 23:39:05.397166
5710 23:39:05.397504 ==
5711 23:39:05.400104 Dram Type= 6, Freq= 0, CH_1, rank 0
5712 23:39:05.403969 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5713 23:39:05.404540 ==
5714 23:39:05.404910
5715 23:39:05.405251
5716 23:39:05.407115 TX Vref Scan disable
5717 23:39:05.407530 == TX Byte 0 ==
5718 23:39:05.413548 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5719 23:39:05.417217 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5720 23:39:05.417827 == TX Byte 1 ==
5721 23:39:05.424033 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5722 23:39:05.427412 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5723 23:39:05.428014 ==
5724 23:39:05.430263 Dram Type= 6, Freq= 0, CH_1, rank 0
5725 23:39:05.433734 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5726 23:39:05.434325 ==
5727 23:39:05.434700
5728 23:39:05.435038
5729 23:39:05.437185 TX Vref Scan disable
5730 23:39:05.440922 == TX Byte 0 ==
5731 23:39:05.444052 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5732 23:39:05.447660 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5733 23:39:05.450216 == TX Byte 1 ==
5734 23:39:05.453747 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5735 23:39:05.456862 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5736 23:39:05.457430
5737 23:39:05.460643 [DATLAT]
5738 23:39:05.461242 Freq=933, CH1 RK0
5739 23:39:05.461667
5740 23:39:05.463339 DATLAT Default: 0xd
5741 23:39:05.463798 0, 0xFFFF, sum = 0
5742 23:39:05.466462 1, 0xFFFF, sum = 0
5743 23:39:05.466930 2, 0xFFFF, sum = 0
5744 23:39:05.470308 3, 0xFFFF, sum = 0
5745 23:39:05.470900 4, 0xFFFF, sum = 0
5746 23:39:05.473351 5, 0xFFFF, sum = 0
5747 23:39:05.473881 6, 0xFFFF, sum = 0
5748 23:39:05.476635 7, 0xFFFF, sum = 0
5749 23:39:05.477101 8, 0xFFFF, sum = 0
5750 23:39:05.480233 9, 0xFFFF, sum = 0
5751 23:39:05.480700 10, 0x0, sum = 1
5752 23:39:05.484050 11, 0x0, sum = 2
5753 23:39:05.484625 12, 0x0, sum = 3
5754 23:39:05.487325 13, 0x0, sum = 4
5755 23:39:05.487900 best_step = 11
5756 23:39:05.488273
5757 23:39:05.488615 ==
5758 23:39:05.490253 Dram Type= 6, Freq= 0, CH_1, rank 0
5759 23:39:05.496718 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5760 23:39:05.497275 ==
5761 23:39:05.497690 RX Vref Scan: 1
5762 23:39:05.498039
5763 23:39:05.500094 RX Vref 0 -> 0, step: 1
5764 23:39:05.500557
5765 23:39:05.503291 RX Delay -45 -> 252, step: 4
5766 23:39:05.503751
5767 23:39:05.506867 Set Vref, RX VrefLevel [Byte0]: 55
5768 23:39:05.510854 [Byte1]: 53
5769 23:39:05.511420
5770 23:39:05.513234 Final RX Vref Byte 0 = 55 to rank0
5771 23:39:05.516624 Final RX Vref Byte 1 = 53 to rank0
5772 23:39:05.519832 Final RX Vref Byte 0 = 55 to rank1
5773 23:39:05.523158 Final RX Vref Byte 1 = 53 to rank1==
5774 23:39:05.526503 Dram Type= 6, Freq= 0, CH_1, rank 0
5775 23:39:05.529904 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5776 23:39:05.530476 ==
5777 23:39:05.532967 DQS Delay:
5778 23:39:05.533462 DQS0 = 0, DQS1 = 0
5779 23:39:05.533874 DQM Delay:
5780 23:39:05.536303 DQM0 = 103, DQM1 = 99
5781 23:39:05.536762 DQ Delay:
5782 23:39:05.539768 DQ0 =106, DQ1 =98, DQ2 =94, DQ3 =102
5783 23:39:05.542975 DQ4 =102, DQ5 =112, DQ6 =110, DQ7 =104
5784 23:39:05.546451 DQ8 =90, DQ9 =92, DQ10 =98, DQ11 =94
5785 23:39:05.550152 DQ12 =106, DQ13 =104, DQ14 =106, DQ15 =108
5786 23:39:05.550723
5787 23:39:05.553356
5788 23:39:05.559830 [DQSOSCAuto] RK0, (LSB)MR18= 0x162e, (MSB)MR19= 0x505, tDQSOscB0 = 407 ps tDQSOscB1 = 414 ps
5789 23:39:05.562873 CH1 RK0: MR19=505, MR18=162E
5790 23:39:05.569822 CH1_RK0: MR19=0x505, MR18=0x162E, DQSOSC=407, MR23=63, INC=65, DEC=43
5791 23:39:05.570250
5792 23:39:05.572847 ----->DramcWriteLeveling(PI) begin...
5793 23:39:05.573360 ==
5794 23:39:05.576276 Dram Type= 6, Freq= 0, CH_1, rank 1
5795 23:39:05.579348 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5796 23:39:05.579938 ==
5797 23:39:05.582917 Write leveling (Byte 0): 28 => 28
5798 23:39:05.585840 Write leveling (Byte 1): 28 => 28
5799 23:39:05.589349 DramcWriteLeveling(PI) end<-----
5800 23:39:05.589809
5801 23:39:05.590149 ==
5802 23:39:05.592927 Dram Type= 6, Freq= 0, CH_1, rank 1
5803 23:39:05.596178 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5804 23:39:05.596597 ==
5805 23:39:05.599486 [Gating] SW mode calibration
5806 23:39:05.606553 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5807 23:39:05.612855 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5808 23:39:05.616398 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5809 23:39:05.619579 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5810 23:39:05.626523 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5811 23:39:05.629640 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5812 23:39:05.633302 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5813 23:39:05.639599 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5814 23:39:05.643236 0 14 24 | B1->B0 | 2c2c 3333 | 1 0 | (1 0) (0 0)
5815 23:39:05.645970 0 14 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5816 23:39:05.653454 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5817 23:39:05.656088 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5818 23:39:05.659483 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5819 23:39:05.666019 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5820 23:39:05.669654 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5821 23:39:05.672782 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5822 23:39:05.676086 0 15 24 | B1->B0 | 3737 2727 | 0 0 | (0 0) (0 0)
5823 23:39:05.683034 0 15 28 | B1->B0 | 4646 3e3e | 0 0 | (0 0) (0 0)
5824 23:39:05.685744 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5825 23:39:05.689662 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5826 23:39:05.696206 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5827 23:39:05.699338 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5828 23:39:05.702698 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5829 23:39:05.709530 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5830 23:39:05.713133 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5831 23:39:05.716085 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5832 23:39:05.723111 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5833 23:39:05.726005 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5834 23:39:05.729562 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5835 23:39:05.736399 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5836 23:39:05.739269 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5837 23:39:05.742401 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5838 23:39:05.749218 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5839 23:39:05.752765 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5840 23:39:05.756244 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5841 23:39:05.762578 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5842 23:39:05.766064 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5843 23:39:05.769423 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5844 23:39:05.775321 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5845 23:39:05.778419 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5846 23:39:05.782178 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5847 23:39:05.788540 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5848 23:39:05.789090 Total UI for P1: 0, mck2ui 16
5849 23:39:05.795501 best dqsien dly found for B0: ( 1, 2, 26)
5850 23:39:05.796073 Total UI for P1: 0, mck2ui 16
5851 23:39:05.802033 best dqsien dly found for B1: ( 1, 2, 24)
5852 23:39:05.805157 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5853 23:39:05.808569 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5854 23:39:05.809145
5855 23:39:05.811926 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5856 23:39:05.815754 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5857 23:39:05.818701 [Gating] SW calibration Done
5858 23:39:05.819159 ==
5859 23:39:05.821956 Dram Type= 6, Freq= 0, CH_1, rank 1
5860 23:39:05.825308 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5861 23:39:05.825930 ==
5862 23:39:05.828762 RX Vref Scan: 0
5863 23:39:05.829321
5864 23:39:05.829747 RX Vref 0 -> 0, step: 1
5865 23:39:05.830099
5866 23:39:05.831941 RX Delay -80 -> 252, step: 8
5867 23:39:05.835004 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5868 23:39:05.842492 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5869 23:39:05.845364 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5870 23:39:05.848575 iDelay=208, Bit 3, Center 95 (8 ~ 183) 176
5871 23:39:05.852080 iDelay=208, Bit 4, Center 95 (8 ~ 183) 176
5872 23:39:05.855089 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5873 23:39:05.858468 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5874 23:39:05.865399 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5875 23:39:05.868193 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5876 23:39:05.872194 iDelay=208, Bit 9, Center 91 (0 ~ 183) 184
5877 23:39:05.875253 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5878 23:39:05.878476 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5879 23:39:05.881752 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5880 23:39:05.888414 iDelay=208, Bit 13, Center 107 (16 ~ 199) 184
5881 23:39:05.891883 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5882 23:39:05.895358 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5883 23:39:05.895921 ==
5884 23:39:05.898234 Dram Type= 6, Freq= 0, CH_1, rank 1
5885 23:39:05.901571 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5886 23:39:05.902093 ==
5887 23:39:05.905329 DQS Delay:
5888 23:39:05.905937 DQS0 = 0, DQS1 = 0
5889 23:39:05.908352 DQM Delay:
5890 23:39:05.908954 DQM0 = 101, DQM1 = 99
5891 23:39:05.909331 DQ Delay:
5892 23:39:05.911904 DQ0 =107, DQ1 =99, DQ2 =91, DQ3 =95
5893 23:39:05.915011 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =99
5894 23:39:05.918623 DQ8 =87, DQ9 =91, DQ10 =99, DQ11 =91
5895 23:39:05.925247 DQ12 =107, DQ13 =107, DQ14 =103, DQ15 =107
5896 23:39:05.925745
5897 23:39:05.926116
5898 23:39:05.926456 ==
5899 23:39:05.928788 Dram Type= 6, Freq= 0, CH_1, rank 1
5900 23:39:05.932206 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5901 23:39:05.932763 ==
5902 23:39:05.933137
5903 23:39:05.933479
5904 23:39:05.935171 TX Vref Scan disable
5905 23:39:05.935634 == TX Byte 0 ==
5906 23:39:05.942199 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5907 23:39:05.945156 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5908 23:39:05.945760 == TX Byte 1 ==
5909 23:39:05.951670 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5910 23:39:05.955192 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5911 23:39:05.955807 ==
5912 23:39:05.958673 Dram Type= 6, Freq= 0, CH_1, rank 1
5913 23:39:05.962031 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5914 23:39:05.962609 ==
5915 23:39:05.963103
5916 23:39:05.963565
5917 23:39:05.964824 TX Vref Scan disable
5918 23:39:05.968327 == TX Byte 0 ==
5919 23:39:05.971681 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5920 23:39:05.975370 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5921 23:39:05.978509 == TX Byte 1 ==
5922 23:39:05.981905 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5923 23:39:05.984886 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5924 23:39:05.985465
5925 23:39:05.987838 [DATLAT]
5926 23:39:05.988336 Freq=933, CH1 RK1
5927 23:39:05.988705
5928 23:39:05.991700 DATLAT Default: 0xb
5929 23:39:05.992261 0, 0xFFFF, sum = 0
5930 23:39:05.994519 1, 0xFFFF, sum = 0
5931 23:39:05.994987 2, 0xFFFF, sum = 0
5932 23:39:05.997719 3, 0xFFFF, sum = 0
5933 23:39:05.998193 4, 0xFFFF, sum = 0
5934 23:39:06.001739 5, 0xFFFF, sum = 0
5935 23:39:06.002214 6, 0xFFFF, sum = 0
5936 23:39:06.004564 7, 0xFFFF, sum = 0
5937 23:39:06.005033 8, 0xFFFF, sum = 0
5938 23:39:06.008017 9, 0xFFFF, sum = 0
5939 23:39:06.008581 10, 0x0, sum = 1
5940 23:39:06.011597 11, 0x0, sum = 2
5941 23:39:06.012168 12, 0x0, sum = 3
5942 23:39:06.014699 13, 0x0, sum = 4
5943 23:39:06.015170 best_step = 11
5944 23:39:06.015538
5945 23:39:06.015881 ==
5946 23:39:06.017718 Dram Type= 6, Freq= 0, CH_1, rank 1
5947 23:39:06.025132 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5948 23:39:06.025750 ==
5949 23:39:06.026130 RX Vref Scan: 0
5950 23:39:06.026472
5951 23:39:06.027852 RX Vref 0 -> 0, step: 1
5952 23:39:06.028313
5953 23:39:06.031065 RX Delay -45 -> 252, step: 4
5954 23:39:06.034749 iDelay=203, Bit 0, Center 110 (27 ~ 194) 168
5955 23:39:06.038136 iDelay=203, Bit 1, Center 98 (15 ~ 182) 168
5956 23:39:06.044743 iDelay=203, Bit 2, Center 94 (11 ~ 178) 168
5957 23:39:06.047464 iDelay=203, Bit 3, Center 100 (19 ~ 182) 164
5958 23:39:06.050965 iDelay=203, Bit 4, Center 100 (19 ~ 182) 164
5959 23:39:06.054148 iDelay=203, Bit 5, Center 116 (31 ~ 202) 172
5960 23:39:06.058190 iDelay=203, Bit 6, Center 112 (27 ~ 198) 172
5961 23:39:06.064780 iDelay=203, Bit 7, Center 104 (19 ~ 190) 172
5962 23:39:06.068105 iDelay=203, Bit 8, Center 92 (11 ~ 174) 164
5963 23:39:06.071360 iDelay=203, Bit 9, Center 92 (7 ~ 178) 172
5964 23:39:06.074883 iDelay=203, Bit 10, Center 100 (15 ~ 186) 172
5965 23:39:06.077956 iDelay=203, Bit 11, Center 94 (11 ~ 178) 168
5966 23:39:06.084795 iDelay=203, Bit 12, Center 108 (19 ~ 198) 180
5967 23:39:06.087888 iDelay=203, Bit 13, Center 106 (23 ~ 190) 168
5968 23:39:06.090899 iDelay=203, Bit 14, Center 104 (19 ~ 190) 172
5969 23:39:06.094978 iDelay=203, Bit 15, Center 106 (19 ~ 194) 176
5970 23:39:06.095538 ==
5971 23:39:06.098033 Dram Type= 6, Freq= 0, CH_1, rank 1
5972 23:39:06.101230 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5973 23:39:06.104661 ==
5974 23:39:06.105121 DQS Delay:
5975 23:39:06.105488 DQS0 = 0, DQS1 = 0
5976 23:39:06.108066 DQM Delay:
5977 23:39:06.108642 DQM0 = 104, DQM1 = 100
5978 23:39:06.111294 DQ Delay:
5979 23:39:06.114857 DQ0 =110, DQ1 =98, DQ2 =94, DQ3 =100
5980 23:39:06.117835 DQ4 =100, DQ5 =116, DQ6 =112, DQ7 =104
5981 23:39:06.121333 DQ8 =92, DQ9 =92, DQ10 =100, DQ11 =94
5982 23:39:06.124826 DQ12 =108, DQ13 =106, DQ14 =104, DQ15 =106
5983 23:39:06.125386
5984 23:39:06.125867
5985 23:39:06.131080 [DQSOSCAuto] RK1, (LSB)MR18= 0x29fd, (MSB)MR19= 0x504, tDQSOscB0 = 423 ps tDQSOscB1 = 408 ps
5986 23:39:06.134063 CH1 RK1: MR19=504, MR18=29FD
5987 23:39:06.140792 CH1_RK1: MR19=0x504, MR18=0x29FD, DQSOSC=408, MR23=63, INC=65, DEC=43
5988 23:39:06.144880 [RxdqsGatingPostProcess] freq 933
5989 23:39:06.151106 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5990 23:39:06.151670 best DQS0 dly(2T, 0.5T) = (0, 10)
5991 23:39:06.154621 best DQS1 dly(2T, 0.5T) = (0, 10)
5992 23:39:06.158050 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5993 23:39:06.161284 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5994 23:39:06.164270 best DQS0 dly(2T, 0.5T) = (0, 10)
5995 23:39:06.167497 best DQS1 dly(2T, 0.5T) = (0, 10)
5996 23:39:06.170960 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5997 23:39:06.174270 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5998 23:39:06.177257 Pre-setting of DQS Precalculation
5999 23:39:06.184545 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6000 23:39:06.190355 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6001 23:39:06.197343 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6002 23:39:06.197960
6003 23:39:06.198426
6004 23:39:06.201156 [Calibration Summary] 1866 Mbps
6005 23:39:06.201668 CH 0, Rank 0
6006 23:39:06.203699 SW Impedance : PASS
6007 23:39:06.207180 DUTY Scan : NO K
6008 23:39:06.207739 ZQ Calibration : PASS
6009 23:39:06.210272 Jitter Meter : NO K
6010 23:39:06.213750 CBT Training : PASS
6011 23:39:06.214313 Write leveling : PASS
6012 23:39:06.217376 RX DQS gating : PASS
6013 23:39:06.218160 RX DQ/DQS(RDDQC) : PASS
6014 23:39:06.220960 TX DQ/DQS : PASS
6015 23:39:06.224036 RX DATLAT : PASS
6016 23:39:06.224500 RX DQ/DQS(Engine): PASS
6017 23:39:06.227536 TX OE : NO K
6018 23:39:06.228097 All Pass.
6019 23:39:06.228464
6020 23:39:06.230156 CH 0, Rank 1
6021 23:39:06.230613 SW Impedance : PASS
6022 23:39:06.233960 DUTY Scan : NO K
6023 23:39:06.237184 ZQ Calibration : PASS
6024 23:39:06.237757 Jitter Meter : NO K
6025 23:39:06.240324 CBT Training : PASS
6026 23:39:06.244042 Write leveling : PASS
6027 23:39:06.244569 RX DQS gating : PASS
6028 23:39:06.247733 RX DQ/DQS(RDDQC) : PASS
6029 23:39:06.251011 TX DQ/DQS : PASS
6030 23:39:06.251601 RX DATLAT : PASS
6031 23:39:06.253905 RX DQ/DQS(Engine): PASS
6032 23:39:06.257110 TX OE : NO K
6033 23:39:06.257728 All Pass.
6034 23:39:06.258128
6035 23:39:06.258470 CH 1, Rank 0
6036 23:39:06.260435 SW Impedance : PASS
6037 23:39:06.264298 DUTY Scan : NO K
6038 23:39:06.264857 ZQ Calibration : PASS
6039 23:39:06.266857 Jitter Meter : NO K
6040 23:39:06.267318 CBT Training : PASS
6041 23:39:06.270177 Write leveling : PASS
6042 23:39:06.273779 RX DQS gating : PASS
6043 23:39:06.274332 RX DQ/DQS(RDDQC) : PASS
6044 23:39:06.277065 TX DQ/DQS : PASS
6045 23:39:06.280024 RX DATLAT : PASS
6046 23:39:06.280486 RX DQ/DQS(Engine): PASS
6047 23:39:06.283782 TX OE : NO K
6048 23:39:06.284350 All Pass.
6049 23:39:06.284722
6050 23:39:06.286925 CH 1, Rank 1
6051 23:39:06.287382 SW Impedance : PASS
6052 23:39:06.290237 DUTY Scan : NO K
6053 23:39:06.293435 ZQ Calibration : PASS
6054 23:39:06.293946 Jitter Meter : NO K
6055 23:39:06.296912 CBT Training : PASS
6056 23:39:06.300062 Write leveling : PASS
6057 23:39:06.300520 RX DQS gating : PASS
6058 23:39:06.303425 RX DQ/DQS(RDDQC) : PASS
6059 23:39:06.307050 TX DQ/DQS : PASS
6060 23:39:06.307618 RX DATLAT : PASS
6061 23:39:06.310398 RX DQ/DQS(Engine): PASS
6062 23:39:06.313705 TX OE : NO K
6063 23:39:06.314267 All Pass.
6064 23:39:06.314680
6065 23:39:06.315062 DramC Write-DBI off
6066 23:39:06.316369 PER_BANK_REFRESH: Hybrid Mode
6067 23:39:06.320405 TX_TRACKING: ON
6068 23:39:06.326733 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6069 23:39:06.330434 [FAST_K] Save calibration result to emmc
6070 23:39:06.336551 dramc_set_vcore_voltage set vcore to 650000
6071 23:39:06.337114 Read voltage for 400, 6
6072 23:39:06.337716 Vio18 = 0
6073 23:39:06.340058 Vcore = 650000
6074 23:39:06.340614 Vdram = 0
6075 23:39:06.340982 Vddq = 0
6076 23:39:06.343254 Vmddr = 0
6077 23:39:06.346524 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6078 23:39:06.353218 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6079 23:39:06.353834 MEM_TYPE=3, freq_sel=20
6080 23:39:06.356820 sv_algorithm_assistance_LP4_800
6081 23:39:06.363880 ============ PULL DRAM RESETB DOWN ============
6082 23:39:06.366698 ========== PULL DRAM RESETB DOWN end =========
6083 23:39:06.370463 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6084 23:39:06.373565 ===================================
6085 23:39:06.377329 LPDDR4 DRAM CONFIGURATION
6086 23:39:06.379840 ===================================
6087 23:39:06.383388 EX_ROW_EN[0] = 0x0
6088 23:39:06.383890 EX_ROW_EN[1] = 0x0
6089 23:39:06.386777 LP4Y_EN = 0x0
6090 23:39:06.387235 WORK_FSP = 0x0
6091 23:39:06.390020 WL = 0x2
6092 23:39:06.390503 RL = 0x2
6093 23:39:06.393532 BL = 0x2
6094 23:39:06.394135 RPST = 0x0
6095 23:39:06.397330 RD_PRE = 0x0
6096 23:39:06.398016 WR_PRE = 0x1
6097 23:39:06.399959 WR_PST = 0x0
6098 23:39:06.400587 DBI_WR = 0x0
6099 23:39:06.403382 DBI_RD = 0x0
6100 23:39:06.403941 OTF = 0x1
6101 23:39:06.406226 ===================================
6102 23:39:06.410399 ===================================
6103 23:39:06.413417 ANA top config
6104 23:39:06.416641 ===================================
6105 23:39:06.420242 DLL_ASYNC_EN = 0
6106 23:39:06.420820 ALL_SLAVE_EN = 1
6107 23:39:06.423169 NEW_RANK_MODE = 1
6108 23:39:06.426292 DLL_IDLE_MODE = 1
6109 23:39:06.430007 LP45_APHY_COMB_EN = 1
6110 23:39:06.430572 TX_ODT_DIS = 1
6111 23:39:06.433104 NEW_8X_MODE = 1
6112 23:39:06.436225 ===================================
6113 23:39:06.439768 ===================================
6114 23:39:06.443273 data_rate = 800
6115 23:39:06.446596 CKR = 1
6116 23:39:06.449972 DQ_P2S_RATIO = 4
6117 23:39:06.453302 ===================================
6118 23:39:06.456809 CA_P2S_RATIO = 4
6119 23:39:06.457370 DQ_CA_OPEN = 0
6120 23:39:06.459731 DQ_SEMI_OPEN = 1
6121 23:39:06.463295 CA_SEMI_OPEN = 1
6122 23:39:06.466547 CA_FULL_RATE = 0
6123 23:39:06.469791 DQ_CKDIV4_EN = 0
6124 23:39:06.470401 CA_CKDIV4_EN = 1
6125 23:39:06.473409 CA_PREDIV_EN = 0
6126 23:39:06.476394 PH8_DLY = 0
6127 23:39:06.479944 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6128 23:39:06.482953 DQ_AAMCK_DIV = 0
6129 23:39:06.486305 CA_AAMCK_DIV = 0
6130 23:39:06.486785 CA_ADMCK_DIV = 4
6131 23:39:06.490375 DQ_TRACK_CA_EN = 0
6132 23:39:06.493188 CA_PICK = 800
6133 23:39:06.496048 CA_MCKIO = 400
6134 23:39:06.499705 MCKIO_SEMI = 400
6135 23:39:06.502798 PLL_FREQ = 3016
6136 23:39:06.506159 DQ_UI_PI_RATIO = 32
6137 23:39:06.509699 CA_UI_PI_RATIO = 32
6138 23:39:06.512647 ===================================
6139 23:39:06.515688 ===================================
6140 23:39:06.516156 memory_type:LPDDR4
6141 23:39:06.519901 GP_NUM : 10
6142 23:39:06.522747 SRAM_EN : 1
6143 23:39:06.523214 MD32_EN : 0
6144 23:39:06.526274 ===================================
6145 23:39:06.529193 [ANA_INIT] >>>>>>>>>>>>>>
6146 23:39:06.532423 <<<<<< [CONFIGURE PHASE]: ANA_TX
6147 23:39:06.535925 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6148 23:39:06.539287 ===================================
6149 23:39:06.542854 data_rate = 800,PCW = 0X7400
6150 23:39:06.545713 ===================================
6151 23:39:06.549128 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6152 23:39:06.552581 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6153 23:39:06.565807 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6154 23:39:06.569489 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6155 23:39:06.572418 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6156 23:39:06.575717 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6157 23:39:06.578952 [ANA_INIT] flow start
6158 23:39:06.579416 [ANA_INIT] PLL >>>>>>>>
6159 23:39:06.582195 [ANA_INIT] PLL <<<<<<<<
6160 23:39:06.586186 [ANA_INIT] MIDPI >>>>>>>>
6161 23:39:06.588798 [ANA_INIT] MIDPI <<<<<<<<
6162 23:39:06.589264 [ANA_INIT] DLL >>>>>>>>
6163 23:39:06.592485 [ANA_INIT] flow end
6164 23:39:06.595706 ============ LP4 DIFF to SE enter ============
6165 23:39:06.599072 ============ LP4 DIFF to SE exit ============
6166 23:39:06.602086 [ANA_INIT] <<<<<<<<<<<<<
6167 23:39:06.605449 [Flow] Enable top DCM control >>>>>
6168 23:39:06.608668 [Flow] Enable top DCM control <<<<<
6169 23:39:06.611795 Enable DLL master slave shuffle
6170 23:39:06.618778 ==============================================================
6171 23:39:06.619219 Gating Mode config
6172 23:39:06.625539 ==============================================================
6173 23:39:06.626014 Config description:
6174 23:39:06.635082 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6175 23:39:06.642061 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6176 23:39:06.649324 SELPH_MODE 0: By rank 1: By Phase
6177 23:39:06.652639 ==============================================================
6178 23:39:06.655536 GAT_TRACK_EN = 0
6179 23:39:06.659133 RX_GATING_MODE = 2
6180 23:39:06.662215 RX_GATING_TRACK_MODE = 2
6181 23:39:06.665723 SELPH_MODE = 1
6182 23:39:06.668567 PICG_EARLY_EN = 1
6183 23:39:06.671788 VALID_LAT_VALUE = 1
6184 23:39:06.675125 ==============================================================
6185 23:39:06.678741 Enter into Gating configuration >>>>
6186 23:39:06.681942 Exit from Gating configuration <<<<
6187 23:39:06.685690 Enter into DVFS_PRE_config >>>>>
6188 23:39:06.698541 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6189 23:39:06.701803 Exit from DVFS_PRE_config <<<<<
6190 23:39:06.705400 Enter into PICG configuration >>>>
6191 23:39:06.709062 Exit from PICG configuration <<<<
6192 23:39:06.709683 [RX_INPUT] configuration >>>>>
6193 23:39:06.711985 [RX_INPUT] configuration <<<<<
6194 23:39:06.718926 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6195 23:39:06.722230 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6196 23:39:06.728635 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6197 23:39:06.735315 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6198 23:39:06.741763 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6199 23:39:06.748413 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6200 23:39:06.751812 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6201 23:39:06.755231 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6202 23:39:06.758422 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6203 23:39:06.765001 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6204 23:39:06.768549 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6205 23:39:06.771747 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6206 23:39:06.774705 ===================================
6207 23:39:06.778380 LPDDR4 DRAM CONFIGURATION
6208 23:39:06.781574 ===================================
6209 23:39:06.785372 EX_ROW_EN[0] = 0x0
6210 23:39:06.785880 EX_ROW_EN[1] = 0x0
6211 23:39:06.788705 LP4Y_EN = 0x0
6212 23:39:06.789267 WORK_FSP = 0x0
6213 23:39:06.791405 WL = 0x2
6214 23:39:06.791873 RL = 0x2
6215 23:39:06.795505 BL = 0x2
6216 23:39:06.796088 RPST = 0x0
6217 23:39:06.797988 RD_PRE = 0x0
6218 23:39:06.798442 WR_PRE = 0x1
6219 23:39:06.802221 WR_PST = 0x0
6220 23:39:06.802772 DBI_WR = 0x0
6221 23:39:06.804802 DBI_RD = 0x0
6222 23:39:06.805405 OTF = 0x1
6223 23:39:06.808466 ===================================
6224 23:39:06.814999 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6225 23:39:06.818119 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6226 23:39:06.821889 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6227 23:39:06.825105 ===================================
6228 23:39:06.828312 LPDDR4 DRAM CONFIGURATION
6229 23:39:06.831475 ===================================
6230 23:39:06.835352 EX_ROW_EN[0] = 0x10
6231 23:39:06.835916 EX_ROW_EN[1] = 0x0
6232 23:39:06.838213 LP4Y_EN = 0x0
6233 23:39:06.838872 WORK_FSP = 0x0
6234 23:39:06.842201 WL = 0x2
6235 23:39:06.842765 RL = 0x2
6236 23:39:06.844749 BL = 0x2
6237 23:39:06.845205 RPST = 0x0
6238 23:39:06.848108 RD_PRE = 0x0
6239 23:39:06.848687 WR_PRE = 0x1
6240 23:39:06.851402 WR_PST = 0x0
6241 23:39:06.851982 DBI_WR = 0x0
6242 23:39:06.854835 DBI_RD = 0x0
6243 23:39:06.855425 OTF = 0x1
6244 23:39:06.858112 ===================================
6245 23:39:06.864737 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6246 23:39:06.869016 nWR fixed to 30
6247 23:39:06.872223 [ModeRegInit_LP4] CH0 RK0
6248 23:39:06.872693 [ModeRegInit_LP4] CH0 RK1
6249 23:39:06.876014 [ModeRegInit_LP4] CH1 RK0
6250 23:39:06.879407 [ModeRegInit_LP4] CH1 RK1
6251 23:39:06.879979 match AC timing 19
6252 23:39:06.885725 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6253 23:39:06.889192 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6254 23:39:06.892450 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6255 23:39:06.899501 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6256 23:39:06.902348 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6257 23:39:06.902808 ==
6258 23:39:06.906001 Dram Type= 6, Freq= 0, CH_0, rank 0
6259 23:39:06.909196 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6260 23:39:06.909967 ==
6261 23:39:06.915788 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6262 23:39:06.922533 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6263 23:39:06.926059 [CA 0] Center 36 (8~64) winsize 57
6264 23:39:06.929497 [CA 1] Center 36 (8~64) winsize 57
6265 23:39:06.932822 [CA 2] Center 36 (8~64) winsize 57
6266 23:39:06.933384 [CA 3] Center 36 (8~64) winsize 57
6267 23:39:06.936199 [CA 4] Center 36 (8~64) winsize 57
6268 23:39:06.939143 [CA 5] Center 36 (8~64) winsize 57
6269 23:39:06.939602
6270 23:39:06.945760 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6271 23:39:06.946321
6272 23:39:06.948975 [CATrainingPosCal] consider 1 rank data
6273 23:39:06.952250 u2DelayCellTimex100 = 270/100 ps
6274 23:39:06.955839 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6275 23:39:06.959118 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6276 23:39:06.962332 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6277 23:39:06.965729 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6278 23:39:06.968996 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6279 23:39:06.972304 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6280 23:39:06.972865
6281 23:39:06.975557 CA PerBit enable=1, Macro0, CA PI delay=36
6282 23:39:06.976015
6283 23:39:06.978850 [CBTSetCACLKResult] CA Dly = 36
6284 23:39:06.982159 CS Dly: 1 (0~32)
6285 23:39:06.982686 ==
6286 23:39:06.985235 Dram Type= 6, Freq= 0, CH_0, rank 1
6287 23:39:06.988734 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6288 23:39:06.989215 ==
6289 23:39:06.995451 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6290 23:39:07.002029 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6291 23:39:07.002598 [CA 0] Center 36 (8~64) winsize 57
6292 23:39:07.005085 [CA 1] Center 36 (8~64) winsize 57
6293 23:39:07.008768 [CA 2] Center 36 (8~64) winsize 57
6294 23:39:07.011613 [CA 3] Center 36 (8~64) winsize 57
6295 23:39:07.014769 [CA 4] Center 36 (8~64) winsize 57
6296 23:39:07.018376 [CA 5] Center 36 (8~64) winsize 57
6297 23:39:07.018965
6298 23:39:07.021393 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6299 23:39:07.021954
6300 23:39:07.024752 [CATrainingPosCal] consider 2 rank data
6301 23:39:07.028221 u2DelayCellTimex100 = 270/100 ps
6302 23:39:07.031662 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6303 23:39:07.034800 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6304 23:39:07.041652 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6305 23:39:07.045246 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6306 23:39:07.048600 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6307 23:39:07.052018 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6308 23:39:07.052582
6309 23:39:07.055463 CA PerBit enable=1, Macro0, CA PI delay=36
6310 23:39:07.056029
6311 23:39:07.058261 [CBTSetCACLKResult] CA Dly = 36
6312 23:39:07.058830 CS Dly: 1 (0~32)
6313 23:39:07.059195
6314 23:39:07.064705 ----->DramcWriteLeveling(PI) begin...
6315 23:39:07.065272 ==
6316 23:39:07.067876 Dram Type= 6, Freq= 0, CH_0, rank 0
6317 23:39:07.071769 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6318 23:39:07.072232 ==
6319 23:39:07.074722 Write leveling (Byte 0): 40 => 8
6320 23:39:07.078195 Write leveling (Byte 1): 40 => 8
6321 23:39:07.082244 DramcWriteLeveling(PI) end<-----
6322 23:39:07.082898
6323 23:39:07.083277 ==
6324 23:39:07.084684 Dram Type= 6, Freq= 0, CH_0, rank 0
6325 23:39:07.088280 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6326 23:39:07.088847 ==
6327 23:39:07.091743 [Gating] SW mode calibration
6328 23:39:07.098208 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6329 23:39:07.101765 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6330 23:39:07.108810 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6331 23:39:07.111583 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6332 23:39:07.114568 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6333 23:39:07.121434 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6334 23:39:07.124688 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6335 23:39:07.128424 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6336 23:39:07.134809 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6337 23:39:07.138117 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6338 23:39:07.141187 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6339 23:39:07.144646 Total UI for P1: 0, mck2ui 16
6340 23:39:07.147979 best dqsien dly found for B0: ( 0, 14, 24)
6341 23:39:07.151077 Total UI for P1: 0, mck2ui 16
6342 23:39:07.154342 best dqsien dly found for B1: ( 0, 14, 24)
6343 23:39:07.157860 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6344 23:39:07.164560 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6345 23:39:07.165155
6346 23:39:07.167970 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6347 23:39:07.171243 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6348 23:39:07.174334 [Gating] SW calibration Done
6349 23:39:07.174956 ==
6350 23:39:07.178353 Dram Type= 6, Freq= 0, CH_0, rank 0
6351 23:39:07.181412 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6352 23:39:07.182035 ==
6353 23:39:07.182417 RX Vref Scan: 0
6354 23:39:07.184252
6355 23:39:07.184717 RX Vref 0 -> 0, step: 1
6356 23:39:07.185085
6357 23:39:07.188019 RX Delay -410 -> 252, step: 16
6358 23:39:07.190881 iDelay=230, Bit 0, Center -11 (-234 ~ 213) 448
6359 23:39:07.197480 iDelay=230, Bit 1, Center -3 (-234 ~ 229) 464
6360 23:39:07.200745 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6361 23:39:07.204133 iDelay=230, Bit 3, Center -27 (-266 ~ 213) 480
6362 23:39:07.207671 iDelay=230, Bit 4, Center -11 (-234 ~ 213) 448
6363 23:39:07.213873 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6364 23:39:07.217518 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6365 23:39:07.221334 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6366 23:39:07.224213 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6367 23:39:07.230648 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6368 23:39:07.234616 iDelay=230, Bit 10, Center -11 (-234 ~ 213) 448
6369 23:39:07.237942 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6370 23:39:07.240845 iDelay=230, Bit 12, Center -11 (-234 ~ 213) 448
6371 23:39:07.248184 iDelay=230, Bit 13, Center -11 (-234 ~ 213) 448
6372 23:39:07.250424 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6373 23:39:07.253610 iDelay=230, Bit 15, Center -11 (-234 ~ 213) 448
6374 23:39:07.254077 ==
6375 23:39:07.257233 Dram Type= 6, Freq= 0, CH_0, rank 0
6376 23:39:07.263790 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6377 23:39:07.264403 ==
6378 23:39:07.264955 DQS Delay:
6379 23:39:07.267277 DQS0 = 27, DQS1 = 35
6380 23:39:07.267831 DQM Delay:
6381 23:39:07.268193 DQM0 = 13, DQM1 = 16
6382 23:39:07.270238 DQ Delay:
6383 23:39:07.273759 DQ0 =16, DQ1 =24, DQ2 =0, DQ3 =0
6384 23:39:07.274334 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6385 23:39:07.277091 DQ8 =0, DQ9 =0, DQ10 =24, DQ11 =8
6386 23:39:07.280732 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6387 23:39:07.281430
6388 23:39:07.284025
6389 23:39:07.284522 ==
6390 23:39:07.286746 Dram Type= 6, Freq= 0, CH_0, rank 0
6391 23:39:07.290205 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6392 23:39:07.290712 ==
6393 23:39:07.291079
6394 23:39:07.291415
6395 23:39:07.293380 TX Vref Scan disable
6396 23:39:07.293897 == TX Byte 0 ==
6397 23:39:07.297027 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6398 23:39:07.304119 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6399 23:39:07.304706 == TX Byte 1 ==
6400 23:39:07.306844 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6401 23:39:07.313798 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6402 23:39:07.314351 ==
6403 23:39:07.316894 Dram Type= 6, Freq= 0, CH_0, rank 0
6404 23:39:07.320639 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6405 23:39:07.321199 ==
6406 23:39:07.321565
6407 23:39:07.321965
6408 23:39:07.323444 TX Vref Scan disable
6409 23:39:07.323895 == TX Byte 0 ==
6410 23:39:07.326500 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6411 23:39:07.333531 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6412 23:39:07.334173 == TX Byte 1 ==
6413 23:39:07.336894 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6414 23:39:07.343467 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6415 23:39:07.344025
6416 23:39:07.344386 [DATLAT]
6417 23:39:07.347152 Freq=400, CH0 RK0
6418 23:39:07.347716
6419 23:39:07.348082 DATLAT Default: 0xf
6420 23:39:07.349722 0, 0xFFFF, sum = 0
6421 23:39:07.350188 1, 0xFFFF, sum = 0
6422 23:39:07.353185 2, 0xFFFF, sum = 0
6423 23:39:07.353699 3, 0xFFFF, sum = 0
6424 23:39:07.356873 4, 0xFFFF, sum = 0
6425 23:39:07.357442 5, 0xFFFF, sum = 0
6426 23:39:07.360465 6, 0xFFFF, sum = 0
6427 23:39:07.361060 7, 0xFFFF, sum = 0
6428 23:39:07.363780 8, 0xFFFF, sum = 0
6429 23:39:07.364391 9, 0xFFFF, sum = 0
6430 23:39:07.366824 10, 0xFFFF, sum = 0
6431 23:39:07.367448 11, 0xFFFF, sum = 0
6432 23:39:07.370197 12, 0xFFFF, sum = 0
6433 23:39:07.370763 13, 0x0, sum = 1
6434 23:39:07.373037 14, 0x0, sum = 2
6435 23:39:07.373502 15, 0x0, sum = 3
6436 23:39:07.376447 16, 0x0, sum = 4
6437 23:39:07.376963 best_step = 14
6438 23:39:07.377340
6439 23:39:07.377740 ==
6440 23:39:07.379819 Dram Type= 6, Freq= 0, CH_0, rank 0
6441 23:39:07.386118 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6442 23:39:07.386583 ==
6443 23:39:07.386952 RX Vref Scan: 1
6444 23:39:07.387325
6445 23:39:07.389676 RX Vref 0 -> 0, step: 1
6446 23:39:07.390142
6447 23:39:07.392722 RX Delay -311 -> 252, step: 8
6448 23:39:07.393181
6449 23:39:07.396321 Set Vref, RX VrefLevel [Byte0]: 54
6450 23:39:07.399336 [Byte1]: 55
6451 23:39:07.399819
6452 23:39:07.402795 Final RX Vref Byte 0 = 54 to rank0
6453 23:39:07.406230 Final RX Vref Byte 1 = 55 to rank0
6454 23:39:07.409566 Final RX Vref Byte 0 = 54 to rank1
6455 23:39:07.413019 Final RX Vref Byte 1 = 55 to rank1==
6456 23:39:07.416576 Dram Type= 6, Freq= 0, CH_0, rank 0
6457 23:39:07.419591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6458 23:39:07.422895 ==
6459 23:39:07.423472 DQS Delay:
6460 23:39:07.423845 DQS0 = 28, DQS1 = 36
6461 23:39:07.426881 DQM Delay:
6462 23:39:07.427456 DQM0 = 10, DQM1 = 13
6463 23:39:07.429857 DQ Delay:
6464 23:39:07.430427 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6465 23:39:07.433020 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =16
6466 23:39:07.435947 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =4
6467 23:39:07.439541 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
6468 23:39:07.440005
6469 23:39:07.440369
6470 23:39:07.449388 [DQSOSCAuto] RK0, (LSB)MR18= 0xc9b5, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 384 ps
6471 23:39:07.452675 CH0 RK0: MR19=C0C, MR18=C9B5
6472 23:39:07.459334 CH0_RK0: MR19=0xC0C, MR18=0xC9B5, DQSOSC=384, MR23=63, INC=400, DEC=267
6473 23:39:07.459910 ==
6474 23:39:07.462471 Dram Type= 6, Freq= 0, CH_0, rank 1
6475 23:39:07.466251 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6476 23:39:07.466827 ==
6477 23:39:07.469162 [Gating] SW mode calibration
6478 23:39:07.476330 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6479 23:39:07.479747 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6480 23:39:07.485686 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6481 23:39:07.489020 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6482 23:39:07.492359 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6483 23:39:07.499014 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6484 23:39:07.502184 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6485 23:39:07.505716 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6486 23:39:07.512628 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6487 23:39:07.516188 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6488 23:39:07.518842 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6489 23:39:07.522652 Total UI for P1: 0, mck2ui 16
6490 23:39:07.525736 best dqsien dly found for B0: ( 0, 14, 24)
6491 23:39:07.529954 Total UI for P1: 0, mck2ui 16
6492 23:39:07.532633 best dqsien dly found for B1: ( 0, 14, 24)
6493 23:39:07.535668 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6494 23:39:07.539115 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6495 23:39:07.539589
6496 23:39:07.546191 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6497 23:39:07.549224 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6498 23:39:07.552041 [Gating] SW calibration Done
6499 23:39:07.552600 ==
6500 23:39:07.555734 Dram Type= 6, Freq= 0, CH_0, rank 1
6501 23:39:07.558585 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6502 23:39:07.559151 ==
6503 23:39:07.559517 RX Vref Scan: 0
6504 23:39:07.559853
6505 23:39:07.561995 RX Vref 0 -> 0, step: 1
6506 23:39:07.562556
6507 23:39:07.566077 RX Delay -410 -> 252, step: 16
6508 23:39:07.569031 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6509 23:39:07.575871 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6510 23:39:07.578496 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6511 23:39:07.582187 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6512 23:39:07.584986 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6513 23:39:07.591845 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6514 23:39:07.595368 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6515 23:39:07.598399 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6516 23:39:07.601952 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6517 23:39:07.608408 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6518 23:39:07.611799 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6519 23:39:07.615548 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6520 23:39:07.618546 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6521 23:39:07.625380 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6522 23:39:07.628620 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6523 23:39:07.631659 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6524 23:39:07.632236 ==
6525 23:39:07.634797 Dram Type= 6, Freq= 0, CH_0, rank 1
6526 23:39:07.638563 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6527 23:39:07.641337 ==
6528 23:39:07.641859 DQS Delay:
6529 23:39:07.642227 DQS0 = 27, DQS1 = 35
6530 23:39:07.644732 DQM Delay:
6531 23:39:07.645189 DQM0 = 12, DQM1 = 10
6532 23:39:07.648220 DQ Delay:
6533 23:39:07.648680 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6534 23:39:07.651102 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6535 23:39:07.654720 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6536 23:39:07.658111 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6537 23:39:07.658525
6538 23:39:07.658851
6539 23:39:07.661230 ==
6540 23:39:07.661714 Dram Type= 6, Freq= 0, CH_0, rank 1
6541 23:39:07.667973 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6542 23:39:07.668390 ==
6543 23:39:07.668722
6544 23:39:07.669026
6545 23:39:07.671579 TX Vref Scan disable
6546 23:39:07.671993 == TX Byte 0 ==
6547 23:39:07.674845 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6548 23:39:07.681416 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6549 23:39:07.682001 == TX Byte 1 ==
6550 23:39:07.684331 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6551 23:39:07.688298 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6552 23:39:07.691024 ==
6553 23:39:07.695216 Dram Type= 6, Freq= 0, CH_0, rank 1
6554 23:39:07.698169 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6555 23:39:07.698602 ==
6556 23:39:07.698941
6557 23:39:07.699253
6558 23:39:07.701487 TX Vref Scan disable
6559 23:39:07.702070 == TX Byte 0 ==
6560 23:39:07.704927 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6561 23:39:07.711426 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6562 23:39:07.711974 == TX Byte 1 ==
6563 23:39:07.714625 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6564 23:39:07.718125 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6565 23:39:07.721567
6566 23:39:07.722170 [DATLAT]
6567 23:39:07.722516 Freq=400, CH0 RK1
6568 23:39:07.722832
6569 23:39:07.724580 DATLAT Default: 0xe
6570 23:39:07.724999 0, 0xFFFF, sum = 0
6571 23:39:07.727733 1, 0xFFFF, sum = 0
6572 23:39:07.728161 2, 0xFFFF, sum = 0
6573 23:39:07.731605 3, 0xFFFF, sum = 0
6574 23:39:07.732142 4, 0xFFFF, sum = 0
6575 23:39:07.734603 5, 0xFFFF, sum = 0
6576 23:39:07.738215 6, 0xFFFF, sum = 0
6577 23:39:07.738753 7, 0xFFFF, sum = 0
6578 23:39:07.741153 8, 0xFFFF, sum = 0
6579 23:39:07.741710 9, 0xFFFF, sum = 0
6580 23:39:07.744079 10, 0xFFFF, sum = 0
6581 23:39:07.744504 11, 0xFFFF, sum = 0
6582 23:39:07.747463 12, 0xFFFF, sum = 0
6583 23:39:07.747892 13, 0x0, sum = 1
6584 23:39:07.751143 14, 0x0, sum = 2
6585 23:39:07.751684 15, 0x0, sum = 3
6586 23:39:07.754259 16, 0x0, sum = 4
6587 23:39:07.754687 best_step = 14
6588 23:39:07.755021
6589 23:39:07.755332 ==
6590 23:39:07.758172 Dram Type= 6, Freq= 0, CH_0, rank 1
6591 23:39:07.761113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6592 23:39:07.764340 ==
6593 23:39:07.764873 RX Vref Scan: 0
6594 23:39:07.765211
6595 23:39:07.767754 RX Vref 0 -> 0, step: 1
6596 23:39:07.768290
6597 23:39:07.771020 RX Delay -311 -> 252, step: 8
6598 23:39:07.773973 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6599 23:39:07.780956 iDelay=217, Bit 1, Center -12 (-231 ~ 208) 440
6600 23:39:07.783761 iDelay=217, Bit 2, Center -16 (-239 ~ 208) 448
6601 23:39:07.787305 iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448
6602 23:39:07.790493 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6603 23:39:07.797280 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6604 23:39:07.801013 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6605 23:39:07.804203 iDelay=217, Bit 7, Center -4 (-223 ~ 216) 440
6606 23:39:07.807416 iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448
6607 23:39:07.814410 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6608 23:39:07.817609 iDelay=217, Bit 10, Center -20 (-239 ~ 200) 440
6609 23:39:07.821495 iDelay=217, Bit 11, Center -32 (-255 ~ 192) 448
6610 23:39:07.824289 iDelay=217, Bit 12, Center -20 (-239 ~ 200) 440
6611 23:39:07.830580 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
6612 23:39:07.833678 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6613 23:39:07.837811 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6614 23:39:07.838398 ==
6615 23:39:07.840899 Dram Type= 6, Freq= 0, CH_0, rank 1
6616 23:39:07.847297 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6617 23:39:07.847850 ==
6618 23:39:07.848228 DQS Delay:
6619 23:39:07.850546 DQS0 = 24, DQS1 = 32
6620 23:39:07.851109 DQM Delay:
6621 23:39:07.851482 DQM0 = 9, DQM1 = 9
6622 23:39:07.853838 DQ Delay:
6623 23:39:07.857387 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =8
6624 23:39:07.858008 DQ4 =8, DQ5 =0, DQ6 =12, DQ7 =20
6625 23:39:07.860518 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =0
6626 23:39:07.864395 DQ12 =12, DQ13 =16, DQ14 =16, DQ15 =16
6627 23:39:07.864961
6628 23:39:07.865332
6629 23:39:07.874258 [DQSOSCAuto] RK1, (LSB)MR18= 0xb354, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 387 ps
6630 23:39:07.877184 CH0 RK1: MR19=C0C, MR18=B354
6631 23:39:07.883637 CH0_RK1: MR19=0xC0C, MR18=0xB354, DQSOSC=387, MR23=63, INC=394, DEC=262
6632 23:39:07.884199 [RxdqsGatingPostProcess] freq 400
6633 23:39:07.890627 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6634 23:39:07.893706 best DQS0 dly(2T, 0.5T) = (0, 10)
6635 23:39:07.897314 best DQS1 dly(2T, 0.5T) = (0, 10)
6636 23:39:07.900198 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6637 23:39:07.903477 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6638 23:39:07.906719 best DQS0 dly(2T, 0.5T) = (0, 10)
6639 23:39:07.909971 best DQS1 dly(2T, 0.5T) = (0, 10)
6640 23:39:07.913655 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6641 23:39:07.916884 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6642 23:39:07.920661 Pre-setting of DQS Precalculation
6643 23:39:07.923762 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6644 23:39:07.924301 ==
6645 23:39:07.926632 Dram Type= 6, Freq= 0, CH_1, rank 0
6646 23:39:07.930092 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6647 23:39:07.933505 ==
6648 23:39:07.936891 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6649 23:39:07.943609 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6650 23:39:07.946462 [CA 0] Center 36 (8~64) winsize 57
6651 23:39:07.949960 [CA 1] Center 36 (8~64) winsize 57
6652 23:39:07.954167 [CA 2] Center 36 (8~64) winsize 57
6653 23:39:07.956914 [CA 3] Center 36 (8~64) winsize 57
6654 23:39:07.960273 [CA 4] Center 36 (8~64) winsize 57
6655 23:39:07.963905 [CA 5] Center 36 (8~64) winsize 57
6656 23:39:07.964503
6657 23:39:07.966606 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6658 23:39:07.967071
6659 23:39:07.970096 [CATrainingPosCal] consider 1 rank data
6660 23:39:07.973356 u2DelayCellTimex100 = 270/100 ps
6661 23:39:07.977240 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6662 23:39:07.980157 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6663 23:39:07.983847 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6664 23:39:07.986749 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6665 23:39:07.989947 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6666 23:39:07.993117 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6667 23:39:07.993721
6668 23:39:07.999742 CA PerBit enable=1, Macro0, CA PI delay=36
6669 23:39:08.000338
6670 23:39:08.000718 [CBTSetCACLKResult] CA Dly = 36
6671 23:39:08.003029 CS Dly: 1 (0~32)
6672 23:39:08.003495 ==
6673 23:39:08.006262 Dram Type= 6, Freq= 0, CH_1, rank 1
6674 23:39:08.009530 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6675 23:39:08.010049 ==
6676 23:39:08.016425 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6677 23:39:08.022897 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6678 23:39:08.026359 [CA 0] Center 36 (8~64) winsize 57
6679 23:39:08.029683 [CA 1] Center 36 (8~64) winsize 57
6680 23:39:08.032697 [CA 2] Center 36 (8~64) winsize 57
6681 23:39:08.033166 [CA 3] Center 36 (8~64) winsize 57
6682 23:39:08.036096 [CA 4] Center 36 (8~64) winsize 57
6683 23:39:08.039473 [CA 5] Center 36 (8~64) winsize 57
6684 23:39:08.040045
6685 23:39:08.046083 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6686 23:39:08.046550
6687 23:39:08.049508 [CATrainingPosCal] consider 2 rank data
6688 23:39:08.053131 u2DelayCellTimex100 = 270/100 ps
6689 23:39:08.056565 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6690 23:39:08.059122 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6691 23:39:08.062582 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6692 23:39:08.066328 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6693 23:39:08.069688 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6694 23:39:08.072594 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6695 23:39:08.073062
6696 23:39:08.075852 CA PerBit enable=1, Macro0, CA PI delay=36
6697 23:39:08.076320
6698 23:39:08.079773 [CBTSetCACLKResult] CA Dly = 36
6699 23:39:08.082616 CS Dly: 1 (0~32)
6700 23:39:08.083083
6701 23:39:08.086218 ----->DramcWriteLeveling(PI) begin...
6702 23:39:08.086688 ==
6703 23:39:08.089775 Dram Type= 6, Freq= 0, CH_1, rank 0
6704 23:39:08.093214 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6705 23:39:08.093792 ==
6706 23:39:08.096327 Write leveling (Byte 0): 40 => 8
6707 23:39:08.099545 Write leveling (Byte 1): 40 => 8
6708 23:39:08.102560 DramcWriteLeveling(PI) end<-----
6709 23:39:08.102982
6710 23:39:08.103318 ==
6711 23:39:08.105897 Dram Type= 6, Freq= 0, CH_1, rank 0
6712 23:39:08.109049 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6713 23:39:08.109477 ==
6714 23:39:08.112864 [Gating] SW mode calibration
6715 23:39:08.119790 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6716 23:39:08.126136 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6717 23:39:08.129401 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6718 23:39:08.133108 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6719 23:39:08.139359 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6720 23:39:08.142692 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6721 23:39:08.145872 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6722 23:39:08.152917 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6723 23:39:08.155865 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6724 23:39:08.159431 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6725 23:39:08.165770 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6726 23:39:08.166344 Total UI for P1: 0, mck2ui 16
6727 23:39:08.172699 best dqsien dly found for B0: ( 0, 14, 24)
6728 23:39:08.173259 Total UI for P1: 0, mck2ui 16
6729 23:39:08.175693 best dqsien dly found for B1: ( 0, 14, 24)
6730 23:39:08.182220 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6731 23:39:08.185488 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6732 23:39:08.186023
6733 23:39:08.188884 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6734 23:39:08.192112 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6735 23:39:08.195359 [Gating] SW calibration Done
6736 23:39:08.195931 ==
6737 23:39:08.199296 Dram Type= 6, Freq= 0, CH_1, rank 0
6738 23:39:08.202320 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6739 23:39:08.202786 ==
6740 23:39:08.205495 RX Vref Scan: 0
6741 23:39:08.205995
6742 23:39:08.206343 RX Vref 0 -> 0, step: 1
6743 23:39:08.206708
6744 23:39:08.209078 RX Delay -410 -> 252, step: 16
6745 23:39:08.215424 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6746 23:39:08.219122 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6747 23:39:08.222324 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6748 23:39:08.225549 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6749 23:39:08.232568 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6750 23:39:08.235616 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6751 23:39:08.239127 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6752 23:39:08.242573 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6753 23:39:08.248841 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6754 23:39:08.252047 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6755 23:39:08.255736 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6756 23:39:08.258938 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6757 23:39:08.265357 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6758 23:39:08.268902 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6759 23:39:08.272051 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6760 23:39:08.275150 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6761 23:39:08.278541 ==
6762 23:39:08.279000 Dram Type= 6, Freq= 0, CH_1, rank 0
6763 23:39:08.285288 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6764 23:39:08.285903 ==
6765 23:39:08.286276 DQS Delay:
6766 23:39:08.288967 DQS0 = 35, DQS1 = 35
6767 23:39:08.289523 DQM Delay:
6768 23:39:08.291585 DQM0 = 17, DQM1 = 13
6769 23:39:08.292160 DQ Delay:
6770 23:39:08.294919 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =16
6771 23:39:08.298674 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6772 23:39:08.302140 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6773 23:39:08.304895 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6774 23:39:08.305468
6775 23:39:08.305904
6776 23:39:08.306251 ==
6777 23:39:08.308396 Dram Type= 6, Freq= 0, CH_1, rank 0
6778 23:39:08.311589 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6779 23:39:08.312059 ==
6780 23:39:08.312428
6781 23:39:08.312768
6782 23:39:08.315293 TX Vref Scan disable
6783 23:39:08.315863 == TX Byte 0 ==
6784 23:39:08.321482 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6785 23:39:08.325606 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6786 23:39:08.326194 == TX Byte 1 ==
6787 23:39:08.331858 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6788 23:39:08.335316 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6789 23:39:08.335889 ==
6790 23:39:08.338227 Dram Type= 6, Freq= 0, CH_1, rank 0
6791 23:39:08.342088 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6792 23:39:08.342673 ==
6793 23:39:08.343170
6794 23:39:08.343529
6795 23:39:08.345070 TX Vref Scan disable
6796 23:39:08.345545 == TX Byte 0 ==
6797 23:39:08.351607 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6798 23:39:08.355422 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6799 23:39:08.355997 == TX Byte 1 ==
6800 23:39:08.361713 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6801 23:39:08.364916 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6802 23:39:08.365492
6803 23:39:08.365905 [DATLAT]
6804 23:39:08.368171 Freq=400, CH1 RK0
6805 23:39:08.368740
6806 23:39:08.369108 DATLAT Default: 0xf
6807 23:39:08.371308 0, 0xFFFF, sum = 0
6808 23:39:08.371786 1, 0xFFFF, sum = 0
6809 23:39:08.374673 2, 0xFFFF, sum = 0
6810 23:39:08.375265 3, 0xFFFF, sum = 0
6811 23:39:08.378077 4, 0xFFFF, sum = 0
6812 23:39:08.378705 5, 0xFFFF, sum = 0
6813 23:39:08.381384 6, 0xFFFF, sum = 0
6814 23:39:08.381908 7, 0xFFFF, sum = 0
6815 23:39:08.384877 8, 0xFFFF, sum = 0
6816 23:39:08.385526 9, 0xFFFF, sum = 0
6817 23:39:08.388663 10, 0xFFFF, sum = 0
6818 23:39:08.391693 11, 0xFFFF, sum = 0
6819 23:39:08.392167 12, 0xFFFF, sum = 0
6820 23:39:08.395013 13, 0x0, sum = 1
6821 23:39:08.395597 14, 0x0, sum = 2
6822 23:39:08.395978 15, 0x0, sum = 3
6823 23:39:08.398191 16, 0x0, sum = 4
6824 23:39:08.398662 best_step = 14
6825 23:39:08.399033
6826 23:39:08.401540 ==
6827 23:39:08.402173 Dram Type= 6, Freq= 0, CH_1, rank 0
6828 23:39:08.408122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6829 23:39:08.408694 ==
6830 23:39:08.409068 RX Vref Scan: 1
6831 23:39:08.409412
6832 23:39:08.410958 RX Vref 0 -> 0, step: 1
6833 23:39:08.411423
6834 23:39:08.414905 RX Delay -311 -> 252, step: 8
6835 23:39:08.415614
6836 23:39:08.417726 Set Vref, RX VrefLevel [Byte0]: 55
6837 23:39:08.421185 [Byte1]: 53
6838 23:39:08.424858
6839 23:39:08.425422 Final RX Vref Byte 0 = 55 to rank0
6840 23:39:08.427612 Final RX Vref Byte 1 = 53 to rank0
6841 23:39:08.431673 Final RX Vref Byte 0 = 55 to rank1
6842 23:39:08.434546 Final RX Vref Byte 1 = 53 to rank1==
6843 23:39:08.437792 Dram Type= 6, Freq= 0, CH_1, rank 0
6844 23:39:08.444617 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6845 23:39:08.445094 ==
6846 23:39:08.445468 DQS Delay:
6847 23:39:08.448256 DQS0 = 24, DQS1 = 32
6848 23:39:08.448824 DQM Delay:
6849 23:39:08.449197 DQM0 = 6, DQM1 = 10
6850 23:39:08.450901 DQ Delay:
6851 23:39:08.451369 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =4
6852 23:39:08.454752 DQ4 =4, DQ5 =16, DQ6 =12, DQ7 =4
6853 23:39:08.458173 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6854 23:39:08.461521 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =24
6855 23:39:08.462092
6856 23:39:08.462431
6857 23:39:08.471065 [DQSOSCAuto] RK0, (LSB)MR18= 0x8ec6, (MSB)MR19= 0xc0c, tDQSOscB0 = 385 ps tDQSOscB1 = 392 ps
6858 23:39:08.474282 CH1 RK0: MR19=C0C, MR18=8EC6
6859 23:39:08.481076 CH1_RK0: MR19=0xC0C, MR18=0x8EC6, DQSOSC=385, MR23=63, INC=398, DEC=265
6860 23:39:08.481651 ==
6861 23:39:08.484164 Dram Type= 6, Freq= 0, CH_1, rank 1
6862 23:39:08.488048 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6863 23:39:08.488582 ==
6864 23:39:08.490824 [Gating] SW mode calibration
6865 23:39:08.497546 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6866 23:39:08.501024 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6867 23:39:08.507578 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6868 23:39:08.511114 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6869 23:39:08.514400 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6870 23:39:08.521573 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6871 23:39:08.524221 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6872 23:39:08.527795 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6873 23:39:08.534454 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6874 23:39:08.538142 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6875 23:39:08.541385 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6876 23:39:08.543998 Total UI for P1: 0, mck2ui 16
6877 23:39:08.548003 best dqsien dly found for B0: ( 0, 14, 24)
6878 23:39:08.550598 Total UI for P1: 0, mck2ui 16
6879 23:39:08.554288 best dqsien dly found for B1: ( 0, 14, 24)
6880 23:39:08.557642 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6881 23:39:08.560578 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6882 23:39:08.561046
6883 23:39:08.567679 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6884 23:39:08.570507 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6885 23:39:08.570972 [Gating] SW calibration Done
6886 23:39:08.574199 ==
6887 23:39:08.577642 Dram Type= 6, Freq= 0, CH_1, rank 1
6888 23:39:08.580859 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6889 23:39:08.581361 ==
6890 23:39:08.581787 RX Vref Scan: 0
6891 23:39:08.582137
6892 23:39:08.583783 RX Vref 0 -> 0, step: 1
6893 23:39:08.584198
6894 23:39:08.587187 RX Delay -410 -> 252, step: 16
6895 23:39:08.590571 iDelay=230, Bit 0, Center -11 (-234 ~ 213) 448
6896 23:39:08.593796 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6897 23:39:08.600791 iDelay=230, Bit 2, Center -27 (-250 ~ 197) 448
6898 23:39:08.603747 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6899 23:39:08.607168 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6900 23:39:08.610360 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6901 23:39:08.617301 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6902 23:39:08.620590 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6903 23:39:08.623761 iDelay=230, Bit 8, Center -27 (-250 ~ 197) 448
6904 23:39:08.626960 iDelay=230, Bit 9, Center -19 (-250 ~ 213) 464
6905 23:39:08.633970 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6906 23:39:08.637317 iDelay=230, Bit 11, Center -19 (-250 ~ 213) 464
6907 23:39:08.640335 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6908 23:39:08.646592 iDelay=230, Bit 13, Center -11 (-250 ~ 229) 480
6909 23:39:08.650517 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6910 23:39:08.653641 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6911 23:39:08.654113 ==
6912 23:39:08.656810 Dram Type= 6, Freq= 0, CH_1, rank 1
6913 23:39:08.660067 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6914 23:39:08.663182 ==
6915 23:39:08.663604 DQS Delay:
6916 23:39:08.663942 DQS0 = 27, DQS1 = 27
6917 23:39:08.666108 DQM Delay:
6918 23:39:08.666530 DQM0 = 12, DQM1 = 10
6919 23:39:08.669349 DQ Delay:
6920 23:39:08.673083 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6921 23:39:08.673522 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6922 23:39:08.676289 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =8
6923 23:39:08.679490 DQ12 =16, DQ13 =16, DQ14 =8, DQ15 =16
6924 23:39:08.679928
6925 23:39:08.680266
6926 23:39:08.683139 ==
6927 23:39:08.683765 Dram Type= 6, Freq= 0, CH_1, rank 1
6928 23:39:08.689972 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6929 23:39:08.690508 ==
6930 23:39:08.690848
6931 23:39:08.691162
6932 23:39:08.693227 TX Vref Scan disable
6933 23:39:08.693688 == TX Byte 0 ==
6934 23:39:08.696434 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6935 23:39:08.702727 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6936 23:39:08.703237 == TX Byte 1 ==
6937 23:39:08.705890 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6938 23:39:08.712569 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6939 23:39:08.713080 ==
6940 23:39:08.716251 Dram Type= 6, Freq= 0, CH_1, rank 1
6941 23:39:08.719526 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6942 23:39:08.720064 ==
6943 23:39:08.720403
6944 23:39:08.720716
6945 23:39:08.722615 TX Vref Scan disable
6946 23:39:08.723274 == TX Byte 0 ==
6947 23:39:08.725796 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6948 23:39:08.732570 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6949 23:39:08.733140 == TX Byte 1 ==
6950 23:39:08.735910 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6951 23:39:08.742716 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6952 23:39:08.743260
6953 23:39:08.743599 [DATLAT]
6954 23:39:08.743971 Freq=400, CH1 RK1
6955 23:39:08.744316
6956 23:39:08.745866 DATLAT Default: 0xe
6957 23:39:08.749650 0, 0xFFFF, sum = 0
6958 23:39:08.750213 1, 0xFFFF, sum = 0
6959 23:39:08.752617 2, 0xFFFF, sum = 0
6960 23:39:08.753168 3, 0xFFFF, sum = 0
6961 23:39:08.756130 4, 0xFFFF, sum = 0
6962 23:39:08.756672 5, 0xFFFF, sum = 0
6963 23:39:08.759086 6, 0xFFFF, sum = 0
6964 23:39:08.759617 7, 0xFFFF, sum = 0
6965 23:39:08.762554 8, 0xFFFF, sum = 0
6966 23:39:08.763096 9, 0xFFFF, sum = 0
6967 23:39:08.765970 10, 0xFFFF, sum = 0
6968 23:39:08.766504 11, 0xFFFF, sum = 0
6969 23:39:08.768617 12, 0xFFFF, sum = 0
6970 23:39:08.769044 13, 0x0, sum = 1
6971 23:39:08.771928 14, 0x0, sum = 2
6972 23:39:08.772371 15, 0x0, sum = 3
6973 23:39:08.775538 16, 0x0, sum = 4
6974 23:39:08.776156 best_step = 14
6975 23:39:08.776502
6976 23:39:08.776819 ==
6977 23:39:08.778888 Dram Type= 6, Freq= 0, CH_1, rank 1
6978 23:39:08.785375 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6979 23:39:08.785941 ==
6980 23:39:08.786337 RX Vref Scan: 0
6981 23:39:08.786661
6982 23:39:08.788320 RX Vref 0 -> 0, step: 1
6983 23:39:08.788741
6984 23:39:08.792000 RX Delay -295 -> 252, step: 8
6985 23:39:08.798143 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6986 23:39:08.802445 iDelay=217, Bit 1, Center -20 (-239 ~ 200) 440
6987 23:39:08.805230 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
6988 23:39:08.808171 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6989 23:39:08.814988 iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440
6990 23:39:08.818306 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
6991 23:39:08.821564 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6992 23:39:08.825278 iDelay=217, Bit 7, Center -16 (-239 ~ 208) 448
6993 23:39:08.828363 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6994 23:39:08.834856 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6995 23:39:08.838266 iDelay=217, Bit 10, Center -20 (-247 ~ 208) 456
6996 23:39:08.841674 iDelay=217, Bit 11, Center -28 (-255 ~ 200) 456
6997 23:39:08.848584 iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456
6998 23:39:08.852051 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
6999 23:39:08.855372 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
7000 23:39:08.858412 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
7001 23:39:08.858947 ==
7002 23:39:08.861934 Dram Type= 6, Freq= 0, CH_1, rank 1
7003 23:39:08.868237 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7004 23:39:08.868771 ==
7005 23:39:08.869110 DQS Delay:
7006 23:39:08.871465 DQS0 = 28, DQS1 = 36
7007 23:39:08.871996 DQM Delay:
7008 23:39:08.874552 DQM0 = 11, DQM1 = 14
7009 23:39:08.875083 DQ Delay:
7010 23:39:08.878603 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =4
7011 23:39:08.881875 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =12
7012 23:39:08.884612 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
7013 23:39:08.888061 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =24
7014 23:39:08.888486
7015 23:39:08.888822
7016 23:39:08.894649 [DQSOSCAuto] RK1, (LSB)MR18= 0xbd50, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 386 ps
7017 23:39:08.898004 CH1 RK1: MR19=C0C, MR18=BD50
7018 23:39:08.904554 CH1_RK1: MR19=0xC0C, MR18=0xBD50, DQSOSC=386, MR23=63, INC=396, DEC=264
7019 23:39:08.907371 [RxdqsGatingPostProcess] freq 400
7020 23:39:08.911096 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7021 23:39:08.914290 best DQS0 dly(2T, 0.5T) = (0, 10)
7022 23:39:08.917687 best DQS1 dly(2T, 0.5T) = (0, 10)
7023 23:39:08.921200 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7024 23:39:08.925000 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7025 23:39:08.927756 best DQS0 dly(2T, 0.5T) = (0, 10)
7026 23:39:08.931027 best DQS1 dly(2T, 0.5T) = (0, 10)
7027 23:39:08.934403 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7028 23:39:08.937946 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7029 23:39:08.940880 Pre-setting of DQS Precalculation
7030 23:39:08.944347 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7031 23:39:08.954351 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7032 23:39:08.960616 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7033 23:39:08.961199
7034 23:39:08.961605
7035 23:39:08.964421 [Calibration Summary] 800 Mbps
7036 23:39:08.964997 CH 0, Rank 0
7037 23:39:08.967614 SW Impedance : PASS
7038 23:39:08.968188 DUTY Scan : NO K
7039 23:39:08.970857 ZQ Calibration : PASS
7040 23:39:08.974217 Jitter Meter : NO K
7041 23:39:08.974789 CBT Training : PASS
7042 23:39:08.977411 Write leveling : PASS
7043 23:39:08.981061 RX DQS gating : PASS
7044 23:39:08.981678 RX DQ/DQS(RDDQC) : PASS
7045 23:39:08.984476 TX DQ/DQS : PASS
7046 23:39:08.987190 RX DATLAT : PASS
7047 23:39:08.987656 RX DQ/DQS(Engine): PASS
7048 23:39:08.990953 TX OE : NO K
7049 23:39:08.991525 All Pass.
7050 23:39:08.991894
7051 23:39:08.994162 CH 0, Rank 1
7052 23:39:08.994627 SW Impedance : PASS
7053 23:39:08.997440 DUTY Scan : NO K
7054 23:39:08.998070 ZQ Calibration : PASS
7055 23:39:09.001069 Jitter Meter : NO K
7056 23:39:09.004710 CBT Training : PASS
7057 23:39:09.005285 Write leveling : NO K
7058 23:39:09.007377 RX DQS gating : PASS
7059 23:39:09.011056 RX DQ/DQS(RDDQC) : PASS
7060 23:39:09.011672 TX DQ/DQS : PASS
7061 23:39:09.014269 RX DATLAT : PASS
7062 23:39:09.017983 RX DQ/DQS(Engine): PASS
7063 23:39:09.018558 TX OE : NO K
7064 23:39:09.020619 All Pass.
7065 23:39:09.021081
7066 23:39:09.021448 CH 1, Rank 0
7067 23:39:09.024882 SW Impedance : PASS
7068 23:39:09.025458 DUTY Scan : NO K
7069 23:39:09.027249 ZQ Calibration : PASS
7070 23:39:09.031948 Jitter Meter : NO K
7071 23:39:09.032521 CBT Training : PASS
7072 23:39:09.034025 Write leveling : PASS
7073 23:39:09.037420 RX DQS gating : PASS
7074 23:39:09.038001 RX DQ/DQS(RDDQC) : PASS
7075 23:39:09.040307 TX DQ/DQS : PASS
7076 23:39:09.040731 RX DATLAT : PASS
7077 23:39:09.043560 RX DQ/DQS(Engine): PASS
7078 23:39:09.047257 TX OE : NO K
7079 23:39:09.047789 All Pass.
7080 23:39:09.048128
7081 23:39:09.050472 CH 1, Rank 1
7082 23:39:09.050891 SW Impedance : PASS
7083 23:39:09.053974 DUTY Scan : NO K
7084 23:39:09.054506 ZQ Calibration : PASS
7085 23:39:09.057017 Jitter Meter : NO K
7086 23:39:09.060997 CBT Training : PASS
7087 23:39:09.061528 Write leveling : NO K
7088 23:39:09.064151 RX DQS gating : PASS
7089 23:39:09.067260 RX DQ/DQS(RDDQC) : PASS
7090 23:39:09.067856 TX DQ/DQS : PASS
7091 23:39:09.070224 RX DATLAT : PASS
7092 23:39:09.073711 RX DQ/DQS(Engine): PASS
7093 23:39:09.074138 TX OE : NO K
7094 23:39:09.077343 All Pass.
7095 23:39:09.077922
7096 23:39:09.078268 DramC Write-DBI off
7097 23:39:09.080127 PER_BANK_REFRESH: Hybrid Mode
7098 23:39:09.080659 TX_TRACKING: ON
7099 23:39:09.090460 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7100 23:39:09.093806 [FAST_K] Save calibration result to emmc
7101 23:39:09.096868 dramc_set_vcore_voltage set vcore to 725000
7102 23:39:09.100952 Read voltage for 1600, 0
7103 23:39:09.101485 Vio18 = 0
7104 23:39:09.103586 Vcore = 725000
7105 23:39:09.104009 Vdram = 0
7106 23:39:09.104347 Vddq = 0
7107 23:39:09.106608 Vmddr = 0
7108 23:39:09.110245 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7109 23:39:09.117397 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7110 23:39:09.117984 MEM_TYPE=3, freq_sel=13
7111 23:39:09.120159 sv_algorithm_assistance_LP4_3733
7112 23:39:09.126826 ============ PULL DRAM RESETB DOWN ============
7113 23:39:09.130094 ========== PULL DRAM RESETB DOWN end =========
7114 23:39:09.133674 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7115 23:39:09.136893 ===================================
7116 23:39:09.140410 LPDDR4 DRAM CONFIGURATION
7117 23:39:09.143647 ===================================
7118 23:39:09.144187 EX_ROW_EN[0] = 0x0
7119 23:39:09.146994 EX_ROW_EN[1] = 0x0
7120 23:39:09.150010 LP4Y_EN = 0x0
7121 23:39:09.150546 WORK_FSP = 0x1
7122 23:39:09.153409 WL = 0x5
7123 23:39:09.153864 RL = 0x5
7124 23:39:09.156864 BL = 0x2
7125 23:39:09.157389 RPST = 0x0
7126 23:39:09.159986 RD_PRE = 0x0
7127 23:39:09.160546 WR_PRE = 0x1
7128 23:39:09.163100 WR_PST = 0x1
7129 23:39:09.163632 DBI_WR = 0x0
7130 23:39:09.166213 DBI_RD = 0x0
7131 23:39:09.166801 OTF = 0x1
7132 23:39:09.170051 ===================================
7133 23:39:09.173174 ===================================
7134 23:39:09.176460 ANA top config
7135 23:39:09.179670 ===================================
7136 23:39:09.180285 DLL_ASYNC_EN = 0
7137 23:39:09.183048 ALL_SLAVE_EN = 0
7138 23:39:09.186304 NEW_RANK_MODE = 1
7139 23:39:09.189932 DLL_IDLE_MODE = 1
7140 23:39:09.192863 LP45_APHY_COMB_EN = 1
7141 23:39:09.193286 TX_ODT_DIS = 0
7142 23:39:09.196440 NEW_8X_MODE = 1
7143 23:39:09.199635 ===================================
7144 23:39:09.203569 ===================================
7145 23:39:09.206305 data_rate = 3200
7146 23:39:09.209560 CKR = 1
7147 23:39:09.213074 DQ_P2S_RATIO = 8
7148 23:39:09.216463 ===================================
7149 23:39:09.216997 CA_P2S_RATIO = 8
7150 23:39:09.220260 DQ_CA_OPEN = 0
7151 23:39:09.223288 DQ_SEMI_OPEN = 0
7152 23:39:09.226919 CA_SEMI_OPEN = 0
7153 23:39:09.229659 CA_FULL_RATE = 0
7154 23:39:09.233009 DQ_CKDIV4_EN = 0
7155 23:39:09.233555 CA_CKDIV4_EN = 0
7156 23:39:09.236615 CA_PREDIV_EN = 0
7157 23:39:09.239912 PH8_DLY = 12
7158 23:39:09.243352 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7159 23:39:09.246550 DQ_AAMCK_DIV = 4
7160 23:39:09.250116 CA_AAMCK_DIV = 4
7161 23:39:09.250647 CA_ADMCK_DIV = 4
7162 23:39:09.252816 DQ_TRACK_CA_EN = 0
7163 23:39:09.256735 CA_PICK = 1600
7164 23:39:09.259729 CA_MCKIO = 1600
7165 23:39:09.263117 MCKIO_SEMI = 0
7166 23:39:09.266306 PLL_FREQ = 3068
7167 23:39:09.269823 DQ_UI_PI_RATIO = 32
7168 23:39:09.273108 CA_UI_PI_RATIO = 0
7169 23:39:09.276511 ===================================
7170 23:39:09.279617 ===================================
7171 23:39:09.280190 memory_type:LPDDR4
7172 23:39:09.282739 GP_NUM : 10
7173 23:39:09.283223 SRAM_EN : 1
7174 23:39:09.286099 MD32_EN : 0
7175 23:39:09.290323 ===================================
7176 23:39:09.292618 [ANA_INIT] >>>>>>>>>>>>>>
7177 23:39:09.295867 <<<<<< [CONFIGURE PHASE]: ANA_TX
7178 23:39:09.298976 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7179 23:39:09.302422 ===================================
7180 23:39:09.305929 data_rate = 3200,PCW = 0X7600
7181 23:39:09.309466 ===================================
7182 23:39:09.313003 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7183 23:39:09.316215 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7184 23:39:09.322568 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7185 23:39:09.325966 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7186 23:39:09.329069 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7187 23:39:09.332602 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7188 23:39:09.335920 [ANA_INIT] flow start
7189 23:39:09.339088 [ANA_INIT] PLL >>>>>>>>
7190 23:39:09.339512 [ANA_INIT] PLL <<<<<<<<
7191 23:39:09.342193 [ANA_INIT] MIDPI >>>>>>>>
7192 23:39:09.345699 [ANA_INIT] MIDPI <<<<<<<<
7193 23:39:09.346227 [ANA_INIT] DLL >>>>>>>>
7194 23:39:09.349251 [ANA_INIT] DLL <<<<<<<<
7195 23:39:09.352268 [ANA_INIT] flow end
7196 23:39:09.355867 ============ LP4 DIFF to SE enter ============
7197 23:39:09.359398 ============ LP4 DIFF to SE exit ============
7198 23:39:09.362550 [ANA_INIT] <<<<<<<<<<<<<
7199 23:39:09.365975 [Flow] Enable top DCM control >>>>>
7200 23:39:09.368697 [Flow] Enable top DCM control <<<<<
7201 23:39:09.372752 Enable DLL master slave shuffle
7202 23:39:09.375400 ==============================================================
7203 23:39:09.379072 Gating Mode config
7204 23:39:09.386201 ==============================================================
7205 23:39:09.386784 Config description:
7206 23:39:09.395502 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7207 23:39:09.402867 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7208 23:39:09.408697 SELPH_MODE 0: By rank 1: By Phase
7209 23:39:09.412067 ==============================================================
7210 23:39:09.415213 GAT_TRACK_EN = 1
7211 23:39:09.418485 RX_GATING_MODE = 2
7212 23:39:09.422513 RX_GATING_TRACK_MODE = 2
7213 23:39:09.425381 SELPH_MODE = 1
7214 23:39:09.428456 PICG_EARLY_EN = 1
7215 23:39:09.431756 VALID_LAT_VALUE = 1
7216 23:39:09.435293 ==============================================================
7217 23:39:09.438355 Enter into Gating configuration >>>>
7218 23:39:09.442336 Exit from Gating configuration <<<<
7219 23:39:09.445230 Enter into DVFS_PRE_config >>>>>
7220 23:39:09.458242 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7221 23:39:09.461879 Exit from DVFS_PRE_config <<<<<
7222 23:39:09.465046 Enter into PICG configuration >>>>
7223 23:39:09.465645 Exit from PICG configuration <<<<
7224 23:39:09.468691 [RX_INPUT] configuration >>>>>
7225 23:39:09.472139 [RX_INPUT] configuration <<<<<
7226 23:39:09.478513 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7227 23:39:09.481514 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7228 23:39:09.487816 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7229 23:39:09.495169 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7230 23:39:09.501677 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7231 23:39:09.508238 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7232 23:39:09.511316 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7233 23:39:09.514972 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7234 23:39:09.521797 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7235 23:39:09.525049 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7236 23:39:09.528003 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7237 23:39:09.531269 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7238 23:39:09.534363 ===================================
7239 23:39:09.537756 LPDDR4 DRAM CONFIGURATION
7240 23:39:09.541119 ===================================
7241 23:39:09.544639 EX_ROW_EN[0] = 0x0
7242 23:39:09.545195 EX_ROW_EN[1] = 0x0
7243 23:39:09.548314 LP4Y_EN = 0x0
7244 23:39:09.548917 WORK_FSP = 0x1
7245 23:39:09.551435 WL = 0x5
7246 23:39:09.551900 RL = 0x5
7247 23:39:09.554277 BL = 0x2
7248 23:39:09.554743 RPST = 0x0
7249 23:39:09.558199 RD_PRE = 0x0
7250 23:39:09.558758 WR_PRE = 0x1
7251 23:39:09.561322 WR_PST = 0x1
7252 23:39:09.561915 DBI_WR = 0x0
7253 23:39:09.564538 DBI_RD = 0x0
7254 23:39:09.565103 OTF = 0x1
7255 23:39:09.567985 ===================================
7256 23:39:09.574559 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7257 23:39:09.578183 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7258 23:39:09.580996 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7259 23:39:09.584604 ===================================
7260 23:39:09.587469 LPDDR4 DRAM CONFIGURATION
7261 23:39:09.590990 ===================================
7262 23:39:09.594287 EX_ROW_EN[0] = 0x10
7263 23:39:09.594848 EX_ROW_EN[1] = 0x0
7264 23:39:09.598085 LP4Y_EN = 0x0
7265 23:39:09.598582 WORK_FSP = 0x1
7266 23:39:09.601327 WL = 0x5
7267 23:39:09.601925 RL = 0x5
7268 23:39:09.604406 BL = 0x2
7269 23:39:09.604870 RPST = 0x0
7270 23:39:09.607889 RD_PRE = 0x0
7271 23:39:09.608359 WR_PRE = 0x1
7272 23:39:09.611282 WR_PST = 0x1
7273 23:39:09.611749 DBI_WR = 0x0
7274 23:39:09.614231 DBI_RD = 0x0
7275 23:39:09.614659 OTF = 0x1
7276 23:39:09.617863 ===================================
7277 23:39:09.624556 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7278 23:39:09.625080 ==
7279 23:39:09.628037 Dram Type= 6, Freq= 0, CH_0, rank 0
7280 23:39:09.631474 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7281 23:39:09.634589 ==
7282 23:39:09.635105 [Duty_Offset_Calibration]
7283 23:39:09.637643 B0:2 B1:1 CA:1
7284 23:39:09.638165
7285 23:39:09.641285 [DutyScan_Calibration_Flow] k_type=0
7286 23:39:09.650446
7287 23:39:09.650972 ==CLK 0==
7288 23:39:09.653329 Final CLK duty delay cell = 0
7289 23:39:09.656934 [0] MAX Duty = 5156%(X100), DQS PI = 22
7290 23:39:09.660169 [0] MIN Duty = 4907%(X100), DQS PI = 0
7291 23:39:09.660690 [0] AVG Duty = 5031%(X100)
7292 23:39:09.663408
7293 23:39:09.663928 CH0 CLK Duty spec in!! Max-Min= 249%
7294 23:39:09.669997 [DutyScan_Calibration_Flow] ====Done====
7295 23:39:09.670693
7296 23:39:09.673264 [DutyScan_Calibration_Flow] k_type=1
7297 23:39:09.689225
7298 23:39:09.689982 ==DQS 0 ==
7299 23:39:09.692731 Final DQS duty delay cell = -4
7300 23:39:09.695447 [-4] MAX Duty = 5125%(X100), DQS PI = 24
7301 23:39:09.699049 [-4] MIN Duty = 4657%(X100), DQS PI = 0
7302 23:39:09.702070 [-4] AVG Duty = 4891%(X100)
7303 23:39:09.702491
7304 23:39:09.702826 ==DQS 1 ==
7305 23:39:09.705611 Final DQS duty delay cell = 0
7306 23:39:09.708886 [0] MAX Duty = 5218%(X100), DQS PI = 22
7307 23:39:09.712005 [0] MIN Duty = 5062%(X100), DQS PI = 34
7308 23:39:09.715402 [0] AVG Duty = 5140%(X100)
7309 23:39:09.715824
7310 23:39:09.718568 CH0 DQS 0 Duty spec in!! Max-Min= 468%
7311 23:39:09.718993
7312 23:39:09.722080 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7313 23:39:09.726107 [DutyScan_Calibration_Flow] ====Done====
7314 23:39:09.726529
7315 23:39:09.728820 [DutyScan_Calibration_Flow] k_type=3
7316 23:39:09.745817
7317 23:39:09.746362 ==DQM 0 ==
7318 23:39:09.749073 Final DQM duty delay cell = 0
7319 23:39:09.752324 [0] MAX Duty = 5187%(X100), DQS PI = 26
7320 23:39:09.755776 [0] MIN Duty = 4875%(X100), DQS PI = 60
7321 23:39:09.756350 [0] AVG Duty = 5031%(X100)
7322 23:39:09.759214
7323 23:39:09.759787 ==DQM 1 ==
7324 23:39:09.762673 Final DQM duty delay cell = -4
7325 23:39:09.765716 [-4] MAX Duty = 4969%(X100), DQS PI = 22
7326 23:39:09.769421 [-4] MIN Duty = 4813%(X100), DQS PI = 14
7327 23:39:09.772671 [-4] AVG Duty = 4891%(X100)
7328 23:39:09.773240
7329 23:39:09.775546 CH0 DQM 0 Duty spec in!! Max-Min= 312%
7330 23:39:09.776016
7331 23:39:09.778978 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7332 23:39:09.782632 [DutyScan_Calibration_Flow] ====Done====
7333 23:39:09.783095
7334 23:39:09.785288 [DutyScan_Calibration_Flow] k_type=2
7335 23:39:09.803654
7336 23:39:09.804223 ==DQ 0 ==
7337 23:39:09.806537 Final DQ duty delay cell = 0
7338 23:39:09.810355 [0] MAX Duty = 5062%(X100), DQS PI = 26
7339 23:39:09.813310 [0] MIN Duty = 4907%(X100), DQS PI = 0
7340 23:39:09.813886 [0] AVG Duty = 4984%(X100)
7341 23:39:09.816743
7342 23:39:09.817310 ==DQ 1 ==
7343 23:39:09.819761 Final DQ duty delay cell = 0
7344 23:39:09.823428 [0] MAX Duty = 5156%(X100), DQS PI = 22
7345 23:39:09.826484 [0] MIN Duty = 4907%(X100), DQS PI = 34
7346 23:39:09.827085 [0] AVG Duty = 5031%(X100)
7347 23:39:09.829921
7348 23:39:09.832943 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7349 23:39:09.833512
7350 23:39:09.836716 CH0 DQ 1 Duty spec in!! Max-Min= 249%
7351 23:39:09.839383 [DutyScan_Calibration_Flow] ====Done====
7352 23:39:09.839950 ==
7353 23:39:09.843259 Dram Type= 6, Freq= 0, CH_1, rank 0
7354 23:39:09.846343 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7355 23:39:09.846816 ==
7356 23:39:09.849875 [Duty_Offset_Calibration]
7357 23:39:09.850444 B0:1 B1:0 CA:0
7358 23:39:09.850815
7359 23:39:09.853116 [DutyScan_Calibration_Flow] k_type=0
7360 23:39:09.862793
7361 23:39:09.863211 ==CLK 0==
7362 23:39:09.866073 Final CLK duty delay cell = -4
7363 23:39:09.869534 [-4] MAX Duty = 4969%(X100), DQS PI = 20
7364 23:39:09.872411 [-4] MIN Duty = 4844%(X100), DQS PI = 50
7365 23:39:09.875655 [-4] AVG Duty = 4906%(X100)
7366 23:39:09.876076
7367 23:39:09.879719 CH1 CLK Duty spec in!! Max-Min= 125%
7368 23:39:09.882850 [DutyScan_Calibration_Flow] ====Done====
7369 23:39:09.883373
7370 23:39:09.885516 [DutyScan_Calibration_Flow] k_type=1
7371 23:39:09.903033
7372 23:39:09.903587 ==DQS 0 ==
7373 23:39:09.906098 Final DQS duty delay cell = 0
7374 23:39:09.909228 [0] MAX Duty = 5094%(X100), DQS PI = 16
7375 23:39:09.912310 [0] MIN Duty = 4844%(X100), DQS PI = 48
7376 23:39:09.915844 [0] AVG Duty = 4969%(X100)
7377 23:39:09.916373
7378 23:39:09.916710 ==DQS 1 ==
7379 23:39:09.919839 Final DQS duty delay cell = 0
7380 23:39:09.922569 [0] MAX Duty = 5249%(X100), DQS PI = 16
7381 23:39:09.925875 [0] MIN Duty = 4969%(X100), DQS PI = 6
7382 23:39:09.929199 [0] AVG Duty = 5109%(X100)
7383 23:39:09.929777
7384 23:39:09.932635 CH1 DQS 0 Duty spec in!! Max-Min= 250%
7385 23:39:09.933161
7386 23:39:09.935783 CH1 DQS 1 Duty spec in!! Max-Min= 280%
7387 23:39:09.938840 [DutyScan_Calibration_Flow] ====Done====
7388 23:39:09.939258
7389 23:39:09.942469 [DutyScan_Calibration_Flow] k_type=3
7390 23:39:09.959652
7391 23:39:09.960218 ==DQM 0 ==
7392 23:39:09.962958 Final DQM duty delay cell = 0
7393 23:39:09.966425 [0] MAX Duty = 5187%(X100), DQS PI = 8
7394 23:39:09.970331 [0] MIN Duty = 4969%(X100), DQS PI = 48
7395 23:39:09.970901 [0] AVG Duty = 5078%(X100)
7396 23:39:09.972874
7397 23:39:09.973436 ==DQM 1 ==
7398 23:39:09.976531 Final DQM duty delay cell = 0
7399 23:39:09.979588 [0] MAX Duty = 5093%(X100), DQS PI = 40
7400 23:39:09.982841 [0] MIN Duty = 4907%(X100), DQS PI = 54
7401 23:39:09.983417 [0] AVG Duty = 5000%(X100)
7402 23:39:09.986584
7403 23:39:09.990051 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7404 23:39:09.990517
7405 23:39:09.993388 CH1 DQM 1 Duty spec in!! Max-Min= 186%
7406 23:39:09.996634 [DutyScan_Calibration_Flow] ====Done====
7407 23:39:09.997205
7408 23:39:09.999326 [DutyScan_Calibration_Flow] k_type=2
7409 23:39:10.016171
7410 23:39:10.016757 ==DQ 0 ==
7411 23:39:10.018686 Final DQ duty delay cell = -4
7412 23:39:10.022064 [-4] MAX Duty = 5062%(X100), DQS PI = 12
7413 23:39:10.025473 [-4] MIN Duty = 4875%(X100), DQS PI = 46
7414 23:39:10.029056 [-4] AVG Duty = 4968%(X100)
7415 23:39:10.029675
7416 23:39:10.030057 ==DQ 1 ==
7417 23:39:10.032658 Final DQ duty delay cell = 0
7418 23:39:10.035688 [0] MAX Duty = 5093%(X100), DQS PI = 16
7419 23:39:10.039052 [0] MIN Duty = 4938%(X100), DQS PI = 8
7420 23:39:10.039619 [0] AVG Duty = 5015%(X100)
7421 23:39:10.042014
7422 23:39:10.045368 CH1 DQ 0 Duty spec in!! Max-Min= 187%
7423 23:39:10.045967
7424 23:39:10.049295 CH1 DQ 1 Duty spec in!! Max-Min= 155%
7425 23:39:10.052439 [DutyScan_Calibration_Flow] ====Done====
7426 23:39:10.055254 nWR fixed to 30
7427 23:39:10.055748 [ModeRegInit_LP4] CH0 RK0
7428 23:39:10.058898 [ModeRegInit_LP4] CH0 RK1
7429 23:39:10.062197 [ModeRegInit_LP4] CH1 RK0
7430 23:39:10.065474 [ModeRegInit_LP4] CH1 RK1
7431 23:39:10.066097 match AC timing 5
7432 23:39:10.072207 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7433 23:39:10.075194 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7434 23:39:10.078686 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7435 23:39:10.085316 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7436 23:39:10.088903 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7437 23:39:10.089368 [MiockJmeterHQA]
7438 23:39:10.089786
7439 23:39:10.092150 [DramcMiockJmeter] u1RxGatingPI = 0
7440 23:39:10.095454 0 : 4257, 4029
7441 23:39:10.096036 4 : 4253, 4026
7442 23:39:10.098932 8 : 4252, 4027
7443 23:39:10.099405 12 : 4363, 4137
7444 23:39:10.099791 16 : 4252, 4027
7445 23:39:10.102403 20 : 4255, 4029
7446 23:39:10.102978 24 : 4253, 4026
7447 23:39:10.105621 28 : 4363, 4137
7448 23:39:10.106202 32 : 4252, 4027
7449 23:39:10.109045 36 : 4363, 4137
7450 23:39:10.109669 40 : 4252, 4027
7451 23:39:10.110137 44 : 4252, 4027
7452 23:39:10.111882 48 : 4253, 4026
7453 23:39:10.112350 52 : 4257, 4032
7454 23:39:10.115706 56 : 4363, 4137
7455 23:39:10.116287 60 : 4250, 4027
7456 23:39:10.119400 64 : 4361, 4137
7457 23:39:10.119974 68 : 4250, 4026
7458 23:39:10.120354 72 : 4250, 4027
7459 23:39:10.122356 76 : 4250, 4027
7460 23:39:10.122827 80 : 4361, 4137
7461 23:39:10.125719 84 : 4250, 4025
7462 23:39:10.126296 88 : 4360, 21
7463 23:39:10.129228 92 : 4361, 0
7464 23:39:10.129845 96 : 4250, 0
7465 23:39:10.130233 100 : 4250, 0
7466 23:39:10.132113 104 : 4250, 0
7467 23:39:10.132616 108 : 4250, 0
7468 23:39:10.133001 112 : 4250, 0
7469 23:39:10.135309 116 : 4250, 0
7470 23:39:10.135779 120 : 4250, 0
7471 23:39:10.139078 124 : 4250, 0
7472 23:39:10.139551 128 : 4250, 0
7473 23:39:10.139927 132 : 4360, 0
7474 23:39:10.141854 136 : 4250, 0
7475 23:39:10.142287 140 : 4250, 0
7476 23:39:10.145855 144 : 4361, 0
7477 23:39:10.146283 148 : 4361, 0
7478 23:39:10.146626 152 : 4250, 0
7479 23:39:10.148876 156 : 4250, 0
7480 23:39:10.149304 160 : 4250, 0
7481 23:39:10.152619 164 : 4250, 0
7482 23:39:10.153329 168 : 4250, 0
7483 23:39:10.153739 172 : 4250, 0
7484 23:39:10.155719 176 : 4250, 0
7485 23:39:10.156246 180 : 4361, 0
7486 23:39:10.156596 184 : 4360, 0
7487 23:39:10.158772 188 : 4250, 0
7488 23:39:10.159298 192 : 4361, 0
7489 23:39:10.162091 196 : 4360, 0
7490 23:39:10.162617 200 : 4361, 0
7491 23:39:10.165348 204 : 4250, 1299
7492 23:39:10.165931 208 : 4252, 3965
7493 23:39:10.166286 212 : 4250, 4027
7494 23:39:10.168964 216 : 4250, 4027
7495 23:39:10.169493 220 : 4360, 4137
7496 23:39:10.172043 224 : 4250, 4027
7497 23:39:10.172615 228 : 4250, 4027
7498 23:39:10.175398 232 : 4360, 4138
7499 23:39:10.175873 236 : 4361, 4137
7500 23:39:10.178501 240 : 4248, 4024
7501 23:39:10.178978 244 : 4361, 4138
7502 23:39:10.182096 248 : 4360, 4137
7503 23:39:10.182638 252 : 4250, 4026
7504 23:39:10.185471 256 : 4250, 4027
7505 23:39:10.186047 260 : 4250, 4027
7506 23:39:10.188768 264 : 4250, 4027
7507 23:39:10.189248 268 : 4250, 4026
7508 23:39:10.189634 272 : 4250, 4026
7509 23:39:10.192051 276 : 4253, 4029
7510 23:39:10.192593 280 : 4250, 4027
7511 23:39:10.195030 284 : 4360, 4137
7512 23:39:10.195461 288 : 4361, 4137
7513 23:39:10.198556 292 : 4250, 4027
7514 23:39:10.199182 296 : 4361, 4137
7515 23:39:10.202070 300 : 4360, 4137
7516 23:39:10.202706 304 : 4250, 4026
7517 23:39:10.205293 308 : 4250, 3962
7518 23:39:10.205752 312 : 4253, 1986
7519 23:39:10.206103
7520 23:39:10.208798 MIOCK jitter meter ch=0
7521 23:39:10.209320
7522 23:39:10.211662 1T = (312-88) = 224 dly cells
7523 23:39:10.215610 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7524 23:39:10.216132 ==
7525 23:39:10.218625 Dram Type= 6, Freq= 0, CH_0, rank 0
7526 23:39:10.225735 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7527 23:39:10.226280 ==
7528 23:39:10.228610 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7529 23:39:10.235377 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7530 23:39:10.238767 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7531 23:39:10.245164 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7532 23:39:10.253111 [CA 0] Center 42 (12~73) winsize 62
7533 23:39:10.257112 [CA 1] Center 42 (12~73) winsize 62
7534 23:39:10.259615 [CA 2] Center 38 (8~68) winsize 61
7535 23:39:10.262989 [CA 3] Center 37 (8~67) winsize 60
7536 23:39:10.266209 [CA 4] Center 36 (6~66) winsize 61
7537 23:39:10.270491 [CA 5] Center 35 (6~64) winsize 59
7538 23:39:10.271043
7539 23:39:10.273322 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7540 23:39:10.273941
7541 23:39:10.277275 [CATrainingPosCal] consider 1 rank data
7542 23:39:10.279887 u2DelayCellTimex100 = 290/100 ps
7543 23:39:10.283938 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7544 23:39:10.289552 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7545 23:39:10.292815 CA2 delay=38 (8~68),Diff = 3 PI (10 cell)
7546 23:39:10.296251 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7547 23:39:10.299468 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7548 23:39:10.302873 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7549 23:39:10.303401
7550 23:39:10.306313 CA PerBit enable=1, Macro0, CA PI delay=35
7551 23:39:10.306877
7552 23:39:10.309677 [CBTSetCACLKResult] CA Dly = 35
7553 23:39:10.312961 CS Dly: 8 (0~39)
7554 23:39:10.316578 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7555 23:39:10.319682 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7556 23:39:10.320245 ==
7557 23:39:10.322978 Dram Type= 6, Freq= 0, CH_0, rank 1
7558 23:39:10.326415 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7559 23:39:10.329279 ==
7560 23:39:10.332808 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7561 23:39:10.336457 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7562 23:39:10.342982 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7563 23:39:10.346252 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7564 23:39:10.356547 [CA 0] Center 42 (12~73) winsize 62
7565 23:39:10.360159 [CA 1] Center 42 (12~73) winsize 62
7566 23:39:10.362993 [CA 2] Center 38 (8~68) winsize 61
7567 23:39:10.366407 [CA 3] Center 37 (8~67) winsize 60
7568 23:39:10.369988 [CA 4] Center 36 (6~66) winsize 61
7569 23:39:10.373368 [CA 5] Center 35 (5~65) winsize 61
7570 23:39:10.373984
7571 23:39:10.376043 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7572 23:39:10.376512
7573 23:39:10.380081 [CATrainingPosCal] consider 2 rank data
7574 23:39:10.383666 u2DelayCellTimex100 = 290/100 ps
7575 23:39:10.386283 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7576 23:39:10.393266 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7577 23:39:10.396618 CA2 delay=38 (8~68),Diff = 3 PI (10 cell)
7578 23:39:10.399710 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7579 23:39:10.403143 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7580 23:39:10.406234 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7581 23:39:10.406706
7582 23:39:10.409511 CA PerBit enable=1, Macro0, CA PI delay=35
7583 23:39:10.410106
7584 23:39:10.412882 [CBTSetCACLKResult] CA Dly = 35
7585 23:39:10.416341 CS Dly: 9 (0~42)
7586 23:39:10.419313 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7587 23:39:10.422860 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7588 23:39:10.423327
7589 23:39:10.426196 ----->DramcWriteLeveling(PI) begin...
7590 23:39:10.426773 ==
7591 23:39:10.429552 Dram Type= 6, Freq= 0, CH_0, rank 0
7592 23:39:10.432827 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7593 23:39:10.436722 ==
7594 23:39:10.437242 Write leveling (Byte 0): 36 => 36
7595 23:39:10.440031 Write leveling (Byte 1): 27 => 27
7596 23:39:10.442692 DramcWriteLeveling(PI) end<-----
7597 23:39:10.443308
7598 23:39:10.443686 ==
7599 23:39:10.445879 Dram Type= 6, Freq= 0, CH_0, rank 0
7600 23:39:10.452932 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7601 23:39:10.453511 ==
7602 23:39:10.453890 [Gating] SW mode calibration
7603 23:39:10.462682 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7604 23:39:10.465821 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7605 23:39:10.472731 1 4 0 | B1->B0 | 2323 2726 | 0 1 | (0 0) (1 1)
7606 23:39:10.475811 1 4 4 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
7607 23:39:10.479389 1 4 8 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
7608 23:39:10.485994 1 4 12 | B1->B0 | 2323 3939 | 0 1 | (0 0) (0 0)
7609 23:39:10.488916 1 4 16 | B1->B0 | 2424 3c3c | 0 0 | (0 0) (0 0)
7610 23:39:10.492805 1 4 20 | B1->B0 | 3333 3a3a | 0 0 | (0 0) (0 0)
7611 23:39:10.495932 1 4 24 | B1->B0 | 3434 3a39 | 1 1 | (1 1) (0 0)
7612 23:39:10.502662 1 4 28 | B1->B0 | 3434 3635 | 1 1 | (1 1) (1 1)
7613 23:39:10.505723 1 5 0 | B1->B0 | 3434 3737 | 1 0 | (1 1) (1 1)
7614 23:39:10.509728 1 5 4 | B1->B0 | 3434 3838 | 1 0 | (1 1) (0 0)
7615 23:39:10.515973 1 5 8 | B1->B0 | 3434 3636 | 1 0 | (1 1) (0 0)
7616 23:39:10.519638 1 5 12 | B1->B0 | 3434 2a29 | 1 1 | (1 1) (1 0)
7617 23:39:10.522771 1 5 16 | B1->B0 | 3434 2929 | 1 0 | (1 1) (0 0)
7618 23:39:10.529859 1 5 20 | B1->B0 | 2323 2d2d | 0 0 | (1 0) (1 1)
7619 23:39:10.532571 1 5 24 | B1->B0 | 2323 2727 | 0 1 | (0 0) (0 0)
7620 23:39:10.536117 1 5 28 | B1->B0 | 2323 2e2d | 0 1 | (0 0) (0 0)
7621 23:39:10.542248 1 6 0 | B1->B0 | 2323 2828 | 0 0 | (0 0) (1 1)
7622 23:39:10.545774 1 6 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7623 23:39:10.549343 1 6 8 | B1->B0 | 2323 3231 | 0 1 | (0 0) (1 1)
7624 23:39:10.555844 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7625 23:39:10.559521 1 6 16 | B1->B0 | 2626 4646 | 0 0 | (0 0) (0 0)
7626 23:39:10.562376 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7627 23:39:10.569181 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7628 23:39:10.572598 1 6 28 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
7629 23:39:10.575588 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7630 23:39:10.581926 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7631 23:39:10.585671 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7632 23:39:10.588706 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7633 23:39:10.595782 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7634 23:39:10.598904 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7635 23:39:10.602081 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7636 23:39:10.608697 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7637 23:39:10.611953 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7638 23:39:10.615062 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7639 23:39:10.621603 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7640 23:39:10.624845 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7641 23:39:10.628666 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7642 23:39:10.635705 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7643 23:39:10.638379 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7644 23:39:10.642288 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7645 23:39:10.648810 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7646 23:39:10.651607 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7647 23:39:10.654851 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7648 23:39:10.661676 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7649 23:39:10.665234 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7650 23:39:10.668642 Total UI for P1: 0, mck2ui 16
7651 23:39:10.671617 best dqsien dly found for B0: ( 1, 9, 12)
7652 23:39:10.674839 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7653 23:39:10.681552 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7654 23:39:10.682129 Total UI for P1: 0, mck2ui 16
7655 23:39:10.684782 best dqsien dly found for B1: ( 1, 9, 20)
7656 23:39:10.691190 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
7657 23:39:10.694622 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7658 23:39:10.695279
7659 23:39:10.698314 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
7660 23:39:10.701550 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7661 23:39:10.705036 [Gating] SW calibration Done
7662 23:39:10.705862 ==
7663 23:39:10.708040 Dram Type= 6, Freq= 0, CH_0, rank 0
7664 23:39:10.711169 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7665 23:39:10.711740 ==
7666 23:39:10.714899 RX Vref Scan: 0
7667 23:39:10.715630
7668 23:39:10.716214 RX Vref 0 -> 0, step: 1
7669 23:39:10.716735
7670 23:39:10.717704 RX Delay 0 -> 252, step: 8
7671 23:39:10.720881 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
7672 23:39:10.727969 iDelay=200, Bit 1, Center 143 (88 ~ 199) 112
7673 23:39:10.731071 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
7674 23:39:10.734565 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7675 23:39:10.737749 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7676 23:39:10.740939 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7677 23:39:10.747823 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7678 23:39:10.751292 iDelay=200, Bit 7, Center 143 (96 ~ 191) 96
7679 23:39:10.754651 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
7680 23:39:10.757573 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
7681 23:39:10.761206 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
7682 23:39:10.764392 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7683 23:39:10.771079 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
7684 23:39:10.774554 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7685 23:39:10.777554 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7686 23:39:10.781036 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7687 23:39:10.781615 ==
7688 23:39:10.784319 Dram Type= 6, Freq= 0, CH_0, rank 0
7689 23:39:10.790637 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7690 23:39:10.791148 ==
7691 23:39:10.791492 DQS Delay:
7692 23:39:10.794192 DQS0 = 0, DQS1 = 0
7693 23:39:10.794712 DQM Delay:
7694 23:39:10.797448 DQM0 = 137, DQM1 = 130
7695 23:39:10.798162 DQ Delay:
7696 23:39:10.801057 DQ0 =135, DQ1 =143, DQ2 =135, DQ3 =131
7697 23:39:10.804188 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =143
7698 23:39:10.807386 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
7699 23:39:10.810804 DQ12 =139, DQ13 =135, DQ14 =139, DQ15 =135
7700 23:39:10.811229
7701 23:39:10.811566
7702 23:39:10.811879 ==
7703 23:39:10.813773 Dram Type= 6, Freq= 0, CH_0, rank 0
7704 23:39:10.820509 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7705 23:39:10.821036 ==
7706 23:39:10.821380
7707 23:39:10.821750
7708 23:39:10.822060 TX Vref Scan disable
7709 23:39:10.823846 == TX Byte 0 ==
7710 23:39:10.827584 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7711 23:39:10.833870 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7712 23:39:10.834300 == TX Byte 1 ==
7713 23:39:10.837427 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7714 23:39:10.844164 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7715 23:39:10.844771 ==
7716 23:39:10.847916 Dram Type= 6, Freq= 0, CH_0, rank 0
7717 23:39:10.850441 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7718 23:39:10.850872 ==
7719 23:39:10.862682
7720 23:39:10.866203 TX Vref early break, caculate TX vref
7721 23:39:10.869347 TX Vref=16, minBit 0, minWin=23, winSum=378
7722 23:39:10.872967 TX Vref=18, minBit 0, minWin=23, winSum=387
7723 23:39:10.876437 TX Vref=20, minBit 0, minWin=24, winSum=400
7724 23:39:10.880102 TX Vref=22, minBit 0, minWin=24, winSum=410
7725 23:39:10.882654 TX Vref=24, minBit 0, minWin=25, winSum=416
7726 23:39:10.889628 TX Vref=26, minBit 2, minWin=25, winSum=422
7727 23:39:10.892589 TX Vref=28, minBit 6, minWin=25, winSum=425
7728 23:39:10.896382 TX Vref=30, minBit 0, minWin=25, winSum=413
7729 23:39:10.899560 TX Vref=32, minBit 6, minWin=23, winSum=402
7730 23:39:10.906330 [TxChooseVref] Worse bit 6, Min win 25, Win sum 425, Final Vref 28
7731 23:39:10.906952
7732 23:39:10.907337 Final TX Range 0 Vref 28
7733 23:39:10.909852
7734 23:39:10.910484 ==
7735 23:39:10.912698 Dram Type= 6, Freq= 0, CH_0, rank 0
7736 23:39:10.915983 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7737 23:39:10.916905 ==
7738 23:39:10.917321
7739 23:39:10.917732
7740 23:39:10.919693 TX Vref Scan disable
7741 23:39:10.922978 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7742 23:39:10.926152 == TX Byte 0 ==
7743 23:39:10.929327 u2DelayCellOfst[0]=10 cells (3 PI)
7744 23:39:10.932673 u2DelayCellOfst[1]=13 cells (4 PI)
7745 23:39:10.936195 u2DelayCellOfst[2]=10 cells (3 PI)
7746 23:39:10.939065 u2DelayCellOfst[3]=10 cells (3 PI)
7747 23:39:10.942886 u2DelayCellOfst[4]=6 cells (2 PI)
7748 23:39:10.943452 u2DelayCellOfst[5]=0 cells (0 PI)
7749 23:39:10.946123 u2DelayCellOfst[6]=16 cells (5 PI)
7750 23:39:10.948995 u2DelayCellOfst[7]=16 cells (5 PI)
7751 23:39:10.955985 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7752 23:39:10.959448 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7753 23:39:10.960013 == TX Byte 1 ==
7754 23:39:10.962323 u2DelayCellOfst[8]=0 cells (0 PI)
7755 23:39:10.965378 u2DelayCellOfst[9]=3 cells (1 PI)
7756 23:39:10.969118 u2DelayCellOfst[10]=10 cells (3 PI)
7757 23:39:10.972516 u2DelayCellOfst[11]=3 cells (1 PI)
7758 23:39:10.975748 u2DelayCellOfst[12]=13 cells (4 PI)
7759 23:39:10.979032 u2DelayCellOfst[13]=10 cells (3 PI)
7760 23:39:10.982418 u2DelayCellOfst[14]=16 cells (5 PI)
7761 23:39:10.985608 u2DelayCellOfst[15]=13 cells (4 PI)
7762 23:39:10.988921 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7763 23:39:10.992055 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7764 23:39:10.995731 DramC Write-DBI on
7765 23:39:10.996292 ==
7766 23:39:10.999063 Dram Type= 6, Freq= 0, CH_0, rank 0
7767 23:39:11.002738 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7768 23:39:11.003304 ==
7769 23:39:11.003680
7770 23:39:11.004023
7771 23:39:11.006163 TX Vref Scan disable
7772 23:39:11.009316 == TX Byte 0 ==
7773 23:39:11.012068 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
7774 23:39:11.015533 == TX Byte 1 ==
7775 23:39:11.018566 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
7776 23:39:11.019082 DramC Write-DBI off
7777 23:39:11.019457
7778 23:39:11.022221 [DATLAT]
7779 23:39:11.022686 Freq=1600, CH0 RK0
7780 23:39:11.023061
7781 23:39:11.025126 DATLAT Default: 0xf
7782 23:39:11.025625 0, 0xFFFF, sum = 0
7783 23:39:11.028682 1, 0xFFFF, sum = 0
7784 23:39:11.029213 2, 0xFFFF, sum = 0
7785 23:39:11.031864 3, 0xFFFF, sum = 0
7786 23:39:11.032337 4, 0xFFFF, sum = 0
7787 23:39:11.035402 5, 0xFFFF, sum = 0
7788 23:39:11.035931 6, 0xFFFF, sum = 0
7789 23:39:11.038977 7, 0xFFFF, sum = 0
7790 23:39:11.042571 8, 0xFFFF, sum = 0
7791 23:39:11.043108 9, 0xFFFF, sum = 0
7792 23:39:11.045448 10, 0xFFFF, sum = 0
7793 23:39:11.045925 11, 0xFFFF, sum = 0
7794 23:39:11.048449 12, 0xFFFF, sum = 0
7795 23:39:11.048981 13, 0xFFFF, sum = 0
7796 23:39:11.052186 14, 0x0, sum = 1
7797 23:39:11.052719 15, 0x0, sum = 2
7798 23:39:11.055105 16, 0x0, sum = 3
7799 23:39:11.055635 17, 0x0, sum = 4
7800 23:39:11.058376 best_step = 15
7801 23:39:11.058800
7802 23:39:11.059138 ==
7803 23:39:11.061365 Dram Type= 6, Freq= 0, CH_0, rank 0
7804 23:39:11.065076 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7805 23:39:11.065623 ==
7806 23:39:11.065976 RX Vref Scan: 1
7807 23:39:11.066298
7808 23:39:11.068245 Set Vref Range= 24 -> 127
7809 23:39:11.068667
7810 23:39:11.071812 RX Vref 24 -> 127, step: 1
7811 23:39:11.072337
7812 23:39:11.074948 RX Delay 19 -> 252, step: 4
7813 23:39:11.075482
7814 23:39:11.078355 Set Vref, RX VrefLevel [Byte0]: 24
7815 23:39:11.082186 [Byte1]: 24
7816 23:39:11.082728
7817 23:39:11.084763 Set Vref, RX VrefLevel [Byte0]: 25
7818 23:39:11.088301 [Byte1]: 25
7819 23:39:11.088818
7820 23:39:11.091254 Set Vref, RX VrefLevel [Byte0]: 26
7821 23:39:11.094912 [Byte1]: 26
7822 23:39:11.098842
7823 23:39:11.099399 Set Vref, RX VrefLevel [Byte0]: 27
7824 23:39:11.101673 [Byte1]: 27
7825 23:39:11.106437
7826 23:39:11.106963 Set Vref, RX VrefLevel [Byte0]: 28
7827 23:39:11.109734 [Byte1]: 28
7828 23:39:11.113684
7829 23:39:11.114211 Set Vref, RX VrefLevel [Byte0]: 29
7830 23:39:11.117019 [Byte1]: 29
7831 23:39:11.121385
7832 23:39:11.122010 Set Vref, RX VrefLevel [Byte0]: 30
7833 23:39:11.125135 [Byte1]: 30
7834 23:39:11.129421
7835 23:39:11.130043 Set Vref, RX VrefLevel [Byte0]: 31
7836 23:39:11.132429 [Byte1]: 31
7837 23:39:11.136655
7838 23:39:11.139921 Set Vref, RX VrefLevel [Byte0]: 32
7839 23:39:11.143073 [Byte1]: 32
7840 23:39:11.143540
7841 23:39:11.146174 Set Vref, RX VrefLevel [Byte0]: 33
7842 23:39:11.149654 [Byte1]: 33
7843 23:39:11.150214
7844 23:39:11.153116 Set Vref, RX VrefLevel [Byte0]: 34
7845 23:39:11.156078 [Byte1]: 34
7846 23:39:11.156543
7847 23:39:11.159800 Set Vref, RX VrefLevel [Byte0]: 35
7848 23:39:11.163061 [Byte1]: 35
7849 23:39:11.167264
7850 23:39:11.167827 Set Vref, RX VrefLevel [Byte0]: 36
7851 23:39:11.170287 [Byte1]: 36
7852 23:39:11.174379
7853 23:39:11.174840 Set Vref, RX VrefLevel [Byte0]: 37
7854 23:39:11.177709 [Byte1]: 37
7855 23:39:11.181891
7856 23:39:11.182451 Set Vref, RX VrefLevel [Byte0]: 38
7857 23:39:11.185386 [Byte1]: 38
7858 23:39:11.189832
7859 23:39:11.190295 Set Vref, RX VrefLevel [Byte0]: 39
7860 23:39:11.193285 [Byte1]: 39
7861 23:39:11.197329
7862 23:39:11.197963 Set Vref, RX VrefLevel [Byte0]: 40
7863 23:39:11.200348 [Byte1]: 40
7864 23:39:11.204822
7865 23:39:11.205384 Set Vref, RX VrefLevel [Byte0]: 41
7866 23:39:11.208208 [Byte1]: 41
7867 23:39:11.212812
7868 23:39:11.213375 Set Vref, RX VrefLevel [Byte0]: 42
7869 23:39:11.215436 [Byte1]: 42
7870 23:39:11.219897
7871 23:39:11.220457 Set Vref, RX VrefLevel [Byte0]: 43
7872 23:39:11.223077 [Byte1]: 43
7873 23:39:11.227439
7874 23:39:11.227997 Set Vref, RX VrefLevel [Byte0]: 44
7875 23:39:11.230718 [Byte1]: 44
7876 23:39:11.235222
7877 23:39:11.235797 Set Vref, RX VrefLevel [Byte0]: 45
7878 23:39:11.238299 [Byte1]: 45
7879 23:39:11.242905
7880 23:39:11.243465 Set Vref, RX VrefLevel [Byte0]: 46
7881 23:39:11.245820 [Byte1]: 46
7882 23:39:11.250223
7883 23:39:11.250793 Set Vref, RX VrefLevel [Byte0]: 47
7884 23:39:11.253279 [Byte1]: 47
7885 23:39:11.257644
7886 23:39:11.258109 Set Vref, RX VrefLevel [Byte0]: 48
7887 23:39:11.260857 [Byte1]: 48
7888 23:39:11.265102
7889 23:39:11.265693 Set Vref, RX VrefLevel [Byte0]: 49
7890 23:39:11.271500 [Byte1]: 49
7891 23:39:11.272084
7892 23:39:11.275268 Set Vref, RX VrefLevel [Byte0]: 50
7893 23:39:11.278373 [Byte1]: 50
7894 23:39:11.278946
7895 23:39:11.281762 Set Vref, RX VrefLevel [Byte0]: 51
7896 23:39:11.285220 [Byte1]: 51
7897 23:39:11.285824
7898 23:39:11.288317 Set Vref, RX VrefLevel [Byte0]: 52
7899 23:39:11.292005 [Byte1]: 52
7900 23:39:11.295499
7901 23:39:11.296066 Set Vref, RX VrefLevel [Byte0]: 53
7902 23:39:11.298541 [Byte1]: 53
7903 23:39:11.302966
7904 23:39:11.303459 Set Vref, RX VrefLevel [Byte0]: 54
7905 23:39:11.306183 [Byte1]: 54
7906 23:39:11.310429
7907 23:39:11.310849 Set Vref, RX VrefLevel [Byte0]: 55
7908 23:39:11.313672 [Byte1]: 55
7909 23:39:11.318352
7910 23:39:11.318968 Set Vref, RX VrefLevel [Byte0]: 56
7911 23:39:11.321606 [Byte1]: 56
7912 23:39:11.325801
7913 23:39:11.326359 Set Vref, RX VrefLevel [Byte0]: 57
7914 23:39:11.329059 [Byte1]: 57
7915 23:39:11.333956
7916 23:39:11.334522 Set Vref, RX VrefLevel [Byte0]: 58
7917 23:39:11.336917 [Byte1]: 58
7918 23:39:11.341616
7919 23:39:11.342183 Set Vref, RX VrefLevel [Byte0]: 59
7920 23:39:11.344653 [Byte1]: 59
7921 23:39:11.349111
7922 23:39:11.349725 Set Vref, RX VrefLevel [Byte0]: 60
7923 23:39:11.351666 [Byte1]: 60
7924 23:39:11.356190
7925 23:39:11.356755 Set Vref, RX VrefLevel [Byte0]: 61
7926 23:39:11.359672 [Byte1]: 61
7927 23:39:11.363565
7928 23:39:11.364125 Set Vref, RX VrefLevel [Byte0]: 62
7929 23:39:11.367316 [Byte1]: 62
7930 23:39:11.371529
7931 23:39:11.372089 Set Vref, RX VrefLevel [Byte0]: 63
7932 23:39:11.374500 [Byte1]: 63
7933 23:39:11.378987
7934 23:39:11.379544 Set Vref, RX VrefLevel [Byte0]: 64
7935 23:39:11.382220 [Byte1]: 64
7936 23:39:11.386323
7937 23:39:11.386787 Set Vref, RX VrefLevel [Byte0]: 65
7938 23:39:11.389539 [Byte1]: 65
7939 23:39:11.393759
7940 23:39:11.394217 Set Vref, RX VrefLevel [Byte0]: 66
7941 23:39:11.397540 [Byte1]: 66
7942 23:39:11.401496
7943 23:39:11.402038 Set Vref, RX VrefLevel [Byte0]: 67
7944 23:39:11.405099 [Byte1]: 67
7945 23:39:11.408844
7946 23:39:11.409678 Set Vref, RX VrefLevel [Byte0]: 68
7947 23:39:11.412190 [Byte1]: 68
7948 23:39:11.416775
7949 23:39:11.417334 Set Vref, RX VrefLevel [Byte0]: 69
7950 23:39:11.420173 [Byte1]: 69
7951 23:39:11.424393
7952 23:39:11.424954 Set Vref, RX VrefLevel [Byte0]: 70
7953 23:39:11.427828 [Byte1]: 70
7954 23:39:11.431824
7955 23:39:11.432570 Set Vref, RX VrefLevel [Byte0]: 71
7956 23:39:11.435644 [Byte1]: 71
7957 23:39:11.440111
7958 23:39:11.440669 Set Vref, RX VrefLevel [Byte0]: 72
7959 23:39:11.442486 [Byte1]: 72
7960 23:39:11.447515
7961 23:39:11.448078 Set Vref, RX VrefLevel [Byte0]: 73
7962 23:39:11.450353 [Byte1]: 73
7963 23:39:11.454681
7964 23:39:11.455241 Set Vref, RX VrefLevel [Byte0]: 74
7965 23:39:11.458165 [Byte1]: 74
7966 23:39:11.462300
7967 23:39:11.462855 Final RX Vref Byte 0 = 56 to rank0
7968 23:39:11.465263 Final RX Vref Byte 1 = 60 to rank0
7969 23:39:11.468823 Final RX Vref Byte 0 = 56 to rank1
7970 23:39:11.472170 Final RX Vref Byte 1 = 60 to rank1==
7971 23:39:11.475810 Dram Type= 6, Freq= 0, CH_0, rank 0
7972 23:39:11.482303 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7973 23:39:11.482772 ==
7974 23:39:11.483145 DQS Delay:
7975 23:39:11.483488 DQS0 = 0, DQS1 = 0
7976 23:39:11.485697 DQM Delay:
7977 23:39:11.486159 DQM0 = 133, DQM1 = 127
7978 23:39:11.488773 DQ Delay:
7979 23:39:11.492094 DQ0 =134, DQ1 =136, DQ2 =134, DQ3 =130
7980 23:39:11.495806 DQ4 =132, DQ5 =124, DQ6 =140, DQ7 =138
7981 23:39:11.498982 DQ8 =116, DQ9 =118, DQ10 =130, DQ11 =120
7982 23:39:11.502242 DQ12 =130, DQ13 =134, DQ14 =138, DQ15 =134
7983 23:39:11.502810
7984 23:39:11.503183
7985 23:39:11.503599
7986 23:39:11.505011 [DramC_TX_OE_Calibration] TA2
7987 23:39:11.508823 Original DQ_B0 (3 6) =30, OEN = 27
7988 23:39:11.511649 Original DQ_B1 (3 6) =30, OEN = 27
7989 23:39:11.515612 24, 0x0, End_B0=24 End_B1=24
7990 23:39:11.516078 25, 0x0, End_B0=25 End_B1=25
7991 23:39:11.518299 26, 0x0, End_B0=26 End_B1=26
7992 23:39:11.522156 27, 0x0, End_B0=27 End_B1=27
7993 23:39:11.525430 28, 0x0, End_B0=28 End_B1=28
7994 23:39:11.526048 29, 0x0, End_B0=29 End_B1=29
7995 23:39:11.529201 30, 0x0, End_B0=30 End_B1=30
7996 23:39:11.531986 31, 0x4141, End_B0=30 End_B1=30
7997 23:39:11.535212 Byte0 end_step=30 best_step=27
7998 23:39:11.538798 Byte1 end_step=30 best_step=27
7999 23:39:11.541879 Byte0 TX OE(2T, 0.5T) = (3, 3)
8000 23:39:11.542454 Byte1 TX OE(2T, 0.5T) = (3, 3)
8001 23:39:11.542855
8002 23:39:11.545019
8003 23:39:11.552033 [DQSOSCAuto] RK0, (LSB)MR18= 0x241f, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 391 ps
8004 23:39:11.555330 CH0 RK0: MR19=303, MR18=241F
8005 23:39:11.561991 CH0_RK0: MR19=0x303, MR18=0x241F, DQSOSC=391, MR23=63, INC=24, DEC=16
8006 23:39:11.562543
8007 23:39:11.564919 ----->DramcWriteLeveling(PI) begin...
8008 23:39:11.565386 ==
8009 23:39:11.568176 Dram Type= 6, Freq= 0, CH_0, rank 1
8010 23:39:11.572092 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8011 23:39:11.572657 ==
8012 23:39:11.575530 Write leveling (Byte 0): 37 => 37
8013 23:39:11.578355 Write leveling (Byte 1): 26 => 26
8014 23:39:11.581738 DramcWriteLeveling(PI) end<-----
8015 23:39:11.582320
8016 23:39:11.582693 ==
8017 23:39:11.585215 Dram Type= 6, Freq= 0, CH_0, rank 1
8018 23:39:11.587847 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8019 23:39:11.588310 ==
8020 23:39:11.591240 [Gating] SW mode calibration
8021 23:39:11.598245 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8022 23:39:11.604939 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8023 23:39:11.608375 1 4 0 | B1->B0 | 2323 2424 | 0 1 | (0 0) (0 0)
8024 23:39:11.611402 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8025 23:39:11.618185 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8026 23:39:11.621003 1 4 12 | B1->B0 | 2323 2a29 | 0 1 | (0 0) (0 0)
8027 23:39:11.624762 1 4 16 | B1->B0 | 2e2e 3636 | 0 1 | (0 0) (1 1)
8028 23:39:11.631176 1 4 20 | B1->B0 | 3434 3a3a | 1 0 | (1 1) (0 0)
8029 23:39:11.634218 1 4 24 | B1->B0 | 3434 3c3b | 1 1 | (1 1) (0 0)
8030 23:39:11.638171 1 4 28 | B1->B0 | 3434 3939 | 1 0 | (1 1) (0 0)
8031 23:39:11.644537 1 5 0 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
8032 23:39:11.647853 1 5 4 | B1->B0 | 3434 3838 | 1 1 | (1 1) (1 1)
8033 23:39:11.651297 1 5 8 | B1->B0 | 3434 3a3a | 1 1 | (1 1) (1 1)
8034 23:39:11.658126 1 5 12 | B1->B0 | 3434 3838 | 1 0 | (1 1) (0 0)
8035 23:39:11.661742 1 5 16 | B1->B0 | 2c2c 2727 | 0 0 | (0 1) (1 0)
8036 23:39:11.664573 1 5 20 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
8037 23:39:11.671370 1 5 24 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8038 23:39:11.674397 1 5 28 | B1->B0 | 2323 2928 | 0 1 | (0 0) (1 1)
8039 23:39:11.677880 1 6 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 1)
8040 23:39:11.684375 1 6 4 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (1 1)
8041 23:39:11.687517 1 6 8 | B1->B0 | 2323 2726 | 0 1 | (0 0) (0 0)
8042 23:39:11.690811 1 6 12 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
8043 23:39:11.697678 1 6 16 | B1->B0 | 3737 4646 | 0 1 | (0 0) (0 0)
8044 23:39:11.700669 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8045 23:39:11.704594 1 6 24 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
8046 23:39:11.711216 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8047 23:39:11.714157 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8048 23:39:11.717353 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8049 23:39:11.724273 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8050 23:39:11.727625 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8051 23:39:11.730897 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8052 23:39:11.737815 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8053 23:39:11.740986 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8054 23:39:11.744318 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8055 23:39:11.750425 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8056 23:39:11.754022 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8057 23:39:11.756972 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8058 23:39:11.764187 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8059 23:39:11.766969 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8060 23:39:11.770967 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8061 23:39:11.774009 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8062 23:39:11.780126 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8063 23:39:11.783421 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8064 23:39:11.787300 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8065 23:39:11.793395 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8066 23:39:11.796806 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8067 23:39:11.800384 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8068 23:39:11.806953 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8069 23:39:11.810274 Total UI for P1: 0, mck2ui 16
8070 23:39:11.813785 best dqsien dly found for B0: ( 1, 9, 14)
8071 23:39:11.814205 Total UI for P1: 0, mck2ui 16
8072 23:39:11.820368 best dqsien dly found for B1: ( 1, 9, 14)
8073 23:39:11.823416 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8074 23:39:11.826834 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8075 23:39:11.827256
8076 23:39:11.830544 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8077 23:39:11.834111 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8078 23:39:11.837375 [Gating] SW calibration Done
8079 23:39:11.837956 ==
8080 23:39:11.840795 Dram Type= 6, Freq= 0, CH_0, rank 1
8081 23:39:11.844274 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8082 23:39:11.844793 ==
8083 23:39:11.846936 RX Vref Scan: 0
8084 23:39:11.847461
8085 23:39:11.847795 RX Vref 0 -> 0, step: 1
8086 23:39:11.850500
8087 23:39:11.850915 RX Delay 0 -> 252, step: 8
8088 23:39:11.853551 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8089 23:39:11.860375 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8090 23:39:11.863869 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8091 23:39:11.867099 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8092 23:39:11.870516 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8093 23:39:11.873731 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8094 23:39:11.880780 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
8095 23:39:11.884270 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8096 23:39:11.886845 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8097 23:39:11.890450 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8098 23:39:11.893265 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8099 23:39:11.900249 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8100 23:39:11.903173 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8101 23:39:11.906810 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8102 23:39:11.910005 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8103 23:39:11.916880 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8104 23:39:11.917401 ==
8105 23:39:11.920407 Dram Type= 6, Freq= 0, CH_0, rank 1
8106 23:39:11.923500 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8107 23:39:11.924025 ==
8108 23:39:11.924362 DQS Delay:
8109 23:39:11.926509 DQS0 = 0, DQS1 = 0
8110 23:39:11.926924 DQM Delay:
8111 23:39:11.929811 DQM0 = 136, DQM1 = 128
8112 23:39:11.930227 DQ Delay:
8113 23:39:11.932985 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
8114 23:39:11.936608 DQ4 =139, DQ5 =127, DQ6 =139, DQ7 =143
8115 23:39:11.939627 DQ8 =119, DQ9 =119, DQ10 =127, DQ11 =119
8116 23:39:11.943155 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8117 23:39:11.943675
8118 23:39:11.946356
8119 23:39:11.946771 ==
8120 23:39:11.949418 Dram Type= 6, Freq= 0, CH_0, rank 1
8121 23:39:11.953135 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8122 23:39:11.953551 ==
8123 23:39:11.953936
8124 23:39:11.954249
8125 23:39:11.955981 TX Vref Scan disable
8126 23:39:11.956397 == TX Byte 0 ==
8127 23:39:11.963016 Update DQ dly =994 (3 ,6, 34) DQ OEN =(3 ,3)
8128 23:39:11.966255 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8129 23:39:11.966778 == TX Byte 1 ==
8130 23:39:11.972817 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8131 23:39:11.975715 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8132 23:39:11.976187 ==
8133 23:39:11.979536 Dram Type= 6, Freq= 0, CH_0, rank 1
8134 23:39:11.982707 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8135 23:39:11.983227 ==
8136 23:39:11.999039
8137 23:39:12.002109 TX Vref early break, caculate TX vref
8138 23:39:12.005344 TX Vref=16, minBit 1, minWin=23, winSum=384
8139 23:39:12.008544 TX Vref=18, minBit 1, minWin=23, winSum=395
8140 23:39:12.012024 TX Vref=20, minBit 1, minWin=23, winSum=402
8141 23:39:12.015315 TX Vref=22, minBit 6, minWin=24, winSum=409
8142 23:39:12.018608 TX Vref=24, minBit 4, minWin=25, winSum=422
8143 23:39:12.025041 TX Vref=26, minBit 1, minWin=24, winSum=420
8144 23:39:12.028154 TX Vref=28, minBit 3, minWin=25, winSum=424
8145 23:39:12.032213 TX Vref=30, minBit 4, minWin=25, winSum=419
8146 23:39:12.035345 TX Vref=32, minBit 0, minWin=25, winSum=410
8147 23:39:12.038355 TX Vref=34, minBit 0, minWin=24, winSum=402
8148 23:39:12.042130 TX Vref=36, minBit 0, minWin=24, winSum=395
8149 23:39:12.047961 [TxChooseVref] Worse bit 3, Min win 25, Win sum 424, Final Vref 28
8150 23:39:12.048430
8151 23:39:12.051770 Final TX Range 0 Vref 28
8152 23:39:12.052339
8153 23:39:12.052711 ==
8154 23:39:12.055113 Dram Type= 6, Freq= 0, CH_0, rank 1
8155 23:39:12.058341 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8156 23:39:12.058819 ==
8157 23:39:12.061570
8158 23:39:12.062078
8159 23:39:12.062453 TX Vref Scan disable
8160 23:39:12.068426 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8161 23:39:12.069009 == TX Byte 0 ==
8162 23:39:12.071367 u2DelayCellOfst[0]=13 cells (4 PI)
8163 23:39:12.074966 u2DelayCellOfst[1]=16 cells (5 PI)
8164 23:39:12.078177 u2DelayCellOfst[2]=13 cells (4 PI)
8165 23:39:12.081906 u2DelayCellOfst[3]=13 cells (4 PI)
8166 23:39:12.084718 u2DelayCellOfst[4]=10 cells (3 PI)
8167 23:39:12.088015 u2DelayCellOfst[5]=0 cells (0 PI)
8168 23:39:12.091220 u2DelayCellOfst[6]=16 cells (5 PI)
8169 23:39:12.094602 u2DelayCellOfst[7]=16 cells (5 PI)
8170 23:39:12.098248 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8171 23:39:12.101395 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8172 23:39:12.105035 == TX Byte 1 ==
8173 23:39:12.107843 u2DelayCellOfst[8]=0 cells (0 PI)
8174 23:39:12.111099 u2DelayCellOfst[9]=0 cells (0 PI)
8175 23:39:12.114458 u2DelayCellOfst[10]=3 cells (1 PI)
8176 23:39:12.118166 u2DelayCellOfst[11]=3 cells (1 PI)
8177 23:39:12.121126 u2DelayCellOfst[12]=10 cells (3 PI)
8178 23:39:12.121617 u2DelayCellOfst[13]=6 cells (2 PI)
8179 23:39:12.124393 u2DelayCellOfst[14]=10 cells (3 PI)
8180 23:39:12.127991 u2DelayCellOfst[15]=6 cells (2 PI)
8181 23:39:12.134390 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8182 23:39:12.137565 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8183 23:39:12.138154 DramC Write-DBI on
8184 23:39:12.140887 ==
8185 23:39:12.144079 Dram Type= 6, Freq= 0, CH_0, rank 1
8186 23:39:12.147705 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8187 23:39:12.148184 ==
8188 23:39:12.148551
8189 23:39:12.148889
8190 23:39:12.151081 TX Vref Scan disable
8191 23:39:12.151539 == TX Byte 0 ==
8192 23:39:12.157660 Update DQM dly =738 (2 ,6, 34) DQM OEN =(3 ,3)
8193 23:39:12.158216 == TX Byte 1 ==
8194 23:39:12.160846 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8195 23:39:12.163903 DramC Write-DBI off
8196 23:39:12.164362
8197 23:39:12.164827 [DATLAT]
8198 23:39:12.167671 Freq=1600, CH0 RK1
8199 23:39:12.168235
8200 23:39:12.168603 DATLAT Default: 0xf
8201 23:39:12.171072 0, 0xFFFF, sum = 0
8202 23:39:12.171638 1, 0xFFFF, sum = 0
8203 23:39:12.174255 2, 0xFFFF, sum = 0
8204 23:39:12.174821 3, 0xFFFF, sum = 0
8205 23:39:12.177350 4, 0xFFFF, sum = 0
8206 23:39:12.177997 5, 0xFFFF, sum = 0
8207 23:39:12.180662 6, 0xFFFF, sum = 0
8208 23:39:12.181126 7, 0xFFFF, sum = 0
8209 23:39:12.184287 8, 0xFFFF, sum = 0
8210 23:39:12.187561 9, 0xFFFF, sum = 0
8211 23:39:12.188131 10, 0xFFFF, sum = 0
8212 23:39:12.190722 11, 0xFFFF, sum = 0
8213 23:39:12.191188 12, 0xFFFF, sum = 0
8214 23:39:12.194053 13, 0xFFFF, sum = 0
8215 23:39:12.194521 14, 0x0, sum = 1
8216 23:39:12.197502 15, 0x0, sum = 2
8217 23:39:12.198119 16, 0x0, sum = 3
8218 23:39:12.201476 17, 0x0, sum = 4
8219 23:39:12.202098 best_step = 15
8220 23:39:12.202471
8221 23:39:12.202813 ==
8222 23:39:12.203859 Dram Type= 6, Freq= 0, CH_0, rank 1
8223 23:39:12.207588 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8224 23:39:12.208150 ==
8225 23:39:12.210350 RX Vref Scan: 0
8226 23:39:12.210815
8227 23:39:12.213781 RX Vref 0 -> 0, step: 1
8228 23:39:12.214241
8229 23:39:12.214610 RX Delay 19 -> 252, step: 4
8230 23:39:12.221325 iDelay=191, Bit 0, Center 134 (83 ~ 186) 104
8231 23:39:12.224362 iDelay=191, Bit 1, Center 138 (91 ~ 186) 96
8232 23:39:12.227555 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8233 23:39:12.231320 iDelay=191, Bit 3, Center 132 (79 ~ 186) 108
8234 23:39:12.234796 iDelay=191, Bit 4, Center 136 (87 ~ 186) 100
8235 23:39:12.241133 iDelay=191, Bit 5, Center 126 (75 ~ 178) 104
8236 23:39:12.244750 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8237 23:39:12.247809 iDelay=191, Bit 7, Center 140 (91 ~ 190) 100
8238 23:39:12.251091 iDelay=191, Bit 8, Center 118 (67 ~ 170) 104
8239 23:39:12.254949 iDelay=191, Bit 9, Center 118 (67 ~ 170) 104
8240 23:39:12.261243 iDelay=191, Bit 10, Center 128 (75 ~ 182) 108
8241 23:39:12.264316 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8242 23:39:12.267825 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
8243 23:39:12.270722 iDelay=191, Bit 13, Center 134 (83 ~ 186) 104
8244 23:39:12.278016 iDelay=191, Bit 14, Center 134 (83 ~ 186) 104
8245 23:39:12.280874 iDelay=191, Bit 15, Center 136 (87 ~ 186) 100
8246 23:39:12.281339 ==
8247 23:39:12.284314 Dram Type= 6, Freq= 0, CH_0, rank 1
8248 23:39:12.288333 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8249 23:39:12.288916 ==
8250 23:39:12.289290 DQS Delay:
8251 23:39:12.290964 DQS0 = 0, DQS1 = 0
8252 23:39:12.291426 DQM Delay:
8253 23:39:12.294257 DQM0 = 134, DQM1 = 127
8254 23:39:12.294743 DQ Delay:
8255 23:39:12.298072 DQ0 =134, DQ1 =138, DQ2 =130, DQ3 =132
8256 23:39:12.300820 DQ4 =136, DQ5 =126, DQ6 =140, DQ7 =140
8257 23:39:12.303786 DQ8 =118, DQ9 =118, DQ10 =128, DQ11 =118
8258 23:39:12.307539 DQ12 =134, DQ13 =134, DQ14 =134, DQ15 =136
8259 23:39:12.310477
8260 23:39:12.310939
8261 23:39:12.311312
8262 23:39:12.311651 [DramC_TX_OE_Calibration] TA2
8263 23:39:12.314093 Original DQ_B0 (3 6) =30, OEN = 27
8264 23:39:12.317821 Original DQ_B1 (3 6) =30, OEN = 27
8265 23:39:12.321293 24, 0x0, End_B0=24 End_B1=24
8266 23:39:12.323870 25, 0x0, End_B0=25 End_B1=25
8267 23:39:12.327697 26, 0x0, End_B0=26 End_B1=26
8268 23:39:12.328273 27, 0x0, End_B0=27 End_B1=27
8269 23:39:12.330883 28, 0x0, End_B0=28 End_B1=28
8270 23:39:12.333762 29, 0x0, End_B0=29 End_B1=29
8271 23:39:12.337822 30, 0x0, End_B0=30 End_B1=30
8272 23:39:12.341057 31, 0x4141, End_B0=30 End_B1=30
8273 23:39:12.341696 Byte0 end_step=30 best_step=27
8274 23:39:12.344291 Byte1 end_step=30 best_step=27
8275 23:39:12.347512 Byte0 TX OE(2T, 0.5T) = (3, 3)
8276 23:39:12.350749 Byte1 TX OE(2T, 0.5T) = (3, 3)
8277 23:39:12.351322
8278 23:39:12.351842
8279 23:39:12.357327 [DQSOSCAuto] RK1, (LSB)MR18= 0x1e06, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 394 ps
8280 23:39:12.360733 CH0 RK1: MR19=303, MR18=1E06
8281 23:39:12.367961 CH0_RK1: MR19=0x303, MR18=0x1E06, DQSOSC=394, MR23=63, INC=23, DEC=15
8282 23:39:12.370469 [RxdqsGatingPostProcess] freq 1600
8283 23:39:12.377173 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8284 23:39:12.380584 best DQS0 dly(2T, 0.5T) = (1, 1)
8285 23:39:12.381186 best DQS1 dly(2T, 0.5T) = (1, 1)
8286 23:39:12.383771 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8287 23:39:12.387239 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8288 23:39:12.390553 best DQS0 dly(2T, 0.5T) = (1, 1)
8289 23:39:12.394182 best DQS1 dly(2T, 0.5T) = (1, 1)
8290 23:39:12.397631 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8291 23:39:12.400987 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8292 23:39:12.404078 Pre-setting of DQS Precalculation
8293 23:39:12.407267 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8294 23:39:12.410744 ==
8295 23:39:12.411211 Dram Type= 6, Freq= 0, CH_1, rank 0
8296 23:39:12.417691 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8297 23:39:12.418259 ==
8298 23:39:12.420100 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8299 23:39:12.427159 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8300 23:39:12.430401 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8301 23:39:12.436934 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8302 23:39:12.445437 [CA 0] Center 42 (12~72) winsize 61
8303 23:39:12.448746 [CA 1] Center 42 (12~72) winsize 61
8304 23:39:12.452067 [CA 2] Center 39 (10~68) winsize 59
8305 23:39:12.455559 [CA 3] Center 38 (9~67) winsize 59
8306 23:39:12.458545 [CA 4] Center 38 (9~68) winsize 60
8307 23:39:12.462387 [CA 5] Center 37 (8~67) winsize 60
8308 23:39:12.462951
8309 23:39:12.465805 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8310 23:39:12.466363
8311 23:39:12.468680 [CATrainingPosCal] consider 1 rank data
8312 23:39:12.471914 u2DelayCellTimex100 = 290/100 ps
8313 23:39:12.475020 CA0 delay=42 (12~72),Diff = 5 PI (16 cell)
8314 23:39:12.481737 CA1 delay=42 (12~72),Diff = 5 PI (16 cell)
8315 23:39:12.485165 CA2 delay=39 (10~68),Diff = 2 PI (6 cell)
8316 23:39:12.488627 CA3 delay=38 (9~67),Diff = 1 PI (3 cell)
8317 23:39:12.492199 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8318 23:39:12.494872 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8319 23:39:12.495333
8320 23:39:12.498915 CA PerBit enable=1, Macro0, CA PI delay=37
8321 23:39:12.499480
8322 23:39:12.501508 [CBTSetCACLKResult] CA Dly = 37
8323 23:39:12.505135 CS Dly: 10 (0~41)
8324 23:39:12.508335 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8325 23:39:12.511996 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8326 23:39:12.512695 ==
8327 23:39:12.515041 Dram Type= 6, Freq= 0, CH_1, rank 1
8328 23:39:12.518342 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8329 23:39:12.521621 ==
8330 23:39:12.524995 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8331 23:39:12.528506 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8332 23:39:12.534861 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8333 23:39:12.541897 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8334 23:39:12.548772 [CA 0] Center 42 (13~72) winsize 60
8335 23:39:12.552025 [CA 1] Center 42 (13~72) winsize 60
8336 23:39:12.555716 [CA 2] Center 39 (9~69) winsize 61
8337 23:39:12.559022 [CA 3] Center 38 (9~68) winsize 60
8338 23:39:12.562022 [CA 4] Center 39 (10~69) winsize 60
8339 23:39:12.565409 [CA 5] Center 38 (9~68) winsize 60
8340 23:39:12.566023
8341 23:39:12.568547 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8342 23:39:12.569008
8343 23:39:12.572123 [CATrainingPosCal] consider 2 rank data
8344 23:39:12.575488 u2DelayCellTimex100 = 290/100 ps
8345 23:39:12.579008 CA0 delay=42 (13~72),Diff = 4 PI (13 cell)
8346 23:39:12.585093 CA1 delay=42 (13~72),Diff = 4 PI (13 cell)
8347 23:39:12.588479 CA2 delay=39 (10~68),Diff = 1 PI (3 cell)
8348 23:39:12.591998 CA3 delay=38 (9~67),Diff = 0 PI (0 cell)
8349 23:39:12.594940 CA4 delay=39 (10~68),Diff = 1 PI (3 cell)
8350 23:39:12.598588 CA5 delay=38 (9~67),Diff = 0 PI (0 cell)
8351 23:39:12.599148
8352 23:39:12.601555 CA PerBit enable=1, Macro0, CA PI delay=38
8353 23:39:12.602176
8354 23:39:12.604736 [CBTSetCACLKResult] CA Dly = 38
8355 23:39:12.608245 CS Dly: 11 (0~44)
8356 23:39:12.611458 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8357 23:39:12.614793 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8358 23:39:12.615435
8359 23:39:12.618218 ----->DramcWriteLeveling(PI) begin...
8360 23:39:12.618680 ==
8361 23:39:12.621866 Dram Type= 6, Freq= 0, CH_1, rank 0
8362 23:39:12.628340 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8363 23:39:12.628799 ==
8364 23:39:12.631266 Write leveling (Byte 0): 26 => 26
8365 23:39:12.634444 Write leveling (Byte 1): 27 => 27
8366 23:39:12.634903 DramcWriteLeveling(PI) end<-----
8367 23:39:12.635266
8368 23:39:12.637892 ==
8369 23:39:12.641254 Dram Type= 6, Freq= 0, CH_1, rank 0
8370 23:39:12.644586 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8371 23:39:12.645103 ==
8372 23:39:12.648130 [Gating] SW mode calibration
8373 23:39:12.655119 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8374 23:39:12.657922 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8375 23:39:12.664852 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8376 23:39:12.667923 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8377 23:39:12.671105 1 4 8 | B1->B0 | 2323 3030 | 0 0 | (0 0) (1 1)
8378 23:39:12.677996 1 4 12 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
8379 23:39:12.681302 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8380 23:39:12.684945 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8381 23:39:12.691588 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8382 23:39:12.694287 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8383 23:39:12.698415 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8384 23:39:12.704583 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8385 23:39:12.708269 1 5 8 | B1->B0 | 3434 3232 | 1 1 | (1 0) (1 0)
8386 23:39:12.711284 1 5 12 | B1->B0 | 2424 2323 | 0 0 | (1 0) (1 0)
8387 23:39:12.717959 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8388 23:39:12.721204 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8389 23:39:12.724520 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8390 23:39:12.731276 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8391 23:39:12.734369 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8392 23:39:12.737546 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8393 23:39:12.744222 1 6 8 | B1->B0 | 2323 3636 | 0 0 | (0 0) (0 0)
8394 23:39:12.747301 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8395 23:39:12.750475 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8396 23:39:12.757461 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8397 23:39:12.760423 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8398 23:39:12.764203 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8399 23:39:12.770415 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8400 23:39:12.773678 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8401 23:39:12.777132 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8402 23:39:12.783659 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8403 23:39:12.787016 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8404 23:39:12.789968 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8405 23:39:12.796694 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8406 23:39:12.799893 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8407 23:39:12.803894 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8408 23:39:12.810828 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8409 23:39:12.813215 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8410 23:39:12.816546 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8411 23:39:12.820500 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8412 23:39:12.826755 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8413 23:39:12.830354 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8414 23:39:12.833463 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8415 23:39:12.840400 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8416 23:39:12.843914 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8417 23:39:12.846923 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8418 23:39:12.853421 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8419 23:39:12.857000 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8420 23:39:12.860080 Total UI for P1: 0, mck2ui 16
8421 23:39:12.863716 best dqsien dly found for B0: ( 1, 9, 12)
8422 23:39:12.866735 Total UI for P1: 0, mck2ui 16
8423 23:39:12.870070 best dqsien dly found for B1: ( 1, 9, 12)
8424 23:39:12.873448 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8425 23:39:12.876811 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8426 23:39:12.877385
8427 23:39:12.880155 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8428 23:39:12.883089 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8429 23:39:12.886605 [Gating] SW calibration Done
8430 23:39:12.887359 ==
8431 23:39:12.889739 Dram Type= 6, Freq= 0, CH_1, rank 0
8432 23:39:12.896253 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8433 23:39:12.896809 ==
8434 23:39:12.897262 RX Vref Scan: 0
8435 23:39:12.897650
8436 23:39:12.899925 RX Vref 0 -> 0, step: 1
8437 23:39:12.900484
8438 23:39:12.903327 RX Delay 0 -> 252, step: 8
8439 23:39:12.906319 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8440 23:39:12.909670 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8441 23:39:12.913152 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8442 23:39:12.916846 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8443 23:39:12.923192 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8444 23:39:12.926500 iDelay=200, Bit 5, Center 151 (104 ~ 199) 96
8445 23:39:12.929974 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8446 23:39:12.932974 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8447 23:39:12.936056 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
8448 23:39:12.943217 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8449 23:39:12.946209 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8450 23:39:12.949699 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8451 23:39:12.953350 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8452 23:39:12.956277 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8453 23:39:12.962761 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8454 23:39:12.966441 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8455 23:39:12.967005 ==
8456 23:39:12.969452 Dram Type= 6, Freq= 0, CH_1, rank 0
8457 23:39:12.972703 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8458 23:39:12.973270 ==
8459 23:39:12.976357 DQS Delay:
8460 23:39:12.976920 DQS0 = 0, DQS1 = 0
8461 23:39:12.977293 DQM Delay:
8462 23:39:12.979490 DQM0 = 137, DQM1 = 132
8463 23:39:12.980053 DQ Delay:
8464 23:39:12.982801 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8465 23:39:12.985835 DQ4 =131, DQ5 =151, DQ6 =147, DQ7 =135
8466 23:39:12.993100 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =127
8467 23:39:12.996119 DQ12 =139, DQ13 =143, DQ14 =139, DQ15 =139
8468 23:39:12.996612
8469 23:39:12.996990
8470 23:39:12.997335 ==
8471 23:39:12.999247 Dram Type= 6, Freq= 0, CH_1, rank 0
8472 23:39:13.003242 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8473 23:39:13.003813 ==
8474 23:39:13.004189
8475 23:39:13.004532
8476 23:39:13.006075 TX Vref Scan disable
8477 23:39:13.006543 == TX Byte 0 ==
8478 23:39:13.012516 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8479 23:39:13.015873 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8480 23:39:13.016443 == TX Byte 1 ==
8481 23:39:13.022686 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8482 23:39:13.025951 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8483 23:39:13.026422 ==
8484 23:39:13.029024 Dram Type= 6, Freq= 0, CH_1, rank 0
8485 23:39:13.032566 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8486 23:39:13.033138 ==
8487 23:39:13.046321
8488 23:39:13.049409 TX Vref early break, caculate TX vref
8489 23:39:13.052694 TX Vref=16, minBit 1, minWin=23, winSum=381
8490 23:39:13.055934 TX Vref=18, minBit 0, minWin=23, winSum=387
8491 23:39:13.059562 TX Vref=20, minBit 5, minWin=23, winSum=396
8492 23:39:13.062701 TX Vref=22, minBit 0, minWin=24, winSum=407
8493 23:39:13.066259 TX Vref=24, minBit 0, minWin=25, winSum=415
8494 23:39:13.072985 TX Vref=26, minBit 1, minWin=26, winSum=429
8495 23:39:13.076285 TX Vref=28, minBit 0, minWin=25, winSum=427
8496 23:39:13.079243 TX Vref=30, minBit 0, minWin=25, winSum=421
8497 23:39:13.082841 TX Vref=32, minBit 0, minWin=24, winSum=412
8498 23:39:13.086000 TX Vref=34, minBit 0, minWin=24, winSum=404
8499 23:39:13.092948 [TxChooseVref] Worse bit 1, Min win 26, Win sum 429, Final Vref 26
8500 23:39:13.093510
8501 23:39:13.095864 Final TX Range 0 Vref 26
8502 23:39:13.096343
8503 23:39:13.096750 ==
8504 23:39:13.099545 Dram Type= 6, Freq= 0, CH_1, rank 0
8505 23:39:13.102383 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8506 23:39:13.102850 ==
8507 23:39:13.103274
8508 23:39:13.103624
8509 23:39:13.105825 TX Vref Scan disable
8510 23:39:13.112774 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8511 23:39:13.113338 == TX Byte 0 ==
8512 23:39:13.115410 u2DelayCellOfst[0]=16 cells (5 PI)
8513 23:39:13.118961 u2DelayCellOfst[1]=10 cells (3 PI)
8514 23:39:13.122251 u2DelayCellOfst[2]=0 cells (0 PI)
8515 23:39:13.125786 u2DelayCellOfst[3]=6 cells (2 PI)
8516 23:39:13.129214 u2DelayCellOfst[4]=6 cells (2 PI)
8517 23:39:13.132245 u2DelayCellOfst[5]=16 cells (5 PI)
8518 23:39:13.135278 u2DelayCellOfst[6]=16 cells (5 PI)
8519 23:39:13.135745 u2DelayCellOfst[7]=3 cells (1 PI)
8520 23:39:13.142311 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8521 23:39:13.145266 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8522 23:39:13.148962 == TX Byte 1 ==
8523 23:39:13.149527 u2DelayCellOfst[8]=0 cells (0 PI)
8524 23:39:13.151648 u2DelayCellOfst[9]=3 cells (1 PI)
8525 23:39:13.155022 u2DelayCellOfst[10]=13 cells (4 PI)
8526 23:39:13.158828 u2DelayCellOfst[11]=6 cells (2 PI)
8527 23:39:13.161994 u2DelayCellOfst[12]=13 cells (4 PI)
8528 23:39:13.165401 u2DelayCellOfst[13]=16 cells (5 PI)
8529 23:39:13.168897 u2DelayCellOfst[14]=16 cells (5 PI)
8530 23:39:13.172270 u2DelayCellOfst[15]=16 cells (5 PI)
8531 23:39:13.175181 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8532 23:39:13.182078 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8533 23:39:13.182646 DramC Write-DBI on
8534 23:39:13.183018 ==
8535 23:39:13.185129 Dram Type= 6, Freq= 0, CH_1, rank 0
8536 23:39:13.191265 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8537 23:39:13.191733 ==
8538 23:39:13.192102
8539 23:39:13.192442
8540 23:39:13.192771 TX Vref Scan disable
8541 23:39:13.195311 == TX Byte 0 ==
8542 23:39:13.199086 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8543 23:39:13.202002 == TX Byte 1 ==
8544 23:39:13.205714 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8545 23:39:13.208398 DramC Write-DBI off
8546 23:39:13.209032
8547 23:39:13.209477 [DATLAT]
8548 23:39:13.209891 Freq=1600, CH1 RK0
8549 23:39:13.210238
8550 23:39:13.212234 DATLAT Default: 0xf
8551 23:39:13.212799 0, 0xFFFF, sum = 0
8552 23:39:13.215127 1, 0xFFFF, sum = 0
8553 23:39:13.215597 2, 0xFFFF, sum = 0
8554 23:39:13.218987 3, 0xFFFF, sum = 0
8555 23:39:13.221742 4, 0xFFFF, sum = 0
8556 23:39:13.222220 5, 0xFFFF, sum = 0
8557 23:39:13.225353 6, 0xFFFF, sum = 0
8558 23:39:13.225977 7, 0xFFFF, sum = 0
8559 23:39:13.228764 8, 0xFFFF, sum = 0
8560 23:39:13.229233 9, 0xFFFF, sum = 0
8561 23:39:13.231874 10, 0xFFFF, sum = 0
8562 23:39:13.232445 11, 0xFFFF, sum = 0
8563 23:39:13.235427 12, 0xFFFF, sum = 0
8564 23:39:13.236015 13, 0xFFFF, sum = 0
8565 23:39:13.238342 14, 0x0, sum = 1
8566 23:39:13.238815 15, 0x0, sum = 2
8567 23:39:13.242027 16, 0x0, sum = 3
8568 23:39:13.242593 17, 0x0, sum = 4
8569 23:39:13.245343 best_step = 15
8570 23:39:13.245969
8571 23:39:13.246346 ==
8572 23:39:13.248502 Dram Type= 6, Freq= 0, CH_1, rank 0
8573 23:39:13.251815 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8574 23:39:13.252383 ==
8575 23:39:13.252758 RX Vref Scan: 1
8576 23:39:13.254694
8577 23:39:13.255158 Set Vref Range= 24 -> 127
8578 23:39:13.255526
8579 23:39:13.258311 RX Vref 24 -> 127, step: 1
8580 23:39:13.258770
8581 23:39:13.261740 RX Delay 27 -> 252, step: 4
8582 23:39:13.262302
8583 23:39:13.265074 Set Vref, RX VrefLevel [Byte0]: 24
8584 23:39:13.268306 [Byte1]: 24
8585 23:39:13.268769
8586 23:39:13.271393 Set Vref, RX VrefLevel [Byte0]: 25
8587 23:39:13.274936 [Byte1]: 25
8588 23:39:13.275543
8589 23:39:13.278495 Set Vref, RX VrefLevel [Byte0]: 26
8590 23:39:13.281756 [Byte1]: 26
8591 23:39:13.285902
8592 23:39:13.286484 Set Vref, RX VrefLevel [Byte0]: 27
8593 23:39:13.288845 [Byte1]: 27
8594 23:39:13.292782
8595 23:39:13.293339 Set Vref, RX VrefLevel [Byte0]: 28
8596 23:39:13.296123 [Byte1]: 28
8597 23:39:13.300694
8598 23:39:13.301252 Set Vref, RX VrefLevel [Byte0]: 29
8599 23:39:13.303778 [Byte1]: 29
8600 23:39:13.308011
8601 23:39:13.308586 Set Vref, RX VrefLevel [Byte0]: 30
8602 23:39:13.311557 [Byte1]: 30
8603 23:39:13.315615
8604 23:39:13.316179 Set Vref, RX VrefLevel [Byte0]: 31
8605 23:39:13.318552 [Byte1]: 31
8606 23:39:13.323103
8607 23:39:13.323629 Set Vref, RX VrefLevel [Byte0]: 32
8608 23:39:13.326532 [Byte1]: 32
8609 23:39:13.330377
8610 23:39:13.330838 Set Vref, RX VrefLevel [Byte0]: 33
8611 23:39:13.333648 [Byte1]: 33
8612 23:39:13.337880
8613 23:39:13.338341 Set Vref, RX VrefLevel [Byte0]: 34
8614 23:39:13.341643 [Byte1]: 34
8615 23:39:13.346328
8616 23:39:13.346890 Set Vref, RX VrefLevel [Byte0]: 35
8617 23:39:13.348969 [Byte1]: 35
8618 23:39:13.352804
8619 23:39:13.353266 Set Vref, RX VrefLevel [Byte0]: 36
8620 23:39:13.357047 [Byte1]: 36
8621 23:39:13.360749
8622 23:39:13.361313 Set Vref, RX VrefLevel [Byte0]: 37
8623 23:39:13.364271 [Byte1]: 37
8624 23:39:13.367897
8625 23:39:13.368358 Set Vref, RX VrefLevel [Byte0]: 38
8626 23:39:13.371484 [Byte1]: 38
8627 23:39:13.376179
8628 23:39:13.376750 Set Vref, RX VrefLevel [Byte0]: 39
8629 23:39:13.378715 [Byte1]: 39
8630 23:39:13.383241
8631 23:39:13.383804 Set Vref, RX VrefLevel [Byte0]: 40
8632 23:39:13.386682 [Byte1]: 40
8633 23:39:13.390775
8634 23:39:13.391335 Set Vref, RX VrefLevel [Byte0]: 41
8635 23:39:13.394078 [Byte1]: 41
8636 23:39:13.398322
8637 23:39:13.398783 Set Vref, RX VrefLevel [Byte0]: 42
8638 23:39:13.401708 [Byte1]: 42
8639 23:39:13.405968
8640 23:39:13.406514 Set Vref, RX VrefLevel [Byte0]: 43
8641 23:39:13.409323 [Byte1]: 43
8642 23:39:13.413662
8643 23:39:13.414234 Set Vref, RX VrefLevel [Byte0]: 44
8644 23:39:13.416988 [Byte1]: 44
8645 23:39:13.420905
8646 23:39:13.421469 Set Vref, RX VrefLevel [Byte0]: 45
8647 23:39:13.424497 [Byte1]: 45
8648 23:39:13.428473
8649 23:39:13.429034 Set Vref, RX VrefLevel [Byte0]: 46
8650 23:39:13.431471 [Byte1]: 46
8651 23:39:13.436321
8652 23:39:13.436876 Set Vref, RX VrefLevel [Byte0]: 47
8653 23:39:13.439130 [Byte1]: 47
8654 23:39:13.443478
8655 23:39:13.444109 Set Vref, RX VrefLevel [Byte0]: 48
8656 23:39:13.447114 [Byte1]: 48
8657 23:39:13.451240
8658 23:39:13.451699 Set Vref, RX VrefLevel [Byte0]: 49
8659 23:39:13.454273 [Byte1]: 49
8660 23:39:13.459028
8661 23:39:13.459586 Set Vref, RX VrefLevel [Byte0]: 50
8662 23:39:13.461951 [Byte1]: 50
8663 23:39:13.466593
8664 23:39:13.467154 Set Vref, RX VrefLevel [Byte0]: 51
8665 23:39:13.469833 [Byte1]: 51
8666 23:39:13.473968
8667 23:39:13.474526 Set Vref, RX VrefLevel [Byte0]: 52
8668 23:39:13.476968 [Byte1]: 52
8669 23:39:13.481216
8670 23:39:13.481719 Set Vref, RX VrefLevel [Byte0]: 53
8671 23:39:13.484274 [Byte1]: 53
8672 23:39:13.489288
8673 23:39:13.489885 Set Vref, RX VrefLevel [Byte0]: 54
8674 23:39:13.492000 [Byte1]: 54
8675 23:39:13.496234
8676 23:39:13.496751 Set Vref, RX VrefLevel [Byte0]: 55
8677 23:39:13.499842 [Byte1]: 55
8678 23:39:13.503717
8679 23:39:13.504185 Set Vref, RX VrefLevel [Byte0]: 56
8680 23:39:13.507419 [Byte1]: 56
8681 23:39:13.511696
8682 23:39:13.512164 Set Vref, RX VrefLevel [Byte0]: 57
8683 23:39:13.514266 [Byte1]: 57
8684 23:39:13.518565
8685 23:39:13.519031 Set Vref, RX VrefLevel [Byte0]: 58
8686 23:39:13.522387 [Byte1]: 58
8687 23:39:13.527416
8688 23:39:13.528163 Set Vref, RX VrefLevel [Byte0]: 59
8689 23:39:13.530134 [Byte1]: 59
8690 23:39:13.533763
8691 23:39:13.534230 Set Vref, RX VrefLevel [Byte0]: 60
8692 23:39:13.536968 [Byte1]: 60
8693 23:39:13.541834
8694 23:39:13.542409 Set Vref, RX VrefLevel [Byte0]: 61
8695 23:39:13.545052 [Byte1]: 61
8696 23:39:13.548954
8697 23:39:13.549523 Set Vref, RX VrefLevel [Byte0]: 62
8698 23:39:13.552312 [Byte1]: 62
8699 23:39:13.556836
8700 23:39:13.557407 Set Vref, RX VrefLevel [Byte0]: 63
8701 23:39:13.559863 [Byte1]: 63
8702 23:39:13.564018
8703 23:39:13.564598 Set Vref, RX VrefLevel [Byte0]: 64
8704 23:39:13.567259 [Byte1]: 64
8705 23:39:13.571341
8706 23:39:13.571809 Set Vref, RX VrefLevel [Byte0]: 65
8707 23:39:13.574883 [Byte1]: 65
8708 23:39:13.579312
8709 23:39:13.579871 Set Vref, RX VrefLevel [Byte0]: 66
8710 23:39:13.582547 [Byte1]: 66
8711 23:39:13.587038
8712 23:39:13.587617 Set Vref, RX VrefLevel [Byte0]: 67
8713 23:39:13.589820 [Byte1]: 67
8714 23:39:13.594613
8715 23:39:13.595175 Set Vref, RX VrefLevel [Byte0]: 68
8716 23:39:13.597644 [Byte1]: 68
8717 23:39:13.602071
8718 23:39:13.602663 Set Vref, RX VrefLevel [Byte0]: 69
8719 23:39:13.605757 [Byte1]: 69
8720 23:39:13.609618
8721 23:39:13.610196 Set Vref, RX VrefLevel [Byte0]: 70
8722 23:39:13.612170 [Byte1]: 70
8723 23:39:13.616999
8724 23:39:13.617568 Set Vref, RX VrefLevel [Byte0]: 71
8725 23:39:13.620471 [Byte1]: 71
8726 23:39:13.624571
8727 23:39:13.625134 Set Vref, RX VrefLevel [Byte0]: 72
8728 23:39:13.627633 [Byte1]: 72
8729 23:39:13.632247
8730 23:39:13.632713 Set Vref, RX VrefLevel [Byte0]: 73
8731 23:39:13.635155 [Byte1]: 73
8732 23:39:13.639571
8733 23:39:13.640038 Set Vref, RX VrefLevel [Byte0]: 74
8734 23:39:13.643309 [Byte1]: 74
8735 23:39:13.647389
8736 23:39:13.647953 Set Vref, RX VrefLevel [Byte0]: 75
8737 23:39:13.650650 [Byte1]: 75
8738 23:39:13.654631
8739 23:39:13.655192 Final RX Vref Byte 0 = 58 to rank0
8740 23:39:13.658004 Final RX Vref Byte 1 = 56 to rank0
8741 23:39:13.661337 Final RX Vref Byte 0 = 58 to rank1
8742 23:39:13.664305 Final RX Vref Byte 1 = 56 to rank1==
8743 23:39:13.668044 Dram Type= 6, Freq= 0, CH_1, rank 0
8744 23:39:13.674310 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8745 23:39:13.675003 ==
8746 23:39:13.675395 DQS Delay:
8747 23:39:13.675743 DQS0 = 0, DQS1 = 0
8748 23:39:13.678457 DQM Delay:
8749 23:39:13.679034 DQM0 = 134, DQM1 = 131
8750 23:39:13.681685 DQ Delay:
8751 23:39:13.684252 DQ0 =140, DQ1 =128, DQ2 =124, DQ3 =130
8752 23:39:13.687760 DQ4 =134, DQ5 =144, DQ6 =142, DQ7 =132
8753 23:39:13.691060 DQ8 =116, DQ9 =122, DQ10 =132, DQ11 =124
8754 23:39:13.694520 DQ12 =140, DQ13 =140, DQ14 =140, DQ15 =140
8755 23:39:13.695084
8756 23:39:13.695463
8757 23:39:13.695807
8758 23:39:13.697438 [DramC_TX_OE_Calibration] TA2
8759 23:39:13.701447 Original DQ_B0 (3 6) =30, OEN = 27
8760 23:39:13.704620 Original DQ_B1 (3 6) =30, OEN = 27
8761 23:39:13.707516 24, 0x0, End_B0=24 End_B1=24
8762 23:39:13.708084 25, 0x0, End_B0=25 End_B1=25
8763 23:39:13.711056 26, 0x0, End_B0=26 End_B1=26
8764 23:39:13.713908 27, 0x0, End_B0=27 End_B1=27
8765 23:39:13.717455 28, 0x0, End_B0=28 End_B1=28
8766 23:39:13.720921 29, 0x0, End_B0=29 End_B1=29
8767 23:39:13.721397 30, 0x0, End_B0=30 End_B1=30
8768 23:39:13.723984 31, 0x4141, End_B0=30 End_B1=30
8769 23:39:13.727527 Byte0 end_step=30 best_step=27
8770 23:39:13.730525 Byte1 end_step=30 best_step=27
8771 23:39:13.733797 Byte0 TX OE(2T, 0.5T) = (3, 3)
8772 23:39:13.737814 Byte1 TX OE(2T, 0.5T) = (3, 3)
8773 23:39:13.738388
8774 23:39:13.738765
8775 23:39:13.744249 [DQSOSCAuto] RK0, (LSB)MR18= 0x1321, (MSB)MR19= 0x303, tDQSOscB0 = 393 ps tDQSOscB1 = 400 ps
8776 23:39:13.747853 CH1 RK0: MR19=303, MR18=1321
8777 23:39:13.754006 CH1_RK0: MR19=0x303, MR18=0x1321, DQSOSC=393, MR23=63, INC=23, DEC=15
8778 23:39:13.754570
8779 23:39:13.757111 ----->DramcWriteLeveling(PI) begin...
8780 23:39:13.757618 ==
8781 23:39:13.760590 Dram Type= 6, Freq= 0, CH_1, rank 1
8782 23:39:13.764199 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8783 23:39:13.764771 ==
8784 23:39:13.767377 Write leveling (Byte 0): 28 => 28
8785 23:39:13.770730 Write leveling (Byte 1): 30 => 30
8786 23:39:13.773873 DramcWriteLeveling(PI) end<-----
8787 23:39:13.774447
8788 23:39:13.774818 ==
8789 23:39:13.777470 Dram Type= 6, Freq= 0, CH_1, rank 1
8790 23:39:13.780899 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8791 23:39:13.781473 ==
8792 23:39:13.783607 [Gating] SW mode calibration
8793 23:39:13.790328 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8794 23:39:13.796873 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8795 23:39:13.800523 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8796 23:39:13.807400 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8797 23:39:13.810680 1 4 8 | B1->B0 | 2524 2323 | 1 0 | (0 0) (0 0)
8798 23:39:13.813570 1 4 12 | B1->B0 | 3434 3232 | 1 0 | (1 1) (1 1)
8799 23:39:13.820079 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8800 23:39:13.823922 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8801 23:39:13.827279 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8802 23:39:13.833110 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8803 23:39:13.836611 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8804 23:39:13.839980 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8805 23:39:13.843529 1 5 8 | B1->B0 | 3232 3434 | 1 1 | (1 0) (1 1)
8806 23:39:13.849692 1 5 12 | B1->B0 | 2424 2d2d | 0 0 | (0 0) (0 0)
8807 23:39:13.853437 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8808 23:39:13.856725 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8809 23:39:13.863141 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8810 23:39:13.866673 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8811 23:39:13.870121 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8812 23:39:13.875979 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8813 23:39:13.879616 1 6 8 | B1->B0 | 3434 2424 | 0 0 | (0 0) (0 0)
8814 23:39:13.883068 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8815 23:39:13.889873 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8816 23:39:13.893181 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8817 23:39:13.896199 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8818 23:39:13.903181 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8819 23:39:13.906624 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8820 23:39:13.909884 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8821 23:39:13.916624 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8822 23:39:13.919773 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8823 23:39:13.923019 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8824 23:39:13.930065 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8825 23:39:13.932937 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8826 23:39:13.936263 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8827 23:39:13.943389 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8828 23:39:13.946692 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8829 23:39:13.949538 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8830 23:39:13.956461 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8831 23:39:13.959708 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8832 23:39:13.962836 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8833 23:39:13.966509 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8834 23:39:13.973340 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8835 23:39:13.976334 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8836 23:39:13.979708 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8837 23:39:13.986191 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8838 23:39:13.989334 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8839 23:39:13.992884 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8840 23:39:13.996486 Total UI for P1: 0, mck2ui 16
8841 23:39:13.999724 best dqsien dly found for B0: ( 1, 9, 12)
8842 23:39:14.002897 Total UI for P1: 0, mck2ui 16
8843 23:39:14.006523 best dqsien dly found for B1: ( 1, 9, 8)
8844 23:39:14.009433 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8845 23:39:14.012899 best DQS1 dly(MCK, UI, PI) = (1, 9, 8)
8846 23:39:14.013434
8847 23:39:14.019501 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8848 23:39:14.023040 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 8)
8849 23:39:14.026088 [Gating] SW calibration Done
8850 23:39:14.026552 ==
8851 23:39:14.030087 Dram Type= 6, Freq= 0, CH_1, rank 1
8852 23:39:14.032855 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8853 23:39:14.033441 ==
8854 23:39:14.034044 RX Vref Scan: 0
8855 23:39:14.034529
8856 23:39:14.036753 RX Vref 0 -> 0, step: 1
8857 23:39:14.037313
8858 23:39:14.039469 RX Delay 0 -> 252, step: 8
8859 23:39:14.042493 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8860 23:39:14.046327 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8861 23:39:14.049801 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8862 23:39:14.056154 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8863 23:39:14.059639 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8864 23:39:14.062813 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8865 23:39:14.065914 iDelay=208, Bit 6, Center 147 (96 ~ 199) 104
8866 23:39:14.069687 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8867 23:39:14.076096 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8868 23:39:14.079481 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8869 23:39:14.082272 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8870 23:39:14.085783 iDelay=208, Bit 11, Center 127 (72 ~ 183) 112
8871 23:39:14.092508 iDelay=208, Bit 12, Center 143 (88 ~ 199) 112
8872 23:39:14.095575 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8873 23:39:14.098767 iDelay=208, Bit 14, Center 139 (88 ~ 191) 104
8874 23:39:14.102639 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8875 23:39:14.103101 ==
8876 23:39:14.105735 Dram Type= 6, Freq= 0, CH_1, rank 1
8877 23:39:14.108988 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8878 23:39:14.112382 ==
8879 23:39:14.112845 DQS Delay:
8880 23:39:14.113210 DQS0 = 0, DQS1 = 0
8881 23:39:14.116031 DQM Delay:
8882 23:39:14.116590 DQM0 = 136, DQM1 = 133
8883 23:39:14.119252 DQ Delay:
8884 23:39:14.122205 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =131
8885 23:39:14.125489 DQ4 =131, DQ5 =151, DQ6 =147, DQ7 =135
8886 23:39:14.129175 DQ8 =119, DQ9 =119, DQ10 =135, DQ11 =127
8887 23:39:14.132483 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8888 23:39:14.133045
8889 23:39:14.133416
8890 23:39:14.133835 ==
8891 23:39:14.135999 Dram Type= 6, Freq= 0, CH_1, rank 1
8892 23:39:14.139433 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8893 23:39:14.139903 ==
8894 23:39:14.142315
8895 23:39:14.142775
8896 23:39:14.143142 TX Vref Scan disable
8897 23:39:14.145399 == TX Byte 0 ==
8898 23:39:14.148886 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
8899 23:39:14.152392 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8900 23:39:14.155630 == TX Byte 1 ==
8901 23:39:14.158824 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8902 23:39:14.162135 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8903 23:39:14.162604 ==
8904 23:39:14.165924 Dram Type= 6, Freq= 0, CH_1, rank 1
8905 23:39:14.172472 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8906 23:39:14.173040 ==
8907 23:39:14.183557
8908 23:39:14.186921 TX Vref early break, caculate TX vref
8909 23:39:14.190568 TX Vref=16, minBit 2, minWin=22, winSum=383
8910 23:39:14.193613 TX Vref=18, minBit 1, minWin=23, winSum=391
8911 23:39:14.197354 TX Vref=20, minBit 4, minWin=24, winSum=400
8912 23:39:14.200359 TX Vref=22, minBit 0, minWin=25, winSum=411
8913 23:39:14.203854 TX Vref=24, minBit 2, minWin=24, winSum=417
8914 23:39:14.210668 TX Vref=26, minBit 0, minWin=26, winSum=422
8915 23:39:14.213565 TX Vref=28, minBit 0, minWin=26, winSum=428
8916 23:39:14.217162 TX Vref=30, minBit 1, minWin=25, winSum=421
8917 23:39:14.220566 TX Vref=32, minBit 1, minWin=25, winSum=408
8918 23:39:14.224064 TX Vref=34, minBit 6, minWin=24, winSum=404
8919 23:39:14.230196 [TxChooseVref] Worse bit 0, Min win 26, Win sum 428, Final Vref 28
8920 23:39:14.230761
8921 23:39:14.233426 Final TX Range 0 Vref 28
8922 23:39:14.233996
8923 23:39:14.234378 ==
8924 23:39:14.236681 Dram Type= 6, Freq= 0, CH_1, rank 1
8925 23:39:14.240015 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8926 23:39:14.240543 ==
8927 23:39:14.240920
8928 23:39:14.241264
8929 23:39:14.243509 TX Vref Scan disable
8930 23:39:14.250089 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8931 23:39:14.250653 == TX Byte 0 ==
8932 23:39:14.253301 u2DelayCellOfst[0]=16 cells (5 PI)
8933 23:39:14.256779 u2DelayCellOfst[1]=10 cells (3 PI)
8934 23:39:14.260685 u2DelayCellOfst[2]=0 cells (0 PI)
8935 23:39:14.263949 u2DelayCellOfst[3]=6 cells (2 PI)
8936 23:39:14.267260 u2DelayCellOfst[4]=6 cells (2 PI)
8937 23:39:14.270202 u2DelayCellOfst[5]=16 cells (5 PI)
8938 23:39:14.273710 u2DelayCellOfst[6]=16 cells (5 PI)
8939 23:39:14.274176 u2DelayCellOfst[7]=6 cells (2 PI)
8940 23:39:14.280271 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8941 23:39:14.283943 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8942 23:39:14.284514 == TX Byte 1 ==
8943 23:39:14.286531 u2DelayCellOfst[8]=0 cells (0 PI)
8944 23:39:14.290292 u2DelayCellOfst[9]=3 cells (1 PI)
8945 23:39:14.293956 u2DelayCellOfst[10]=10 cells (3 PI)
8946 23:39:14.296526 u2DelayCellOfst[11]=3 cells (1 PI)
8947 23:39:14.300004 u2DelayCellOfst[12]=16 cells (5 PI)
8948 23:39:14.303476 u2DelayCellOfst[13]=16 cells (5 PI)
8949 23:39:14.307008 u2DelayCellOfst[14]=16 cells (5 PI)
8950 23:39:14.310949 u2DelayCellOfst[15]=16 cells (5 PI)
8951 23:39:14.313478 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8952 23:39:14.316622 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8953 23:39:14.319832 DramC Write-DBI on
8954 23:39:14.320344 ==
8955 23:39:14.323632 Dram Type= 6, Freq= 0, CH_1, rank 1
8956 23:39:14.326393 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8957 23:39:14.326861 ==
8958 23:39:14.327228
8959 23:39:14.330368
8960 23:39:14.330932 TX Vref Scan disable
8961 23:39:14.333011 == TX Byte 0 ==
8962 23:39:14.336756 Update DQM dly =727 (2 ,6, 23) DQM OEN =(3 ,3)
8963 23:39:14.339961 == TX Byte 1 ==
8964 23:39:14.343156 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8965 23:39:14.343670 DramC Write-DBI off
8966 23:39:14.344039
8967 23:39:14.346319 [DATLAT]
8968 23:39:14.346851 Freq=1600, CH1 RK1
8969 23:39:14.347225
8970 23:39:14.350482 DATLAT Default: 0xf
8971 23:39:14.351063 0, 0xFFFF, sum = 0
8972 23:39:14.352969 1, 0xFFFF, sum = 0
8973 23:39:14.353438 2, 0xFFFF, sum = 0
8974 23:39:14.356436 3, 0xFFFF, sum = 0
8975 23:39:14.357205 4, 0xFFFF, sum = 0
8976 23:39:14.360250 5, 0xFFFF, sum = 0
8977 23:39:14.360820 6, 0xFFFF, sum = 0
8978 23:39:14.363532 7, 0xFFFF, sum = 0
8979 23:39:14.366509 8, 0xFFFF, sum = 0
8980 23:39:14.366979 9, 0xFFFF, sum = 0
8981 23:39:14.369700 10, 0xFFFF, sum = 0
8982 23:39:14.370268 11, 0xFFFF, sum = 0
8983 23:39:14.373187 12, 0xFFFF, sum = 0
8984 23:39:14.373704 13, 0xFFFF, sum = 0
8985 23:39:14.376338 14, 0x0, sum = 1
8986 23:39:14.376894 15, 0x0, sum = 2
8987 23:39:14.380123 16, 0x0, sum = 3
8988 23:39:14.380693 17, 0x0, sum = 4
8989 23:39:14.383200 best_step = 15
8990 23:39:14.383758
8991 23:39:14.384126 ==
8992 23:39:14.386405 Dram Type= 6, Freq= 0, CH_1, rank 1
8993 23:39:14.389904 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8994 23:39:14.390473 ==
8995 23:39:14.390853 RX Vref Scan: 0
8996 23:39:14.391304
8997 23:39:14.392889 RX Vref 0 -> 0, step: 1
8998 23:39:14.393350
8999 23:39:14.396495 RX Delay 19 -> 252, step: 4
9000 23:39:14.400176 iDelay=195, Bit 0, Center 138 (91 ~ 186) 96
9001 23:39:14.403252 iDelay=195, Bit 1, Center 128 (79 ~ 178) 100
9002 23:39:14.409751 iDelay=195, Bit 2, Center 122 (71 ~ 174) 104
9003 23:39:14.413492 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
9004 23:39:14.416454 iDelay=195, Bit 4, Center 130 (83 ~ 178) 96
9005 23:39:14.419847 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
9006 23:39:14.422794 iDelay=195, Bit 6, Center 144 (95 ~ 194) 100
9007 23:39:14.429340 iDelay=195, Bit 7, Center 132 (79 ~ 186) 108
9008 23:39:14.432640 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
9009 23:39:14.436131 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
9010 23:39:14.439071 iDelay=195, Bit 10, Center 132 (83 ~ 182) 100
9011 23:39:14.443085 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
9012 23:39:14.449410 iDelay=195, Bit 12, Center 140 (87 ~ 194) 108
9013 23:39:14.452815 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
9014 23:39:14.456030 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
9015 23:39:14.459335 iDelay=195, Bit 15, Center 142 (91 ~ 194) 104
9016 23:39:14.459801 ==
9017 23:39:14.462197 Dram Type= 6, Freq= 0, CH_1, rank 1
9018 23:39:14.469021 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9019 23:39:14.469632 ==
9020 23:39:14.470018 DQS Delay:
9021 23:39:14.472551 DQS0 = 0, DQS1 = 0
9022 23:39:14.473113 DQM Delay:
9023 23:39:14.475283 DQM0 = 133, DQM1 = 130
9024 23:39:14.475746 DQ Delay:
9025 23:39:14.478778 DQ0 =138, DQ1 =128, DQ2 =122, DQ3 =130
9026 23:39:14.482294 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =132
9027 23:39:14.485277 DQ8 =116, DQ9 =118, DQ10 =132, DQ11 =124
9028 23:39:14.489164 DQ12 =140, DQ13 =138, DQ14 =136, DQ15 =142
9029 23:39:14.489785
9030 23:39:14.490164
9031 23:39:14.490507
9032 23:39:14.491787 [DramC_TX_OE_Calibration] TA2
9033 23:39:14.494865 Original DQ_B0 (3 6) =30, OEN = 27
9034 23:39:14.498768 Original DQ_B1 (3 6) =30, OEN = 27
9035 23:39:14.501817 24, 0x0, End_B0=24 End_B1=24
9036 23:39:14.505375 25, 0x0, End_B0=25 End_B1=25
9037 23:39:14.505985 26, 0x0, End_B0=26 End_B1=26
9038 23:39:14.508787 27, 0x0, End_B0=27 End_B1=27
9039 23:39:14.512300 28, 0x0, End_B0=28 End_B1=28
9040 23:39:14.515518 29, 0x0, End_B0=29 End_B1=29
9041 23:39:14.518439 30, 0x0, End_B0=30 End_B1=30
9042 23:39:14.518912 31, 0x4141, End_B0=30 End_B1=30
9043 23:39:14.521924 Byte0 end_step=30 best_step=27
9044 23:39:14.525024 Byte1 end_step=30 best_step=27
9045 23:39:14.528342 Byte0 TX OE(2T, 0.5T) = (3, 3)
9046 23:39:14.531196 Byte1 TX OE(2T, 0.5T) = (3, 3)
9047 23:39:14.531661
9048 23:39:14.532028
9049 23:39:14.538143 [DQSOSCAuto] RK1, (LSB)MR18= 0x2004, (MSB)MR19= 0x303, tDQSOscB0 = 408 ps tDQSOscB1 = 393 ps
9050 23:39:14.541271 CH1 RK1: MR19=303, MR18=2004
9051 23:39:14.548117 CH1_RK1: MR19=0x303, MR18=0x2004, DQSOSC=393, MR23=63, INC=23, DEC=15
9052 23:39:14.551414 [RxdqsGatingPostProcess] freq 1600
9053 23:39:14.558202 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9054 23:39:14.561188 best DQS0 dly(2T, 0.5T) = (1, 1)
9055 23:39:14.561688 best DQS1 dly(2T, 0.5T) = (1, 1)
9056 23:39:14.564534 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9057 23:39:14.567947 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9058 23:39:14.571485 best DQS0 dly(2T, 0.5T) = (1, 1)
9059 23:39:14.574383 best DQS1 dly(2T, 0.5T) = (1, 1)
9060 23:39:14.577836 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9061 23:39:14.581044 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9062 23:39:14.584360 Pre-setting of DQS Precalculation
9063 23:39:14.587956 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9064 23:39:14.597470 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9065 23:39:14.604304 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9066 23:39:14.604873
9067 23:39:14.605239
9068 23:39:14.607620 [Calibration Summary] 3200 Mbps
9069 23:39:14.608106 CH 0, Rank 0
9070 23:39:14.610995 SW Impedance : PASS
9071 23:39:14.611460 DUTY Scan : NO K
9072 23:39:14.614357 ZQ Calibration : PASS
9073 23:39:14.617514 Jitter Meter : NO K
9074 23:39:14.618132 CBT Training : PASS
9075 23:39:14.620917 Write leveling : PASS
9076 23:39:14.625022 RX DQS gating : PASS
9077 23:39:14.625486 RX DQ/DQS(RDDQC) : PASS
9078 23:39:14.627512 TX DQ/DQS : PASS
9079 23:39:14.630877 RX DATLAT : PASS
9080 23:39:14.631342 RX DQ/DQS(Engine): PASS
9081 23:39:14.634567 TX OE : PASS
9082 23:39:14.635131 All Pass.
9083 23:39:14.635506
9084 23:39:14.637914 CH 0, Rank 1
9085 23:39:14.638377 SW Impedance : PASS
9086 23:39:14.641147 DUTY Scan : NO K
9087 23:39:14.644893 ZQ Calibration : PASS
9088 23:39:14.645455 Jitter Meter : NO K
9089 23:39:14.647758 CBT Training : PASS
9090 23:39:14.651072 Write leveling : PASS
9091 23:39:14.651634 RX DQS gating : PASS
9092 23:39:14.654261 RX DQ/DQS(RDDQC) : PASS
9093 23:39:14.654828 TX DQ/DQS : PASS
9094 23:39:14.657632 RX DATLAT : PASS
9095 23:39:14.660955 RX DQ/DQS(Engine): PASS
9096 23:39:14.661510 TX OE : PASS
9097 23:39:14.664671 All Pass.
9098 23:39:14.665230
9099 23:39:14.665641 CH 1, Rank 0
9100 23:39:14.667412 SW Impedance : PASS
9101 23:39:14.667875 DUTY Scan : NO K
9102 23:39:14.671165 ZQ Calibration : PASS
9103 23:39:14.673991 Jitter Meter : NO K
9104 23:39:14.674452 CBT Training : PASS
9105 23:39:14.677836 Write leveling : PASS
9106 23:39:14.680856 RX DQS gating : PASS
9107 23:39:14.681327 RX DQ/DQS(RDDQC) : PASS
9108 23:39:14.684280 TX DQ/DQS : PASS
9109 23:39:14.687675 RX DATLAT : PASS
9110 23:39:14.688241 RX DQ/DQS(Engine): PASS
9111 23:39:14.690884 TX OE : PASS
9112 23:39:14.691348 All Pass.
9113 23:39:14.691749
9114 23:39:14.693801 CH 1, Rank 1
9115 23:39:14.694269 SW Impedance : PASS
9116 23:39:14.697516 DUTY Scan : NO K
9117 23:39:14.701216 ZQ Calibration : PASS
9118 23:39:14.701811 Jitter Meter : NO K
9119 23:39:14.703946 CBT Training : PASS
9120 23:39:14.704504 Write leveling : PASS
9121 23:39:14.707536 RX DQS gating : PASS
9122 23:39:14.710641 RX DQ/DQS(RDDQC) : PASS
9123 23:39:14.711205 TX DQ/DQS : PASS
9124 23:39:14.714424 RX DATLAT : PASS
9125 23:39:14.717377 RX DQ/DQS(Engine): PASS
9126 23:39:14.718186 TX OE : PASS
9127 23:39:14.720614 All Pass.
9128 23:39:14.721075
9129 23:39:14.721440 DramC Write-DBI on
9130 23:39:14.724357 PER_BANK_REFRESH: Hybrid Mode
9131 23:39:14.725051 TX_TRACKING: ON
9132 23:39:14.734289 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9133 23:39:14.744014 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9134 23:39:14.750606 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9135 23:39:14.753779 [FAST_K] Save calibration result to emmc
9136 23:39:14.757484 sync common calibartion params.
9137 23:39:14.757989 sync cbt_mode0:1, 1:1
9138 23:39:14.760380 dram_init: ddr_geometry: 2
9139 23:39:14.764238 dram_init: ddr_geometry: 2
9140 23:39:14.764869 dram_init: ddr_geometry: 2
9141 23:39:14.767239 0:dram_rank_size:100000000
9142 23:39:14.770634 1:dram_rank_size:100000000
9143 23:39:14.777107 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9144 23:39:14.777737 DFS_SHUFFLE_HW_MODE: ON
9145 23:39:14.780898 dramc_set_vcore_voltage set vcore to 725000
9146 23:39:14.783528 Read voltage for 1600, 0
9147 23:39:14.783993 Vio18 = 0
9148 23:39:14.787426 Vcore = 725000
9149 23:39:14.788022 Vdram = 0
9150 23:39:14.788397 Vddq = 0
9151 23:39:14.790339 Vmddr = 0
9152 23:39:14.790802 switch to 3200 Mbps bootup
9153 23:39:14.793638 [DramcRunTimeConfig]
9154 23:39:14.794119 PHYPLL
9155 23:39:14.796728 DPM_CONTROL_AFTERK: ON
9156 23:39:14.797189 PER_BANK_REFRESH: ON
9157 23:39:14.800223 REFRESH_OVERHEAD_REDUCTION: ON
9158 23:39:14.803646 CMD_PICG_NEW_MODE: OFF
9159 23:39:14.804207 XRTWTW_NEW_MODE: ON
9160 23:39:14.807397 XRTRTR_NEW_MODE: ON
9161 23:39:14.807964 TX_TRACKING: ON
9162 23:39:14.810307 RDSEL_TRACKING: OFF
9163 23:39:14.813858 DQS Precalculation for DVFS: ON
9164 23:39:14.814417 RX_TRACKING: OFF
9165 23:39:14.817190 HW_GATING DBG: ON
9166 23:39:14.817783 ZQCS_ENABLE_LP4: ON
9167 23:39:14.820328 RX_PICG_NEW_MODE: ON
9168 23:39:14.820894 TX_PICG_NEW_MODE: ON
9169 23:39:14.823357 ENABLE_RX_DCM_DPHY: ON
9170 23:39:14.826535 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9171 23:39:14.830005 DUMMY_READ_FOR_TRACKING: OFF
9172 23:39:14.830468 !!! SPM_CONTROL_AFTERK: OFF
9173 23:39:14.833632 !!! SPM could not control APHY
9174 23:39:14.837075 IMPEDANCE_TRACKING: ON
9175 23:39:14.837875 TEMP_SENSOR: ON
9176 23:39:14.840252 HW_SAVE_FOR_SR: OFF
9177 23:39:14.843517 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9178 23:39:14.847120 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9179 23:39:14.850047 Read ODT Tracking: ON
9180 23:39:14.850603 Refresh Rate DeBounce: ON
9181 23:39:14.853726 DFS_NO_QUEUE_FLUSH: ON
9182 23:39:14.857144 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9183 23:39:14.859900 ENABLE_DFS_RUNTIME_MRW: OFF
9184 23:39:14.860363 DDR_RESERVE_NEW_MODE: ON
9185 23:39:14.863439 MR_CBT_SWITCH_FREQ: ON
9186 23:39:14.866594 =========================
9187 23:39:14.883858 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9188 23:39:14.887704 dram_init: ddr_geometry: 2
9189 23:39:14.905525 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9190 23:39:14.908995 dram_init: dram init end (result: 0)
9191 23:39:14.915476 DRAM-K: Full calibration passed in 24423 msecs
9192 23:39:14.918854 MRC: failed to locate region type 0.
9193 23:39:14.919448 DRAM rank0 size:0x100000000,
9194 23:39:14.922205 DRAM rank1 size=0x100000000
9195 23:39:14.931947 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9196 23:39:14.938540 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9197 23:39:14.945456 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9198 23:39:14.952354 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9199 23:39:14.955152 DRAM rank0 size:0x100000000,
9200 23:39:14.959040 DRAM rank1 size=0x100000000
9201 23:39:14.959504 CBMEM:
9202 23:39:14.962349 IMD: root @ 0xfffff000 254 entries.
9203 23:39:14.965058 IMD: root @ 0xffffec00 62 entries.
9204 23:39:14.969049 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9205 23:39:14.972390 WARNING: RO_VPD is uninitialized or empty.
9206 23:39:14.978905 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9207 23:39:14.986056 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9208 23:39:14.998594 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9209 23:39:15.010430 BS: romstage times (exec / console): total (unknown) / 23958 ms
9210 23:39:15.010990
9211 23:39:15.011360
9212 23:39:15.019846 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9213 23:39:15.023210 ARM64: Exception handlers installed.
9214 23:39:15.026162 ARM64: Testing exception
9215 23:39:15.029514 ARM64: Done test exception
9216 23:39:15.030173 Enumerating buses...
9217 23:39:15.032834 Show all devs... Before device enumeration.
9218 23:39:15.036480 Root Device: enabled 1
9219 23:39:15.039990 CPU_CLUSTER: 0: enabled 1
9220 23:39:15.040465 CPU: 00: enabled 1
9221 23:39:15.043383 Compare with tree...
9222 23:39:15.043944 Root Device: enabled 1
9223 23:39:15.046365 CPU_CLUSTER: 0: enabled 1
9224 23:39:15.049797 CPU: 00: enabled 1
9225 23:39:15.050431 Root Device scanning...
9226 23:39:15.052917 scan_static_bus for Root Device
9227 23:39:15.056515 CPU_CLUSTER: 0 enabled
9228 23:39:15.059565 scan_static_bus for Root Device done
9229 23:39:15.063230 scan_bus: bus Root Device finished in 8 msecs
9230 23:39:15.063903 done
9231 23:39:15.069450 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9232 23:39:15.073205 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9233 23:39:15.079946 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9234 23:39:15.082900 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9235 23:39:15.086170 Allocating resources...
9236 23:39:15.089870 Reading resources...
9237 23:39:15.093374 Root Device read_resources bus 0 link: 0
9238 23:39:15.093981 DRAM rank0 size:0x100000000,
9239 23:39:15.096107 DRAM rank1 size=0x100000000
9240 23:39:15.099519 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9241 23:39:15.102831 CPU: 00 missing read_resources
9242 23:39:15.105895 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9243 23:39:15.113066 Root Device read_resources bus 0 link: 0 done
9244 23:39:15.113678 Done reading resources.
9245 23:39:15.119430 Show resources in subtree (Root Device)...After reading.
9246 23:39:15.122898 Root Device child on link 0 CPU_CLUSTER: 0
9247 23:39:15.126241 CPU_CLUSTER: 0 child on link 0 CPU: 00
9248 23:39:15.136367 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9249 23:39:15.136933 CPU: 00
9250 23:39:15.139811 Root Device assign_resources, bus 0 link: 0
9251 23:39:15.142715 CPU_CLUSTER: 0 missing set_resources
9252 23:39:15.145987 Root Device assign_resources, bus 0 link: 0 done
9253 23:39:15.149375 Done setting resources.
9254 23:39:15.155895 Show resources in subtree (Root Device)...After assigning values.
9255 23:39:15.159178 Root Device child on link 0 CPU_CLUSTER: 0
9256 23:39:15.162859 CPU_CLUSTER: 0 child on link 0 CPU: 00
9257 23:39:15.172835 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9258 23:39:15.173400 CPU: 00
9259 23:39:15.176484 Done allocating resources.
9260 23:39:15.179955 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9261 23:39:15.183637 Enabling resources...
9262 23:39:15.184196 done.
9263 23:39:15.189083 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9264 23:39:15.189549 Initializing devices...
9265 23:39:15.193433 Root Device init
9266 23:39:15.194052 init hardware done!
9267 23:39:15.195976 0x00000018: ctrlr->caps
9268 23:39:15.199380 52.000 MHz: ctrlr->f_max
9269 23:39:15.199854 0.400 MHz: ctrlr->f_min
9270 23:39:15.202287 0x40ff8080: ctrlr->voltages
9271 23:39:15.202756 sclk: 390625
9272 23:39:15.206336 Bus Width = 1
9273 23:39:15.206900 sclk: 390625
9274 23:39:15.209390 Bus Width = 1
9275 23:39:15.210002 Early init status = 3
9276 23:39:15.216088 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9277 23:39:15.219106 in-header: 03 fc 00 00 01 00 00 00
9278 23:39:15.219668 in-data: 00
9279 23:39:15.225986 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9280 23:39:15.228766 in-header: 03 fd 00 00 00 00 00 00
9281 23:39:15.232397 in-data:
9282 23:39:15.236259 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9283 23:39:15.239311 in-header: 03 fc 00 00 01 00 00 00
9284 23:39:15.242134 in-data: 00
9285 23:39:15.245845 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9286 23:39:15.250089 in-header: 03 fd 00 00 00 00 00 00
9287 23:39:15.253529 in-data:
9288 23:39:15.256044 [SSUSB] Setting up USB HOST controller...
9289 23:39:15.260498 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9290 23:39:15.263155 [SSUSB] phy power-on done.
9291 23:39:15.266086 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9292 23:39:15.272650 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9293 23:39:15.276451 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9294 23:39:15.282658 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9295 23:39:15.289461 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
9296 23:39:15.296760 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9297 23:39:15.303030 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9298 23:39:15.309471 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9299 23:39:15.312660 SPM: binary array size = 0x9dc
9300 23:39:15.316255 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9301 23:39:15.322877 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9302 23:39:15.328950 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9303 23:39:15.336344 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9304 23:39:15.339000 configure_display: Starting display init
9305 23:39:15.373449 anx7625_power_on_init: Init interface.
9306 23:39:15.376613 anx7625_disable_pd_protocol: Disabled PD feature.
9307 23:39:15.379810 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9308 23:39:15.407632 anx7625_start_dp_work: Secure OCM version=00
9309 23:39:15.410675 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9310 23:39:15.425777 sp_tx_get_edid_block: EDID Block = 1
9311 23:39:15.528082 Extracted contents:
9312 23:39:15.531134 header: 00 ff ff ff ff ff ff 00
9313 23:39:15.534429 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9314 23:39:15.537996 version: 01 04
9315 23:39:15.541667 basic params: 95 1f 11 78 0a
9316 23:39:15.544680 chroma info: 76 90 94 55 54 90 27 21 50 54
9317 23:39:15.547875 established: 00 00 00
9318 23:39:15.554488 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9319 23:39:15.558088 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9320 23:39:15.564870 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9321 23:39:15.571878 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9322 23:39:15.577805 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9323 23:39:15.581409 extensions: 00
9324 23:39:15.582032 checksum: fb
9325 23:39:15.582409
9326 23:39:15.584824 Manufacturer: IVO Model 57d Serial Number 0
9327 23:39:15.588084 Made week 0 of 2020
9328 23:39:15.588650 EDID version: 1.4
9329 23:39:15.591029 Digital display
9330 23:39:15.594318 6 bits per primary color channel
9331 23:39:15.594788 DisplayPort interface
9332 23:39:15.598237 Maximum image size: 31 cm x 17 cm
9333 23:39:15.601033 Gamma: 220%
9334 23:39:15.601494 Check DPMS levels
9335 23:39:15.604861 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9336 23:39:15.610985 First detailed timing is preferred timing
9337 23:39:15.611554 Established timings supported:
9338 23:39:15.614510 Standard timings supported:
9339 23:39:15.617668 Detailed timings
9340 23:39:15.620925 Hex of detail: 383680a07038204018303c0035ae10000019
9341 23:39:15.624394 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9342 23:39:15.630611 0780 0798 07c8 0820 hborder 0
9343 23:39:15.633995 0438 043b 0447 0458 vborder 0
9344 23:39:15.637231 -hsync -vsync
9345 23:39:15.637742 Did detailed timing
9346 23:39:15.644054 Hex of detail: 000000000000000000000000000000000000
9347 23:39:15.644523 Manufacturer-specified data, tag 0
9348 23:39:15.650987 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9349 23:39:15.654347 ASCII string: InfoVision
9350 23:39:15.657726 Hex of detail: 000000fe00523134304e574635205248200a
9351 23:39:15.661306 ASCII string: R140NWF5 RH
9352 23:39:15.661805 Checksum
9353 23:39:15.662177 Checksum: 0xfb (valid)
9354 23:39:15.667375 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9355 23:39:15.670570 DSI data_rate: 832800000 bps
9356 23:39:15.677162 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9357 23:39:15.680670 anx7625_parse_edid: pixelclock(138800).
9358 23:39:15.683760 hactive(1920), hsync(48), hfp(24), hbp(88)
9359 23:39:15.687281 vactive(1080), vsync(12), vfp(3), vbp(17)
9360 23:39:15.690208 anx7625_dsi_config: config dsi.
9361 23:39:15.697322 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9362 23:39:15.710265 anx7625_dsi_config: success to config DSI
9363 23:39:15.713534 anx7625_dp_start: MIPI phy setup OK.
9364 23:39:15.717125 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9365 23:39:15.720294 mtk_ddp_mode_set invalid vrefresh 60
9366 23:39:15.723241 main_disp_path_setup
9367 23:39:15.723659 ovl_layer_smi_id_en
9368 23:39:15.726777 ovl_layer_smi_id_en
9369 23:39:15.727314 ccorr_config
9370 23:39:15.727649 aal_config
9371 23:39:15.729916 gamma_config
9372 23:39:15.730334 postmask_config
9373 23:39:15.733038 dither_config
9374 23:39:15.736747 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9375 23:39:15.743076 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9376 23:39:15.746115 Root Device init finished in 551 msecs
9377 23:39:15.749917 CPU_CLUSTER: 0 init
9378 23:39:15.756425 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9379 23:39:15.759583 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9380 23:39:15.763453 APU_MBOX 0x190000b0 = 0x10001
9381 23:39:15.766453 APU_MBOX 0x190001b0 = 0x10001
9382 23:39:15.769646 APU_MBOX 0x190005b0 = 0x10001
9383 23:39:15.773128 APU_MBOX 0x190006b0 = 0x10001
9384 23:39:15.779272 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9385 23:39:15.788981 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9386 23:39:15.801422 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9387 23:39:15.808173 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9388 23:39:15.820217 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9389 23:39:15.828997 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9390 23:39:15.832234 CPU_CLUSTER: 0 init finished in 81 msecs
9391 23:39:15.835219 Devices initialized
9392 23:39:15.838787 Show all devs... After init.
9393 23:39:15.839348 Root Device: enabled 1
9394 23:39:15.841932 CPU_CLUSTER: 0: enabled 1
9395 23:39:15.845417 CPU: 00: enabled 1
9396 23:39:15.848838 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9397 23:39:15.852242 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9398 23:39:15.855823 ELOG: NV offset 0x57f000 size 0x1000
9399 23:39:15.861925 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9400 23:39:15.868345 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9401 23:39:15.871666 ELOG: Event(17) added with size 13 at 2023-12-03 23:37:01 UTC
9402 23:39:15.875171 out: cmd=0x121: 03 db 21 01 00 00 00 00
9403 23:39:15.879373 in-header: 03 00 00 00 2c 00 00 00
9404 23:39:15.892778 in-data: 5f 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9405 23:39:15.898920 ELOG: Event(A1) added with size 10 at 2023-12-03 23:37:02 UTC
9406 23:39:15.906011 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9407 23:39:15.913010 ELOG: Event(A0) added with size 9 at 2023-12-03 23:37:02 UTC
9408 23:39:15.915773 elog_add_boot_reason: Logged dev mode boot
9409 23:39:15.918905 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9410 23:39:15.922694 Finalize devices...
9411 23:39:15.923249 Devices finalized
9412 23:39:15.928642 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9413 23:39:15.932175 Writing coreboot table at 0xffe64000
9414 23:39:15.935602 0. 000000000010a000-0000000000113fff: RAMSTAGE
9415 23:39:15.939001 1. 0000000040000000-00000000400fffff: RAM
9416 23:39:15.942275 2. 0000000040100000-000000004032afff: RAMSTAGE
9417 23:39:15.949084 3. 000000004032b000-00000000545fffff: RAM
9418 23:39:15.952333 4. 0000000054600000-000000005465ffff: BL31
9419 23:39:15.955733 5. 0000000054660000-00000000ffe63fff: RAM
9420 23:39:15.962570 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9421 23:39:15.965698 7. 0000000100000000-000000023fffffff: RAM
9422 23:39:15.966166 Passing 5 GPIOs to payload:
9423 23:39:15.972258 NAME | PORT | POLARITY | VALUE
9424 23:39:15.975203 EC in RW | 0x000000aa | low | undefined
9425 23:39:15.982350 EC interrupt | 0x00000005 | low | undefined
9426 23:39:15.985770 TPM interrupt | 0x000000ab | high | undefined
9427 23:39:15.988600 SD card detect | 0x00000011 | high | undefined
9428 23:39:15.995463 speaker enable | 0x00000093 | high | undefined
9429 23:39:15.998528 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9430 23:39:16.001774 in-header: 03 f9 00 00 02 00 00 00
9431 23:39:16.002242 in-data: 02 00
9432 23:39:16.005494 ADC[4]: Raw value=905096 ID=7
9433 23:39:16.008399 ADC[3]: Raw value=213441 ID=1
9434 23:39:16.008868 RAM Code: 0x71
9435 23:39:16.012116 ADC[6]: Raw value=75701 ID=0
9436 23:39:16.015333 ADC[5]: Raw value=213072 ID=1
9437 23:39:16.015911 SKU Code: 0x1
9438 23:39:16.022390 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 425c
9439 23:39:16.025491 coreboot table: 964 bytes.
9440 23:39:16.028686 IMD ROOT 0. 0xfffff000 0x00001000
9441 23:39:16.032270 IMD SMALL 1. 0xffffe000 0x00001000
9442 23:39:16.034777 RO MCACHE 2. 0xffffc000 0x00001104
9443 23:39:16.039016 CONSOLE 3. 0xfff7c000 0x00080000
9444 23:39:16.042071 FMAP 4. 0xfff7b000 0x00000452
9445 23:39:16.045100 TIME STAMP 5. 0xfff7a000 0x00000910
9446 23:39:16.048603 VBOOT WORK 6. 0xfff66000 0x00014000
9447 23:39:16.052037 RAMOOPS 7. 0xffe66000 0x00100000
9448 23:39:16.055110 COREBOOT 8. 0xffe64000 0x00002000
9449 23:39:16.055676 IMD small region:
9450 23:39:16.058204 IMD ROOT 0. 0xffffec00 0x00000400
9451 23:39:16.061825 VPD 1. 0xffffeb80 0x0000006c
9452 23:39:16.065080 MMC STATUS 2. 0xffffeb60 0x00000004
9453 23:39:16.071574 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9454 23:39:16.074910 Probing TPM: done!
9455 23:39:16.077997 Connected to device vid:did:rid of 1ae0:0028:00
9456 23:39:16.088582 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9457 23:39:16.091518 Initialized TPM device CR50 revision 0
9458 23:39:16.095528 Checking cr50 for pending updates
9459 23:39:16.098763 Reading cr50 TPM mode
9460 23:39:16.107253 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9461 23:39:16.114223 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9462 23:39:16.154031 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9463 23:39:16.157366 Checking segment from ROM address 0x40100000
9464 23:39:16.160932 Checking segment from ROM address 0x4010001c
9465 23:39:16.167289 Loading segment from ROM address 0x40100000
9466 23:39:16.167852 code (compression=0)
9467 23:39:16.174209 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9468 23:39:16.184126 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9469 23:39:16.184694 it's not compressed!
9470 23:39:16.190893 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9471 23:39:16.194568 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9472 23:39:16.214206 Loading segment from ROM address 0x4010001c
9473 23:39:16.214782 Entry Point 0x80000000
9474 23:39:16.217809 Loaded segments
9475 23:39:16.220960 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9476 23:39:16.227812 Jumping to boot code at 0x80000000(0xffe64000)
9477 23:39:16.234394 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9478 23:39:16.241048 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9479 23:39:16.248828 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9480 23:39:16.252091 Checking segment from ROM address 0x40100000
9481 23:39:16.255925 Checking segment from ROM address 0x4010001c
9482 23:39:16.261946 Loading segment from ROM address 0x40100000
9483 23:39:16.262416 code (compression=1)
9484 23:39:16.269460 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9485 23:39:16.278698 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9486 23:39:16.279252 using LZMA
9487 23:39:16.287551 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9488 23:39:16.293983 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9489 23:39:16.297299 Loading segment from ROM address 0x4010001c
9490 23:39:16.297815 Entry Point 0x54601000
9491 23:39:16.300515 Loaded segments
9492 23:39:16.303746 NOTICE: MT8192 bl31_setup
9493 23:39:16.310892 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9494 23:39:16.314462 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9495 23:39:16.317305 WARNING: region 0:
9496 23:39:16.320951 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9497 23:39:16.321518 WARNING: region 1:
9498 23:39:16.327483 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9499 23:39:16.330524 WARNING: region 2:
9500 23:39:16.334313 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9501 23:39:16.337639 WARNING: region 3:
9502 23:39:16.341231 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9503 23:39:16.344560 WARNING: region 4:
9504 23:39:16.347376 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9505 23:39:16.351294 WARNING: region 5:
9506 23:39:16.353989 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9507 23:39:16.357428 WARNING: region 6:
9508 23:39:16.361176 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9509 23:39:16.361833 WARNING: region 7:
9510 23:39:16.367810 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9511 23:39:16.374162 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9512 23:39:16.377457 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9513 23:39:16.380829 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9514 23:39:16.387533 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9515 23:39:16.390949 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9516 23:39:16.394144 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9517 23:39:16.401037 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9518 23:39:16.404065 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9519 23:39:16.407651 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9520 23:39:16.413995 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9521 23:39:16.417244 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9522 23:39:16.424328 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9523 23:39:16.427255 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9524 23:39:16.430841 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9525 23:39:16.437353 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9526 23:39:16.441373 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9527 23:39:16.444567 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9528 23:39:16.450910 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9529 23:39:16.454453 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9530 23:39:16.457441 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9531 23:39:16.464339 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9532 23:39:16.467976 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9533 23:39:16.474559 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9534 23:39:16.478020 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9535 23:39:16.481338 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9536 23:39:16.487610 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9537 23:39:16.490979 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9538 23:39:16.497466 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9539 23:39:16.500968 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9540 23:39:16.504381 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9541 23:39:16.511108 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9542 23:39:16.514272 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9543 23:39:16.517949 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9544 23:39:16.524504 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9545 23:39:16.527426 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9546 23:39:16.531050 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9547 23:39:16.534420 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9548 23:39:16.540842 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9549 23:39:16.544290 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9550 23:39:16.547721 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9551 23:39:16.551244 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9552 23:39:16.558597 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9553 23:39:16.561506 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9554 23:39:16.564240 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9555 23:39:16.568031 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9556 23:39:16.574829 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9557 23:39:16.578196 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9558 23:39:16.581656 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9559 23:39:16.588176 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9560 23:39:16.591617 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9561 23:39:16.594405 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9562 23:39:16.601656 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9563 23:39:16.604900 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9564 23:39:16.611618 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9565 23:39:16.614525 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9566 23:39:16.621499 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9567 23:39:16.624662 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9568 23:39:16.627700 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9569 23:39:16.634650 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9570 23:39:16.637654 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9571 23:39:16.644413 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9572 23:39:16.647937 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9573 23:39:16.654377 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9574 23:39:16.657946 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9575 23:39:16.661289 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9576 23:39:16.668041 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9577 23:39:16.671779 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9578 23:39:16.678265 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9579 23:39:16.681764 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9580 23:39:16.688389 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9581 23:39:16.691588 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9582 23:39:16.694606 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9583 23:39:16.701441 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9584 23:39:16.704874 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9585 23:39:16.711427 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9586 23:39:16.714834 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9587 23:39:16.721825 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9588 23:39:16.724958 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9589 23:39:16.728435 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9590 23:39:16.734932 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9591 23:39:16.737887 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9592 23:39:16.744671 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9593 23:39:16.747943 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9594 23:39:16.754938 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9595 23:39:16.757816 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9596 23:39:16.761232 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9597 23:39:16.767850 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9598 23:39:16.771152 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9599 23:39:16.778588 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9600 23:39:16.782067 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9601 23:39:16.787697 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9602 23:39:16.791101 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9603 23:39:16.794863 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9604 23:39:16.801385 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9605 23:39:16.805280 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9606 23:39:16.811658 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9607 23:39:16.815070 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9608 23:39:16.818301 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9609 23:39:16.824669 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9610 23:39:16.828676 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9611 23:39:16.831510 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9612 23:39:16.834821 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9613 23:39:16.841860 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9614 23:39:16.844699 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9615 23:39:16.851228 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9616 23:39:16.855549 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9617 23:39:16.858534 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9618 23:39:16.864715 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9619 23:39:16.868200 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9620 23:39:16.874883 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9621 23:39:16.878841 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9622 23:39:16.881433 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9623 23:39:16.888527 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9624 23:39:16.891423 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9625 23:39:16.898274 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9626 23:39:16.901556 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9627 23:39:16.905034 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9628 23:39:16.908553 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9629 23:39:16.915089 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9630 23:39:16.918648 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9631 23:39:16.921990 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9632 23:39:16.925251 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9633 23:39:16.931513 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9634 23:39:16.935030 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9635 23:39:16.938247 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9636 23:39:16.945253 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9637 23:39:16.948484 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9638 23:39:16.952375 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9639 23:39:16.958632 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9640 23:39:16.961871 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9641 23:39:16.968378 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9642 23:39:16.971978 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9643 23:39:16.974917 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9644 23:39:16.981881 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9645 23:39:16.985181 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9646 23:39:16.991713 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9647 23:39:16.995764 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9648 23:39:16.998209 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9649 23:39:17.004965 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9650 23:39:17.008755 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9651 23:39:17.011776 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9652 23:39:17.018229 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9653 23:39:17.021461 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9654 23:39:17.028398 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9655 23:39:17.031302 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9656 23:39:17.035084 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9657 23:39:17.041177 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9658 23:39:17.044755 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9659 23:39:17.051598 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9660 23:39:17.055188 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9661 23:39:17.058001 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9662 23:39:17.064689 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9663 23:39:17.068106 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9664 23:39:17.075456 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9665 23:39:17.078222 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9666 23:39:17.081793 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9667 23:39:17.088325 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9668 23:39:17.091496 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9669 23:39:17.095141 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9670 23:39:17.101740 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9671 23:39:17.104641 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9672 23:39:17.112063 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9673 23:39:17.114859 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9674 23:39:17.118192 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9675 23:39:17.125034 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9676 23:39:17.128422 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9677 23:39:17.134949 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9678 23:39:17.138076 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9679 23:39:17.141047 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9680 23:39:17.148308 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9681 23:39:17.151314 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9682 23:39:17.158452 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9683 23:39:17.161555 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9684 23:39:17.164661 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9685 23:39:17.171711 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9686 23:39:17.174601 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9687 23:39:17.181655 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9688 23:39:17.184497 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9689 23:39:17.188177 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9690 23:39:17.194567 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9691 23:39:17.197772 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9692 23:39:17.201279 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9693 23:39:17.208327 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9694 23:39:17.211071 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9695 23:39:17.217698 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9696 23:39:17.221129 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9697 23:39:17.224486 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9698 23:39:17.231043 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9699 23:39:17.234233 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9700 23:39:17.240802 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9701 23:39:17.244860 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9702 23:39:17.251169 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9703 23:39:17.254193 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9704 23:39:17.257473 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9705 23:39:17.264464 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9706 23:39:17.267968 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9707 23:39:17.274537 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9708 23:39:17.277695 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9709 23:39:17.280907 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9710 23:39:17.287508 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9711 23:39:17.291018 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9712 23:39:17.297479 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9713 23:39:17.300919 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9714 23:39:17.303913 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9715 23:39:17.310751 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9716 23:39:17.314102 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9717 23:39:17.320702 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9718 23:39:17.324134 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9719 23:39:17.330472 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9720 23:39:17.333680 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9721 23:39:17.336803 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9722 23:39:17.344297 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9723 23:39:17.346949 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9724 23:39:17.353939 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9725 23:39:17.357508 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9726 23:39:17.360573 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9727 23:39:17.367438 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9728 23:39:17.370371 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9729 23:39:17.377749 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9730 23:39:17.380317 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9731 23:39:17.387292 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9732 23:39:17.390510 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9733 23:39:17.393964 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9734 23:39:17.400524 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9735 23:39:17.403939 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9736 23:39:17.410324 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9737 23:39:17.413955 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9738 23:39:17.420326 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9739 23:39:17.423824 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9740 23:39:17.427098 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9741 23:39:17.430245 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9742 23:39:17.436829 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9743 23:39:17.440307 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9744 23:39:17.443448 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9745 23:39:17.446801 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9746 23:39:17.453374 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9747 23:39:17.456781 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9748 23:39:17.463077 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9749 23:39:17.466472 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9750 23:39:17.469903 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9751 23:39:17.476693 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9752 23:39:17.479860 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9753 23:39:17.483331 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9754 23:39:17.489750 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9755 23:39:17.492496 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9756 23:39:17.499491 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9757 23:39:17.502693 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9758 23:39:17.506080 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9759 23:39:17.513000 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9760 23:39:17.516138 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9761 23:39:17.519194 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9762 23:39:17.526284 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9763 23:39:17.529652 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9764 23:39:17.532857 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9765 23:39:17.539568 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9766 23:39:17.542743 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9767 23:39:17.549326 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9768 23:39:17.552571 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9769 23:39:17.556033 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9770 23:39:17.562229 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9771 23:39:17.565736 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9772 23:39:17.569135 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9773 23:39:17.575474 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9774 23:39:17.579669 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9775 23:39:17.582307 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9776 23:39:17.589492 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9777 23:39:17.592431 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9778 23:39:17.599097 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9779 23:39:17.602426 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9780 23:39:17.605563 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9781 23:39:17.608896 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9782 23:39:17.616235 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9783 23:39:17.619107 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9784 23:39:17.622178 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9785 23:39:17.626016 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9786 23:39:17.629506 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9787 23:39:17.636647 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9788 23:39:17.638771 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9789 23:39:17.642122 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9790 23:39:17.645398 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9791 23:39:17.652812 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9792 23:39:17.655196 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9793 23:39:17.662113 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9794 23:39:17.665748 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9795 23:39:17.668805 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9796 23:39:17.675282 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9797 23:39:17.679036 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9798 23:39:17.685748 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9799 23:39:17.688787 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9800 23:39:17.692062 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9801 23:39:17.698794 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9802 23:39:17.702175 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9803 23:39:17.708673 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9804 23:39:17.712180 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9805 23:39:17.718588 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9806 23:39:17.722172 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9807 23:39:17.725375 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9808 23:39:17.731865 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9809 23:39:17.734938 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9810 23:39:17.738355 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9811 23:39:17.744864 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9812 23:39:17.748894 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9813 23:39:17.755039 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9814 23:39:17.758242 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9815 23:39:17.765477 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9816 23:39:17.768612 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9817 23:39:17.771539 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9818 23:39:17.778104 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9819 23:39:17.781408 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9820 23:39:17.788030 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9821 23:39:17.791664 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9822 23:39:17.797984 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9823 23:39:17.801792 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9824 23:39:17.804499 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9825 23:39:17.811031 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9826 23:39:17.814907 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9827 23:39:17.821252 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9828 23:39:17.824304 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9829 23:39:17.828319 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9830 23:39:17.834395 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9831 23:39:17.838170 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9832 23:39:17.844617 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9833 23:39:17.847360 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9834 23:39:17.851176 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9835 23:39:17.857769 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9836 23:39:17.861202 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9837 23:39:17.867359 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9838 23:39:17.871198 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9839 23:39:17.874325 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9840 23:39:17.881195 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9841 23:39:17.884182 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9842 23:39:17.890913 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9843 23:39:17.894019 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9844 23:39:17.897987 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9845 23:39:17.904128 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9846 23:39:17.907812 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9847 23:39:17.914444 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9848 23:39:17.918053 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9849 23:39:17.921140 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9850 23:39:17.928087 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9851 23:39:17.931322 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9852 23:39:17.937441 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9853 23:39:17.941249 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9854 23:39:17.947206 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9855 23:39:17.950951 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9856 23:39:17.954309 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9857 23:39:17.960494 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9858 23:39:17.964381 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9859 23:39:17.970415 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9860 23:39:17.973977 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9861 23:39:17.977237 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9862 23:39:17.983954 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9863 23:39:17.986865 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9864 23:39:17.993935 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9865 23:39:17.996760 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9866 23:39:18.003561 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9867 23:39:18.007020 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9868 23:39:18.009954 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9869 23:39:18.016591 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9870 23:39:18.019760 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9871 23:39:18.026627 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9872 23:39:18.029717 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9873 23:39:18.036708 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9874 23:39:18.039662 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9875 23:39:18.046146 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9876 23:39:18.050111 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9877 23:39:18.056144 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9878 23:39:18.059901 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9879 23:39:18.062680 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9880 23:39:18.069603 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9881 23:39:18.072936 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9882 23:39:18.079605 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9883 23:39:18.082875 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9884 23:39:18.089635 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9885 23:39:18.092383 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9886 23:39:18.096485 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9887 23:39:18.102682 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9888 23:39:18.105467 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9889 23:39:18.113102 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9890 23:39:18.115938 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9891 23:39:18.122441 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9892 23:39:18.126152 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9893 23:39:18.129025 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9894 23:39:18.135685 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9895 23:39:18.139057 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9896 23:39:18.145633 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9897 23:39:18.149015 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9898 23:39:18.156071 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9899 23:39:18.159293 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9900 23:39:18.165654 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9901 23:39:18.168945 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9902 23:39:18.172265 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9903 23:39:18.178472 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9904 23:39:18.182528 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9905 23:39:18.188760 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9906 23:39:18.192693 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9907 23:39:18.198685 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9908 23:39:18.201911 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9909 23:39:18.205698 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9910 23:39:18.212308 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9911 23:39:18.215458 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9912 23:39:18.222077 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9913 23:39:18.224978 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9914 23:39:18.228664 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9915 23:39:18.235167 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9916 23:39:18.238829 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9917 23:39:18.245377 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9918 23:39:18.248351 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9919 23:39:18.254922 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9920 23:39:18.258514 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9921 23:39:18.265360 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9922 23:39:18.268361 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9923 23:39:18.274709 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9924 23:39:18.278184 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9925 23:39:18.284896 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9926 23:39:18.288094 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9927 23:39:18.294478 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9928 23:39:18.298098 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9929 23:39:18.305112 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9930 23:39:18.307794 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9931 23:39:18.314954 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9932 23:39:18.317870 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9933 23:39:18.324499 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9934 23:39:18.328334 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9935 23:39:18.334430 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9936 23:39:18.337822 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9937 23:39:18.345037 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9938 23:39:18.348084 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9939 23:39:18.354333 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9940 23:39:18.357955 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9941 23:39:18.364309 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9942 23:39:18.367538 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9943 23:39:18.374463 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9944 23:39:18.377484 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9945 23:39:18.380892 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9946 23:39:18.384121 INFO: [APUAPC] vio 0
9947 23:39:18.390859 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9948 23:39:18.394347 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9949 23:39:18.397355 INFO: [APUAPC] D0_APC_0: 0x400510
9950 23:39:18.401124 INFO: [APUAPC] D0_APC_1: 0x0
9951 23:39:18.404169 INFO: [APUAPC] D0_APC_2: 0x1540
9952 23:39:18.407280 INFO: [APUAPC] D0_APC_3: 0x0
9953 23:39:18.411162 INFO: [APUAPC] D1_APC_0: 0xffffffff
9954 23:39:18.413769 INFO: [APUAPC] D1_APC_1: 0xffffffff
9955 23:39:18.417521 INFO: [APUAPC] D1_APC_2: 0x3fffff
9956 23:39:18.420952 INFO: [APUAPC] D1_APC_3: 0x0
9957 23:39:18.423794 INFO: [APUAPC] D2_APC_0: 0xffffffff
9958 23:39:18.427454 INFO: [APUAPC] D2_APC_1: 0xffffffff
9959 23:39:18.430495 INFO: [APUAPC] D2_APC_2: 0x3fffff
9960 23:39:18.433758 INFO: [APUAPC] D2_APC_3: 0x0
9961 23:39:18.437031 INFO: [APUAPC] D3_APC_0: 0xffffffff
9962 23:39:18.440909 INFO: [APUAPC] D3_APC_1: 0xffffffff
9963 23:39:18.443749 INFO: [APUAPC] D3_APC_2: 0x3fffff
9964 23:39:18.444327 INFO: [APUAPC] D3_APC_3: 0x0
9965 23:39:18.447058 INFO: [APUAPC] D4_APC_0: 0xffffffff
9966 23:39:18.454298 INFO: [APUAPC] D4_APC_1: 0xffffffff
9967 23:39:18.454868 INFO: [APUAPC] D4_APC_2: 0x3fffff
9968 23:39:18.457489 INFO: [APUAPC] D4_APC_3: 0x0
9969 23:39:18.460848 INFO: [APUAPC] D5_APC_0: 0xffffffff
9970 23:39:18.463937 INFO: [APUAPC] D5_APC_1: 0xffffffff
9971 23:39:18.467434 INFO: [APUAPC] D5_APC_2: 0x3fffff
9972 23:39:18.470725 INFO: [APUAPC] D5_APC_3: 0x0
9973 23:39:18.473948 INFO: [APUAPC] D6_APC_0: 0xffffffff
9974 23:39:18.477507 INFO: [APUAPC] D6_APC_1: 0xffffffff
9975 23:39:18.480820 INFO: [APUAPC] D6_APC_2: 0x3fffff
9976 23:39:18.483629 INFO: [APUAPC] D6_APC_3: 0x0
9977 23:39:18.487542 INFO: [APUAPC] D7_APC_0: 0xffffffff
9978 23:39:18.490578 INFO: [APUAPC] D7_APC_1: 0xffffffff
9979 23:39:18.494077 INFO: [APUAPC] D7_APC_2: 0x3fffff
9980 23:39:18.496710 INFO: [APUAPC] D7_APC_3: 0x0
9981 23:39:18.500370 INFO: [APUAPC] D8_APC_0: 0xffffffff
9982 23:39:18.503310 INFO: [APUAPC] D8_APC_1: 0xffffffff
9983 23:39:18.506860 INFO: [APUAPC] D8_APC_2: 0x3fffff
9984 23:39:18.510971 INFO: [APUAPC] D8_APC_3: 0x0
9985 23:39:18.513699 INFO: [APUAPC] D9_APC_0: 0xffffffff
9986 23:39:18.517051 INFO: [APUAPC] D9_APC_1: 0xffffffff
9987 23:39:18.520286 INFO: [APUAPC] D9_APC_2: 0x3fffff
9988 23:39:18.523660 INFO: [APUAPC] D9_APC_3: 0x0
9989 23:39:18.526505 INFO: [APUAPC] D10_APC_0: 0xffffffff
9990 23:39:18.530349 INFO: [APUAPC] D10_APC_1: 0xffffffff
9991 23:39:18.533639 INFO: [APUAPC] D10_APC_2: 0x3fffff
9992 23:39:18.536654 INFO: [APUAPC] D10_APC_3: 0x0
9993 23:39:18.540035 INFO: [APUAPC] D11_APC_0: 0xffffffff
9994 23:39:18.543206 INFO: [APUAPC] D11_APC_1: 0xffffffff
9995 23:39:18.546751 INFO: [APUAPC] D11_APC_2: 0x3fffff
9996 23:39:18.549944 INFO: [APUAPC] D11_APC_3: 0x0
9997 23:39:18.553793 INFO: [APUAPC] D12_APC_0: 0xffffffff
9998 23:39:18.556454 INFO: [APUAPC] D12_APC_1: 0xffffffff
9999 23:39:18.559965 INFO: [APUAPC] D12_APC_2: 0x3fffff
10000 23:39:18.563796 INFO: [APUAPC] D12_APC_3: 0x0
10001 23:39:18.567334 INFO: [APUAPC] D13_APC_0: 0xffffffff
10002 23:39:18.570537 INFO: [APUAPC] D13_APC_1: 0xffffffff
10003 23:39:18.574284 INFO: [APUAPC] D13_APC_2: 0x3fffff
10004 23:39:18.577261 INFO: [APUAPC] D13_APC_3: 0x0
10005 23:39:18.580733 INFO: [APUAPC] D14_APC_0: 0xffffffff
10006 23:39:18.583320 INFO: [APUAPC] D14_APC_1: 0xffffffff
10007 23:39:18.586771 INFO: [APUAPC] D14_APC_2: 0x3fffff
10008 23:39:18.590019 INFO: [APUAPC] D14_APC_3: 0x0
10009 23:39:18.593443 INFO: [APUAPC] D15_APC_0: 0xffffffff
10010 23:39:18.596650 INFO: [APUAPC] D15_APC_1: 0xffffffff
10011 23:39:18.599833 INFO: [APUAPC] D15_APC_2: 0x3fffff
10012 23:39:18.603127 INFO: [APUAPC] D15_APC_3: 0x0
10013 23:39:18.606691 INFO: [APUAPC] APC_CON: 0x4
10014 23:39:18.609684 INFO: [NOCDAPC] D0_APC_0: 0x0
10015 23:39:18.613271 INFO: [NOCDAPC] D0_APC_1: 0x0
10016 23:39:18.616101 INFO: [NOCDAPC] D1_APC_0: 0x0
10017 23:39:18.620104 INFO: [NOCDAPC] D1_APC_1: 0xfff
10018 23:39:18.620671 INFO: [NOCDAPC] D2_APC_0: 0x0
10019 23:39:18.622828 INFO: [NOCDAPC] D2_APC_1: 0xfff
10020 23:39:18.626095 INFO: [NOCDAPC] D3_APC_0: 0x0
10021 23:39:18.629387 INFO: [NOCDAPC] D3_APC_1: 0xfff
10022 23:39:18.632788 INFO: [NOCDAPC] D4_APC_0: 0x0
10023 23:39:18.636066 INFO: [NOCDAPC] D4_APC_1: 0xfff
10024 23:39:18.639276 INFO: [NOCDAPC] D5_APC_0: 0x0
10025 23:39:18.642879 INFO: [NOCDAPC] D5_APC_1: 0xfff
10026 23:39:18.646201 INFO: [NOCDAPC] D6_APC_0: 0x0
10027 23:39:18.649038 INFO: [NOCDAPC] D6_APC_1: 0xfff
10028 23:39:18.652415 INFO: [NOCDAPC] D7_APC_0: 0x0
10029 23:39:18.652880 INFO: [NOCDAPC] D7_APC_1: 0xfff
10030 23:39:18.656125 INFO: [NOCDAPC] D8_APC_0: 0x0
10031 23:39:18.659527 INFO: [NOCDAPC] D8_APC_1: 0xfff
10032 23:39:18.662924 INFO: [NOCDAPC] D9_APC_0: 0x0
10033 23:39:18.666196 INFO: [NOCDAPC] D9_APC_1: 0xfff
10034 23:39:18.669218 INFO: [NOCDAPC] D10_APC_0: 0x0
10035 23:39:18.672456 INFO: [NOCDAPC] D10_APC_1: 0xfff
10036 23:39:18.676330 INFO: [NOCDAPC] D11_APC_0: 0x0
10037 23:39:18.679552 INFO: [NOCDAPC] D11_APC_1: 0xfff
10038 23:39:18.682791 INFO: [NOCDAPC] D12_APC_0: 0x0
10039 23:39:18.685975 INFO: [NOCDAPC] D12_APC_1: 0xfff
10040 23:39:18.689871 INFO: [NOCDAPC] D13_APC_0: 0x0
10041 23:39:18.692895 INFO: [NOCDAPC] D13_APC_1: 0xfff
10042 23:39:18.695521 INFO: [NOCDAPC] D14_APC_0: 0x0
10043 23:39:18.695998 INFO: [NOCDAPC] D14_APC_1: 0xfff
10044 23:39:18.699899 INFO: [NOCDAPC] D15_APC_0: 0x0
10045 23:39:18.702848 INFO: [NOCDAPC] D15_APC_1: 0xfff
10046 23:39:18.705756 INFO: [NOCDAPC] APC_CON: 0x4
10047 23:39:18.709221 INFO: [APUAPC] set_apusys_apc done
10048 23:39:18.712590 INFO: [DEVAPC] devapc_init done
10049 23:39:18.715951 INFO: GICv3 without legacy support detected.
10050 23:39:18.722547 INFO: ARM GICv3 driver initialized in EL3
10051 23:39:18.725986 INFO: Maximum SPI INTID supported: 639
10052 23:39:18.729023 INFO: BL31: Initializing runtime services
10053 23:39:18.735920 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10054 23:39:18.738562 INFO: SPM: enable CPC mode
10055 23:39:18.742026 INFO: mcdi ready for mcusys-off-idle and system suspend
10056 23:39:18.748673 INFO: BL31: Preparing for EL3 exit to normal world
10057 23:39:18.752226 INFO: Entry point address = 0x80000000
10058 23:39:18.752788 INFO: SPSR = 0x8
10059 23:39:18.758996
10060 23:39:18.759548
10061 23:39:18.759935
10062 23:39:18.762099 Starting depthcharge on Spherion...
10063 23:39:18.762565
10064 23:39:18.762931 Wipe memory regions:
10065 23:39:18.763324
10066 23:39:18.766072 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
10067 23:39:18.766600 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10068 23:39:18.767047 Setting prompt string to ['asurada:']
10069 23:39:18.767498 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10070 23:39:18.768208 [0x00000040000000, 0x00000054600000)
10071 23:39:18.887759
10072 23:39:18.888319 [0x00000054660000, 0x00000080000000)
10073 23:39:19.148338
10074 23:39:19.148910 [0x000000821a7280, 0x000000ffe64000)
10075 23:39:19.893016
10076 23:39:19.896468 [0x00000100000000, 0x00000240000000)
10077 23:39:21.783870
10078 23:39:21.786644 Initializing XHCI USB controller at 0x11200000.
10079 23:39:22.825383
10080 23:39:22.828506 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10081 23:39:22.828970
10082 23:39:22.829333
10083 23:39:22.829708
10084 23:39:22.830519 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10086 23:39:22.931933 asurada: tftpboot 192.168.201.1 12172444/tftp-deploy-t846xybh/kernel/image.itb 12172444/tftp-deploy-t846xybh/kernel/cmdline
10087 23:39:22.932589 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10088 23:39:22.933078 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10089 23:39:22.937819 tftpboot 192.168.201.1 12172444/tftp-deploy-t846xybh/kernel/image.ittp-deploy-t846xybh/kernel/cmdline
10090 23:39:22.938391
10091 23:39:22.938760 Waiting for link
10092 23:39:23.098194
10093 23:39:23.098753 R8152: Initializing
10094 23:39:23.099126
10095 23:39:23.101086 Version 9 (ocp_data = 6010)
10096 23:39:23.101549
10097 23:39:23.104578 R8152: Done initializing
10098 23:39:23.105170
10099 23:39:23.105546 Adding net device
10100 23:39:25.047709
10101 23:39:25.048280 done.
10102 23:39:25.048752
10103 23:39:25.049107 MAC: 00:e0:4c:78:7a:aa
10104 23:39:25.049441
10105 23:39:25.050561 Sending DHCP discover... done.
10106 23:39:25.051026
10107 23:39:25.053749 Waiting for reply... done.
10108 23:39:25.054267
10109 23:39:25.057512 Sending DHCP request... done.
10110 23:39:25.058011
10111 23:39:25.060696 Waiting for reply... done.
10112 23:39:25.061159
10113 23:39:25.061528 My ip is 192.168.201.12
10114 23:39:25.061925
10115 23:39:25.064024 The DHCP server ip is 192.168.201.1
10116 23:39:25.064671
10117 23:39:25.067312 TFTP server IP predefined by user: 192.168.201.1
10118 23:39:25.070491
10119 23:39:25.073640 Bootfile predefined by user: 12172444/tftp-deploy-t846xybh/kernel/image.itb
10120 23:39:25.078011
10121 23:39:25.078694 Sending tftp read request... done.
10122 23:39:25.079086
10123 23:39:25.086459 Waiting for the transfer...
10124 23:39:25.086926
10125 23:39:25.414361 00000000 ################################################################
10126 23:39:25.414539
10127 23:39:25.705394 00080000 ################################################################
10128 23:39:25.705543
10129 23:39:26.000006 00100000 ################################################################
10130 23:39:26.000144
10131 23:39:26.289939 00180000 ################################################################
10132 23:39:26.290092
10133 23:39:26.591165 00200000 ################################################################
10134 23:39:26.591312
10135 23:39:26.888639 00280000 ################################################################
10136 23:39:26.888809
10137 23:39:27.273428 00300000 ################################################################
10138 23:39:27.273994
10139 23:39:27.679157 00380000 ################################################################
10140 23:39:27.679301
10141 23:39:27.975647 00400000 ################################################################
10142 23:39:27.975809
10143 23:39:28.277214 00480000 ################################################################
10144 23:39:28.277384
10145 23:39:28.564859 00500000 ################################################################
10146 23:39:28.565004
10147 23:39:28.866341 00580000 ################################################################
10148 23:39:28.866504
10149 23:39:29.167776 00600000 ################################################################
10150 23:39:29.167913
10151 23:39:29.442394 00680000 ################################################################
10152 23:39:29.442535
10153 23:39:29.738368 00700000 ################################################################
10154 23:39:29.738507
10155 23:39:30.036360 00780000 ################################################################
10156 23:39:30.036521
10157 23:39:30.330784 00800000 ################################################################
10158 23:39:30.330931
10159 23:39:30.612271 00880000 ################################################################
10160 23:39:30.612416
10161 23:39:30.901725 00900000 ################################################################
10162 23:39:30.901896
10163 23:39:31.194807 00980000 ################################################################
10164 23:39:31.194946
10165 23:39:31.487035 00a00000 ################################################################
10166 23:39:31.487172
10167 23:39:31.769065 00a80000 ################################################################
10168 23:39:31.769206
10169 23:39:32.056386 00b00000 ################################################################
10170 23:39:32.056524
10171 23:39:32.354990 00b80000 ################################################################
10172 23:39:32.355134
10173 23:39:32.639194 00c00000 ################################################################
10174 23:39:32.639376
10175 23:39:32.931980 00c80000 ################################################################
10176 23:39:32.932120
10177 23:39:33.216566 00d00000 ################################################################
10178 23:39:33.216707
10179 23:39:33.505925 00d80000 ################################################################
10180 23:39:33.506068
10181 23:39:33.801486 00e00000 ################################################################
10182 23:39:33.801677
10183 23:39:34.100967 00e80000 ################################################################
10184 23:39:34.101114
10185 23:39:34.396748 00f00000 ################################################################
10186 23:39:34.396890
10187 23:39:34.683902 00f80000 ################################################################
10188 23:39:34.684053
10189 23:39:34.979219 01000000 ################################################################
10190 23:39:34.979359
10191 23:39:35.280670 01080000 ################################################################
10192 23:39:35.280813
10193 23:39:35.579252 01100000 ################################################################
10194 23:39:35.579398
10195 23:39:35.881237 01180000 ################################################################
10196 23:39:35.881380
10197 23:39:36.181720 01200000 ################################################################
10198 23:39:36.181864
10199 23:39:36.476311 01280000 ################################################################
10200 23:39:36.476451
10201 23:39:36.770017 01300000 ################################################################
10202 23:39:36.770162
10203 23:39:37.068224 01380000 ################################################################
10204 23:39:37.068360
10205 23:39:37.362883 01400000 ################################################################
10206 23:39:37.363036
10207 23:39:37.661989 01480000 ################################################################
10208 23:39:37.662135
10209 23:39:37.958971 01500000 ################################################################
10210 23:39:37.959125
10211 23:39:38.245542 01580000 ################################################################
10212 23:39:38.245691
10213 23:39:38.542199 01600000 ################################################################
10214 23:39:38.542335
10215 23:39:38.839282 01680000 ################################################################
10216 23:39:38.839451
10217 23:39:39.136380 01700000 ################################################################
10218 23:39:39.136547
10219 23:39:39.416247 01780000 ################################################################
10220 23:39:39.416413
10221 23:39:39.712977 01800000 ################################################################
10222 23:39:39.713116
10223 23:39:40.013796 01880000 ################################################################
10224 23:39:40.013933
10225 23:39:40.308994 01900000 ################################################################
10226 23:39:40.309139
10227 23:39:40.593755 01980000 ################################################################
10228 23:39:40.593892
10229 23:39:40.881056 01a00000 ################################################################
10230 23:39:40.881199
10231 23:39:41.173396 01a80000 ################################################################
10232 23:39:41.173558
10233 23:39:41.467308 01b00000 ################################################################
10234 23:39:41.467470
10235 23:39:41.500953 01b80000 ######## done.
10236 23:39:41.501039
10237 23:39:41.504196 The bootfile was 28894098 bytes long.
10238 23:39:41.504276
10239 23:39:41.508088 Sending tftp read request... done.
10240 23:39:41.508176
10241 23:39:41.511209 Waiting for the transfer...
10242 23:39:41.511303
10243 23:39:41.511378 00000000 # done.
10244 23:39:41.511448
10245 23:39:41.517925 Command line loaded dynamically from TFTP file: 12172444/tftp-deploy-t846xybh/kernel/cmdline
10246 23:39:41.518109
10247 23:39:41.540938 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12172444/extract-nfsrootfs-7o9ql60f,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10248 23:39:41.541205
10249 23:39:41.541367 Loading FIT.
10250 23:39:41.541505
10251 23:39:41.544272 Image ramdisk-1 has 17795439 bytes.
10252 23:39:41.544555
10253 23:39:41.547286 Image fdt-1 has 47278 bytes.
10254 23:39:41.547492
10255 23:39:41.551050 Image kernel-1 has 11049348 bytes.
10256 23:39:41.551382
10257 23:39:41.561048 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10258 23:39:41.561538
10259 23:39:41.577742 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10260 23:39:41.578348
10261 23:39:41.584392 Choosing best match conf-1 for compat google,spherion-rev2.
10262 23:39:41.587377
10263 23:39:41.592144 Connected to device vid:did:rid of 1ae0:0028:00
10264 23:39:41.600755
10265 23:39:41.603665 tpm_get_response: command 0x17b, return code 0x0
10266 23:39:41.604182
10267 23:39:41.606729 ec_init: CrosEC protocol v3 supported (256, 248)
10268 23:39:41.610872
10269 23:39:41.614012 tpm_cleanup: add release locality here.
10270 23:39:41.614476
10271 23:39:41.614841 Shutting down all USB controllers.
10272 23:39:41.617693
10273 23:39:41.618175 Removing current net device
10274 23:39:41.618567
10275 23:39:41.624456 Exiting depthcharge with code 4 at timestamp: 52104579
10276 23:39:41.624926
10277 23:39:41.627668 LZMA decompressing kernel-1 to 0x821a6718
10278 23:39:41.628088
10279 23:39:41.630836 LZMA decompressing kernel-1 to 0x40000000
10280 23:39:43.019408
10281 23:39:43.019970 jumping to kernel
10282 23:39:43.021677 end: 2.2.4 bootloader-commands (duration 00:00:24) [common]
10283 23:39:43.022190 start: 2.2.5 auto-login-action (timeout 00:04:01) [common]
10284 23:39:43.022603 Setting prompt string to ['Linux version [0-9]']
10285 23:39:43.022973 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10286 23:39:43.023344 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10287 23:39:43.102083
10288 23:39:43.105968 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10289 23:39:43.108843 start: 2.2.5.1 login-action (timeout 00:04:01) [common]
10290 23:39:43.109388 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10291 23:39:43.110024 Setting prompt string to []
10292 23:39:43.110491 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10293 23:39:43.110892 Using line separator: #'\n'#
10294 23:39:43.111233 No login prompt set.
10295 23:39:43.111583 Parsing kernel messages
10296 23:39:43.111896 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10297 23:39:43.112476 [login-action] Waiting for messages, (timeout 00:04:01)
10298 23:39:43.128413 [ 0.000000] Linux version 6.1.64-cip10-rt5 (KernelCI@build-j33605-arm64-gcc-10-defconfig-arm64-chromebook-7778h) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sun Dec 3 22:38:18 UTC 2023
10299 23:39:43.131894 [ 0.000000] random: crng init done
10300 23:39:43.138154 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10301 23:39:43.141708 [ 0.000000] efi: UEFI not found.
10302 23:39:43.148082 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10303 23:39:43.155007 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10304 23:39:43.165221 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10305 23:39:43.175259 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10306 23:39:43.182171 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10307 23:39:43.188189 [ 0.000000] printk: bootconsole [mtk8250] enabled
10308 23:39:43.195090 [ 0.000000] NUMA: No NUMA configuration found
10309 23:39:43.201532 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10310 23:39:43.204894 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10311 23:39:43.208423 [ 0.000000] Zone ranges:
10312 23:39:43.215093 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10313 23:39:43.218114 [ 0.000000] DMA32 empty
10314 23:39:43.225027 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10315 23:39:43.228244 [ 0.000000] Movable zone start for each node
10316 23:39:43.231707 [ 0.000000] Early memory node ranges
10317 23:39:43.238198 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10318 23:39:43.244769 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10319 23:39:43.251046 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10320 23:39:43.257990 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10321 23:39:43.264504 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10322 23:39:43.270849 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10323 23:39:43.326833 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10324 23:39:43.333334 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10325 23:39:43.339918 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10326 23:39:43.343157 [ 0.000000] psci: probing for conduit method from DT.
10327 23:39:43.349556 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10328 23:39:43.353220 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10329 23:39:43.360031 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10330 23:39:43.363477 [ 0.000000] psci: SMC Calling Convention v1.2
10331 23:39:43.370019 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10332 23:39:43.373099 [ 0.000000] Detected VIPT I-cache on CPU0
10333 23:39:43.379592 [ 0.000000] CPU features: detected: GIC system register CPU interface
10334 23:39:43.386114 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10335 23:39:43.393146 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10336 23:39:43.399877 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10337 23:39:43.406152 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10338 23:39:43.416211 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10339 23:39:43.419430 [ 0.000000] alternatives: applying boot alternatives
10340 23:39:43.426542 [ 0.000000] Fallback order for Node 0: 0
10341 23:39:43.432798 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10342 23:39:43.435684 [ 0.000000] Policy zone: Normal
10343 23:39:43.459235 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12172444/extract-nfsrootfs-7o9ql60f,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10344 23:39:43.469059 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10345 23:39:43.479300 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10346 23:39:43.489201 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10347 23:39:43.495751 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10348 23:39:43.498800 <6>[ 0.000000] software IO TLB: area num 8.
10349 23:39:43.555689 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10350 23:39:43.704270 <6>[ 0.000000] Memory: 7952180K/8385536K available (17984K kernel code, 4116K rwdata, 17316K rodata, 8448K init, 615K bss, 400588K reserved, 32768K cma-reserved)
10351 23:39:43.711299 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10352 23:39:43.717840 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10353 23:39:43.720636 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10354 23:39:43.727315 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10355 23:39:43.733883 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10356 23:39:43.737634 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10357 23:39:43.747171 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10358 23:39:43.754316 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10359 23:39:43.760627 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10360 23:39:43.767926 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10361 23:39:43.770607 <6>[ 0.000000] GICv3: 608 SPIs implemented
10362 23:39:43.774069 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10363 23:39:43.780961 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10364 23:39:43.784084 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10365 23:39:43.790609 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10366 23:39:43.803898 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10367 23:39:43.814055 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10368 23:39:43.823512 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10369 23:39:43.830901 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10370 23:39:43.844188 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10371 23:39:43.851168 <6>[ 0.000001] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10372 23:39:43.857811 <6>[ 0.009183] Console: colour dummy device 80x25
10373 23:39:43.867631 <6>[ 0.013905] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10374 23:39:43.870769 <6>[ 0.024347] pid_max: default: 32768 minimum: 301
10375 23:39:43.877739 <6>[ 0.029214] LSM: Security Framework initializing
10376 23:39:43.884148 <6>[ 0.034150] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10377 23:39:43.894373 <6>[ 0.042013] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10378 23:39:43.901813 <6>[ 0.051417] cblist_init_generic: Setting adjustable number of callback queues.
10379 23:39:43.908165 <6>[ 0.058860] cblist_init_generic: Setting shift to 3 and lim to 1.
10380 23:39:43.918063 <6>[ 0.065198] cblist_init_generic: Setting adjustable number of callback queues.
10381 23:39:43.921070 <6>[ 0.072626] cblist_init_generic: Setting shift to 3 and lim to 1.
10382 23:39:43.927660 <6>[ 0.079104] rcu: Hierarchical SRCU implementation.
10383 23:39:43.933911 <6>[ 0.079106] rcu: Max phase no-delay instances is 1000.
10384 23:39:43.940478 <6>[ 0.079131] printk: bootconsole [mtk8250] printing thread started
10385 23:39:43.947386 <6>[ 0.097458] EFI services will not be available.
10386 23:39:43.950322 <6>[ 0.097656] smp: Bringing up secondary CPUs ...
10387 23:39:43.953925 <6>[ 0.097964] Detected VIPT I-cache on CPU1
10388 23:39:43.963982 <6>[ 0.098034] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10389 23:39:43.970526 <6>[ 0.098066] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10390 23:39:43.979425 <6>[ 0.125921] Detected VIPT I-cache on CPU2
10391 23:39:43.985737 <6>[ 0.125969] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10392 23:39:43.996061 <6>[ 0.125984] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10393 23:39:43.999074 <6>[ 0.126238] Detected VIPT I-cache on CPU3
10394 23:39:44.005640 <6>[ 0.126283] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10395 23:39:44.012406 <6>[ 0.126297] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10396 23:39:44.015616 <6>[ 0.126606] CPU features: detected: Spectre-v4
10397 23:39:44.021927 <6>[ 0.126612] CPU features: detected: Spectre-BHB
10398 23:39:44.025365 <6>[ 0.126616] Detected PIPT I-cache on CPU4
10399 23:39:44.032231 <6>[ 0.126673] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10400 23:39:44.038973 <6>[ 0.126690] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10401 23:39:44.045745 <6>[ 0.126984] Detected PIPT I-cache on CPU5
10402 23:39:44.051933 <6>[ 0.127043] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10403 23:39:44.058897 <6>[ 0.127060] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10404 23:39:44.062155 <6>[ 0.127336] Detected PIPT I-cache on CPU6
10405 23:39:44.068460 <6>[ 0.127400] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10406 23:39:44.075136 <6>[ 0.127417] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10407 23:39:44.081808 <6>[ 0.127708] Detected PIPT I-cache on CPU7
10408 23:39:44.088857 <6>[ 0.127774] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10409 23:39:44.095410 <6>[ 0.127791] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10410 23:39:44.098729 <6>[ 0.127837] smp: Brought up 1 node, 8 CPUs
10411 23:39:44.104799 <6>[ 0.127841] SMP: Total of 8 processors activated.
10412 23:39:44.108331 <6>[ 0.127844] CPU features: detected: 32-bit EL0 Support
10413 23:39:44.118044 <6>[ 0.127846] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10414 23:39:44.124512 <6>[ 0.127849] CPU features: detected: Common not Private translations
10415 23:39:44.131740 <6>[ 0.127850] CPU features: detected: CRC32 instructions
10416 23:39:44.135217 <6>[ 0.127853] CPU features: detected: RCpc load-acquire (LDAPR)
10417 23:39:44.141824 <6>[ 0.127854] CPU features: detected: LSE atomic instructions
10418 23:39:44.147651 <6>[ 0.127856] CPU features: detected: Privileged Access Never
10419 23:39:44.154518 <6>[ 0.127858] CPU features: detected: RAS Extension Support
10420 23:39:44.161173 <6>[ 0.127861] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10421 23:39:44.164437 <6>[ 0.127929] CPU: All CPU(s) started at EL2
10422 23:39:44.170920 <6>[ 0.127931] alternatives: applying system-wide alternatives
10423 23:39:44.173837 <6>[ 0.141009] devtmpfs: initialized
10424 23:39:44.199703 � $$ZX.lH]XٶYHY�ies: 512 (order 0, 4096 bytes)
10425 23:39:44.206078 <6>[ 0.355583] pri<ntk: console [ttyS0] printing thread started
10426 23:39:44.209837 6>[ 0.225567] pnp: PnP ACPI: disabled
10427 23:39:44.212374 <6>[ 0.355598] printk: console [ttyS0] enabled
10428 23:39:44.219481 <6>[ 0.355602] printk: bootconsole [mtk8250] disabled
10429 23:39:44.226282 <6>[ 0.365171] printk: bootconsole [mtk8250] printing thread stopped
10430 23:39:44.229033 <6>[ 0.366145] SuperH (H)SCI(F) driver initialized
10431 23:39:44.232571 <6>[ 0.366623] msm_serial: driver initialized
10432 23:39:44.242521 <6>[ 0.371124] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10433 23:39:44.252359 <6>[ 0.371151] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10434 23:39:44.258953 <6>[ 0.371180] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10435 23:39:44.268023 <6>[ 0.371209] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10436 23:39:44.277415 <6>[ 0.371230] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10437 23:39:44.286202 <6>[ 0.371258] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10438 23:39:44.296706 <6>[ 0.371286] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10439 23:39:44.309167 <6>[ 0.371389] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10440 23:39:44.315190 <6>[ 0.371423] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10441 23:39:44.315799 <6>[ 0.378661] loop: module loaded
10442 23:39:44.322544 <6>[ 0.381253] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10443 23:39:44.330804 <4>[ 0.398053] mtk-pmic-keys: Failed to locate of_node [id: -1]
10444 23:39:44.331386 <6>[ 0.398840] megasas: 07.719.03.00-rc1
10445 23:39:44.334302 <6>[ 0.408698] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10446 23:39:44.340488 <6>[ 0.420751] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10447 23:39:44.347198 <6>[ 0.433616] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10448 23:39:44.360522 <6>[ 0.488795] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10449 23:39:44.809383 <6>[ 0.960502] Freeing initrd memory: 17372K
10450 23:39:44.817688 <6>[ 0.966600] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10451 23:39:44.824419 <6>[ 0.971233] tun: Universal TUN/TAP device driver, 1.6
10452 23:39:44.827315 <6>[ 0.971973] thunder_xcv, ver 1.0
10453 23:39:44.830940 <6>[ 0.971990] thunder_bgx, ver 1.0
10454 23:39:44.834412 <6>[ 0.972004] nicpf, ver 1.0
10455 23:39:44.841153 <6>[ 0.973044] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10456 23:39:44.847811 <6>[ 0.973048] hns3: Copyright (c) 2017 Huawei Corporation.
10457 23:39:44.850821 <6>[ 0.973072] hclge is initializing
10458 23:39:44.854524 <6>[ 0.973085] e1000: Intel(R) PRO/1000 Network Driver
10459 23:39:44.861236 <6>[ 0.973087] e1000: Copyright (c) 1999-2006 Intel Corporation.
10460 23:39:44.869075 <6>[ 0.973110] e1000e: Intel(R) PRO/1000 Network Driver
10461 23:39:44.872750 <6>[ 0.973112] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10462 23:39:44.879339 <6>[ 0.973128] igb: Intel(R) Gigabit Ethernet Network Driver
10463 23:39:44.886229 <6>[ 0.973130] igb: Copyright (c) 2007-2014 Intel Corporation.
10464 23:39:44.893641 <6>[ 0.973143] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10465 23:39:44.896599 <6>[ 0.973145] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10466 23:39:44.899997 <6>[ 0.973445] sky2: driver version 1.30
10467 23:39:44.907264 <6>[ 0.974502] VFIO - User Level meta-driver version: 0.3
10468 23:39:44.913724 <6>[ 0.977320] usbcore: registered new interface driver usb-storage
10469 23:39:44.920483 <6>[ 0.977499] usbcore: registered new device driver onboard-usb-hub
10470 23:39:44.924053 <6>[ 0.980238] mt6397-rtc mt6359-rtc: registered as rtc0
10471 23:39:44.933377 <6>[ 0.980391] mt6397-rtc mt6359-rtc: setting system clock to 2023-12-03T23:37:30 UTC (1701646650)
10472 23:39:44.936989 <6>[ 0.981000] i2c_dev: i2c /dev entries driver
10473 23:39:44.947064 <6>[ 0.988062] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10474 23:39:44.950079 <6>[ 1.003030] cpu cpu0: EM: created perf domain
10475 23:39:44.953338 <6>[ 1.003355] cpu cpu4: EM: created perf domain
10476 23:39:44.960539 <6>[ 1.007533] sdhci: Secure Digital Host Controller Interface driver
10477 23:39:44.967032 <6>[ 1.007534] sdhci: Copyright(c) Pierre Ossman
10478 23:39:44.973609 <6>[ 1.007897] Synopsys Designware Multimedia Card Interface Driver
10479 23:39:44.977087 <6>[ 1.008278] sdhci-pltfm: SDHCI platform and OF driver helper
10480 23:39:44.983571 <6>[ 1.012537] ledtrig-cpu: registered to indicate activity on CPUs
10481 23:39:44.986619 <6>[ 1.013171] mmc0: CQHCI version 5.10
10482 23:39:44.996802 <6>[ 1.013197] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10483 23:39:45.000782 <6>[ 1.013481] usbcore: registered new interface driver usbhid
10484 23:39:45.003546 <6>[ 1.013483] usbhid: USB HID core driver
10485 23:39:45.013908 <6>[ 1.013615] spi_master spi0: will run message pump with realtime priority
10486 23:39:45.023832 <6>[ 1.046844] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10487 23:39:45.037375 <6>[ 1.048909] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10488 23:39:45.043684 <6>[ 1.049868] cros-ec-spi spi0.0: Chrome EC device registered
10489 23:39:45.053235 <6>[ 1.070141] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10490 23:39:45.057119 <6>[ 1.072497] NET: Registered PF_PACKET protocol family
10491 23:39:45.063985 <6>[ 1.072595] 9pnet: Installing 9P2000 support
10492 23:39:45.067110 <5>[ 1.072637] Key type dns_resolver registered
10493 23:39:45.073735 <6>[ 1.072973] registered taskstats version 1
10494 23:39:45.076769 <5>[ 1.072998] Loading compiled-in X.509 certificates
10495 23:39:45.086733 <4>[ 1.088579] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10496 23:39:45.096602 <4>[ 1.088773] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10497 23:39:45.103669 <3>[ 1.088787] debugfs: File 'uA_load' in directory '/' already present!
10498 23:39:45.110195 <3>[ 1.088796] debugfs: File 'min_uV' in directory '/' already present!
10499 23:39:45.117138 <3>[ 1.088800] debugfs: File 'max_uV' in directory '/' already present!
10500 23:39:45.126700 <3>[ 1.088805] debugfs: File 'constraint_flags' in directory '/' already present!
10501 23:39:45.133339 <3>[ 1.092313] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10502 23:39:45.140178 <6>[ 1.104222] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10503 23:39:45.146649 <6>[ 1.104827] xhci-mtk 11200000.usb: xHCI Host Controller
10504 23:39:45.153404 <6>[ 1.104849] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10505 23:39:45.163093 <6>[ 1.105071] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10506 23:39:45.169845 <6>[ 1.105116] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10507 23:39:45.173229 <6>[ 1.105205] xhci-mtk 11200000.usb: xHCI Host Controller
10508 23:39:45.183067 <6>[ 1.105213] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10509 23:39:45.189776 <6>[ 1.105221] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10510 23:39:45.192816 <6>[ 1.105743] hub 1-0:1.0: USB hub found
10511 23:39:45.196809 <6>[ 1.105763] hub 1-0:1.0: 1 port detected
10512 23:39:45.206605 <6>[ 1.106016] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10513 23:39:45.210160 <6>[ 1.106335] hub 2-0:1.0: USB hub found
10514 23:39:45.213267 <6>[ 1.106352] hub 2-0:1.0: 1 port detected
10515 23:39:45.217193 <6>[ 1.107447] mmc0: Command Queue Engine enabled
10516 23:39:45.223396 <6>[ 1.107459] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10517 23:39:45.230435 <6>[ 1.107944] mmcblk0: mmc0:0001 DA4128 116 GiB
10518 23:39:45.233625 <6>[ 1.110360] mtk-msdc 11f70000.mmc: Got CD GPIO
10519 23:39:45.240608 <6>[ 1.111566] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10520 23:39:45.246482 <6>[ 1.112983] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10521 23:39:45.249926 <6>[ 1.114135] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10522 23:39:45.256994 <6>[ 1.114911] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10523 23:39:45.266475 <6>[ 1.127651] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10524 23:39:45.273309 <6>[ 1.127660] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10525 23:39:45.283108 <4>[ 1.127804] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10526 23:39:45.289884 <6>[ 1.128436] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10527 23:39:45.296474 <6>[ 1.128439] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10528 23:39:45.306431 <6>[ 1.128566] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10529 23:39:45.313568 <6>[ 1.128577] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10530 23:39:45.322918 <6>[ 1.128581] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10531 23:39:45.330065 <6>[ 1.128586] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10532 23:39:45.339947 <6>[ 1.130174] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10533 23:39:45.346852 <6>[ 1.130192] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10534 23:39:45.356562 <6>[ 1.130198] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10535 23:39:45.362916 <6>[ 1.130205] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10536 23:39:45.373571 <6>[ 1.130212] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10537 23:39:45.379666 <6>[ 1.130218] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10538 23:39:45.389392 <6>[ 1.130224] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10539 23:39:45.396042 <6>[ 1.130230] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10540 23:39:45.405854 <6>[ 1.130237] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10541 23:39:45.412996 <6>[ 1.130243] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10542 23:39:45.422443 <6>[ 1.130250] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10543 23:39:45.429068 <6>[ 1.130256] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10544 23:39:45.438963 <6>[ 1.130267] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10545 23:39:45.445900 <6>[ 1.130274] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10546 23:39:45.455292 <6>[ 1.130280] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10547 23:39:45.462305 <6>[ 1.130806] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10548 23:39:45.468947 <6>[ 1.131685] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10549 23:39:45.475012 <6>[ 1.132234] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10550 23:39:45.482446 <6>[ 1.132841] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10551 23:39:45.488148 <6>[ 1.133500] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10552 23:39:45.498505 <6>[ 1.133694] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10553 23:39:45.505169 <6>[ 1.133706] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10554 23:39:45.515294 <6>[ 1.133712] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10555 23:39:45.525201 <6>[ 1.133717] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10556 23:39:45.535211 <6>[ 1.133723] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10557 23:39:45.544711 <6>[ 1.133728] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10558 23:39:45.554497 <6>[ 1.133734] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10559 23:39:45.560951 <6>[ 1.133738] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10560 23:39:45.571259 <6>[ 1.133743] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10561 23:39:45.581317 <6>[ 1.133750] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10562 23:39:45.590949 <6>[ 1.133755] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10563 23:39:45.601161 <6>[ 1.134619] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10564 23:39:45.607654 <6>[ 1.142076] Trying to probe devices needed for running init ...
10565 23:39:45.614541 <6>[ 1.533473] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10566 23:39:45.617744 <6>[ 1.693555] hub 1-1:1.0: USB hub found
10567 23:39:45.621288 <6>[ 1.693956] hub 1-1:1.0: 4 ports detected
10568 23:39:45.624383 <6>[ 1.696732] hub 1-1:1.0: USB hub found
10569 23:39:45.630991 <6>[ 1.696994] hub 1-1:1.0: 4 ports detected
10570 23:39:45.672901 <6>[ 1.817599] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10571 23:39:45.693651 <6>[ 1.842205] hub 2-1:1.0: USB hub found
10572 23:39:45.696934 <6>[ 1.842591] hub 2-1:1.0: 3 ports detected
10573 23:39:45.700138 <6>[ 1.845109] hub 2-1:1.0: USB hub found
10574 23:39:45.703453 <6>[ 1.845525] hub 2-1:1.0: 3 ports detected
10575 23:39:45.864685 <6>[ 2.009636] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10576 23:39:45.985516 <6>[ 2.136890] hub 1-1.4:1.0: USB hub found
10577 23:39:45.988958 <6>[ 2.137238] hub 1-1.4:1.0: 2 ports detected
10578 23:39:45.991917 <6>[ 2.140867] hub 1-1.4:1.0: USB hub found
10579 23:39:45.999041 <6>[ 2.141211] hub 1-1.4:1.0: 2 ports detected
10580 23:39:46.068911 <6>[ 2.213728] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10581 23:39:46.284916 <6>[ 2.429607] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10582 23:39:46.468929 <6>[ 2.613623] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10583 23:39:57.288969 <6>[ 13.442595] ALSA device list:
10584 23:39:57.295889 <6>[ 13.442617] No soundcards found.
10585 23:39:57.298627 <6>[ 13.446961] Freeing unused kernel memory: 8448K
10586 23:39:57.302462 <6>[ 13.447045] Run /init as init process
10587 23:39:57.305754 Loading, please wait...
10588 23:39:57.325555 Starting version 247.3-7+deb11u2
10589 23:39:57.511810 <6>[ 13.660578] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10590 23:39:57.518182 <6>[ 13.660638] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10591 23:39:57.528077 <6>[ 13.660647] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10592 23:39:57.534952 <6>[ 13.660696] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10593 23:39:57.541164 <6>[ 13.665252] remoteproc remoteproc0: scp is available
10594 23:39:57.544769 <6>[ 13.665723] remoteproc remoteproc0: powering up scp
10595 23:39:57.554644 <6>[ 13.665751] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10596 23:39:57.561474 <6>[ 13.665830] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10597 23:39:57.575584 <3>[ 13.721359] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10598 23:39:57.582183 <3>[ 13.721399] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10599 23:39:57.592715 <3>[ 13.721407] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10600 23:39:57.598972 <6>[ 13.722517] usbcore: registered new interface driver r8152
10601 23:39:57.605843 <3>[ 13.722740] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10602 23:39:57.612172 <3>[ 13.722774] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10603 23:39:57.622877 <3>[ 13.722785] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10604 23:39:57.629412 <3>[ 13.722800] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10605 23:39:57.636607 <3>[ 13.722809] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10606 23:39:57.646209 <3>[ 13.723249] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10607 23:39:57.652990 <3>[ 13.723309] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10608 23:39:57.663371 <3>[ 13.723314] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10609 23:39:57.670157 <3>[ 13.723317] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10610 23:39:57.676477 <3>[ 13.730257] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10611 23:39:57.686556 <3>[ 13.730281] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10612 23:39:57.693383 <3>[ 13.730289] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10613 23:39:57.703068 <3>[ 13.730298] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10614 23:39:57.709939 <3>[ 13.730318] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10615 23:39:57.719269 <3>[ 13.730408] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10616 23:39:57.726586 <6>[ 13.734022] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10617 23:39:57.729453 <6>[ 13.742332] mc: Linux media interface: v0.10
10618 23:39:57.739818 <4>[ 13.742398] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10619 23:39:57.746057 <4>[ 13.744112] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10620 23:39:57.752769 <4>[ 13.760329] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10621 23:39:57.759594 <4>[ 13.760329] Fallback method does not support PEC.
10622 23:39:57.765694 <6>[ 13.789171] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10623 23:39:57.772868 <6>[ 13.789182] pci_bus 0000:00: root bus resource [bus 00-ff]
10624 23:39:57.779171 <6>[ 13.789188] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10625 23:39:57.788926 <6>[ 13.789190] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10626 23:39:57.795636 <6>[ 13.789219] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10627 23:39:57.802419 <6>[ 13.789232] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10628 23:39:57.805895 <6>[ 13.789304] pci 0000:00:00.0: supports D1 D2
10629 23:39:57.812393 <6>[ 13.789306] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10630 23:39:57.821978 <3>[ 13.790670] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10631 23:39:57.829145 <6>[ 13.791210] videodev: Linux video capture interface: v2.00
10632 23:39:57.836139 <6>[ 13.791605] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10633 23:39:57.842494 <6>[ 13.791612] remoteproc remoteproc0: remote processor scp is now up
10634 23:39:57.848634 <6>[ 13.791614] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10635 23:39:57.858847 <6>[ 13.791984] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10636 23:39:57.865205 <6>[ 13.794288] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10637 23:39:57.871881 <6>[ 13.794328] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10638 23:39:57.878292 <6>[ 13.794357] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10639 23:39:57.888738 <6>[ 13.794376] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10640 23:39:57.891475 <6>[ 13.794531] pci 0000:01:00.0: supports D1 D2
10641 23:39:57.898579 <6>[ 13.794535] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10642 23:39:57.901808 <6>[ 13.798122] Bluetooth: Core ver 2.22
10643 23:39:57.908486 <6>[ 13.798287] NET: Registered PF_BLUETOOTH protocol family
10644 23:39:57.915174 <6>[ 13.798292] Bluetooth: HCI device and connection manager initialized
10645 23:39:57.917970 <6>[ 13.798315] Bluetooth: HCI socket layer initialized
10646 23:39:57.924916 <6>[ 13.798322] Bluetooth: L2CAP socket layer initialized
10647 23:39:57.931909 <6>[ 13.798338] Bluetooth: SCO socket layer initialized
10648 23:39:57.938498 <6>[ 13.805841] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10649 23:39:57.944653 <6>[ 13.805915] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10650 23:39:57.951317 <6>[ 13.805922] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10651 23:39:57.961292 <6>[ 13.805938] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10652 23:39:57.968082 <6>[ 13.805954] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10653 23:39:57.977491 <6>[ 13.805970] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10654 23:39:57.981228 <6>[ 13.805986] pci 0000:00:00.0: PCI bridge to [bus 01]
10655 23:39:57.991305 <6>[ 13.805995] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10656 23:39:57.997809 <6>[ 13.806598] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10657 23:39:58.004323 <3>[ 13.816358] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10658 23:39:58.010996 <6>[ 13.817742] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10659 23:39:58.017675 <6>[ 13.818113] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10660 23:39:58.027660 <6>[ 13.853564] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10661 23:39:58.033734 <6>[ 13.853700] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10662 23:39:58.043866 <6>[ 13.855364] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10663 23:39:58.051009 <6>[ 13.857518] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10664 23:39:58.060734 <4>[ 13.880883] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10665 23:39:58.067237 <4>[ 13.880894] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10666 23:39:58.077129 <6>[ 13.910158] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10667 23:39:58.087339 <6>[ 13.910468] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10668 23:39:58.093634 <6>[ 13.925036] usbcore: registered new interface driver cdc_ether
10669 23:39:58.100467 <5>[ 13.932293] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10670 23:39:58.103553 <6>[ 13.938485] r8152 2-1.3:1.0 eth0: v1.12.13
10671 23:39:58.110009 <6>[ 13.938892] usbcore: registered new interface driver r8153_ecm
10672 23:39:58.116871 <5>[ 13.943148] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10673 23:39:58.126589 <4>[ 13.943211] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10674 23:39:58.130162 <6>[ 13.943218] cfg80211: failed to load regulatory.db
10675 23:39:58.137066 <6>[ 13.948416] r8152 2-1.3:1.0 enx00e04c787aaa: renamed from eth0
10676 23:39:58.143264 <6>[ 13.982697] usbcore: registered new interface driver btusb
10677 23:39:58.150283 <6>[ 13.983362] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10678 23:39:58.159826 <4>[ 13.983920] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10679 23:39:58.166361 <3>[ 13.983929] Bluetooth: hci0: Failed to load firmware file (-2)
10680 23:39:58.172956 <3>[ 13.983931] Bluetooth: hci0: Failed to set up firmware (-2)
10681 23:39:58.182757 <4>[ 13.983933] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10682 23:39:58.196527 <6>[ 13.984663] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10683 23:39:58.202971 <6>[ 13.984802] usbcore: registered new interface driver uvcvideo
10684 23:39:58.209381 <6>[ 14.017081] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10685 23:39:58.215860 <6>[ 14.289503] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10686 23:39:58.222494 <6>[ 14.289627] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10687 23:39:58.225368 <6>[ 14.309499] mt7921e 0000:01:00.0: ASIC revision: 79610010
10688 23:39:58.258723 <4>[ 14.404490] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10689 23:39:58.262112 Begin: Loading essential drivers ... done.
10690 23:39:58.265275 Begin: Running /scripts/init-premount ... done.
10691 23:39:58.275255 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10692 23:39:58.281821 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10693 23:39:58.285012 Device /sys/class/net/enx00e04c787aaa found
10694 23:39:58.288264 done.
10695 23:39:58.327248 IP-Config: enx00e04c787aaa hardware address 00:e0:4c:78:7a:aa mtu 1500 DHCP
10696 23:39:58.370784 <4>[ 14.516170] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10697 23:39:58.478997 <4>[ 14.622757] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10698 23:39:58.582998 <4>[ 14.726626] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10699 23:39:58.687299 <4>[ 14.830515] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10700 23:39:58.790830 <4>[ 14.934661] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10701 23:39:58.894966 <4>[ 15.038536] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10702 23:39:58.998844 <4>[ 15.142658] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10703 23:39:59.102687 <4>[ 15.246576] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10704 23:39:59.206481 <4>[ 15.350504] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10705 23:39:59.299976 <3>[ 15.452344] mt7921e 0000:01:00.0: hardware init failed
10706 23:39:59.424233 <6>[ 15.574334] r8152 2-1.3:1.0 enx00e04c787aaa: carrier on
10707 23:40:00.326559 IP-Config: no response after 2 secs - giving up
10708 23:40:00.359492 IP-Config: enx00e04c787aaa hardware address 00:e0:4c:78:7a:aa mtu 1500 DHCP
10709 23:40:00.365786 IP-Config: enx00e04c787aaa complete (dhcp from 192.168.201.1):
10710 23:40:00.372181 address: 192.168.201.12 broadcast: 192.168.201.255 netmask: 255.255.255.0
10711 23:40:00.379328 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10712 23:40:00.385842 host : mt8192-asurada-spherion-r0-cbg-0
10713 23:40:00.392286 domain : lava-rack
10714 23:40:00.395173 rootserver: 192.168.201.1 rootpath:
10715 23:40:00.395256 filename :
10716 23:40:00.483511 done.
10717 23:40:00.490597 Begin: Running /scripts/nfs-bottom ... done.
10718 23:40:00.507156 Begin: Running /scripts/init-bottom ... done.
10719 23:40:01.723737 <6>[ 17.877207] NET: Registered PF_INET6 protocol family
10720 23:40:01.731438 <6>[ 17.884066] Segment Routing with IPv6
10721 23:40:01.735141 <6>[ 17.884087] In-situ OAM (IOAM) with IPv6
10722 23:40:01.859655 <30>[ 17.992400] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10723 23:40:01.862828 <30>[ 17.993480] systemd[1]: Detected architecture arm64.
10724 23:40:01.883654
10725 23:40:01.886313 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10726 23:40:01.886804
10727 23:40:01.903906 <30>[ 18.056318] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10728 23:40:02.739294 <30>[ 18.888089] systemd[1]: Queued start job for default target Graphical Interface.
10729 23:40:02.770028 [[0;32m OK [<30>[ 18.920004] systemd[1]: Created slice system-getty.slice.
10730 23:40:02.772981 0m] Created slice [0;1;39msystem-getty.slice[0m.
10731 23:40:02.792698 [[0;32m OK [0m] Created slic<30>[ 18.942921] systemd[1]: Created slice system-modprobe.slice.
10732 23:40:02.795897 e [0;1;39msystem-modprobe.slice[0m.
10733 23:40:02.816715 [[0;32m OK [0m] Created slic<30>[ 18.966810] systemd[1]: Created slice system-serial\x2dgetty.slice.
10734 23:40:02.822950 e [0;1;39msystem-serial\x2dgetty.slice[0m.
10735 23:40:02.841405 [[0;32m OK [0m] Created slic<30>[ 18.991468] systemd[1]: Created slice User and Session Slice.
10736 23:40:02.844769 e [0;1;39mUser and Session Slice[0m.
10737 23:40:02.867605 [[0;32m OK [0m] Started [0;<30>[ 19.014435] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10738 23:40:02.871103 1;39mDispatch Password …ts to Console Directory Watch[0m.
10739 23:40:02.895628 [[0;32m OK [0m] Started [0;<30>[ 19.042401] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10740 23:40:02.898984 1;39mForward Password R…uests to Wall Directory Watch[0m.
10741 23:40:02.927204 [[0;32m OK [0m] Reached targ<30>[ 19.070161] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10742 23:40:02.933768 <30>[ 19.070440] systemd[1]: Reached target Local Encrypted Volumes.
10743 23:40:02.936958 et [0;1;39mLocal Encrypted Volumes[0m.
10744 23:40:02.955689 [[0;32m OK [0m] Reached target [0;1;39mPath<30>[ 19.105726] systemd[1]: Reached target Paths.
10745 23:40:02.956257 s[0m.
10746 23:40:02.978422 [[0;32m OK [0m] Reached target [0;1;39mRemo<30>[ 19.125595] systemd[1]: Reached target Remote File Systems.
10747 23:40:02.978992 te File Systems[0m.
10748 23:40:02.999991 [[0;32m OK [0m] Reached target [0;1;39mSlic<30>[ 19.149977] systemd[1]: Reached target Slices.
10749 23:40:03.000567 es[0m.
10750 23:40:03.019833 [[0;32m OK [0m] Reached target [0;1;39mSwap<30>[ 19.169704] systemd[1]: Reached target Swap.
10751 23:40:03.020405 [0m.
10752 23:40:03.043114 [[0;32m OK [0m] Listening on [0;1;39minitct<30>[ 19.190081] systemd[1]: Listening on initctl Compatibility Named Pipe.
10753 23:40:03.046049 l Compatibility Named Pipe[0m.
10754 23:40:03.056093 [[0;32m OK [0m] Listening on [0;1;39mJourna<30>[ 19.206235] systemd[1]: Listening on Journal Audit Socket.
10755 23:40:03.059473 l Audit Socket[0m.
10756 23:40:03.080326 [[0;32m OK [0m] Listening on<30>[ 19.230928] systemd[1]: Listening on Journal Socket (/dev/log).
10757 23:40:03.083812 [0;1;39mJournal Socket (/dev/log)[0m.
10758 23:40:03.104713 [[0;32m OK [0m] Listening on<30>[ 19.254854] systemd[1]: Listening on Journal Socket.
10759 23:40:03.107827 [0;1;39mJournal Socket[0m.
10760 23:40:03.125047 [[0;32m OK [0m] Listening on<30>[ 19.275310] systemd[1]: Listening on Network Service Netlink Socket.
10761 23:40:03.131477 [0;1;39mNetwork Service Netlink Socket[0m.
10762 23:40:03.151066 [[0;32m OK [0m] Listening on [0;1;39mudev C<30>[ 19.301476] systemd[1]: Listening on udev Control Socket.
10763 23:40:03.154590 ontrol Socket[0m.
10764 23:40:03.171672 [[0;32m OK [0m] Listening on [0;1;39mudev K<30>[ 19.322092] systemd[1]: Listening on udev Kernel Socket.
10765 23:40:03.175481 ernel Socket[0m.
10766 23:40:03.230861 Mounting [0;1;39mHuge Pages File Syste<30>[ 19.378114] systemd[1]: Mounting Huge Pages File System...
10767 23:40:03.231418 m[0m...
10768 23:40:03.249612 Mounting [0;1;39mPOSIX<30>[ 19.399755] systemd[1]: Mounting POSIX Message Queue File System...
10769 23:40:03.252482 Message Queue File System[0m...
10770 23:40:03.279331 Mounting [0;1;39mKernel Debug File Sys<30>[ 19.425929] systemd[1]: Mounting Kernel Debug File System...
10771 23:40:03.279818 tem[0m...
10772 23:40:03.298089 <30>[ 19.446073] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10773 23:40:03.308191 <30>[ 19.452311] systemd[1]: Starting Create list of static device nodes for the current kernel...
10774 23:40:03.314767 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10775 23:40:03.339687 Starting [0;1;39mLoad <30>[ 19.490375] systemd[1]: Starting Load Kernel Module configfs...
10776 23:40:03.342963 Kernel Module configfs[0m...
10777 23:40:03.364307 Starting [0;1;39mLoad <30>[ 19.514490] systemd[1]: Starting Load Kernel Module drm...
10778 23:40:03.367429 Kernel Module drm[0m...
10779 23:40:03.388021 Starting [0;1;39mLoad <30>[ 19.538279] systemd[1]: Starting Load Kernel Module fuse...
10780 23:40:03.391213 Kernel Module fuse[0m...
10781 23:40:03.424143 <6>[ 19.575931] fuse: init (API version 7.37)
10782 23:40:03.433088 <30>[ 19.576831] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10783 23:40:03.476265 Starting [0;1;39mJourn<30>[ 19.626456] systemd[1]: Starting Journal Service...
10784 23:40:03.476793 al Service[0m...
10785 23:40:03.506158 Startin<30>[ 19.656610] systemd[1]: Starting Load Kernel Modules...
10786 23:40:03.509300 g [0;1;39mLoad Kernel Modules[0m...
10787 23:40:03.531912 Starting [0;1;39mRemou<30>[ 19.682620] systemd[1]: Starting Remount Root and Kernel File Systems...
10788 23:40:03.538863 nt Root and Kernel File Systems[0m...
10789 23:40:03.558155 Startin<30>[ 19.708398] systemd[1]: Starting Coldplug All udev Devices...
10790 23:40:03.561264 g [0;1;39mColdplug All udev Devices[0m...
10791 23:40:03.592047 [[0;32m OK [0m] Mounted [0;<30>[ 19.742489] systemd[1]: Mounted Huge Pages File System.
10792 23:40:03.595101 1;39mHuge Pages File System[0m.
10793 23:40:03.614551 <3>[ 19.764369] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10794 23:40:03.624635 [[0;32m OK [0m] Mounted [0;<30>[ 19.774849] systemd[1]: Mounted POSIX Message Queue File System.
10795 23:40:03.628028 1;39mPOSIX Message Queue File System[0m.
10796 23:40:03.650788 [[0;32m OK [0m] Mounted [0;1;39mKernel Debu<3>[ 19.797604] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10797 23:40:03.657558 g File System[0<30>[ 19.797794] systemd[1]: Mounted Kernel Debug File System.
10798 23:40:03.661014 m.
10799 23:40:03.683810 [[0;32m OK [0m] Finished [0;1;39mCreate lis<30>[ 19.830360] systemd[1]: Finished Create list of static device nodes for the current kernel.
10800 23:40:03.693547 t of st… nodes<3>[ 19.832027] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10801 23:40:03.696488 for the current kernel[0m.
10802 23:40:03.714686 <3>[ 19.862501] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10803 23:40:03.722310 <30>[ 19.866397] systemd[1]: modprobe@configfs.service: Succeeded.
10804 23:40:03.729135 <30>[ 19.867096] systemd[1]: Finished Load Kernel Module configfs.
10805 23:40:03.742399 [[0;32m OK [0m] Finished [0;1;39mLoad Kerne<3>[ 19.887896] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10806 23:40:03.743078 l Module configfs[0m.
10807 23:40:03.759113 <3>[ 19.908798] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10808 23:40:03.766171 <30>[ 19.910889] systemd[1]: modprobe@drm.service: Succeeded.
10809 23:40:03.773024 [[0;32m OK [0m] Finished [0<30>[ 19.911724] systemd[1]: Finished Load Kernel Module drm.
10810 23:40:03.782875 ;1;39mLoad Kerne<3>[ 19.929076] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10811 23:40:03.785736 l Module drm[0m.
10812 23:40:03.805460 [[0;32m OK [0m] Finished [0<30>[ 19.954457] systemd[1]: modprobe@fuse.service: Succeeded.
10813 23:40:03.811833 ;1;39mLoad Kerne<30>[ 19.955080] systemd[1]: Finished Load Kernel Module fuse.
10814 23:40:03.822577 <3>[ 19.959452] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10815 23:40:03.823145 l Module fuse[0m.
10816 23:40:03.838831 <3>[ 19.989242] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10817 23:40:03.849087 [[0;32m OK [0m] Finished [0<30>[ 19.999223] systemd[1]: Finished Load Kernel Modules.
10818 23:40:03.852451 ;1;39mLoad Kernel Modules[0m.
10819 23:40:03.863485 <3>[ 20.011043] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10820 23:40:03.873796 [[0;32m OK [0m] Finished [0<30>[ 20.023766] systemd[1]: Finished Remount Root and Kernel File Systems.
10821 23:40:03.880252 ;1;39mRemount Root and Kernel File Systems[0m.
10822 23:40:03.932360 [[0;32m OK [0m] Started [0;<30>[ 20.083134] systemd[1]: Started Journal Service.
10823 23:40:03.935812 1;39mJournal Service[0m.
10824 23:40:03.957538 Mounting [0;1;39mFUSE Control File System[0m...
10825 23:40:03.978216 Mounting [0;1;39mKernel Configuration File System[0m...
10826 23:40:04.006240 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10827 23:40:04.030904 Starting [0;1;39mLoad/Save Random Seed[0m...
10828 23:40:04.061147 Starting [0;1;39mApply<46>[ 20.209696] systemd-journald[304]: Received client request to flush runtime journal.
10829 23:40:04.061643 Kernel Variables[0m...
10830 23:40:04.093708 <4>[ 20.234387] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10831 23:40:04.119004 <3>[ 20.234406] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10832 23:40:04.125635 Starting [0;1;39mCreate System Users[0m...
10833 23:40:04.158031 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10834 23:40:04.172257 See 'systemctl status systemd-udev-trigger.service' for details.
10835 23:40:04.188479 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10836 23:40:04.204056 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10837 23:40:04.221510 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10838 23:40:04.840141 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10839 23:40:05.492265 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10840 23:40:05.536972 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10841 23:40:05.592820 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10842 23:40:05.682730 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10843 23:40:05.700480 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10844 23:40:05.720619 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10845 23:40:05.776147 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10846 23:40:05.802629 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10847 23:40:05.946583 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10848 23:40:05.989116 Starting [0;1;39mNetwork Service[0m...
10849 23:40:06.088537 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10850 23:40:06.157891 Starting [0;1;39mNetwork Time Synchronization[0m...
10851 23:40:06.178814 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10852 23:40:06.327996 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10853 23:40:06.355435 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10854 23:40:06.399297 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10855 23:40:06.639850 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10856 23:40:06.658505 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10857 23:40:06.727721 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10858 23:40:06.744748 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10859 23:40:06.769232 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10860 23:40:06.787953 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10861 23:40:06.856317 Starting [0;1;39mNetwork Name Resolution[0m...
10862 23:40:06.872602 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10863 23:40:06.893420 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10864 23:40:06.913437 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10865 23:40:06.934457 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10866 23:40:06.951190 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10867 23:40:06.971028 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10868 23:40:07.008253 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10869 23:40:07.037066 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10870 23:40:07.069519 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10871 23:40:07.099218 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10872 23:40:07.111964 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10873 23:40:07.141461 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10874 23:40:07.156111 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10875 23:40:07.172174 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10876 23:40:07.228624 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10877 23:40:07.379807 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
10878 23:40:07.488423 Starting [0;1;39mUser Login Management[0m...
10879 23:40:07.683466 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10880 23:40:07.703257 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10881 23:40:07.726318 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10882 23:40:07.780227 Starting [0;1;39mPermit User Sessions[0m...
10883 23:40:07.816073 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
10884 23:40:07.840097 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10885 23:40:07.860251 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10886 23:40:07.913674 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10887 23:40:07.941561 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10888 23:40:07.959809 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10889 23:40:07.975168 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10890 23:40:07.991940 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10891 23:40:08.045703 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10892 23:40:08.089506 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10893 23:40:08.162331
10894 23:40:08.162490
10895 23:40:08.165156 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10896 23:40:08.165239
10897 23:40:08.168787 debian-bullseye-arm64 login: root (automatic login)
10898 23:40:08.168883
10899 23:40:08.168953
10900 23:40:08.521535 Linux debian-bullseye-arm64 6.1.64-cip10-rt5 #1 SMP PREEMPT Sun Dec 3 22:38:18 UTC 2023 aarch64
10901 23:40:08.522066
10902 23:40:08.527882 The programs included with the Debian GNU/Linux system are free software;
10903 23:40:08.534211 the exact distribution terms for each program are described in the
10904 23:40:08.537680 individual files in /usr/share/doc/*/copyright.
10905 23:40:08.538210
10906 23:40:08.544164 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10907 23:40:08.547468 permitted by applicable law.
10908 23:40:09.470425 Matched prompt #10: / #
10910 23:40:09.471586 Setting prompt string to ['/ #']
10911 23:40:09.472023 end: 2.2.5.1 login-action (duration 00:00:26) [common]
10913 23:40:09.473003 end: 2.2.5 auto-login-action (duration 00:00:26) [common]
10914 23:40:09.473458 start: 2.2.6 expect-shell-connection (timeout 00:03:35) [common]
10915 23:40:09.473851 Setting prompt string to ['/ #']
10916 23:40:09.474171 Forcing a shell prompt, looking for ['/ #']
10918 23:40:09.524990 / #
10919 23:40:09.525710 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10920 23:40:09.526207 Waiting using forced prompt support (timeout 00:02:30)
10921 23:40:09.531212
10922 23:40:09.532208 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10923 23:40:09.532752 start: 2.2.7 export-device-env (timeout 00:03:35) [common]
10925 23:40:09.634137 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12172444/extract-nfsrootfs-7o9ql60f'
10926 23:40:09.640511 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12172444/extract-nfsrootfs-7o9ql60f'
10928 23:40:09.742191 / # export NFS_SERVER_IP='192.168.201.1'
10929 23:40:09.748969 export NFS_SERVER_IP='192.168.201.1'
10930 23:40:09.749914 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10931 23:40:09.750474 end: 2.2 depthcharge-retry (duration 00:01:26) [common]
10932 23:40:09.750982 end: 2 depthcharge-action (duration 00:01:26) [common]
10933 23:40:09.751490 start: 3 lava-test-retry (timeout 00:07:56) [common]
10934 23:40:09.751986 start: 3.1 lava-test-shell (timeout 00:07:56) [common]
10935 23:40:09.752413 Using namespace: common
10937 23:40:09.853539 / # #
10938 23:40:09.854227 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
10939 23:40:09.860577 #
10940 23:40:09.861462 Using /lava-12172444
10942 23:40:09.962812 / # export SHELL=/bin/bash
10943 23:40:09.969208 export SHELL=/bin/bash
10945 23:40:10.071049 / # . /lava-12172444/environment
10946 23:40:10.077682 . /lava-12172444/environment
10948 23:40:10.185177 / # /lava-12172444/bin/lava-test-runner /lava-12172444/0
10949 23:40:10.185905 Test shell timeout: 10s (minimum of the action and connection timeout)
10950 23:40:10.192012 /lava-12172444/bin/lava-test-runner /lava-12172444/0
10951 23:40:10.489533 + export TESTRUN_ID=0_timesync-off
10952 23:40:10.492940 + TESTRUN_ID=0_timesync-off
10953 23:40:10.496478 + cd /lava-12172444/0/tests/0_timesync-off
10954 23:40:10.499776 ++ cat uuid
10955 23:40:10.505738 + UUID=12172444_1.6.2.3.1
10956 23:40:10.506167 + set +x
10957 23:40:10.512636 <LAVA_SIGNAL_STARTRUN 0_timesync-off 12172444_1.6.2.3.1>
10958 23:40:10.513326 Received signal: <STARTRUN> 0_timesync-off 12172444_1.6.2.3.1
10959 23:40:10.513795 Starting test lava.0_timesync-off (12172444_1.6.2.3.1)
10960 23:40:10.514591 Skipping test definition patterns.
10961 23:40:10.516077 + systemctl stop systemd-timesyncd
10962 23:40:10.580648 + set +x
10963 23:40:10.583309 <LAVA_SIGNAL_ENDRUN 0_timesync-off 12172444_1.6.2.3.1>
10964 23:40:10.583998 Received signal: <ENDRUN> 0_timesync-off 12172444_1.6.2.3.1
10965 23:40:10.584408 Ending use of test pattern.
10966 23:40:10.584735 Ending test lava.0_timesync-off (12172444_1.6.2.3.1), duration 0.07
10968 23:40:10.668036 + export TESTRUN_ID=1_kselftest-arm64
10969 23:40:10.668546 + TESTRUN_ID=1_kselftest-arm64
10970 23:40:10.674862 + cd /lava-12172444/0/tests/1_kselftest-arm64
10971 23:40:10.675314 ++ cat uuid
10972 23:40:10.679450 + UUID=12172444_1.6.2.3.5
10973 23:40:10.679886 + set +x
10974 23:40:10.686407 <LAVA_SIGNAL_STARTRUN 1_kselftest-arm64 12172444_1.6.2.3.5>
10975 23:40:10.687115 Received signal: <STARTRUN> 1_kselftest-arm64 12172444_1.6.2.3.5
10976 23:40:10.687506 Starting test lava.1_kselftest-arm64 (12172444_1.6.2.3.5)
10977 23:40:10.687912 Skipping test definition patterns.
10978 23:40:10.689873 + cd ./automated/linux/kselftest/
10979 23:40:10.715846 + ./kselftest.sh -c arm64 -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.64-cip10-rt5/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip-gitlab -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
10980 23:40:10.754205 INFO: install_deps skipped
10981 23:40:10.869340 --2023-12-03 23:37:56-- http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.64-cip10-rt5/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
10982 23:40:10.886030 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
10983 23:40:11.019353 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
10984 23:40:11.152944 HTTP request sent, awaiting response... 200 OK
10985 23:40:11.155953 Length: 2966880 (2.8M) [application/octet-stream]
10986 23:40:11.159176 Saving to: 'kselftest.tar.xz'
10987 23:40:11.159645
10988 23:40:11.160018
10989 23:40:11.418720 kselftest.tar.xz 0%[ ] 0 --.-KB/s
10990 23:40:11.684904 kselftest.tar.xz 1%[ ] 44.98K 170KB/s
10991 23:40:12.134362 kselftest.tar.xz 7%[> ] 217.50K 410KB/s
10992 23:40:12.411161 kselftest.tar.xz 28%[====> ] 821.30K 838KB/s
10993 23:40:12.488517 kselftest.tar.xz 84%[===============> ] 2.38M 1.90MB/s
10994 23:40:12.495203 kselftest.tar.xz 100%[===================>] 2.83M 2.12MB/s in 1.3s
10995 23:40:12.495922
10996 23:40:12.752416 2023-12-03 23:37:58 (2.12 MB/s) - 'kselftest.tar.xz' saved [2966880/2966880]
10997 23:40:12.752598
10998 23:40:18.645984 skiplist:
10999 23:40:18.648951 ========================================
11000 23:40:18.652001 ========================================
11001 23:40:18.703656 arm64:tags_test
11002 23:40:18.707096 arm64:run_tags_test.sh
11003 23:40:18.707558 arm64:fake_sigreturn_bad_magic
11004 23:40:18.710276 arm64:fake_sigreturn_bad_size
11005 23:40:18.713921 arm64:fake_sigreturn_bad_size_for_magic0
11006 23:40:18.716915 arm64:fake_sigreturn_duplicated_fpsimd
11007 23:40:18.720122 arm64:fake_sigreturn_misaligned_sp
11008 23:40:18.723296 arm64:fake_sigreturn_missing_fpsimd
11009 23:40:18.726784 arm64:fake_sigreturn_sme_change_vl
11010 23:40:18.730070 arm64:fake_sigreturn_sve_change_vl
11011 23:40:18.733321 arm64:mangle_pstate_invalid_compat_toggle
11012 23:40:18.737074 arm64:mangle_pstate_invalid_daif_bits
11013 23:40:18.739866 arm64:mangle_pstate_invalid_mode_el1h
11014 23:40:18.743191 arm64:mangle_pstate_invalid_mode_el1t
11015 23:40:18.746548 arm64:mangle_pstate_invalid_mode_el2h
11016 23:40:18.749416 arm64:mangle_pstate_invalid_mode_el2t
11017 23:40:18.756195 arm64:mangle_pstate_invalid_mode_el3h
11018 23:40:18.759361 arm64:mangle_pstate_invalid_mode_el3t
11019 23:40:18.759473 arm64:sme_trap_no_sm
11020 23:40:18.762682 arm64:sme_trap_non_streaming
11021 23:40:18.762765 arm64:sme_trap_za
11022 23:40:18.766208 arm64:sme_vl
11023 23:40:18.766304 arm64:ssve_regs
11024 23:40:18.769164 arm64:sve_regs
11025 23:40:18.769350 arm64:sve_vl
11026 23:40:18.769442 arm64:za_no_regs
11027 23:40:18.772588 arm64:za_regs
11028 23:40:18.772734 arm64:pac
11029 23:40:18.776084 arm64:fp-stress
11030 23:40:18.776178 arm64:sve-ptrace
11031 23:40:18.779279 arm64:sve-probe-vls
11032 23:40:18.779368 arm64:vec-syscfg
11033 23:40:18.782341 arm64:za-fork
11034 23:40:18.782430 arm64:za-ptrace
11035 23:40:18.785666 arm64:check_buffer_fill
11036 23:40:18.785762 arm64:check_child_memory
11037 23:40:18.788907 arm64:check_gcr_el1_cswitch
11038 23:40:18.792403 arm64:check_ksm_options
11039 23:40:18.792506 arm64:check_mmap_options
11040 23:40:18.795485 arm64:check_prctl
11041 23:40:18.798865 arm64:check_tags_inclusion
11042 23:40:18.798989 arm64:check_user_mem
11043 23:40:18.802572 arm64:btitest
11044 23:40:18.802695 arm64:nobtitest
11045 23:40:18.802792 arm64:hwcap
11046 23:40:18.805337 arm64:ptrace
11047 23:40:18.805471 arm64:syscall-abi
11048 23:40:18.808714 arm64:tpidr2
11049 23:40:18.812213 ============== Tests to run ===============
11050 23:40:18.812434 arm64:tags_test
11051 23:40:18.815589 arm64:run_tags_test.sh
11052 23:40:18.818645 arm64:fake_sigreturn_bad_magic
11053 23:40:18.821928 arm64:fake_sigreturn_bad_size
11054 23:40:18.825841 arm64:fake_sigreturn_bad_size_for_magic0
11055 23:40:18.828785 arm64:fake_sigreturn_duplicated_fpsimd
11056 23:40:18.832548 arm64:fake_sigreturn_misaligned_sp
11057 23:40:18.835671 arm64:fake_sigreturn_missing_fpsimd
11058 23:40:18.838576 arm64:fake_sigreturn_sme_change_vl
11059 23:40:18.842881 arm64:fake_sigreturn_sve_change_vl
11060 23:40:18.845404 arm64:mangle_pstate_invalid_compat_toggle
11061 23:40:18.848576 arm64:mangle_pstate_invalid_daif_bits
11062 23:40:18.852254 arm64:mangle_pstate_invalid_mode_el1h
11063 23:40:18.855048 arm64:mangle_pstate_invalid_mode_el1t
11064 23:40:18.859056 arm64:mangle_pstate_invalid_mode_el2h
11065 23:40:18.862036 arm64:mangle_pstate_invalid_mode_el2t
11066 23:40:18.865235 arm64:mangle_pstate_invalid_mode_el3h
11067 23:40:18.868400 arm64:mangle_pstate_invalid_mode_el3t
11068 23:40:18.868819 arm64:sme_trap_no_sm
11069 23:40:18.871528 arm64:sme_trap_non_streaming
11070 23:40:18.875272 arm64:sme_trap_za
11071 23:40:18.875691 arm64:sme_vl
11072 23:40:18.878702 arm64:ssve_regs
11073 23:40:18.879123 arm64:sve_regs
11074 23:40:18.879457 arm64:sve_vl
11075 23:40:18.881616 arm64:za_no_regs
11076 23:40:18.882038 arm64:za_regs
11077 23:40:18.885329 arm64:pac
11078 23:40:18.885780 arm64:fp-stress
11079 23:40:18.886114 arm64:sve-ptrace
11080 23:40:18.888346 arm64:sve-probe-vls
11081 23:40:18.888763 arm64:vec-syscfg
11082 23:40:18.891517 arm64:za-fork
11083 23:40:18.891937 arm64:za-ptrace
11084 23:40:18.894669 arm64:check_buffer_fill
11085 23:40:18.898239 arm64:check_child_memory
11086 23:40:18.898675 arm64:check_gcr_el1_cswitch
11087 23:40:18.901433 arm64:check_ksm_options
11088 23:40:18.904852 arm64:check_mmap_options
11089 23:40:18.905269 arm64:check_prctl
11090 23:40:18.908273 arm64:check_tags_inclusion
11091 23:40:18.911364 arm64:check_user_mem
11092 23:40:18.911784 arm64:btitest
11093 23:40:18.912115 arm64:nobtitest
11094 23:40:18.914622 arm64:hwcap
11095 23:40:18.915040 arm64:ptrace
11096 23:40:18.918711 arm64:syscall-abi
11097 23:40:18.919306 arm64:tpidr2
11098 23:40:18.921782 ===========End Tests to run ===============
11099 23:40:18.924504 shardfile-arm64 pass
11100 23:40:19.185419 <12>[ 35.338362] kselftest: Running tests in arm64
11101 23:40:19.192089 TAP version 13
11102 23:40:19.205236 1..48
11103 23:40:19.224501 # selftests: arm64: tags_test
11104 23:40:19.675651 ok 1 selftests: arm64: tags_test
11105 23:40:19.696840 # selftests: arm64: run_tags_test.sh
11106 23:40:19.736970 # --------------------
11107 23:40:19.740011 # running tags test
11108 23:40:19.740581 # --------------------
11109 23:40:19.743297 # [PASS]
11110 23:40:19.746434 ok 2 selftests: arm64: run_tags_test.sh
11111 23:40:19.760596 # selftests: arm64: fake_sigreturn_bad_magic
11112 23:40:19.826947 # Registered handlers for all signals.
11113 23:40:19.827521 # Detected MINSTKSIGSZ:4720
11114 23:40:19.829916 # Testcase initialized.
11115 23:40:19.833520 # uc context validated.
11116 23:40:19.836889 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11117 23:40:19.839841 # Handled SIG_COPYCTX
11118 23:40:19.840303 # Available space:3568
11119 23:40:19.846781 # Using badly built context - ERR: BAD MAGIC !
11120 23:40:19.853486 # SIG_OK -- SP:0xFFFFD0AB3630 si_addr@:0xffffd0ab3630 si_code:2 token@:0xffffd0ab23d0 offset:-4704
11121 23:40:19.856960 # ==>> completed. PASS(1)
11122 23:40:19.863101 # # FAKE_SIGRETURN_BAD_MAGIC :: Trigger a sigreturn with a sigframe with a bad magic
11123 23:40:19.870160 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFD0AB23D0
11124 23:40:19.873070 ok 3 selftests: arm64: fake_sigreturn_bad_magic
11125 23:40:19.879835 # selftests: arm64: fake_sigreturn_bad_size
11126 23:40:19.912906 # Registered handlers for all signals.
11127 23:40:19.913460 # Detected MINSTKSIGSZ:4720
11128 23:40:19.916163 # Testcase initialized.
11129 23:40:19.919550 # uc context validated.
11130 23:40:19.922501 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11131 23:40:19.925644 # Handled SIG_COPYCTX
11132 23:40:19.926111 # Available space:3568
11133 23:40:19.929112 # uc context validated.
11134 23:40:19.936038 # Using badly built context - ERR: Bad size for esr_context
11135 23:40:19.942352 # SIG_OK -- SP:0xFFFFCB3773F0 si_addr@:0xffffcb3773f0 si_code:2 token@:0xffffcb376190 offset:-4704
11136 23:40:19.945859 # ==>> completed. PASS(1)
11137 23:40:19.952346 # # FAKE_SIGRETURN_BAD_SIZE :: Triggers a sigreturn with a overrun __reserved area
11138 23:40:19.959828 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFCB376190
11139 23:40:19.962209 ok 4 selftests: arm64: fake_sigreturn_bad_size
11140 23:40:19.968953 # selftests: arm64: fake_sigreturn_bad_size_for_magic0
11141 23:40:19.985557 # Registered handlers for all signals.
11142 23:40:19.986149 # Detected MINSTKSIGSZ:4720
11143 23:40:19.988682 # Testcase initialized.
11144 23:40:19.992331 # uc context validated.
11145 23:40:19.995504 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11146 23:40:19.999385 # Handled SIG_COPYCTX
11147 23:40:19.999812 # Available space:3568
11148 23:40:20.005471 # Using badly built context - ERR: Bad size for terminator
11149 23:40:20.015619 # SIG_OK -- SP:0xFFFFE6B93040 si_addr@:0xffffe6b93040 si_code:2 token@:0xffffe6b91de0 offset:-4704
11150 23:40:20.016179 # ==>> completed. PASS(1)
11151 23:40:20.025520 # # FAKE_SIGRETURN_BAD_SIZE_FOR_TERMINATOR :: Trigger a sigreturn using non-zero size terminator
11152 23:40:20.032449 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFE6B91DE0
11153 23:40:20.035622 ok 5 selftests: arm64: fake_sigreturn_bad_size_for_magic0
11154 23:40:20.042260 # selftests: arm64: fake_sigreturn_duplicated_fpsimd
11155 23:40:20.067223 # Registered handlers for all signals.
11156 23:40:20.067780 # Detected MINSTKSIGSZ:4720
11157 23:40:20.070478 # Testcase initialized.
11158 23:40:20.073326 # uc context validated.
11159 23:40:20.076789 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11160 23:40:20.080446 # Handled SIG_COPYCTX
11161 23:40:20.080912 # Available space:3568
11162 23:40:20.086882 # Using badly built context - ERR: Multiple FPSIMD_MAGIC
11163 23:40:20.096913 # SIG_OK -- SP:0xFFFFEA505AB0 si_addr@:0xffffea505ab0 si_code:2 token@:0xffffea504850 offset:-4704
11164 23:40:20.097345 # ==>> completed. PASS(1)
11165 23:40:20.106607 # # FAKE_SIGRETURN_DUPLICATED_FPSIMD :: Triggers a sigreturn including two fpsimd_context
11166 23:40:20.113372 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFEA504850
11167 23:40:20.116819 ok 6 selftests: arm64: fake_sigreturn_duplicated_fpsimd
11168 23:40:20.119893 # selftests: arm64: fake_sigreturn_misaligned_sp
11169 23:40:20.153979 # Registered handlers for all signals.
11170 23:40:20.154550 # Detected MINSTKSIGSZ:4720
11171 23:40:20.157745 # Testcase initialized.
11172 23:40:20.160716 # uc context validated.
11173 23:40:20.163900 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11174 23:40:20.167408 # Handled SIG_COPYCTX
11175 23:40:20.173900 # SIG_OK -- SP:0xFFFFC0C52D33 si_addr@:0xffffc0c52d33 si_code:2 token@:0xffffc0c52d33 offset:0
11176 23:40:20.177031 # ==>> completed. PASS(1)
11177 23:40:20.183877 # # FAKE_SIGRETURN_MISALIGNED_SP :: Triggers a sigreturn with a misaligned sigframe
11178 23:40:20.190428 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFC0C52D33
11179 23:40:20.197612 ok 7 selftests: arm64: fake_sigreturn_misaligned_sp
11180 23:40:20.200343 # selftests: arm64: fake_sigreturn_missing_fpsimd
11181 23:40:20.233552 # Registered handlers for all signals.
11182 23:40:20.234169 # Detected MINSTKSIGSZ:4720
11183 23:40:20.236308 # Testcase initialized.
11184 23:40:20.240069 # uc context validated.
11185 23:40:20.242707 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11186 23:40:20.246498 # Handled SIG_COPYCTX
11187 23:40:20.249705 # Mangling template header. Spare space:4096
11188 23:40:20.253071 # Using badly built context - ERR: Missing FPSIMD
11189 23:40:20.263175 # SIG_OK -- SP:0xFFFFEF8A6590 si_addr@:0xffffef8a6590 si_code:2 token@:0xffffef8a5330 offset:-4704
11190 23:40:20.266043 # ==>> completed. PASS(1)
11191 23:40:20.272857 # # FAKE_SIGRETURN_MISSING_FPSIMD :: Triggers a sigreturn with a missing fpsimd_context
11192 23:40:20.279314 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFEF8A5330
11193 23:40:20.282491 ok 8 selftests: arm64: fake_sigreturn_missing_fpsimd
11194 23:40:20.289458 # selftests: arm64: fake_sigreturn_sme_change_vl
11195 23:40:20.314172 # Registered handlers for all signals.
11196 23:40:20.314758 # Detected MINSTKSIGSZ:4720
11197 23:40:20.317877 # ==>> completed. SKIP.
11198 23:40:20.324275 # # FAKE_SIGRETURN_SSVE_CHANGE :: Attempt to change Streaming SVE VL
11199 23:40:20.327551 ok 9 selftests: arm64: fake_sigreturn_sme_change_vl # SKIP
11200 23:40:20.334131 # selftests: arm64: fake_sigreturn_sve_change_vl
11201 23:40:20.401490 # Registered handlers for all signals.
11202 23:40:20.402099 # Detected MINSTKSIGSZ:4720
11203 23:40:20.404581 # ==>> completed. SKIP.
11204 23:40:20.407427 # # FAKE_SIGRETURN_SVE_CHANGE :: Attempt to change SVE VL
11205 23:40:20.414238 ok 10 selftests: arm64: fake_sigreturn_sve_change_vl # SKIP
11206 23:40:20.420776 # selftests: arm64: mangle_pstate_invalid_compat_toggle
11207 23:40:20.461799 # Registered handlers for all signals.
11208 23:40:20.462356 # Detected MINSTKSIGSZ:4720
11209 23:40:20.464805 # Testcase initialized.
11210 23:40:20.467666 # uc context validated.
11211 23:40:20.468317 # Handled SIG_TRIG
11212 23:40:20.477501 # SIG_OK -- SP:0xFFFFC0EF7150 si_addr@:0xffffc0ef7150 si_code:2 token@:(nil) offset:-281473918660944
11213 23:40:20.481301 # ==>> completed. PASS(1)
11214 23:40:20.487587 # # MANGLE_PSTATE_INVALID_STATE_TOGGLE :: Mangling uc_mcontext with INVALID STATE_TOGGLE
11215 23:40:20.494169 ok 11 selftests: arm64: mangle_pstate_invalid_compat_toggle
11216 23:40:20.497743 # selftests: arm64: mangle_pstate_invalid_daif_bits
11217 23:40:20.544046 # Registered handlers for all signals.
11218 23:40:20.544638 # Detected MINSTKSIGSZ:4720
11219 23:40:20.547269 # Testcase initialized.
11220 23:40:20.550855 # uc context validated.
11221 23:40:20.551317 # Handled SIG_TRIG
11222 23:40:20.560421 # SIG_OK -- SP:0xFFFFC2543170 si_addr@:0xffffc2543170 si_code:2 token@:(nil) offset:-281473942040944
11223 23:40:20.563545 # ==>> completed. PASS(1)
11224 23:40:20.570216 # # MANGLE_PSTATE_INVALID_DAIF_BITS :: Mangling uc_mcontext with INVALID DAIF_BITS
11225 23:40:20.573719 ok 12 selftests: arm64: mangle_pstate_invalid_daif_bits
11226 23:40:20.580360 # selftests: arm64: mangle_pstate_invalid_mode_el1h
11227 23:40:20.624590 # Registered handlers for all signals.
11228 23:40:20.625192 # Detected MINSTKSIGSZ:4720
11229 23:40:20.628354 # Testcase initialized.
11230 23:40:20.631115 # uc context validated.
11231 23:40:20.631578 # Handled SIG_TRIG
11232 23:40:20.641254 # SIG_OK -- SP:0xFFFFE280C2C0 si_addr@:0xffffe280c2c0 si_code:2 token@:(nil) offset:-281474481832640
11233 23:40:20.644534 # ==>> completed. PASS(1)
11234 23:40:20.650931 # # MANGLE_PSTATE_INVALID_MODE_EL1h :: Mangling uc_mcontext INVALID MODE EL1h
11235 23:40:20.654295 ok 13 selftests: arm64: mangle_pstate_invalid_mode_el1h
11236 23:40:20.660932 # selftests: arm64: mangle_pstate_invalid_mode_el1t
11237 23:40:20.699756 # Registered handlers for all signals.
11238 23:40:20.700356 # Detected MINSTKSIGSZ:4720
11239 23:40:20.702693 # Testcase initialized.
11240 23:40:20.706457 # uc context validated.
11241 23:40:20.706922 # Handled SIG_TRIG
11242 23:40:20.716072 # SIG_OK -- SP:0xFFFFD7EC4950 si_addr@:0xffffd7ec4950 si_code:2 token@:(nil) offset:-281474304330064
11243 23:40:20.719883 # ==>> completed. PASS(1)
11244 23:40:20.726279 # # MANGLE_PSTATE_INVALID_MODE_EL1t :: Mangling uc_mcontext INVALID MODE EL1t
11245 23:40:20.729156 ok 14 selftests: arm64: mangle_pstate_invalid_mode_el1t
11246 23:40:20.735893 # selftests: arm64: mangle_pstate_invalid_mode_el2h
11247 23:40:20.782928 # Registered handlers for all signals.
11248 23:40:20.783485 # Detected MINSTKSIGSZ:4720
11249 23:40:20.786268 # Testcase initialized.
11250 23:40:20.789848 # uc context validated.
11251 23:40:20.790483 # Handled SIG_TRIG
11252 23:40:20.799813 # SIG_OK -- SP:0xFFFFDEC436C0 si_addr@:0xffffdec436c0 si_code:2 token@:(nil) offset:-281474419144384
11253 23:40:20.802817 # ==>> completed. PASS(1)
11254 23:40:20.809991 # # MANGLE_PSTATE_INVALID_MODE_EL2h :: Mangling uc_mcontext INVALID MODE EL2h
11255 23:40:20.812578 ok 15 selftests: arm64: mangle_pstate_invalid_mode_el2h
11256 23:40:20.819605 # selftests: arm64: mangle_pstate_invalid_mode_el2t
11257 23:40:20.865907 # Registered handlers for all signals.
11258 23:40:20.866469 # Detected MINSTKSIGSZ:4720
11259 23:40:20.869490 # Testcase initialized.
11260 23:40:20.872725 # uc context validated.
11261 23:40:20.873254 # Handled SIG_TRIG
11262 23:40:20.882216 # SIG_OK -- SP:0xFFFFC9050C10 si_addr@:0xffffc9050c10 si_code:2 token@:(nil) offset:-281474054294544
11263 23:40:20.885665 # ==>> completed. PASS(1)
11264 23:40:20.891967 # # MANGLE_PSTATE_INVALID_MODE_EL2t :: Mangling uc_mcontext INVALID MODE EL2t
11265 23:40:20.895284 ok 16 selftests: arm64: mangle_pstate_invalid_mode_el2t
11266 23:40:20.901741 # selftests: arm64: mangle_pstate_invalid_mode_el3h
11267 23:40:20.949069 # Registered handlers for all signals.
11268 23:40:20.949686 # Detected MINSTKSIGSZ:4720
11269 23:40:20.952757 # Testcase initialized.
11270 23:40:20.955515 # uc context validated.
11271 23:40:20.955986 # Handled SIG_TRIG
11272 23:40:20.965925 # SIG_OK -- SP:0xFFFFDB4026C0 si_addr@:0xffffdb4026c0 si_code:2 token@:(nil) offset:-281474360157888
11273 23:40:20.969394 # ==>> completed. PASS(1)
11274 23:40:20.975221 # # MANGLE_PSTATE_INVALID_MODE_EL3h :: Mangling uc_mcontext INVALID MODE EL3h
11275 23:40:20.978896 ok 17 selftests: arm64: mangle_pstate_invalid_mode_el3h
11276 23:40:20.984685 # selftests: arm64: mangle_pstate_invalid_mode_el3t
11277 23:40:21.046240 # Registered handlers for all signals.
11278 23:40:21.046648 # Detected MINSTKSIGSZ:4720
11279 23:40:21.049844 # Testcase initialized.
11280 23:40:21.052801 # uc context validated.
11281 23:40:21.053234 # Handled SIG_TRIG
11282 23:40:21.062753 # SIG_OK -- SP:0xFFFFCBB87170 si_addr@:0xffffcbb87170 si_code:2 token@:(nil) offset:-281474099605872
11283 23:40:21.066060 # ==>> completed. PASS(1)
11284 23:40:21.072584 # # MANGLE_PSTATE_INVALID_MODE_EL3t :: Mangling uc_mcontext INVALID MODE EL3t
11285 23:40:21.075857 ok 18 selftests: arm64: mangle_pstate_invalid_mode_el3t
11286 23:40:21.078963 # selftests: arm64: sme_trap_no_sm
11287 23:40:21.130984 # Registered handlers for all signals.
11288 23:40:21.131590 # Detected MINSTKSIGSZ:4720
11289 23:40:21.134208 # ==>> completed. SKIP.
11290 23:40:21.143806 # # SME trap without SM :: Check that we get a SIGILL if we use streaming mode without enabling it
11291 23:40:21.147122 ok 19 selftests: arm64: sme_trap_no_sm # SKIP
11292 23:40:21.150321 # selftests: arm64: sme_trap_non_streaming
11293 23:40:21.218286 # Registered handlers for all signals.
11294 23:40:21.218847 # Detected MINSTKSIGSZ:4720
11295 23:40:21.221343 # ==>> completed. SKIP.
11296 23:40:21.231675 # # SME SM trap unsupported instruction :: Check that we get a SIGILL if we use an unsupported instruction in streaming mode
11297 23:40:21.238427 ok 20 selftests: arm64: sme_trap_non_streaming # SKIP
11298 23:40:21.241016 # selftests: arm64: sme_trap_za
11299 23:40:21.309055 # Registered handlers for all signals.
11300 23:40:21.309697 # Detected MINSTKSIGSZ:4720
11301 23:40:21.312306 # Testcase initialized.
11302 23:40:21.322029 # SIG_OK -- SP:0xFFFFCC5BFFB0 si_addr@:0xaaaae4ba2510 si_code:1 token@:(nil) offset:-187650958566672
11303 23:40:21.322524 # ==>> completed. PASS(1)
11304 23:40:21.331708 # # SME ZA trap :: Check that we get a SIGILL if we access ZA without enabling
11305 23:40:21.332347 ok 21 selftests: arm64: sme_trap_za
11306 23:40:21.335662 # selftests: arm64: sme_vl
11307 23:40:21.413157 # Registered handlers for all signals.
11308 23:40:21.413838 # Detected MINSTKSIGSZ:4720
11309 23:40:21.416097 # ==>> completed. SKIP.
11310 23:40:21.423218 # # SME VL :: Check that we get the right SME VL reported
11311 23:40:21.426249 ok 22 selftests: arm64: sme_vl # SKIP
11312 23:40:21.430378 # selftests: arm64: ssve_regs
11313 23:40:21.494636 # Registered handlers for all signals.
11314 23:40:21.495188 # Detected MINSTKSIGSZ:4720
11315 23:40:21.497519 # ==>> completed. SKIP.
11316 23:40:21.504484 # # Streaming SVE registers :: Check that we get the right Streaming SVE registers reported
11317 23:40:21.510883 ok 23 selftests: arm64: ssve_regs # SKIP
11318 23:40:21.516932 # selftests: arm64: sve_regs
11319 23:40:21.579247 # Registered handlers for all signals.
11320 23:40:21.579833 # Detected MINSTKSIGSZ:4720
11321 23:40:21.582373 # ==>> completed. SKIP.
11322 23:40:21.588830 # # SVE registers :: Check that we get the right SVE registers reported
11323 23:40:21.592593 ok 24 selftests: arm64: sve_regs # SKIP
11324 23:40:21.597234 # selftests: arm64: sve_vl
11325 23:40:21.654063 # Registered handlers for all signals.
11326 23:40:21.654635 # Detected MINSTKSIGSZ:4720
11327 23:40:21.657269 # ==>> completed. SKIP.
11328 23:40:21.661052 # # SVE VL :: Check that we get the right SVE VL reported
11329 23:40:21.663899 ok 25 selftests: arm64: sve_vl # SKIP
11330 23:40:21.671498 # selftests: arm64: za_no_regs
11331 23:40:21.757027 # Registered handlers for all signals.
11332 23:40:21.757670 # Detected MINSTKSIGSZ:4720
11333 23:40:21.760425 # ==>> completed. SKIP.
11334 23:40:21.766857 # # ZA registers - ZA disabled :: Check ZA context with ZA disabled
11335 23:40:21.770478 ok 26 selftests: arm64: za_no_regs # SKIP
11336 23:40:21.775865 # selftests: arm64: za_regs
11337 23:40:21.840335 # Registered handlers for all signals.
11338 23:40:21.840909 # Detected MINSTKSIGSZ:4720
11339 23:40:21.843608 # ==>> completed. SKIP.
11340 23:40:21.849950 # # ZA register :: Check that we get the right ZA registers reported
11341 23:40:21.853239 ok 27 selftests: arm64: za_regs # SKIP
11342 23:40:21.857645 # selftests: arm64: pac
11343 23:40:21.927276 # TAP version 13
11344 23:40:21.927913 # 1..7
11345 23:40:21.931010 # # Starting 7 tests from 1 test cases.
11346 23:40:21.933650 # # RUN global.corrupt_pac ...
11347 23:40:21.937070 # # SKIP PAUTH not enabled
11348 23:40:21.940587 # # OK global.corrupt_pac
11349 23:40:21.943698 # ok 1 # SKIP PAUTH not enabled
11350 23:40:21.950165 # # RUN global.pac_instructions_not_nop ...
11351 23:40:21.953716 # # SKIP PAUTH not enabled
11352 23:40:21.956573 # # OK global.pac_instructions_not_nop
11353 23:40:21.959946 # ok 2 # SKIP PAUTH not enabled
11354 23:40:21.967013 # # RUN global.pac_instructions_not_nop_generic ...
11355 23:40:21.969993 # # SKIP Generic PAUTH not enabled
11356 23:40:21.973245 # # OK global.pac_instructions_not_nop_generic
11357 23:40:21.980278 # ok 3 # SKIP Generic PAUTH not enabled
11358 23:40:21.983646 # # RUN global.single_thread_different_keys ...
11359 23:40:21.986551 # # SKIP PAUTH not enabled
11360 23:40:21.993324 # # OK global.single_thread_different_keys
11361 23:40:21.993913 # ok 4 # SKIP PAUTH not enabled
11362 23:40:22.000194 # # RUN global.exec_changed_keys ...
11363 23:40:22.003332 # # SKIP PAUTH not enabled
11364 23:40:22.006436 # # OK global.exec_changed_keys
11365 23:40:22.010076 # ok 5 # SKIP PAUTH not enabled
11366 23:40:22.013172 # # RUN global.context_switch_keep_keys ...
11367 23:40:22.016588 # # SKIP PAUTH not enabled
11368 23:40:22.022911 # # OK global.context_switch_keep_keys
11369 23:40:22.023425 # ok 6 # SKIP PAUTH not enabled
11370 23:40:22.029670 # # RUN global.context_switch_keep_keys_generic ...
11371 23:40:22.032930 # # SKIP Generic PAUTH not enabled
11372 23:40:22.039772 # # OK global.context_switch_keep_keys_generic
11373 23:40:22.042673 # ok 7 # SKIP Generic PAUTH not enabled
11374 23:40:22.046407 # # PASSED: 7 / 7 tests passed.
11375 23:40:22.049517 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:7 error:0
11376 23:40:22.052784 ok 28 selftests: arm64: pac
11377 23:40:22.056518 # selftests: arm64: fp-stress
11378 23:40:27.877739 <6>[ 44.033398] vpu: disabling
11379 23:40:27.880938 <6>[ 44.033484] vproc2: disabling
11380 23:40:27.884505 <6>[ 44.033521] vproc1: disabling
11381 23:40:27.887470 <6>[ 44.033559] vaud18: disabling
11382 23:40:27.890662 <6>[ 44.033740] vsram_others: disabling
11383 23:40:27.894217 <6>[ 44.033869] va09: disabling
11384 23:40:27.897900 <6>[ 44.033924] vsram_md: disabling
11385 23:40:27.900798 <6>[ 44.034020] Vgpu: disabling
11386 23:40:32.003347 # TAP version 13
11387 23:40:32.003910 # 1..16
11388 23:40:32.006270 # # 8 CPUs, 0 SVE VLs, 0 SME VLs
11389 23:40:32.009846 # # Will run for 10s
11390 23:40:32.010412 # # Started FPSIMD-0-0
11391 23:40:32.013437 # # Started FPSIMD-0-1
11392 23:40:32.016038 # # Started FPSIMD-1-0
11393 23:40:32.016512 # # Started FPSIMD-1-1
11394 23:40:32.019934 # # Started FPSIMD-2-0
11395 23:40:32.023063 # # Started FPSIMD-2-1
11396 23:40:32.023650 # # Started FPSIMD-3-0
11397 23:40:32.026190 # # Started FPSIMD-3-1
11398 23:40:32.029570 # # Started FPSIMD-4-0
11399 23:40:32.030036 # # Started FPSIMD-4-1
11400 23:40:32.032899 # # Started FPSIMD-5-0
11401 23:40:32.033367 # # Started FPSIMD-5-1
11402 23:40:32.035984 # # Started FPSIMD-6-0
11403 23:40:32.039243 # # Started FPSIMD-6-1
11404 23:40:32.039668 # # Started FPSIMD-7-0
11405 23:40:32.042473 # # Started FPSIMD-7-1
11406 23:40:32.046155 # # FPSIMD-0-0: Vector length: 128 bits
11407 23:40:32.049370 # # FPSIMD-0-0: PID: 1164
11408 23:40:32.052482 # # FPSIMD-0-1: Vector length: 128 bits
11409 23:40:32.052905 # # FPSIMD-0-1: PID: 1165
11410 23:40:32.059380 # # FPSIMD-1-1: Vector length: 128 bits
11411 23:40:32.059808 # # FPSIMD-1-1: PID: 1167
11412 23:40:32.062670 # # FPSIMD-1-0: Vector length: 128 bits
11413 23:40:32.066216 # # FPSIMD-1-0: PID: 1166
11414 23:40:32.069073 # # FPSIMD-2-1: Vector length: 128 bits
11415 23:40:32.072476 # # FPSIMD-2-1: PID: 1169
11416 23:40:32.076013 # # FPSIMD-2-0: Vector length: 128 bits
11417 23:40:32.079019 # # FPSIMD-2-0: PID: 1168
11418 23:40:32.082398 # # FPSIMD-4-1: Vector length: 128 bits
11419 23:40:32.082826 # # FPSIMD-4-1: PID: 1173
11420 23:40:32.085704 # # FPSIMD-3-1: Vector length: 128 bits
11421 23:40:32.088912 # # FPSIMD-3-1: PID: 1171
11422 23:40:32.092098 # # FPSIMD-5-1: Vector length: 128 bits
11423 23:40:32.095444 # # FPSIMD-5-1: PID: 1175
11424 23:40:32.098730 # # FPSIMD-4-0: Vector length: 128 bits
11425 23:40:32.102151 # # FPSIMD-4-0: PID: 1172
11426 23:40:32.105980 # # FPSIMD-3-0: Vector length: 128 bits
11427 23:40:32.108836 # # FPSIMD-3-0: PID: 1170
11428 23:40:32.112181 # # FPSIMD-6-0: Vector length: 128 bits
11429 23:40:32.112605 # # FPSIMD-6-0: PID: 1176
11430 23:40:32.115640 # # FPSIMD-7-0: Vector length: 128 bits
11431 23:40:32.119027 # # FPSIMD-7-0: PID: 1178
11432 23:40:32.122148 # # FPSIMD-7-1: Vector length: 128 bits
11433 23:40:32.125189 # # FPSIMD-7-1: PID: 1179
11434 23:40:32.128735 # # FPSIMD-6-1: Vector length: 128 bits
11435 23:40:32.131933 # # FPSIMD-6-1: PID: 1177
11436 23:40:32.135369 # # FPSIMD-5-0: Vector length: 128 bits
11437 23:40:32.135795 # # FPSIMD-5-0: PID: 1174
11438 23:40:32.138771 # # Finishing up...
11439 23:40:32.145401 # # FPSIMD-0-0: Terminated by signal 15, no error, iterations=1115876, signals=10
11440 23:40:32.152135 # # FPSIMD-2-0: Terminated by signal 15, no error, iterations=1172027, signals=10
11441 23:40:32.158817 # # FPSIMD-2-1: Terminated by signal 15, no error, iterations=1755784, signals=10
11442 23:40:32.168975 # # FPSIMD-4-0: Terminated by signal 15, no error, iterations=1381023, signals=10
11443 23:40:32.175549 # # FPSIMD-4-1: Terminated by signal 15, no error, iterations=1201145, signals=10
11444 23:40:32.182239 # # FPSIMD-5-0: Terminated by signal 15, no error, iterations=2039237, signals=10
11445 23:40:32.188748 # # FPSIMD-6-1: Terminated by signal 15, no error, iterations=1134352, signals=10
11446 23:40:32.191561 # ok 1 FPSIMD-0-0
11447 23:40:32.191984 # ok 2 FPSIMD-0-1
11448 23:40:32.195263 # ok 3 FPSIMD-1-0
11449 23:40:32.195895 # ok 4 FPSIMD-1-1
11450 23:40:32.198271 # ok 5 FPSIMD-2-0
11451 23:40:32.198697 # ok 6 FPSIMD-2-1
11452 23:40:32.201291 # ok 7 FPSIMD-3-0
11453 23:40:32.201767 # ok 8 FPSIMD-3-1
11454 23:40:32.204607 # ok 9 FPSIMD-4-0
11455 23:40:32.205027 # ok 10 FPSIMD-4-1
11456 23:40:32.207897 # ok 11 FPSIMD-5-0
11457 23:40:32.208317 # ok 12 FPSIMD-5-1
11458 23:40:32.211552 # ok 13 FPSIMD-6-0
11459 23:40:32.211975 # ok 14 FPSIMD-6-1
11460 23:40:32.215084 # ok 15 FPSIMD-7-0
11461 23:40:32.215510 # ok 16 FPSIMD-7-1
11462 23:40:32.224662 # # FPSIMD-1-0: Terminated by signal 15, no error, iterations=1051522, signals=9
11463 23:40:32.231462 # # FPSIMD-5-1: Terminated by signal 15, no error, iterations=1044075, signals=9
11464 23:40:32.238114 # # FPSIMD-0-1: Terminated by signal 15, no error, iterations=1426944, signals=10
11465 23:40:32.244721 # # FPSIMD-3-0: Terminated by signal 15, no error, iterations=1206819, signals=10
11466 23:40:32.251335 # # FPSIMD-1-1: Terminated by signal 15, no error, iterations=968853, signals=10
11467 23:40:32.257757 # # FPSIMD-6-0: Terminated by signal 15, no error, iterations=1357045, signals=10
11468 23:40:32.267531 # # FPSIMD-3-1: Terminated by signal 15, no error, iterations=1264039, signals=10
11469 23:40:32.274546 # # FPSIMD-7-1: Terminated by signal 15, no error, iterations=1309857, signals=9
11470 23:40:32.280657 # # FPSIMD-7-0: Terminated by signal 15, no error, iterations=984404, signals=10
11471 23:40:32.284589 # # Totals: pass:16 fail:0 xfail:0 xpass:0 skip:0 error:0
11472 23:40:32.287654 ok 29 selftests: arm64: fp-stress
11473 23:40:32.290880 # selftests: arm64: sve-ptrace
11474 23:40:32.293919 # TAP version 13
11475 23:40:32.294436 # 1..4104
11476 23:40:32.297203 # ok 2 # SKIP SVE not available
11477 23:40:32.300636 # # Planned tests != run tests (4104 != 1)
11478 23:40:32.303763 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11479 23:40:32.310878 ok 30 selftests: arm64: sve-ptrace # SKIP
11480 23:40:32.314310 # selftests: arm64: sve-probe-vls
11481 23:40:32.314835 # TAP version 13
11482 23:40:32.315181 # 1..2
11483 23:40:32.317391 # ok 2 # SKIP SVE not available
11484 23:40:32.320692 # # Planned tests != run tests (2 != 1)
11485 23:40:32.327522 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11486 23:40:32.330799 ok 31 selftests: arm64: sve-probe-vls # SKIP
11487 23:40:32.333723 # selftests: arm64: vec-syscfg
11488 23:40:32.334242 # TAP version 13
11489 23:40:32.334745 # 1..20
11490 23:40:32.337824 # ok 1 # SKIP SVE not supported
11491 23:40:32.340462 # ok 2 # SKIP SVE not supported
11492 23:40:32.343712 # ok 3 # SKIP SVE not supported
11493 23:40:32.347475 # ok 4 # SKIP SVE not supported
11494 23:40:32.350223 # ok 5 # SKIP SVE not supported
11495 23:40:32.354194 # ok 6 # SKIP SVE not supported
11496 23:40:32.355021 # ok 7 # SKIP SVE not supported
11497 23:40:32.357226 # ok 8 # SKIP SVE not supported
11498 23:40:32.359926 # ok 9 # SKIP SVE not supported
11499 23:40:32.363921 # ok 10 # SKIP SVE not supported
11500 23:40:32.366700 # ok 11 # SKIP SME not supported
11501 23:40:32.370228 # ok 12 # SKIP SME not supported
11502 23:40:32.373554 # ok 13 # SKIP SME not supported
11503 23:40:32.376767 # ok 14 # SKIP SME not supported
11504 23:40:32.379792 # ok 15 # SKIP SME not supported
11505 23:40:32.380464 # ok 16 # SKIP SME not supported
11506 23:40:32.383169 # ok 17 # SKIP SME not supported
11507 23:40:32.386691 # ok 18 # SKIP SME not supported
11508 23:40:32.390108 # ok 19 # SKIP SME not supported
11509 23:40:32.393368 # ok 20 # SKIP SME not supported
11510 23:40:32.400401 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:20 error:0
11511 23:40:32.403407 ok 32 selftests: arm64: vec-syscfg
11512 23:40:32.403959 # selftests: arm64: za-fork
11513 23:40:32.406344 # TAP version 13
11514 23:40:32.406771 # 1..1
11515 23:40:32.407116 # # PID: 1254
11516 23:40:32.409881 # # SME support not present
11517 23:40:32.413319 # ok 0 skipped
11518 23:40:32.416639 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11519 23:40:32.419860 ok 33 selftests: arm64: za-fork
11520 23:40:32.423472 # selftests: arm64: za-ptrace
11521 23:40:32.424037 # TAP version 13
11522 23:40:32.426686 # 1..1
11523 23:40:32.429910 # ok 2 # SKIP SME not available
11524 23:40:32.433087 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11525 23:40:32.436267 ok 34 selftests: arm64: za-ptrace # SKIP
11526 23:40:32.446950 # selftests: arm64: check_buffer_fill
11527 23:40:32.498628 # # SKIP: MTE features unavailable
11528 23:40:32.506305 ok 35 selftests: arm64: check_buffer_fill # SKIP
11529 23:40:32.522584 # selftests: arm64: check_child_memory
11530 23:40:32.575578 # # SKIP: MTE features unavailable
11531 23:40:32.582631 ok 36 selftests: arm64: check_child_memory # SKIP
11532 23:40:32.599624 # selftests: arm64: check_gcr_el1_cswitch
11533 23:40:32.661553 # # SKIP: MTE features unavailable
11534 23:40:32.668711 ok 37 selftests: arm64: check_gcr_el1_cswitch # SKIP
11535 23:40:32.686062 # selftests: arm64: check_ksm_options
11536 23:40:32.734132 # # SKIP: MTE features unavailable
11537 23:40:32.741152 ok 38 selftests: arm64: check_ksm_options # SKIP
11538 23:40:32.755669 # selftests: arm64: check_mmap_options
11539 23:40:32.815475 # # SKIP: MTE features unavailable
11540 23:40:32.822704 ok 39 selftests: arm64: check_mmap_options # SKIP
11541 23:40:32.835785 # selftests: arm64: check_prctl
11542 23:40:32.878655 # TAP version 13
11543 23:40:32.879235 # 1..5
11544 23:40:32.881706 # ok 1 check_basic_read
11545 23:40:32.882174 # ok 2 NONE
11546 23:40:32.884988 # ok 3 # SKIP SYNC
11547 23:40:32.885480 # ok 4 # SKIP ASYNC
11548 23:40:32.887892 # ok 5 # SKIP SYNC+ASYNC
11549 23:40:32.891456 # # Totals: pass:2 fail:0 xfail:0 xpass:0 skip:3 error:0
11550 23:40:32.894680 ok 40 selftests: arm64: check_prctl
11551 23:40:32.900902 # selftests: arm64: check_tags_inclusion
11552 23:40:32.953766 # # SKIP: MTE features unavailable
11553 23:40:32.962009 ok 41 selftests: arm64: check_tags_inclusion # SKIP
11554 23:40:32.974499 # selftests: arm64: check_user_mem
11555 23:40:33.055093 # # SKIP: MTE features unavailable
11556 23:40:33.062835 ok 42 selftests: arm64: check_user_mem # SKIP
11557 23:40:33.075847 # selftests: arm64: btitest
11558 23:40:33.128873 # TAP version 13
11559 23:40:33.129431 # 1..18
11560 23:40:33.132274 # # HWCAP_PACA not present
11561 23:40:33.135241 # # HWCAP2_BTI not present
11562 23:40:33.135718 # # Test binary built for BTI
11563 23:40:33.141764 # ok 1 nohint_func/call_using_br_x0 # SKIP
11564 23:40:33.145197 # ok 1 nohint_func/call_using_br_x16 # SKIP
11565 23:40:33.148148 # ok 1 nohint_func/call_using_blr # SKIP
11566 23:40:33.151691 # ok 1 bti_none_func/call_using_br_x0 # SKIP
11567 23:40:33.155156 # ok 1 bti_none_func/call_using_br_x16 # SKIP
11568 23:40:33.161463 # ok 1 bti_none_func/call_using_blr # SKIP
11569 23:40:33.164540 # ok 1 bti_c_func/call_using_br_x0 # SKIP
11570 23:40:33.168150 # ok 1 bti_c_func/call_using_br_x16 # SKIP
11571 23:40:33.171730 # ok 1 bti_c_func/call_using_blr # SKIP
11572 23:40:33.174943 # ok 1 bti_j_func/call_using_br_x0 # SKIP
11573 23:40:33.178540 # ok 1 bti_j_func/call_using_br_x16 # SKIP
11574 23:40:33.181414 # ok 1 bti_j_func/call_using_blr # SKIP
11575 23:40:33.185165 # ok 1 bti_jc_func/call_using_br_x0 # SKIP
11576 23:40:33.191452 # ok 1 bti_jc_func/call_using_br_x16 # SKIP
11577 23:40:33.194465 # ok 1 bti_jc_func/call_using_blr # SKIP
11578 23:40:33.198117 # ok 1 paciasp_func/call_using_br_x0 # SKIP
11579 23:40:33.201219 # ok 1 paciasp_func/call_using_br_x16 # SKIP
11580 23:40:33.204484 # ok 1 paciasp_func/call_using_blr # SKIP
11581 23:40:33.211304 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:18 error:0
11582 23:40:33.214868 # # WARNING - EXPECTED TEST COUNT WRONG
11583 23:40:33.217838 ok 43 selftests: arm64: btitest
11584 23:40:33.221181 # selftests: arm64: nobtitest
11585 23:40:33.221701 # TAP version 13
11586 23:40:33.222048 # 1..18
11587 23:40:33.224468 # # HWCAP_PACA not present
11588 23:40:33.228101 # # HWCAP2_BTI not present
11589 23:40:33.230867 # # Test binary not built for BTI
11590 23:40:33.234362 # ok 1 nohint_func/call_using_br_x0 # SKIP
11591 23:40:33.237690 # ok 1 nohint_func/call_using_br_x16 # SKIP
11592 23:40:33.240910 # ok 1 nohint_func/call_using_blr # SKIP
11593 23:40:33.244397 # ok 1 bti_none_func/call_using_br_x0 # SKIP
11594 23:40:33.247489 # ok 1 bti_none_func/call_using_br_x16 # SKIP
11595 23:40:33.254508 # ok 1 bti_none_func/call_using_blr # SKIP
11596 23:40:33.257550 # ok 1 bti_c_func/call_using_br_x0 # SKIP
11597 23:40:33.260708 # ok 1 bti_c_func/call_using_br_x16 # SKIP
11598 23:40:33.264232 # ok 1 bti_c_func/call_using_blr # SKIP
11599 23:40:33.267798 # ok 1 bti_j_func/call_using_br_x0 # SKIP
11600 23:40:33.271331 # ok 1 bti_j_func/call_using_br_x16 # SKIP
11601 23:40:33.274203 # ok 1 bti_j_func/call_using_blr # SKIP
11602 23:40:33.277424 # ok 1 bti_jc_func/call_using_br_x0 # SKIP
11603 23:40:33.284490 # ok 1 bti_jc_func/call_using_br_x16 # SKIP
11604 23:40:33.287543 # ok 1 bti_jc_func/call_using_blr # SKIP
11605 23:40:33.291227 # ok 1 paciasp_func/call_using_br_x0 # SKIP
11606 23:40:33.294205 # ok 1 paciasp_func/call_using_br_x16 # SKIP
11607 23:40:33.297809 # ok 1 paciasp_func/call_using_blr # SKIP
11608 23:40:33.303853 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:18 error:0
11609 23:40:33.306889 # # WARNING - EXPECTED TEST COUNT WRONG
11610 23:40:33.310290 ok 44 selftests: arm64: nobtitest
11611 23:40:33.313607 # selftests: arm64: hwcap
11612 23:40:33.314040 # TAP version 13
11613 23:40:33.314383 # 1..28
11614 23:40:33.316986 # ok 1 cpuinfo_match_RNG
11615 23:40:33.320844 # # SIGILL reported for RNG
11616 23:40:33.321272 # ok 2 # SKIP sigill_RNG
11617 23:40:33.323799 # ok 3 cpuinfo_match_SME
11618 23:40:33.326985 # ok 4 sigill_SME
11619 23:40:33.327409 # ok 5 cpuinfo_match_SVE
11620 23:40:33.330540 # ok 6 sigill_SVE
11621 23:40:33.330966 # ok 7 cpuinfo_match_SVE 2
11622 23:40:33.333457 # # SIGILL reported for SVE 2
11623 23:40:33.337023 # ok 8 # SKIP sigill_SVE 2
11624 23:40:33.340573 # ok 9 cpuinfo_match_SVE AES
11625 23:40:33.343458 # # SIGILL reported for SVE AES
11626 23:40:33.343883 # ok 10 # SKIP sigill_SVE AES
11627 23:40:33.347211 # ok 11 cpuinfo_match_SVE2 PMULL
11628 23:40:33.350159 # # SIGILL reported for SVE2 PMULL
11629 23:40:33.353200 # ok 12 # SKIP sigill_SVE2 PMULL
11630 23:40:33.356582 # ok 13 cpuinfo_match_SVE2 BITPERM
11631 23:40:33.359796 # # SIGILL reported for SVE2 BITPERM
11632 23:40:33.363244 # ok 14 # SKIP sigill_SVE2 BITPERM
11633 23:40:33.367096 # ok 15 cpuinfo_match_SVE2 SHA3
11634 23:40:33.369974 # # SIGILL reported for SVE2 SHA3
11635 23:40:33.373394 # ok 16 # SKIP sigill_SVE2 SHA3
11636 23:40:33.376621 # ok 17 cpuinfo_match_SVE2 SM4
11637 23:40:33.379921 # # SIGILL reported for SVE2 SM4
11638 23:40:33.380345 # ok 18 # SKIP sigill_SVE2 SM4
11639 23:40:33.383041 # ok 19 cpuinfo_match_SVE2 I8MM
11640 23:40:33.386427 # # SIGILL reported for SVE2 I8MM
11641 23:40:33.389414 # ok 20 # SKIP sigill_SVE2 I8MM
11642 23:40:33.392945 # ok 21 cpuinfo_match_SVE2 F32MM
11643 23:40:33.396188 # # SIGILL reported for SVE2 F32MM
11644 23:40:33.399610 # ok 22 # SKIP sigill_SVE2 F32MM
11645 23:40:33.402600 # ok 23 cpuinfo_match_SVE2 F64MM
11646 23:40:33.405850 # # SIGILL reported for SVE2 F64MM
11647 23:40:33.406450 # ok 24 # SKIP sigill_SVE2 F64MM
11648 23:40:33.409002 # ok 25 cpuinfo_match_SVE2 BF16
11649 23:40:33.412634 # # SIGILL reported for SVE2 BF16
11650 23:40:33.416206 # ok 26 # SKIP sigill_SVE2 BF16
11651 23:40:33.419040 # ok 27 cpuinfo_match_SVE2 EBF16
11652 23:40:33.422747 # ok 28 # SKIP sigill_SVE2 EBF16
11653 23:40:33.426430 # # Totals: pass:16 fail:0 xfail:0 xpass:0 skip:12 error:0
11654 23:40:33.429340 ok 45 selftests: arm64: hwcap
11655 23:40:33.432906 # selftests: arm64: ptrace
11656 23:40:33.436178 # TAP version 13
11657 23:40:33.436698 # 1..7
11658 23:40:33.439599 # # Parent is 1496, child is 1497
11659 23:40:33.440134 # ok 1 read_tpidr_one
11660 23:40:33.442649 # ok 2 write_tpidr_one
11661 23:40:33.445697 # ok 3 verify_tpidr_one
11662 23:40:33.446125 # ok 4 count_tpidrs
11663 23:40:33.449265 # ok 5 tpidr2_write
11664 23:40:33.449747 # ok 6 tpidr2_read
11665 23:40:33.452743 # ok 7 write_tpidr_only
11666 23:40:33.455670 # # Totals: pass:7 fail:0 xfail:0 xpass:0 skip:0 error:0
11667 23:40:33.459317 ok 46 selftests: arm64: ptrace
11668 23:40:33.462851 # selftests: arm64: syscall-abi
11669 23:40:33.463277 # TAP version 13
11670 23:40:33.465502 # 1..2
11671 23:40:33.465965 # ok 1 getpid() FPSIMD
11672 23:40:33.468729 # ok 2 sched_yield() FPSIMD
11673 23:40:33.475699 # # Totals: pass:2 fail:0 xfail:0 xpass:0 skip:0 error:0
11674 23:40:33.478938 ok 47 selftests: arm64: syscall-abi
11675 23:40:33.479365 # selftests: arm64: tpidr2
11676 23:40:33.518383 # TAP version 13
11677 23:40:33.518941 # 1..5
11678 23:40:33.521359 # # PID: 1533
11679 23:40:33.521880 # # SME support not present
11680 23:40:33.524568 # ok 0 skipped, TPIDR2 not supported
11681 23:40:33.527995 # ok 1 skipped, TPIDR2 not supported
11682 23:40:33.531612 # ok 2 skipped, TPIDR2 not supported
11683 23:40:33.534680 # ok 3 skipped, TPIDR2 not supported
11684 23:40:33.537987 # ok 4 skipped, TPIDR2 not supported
11685 23:40:33.544336 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:5 error:0
11686 23:40:33.547663 ok 48 selftests: arm64: tpidr2
11687 23:40:34.178209 arm64_tags_test pass
11688 23:40:34.181657 arm64_run_tags_test_sh pass
11689 23:40:34.184890 arm64_fake_sigreturn_bad_magic pass
11690 23:40:34.188443 arm64_fake_sigreturn_bad_size pass
11691 23:40:34.191547 arm64_fake_sigreturn_bad_size_for_magic0 pass
11692 23:40:34.195210 arm64_fake_sigreturn_duplicated_fpsimd pass
11693 23:40:34.198274 arm64_fake_sigreturn_misaligned_sp pass
11694 23:40:34.201632 arm64_fake_sigreturn_missing_fpsimd pass
11695 23:40:34.204488 arm64_fake_sigreturn_sme_change_vl skip
11696 23:40:34.208363 arm64_fake_sigreturn_sve_change_vl skip
11697 23:40:34.214510 arm64_mangle_pstate_invalid_compat_toggle pass
11698 23:40:34.218634 arm64_mangle_pstate_invalid_daif_bits pass
11699 23:40:34.221471 arm64_mangle_pstate_invalid_mode_el1h pass
11700 23:40:34.224363 arm64_mangle_pstate_invalid_mode_el1t pass
11701 23:40:34.228413 arm64_mangle_pstate_invalid_mode_el2h pass
11702 23:40:34.234796 arm64_mangle_pstate_invalid_mode_el2t pass
11703 23:40:34.238154 arm64_mangle_pstate_invalid_mode_el3h pass
11704 23:40:34.241377 arm64_mangle_pstate_invalid_mode_el3t pass
11705 23:40:34.244535 arm64_sme_trap_no_sm skip
11706 23:40:34.245124 arm64_sme_trap_non_streaming skip
11707 23:40:34.247805 arm64_sme_trap_za pass
11708 23:40:34.250961 arm64_sme_vl skip
11709 23:40:34.251426 arm64_ssve_regs skip
11710 23:40:34.254890 arm64_sve_regs skip
11711 23:40:34.255451 arm64_sve_vl skip
11712 23:40:34.257793 arm64_za_no_regs skip
11713 23:40:34.258286 arm64_za_regs skip
11714 23:40:34.261047 arm64_pac_pauth_not_enabled skip
11715 23:40:34.264100 arm64_pac_pauth_not_enabled skip
11716 23:40:34.267609 arm64_pac_generic_pauth_not_enabled skip
11717 23:40:34.270540 arm64_pac_pauth_not_enabled skip
11718 23:40:34.274432 arm64_pac_pauth_not_enabled skip
11719 23:40:34.277610 arm64_pac_pauth_not_enabled skip
11720 23:40:34.280979 arm64_pac_generic_pauth_not_enabled skip
11721 23:40:34.281459 arm64_pac pass
11722 23:40:34.284068 arm64_fp-stress_FPSIMD-0-0 pass
11723 23:40:34.287531 arm64_fp-stress_FPSIMD-0-1 pass
11724 23:40:34.290909 arm64_fp-stress_FPSIMD-1-0 pass
11725 23:40:34.294271 arm64_fp-stress_FPSIMD-1-1 pass
11726 23:40:34.297296 arm64_fp-stress_FPSIMD-2-0 pass
11727 23:40:34.300698 arm64_fp-stress_FPSIMD-2-1 pass
11728 23:40:34.301261 arm64_fp-stress_FPSIMD-3-0 pass
11729 23:40:34.303825 arm64_fp-stress_FPSIMD-3-1 pass
11730 23:40:34.307188 arm64_fp-stress_FPSIMD-4-0 pass
11731 23:40:34.310433 arm64_fp-stress_FPSIMD-4-1 pass
11732 23:40:34.313830 arm64_fp-stress_FPSIMD-5-0 pass
11733 23:40:34.317040 arm64_fp-stress_FPSIMD-5-1 pass
11734 23:40:34.320422 arm64_fp-stress_FPSIMD-6-0 pass
11735 23:40:34.323446 arm64_fp-stress_FPSIMD-6-1 pass
11736 23:40:34.323915 arm64_fp-stress_FPSIMD-7-0 pass
11737 23:40:34.327107 arm64_fp-stress_FPSIMD-7-1 pass
11738 23:40:34.330324 arm64_fp-stress pass
11739 23:40:34.333937 arm64_sve-ptrace_sve_not_available skip
11740 23:40:34.336681 arm64_sve-ptrace skip
11741 23:40:34.340704 arm64_sve-probe-vls_sve_not_available skip
11742 23:40:34.341269 arm64_sve-probe-vls skip
11743 23:40:34.343651 arm64_vec-syscfg_sve_not_supported skip
11744 23:40:34.350325 arm64_vec-syscfg_sve_not_supported skip
11745 23:40:34.354151 arm64_vec-syscfg_sve_not_supported skip
11746 23:40:34.357258 arm64_vec-syscfg_sve_not_supported skip
11747 23:40:34.360063 arm64_vec-syscfg_sve_not_supported skip
11748 23:40:34.363439 arm64_vec-syscfg_sve_not_supported skip
11749 23:40:34.366857 arm64_vec-syscfg_sve_not_supported skip
11750 23:40:34.370212 arm64_vec-syscfg_sve_not_supported skip
11751 23:40:34.373527 arm64_vec-syscfg_sve_not_supported skip
11752 23:40:34.376864 arm64_vec-syscfg_sve_not_supported skip
11753 23:40:34.380079 arm64_vec-syscfg_sme_not_supported skip
11754 23:40:34.383481 arm64_vec-syscfg_sme_not_supported skip
11755 23:40:34.386584 arm64_vec-syscfg_sme_not_supported skip
11756 23:40:34.390519 arm64_vec-syscfg_sme_not_supported skip
11757 23:40:34.393457 arm64_vec-syscfg_sme_not_supported skip
11758 23:40:34.400212 arm64_vec-syscfg_sme_not_supported skip
11759 23:40:34.403096 arm64_vec-syscfg_sme_not_supported skip
11760 23:40:34.406924 arm64_vec-syscfg_sme_not_supported skip
11761 23:40:34.410229 arm64_vec-syscfg_sme_not_supported skip
11762 23:40:34.413022 arm64_vec-syscfg_sme_not_supported skip
11763 23:40:34.413496 arm64_vec-syscfg pass
11764 23:40:34.416260 arm64_za-fork_skipped pass
11765 23:40:34.420043 arm64_za-fork pass
11766 23:40:34.423086 arm64_za-ptrace_sme_not_available skip
11767 23:40:34.423635 arm64_za-ptrace skip
11768 23:40:34.426397 arm64_check_buffer_fill skip
11769 23:40:34.429673 arm64_check_child_memory skip
11770 23:40:34.432847 arm64_check_gcr_el1_cswitch skip
11771 23:40:34.436473 arm64_check_ksm_options skip
11772 23:40:34.436940 arm64_check_mmap_options skip
11773 23:40:34.439679 arm64_check_prctl_check_basic_read pass
11774 23:40:34.443186 arm64_check_prctl_NONE pass
11775 23:40:34.446716 arm64_check_prctl_sync skip
11776 23:40:34.450106 arm64_check_prctl_async skip
11777 23:40:34.453253 arm64_check_prctl_sync_async skip
11778 23:40:34.453720 arm64_check_prctl pass
11779 23:40:34.456548 arm64_check_tags_inclusion skip
11780 23:40:34.460113 arm64_check_user_mem skip
11781 23:40:34.463480 arm64_btitest_nohint_func_call_using_br_x0 skip
11782 23:40:34.466077 arm64_btitest_nohint_func_call_using_br_x16 skip
11783 23:40:34.473324 arm64_btitest_nohint_func_call_using_blr skip
11784 23:40:34.476662 arm64_btitest_bti_none_func_call_using_br_x0 skip
11785 23:40:34.479888 arm64_btitest_bti_none_func_call_using_br_x16 skip
11786 23:40:34.486257 arm64_btitest_bti_none_func_call_using_blr skip
11787 23:40:34.489911 arm64_btitest_bti_c_func_call_using_br_x0 skip
11788 23:40:34.492948 arm64_btitest_bti_c_func_call_using_br_x16 skip
11789 23:40:34.496578 arm64_btitest_bti_c_func_call_using_blr skip
11790 23:40:34.503189 arm64_btitest_bti_j_func_call_using_br_x0 skip
11791 23:40:34.505988 arm64_btitest_bti_j_func_call_using_br_x16 skip
11792 23:40:34.509567 arm64_btitest_bti_j_func_call_using_blr skip
11793 23:40:34.512469 arm64_btitest_bti_jc_func_call_using_br_x0 skip
11794 23:40:34.519011 arm64_btitest_bti_jc_func_call_using_br_x16 skip
11795 23:40:34.522508 arm64_btitest_bti_jc_func_call_using_blr skip
11796 23:40:34.525632 arm64_btitest_paciasp_func_call_using_br_x0 skip
11797 23:40:34.532313 arm64_btitest_paciasp_func_call_using_br_x16 skip
11798 23:40:34.535539 arm64_btitest_paciasp_func_call_using_blr skip
11799 23:40:34.535963 arm64_btitest pass
11800 23:40:34.541979 arm64_nobtitest_nohint_func_call_using_br_x0 skip
11801 23:40:34.545428 arm64_nobtitest_nohint_func_call_using_br_x16 skip
11802 23:40:34.548655 arm64_nobtitest_nohint_func_call_using_blr skip
11803 23:40:34.555580 arm64_nobtitest_bti_none_func_call_using_br_x0 skip
11804 23:40:34.558694 arm64_nobtitest_bti_none_func_call_using_br_x16 skip
11805 23:40:34.565325 arm64_nobtitest_bti_none_func_call_using_blr skip
11806 23:40:34.568705 arm64_nobtitest_bti_c_func_call_using_br_x0 skip
11807 23:40:34.571983 arm64_nobtitest_bti_c_func_call_using_br_x16 skip
11808 23:40:34.578570 arm64_nobtitest_bti_c_func_call_using_blr skip
11809 23:40:34.582044 arm64_nobtitest_bti_j_func_call_using_br_x0 skip
11810 23:40:34.585228 arm64_nobtitest_bti_j_func_call_using_br_x16 skip
11811 23:40:34.589063 arm64_nobtitest_bti_j_func_call_using_blr skip
11812 23:40:34.595250 arm64_nobtitest_bti_jc_func_call_using_br_x0 skip
11813 23:40:34.598329 arm64_nobtitest_bti_jc_func_call_using_br_x16 skip
11814 23:40:34.601862 arm64_nobtitest_bti_jc_func_call_using_blr skip
11815 23:40:34.608304 arm64_nobtitest_paciasp_func_call_using_br_x0 skip
11816 23:40:34.612142 arm64_nobtitest_paciasp_func_call_using_br_x16 skip
11817 23:40:34.614872 arm64_nobtitest_paciasp_func_call_using_blr skip
11818 23:40:34.618569 arm64_nobtitest pass
11819 23:40:34.621498 arm64_hwcap_cpuinfo_match_RNG pass
11820 23:40:34.624872 arm64_hwcap_sigill_rng skip
11821 23:40:34.628428 arm64_hwcap_cpuinfo_match_SME pass
11822 23:40:34.628853 arm64_hwcap_sigill_SME pass
11823 23:40:34.631280 arm64_hwcap_cpuinfo_match_SVE pass
11824 23:40:34.634947 arm64_hwcap_sigill_SVE pass
11825 23:40:34.638133 arm64_hwcap_cpuinfo_match_SVE_2 pass
11826 23:40:34.641608 arm64_hwcap_sigill_sve_2 skip
11827 23:40:34.644959 arm64_hwcap_cpuinfo_match_SVE_AES pass
11828 23:40:34.648012 arm64_hwcap_sigill_sve_aes skip
11829 23:40:34.651558 arm64_hwcap_cpuinfo_match_SVE2_PMULL pass
11830 23:40:34.655240 arm64_hwcap_sigill_sve2_pmull skip
11831 23:40:34.658066 arm64_hwcap_cpuinfo_match_SVE2_BITPERM pass
11832 23:40:34.661620 arm64_hwcap_sigill_sve2_bitperm skip
11833 23:40:34.664564 arm64_hwcap_cpuinfo_match_SVE2_SHA3 pass
11834 23:40:34.668334 arm64_hwcap_sigill_sve2_sha3 skip
11835 23:40:34.671462 arm64_hwcap_cpuinfo_match_SVE2_SM4 pass
11836 23:40:34.674850 arm64_hwcap_sigill_sve2_sm4 skip
11837 23:40:34.677730 arm64_hwcap_cpuinfo_match_SVE2_I8MM pass
11838 23:40:34.681175 arm64_hwcap_sigill_sve2_i8mm skip
11839 23:40:34.684425 arm64_hwcap_cpuinfo_match_SVE2_F32MM pass
11840 23:40:34.687784 arm64_hwcap_sigill_sve2_f32mm skip
11841 23:40:34.691132 arm64_hwcap_cpuinfo_match_SVE2_F64MM pass
11842 23:40:34.694413 arm64_hwcap_sigill_sve2_f64mm skip
11843 23:40:34.697772 arm64_hwcap_cpuinfo_match_SVE2_BF16 pass
11844 23:40:34.700997 arm64_hwcap_sigill_sve2_bf16 skip
11845 23:40:34.704049 arm64_hwcap_cpuinfo_match_SVE2_EBF16 pass
11846 23:40:34.707728 arm64_hwcap_sigill_sve2_ebf16 skip
11847 23:40:34.710974 arm64_hwcap pass
11848 23:40:34.714256 arm64_ptrace_read_tpidr_one pass
11849 23:40:34.718128 arm64_ptrace_write_tpidr_one pass
11850 23:40:34.721215 arm64_ptrace_verify_tpidr_one pass
11851 23:40:34.721684 arm64_ptrace_count_tpidrs pass
11852 23:40:34.724090 arm64_ptrace_tpidr2_write pass
11853 23:40:34.727633 arm64_ptrace_tpidr2_read pass
11854 23:40:34.731195 arm64_ptrace_write_tpidr_only pass
11855 23:40:34.731617 arm64_ptrace pass
11856 23:40:34.734658 arm64_syscall-abi_getpid_FPSIMD pass
11857 23:40:34.740714 arm64_syscall-abi_sched_yield_FPSIMD pass
11858 23:40:34.741135 arm64_syscall-abi pass
11859 23:40:34.747357 arm64_tpidr2_skipped_TPIDR2_not_supported pass
11860 23:40:34.750603 arm64_tpidr2_skipped_TPIDR2_not_supported pass
11861 23:40:34.753961 arm64_tpidr2_skipped_TPIDR2_not_supported pass
11862 23:40:34.757256 arm64_tpidr2_skipped_TPIDR2_not_supported pass
11863 23:40:34.764008 arm64_tpidr2_skipped_TPIDR2_not_supported pass
11864 23:40:34.764467 arm64_tpidr2 pass
11865 23:40:34.767457 + ../../utils/send-to-lava.sh ./output/result.txt
11866 23:40:34.774528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-arm64 RESULT=pass>
11867 23:40:34.775359 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-arm64 RESULT=pass
11869 23:40:34.781089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tags_test RESULT=pass>
11870 23:40:34.781808 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tags_test RESULT=pass
11872 23:40:34.787210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_run_tags_test_sh RESULT=pass>
11873 23:40:34.787905 Received signal: <TESTCASE> TEST_CASE_ID=arm64_run_tags_test_sh RESULT=pass
11875 23:40:34.794064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_magic RESULT=pass>
11876 23:40:34.794781 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_magic RESULT=pass
11878 23:40:34.823532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_size RESULT=pass>
11879 23:40:34.824256 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_size RESULT=pass
11881 23:40:34.885013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_size_for_magic0 RESULT=pass>
11882 23:40:34.885703 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_size_for_magic0 RESULT=pass
11884 23:40:34.948536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_duplicated_fpsimd RESULT=pass>
11885 23:40:34.949255 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_duplicated_fpsimd RESULT=pass
11887 23:40:35.010883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_misaligned_sp RESULT=pass>
11888 23:40:35.011686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_misaligned_sp RESULT=pass
11890 23:40:35.066443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_missing_fpsimd RESULT=pass>
11891 23:40:35.067258 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_missing_fpsimd RESULT=pass
11893 23:40:35.123724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_sme_change_vl RESULT=skip>
11894 23:40:35.124490 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_sme_change_vl RESULT=skip
11896 23:40:35.174911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_sve_change_vl RESULT=skip>
11897 23:40:35.175793 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_sve_change_vl RESULT=skip
11899 23:40:35.224412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_compat_toggle RESULT=pass>
11900 23:40:35.225102 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_compat_toggle RESULT=pass
11902 23:40:35.274671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_daif_bits RESULT=pass>
11903 23:40:35.275429 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_daif_bits RESULT=pass
11905 23:40:35.329928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1h RESULT=pass>
11906 23:40:35.330709 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1h RESULT=pass
11908 23:40:35.386896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1t RESULT=pass>
11909 23:40:35.387662 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1t RESULT=pass
11911 23:40:35.440770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2h RESULT=pass>
11912 23:40:35.441485 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2h RESULT=pass
11914 23:40:35.496004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2t RESULT=pass>
11915 23:40:35.496764 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2t RESULT=pass
11917 23:40:35.554868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3h RESULT=pass>
11918 23:40:35.555657 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3h RESULT=pass
11920 23:40:35.604806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3t RESULT=pass>
11921 23:40:35.605491 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3t RESULT=pass
11923 23:40:35.652445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_no_sm RESULT=skip>
11924 23:40:35.653297 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_no_sm RESULT=skip
11926 23:40:35.700863 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_non_streaming RESULT=skip
11928 23:40:35.704172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_non_streaming RESULT=skip>
11929 23:40:35.748766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_za RESULT=pass>
11930 23:40:35.749300 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_za RESULT=pass
11932 23:40:35.801495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_vl RESULT=skip>
11933 23:40:35.802242 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_vl RESULT=skip
11935 23:40:35.860261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ssve_regs RESULT=skip>
11936 23:40:35.861062 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ssve_regs RESULT=skip
11938 23:40:35.913021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve_regs RESULT=skip>
11939 23:40:35.913790 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve_regs RESULT=skip
11941 23:40:35.969054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve_vl RESULT=skip>
11942 23:40:35.969766 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve_vl RESULT=skip
11944 23:40:36.030120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za_no_regs RESULT=skip>
11945 23:40:36.030821 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za_no_regs RESULT=skip
11947 23:40:36.074605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za_regs RESULT=skip>
11948 23:40:36.074863 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za_regs RESULT=skip
11950 23:40:36.113414 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip
11952 23:40:36.115373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip>
11953 23:40:36.155540 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip
11955 23:40:36.158445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip>
11956 23:40:36.197525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_generic_pauth_not_enabled RESULT=skip>
11957 23:40:36.197811 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_generic_pauth_not_enabled RESULT=skip
11959 23:40:36.242899 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip
11961 23:40:36.245530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip>
11962 23:40:36.294344 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip
11964 23:40:36.297055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip>
11965 23:40:36.348023 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip
11967 23:40:36.351167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip>
11968 23:40:36.402252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_generic_pauth_not_enabled RESULT=skip>
11969 23:40:36.402979 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_generic_pauth_not_enabled RESULT=skip
11971 23:40:36.456321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac RESULT=pass>
11972 23:40:36.457057 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac RESULT=pass
11974 23:40:36.513800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-0 RESULT=pass>
11975 23:40:36.514730 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-0 RESULT=pass
11977 23:40:36.569213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-1 RESULT=pass>
11978 23:40:36.570035 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-1 RESULT=pass
11980 23:40:36.620773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-0 RESULT=pass>
11981 23:40:36.621463 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-0 RESULT=pass
11983 23:40:36.668756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-1 RESULT=pass>
11984 23:40:36.669449 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-1 RESULT=pass
11986 23:40:36.724250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-0 RESULT=pass>
11987 23:40:36.725042 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-0 RESULT=pass
11989 23:40:36.780139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-1 RESULT=pass>
11990 23:40:36.780826 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-1 RESULT=pass
11992 23:40:36.832688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-0 RESULT=pass>
11993 23:40:36.833442 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-0 RESULT=pass
11995 23:40:36.886556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-1 RESULT=pass>
11996 23:40:36.887280 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-1 RESULT=pass
11998 23:40:36.938889 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-0 RESULT=pass
12000 23:40:36.941225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-0 RESULT=pass>
12001 23:40:36.990674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-1 RESULT=pass>
12002 23:40:36.991415 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-1 RESULT=pass
12004 23:40:37.044865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-0 RESULT=pass>
12005 23:40:37.045674 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-0 RESULT=pass
12007 23:40:37.096880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-1 RESULT=pass>
12008 23:40:37.097643 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-1 RESULT=pass
12010 23:40:37.152224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-0 RESULT=pass>
12011 23:40:37.152950 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-0 RESULT=pass
12013 23:40:37.204679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-1 RESULT=pass>
12014 23:40:37.205479 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-1 RESULT=pass
12016 23:40:37.260268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-0 RESULT=pass>
12017 23:40:37.261019 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-0 RESULT=pass
12019 23:40:37.311329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-1 RESULT=pass>
12020 23:40:37.312067 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-1 RESULT=pass
12022 23:40:37.369048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress RESULT=pass>
12023 23:40:37.369743 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress RESULT=pass
12025 23:40:37.427512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_sve_not_available RESULT=skip>
12026 23:40:37.428300 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_sve_not_available RESULT=skip
12028 23:40:37.481245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace RESULT=skip>
12029 23:40:37.481620 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace RESULT=skip
12031 23:40:37.534201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls_sve_not_available RESULT=skip>
12032 23:40:37.535197 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls_sve_not_available RESULT=skip
12034 23:40:37.583256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls RESULT=skip>
12035 23:40:37.583970 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls RESULT=skip
12037 23:40:37.643188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12038 23:40:37.643936 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12040 23:40:37.701720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12041 23:40:37.702534 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12043 23:40:37.755491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12044 23:40:37.756389 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12046 23:40:37.809058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12047 23:40:37.809779 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12049 23:40:37.859528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12050 23:40:37.860226 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12052 23:40:37.908596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12053 23:40:37.909280 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12055 23:40:37.957878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12056 23:40:37.958576 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12058 23:40:38.014219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12059 23:40:38.014916 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12061 23:40:38.076436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12062 23:40:38.077208 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12064 23:40:38.133797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12065 23:40:38.134485 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12067 23:40:38.188913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12068 23:40:38.189641 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12070 23:40:38.245053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12071 23:40:38.245750 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12073 23:40:38.302157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12074 23:40:38.302872 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12076 23:40:38.359557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12077 23:40:38.360324 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12079 23:40:38.399187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12080 23:40:38.399445 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12082 23:40:38.444218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12083 23:40:38.444481 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12085 23:40:38.487018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12086 23:40:38.487302 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12088 23:40:38.532553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12089 23:40:38.533195 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12091 23:40:38.582191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12092 23:40:38.582885 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12094 23:40:38.633744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12095 23:40:38.634617 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12097 23:40:38.687467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg RESULT=pass>
12098 23:40:38.688207 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg RESULT=pass
12100 23:40:38.737952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-fork_skipped RESULT=pass>
12101 23:40:38.738639 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-fork_skipped RESULT=pass
12103 23:40:38.800718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-fork RESULT=pass>
12104 23:40:38.801437 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-fork RESULT=pass
12106 23:40:38.858894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_sme_not_available RESULT=skip>
12107 23:40:38.859584 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_sme_not_available RESULT=skip
12109 23:40:38.909347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace RESULT=skip>
12110 23:40:38.910095 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace RESULT=skip
12112 23:40:38.971329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill RESULT=skip>
12113 23:40:38.972157 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill RESULT=skip
12115 23:40:39.031749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory RESULT=skip>
12116 23:40:39.032567 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory RESULT=skip
12118 23:40:39.089794 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_gcr_el1_cswitch RESULT=skip
12120 23:40:39.092586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_gcr_el1_cswitch RESULT=skip>
12121 23:40:39.145246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_ksm_options RESULT=skip>
12122 23:40:39.145995 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_ksm_options RESULT=skip
12124 23:40:39.207876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options RESULT=skip>
12125 23:40:39.208581 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options RESULT=skip
12127 23:40:39.262325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_check_basic_read RESULT=pass>
12128 23:40:39.263013 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_check_basic_read RESULT=pass
12130 23:40:39.314171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_NONE RESULT=pass>
12131 23:40:39.314868 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_NONE RESULT=pass
12133 23:40:39.371015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_sync RESULT=skip>
12134 23:40:39.371723 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_sync RESULT=skip
12136 23:40:39.431616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_async RESULT=skip>
12137 23:40:39.432319 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_async RESULT=skip
12139 23:40:39.497665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_sync_async RESULT=skip>
12140 23:40:39.498480 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_sync_async RESULT=skip
12142 23:40:39.549179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl RESULT=pass>
12143 23:40:39.549921 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl RESULT=pass
12145 23:40:39.601072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_tags_inclusion RESULT=skip>
12146 23:40:39.601773 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_tags_inclusion RESULT=skip
12148 23:40:39.653246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem RESULT=skip>
12149 23:40:39.654017 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem RESULT=skip
12151 23:40:39.714409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x0 RESULT=skip>
12152 23:40:39.715107 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x0 RESULT=skip
12154 23:40:39.767485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x16 RESULT=skip>
12155 23:40:39.768199 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x16 RESULT=skip
12157 23:40:39.823012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_blr RESULT=skip>
12158 23:40:39.823695 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_blr RESULT=skip
12160 23:40:39.878628 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x0 RESULT=skip>
12161 23:40:39.879321 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x0 RESULT=skip
12163 23:40:39.932597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x16 RESULT=skip>
12164 23:40:39.933315 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x16 RESULT=skip
12166 23:40:39.982050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_blr RESULT=skip>
12167 23:40:39.982729 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_blr RESULT=skip
12169 23:40:40.033917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x0 RESULT=skip>
12170 23:40:40.034618 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x0 RESULT=skip
12172 23:40:40.093085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x16 RESULT=skip>
12173 23:40:40.093777 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x16 RESULT=skip
12175 23:40:40.145970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_blr RESULT=skip>
12176 23:40:40.146671 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_blr RESULT=skip
12178 23:40:40.199117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x0 RESULT=skip>
12179 23:40:40.199837 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x0 RESULT=skip
12181 23:40:40.249337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x16 RESULT=skip>
12182 23:40:40.250117 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x16 RESULT=skip
12184 23:40:40.311846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_blr RESULT=skip>
12185 23:40:40.312531 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_blr RESULT=skip
12187 23:40:40.366102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x0 RESULT=skip>
12188 23:40:40.366815 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x0 RESULT=skip
12190 23:40:40.423258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x16 RESULT=skip>
12191 23:40:40.423946 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x16 RESULT=skip
12193 23:40:40.474851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_blr RESULT=skip>
12194 23:40:40.475542 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_blr RESULT=skip
12196 23:40:40.526803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x0 RESULT=skip>
12197 23:40:40.527492 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x0 RESULT=skip
12199 23:40:40.577366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x16 RESULT=skip>
12200 23:40:40.578087 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x16 RESULT=skip
12202 23:40:40.625820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_blr RESULT=skip>
12203 23:40:40.626589 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_blr RESULT=skip
12205 23:40:40.667685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest RESULT=pass>
12206 23:40:40.668372 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest RESULT=pass
12208 23:40:40.721255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x0 RESULT=skip>
12209 23:40:40.721525 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x0 RESULT=skip
12211 23:40:40.764010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x16 RESULT=skip>
12212 23:40:40.764724 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x16 RESULT=skip
12214 23:40:40.816625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_blr RESULT=skip>
12215 23:40:40.816884 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_blr RESULT=skip
12217 23:40:40.864386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x0 RESULT=skip>
12218 23:40:40.865078 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x0 RESULT=skip
12220 23:40:40.916681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x16 RESULT=skip>
12221 23:40:40.917363 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x16 RESULT=skip
12223 23:40:40.972484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_blr RESULT=skip>
12224 23:40:40.973172 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_blr RESULT=skip
12226 23:40:41.025852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x0 RESULT=skip>
12227 23:40:41.026540 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x0 RESULT=skip
12229 23:40:41.076109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x16 RESULT=skip>
12230 23:40:41.076827 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x16 RESULT=skip
12232 23:40:41.133061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_blr RESULT=skip>
12233 23:40:41.133752 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_blr RESULT=skip
12235 23:40:41.184009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x0 RESULT=skip>
12236 23:40:41.184690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x0 RESULT=skip
12238 23:40:41.234603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x16 RESULT=skip>
12239 23:40:41.234871 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x16 RESULT=skip
12241 23:40:41.282048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_blr RESULT=skip>
12242 23:40:41.282374 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_blr RESULT=skip
12244 23:40:41.326442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x0 RESULT=skip>
12245 23:40:41.326740 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x0 RESULT=skip
12247 23:40:41.374650 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x16 RESULT=skip>
12248 23:40:41.375343 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x16 RESULT=skip
12250 23:40:41.421765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_blr RESULT=skip>
12251 23:40:41.422103 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_blr RESULT=skip
12253 23:40:41.464200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x0 RESULT=skip>
12254 23:40:41.464480 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x0 RESULT=skip
12256 23:40:41.508416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x16 RESULT=skip>
12257 23:40:41.508959 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x16 RESULT=skip
12259 23:40:41.560643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_blr RESULT=skip>
12260 23:40:41.561351 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_blr RESULT=skip
12262 23:40:41.607299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest RESULT=pass>
12263 23:40:41.607579 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest RESULT=pass
12265 23:40:41.661833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_RNG RESULT=pass>
12266 23:40:41.662123 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_RNG RESULT=pass
12268 23:40:41.697981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_rng RESULT=skip>
12269 23:40:41.698310 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_rng RESULT=skip
12271 23:40:41.746131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SME RESULT=pass>
12272 23:40:41.746419 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SME RESULT=pass
12274 23:40:41.784627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SME RESULT=pass>
12275 23:40:41.784883 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SME RESULT=pass
12277 23:40:41.830498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE RESULT=pass>
12278 23:40:41.830760 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE RESULT=pass
12280 23:40:41.874607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE RESULT=pass>
12281 23:40:41.874948 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE RESULT=pass
12283 23:40:41.925069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_2 RESULT=pass>
12284 23:40:41.925983 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_2 RESULT=pass
12286 23:40:41.969639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve_2 RESULT=skip>
12287 23:40:41.970569 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve_2 RESULT=skip
12289 23:40:42.025352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_AES RESULT=pass>
12290 23:40:42.026125 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_AES RESULT=pass
12292 23:40:42.079750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve_aes RESULT=skip>
12293 23:40:42.080450 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve_aes RESULT=skip
12295 23:40:42.133946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_PMULL RESULT=pass>
12296 23:40:42.134714 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_PMULL RESULT=pass
12298 23:40:42.190024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_pmull RESULT=skip>
12299 23:40:42.190713 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_pmull RESULT=skip
12301 23:40:42.244732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BITPERM RESULT=pass>
12302 23:40:42.245420 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BITPERM RESULT=pass
12304 23:40:42.302307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_bitperm RESULT=skip>
12305 23:40:42.302986 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_bitperm RESULT=skip
12307 23:40:42.358824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SHA3 RESULT=pass>
12308 23:40:42.359515 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SHA3 RESULT=pass
12310 23:40:42.410401 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_sha3 RESULT=skip
12312 23:40:42.413530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_sha3 RESULT=skip>
12313 23:40:42.472558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SM4 RESULT=pass>
12314 23:40:42.473363 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SM4 RESULT=pass
12316 23:40:42.514986 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_sm4 RESULT=skip
12318 23:40:42.517990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_sm4 RESULT=skip>
12319 23:40:42.561738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_I8MM RESULT=pass>
12320 23:40:42.562108 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_I8MM RESULT=pass
12322 23:40:42.611193 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_i8mm RESULT=skip
12324 23:40:42.614276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_i8mm RESULT=skip>
12325 23:40:42.663527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F32MM RESULT=pass>
12326 23:40:42.664253 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F32MM RESULT=pass
12328 23:40:42.715469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_f32mm RESULT=skip>
12329 23:40:42.716353 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_f32mm RESULT=skip
12331 23:40:42.766130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F64MM RESULT=pass>
12332 23:40:42.766897 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F64MM RESULT=pass
12334 23:40:42.816335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_f64mm RESULT=skip>
12335 23:40:42.817066 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_f64mm RESULT=skip
12337 23:40:42.865602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BF16 RESULT=pass>
12338 23:40:42.866394 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BF16 RESULT=pass
12340 23:40:42.914087 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_bf16 RESULT=skip
12342 23:40:42.917102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_bf16 RESULT=skip>
12343 23:40:42.972956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_EBF16 RESULT=pass>
12344 23:40:42.973900 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_EBF16 RESULT=pass
12346 23:40:43.024195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_ebf16 RESULT=skip>
12347 23:40:43.024980 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_ebf16 RESULT=skip
12349 23:40:43.071268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap RESULT=pass>
12350 23:40:43.071955 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap RESULT=pass
12352 23:40:43.126948 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_read_tpidr_one RESULT=pass
12354 23:40:43.129708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_read_tpidr_one RESULT=pass>
12355 23:40:43.179403 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_write_tpidr_one RESULT=pass
12357 23:40:43.182135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_write_tpidr_one RESULT=pass>
12358 23:40:43.233018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_verify_tpidr_one RESULT=pass>
12359 23:40:43.233752 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_verify_tpidr_one RESULT=pass
12361 23:40:43.282776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_count_tpidrs RESULT=pass>
12362 23:40:43.283486 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_count_tpidrs RESULT=pass
12364 23:40:43.337144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_tpidr2_write RESULT=pass>
12365 23:40:43.337923 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_tpidr2_write RESULT=pass
12367 23:40:43.389621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_tpidr2_read RESULT=pass>
12368 23:40:43.390347 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_tpidr2_read RESULT=pass
12370 23:40:43.446057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_write_tpidr_only RESULT=pass>
12371 23:40:43.446771 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_write_tpidr_only RESULT=pass
12373 23:40:43.498242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace RESULT=pass>
12374 23:40:43.498926 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace RESULT=pass
12376 23:40:43.557739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_FPSIMD RESULT=pass>
12377 23:40:43.558443 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_FPSIMD RESULT=pass
12379 23:40:43.614071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_FPSIMD RESULT=pass>
12380 23:40:43.614335 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_FPSIMD RESULT=pass
12382 23:40:43.658116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi RESULT=pass>
12383 23:40:43.658379 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi RESULT=pass
12385 23:40:43.706306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12386 23:40:43.706594 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12388 23:40:43.755430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12389 23:40:43.756469 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12391 23:40:43.806644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12392 23:40:43.807463 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12394 23:40:43.859736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12395 23:40:43.860525 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12397 23:40:43.912838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12398 23:40:43.913535 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12400 23:40:43.962651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2 RESULT=pass>
12401 23:40:43.963097 + set +x
12402 23:40:43.963690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2 RESULT=pass
12404 23:40:43.969278 <LAVA_SIGNAL_ENDRUN 1_kselftest-arm64 12172444_1.6.2.3.5>
12405 23:40:43.970004 Received signal: <ENDRUN> 1_kselftest-arm64 12172444_1.6.2.3.5
12406 23:40:43.970383 Ending use of test pattern.
12407 23:40:43.970718 Ending test lava.1_kselftest-arm64 (12172444_1.6.2.3.5), duration 33.28
12409 23:40:43.972837 <LAVA_TEST_RUNNER EXIT>
12410 23:40:43.973503 ok: lava_test_shell seems to have completed
12411 23:40:43.978384 arm64_btitest: pass
arm64_btitest_bti_c_func_call_using_blr: skip
arm64_btitest_bti_c_func_call_using_br_x0: skip
arm64_btitest_bti_c_func_call_using_br_x16: skip
arm64_btitest_bti_j_func_call_using_blr: skip
arm64_btitest_bti_j_func_call_using_br_x0: skip
arm64_btitest_bti_j_func_call_using_br_x16: skip
arm64_btitest_bti_jc_func_call_using_blr: skip
arm64_btitest_bti_jc_func_call_using_br_x0: skip
arm64_btitest_bti_jc_func_call_using_br_x16: skip
arm64_btitest_bti_none_func_call_using_blr: skip
arm64_btitest_bti_none_func_call_using_br_x0: skip
arm64_btitest_bti_none_func_call_using_br_x16: skip
arm64_btitest_nohint_func_call_using_blr: skip
arm64_btitest_nohint_func_call_using_br_x0: skip
arm64_btitest_nohint_func_call_using_br_x16: skip
arm64_btitest_paciasp_func_call_using_blr: skip
arm64_btitest_paciasp_func_call_using_br_x0: skip
arm64_btitest_paciasp_func_call_using_br_x16: skip
arm64_check_buffer_fill: skip
arm64_check_child_memory: skip
arm64_check_gcr_el1_cswitch: skip
arm64_check_ksm_options: skip
arm64_check_mmap_options: skip
arm64_check_prctl: pass
arm64_check_prctl_NONE: pass
arm64_check_prctl_async: skip
arm64_check_prctl_check_basic_read: pass
arm64_check_prctl_sync: skip
arm64_check_prctl_sync_async: skip
arm64_check_tags_inclusion: skip
arm64_check_user_mem: skip
arm64_fake_sigreturn_bad_magic: pass
arm64_fake_sigreturn_bad_size: pass
arm64_fake_sigreturn_bad_size_for_magic0: pass
arm64_fake_sigreturn_duplicated_fpsimd: pass
arm64_fake_sigreturn_misaligned_sp: pass
arm64_fake_sigreturn_missing_fpsimd: pass
arm64_fake_sigreturn_sme_change_vl: skip
arm64_fake_sigreturn_sve_change_vl: skip
arm64_fp-stress: pass
arm64_fp-stress_FPSIMD-0-0: pass
arm64_fp-stress_FPSIMD-0-1: pass
arm64_fp-stress_FPSIMD-1-0: pass
arm64_fp-stress_FPSIMD-1-1: pass
arm64_fp-stress_FPSIMD-2-0: pass
arm64_fp-stress_FPSIMD-2-1: pass
arm64_fp-stress_FPSIMD-3-0: pass
arm64_fp-stress_FPSIMD-3-1: pass
arm64_fp-stress_FPSIMD-4-0: pass
arm64_fp-stress_FPSIMD-4-1: pass
arm64_fp-stress_FPSIMD-5-0: pass
arm64_fp-stress_FPSIMD-5-1: pass
arm64_fp-stress_FPSIMD-6-0: pass
arm64_fp-stress_FPSIMD-6-1: pass
arm64_fp-stress_FPSIMD-7-0: pass
arm64_fp-stress_FPSIMD-7-1: pass
arm64_hwcap: pass
arm64_hwcap_cpuinfo_match_RNG: pass
arm64_hwcap_cpuinfo_match_SME: pass
arm64_hwcap_cpuinfo_match_SVE: pass
arm64_hwcap_cpuinfo_match_SVE2_BF16: pass
arm64_hwcap_cpuinfo_match_SVE2_BITPERM: pass
arm64_hwcap_cpuinfo_match_SVE2_EBF16: pass
arm64_hwcap_cpuinfo_match_SVE2_F32MM: pass
arm64_hwcap_cpuinfo_match_SVE2_F64MM: pass
arm64_hwcap_cpuinfo_match_SVE2_I8MM: pass
arm64_hwcap_cpuinfo_match_SVE2_PMULL: pass
arm64_hwcap_cpuinfo_match_SVE2_SHA3: pass
arm64_hwcap_cpuinfo_match_SVE2_SM4: pass
arm64_hwcap_cpuinfo_match_SVE_2: pass
arm64_hwcap_cpuinfo_match_SVE_AES: pass
arm64_hwcap_sigill_SME: pass
arm64_hwcap_sigill_SVE: pass
arm64_hwcap_sigill_rng: skip
arm64_hwcap_sigill_sve2_bf16: skip
arm64_hwcap_sigill_sve2_bitperm: skip
arm64_hwcap_sigill_sve2_ebf16: skip
arm64_hwcap_sigill_sve2_f32mm: skip
arm64_hwcap_sigill_sve2_f64mm: skip
arm64_hwcap_sigill_sve2_i8mm: skip
arm64_hwcap_sigill_sve2_pmull: skip
arm64_hwcap_sigill_sve2_sha3: skip
arm64_hwcap_sigill_sve2_sm4: skip
arm64_hwcap_sigill_sve_2: skip
arm64_hwcap_sigill_sve_aes: skip
arm64_mangle_pstate_invalid_compat_toggle: pass
arm64_mangle_pstate_invalid_daif_bits: pass
arm64_mangle_pstate_invalid_mode_el1h: pass
arm64_mangle_pstate_invalid_mode_el1t: pass
arm64_mangle_pstate_invalid_mode_el2h: pass
arm64_mangle_pstate_invalid_mode_el2t: pass
arm64_mangle_pstate_invalid_mode_el3h: pass
arm64_mangle_pstate_invalid_mode_el3t: pass
arm64_nobtitest: pass
arm64_nobtitest_bti_c_func_call_using_blr: skip
arm64_nobtitest_bti_c_func_call_using_br_x0: skip
arm64_nobtitest_bti_c_func_call_using_br_x16: skip
arm64_nobtitest_bti_j_func_call_using_blr: skip
arm64_nobtitest_bti_j_func_call_using_br_x0: skip
arm64_nobtitest_bti_j_func_call_using_br_x16: skip
arm64_nobtitest_bti_jc_func_call_using_blr: skip
arm64_nobtitest_bti_jc_func_call_using_br_x0: skip
arm64_nobtitest_bti_jc_func_call_using_br_x16: skip
arm64_nobtitest_bti_none_func_call_using_blr: skip
arm64_nobtitest_bti_none_func_call_using_br_x0: skip
arm64_nobtitest_bti_none_func_call_using_br_x16: skip
arm64_nobtitest_nohint_func_call_using_blr: skip
arm64_nobtitest_nohint_func_call_using_br_x0: skip
arm64_nobtitest_nohint_func_call_using_br_x16: skip
arm64_nobtitest_paciasp_func_call_using_blr: skip
arm64_nobtitest_paciasp_func_call_using_br_x0: skip
arm64_nobtitest_paciasp_func_call_using_br_x16: skip
arm64_pac: pass
arm64_pac_generic_pauth_not_enabled: skip
arm64_pac_pauth_not_enabled: skip
arm64_ptrace: pass
arm64_ptrace_count_tpidrs: pass
arm64_ptrace_read_tpidr_one: pass
arm64_ptrace_tpidr2_read: pass
arm64_ptrace_tpidr2_write: pass
arm64_ptrace_verify_tpidr_one: pass
arm64_ptrace_write_tpidr_one: pass
arm64_ptrace_write_tpidr_only: pass
arm64_run_tags_test_sh: pass
arm64_sme_trap_no_sm: skip
arm64_sme_trap_non_streaming: skip
arm64_sme_trap_za: pass
arm64_sme_vl: skip
arm64_ssve_regs: skip
arm64_sve-probe-vls: skip
arm64_sve-probe-vls_sve_not_available: skip
arm64_sve-ptrace: skip
arm64_sve-ptrace_sve_not_available: skip
arm64_sve_regs: skip
arm64_sve_vl: skip
arm64_syscall-abi: pass
arm64_syscall-abi_getpid_FPSIMD: pass
arm64_syscall-abi_sched_yield_FPSIMD: pass
arm64_tags_test: pass
arm64_tpidr2: pass
arm64_tpidr2_skipped_TPIDR2_not_supported: pass
arm64_vec-syscfg: pass
arm64_vec-syscfg_sme_not_supported: skip
arm64_vec-syscfg_sve_not_supported: skip
arm64_za-fork: pass
arm64_za-fork_skipped: pass
arm64_za-ptrace: skip
arm64_za-ptrace_sme_not_available: skip
arm64_za_no_regs: skip
arm64_za_regs: skip
shardfile-arm64: pass
12412 23:40:43.979089 end: 3.1 lava-test-shell (duration 00:00:34) [common]
12413 23:40:43.979537 end: 3 lava-test-retry (duration 00:00:34) [common]
12414 23:40:43.979976 start: 4 finalize (timeout 00:07:22) [common]
12415 23:40:43.980425 start: 4.1 power-off (timeout 00:00:30) [common]
12416 23:40:43.981167 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=off'
12417 23:40:44.105102 >> Command sent successfully.
12418 23:40:44.109521 Returned 0 in 0 seconds
12419 23:40:44.210487 end: 4.1 power-off (duration 00:00:00) [common]
12421 23:40:44.212042 start: 4.2 read-feedback (timeout 00:07:21) [common]
12422 23:40:44.213414 Listened to connection for namespace 'common' for up to 1s
12423 23:40:45.213848 Finalising connection for namespace 'common'
12424 23:40:45.214518 Disconnecting from shell: Finalise
12425 23:40:45.214957 / #
12426 23:40:45.315992 end: 4.2 read-feedback (duration 00:00:01) [common]
12427 23:40:45.316707 end: 4 finalize (duration 00:00:01) [common]
12428 23:40:45.317313 Cleaning after the job
12429 23:40:45.317894 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12172444/tftp-deploy-t846xybh/ramdisk
12430 23:40:45.331913 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12172444/tftp-deploy-t846xybh/kernel
12431 23:40:45.370069 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12172444/tftp-deploy-t846xybh/dtb
12432 23:40:45.370374 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12172444/tftp-deploy-t846xybh/nfsrootfs
12433 23:40:45.464344 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12172444/tftp-deploy-t846xybh/modules
12434 23:40:45.471751 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12172444
12435 23:40:46.112000 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12172444
12436 23:40:46.112181 Job finished correctly