Boot log: mt8192-asurada-spherion-r0
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 24
- Kernel Errors: 35
- Errors: 0
1 23:34:04.082540 lava-dispatcher, installed at version: 2023.10
2 23:34:04.082745 start: 0 validate
3 23:34:04.082874 Start time: 2023-12-03 23:34:04.082866+00:00 (UTC)
4 23:34:04.082994 Using caching service: 'http://localhost/cache/?uri=%s'
5 23:34:04.083126 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230623.0%2Farm64%2Finitrd.cpio.gz exists
6 23:34:04.368426 Using caching service: 'http://localhost/cache/?uri=%s'
7 23:34:04.369471 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.64-cip10-rt5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 23:34:04.640190 Using caching service: 'http://localhost/cache/?uri=%s'
9 23:34:04.641016 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.64-cip10-rt5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 23:34:04.911209 Using caching service: 'http://localhost/cache/?uri=%s'
11 23:34:04.911993 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230623.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 23:34:05.181653 Using caching service: 'http://localhost/cache/?uri=%s'
13 23:34:05.182434 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.64-cip10-rt5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 23:34:05.459515 validate duration: 1.38
16 23:34:05.460763 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 23:34:05.461317 start: 1.1 download-retry (timeout 00:10:00) [common]
18 23:34:05.461912 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 23:34:05.462574 Not decompressing ramdisk as can be used compressed.
20 23:34:05.463081 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230623.0/arm64/initrd.cpio.gz
21 23:34:05.463460 saving as /var/lib/lava/dispatcher/tmp/12172440/tftp-deploy-jip4knts/ramdisk/initrd.cpio.gz
22 23:34:05.463864 total size: 4665395 (4 MB)
23 23:34:05.469061 progress 0 % (0 MB)
24 23:34:05.477499 progress 5 % (0 MB)
25 23:34:05.484461 progress 10 % (0 MB)
26 23:34:05.489368 progress 15 % (0 MB)
27 23:34:05.493016 progress 20 % (0 MB)
28 23:34:05.496127 progress 25 % (1 MB)
29 23:34:05.499141 progress 30 % (1 MB)
30 23:34:05.501501 progress 35 % (1 MB)
31 23:34:05.503889 progress 40 % (1 MB)
32 23:34:05.506219 progress 45 % (2 MB)
33 23:34:05.508246 progress 50 % (2 MB)
34 23:34:05.510157 progress 55 % (2 MB)
35 23:34:05.511931 progress 60 % (2 MB)
36 23:34:05.513833 progress 65 % (2 MB)
37 23:34:05.515439 progress 70 % (3 MB)
38 23:34:05.517002 progress 75 % (3 MB)
39 23:34:05.518586 progress 80 % (3 MB)
40 23:34:05.520238 progress 85 % (3 MB)
41 23:34:05.521702 progress 90 % (4 MB)
42 23:34:05.523114 progress 95 % (4 MB)
43 23:34:05.524499 progress 100 % (4 MB)
44 23:34:05.524658 4 MB downloaded in 0.06 s (73.16 MB/s)
45 23:34:05.524812 end: 1.1.1 http-download (duration 00:00:00) [common]
47 23:34:05.525068 end: 1.1 download-retry (duration 00:00:00) [common]
48 23:34:05.525158 start: 1.2 download-retry (timeout 00:10:00) [common]
49 23:34:05.525246 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 23:34:05.525384 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.64-cip10-rt5/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 23:34:05.525459 saving as /var/lib/lava/dispatcher/tmp/12172440/tftp-deploy-jip4knts/kernel/Image
52 23:34:05.525523 total size: 49172992 (46 MB)
53 23:34:05.525596 No compression specified
54 23:34:05.526738 progress 0 % (0 MB)
55 23:34:05.539661 progress 5 % (2 MB)
56 23:34:05.552338 progress 10 % (4 MB)
57 23:34:05.565076 progress 15 % (7 MB)
58 23:34:05.577753 progress 20 % (9 MB)
59 23:34:05.590416 progress 25 % (11 MB)
60 23:34:05.603149 progress 30 % (14 MB)
61 23:34:05.615800 progress 35 % (16 MB)
62 23:34:05.628612 progress 40 % (18 MB)
63 23:34:05.641407 progress 45 % (21 MB)
64 23:34:05.654105 progress 50 % (23 MB)
65 23:34:05.666585 progress 55 % (25 MB)
66 23:34:05.679277 progress 60 % (28 MB)
67 23:34:05.691768 progress 65 % (30 MB)
68 23:34:05.704476 progress 70 % (32 MB)
69 23:34:05.717048 progress 75 % (35 MB)
70 23:34:05.729619 progress 80 % (37 MB)
71 23:34:05.742350 progress 85 % (39 MB)
72 23:34:05.755076 progress 90 % (42 MB)
73 23:34:05.767510 progress 95 % (44 MB)
74 23:34:05.779882 progress 100 % (46 MB)
75 23:34:05.780087 46 MB downloaded in 0.25 s (184.22 MB/s)
76 23:34:05.780233 end: 1.2.1 http-download (duration 00:00:00) [common]
78 23:34:05.780462 end: 1.2 download-retry (duration 00:00:00) [common]
79 23:34:05.780551 start: 1.3 download-retry (timeout 00:10:00) [common]
80 23:34:05.780636 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 23:34:05.780775 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.64-cip10-rt5/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 23:34:05.780844 saving as /var/lib/lava/dispatcher/tmp/12172440/tftp-deploy-jip4knts/dtb/mt8192-asurada-spherion-r0.dtb
83 23:34:05.780939 total size: 47278 (0 MB)
84 23:34:05.781037 No compression specified
85 23:34:05.782203 progress 69 % (0 MB)
86 23:34:05.782471 progress 100 % (0 MB)
87 23:34:05.782625 0 MB downloaded in 0.00 s (26.78 MB/s)
88 23:34:05.782746 end: 1.3.1 http-download (duration 00:00:00) [common]
90 23:34:05.782972 end: 1.3 download-retry (duration 00:00:00) [common]
91 23:34:05.783058 start: 1.4 download-retry (timeout 00:10:00) [common]
92 23:34:05.783139 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 23:34:05.783253 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230623.0/arm64/full.rootfs.tar.xz
94 23:34:05.783320 saving as /var/lib/lava/dispatcher/tmp/12172440/tftp-deploy-jip4knts/nfsrootfs/full.rootfs.tar
95 23:34:05.783380 total size: 200813988 (191 MB)
96 23:34:05.783440 Using unxz to decompress xz
97 23:34:05.787481 progress 0 % (0 MB)
98 23:34:06.309372 progress 5 % (9 MB)
99 23:34:06.818973 progress 10 % (19 MB)
100 23:34:07.395929 progress 15 % (28 MB)
101 23:34:07.766988 progress 20 % (38 MB)
102 23:34:08.087877 progress 25 % (47 MB)
103 23:34:08.673522 progress 30 % (57 MB)
104 23:34:09.229479 progress 35 % (67 MB)
105 23:34:09.815338 progress 40 % (76 MB)
106 23:34:10.369283 progress 45 % (86 MB)
107 23:34:10.949375 progress 50 % (95 MB)
108 23:34:11.570830 progress 55 % (105 MB)
109 23:34:12.228992 progress 60 % (114 MB)
110 23:34:12.345268 progress 65 % (124 MB)
111 23:34:12.483439 progress 70 % (134 MB)
112 23:34:12.578697 progress 75 % (143 MB)
113 23:34:12.649808 progress 80 % (153 MB)
114 23:34:12.717846 progress 85 % (162 MB)
115 23:34:12.817987 progress 90 % (172 MB)
116 23:34:13.091623 progress 95 % (181 MB)
117 23:34:13.658545 progress 100 % (191 MB)
118 23:34:13.663787 191 MB downloaded in 7.88 s (24.30 MB/s)
119 23:34:13.664046 end: 1.4.1 http-download (duration 00:00:08) [common]
121 23:34:13.664310 end: 1.4 download-retry (duration 00:00:08) [common]
122 23:34:13.664401 start: 1.5 download-retry (timeout 00:09:52) [common]
123 23:34:13.664489 start: 1.5.1 http-download (timeout 00:09:52) [common]
124 23:34:13.664649 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.64-cip10-rt5/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 23:34:13.664721 saving as /var/lib/lava/dispatcher/tmp/12172440/tftp-deploy-jip4knts/modules/modules.tar
126 23:34:13.664785 total size: 8614132 (8 MB)
127 23:34:13.664851 Using unxz to decompress xz
128 23:34:13.669141 progress 0 % (0 MB)
129 23:34:13.690080 progress 5 % (0 MB)
130 23:34:13.714061 progress 10 % (0 MB)
131 23:34:13.737301 progress 15 % (1 MB)
132 23:34:13.760538 progress 20 % (1 MB)
133 23:34:13.784227 progress 25 % (2 MB)
134 23:34:13.809828 progress 30 % (2 MB)
135 23:34:13.835731 progress 35 % (2 MB)
136 23:34:13.858905 progress 40 % (3 MB)
137 23:34:13.882850 progress 45 % (3 MB)
138 23:34:13.912645 progress 50 % (4 MB)
139 23:34:13.940513 progress 55 % (4 MB)
140 23:34:13.968890 progress 60 % (4 MB)
141 23:34:13.997824 progress 65 % (5 MB)
142 23:34:14.027991 progress 70 % (5 MB)
143 23:34:14.055096 progress 75 % (6 MB)
144 23:34:14.084424 progress 80 % (6 MB)
145 23:34:14.112810 progress 85 % (7 MB)
146 23:34:14.140457 progress 90 % (7 MB)
147 23:34:14.173344 progress 95 % (7 MB)
148 23:34:14.204002 progress 100 % (8 MB)
149 23:34:14.211915 8 MB downloaded in 0.55 s (15.02 MB/s)
150 23:34:14.212200 end: 1.5.1 http-download (duration 00:00:01) [common]
152 23:34:14.212498 end: 1.5 download-retry (duration 00:00:01) [common]
153 23:34:14.212608 start: 1.6 prepare-tftp-overlay (timeout 00:09:51) [common]
154 23:34:14.212720 start: 1.6.1 extract-nfsrootfs (timeout 00:09:51) [common]
155 23:34:17.693197 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/12172440/extract-nfsrootfs-4jgnn23a
156 23:34:17.693412 end: 1.6.1 extract-nfsrootfs (duration 00:00:03) [common]
157 23:34:17.693560 start: 1.6.2 lava-overlay (timeout 00:09:48) [common]
158 23:34:17.694143 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12172440/lava-overlay-qbgttqq8
159 23:34:17.694327 makedir: /var/lib/lava/dispatcher/tmp/12172440/lava-overlay-qbgttqq8/lava-12172440/bin
160 23:34:17.694476 makedir: /var/lib/lava/dispatcher/tmp/12172440/lava-overlay-qbgttqq8/lava-12172440/tests
161 23:34:17.694625 makedir: /var/lib/lava/dispatcher/tmp/12172440/lava-overlay-qbgttqq8/lava-12172440/results
162 23:34:17.694776 Creating /var/lib/lava/dispatcher/tmp/12172440/lava-overlay-qbgttqq8/lava-12172440/bin/lava-add-keys
163 23:34:17.694992 Creating /var/lib/lava/dispatcher/tmp/12172440/lava-overlay-qbgttqq8/lava-12172440/bin/lava-add-sources
164 23:34:17.695154 Creating /var/lib/lava/dispatcher/tmp/12172440/lava-overlay-qbgttqq8/lava-12172440/bin/lava-background-process-start
165 23:34:17.695287 Creating /var/lib/lava/dispatcher/tmp/12172440/lava-overlay-qbgttqq8/lava-12172440/bin/lava-background-process-stop
166 23:34:17.695416 Creating /var/lib/lava/dispatcher/tmp/12172440/lava-overlay-qbgttqq8/lava-12172440/bin/lava-common-functions
167 23:34:17.695543 Creating /var/lib/lava/dispatcher/tmp/12172440/lava-overlay-qbgttqq8/lava-12172440/bin/lava-echo-ipv4
168 23:34:17.695670 Creating /var/lib/lava/dispatcher/tmp/12172440/lava-overlay-qbgttqq8/lava-12172440/bin/lava-install-packages
169 23:34:17.695795 Creating /var/lib/lava/dispatcher/tmp/12172440/lava-overlay-qbgttqq8/lava-12172440/bin/lava-installed-packages
170 23:34:17.695918 Creating /var/lib/lava/dispatcher/tmp/12172440/lava-overlay-qbgttqq8/lava-12172440/bin/lava-os-build
171 23:34:17.696043 Creating /var/lib/lava/dispatcher/tmp/12172440/lava-overlay-qbgttqq8/lava-12172440/bin/lava-probe-channel
172 23:34:17.696168 Creating /var/lib/lava/dispatcher/tmp/12172440/lava-overlay-qbgttqq8/lava-12172440/bin/lava-probe-ip
173 23:34:17.696292 Creating /var/lib/lava/dispatcher/tmp/12172440/lava-overlay-qbgttqq8/lava-12172440/bin/lava-target-ip
174 23:34:17.696417 Creating /var/lib/lava/dispatcher/tmp/12172440/lava-overlay-qbgttqq8/lava-12172440/bin/lava-target-mac
175 23:34:17.696544 Creating /var/lib/lava/dispatcher/tmp/12172440/lava-overlay-qbgttqq8/lava-12172440/bin/lava-target-storage
176 23:34:17.696672 Creating /var/lib/lava/dispatcher/tmp/12172440/lava-overlay-qbgttqq8/lava-12172440/bin/lava-test-case
177 23:34:17.696800 Creating /var/lib/lava/dispatcher/tmp/12172440/lava-overlay-qbgttqq8/lava-12172440/bin/lava-test-event
178 23:34:17.696925 Creating /var/lib/lava/dispatcher/tmp/12172440/lava-overlay-qbgttqq8/lava-12172440/bin/lava-test-feedback
179 23:34:17.697050 Creating /var/lib/lava/dispatcher/tmp/12172440/lava-overlay-qbgttqq8/lava-12172440/bin/lava-test-raise
180 23:34:17.697173 Creating /var/lib/lava/dispatcher/tmp/12172440/lava-overlay-qbgttqq8/lava-12172440/bin/lava-test-reference
181 23:34:17.697302 Creating /var/lib/lava/dispatcher/tmp/12172440/lava-overlay-qbgttqq8/lava-12172440/bin/lava-test-runner
182 23:34:17.697426 Creating /var/lib/lava/dispatcher/tmp/12172440/lava-overlay-qbgttqq8/lava-12172440/bin/lava-test-set
183 23:34:17.697552 Creating /var/lib/lava/dispatcher/tmp/12172440/lava-overlay-qbgttqq8/lava-12172440/bin/lava-test-shell
184 23:34:17.697710 Updating /var/lib/lava/dispatcher/tmp/12172440/lava-overlay-qbgttqq8/lava-12172440/bin/lava-add-keys (debian)
185 23:34:17.697914 Updating /var/lib/lava/dispatcher/tmp/12172440/lava-overlay-qbgttqq8/lava-12172440/bin/lava-add-sources (debian)
186 23:34:17.698058 Updating /var/lib/lava/dispatcher/tmp/12172440/lava-overlay-qbgttqq8/lava-12172440/bin/lava-install-packages (debian)
187 23:34:17.698197 Updating /var/lib/lava/dispatcher/tmp/12172440/lava-overlay-qbgttqq8/lava-12172440/bin/lava-installed-packages (debian)
188 23:34:17.698335 Updating /var/lib/lava/dispatcher/tmp/12172440/lava-overlay-qbgttqq8/lava-12172440/bin/lava-os-build (debian)
189 23:34:17.698456 Creating /var/lib/lava/dispatcher/tmp/12172440/lava-overlay-qbgttqq8/lava-12172440/environment
190 23:34:17.698552 LAVA metadata
191 23:34:17.698623 - LAVA_JOB_ID=12172440
192 23:34:17.698687 - LAVA_DISPATCHER_IP=192.168.201.1
193 23:34:17.698786 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:48) [common]
194 23:34:17.698853 skipped lava-vland-overlay
195 23:34:17.698926 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 23:34:17.699005 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:48) [common]
197 23:34:17.699066 skipped lava-multinode-overlay
198 23:34:17.699138 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 23:34:17.699226 start: 1.6.2.3 test-definition (timeout 00:09:48) [common]
200 23:34:17.699298 Loading test definitions
201 23:34:17.699386 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:48) [common]
202 23:34:17.699460 Using /lava-12172440 at stage 0
203 23:34:17.699743 uuid=12172440_1.6.2.3.1 testdef=None
204 23:34:17.699831 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 23:34:17.699914 start: 1.6.2.3.2 test-overlay (timeout 00:09:48) [common]
206 23:34:17.700371 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 23:34:17.700588 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:48) [common]
209 23:34:17.701148 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 23:34:17.701378 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:48) [common]
212 23:34:17.701933 runner path: /var/lib/lava/dispatcher/tmp/12172440/lava-overlay-qbgttqq8/lava-12172440/0/tests/0_timesync-off test_uuid 12172440_1.6.2.3.1
213 23:34:17.702088 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 23:34:17.702312 start: 1.6.2.3.5 git-repo-action (timeout 00:09:48) [common]
216 23:34:17.702384 Using /lava-12172440 at stage 0
217 23:34:17.702479 Fetching tests from https://github.com/kernelci/test-definitions.git
218 23:34:17.702556 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/12172440/lava-overlay-qbgttqq8/lava-12172440/0/tests/1_kselftest-rtc'
219 23:34:20.793568 Running '/usr/bin/git checkout kernelci.org
220 23:34:20.941493 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/12172440/lava-overlay-qbgttqq8/lava-12172440/0/tests/1_kselftest-rtc/automated/linux/kselftest/kselftest.yaml
221 23:34:20.942256 uuid=12172440_1.6.2.3.5 testdef=None
222 23:34:20.942410 end: 1.6.2.3.5 git-repo-action (duration 00:00:03) [common]
224 23:34:20.942663 start: 1.6.2.3.6 test-overlay (timeout 00:09:45) [common]
225 23:34:20.943436 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 23:34:20.943675 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:45) [common]
228 23:34:20.944655 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 23:34:20.944895 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:45) [common]
231 23:34:20.945877 runner path: /var/lib/lava/dispatcher/tmp/12172440/lava-overlay-qbgttqq8/lava-12172440/0/tests/1_kselftest-rtc test_uuid 12172440_1.6.2.3.5
232 23:34:20.945969 BOARD='mt8192-asurada-spherion-r0'
233 23:34:20.946036 BRANCH='cip-gitlab'
234 23:34:20.946096 SKIPFILE='/dev/null'
235 23:34:20.946156 SKIP_INSTALL='True'
236 23:34:20.946243 TESTPROG_URL='http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.64-cip10-rt5/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 23:34:20.946301 TST_CASENAME=''
238 23:34:20.946357 TST_CMDFILES='rtc'
239 23:34:20.946502 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 23:34:20.946711 Creating lava-test-runner.conf files
242 23:34:20.946777 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12172440/lava-overlay-qbgttqq8/lava-12172440/0 for stage 0
243 23:34:20.946871 - 0_timesync-off
244 23:34:20.946943 - 1_kselftest-rtc
245 23:34:20.947040 end: 1.6.2.3 test-definition (duration 00:00:03) [common]
246 23:34:20.947128 start: 1.6.2.4 compress-overlay (timeout 00:09:45) [common]
247 23:34:28.526813 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 23:34:28.526969 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:37) [common]
249 23:34:28.527063 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 23:34:28.527162 end: 1.6.2 lava-overlay (duration 00:00:11) [common]
251 23:34:28.527252 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:37) [common]
252 23:34:28.646296 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 23:34:28.646727 start: 1.6.4 extract-modules (timeout 00:09:37) [common]
254 23:34:28.646915 extracting modules file /var/lib/lava/dispatcher/tmp/12172440/tftp-deploy-jip4knts/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12172440/extract-nfsrootfs-4jgnn23a
255 23:34:28.868187 extracting modules file /var/lib/lava/dispatcher/tmp/12172440/tftp-deploy-jip4knts/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12172440/extract-overlay-ramdisk-uhbq3xah/ramdisk
256 23:34:29.103745 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 23:34:29.103935 start: 1.6.5 apply-overlay-tftp (timeout 00:09:36) [common]
258 23:34:29.104050 [common] Applying overlay to NFS
259 23:34:29.104136 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12172440/compress-overlay-g5qee98i/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12172440/extract-nfsrootfs-4jgnn23a
260 23:34:30.018674 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 23:34:30.018858 start: 1.6.6 configure-preseed-file (timeout 00:09:35) [common]
262 23:34:30.018979 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 23:34:30.019089 start: 1.6.7 compress-ramdisk (timeout 00:09:35) [common]
264 23:34:30.019188 Building ramdisk /var/lib/lava/dispatcher/tmp/12172440/extract-overlay-ramdisk-uhbq3xah/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12172440/extract-overlay-ramdisk-uhbq3xah/ramdisk
265 23:34:30.367582 >> 119416 blocks
266 23:34:32.283822 rename /var/lib/lava/dispatcher/tmp/12172440/extract-overlay-ramdisk-uhbq3xah/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12172440/tftp-deploy-jip4knts/ramdisk/ramdisk.cpio.gz
267 23:34:32.284288 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 23:34:32.284416 start: 1.6.8 prepare-kernel (timeout 00:09:33) [common]
269 23:34:32.284520 start: 1.6.8.1 prepare-fit (timeout 00:09:33) [common]
270 23:34:32.284632 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12172440/tftp-deploy-jip4knts/kernel/Image'
271 23:34:44.098358 Returned 0 in 11 seconds
272 23:34:44.199359 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12172440/tftp-deploy-jip4knts/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12172440/tftp-deploy-jip4knts/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12172440/tftp-deploy-jip4knts/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12172440/tftp-deploy-jip4knts/kernel/image.itb
273 23:34:44.578053 output: FIT description: Kernel Image image with one or more FDT blobs
274 23:34:44.578448 output: Created: Sun Dec 3 23:34:44 2023
275 23:34:44.578559 output: Image 0 (kernel-1)
276 23:34:44.578651 output: Description:
277 23:34:44.578740 output: Created: Sun Dec 3 23:34:44 2023
278 23:34:44.578827 output: Type: Kernel Image
279 23:34:44.578912 output: Compression: lzma compressed
280 23:34:44.578994 output: Data Size: 11049348 Bytes = 10790.38 KiB = 10.54 MiB
281 23:34:44.579097 output: Architecture: AArch64
282 23:34:44.579200 output: OS: Linux
283 23:34:44.579297 output: Load Address: 0x00000000
284 23:34:44.579398 output: Entry Point: 0x00000000
285 23:34:44.579498 output: Hash algo: crc32
286 23:34:44.579598 output: Hash value: c85ea8f0
287 23:34:44.579697 output: Image 1 (fdt-1)
288 23:34:44.579793 output: Description: mt8192-asurada-spherion-r0
289 23:34:44.579887 output: Created: Sun Dec 3 23:34:44 2023
290 23:34:44.579982 output: Type: Flat Device Tree
291 23:34:44.580076 output: Compression: uncompressed
292 23:34:44.580171 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
293 23:34:44.580266 output: Architecture: AArch64
294 23:34:44.580360 output: Hash algo: crc32
295 23:34:44.580453 output: Hash value: cc4352de
296 23:34:44.580547 output: Image 2 (ramdisk-1)
297 23:34:44.580641 output: Description: unavailable
298 23:34:44.580735 output: Created: Sun Dec 3 23:34:44 2023
299 23:34:44.580830 output: Type: RAMDisk Image
300 23:34:44.580924 output: Compression: Unknown Compression
301 23:34:44.581018 output: Data Size: 17795489 Bytes = 17378.41 KiB = 16.97 MiB
302 23:34:44.581112 output: Architecture: AArch64
303 23:34:44.581206 output: OS: Linux
304 23:34:44.581299 output: Load Address: unavailable
305 23:34:44.581393 output: Entry Point: unavailable
306 23:34:44.581487 output: Hash algo: crc32
307 23:34:44.581587 output: Hash value: 75d1eb0f
308 23:34:44.581717 output: Default Configuration: 'conf-1'
309 23:34:44.581811 output: Configuration 0 (conf-1)
310 23:34:44.581906 output: Description: mt8192-asurada-spherion-r0
311 23:34:44.582000 output: Kernel: kernel-1
312 23:34:44.582094 output: Init Ramdisk: ramdisk-1
313 23:34:44.582187 output: FDT: fdt-1
314 23:34:44.582281 output: Loadables: kernel-1
315 23:34:44.582374 output:
316 23:34:44.582629 end: 1.6.8.1 prepare-fit (duration 00:00:12) [common]
317 23:34:44.582774 end: 1.6.8 prepare-kernel (duration 00:00:12) [common]
318 23:34:44.582925 end: 1.6 prepare-tftp-overlay (duration 00:00:30) [common]
319 23:34:44.583062 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:21) [common]
320 23:34:44.583183 No LXC device requested
321 23:34:44.583310 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 23:34:44.583438 start: 1.8 deploy-device-env (timeout 00:09:21) [common]
323 23:34:44.583561 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 23:34:44.583670 Checking files for TFTP limit of 4294967296 bytes.
325 23:34:44.584354 end: 1 tftp-deploy (duration 00:00:39) [common]
326 23:34:44.584533 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 23:34:44.584671 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 23:34:44.584854 substitutions:
329 23:34:44.584956 - {DTB}: 12172440/tftp-deploy-jip4knts/dtb/mt8192-asurada-spherion-r0.dtb
330 23:34:44.585062 - {INITRD}: 12172440/tftp-deploy-jip4knts/ramdisk/ramdisk.cpio.gz
331 23:34:44.585163 - {KERNEL}: 12172440/tftp-deploy-jip4knts/kernel/Image
332 23:34:44.585264 - {LAVA_MAC}: None
333 23:34:44.585364 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/12172440/extract-nfsrootfs-4jgnn23a
334 23:34:44.585464 - {NFS_SERVER_IP}: 192.168.201.1
335 23:34:44.585563 - {PRESEED_CONFIG}: None
336 23:34:44.585704 - {PRESEED_LOCAL}: None
337 23:34:44.585802 - {RAMDISK}: 12172440/tftp-deploy-jip4knts/ramdisk/ramdisk.cpio.gz
338 23:34:44.585900 - {ROOT_PART}: None
339 23:34:44.585998 - {ROOT}: None
340 23:34:44.586095 - {SERVER_IP}: 192.168.201.1
341 23:34:44.586192 - {TEE}: None
342 23:34:44.586288 Parsed boot commands:
343 23:34:44.586383 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 23:34:44.586655 Parsed boot commands: tftpboot 192.168.201.1 12172440/tftp-deploy-jip4knts/kernel/image.itb 12172440/tftp-deploy-jip4knts/kernel/cmdline
345 23:34:44.586781 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 23:34:44.586903 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 23:34:44.587031 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 23:34:44.587154 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 23:34:44.587256 Not connected, no need to disconnect.
350 23:34:44.587364 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 23:34:44.587479 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 23:34:44.587575 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-0'
353 23:34:44.591965 Setting prompt string to ['lava-test: # ']
354 23:34:44.592340 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 23:34:44.592459 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 23:34:44.592679 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 23:34:44.592818 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 23:34:44.593040 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=reboot'
359 23:34:49.745119 >> Command sent successfully.
360 23:34:49.751524 Returned 0 in 5 seconds
361 23:34:49.852361 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 23:34:49.854098 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 23:34:49.854685 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 23:34:49.855201 Setting prompt string to 'Starting depthcharge on Spherion...'
366 23:34:49.855564 Changing prompt to 'Starting depthcharge on Spherion...'
367 23:34:49.856027 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 23:34:49.857456 [Enter `^Ec?' for help]
369 23:34:50.021968
370 23:34:50.022528
371 23:34:50.022914 F0: 102B 0000
372 23:34:50.023284
373 23:34:50.023626 F3: 1001 0000 [0200]
374 23:34:50.025157
375 23:34:50.025645 F3: 1001 0000
376 23:34:50.026099
377 23:34:50.026435 F7: 102D 0000
378 23:34:50.026757
379 23:34:50.028149 F1: 0000 0000
380 23:34:50.028586
381 23:34:50.028936 V0: 0000 0000 [0001]
382 23:34:50.029282
383 23:34:50.031331 00: 0007 8000
384 23:34:50.031789
385 23:34:50.032140 01: 0000 0000
386 23:34:50.032477
387 23:34:50.034794 BP: 0C00 0209 [0000]
388 23:34:50.035310
389 23:34:50.035675 G0: 1182 0000
390 23:34:50.036009
391 23:34:50.039129 EC: 0000 0021 [4000]
392 23:34:50.039649
393 23:34:50.040015 S7: 0000 0000 [0000]
394 23:34:50.040349
395 23:34:50.042287 CC: 0000 0000 [0001]
396 23:34:50.042718
397 23:34:50.043065 T0: 0000 0040 [010F]
398 23:34:50.043394
399 23:34:50.043707 Jump to BL
400 23:34:50.044018
401 23:34:50.068558
402 23:34:50.069224
403 23:34:50.069785
404 23:34:50.075314 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 23:34:50.078904 ARM64: Exception handlers installed.
406 23:34:50.082573 ARM64: Testing exception
407 23:34:50.085999 ARM64: Done test exception
408 23:34:50.092638 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 23:34:50.102976 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 23:34:50.109940 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 23:34:50.119792 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 23:34:50.127047 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 23:34:50.133486 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 23:34:50.146052 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 23:34:50.153045 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 23:34:50.171239 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 23:34:50.175084 WDT: Last reset was cold boot
418 23:34:50.178534 SPI1(PAD0) initialized at 2873684 Hz
419 23:34:50.181991 SPI5(PAD0) initialized at 992727 Hz
420 23:34:50.184890 VBOOT: Loading verstage.
421 23:34:50.192221 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 23:34:50.194610 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 23:34:50.198361 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 23:34:50.201775 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 23:34:50.209113 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 23:34:50.216302 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 23:34:50.226918 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
428 23:34:50.227355
429 23:34:50.227699
430 23:34:50.237767 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 23:34:50.240994 ARM64: Exception handlers installed.
432 23:34:50.241443 ARM64: Testing exception
433 23:34:50.244239 ARM64: Done test exception
434 23:34:50.247880 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 23:34:50.254088 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 23:34:50.267592 Probing TPM: . done!
437 23:34:50.268056 TPM ready after 0 ms
438 23:34:50.275313 Connected to device vid:did:rid of 1ae0:0028:00
439 23:34:50.282121 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
440 23:34:50.340133 Initialized TPM device CR50 revision 0
441 23:34:50.352426 tlcl_send_startup: Startup return code is 0
442 23:34:50.352579 TPM: setup succeeded
443 23:34:50.363683 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 23:34:50.372295 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 23:34:50.384670 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 23:34:50.394622 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 23:34:50.398620 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 23:34:50.402407 in-header: 03 07 00 00 08 00 00 00
449 23:34:50.405927 in-data: aa e4 47 04 13 02 00 00
450 23:34:50.406027 Chrome EC: UHEPI supported
451 23:34:50.412953 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 23:34:50.416714 in-header: 03 95 00 00 08 00 00 00
453 23:34:50.420262 in-data: 18 20 20 08 00 00 00 00
454 23:34:50.420359 Phase 1
455 23:34:50.424136 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 23:34:50.431968 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 23:34:50.435795 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 23:34:50.438872 Recovery requested (1009000e)
459 23:34:50.449003 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 23:34:50.454403 tlcl_extend: response is 0
461 23:34:50.464229 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 23:34:50.469256 tlcl_extend: response is 0
463 23:34:50.477117 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 23:34:50.496843 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
465 23:34:50.503169 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 23:34:50.503624
467 23:34:50.504076
468 23:34:50.513413 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 23:34:50.516188 ARM64: Exception handlers installed.
470 23:34:50.519882 ARM64: Testing exception
471 23:34:50.520120 ARM64: Done test exception
472 23:34:50.542191 pmic_efuse_setting: Set efuses in 11 msecs
473 23:34:50.545403 pmwrap_interface_init: Select PMIF_VLD_RDY
474 23:34:50.552663 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 23:34:50.556104 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 23:34:50.563000 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 23:34:50.566749 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 23:34:50.570650 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 23:34:50.574358 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 23:34:50.581347 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 23:34:50.585618 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 23:34:50.589167 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 23:34:50.592565 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 23:34:50.600341 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 23:34:50.603909 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 23:34:50.608067 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 23:34:50.615351 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 23:34:50.618794 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 23:34:50.626257 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 23:34:50.630121 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 23:34:50.637213 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 23:34:50.644596 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 23:34:50.648351 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 23:34:50.652154 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 23:34:50.658940 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 23:34:50.666759 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 23:34:50.670714 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 23:34:50.674342 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 23:34:50.682065 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 23:34:50.686004 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 23:34:50.692667 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 23:34:50.696308 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 23:34:50.700386 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 23:34:50.707603 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 23:34:50.711033 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 23:34:50.714781 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 23:34:50.721464 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 23:34:50.725372 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 23:34:50.732395 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 23:34:50.736386 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 23:34:50.740133 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 23:34:50.743647 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 23:34:50.751355 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 23:34:50.755115 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 23:34:50.758497 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 23:34:50.762986 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 23:34:50.765912 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 23:34:50.773349 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 23:34:50.777119 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 23:34:50.781360 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 23:34:50.784854 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 23:34:50.788210 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 23:34:50.792015 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 23:34:50.795540 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 23:34:50.803728 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 23:34:50.814483 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 23:34:50.818268 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 23:34:50.825162 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 23:34:50.836611 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 23:34:50.840360 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 23:34:50.844030 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 23:34:50.847429 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 23:34:50.855536 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x1b
534 23:34:50.859407 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 23:34:50.864267 [RTC]rtc_osc_init,62: osc32con val = 0xde70
536 23:34:50.871058 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 23:34:50.880112 [RTC]rtc_get_frequency_meter,154: input=15, output=759
538 23:34:50.889800 [RTC]rtc_get_frequency_meter,154: input=23, output=941
539 23:34:50.898861 [RTC]rtc_get_frequency_meter,154: input=19, output=849
540 23:34:50.908465 [RTC]rtc_get_frequency_meter,154: input=17, output=805
541 23:34:50.917807 [RTC]rtc_get_frequency_meter,154: input=16, output=780
542 23:34:50.927208 [RTC]rtc_get_frequency_meter,154: input=16, output=781
543 23:34:50.937558 [RTC]rtc_get_frequency_meter,154: input=17, output=805
544 23:34:50.941279 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
545 23:34:50.945099 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
546 23:34:50.948931 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
547 23:34:50.956027 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
548 23:34:50.960220 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
549 23:34:50.964090 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
550 23:34:50.967884 ADC[4]: Raw value=906573 ID=7
551 23:34:50.968475 ADC[3]: Raw value=213441 ID=1
552 23:34:50.971055 RAM Code: 0x71
553 23:34:50.975038 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
554 23:34:50.978287 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
555 23:34:50.989635 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
556 23:34:50.993458 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
557 23:34:50.996632 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
558 23:34:51.002491 in-header: 03 07 00 00 08 00 00 00
559 23:34:51.005776 in-data: aa e4 47 04 13 02 00 00
560 23:34:51.009408 Chrome EC: UHEPI supported
561 23:34:51.017327 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
562 23:34:51.017932 in-header: 03 95 00 00 08 00 00 00
563 23:34:51.020776 in-data: 18 20 20 08 00 00 00 00
564 23:34:51.025073 MRC: failed to locate region type 0.
565 23:34:51.032488 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
566 23:34:51.036627 DRAM-K: Running full calibration
567 23:34:51.039952 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
568 23:34:51.044027 header.status = 0x0
569 23:34:51.047743 header.version = 0x6 (expected: 0x6)
570 23:34:51.051164 header.size = 0xd00 (expected: 0xd00)
571 23:34:51.051609 header.flags = 0x0
572 23:34:51.058744 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
573 23:34:51.075764 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
574 23:34:51.083157 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
575 23:34:51.086732 dram_init: ddr_geometry: 2
576 23:34:51.087223 [EMI] MDL number = 2
577 23:34:51.091008 [EMI] Get MDL freq = 0
578 23:34:51.091497 dram_init: ddr_type: 0
579 23:34:51.094383 is_discrete_lpddr4: 1
580 23:34:51.098046 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
581 23:34:51.098536
582 23:34:51.099041
583 23:34:51.099462 [Bian_co] ETT version 0.0.0.1
584 23:34:51.102116 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
585 23:34:51.106121
586 23:34:51.109697 dramc_set_vcore_voltage set vcore to 650000
587 23:34:51.110139 Read voltage for 800, 4
588 23:34:51.110587 Vio18 = 0
589 23:34:51.113277 Vcore = 650000
590 23:34:51.113849 Vdram = 0
591 23:34:51.114294 Vddq = 0
592 23:34:51.114735 Vmddr = 0
593 23:34:51.116987 dram_init: config_dvfs: 1
594 23:34:51.120888 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
595 23:34:51.128076 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
596 23:34:51.132032 [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9
597 23:34:51.135525 freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9
598 23:34:51.140023 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
599 23:34:51.143372 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
600 23:34:51.146527 MEM_TYPE=3, freq_sel=18
601 23:34:51.146963 sv_algorithm_assistance_LP4_1600
602 23:34:51.153361 ============ PULL DRAM RESETB DOWN ============
603 23:34:51.157148 ========== PULL DRAM RESETB DOWN end =========
604 23:34:51.160088 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
605 23:34:51.163659 ===================================
606 23:34:51.168118 LPDDR4 DRAM CONFIGURATION
607 23:34:51.171045 ===================================
608 23:34:51.171484 EX_ROW_EN[0] = 0x0
609 23:34:51.174690 EX_ROW_EN[1] = 0x0
610 23:34:51.175119 LP4Y_EN = 0x0
611 23:34:51.178613 WORK_FSP = 0x0
612 23:34:51.179045 WL = 0x2
613 23:34:51.181935 RL = 0x2
614 23:34:51.182365 BL = 0x2
615 23:34:51.185823 RPST = 0x0
616 23:34:51.186253 RD_PRE = 0x0
617 23:34:51.189299 WR_PRE = 0x1
618 23:34:51.189926 WR_PST = 0x0
619 23:34:51.192615 DBI_WR = 0x0
620 23:34:51.193153 DBI_RD = 0x0
621 23:34:51.196093 OTF = 0x1
622 23:34:51.199283 ===================================
623 23:34:51.203200 ===================================
624 23:34:51.203746 ANA top config
625 23:34:51.206257 ===================================
626 23:34:51.209724 DLL_ASYNC_EN = 0
627 23:34:51.212811 ALL_SLAVE_EN = 1
628 23:34:51.213287 NEW_RANK_MODE = 1
629 23:34:51.216151 DLL_IDLE_MODE = 1
630 23:34:51.219520 LP45_APHY_COMB_EN = 1
631 23:34:51.222506 TX_ODT_DIS = 1
632 23:34:51.222990 NEW_8X_MODE = 1
633 23:34:51.226491 ===================================
634 23:34:51.229878 ===================================
635 23:34:51.233076 data_rate = 1600
636 23:34:51.236616 CKR = 1
637 23:34:51.240449 DQ_P2S_RATIO = 8
638 23:34:51.243218 ===================================
639 23:34:51.247108 CA_P2S_RATIO = 8
640 23:34:51.247696 DQ_CA_OPEN = 0
641 23:34:51.250275 DQ_SEMI_OPEN = 0
642 23:34:51.252968 CA_SEMI_OPEN = 0
643 23:34:51.256687 CA_FULL_RATE = 0
644 23:34:51.259898 DQ_CKDIV4_EN = 1
645 23:34:51.262991 CA_CKDIV4_EN = 1
646 23:34:51.263473 CA_PREDIV_EN = 0
647 23:34:51.266600 PH8_DLY = 0
648 23:34:51.270045 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
649 23:34:51.273279 DQ_AAMCK_DIV = 4
650 23:34:51.276739 CA_AAMCK_DIV = 4
651 23:34:51.277332 CA_ADMCK_DIV = 4
652 23:34:51.280068 DQ_TRACK_CA_EN = 0
653 23:34:51.283691 CA_PICK = 800
654 23:34:51.286822 CA_MCKIO = 800
655 23:34:51.290592 MCKIO_SEMI = 0
656 23:34:51.294928 PLL_FREQ = 3068
657 23:34:51.295505 DQ_UI_PI_RATIO = 32
658 23:34:51.298114 CA_UI_PI_RATIO = 0
659 23:34:51.302408 ===================================
660 23:34:51.305908 ===================================
661 23:34:51.306413 memory_type:LPDDR4
662 23:34:51.309559 GP_NUM : 10
663 23:34:51.313151 SRAM_EN : 1
664 23:34:51.313689 MD32_EN : 0
665 23:34:51.317180 ===================================
666 23:34:51.320985 [ANA_INIT] >>>>>>>>>>>>>>
667 23:34:51.321558 <<<<<< [CONFIGURE PHASE]: ANA_TX
668 23:34:51.324921 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
669 23:34:51.327954 ===================================
670 23:34:51.331497 data_rate = 1600,PCW = 0X7600
671 23:34:51.334794 ===================================
672 23:34:51.337776 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
673 23:34:51.344660 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 23:34:51.348287 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
675 23:34:51.354454 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
676 23:34:51.357741 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
677 23:34:51.361672 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
678 23:34:51.362243 [ANA_INIT] flow start
679 23:34:51.364417 [ANA_INIT] PLL >>>>>>>>
680 23:34:51.368363 [ANA_INIT] PLL <<<<<<<<
681 23:34:51.371497 [ANA_INIT] MIDPI >>>>>>>>
682 23:34:51.372089 [ANA_INIT] MIDPI <<<<<<<<
683 23:34:51.374140 [ANA_INIT] DLL >>>>>>>>
684 23:34:51.374671 [ANA_INIT] flow end
685 23:34:51.381199 ============ LP4 DIFF to SE enter ============
686 23:34:51.384569 ============ LP4 DIFF to SE exit ============
687 23:34:51.387896 [ANA_INIT] <<<<<<<<<<<<<
688 23:34:51.391663 [Flow] Enable top DCM control >>>>>
689 23:34:51.394957 [Flow] Enable top DCM control <<<<<
690 23:34:51.395533 Enable DLL master slave shuffle
691 23:34:51.401370 ==============================================================
692 23:34:51.404767 Gating Mode config
693 23:34:51.408099 ==============================================================
694 23:34:51.411360 Config description:
695 23:34:51.421330 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
696 23:34:51.427749 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
697 23:34:51.431228 SELPH_MODE 0: By rank 1: By Phase
698 23:34:51.437989 ==============================================================
699 23:34:51.441127 GAT_TRACK_EN = 1
700 23:34:51.445010 RX_GATING_MODE = 2
701 23:34:51.447845 RX_GATING_TRACK_MODE = 2
702 23:34:51.451202 SELPH_MODE = 1
703 23:34:51.451685 PICG_EARLY_EN = 1
704 23:34:51.454635 VALID_LAT_VALUE = 1
705 23:34:51.461365 ==============================================================
706 23:34:51.464314 Enter into Gating configuration >>>>
707 23:34:51.468661 Exit from Gating configuration <<<<
708 23:34:51.471260 Enter into DVFS_PRE_config >>>>>
709 23:34:51.481534 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
710 23:34:51.484888 Exit from DVFS_PRE_config <<<<<
711 23:34:51.488403 Enter into PICG configuration >>>>
712 23:34:51.491434 Exit from PICG configuration <<<<
713 23:34:51.494962 [RX_INPUT] configuration >>>>>
714 23:34:51.497830 [RX_INPUT] configuration <<<<<
715 23:34:51.501193 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
716 23:34:51.507743 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
717 23:34:51.514580 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
718 23:34:51.521671 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
719 23:34:51.524665 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
720 23:34:51.531229 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
721 23:34:51.534930 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
722 23:34:51.541552 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
723 23:34:51.544851 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
724 23:34:51.548343 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
725 23:34:51.551735 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
726 23:34:51.557961 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
727 23:34:51.561555 ===================================
728 23:34:51.562212 LPDDR4 DRAM CONFIGURATION
729 23:34:51.564758 ===================================
730 23:34:51.568374 EX_ROW_EN[0] = 0x0
731 23:34:51.572015 EX_ROW_EN[1] = 0x0
732 23:34:51.572600 LP4Y_EN = 0x0
733 23:34:51.574962 WORK_FSP = 0x0
734 23:34:51.575444 WL = 0x2
735 23:34:51.578070 RL = 0x2
736 23:34:51.578544 BL = 0x2
737 23:34:51.582016 RPST = 0x0
738 23:34:51.582609 RD_PRE = 0x0
739 23:34:51.585231 WR_PRE = 0x1
740 23:34:51.585884 WR_PST = 0x0
741 23:34:51.588095 DBI_WR = 0x0
742 23:34:51.588681 DBI_RD = 0x0
743 23:34:51.592114 OTF = 0x1
744 23:34:51.594726 ===================================
745 23:34:51.597855 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
746 23:34:51.601203 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
747 23:34:51.607791 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
748 23:34:51.611219 ===================================
749 23:34:51.611621 LPDDR4 DRAM CONFIGURATION
750 23:34:51.614831 ===================================
751 23:34:51.617905 EX_ROW_EN[0] = 0x10
752 23:34:51.618342 EX_ROW_EN[1] = 0x0
753 23:34:51.621264 LP4Y_EN = 0x0
754 23:34:51.621733 WORK_FSP = 0x0
755 23:34:51.624636 WL = 0x2
756 23:34:51.625070 RL = 0x2
757 23:34:51.628540 BL = 0x2
758 23:34:51.631252 RPST = 0x0
759 23:34:51.631731 RD_PRE = 0x0
760 23:34:51.634699 WR_PRE = 0x1
761 23:34:51.635179 WR_PST = 0x0
762 23:34:51.638185 DBI_WR = 0x0
763 23:34:51.638613 DBI_RD = 0x0
764 23:34:51.641667 OTF = 0x1
765 23:34:51.644969 ===================================
766 23:34:51.648590 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
767 23:34:51.653856 nWR fixed to 40
768 23:34:51.657701 [ModeRegInit_LP4] CH0 RK0
769 23:34:51.658284 [ModeRegInit_LP4] CH0 RK1
770 23:34:51.660732 [ModeRegInit_LP4] CH1 RK0
771 23:34:51.663752 [ModeRegInit_LP4] CH1 RK1
772 23:34:51.664311 match AC timing 13
773 23:34:51.670227 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
774 23:34:51.673709 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
775 23:34:51.677030 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
776 23:34:51.684027 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
777 23:34:51.687169 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
778 23:34:51.687645 [EMI DOE] emi_dcm 0
779 23:34:51.693888 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
780 23:34:51.694470 ==
781 23:34:51.697099 Dram Type= 6, Freq= 0, CH_0, rank 0
782 23:34:51.700531 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
783 23:34:51.701118 ==
784 23:34:51.707507 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
785 23:34:51.710450 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
786 23:34:51.721571 [CA 0] Center 36 (6~67) winsize 62
787 23:34:51.724457 [CA 1] Center 36 (6~67) winsize 62
788 23:34:51.727761 [CA 2] Center 34 (4~65) winsize 62
789 23:34:51.731300 [CA 3] Center 33 (3~64) winsize 62
790 23:34:51.734391 [CA 4] Center 33 (3~64) winsize 62
791 23:34:51.737606 [CA 5] Center 32 (3~62) winsize 60
792 23:34:51.738089
793 23:34:51.741100 [CmdBusTrainingLP45] Vref(ca) range 1: 32
794 23:34:51.741742
795 23:34:51.744391 [CATrainingPosCal] consider 1 rank data
796 23:34:51.747475 u2DelayCellTimex100 = 270/100 ps
797 23:34:51.751070 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
798 23:34:51.754623 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
799 23:34:51.761393 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
800 23:34:51.765236 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
801 23:34:51.767684 CA4 delay=33 (3~64),Diff = 1 PI (7 cell)
802 23:34:51.771353 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
803 23:34:51.771831
804 23:34:51.774543 CA PerBit enable=1, Macro0, CA PI delay=32
805 23:34:51.775022
806 23:34:51.777987 [CBTSetCACLKResult] CA Dly = 32
807 23:34:51.778465 CS Dly: 5 (0~36)
808 23:34:51.779079 ==
809 23:34:51.781734 Dram Type= 6, Freq= 0, CH_0, rank 1
810 23:34:51.788197 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
811 23:34:51.788635 ==
812 23:34:51.791385 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
813 23:34:51.798183 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
814 23:34:51.807501 [CA 0] Center 36 (6~67) winsize 62
815 23:34:51.810321 [CA 1] Center 36 (6~67) winsize 62
816 23:34:51.813754 [CA 2] Center 34 (4~65) winsize 62
817 23:34:51.816756 [CA 3] Center 34 (3~65) winsize 63
818 23:34:51.820359 [CA 4] Center 33 (3~63) winsize 61
819 23:34:51.823466 [CA 5] Center 32 (2~62) winsize 61
820 23:34:51.824181
821 23:34:51.826659 [CmdBusTrainingLP45] Vref(ca) range 1: 32
822 23:34:51.827099
823 23:34:51.830256 [CATrainingPosCal] consider 2 rank data
824 23:34:51.833445 u2DelayCellTimex100 = 270/100 ps
825 23:34:51.837041 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
826 23:34:51.840859 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
827 23:34:51.847413 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
828 23:34:51.851051 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
829 23:34:51.853876 CA4 delay=33 (3~63),Diff = 1 PI (7 cell)
830 23:34:51.857533 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
831 23:34:51.858154
832 23:34:51.860237 CA PerBit enable=1, Macro0, CA PI delay=32
833 23:34:51.860713
834 23:34:51.863816 [CBTSetCACLKResult] CA Dly = 32
835 23:34:51.864310 CS Dly: 5 (0~37)
836 23:34:51.866920
837 23:34:51.867390 ----->DramcWriteLeveling(PI) begin...
838 23:34:51.870493 ==
839 23:34:51.870923 Dram Type= 6, Freq= 0, CH_0, rank 0
840 23:34:51.877838 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
841 23:34:51.878290 ==
842 23:34:51.878639 Write leveling (Byte 0): 32 => 32
843 23:34:51.881609 Write leveling (Byte 1): 29 => 29
844 23:34:51.884602 DramcWriteLeveling(PI) end<-----
845 23:34:51.885036
846 23:34:51.885383 ==
847 23:34:51.888323 Dram Type= 6, Freq= 0, CH_0, rank 0
848 23:34:51.894615 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
849 23:34:51.895144 ==
850 23:34:51.895667 [Gating] SW mode calibration
851 23:34:51.902340 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
852 23:34:51.909314 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
853 23:34:51.912269 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
854 23:34:51.915591 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
855 23:34:51.922720 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
856 23:34:51.925714 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
857 23:34:51.929174 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 23:34:51.936272 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 23:34:51.939368 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 23:34:51.942310 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 23:34:51.949388 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 23:34:51.952794 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 23:34:51.956037 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 23:34:51.962809 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 23:34:51.966254 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 23:34:51.969750 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 23:34:51.976307 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 23:34:51.979458 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 23:34:51.982507 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
870 23:34:51.989795 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
871 23:34:51.992643 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
872 23:34:51.996239 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 23:34:51.999348 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 23:34:52.006040 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 23:34:52.009504 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 23:34:52.012996 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 23:34:52.019405 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 23:34:52.022771 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
879 23:34:52.025919 0 9 8 | B1->B0 | 2323 3131 | 0 0 | (1 1) (0 0)
880 23:34:52.032679 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
881 23:34:52.035925 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 23:34:52.039219 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 23:34:52.045837 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
884 23:34:52.049165 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
885 23:34:52.053043 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
886 23:34:52.059308 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
887 23:34:52.062856 0 10 8 | B1->B0 | 3232 2b2b | 1 0 | (1 1) (1 0)
888 23:34:52.065707 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
889 23:34:52.072857 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 23:34:52.076216 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 23:34:52.080010 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
892 23:34:52.085688 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
893 23:34:52.089406 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
894 23:34:52.092756 0 11 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
895 23:34:52.095851 0 11 8 | B1->B0 | 2f2f 4040 | 1 0 | (0 0) (0 0)
896 23:34:52.102835 0 11 12 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
897 23:34:52.106263 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 23:34:52.109413 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 23:34:52.115786 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
900 23:34:52.119572 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
901 23:34:52.123036 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
902 23:34:52.129546 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
903 23:34:52.132675 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
904 23:34:52.135949 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 23:34:52.143092 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 23:34:52.146304 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 23:34:52.149570 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 23:34:52.156034 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 23:34:52.159702 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 23:34:52.163150 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 23:34:52.165864 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 23:34:52.173053 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 23:34:52.175795 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 23:34:52.179551 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 23:34:52.186062 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
916 23:34:52.189687 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
917 23:34:52.193092 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
918 23:34:52.199380 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
919 23:34:52.202576 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
920 23:34:52.206341 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
921 23:34:52.209884 Total UI for P1: 0, mck2ui 16
922 23:34:52.213284 best dqsien dly found for B0: ( 0, 14, 6)
923 23:34:52.219899 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
924 23:34:52.220482 Total UI for P1: 0, mck2ui 16
925 23:34:52.223636 best dqsien dly found for B1: ( 0, 14, 12)
926 23:34:52.226695 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
927 23:34:52.233640 best DQS1 dly(MCK, UI, PI) = (0, 14, 12)
928 23:34:52.234230
929 23:34:52.236871 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
930 23:34:52.240751 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 12)
931 23:34:52.243819 [Gating] SW calibration Done
932 23:34:52.244293 ==
933 23:34:52.246754 Dram Type= 6, Freq= 0, CH_0, rank 0
934 23:34:52.250459 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
935 23:34:52.250934 ==
936 23:34:52.251312 RX Vref Scan: 0
937 23:34:52.251666
938 23:34:52.253565 RX Vref 0 -> 0, step: 1
939 23:34:52.254101
940 23:34:52.256832 RX Delay -130 -> 252, step: 16
941 23:34:52.260480 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
942 23:34:52.263743 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
943 23:34:52.270431 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
944 23:34:52.273561 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
945 23:34:52.276750 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
946 23:34:52.280500 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
947 23:34:52.283628 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
948 23:34:52.290473 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
949 23:34:52.294094 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
950 23:34:52.297042 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
951 23:34:52.300868 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
952 23:34:52.303589 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
953 23:34:52.310107 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
954 23:34:52.314234 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
955 23:34:52.316957 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
956 23:34:52.320514 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
957 23:34:52.321092 ==
958 23:34:52.324388 Dram Type= 6, Freq= 0, CH_0, rank 0
959 23:34:52.327026 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
960 23:34:52.330454 ==
961 23:34:52.330956 DQS Delay:
962 23:34:52.331338 DQS0 = 0, DQS1 = 0
963 23:34:52.334185 DQM Delay:
964 23:34:52.334764 DQM0 = 89, DQM1 = 82
965 23:34:52.337014 DQ Delay:
966 23:34:52.337484 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
967 23:34:52.340585 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =101
968 23:34:52.343987 DQ8 =77, DQ9 =77, DQ10 =77, DQ11 =77
969 23:34:52.347964 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85
970 23:34:52.348549
971 23:34:52.350826
972 23:34:52.351404 ==
973 23:34:52.353814 Dram Type= 6, Freq= 0, CH_0, rank 0
974 23:34:52.357313 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
975 23:34:52.357836 ==
976 23:34:52.358217
977 23:34:52.358568
978 23:34:52.360412 TX Vref Scan disable
979 23:34:52.360884 == TX Byte 0 ==
980 23:34:52.364089 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
981 23:34:52.371427 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
982 23:34:52.372008 == TX Byte 1 ==
983 23:34:52.373949 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
984 23:34:52.380673 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
985 23:34:52.381257 ==
986 23:34:52.384310 Dram Type= 6, Freq= 0, CH_0, rank 0
987 23:34:52.387372 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
988 23:34:52.387955 ==
989 23:34:52.401530 TX Vref=22, minBit 5, minWin=27, winSum=446
990 23:34:52.404549 TX Vref=24, minBit 8, minWin=27, winSum=450
991 23:34:52.407593 TX Vref=26, minBit 13, minWin=27, winSum=456
992 23:34:52.410781 TX Vref=28, minBit 0, minWin=28, winSum=457
993 23:34:52.414072 TX Vref=30, minBit 8, minWin=28, winSum=459
994 23:34:52.418099 TX Vref=32, minBit 0, minWin=28, winSum=456
995 23:34:52.424207 [TxChooseVref] Worse bit 8, Min win 28, Win sum 459, Final Vref 30
996 23:34:52.424783
997 23:34:52.427890 Final TX Range 1 Vref 30
998 23:34:52.428391
999 23:34:52.428834 ==
1000 23:34:52.431189 Dram Type= 6, Freq= 0, CH_0, rank 0
1001 23:34:52.434118 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1002 23:34:52.434593 ==
1003 23:34:52.434967
1004 23:34:52.437478
1005 23:34:52.437935 TX Vref Scan disable
1006 23:34:52.441293 == TX Byte 0 ==
1007 23:34:52.443928 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1008 23:34:52.447534 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1009 23:34:52.450453 == TX Byte 1 ==
1010 23:34:52.454524 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1011 23:34:52.457467 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1012 23:34:52.458069
1013 23:34:52.461536 [DATLAT]
1014 23:34:52.462136 Freq=800, CH0 RK0
1015 23:34:52.462492
1016 23:34:52.464796 DATLAT Default: 0xa
1017 23:34:52.465329 0, 0xFFFF, sum = 0
1018 23:34:52.467535 1, 0xFFFF, sum = 0
1019 23:34:52.468074 2, 0xFFFF, sum = 0
1020 23:34:52.471411 3, 0xFFFF, sum = 0
1021 23:34:52.471846 4, 0xFFFF, sum = 0
1022 23:34:52.474599 5, 0xFFFF, sum = 0
1023 23:34:52.475031 6, 0xFFFF, sum = 0
1024 23:34:52.477410 7, 0xFFFF, sum = 0
1025 23:34:52.477914 8, 0xFFFF, sum = 0
1026 23:34:52.480860 9, 0x0, sum = 1
1027 23:34:52.481389 10, 0x0, sum = 2
1028 23:34:52.484594 11, 0x0, sum = 3
1029 23:34:52.485134 12, 0x0, sum = 4
1030 23:34:52.487438 best_step = 10
1031 23:34:52.487860
1032 23:34:52.488197 ==
1033 23:34:52.491047 Dram Type= 6, Freq= 0, CH_0, rank 0
1034 23:34:52.494553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1035 23:34:52.495087 ==
1036 23:34:52.497444 RX Vref Scan: 1
1037 23:34:52.497901
1038 23:34:52.498237 Set Vref Range= 32 -> 127
1039 23:34:52.498555
1040 23:34:52.500767 RX Vref 32 -> 127, step: 1
1041 23:34:52.501190
1042 23:34:52.504492 RX Delay -79 -> 252, step: 8
1043 23:34:52.505034
1044 23:34:52.507845 Set Vref, RX VrefLevel [Byte0]: 32
1045 23:34:52.511078 [Byte1]: 32
1046 23:34:52.511544
1047 23:34:52.514198 Set Vref, RX VrefLevel [Byte0]: 33
1048 23:34:52.517573 [Byte1]: 33
1049 23:34:52.521741
1050 23:34:52.522285 Set Vref, RX VrefLevel [Byte0]: 34
1051 23:34:52.524768 [Byte1]: 34
1052 23:34:52.528884
1053 23:34:52.529407 Set Vref, RX VrefLevel [Byte0]: 35
1054 23:34:52.532174 [Byte1]: 35
1055 23:34:52.536751
1056 23:34:52.537175 Set Vref, RX VrefLevel [Byte0]: 36
1057 23:34:52.539770 [Byte1]: 36
1058 23:34:52.544483
1059 23:34:52.545015 Set Vref, RX VrefLevel [Byte0]: 37
1060 23:34:52.547744 [Byte1]: 37
1061 23:34:52.551885
1062 23:34:52.552428 Set Vref, RX VrefLevel [Byte0]: 38
1063 23:34:52.554724 [Byte1]: 38
1064 23:34:52.559575
1065 23:34:52.560148 Set Vref, RX VrefLevel [Byte0]: 39
1066 23:34:52.562120 [Byte1]: 39
1067 23:34:52.566810
1068 23:34:52.567232 Set Vref, RX VrefLevel [Byte0]: 40
1069 23:34:52.569701 [Byte1]: 40
1070 23:34:52.574142
1071 23:34:52.574667 Set Vref, RX VrefLevel [Byte0]: 41
1072 23:34:52.577015 [Byte1]: 41
1073 23:34:52.581789
1074 23:34:52.582313 Set Vref, RX VrefLevel [Byte0]: 42
1075 23:34:52.584759 [Byte1]: 42
1076 23:34:52.588877
1077 23:34:52.589402 Set Vref, RX VrefLevel [Byte0]: 43
1078 23:34:52.592596 [Byte1]: 43
1079 23:34:52.596960
1080 23:34:52.597489 Set Vref, RX VrefLevel [Byte0]: 44
1081 23:34:52.599930 [Byte1]: 44
1082 23:34:52.604768
1083 23:34:52.605346 Set Vref, RX VrefLevel [Byte0]: 45
1084 23:34:52.607411 [Byte1]: 45
1085 23:34:52.611416
1086 23:34:52.611841 Set Vref, RX VrefLevel [Byte0]: 46
1087 23:34:52.615216 [Byte1]: 46
1088 23:34:52.619283
1089 23:34:52.619703 Set Vref, RX VrefLevel [Byte0]: 47
1090 23:34:52.622338 [Byte1]: 47
1091 23:34:52.626918
1092 23:34:52.627444 Set Vref, RX VrefLevel [Byte0]: 48
1093 23:34:52.630155 [Byte1]: 48
1094 23:34:52.634134
1095 23:34:52.634558 Set Vref, RX VrefLevel [Byte0]: 49
1096 23:34:52.638267 [Byte1]: 49
1097 23:34:52.642017
1098 23:34:52.642575 Set Vref, RX VrefLevel [Byte0]: 50
1099 23:34:52.645250 [Byte1]: 50
1100 23:34:52.649355
1101 23:34:52.649960 Set Vref, RX VrefLevel [Byte0]: 51
1102 23:34:52.652632 [Byte1]: 51
1103 23:34:52.657169
1104 23:34:52.657759 Set Vref, RX VrefLevel [Byte0]: 52
1105 23:34:52.660071 [Byte1]: 52
1106 23:34:52.664676
1107 23:34:52.665295 Set Vref, RX VrefLevel [Byte0]: 53
1108 23:34:52.667752 [Byte1]: 53
1109 23:34:52.672074
1110 23:34:52.672602 Set Vref, RX VrefLevel [Byte0]: 54
1111 23:34:52.675425 [Byte1]: 54
1112 23:34:52.679998
1113 23:34:52.680526 Set Vref, RX VrefLevel [Byte0]: 55
1114 23:34:52.682919 [Byte1]: 55
1115 23:34:52.687288
1116 23:34:52.687812 Set Vref, RX VrefLevel [Byte0]: 56
1117 23:34:52.690629 [Byte1]: 56
1118 23:34:52.694478
1119 23:34:52.695000 Set Vref, RX VrefLevel [Byte0]: 57
1120 23:34:52.697948 [Byte1]: 57
1121 23:34:52.702284
1122 23:34:52.702815 Set Vref, RX VrefLevel [Byte0]: 58
1123 23:34:52.705987 [Byte1]: 58
1124 23:34:52.709669
1125 23:34:52.710247 Set Vref, RX VrefLevel [Byte0]: 59
1126 23:34:52.713180 [Byte1]: 59
1127 23:34:52.717619
1128 23:34:52.718249 Set Vref, RX VrefLevel [Byte0]: 60
1129 23:34:52.721178 [Byte1]: 60
1130 23:34:52.725318
1131 23:34:52.725944 Set Vref, RX VrefLevel [Byte0]: 61
1132 23:34:52.728355 [Byte1]: 61
1133 23:34:52.732492
1134 23:34:52.732958 Set Vref, RX VrefLevel [Byte0]: 62
1135 23:34:52.735534 [Byte1]: 62
1136 23:34:52.740259
1137 23:34:52.740858 Set Vref, RX VrefLevel [Byte0]: 63
1138 23:34:52.743146 [Byte1]: 63
1139 23:34:52.747468
1140 23:34:52.748041 Set Vref, RX VrefLevel [Byte0]: 64
1141 23:34:52.750816 [Byte1]: 64
1142 23:34:52.755212
1143 23:34:52.755787 Set Vref, RX VrefLevel [Byte0]: 65
1144 23:34:52.758458 [Byte1]: 65
1145 23:34:52.762459
1146 23:34:52.763021 Set Vref, RX VrefLevel [Byte0]: 66
1147 23:34:52.765924 [Byte1]: 66
1148 23:34:52.770799
1149 23:34:52.771365 Set Vref, RX VrefLevel [Byte0]: 67
1150 23:34:52.773413 [Byte1]: 67
1151 23:34:52.777688
1152 23:34:52.778157 Set Vref, RX VrefLevel [Byte0]: 68
1153 23:34:52.781180 [Byte1]: 68
1154 23:34:52.785429
1155 23:34:52.786177 Set Vref, RX VrefLevel [Byte0]: 69
1156 23:34:52.788474 [Byte1]: 69
1157 23:34:52.793205
1158 23:34:52.793831 Set Vref, RX VrefLevel [Byte0]: 70
1159 23:34:52.796182 [Byte1]: 70
1160 23:34:52.800315
1161 23:34:52.800891 Set Vref, RX VrefLevel [Byte0]: 71
1162 23:34:52.803401 [Byte1]: 71
1163 23:34:52.807971
1164 23:34:52.808434 Set Vref, RX VrefLevel [Byte0]: 72
1165 23:34:52.811520 [Byte1]: 72
1166 23:34:52.815658
1167 23:34:52.816246 Set Vref, RX VrefLevel [Byte0]: 73
1168 23:34:52.818478 [Byte1]: 73
1169 23:34:52.823216
1170 23:34:52.823789 Set Vref, RX VrefLevel [Byte0]: 74
1171 23:34:52.826577 [Byte1]: 74
1172 23:34:52.830478
1173 23:34:52.830948 Set Vref, RX VrefLevel [Byte0]: 75
1174 23:34:52.833568 [Byte1]: 75
1175 23:34:52.838077
1176 23:34:52.838543 Set Vref, RX VrefLevel [Byte0]: 76
1177 23:34:52.841143 [Byte1]: 76
1178 23:34:52.845624
1179 23:34:52.846157 Set Vref, RX VrefLevel [Byte0]: 77
1180 23:34:52.848639 [Byte1]: 77
1181 23:34:52.852775
1182 23:34:52.853330 Set Vref, RX VrefLevel [Byte0]: 78
1183 23:34:52.856371 [Byte1]: 78
1184 23:34:52.860855
1185 23:34:52.861555 Final RX Vref Byte 0 = 58 to rank0
1186 23:34:52.864097 Final RX Vref Byte 1 = 60 to rank0
1187 23:34:52.867105 Final RX Vref Byte 0 = 58 to rank1
1188 23:34:52.870758 Final RX Vref Byte 1 = 60 to rank1==
1189 23:34:52.873984 Dram Type= 6, Freq= 0, CH_0, rank 0
1190 23:34:52.877183 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1191 23:34:52.880683 ==
1192 23:34:52.881243 DQS Delay:
1193 23:34:52.881754 DQS0 = 0, DQS1 = 0
1194 23:34:52.884314 DQM Delay:
1195 23:34:52.884740 DQM0 = 92, DQM1 = 86
1196 23:34:52.887471 DQ Delay:
1197 23:34:52.887898 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88
1198 23:34:52.890830 DQ4 =96, DQ5 =80, DQ6 =100, DQ7 =100
1199 23:34:52.894025 DQ8 =76, DQ9 =80, DQ10 =84, DQ11 =80
1200 23:34:52.897522 DQ12 =92, DQ13 =92, DQ14 =96, DQ15 =92
1201 23:34:52.900989
1202 23:34:52.901413
1203 23:34:52.907312 [DQSOSCAuto] RK0, (LSB)MR18= 0x4a41, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 391 ps
1204 23:34:52.910926 CH0 RK0: MR19=606, MR18=4A41
1205 23:34:52.917621 CH0_RK0: MR19=0x606, MR18=0x4A41, DQSOSC=391, MR23=63, INC=96, DEC=64
1206 23:34:52.918261
1207 23:34:52.921350 ----->DramcWriteLeveling(PI) begin...
1208 23:34:52.921962 ==
1209 23:34:52.924740 Dram Type= 6, Freq= 0, CH_0, rank 1
1210 23:34:52.927645 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1211 23:34:52.928078 ==
1212 23:34:52.931119 Write leveling (Byte 0): 34 => 34
1213 23:34:52.934309 Write leveling (Byte 1): 29 => 29
1214 23:34:52.937830 DramcWriteLeveling(PI) end<-----
1215 23:34:52.938309
1216 23:34:52.938655 ==
1217 23:34:52.940728 Dram Type= 6, Freq= 0, CH_0, rank 1
1218 23:34:52.981821 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1219 23:34:52.982633 ==
1220 23:34:52.983232 [Gating] SW mode calibration
1221 23:34:52.983989 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1222 23:34:52.984378 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1223 23:34:52.984730 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1224 23:34:52.985064 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1225 23:34:52.985395 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1226 23:34:52.985761 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 23:34:52.986154 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 23:34:52.986485 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 23:34:52.989844 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 23:34:52.996533 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 23:34:52.999355 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 23:34:53.002736 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 23:34:53.009396 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 23:34:53.013175 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 23:34:53.016119 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 23:34:53.022899 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 23:34:53.026159 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 23:34:53.028930 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 23:34:53.036103 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1240 23:34:53.039306 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1241 23:34:53.042671 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1242 23:34:53.049500 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1243 23:34:53.053413 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 23:34:53.056339 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1245 23:34:53.059656 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1246 23:34:53.066216 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1247 23:34:53.070000 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1248 23:34:53.073041 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1249 23:34:53.080140 0 9 8 | B1->B0 | 2f2f 2b2a | 0 1 | (0 0) (0 0)
1250 23:34:53.083096 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1251 23:34:53.086277 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1252 23:34:53.093178 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1253 23:34:53.096230 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1254 23:34:53.099793 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1255 23:34:53.106299 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1256 23:34:53.110170 0 10 4 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
1257 23:34:53.113751 0 10 8 | B1->B0 | 2828 2929 | 1 1 | (1 1) (1 1)
1258 23:34:53.117270 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1259 23:34:53.123959 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1260 23:34:53.128182 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1261 23:34:53.130915 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1262 23:34:53.137647 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1263 23:34:53.141020 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1264 23:34:53.144658 0 11 4 | B1->B0 | 2525 2626 | 0 1 | (0 0) (0 0)
1265 23:34:53.147881 0 11 8 | B1->B0 | 3a3a 3d3d | 0 0 | (0 0) (0 0)
1266 23:34:53.155629 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1267 23:34:53.158445 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1268 23:34:53.161699 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1269 23:34:53.164847 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1270 23:34:53.171534 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1271 23:34:53.175074 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1272 23:34:53.178133 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1273 23:34:53.184934 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1274 23:34:53.188353 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 23:34:53.192184 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1276 23:34:53.198633 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1277 23:34:53.202061 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1278 23:34:53.205514 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1279 23:34:53.211547 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1280 23:34:53.215113 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1281 23:34:53.218519 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1282 23:34:53.225622 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1283 23:34:53.228752 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1284 23:34:53.231763 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1285 23:34:53.235329 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1286 23:34:53.241914 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1287 23:34:53.245526 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1288 23:34:53.248626 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1289 23:34:53.254995 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1290 23:34:53.258371 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1291 23:34:53.261519 Total UI for P1: 0, mck2ui 16
1292 23:34:53.265136 best dqsien dly found for B0: ( 0, 14, 8)
1293 23:34:53.267977 Total UI for P1: 0, mck2ui 16
1294 23:34:53.271362 best dqsien dly found for B1: ( 0, 14, 8)
1295 23:34:53.275232 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1296 23:34:53.277869 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1297 23:34:53.278399
1298 23:34:53.281498 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1299 23:34:53.284725 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1300 23:34:53.288265 [Gating] SW calibration Done
1301 23:34:53.288794 ==
1302 23:34:53.291961 Dram Type= 6, Freq= 0, CH_0, rank 1
1303 23:34:53.295044 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1304 23:34:53.298409 ==
1305 23:34:53.298838 RX Vref Scan: 0
1306 23:34:53.299185
1307 23:34:53.301563 RX Vref 0 -> 0, step: 1
1308 23:34:53.302033
1309 23:34:53.304448 RX Delay -130 -> 252, step: 16
1310 23:34:53.308060 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1311 23:34:53.311099 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1312 23:34:53.314715 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1313 23:34:53.317875 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1314 23:34:53.325285 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1315 23:34:53.328844 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1316 23:34:53.331886 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1317 23:34:53.335001 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1318 23:34:53.338365 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1319 23:34:53.345050 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1320 23:34:53.348401 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1321 23:34:53.351799 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1322 23:34:53.355298 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1323 23:34:53.358075 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1324 23:34:53.365243 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1325 23:34:53.368114 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1326 23:34:53.368544 ==
1327 23:34:53.371720 Dram Type= 6, Freq= 0, CH_0, rank 1
1328 23:34:53.375338 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1329 23:34:53.375871 ==
1330 23:34:53.376223 DQS Delay:
1331 23:34:53.378620 DQS0 = 0, DQS1 = 0
1332 23:34:53.379047 DQM Delay:
1333 23:34:53.381691 DQM0 = 91, DQM1 = 83
1334 23:34:53.382122 DQ Delay:
1335 23:34:53.385035 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =85
1336 23:34:53.388681 DQ4 =93, DQ5 =85, DQ6 =93, DQ7 =101
1337 23:34:53.391801 DQ8 =77, DQ9 =77, DQ10 =77, DQ11 =77
1338 23:34:53.395366 DQ12 =85, DQ13 =93, DQ14 =93, DQ15 =85
1339 23:34:53.396015
1340 23:34:53.396567
1341 23:34:53.397029 ==
1342 23:34:53.398797 Dram Type= 6, Freq= 0, CH_0, rank 1
1343 23:34:53.402016 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1344 23:34:53.404885 ==
1345 23:34:53.405313
1346 23:34:53.405686
1347 23:34:53.406005 TX Vref Scan disable
1348 23:34:53.408925 == TX Byte 0 ==
1349 23:34:53.411855 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
1350 23:34:53.415121 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
1351 23:34:53.418327 == TX Byte 1 ==
1352 23:34:53.421996 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1353 23:34:53.425604 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1354 23:34:53.426139 ==
1355 23:34:53.428398 Dram Type= 6, Freq= 0, CH_0, rank 1
1356 23:34:53.435024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1357 23:34:53.435674 ==
1358 23:34:53.447691 TX Vref=22, minBit 11, minWin=27, winSum=446
1359 23:34:53.451312 TX Vref=24, minBit 12, minWin=27, winSum=452
1360 23:34:53.454579 TX Vref=26, minBit 1, minWin=28, winSum=458
1361 23:34:53.458255 TX Vref=28, minBit 7, minWin=28, winSum=458
1362 23:34:53.461164 TX Vref=30, minBit 1, minWin=28, winSum=457
1363 23:34:53.464756 TX Vref=32, minBit 2, minWin=28, winSum=453
1364 23:34:53.471438 [TxChooseVref] Worse bit 1, Min win 28, Win sum 458, Final Vref 26
1365 23:34:53.471867
1366 23:34:53.474604 Final TX Range 1 Vref 26
1367 23:34:53.475030
1368 23:34:53.475421 ==
1369 23:34:53.478122 Dram Type= 6, Freq= 0, CH_0, rank 1
1370 23:34:53.481293 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1371 23:34:53.481746 ==
1372 23:34:53.482091
1373 23:34:53.484963
1374 23:34:53.485488 TX Vref Scan disable
1375 23:34:53.488071 == TX Byte 0 ==
1376 23:34:53.491329 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
1377 23:34:53.494901 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
1378 23:34:53.497757 == TX Byte 1 ==
1379 23:34:53.501372 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1380 23:34:53.504746 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1381 23:34:53.507954
1382 23:34:53.508599 [DATLAT]
1383 23:34:53.509082 Freq=800, CH0 RK1
1384 23:34:53.509546
1385 23:34:53.512000 DATLAT Default: 0xa
1386 23:34:53.512424 0, 0xFFFF, sum = 0
1387 23:34:53.514591 1, 0xFFFF, sum = 0
1388 23:34:53.515023 2, 0xFFFF, sum = 0
1389 23:34:53.518005 3, 0xFFFF, sum = 0
1390 23:34:53.518528 4, 0xFFFF, sum = 0
1391 23:34:53.521391 5, 0xFFFF, sum = 0
1392 23:34:53.521859 6, 0xFFFF, sum = 0
1393 23:34:53.524778 7, 0xFFFF, sum = 0
1394 23:34:53.527977 8, 0xFFFF, sum = 0
1395 23:34:53.528406 9, 0x0, sum = 1
1396 23:34:53.528752 10, 0x0, sum = 2
1397 23:34:53.531644 11, 0x0, sum = 3
1398 23:34:53.532075 12, 0x0, sum = 4
1399 23:34:53.534697 best_step = 10
1400 23:34:53.535118
1401 23:34:53.535457 ==
1402 23:34:53.538150 Dram Type= 6, Freq= 0, CH_0, rank 1
1403 23:34:53.541197 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1404 23:34:53.541654 ==
1405 23:34:53.544736 RX Vref Scan: 0
1406 23:34:53.545283
1407 23:34:53.545704 RX Vref 0 -> 0, step: 1
1408 23:34:53.546041
1409 23:34:53.548025 RX Delay -79 -> 252, step: 8
1410 23:34:53.554432 iDelay=209, Bit 0, Center 92 (-15 ~ 200) 216
1411 23:34:53.557889 iDelay=209, Bit 1, Center 96 (-7 ~ 200) 208
1412 23:34:53.561749 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1413 23:34:53.564926 iDelay=209, Bit 3, Center 88 (-23 ~ 200) 224
1414 23:34:53.567782 iDelay=209, Bit 4, Center 96 (-15 ~ 208) 224
1415 23:34:53.574557 iDelay=209, Bit 5, Center 88 (-23 ~ 200) 224
1416 23:34:53.577761 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1417 23:34:53.581132 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1418 23:34:53.585210 iDelay=209, Bit 8, Center 76 (-31 ~ 184) 216
1419 23:34:53.588384 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1420 23:34:53.594824 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1421 23:34:53.598499 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1422 23:34:53.601736 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
1423 23:34:53.604841 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1424 23:34:53.608017 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1425 23:34:53.614817 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1426 23:34:53.615398 ==
1427 23:34:53.618308 Dram Type= 6, Freq= 0, CH_0, rank 1
1428 23:34:53.621731 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1429 23:34:53.622300 ==
1430 23:34:53.622677 DQS Delay:
1431 23:34:53.624818 DQS0 = 0, DQS1 = 0
1432 23:34:53.625288 DQM Delay:
1433 23:34:53.628250 DQM0 = 93, DQM1 = 83
1434 23:34:53.628765 DQ Delay:
1435 23:34:53.631597 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1436 23:34:53.634778 DQ4 =96, DQ5 =88, DQ6 =100, DQ7 =100
1437 23:34:53.637702 DQ8 =76, DQ9 =72, DQ10 =84, DQ11 =76
1438 23:34:53.641357 DQ12 =92, DQ13 =84, DQ14 =92, DQ15 =88
1439 23:34:53.641926
1440 23:34:53.642277
1441 23:34:53.651309 [DQSOSCAuto] RK1, (LSB)MR18= 0x4314, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 393 ps
1442 23:34:53.651819 CH0 RK1: MR19=606, MR18=4314
1443 23:34:53.658308 CH0_RK1: MR19=0x606, MR18=0x4314, DQSOSC=393, MR23=63, INC=95, DEC=63
1444 23:34:53.661273 [RxdqsGatingPostProcess] freq 800
1445 23:34:53.667739 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1446 23:34:53.671351 Pre-setting of DQS Precalculation
1447 23:34:53.674546 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1448 23:34:53.675064 ==
1449 23:34:53.678064 Dram Type= 6, Freq= 0, CH_1, rank 0
1450 23:34:53.681251 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1451 23:34:53.681793 ==
1452 23:34:53.688124 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1453 23:34:53.694821 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1454 23:34:53.702888 [CA 0] Center 36 (6~67) winsize 62
1455 23:34:53.706341 [CA 1] Center 36 (6~67) winsize 62
1456 23:34:53.709845 [CA 2] Center 35 (5~66) winsize 62
1457 23:34:53.712838 [CA 3] Center 34 (4~65) winsize 62
1458 23:34:53.716087 [CA 4] Center 35 (5~65) winsize 61
1459 23:34:53.719332 [CA 5] Center 33 (3~64) winsize 62
1460 23:34:53.719900
1461 23:34:53.722642 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1462 23:34:53.723189
1463 23:34:53.726503 [CATrainingPosCal] consider 1 rank data
1464 23:34:53.729572 u2DelayCellTimex100 = 270/100 ps
1465 23:34:53.733359 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1466 23:34:53.739636 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1467 23:34:53.743002 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
1468 23:34:53.746054 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1469 23:34:53.749517 CA4 delay=35 (5~65),Diff = 2 PI (14 cell)
1470 23:34:53.752855 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1471 23:34:53.753343
1472 23:34:53.756529 CA PerBit enable=1, Macro0, CA PI delay=33
1473 23:34:53.757118
1474 23:34:53.759793 [CBTSetCACLKResult] CA Dly = 33
1475 23:34:53.763187 CS Dly: 6 (0~37)
1476 23:34:53.763786 ==
1477 23:34:53.766063 Dram Type= 6, Freq= 0, CH_1, rank 1
1478 23:34:53.769496 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1479 23:34:53.770030 ==
1480 23:34:53.776783 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1481 23:34:53.779498 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1482 23:34:53.790279 [CA 0] Center 36 (6~67) winsize 62
1483 23:34:53.793717 [CA 1] Center 37 (6~68) winsize 63
1484 23:34:53.797288 [CA 2] Center 35 (5~66) winsize 62
1485 23:34:53.801572 [CA 3] Center 34 (4~65) winsize 62
1486 23:34:53.805510 [CA 4] Center 35 (5~66) winsize 62
1487 23:34:53.806027 [CA 5] Center 34 (4~65) winsize 62
1488 23:34:53.806403
1489 23:34:53.809368 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1490 23:34:53.809969
1491 23:34:53.812606 [CATrainingPosCal] consider 2 rank data
1492 23:34:53.816275 u2DelayCellTimex100 = 270/100 ps
1493 23:34:53.819534 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1494 23:34:53.822824 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1495 23:34:53.829559 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
1496 23:34:53.833330 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1497 23:34:53.836290 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1498 23:34:53.839566 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1499 23:34:53.840089
1500 23:34:53.843157 CA PerBit enable=1, Macro0, CA PI delay=34
1501 23:34:53.843725
1502 23:34:53.846066 [CBTSetCACLKResult] CA Dly = 34
1503 23:34:53.846626 CS Dly: 7 (0~39)
1504 23:34:53.847008
1505 23:34:53.849423 ----->DramcWriteLeveling(PI) begin...
1506 23:34:53.852726 ==
1507 23:34:53.853200 Dram Type= 6, Freq= 0, CH_1, rank 0
1508 23:34:53.859937 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1509 23:34:53.860509 ==
1510 23:34:53.863272 Write leveling (Byte 0): 24 => 24
1511 23:34:53.866352 Write leveling (Byte 1): 24 => 24
1512 23:34:53.866824 DramcWriteLeveling(PI) end<-----
1513 23:34:53.869430
1514 23:34:53.869942 ==
1515 23:34:53.873261 Dram Type= 6, Freq= 0, CH_1, rank 0
1516 23:34:53.876606 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1517 23:34:53.877170 ==
1518 23:34:53.879757 [Gating] SW mode calibration
1519 23:34:53.886627 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1520 23:34:53.889760 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1521 23:34:53.896480 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1522 23:34:53.899646 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1523 23:34:53.902645 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 23:34:53.909417 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 23:34:53.912634 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 23:34:53.916535 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 23:34:53.923049 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 23:34:53.925902 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 23:34:53.929284 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 23:34:53.935808 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 23:34:53.939485 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 23:34:53.942721 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 23:34:53.949823 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 23:34:53.952698 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 23:34:53.956325 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 23:34:53.959799 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 23:34:53.966173 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 23:34:53.969544 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1539 23:34:53.972955 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1540 23:34:53.979536 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 23:34:53.983531 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1542 23:34:53.986566 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1543 23:34:53.993143 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1544 23:34:53.996468 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1545 23:34:53.999979 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1546 23:34:54.006793 0 9 4 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
1547 23:34:54.009980 0 9 8 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
1548 23:34:54.013056 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1549 23:34:54.020309 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1550 23:34:54.023118 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1551 23:34:54.026535 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1552 23:34:54.033424 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1553 23:34:54.036225 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
1554 23:34:54.039421 0 10 4 | B1->B0 | 3333 2f2f | 1 0 | (1 0) (0 0)
1555 23:34:54.046625 0 10 8 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
1556 23:34:54.049449 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1557 23:34:54.052718 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1558 23:34:54.056665 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1559 23:34:54.063095 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1560 23:34:54.066641 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1561 23:34:54.069949 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1562 23:34:54.076505 0 11 4 | B1->B0 | 2a2a 3939 | 0 0 | (0 0) (0 0)
1563 23:34:54.079722 0 11 8 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
1564 23:34:54.083279 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1565 23:34:54.090163 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1566 23:34:54.093715 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1567 23:34:54.096934 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1568 23:34:54.103356 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1569 23:34:54.107027 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1570 23:34:54.110071 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1571 23:34:54.113161 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 23:34:54.120467 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 23:34:54.123658 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1574 23:34:54.126358 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1575 23:34:54.133856 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1576 23:34:54.136540 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1577 23:34:54.139794 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1578 23:34:54.147041 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1579 23:34:54.149637 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1580 23:34:54.153340 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1581 23:34:54.159812 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1582 23:34:54.163729 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1583 23:34:54.167069 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1584 23:34:54.173664 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1585 23:34:54.176747 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1586 23:34:54.179633 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1587 23:34:54.183836 Total UI for P1: 0, mck2ui 16
1588 23:34:54.186660 best dqsien dly found for B1: ( 0, 14, 0)
1589 23:34:54.193724 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1590 23:34:54.194278 Total UI for P1: 0, mck2ui 16
1591 23:34:54.196531 best dqsien dly found for B0: ( 0, 14, 2)
1592 23:34:54.200366 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1593 23:34:54.206491 best DQS1 dly(MCK, UI, PI) = (0, 14, 0)
1594 23:34:54.207037
1595 23:34:54.210630 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1596 23:34:54.213227 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 0)
1597 23:34:54.217171 [Gating] SW calibration Done
1598 23:34:54.217777 ==
1599 23:34:54.220508 Dram Type= 6, Freq= 0, CH_1, rank 0
1600 23:34:54.223617 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1601 23:34:54.224186 ==
1602 23:34:54.224566 RX Vref Scan: 0
1603 23:34:54.224915
1604 23:34:54.227163 RX Vref 0 -> 0, step: 1
1605 23:34:54.227796
1606 23:34:54.230444 RX Delay -130 -> 252, step: 16
1607 23:34:54.233728 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1608 23:34:54.236908 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1609 23:34:54.243540 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1610 23:34:54.246868 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1611 23:34:54.250017 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1612 23:34:54.253617 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1613 23:34:54.257356 iDelay=222, Bit 6, Center 109 (-2 ~ 221) 224
1614 23:34:54.263561 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1615 23:34:54.267668 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1616 23:34:54.270598 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1617 23:34:54.273915 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1618 23:34:54.276772 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1619 23:34:54.283230 iDelay=222, Bit 12, Center 101 (-2 ~ 205) 208
1620 23:34:54.286711 iDelay=222, Bit 13, Center 101 (-2 ~ 205) 208
1621 23:34:54.290167 iDelay=222, Bit 14, Center 101 (-2 ~ 205) 208
1622 23:34:54.293315 iDelay=222, Bit 15, Center 101 (-2 ~ 205) 208
1623 23:34:54.293760 ==
1624 23:34:54.297234 Dram Type= 6, Freq= 0, CH_1, rank 0
1625 23:34:54.300224 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1626 23:34:54.304093 ==
1627 23:34:54.304619 DQS Delay:
1628 23:34:54.304957 DQS0 = 0, DQS1 = 0
1629 23:34:54.306871 DQM Delay:
1630 23:34:54.307390 DQM0 = 95, DQM1 = 91
1631 23:34:54.310620 DQ Delay:
1632 23:34:54.313659 DQ0 =101, DQ1 =85, DQ2 =77, DQ3 =93
1633 23:34:54.314260 DQ4 =93, DQ5 =109, DQ6 =109, DQ7 =93
1634 23:34:54.316886 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =85
1635 23:34:54.323682 DQ12 =101, DQ13 =101, DQ14 =101, DQ15 =101
1636 23:34:54.324246
1637 23:34:54.324619
1638 23:34:54.324960 ==
1639 23:34:54.326827 Dram Type= 6, Freq= 0, CH_1, rank 0
1640 23:34:54.330481 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1641 23:34:54.331049 ==
1642 23:34:54.331424
1643 23:34:54.331766
1644 23:34:54.333370 TX Vref Scan disable
1645 23:34:54.333860 == TX Byte 0 ==
1646 23:34:54.340152 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1647 23:34:54.343852 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1648 23:34:54.344416 == TX Byte 1 ==
1649 23:34:54.350384 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1650 23:34:54.354035 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1651 23:34:54.354542 ==
1652 23:34:54.357000 Dram Type= 6, Freq= 0, CH_1, rank 0
1653 23:34:54.360322 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1654 23:34:54.360738 ==
1655 23:34:54.373831 TX Vref=22, minBit 0, minWin=26, winSum=435
1656 23:34:54.377181 TX Vref=24, minBit 3, minWin=25, winSum=437
1657 23:34:54.380653 TX Vref=26, minBit 0, minWin=26, winSum=442
1658 23:34:54.384110 TX Vref=28, minBit 5, minWin=26, winSum=446
1659 23:34:54.387438 TX Vref=30, minBit 5, minWin=26, winSum=447
1660 23:34:54.390989 TX Vref=32, minBit 2, minWin=26, winSum=441
1661 23:34:54.397447 [TxChooseVref] Worse bit 5, Min win 26, Win sum 447, Final Vref 30
1662 23:34:54.398050
1663 23:34:54.400972 Final TX Range 1 Vref 30
1664 23:34:54.401495
1665 23:34:54.401880 ==
1666 23:34:54.404262 Dram Type= 6, Freq= 0, CH_1, rank 0
1667 23:34:54.407539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1668 23:34:54.407962 ==
1669 23:34:54.408300
1670 23:34:54.408616
1671 23:34:54.410775 TX Vref Scan disable
1672 23:34:54.414023 == TX Byte 0 ==
1673 23:34:54.417518 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1674 23:34:54.420819 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1675 23:34:54.424073 == TX Byte 1 ==
1676 23:34:54.427559 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1677 23:34:54.430730 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1678 23:34:54.431236
1679 23:34:54.434122 [DATLAT]
1680 23:34:54.434651 Freq=800, CH1 RK0
1681 23:34:54.434998
1682 23:34:54.437648 DATLAT Default: 0xa
1683 23:34:54.438208 0, 0xFFFF, sum = 0
1684 23:34:54.440976 1, 0xFFFF, sum = 0
1685 23:34:54.441403 2, 0xFFFF, sum = 0
1686 23:34:54.444311 3, 0xFFFF, sum = 0
1687 23:34:54.444734 4, 0xFFFF, sum = 0
1688 23:34:54.447533 5, 0xFFFF, sum = 0
1689 23:34:54.447957 6, 0xFFFF, sum = 0
1690 23:34:54.450936 7, 0xFFFF, sum = 0
1691 23:34:54.451368 8, 0xFFFF, sum = 0
1692 23:34:54.454204 9, 0x0, sum = 1
1693 23:34:54.454631 10, 0x0, sum = 2
1694 23:34:54.457935 11, 0x0, sum = 3
1695 23:34:54.458361 12, 0x0, sum = 4
1696 23:34:54.461291 best_step = 10
1697 23:34:54.461742
1698 23:34:54.462075 ==
1699 23:34:54.464665 Dram Type= 6, Freq= 0, CH_1, rank 0
1700 23:34:54.467784 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1701 23:34:54.468316 ==
1702 23:34:54.471155 RX Vref Scan: 1
1703 23:34:54.471574
1704 23:34:54.471909 Set Vref Range= 32 -> 127
1705 23:34:54.472224
1706 23:34:54.474148 RX Vref 32 -> 127, step: 1
1707 23:34:54.474570
1708 23:34:54.477666 RX Delay -79 -> 252, step: 8
1709 23:34:54.478092
1710 23:34:54.481209 Set Vref, RX VrefLevel [Byte0]: 32
1711 23:34:54.484495 [Byte1]: 32
1712 23:34:54.485026
1713 23:34:54.487946 Set Vref, RX VrefLevel [Byte0]: 33
1714 23:34:54.491343 [Byte1]: 33
1715 23:34:54.491876
1716 23:34:54.494326 Set Vref, RX VrefLevel [Byte0]: 34
1717 23:34:54.498326 [Byte1]: 34
1718 23:34:54.501778
1719 23:34:54.502305 Set Vref, RX VrefLevel [Byte0]: 35
1720 23:34:54.505436 [Byte1]: 35
1721 23:34:54.509535
1722 23:34:54.510120 Set Vref, RX VrefLevel [Byte0]: 36
1723 23:34:54.512687 [Byte1]: 36
1724 23:34:54.516880
1725 23:34:54.517435 Set Vref, RX VrefLevel [Byte0]: 37
1726 23:34:54.520185 [Byte1]: 37
1727 23:34:54.524309
1728 23:34:54.524837 Set Vref, RX VrefLevel [Byte0]: 38
1729 23:34:54.527682 [Byte1]: 38
1730 23:34:54.531673
1731 23:34:54.532092 Set Vref, RX VrefLevel [Byte0]: 39
1732 23:34:54.535260 [Byte1]: 39
1733 23:34:54.539557
1734 23:34:54.539978 Set Vref, RX VrefLevel [Byte0]: 40
1735 23:34:54.542789 [Byte1]: 40
1736 23:34:54.547404
1737 23:34:54.547933 Set Vref, RX VrefLevel [Byte0]: 41
1738 23:34:54.550040 [Byte1]: 41
1739 23:34:54.555067
1740 23:34:54.555655 Set Vref, RX VrefLevel [Byte0]: 42
1741 23:34:54.558312 [Byte1]: 42
1742 23:34:54.562306
1743 23:34:54.562722 Set Vref, RX VrefLevel [Byte0]: 43
1744 23:34:54.565340 [Byte1]: 43
1745 23:34:54.569780
1746 23:34:54.570307 Set Vref, RX VrefLevel [Byte0]: 44
1747 23:34:54.573395 [Byte1]: 44
1748 23:34:54.577689
1749 23:34:54.578223 Set Vref, RX VrefLevel [Byte0]: 45
1750 23:34:54.580588 [Byte1]: 45
1751 23:34:54.584559
1752 23:34:54.585086 Set Vref, RX VrefLevel [Byte0]: 46
1753 23:34:54.588130 [Byte1]: 46
1754 23:34:54.592352
1755 23:34:54.592880 Set Vref, RX VrefLevel [Byte0]: 47
1756 23:34:54.595660 [Byte1]: 47
1757 23:34:54.600035
1758 23:34:54.600695 Set Vref, RX VrefLevel [Byte0]: 48
1759 23:34:54.603227 [Byte1]: 48
1760 23:34:54.607114
1761 23:34:54.607533 Set Vref, RX VrefLevel [Byte0]: 49
1762 23:34:54.610448 [Byte1]: 49
1763 23:34:54.614847
1764 23:34:54.615377 Set Vref, RX VrefLevel [Byte0]: 50
1765 23:34:54.618437 [Byte1]: 50
1766 23:34:54.622160
1767 23:34:54.622663 Set Vref, RX VrefLevel [Byte0]: 51
1768 23:34:54.625562 [Byte1]: 51
1769 23:34:54.630123
1770 23:34:54.630643 Set Vref, RX VrefLevel [Byte0]: 52
1771 23:34:54.633214 [Byte1]: 52
1772 23:34:54.637420
1773 23:34:54.637870 Set Vref, RX VrefLevel [Byte0]: 53
1774 23:34:54.640607 [Byte1]: 53
1775 23:34:54.645361
1776 23:34:54.645924 Set Vref, RX VrefLevel [Byte0]: 54
1777 23:34:54.648560 [Byte1]: 54
1778 23:34:54.652844
1779 23:34:54.653366 Set Vref, RX VrefLevel [Byte0]: 55
1780 23:34:54.656105 [Byte1]: 55
1781 23:34:54.660336
1782 23:34:54.660872 Set Vref, RX VrefLevel [Byte0]: 56
1783 23:34:54.663565 [Byte1]: 56
1784 23:34:54.667905
1785 23:34:54.668451 Set Vref, RX VrefLevel [Byte0]: 57
1786 23:34:54.670849 [Byte1]: 57
1787 23:34:54.675438
1788 23:34:54.676008 Set Vref, RX VrefLevel [Byte0]: 58
1789 23:34:54.679044 [Byte1]: 58
1790 23:34:54.682835
1791 23:34:54.683303 Set Vref, RX VrefLevel [Byte0]: 59
1792 23:34:54.687034 [Byte1]: 59
1793 23:34:54.690608
1794 23:34:54.691174 Set Vref, RX VrefLevel [Byte0]: 60
1795 23:34:54.693672 [Byte1]: 60
1796 23:34:54.698210
1797 23:34:54.698780 Set Vref, RX VrefLevel [Byte0]: 61
1798 23:34:54.701751 [Byte1]: 61
1799 23:34:54.705743
1800 23:34:54.706270 Set Vref, RX VrefLevel [Byte0]: 62
1801 23:34:54.708831 [Byte1]: 62
1802 23:34:54.713317
1803 23:34:54.713965 Set Vref, RX VrefLevel [Byte0]: 63
1804 23:34:54.716635 [Byte1]: 63
1805 23:34:54.720309
1806 23:34:54.720772 Set Vref, RX VrefLevel [Byte0]: 64
1807 23:34:54.724377 [Byte1]: 64
1808 23:34:54.728164
1809 23:34:54.728728 Set Vref, RX VrefLevel [Byte0]: 65
1810 23:34:54.731396 [Byte1]: 65
1811 23:34:54.735828
1812 23:34:54.736356 Set Vref, RX VrefLevel [Byte0]: 66
1813 23:34:54.739008 [Byte1]: 66
1814 23:34:54.743358
1815 23:34:54.743887 Set Vref, RX VrefLevel [Byte0]: 67
1816 23:34:54.746514 [Byte1]: 67
1817 23:34:54.750648
1818 23:34:54.751062 Set Vref, RX VrefLevel [Byte0]: 68
1819 23:34:54.753683 [Byte1]: 68
1820 23:34:54.758098
1821 23:34:54.758521 Set Vref, RX VrefLevel [Byte0]: 69
1822 23:34:54.762173 [Byte1]: 69
1823 23:34:54.766108
1824 23:34:54.766523 Set Vref, RX VrefLevel [Byte0]: 70
1825 23:34:54.769533 [Byte1]: 70
1826 23:34:54.773519
1827 23:34:54.774095 Set Vref, RX VrefLevel [Byte0]: 71
1828 23:34:54.776838 [Byte1]: 71
1829 23:34:54.780844
1830 23:34:54.781278 Set Vref, RX VrefLevel [Byte0]: 72
1831 23:34:54.784249 [Byte1]: 72
1832 23:34:54.788556
1833 23:34:54.789094 Final RX Vref Byte 0 = 58 to rank0
1834 23:34:54.791880 Final RX Vref Byte 1 = 53 to rank0
1835 23:34:54.795311 Final RX Vref Byte 0 = 58 to rank1
1836 23:34:54.798162 Final RX Vref Byte 1 = 53 to rank1==
1837 23:34:54.801686 Dram Type= 6, Freq= 0, CH_1, rank 0
1838 23:34:54.808468 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1839 23:34:54.808994 ==
1840 23:34:54.809330 DQS Delay:
1841 23:34:54.809732 DQS0 = 0, DQS1 = 0
1842 23:34:54.812019 DQM Delay:
1843 23:34:54.812478 DQM0 = 96, DQM1 = 90
1844 23:34:54.815210 DQ Delay:
1845 23:34:54.818609 DQ0 =100, DQ1 =88, DQ2 =84, DQ3 =92
1846 23:34:54.821722 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =96
1847 23:34:54.825015 DQ8 =76, DQ9 =80, DQ10 =92, DQ11 =84
1848 23:34:54.828448 DQ12 =96, DQ13 =100, DQ14 =96, DQ15 =100
1849 23:34:54.829008
1850 23:34:54.829377
1851 23:34:54.835250 [DQSOSCAuto] RK0, (LSB)MR18= 0x2e4b, (MSB)MR19= 0x606, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
1852 23:34:54.838249 CH1 RK0: MR19=606, MR18=2E4B
1853 23:34:54.845448 CH1_RK0: MR19=0x606, MR18=0x2E4B, DQSOSC=391, MR23=63, INC=96, DEC=64
1854 23:34:54.846058
1855 23:34:54.848856 ----->DramcWriteLeveling(PI) begin...
1856 23:34:54.849324 ==
1857 23:34:54.851867 Dram Type= 6, Freq= 0, CH_1, rank 1
1858 23:34:54.855046 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1859 23:34:54.855570 ==
1860 23:34:54.858594 Write leveling (Byte 0): 28 => 28
1861 23:34:54.861813 Write leveling (Byte 1): 28 => 28
1862 23:34:54.865688 DramcWriteLeveling(PI) end<-----
1863 23:34:54.866114
1864 23:34:54.866450 ==
1865 23:34:54.868584 Dram Type= 6, Freq= 0, CH_1, rank 1
1866 23:34:54.872486 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1867 23:34:54.873018 ==
1868 23:34:54.875796 [Gating] SW mode calibration
1869 23:34:54.881814 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1870 23:34:54.888804 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1871 23:34:54.892244 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1872 23:34:54.895926 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1873 23:34:54.902415 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 23:34:54.905606 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 23:34:54.908663 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 23:34:54.915664 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 23:34:54.919095 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 23:34:54.922307 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 23:34:54.929369 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 23:34:54.932328 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 23:34:54.935637 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 23:34:54.938939 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 23:34:54.945913 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 23:34:54.948919 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 23:34:54.952226 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 23:34:54.958994 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1887 23:34:54.962184 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1888 23:34:54.965802 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1889 23:34:54.972368 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 23:34:54.975980 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 23:34:54.978811 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 23:34:54.985981 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 23:34:54.989247 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1894 23:34:54.993012 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 23:34:54.999112 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 23:34:55.002198 0 9 4 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
1897 23:34:55.005881 0 9 8 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
1898 23:34:55.013016 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1899 23:34:55.015808 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1900 23:34:55.019396 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1901 23:34:55.022543 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1902 23:34:55.029606 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1903 23:34:55.033076 0 10 0 | B1->B0 | 3333 3434 | 1 1 | (1 0) (1 0)
1904 23:34:55.035605 0 10 4 | B1->B0 | 2e2e 3232 | 1 0 | (1 0) (0 1)
1905 23:34:55.042591 0 10 8 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
1906 23:34:55.045977 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1907 23:34:55.048935 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1908 23:34:55.055482 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1909 23:34:55.059321 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1910 23:34:55.062208 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1911 23:34:55.069142 0 11 0 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1912 23:34:55.072757 0 11 4 | B1->B0 | 3939 2929 | 1 0 | (1 1) (0 0)
1913 23:34:55.075827 0 11 8 | B1->B0 | 4646 4343 | 0 0 | (0 0) (1 1)
1914 23:34:55.082571 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1915 23:34:55.086280 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1916 23:34:55.089519 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1917 23:34:55.092703 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1918 23:34:55.099996 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1919 23:34:55.102470 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1920 23:34:55.106126 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1921 23:34:55.112943 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1922 23:34:55.116247 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1923 23:34:55.119163 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1924 23:34:55.125917 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1925 23:34:55.129290 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1926 23:34:55.132461 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1927 23:34:55.139171 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1928 23:34:55.142421 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1929 23:34:55.145899 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1930 23:34:55.152538 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1931 23:34:55.155747 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1932 23:34:55.159217 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1933 23:34:55.165855 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1934 23:34:55.169114 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1935 23:34:55.172420 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1936 23:34:55.179436 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1937 23:34:55.182649 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1938 23:34:55.186491 Total UI for P1: 0, mck2ui 16
1939 23:34:55.189473 best dqsien dly found for B0: ( 0, 14, 2)
1940 23:34:55.192677 Total UI for P1: 0, mck2ui 16
1941 23:34:55.195868 best dqsien dly found for B1: ( 0, 14, 4)
1942 23:34:55.199244 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1943 23:34:55.202687 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1944 23:34:55.203245
1945 23:34:55.206316 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1946 23:34:55.209603 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1947 23:34:55.212465 [Gating] SW calibration Done
1948 23:34:55.212887 ==
1949 23:34:55.215554 Dram Type= 6, Freq= 0, CH_1, rank 1
1950 23:34:55.219211 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1951 23:34:55.219747 ==
1952 23:34:55.222727 RX Vref Scan: 0
1953 23:34:55.223256
1954 23:34:55.223595 RX Vref 0 -> 0, step: 1
1955 23:34:55.226071
1956 23:34:55.226489 RX Delay -130 -> 252, step: 16
1957 23:34:55.232332 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1958 23:34:55.236099 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1959 23:34:55.239530 iDelay=222, Bit 2, Center 85 (-18 ~ 189) 208
1960 23:34:55.242689 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1961 23:34:55.245811 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1962 23:34:55.252449 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1963 23:34:55.255861 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1964 23:34:55.259518 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1965 23:34:55.262259 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1966 23:34:55.265855 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1967 23:34:55.272609 iDelay=222, Bit 10, Center 93 (-18 ~ 205) 224
1968 23:34:55.275809 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1969 23:34:55.279226 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1970 23:34:55.282732 iDelay=222, Bit 13, Center 101 (-2 ~ 205) 208
1971 23:34:55.286212 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1972 23:34:55.292436 iDelay=222, Bit 15, Center 101 (-2 ~ 205) 208
1973 23:34:55.292993 ==
1974 23:34:55.295697 Dram Type= 6, Freq= 0, CH_1, rank 1
1975 23:34:55.299170 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1976 23:34:55.299702 ==
1977 23:34:55.300045 DQS Delay:
1978 23:34:55.302820 DQS0 = 0, DQS1 = 0
1979 23:34:55.303353 DQM Delay:
1980 23:34:55.305625 DQM0 = 93, DQM1 = 90
1981 23:34:55.306059 DQ Delay:
1982 23:34:55.309275 DQ0 =101, DQ1 =85, DQ2 =85, DQ3 =85
1983 23:34:55.312680 DQ4 =85, DQ5 =109, DQ6 =101, DQ7 =93
1984 23:34:55.315707 DQ8 =77, DQ9 =77, DQ10 =93, DQ11 =85
1985 23:34:55.318999 DQ12 =93, DQ13 =101, DQ14 =93, DQ15 =101
1986 23:34:55.319578
1987 23:34:55.319932
1988 23:34:55.320245 ==
1989 23:34:55.322263 Dram Type= 6, Freq= 0, CH_1, rank 1
1990 23:34:55.326013 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1991 23:34:55.329800 ==
1992 23:34:55.330327
1993 23:34:55.330663
1994 23:34:55.330972 TX Vref Scan disable
1995 23:34:55.332651 == TX Byte 0 ==
1996 23:34:55.336251 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1997 23:34:55.338843 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1998 23:34:55.342639 == TX Byte 1 ==
1999 23:34:55.345823 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2000 23:34:55.349100 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2001 23:34:55.349675 ==
2002 23:34:55.352768 Dram Type= 6, Freq= 0, CH_1, rank 1
2003 23:34:55.359057 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2004 23:34:55.359567 ==
2005 23:34:55.371550 TX Vref=22, minBit 3, minWin=26, winSum=441
2006 23:34:55.374728 TX Vref=24, minBit 1, minWin=27, winSum=446
2007 23:34:55.377974 TX Vref=26, minBit 1, minWin=27, winSum=454
2008 23:34:55.381819 TX Vref=28, minBit 1, minWin=27, winSum=455
2009 23:34:55.384656 TX Vref=30, minBit 2, minWin=27, winSum=455
2010 23:34:55.388174 TX Vref=32, minBit 0, minWin=27, winSum=450
2011 23:34:55.394737 [TxChooseVref] Worse bit 1, Min win 27, Win sum 455, Final Vref 28
2012 23:34:55.395338
2013 23:34:55.398022 Final TX Range 1 Vref 28
2014 23:34:55.398484
2015 23:34:55.398855 ==
2016 23:34:55.401666 Dram Type= 6, Freq= 0, CH_1, rank 1
2017 23:34:55.404557 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2018 23:34:55.405220 ==
2019 23:34:55.405641
2020 23:34:55.406003
2021 23:34:55.408156 TX Vref Scan disable
2022 23:34:55.411759 == TX Byte 0 ==
2023 23:34:55.414677 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2024 23:34:55.418055 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2025 23:34:55.421476 == TX Byte 1 ==
2026 23:34:55.424679 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2027 23:34:55.428969 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2028 23:34:55.429545
2029 23:34:55.431771 [DATLAT]
2030 23:34:55.432418 Freq=800, CH1 RK1
2031 23:34:55.432807
2032 23:34:55.434826 DATLAT Default: 0xa
2033 23:34:55.435288 0, 0xFFFF, sum = 0
2034 23:34:55.438496 1, 0xFFFF, sum = 0
2035 23:34:55.439085 2, 0xFFFF, sum = 0
2036 23:34:55.441305 3, 0xFFFF, sum = 0
2037 23:34:55.441905 4, 0xFFFF, sum = 0
2038 23:34:55.444999 5, 0xFFFF, sum = 0
2039 23:34:55.445564 6, 0xFFFF, sum = 0
2040 23:34:55.448290 7, 0xFFFF, sum = 0
2041 23:34:55.448816 8, 0xFFFF, sum = 0
2042 23:34:55.451754 9, 0x0, sum = 1
2043 23:34:55.452281 10, 0x0, sum = 2
2044 23:34:55.454908 11, 0x0, sum = 3
2045 23:34:55.455331 12, 0x0, sum = 4
2046 23:34:55.458509 best_step = 10
2047 23:34:55.459072
2048 23:34:55.459440 ==
2049 23:34:55.461532 Dram Type= 6, Freq= 0, CH_1, rank 1
2050 23:34:55.465085 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2051 23:34:55.465562 ==
2052 23:34:55.466019 RX Vref Scan: 0
2053 23:34:55.468306
2054 23:34:55.468765 RX Vref 0 -> 0, step: 1
2055 23:34:55.469179
2056 23:34:55.472086 RX Delay -79 -> 252, step: 8
2057 23:34:55.475154 iDelay=209, Bit 0, Center 104 (9 ~ 200) 192
2058 23:34:55.482514 iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200
2059 23:34:55.484965 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
2060 23:34:55.488829 iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200
2061 23:34:55.491929 iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200
2062 23:34:55.495237 iDelay=209, Bit 5, Center 112 (17 ~ 208) 192
2063 23:34:55.498594 iDelay=209, Bit 6, Center 108 (9 ~ 208) 200
2064 23:34:55.505314 iDelay=209, Bit 7, Center 96 (-7 ~ 200) 208
2065 23:34:55.508799 iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208
2066 23:34:55.511807 iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208
2067 23:34:55.515038 iDelay=209, Bit 10, Center 92 (-7 ~ 192) 200
2068 23:34:55.518638 iDelay=209, Bit 11, Center 84 (-15 ~ 184) 200
2069 23:34:55.524765 iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216
2070 23:34:55.528805 iDelay=209, Bit 13, Center 96 (-7 ~ 200) 208
2071 23:34:55.531928 iDelay=209, Bit 14, Center 96 (-7 ~ 200) 208
2072 23:34:55.535289 iDelay=209, Bit 15, Center 96 (-7 ~ 200) 208
2073 23:34:55.535854 ==
2074 23:34:55.538618 Dram Type= 6, Freq= 0, CH_1, rank 1
2075 23:34:55.541771 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2076 23:34:55.545043 ==
2077 23:34:55.545683 DQS Delay:
2078 23:34:55.546070 DQS0 = 0, DQS1 = 0
2079 23:34:55.548687 DQM Delay:
2080 23:34:55.549271 DQM0 = 97, DQM1 = 90
2081 23:34:55.551920 DQ Delay:
2082 23:34:55.555536 DQ0 =104, DQ1 =92, DQ2 =84, DQ3 =92
2083 23:34:55.558336 DQ4 =92, DQ5 =112, DQ6 =108, DQ7 =96
2084 23:34:55.558799 DQ8 =80, DQ9 =80, DQ10 =92, DQ11 =84
2085 23:34:55.565501 DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =96
2086 23:34:55.566134
2087 23:34:55.566510
2088 23:34:55.571805 [DQSOSCAuto] RK1, (LSB)MR18= 0x440f, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 392 ps
2089 23:34:55.575206 CH1 RK1: MR19=606, MR18=440F
2090 23:34:55.582284 CH1_RK1: MR19=0x606, MR18=0x440F, DQSOSC=392, MR23=63, INC=96, DEC=64
2091 23:34:55.585544 [RxdqsGatingPostProcess] freq 800
2092 23:34:55.588854 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2093 23:34:55.592365 Pre-setting of DQS Precalculation
2094 23:34:55.598908 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2095 23:34:55.606229 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2096 23:34:55.612490 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2097 23:34:55.613066
2098 23:34:55.613436
2099 23:34:55.615249 [Calibration Summary] 1600 Mbps
2100 23:34:55.615710 CH 0, Rank 0
2101 23:34:55.618605 SW Impedance : PASS
2102 23:34:55.622109 DUTY Scan : NO K
2103 23:34:55.622576 ZQ Calibration : PASS
2104 23:34:55.625077 Jitter Meter : NO K
2105 23:34:55.625496 CBT Training : PASS
2106 23:34:55.629056 Write leveling : PASS
2107 23:34:55.631899 RX DQS gating : PASS
2108 23:34:55.632429 RX DQ/DQS(RDDQC) : PASS
2109 23:34:55.635421 TX DQ/DQS : PASS
2110 23:34:55.638722 RX DATLAT : PASS
2111 23:34:55.639257 RX DQ/DQS(Engine): PASS
2112 23:34:55.642243 TX OE : NO K
2113 23:34:55.642665 All Pass.
2114 23:34:55.642997
2115 23:34:55.645417 CH 0, Rank 1
2116 23:34:55.645874 SW Impedance : PASS
2117 23:34:55.649217 DUTY Scan : NO K
2118 23:34:55.652108 ZQ Calibration : PASS
2119 23:34:55.652632 Jitter Meter : NO K
2120 23:34:55.655947 CBT Training : PASS
2121 23:34:55.658844 Write leveling : PASS
2122 23:34:55.659270 RX DQS gating : PASS
2123 23:34:55.661904 RX DQ/DQS(RDDQC) : PASS
2124 23:34:55.662323 TX DQ/DQS : PASS
2125 23:34:55.665462 RX DATLAT : PASS
2126 23:34:55.668621 RX DQ/DQS(Engine): PASS
2127 23:34:55.669045 TX OE : NO K
2128 23:34:55.671893 All Pass.
2129 23:34:55.672316
2130 23:34:55.672762 CH 1, Rank 0
2131 23:34:55.675346 SW Impedance : PASS
2132 23:34:55.675768 DUTY Scan : NO K
2133 23:34:55.678539 ZQ Calibration : PASS
2134 23:34:55.682552 Jitter Meter : NO K
2135 23:34:55.683104 CBT Training : PASS
2136 23:34:55.685767 Write leveling : PASS
2137 23:34:55.689006 RX DQS gating : PASS
2138 23:34:55.689533 RX DQ/DQS(RDDQC) : PASS
2139 23:34:55.692279 TX DQ/DQS : PASS
2140 23:34:55.695988 RX DATLAT : PASS
2141 23:34:55.696515 RX DQ/DQS(Engine): PASS
2142 23:34:55.699236 TX OE : NO K
2143 23:34:55.699760 All Pass.
2144 23:34:55.700097
2145 23:34:55.702291 CH 1, Rank 1
2146 23:34:55.702835 SW Impedance : PASS
2147 23:34:55.705749 DUTY Scan : NO K
2148 23:34:55.706275 ZQ Calibration : PASS
2149 23:34:55.708760 Jitter Meter : NO K
2150 23:34:55.712375 CBT Training : PASS
2151 23:34:55.712903 Write leveling : PASS
2152 23:34:55.715682 RX DQS gating : PASS
2153 23:34:55.718858 RX DQ/DQS(RDDQC) : PASS
2154 23:34:55.719405 TX DQ/DQS : PASS
2155 23:34:55.722312 RX DATLAT : PASS
2156 23:34:55.725235 RX DQ/DQS(Engine): PASS
2157 23:34:55.725735 TX OE : NO K
2158 23:34:55.729153 All Pass.
2159 23:34:55.729736
2160 23:34:55.730084 DramC Write-DBI off
2161 23:34:55.732384 PER_BANK_REFRESH: Hybrid Mode
2162 23:34:55.732908 TX_TRACKING: ON
2163 23:34:55.735227 [GetDramInforAfterCalByMRR] Vendor 6.
2164 23:34:55.742040 [GetDramInforAfterCalByMRR] Revision 606.
2165 23:34:55.745680 [GetDramInforAfterCalByMRR] Revision 2 0.
2166 23:34:55.746211 MR0 0x3b3b
2167 23:34:55.746559 MR8 0x5151
2168 23:34:55.748708 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2169 23:34:55.752153
2170 23:34:55.752674 MR0 0x3b3b
2171 23:34:55.753015 MR8 0x5151
2172 23:34:55.755083 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2173 23:34:55.755506
2174 23:34:55.765734 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2175 23:34:55.768453 [FAST_K] Save calibration result to emmc
2176 23:34:55.771979 [FAST_K] Save calibration result to emmc
2177 23:34:55.775194 dram_init: config_dvfs: 1
2178 23:34:55.778432 dramc_set_vcore_voltage set vcore to 662500
2179 23:34:55.782286 Read voltage for 1200, 2
2180 23:34:55.782834 Vio18 = 0
2181 23:34:55.783186 Vcore = 662500
2182 23:34:55.785089 Vdram = 0
2183 23:34:55.785521 Vddq = 0
2184 23:34:55.785884 Vmddr = 0
2185 23:34:55.791770 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2186 23:34:55.795280 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2187 23:34:55.798724 MEM_TYPE=3, freq_sel=15
2188 23:34:55.802343 sv_algorithm_assistance_LP4_1600
2189 23:34:55.805714 ============ PULL DRAM RESETB DOWN ============
2190 23:34:55.808880 ========== PULL DRAM RESETB DOWN end =========
2191 23:34:55.815372 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2192 23:34:55.818783 ===================================
2193 23:34:55.819251 LPDDR4 DRAM CONFIGURATION
2194 23:34:55.822187 ===================================
2195 23:34:55.826097 EX_ROW_EN[0] = 0x0
2196 23:34:55.828754 EX_ROW_EN[1] = 0x0
2197 23:34:55.829323 LP4Y_EN = 0x0
2198 23:34:55.832527 WORK_FSP = 0x0
2199 23:34:55.833097 WL = 0x4
2200 23:34:55.835483 RL = 0x4
2201 23:34:55.835951 BL = 0x2
2202 23:34:55.839131 RPST = 0x0
2203 23:34:55.839766 RD_PRE = 0x0
2204 23:34:55.842614 WR_PRE = 0x1
2205 23:34:55.843190 WR_PST = 0x0
2206 23:34:55.845750 DBI_WR = 0x0
2207 23:34:55.846325 DBI_RD = 0x0
2208 23:34:55.848807 OTF = 0x1
2209 23:34:55.851782 ===================================
2210 23:34:55.855855 ===================================
2211 23:34:55.856435 ANA top config
2212 23:34:55.858642 ===================================
2213 23:34:55.861987 DLL_ASYNC_EN = 0
2214 23:34:55.865686 ALL_SLAVE_EN = 0
2215 23:34:55.866267 NEW_RANK_MODE = 1
2216 23:34:55.868726 DLL_IDLE_MODE = 1
2217 23:34:55.871898 LP45_APHY_COMB_EN = 1
2218 23:34:55.875346 TX_ODT_DIS = 1
2219 23:34:55.879317 NEW_8X_MODE = 1
2220 23:34:55.882281 ===================================
2221 23:34:55.885208 ===================================
2222 23:34:55.885709 data_rate = 2400
2223 23:34:55.888716 CKR = 1
2224 23:34:55.892351 DQ_P2S_RATIO = 8
2225 23:34:55.895368 ===================================
2226 23:34:55.898858 CA_P2S_RATIO = 8
2227 23:34:55.901786 DQ_CA_OPEN = 0
2228 23:34:55.905889 DQ_SEMI_OPEN = 0
2229 23:34:55.906617 CA_SEMI_OPEN = 0
2230 23:34:55.908513 CA_FULL_RATE = 0
2231 23:34:55.912009 DQ_CKDIV4_EN = 0
2232 23:34:55.915400 CA_CKDIV4_EN = 0
2233 23:34:55.918941 CA_PREDIV_EN = 0
2234 23:34:55.921970 PH8_DLY = 17
2235 23:34:55.922433 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2236 23:34:55.925534 DQ_AAMCK_DIV = 4
2237 23:34:55.928369 CA_AAMCK_DIV = 4
2238 23:34:55.931742 CA_ADMCK_DIV = 4
2239 23:34:55.935400 DQ_TRACK_CA_EN = 0
2240 23:34:55.938331 CA_PICK = 1200
2241 23:34:55.938734 CA_MCKIO = 1200
2242 23:34:55.941923 MCKIO_SEMI = 0
2243 23:34:55.944998 PLL_FREQ = 2366
2244 23:34:55.948351 DQ_UI_PI_RATIO = 32
2245 23:34:55.951568 CA_UI_PI_RATIO = 0
2246 23:34:55.955425 ===================================
2247 23:34:55.958730 ===================================
2248 23:34:55.961882 memory_type:LPDDR4
2249 23:34:55.962335 GP_NUM : 10
2250 23:34:55.965160 SRAM_EN : 1
2251 23:34:55.965507 MD32_EN : 0
2252 23:34:55.968863 ===================================
2253 23:34:55.971661 [ANA_INIT] >>>>>>>>>>>>>>
2254 23:34:55.974989 <<<<<< [CONFIGURE PHASE]: ANA_TX
2255 23:34:55.978615 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2256 23:34:55.981500 ===================================
2257 23:34:55.984819 data_rate = 2400,PCW = 0X5b00
2258 23:34:55.988234 ===================================
2259 23:34:55.991608 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2260 23:34:55.995663 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2261 23:34:56.001594 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2262 23:34:56.008447 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2263 23:34:56.012073 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2264 23:34:56.015153 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2265 23:34:56.015446 [ANA_INIT] flow start
2266 23:34:56.018294 [ANA_INIT] PLL >>>>>>>>
2267 23:34:56.022018 [ANA_INIT] PLL <<<<<<<<
2268 23:34:56.022349 [ANA_INIT] MIDPI >>>>>>>>
2269 23:34:56.025389 [ANA_INIT] MIDPI <<<<<<<<
2270 23:34:56.029139 [ANA_INIT] DLL >>>>>>>>
2271 23:34:56.029681 [ANA_INIT] DLL <<<<<<<<
2272 23:34:56.032040 [ANA_INIT] flow end
2273 23:34:56.035031 ============ LP4 DIFF to SE enter ============
2274 23:34:56.038925 ============ LP4 DIFF to SE exit ============
2275 23:34:56.042184 [ANA_INIT] <<<<<<<<<<<<<
2276 23:34:56.045494 [Flow] Enable top DCM control >>>>>
2277 23:34:56.048326 [Flow] Enable top DCM control <<<<<
2278 23:34:56.051621 Enable DLL master slave shuffle
2279 23:34:56.058751 ==============================================================
2280 23:34:56.059326 Gating Mode config
2281 23:34:56.065559 ==============================================================
2282 23:34:56.066189 Config description:
2283 23:34:56.075581 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2284 23:34:56.082296 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2285 23:34:56.088893 SELPH_MODE 0: By rank 1: By Phase
2286 23:34:56.091662 ==============================================================
2287 23:34:56.095387 GAT_TRACK_EN = 1
2288 23:34:56.098915 RX_GATING_MODE = 2
2289 23:34:56.102411 RX_GATING_TRACK_MODE = 2
2290 23:34:56.105260 SELPH_MODE = 1
2291 23:34:56.108581 PICG_EARLY_EN = 1
2292 23:34:56.111720 VALID_LAT_VALUE = 1
2293 23:34:56.115303 ==============================================================
2294 23:34:56.118418 Enter into Gating configuration >>>>
2295 23:34:56.121762 Exit from Gating configuration <<<<
2296 23:34:56.125469 Enter into DVFS_PRE_config >>>>>
2297 23:34:56.138637 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2298 23:34:56.141988 Exit from DVFS_PRE_config <<<<<
2299 23:34:56.145527 Enter into PICG configuration >>>>
2300 23:34:56.148279 Exit from PICG configuration <<<<
2301 23:34:56.148981 [RX_INPUT] configuration >>>>>
2302 23:34:56.151631 [RX_INPUT] configuration <<<<<
2303 23:34:56.158546 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2304 23:34:56.161646 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2305 23:34:56.168277 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2306 23:34:56.175344 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2307 23:34:56.182588 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2308 23:34:56.188668 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2309 23:34:56.192461 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2310 23:34:56.195779 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2311 23:34:56.198456 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2312 23:34:56.205149 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2313 23:34:56.208673 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2314 23:34:56.211748 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2315 23:34:56.215338 ===================================
2316 23:34:56.218332 LPDDR4 DRAM CONFIGURATION
2317 23:34:56.221676 ===================================
2318 23:34:56.225183 EX_ROW_EN[0] = 0x0
2319 23:34:56.225707 EX_ROW_EN[1] = 0x0
2320 23:34:56.228505 LP4Y_EN = 0x0
2321 23:34:56.229083 WORK_FSP = 0x0
2322 23:34:56.231539 WL = 0x4
2323 23:34:56.232004 RL = 0x4
2324 23:34:56.235067 BL = 0x2
2325 23:34:56.235542 RPST = 0x0
2326 23:34:56.238439 RD_PRE = 0x0
2327 23:34:56.238865 WR_PRE = 0x1
2328 23:34:56.242076 WR_PST = 0x0
2329 23:34:56.242651 DBI_WR = 0x0
2330 23:34:56.245478 DBI_RD = 0x0
2331 23:34:56.245981 OTF = 0x1
2332 23:34:56.248396 ===================================
2333 23:34:56.252096 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2334 23:34:56.258846 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2335 23:34:56.262303 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2336 23:34:56.265616 ===================================
2337 23:34:56.268663 LPDDR4 DRAM CONFIGURATION
2338 23:34:56.272184 ===================================
2339 23:34:56.272656 EX_ROW_EN[0] = 0x10
2340 23:34:56.275499 EX_ROW_EN[1] = 0x0
2341 23:34:56.276093 LP4Y_EN = 0x0
2342 23:34:56.278462 WORK_FSP = 0x0
2343 23:34:56.282071 WL = 0x4
2344 23:34:56.282536 RL = 0x4
2345 23:34:56.285606 BL = 0x2
2346 23:34:56.286079 RPST = 0x0
2347 23:34:56.289132 RD_PRE = 0x0
2348 23:34:56.289719 WR_PRE = 0x1
2349 23:34:56.292373 WR_PST = 0x0
2350 23:34:56.292907 DBI_WR = 0x0
2351 23:34:56.295862 DBI_RD = 0x0
2352 23:34:56.296396 OTF = 0x1
2353 23:34:56.299040 ===================================
2354 23:34:56.305847 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2355 23:34:56.306387 ==
2356 23:34:56.309021 Dram Type= 6, Freq= 0, CH_0, rank 0
2357 23:34:56.311707 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2358 23:34:56.312134 ==
2359 23:34:56.315436 [Duty_Offset_Calibration]
2360 23:34:56.318900 B0:2 B1:1 CA:1
2361 23:34:56.319323
2362 23:34:56.322024 [DutyScan_Calibration_Flow] k_type=0
2363 23:34:56.329567
2364 23:34:56.330028 ==CLK 0==
2365 23:34:56.332867 Final CLK duty delay cell = 0
2366 23:34:56.337157 [0] MAX Duty = 5187%(X100), DQS PI = 24
2367 23:34:56.340028 [0] MIN Duty = 4875%(X100), DQS PI = 0
2368 23:34:56.340593 [0] AVG Duty = 5031%(X100)
2369 23:34:56.340948
2370 23:34:56.343149 CH0 CLK Duty spec in!! Max-Min= 312%
2371 23:34:56.349792 [DutyScan_Calibration_Flow] ====Done====
2372 23:34:56.350232
2373 23:34:56.352873 [DutyScan_Calibration_Flow] k_type=1
2374 23:34:56.368827
2375 23:34:56.369421 ==DQS 0 ==
2376 23:34:56.371653 Final DQS duty delay cell = -4
2377 23:34:56.375289 [-4] MAX Duty = 5124%(X100), DQS PI = 22
2378 23:34:56.378177 [-4] MIN Duty = 4782%(X100), DQS PI = 0
2379 23:34:56.381499 [-4] AVG Duty = 4953%(X100)
2380 23:34:56.381996
2381 23:34:56.382366 ==DQS 1 ==
2382 23:34:56.384755 Final DQS duty delay cell = 0
2383 23:34:56.388342 [0] MAX Duty = 5156%(X100), DQS PI = 0
2384 23:34:56.391709 [0] MIN Duty = 5031%(X100), DQS PI = 32
2385 23:34:56.395325 [0] AVG Duty = 5093%(X100)
2386 23:34:56.395786
2387 23:34:56.398325 CH0 DQS 0 Duty spec in!! Max-Min= 342%
2388 23:34:56.398797
2389 23:34:56.401961 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2390 23:34:56.405378 [DutyScan_Calibration_Flow] ====Done====
2391 23:34:56.405998
2392 23:34:56.408196 [DutyScan_Calibration_Flow] k_type=3
2393 23:34:56.425499
2394 23:34:56.426111 ==DQM 0 ==
2395 23:34:56.428536 Final DQM duty delay cell = 0
2396 23:34:56.432142 [0] MAX Duty = 5156%(X100), DQS PI = 30
2397 23:34:56.435454 [0] MIN Duty = 4906%(X100), DQS PI = 50
2398 23:34:56.435917 [0] AVG Duty = 5031%(X100)
2399 23:34:56.438839
2400 23:34:56.439401 ==DQM 1 ==
2401 23:34:56.442173 Final DQM duty delay cell = 0
2402 23:34:56.445539 [0] MAX Duty = 5093%(X100), DQS PI = 0
2403 23:34:56.448884 [0] MIN Duty = 5031%(X100), DQS PI = 16
2404 23:34:56.449448 [0] AVG Duty = 5062%(X100)
2405 23:34:56.449881
2406 23:34:56.456094 CH0 DQM 0 Duty spec in!! Max-Min= 250%
2407 23:34:56.456667
2408 23:34:56.459312 CH0 DQM 1 Duty spec in!! Max-Min= 62%
2409 23:34:56.462314 [DutyScan_Calibration_Flow] ====Done====
2410 23:34:56.463029
2411 23:34:56.465300 [DutyScan_Calibration_Flow] k_type=2
2412 23:34:56.481534
2413 23:34:56.482152 ==DQ 0 ==
2414 23:34:56.484891 Final DQ duty delay cell = 0
2415 23:34:56.488654 [0] MAX Duty = 5031%(X100), DQS PI = 26
2416 23:34:56.492127 [0] MIN Duty = 4875%(X100), DQS PI = 62
2417 23:34:56.492721 [0] AVG Duty = 4953%(X100)
2418 23:34:56.493097
2419 23:34:56.495256 ==DQ 1 ==
2420 23:34:56.498316 Final DQ duty delay cell = 0
2421 23:34:56.502010 [0] MAX Duty = 5093%(X100), DQS PI = 24
2422 23:34:56.505389 [0] MIN Duty = 4907%(X100), DQS PI = 36
2423 23:34:56.506020 [0] AVG Duty = 5000%(X100)
2424 23:34:56.506402
2425 23:34:56.508305 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2426 23:34:56.512359
2427 23:34:56.514944 CH0 DQ 1 Duty spec in!! Max-Min= 186%
2428 23:34:56.518017 [DutyScan_Calibration_Flow] ====Done====
2429 23:34:56.518485 ==
2430 23:34:56.521649 Dram Type= 6, Freq= 0, CH_1, rank 0
2431 23:34:56.525322 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2432 23:34:56.525958 ==
2433 23:34:56.528643 [Duty_Offset_Calibration]
2434 23:34:56.529206 B0:1 B1:0 CA:0
2435 23:34:56.529623
2436 23:34:56.531887 [DutyScan_Calibration_Flow] k_type=0
2437 23:34:56.541097
2438 23:34:56.541706 ==CLK 0==
2439 23:34:56.544505 Final CLK duty delay cell = -4
2440 23:34:56.548028 [-4] MAX Duty = 5000%(X100), DQS PI = 18
2441 23:34:56.550842 [-4] MIN Duty = 4875%(X100), DQS PI = 50
2442 23:34:56.554914 [-4] AVG Duty = 4937%(X100)
2443 23:34:56.555480
2444 23:34:56.557768 CH1 CLK Duty spec in!! Max-Min= 125%
2445 23:34:56.560954 [DutyScan_Calibration_Flow] ====Done====
2446 23:34:56.561530
2447 23:34:56.564450 [DutyScan_Calibration_Flow] k_type=1
2448 23:34:56.580725
2449 23:34:56.581288 ==DQS 0 ==
2450 23:34:56.584147 Final DQS duty delay cell = 0
2451 23:34:56.587450 [0] MAX Duty = 5094%(X100), DQS PI = 24
2452 23:34:56.590831 [0] MIN Duty = 4875%(X100), DQS PI = 0
2453 23:34:56.591400 [0] AVG Duty = 4984%(X100)
2454 23:34:56.591768
2455 23:34:56.594575 ==DQS 1 ==
2456 23:34:56.597557 Final DQS duty delay cell = 0
2457 23:34:56.600933 [0] MAX Duty = 5187%(X100), DQS PI = 18
2458 23:34:56.604212 [0] MIN Duty = 4938%(X100), DQS PI = 12
2459 23:34:56.604633 [0] AVG Duty = 5062%(X100)
2460 23:34:56.604996
2461 23:34:56.607789 CH1 DQS 0 Duty spec in!! Max-Min= 219%
2462 23:34:56.611184
2463 23:34:56.614770 CH1 DQS 1 Duty spec in!! Max-Min= 249%
2464 23:34:56.617396 [DutyScan_Calibration_Flow] ====Done====
2465 23:34:56.617915
2466 23:34:56.621022 [DutyScan_Calibration_Flow] k_type=3
2467 23:34:56.637806
2468 23:34:56.638494 ==DQM 0 ==
2469 23:34:56.641182 Final DQM duty delay cell = 0
2470 23:34:56.644160 [0] MAX Duty = 5156%(X100), DQS PI = 8
2471 23:34:56.647532 [0] MIN Duty = 5031%(X100), DQS PI = 0
2472 23:34:56.648113 [0] AVG Duty = 5093%(X100)
2473 23:34:56.650185
2474 23:34:56.650649 ==DQM 1 ==
2475 23:34:56.653653 Final DQM duty delay cell = 0
2476 23:34:56.657213 [0] MAX Duty = 5031%(X100), DQS PI = 16
2477 23:34:56.660735 [0] MIN Duty = 4907%(X100), DQS PI = 34
2478 23:34:56.663745 [0] AVG Duty = 4969%(X100)
2479 23:34:56.664327
2480 23:34:56.667499 CH1 DQM 0 Duty spec in!! Max-Min= 125%
2481 23:34:56.668069
2482 23:34:56.670506 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2483 23:34:56.673787 [DutyScan_Calibration_Flow] ====Done====
2484 23:34:56.674377
2485 23:34:56.677203 [DutyScan_Calibration_Flow] k_type=2
2486 23:34:56.693137
2487 23:34:56.693778 ==DQ 0 ==
2488 23:34:56.696401 Final DQ duty delay cell = -4
2489 23:34:56.699999 [-4] MAX Duty = 5094%(X100), DQS PI = 10
2490 23:34:56.703174 [-4] MIN Duty = 4906%(X100), DQS PI = 46
2491 23:34:56.706543 [-4] AVG Duty = 5000%(X100)
2492 23:34:56.707009
2493 23:34:56.707379 ==DQ 1 ==
2494 23:34:56.709453 Final DQ duty delay cell = 0
2495 23:34:56.712840 [0] MAX Duty = 5125%(X100), DQS PI = 20
2496 23:34:56.716354 [0] MIN Duty = 4969%(X100), DQS PI = 12
2497 23:34:56.716917 [0] AVG Duty = 5047%(X100)
2498 23:34:56.719933
2499 23:34:56.722944 CH1 DQ 0 Duty spec in!! Max-Min= 188%
2500 23:34:56.723417
2501 23:34:56.726851 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2502 23:34:56.730498 [DutyScan_Calibration_Flow] ====Done====
2503 23:34:56.733922 nWR fixed to 30
2504 23:34:56.734494 [ModeRegInit_LP4] CH0 RK0
2505 23:34:56.736375 [ModeRegInit_LP4] CH0 RK1
2506 23:34:56.739721 [ModeRegInit_LP4] CH1 RK0
2507 23:34:56.743272 [ModeRegInit_LP4] CH1 RK1
2508 23:34:56.743841 match AC timing 7
2509 23:34:56.746363 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2510 23:34:56.753222 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2511 23:34:56.756368 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2512 23:34:56.763016 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2513 23:34:56.766432 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2514 23:34:56.766899 ==
2515 23:34:56.769810 Dram Type= 6, Freq= 0, CH_0, rank 0
2516 23:34:56.773346 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2517 23:34:56.774068 ==
2518 23:34:56.779659 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2519 23:34:56.785782 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2520 23:34:56.793968 [CA 0] Center 39 (8~70) winsize 63
2521 23:34:56.796603 [CA 1] Center 39 (8~70) winsize 63
2522 23:34:56.800891 [CA 2] Center 35 (5~66) winsize 62
2523 23:34:56.803583 [CA 3] Center 34 (4~65) winsize 62
2524 23:34:56.806593 [CA 4] Center 33 (3~64) winsize 62
2525 23:34:56.810173 [CA 5] Center 32 (3~62) winsize 60
2526 23:34:56.810745
2527 23:34:56.813022 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2528 23:34:56.813488
2529 23:34:56.816263 [CATrainingPosCal] consider 1 rank data
2530 23:34:56.819984 u2DelayCellTimex100 = 270/100 ps
2531 23:34:56.823623 CA0 delay=39 (8~70),Diff = 7 PI (33 cell)
2532 23:34:56.826637 CA1 delay=39 (8~70),Diff = 7 PI (33 cell)
2533 23:34:56.833420 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2534 23:34:56.836307 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2535 23:34:56.840134 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2536 23:34:56.843401 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2537 23:34:56.843985
2538 23:34:56.846835 CA PerBit enable=1, Macro0, CA PI delay=32
2539 23:34:56.847402
2540 23:34:56.849997 [CBTSetCACLKResult] CA Dly = 32
2541 23:34:56.850463 CS Dly: 6 (0~37)
2542 23:34:56.853467 ==
2543 23:34:56.853988 Dram Type= 6, Freq= 0, CH_0, rank 1
2544 23:34:56.859717 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2545 23:34:56.860281 ==
2546 23:34:56.863346 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2547 23:34:56.869856 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2548 23:34:56.879989 [CA 0] Center 38 (8~69) winsize 62
2549 23:34:56.882128 [CA 1] Center 38 (8~69) winsize 62
2550 23:34:56.885839 [CA 2] Center 35 (4~66) winsize 63
2551 23:34:56.889029 [CA 3] Center 34 (4~65) winsize 62
2552 23:34:56.892264 [CA 4] Center 33 (3~64) winsize 62
2553 23:34:56.895725 [CA 5] Center 32 (3~62) winsize 60
2554 23:34:56.896314
2555 23:34:56.898946 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2556 23:34:56.899415
2557 23:34:56.902213 [CATrainingPosCal] consider 2 rank data
2558 23:34:56.906055 u2DelayCellTimex100 = 270/100 ps
2559 23:34:56.909113 CA0 delay=38 (8~69),Diff = 6 PI (28 cell)
2560 23:34:56.912596 CA1 delay=38 (8~69),Diff = 6 PI (28 cell)
2561 23:34:56.919308 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2562 23:34:56.922190 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2563 23:34:56.925798 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2564 23:34:56.928736 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2565 23:34:56.929205
2566 23:34:56.932731 CA PerBit enable=1, Macro0, CA PI delay=32
2567 23:34:56.933307
2568 23:34:56.936150 [CBTSetCACLKResult] CA Dly = 32
2569 23:34:56.936729 CS Dly: 6 (0~38)
2570 23:34:56.937109
2571 23:34:56.939317 ----->DramcWriteLeveling(PI) begin...
2572 23:34:56.942513 ==
2573 23:34:56.945829 Dram Type= 6, Freq= 0, CH_0, rank 0
2574 23:34:56.949345 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2575 23:34:56.949985 ==
2576 23:34:56.952948 Write leveling (Byte 0): 33 => 33
2577 23:34:56.955879 Write leveling (Byte 1): 29 => 29
2578 23:34:56.959176 DramcWriteLeveling(PI) end<-----
2579 23:34:56.959642
2580 23:34:56.960015 ==
2581 23:34:56.962970 Dram Type= 6, Freq= 0, CH_0, rank 0
2582 23:34:56.965556 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2583 23:34:56.966100 ==
2584 23:34:56.969027 [Gating] SW mode calibration
2585 23:34:56.976125 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2586 23:34:56.979353 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2587 23:34:56.985565 0 15 0 | B1->B0 | 2323 3231 | 0 1 | (0 0) (1 1)
2588 23:34:56.988764 0 15 4 | B1->B0 | 3232 3434 | 1 1 | (0 0) (1 1)
2589 23:34:56.993061 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2590 23:34:56.998886 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2591 23:34:57.002325 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2592 23:34:57.005318 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2593 23:34:57.012219 0 15 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
2594 23:34:57.015313 0 15 28 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
2595 23:34:57.019357 1 0 0 | B1->B0 | 2929 2323 | 1 0 | (0 1) (0 0)
2596 23:34:57.025852 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2597 23:34:57.028750 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2598 23:34:57.032638 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2599 23:34:57.038985 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2600 23:34:57.042068 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2601 23:34:57.046232 1 0 24 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
2602 23:34:57.052497 1 0 28 | B1->B0 | 2828 4444 | 0 0 | (0 0) (0 0)
2603 23:34:57.055915 1 1 0 | B1->B0 | 3333 4646 | 0 0 | (0 0) (0 0)
2604 23:34:57.058976 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2605 23:34:57.062596 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2606 23:34:57.069239 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2607 23:34:57.071950 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2608 23:34:57.075485 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2609 23:34:57.082359 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2610 23:34:57.085534 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2611 23:34:57.088820 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2612 23:34:57.095860 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2613 23:34:57.098990 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2614 23:34:57.102355 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2615 23:34:57.108914 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2616 23:34:57.112066 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2617 23:34:57.115354 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2618 23:34:57.122213 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2619 23:34:57.125349 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2620 23:34:57.128704 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2621 23:34:57.135564 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2622 23:34:57.138890 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2623 23:34:57.142291 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2624 23:34:57.149663 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2625 23:34:57.152881 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2626 23:34:57.155779 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2627 23:34:57.162214 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2628 23:34:57.162684 Total UI for P1: 0, mck2ui 16
2629 23:34:57.165779 best dqsien dly found for B0: ( 1, 3, 28)
2630 23:34:57.172257 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2631 23:34:57.175696 Total UI for P1: 0, mck2ui 16
2632 23:34:57.179016 best dqsien dly found for B1: ( 1, 3, 30)
2633 23:34:57.183016 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2634 23:34:57.185510 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2635 23:34:57.186011
2636 23:34:57.189253 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2637 23:34:57.192924 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2638 23:34:57.196133 [Gating] SW calibration Done
2639 23:34:57.196697 ==
2640 23:34:57.199201 Dram Type= 6, Freq= 0, CH_0, rank 0
2641 23:34:57.202445 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2642 23:34:57.202917 ==
2643 23:34:57.206095 RX Vref Scan: 0
2644 23:34:57.206660
2645 23:34:57.207040 RX Vref 0 -> 0, step: 1
2646 23:34:57.207394
2647 23:34:57.209449 RX Delay -40 -> 252, step: 8
2648 23:34:57.213067 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2649 23:34:57.219325 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2650 23:34:57.222588 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2651 23:34:57.225736 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2652 23:34:57.229807 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2653 23:34:57.232931 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2654 23:34:57.239190 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2655 23:34:57.242467 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2656 23:34:57.245862 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
2657 23:34:57.249464 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
2658 23:34:57.252568 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2659 23:34:57.258789 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2660 23:34:57.262909 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2661 23:34:57.266238 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2662 23:34:57.269122 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2663 23:34:57.275687 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2664 23:34:57.276174 ==
2665 23:34:57.278899 Dram Type= 6, Freq= 0, CH_0, rank 0
2666 23:34:57.282581 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2667 23:34:57.283178 ==
2668 23:34:57.283680 DQS Delay:
2669 23:34:57.285772 DQS0 = 0, DQS1 = 0
2670 23:34:57.286273 DQM Delay:
2671 23:34:57.288701 DQM0 = 121, DQM1 = 113
2672 23:34:57.289183 DQ Delay:
2673 23:34:57.292686 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2674 23:34:57.295578 DQ4 =123, DQ5 =115, DQ6 =127, DQ7 =127
2675 23:34:57.299472 DQ8 =103, DQ9 =107, DQ10 =111, DQ11 =107
2676 23:34:57.302504 DQ12 =115, DQ13 =123, DQ14 =123, DQ15 =119
2677 23:34:57.302986
2678 23:34:57.303471
2679 23:34:57.303931 ==
2680 23:34:57.305825 Dram Type= 6, Freq= 0, CH_0, rank 0
2681 23:34:57.312350 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2682 23:34:57.312939 ==
2683 23:34:57.313449
2684 23:34:57.313959
2685 23:34:57.314416 TX Vref Scan disable
2686 23:34:57.315896 == TX Byte 0 ==
2687 23:34:57.319137 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2688 23:34:57.326363 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2689 23:34:57.326933 == TX Byte 1 ==
2690 23:34:57.329394 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2691 23:34:57.336235 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2692 23:34:57.336816 ==
2693 23:34:57.339081 Dram Type= 6, Freq= 0, CH_0, rank 0
2694 23:34:57.342735 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2695 23:34:57.343318 ==
2696 23:34:57.354299 TX Vref=22, minBit 0, minWin=25, winSum=404
2697 23:34:57.357437 TX Vref=24, minBit 0, minWin=25, winSum=408
2698 23:34:57.361132 TX Vref=26, minBit 3, minWin=25, winSum=415
2699 23:34:57.364508 TX Vref=28, minBit 13, minWin=25, winSum=419
2700 23:34:57.367353 TX Vref=30, minBit 10, minWin=25, winSum=423
2701 23:34:57.373951 TX Vref=32, minBit 10, minWin=25, winSum=420
2702 23:34:57.377302 [TxChooseVref] Worse bit 10, Min win 25, Win sum 423, Final Vref 30
2703 23:34:57.377942
2704 23:34:57.380704 Final TX Range 1 Vref 30
2705 23:34:57.381283
2706 23:34:57.381902 ==
2707 23:34:57.384209 Dram Type= 6, Freq= 0, CH_0, rank 0
2708 23:34:57.387373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2709 23:34:57.391067 ==
2710 23:34:57.391630
2711 23:34:57.392009
2712 23:34:57.392358 TX Vref Scan disable
2713 23:34:57.394146 == TX Byte 0 ==
2714 23:34:57.397665 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2715 23:34:57.400720 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2716 23:34:57.404436 == TX Byte 1 ==
2717 23:34:57.407660 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2718 23:34:57.411019 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2719 23:34:57.414281
2720 23:34:57.414745 [DATLAT]
2721 23:34:57.415126 Freq=1200, CH0 RK0
2722 23:34:57.415476
2723 23:34:57.417535 DATLAT Default: 0xd
2724 23:34:57.418037 0, 0xFFFF, sum = 0
2725 23:34:57.421222 1, 0xFFFF, sum = 0
2726 23:34:57.421769 2, 0xFFFF, sum = 0
2727 23:34:57.424434 3, 0xFFFF, sum = 0
2728 23:34:57.424904 4, 0xFFFF, sum = 0
2729 23:34:57.427415 5, 0xFFFF, sum = 0
2730 23:34:57.431218 6, 0xFFFF, sum = 0
2731 23:34:57.431803 7, 0xFFFF, sum = 0
2732 23:34:57.434155 8, 0xFFFF, sum = 0
2733 23:34:57.434734 9, 0xFFFF, sum = 0
2734 23:34:57.437694 10, 0xFFFF, sum = 0
2735 23:34:57.438279 11, 0xFFFF, sum = 0
2736 23:34:57.441058 12, 0x0, sum = 1
2737 23:34:57.441533 13, 0x0, sum = 2
2738 23:34:57.444086 14, 0x0, sum = 3
2739 23:34:57.444560 15, 0x0, sum = 4
2740 23:34:57.444942 best_step = 13
2741 23:34:57.447443
2742 23:34:57.447909 ==
2743 23:34:57.450837 Dram Type= 6, Freq= 0, CH_0, rank 0
2744 23:34:57.454196 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2745 23:34:57.454787 ==
2746 23:34:57.455169 RX Vref Scan: 1
2747 23:34:57.455528
2748 23:34:57.457731 Set Vref Range= 32 -> 127
2749 23:34:57.458203
2750 23:34:57.460856 RX Vref 32 -> 127, step: 1
2751 23:34:57.461325
2752 23:34:57.464404 RX Delay -5 -> 252, step: 4
2753 23:34:57.464871
2754 23:34:57.467358 Set Vref, RX VrefLevel [Byte0]: 32
2755 23:34:57.470856 [Byte1]: 32
2756 23:34:57.471375
2757 23:34:57.474121 Set Vref, RX VrefLevel [Byte0]: 33
2758 23:34:57.477528 [Byte1]: 33
2759 23:34:57.478132
2760 23:34:57.480978 Set Vref, RX VrefLevel [Byte0]: 34
2761 23:34:57.484223 [Byte1]: 34
2762 23:34:57.488401
2763 23:34:57.488825 Set Vref, RX VrefLevel [Byte0]: 35
2764 23:34:57.491738 [Byte1]: 35
2765 23:34:57.496753
2766 23:34:57.497287 Set Vref, RX VrefLevel [Byte0]: 36
2767 23:34:57.499289 [Byte1]: 36
2768 23:34:57.504056
2769 23:34:57.504583 Set Vref, RX VrefLevel [Byte0]: 37
2770 23:34:57.507389 [Byte1]: 37
2771 23:34:57.511628
2772 23:34:57.512163 Set Vref, RX VrefLevel [Byte0]: 38
2773 23:34:57.515542 [Byte1]: 38
2774 23:34:57.519824
2775 23:34:57.520359 Set Vref, RX VrefLevel [Byte0]: 39
2776 23:34:57.523126 [Byte1]: 39
2777 23:34:57.528289
2778 23:34:57.528818 Set Vref, RX VrefLevel [Byte0]: 40
2779 23:34:57.530728 [Byte1]: 40
2780 23:34:57.536295
2781 23:34:57.536841 Set Vref, RX VrefLevel [Byte0]: 41
2782 23:34:57.538829 [Byte1]: 41
2783 23:34:57.543002
2784 23:34:57.543434 Set Vref, RX VrefLevel [Byte0]: 42
2785 23:34:57.546867 [Byte1]: 42
2786 23:34:57.551237
2787 23:34:57.551779 Set Vref, RX VrefLevel [Byte0]: 43
2788 23:34:57.554538 [Byte1]: 43
2789 23:34:57.558820
2790 23:34:57.559368 Set Vref, RX VrefLevel [Byte0]: 44
2791 23:34:57.562077 [Byte1]: 44
2792 23:34:57.566965
2793 23:34:57.567491 Set Vref, RX VrefLevel [Byte0]: 45
2794 23:34:57.569908 [Byte1]: 45
2795 23:34:57.575110
2796 23:34:57.575647 Set Vref, RX VrefLevel [Byte0]: 46
2797 23:34:57.577905 [Byte1]: 46
2798 23:34:57.582371
2799 23:34:57.582899 Set Vref, RX VrefLevel [Byte0]: 47
2800 23:34:57.585722 [Byte1]: 47
2801 23:34:57.590514
2802 23:34:57.591050 Set Vref, RX VrefLevel [Byte0]: 48
2803 23:34:57.593681 [Byte1]: 48
2804 23:34:57.598185
2805 23:34:57.598720 Set Vref, RX VrefLevel [Byte0]: 49
2806 23:34:57.602205 [Byte1]: 49
2807 23:34:57.606147
2808 23:34:57.606674 Set Vref, RX VrefLevel [Byte0]: 50
2809 23:34:57.609174 [Byte1]: 50
2810 23:34:57.613834
2811 23:34:57.614376 Set Vref, RX VrefLevel [Byte0]: 51
2812 23:34:57.617292 [Byte1]: 51
2813 23:34:57.621648
2814 23:34:57.622169 Set Vref, RX VrefLevel [Byte0]: 52
2815 23:34:57.625397 [Byte1]: 52
2816 23:34:57.629640
2817 23:34:57.630086 Set Vref, RX VrefLevel [Byte0]: 53
2818 23:34:57.633056 [Byte1]: 53
2819 23:34:57.637483
2820 23:34:57.638056 Set Vref, RX VrefLevel [Byte0]: 54
2821 23:34:57.640450 [Byte1]: 54
2822 23:34:57.645481
2823 23:34:57.646061 Set Vref, RX VrefLevel [Byte0]: 55
2824 23:34:57.648590 [Byte1]: 55
2825 23:34:57.653407
2826 23:34:57.654004 Set Vref, RX VrefLevel [Byte0]: 56
2827 23:34:57.656454 [Byte1]: 56
2828 23:34:57.661332
2829 23:34:57.661934 Set Vref, RX VrefLevel [Byte0]: 57
2830 23:34:57.664529 [Byte1]: 57
2831 23:34:57.668895
2832 23:34:57.669529 Set Vref, RX VrefLevel [Byte0]: 58
2833 23:34:57.671748 [Byte1]: 58
2834 23:34:57.676501
2835 23:34:57.676925 Set Vref, RX VrefLevel [Byte0]: 59
2836 23:34:57.680230 [Byte1]: 59
2837 23:34:57.684852
2838 23:34:57.685383 Set Vref, RX VrefLevel [Byte0]: 60
2839 23:34:57.687799 [Byte1]: 60
2840 23:34:57.692144
2841 23:34:57.692597 Set Vref, RX VrefLevel [Byte0]: 61
2842 23:34:57.695574 [Byte1]: 61
2843 23:34:57.700348
2844 23:34:57.700897 Set Vref, RX VrefLevel [Byte0]: 62
2845 23:34:57.704057 [Byte1]: 62
2846 23:34:57.708126
2847 23:34:57.708659 Set Vref, RX VrefLevel [Byte0]: 63
2848 23:34:57.711579 [Byte1]: 63
2849 23:34:57.716122
2850 23:34:57.716668 Set Vref, RX VrefLevel [Byte0]: 64
2851 23:34:57.719242 [Byte1]: 64
2852 23:34:57.723612
2853 23:34:57.724035 Set Vref, RX VrefLevel [Byte0]: 65
2854 23:34:57.727476 [Byte1]: 65
2855 23:34:57.732042
2856 23:34:57.732571 Set Vref, RX VrefLevel [Byte0]: 66
2857 23:34:57.735180 [Byte1]: 66
2858 23:34:57.739686
2859 23:34:57.740215 Set Vref, RX VrefLevel [Byte0]: 67
2860 23:34:57.742732 [Byte1]: 67
2861 23:34:57.747974
2862 23:34:57.748534 Set Vref, RX VrefLevel [Byte0]: 68
2863 23:34:57.750629 [Byte1]: 68
2864 23:34:57.755065
2865 23:34:57.755652 Set Vref, RX VrefLevel [Byte0]: 69
2866 23:34:57.758787 [Byte1]: 69
2867 23:34:57.763007
2868 23:34:57.763583 Set Vref, RX VrefLevel [Byte0]: 70
2869 23:34:57.766504 [Byte1]: 70
2870 23:34:57.770703
2871 23:34:57.771277 Set Vref, RX VrefLevel [Byte0]: 71
2872 23:34:57.774143 [Byte1]: 71
2873 23:34:57.779158
2874 23:34:57.779740 Final RX Vref Byte 0 = 53 to rank0
2875 23:34:57.782074 Final RX Vref Byte 1 = 55 to rank0
2876 23:34:57.785438 Final RX Vref Byte 0 = 53 to rank1
2877 23:34:57.788836 Final RX Vref Byte 1 = 55 to rank1==
2878 23:34:57.792184 Dram Type= 6, Freq= 0, CH_0, rank 0
2879 23:34:57.798701 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2880 23:34:57.799281 ==
2881 23:34:57.799667 DQS Delay:
2882 23:34:57.800020 DQS0 = 0, DQS1 = 0
2883 23:34:57.801901 DQM Delay:
2884 23:34:57.802364 DQM0 = 120, DQM1 = 112
2885 23:34:57.805624 DQ Delay:
2886 23:34:57.809060 DQ0 =120, DQ1 =122, DQ2 =118, DQ3 =118
2887 23:34:57.812185 DQ4 =122, DQ5 =112, DQ6 =126, DQ7 =128
2888 23:34:57.815696 DQ8 =100, DQ9 =102, DQ10 =114, DQ11 =106
2889 23:34:57.818585 DQ12 =118, DQ13 =118, DQ14 =124, DQ15 =120
2890 23:34:57.819092
2891 23:34:57.819479
2892 23:34:57.825379 [DQSOSCAuto] RK0, (LSB)MR18= 0x140d, (MSB)MR19= 0x404, tDQSOscB0 = 405 ps tDQSOscB1 = 402 ps
2893 23:34:57.828977 CH0 RK0: MR19=404, MR18=140D
2894 23:34:57.835990 CH0_RK0: MR19=0x404, MR18=0x140D, DQSOSC=402, MR23=63, INC=40, DEC=27
2895 23:34:57.836559
2896 23:34:57.839209 ----->DramcWriteLeveling(PI) begin...
2897 23:34:57.839784 ==
2898 23:34:57.842470 Dram Type= 6, Freq= 0, CH_0, rank 1
2899 23:34:57.845821 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2900 23:34:57.849477 ==
2901 23:34:57.850124 Write leveling (Byte 0): 36 => 36
2902 23:34:57.852188 Write leveling (Byte 1): 29 => 29
2903 23:34:57.855760 DramcWriteLeveling(PI) end<-----
2904 23:34:57.856225
2905 23:34:57.856598 ==
2906 23:34:57.858691 Dram Type= 6, Freq= 0, CH_0, rank 1
2907 23:34:57.866040 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2908 23:34:57.866612 ==
2909 23:34:57.866986 [Gating] SW mode calibration
2910 23:34:57.875458 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2911 23:34:57.878859 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2912 23:34:57.882080 0 15 0 | B1->B0 | 3333 3232 | 1 0 | (1 1) (0 0)
2913 23:34:57.888725 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2914 23:34:57.892229 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2915 23:34:57.895694 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2916 23:34:57.901973 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2917 23:34:57.905643 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2918 23:34:57.908719 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2919 23:34:57.915232 0 15 28 | B1->B0 | 3131 3030 | 1 1 | (0 1) (0 0)
2920 23:34:57.918822 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2921 23:34:57.921909 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2922 23:34:57.929323 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2923 23:34:57.932546 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2924 23:34:57.935713 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2925 23:34:57.942216 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2926 23:34:57.945803 1 0 24 | B1->B0 | 2727 2424 | 0 1 | (0 0) (0 0)
2927 23:34:57.949226 1 0 28 | B1->B0 | 403f 4040 | 1 0 | (0 0) (0 0)
2928 23:34:57.955412 1 1 0 | B1->B0 | 4646 4545 | 0 1 | (0 0) (0 0)
2929 23:34:57.959088 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2930 23:34:57.961752 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2931 23:34:57.968936 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2932 23:34:57.971679 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2933 23:34:57.975419 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2934 23:34:57.981818 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
2935 23:34:57.985240 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2936 23:34:57.988585 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2937 23:34:57.992394 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2938 23:34:57.998516 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2939 23:34:58.002306 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2940 23:34:58.005571 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2941 23:34:58.011938 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2942 23:34:58.015476 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2943 23:34:58.018453 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2944 23:34:58.025223 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2945 23:34:58.028794 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2946 23:34:58.031988 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2947 23:34:58.038461 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2948 23:34:58.042008 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2949 23:34:58.045636 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2950 23:34:58.051976 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2951 23:34:58.055520 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2952 23:34:58.058501 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2953 23:34:58.061819 Total UI for P1: 0, mck2ui 16
2954 23:34:58.065023 best dqsien dly found for B0: ( 1, 3, 28)
2955 23:34:58.068391 Total UI for P1: 0, mck2ui 16
2956 23:34:58.072038 best dqsien dly found for B1: ( 1, 3, 28)
2957 23:34:58.075171 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2958 23:34:58.078612 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2959 23:34:58.079036
2960 23:34:58.082003 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2961 23:34:58.088918 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2962 23:34:58.089490 [Gating] SW calibration Done
2963 23:34:58.089940 ==
2964 23:34:58.092694 Dram Type= 6, Freq= 0, CH_0, rank 1
2965 23:34:58.098949 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2966 23:34:58.099524 ==
2967 23:34:58.099909 RX Vref Scan: 0
2968 23:34:58.100264
2969 23:34:58.101925 RX Vref 0 -> 0, step: 1
2970 23:34:58.102396
2971 23:34:58.105778 RX Delay -40 -> 252, step: 8
2972 23:34:58.109182 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2973 23:34:58.112318 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2974 23:34:58.115584 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2975 23:34:58.119302 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2976 23:34:58.125534 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2977 23:34:58.129281 iDelay=200, Bit 5, Center 119 (48 ~ 191) 144
2978 23:34:58.132274 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2979 23:34:58.135769 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2980 23:34:58.139066 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2981 23:34:58.145752 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
2982 23:34:58.149006 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
2983 23:34:58.152376 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2984 23:34:58.155750 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2985 23:34:58.158698 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2986 23:34:58.165893 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2987 23:34:58.168609 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
2988 23:34:58.169096 ==
2989 23:34:58.172270 Dram Type= 6, Freq= 0, CH_0, rank 1
2990 23:34:58.175811 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2991 23:34:58.176288 ==
2992 23:34:58.179105 DQS Delay:
2993 23:34:58.179721 DQS0 = 0, DQS1 = 0
2994 23:34:58.180198 DQM Delay:
2995 23:34:58.182466 DQM0 = 122, DQM1 = 113
2996 23:34:58.182933 DQ Delay:
2997 23:34:58.185885 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =119
2998 23:34:58.189023 DQ4 =127, DQ5 =119, DQ6 =127, DQ7 =127
2999 23:34:58.192437 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3000 23:34:58.195912 DQ12 =115, DQ13 =123, DQ14 =123, DQ15 =123
3001 23:34:58.199163
3002 23:34:58.199753
3003 23:34:58.200127 ==
3004 23:34:58.202466 Dram Type= 6, Freq= 0, CH_0, rank 1
3005 23:34:58.205991 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3006 23:34:58.206567 ==
3007 23:34:58.206950
3008 23:34:58.207296
3009 23:34:58.209399 TX Vref Scan disable
3010 23:34:58.210028 == TX Byte 0 ==
3011 23:34:58.215808 Update DQ dly =855 (3 ,2, 23) DQ OEN =(2 ,7)
3012 23:34:58.219221 Update DQM dly =855 (3 ,2, 23) DQM OEN =(2 ,7)
3013 23:34:58.219799 == TX Byte 1 ==
3014 23:34:58.225999 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3015 23:34:58.229685 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3016 23:34:58.230280 ==
3017 23:34:58.232535 Dram Type= 6, Freq= 0, CH_0, rank 1
3018 23:34:58.235921 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3019 23:34:58.236488 ==
3020 23:34:58.249143 TX Vref=22, minBit 5, minWin=24, winSum=418
3021 23:34:58.252180 TX Vref=24, minBit 13, minWin=25, winSum=422
3022 23:34:58.255481 TX Vref=26, minBit 0, minWin=26, winSum=425
3023 23:34:58.259030 TX Vref=28, minBit 5, minWin=25, winSum=430
3024 23:34:58.261901 TX Vref=30, minBit 1, minWin=26, winSum=428
3025 23:34:58.268746 TX Vref=32, minBit 5, minWin=25, winSum=427
3026 23:34:58.272329 [TxChooseVref] Worse bit 1, Min win 26, Win sum 428, Final Vref 30
3027 23:34:58.273028
3028 23:34:58.275054 Final TX Range 1 Vref 30
3029 23:34:58.275721
3030 23:34:58.276169 ==
3031 23:34:58.278368 Dram Type= 6, Freq= 0, CH_0, rank 1
3032 23:34:58.282200 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3033 23:34:58.282824 ==
3034 23:34:58.285022
3035 23:34:58.285490
3036 23:34:58.285944 TX Vref Scan disable
3037 23:34:58.288517 == TX Byte 0 ==
3038 23:34:58.292139 Update DQ dly =855 (3 ,2, 23) DQ OEN =(2 ,7)
3039 23:34:58.295040 Update DQM dly =855 (3 ,2, 23) DQM OEN =(2 ,7)
3040 23:34:58.298639 == TX Byte 1 ==
3041 23:34:58.302223 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3042 23:34:58.305482 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3043 23:34:58.308873
3044 23:34:58.309333 [DATLAT]
3045 23:34:58.309750 Freq=1200, CH0 RK1
3046 23:34:58.310113
3047 23:34:58.311763 DATLAT Default: 0xd
3048 23:34:58.312229 0, 0xFFFF, sum = 0
3049 23:34:58.315242 1, 0xFFFF, sum = 0
3050 23:34:58.315672 2, 0xFFFF, sum = 0
3051 23:34:58.318474 3, 0xFFFF, sum = 0
3052 23:34:58.318905 4, 0xFFFF, sum = 0
3053 23:34:58.322130 5, 0xFFFF, sum = 0
3054 23:34:58.325327 6, 0xFFFF, sum = 0
3055 23:34:58.325845 7, 0xFFFF, sum = 0
3056 23:34:58.328804 8, 0xFFFF, sum = 0
3057 23:34:58.329343 9, 0xFFFF, sum = 0
3058 23:34:58.331734 10, 0xFFFF, sum = 0
3059 23:34:58.332169 11, 0xFFFF, sum = 0
3060 23:34:58.335267 12, 0x0, sum = 1
3061 23:34:58.335809 13, 0x0, sum = 2
3062 23:34:58.338883 14, 0x0, sum = 3
3063 23:34:58.339427 15, 0x0, sum = 4
3064 23:34:58.339780 best_step = 13
3065 23:34:58.340104
3066 23:34:58.342580 ==
3067 23:34:58.345228 Dram Type= 6, Freq= 0, CH_0, rank 1
3068 23:34:58.348814 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3069 23:34:58.349351 ==
3070 23:34:58.349735 RX Vref Scan: 0
3071 23:34:58.350063
3072 23:34:58.352776 RX Vref 0 -> 0, step: 1
3073 23:34:58.353308
3074 23:34:58.355747 RX Delay -13 -> 252, step: 4
3075 23:34:58.359076 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3076 23:34:58.361936 iDelay=195, Bit 1, Center 122 (55 ~ 190) 136
3077 23:34:58.369053 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3078 23:34:58.372355 iDelay=195, Bit 3, Center 118 (51 ~ 186) 136
3079 23:34:58.375537 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3080 23:34:58.378905 iDelay=195, Bit 5, Center 116 (51 ~ 182) 132
3081 23:34:58.382080 iDelay=195, Bit 6, Center 126 (63 ~ 190) 128
3082 23:34:58.388640 iDelay=195, Bit 7, Center 128 (63 ~ 194) 132
3083 23:34:58.391958 iDelay=195, Bit 8, Center 102 (35 ~ 170) 136
3084 23:34:58.395078 iDelay=195, Bit 9, Center 100 (35 ~ 166) 132
3085 23:34:58.398417 iDelay=195, Bit 10, Center 112 (47 ~ 178) 132
3086 23:34:58.401836 iDelay=195, Bit 11, Center 104 (39 ~ 170) 132
3087 23:34:58.408987 iDelay=195, Bit 12, Center 118 (55 ~ 182) 128
3088 23:34:58.412091 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3089 23:34:58.415254 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3090 23:34:58.418916 iDelay=195, Bit 15, Center 118 (55 ~ 182) 128
3091 23:34:58.419451 ==
3092 23:34:58.421972 Dram Type= 6, Freq= 0, CH_0, rank 1
3093 23:34:58.428986 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3094 23:34:58.429526 ==
3095 23:34:58.429933 DQS Delay:
3096 23:34:58.432019 DQS0 = 0, DQS1 = 0
3097 23:34:58.432446 DQM Delay:
3098 23:34:58.432786 DQM0 = 121, DQM1 = 111
3099 23:34:58.435339 DQ Delay:
3100 23:34:58.438804 DQ0 =118, DQ1 =122, DQ2 =118, DQ3 =118
3101 23:34:58.442360 DQ4 =122, DQ5 =116, DQ6 =126, DQ7 =128
3102 23:34:58.445362 DQ8 =102, DQ9 =100, DQ10 =112, DQ11 =104
3103 23:34:58.448929 DQ12 =118, DQ13 =118, DQ14 =122, DQ15 =118
3104 23:34:58.449489
3105 23:34:58.449879
3106 23:34:58.455813 [DQSOSCAuto] RK1, (LSB)MR18= 0xeef, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 404 ps
3107 23:34:58.459039 CH0 RK1: MR19=403, MR18=EEF
3108 23:34:58.466160 CH0_RK1: MR19=0x403, MR18=0xEEF, DQSOSC=404, MR23=63, INC=40, DEC=26
3109 23:34:58.468841 [RxdqsGatingPostProcess] freq 1200
3110 23:34:58.476170 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3111 23:34:58.478987 best DQS0 dly(2T, 0.5T) = (0, 11)
3112 23:34:58.479525 best DQS1 dly(2T, 0.5T) = (0, 11)
3113 23:34:58.482373 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3114 23:34:58.485626 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3115 23:34:58.489443 best DQS0 dly(2T, 0.5T) = (0, 11)
3116 23:34:58.492340 best DQS1 dly(2T, 0.5T) = (0, 11)
3117 23:34:58.495668 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3118 23:34:58.498803 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3119 23:34:58.502889 Pre-setting of DQS Precalculation
3120 23:34:58.508823 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3121 23:34:58.509354 ==
3122 23:34:58.512717 Dram Type= 6, Freq= 0, CH_1, rank 0
3123 23:34:58.515942 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3124 23:34:58.516480 ==
3125 23:34:58.522518 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3126 23:34:58.525972 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3127 23:34:58.535605 [CA 0] Center 37 (7~68) winsize 62
3128 23:34:58.538304 [CA 1] Center 37 (7~68) winsize 62
3129 23:34:58.542060 [CA 2] Center 35 (5~65) winsize 61
3130 23:34:58.545413 [CA 3] Center 34 (4~64) winsize 61
3131 23:34:58.548825 [CA 4] Center 34 (4~64) winsize 61
3132 23:34:58.551785 [CA 5] Center 33 (3~63) winsize 61
3133 23:34:58.552318
3134 23:34:58.555618 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3135 23:34:58.556154
3136 23:34:58.558787 [CATrainingPosCal] consider 1 rank data
3137 23:34:58.561972 u2DelayCellTimex100 = 270/100 ps
3138 23:34:58.565313 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3139 23:34:58.568565 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3140 23:34:58.574852 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3141 23:34:58.578290 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3142 23:34:58.581755 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3143 23:34:58.585033 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3144 23:34:58.585559
3145 23:34:58.588644 CA PerBit enable=1, Macro0, CA PI delay=33
3146 23:34:58.589106
3147 23:34:58.591767 [CBTSetCACLKResult] CA Dly = 33
3148 23:34:58.592226 CS Dly: 8 (0~39)
3149 23:34:58.592595 ==
3150 23:34:58.595541 Dram Type= 6, Freq= 0, CH_1, rank 1
3151 23:34:58.602182 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3152 23:34:58.602744 ==
3153 23:34:58.605302 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3154 23:34:58.612020 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3155 23:34:58.621089 [CA 0] Center 37 (7~68) winsize 62
3156 23:34:58.624423 [CA 1] Center 37 (7~68) winsize 62
3157 23:34:58.627141 [CA 2] Center 35 (5~65) winsize 61
3158 23:34:58.630521 [CA 3] Center 34 (4~65) winsize 62
3159 23:34:58.634217 [CA 4] Center 34 (4~65) winsize 62
3160 23:34:58.637831 [CA 5] Center 34 (4~64) winsize 61
3161 23:34:58.638409
3162 23:34:58.640674 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3163 23:34:58.641138
3164 23:34:58.643985 [CATrainingPosCal] consider 2 rank data
3165 23:34:58.647849 u2DelayCellTimex100 = 270/100 ps
3166 23:34:58.650667 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3167 23:34:58.654569 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3168 23:34:58.660899 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3169 23:34:58.664009 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3170 23:34:58.667361 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3171 23:34:58.670700 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3172 23:34:58.671275
3173 23:34:58.674307 CA PerBit enable=1, Macro0, CA PI delay=33
3174 23:34:58.674776
3175 23:34:58.677407 [CBTSetCACLKResult] CA Dly = 33
3176 23:34:58.678151 CS Dly: 8 (0~40)
3177 23:34:58.678582
3178 23:34:58.680551 ----->DramcWriteLeveling(PI) begin...
3179 23:34:58.683906 ==
3180 23:34:58.687245 Dram Type= 6, Freq= 0, CH_1, rank 0
3181 23:34:58.690696 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3182 23:34:58.691168 ==
3183 23:34:58.694273 Write leveling (Byte 0): 26 => 26
3184 23:34:58.697217 Write leveling (Byte 1): 27 => 27
3185 23:34:58.700523 DramcWriteLeveling(PI) end<-----
3186 23:34:58.701281
3187 23:34:58.701744 ==
3188 23:34:58.703887 Dram Type= 6, Freq= 0, CH_1, rank 0
3189 23:34:58.707155 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3190 23:34:58.707736 ==
3191 23:34:58.710708 [Gating] SW mode calibration
3192 23:34:58.717041 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3193 23:34:58.720636 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3194 23:34:58.726992 0 15 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3195 23:34:58.730594 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3196 23:34:58.734115 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3197 23:34:58.740657 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3198 23:34:58.743975 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3199 23:34:58.747432 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3200 23:34:58.754054 0 15 24 | B1->B0 | 3232 2a2a | 0 0 | (0 1) (0 0)
3201 23:34:58.757221 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
3202 23:34:58.760875 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3203 23:34:58.767213 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3204 23:34:58.770909 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3205 23:34:58.774236 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3206 23:34:58.780830 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3207 23:34:58.784208 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3208 23:34:58.787494 1 0 24 | B1->B0 | 2f2f 3c3c | 0 0 | (0 0) (1 1)
3209 23:34:58.794153 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3210 23:34:58.797450 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3211 23:34:58.800749 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3212 23:34:58.807506 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3213 23:34:58.811060 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3214 23:34:58.814326 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3215 23:34:58.817096 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3216 23:34:58.824275 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3217 23:34:58.827415 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3218 23:34:58.830990 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3219 23:34:58.837636 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3220 23:34:58.840784 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3221 23:34:58.844029 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3222 23:34:58.850853 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3223 23:34:58.854038 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3224 23:34:58.857974 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3225 23:34:58.864167 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3226 23:34:58.867301 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3227 23:34:58.870649 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3228 23:34:58.877615 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3229 23:34:58.880718 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3230 23:34:58.884553 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3231 23:34:58.890679 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3232 23:34:58.894448 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3233 23:34:58.897711 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3234 23:34:58.903933 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3235 23:34:58.904405 Total UI for P1: 0, mck2ui 16
3236 23:34:58.907572 best dqsien dly found for B0: ( 1, 3, 26)
3237 23:34:58.911086 Total UI for P1: 0, mck2ui 16
3238 23:34:58.914311 best dqsien dly found for B1: ( 1, 3, 26)
3239 23:34:58.917329 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3240 23:34:58.923882 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3241 23:34:58.924441
3242 23:34:58.927850 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3243 23:34:58.931279 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3244 23:34:58.933931 [Gating] SW calibration Done
3245 23:34:58.934399 ==
3246 23:34:58.937491 Dram Type= 6, Freq= 0, CH_1, rank 0
3247 23:34:58.940584 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3248 23:34:58.941160 ==
3249 23:34:58.941542 RX Vref Scan: 0
3250 23:34:58.944239
3251 23:34:58.944826 RX Vref 0 -> 0, step: 1
3252 23:34:58.945207
3253 23:34:58.948013 RX Delay -40 -> 252, step: 8
3254 23:34:58.950392 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3255 23:34:58.954297 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3256 23:34:58.961240 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3257 23:34:58.964118 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3258 23:34:58.967714 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3259 23:34:58.970668 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3260 23:34:58.974539 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3261 23:34:58.977931 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3262 23:34:58.984322 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3263 23:34:58.987254 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3264 23:34:58.990983 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3265 23:34:58.993941 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3266 23:34:59.000568 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3267 23:34:59.004487 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3268 23:34:59.007548 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3269 23:34:59.011435 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3270 23:34:59.012012 ==
3271 23:34:59.014364 Dram Type= 6, Freq= 0, CH_1, rank 0
3272 23:34:59.017711 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3273 23:34:59.021114 ==
3274 23:34:59.021754 DQS Delay:
3275 23:34:59.022148 DQS0 = 0, DQS1 = 0
3276 23:34:59.024166 DQM Delay:
3277 23:34:59.024634 DQM0 = 119, DQM1 = 116
3278 23:34:59.027538 DQ Delay:
3279 23:34:59.031358 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3280 23:34:59.033877 DQ4 =119, DQ5 =127, DQ6 =127, DQ7 =119
3281 23:34:59.038072 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =111
3282 23:34:59.040722 DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123
3283 23:34:59.041219
3284 23:34:59.041832
3285 23:34:59.042316 ==
3286 23:34:59.044760 Dram Type= 6, Freq= 0, CH_1, rank 0
3287 23:34:59.047928 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3288 23:34:59.048396 ==
3289 23:34:59.048880
3290 23:34:59.049339
3291 23:34:59.050855 TX Vref Scan disable
3292 23:34:59.054484 == TX Byte 0 ==
3293 23:34:59.057762 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3294 23:34:59.061113 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3295 23:34:59.064410 == TX Byte 1 ==
3296 23:34:59.067654 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3297 23:34:59.070968 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3298 23:34:59.071451 ==
3299 23:34:59.074217 Dram Type= 6, Freq= 0, CH_1, rank 0
3300 23:34:59.077631 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3301 23:34:59.080481 ==
3302 23:34:59.090639 TX Vref=22, minBit 9, minWin=24, winSum=410
3303 23:34:59.094064 TX Vref=24, minBit 9, minWin=24, winSum=419
3304 23:34:59.097246 TX Vref=26, minBit 9, minWin=25, winSum=423
3305 23:34:59.101196 TX Vref=28, minBit 2, minWin=26, winSum=427
3306 23:34:59.104636 TX Vref=30, minBit 2, minWin=26, winSum=429
3307 23:34:59.111299 TX Vref=32, minBit 10, minWin=25, winSum=433
3308 23:34:59.114585 [TxChooseVref] Worse bit 2, Min win 26, Win sum 429, Final Vref 30
3309 23:34:59.115109
3310 23:34:59.117517 Final TX Range 1 Vref 30
3311 23:34:59.117972
3312 23:34:59.118311 ==
3313 23:34:59.120824 Dram Type= 6, Freq= 0, CH_1, rank 0
3314 23:34:59.124095 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3315 23:34:59.124530 ==
3316 23:34:59.127113
3317 23:34:59.127541
3318 23:34:59.127884 TX Vref Scan disable
3319 23:34:59.130673 == TX Byte 0 ==
3320 23:34:59.134114 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3321 23:34:59.137874 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3322 23:34:59.140935 == TX Byte 1 ==
3323 23:34:59.144441 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3324 23:34:59.147391 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3325 23:34:59.150661
3326 23:34:59.151186 [DATLAT]
3327 23:34:59.151535 Freq=1200, CH1 RK0
3328 23:34:59.151856
3329 23:34:59.153939 DATLAT Default: 0xd
3330 23:34:59.154457 0, 0xFFFF, sum = 0
3331 23:34:59.157080 1, 0xFFFF, sum = 0
3332 23:34:59.157514 2, 0xFFFF, sum = 0
3333 23:34:59.160700 3, 0xFFFF, sum = 0
3334 23:34:59.161132 4, 0xFFFF, sum = 0
3335 23:34:59.164234 5, 0xFFFF, sum = 0
3336 23:34:59.167084 6, 0xFFFF, sum = 0
3337 23:34:59.167535 7, 0xFFFF, sum = 0
3338 23:34:59.170393 8, 0xFFFF, sum = 0
3339 23:34:59.170827 9, 0xFFFF, sum = 0
3340 23:34:59.173614 10, 0xFFFF, sum = 0
3341 23:34:59.174060 11, 0xFFFF, sum = 0
3342 23:34:59.177262 12, 0x0, sum = 1
3343 23:34:59.177774 13, 0x0, sum = 2
3344 23:34:59.180595 14, 0x0, sum = 3
3345 23:34:59.181044 15, 0x0, sum = 4
3346 23:34:59.181501 best_step = 13
3347 23:34:59.181967
3348 23:34:59.184003 ==
3349 23:34:59.187653 Dram Type= 6, Freq= 0, CH_1, rank 0
3350 23:34:59.190304 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3351 23:34:59.190755 ==
3352 23:34:59.191203 RX Vref Scan: 1
3353 23:34:59.191645
3354 23:34:59.193705 Set Vref Range= 32 -> 127
3355 23:34:59.194150
3356 23:34:59.197313 RX Vref 32 -> 127, step: 1
3357 23:34:59.197898
3358 23:34:59.201008 RX Delay -5 -> 252, step: 4
3359 23:34:59.201541
3360 23:34:59.204103 Set Vref, RX VrefLevel [Byte0]: 32
3361 23:34:59.207195 [Byte1]: 32
3362 23:34:59.207726
3363 23:34:59.210611 Set Vref, RX VrefLevel [Byte0]: 33
3364 23:34:59.214028 [Byte1]: 33
3365 23:34:59.214396
3366 23:34:59.216937 Set Vref, RX VrefLevel [Byte0]: 34
3367 23:34:59.220202 [Byte1]: 34
3368 23:34:59.224331
3369 23:34:59.224599 Set Vref, RX VrefLevel [Byte0]: 35
3370 23:34:59.227839 [Byte1]: 35
3371 23:34:59.232731
3372 23:34:59.232962 Set Vref, RX VrefLevel [Byte0]: 36
3373 23:34:59.235643 [Byte1]: 36
3374 23:34:59.240378
3375 23:34:59.240615 Set Vref, RX VrefLevel [Byte0]: 37
3376 23:34:59.243415 [Byte1]: 37
3377 23:34:59.248516
3378 23:34:59.248750 Set Vref, RX VrefLevel [Byte0]: 38
3379 23:34:59.251727 [Byte1]: 38
3380 23:34:59.255632
3381 23:34:59.255864 Set Vref, RX VrefLevel [Byte0]: 39
3382 23:34:59.258944 [Byte1]: 39
3383 23:34:59.263736
3384 23:34:59.263995 Set Vref, RX VrefLevel [Byte0]: 40
3385 23:34:59.266851 [Byte1]: 40
3386 23:34:59.272110
3387 23:34:59.272460 Set Vref, RX VrefLevel [Byte0]: 41
3388 23:34:59.274845 [Byte1]: 41
3389 23:34:59.279848
3390 23:34:59.280149 Set Vref, RX VrefLevel [Byte0]: 42
3391 23:34:59.283168 [Byte1]: 42
3392 23:34:59.287612
3393 23:34:59.288137 Set Vref, RX VrefLevel [Byte0]: 43
3394 23:34:59.290686 [Byte1]: 43
3395 23:34:59.295621
3396 23:34:59.296042 Set Vref, RX VrefLevel [Byte0]: 44
3397 23:34:59.299072 [Byte1]: 44
3398 23:34:59.303066
3399 23:34:59.303486 Set Vref, RX VrefLevel [Byte0]: 45
3400 23:34:59.307075 [Byte1]: 45
3401 23:34:59.311114
3402 23:34:59.311627 Set Vref, RX VrefLevel [Byte0]: 46
3403 23:34:59.314305 [Byte1]: 46
3404 23:34:59.318938
3405 23:34:59.319472 Set Vref, RX VrefLevel [Byte0]: 47
3406 23:34:59.322651 [Byte1]: 47
3407 23:34:59.326981
3408 23:34:59.327401 Set Vref, RX VrefLevel [Byte0]: 48
3409 23:34:59.329887 [Byte1]: 48
3410 23:34:59.334608
3411 23:34:59.335140 Set Vref, RX VrefLevel [Byte0]: 49
3412 23:34:59.338130 [Byte1]: 49
3413 23:34:59.342990
3414 23:34:59.343505 Set Vref, RX VrefLevel [Byte0]: 50
3415 23:34:59.346197 [Byte1]: 50
3416 23:34:59.350380
3417 23:34:59.350895 Set Vref, RX VrefLevel [Byte0]: 51
3418 23:34:59.353651 [Byte1]: 51
3419 23:34:59.358691
3420 23:34:59.359208 Set Vref, RX VrefLevel [Byte0]: 52
3421 23:34:59.362172 [Byte1]: 52
3422 23:34:59.366453
3423 23:34:59.367030 Set Vref, RX VrefLevel [Byte0]: 53
3424 23:34:59.369104 [Byte1]: 53
3425 23:34:59.373658
3426 23:34:59.374101 Set Vref, RX VrefLevel [Byte0]: 54
3427 23:34:59.377426 [Byte1]: 54
3428 23:34:59.381618
3429 23:34:59.382069 Set Vref, RX VrefLevel [Byte0]: 55
3430 23:34:59.385725 [Byte1]: 55
3431 23:34:59.389704
3432 23:34:59.390323 Set Vref, RX VrefLevel [Byte0]: 56
3433 23:34:59.393033 [Byte1]: 56
3434 23:34:59.397609
3435 23:34:59.398160 Set Vref, RX VrefLevel [Byte0]: 57
3436 23:34:59.400783 [Byte1]: 57
3437 23:34:59.405437
3438 23:34:59.406034 Set Vref, RX VrefLevel [Byte0]: 58
3439 23:34:59.408805 [Byte1]: 58
3440 23:34:59.413322
3441 23:34:59.413903 Set Vref, RX VrefLevel [Byte0]: 59
3442 23:34:59.417137 [Byte1]: 59
3443 23:34:59.421202
3444 23:34:59.421781 Set Vref, RX VrefLevel [Byte0]: 60
3445 23:34:59.424042 [Byte1]: 60
3446 23:34:59.428720
3447 23:34:59.429160 Set Vref, RX VrefLevel [Byte0]: 61
3448 23:34:59.432436 [Byte1]: 61
3449 23:34:59.437107
3450 23:34:59.437674 Set Vref, RX VrefLevel [Byte0]: 62
3451 23:34:59.440130 [Byte1]: 62
3452 23:34:59.445173
3453 23:34:59.445752 Set Vref, RX VrefLevel [Byte0]: 63
3454 23:34:59.447473 [Byte1]: 63
3455 23:34:59.452687
3456 23:34:59.453222 Set Vref, RX VrefLevel [Byte0]: 64
3457 23:34:59.455664 [Byte1]: 64
3458 23:34:59.460322
3459 23:34:59.460860 Set Vref, RX VrefLevel [Byte0]: 65
3460 23:34:59.463557 [Byte1]: 65
3461 23:34:59.468033
3462 23:34:59.468563 Set Vref, RX VrefLevel [Byte0]: 66
3463 23:34:59.471492 [Byte1]: 66
3464 23:34:59.475831
3465 23:34:59.476376 Set Vref, RX VrefLevel [Byte0]: 67
3466 23:34:59.478673 [Byte1]: 67
3467 23:34:59.483725
3468 23:34:59.484280 Set Vref, RX VrefLevel [Byte0]: 68
3469 23:34:59.486999 [Byte1]: 68
3470 23:34:59.491347
3471 23:34:59.491788 Set Vref, RX VrefLevel [Byte0]: 69
3472 23:34:59.494823 [Byte1]: 69
3473 23:34:59.499464
3474 23:34:59.500000 Set Vref, RX VrefLevel [Byte0]: 70
3475 23:34:59.503003 [Byte1]: 70
3476 23:34:59.507375
3477 23:34:59.507917 Set Vref, RX VrefLevel [Byte0]: 71
3478 23:34:59.510424 [Byte1]: 71
3479 23:34:59.515398
3480 23:34:59.515942 Final RX Vref Byte 0 = 53 to rank0
3481 23:34:59.518460 Final RX Vref Byte 1 = 54 to rank0
3482 23:34:59.522032 Final RX Vref Byte 0 = 53 to rank1
3483 23:34:59.525262 Final RX Vref Byte 1 = 54 to rank1==
3484 23:34:59.528600 Dram Type= 6, Freq= 0, CH_1, rank 0
3485 23:34:59.535082 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3486 23:34:59.535619 ==
3487 23:34:59.535966 DQS Delay:
3488 23:34:59.536282 DQS0 = 0, DQS1 = 0
3489 23:34:59.538293 DQM Delay:
3490 23:34:59.538722 DQM0 = 119, DQM1 = 117
3491 23:34:59.541540 DQ Delay:
3492 23:34:59.544827 DQ0 =122, DQ1 =114, DQ2 =110, DQ3 =114
3493 23:34:59.548805 DQ4 =118, DQ5 =128, DQ6 =130, DQ7 =120
3494 23:34:59.552177 DQ8 =104, DQ9 =110, DQ10 =118, DQ11 =112
3495 23:34:59.555306 DQ12 =124, DQ13 =124, DQ14 =124, DQ15 =126
3496 23:34:59.555837
3497 23:34:59.556184
3498 23:34:59.562334 [DQSOSCAuto] RK0, (LSB)MR18= 0xfe10, (MSB)MR19= 0x304, tDQSOscB0 = 403 ps tDQSOscB1 = 410 ps
3499 23:34:59.565433 CH1 RK0: MR19=304, MR18=FE10
3500 23:34:59.572423 CH1_RK0: MR19=0x304, MR18=0xFE10, DQSOSC=403, MR23=63, INC=40, DEC=26
3501 23:34:59.573011
3502 23:34:59.575432 ----->DramcWriteLeveling(PI) begin...
3503 23:34:59.575908 ==
3504 23:34:59.578628 Dram Type= 6, Freq= 0, CH_1, rank 1
3505 23:34:59.581839 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3506 23:34:59.585241 ==
3507 23:34:59.585727 Write leveling (Byte 0): 24 => 24
3508 23:34:59.588622 Write leveling (Byte 1): 28 => 28
3509 23:34:59.592414 DramcWriteLeveling(PI) end<-----
3510 23:34:59.592942
3511 23:34:59.593389 ==
3512 23:34:59.595282 Dram Type= 6, Freq= 0, CH_1, rank 1
3513 23:34:59.602229 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3514 23:34:59.602781 ==
3515 23:34:59.603279 [Gating] SW mode calibration
3516 23:34:59.612691 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3517 23:34:59.615794 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3518 23:34:59.618648 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3519 23:34:59.625500 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3520 23:34:59.629254 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3521 23:34:59.632238 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3522 23:34:59.638738 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3523 23:34:59.642085 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3524 23:34:59.645561 0 15 24 | B1->B0 | 2c2c 3434 | 0 1 | (0 1) (1 0)
3525 23:34:59.652254 0 15 28 | B1->B0 | 2323 2828 | 0 1 | (0 0) (1 0)
3526 23:34:59.655713 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3527 23:34:59.658544 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3528 23:34:59.666059 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3529 23:34:59.668869 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3530 23:34:59.672462 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3531 23:34:59.678958 1 0 20 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
3532 23:34:59.681972 1 0 24 | B1->B0 | 4242 2828 | 0 1 | (0 0) (0 0)
3533 23:34:59.685698 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3534 23:34:59.691636 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3535 23:34:59.695548 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3536 23:34:59.698339 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3537 23:34:59.701790 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3538 23:34:59.708775 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3539 23:34:59.712000 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3540 23:34:59.715293 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3541 23:34:59.722558 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3542 23:34:59.725538 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3543 23:34:59.729018 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3544 23:34:59.735071 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3545 23:34:59.738859 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3546 23:34:59.741819 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3547 23:34:59.748747 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3548 23:34:59.751822 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3549 23:34:59.755387 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3550 23:34:59.761444 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3551 23:34:59.764897 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3552 23:34:59.768305 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3553 23:34:59.775127 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3554 23:34:59.778164 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3555 23:34:59.781461 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3556 23:34:59.788561 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3557 23:34:59.789115 Total UI for P1: 0, mck2ui 16
3558 23:34:59.794956 best dqsien dly found for B1: ( 1, 3, 20)
3559 23:34:59.798295 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3560 23:34:59.802326 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3561 23:34:59.805238 Total UI for P1: 0, mck2ui 16
3562 23:34:59.808324 best dqsien dly found for B0: ( 1, 3, 26)
3563 23:34:59.811727 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3564 23:34:59.815273 best DQS1 dly(MCK, UI, PI) = (1, 3, 20)
3565 23:34:59.815789
3566 23:34:59.818232 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3567 23:34:59.824790 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 20)
3568 23:34:59.825322 [Gating] SW calibration Done
3569 23:34:59.825828 ==
3570 23:34:59.828222 Dram Type= 6, Freq= 0, CH_1, rank 1
3571 23:34:59.835151 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3572 23:34:59.835707 ==
3573 23:34:59.836169 RX Vref Scan: 0
3574 23:34:59.836600
3575 23:34:59.838461 RX Vref 0 -> 0, step: 1
3576 23:34:59.838898
3577 23:34:59.841475 RX Delay -40 -> 252, step: 8
3578 23:34:59.845490 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3579 23:34:59.848420 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3580 23:34:59.852154 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3581 23:34:59.858600 iDelay=200, Bit 3, Center 119 (56 ~ 183) 128
3582 23:34:59.862135 iDelay=200, Bit 4, Center 119 (56 ~ 183) 128
3583 23:34:59.864821 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3584 23:34:59.868114 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3585 23:34:59.871984 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3586 23:34:59.878002 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3587 23:34:59.881469 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3588 23:34:59.884789 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3589 23:34:59.887772 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3590 23:34:59.891257 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3591 23:34:59.898103 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3592 23:34:59.901676 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3593 23:34:59.904992 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3594 23:34:59.905535 ==
3595 23:34:59.908299 Dram Type= 6, Freq= 0, CH_1, rank 1
3596 23:34:59.912236 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3597 23:34:59.912789 ==
3598 23:34:59.915333 DQS Delay:
3599 23:34:59.915883 DQS0 = 0, DQS1 = 0
3600 23:34:59.918329 DQM Delay:
3601 23:34:59.918769 DQM0 = 120, DQM1 = 116
3602 23:34:59.919218 DQ Delay:
3603 23:34:59.924719 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3604 23:34:59.928212 DQ4 =119, DQ5 =131, DQ6 =131, DQ7 =119
3605 23:34:59.931140 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =111
3606 23:34:59.935057 DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123
3607 23:34:59.935582
3608 23:34:59.935928
3609 23:34:59.936247 ==
3610 23:34:59.937709 Dram Type= 6, Freq= 0, CH_1, rank 1
3611 23:34:59.941398 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3612 23:34:59.941869 ==
3613 23:34:59.942216
3614 23:34:59.942538
3615 23:34:59.944367 TX Vref Scan disable
3616 23:34:59.947854 == TX Byte 0 ==
3617 23:34:59.951423 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3618 23:34:59.954891 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3619 23:34:59.957764 == TX Byte 1 ==
3620 23:34:59.961519 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3621 23:34:59.964332 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3622 23:34:59.964898 ==
3623 23:34:59.968226 Dram Type= 6, Freq= 0, CH_1, rank 1
3624 23:34:59.974715 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3625 23:34:59.975282 ==
3626 23:34:59.984385 TX Vref=22, minBit 9, minWin=24, winSum=420
3627 23:34:59.988103 TX Vref=24, minBit 1, minWin=26, winSum=424
3628 23:34:59.991529 TX Vref=26, minBit 2, minWin=26, winSum=431
3629 23:34:59.994461 TX Vref=28, minBit 9, minWin=26, winSum=432
3630 23:34:59.997997 TX Vref=30, minBit 9, minWin=26, winSum=435
3631 23:35:00.004684 TX Vref=32, minBit 10, minWin=26, winSum=433
3632 23:35:00.008108 [TxChooseVref] Worse bit 9, Min win 26, Win sum 435, Final Vref 30
3633 23:35:00.008637
3634 23:35:00.011329 Final TX Range 1 Vref 30
3635 23:35:00.011852
3636 23:35:00.012212 ==
3637 23:35:00.014317 Dram Type= 6, Freq= 0, CH_1, rank 1
3638 23:35:00.018327 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3639 23:35:00.021482 ==
3640 23:35:00.022096
3641 23:35:00.022474
3642 23:35:00.022823 TX Vref Scan disable
3643 23:35:00.024988 == TX Byte 0 ==
3644 23:35:00.027792 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3645 23:35:00.034493 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3646 23:35:00.035059 == TX Byte 1 ==
3647 23:35:00.037639 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3648 23:35:00.044427 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3649 23:35:00.044995
3650 23:35:00.045374 [DATLAT]
3651 23:35:00.045925 Freq=1200, CH1 RK1
3652 23:35:00.046458
3653 23:35:00.047541 DATLAT Default: 0xd
3654 23:35:00.048005 0, 0xFFFF, sum = 0
3655 23:35:00.051641 1, 0xFFFF, sum = 0
3656 23:35:00.054306 2, 0xFFFF, sum = 0
3657 23:35:00.054781 3, 0xFFFF, sum = 0
3658 23:35:00.057855 4, 0xFFFF, sum = 0
3659 23:35:00.058327 5, 0xFFFF, sum = 0
3660 23:35:00.060796 6, 0xFFFF, sum = 0
3661 23:35:00.061226 7, 0xFFFF, sum = 0
3662 23:35:00.064381 8, 0xFFFF, sum = 0
3663 23:35:00.064914 9, 0xFFFF, sum = 0
3664 23:35:00.067735 10, 0xFFFF, sum = 0
3665 23:35:00.068286 11, 0xFFFF, sum = 0
3666 23:35:00.070961 12, 0x0, sum = 1
3667 23:35:00.071433 13, 0x0, sum = 2
3668 23:35:00.074046 14, 0x0, sum = 3
3669 23:35:00.074602 15, 0x0, sum = 4
3670 23:35:00.077292 best_step = 13
3671 23:35:00.077746
3672 23:35:00.078090 ==
3673 23:35:00.080904 Dram Type= 6, Freq= 0, CH_1, rank 1
3674 23:35:00.084467 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3675 23:35:00.084895 ==
3676 23:35:00.085233 RX Vref Scan: 0
3677 23:35:00.085553
3678 23:35:00.088110 RX Vref 0 -> 0, step: 1
3679 23:35:00.088642
3680 23:35:00.090645 RX Delay -5 -> 252, step: 4
3681 23:35:00.093983 iDelay=195, Bit 0, Center 122 (59 ~ 186) 128
3682 23:35:00.100677 iDelay=195, Bit 1, Center 116 (55 ~ 178) 124
3683 23:35:00.104449 iDelay=195, Bit 2, Center 110 (51 ~ 170) 120
3684 23:35:00.107104 iDelay=195, Bit 3, Center 116 (55 ~ 178) 124
3685 23:35:00.110535 iDelay=195, Bit 4, Center 116 (55 ~ 178) 124
3686 23:35:00.113898 iDelay=195, Bit 5, Center 132 (71 ~ 194) 124
3687 23:35:00.120853 iDelay=195, Bit 6, Center 130 (67 ~ 194) 128
3688 23:35:00.123833 iDelay=195, Bit 7, Center 120 (59 ~ 182) 124
3689 23:35:00.126999 iDelay=195, Bit 8, Center 106 (47 ~ 166) 120
3690 23:35:00.130771 iDelay=195, Bit 9, Center 108 (47 ~ 170) 124
3691 23:35:00.133942 iDelay=195, Bit 10, Center 116 (55 ~ 178) 124
3692 23:35:00.140846 iDelay=195, Bit 11, Center 112 (51 ~ 174) 124
3693 23:35:00.143582 iDelay=195, Bit 12, Center 126 (63 ~ 190) 128
3694 23:35:00.146990 iDelay=195, Bit 13, Center 124 (67 ~ 182) 116
3695 23:35:00.151137 iDelay=195, Bit 14, Center 124 (67 ~ 182) 116
3696 23:35:00.157004 iDelay=195, Bit 15, Center 128 (67 ~ 190) 124
3697 23:35:00.157435 ==
3698 23:35:00.160450 Dram Type= 6, Freq= 0, CH_1, rank 1
3699 23:35:00.163640 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3700 23:35:00.164069 ==
3701 23:35:00.164413 DQS Delay:
3702 23:35:00.167596 DQS0 = 0, DQS1 = 0
3703 23:35:00.168121 DQM Delay:
3704 23:35:00.170939 DQM0 = 120, DQM1 = 118
3705 23:35:00.171467 DQ Delay:
3706 23:35:00.173753 DQ0 =122, DQ1 =116, DQ2 =110, DQ3 =116
3707 23:35:00.176800 DQ4 =116, DQ5 =132, DQ6 =130, DQ7 =120
3708 23:35:00.180415 DQ8 =106, DQ9 =108, DQ10 =116, DQ11 =112
3709 23:35:00.183462 DQ12 =126, DQ13 =124, DQ14 =124, DQ15 =128
3710 23:35:00.183889
3711 23:35:00.184227
3712 23:35:00.193478 [DQSOSCAuto] RK1, (LSB)MR18= 0x11ef, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 403 ps
3713 23:35:00.196849 CH1 RK1: MR19=403, MR18=11EF
3714 23:35:00.200375 CH1_RK1: MR19=0x403, MR18=0x11EF, DQSOSC=403, MR23=63, INC=40, DEC=26
3715 23:35:00.204062 [RxdqsGatingPostProcess] freq 1200
3716 23:35:00.210304 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3717 23:35:00.213743 best DQS0 dly(2T, 0.5T) = (0, 11)
3718 23:35:00.217163 best DQS1 dly(2T, 0.5T) = (0, 11)
3719 23:35:00.220426 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3720 23:35:00.223220 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3721 23:35:00.226553 best DQS0 dly(2T, 0.5T) = (0, 11)
3722 23:35:00.229752 best DQS1 dly(2T, 0.5T) = (0, 11)
3723 23:35:00.233631 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3724 23:35:00.236779 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3725 23:35:00.240300 Pre-setting of DQS Precalculation
3726 23:35:00.243096 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3727 23:35:00.250326 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3728 23:35:00.259905 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3729 23:35:00.260437
3730 23:35:00.260785
3731 23:35:00.261108 [Calibration Summary] 2400 Mbps
3732 23:35:00.263224 CH 0, Rank 0
3733 23:35:00.263649 SW Impedance : PASS
3734 23:35:00.266370 DUTY Scan : NO K
3735 23:35:00.269737 ZQ Calibration : PASS
3736 23:35:00.270254 Jitter Meter : NO K
3737 23:35:00.273040 CBT Training : PASS
3738 23:35:00.276289 Write leveling : PASS
3739 23:35:00.276714 RX DQS gating : PASS
3740 23:35:00.279791 RX DQ/DQS(RDDQC) : PASS
3741 23:35:00.283228 TX DQ/DQS : PASS
3742 23:35:00.283657 RX DATLAT : PASS
3743 23:35:00.286052 RX DQ/DQS(Engine): PASS
3744 23:35:00.289630 TX OE : NO K
3745 23:35:00.290065 All Pass.
3746 23:35:00.290461
3747 23:35:00.290817 CH 0, Rank 1
3748 23:35:00.293109 SW Impedance : PASS
3749 23:35:00.296317 DUTY Scan : NO K
3750 23:35:00.296841 ZQ Calibration : PASS
3751 23:35:00.299823 Jitter Meter : NO K
3752 23:35:00.302660 CBT Training : PASS
3753 23:35:00.303237 Write leveling : PASS
3754 23:35:00.306431 RX DQS gating : PASS
3755 23:35:00.309557 RX DQ/DQS(RDDQC) : PASS
3756 23:35:00.310166 TX DQ/DQS : PASS
3757 23:35:00.312900 RX DATLAT : PASS
3758 23:35:00.313416 RX DQ/DQS(Engine): PASS
3759 23:35:00.316846 TX OE : NO K
3760 23:35:00.317373 All Pass.
3761 23:35:00.317803
3762 23:35:00.319682 CH 1, Rank 0
3763 23:35:00.320109 SW Impedance : PASS
3764 23:35:00.323192 DUTY Scan : NO K
3765 23:35:00.326557 ZQ Calibration : PASS
3766 23:35:00.327077 Jitter Meter : NO K
3767 23:35:00.329714 CBT Training : PASS
3768 23:35:00.332927 Write leveling : PASS
3769 23:35:00.333342 RX DQS gating : PASS
3770 23:35:00.336907 RX DQ/DQS(RDDQC) : PASS
3771 23:35:00.339747 TX DQ/DQS : PASS
3772 23:35:00.340431 RX DATLAT : PASS
3773 23:35:00.343118 RX DQ/DQS(Engine): PASS
3774 23:35:00.346103 TX OE : NO K
3775 23:35:00.346565 All Pass.
3776 23:35:00.346933
3777 23:35:00.347281 CH 1, Rank 1
3778 23:35:00.349866 SW Impedance : PASS
3779 23:35:00.353066 DUTY Scan : NO K
3780 23:35:00.353663 ZQ Calibration : PASS
3781 23:35:00.356590 Jitter Meter : NO K
3782 23:35:00.357154 CBT Training : PASS
3783 23:35:00.359546 Write leveling : PASS
3784 23:35:00.363534 RX DQS gating : PASS
3785 23:35:00.364095 RX DQ/DQS(RDDQC) : PASS
3786 23:35:00.366243 TX DQ/DQS : PASS
3787 23:35:00.369963 RX DATLAT : PASS
3788 23:35:00.370525 RX DQ/DQS(Engine): PASS
3789 23:35:00.373207 TX OE : NO K
3790 23:35:00.373834 All Pass.
3791 23:35:00.374216
3792 23:35:00.376048 DramC Write-DBI off
3793 23:35:00.379840 PER_BANK_REFRESH: Hybrid Mode
3794 23:35:00.380405 TX_TRACKING: ON
3795 23:35:00.389816 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3796 23:35:00.392360 [FAST_K] Save calibration result to emmc
3797 23:35:00.396093 dramc_set_vcore_voltage set vcore to 650000
3798 23:35:00.399646 Read voltage for 600, 5
3799 23:35:00.400211 Vio18 = 0
3800 23:35:00.400588 Vcore = 650000
3801 23:35:00.402769 Vdram = 0
3802 23:35:00.403238 Vddq = 0
3803 23:35:00.403613 Vmddr = 0
3804 23:35:00.409304 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3805 23:35:00.412526 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3806 23:35:00.416255 MEM_TYPE=3, freq_sel=19
3807 23:35:00.419117 sv_algorithm_assistance_LP4_1600
3808 23:35:00.422545 ============ PULL DRAM RESETB DOWN ============
3809 23:35:00.429236 ========== PULL DRAM RESETB DOWN end =========
3810 23:35:00.432281 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3811 23:35:00.435833 ===================================
3812 23:35:00.438870 LPDDR4 DRAM CONFIGURATION
3813 23:35:00.442376 ===================================
3814 23:35:00.442872 EX_ROW_EN[0] = 0x0
3815 23:35:00.445234 EX_ROW_EN[1] = 0x0
3816 23:35:00.445753 LP4Y_EN = 0x0
3817 23:35:00.448850 WORK_FSP = 0x0
3818 23:35:00.449423 WL = 0x2
3819 23:35:00.452152 RL = 0x2
3820 23:35:00.452612 BL = 0x2
3821 23:35:00.455400 RPST = 0x0
3822 23:35:00.455861 RD_PRE = 0x0
3823 23:35:00.458792 WR_PRE = 0x1
3824 23:35:00.462061 WR_PST = 0x0
3825 23:35:00.462482 DBI_WR = 0x0
3826 23:35:00.465755 DBI_RD = 0x0
3827 23:35:00.466278 OTF = 0x1
3828 23:35:00.469280 ===================================
3829 23:35:00.472254 ===================================
3830 23:35:00.472809 ANA top config
3831 23:35:00.475149 ===================================
3832 23:35:00.479108 DLL_ASYNC_EN = 0
3833 23:35:00.481854 ALL_SLAVE_EN = 1
3834 23:35:00.485649 NEW_RANK_MODE = 1
3835 23:35:00.489008 DLL_IDLE_MODE = 1
3836 23:35:00.489538 LP45_APHY_COMB_EN = 1
3837 23:35:00.492170 TX_ODT_DIS = 1
3838 23:35:00.495132 NEW_8X_MODE = 1
3839 23:35:00.498472 ===================================
3840 23:35:00.501658 ===================================
3841 23:35:00.505621 data_rate = 1200
3842 23:35:00.508866 CKR = 1
3843 23:35:00.509392 DQ_P2S_RATIO = 8
3844 23:35:00.511954 ===================================
3845 23:35:00.515642 CA_P2S_RATIO = 8
3846 23:35:00.518433 DQ_CA_OPEN = 0
3847 23:35:00.522332 DQ_SEMI_OPEN = 0
3848 23:35:00.525406 CA_SEMI_OPEN = 0
3849 23:35:00.528371 CA_FULL_RATE = 0
3850 23:35:00.528791 DQ_CKDIV4_EN = 1
3851 23:35:00.531604 CA_CKDIV4_EN = 1
3852 23:35:00.535053 CA_PREDIV_EN = 0
3853 23:35:00.538405 PH8_DLY = 0
3854 23:35:00.541903 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3855 23:35:00.545437 DQ_AAMCK_DIV = 4
3856 23:35:00.546051 CA_AAMCK_DIV = 4
3857 23:35:00.548494 CA_ADMCK_DIV = 4
3858 23:35:00.551908 DQ_TRACK_CA_EN = 0
3859 23:35:00.554803 CA_PICK = 600
3860 23:35:00.558237 CA_MCKIO = 600
3861 23:35:00.561779 MCKIO_SEMI = 0
3862 23:35:00.565547 PLL_FREQ = 2288
3863 23:35:00.566252 DQ_UI_PI_RATIO = 32
3864 23:35:00.568294 CA_UI_PI_RATIO = 0
3865 23:35:00.571966 ===================================
3866 23:35:00.574765 ===================================
3867 23:35:00.578019 memory_type:LPDDR4
3868 23:35:00.581533 GP_NUM : 10
3869 23:35:00.581994 SRAM_EN : 1
3870 23:35:00.584752 MD32_EN : 0
3871 23:35:00.587974 ===================================
3872 23:35:00.591933 [ANA_INIT] >>>>>>>>>>>>>>
3873 23:35:00.592456 <<<<<< [CONFIGURE PHASE]: ANA_TX
3874 23:35:00.594515 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3875 23:35:00.598340 ===================================
3876 23:35:00.601716 data_rate = 1200,PCW = 0X5800
3877 23:35:00.604947 ===================================
3878 23:35:00.608349 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3879 23:35:00.615042 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3880 23:35:00.621249 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3881 23:35:00.625130 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3882 23:35:00.628098 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3883 23:35:00.631266 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3884 23:35:00.635009 [ANA_INIT] flow start
3885 23:35:00.635548 [ANA_INIT] PLL >>>>>>>>
3886 23:35:00.637972 [ANA_INIT] PLL <<<<<<<<
3887 23:35:00.641645 [ANA_INIT] MIDPI >>>>>>>>
3888 23:35:00.642180 [ANA_INIT] MIDPI <<<<<<<<
3889 23:35:00.644743 [ANA_INIT] DLL >>>>>>>>
3890 23:35:00.647884 [ANA_INIT] flow end
3891 23:35:00.651544 ============ LP4 DIFF to SE enter ============
3892 23:35:00.655036 ============ LP4 DIFF to SE exit ============
3893 23:35:00.657804 [ANA_INIT] <<<<<<<<<<<<<
3894 23:35:00.661686 [Flow] Enable top DCM control >>>>>
3895 23:35:00.664584 [Flow] Enable top DCM control <<<<<
3896 23:35:00.668342 Enable DLL master slave shuffle
3897 23:35:00.671259 ==============================================================
3898 23:35:00.674785 Gating Mode config
3899 23:35:00.681208 ==============================================================
3900 23:35:00.681886 Config description:
3901 23:35:00.690765 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3902 23:35:00.697873 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3903 23:35:00.704498 SELPH_MODE 0: By rank 1: By Phase
3904 23:35:00.707338 ==============================================================
3905 23:35:00.710962 GAT_TRACK_EN = 1
3906 23:35:00.714178 RX_GATING_MODE = 2
3907 23:35:00.717498 RX_GATING_TRACK_MODE = 2
3908 23:35:00.721027 SELPH_MODE = 1
3909 23:35:00.724032 PICG_EARLY_EN = 1
3910 23:35:00.727370 VALID_LAT_VALUE = 1
3911 23:35:00.730968 ==============================================================
3912 23:35:00.734135 Enter into Gating configuration >>>>
3913 23:35:00.737354 Exit from Gating configuration <<<<
3914 23:35:00.741142 Enter into DVFS_PRE_config >>>>>
3915 23:35:00.754435 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3916 23:35:00.757368 Exit from DVFS_PRE_config <<<<<
3917 23:35:00.761049 Enter into PICG configuration >>>>
3918 23:35:00.761789 Exit from PICG configuration <<<<
3919 23:35:00.764067 [RX_INPUT] configuration >>>>>
3920 23:35:00.767289 [RX_INPUT] configuration <<<<<
3921 23:35:00.774003 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3922 23:35:00.777264 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3923 23:35:00.784066 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3924 23:35:00.790726 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3925 23:35:00.797014 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3926 23:35:00.803831 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3927 23:35:00.807710 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3928 23:35:00.810928 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3929 23:35:00.814041 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3930 23:35:00.820679 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3931 23:35:00.824263 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3932 23:35:00.827541 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3933 23:35:00.831045 ===================================
3934 23:35:00.834192 LPDDR4 DRAM CONFIGURATION
3935 23:35:00.837237 ===================================
3936 23:35:00.840701 EX_ROW_EN[0] = 0x0
3937 23:35:00.841166 EX_ROW_EN[1] = 0x0
3938 23:35:00.843676 LP4Y_EN = 0x0
3939 23:35:00.844155 WORK_FSP = 0x0
3940 23:35:00.847539 WL = 0x2
3941 23:35:00.848074 RL = 0x2
3942 23:35:00.850254 BL = 0x2
3943 23:35:00.850724 RPST = 0x0
3944 23:35:00.853639 RD_PRE = 0x0
3945 23:35:00.854180 WR_PRE = 0x1
3946 23:35:00.857078 WR_PST = 0x0
3947 23:35:00.857655 DBI_WR = 0x0
3948 23:35:00.860063 DBI_RD = 0x0
3949 23:35:00.860482 OTF = 0x1
3950 23:35:00.863838 ===================================
3951 23:35:00.870229 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3952 23:35:00.873882 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3953 23:35:00.876870 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3954 23:35:00.879858 ===================================
3955 23:35:00.883816 LPDDR4 DRAM CONFIGURATION
3956 23:35:00.886892 ===================================
3957 23:35:00.890019 EX_ROW_EN[0] = 0x10
3958 23:35:00.890486 EX_ROW_EN[1] = 0x0
3959 23:35:00.893086 LP4Y_EN = 0x0
3960 23:35:00.893549 WORK_FSP = 0x0
3961 23:35:00.896421 WL = 0x2
3962 23:35:00.896882 RL = 0x2
3963 23:35:00.900264 BL = 0x2
3964 23:35:00.900824 RPST = 0x0
3965 23:35:00.903611 RD_PRE = 0x0
3966 23:35:00.904198 WR_PRE = 0x1
3967 23:35:00.906474 WR_PST = 0x0
3968 23:35:00.906978 DBI_WR = 0x0
3969 23:35:00.910218 DBI_RD = 0x0
3970 23:35:00.910684 OTF = 0x1
3971 23:35:00.913411 ===================================
3972 23:35:00.919806 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3973 23:35:00.924846 nWR fixed to 30
3974 23:35:00.927967 [ModeRegInit_LP4] CH0 RK0
3975 23:35:00.928473 [ModeRegInit_LP4] CH0 RK1
3976 23:35:00.931262 [ModeRegInit_LP4] CH1 RK0
3977 23:35:00.935086 [ModeRegInit_LP4] CH1 RK1
3978 23:35:00.935656 match AC timing 17
3979 23:35:00.940972 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3980 23:35:00.944678 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3981 23:35:00.947761 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3982 23:35:00.954165 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3983 23:35:00.957808 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3984 23:35:00.958386 ==
3985 23:35:00.961316 Dram Type= 6, Freq= 0, CH_0, rank 0
3986 23:35:00.964490 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3987 23:35:00.965066 ==
3988 23:35:00.970805 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3989 23:35:00.977200 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3990 23:35:00.980545 [CA 0] Center 35 (5~66) winsize 62
3991 23:35:00.984265 [CA 1] Center 36 (5~67) winsize 63
3992 23:35:00.987031 [CA 2] Center 34 (3~65) winsize 63
3993 23:35:00.990741 [CA 3] Center 33 (2~64) winsize 63
3994 23:35:00.993628 [CA 4] Center 33 (2~64) winsize 63
3995 23:35:00.997004 [CA 5] Center 32 (2~63) winsize 62
3996 23:35:00.997466
3997 23:35:01.000733 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3998 23:35:01.001301
3999 23:35:01.004133 [CATrainingPosCal] consider 1 rank data
4000 23:35:01.007247 u2DelayCellTimex100 = 270/100 ps
4001 23:35:01.010704 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
4002 23:35:01.013874 CA1 delay=36 (5~67),Diff = 4 PI (38 cell)
4003 23:35:01.016959 CA2 delay=34 (3~65),Diff = 2 PI (19 cell)
4004 23:35:01.020396 CA3 delay=33 (2~64),Diff = 1 PI (9 cell)
4005 23:35:01.026954 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
4006 23:35:01.030428 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
4007 23:35:01.030973
4008 23:35:01.033611 CA PerBit enable=1, Macro0, CA PI delay=32
4009 23:35:01.034061
4010 23:35:01.037006 [CBTSetCACLKResult] CA Dly = 32
4011 23:35:01.037449 CS Dly: 5 (0~36)
4012 23:35:01.037857 ==
4013 23:35:01.040193 Dram Type= 6, Freq= 0, CH_0, rank 1
4014 23:35:01.046809 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4015 23:35:01.047473 ==
4016 23:35:01.050398 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4017 23:35:01.056762 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4018 23:35:01.060110 [CA 0] Center 35 (5~66) winsize 62
4019 23:35:01.063457 [CA 1] Center 35 (5~66) winsize 62
4020 23:35:01.066730 [CA 2] Center 34 (3~65) winsize 63
4021 23:35:01.069780 [CA 3] Center 33 (3~64) winsize 62
4022 23:35:01.073200 [CA 4] Center 32 (2~63) winsize 62
4023 23:35:01.076354 [CA 5] Center 32 (2~63) winsize 62
4024 23:35:01.076675
4025 23:35:01.079774 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4026 23:35:01.080055
4027 23:35:01.083130 [CATrainingPosCal] consider 2 rank data
4028 23:35:01.086384 u2DelayCellTimex100 = 270/100 ps
4029 23:35:01.089402 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
4030 23:35:01.093418 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
4031 23:35:01.099953 CA2 delay=34 (3~65),Diff = 2 PI (19 cell)
4032 23:35:01.102927 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
4033 23:35:01.106582 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
4034 23:35:01.109517 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
4035 23:35:01.109985
4036 23:35:01.112930 CA PerBit enable=1, Macro0, CA PI delay=32
4037 23:35:01.113358
4038 23:35:01.116489 [CBTSetCACLKResult] CA Dly = 32
4039 23:35:01.116916 CS Dly: 5 (0~36)
4040 23:35:01.117334
4041 23:35:01.119475 ----->DramcWriteLeveling(PI) begin...
4042 23:35:01.123142 ==
4043 23:35:01.126829 Dram Type= 6, Freq= 0, CH_0, rank 0
4044 23:35:01.129563 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4045 23:35:01.130029 ==
4046 23:35:01.132648 Write leveling (Byte 0): 32 => 32
4047 23:35:01.136660 Write leveling (Byte 1): 32 => 32
4048 23:35:01.139783 DramcWriteLeveling(PI) end<-----
4049 23:35:01.140211
4050 23:35:01.140552 ==
4051 23:35:01.142585 Dram Type= 6, Freq= 0, CH_0, rank 0
4052 23:35:01.146387 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4053 23:35:01.146752 ==
4054 23:35:01.149786 [Gating] SW mode calibration
4055 23:35:01.155882 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4056 23:35:01.162791 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4057 23:35:01.165839 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4058 23:35:01.169534 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4059 23:35:01.172545 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4060 23:35:01.179351 0 9 12 | B1->B0 | 3434 2e2e | 1 1 | (1 1) (1 1)
4061 23:35:01.182796 0 9 16 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
4062 23:35:01.185687 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4063 23:35:01.192364 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4064 23:35:01.195678 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4065 23:35:01.198990 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4066 23:35:01.205766 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4067 23:35:01.209314 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4068 23:35:01.212450 0 10 12 | B1->B0 | 2323 3939 | 0 0 | (0 0) (0 0)
4069 23:35:01.218794 0 10 16 | B1->B0 | 3434 4646 | 0 0 | (0 0) (0 0)
4070 23:35:01.222369 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4071 23:35:01.225605 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4072 23:35:01.232568 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4073 23:35:01.235666 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4074 23:35:01.238685 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4075 23:35:01.245571 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4076 23:35:01.249393 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4077 23:35:01.251996 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4078 23:35:01.258803 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4079 23:35:01.262425 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4080 23:35:01.265369 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4081 23:35:01.271905 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4082 23:35:01.275581 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4083 23:35:01.278695 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4084 23:35:01.285600 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4085 23:35:01.288822 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4086 23:35:01.291960 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4087 23:35:01.299086 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4088 23:35:01.301764 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4089 23:35:01.305146 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4090 23:35:01.312083 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4091 23:35:01.315282 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4092 23:35:01.319049 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4093 23:35:01.325111 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4094 23:35:01.325682 Total UI for P1: 0, mck2ui 16
4095 23:35:01.331630 best dqsien dly found for B0: ( 0, 13, 12)
4096 23:35:01.334866 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4097 23:35:01.338214 Total UI for P1: 0, mck2ui 16
4098 23:35:01.341696 best dqsien dly found for B1: ( 0, 13, 16)
4099 23:35:01.345353 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4100 23:35:01.348186 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4101 23:35:01.348485
4102 23:35:01.351446 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4103 23:35:01.354665 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4104 23:35:01.358344 [Gating] SW calibration Done
4105 23:35:01.358675 ==
4106 23:35:01.361957 Dram Type= 6, Freq= 0, CH_0, rank 0
4107 23:35:01.365117 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4108 23:35:01.368397 ==
4109 23:35:01.368844 RX Vref Scan: 0
4110 23:35:01.369122
4111 23:35:01.371756 RX Vref 0 -> 0, step: 1
4112 23:35:01.372206
4113 23:35:01.375301 RX Delay -230 -> 252, step: 16
4114 23:35:01.378319 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4115 23:35:01.381879 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4116 23:35:01.385308 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4117 23:35:01.388312 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4118 23:35:01.394789 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4119 23:35:01.398524 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4120 23:35:01.401761 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4121 23:35:01.404981 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4122 23:35:01.408101 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4123 23:35:01.415029 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4124 23:35:01.418083 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4125 23:35:01.421681 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4126 23:35:01.424851 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4127 23:35:01.431251 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4128 23:35:01.434375 iDelay=218, Bit 14, Center 65 (-86 ~ 217) 304
4129 23:35:01.437756 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4130 23:35:01.437939 ==
4131 23:35:01.441424 Dram Type= 6, Freq= 0, CH_0, rank 0
4132 23:35:01.444244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4133 23:35:01.447894 ==
4134 23:35:01.448024 DQS Delay:
4135 23:35:01.448130 DQS0 = 0, DQS1 = 0
4136 23:35:01.450924 DQM Delay:
4137 23:35:01.451060 DQM0 = 50, DQM1 = 45
4138 23:35:01.454335 DQ Delay:
4139 23:35:01.457987 DQ0 =41, DQ1 =57, DQ2 =41, DQ3 =41
4140 23:35:01.458162 DQ4 =49, DQ5 =41, DQ6 =65, DQ7 =65
4141 23:35:01.461318 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =41
4142 23:35:01.464665 DQ12 =49, DQ13 =49, DQ14 =65, DQ15 =49
4143 23:35:01.467956
4144 23:35:01.468149
4145 23:35:01.468254 ==
4146 23:35:01.471246 Dram Type= 6, Freq= 0, CH_0, rank 0
4147 23:35:01.474392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4148 23:35:01.474552 ==
4149 23:35:01.474653
4150 23:35:01.474743
4151 23:35:01.477888 TX Vref Scan disable
4152 23:35:01.478328 == TX Byte 0 ==
4153 23:35:01.484567 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4154 23:35:01.487682 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4155 23:35:01.488107 == TX Byte 1 ==
4156 23:35:01.494250 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4157 23:35:01.498268 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4158 23:35:01.498694 ==
4159 23:35:01.501055 Dram Type= 6, Freq= 0, CH_0, rank 0
4160 23:35:01.504337 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4161 23:35:01.504769 ==
4162 23:35:01.505110
4163 23:35:01.505423
4164 23:35:01.507724 TX Vref Scan disable
4165 23:35:01.510794 == TX Byte 0 ==
4166 23:35:01.515107 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4167 23:35:01.517828 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4168 23:35:01.521168 == TX Byte 1 ==
4169 23:35:01.524603 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4170 23:35:01.527791 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4171 23:35:01.528265
4172 23:35:01.531389 [DATLAT]
4173 23:35:01.531857 Freq=600, CH0 RK0
4174 23:35:01.532233
4175 23:35:01.534243 DATLAT Default: 0x9
4176 23:35:01.534713 0, 0xFFFF, sum = 0
4177 23:35:01.537702 1, 0xFFFF, sum = 0
4178 23:35:01.538131 2, 0xFFFF, sum = 0
4179 23:35:01.540836 3, 0xFFFF, sum = 0
4180 23:35:01.541270 4, 0xFFFF, sum = 0
4181 23:35:01.544365 5, 0xFFFF, sum = 0
4182 23:35:01.544795 6, 0xFFFF, sum = 0
4183 23:35:01.547743 7, 0xFFFF, sum = 0
4184 23:35:01.548172 8, 0x0, sum = 1
4185 23:35:01.550660 9, 0x0, sum = 2
4186 23:35:01.551089 10, 0x0, sum = 3
4187 23:35:01.554964 11, 0x0, sum = 4
4188 23:35:01.555497 best_step = 9
4189 23:35:01.555837
4190 23:35:01.556150 ==
4191 23:35:01.557443 Dram Type= 6, Freq= 0, CH_0, rank 0
4192 23:35:01.564176 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4193 23:35:01.564751 ==
4194 23:35:01.565143 RX Vref Scan: 1
4195 23:35:01.565467
4196 23:35:01.568156 RX Vref 0 -> 0, step: 1
4197 23:35:01.568729
4198 23:35:01.571458 RX Delay -163 -> 252, step: 8
4199 23:35:01.572054
4200 23:35:01.574035 Set Vref, RX VrefLevel [Byte0]: 53
4201 23:35:01.577394 [Byte1]: 55
4202 23:35:01.577942
4203 23:35:01.580861 Final RX Vref Byte 0 = 53 to rank0
4204 23:35:01.584420 Final RX Vref Byte 1 = 55 to rank0
4205 23:35:01.587555 Final RX Vref Byte 0 = 53 to rank1
4206 23:35:01.590675 Final RX Vref Byte 1 = 55 to rank1==
4207 23:35:01.593943 Dram Type= 6, Freq= 0, CH_0, rank 0
4208 23:35:01.597569 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4209 23:35:01.598153 ==
4210 23:35:01.600646 DQS Delay:
4211 23:35:01.601102 DQS0 = 0, DQS1 = 0
4212 23:35:01.601444 DQM Delay:
4213 23:35:01.603834 DQM0 = 52, DQM1 = 46
4214 23:35:01.604254 DQ Delay:
4215 23:35:01.607559 DQ0 =52, DQ1 =52, DQ2 =48, DQ3 =48
4216 23:35:01.610997 DQ4 =52, DQ5 =44, DQ6 =60, DQ7 =60
4217 23:35:01.613965 DQ8 =32, DQ9 =36, DQ10 =48, DQ11 =40
4218 23:35:01.617698 DQ12 =52, DQ13 =52, DQ14 =56, DQ15 =52
4219 23:35:01.618276
4220 23:35:01.618654
4221 23:35:01.627291 [DQSOSCAuto] RK0, (LSB)MR18= 0x7265, (MSB)MR19= 0x808, tDQSOscB0 = 390 ps tDQSOscB1 = 388 ps
4222 23:35:01.627861 CH0 RK0: MR19=808, MR18=7265
4223 23:35:01.634006 CH0_RK0: MR19=0x808, MR18=0x7265, DQSOSC=388, MR23=63, INC=174, DEC=116
4224 23:35:01.634571
4225 23:35:01.637612 ----->DramcWriteLeveling(PI) begin...
4226 23:35:01.640873 ==
4227 23:35:01.641438 Dram Type= 6, Freq= 0, CH_0, rank 1
4228 23:35:01.647610 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4229 23:35:01.648184 ==
4230 23:35:01.650461 Write leveling (Byte 0): 34 => 34
4231 23:35:01.653931 Write leveling (Byte 1): 31 => 31
4232 23:35:01.657342 DramcWriteLeveling(PI) end<-----
4233 23:35:01.657934
4234 23:35:01.658308 ==
4235 23:35:01.660775 Dram Type= 6, Freq= 0, CH_0, rank 1
4236 23:35:01.663946 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4237 23:35:01.664515 ==
4238 23:35:01.667707 [Gating] SW mode calibration
4239 23:35:01.674306 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4240 23:35:01.677048 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4241 23:35:01.683744 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4242 23:35:01.686899 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4243 23:35:01.690687 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4244 23:35:01.697094 0 9 12 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
4245 23:35:01.700471 0 9 16 | B1->B0 | 2b2b 2424 | 0 0 | (0 0) (0 0)
4246 23:35:01.703309 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4247 23:35:01.710371 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4248 23:35:01.713729 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4249 23:35:01.716731 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4250 23:35:01.723536 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4251 23:35:01.726672 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4252 23:35:01.730269 0 10 12 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (0 0)
4253 23:35:01.736902 0 10 16 | B1->B0 | 3b3b 403f | 0 1 | (0 0) (0 0)
4254 23:35:01.740571 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4255 23:35:01.743577 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4256 23:35:01.750202 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4257 23:35:01.753573 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4258 23:35:01.757133 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4259 23:35:01.763246 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4260 23:35:01.766393 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4261 23:35:01.769989 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4262 23:35:01.776387 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4263 23:35:01.779768 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4264 23:35:01.783482 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4265 23:35:01.789901 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4266 23:35:01.793237 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4267 23:35:01.796791 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4268 23:35:01.803149 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4269 23:35:01.806204 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4270 23:35:01.809853 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4271 23:35:01.817067 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4272 23:35:01.820074 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4273 23:35:01.822824 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4274 23:35:01.829566 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4275 23:35:01.832981 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4276 23:35:01.836579 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4277 23:35:01.843127 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4278 23:35:01.843695 Total UI for P1: 0, mck2ui 16
4279 23:35:01.846622 best dqsien dly found for B0: ( 0, 13, 14)
4280 23:35:01.853311 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4281 23:35:01.856861 Total UI for P1: 0, mck2ui 16
4282 23:35:01.859900 best dqsien dly found for B1: ( 0, 13, 14)
4283 23:35:01.862840 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4284 23:35:01.866554 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4285 23:35:01.867124
4286 23:35:01.870097 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4287 23:35:01.872764 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4288 23:35:01.876757 [Gating] SW calibration Done
4289 23:35:01.877321 ==
4290 23:35:01.879662 Dram Type= 6, Freq= 0, CH_0, rank 1
4291 23:35:01.882611 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4292 23:35:01.883076 ==
4293 23:35:01.886241 RX Vref Scan: 0
4294 23:35:01.886715
4295 23:35:01.889340 RX Vref 0 -> 0, step: 1
4296 23:35:01.889963
4297 23:35:01.890442 RX Delay -230 -> 252, step: 16
4298 23:35:01.896498 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4299 23:35:01.899237 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4300 23:35:01.903195 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4301 23:35:01.905943 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4302 23:35:01.913307 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4303 23:35:01.916288 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4304 23:35:01.919485 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4305 23:35:01.922652 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4306 23:35:01.926156 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4307 23:35:01.932629 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4308 23:35:01.936544 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4309 23:35:01.939686 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4310 23:35:01.942547 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4311 23:35:01.949405 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4312 23:35:01.952610 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4313 23:35:01.956235 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4314 23:35:01.956799 ==
4315 23:35:01.959719 Dram Type= 6, Freq= 0, CH_0, rank 1
4316 23:35:01.963031 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4317 23:35:01.966172 ==
4318 23:35:01.966734 DQS Delay:
4319 23:35:01.967115 DQS0 = 0, DQS1 = 0
4320 23:35:01.969620 DQM Delay:
4321 23:35:01.970223 DQM0 = 51, DQM1 = 42
4322 23:35:01.972533 DQ Delay:
4323 23:35:01.975913 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =49
4324 23:35:01.976484 DQ4 =57, DQ5 =41, DQ6 =57, DQ7 =57
4325 23:35:01.978937 DQ8 =33, DQ9 =25, DQ10 =49, DQ11 =33
4326 23:35:01.982598 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4327 23:35:01.985508
4328 23:35:01.986019
4329 23:35:01.986393 ==
4330 23:35:01.989469 Dram Type= 6, Freq= 0, CH_0, rank 1
4331 23:35:01.992113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4332 23:35:01.992592 ==
4333 23:35:01.992968
4334 23:35:01.993315
4335 23:35:01.995585 TX Vref Scan disable
4336 23:35:01.996047 == TX Byte 0 ==
4337 23:35:02.002129 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4338 23:35:02.005454 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4339 23:35:02.005970 == TX Byte 1 ==
4340 23:35:02.012727 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4341 23:35:02.015681 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4342 23:35:02.016247 ==
4343 23:35:02.019316 Dram Type= 6, Freq= 0, CH_0, rank 1
4344 23:35:02.022327 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4345 23:35:02.022794 ==
4346 23:35:02.023164
4347 23:35:02.023510
4348 23:35:02.025655 TX Vref Scan disable
4349 23:35:02.029166 == TX Byte 0 ==
4350 23:35:02.032307 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4351 23:35:02.035780 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4352 23:35:02.038774 == TX Byte 1 ==
4353 23:35:02.042289 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4354 23:35:02.045717 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4355 23:35:02.049011
4356 23:35:02.049566 [DATLAT]
4357 23:35:02.050019 Freq=600, CH0 RK1
4358 23:35:02.050375
4359 23:35:02.052234 DATLAT Default: 0x9
4360 23:35:02.052690 0, 0xFFFF, sum = 0
4361 23:35:02.055357 1, 0xFFFF, sum = 0
4362 23:35:02.055828 2, 0xFFFF, sum = 0
4363 23:35:02.058900 3, 0xFFFF, sum = 0
4364 23:35:02.059392 4, 0xFFFF, sum = 0
4365 23:35:02.062161 5, 0xFFFF, sum = 0
4366 23:35:02.062624 6, 0xFFFF, sum = 0
4367 23:35:02.065486 7, 0xFFFF, sum = 0
4368 23:35:02.066001 8, 0x0, sum = 1
4369 23:35:02.068812 9, 0x0, sum = 2
4370 23:35:02.069229 10, 0x0, sum = 3
4371 23:35:02.071880 11, 0x0, sum = 4
4372 23:35:02.072297 best_step = 9
4373 23:35:02.072628
4374 23:35:02.072939 ==
4375 23:35:02.075284 Dram Type= 6, Freq= 0, CH_0, rank 1
4376 23:35:02.082054 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4377 23:35:02.082568 ==
4378 23:35:02.082904 RX Vref Scan: 0
4379 23:35:02.083234
4380 23:35:02.085069 RX Vref 0 -> 0, step: 1
4381 23:35:02.085483
4382 23:35:02.088416 RX Delay -179 -> 252, step: 8
4383 23:35:02.092225 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4384 23:35:02.098310 iDelay=205, Bit 1, Center 56 (-83 ~ 196) 280
4385 23:35:02.102342 iDelay=205, Bit 2, Center 52 (-91 ~ 196) 288
4386 23:35:02.105533 iDelay=205, Bit 3, Center 52 (-91 ~ 196) 288
4387 23:35:02.108713 iDelay=205, Bit 4, Center 60 (-83 ~ 204) 288
4388 23:35:02.112325 iDelay=205, Bit 5, Center 44 (-99 ~ 188) 288
4389 23:35:02.115639 iDelay=205, Bit 6, Center 60 (-75 ~ 196) 272
4390 23:35:02.121945 iDelay=205, Bit 7, Center 56 (-83 ~ 196) 280
4391 23:35:02.125497 iDelay=205, Bit 8, Center 36 (-107 ~ 180) 288
4392 23:35:02.128447 iDelay=205, Bit 9, Center 36 (-107 ~ 180) 288
4393 23:35:02.132053 iDelay=205, Bit 10, Center 44 (-99 ~ 188) 288
4394 23:35:02.138689 iDelay=205, Bit 11, Center 36 (-107 ~ 180) 288
4395 23:35:02.141906 iDelay=205, Bit 12, Center 52 (-91 ~ 196) 288
4396 23:35:02.145696 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4397 23:35:02.148711 iDelay=205, Bit 14, Center 56 (-83 ~ 196) 280
4398 23:35:02.151871 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4399 23:35:02.155010 ==
4400 23:35:02.155473 Dram Type= 6, Freq= 0, CH_0, rank 1
4401 23:35:02.162645 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4402 23:35:02.163207 ==
4403 23:35:02.163583 DQS Delay:
4404 23:35:02.165895 DQS0 = 0, DQS1 = 0
4405 23:35:02.166460 DQM Delay:
4406 23:35:02.168451 DQM0 = 54, DQM1 = 45
4407 23:35:02.168930 DQ Delay:
4408 23:35:02.171924 DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =52
4409 23:35:02.175161 DQ4 =60, DQ5 =44, DQ6 =60, DQ7 =56
4410 23:35:02.178825 DQ8 =36, DQ9 =36, DQ10 =44, DQ11 =36
4411 23:35:02.181313 DQ12 =52, DQ13 =52, DQ14 =56, DQ15 =52
4412 23:35:02.181826
4413 23:35:02.182555
4414 23:35:02.188156 [DQSOSCAuto] RK1, (LSB)MR18= 0x6324, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 391 ps
4415 23:35:02.191313 CH0 RK1: MR19=808, MR18=6324
4416 23:35:02.198309 CH0_RK1: MR19=0x808, MR18=0x6324, DQSOSC=391, MR23=63, INC=171, DEC=114
4417 23:35:02.201460 [RxdqsGatingPostProcess] freq 600
4418 23:35:02.208622 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4419 23:35:02.209184 Pre-setting of DQS Precalculation
4420 23:35:02.215326 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4421 23:35:02.215890 ==
4422 23:35:02.217984 Dram Type= 6, Freq= 0, CH_1, rank 0
4423 23:35:02.221735 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4424 23:35:02.222305 ==
4425 23:35:02.228095 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4426 23:35:02.234533 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4427 23:35:02.238082 [CA 0] Center 35 (5~66) winsize 62
4428 23:35:02.241450 [CA 1] Center 36 (5~67) winsize 63
4429 23:35:02.244662 [CA 2] Center 34 (4~65) winsize 62
4430 23:35:02.247945 [CA 3] Center 34 (4~65) winsize 62
4431 23:35:02.251361 [CA 4] Center 34 (4~65) winsize 62
4432 23:35:02.254865 [CA 5] Center 33 (3~64) winsize 62
4433 23:35:02.255431
4434 23:35:02.257911 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4435 23:35:02.258527
4436 23:35:02.261428 [CATrainingPosCal] consider 1 rank data
4437 23:35:02.264566 u2DelayCellTimex100 = 270/100 ps
4438 23:35:02.267678 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4439 23:35:02.271142 CA1 delay=36 (5~67),Diff = 3 PI (28 cell)
4440 23:35:02.274964 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4441 23:35:02.277816 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4442 23:35:02.281327 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4443 23:35:02.284145 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4444 23:35:02.288178
4445 23:35:02.290779 CA PerBit enable=1, Macro0, CA PI delay=33
4446 23:35:02.291242
4447 23:35:02.294272 [CBTSetCACLKResult] CA Dly = 33
4448 23:35:02.294733 CS Dly: 6 (0~37)
4449 23:35:02.295105 ==
4450 23:35:02.297552 Dram Type= 6, Freq= 0, CH_1, rank 1
4451 23:35:02.301651 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4452 23:35:02.302122 ==
4453 23:35:02.307751 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4454 23:35:02.314320 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4455 23:35:02.317756 [CA 0] Center 36 (5~67) winsize 63
4456 23:35:02.321420 [CA 1] Center 36 (5~67) winsize 63
4457 23:35:02.324584 [CA 2] Center 34 (4~65) winsize 62
4458 23:35:02.328059 [CA 3] Center 34 (4~65) winsize 62
4459 23:35:02.330945 [CA 4] Center 34 (4~65) winsize 62
4460 23:35:02.334455 [CA 5] Center 34 (3~65) winsize 63
4461 23:35:02.334937
4462 23:35:02.337795 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4463 23:35:02.338358
4464 23:35:02.341730 [CATrainingPosCal] consider 2 rank data
4465 23:35:02.344215 u2DelayCellTimex100 = 270/100 ps
4466 23:35:02.347595 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4467 23:35:02.351137 CA1 delay=36 (5~67),Diff = 3 PI (28 cell)
4468 23:35:02.354356 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4469 23:35:02.357659 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4470 23:35:02.361320 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4471 23:35:02.367856 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4472 23:35:02.368423
4473 23:35:02.370847 CA PerBit enable=1, Macro0, CA PI delay=33
4474 23:35:02.371414
4475 23:35:02.374135 [CBTSetCACLKResult] CA Dly = 33
4476 23:35:02.374698 CS Dly: 6 (0~38)
4477 23:35:02.375287
4478 23:35:02.377678 ----->DramcWriteLeveling(PI) begin...
4479 23:35:02.378252 ==
4480 23:35:02.380496 Dram Type= 6, Freq= 0, CH_1, rank 0
4481 23:35:02.387825 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4482 23:35:02.388394 ==
4483 23:35:02.390721 Write leveling (Byte 0): 32 => 32
4484 23:35:02.391183 Write leveling (Byte 1): 32 => 32
4485 23:35:02.393955 DramcWriteLeveling(PI) end<-----
4486 23:35:02.394415
4487 23:35:02.397197 ==
4488 23:35:02.397704 Dram Type= 6, Freq= 0, CH_1, rank 0
4489 23:35:02.403705 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4490 23:35:02.404174 ==
4491 23:35:02.407717 [Gating] SW mode calibration
4492 23:35:02.413983 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4493 23:35:02.417074 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4494 23:35:02.423614 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4495 23:35:02.427294 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4496 23:35:02.430271 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
4497 23:35:02.437664 0 9 12 | B1->B0 | 2f2f 2e2e | 0 0 | (0 0) (0 0)
4498 23:35:02.440525 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4499 23:35:02.443530 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4500 23:35:02.450602 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4501 23:35:02.453730 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4502 23:35:02.457120 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4503 23:35:02.463962 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4504 23:35:02.467152 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4505 23:35:02.470508 0 10 12 | B1->B0 | 3434 3636 | 0 0 | (0 0) (0 0)
4506 23:35:02.474315 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4507 23:35:02.479938 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4508 23:35:02.483279 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4509 23:35:02.486905 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4510 23:35:02.493456 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4511 23:35:02.496824 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4512 23:35:02.500186 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4513 23:35:02.506975 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4514 23:35:02.510327 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4515 23:35:02.513447 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4516 23:35:02.520626 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4517 23:35:02.523366 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4518 23:35:02.526746 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4519 23:35:02.533718 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4520 23:35:02.536769 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4521 23:35:02.539895 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4522 23:35:02.546577 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4523 23:35:02.550276 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4524 23:35:02.553400 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4525 23:35:02.559995 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4526 23:35:02.563744 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4527 23:35:02.566928 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4528 23:35:02.573238 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4529 23:35:02.576842 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4530 23:35:02.580205 Total UI for P1: 0, mck2ui 16
4531 23:35:02.583411 best dqsien dly found for B0: ( 0, 13, 8)
4532 23:35:02.586326 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4533 23:35:02.590009 Total UI for P1: 0, mck2ui 16
4534 23:35:02.593412 best dqsien dly found for B1: ( 0, 13, 10)
4535 23:35:02.596699 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4536 23:35:02.599516 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4537 23:35:02.599981
4538 23:35:02.603018 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4539 23:35:02.610087 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4540 23:35:02.610656 [Gating] SW calibration Done
4541 23:35:02.611038 ==
4542 23:35:02.613457 Dram Type= 6, Freq= 0, CH_1, rank 0
4543 23:35:02.620087 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4544 23:35:02.620655 ==
4545 23:35:02.621032 RX Vref Scan: 0
4546 23:35:02.621379
4547 23:35:02.622995 RX Vref 0 -> 0, step: 1
4548 23:35:02.623458
4549 23:35:02.626260 RX Delay -230 -> 252, step: 16
4550 23:35:02.630138 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4551 23:35:02.632786 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4552 23:35:02.639584 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4553 23:35:02.642736 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4554 23:35:02.646283 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4555 23:35:02.649715 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4556 23:35:02.652892 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4557 23:35:02.659517 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4558 23:35:02.662816 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4559 23:35:02.666302 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4560 23:35:02.669619 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4561 23:35:02.675838 iDelay=218, Bit 11, Center 49 (-102 ~ 201) 304
4562 23:35:02.679697 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4563 23:35:02.682200 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4564 23:35:02.685696 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4565 23:35:02.692875 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4566 23:35:02.693465 ==
4567 23:35:02.695559 Dram Type= 6, Freq= 0, CH_1, rank 0
4568 23:35:02.698997 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4569 23:35:02.699654 ==
4570 23:35:02.700094 DQS Delay:
4571 23:35:02.702086 DQS0 = 0, DQS1 = 0
4572 23:35:02.702556 DQM Delay:
4573 23:35:02.705917 DQM0 = 51, DQM1 = 47
4574 23:35:02.706485 DQ Delay:
4575 23:35:02.709158 DQ0 =57, DQ1 =49, DQ2 =41, DQ3 =49
4576 23:35:02.712340 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4577 23:35:02.715419 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =49
4578 23:35:02.719152 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4579 23:35:02.719750
4580 23:35:02.720136
4581 23:35:02.720492 ==
4582 23:35:02.722117 Dram Type= 6, Freq= 0, CH_1, rank 0
4583 23:35:02.725311 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4584 23:35:02.725835 ==
4585 23:35:02.728911
4586 23:35:02.729374
4587 23:35:02.729863 TX Vref Scan disable
4588 23:35:02.732052 == TX Byte 0 ==
4589 23:35:02.735179 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4590 23:35:02.738877 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4591 23:35:02.742075 == TX Byte 1 ==
4592 23:35:02.745682 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4593 23:35:02.748345 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4594 23:35:02.752149 ==
4595 23:35:02.755365 Dram Type= 6, Freq= 0, CH_1, rank 0
4596 23:35:02.758589 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4597 23:35:02.759214 ==
4598 23:35:02.759602
4599 23:35:02.759959
4600 23:35:02.762193 TX Vref Scan disable
4601 23:35:02.762769 == TX Byte 0 ==
4602 23:35:02.768711 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4603 23:35:02.771451 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4604 23:35:02.771921 == TX Byte 1 ==
4605 23:35:02.778667 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4606 23:35:02.781607 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4607 23:35:02.782196
4608 23:35:02.782578 [DATLAT]
4609 23:35:02.785369 Freq=600, CH1 RK0
4610 23:35:02.785985
4611 23:35:02.786374 DATLAT Default: 0x9
4612 23:35:02.788577 0, 0xFFFF, sum = 0
4613 23:35:02.789149 1, 0xFFFF, sum = 0
4614 23:35:02.791609 2, 0xFFFF, sum = 0
4615 23:35:02.792180 3, 0xFFFF, sum = 0
4616 23:35:02.795311 4, 0xFFFF, sum = 0
4617 23:35:02.798483 5, 0xFFFF, sum = 0
4618 23:35:02.798957 6, 0xFFFF, sum = 0
4619 23:35:02.801532 7, 0xFFFF, sum = 0
4620 23:35:02.802065 8, 0x0, sum = 1
4621 23:35:02.802454 9, 0x0, sum = 2
4622 23:35:02.804705 10, 0x0, sum = 3
4623 23:35:02.805179 11, 0x0, sum = 4
4624 23:35:02.808216 best_step = 9
4625 23:35:02.808781
4626 23:35:02.809203 ==
4627 23:35:02.811561 Dram Type= 6, Freq= 0, CH_1, rank 0
4628 23:35:02.815145 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4629 23:35:02.815712 ==
4630 23:35:02.818558 RX Vref Scan: 1
4631 23:35:02.819021
4632 23:35:02.819388 RX Vref 0 -> 0, step: 1
4633 23:35:02.819736
4634 23:35:02.821711 RX Delay -163 -> 252, step: 8
4635 23:35:02.822177
4636 23:35:02.825413 Set Vref, RX VrefLevel [Byte0]: 53
4637 23:35:02.828520 [Byte1]: 54
4638 23:35:02.831917
4639 23:35:02.832396 Final RX Vref Byte 0 = 53 to rank0
4640 23:35:02.835475 Final RX Vref Byte 1 = 54 to rank0
4641 23:35:02.838923 Final RX Vref Byte 0 = 53 to rank1
4642 23:35:02.841882 Final RX Vref Byte 1 = 54 to rank1==
4643 23:35:02.845350 Dram Type= 6, Freq= 0, CH_1, rank 0
4644 23:35:02.851978 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4645 23:35:02.852557 ==
4646 23:35:02.852934 DQS Delay:
4647 23:35:02.853284 DQS0 = 0, DQS1 = 0
4648 23:35:02.855746 DQM Delay:
4649 23:35:02.856319 DQM0 = 48, DQM1 = 44
4650 23:35:02.859022 DQ Delay:
4651 23:35:02.862003 DQ0 =52, DQ1 =40, DQ2 =36, DQ3 =44
4652 23:35:02.865510 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4653 23:35:02.869159 DQ8 =32, DQ9 =36, DQ10 =44, DQ11 =36
4654 23:35:02.872117 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =52
4655 23:35:02.872687
4656 23:35:02.873061
4657 23:35:02.878590 [DQSOSCAuto] RK0, (LSB)MR18= 0x4469, (MSB)MR19= 0x808, tDQSOscB0 = 390 ps tDQSOscB1 = 396 ps
4658 23:35:02.881570 CH1 RK0: MR19=808, MR18=4469
4659 23:35:02.888470 CH1_RK0: MR19=0x808, MR18=0x4469, DQSOSC=390, MR23=63, INC=172, DEC=114
4660 23:35:02.889029
4661 23:35:02.891813 ----->DramcWriteLeveling(PI) begin...
4662 23:35:02.892390 ==
4663 23:35:02.894942 Dram Type= 6, Freq= 0, CH_1, rank 1
4664 23:35:02.898551 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4665 23:35:02.899017 ==
4666 23:35:02.901956 Write leveling (Byte 0): 32 => 32
4667 23:35:02.904914 Write leveling (Byte 1): 32 => 32
4668 23:35:02.909066 DramcWriteLeveling(PI) end<-----
4669 23:35:02.909768
4670 23:35:02.910183 ==
4671 23:35:02.911797 Dram Type= 6, Freq= 0, CH_1, rank 1
4672 23:35:02.915042 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4673 23:35:02.915616 ==
4674 23:35:02.918812 [Gating] SW mode calibration
4675 23:35:02.925034 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4676 23:35:02.931430 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4677 23:35:02.935474 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4678 23:35:02.941777 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4679 23:35:02.944598 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
4680 23:35:02.948260 0 9 12 | B1->B0 | 2d2d 2f2f | 0 1 | (0 0) (1 0)
4681 23:35:02.951571 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4682 23:35:02.958322 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4683 23:35:02.961513 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4684 23:35:02.964551 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4685 23:35:02.971891 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4686 23:35:02.975123 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4687 23:35:02.978543 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4688 23:35:02.985192 0 10 12 | B1->B0 | 3535 3636 | 0 1 | (0 0) (0 0)
4689 23:35:02.987925 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4690 23:35:02.991297 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4691 23:35:02.998013 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4692 23:35:03.001653 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4693 23:35:03.005103 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4694 23:35:03.011706 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4695 23:35:03.015152 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4696 23:35:03.018625 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4697 23:35:03.024797 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4698 23:35:03.028231 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4699 23:35:03.031356 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4700 23:35:03.038495 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4701 23:35:03.041776 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4702 23:35:03.044788 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4703 23:35:03.052210 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4704 23:35:03.054769 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4705 23:35:03.058090 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4706 23:35:03.064927 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4707 23:35:03.067947 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4708 23:35:03.071300 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4709 23:35:03.077701 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4710 23:35:03.081221 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4711 23:35:03.084432 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4712 23:35:03.091424 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4713 23:35:03.094844 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4714 23:35:03.097479 Total UI for P1: 0, mck2ui 16
4715 23:35:03.101196 best dqsien dly found for B0: ( 0, 13, 12)
4716 23:35:03.104473 Total UI for P1: 0, mck2ui 16
4717 23:35:03.107700 best dqsien dly found for B1: ( 0, 13, 12)
4718 23:35:03.110744 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4719 23:35:03.114211 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4720 23:35:03.114780
4721 23:35:03.117661 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4722 23:35:03.121040 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4723 23:35:03.124260 [Gating] SW calibration Done
4724 23:35:03.124838 ==
4725 23:35:03.126902 Dram Type= 6, Freq= 0, CH_1, rank 1
4726 23:35:03.130249 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4727 23:35:03.134194 ==
4728 23:35:03.134784 RX Vref Scan: 0
4729 23:35:03.135275
4730 23:35:03.137294 RX Vref 0 -> 0, step: 1
4731 23:35:03.137817
4732 23:35:03.140807 RX Delay -230 -> 252, step: 16
4733 23:35:03.144200 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4734 23:35:03.146996 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4735 23:35:03.150249 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4736 23:35:03.154031 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4737 23:35:03.160575 iDelay=218, Bit 4, Center 57 (-86 ~ 201) 288
4738 23:35:03.163883 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4739 23:35:03.167553 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4740 23:35:03.170194 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4741 23:35:03.174019 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4742 23:35:03.180309 iDelay=218, Bit 9, Center 41 (-118 ~ 201) 320
4743 23:35:03.183754 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4744 23:35:03.186544 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4745 23:35:03.189978 iDelay=218, Bit 12, Center 65 (-86 ~ 217) 304
4746 23:35:03.196640 iDelay=218, Bit 13, Center 65 (-86 ~ 217) 304
4747 23:35:03.199791 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4748 23:35:03.203254 iDelay=218, Bit 15, Center 65 (-86 ~ 217) 304
4749 23:35:03.203738 ==
4750 23:35:03.206478 Dram Type= 6, Freq= 0, CH_1, rank 1
4751 23:35:03.213521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4752 23:35:03.214032 ==
4753 23:35:03.214599 DQS Delay:
4754 23:35:03.215043 DQS0 = 0, DQS1 = 0
4755 23:35:03.216368 DQM Delay:
4756 23:35:03.216852 DQM0 = 52, DQM1 = 51
4757 23:35:03.219711 DQ Delay:
4758 23:35:03.223286 DQ0 =57, DQ1 =41, DQ2 =33, DQ3 =49
4759 23:35:03.223828 DQ4 =57, DQ5 =65, DQ6 =65, DQ7 =49
4760 23:35:03.226505 DQ8 =33, DQ9 =41, DQ10 =49, DQ11 =41
4761 23:35:03.229667 DQ12 =65, DQ13 =65, DQ14 =49, DQ15 =65
4762 23:35:03.233348
4763 23:35:03.233823
4764 23:35:03.234261 ==
4765 23:35:03.236282 Dram Type= 6, Freq= 0, CH_1, rank 1
4766 23:35:03.240210 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4767 23:35:03.240926 ==
4768 23:35:03.241377
4769 23:35:03.241848
4770 23:35:03.243200 TX Vref Scan disable
4771 23:35:03.243622 == TX Byte 0 ==
4772 23:35:03.249767 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4773 23:35:03.253736 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4774 23:35:03.254256 == TX Byte 1 ==
4775 23:35:03.259584 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4776 23:35:03.263160 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4777 23:35:03.263585 ==
4778 23:35:03.266262 Dram Type= 6, Freq= 0, CH_1, rank 1
4779 23:35:03.269955 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4780 23:35:03.270481 ==
4781 23:35:03.270826
4782 23:35:03.271141
4783 23:35:03.272684 TX Vref Scan disable
4784 23:35:03.276742 == TX Byte 0 ==
4785 23:35:03.279692 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4786 23:35:03.282625 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4787 23:35:03.286158 == TX Byte 1 ==
4788 23:35:03.289679 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4789 23:35:03.292996 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4790 23:35:03.295954
4791 23:35:03.296509 [DATLAT]
4792 23:35:03.296888 Freq=600, CH1 RK1
4793 23:35:03.297243
4794 23:35:03.299603 DATLAT Default: 0x9
4795 23:35:03.300183 0, 0xFFFF, sum = 0
4796 23:35:03.303146 1, 0xFFFF, sum = 0
4797 23:35:03.303622 2, 0xFFFF, sum = 0
4798 23:35:03.306154 3, 0xFFFF, sum = 0
4799 23:35:03.306624 4, 0xFFFF, sum = 0
4800 23:35:03.309776 5, 0xFFFF, sum = 0
4801 23:35:03.312593 6, 0xFFFF, sum = 0
4802 23:35:03.313065 7, 0xFFFF, sum = 0
4803 23:35:03.313445 8, 0x0, sum = 1
4804 23:35:03.316817 9, 0x0, sum = 2
4805 23:35:03.317391 10, 0x0, sum = 3
4806 23:35:03.319525 11, 0x0, sum = 4
4807 23:35:03.320097 best_step = 9
4808 23:35:03.320471
4809 23:35:03.320815 ==
4810 23:35:03.322618 Dram Type= 6, Freq= 0, CH_1, rank 1
4811 23:35:03.330049 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4812 23:35:03.330621 ==
4813 23:35:03.330998 RX Vref Scan: 0
4814 23:35:03.331348
4815 23:35:03.333255 RX Vref 0 -> 0, step: 1
4816 23:35:03.333867
4817 23:35:03.336281 RX Delay -163 -> 252, step: 8
4818 23:35:03.339632 iDelay=205, Bit 0, Center 56 (-83 ~ 196) 280
4819 23:35:03.342768 iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288
4820 23:35:03.349510 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4821 23:35:03.353197 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4822 23:35:03.356252 iDelay=205, Bit 4, Center 44 (-99 ~ 188) 288
4823 23:35:03.359521 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4824 23:35:03.363333 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4825 23:35:03.370084 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4826 23:35:03.372871 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4827 23:35:03.376729 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4828 23:35:03.379671 iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296
4829 23:35:03.386343 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4830 23:35:03.389519 iDelay=205, Bit 12, Center 52 (-99 ~ 204) 304
4831 23:35:03.392952 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4832 23:35:03.395860 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4833 23:35:03.399698 iDelay=205, Bit 15, Center 56 (-91 ~ 204) 296
4834 23:35:03.400265 ==
4835 23:35:03.402792 Dram Type= 6, Freq= 0, CH_1, rank 1
4836 23:35:03.409510 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4837 23:35:03.410138 ==
4838 23:35:03.410518 DQS Delay:
4839 23:35:03.412707 DQS0 = 0, DQS1 = 0
4840 23:35:03.413223 DQM Delay:
4841 23:35:03.413854 DQM0 = 49, DQM1 = 45
4842 23:35:03.416273 DQ Delay:
4843 23:35:03.419381 DQ0 =56, DQ1 =44, DQ2 =36, DQ3 =44
4844 23:35:03.422496 DQ4 =44, DQ5 =60, DQ6 =60, DQ7 =48
4845 23:35:03.425961 DQ8 =32, DQ9 =32, DQ10 =48, DQ11 =40
4846 23:35:03.429866 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =56
4847 23:35:03.430427
4848 23:35:03.430800
4849 23:35:03.436590 [DQSOSCAuto] RK1, (LSB)MR18= 0x641c, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 391 ps
4850 23:35:03.439916 CH1 RK1: MR19=808, MR18=641C
4851 23:35:03.446152 CH1_RK1: MR19=0x808, MR18=0x641C, DQSOSC=391, MR23=63, INC=171, DEC=114
4852 23:35:03.449311 [RxdqsGatingPostProcess] freq 600
4853 23:35:03.452695 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4854 23:35:03.456033 Pre-setting of DQS Precalculation
4855 23:35:03.462484 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4856 23:35:03.469146 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4857 23:35:03.475683 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4858 23:35:03.476250
4859 23:35:03.476629
4860 23:35:03.479185 [Calibration Summary] 1200 Mbps
4861 23:35:03.479830 CH 0, Rank 0
4862 23:35:03.482570 SW Impedance : PASS
4863 23:35:03.485791 DUTY Scan : NO K
4864 23:35:03.486369 ZQ Calibration : PASS
4865 23:35:03.488680 Jitter Meter : NO K
4866 23:35:03.492792 CBT Training : PASS
4867 23:35:03.493360 Write leveling : PASS
4868 23:35:03.495923 RX DQS gating : PASS
4869 23:35:03.499267 RX DQ/DQS(RDDQC) : PASS
4870 23:35:03.499834 TX DQ/DQS : PASS
4871 23:35:03.502197 RX DATLAT : PASS
4872 23:35:03.505718 RX DQ/DQS(Engine): PASS
4873 23:35:03.506185 TX OE : NO K
4874 23:35:03.508728 All Pass.
4875 23:35:03.509286
4876 23:35:03.509836 CH 0, Rank 1
4877 23:35:03.511997 SW Impedance : PASS
4878 23:35:03.512477 DUTY Scan : NO K
4879 23:35:03.515733 ZQ Calibration : PASS
4880 23:35:03.518616 Jitter Meter : NO K
4881 23:35:03.519086 CBT Training : PASS
4882 23:35:03.522121 Write leveling : PASS
4883 23:35:03.525441 RX DQS gating : PASS
4884 23:35:03.526103 RX DQ/DQS(RDDQC) : PASS
4885 23:35:03.528698 TX DQ/DQS : PASS
4886 23:35:03.531842 RX DATLAT : PASS
4887 23:35:03.532367 RX DQ/DQS(Engine): PASS
4888 23:35:03.535454 TX OE : NO K
4889 23:35:03.535920 All Pass.
4890 23:35:03.536294
4891 23:35:03.538525 CH 1, Rank 0
4892 23:35:03.538993 SW Impedance : PASS
4893 23:35:03.541802 DUTY Scan : NO K
4894 23:35:03.542355 ZQ Calibration : PASS
4895 23:35:03.545387 Jitter Meter : NO K
4896 23:35:03.548951 CBT Training : PASS
4897 23:35:03.549415 Write leveling : PASS
4898 23:35:03.552167 RX DQS gating : PASS
4899 23:35:03.555574 RX DQ/DQS(RDDQC) : PASS
4900 23:35:03.556142 TX DQ/DQS : PASS
4901 23:35:03.558642 RX DATLAT : PASS
4902 23:35:03.562076 RX DQ/DQS(Engine): PASS
4903 23:35:03.562635 TX OE : NO K
4904 23:35:03.565637 All Pass.
4905 23:35:03.566116
4906 23:35:03.566488 CH 1, Rank 1
4907 23:35:03.568642 SW Impedance : PASS
4908 23:35:03.569209 DUTY Scan : NO K
4909 23:35:03.571884 ZQ Calibration : PASS
4910 23:35:03.575729 Jitter Meter : NO K
4911 23:35:03.576298 CBT Training : PASS
4912 23:35:03.578569 Write leveling : PASS
4913 23:35:03.581977 RX DQS gating : PASS
4914 23:35:03.582438 RX DQ/DQS(RDDQC) : PASS
4915 23:35:03.585213 TX DQ/DQS : PASS
4916 23:35:03.585815 RX DATLAT : PASS
4917 23:35:03.588433 RX DQ/DQS(Engine): PASS
4918 23:35:03.591570 TX OE : NO K
4919 23:35:03.592032 All Pass.
4920 23:35:03.592403
4921 23:35:03.595359 DramC Write-DBI off
4922 23:35:03.598364 PER_BANK_REFRESH: Hybrid Mode
4923 23:35:03.598827 TX_TRACKING: ON
4924 23:35:03.608791 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4925 23:35:03.612062 [FAST_K] Save calibration result to emmc
4926 23:35:03.614952 dramc_set_vcore_voltage set vcore to 662500
4927 23:35:03.618078 Read voltage for 933, 3
4928 23:35:03.618541 Vio18 = 0
4929 23:35:03.618913 Vcore = 662500
4930 23:35:03.621416 Vdram = 0
4931 23:35:03.621942 Vddq = 0
4932 23:35:03.622321 Vmddr = 0
4933 23:35:03.627737 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4934 23:35:03.630985 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4935 23:35:03.634750 MEM_TYPE=3, freq_sel=17
4936 23:35:03.638093 sv_algorithm_assistance_LP4_1600
4937 23:35:03.641499 ============ PULL DRAM RESETB DOWN ============
4938 23:35:03.644565 ========== PULL DRAM RESETB DOWN end =========
4939 23:35:03.651517 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4940 23:35:03.654993 ===================================
4941 23:35:03.655561 LPDDR4 DRAM CONFIGURATION
4942 23:35:03.658227 ===================================
4943 23:35:03.661456 EX_ROW_EN[0] = 0x0
4944 23:35:03.664654 EX_ROW_EN[1] = 0x0
4945 23:35:03.665220 LP4Y_EN = 0x0
4946 23:35:03.667616 WORK_FSP = 0x0
4947 23:35:03.668078 WL = 0x3
4948 23:35:03.671532 RL = 0x3
4949 23:35:03.672101 BL = 0x2
4950 23:35:03.674799 RPST = 0x0
4951 23:35:03.675284 RD_PRE = 0x0
4952 23:35:03.678069 WR_PRE = 0x1
4953 23:35:03.678634 WR_PST = 0x0
4954 23:35:03.681272 DBI_WR = 0x0
4955 23:35:03.681878 DBI_RD = 0x0
4956 23:35:03.684177 OTF = 0x1
4957 23:35:03.687314 ===================================
4958 23:35:03.690833 ===================================
4959 23:35:03.691314 ANA top config
4960 23:35:03.694143 ===================================
4961 23:35:03.697889 DLL_ASYNC_EN = 0
4962 23:35:03.701103 ALL_SLAVE_EN = 1
4963 23:35:03.703980 NEW_RANK_MODE = 1
4964 23:35:03.704447 DLL_IDLE_MODE = 1
4965 23:35:03.707813 LP45_APHY_COMB_EN = 1
4966 23:35:03.710844 TX_ODT_DIS = 1
4967 23:35:03.713938 NEW_8X_MODE = 1
4968 23:35:03.717521 ===================================
4969 23:35:03.720964 ===================================
4970 23:35:03.724612 data_rate = 1866
4971 23:35:03.725172 CKR = 1
4972 23:35:03.727243 DQ_P2S_RATIO = 8
4973 23:35:03.730390 ===================================
4974 23:35:03.734136 CA_P2S_RATIO = 8
4975 23:35:03.737215 DQ_CA_OPEN = 0
4976 23:35:03.740588 DQ_SEMI_OPEN = 0
4977 23:35:03.743691 CA_SEMI_OPEN = 0
4978 23:35:03.744252 CA_FULL_RATE = 0
4979 23:35:03.748006 DQ_CKDIV4_EN = 1
4980 23:35:03.751231 CA_CKDIV4_EN = 1
4981 23:35:03.753666 CA_PREDIV_EN = 0
4982 23:35:03.757249 PH8_DLY = 0
4983 23:35:03.760109 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4984 23:35:03.760536 DQ_AAMCK_DIV = 4
4985 23:35:03.763906 CA_AAMCK_DIV = 4
4986 23:35:03.767571 CA_ADMCK_DIV = 4
4987 23:35:03.770108 DQ_TRACK_CA_EN = 0
4988 23:35:03.773307 CA_PICK = 933
4989 23:35:03.776971 CA_MCKIO = 933
4990 23:35:03.777418 MCKIO_SEMI = 0
4991 23:35:03.780436 PLL_FREQ = 3732
4992 23:35:03.783523 DQ_UI_PI_RATIO = 32
4993 23:35:03.786707 CA_UI_PI_RATIO = 0
4994 23:35:03.790637 ===================================
4995 23:35:03.793258 ===================================
4996 23:35:03.797370 memory_type:LPDDR4
4997 23:35:03.797959 GP_NUM : 10
4998 23:35:03.800289 SRAM_EN : 1
4999 23:35:03.803527 MD32_EN : 0
5000 23:35:03.807115 ===================================
5001 23:35:03.807532 [ANA_INIT] >>>>>>>>>>>>>>
5002 23:35:03.809833 <<<<<< [CONFIGURE PHASE]: ANA_TX
5003 23:35:03.813717 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5004 23:35:03.817144 ===================================
5005 23:35:03.820424 data_rate = 1866,PCW = 0X8f00
5006 23:35:03.823766 ===================================
5007 23:35:03.826817 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5008 23:35:03.833204 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5009 23:35:03.836739 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5010 23:35:03.843304 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5011 23:35:03.846398 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5012 23:35:03.850072 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5013 23:35:03.850594 [ANA_INIT] flow start
5014 23:35:03.853547 [ANA_INIT] PLL >>>>>>>>
5015 23:35:03.856787 [ANA_INIT] PLL <<<<<<<<
5016 23:35:03.860266 [ANA_INIT] MIDPI >>>>>>>>
5017 23:35:03.860787 [ANA_INIT] MIDPI <<<<<<<<
5018 23:35:03.863019 [ANA_INIT] DLL >>>>>>>>
5019 23:35:03.863438 [ANA_INIT] flow end
5020 23:35:03.870226 ============ LP4 DIFF to SE enter ============
5021 23:35:03.873358 ============ LP4 DIFF to SE exit ============
5022 23:35:03.876656 [ANA_INIT] <<<<<<<<<<<<<
5023 23:35:03.880055 [Flow] Enable top DCM control >>>>>
5024 23:35:03.883296 [Flow] Enable top DCM control <<<<<
5025 23:35:03.886271 Enable DLL master slave shuffle
5026 23:35:03.889890 ==============================================================
5027 23:35:03.893020 Gating Mode config
5028 23:35:03.897030 ==============================================================
5029 23:35:03.899823 Config description:
5030 23:35:03.910298 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5031 23:35:03.916626 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5032 23:35:03.920214 SELPH_MODE 0: By rank 1: By Phase
5033 23:35:03.926574 ==============================================================
5034 23:35:03.929699 GAT_TRACK_EN = 1
5035 23:35:03.933072 RX_GATING_MODE = 2
5036 23:35:03.936202 RX_GATING_TRACK_MODE = 2
5037 23:35:03.940499 SELPH_MODE = 1
5038 23:35:03.943416 PICG_EARLY_EN = 1
5039 23:35:03.943939 VALID_LAT_VALUE = 1
5040 23:35:03.949753 ==============================================================
5041 23:35:03.953183 Enter into Gating configuration >>>>
5042 23:35:03.956779 Exit from Gating configuration <<<<
5043 23:35:03.959602 Enter into DVFS_PRE_config >>>>>
5044 23:35:03.969859 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5045 23:35:03.973261 Exit from DVFS_PRE_config <<<<<
5046 23:35:03.976690 Enter into PICG configuration >>>>
5047 23:35:03.979982 Exit from PICG configuration <<<<
5048 23:35:03.982939 [RX_INPUT] configuration >>>>>
5049 23:35:03.985997 [RX_INPUT] configuration <<<<<
5050 23:35:03.989553 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5051 23:35:03.996378 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5052 23:35:04.002787 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5053 23:35:04.009441 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5054 23:35:04.016607 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5055 23:35:04.022736 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5056 23:35:04.026506 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5057 23:35:04.029877 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5058 23:35:04.032872 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5059 23:35:04.036382 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5060 23:35:04.042899 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5061 23:35:04.046164 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5062 23:35:04.049846 ===================================
5063 23:35:04.052797 LPDDR4 DRAM CONFIGURATION
5064 23:35:04.056372 ===================================
5065 23:35:04.057001 EX_ROW_EN[0] = 0x0
5066 23:35:04.059470 EX_ROW_EN[1] = 0x0
5067 23:35:04.059933 LP4Y_EN = 0x0
5068 23:35:04.062944 WORK_FSP = 0x0
5069 23:35:04.063513 WL = 0x3
5070 23:35:04.066129 RL = 0x3
5071 23:35:04.066592 BL = 0x2
5072 23:35:04.069434 RPST = 0x0
5073 23:35:04.070058 RD_PRE = 0x0
5074 23:35:04.072694 WR_PRE = 0x1
5075 23:35:04.076322 WR_PST = 0x0
5076 23:35:04.076883 DBI_WR = 0x0
5077 23:35:04.079497 DBI_RD = 0x0
5078 23:35:04.080263 OTF = 0x1
5079 23:35:04.082679 ===================================
5080 23:35:04.086078 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5081 23:35:04.089685 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5082 23:35:04.096235 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5083 23:35:04.099121 ===================================
5084 23:35:04.102636 LPDDR4 DRAM CONFIGURATION
5085 23:35:04.105715 ===================================
5086 23:35:04.106337 EX_ROW_EN[0] = 0x10
5087 23:35:04.108977 EX_ROW_EN[1] = 0x0
5088 23:35:04.109437 LP4Y_EN = 0x0
5089 23:35:04.112618 WORK_FSP = 0x0
5090 23:35:04.113186 WL = 0x3
5091 23:35:04.115660 RL = 0x3
5092 23:35:04.116124 BL = 0x2
5093 23:35:04.119191 RPST = 0x0
5094 23:35:04.119753 RD_PRE = 0x0
5095 23:35:04.122208 WR_PRE = 0x1
5096 23:35:04.122669 WR_PST = 0x0
5097 23:35:04.125721 DBI_WR = 0x0
5098 23:35:04.126191 DBI_RD = 0x0
5099 23:35:04.129283 OTF = 0x1
5100 23:35:04.132785 ===================================
5101 23:35:04.138830 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5102 23:35:04.142774 nWR fixed to 30
5103 23:35:04.145683 [ModeRegInit_LP4] CH0 RK0
5104 23:35:04.146203 [ModeRegInit_LP4] CH0 RK1
5105 23:35:04.149001 [ModeRegInit_LP4] CH1 RK0
5106 23:35:04.152653 [ModeRegInit_LP4] CH1 RK1
5107 23:35:04.153175 match AC timing 9
5108 23:35:04.159259 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5109 23:35:04.162493 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5110 23:35:04.166000 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5111 23:35:04.172258 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5112 23:35:04.175878 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5113 23:35:04.176410 ==
5114 23:35:04.178481 Dram Type= 6, Freq= 0, CH_0, rank 0
5115 23:35:04.182426 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5116 23:35:04.182953 ==
5117 23:35:04.188708 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5118 23:35:04.195870 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5119 23:35:04.198745 [CA 0] Center 37 (6~68) winsize 63
5120 23:35:04.202281 [CA 1] Center 37 (7~68) winsize 62
5121 23:35:04.204867 [CA 2] Center 34 (4~65) winsize 62
5122 23:35:04.208962 [CA 3] Center 34 (3~65) winsize 63
5123 23:35:04.212439 [CA 4] Center 33 (3~64) winsize 62
5124 23:35:04.215425 [CA 5] Center 32 (2~62) winsize 61
5125 23:35:04.215951
5126 23:35:04.218712 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5127 23:35:04.219156
5128 23:35:04.221662 [CATrainingPosCal] consider 1 rank data
5129 23:35:04.225115 u2DelayCellTimex100 = 270/100 ps
5130 23:35:04.228539 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5131 23:35:04.231784 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5132 23:35:04.234985 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5133 23:35:04.238341 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5134 23:35:04.241539 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5135 23:35:04.248323 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5136 23:35:04.248792
5137 23:35:04.251554 CA PerBit enable=1, Macro0, CA PI delay=32
5138 23:35:04.251974
5139 23:35:04.255203 [CBTSetCACLKResult] CA Dly = 32
5140 23:35:04.255735 CS Dly: 5 (0~36)
5141 23:35:04.256077 ==
5142 23:35:04.258307 Dram Type= 6, Freq= 0, CH_0, rank 1
5143 23:35:04.261685 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5144 23:35:04.265381 ==
5145 23:35:04.268761 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5146 23:35:04.274739 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5147 23:35:04.278707 [CA 0] Center 37 (6~68) winsize 63
5148 23:35:04.281885 [CA 1] Center 37 (6~68) winsize 63
5149 23:35:04.285130 [CA 2] Center 34 (4~65) winsize 62
5150 23:35:04.288195 [CA 3] Center 34 (4~64) winsize 61
5151 23:35:04.291961 [CA 4] Center 33 (3~64) winsize 62
5152 23:35:04.294995 [CA 5] Center 32 (2~62) winsize 61
5153 23:35:04.295464
5154 23:35:04.298268 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5155 23:35:04.298734
5156 23:35:04.301640 [CATrainingPosCal] consider 2 rank data
5157 23:35:04.305397 u2DelayCellTimex100 = 270/100 ps
5158 23:35:04.308425 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5159 23:35:04.311772 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5160 23:35:04.314654 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5161 23:35:04.321465 CA3 delay=34 (4~64),Diff = 2 PI (12 cell)
5162 23:35:04.324833 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5163 23:35:04.328570 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5164 23:35:04.329133
5165 23:35:04.331669 CA PerBit enable=1, Macro0, CA PI delay=32
5166 23:35:04.332234
5167 23:35:04.334320 [CBTSetCACLKResult] CA Dly = 32
5168 23:35:04.334894 CS Dly: 5 (0~37)
5169 23:35:04.335292
5170 23:35:04.337766 ----->DramcWriteLeveling(PI) begin...
5171 23:35:04.338239 ==
5172 23:35:04.341557 Dram Type= 6, Freq= 0, CH_0, rank 0
5173 23:35:04.347708 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5174 23:35:04.348171 ==
5175 23:35:04.351189 Write leveling (Byte 0): 32 => 32
5176 23:35:04.354681 Write leveling (Byte 1): 32 => 32
5177 23:35:04.355236 DramcWriteLeveling(PI) end<-----
5178 23:35:04.357772
5179 23:35:04.358325 ==
5180 23:35:04.361198 Dram Type= 6, Freq= 0, CH_0, rank 0
5181 23:35:04.365161 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5182 23:35:04.366053 ==
5183 23:35:04.368200 [Gating] SW mode calibration
5184 23:35:04.374879 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5185 23:35:04.377469 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5186 23:35:04.384921 0 14 0 | B1->B0 | 2727 3434 | 0 1 | (0 0) (1 1)
5187 23:35:04.387760 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5188 23:35:04.390983 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5189 23:35:04.398014 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5190 23:35:04.401299 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5191 23:35:04.404496 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5192 23:35:04.411556 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5193 23:35:04.414089 0 14 28 | B1->B0 | 3333 2525 | 1 0 | (1 1) (0 0)
5194 23:35:04.417846 0 15 0 | B1->B0 | 2e2e 2323 | 0 0 | (0 1) (0 0)
5195 23:35:04.424388 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5196 23:35:04.427735 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5197 23:35:04.430898 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5198 23:35:04.437739 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5199 23:35:04.441693 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5200 23:35:04.444753 0 15 24 | B1->B0 | 2323 2727 | 0 1 | (0 0) (0 0)
5201 23:35:04.450959 0 15 28 | B1->B0 | 2424 3b3b | 0 0 | (0 0) (0 0)
5202 23:35:04.454565 1 0 0 | B1->B0 | 3b3b 4646 | 0 0 | (1 1) (0 0)
5203 23:35:04.457566 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5204 23:35:04.464346 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5205 23:35:04.467535 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5206 23:35:04.471335 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5207 23:35:04.477241 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5208 23:35:04.480862 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5209 23:35:04.484507 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5210 23:35:04.490773 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5211 23:35:04.494209 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5212 23:35:04.497156 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5213 23:35:04.504444 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5214 23:35:04.507443 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5215 23:35:04.510198 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5216 23:35:04.513990 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5217 23:35:04.520679 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5218 23:35:04.524458 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5219 23:35:04.527807 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5220 23:35:04.533819 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5221 23:35:04.537332 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5222 23:35:04.540746 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5223 23:35:04.547160 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5224 23:35:04.550256 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5225 23:35:04.554223 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5226 23:35:04.557773 Total UI for P1: 0, mck2ui 16
5227 23:35:04.560688 best dqsien dly found for B0: ( 1, 2, 24)
5228 23:35:04.567451 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5229 23:35:04.568024 Total UI for P1: 0, mck2ui 16
5230 23:35:04.573809 best dqsien dly found for B1: ( 1, 2, 28)
5231 23:35:04.577301 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5232 23:35:04.580767 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5233 23:35:04.581330
5234 23:35:04.583680 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5235 23:35:04.587061 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5236 23:35:04.590280 [Gating] SW calibration Done
5237 23:35:04.590790 ==
5238 23:35:04.593430 Dram Type= 6, Freq= 0, CH_0, rank 0
5239 23:35:04.596946 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5240 23:35:04.597413 ==
5241 23:35:04.600518 RX Vref Scan: 0
5242 23:35:04.601100
5243 23:35:04.601475 RX Vref 0 -> 0, step: 1
5244 23:35:04.601874
5245 23:35:04.603465 RX Delay -80 -> 252, step: 8
5246 23:35:04.606849 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5247 23:35:04.613603 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5248 23:35:04.616699 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5249 23:35:04.620495 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5250 23:35:04.623923 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5251 23:35:04.626776 iDelay=208, Bit 5, Center 91 (0 ~ 183) 184
5252 23:35:04.630322 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5253 23:35:04.636690 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5254 23:35:04.640121 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5255 23:35:04.643601 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5256 23:35:04.646657 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5257 23:35:04.650206 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5258 23:35:04.653641 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5259 23:35:04.660283 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5260 23:35:04.663282 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5261 23:35:04.667062 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5262 23:35:04.667629 ==
5263 23:35:04.670000 Dram Type= 6, Freq= 0, CH_0, rank 0
5264 23:35:04.673794 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5265 23:35:04.674365 ==
5266 23:35:04.677190 DQS Delay:
5267 23:35:04.677804 DQS0 = 0, DQS1 = 0
5268 23:35:04.680446 DQM Delay:
5269 23:35:04.681011 DQM0 = 105, DQM1 = 94
5270 23:35:04.681388 DQ Delay:
5271 23:35:04.683430 DQ0 =107, DQ1 =107, DQ2 =99, DQ3 =99
5272 23:35:04.686722 DQ4 =107, DQ5 =91, DQ6 =115, DQ7 =115
5273 23:35:04.690303 DQ8 =87, DQ9 =87, DQ10 =95, DQ11 =91
5274 23:35:04.693738 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =99
5275 23:35:04.694310
5276 23:35:04.696412
5277 23:35:04.696875 ==
5278 23:35:04.699785 Dram Type= 6, Freq= 0, CH_0, rank 0
5279 23:35:04.703421 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5280 23:35:04.704253 ==
5281 23:35:04.704657
5282 23:35:04.705010
5283 23:35:04.706524 TX Vref Scan disable
5284 23:35:04.706985 == TX Byte 0 ==
5285 23:35:04.713508 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5286 23:35:04.716348 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5287 23:35:04.716820 == TX Byte 1 ==
5288 23:35:04.723148 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5289 23:35:04.726513 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5290 23:35:04.726982 ==
5291 23:35:04.730170 Dram Type= 6, Freq= 0, CH_0, rank 0
5292 23:35:04.733269 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5293 23:35:04.733883 ==
5294 23:35:04.734388
5295 23:35:04.734864
5296 23:35:04.736487 TX Vref Scan disable
5297 23:35:04.739809 == TX Byte 0 ==
5298 23:35:04.743174 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5299 23:35:04.747008 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5300 23:35:04.749444 == TX Byte 1 ==
5301 23:35:04.752939 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5302 23:35:04.756659 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5303 23:35:04.757192
5304 23:35:04.759504 [DATLAT]
5305 23:35:04.760034 Freq=933, CH0 RK0
5306 23:35:04.760378
5307 23:35:04.762977 DATLAT Default: 0xd
5308 23:35:04.763395 0, 0xFFFF, sum = 0
5309 23:35:04.766532 1, 0xFFFF, sum = 0
5310 23:35:04.767067 2, 0xFFFF, sum = 0
5311 23:35:04.769790 3, 0xFFFF, sum = 0
5312 23:35:04.770328 4, 0xFFFF, sum = 0
5313 23:35:04.772767 5, 0xFFFF, sum = 0
5314 23:35:04.773303 6, 0xFFFF, sum = 0
5315 23:35:04.776029 7, 0xFFFF, sum = 0
5316 23:35:04.776567 8, 0xFFFF, sum = 0
5317 23:35:04.779264 9, 0xFFFF, sum = 0
5318 23:35:04.779799 10, 0x0, sum = 1
5319 23:35:04.782480 11, 0x0, sum = 2
5320 23:35:04.782912 12, 0x0, sum = 3
5321 23:35:04.785839 13, 0x0, sum = 4
5322 23:35:04.786287 best_step = 11
5323 23:35:04.786633
5324 23:35:04.786961 ==
5325 23:35:04.789523 Dram Type= 6, Freq= 0, CH_0, rank 0
5326 23:35:04.796258 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5327 23:35:04.796827 ==
5328 23:35:04.797181 RX Vref Scan: 1
5329 23:35:04.797508
5330 23:35:04.799575 RX Vref 0 -> 0, step: 1
5331 23:35:04.800098
5332 23:35:04.802386 RX Delay -45 -> 252, step: 4
5333 23:35:04.802857
5334 23:35:04.805810 Set Vref, RX VrefLevel [Byte0]: 53
5335 23:35:04.809274 [Byte1]: 55
5336 23:35:04.809955
5337 23:35:04.812992 Final RX Vref Byte 0 = 53 to rank0
5338 23:35:04.815778 Final RX Vref Byte 1 = 55 to rank0
5339 23:35:04.819464 Final RX Vref Byte 0 = 53 to rank1
5340 23:35:04.822865 Final RX Vref Byte 1 = 55 to rank1==
5341 23:35:04.825819 Dram Type= 6, Freq= 0, CH_0, rank 0
5342 23:35:04.829388 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5343 23:35:04.829996 ==
5344 23:35:04.832250 DQS Delay:
5345 23:35:04.832673 DQS0 = 0, DQS1 = 0
5346 23:35:04.833013 DQM Delay:
5347 23:35:04.835611 DQM0 = 104, DQM1 = 96
5348 23:35:04.836032 DQ Delay:
5349 23:35:04.839027 DQ0 =106, DQ1 =106, DQ2 =102, DQ3 =102
5350 23:35:04.842027 DQ4 =106, DQ5 =96, DQ6 =110, DQ7 =110
5351 23:35:04.845457 DQ8 =86, DQ9 =86, DQ10 =96, DQ11 =92
5352 23:35:04.848954 DQ12 =100, DQ13 =100, DQ14 =104, DQ15 =106
5353 23:35:04.852283
5354 23:35:04.852759
5355 23:35:04.858969 [DQSOSCAuto] RK0, (LSB)MR18= 0x2d24, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 407 ps
5356 23:35:04.862553 CH0 RK0: MR19=505, MR18=2D24
5357 23:35:04.869032 CH0_RK0: MR19=0x505, MR18=0x2D24, DQSOSC=407, MR23=63, INC=65, DEC=43
5358 23:35:04.869611
5359 23:35:04.871986 ----->DramcWriteLeveling(PI) begin...
5360 23:35:04.872437 ==
5361 23:35:04.875656 Dram Type= 6, Freq= 0, CH_0, rank 1
5362 23:35:04.878936 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5363 23:35:04.879352 ==
5364 23:35:04.882062 Write leveling (Byte 0): 30 => 30
5365 23:35:04.885261 Write leveling (Byte 1): 29 => 29
5366 23:35:04.888571 DramcWriteLeveling(PI) end<-----
5367 23:35:04.888994
5368 23:35:04.889357 ==
5369 23:35:04.891742 Dram Type= 6, Freq= 0, CH_0, rank 1
5370 23:35:04.895347 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5371 23:35:04.895764 ==
5372 23:35:04.898597 [Gating] SW mode calibration
5373 23:35:04.905613 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5374 23:35:04.911971 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5375 23:35:04.915320 0 14 0 | B1->B0 | 3333 3232 | 1 1 | (1 1) (1 1)
5376 23:35:04.918494 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5377 23:35:04.925704 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5378 23:35:04.928447 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5379 23:35:04.931762 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5380 23:35:04.938179 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5381 23:35:04.941509 0 14 24 | B1->B0 | 3434 3434 | 0 1 | (0 1) (1 0)
5382 23:35:04.945502 0 14 28 | B1->B0 | 2525 2323 | 0 0 | (0 0) (1 0)
5383 23:35:04.952115 0 15 0 | B1->B0 | 2424 2424 | 0 0 | (1 0) (1 0)
5384 23:35:04.955307 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5385 23:35:04.958300 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5386 23:35:04.965203 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5387 23:35:04.968216 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5388 23:35:04.971766 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5389 23:35:04.978537 0 15 24 | B1->B0 | 2626 2525 | 0 0 | (0 0) (0 0)
5390 23:35:04.982012 0 15 28 | B1->B0 | 3d3d 3535 | 0 0 | (0 0) (1 1)
5391 23:35:04.985444 1 0 0 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
5392 23:35:04.991349 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5393 23:35:04.994848 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5394 23:35:04.997907 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5395 23:35:05.005133 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5396 23:35:05.008436 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5397 23:35:05.011746 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5398 23:35:05.018457 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5399 23:35:05.021721 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5400 23:35:05.025092 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5401 23:35:05.031480 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5402 23:35:05.034860 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5403 23:35:05.038337 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5404 23:35:05.044950 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5405 23:35:05.048103 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5406 23:35:05.051664 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5407 23:35:05.058067 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5408 23:35:05.060883 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5409 23:35:05.064801 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5410 23:35:05.071233 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5411 23:35:05.074284 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5412 23:35:05.078422 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5413 23:35:05.084184 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5414 23:35:05.087757 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5415 23:35:05.090916 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5416 23:35:05.094133 Total UI for P1: 0, mck2ui 16
5417 23:35:05.097404 best dqsien dly found for B1: ( 1, 2, 28)
5418 23:35:05.100861 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5419 23:35:05.104300 Total UI for P1: 0, mck2ui 16
5420 23:35:05.107224 best dqsien dly found for B0: ( 1, 2, 30)
5421 23:35:05.111137 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5422 23:35:05.117318 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5423 23:35:05.117898
5424 23:35:05.120733 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5425 23:35:05.124087 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5426 23:35:05.127633 [Gating] SW calibration Done
5427 23:35:05.128167 ==
5428 23:35:05.130959 Dram Type= 6, Freq= 0, CH_0, rank 1
5429 23:35:05.134212 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5430 23:35:05.134643 ==
5431 23:35:05.137055 RX Vref Scan: 0
5432 23:35:05.137474
5433 23:35:05.137852 RX Vref 0 -> 0, step: 1
5434 23:35:05.138175
5435 23:35:05.140132 RX Delay -80 -> 252, step: 8
5436 23:35:05.144223 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5437 23:35:05.150131 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5438 23:35:05.153886 iDelay=208, Bit 2, Center 103 (8 ~ 199) 192
5439 23:35:05.156987 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5440 23:35:05.160281 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5441 23:35:05.163985 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5442 23:35:05.166560 iDelay=208, Bit 6, Center 111 (24 ~ 199) 176
5443 23:35:05.173212 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5444 23:35:05.176573 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5445 23:35:05.179858 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5446 23:35:05.183173 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5447 23:35:05.186510 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5448 23:35:05.190661 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5449 23:35:05.196890 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5450 23:35:05.199950 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5451 23:35:05.203541 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5452 23:35:05.204069 ==
5453 23:35:05.206603 Dram Type= 6, Freq= 0, CH_0, rank 1
5454 23:35:05.210636 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5455 23:35:05.211109 ==
5456 23:35:05.213183 DQS Delay:
5457 23:35:05.213813 DQS0 = 0, DQS1 = 0
5458 23:35:05.216779 DQM Delay:
5459 23:35:05.217202 DQM0 = 104, DQM1 = 93
5460 23:35:05.217542 DQ Delay:
5461 23:35:05.220443 DQ0 =103, DQ1 =107, DQ2 =103, DQ3 =99
5462 23:35:05.223377 DQ4 =107, DQ5 =95, DQ6 =111, DQ7 =111
5463 23:35:05.226982 DQ8 =87, DQ9 =83, DQ10 =91, DQ11 =87
5464 23:35:05.230088 DQ12 =99, DQ13 =99, DQ14 =103, DQ15 =99
5465 23:35:05.234090
5466 23:35:05.234615
5467 23:35:05.234961 ==
5468 23:35:05.236301 Dram Type= 6, Freq= 0, CH_0, rank 1
5469 23:35:05.239931 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5470 23:35:05.240356 ==
5471 23:35:05.240697
5472 23:35:05.241009
5473 23:35:05.243052 TX Vref Scan disable
5474 23:35:05.243472 == TX Byte 0 ==
5475 23:35:05.249920 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5476 23:35:05.253124 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5477 23:35:05.253765 == TX Byte 1 ==
5478 23:35:05.259727 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5479 23:35:05.263126 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5480 23:35:05.263552 ==
5481 23:35:05.266320 Dram Type= 6, Freq= 0, CH_0, rank 1
5482 23:35:05.269523 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5483 23:35:05.270337 ==
5484 23:35:05.270979
5485 23:35:05.271605
5486 23:35:05.272931 TX Vref Scan disable
5487 23:35:05.276737 == TX Byte 0 ==
5488 23:35:05.279687 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5489 23:35:05.283360 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5490 23:35:05.286366 == TX Byte 1 ==
5491 23:35:05.289762 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5492 23:35:05.293182 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5493 23:35:05.293640
5494 23:35:05.296558 [DATLAT]
5495 23:35:05.297096 Freq=933, CH0 RK1
5496 23:35:05.297471
5497 23:35:05.299437 DATLAT Default: 0xb
5498 23:35:05.299856 0, 0xFFFF, sum = 0
5499 23:35:05.303089 1, 0xFFFF, sum = 0
5500 23:35:05.303523 2, 0xFFFF, sum = 0
5501 23:35:05.306037 3, 0xFFFF, sum = 0
5502 23:35:05.306464 4, 0xFFFF, sum = 0
5503 23:35:05.309714 5, 0xFFFF, sum = 0
5504 23:35:05.310144 6, 0xFFFF, sum = 0
5505 23:35:05.312825 7, 0xFFFF, sum = 0
5506 23:35:05.313253 8, 0xFFFF, sum = 0
5507 23:35:05.316138 9, 0xFFFF, sum = 0
5508 23:35:05.316687 10, 0x0, sum = 1
5509 23:35:05.320141 11, 0x0, sum = 2
5510 23:35:05.320676 12, 0x0, sum = 3
5511 23:35:05.323200 13, 0x0, sum = 4
5512 23:35:05.323739 best_step = 11
5513 23:35:05.324083
5514 23:35:05.324398 ==
5515 23:35:05.326157 Dram Type= 6, Freq= 0, CH_0, rank 1
5516 23:35:05.333101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5517 23:35:05.333669 ==
5518 23:35:05.334019 RX Vref Scan: 0
5519 23:35:05.334343
5520 23:35:05.335910 RX Vref 0 -> 0, step: 1
5521 23:35:05.336335
5522 23:35:05.339476 RX Delay -53 -> 252, step: 4
5523 23:35:05.343114 iDelay=199, Bit 0, Center 104 (15 ~ 194) 180
5524 23:35:05.345942 iDelay=199, Bit 1, Center 106 (19 ~ 194) 176
5525 23:35:05.353016 iDelay=199, Bit 2, Center 102 (15 ~ 190) 176
5526 23:35:05.355871 iDelay=199, Bit 3, Center 102 (15 ~ 190) 176
5527 23:35:05.359676 iDelay=199, Bit 4, Center 106 (19 ~ 194) 176
5528 23:35:05.362726 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5529 23:35:05.365901 iDelay=199, Bit 6, Center 110 (27 ~ 194) 168
5530 23:35:05.372940 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5531 23:35:05.376524 iDelay=199, Bit 8, Center 86 (3 ~ 170) 168
5532 23:35:05.379961 iDelay=199, Bit 9, Center 86 (3 ~ 170) 168
5533 23:35:05.383166 iDelay=199, Bit 10, Center 96 (15 ~ 178) 164
5534 23:35:05.386529 iDelay=199, Bit 11, Center 92 (11 ~ 174) 164
5535 23:35:05.389881 iDelay=199, Bit 12, Center 100 (19 ~ 182) 164
5536 23:35:05.396201 iDelay=199, Bit 13, Center 100 (15 ~ 186) 172
5537 23:35:05.399700 iDelay=199, Bit 14, Center 104 (19 ~ 190) 172
5538 23:35:05.402732 iDelay=199, Bit 15, Center 104 (23 ~ 186) 164
5539 23:35:05.403160 ==
5540 23:35:05.406053 Dram Type= 6, Freq= 0, CH_0, rank 1
5541 23:35:05.409693 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5542 23:35:05.413448 ==
5543 23:35:05.414031 DQS Delay:
5544 23:35:05.414379 DQS0 = 0, DQS1 = 0
5545 23:35:05.415842 DQM Delay:
5546 23:35:05.416281 DQM0 = 105, DQM1 = 96
5547 23:35:05.419565 DQ Delay:
5548 23:35:05.422481 DQ0 =104, DQ1 =106, DQ2 =102, DQ3 =102
5549 23:35:05.426029 DQ4 =106, DQ5 =98, DQ6 =110, DQ7 =112
5550 23:35:05.429845 DQ8 =86, DQ9 =86, DQ10 =96, DQ11 =92
5551 23:35:05.432869 DQ12 =100, DQ13 =100, DQ14 =104, DQ15 =104
5552 23:35:05.433293
5553 23:35:05.433682
5554 23:35:05.439713 [DQSOSCAuto] RK1, (LSB)MR18= 0x2a04, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 408 ps
5555 23:35:05.442467 CH0 RK1: MR19=505, MR18=2A04
5556 23:35:05.448931 CH0_RK1: MR19=0x505, MR18=0x2A04, DQSOSC=408, MR23=63, INC=65, DEC=43
5557 23:35:05.452476 [RxdqsGatingPostProcess] freq 933
5558 23:35:05.456204 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5559 23:35:05.459042 best DQS0 dly(2T, 0.5T) = (0, 10)
5560 23:35:05.463117 best DQS1 dly(2T, 0.5T) = (0, 10)
5561 23:35:05.466263 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5562 23:35:05.469385 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5563 23:35:05.473224 best DQS0 dly(2T, 0.5T) = (0, 10)
5564 23:35:05.475992 best DQS1 dly(2T, 0.5T) = (0, 10)
5565 23:35:05.479288 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5566 23:35:05.482739 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5567 23:35:05.486026 Pre-setting of DQS Precalculation
5568 23:35:05.489465 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5569 23:35:05.492480 ==
5570 23:35:05.492907 Dram Type= 6, Freq= 0, CH_1, rank 0
5571 23:35:05.499291 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5572 23:35:05.499829 ==
5573 23:35:05.502114 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5574 23:35:05.509220 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5575 23:35:05.512625 [CA 0] Center 36 (6~67) winsize 62
5576 23:35:05.515977 [CA 1] Center 36 (6~67) winsize 62
5577 23:35:05.519250 [CA 2] Center 34 (4~65) winsize 62
5578 23:35:05.522746 [CA 3] Center 34 (4~65) winsize 62
5579 23:35:05.525983 [CA 4] Center 34 (4~64) winsize 61
5580 23:35:05.529244 [CA 5] Center 33 (3~64) winsize 62
5581 23:35:05.529805
5582 23:35:05.532663 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5583 23:35:05.533227
5584 23:35:05.535956 [CATrainingPosCal] consider 1 rank data
5585 23:35:05.538919 u2DelayCellTimex100 = 270/100 ps
5586 23:35:05.542451 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5587 23:35:05.545795 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5588 23:35:05.552528 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5589 23:35:05.555940 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5590 23:35:05.559167 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5591 23:35:05.563490 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5592 23:35:05.564039
5593 23:35:05.566452 CA PerBit enable=1, Macro0, CA PI delay=33
5594 23:35:05.566869
5595 23:35:05.569198 [CBTSetCACLKResult] CA Dly = 33
5596 23:35:05.569781 CS Dly: 7 (0~38)
5597 23:35:05.570142 ==
5598 23:35:05.572587 Dram Type= 6, Freq= 0, CH_1, rank 1
5599 23:35:05.579114 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5600 23:35:05.579644 ==
5601 23:35:05.582781 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5602 23:35:05.589133 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5603 23:35:05.592324 [CA 0] Center 36 (6~67) winsize 62
5604 23:35:05.596193 [CA 1] Center 37 (6~68) winsize 63
5605 23:35:05.599478 [CA 2] Center 35 (4~66) winsize 63
5606 23:35:05.602404 [CA 3] Center 34 (4~65) winsize 62
5607 23:35:05.605630 [CA 4] Center 34 (4~65) winsize 62
5608 23:35:05.609146 [CA 5] Center 34 (4~64) winsize 61
5609 23:35:05.609567
5610 23:35:05.612110 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5611 23:35:05.612535
5612 23:35:05.615684 [CATrainingPosCal] consider 2 rank data
5613 23:35:05.618972 u2DelayCellTimex100 = 270/100 ps
5614 23:35:05.622562 CA0 delay=36 (6~67),Diff = 2 PI (12 cell)
5615 23:35:05.626090 CA1 delay=36 (6~67),Diff = 2 PI (12 cell)
5616 23:35:05.632130 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
5617 23:35:05.635997 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5618 23:35:05.638732 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5619 23:35:05.642228 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5620 23:35:05.642649
5621 23:35:05.645666 CA PerBit enable=1, Macro0, CA PI delay=34
5622 23:35:05.646202
5623 23:35:05.649147 [CBTSetCACLKResult] CA Dly = 34
5624 23:35:05.649737 CS Dly: 8 (0~40)
5625 23:35:05.650097
5626 23:35:05.655924 ----->DramcWriteLeveling(PI) begin...
5627 23:35:05.656456 ==
5628 23:35:05.659126 Dram Type= 6, Freq= 0, CH_1, rank 0
5629 23:35:05.662158 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5630 23:35:05.662583 ==
5631 23:35:05.665559 Write leveling (Byte 0): 26 => 26
5632 23:35:05.668754 Write leveling (Byte 1): 26 => 26
5633 23:35:05.672358 DramcWriteLeveling(PI) end<-----
5634 23:35:05.672885
5635 23:35:05.673230 ==
5636 23:35:05.675634 Dram Type= 6, Freq= 0, CH_1, rank 0
5637 23:35:05.679089 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5638 23:35:05.679619 ==
5639 23:35:05.682260 [Gating] SW mode calibration
5640 23:35:05.688838 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5641 23:35:05.695725 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5642 23:35:05.698815 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5643 23:35:05.702340 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5644 23:35:05.708630 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5645 23:35:05.712283 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5646 23:35:05.715373 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5647 23:35:05.722278 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5648 23:35:05.725239 0 14 24 | B1->B0 | 3434 2d2d | 0 0 | (0 1) (0 0)
5649 23:35:05.728576 0 14 28 | B1->B0 | 2727 2323 | 0 0 | (1 0) (1 0)
5650 23:35:05.735418 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5651 23:35:05.738458 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5652 23:35:05.741825 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5653 23:35:05.744780 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5654 23:35:05.751834 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5655 23:35:05.754914 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5656 23:35:05.759015 0 15 24 | B1->B0 | 2b2b 3636 | 0 0 | (0 0) (0 0)
5657 23:35:05.765101 0 15 28 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
5658 23:35:05.768630 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5659 23:35:05.772055 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5660 23:35:05.778325 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5661 23:35:05.782533 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5662 23:35:05.785425 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5663 23:35:05.791535 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5664 23:35:05.795203 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5665 23:35:05.799245 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5666 23:35:05.804809 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5667 23:35:05.808301 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5668 23:35:05.811881 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5669 23:35:05.818068 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5670 23:35:05.821472 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5671 23:35:05.824907 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5672 23:35:05.831381 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5673 23:35:05.835084 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5674 23:35:05.838131 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5675 23:35:05.845020 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5676 23:35:05.848372 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5677 23:35:05.851557 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5678 23:35:05.858185 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5679 23:35:05.862121 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5680 23:35:05.864663 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5681 23:35:05.872396 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5682 23:35:05.872966 Total UI for P1: 0, mck2ui 16
5683 23:35:05.875625 best dqsien dly found for B0: ( 1, 2, 24)
5684 23:35:05.878226 Total UI for P1: 0, mck2ui 16
5685 23:35:05.881351 best dqsien dly found for B1: ( 1, 2, 24)
5686 23:35:05.885030 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5687 23:35:05.891428 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5688 23:35:05.891990
5689 23:35:05.894834 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5690 23:35:05.898555 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5691 23:35:05.901397 [Gating] SW calibration Done
5692 23:35:05.902012 ==
5693 23:35:05.904922 Dram Type= 6, Freq= 0, CH_1, rank 0
5694 23:35:05.908375 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5695 23:35:05.908953 ==
5696 23:35:05.911176 RX Vref Scan: 0
5697 23:35:05.911743
5698 23:35:05.912118 RX Vref 0 -> 0, step: 1
5699 23:35:05.912475
5700 23:35:05.914492 RX Delay -80 -> 252, step: 8
5701 23:35:05.917704 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5702 23:35:05.921090 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5703 23:35:05.928295 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5704 23:35:05.930890 iDelay=208, Bit 3, Center 103 (16 ~ 191) 176
5705 23:35:05.934433 iDelay=208, Bit 4, Center 103 (16 ~ 191) 176
5706 23:35:05.937406 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5707 23:35:05.941037 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5708 23:35:05.947609 iDelay=208, Bit 7, Center 107 (16 ~ 199) 184
5709 23:35:05.951333 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5710 23:35:05.954251 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5711 23:35:05.957881 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5712 23:35:05.961010 iDelay=208, Bit 11, Center 95 (8 ~ 183) 176
5713 23:35:05.964331 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5714 23:35:05.971243 iDelay=208, Bit 13, Center 107 (24 ~ 191) 168
5715 23:35:05.974376 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5716 23:35:05.978045 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5717 23:35:05.978615 ==
5718 23:35:05.981037 Dram Type= 6, Freq= 0, CH_1, rank 0
5719 23:35:05.984693 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5720 23:35:05.985268 ==
5721 23:35:05.987184 DQS Delay:
5722 23:35:05.987651 DQS0 = 0, DQS1 = 0
5723 23:35:05.990787 DQM Delay:
5724 23:35:05.991254 DQM0 = 104, DQM1 = 98
5725 23:35:05.994094 DQ Delay:
5726 23:35:05.994562 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =103
5727 23:35:06.000913 DQ4 =103, DQ5 =115, DQ6 =115, DQ7 =107
5728 23:35:06.001488 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =95
5729 23:35:06.007176 DQ12 =107, DQ13 =107, DQ14 =99, DQ15 =107
5730 23:35:06.007648
5731 23:35:06.008027
5732 23:35:06.008377 ==
5733 23:35:06.011441 Dram Type= 6, Freq= 0, CH_1, rank 0
5734 23:35:06.014362 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5735 23:35:06.015040 ==
5736 23:35:06.015435
5737 23:35:06.015789
5738 23:35:06.017129 TX Vref Scan disable
5739 23:35:06.017662 == TX Byte 0 ==
5740 23:35:06.024394 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5741 23:35:06.027679 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5742 23:35:06.028205 == TX Byte 1 ==
5743 23:35:06.034056 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5744 23:35:06.037161 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5745 23:35:06.037735 ==
5746 23:35:06.040866 Dram Type= 6, Freq= 0, CH_1, rank 0
5747 23:35:06.044127 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5748 23:35:06.044650 ==
5749 23:35:06.045000
5750 23:35:06.045316
5751 23:35:06.047133 TX Vref Scan disable
5752 23:35:06.050326 == TX Byte 0 ==
5753 23:35:06.055472 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5754 23:35:06.057431 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5755 23:35:06.060445 == TX Byte 1 ==
5756 23:35:06.063755 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5757 23:35:06.067135 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5758 23:35:06.067660
5759 23:35:06.070090 [DATLAT]
5760 23:35:06.070516 Freq=933, CH1 RK0
5761 23:35:06.070861
5762 23:35:06.073525 DATLAT Default: 0xd
5763 23:35:06.073987 0, 0xFFFF, sum = 0
5764 23:35:06.077142 1, 0xFFFF, sum = 0
5765 23:35:06.077744 2, 0xFFFF, sum = 0
5766 23:35:06.080742 3, 0xFFFF, sum = 0
5767 23:35:06.081284 4, 0xFFFF, sum = 0
5768 23:35:06.083884 5, 0xFFFF, sum = 0
5769 23:35:06.084403 6, 0xFFFF, sum = 0
5770 23:35:06.087293 7, 0xFFFF, sum = 0
5771 23:35:06.090037 8, 0xFFFF, sum = 0
5772 23:35:06.090469 9, 0xFFFF, sum = 0
5773 23:35:06.094106 10, 0x0, sum = 1
5774 23:35:06.094539 11, 0x0, sum = 2
5775 23:35:06.094889 12, 0x0, sum = 3
5776 23:35:06.096718 13, 0x0, sum = 4
5777 23:35:06.097152 best_step = 11
5778 23:35:06.097494
5779 23:35:06.097879 ==
5780 23:35:06.100604 Dram Type= 6, Freq= 0, CH_1, rank 0
5781 23:35:06.107166 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5782 23:35:06.107693 ==
5783 23:35:06.108036 RX Vref Scan: 1
5784 23:35:06.108349
5785 23:35:06.109936 RX Vref 0 -> 0, step: 1
5786 23:35:06.110354
5787 23:35:06.113423 RX Delay -45 -> 252, step: 4
5788 23:35:06.114001
5789 23:35:06.116851 Set Vref, RX VrefLevel [Byte0]: 53
5790 23:35:06.120632 [Byte1]: 54
5791 23:35:06.121191
5792 23:35:06.123657 Final RX Vref Byte 0 = 53 to rank0
5793 23:35:06.127268 Final RX Vref Byte 1 = 54 to rank0
5794 23:35:06.130641 Final RX Vref Byte 0 = 53 to rank1
5795 23:35:06.133703 Final RX Vref Byte 1 = 54 to rank1==
5796 23:35:06.137400 Dram Type= 6, Freq= 0, CH_1, rank 0
5797 23:35:06.141076 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5798 23:35:06.141738 ==
5799 23:35:06.143658 DQS Delay:
5800 23:35:06.144230 DQS0 = 0, DQS1 = 0
5801 23:35:06.146794 DQM Delay:
5802 23:35:06.147272 DQM0 = 103, DQM1 = 100
5803 23:35:06.147646 DQ Delay:
5804 23:35:06.150258 DQ0 =106, DQ1 =96, DQ2 =94, DQ3 =100
5805 23:35:06.153385 DQ4 =102, DQ5 =112, DQ6 =112, DQ7 =102
5806 23:35:06.160375 DQ8 =88, DQ9 =90, DQ10 =100, DQ11 =94
5807 23:35:06.163788 DQ12 =106, DQ13 =108, DQ14 =108, DQ15 =108
5808 23:35:06.164361
5809 23:35:06.164737
5810 23:35:06.170073 [DQSOSCAuto] RK0, (LSB)MR18= 0x152d, (MSB)MR19= 0x505, tDQSOscB0 = 407 ps tDQSOscB1 = 415 ps
5811 23:35:06.173285 CH1 RK0: MR19=505, MR18=152D
5812 23:35:06.179903 CH1_RK0: MR19=0x505, MR18=0x152D, DQSOSC=407, MR23=63, INC=65, DEC=43
5813 23:35:06.180475
5814 23:35:06.183485 ----->DramcWriteLeveling(PI) begin...
5815 23:35:06.184072 ==
5816 23:35:06.186528 Dram Type= 6, Freq= 0, CH_1, rank 1
5817 23:35:06.189896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5818 23:35:06.190404 ==
5819 23:35:06.193076 Write leveling (Byte 0): 27 => 27
5820 23:35:06.196531 Write leveling (Byte 1): 28 => 28
5821 23:35:06.199949 DramcWriteLeveling(PI) end<-----
5822 23:35:06.200540
5823 23:35:06.200918 ==
5824 23:35:06.203176 Dram Type= 6, Freq= 0, CH_1, rank 1
5825 23:35:06.206466 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5826 23:35:06.206936 ==
5827 23:35:06.209756 [Gating] SW mode calibration
5828 23:35:06.216210 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5829 23:35:06.223097 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5830 23:35:06.226554 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5831 23:35:06.233036 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5832 23:35:06.236465 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5833 23:35:06.239774 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5834 23:35:06.246508 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5835 23:35:06.249749 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5836 23:35:06.252635 0 14 24 | B1->B0 | 2f2f 3030 | 1 1 | (1 1) (1 1)
5837 23:35:06.259658 0 14 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (1 0)
5838 23:35:06.262768 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5839 23:35:06.266567 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5840 23:35:06.272915 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5841 23:35:06.276619 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5842 23:35:06.279785 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5843 23:35:06.286147 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5844 23:35:06.289465 0 15 24 | B1->B0 | 3535 2525 | 1 0 | (0 0) (0 0)
5845 23:35:06.292739 0 15 28 | B1->B0 | 4646 4141 | 0 0 | (0 0) (0 0)
5846 23:35:06.296061 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5847 23:35:06.302272 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5848 23:35:06.306460 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5849 23:35:06.309072 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5850 23:35:06.315714 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5851 23:35:06.319440 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5852 23:35:06.322632 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5853 23:35:06.329264 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5854 23:35:06.332572 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5855 23:35:06.336053 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5856 23:35:06.342510 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5857 23:35:06.345701 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5858 23:35:06.349259 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5859 23:35:06.355831 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5860 23:35:06.359134 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5861 23:35:06.362934 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5862 23:35:06.368757 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5863 23:35:06.372592 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5864 23:35:06.375962 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5865 23:35:06.382217 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5866 23:35:06.385538 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5867 23:35:06.389226 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5868 23:35:06.395821 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5869 23:35:06.399020 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5870 23:35:06.402306 Total UI for P1: 0, mck2ui 16
5871 23:35:06.405597 best dqsien dly found for B1: ( 1, 2, 24)
5872 23:35:06.408951 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5873 23:35:06.412432 Total UI for P1: 0, mck2ui 16
5874 23:35:06.415854 best dqsien dly found for B0: ( 1, 2, 26)
5875 23:35:06.418530 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5876 23:35:06.422216 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5877 23:35:06.422807
5878 23:35:06.428986 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5879 23:35:06.432318 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5880 23:35:06.432905 [Gating] SW calibration Done
5881 23:35:06.435298 ==
5882 23:35:06.438372 Dram Type= 6, Freq= 0, CH_1, rank 1
5883 23:35:06.441793 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5884 23:35:06.442376 ==
5885 23:35:06.442785 RX Vref Scan: 0
5886 23:35:06.443264
5887 23:35:06.445262 RX Vref 0 -> 0, step: 1
5888 23:35:06.445796
5889 23:35:06.448293 RX Delay -80 -> 252, step: 8
5890 23:35:06.451724 iDelay=208, Bit 0, Center 111 (24 ~ 199) 176
5891 23:35:06.455165 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5892 23:35:06.458320 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5893 23:35:06.465412 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5894 23:35:06.468284 iDelay=208, Bit 4, Center 95 (8 ~ 183) 176
5895 23:35:06.471560 iDelay=208, Bit 5, Center 119 (32 ~ 207) 176
5896 23:35:06.475123 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5897 23:35:06.478105 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5898 23:35:06.481540 iDelay=208, Bit 8, Center 91 (0 ~ 183) 184
5899 23:35:06.488370 iDelay=208, Bit 9, Center 91 (0 ~ 183) 184
5900 23:35:06.491260 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5901 23:35:06.495314 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5902 23:35:06.498358 iDelay=208, Bit 12, Center 111 (16 ~ 207) 192
5903 23:35:06.501526 iDelay=208, Bit 13, Center 107 (16 ~ 199) 184
5904 23:35:06.505320 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5905 23:35:06.511957 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5906 23:35:06.512552 ==
5907 23:35:06.514869 Dram Type= 6, Freq= 0, CH_1, rank 1
5908 23:35:06.518148 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5909 23:35:06.518676 ==
5910 23:35:06.519171 DQS Delay:
5911 23:35:06.521241 DQS0 = 0, DQS1 = 0
5912 23:35:06.521762 DQM Delay:
5913 23:35:06.524704 DQM0 = 103, DQM1 = 99
5914 23:35:06.525296 DQ Delay:
5915 23:35:06.528081 DQ0 =111, DQ1 =99, DQ2 =91, DQ3 =99
5916 23:35:06.531234 DQ4 =95, DQ5 =119, DQ6 =115, DQ7 =99
5917 23:35:06.534602 DQ8 =91, DQ9 =91, DQ10 =99, DQ11 =91
5918 23:35:06.538240 DQ12 =111, DQ13 =107, DQ14 =99, DQ15 =107
5919 23:35:06.539012
5920 23:35:06.539477
5921 23:35:06.539836 ==
5922 23:35:06.541285 Dram Type= 6, Freq= 0, CH_1, rank 1
5923 23:35:06.548139 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5924 23:35:06.548678 ==
5925 23:35:06.549023
5926 23:35:06.549344
5927 23:35:06.549701 TX Vref Scan disable
5928 23:35:06.551392 == TX Byte 0 ==
5929 23:35:06.554642 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5930 23:35:06.561350 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5931 23:35:06.562021 == TX Byte 1 ==
5932 23:35:06.564954 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5933 23:35:06.571502 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5934 23:35:06.572040 ==
5935 23:35:06.574742 Dram Type= 6, Freq= 0, CH_1, rank 1
5936 23:35:06.577979 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5937 23:35:06.578518 ==
5938 23:35:06.578862
5939 23:35:06.579180
5940 23:35:06.581030 TX Vref Scan disable
5941 23:35:06.581456 == TX Byte 0 ==
5942 23:35:06.587597 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5943 23:35:06.590771 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5944 23:35:06.594146 == TX Byte 1 ==
5945 23:35:06.597875 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5946 23:35:06.600918 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5947 23:35:06.601462
5948 23:35:06.601853 [DATLAT]
5949 23:35:06.604000 Freq=933, CH1 RK1
5950 23:35:06.604518
5951 23:35:06.604880 DATLAT Default: 0xb
5952 23:35:06.607369 0, 0xFFFF, sum = 0
5953 23:35:06.607801 1, 0xFFFF, sum = 0
5954 23:35:06.610842 2, 0xFFFF, sum = 0
5955 23:35:06.614216 3, 0xFFFF, sum = 0
5956 23:35:06.614737 4, 0xFFFF, sum = 0
5957 23:35:06.618041 5, 0xFFFF, sum = 0
5958 23:35:06.618623 6, 0xFFFF, sum = 0
5959 23:35:06.621422 7, 0xFFFF, sum = 0
5960 23:35:06.621900 8, 0xFFFF, sum = 0
5961 23:35:06.624739 9, 0xFFFF, sum = 0
5962 23:35:06.625278 10, 0x0, sum = 1
5963 23:35:06.627366 11, 0x0, sum = 2
5964 23:35:06.628061 12, 0x0, sum = 3
5965 23:35:06.630964 13, 0x0, sum = 4
5966 23:35:06.631508 best_step = 11
5967 23:35:06.631859
5968 23:35:06.632184 ==
5969 23:35:06.633812 Dram Type= 6, Freq= 0, CH_1, rank 1
5970 23:35:06.637400 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5971 23:35:06.637998 ==
5972 23:35:06.640993 RX Vref Scan: 0
5973 23:35:06.641616
5974 23:35:06.643722 RX Vref 0 -> 0, step: 1
5975 23:35:06.644149
5976 23:35:06.644492 RX Delay -45 -> 252, step: 4
5977 23:35:06.651524 iDelay=203, Bit 0, Center 110 (27 ~ 194) 168
5978 23:35:06.655149 iDelay=203, Bit 1, Center 98 (15 ~ 182) 168
5979 23:35:06.658411 iDelay=203, Bit 2, Center 94 (11 ~ 178) 168
5980 23:35:06.661564 iDelay=203, Bit 3, Center 100 (19 ~ 182) 164
5981 23:35:06.665291 iDelay=203, Bit 4, Center 100 (19 ~ 182) 164
5982 23:35:06.671578 iDelay=203, Bit 5, Center 118 (35 ~ 202) 168
5983 23:35:06.675046 iDelay=203, Bit 6, Center 114 (31 ~ 198) 168
5984 23:35:06.678046 iDelay=203, Bit 7, Center 102 (19 ~ 186) 168
5985 23:35:06.682193 iDelay=203, Bit 8, Center 90 (7 ~ 174) 168
5986 23:35:06.685087 iDelay=203, Bit 9, Center 88 (3 ~ 174) 172
5987 23:35:06.688001 iDelay=203, Bit 10, Center 98 (11 ~ 186) 176
5988 23:35:06.695022 iDelay=203, Bit 11, Center 92 (7 ~ 178) 172
5989 23:35:06.698002 iDelay=203, Bit 12, Center 108 (19 ~ 198) 180
5990 23:35:06.701674 iDelay=203, Bit 13, Center 108 (27 ~ 190) 164
5991 23:35:06.705026 iDelay=203, Bit 14, Center 108 (27 ~ 190) 164
5992 23:35:06.711317 iDelay=203, Bit 15, Center 110 (27 ~ 194) 168
5993 23:35:06.711747 ==
5994 23:35:06.714581 Dram Type= 6, Freq= 0, CH_1, rank 1
5995 23:35:06.717782 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5996 23:35:06.718321 ==
5997 23:35:06.718735 DQS Delay:
5998 23:35:06.721286 DQS0 = 0, DQS1 = 0
5999 23:35:06.721877 DQM Delay:
6000 23:35:06.724466 DQM0 = 104, DQM1 = 100
6001 23:35:06.725038 DQ Delay:
6002 23:35:06.728163 DQ0 =110, DQ1 =98, DQ2 =94, DQ3 =100
6003 23:35:06.731900 DQ4 =100, DQ5 =118, DQ6 =114, DQ7 =102
6004 23:35:06.735281 DQ8 =90, DQ9 =88, DQ10 =98, DQ11 =92
6005 23:35:06.738202 DQ12 =108, DQ13 =108, DQ14 =108, DQ15 =110
6006 23:35:06.738740
6007 23:35:06.739139
6008 23:35:06.748017 [DQSOSCAuto] RK1, (LSB)MR18= 0x2afe, (MSB)MR19= 0x504, tDQSOscB0 = 422 ps tDQSOscB1 = 408 ps
6009 23:35:06.748555 CH1 RK1: MR19=504, MR18=2AFE
6010 23:35:06.754300 CH1_RK1: MR19=0x504, MR18=0x2AFE, DQSOSC=408, MR23=63, INC=65, DEC=43
6011 23:35:06.757766 [RxdqsGatingPostProcess] freq 933
6012 23:35:06.764819 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6013 23:35:06.767907 best DQS0 dly(2T, 0.5T) = (0, 10)
6014 23:35:06.771160 best DQS1 dly(2T, 0.5T) = (0, 10)
6015 23:35:06.774390 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6016 23:35:06.778052 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6017 23:35:06.781295 best DQS0 dly(2T, 0.5T) = (0, 10)
6018 23:35:06.784543 best DQS1 dly(2T, 0.5T) = (0, 10)
6019 23:35:06.787705 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6020 23:35:06.790819 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6021 23:35:06.794195 Pre-setting of DQS Precalculation
6022 23:35:06.797238 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6023 23:35:06.804099 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6024 23:35:06.810373 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6025 23:35:06.810842
6026 23:35:06.811359
6027 23:35:06.813730 [Calibration Summary] 1866 Mbps
6028 23:35:06.817209 CH 0, Rank 0
6029 23:35:06.817821 SW Impedance : PASS
6030 23:35:06.820407 DUTY Scan : NO K
6031 23:35:06.823882 ZQ Calibration : PASS
6032 23:35:06.824346 Jitter Meter : NO K
6033 23:35:06.827374 CBT Training : PASS
6034 23:35:06.830247 Write leveling : PASS
6035 23:35:06.830810 RX DQS gating : PASS
6036 23:35:06.833387 RX DQ/DQS(RDDQC) : PASS
6037 23:35:06.837043 TX DQ/DQS : PASS
6038 23:35:06.837662 RX DATLAT : PASS
6039 23:35:06.840016 RX DQ/DQS(Engine): PASS
6040 23:35:06.843188 TX OE : NO K
6041 23:35:06.843657 All Pass.
6042 23:35:06.844033
6043 23:35:06.844381 CH 0, Rank 1
6044 23:35:06.846672 SW Impedance : PASS
6045 23:35:06.850269 DUTY Scan : NO K
6046 23:35:06.850713 ZQ Calibration : PASS
6047 23:35:06.853476 Jitter Meter : NO K
6048 23:35:06.853966 CBT Training : PASS
6049 23:35:06.856672 Write leveling : PASS
6050 23:35:06.860275 RX DQS gating : PASS
6051 23:35:06.860795 RX DQ/DQS(RDDQC) : PASS
6052 23:35:06.863695 TX DQ/DQS : PASS
6053 23:35:06.866552 RX DATLAT : PASS
6054 23:35:06.866990 RX DQ/DQS(Engine): PASS
6055 23:35:06.870174 TX OE : NO K
6056 23:35:06.870736 All Pass.
6057 23:35:06.871289
6058 23:35:06.873333 CH 1, Rank 0
6059 23:35:06.873786 SW Impedance : PASS
6060 23:35:06.876356 DUTY Scan : NO K
6061 23:35:06.880105 ZQ Calibration : PASS
6062 23:35:06.880527 Jitter Meter : NO K
6063 23:35:06.883313 CBT Training : PASS
6064 23:35:06.886575 Write leveling : PASS
6065 23:35:06.887100 RX DQS gating : PASS
6066 23:35:06.889831 RX DQ/DQS(RDDQC) : PASS
6067 23:35:06.893081 TX DQ/DQS : PASS
6068 23:35:06.893504 RX DATLAT : PASS
6069 23:35:06.896444 RX DQ/DQS(Engine): PASS
6070 23:35:06.899907 TX OE : NO K
6071 23:35:06.900432 All Pass.
6072 23:35:06.900774
6073 23:35:06.901085 CH 1, Rank 1
6074 23:35:06.903486 SW Impedance : PASS
6075 23:35:06.906908 DUTY Scan : NO K
6076 23:35:06.907427 ZQ Calibration : PASS
6077 23:35:06.909827 Jitter Meter : NO K
6078 23:35:06.913314 CBT Training : PASS
6079 23:35:06.913868 Write leveling : PASS
6080 23:35:06.916434 RX DQS gating : PASS
6081 23:35:06.916956 RX DQ/DQS(RDDQC) : PASS
6082 23:35:06.919740 TX DQ/DQS : PASS
6083 23:35:06.923110 RX DATLAT : PASS
6084 23:35:06.923571 RX DQ/DQS(Engine): PASS
6085 23:35:06.926678 TX OE : NO K
6086 23:35:06.927238 All Pass.
6087 23:35:06.927608
6088 23:35:06.929780 DramC Write-DBI off
6089 23:35:06.933052 PER_BANK_REFRESH: Hybrid Mode
6090 23:35:06.933673 TX_TRACKING: ON
6091 23:35:06.942931 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6092 23:35:06.946336 [FAST_K] Save calibration result to emmc
6093 23:35:06.949692 dramc_set_vcore_voltage set vcore to 650000
6094 23:35:06.952981 Read voltage for 400, 6
6095 23:35:06.953546 Vio18 = 0
6096 23:35:06.953964 Vcore = 650000
6097 23:35:06.956212 Vdram = 0
6098 23:35:06.956769 Vddq = 0
6099 23:35:06.957140 Vmddr = 0
6100 23:35:06.962603 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6101 23:35:06.966158 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6102 23:35:06.969814 MEM_TYPE=3, freq_sel=20
6103 23:35:06.972797 sv_algorithm_assistance_LP4_800
6104 23:35:06.976638 ============ PULL DRAM RESETB DOWN ============
6105 23:35:06.979500 ========== PULL DRAM RESETB DOWN end =========
6106 23:35:06.986111 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6107 23:35:06.989796 ===================================
6108 23:35:06.993073 LPDDR4 DRAM CONFIGURATION
6109 23:35:06.996060 ===================================
6110 23:35:06.996526 EX_ROW_EN[0] = 0x0
6111 23:35:06.999403 EX_ROW_EN[1] = 0x0
6112 23:35:06.999870 LP4Y_EN = 0x0
6113 23:35:07.002903 WORK_FSP = 0x0
6114 23:35:07.003467 WL = 0x2
6115 23:35:07.006040 RL = 0x2
6116 23:35:07.006505 BL = 0x2
6117 23:35:07.009986 RPST = 0x0
6118 23:35:07.010577 RD_PRE = 0x0
6119 23:35:07.012588 WR_PRE = 0x1
6120 23:35:07.013054 WR_PST = 0x0
6121 23:35:07.016035 DBI_WR = 0x0
6122 23:35:07.016500 DBI_RD = 0x0
6123 23:35:07.019441 OTF = 0x1
6124 23:35:07.022831 ===================================
6125 23:35:07.025810 ===================================
6126 23:35:07.026279 ANA top config
6127 23:35:07.029684 ===================================
6128 23:35:07.033095 DLL_ASYNC_EN = 0
6129 23:35:07.036374 ALL_SLAVE_EN = 1
6130 23:35:07.039618 NEW_RANK_MODE = 1
6131 23:35:07.040185 DLL_IDLE_MODE = 1
6132 23:35:07.042545 LP45_APHY_COMB_EN = 1
6133 23:35:07.046471 TX_ODT_DIS = 1
6134 23:35:07.049858 NEW_8X_MODE = 1
6135 23:35:07.052975 ===================================
6136 23:35:07.055595 ===================================
6137 23:35:07.059688 data_rate = 800
6138 23:35:07.060253 CKR = 1
6139 23:35:07.062811 DQ_P2S_RATIO = 4
6140 23:35:07.065925 ===================================
6141 23:35:07.069687 CA_P2S_RATIO = 4
6142 23:35:07.072870 DQ_CA_OPEN = 0
6143 23:35:07.075987 DQ_SEMI_OPEN = 1
6144 23:35:07.079648 CA_SEMI_OPEN = 1
6145 23:35:07.080215 CA_FULL_RATE = 0
6146 23:35:07.082505 DQ_CKDIV4_EN = 0
6147 23:35:07.085879 CA_CKDIV4_EN = 1
6148 23:35:07.089421 CA_PREDIV_EN = 0
6149 23:35:07.092433 PH8_DLY = 0
6150 23:35:07.096021 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6151 23:35:07.096583 DQ_AAMCK_DIV = 0
6152 23:35:07.099320 CA_AAMCK_DIV = 0
6153 23:35:07.102343 CA_ADMCK_DIV = 4
6154 23:35:07.105684 DQ_TRACK_CA_EN = 0
6155 23:35:07.109233 CA_PICK = 800
6156 23:35:07.112164 CA_MCKIO = 400
6157 23:35:07.115697 MCKIO_SEMI = 400
6158 23:35:07.116165 PLL_FREQ = 3016
6159 23:35:07.119564 DQ_UI_PI_RATIO = 32
6160 23:35:07.122212 CA_UI_PI_RATIO = 32
6161 23:35:07.125691 ===================================
6162 23:35:07.129164 ===================================
6163 23:35:07.132165 memory_type:LPDDR4
6164 23:35:07.135568 GP_NUM : 10
6165 23:35:07.136185 SRAM_EN : 1
6166 23:35:07.139315 MD32_EN : 0
6167 23:35:07.142173 ===================================
6168 23:35:07.142640 [ANA_INIT] >>>>>>>>>>>>>>
6169 23:35:07.146200 <<<<<< [CONFIGURE PHASE]: ANA_TX
6170 23:35:07.149099 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6171 23:35:07.152617 ===================================
6172 23:35:07.155653 data_rate = 800,PCW = 0X7400
6173 23:35:07.159666 ===================================
6174 23:35:07.162172 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6175 23:35:07.169066 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6176 23:35:07.178801 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6177 23:35:07.185514 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6178 23:35:07.188816 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6179 23:35:07.191926 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6180 23:35:07.192397 [ANA_INIT] flow start
6181 23:35:07.195497 [ANA_INIT] PLL >>>>>>>>
6182 23:35:07.198544 [ANA_INIT] PLL <<<<<<<<
6183 23:35:07.199326 [ANA_INIT] MIDPI >>>>>>>>
6184 23:35:07.202547 [ANA_INIT] MIDPI <<<<<<<<
6185 23:35:07.205225 [ANA_INIT] DLL >>>>>>>>
6186 23:35:07.205903 [ANA_INIT] flow end
6187 23:35:07.212144 ============ LP4 DIFF to SE enter ============
6188 23:35:07.215527 ============ LP4 DIFF to SE exit ============
6189 23:35:07.218823 [ANA_INIT] <<<<<<<<<<<<<
6190 23:35:07.221979 [Flow] Enable top DCM control >>>>>
6191 23:35:07.225087 [Flow] Enable top DCM control <<<<<
6192 23:35:07.225652 Enable DLL master slave shuffle
6193 23:35:07.231881 ==============================================================
6194 23:35:07.235301 Gating Mode config
6195 23:35:07.239243 ==============================================================
6196 23:35:07.241706 Config description:
6197 23:35:07.251861 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6198 23:35:07.258377 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6199 23:35:07.261250 SELPH_MODE 0: By rank 1: By Phase
6200 23:35:07.268309 ==============================================================
6201 23:35:07.271928 GAT_TRACK_EN = 0
6202 23:35:07.275092 RX_GATING_MODE = 2
6203 23:35:07.277936 RX_GATING_TRACK_MODE = 2
6204 23:35:07.282144 SELPH_MODE = 1
6205 23:35:07.282709 PICG_EARLY_EN = 1
6206 23:35:07.285237 VALID_LAT_VALUE = 1
6207 23:35:07.291675 ==============================================================
6208 23:35:07.294915 Enter into Gating configuration >>>>
6209 23:35:07.298361 Exit from Gating configuration <<<<
6210 23:35:07.301913 Enter into DVFS_PRE_config >>>>>
6211 23:35:07.311469 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6212 23:35:07.314833 Exit from DVFS_PRE_config <<<<<
6213 23:35:07.317992 Enter into PICG configuration >>>>
6214 23:35:07.321468 Exit from PICG configuration <<<<
6215 23:35:07.324823 [RX_INPUT] configuration >>>>>
6216 23:35:07.327758 [RX_INPUT] configuration <<<<<
6217 23:35:07.331071 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6218 23:35:07.337499 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6219 23:35:07.344117 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6220 23:35:07.350687 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6221 23:35:07.357894 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6222 23:35:07.364067 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6223 23:35:07.368037 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6224 23:35:07.371103 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6225 23:35:07.374282 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6226 23:35:07.380846 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6227 23:35:07.384607 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6228 23:35:07.388072 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6229 23:35:07.390738 ===================================
6230 23:35:07.394174 LPDDR4 DRAM CONFIGURATION
6231 23:35:07.397440 ===================================
6232 23:35:07.398070 EX_ROW_EN[0] = 0x0
6233 23:35:07.401037 EX_ROW_EN[1] = 0x0
6234 23:35:07.401646 LP4Y_EN = 0x0
6235 23:35:07.404438 WORK_FSP = 0x0
6236 23:35:07.404900 WL = 0x2
6237 23:35:07.407433 RL = 0x2
6238 23:35:07.407896 BL = 0x2
6239 23:35:07.410939 RPST = 0x0
6240 23:35:07.413989 RD_PRE = 0x0
6241 23:35:07.414454 WR_PRE = 0x1
6242 23:35:07.418017 WR_PST = 0x0
6243 23:35:07.418499 DBI_WR = 0x0
6244 23:35:07.420971 DBI_RD = 0x0
6245 23:35:07.421409 OTF = 0x1
6246 23:35:07.424637 ===================================
6247 23:35:07.427618 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6248 23:35:07.434020 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6249 23:35:07.437298 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6250 23:35:07.440708 ===================================
6251 23:35:07.443836 LPDDR4 DRAM CONFIGURATION
6252 23:35:07.447197 ===================================
6253 23:35:07.447616 EX_ROW_EN[0] = 0x10
6254 23:35:07.450280 EX_ROW_EN[1] = 0x0
6255 23:35:07.450699 LP4Y_EN = 0x0
6256 23:35:07.454021 WORK_FSP = 0x0
6257 23:35:07.454542 WL = 0x2
6258 23:35:07.457265 RL = 0x2
6259 23:35:07.457740 BL = 0x2
6260 23:35:07.460814 RPST = 0x0
6261 23:35:07.461338 RD_PRE = 0x0
6262 23:35:07.464031 WR_PRE = 0x1
6263 23:35:07.467191 WR_PST = 0x0
6264 23:35:07.467756 DBI_WR = 0x0
6265 23:35:07.470864 DBI_RD = 0x0
6266 23:35:07.471429 OTF = 0x1
6267 23:35:07.473891 ===================================
6268 23:35:07.480751 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6269 23:35:07.484798 nWR fixed to 30
6270 23:35:07.487529 [ModeRegInit_LP4] CH0 RK0
6271 23:35:07.488129 [ModeRegInit_LP4] CH0 RK1
6272 23:35:07.491080 [ModeRegInit_LP4] CH1 RK0
6273 23:35:07.493958 [ModeRegInit_LP4] CH1 RK1
6274 23:35:07.494419 match AC timing 19
6275 23:35:07.500578 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6276 23:35:07.504672 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6277 23:35:07.507404 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6278 23:35:07.513945 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6279 23:35:07.517625 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6280 23:35:07.518203 ==
6281 23:35:07.521017 Dram Type= 6, Freq= 0, CH_0, rank 0
6282 23:35:07.524449 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6283 23:35:07.525011 ==
6284 23:35:07.531045 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6285 23:35:07.537394 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6286 23:35:07.540346 [CA 0] Center 36 (8~64) winsize 57
6287 23:35:07.543936 [CA 1] Center 36 (8~64) winsize 57
6288 23:35:07.547610 [CA 2] Center 36 (8~64) winsize 57
6289 23:35:07.550420 [CA 3] Center 36 (8~64) winsize 57
6290 23:35:07.550948 [CA 4] Center 36 (8~64) winsize 57
6291 23:35:07.553700 [CA 5] Center 36 (8~64) winsize 57
6292 23:35:07.554185
6293 23:35:07.560285 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6294 23:35:07.560784
6295 23:35:07.563661 [CATrainingPosCal] consider 1 rank data
6296 23:35:07.567307 u2DelayCellTimex100 = 270/100 ps
6297 23:35:07.570408 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6298 23:35:07.573993 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6299 23:35:07.577370 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6300 23:35:07.580097 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6301 23:35:07.583935 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6302 23:35:07.587207 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6303 23:35:07.587932
6304 23:35:07.590463 CA PerBit enable=1, Macro0, CA PI delay=36
6305 23:35:07.591061
6306 23:35:07.593444 [CBTSetCACLKResult] CA Dly = 36
6307 23:35:07.597095 CS Dly: 1 (0~32)
6308 23:35:07.597704 ==
6309 23:35:07.600365 Dram Type= 6, Freq= 0, CH_0, rank 1
6310 23:35:07.603589 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6311 23:35:07.604163 ==
6312 23:35:07.610173 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6313 23:35:07.613874 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6314 23:35:07.617217 [CA 0] Center 36 (8~64) winsize 57
6315 23:35:07.620309 [CA 1] Center 36 (8~64) winsize 57
6316 23:35:07.624062 [CA 2] Center 36 (8~64) winsize 57
6317 23:35:07.626786 [CA 3] Center 36 (8~64) winsize 57
6318 23:35:07.630508 [CA 4] Center 36 (8~64) winsize 57
6319 23:35:07.633730 [CA 5] Center 36 (8~64) winsize 57
6320 23:35:07.634451
6321 23:35:07.636948 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6322 23:35:07.637509
6323 23:35:07.640186 [CATrainingPosCal] consider 2 rank data
6324 23:35:07.643943 u2DelayCellTimex100 = 270/100 ps
6325 23:35:07.646845 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6326 23:35:07.650334 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6327 23:35:07.654119 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6328 23:35:07.659961 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6329 23:35:07.663482 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6330 23:35:07.666823 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6331 23:35:07.667394
6332 23:35:07.670329 CA PerBit enable=1, Macro0, CA PI delay=36
6333 23:35:07.670891
6334 23:35:07.673746 [CBTSetCACLKResult] CA Dly = 36
6335 23:35:07.674311 CS Dly: 1 (0~32)
6336 23:35:07.674687
6337 23:35:07.676813 ----->DramcWriteLeveling(PI) begin...
6338 23:35:07.677286 ==
6339 23:35:07.680482 Dram Type= 6, Freq= 0, CH_0, rank 0
6340 23:35:07.686896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6341 23:35:07.687461 ==
6342 23:35:07.690071 Write leveling (Byte 0): 40 => 8
6343 23:35:07.693213 Write leveling (Byte 1): 40 => 8
6344 23:35:07.693735 DramcWriteLeveling(PI) end<-----
6345 23:35:07.694119
6346 23:35:07.696931 ==
6347 23:35:07.699843 Dram Type= 6, Freq= 0, CH_0, rank 0
6348 23:35:07.703144 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6349 23:35:07.703615 ==
6350 23:35:07.706682 [Gating] SW mode calibration
6351 23:35:07.713470 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6352 23:35:07.716311 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6353 23:35:07.723520 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6354 23:35:07.726509 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6355 23:35:07.730362 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6356 23:35:07.736627 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6357 23:35:07.740095 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6358 23:35:07.743139 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6359 23:35:07.749477 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6360 23:35:07.752785 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6361 23:35:07.756195 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6362 23:35:07.759572 Total UI for P1: 0, mck2ui 16
6363 23:35:07.762697 best dqsien dly found for B0: ( 0, 14, 24)
6364 23:35:07.766346 Total UI for P1: 0, mck2ui 16
6365 23:35:07.769473 best dqsien dly found for B1: ( 0, 14, 24)
6366 23:35:07.773014 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6367 23:35:07.776363 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6368 23:35:07.776938
6369 23:35:07.783244 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6370 23:35:07.786178 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6371 23:35:07.789394 [Gating] SW calibration Done
6372 23:35:07.789962 ==
6373 23:35:07.792869 Dram Type= 6, Freq= 0, CH_0, rank 0
6374 23:35:07.795712 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6375 23:35:07.796138 ==
6376 23:35:07.796477 RX Vref Scan: 0
6377 23:35:07.796793
6378 23:35:07.799284 RX Vref 0 -> 0, step: 1
6379 23:35:07.799704
6380 23:35:07.802248 RX Delay -410 -> 252, step: 16
6381 23:35:07.806107 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6382 23:35:07.812732 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6383 23:35:07.816182 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6384 23:35:07.819930 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6385 23:35:07.822840 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6386 23:35:07.829231 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6387 23:35:07.832871 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6388 23:35:07.835824 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6389 23:35:07.838810 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6390 23:35:07.845655 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6391 23:35:07.849391 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6392 23:35:07.852502 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6393 23:35:07.856408 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6394 23:35:07.862247 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6395 23:35:07.865742 iDelay=230, Bit 14, Center -11 (-250 ~ 229) 480
6396 23:35:07.869171 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6397 23:35:07.869796 ==
6398 23:35:07.872503 Dram Type= 6, Freq= 0, CH_0, rank 0
6399 23:35:07.876136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6400 23:35:07.878948 ==
6401 23:35:07.879513 DQS Delay:
6402 23:35:07.879887 DQS0 = 27, DQS1 = 35
6403 23:35:07.882207 DQM Delay:
6404 23:35:07.882664 DQM0 = 10, DQM1 = 12
6405 23:35:07.885780 DQ Delay:
6406 23:35:07.889274 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6407 23:35:07.889885 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6408 23:35:07.892208 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6409 23:35:07.895715 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6410 23:35:07.896175
6411 23:35:07.896542
6412 23:35:07.898880 ==
6413 23:35:07.902331 Dram Type= 6, Freq= 0, CH_0, rank 0
6414 23:35:07.905823 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6415 23:35:07.906377 ==
6416 23:35:07.906748
6417 23:35:07.907234
6418 23:35:07.908627 TX Vref Scan disable
6419 23:35:07.909102 == TX Byte 0 ==
6420 23:35:07.912118 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6421 23:35:07.919195 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6422 23:35:07.919759 == TX Byte 1 ==
6423 23:35:07.922057 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6424 23:35:07.928333 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6425 23:35:07.928908 ==
6426 23:35:07.932109 Dram Type= 6, Freq= 0, CH_0, rank 0
6427 23:35:07.935438 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6428 23:35:07.935999 ==
6429 23:35:07.936369
6430 23:35:07.936717
6431 23:35:07.938133 TX Vref Scan disable
6432 23:35:07.938589 == TX Byte 0 ==
6433 23:35:07.941472 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6434 23:35:07.948377 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6435 23:35:07.948935 == TX Byte 1 ==
6436 23:35:07.951849 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6437 23:35:07.958570 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6438 23:35:07.959051
6439 23:35:07.959634 [DATLAT]
6440 23:35:07.960022 Freq=400, CH0 RK0
6441 23:35:07.960372
6442 23:35:07.961915 DATLAT Default: 0xf
6443 23:35:07.965022 0, 0xFFFF, sum = 0
6444 23:35:07.965638 1, 0xFFFF, sum = 0
6445 23:35:07.968653 2, 0xFFFF, sum = 0
6446 23:35:07.969210 3, 0xFFFF, sum = 0
6447 23:35:07.971655 4, 0xFFFF, sum = 0
6448 23:35:07.972220 5, 0xFFFF, sum = 0
6449 23:35:07.975020 6, 0xFFFF, sum = 0
6450 23:35:07.975587 7, 0xFFFF, sum = 0
6451 23:35:07.978486 8, 0xFFFF, sum = 0
6452 23:35:07.979048 9, 0xFFFF, sum = 0
6453 23:35:07.981991 10, 0xFFFF, sum = 0
6454 23:35:07.982570 11, 0xFFFF, sum = 0
6455 23:35:07.984777 12, 0xFFFF, sum = 0
6456 23:35:07.985339 13, 0x0, sum = 1
6457 23:35:07.988158 14, 0x0, sum = 2
6458 23:35:07.988624 15, 0x0, sum = 3
6459 23:35:07.991434 16, 0x0, sum = 4
6460 23:35:07.991902 best_step = 14
6461 23:35:07.992277
6462 23:35:07.992623 ==
6463 23:35:07.994709 Dram Type= 6, Freq= 0, CH_0, rank 0
6464 23:35:08.001633 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6465 23:35:08.002108 ==
6466 23:35:08.002482 RX Vref Scan: 1
6467 23:35:08.002836
6468 23:35:08.004663 RX Vref 0 -> 0, step: 1
6469 23:35:08.005083
6470 23:35:08.007927 RX Delay -311 -> 252, step: 8
6471 23:35:08.008349
6472 23:35:08.011567 Set Vref, RX VrefLevel [Byte0]: 53
6473 23:35:08.014516 [Byte1]: 55
6474 23:35:08.014940
6475 23:35:08.017960 Final RX Vref Byte 0 = 53 to rank0
6476 23:35:08.021568 Final RX Vref Byte 1 = 55 to rank0
6477 23:35:08.024772 Final RX Vref Byte 0 = 53 to rank1
6478 23:35:08.028649 Final RX Vref Byte 1 = 55 to rank1==
6479 23:35:08.031606 Dram Type= 6, Freq= 0, CH_0, rank 0
6480 23:35:08.034568 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6481 23:35:08.035094 ==
6482 23:35:08.038055 DQS Delay:
6483 23:35:08.038570 DQS0 = 28, DQS1 = 36
6484 23:35:08.041692 DQM Delay:
6485 23:35:08.042227 DQM0 = 11, DQM1 = 13
6486 23:35:08.044723 DQ Delay:
6487 23:35:08.045146 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6488 23:35:08.047978 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6489 23:35:08.051826 DQ8 =0, DQ9 =4, DQ10 =12, DQ11 =4
6490 23:35:08.054253 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6491 23:35:08.054726
6492 23:35:08.055239
6493 23:35:08.064462 [DQSOSCAuto] RK0, (LSB)MR18= 0xc8b5, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 385 ps
6494 23:35:08.067857 CH0 RK0: MR19=C0C, MR18=C8B5
6495 23:35:08.070851 CH0_RK0: MR19=0xC0C, MR18=0xC8B5, DQSOSC=385, MR23=63, INC=398, DEC=265
6496 23:35:08.074377 ==
6497 23:35:08.078096 Dram Type= 6, Freq= 0, CH_0, rank 1
6498 23:35:08.080778 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6499 23:35:08.081332 ==
6500 23:35:08.084359 [Gating] SW mode calibration
6501 23:35:08.090946 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6502 23:35:08.094283 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6503 23:35:08.101374 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6504 23:35:08.104151 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6505 23:35:08.107246 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6506 23:35:08.114591 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6507 23:35:08.117399 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6508 23:35:08.120587 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6509 23:35:08.127724 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6510 23:35:08.130996 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6511 23:35:08.133919 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6512 23:35:08.137221 Total UI for P1: 0, mck2ui 16
6513 23:35:08.140592 best dqsien dly found for B0: ( 0, 14, 24)
6514 23:35:08.144099 Total UI for P1: 0, mck2ui 16
6515 23:35:08.147288 best dqsien dly found for B1: ( 0, 14, 24)
6516 23:35:08.150668 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6517 23:35:08.154546 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6518 23:35:08.155149
6519 23:35:08.161071 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6520 23:35:08.164111 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6521 23:35:08.164695 [Gating] SW calibration Done
6522 23:35:08.167413 ==
6523 23:35:08.171207 Dram Type= 6, Freq= 0, CH_0, rank 1
6524 23:35:08.174213 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6525 23:35:08.174799 ==
6526 23:35:08.175303 RX Vref Scan: 0
6527 23:35:08.175774
6528 23:35:08.177318 RX Vref 0 -> 0, step: 1
6529 23:35:08.177858
6530 23:35:08.181021 RX Delay -410 -> 252, step: 16
6531 23:35:08.184224 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6532 23:35:08.187534 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6533 23:35:08.193886 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6534 23:35:08.197087 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6535 23:35:08.200682 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6536 23:35:08.204204 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6537 23:35:08.210754 iDelay=230, Bit 6, Center 5 (-218 ~ 229) 448
6538 23:35:08.213723 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6539 23:35:08.217196 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6540 23:35:08.220367 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6541 23:35:08.227060 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6542 23:35:08.230318 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6543 23:35:08.233665 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6544 23:35:08.237480 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6545 23:35:08.243797 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6546 23:35:08.246692 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6547 23:35:08.247163 ==
6548 23:35:08.250297 Dram Type= 6, Freq= 0, CH_0, rank 1
6549 23:35:08.253729 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6550 23:35:08.254311 ==
6551 23:35:08.256990 DQS Delay:
6552 23:35:08.257501 DQS0 = 27, DQS1 = 35
6553 23:35:08.260525 DQM Delay:
6554 23:35:08.260989 DQM0 = 14, DQM1 = 11
6555 23:35:08.261365 DQ Delay:
6556 23:35:08.263981 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6557 23:35:08.266895 DQ4 =16, DQ5 =0, DQ6 =32, DQ7 =24
6558 23:35:08.270214 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6559 23:35:08.273820 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6560 23:35:08.274401
6561 23:35:08.274781
6562 23:35:08.275132 ==
6563 23:35:08.276818 Dram Type= 6, Freq= 0, CH_0, rank 1
6564 23:35:08.283599 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6565 23:35:08.284175 ==
6566 23:35:08.284552
6567 23:35:08.284906
6568 23:35:08.285238 TX Vref Scan disable
6569 23:35:08.286874 == TX Byte 0 ==
6570 23:35:08.290521 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6571 23:35:08.293387 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6572 23:35:08.296969 == TX Byte 1 ==
6573 23:35:08.300598 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6574 23:35:08.303613 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6575 23:35:08.304185 ==
6576 23:35:08.306460 Dram Type= 6, Freq= 0, CH_0, rank 1
6577 23:35:08.313687 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6578 23:35:08.314263 ==
6579 23:35:08.314642
6580 23:35:08.315030
6581 23:35:08.315536 TX Vref Scan disable
6582 23:35:08.316737 == TX Byte 0 ==
6583 23:35:08.320435 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6584 23:35:08.323228 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6585 23:35:08.326761 == TX Byte 1 ==
6586 23:35:08.330083 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6587 23:35:08.333454 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6588 23:35:08.334311
6589 23:35:08.336801 [DATLAT]
6590 23:35:08.337266 Freq=400, CH0 RK1
6591 23:35:08.337690
6592 23:35:08.340029 DATLAT Default: 0xe
6593 23:35:08.340495 0, 0xFFFF, sum = 0
6594 23:35:08.343787 1, 0xFFFF, sum = 0
6595 23:35:08.344364 2, 0xFFFF, sum = 0
6596 23:35:08.346690 3, 0xFFFF, sum = 0
6597 23:35:08.347166 4, 0xFFFF, sum = 0
6598 23:35:08.350219 5, 0xFFFF, sum = 0
6599 23:35:08.350695 6, 0xFFFF, sum = 0
6600 23:35:08.352906 7, 0xFFFF, sum = 0
6601 23:35:08.353382 8, 0xFFFF, sum = 0
6602 23:35:08.356483 9, 0xFFFF, sum = 0
6603 23:35:08.356913 10, 0xFFFF, sum = 0
6604 23:35:08.360032 11, 0xFFFF, sum = 0
6605 23:35:08.363323 12, 0xFFFF, sum = 0
6606 23:35:08.363790 13, 0x0, sum = 1
6607 23:35:08.364147 14, 0x0, sum = 2
6608 23:35:08.366167 15, 0x0, sum = 3
6609 23:35:08.366598 16, 0x0, sum = 4
6610 23:35:08.369920 best_step = 14
6611 23:35:08.370346
6612 23:35:08.370685 ==
6613 23:35:08.373519 Dram Type= 6, Freq= 0, CH_0, rank 1
6614 23:35:08.376264 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6615 23:35:08.376698 ==
6616 23:35:08.379817 RX Vref Scan: 0
6617 23:35:08.380250
6618 23:35:08.380591 RX Vref 0 -> 0, step: 1
6619 23:35:08.383139
6620 23:35:08.383564 RX Delay -311 -> 252, step: 8
6621 23:35:08.391382 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6622 23:35:08.394661 iDelay=217, Bit 1, Center -12 (-231 ~ 208) 440
6623 23:35:08.397572 iDelay=217, Bit 2, Center -20 (-247 ~ 208) 456
6624 23:35:08.404859 iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448
6625 23:35:08.407722 iDelay=217, Bit 4, Center -12 (-239 ~ 216) 456
6626 23:35:08.411399 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6627 23:35:08.414594 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6628 23:35:08.417514 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6629 23:35:08.424820 iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448
6630 23:35:08.427692 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6631 23:35:08.431108 iDelay=217, Bit 10, Center -20 (-239 ~ 200) 440
6632 23:35:08.437738 iDelay=217, Bit 11, Center -32 (-255 ~ 192) 448
6633 23:35:08.441029 iDelay=217, Bit 12, Center -16 (-239 ~ 208) 448
6634 23:35:08.444307 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
6635 23:35:08.447896 iDelay=217, Bit 14, Center -12 (-231 ~ 208) 440
6636 23:35:08.454291 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6637 23:35:08.455075 ==
6638 23:35:08.457642 Dram Type= 6, Freq= 0, CH_0, rank 1
6639 23:35:08.461084 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6640 23:35:08.461735 ==
6641 23:35:08.462128 DQS Delay:
6642 23:35:08.464484 DQS0 = 24, DQS1 = 32
6643 23:35:08.465053 DQM Delay:
6644 23:35:08.467952 DQM0 = 9, DQM1 = 10
6645 23:35:08.468531 DQ Delay:
6646 23:35:08.471156 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =8
6647 23:35:08.474185 DQ4 =12, DQ5 =0, DQ6 =12, DQ7 =16
6648 23:35:08.477384 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =0
6649 23:35:08.480767 DQ12 =16, DQ13 =16, DQ14 =20, DQ15 =16
6650 23:35:08.481360
6651 23:35:08.481846
6652 23:35:08.487441 [DQSOSCAuto] RK1, (LSB)MR18= 0xbb5c, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 386 ps
6653 23:35:08.490933 CH0 RK1: MR19=C0C, MR18=BB5C
6654 23:35:08.497444 CH0_RK1: MR19=0xC0C, MR18=0xBB5C, DQSOSC=386, MR23=63, INC=396, DEC=264
6655 23:35:08.500461 [RxdqsGatingPostProcess] freq 400
6656 23:35:08.507300 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6657 23:35:08.510986 best DQS0 dly(2T, 0.5T) = (0, 10)
6658 23:35:08.511566 best DQS1 dly(2T, 0.5T) = (0, 10)
6659 23:35:08.514201 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6660 23:35:08.516962 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6661 23:35:08.520836 best DQS0 dly(2T, 0.5T) = (0, 10)
6662 23:35:08.524270 best DQS1 dly(2T, 0.5T) = (0, 10)
6663 23:35:08.527535 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6664 23:35:08.530406 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6665 23:35:08.533546 Pre-setting of DQS Precalculation
6666 23:35:08.540790 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6667 23:35:08.541366 ==
6668 23:35:08.544045 Dram Type= 6, Freq= 0, CH_1, rank 0
6669 23:35:08.546913 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6670 23:35:08.547384 ==
6671 23:35:08.554072 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6672 23:35:08.557069 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6673 23:35:08.560528 [CA 0] Center 36 (8~64) winsize 57
6674 23:35:08.563632 [CA 1] Center 36 (8~64) winsize 57
6675 23:35:08.567009 [CA 2] Center 36 (8~64) winsize 57
6676 23:35:08.570218 [CA 3] Center 36 (8~64) winsize 57
6677 23:35:08.573648 [CA 4] Center 36 (8~64) winsize 57
6678 23:35:08.576852 [CA 5] Center 36 (8~64) winsize 57
6679 23:35:08.577422
6680 23:35:08.580400 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6681 23:35:08.580983
6682 23:35:08.583633 [CATrainingPosCal] consider 1 rank data
6683 23:35:08.587298 u2DelayCellTimex100 = 270/100 ps
6684 23:35:08.590353 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6685 23:35:08.593533 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6686 23:35:08.596973 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6687 23:35:08.603793 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6688 23:35:08.606689 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6689 23:35:08.610319 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6690 23:35:08.610893
6691 23:35:08.613434 CA PerBit enable=1, Macro0, CA PI delay=36
6692 23:35:08.613952
6693 23:35:08.616698 [CBTSetCACLKResult] CA Dly = 36
6694 23:35:08.617164 CS Dly: 1 (0~32)
6695 23:35:08.617539 ==
6696 23:35:08.619894 Dram Type= 6, Freq= 0, CH_1, rank 1
6697 23:35:08.626494 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6698 23:35:08.627068 ==
6699 23:35:08.630074 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6700 23:35:08.636435 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6701 23:35:08.639997 [CA 0] Center 36 (8~64) winsize 57
6702 23:35:08.642892 [CA 1] Center 36 (8~64) winsize 57
6703 23:35:08.646816 [CA 2] Center 36 (8~64) winsize 57
6704 23:35:08.650228 [CA 3] Center 36 (8~64) winsize 57
6705 23:35:08.653557 [CA 4] Center 36 (8~64) winsize 57
6706 23:35:08.656656 [CA 5] Center 36 (8~64) winsize 57
6707 23:35:08.657232
6708 23:35:08.659868 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6709 23:35:08.660333
6710 23:35:08.663047 [CATrainingPosCal] consider 2 rank data
6711 23:35:08.666575 u2DelayCellTimex100 = 270/100 ps
6712 23:35:08.669755 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6713 23:35:08.673131 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6714 23:35:08.677015 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6715 23:35:08.679768 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6716 23:35:08.683563 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6717 23:35:08.686184 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6718 23:35:08.689649
6719 23:35:08.693169 CA PerBit enable=1, Macro0, CA PI delay=36
6720 23:35:08.693682
6721 23:35:08.696137 [CBTSetCACLKResult] CA Dly = 36
6722 23:35:08.696598 CS Dly: 1 (0~32)
6723 23:35:08.696976
6724 23:35:08.699923 ----->DramcWriteLeveling(PI) begin...
6725 23:35:08.700396 ==
6726 23:35:08.703072 Dram Type= 6, Freq= 0, CH_1, rank 0
6727 23:35:08.706610 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6728 23:35:08.707039 ==
6729 23:35:08.709547 Write leveling (Byte 0): 40 => 8
6730 23:35:08.713756 Write leveling (Byte 1): 40 => 8
6731 23:35:08.716102 DramcWriteLeveling(PI) end<-----
6732 23:35:08.716558
6733 23:35:08.716894 ==
6734 23:35:08.719496 Dram Type= 6, Freq= 0, CH_1, rank 0
6735 23:35:08.722921 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6736 23:35:08.726706 ==
6737 23:35:08.727276 [Gating] SW mode calibration
6738 23:35:08.732958 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6739 23:35:08.740294 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6740 23:35:08.743308 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6741 23:35:08.750272 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6742 23:35:08.753720 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6743 23:35:08.756736 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6744 23:35:08.763147 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6745 23:35:08.766423 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6746 23:35:08.769784 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6747 23:35:08.776294 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6748 23:35:08.779591 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6749 23:35:08.782753 Total UI for P1: 0, mck2ui 16
6750 23:35:08.786544 best dqsien dly found for B0: ( 0, 14, 24)
6751 23:35:08.789433 Total UI for P1: 0, mck2ui 16
6752 23:35:08.792854 best dqsien dly found for B1: ( 0, 14, 24)
6753 23:35:08.796132 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6754 23:35:08.799561 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6755 23:35:08.800133
6756 23:35:08.802617 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6757 23:35:08.806429 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6758 23:35:08.809260 [Gating] SW calibration Done
6759 23:35:08.809765 ==
6760 23:35:08.813117 Dram Type= 6, Freq= 0, CH_1, rank 0
6761 23:35:08.819660 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6762 23:35:08.820136 ==
6763 23:35:08.820616 RX Vref Scan: 0
6764 23:35:08.820981
6765 23:35:08.822999 RX Vref 0 -> 0, step: 1
6766 23:35:08.823462
6767 23:35:08.825747 RX Delay -410 -> 252, step: 16
6768 23:35:08.829296 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6769 23:35:08.832224 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6770 23:35:08.836347 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6771 23:35:08.842613 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6772 23:35:08.845734 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6773 23:35:08.849237 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6774 23:35:08.852574 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6775 23:35:08.858918 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6776 23:35:08.862205 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6777 23:35:08.865303 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6778 23:35:08.869407 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6779 23:35:08.876006 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6780 23:35:08.878789 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6781 23:35:08.882202 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6782 23:35:08.889433 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6783 23:35:08.892713 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6784 23:35:08.893279 ==
6785 23:35:08.895127 Dram Type= 6, Freq= 0, CH_1, rank 0
6786 23:35:08.898794 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6787 23:35:08.899262 ==
6788 23:35:08.902021 DQS Delay:
6789 23:35:08.902483 DQS0 = 35, DQS1 = 35
6790 23:35:08.902857 DQM Delay:
6791 23:35:08.906034 DQM0 = 17, DQM1 = 13
6792 23:35:08.906606 DQ Delay:
6793 23:35:08.908611 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =16
6794 23:35:08.911926 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6795 23:35:08.914995 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6796 23:35:08.918673 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6797 23:35:08.919143
6798 23:35:08.919515
6799 23:35:08.919861 ==
6800 23:35:08.921677 Dram Type= 6, Freq= 0, CH_1, rank 0
6801 23:35:08.925523 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6802 23:35:08.928331 ==
6803 23:35:08.928797
6804 23:35:08.929196
6805 23:35:08.929574 TX Vref Scan disable
6806 23:35:08.932325 == TX Byte 0 ==
6807 23:35:08.935547 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6808 23:35:08.938609 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6809 23:35:08.942111 == TX Byte 1 ==
6810 23:35:08.945893 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6811 23:35:08.948287 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6812 23:35:08.948756 ==
6813 23:35:08.951553 Dram Type= 6, Freq= 0, CH_1, rank 0
6814 23:35:08.958705 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6815 23:35:08.959362 ==
6816 23:35:08.959750
6817 23:35:08.960102
6818 23:35:08.960432 TX Vref Scan disable
6819 23:35:08.961488 == TX Byte 0 ==
6820 23:35:08.965547 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6821 23:35:08.968302 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6822 23:35:08.971884 == TX Byte 1 ==
6823 23:35:08.975489 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6824 23:35:08.978376 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6825 23:35:08.978850
6826 23:35:08.981365 [DATLAT]
6827 23:35:08.981876 Freq=400, CH1 RK0
6828 23:35:08.982259
6829 23:35:08.984963 DATLAT Default: 0xf
6830 23:35:08.985431 0, 0xFFFF, sum = 0
6831 23:35:08.988352 1, 0xFFFF, sum = 0
6832 23:35:08.988931 2, 0xFFFF, sum = 0
6833 23:35:08.991735 3, 0xFFFF, sum = 0
6834 23:35:08.992230 4, 0xFFFF, sum = 0
6835 23:35:08.995282 5, 0xFFFF, sum = 0
6836 23:35:08.995756 6, 0xFFFF, sum = 0
6837 23:35:08.998210 7, 0xFFFF, sum = 0
6838 23:35:08.998741 8, 0xFFFF, sum = 0
6839 23:35:09.001295 9, 0xFFFF, sum = 0
6840 23:35:09.001795 10, 0xFFFF, sum = 0
6841 23:35:09.005230 11, 0xFFFF, sum = 0
6842 23:35:09.007926 12, 0xFFFF, sum = 0
6843 23:35:09.008398 13, 0x0, sum = 1
6844 23:35:09.008780 14, 0x0, sum = 2
6845 23:35:09.011554 15, 0x0, sum = 3
6846 23:35:09.012137 16, 0x0, sum = 4
6847 23:35:09.014535 best_step = 14
6848 23:35:09.015001
6849 23:35:09.015372 ==
6850 23:35:09.018042 Dram Type= 6, Freq= 0, CH_1, rank 0
6851 23:35:09.021167 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6852 23:35:09.021670 ==
6853 23:35:09.024973 RX Vref Scan: 1
6854 23:35:09.025541
6855 23:35:09.025970 RX Vref 0 -> 0, step: 1
6856 23:35:09.026327
6857 23:35:09.028725 RX Delay -311 -> 252, step: 8
6858 23:35:09.029298
6859 23:35:09.031131 Set Vref, RX VrefLevel [Byte0]: 53
6860 23:35:09.034909 [Byte1]: 54
6861 23:35:09.039744
6862 23:35:09.040316 Final RX Vref Byte 0 = 53 to rank0
6863 23:35:09.042868 Final RX Vref Byte 1 = 54 to rank0
6864 23:35:09.046364 Final RX Vref Byte 0 = 53 to rank1
6865 23:35:09.049844 Final RX Vref Byte 1 = 54 to rank1==
6866 23:35:09.053133 Dram Type= 6, Freq= 0, CH_1, rank 0
6867 23:35:09.059351 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6868 23:35:09.059984 ==
6869 23:35:09.060374 DQS Delay:
6870 23:35:09.062971 DQS0 = 32, DQS1 = 32
6871 23:35:09.063548 DQM Delay:
6872 23:35:09.063931 DQM0 = 13, DQM1 = 11
6873 23:35:09.066076 DQ Delay:
6874 23:35:09.069954 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6875 23:35:09.073071 DQ4 =16, DQ5 =24, DQ6 =20, DQ7 =12
6876 23:35:09.073713 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6877 23:35:09.076210 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
6878 23:35:09.079565
6879 23:35:09.080030
6880 23:35:09.085855 [DQSOSCAuto] RK0, (LSB)MR18= 0x8dc6, (MSB)MR19= 0xc0c, tDQSOscB0 = 385 ps tDQSOscB1 = 392 ps
6881 23:35:09.089069 CH1 RK0: MR19=C0C, MR18=8DC6
6882 23:35:09.095881 CH1_RK0: MR19=0xC0C, MR18=0x8DC6, DQSOSC=385, MR23=63, INC=398, DEC=265
6883 23:35:09.096449 ==
6884 23:35:09.099035 Dram Type= 6, Freq= 0, CH_1, rank 1
6885 23:35:09.102596 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6886 23:35:09.103066 ==
6887 23:35:09.106072 [Gating] SW mode calibration
6888 23:35:09.112445 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6889 23:35:09.119135 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6890 23:35:09.122113 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6891 23:35:09.125409 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6892 23:35:09.132607 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6893 23:35:09.135222 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6894 23:35:09.138901 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6895 23:35:09.145764 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6896 23:35:09.148398 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6897 23:35:09.151854 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6898 23:35:09.158548 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6899 23:35:09.159127 Total UI for P1: 0, mck2ui 16
6900 23:35:09.165196 best dqsien dly found for B0: ( 0, 14, 24)
6901 23:35:09.165824 Total UI for P1: 0, mck2ui 16
6902 23:35:09.172144 best dqsien dly found for B1: ( 0, 14, 24)
6903 23:35:09.175067 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6904 23:35:09.178372 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6905 23:35:09.178951
6906 23:35:09.181962 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6907 23:35:09.185264 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6908 23:35:09.188639 [Gating] SW calibration Done
6909 23:35:09.189163 ==
6910 23:35:09.191594 Dram Type= 6, Freq= 0, CH_1, rank 1
6911 23:35:09.195278 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6912 23:35:09.196021 ==
6913 23:35:09.197949 RX Vref Scan: 0
6914 23:35:09.198435
6915 23:35:09.199004 RX Vref 0 -> 0, step: 1
6916 23:35:09.199377
6917 23:35:09.201475 RX Delay -410 -> 252, step: 16
6918 23:35:09.208449 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6919 23:35:09.211224 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6920 23:35:09.215334 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6921 23:35:09.217875 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6922 23:35:09.225253 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6923 23:35:09.228285 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6924 23:35:09.231313 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6925 23:35:09.234698 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6926 23:35:09.241755 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6927 23:35:09.244735 iDelay=230, Bit 9, Center -27 (-266 ~ 213) 480
6928 23:35:09.248539 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6929 23:35:09.251871 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6930 23:35:09.257928 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6931 23:35:09.260882 iDelay=230, Bit 13, Center -11 (-250 ~ 229) 480
6932 23:35:09.265117 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6933 23:35:09.267971 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6934 23:35:09.271786 ==
6935 23:35:09.274656 Dram Type= 6, Freq= 0, CH_1, rank 1
6936 23:35:09.277937 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6937 23:35:09.278520 ==
6938 23:35:09.278904 DQS Delay:
6939 23:35:09.281322 DQS0 = 35, DQS1 = 35
6940 23:35:09.281964 DQM Delay:
6941 23:35:09.284528 DQM0 = 17, DQM1 = 15
6942 23:35:09.285102 DQ Delay:
6943 23:35:09.287695 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6944 23:35:09.291224 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6945 23:35:09.294124 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6946 23:35:09.297762 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =24
6947 23:35:09.298235
6948 23:35:09.298610
6949 23:35:09.299133 ==
6950 23:35:09.300822 Dram Type= 6, Freq= 0, CH_1, rank 1
6951 23:35:09.304381 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6952 23:35:09.304979 ==
6953 23:35:09.305360
6954 23:35:09.305764
6955 23:35:09.307790 TX Vref Scan disable
6956 23:35:09.308366 == TX Byte 0 ==
6957 23:35:09.314330 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6958 23:35:09.317409 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6959 23:35:09.318019 == TX Byte 1 ==
6960 23:35:09.324025 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6961 23:35:09.327313 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6962 23:35:09.327787 ==
6963 23:35:09.330952 Dram Type= 6, Freq= 0, CH_1, rank 1
6964 23:35:09.333887 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6965 23:35:09.334365 ==
6966 23:35:09.334742
6967 23:35:09.335089
6968 23:35:09.337559 TX Vref Scan disable
6969 23:35:09.338142 == TX Byte 0 ==
6970 23:35:09.344803 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6971 23:35:09.347443 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6972 23:35:09.347917 == TX Byte 1 ==
6973 23:35:09.354372 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6974 23:35:09.357656 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6975 23:35:09.358249
6976 23:35:09.358645 [DATLAT]
6977 23:35:09.361145 Freq=400, CH1 RK1
6978 23:35:09.361760
6979 23:35:09.362145 DATLAT Default: 0xe
6980 23:35:09.364130 0, 0xFFFF, sum = 0
6981 23:35:09.364713 1, 0xFFFF, sum = 0
6982 23:35:09.367282 2, 0xFFFF, sum = 0
6983 23:35:09.367769 3, 0xFFFF, sum = 0
6984 23:35:09.370602 4, 0xFFFF, sum = 0
6985 23:35:09.371184 5, 0xFFFF, sum = 0
6986 23:35:09.373968 6, 0xFFFF, sum = 0
6987 23:35:09.377327 7, 0xFFFF, sum = 0
6988 23:35:09.377881 8, 0xFFFF, sum = 0
6989 23:35:09.380896 9, 0xFFFF, sum = 0
6990 23:35:09.381368 10, 0xFFFF, sum = 0
6991 23:35:09.383591 11, 0xFFFF, sum = 0
6992 23:35:09.384064 12, 0xFFFF, sum = 0
6993 23:35:09.387494 13, 0x0, sum = 1
6994 23:35:09.387969 14, 0x0, sum = 2
6995 23:35:09.390296 15, 0x0, sum = 3
6996 23:35:09.390813 16, 0x0, sum = 4
6997 23:35:09.391190 best_step = 14
6998 23:35:09.393573
6999 23:35:09.394028 ==
7000 23:35:09.396851 Dram Type= 6, Freq= 0, CH_1, rank 1
7001 23:35:09.400218 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7002 23:35:09.400646 ==
7003 23:35:09.400985 RX Vref Scan: 0
7004 23:35:09.401307
7005 23:35:09.403500 RX Vref 0 -> 0, step: 1
7006 23:35:09.403924
7007 23:35:09.407632 RX Delay -311 -> 252, step: 8
7008 23:35:09.414524 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
7009 23:35:09.417436 iDelay=217, Bit 1, Center -20 (-239 ~ 200) 440
7010 23:35:09.421266 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
7011 23:35:09.424306 iDelay=217, Bit 3, Center -20 (-239 ~ 200) 440
7012 23:35:09.431240 iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440
7013 23:35:09.433907 iDelay=217, Bit 5, Center -4 (-223 ~ 216) 440
7014 23:35:09.437678 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
7015 23:35:09.440782 iDelay=217, Bit 7, Center -20 (-239 ~ 200) 440
7016 23:35:09.447759 iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448
7017 23:35:09.450719 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
7018 23:35:09.454172 iDelay=217, Bit 10, Center -16 (-239 ~ 208) 448
7019 23:35:09.457749 iDelay=217, Bit 11, Center -28 (-255 ~ 200) 456
7020 23:35:09.463774 iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456
7021 23:35:09.467369 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
7022 23:35:09.470823 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
7023 23:35:09.474179 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
7024 23:35:09.477617 ==
7025 23:35:09.480593 Dram Type= 6, Freq= 0, CH_1, rank 1
7026 23:35:09.484276 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7027 23:35:09.484810 ==
7028 23:35:09.485158 DQS Delay:
7029 23:35:09.487358 DQS0 = 28, DQS1 = 32
7030 23:35:09.487785 DQM Delay:
7031 23:35:09.490836 DQM0 = 11, DQM1 = 11
7032 23:35:09.491370 DQ Delay:
7033 23:35:09.493934 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
7034 23:35:09.497615 DQ4 =8, DQ5 =24, DQ6 =20, DQ7 =8
7035 23:35:09.501109 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
7036 23:35:09.503739 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =20
7037 23:35:09.504166
7038 23:35:09.504505
7039 23:35:09.510561 [DQSOSCAuto] RK1, (LSB)MR18= 0xbe50, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 386 ps
7040 23:35:09.513685 CH1 RK1: MR19=C0C, MR18=BE50
7041 23:35:09.520214 CH1_RK1: MR19=0xC0C, MR18=0xBE50, DQSOSC=386, MR23=63, INC=396, DEC=264
7042 23:35:09.524060 [RxdqsGatingPostProcess] freq 400
7043 23:35:09.527165 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7044 23:35:09.530781 best DQS0 dly(2T, 0.5T) = (0, 10)
7045 23:35:09.533896 best DQS1 dly(2T, 0.5T) = (0, 10)
7046 23:35:09.537333 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7047 23:35:09.540908 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7048 23:35:09.544045 best DQS0 dly(2T, 0.5T) = (0, 10)
7049 23:35:09.546920 best DQS1 dly(2T, 0.5T) = (0, 10)
7050 23:35:09.550746 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7051 23:35:09.554085 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7052 23:35:09.557166 Pre-setting of DQS Precalculation
7053 23:35:09.560410 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7054 23:35:09.570545 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7055 23:35:09.577192 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7056 23:35:09.577770
7057 23:35:09.578124
7058 23:35:09.580910 [Calibration Summary] 800 Mbps
7059 23:35:09.581438 CH 0, Rank 0
7060 23:35:09.583807 SW Impedance : PASS
7061 23:35:09.584336 DUTY Scan : NO K
7062 23:35:09.587099 ZQ Calibration : PASS
7063 23:35:09.590640 Jitter Meter : NO K
7064 23:35:09.591243 CBT Training : PASS
7065 23:35:09.593938 Write leveling : PASS
7066 23:35:09.597130 RX DQS gating : PASS
7067 23:35:09.597560 RX DQ/DQS(RDDQC) : PASS
7068 23:35:09.600721 TX DQ/DQS : PASS
7069 23:35:09.601250 RX DATLAT : PASS
7070 23:35:09.603594 RX DQ/DQS(Engine): PASS
7071 23:35:09.607029 TX OE : NO K
7072 23:35:09.607564 All Pass.
7073 23:35:09.607907
7074 23:35:09.608224 CH 0, Rank 1
7075 23:35:09.610180 SW Impedance : PASS
7076 23:35:09.613981 DUTY Scan : NO K
7077 23:35:09.614508 ZQ Calibration : PASS
7078 23:35:09.617194 Jitter Meter : NO K
7079 23:35:09.620536 CBT Training : PASS
7080 23:35:09.621086 Write leveling : NO K
7081 23:35:09.623405 RX DQS gating : PASS
7082 23:35:09.627051 RX DQ/DQS(RDDQC) : PASS
7083 23:35:09.627637 TX DQ/DQS : PASS
7084 23:35:09.630169 RX DATLAT : PASS
7085 23:35:09.633801 RX DQ/DQS(Engine): PASS
7086 23:35:09.634374 TX OE : NO K
7087 23:35:09.636601 All Pass.
7088 23:35:09.637064
7089 23:35:09.637439 CH 1, Rank 0
7090 23:35:09.640191 SW Impedance : PASS
7091 23:35:09.640755 DUTY Scan : NO K
7092 23:35:09.643590 ZQ Calibration : PASS
7093 23:35:09.646671 Jitter Meter : NO K
7094 23:35:09.647139 CBT Training : PASS
7095 23:35:09.649679 Write leveling : PASS
7096 23:35:09.653560 RX DQS gating : PASS
7097 23:35:09.654074 RX DQ/DQS(RDDQC) : PASS
7098 23:35:09.656598 TX DQ/DQS : PASS
7099 23:35:09.660074 RX DATLAT : PASS
7100 23:35:09.660646 RX DQ/DQS(Engine): PASS
7101 23:35:09.663315 TX OE : NO K
7102 23:35:09.663786 All Pass.
7103 23:35:09.664164
7104 23:35:09.666510 CH 1, Rank 1
7105 23:35:09.666982 SW Impedance : PASS
7106 23:35:09.670056 DUTY Scan : NO K
7107 23:35:09.670626 ZQ Calibration : PASS
7108 23:35:09.673111 Jitter Meter : NO K
7109 23:35:09.676371 CBT Training : PASS
7110 23:35:09.676939 Write leveling : NO K
7111 23:35:09.680207 RX DQS gating : PASS
7112 23:35:09.682889 RX DQ/DQS(RDDQC) : PASS
7113 23:35:09.683403 TX DQ/DQS : PASS
7114 23:35:09.686357 RX DATLAT : PASS
7115 23:35:09.689953 RX DQ/DQS(Engine): PASS
7116 23:35:09.690419 TX OE : NO K
7117 23:35:09.693217 All Pass.
7118 23:35:09.693833
7119 23:35:09.694215 DramC Write-DBI off
7120 23:35:09.696800 PER_BANK_REFRESH: Hybrid Mode
7121 23:35:09.697368 TX_TRACKING: ON
7122 23:35:09.706461 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7123 23:35:09.710244 [FAST_K] Save calibration result to emmc
7124 23:35:09.712998 dramc_set_vcore_voltage set vcore to 725000
7125 23:35:09.716824 Read voltage for 1600, 0
7126 23:35:09.717389 Vio18 = 0
7127 23:35:09.719485 Vcore = 725000
7128 23:35:09.719948 Vdram = 0
7129 23:35:09.720404 Vddq = 0
7130 23:35:09.722850 Vmddr = 0
7131 23:35:09.726165 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7132 23:35:09.732982 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7133 23:35:09.733549 MEM_TYPE=3, freq_sel=13
7134 23:35:09.736762 sv_algorithm_assistance_LP4_3733
7135 23:35:09.739504 ============ PULL DRAM RESETB DOWN ============
7136 23:35:09.746283 ========== PULL DRAM RESETB DOWN end =========
7137 23:35:09.749794 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7138 23:35:09.752970 ===================================
7139 23:35:09.756789 LPDDR4 DRAM CONFIGURATION
7140 23:35:09.759973 ===================================
7141 23:35:09.760544 EX_ROW_EN[0] = 0x0
7142 23:35:09.762857 EX_ROW_EN[1] = 0x0
7143 23:35:09.766266 LP4Y_EN = 0x0
7144 23:35:09.766833 WORK_FSP = 0x1
7145 23:35:09.769760 WL = 0x5
7146 23:35:09.770326 RL = 0x5
7147 23:35:09.773337 BL = 0x2
7148 23:35:09.773967 RPST = 0x0
7149 23:35:09.776522 RD_PRE = 0x0
7150 23:35:09.777093 WR_PRE = 0x1
7151 23:35:09.779653 WR_PST = 0x1
7152 23:35:09.780217 DBI_WR = 0x0
7153 23:35:09.782649 DBI_RD = 0x0
7154 23:35:09.783112 OTF = 0x1
7155 23:35:09.786332 ===================================
7156 23:35:09.789646 ===================================
7157 23:35:09.793027 ANA top config
7158 23:35:09.795747 ===================================
7159 23:35:09.796241 DLL_ASYNC_EN = 0
7160 23:35:09.799202 ALL_SLAVE_EN = 0
7161 23:35:09.802776 NEW_RANK_MODE = 1
7162 23:35:09.806045 DLL_IDLE_MODE = 1
7163 23:35:09.809506 LP45_APHY_COMB_EN = 1
7164 23:35:09.810122 TX_ODT_DIS = 0
7165 23:35:09.812741 NEW_8X_MODE = 1
7166 23:35:09.816730 ===================================
7167 23:35:09.819466 ===================================
7168 23:35:09.822566 data_rate = 3200
7169 23:35:09.825943 CKR = 1
7170 23:35:09.829336 DQ_P2S_RATIO = 8
7171 23:35:09.832680 ===================================
7172 23:35:09.833253 CA_P2S_RATIO = 8
7173 23:35:09.835698 DQ_CA_OPEN = 0
7174 23:35:09.839140 DQ_SEMI_OPEN = 0
7175 23:35:09.842525 CA_SEMI_OPEN = 0
7176 23:35:09.845700 CA_FULL_RATE = 0
7177 23:35:09.849097 DQ_CKDIV4_EN = 0
7178 23:35:09.849564 CA_CKDIV4_EN = 0
7179 23:35:09.852663 CA_PREDIV_EN = 0
7180 23:35:09.856136 PH8_DLY = 12
7181 23:35:09.859494 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7182 23:35:09.862592 DQ_AAMCK_DIV = 4
7183 23:35:09.865789 CA_AAMCK_DIV = 4
7184 23:35:09.866255 CA_ADMCK_DIV = 4
7185 23:35:09.869420 DQ_TRACK_CA_EN = 0
7186 23:35:09.872501 CA_PICK = 1600
7187 23:35:09.876582 CA_MCKIO = 1600
7188 23:35:09.879371 MCKIO_SEMI = 0
7189 23:35:09.882841 PLL_FREQ = 3068
7190 23:35:09.885622 DQ_UI_PI_RATIO = 32
7191 23:35:09.886093 CA_UI_PI_RATIO = 0
7192 23:35:09.889468 ===================================
7193 23:35:09.892563 ===================================
7194 23:35:09.895567 memory_type:LPDDR4
7195 23:35:09.899082 GP_NUM : 10
7196 23:35:09.899667 SRAM_EN : 1
7197 23:35:09.902741 MD32_EN : 0
7198 23:35:09.905683 ===================================
7199 23:35:09.909215 [ANA_INIT] >>>>>>>>>>>>>>
7200 23:35:09.912277 <<<<<< [CONFIGURE PHASE]: ANA_TX
7201 23:35:09.915679 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7202 23:35:09.918920 ===================================
7203 23:35:09.919492 data_rate = 3200,PCW = 0X7600
7204 23:35:09.921971 ===================================
7205 23:35:09.925451 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7206 23:35:09.931957 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7207 23:35:09.938906 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7208 23:35:09.942066 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7209 23:35:09.945200 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7210 23:35:09.948575 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7211 23:35:09.952130 [ANA_INIT] flow start
7212 23:35:09.955307 [ANA_INIT] PLL >>>>>>>>
7213 23:35:09.955868 [ANA_INIT] PLL <<<<<<<<
7214 23:35:09.958848 [ANA_INIT] MIDPI >>>>>>>>
7215 23:35:09.962022 [ANA_INIT] MIDPI <<<<<<<<
7216 23:35:09.962491 [ANA_INIT] DLL >>>>>>>>
7217 23:35:09.965290 [ANA_INIT] DLL <<<<<<<<
7218 23:35:09.969012 [ANA_INIT] flow end
7219 23:35:09.971959 ============ LP4 DIFF to SE enter ============
7220 23:35:09.975680 ============ LP4 DIFF to SE exit ============
7221 23:35:09.978557 [ANA_INIT] <<<<<<<<<<<<<
7222 23:35:09.982505 [Flow] Enable top DCM control >>>>>
7223 23:35:09.985463 [Flow] Enable top DCM control <<<<<
7224 23:35:09.988699 Enable DLL master slave shuffle
7225 23:35:09.991947 ==============================================================
7226 23:35:09.996039 Gating Mode config
7227 23:35:10.001965 ==============================================================
7228 23:35:10.002433 Config description:
7229 23:35:10.011518 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7230 23:35:10.018500 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7231 23:35:10.021903 SELPH_MODE 0: By rank 1: By Phase
7232 23:35:10.028251 ==============================================================
7233 23:35:10.031782 GAT_TRACK_EN = 1
7234 23:35:10.035480 RX_GATING_MODE = 2
7235 23:35:10.038111 RX_GATING_TRACK_MODE = 2
7236 23:35:10.041645 SELPH_MODE = 1
7237 23:35:10.044539 PICG_EARLY_EN = 1
7238 23:35:10.048317 VALID_LAT_VALUE = 1
7239 23:35:10.051475 ==============================================================
7240 23:35:10.054438 Enter into Gating configuration >>>>
7241 23:35:10.058124 Exit from Gating configuration <<<<
7242 23:35:10.061499 Enter into DVFS_PRE_config >>>>>
7243 23:35:10.074533 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7244 23:35:10.075126 Exit from DVFS_PRE_config <<<<<
7245 23:35:10.078529 Enter into PICG configuration >>>>
7246 23:35:10.081410 Exit from PICG configuration <<<<
7247 23:35:10.084907 [RX_INPUT] configuration >>>>>
7248 23:35:10.087997 [RX_INPUT] configuration <<<<<
7249 23:35:10.095257 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7250 23:35:10.097847 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7251 23:35:10.104634 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7252 23:35:10.111327 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7253 23:35:10.118494 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7254 23:35:10.124639 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7255 23:35:10.127929 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7256 23:35:10.131306 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7257 23:35:10.134773 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7258 23:35:10.140789 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7259 23:35:10.144726 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7260 23:35:10.147936 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7261 23:35:10.151043 ===================================
7262 23:35:10.154596 LPDDR4 DRAM CONFIGURATION
7263 23:35:10.157451 ===================================
7264 23:35:10.161017 EX_ROW_EN[0] = 0x0
7265 23:35:10.161646 EX_ROW_EN[1] = 0x0
7266 23:35:10.164322 LP4Y_EN = 0x0
7267 23:35:10.164828 WORK_FSP = 0x1
7268 23:35:10.167627 WL = 0x5
7269 23:35:10.168094 RL = 0x5
7270 23:35:10.171291 BL = 0x2
7271 23:35:10.171870 RPST = 0x0
7272 23:35:10.174586 RD_PRE = 0x0
7273 23:35:10.175125 WR_PRE = 0x1
7274 23:35:10.177492 WR_PST = 0x1
7275 23:35:10.178110 DBI_WR = 0x0
7276 23:35:10.181318 DBI_RD = 0x0
7277 23:35:10.181968 OTF = 0x1
7278 23:35:10.184815 ===================================
7279 23:35:10.187353 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7280 23:35:10.194248 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7281 23:35:10.197430 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7282 23:35:10.200790 ===================================
7283 23:35:10.204114 LPDDR4 DRAM CONFIGURATION
7284 23:35:10.207798 ===================================
7285 23:35:10.208369 EX_ROW_EN[0] = 0x10
7286 23:35:10.210684 EX_ROW_EN[1] = 0x0
7287 23:35:10.214627 LP4Y_EN = 0x0
7288 23:35:10.215198 WORK_FSP = 0x1
7289 23:35:10.217656 WL = 0x5
7290 23:35:10.218236 RL = 0x5
7291 23:35:10.220962 BL = 0x2
7292 23:35:10.221425 RPST = 0x0
7293 23:35:10.223924 RD_PRE = 0x0
7294 23:35:10.224387 WR_PRE = 0x1
7295 23:35:10.227372 WR_PST = 0x1
7296 23:35:10.228023 DBI_WR = 0x0
7297 23:35:10.230927 DBI_RD = 0x0
7298 23:35:10.231426 OTF = 0x1
7299 23:35:10.234168 ===================================
7300 23:35:10.240947 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7301 23:35:10.241418 ==
7302 23:35:10.244315 Dram Type= 6, Freq= 0, CH_0, rank 0
7303 23:35:10.247473 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7304 23:35:10.247934 ==
7305 23:35:10.251175 [Duty_Offset_Calibration]
7306 23:35:10.254378 B0:2 B1:1 CA:1
7307 23:35:10.254909
7308 23:35:10.257751 [DutyScan_Calibration_Flow] k_type=0
7309 23:35:10.265981
7310 23:35:10.266503 ==CLK 0==
7311 23:35:10.269414 Final CLK duty delay cell = 0
7312 23:35:10.272767 [0] MAX Duty = 5156%(X100), DQS PI = 22
7313 23:35:10.275980 [0] MIN Duty = 4907%(X100), DQS PI = 0
7314 23:35:10.276511 [0] AVG Duty = 5031%(X100)
7315 23:35:10.279458
7316 23:35:10.283108 CH0 CLK Duty spec in!! Max-Min= 249%
7317 23:35:10.286179 [DutyScan_Calibration_Flow] ====Done====
7318 23:35:10.286710
7319 23:35:10.288955 [DutyScan_Calibration_Flow] k_type=1
7320 23:35:10.304837
7321 23:35:10.305424 ==DQS 0 ==
7322 23:35:10.308426 Final DQS duty delay cell = -4
7323 23:35:10.311447 [-4] MAX Duty = 5125%(X100), DQS PI = 24
7324 23:35:10.315142 [-4] MIN Duty = 4657%(X100), DQS PI = 2
7325 23:35:10.318303 [-4] AVG Duty = 4891%(X100)
7326 23:35:10.318872
7327 23:35:10.319249 ==DQS 1 ==
7328 23:35:10.321658 Final DQS duty delay cell = 0
7329 23:35:10.324839 [0] MAX Duty = 5187%(X100), DQS PI = 4
7330 23:35:10.328337 [0] MIN Duty = 5062%(X100), DQS PI = 32
7331 23:35:10.331848 [0] AVG Duty = 5124%(X100)
7332 23:35:10.332464
7333 23:35:10.334938 CH0 DQS 0 Duty spec in!! Max-Min= 468%
7334 23:35:10.335421
7335 23:35:10.338173 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7336 23:35:10.341508 [DutyScan_Calibration_Flow] ====Done====
7337 23:35:10.342051
7338 23:35:10.345241 [DutyScan_Calibration_Flow] k_type=3
7339 23:35:10.362634
7340 23:35:10.363323 ==DQM 0 ==
7341 23:35:10.366126 Final DQM duty delay cell = 0
7342 23:35:10.369403 [0] MAX Duty = 5187%(X100), DQS PI = 26
7343 23:35:10.372469 [0] MIN Duty = 4875%(X100), DQS PI = 60
7344 23:35:10.375717 [0] AVG Duty = 5031%(X100)
7345 23:35:10.376294
7346 23:35:10.376791 ==DQM 1 ==
7347 23:35:10.379180 Final DQM duty delay cell = 0
7348 23:35:10.382963 [0] MAX Duty = 5187%(X100), DQS PI = 4
7349 23:35:10.386052 [0] MIN Duty = 5062%(X100), DQS PI = 12
7350 23:35:10.389688 [0] AVG Duty = 5124%(X100)
7351 23:35:10.390265
7352 23:35:10.392442 CH0 DQM 0 Duty spec in!! Max-Min= 312%
7353 23:35:10.393024
7354 23:35:10.396297 CH0 DQM 1 Duty spec in!! Max-Min= 125%
7355 23:35:10.399295 [DutyScan_Calibration_Flow] ====Done====
7356 23:35:10.400030
7357 23:35:10.402238 [DutyScan_Calibration_Flow] k_type=2
7358 23:35:10.419632
7359 23:35:10.420185 ==DQ 0 ==
7360 23:35:10.422821 Final DQ duty delay cell = 0
7361 23:35:10.426043 [0] MAX Duty = 5062%(X100), DQS PI = 24
7362 23:35:10.429433 [0] MIN Duty = 4907%(X100), DQS PI = 0
7363 23:35:10.429998 [0] AVG Duty = 4984%(X100)
7364 23:35:10.430360
7365 23:35:10.432604 ==DQ 1 ==
7366 23:35:10.436702 Final DQ duty delay cell = 0
7367 23:35:10.439482 [0] MAX Duty = 5125%(X100), DQS PI = 6
7368 23:35:10.442395 [0] MIN Duty = 4907%(X100), DQS PI = 34
7369 23:35:10.442622 [0] AVG Duty = 5016%(X100)
7370 23:35:10.442802
7371 23:35:10.446046 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7372 23:35:10.446227
7373 23:35:10.449101 CH0 DQ 1 Duty spec in!! Max-Min= 218%
7374 23:35:10.455838 [DutyScan_Calibration_Flow] ====Done====
7375 23:35:10.456096 ==
7376 23:35:10.459178 Dram Type= 6, Freq= 0, CH_1, rank 0
7377 23:35:10.462860 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7378 23:35:10.463062 ==
7379 23:35:10.465931 [Duty_Offset_Calibration]
7380 23:35:10.466111 B0:1 B1:0 CA:0
7381 23:35:10.466257
7382 23:35:10.469011 [DutyScan_Calibration_Flow] k_type=0
7383 23:35:10.478696
7384 23:35:10.478993 ==CLK 0==
7385 23:35:10.481996 Final CLK duty delay cell = -4
7386 23:35:10.485550 [-4] MAX Duty = 4969%(X100), DQS PI = 22
7387 23:35:10.488683 [-4] MIN Duty = 4844%(X100), DQS PI = 52
7388 23:35:10.492337 [-4] AVG Duty = 4906%(X100)
7389 23:35:10.492873
7390 23:35:10.495907 CH1 CLK Duty spec in!! Max-Min= 125%
7391 23:35:10.498998 [DutyScan_Calibration_Flow] ====Done====
7392 23:35:10.499562
7393 23:35:10.502133 [DutyScan_Calibration_Flow] k_type=1
7394 23:35:10.518967
7395 23:35:10.519571 ==DQS 0 ==
7396 23:35:10.522355 Final DQS duty delay cell = 0
7397 23:35:10.525686 [0] MAX Duty = 5094%(X100), DQS PI = 24
7398 23:35:10.528711 [0] MIN Duty = 4875%(X100), DQS PI = 0
7399 23:35:10.529284 [0] AVG Duty = 4984%(X100)
7400 23:35:10.532579
7401 23:35:10.533137 ==DQS 1 ==
7402 23:35:10.535749 Final DQS duty delay cell = 0
7403 23:35:10.538819 [0] MAX Duty = 5249%(X100), DQS PI = 16
7404 23:35:10.542031 [0] MIN Duty = 4969%(X100), DQS PI = 6
7405 23:35:10.542499 [0] AVG Duty = 5109%(X100)
7406 23:35:10.545637
7407 23:35:10.548865 CH1 DQS 0 Duty spec in!! Max-Min= 219%
7408 23:35:10.549436
7409 23:35:10.551758 CH1 DQS 1 Duty spec in!! Max-Min= 280%
7410 23:35:10.555003 [DutyScan_Calibration_Flow] ====Done====
7411 23:35:10.555467
7412 23:35:10.558510 [DutyScan_Calibration_Flow] k_type=3
7413 23:35:10.575776
7414 23:35:10.576319 ==DQM 0 ==
7415 23:35:10.579105 Final DQM duty delay cell = 0
7416 23:35:10.582324 [0] MAX Duty = 5218%(X100), DQS PI = 18
7417 23:35:10.585951 [0] MIN Duty = 4969%(X100), DQS PI = 48
7418 23:35:10.589060 [0] AVG Duty = 5093%(X100)
7419 23:35:10.589650
7420 23:35:10.590032 ==DQM 1 ==
7421 23:35:10.592329 Final DQM duty delay cell = 0
7422 23:35:10.595433 [0] MAX Duty = 5093%(X100), DQS PI = 42
7423 23:35:10.598852 [0] MIN Duty = 4907%(X100), DQS PI = 34
7424 23:35:10.602187 [0] AVG Duty = 5000%(X100)
7425 23:35:10.602651
7426 23:35:10.605259 CH1 DQM 0 Duty spec in!! Max-Min= 249%
7427 23:35:10.605769
7428 23:35:10.608777 CH1 DQM 1 Duty spec in!! Max-Min= 186%
7429 23:35:10.612027 [DutyScan_Calibration_Flow] ====Done====
7430 23:35:10.612558
7431 23:35:10.615230 [DutyScan_Calibration_Flow] k_type=2
7432 23:35:10.632069
7433 23:35:10.632641 ==DQ 0 ==
7434 23:35:10.635609 Final DQ duty delay cell = -4
7435 23:35:10.638931 [-4] MAX Duty = 5062%(X100), DQS PI = 14
7436 23:35:10.641675 [-4] MIN Duty = 4875%(X100), DQS PI = 46
7437 23:35:10.645275 [-4] AVG Duty = 4968%(X100)
7438 23:35:10.645905
7439 23:35:10.646283 ==DQ 1 ==
7440 23:35:10.648220 Final DQ duty delay cell = 0
7441 23:35:10.652089 [0] MAX Duty = 5124%(X100), DQS PI = 18
7442 23:35:10.654862 [0] MIN Duty = 4938%(X100), DQS PI = 8
7443 23:35:10.658199 [0] AVG Duty = 5031%(X100)
7444 23:35:10.658765
7445 23:35:10.661453 CH1 DQ 0 Duty spec in!! Max-Min= 187%
7446 23:35:10.661938
7447 23:35:10.664882 CH1 DQ 1 Duty spec in!! Max-Min= 186%
7448 23:35:10.668915 [DutyScan_Calibration_Flow] ====Done====
7449 23:35:10.671895 nWR fixed to 30
7450 23:35:10.674967 [ModeRegInit_LP4] CH0 RK0
7451 23:35:10.675529 [ModeRegInit_LP4] CH0 RK1
7452 23:35:10.678141 [ModeRegInit_LP4] CH1 RK0
7453 23:35:10.681871 [ModeRegInit_LP4] CH1 RK1
7454 23:35:10.682435 match AC timing 5
7455 23:35:10.688284 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7456 23:35:10.691585 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7457 23:35:10.695120 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7458 23:35:10.701745 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7459 23:35:10.704629 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7460 23:35:10.705095 [MiockJmeterHQA]
7461 23:35:10.705549
7462 23:35:10.708145 [DramcMiockJmeter] u1RxGatingPI = 0
7463 23:35:10.711481 0 : 4255, 4029
7464 23:35:10.712057 4 : 4252, 4026
7465 23:35:10.714303 8 : 4253, 4027
7466 23:35:10.714773 12 : 4257, 4030
7467 23:35:10.717781 16 : 4258, 4029
7468 23:35:10.718281 20 : 4368, 4139
7469 23:35:10.718660 24 : 4252, 4027
7470 23:35:10.721340 28 : 4252, 4027
7471 23:35:10.721932 32 : 4253, 4026
7472 23:35:10.724695 36 : 4255, 4029
7473 23:35:10.725164 40 : 4252, 4027
7474 23:35:10.727904 44 : 4363, 4137
7475 23:35:10.728375 48 : 4363, 4138
7476 23:35:10.728771 52 : 4253, 4027
7477 23:35:10.731038 56 : 4252, 4027
7478 23:35:10.731515 60 : 4253, 4026
7479 23:35:10.734680 64 : 4252, 4027
7480 23:35:10.735178 68 : 4254, 4029
7481 23:35:10.738022 72 : 4361, 4137
7482 23:35:10.738627 76 : 4250, 4027
7483 23:35:10.741286 80 : 4250, 4026
7484 23:35:10.741802 84 : 4250, 4024
7485 23:35:10.742190 88 : 4252, 41
7486 23:35:10.744556 92 : 4250, 0
7487 23:35:10.745029 96 : 4252, 0
7488 23:35:10.745407 100 : 4250, 0
7489 23:35:10.747987 104 : 4249, 0
7490 23:35:10.748438 108 : 4250, 0
7491 23:35:10.751418 112 : 4360, 0
7492 23:35:10.751845 116 : 4361, 0
7493 23:35:10.752190 120 : 4250, 0
7494 23:35:10.754570 124 : 4250, 0
7495 23:35:10.755109 128 : 4250, 0
7496 23:35:10.757865 132 : 4250, 0
7497 23:35:10.758398 136 : 4250, 0
7498 23:35:10.758745 140 : 4250, 0
7499 23:35:10.761458 144 : 4252, 0
7500 23:35:10.762049 148 : 4250, 0
7501 23:35:10.764446 152 : 4250, 0
7502 23:35:10.764873 156 : 4252, 0
7503 23:35:10.765217 160 : 4361, 0
7504 23:35:10.768432 164 : 4360, 0
7505 23:35:10.768975 168 : 4363, 0
7506 23:35:10.770872 172 : 4360, 0
7507 23:35:10.771300 176 : 4250, 0
7508 23:35:10.771640 180 : 4250, 0
7509 23:35:10.774438 184 : 4250, 0
7510 23:35:10.774973 188 : 4250, 0
7511 23:35:10.775324 192 : 4250, 0
7512 23:35:10.777921 196 : 4249, 0
7513 23:35:10.778345 200 : 4250, 0
7514 23:35:10.780786 204 : 4250, 1260
7515 23:35:10.781212 208 : 4250, 4006
7516 23:35:10.784861 212 : 4255, 4029
7517 23:35:10.785396 216 : 4250, 4027
7518 23:35:10.788053 220 : 4249, 4027
7519 23:35:10.788616 224 : 4253, 4026
7520 23:35:10.790955 228 : 4361, 4137
7521 23:35:10.791381 232 : 4250, 4026
7522 23:35:10.791723 236 : 4250, 4027
7523 23:35:10.794493 240 : 4360, 4137
7524 23:35:10.795039 244 : 4250, 4027
7525 23:35:10.797721 248 : 4250, 4027
7526 23:35:10.798265 252 : 4363, 4140
7527 23:35:10.801150 256 : 4250, 4027
7528 23:35:10.801761 260 : 4250, 4026
7529 23:35:10.803818 264 : 4250, 4027
7530 23:35:10.804247 268 : 4252, 4030
7531 23:35:10.807281 272 : 4250, 4027
7532 23:35:10.807707 276 : 4253, 4027
7533 23:35:10.810821 280 : 4361, 4137
7534 23:35:10.811250 284 : 4250, 4026
7535 23:35:10.814105 288 : 4250, 4027
7536 23:35:10.814530 292 : 4360, 4138
7537 23:35:10.817433 296 : 4250, 4027
7538 23:35:10.818014 300 : 4250, 4027
7539 23:35:10.818363 304 : 4363, 4140
7540 23:35:10.820606 308 : 4250, 3957
7541 23:35:10.821136 312 : 4250, 1857
7542 23:35:10.821496
7543 23:35:10.823967 MIOCK jitter meter ch=0
7544 23:35:10.824385
7545 23:35:10.827412 1T = (312-88) = 224 dly cells
7546 23:35:10.834145 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7547 23:35:10.834678 ==
7548 23:35:10.837205 Dram Type= 6, Freq= 0, CH_0, rank 0
7549 23:35:10.840546 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7550 23:35:10.841078 ==
7551 23:35:10.847383 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7552 23:35:10.850274 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7553 23:35:10.854050 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7554 23:35:10.860138 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7555 23:35:10.869623 [CA 0] Center 42 (12~73) winsize 62
7556 23:35:10.873220 [CA 1] Center 42 (12~73) winsize 62
7557 23:35:10.876355 [CA 2] Center 38 (8~68) winsize 61
7558 23:35:10.879652 [CA 3] Center 37 (8~67) winsize 60
7559 23:35:10.882897 [CA 4] Center 36 (6~66) winsize 61
7560 23:35:10.886191 [CA 5] Center 35 (6~64) winsize 59
7561 23:35:10.886769
7562 23:35:10.889797 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7563 23:35:10.890411
7564 23:35:10.892954 [CATrainingPosCal] consider 1 rank data
7565 23:35:10.895646 u2DelayCellTimex100 = 290/100 ps
7566 23:35:10.898955 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7567 23:35:10.906000 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7568 23:35:10.909326 CA2 delay=38 (8~68),Diff = 3 PI (10 cell)
7569 23:35:10.912431 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7570 23:35:10.915717 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7571 23:35:10.919519 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7572 23:35:10.920124
7573 23:35:10.922895 CA PerBit enable=1, Macro0, CA PI delay=35
7574 23:35:10.923364
7575 23:35:10.925972 [CBTSetCACLKResult] CA Dly = 35
7576 23:35:10.929352 CS Dly: 9 (0~40)
7577 23:35:10.932169 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7578 23:35:10.935666 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7579 23:35:10.936235 ==
7580 23:35:10.939102 Dram Type= 6, Freq= 0, CH_0, rank 1
7581 23:35:10.942465 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7582 23:35:10.945713 ==
7583 23:35:10.948672 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7584 23:35:10.952212 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7585 23:35:10.958936 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7586 23:35:10.965514 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7587 23:35:10.972870 [CA 0] Center 43 (13~73) winsize 61
7588 23:35:10.976269 [CA 1] Center 43 (13~73) winsize 61
7589 23:35:10.979805 [CA 2] Center 37 (8~67) winsize 60
7590 23:35:10.982997 [CA 3] Center 38 (8~68) winsize 61
7591 23:35:10.986134 [CA 4] Center 35 (6~65) winsize 60
7592 23:35:10.989739 [CA 5] Center 35 (6~65) winsize 60
7593 23:35:10.990210
7594 23:35:10.992727 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7595 23:35:10.993288
7596 23:35:10.995867 [CATrainingPosCal] consider 2 rank data
7597 23:35:10.999684 u2DelayCellTimex100 = 290/100 ps
7598 23:35:11.002916 CA0 delay=43 (13~73),Diff = 8 PI (26 cell)
7599 23:35:11.009421 CA1 delay=43 (13~73),Diff = 8 PI (26 cell)
7600 23:35:11.013054 CA2 delay=37 (8~67),Diff = 2 PI (6 cell)
7601 23:35:11.016513 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7602 23:35:11.019501 CA4 delay=35 (6~65),Diff = 0 PI (0 cell)
7603 23:35:11.022786 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7604 23:35:11.023356
7605 23:35:11.025916 CA PerBit enable=1, Macro0, CA PI delay=35
7606 23:35:11.026385
7607 23:35:11.029313 [CBTSetCACLKResult] CA Dly = 35
7608 23:35:11.032328 CS Dly: 9 (0~41)
7609 23:35:11.036263 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7610 23:35:11.039884 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7611 23:35:11.040466
7612 23:35:11.042452 ----->DramcWriteLeveling(PI) begin...
7613 23:35:11.042929 ==
7614 23:35:11.045938 Dram Type= 6, Freq= 0, CH_0, rank 0
7615 23:35:11.049741 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7616 23:35:11.052342 ==
7617 23:35:11.052811 Write leveling (Byte 0): 36 => 36
7618 23:35:11.056500 Write leveling (Byte 1): 25 => 25
7619 23:35:11.059625 DramcWriteLeveling(PI) end<-----
7620 23:35:11.060199
7621 23:35:11.060575 ==
7622 23:35:11.062395 Dram Type= 6, Freq= 0, CH_0, rank 0
7623 23:35:11.069569 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7624 23:35:11.070196 ==
7625 23:35:11.070581 [Gating] SW mode calibration
7626 23:35:11.079127 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7627 23:35:11.082716 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7628 23:35:11.086368 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7629 23:35:11.092209 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7630 23:35:11.095537 1 4 8 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
7631 23:35:11.098792 1 4 12 | B1->B0 | 2323 3333 | 0 1 | (0 0) (1 1)
7632 23:35:11.105558 1 4 16 | B1->B0 | 2323 3939 | 0 1 | (0 0) (0 0)
7633 23:35:11.108777 1 4 20 | B1->B0 | 3434 3c3b | 1 1 | (1 1) (0 0)
7634 23:35:11.112843 1 4 24 | B1->B0 | 3434 3838 | 1 1 | (1 1) (1 1)
7635 23:35:11.118817 1 4 28 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7636 23:35:11.122581 1 5 0 | B1->B0 | 3434 3838 | 1 0 | (1 1) (0 0)
7637 23:35:11.126051 1 5 4 | B1->B0 | 3434 3636 | 1 1 | (1 1) (1 1)
7638 23:35:11.132339 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
7639 23:35:11.135922 1 5 12 | B1->B0 | 3434 2a2a | 1 0 | (1 1) (0 0)
7640 23:35:11.139024 1 5 16 | B1->B0 | 3434 2727 | 1 0 | (1 0) (0 0)
7641 23:35:11.145532 1 5 20 | B1->B0 | 2626 2323 | 0 0 | (1 0) (0 0)
7642 23:35:11.148598 1 5 24 | B1->B0 | 2323 2726 | 0 1 | (0 0) (0 0)
7643 23:35:11.152011 1 5 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7644 23:35:11.159214 1 6 0 | B1->B0 | 2323 2827 | 0 1 | (0 0) (0 0)
7645 23:35:11.162282 1 6 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7646 23:35:11.166118 1 6 8 | B1->B0 | 2323 3636 | 0 0 | (0 0) (0 0)
7647 23:35:11.172242 1 6 12 | B1->B0 | 2323 4645 | 0 1 | (0 0) (0 0)
7648 23:35:11.175960 1 6 16 | B1->B0 | 2727 4646 | 0 0 | (1 1) (0 0)
7649 23:35:11.179342 1 6 20 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
7650 23:35:11.185169 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7651 23:35:11.188649 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7652 23:35:11.192043 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7653 23:35:11.198518 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7654 23:35:11.201978 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7655 23:35:11.205842 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7656 23:35:11.211693 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7657 23:35:11.215200 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7658 23:35:11.218437 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7659 23:35:11.225574 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7660 23:35:11.228059 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7661 23:35:11.231978 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7662 23:35:11.238524 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7663 23:35:11.242004 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7664 23:35:11.244671 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7665 23:35:11.251510 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7666 23:35:11.255100 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7667 23:35:11.257940 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7668 23:35:11.261371 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7669 23:35:11.268389 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7670 23:35:11.271290 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7671 23:35:11.274876 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7672 23:35:11.281531 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7673 23:35:11.284937 Total UI for P1: 0, mck2ui 16
7674 23:35:11.288580 best dqsien dly found for B0: ( 1, 9, 12)
7675 23:35:11.291453 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7676 23:35:11.294654 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7677 23:35:11.297951 Total UI for P1: 0, mck2ui 16
7678 23:35:11.301170 best dqsien dly found for B1: ( 1, 9, 18)
7679 23:35:11.304294 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
7680 23:35:11.307676 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7681 23:35:11.311203
7682 23:35:11.314578 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
7683 23:35:11.317980 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7684 23:35:11.321415 [Gating] SW calibration Done
7685 23:35:11.322072 ==
7686 23:35:11.324866 Dram Type= 6, Freq= 0, CH_0, rank 0
7687 23:35:11.327624 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7688 23:35:11.328092 ==
7689 23:35:11.328485 RX Vref Scan: 0
7690 23:35:11.331565
7691 23:35:11.332140 RX Vref 0 -> 0, step: 1
7692 23:35:11.332519
7693 23:35:11.334396 RX Delay 0 -> 252, step: 8
7694 23:35:11.338083 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
7695 23:35:11.341556 iDelay=200, Bit 1, Center 143 (88 ~ 199) 112
7696 23:35:11.347821 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
7697 23:35:11.350988 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7698 23:35:11.354468 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7699 23:35:11.357528 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7700 23:35:11.360896 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
7701 23:35:11.364274 iDelay=200, Bit 7, Center 143 (96 ~ 191) 96
7702 23:35:11.371418 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
7703 23:35:11.374118 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
7704 23:35:11.378093 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
7705 23:35:11.381149 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7706 23:35:11.384672 iDelay=200, Bit 12, Center 135 (88 ~ 183) 96
7707 23:35:11.390948 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
7708 23:35:11.394260 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7709 23:35:11.397495 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7710 23:35:11.398141 ==
7711 23:35:11.400762 Dram Type= 6, Freq= 0, CH_0, rank 0
7712 23:35:11.404022 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7713 23:35:11.407550 ==
7714 23:35:11.408189 DQS Delay:
7715 23:35:11.408588 DQS0 = 0, DQS1 = 0
7716 23:35:11.411080 DQM Delay:
7717 23:35:11.411550 DQM0 = 136, DQM1 = 130
7718 23:35:11.414167 DQ Delay:
7719 23:35:11.417708 DQ0 =135, DQ1 =143, DQ2 =135, DQ3 =131
7720 23:35:11.421034 DQ4 =139, DQ5 =123, DQ6 =143, DQ7 =143
7721 23:35:11.424615 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =123
7722 23:35:11.427174 DQ12 =135, DQ13 =139, DQ14 =139, DQ15 =135
7723 23:35:11.427642
7724 23:35:11.428018
7725 23:35:11.428368 ==
7726 23:35:11.430870 Dram Type= 6, Freq= 0, CH_0, rank 0
7727 23:35:11.434071 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7728 23:35:11.434602 ==
7729 23:35:11.435164
7730 23:35:11.437848
7731 23:35:11.438314 TX Vref Scan disable
7732 23:35:11.440855 == TX Byte 0 ==
7733 23:35:11.444194 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7734 23:35:11.447318 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7735 23:35:11.450694 == TX Byte 1 ==
7736 23:35:11.453695 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7737 23:35:11.457426 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
7738 23:35:11.457919 ==
7739 23:35:11.460653 Dram Type= 6, Freq= 0, CH_0, rank 0
7740 23:35:11.466954 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7741 23:35:11.467392 ==
7742 23:35:11.479861
7743 23:35:11.483187 TX Vref early break, caculate TX vref
7744 23:35:11.486293 TX Vref=16, minBit 7, minWin=22, winSum=378
7745 23:35:11.490133 TX Vref=18, minBit 7, minWin=22, winSum=385
7746 23:35:11.493191 TX Vref=20, minBit 7, minWin=23, winSum=403
7747 23:35:11.496459 TX Vref=22, minBit 7, minWin=24, winSum=408
7748 23:35:11.500090 TX Vref=24, minBit 3, minWin=24, winSum=419
7749 23:35:11.506235 TX Vref=26, minBit 2, minWin=25, winSum=424
7750 23:35:11.509408 TX Vref=28, minBit 2, minWin=25, winSum=422
7751 23:35:11.512846 TX Vref=30, minBit 2, minWin=25, winSum=414
7752 23:35:11.516381 TX Vref=32, minBit 0, minWin=24, winSum=402
7753 23:35:11.519829 TX Vref=34, minBit 2, minWin=23, winSum=394
7754 23:35:11.526024 [TxChooseVref] Worse bit 2, Min win 25, Win sum 424, Final Vref 26
7755 23:35:11.526338
7756 23:35:11.529177 Final TX Range 0 Vref 26
7757 23:35:11.529482
7758 23:35:11.529754 ==
7759 23:35:11.532512 Dram Type= 6, Freq= 0, CH_0, rank 0
7760 23:35:11.536106 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7761 23:35:11.536521 ==
7762 23:35:11.536784
7763 23:35:11.537010
7764 23:35:11.539703 TX Vref Scan disable
7765 23:35:11.546359 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7766 23:35:11.546906 == TX Byte 0 ==
7767 23:35:11.549572 u2DelayCellOfst[0]=10 cells (3 PI)
7768 23:35:11.553535 u2DelayCellOfst[1]=10 cells (3 PI)
7769 23:35:11.556139 u2DelayCellOfst[2]=10 cells (3 PI)
7770 23:35:11.559879 u2DelayCellOfst[3]=10 cells (3 PI)
7771 23:35:11.563139 u2DelayCellOfst[4]=6 cells (2 PI)
7772 23:35:11.566080 u2DelayCellOfst[5]=0 cells (0 PI)
7773 23:35:11.569729 u2DelayCellOfst[6]=16 cells (5 PI)
7774 23:35:11.573062 u2DelayCellOfst[7]=16 cells (5 PI)
7775 23:35:11.576241 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7776 23:35:11.579859 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7777 23:35:11.582728 == TX Byte 1 ==
7778 23:35:11.585974 u2DelayCellOfst[8]=3 cells (1 PI)
7779 23:35:11.586461 u2DelayCellOfst[9]=0 cells (0 PI)
7780 23:35:11.589288 u2DelayCellOfst[10]=10 cells (3 PI)
7781 23:35:11.592746 u2DelayCellOfst[11]=3 cells (1 PI)
7782 23:35:11.596101 u2DelayCellOfst[12]=13 cells (4 PI)
7783 23:35:11.598695 u2DelayCellOfst[13]=13 cells (4 PI)
7784 23:35:11.602488 u2DelayCellOfst[14]=16 cells (5 PI)
7785 23:35:11.605296 u2DelayCellOfst[15]=10 cells (3 PI)
7786 23:35:11.612532 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
7787 23:35:11.616330 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
7788 23:35:11.616903 DramC Write-DBI on
7789 23:35:11.617281 ==
7790 23:35:11.619001 Dram Type= 6, Freq= 0, CH_0, rank 0
7791 23:35:11.625535 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7792 23:35:11.626163 ==
7793 23:35:11.626547
7794 23:35:11.626896
7795 23:35:11.628747 TX Vref Scan disable
7796 23:35:11.629226 == TX Byte 0 ==
7797 23:35:11.634872 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7798 23:35:11.635434 == TX Byte 1 ==
7799 23:35:11.638630 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
7800 23:35:11.642034 DramC Write-DBI off
7801 23:35:11.642609
7802 23:35:11.642985 [DATLAT]
7803 23:35:11.645008 Freq=1600, CH0 RK0
7804 23:35:11.645476
7805 23:35:11.645960 DATLAT Default: 0xf
7806 23:35:11.648645 0, 0xFFFF, sum = 0
7807 23:35:11.649121 1, 0xFFFF, sum = 0
7808 23:35:11.651520 2, 0xFFFF, sum = 0
7809 23:35:11.651991 3, 0xFFFF, sum = 0
7810 23:35:11.654747 4, 0xFFFF, sum = 0
7811 23:35:11.655226 5, 0xFFFF, sum = 0
7812 23:35:11.658738 6, 0xFFFF, sum = 0
7813 23:35:11.659302 7, 0xFFFF, sum = 0
7814 23:35:11.661903 8, 0xFFFF, sum = 0
7815 23:35:11.662471 9, 0xFFFF, sum = 0
7816 23:35:11.665507 10, 0xFFFF, sum = 0
7817 23:35:11.668691 11, 0xFFFF, sum = 0
7818 23:35:11.669288 12, 0xFFFF, sum = 0
7819 23:35:11.671831 13, 0xFFFF, sum = 0
7820 23:35:11.672398 14, 0x0, sum = 1
7821 23:35:11.675190 15, 0x0, sum = 2
7822 23:35:11.675663 16, 0x0, sum = 3
7823 23:35:11.678576 17, 0x0, sum = 4
7824 23:35:11.679045 best_step = 15
7825 23:35:11.679424
7826 23:35:11.679770 ==
7827 23:35:11.681988 Dram Type= 6, Freq= 0, CH_0, rank 0
7828 23:35:11.685674 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7829 23:35:11.686263 ==
7830 23:35:11.688811 RX Vref Scan: 1
7831 23:35:11.689370
7832 23:35:11.691798 Set Vref Range= 24 -> 127
7833 23:35:11.692375
7834 23:35:11.692750 RX Vref 24 -> 127, step: 1
7835 23:35:11.693103
7836 23:35:11.695335 RX Delay 27 -> 252, step: 4
7837 23:35:11.695901
7838 23:35:11.699172 Set Vref, RX VrefLevel [Byte0]: 24
7839 23:35:11.702196 [Byte1]: 24
7840 23:35:11.702660
7841 23:35:11.705029 Set Vref, RX VrefLevel [Byte0]: 25
7842 23:35:11.708482 [Byte1]: 25
7843 23:35:11.712617
7844 23:35:11.713180 Set Vref, RX VrefLevel [Byte0]: 26
7845 23:35:11.715762 [Byte1]: 26
7846 23:35:11.720165
7847 23:35:11.720727 Set Vref, RX VrefLevel [Byte0]: 27
7848 23:35:11.723058 [Byte1]: 27
7849 23:35:11.727343
7850 23:35:11.727922 Set Vref, RX VrefLevel [Byte0]: 28
7851 23:35:11.730779 [Byte1]: 28
7852 23:35:11.734748
7853 23:35:11.735212 Set Vref, RX VrefLevel [Byte0]: 29
7854 23:35:11.738525 [Byte1]: 29
7855 23:35:11.742379
7856 23:35:11.742934 Set Vref, RX VrefLevel [Byte0]: 30
7857 23:35:11.746054 [Byte1]: 30
7858 23:35:11.749800
7859 23:35:11.750266 Set Vref, RX VrefLevel [Byte0]: 31
7860 23:35:11.753451 [Byte1]: 31
7861 23:35:11.757816
7862 23:35:11.758387 Set Vref, RX VrefLevel [Byte0]: 32
7863 23:35:11.761204 [Byte1]: 32
7864 23:35:11.764990
7865 23:35:11.765469 Set Vref, RX VrefLevel [Byte0]: 33
7866 23:35:11.768376 [Byte1]: 33
7867 23:35:11.772585
7868 23:35:11.773047 Set Vref, RX VrefLevel [Byte0]: 34
7869 23:35:11.775627 [Byte1]: 34
7870 23:35:11.780238
7871 23:35:11.780803 Set Vref, RX VrefLevel [Byte0]: 35
7872 23:35:11.783562 [Byte1]: 35
7873 23:35:11.787531
7874 23:35:11.788088 Set Vref, RX VrefLevel [Byte0]: 36
7875 23:35:11.790853 [Byte1]: 36
7876 23:35:11.795596
7877 23:35:11.796160 Set Vref, RX VrefLevel [Byte0]: 37
7878 23:35:11.798238 [Byte1]: 37
7879 23:35:11.802555
7880 23:35:11.803028 Set Vref, RX VrefLevel [Byte0]: 38
7881 23:35:11.806167 [Byte1]: 38
7882 23:35:11.810039
7883 23:35:11.810502 Set Vref, RX VrefLevel [Byte0]: 39
7884 23:35:11.813910 [Byte1]: 39
7885 23:35:11.817833
7886 23:35:11.818301 Set Vref, RX VrefLevel [Byte0]: 40
7887 23:35:11.821318 [Byte1]: 40
7888 23:35:11.825861
7889 23:35:11.826436 Set Vref, RX VrefLevel [Byte0]: 41
7890 23:35:11.829132 [Byte1]: 41
7891 23:35:11.833469
7892 23:35:11.834089 Set Vref, RX VrefLevel [Byte0]: 42
7893 23:35:11.836033 [Byte1]: 42
7894 23:35:11.840490
7895 23:35:11.841067 Set Vref, RX VrefLevel [Byte0]: 43
7896 23:35:11.843943 [Byte1]: 43
7897 23:35:11.847907
7898 23:35:11.848374 Set Vref, RX VrefLevel [Byte0]: 44
7899 23:35:11.851416 [Byte1]: 44
7900 23:35:11.855446
7901 23:35:11.855914 Set Vref, RX VrefLevel [Byte0]: 45
7902 23:35:11.859072 [Byte1]: 45
7903 23:35:11.863201
7904 23:35:11.863770 Set Vref, RX VrefLevel [Byte0]: 46
7905 23:35:11.866551 [Byte1]: 46
7906 23:35:11.871060
7907 23:35:11.871638 Set Vref, RX VrefLevel [Byte0]: 47
7908 23:35:11.873755 [Byte1]: 47
7909 23:35:11.878132
7910 23:35:11.878597 Set Vref, RX VrefLevel [Byte0]: 48
7911 23:35:11.881695 [Byte1]: 48
7912 23:35:11.886012
7913 23:35:11.886589 Set Vref, RX VrefLevel [Byte0]: 49
7914 23:35:11.892091 [Byte1]: 49
7915 23:35:11.892668
7916 23:35:11.895546 Set Vref, RX VrefLevel [Byte0]: 50
7917 23:35:11.899136 [Byte1]: 50
7918 23:35:11.899710
7919 23:35:11.902201 Set Vref, RX VrefLevel [Byte0]: 51
7920 23:35:11.905237 [Byte1]: 51
7921 23:35:11.905764
7922 23:35:11.908499 Set Vref, RX VrefLevel [Byte0]: 52
7923 23:35:11.912476 [Byte1]: 52
7924 23:35:11.915475
7925 23:35:11.915941 Set Vref, RX VrefLevel [Byte0]: 53
7926 23:35:11.919057 [Byte1]: 53
7927 23:35:11.923133
7928 23:35:11.923693 Set Vref, RX VrefLevel [Byte0]: 54
7929 23:35:11.926745 [Byte1]: 54
7930 23:35:11.930783
7931 23:35:11.931362 Set Vref, RX VrefLevel [Byte0]: 55
7932 23:35:11.934080 [Byte1]: 55
7933 23:35:11.938487
7934 23:35:11.938953 Set Vref, RX VrefLevel [Byte0]: 56
7935 23:35:11.941646 [Byte1]: 56
7936 23:35:11.945945
7937 23:35:11.946415 Set Vref, RX VrefLevel [Byte0]: 57
7938 23:35:11.949214 [Byte1]: 57
7939 23:35:11.953216
7940 23:35:11.953840 Set Vref, RX VrefLevel [Byte0]: 58
7941 23:35:11.956711 [Byte1]: 58
7942 23:35:11.961042
7943 23:35:11.961655 Set Vref, RX VrefLevel [Byte0]: 59
7944 23:35:11.964479 [Byte1]: 59
7945 23:35:11.968293
7946 23:35:11.968759 Set Vref, RX VrefLevel [Byte0]: 60
7947 23:35:11.972394 [Byte1]: 60
7948 23:35:11.976443
7949 23:35:11.977006 Set Vref, RX VrefLevel [Byte0]: 61
7950 23:35:11.979764 [Byte1]: 61
7951 23:35:11.983821
7952 23:35:11.984382 Set Vref, RX VrefLevel [Byte0]: 62
7953 23:35:11.987052 [Byte1]: 62
7954 23:35:11.991388
7955 23:35:11.991951 Set Vref, RX VrefLevel [Byte0]: 63
7956 23:35:11.994505 [Byte1]: 63
7957 23:35:11.998561
7958 23:35:11.999118 Set Vref, RX VrefLevel [Byte0]: 64
7959 23:35:12.001860 [Byte1]: 64
7960 23:35:12.005894
7961 23:35:12.006365 Set Vref, RX VrefLevel [Byte0]: 65
7962 23:35:12.009681 [Byte1]: 65
7963 23:35:12.013948
7964 23:35:12.014509 Set Vref, RX VrefLevel [Byte0]: 66
7965 23:35:12.017172 [Byte1]: 66
7966 23:35:12.021858
7967 23:35:12.022430 Set Vref, RX VrefLevel [Byte0]: 67
7968 23:35:12.024715 [Byte1]: 67
7969 23:35:12.028677
7970 23:35:12.029142 Set Vref, RX VrefLevel [Byte0]: 68
7971 23:35:12.032363 [Byte1]: 68
7972 23:35:12.036648
7973 23:35:12.037228 Set Vref, RX VrefLevel [Byte0]: 69
7974 23:35:12.039812 [Byte1]: 69
7975 23:35:12.044515
7976 23:35:12.044982 Set Vref, RX VrefLevel [Byte0]: 70
7977 23:35:12.047151 [Byte1]: 70
7978 23:35:12.051330
7979 23:35:12.051792 Set Vref, RX VrefLevel [Byte0]: 71
7980 23:35:12.054366 [Byte1]: 71
7981 23:35:12.058886
7982 23:35:12.059352 Set Vref, RX VrefLevel [Byte0]: 72
7983 23:35:12.062186 [Byte1]: 72
7984 23:35:12.066780
7985 23:35:12.067482 Set Vref, RX VrefLevel [Byte0]: 73
7986 23:35:12.069473 [Byte1]: 73
7987 23:35:12.074018
7988 23:35:12.074578 Set Vref, RX VrefLevel [Byte0]: 74
7989 23:35:12.077435 [Byte1]: 74
7990 23:35:12.081387
7991 23:35:12.081888 Set Vref, RX VrefLevel [Byte0]: 75
7992 23:35:12.084900 [Byte1]: 75
7993 23:35:12.089092
7994 23:35:12.089767 Final RX Vref Byte 0 = 56 to rank0
7995 23:35:12.092882 Final RX Vref Byte 1 = 64 to rank0
7996 23:35:12.095820 Final RX Vref Byte 0 = 56 to rank1
7997 23:35:12.098664 Final RX Vref Byte 1 = 64 to rank1==
7998 23:35:12.102135 Dram Type= 6, Freq= 0, CH_0, rank 0
7999 23:35:12.108876 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8000 23:35:12.109446 ==
8001 23:35:12.109869 DQS Delay:
8002 23:35:12.110224 DQS0 = 0, DQS1 = 0
8003 23:35:12.112701 DQM Delay:
8004 23:35:12.113266 DQM0 = 134, DQM1 = 127
8005 23:35:12.115420 DQ Delay:
8006 23:35:12.119080 DQ0 =134, DQ1 =138, DQ2 =134, DQ3 =130
8007 23:35:12.122005 DQ4 =132, DQ5 =124, DQ6 =142, DQ7 =138
8008 23:35:12.125743 DQ8 =116, DQ9 =118, DQ10 =130, DQ11 =120
8009 23:35:12.128907 DQ12 =132, DQ13 =132, DQ14 =138, DQ15 =136
8010 23:35:12.129478
8011 23:35:12.129900
8012 23:35:12.130252
8013 23:35:12.131874 [DramC_TX_OE_Calibration] TA2
8014 23:35:12.135684 Original DQ_B0 (3 6) =30, OEN = 27
8015 23:35:12.138811 Original DQ_B1 (3 6) =30, OEN = 27
8016 23:35:12.142221 24, 0x0, End_B0=24 End_B1=24
8017 23:35:12.142792 25, 0x0, End_B0=25 End_B1=25
8018 23:35:12.145557 26, 0x0, End_B0=26 End_B1=26
8019 23:35:12.148990 27, 0x0, End_B0=27 End_B1=27
8020 23:35:12.151792 28, 0x0, End_B0=28 End_B1=28
8021 23:35:12.155256 29, 0x0, End_B0=29 End_B1=29
8022 23:35:12.155850 30, 0x0, End_B0=30 End_B1=30
8023 23:35:12.158807 31, 0x4545, End_B0=30 End_B1=30
8024 23:35:12.162179 Byte0 end_step=30 best_step=27
8025 23:35:12.165184 Byte1 end_step=30 best_step=27
8026 23:35:12.168296 Byte0 TX OE(2T, 0.5T) = (3, 3)
8027 23:35:12.171710 Byte1 TX OE(2T, 0.5T) = (3, 3)
8028 23:35:12.172427
8029 23:35:12.172813
8030 23:35:12.178244 [DQSOSCAuto] RK0, (LSB)MR18= 0x2622, (MSB)MR19= 0x303, tDQSOscB0 = 392 ps tDQSOscB1 = 390 ps
8031 23:35:12.181733 CH0 RK0: MR19=303, MR18=2622
8032 23:35:12.188172 CH0_RK0: MR19=0x303, MR18=0x2622, DQSOSC=390, MR23=63, INC=24, DEC=16
8033 23:35:12.188736
8034 23:35:12.191355 ----->DramcWriteLeveling(PI) begin...
8035 23:35:12.191928 ==
8036 23:35:12.194471 Dram Type= 6, Freq= 0, CH_0, rank 1
8037 23:35:12.198152 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8038 23:35:12.198751 ==
8039 23:35:12.201318 Write leveling (Byte 0): 34 => 34
8040 23:35:12.204306 Write leveling (Byte 1): 27 => 27
8041 23:35:12.207668 DramcWriteLeveling(PI) end<-----
8042 23:35:12.208135
8043 23:35:12.208506 ==
8044 23:35:12.211466 Dram Type= 6, Freq= 0, CH_0, rank 1
8045 23:35:12.214422 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8046 23:35:12.214895 ==
8047 23:35:12.218176 [Gating] SW mode calibration
8048 23:35:12.224929 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8049 23:35:12.231283 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8050 23:35:12.234618 1 4 0 | B1->B0 | 2323 2524 | 0 1 | (0 0) (0 0)
8051 23:35:12.241430 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8052 23:35:12.244488 1 4 8 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
8053 23:35:12.248322 1 4 12 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
8054 23:35:12.254212 1 4 16 | B1->B0 | 2a2a 3535 | 1 0 | (1 1) (0 0)
8055 23:35:12.257746 1 4 20 | B1->B0 | 3434 3636 | 1 0 | (1 1) (0 0)
8056 23:35:12.260819 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8057 23:35:12.267220 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8058 23:35:12.271467 1 5 0 | B1->B0 | 3434 3636 | 1 1 | (1 1) (1 1)
8059 23:35:12.274351 1 5 4 | B1->B0 | 3434 3535 | 1 0 | (1 1) (1 1)
8060 23:35:12.281298 1 5 8 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
8061 23:35:12.284105 1 5 12 | B1->B0 | 3434 3333 | 1 0 | (1 0) (1 0)
8062 23:35:12.287250 1 5 16 | B1->B0 | 2e2e 2929 | 0 0 | (0 1) (1 0)
8063 23:35:12.294402 1 5 20 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
8064 23:35:12.297938 1 5 24 | B1->B0 | 2323 3130 | 0 1 | (0 0) (1 1)
8065 23:35:12.300704 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8066 23:35:12.307405 1 6 0 | B1->B0 | 2323 2828 | 0 1 | (0 0) (0 0)
8067 23:35:12.310355 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8068 23:35:12.314103 1 6 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
8069 23:35:12.321079 1 6 12 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (1 1)
8070 23:35:12.324075 1 6 16 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
8071 23:35:12.327174 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8072 23:35:12.330530 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8073 23:35:12.337173 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8074 23:35:12.341270 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8075 23:35:12.344016 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8076 23:35:12.350513 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8077 23:35:12.353660 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8078 23:35:12.357489 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8079 23:35:12.364665 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8080 23:35:12.367412 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8081 23:35:12.371114 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8082 23:35:12.377366 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8083 23:35:12.380767 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8084 23:35:12.384141 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8085 23:35:12.391093 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8086 23:35:12.393700 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8087 23:35:12.397170 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8088 23:35:12.404017 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8089 23:35:12.407227 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8090 23:35:12.410418 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8091 23:35:12.416984 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8092 23:35:12.420584 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8093 23:35:12.423625 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8094 23:35:12.430360 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8095 23:35:12.430932 Total UI for P1: 0, mck2ui 16
8096 23:35:12.437051 best dqsien dly found for B0: ( 1, 9, 10)
8097 23:35:12.437655 Total UI for P1: 0, mck2ui 16
8098 23:35:12.440209 best dqsien dly found for B1: ( 1, 9, 12)
8099 23:35:12.447186 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8100 23:35:12.450481 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8101 23:35:12.451131
8102 23:35:12.453215 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8103 23:35:12.457021 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8104 23:35:12.459977 [Gating] SW calibration Done
8105 23:35:12.460445 ==
8106 23:35:12.463824 Dram Type= 6, Freq= 0, CH_0, rank 1
8107 23:35:12.466910 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8108 23:35:12.467490 ==
8109 23:35:12.469956 RX Vref Scan: 0
8110 23:35:12.470422
8111 23:35:12.470797 RX Vref 0 -> 0, step: 1
8112 23:35:12.471147
8113 23:35:12.473323 RX Delay 0 -> 252, step: 8
8114 23:35:12.476493 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8115 23:35:12.483240 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8116 23:35:12.486626 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8117 23:35:12.490259 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8118 23:35:12.493034 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8119 23:35:12.496337 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8120 23:35:12.499747 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8121 23:35:12.506269 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8122 23:35:12.510089 iDelay=200, Bit 8, Center 123 (72 ~ 175) 104
8123 23:35:12.513524 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8124 23:35:12.516698 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8125 23:35:12.523161 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8126 23:35:12.526536 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8127 23:35:12.529706 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8128 23:35:12.533091 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8129 23:35:12.536105 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8130 23:35:12.539492 ==
8131 23:35:12.539918 Dram Type= 6, Freq= 0, CH_0, rank 1
8132 23:35:12.546410 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8133 23:35:12.546928 ==
8134 23:35:12.547274 DQS Delay:
8135 23:35:12.549517 DQS0 = 0, DQS1 = 0
8136 23:35:12.549992 DQM Delay:
8137 23:35:12.552763 DQM0 = 137, DQM1 = 130
8138 23:35:12.553243 DQ Delay:
8139 23:35:12.556152 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
8140 23:35:12.559903 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8141 23:35:12.562898 DQ8 =123, DQ9 =119, DQ10 =131, DQ11 =123
8142 23:35:12.566114 DQ12 =135, DQ13 =135, DQ14 =139, DQ15 =139
8143 23:35:12.566539
8144 23:35:12.566874
8145 23:35:12.567195 ==
8146 23:35:12.569557 Dram Type= 6, Freq= 0, CH_0, rank 1
8147 23:35:12.576229 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8148 23:35:12.576767 ==
8149 23:35:12.577112
8150 23:35:12.577430
8151 23:35:12.577782 TX Vref Scan disable
8152 23:35:12.579877 == TX Byte 0 ==
8153 23:35:12.582999 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8154 23:35:12.586435 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8155 23:35:12.589940 == TX Byte 1 ==
8156 23:35:12.593489 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8157 23:35:12.599882 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8158 23:35:12.600410 ==
8159 23:35:12.602803 Dram Type= 6, Freq= 0, CH_0, rank 1
8160 23:35:12.605933 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8161 23:35:12.606404 ==
8162 23:35:12.619686
8163 23:35:12.622940 TX Vref early break, caculate TX vref
8164 23:35:12.626043 TX Vref=16, minBit 0, minWin=23, winSum=385
8165 23:35:12.629294 TX Vref=18, minBit 0, minWin=23, winSum=398
8166 23:35:12.632607 TX Vref=20, minBit 1, minWin=23, winSum=405
8167 23:35:12.636607 TX Vref=22, minBit 1, minWin=24, winSum=411
8168 23:35:12.639890 TX Vref=24, minBit 1, minWin=25, winSum=420
8169 23:35:12.646135 TX Vref=26, minBit 1, minWin=25, winSum=429
8170 23:35:12.649200 TX Vref=28, minBit 1, minWin=25, winSum=423
8171 23:35:12.652410 TX Vref=30, minBit 1, minWin=25, winSum=422
8172 23:35:12.656228 TX Vref=32, minBit 0, minWin=25, winSum=412
8173 23:35:12.658939 TX Vref=34, minBit 0, minWin=24, winSum=403
8174 23:35:12.665418 [TxChooseVref] Worse bit 1, Min win 25, Win sum 429, Final Vref 26
8175 23:35:12.665893
8176 23:35:12.668689 Final TX Range 0 Vref 26
8177 23:35:12.669155
8178 23:35:12.669534 ==
8179 23:35:12.672105 Dram Type= 6, Freq= 0, CH_0, rank 1
8180 23:35:12.675795 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8181 23:35:12.676232 ==
8182 23:35:12.676572
8183 23:35:12.676888
8184 23:35:12.678825 TX Vref Scan disable
8185 23:35:12.686045 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8186 23:35:12.686580 == TX Byte 0 ==
8187 23:35:12.688937 u2DelayCellOfst[0]=13 cells (4 PI)
8188 23:35:12.692142 u2DelayCellOfst[1]=16 cells (5 PI)
8189 23:35:12.696004 u2DelayCellOfst[2]=10 cells (3 PI)
8190 23:35:12.698463 u2DelayCellOfst[3]=10 cells (3 PI)
8191 23:35:12.702291 u2DelayCellOfst[4]=6 cells (2 PI)
8192 23:35:12.705708 u2DelayCellOfst[5]=0 cells (0 PI)
8193 23:35:12.708983 u2DelayCellOfst[6]=13 cells (4 PI)
8194 23:35:12.712248 u2DelayCellOfst[7]=16 cells (5 PI)
8195 23:35:12.715666 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8196 23:35:12.718962 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8197 23:35:12.722014 == TX Byte 1 ==
8198 23:35:12.725238 u2DelayCellOfst[8]=3 cells (1 PI)
8199 23:35:12.725811 u2DelayCellOfst[9]=0 cells (0 PI)
8200 23:35:12.728474 u2DelayCellOfst[10]=6 cells (2 PI)
8201 23:35:12.732477 u2DelayCellOfst[11]=3 cells (1 PI)
8202 23:35:12.735040 u2DelayCellOfst[12]=10 cells (3 PI)
8203 23:35:12.738418 u2DelayCellOfst[13]=10 cells (3 PI)
8204 23:35:12.741712 u2DelayCellOfst[14]=16 cells (5 PI)
8205 23:35:12.745787 u2DelayCellOfst[15]=10 cells (3 PI)
8206 23:35:12.748860 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8207 23:35:12.754881 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8208 23:35:12.755312 DramC Write-DBI on
8209 23:35:12.755654 ==
8210 23:35:12.758213 Dram Type= 6, Freq= 0, CH_0, rank 1
8211 23:35:12.765262 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8212 23:35:12.765847 ==
8213 23:35:12.766204
8214 23:35:12.766521
8215 23:35:12.766827 TX Vref Scan disable
8216 23:35:12.769050 == TX Byte 0 ==
8217 23:35:12.772240 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
8218 23:35:12.775363 == TX Byte 1 ==
8219 23:35:12.779212 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8220 23:35:12.782304 DramC Write-DBI off
8221 23:35:12.782865
8222 23:35:12.783237 [DATLAT]
8223 23:35:12.783583 Freq=1600, CH0 RK1
8224 23:35:12.783918
8225 23:35:12.785262 DATLAT Default: 0xf
8226 23:35:12.785756 0, 0xFFFF, sum = 0
8227 23:35:12.788769 1, 0xFFFF, sum = 0
8228 23:35:12.792060 2, 0xFFFF, sum = 0
8229 23:35:12.792667 3, 0xFFFF, sum = 0
8230 23:35:12.796057 4, 0xFFFF, sum = 0
8231 23:35:12.796632 5, 0xFFFF, sum = 0
8232 23:35:12.799149 6, 0xFFFF, sum = 0
8233 23:35:12.799716 7, 0xFFFF, sum = 0
8234 23:35:12.802575 8, 0xFFFF, sum = 0
8235 23:35:12.803149 9, 0xFFFF, sum = 0
8236 23:35:12.805503 10, 0xFFFF, sum = 0
8237 23:35:12.806055 11, 0xFFFF, sum = 0
8238 23:35:12.809140 12, 0xFFFF, sum = 0
8239 23:35:12.809767 13, 0xFFFF, sum = 0
8240 23:35:12.811976 14, 0x0, sum = 1
8241 23:35:12.812456 15, 0x0, sum = 2
8242 23:35:12.815828 16, 0x0, sum = 3
8243 23:35:12.816402 17, 0x0, sum = 4
8244 23:35:12.819142 best_step = 15
8245 23:35:12.819715
8246 23:35:12.820091 ==
8247 23:35:12.822314 Dram Type= 6, Freq= 0, CH_0, rank 1
8248 23:35:12.825990 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8249 23:35:12.826564 ==
8250 23:35:12.826947 RX Vref Scan: 0
8251 23:35:12.828785
8252 23:35:12.829250 RX Vref 0 -> 0, step: 1
8253 23:35:12.829710
8254 23:35:12.832429 RX Delay 19 -> 252, step: 4
8255 23:35:12.835274 iDelay=191, Bit 0, Center 134 (83 ~ 186) 104
8256 23:35:12.842309 iDelay=191, Bit 1, Center 138 (91 ~ 186) 96
8257 23:35:12.845630 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8258 23:35:12.849473 iDelay=191, Bit 3, Center 132 (79 ~ 186) 108
8259 23:35:12.852229 iDelay=191, Bit 4, Center 136 (87 ~ 186) 100
8260 23:35:12.855298 iDelay=191, Bit 5, Center 124 (71 ~ 178) 108
8261 23:35:12.862398 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8262 23:35:12.866054 iDelay=191, Bit 7, Center 140 (91 ~ 190) 100
8263 23:35:12.868691 iDelay=191, Bit 8, Center 120 (71 ~ 170) 100
8264 23:35:12.872135 iDelay=191, Bit 9, Center 116 (67 ~ 166) 100
8265 23:35:12.875754 iDelay=191, Bit 10, Center 130 (79 ~ 182) 104
8266 23:35:12.881648 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8267 23:35:12.885106 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
8268 23:35:12.888784 iDelay=191, Bit 13, Center 132 (83 ~ 182) 100
8269 23:35:12.891974 iDelay=191, Bit 14, Center 134 (83 ~ 186) 104
8270 23:35:12.895149 iDelay=191, Bit 15, Center 134 (87 ~ 182) 96
8271 23:35:12.898343 ==
8272 23:35:12.901942 Dram Type= 6, Freq= 0, CH_0, rank 1
8273 23:35:12.904969 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8274 23:35:12.905536 ==
8275 23:35:12.906017 DQS Delay:
8276 23:35:12.908340 DQS0 = 0, DQS1 = 0
8277 23:35:12.908763 DQM Delay:
8278 23:35:12.911314 DQM0 = 134, DQM1 = 127
8279 23:35:12.911743 DQ Delay:
8280 23:35:12.915541 DQ0 =134, DQ1 =138, DQ2 =130, DQ3 =132
8281 23:35:12.918100 DQ4 =136, DQ5 =124, DQ6 =140, DQ7 =140
8282 23:35:12.921816 DQ8 =120, DQ9 =116, DQ10 =130, DQ11 =118
8283 23:35:12.925450 DQ12 =134, DQ13 =132, DQ14 =134, DQ15 =134
8284 23:35:12.926034
8285 23:35:12.926379
8286 23:35:12.926693
8287 23:35:12.928392 [DramC_TX_OE_Calibration] TA2
8288 23:35:12.931649 Original DQ_B0 (3 6) =30, OEN = 27
8289 23:35:12.935580 Original DQ_B1 (3 6) =30, OEN = 27
8290 23:35:12.938476 24, 0x0, End_B0=24 End_B1=24
8291 23:35:12.941903 25, 0x0, End_B0=25 End_B1=25
8292 23:35:12.942485 26, 0x0, End_B0=26 End_B1=26
8293 23:35:12.945432 27, 0x0, End_B0=27 End_B1=27
8294 23:35:12.948279 28, 0x0, End_B0=28 End_B1=28
8295 23:35:12.951663 29, 0x0, End_B0=29 End_B1=29
8296 23:35:12.952098 30, 0x0, End_B0=30 End_B1=30
8297 23:35:12.954888 31, 0x4545, End_B0=30 End_B1=30
8298 23:35:12.958919 Byte0 end_step=30 best_step=27
8299 23:35:12.962182 Byte1 end_step=30 best_step=27
8300 23:35:12.965127 Byte0 TX OE(2T, 0.5T) = (3, 3)
8301 23:35:12.968861 Byte1 TX OE(2T, 0.5T) = (3, 3)
8302 23:35:12.969394
8303 23:35:12.969988
8304 23:35:12.974966 [DQSOSCAuto] RK1, (LSB)MR18= 0x2009, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 393 ps
8305 23:35:12.978131 CH0 RK1: MR19=303, MR18=2009
8306 23:35:12.985178 CH0_RK1: MR19=0x303, MR18=0x2009, DQSOSC=393, MR23=63, INC=23, DEC=15
8307 23:35:12.988393 [RxdqsGatingPostProcess] freq 1600
8308 23:35:12.991497 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8309 23:35:12.994768 best DQS0 dly(2T, 0.5T) = (1, 1)
8310 23:35:12.998066 best DQS1 dly(2T, 0.5T) = (1, 1)
8311 23:35:13.001470 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8312 23:35:13.004480 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8313 23:35:13.007992 best DQS0 dly(2T, 0.5T) = (1, 1)
8314 23:35:13.011544 best DQS1 dly(2T, 0.5T) = (1, 1)
8315 23:35:13.014999 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8316 23:35:13.018138 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8317 23:35:13.021086 Pre-setting of DQS Precalculation
8318 23:35:13.024666 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8319 23:35:13.025236 ==
8320 23:35:13.027708 Dram Type= 6, Freq= 0, CH_1, rank 0
8321 23:35:13.035107 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8322 23:35:13.035679 ==
8323 23:35:13.037984 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8324 23:35:13.045075 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8325 23:35:13.047798 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8326 23:35:13.054128 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8327 23:35:13.061996 [CA 0] Center 41 (11~71) winsize 61
8328 23:35:13.065378 [CA 1] Center 41 (12~71) winsize 60
8329 23:35:13.069332 [CA 2] Center 38 (9~68) winsize 60
8330 23:35:13.071921 [CA 3] Center 37 (8~66) winsize 59
8331 23:35:13.075308 [CA 4] Center 38 (9~67) winsize 59
8332 23:35:13.078564 [CA 5] Center 37 (8~66) winsize 59
8333 23:35:13.079034
8334 23:35:13.082161 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8335 23:35:13.082629
8336 23:35:13.085472 [CATrainingPosCal] consider 1 rank data
8337 23:35:13.088678 u2DelayCellTimex100 = 290/100 ps
8338 23:35:13.091904 CA0 delay=41 (11~71),Diff = 4 PI (13 cell)
8339 23:35:13.099015 CA1 delay=41 (12~71),Diff = 4 PI (13 cell)
8340 23:35:13.101790 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8341 23:35:13.105031 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8342 23:35:13.108217 CA4 delay=38 (9~67),Diff = 1 PI (3 cell)
8343 23:35:13.112164 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8344 23:35:13.112778
8345 23:35:13.115255 CA PerBit enable=1, Macro0, CA PI delay=37
8346 23:35:13.115822
8347 23:35:13.118254 [CBTSetCACLKResult] CA Dly = 37
8348 23:35:13.121630 CS Dly: 10 (0~41)
8349 23:35:13.125423 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8350 23:35:13.128266 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8351 23:35:13.128757 ==
8352 23:35:13.131923 Dram Type= 6, Freq= 0, CH_1, rank 1
8353 23:35:13.135018 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8354 23:35:13.135709 ==
8355 23:35:13.141722 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8356 23:35:13.144720 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8357 23:35:13.151487 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8358 23:35:13.154683 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8359 23:35:13.164929 [CA 0] Center 42 (12~72) winsize 61
8360 23:35:13.168561 [CA 1] Center 42 (12~72) winsize 61
8361 23:35:13.171654 [CA 2] Center 38 (9~68) winsize 60
8362 23:35:13.175034 [CA 3] Center 38 (8~68) winsize 61
8363 23:35:13.178556 [CA 4] Center 38 (8~68) winsize 61
8364 23:35:13.181522 [CA 5] Center 37 (8~67) winsize 60
8365 23:35:13.182123
8366 23:35:13.185158 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8367 23:35:13.185738
8368 23:35:13.188095 [CATrainingPosCal] consider 2 rank data
8369 23:35:13.191736 u2DelayCellTimex100 = 290/100 ps
8370 23:35:13.195305 CA0 delay=41 (12~71),Diff = 4 PI (13 cell)
8371 23:35:13.202227 CA1 delay=41 (12~71),Diff = 4 PI (13 cell)
8372 23:35:13.204850 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8373 23:35:13.208206 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8374 23:35:13.211607 CA4 delay=38 (9~67),Diff = 1 PI (3 cell)
8375 23:35:13.215378 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8376 23:35:13.215946
8377 23:35:13.218198 CA PerBit enable=1, Macro0, CA PI delay=37
8378 23:35:13.218662
8379 23:35:13.221492 [CBTSetCACLKResult] CA Dly = 37
8380 23:35:13.224943 CS Dly: 12 (0~45)
8381 23:35:13.228020 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8382 23:35:13.231450 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8383 23:35:13.231920
8384 23:35:13.235048 ----->DramcWriteLeveling(PI) begin...
8385 23:35:13.235626 ==
8386 23:35:13.238367 Dram Type= 6, Freq= 0, CH_1, rank 0
8387 23:35:13.244879 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8388 23:35:13.245343 ==
8389 23:35:13.248129 Write leveling (Byte 0): 25 => 25
8390 23:35:13.248702 Write leveling (Byte 1): 27 => 27
8391 23:35:13.251670 DramcWriteLeveling(PI) end<-----
8392 23:35:13.252271
8393 23:35:13.252644 ==
8394 23:35:13.254318 Dram Type= 6, Freq= 0, CH_1, rank 0
8395 23:35:13.261305 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8396 23:35:13.261926 ==
8397 23:35:13.264706 [Gating] SW mode calibration
8398 23:35:13.271092 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8399 23:35:13.274474 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8400 23:35:13.281275 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8401 23:35:13.284537 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8402 23:35:13.288141 1 4 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
8403 23:35:13.294583 1 4 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8404 23:35:13.297493 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8405 23:35:13.301357 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8406 23:35:13.307555 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8407 23:35:13.310999 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8408 23:35:13.314576 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8409 23:35:13.321188 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8410 23:35:13.324773 1 5 8 | B1->B0 | 3434 3030 | 1 1 | (1 0) (1 0)
8411 23:35:13.327909 1 5 12 | B1->B0 | 2929 2323 | 0 0 | (1 0) (0 0)
8412 23:35:13.331178 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8413 23:35:13.337683 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8414 23:35:13.340770 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8415 23:35:13.344438 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8416 23:35:13.350855 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8417 23:35:13.354270 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8418 23:35:13.357424 1 6 8 | B1->B0 | 2424 4141 | 0 0 | (0 0) (0 0)
8419 23:35:13.364354 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8420 23:35:13.367818 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8421 23:35:13.370904 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8422 23:35:13.377383 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8423 23:35:13.380900 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8424 23:35:13.384208 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8425 23:35:13.390719 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8426 23:35:13.394329 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8427 23:35:13.397264 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8428 23:35:13.403811 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8429 23:35:13.407306 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8430 23:35:13.410491 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8431 23:35:13.417322 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8432 23:35:13.421185 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8433 23:35:13.423708 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8434 23:35:13.431164 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8435 23:35:13.434045 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8436 23:35:13.437492 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8437 23:35:13.443922 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8438 23:35:13.447521 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8439 23:35:13.450512 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8440 23:35:13.456789 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8441 23:35:13.460459 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8442 23:35:13.463372 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8443 23:35:13.470507 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8444 23:35:13.473405 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8445 23:35:13.477233 Total UI for P1: 0, mck2ui 16
8446 23:35:13.479885 best dqsien dly found for B0: ( 1, 9, 12)
8447 23:35:13.483132 Total UI for P1: 0, mck2ui 16
8448 23:35:13.487134 best dqsien dly found for B1: ( 1, 9, 10)
8449 23:35:13.489862 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8450 23:35:13.493665 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8451 23:35:13.494192
8452 23:35:13.496499 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8453 23:35:13.500078 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8454 23:35:13.503457 [Gating] SW calibration Done
8455 23:35:13.503884 ==
8456 23:35:13.506561 Dram Type= 6, Freq= 0, CH_1, rank 0
8457 23:35:13.509939 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8458 23:35:13.510368 ==
8459 23:35:13.513067 RX Vref Scan: 0
8460 23:35:13.513496
8461 23:35:13.517214 RX Vref 0 -> 0, step: 1
8462 23:35:13.517791
8463 23:35:13.518143 RX Delay 0 -> 252, step: 8
8464 23:35:13.523482 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8465 23:35:13.526825 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8466 23:35:13.529840 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8467 23:35:13.533167 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8468 23:35:13.536564 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8469 23:35:13.543195 iDelay=200, Bit 5, Center 151 (104 ~ 199) 96
8470 23:35:13.546543 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8471 23:35:13.550164 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8472 23:35:13.553707 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
8473 23:35:13.556396 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8474 23:35:13.563359 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8475 23:35:13.566434 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8476 23:35:13.569556 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8477 23:35:13.573118 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8478 23:35:13.576774 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8479 23:35:13.582967 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8480 23:35:13.583539 ==
8481 23:35:13.586689 Dram Type= 6, Freq= 0, CH_1, rank 0
8482 23:35:13.590030 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8483 23:35:13.590565 ==
8484 23:35:13.590923 DQS Delay:
8485 23:35:13.593732 DQS0 = 0, DQS1 = 0
8486 23:35:13.594308 DQM Delay:
8487 23:35:13.596620 DQM0 = 137, DQM1 = 132
8488 23:35:13.597187 DQ Delay:
8489 23:35:13.599952 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8490 23:35:13.603127 DQ4 =131, DQ5 =151, DQ6 =147, DQ7 =135
8491 23:35:13.607272 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =127
8492 23:35:13.610023 DQ12 =139, DQ13 =143, DQ14 =139, DQ15 =139
8493 23:35:13.610492
8494 23:35:13.612968
8495 23:35:13.613559 ==
8496 23:35:13.616374 Dram Type= 6, Freq= 0, CH_1, rank 0
8497 23:35:13.619232 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8498 23:35:13.619717 ==
8499 23:35:13.620303
8500 23:35:13.620682
8501 23:35:13.623186 TX Vref Scan disable
8502 23:35:13.623766 == TX Byte 0 ==
8503 23:35:13.629390 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8504 23:35:13.632952 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8505 23:35:13.633494 == TX Byte 1 ==
8506 23:35:13.636025 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8507 23:35:13.642917 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8508 23:35:13.643445 ==
8509 23:35:13.646248 Dram Type= 6, Freq= 0, CH_1, rank 0
8510 23:35:13.649505 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8511 23:35:13.650127 ==
8512 23:35:13.662449
8513 23:35:13.666185 TX Vref early break, caculate TX vref
8514 23:35:13.669442 TX Vref=16, minBit 0, minWin=22, winSum=377
8515 23:35:13.672364 TX Vref=18, minBit 9, minWin=22, winSum=388
8516 23:35:13.675877 TX Vref=20, minBit 0, minWin=23, winSum=400
8517 23:35:13.678946 TX Vref=22, minBit 0, minWin=25, winSum=407
8518 23:35:13.682473 TX Vref=24, minBit 0, minWin=25, winSum=413
8519 23:35:13.689198 TX Vref=26, minBit 0, minWin=25, winSum=424
8520 23:35:13.693034 TX Vref=28, minBit 2, minWin=25, winSum=428
8521 23:35:13.695508 TX Vref=30, minBit 2, minWin=25, winSum=421
8522 23:35:13.699290 TX Vref=32, minBit 0, minWin=24, winSum=414
8523 23:35:13.702315 TX Vref=34, minBit 0, minWin=24, winSum=403
8524 23:35:13.709377 [TxChooseVref] Worse bit 2, Min win 25, Win sum 428, Final Vref 28
8525 23:35:13.709984
8526 23:35:13.712369 Final TX Range 0 Vref 28
8527 23:35:13.712835
8528 23:35:13.713204 ==
8529 23:35:13.715834 Dram Type= 6, Freq= 0, CH_1, rank 0
8530 23:35:13.718691 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8531 23:35:13.719205 ==
8532 23:35:13.719586
8533 23:35:13.719937
8534 23:35:13.722530 TX Vref Scan disable
8535 23:35:13.728772 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8536 23:35:13.729462 == TX Byte 0 ==
8537 23:35:13.732103 u2DelayCellOfst[0]=16 cells (5 PI)
8538 23:35:13.735570 u2DelayCellOfst[1]=10 cells (3 PI)
8539 23:35:13.738782 u2DelayCellOfst[2]=0 cells (0 PI)
8540 23:35:13.742275 u2DelayCellOfst[3]=6 cells (2 PI)
8541 23:35:13.745238 u2DelayCellOfst[4]=10 cells (3 PI)
8542 23:35:13.748902 u2DelayCellOfst[5]=16 cells (5 PI)
8543 23:35:13.752168 u2DelayCellOfst[6]=16 cells (5 PI)
8544 23:35:13.752782 u2DelayCellOfst[7]=6 cells (2 PI)
8545 23:35:13.758606 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8546 23:35:13.762158 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8547 23:35:13.762734 == TX Byte 1 ==
8548 23:35:13.765371 u2DelayCellOfst[8]=0 cells (0 PI)
8549 23:35:13.769079 u2DelayCellOfst[9]=3 cells (1 PI)
8550 23:35:13.771676 u2DelayCellOfst[10]=10 cells (3 PI)
8551 23:35:13.775296 u2DelayCellOfst[11]=3 cells (1 PI)
8552 23:35:13.778488 u2DelayCellOfst[12]=16 cells (5 PI)
8553 23:35:13.781802 u2DelayCellOfst[13]=16 cells (5 PI)
8554 23:35:13.785755 u2DelayCellOfst[14]=16 cells (5 PI)
8555 23:35:13.788516 u2DelayCellOfst[15]=16 cells (5 PI)
8556 23:35:13.792378 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8557 23:35:13.798574 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8558 23:35:13.799146 DramC Write-DBI on
8559 23:35:13.799525 ==
8560 23:35:13.801926 Dram Type= 6, Freq= 0, CH_1, rank 0
8561 23:35:13.805214 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8562 23:35:13.808137 ==
8563 23:35:13.808597
8564 23:35:13.808966
8565 23:35:13.809315 TX Vref Scan disable
8566 23:35:13.811620 == TX Byte 0 ==
8567 23:35:13.815050 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8568 23:35:13.818535 == TX Byte 1 ==
8569 23:35:13.822212 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8570 23:35:13.822745 DramC Write-DBI off
8571 23:35:13.825082
8572 23:35:13.825497 [DATLAT]
8573 23:35:13.825861 Freq=1600, CH1 RK0
8574 23:35:13.826178
8575 23:35:13.828288 DATLAT Default: 0xf
8576 23:35:13.828816 0, 0xFFFF, sum = 0
8577 23:35:13.831679 1, 0xFFFF, sum = 0
8578 23:35:13.832104 2, 0xFFFF, sum = 0
8579 23:35:13.834739 3, 0xFFFF, sum = 0
8580 23:35:13.838367 4, 0xFFFF, sum = 0
8581 23:35:13.838793 5, 0xFFFF, sum = 0
8582 23:35:13.841361 6, 0xFFFF, sum = 0
8583 23:35:13.841811 7, 0xFFFF, sum = 0
8584 23:35:13.845028 8, 0xFFFF, sum = 0
8585 23:35:13.845569 9, 0xFFFF, sum = 0
8586 23:35:13.848234 10, 0xFFFF, sum = 0
8587 23:35:13.848659 11, 0xFFFF, sum = 0
8588 23:35:13.851865 12, 0xFFFF, sum = 0
8589 23:35:13.852402 13, 0xFFFF, sum = 0
8590 23:35:13.855020 14, 0x0, sum = 1
8591 23:35:13.855562 15, 0x0, sum = 2
8592 23:35:13.857976 16, 0x0, sum = 3
8593 23:35:13.858407 17, 0x0, sum = 4
8594 23:35:13.861284 best_step = 15
8595 23:35:13.861942
8596 23:35:13.862300 ==
8597 23:35:13.864711 Dram Type= 6, Freq= 0, CH_1, rank 0
8598 23:35:13.868383 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8599 23:35:13.868914 ==
8600 23:35:13.871692 RX Vref Scan: 1
8601 23:35:13.872111
8602 23:35:13.872514 Set Vref Range= 24 -> 127
8603 23:35:13.872851
8604 23:35:13.875031 RX Vref 24 -> 127, step: 1
8605 23:35:13.875563
8606 23:35:13.877779 RX Delay 27 -> 252, step: 4
8607 23:35:13.878203
8608 23:35:13.881901 Set Vref, RX VrefLevel [Byte0]: 24
8609 23:35:13.884708 [Byte1]: 24
8610 23:35:13.885241
8611 23:35:13.888184 Set Vref, RX VrefLevel [Byte0]: 25
8612 23:35:13.891495 [Byte1]: 25
8613 23:35:13.892028
8614 23:35:13.894392 Set Vref, RX VrefLevel [Byte0]: 26
8615 23:35:13.897939 [Byte1]: 26
8616 23:35:13.902123
8617 23:35:13.902654 Set Vref, RX VrefLevel [Byte0]: 27
8618 23:35:13.905120 [Byte1]: 27
8619 23:35:13.909151
8620 23:35:13.909572 Set Vref, RX VrefLevel [Byte0]: 28
8621 23:35:13.913067 [Byte1]: 28
8622 23:35:13.917054
8623 23:35:13.917683 Set Vref, RX VrefLevel [Byte0]: 29
8624 23:35:13.920056 [Byte1]: 29
8625 23:35:13.924799
8626 23:35:13.925330 Set Vref, RX VrefLevel [Byte0]: 30
8627 23:35:13.927788 [Byte1]: 30
8628 23:35:13.932320
8629 23:35:13.932893 Set Vref, RX VrefLevel [Byte0]: 31
8630 23:35:13.935645 [Byte1]: 31
8631 23:35:13.939763
8632 23:35:13.940341 Set Vref, RX VrefLevel [Byte0]: 32
8633 23:35:13.943030 [Byte1]: 32
8634 23:35:13.947142
8635 23:35:13.947758 Set Vref, RX VrefLevel [Byte0]: 33
8636 23:35:13.950453 [Byte1]: 33
8637 23:35:13.955164
8638 23:35:13.955795 Set Vref, RX VrefLevel [Byte0]: 34
8639 23:35:13.958062 [Byte1]: 34
8640 23:35:13.962384
8641 23:35:13.962853 Set Vref, RX VrefLevel [Byte0]: 35
8642 23:35:13.965555 [Byte1]: 35
8643 23:35:13.969704
8644 23:35:13.970269 Set Vref, RX VrefLevel [Byte0]: 36
8645 23:35:13.972538 [Byte1]: 36
8646 23:35:13.977148
8647 23:35:13.977731 Set Vref, RX VrefLevel [Byte0]: 37
8648 23:35:13.980881 [Byte1]: 37
8649 23:35:13.984986
8650 23:35:13.985518 Set Vref, RX VrefLevel [Byte0]: 38
8651 23:35:13.988098 [Byte1]: 38
8652 23:35:13.992175
8653 23:35:13.992711 Set Vref, RX VrefLevel [Byte0]: 39
8654 23:35:13.995524 [Byte1]: 39
8655 23:35:14.000021
8656 23:35:14.000448 Set Vref, RX VrefLevel [Byte0]: 40
8657 23:35:14.003412 [Byte1]: 40
8658 23:35:14.007503
8659 23:35:14.008095 Set Vref, RX VrefLevel [Byte0]: 41
8660 23:35:14.010302 [Byte1]: 41
8661 23:35:14.014620
8662 23:35:14.015043 Set Vref, RX VrefLevel [Byte0]: 42
8663 23:35:14.018252 [Byte1]: 42
8664 23:35:14.022398
8665 23:35:14.022826 Set Vref, RX VrefLevel [Byte0]: 43
8666 23:35:14.025705 [Byte1]: 43
8667 23:35:14.029838
8668 23:35:14.030465 Set Vref, RX VrefLevel [Byte0]: 44
8669 23:35:14.033236 [Byte1]: 44
8670 23:35:14.038001
8671 23:35:14.038536 Set Vref, RX VrefLevel [Byte0]: 45
8672 23:35:14.040714 [Byte1]: 45
8673 23:35:14.045049
8674 23:35:14.045618 Set Vref, RX VrefLevel [Byte0]: 46
8675 23:35:14.048467 [Byte1]: 46
8676 23:35:14.053073
8677 23:35:14.053647 Set Vref, RX VrefLevel [Byte0]: 47
8678 23:35:14.055979 [Byte1]: 47
8679 23:35:14.059916
8680 23:35:14.060537 Set Vref, RX VrefLevel [Byte0]: 48
8681 23:35:14.063318 [Byte1]: 48
8682 23:35:14.067689
8683 23:35:14.068218 Set Vref, RX VrefLevel [Byte0]: 49
8684 23:35:14.070998 [Byte1]: 49
8685 23:35:14.075039
8686 23:35:14.075571 Set Vref, RX VrefLevel [Byte0]: 50
8687 23:35:14.078509 [Byte1]: 50
8688 23:35:14.082800
8689 23:35:14.083348 Set Vref, RX VrefLevel [Byte0]: 51
8690 23:35:14.086457 [Byte1]: 51
8691 23:35:14.090786
8692 23:35:14.091325 Set Vref, RX VrefLevel [Byte0]: 52
8693 23:35:14.093641 [Byte1]: 52
8694 23:35:14.097954
8695 23:35:14.098562 Set Vref, RX VrefLevel [Byte0]: 53
8696 23:35:14.100894 [Byte1]: 53
8697 23:35:14.105666
8698 23:35:14.106194 Set Vref, RX VrefLevel [Byte0]: 54
8699 23:35:14.108815 [Byte1]: 54
8700 23:35:14.113221
8701 23:35:14.113787 Set Vref, RX VrefLevel [Byte0]: 55
8702 23:35:14.116143 [Byte1]: 55
8703 23:35:14.120099
8704 23:35:14.120521 Set Vref, RX VrefLevel [Byte0]: 56
8705 23:35:14.123561 [Byte1]: 56
8706 23:35:14.128288
8707 23:35:14.128881 Set Vref, RX VrefLevel [Byte0]: 57
8708 23:35:14.131018 [Byte1]: 57
8709 23:35:14.135883
8710 23:35:14.136464 Set Vref, RX VrefLevel [Byte0]: 58
8711 23:35:14.138461 [Byte1]: 58
8712 23:35:14.143308
8713 23:35:14.143881 Set Vref, RX VrefLevel [Byte0]: 59
8714 23:35:14.146546 [Byte1]: 59
8715 23:35:14.150406
8716 23:35:14.150870 Set Vref, RX VrefLevel [Byte0]: 60
8717 23:35:14.154135 [Byte1]: 60
8718 23:35:14.157901
8719 23:35:14.158367 Set Vref, RX VrefLevel [Byte0]: 61
8720 23:35:14.161289 [Byte1]: 61
8721 23:35:14.165949
8722 23:35:14.166520 Set Vref, RX VrefLevel [Byte0]: 62
8723 23:35:14.168522 [Byte1]: 62
8724 23:35:14.173171
8725 23:35:14.173704 Set Vref, RX VrefLevel [Byte0]: 63
8726 23:35:14.176314 [Byte1]: 63
8727 23:35:14.180818
8728 23:35:14.181237 Set Vref, RX VrefLevel [Byte0]: 64
8729 23:35:14.183964 [Byte1]: 64
8730 23:35:14.188109
8731 23:35:14.188641 Set Vref, RX VrefLevel [Byte0]: 65
8732 23:35:14.191279 [Byte1]: 65
8733 23:35:14.195566
8734 23:35:14.196106 Set Vref, RX VrefLevel [Byte0]: 66
8735 23:35:14.199092 [Byte1]: 66
8736 23:35:14.203045
8737 23:35:14.203467 Set Vref, RX VrefLevel [Byte0]: 67
8738 23:35:14.206909 [Byte1]: 67
8739 23:35:14.210696
8740 23:35:14.211121 Set Vref, RX VrefLevel [Byte0]: 68
8741 23:35:14.214170 [Byte1]: 68
8742 23:35:14.218290
8743 23:35:14.218824 Set Vref, RX VrefLevel [Byte0]: 69
8744 23:35:14.221869 [Byte1]: 69
8745 23:35:14.226238
8746 23:35:14.226815 Set Vref, RX VrefLevel [Byte0]: 70
8747 23:35:14.229240 [Byte1]: 70
8748 23:35:14.233390
8749 23:35:14.234010 Set Vref, RX VrefLevel [Byte0]: 71
8750 23:35:14.236831 [Byte1]: 71
8751 23:35:14.240950
8752 23:35:14.241523 Set Vref, RX VrefLevel [Byte0]: 72
8753 23:35:14.244238 [Byte1]: 72
8754 23:35:14.248302
8755 23:35:14.248891 Set Vref, RX VrefLevel [Byte0]: 73
8756 23:35:14.252019 [Byte1]: 73
8757 23:35:14.256589
8758 23:35:14.257164 Set Vref, RX VrefLevel [Byte0]: 74
8759 23:35:14.262369 [Byte1]: 74
8760 23:35:14.262940
8761 23:35:14.266091 Set Vref, RX VrefLevel [Byte0]: 75
8762 23:35:14.269440 [Byte1]: 75
8763 23:35:14.270054
8764 23:35:14.273024 Set Vref, RX VrefLevel [Byte0]: 76
8765 23:35:14.276051 [Byte1]: 76
8766 23:35:14.276624
8767 23:35:14.279246 Set Vref, RX VrefLevel [Byte0]: 77
8768 23:35:14.282327 [Byte1]: 77
8769 23:35:14.286371
8770 23:35:14.287055 Set Vref, RX VrefLevel [Byte0]: 78
8771 23:35:14.289624 [Byte1]: 78
8772 23:35:14.293774
8773 23:35:14.294357 Final RX Vref Byte 0 = 58 to rank0
8774 23:35:14.296931 Final RX Vref Byte 1 = 54 to rank0
8775 23:35:14.300202 Final RX Vref Byte 0 = 58 to rank1
8776 23:35:14.303500 Final RX Vref Byte 1 = 54 to rank1==
8777 23:35:14.307191 Dram Type= 6, Freq= 0, CH_1, rank 0
8778 23:35:14.313766 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8779 23:35:14.314350 ==
8780 23:35:14.314734 DQS Delay:
8781 23:35:14.315091 DQS0 = 0, DQS1 = 0
8782 23:35:14.316600 DQM Delay:
8783 23:35:14.317065 DQM0 = 134, DQM1 = 131
8784 23:35:14.320693 DQ Delay:
8785 23:35:14.323499 DQ0 =140, DQ1 =128, DQ2 =122, DQ3 =130
8786 23:35:14.326754 DQ4 =134, DQ5 =144, DQ6 =144, DQ7 =132
8787 23:35:14.330376 DQ8 =116, DQ9 =122, DQ10 =132, DQ11 =124
8788 23:35:14.333170 DQ12 =138, DQ13 =140, DQ14 =140, DQ15 =140
8789 23:35:14.333795
8790 23:35:14.334176
8791 23:35:14.334528
8792 23:35:14.336829 [DramC_TX_OE_Calibration] TA2
8793 23:35:14.339984 Original DQ_B0 (3 6) =30, OEN = 27
8794 23:35:14.344150 Original DQ_B1 (3 6) =30, OEN = 27
8795 23:35:14.346458 24, 0x0, End_B0=24 End_B1=24
8796 23:35:14.346933 25, 0x0, End_B0=25 End_B1=25
8797 23:35:14.349767 26, 0x0, End_B0=26 End_B1=26
8798 23:35:14.353217 27, 0x0, End_B0=27 End_B1=27
8799 23:35:14.356391 28, 0x0, End_B0=28 End_B1=28
8800 23:35:14.359838 29, 0x0, End_B0=29 End_B1=29
8801 23:35:14.360315 30, 0x0, End_B0=30 End_B1=30
8802 23:35:14.363649 31, 0x4545, End_B0=30 End_B1=30
8803 23:35:14.366507 Byte0 end_step=30 best_step=27
8804 23:35:14.369821 Byte1 end_step=30 best_step=27
8805 23:35:14.372949 Byte0 TX OE(2T, 0.5T) = (3, 3)
8806 23:35:14.377084 Byte1 TX OE(2T, 0.5T) = (3, 3)
8807 23:35:14.377703
8808 23:35:14.378080
8809 23:35:14.383424 [DQSOSCAuto] RK0, (LSB)MR18= 0x1826, (MSB)MR19= 0x303, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
8810 23:35:14.386185 CH1 RK0: MR19=303, MR18=1826
8811 23:35:14.393317 CH1_RK0: MR19=0x303, MR18=0x1826, DQSOSC=390, MR23=63, INC=24, DEC=16
8812 23:35:14.393979
8813 23:35:14.396138 ----->DramcWriteLeveling(PI) begin...
8814 23:35:14.396652 ==
8815 23:35:14.399997 Dram Type= 6, Freq= 0, CH_1, rank 1
8816 23:35:14.403500 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8817 23:35:14.404068 ==
8818 23:35:14.406263 Write leveling (Byte 0): 24 => 24
8819 23:35:14.409438 Write leveling (Byte 1): 28 => 28
8820 23:35:14.413204 DramcWriteLeveling(PI) end<-----
8821 23:35:14.413815
8822 23:35:14.414197 ==
8823 23:35:14.416284 Dram Type= 6, Freq= 0, CH_1, rank 1
8824 23:35:14.419526 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8825 23:35:14.419955 ==
8826 23:35:14.422834 [Gating] SW mode calibration
8827 23:35:14.429934 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8828 23:35:14.436793 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8829 23:35:14.439802 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8830 23:35:14.442930 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8831 23:35:14.449469 1 4 8 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
8832 23:35:14.453407 1 4 12 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
8833 23:35:14.456626 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8834 23:35:14.462800 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8835 23:35:14.466279 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8836 23:35:14.469302 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8837 23:35:14.476309 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8838 23:35:14.479550 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8839 23:35:14.482397 1 5 8 | B1->B0 | 3434 3434 | 0 1 | (0 1) (1 1)
8840 23:35:14.489570 1 5 12 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (1 0)
8841 23:35:14.492853 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8842 23:35:14.496104 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8843 23:35:14.502519 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8844 23:35:14.506022 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8845 23:35:14.509323 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8846 23:35:14.516093 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8847 23:35:14.519425 1 6 8 | B1->B0 | 3a3a 2424 | 0 0 | (0 0) (0 0)
8848 23:35:14.522867 1 6 12 | B1->B0 | 4646 4343 | 0 0 | (0 0) (0 0)
8849 23:35:14.529751 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8850 23:35:14.533050 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8851 23:35:14.535850 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8852 23:35:14.542398 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8853 23:35:14.546190 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8854 23:35:14.549039 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8855 23:35:14.555788 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8856 23:35:14.558695 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8857 23:35:14.561992 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8858 23:35:14.568997 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8859 23:35:14.572375 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8860 23:35:14.575247 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8861 23:35:14.582401 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8862 23:35:14.585814 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8863 23:35:14.589066 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8864 23:35:14.592096 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8865 23:35:14.598920 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8866 23:35:14.602578 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8867 23:35:14.605986 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8868 23:35:14.612217 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8869 23:35:14.615561 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8870 23:35:14.619015 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8871 23:35:14.625666 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8872 23:35:14.629221 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8873 23:35:14.632188 Total UI for P1: 0, mck2ui 16
8874 23:35:14.635560 best dqsien dly found for B1: ( 1, 9, 6)
8875 23:35:14.638398 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8876 23:35:14.641869 Total UI for P1: 0, mck2ui 16
8877 23:35:14.645912 best dqsien dly found for B0: ( 1, 9, 10)
8878 23:35:14.648880 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8879 23:35:14.652324 best DQS1 dly(MCK, UI, PI) = (1, 9, 6)
8880 23:35:14.652791
8881 23:35:14.658617 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8882 23:35:14.661956 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 6)
8883 23:35:14.665264 [Gating] SW calibration Done
8884 23:35:14.665723 ==
8885 23:35:14.669029 Dram Type= 6, Freq= 0, CH_1, rank 1
8886 23:35:14.672093 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8887 23:35:14.672683 ==
8888 23:35:14.673034 RX Vref Scan: 0
8889 23:35:14.673354
8890 23:35:14.675063 RX Vref 0 -> 0, step: 1
8891 23:35:14.675489
8892 23:35:14.678997 RX Delay 0 -> 252, step: 8
8893 23:35:14.682323 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8894 23:35:14.685615 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8895 23:35:14.688610 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8896 23:35:14.695013 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8897 23:35:14.698436 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8898 23:35:14.701896 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8899 23:35:14.705520 iDelay=208, Bit 6, Center 143 (88 ~ 199) 112
8900 23:35:14.708811 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8901 23:35:14.715692 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8902 23:35:14.718327 iDelay=208, Bit 9, Center 123 (64 ~ 183) 120
8903 23:35:14.722298 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8904 23:35:14.725119 iDelay=208, Bit 11, Center 127 (72 ~ 183) 112
8905 23:35:14.728948 iDelay=208, Bit 12, Center 143 (88 ~ 199) 112
8906 23:35:14.735185 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8907 23:35:14.738692 iDelay=208, Bit 14, Center 139 (88 ~ 191) 104
8908 23:35:14.741805 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8909 23:35:14.742385 ==
8910 23:35:14.745701 Dram Type= 6, Freq= 0, CH_1, rank 1
8911 23:35:14.748567 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8912 23:35:14.751979 ==
8913 23:35:14.752455 DQS Delay:
8914 23:35:14.752832 DQS0 = 0, DQS1 = 0
8915 23:35:14.755167 DQM Delay:
8916 23:35:14.755814 DQM0 = 136, DQM1 = 134
8917 23:35:14.758616 DQ Delay:
8918 23:35:14.762009 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =131
8919 23:35:14.764895 DQ4 =131, DQ5 =151, DQ6 =143, DQ7 =135
8920 23:35:14.768484 DQ8 =119, DQ9 =123, DQ10 =135, DQ11 =127
8921 23:35:14.771773 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8922 23:35:14.772348
8923 23:35:14.772725
8924 23:35:14.773072 ==
8925 23:35:14.775098 Dram Type= 6, Freq= 0, CH_1, rank 1
8926 23:35:14.778333 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8927 23:35:14.778912 ==
8928 23:35:14.779291
8929 23:35:14.779685
8930 23:35:14.782099 TX Vref Scan disable
8931 23:35:14.785267 == TX Byte 0 ==
8932 23:35:14.788493 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8933 23:35:14.791713 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8934 23:35:14.795151 == TX Byte 1 ==
8935 23:35:14.798893 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8936 23:35:14.801845 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8937 23:35:14.802428 ==
8938 23:35:14.804605 Dram Type= 6, Freq= 0, CH_1, rank 1
8939 23:35:14.811431 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8940 23:35:14.811996 ==
8941 23:35:14.824280
8942 23:35:14.827191 TX Vref early break, caculate TX vref
8943 23:35:14.831410 TX Vref=16, minBit 0, minWin=23, winSum=387
8944 23:35:14.834008 TX Vref=18, minBit 0, minWin=23, winSum=394
8945 23:35:14.837371 TX Vref=20, minBit 0, minWin=23, winSum=398
8946 23:35:14.840660 TX Vref=22, minBit 0, minWin=24, winSum=409
8947 23:35:14.844112 TX Vref=24, minBit 0, minWin=25, winSum=419
8948 23:35:14.850601 TX Vref=26, minBit 0, minWin=25, winSum=425
8949 23:35:14.853748 TX Vref=28, minBit 1, minWin=25, winSum=427
8950 23:35:14.857402 TX Vref=30, minBit 6, minWin=25, winSum=421
8951 23:35:14.860793 TX Vref=32, minBit 0, minWin=25, winSum=415
8952 23:35:14.864117 TX Vref=34, minBit 1, minWin=24, winSum=405
8953 23:35:14.866879 TX Vref=36, minBit 0, minWin=24, winSum=397
8954 23:35:14.873619 [TxChooseVref] Worse bit 1, Min win 25, Win sum 427, Final Vref 28
8955 23:35:14.874111
8956 23:35:14.877416 Final TX Range 0 Vref 28
8957 23:35:14.878082
8958 23:35:14.878589 ==
8959 23:35:14.880272 Dram Type= 6, Freq= 0, CH_1, rank 1
8960 23:35:14.884452 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8961 23:35:14.885033 ==
8962 23:35:14.885415
8963 23:35:14.885816
8964 23:35:14.887206 TX Vref Scan disable
8965 23:35:14.893919 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8966 23:35:14.894458 == TX Byte 0 ==
8967 23:35:14.897626 u2DelayCellOfst[0]=20 cells (6 PI)
8968 23:35:14.901017 u2DelayCellOfst[1]=10 cells (3 PI)
8969 23:35:14.903779 u2DelayCellOfst[2]=0 cells (0 PI)
8970 23:35:14.906971 u2DelayCellOfst[3]=6 cells (2 PI)
8971 23:35:14.910565 u2DelayCellOfst[4]=10 cells (3 PI)
8972 23:35:14.914053 u2DelayCellOfst[5]=16 cells (5 PI)
8973 23:35:14.917116 u2DelayCellOfst[6]=20 cells (6 PI)
8974 23:35:14.920444 u2DelayCellOfst[7]=6 cells (2 PI)
8975 23:35:14.923463 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8976 23:35:14.927503 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8977 23:35:14.930388 == TX Byte 1 ==
8978 23:35:14.933345 u2DelayCellOfst[8]=0 cells (0 PI)
8979 23:35:14.933806 u2DelayCellOfst[9]=3 cells (1 PI)
8980 23:35:14.937148 u2DelayCellOfst[10]=10 cells (3 PI)
8981 23:35:14.940479 u2DelayCellOfst[11]=6 cells (2 PI)
8982 23:35:14.943569 u2DelayCellOfst[12]=16 cells (5 PI)
8983 23:35:14.947351 u2DelayCellOfst[13]=16 cells (5 PI)
8984 23:35:14.950343 u2DelayCellOfst[14]=16 cells (5 PI)
8985 23:35:14.953669 u2DelayCellOfst[15]=16 cells (5 PI)
8986 23:35:14.956757 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8987 23:35:14.963624 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8988 23:35:14.964187 DramC Write-DBI on
8989 23:35:14.964665 ==
8990 23:35:14.966784 Dram Type= 6, Freq= 0, CH_1, rank 1
8991 23:35:14.973829 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8992 23:35:14.974408 ==
8993 23:35:14.974787
8994 23:35:14.975244
8995 23:35:14.975596 TX Vref Scan disable
8996 23:35:14.977378 == TX Byte 0 ==
8997 23:35:14.980678 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8998 23:35:14.983835 == TX Byte 1 ==
8999 23:35:14.987264 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
9000 23:35:14.991025 DramC Write-DBI off
9001 23:35:14.991598
9002 23:35:14.991976 [DATLAT]
9003 23:35:14.992322 Freq=1600, CH1 RK1
9004 23:35:14.992665
9005 23:35:14.993923 DATLAT Default: 0xf
9006 23:35:14.994394 0, 0xFFFF, sum = 0
9007 23:35:14.997217 1, 0xFFFF, sum = 0
9008 23:35:15.000919 2, 0xFFFF, sum = 0
9009 23:35:15.001511 3, 0xFFFF, sum = 0
9010 23:35:15.004589 4, 0xFFFF, sum = 0
9011 23:35:15.005134 5, 0xFFFF, sum = 0
9012 23:35:15.007296 6, 0xFFFF, sum = 0
9013 23:35:15.007729 7, 0xFFFF, sum = 0
9014 23:35:15.010815 8, 0xFFFF, sum = 0
9015 23:35:15.011426 9, 0xFFFF, sum = 0
9016 23:35:15.014058 10, 0xFFFF, sum = 0
9017 23:35:15.014492 11, 0xFFFF, sum = 0
9018 23:35:15.017633 12, 0xFFFF, sum = 0
9019 23:35:15.018069 13, 0xFFFF, sum = 0
9020 23:35:15.020370 14, 0x0, sum = 1
9021 23:35:15.020800 15, 0x0, sum = 2
9022 23:35:15.024176 16, 0x0, sum = 3
9023 23:35:15.024719 17, 0x0, sum = 4
9024 23:35:15.027221 best_step = 15
9025 23:35:15.027805
9026 23:35:15.028167 ==
9027 23:35:15.030823 Dram Type= 6, Freq= 0, CH_1, rank 1
9028 23:35:15.034046 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9029 23:35:15.034477 ==
9030 23:35:15.037091 RX Vref Scan: 0
9031 23:35:15.037515
9032 23:35:15.037894 RX Vref 0 -> 0, step: 1
9033 23:35:15.038216
9034 23:35:15.041003 RX Delay 19 -> 252, step: 4
9035 23:35:15.044061 iDelay=195, Bit 0, Center 138 (91 ~ 186) 96
9036 23:35:15.050245 iDelay=195, Bit 1, Center 130 (83 ~ 178) 96
9037 23:35:15.054043 iDelay=195, Bit 2, Center 122 (71 ~ 174) 104
9038 23:35:15.057340 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
9039 23:35:15.060733 iDelay=195, Bit 4, Center 130 (83 ~ 178) 96
9040 23:35:15.064162 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
9041 23:35:15.070197 iDelay=195, Bit 6, Center 144 (95 ~ 194) 100
9042 23:35:15.073826 iDelay=195, Bit 7, Center 134 (83 ~ 186) 104
9043 23:35:15.076808 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
9044 23:35:15.080162 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
9045 23:35:15.083618 iDelay=195, Bit 10, Center 132 (83 ~ 182) 100
9046 23:35:15.090330 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
9047 23:35:15.093461 iDelay=195, Bit 12, Center 140 (87 ~ 194) 108
9048 23:35:15.096891 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
9049 23:35:15.100051 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
9050 23:35:15.103334 iDelay=195, Bit 15, Center 140 (91 ~ 190) 100
9051 23:35:15.106490 ==
9052 23:35:15.110092 Dram Type= 6, Freq= 0, CH_1, rank 1
9053 23:35:15.113359 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9054 23:35:15.113855 ==
9055 23:35:15.114208 DQS Delay:
9056 23:35:15.116358 DQS0 = 0, DQS1 = 0
9057 23:35:15.116783 DQM Delay:
9058 23:35:15.119824 DQM0 = 134, DQM1 = 130
9059 23:35:15.120295 DQ Delay:
9060 23:35:15.123405 DQ0 =138, DQ1 =130, DQ2 =122, DQ3 =130
9061 23:35:15.126604 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =134
9062 23:35:15.130172 DQ8 =116, DQ9 =118, DQ10 =132, DQ11 =124
9063 23:35:15.133391 DQ12 =140, DQ13 =138, DQ14 =136, DQ15 =140
9064 23:35:15.133904
9065 23:35:15.134284
9066 23:35:15.134630
9067 23:35:15.136366 [DramC_TX_OE_Calibration] TA2
9068 23:35:15.139858 Original DQ_B0 (3 6) =30, OEN = 27
9069 23:35:15.143945 Original DQ_B1 (3 6) =30, OEN = 27
9070 23:35:15.146244 24, 0x0, End_B0=24 End_B1=24
9071 23:35:15.149956 25, 0x0, End_B0=25 End_B1=25
9072 23:35:15.150582 26, 0x0, End_B0=26 End_B1=26
9073 23:35:15.153288 27, 0x0, End_B0=27 End_B1=27
9074 23:35:15.156612 28, 0x0, End_B0=28 End_B1=28
9075 23:35:15.159807 29, 0x0, End_B0=29 End_B1=29
9076 23:35:15.160283 30, 0x0, End_B0=30 End_B1=30
9077 23:35:15.163295 31, 0x4141, End_B0=30 End_B1=30
9078 23:35:15.166242 Byte0 end_step=30 best_step=27
9079 23:35:15.170077 Byte1 end_step=30 best_step=27
9080 23:35:15.173256 Byte0 TX OE(2T, 0.5T) = (3, 3)
9081 23:35:15.176354 Byte1 TX OE(2T, 0.5T) = (3, 3)
9082 23:35:15.176821
9083 23:35:15.177191
9084 23:35:15.183292 [DQSOSCAuto] RK1, (LSB)MR18= 0x2107, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 393 ps
9085 23:35:15.186330 CH1 RK1: MR19=303, MR18=2107
9086 23:35:15.193268 CH1_RK1: MR19=0x303, MR18=0x2107, DQSOSC=393, MR23=63, INC=23, DEC=15
9087 23:35:15.196080 [RxdqsGatingPostProcess] freq 1600
9088 23:35:15.199730 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9089 23:35:15.203314 best DQS0 dly(2T, 0.5T) = (1, 1)
9090 23:35:15.206530 best DQS1 dly(2T, 0.5T) = (1, 1)
9091 23:35:15.209857 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9092 23:35:15.212938 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9093 23:35:15.216298 best DQS0 dly(2T, 0.5T) = (1, 1)
9094 23:35:15.219537 best DQS1 dly(2T, 0.5T) = (1, 1)
9095 23:35:15.222777 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9096 23:35:15.225983 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9097 23:35:15.229628 Pre-setting of DQS Precalculation
9098 23:35:15.233054 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9099 23:35:15.240198 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9100 23:35:15.249736 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9101 23:35:15.250312
9102 23:35:15.250688
9103 23:35:15.253346 [Calibration Summary] 3200 Mbps
9104 23:35:15.253978 CH 0, Rank 0
9105 23:35:15.256121 SW Impedance : PASS
9106 23:35:15.256585 DUTY Scan : NO K
9107 23:35:15.259752 ZQ Calibration : PASS
9108 23:35:15.262964 Jitter Meter : NO K
9109 23:35:15.263489 CBT Training : PASS
9110 23:35:15.266081 Write leveling : PASS
9111 23:35:15.266678 RX DQS gating : PASS
9112 23:35:15.269372 RX DQ/DQS(RDDQC) : PASS
9113 23:35:15.273142 TX DQ/DQS : PASS
9114 23:35:15.273808 RX DATLAT : PASS
9115 23:35:15.275944 RX DQ/DQS(Engine): PASS
9116 23:35:15.279932 TX OE : PASS
9117 23:35:15.280544 All Pass.
9118 23:35:15.281036
9119 23:35:15.281498 CH 0, Rank 1
9120 23:35:15.282506 SW Impedance : PASS
9121 23:35:15.286214 DUTY Scan : NO K
9122 23:35:15.286790 ZQ Calibration : PASS
9123 23:35:15.289341 Jitter Meter : NO K
9124 23:35:15.292655 CBT Training : PASS
9125 23:35:15.293291 Write leveling : PASS
9126 23:35:15.296350 RX DQS gating : PASS
9127 23:35:15.299533 RX DQ/DQS(RDDQC) : PASS
9128 23:35:15.300111 TX DQ/DQS : PASS
9129 23:35:15.302740 RX DATLAT : PASS
9130 23:35:15.306032 RX DQ/DQS(Engine): PASS
9131 23:35:15.306608 TX OE : PASS
9132 23:35:15.308889 All Pass.
9133 23:35:15.309364
9134 23:35:15.309797 CH 1, Rank 0
9135 23:35:15.312671 SW Impedance : PASS
9136 23:35:15.313133 DUTY Scan : NO K
9137 23:35:15.316299 ZQ Calibration : PASS
9138 23:35:15.319187 Jitter Meter : NO K
9139 23:35:15.319655 CBT Training : PASS
9140 23:35:15.322651 Write leveling : PASS
9141 23:35:15.323137 RX DQS gating : PASS
9142 23:35:15.326050 RX DQ/DQS(RDDQC) : PASS
9143 23:35:15.329010 TX DQ/DQS : PASS
9144 23:35:15.329491 RX DATLAT : PASS
9145 23:35:15.332687 RX DQ/DQS(Engine): PASS
9146 23:35:15.336013 TX OE : PASS
9147 23:35:15.336621 All Pass.
9148 23:35:15.337039
9149 23:35:15.337462 CH 1, Rank 1
9150 23:35:15.338956 SW Impedance : PASS
9151 23:35:15.342249 DUTY Scan : NO K
9152 23:35:15.342890 ZQ Calibration : PASS
9153 23:35:15.345752 Jitter Meter : NO K
9154 23:35:15.349441 CBT Training : PASS
9155 23:35:15.350071 Write leveling : PASS
9156 23:35:15.352255 RX DQS gating : PASS
9157 23:35:15.355842 RX DQ/DQS(RDDQC) : PASS
9158 23:35:15.356307 TX DQ/DQS : PASS
9159 23:35:15.358709 RX DATLAT : PASS
9160 23:35:15.362206 RX DQ/DQS(Engine): PASS
9161 23:35:15.362767 TX OE : PASS
9162 23:35:15.363143 All Pass.
9163 23:35:15.365970
9164 23:35:15.366552 DramC Write-DBI on
9165 23:35:15.369121 PER_BANK_REFRESH: Hybrid Mode
9166 23:35:15.369732 TX_TRACKING: ON
9167 23:35:15.379042 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9168 23:35:15.385387 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9169 23:35:15.396045 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9170 23:35:15.398724 [FAST_K] Save calibration result to emmc
9171 23:35:15.402389 sync common calibartion params.
9172 23:35:15.402970 sync cbt_mode0:1, 1:1
9173 23:35:15.405402 dram_init: ddr_geometry: 2
9174 23:35:15.409255 dram_init: ddr_geometry: 2
9175 23:35:15.409919 dram_init: ddr_geometry: 2
9176 23:35:15.411976 0:dram_rank_size:100000000
9177 23:35:15.415346 1:dram_rank_size:100000000
9178 23:35:15.418867 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9179 23:35:15.422368 DFS_SHUFFLE_HW_MODE: ON
9180 23:35:15.425774 dramc_set_vcore_voltage set vcore to 725000
9181 23:35:15.429014 Read voltage for 1600, 0
9182 23:35:15.429687 Vio18 = 0
9183 23:35:15.432418 Vcore = 725000
9184 23:35:15.433021 Vdram = 0
9185 23:35:15.433400 Vddq = 0
9186 23:35:15.433822 Vmddr = 0
9187 23:35:15.435484 switch to 3200 Mbps bootup
9188 23:35:15.438833 [DramcRunTimeConfig]
9189 23:35:15.439399 PHYPLL
9190 23:35:15.442234 DPM_CONTROL_AFTERK: ON
9191 23:35:15.442798 PER_BANK_REFRESH: ON
9192 23:35:15.445986 REFRESH_OVERHEAD_REDUCTION: ON
9193 23:35:15.448626 CMD_PICG_NEW_MODE: OFF
9194 23:35:15.449219 XRTWTW_NEW_MODE: ON
9195 23:35:15.452458 XRTRTR_NEW_MODE: ON
9196 23:35:15.452915 TX_TRACKING: ON
9197 23:35:15.455437 RDSEL_TRACKING: OFF
9198 23:35:15.458367 DQS Precalculation for DVFS: ON
9199 23:35:15.458828 RX_TRACKING: OFF
9200 23:35:15.461634 HW_GATING DBG: ON
9201 23:35:15.462099 ZQCS_ENABLE_LP4: ON
9202 23:35:15.465369 RX_PICG_NEW_MODE: ON
9203 23:35:15.465982 TX_PICG_NEW_MODE: ON
9204 23:35:15.468382 ENABLE_RX_DCM_DPHY: ON
9205 23:35:15.471890 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9206 23:35:15.474864 DUMMY_READ_FOR_TRACKING: OFF
9207 23:35:15.475326 !!! SPM_CONTROL_AFTERK: OFF
9208 23:35:15.478236 !!! SPM could not control APHY
9209 23:35:15.482047 IMPEDANCE_TRACKING: ON
9210 23:35:15.482610 TEMP_SENSOR: ON
9211 23:35:15.484968 HW_SAVE_FOR_SR: OFF
9212 23:35:15.488424 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9213 23:35:15.492211 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9214 23:35:15.492775 Read ODT Tracking: ON
9215 23:35:15.495275 Refresh Rate DeBounce: ON
9216 23:35:15.498444 DFS_NO_QUEUE_FLUSH: ON
9217 23:35:15.501819 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9218 23:35:15.502380 ENABLE_DFS_RUNTIME_MRW: OFF
9219 23:35:15.504820 DDR_RESERVE_NEW_MODE: ON
9220 23:35:15.508391 MR_CBT_SWITCH_FREQ: ON
9221 23:35:15.508881 =========================
9222 23:35:15.528912 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9223 23:35:15.531626 dram_init: ddr_geometry: 2
9224 23:35:15.550196 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9225 23:35:15.553385 dram_init: dram init end (result: 0)
9226 23:35:15.560020 DRAM-K: Full calibration passed in 24513 msecs
9227 23:35:15.563411 MRC: failed to locate region type 0.
9228 23:35:15.564000 DRAM rank0 size:0x100000000,
9229 23:35:15.566270 DRAM rank1 size=0x100000000
9230 23:35:15.576559 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9231 23:35:15.582818 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9232 23:35:15.589370 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9233 23:35:15.596462 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9234 23:35:15.600038 DRAM rank0 size:0x100000000,
9235 23:35:15.603706 DRAM rank1 size=0x100000000
9236 23:35:15.604238 CBMEM:
9237 23:35:15.606001 IMD: root @ 0xfffff000 254 entries.
9238 23:35:15.609609 IMD: root @ 0xffffec00 62 entries.
9239 23:35:15.612692 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9240 23:35:15.616092 WARNING: RO_VPD is uninitialized or empty.
9241 23:35:15.622650 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9242 23:35:15.630137 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9243 23:35:15.642670 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9244 23:35:15.654223 BS: romstage times (exec / console): total (unknown) / 24037 ms
9245 23:35:15.654787
9246 23:35:15.655169
9247 23:35:15.664237 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9248 23:35:15.667787 ARM64: Exception handlers installed.
9249 23:35:15.670748 ARM64: Testing exception
9250 23:35:15.673894 ARM64: Done test exception
9251 23:35:15.674366 Enumerating buses...
9252 23:35:15.677165 Show all devs... Before device enumeration.
9253 23:35:15.681036 Root Device: enabled 1
9254 23:35:15.684167 CPU_CLUSTER: 0: enabled 1
9255 23:35:15.684904 CPU: 00: enabled 1
9256 23:35:15.687241 Compare with tree...
9257 23:35:15.687712 Root Device: enabled 1
9258 23:35:15.690900 CPU_CLUSTER: 0: enabled 1
9259 23:35:15.694146 CPU: 00: enabled 1
9260 23:35:15.694731 Root Device scanning...
9261 23:35:15.697119 scan_static_bus for Root Device
9262 23:35:15.700942 CPU_CLUSTER: 0 enabled
9263 23:35:15.704148 scan_static_bus for Root Device done
9264 23:35:15.707352 scan_bus: bus Root Device finished in 8 msecs
9265 23:35:15.707932 done
9266 23:35:15.713932 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9267 23:35:15.717268 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9268 23:35:15.724230 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9269 23:35:15.726902 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9270 23:35:15.730929 Allocating resources...
9271 23:35:15.733501 Reading resources...
9272 23:35:15.737256 Root Device read_resources bus 0 link: 0
9273 23:35:15.737980 DRAM rank0 size:0x100000000,
9274 23:35:15.740863 DRAM rank1 size=0x100000000
9275 23:35:15.743775 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9276 23:35:15.747108 CPU: 00 missing read_resources
9277 23:35:15.750558 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9278 23:35:15.756999 Root Device read_resources bus 0 link: 0 done
9279 23:35:15.757715 Done reading resources.
9280 23:35:15.764201 Show resources in subtree (Root Device)...After reading.
9281 23:35:15.766753 Root Device child on link 0 CPU_CLUSTER: 0
9282 23:35:15.770008 CPU_CLUSTER: 0 child on link 0 CPU: 00
9283 23:35:15.780487 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9284 23:35:15.781071 CPU: 00
9285 23:35:15.783593 Root Device assign_resources, bus 0 link: 0
9286 23:35:15.786744 CPU_CLUSTER: 0 missing set_resources
9287 23:35:15.793484 Root Device assign_resources, bus 0 link: 0 done
9288 23:35:15.794097 Done setting resources.
9289 23:35:15.800415 Show resources in subtree (Root Device)...After assigning values.
9290 23:35:15.803590 Root Device child on link 0 CPU_CLUSTER: 0
9291 23:35:15.806911 CPU_CLUSTER: 0 child on link 0 CPU: 00
9292 23:35:15.816713 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9293 23:35:15.817277 CPU: 00
9294 23:35:15.820258 Done allocating resources.
9295 23:35:15.823076 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9296 23:35:15.826869 Enabling resources...
9297 23:35:15.827449 done.
9298 23:35:15.833759 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9299 23:35:15.834337 Initializing devices...
9300 23:35:15.836979 Root Device init
9301 23:35:15.837573 init hardware done!
9302 23:35:15.840174 0x00000018: ctrlr->caps
9303 23:35:15.843894 52.000 MHz: ctrlr->f_max
9304 23:35:15.844485 0.400 MHz: ctrlr->f_min
9305 23:35:15.846472 0x40ff8080: ctrlr->voltages
9306 23:35:15.846980 sclk: 390625
9307 23:35:15.850126 Bus Width = 1
9308 23:35:15.850739 sclk: 390625
9309 23:35:15.852896 Bus Width = 1
9310 23:35:15.853362 Early init status = 3
9311 23:35:15.859731 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9312 23:35:15.863800 in-header: 03 fc 00 00 01 00 00 00
9313 23:35:15.864376 in-data: 00
9314 23:35:15.869975 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9315 23:35:15.873120 in-header: 03 fd 00 00 00 00 00 00
9316 23:35:15.876530 in-data:
9317 23:35:15.879947 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9318 23:35:15.883297 in-header: 03 fc 00 00 01 00 00 00
9319 23:35:15.886751 in-data: 00
9320 23:35:15.890067 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9321 23:35:15.894007 in-header: 03 fd 00 00 00 00 00 00
9322 23:35:15.897280 in-data:
9323 23:35:15.900909 [SSUSB] Setting up USB HOST controller...
9324 23:35:15.903822 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9325 23:35:15.907565 [SSUSB] phy power-on done.
9326 23:35:15.910351 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9327 23:35:15.917440 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9328 23:35:15.920681 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9329 23:35:15.927248 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9330 23:35:15.934359 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9331 23:35:15.940713 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9332 23:35:15.947775 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9333 23:35:15.954295 read SPI 0x705bc 0x1f6a: 923 us, 8712 KB/s, 69.696 Mbps
9334 23:35:15.957467 SPM: binary array size = 0x9dc
9335 23:35:15.960651 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9336 23:35:15.967170 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9337 23:35:15.974138 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9338 23:35:15.977272 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9339 23:35:15.980723 configure_display: Starting display init
9340 23:35:16.018010 anx7625_power_on_init: Init interface.
9341 23:35:16.021022 anx7625_disable_pd_protocol: Disabled PD feature.
9342 23:35:16.023680 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9343 23:35:16.052255 anx7625_start_dp_work: Secure OCM version=00
9344 23:35:16.055200 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9345 23:35:16.070124 sp_tx_get_edid_block: EDID Block = 1
9346 23:35:16.172540 Extracted contents:
9347 23:35:16.175800 header: 00 ff ff ff ff ff ff 00
9348 23:35:16.179360 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9349 23:35:16.182536 version: 01 04
9350 23:35:16.185829 basic params: 95 1f 11 78 0a
9351 23:35:16.189212 chroma info: 76 90 94 55 54 90 27 21 50 54
9352 23:35:16.192436 established: 00 00 00
9353 23:35:16.199492 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9354 23:35:16.202385 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9355 23:35:16.209164 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9356 23:35:16.215466 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9357 23:35:16.222574 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9358 23:35:16.225664 extensions: 00
9359 23:35:16.226134 checksum: fb
9360 23:35:16.226511
9361 23:35:16.228622 Manufacturer: IVO Model 57d Serial Number 0
9362 23:35:16.232275 Made week 0 of 2020
9363 23:35:16.232729 EDID version: 1.4
9364 23:35:16.235386 Digital display
9365 23:35:16.238801 6 bits per primary color channel
9366 23:35:16.239265 DisplayPort interface
9367 23:35:16.241937 Maximum image size: 31 cm x 17 cm
9368 23:35:16.245318 Gamma: 220%
9369 23:35:16.245807 Check DPMS levels
9370 23:35:16.248886 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9371 23:35:16.251856 First detailed timing is preferred timing
9372 23:35:16.255772 Established timings supported:
9373 23:35:16.258544 Standard timings supported:
9374 23:35:16.262134 Detailed timings
9375 23:35:16.264994 Hex of detail: 383680a07038204018303c0035ae10000019
9376 23:35:16.268578 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9377 23:35:16.275041 0780 0798 07c8 0820 hborder 0
9378 23:35:16.278248 0438 043b 0447 0458 vborder 0
9379 23:35:16.281695 -hsync -vsync
9380 23:35:16.282117 Did detailed timing
9381 23:35:16.288628 Hex of detail: 000000000000000000000000000000000000
9382 23:35:16.289052 Manufacturer-specified data, tag 0
9383 23:35:16.295006 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9384 23:35:16.298023 ASCII string: InfoVision
9385 23:35:16.301480 Hex of detail: 000000fe00523134304e574635205248200a
9386 23:35:16.304996 ASCII string: R140NWF5 RH
9387 23:35:16.305524 Checksum
9388 23:35:16.308715 Checksum: 0xfb (valid)
9389 23:35:16.311505 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9390 23:35:16.315039 DSI data_rate: 832800000 bps
9391 23:35:16.322181 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9392 23:35:16.325342 anx7625_parse_edid: pixelclock(138800).
9393 23:35:16.328305 hactive(1920), hsync(48), hfp(24), hbp(88)
9394 23:35:16.331376 vactive(1080), vsync(12), vfp(3), vbp(17)
9395 23:35:16.334869 anx7625_dsi_config: config dsi.
9396 23:35:16.341097 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9397 23:35:16.354961 anx7625_dsi_config: success to config DSI
9398 23:35:16.357773 anx7625_dp_start: MIPI phy setup OK.
9399 23:35:16.361038 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9400 23:35:16.364434 mtk_ddp_mode_set invalid vrefresh 60
9401 23:35:16.367685 main_disp_path_setup
9402 23:35:16.368251 ovl_layer_smi_id_en
9403 23:35:16.370723 ovl_layer_smi_id_en
9404 23:35:16.371188 ccorr_config
9405 23:35:16.371562 aal_config
9406 23:35:16.374249 gamma_config
9407 23:35:16.374769 postmask_config
9408 23:35:16.377674 dither_config
9409 23:35:16.381057 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9410 23:35:16.387743 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9411 23:35:16.391404 Root Device init finished in 551 msecs
9412 23:35:16.393942 CPU_CLUSTER: 0 init
9413 23:35:16.400965 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9414 23:35:16.407612 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9415 23:35:16.408189 APU_MBOX 0x190000b0 = 0x10001
9416 23:35:16.410990 APU_MBOX 0x190001b0 = 0x10001
9417 23:35:16.413661 APU_MBOX 0x190005b0 = 0x10001
9418 23:35:16.417511 APU_MBOX 0x190006b0 = 0x10001
9419 23:35:16.423835 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9420 23:35:16.433846 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9421 23:35:16.445717 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9422 23:35:16.452111 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9423 23:35:16.463966 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9424 23:35:16.473757 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9425 23:35:16.477261 CPU_CLUSTER: 0 init finished in 81 msecs
9426 23:35:16.480200 Devices initialized
9427 23:35:16.483352 Show all devs... After init.
9428 23:35:16.483814 Root Device: enabled 1
9429 23:35:16.486634 CPU_CLUSTER: 0: enabled 1
9430 23:35:16.489716 CPU: 00: enabled 1
9431 23:35:16.493816 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9432 23:35:16.496753 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9433 23:35:16.500094 ELOG: NV offset 0x57f000 size 0x1000
9434 23:35:16.506579 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9435 23:35:16.513477 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9436 23:35:16.516149 ELOG: Event(17) added with size 13 at 2023-12-03 23:33:02 UTC
9437 23:35:16.520340 out: cmd=0x121: 03 db 21 01 00 00 00 00
9438 23:35:16.523534 in-header: 03 a4 00 00 2c 00 00 00
9439 23:35:16.537130 in-data: bb 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9440 23:35:16.543758 ELOG: Event(A1) added with size 10 at 2023-12-03 23:33:02 UTC
9441 23:35:16.549975 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9442 23:35:16.556874 ELOG: Event(A0) added with size 9 at 2023-12-03 23:33:02 UTC
9443 23:35:16.559613 elog_add_boot_reason: Logged dev mode boot
9444 23:35:16.563249 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9445 23:35:16.566313 Finalize devices...
9446 23:35:16.566777 Devices finalized
9447 23:35:16.573370 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9448 23:35:16.576509 Writing coreboot table at 0xffe64000
9449 23:35:16.580318 0. 000000000010a000-0000000000113fff: RAMSTAGE
9450 23:35:16.583091 1. 0000000040000000-00000000400fffff: RAM
9451 23:35:16.590079 2. 0000000040100000-000000004032afff: RAMSTAGE
9452 23:35:16.593440 3. 000000004032b000-00000000545fffff: RAM
9453 23:35:16.596394 4. 0000000054600000-000000005465ffff: BL31
9454 23:35:16.599995 5. 0000000054660000-00000000ffe63fff: RAM
9455 23:35:16.606486 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9456 23:35:16.609972 7. 0000000100000000-000000023fffffff: RAM
9457 23:35:16.610401 Passing 5 GPIOs to payload:
9458 23:35:16.616357 NAME | PORT | POLARITY | VALUE
9459 23:35:16.620196 EC in RW | 0x000000aa | low | undefined
9460 23:35:16.626123 EC interrupt | 0x00000005 | low | undefined
9461 23:35:16.629835 TPM interrupt | 0x000000ab | high | undefined
9462 23:35:16.633074 SD card detect | 0x00000011 | high | undefined
9463 23:35:16.639629 speaker enable | 0x00000093 | high | undefined
9464 23:35:16.642966 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9465 23:35:16.646208 in-header: 03 f9 00 00 02 00 00 00
9466 23:35:16.646711 in-data: 02 00
9467 23:35:16.649598 ADC[4]: Raw value=905096 ID=7
9468 23:35:16.652695 ADC[3]: Raw value=213441 ID=1
9469 23:35:16.653246 RAM Code: 0x71
9470 23:35:16.656599 ADC[6]: Raw value=75332 ID=0
9471 23:35:16.659202 ADC[5]: Raw value=213072 ID=1
9472 23:35:16.659696 SKU Code: 0x1
9473 23:35:16.665785 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 425c
9474 23:35:16.669284 coreboot table: 964 bytes.
9475 23:35:16.673065 IMD ROOT 0. 0xfffff000 0x00001000
9476 23:35:16.675825 IMD SMALL 1. 0xffffe000 0x00001000
9477 23:35:16.679439 RO MCACHE 2. 0xffffc000 0x00001104
9478 23:35:16.682671 CONSOLE 3. 0xfff7c000 0x00080000
9479 23:35:16.685872 FMAP 4. 0xfff7b000 0x00000452
9480 23:35:16.689544 TIME STAMP 5. 0xfff7a000 0x00000910
9481 23:35:16.692723 VBOOT WORK 6. 0xfff66000 0x00014000
9482 23:35:16.696517 RAMOOPS 7. 0xffe66000 0x00100000
9483 23:35:16.699423 COREBOOT 8. 0xffe64000 0x00002000
9484 23:35:16.699994 IMD small region:
9485 23:35:16.702256 IMD ROOT 0. 0xffffec00 0x00000400
9486 23:35:16.705967 VPD 1. 0xffffeb80 0x0000006c
9487 23:35:16.708937 MMC STATUS 2. 0xffffeb60 0x00000004
9488 23:35:16.715456 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9489 23:35:16.718701 Probing TPM: done!
9490 23:35:16.722797 Connected to device vid:did:rid of 1ae0:0028:00
9491 23:35:16.732232 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9492 23:35:16.735471 Initialized TPM device CR50 revision 0
9493 23:35:16.740268 Checking cr50 for pending updates
9494 23:35:16.743538 Reading cr50 TPM mode
9495 23:35:16.751624 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9496 23:35:16.758269 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9497 23:35:16.798534 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9498 23:35:16.801944 Checking segment from ROM address 0x40100000
9499 23:35:16.804730 Checking segment from ROM address 0x4010001c
9500 23:35:16.811730 Loading segment from ROM address 0x40100000
9501 23:35:16.812297 code (compression=0)
9502 23:35:16.821957 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9503 23:35:16.828480 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9504 23:35:16.829061 it's not compressed!
9505 23:35:16.834947 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9506 23:35:16.838483 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9507 23:35:16.858592 Loading segment from ROM address 0x4010001c
9508 23:35:16.859161 Entry Point 0x80000000
9509 23:35:16.862646 Loaded segments
9510 23:35:16.865224 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9511 23:35:16.871888 Jumping to boot code at 0x80000000(0xffe64000)
9512 23:35:16.878820 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9513 23:35:16.885312 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9514 23:35:16.892958 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9515 23:35:16.896501 Checking segment from ROM address 0x40100000
9516 23:35:16.899645 Checking segment from ROM address 0x4010001c
9517 23:35:16.906411 Loading segment from ROM address 0x40100000
9518 23:35:16.906718 code (compression=1)
9519 23:35:16.912983 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9520 23:35:16.923148 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9521 23:35:16.923477 using LZMA
9522 23:35:16.931624 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9523 23:35:16.938026 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9524 23:35:16.941361 Loading segment from ROM address 0x4010001c
9525 23:35:16.941714 Entry Point 0x54601000
9526 23:35:16.944521 Loaded segments
9527 23:35:16.948428 NOTICE: MT8192 bl31_setup
9528 23:35:16.954929 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9529 23:35:16.958697 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9530 23:35:16.962105 WARNING: region 0:
9531 23:35:16.965628 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9532 23:35:16.966230 WARNING: region 1:
9533 23:35:16.972412 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9534 23:35:16.975267 WARNING: region 2:
9535 23:35:16.978543 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9536 23:35:16.981711 WARNING: region 3:
9537 23:35:16.985205 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9538 23:35:16.989105 WARNING: region 4:
9539 23:35:16.995468 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9540 23:35:16.996047 WARNING: region 5:
9541 23:35:16.998869 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9542 23:35:17.001872 WARNING: region 6:
9543 23:35:17.005062 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9544 23:35:17.005533 WARNING: region 7:
9545 23:35:17.011624 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9546 23:35:17.018528 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9547 23:35:17.022035 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9548 23:35:17.025490 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9549 23:35:17.032429 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9550 23:35:17.035352 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9551 23:35:17.038742 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9552 23:35:17.045807 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9553 23:35:17.048621 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9554 23:35:17.052554 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9555 23:35:17.059100 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9556 23:35:17.062508 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9557 23:35:17.066132 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9558 23:35:17.072856 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9559 23:35:17.075528 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9560 23:35:17.082556 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9561 23:35:17.085341 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9562 23:35:17.089503 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9563 23:35:17.095900 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9564 23:35:17.099037 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9565 23:35:17.102670 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9566 23:35:17.109171 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9567 23:35:17.112796 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9568 23:35:17.118887 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9569 23:35:17.122312 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9570 23:35:17.126189 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9571 23:35:17.132431 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9572 23:35:17.136047 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9573 23:35:17.139447 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9574 23:35:17.146257 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9575 23:35:17.149363 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9576 23:35:17.156655 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9577 23:35:17.159403 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9578 23:35:17.162855 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9579 23:35:17.169261 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9580 23:35:17.172690 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9581 23:35:17.176209 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9582 23:35:17.179237 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9583 23:35:17.183229 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9584 23:35:17.189442 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9585 23:35:17.192808 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9586 23:35:17.195954 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9587 23:35:17.199598 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9588 23:35:17.206362 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9589 23:35:17.209509 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9590 23:35:17.212834 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9591 23:35:17.219406 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9592 23:35:17.222830 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9593 23:35:17.226103 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9594 23:35:17.229230 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9595 23:35:17.236152 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9596 23:35:17.239637 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9597 23:35:17.246099 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9598 23:35:17.249666 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9599 23:35:17.256570 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9600 23:35:17.259213 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9601 23:35:17.262682 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9602 23:35:17.270210 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9603 23:35:17.273007 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9604 23:35:17.278960 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9605 23:35:17.282491 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9606 23:35:17.289705 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9607 23:35:17.293001 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9608 23:35:17.295918 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9609 23:35:17.302865 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9610 23:35:17.306189 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9611 23:35:17.313192 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9612 23:35:17.316413 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9613 23:35:17.322940 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9614 23:35:17.326342 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9615 23:35:17.329711 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9616 23:35:17.336394 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9617 23:35:17.339594 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9618 23:35:17.346288 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9619 23:35:17.349438 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9620 23:35:17.356706 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9621 23:35:17.359575 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9622 23:35:17.363054 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9623 23:35:17.369106 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9624 23:35:17.372869 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9625 23:35:17.379329 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9626 23:35:17.382856 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9627 23:35:17.389710 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9628 23:35:17.393038 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9629 23:35:17.399391 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9630 23:35:17.402655 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9631 23:35:17.406274 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9632 23:35:17.412489 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9633 23:35:17.416570 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9634 23:35:17.422523 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9635 23:35:17.425982 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9636 23:35:17.429764 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9637 23:35:17.436569 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9638 23:35:17.439523 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9639 23:35:17.446237 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9640 23:35:17.449721 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9641 23:35:17.456233 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9642 23:35:17.459845 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9643 23:35:17.462736 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9644 23:35:17.466230 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9645 23:35:17.472863 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9646 23:35:17.476363 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9647 23:35:17.479706 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9648 23:35:17.485910 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9649 23:35:17.489488 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9650 23:35:17.496288 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9651 23:35:17.499871 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9652 23:35:17.503097 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9653 23:35:17.509659 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9654 23:35:17.512755 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9655 23:35:17.519399 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9656 23:35:17.523108 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9657 23:35:17.526457 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9658 23:35:17.533276 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9659 23:35:17.536491 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9660 23:35:17.542621 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9661 23:35:17.546398 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9662 23:35:17.549645 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9663 23:35:17.553261 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9664 23:35:17.559860 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9665 23:35:17.562686 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9666 23:35:17.566582 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9667 23:35:17.569561 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9668 23:35:17.576829 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9669 23:35:17.579918 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9670 23:35:17.583458 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9671 23:35:17.590031 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9672 23:35:17.592977 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9673 23:35:17.596394 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9674 23:35:17.603057 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9675 23:35:17.606100 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9676 23:35:17.613296 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9677 23:35:17.616941 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9678 23:35:17.619860 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9679 23:35:17.626361 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9680 23:35:17.629877 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9681 23:35:17.632853 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9682 23:35:17.639863 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9683 23:35:17.643064 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9684 23:35:17.649736 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9685 23:35:17.653476 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9686 23:35:17.656553 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9687 23:35:17.663157 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9688 23:35:17.666266 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9689 23:35:17.673475 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9690 23:35:17.677224 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9691 23:35:17.680236 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9692 23:35:17.686742 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9693 23:35:17.689953 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9694 23:35:17.692986 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9695 23:35:17.700045 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9696 23:35:17.703240 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9697 23:35:17.710181 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9698 23:35:17.713277 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9699 23:35:17.716861 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9700 23:35:17.723365 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9701 23:35:17.726672 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9702 23:35:17.730342 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9703 23:35:17.737096 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9704 23:35:17.739909 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9705 23:35:17.746885 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9706 23:35:17.750044 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9707 23:35:17.753805 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9708 23:35:17.760159 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9709 23:35:17.763228 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9710 23:35:17.770051 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9711 23:35:17.773390 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9712 23:35:17.776865 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9713 23:35:17.783507 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9714 23:35:17.786999 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9715 23:35:17.793262 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9716 23:35:17.796854 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9717 23:35:17.800125 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9718 23:35:17.806449 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9719 23:35:17.810316 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9720 23:35:17.813654 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9721 23:35:17.819698 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9722 23:35:17.823599 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9723 23:35:17.829705 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9724 23:35:17.833287 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9725 23:35:17.837099 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9726 23:35:17.842909 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9727 23:35:17.846912 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9728 23:35:17.853358 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9729 23:35:17.856677 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9730 23:35:17.860171 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9731 23:35:17.866774 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9732 23:35:17.870009 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9733 23:35:17.876526 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9734 23:35:17.879831 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9735 23:35:17.883820 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9736 23:35:17.890077 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9737 23:35:17.892968 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9738 23:35:17.899768 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9739 23:35:17.902731 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9740 23:35:17.906251 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9741 23:35:17.913143 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9742 23:35:17.916899 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9743 23:35:17.923354 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9744 23:35:17.926641 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9745 23:35:17.933209 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9746 23:35:17.935978 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9747 23:35:17.939612 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9748 23:35:17.946890 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9749 23:35:17.949485 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9750 23:35:17.955962 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9751 23:35:17.959272 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9752 23:35:17.962964 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9753 23:35:17.969724 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9754 23:35:17.972499 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9755 23:35:17.979302 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9756 23:35:17.982662 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9757 23:35:17.989410 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9758 23:35:17.992896 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9759 23:35:17.996308 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9760 23:35:18.002337 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9761 23:35:18.006050 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9762 23:35:18.012552 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9763 23:35:18.015821 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9764 23:35:18.019028 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9765 23:35:18.025768 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9766 23:35:18.029620 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9767 23:35:18.035573 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9768 23:35:18.039472 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9769 23:35:18.042277 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9770 23:35:18.049964 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9771 23:35:18.052663 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9772 23:35:18.059085 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9773 23:35:18.062321 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9774 23:35:18.069051 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9775 23:35:18.072445 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9776 23:35:18.075414 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9777 23:35:18.078801 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9778 23:35:18.082343 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9779 23:35:18.089150 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9780 23:35:18.092306 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9781 23:35:18.096104 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9782 23:35:18.102639 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9783 23:35:18.105692 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9784 23:35:18.108902 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9785 23:35:18.115998 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9786 23:35:18.118895 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9787 23:35:18.125366 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9788 23:35:18.128779 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9789 23:35:18.132339 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9790 23:35:18.138525 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9791 23:35:18.141703 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9792 23:35:18.148775 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9793 23:35:18.151639 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9794 23:35:18.155559 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9795 23:35:18.162330 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9796 23:35:18.165525 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9797 23:35:18.168696 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9798 23:35:18.175436 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9799 23:35:18.178718 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9800 23:35:18.181728 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9801 23:35:18.188513 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9802 23:35:18.192111 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9803 23:35:18.198070 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9804 23:35:18.201617 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9805 23:35:18.204957 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9806 23:35:18.211756 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9807 23:35:18.215234 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9808 23:35:18.218349 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9809 23:35:18.225035 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9810 23:35:18.228227 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9811 23:35:18.231863 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9812 23:35:18.237977 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9813 23:35:18.241654 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9814 23:35:18.248327 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9815 23:35:18.251634 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9816 23:35:18.255218 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9817 23:35:18.257731 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9818 23:35:18.261223 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9819 23:35:18.267869 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9820 23:35:18.270912 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9821 23:35:18.274665 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9822 23:35:18.277691 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9823 23:35:18.284509 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9824 23:35:18.287378 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9825 23:35:18.291097 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9826 23:35:18.297469 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9827 23:35:18.301239 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9828 23:35:18.304664 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9829 23:35:18.311264 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9830 23:35:18.314019 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9831 23:35:18.317252 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9832 23:35:18.324453 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9833 23:35:18.327414 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9834 23:35:18.334535 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9835 23:35:18.337740 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9836 23:35:18.341230 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9837 23:35:18.347954 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9838 23:35:18.350761 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9839 23:35:18.358168 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9840 23:35:18.360766 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9841 23:35:18.367640 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9842 23:35:18.370610 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9843 23:35:18.374503 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9844 23:35:18.380659 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9845 23:35:18.383849 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9846 23:35:18.390884 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9847 23:35:18.393673 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9848 23:35:18.397033 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9849 23:35:18.404636 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9850 23:35:18.407621 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9851 23:35:18.413946 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9852 23:35:18.417742 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9853 23:35:18.420501 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9854 23:35:18.427274 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9855 23:35:18.430373 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9856 23:35:18.437491 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9857 23:35:18.440679 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9858 23:35:18.447433 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9859 23:35:18.450965 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9860 23:35:18.453988 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9861 23:35:18.460824 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9862 23:35:18.463734 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9863 23:35:18.467530 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9864 23:35:18.474056 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9865 23:35:18.477160 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9866 23:35:18.484395 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9867 23:35:18.487461 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9868 23:35:18.490741 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9869 23:35:18.497383 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9870 23:35:18.500453 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9871 23:35:18.507384 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9872 23:35:18.510364 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9873 23:35:18.517226 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9874 23:35:18.520324 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9875 23:35:18.524001 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9876 23:35:18.530589 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9877 23:35:18.533643 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9878 23:35:18.540789 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9879 23:35:18.543530 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9880 23:35:18.546741 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9881 23:35:18.553969 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9882 23:35:18.556812 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9883 23:35:18.563344 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9884 23:35:18.566762 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9885 23:35:18.570547 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9886 23:35:18.576630 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9887 23:35:18.580229 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9888 23:35:18.586776 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9889 23:35:18.590267 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9890 23:35:18.596761 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9891 23:35:18.600265 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9892 23:35:18.603176 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9893 23:35:18.610427 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9894 23:35:18.613141 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9895 23:35:18.620145 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9896 23:35:18.622903 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9897 23:35:18.626605 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9898 23:35:18.633390 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9899 23:35:18.636473 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9900 23:35:18.643284 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9901 23:35:18.646619 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9902 23:35:18.649807 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9903 23:35:18.656782 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9904 23:35:18.659726 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9905 23:35:18.666224 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9906 23:35:18.669540 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9907 23:35:18.676255 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9908 23:35:18.679287 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9909 23:35:18.682964 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9910 23:35:18.689275 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9911 23:35:18.692670 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9912 23:35:18.699524 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9913 23:35:18.702994 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9914 23:35:18.709802 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9915 23:35:18.712855 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9916 23:35:18.719412 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9917 23:35:18.722482 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9918 23:35:18.726502 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9919 23:35:18.733047 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9920 23:35:18.736761 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9921 23:35:18.742598 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9922 23:35:18.745924 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9923 23:35:18.749932 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9924 23:35:18.756534 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9925 23:35:18.759734 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9926 23:35:18.766012 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9927 23:35:18.769747 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9928 23:35:18.775709 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9929 23:35:18.779306 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9930 23:35:18.785995 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9931 23:35:18.789063 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9932 23:35:18.792638 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9933 23:35:18.799764 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9934 23:35:18.802241 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9935 23:35:18.809124 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9936 23:35:18.812512 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9937 23:35:18.818911 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9938 23:35:18.822787 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9939 23:35:18.825922 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9940 23:35:18.832530 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9941 23:35:18.836003 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9942 23:35:18.842075 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9943 23:35:18.845455 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9944 23:35:18.852442 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9945 23:35:18.855848 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9946 23:35:18.862418 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9947 23:35:18.865332 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9948 23:35:18.868688 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9949 23:35:18.875428 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9950 23:35:18.878464 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9951 23:35:18.885665 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9952 23:35:18.888744 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9953 23:35:18.895259 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9954 23:35:18.898739 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9955 23:35:18.905067 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9956 23:35:18.908789 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9957 23:35:18.915499 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9958 23:35:18.918685 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9959 23:35:18.921949 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9960 23:35:18.928443 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9961 23:35:18.931917 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9962 23:35:18.938848 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9963 23:35:18.941720 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9964 23:35:18.948679 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9965 23:35:18.951998 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9966 23:35:18.958940 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9967 23:35:18.962124 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9968 23:35:18.968449 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9969 23:35:18.971766 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9970 23:35:18.978174 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9971 23:35:18.982700 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9972 23:35:18.988312 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9973 23:35:18.991868 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9974 23:35:18.998219 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9975 23:35:19.001443 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9976 23:35:19.008018 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9977 23:35:19.011652 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9978 23:35:19.018252 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9979 23:35:19.021079 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9980 23:35:19.027793 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9981 23:35:19.028260 INFO: [APUAPC] vio 0
9982 23:35:19.034745 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9983 23:35:19.038383 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9984 23:35:19.042164 INFO: [APUAPC] D0_APC_0: 0x400510
9985 23:35:19.044936 INFO: [APUAPC] D0_APC_1: 0x0
9986 23:35:19.048269 INFO: [APUAPC] D0_APC_2: 0x1540
9987 23:35:19.051740 INFO: [APUAPC] D0_APC_3: 0x0
9988 23:35:19.054747 INFO: [APUAPC] D1_APC_0: 0xffffffff
9989 23:35:19.058183 INFO: [APUAPC] D1_APC_1: 0xffffffff
9990 23:35:19.061432 INFO: [APUAPC] D1_APC_2: 0x3fffff
9991 23:35:19.065077 INFO: [APUAPC] D1_APC_3: 0x0
9992 23:35:19.068290 INFO: [APUAPC] D2_APC_0: 0xffffffff
9993 23:35:19.071461 INFO: [APUAPC] D2_APC_1: 0xffffffff
9994 23:35:19.074631 INFO: [APUAPC] D2_APC_2: 0x3fffff
9995 23:35:19.078188 INFO: [APUAPC] D2_APC_3: 0x0
9996 23:35:19.081465 INFO: [APUAPC] D3_APC_0: 0xffffffff
9997 23:35:19.084698 INFO: [APUAPC] D3_APC_1: 0xffffffff
9998 23:35:19.087867 INFO: [APUAPC] D3_APC_2: 0x3fffff
9999 23:35:19.091755 INFO: [APUAPC] D3_APC_3: 0x0
10000 23:35:19.094753 INFO: [APUAPC] D4_APC_0: 0xffffffff
10001 23:35:19.097572 INFO: [APUAPC] D4_APC_1: 0xffffffff
10002 23:35:19.101209 INFO: [APUAPC] D4_APC_2: 0x3fffff
10003 23:35:19.104137 INFO: [APUAPC] D4_APC_3: 0x0
10004 23:35:19.107725 INFO: [APUAPC] D5_APC_0: 0xffffffff
10005 23:35:19.111060 INFO: [APUAPC] D5_APC_1: 0xffffffff
10006 23:35:19.114662 INFO: [APUAPC] D5_APC_2: 0x3fffff
10007 23:35:19.115128 INFO: [APUAPC] D5_APC_3: 0x0
10008 23:35:19.117687 INFO: [APUAPC] D6_APC_0: 0xffffffff
10009 23:35:19.124621 INFO: [APUAPC] D6_APC_1: 0xffffffff
10010 23:35:19.125198 INFO: [APUAPC] D6_APC_2: 0x3fffff
10011 23:35:19.127895 INFO: [APUAPC] D6_APC_3: 0x0
10012 23:35:19.131074 INFO: [APUAPC] D7_APC_0: 0xffffffff
10013 23:35:19.134524 INFO: [APUAPC] D7_APC_1: 0xffffffff
10014 23:35:19.138056 INFO: [APUAPC] D7_APC_2: 0x3fffff
10015 23:35:19.140854 INFO: [APUAPC] D7_APC_3: 0x0
10016 23:35:19.144289 INFO: [APUAPC] D8_APC_0: 0xffffffff
10017 23:35:19.147602 INFO: [APUAPC] D8_APC_1: 0xffffffff
10018 23:35:19.150704 INFO: [APUAPC] D8_APC_2: 0x3fffff
10019 23:35:19.154435 INFO: [APUAPC] D8_APC_3: 0x0
10020 23:35:19.157648 INFO: [APUAPC] D9_APC_0: 0xffffffff
10021 23:35:19.160474 INFO: [APUAPC] D9_APC_1: 0xffffffff
10022 23:35:19.164374 INFO: [APUAPC] D9_APC_2: 0x3fffff
10023 23:35:19.167286 INFO: [APUAPC] D9_APC_3: 0x0
10024 23:35:19.170597 INFO: [APUAPC] D10_APC_0: 0xffffffff
10025 23:35:19.174272 INFO: [APUAPC] D10_APC_1: 0xffffffff
10026 23:35:19.177278 INFO: [APUAPC] D10_APC_2: 0x3fffff
10027 23:35:19.180523 INFO: [APUAPC] D10_APC_3: 0x0
10028 23:35:19.184216 INFO: [APUAPC] D11_APC_0: 0xffffffff
10029 23:35:19.187321 INFO: [APUAPC] D11_APC_1: 0xffffffff
10030 23:35:19.190769 INFO: [APUAPC] D11_APC_2: 0x3fffff
10031 23:35:19.194071 INFO: [APUAPC] D11_APC_3: 0x0
10032 23:35:19.197013 INFO: [APUAPC] D12_APC_0: 0xffffffff
10033 23:35:19.200741 INFO: [APUAPC] D12_APC_1: 0xffffffff
10034 23:35:19.204031 INFO: [APUAPC] D12_APC_2: 0x3fffff
10035 23:35:19.207628 INFO: [APUAPC] D12_APC_3: 0x0
10036 23:35:19.211158 INFO: [APUAPC] D13_APC_0: 0xffffffff
10037 23:35:19.213657 INFO: [APUAPC] D13_APC_1: 0xffffffff
10038 23:35:19.217184 INFO: [APUAPC] D13_APC_2: 0x3fffff
10039 23:35:19.220764 INFO: [APUAPC] D13_APC_3: 0x0
10040 23:35:19.223987 INFO: [APUAPC] D14_APC_0: 0xffffffff
10041 23:35:19.227127 INFO: [APUAPC] D14_APC_1: 0xffffffff
10042 23:35:19.230305 INFO: [APUAPC] D14_APC_2: 0x3fffff
10043 23:35:19.233610 INFO: [APUAPC] D14_APC_3: 0x0
10044 23:35:19.237075 INFO: [APUAPC] D15_APC_0: 0xffffffff
10045 23:35:19.240488 INFO: [APUAPC] D15_APC_1: 0xffffffff
10046 23:35:19.244032 INFO: [APUAPC] D15_APC_2: 0x3fffff
10047 23:35:19.247041 INFO: [APUAPC] D15_APC_3: 0x0
10048 23:35:19.251128 INFO: [APUAPC] APC_CON: 0x4
10049 23:35:19.254551 INFO: [NOCDAPC] D0_APC_0: 0x0
10050 23:35:19.257234 INFO: [NOCDAPC] D0_APC_1: 0x0
10051 23:35:19.261005 INFO: [NOCDAPC] D1_APC_0: 0x0
10052 23:35:19.264062 INFO: [NOCDAPC] D1_APC_1: 0xfff
10053 23:35:19.266981 INFO: [NOCDAPC] D2_APC_0: 0x0
10054 23:35:19.267460 INFO: [NOCDAPC] D2_APC_1: 0xfff
10055 23:35:19.270898 INFO: [NOCDAPC] D3_APC_0: 0x0
10056 23:35:19.274107 INFO: [NOCDAPC] D3_APC_1: 0xfff
10057 23:35:19.277242 INFO: [NOCDAPC] D4_APC_0: 0x0
10058 23:35:19.281021 INFO: [NOCDAPC] D4_APC_1: 0xfff
10059 23:35:19.284220 INFO: [NOCDAPC] D5_APC_0: 0x0
10060 23:35:19.287147 INFO: [NOCDAPC] D5_APC_1: 0xfff
10061 23:35:19.290496 INFO: [NOCDAPC] D6_APC_0: 0x0
10062 23:35:19.294063 INFO: [NOCDAPC] D6_APC_1: 0xfff
10063 23:35:19.296968 INFO: [NOCDAPC] D7_APC_0: 0x0
10064 23:35:19.297461 INFO: [NOCDAPC] D7_APC_1: 0xfff
10065 23:35:19.300299 INFO: [NOCDAPC] D8_APC_0: 0x0
10066 23:35:19.304048 INFO: [NOCDAPC] D8_APC_1: 0xfff
10067 23:35:19.307323 INFO: [NOCDAPC] D9_APC_0: 0x0
10068 23:35:19.309992 INFO: [NOCDAPC] D9_APC_1: 0xfff
10069 23:35:19.313740 INFO: [NOCDAPC] D10_APC_0: 0x0
10070 23:35:19.316740 INFO: [NOCDAPC] D10_APC_1: 0xfff
10071 23:35:19.320621 INFO: [NOCDAPC] D11_APC_0: 0x0
10072 23:35:19.323253 INFO: [NOCDAPC] D11_APC_1: 0xfff
10073 23:35:19.326762 INFO: [NOCDAPC] D12_APC_0: 0x0
10074 23:35:19.330335 INFO: [NOCDAPC] D12_APC_1: 0xfff
10075 23:35:19.333904 INFO: [NOCDAPC] D13_APC_0: 0x0
10076 23:35:19.337051 INFO: [NOCDAPC] D13_APC_1: 0xfff
10077 23:35:19.339812 INFO: [NOCDAPC] D14_APC_0: 0x0
10078 23:35:19.343118 INFO: [NOCDAPC] D14_APC_1: 0xfff
10079 23:35:19.343624 INFO: [NOCDAPC] D15_APC_0: 0x0
10080 23:35:19.346873 INFO: [NOCDAPC] D15_APC_1: 0xfff
10081 23:35:19.349989 INFO: [NOCDAPC] APC_CON: 0x4
10082 23:35:19.353292 INFO: [APUAPC] set_apusys_apc done
10083 23:35:19.356876 INFO: [DEVAPC] devapc_init done
10084 23:35:19.360262 INFO: GICv3 without legacy support detected.
10085 23:35:19.366827 INFO: ARM GICv3 driver initialized in EL3
10086 23:35:19.370143 INFO: Maximum SPI INTID supported: 639
10087 23:35:19.373403 INFO: BL31: Initializing runtime services
10088 23:35:19.379958 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10089 23:35:19.383731 INFO: SPM: enable CPC mode
10090 23:35:19.386603 INFO: mcdi ready for mcusys-off-idle and system suspend
10091 23:35:19.393292 INFO: BL31: Preparing for EL3 exit to normal world
10092 23:35:19.396440 INFO: Entry point address = 0x80000000
10093 23:35:19.397009 INFO: SPSR = 0x8
10094 23:35:19.403093
10095 23:35:19.403658
10096 23:35:19.404031
10097 23:35:19.406654 Starting depthcharge on Spherion...
10098 23:35:19.407257
10099 23:35:19.407639 Wipe memory regions:
10100 23:35:19.407990
10101 23:35:19.410819 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10102 23:35:19.411372 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10103 23:35:19.411818 Setting prompt string to ['asurada:']
10104 23:35:19.412267 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10105 23:35:19.412997 [0x00000040000000, 0x00000054600000)
10106 23:35:19.532586
10107 23:35:19.533149 [0x00000054660000, 0x00000080000000)
10108 23:35:19.792531
10109 23:35:19.793092 [0x000000821a7280, 0x000000ffe64000)
10110 23:35:20.537391
10111 23:35:20.537993 [0x00000100000000, 0x00000240000000)
10112 23:35:22.427337
10113 23:35:22.430171 Initializing XHCI USB controller at 0x11200000.
10114 23:35:23.468483
10115 23:35:23.471961 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10116 23:35:23.472525
10117 23:35:23.472906
10118 23:35:23.473260
10119 23:35:23.474121 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10121 23:35:23.575570 asurada: tftpboot 192.168.201.1 12172440/tftp-deploy-jip4knts/kernel/image.itb 12172440/tftp-deploy-jip4knts/kernel/cmdline
10122 23:35:23.576234 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10123 23:35:23.576734 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10124 23:35:23.581512 tftpboot 192.168.201.1 12172440/tftp-deploy-jip4knts/kernel/image.itbtp-deploy-jip4knts/kernel/cmdline
10125 23:35:23.582132
10126 23:35:23.582512 Waiting for link
10127 23:35:23.742468
10128 23:35:23.743030 R8152: Initializing
10129 23:35:23.743412
10130 23:35:23.745082 Version 9 (ocp_data = 6010)
10131 23:35:23.745547
10132 23:35:23.748947 R8152: Done initializing
10133 23:35:23.749536
10134 23:35:23.749982 Adding net device
10135 23:35:25.690332
10136 23:35:25.690907 done.
10137 23:35:25.691290
10138 23:35:25.691639 MAC: 00:e0:4c:78:7a:aa
10139 23:35:25.692069
10140 23:35:25.693301 Sending DHCP discover... done.
10141 23:35:25.693814
10142 23:35:25.696403 Waiting for reply... done.
10143 23:35:25.696949
10144 23:35:25.699707 Sending DHCP request... done.
10145 23:35:25.700167
10146 23:35:25.704470 Waiting for reply... done.
10147 23:35:25.705138
10148 23:35:25.705528 My ip is 192.168.201.12
10149 23:35:25.705986
10150 23:35:25.708208 The DHCP server ip is 192.168.201.1
10151 23:35:25.708780
10152 23:35:25.714348 TFTP server IP predefined by user: 192.168.201.1
10153 23:35:25.714937
10154 23:35:25.720887 Bootfile predefined by user: 12172440/tftp-deploy-jip4knts/kernel/image.itb
10155 23:35:25.721502
10156 23:35:25.724064 Sending tftp read request... done.
10157 23:35:25.724527
10158 23:35:25.728045 Waiting for the transfer...
10159 23:35:25.728468
10160 23:35:26.113000 00000000 ################################################################
10161 23:35:26.113704
10162 23:35:26.493743 00080000 ################################################################
10163 23:35:26.494297
10164 23:35:26.894629 00100000 ################################################################
10165 23:35:26.895149
10166 23:35:27.203606 00180000 ################################################################
10167 23:35:27.203775
10168 23:35:27.497417 00200000 ################################################################
10169 23:35:27.497590
10170 23:35:27.776950 00280000 ################################################################
10171 23:35:27.777120
10172 23:35:28.069253 00300000 ################################################################
10173 23:35:28.069427
10174 23:35:28.332703 00380000 ################################################################
10175 23:35:28.332875
10176 23:35:28.608322 00400000 ################################################################
10177 23:35:28.608493
10178 23:35:28.887254 00480000 ################################################################
10179 23:35:28.887395
10180 23:35:29.144520 00500000 ################################################################
10181 23:35:29.144661
10182 23:35:29.406360 00580000 ################################################################
10183 23:35:29.406500
10184 23:35:29.703496 00600000 ################################################################
10185 23:35:29.703663
10186 23:35:30.001550 00680000 ################################################################
10187 23:35:30.001725
10188 23:35:30.266552 00700000 ################################################################
10189 23:35:30.266718
10190 23:35:30.545454 00780000 ################################################################
10191 23:35:30.545656
10192 23:35:30.834757 00800000 ################################################################
10193 23:35:30.834902
10194 23:35:31.116210 00880000 ################################################################
10195 23:35:31.116354
10196 23:35:31.393607 00900000 ################################################################
10197 23:35:31.393743
10198 23:35:31.682183 00980000 ################################################################
10199 23:35:31.682322
10200 23:35:31.939795 00a00000 ################################################################
10201 23:35:31.939937
10202 23:35:32.223790 00a80000 ################################################################
10203 23:35:32.223933
10204 23:35:32.490739 00b00000 ################################################################
10205 23:35:32.490882
10206 23:35:32.776866 00b80000 ################################################################
10207 23:35:32.777006
10208 23:35:33.040170 00c00000 ################################################################
10209 23:35:33.040312
10210 23:35:33.295999 00c80000 ################################################################
10211 23:35:33.296141
10212 23:35:33.581798 00d00000 ################################################################
10213 23:35:33.581936
10214 23:35:33.873888 00d80000 ################################################################
10215 23:35:33.874028
10216 23:35:34.149119 00e00000 ################################################################
10217 23:35:34.149264
10218 23:35:34.400863 00e80000 ################################################################
10219 23:35:34.401003
10220 23:35:34.664920 00f00000 ################################################################
10221 23:35:34.665056
10222 23:35:34.937310 00f80000 ################################################################
10223 23:35:34.937445
10224 23:35:35.228570 01000000 ################################################################
10225 23:35:35.228718
10226 23:35:35.519238 01080000 ################################################################
10227 23:35:35.519381
10228 23:35:35.810247 01100000 ################################################################
10229 23:35:35.810386
10230 23:35:36.098074 01180000 ################################################################
10231 23:35:36.098214
10232 23:35:36.378041 01200000 ################################################################
10233 23:35:36.378191
10234 23:35:36.671735 01280000 ################################################################
10235 23:35:36.671873
10236 23:35:36.930982 01300000 ################################################################
10237 23:35:36.931118
10238 23:35:37.227210 01380000 ################################################################
10239 23:35:37.227347
10240 23:35:37.495816 01400000 ################################################################
10241 23:35:37.495957
10242 23:35:37.784062 01480000 ################################################################
10243 23:35:37.784202
10244 23:35:38.081683 01500000 ################################################################
10245 23:35:38.081826
10246 23:35:38.358613 01580000 ################################################################
10247 23:35:38.358785
10248 23:35:38.617842 01600000 ################################################################
10249 23:35:38.617981
10250 23:35:38.877594 01680000 ################################################################
10251 23:35:38.877740
10252 23:35:39.148200 01700000 ################################################################
10253 23:35:39.148338
10254 23:35:39.434439 01780000 ################################################################
10255 23:35:39.434582
10256 23:35:39.718991 01800000 ################################################################
10257 23:35:39.719126
10258 23:35:40.007747 01880000 ################################################################
10259 23:35:40.007890
10260 23:35:40.267781 01900000 ################################################################
10261 23:35:40.267923
10262 23:35:40.542503 01980000 ################################################################
10263 23:35:40.542650
10264 23:35:40.834577 01a00000 ################################################################
10265 23:35:40.834719
10266 23:35:41.129496 01a80000 ################################################################
10267 23:35:41.129675
10268 23:35:41.423731 01b00000 ################################################################
10269 23:35:41.424245
10270 23:35:41.465827 01b80000 ######## done.
10271 23:35:41.466273
10272 23:35:41.468942 The bootfile was 28894150 bytes long.
10273 23:35:41.469374
10274 23:35:41.472188 Sending tftp read request... done.
10275 23:35:41.472614
10276 23:35:41.475549 Waiting for the transfer...
10277 23:35:41.475979
10278 23:35:41.476317 00000000 # done.
10279 23:35:41.476646
10280 23:35:41.485686 Command line loaded dynamically from TFTP file: 12172440/tftp-deploy-jip4knts/kernel/cmdline
10281 23:35:41.486195
10282 23:35:41.505677 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12172440/extract-nfsrootfs-4jgnn23a,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10283 23:35:41.506129
10284 23:35:41.509145 Loading FIT.
10285 23:35:41.509719
10286 23:35:41.512070 Image ramdisk-1 has 17795489 bytes.
10287 23:35:41.512499
10288 23:35:41.512846 Image fdt-1 has 47278 bytes.
10289 23:35:41.513172
10290 23:35:41.516012 Image kernel-1 has 11049348 bytes.
10291 23:35:41.516535
10292 23:35:41.525717 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10293 23:35:41.526229
10294 23:35:41.542171 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10295 23:35:41.542725
10296 23:35:41.548985 Choosing best match conf-1 for compat google,spherion-rev2.
10297 23:35:41.552669
10298 23:35:41.557224 Connected to device vid:did:rid of 1ae0:0028:00
10299 23:35:41.565321
10300 23:35:41.568931 tpm_get_response: command 0x17b, return code 0x0
10301 23:35:41.569467
10302 23:35:41.572280 ec_init: CrosEC protocol v3 supported (256, 248)
10303 23:35:41.575993
10304 23:35:41.579801 tpm_cleanup: add release locality here.
10305 23:35:41.580329
10306 23:35:41.580675 Shutting down all USB controllers.
10307 23:35:41.582631
10308 23:35:41.583057 Removing current net device
10309 23:35:41.583405
10310 23:35:41.589171 Exiting depthcharge with code 4 at timestamp: 51516671
10311 23:35:41.589654
10312 23:35:41.592629 LZMA decompressing kernel-1 to 0x821a6718
10313 23:35:41.593157
10314 23:35:41.596003 LZMA decompressing kernel-1 to 0x40000000
10315 23:35:42.983851
10316 23:35:42.984411 jumping to kernel
10317 23:35:42.986206 end: 2.2.4 bootloader-commands (duration 00:00:24) [common]
10318 23:35:42.986760 start: 2.2.5 auto-login-action (timeout 00:04:02) [common]
10319 23:35:42.987178 Setting prompt string to ['Linux version [0-9]']
10320 23:35:42.987558 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10321 23:35:42.987943 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10322 23:35:43.066093
10323 23:35:43.068852 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10324 23:35:43.072526 start: 2.2.5.1 login-action (timeout 00:04:02) [common]
10325 23:35:43.073048 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10326 23:35:43.073455 Setting prompt string to []
10327 23:35:43.073964 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10328 23:35:43.074376 Using line separator: #'\n'#
10329 23:35:43.074721 No login prompt set.
10330 23:35:43.075077 Parsing kernel messages
10331 23:35:43.075585 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10332 23:35:43.076207 [login-action] Waiting for messages, (timeout 00:04:02)
10333 23:35:43.092728 [ 0.000000] Linux version 6.1.64-cip10-rt5 (KernelCI@build-j33605-arm64-gcc-10-defconfig-arm64-chromebook-7778h) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sun Dec 3 22:38:18 UTC 2023
10334 23:35:43.095858 [ 0.000000] random: crng init done
10335 23:35:43.102421 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10336 23:35:43.105566 [ 0.000000] efi: UEFI not found.
10337 23:35:43.112718 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10338 23:35:43.122351 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10339 23:35:43.128892 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10340 23:35:43.139140 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10341 23:35:43.145747 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10342 23:35:43.152109 [ 0.000000] printk: bootconsole [mtk8250] enabled
10343 23:35:43.158527 [ 0.000000] NUMA: No NUMA configuration found
10344 23:35:43.165510 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10345 23:35:43.168341 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcfa00-0x23efd1fff]
10346 23:35:43.172260 [ 0.000000] Zone ranges:
10347 23:35:43.178236 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10348 23:35:43.182233 [ 0.000000] DMA32 empty
10349 23:35:43.188642 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10350 23:35:43.191518 [ 0.000000] Movable zone start for each node
10351 23:35:43.195764 [ 0.000000] Early memory node ranges
10352 23:35:43.202222 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10353 23:35:43.208045 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10354 23:35:43.215186 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10355 23:35:43.221772 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10356 23:35:43.227988 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10357 23:35:43.234313 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10358 23:35:43.290780 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10359 23:35:43.297695 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10360 23:35:43.304234 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10361 23:35:43.307473 [ 0.000000] psci: probing for conduit method from DT.
10362 23:35:43.313832 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10363 23:35:43.317841 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10364 23:35:43.323462 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10365 23:35:43.327657 [ 0.000000] psci: SMC Calling Convention v1.2
10366 23:35:43.333641 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10367 23:35:43.337267 [ 0.000000] Detected VIPT I-cache on CPU0
10368 23:35:43.343885 [ 0.000000] CPU features: detected: GIC system register CPU interface
10369 23:35:43.350170 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10370 23:35:43.357235 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10371 23:35:43.363444 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10372 23:35:43.370041 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10373 23:35:43.376854 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10374 23:35:43.383596 [ 0.000000] alternatives: applying boot alternatives
10375 23:35:43.387054 [ 0.000000] Fallback order for Node 0: 0
10376 23:35:43.396859 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10377 23:35:43.397435 [ 0.000000] Policy zone: Normal
10378 23:35:43.422923 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12172440/extract-nfsrootfs-4jgnn23a,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10379 23:35:43.433327 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10380 23:35:43.443864 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10381 23:35:43.454248 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10382 23:35:43.460688 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10383 23:35:43.463381 <6>[ 0.000000] software IO TLB: area num 8.
10384 23:35:43.520000 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10385 23:35:43.669385 <6>[ 0.000000] Memory: 7952176K/8385536K available (17984K kernel code, 4116K rwdata, 17316K rodata, 8448K init, 615K bss, 400592K reserved, 32768K cma-reserved)
10386 23:35:43.675791 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10387 23:35:43.682380 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10388 23:35:43.685767 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10389 23:35:43.692741 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10390 23:35:43.698921 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10391 23:35:43.702243 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10392 23:35:43.712441 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10393 23:35:43.718769 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10394 23:35:43.725669 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10395 23:35:43.732330 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10396 23:35:43.735267 <6>[ 0.000000] GICv3: 608 SPIs implemented
10397 23:35:43.739077 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10398 23:35:43.745760 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10399 23:35:43.748831 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10400 23:35:43.755537 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10401 23:35:43.768594 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10402 23:35:43.778374 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10403 23:35:43.788557 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10404 23:35:43.795511 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10405 23:35:43.808614 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10406 23:35:43.815653 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10407 23:35:43.822493 <6>[ 0.009234] Console: colour dummy device 80x25
10408 23:35:43.832063 <6>[ 0.013981] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10409 23:35:43.838610 <6>[ 0.024423] pid_max: default: 32768 minimum: 301
10410 23:35:43.841745 <6>[ 0.029295] LSM: Security Framework initializing
10411 23:35:43.848957 <6>[ 0.034262] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10412 23:35:43.858565 <6>[ 0.042126] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10413 23:35:43.868735 <6>[ 0.051527] cblist_init_generic: Setting adjustable number of callback queues.
10414 23:35:43.872215 <6>[ 0.059014] cblist_init_generic: Setting shift to 3 and lim to 1.
10415 23:35:43.881833 <6>[ 0.065352] cblist_init_generic: Setting adjustable number of callback queues.
10416 23:35:43.888765 <6>[ 0.072779] cblist_init_generic: Setting shift to 3 and lim to 1.
10417 23:35:43.891993 <6>[ 0.079218] rcu: Hierarchical SRCU implementation.
10418 23:35:43.898785 <6>[ 0.079220] rcu: Max phase no-delay instances is 1000.
10419 23:35:43.905280 <6>[ 0.079243] printk: bootconsole [mtk8250] printing thread started
10420 23:35:43.912175 <6>[ 0.097544] EFI services will not be available.
10421 23:35:43.915027 <6>[ 0.097749] smp: Bringing up secondary CPUs ...
10422 23:35:43.918434 <6>[ 0.098059] Detected VIPT I-cache on CPU1
10423 23:35:43.928619 <6>[ 0.098127] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10424 23:35:43.934690 <6>[ 0.098160] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10425 23:35:43.943839 <6>[ 0.126005] Detected VIPT I-cache on CPU2
10426 23:35:43.950495 <6>[ 0.126052] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10427 23:35:43.957709 <6>[ 0.126066] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10428 23:35:43.964228 <6>[ 0.126321] Detected VIPT I-cache on CPU3
10429 23:35:43.970469 <6>[ 0.126367] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10430 23:35:43.977179 <6>[ 0.126380] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10431 23:35:43.980744 <6>[ 0.126691] CPU features: detected: Spectre-v4
10432 23:35:43.987623 <6>[ 0.126697] CPU features: detected: Spectre-BHB
10433 23:35:43.990738 <6>[ 0.126702] Detected PIPT I-cache on CPU4
10434 23:35:43.997542 <6>[ 0.126760] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10435 23:35:44.004367 <6>[ 0.126777] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10436 23:35:44.010309 <6>[ 0.127069] Detected PIPT I-cache on CPU5
10437 23:35:44.016855 <6>[ 0.127128] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10438 23:35:44.024058 <6>[ 0.127144] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10439 23:35:44.027029 <6>[ 0.127417] Detected PIPT I-cache on CPU6
10440 23:35:44.033508 <6>[ 0.127483] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10441 23:35:44.040167 <6>[ 0.127499] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10442 23:35:44.047068 <6>[ 0.127791] Detected PIPT I-cache on CPU7
10443 23:35:44.053529 <6>[ 0.127855] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10444 23:35:44.059968 <6>[ 0.127871] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10445 23:35:44.063787 <6>[ 0.127918] smp: Brought up 1 node, 8 CPUs
10446 23:35:44.070141 <6>[ 0.127923] SMP: Total of 8 processors activated.
10447 23:35:44.073453 <6>[ 0.127925] CPU features: detected: 32-bit EL0 Support
10448 23:35:44.083443 <6>[ 0.127927] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10449 23:35:44.090084 <6>[ 0.127930] CPU features: detected: Common not Private translations
10450 23:35:44.096728 <6>[ 0.127931] CPU features: detected: CRC32 instructions
10451 23:35:44.100104 <6>[ 0.127934] CPU features: detected: RCpc load-acquire (LDAPR)
10452 23:35:44.106188 <6>[ 0.127936] CPU features: detected: LSE atomic instructions
10453 23:35:44.113495 <6>[ 0.127938] CPU features: detected: Privileged Access Never
10454 23:35:44.119876 <6>[ 0.127939] CPU features: detected: RAS Extension Support
10455 23:35:44.126220 <6>[ 0.127943] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10456 23:35:44.129633 <6>[ 0.128008] CPU: All CPU(s) started at EL2
10457 23:35:44.136485 <6>[ 0.128009] alternatives: applying system-wide alternatives
10458 23:35:44.157403 ��_6.6.0
10459 23:35:44.164148 <6>[ 0.<348602] printk: console [ttyS0] printing thread started
10460 23:35:44.170676 6>[ 0.225529] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10461 23:35:44.177923 <6>[ 0.348612] printk: console [ttyS0] enabled
10462 23:35:44.181692 <6>[ 0.348616] printk: bootconsole [mtk8250] disabled
10463 23:35:44.188757 <6>[ 0.361589] printk: bootconsole [mtk8250] printing thread stopped
10464 23:35:44.195126 <6>[ 0.362808] SuperH (H)SCI(F) driver initialized
10465 23:35:44.198607 <6>[ 0.363287] msm_serial: driver initialized
10466 23:35:44.207840 <6>[ 0.367941] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10467 23:35:44.214876 <6>[ 0.367973] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10468 23:35:44.223607 <6>[ 0.368003] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10469 23:35:44.238642 <6>[ 0.368033] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10470 23:35:44.246320 <6>[ 0.368055] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10471 23:35:44.251242 <6>[ 0.368083] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10472 23:35:44.264405 <6>[ 0.368113] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10473 23:35:44.267971 <6>[ 0.368226] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10474 23:35:44.278453 <6>[ 0.368257] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10475 23:35:44.279009 <6>[ 0.378762] loop: module loaded
10476 23:35:44.287160 <6>[ 0.381309] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10477 23:35:44.290695 <4>[ 0.398376] mtk-pmic-keys: Failed to locate of_node [id: -1]
10478 23:35:44.294092 <6>[ 0.399275] megasas: 07.719.03.00-rc1
10479 23:35:44.300201 <6>[ 0.408732] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10480 23:35:44.307180 <6>[ 0.412760] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10481 23:35:44.313866 <6>[ 0.424962] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10482 23:35:44.323227 <6>[ 0.479923] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10483 23:35:44.790328 <6>[ 0.974248] Freeing initrd memory: 17372K
10484 23:35:44.796959 <6>[ 0.980472] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10485 23:35:44.800728 <6>[ 0.985123] tun: Universal TUN/TAP device driver, 1.6
10486 23:35:44.803346 <6>[ 0.985874] thunder_xcv, ver 1.0
10487 23:35:44.806864 <6>[ 0.985892] thunder_bgx, ver 1.0
10488 23:35:44.809861 <6>[ 0.985905] nicpf, ver 1.0
10489 23:35:44.817042 <6>[ 0.986941] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10490 23:35:44.823928 <6>[ 0.986944] hns3: Copyright (c) 2017 Huawei Corporation.
10491 23:35:44.826905 <6>[ 0.986969] hclge is initializing
10492 23:35:44.833376 <6>[ 0.986984] e1000: Intel(R) PRO/1000 Network Driver
10493 23:35:44.840357 <6>[ 0.986986] e1000: Copyright (c) 1999-2006 Intel Corporation.
10494 23:35:44.844161 <6>[ 0.987003] e1000e: Intel(R) PRO/1000 Network Driver
10495 23:35:44.851683 <6>[ 0.987005] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10496 23:35:44.854693 <6>[ 0.987026] igb: Intel(R) Gigabit Ethernet Network Driver
10497 23:35:44.861608 <6>[ 0.987028] igb: Copyright (c) 2007-2014 Intel Corporation.
10498 23:35:44.868432 <6>[ 0.987041] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10499 23:35:44.875383 <6>[ 0.987043] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10500 23:35:44.878667 <6>[ 0.987329] sky2: driver version 1.30
10501 23:35:44.881555 <6>[ 0.988388] VFIO - User Level meta-driver version: 0.3
10502 23:35:44.888410 <6>[ 0.991196] usbcore: registered new interface driver usb-storage
10503 23:35:44.895263 <6>[ 0.991373] usbcore: registered new device driver onboard-usb-hub
10504 23:35:44.902334 <6>[ 0.994079] mt6397-rtc mt6359-rtc: registered as rtc0
10505 23:35:44.912219 <6>[ 0.994228] mt6397-rtc mt6359-rtc: setting system clock to 2023-12-03T23:33:31 UTC (1701646411)
10506 23:35:44.915340 <6>[ 0.994831] i2c_dev: i2c /dev entries driver
10507 23:35:44.922010 <6>[ 1.001864] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10508 23:35:44.928467 <6>[ 1.016838] cpu cpu0: EM: created perf domain
10509 23:35:44.932190 <6>[ 1.017147] cpu cpu4: EM: created perf domain
10510 23:35:44.938634 <6>[ 1.019853] sdhci: Secure Digital Host Controller Interface driver
10511 23:35:44.941929 <6>[ 1.019855] sdhci: Copyright(c) Pierre Ossman
10512 23:35:44.948151 <6>[ 1.020197] Synopsys Designware Multimedia Card Interface Driver
10513 23:35:44.955539 <6>[ 1.020581] sdhci-pltfm: SDHCI platform and OF driver helper
10514 23:35:44.961731 <6>[ 1.024856] ledtrig-cpu: registered to indicate activity on CPUs
10515 23:35:44.968556 <6>[ 1.025502] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10516 23:35:44.971493 <6>[ 1.025507] mmc0: CQHCI version 5.10
10517 23:35:44.978204 <6>[ 1.025777] usbcore: registered new interface driver usbhid
10518 23:35:44.981571 <6>[ 1.025778] usbhid: USB HID core driver
10519 23:35:44.988732 <6>[ 1.025897] spi_master spi0: will run message pump with realtime priority
10520 23:35:45.002079 <6>[ 1.054733] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10521 23:35:45.015521 <6>[ 1.056498] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10522 23:35:45.022604 <6>[ 1.058576] cros-ec-spi spi0.0: Chrome EC device registered
10523 23:35:45.028316 <6>[ 1.070703] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10524 23:35:45.034955 <6>[ 1.071666] NET: Registered PF_PACKET protocol family
10525 23:35:45.038359 <6>[ 1.071736] 9pnet: Installing 9P2000 support
10526 23:35:45.045461 <5>[ 1.071774] Key type dns_resolver registered
10527 23:35:45.048607 <6>[ 1.072076] registered taskstats version 1
10528 23:35:45.055533 <5>[ 1.072088] Loading compiled-in X.509 certificates
10529 23:35:45.065798 <4>[ 1.091539] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10530 23:35:45.075690 <4>[ 1.091800] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10531 23:35:45.081804 <3>[ 1.091821] debugfs: File 'uA_load' in directory '/' already present!
10532 23:35:45.089252 <3>[ 1.091833] debugfs: File 'min_uV' in directory '/' already present!
10533 23:35:45.095123 <3>[ 1.091840] debugfs: File 'max_uV' in directory '/' already present!
10534 23:35:45.102379 <3>[ 1.091847] debugfs: File 'constraint_flags' in directory '/' already present!
10535 23:35:45.111928 <3>[ 1.094824] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10536 23:35:45.118593 <6>[ 1.102451] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10537 23:35:45.121567 <6>[ 1.103056] xhci-mtk 11200000.usb: xHCI Host Controller
10538 23:35:45.131991 <6>[ 1.103093] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10539 23:35:45.138562 <6>[ 1.103308] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10540 23:35:45.145020 <6>[ 1.103359] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10541 23:35:45.151761 <6>[ 1.103453] xhci-mtk 11200000.usb: xHCI Host Controller
10542 23:35:45.158403 <6>[ 1.103460] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10543 23:35:45.165042 <6>[ 1.103467] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10544 23:35:45.168536 <6>[ 1.103870] hub 1-0:1.0: USB hub found
10545 23:35:45.175292 <6>[ 1.103901] hub 1-0:1.0: 1 port detected
10546 23:35:45.181493 <6>[ 1.104272] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10547 23:35:45.185079 <6>[ 1.104782] hub 2-0:1.0: USB hub found
10548 23:35:45.191914 <6>[ 1.104795] hub 2-0:1.0: 1 port detected
10549 23:35:45.195113 <6>[ 1.107541] mtk-msdc 11f70000.mmc: Got CD GPIO
10550 23:35:45.202037 <6>[ 1.113939] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10551 23:35:45.211360 <6>[ 1.113947] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10552 23:35:45.221626 <4>[ 1.114033] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10553 23:35:45.228445 <6>[ 1.114532] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10554 23:35:45.235128 <6>[ 1.114533] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10555 23:35:45.244993 <6>[ 1.114833] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10556 23:35:45.252135 <6>[ 1.114848] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10557 23:35:45.258268 <6>[ 1.114851] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10558 23:35:45.268528 <6>[ 1.114856] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10559 23:35:45.278200 <6>[ 1.116430] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10560 23:35:45.285053 <6>[ 1.116446] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10561 23:35:45.294945 <6>[ 1.116450] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10562 23:35:45.301967 <6>[ 1.116453] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10563 23:35:45.311732 <6>[ 1.116457] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10564 23:35:45.317746 <6>[ 1.116461] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10565 23:35:45.328360 <6>[ 1.116464] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10566 23:35:45.334412 <6>[ 1.116468] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10567 23:35:45.344661 <6>[ 1.116471] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10568 23:35:45.351554 <6>[ 1.116475] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10569 23:35:45.360907 <6>[ 1.116479] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10570 23:35:45.368013 <6>[ 1.116482] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10571 23:35:45.377532 <6>[ 1.116486] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10572 23:35:45.384223 <6>[ 1.116492] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10573 23:35:45.394819 <6>[ 1.116496] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10574 23:35:45.400961 <6>[ 1.116853] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10575 23:35:45.407734 <6>[ 1.117521] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10576 23:35:45.414174 <6>[ 1.117780] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10577 23:35:45.420660 <6>[ 1.118027] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10578 23:35:45.427704 <6>[ 1.118265] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10579 23:35:45.437109 <6>[ 1.118427] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10580 23:35:45.443784 <6>[ 1.118435] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10581 23:35:45.453772 <6>[ 1.118437] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10582 23:35:45.463952 <6>[ 1.118440] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10583 23:35:45.474048 <6>[ 1.118444] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10584 23:35:45.483647 <6>[ 1.118447] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10585 23:35:45.490835 <6>[ 1.118450] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10586 23:35:45.500292 <6>[ 1.118452] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10587 23:35:45.510201 <6>[ 1.118455] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10588 23:35:45.520089 <6>[ 1.118458] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10589 23:35:45.529911 <6>[ 1.118461] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10590 23:35:45.539896 <6>[ 1.119477] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10591 23:35:45.544036 <6>[ 1.124316] mmc0: Command Queue Engine enabled
10592 23:35:45.550381 <6>[ 1.124327] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10593 23:35:45.553511 <6>[ 1.124775] mmcblk0: mmc0:0001 DA4128 116 GiB
10594 23:35:45.559821 <6>[ 1.127917] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10595 23:35:45.566634 <6>[ 1.128811] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10596 23:35:45.570148 <6>[ 1.129536] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10597 23:35:45.576779 <6>[ 1.130136] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10598 23:35:45.582992 <6>[ 1.146087] Trying to probe devices needed for running init ...
10599 23:35:45.589949 <6>[ 1.485753] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10600 23:35:45.593048 <6>[ 1.512688] hub 2-1:1.0: USB hub found
10601 23:35:45.599767 <6>[ 1.513066] hub 2-1:1.0: 3 ports detected
10602 23:35:45.603109 <6>[ 1.515391] hub 2-1:1.0: USB hub found
10603 23:35:45.606077 <6>[ 1.515760] hub 2-1:1.0: 3 ports detected
10604 23:35:45.612711 <6>[ 1.633579] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10605 23:35:45.619440 <6>[ 1.786456] hub 1-1:1.0: USB hub found
10606 23:35:45.622654 <6>[ 1.786864] hub 1-1:1.0: 4 ports detected
10607 23:35:45.626156 <6>[ 1.790450] hub 1-1:1.0: USB hub found
10608 23:35:45.629442 <6>[ 1.790854] hub 1-1:1.0: 4 ports detected
10609 23:35:45.685867 <6>[ 1.865735] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10610 23:35:45.921664 <6>[ 2.101700] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10611 23:35:46.046168 <6>[ 2.229675] hub 1-1.4:1.0: USB hub found
10612 23:35:46.049818 <6>[ 2.230132] hub 1-1.4:1.0: 2 ports detected
10613 23:35:46.053318 <6>[ 2.234415] hub 1-1.4:1.0: USB hub found
10614 23:35:46.060064 <6>[ 2.234767] hub 1-1.4:1.0: 2 ports detected
10615 23:35:46.341654 <6>[ 2.521670] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10616 23:35:46.525761 <6>[ 2.705651] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10617 23:35:57.253988 <6>[ 13.442689] ALSA device list:
10618 23:35:57.260628 <6>[ 13.442711] No soundcards found.
10619 23:35:57.263529 <6>[ 13.447127] Freeing unused kernel memory: 8448K
10620 23:35:57.267137 <6>[ 13.447275] Run /init as init process
10621 23:35:57.270532 Loading, please wait...
10622 23:35:57.294129 Starting version 247.3-7+deb11u2
10623 23:35:57.468320 <6>[ 13.653167] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10624 23:35:57.471447 <6>[ 13.657441] remoteproc remoteproc0: scp is available
10625 23:35:57.478193 <6>[ 13.657580] remoteproc remoteproc0: powering up scp
10626 23:35:57.485245 <6>[ 13.657590] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10627 23:35:57.491655 <6>[ 13.657647] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10628 23:35:57.524395 <3>[ 13.706162] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10629 23:35:57.531007 <3>[ 13.706192] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10630 23:35:57.540713 <3>[ 13.706197] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10631 23:35:57.547482 <3>[ 13.706351] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10632 23:35:57.557272 <3>[ 13.706360] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10633 23:35:57.564256 <3>[ 13.706365] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10634 23:35:57.574115 <3>[ 13.706374] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10635 23:35:57.580720 <3>[ 13.706377] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10636 23:35:57.590633 <3>[ 13.706413] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10637 23:35:57.597342 <3>[ 13.706442] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10638 23:35:57.604236 <3>[ 13.706446] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10639 23:35:57.614146 <3>[ 13.706449] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10640 23:35:57.621005 <3>[ 13.706486] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10641 23:35:57.627667 <3>[ 13.706488] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10642 23:35:57.638128 <3>[ 13.706492] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10643 23:35:57.644933 <3>[ 13.706496] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10644 23:35:57.655053 <3>[ 13.706499] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10645 23:35:57.661480 <3>[ 13.706522] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10646 23:35:57.667847 <6>[ 13.708891] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10647 23:35:57.678011 <6>[ 13.708935] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10648 23:35:57.687838 <6>[ 13.708943] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10649 23:35:57.694147 <4>[ 13.770596] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10650 23:35:57.700705 <4>[ 13.771770] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10651 23:35:57.708043 <6>[ 13.771991] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10652 23:35:57.713910 <6>[ 13.777329] mc: Linux media interface: v0.10
10653 23:35:57.720522 <6>[ 13.783535] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10654 23:35:57.727568 <6>[ 13.783566] remoteproc remoteproc0: remote processor scp is now up
10655 23:35:57.734073 <6>[ 13.783596] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10656 23:35:57.740686 <6>[ 13.791791] usbcore: registered new interface driver r8152
10657 23:35:57.750316 <4>[ 13.795719] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10658 23:35:57.753993 <4>[ 13.795719] Fallback method does not support PEC.
10659 23:35:57.763600 <3>[ 13.811148] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10660 23:35:57.770023 <6>[ 13.823837] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10661 23:35:57.780254 <6>[ 13.824991] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10662 23:35:57.787414 <6>[ 13.830702] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10663 23:35:57.793667 <6>[ 13.830711] pci_bus 0000:00: root bus resource [bus 00-ff]
10664 23:35:57.800115 <6>[ 13.830719] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10665 23:35:57.810548 <6>[ 13.830725] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10666 23:35:57.816777 <6>[ 13.830770] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10667 23:35:57.823343 <6>[ 13.830795] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10668 23:35:57.826871 <6>[ 13.830888] pci 0000:00:00.0: supports D1 D2
10669 23:35:57.833800 <6>[ 13.830891] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10670 23:35:57.843430 <6>[ 13.832623] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10671 23:35:57.850192 <6>[ 13.832754] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10672 23:35:57.856726 <6>[ 13.832785] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10673 23:35:57.863249 <6>[ 13.832806] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10674 23:35:57.869806 <6>[ 13.832825] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10675 23:35:57.876514 <6>[ 13.832947] pci 0000:01:00.0: supports D1 D2
10676 23:35:57.883248 <6>[ 13.832949] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10677 23:35:57.892936 <3>[ 13.834327] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10678 23:35:57.899905 <6>[ 13.845505] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10679 23:35:57.906170 <6>[ 13.845544] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10680 23:35:57.913044 <6>[ 13.845551] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10681 23:35:57.923061 <6>[ 13.845564] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10682 23:35:57.929741 <6>[ 13.845580] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10683 23:35:57.939353 <6>[ 13.845596] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10684 23:35:57.942395 <6>[ 13.845612] pci 0000:00:00.0: PCI bridge to [bus 01]
10685 23:35:57.952677 <6>[ 13.845620] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10686 23:35:57.959082 <6>[ 13.845749] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10687 23:35:57.962220 <6>[ 13.846722] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10688 23:35:57.969472 <6>[ 13.847202] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10689 23:35:57.976429 <6>[ 13.881990] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10690 23:35:57.986003 <6>[ 13.885168] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10691 23:35:57.995810 <6>[ 13.898478] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10692 23:35:58.005622 <6>[ 13.898838] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10693 23:35:58.012360 <6>[ 13.908473] videodev: Linux video capture interface: v2.00
10694 23:35:58.018726 <4>[ 13.922808] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10695 23:35:58.028629 <4>[ 13.922832] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10696 23:35:58.035466 <6>[ 13.923035] usbcore: registered new interface driver cdc_ether
10697 23:35:58.041923 <5>[ 13.928276] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10698 23:35:58.048840 <6>[ 13.934987] usbcore: registered new interface driver r8153_ecm
10699 23:35:58.055192 <5>[ 13.942901] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10700 23:35:58.065072 <4>[ 13.943028] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10701 23:35:58.068464 <6>[ 13.943040] cfg80211: failed to load regulatory.db
10702 23:35:58.071587 <6>[ 13.948684] Bluetooth: Core ver 2.22
10703 23:35:58.078485 <6>[ 13.948804] NET: Registered PF_BLUETOOTH protocol family
10704 23:35:58.084873 <6>[ 13.948808] Bluetooth: HCI device and connection manager initialized
10705 23:35:58.091432 <6>[ 13.948874] Bluetooth: HCI socket layer initialized
10706 23:35:58.094906 <6>[ 13.948881] Bluetooth: L2CAP socket layer initialized
10707 23:35:58.101529 <6>[ 13.948894] Bluetooth: SCO socket layer initialized
10708 23:35:58.105025 <6>[ 13.977516] r8152 2-1.3:1.0 eth0: v1.12.13
10709 23:35:58.111573 <6>[ 13.982638] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10710 23:35:58.124848 <6>[ 13.983957] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10711 23:35:58.131529 <6>[ 13.984139] usbcore: registered new interface driver uvcvideo
10712 23:35:58.134655 <6>[ 13.987942] r8152 2-1.3:1.0 enx00e04c787aaa: renamed from eth0
10713 23:35:58.141551 <6>[ 14.022356] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10714 23:35:58.148321 <6>[ 14.022365] usbcore: registered new interface driver btusb
10715 23:35:58.157803 <4>[ 14.024250] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10716 23:35:58.164770 <3>[ 14.024273] Bluetooth: hci0: Failed to load firmware file (-2)
10717 23:35:58.171047 <3>[ 14.024277] Bluetooth: hci0: Failed to set up firmware (-2)
10718 23:35:58.181442 <4>[ 14.024281] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10719 23:35:58.187880 <6>[ 14.049539] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10720 23:35:58.194481 <6>[ 14.049665] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10721 23:35:58.201282 <6>[ 14.069563] mt7921e 0000:01:00.0: ASIC revision: 79610010
10722 23:35:58.211191 <4>[ 14.164685] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10723 23:35:58.224860 <4>[ 14.271238] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10724 23:35:58.234534 <4>[ 14.375121] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10725 23:35:58.237325 Begin: Loading essential drivers ... done.
10726 23:35:58.243984 Begin: Running /scripts/init-premount ... done.
10727 23:35:58.251179 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10728 23:35:58.257135 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10729 23:35:58.264068 Device /sys/class/net/enx00e04c787aaa found
10730 23:35:58.264640 done.
10731 23:35:58.270607 IP-Config: enx00e04c787aaa hardware address 00:e0:4c:78:7a:aa mtu 1500 DHCP
10732 23:35:58.299884 <4>[ 14.479346] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10733 23:35:58.403860 <4>[ 14.582865] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10734 23:35:58.507620 <4>[ 14.686592] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10735 23:35:58.611986 <4>[ 14.790624] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10736 23:35:58.715669 <4>[ 14.894434] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10737 23:35:58.819588 <4>[ 14.998559] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10738 23:35:58.923388 <4>[ 15.102381] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10739 23:35:59.016632 <3>[ 15.204346] mt7921e 0000:01:00.0: hardware init failed
10740 23:35:59.305697 IP-Config: no response after 2 secs - giving up
10741 23:35:59.336997 IP-Config: enx00e04c787aaa hardware address 00:e0:4c:78:7a:aa mtu 1500 DHCP
10742 23:35:59.453160 <6>[ 15.638001] r8152 2-1.3:1.0 enx00e04c787aaa: carrier on
10743 23:36:00.442588 IP-Config: enx00e04c787aaa complete (dhcp from 192.168.201.1):
10744 23:36:00.449981 address: 192.168.201.12 broadcast: 192.168.201.255 netmask: 255.255.255.0
10745 23:36:00.456391 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10746 23:36:00.462960 host : mt8192-asurada-spherion-r0-cbg-0
10747 23:36:00.469547 domain : lava-rack
10748 23:36:00.472882 rootserver: 192.168.201.1 rootpath:
10749 23:36:00.476076 filename :
10750 23:36:00.589226 done.
10751 23:36:00.596004 Begin: Running /scripts/nfs-bottom ... done.
10752 23:36:00.617651 Begin: Running /scripts/init-bottom ... done.
10753 23:36:01.808088 <6>[ 17.996939] NET: Registered PF_INET6 protocol family
10754 23:36:01.811338 <6>[ 17.998803] Segment Routing with IPv6
10755 23:36:01.817777 <6>[ 17.998873] In-situ OAM (IOAM) with IPv6
10756 23:36:01.921554 <30>[ 18.093248] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10757 23:36:01.927900 <30>[ 18.094369] systemd[1]: Detected architecture arm64.
10758 23:36:01.928420
10759 23:36:01.934349 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10760 23:36:01.934864
10761 23:36:01.956194 <30>[ 18.144064] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10762 23:36:02.783770 <30>[ 18.966696] systemd[1]: Queued start job for default target Graphical Interface.
10763 23:36:02.822633 [[0;32m OK [<30>[ 19.008129] systemd[1]: Created slice system-getty.slice.
10764 23:36:02.825802 0m] Created slice [0;1;39msystem-getty.slice[0m.
10765 23:36:02.845859 [[0;32m OK [0m] Created slic<30>[ 19.031064] systemd[1]: Created slice system-modprobe.slice.
10766 23:36:02.848679 e [0;1;39msystem-modprobe.slice[0m.
10767 23:36:02.869644 [[0;32m OK [0m] Created slic<30>[ 19.054991] systemd[1]: Created slice system-serial\x2dgetty.slice.
10768 23:36:02.875883 e [0;1;39msystem-serial\x2dgetty.slice[0m.
10769 23:36:02.893975 [[0;32m OK [0m] Created slic<30>[ 19.079508] systemd[1]: Created slice User and Session Slice.
10770 23:36:02.897256 e [0;1;39mUser and Session Slice[0m.
10771 23:36:02.919985 [[0;32m OK [0m] Started [0;<30>[ 19.102508] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10772 23:36:02.923629 1;39mDispatch Password …ts to Console Directory Watch[0m.
10773 23:36:02.947555 [[0;32m OK [0m] Started [0;1;39mForward Pas<30>[ 19.129870] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10774 23:36:02.950883 sword R…uests to Wall Directory Watch[0m.
10775 23:36:02.975052 [[0;32m OK [0m] Reached target [0;1;39mLoca<30>[ 19.153849] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10776 23:36:02.981894 <30>[ 19.154037] systemd[1]: Reached target Local Encrypted Volumes.
10777 23:36:02.985075 l Encrypted Volumes[0m.
10778 23:36:03.004402 [[0;32m OK [0m] Reached target [0;1;39mPath<30>[ 19.190111] systemd[1]: Reached target Paths.
10779 23:36:03.004980 s[0m.
10780 23:36:03.027274 [[0;32m OK [0m] Reached target [0;1;39mRemo<30>[ 19.209657] systemd[1]: Reached target Remote File Systems.
10781 23:36:03.027858 te File Systems[0m.
10782 23:36:03.048501 [[0;32m OK [0m] Reached target [0;1;39mSlic<30>[ 19.234076] systemd[1]: Reached target Slices.
10783 23:36:03.049080 es[0m.
10784 23:36:03.068076 [[0;32m OK [0m] Reached target [0;1;39mSwap<30>[ 19.253689] systemd[1]: Reached target Swap.
10785 23:36:03.068651 [0m.
10786 23:36:03.091533 [[0;32m OK [0m] Listening on [0;1;39minitct<30>[ 19.274191] systemd[1]: Listening on initctl Compatibility Named Pipe.
10787 23:36:03.095359 l Compatibility Named Pipe[0m.
10788 23:36:03.105275 [[0;32m OK [0m] Listening on [0;1;39mJourna<30>[ 19.290378] systemd[1]: Listening on Journal Audit Socket.
10789 23:36:03.108374 l Audit Socket[0m.
10790 23:36:03.129781 [[0;32m OK [0m] Listening on<30>[ 19.315087] systemd[1]: Listening on Journal Socket (/dev/log).
10791 23:36:03.132677 [0;1;39mJournal Socket (/dev/log)[0m.
10792 23:36:03.153754 [[0;32m OK [0m] Listening on<30>[ 19.338936] systemd[1]: Listening on Journal Socket.
10793 23:36:03.156563 [0;1;39mJournal Socket[0m.
10794 23:36:03.173705 [[0;32m OK [0m] Listening on<30>[ 19.359497] systemd[1]: Listening on Network Service Netlink Socket.
10795 23:36:03.180241 [0;1;39mNetwork Service Netlink Socket[0m.
10796 23:36:03.200204 [[0;32m OK [0m] Listening on [0;1;39mudev C<30>[ 19.385693] systemd[1]: Listening on udev Control Socket.
10797 23:36:03.203124 ontrol Socket[0m.
10798 23:36:03.220412 [[0;32m OK [0m] Listening on [0;1;39mudev K<30>[ 19.406143] systemd[1]: Listening on udev Kernel Socket.
10799 23:36:03.223527 ernel Socket[0m.
10800 23:36:03.283398 Mounting [0;1;39mHuge Pages File Syste<30>[ 19.465867] systemd[1]: Mounting Huge Pages File System...
10801 23:36:03.283969 m[0m...
10802 23:36:03.306936 Mounting [0;1;39mPOSIX Message Queue F<30>[ 19.489422] systemd[1]: Mounting POSIX Message Queue File System...
10803 23:36:03.307500 ile System[0m...
10804 23:36:03.336239 Mounting [0;1;39mKernel Debug File Sys<30>[ 19.518305] systemd[1]: Mounting Kernel Debug File System...
10805 23:36:03.336676 tem[0m...
10806 23:36:03.355504 <30>[ 19.538375] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10807 23:36:03.368830 Starting [0;1;39mCreat<30>[ 19.551019] systemd[1]: Starting Create list of static device nodes for the current kernel...
10808 23:36:03.372053 e list of st…odes for the current kernel[0m...
10809 23:36:03.402329 Starting [0;1;39mLoad <30>[ 19.587698] systemd[1]: Starting Load Kernel Module configfs...
10810 23:36:03.405324 Kernel Module configfs[0m...
10811 23:36:03.428758 Starting [0;1;39mLoad <30>[ 19.614538] systemd[1]: Starting Load Kernel Module drm...
10812 23:36:03.432225 Kernel Module drm[0m...
10813 23:36:03.453181 Starting [0;1;39mLoad <30>[ 19.638474] systemd[1]: Starting Load Kernel Module fuse...
10814 23:36:03.456089 Kernel Module fuse[0m...
10815 23:36:03.488536 <6>[ 19.676158] fuse: init (API version 7.37)
10816 23:36:03.498225 <30>[ 19.677347] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10817 23:36:03.509808 Starting [0;1;39mJourn<30>[ 19.695269] systemd[1]: Starting Journal Service...
10818 23:36:03.510391 al Service[0m...
10819 23:36:03.546672 Startin<30>[ 19.732106] systemd[1]: Starting Load Kernel Modules...
10820 23:36:03.549955 g [0;1;39mLoad Kernel Modules[0m...
10821 23:36:03.578908 Startin<30>[ 19.764487] systemd[1]: Starting Remount Root and Kernel File Systems...
10822 23:36:03.585539 g [0;1;39mRemount Root and Kernel File Systems[0m...
10823 23:36:03.606042 Starting [0;1;39mColdp<30>[ 19.791429] systemd[1]: Starting Coldplug All udev Devices...
10824 23:36:03.609124 lug All udev Devices[0m...
10825 23:36:03.635611 <3>[ 19.819278] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10826 23:36:03.642033 <30>[ 19.821536] systemd[1]: Mounted Huge Pages File System.
10827 23:36:03.648577 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10828 23:36:03.659422 <3>[ 19.843641] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10829 23:36:03.669082 [[0;32m OK [0m] Mounted [0;<30>[ 19.854900] systemd[1]: Mounted POSIX Message Queue File System.
10830 23:36:03.672407 1;39mPOSIX Message Queue File System[0m.
10831 23:36:03.693265 [[0;32m OK [0m] Mounted [0;<30>[ 19.878526] systemd[1]: Mounted Kernel Debug File System.
10832 23:36:03.703781 1;39mKernel Debu<3>[ 19.884855] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10833 23:36:03.704320 g File System[0m.
10834 23:36:03.719619 <3>[ 19.904925] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10835 23:36:03.733515 [[0;32m OK [0m] Finished [0<30>[ 19.915735] systemd[1]: Finished Create list of static device nodes for the current kernel.
10836 23:36:03.743372 ;1;39mCreate lis<3>[ 19.926531] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10837 23:36:03.746967 t of st… nodes for the current kernel[0m.
10838 23:36:03.763820 <3>[ 19.946857] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10839 23:36:03.774149 [[0;32m OK [0m] Finished [0;1;39mLoad Kerne<30>[ 19.950522] systemd[1]: modprobe@configfs.service: Succeeded.
10840 23:36:03.781366 l Module configf<30>[ 19.951172] systemd[1]: Finished Load Kernel Module configfs.
10841 23:36:03.784658 s[0m.
10842 23:36:03.790749 <3>[ 19.968074] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10843 23:36:03.801992 [[0;32m OK [0m] Finished [0<30>[ 19.986625] systemd[1]: modprobe@drm.service: Succeeded.
10844 23:36:03.809171 ;1;39mLoad Kerne<30>[ 19.987265] systemd[1]: Finished Load Kernel Module drm.
10845 23:36:03.819238 l Module drm[0m<3>[ 19.988522] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10846 23:36:03.819808 .
10847 23:36:03.829302 <3>[ 20.009878] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10848 23:36:03.836820 [[0;32m OK [0m] Finished [0<30>[ 20.023087] systemd[1]: modprobe@fuse.service: Succeeded.
10849 23:36:03.846329 ;1;39mLoad Kerne<30>[ 20.023691] systemd[1]: Finished Load Kernel Module fuse.
10850 23:36:03.856522 l Module fuse[0<3>[ 20.030616] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10851 23:36:03.857097 m.
10852 23:36:03.877655 [[0;32m OK [0m] Finished [0<30>[ 20.062968] systemd[1]: Finished Load Kernel Modules.
10853 23:36:03.880535 ;1;39mLoad Kernel Modules[0m.
10854 23:36:03.896482 [[0;32m OK [0m] Started [0;1;39mJournal Ser<30>[ 20.082043] systemd[1]: Started Journal Service.
10855 23:36:03.899694 vice[0m.
10856 23:36:03.918041 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10857 23:36:03.965557 Mounting [0;1;39mFUSE Control File System[0m...
10858 23:36:03.983685 Mounting [0;1;39mKernel Configuration File System[0m...
10859 23:36:04.007001 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10860 23:36:04.032794 Starting [0;1;39mLoad/Save Random Seed[0m...
10861 23:36:04.060456 Starting [0;1;39mApply<46>[ 20.241644] systemd-journald[305]: Received client request to flush runtime journal.
10862 23:36:04.060938 Kernel Variables[0m...
10863 23:36:04.118140 <4>[ 20.297216] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10864 23:36:04.127615 <3>[ 20.297232] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10865 23:36:04.131466 Starting [0;1;39mCreate System Users[0m...
10866 23:36:04.159024 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10867 23:36:04.172563 See 'systemctl status systemd-udev-trigger.service' for details.
10868 23:36:04.189310 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10869 23:36:04.204711 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10870 23:36:04.221556 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10871 23:36:05.147288 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10872 23:36:05.504976 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10873 23:36:05.539501 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10874 23:36:05.569310 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10875 23:36:05.643233 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10876 23:36:05.656958 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10877 23:36:05.676348 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10878 23:36:05.741185 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10879 23:36:05.768874 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10880 23:36:05.937244 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10881 23:36:05.997544 Starting [0;1;39mNetwork Service[0m...
10882 23:36:06.037040 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10883 23:36:06.121885 Starting [0;1;39mNetwork Time Synchronization[0m...
10884 23:36:06.145947 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10885 23:36:06.347790 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10886 23:36:06.368252 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10887 23:36:06.421505 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10888 23:36:06.636447 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10889 23:36:06.652476 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10890 23:36:06.671286 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10891 23:36:06.688135 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10892 23:36:06.704602 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10893 23:36:06.724516 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10894 23:36:06.755449 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10895 23:36:06.779920 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10896 23:36:06.792130 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10897 23:36:06.808283 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10898 23:36:06.845486 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10899 23:36:07.222098 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10900 23:36:07.585255 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10901 23:36:07.914624 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10902 23:36:07.927695 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10903 23:36:07.951660 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10904 23:36:07.964585 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10905 23:36:07.980195 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10906 23:36:08.030030 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10907 23:36:08.081658 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
10908 23:36:08.121254 Starting [0;1;39mUser Login Management[0m...
10909 23:36:08.240255 Starting [0;1;39mNetwork Name Resolution[0m...
10910 23:36:08.262641 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10911 23:36:08.349863 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10912 23:36:08.418110 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
10913 23:36:08.437660 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10914 23:36:09.035135 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10915 23:36:09.057727 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10916 23:36:09.075937 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10917 23:36:09.139358 Starting [0;1;39mPermit User Sessions[0m...
10918 23:36:09.175581 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10919 23:36:09.239294 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10920 23:36:09.295007 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10921 23:36:09.315187 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10922 23:36:09.330258 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10923 23:36:09.349814 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10924 23:36:09.397708 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10925 23:36:09.459706 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10926 23:36:09.514446
10927 23:36:09.514604
10928 23:36:09.518061 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10929 23:36:09.518144
10930 23:36:09.520875 debian-bullseye-arm64 login: root (automatic login)
10931 23:36:09.520947
10932 23:36:09.521009
10933 23:36:09.843849 Linux debian-bullseye-arm64 6.1.64-cip10-rt5 #1 SMP PREEMPT Sun Dec 3 22:38:18 UTC 2023 aarch64
10934 23:36:09.844353
10935 23:36:09.851133 The programs included with the Debian GNU/Linux system are free software;
10936 23:36:09.857400 the exact distribution terms for each program are described in the
10937 23:36:09.860935 individual files in /usr/share/doc/*/copyright.
10938 23:36:09.861358
10939 23:36:09.867071 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10940 23:36:09.870809 permitted by applicable law.
10941 23:36:10.799142 Matched prompt #10: / #
10943 23:36:10.800299 Setting prompt string to ['/ #']
10944 23:36:10.800749 end: 2.2.5.1 login-action (duration 00:00:28) [common]
10946 23:36:10.801867 end: 2.2.5 auto-login-action (duration 00:00:28) [common]
10947 23:36:10.802363 start: 2.2.6 expect-shell-connection (timeout 00:03:34) [common]
10948 23:36:10.802764 Setting prompt string to ['/ #']
10949 23:36:10.803099 Forcing a shell prompt, looking for ['/ #']
10951 23:36:10.853994 / #
10952 23:36:10.854593 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10953 23:36:10.854992 Waiting using forced prompt support (timeout 00:02:30)
10954 23:36:10.860735
10955 23:36:10.861729 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10956 23:36:10.862251 start: 2.2.7 export-device-env (timeout 00:03:34) [common]
10958 23:36:10.963595 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12172440/extract-nfsrootfs-4jgnn23a'
10959 23:36:10.969702 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12172440/extract-nfsrootfs-4jgnn23a'
10961 23:36:11.071172 / # export NFS_SERVER_IP='192.168.201.1'
10962 23:36:11.077785 export NFS_SERVER_IP='192.168.201.1'
10963 23:36:11.078625 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10964 23:36:11.079177 end: 2.2 depthcharge-retry (duration 00:01:26) [common]
10965 23:36:11.079689 end: 2 depthcharge-action (duration 00:01:26) [common]
10966 23:36:11.080196 start: 3 lava-test-retry (timeout 00:07:54) [common]
10967 23:36:11.080697 start: 3.1 lava-test-shell (timeout 00:07:54) [common]
10968 23:36:11.081123 Using namespace: common
10970 23:36:11.182322 / # #
10971 23:36:11.182969 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
10972 23:36:11.188914 #
10973 23:36:11.189733 Using /lava-12172440
10975 23:36:11.291026 / # export SHELL=/bin/bash
10976 23:36:11.297761 export SHELL=/bin/bash
10978 23:36:11.399587 / # . /lava-12172440/environment
10979 23:36:11.406165 . /lava-12172440/environment
10981 23:36:11.512825 / # /lava-12172440/bin/lava-test-runner /lava-12172440/0
10982 23:36:11.513448 Test shell timeout: 10s (minimum of the action and connection timeout)
10983 23:36:11.519650 /lava-12172440/bin/lava-test-runner /lava-12172440/0
10984 23:36:11.798292 + export TESTRUN_ID=0_timesync-off
10985 23:36:11.801737 + TESTRUN_ID=0_timesync-off
10986 23:36:11.805420 + cd /lava-12172440/0/tests/0_timesync-off
10987 23:36:11.808109 ++ cat uuid
10988 23:36:11.811550 + UUID=12172440_1.6.2.3.1
10989 23:36:11.811980 + set +x
10990 23:36:11.818979 <LAVA_SIGNAL_STARTRUN 0_timesync-off 12172440_1.6.2.3.1>
10991 23:36:11.819690 Received signal: <STARTRUN> 0_timesync-off 12172440_1.6.2.3.1
10992 23:36:11.820083 Starting test lava.0_timesync-off (12172440_1.6.2.3.1)
10993 23:36:11.820507 Skipping test definition patterns.
10994 23:36:11.821316 + systemctl stop systemd-timesyncd
10995 23:36:11.889653 + set +x
10996 23:36:11.892980 <LAVA_SIGNAL_ENDRUN 0_timesync-off 12172440_1.6.2.3.1>
10997 23:36:11.893738 Received signal: <ENDRUN> 0_timesync-off 12172440_1.6.2.3.1
10998 23:36:11.894242 Ending use of test pattern.
10999 23:36:11.894725 Ending test lava.0_timesync-off (12172440_1.6.2.3.1), duration 0.07
11001 23:36:11.970347 + export TESTRUN_ID=1_kselftest-rtc
11002 23:36:11.973933 + TESTRUN_ID=1_kselftest-rtc
11003 23:36:11.977196 + cd /lava-12172440/0/tests/1_kselftest-rtc
11004 23:36:11.979866 ++ cat uuid
11005 23:36:11.983158 + UUID=12172440_1.6.2.3.5
11006 23:36:11.983595 + set +x
11007 23:36:11.990016 <LAVA_SIGNAL_STARTRUN 1_kselftest-rtc 12172440_1.6.2.3.5>
11008 23:36:11.990710 Received signal: <STARTRUN> 1_kselftest-rtc 12172440_1.6.2.3.5
11009 23:36:11.991096 Starting test lava.1_kselftest-rtc (12172440_1.6.2.3.5)
11010 23:36:11.991611 Skipping test definition patterns.
11011 23:36:11.993257 + cd ./automated/linux/kselftest/
11012 23:36:12.020216 + ./kselftest.sh -c rtc -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.64-cip10-rt5/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip-gitlab -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11013 23:36:12.056941 INFO: install_deps skipped
11014 23:36:12.174345 --2023-12-03 23:33:58-- http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.64-cip10-rt5/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11015 23:36:12.187404 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11016 23:36:12.316870 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11017 23:36:12.448408 HTTP request sent, awaiting response... 200 OK
11018 23:36:12.451038 Length: 2966880 (2.8M) [application/octet-stream]
11019 23:36:12.454714 Saving to: 'kselftest.tar.xz'
11020 23:36:12.455183
11021 23:36:12.455561
11022 23:36:12.705279 kselftest.tar.xz 0%[ ] 0 --.-KB/s
11023 23:36:12.963788 kselftest.tar.xz 1%[ ] 49.22K 192KB/s
11024 23:36:13.398955 kselftest.tar.xz 7%[> ] 217.50K 423KB/s
11025 23:36:13.666623 kselftest.tar.xz 28%[====> ] 818.47K 862KB/s
11026 23:36:13.745807 kselftest.tar.xz 80%[===============> ] 2.29M 1.88MB/s
11027 23:36:13.752025 kselftest.tar.xz 100%[===================>] 2.83M 2.18MB/s in 1.3s
11028 23:36:13.752495
11029 23:36:14.011060 2023-12-03 23:34:00 (2.18 MB/s) - 'kselftest.tar.xz' saved [2966880/2966880]
11030 23:36:14.011428
11031 23:36:19.348177 skiplist:
11032 23:36:19.351314 ========================================
11033 23:36:19.355025 ========================================
11034 23:36:19.397398 rtc:rtctest
11035 23:36:19.416123 ============== Tests to run ===============
11036 23:36:19.416555 rtc:rtctest
11037 23:36:19.419608 ===========End Tests to run ===============
11038 23:36:19.422713 shardfile-rtc pass
11039 23:36:19.522457 <12>[ 35.710487] kselftest: Running tests in rtc
11040 23:36:19.522915 TAP version 13
11041 23:36:19.536880 1..1
11042 23:36:19.567791 # selftests: rtc: rtctest
11043 23:36:20.001725 # TAP version 13
11044 23:36:20.002295 # 1..8
11045 23:36:20.004975 # # Starting 8 tests from 2 test cases.
11046 23:36:20.008501 # # RUN rtc.date_read ...
11047 23:36:20.015431 # # rtctest.c:49:date_read:Current RTC date/time is 03/12/2023 23:34:05.
11048 23:36:20.018233 # # OK rtc.date_read
11049 23:36:20.021902 # ok 1 rtc.date_read
11050 23:36:20.024781 # # RUN rtc.date_read_loop ...
11051 23:36:20.034868 # # rtctest.c:88:date_read_loop:Continuously reading RTC time for 30s (with 11ms breaks after every read).
11052 23:36:27.842361 <6>[ 44.033824] vpu: disabling
11053 23:36:27.846076 <6>[ 44.033951] vproc2: disabling
11054 23:36:27.848882 <6>[ 44.034005] vproc1: disabling
11055 23:36:27.852089 <6>[ 44.034061] vaud18: disabling
11056 23:36:27.859020 <6>[ 44.034313] vsram_others: disabling
11057 23:36:27.862094 <6>[ 44.034493] va09: disabling
11058 23:36:27.865949 <6>[ 44.034572] vsram_md: disabling
11059 23:36:27.868465 <6>[ 44.034705] Vgpu: disabling
11060 23:36:49.921185 # # rtctest.c:115:date_read_loop:Performed 2629 RTC time reads.
11061 23:36:49.924476 # # OK rtc.date_read_loop
11062 23:36:49.927934 # ok 2 rtc.date_read_loop
11063 23:36:49.930840 # # RUN rtc.uie_read ...
11064 23:36:52.901751 # # OK rtc.uie_read
11065 23:36:52.904697 # ok 3 rtc.uie_read
11066 23:36:52.908844 # # RUN rtc.uie_select ...
11067 23:36:55.901741 # # OK rtc.uie_select
11068 23:36:55.904493 # ok 4 rtc.uie_select
11069 23:36:55.908333 # # RUN rtc.alarm_alm_set ...
11070 23:36:55.914143 # # rtctest.c:202:alarm_alm_set:Alarm time now set to 23:34:45.
11071 23:36:55.917890 # # rtctest.c:207:alarm_alm_set:Expected -1 (-1) != rc (-1)
11072 23:36:55.924678 # # alarm_alm_set: Test terminated by assertion
11073 23:36:55.927782 # # FAIL rtc.alarm_alm_set
11074 23:36:55.931540 # not ok 5 rtc.alarm_alm_set
11075 23:36:55.934334 # # RUN rtc.alarm_wkalm_set ...
11076 23:36:55.941273 # # rtctest.c:258:alarm_wkalm_set:Alarm time now set to 03/12/2023 23:34:45.
11077 23:36:58.903933 # # OK rtc.alarm_wkalm_set
11078 23:36:58.904486 # ok 6 rtc.alarm_wkalm_set
11079 23:36:58.910758 # # RUN rtc.alarm_alm_set_minute ...
11080 23:36:58.913799 # # rtctest.c:304:alarm_alm_set_minute:Alarm time now set to 23:35:00.
11081 23:36:58.920680 # # rtctest.c:309:alarm_alm_set_minute:Expected -1 (-1) != rc (-1)
11082 23:36:58.926831 # # alarm_alm_set_minute: Test terminated by assertion
11083 23:36:58.929967 # # FAIL rtc.alarm_alm_set_minute
11084 23:36:58.933475 # not ok 7 rtc.alarm_alm_set_minute
11085 23:36:58.937168 # # RUN rtc.alarm_wkalm_set_minute ...
11086 23:36:58.943730 # # rtctest.c:360:alarm_wkalm_set_minute:Alarm time now set to 03/12/2023 23:35:00.
11087 23:37:13.902057 # # OK rtc.alarm_wkalm_set_minute
11088 23:37:13.905699 # ok 8 rtc.alarm_wkalm_set_minute
11089 23:37:13.908746 # # FAILED: 6 / 8 tests passed.
11090 23:37:13.912357 # # Totals: pass:6 fail:2 xfail:0 xpass:0 skip:0 error:0
11091 23:37:13.915196 not ok 1 selftests: rtc: rtctest # exit=1
11092 23:37:14.514599 rtc_rtctest_rtc_date_read pass
11093 23:37:14.517687 rtc_rtctest_rtc_date_read_loop pass
11094 23:37:14.521106 rtc_rtctest_rtc_uie_read pass
11095 23:37:14.524318 rtc_rtctest_rtc_uie_select pass
11096 23:37:14.528349 rtc_rtctest_rtc_alarm_alm_set fail
11097 23:37:14.530614 rtc_rtctest_rtc_alarm_wkalm_set pass
11098 23:37:14.534489 rtc_rtctest_rtc_alarm_alm_set_minute fail
11099 23:37:14.537558 rtc_rtctest_rtc_alarm_wkalm_set_minute pass
11100 23:37:14.540372 rtc_rtctest fail
11101 23:37:14.543325 + ../../utils/send-to-lava.sh ./output/result.txt
11102 23:37:14.607631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-rtc RESULT=pass>
11103 23:37:14.608436 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-rtc RESULT=pass
11105 23:37:14.655679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_date_read RESULT=pass>
11106 23:37:14.656375 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_date_read RESULT=pass
11108 23:37:14.706207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_date_read_loop RESULT=pass>
11109 23:37:14.706902 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_date_read_loop RESULT=pass
11111 23:37:14.747577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_uie_read RESULT=pass>
11112 23:37:14.748356 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_uie_read RESULT=pass
11114 23:37:14.795624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_uie_select RESULT=pass>
11115 23:37:14.796441 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_uie_select RESULT=pass
11117 23:37:14.845020 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set RESULT=fail
11119 23:37:14.847892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set RESULT=fail>
11120 23:37:14.898530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set RESULT=pass>
11121 23:37:14.899234 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set RESULT=pass
11123 23:37:14.948548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set_minute RESULT=fail>
11124 23:37:14.949249 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set_minute RESULT=fail
11126 23:37:14.993620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set_minute RESULT=pass>
11127 23:37:14.994323 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set_minute RESULT=pass
11129 23:37:15.041095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest RESULT=fail>
11130 23:37:15.041646 + set +x
11131 23:37:15.042259 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest RESULT=fail
11133 23:37:15.047611 <LAVA_SIGNAL_ENDRUN 1_kselftest-rtc 12172440_1.6.2.3.5>
11134 23:37:15.048289 Received signal: <ENDRUN> 1_kselftest-rtc 12172440_1.6.2.3.5
11135 23:37:15.048666 Ending use of test pattern.
11136 23:37:15.048990 Ending test lava.1_kselftest-rtc (12172440_1.6.2.3.5), duration 63.06
11138 23:37:15.050112 ok: lava_test_shell seems to have completed
11139 23:37:15.050794 rtc_rtctest: fail
rtc_rtctest_rtc_alarm_alm_set: fail
rtc_rtctest_rtc_alarm_alm_set_minute: fail
rtc_rtctest_rtc_alarm_wkalm_set: pass
rtc_rtctest_rtc_alarm_wkalm_set_minute: pass
rtc_rtctest_rtc_date_read: pass
rtc_rtctest_rtc_date_read_loop: pass
rtc_rtctest_rtc_uie_read: pass
rtc_rtctest_rtc_uie_select: pass
shardfile-rtc: pass
11140 23:37:15.051238 end: 3.1 lava-test-shell (duration 00:01:04) [common]
11141 23:37:15.051662 end: 3 lava-test-retry (duration 00:01:04) [common]
11142 23:37:15.052100 start: 4 finalize (timeout 00:06:50) [common]
11143 23:37:15.052559 start: 4.1 power-off (timeout 00:00:30) [common]
11144 23:37:15.053557 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=off'
11145 23:37:15.174879 >> Command sent successfully.
11146 23:37:15.179409 Returned 0 in 0 seconds
11147 23:37:15.280351 end: 4.1 power-off (duration 00:00:00) [common]
11149 23:37:15.282084 start: 4.2 read-feedback (timeout 00:06:50) [common]
11151 23:37:15.284284 Listened to connection for namespace 'common' for up to 1s
11152 23:37:16.284014 Finalising connection for namespace 'common'
11153 23:37:16.284707 Disconnecting from shell: Finalise
11154 23:37:16.285391 / #
11155 23:37:16.386523 end: 4.2 read-feedback (duration 00:00:01) [common]
11156 23:37:16.387248 end: 4 finalize (duration 00:00:01) [common]
11157 23:37:16.387837 Cleaning after the job
11158 23:37:16.388376 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12172440/tftp-deploy-jip4knts/ramdisk
11159 23:37:16.402183 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12172440/tftp-deploy-jip4knts/kernel
11160 23:37:16.436178 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12172440/tftp-deploy-jip4knts/dtb
11161 23:37:16.436470 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12172440/tftp-deploy-jip4knts/nfsrootfs
11162 23:37:16.530123 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12172440/tftp-deploy-jip4knts/modules
11163 23:37:16.537299 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12172440
11164 23:37:17.179964 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12172440
11165 23:37:17.180149 Job finished correctly