Boot log: mt8192-asurada-spherion-r0
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 18
- Kernel Errors: 32
- Errors: 1
1 22:57:02.556005 lava-dispatcher, installed at version: 2023.10
2 22:57:02.556231 start: 0 validate
3 22:57:02.556367 Start time: 2023-12-03 22:57:02.556360+00:00 (UTC)
4 22:57:02.556545 Using caching service: 'http://localhost/cache/?uri=%s'
5 22:57:02.556683 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-v4l2%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 22:57:02.830104 Using caching service: 'http://localhost/cache/?uri=%s'
7 22:57:02.830278 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.64-cip10-rt5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 22:57:03.097124 Using caching service: 'http://localhost/cache/?uri=%s'
9 22:57:03.098018 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.64-cip10-rt5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 22:57:18.569679 Using caching service: 'http://localhost/cache/?uri=%s'
11 22:57:18.570412 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.64-cip10-rt5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 22:57:19.096433 validate duration: 16.54
14 22:57:19.096709 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 22:57:19.096807 start: 1.1 download-retry (timeout 00:10:00) [common]
16 22:57:19.096897 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 22:57:19.097024 Not decompressing ramdisk as can be used compressed.
18 22:57:19.097113 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-v4l2/20230623.0/arm64/rootfs.cpio.gz
19 22:57:19.097181 saving as /var/lib/lava/dispatcher/tmp/12172390/tftp-deploy-rtufekp4/ramdisk/rootfs.cpio.gz
20 22:57:19.097246 total size: 26246609 (25 MB)
21 22:57:22.697408 progress 0 % (0 MB)
22 22:57:22.707846 progress 5 % (1 MB)
23 22:57:22.714732 progress 10 % (2 MB)
24 22:57:22.721577 progress 15 % (3 MB)
25 22:57:22.728388 progress 20 % (5 MB)
26 22:57:22.735257 progress 25 % (6 MB)
27 22:57:22.742164 progress 30 % (7 MB)
28 22:57:22.749000 progress 35 % (8 MB)
29 22:57:22.755877 progress 40 % (10 MB)
30 22:57:22.762726 progress 45 % (11 MB)
31 22:57:22.769554 progress 50 % (12 MB)
32 22:57:22.776564 progress 55 % (13 MB)
33 22:57:22.783488 progress 60 % (15 MB)
34 22:57:22.790514 progress 65 % (16 MB)
35 22:57:22.797471 progress 70 % (17 MB)
36 22:57:22.804449 progress 75 % (18 MB)
37 22:57:22.811695 progress 80 % (20 MB)
38 22:57:22.818945 progress 85 % (21 MB)
39 22:57:22.825784 progress 90 % (22 MB)
40 22:57:22.832500 progress 95 % (23 MB)
41 22:57:22.839491 progress 100 % (25 MB)
42 22:57:22.839815 25 MB downloaded in 3.74 s (6.69 MB/s)
43 22:57:22.839980 end: 1.1.1 http-download (duration 00:00:04) [common]
45 22:57:22.840227 end: 1.1 download-retry (duration 00:00:04) [common]
46 22:57:22.840315 start: 1.2 download-retry (timeout 00:09:56) [common]
47 22:57:22.840402 start: 1.2.1 http-download (timeout 00:09:56) [common]
48 22:57:22.840632 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.64-cip10-rt5/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 22:57:22.840707 saving as /var/lib/lava/dispatcher/tmp/12172390/tftp-deploy-rtufekp4/kernel/Image
50 22:57:22.840770 total size: 49172992 (46 MB)
51 22:57:22.840833 No compression specified
52 22:57:22.841981 progress 0 % (0 MB)
53 22:57:22.854949 progress 5 % (2 MB)
54 22:57:22.867776 progress 10 % (4 MB)
55 22:57:22.880774 progress 15 % (7 MB)
56 22:57:22.893714 progress 20 % (9 MB)
57 22:57:22.906643 progress 25 % (11 MB)
58 22:57:22.919722 progress 30 % (14 MB)
59 22:57:22.932738 progress 35 % (16 MB)
60 22:57:22.945837 progress 40 % (18 MB)
61 22:57:22.958888 progress 45 % (21 MB)
62 22:57:22.971723 progress 50 % (23 MB)
63 22:57:22.984586 progress 55 % (25 MB)
64 22:57:22.997460 progress 60 % (28 MB)
65 22:57:23.010199 progress 65 % (30 MB)
66 22:57:23.023085 progress 70 % (32 MB)
67 22:57:23.036077 progress 75 % (35 MB)
68 22:57:23.049093 progress 80 % (37 MB)
69 22:57:23.062130 progress 85 % (39 MB)
70 22:57:23.075323 progress 90 % (42 MB)
71 22:57:23.088199 progress 95 % (44 MB)
72 22:57:23.100799 progress 100 % (46 MB)
73 22:57:23.101040 46 MB downloaded in 0.26 s (180.18 MB/s)
74 22:57:23.101198 end: 1.2.1 http-download (duration 00:00:00) [common]
76 22:57:23.101436 end: 1.2 download-retry (duration 00:00:00) [common]
77 22:57:23.101529 start: 1.3 download-retry (timeout 00:09:56) [common]
78 22:57:23.101659 start: 1.3.1 http-download (timeout 00:09:56) [common]
79 22:57:23.101810 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.64-cip10-rt5/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 22:57:23.101882 saving as /var/lib/lava/dispatcher/tmp/12172390/tftp-deploy-rtufekp4/dtb/mt8192-asurada-spherion-r0.dtb
81 22:57:23.101946 total size: 47278 (0 MB)
82 22:57:23.102009 No compression specified
83 22:57:23.103155 progress 69 % (0 MB)
84 22:57:23.103440 progress 100 % (0 MB)
85 22:57:23.103598 0 MB downloaded in 0.00 s (27.34 MB/s)
86 22:57:23.103723 end: 1.3.1 http-download (duration 00:00:00) [common]
88 22:57:23.103948 end: 1.3 download-retry (duration 00:00:00) [common]
89 22:57:23.104034 start: 1.4 download-retry (timeout 00:09:56) [common]
90 22:57:23.104117 start: 1.4.1 http-download (timeout 00:09:56) [common]
91 22:57:23.104261 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.64-cip10-rt5/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 22:57:23.104344 saving as /var/lib/lava/dispatcher/tmp/12172390/tftp-deploy-rtufekp4/modules/modules.tar
93 22:57:23.104406 total size: 8614132 (8 MB)
94 22:57:23.104468 Using unxz to decompress xz
95 22:57:23.108665 progress 0 % (0 MB)
96 22:57:23.129611 progress 5 % (0 MB)
97 22:57:23.153843 progress 10 % (0 MB)
98 22:57:23.177688 progress 15 % (1 MB)
99 22:57:23.203165 progress 20 % (1 MB)
100 22:57:23.228771 progress 25 % (2 MB)
101 22:57:23.256081 progress 30 % (2 MB)
102 22:57:23.282593 progress 35 % (2 MB)
103 22:57:23.307105 progress 40 % (3 MB)
104 22:57:23.332951 progress 45 % (3 MB)
105 22:57:23.360214 progress 50 % (4 MB)
106 22:57:23.386395 progress 55 % (4 MB)
107 22:57:23.412956 progress 60 % (4 MB)
108 22:57:23.440144 progress 65 % (5 MB)
109 22:57:23.468356 progress 70 % (5 MB)
110 22:57:23.491886 progress 75 % (6 MB)
111 22:57:23.520093 progress 80 % (6 MB)
112 22:57:23.547352 progress 85 % (7 MB)
113 22:57:23.574452 progress 90 % (7 MB)
114 22:57:23.605928 progress 95 % (7 MB)
115 22:57:23.634070 progress 100 % (8 MB)
116 22:57:23.640603 8 MB downloaded in 0.54 s (15.32 MB/s)
117 22:57:23.640873 end: 1.4.1 http-download (duration 00:00:01) [common]
119 22:57:23.641225 end: 1.4 download-retry (duration 00:00:01) [common]
120 22:57:23.641326 start: 1.5 prepare-tftp-overlay (timeout 00:09:55) [common]
121 22:57:23.641425 start: 1.5.1 extract-nfsrootfs (timeout 00:09:55) [common]
122 22:57:23.641506 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 22:57:23.641639 start: 1.5.2 lava-overlay (timeout 00:09:55) [common]
124 22:57:23.641913 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12172390/lava-overlay-ta_8mglt
125 22:57:23.642083 makedir: /var/lib/lava/dispatcher/tmp/12172390/lava-overlay-ta_8mglt/lava-12172390/bin
126 22:57:23.642227 makedir: /var/lib/lava/dispatcher/tmp/12172390/lava-overlay-ta_8mglt/lava-12172390/tests
127 22:57:23.642360 makedir: /var/lib/lava/dispatcher/tmp/12172390/lava-overlay-ta_8mglt/lava-12172390/results
128 22:57:23.642510 Creating /var/lib/lava/dispatcher/tmp/12172390/lava-overlay-ta_8mglt/lava-12172390/bin/lava-add-keys
129 22:57:23.642717 Creating /var/lib/lava/dispatcher/tmp/12172390/lava-overlay-ta_8mglt/lava-12172390/bin/lava-add-sources
130 22:57:23.642889 Creating /var/lib/lava/dispatcher/tmp/12172390/lava-overlay-ta_8mglt/lava-12172390/bin/lava-background-process-start
131 22:57:23.643060 Creating /var/lib/lava/dispatcher/tmp/12172390/lava-overlay-ta_8mglt/lava-12172390/bin/lava-background-process-stop
132 22:57:23.643223 Creating /var/lib/lava/dispatcher/tmp/12172390/lava-overlay-ta_8mglt/lava-12172390/bin/lava-common-functions
133 22:57:23.643386 Creating /var/lib/lava/dispatcher/tmp/12172390/lava-overlay-ta_8mglt/lava-12172390/bin/lava-echo-ipv4
134 22:57:23.643551 Creating /var/lib/lava/dispatcher/tmp/12172390/lava-overlay-ta_8mglt/lava-12172390/bin/lava-install-packages
135 22:57:23.643712 Creating /var/lib/lava/dispatcher/tmp/12172390/lava-overlay-ta_8mglt/lava-12172390/bin/lava-installed-packages
136 22:57:23.643875 Creating /var/lib/lava/dispatcher/tmp/12172390/lava-overlay-ta_8mglt/lava-12172390/bin/lava-os-build
137 22:57:23.644037 Creating /var/lib/lava/dispatcher/tmp/12172390/lava-overlay-ta_8mglt/lava-12172390/bin/lava-probe-channel
138 22:57:23.644200 Creating /var/lib/lava/dispatcher/tmp/12172390/lava-overlay-ta_8mglt/lava-12172390/bin/lava-probe-ip
139 22:57:23.644386 Creating /var/lib/lava/dispatcher/tmp/12172390/lava-overlay-ta_8mglt/lava-12172390/bin/lava-target-ip
140 22:57:23.644542 Creating /var/lib/lava/dispatcher/tmp/12172390/lava-overlay-ta_8mglt/lava-12172390/bin/lava-target-mac
141 22:57:23.644682 Creating /var/lib/lava/dispatcher/tmp/12172390/lava-overlay-ta_8mglt/lava-12172390/bin/lava-target-storage
142 22:57:23.644847 Creating /var/lib/lava/dispatcher/tmp/12172390/lava-overlay-ta_8mglt/lava-12172390/bin/lava-test-case
143 22:57:23.645019 Creating /var/lib/lava/dispatcher/tmp/12172390/lava-overlay-ta_8mglt/lava-12172390/bin/lava-test-event
144 22:57:23.645153 Creating /var/lib/lava/dispatcher/tmp/12172390/lava-overlay-ta_8mglt/lava-12172390/bin/lava-test-feedback
145 22:57:23.645282 Creating /var/lib/lava/dispatcher/tmp/12172390/lava-overlay-ta_8mglt/lava-12172390/bin/lava-test-raise
146 22:57:23.645413 Creating /var/lib/lava/dispatcher/tmp/12172390/lava-overlay-ta_8mglt/lava-12172390/bin/lava-test-reference
147 22:57:23.645569 Creating /var/lib/lava/dispatcher/tmp/12172390/lava-overlay-ta_8mglt/lava-12172390/bin/lava-test-runner
148 22:57:23.645744 Creating /var/lib/lava/dispatcher/tmp/12172390/lava-overlay-ta_8mglt/lava-12172390/bin/lava-test-set
149 22:57:23.645875 Creating /var/lib/lava/dispatcher/tmp/12172390/lava-overlay-ta_8mglt/lava-12172390/bin/lava-test-shell
150 22:57:23.646059 Updating /var/lib/lava/dispatcher/tmp/12172390/lava-overlay-ta_8mglt/lava-12172390/bin/lava-install-packages (oe)
151 22:57:23.646243 Updating /var/lib/lava/dispatcher/tmp/12172390/lava-overlay-ta_8mglt/lava-12172390/bin/lava-installed-packages (oe)
152 22:57:23.646377 Creating /var/lib/lava/dispatcher/tmp/12172390/lava-overlay-ta_8mglt/lava-12172390/environment
153 22:57:23.646508 LAVA metadata
154 22:57:23.646612 - LAVA_JOB_ID=12172390
155 22:57:23.646709 - LAVA_DISPATCHER_IP=192.168.201.1
156 22:57:23.646850 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:55) [common]
157 22:57:23.646946 skipped lava-vland-overlay
158 22:57:23.647052 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 22:57:23.647178 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:55) [common]
160 22:57:23.647277 skipped lava-multinode-overlay
161 22:57:23.647382 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 22:57:23.647497 start: 1.5.2.3 test-definition (timeout 00:09:55) [common]
163 22:57:23.647614 Loading test definitions
164 22:57:23.647746 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:55) [common]
165 22:57:23.647847 Using /lava-12172390 at stage 0
166 22:57:23.648168 uuid=12172390_1.5.2.3.1 testdef=None
167 22:57:23.648257 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 22:57:23.648346 start: 1.5.2.3.2 test-overlay (timeout 00:09:55) [common]
169 22:57:23.649035 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 22:57:23.649258 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:55) [common]
172 22:57:23.649938 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 22:57:23.650175 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:55) [common]
175 22:57:23.650782 runner path: /var/lib/lava/dispatcher/tmp/12172390/lava-overlay-ta_8mglt/lava-12172390/0/tests/0_v4l2-compliance-uvc test_uuid 12172390_1.5.2.3.1
176 22:57:23.650941 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 22:57:23.651151 Creating lava-test-runner.conf files
179 22:57:23.651216 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12172390/lava-overlay-ta_8mglt/lava-12172390/0 for stage 0
180 22:57:23.651307 - 0_v4l2-compliance-uvc
181 22:57:23.651404 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 22:57:23.651490 start: 1.5.2.4 compress-overlay (timeout 00:09:55) [common]
183 22:57:23.658314 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 22:57:23.658426 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:55) [common]
185 22:57:23.658515 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 22:57:23.658601 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 22:57:23.658692 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:55) [common]
188 22:57:24.403471 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 22:57:24.403872 start: 1.5.4 extract-modules (timeout 00:09:55) [common]
190 22:57:24.404016 extracting modules file /var/lib/lava/dispatcher/tmp/12172390/tftp-deploy-rtufekp4/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12172390/extract-overlay-ramdisk-5i0358di/ramdisk
191 22:57:24.649334 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 22:57:24.649514 start: 1.5.5 apply-overlay-tftp (timeout 00:09:54) [common]
193 22:57:24.649658 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12172390/compress-overlay-lt_s96s5/overlay-1.5.2.4.tar.gz to ramdisk
194 22:57:24.649735 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12172390/compress-overlay-lt_s96s5/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12172390/extract-overlay-ramdisk-5i0358di/ramdisk
195 22:57:24.656584 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 22:57:24.656721 start: 1.5.6 configure-preseed-file (timeout 00:09:54) [common]
197 22:57:24.656817 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 22:57:24.656908 start: 1.5.7 compress-ramdisk (timeout 00:09:54) [common]
199 22:57:24.656990 Building ramdisk /var/lib/lava/dispatcher/tmp/12172390/extract-overlay-ramdisk-5i0358di/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12172390/extract-overlay-ramdisk-5i0358di/ramdisk
200 22:57:25.319556 >> 228445 blocks
201 22:57:29.348448 rename /var/lib/lava/dispatcher/tmp/12172390/extract-overlay-ramdisk-5i0358di/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12172390/tftp-deploy-rtufekp4/ramdisk/ramdisk.cpio.gz
202 22:57:29.348973 end: 1.5.7 compress-ramdisk (duration 00:00:05) [common]
203 22:57:29.349111 start: 1.5.8 prepare-kernel (timeout 00:09:50) [common]
204 22:57:29.349213 start: 1.5.8.1 prepare-fit (timeout 00:09:50) [common]
205 22:57:29.349319 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12172390/tftp-deploy-rtufekp4/kernel/Image'
206 22:57:42.525897 Returned 0 in 13 seconds
207 22:57:42.626657 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12172390/tftp-deploy-rtufekp4/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12172390/tftp-deploy-rtufekp4/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12172390/tftp-deploy-rtufekp4/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12172390/tftp-deploy-rtufekp4/kernel/image.itb
208 22:57:43.244666 output: FIT description: Kernel Image image with one or more FDT blobs
209 22:57:43.245072 output: Created: Sun Dec 3 22:57:43 2023
210 22:57:43.245156 output: Image 0 (kernel-1)
211 22:57:43.245229 output: Description:
212 22:57:43.245298 output: Created: Sun Dec 3 22:57:43 2023
213 22:57:43.245364 output: Type: Kernel Image
214 22:57:43.245427 output: Compression: lzma compressed
215 22:57:43.245488 output: Data Size: 11049348 Bytes = 10790.38 KiB = 10.54 MiB
216 22:57:43.245550 output: Architecture: AArch64
217 22:57:43.245671 output: OS: Linux
218 22:57:43.245741 output: Load Address: 0x00000000
219 22:57:43.245825 output: Entry Point: 0x00000000
220 22:57:43.245908 output: Hash algo: crc32
221 22:57:43.245966 output: Hash value: c85ea8f0
222 22:57:43.246027 output: Image 1 (fdt-1)
223 22:57:43.246083 output: Description: mt8192-asurada-spherion-r0
224 22:57:43.246138 output: Created: Sun Dec 3 22:57:43 2023
225 22:57:43.246193 output: Type: Flat Device Tree
226 22:57:43.246248 output: Compression: uncompressed
227 22:57:43.246303 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
228 22:57:43.246358 output: Architecture: AArch64
229 22:57:43.246412 output: Hash algo: crc32
230 22:57:43.246467 output: Hash value: cc4352de
231 22:57:43.246521 output: Image 2 (ramdisk-1)
232 22:57:43.246575 output: Description: unavailable
233 22:57:43.246629 output: Created: Sun Dec 3 22:57:43 2023
234 22:57:43.246683 output: Type: RAMDisk Image
235 22:57:43.246737 output: Compression: Unknown Compression
236 22:57:43.246792 output: Data Size: 39354878 Bytes = 38432.50 KiB = 37.53 MiB
237 22:57:43.246846 output: Architecture: AArch64
238 22:57:43.246900 output: OS: Linux
239 22:57:43.246954 output: Load Address: unavailable
240 22:57:43.247008 output: Entry Point: unavailable
241 22:57:43.247062 output: Hash algo: crc32
242 22:57:43.247115 output: Hash value: 058f0820
243 22:57:43.247169 output: Default Configuration: 'conf-1'
244 22:57:43.247223 output: Configuration 0 (conf-1)
245 22:57:43.247277 output: Description: mt8192-asurada-spherion-r0
246 22:57:43.247330 output: Kernel: kernel-1
247 22:57:43.247384 output: Init Ramdisk: ramdisk-1
248 22:57:43.247438 output: FDT: fdt-1
249 22:57:43.247491 output: Loadables: kernel-1
250 22:57:43.247544 output:
251 22:57:43.247749 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
252 22:57:43.247853 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
253 22:57:43.247960 end: 1.5 prepare-tftp-overlay (duration 00:00:20) [common]
254 22:57:43.248056 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:36) [common]
255 22:57:43.248137 No LXC device requested
256 22:57:43.248222 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 22:57:43.248306 start: 1.7 deploy-device-env (timeout 00:09:36) [common]
258 22:57:43.248383 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 22:57:43.248456 Checking files for TFTP limit of 4294967296 bytes.
260 22:57:43.248975 end: 1 tftp-deploy (duration 00:00:24) [common]
261 22:57:43.249084 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 22:57:43.249173 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 22:57:43.249294 substitutions:
264 22:57:43.249364 - {DTB}: 12172390/tftp-deploy-rtufekp4/dtb/mt8192-asurada-spherion-r0.dtb
265 22:57:43.249430 - {INITRD}: 12172390/tftp-deploy-rtufekp4/ramdisk/ramdisk.cpio.gz
266 22:57:43.249490 - {KERNEL}: 12172390/tftp-deploy-rtufekp4/kernel/Image
267 22:57:43.249548 - {LAVA_MAC}: None
268 22:57:43.249655 - {PRESEED_CONFIG}: None
269 22:57:43.249713 - {PRESEED_LOCAL}: None
270 22:57:43.249769 - {RAMDISK}: 12172390/tftp-deploy-rtufekp4/ramdisk/ramdisk.cpio.gz
271 22:57:43.249825 - {ROOT_PART}: None
272 22:57:43.249880 - {ROOT}: None
273 22:57:43.249935 - {SERVER_IP}: 192.168.201.1
274 22:57:43.249989 - {TEE}: None
275 22:57:43.250044 Parsed boot commands:
276 22:57:43.250098 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 22:57:43.250286 Parsed boot commands: tftpboot 192.168.201.1 12172390/tftp-deploy-rtufekp4/kernel/image.itb 12172390/tftp-deploy-rtufekp4/kernel/cmdline
278 22:57:43.250377 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 22:57:43.250463 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 22:57:43.250562 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 22:57:43.250650 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 22:57:43.250721 Not connected, no need to disconnect.
283 22:57:43.250795 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 22:57:43.250876 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 22:57:43.250941 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-0'
286 22:57:43.255121 Setting prompt string to ['lava-test: # ']
287 22:57:43.255525 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 22:57:43.255659 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 22:57:43.255780 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 22:57:43.255905 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 22:57:43.256181 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=reboot'
292 22:57:48.392841 >> Command sent successfully.
293 22:57:48.395259 Returned 0 in 5 seconds
294 22:57:48.495654 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 22:57:48.495996 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 22:57:48.496100 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 22:57:48.496192 Setting prompt string to 'Starting depthcharge on Spherion...'
299 22:57:48.496261 Changing prompt to 'Starting depthcharge on Spherion...'
300 22:57:48.496331 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 22:57:48.496600 [Enter `^Ec?' for help]
302 22:57:48.667871
303 22:57:48.668025
304 22:57:48.668102 F0: 102B 0000
305 22:57:48.668172
306 22:57:48.668235 F3: 1001 0000 [0200]
307 22:57:48.671677
308 22:57:48.671765 F3: 1001 0000
309 22:57:48.671834
310 22:57:48.671899 F7: 102D 0000
311 22:57:48.671960
312 22:57:48.675031 F1: 0000 0000
313 22:57:48.675119
314 22:57:48.675187 V0: 0000 0000 [0001]
315 22:57:48.675254
316 22:57:48.677717 00: 0007 8000
317 22:57:48.677807
318 22:57:48.677874 01: 0000 0000
319 22:57:48.677939
320 22:57:48.681419 BP: 0C00 0209 [0000]
321 22:57:48.681504
322 22:57:48.681573 G0: 1182 0000
323 22:57:48.681678
324 22:57:48.685035 EC: 0000 0021 [4000]
325 22:57:48.685136
326 22:57:48.685204 S7: 0000 0000 [0000]
327 22:57:48.685267
328 22:57:48.688607 CC: 0000 0000 [0001]
329 22:57:48.688693
330 22:57:48.688761 T0: 0000 0040 [010F]
331 22:57:48.688825
332 22:57:48.688885 Jump to BL
333 22:57:48.691754
334 22:57:48.715051
335 22:57:48.715184
336 22:57:48.715255
337 22:57:48.722521 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 22:57:48.726022 ARM64: Exception handlers installed.
339 22:57:48.729759 ARM64: Testing exception
340 22:57:48.733520 ARM64: Done test exception
341 22:57:48.740165 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 22:57:48.749987 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 22:57:48.756683 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 22:57:48.767675 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 22:57:48.773768 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 22:57:48.780796 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 22:57:48.791925 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 22:57:48.798363 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 22:57:48.818235 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 22:57:48.821517 WDT: Last reset was cold boot
351 22:57:48.824609 SPI1(PAD0) initialized at 2873684 Hz
352 22:57:48.827871 SPI5(PAD0) initialized at 992727 Hz
353 22:57:48.831387 VBOOT: Loading verstage.
354 22:57:48.838181 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 22:57:48.842091 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 22:57:48.845602 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 22:57:48.848468 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 22:57:48.855308 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 22:57:48.862384 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 22:57:48.873057 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
361 22:57:48.873240
362 22:57:48.873329
363 22:57:48.883335 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 22:57:48.886947 ARM64: Exception handlers installed.
365 22:57:48.889720 ARM64: Testing exception
366 22:57:48.889806 ARM64: Done test exception
367 22:57:48.896537 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 22:57:48.900023 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 22:57:48.913952 Probing TPM: . done!
370 22:57:48.914073 TPM ready after 0 ms
371 22:57:48.921007 Connected to device vid:did:rid of 1ae0:0028:00
372 22:57:48.927614 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
373 22:57:48.988992 Initialized TPM device CR50 revision 0
374 22:57:48.998708 tlcl_send_startup: Startup return code is 0
375 22:57:48.998855 TPM: setup succeeded
376 22:57:49.010071 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 22:57:49.019244 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 22:57:49.032699 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 22:57:49.040279 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 22:57:49.043756 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 22:57:49.047269 in-header: 03 07 00 00 08 00 00 00
382 22:57:49.051332 in-data: aa e4 47 04 13 02 00 00
383 22:57:49.055089 Chrome EC: UHEPI supported
384 22:57:49.058571 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 22:57:49.062621 in-header: 03 95 00 00 08 00 00 00
386 22:57:49.066166 in-data: 18 20 20 08 00 00 00 00
387 22:57:49.066252 Phase 1
388 22:57:49.070032 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 22:57:49.077238 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 22:57:49.084704 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 22:57:49.084812 Recovery requested (1009000e)
392 22:57:49.095322 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 22:57:49.100691 tlcl_extend: response is 0
394 22:57:49.110117 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 22:57:49.115886 tlcl_extend: response is 0
396 22:57:49.122950 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 22:57:49.142372 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
398 22:57:49.149318 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 22:57:49.149463
400 22:57:49.149562
401 22:57:49.159051 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 22:57:49.162351 ARM64: Exception handlers installed.
403 22:57:49.166005 ARM64: Testing exception
404 22:57:49.166118 ARM64: Done test exception
405 22:57:49.187907 pmic_efuse_setting: Set efuses in 11 msecs
406 22:57:49.191265 pmwrap_interface_init: Select PMIF_VLD_RDY
407 22:57:49.197922 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 22:57:49.201374 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 22:57:49.208866 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 22:57:49.212405 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 22:57:49.216105 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 22:57:49.220493 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 22:57:49.227359 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 22:57:49.230860 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 22:57:49.234626 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 22:57:49.242192 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 22:57:49.245694 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 22:57:49.249972 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 22:57:49.253539 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 22:57:49.260552 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 22:57:49.264984 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 22:57:49.271547 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 22:57:49.279017 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 22:57:49.282858 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 22:57:49.290167 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 22:57:49.294225 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 22:57:49.301510 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 22:57:49.305533 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 22:57:49.312963 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 22:57:49.317131 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 22:57:49.320328 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 22:57:49.327738 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 22:57:49.331272 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 22:57:49.339003 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 22:57:49.342456 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 22:57:49.346689 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 22:57:49.353507 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 22:57:49.357242 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 22:57:49.361205 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 22:57:49.368334 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 22:57:49.371955 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 22:57:49.375713 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 22:57:49.383418 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 22:57:49.386968 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 22:57:49.390798 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 22:57:49.394044 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 22:57:49.401670 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 22:57:49.405526 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 22:57:49.408952 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 22:57:49.412739 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 22:57:49.416512 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 22:57:49.424084 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 22:57:49.427704 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 22:57:49.431648 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 22:57:49.435431 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 22:57:49.438797 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 22:57:49.442906 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 22:57:49.449878 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 22:57:49.457940 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 22:57:49.465039 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 22:57:49.472344 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 22:57:49.480124 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 22:57:49.483935 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 22:57:49.491236 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 22:57:49.495811 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 22:57:49.502591 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x0
467 22:57:49.505760 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 22:57:49.509890 [RTC]rtc_osc_init,62: osc32con val = 0xde70
469 22:57:49.516585 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 22:57:49.525658 [RTC]rtc_get_frequency_meter,154: input=15, output=760
471 22:57:49.535123 [RTC]rtc_get_frequency_meter,154: input=23, output=941
472 22:57:49.544673 [RTC]rtc_get_frequency_meter,154: input=19, output=849
473 22:57:49.553946 [RTC]rtc_get_frequency_meter,154: input=17, output=805
474 22:57:49.563349 [RTC]rtc_get_frequency_meter,154: input=16, output=782
475 22:57:49.573499 [RTC]rtc_get_frequency_meter,154: input=16, output=783
476 22:57:49.583182 [RTC]rtc_get_frequency_meter,154: input=17, output=805
477 22:57:49.587064 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
478 22:57:49.591042 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
479 22:57:49.594657 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 22:57:49.598829 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
481 22:57:49.606474 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 22:57:49.610186 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
483 22:57:49.610311 ADC[4]: Raw value=906573 ID=7
484 22:57:49.613420 ADC[3]: Raw value=213810 ID=1
485 22:57:49.617840 RAM Code: 0x71
486 22:57:49.621456 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 22:57:49.624885 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 22:57:49.632505 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
489 22:57:49.640623 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
490 22:57:49.644794 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 22:57:49.648031 in-header: 03 07 00 00 08 00 00 00
492 22:57:49.651450 in-data: aa e4 47 04 13 02 00 00
493 22:57:49.655229 Chrome EC: UHEPI supported
494 22:57:49.658361 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 22:57:49.662376 in-header: 03 95 00 00 08 00 00 00
496 22:57:49.666092 in-data: 18 20 20 08 00 00 00 00
497 22:57:49.669892 MRC: failed to locate region type 0.
498 22:57:49.677041 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 22:57:49.681152 DRAM-K: Running full calibration
500 22:57:49.684598 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
501 22:57:49.688129 header.status = 0x0
502 22:57:49.691886 header.version = 0x6 (expected: 0x6)
503 22:57:49.695633 header.size = 0xd00 (expected: 0xd00)
504 22:57:49.695745 header.flags = 0x0
505 22:57:49.702776 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 22:57:49.721048 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
507 22:57:49.727771 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 22:57:49.731324 dram_init: ddr_geometry: 2
509 22:57:49.731433 [EMI] MDL number = 2
510 22:57:49.735390 [EMI] Get MDL freq = 0
511 22:57:49.735499 dram_init: ddr_type: 0
512 22:57:49.739100 is_discrete_lpddr4: 1
513 22:57:49.742701 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 22:57:49.742808
515 22:57:49.742900
516 22:57:49.745825 [Bian_co] ETT version 0.0.0.1
517 22:57:49.749829 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
518 22:57:49.749933
519 22:57:49.754018 dramc_set_vcore_voltage set vcore to 650000
520 22:57:49.754141 Read voltage for 800, 4
521 22:57:49.758156 Vio18 = 0
522 22:57:49.758263 Vcore = 650000
523 22:57:49.758358 Vdram = 0
524 22:57:49.758449 Vddq = 0
525 22:57:49.761542 Vmddr = 0
526 22:57:49.761655 dram_init: config_dvfs: 1
527 22:57:49.769296 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 22:57:49.772860 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 22:57:49.776546 [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9
530 22:57:49.780313 freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9
531 22:57:49.784229 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
532 22:57:49.787787 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
533 22:57:49.791221 MEM_TYPE=3, freq_sel=18
534 22:57:49.794462 sv_algorithm_assistance_LP4_1600
535 22:57:49.798068 ============ PULL DRAM RESETB DOWN ============
536 22:57:49.800929 ========== PULL DRAM RESETB DOWN end =========
537 22:57:49.804651 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 22:57:49.807743 ===================================
539 22:57:49.811381 LPDDR4 DRAM CONFIGURATION
540 22:57:49.815236 ===================================
541 22:57:49.818786 EX_ROW_EN[0] = 0x0
542 22:57:49.818898 EX_ROW_EN[1] = 0x0
543 22:57:49.822554 LP4Y_EN = 0x0
544 22:57:49.822665 WORK_FSP = 0x0
545 22:57:49.822760 WL = 0x2
546 22:57:49.826520 RL = 0x2
547 22:57:49.826625 BL = 0x2
548 22:57:49.830011 RPST = 0x0
549 22:57:49.830117 RD_PRE = 0x0
550 22:57:49.833879 WR_PRE = 0x1
551 22:57:49.833985 WR_PST = 0x0
552 22:57:49.837314 DBI_WR = 0x0
553 22:57:49.837419 DBI_RD = 0x0
554 22:57:49.840287 OTF = 0x1
555 22:57:49.844039 ===================================
556 22:57:49.846927 ===================================
557 22:57:49.847035 ANA top config
558 22:57:49.850217 ===================================
559 22:57:49.853709 DLL_ASYNC_EN = 0
560 22:57:49.857154 ALL_SLAVE_EN = 1
561 22:57:49.857262 NEW_RANK_MODE = 1
562 22:57:49.860451 DLL_IDLE_MODE = 1
563 22:57:49.863848 LP45_APHY_COMB_EN = 1
564 22:57:49.867257 TX_ODT_DIS = 1
565 22:57:49.870821 NEW_8X_MODE = 1
566 22:57:49.870928 ===================================
567 22:57:49.874589 ===================================
568 22:57:49.878083 data_rate = 1600
569 22:57:49.881093 CKR = 1
570 22:57:49.884788 DQ_P2S_RATIO = 8
571 22:57:49.887862 ===================================
572 22:57:49.891440 CA_P2S_RATIO = 8
573 22:57:49.891547 DQ_CA_OPEN = 0
574 22:57:49.895030 DQ_SEMI_OPEN = 0
575 22:57:49.897814 CA_SEMI_OPEN = 0
576 22:57:49.901162 CA_FULL_RATE = 0
577 22:57:49.904817 DQ_CKDIV4_EN = 1
578 22:57:49.908226 CA_CKDIV4_EN = 1
579 22:57:49.908334 CA_PREDIV_EN = 0
580 22:57:49.911172 PH8_DLY = 0
581 22:57:49.914463 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 22:57:49.918130 DQ_AAMCK_DIV = 4
583 22:57:49.921468 CA_AAMCK_DIV = 4
584 22:57:49.924770 CA_ADMCK_DIV = 4
585 22:57:49.924882 DQ_TRACK_CA_EN = 0
586 22:57:49.928196 CA_PICK = 800
587 22:57:49.931207 CA_MCKIO = 800
588 22:57:49.935193 MCKIO_SEMI = 0
589 22:57:49.938677 PLL_FREQ = 3068
590 22:57:49.942444 DQ_UI_PI_RATIO = 32
591 22:57:49.942613 CA_UI_PI_RATIO = 0
592 22:57:49.946019 ===================================
593 22:57:49.950020 ===================================
594 22:57:49.953667 memory_type:LPDDR4
595 22:57:49.953779 GP_NUM : 10
596 22:57:49.957376 SRAM_EN : 1
597 22:57:49.957490 MD32_EN : 0
598 22:57:49.961066 ===================================
599 22:57:49.965259 [ANA_INIT] >>>>>>>>>>>>>>
600 22:57:49.969075 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 22:57:49.969197 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 22:57:49.973124 ===================================
603 22:57:49.975949 data_rate = 1600,PCW = 0X7600
604 22:57:49.979276 ===================================
605 22:57:49.982988 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 22:57:49.989908 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 22:57:49.992666 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 22:57:49.999500 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 22:57:50.002478 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 22:57:50.005866 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 22:57:50.005978 [ANA_INIT] flow start
612 22:57:50.009862 [ANA_INIT] PLL >>>>>>>>
613 22:57:50.012757 [ANA_INIT] PLL <<<<<<<<
614 22:57:50.016103 [ANA_INIT] MIDPI >>>>>>>>
615 22:57:50.016211 [ANA_INIT] MIDPI <<<<<<<<
616 22:57:50.019957 [ANA_INIT] DLL >>>>>>>>
617 22:57:50.020070 [ANA_INIT] flow end
618 22:57:50.026592 ============ LP4 DIFF to SE enter ============
619 22:57:50.030002 ============ LP4 DIFF to SE exit ============
620 22:57:50.032847 [ANA_INIT] <<<<<<<<<<<<<
621 22:57:50.036143 [Flow] Enable top DCM control >>>>>
622 22:57:50.039596 [Flow] Enable top DCM control <<<<<
623 22:57:50.039708 Enable DLL master slave shuffle
624 22:57:50.046120 ==============================================================
625 22:57:50.049482 Gating Mode config
626 22:57:50.052785 ==============================================================
627 22:57:50.056658 Config description:
628 22:57:50.066106 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 22:57:50.073022 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 22:57:50.076267 SELPH_MODE 0: By rank 1: By Phase
631 22:57:50.083140 ==============================================================
632 22:57:50.085999 GAT_TRACK_EN = 1
633 22:57:50.089695 RX_GATING_MODE = 2
634 22:57:50.092778 RX_GATING_TRACK_MODE = 2
635 22:57:50.092884 SELPH_MODE = 1
636 22:57:50.096309 PICG_EARLY_EN = 1
637 22:57:50.099839 VALID_LAT_VALUE = 1
638 22:57:50.106327 ==============================================================
639 22:57:50.109813 Enter into Gating configuration >>>>
640 22:57:50.112853 Exit from Gating configuration <<<<
641 22:57:50.116375 Enter into DVFS_PRE_config >>>>>
642 22:57:50.126516 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 22:57:50.129682 Exit from DVFS_PRE_config <<<<<
644 22:57:50.132721 Enter into PICG configuration >>>>
645 22:57:50.136265 Exit from PICG configuration <<<<
646 22:57:50.139380 [RX_INPUT] configuration >>>>>
647 22:57:50.142720 [RX_INPUT] configuration <<<<<
648 22:57:50.146240 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 22:57:50.152897 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 22:57:50.159590 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 22:57:50.166146 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 22:57:50.169668 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 22:57:50.176351 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 22:57:50.179584 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 22:57:50.186688 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 22:57:50.190150 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 22:57:50.193323 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 22:57:50.196154 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 22:57:50.203090 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 22:57:50.206570 ===================================
661 22:57:50.206682 LPDDR4 DRAM CONFIGURATION
662 22:57:50.209891 ===================================
663 22:57:50.213202 EX_ROW_EN[0] = 0x0
664 22:57:50.216274 EX_ROW_EN[1] = 0x0
665 22:57:50.216385 LP4Y_EN = 0x0
666 22:57:50.219722 WORK_FSP = 0x0
667 22:57:50.219831 WL = 0x2
668 22:57:50.222957 RL = 0x2
669 22:57:50.223065 BL = 0x2
670 22:57:50.226560 RPST = 0x0
671 22:57:50.226669 RD_PRE = 0x0
672 22:57:50.229839 WR_PRE = 0x1
673 22:57:50.229948 WR_PST = 0x0
674 22:57:50.233390 DBI_WR = 0x0
675 22:57:50.233496 DBI_RD = 0x0
676 22:57:50.236265 OTF = 0x1
677 22:57:50.239770 ===================================
678 22:57:50.243066 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 22:57:50.246505 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 22:57:50.253095 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 22:57:50.253205 ===================================
682 22:57:50.256309 LPDDR4 DRAM CONFIGURATION
683 22:57:50.260049 ===================================
684 22:57:50.263045 EX_ROW_EN[0] = 0x10
685 22:57:50.263152 EX_ROW_EN[1] = 0x0
686 22:57:50.266523 LP4Y_EN = 0x0
687 22:57:50.266630 WORK_FSP = 0x0
688 22:57:50.270043 WL = 0x2
689 22:57:50.270152 RL = 0x2
690 22:57:50.273522 BL = 0x2
691 22:57:50.273635 RPST = 0x0
692 22:57:50.276717 RD_PRE = 0x0
693 22:57:50.276825 WR_PRE = 0x1
694 22:57:50.280031 WR_PST = 0x0
695 22:57:50.283410 DBI_WR = 0x0
696 22:57:50.283519 DBI_RD = 0x0
697 22:57:50.287069 OTF = 0x1
698 22:57:50.290162 ===================================
699 22:57:50.293169 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 22:57:50.298387 nWR fixed to 40
701 22:57:50.302148 [ModeRegInit_LP4] CH0 RK0
702 22:57:50.302257 [ModeRegInit_LP4] CH0 RK1
703 22:57:50.305477 [ModeRegInit_LP4] CH1 RK0
704 22:57:50.308450 [ModeRegInit_LP4] CH1 RK1
705 22:57:50.308574 match AC timing 13
706 22:57:50.315346 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
707 22:57:50.318664 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 22:57:50.321994 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 22:57:50.328746 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 22:57:50.331865 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 22:57:50.331972 [EMI DOE] emi_dcm 0
712 22:57:50.338956 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 22:57:50.339068 ==
714 22:57:50.342095 Dram Type= 6, Freq= 0, CH_0, rank 0
715 22:57:50.345388 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
716 22:57:50.345497 ==
717 22:57:50.351828 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 22:57:50.358448 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 22:57:50.365998 [CA 0] Center 36 (6~67) winsize 62
720 22:57:50.369380 [CA 1] Center 36 (6~67) winsize 62
721 22:57:50.372288 [CA 2] Center 34 (4~65) winsize 62
722 22:57:50.376126 [CA 3] Center 34 (4~64) winsize 61
723 22:57:50.379216 [CA 4] Center 33 (2~64) winsize 63
724 22:57:50.382890 [CA 5] Center 32 (2~62) winsize 61
725 22:57:50.382999
726 22:57:50.385776 [CmdBusTrainingLP45] Vref(ca) range 1: 34
727 22:57:50.385884
728 22:57:50.389452 [CATrainingPosCal] consider 1 rank data
729 22:57:50.392631 u2DelayCellTimex100 = 270/100 ps
730 22:57:50.396300 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
731 22:57:50.399122 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
732 22:57:50.405851 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
733 22:57:50.409424 CA3 delay=34 (4~64),Diff = 2 PI (14 cell)
734 22:57:50.412718 CA4 delay=33 (2~64),Diff = 1 PI (7 cell)
735 22:57:50.416321 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
736 22:57:50.416435
737 22:57:50.419178 CA PerBit enable=1, Macro0, CA PI delay=32
738 22:57:50.419273
739 22:57:50.422443 [CBTSetCACLKResult] CA Dly = 32
740 22:57:50.422529 CS Dly: 4 (0~35)
741 22:57:50.422597 ==
742 22:57:50.425873 Dram Type= 6, Freq= 0, CH_0, rank 1
743 22:57:50.432410 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
744 22:57:50.432496 ==
745 22:57:50.435729 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 22:57:50.442422 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 22:57:50.452510 [CA 0] Center 36 (6~67) winsize 62
748 22:57:50.455277 [CA 1] Center 36 (6~67) winsize 62
749 22:57:50.458752 [CA 2] Center 34 (3~65) winsize 63
750 22:57:50.461958 [CA 3] Center 34 (3~65) winsize 63
751 22:57:50.466080 [CA 4] Center 32 (2~63) winsize 62
752 22:57:50.469302 [CA 5] Center 32 (2~63) winsize 62
753 22:57:50.469409
754 22:57:50.472393 [CmdBusTrainingLP45] Vref(ca) range 1: 32
755 22:57:50.472500
756 22:57:50.475633 [CATrainingPosCal] consider 2 rank data
757 22:57:50.478749 u2DelayCellTimex100 = 270/100 ps
758 22:57:50.482367 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
759 22:57:50.485480 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
760 22:57:50.491892 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
761 22:57:50.495399 CA3 delay=34 (4~64),Diff = 2 PI (14 cell)
762 22:57:50.498642 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
763 22:57:50.502361 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
764 22:57:50.502471
765 22:57:50.506034 CA PerBit enable=1, Macro0, CA PI delay=32
766 22:57:50.506140
767 22:57:50.509208 [CBTSetCACLKResult] CA Dly = 32
768 22:57:50.509316 CS Dly: 4 (0~36)
769 22:57:50.509409
770 22:57:50.512262 ----->DramcWriteLeveling(PI) begin...
771 22:57:50.515529 ==
772 22:57:50.515637 Dram Type= 6, Freq= 0, CH_0, rank 0
773 22:57:50.523785 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 22:57:50.523897 ==
775 22:57:50.523997 Write leveling (Byte 0): 33 => 33
776 22:57:50.527063 Write leveling (Byte 1): 29 => 29
777 22:57:50.531011 DramcWriteLeveling(PI) end<-----
778 22:57:50.531118
779 22:57:50.531210 ==
780 22:57:50.534471 Dram Type= 6, Freq= 0, CH_0, rank 0
781 22:57:50.537827 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 22:57:50.537937 ==
783 22:57:50.541076 [Gating] SW mode calibration
784 22:57:50.548389 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 22:57:50.554803 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 22:57:50.558297 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 22:57:50.561894 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
788 22:57:50.568772 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
789 22:57:50.571913 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 22:57:50.575074 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 22:57:50.578708 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 22:57:50.584886 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 22:57:50.588442 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 22:57:50.591602 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 22:57:50.598313 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 22:57:50.601856 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 22:57:50.604999 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 22:57:50.611527 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 22:57:50.615498 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 22:57:50.618506 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 22:57:50.625189 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 22:57:50.628886 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 22:57:50.631989 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
804 22:57:50.638602 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
805 22:57:50.641814 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 22:57:50.645850 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 22:57:50.648844 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 22:57:50.655377 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 22:57:50.658866 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 22:57:50.661754 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 22:57:50.668484 0 9 4 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
812 22:57:50.671879 0 9 8 | B1->B0 | 2323 3131 | 0 1 | (1 1) (1 1)
813 22:57:50.675092 0 9 12 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
814 22:57:50.682025 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 22:57:50.685374 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 22:57:50.688667 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 22:57:50.695180 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 22:57:50.698668 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 22:57:50.702330 0 10 4 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
820 22:57:50.708627 0 10 8 | B1->B0 | 2f2f 2525 | 0 0 | (1 0) (0 0)
821 22:57:50.711677 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
822 22:57:50.714912 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 22:57:50.721693 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 22:57:50.724916 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 22:57:50.728613 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 22:57:50.735212 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 22:57:50.738892 0 11 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
828 22:57:50.742092 0 11 8 | B1->B0 | 2828 4444 | 0 0 | (0 0) (0 0)
829 22:57:50.748417 0 11 12 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
830 22:57:50.752255 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 22:57:50.755349 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 22:57:50.758544 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 22:57:50.765079 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 22:57:50.768797 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 22:57:50.772228 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
836 22:57:50.778469 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
837 22:57:50.782163 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
838 22:57:50.785544 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 22:57:50.791966 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 22:57:50.795177 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 22:57:50.798812 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 22:57:50.805474 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 22:57:50.808488 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 22:57:50.811989 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 22:57:50.818733 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 22:57:50.822221 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 22:57:50.825391 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 22:57:50.828700 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 22:57:50.835334 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 22:57:50.838948 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 22:57:50.842423 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
852 22:57:50.848662 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
853 22:57:50.852197 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
854 22:57:50.855478 Total UI for P1: 0, mck2ui 16
855 22:57:50.858821 best dqsien dly found for B0: ( 0, 14, 8)
856 22:57:50.862199 Total UI for P1: 0, mck2ui 16
857 22:57:50.865766 best dqsien dly found for B1: ( 0, 14, 10)
858 22:57:50.869962 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
859 22:57:50.873031 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
860 22:57:50.873141
861 22:57:50.876770 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
862 22:57:50.879964 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
863 22:57:50.883358 [Gating] SW calibration Done
864 22:57:50.883466 ==
865 22:57:50.886308 Dram Type= 6, Freq= 0, CH_0, rank 0
866 22:57:50.889844 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
867 22:57:50.889953 ==
868 22:57:50.893430 RX Vref Scan: 0
869 22:57:50.893538
870 22:57:50.893672 RX Vref 0 -> 0, step: 1
871 22:57:50.893761
872 22:57:50.896734 RX Delay -130 -> 252, step: 16
873 22:57:50.903303 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
874 22:57:50.906629 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
875 22:57:50.910194 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
876 22:57:50.913400 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
877 22:57:50.916438 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
878 22:57:50.920099 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
879 22:57:50.926289 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
880 22:57:50.930040 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
881 22:57:50.933311 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
882 22:57:50.939293 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
883 22:57:50.940194 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
884 22:57:50.946500 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
885 22:57:50.949991 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
886 22:57:50.953366 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
887 22:57:50.956524 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
888 22:57:50.963297 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
889 22:57:50.963405 ==
890 22:57:50.966704 Dram Type= 6, Freq= 0, CH_0, rank 0
891 22:57:50.969995 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
892 22:57:50.970104 ==
893 22:57:50.970198 DQS Delay:
894 22:57:50.973528 DQS0 = 0, DQS1 = 0
895 22:57:50.973672 DQM Delay:
896 22:57:50.977126 DQM0 = 93, DQM1 = 85
897 22:57:50.977230 DQ Delay:
898 22:57:50.979995 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =93
899 22:57:50.983244 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =101
900 22:57:50.986514 DQ8 =77, DQ9 =69, DQ10 =85, DQ11 =77
901 22:57:50.989904 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
902 22:57:50.990014
903 22:57:50.990108
904 22:57:50.990201 ==
905 22:57:50.993444 Dram Type= 6, Freq= 0, CH_0, rank 0
906 22:57:50.996539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
907 22:57:50.996647 ==
908 22:57:50.996742
909 22:57:50.996833
910 22:57:51.000213 TX Vref Scan disable
911 22:57:51.003307 == TX Byte 0 ==
912 22:57:51.007242 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
913 22:57:51.010264 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
914 22:57:51.013533 == TX Byte 1 ==
915 22:57:51.016921 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
916 22:57:51.020050 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
917 22:57:51.020161 ==
918 22:57:51.023477 Dram Type= 6, Freq= 0, CH_0, rank 0
919 22:57:51.026785 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
920 22:57:51.029828 ==
921 22:57:51.041831 TX Vref=22, minBit 10, minWin=27, winSum=450
922 22:57:51.045442 TX Vref=24, minBit 8, minWin=27, winSum=450
923 22:57:51.048736 TX Vref=26, minBit 0, minWin=28, winSum=455
924 22:57:51.051576 TX Vref=28, minBit 4, minWin=28, winSum=458
925 22:57:51.055051 TX Vref=30, minBit 8, minWin=28, winSum=458
926 22:57:51.061556 TX Vref=32, minBit 2, minWin=28, winSum=452
927 22:57:51.065282 [TxChooseVref] Worse bit 4, Min win 28, Win sum 458, Final Vref 28
928 22:57:51.065412
929 22:57:51.068604 Final TX Range 1 Vref 28
930 22:57:51.068690
931 22:57:51.068757 ==
932 22:57:51.072090 Dram Type= 6, Freq= 0, CH_0, rank 0
933 22:57:51.075829 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 22:57:51.075936 ==
935 22:57:51.076006
936 22:57:51.078322
937 22:57:51.078407 TX Vref Scan disable
938 22:57:51.081960 == TX Byte 0 ==
939 22:57:51.085570 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
940 22:57:51.088740 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
941 22:57:51.092301 == TX Byte 1 ==
942 22:57:51.095468 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
943 22:57:51.098834 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
944 22:57:51.101837
945 22:57:51.101920 [DATLAT]
946 22:57:51.101986 Freq=800, CH0 RK0
947 22:57:51.102048
948 22:57:51.105384 DATLAT Default: 0xa
949 22:57:51.105468 0, 0xFFFF, sum = 0
950 22:57:51.108694 1, 0xFFFF, sum = 0
951 22:57:51.108782 2, 0xFFFF, sum = 0
952 22:57:51.112167 3, 0xFFFF, sum = 0
953 22:57:51.112294 4, 0xFFFF, sum = 0
954 22:57:51.115511 5, 0xFFFF, sum = 0
955 22:57:51.115596 6, 0xFFFF, sum = 0
956 22:57:51.118735 7, 0xFFFF, sum = 0
957 22:57:51.118822 8, 0xFFFF, sum = 0
958 22:57:51.122339 9, 0x0, sum = 1
959 22:57:51.122429 10, 0x0, sum = 2
960 22:57:51.125434 11, 0x0, sum = 3
961 22:57:51.125519 12, 0x0, sum = 4
962 22:57:51.129014 best_step = 10
963 22:57:51.129100
964 22:57:51.129166 ==
965 22:57:51.132093 Dram Type= 6, Freq= 0, CH_0, rank 0
966 22:57:51.135892 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
967 22:57:51.135976 ==
968 22:57:51.139233 RX Vref Scan: 1
969 22:57:51.139331
970 22:57:51.139398 Set Vref Range= 32 -> 127
971 22:57:51.139460
972 22:57:51.142301 RX Vref 32 -> 127, step: 1
973 22:57:51.142385
974 22:57:51.145519 RX Delay -95 -> 252, step: 8
975 22:57:51.145625
976 22:57:51.149189 Set Vref, RX VrefLevel [Byte0]: 32
977 22:57:51.152459 [Byte1]: 32
978 22:57:51.152546
979 22:57:51.155456 Set Vref, RX VrefLevel [Byte0]: 33
980 22:57:51.159233 [Byte1]: 33
981 22:57:51.162372
982 22:57:51.162455 Set Vref, RX VrefLevel [Byte0]: 34
983 22:57:51.165440 [Byte1]: 34
984 22:57:51.170083
985 22:57:51.170177 Set Vref, RX VrefLevel [Byte0]: 35
986 22:57:51.172919 [Byte1]: 35
987 22:57:51.177544
988 22:57:51.177637 Set Vref, RX VrefLevel [Byte0]: 36
989 22:57:51.180998 [Byte1]: 36
990 22:57:51.185698
991 22:57:51.185792 Set Vref, RX VrefLevel [Byte0]: 37
992 22:57:51.188507 [Byte1]: 37
993 22:57:51.193478
994 22:57:51.193588 Set Vref, RX VrefLevel [Byte0]: 38
995 22:57:51.196983 [Byte1]: 38
996 22:57:51.200803
997 22:57:51.200891 Set Vref, RX VrefLevel [Byte0]: 39
998 22:57:51.204340 [Byte1]: 39
999 22:57:51.208100
1000 22:57:51.208189 Set Vref, RX VrefLevel [Byte0]: 40
1001 22:57:51.211613 [Byte1]: 40
1002 22:57:51.215759
1003 22:57:51.215851 Set Vref, RX VrefLevel [Byte0]: 41
1004 22:57:51.219354 [Byte1]: 41
1005 22:57:51.223118
1006 22:57:51.223211 Set Vref, RX VrefLevel [Byte0]: 42
1007 22:57:51.226576 [Byte1]: 42
1008 22:57:51.230583
1009 22:57:51.230670 Set Vref, RX VrefLevel [Byte0]: 43
1010 22:57:51.234114 [Byte1]: 43
1011 22:57:51.238199
1012 22:57:51.238305 Set Vref, RX VrefLevel [Byte0]: 44
1013 22:57:51.241395 [Byte1]: 44
1014 22:57:51.245636
1015 22:57:51.245753 Set Vref, RX VrefLevel [Byte0]: 45
1016 22:57:51.249561 [Byte1]: 45
1017 22:57:51.253527
1018 22:57:51.253640 Set Vref, RX VrefLevel [Byte0]: 46
1019 22:57:51.256683 [Byte1]: 46
1020 22:57:51.261323
1021 22:57:51.261409 Set Vref, RX VrefLevel [Byte0]: 47
1022 22:57:51.264647 [Byte1]: 47
1023 22:57:51.268663
1024 22:57:51.268753 Set Vref, RX VrefLevel [Byte0]: 48
1025 22:57:51.271742 [Byte1]: 48
1026 22:57:51.276435
1027 22:57:51.276519 Set Vref, RX VrefLevel [Byte0]: 49
1028 22:57:51.279740 [Byte1]: 49
1029 22:57:51.283734
1030 22:57:51.283820 Set Vref, RX VrefLevel [Byte0]: 50
1031 22:57:51.286943 [Byte1]: 50
1032 22:57:51.291634
1033 22:57:51.291719 Set Vref, RX VrefLevel [Byte0]: 51
1034 22:57:51.294730 [Byte1]: 51
1035 22:57:51.299411
1036 22:57:51.299501 Set Vref, RX VrefLevel [Byte0]: 52
1037 22:57:51.302342 [Byte1]: 52
1038 22:57:51.306686
1039 22:57:51.306772 Set Vref, RX VrefLevel [Byte0]: 53
1040 22:57:51.310021 [Byte1]: 53
1041 22:57:51.314454
1042 22:57:51.314541 Set Vref, RX VrefLevel [Byte0]: 54
1043 22:57:51.317332 [Byte1]: 54
1044 22:57:51.322049
1045 22:57:51.322140 Set Vref, RX VrefLevel [Byte0]: 55
1046 22:57:51.325196 [Byte1]: 55
1047 22:57:51.329380
1048 22:57:51.329466 Set Vref, RX VrefLevel [Byte0]: 56
1049 22:57:51.332469 [Byte1]: 56
1050 22:57:51.336991
1051 22:57:51.337078 Set Vref, RX VrefLevel [Byte0]: 57
1052 22:57:51.340674 [Byte1]: 57
1053 22:57:51.344659
1054 22:57:51.344743 Set Vref, RX VrefLevel [Byte0]: 58
1055 22:57:51.348412 [Byte1]: 58
1056 22:57:51.351993
1057 22:57:51.352078 Set Vref, RX VrefLevel [Byte0]: 59
1058 22:57:51.355751 [Byte1]: 59
1059 22:57:51.359985
1060 22:57:51.360075 Set Vref, RX VrefLevel [Byte0]: 60
1061 22:57:51.363258 [Byte1]: 60
1062 22:57:51.367242
1063 22:57:51.367326 Set Vref, RX VrefLevel [Byte0]: 61
1064 22:57:51.370856 [Byte1]: 61
1065 22:57:51.375344
1066 22:57:51.375427 Set Vref, RX VrefLevel [Byte0]: 62
1067 22:57:51.378489 [Byte1]: 62
1068 22:57:51.382669
1069 22:57:51.382755 Set Vref, RX VrefLevel [Byte0]: 63
1070 22:57:51.385707 [Byte1]: 63
1071 22:57:51.390150
1072 22:57:51.390243 Set Vref, RX VrefLevel [Byte0]: 64
1073 22:57:51.393556 [Byte1]: 64
1074 22:57:51.397775
1075 22:57:51.397859 Set Vref, RX VrefLevel [Byte0]: 65
1076 22:57:51.401254 [Byte1]: 65
1077 22:57:51.405433
1078 22:57:51.405524 Set Vref, RX VrefLevel [Byte0]: 66
1079 22:57:51.409111 [Byte1]: 66
1080 22:57:51.413262
1081 22:57:51.413349 Set Vref, RX VrefLevel [Byte0]: 67
1082 22:57:51.416646 [Byte1]: 67
1083 22:57:51.421077
1084 22:57:51.421166 Set Vref, RX VrefLevel [Byte0]: 68
1085 22:57:51.423848 [Byte1]: 68
1086 22:57:51.428035
1087 22:57:51.428120 Set Vref, RX VrefLevel [Byte0]: 69
1088 22:57:51.431377 [Byte1]: 69
1089 22:57:51.435859
1090 22:57:51.435944 Set Vref, RX VrefLevel [Byte0]: 70
1091 22:57:51.439464 [Byte1]: 70
1092 22:57:51.443678
1093 22:57:51.443765 Set Vref, RX VrefLevel [Byte0]: 71
1094 22:57:51.446499 [Byte1]: 71
1095 22:57:51.450741
1096 22:57:51.450851 Set Vref, RX VrefLevel [Byte0]: 72
1097 22:57:51.454168 [Byte1]: 72
1098 22:57:51.458643
1099 22:57:51.458742 Set Vref, RX VrefLevel [Byte0]: 73
1100 22:57:51.462071 [Byte1]: 73
1101 22:57:51.466389
1102 22:57:51.466476 Set Vref, RX VrefLevel [Byte0]: 74
1103 22:57:51.469445 [Byte1]: 74
1104 22:57:51.474032
1105 22:57:51.474121 Set Vref, RX VrefLevel [Byte0]: 75
1106 22:57:51.477244 [Byte1]: 75
1107 22:57:51.481701
1108 22:57:51.481786 Set Vref, RX VrefLevel [Byte0]: 76
1109 22:57:51.485015 [Byte1]: 76
1110 22:57:51.489001
1111 22:57:51.489087 Set Vref, RX VrefLevel [Byte0]: 77
1112 22:57:51.492050 [Byte1]: 77
1113 22:57:51.496627
1114 22:57:51.496711 Set Vref, RX VrefLevel [Byte0]: 78
1115 22:57:51.500007 [Byte1]: 78
1116 22:57:51.504370
1117 22:57:51.504468 Final RX Vref Byte 0 = 55 to rank0
1118 22:57:51.507663 Final RX Vref Byte 1 = 59 to rank0
1119 22:57:51.511144 Final RX Vref Byte 0 = 55 to rank1
1120 22:57:51.514347 Final RX Vref Byte 1 = 59 to rank1==
1121 22:57:51.517767 Dram Type= 6, Freq= 0, CH_0, rank 0
1122 22:57:51.524503 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1123 22:57:51.524603 ==
1124 22:57:51.524670 DQS Delay:
1125 22:57:51.524729 DQS0 = 0, DQS1 = 0
1126 22:57:51.527587 DQM Delay:
1127 22:57:51.527672 DQM0 = 92, DQM1 = 86
1128 22:57:51.530971 DQ Delay:
1129 22:57:51.534021 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1130 22:57:51.537908 DQ4 =92, DQ5 =80, DQ6 =100, DQ7 =100
1131 22:57:51.541228 DQ8 =76, DQ9 =80, DQ10 =88, DQ11 =76
1132 22:57:51.544555 DQ12 =92, DQ13 =92, DQ14 =92, DQ15 =92
1133 22:57:51.544641
1134 22:57:51.544704
1135 22:57:51.551102 [DQSOSCAuto] RK0, (LSB)MR18= 0x4b41, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 391 ps
1136 22:57:51.554346 CH0 RK0: MR19=606, MR18=4B41
1137 22:57:51.561201 CH0_RK0: MR19=0x606, MR18=0x4B41, DQSOSC=391, MR23=63, INC=96, DEC=64
1138 22:57:51.561304
1139 22:57:51.564389 ----->DramcWriteLeveling(PI) begin...
1140 22:57:51.564475 ==
1141 22:57:51.567637 Dram Type= 6, Freq= 0, CH_0, rank 1
1142 22:57:51.571117 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1143 22:57:51.571223 ==
1144 22:57:51.574745 Write leveling (Byte 0): 33 => 33
1145 22:57:51.577696 Write leveling (Byte 1): 28 => 28
1146 22:57:51.580889 DramcWriteLeveling(PI) end<-----
1147 22:57:51.580974
1148 22:57:51.581039 ==
1149 22:57:51.584546 Dram Type= 6, Freq= 0, CH_0, rank 1
1150 22:57:51.587545 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1151 22:57:51.587636 ==
1152 22:57:51.631569 [Gating] SW mode calibration
1153 22:57:51.631948 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1154 22:57:51.632051 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1155 22:57:51.632130 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1156 22:57:51.632427 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1157 22:57:51.632565 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1158 22:57:51.632711 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 22:57:51.632837 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 22:57:51.632940 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 22:57:51.675999 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 22:57:51.676190 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 22:57:51.676485 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 22:57:51.676624 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 22:57:51.677380 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 22:57:51.677661 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 22:57:51.677816 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 22:57:51.677917 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 22:57:51.678350 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 22:57:51.679024 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 22:57:51.719586 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 22:57:51.719746 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1173 22:57:51.719816 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1174 22:57:51.720073 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 22:57:51.720323 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 22:57:51.720992 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 22:57:51.721075 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 22:57:51.721324 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 22:57:51.722246 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 22:57:51.722581 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 22:57:51.729326 0 9 8 | B1->B0 | 2d2d 2c2c | 1 0 | (1 1) (0 0)
1182 22:57:51.729427 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1183 22:57:51.732743 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1184 22:57:51.735995 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1185 22:57:51.739326 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1186 22:57:51.743122 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1187 22:57:51.749409 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1188 22:57:51.752805 0 10 4 | B1->B0 | 3333 3232 | 0 0 | (0 0) (0 0)
1189 22:57:51.756426 0 10 8 | B1->B0 | 2525 2424 | 0 0 | (1 0) (0 1)
1190 22:57:51.763703 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1191 22:57:51.767200 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 22:57:51.771003 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 22:57:51.774370 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 22:57:51.777938 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 22:57:51.784526 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1196 22:57:51.788031 0 11 4 | B1->B0 | 2626 2424 | 1 0 | (0 0) (0 0)
1197 22:57:51.792518 0 11 8 | B1->B0 | 3d3d 3e3e | 0 1 | (0 0) (0 0)
1198 22:57:51.795789 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1199 22:57:51.802223 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1200 22:57:51.805818 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1201 22:57:51.808975 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1202 22:57:51.815635 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1203 22:57:51.818837 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1204 22:57:51.822554 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1205 22:57:51.828807 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1206 22:57:51.832402 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 22:57:51.835751 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 22:57:51.839058 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 22:57:51.845771 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 22:57:51.849016 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 22:57:51.852283 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 22:57:51.859020 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 22:57:51.862202 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 22:57:51.865561 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 22:57:51.872025 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 22:57:51.875889 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 22:57:51.878927 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 22:57:51.885589 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1219 22:57:51.889117 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1220 22:57:51.892328 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1221 22:57:51.898617 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1222 22:57:51.898722 Total UI for P1: 0, mck2ui 16
1223 22:57:51.905311 best dqsien dly found for B1: ( 0, 14, 6)
1224 22:57:51.908811 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1225 22:57:51.911963 Total UI for P1: 0, mck2ui 16
1226 22:57:51.915451 best dqsien dly found for B0: ( 0, 14, 8)
1227 22:57:51.918650 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1228 22:57:51.922000 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1229 22:57:51.922090
1230 22:57:51.925676 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1231 22:57:51.928951 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1232 22:57:51.932369 [Gating] SW calibration Done
1233 22:57:51.932459 ==
1234 22:57:51.935489 Dram Type= 6, Freq= 0, CH_0, rank 1
1235 22:57:51.938867 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1236 22:57:51.938959 ==
1237 22:57:51.942215 RX Vref Scan: 0
1238 22:57:51.942298
1239 22:57:51.945488 RX Vref 0 -> 0, step: 1
1240 22:57:51.945595
1241 22:57:51.945675 RX Delay -130 -> 252, step: 16
1242 22:57:51.952277 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1243 22:57:51.955690 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1244 22:57:51.959044 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1245 22:57:51.962156 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1246 22:57:51.965490 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1247 22:57:51.972437 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1248 22:57:51.975752 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1249 22:57:51.979184 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1250 22:57:51.982525 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1251 22:57:51.985564 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1252 22:57:51.992132 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1253 22:57:51.996553 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1254 22:57:51.998880 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1255 22:57:52.002160 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1256 22:57:52.005539 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1257 22:57:52.012061 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1258 22:57:52.012168 ==
1259 22:57:52.015529 Dram Type= 6, Freq= 0, CH_0, rank 1
1260 22:57:52.019207 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1261 22:57:52.019299 ==
1262 22:57:52.019365 DQS Delay:
1263 22:57:52.022291 DQS0 = 0, DQS1 = 0
1264 22:57:52.022378 DQM Delay:
1265 22:57:52.025773 DQM0 = 90, DQM1 = 83
1266 22:57:52.025891 DQ Delay:
1267 22:57:52.028855 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
1268 22:57:52.032169 DQ4 =93, DQ5 =85, DQ6 =93, DQ7 =101
1269 22:57:52.035721 DQ8 =77, DQ9 =77, DQ10 =77, DQ11 =77
1270 22:57:52.038701 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =93
1271 22:57:52.038788
1272 22:57:52.038854
1273 22:57:52.038914 ==
1274 22:57:52.042475 Dram Type= 6, Freq= 0, CH_0, rank 1
1275 22:57:52.046051 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1276 22:57:52.046139 ==
1277 22:57:52.046204
1278 22:57:52.049288
1279 22:57:52.049373 TX Vref Scan disable
1280 22:57:52.052488 == TX Byte 0 ==
1281 22:57:52.055843 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1282 22:57:52.059170 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1283 22:57:52.062659 == TX Byte 1 ==
1284 22:57:52.065853 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1285 22:57:52.069148 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1286 22:57:52.069233 ==
1287 22:57:52.072483 Dram Type= 6, Freq= 0, CH_0, rank 1
1288 22:57:52.079520 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1289 22:57:52.079628 ==
1290 22:57:52.091538 TX Vref=22, minBit 8, minWin=27, winSum=447
1291 22:57:52.094506 TX Vref=24, minBit 1, minWin=28, winSum=454
1292 22:57:52.098094 TX Vref=26, minBit 1, minWin=28, winSum=458
1293 22:57:52.101281 TX Vref=28, minBit 4, minWin=28, winSum=458
1294 22:57:52.104502 TX Vref=30, minBit 2, minWin=28, winSum=460
1295 22:57:52.108248 TX Vref=32, minBit 2, minWin=28, winSum=454
1296 22:57:52.115124 [TxChooseVref] Worse bit 2, Min win 28, Win sum 460, Final Vref 30
1297 22:57:52.115257
1298 22:57:52.118574 Final TX Range 1 Vref 30
1299 22:57:52.118661
1300 22:57:52.118727 ==
1301 22:57:52.121292 Dram Type= 6, Freq= 0, CH_0, rank 1
1302 22:57:52.124716 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1303 22:57:52.124803 ==
1304 22:57:52.124873
1305 22:57:52.124933
1306 22:57:52.128099 TX Vref Scan disable
1307 22:57:52.131742 == TX Byte 0 ==
1308 22:57:52.135134 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1309 22:57:52.138565 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1310 22:57:52.141985 == TX Byte 1 ==
1311 22:57:52.145454 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1312 22:57:52.148803 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1313 22:57:52.148894
1314 22:57:52.151569 [DATLAT]
1315 22:57:52.151652 Freq=800, CH0 RK1
1316 22:57:52.151717
1317 22:57:52.154979 DATLAT Default: 0xa
1318 22:57:52.155065 0, 0xFFFF, sum = 0
1319 22:57:52.158633 1, 0xFFFF, sum = 0
1320 22:57:52.158722 2, 0xFFFF, sum = 0
1321 22:57:52.162101 3, 0xFFFF, sum = 0
1322 22:57:52.162186 4, 0xFFFF, sum = 0
1323 22:57:52.165145 5, 0xFFFF, sum = 0
1324 22:57:52.165229 6, 0xFFFF, sum = 0
1325 22:57:52.168774 7, 0xFFFF, sum = 0
1326 22:57:52.168860 8, 0xFFFF, sum = 0
1327 22:57:52.171803 9, 0x0, sum = 1
1328 22:57:52.171887 10, 0x0, sum = 2
1329 22:57:52.175085 11, 0x0, sum = 3
1330 22:57:52.175170 12, 0x0, sum = 4
1331 22:57:52.178614 best_step = 10
1332 22:57:52.178699
1333 22:57:52.178764 ==
1334 22:57:52.181748 Dram Type= 6, Freq= 0, CH_0, rank 1
1335 22:57:52.185038 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1336 22:57:52.185126 ==
1337 22:57:52.188501 RX Vref Scan: 0
1338 22:57:52.188587
1339 22:57:52.188652 RX Vref 0 -> 0, step: 1
1340 22:57:52.188713
1341 22:57:52.192000 RX Delay -79 -> 252, step: 8
1342 22:57:52.198515 iDelay=209, Bit 0, Center 92 (-15 ~ 200) 216
1343 22:57:52.202128 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1344 22:57:52.205188 iDelay=209, Bit 2, Center 92 (-15 ~ 200) 216
1345 22:57:52.208574 iDelay=209, Bit 3, Center 92 (-15 ~ 200) 216
1346 22:57:52.211434 iDelay=209, Bit 4, Center 96 (-15 ~ 208) 224
1347 22:57:52.218350 iDelay=209, Bit 5, Center 84 (-23 ~ 192) 216
1348 22:57:52.221736 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1349 22:57:52.225104 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1350 22:57:52.228273 iDelay=209, Bit 8, Center 72 (-39 ~ 184) 224
1351 22:57:52.231622 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1352 22:57:52.238484 iDelay=209, Bit 10, Center 88 (-15 ~ 192) 208
1353 22:57:52.241892 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1354 22:57:52.244964 iDelay=209, Bit 12, Center 88 (-15 ~ 192) 208
1355 22:57:52.248468 iDelay=209, Bit 13, Center 92 (-15 ~ 200) 216
1356 22:57:52.251980 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1357 22:57:52.258375 iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216
1358 22:57:52.258509 ==
1359 22:57:52.261717 Dram Type= 6, Freq= 0, CH_0, rank 1
1360 22:57:52.264868 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1361 22:57:52.264953 ==
1362 22:57:52.265018 DQS Delay:
1363 22:57:52.268530 DQS0 = 0, DQS1 = 0
1364 22:57:52.268617 DQM Delay:
1365 22:57:52.271520 DQM0 = 93, DQM1 = 84
1366 22:57:52.271603 DQ Delay:
1367 22:57:52.274799 DQ0 =92, DQ1 =92, DQ2 =92, DQ3 =92
1368 22:57:52.278582 DQ4 =96, DQ5 =84, DQ6 =100, DQ7 =100
1369 22:57:52.281483 DQ8 =72, DQ9 =72, DQ10 =88, DQ11 =76
1370 22:57:52.285140 DQ12 =88, DQ13 =92, DQ14 =92, DQ15 =92
1371 22:57:52.285230
1372 22:57:52.285297
1373 22:57:52.292165 [DQSOSCAuto] RK1, (LSB)MR18= 0x4214, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 393 ps
1374 22:57:52.295165 CH0 RK1: MR19=606, MR18=4214
1375 22:57:52.301520 CH0_RK1: MR19=0x606, MR18=0x4214, DQSOSC=393, MR23=63, INC=95, DEC=63
1376 22:57:52.305268 [RxdqsGatingPostProcess] freq 800
1377 22:57:52.311765 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1378 22:57:52.311875 Pre-setting of DQS Precalculation
1379 22:57:52.318616 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1380 22:57:52.318725 ==
1381 22:57:52.322174 Dram Type= 6, Freq= 0, CH_1, rank 0
1382 22:57:52.325117 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1383 22:57:52.325204 ==
1384 22:57:52.331722 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1385 22:57:52.338600 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1386 22:57:52.346392 [CA 0] Center 36 (6~67) winsize 62
1387 22:57:52.349617 [CA 1] Center 36 (6~67) winsize 62
1388 22:57:52.353102 [CA 2] Center 35 (5~66) winsize 62
1389 22:57:52.356348 [CA 3] Center 34 (4~65) winsize 62
1390 22:57:52.359715 [CA 4] Center 35 (5~65) winsize 61
1391 22:57:52.363075 [CA 5] Center 34 (4~64) winsize 61
1392 22:57:52.363162
1393 22:57:52.366533 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1394 22:57:52.366617
1395 22:57:52.370623 [CATrainingPosCal] consider 1 rank data
1396 22:57:52.373217 u2DelayCellTimex100 = 270/100 ps
1397 22:57:52.376851 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1398 22:57:52.379819 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1399 22:57:52.383535 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
1400 22:57:52.389974 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1401 22:57:52.393324 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1402 22:57:52.396500 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1403 22:57:52.396589
1404 22:57:52.400199 CA PerBit enable=1, Macro0, CA PI delay=34
1405 22:57:52.400284
1406 22:57:52.403227 [CBTSetCACLKResult] CA Dly = 34
1407 22:57:52.403313 CS Dly: 6 (0~37)
1408 22:57:52.403379 ==
1409 22:57:52.406829 Dram Type= 6, Freq= 0, CH_1, rank 1
1410 22:57:52.413021 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1411 22:57:52.413124 ==
1412 22:57:52.416590 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1413 22:57:52.423020 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1414 22:57:52.433424 [CA 0] Center 36 (6~67) winsize 62
1415 22:57:52.437119 [CA 1] Center 37 (6~68) winsize 63
1416 22:57:52.441293 [CA 2] Center 35 (5~66) winsize 62
1417 22:57:52.444947 [CA 3] Center 34 (4~65) winsize 62
1418 22:57:52.448533 [CA 4] Center 35 (4~66) winsize 63
1419 22:57:52.448636 [CA 5] Center 34 (4~65) winsize 62
1420 22:57:52.448703
1421 22:57:52.452537 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1422 22:57:52.452626
1423 22:57:52.455930 [CATrainingPosCal] consider 2 rank data
1424 22:57:52.459982 u2DelayCellTimex100 = 270/100 ps
1425 22:57:52.462928 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1426 22:57:52.466059 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1427 22:57:52.469583 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
1428 22:57:52.476158 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1429 22:57:52.479561 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1430 22:57:52.482928 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1431 22:57:52.483018
1432 22:57:52.486228 CA PerBit enable=1, Macro0, CA PI delay=34
1433 22:57:52.486324
1434 22:57:52.489241 [CBTSetCACLKResult] CA Dly = 34
1435 22:57:52.489330 CS Dly: 7 (0~39)
1436 22:57:52.489397
1437 22:57:52.492604 ----->DramcWriteLeveling(PI) begin...
1438 22:57:52.492692 ==
1439 22:57:52.495873 Dram Type= 6, Freq= 0, CH_1, rank 0
1440 22:57:52.502486 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1441 22:57:52.502593 ==
1442 22:57:52.506170 Write leveling (Byte 0): 25 => 25
1443 22:57:52.509327 Write leveling (Byte 1): 30 => 30
1444 22:57:52.509417 DramcWriteLeveling(PI) end<-----
1445 22:57:52.512788
1446 22:57:52.512911 ==
1447 22:57:52.516160 Dram Type= 6, Freq= 0, CH_1, rank 0
1448 22:57:52.519254 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1449 22:57:52.519345 ==
1450 22:57:52.523006 [Gating] SW mode calibration
1451 22:57:52.529622 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1452 22:57:52.532799 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1453 22:57:52.539987 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1454 22:57:52.542708 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1455 22:57:52.546076 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1456 22:57:52.552869 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 22:57:52.556099 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 22:57:52.559960 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 22:57:52.565946 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 22:57:52.569701 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 22:57:52.572904 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 22:57:52.579823 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 22:57:52.583104 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 22:57:52.586105 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 22:57:52.589619 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 22:57:52.596337 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 22:57:52.599825 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 22:57:52.602754 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 22:57:52.609866 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 1)
1470 22:57:52.613246 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 1)
1471 22:57:52.616518 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 22:57:52.623355 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 22:57:52.626582 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 22:57:52.629668 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 22:57:52.636337 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 22:57:52.639733 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 22:57:52.642991 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 22:57:52.649852 0 9 4 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
1479 22:57:52.653129 0 9 8 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
1480 22:57:52.656759 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1481 22:57:52.659943 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1482 22:57:52.666420 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1483 22:57:52.670138 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1484 22:57:52.673111 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1485 22:57:52.679766 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1486 22:57:52.683228 0 10 4 | B1->B0 | 3333 2e2e | 1 0 | (0 0) (0 1)
1487 22:57:52.686477 0 10 8 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
1488 22:57:52.693708 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 22:57:52.696978 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 22:57:52.700352 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 22:57:52.706904 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 22:57:52.710151 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 22:57:52.713239 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1494 22:57:52.720470 0 11 4 | B1->B0 | 2525 3131 | 1 1 | (0 0) (0 0)
1495 22:57:52.723290 0 11 8 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
1496 22:57:52.726936 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1497 22:57:52.730609 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1498 22:57:52.737117 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1499 22:57:52.740508 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1500 22:57:52.743335 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1501 22:57:52.750399 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1502 22:57:52.753682 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1503 22:57:52.756911 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1504 22:57:52.763608 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 22:57:52.766988 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 22:57:52.770619 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 22:57:52.777240 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 22:57:52.780596 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 22:57:52.783487 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 22:57:52.790320 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 22:57:52.793456 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 22:57:52.797183 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 22:57:52.803721 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 22:57:52.807072 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 22:57:52.810362 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 22:57:52.813771 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1517 22:57:52.820745 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1518 22:57:52.824222 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1519 22:57:52.827248 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1520 22:57:52.830780 Total UI for P1: 0, mck2ui 16
1521 22:57:52.833553 best dqsien dly found for B0: ( 0, 14, 2)
1522 22:57:52.837655 Total UI for P1: 0, mck2ui 16
1523 22:57:52.840495 best dqsien dly found for B1: ( 0, 14, 2)
1524 22:57:52.843901 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1525 22:57:52.847223 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1526 22:57:52.847324
1527 22:57:52.854214 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1528 22:57:52.857278 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1529 22:57:52.857386 [Gating] SW calibration Done
1530 22:57:52.860919 ==
1531 22:57:52.861015 Dram Type= 6, Freq= 0, CH_1, rank 0
1532 22:57:52.867033 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1533 22:57:52.867197 ==
1534 22:57:52.867295 RX Vref Scan: 0
1535 22:57:52.867378
1536 22:57:52.870499 RX Vref 0 -> 0, step: 1
1537 22:57:52.870590
1538 22:57:52.873858 RX Delay -130 -> 252, step: 16
1539 22:57:52.877296 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1540 22:57:52.880298 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1541 22:57:52.883759 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1542 22:57:52.890997 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1543 22:57:52.893465 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1544 22:57:52.897251 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1545 22:57:52.900469 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1546 22:57:52.903979 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1547 22:57:52.910759 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1548 22:57:52.913628 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1549 22:57:52.917257 iDelay=222, Bit 10, Center 93 (-2 ~ 189) 192
1550 22:57:52.920412 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1551 22:57:52.924014 iDelay=222, Bit 12, Center 101 (-2 ~ 205) 208
1552 22:57:52.930573 iDelay=222, Bit 13, Center 101 (-2 ~ 205) 208
1553 22:57:52.934024 iDelay=222, Bit 14, Center 101 (-2 ~ 205) 208
1554 22:57:52.937374 iDelay=222, Bit 15, Center 101 (-2 ~ 205) 208
1555 22:57:52.937479 ==
1556 22:57:52.940307 Dram Type= 6, Freq= 0, CH_1, rank 0
1557 22:57:52.944086 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1558 22:57:52.944195 ==
1559 22:57:52.947011 DQS Delay:
1560 22:57:52.947103 DQS0 = 0, DQS1 = 0
1561 22:57:52.950357 DQM Delay:
1562 22:57:52.950458 DQM0 = 94, DQM1 = 92
1563 22:57:52.950526 DQ Delay:
1564 22:57:52.953755 DQ0 =101, DQ1 =85, DQ2 =77, DQ3 =93
1565 22:57:52.957202 DQ4 =93, DQ5 =109, DQ6 =101, DQ7 =93
1566 22:57:52.960834 DQ8 =77, DQ9 =77, DQ10 =93, DQ11 =85
1567 22:57:52.963807 DQ12 =101, DQ13 =101, DQ14 =101, DQ15 =101
1568 22:57:52.967221
1569 22:57:52.967328
1570 22:57:52.967417 ==
1571 22:57:52.970465 Dram Type= 6, Freq= 0, CH_1, rank 0
1572 22:57:52.973807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1573 22:57:52.973908 ==
1574 22:57:52.973998
1575 22:57:52.974079
1576 22:57:52.977366 TX Vref Scan disable
1577 22:57:52.977458 == TX Byte 0 ==
1578 22:57:52.983871 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1579 22:57:52.987434 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1580 22:57:52.987568 == TX Byte 1 ==
1581 22:57:52.993784 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1582 22:57:52.997460 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1583 22:57:52.997583 ==
1584 22:57:53.000698 Dram Type= 6, Freq= 0, CH_1, rank 0
1585 22:57:53.004038 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1586 22:57:53.004144 ==
1587 22:57:53.017602 TX Vref=22, minBit 0, minWin=26, winSum=428
1588 22:57:53.021221 TX Vref=24, minBit 0, minWin=26, winSum=432
1589 22:57:53.024371 TX Vref=26, minBit 0, minWin=26, winSum=433
1590 22:57:53.027826 TX Vref=28, minBit 3, minWin=26, winSum=440
1591 22:57:53.031158 TX Vref=30, minBit 0, minWin=26, winSum=440
1592 22:57:53.034314 TX Vref=32, minBit 0, minWin=26, winSum=441
1593 22:57:53.041100 [TxChooseVref] Worse bit 0, Min win 26, Win sum 441, Final Vref 32
1594 22:57:53.041237
1595 22:57:53.044561 Final TX Range 1 Vref 32
1596 22:57:53.044659
1597 22:57:53.044726 ==
1598 22:57:53.047459 Dram Type= 6, Freq= 0, CH_1, rank 0
1599 22:57:53.051065 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1600 22:57:53.051166 ==
1601 22:57:53.051236
1602 22:57:53.054265
1603 22:57:53.054367 TX Vref Scan disable
1604 22:57:53.057378 == TX Byte 0 ==
1605 22:57:53.061316 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1606 22:57:53.067572 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1607 22:57:53.067716 == TX Byte 1 ==
1608 22:57:53.070770 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1609 22:57:53.077864 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1610 22:57:53.078003
1611 22:57:53.078073 [DATLAT]
1612 22:57:53.078134 Freq=800, CH1 RK0
1613 22:57:53.078194
1614 22:57:53.080978 DATLAT Default: 0xa
1615 22:57:53.081067 0, 0xFFFF, sum = 0
1616 22:57:53.084759 1, 0xFFFF, sum = 0
1617 22:57:53.084857 2, 0xFFFF, sum = 0
1618 22:57:53.087594 3, 0xFFFF, sum = 0
1619 22:57:53.087726 4, 0xFFFF, sum = 0
1620 22:57:53.091208 5, 0xFFFF, sum = 0
1621 22:57:53.091308 6, 0xFFFF, sum = 0
1622 22:57:53.094608 7, 0xFFFF, sum = 0
1623 22:57:53.097518 8, 0xFFFF, sum = 0
1624 22:57:53.097657 9, 0x0, sum = 1
1625 22:57:53.097728 10, 0x0, sum = 2
1626 22:57:53.101081 11, 0x0, sum = 3
1627 22:57:53.101176 12, 0x0, sum = 4
1628 22:57:53.104485 best_step = 10
1629 22:57:53.104587
1630 22:57:53.104653 ==
1631 22:57:53.108066 Dram Type= 6, Freq= 0, CH_1, rank 0
1632 22:57:53.111376 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1633 22:57:53.111486 ==
1634 22:57:53.114227 RX Vref Scan: 1
1635 22:57:53.114362
1636 22:57:53.114461 Set Vref Range= 32 -> 127
1637 22:57:53.117499
1638 22:57:53.117649 RX Vref 32 -> 127, step: 1
1639 22:57:53.117719
1640 22:57:53.121087 RX Delay -79 -> 252, step: 8
1641 22:57:53.121181
1642 22:57:53.124120 Set Vref, RX VrefLevel [Byte0]: 32
1643 22:57:53.127624 [Byte1]: 32
1644 22:57:53.127735
1645 22:57:53.130949 Set Vref, RX VrefLevel [Byte0]: 33
1646 22:57:53.134293 [Byte1]: 33
1647 22:57:53.138107
1648 22:57:53.138225 Set Vref, RX VrefLevel [Byte0]: 34
1649 22:57:53.141496 [Byte1]: 34
1650 22:57:53.146001
1651 22:57:53.146129 Set Vref, RX VrefLevel [Byte0]: 35
1652 22:57:53.148604 [Byte1]: 35
1653 22:57:53.153080
1654 22:57:53.153197 Set Vref, RX VrefLevel [Byte0]: 36
1655 22:57:53.156490 [Byte1]: 36
1656 22:57:53.160554
1657 22:57:53.160683 Set Vref, RX VrefLevel [Byte0]: 37
1658 22:57:53.163947 [Byte1]: 37
1659 22:57:53.168393
1660 22:57:53.168509 Set Vref, RX VrefLevel [Byte0]: 38
1661 22:57:53.171761 [Byte1]: 38
1662 22:57:53.175959
1663 22:57:53.176128 Set Vref, RX VrefLevel [Byte0]: 39
1664 22:57:53.178742 [Byte1]: 39
1665 22:57:53.183216
1666 22:57:53.183326 Set Vref, RX VrefLevel [Byte0]: 40
1667 22:57:53.186637 [Byte1]: 40
1668 22:57:53.191300
1669 22:57:53.191431 Set Vref, RX VrefLevel [Byte0]: 41
1670 22:57:53.193994 [Byte1]: 41
1671 22:57:53.198569
1672 22:57:53.198686 Set Vref, RX VrefLevel [Byte0]: 42
1673 22:57:53.201813 [Byte1]: 42
1674 22:57:53.206030
1675 22:57:53.206146 Set Vref, RX VrefLevel [Byte0]: 43
1676 22:57:53.209401 [Byte1]: 43
1677 22:57:53.213810
1678 22:57:53.213934 Set Vref, RX VrefLevel [Byte0]: 44
1679 22:57:53.217163 [Byte1]: 44
1680 22:57:53.220723
1681 22:57:53.220850 Set Vref, RX VrefLevel [Byte0]: 45
1682 22:57:53.224429 [Byte1]: 45
1683 22:57:53.228708
1684 22:57:53.228842 Set Vref, RX VrefLevel [Byte0]: 46
1685 22:57:53.231921 [Byte1]: 46
1686 22:57:53.236223
1687 22:57:53.236348 Set Vref, RX VrefLevel [Byte0]: 47
1688 22:57:53.239351 [Byte1]: 47
1689 22:57:53.243706
1690 22:57:53.243829 Set Vref, RX VrefLevel [Byte0]: 48
1691 22:57:53.246920 [Byte1]: 48
1692 22:57:53.251449
1693 22:57:53.251572 Set Vref, RX VrefLevel [Byte0]: 49
1694 22:57:53.254563 [Byte1]: 49
1695 22:57:53.258630
1696 22:57:53.258746 Set Vref, RX VrefLevel [Byte0]: 50
1697 22:57:53.261931 [Byte1]: 50
1698 22:57:53.266324
1699 22:57:53.266443 Set Vref, RX VrefLevel [Byte0]: 51
1700 22:57:53.269673 [Byte1]: 51
1701 22:57:53.274218
1702 22:57:53.274342 Set Vref, RX VrefLevel [Byte0]: 52
1703 22:57:53.277049 [Byte1]: 52
1704 22:57:53.281257
1705 22:57:53.281371 Set Vref, RX VrefLevel [Byte0]: 53
1706 22:57:53.284924 [Byte1]: 53
1707 22:57:53.289058
1708 22:57:53.289177 Set Vref, RX VrefLevel [Byte0]: 54
1709 22:57:53.292682 [Byte1]: 54
1710 22:57:53.296350
1711 22:57:53.296572 Set Vref, RX VrefLevel [Byte0]: 55
1712 22:57:53.300057 [Byte1]: 55
1713 22:57:53.304143
1714 22:57:53.304260 Set Vref, RX VrefLevel [Byte0]: 56
1715 22:57:53.307196 [Byte1]: 56
1716 22:57:53.311692
1717 22:57:53.311821 Set Vref, RX VrefLevel [Byte0]: 57
1718 22:57:53.314595 [Byte1]: 57
1719 22:57:53.319425
1720 22:57:53.319557 Set Vref, RX VrefLevel [Byte0]: 58
1721 22:57:53.322314 [Byte1]: 58
1722 22:57:53.326911
1723 22:57:53.327036 Set Vref, RX VrefLevel [Byte0]: 59
1724 22:57:53.329627 [Byte1]: 59
1725 22:57:53.334471
1726 22:57:53.334597 Set Vref, RX VrefLevel [Byte0]: 60
1727 22:57:53.337217 [Byte1]: 60
1728 22:57:53.341867
1729 22:57:53.342034 Set Vref, RX VrefLevel [Byte0]: 61
1730 22:57:53.347894 [Byte1]: 61
1731 22:57:53.348059
1732 22:57:53.351288 Set Vref, RX VrefLevel [Byte0]: 62
1733 22:57:53.354836 [Byte1]: 62
1734 22:57:53.354972
1735 22:57:53.358084 Set Vref, RX VrefLevel [Byte0]: 63
1736 22:57:53.361496 [Byte1]: 63
1737 22:57:53.361646
1738 22:57:53.364877 Set Vref, RX VrefLevel [Byte0]: 64
1739 22:57:53.368171 [Byte1]: 64
1740 22:57:53.372013
1741 22:57:53.372159 Set Vref, RX VrefLevel [Byte0]: 65
1742 22:57:53.374991 [Byte1]: 65
1743 22:57:53.379538
1744 22:57:53.379702 Set Vref, RX VrefLevel [Byte0]: 66
1745 22:57:53.382873 [Byte1]: 66
1746 22:57:53.387362
1747 22:57:53.387522 Set Vref, RX VrefLevel [Byte0]: 67
1748 22:57:53.390016 [Byte1]: 67
1749 22:57:53.394823
1750 22:57:53.394959 Set Vref, RX VrefLevel [Byte0]: 68
1751 22:57:53.398024 [Byte1]: 68
1752 22:57:53.402027
1753 22:57:53.402160 Set Vref, RX VrefLevel [Byte0]: 69
1754 22:57:53.405557 [Byte1]: 69
1755 22:57:53.409561
1756 22:57:53.409749 Set Vref, RX VrefLevel [Byte0]: 70
1757 22:57:53.412940 [Byte1]: 70
1758 22:57:53.417324
1759 22:57:53.417480 Set Vref, RX VrefLevel [Byte0]: 71
1760 22:57:53.420575 [Byte1]: 71
1761 22:57:53.425005
1762 22:57:53.425157 Final RX Vref Byte 0 = 59 to rank0
1763 22:57:53.428224 Final RX Vref Byte 1 = 57 to rank0
1764 22:57:53.431255 Final RX Vref Byte 0 = 59 to rank1
1765 22:57:53.434551 Final RX Vref Byte 1 = 57 to rank1==
1766 22:57:53.437901 Dram Type= 6, Freq= 0, CH_1, rank 0
1767 22:57:53.444820 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1768 22:57:53.444968 ==
1769 22:57:53.445070 DQS Delay:
1770 22:57:53.445153 DQS0 = 0, DQS1 = 0
1771 22:57:53.447787 DQM Delay:
1772 22:57:53.447876 DQM0 = 96, DQM1 = 90
1773 22:57:53.451556 DQ Delay:
1774 22:57:53.455062 DQ0 =100, DQ1 =88, DQ2 =84, DQ3 =88
1775 22:57:53.458203 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =96
1776 22:57:53.461783 DQ8 =80, DQ9 =84, DQ10 =88, DQ11 =84
1777 22:57:53.465176 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
1778 22:57:53.465289
1779 22:57:53.465356
1780 22:57:53.471234 [DQSOSCAuto] RK0, (LSB)MR18= 0x2f4c, (MSB)MR19= 0x606, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
1781 22:57:53.475125 CH1 RK0: MR19=606, MR18=2F4C
1782 22:57:53.481690 CH1_RK0: MR19=0x606, MR18=0x2F4C, DQSOSC=390, MR23=63, INC=97, DEC=64
1783 22:57:53.481834
1784 22:57:53.484544 ----->DramcWriteLeveling(PI) begin...
1785 22:57:53.484637 ==
1786 22:57:53.487920 Dram Type= 6, Freq= 0, CH_1, rank 1
1787 22:57:53.491529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1788 22:57:53.491652 ==
1789 22:57:53.494647 Write leveling (Byte 0): 29 => 29
1790 22:57:53.498132 Write leveling (Byte 1): 28 => 28
1791 22:57:53.501407 DramcWriteLeveling(PI) end<-----
1792 22:57:53.501513
1793 22:57:53.501608 ==
1794 22:57:53.504536 Dram Type= 6, Freq= 0, CH_1, rank 1
1795 22:57:53.508013 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1796 22:57:53.508120 ==
1797 22:57:53.511314 [Gating] SW mode calibration
1798 22:57:53.518103 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1799 22:57:53.524973 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1800 22:57:53.528215 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1801 22:57:53.531252 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1802 22:57:53.538075 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1803 22:57:53.541337 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1804 22:57:53.544695 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1805 22:57:53.551296 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1806 22:57:53.554941 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1807 22:57:53.558270 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1808 22:57:53.565026 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1809 22:57:53.568369 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1810 22:57:53.571526 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1811 22:57:53.578701 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1812 22:57:53.581495 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1813 22:57:53.584817 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1814 22:57:53.588141 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 22:57:53.594960 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 22:57:53.598496 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1817 22:57:53.601682 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 1)
1818 22:57:53.608163 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1819 22:57:53.611558 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 22:57:53.614936 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 22:57:53.621685 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 22:57:53.625282 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 22:57:53.628314 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 22:57:53.635514 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 22:57:53.638857 0 9 4 | B1->B0 | 2b2b 2323 | 1 0 | (0 0) (0 0)
1826 22:57:53.642361 0 9 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
1827 22:57:53.644964 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1828 22:57:53.651891 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1829 22:57:53.655180 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1830 22:57:53.658451 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1831 22:57:53.665415 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1832 22:57:53.668750 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (0 0) (1 1)
1833 22:57:53.672177 0 10 4 | B1->B0 | 2a2a 3232 | 0 0 | (1 1) (0 1)
1834 22:57:53.678573 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 22:57:53.681921 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 22:57:53.685159 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 22:57:53.691606 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 22:57:53.695253 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 22:57:53.698820 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 22:57:53.705546 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 22:57:53.708606 0 11 4 | B1->B0 | 3737 2d2d | 0 0 | (0 0) (0 0)
1842 22:57:53.711821 0 11 8 | B1->B0 | 4646 4040 | 0 1 | (0 0) (0 0)
1843 22:57:53.718719 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1844 22:57:53.721957 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1845 22:57:53.725742 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1846 22:57:53.729221 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1847 22:57:53.735301 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1848 22:57:53.738566 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1849 22:57:53.742275 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1850 22:57:53.748816 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1851 22:57:53.752131 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1852 22:57:53.755538 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1853 22:57:53.761959 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1854 22:57:53.765801 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1855 22:57:53.768940 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1856 22:57:53.775283 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1857 22:57:53.778862 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1858 22:57:53.782021 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1859 22:57:53.788733 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1860 22:57:53.792116 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1861 22:57:53.795557 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1862 22:57:53.802599 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1863 22:57:53.806056 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 22:57:53.809049 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1865 22:57:53.812383 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1866 22:57:53.818772 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1867 22:57:53.822155 Total UI for P1: 0, mck2ui 16
1868 22:57:53.825426 best dqsien dly found for B0: ( 0, 14, 4)
1869 22:57:53.829127 Total UI for P1: 0, mck2ui 16
1870 22:57:53.832336 best dqsien dly found for B1: ( 0, 14, 2)
1871 22:57:53.835524 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1872 22:57:53.839153 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1873 22:57:53.839278
1874 22:57:53.842590 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1875 22:57:53.845507 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1876 22:57:53.849234 [Gating] SW calibration Done
1877 22:57:53.849388 ==
1878 22:57:53.852560 Dram Type= 6, Freq= 0, CH_1, rank 1
1879 22:57:53.856065 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1880 22:57:53.856223 ==
1881 22:57:53.859138 RX Vref Scan: 0
1882 22:57:53.859277
1883 22:57:53.859378 RX Vref 0 -> 0, step: 1
1884 22:57:53.859474
1885 22:57:53.862610 RX Delay -130 -> 252, step: 16
1886 22:57:53.866039 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1887 22:57:53.872695 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1888 22:57:53.875547 iDelay=222, Bit 2, Center 85 (-18 ~ 189) 208
1889 22:57:53.879487 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1890 22:57:53.882716 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1891 22:57:53.886229 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1892 22:57:53.892592 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1893 22:57:53.895663 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1894 22:57:53.899081 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1895 22:57:53.902751 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1896 22:57:53.905808 iDelay=222, Bit 10, Center 93 (-18 ~ 205) 224
1897 22:57:53.912594 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1898 22:57:53.915573 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1899 22:57:53.918842 iDelay=222, Bit 13, Center 101 (-2 ~ 205) 208
1900 22:57:53.922236 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1901 22:57:53.925565 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1902 22:57:53.929246 ==
1903 22:57:53.932724 Dram Type= 6, Freq= 0, CH_1, rank 1
1904 22:57:53.935538 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1905 22:57:53.935660 ==
1906 22:57:53.935754 DQS Delay:
1907 22:57:53.939194 DQS0 = 0, DQS1 = 0
1908 22:57:53.939311 DQM Delay:
1909 22:57:53.942297 DQM0 = 93, DQM1 = 89
1910 22:57:53.942398 DQ Delay:
1911 22:57:53.945709 DQ0 =101, DQ1 =85, DQ2 =85, DQ3 =85
1912 22:57:53.948953 DQ4 =85, DQ5 =109, DQ6 =101, DQ7 =93
1913 22:57:53.952206 DQ8 =77, DQ9 =77, DQ10 =93, DQ11 =85
1914 22:57:53.955565 DQ12 =93, DQ13 =101, DQ14 =93, DQ15 =93
1915 22:57:53.955687
1916 22:57:53.955780
1917 22:57:53.955861 ==
1918 22:57:53.959103 Dram Type= 6, Freq= 0, CH_1, rank 1
1919 22:57:53.962551 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1920 22:57:53.962683 ==
1921 22:57:53.962777
1922 22:57:53.962858
1923 22:57:53.965565 TX Vref Scan disable
1924 22:57:53.968970 == TX Byte 0 ==
1925 22:57:53.972385 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1926 22:57:53.975961 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1927 22:57:53.979024 == TX Byte 1 ==
1928 22:57:53.982300 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1929 22:57:53.985710 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1930 22:57:53.985826 ==
1931 22:57:53.989121 Dram Type= 6, Freq= 0, CH_1, rank 1
1932 22:57:53.992263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1933 22:57:53.995667 ==
1934 22:57:54.007820 TX Vref=22, minBit 1, minWin=27, winSum=441
1935 22:57:54.011034 TX Vref=24, minBit 1, minWin=27, winSum=448
1936 22:57:54.013970 TX Vref=26, minBit 1, minWin=27, winSum=452
1937 22:57:54.018102 TX Vref=28, minBit 2, minWin=27, winSum=454
1938 22:57:54.020866 TX Vref=30, minBit 3, minWin=27, winSum=454
1939 22:57:54.023870 TX Vref=32, minBit 1, minWin=27, winSum=450
1940 22:57:54.030735 [TxChooseVref] Worse bit 2, Min win 27, Win sum 454, Final Vref 28
1941 22:57:54.030959
1942 22:57:54.034318 Final TX Range 1 Vref 28
1943 22:57:54.034437
1944 22:57:54.034530 ==
1945 22:57:54.037518 Dram Type= 6, Freq= 0, CH_1, rank 1
1946 22:57:54.040724 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1947 22:57:54.040840 ==
1948 22:57:54.040931
1949 22:57:54.041013
1950 22:57:54.044137 TX Vref Scan disable
1951 22:57:54.047690 == TX Byte 0 ==
1952 22:57:54.050921 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1953 22:57:54.054331 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1954 22:57:54.057329 == TX Byte 1 ==
1955 22:57:54.060848 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1956 22:57:54.064119 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1957 22:57:54.064257
1958 22:57:54.067628 [DATLAT]
1959 22:57:54.067749 Freq=800, CH1 RK1
1960 22:57:54.067843
1961 22:57:54.071316 DATLAT Default: 0xa
1962 22:57:54.071432 0, 0xFFFF, sum = 0
1963 22:57:54.074385 1, 0xFFFF, sum = 0
1964 22:57:54.074496 2, 0xFFFF, sum = 0
1965 22:57:54.077613 3, 0xFFFF, sum = 0
1966 22:57:54.077765 4, 0xFFFF, sum = 0
1967 22:57:54.080854 5, 0xFFFF, sum = 0
1968 22:57:54.080960 6, 0xFFFF, sum = 0
1969 22:57:54.084138 7, 0xFFFF, sum = 0
1970 22:57:54.084244 8, 0xFFFF, sum = 0
1971 22:57:54.087813 9, 0x0, sum = 1
1972 22:57:54.087922 10, 0x0, sum = 2
1973 22:57:54.090917 11, 0x0, sum = 3
1974 22:57:54.091030 12, 0x0, sum = 4
1975 22:57:54.094138 best_step = 10
1976 22:57:54.094246
1977 22:57:54.094313 ==
1978 22:57:54.097301 Dram Type= 6, Freq= 0, CH_1, rank 1
1979 22:57:54.100760 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1980 22:57:54.100879 ==
1981 22:57:54.104451 RX Vref Scan: 0
1982 22:57:54.104569
1983 22:57:54.104663 RX Vref 0 -> 0, step: 1
1984 22:57:54.104745
1985 22:57:54.107305 RX Delay -79 -> 252, step: 8
1986 22:57:54.114038 iDelay=209, Bit 0, Center 104 (9 ~ 200) 192
1987 22:57:54.117354 iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200
1988 22:57:54.120703 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
1989 22:57:54.124280 iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200
1990 22:57:54.127492 iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200
1991 22:57:54.131056 iDelay=209, Bit 5, Center 112 (17 ~ 208) 192
1992 22:57:54.134311 iDelay=209, Bit 6, Center 108 (9 ~ 208) 200
1993 22:57:54.141126 iDelay=209, Bit 7, Center 96 (-7 ~ 200) 208
1994 22:57:54.144195 iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208
1995 22:57:54.147631 iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208
1996 22:57:54.151155 iDelay=209, Bit 10, Center 88 (-15 ~ 192) 208
1997 22:57:54.154837 iDelay=209, Bit 11, Center 88 (-15 ~ 192) 208
1998 22:57:54.161010 iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216
1999 22:57:54.164331 iDelay=209, Bit 13, Center 96 (-7 ~ 200) 208
2000 22:57:54.167897 iDelay=209, Bit 14, Center 96 (-7 ~ 200) 208
2001 22:57:54.171116 iDelay=209, Bit 15, Center 100 (-7 ~ 208) 216
2002 22:57:54.171265 ==
2003 22:57:54.174716 Dram Type= 6, Freq= 0, CH_1, rank 1
2004 22:57:54.181032 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2005 22:57:54.181188 ==
2006 22:57:54.181285 DQS Delay:
2007 22:57:54.181368 DQS0 = 0, DQS1 = 0
2008 22:57:54.184243 DQM Delay:
2009 22:57:54.184354 DQM0 = 97, DQM1 = 91
2010 22:57:54.187743 DQ Delay:
2011 22:57:54.191202 DQ0 =104, DQ1 =92, DQ2 =84, DQ3 =92
2012 22:57:54.194345 DQ4 =92, DQ5 =112, DQ6 =108, DQ7 =96
2013 22:57:54.197653 DQ8 =80, DQ9 =80, DQ10 =88, DQ11 =88
2014 22:57:54.201016 DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =100
2015 22:57:54.201162
2016 22:57:54.201264
2017 22:57:54.207949 [DQSOSCAuto] RK1, (LSB)MR18= 0x440e, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 392 ps
2018 22:57:54.211144 CH1 RK1: MR19=606, MR18=440E
2019 22:57:54.217903 CH1_RK1: MR19=0x606, MR18=0x440E, DQSOSC=392, MR23=63, INC=96, DEC=64
2020 22:57:54.221388 [RxdqsGatingPostProcess] freq 800
2021 22:57:54.224665 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2022 22:57:54.228285 Pre-setting of DQS Precalculation
2023 22:57:54.234337 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2024 22:57:54.241082 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2025 22:57:54.247936 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2026 22:57:54.248126
2027 22:57:54.248234
2028 22:57:54.251657 [Calibration Summary] 1600 Mbps
2029 22:57:54.251789 CH 0, Rank 0
2030 22:57:54.254891 SW Impedance : PASS
2031 22:57:54.258212 DUTY Scan : NO K
2032 22:57:54.258382 ZQ Calibration : PASS
2033 22:57:54.261203 Jitter Meter : NO K
2034 22:57:54.264680 CBT Training : PASS
2035 22:57:54.264847 Write leveling : PASS
2036 22:57:54.267779 RX DQS gating : PASS
2037 22:57:54.271522 RX DQ/DQS(RDDQC) : PASS
2038 22:57:54.271681 TX DQ/DQS : PASS
2039 22:57:54.274803 RX DATLAT : PASS
2040 22:57:54.274939 RX DQ/DQS(Engine): PASS
2041 22:57:54.278015 TX OE : NO K
2042 22:57:54.278147 All Pass.
2043 22:57:54.278249
2044 22:57:54.281205 CH 0, Rank 1
2045 22:57:54.281326 SW Impedance : PASS
2046 22:57:54.284947 DUTY Scan : NO K
2047 22:57:54.287911 ZQ Calibration : PASS
2048 22:57:54.288049 Jitter Meter : NO K
2049 22:57:54.291267 CBT Training : PASS
2050 22:57:54.295006 Write leveling : PASS
2051 22:57:54.295175 RX DQS gating : PASS
2052 22:57:54.298193 RX DQ/DQS(RDDQC) : PASS
2053 22:57:54.301817 TX DQ/DQS : PASS
2054 22:57:54.301978 RX DATLAT : PASS
2055 22:57:54.304596 RX DQ/DQS(Engine): PASS
2056 22:57:54.304724 TX OE : NO K
2057 22:57:54.307862 All Pass.
2058 22:57:54.308010
2059 22:57:54.308114 CH 1, Rank 0
2060 22:57:54.311494 SW Impedance : PASS
2061 22:57:54.314601 DUTY Scan : NO K
2062 22:57:54.314754 ZQ Calibration : PASS
2063 22:57:54.318193 Jitter Meter : NO K
2064 22:57:54.318337 CBT Training : PASS
2065 22:57:54.321366 Write leveling : PASS
2066 22:57:54.324943 RX DQS gating : PASS
2067 22:57:54.325111 RX DQ/DQS(RDDQC) : PASS
2068 22:57:54.328301 TX DQ/DQS : PASS
2069 22:57:54.331889 RX DATLAT : PASS
2070 22:57:54.332033 RX DQ/DQS(Engine): PASS
2071 22:57:54.334906 TX OE : NO K
2072 22:57:54.335036 All Pass.
2073 22:57:54.335135
2074 22:57:54.338193 CH 1, Rank 1
2075 22:57:54.338313 SW Impedance : PASS
2076 22:57:54.341445 DUTY Scan : NO K
2077 22:57:54.345194 ZQ Calibration : PASS
2078 22:57:54.345334 Jitter Meter : NO K
2079 22:57:54.348380 CBT Training : PASS
2080 22:57:54.348505 Write leveling : PASS
2081 22:57:54.351242 RX DQS gating : PASS
2082 22:57:54.354842 RX DQ/DQS(RDDQC) : PASS
2083 22:57:54.354986 TX DQ/DQS : PASS
2084 22:57:54.358254 RX DATLAT : PASS
2085 22:57:54.361344 RX DQ/DQS(Engine): PASS
2086 22:57:54.361503 TX OE : NO K
2087 22:57:54.364719 All Pass.
2088 22:57:54.364849
2089 22:57:54.364950 DramC Write-DBI off
2090 22:57:54.368203 PER_BANK_REFRESH: Hybrid Mode
2091 22:57:54.368335 TX_TRACKING: ON
2092 22:57:54.371600 [GetDramInforAfterCalByMRR] Vendor 6.
2093 22:57:54.378524 [GetDramInforAfterCalByMRR] Revision 606.
2094 22:57:54.381464 [GetDramInforAfterCalByMRR] Revision 2 0.
2095 22:57:54.381662 MR0 0x3b3b
2096 22:57:54.381767 MR8 0x5151
2097 22:57:54.384961 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2098 22:57:54.385095
2099 22:57:54.388111 MR0 0x3b3b
2100 22:57:54.388258 MR8 0x5151
2101 22:57:54.391622 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2102 22:57:54.391773
2103 22:57:54.401524 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2104 22:57:54.405319 [FAST_K] Save calibration result to emmc
2105 22:57:54.408068 [FAST_K] Save calibration result to emmc
2106 22:57:54.411701 dram_init: config_dvfs: 1
2107 22:57:54.415232 dramc_set_vcore_voltage set vcore to 662500
2108 22:57:54.418480 Read voltage for 1200, 2
2109 22:57:54.418640 Vio18 = 0
2110 22:57:54.418741 Vcore = 662500
2111 22:57:54.421866 Vdram = 0
2112 22:57:54.421994 Vddq = 0
2113 22:57:54.422092 Vmddr = 0
2114 22:57:54.428248 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2115 22:57:54.431647 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2116 22:57:54.435142 MEM_TYPE=3, freq_sel=15
2117 22:57:54.438512 sv_algorithm_assistance_LP4_1600
2118 22:57:54.442192 ============ PULL DRAM RESETB DOWN ============
2119 22:57:54.445439 ========== PULL DRAM RESETB DOWN end =========
2120 22:57:54.451488 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2121 22:57:54.455409 ===================================
2122 22:57:54.455577 LPDDR4 DRAM CONFIGURATION
2123 22:57:54.458062 ===================================
2124 22:57:54.461635 EX_ROW_EN[0] = 0x0
2125 22:57:54.465030 EX_ROW_EN[1] = 0x0
2126 22:57:54.465178 LP4Y_EN = 0x0
2127 22:57:54.468250 WORK_FSP = 0x0
2128 22:57:54.468381 WL = 0x4
2129 22:57:54.471629 RL = 0x4
2130 22:57:54.471784 BL = 0x2
2131 22:57:54.475014 RPST = 0x0
2132 22:57:54.475144 RD_PRE = 0x0
2133 22:57:54.478355 WR_PRE = 0x1
2134 22:57:54.478494 WR_PST = 0x0
2135 22:57:54.481806 DBI_WR = 0x0
2136 22:57:54.481943 DBI_RD = 0x0
2137 22:57:54.484905 OTF = 0x1
2138 22:57:54.488234 ===================================
2139 22:57:54.491782 ===================================
2140 22:57:54.491954 ANA top config
2141 22:57:54.494788 ===================================
2142 22:57:54.498427 DLL_ASYNC_EN = 0
2143 22:57:54.501745 ALL_SLAVE_EN = 0
2144 22:57:54.501902 NEW_RANK_MODE = 1
2145 22:57:54.505134 DLL_IDLE_MODE = 1
2146 22:57:54.508251 LP45_APHY_COMB_EN = 1
2147 22:57:54.512063 TX_ODT_DIS = 1
2148 22:57:54.515136 NEW_8X_MODE = 1
2149 22:57:54.515290 ===================================
2150 22:57:54.518726 ===================================
2151 22:57:54.521941 data_rate = 2400
2152 22:57:54.525350 CKR = 1
2153 22:57:54.528548 DQ_P2S_RATIO = 8
2154 22:57:54.531643 ===================================
2155 22:57:54.535286 CA_P2S_RATIO = 8
2156 22:57:54.538610 DQ_CA_OPEN = 0
2157 22:57:54.542098 DQ_SEMI_OPEN = 0
2158 22:57:54.542248 CA_SEMI_OPEN = 0
2159 22:57:54.545488 CA_FULL_RATE = 0
2160 22:57:54.548666 DQ_CKDIV4_EN = 0
2161 22:57:54.551591 CA_CKDIV4_EN = 0
2162 22:57:54.554978 CA_PREDIV_EN = 0
2163 22:57:54.555122 PH8_DLY = 17
2164 22:57:54.558278 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2165 22:57:54.562278 DQ_AAMCK_DIV = 4
2166 22:57:54.564954 CA_AAMCK_DIV = 4
2167 22:57:54.569009 CA_ADMCK_DIV = 4
2168 22:57:54.571625 DQ_TRACK_CA_EN = 0
2169 22:57:54.574934 CA_PICK = 1200
2170 22:57:54.575089 CA_MCKIO = 1200
2171 22:57:54.578498 MCKIO_SEMI = 0
2172 22:57:54.581612 PLL_FREQ = 2366
2173 22:57:54.585276 DQ_UI_PI_RATIO = 32
2174 22:57:54.588568 CA_UI_PI_RATIO = 0
2175 22:57:54.591717 ===================================
2176 22:57:54.594953 ===================================
2177 22:57:54.598233 memory_type:LPDDR4
2178 22:57:54.598384 GP_NUM : 10
2179 22:57:54.601831 SRAM_EN : 1
2180 22:57:54.601978 MD32_EN : 0
2181 22:57:54.605153 ===================================
2182 22:57:54.608585 [ANA_INIT] >>>>>>>>>>>>>>
2183 22:57:54.611705 <<<<<< [CONFIGURE PHASE]: ANA_TX
2184 22:57:54.615160 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2185 22:57:54.618302 ===================================
2186 22:57:54.622186 data_rate = 2400,PCW = 0X5b00
2187 22:57:54.625481 ===================================
2188 22:57:54.628382 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2189 22:57:54.631694 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2190 22:57:54.638451 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2191 22:57:54.641921 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2192 22:57:54.645117 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2193 22:57:54.651684 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2194 22:57:54.651880 [ANA_INIT] flow start
2195 22:57:54.654950 [ANA_INIT] PLL >>>>>>>>
2196 22:57:54.655098 [ANA_INIT] PLL <<<<<<<<
2197 22:57:54.658638 [ANA_INIT] MIDPI >>>>>>>>
2198 22:57:54.661803 [ANA_INIT] MIDPI <<<<<<<<
2199 22:57:54.665358 [ANA_INIT] DLL >>>>>>>>
2200 22:57:54.665518 [ANA_INIT] DLL <<<<<<<<
2201 22:57:54.668577 [ANA_INIT] flow end
2202 22:57:54.671854 ============ LP4 DIFF to SE enter ============
2203 22:57:54.675400 ============ LP4 DIFF to SE exit ============
2204 22:57:54.678729 [ANA_INIT] <<<<<<<<<<<<<
2205 22:57:54.681881 [Flow] Enable top DCM control >>>>>
2206 22:57:54.685212 [Flow] Enable top DCM control <<<<<
2207 22:57:54.688417 Enable DLL master slave shuffle
2208 22:57:54.695573 ==============================================================
2209 22:57:54.695763 Gating Mode config
2210 22:57:54.702019 ==============================================================
2211 22:57:54.702158 Config description:
2212 22:57:54.712251 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2213 22:57:54.719169 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2214 22:57:54.725296 SELPH_MODE 0: By rank 1: By Phase
2215 22:57:54.728965 ==============================================================
2216 22:57:54.732121 GAT_TRACK_EN = 1
2217 22:57:54.735382 RX_GATING_MODE = 2
2218 22:57:54.738627 RX_GATING_TRACK_MODE = 2
2219 22:57:54.742113 SELPH_MODE = 1
2220 22:57:54.745205 PICG_EARLY_EN = 1
2221 22:57:54.748487 VALID_LAT_VALUE = 1
2222 22:57:54.751799 ==============================================================
2223 22:57:54.755267 Enter into Gating configuration >>>>
2224 22:57:54.758955 Exit from Gating configuration <<<<
2225 22:57:54.761756 Enter into DVFS_PRE_config >>>>>
2226 22:57:54.775485 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2227 22:57:54.775688 Exit from DVFS_PRE_config <<<<<
2228 22:57:54.779124 Enter into PICG configuration >>>>
2229 22:57:54.781889 Exit from PICG configuration <<<<
2230 22:57:54.785521 [RX_INPUT] configuration >>>>>
2231 22:57:54.788556 [RX_INPUT] configuration <<<<<
2232 22:57:54.795327 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2233 22:57:54.798927 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2234 22:57:54.805481 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2235 22:57:54.812470 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2236 22:57:54.818729 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2237 22:57:54.825962 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2238 22:57:54.829161 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2239 22:57:54.832287 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2240 22:57:54.835960 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2241 22:57:54.839338 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2242 22:57:54.845397 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2243 22:57:54.848838 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2244 22:57:54.852260 ===================================
2245 22:57:54.855596 LPDDR4 DRAM CONFIGURATION
2246 22:57:54.859277 ===================================
2247 22:57:54.859449 EX_ROW_EN[0] = 0x0
2248 22:57:54.862528 EX_ROW_EN[1] = 0x0
2249 22:57:54.862673 LP4Y_EN = 0x0
2250 22:57:54.865423 WORK_FSP = 0x0
2251 22:57:54.865555 WL = 0x4
2252 22:57:54.869200 RL = 0x4
2253 22:57:54.869353 BL = 0x2
2254 22:57:54.872209 RPST = 0x0
2255 22:57:54.875576 RD_PRE = 0x0
2256 22:57:54.875722 WR_PRE = 0x1
2257 22:57:54.878697 WR_PST = 0x0
2258 22:57:54.878827 DBI_WR = 0x0
2259 22:57:54.882242 DBI_RD = 0x0
2260 22:57:54.882378 OTF = 0x1
2261 22:57:54.885718 ===================================
2262 22:57:54.888875 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2263 22:57:54.892671 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2264 22:57:54.899141 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2265 22:57:54.902757 ===================================
2266 22:57:54.905491 LPDDR4 DRAM CONFIGURATION
2267 22:57:54.909183 ===================================
2268 22:57:54.909348 EX_ROW_EN[0] = 0x10
2269 22:57:54.912217 EX_ROW_EN[1] = 0x0
2270 22:57:54.912359 LP4Y_EN = 0x0
2271 22:57:54.915842 WORK_FSP = 0x0
2272 22:57:54.915991 WL = 0x4
2273 22:57:54.919337 RL = 0x4
2274 22:57:54.919484 BL = 0x2
2275 22:57:54.922161 RPST = 0x0
2276 22:57:54.922289 RD_PRE = 0x0
2277 22:57:54.925784 WR_PRE = 0x1
2278 22:57:54.925940 WR_PST = 0x0
2279 22:57:54.929329 DBI_WR = 0x0
2280 22:57:54.929480 DBI_RD = 0x0
2281 22:57:54.932515 OTF = 0x1
2282 22:57:54.935771 ===================================
2283 22:57:54.942509 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2284 22:57:54.942699 ==
2285 22:57:54.945728 Dram Type= 6, Freq= 0, CH_0, rank 0
2286 22:57:54.949242 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2287 22:57:54.949407 ==
2288 22:57:54.952474 [Duty_Offset_Calibration]
2289 22:57:54.952610 B0:2 B1:1 CA:1
2290 22:57:54.952750
2291 22:57:54.955787 [DutyScan_Calibration_Flow] k_type=0
2292 22:57:54.966059
2293 22:57:54.966260 ==CLK 0==
2294 22:57:54.969491 Final CLK duty delay cell = 0
2295 22:57:54.973027 [0] MAX Duty = 5218%(X100), DQS PI = 24
2296 22:57:54.976143 [0] MIN Duty = 4844%(X100), DQS PI = 48
2297 22:57:54.976287 [0] AVG Duty = 5031%(X100)
2298 22:57:54.979672
2299 22:57:54.979806 CH0 CLK Duty spec in!! Max-Min= 374%
2300 22:57:54.986366 [DutyScan_Calibration_Flow] ====Done====
2301 22:57:54.986552
2302 22:57:54.989257 [DutyScan_Calibration_Flow] k_type=1
2303 22:57:55.004883
2304 22:57:55.005090 ==DQS 0 ==
2305 22:57:55.007820 Final DQS duty delay cell = -4
2306 22:57:55.011303 [-4] MAX Duty = 5124%(X100), DQS PI = 22
2307 22:57:55.014781 [-4] MIN Duty = 4751%(X100), DQS PI = 62
2308 22:57:55.017824 [-4] AVG Duty = 4937%(X100)
2309 22:57:55.017979
2310 22:57:55.018079 ==DQS 1 ==
2311 22:57:55.021757 Final DQS duty delay cell = 0
2312 22:57:55.025304 [0] MAX Duty = 5156%(X100), DQS PI = 0
2313 22:57:55.027855 [0] MIN Duty = 5000%(X100), DQS PI = 32
2314 22:57:55.031750 [0] AVG Duty = 5078%(X100)
2315 22:57:55.031906
2316 22:57:55.034756 CH0 DQS 0 Duty spec in!! Max-Min= 373%
2317 22:57:55.034891
2318 22:57:55.038337 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2319 22:57:55.041282 [DutyScan_Calibration_Flow] ====Done====
2320 22:57:55.041425
2321 22:57:55.045030 [DutyScan_Calibration_Flow] k_type=3
2322 22:57:55.061670
2323 22:57:55.061871 ==DQM 0 ==
2324 22:57:55.065255 Final DQM duty delay cell = 0
2325 22:57:55.068215 [0] MAX Duty = 5156%(X100), DQS PI = 30
2326 22:57:55.071759 [0] MIN Duty = 4907%(X100), DQS PI = 58
2327 22:57:55.071904 [0] AVG Duty = 5031%(X100)
2328 22:57:55.075137
2329 22:57:55.075244 ==DQM 1 ==
2330 22:57:55.078582 Final DQM duty delay cell = 0
2331 22:57:55.081817 [0] MAX Duty = 5125%(X100), DQS PI = 60
2332 22:57:55.085276 [0] MIN Duty = 5031%(X100), DQS PI = 36
2333 22:57:55.085418 [0] AVG Duty = 5078%(X100)
2334 22:57:55.085518
2335 22:57:55.091496 CH0 DQM 0 Duty spec in!! Max-Min= 249%
2336 22:57:55.091651
2337 22:57:55.094888 CH0 DQM 1 Duty spec in!! Max-Min= 94%
2338 22:57:55.098293 [DutyScan_Calibration_Flow] ====Done====
2339 22:57:55.098438
2340 22:57:55.101570 [DutyScan_Calibration_Flow] k_type=2
2341 22:57:55.118483
2342 22:57:55.118686 ==DQ 0 ==
2343 22:57:55.121260 Final DQ duty delay cell = 0
2344 22:57:55.124738 [0] MAX Duty = 5062%(X100), DQS PI = 32
2345 22:57:55.127698 [0] MIN Duty = 4906%(X100), DQS PI = 0
2346 22:57:55.127818 [0] AVG Duty = 4984%(X100)
2347 22:57:55.131205
2348 22:57:55.131364 ==DQ 1 ==
2349 22:57:55.134665 Final DQ duty delay cell = 0
2350 22:57:55.137782 [0] MAX Duty = 5093%(X100), DQS PI = 24
2351 22:57:55.141206 [0] MIN Duty = 4938%(X100), DQS PI = 36
2352 22:57:55.141322 [0] AVG Duty = 5015%(X100)
2353 22:57:55.144881
2354 22:57:55.147926 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2355 22:57:55.148042
2356 22:57:55.151091 CH0 DQ 1 Duty spec in!! Max-Min= 155%
2357 22:57:55.154504 [DutyScan_Calibration_Flow] ====Done====
2358 22:57:55.154619 ==
2359 22:57:55.157937 Dram Type= 6, Freq= 0, CH_1, rank 0
2360 22:57:55.161109 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2361 22:57:55.161220 ==
2362 22:57:55.164672 [Duty_Offset_Calibration]
2363 22:57:55.164783 B0:1 B1:0 CA:0
2364 22:57:55.164875
2365 22:57:55.167867 [DutyScan_Calibration_Flow] k_type=0
2366 22:57:55.177550
2367 22:57:55.177745 ==CLK 0==
2368 22:57:55.180772 Final CLK duty delay cell = -4
2369 22:57:55.183989 [-4] MAX Duty = 5000%(X100), DQS PI = 18
2370 22:57:55.187613 [-4] MIN Duty = 4875%(X100), DQS PI = 50
2371 22:57:55.190839 [-4] AVG Duty = 4937%(X100)
2372 22:57:55.190960
2373 22:57:55.194636 CH1 CLK Duty spec in!! Max-Min= 125%
2374 22:57:55.197124 [DutyScan_Calibration_Flow] ====Done====
2375 22:57:55.197230
2376 22:57:55.200509 [DutyScan_Calibration_Flow] k_type=1
2377 22:57:55.217239
2378 22:57:55.217405 ==DQS 0 ==
2379 22:57:55.220596 Final DQS duty delay cell = 0
2380 22:57:55.224013 [0] MAX Duty = 5094%(X100), DQS PI = 14
2381 22:57:55.227279 [0] MIN Duty = 4875%(X100), DQS PI = 0
2382 22:57:55.227435 [0] AVG Duty = 4984%(X100)
2383 22:57:55.227527
2384 22:57:55.230345 ==DQS 1 ==
2385 22:57:55.233867 Final DQS duty delay cell = 0
2386 22:57:55.237273 [0] MAX Duty = 5218%(X100), DQS PI = 20
2387 22:57:55.240867 [0] MIN Duty = 4938%(X100), DQS PI = 58
2388 22:57:55.240987 [0] AVG Duty = 5078%(X100)
2389 22:57:55.243712
2390 22:57:55.247107 CH1 DQS 0 Duty spec in!! Max-Min= 219%
2391 22:57:55.247250
2392 22:57:55.250630 CH1 DQS 1 Duty spec in!! Max-Min= 280%
2393 22:57:55.254098 [DutyScan_Calibration_Flow] ====Done====
2394 22:57:55.254225
2395 22:57:55.257229 [DutyScan_Calibration_Flow] k_type=3
2396 22:57:55.273712
2397 22:57:55.273851 ==DQM 0 ==
2398 22:57:55.277186 Final DQM duty delay cell = 0
2399 22:57:55.280350 [0] MAX Duty = 5187%(X100), DQS PI = 10
2400 22:57:55.283904 [0] MIN Duty = 5031%(X100), DQS PI = 0
2401 22:57:55.284019 [0] AVG Duty = 5109%(X100)
2402 22:57:55.287102
2403 22:57:55.287201 ==DQM 1 ==
2404 22:57:55.290221 Final DQM duty delay cell = 0
2405 22:57:55.293960 [0] MAX Duty = 5031%(X100), DQS PI = 16
2406 22:57:55.296966 [0] MIN Duty = 4907%(X100), DQS PI = 34
2407 22:57:55.297079 [0] AVG Duty = 4969%(X100)
2408 22:57:55.300533
2409 22:57:55.303606 CH1 DQM 0 Duty spec in!! Max-Min= 156%
2410 22:57:55.303719
2411 22:57:55.306911 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2412 22:57:55.310666 [DutyScan_Calibration_Flow] ====Done====
2413 22:57:55.310783
2414 22:57:55.313940 [DutyScan_Calibration_Flow] k_type=2
2415 22:57:55.329814
2416 22:57:55.329973 ==DQ 0 ==
2417 22:57:55.332910 Final DQ duty delay cell = -4
2418 22:57:55.336578 [-4] MAX Duty = 5094%(X100), DQS PI = 10
2419 22:57:55.339698 [-4] MIN Duty = 4938%(X100), DQS PI = 0
2420 22:57:55.343265 [-4] AVG Duty = 5016%(X100)
2421 22:57:55.343383
2422 22:57:55.343453 ==DQ 1 ==
2423 22:57:55.346017 Final DQ duty delay cell = 0
2424 22:57:55.349784 [0] MAX Duty = 5125%(X100), DQS PI = 20
2425 22:57:55.353014 [0] MIN Duty = 4969%(X100), DQS PI = 32
2426 22:57:55.353127 [0] AVG Duty = 5047%(X100)
2427 22:57:55.356111
2428 22:57:55.359439 CH1 DQ 0 Duty spec in!! Max-Min= 156%
2429 22:57:55.359539
2430 22:57:55.362814 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2431 22:57:55.366218 [DutyScan_Calibration_Flow] ====Done====
2432 22:57:55.369336 nWR fixed to 30
2433 22:57:55.369465 [ModeRegInit_LP4] CH0 RK0
2434 22:57:55.372648 [ModeRegInit_LP4] CH0 RK1
2435 22:57:55.376228 [ModeRegInit_LP4] CH1 RK0
2436 22:57:55.379308 [ModeRegInit_LP4] CH1 RK1
2437 22:57:55.379424 match AC timing 7
2438 22:57:55.382786 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2439 22:57:55.389314 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2440 22:57:55.393237 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2441 22:57:55.396520 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2442 22:57:55.403292 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2443 22:57:55.403440 ==
2444 22:57:55.406896 Dram Type= 6, Freq= 0, CH_0, rank 0
2445 22:57:55.409420 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2446 22:57:55.409521 ==
2447 22:57:55.416224 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2448 22:57:55.419773 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2449 22:57:55.429829 [CA 0] Center 39 (8~70) winsize 63
2450 22:57:55.433190 [CA 1] Center 39 (8~70) winsize 63
2451 22:57:55.436725 [CA 2] Center 35 (5~66) winsize 62
2452 22:57:55.439866 [CA 3] Center 34 (4~65) winsize 62
2453 22:57:55.443506 [CA 4] Center 33 (3~64) winsize 62
2454 22:57:55.446306 [CA 5] Center 32 (3~62) winsize 60
2455 22:57:55.446416
2456 22:57:55.449506 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2457 22:57:55.449647
2458 22:57:55.452852 [CATrainingPosCal] consider 1 rank data
2459 22:57:55.456229 u2DelayCellTimex100 = 270/100 ps
2460 22:57:55.459706 CA0 delay=39 (8~70),Diff = 7 PI (33 cell)
2461 22:57:55.463162 CA1 delay=39 (8~70),Diff = 7 PI (33 cell)
2462 22:57:55.470109 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2463 22:57:55.472982 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2464 22:57:55.476174 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2465 22:57:55.479566 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2466 22:57:55.479710
2467 22:57:55.482933 CA PerBit enable=1, Macro0, CA PI delay=32
2468 22:57:55.483041
2469 22:57:55.486520 [CBTSetCACLKResult] CA Dly = 32
2470 22:57:55.486632 CS Dly: 6 (0~37)
2471 22:57:55.486700 ==
2472 22:57:55.489798 Dram Type= 6, Freq= 0, CH_0, rank 1
2473 22:57:55.496760 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2474 22:57:55.496905 ==
2475 22:57:55.499970 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2476 22:57:55.506538 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2477 22:57:55.515476 [CA 0] Center 38 (8~69) winsize 62
2478 22:57:55.518751 [CA 1] Center 38 (8~69) winsize 62
2479 22:57:55.522152 [CA 2] Center 35 (4~66) winsize 63
2480 22:57:55.525408 [CA 3] Center 34 (4~65) winsize 62
2481 22:57:55.529002 [CA 4] Center 33 (3~64) winsize 62
2482 22:57:55.532349 [CA 5] Center 32 (3~62) winsize 60
2483 22:57:55.532470
2484 22:57:55.535673 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2485 22:57:55.535778
2486 22:57:55.538719 [CATrainingPosCal] consider 2 rank data
2487 22:57:55.542113 u2DelayCellTimex100 = 270/100 ps
2488 22:57:55.545556 CA0 delay=38 (8~69),Diff = 6 PI (28 cell)
2489 22:57:55.548904 CA1 delay=38 (8~69),Diff = 6 PI (28 cell)
2490 22:57:55.555737 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2491 22:57:55.559354 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2492 22:57:55.562643 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2493 22:57:55.565595 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2494 22:57:55.565709
2495 22:57:55.568766 CA PerBit enable=1, Macro0, CA PI delay=32
2496 22:57:55.568866
2497 22:57:55.572718 [CBTSetCACLKResult] CA Dly = 32
2498 22:57:55.572825 CS Dly: 6 (0~38)
2499 22:57:55.572893
2500 22:57:55.575463 ----->DramcWriteLeveling(PI) begin...
2501 22:57:55.575556 ==
2502 22:57:55.579099 Dram Type= 6, Freq= 0, CH_0, rank 0
2503 22:57:55.585496 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2504 22:57:55.585656 ==
2505 22:57:55.588830 Write leveling (Byte 0): 35 => 35
2506 22:57:55.592368 Write leveling (Byte 1): 28 => 28
2507 22:57:55.592482 DramcWriteLeveling(PI) end<-----
2508 22:57:55.595655
2509 22:57:55.595759 ==
2510 22:57:55.599073 Dram Type= 6, Freq= 0, CH_0, rank 0
2511 22:57:55.602168 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2512 22:57:55.602285 ==
2513 22:57:55.606068 [Gating] SW mode calibration
2514 22:57:55.612478 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2515 22:57:55.615482 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2516 22:57:55.622404 0 15 0 | B1->B0 | 2323 3434 | 1 1 | (1 1) (1 1)
2517 22:57:55.625330 0 15 4 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
2518 22:57:55.628891 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2519 22:57:55.635362 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2520 22:57:55.639126 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2521 22:57:55.641912 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2522 22:57:55.648924 0 15 24 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
2523 22:57:55.651756 0 15 28 | B1->B0 | 3434 2525 | 0 1 | (0 0) (1 1)
2524 22:57:55.655336 1 0 0 | B1->B0 | 2929 2424 | 0 0 | (1 0) (0 0)
2525 22:57:55.662218 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2526 22:57:55.665348 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2527 22:57:55.668968 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2528 22:57:55.675332 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2529 22:57:55.679086 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2530 22:57:55.682243 1 0 24 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (0 0)
2531 22:57:55.688935 1 0 28 | B1->B0 | 2525 4646 | 0 0 | (0 0) (0 0)
2532 22:57:55.691764 1 1 0 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
2533 22:57:55.695699 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2534 22:57:55.701552 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2535 22:57:55.704929 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2536 22:57:55.708458 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2537 22:57:55.714914 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2538 22:57:55.718451 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2539 22:57:55.721723 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2540 22:57:55.728764 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2541 22:57:55.731751 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2542 22:57:55.735125 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2543 22:57:55.739104 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2544 22:57:55.745017 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2545 22:57:55.748201 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2546 22:57:55.751449 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2547 22:57:55.758412 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2548 22:57:55.761496 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2549 22:57:55.765106 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2550 22:57:55.772333 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2551 22:57:55.774942 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2552 22:57:55.778227 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2553 22:57:55.784770 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2554 22:57:55.788782 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2555 22:57:55.791708 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2556 22:57:55.798496 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2557 22:57:55.798642 Total UI for P1: 0, mck2ui 16
2558 22:57:55.804785 best dqsien dly found for B0: ( 1, 3, 28)
2559 22:57:55.808266 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2560 22:57:55.811698 Total UI for P1: 0, mck2ui 16
2561 22:57:55.814796 best dqsien dly found for B1: ( 1, 4, 0)
2562 22:57:55.818151 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2563 22:57:55.821499 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2564 22:57:55.821678
2565 22:57:55.824853 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2566 22:57:55.828510 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2567 22:57:55.831582 [Gating] SW calibration Done
2568 22:57:55.831693 ==
2569 22:57:55.835210 Dram Type= 6, Freq= 0, CH_0, rank 0
2570 22:57:55.838192 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2571 22:57:55.838300 ==
2572 22:57:55.842073 RX Vref Scan: 0
2573 22:57:55.842181
2574 22:57:55.844794 RX Vref 0 -> 0, step: 1
2575 22:57:55.844886
2576 22:57:55.844953 RX Delay -40 -> 252, step: 8
2577 22:57:55.851494 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2578 22:57:55.855560 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2579 22:57:55.858253 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2580 22:57:55.861817 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2581 22:57:55.864841 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2582 22:57:55.871926 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2583 22:57:55.874982 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2584 22:57:55.878463 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2585 22:57:55.881801 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2586 22:57:55.885402 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
2587 22:57:55.888124 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2588 22:57:55.895233 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2589 22:57:55.898148 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2590 22:57:55.901744 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2591 22:57:55.905030 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2592 22:57:55.911726 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2593 22:57:55.911864 ==
2594 22:57:55.915140 Dram Type= 6, Freq= 0, CH_0, rank 0
2595 22:57:55.918655 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2596 22:57:55.918778 ==
2597 22:57:55.918848 DQS Delay:
2598 22:57:55.921623 DQS0 = 0, DQS1 = 0
2599 22:57:55.921737 DQM Delay:
2600 22:57:55.925141 DQM0 = 121, DQM1 = 113
2601 22:57:55.925244 DQ Delay:
2602 22:57:55.928239 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2603 22:57:55.931549 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2604 22:57:55.936246 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
2605 22:57:55.938843 DQ12 =119, DQ13 =123, DQ14 =123, DQ15 =119
2606 22:57:55.938955
2607 22:57:55.939022
2608 22:57:55.939083 ==
2609 22:57:55.942166 Dram Type= 6, Freq= 0, CH_0, rank 0
2610 22:57:55.948601 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2611 22:57:55.948737 ==
2612 22:57:55.948811
2613 22:57:55.948873
2614 22:57:55.948932 TX Vref Scan disable
2615 22:57:55.952527 == TX Byte 0 ==
2616 22:57:55.955709 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
2617 22:57:55.958896 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
2618 22:57:55.962457 == TX Byte 1 ==
2619 22:57:55.965744 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2620 22:57:55.968985 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2621 22:57:55.971936 ==
2622 22:57:55.975398 Dram Type= 6, Freq= 0, CH_0, rank 0
2623 22:57:55.978756 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2624 22:57:55.978872 ==
2625 22:57:55.990896 TX Vref=22, minBit 0, minWin=24, winSum=403
2626 22:57:55.994121 TX Vref=24, minBit 4, minWin=24, winSum=409
2627 22:57:55.997026 TX Vref=26, minBit 4, minWin=25, winSum=417
2628 22:57:56.000455 TX Vref=28, minBit 0, minWin=26, winSum=421
2629 22:57:56.003606 TX Vref=30, minBit 0, minWin=26, winSum=424
2630 22:57:56.007099 TX Vref=32, minBit 5, minWin=25, winSum=420
2631 22:57:56.013689 [TxChooseVref] Worse bit 0, Min win 26, Win sum 424, Final Vref 30
2632 22:57:56.013814
2633 22:57:56.017095 Final TX Range 1 Vref 30
2634 22:57:56.017198
2635 22:57:56.017266 ==
2636 22:57:56.020254 Dram Type= 6, Freq= 0, CH_0, rank 0
2637 22:57:56.023598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2638 22:57:56.023714 ==
2639 22:57:56.023784
2640 22:57:56.026923
2641 22:57:56.027026 TX Vref Scan disable
2642 22:57:56.030527 == TX Byte 0 ==
2643 22:57:56.033496 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2644 22:57:56.036792 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2645 22:57:56.040474 == TX Byte 1 ==
2646 22:57:56.043938 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2647 22:57:56.047303 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2648 22:57:56.047421
2649 22:57:56.050341 [DATLAT]
2650 22:57:56.050445 Freq=1200, CH0 RK0
2651 22:57:56.050514
2652 22:57:56.053775 DATLAT Default: 0xd
2653 22:57:56.053882 0, 0xFFFF, sum = 0
2654 22:57:56.057361 1, 0xFFFF, sum = 0
2655 22:57:56.057478 2, 0xFFFF, sum = 0
2656 22:57:56.060435 3, 0xFFFF, sum = 0
2657 22:57:56.060538 4, 0xFFFF, sum = 0
2658 22:57:56.063769 5, 0xFFFF, sum = 0
2659 22:57:56.063882 6, 0xFFFF, sum = 0
2660 22:57:56.066960 7, 0xFFFF, sum = 0
2661 22:57:56.070511 8, 0xFFFF, sum = 0
2662 22:57:56.070629 9, 0xFFFF, sum = 0
2663 22:57:56.073701 10, 0xFFFF, sum = 0
2664 22:57:56.073808 11, 0xFFFF, sum = 0
2665 22:57:56.077137 12, 0x0, sum = 1
2666 22:57:56.077245 13, 0x0, sum = 2
2667 22:57:56.080350 14, 0x0, sum = 3
2668 22:57:56.080461 15, 0x0, sum = 4
2669 22:57:56.080535 best_step = 13
2670 22:57:56.080598
2671 22:57:56.083511 ==
2672 22:57:56.087229 Dram Type= 6, Freq= 0, CH_0, rank 0
2673 22:57:56.090805 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2674 22:57:56.090925 ==
2675 22:57:56.090994 RX Vref Scan: 1
2676 22:57:56.091057
2677 22:57:56.093572 Set Vref Range= 32 -> 127
2678 22:57:56.093704
2679 22:57:56.096848 RX Vref 32 -> 127, step: 1
2680 22:57:56.096959
2681 22:57:56.100327 RX Delay -13 -> 252, step: 4
2682 22:57:56.100436
2683 22:57:56.104055 Set Vref, RX VrefLevel [Byte0]: 32
2684 22:57:56.107059 [Byte1]: 32
2685 22:57:56.107175
2686 22:57:56.110083 Set Vref, RX VrefLevel [Byte0]: 33
2687 22:57:56.113553 [Byte1]: 33
2688 22:57:56.113708
2689 22:57:56.116830 Set Vref, RX VrefLevel [Byte0]: 34
2690 22:57:56.120001 [Byte1]: 34
2691 22:57:56.124751
2692 22:57:56.124903 Set Vref, RX VrefLevel [Byte0]: 35
2693 22:57:56.127731 [Byte1]: 35
2694 22:57:56.132848
2695 22:57:56.132978 Set Vref, RX VrefLevel [Byte0]: 36
2696 22:57:56.135487 [Byte1]: 36
2697 22:57:56.140508
2698 22:57:56.140630 Set Vref, RX VrefLevel [Byte0]: 37
2699 22:57:56.143745 [Byte1]: 37
2700 22:57:56.148458
2701 22:57:56.148579 Set Vref, RX VrefLevel [Byte0]: 38
2702 22:57:56.151594 [Byte1]: 38
2703 22:57:56.156238
2704 22:57:56.156358 Set Vref, RX VrefLevel [Byte0]: 39
2705 22:57:56.159572 [Byte1]: 39
2706 22:57:56.164216
2707 22:57:56.164338 Set Vref, RX VrefLevel [Byte0]: 40
2708 22:57:56.167102 [Byte1]: 40
2709 22:57:56.172111
2710 22:57:56.172249 Set Vref, RX VrefLevel [Byte0]: 41
2711 22:57:56.175218 [Byte1]: 41
2712 22:57:56.179494
2713 22:57:56.179613 Set Vref, RX VrefLevel [Byte0]: 42
2714 22:57:56.183183 [Byte1]: 42
2715 22:57:56.187760
2716 22:57:56.187881 Set Vref, RX VrefLevel [Byte0]: 43
2717 22:57:56.191085 [Byte1]: 43
2718 22:57:56.195842
2719 22:57:56.195963 Set Vref, RX VrefLevel [Byte0]: 44
2720 22:57:56.198804 [Byte1]: 44
2721 22:57:56.203317
2722 22:57:56.203433 Set Vref, RX VrefLevel [Byte0]: 45
2723 22:57:56.206596 [Byte1]: 45
2724 22:57:56.211742
2725 22:57:56.211864 Set Vref, RX VrefLevel [Byte0]: 46
2726 22:57:56.214990 [Byte1]: 46
2727 22:57:56.219513
2728 22:57:56.219633 Set Vref, RX VrefLevel [Byte0]: 47
2729 22:57:56.222541 [Byte1]: 47
2730 22:57:56.226937
2731 22:57:56.227054 Set Vref, RX VrefLevel [Byte0]: 48
2732 22:57:56.230524 [Byte1]: 48
2733 22:57:56.235024
2734 22:57:56.235156 Set Vref, RX VrefLevel [Byte0]: 49
2735 22:57:56.238557 [Byte1]: 49
2736 22:57:56.242805
2737 22:57:56.242927 Set Vref, RX VrefLevel [Byte0]: 50
2738 22:57:56.246210 [Byte1]: 50
2739 22:57:56.250786
2740 22:57:56.250906 Set Vref, RX VrefLevel [Byte0]: 51
2741 22:57:56.254100 [Byte1]: 51
2742 22:57:56.258486
2743 22:57:56.258624 Set Vref, RX VrefLevel [Byte0]: 52
2744 22:57:56.261888 [Byte1]: 52
2745 22:57:56.266528
2746 22:57:56.266658 Set Vref, RX VrefLevel [Byte0]: 53
2747 22:57:56.269849 [Byte1]: 53
2748 22:57:56.274310
2749 22:57:56.274433 Set Vref, RX VrefLevel [Byte0]: 54
2750 22:57:56.278007 [Byte1]: 54
2751 22:57:56.282099
2752 22:57:56.282214 Set Vref, RX VrefLevel [Byte0]: 55
2753 22:57:56.285877 [Byte1]: 55
2754 22:57:56.290403
2755 22:57:56.290521 Set Vref, RX VrefLevel [Byte0]: 56
2756 22:57:56.293632 [Byte1]: 56
2757 22:57:56.298052
2758 22:57:56.298180 Set Vref, RX VrefLevel [Byte0]: 57
2759 22:57:56.302098 [Byte1]: 57
2760 22:57:56.305976
2761 22:57:56.306099 Set Vref, RX VrefLevel [Byte0]: 58
2762 22:57:56.309244 [Byte1]: 58
2763 22:57:56.313683
2764 22:57:56.313810 Set Vref, RX VrefLevel [Byte0]: 59
2765 22:57:56.317492 [Byte1]: 59
2766 22:57:56.321927
2767 22:57:56.322057 Set Vref, RX VrefLevel [Byte0]: 60
2768 22:57:56.325323 [Byte1]: 60
2769 22:57:56.329700
2770 22:57:56.329825 Set Vref, RX VrefLevel [Byte0]: 61
2771 22:57:56.333209 [Byte1]: 61
2772 22:57:56.337628
2773 22:57:56.337747 Set Vref, RX VrefLevel [Byte0]: 62
2774 22:57:56.340975 [Byte1]: 62
2775 22:57:56.345432
2776 22:57:56.345552 Set Vref, RX VrefLevel [Byte0]: 63
2777 22:57:56.348726 [Byte1]: 63
2778 22:57:56.353572
2779 22:57:56.353724 Set Vref, RX VrefLevel [Byte0]: 64
2780 22:57:56.356953 [Byte1]: 64
2781 22:57:56.361268
2782 22:57:56.361392 Set Vref, RX VrefLevel [Byte0]: 65
2783 22:57:56.364400 [Byte1]: 65
2784 22:57:56.369638
2785 22:57:56.369767 Set Vref, RX VrefLevel [Byte0]: 66
2786 22:57:56.372446 [Byte1]: 66
2787 22:57:56.376790
2788 22:57:56.380622 Set Vref, RX VrefLevel [Byte0]: 67
2789 22:57:56.383557 [Byte1]: 67
2790 22:57:56.383665
2791 22:57:56.386636 Set Vref, RX VrefLevel [Byte0]: 68
2792 22:57:56.390593 [Byte1]: 68
2793 22:57:56.390706
2794 22:57:56.393391 Set Vref, RX VrefLevel [Byte0]: 69
2795 22:57:56.396968 [Byte1]: 69
2796 22:57:56.400919
2797 22:57:56.401047 Final RX Vref Byte 0 = 55 to rank0
2798 22:57:56.404327 Final RX Vref Byte 1 = 50 to rank0
2799 22:57:56.407407 Final RX Vref Byte 0 = 55 to rank1
2800 22:57:56.410972 Final RX Vref Byte 1 = 50 to rank1==
2801 22:57:56.414284 Dram Type= 6, Freq= 0, CH_0, rank 0
2802 22:57:56.420767 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2803 22:57:56.420936 ==
2804 22:57:56.421011 DQS Delay:
2805 22:57:56.421117 DQS0 = 0, DQS1 = 0
2806 22:57:56.423965 DQM Delay:
2807 22:57:56.424062 DQM0 = 120, DQM1 = 112
2808 22:57:56.427542 DQ Delay:
2809 22:57:56.430575 DQ0 =120, DQ1 =120, DQ2 =118, DQ3 =118
2810 22:57:56.434138 DQ4 =122, DQ5 =112, DQ6 =126, DQ7 =126
2811 22:57:56.437509 DQ8 =100, DQ9 =102, DQ10 =112, DQ11 =106
2812 22:57:56.440547 DQ12 =116, DQ13 =116, DQ14 =124, DQ15 =122
2813 22:57:56.440658
2814 22:57:56.440726
2815 22:57:56.447953 [DQSOSCAuto] RK0, (LSB)MR18= 0x150e, (MSB)MR19= 0x404, tDQSOscB0 = 404 ps tDQSOscB1 = 401 ps
2816 22:57:56.450925 CH0 RK0: MR19=404, MR18=150E
2817 22:57:56.457512 CH0_RK0: MR19=0x404, MR18=0x150E, DQSOSC=401, MR23=63, INC=40, DEC=27
2818 22:57:56.457693
2819 22:57:56.461049 ----->DramcWriteLeveling(PI) begin...
2820 22:57:56.461152 ==
2821 22:57:56.464369 Dram Type= 6, Freq= 0, CH_0, rank 1
2822 22:57:56.467723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2823 22:57:56.467844 ==
2824 22:57:56.470908 Write leveling (Byte 0): 34 => 34
2825 22:57:56.474597 Write leveling (Byte 1): 29 => 29
2826 22:57:56.477554 DramcWriteLeveling(PI) end<-----
2827 22:57:56.477672
2828 22:57:56.477738 ==
2829 22:57:56.480811 Dram Type= 6, Freq= 0, CH_0, rank 1
2830 22:57:56.487477 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2831 22:57:56.487606 ==
2832 22:57:56.487674 [Gating] SW mode calibration
2833 22:57:56.497778 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2834 22:57:56.501261 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2835 22:57:56.504248 0 15 0 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 1)
2836 22:57:56.511121 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2837 22:57:56.514269 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2838 22:57:56.517971 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2839 22:57:56.524461 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2840 22:57:56.527826 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2841 22:57:56.531183 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2842 22:57:56.537700 0 15 28 | B1->B0 | 2f2f 2d2d | 1 0 | (1 0) (0 0)
2843 22:57:56.541063 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2844 22:57:56.544856 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2845 22:57:56.548276 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2846 22:57:56.554796 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2847 22:57:56.558120 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2848 22:57:56.561296 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2849 22:57:56.568067 1 0 24 | B1->B0 | 2525 2525 | 0 0 | (0 0) (0 0)
2850 22:57:56.571205 1 0 28 | B1->B0 | 3939 3736 | 0 1 | (0 0) (0 0)
2851 22:57:56.574598 1 1 0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
2852 22:57:56.580871 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2853 22:57:56.584373 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2854 22:57:56.587652 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2855 22:57:56.594620 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2856 22:57:56.598228 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2857 22:57:56.601074 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2858 22:57:56.607532 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2859 22:57:56.611049 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
2860 22:57:56.614568 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2861 22:57:56.620923 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2862 22:57:56.624505 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2863 22:57:56.627632 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2864 22:57:56.634762 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2865 22:57:56.638185 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2866 22:57:56.640755 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2867 22:57:56.647880 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2868 22:57:56.651170 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2869 22:57:56.654319 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2870 22:57:56.660988 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2871 22:57:56.664315 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2872 22:57:56.667668 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2873 22:57:56.674395 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2874 22:57:56.677547 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2875 22:57:56.680998 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2876 22:57:56.684111 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2877 22:57:56.687503 Total UI for P1: 0, mck2ui 16
2878 22:57:56.690747 best dqsien dly found for B0: ( 1, 3, 30)
2879 22:57:56.694131 Total UI for P1: 0, mck2ui 16
2880 22:57:56.697286 best dqsien dly found for B1: ( 1, 3, 30)
2881 22:57:56.700745 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2882 22:57:56.704607 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2883 22:57:56.704725
2884 22:57:56.710703 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2885 22:57:56.714367 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2886 22:57:56.717379 [Gating] SW calibration Done
2887 22:57:56.717486 ==
2888 22:57:56.721057 Dram Type= 6, Freq= 0, CH_0, rank 1
2889 22:57:56.724382 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2890 22:57:56.724506 ==
2891 22:57:56.724578 RX Vref Scan: 0
2892 22:57:56.724640
2893 22:57:56.727523 RX Vref 0 -> 0, step: 1
2894 22:57:56.727619
2895 22:57:56.731306 RX Delay -40 -> 252, step: 8
2896 22:57:56.734735 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2897 22:57:56.737723 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2898 22:57:56.744531 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2899 22:57:56.747981 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2900 22:57:56.751126 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2901 22:57:56.754248 iDelay=200, Bit 5, Center 119 (48 ~ 191) 144
2902 22:57:56.757761 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2903 22:57:56.760667 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2904 22:57:56.767805 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2905 22:57:56.771181 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
2906 22:57:56.774465 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2907 22:57:56.777684 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2908 22:57:56.781383 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2909 22:57:56.787927 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2910 22:57:56.791023 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2911 22:57:56.794220 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
2912 22:57:56.794331 ==
2913 22:57:56.797696 Dram Type= 6, Freq= 0, CH_0, rank 1
2914 22:57:56.800915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2915 22:57:56.801026 ==
2916 22:57:56.804373 DQS Delay:
2917 22:57:56.804506 DQS0 = 0, DQS1 = 0
2918 22:57:56.807925 DQM Delay:
2919 22:57:56.808056 DQM0 = 122, DQM1 = 112
2920 22:57:56.811153 DQ Delay:
2921 22:57:56.814254 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =119
2922 22:57:56.817724 DQ4 =127, DQ5 =119, DQ6 =127, DQ7 =127
2923 22:57:56.821073 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
2924 22:57:56.824564 DQ12 =115, DQ13 =119, DQ14 =123, DQ15 =123
2925 22:57:56.824686
2926 22:57:56.824758
2927 22:57:56.824819 ==
2928 22:57:56.827789 Dram Type= 6, Freq= 0, CH_0, rank 1
2929 22:57:56.830991 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2930 22:57:56.831103 ==
2931 22:57:56.831173
2932 22:57:56.831235
2933 22:57:56.834537 TX Vref Scan disable
2934 22:57:56.837943 == TX Byte 0 ==
2935 22:57:56.841098 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
2936 22:57:56.844174 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
2937 22:57:56.848237 == TX Byte 1 ==
2938 22:57:56.851339 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2939 22:57:56.854260 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2940 22:57:56.854371 ==
2941 22:57:56.857750 Dram Type= 6, Freq= 0, CH_0, rank 1
2942 22:57:56.860980 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2943 22:57:56.864220 ==
2944 22:57:56.874708 TX Vref=22, minBit 1, minWin=25, winSum=417
2945 22:57:56.878308 TX Vref=24, minBit 2, minWin=25, winSum=419
2946 22:57:56.881812 TX Vref=26, minBit 0, minWin=26, winSum=426
2947 22:57:56.885272 TX Vref=28, minBit 1, minWin=26, winSum=428
2948 22:57:56.888520 TX Vref=30, minBit 3, minWin=26, winSum=432
2949 22:57:56.891910 TX Vref=32, minBit 5, minWin=25, winSum=426
2950 22:57:56.898467 [TxChooseVref] Worse bit 3, Min win 26, Win sum 432, Final Vref 30
2951 22:57:56.898604
2952 22:57:56.902023 Final TX Range 1 Vref 30
2953 22:57:56.902141
2954 22:57:56.902209 ==
2955 22:57:56.905345 Dram Type= 6, Freq= 0, CH_0, rank 1
2956 22:57:56.908843 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2957 22:57:56.908953 ==
2958 22:57:56.909023
2959 22:57:56.909086
2960 22:57:56.912039 TX Vref Scan disable
2961 22:57:56.915127 == TX Byte 0 ==
2962 22:57:56.918756 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2963 22:57:56.921898 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2964 22:57:56.925348 == TX Byte 1 ==
2965 22:57:56.929128 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2966 22:57:56.932325 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2967 22:57:56.932443
2968 22:57:56.935332 [DATLAT]
2969 22:57:56.935430 Freq=1200, CH0 RK1
2970 22:57:56.935499
2971 22:57:56.938801 DATLAT Default: 0xd
2972 22:57:56.938903 0, 0xFFFF, sum = 0
2973 22:57:56.942494 1, 0xFFFF, sum = 0
2974 22:57:56.942638 2, 0xFFFF, sum = 0
2975 22:57:56.945622 3, 0xFFFF, sum = 0
2976 22:57:56.945725 4, 0xFFFF, sum = 0
2977 22:57:56.948849 5, 0xFFFF, sum = 0
2978 22:57:56.948952 6, 0xFFFF, sum = 0
2979 22:57:56.952445 7, 0xFFFF, sum = 0
2980 22:57:56.952546 8, 0xFFFF, sum = 0
2981 22:57:56.955666 9, 0xFFFF, sum = 0
2982 22:57:56.955770 10, 0xFFFF, sum = 0
2983 22:57:56.958702 11, 0xFFFF, sum = 0
2984 22:57:56.958801 12, 0x0, sum = 1
2985 22:57:56.961991 13, 0x0, sum = 2
2986 22:57:56.962092 14, 0x0, sum = 3
2987 22:57:56.965650 15, 0x0, sum = 4
2988 22:57:56.965761 best_step = 13
2989 22:57:56.965828
2990 22:57:56.965891 ==
2991 22:57:56.968989 Dram Type= 6, Freq= 0, CH_0, rank 1
2992 22:57:56.975453 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2993 22:57:56.975588 ==
2994 22:57:56.975658 RX Vref Scan: 0
2995 22:57:56.975721
2996 22:57:56.978692 RX Vref 0 -> 0, step: 1
2997 22:57:56.978789
2998 22:57:56.982205 RX Delay -13 -> 252, step: 4
2999 22:57:56.985190 iDelay=195, Bit 0, Center 120 (51 ~ 190) 140
3000 22:57:56.989147 iDelay=195, Bit 1, Center 122 (55 ~ 190) 136
3001 22:57:56.995593 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3002 22:57:56.998486 iDelay=195, Bit 3, Center 118 (51 ~ 186) 136
3003 22:57:57.002098 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3004 22:57:57.005303 iDelay=195, Bit 5, Center 116 (51 ~ 182) 132
3005 22:57:57.009048 iDelay=195, Bit 6, Center 128 (63 ~ 194) 132
3006 22:57:57.011810 iDelay=195, Bit 7, Center 128 (63 ~ 194) 132
3007 22:57:57.018604 iDelay=195, Bit 8, Center 100 (35 ~ 166) 132
3008 22:57:57.021872 iDelay=195, Bit 9, Center 100 (35 ~ 166) 132
3009 22:57:57.025514 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3010 22:57:57.028717 iDelay=195, Bit 11, Center 104 (39 ~ 170) 132
3011 22:57:57.032193 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3012 22:57:57.038632 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3013 22:57:57.042055 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3014 22:57:57.045493 iDelay=195, Bit 15, Center 120 (55 ~ 186) 132
3015 22:57:57.045653 ==
3016 22:57:57.048734 Dram Type= 6, Freq= 0, CH_0, rank 1
3017 22:57:57.052224 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3018 22:57:57.052336 ==
3019 22:57:57.055452 DQS Delay:
3020 22:57:57.055555 DQS0 = 0, DQS1 = 0
3021 22:57:57.059109 DQM Delay:
3022 22:57:57.059211 DQM0 = 121, DQM1 = 111
3023 22:57:57.062261 DQ Delay:
3024 22:57:57.065596 DQ0 =120, DQ1 =122, DQ2 =118, DQ3 =118
3025 22:57:57.068628 DQ4 =122, DQ5 =116, DQ6 =128, DQ7 =128
3026 22:57:57.072522 DQ8 =100, DQ9 =100, DQ10 =110, DQ11 =104
3027 22:57:57.075395 DQ12 =114, DQ13 =118, DQ14 =122, DQ15 =120
3028 22:57:57.075500
3029 22:57:57.075566
3030 22:57:57.082013 [DQSOSCAuto] RK1, (LSB)MR18= 0x11f2, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 403 ps
3031 22:57:57.085626 CH0 RK1: MR19=403, MR18=11F2
3032 22:57:57.092296 CH0_RK1: MR19=0x403, MR18=0x11F2, DQSOSC=403, MR23=63, INC=40, DEC=26
3033 22:57:57.095733 [RxdqsGatingPostProcess] freq 1200
3034 22:57:57.102387 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3035 22:57:57.102537 best DQS0 dly(2T, 0.5T) = (0, 11)
3036 22:57:57.105826 best DQS1 dly(2T, 0.5T) = (0, 12)
3037 22:57:57.109270 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3038 22:57:57.112505 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3039 22:57:57.115884 best DQS0 dly(2T, 0.5T) = (0, 11)
3040 22:57:57.119150 best DQS1 dly(2T, 0.5T) = (0, 11)
3041 22:57:57.122585 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3042 22:57:57.126206 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3043 22:57:57.129073 Pre-setting of DQS Precalculation
3044 22:57:57.132734 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3045 22:57:57.135697 ==
3046 22:57:57.135809 Dram Type= 6, Freq= 0, CH_1, rank 0
3047 22:57:57.142565 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3048 22:57:57.142701 ==
3049 22:57:57.145852 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3050 22:57:57.152683 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3051 22:57:57.161649 [CA 0] Center 37 (7~68) winsize 62
3052 22:57:57.164515 [CA 1] Center 37 (7~68) winsize 62
3053 22:57:57.168009 [CA 2] Center 35 (5~65) winsize 61
3054 22:57:57.171164 [CA 3] Center 34 (4~64) winsize 61
3055 22:57:57.174678 [CA 4] Center 34 (4~64) winsize 61
3056 22:57:57.177972 [CA 5] Center 33 (3~63) winsize 61
3057 22:57:57.178083
3058 22:57:57.181434 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3059 22:57:57.181534
3060 22:57:57.184864 [CATrainingPosCal] consider 1 rank data
3061 22:57:57.187896 u2DelayCellTimex100 = 270/100 ps
3062 22:57:57.191458 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3063 22:57:57.194679 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3064 22:57:57.201448 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3065 22:57:57.204501 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3066 22:57:57.208091 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3067 22:57:57.211560 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3068 22:57:57.211674
3069 22:57:57.215004 CA PerBit enable=1, Macro0, CA PI delay=33
3070 22:57:57.215109
3071 22:57:57.218243 [CBTSetCACLKResult] CA Dly = 33
3072 22:57:57.218348 CS Dly: 7 (0~38)
3073 22:57:57.218415 ==
3074 22:57:57.221743 Dram Type= 6, Freq= 0, CH_1, rank 1
3075 22:57:57.227927 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3076 22:57:57.228075 ==
3077 22:57:57.231215 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3078 22:57:57.238183 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3079 22:57:57.246925 [CA 0] Center 37 (7~68) winsize 62
3080 22:57:57.250408 [CA 1] Center 37 (7~68) winsize 62
3081 22:57:57.253517 [CA 2] Center 35 (5~65) winsize 61
3082 22:57:57.257053 [CA 3] Center 34 (4~65) winsize 62
3083 22:57:57.260533 [CA 4] Center 34 (4~65) winsize 62
3084 22:57:57.263709 [CA 5] Center 34 (4~64) winsize 61
3085 22:57:57.263820
3086 22:57:57.267124 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3087 22:57:57.267234
3088 22:57:57.270330 [CATrainingPosCal] consider 2 rank data
3089 22:57:57.274185 u2DelayCellTimex100 = 270/100 ps
3090 22:57:57.276961 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3091 22:57:57.280312 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3092 22:57:57.287093 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3093 22:57:57.290077 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3094 22:57:57.293757 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3095 22:57:57.296987 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3096 22:57:57.297110
3097 22:57:57.300470 CA PerBit enable=1, Macro0, CA PI delay=33
3098 22:57:57.300575
3099 22:57:57.303809 [CBTSetCACLKResult] CA Dly = 33
3100 22:57:57.303909 CS Dly: 8 (0~41)
3101 22:57:57.303975
3102 22:57:57.307386 ----->DramcWriteLeveling(PI) begin...
3103 22:57:57.307489 ==
3104 22:57:57.310697 Dram Type= 6, Freq= 0, CH_1, rank 0
3105 22:57:57.317364 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3106 22:57:57.317496 ==
3107 22:57:57.320809 Write leveling (Byte 0): 25 => 25
3108 22:57:57.323802 Write leveling (Byte 1): 28 => 28
3109 22:57:57.323918 DramcWriteLeveling(PI) end<-----
3110 22:57:57.327215
3111 22:57:57.327324 ==
3112 22:57:57.330761 Dram Type= 6, Freq= 0, CH_1, rank 0
3113 22:57:57.333994 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3114 22:57:57.334110 ==
3115 22:57:57.337167 [Gating] SW mode calibration
3116 22:57:57.343848 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3117 22:57:57.347238 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3118 22:57:57.354003 0 15 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3119 22:57:57.357705 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3120 22:57:57.360706 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3121 22:57:57.367577 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3122 22:57:57.370704 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3123 22:57:57.373953 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3124 22:57:57.380480 0 15 24 | B1->B0 | 3333 2828 | 1 0 | (1 0) (0 1)
3125 22:57:57.384247 0 15 28 | B1->B0 | 2424 2323 | 0 0 | (1 0) (1 0)
3126 22:57:57.387502 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3127 22:57:57.394095 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3128 22:57:57.397564 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3129 22:57:57.400703 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3130 22:57:57.404152 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3131 22:57:57.410720 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3132 22:57:57.414024 1 0 24 | B1->B0 | 3737 4545 | 0 0 | (0 0) (0 0)
3133 22:57:57.417682 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3134 22:57:57.424445 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3135 22:57:57.427671 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3136 22:57:57.430889 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3137 22:57:57.437772 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3138 22:57:57.440570 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3139 22:57:57.444251 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3140 22:57:57.450691 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3141 22:57:57.454006 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3142 22:57:57.457523 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3143 22:57:57.464245 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3144 22:57:57.467650 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3145 22:57:57.471065 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3146 22:57:57.477843 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3147 22:57:57.480844 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3148 22:57:57.484219 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3149 22:57:57.487904 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3150 22:57:57.494342 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3151 22:57:57.497903 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3152 22:57:57.500627 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3153 22:57:57.507391 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3154 22:57:57.510918 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3155 22:57:57.514772 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3156 22:57:57.520618 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3157 22:57:57.524674 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3158 22:57:57.527723 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3159 22:57:57.531244 Total UI for P1: 0, mck2ui 16
3160 22:57:57.534111 best dqsien dly found for B0: ( 1, 3, 26)
3161 22:57:57.538073 Total UI for P1: 0, mck2ui 16
3162 22:57:57.540915 best dqsien dly found for B1: ( 1, 3, 26)
3163 22:57:57.544421 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3164 22:57:57.547737 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3165 22:57:57.547857
3166 22:57:57.550929 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3167 22:57:57.557957 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3168 22:57:57.558092 [Gating] SW calibration Done
3169 22:57:57.558164 ==
3170 22:57:57.561083 Dram Type= 6, Freq= 0, CH_1, rank 0
3171 22:57:57.567932 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3172 22:57:57.568064 ==
3173 22:57:57.568135 RX Vref Scan: 0
3174 22:57:57.568197
3175 22:57:57.571126 RX Vref 0 -> 0, step: 1
3176 22:57:57.571226
3177 22:57:57.574825 RX Delay -40 -> 252, step: 8
3178 22:57:57.577946 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3179 22:57:57.580943 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3180 22:57:57.584540 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3181 22:57:57.591222 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3182 22:57:57.594338 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3183 22:57:57.597706 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3184 22:57:57.601149 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3185 22:57:57.604230 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
3186 22:57:57.611170 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
3187 22:57:57.614460 iDelay=200, Bit 9, Center 103 (40 ~ 167) 128
3188 22:57:57.618001 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3189 22:57:57.621108 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3190 22:57:57.624327 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3191 22:57:57.631130 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3192 22:57:57.634408 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3193 22:57:57.637866 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3194 22:57:57.638019 ==
3195 22:57:57.641150 Dram Type= 6, Freq= 0, CH_1, rank 0
3196 22:57:57.644511 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3197 22:57:57.644622 ==
3198 22:57:57.648154 DQS Delay:
3199 22:57:57.648264 DQS0 = 0, DQS1 = 0
3200 22:57:57.648333 DQM Delay:
3201 22:57:57.651281 DQM0 = 120, DQM1 = 116
3202 22:57:57.651375 DQ Delay:
3203 22:57:57.654665 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3204 22:57:57.658006 DQ4 =119, DQ5 =127, DQ6 =127, DQ7 =123
3205 22:57:57.661819 DQ8 =107, DQ9 =103, DQ10 =115, DQ11 =111
3206 22:57:57.667806 DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123
3207 22:57:57.667942
3208 22:57:57.668012
3209 22:57:57.668075 ==
3210 22:57:57.671902 Dram Type= 6, Freq= 0, CH_1, rank 0
3211 22:57:57.674742 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3212 22:57:57.674848 ==
3213 22:57:57.674917
3214 22:57:57.674979
3215 22:57:57.677975 TX Vref Scan disable
3216 22:57:57.678071 == TX Byte 0 ==
3217 22:57:57.684547 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3218 22:57:57.687919 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3219 22:57:57.688058 == TX Byte 1 ==
3220 22:57:57.694698 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3221 22:57:57.698200 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3222 22:57:57.698325 ==
3223 22:57:57.701288 Dram Type= 6, Freq= 0, CH_1, rank 0
3224 22:57:57.704786 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3225 22:57:57.704907 ==
3226 22:57:57.717436 TX Vref=22, minBit 10, minWin=25, winSum=412
3227 22:57:57.720819 TX Vref=24, minBit 9, minWin=24, winSum=415
3228 22:57:57.724244 TX Vref=26, minBit 1, minWin=26, winSum=429
3229 22:57:57.727625 TX Vref=28, minBit 2, minWin=26, winSum=428
3230 22:57:57.730904 TX Vref=30, minBit 3, minWin=26, winSum=433
3231 22:57:57.737492 TX Vref=32, minBit 9, minWin=26, winSum=426
3232 22:57:57.740508 [TxChooseVref] Worse bit 3, Min win 26, Win sum 433, Final Vref 30
3233 22:57:57.740623
3234 22:57:57.744008 Final TX Range 1 Vref 30
3235 22:57:57.744160
3236 22:57:57.744228 ==
3237 22:57:57.747622 Dram Type= 6, Freq= 0, CH_1, rank 0
3238 22:57:57.751004 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3239 22:57:57.751111 ==
3240 22:57:57.751180
3241 22:57:57.753907
3242 22:57:57.753998 TX Vref Scan disable
3243 22:57:57.757301 == TX Byte 0 ==
3244 22:57:57.760605 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3245 22:57:57.764468 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3246 22:57:57.767544 == TX Byte 1 ==
3247 22:57:57.770786 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3248 22:57:57.774084 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3249 22:57:57.774197
3250 22:57:57.777382 [DATLAT]
3251 22:57:57.777482 Freq=1200, CH1 RK0
3252 22:57:57.777550
3253 22:57:57.780815 DATLAT Default: 0xd
3254 22:57:57.780910 0, 0xFFFF, sum = 0
3255 22:57:57.784213 1, 0xFFFF, sum = 0
3256 22:57:57.784312 2, 0xFFFF, sum = 0
3257 22:57:57.787747 3, 0xFFFF, sum = 0
3258 22:57:57.787844 4, 0xFFFF, sum = 0
3259 22:57:57.790599 5, 0xFFFF, sum = 0
3260 22:57:57.790692 6, 0xFFFF, sum = 0
3261 22:57:57.794093 7, 0xFFFF, sum = 0
3262 22:57:57.797686 8, 0xFFFF, sum = 0
3263 22:57:57.797804 9, 0xFFFF, sum = 0
3264 22:57:57.800638 10, 0xFFFF, sum = 0
3265 22:57:57.800739 11, 0xFFFF, sum = 0
3266 22:57:57.804018 12, 0x0, sum = 1
3267 22:57:57.804119 13, 0x0, sum = 2
3268 22:57:57.804187 14, 0x0, sum = 3
3269 22:57:57.807738 15, 0x0, sum = 4
3270 22:57:57.807839 best_step = 13
3271 22:57:57.807905
3272 22:57:57.810600 ==
3273 22:57:57.810693 Dram Type= 6, Freq= 0, CH_1, rank 0
3274 22:57:57.817392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3275 22:57:57.817559 ==
3276 22:57:57.817703 RX Vref Scan: 1
3277 22:57:57.817795
3278 22:57:57.820682 Set Vref Range= 32 -> 127
3279 22:57:57.820779
3280 22:57:57.823985 RX Vref 32 -> 127, step: 1
3281 22:57:57.824087
3282 22:57:57.827305 RX Delay -5 -> 252, step: 4
3283 22:57:57.827405
3284 22:57:57.830581 Set Vref, RX VrefLevel [Byte0]: 32
3285 22:57:57.834032 [Byte1]: 32
3286 22:57:57.834145
3287 22:57:57.837607 Set Vref, RX VrefLevel [Byte0]: 33
3288 22:57:57.840837 [Byte1]: 33
3289 22:57:57.840956
3290 22:57:57.843945 Set Vref, RX VrefLevel [Byte0]: 34
3291 22:57:57.847671 [Byte1]: 34
3292 22:57:57.851291
3293 22:57:57.851431 Set Vref, RX VrefLevel [Byte0]: 35
3294 22:57:57.854575 [Byte1]: 35
3295 22:57:57.859331
3296 22:57:57.859467 Set Vref, RX VrefLevel [Byte0]: 36
3297 22:57:57.862813 [Byte1]: 36
3298 22:57:57.867051
3299 22:57:57.867215 Set Vref, RX VrefLevel [Byte0]: 37
3300 22:57:57.870519 [Byte1]: 37
3301 22:57:57.874696
3302 22:57:57.874885 Set Vref, RX VrefLevel [Byte0]: 38
3303 22:57:57.877997 [Byte1]: 38
3304 22:57:57.883001
3305 22:57:57.883136 Set Vref, RX VrefLevel [Byte0]: 39
3306 22:57:57.886107 [Byte1]: 39
3307 22:57:57.890725
3308 22:57:57.890843 Set Vref, RX VrefLevel [Byte0]: 40
3309 22:57:57.893711 [Byte1]: 40
3310 22:57:57.898445
3311 22:57:57.898571 Set Vref, RX VrefLevel [Byte0]: 41
3312 22:57:57.901847 [Byte1]: 41
3313 22:57:57.906259
3314 22:57:57.906390 Set Vref, RX VrefLevel [Byte0]: 42
3315 22:57:57.909495 [Byte1]: 42
3316 22:57:57.914018
3317 22:57:57.914178 Set Vref, RX VrefLevel [Byte0]: 43
3318 22:57:57.917500 [Byte1]: 43
3319 22:57:57.922343
3320 22:57:57.922472 Set Vref, RX VrefLevel [Byte0]: 44
3321 22:57:57.925478 [Byte1]: 44
3322 22:57:57.929973
3323 22:57:57.930132 Set Vref, RX VrefLevel [Byte0]: 45
3324 22:57:57.933111 [Byte1]: 45
3325 22:57:57.937511
3326 22:57:57.937680 Set Vref, RX VrefLevel [Byte0]: 46
3327 22:57:57.940925 [Byte1]: 46
3328 22:57:57.945328
3329 22:57:57.945482 Set Vref, RX VrefLevel [Byte0]: 47
3330 22:57:57.949336 [Byte1]: 47
3331 22:57:57.953643
3332 22:57:57.953761 Set Vref, RX VrefLevel [Byte0]: 48
3333 22:57:57.956771 [Byte1]: 48
3334 22:57:57.960929
3335 22:57:57.961048 Set Vref, RX VrefLevel [Byte0]: 49
3336 22:57:57.964309 [Byte1]: 49
3337 22:57:57.969174
3338 22:57:57.969307 Set Vref, RX VrefLevel [Byte0]: 50
3339 22:57:57.972709 [Byte1]: 50
3340 22:57:57.976877
3341 22:57:57.977000 Set Vref, RX VrefLevel [Byte0]: 51
3342 22:57:57.980404 [Byte1]: 51
3343 22:57:57.984499
3344 22:57:57.984621 Set Vref, RX VrefLevel [Byte0]: 52
3345 22:57:57.988118 [Byte1]: 52
3346 22:57:57.992416
3347 22:57:57.992536 Set Vref, RX VrefLevel [Byte0]: 53
3348 22:57:57.996136 [Byte1]: 53
3349 22:57:58.000381
3350 22:57:58.000542 Set Vref, RX VrefLevel [Byte0]: 54
3351 22:57:58.003891 [Byte1]: 54
3352 22:57:58.008194
3353 22:57:58.008317 Set Vref, RX VrefLevel [Byte0]: 55
3354 22:57:58.011641 [Byte1]: 55
3355 22:57:58.015899
3356 22:57:58.016021 Set Vref, RX VrefLevel [Byte0]: 56
3357 22:57:58.019277 [Byte1]: 56
3358 22:57:58.024028
3359 22:57:58.024153 Set Vref, RX VrefLevel [Byte0]: 57
3360 22:57:58.027571 [Byte1]: 57
3361 22:57:58.032193
3362 22:57:58.032329 Set Vref, RX VrefLevel [Byte0]: 58
3363 22:57:58.035056 [Byte1]: 58
3364 22:57:58.040157
3365 22:57:58.040289 Set Vref, RX VrefLevel [Byte0]: 59
3366 22:57:58.043124 [Byte1]: 59
3367 22:57:58.047661
3368 22:57:58.047782 Set Vref, RX VrefLevel [Byte0]: 60
3369 22:57:58.050888 [Byte1]: 60
3370 22:57:58.055424
3371 22:57:58.055551 Set Vref, RX VrefLevel [Byte0]: 61
3372 22:57:58.058943 [Byte1]: 61
3373 22:57:58.063086
3374 22:57:58.063203 Set Vref, RX VrefLevel [Byte0]: 62
3375 22:57:58.066722 [Byte1]: 62
3376 22:57:58.071184
3377 22:57:58.071310 Set Vref, RX VrefLevel [Byte0]: 63
3378 22:57:58.074720 [Byte1]: 63
3379 22:57:58.079029
3380 22:57:58.079157 Set Vref, RX VrefLevel [Byte0]: 64
3381 22:57:58.082413 [Byte1]: 64
3382 22:57:58.086937
3383 22:57:58.087064 Set Vref, RX VrefLevel [Byte0]: 65
3384 22:57:58.090321 [Byte1]: 65
3385 22:57:58.094699
3386 22:57:58.094823 Set Vref, RX VrefLevel [Byte0]: 66
3387 22:57:58.098064 [Byte1]: 66
3388 22:57:58.102483
3389 22:57:58.102613 Set Vref, RX VrefLevel [Byte0]: 67
3390 22:57:58.105820 [Byte1]: 67
3391 22:57:58.110232
3392 22:57:58.110363 Set Vref, RX VrefLevel [Byte0]: 68
3393 22:57:58.113823 [Byte1]: 68
3394 22:57:58.118470
3395 22:57:58.118604 Set Vref, RX VrefLevel [Byte0]: 69
3396 22:57:58.121549 [Byte1]: 69
3397 22:57:58.126246
3398 22:57:58.126374 Final RX Vref Byte 0 = 55 to rank0
3399 22:57:58.129632 Final RX Vref Byte 1 = 48 to rank0
3400 22:57:58.132960 Final RX Vref Byte 0 = 55 to rank1
3401 22:57:58.136310 Final RX Vref Byte 1 = 48 to rank1==
3402 22:57:58.139685 Dram Type= 6, Freq= 0, CH_1, rank 0
3403 22:57:58.146131 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3404 22:57:58.146269 ==
3405 22:57:58.146341 DQS Delay:
3406 22:57:58.146403 DQS0 = 0, DQS1 = 0
3407 22:57:58.149446 DQM Delay:
3408 22:57:58.149570 DQM0 = 120, DQM1 = 116
3409 22:57:58.152554 DQ Delay:
3410 22:57:58.156234 DQ0 =124, DQ1 =114, DQ2 =110, DQ3 =118
3411 22:57:58.159214 DQ4 =118, DQ5 =128, DQ6 =128, DQ7 =120
3412 22:57:58.162908 DQ8 =104, DQ9 =106, DQ10 =118, DQ11 =108
3413 22:57:58.165925 DQ12 =122, DQ13 =124, DQ14 =124, DQ15 =126
3414 22:57:58.166035
3415 22:57:58.166102
3416 22:57:58.173113 [DQSOSCAuto] RK0, (LSB)MR18= 0x13, (MSB)MR19= 0x404, tDQSOscB0 = 402 ps tDQSOscB1 = 410 ps
3417 22:57:58.176064 CH1 RK0: MR19=404, MR18=13
3418 22:57:58.182742 CH1_RK0: MR19=0x404, MR18=0x13, DQSOSC=402, MR23=63, INC=40, DEC=27
3419 22:57:58.182918
3420 22:57:58.185915 ----->DramcWriteLeveling(PI) begin...
3421 22:57:58.186006 ==
3422 22:57:58.189854 Dram Type= 6, Freq= 0, CH_1, rank 1
3423 22:57:58.193218 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3424 22:57:58.193319 ==
3425 22:57:58.196169 Write leveling (Byte 0): 25 => 25
3426 22:57:58.199956 Write leveling (Byte 1): 31 => 31
3427 22:57:58.202757 DramcWriteLeveling(PI) end<-----
3428 22:57:58.202860
3429 22:57:58.202927 ==
3430 22:57:58.206252 Dram Type= 6, Freq= 0, CH_1, rank 1
3431 22:57:58.209456 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3432 22:57:58.209572 ==
3433 22:57:58.213245 [Gating] SW mode calibration
3434 22:57:58.219668 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3435 22:57:58.226469 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3436 22:57:58.229484 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3437 22:57:58.236573 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3438 22:57:58.239987 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3439 22:57:58.243302 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3440 22:57:58.246721 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3441 22:57:58.253419 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
3442 22:57:58.256628 0 15 24 | B1->B0 | 2626 2f2f | 0 1 | (1 0) (1 0)
3443 22:57:58.260341 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
3444 22:57:58.266622 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3445 22:57:58.269944 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3446 22:57:58.273494 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3447 22:57:58.279814 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3448 22:57:58.283417 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3449 22:57:58.286524 1 0 20 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
3450 22:57:58.293218 1 0 24 | B1->B0 | 4646 3030 | 0 0 | (0 0) (0 0)
3451 22:57:58.296735 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3452 22:57:58.299886 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3453 22:57:58.306501 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3454 22:57:58.309879 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3455 22:57:58.313508 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3456 22:57:58.320101 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3457 22:57:58.323438 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3458 22:57:58.326621 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3459 22:57:58.333105 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3460 22:57:58.336326 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3461 22:57:58.339890 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3462 22:57:58.343328 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3463 22:57:58.349554 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3464 22:57:58.352970 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3465 22:57:58.356249 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3466 22:57:58.363105 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3467 22:57:58.366477 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3468 22:57:58.369554 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3469 22:57:58.376248 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3470 22:57:58.379526 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3471 22:57:58.382958 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3472 22:57:58.389859 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3473 22:57:58.393338 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3474 22:57:58.395957 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3475 22:57:58.399646 Total UI for P1: 0, mck2ui 16
3476 22:57:58.403078 best dqsien dly found for B1: ( 1, 3, 20)
3477 22:57:58.409456 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3478 22:57:58.412841 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3479 22:57:58.416360 Total UI for P1: 0, mck2ui 16
3480 22:57:58.419715 best dqsien dly found for B0: ( 1, 3, 26)
3481 22:57:58.422992 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3482 22:57:58.426157 best DQS1 dly(MCK, UI, PI) = (1, 3, 20)
3483 22:57:58.426264
3484 22:57:58.429343 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3485 22:57:58.433055 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 20)
3486 22:57:58.436176 [Gating] SW calibration Done
3487 22:57:58.436277 ==
3488 22:57:58.439919 Dram Type= 6, Freq= 0, CH_1, rank 1
3489 22:57:58.443136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3490 22:57:58.443239 ==
3491 22:57:58.446326 RX Vref Scan: 0
3492 22:57:58.446419
3493 22:57:58.449526 RX Vref 0 -> 0, step: 1
3494 22:57:58.449643
3495 22:57:58.449713 RX Delay -40 -> 252, step: 8
3496 22:57:58.456271 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3497 22:57:58.459824 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3498 22:57:58.462893 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3499 22:57:58.465953 iDelay=200, Bit 3, Center 119 (56 ~ 183) 128
3500 22:57:58.469397 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3501 22:57:58.476116 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3502 22:57:58.479637 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3503 22:57:58.482498 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3504 22:57:58.485917 iDelay=200, Bit 8, Center 107 (40 ~ 175) 136
3505 22:57:58.492801 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3506 22:57:58.495708 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3507 22:57:58.498979 iDelay=200, Bit 11, Center 115 (48 ~ 183) 136
3508 22:57:58.502591 iDelay=200, Bit 12, Center 127 (56 ~ 199) 144
3509 22:57:58.505560 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3510 22:57:58.512545 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3511 22:57:58.516154 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
3512 22:57:58.516254 ==
3513 22:57:58.519014 Dram Type= 6, Freq= 0, CH_1, rank 1
3514 22:57:58.522234 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3515 22:57:58.522327 ==
3516 22:57:58.525594 DQS Delay:
3517 22:57:58.525698 DQS0 = 0, DQS1 = 0
3518 22:57:58.525767 DQM Delay:
3519 22:57:58.528941 DQM0 = 120, DQM1 = 118
3520 22:57:58.529055 DQ Delay:
3521 22:57:58.532328 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3522 22:57:58.535636 DQ4 =115, DQ5 =131, DQ6 =131, DQ7 =119
3523 22:57:58.539069 DQ8 =107, DQ9 =107, DQ10 =115, DQ11 =115
3524 22:57:58.545709 DQ12 =127, DQ13 =127, DQ14 =123, DQ15 =127
3525 22:57:58.545820
3526 22:57:58.545891
3527 22:57:58.545953 ==
3528 22:57:58.549080 Dram Type= 6, Freq= 0, CH_1, rank 1
3529 22:57:58.552177 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3530 22:57:58.552268 ==
3531 22:57:58.552336
3532 22:57:58.552397
3533 22:57:58.555516 TX Vref Scan disable
3534 22:57:58.555601 == TX Byte 0 ==
3535 22:57:58.562279 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3536 22:57:58.565770 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3537 22:57:58.565863 == TX Byte 1 ==
3538 22:57:58.572204 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3539 22:57:58.575594 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3540 22:57:58.575690 ==
3541 22:57:58.579082 Dram Type= 6, Freq= 0, CH_1, rank 1
3542 22:57:58.582366 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3543 22:57:58.582459 ==
3544 22:57:58.595533 TX Vref=22, minBit 9, minWin=25, winSum=419
3545 22:57:58.598923 TX Vref=24, minBit 2, minWin=25, winSum=426
3546 22:57:58.602164 TX Vref=26, minBit 2, minWin=26, winSum=429
3547 22:57:58.605197 TX Vref=28, minBit 9, minWin=26, winSum=434
3548 22:57:58.608715 TX Vref=30, minBit 0, minWin=27, winSum=438
3549 22:57:58.612052 TX Vref=32, minBit 1, minWin=26, winSum=434
3550 22:57:58.618371 [TxChooseVref] Worse bit 0, Min win 27, Win sum 438, Final Vref 30
3551 22:57:58.618492
3552 22:57:58.621847 Final TX Range 1 Vref 30
3553 22:57:58.621967
3554 22:57:58.622037 ==
3555 22:57:58.625783 Dram Type= 6, Freq= 0, CH_1, rank 1
3556 22:57:58.628436 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3557 22:57:58.628527 ==
3558 22:57:58.628594
3559 22:57:58.632221
3560 22:57:58.632312 TX Vref Scan disable
3561 22:57:58.635229 == TX Byte 0 ==
3562 22:57:58.638580 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3563 22:57:58.642090 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3564 22:57:58.645293 == TX Byte 1 ==
3565 22:57:58.648439 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3566 22:57:58.651791 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3567 22:57:58.651884
3568 22:57:58.655253 [DATLAT]
3569 22:57:58.655340 Freq=1200, CH1 RK1
3570 22:57:58.655407
3571 22:57:58.658722 DATLAT Default: 0xd
3572 22:57:58.658810 0, 0xFFFF, sum = 0
3573 22:57:58.662016 1, 0xFFFF, sum = 0
3574 22:57:58.662105 2, 0xFFFF, sum = 0
3575 22:57:58.665336 3, 0xFFFF, sum = 0
3576 22:57:58.665425 4, 0xFFFF, sum = 0
3577 22:57:58.668929 5, 0xFFFF, sum = 0
3578 22:57:58.669021 6, 0xFFFF, sum = 0
3579 22:57:58.671966 7, 0xFFFF, sum = 0
3580 22:57:58.672064 8, 0xFFFF, sum = 0
3581 22:57:58.675351 9, 0xFFFF, sum = 0
3582 22:57:58.678980 10, 0xFFFF, sum = 0
3583 22:57:58.679075 11, 0xFFFF, sum = 0
3584 22:57:58.682074 12, 0x0, sum = 1
3585 22:57:58.682176 13, 0x0, sum = 2
3586 22:57:58.682244 14, 0x0, sum = 3
3587 22:57:58.685543 15, 0x0, sum = 4
3588 22:57:58.685679 best_step = 13
3589 22:57:58.685747
3590 22:57:58.688484 ==
3591 22:57:58.688569 Dram Type= 6, Freq= 0, CH_1, rank 1
3592 22:57:58.695485 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3593 22:57:58.695602 ==
3594 22:57:58.695671 RX Vref Scan: 0
3595 22:57:58.695733
3596 22:57:58.698670 RX Vref 0 -> 0, step: 1
3597 22:57:58.698756
3598 22:57:58.702011 RX Delay -5 -> 252, step: 4
3599 22:57:58.705067 iDelay=195, Bit 0, Center 122 (59 ~ 186) 128
3600 22:57:58.708643 iDelay=195, Bit 1, Center 116 (55 ~ 178) 124
3601 22:57:58.715096 iDelay=195, Bit 2, Center 110 (51 ~ 170) 120
3602 22:57:58.718329 iDelay=195, Bit 3, Center 116 (55 ~ 178) 124
3603 22:57:58.721874 iDelay=195, Bit 4, Center 116 (55 ~ 178) 124
3604 22:57:58.725059 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3605 22:57:58.728600 iDelay=195, Bit 6, Center 130 (67 ~ 194) 128
3606 22:57:58.734911 iDelay=195, Bit 7, Center 120 (59 ~ 182) 124
3607 22:57:58.738204 iDelay=195, Bit 8, Center 104 (43 ~ 166) 124
3608 22:57:58.742156 iDelay=195, Bit 9, Center 106 (47 ~ 166) 120
3609 22:57:58.744816 iDelay=195, Bit 10, Center 116 (55 ~ 178) 124
3610 22:57:58.748295 iDelay=195, Bit 11, Center 110 (51 ~ 170) 120
3611 22:57:58.754798 iDelay=195, Bit 12, Center 126 (63 ~ 190) 128
3612 22:57:58.758113 iDelay=195, Bit 13, Center 124 (67 ~ 182) 116
3613 22:57:58.761881 iDelay=195, Bit 14, Center 122 (63 ~ 182) 120
3614 22:57:58.764745 iDelay=195, Bit 15, Center 124 (63 ~ 186) 124
3615 22:57:58.764841 ==
3616 22:57:58.768060 Dram Type= 6, Freq= 0, CH_1, rank 1
3617 22:57:58.774609 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3618 22:57:58.774742 ==
3619 22:57:58.774812 DQS Delay:
3620 22:57:58.778586 DQS0 = 0, DQS1 = 0
3621 22:57:58.778683 DQM Delay:
3622 22:57:58.781141 DQM0 = 120, DQM1 = 116
3623 22:57:58.781226 DQ Delay:
3624 22:57:58.784758 DQ0 =122, DQ1 =116, DQ2 =110, DQ3 =116
3625 22:57:58.787968 DQ4 =116, DQ5 =130, DQ6 =130, DQ7 =120
3626 22:57:58.791296 DQ8 =104, DQ9 =106, DQ10 =116, DQ11 =110
3627 22:57:58.795117 DQ12 =126, DQ13 =124, DQ14 =122, DQ15 =124
3628 22:57:58.795216
3629 22:57:58.795282
3630 22:57:58.804587 [DQSOSCAuto] RK1, (LSB)MR18= 0x11ef, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 403 ps
3631 22:57:58.807706 CH1 RK1: MR19=403, MR18=11EF
3632 22:57:58.810931 CH1_RK1: MR19=0x403, MR18=0x11EF, DQSOSC=403, MR23=63, INC=40, DEC=26
3633 22:57:58.814510 [RxdqsGatingPostProcess] freq 1200
3634 22:57:58.821049 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3635 22:57:58.824392 best DQS0 dly(2T, 0.5T) = (0, 11)
3636 22:57:58.827835 best DQS1 dly(2T, 0.5T) = (0, 11)
3637 22:57:58.831043 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3638 22:57:58.834434 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3639 22:57:58.837977 best DQS0 dly(2T, 0.5T) = (0, 11)
3640 22:57:58.841002 best DQS1 dly(2T, 0.5T) = (0, 11)
3641 22:57:58.844712 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3642 22:57:58.847709 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3643 22:57:58.847807 Pre-setting of DQS Precalculation
3644 22:57:58.854653 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3645 22:57:58.860965 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3646 22:57:58.867811 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3647 22:57:58.867968
3648 22:57:58.868038
3649 22:57:58.871212 [Calibration Summary] 2400 Mbps
3650 22:57:58.874579 CH 0, Rank 0
3651 22:57:58.874678 SW Impedance : PASS
3652 22:57:58.877544 DUTY Scan : NO K
3653 22:57:58.880780 ZQ Calibration : PASS
3654 22:57:58.880880 Jitter Meter : NO K
3655 22:57:58.884078 CBT Training : PASS
3656 22:57:58.887438 Write leveling : PASS
3657 22:57:58.887543 RX DQS gating : PASS
3658 22:57:58.890777 RX DQ/DQS(RDDQC) : PASS
3659 22:57:58.890869 TX DQ/DQS : PASS
3660 22:57:58.894078 RX DATLAT : PASS
3661 22:57:58.897545 RX DQ/DQS(Engine): PASS
3662 22:57:58.897685 TX OE : NO K
3663 22:57:58.900816 All Pass.
3664 22:57:58.900911
3665 22:57:58.900979 CH 0, Rank 1
3666 22:57:58.904212 SW Impedance : PASS
3667 22:57:58.904304 DUTY Scan : NO K
3668 22:57:58.907419 ZQ Calibration : PASS
3669 22:57:58.910686 Jitter Meter : NO K
3670 22:57:58.910781 CBT Training : PASS
3671 22:57:58.914285 Write leveling : PASS
3672 22:57:58.917784 RX DQS gating : PASS
3673 22:57:58.917892 RX DQ/DQS(RDDQC) : PASS
3674 22:57:58.920913 TX DQ/DQS : PASS
3675 22:57:58.924247 RX DATLAT : PASS
3676 22:57:58.924384 RX DQ/DQS(Engine): PASS
3677 22:57:58.927566 TX OE : NO K
3678 22:57:58.927673 All Pass.
3679 22:57:58.927741
3680 22:57:58.930811 CH 1, Rank 0
3681 22:57:58.930905 SW Impedance : PASS
3682 22:57:58.934182 DUTY Scan : NO K
3683 22:57:58.937552 ZQ Calibration : PASS
3684 22:57:58.937675 Jitter Meter : NO K
3685 22:57:58.940885 CBT Training : PASS
3686 22:57:58.940980 Write leveling : PASS
3687 22:57:58.944316 RX DQS gating : PASS
3688 22:57:58.947593 RX DQ/DQS(RDDQC) : PASS
3689 22:57:58.947691 TX DQ/DQS : PASS
3690 22:57:58.951165 RX DATLAT : PASS
3691 22:57:58.954190 RX DQ/DQS(Engine): PASS
3692 22:57:58.954285 TX OE : NO K
3693 22:57:58.957722 All Pass.
3694 22:57:58.957815
3695 22:57:58.957882 CH 1, Rank 1
3696 22:57:58.960921 SW Impedance : PASS
3697 22:57:58.961009 DUTY Scan : NO K
3698 22:57:58.964069 ZQ Calibration : PASS
3699 22:57:58.967874 Jitter Meter : NO K
3700 22:57:58.968008 CBT Training : PASS
3701 22:57:58.971238 Write leveling : PASS
3702 22:57:58.974448 RX DQS gating : PASS
3703 22:57:58.974549 RX DQ/DQS(RDDQC) : PASS
3704 22:57:58.977551 TX DQ/DQS : PASS
3705 22:57:58.980723 RX DATLAT : PASS
3706 22:57:58.980822 RX DQ/DQS(Engine): PASS
3707 22:57:58.984263 TX OE : NO K
3708 22:57:58.984353 All Pass.
3709 22:57:58.984485
3710 22:57:58.987573 DramC Write-DBI off
3711 22:57:58.987662 PER_BANK_REFRESH: Hybrid Mode
3712 22:57:58.990814 TX_TRACKING: ON
3713 22:57:59.000785 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3714 22:57:59.004153 [FAST_K] Save calibration result to emmc
3715 22:57:59.007213 dramc_set_vcore_voltage set vcore to 650000
3716 22:57:59.010980 Read voltage for 600, 5
3717 22:57:59.011091 Vio18 = 0
3718 22:57:59.011159 Vcore = 650000
3719 22:57:59.013966 Vdram = 0
3720 22:57:59.014054 Vddq = 0
3721 22:57:59.014119 Vmddr = 0
3722 22:57:59.020971 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3723 22:57:59.024054 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3724 22:57:59.027091 MEM_TYPE=3, freq_sel=19
3725 22:57:59.030547 sv_algorithm_assistance_LP4_1600
3726 22:57:59.033868 ============ PULL DRAM RESETB DOWN ============
3727 22:57:59.036926 ========== PULL DRAM RESETB DOWN end =========
3728 22:57:59.043835 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3729 22:57:59.047529 ===================================
3730 22:57:59.047650 LPDDR4 DRAM CONFIGURATION
3731 22:57:59.050821 ===================================
3732 22:57:59.054017 EX_ROW_EN[0] = 0x0
3733 22:57:59.057232 EX_ROW_EN[1] = 0x0
3734 22:57:59.057328 LP4Y_EN = 0x0
3735 22:57:59.060782 WORK_FSP = 0x0
3736 22:57:59.060875 WL = 0x2
3737 22:57:59.063763 RL = 0x2
3738 22:57:59.063855 BL = 0x2
3739 22:57:59.066843 RPST = 0x0
3740 22:57:59.066933 RD_PRE = 0x0
3741 22:57:59.070910 WR_PRE = 0x1
3742 22:57:59.071023 WR_PST = 0x0
3743 22:57:59.073835 DBI_WR = 0x0
3744 22:57:59.073934 DBI_RD = 0x0
3745 22:57:59.077334 OTF = 0x1
3746 22:57:59.080288 ===================================
3747 22:57:59.083818 ===================================
3748 22:57:59.083951 ANA top config
3749 22:57:59.087172 ===================================
3750 22:57:59.090674 DLL_ASYNC_EN = 0
3751 22:57:59.093751 ALL_SLAVE_EN = 1
3752 22:57:59.093871 NEW_RANK_MODE = 1
3753 22:57:59.097241 DLL_IDLE_MODE = 1
3754 22:57:59.100297 LP45_APHY_COMB_EN = 1
3755 22:57:59.103732 TX_ODT_DIS = 1
3756 22:57:59.107072 NEW_8X_MODE = 1
3757 22:57:59.110399 ===================================
3758 22:57:59.114017 ===================================
3759 22:57:59.114148 data_rate = 1200
3760 22:57:59.116777 CKR = 1
3761 22:57:59.120172 DQ_P2S_RATIO = 8
3762 22:57:59.123559 ===================================
3763 22:57:59.126858 CA_P2S_RATIO = 8
3764 22:57:59.130351 DQ_CA_OPEN = 0
3765 22:57:59.133977 DQ_SEMI_OPEN = 0
3766 22:57:59.134101 CA_SEMI_OPEN = 0
3767 22:57:59.136670 CA_FULL_RATE = 0
3768 22:57:59.140512 DQ_CKDIV4_EN = 1
3769 22:57:59.143276 CA_CKDIV4_EN = 1
3770 22:57:59.146715 CA_PREDIV_EN = 0
3771 22:57:59.150018 PH8_DLY = 0
3772 22:57:59.150143 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3773 22:57:59.153394 DQ_AAMCK_DIV = 4
3774 22:57:59.156810 CA_AAMCK_DIV = 4
3775 22:57:59.160027 CA_ADMCK_DIV = 4
3776 22:57:59.163218 DQ_TRACK_CA_EN = 0
3777 22:57:59.167144 CA_PICK = 600
3778 22:57:59.167274 CA_MCKIO = 600
3779 22:57:59.170131 MCKIO_SEMI = 0
3780 22:57:59.173303 PLL_FREQ = 2288
3781 22:57:59.176673 DQ_UI_PI_RATIO = 32
3782 22:57:59.179890 CA_UI_PI_RATIO = 0
3783 22:57:59.183135 ===================================
3784 22:57:59.186937 ===================================
3785 22:57:59.189847 memory_type:LPDDR4
3786 22:57:59.189961 GP_NUM : 10
3787 22:57:59.193503 SRAM_EN : 1
3788 22:57:59.193622 MD32_EN : 0
3789 22:57:59.196651 ===================================
3790 22:57:59.199792 [ANA_INIT] >>>>>>>>>>>>>>
3791 22:57:59.203192 <<<<<< [CONFIGURE PHASE]: ANA_TX
3792 22:57:59.207027 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3793 22:57:59.209910 ===================================
3794 22:57:59.213615 data_rate = 1200,PCW = 0X5800
3795 22:57:59.217108 ===================================
3796 22:57:59.219913 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3797 22:57:59.223776 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3798 22:57:59.230028 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3799 22:57:59.233280 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3800 22:57:59.240074 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3801 22:57:59.243216 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3802 22:57:59.243325 [ANA_INIT] flow start
3803 22:57:59.246399 [ANA_INIT] PLL >>>>>>>>
3804 22:57:59.249767 [ANA_INIT] PLL <<<<<<<<
3805 22:57:59.249867 [ANA_INIT] MIDPI >>>>>>>>
3806 22:57:59.253484 [ANA_INIT] MIDPI <<<<<<<<
3807 22:57:59.256493 [ANA_INIT] DLL >>>>>>>>
3808 22:57:59.256588 [ANA_INIT] flow end
3809 22:57:59.263096 ============ LP4 DIFF to SE enter ============
3810 22:57:59.266596 ============ LP4 DIFF to SE exit ============
3811 22:57:59.266707 [ANA_INIT] <<<<<<<<<<<<<
3812 22:57:59.270005 [Flow] Enable top DCM control >>>>>
3813 22:57:59.273023 [Flow] Enable top DCM control <<<<<
3814 22:57:59.276621 Enable DLL master slave shuffle
3815 22:57:59.283121 ==============================================================
3816 22:57:59.286629 Gating Mode config
3817 22:57:59.289696 ==============================================================
3818 22:57:59.292979 Config description:
3819 22:57:59.303005 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3820 22:57:59.309769 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3821 22:57:59.313164 SELPH_MODE 0: By rank 1: By Phase
3822 22:57:59.319519 ==============================================================
3823 22:57:59.322974 GAT_TRACK_EN = 1
3824 22:57:59.326176 RX_GATING_MODE = 2
3825 22:57:59.326289 RX_GATING_TRACK_MODE = 2
3826 22:57:59.329866 SELPH_MODE = 1
3827 22:57:59.333084 PICG_EARLY_EN = 1
3828 22:57:59.336292 VALID_LAT_VALUE = 1
3829 22:57:59.343282 ==============================================================
3830 22:57:59.346608 Enter into Gating configuration >>>>
3831 22:57:59.349864 Exit from Gating configuration <<<<
3832 22:57:59.352618 Enter into DVFS_PRE_config >>>>>
3833 22:57:59.363151 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3834 22:57:59.365959 Exit from DVFS_PRE_config <<<<<
3835 22:57:59.369926 Enter into PICG configuration >>>>
3836 22:57:59.372760 Exit from PICG configuration <<<<
3837 22:57:59.376478 [RX_INPUT] configuration >>>>>
3838 22:57:59.379550 [RX_INPUT] configuration <<<<<
3839 22:57:59.382715 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3840 22:57:59.389333 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3841 22:57:59.395933 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3842 22:57:59.402622 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3843 22:57:59.405940 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3844 22:57:59.412776 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3845 22:57:59.415971 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3846 22:57:59.422686 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3847 22:57:59.425814 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3848 22:57:59.429197 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3849 22:57:59.432341 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3850 22:57:59.439092 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3851 22:57:59.442636 ===================================
3852 22:57:59.445529 LPDDR4 DRAM CONFIGURATION
3853 22:57:59.449030 ===================================
3854 22:57:59.449136 EX_ROW_EN[0] = 0x0
3855 22:57:59.452074 EX_ROW_EN[1] = 0x0
3856 22:57:59.452164 LP4Y_EN = 0x0
3857 22:57:59.455828 WORK_FSP = 0x0
3858 22:57:59.455948 WL = 0x2
3859 22:57:59.459101 RL = 0x2
3860 22:57:59.459195 BL = 0x2
3861 22:57:59.462317 RPST = 0x0
3862 22:57:59.462410 RD_PRE = 0x0
3863 22:57:59.465842 WR_PRE = 0x1
3864 22:57:59.465939 WR_PST = 0x0
3865 22:57:59.469422 DBI_WR = 0x0
3866 22:57:59.469551 DBI_RD = 0x0
3867 22:57:59.472317 OTF = 0x1
3868 22:57:59.475721 ===================================
3869 22:57:59.478920 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3870 22:57:59.482461 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3871 22:57:59.489084 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3872 22:57:59.492349 ===================================
3873 22:57:59.492449 LPDDR4 DRAM CONFIGURATION
3874 22:57:59.495424 ===================================
3875 22:57:59.498575 EX_ROW_EN[0] = 0x10
3876 22:57:59.502394 EX_ROW_EN[1] = 0x0
3877 22:57:59.502520 LP4Y_EN = 0x0
3878 22:57:59.505535 WORK_FSP = 0x0
3879 22:57:59.505672 WL = 0x2
3880 22:57:59.509283 RL = 0x2
3881 22:57:59.509375 BL = 0x2
3882 22:57:59.512160 RPST = 0x0
3883 22:57:59.512240 RD_PRE = 0x0
3884 22:57:59.515593 WR_PRE = 0x1
3885 22:57:59.515674 WR_PST = 0x0
3886 22:57:59.518896 DBI_WR = 0x0
3887 22:57:59.518979 DBI_RD = 0x0
3888 22:57:59.521932 OTF = 0x1
3889 22:57:59.525365 ===================================
3890 22:57:59.531855 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3891 22:57:59.535414 nWR fixed to 30
3892 22:57:59.535555 [ModeRegInit_LP4] CH0 RK0
3893 22:57:59.538596 [ModeRegInit_LP4] CH0 RK1
3894 22:57:59.542287 [ModeRegInit_LP4] CH1 RK0
3895 22:57:59.545307 [ModeRegInit_LP4] CH1 RK1
3896 22:57:59.545395 match AC timing 17
3897 22:57:59.552452 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3898 22:57:59.555636 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3899 22:57:59.559073 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3900 22:57:59.565485 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3901 22:57:59.568779 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3902 22:57:59.568874 ==
3903 22:57:59.571846 Dram Type= 6, Freq= 0, CH_0, rank 0
3904 22:57:59.575029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3905 22:57:59.575125 ==
3906 22:57:59.581787 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3907 22:57:59.588671 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3908 22:57:59.591907 [CA 0] Center 35 (5~66) winsize 62
3909 22:57:59.594957 [CA 1] Center 36 (5~67) winsize 63
3910 22:57:59.598423 [CA 2] Center 33 (3~64) winsize 62
3911 22:57:59.601694 [CA 3] Center 33 (2~64) winsize 63
3912 22:57:59.605171 [CA 4] Center 33 (2~64) winsize 63
3913 22:57:59.608601 [CA 5] Center 32 (2~63) winsize 62
3914 22:57:59.608698
3915 22:57:59.611942 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3916 22:57:59.612040
3917 22:57:59.615319 [CATrainingPosCal] consider 1 rank data
3918 22:57:59.618342 u2DelayCellTimex100 = 270/100 ps
3919 22:57:59.621740 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3920 22:57:59.625350 CA1 delay=36 (5~67),Diff = 4 PI (38 cell)
3921 22:57:59.628497 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3922 22:57:59.632151 CA3 delay=33 (2~64),Diff = 1 PI (9 cell)
3923 22:57:59.635510 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3924 22:57:59.638394 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3925 22:57:59.638499
3926 22:57:59.642175 CA PerBit enable=1, Macro0, CA PI delay=32
3927 22:57:59.645365
3928 22:57:59.645495 [CBTSetCACLKResult] CA Dly = 32
3929 22:57:59.648556 CS Dly: 3 (0~34)
3930 22:57:59.648646 ==
3931 22:57:59.652136 Dram Type= 6, Freq= 0, CH_0, rank 1
3932 22:57:59.655429 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3933 22:57:59.655524 ==
3934 22:57:59.661783 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3935 22:57:59.668215 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3936 22:57:59.671947 [CA 0] Center 35 (5~66) winsize 62
3937 22:57:59.674953 [CA 1] Center 35 (5~66) winsize 62
3938 22:57:59.678393 [CA 2] Center 33 (3~64) winsize 62
3939 22:57:59.681385 [CA 3] Center 33 (3~64) winsize 62
3940 22:57:59.685020 [CA 4] Center 32 (2~63) winsize 62
3941 22:57:59.687958 [CA 5] Center 32 (2~63) winsize 62
3942 22:57:59.688124
3943 22:57:59.691819 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3944 22:57:59.691916
3945 22:57:59.694743 [CATrainingPosCal] consider 2 rank data
3946 22:57:59.698095 u2DelayCellTimex100 = 270/100 ps
3947 22:57:59.701713 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3948 22:57:59.704821 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3949 22:57:59.708017 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3950 22:57:59.711435 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
3951 22:57:59.714664 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
3952 22:57:59.718245 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3953 22:57:59.721131
3954 22:57:59.724702 CA PerBit enable=1, Macro0, CA PI delay=32
3955 22:57:59.724818
3956 22:57:59.727740 [CBTSetCACLKResult] CA Dly = 32
3957 22:57:59.727850 CS Dly: 4 (0~36)
3958 22:57:59.727957
3959 22:57:59.731222 ----->DramcWriteLeveling(PI) begin...
3960 22:57:59.731357 ==
3961 22:57:59.734675 Dram Type= 6, Freq= 0, CH_0, rank 0
3962 22:57:59.737773 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3963 22:57:59.741250 ==
3964 22:57:59.741363 Write leveling (Byte 0): 35 => 35
3965 22:57:59.744186 Write leveling (Byte 1): 32 => 32
3966 22:57:59.747593 DramcWriteLeveling(PI) end<-----
3967 22:57:59.747692
3968 22:57:59.747781 ==
3969 22:57:59.751278 Dram Type= 6, Freq= 0, CH_0, rank 0
3970 22:57:59.758107 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3971 22:57:59.758229 ==
3972 22:57:59.758300 [Gating] SW mode calibration
3973 22:57:59.767690 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3974 22:57:59.771328 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3975 22:57:59.777445 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3976 22:57:59.781448 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3977 22:57:59.784149 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3978 22:57:59.787390 0 9 12 | B1->B0 | 3434 2c2c | 1 1 | (1 1) (1 0)
3979 22:57:59.794317 0 9 16 | B1->B0 | 2f2f 2323 | 0 0 | (0 1) (0 0)
3980 22:57:59.797690 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3981 22:57:59.801503 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3982 22:57:59.807407 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3983 22:57:59.811126 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3984 22:57:59.814235 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3985 22:57:59.821113 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3986 22:57:59.823941 0 10 12 | B1->B0 | 2323 3737 | 0 0 | (0 0) (0 0)
3987 22:57:59.827810 0 10 16 | B1->B0 | 3636 4646 | 0 0 | (0 0) (0 0)
3988 22:57:59.834072 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3989 22:57:59.837863 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3990 22:57:59.840851 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3991 22:57:59.847082 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3992 22:57:59.850524 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3993 22:57:59.853823 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3994 22:57:59.860842 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3995 22:57:59.863716 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3996 22:57:59.867224 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3997 22:57:59.873935 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3998 22:57:59.877214 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3999 22:57:59.880594 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4000 22:57:59.886944 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4001 22:57:59.890304 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4002 22:57:59.893772 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4003 22:57:59.900298 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4004 22:57:59.903491 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4005 22:57:59.907155 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4006 22:57:59.913664 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4007 22:57:59.916967 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4008 22:57:59.920156 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4009 22:57:59.926659 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4010 22:57:59.930413 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4011 22:57:59.933855 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4012 22:57:59.936847 Total UI for P1: 0, mck2ui 16
4013 22:57:59.940085 best dqsien dly found for B0: ( 0, 13, 14)
4014 22:57:59.943700 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4015 22:57:59.946723 Total UI for P1: 0, mck2ui 16
4016 22:57:59.950035 best dqsien dly found for B1: ( 0, 13, 16)
4017 22:57:59.956585 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4018 22:57:59.960117 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4019 22:57:59.960255
4020 22:57:59.963289 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4021 22:57:59.966476 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4022 22:57:59.970016 [Gating] SW calibration Done
4023 22:57:59.970128 ==
4024 22:57:59.974109 Dram Type= 6, Freq= 0, CH_0, rank 0
4025 22:57:59.977337 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4026 22:57:59.977445 ==
4027 22:57:59.980423 RX Vref Scan: 0
4028 22:57:59.980526
4029 22:57:59.980594 RX Vref 0 -> 0, step: 1
4030 22:57:59.980655
4031 22:57:59.983891 RX Delay -230 -> 252, step: 16
4032 22:57:59.986921 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4033 22:57:59.993203 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4034 22:57:59.996634 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4035 22:58:00.000329 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4036 22:58:00.003214 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4037 22:58:00.006967 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4038 22:58:00.013343 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4039 22:58:00.016668 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4040 22:58:00.019906 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4041 22:58:00.023271 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4042 22:58:00.030210 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4043 22:58:00.033450 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4044 22:58:00.036639 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4045 22:58:00.039686 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4046 22:58:00.046763 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4047 22:58:00.049954 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4048 22:58:00.050070 ==
4049 22:58:00.053287 Dram Type= 6, Freq= 0, CH_0, rank 0
4050 22:58:00.056562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4051 22:58:00.056669 ==
4052 22:58:00.060223 DQS Delay:
4053 22:58:00.060326 DQS0 = 0, DQS1 = 0
4054 22:58:00.060416 DQM Delay:
4055 22:58:00.063272 DQM0 = 49, DQM1 = 45
4056 22:58:00.063367 DQ Delay:
4057 22:58:00.066267 DQ0 =49, DQ1 =57, DQ2 =41, DQ3 =41
4058 22:58:00.069815 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4059 22:58:00.073063 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =41
4060 22:58:00.076469 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =57
4061 22:58:00.076586
4062 22:58:00.076677
4063 22:58:00.076760 ==
4064 22:58:00.079874 Dram Type= 6, Freq= 0, CH_0, rank 0
4065 22:58:00.086029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4066 22:58:00.086159 ==
4067 22:58:00.086255
4068 22:58:00.086338
4069 22:58:00.086417 TX Vref Scan disable
4070 22:58:00.089778 == TX Byte 0 ==
4071 22:58:00.093297 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4072 22:58:00.100232 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4073 22:58:00.100369 == TX Byte 1 ==
4074 22:58:00.103021 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4075 22:58:00.109840 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4076 22:58:00.109970 ==
4077 22:58:00.113481 Dram Type= 6, Freq= 0, CH_0, rank 0
4078 22:58:00.116444 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4079 22:58:00.116543 ==
4080 22:58:00.116609
4081 22:58:00.116669
4082 22:58:00.119665 TX Vref Scan disable
4083 22:58:00.123207 == TX Byte 0 ==
4084 22:58:00.126343 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4085 22:58:00.129533 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4086 22:58:00.133058 == TX Byte 1 ==
4087 22:58:00.136356 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4088 22:58:00.140137 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4089 22:58:00.140252
4090 22:58:00.140321 [DATLAT]
4091 22:58:00.143553 Freq=600, CH0 RK0
4092 22:58:00.143650
4093 22:58:00.143721 DATLAT Default: 0x9
4094 22:58:00.146831 0, 0xFFFF, sum = 0
4095 22:58:00.146928 1, 0xFFFF, sum = 0
4096 22:58:00.149991 2, 0xFFFF, sum = 0
4097 22:58:00.150078 3, 0xFFFF, sum = 0
4098 22:58:00.153104 4, 0xFFFF, sum = 0
4099 22:58:00.156420 5, 0xFFFF, sum = 0
4100 22:58:00.156496 6, 0xFFFF, sum = 0
4101 22:58:00.159843 7, 0xFFFF, sum = 0
4102 22:58:00.159919 8, 0x0, sum = 1
4103 22:58:00.159983 9, 0x0, sum = 2
4104 22:58:00.163217 10, 0x0, sum = 3
4105 22:58:00.163291 11, 0x0, sum = 4
4106 22:58:00.166044 best_step = 9
4107 22:58:00.166119
4108 22:58:00.166180 ==
4109 22:58:00.169724 Dram Type= 6, Freq= 0, CH_0, rank 0
4110 22:58:00.172768 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4111 22:58:00.172849 ==
4112 22:58:00.176166 RX Vref Scan: 1
4113 22:58:00.176243
4114 22:58:00.176314 RX Vref 0 -> 0, step: 1
4115 22:58:00.176377
4116 22:58:00.179565 RX Delay -163 -> 252, step: 8
4117 22:58:00.179679
4118 22:58:00.182828 Set Vref, RX VrefLevel [Byte0]: 55
4119 22:58:00.186233 [Byte1]: 50
4120 22:58:00.190085
4121 22:58:00.190165 Final RX Vref Byte 0 = 55 to rank0
4122 22:58:00.193948 Final RX Vref Byte 1 = 50 to rank0
4123 22:58:00.196899 Final RX Vref Byte 0 = 55 to rank1
4124 22:58:00.200567 Final RX Vref Byte 1 = 50 to rank1==
4125 22:58:00.203998 Dram Type= 6, Freq= 0, CH_0, rank 0
4126 22:58:00.210204 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4127 22:58:00.210371 ==
4128 22:58:00.210499 DQS Delay:
4129 22:58:00.210616 DQS0 = 0, DQS1 = 0
4130 22:58:00.213817 DQM Delay:
4131 22:58:00.213972 DQM0 = 53, DQM1 = 47
4132 22:58:00.217056 DQ Delay:
4133 22:58:00.220508 DQ0 =52, DQ1 =56, DQ2 =48, DQ3 =48
4134 22:58:00.220658 DQ4 =56, DQ5 =44, DQ6 =64, DQ7 =60
4135 22:58:00.223422 DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =40
4136 22:58:00.230008 DQ12 =56, DQ13 =52, DQ14 =56, DQ15 =52
4137 22:58:00.230194
4138 22:58:00.230323
4139 22:58:00.237241 [DQSOSCAuto] RK0, (LSB)MR18= 0x7164, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 388 ps
4140 22:58:00.240526 CH0 RK0: MR19=808, MR18=7164
4141 22:58:00.247448 CH0_RK0: MR19=0x808, MR18=0x7164, DQSOSC=388, MR23=63, INC=174, DEC=116
4142 22:58:00.247585
4143 22:58:00.250449 ----->DramcWriteLeveling(PI) begin...
4144 22:58:00.250546 ==
4145 22:58:00.253947 Dram Type= 6, Freq= 0, CH_0, rank 1
4146 22:58:00.257036 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4147 22:58:00.257153 ==
4148 22:58:00.260266 Write leveling (Byte 0): 35 => 35
4149 22:58:00.263484 Write leveling (Byte 1): 32 => 32
4150 22:58:00.266916 DramcWriteLeveling(PI) end<-----
4151 22:58:00.267023
4152 22:58:00.267092 ==
4153 22:58:00.269915 Dram Type= 6, Freq= 0, CH_0, rank 1
4154 22:58:00.273705 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4155 22:58:00.273831 ==
4156 22:58:00.276793 [Gating] SW mode calibration
4157 22:58:00.283619 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4158 22:58:00.289836 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4159 22:58:00.293473 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4160 22:58:00.296556 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4161 22:58:00.303412 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4162 22:58:00.306361 0 9 12 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
4163 22:58:00.309822 0 9 16 | B1->B0 | 2e2e 2626 | 0 0 | (1 1) (0 0)
4164 22:58:00.316399 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4165 22:58:00.319681 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4166 22:58:00.323441 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4167 22:58:00.329938 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4168 22:58:00.333365 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4169 22:58:00.336610 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4170 22:58:00.343249 0 10 12 | B1->B0 | 2626 2929 | 0 0 | (0 0) (0 0)
4171 22:58:00.346801 0 10 16 | B1->B0 | 4444 4040 | 0 0 | (0 0) (1 1)
4172 22:58:00.349546 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4173 22:58:00.356345 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4174 22:58:00.359624 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4175 22:58:00.362918 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4176 22:58:00.369450 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4177 22:58:00.373086 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4178 22:58:00.376422 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4179 22:58:00.383413 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4180 22:58:00.386050 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4181 22:58:00.389778 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4182 22:58:00.396502 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4183 22:58:00.399238 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4184 22:58:00.402752 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4185 22:58:00.409709 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4186 22:58:00.412520 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4187 22:58:00.415842 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4188 22:58:00.422623 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4189 22:58:00.425990 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4190 22:58:00.429255 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4191 22:58:00.435898 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4192 22:58:00.439730 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4193 22:58:00.442646 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4194 22:58:00.449468 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4195 22:58:00.452626 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4196 22:58:00.456105 Total UI for P1: 0, mck2ui 16
4197 22:58:00.459020 best dqsien dly found for B0: ( 0, 13, 14)
4198 22:58:00.462626 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4199 22:58:00.466146 Total UI for P1: 0, mck2ui 16
4200 22:58:00.469306 best dqsien dly found for B1: ( 0, 13, 16)
4201 22:58:00.473006 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4202 22:58:00.475808 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4203 22:58:00.475899
4204 22:58:00.479183 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4205 22:58:00.485657 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4206 22:58:00.485754 [Gating] SW calibration Done
4207 22:58:00.485843 ==
4208 22:58:00.489414 Dram Type= 6, Freq= 0, CH_0, rank 1
4209 22:58:00.495752 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4210 22:58:00.495853 ==
4211 22:58:00.495942 RX Vref Scan: 0
4212 22:58:00.496024
4213 22:58:00.499649 RX Vref 0 -> 0, step: 1
4214 22:58:00.499740
4215 22:58:00.502482 RX Delay -230 -> 252, step: 16
4216 22:58:00.505483 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4217 22:58:00.509218 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4218 22:58:00.515945 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4219 22:58:00.518714 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4220 22:58:00.522052 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4221 22:58:00.525528 iDelay=218, Bit 5, Center 49 (-102 ~ 201) 304
4222 22:58:00.528776 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4223 22:58:00.535674 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4224 22:58:00.538473 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4225 22:58:00.541844 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4226 22:58:00.545261 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4227 22:58:00.552160 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4228 22:58:00.555343 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4229 22:58:00.558512 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4230 22:58:00.562189 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4231 22:58:00.568261 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4232 22:58:00.568363 ==
4233 22:58:00.571607 Dram Type= 6, Freq= 0, CH_0, rank 1
4234 22:58:00.574988 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4235 22:58:00.575076 ==
4236 22:58:00.575163 DQS Delay:
4237 22:58:00.578213 DQS0 = 0, DQS1 = 0
4238 22:58:00.578300 DQM Delay:
4239 22:58:00.582050 DQM0 = 54, DQM1 = 43
4240 22:58:00.582138 DQ Delay:
4241 22:58:00.585134 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =49
4242 22:58:00.588640 DQ4 =57, DQ5 =49, DQ6 =65, DQ7 =65
4243 22:58:00.591548 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =33
4244 22:58:00.595052 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4245 22:58:00.595143
4246 22:58:00.595230
4247 22:58:00.595312 ==
4248 22:58:00.598418 Dram Type= 6, Freq= 0, CH_0, rank 1
4249 22:58:00.601817 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4250 22:58:00.601912 ==
4251 22:58:00.602017
4252 22:58:00.602113
4253 22:58:00.605119 TX Vref Scan disable
4254 22:58:00.608281 == TX Byte 0 ==
4255 22:58:00.611514 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4256 22:58:00.614911 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4257 22:58:00.618295 == TX Byte 1 ==
4258 22:58:00.621375 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4259 22:58:00.624768 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4260 22:58:00.624875 ==
4261 22:58:00.628480 Dram Type= 6, Freq= 0, CH_0, rank 1
4262 22:58:00.634482 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4263 22:58:00.634597 ==
4264 22:58:00.634667
4265 22:58:00.634729
4266 22:58:00.634788 TX Vref Scan disable
4267 22:58:00.639307 == TX Byte 0 ==
4268 22:58:00.642868 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4269 22:58:00.649059 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4270 22:58:00.649166 == TX Byte 1 ==
4271 22:58:00.652644 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4272 22:58:00.659129 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4273 22:58:00.659229
4274 22:58:00.659297 [DATLAT]
4275 22:58:00.659359 Freq=600, CH0 RK1
4276 22:58:00.659420
4277 22:58:00.662805 DATLAT Default: 0x9
4278 22:58:00.662891 0, 0xFFFF, sum = 0
4279 22:58:00.665723 1, 0xFFFF, sum = 0
4280 22:58:00.665811 2, 0xFFFF, sum = 0
4281 22:58:00.668988 3, 0xFFFF, sum = 0
4282 22:58:00.672325 4, 0xFFFF, sum = 0
4283 22:58:00.672414 5, 0xFFFF, sum = 0
4284 22:58:00.675588 6, 0xFFFF, sum = 0
4285 22:58:00.675676 7, 0xFFFF, sum = 0
4286 22:58:00.679237 8, 0x0, sum = 1
4287 22:58:00.679328 9, 0x0, sum = 2
4288 22:58:00.679396 10, 0x0, sum = 3
4289 22:58:00.682168 11, 0x0, sum = 4
4290 22:58:00.682253 best_step = 9
4291 22:58:00.682320
4292 22:58:00.682381 ==
4293 22:58:00.685765 Dram Type= 6, Freq= 0, CH_0, rank 1
4294 22:58:00.692663 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4295 22:58:00.692799 ==
4296 22:58:00.692866 RX Vref Scan: 0
4297 22:58:00.692928
4298 22:58:00.695626 RX Vref 0 -> 0, step: 1
4299 22:58:00.695712
4300 22:58:00.698740 RX Delay -163 -> 252, step: 8
4301 22:58:00.702368 iDelay=197, Bit 0, Center 52 (-91 ~ 196) 288
4302 22:58:00.708948 iDelay=197, Bit 1, Center 56 (-83 ~ 196) 280
4303 22:58:00.712268 iDelay=197, Bit 2, Center 52 (-91 ~ 196) 288
4304 22:58:00.715818 iDelay=197, Bit 3, Center 52 (-91 ~ 196) 288
4305 22:58:00.718961 iDelay=197, Bit 4, Center 52 (-91 ~ 196) 288
4306 22:58:00.722161 iDelay=197, Bit 5, Center 44 (-99 ~ 188) 288
4307 22:58:00.728498 iDelay=197, Bit 6, Center 60 (-75 ~ 196) 272
4308 22:58:00.732005 iDelay=197, Bit 7, Center 56 (-83 ~ 196) 280
4309 22:58:00.735350 iDelay=197, Bit 8, Center 40 (-99 ~ 180) 280
4310 22:58:00.738606 iDelay=197, Bit 9, Center 36 (-107 ~ 180) 288
4311 22:58:00.741957 iDelay=197, Bit 10, Center 48 (-91 ~ 188) 280
4312 22:58:00.748739 iDelay=197, Bit 11, Center 40 (-99 ~ 180) 280
4313 22:58:00.752015 iDelay=197, Bit 12, Center 52 (-91 ~ 196) 288
4314 22:58:00.755425 iDelay=197, Bit 13, Center 52 (-91 ~ 196) 288
4315 22:58:00.758683 iDelay=197, Bit 14, Center 56 (-83 ~ 196) 280
4316 22:58:00.765084 iDelay=197, Bit 15, Center 52 (-91 ~ 196) 288
4317 22:58:00.765208 ==
4318 22:58:00.768251 Dram Type= 6, Freq= 0, CH_0, rank 1
4319 22:58:00.771977 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4320 22:58:00.772072 ==
4321 22:58:00.772138 DQS Delay:
4322 22:58:00.775047 DQS0 = 0, DQS1 = 0
4323 22:58:00.775131 DQM Delay:
4324 22:58:00.778480 DQM0 = 53, DQM1 = 47
4325 22:58:00.778568 DQ Delay:
4326 22:58:00.782089 DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =52
4327 22:58:00.785301 DQ4 =52, DQ5 =44, DQ6 =60, DQ7 =56
4328 22:58:00.788194 DQ8 =40, DQ9 =36, DQ10 =48, DQ11 =40
4329 22:58:00.791485 DQ12 =52, DQ13 =52, DQ14 =56, DQ15 =52
4330 22:58:00.791571
4331 22:58:00.791636
4332 22:58:00.798296 [DQSOSCAuto] RK1, (LSB)MR18= 0x6729, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 390 ps
4333 22:58:00.801447 CH0 RK1: MR19=808, MR18=6729
4334 22:58:00.808510 CH0_RK1: MR19=0x808, MR18=0x6729, DQSOSC=390, MR23=63, INC=172, DEC=114
4335 22:58:00.811877 [RxdqsGatingPostProcess] freq 600
4336 22:58:00.818008 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4337 22:58:00.821525 Pre-setting of DQS Precalculation
4338 22:58:00.824684 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4339 22:58:00.824787 ==
4340 22:58:00.828157 Dram Type= 6, Freq= 0, CH_1, rank 0
4341 22:58:00.831383 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4342 22:58:00.831485 ==
4343 22:58:00.838154 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4344 22:58:00.844748 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4345 22:58:00.848013 [CA 0] Center 36 (5~67) winsize 63
4346 22:58:00.851682 [CA 1] Center 36 (5~67) winsize 63
4347 22:58:00.854967 [CA 2] Center 34 (4~65) winsize 62
4348 22:58:00.858312 [CA 3] Center 34 (4~65) winsize 62
4349 22:58:00.861783 [CA 4] Center 34 (4~65) winsize 62
4350 22:58:00.864445 [CA 5] Center 33 (3~64) winsize 62
4351 22:58:00.864548
4352 22:58:00.868340 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4353 22:58:00.868432
4354 22:58:00.871686 [CATrainingPosCal] consider 1 rank data
4355 22:58:00.874941 u2DelayCellTimex100 = 270/100 ps
4356 22:58:00.877841 CA0 delay=36 (5~67),Diff = 3 PI (28 cell)
4357 22:58:00.881532 CA1 delay=36 (5~67),Diff = 3 PI (28 cell)
4358 22:58:00.884914 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4359 22:58:00.888040 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4360 22:58:00.891607 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4361 22:58:00.894847 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4362 22:58:00.898045
4363 22:58:00.901445 CA PerBit enable=1, Macro0, CA PI delay=33
4364 22:58:00.901548
4365 22:58:00.904620 [CBTSetCACLKResult] CA Dly = 33
4366 22:58:00.904714 CS Dly: 6 (0~37)
4367 22:58:00.904783 ==
4368 22:58:00.907854 Dram Type= 6, Freq= 0, CH_1, rank 1
4369 22:58:00.910901 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4370 22:58:00.910996 ==
4371 22:58:00.917768 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4372 22:58:00.924561 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4373 22:58:00.927562 [CA 0] Center 36 (5~67) winsize 63
4374 22:58:00.930926 [CA 1] Center 36 (5~67) winsize 63
4375 22:58:00.934171 [CA 2] Center 34 (4~65) winsize 62
4376 22:58:00.937997 [CA 3] Center 34 (3~65) winsize 63
4377 22:58:00.940729 [CA 4] Center 35 (4~66) winsize 63
4378 22:58:00.944060 [CA 5] Center 34 (3~65) winsize 63
4379 22:58:00.944159
4380 22:58:00.947819 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4381 22:58:00.947917
4382 22:58:00.950794 [CATrainingPosCal] consider 2 rank data
4383 22:58:00.954127 u2DelayCellTimex100 = 270/100 ps
4384 22:58:00.957459 CA0 delay=36 (5~67),Diff = 3 PI (28 cell)
4385 22:58:00.961376 CA1 delay=36 (5~67),Diff = 3 PI (28 cell)
4386 22:58:00.964447 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4387 22:58:00.967524 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4388 22:58:00.974213 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4389 22:58:00.977572 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4390 22:58:00.977714
4391 22:58:00.981003 CA PerBit enable=1, Macro0, CA PI delay=33
4392 22:58:00.981197
4393 22:58:00.984259 [CBTSetCACLKResult] CA Dly = 33
4394 22:58:00.984347 CS Dly: 6 (0~38)
4395 22:58:00.984415
4396 22:58:00.987894 ----->DramcWriteLeveling(PI) begin...
4397 22:58:00.987982 ==
4398 22:58:00.990859 Dram Type= 6, Freq= 0, CH_1, rank 0
4399 22:58:00.997630 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4400 22:58:00.997755 ==
4401 22:58:01.000869 Write leveling (Byte 0): 30 => 30
4402 22:58:01.000964 Write leveling (Byte 1): 32 => 32
4403 22:58:01.003984 DramcWriteLeveling(PI) end<-----
4404 22:58:01.004079
4405 22:58:01.007806 ==
4406 22:58:01.007909 Dram Type= 6, Freq= 0, CH_1, rank 0
4407 22:58:01.014042 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4408 22:58:01.014157 ==
4409 22:58:01.017542 [Gating] SW mode calibration
4410 22:58:01.024051 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4411 22:58:01.027550 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4412 22:58:01.034244 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4413 22:58:01.037063 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4414 22:58:01.040778 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 1)
4415 22:58:01.047142 0 9 12 | B1->B0 | 3030 2c2c | 1 1 | (1 0) (0 0)
4416 22:58:01.050638 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4417 22:58:01.054136 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4418 22:58:01.060446 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4419 22:58:01.064066 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4420 22:58:01.067067 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4421 22:58:01.074149 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4422 22:58:01.076849 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4423 22:58:01.080788 0 10 12 | B1->B0 | 3737 3e3e | 0 0 | (0 0) (1 1)
4424 22:58:01.087011 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4425 22:58:01.090115 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4426 22:58:01.093928 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4427 22:58:01.100702 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4428 22:58:01.104031 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4429 22:58:01.107109 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4430 22:58:01.110462 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4431 22:58:01.117030 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4432 22:58:01.120349 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4433 22:58:01.124090 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4434 22:58:01.130645 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4435 22:58:01.133878 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4436 22:58:01.137181 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4437 22:58:01.143711 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4438 22:58:01.147007 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4439 22:58:01.150245 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4440 22:58:01.156629 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4441 22:58:01.160084 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4442 22:58:01.163473 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4443 22:58:01.170401 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4444 22:58:01.173350 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4445 22:58:01.176648 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4446 22:58:01.183466 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4447 22:58:01.186637 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4448 22:58:01.190245 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4449 22:58:01.193555 Total UI for P1: 0, mck2ui 16
4450 22:58:01.196901 best dqsien dly found for B0: ( 0, 13, 10)
4451 22:58:01.200133 Total UI for P1: 0, mck2ui 16
4452 22:58:01.203500 best dqsien dly found for B1: ( 0, 13, 12)
4453 22:58:01.206913 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4454 22:58:01.209875 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4455 22:58:01.209969
4456 22:58:01.216700 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4457 22:58:01.220188 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4458 22:58:01.220281 [Gating] SW calibration Done
4459 22:58:01.223375 ==
4460 22:58:01.226549 Dram Type= 6, Freq= 0, CH_1, rank 0
4461 22:58:01.230156 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4462 22:58:01.230247 ==
4463 22:58:01.230313 RX Vref Scan: 0
4464 22:58:01.230375
4465 22:58:01.233138 RX Vref 0 -> 0, step: 1
4466 22:58:01.233228
4467 22:58:01.236453 RX Delay -230 -> 252, step: 16
4468 22:58:01.239809 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4469 22:58:01.243155 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4470 22:58:01.249482 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4471 22:58:01.252993 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4472 22:58:01.256228 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4473 22:58:01.259468 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4474 22:58:01.265892 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4475 22:58:01.269836 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4476 22:58:01.272783 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4477 22:58:01.275852 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4478 22:58:01.279222 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4479 22:58:01.286208 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4480 22:58:01.289238 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4481 22:58:01.293091 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4482 22:58:01.296104 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4483 22:58:01.302466 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4484 22:58:01.302584 ==
4485 22:58:01.306561 Dram Type= 6, Freq= 0, CH_1, rank 0
4486 22:58:01.309055 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4487 22:58:01.309145 ==
4488 22:58:01.309211 DQS Delay:
4489 22:58:01.312490 DQS0 = 0, DQS1 = 0
4490 22:58:01.312576 DQM Delay:
4491 22:58:01.315870 DQM0 = 49, DQM1 = 46
4492 22:58:01.315959 DQ Delay:
4493 22:58:01.319775 DQ0 =57, DQ1 =41, DQ2 =41, DQ3 =49
4494 22:58:01.323094 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =41
4495 22:58:01.326168 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4496 22:58:01.329215 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4497 22:58:01.329300
4498 22:58:01.329366
4499 22:58:01.329427 ==
4500 22:58:01.332450 Dram Type= 6, Freq= 0, CH_1, rank 0
4501 22:58:01.336118 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4502 22:58:01.336204 ==
4503 22:58:01.339478
4504 22:58:01.339561
4505 22:58:01.339626 TX Vref Scan disable
4506 22:58:01.343003 == TX Byte 0 ==
4507 22:58:01.346296 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4508 22:58:01.349342 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4509 22:58:01.352708 == TX Byte 1 ==
4510 22:58:01.355721 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4511 22:58:01.358814 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4512 22:58:01.362257 ==
4513 22:58:01.365764 Dram Type= 6, Freq= 0, CH_1, rank 0
4514 22:58:01.368980 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4515 22:58:01.369066 ==
4516 22:58:01.369133
4517 22:58:01.369271
4518 22:58:01.372033 TX Vref Scan disable
4519 22:58:01.372118 == TX Byte 0 ==
4520 22:58:01.378695 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4521 22:58:01.382310 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4522 22:58:01.382398 == TX Byte 1 ==
4523 22:58:01.388546 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4524 22:58:01.392209 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4525 22:58:01.392328
4526 22:58:01.392435 [DATLAT]
4527 22:58:01.395214 Freq=600, CH1 RK0
4528 22:58:01.395298
4529 22:58:01.395364 DATLAT Default: 0x9
4530 22:58:01.398915 0, 0xFFFF, sum = 0
4531 22:58:01.399002 1, 0xFFFF, sum = 0
4532 22:58:01.402153 2, 0xFFFF, sum = 0
4533 22:58:01.405919 3, 0xFFFF, sum = 0
4534 22:58:01.406010 4, 0xFFFF, sum = 0
4535 22:58:01.408539 5, 0xFFFF, sum = 0
4536 22:58:01.408624 6, 0xFFFF, sum = 0
4537 22:58:01.411902 7, 0xFFFF, sum = 0
4538 22:58:01.411987 8, 0x0, sum = 1
4539 22:58:01.412054 9, 0x0, sum = 2
4540 22:58:01.415477 10, 0x0, sum = 3
4541 22:58:01.415562 11, 0x0, sum = 4
4542 22:58:01.418539 best_step = 9
4543 22:58:01.418651
4544 22:58:01.418745 ==
4545 22:58:01.422182 Dram Type= 6, Freq= 0, CH_1, rank 0
4546 22:58:01.425293 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4547 22:58:01.425377 ==
4548 22:58:01.428483 RX Vref Scan: 1
4549 22:58:01.428565
4550 22:58:01.428631 RX Vref 0 -> 0, step: 1
4551 22:58:01.428693
4552 22:58:01.431758 RX Delay -163 -> 252, step: 8
4553 22:58:01.431842
4554 22:58:01.435266 Set Vref, RX VrefLevel [Byte0]: 55
4555 22:58:01.438558 [Byte1]: 48
4556 22:58:01.442400
4557 22:58:01.442485 Final RX Vref Byte 0 = 55 to rank0
4558 22:58:01.446056 Final RX Vref Byte 1 = 48 to rank0
4559 22:58:01.449504 Final RX Vref Byte 0 = 55 to rank1
4560 22:58:01.453115 Final RX Vref Byte 1 = 48 to rank1==
4561 22:58:01.455750 Dram Type= 6, Freq= 0, CH_1, rank 0
4562 22:58:01.462590 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4563 22:58:01.462682 ==
4564 22:58:01.462749 DQS Delay:
4565 22:58:01.462811 DQS0 = 0, DQS1 = 0
4566 22:58:01.465620 DQM Delay:
4567 22:58:01.465719 DQM0 = 48, DQM1 = 45
4568 22:58:01.469241 DQ Delay:
4569 22:58:01.472464 DQ0 =52, DQ1 =40, DQ2 =40, DQ3 =48
4570 22:58:01.472551 DQ4 =48, DQ5 =56, DQ6 =56, DQ7 =48
4571 22:58:01.475736 DQ8 =32, DQ9 =36, DQ10 =44, DQ11 =36
4572 22:58:01.482291 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =60
4573 22:58:01.482385
4574 22:58:01.482451
4575 22:58:01.489183 [DQSOSCAuto] RK0, (LSB)MR18= 0x456b, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
4576 22:58:01.492213 CH1 RK0: MR19=808, MR18=456B
4577 22:58:01.499136 CH1_RK0: MR19=0x808, MR18=0x456B, DQSOSC=389, MR23=63, INC=173, DEC=115
4578 22:58:01.499226
4579 22:58:01.502315 ----->DramcWriteLeveling(PI) begin...
4580 22:58:01.502400 ==
4581 22:58:01.505289 Dram Type= 6, Freq= 0, CH_1, rank 1
4582 22:58:01.509092 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4583 22:58:01.509178 ==
4584 22:58:01.512367 Write leveling (Byte 0): 29 => 29
4585 22:58:01.515529 Write leveling (Byte 1): 30 => 30
4586 22:58:01.518775 DramcWriteLeveling(PI) end<-----
4587 22:58:01.518859
4588 22:58:01.518926 ==
4589 22:58:01.522117 Dram Type= 6, Freq= 0, CH_1, rank 1
4590 22:58:01.525550 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4591 22:58:01.525686 ==
4592 22:58:01.528783 [Gating] SW mode calibration
4593 22:58:01.535550 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4594 22:58:01.542202 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4595 22:58:01.545729 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4596 22:58:01.552002 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4597 22:58:01.555683 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
4598 22:58:01.559011 0 9 12 | B1->B0 | 2e2e 2f2f | 1 1 | (1 0) (1 1)
4599 22:58:01.565138 0 9 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4600 22:58:01.568454 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4601 22:58:01.572049 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4602 22:58:01.578617 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4603 22:58:01.582020 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4604 22:58:01.585249 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4605 22:58:01.588488 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4606 22:58:01.594925 0 10 12 | B1->B0 | 3c3b 3838 | 1 0 | (0 0) (0 0)
4607 22:58:01.598492 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4608 22:58:01.601736 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4609 22:58:01.608195 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4610 22:58:01.611420 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4611 22:58:01.615093 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4612 22:58:01.621812 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4613 22:58:01.624947 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4614 22:58:01.628078 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4615 22:58:01.634859 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4616 22:58:01.638131 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4617 22:58:01.641622 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4618 22:58:01.648110 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4619 22:58:01.651736 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4620 22:58:01.654901 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4621 22:58:01.661482 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4622 22:58:01.664609 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4623 22:58:01.668061 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4624 22:58:01.674656 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4625 22:58:01.678071 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4626 22:58:01.681175 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4627 22:58:01.688409 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4628 22:58:01.691653 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4629 22:58:01.694989 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4630 22:58:01.701311 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4631 22:58:01.701415 Total UI for P1: 0, mck2ui 16
4632 22:58:01.705019 best dqsien dly found for B1: ( 0, 13, 8)
4633 22:58:01.711252 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4634 22:58:01.714802 Total UI for P1: 0, mck2ui 16
4635 22:58:01.718036 best dqsien dly found for B0: ( 0, 13, 12)
4636 22:58:01.721681 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4637 22:58:01.724767 best DQS1 dly(MCK, UI, PI) = (0, 13, 8)
4638 22:58:01.724858
4639 22:58:01.728586 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4640 22:58:01.731475 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 8)
4641 22:58:01.734974 [Gating] SW calibration Done
4642 22:58:01.735072 ==
4643 22:58:01.738464 Dram Type= 6, Freq= 0, CH_1, rank 1
4644 22:58:01.741550 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4645 22:58:01.741685 ==
4646 22:58:01.744749 RX Vref Scan: 0
4647 22:58:01.744838
4648 22:58:01.747980 RX Vref 0 -> 0, step: 1
4649 22:58:01.748143
4650 22:58:01.748270 RX Delay -230 -> 252, step: 16
4651 22:58:01.754792 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4652 22:58:01.757654 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4653 22:58:01.761352 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4654 22:58:01.764420 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4655 22:58:01.771476 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4656 22:58:01.774378 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4657 22:58:01.778224 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4658 22:58:01.781358 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4659 22:58:01.784443 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4660 22:58:01.791058 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4661 22:58:01.794617 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4662 22:58:01.797769 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4663 22:58:01.801255 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4664 22:58:01.807986 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4665 22:58:01.811124 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4666 22:58:01.814517 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4667 22:58:01.814640 ==
4668 22:58:01.817992 Dram Type= 6, Freq= 0, CH_1, rank 1
4669 22:58:01.821158 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4670 22:58:01.824445 ==
4671 22:58:01.824538 DQS Delay:
4672 22:58:01.824604 DQS0 = 0, DQS1 = 0
4673 22:58:01.828117 DQM Delay:
4674 22:58:01.828207 DQM0 = 50, DQM1 = 47
4675 22:58:01.831308 DQ Delay:
4676 22:58:01.831394 DQ0 =49, DQ1 =49, DQ2 =33, DQ3 =49
4677 22:58:01.834312 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49
4678 22:58:01.837881 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4679 22:58:01.841032 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =57
4680 22:58:01.841124
4681 22:58:01.844235
4682 22:58:01.844323 ==
4683 22:58:01.847946 Dram Type= 6, Freq= 0, CH_1, rank 1
4684 22:58:01.851119 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4685 22:58:01.851211 ==
4686 22:58:01.851277
4687 22:58:01.851338
4688 22:58:01.854279 TX Vref Scan disable
4689 22:58:01.854383 == TX Byte 0 ==
4690 22:58:01.860808 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4691 22:58:01.864236 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4692 22:58:01.864337 == TX Byte 1 ==
4693 22:58:01.870796 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4694 22:58:01.874036 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4695 22:58:01.874136 ==
4696 22:58:01.877598 Dram Type= 6, Freq= 0, CH_1, rank 1
4697 22:58:01.880722 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4698 22:58:01.880815 ==
4699 22:58:01.880880
4700 22:58:01.880941
4701 22:58:01.884418 TX Vref Scan disable
4702 22:58:01.887204 == TX Byte 0 ==
4703 22:58:01.890571 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4704 22:58:01.893803 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4705 22:58:01.897321 == TX Byte 1 ==
4706 22:58:01.900731 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4707 22:58:01.903749 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4708 22:58:01.903838
4709 22:58:01.907304 [DATLAT]
4710 22:58:01.907393 Freq=600, CH1 RK1
4711 22:58:01.907458
4712 22:58:01.910662 DATLAT Default: 0x9
4713 22:58:01.910781 0, 0xFFFF, sum = 0
4714 22:58:01.913796 1, 0xFFFF, sum = 0
4715 22:58:01.913891 2, 0xFFFF, sum = 0
4716 22:58:01.917203 3, 0xFFFF, sum = 0
4717 22:58:01.917288 4, 0xFFFF, sum = 0
4718 22:58:01.920891 5, 0xFFFF, sum = 0
4719 22:58:01.920977 6, 0xFFFF, sum = 0
4720 22:58:01.923695 7, 0xFFFF, sum = 0
4721 22:58:01.923780 8, 0x0, sum = 1
4722 22:58:01.926795 9, 0x0, sum = 2
4723 22:58:01.926881 10, 0x0, sum = 3
4724 22:58:01.930095 11, 0x0, sum = 4
4725 22:58:01.930182 best_step = 9
4726 22:58:01.930248
4727 22:58:01.930309 ==
4728 22:58:01.933466 Dram Type= 6, Freq= 0, CH_1, rank 1
4729 22:58:01.940318 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4730 22:58:01.940422 ==
4731 22:58:01.940490 RX Vref Scan: 0
4732 22:58:01.940551
4733 22:58:01.943889 RX Vref 0 -> 0, step: 1
4734 22:58:01.943975
4735 22:58:01.946969 RX Delay -163 -> 252, step: 8
4736 22:58:01.950091 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4737 22:58:01.956897 iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288
4738 22:58:01.960064 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4739 22:58:01.963458 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4740 22:58:01.966910 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4741 22:58:01.969697 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4742 22:58:01.976392 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4743 22:58:01.979824 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4744 22:58:01.983018 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4745 22:58:01.986485 iDelay=205, Bit 9, Center 36 (-107 ~ 180) 288
4746 22:58:01.990022 iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296
4747 22:58:01.996474 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4748 22:58:02.000121 iDelay=205, Bit 12, Center 56 (-91 ~ 204) 296
4749 22:58:02.003273 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4750 22:58:02.006524 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4751 22:58:02.013042 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4752 22:58:02.013173 ==
4753 22:58:02.016605 Dram Type= 6, Freq= 0, CH_1, rank 1
4754 22:58:02.019657 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4755 22:58:02.019753 ==
4756 22:58:02.019822 DQS Delay:
4757 22:58:02.022829 DQS0 = 0, DQS1 = 0
4758 22:58:02.022918 DQM Delay:
4759 22:58:02.026715 DQM0 = 49, DQM1 = 46
4760 22:58:02.026807 DQ Delay:
4761 22:58:02.029558 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4762 22:58:02.032953 DQ4 =48, DQ5 =60, DQ6 =60, DQ7 =48
4763 22:58:02.036334 DQ8 =32, DQ9 =36, DQ10 =48, DQ11 =40
4764 22:58:02.039300 DQ12 =56, DQ13 =52, DQ14 =52, DQ15 =52
4765 22:58:02.039392
4766 22:58:02.039460
4767 22:58:02.046599 [DQSOSCAuto] RK1, (LSB)MR18= 0x6e26, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 389 ps
4768 22:58:02.049816 CH1 RK1: MR19=808, MR18=6E26
4769 22:58:02.055967 CH1_RK1: MR19=0x808, MR18=0x6E26, DQSOSC=389, MR23=63, INC=173, DEC=115
4770 22:58:02.059630 [RxdqsGatingPostProcess] freq 600
4771 22:58:02.065996 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4772 22:58:02.069509 Pre-setting of DQS Precalculation
4773 22:58:02.072970 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4774 22:58:02.079247 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4775 22:58:02.086080 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4776 22:58:02.086182
4777 22:58:02.086249
4778 22:58:02.089482 [Calibration Summary] 1200 Mbps
4779 22:58:02.092929 CH 0, Rank 0
4780 22:58:02.093017 SW Impedance : PASS
4781 22:58:02.096372 DUTY Scan : NO K
4782 22:58:02.099118 ZQ Calibration : PASS
4783 22:58:02.099230 Jitter Meter : NO K
4784 22:58:02.102714 CBT Training : PASS
4785 22:58:02.106273 Write leveling : PASS
4786 22:58:02.106364 RX DQS gating : PASS
4787 22:58:02.109093 RX DQ/DQS(RDDQC) : PASS
4788 22:58:02.109179 TX DQ/DQS : PASS
4789 22:58:02.112381 RX DATLAT : PASS
4790 22:58:02.115883 RX DQ/DQS(Engine): PASS
4791 22:58:02.115972 TX OE : NO K
4792 22:58:02.119096 All Pass.
4793 22:58:02.119210
4794 22:58:02.119367 CH 0, Rank 1
4795 22:58:02.122586 SW Impedance : PASS
4796 22:58:02.122733 DUTY Scan : NO K
4797 22:58:02.125781 ZQ Calibration : PASS
4798 22:58:02.128995 Jitter Meter : NO K
4799 22:58:02.129083 CBT Training : PASS
4800 22:58:02.132633 Write leveling : PASS
4801 22:58:02.135786 RX DQS gating : PASS
4802 22:58:02.135880 RX DQ/DQS(RDDQC) : PASS
4803 22:58:02.139160 TX DQ/DQS : PASS
4804 22:58:02.142445 RX DATLAT : PASS
4805 22:58:02.142535 RX DQ/DQS(Engine): PASS
4806 22:58:02.145512 TX OE : NO K
4807 22:58:02.145646 All Pass.
4808 22:58:02.145715
4809 22:58:02.148905 CH 1, Rank 0
4810 22:58:02.148990 SW Impedance : PASS
4811 22:58:02.152155 DUTY Scan : NO K
4812 22:58:02.155723 ZQ Calibration : PASS
4813 22:58:02.155812 Jitter Meter : NO K
4814 22:58:02.158856 CBT Training : PASS
4815 22:58:02.162305 Write leveling : PASS
4816 22:58:02.162394 RX DQS gating : PASS
4817 22:58:02.165670 RX DQ/DQS(RDDQC) : PASS
4818 22:58:02.165756 TX DQ/DQS : PASS
4819 22:58:02.168901 RX DATLAT : PASS
4820 22:58:02.172331 RX DQ/DQS(Engine): PASS
4821 22:58:02.172444 TX OE : NO K
4822 22:58:02.175518 All Pass.
4823 22:58:02.175605
4824 22:58:02.175671 CH 1, Rank 1
4825 22:58:02.179065 SW Impedance : PASS
4826 22:58:02.179152 DUTY Scan : NO K
4827 22:58:02.182438 ZQ Calibration : PASS
4828 22:58:02.185557 Jitter Meter : NO K
4829 22:58:02.185653 CBT Training : PASS
4830 22:58:02.188997 Write leveling : PASS
4831 22:58:02.192371 RX DQS gating : PASS
4832 22:58:02.192461 RX DQ/DQS(RDDQC) : PASS
4833 22:58:02.195593 TX DQ/DQS : PASS
4834 22:58:02.199390 RX DATLAT : PASS
4835 22:58:02.199481 RX DQ/DQS(Engine): PASS
4836 22:58:02.202371 TX OE : NO K
4837 22:58:02.202460 All Pass.
4838 22:58:02.202528
4839 22:58:02.205713 DramC Write-DBI off
4840 22:58:02.209197 PER_BANK_REFRESH: Hybrid Mode
4841 22:58:02.209288 TX_TRACKING: ON
4842 22:58:02.219089 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4843 22:58:02.222604 [FAST_K] Save calibration result to emmc
4844 22:58:02.226057 dramc_set_vcore_voltage set vcore to 662500
4845 22:58:02.226154 Read voltage for 933, 3
4846 22:58:02.229200 Vio18 = 0
4847 22:58:02.229288 Vcore = 662500
4848 22:58:02.229354 Vdram = 0
4849 22:58:02.232189 Vddq = 0
4850 22:58:02.232300 Vmddr = 0
4851 22:58:02.235826 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4852 22:58:02.242285 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4853 22:58:02.245844 MEM_TYPE=3, freq_sel=17
4854 22:58:02.249142 sv_algorithm_assistance_LP4_1600
4855 22:58:02.252420 ============ PULL DRAM RESETB DOWN ============
4856 22:58:02.255828 ========== PULL DRAM RESETB DOWN end =========
4857 22:58:02.262479 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4858 22:58:02.265845 ===================================
4859 22:58:02.265947 LPDDR4 DRAM CONFIGURATION
4860 22:58:02.269226 ===================================
4861 22:58:02.272584 EX_ROW_EN[0] = 0x0
4862 22:58:02.272703 EX_ROW_EN[1] = 0x0
4863 22:58:02.275987 LP4Y_EN = 0x0
4864 22:58:02.276076 WORK_FSP = 0x0
4865 22:58:02.279120 WL = 0x3
4866 22:58:02.279206 RL = 0x3
4867 22:58:02.282457 BL = 0x2
4868 22:58:02.285934 RPST = 0x0
4869 22:58:02.286020 RD_PRE = 0x0
4870 22:58:02.289205 WR_PRE = 0x1
4871 22:58:02.289292 WR_PST = 0x0
4872 22:58:02.292591 DBI_WR = 0x0
4873 22:58:02.292676 DBI_RD = 0x0
4874 22:58:02.295732 OTF = 0x1
4875 22:58:02.298896 ===================================
4876 22:58:02.302265 ===================================
4877 22:58:02.302360 ANA top config
4878 22:58:02.305740 ===================================
4879 22:58:02.309122 DLL_ASYNC_EN = 0
4880 22:58:02.312746 ALL_SLAVE_EN = 1
4881 22:58:02.312833 NEW_RANK_MODE = 1
4882 22:58:02.315778 DLL_IDLE_MODE = 1
4883 22:58:02.319022 LP45_APHY_COMB_EN = 1
4884 22:58:02.322316 TX_ODT_DIS = 1
4885 22:58:02.322403 NEW_8X_MODE = 1
4886 22:58:02.325967 ===================================
4887 22:58:02.328949 ===================================
4888 22:58:02.332195 data_rate = 1866
4889 22:58:02.335500 CKR = 1
4890 22:58:02.338823 DQ_P2S_RATIO = 8
4891 22:58:02.342160 ===================================
4892 22:58:02.345503 CA_P2S_RATIO = 8
4893 22:58:02.349174 DQ_CA_OPEN = 0
4894 22:58:02.349268 DQ_SEMI_OPEN = 0
4895 22:58:02.352267 CA_SEMI_OPEN = 0
4896 22:58:02.355546 CA_FULL_RATE = 0
4897 22:58:02.358980 DQ_CKDIV4_EN = 1
4898 22:58:02.362586 CA_CKDIV4_EN = 1
4899 22:58:02.365753 CA_PREDIV_EN = 0
4900 22:58:02.365842 PH8_DLY = 0
4901 22:58:02.368616 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4902 22:58:02.371972 DQ_AAMCK_DIV = 4
4903 22:58:02.375201 CA_AAMCK_DIV = 4
4904 22:58:02.378803 CA_ADMCK_DIV = 4
4905 22:58:02.382161 DQ_TRACK_CA_EN = 0
4906 22:58:02.385326 CA_PICK = 933
4907 22:58:02.385419 CA_MCKIO = 933
4908 22:58:02.388859 MCKIO_SEMI = 0
4909 22:58:02.391773 PLL_FREQ = 3732
4910 22:58:02.395280 DQ_UI_PI_RATIO = 32
4911 22:58:02.398441 CA_UI_PI_RATIO = 0
4912 22:58:02.402037 ===================================
4913 22:58:02.405086 ===================================
4914 22:58:02.408603 memory_type:LPDDR4
4915 22:58:02.408695 GP_NUM : 10
4916 22:58:02.411767 SRAM_EN : 1
4917 22:58:02.411869 MD32_EN : 0
4918 22:58:02.415241 ===================================
4919 22:58:02.418428 [ANA_INIT] >>>>>>>>>>>>>>
4920 22:58:02.421911 <<<<<< [CONFIGURE PHASE]: ANA_TX
4921 22:58:02.425370 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4922 22:58:02.428955 ===================================
4923 22:58:02.432096 data_rate = 1866,PCW = 0X8f00
4924 22:58:02.435372 ===================================
4925 22:58:02.438980 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4926 22:58:02.441858 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4927 22:58:02.448366 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4928 22:58:02.451910 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4929 22:58:02.458501 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4930 22:58:02.461442 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4931 22:58:02.461537 [ANA_INIT] flow start
4932 22:58:02.464955 [ANA_INIT] PLL >>>>>>>>
4933 22:58:02.468451 [ANA_INIT] PLL <<<<<<<<
4934 22:58:02.468543 [ANA_INIT] MIDPI >>>>>>>>
4935 22:58:02.471716 [ANA_INIT] MIDPI <<<<<<<<
4936 22:58:02.474869 [ANA_INIT] DLL >>>>>>>>
4937 22:58:02.474958 [ANA_INIT] flow end
4938 22:58:02.478360 ============ LP4 DIFF to SE enter ============
4939 22:58:02.484810 ============ LP4 DIFF to SE exit ============
4940 22:58:02.484921 [ANA_INIT] <<<<<<<<<<<<<
4941 22:58:02.488147 [Flow] Enable top DCM control >>>>>
4942 22:58:02.491804 [Flow] Enable top DCM control <<<<<
4943 22:58:02.494911 Enable DLL master slave shuffle
4944 22:58:02.501732 ==============================================================
4945 22:58:02.501846 Gating Mode config
4946 22:58:02.508465 ==============================================================
4947 22:58:02.511471 Config description:
4948 22:58:02.521827 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4949 22:58:02.528325 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4950 22:58:02.531503 SELPH_MODE 0: By rank 1: By Phase
4951 22:58:02.538527 ==============================================================
4952 22:58:02.541491 GAT_TRACK_EN = 1
4953 22:58:02.541622 RX_GATING_MODE = 2
4954 22:58:02.545492 RX_GATING_TRACK_MODE = 2
4955 22:58:02.548908 SELPH_MODE = 1
4956 22:58:02.551868 PICG_EARLY_EN = 1
4957 22:58:02.554967 VALID_LAT_VALUE = 1
4958 22:58:02.561509 ==============================================================
4959 22:58:02.565359 Enter into Gating configuration >>>>
4960 22:58:02.568276 Exit from Gating configuration <<<<
4961 22:58:02.571383 Enter into DVFS_PRE_config >>>>>
4962 22:58:02.581473 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4963 22:58:02.584871 Exit from DVFS_PRE_config <<<<<
4964 22:58:02.588246 Enter into PICG configuration >>>>
4965 22:58:02.591733 Exit from PICG configuration <<<<
4966 22:58:02.594778 [RX_INPUT] configuration >>>>>
4967 22:58:02.598319 [RX_INPUT] configuration <<<<<
4968 22:58:02.601611 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4969 22:58:02.608147 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4970 22:58:02.614996 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4971 22:58:02.621335 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4972 22:58:02.624541 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4973 22:58:02.631047 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4974 22:58:02.634519 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4975 22:58:02.640687 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4976 22:58:02.644337 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4977 22:58:02.647196 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4978 22:58:02.651115 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4979 22:58:02.657403 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4980 22:58:02.660725 ===================================
4981 22:58:02.663906 LPDDR4 DRAM CONFIGURATION
4982 22:58:02.667251 ===================================
4983 22:58:02.667349 EX_ROW_EN[0] = 0x0
4984 22:58:02.670920 EX_ROW_EN[1] = 0x0
4985 22:58:02.671009 LP4Y_EN = 0x0
4986 22:58:02.674055 WORK_FSP = 0x0
4987 22:58:02.674145 WL = 0x3
4988 22:58:02.677408 RL = 0x3
4989 22:58:02.677495 BL = 0x2
4990 22:58:02.680587 RPST = 0x0
4991 22:58:02.680675 RD_PRE = 0x0
4992 22:58:02.684207 WR_PRE = 0x1
4993 22:58:02.684300 WR_PST = 0x0
4994 22:58:02.687537 DBI_WR = 0x0
4995 22:58:02.687632 DBI_RD = 0x0
4996 22:58:02.690403 OTF = 0x1
4997 22:58:02.694247 ===================================
4998 22:58:02.697243 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4999 22:58:02.700487 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5000 22:58:02.707304 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5001 22:58:02.710363 ===================================
5002 22:58:02.710476 LPDDR4 DRAM CONFIGURATION
5003 22:58:02.714171 ===================================
5004 22:58:02.717486 EX_ROW_EN[0] = 0x10
5005 22:58:02.720611 EX_ROW_EN[1] = 0x0
5006 22:58:02.720714 LP4Y_EN = 0x0
5007 22:58:02.724198 WORK_FSP = 0x0
5008 22:58:02.724290 WL = 0x3
5009 22:58:02.727048 RL = 0x3
5010 22:58:02.727141 BL = 0x2
5011 22:58:02.730470 RPST = 0x0
5012 22:58:02.730562 RD_PRE = 0x0
5013 22:58:02.733750 WR_PRE = 0x1
5014 22:58:02.733845 WR_PST = 0x0
5015 22:58:02.736902 DBI_WR = 0x0
5016 22:58:02.737004 DBI_RD = 0x0
5017 22:58:02.740429 OTF = 0x1
5018 22:58:02.743897 ===================================
5019 22:58:02.750460 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5020 22:58:02.753397 nWR fixed to 30
5021 22:58:02.757069 [ModeRegInit_LP4] CH0 RK0
5022 22:58:02.757177 [ModeRegInit_LP4] CH0 RK1
5023 22:58:02.760256 [ModeRegInit_LP4] CH1 RK0
5024 22:58:02.763524 [ModeRegInit_LP4] CH1 RK1
5025 22:58:02.763623 match AC timing 9
5026 22:58:02.769844 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5027 22:58:02.773335 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5028 22:58:02.776749 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5029 22:58:02.784032 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5030 22:58:02.786519 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5031 22:58:02.786614 ==
5032 22:58:02.789880 Dram Type= 6, Freq= 0, CH_0, rank 0
5033 22:58:02.793138 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5034 22:58:02.793227 ==
5035 22:58:02.800023 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5036 22:58:02.806158 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5037 22:58:02.809719 [CA 0] Center 37 (6~68) winsize 63
5038 22:58:02.813027 [CA 1] Center 37 (7~68) winsize 62
5039 22:58:02.816336 [CA 2] Center 34 (4~65) winsize 62
5040 22:58:02.819576 [CA 3] Center 34 (3~65) winsize 63
5041 22:58:02.823482 [CA 4] Center 33 (3~64) winsize 62
5042 22:58:02.826331 [CA 5] Center 32 (2~62) winsize 61
5043 22:58:02.826427
5044 22:58:02.829451 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5045 22:58:02.829570
5046 22:58:02.832840 [CATrainingPosCal] consider 1 rank data
5047 22:58:02.836383 u2DelayCellTimex100 = 270/100 ps
5048 22:58:02.839794 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5049 22:58:02.842964 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5050 22:58:02.846620 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5051 22:58:02.849615 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5052 22:58:02.853184 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5053 22:58:02.856711 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5054 22:58:02.859453
5055 22:58:02.862761 CA PerBit enable=1, Macro0, CA PI delay=32
5056 22:58:02.862856
5057 22:58:02.866255 [CBTSetCACLKResult] CA Dly = 32
5058 22:58:02.866343 CS Dly: 5 (0~36)
5059 22:58:02.866410 ==
5060 22:58:02.869603 Dram Type= 6, Freq= 0, CH_0, rank 1
5061 22:58:02.872904 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5062 22:58:02.872991 ==
5063 22:58:02.879542 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5064 22:58:02.886181 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5065 22:58:02.889305 [CA 0] Center 37 (6~68) winsize 63
5066 22:58:02.893049 [CA 1] Center 37 (6~68) winsize 63
5067 22:58:02.896799 [CA 2] Center 34 (4~65) winsize 62
5068 22:58:02.899776 [CA 3] Center 34 (3~65) winsize 63
5069 22:58:02.902936 [CA 4] Center 32 (2~63) winsize 62
5070 22:58:02.906299 [CA 5] Center 32 (2~62) winsize 61
5071 22:58:02.906396
5072 22:58:02.909251 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5073 22:58:02.909345
5074 22:58:02.912460 [CATrainingPosCal] consider 2 rank data
5075 22:58:02.915902 u2DelayCellTimex100 = 270/100 ps
5076 22:58:02.919369 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5077 22:58:02.922687 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5078 22:58:02.926234 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5079 22:58:02.929453 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5080 22:58:02.936251 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5081 22:58:02.939287 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5082 22:58:02.939393
5083 22:58:02.942357 CA PerBit enable=1, Macro0, CA PI delay=32
5084 22:58:02.942447
5085 22:58:02.945915 [CBTSetCACLKResult] CA Dly = 32
5086 22:58:02.946013 CS Dly: 5 (0~37)
5087 22:58:02.946080
5088 22:58:02.949449 ----->DramcWriteLeveling(PI) begin...
5089 22:58:02.949544 ==
5090 22:58:02.952267 Dram Type= 6, Freq= 0, CH_0, rank 0
5091 22:58:02.959183 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5092 22:58:02.959301 ==
5093 22:58:02.962623 Write leveling (Byte 0): 33 => 33
5094 22:58:02.962715 Write leveling (Byte 1): 30 => 30
5095 22:58:02.965847 DramcWriteLeveling(PI) end<-----
5096 22:58:02.965940
5097 22:58:02.969199 ==
5098 22:58:02.969312 Dram Type= 6, Freq= 0, CH_0, rank 0
5099 22:58:02.975789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5100 22:58:02.975896 ==
5101 22:58:02.979185 [Gating] SW mode calibration
5102 22:58:02.985534 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5103 22:58:02.989048 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5104 22:58:02.995767 0 14 0 | B1->B0 | 2929 3434 | 0 1 | (0 0) (1 1)
5105 22:58:02.999113 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5106 22:58:03.002202 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5107 22:58:03.008881 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5108 22:58:03.012304 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5109 22:58:03.015467 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5110 22:58:03.021898 0 14 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
5111 22:58:03.025294 0 14 28 | B1->B0 | 3131 2323 | 0 0 | (0 1) (0 0)
5112 22:58:03.028605 0 15 0 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
5113 22:58:03.035288 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5114 22:58:03.038553 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5115 22:58:03.042181 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5116 22:58:03.049031 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5117 22:58:03.052088 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5118 22:58:03.055306 0 15 24 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
5119 22:58:03.061950 0 15 28 | B1->B0 | 2525 3939 | 0 0 | (0 0) (0 0)
5120 22:58:03.065207 1 0 0 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
5121 22:58:03.068510 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5122 22:58:03.075080 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5123 22:58:03.078762 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5124 22:58:03.081803 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5125 22:58:03.088304 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5126 22:58:03.091798 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5127 22:58:03.094784 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5128 22:58:03.098560 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5129 22:58:03.104776 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5130 22:58:03.108211 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5131 22:58:03.111497 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5132 22:58:03.118106 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5133 22:58:03.121432 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5134 22:58:03.124837 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5135 22:58:03.131310 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5136 22:58:03.134811 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5137 22:58:03.138202 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5138 22:58:03.144618 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5139 22:58:03.148285 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5140 22:58:03.151385 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5141 22:58:03.158254 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5142 22:58:03.161071 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5143 22:58:03.164502 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5144 22:58:03.171483 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5145 22:58:03.171575 Total UI for P1: 0, mck2ui 16
5146 22:58:03.177964 best dqsien dly found for B0: ( 1, 2, 26)
5147 22:58:03.181233 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5148 22:58:03.184546 Total UI for P1: 0, mck2ui 16
5149 22:58:03.188032 best dqsien dly found for B1: ( 1, 3, 0)
5150 22:58:03.191382 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5151 22:58:03.194573 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5152 22:58:03.194661
5153 22:58:03.197991 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5154 22:58:03.201288 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5155 22:58:03.204238 [Gating] SW calibration Done
5156 22:58:03.204324 ==
5157 22:58:03.207443 Dram Type= 6, Freq= 0, CH_0, rank 0
5158 22:58:03.210867 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5159 22:58:03.210956 ==
5160 22:58:03.214329 RX Vref Scan: 0
5161 22:58:03.214413
5162 22:58:03.217820 RX Vref 0 -> 0, step: 1
5163 22:58:03.217904
5164 22:58:03.217971 RX Delay -80 -> 252, step: 8
5165 22:58:03.224361 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5166 22:58:03.227704 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5167 22:58:03.230996 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5168 22:58:03.234870 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5169 22:58:03.238087 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5170 22:58:03.241468 iDelay=208, Bit 5, Center 91 (0 ~ 183) 184
5171 22:58:03.248325 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5172 22:58:03.251732 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5173 22:58:03.254841 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5174 22:58:03.258199 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5175 22:58:03.261307 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5176 22:58:03.264489 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5177 22:58:03.271378 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5178 22:58:03.274557 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5179 22:58:03.277917 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5180 22:58:03.281288 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5181 22:58:03.281375 ==
5182 22:58:03.284522 Dram Type= 6, Freq= 0, CH_0, rank 0
5183 22:58:03.287928 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5184 22:58:03.291721 ==
5185 22:58:03.291804 DQS Delay:
5186 22:58:03.291870 DQS0 = 0, DQS1 = 0
5187 22:58:03.294454 DQM Delay:
5188 22:58:03.294535 DQM0 = 104, DQM1 = 95
5189 22:58:03.298111 DQ Delay:
5190 22:58:03.301741 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5191 22:58:03.304312 DQ4 =107, DQ5 =91, DQ6 =115, DQ7 =115
5192 22:58:03.307615 DQ8 =87, DQ9 =87, DQ10 =95, DQ11 =91
5193 22:58:03.311016 DQ12 =99, DQ13 =103, DQ14 =103, DQ15 =99
5194 22:58:03.311103
5195 22:58:03.311168
5196 22:58:03.311228 ==
5197 22:58:03.314769 Dram Type= 6, Freq= 0, CH_0, rank 0
5198 22:58:03.317896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5199 22:58:03.317980 ==
5200 22:58:03.318046
5201 22:58:03.318106
5202 22:58:03.321406 TX Vref Scan disable
5203 22:58:03.321487 == TX Byte 0 ==
5204 22:58:03.327830 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5205 22:58:03.331236 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5206 22:58:03.331321 == TX Byte 1 ==
5207 22:58:03.338071 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5208 22:58:03.341056 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5209 22:58:03.341144 ==
5210 22:58:03.344864 Dram Type= 6, Freq= 0, CH_0, rank 0
5211 22:58:03.347747 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5212 22:58:03.347831 ==
5213 22:58:03.351173
5214 22:58:03.351266
5215 22:58:03.351348 TX Vref Scan disable
5216 22:58:03.354469 == TX Byte 0 ==
5217 22:58:03.357533 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5218 22:58:03.364257 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5219 22:58:03.364356 == TX Byte 1 ==
5220 22:58:03.367687 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5221 22:58:03.374063 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5222 22:58:03.374154
5223 22:58:03.374248 [DATLAT]
5224 22:58:03.374328 Freq=933, CH0 RK0
5225 22:58:03.374407
5226 22:58:03.377819 DATLAT Default: 0xd
5227 22:58:03.377898 0, 0xFFFF, sum = 0
5228 22:58:03.380894 1, 0xFFFF, sum = 0
5229 22:58:03.381012 2, 0xFFFF, sum = 0
5230 22:58:03.384396 3, 0xFFFF, sum = 0
5231 22:58:03.384476 4, 0xFFFF, sum = 0
5232 22:58:03.387578 5, 0xFFFF, sum = 0
5233 22:58:03.390879 6, 0xFFFF, sum = 0
5234 22:58:03.390965 7, 0xFFFF, sum = 0
5235 22:58:03.394330 8, 0xFFFF, sum = 0
5236 22:58:03.394412 9, 0xFFFF, sum = 0
5237 22:58:03.397884 10, 0x0, sum = 1
5238 22:58:03.397969 11, 0x0, sum = 2
5239 22:58:03.398054 12, 0x0, sum = 3
5240 22:58:03.401437 13, 0x0, sum = 4
5241 22:58:03.401541 best_step = 11
5242 22:58:03.401666
5243 22:58:03.401745 ==
5244 22:58:03.404409 Dram Type= 6, Freq= 0, CH_0, rank 0
5245 22:58:03.411036 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5246 22:58:03.411132 ==
5247 22:58:03.411223 RX Vref Scan: 1
5248 22:58:03.411303
5249 22:58:03.414479 RX Vref 0 -> 0, step: 1
5250 22:58:03.414560
5251 22:58:03.417518 RX Delay -45 -> 252, step: 4
5252 22:58:03.417650
5253 22:58:03.420916 Set Vref, RX VrefLevel [Byte0]: 55
5254 22:58:03.424279 [Byte1]: 50
5255 22:58:03.424359
5256 22:58:03.427503 Final RX Vref Byte 0 = 55 to rank0
5257 22:58:03.431180 Final RX Vref Byte 1 = 50 to rank0
5258 22:58:03.434294 Final RX Vref Byte 0 = 55 to rank1
5259 22:58:03.437483 Final RX Vref Byte 1 = 50 to rank1==
5260 22:58:03.440471 Dram Type= 6, Freq= 0, CH_0, rank 0
5261 22:58:03.444289 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5262 22:58:03.444382 ==
5263 22:58:03.447726 DQS Delay:
5264 22:58:03.447806 DQS0 = 0, DQS1 = 0
5265 22:58:03.450828 DQM Delay:
5266 22:58:03.450905 DQM0 = 104, DQM1 = 96
5267 22:58:03.450990 DQ Delay:
5268 22:58:03.457229 DQ0 =104, DQ1 =106, DQ2 =102, DQ3 =102
5269 22:58:03.460658 DQ4 =106, DQ5 =96, DQ6 =110, DQ7 =110
5270 22:58:03.464168 DQ8 =86, DQ9 =88, DQ10 =96, DQ11 =92
5271 22:58:03.467932 DQ12 =100, DQ13 =100, DQ14 =102, DQ15 =104
5272 22:58:03.468018
5273 22:58:03.468101
5274 22:58:03.473974 [DQSOSCAuto] RK0, (LSB)MR18= 0x3028, (MSB)MR19= 0x505, tDQSOscB0 = 409 ps tDQSOscB1 = 406 ps
5275 22:58:03.477289 CH0 RK0: MR19=505, MR18=3028
5276 22:58:03.483866 CH0_RK0: MR19=0x505, MR18=0x3028, DQSOSC=406, MR23=63, INC=65, DEC=43
5277 22:58:03.483968
5278 22:58:03.486970 ----->DramcWriteLeveling(PI) begin...
5279 22:58:03.487077 ==
5280 22:58:03.490765 Dram Type= 6, Freq= 0, CH_0, rank 1
5281 22:58:03.493860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5282 22:58:03.493946 ==
5283 22:58:03.497470 Write leveling (Byte 0): 33 => 33
5284 22:58:03.500527 Write leveling (Byte 1): 30 => 30
5285 22:58:03.503552 DramcWriteLeveling(PI) end<-----
5286 22:58:03.503638
5287 22:58:03.503739 ==
5288 22:58:03.507111 Dram Type= 6, Freq= 0, CH_0, rank 1
5289 22:58:03.510227 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5290 22:58:03.513493 ==
5291 22:58:03.513648 [Gating] SW mode calibration
5292 22:58:03.520205 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5293 22:58:03.526869 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5294 22:58:03.530217 0 14 0 | B1->B0 | 3232 3232 | 1 0 | (1 1) (0 0)
5295 22:58:03.536990 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5296 22:58:03.540435 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5297 22:58:03.543562 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5298 22:58:03.550136 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5299 22:58:03.553438 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5300 22:58:03.557261 0 14 24 | B1->B0 | 3333 3333 | 0 0 | (0 0) (0 0)
5301 22:58:03.563314 0 14 28 | B1->B0 | 2b2b 2a2a | 0 0 | (0 0) (1 0)
5302 22:58:03.566733 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
5303 22:58:03.570119 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5304 22:58:03.577034 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5305 22:58:03.580214 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5306 22:58:03.583492 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5307 22:58:03.589830 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5308 22:58:03.593235 0 15 24 | B1->B0 | 2525 2424 | 0 0 | (0 0) (0 0)
5309 22:58:03.596589 0 15 28 | B1->B0 | 3a3a 3736 | 0 1 | (0 0) (1 1)
5310 22:58:03.603336 1 0 0 | B1->B0 | 4545 4342 | 0 1 | (0 0) (0 0)
5311 22:58:03.606525 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5312 22:58:03.609865 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5313 22:58:03.616396 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5314 22:58:03.620106 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5315 22:58:03.623101 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5316 22:58:03.629941 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5317 22:58:03.633570 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5318 22:58:03.636314 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5319 22:58:03.639823 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5320 22:58:03.646868 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5321 22:58:03.649762 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5322 22:58:03.652860 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5323 22:58:03.659809 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5324 22:58:03.663322 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5325 22:58:03.666190 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5326 22:58:03.673187 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5327 22:58:03.676432 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5328 22:58:03.679331 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5329 22:58:03.686073 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5330 22:58:03.689208 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5331 22:58:03.692637 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5332 22:58:03.699305 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5333 22:58:03.702289 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5334 22:58:03.705613 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5335 22:58:03.708958 Total UI for P1: 0, mck2ui 16
5336 22:58:03.712358 best dqsien dly found for B0: ( 1, 2, 28)
5337 22:58:03.715856 Total UI for P1: 0, mck2ui 16
5338 22:58:03.719141 best dqsien dly found for B1: ( 1, 2, 30)
5339 22:58:03.722093 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5340 22:58:03.725393 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5341 22:58:03.725474
5342 22:58:03.732415 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5343 22:58:03.735672 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5344 22:58:03.738654 [Gating] SW calibration Done
5345 22:58:03.738748 ==
5346 22:58:03.742327 Dram Type= 6, Freq= 0, CH_0, rank 1
5347 22:58:03.745354 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5348 22:58:03.745465 ==
5349 22:58:03.745567 RX Vref Scan: 0
5350 22:58:03.745802
5351 22:58:03.749005 RX Vref 0 -> 0, step: 1
5352 22:58:03.749083
5353 22:58:03.752046 RX Delay -80 -> 252, step: 8
5354 22:58:03.755400 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5355 22:58:03.758776 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5356 22:58:03.765181 iDelay=208, Bit 2, Center 103 (8 ~ 199) 192
5357 22:58:03.768743 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5358 22:58:03.772315 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5359 22:58:03.775572 iDelay=208, Bit 5, Center 99 (8 ~ 191) 184
5360 22:58:03.778990 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5361 22:58:03.782232 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5362 22:58:03.788595 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5363 22:58:03.792032 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5364 22:58:03.795238 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5365 22:58:03.798643 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5366 22:58:03.801991 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5367 22:58:03.805536 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5368 22:58:03.812018 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5369 22:58:03.815260 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5370 22:58:03.815344 ==
5371 22:58:03.818694 Dram Type= 6, Freq= 0, CH_0, rank 1
5372 22:58:03.821785 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5373 22:58:03.821866 ==
5374 22:58:03.821948 DQS Delay:
5375 22:58:03.825312 DQS0 = 0, DQS1 = 0
5376 22:58:03.825388 DQM Delay:
5377 22:58:03.828396 DQM0 = 104, DQM1 = 93
5378 22:58:03.828477 DQ Delay:
5379 22:58:03.831925 DQ0 =103, DQ1 =107, DQ2 =103, DQ3 =99
5380 22:58:03.835518 DQ4 =107, DQ5 =99, DQ6 =107, DQ7 =111
5381 22:58:03.838793 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =87
5382 22:58:03.841910 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =99
5383 22:58:03.842030
5384 22:58:03.842096
5385 22:58:03.842157 ==
5386 22:58:03.845429 Dram Type= 6, Freq= 0, CH_0, rank 1
5387 22:58:03.851726 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5388 22:58:03.851814 ==
5389 22:58:03.851881
5390 22:58:03.851943
5391 22:58:03.852001 TX Vref Scan disable
5392 22:58:03.855528 == TX Byte 0 ==
5393 22:58:03.859684 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5394 22:58:03.861955 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5395 22:58:03.865879 == TX Byte 1 ==
5396 22:58:03.868717 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5397 22:58:03.872226 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5398 22:58:03.875643 ==
5399 22:58:03.878725 Dram Type= 6, Freq= 0, CH_0, rank 1
5400 22:58:03.882093 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5401 22:58:03.882180 ==
5402 22:58:03.882245
5403 22:58:03.882306
5404 22:58:03.885481 TX Vref Scan disable
5405 22:58:03.885596 == TX Byte 0 ==
5406 22:58:03.892174 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5407 22:58:03.895570 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5408 22:58:03.895668 == TX Byte 1 ==
5409 22:58:03.902321 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5410 22:58:03.905408 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5411 22:58:03.905489
5412 22:58:03.905613 [DATLAT]
5413 22:58:03.908699 Freq=933, CH0 RK1
5414 22:58:03.908776
5415 22:58:03.908860 DATLAT Default: 0xb
5416 22:58:03.911975 0, 0xFFFF, sum = 0
5417 22:58:03.912069 1, 0xFFFF, sum = 0
5418 22:58:03.915171 2, 0xFFFF, sum = 0
5419 22:58:03.915250 3, 0xFFFF, sum = 0
5420 22:58:03.918480 4, 0xFFFF, sum = 0
5421 22:58:03.918557 5, 0xFFFF, sum = 0
5422 22:58:03.921873 6, 0xFFFF, sum = 0
5423 22:58:03.925715 7, 0xFFFF, sum = 0
5424 22:58:03.925796 8, 0xFFFF, sum = 0
5425 22:58:03.928757 9, 0xFFFF, sum = 0
5426 22:58:03.928857 10, 0x0, sum = 1
5427 22:58:03.928941 11, 0x0, sum = 2
5428 22:58:03.931698 12, 0x0, sum = 3
5429 22:58:03.931778 13, 0x0, sum = 4
5430 22:58:03.935318 best_step = 11
5431 22:58:03.935443
5432 22:58:03.935560 ==
5433 22:58:03.938755 Dram Type= 6, Freq= 0, CH_0, rank 1
5434 22:58:03.941966 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5435 22:58:03.942087 ==
5436 22:58:03.945392 RX Vref Scan: 0
5437 22:58:03.945499
5438 22:58:03.945627 RX Vref 0 -> 0, step: 1
5439 22:58:03.948790
5440 22:58:03.948894 RX Delay -53 -> 252, step: 4
5441 22:58:03.955993 iDelay=199, Bit 0, Center 104 (15 ~ 194) 180
5442 22:58:03.959035 iDelay=199, Bit 1, Center 106 (23 ~ 190) 168
5443 22:58:03.962256 iDelay=199, Bit 2, Center 102 (15 ~ 190) 176
5444 22:58:03.965538 iDelay=199, Bit 3, Center 102 (15 ~ 190) 176
5445 22:58:03.969145 iDelay=199, Bit 4, Center 108 (23 ~ 194) 172
5446 22:58:03.976170 iDelay=199, Bit 5, Center 96 (7 ~ 186) 180
5447 22:58:03.979140 iDelay=199, Bit 6, Center 108 (23 ~ 194) 172
5448 22:58:03.982661 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5449 22:58:03.985511 iDelay=199, Bit 8, Center 86 (3 ~ 170) 168
5450 22:58:03.988956 iDelay=199, Bit 9, Center 82 (-1 ~ 166) 168
5451 22:58:03.995559 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5452 22:58:03.999277 iDelay=199, Bit 11, Center 88 (7 ~ 170) 164
5453 22:58:04.002461 iDelay=199, Bit 12, Center 100 (19 ~ 182) 164
5454 22:58:04.005730 iDelay=199, Bit 13, Center 100 (19 ~ 182) 164
5455 22:58:04.009067 iDelay=199, Bit 14, Center 102 (19 ~ 186) 168
5456 22:58:04.015387 iDelay=199, Bit 15, Center 102 (19 ~ 186) 168
5457 22:58:04.015483 ==
5458 22:58:04.018813 Dram Type= 6, Freq= 0, CH_0, rank 1
5459 22:58:04.022466 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5460 22:58:04.022554 ==
5461 22:58:04.022620 DQS Delay:
5462 22:58:04.025470 DQS0 = 0, DQS1 = 0
5463 22:58:04.025553 DQM Delay:
5464 22:58:04.028950 DQM0 = 104, DQM1 = 94
5465 22:58:04.029108 DQ Delay:
5466 22:58:04.032476 DQ0 =104, DQ1 =106, DQ2 =102, DQ3 =102
5467 22:58:04.035769 DQ4 =108, DQ5 =96, DQ6 =108, DQ7 =112
5468 22:58:04.038873 DQ8 =86, DQ9 =82, DQ10 =94, DQ11 =88
5469 22:58:04.042382 DQ12 =100, DQ13 =100, DQ14 =102, DQ15 =102
5470 22:58:04.042517
5471 22:58:04.042610
5472 22:58:04.052103 [DQSOSCAuto] RK1, (LSB)MR18= 0x2b04, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 408 ps
5473 22:58:04.052277 CH0 RK1: MR19=505, MR18=2B04
5474 22:58:04.058703 CH0_RK1: MR19=0x505, MR18=0x2B04, DQSOSC=408, MR23=63, INC=65, DEC=43
5475 22:58:04.062184 [RxdqsGatingPostProcess] freq 933
5476 22:58:04.068823 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5477 22:58:04.072066 best DQS0 dly(2T, 0.5T) = (0, 10)
5478 22:58:04.075241 best DQS1 dly(2T, 0.5T) = (0, 11)
5479 22:58:04.078387 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5480 22:58:04.081773 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5481 22:58:04.085135 best DQS0 dly(2T, 0.5T) = (0, 10)
5482 22:58:04.088784 best DQS1 dly(2T, 0.5T) = (0, 10)
5483 22:58:04.091979 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5484 22:58:04.095391 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5485 22:58:04.095499 Pre-setting of DQS Precalculation
5486 22:58:04.101695 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5487 22:58:04.101812 ==
5488 22:58:04.105048 Dram Type= 6, Freq= 0, CH_1, rank 0
5489 22:58:04.108402 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5490 22:58:04.108510 ==
5491 22:58:04.115611 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5492 22:58:04.122028 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5493 22:58:04.125247 [CA 0] Center 36 (6~67) winsize 62
5494 22:58:04.128249 [CA 1] Center 37 (6~68) winsize 63
5495 22:58:04.131510 [CA 2] Center 35 (5~65) winsize 61
5496 22:58:04.135202 [CA 3] Center 34 (4~65) winsize 62
5497 22:58:04.138329 [CA 4] Center 34 (4~65) winsize 62
5498 22:58:04.141967 [CA 5] Center 33 (3~64) winsize 62
5499 22:58:04.142082
5500 22:58:04.144955 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5501 22:58:04.145061
5502 22:58:04.148050 [CATrainingPosCal] consider 1 rank data
5503 22:58:04.151696 u2DelayCellTimex100 = 270/100 ps
5504 22:58:04.155109 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5505 22:58:04.158070 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5506 22:58:04.161676 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5507 22:58:04.165285 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5508 22:58:04.168170 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5509 22:58:04.171654 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5510 22:58:04.174609
5511 22:58:04.178023 CA PerBit enable=1, Macro0, CA PI delay=33
5512 22:58:04.178118
5513 22:58:04.181539 [CBTSetCACLKResult] CA Dly = 33
5514 22:58:04.181678 CS Dly: 6 (0~37)
5515 22:58:04.181745 ==
5516 22:58:04.184792 Dram Type= 6, Freq= 0, CH_1, rank 1
5517 22:58:04.188170 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5518 22:58:04.188243 ==
5519 22:58:04.194770 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5520 22:58:04.201413 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5521 22:58:04.204785 [CA 0] Center 36 (6~67) winsize 62
5522 22:58:04.208487 [CA 1] Center 37 (6~68) winsize 63
5523 22:58:04.211512 [CA 2] Center 35 (4~66) winsize 63
5524 22:58:04.214595 [CA 3] Center 34 (4~65) winsize 62
5525 22:58:04.218294 [CA 4] Center 34 (4~65) winsize 62
5526 22:58:04.221085 [CA 5] Center 34 (4~64) winsize 61
5527 22:58:04.221191
5528 22:58:04.225054 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5529 22:58:04.225153
5530 22:58:04.228245 [CATrainingPosCal] consider 2 rank data
5531 22:58:04.231038 u2DelayCellTimex100 = 270/100 ps
5532 22:58:04.234882 CA0 delay=36 (6~67),Diff = 2 PI (12 cell)
5533 22:58:04.238088 CA1 delay=37 (6~68),Diff = 3 PI (18 cell)
5534 22:58:04.241002 CA2 delay=35 (5~65),Diff = 1 PI (6 cell)
5535 22:58:04.244849 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5536 22:58:04.247757 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5537 22:58:04.254511 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5538 22:58:04.254601
5539 22:58:04.258116 CA PerBit enable=1, Macro0, CA PI delay=34
5540 22:58:04.258191
5541 22:58:04.261219 [CBTSetCACLKResult] CA Dly = 34
5542 22:58:04.261290 CS Dly: 7 (0~40)
5543 22:58:04.261351
5544 22:58:04.264345 ----->DramcWriteLeveling(PI) begin...
5545 22:58:04.264415 ==
5546 22:58:04.267788 Dram Type= 6, Freq= 0, CH_1, rank 0
5547 22:58:04.270933 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5548 22:58:04.274403 ==
5549 22:58:04.277784 Write leveling (Byte 0): 28 => 28
5550 22:58:04.277892 Write leveling (Byte 1): 29 => 29
5551 22:58:04.281164 DramcWriteLeveling(PI) end<-----
5552 22:58:04.281347
5553 22:58:04.281422 ==
5554 22:58:04.284318 Dram Type= 6, Freq= 0, CH_1, rank 0
5555 22:58:04.291170 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5556 22:58:04.291323 ==
5557 22:58:04.294695 [Gating] SW mode calibration
5558 22:58:04.301343 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5559 22:58:04.304749 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5560 22:58:04.311009 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5561 22:58:04.314360 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5562 22:58:04.318065 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5563 22:58:04.321431 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5564 22:58:04.327813 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5565 22:58:04.331220 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5566 22:58:04.334301 0 14 24 | B1->B0 | 3434 2b2b | 1 0 | (1 0) (0 0)
5567 22:58:04.340990 0 14 28 | B1->B0 | 2929 2323 | 0 0 | (1 1) (0 0)
5568 22:58:04.345125 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5569 22:58:04.347672 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5570 22:58:04.354578 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5571 22:58:04.357865 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5572 22:58:04.360682 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5573 22:58:04.367689 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5574 22:58:04.370928 0 15 24 | B1->B0 | 2424 3737 | 0 1 | (0 0) (0 0)
5575 22:58:04.374243 0 15 28 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
5576 22:58:04.380594 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5577 22:58:04.384226 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5578 22:58:04.387435 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5579 22:58:04.394102 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5580 22:58:04.397413 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5581 22:58:04.401090 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5582 22:58:04.407292 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5583 22:58:04.410819 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5584 22:58:04.413901 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5585 22:58:04.420395 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5586 22:58:04.423759 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5587 22:58:04.427519 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5588 22:58:04.433949 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5589 22:58:04.437336 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5590 22:58:04.440159 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5591 22:58:04.447023 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5592 22:58:04.450325 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5593 22:58:04.454089 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5594 22:58:04.460318 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5595 22:58:04.463972 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5596 22:58:04.467143 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5597 22:58:04.473801 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5598 22:58:04.477028 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5599 22:58:04.480438 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5600 22:58:04.483671 Total UI for P1: 0, mck2ui 16
5601 22:58:04.487196 best dqsien dly found for B0: ( 1, 2, 24)
5602 22:58:04.490616 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5603 22:58:04.493488 Total UI for P1: 0, mck2ui 16
5604 22:58:04.497094 best dqsien dly found for B1: ( 1, 2, 26)
5605 22:58:04.500306 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5606 22:58:04.507130 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5607 22:58:04.507219
5608 22:58:04.510192 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5609 22:58:04.513676 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5610 22:58:04.516626 [Gating] SW calibration Done
5611 22:58:04.516705 ==
5612 22:58:04.520498 Dram Type= 6, Freq= 0, CH_1, rank 0
5613 22:58:04.523179 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5614 22:58:04.523279 ==
5615 22:58:04.523373 RX Vref Scan: 0
5616 22:58:04.526744
5617 22:58:04.526844 RX Vref 0 -> 0, step: 1
5618 22:58:04.526933
5619 22:58:04.529831 RX Delay -80 -> 252, step: 8
5620 22:58:04.533177 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5621 22:58:04.536770 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5622 22:58:04.543306 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5623 22:58:04.546538 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5624 22:58:04.550030 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5625 22:58:04.553374 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5626 22:58:04.556656 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5627 22:58:04.559888 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5628 22:58:04.566730 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5629 22:58:04.569777 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5630 22:58:04.573607 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5631 22:58:04.576643 iDelay=208, Bit 11, Center 95 (8 ~ 183) 176
5632 22:58:04.579838 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5633 22:58:04.583308 iDelay=208, Bit 13, Center 107 (16 ~ 199) 184
5634 22:58:04.589842 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5635 22:58:04.593272 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5636 22:58:04.593374 ==
5637 22:58:04.596549 Dram Type= 6, Freq= 0, CH_1, rank 0
5638 22:58:04.600025 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5639 22:58:04.600109 ==
5640 22:58:04.603270 DQS Delay:
5641 22:58:04.603342 DQS0 = 0, DQS1 = 0
5642 22:58:04.603404 DQM Delay:
5643 22:58:04.606704 DQM0 = 102, DQM1 = 99
5644 22:58:04.606782 DQ Delay:
5645 22:58:04.609763 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
5646 22:58:04.613474 DQ4 =99, DQ5 =115, DQ6 =107, DQ7 =103
5647 22:58:04.616277 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =95
5648 22:58:04.619927 DQ12 =107, DQ13 =107, DQ14 =103, DQ15 =107
5649 22:58:04.620032
5650 22:58:04.623189
5651 22:58:04.623291 ==
5652 22:58:04.626864 Dram Type= 6, Freq= 0, CH_1, rank 0
5653 22:58:04.629604 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5654 22:58:04.629696 ==
5655 22:58:04.629761
5656 22:58:04.629820
5657 22:58:04.633226 TX Vref Scan disable
5658 22:58:04.633329 == TX Byte 0 ==
5659 22:58:04.639742 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5660 22:58:04.643334 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5661 22:58:04.643441 == TX Byte 1 ==
5662 22:58:04.649625 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5663 22:58:04.653119 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5664 22:58:04.653289 ==
5665 22:58:04.656485 Dram Type= 6, Freq= 0, CH_1, rank 0
5666 22:58:04.659907 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5667 22:58:04.660049 ==
5668 22:58:04.660157
5669 22:58:04.660263
5670 22:58:04.662911 TX Vref Scan disable
5671 22:58:04.666320 == TX Byte 0 ==
5672 22:58:04.669867 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5673 22:58:04.672693 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5674 22:58:04.676154 == TX Byte 1 ==
5675 22:58:04.679564 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5676 22:58:04.683216 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5677 22:58:04.683305
5678 22:58:04.686646 [DATLAT]
5679 22:58:04.686735 Freq=933, CH1 RK0
5680 22:58:04.686823
5681 22:58:04.690158 DATLAT Default: 0xd
5682 22:58:04.690244 0, 0xFFFF, sum = 0
5683 22:58:04.693059 1, 0xFFFF, sum = 0
5684 22:58:04.693148 2, 0xFFFF, sum = 0
5685 22:58:04.696472 3, 0xFFFF, sum = 0
5686 22:58:04.696597 4, 0xFFFF, sum = 0
5687 22:58:04.699833 5, 0xFFFF, sum = 0
5688 22:58:04.699949 6, 0xFFFF, sum = 0
5689 22:58:04.703285 7, 0xFFFF, sum = 0
5690 22:58:04.703374 8, 0xFFFF, sum = 0
5691 22:58:04.706009 9, 0xFFFF, sum = 0
5692 22:58:04.706098 10, 0x0, sum = 1
5693 22:58:04.709381 11, 0x0, sum = 2
5694 22:58:04.709469 12, 0x0, sum = 3
5695 22:58:04.712911 13, 0x0, sum = 4
5696 22:58:04.713004 best_step = 11
5697 22:58:04.713092
5698 22:58:04.713176 ==
5699 22:58:04.716225 Dram Type= 6, Freq= 0, CH_1, rank 0
5700 22:58:04.719420 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5701 22:58:04.722909 ==
5702 22:58:04.722998 RX Vref Scan: 1
5703 22:58:04.723085
5704 22:58:04.725948 RX Vref 0 -> 0, step: 1
5705 22:58:04.726034
5706 22:58:04.729189 RX Delay -45 -> 252, step: 4
5707 22:58:04.729275
5708 22:58:04.732726 Set Vref, RX VrefLevel [Byte0]: 55
5709 22:58:04.736211 [Byte1]: 48
5710 22:58:04.736323
5711 22:58:04.739138 Final RX Vref Byte 0 = 55 to rank0
5712 22:58:04.742715 Final RX Vref Byte 1 = 48 to rank0
5713 22:58:04.746089 Final RX Vref Byte 0 = 55 to rank1
5714 22:58:04.748958 Final RX Vref Byte 1 = 48 to rank1==
5715 22:58:04.752597 Dram Type= 6, Freq= 0, CH_1, rank 0
5716 22:58:04.755663 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5717 22:58:04.755751 ==
5718 22:58:04.759333 DQS Delay:
5719 22:58:04.759419 DQS0 = 0, DQS1 = 0
5720 22:58:04.759507 DQM Delay:
5721 22:58:04.762385 DQM0 = 103, DQM1 = 99
5722 22:58:04.762485 DQ Delay:
5723 22:58:04.766051 DQ0 =106, DQ1 =98, DQ2 =94, DQ3 =102
5724 22:58:04.769503 DQ4 =102, DQ5 =112, DQ6 =112, DQ7 =102
5725 22:58:04.772567 DQ8 =86, DQ9 =90, DQ10 =98, DQ11 =92
5726 22:58:04.775809 DQ12 =106, DQ13 =104, DQ14 =108, DQ15 =108
5727 22:58:04.775896
5728 22:58:04.779384
5729 22:58:04.785560 [DQSOSCAuto] RK0, (LSB)MR18= 0x1b32, (MSB)MR19= 0x505, tDQSOscB0 = 406 ps tDQSOscB1 = 413 ps
5730 22:58:04.789424 CH1 RK0: MR19=505, MR18=1B32
5731 22:58:04.795630 CH1_RK0: MR19=0x505, MR18=0x1B32, DQSOSC=406, MR23=63, INC=65, DEC=43
5732 22:58:04.795721
5733 22:58:04.799412 ----->DramcWriteLeveling(PI) begin...
5734 22:58:04.799498 ==
5735 22:58:04.802471 Dram Type= 6, Freq= 0, CH_1, rank 1
5736 22:58:04.806042 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5737 22:58:04.806127 ==
5738 22:58:04.808978 Write leveling (Byte 0): 25 => 25
5739 22:58:04.812057 Write leveling (Byte 1): 27 => 27
5740 22:58:04.815646 DramcWriteLeveling(PI) end<-----
5741 22:58:04.815732
5742 22:58:04.815799 ==
5743 22:58:04.818947 Dram Type= 6, Freq= 0, CH_1, rank 1
5744 22:58:04.822315 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5745 22:58:04.822399 ==
5746 22:58:04.825834 [Gating] SW mode calibration
5747 22:58:04.832312 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5748 22:58:04.838956 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5749 22:58:04.842147 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5750 22:58:04.845371 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5751 22:58:04.852435 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5752 22:58:04.855364 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5753 22:58:04.858727 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5754 22:58:04.865658 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5755 22:58:04.868995 0 14 24 | B1->B0 | 2c2c 3131 | 0 0 | (0 0) (0 0)
5756 22:58:04.872131 0 14 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5757 22:58:04.878787 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5758 22:58:04.882361 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5759 22:58:04.885292 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5760 22:58:04.892166 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5761 22:58:04.895579 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5762 22:58:04.899043 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5763 22:58:04.902265 0 15 24 | B1->B0 | 3838 2b2b | 0 0 | (0 0) (0 0)
5764 22:58:04.909313 0 15 28 | B1->B0 | 4646 4141 | 0 1 | (0 0) (0 0)
5765 22:58:04.912105 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5766 22:58:04.915362 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5767 22:58:04.922498 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5768 22:58:04.925871 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5769 22:58:04.928775 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5770 22:58:04.935787 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5771 22:58:04.939118 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5772 22:58:04.942057 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5773 22:58:04.948985 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5774 22:58:04.952203 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5775 22:58:04.955494 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5776 22:58:04.962402 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5777 22:58:04.965244 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5778 22:58:04.968905 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5779 22:58:04.975726 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5780 22:58:04.978859 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5781 22:58:04.981906 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5782 22:58:04.988512 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5783 22:58:04.991999 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5784 22:58:04.995735 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5785 22:58:05.001771 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5786 22:58:05.005101 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5787 22:58:05.008243 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5788 22:58:05.015072 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5789 22:58:05.018691 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5790 22:58:05.022089 Total UI for P1: 0, mck2ui 16
5791 22:58:05.025709 best dqsien dly found for B0: ( 1, 2, 26)
5792 22:58:05.028534 Total UI for P1: 0, mck2ui 16
5793 22:58:05.032029 best dqsien dly found for B1: ( 1, 2, 26)
5794 22:58:05.034925 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5795 22:58:05.038364 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5796 22:58:05.038454
5797 22:58:05.042076 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5798 22:58:05.044976 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5799 22:58:05.048362 [Gating] SW calibration Done
5800 22:58:05.048450 ==
5801 22:58:05.051893 Dram Type= 6, Freq= 0, CH_1, rank 1
5802 22:58:05.055253 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5803 22:58:05.055340 ==
5804 22:58:05.058509 RX Vref Scan: 0
5805 22:58:05.058603
5806 22:58:05.061753 RX Vref 0 -> 0, step: 1
5807 22:58:05.061917
5808 22:58:05.062024 RX Delay -80 -> 252, step: 8
5809 22:58:05.068174 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5810 22:58:05.071881 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5811 22:58:05.074853 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5812 22:58:05.078487 iDelay=208, Bit 3, Center 95 (8 ~ 183) 176
5813 22:58:05.081846 iDelay=208, Bit 4, Center 95 (8 ~ 183) 176
5814 22:58:05.084753 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5815 22:58:05.091445 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5816 22:58:05.094838 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5817 22:58:05.098223 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5818 22:58:05.101702 iDelay=208, Bit 9, Center 91 (0 ~ 183) 184
5819 22:58:05.105076 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5820 22:58:05.108516 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5821 22:58:05.114812 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5822 22:58:05.118107 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5823 22:58:05.121585 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5824 22:58:05.125114 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5825 22:58:05.125197 ==
5826 22:58:05.128536 Dram Type= 6, Freq= 0, CH_1, rank 1
5827 22:58:05.131453 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5828 22:58:05.134784 ==
5829 22:58:05.134893 DQS Delay:
5830 22:58:05.134997 DQS0 = 0, DQS1 = 0
5831 22:58:05.138342 DQM Delay:
5832 22:58:05.138444 DQM0 = 102, DQM1 = 98
5833 22:58:05.141637 DQ Delay:
5834 22:58:05.145034 DQ0 =107, DQ1 =99, DQ2 =91, DQ3 =95
5835 22:58:05.148664 DQ4 =95, DQ5 =115, DQ6 =115, DQ7 =99
5836 22:58:05.151570 DQ8 =87, DQ9 =91, DQ10 =99, DQ11 =91
5837 22:58:05.155016 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =107
5838 22:58:05.155100
5839 22:58:05.155165
5840 22:58:05.155226 ==
5841 22:58:05.158207 Dram Type= 6, Freq= 0, CH_1, rank 1
5842 22:58:05.161504 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5843 22:58:05.161638 ==
5844 22:58:05.161707
5845 22:58:05.161781
5846 22:58:05.165027 TX Vref Scan disable
5847 22:58:05.165099 == TX Byte 0 ==
5848 22:58:05.171827 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5849 22:58:05.174635 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5850 22:58:05.174740 == TX Byte 1 ==
5851 22:58:05.181484 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5852 22:58:05.184913 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5853 22:58:05.185013 ==
5854 22:58:05.188219 Dram Type= 6, Freq= 0, CH_1, rank 1
5855 22:58:05.191447 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5856 22:58:05.191532 ==
5857 22:58:05.195088
5858 22:58:05.195171
5859 22:58:05.195237 TX Vref Scan disable
5860 22:58:05.198343 == TX Byte 0 ==
5861 22:58:05.201286 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5862 22:58:05.204804 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5863 22:58:05.207935 == TX Byte 1 ==
5864 22:58:05.210971 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5865 22:58:05.217997 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5866 22:58:05.218088
5867 22:58:05.218154 [DATLAT]
5868 22:58:05.218216 Freq=933, CH1 RK1
5869 22:58:05.218277
5870 22:58:05.220920 DATLAT Default: 0xb
5871 22:58:05.221003 0, 0xFFFF, sum = 0
5872 22:58:05.224306 1, 0xFFFF, sum = 0
5873 22:58:05.224392 2, 0xFFFF, sum = 0
5874 22:58:05.227905 3, 0xFFFF, sum = 0
5875 22:58:05.231217 4, 0xFFFF, sum = 0
5876 22:58:05.231339 5, 0xFFFF, sum = 0
5877 22:58:05.234209 6, 0xFFFF, sum = 0
5878 22:58:05.234294 7, 0xFFFF, sum = 0
5879 22:58:05.237619 8, 0xFFFF, sum = 0
5880 22:58:05.237732 9, 0xFFFF, sum = 0
5881 22:58:05.240653 10, 0x0, sum = 1
5882 22:58:05.240738 11, 0x0, sum = 2
5883 22:58:05.244177 12, 0x0, sum = 3
5884 22:58:05.244262 13, 0x0, sum = 4
5885 22:58:05.244329 best_step = 11
5886 22:58:05.247636
5887 22:58:05.247718 ==
5888 22:58:05.250863 Dram Type= 6, Freq= 0, CH_1, rank 1
5889 22:58:05.254396 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5890 22:58:05.254481 ==
5891 22:58:05.254548 RX Vref Scan: 0
5892 22:58:05.254609
5893 22:58:05.257845 RX Vref 0 -> 0, step: 1
5894 22:58:05.257929
5895 22:58:05.260624 RX Delay -45 -> 252, step: 4
5896 22:58:05.267546 iDelay=203, Bit 0, Center 110 (27 ~ 194) 168
5897 22:58:05.271017 iDelay=203, Bit 1, Center 102 (19 ~ 186) 168
5898 22:58:05.274187 iDelay=203, Bit 2, Center 94 (11 ~ 178) 168
5899 22:58:05.277627 iDelay=203, Bit 3, Center 100 (19 ~ 182) 164
5900 22:58:05.281037 iDelay=203, Bit 4, Center 100 (19 ~ 182) 164
5901 22:58:05.283963 iDelay=203, Bit 5, Center 116 (31 ~ 202) 172
5902 22:58:05.290961 iDelay=203, Bit 6, Center 114 (31 ~ 198) 168
5903 22:58:05.294250 iDelay=203, Bit 7, Center 104 (19 ~ 190) 172
5904 22:58:05.297258 iDelay=203, Bit 8, Center 92 (11 ~ 174) 164
5905 22:58:05.300770 iDelay=203, Bit 9, Center 88 (3 ~ 174) 172
5906 22:58:05.304450 iDelay=203, Bit 10, Center 100 (15 ~ 186) 172
5907 22:58:05.310717 iDelay=203, Bit 11, Center 94 (11 ~ 178) 168
5908 22:58:05.314121 iDelay=203, Bit 12, Center 108 (19 ~ 198) 180
5909 22:58:05.317246 iDelay=203, Bit 13, Center 104 (19 ~ 190) 172
5910 22:58:05.321027 iDelay=203, Bit 14, Center 102 (19 ~ 186) 168
5911 22:58:05.324085 iDelay=203, Bit 15, Center 108 (23 ~ 194) 172
5912 22:58:05.324173 ==
5913 22:58:05.327411 Dram Type= 6, Freq= 0, CH_1, rank 1
5914 22:58:05.333939 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5915 22:58:05.334037 ==
5916 22:58:05.334107 DQS Delay:
5917 22:58:05.337453 DQS0 = 0, DQS1 = 0
5918 22:58:05.337552 DQM Delay:
5919 22:58:05.340793 DQM0 = 105, DQM1 = 99
5920 22:58:05.340879 DQ Delay:
5921 22:58:05.344296 DQ0 =110, DQ1 =102, DQ2 =94, DQ3 =100
5922 22:58:05.347207 DQ4 =100, DQ5 =116, DQ6 =114, DQ7 =104
5923 22:58:05.350752 DQ8 =92, DQ9 =88, DQ10 =100, DQ11 =94
5924 22:58:05.354179 DQ12 =108, DQ13 =104, DQ14 =102, DQ15 =108
5925 22:58:05.354268
5926 22:58:05.354385
5927 22:58:05.364237 [DQSOSCAuto] RK1, (LSB)MR18= 0x2d02, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 407 ps
5928 22:58:05.364340 CH1 RK1: MR19=505, MR18=2D02
5929 22:58:05.370546 CH1_RK1: MR19=0x505, MR18=0x2D02, DQSOSC=407, MR23=63, INC=65, DEC=43
5930 22:58:05.373937 [RxdqsGatingPostProcess] freq 933
5931 22:58:05.380494 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5932 22:58:05.383934 best DQS0 dly(2T, 0.5T) = (0, 10)
5933 22:58:05.387511 best DQS1 dly(2T, 0.5T) = (0, 10)
5934 22:58:05.390939 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5935 22:58:05.393723 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5936 22:58:05.393830 best DQS0 dly(2T, 0.5T) = (0, 10)
5937 22:58:05.397152 best DQS1 dly(2T, 0.5T) = (0, 10)
5938 22:58:05.400748 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5939 22:58:05.404014 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5940 22:58:05.407021 Pre-setting of DQS Precalculation
5941 22:58:05.413762 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5942 22:58:05.420543 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5943 22:58:05.426923 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5944 22:58:05.427060
5945 22:58:05.427172
5946 22:58:05.430559 [Calibration Summary] 1866 Mbps
5947 22:58:05.430683 CH 0, Rank 0
5948 22:58:05.433693 SW Impedance : PASS
5949 22:58:05.437228 DUTY Scan : NO K
5950 22:58:05.437373 ZQ Calibration : PASS
5951 22:58:05.440632 Jitter Meter : NO K
5952 22:58:05.443872 CBT Training : PASS
5953 22:58:05.443969 Write leveling : PASS
5954 22:58:05.446888 RX DQS gating : PASS
5955 22:58:05.450108 RX DQ/DQS(RDDQC) : PASS
5956 22:58:05.450200 TX DQ/DQS : PASS
5957 22:58:05.453702 RX DATLAT : PASS
5958 22:58:05.456688 RX DQ/DQS(Engine): PASS
5959 22:58:05.456771 TX OE : NO K
5960 22:58:05.456874 All Pass.
5961 22:58:05.460059
5962 22:58:05.460141 CH 0, Rank 1
5963 22:58:05.463596 SW Impedance : PASS
5964 22:58:05.463681 DUTY Scan : NO K
5965 22:58:05.467192 ZQ Calibration : PASS
5966 22:58:05.467282 Jitter Meter : NO K
5967 22:58:05.470591 CBT Training : PASS
5968 22:58:05.473878 Write leveling : PASS
5969 22:58:05.473960 RX DQS gating : PASS
5970 22:58:05.476924 RX DQ/DQS(RDDQC) : PASS
5971 22:58:05.480092 TX DQ/DQS : PASS
5972 22:58:05.480181 RX DATLAT : PASS
5973 22:58:05.483640 RX DQ/DQS(Engine): PASS
5974 22:58:05.487015 TX OE : NO K
5975 22:58:05.487099 All Pass.
5976 22:58:05.487165
5977 22:58:05.487265 CH 1, Rank 0
5978 22:58:05.490247 SW Impedance : PASS
5979 22:58:05.493530 DUTY Scan : NO K
5980 22:58:05.493672 ZQ Calibration : PASS
5981 22:58:05.496860 Jitter Meter : NO K
5982 22:58:05.500208 CBT Training : PASS
5983 22:58:05.500282 Write leveling : PASS
5984 22:58:05.503692 RX DQS gating : PASS
5985 22:58:05.506926 RX DQ/DQS(RDDQC) : PASS
5986 22:58:05.507042 TX DQ/DQS : PASS
5987 22:58:05.510320 RX DATLAT : PASS
5988 22:58:05.510422 RX DQ/DQS(Engine): PASS
5989 22:58:05.513733 TX OE : NO K
5990 22:58:05.513832 All Pass.
5991 22:58:05.513929
5992 22:58:05.517120 CH 1, Rank 1
5993 22:58:05.517217 SW Impedance : PASS
5994 22:58:05.520261 DUTY Scan : NO K
5995 22:58:05.523642 ZQ Calibration : PASS
5996 22:58:05.523724 Jitter Meter : NO K
5997 22:58:05.527103 CBT Training : PASS
5998 22:58:05.530404 Write leveling : PASS
5999 22:58:05.530508 RX DQS gating : PASS
6000 22:58:05.533346 RX DQ/DQS(RDDQC) : PASS
6001 22:58:05.536846 TX DQ/DQS : PASS
6002 22:58:05.536934 RX DATLAT : PASS
6003 22:58:05.540456 RX DQ/DQS(Engine): PASS
6004 22:58:05.543624 TX OE : NO K
6005 22:58:05.543708 All Pass.
6006 22:58:05.543772
6007 22:58:05.543833 DramC Write-DBI off
6008 22:58:05.546807 PER_BANK_REFRESH: Hybrid Mode
6009 22:58:05.550470 TX_TRACKING: ON
6010 22:58:05.556855 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6011 22:58:05.560028 [FAST_K] Save calibration result to emmc
6012 22:58:05.566867 dramc_set_vcore_voltage set vcore to 650000
6013 22:58:05.566964 Read voltage for 400, 6
6014 22:58:05.570291 Vio18 = 0
6015 22:58:05.570363 Vcore = 650000
6016 22:58:05.570425 Vdram = 0
6017 22:58:05.573159 Vddq = 0
6018 22:58:05.573255 Vmddr = 0
6019 22:58:05.576697 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6020 22:58:05.583501 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6021 22:58:05.586478 MEM_TYPE=3, freq_sel=20
6022 22:58:05.589791 sv_algorithm_assistance_LP4_800
6023 22:58:05.593297 ============ PULL DRAM RESETB DOWN ============
6024 22:58:05.596642 ========== PULL DRAM RESETB DOWN end =========
6025 22:58:05.599821 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6026 22:58:05.602847 ===================================
6027 22:58:05.606349 LPDDR4 DRAM CONFIGURATION
6028 22:58:05.609394 ===================================
6029 22:58:05.613129 EX_ROW_EN[0] = 0x0
6030 22:58:05.613234 EX_ROW_EN[1] = 0x0
6031 22:58:05.616030 LP4Y_EN = 0x0
6032 22:58:05.616104 WORK_FSP = 0x0
6033 22:58:05.619514 WL = 0x2
6034 22:58:05.619588 RL = 0x2
6035 22:58:05.623129 BL = 0x2
6036 22:58:05.623201 RPST = 0x0
6037 22:58:05.626387 RD_PRE = 0x0
6038 22:58:05.629508 WR_PRE = 0x1
6039 22:58:05.629646 WR_PST = 0x0
6040 22:58:05.632687 DBI_WR = 0x0
6041 22:58:05.632805 DBI_RD = 0x0
6042 22:58:05.635810 OTF = 0x1
6043 22:58:05.639515 ===================================
6044 22:58:05.642867 ===================================
6045 22:58:05.642950 ANA top config
6046 22:58:05.646165 ===================================
6047 22:58:05.649444 DLL_ASYNC_EN = 0
6048 22:58:05.652966 ALL_SLAVE_EN = 1
6049 22:58:05.653063 NEW_RANK_MODE = 1
6050 22:58:05.656374 DLL_IDLE_MODE = 1
6051 22:58:05.659222 LP45_APHY_COMB_EN = 1
6052 22:58:05.662644 TX_ODT_DIS = 1
6053 22:58:05.662738 NEW_8X_MODE = 1
6054 22:58:05.666092 ===================================
6055 22:58:05.669346 ===================================
6056 22:58:05.672687 data_rate = 800
6057 22:58:05.675851 CKR = 1
6058 22:58:05.679097 DQ_P2S_RATIO = 4
6059 22:58:05.682685 ===================================
6060 22:58:05.686145 CA_P2S_RATIO = 4
6061 22:58:05.689056 DQ_CA_OPEN = 0
6062 22:58:05.689168 DQ_SEMI_OPEN = 1
6063 22:58:05.692478 CA_SEMI_OPEN = 1
6064 22:58:05.696058 CA_FULL_RATE = 0
6065 22:58:05.699243 DQ_CKDIV4_EN = 0
6066 22:58:05.702311 CA_CKDIV4_EN = 1
6067 22:58:05.705690 CA_PREDIV_EN = 0
6068 22:58:05.705783 PH8_DLY = 0
6069 22:58:05.709042 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6070 22:58:05.712176 DQ_AAMCK_DIV = 0
6071 22:58:05.715714 CA_AAMCK_DIV = 0
6072 22:58:05.719357 CA_ADMCK_DIV = 4
6073 22:58:05.722372 DQ_TRACK_CA_EN = 0
6074 22:58:05.722449 CA_PICK = 800
6075 22:58:05.725375 CA_MCKIO = 400
6076 22:58:05.729025 MCKIO_SEMI = 400
6077 22:58:05.732586 PLL_FREQ = 3016
6078 22:58:05.735403 DQ_UI_PI_RATIO = 32
6079 22:58:05.738903 CA_UI_PI_RATIO = 32
6080 22:58:05.742266 ===================================
6081 22:58:05.745600 ===================================
6082 22:58:05.748931 memory_type:LPDDR4
6083 22:58:05.749083 GP_NUM : 10
6084 22:58:05.752259 SRAM_EN : 1
6085 22:58:05.752366 MD32_EN : 0
6086 22:58:05.755964 ===================================
6087 22:58:05.759057 [ANA_INIT] >>>>>>>>>>>>>>
6088 22:58:05.762412 <<<<<< [CONFIGURE PHASE]: ANA_TX
6089 22:58:05.765511 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6090 22:58:05.768877 ===================================
6091 22:58:05.771988 data_rate = 800,PCW = 0X7400
6092 22:58:05.775293 ===================================
6093 22:58:05.779111 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6094 22:58:05.782291 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6095 22:58:05.795533 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6096 22:58:05.799047 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6097 22:58:05.802290 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6098 22:58:05.805256 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6099 22:58:05.808776 [ANA_INIT] flow start
6100 22:58:05.812304 [ANA_INIT] PLL >>>>>>>>
6101 22:58:05.812422 [ANA_INIT] PLL <<<<<<<<
6102 22:58:05.815388 [ANA_INIT] MIDPI >>>>>>>>
6103 22:58:05.818746 [ANA_INIT] MIDPI <<<<<<<<
6104 22:58:05.818851 [ANA_INIT] DLL >>>>>>>>
6105 22:58:05.822254 [ANA_INIT] flow end
6106 22:58:05.825169 ============ LP4 DIFF to SE enter ============
6107 22:58:05.832213 ============ LP4 DIFF to SE exit ============
6108 22:58:05.832342 [ANA_INIT] <<<<<<<<<<<<<
6109 22:58:05.835121 [Flow] Enable top DCM control >>>>>
6110 22:58:05.838691 [Flow] Enable top DCM control <<<<<
6111 22:58:05.842168 Enable DLL master slave shuffle
6112 22:58:05.848412 ==============================================================
6113 22:58:05.848501 Gating Mode config
6114 22:58:05.855268 ==============================================================
6115 22:58:05.858464 Config description:
6116 22:58:05.864950 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6117 22:58:05.871919 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6118 22:58:05.878656 SELPH_MODE 0: By rank 1: By Phase
6119 22:58:05.884828 ==============================================================
6120 22:58:05.888138 GAT_TRACK_EN = 0
6121 22:58:05.888225 RX_GATING_MODE = 2
6122 22:58:05.891699 RX_GATING_TRACK_MODE = 2
6123 22:58:05.894956 SELPH_MODE = 1
6124 22:58:05.898301 PICG_EARLY_EN = 1
6125 22:58:05.901870 VALID_LAT_VALUE = 1
6126 22:58:05.908554 ==============================================================
6127 22:58:05.911404 Enter into Gating configuration >>>>
6128 22:58:05.914985 Exit from Gating configuration <<<<
6129 22:58:05.918376 Enter into DVFS_PRE_config >>>>>
6130 22:58:05.928203 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6131 22:58:05.932019 Exit from DVFS_PRE_config <<<<<
6132 22:58:05.935025 Enter into PICG configuration >>>>
6133 22:58:05.938381 Exit from PICG configuration <<<<
6134 22:58:05.941247 [RX_INPUT] configuration >>>>>
6135 22:58:05.941426 [RX_INPUT] configuration <<<<<
6136 22:58:05.947890 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6137 22:58:05.954575 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6138 22:58:05.961376 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6139 22:58:05.964456 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6140 22:58:05.971631 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6141 22:58:05.978069 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6142 22:58:05.981278 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6143 22:58:05.984858 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6144 22:58:05.991541 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6145 22:58:05.995141 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6146 22:58:05.998004 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6147 22:58:06.005343 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6148 22:58:06.007941 ===================================
6149 22:58:06.008050 LPDDR4 DRAM CONFIGURATION
6150 22:58:06.011426 ===================================
6151 22:58:06.014815 EX_ROW_EN[0] = 0x0
6152 22:58:06.014978 EX_ROW_EN[1] = 0x0
6153 22:58:06.017787 LP4Y_EN = 0x0
6154 22:58:06.017899 WORK_FSP = 0x0
6155 22:58:06.021358 WL = 0x2
6156 22:58:06.021467 RL = 0x2
6157 22:58:06.024834 BL = 0x2
6158 22:58:06.028285 RPST = 0x0
6159 22:58:06.028367 RD_PRE = 0x0
6160 22:58:06.031315 WR_PRE = 0x1
6161 22:58:06.031397 WR_PST = 0x0
6162 22:58:06.034559 DBI_WR = 0x0
6163 22:58:06.034643 DBI_RD = 0x0
6164 22:58:06.038074 OTF = 0x1
6165 22:58:06.041536 ===================================
6166 22:58:06.044614 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6167 22:58:06.048234 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6168 22:58:06.051651 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6169 22:58:06.054399 ===================================
6170 22:58:06.057745 LPDDR4 DRAM CONFIGURATION
6171 22:58:06.061004 ===================================
6172 22:58:06.064411 EX_ROW_EN[0] = 0x10
6173 22:58:06.064520 EX_ROW_EN[1] = 0x0
6174 22:58:06.067580 LP4Y_EN = 0x0
6175 22:58:06.067691 WORK_FSP = 0x0
6176 22:58:06.071172 WL = 0x2
6177 22:58:06.071283 RL = 0x2
6178 22:58:06.074333 BL = 0x2
6179 22:58:06.074456 RPST = 0x0
6180 22:58:06.077798 RD_PRE = 0x0
6181 22:58:06.080786 WR_PRE = 0x1
6182 22:58:06.080894 WR_PST = 0x0
6183 22:58:06.084036 DBI_WR = 0x0
6184 22:58:06.084155 DBI_RD = 0x0
6185 22:58:06.087617 OTF = 0x1
6186 22:58:06.091147 ===================================
6187 22:58:06.094085 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6188 22:58:06.099420 nWR fixed to 30
6189 22:58:06.102750 [ModeRegInit_LP4] CH0 RK0
6190 22:58:06.102913 [ModeRegInit_LP4] CH0 RK1
6191 22:58:06.105941 [ModeRegInit_LP4] CH1 RK0
6192 22:58:06.109736 [ModeRegInit_LP4] CH1 RK1
6193 22:58:06.109878 match AC timing 19
6194 22:58:06.116091 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6195 22:58:06.119465 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6196 22:58:06.122718 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6197 22:58:06.129247 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6198 22:58:06.132819 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6199 22:58:06.132946 ==
6200 22:58:06.136011 Dram Type= 6, Freq= 0, CH_0, rank 0
6201 22:58:06.139483 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6202 22:58:06.139592 ==
6203 22:58:06.145768 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6204 22:58:06.152917 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6205 22:58:06.156172 [CA 0] Center 36 (8~64) winsize 57
6206 22:58:06.159730 [CA 1] Center 36 (8~64) winsize 57
6207 22:58:06.162653 [CA 2] Center 36 (8~64) winsize 57
6208 22:58:06.162738 [CA 3] Center 36 (8~64) winsize 57
6209 22:58:06.165993 [CA 4] Center 36 (8~64) winsize 57
6210 22:58:06.169086 [CA 5] Center 36 (8~64) winsize 57
6211 22:58:06.169177
6212 22:58:06.176003 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6213 22:58:06.176144
6214 22:58:06.179310 [CATrainingPosCal] consider 1 rank data
6215 22:58:06.182615 u2DelayCellTimex100 = 270/100 ps
6216 22:58:06.185595 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6217 22:58:06.189108 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6218 22:58:06.192242 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6219 22:58:06.195831 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6220 22:58:06.199544 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6221 22:58:06.202776 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6222 22:58:06.202890
6223 22:58:06.205819 CA PerBit enable=1, Macro0, CA PI delay=36
6224 22:58:06.205908
6225 22:58:06.209253 [CBTSetCACLKResult] CA Dly = 36
6226 22:58:06.212262 CS Dly: 1 (0~32)
6227 22:58:06.212354 ==
6228 22:58:06.215846 Dram Type= 6, Freq= 0, CH_0, rank 1
6229 22:58:06.218971 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6230 22:58:06.219059 ==
6231 22:58:06.226050 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6232 22:58:06.229146 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6233 22:58:06.232399 [CA 0] Center 36 (8~64) winsize 57
6234 22:58:06.235714 [CA 1] Center 36 (8~64) winsize 57
6235 22:58:06.239238 [CA 2] Center 36 (8~64) winsize 57
6236 22:58:06.242638 [CA 3] Center 36 (8~64) winsize 57
6237 22:58:06.245631 [CA 4] Center 36 (8~64) winsize 57
6238 22:58:06.249183 [CA 5] Center 36 (8~64) winsize 57
6239 22:58:06.249265
6240 22:58:06.252171 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6241 22:58:06.252251
6242 22:58:06.255547 [CATrainingPosCal] consider 2 rank data
6243 22:58:06.259027 u2DelayCellTimex100 = 270/100 ps
6244 22:58:06.262483 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6245 22:58:06.265364 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6246 22:58:06.268802 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6247 22:58:06.275365 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6248 22:58:06.278798 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6249 22:58:06.282113 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6250 22:58:06.282269
6251 22:58:06.285926 CA PerBit enable=1, Macro0, CA PI delay=36
6252 22:58:06.286086
6253 22:58:06.289067 [CBTSetCACLKResult] CA Dly = 36
6254 22:58:06.289219 CS Dly: 1 (0~32)
6255 22:58:06.289350
6256 22:58:06.292173 ----->DramcWriteLeveling(PI) begin...
6257 22:58:06.292320 ==
6258 22:58:06.295434 Dram Type= 6, Freq= 0, CH_0, rank 0
6259 22:58:06.302605 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6260 22:58:06.302793 ==
6261 22:58:06.305477 Write leveling (Byte 0): 40 => 8
6262 22:58:06.308988 Write leveling (Byte 1): 40 => 8
6263 22:58:06.309151 DramcWriteLeveling(PI) end<-----
6264 22:58:06.309259
6265 22:58:06.312286 ==
6266 22:58:06.315967 Dram Type= 6, Freq= 0, CH_0, rank 0
6267 22:58:06.318755 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6268 22:58:06.318853 ==
6269 22:58:06.322502 [Gating] SW mode calibration
6270 22:58:06.328900 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6271 22:58:06.332154 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6272 22:58:06.339289 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6273 22:58:06.342139 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6274 22:58:06.345374 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6275 22:58:06.352185 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6276 22:58:06.355594 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6277 22:58:06.358851 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6278 22:58:06.365726 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6279 22:58:06.368742 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6280 22:58:06.372190 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6281 22:58:06.375628 Total UI for P1: 0, mck2ui 16
6282 22:58:06.378907 best dqsien dly found for B0: ( 0, 14, 24)
6283 22:58:06.382481 Total UI for P1: 0, mck2ui 16
6284 22:58:06.385430 best dqsien dly found for B1: ( 0, 14, 24)
6285 22:58:06.388798 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6286 22:58:06.392457 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6287 22:58:06.392546
6288 22:58:06.398968 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6289 22:58:06.402359 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6290 22:58:06.402448 [Gating] SW calibration Done
6291 22:58:06.405134 ==
6292 22:58:06.405218 Dram Type= 6, Freq= 0, CH_0, rank 0
6293 22:58:06.411783 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6294 22:58:06.411871 ==
6295 22:58:06.411936 RX Vref Scan: 0
6296 22:58:06.411996
6297 22:58:06.415126 RX Vref 0 -> 0, step: 1
6298 22:58:06.415240
6299 22:58:06.418732 RX Delay -410 -> 252, step: 16
6300 22:58:06.422389 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6301 22:58:06.425169 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6302 22:58:06.432127 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6303 22:58:06.435453 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6304 22:58:06.438951 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6305 22:58:06.442346 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6306 22:58:06.448818 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6307 22:58:06.451788 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6308 22:58:06.454999 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6309 22:58:06.458673 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6310 22:58:06.465018 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6311 22:58:06.468634 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6312 22:58:06.471676 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6313 22:58:06.475300 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6314 22:58:06.481630 iDelay=230, Bit 14, Center -11 (-250 ~ 229) 480
6315 22:58:06.485093 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6316 22:58:06.485174 ==
6317 22:58:06.488670 Dram Type= 6, Freq= 0, CH_0, rank 0
6318 22:58:06.491991 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6319 22:58:06.492073 ==
6320 22:58:06.495354 DQS Delay:
6321 22:58:06.495434 DQS0 = 27, DQS1 = 35
6322 22:58:06.498448 DQM Delay:
6323 22:58:06.498528 DQM0 = 12, DQM1 = 12
6324 22:58:06.498593 DQ Delay:
6325 22:58:06.501677 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6326 22:58:06.505003 DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =24
6327 22:58:06.508160 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6328 22:58:06.511830 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6329 22:58:06.511914
6330 22:58:06.511980
6331 22:58:06.512040 ==
6332 22:58:06.514794 Dram Type= 6, Freq= 0, CH_0, rank 0
6333 22:58:06.521741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6334 22:58:06.521840 ==
6335 22:58:06.521907
6336 22:58:06.521969
6337 22:58:06.522027 TX Vref Scan disable
6338 22:58:06.525317 == TX Byte 0 ==
6339 22:58:06.528388 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6340 22:58:06.531360 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6341 22:58:06.534860 == TX Byte 1 ==
6342 22:58:06.538342 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6343 22:58:06.541523 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6344 22:58:06.541648 ==
6345 22:58:06.544950 Dram Type= 6, Freq= 0, CH_0, rank 0
6346 22:58:06.551328 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6347 22:58:06.551424 ==
6348 22:58:06.551491
6349 22:58:06.551550
6350 22:58:06.551608 TX Vref Scan disable
6351 22:58:06.554787 == TX Byte 0 ==
6352 22:58:06.558378 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6353 22:58:06.562013 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6354 22:58:06.564886 == TX Byte 1 ==
6355 22:58:06.568404 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6356 22:58:06.571788 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6357 22:58:06.571875
6358 22:58:06.574972 [DATLAT]
6359 22:58:06.575070 Freq=400, CH0 RK0
6360 22:58:06.575136
6361 22:58:06.578328 DATLAT Default: 0xf
6362 22:58:06.578451 0, 0xFFFF, sum = 0
6363 22:58:06.581379 1, 0xFFFF, sum = 0
6364 22:58:06.581464 2, 0xFFFF, sum = 0
6365 22:58:06.584848 3, 0xFFFF, sum = 0
6366 22:58:06.584962 4, 0xFFFF, sum = 0
6367 22:58:06.588433 5, 0xFFFF, sum = 0
6368 22:58:06.588525 6, 0xFFFF, sum = 0
6369 22:58:06.591310 7, 0xFFFF, sum = 0
6370 22:58:06.591390 8, 0xFFFF, sum = 0
6371 22:58:06.594763 9, 0xFFFF, sum = 0
6372 22:58:06.594868 10, 0xFFFF, sum = 0
6373 22:58:06.598249 11, 0xFFFF, sum = 0
6374 22:58:06.601224 12, 0xFFFF, sum = 0
6375 22:58:06.601326 13, 0x0, sum = 1
6376 22:58:06.601422 14, 0x0, sum = 2
6377 22:58:06.604660 15, 0x0, sum = 3
6378 22:58:06.604794 16, 0x0, sum = 4
6379 22:58:06.607944 best_step = 14
6380 22:58:06.608026
6381 22:58:06.608090 ==
6382 22:58:06.611414 Dram Type= 6, Freq= 0, CH_0, rank 0
6383 22:58:06.614512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6384 22:58:06.614593 ==
6385 22:58:06.618202 RX Vref Scan: 1
6386 22:58:06.618285
6387 22:58:06.618348 RX Vref 0 -> 0, step: 1
6388 22:58:06.618408
6389 22:58:06.621451 RX Delay -311 -> 252, step: 8
6390 22:58:06.621532
6391 22:58:06.624300 Set Vref, RX VrefLevel [Byte0]: 55
6392 22:58:06.627952 [Byte1]: 50
6393 22:58:06.632627
6394 22:58:06.632707 Final RX Vref Byte 0 = 55 to rank0
6395 22:58:06.636138 Final RX Vref Byte 1 = 50 to rank0
6396 22:58:06.639727 Final RX Vref Byte 0 = 55 to rank1
6397 22:58:06.642522 Final RX Vref Byte 1 = 50 to rank1==
6398 22:58:06.646560 Dram Type= 6, Freq= 0, CH_0, rank 0
6399 22:58:06.652667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6400 22:58:06.652794 ==
6401 22:58:06.652892 DQS Delay:
6402 22:58:06.652988 DQS0 = 24, DQS1 = 36
6403 22:58:06.656132 DQM Delay:
6404 22:58:06.656231 DQM0 = 8, DQM1 = 13
6405 22:58:06.659600 DQ Delay:
6406 22:58:06.659700 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =4
6407 22:58:06.662615 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6408 22:58:06.666146 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6409 22:58:06.669610 DQ12 =20, DQ13 =16, DQ14 =24, DQ15 =20
6410 22:58:06.669700
6411 22:58:06.669763
6412 22:58:06.679669 [DQSOSCAuto] RK0, (LSB)MR18= 0xd1bd, (MSB)MR19= 0xc0c, tDQSOscB0 = 386 ps tDQSOscB1 = 384 ps
6413 22:58:06.682449 CH0 RK0: MR19=C0C, MR18=D1BD
6414 22:58:06.689369 CH0_RK0: MR19=0xC0C, MR18=0xD1BD, DQSOSC=384, MR23=63, INC=400, DEC=267
6415 22:58:06.689485 ==
6416 22:58:06.692986 Dram Type= 6, Freq= 0, CH_0, rank 1
6417 22:58:06.696231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6418 22:58:06.696312 ==
6419 22:58:06.699618 [Gating] SW mode calibration
6420 22:58:06.706072 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6421 22:58:06.709512 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6422 22:58:06.716070 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6423 22:58:06.719405 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6424 22:58:06.722544 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6425 22:58:06.729080 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6426 22:58:06.732739 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6427 22:58:06.736120 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6428 22:58:06.742788 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6429 22:58:06.746177 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6430 22:58:06.749809 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6431 22:58:06.752843 Total UI for P1: 0, mck2ui 16
6432 22:58:06.756208 best dqsien dly found for B0: ( 0, 14, 24)
6433 22:58:06.759251 Total UI for P1: 0, mck2ui 16
6434 22:58:06.762882 best dqsien dly found for B1: ( 0, 14, 24)
6435 22:58:06.766440 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6436 22:58:06.769456 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6437 22:58:06.769569
6438 22:58:06.776098 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6439 22:58:06.779237 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6440 22:58:06.779320 [Gating] SW calibration Done
6441 22:58:06.782368 ==
6442 22:58:06.785818 Dram Type= 6, Freq= 0, CH_0, rank 1
6443 22:58:06.789462 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6444 22:58:06.789547 ==
6445 22:58:06.789652 RX Vref Scan: 0
6446 22:58:06.789716
6447 22:58:06.792356 RX Vref 0 -> 0, step: 1
6448 22:58:06.792439
6449 22:58:06.795727 RX Delay -410 -> 252, step: 16
6450 22:58:06.799070 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6451 22:58:06.802570 iDelay=230, Bit 1, Center -11 (-234 ~ 213) 448
6452 22:58:06.809327 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6453 22:58:06.812712 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6454 22:58:06.815417 iDelay=230, Bit 4, Center -3 (-234 ~ 229) 464
6455 22:58:06.819266 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6456 22:58:06.825648 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6457 22:58:06.828712 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6458 22:58:06.832153 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6459 22:58:06.835721 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6460 22:58:06.842273 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6461 22:58:06.845547 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6462 22:58:06.849092 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6463 22:58:06.852462 iDelay=230, Bit 13, Center -11 (-234 ~ 213) 448
6464 22:58:06.859261 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6465 22:58:06.862420 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6466 22:58:06.862502 ==
6467 22:58:06.865573 Dram Type= 6, Freq= 0, CH_0, rank 1
6468 22:58:06.868599 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6469 22:58:06.868681 ==
6470 22:58:06.872274 DQS Delay:
6471 22:58:06.872355 DQS0 = 27, DQS1 = 35
6472 22:58:06.875856 DQM Delay:
6473 22:58:06.875938 DQM0 = 14, DQM1 = 12
6474 22:58:06.876003 DQ Delay:
6475 22:58:06.878607 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6476 22:58:06.882218 DQ4 =24, DQ5 =0, DQ6 =24, DQ7 =24
6477 22:58:06.885914 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6478 22:58:06.889198 DQ12 =16, DQ13 =24, DQ14 =24, DQ15 =16
6479 22:58:06.889280
6480 22:58:06.889345
6481 22:58:06.889405 ==
6482 22:58:06.891990 Dram Type= 6, Freq= 0, CH_0, rank 1
6483 22:58:06.898790 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6484 22:58:06.898873 ==
6485 22:58:06.898938
6486 22:58:06.898999
6487 22:58:06.899056 TX Vref Scan disable
6488 22:58:06.902300 == TX Byte 0 ==
6489 22:58:06.905636 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6490 22:58:06.908676 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6491 22:58:06.912372 == TX Byte 1 ==
6492 22:58:06.915656 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6493 22:58:06.918792 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6494 22:58:06.918878 ==
6495 22:58:06.922088 Dram Type= 6, Freq= 0, CH_0, rank 1
6496 22:58:06.928564 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6497 22:58:06.928650 ==
6498 22:58:06.928716
6499 22:58:06.928776
6500 22:58:06.928835 TX Vref Scan disable
6501 22:58:06.932049 == TX Byte 0 ==
6502 22:58:06.935686 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6503 22:58:06.938652 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6504 22:58:06.942143 == TX Byte 1 ==
6505 22:58:06.945793 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6506 22:58:06.948800 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6507 22:58:06.948885
6508 22:58:06.951980 [DATLAT]
6509 22:58:06.952062 Freq=400, CH0 RK1
6510 22:58:06.952128
6511 22:58:06.955191 DATLAT Default: 0xe
6512 22:58:06.955273 0, 0xFFFF, sum = 0
6513 22:58:06.958620 1, 0xFFFF, sum = 0
6514 22:58:06.958704 2, 0xFFFF, sum = 0
6515 22:58:06.962539 3, 0xFFFF, sum = 0
6516 22:58:06.962623 4, 0xFFFF, sum = 0
6517 22:58:06.965081 5, 0xFFFF, sum = 0
6518 22:58:06.965163 6, 0xFFFF, sum = 0
6519 22:58:06.968810 7, 0xFFFF, sum = 0
6520 22:58:06.968897 8, 0xFFFF, sum = 0
6521 22:58:06.972171 9, 0xFFFF, sum = 0
6522 22:58:06.972254 10, 0xFFFF, sum = 0
6523 22:58:06.974978 11, 0xFFFF, sum = 0
6524 22:58:06.978674 12, 0xFFFF, sum = 0
6525 22:58:06.978766 13, 0x0, sum = 1
6526 22:58:06.978832 14, 0x0, sum = 2
6527 22:58:06.981717 15, 0x0, sum = 3
6528 22:58:06.981800 16, 0x0, sum = 4
6529 22:58:06.984827 best_step = 14
6530 22:58:06.984908
6531 22:58:06.984973 ==
6532 22:58:06.988638 Dram Type= 6, Freq= 0, CH_0, rank 1
6533 22:58:06.992095 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6534 22:58:06.992177 ==
6535 22:58:06.995279 RX Vref Scan: 0
6536 22:58:06.995360
6537 22:58:06.995426 RX Vref 0 -> 0, step: 1
6538 22:58:06.995487
6539 22:58:06.998256 RX Delay -311 -> 252, step: 8
6540 22:58:07.006779 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6541 22:58:07.009734 iDelay=217, Bit 1, Center -12 (-231 ~ 208) 440
6542 22:58:07.013413 iDelay=217, Bit 2, Center -16 (-239 ~ 208) 448
6543 22:58:07.016748 iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448
6544 22:58:07.022828 iDelay=217, Bit 4, Center -12 (-231 ~ 208) 440
6545 22:58:07.026394 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6546 22:58:07.029747 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6547 22:58:07.032976 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6548 22:58:07.039630 iDelay=217, Bit 8, Center -28 (-247 ~ 192) 440
6549 22:58:07.042647 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6550 22:58:07.046238 iDelay=217, Bit 10, Center -20 (-239 ~ 200) 440
6551 22:58:07.052679 iDelay=217, Bit 11, Center -28 (-247 ~ 192) 440
6552 22:58:07.056057 iDelay=217, Bit 12, Center -16 (-231 ~ 200) 432
6553 22:58:07.059538 iDelay=217, Bit 13, Center -16 (-231 ~ 200) 432
6554 22:58:07.062749 iDelay=217, Bit 14, Center -12 (-231 ~ 208) 440
6555 22:58:07.069145 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6556 22:58:07.069229 ==
6557 22:58:07.072687 Dram Type= 6, Freq= 0, CH_0, rank 1
6558 22:58:07.076230 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6559 22:58:07.076314 ==
6560 22:58:07.076379 DQS Delay:
6561 22:58:07.079474 DQS0 = 24, DQS1 = 32
6562 22:58:07.079590 DQM Delay:
6563 22:58:07.082522 DQM0 = 9, DQM1 = 11
6564 22:58:07.082605 DQ Delay:
6565 22:58:07.085743 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =8
6566 22:58:07.089192 DQ4 =12, DQ5 =0, DQ6 =12, DQ7 =16
6567 22:58:07.092376 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =4
6568 22:58:07.095884 DQ12 =16, DQ13 =16, DQ14 =20, DQ15 =16
6569 22:58:07.095966
6570 22:58:07.096032
6571 22:58:07.102428 [DQSOSCAuto] RK1, (LSB)MR18= 0xba59, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 386 ps
6572 22:58:07.105856 CH0 RK1: MR19=C0C, MR18=BA59
6573 22:58:07.112616 CH0_RK1: MR19=0xC0C, MR18=0xBA59, DQSOSC=386, MR23=63, INC=396, DEC=264
6574 22:58:07.115747 [RxdqsGatingPostProcess] freq 400
6575 22:58:07.122688 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6576 22:58:07.125801 best DQS0 dly(2T, 0.5T) = (0, 10)
6577 22:58:07.125885 best DQS1 dly(2T, 0.5T) = (0, 10)
6578 22:58:07.128867 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6579 22:58:07.132309 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6580 22:58:07.136062 best DQS0 dly(2T, 0.5T) = (0, 10)
6581 22:58:07.139224 best DQS1 dly(2T, 0.5T) = (0, 10)
6582 22:58:07.142390 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6583 22:58:07.145772 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6584 22:58:07.149252 Pre-setting of DQS Precalculation
6585 22:58:07.155806 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6586 22:58:07.155881 ==
6587 22:58:07.158837 Dram Type= 6, Freq= 0, CH_1, rank 0
6588 22:58:07.162276 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6589 22:58:07.162356 ==
6590 22:58:07.169112 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6591 22:58:07.172573 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6592 22:58:07.175490 [CA 0] Center 36 (8~64) winsize 57
6593 22:58:07.179052 [CA 1] Center 36 (8~64) winsize 57
6594 22:58:07.182037 [CA 2] Center 36 (8~64) winsize 57
6595 22:58:07.185742 [CA 3] Center 36 (8~64) winsize 57
6596 22:58:07.189183 [CA 4] Center 36 (8~64) winsize 57
6597 22:58:07.192165 [CA 5] Center 36 (8~64) winsize 57
6598 22:58:07.192234
6599 22:58:07.195661 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6600 22:58:07.195747
6601 22:58:07.198660 [CATrainingPosCal] consider 1 rank data
6602 22:58:07.202181 u2DelayCellTimex100 = 270/100 ps
6603 22:58:07.205620 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6604 22:58:07.208791 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6605 22:58:07.212236 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6606 22:58:07.218893 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6607 22:58:07.222134 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6608 22:58:07.225314 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6609 22:58:07.225423
6610 22:58:07.228751 CA PerBit enable=1, Macro0, CA PI delay=36
6611 22:58:07.228835
6612 22:58:07.231927 [CBTSetCACLKResult] CA Dly = 36
6613 22:58:07.232033 CS Dly: 1 (0~32)
6614 22:58:07.232129 ==
6615 22:58:07.235457 Dram Type= 6, Freq= 0, CH_1, rank 1
6616 22:58:07.241818 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6617 22:58:07.241906 ==
6618 22:58:07.245519 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6619 22:58:07.251756 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6620 22:58:07.255182 [CA 0] Center 36 (8~64) winsize 57
6621 22:58:07.258796 [CA 1] Center 36 (8~64) winsize 57
6622 22:58:07.261646 [CA 2] Center 36 (8~64) winsize 57
6623 22:58:07.265121 [CA 3] Center 36 (8~64) winsize 57
6624 22:58:07.268461 [CA 4] Center 36 (8~64) winsize 57
6625 22:58:07.272080 [CA 5] Center 36 (8~64) winsize 57
6626 22:58:07.272189
6627 22:58:07.274967 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6628 22:58:07.275039
6629 22:58:07.278300 [CATrainingPosCal] consider 2 rank data
6630 22:58:07.281750 u2DelayCellTimex100 = 270/100 ps
6631 22:58:07.285265 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6632 22:58:07.288214 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6633 22:58:07.291917 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6634 22:58:07.295324 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6635 22:58:07.298144 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6636 22:58:07.301925 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6637 22:58:07.302026
6638 22:58:07.308217 CA PerBit enable=1, Macro0, CA PI delay=36
6639 22:58:07.308290
6640 22:58:07.311628 [CBTSetCACLKResult] CA Dly = 36
6641 22:58:07.311704 CS Dly: 1 (0~32)
6642 22:58:07.311766
6643 22:58:07.315214 ----->DramcWriteLeveling(PI) begin...
6644 22:58:07.315286 ==
6645 22:58:07.318581 Dram Type= 6, Freq= 0, CH_1, rank 0
6646 22:58:07.321765 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6647 22:58:07.321864 ==
6648 22:58:07.325012 Write leveling (Byte 0): 40 => 8
6649 22:58:07.328183 Write leveling (Byte 1): 40 => 8
6650 22:58:07.331785 DramcWriteLeveling(PI) end<-----
6651 22:58:07.331870
6652 22:58:07.331935 ==
6653 22:58:07.335113 Dram Type= 6, Freq= 0, CH_1, rank 0
6654 22:58:07.338326 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6655 22:58:07.341953 ==
6656 22:58:07.342058 [Gating] SW mode calibration
6657 22:58:07.348539 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6658 22:58:07.355261 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6659 22:58:07.358672 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6660 22:58:07.365181 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6661 22:58:07.368461 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6662 22:58:07.371788 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6663 22:58:07.378291 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6664 22:58:07.381653 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6665 22:58:07.385216 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6666 22:58:07.391656 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6667 22:58:07.395129 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6668 22:58:07.398716 Total UI for P1: 0, mck2ui 16
6669 22:58:07.401583 best dqsien dly found for B0: ( 0, 14, 24)
6670 22:58:07.405128 Total UI for P1: 0, mck2ui 16
6671 22:58:07.408641 best dqsien dly found for B1: ( 0, 14, 24)
6672 22:58:07.411567 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6673 22:58:07.415026 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6674 22:58:07.415109
6675 22:58:07.418650 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6676 22:58:07.421535 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6677 22:58:07.424927 [Gating] SW calibration Done
6678 22:58:07.425010 ==
6679 22:58:07.428436 Dram Type= 6, Freq= 0, CH_1, rank 0
6680 22:58:07.431783 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6681 22:58:07.431866 ==
6682 22:58:07.435085 RX Vref Scan: 0
6683 22:58:07.435171
6684 22:58:07.438028 RX Vref 0 -> 0, step: 1
6685 22:58:07.438101
6686 22:58:07.438165 RX Delay -410 -> 252, step: 16
6687 22:58:07.445216 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6688 22:58:07.448076 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6689 22:58:07.451875 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6690 22:58:07.458067 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6691 22:58:07.461368 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6692 22:58:07.465037 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6693 22:58:07.468411 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6694 22:58:07.471604 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6695 22:58:07.478404 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6696 22:58:07.481495 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6697 22:58:07.484968 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6698 22:58:07.488235 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6699 22:58:07.494680 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6700 22:58:07.498236 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6701 22:58:07.501145 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6702 22:58:07.508218 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6703 22:58:07.508297 ==
6704 22:58:07.511319 Dram Type= 6, Freq= 0, CH_1, rank 0
6705 22:58:07.514737 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6706 22:58:07.514815 ==
6707 22:58:07.514877 DQS Delay:
6708 22:58:07.518256 DQS0 = 27, DQS1 = 35
6709 22:58:07.518337 DQM Delay:
6710 22:58:07.521740 DQM0 = 11, DQM1 = 13
6711 22:58:07.521818 DQ Delay:
6712 22:58:07.524782 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6713 22:58:07.528073 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6714 22:58:07.531382 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6715 22:58:07.534826 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6716 22:58:07.534907
6717 22:58:07.534971
6718 22:58:07.535031 ==
6719 22:58:07.538186 Dram Type= 6, Freq= 0, CH_1, rank 0
6720 22:58:07.541711 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6721 22:58:07.541787 ==
6722 22:58:07.541850
6723 22:58:07.541917
6724 22:58:07.544835 TX Vref Scan disable
6725 22:58:07.544914 == TX Byte 0 ==
6726 22:58:07.551827 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6727 22:58:07.554753 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6728 22:58:07.554825 == TX Byte 1 ==
6729 22:58:07.561567 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6730 22:58:07.564970 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6731 22:58:07.565050 ==
6732 22:58:07.568112 Dram Type= 6, Freq= 0, CH_1, rank 0
6733 22:58:07.571253 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6734 22:58:07.571325 ==
6735 22:58:07.571386
6736 22:58:07.571452
6737 22:58:07.574689 TX Vref Scan disable
6738 22:58:07.574762 == TX Byte 0 ==
6739 22:58:07.581667 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6740 22:58:07.585102 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6741 22:58:07.585177 == TX Byte 1 ==
6742 22:58:07.591311 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6743 22:58:07.594691 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6744 22:58:07.594765
6745 22:58:07.594827 [DATLAT]
6746 22:58:07.598176 Freq=400, CH1 RK0
6747 22:58:07.598246
6748 22:58:07.598306 DATLAT Default: 0xf
6749 22:58:07.601514 0, 0xFFFF, sum = 0
6750 22:58:07.601615 1, 0xFFFF, sum = 0
6751 22:58:07.604616 2, 0xFFFF, sum = 0
6752 22:58:07.604697 3, 0xFFFF, sum = 0
6753 22:58:07.608411 4, 0xFFFF, sum = 0
6754 22:58:07.608482 5, 0xFFFF, sum = 0
6755 22:58:07.611292 6, 0xFFFF, sum = 0
6756 22:58:07.611363 7, 0xFFFF, sum = 0
6757 22:58:07.614538 8, 0xFFFF, sum = 0
6758 22:58:07.614616 9, 0xFFFF, sum = 0
6759 22:58:07.617835 10, 0xFFFF, sum = 0
6760 22:58:07.621299 11, 0xFFFF, sum = 0
6761 22:58:07.621373 12, 0xFFFF, sum = 0
6762 22:58:07.624819 13, 0x0, sum = 1
6763 22:58:07.624896 14, 0x0, sum = 2
6764 22:58:07.624960 15, 0x0, sum = 3
6765 22:58:07.628415 16, 0x0, sum = 4
6766 22:58:07.628487 best_step = 14
6767 22:58:07.628547
6768 22:58:07.628604 ==
6769 22:58:07.631298 Dram Type= 6, Freq= 0, CH_1, rank 0
6770 22:58:07.638069 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6771 22:58:07.638154 ==
6772 22:58:07.638220 RX Vref Scan: 1
6773 22:58:07.638280
6774 22:58:07.641766 RX Vref 0 -> 0, step: 1
6775 22:58:07.641843
6776 22:58:07.644842 RX Delay -311 -> 252, step: 8
6777 22:58:07.644922
6778 22:58:07.648181 Set Vref, RX VrefLevel [Byte0]: 55
6779 22:58:07.651176 [Byte1]: 48
6780 22:58:07.654659
6781 22:58:07.654733 Final RX Vref Byte 0 = 55 to rank0
6782 22:58:07.658222 Final RX Vref Byte 1 = 48 to rank0
6783 22:58:07.661301 Final RX Vref Byte 0 = 55 to rank1
6784 22:58:07.664676 Final RX Vref Byte 1 = 48 to rank1==
6785 22:58:07.668159 Dram Type= 6, Freq= 0, CH_1, rank 0
6786 22:58:07.674393 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6787 22:58:07.674467 ==
6788 22:58:07.674538 DQS Delay:
6789 22:58:07.674597 DQS0 = 28, DQS1 = 32
6790 22:58:07.677848 DQM Delay:
6791 22:58:07.677923 DQM0 = 9, DQM1 = 11
6792 22:58:07.681503 DQ Delay:
6793 22:58:07.681583 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =8
6794 22:58:07.684814 DQ4 =8, DQ5 =20, DQ6 =16, DQ7 =8
6795 22:58:07.687795 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
6796 22:58:07.690957 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =24
6797 22:58:07.691032
6798 22:58:07.691094
6799 22:58:07.701080 [DQSOSCAuto] RK0, (LSB)MR18= 0x91c9, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 391 ps
6800 22:58:07.704408 CH1 RK0: MR19=C0C, MR18=91C9
6801 22:58:07.710998 CH1_RK0: MR19=0xC0C, MR18=0x91C9, DQSOSC=384, MR23=63, INC=400, DEC=267
6802 22:58:07.711075 ==
6803 22:58:07.714314 Dram Type= 6, Freq= 0, CH_1, rank 1
6804 22:58:07.717600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6805 22:58:07.717684 ==
6806 22:58:07.720814 [Gating] SW mode calibration
6807 22:58:07.727816 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6808 22:58:07.730704 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6809 22:58:07.737750 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6810 22:58:07.741156 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6811 22:58:07.744256 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6812 22:58:07.750941 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6813 22:58:07.754262 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6814 22:58:07.757887 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6815 22:58:07.764364 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6816 22:58:07.767384 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6817 22:58:07.770814 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6818 22:58:07.774503 Total UI for P1: 0, mck2ui 16
6819 22:58:07.777590 best dqsien dly found for B0: ( 0, 14, 24)
6820 22:58:07.781019 Total UI for P1: 0, mck2ui 16
6821 22:58:07.784237 best dqsien dly found for B1: ( 0, 14, 24)
6822 22:58:07.787652 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6823 22:58:07.790998 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6824 22:58:07.791071
6825 22:58:07.797256 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6826 22:58:07.801054 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6827 22:58:07.801126 [Gating] SW calibration Done
6828 22:58:07.804480 ==
6829 22:58:07.807391 Dram Type= 6, Freq= 0, CH_1, rank 1
6830 22:58:07.810594 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6831 22:58:07.810665 ==
6832 22:58:07.810727 RX Vref Scan: 0
6833 22:58:07.810793
6834 22:58:07.814181 RX Vref 0 -> 0, step: 1
6835 22:58:07.814257
6836 22:58:07.817366 RX Delay -410 -> 252, step: 16
6837 22:58:07.820717 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6838 22:58:07.827412 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6839 22:58:07.830832 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6840 22:58:07.833760 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6841 22:58:07.837333 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6842 22:58:07.840388 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6843 22:58:07.847011 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6844 22:58:07.850566 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6845 22:58:07.854064 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6846 22:58:07.857427 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6847 22:58:07.864130 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6848 22:58:07.867121 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6849 22:58:07.870674 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6850 22:58:07.874233 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6851 22:58:07.880653 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6852 22:58:07.883627 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6853 22:58:07.883710 ==
6854 22:58:07.887070 Dram Type= 6, Freq= 0, CH_1, rank 1
6855 22:58:07.890532 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6856 22:58:07.890615 ==
6857 22:58:07.893921 DQS Delay:
6858 22:58:07.894002 DQS0 = 35, DQS1 = 35
6859 22:58:07.897547 DQM Delay:
6860 22:58:07.897651 DQM0 = 18, DQM1 = 13
6861 22:58:07.897717 DQ Delay:
6862 22:58:07.900301 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6863 22:58:07.903585 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6864 22:58:07.907014 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6865 22:58:07.910757 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6866 22:58:07.910875
6867 22:58:07.910939
6868 22:58:07.911000 ==
6869 22:58:07.913648 Dram Type= 6, Freq= 0, CH_1, rank 1
6870 22:58:07.920281 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6871 22:58:07.920360 ==
6872 22:58:07.920471
6873 22:58:07.920532
6874 22:58:07.920590 TX Vref Scan disable
6875 22:58:07.923892 == TX Byte 0 ==
6876 22:58:07.927063 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6877 22:58:07.930656 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6878 22:58:07.933934 == TX Byte 1 ==
6879 22:58:07.936842 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6880 22:58:07.940223 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6881 22:58:07.940306 ==
6882 22:58:07.944017 Dram Type= 6, Freq= 0, CH_1, rank 1
6883 22:58:07.950453 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6884 22:58:07.950536 ==
6885 22:58:07.950603
6886 22:58:07.950666
6887 22:58:07.953507 TX Vref Scan disable
6888 22:58:07.953620 == TX Byte 0 ==
6889 22:58:07.956772 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6890 22:58:07.963780 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6891 22:58:07.963863 == TX Byte 1 ==
6892 22:58:07.966928 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6893 22:58:07.969980 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6894 22:58:07.973351
6895 22:58:07.973432 [DATLAT]
6896 22:58:07.973498 Freq=400, CH1 RK1
6897 22:58:07.973560
6898 22:58:07.976947 DATLAT Default: 0xe
6899 22:58:07.977028 0, 0xFFFF, sum = 0
6900 22:58:07.980308 1, 0xFFFF, sum = 0
6901 22:58:07.980392 2, 0xFFFF, sum = 0
6902 22:58:07.983390 3, 0xFFFF, sum = 0
6903 22:58:07.983474 4, 0xFFFF, sum = 0
6904 22:58:07.986964 5, 0xFFFF, sum = 0
6905 22:58:07.987048 6, 0xFFFF, sum = 0
6906 22:58:07.990566 7, 0xFFFF, sum = 0
6907 22:58:07.993289 8, 0xFFFF, sum = 0
6908 22:58:07.993373 9, 0xFFFF, sum = 0
6909 22:58:07.996703 10, 0xFFFF, sum = 0
6910 22:58:07.996787 11, 0xFFFF, sum = 0
6911 22:58:08.000168 12, 0xFFFF, sum = 0
6912 22:58:08.000252 13, 0x0, sum = 1
6913 22:58:08.003292 14, 0x0, sum = 2
6914 22:58:08.003376 15, 0x0, sum = 3
6915 22:58:08.006846 16, 0x0, sum = 4
6916 22:58:08.006930 best_step = 14
6917 22:58:08.006995
6918 22:58:08.007055 ==
6919 22:58:08.010139 Dram Type= 6, Freq= 0, CH_1, rank 1
6920 22:58:08.013373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6921 22:58:08.013456 ==
6922 22:58:08.017114 RX Vref Scan: 0
6923 22:58:08.017196
6924 22:58:08.020612 RX Vref 0 -> 0, step: 1
6925 22:58:08.020695
6926 22:58:08.020761 RX Delay -311 -> 252, step: 8
6927 22:58:08.029033 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6928 22:58:08.031742 iDelay=217, Bit 1, Center -20 (-239 ~ 200) 440
6929 22:58:08.035402 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
6930 22:58:08.038423 iDelay=217, Bit 3, Center -20 (-239 ~ 200) 440
6931 22:58:08.045453 iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440
6932 22:58:08.048539 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
6933 22:58:08.052068 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6934 22:58:08.054962 iDelay=217, Bit 7, Center -16 (-239 ~ 208) 448
6935 22:58:08.061833 iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448
6936 22:58:08.065516 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6937 22:58:08.068783 iDelay=217, Bit 10, Center -20 (-247 ~ 208) 456
6938 22:58:08.072319 iDelay=217, Bit 11, Center -24 (-247 ~ 200) 448
6939 22:58:08.078596 iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456
6940 22:58:08.081548 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
6941 22:58:08.085108 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6942 22:58:08.088525 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
6943 22:58:08.092075 ==
6944 22:58:08.095029 Dram Type= 6, Freq= 0, CH_1, rank 1
6945 22:58:08.098346 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6946 22:58:08.098428 ==
6947 22:58:08.098492 DQS Delay:
6948 22:58:08.101944 DQS0 = 28, DQS1 = 32
6949 22:58:08.102014 DQM Delay:
6950 22:58:08.105436 DQM0 = 11, DQM1 = 11
6951 22:58:08.105538 DQ Delay:
6952 22:58:08.108514 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6953 22:58:08.111994 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =12
6954 22:58:08.115150 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8
6955 22:58:08.118268 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =20
6956 22:58:08.118345
6957 22:58:08.118408
6958 22:58:08.125367 [DQSOSCAuto] RK1, (LSB)MR18= 0xc859, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 385 ps
6959 22:58:08.128537 CH1 RK1: MR19=C0C, MR18=C859
6960 22:58:08.135280 CH1_RK1: MR19=0xC0C, MR18=0xC859, DQSOSC=385, MR23=63, INC=398, DEC=265
6961 22:58:08.138366 [RxdqsGatingPostProcess] freq 400
6962 22:58:08.141562 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6963 22:58:08.145248 best DQS0 dly(2T, 0.5T) = (0, 10)
6964 22:58:08.148532 best DQS1 dly(2T, 0.5T) = (0, 10)
6965 22:58:08.151435 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6966 22:58:08.154972 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6967 22:58:08.158584 best DQS0 dly(2T, 0.5T) = (0, 10)
6968 22:58:08.161449 best DQS1 dly(2T, 0.5T) = (0, 10)
6969 22:58:08.165087 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6970 22:58:08.168640 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6971 22:58:08.172163 Pre-setting of DQS Precalculation
6972 22:58:08.174863 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6973 22:58:08.184631 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6974 22:58:08.191657 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6975 22:58:08.191736
6976 22:58:08.191802
6977 22:58:08.194842 [Calibration Summary] 800 Mbps
6978 22:58:08.194919 CH 0, Rank 0
6979 22:58:08.198167 SW Impedance : PASS
6980 22:58:08.198237 DUTY Scan : NO K
6981 22:58:08.201423 ZQ Calibration : PASS
6982 22:58:08.205013 Jitter Meter : NO K
6983 22:58:08.205084 CBT Training : PASS
6984 22:58:08.208154 Write leveling : PASS
6985 22:58:08.211628 RX DQS gating : PASS
6986 22:58:08.211704 RX DQ/DQS(RDDQC) : PASS
6987 22:58:08.215210 TX DQ/DQS : PASS
6988 22:58:08.218163 RX DATLAT : PASS
6989 22:58:08.218244 RX DQ/DQS(Engine): PASS
6990 22:58:08.221774 TX OE : NO K
6991 22:58:08.221846 All Pass.
6992 22:58:08.221907
6993 22:58:08.225013 CH 0, Rank 1
6994 22:58:08.225083 SW Impedance : PASS
6995 22:58:08.228226 DUTY Scan : NO K
6996 22:58:08.228296 ZQ Calibration : PASS
6997 22:58:08.231354 Jitter Meter : NO K
6998 22:58:08.234730 CBT Training : PASS
6999 22:58:08.234802 Write leveling : NO K
7000 22:58:08.237979 RX DQS gating : PASS
7001 22:58:08.241379 RX DQ/DQS(RDDQC) : PASS
7002 22:58:08.241465 TX DQ/DQS : PASS
7003 22:58:08.244846 RX DATLAT : PASS
7004 22:58:08.248172 RX DQ/DQS(Engine): PASS
7005 22:58:08.248244 TX OE : NO K
7006 22:58:08.251290 All Pass.
7007 22:58:08.251364
7008 22:58:08.251425 CH 1, Rank 0
7009 22:58:08.254844 SW Impedance : PASS
7010 22:58:08.254923 DUTY Scan : NO K
7011 22:58:08.258192 ZQ Calibration : PASS
7012 22:58:08.261765 Jitter Meter : NO K
7013 22:58:08.261836 CBT Training : PASS
7014 22:58:08.264718 Write leveling : PASS
7015 22:58:08.267689 RX DQS gating : PASS
7016 22:58:08.267759 RX DQ/DQS(RDDQC) : PASS
7017 22:58:08.271370 TX DQ/DQS : PASS
7018 22:58:08.271441 RX DATLAT : PASS
7019 22:58:08.274740 RX DQ/DQS(Engine): PASS
7020 22:58:08.277787 TX OE : NO K
7021 22:58:08.277857 All Pass.
7022 22:58:08.277918
7023 22:58:08.277976 CH 1, Rank 1
7024 22:58:08.281217 SW Impedance : PASS
7025 22:58:08.284570 DUTY Scan : NO K
7026 22:58:08.284640 ZQ Calibration : PASS
7027 22:58:08.288027 Jitter Meter : NO K
7028 22:58:08.291156 CBT Training : PASS
7029 22:58:08.291233 Write leveling : NO K
7030 22:58:08.294375 RX DQS gating : PASS
7031 22:58:08.297795 RX DQ/DQS(RDDQC) : PASS
7032 22:58:08.297876 TX DQ/DQS : PASS
7033 22:58:08.300843 RX DATLAT : PASS
7034 22:58:08.304461 RX DQ/DQS(Engine): PASS
7035 22:58:08.304532 TX OE : NO K
7036 22:58:08.320930 All Pass.
7037 22:58:08.321063
7038 22:58:08.321164 DramC Write-DBI off
7039 22:58:08.321263 PER_BANK_REFRESH: Hybrid Mode
7040 22:58:08.321347 TX_TRACKING: ON
7041 22:58:08.321652 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7042 22:58:08.324610 [FAST_K] Save calibration result to emmc
7043 22:58:08.327735 dramc_set_vcore_voltage set vcore to 725000
7044 22:58:08.331204 Read voltage for 1600, 0
7045 22:58:08.331276 Vio18 = 0
7046 22:58:08.334407 Vcore = 725000
7047 22:58:08.334479 Vdram = 0
7048 22:58:08.334541 Vddq = 0
7049 22:58:08.337605 Vmddr = 0
7050 22:58:08.340981 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7051 22:58:08.347637 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7052 22:58:08.347721 MEM_TYPE=3, freq_sel=13
7053 22:58:08.350851 sv_algorithm_assistance_LP4_3733
7054 22:58:08.357756 ============ PULL DRAM RESETB DOWN ============
7055 22:58:08.360704 ========== PULL DRAM RESETB DOWN end =========
7056 22:58:08.363915 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7057 22:58:08.367752 ===================================
7058 22:58:08.370646 LPDDR4 DRAM CONFIGURATION
7059 22:58:08.374072 ===================================
7060 22:58:08.374144 EX_ROW_EN[0] = 0x0
7061 22:58:08.377695 EX_ROW_EN[1] = 0x0
7062 22:58:08.380586 LP4Y_EN = 0x0
7063 22:58:08.380656 WORK_FSP = 0x1
7064 22:58:08.384317 WL = 0x5
7065 22:58:08.384397 RL = 0x5
7066 22:58:08.387599 BL = 0x2
7067 22:58:08.387676 RPST = 0x0
7068 22:58:08.390475 RD_PRE = 0x0
7069 22:58:08.390545 WR_PRE = 0x1
7070 22:58:08.394041 WR_PST = 0x1
7071 22:58:08.394117 DBI_WR = 0x0
7072 22:58:08.397084 DBI_RD = 0x0
7073 22:58:08.397155 OTF = 0x1
7074 22:58:08.401114 ===================================
7075 22:58:08.403674 ===================================
7076 22:58:08.407129 ANA top config
7077 22:58:08.410614 ===================================
7078 22:58:08.410687 DLL_ASYNC_EN = 0
7079 22:58:08.414127 ALL_SLAVE_EN = 0
7080 22:58:08.417143 NEW_RANK_MODE = 1
7081 22:58:08.420391 DLL_IDLE_MODE = 1
7082 22:58:08.423654 LP45_APHY_COMB_EN = 1
7083 22:58:08.423731 TX_ODT_DIS = 0
7084 22:58:08.427191 NEW_8X_MODE = 1
7085 22:58:08.430751 ===================================
7086 22:58:08.434088 ===================================
7087 22:58:08.437186 data_rate = 3200
7088 22:58:08.440660 CKR = 1
7089 22:58:08.443795 DQ_P2S_RATIO = 8
7090 22:58:08.447289 ===================================
7091 22:58:08.447367 CA_P2S_RATIO = 8
7092 22:58:08.450258 DQ_CA_OPEN = 0
7093 22:58:08.453558 DQ_SEMI_OPEN = 0
7094 22:58:08.457386 CA_SEMI_OPEN = 0
7095 22:58:08.460651 CA_FULL_RATE = 0
7096 22:58:08.463917 DQ_CKDIV4_EN = 0
7097 22:58:08.463994 CA_CKDIV4_EN = 0
7098 22:58:08.467214 CA_PREDIV_EN = 0
7099 22:58:08.470419 PH8_DLY = 12
7100 22:58:08.473564 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7101 22:58:08.476936 DQ_AAMCK_DIV = 4
7102 22:58:08.480562 CA_AAMCK_DIV = 4
7103 22:58:08.480637 CA_ADMCK_DIV = 4
7104 22:58:08.483864 DQ_TRACK_CA_EN = 0
7105 22:58:08.486884 CA_PICK = 1600
7106 22:58:08.490413 CA_MCKIO = 1600
7107 22:58:08.493714 MCKIO_SEMI = 0
7108 22:58:08.496719 PLL_FREQ = 3068
7109 22:58:08.500188 DQ_UI_PI_RATIO = 32
7110 22:58:08.503831 CA_UI_PI_RATIO = 0
7111 22:58:08.506619 ===================================
7112 22:58:08.510133 ===================================
7113 22:58:08.510214 memory_type:LPDDR4
7114 22:58:08.513558 GP_NUM : 10
7115 22:58:08.513637 SRAM_EN : 1
7116 22:58:08.516576 MD32_EN : 0
7117 22:58:08.520058 ===================================
7118 22:58:08.523471 [ANA_INIT] >>>>>>>>>>>>>>
7119 22:58:08.526650 <<<<<< [CONFIGURE PHASE]: ANA_TX
7120 22:58:08.530142 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7121 22:58:08.533668 ===================================
7122 22:58:08.533745 data_rate = 3200,PCW = 0X7600
7123 22:58:08.536643 ===================================
7124 22:58:08.540439 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7125 22:58:08.546887 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7126 22:58:08.553232 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7127 22:58:08.556801 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7128 22:58:08.560278 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7129 22:58:08.563806 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7130 22:58:08.567019 [ANA_INIT] flow start
7131 22:58:08.569817 [ANA_INIT] PLL >>>>>>>>
7132 22:58:08.569896 [ANA_INIT] PLL <<<<<<<<
7133 22:58:08.573142 [ANA_INIT] MIDPI >>>>>>>>
7134 22:58:08.576831 [ANA_INIT] MIDPI <<<<<<<<
7135 22:58:08.576900 [ANA_INIT] DLL >>>>>>>>
7136 22:58:08.579943 [ANA_INIT] DLL <<<<<<<<
7137 22:58:08.583692 [ANA_INIT] flow end
7138 22:58:08.586691 ============ LP4 DIFF to SE enter ============
7139 22:58:08.590365 ============ LP4 DIFF to SE exit ============
7140 22:58:08.593096 [ANA_INIT] <<<<<<<<<<<<<
7141 22:58:08.597094 [Flow] Enable top DCM control >>>>>
7142 22:58:08.600084 [Flow] Enable top DCM control <<<<<
7143 22:58:08.603673 Enable DLL master slave shuffle
7144 22:58:08.606762 ==============================================================
7145 22:58:08.610289 Gating Mode config
7146 22:58:08.617057 ==============================================================
7147 22:58:08.617132 Config description:
7148 22:58:08.626730 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7149 22:58:08.633296 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7150 22:58:08.636845 SELPH_MODE 0: By rank 1: By Phase
7151 22:58:08.643202 ==============================================================
7152 22:58:08.646482 GAT_TRACK_EN = 1
7153 22:58:08.649766 RX_GATING_MODE = 2
7154 22:58:08.652820 RX_GATING_TRACK_MODE = 2
7155 22:58:08.656249 SELPH_MODE = 1
7156 22:58:08.659498 PICG_EARLY_EN = 1
7157 22:58:08.663388 VALID_LAT_VALUE = 1
7158 22:58:08.666672 ==============================================================
7159 22:58:08.669737 Enter into Gating configuration >>>>
7160 22:58:08.673090 Exit from Gating configuration <<<<
7161 22:58:08.675965 Enter into DVFS_PRE_config >>>>>
7162 22:58:08.689230 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7163 22:58:08.689311 Exit from DVFS_PRE_config <<<<<
7164 22:58:08.693037 Enter into PICG configuration >>>>
7165 22:58:08.696581 Exit from PICG configuration <<<<
7166 22:58:08.699435 [RX_INPUT] configuration >>>>>
7167 22:58:08.702767 [RX_INPUT] configuration <<<<<
7168 22:58:08.709589 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7169 22:58:08.712563 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7170 22:58:08.719574 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7171 22:58:08.726387 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7172 22:58:08.732696 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7173 22:58:08.739316 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7174 22:58:08.742960 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7175 22:58:08.745728 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7176 22:58:08.749085 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7177 22:58:08.755779 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7178 22:58:08.759164 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7179 22:58:08.762259 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7180 22:58:08.766035 ===================================
7181 22:58:08.769330 LPDDR4 DRAM CONFIGURATION
7182 22:58:08.772559 ===================================
7183 22:58:08.772630 EX_ROW_EN[0] = 0x0
7184 22:58:08.775755 EX_ROW_EN[1] = 0x0
7185 22:58:08.779030 LP4Y_EN = 0x0
7186 22:58:08.779098 WORK_FSP = 0x1
7187 22:58:08.782665 WL = 0x5
7188 22:58:08.782736 RL = 0x5
7189 22:58:08.785788 BL = 0x2
7190 22:58:08.785863 RPST = 0x0
7191 22:58:08.788913 RD_PRE = 0x0
7192 22:58:08.788981 WR_PRE = 0x1
7193 22:58:08.792414 WR_PST = 0x1
7194 22:58:08.792488 DBI_WR = 0x0
7195 22:58:08.795939 DBI_RD = 0x0
7196 22:58:08.796007 OTF = 0x1
7197 22:58:08.799097 ===================================
7198 22:58:08.802151 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7199 22:58:08.808685 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7200 22:58:08.812256 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7201 22:58:08.815835 ===================================
7202 22:58:08.818763 LPDDR4 DRAM CONFIGURATION
7203 22:58:08.822199 ===================================
7204 22:58:08.822272 EX_ROW_EN[0] = 0x10
7205 22:58:08.825634 EX_ROW_EN[1] = 0x0
7206 22:58:08.825709 LP4Y_EN = 0x0
7207 22:58:08.829165 WORK_FSP = 0x1
7208 22:58:08.832364 WL = 0x5
7209 22:58:08.832432 RL = 0x5
7210 22:58:08.835249 BL = 0x2
7211 22:58:08.835316 RPST = 0x0
7212 22:58:08.838759 RD_PRE = 0x0
7213 22:58:08.838826 WR_PRE = 0x1
7214 22:58:08.842281 WR_PST = 0x1
7215 22:58:08.842352 DBI_WR = 0x0
7216 22:58:08.845223 DBI_RD = 0x0
7217 22:58:08.845289 OTF = 0x1
7218 22:58:08.848860 ===================================
7219 22:58:08.855099 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7220 22:58:08.855170 ==
7221 22:58:08.858669 Dram Type= 6, Freq= 0, CH_0, rank 0
7222 22:58:08.862162 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7223 22:58:08.862230 ==
7224 22:58:08.865093 [Duty_Offset_Calibration]
7225 22:58:08.868558 B0:2 B1:1 CA:1
7226 22:58:08.868625
7227 22:58:08.871969 [DutyScan_Calibration_Flow] k_type=0
7228 22:58:08.880811
7229 22:58:08.880879 ==CLK 0==
7230 22:58:08.884113 Final CLK duty delay cell = 0
7231 22:58:08.887515 [0] MAX Duty = 5156%(X100), DQS PI = 22
7232 22:58:08.890687 [0] MIN Duty = 4876%(X100), DQS PI = 48
7233 22:58:08.890755 [0] AVG Duty = 5016%(X100)
7234 22:58:08.893626
7235 22:58:08.897155 CH0 CLK Duty spec in!! Max-Min= 280%
7236 22:58:08.900318 [DutyScan_Calibration_Flow] ====Done====
7237 22:58:08.900393
7238 22:58:08.903926 [DutyScan_Calibration_Flow] k_type=1
7239 22:58:08.919911
7240 22:58:08.920015 ==DQS 0 ==
7241 22:58:08.923227 Final DQS duty delay cell = -4
7242 22:58:08.926228 [-4] MAX Duty = 5125%(X100), DQS PI = 24
7243 22:58:08.929825 [-4] MIN Duty = 4657%(X100), DQS PI = 0
7244 22:58:08.932902 [-4] AVG Duty = 4891%(X100)
7245 22:58:08.932977
7246 22:58:08.933039 ==DQS 1 ==
7247 22:58:08.936079 Final DQS duty delay cell = 0
7248 22:58:08.939895 [0] MAX Duty = 5187%(X100), DQS PI = 20
7249 22:58:08.942897 [0] MIN Duty = 5031%(X100), DQS PI = 32
7250 22:58:08.946376 [0] AVG Duty = 5109%(X100)
7251 22:58:08.946451
7252 22:58:08.949880 CH0 DQS 0 Duty spec in!! Max-Min= 468%
7253 22:58:08.949960
7254 22:58:08.953048 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7255 22:58:08.956270 [DutyScan_Calibration_Flow] ====Done====
7256 22:58:08.956347
7257 22:58:08.959248 [DutyScan_Calibration_Flow] k_type=3
7258 22:58:08.976279
7259 22:58:08.976354 ==DQM 0 ==
7260 22:58:08.979687 Final DQM duty delay cell = 0
7261 22:58:08.983162 [0] MAX Duty = 5218%(X100), DQS PI = 34
7262 22:58:08.986210 [0] MIN Duty = 4907%(X100), DQS PI = 56
7263 22:58:08.986283 [0] AVG Duty = 5062%(X100)
7264 22:58:08.989560
7265 22:58:08.989639 ==DQM 1 ==
7266 22:58:08.993096 Final DQM duty delay cell = -4
7267 22:58:08.996581 [-4] MAX Duty = 4969%(X100), DQS PI = 22
7268 22:58:08.999896 [-4] MIN Duty = 4813%(X100), DQS PI = 50
7269 22:58:09.003214 [-4] AVG Duty = 4891%(X100)
7270 22:58:09.003288
7271 22:58:09.006468 CH0 DQM 0 Duty spec in!! Max-Min= 311%
7272 22:58:09.006544
7273 22:58:09.009618 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7274 22:58:09.013148 [DutyScan_Calibration_Flow] ====Done====
7275 22:58:09.013220
7276 22:58:09.016340 [DutyScan_Calibration_Flow] k_type=2
7277 22:58:09.033821
7278 22:58:09.033903 ==DQ 0 ==
7279 22:58:09.037587 Final DQ duty delay cell = 0
7280 22:58:09.040591 [0] MAX Duty = 5062%(X100), DQS PI = 24
7281 22:58:09.043770 [0] MIN Duty = 4907%(X100), DQS PI = 0
7282 22:58:09.043876 [0] AVG Duty = 4984%(X100)
7283 22:58:09.043968
7284 22:58:09.047624 ==DQ 1 ==
7285 22:58:09.050621 Final DQ duty delay cell = 0
7286 22:58:09.054136 [0] MAX Duty = 5125%(X100), DQS PI = 6
7287 22:58:09.057119 [0] MIN Duty = 4907%(X100), DQS PI = 34
7288 22:58:09.057187 [0] AVG Duty = 5016%(X100)
7289 22:58:09.057255
7290 22:58:09.060460 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7291 22:58:09.063897
7292 22:58:09.066994 CH0 DQ 1 Duty spec in!! Max-Min= 218%
7293 22:58:09.070577 [DutyScan_Calibration_Flow] ====Done====
7294 22:58:09.070660 ==
7295 22:58:09.074122 Dram Type= 6, Freq= 0, CH_1, rank 0
7296 22:58:09.077420 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7297 22:58:09.077502 ==
7298 22:58:09.080500 [Duty_Offset_Calibration]
7299 22:58:09.080582 B0:2 B1:0 CA:0
7300 22:58:09.080648
7301 22:58:09.083773 [DutyScan_Calibration_Flow] k_type=0
7302 22:58:09.093405
7303 22:58:09.093487 ==CLK 0==
7304 22:58:09.096437 Final CLK duty delay cell = -4
7305 22:58:09.099997 [-4] MAX Duty = 4969%(X100), DQS PI = 22
7306 22:58:09.103319 [-4] MIN Duty = 4844%(X100), DQS PI = 2
7307 22:58:09.106716 [-4] AVG Duty = 4906%(X100)
7308 22:58:09.106797
7309 22:58:09.109739 CH1 CLK Duty spec in!! Max-Min= 125%
7310 22:58:09.113255 [DutyScan_Calibration_Flow] ====Done====
7311 22:58:09.113336
7312 22:58:09.117858 [DutyScan_Calibration_Flow] k_type=1
7313 22:58:09.132519
7314 22:58:09.132612 ==DQS 0 ==
7315 22:58:09.135734 Final DQS duty delay cell = 0
7316 22:58:09.139032 [0] MAX Duty = 5093%(X100), DQS PI = 22
7317 22:58:09.142680 [0] MIN Duty = 4844%(X100), DQS PI = 44
7318 22:58:09.145747 [0] AVG Duty = 4968%(X100)
7319 22:58:09.145830
7320 22:58:09.145894 ==DQS 1 ==
7321 22:58:09.148975 Final DQS duty delay cell = -4
7322 22:58:09.152139 [-4] MAX Duty = 4969%(X100), DQS PI = 18
7323 22:58:09.155754 [-4] MIN Duty = 4750%(X100), DQS PI = 8
7324 22:58:09.159124 [-4] AVG Duty = 4859%(X100)
7325 22:58:09.159206
7326 22:58:09.162161 CH1 DQS 0 Duty spec in!! Max-Min= 249%
7327 22:58:09.162243
7328 22:58:09.165413 CH1 DQS 1 Duty spec in!! Max-Min= 219%
7329 22:58:09.168814 [DutyScan_Calibration_Flow] ====Done====
7330 22:58:09.168895
7331 22:58:09.172516 [DutyScan_Calibration_Flow] k_type=3
7332 22:58:09.189385
7333 22:58:09.189494 ==DQM 0 ==
7334 22:58:09.193421 Final DQM duty delay cell = 0
7335 22:58:09.196525 [0] MAX Duty = 5187%(X100), DQS PI = 8
7336 22:58:09.199874 [0] MIN Duty = 4969%(X100), DQS PI = 48
7337 22:58:09.199955 [0] AVG Duty = 5078%(X100)
7338 22:58:09.202806
7339 22:58:09.202886 ==DQM 1 ==
7340 22:58:09.206258 Final DQM duty delay cell = 0
7341 22:58:09.209695 [0] MAX Duty = 5093%(X100), DQS PI = 16
7342 22:58:09.212721 [0] MIN Duty = 4907%(X100), DQS PI = 34
7343 22:58:09.216169 [0] AVG Duty = 5000%(X100)
7344 22:58:09.216251
7345 22:58:09.219299 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7346 22:58:09.219381
7347 22:58:09.223045 CH1 DQM 1 Duty spec in!! Max-Min= 186%
7348 22:58:09.226422 [DutyScan_Calibration_Flow] ====Done====
7349 22:58:09.226503
7350 22:58:09.229524 [DutyScan_Calibration_Flow] k_type=2
7351 22:58:09.245777
7352 22:58:09.245861 ==DQ 0 ==
7353 22:58:09.248984 Final DQ duty delay cell = -4
7354 22:58:09.252050 [-4] MAX Duty = 5062%(X100), DQS PI = 10
7355 22:58:09.255546 [-4] MIN Duty = 4876%(X100), DQS PI = 46
7356 22:58:09.259086 [-4] AVG Duty = 4969%(X100)
7357 22:58:09.259167
7358 22:58:09.259231 ==DQ 1 ==
7359 22:58:09.262126 Final DQ duty delay cell = 0
7360 22:58:09.265762 [0] MAX Duty = 5124%(X100), DQS PI = 16
7361 22:58:09.268652 [0] MIN Duty = 4938%(X100), DQS PI = 8
7362 22:58:09.272375 [0] AVG Duty = 5031%(X100)
7363 22:58:09.272460
7364 22:58:09.275292 CH1 DQ 0 Duty spec in!! Max-Min= 186%
7365 22:58:09.275373
7366 22:58:09.278995 CH1 DQ 1 Duty spec in!! Max-Min= 186%
7367 22:58:09.282376 [DutyScan_Calibration_Flow] ====Done====
7368 22:58:09.285457 nWR fixed to 30
7369 22:58:09.289082 [ModeRegInit_LP4] CH0 RK0
7370 22:58:09.289163 [ModeRegInit_LP4] CH0 RK1
7371 22:58:09.292220 [ModeRegInit_LP4] CH1 RK0
7372 22:58:09.295727 [ModeRegInit_LP4] CH1 RK1
7373 22:58:09.295808 match AC timing 5
7374 22:58:09.302279 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7375 22:58:09.305363 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7376 22:58:09.308884 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7377 22:58:09.315655 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7378 22:58:09.318742 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7379 22:58:09.318823 [MiockJmeterHQA]
7380 22:58:09.318887
7381 22:58:09.321979 [DramcMiockJmeter] u1RxGatingPI = 0
7382 22:58:09.325563 0 : 4252, 4027
7383 22:58:09.325685 4 : 4363, 4138
7384 22:58:09.328916 8 : 4252, 4027
7385 22:58:09.328998 12 : 4252, 4027
7386 22:58:09.329064 16 : 4253, 4027
7387 22:58:09.331839 20 : 4253, 4027
7388 22:58:09.331921 24 : 4255, 4029
7389 22:58:09.335200 28 : 4252, 4027
7390 22:58:09.335282 32 : 4253, 4026
7391 22:58:09.338503 36 : 4366, 4140
7392 22:58:09.338622 40 : 4254, 4029
7393 22:58:09.341805 44 : 4255, 4029
7394 22:58:09.341887 48 : 4252, 4027
7395 22:58:09.341952 52 : 4365, 4140
7396 22:58:09.345001 56 : 4253, 4027
7397 22:58:09.345083 60 : 4361, 4138
7398 22:58:09.348688 64 : 4250, 4027
7399 22:58:09.348770 68 : 4250, 4027
7400 22:58:09.352069 72 : 4252, 4027
7401 22:58:09.352152 76 : 4252, 4029
7402 22:58:09.355420 80 : 4250, 4027
7403 22:58:09.355502 84 : 4250, 4026
7404 22:58:09.355568 88 : 4363, 112
7405 22:58:09.358631 92 : 4361, 0
7406 22:58:09.358716 96 : 4252, 0
7407 22:58:09.361987 100 : 4250, 0
7408 22:58:09.362070 104 : 4253, 0
7409 22:58:09.362136 108 : 4363, 0
7410 22:58:09.364989 112 : 4361, 0
7411 22:58:09.365072 116 : 4250, 0
7412 22:58:09.365138 120 : 4253, 0
7413 22:58:09.368296 124 : 4253, 0
7414 22:58:09.368379 128 : 4363, 0
7415 22:58:09.371695 132 : 4253, 0
7416 22:58:09.371779 136 : 4252, 0
7417 22:58:09.371845 140 : 4250, 0
7418 22:58:09.375050 144 : 4253, 0
7419 22:58:09.375133 148 : 4250, 0
7420 22:58:09.378675 152 : 4250, 0
7421 22:58:09.378759 156 : 4253, 0
7422 22:58:09.378825 160 : 4363, 0
7423 22:58:09.381902 164 : 4361, 0
7424 22:58:09.381986 168 : 4250, 0
7425 22:58:09.384786 172 : 4250, 0
7426 22:58:09.384869 176 : 4250, 0
7427 22:58:09.384936 180 : 4361, 0
7428 22:58:09.388770 184 : 4253, 0
7429 22:58:09.388862 188 : 4250, 0
7430 22:58:09.388929 192 : 4250, 0
7431 22:58:09.391663 196 : 4253, 0
7432 22:58:09.391746 200 : 4250, 0
7433 22:58:09.395278 204 : 4250, 1278
7434 22:58:09.395361 208 : 4250, 4013
7435 22:58:09.398221 212 : 4250, 4027
7436 22:58:09.398305 216 : 4250, 4027
7437 22:58:09.401817 220 : 4250, 4027
7438 22:58:09.401900 224 : 4250, 4026
7439 22:58:09.401966 228 : 4250, 4027
7440 22:58:09.404820 232 : 4252, 4029
7441 22:58:09.404913 236 : 4250, 4027
7442 22:58:09.408302 240 : 4360, 4137
7443 22:58:09.408386 244 : 4361, 4138
7444 22:58:09.411732 248 : 4250, 4027
7445 22:58:09.411816 252 : 4363, 4140
7446 22:58:09.414795 256 : 4250, 4027
7447 22:58:09.414878 260 : 4250, 4026
7448 22:58:09.418368 264 : 4250, 4027
7449 22:58:09.418451 268 : 4252, 4029
7450 22:58:09.421414 272 : 4250, 4027
7451 22:58:09.421532 276 : 4250, 4026
7452 22:58:09.424977 280 : 4250, 4027
7453 22:58:09.425062 284 : 4252, 4029
7454 22:58:09.428243 288 : 4250, 4027
7455 22:58:09.428325 292 : 4361, 4137
7456 22:58:09.428391 296 : 4361, 4137
7457 22:58:09.431763 300 : 4250, 4027
7458 22:58:09.431845 304 : 4363, 4140
7459 22:58:09.434728 308 : 4250, 3912
7460 22:58:09.434810 312 : 4250, 1987
7461 22:58:09.434874
7462 22:58:09.438109 MIOCK jitter meter ch=0
7463 22:58:09.438189
7464 22:58:09.441615 1T = (312-88) = 224 dly cells
7465 22:58:09.447877 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7466 22:58:09.447986 ==
7467 22:58:09.451229 Dram Type= 6, Freq= 0, CH_0, rank 0
7468 22:58:09.454566 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7469 22:58:09.454657 ==
7470 22:58:09.461044 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7471 22:58:09.464342 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7472 22:58:09.467698 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7473 22:58:09.474725 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7474 22:58:09.483247 [CA 0] Center 42 (12~73) winsize 62
7475 22:58:09.486677 [CA 1] Center 42 (12~73) winsize 62
7476 22:58:09.489849 [CA 2] Center 38 (8~68) winsize 61
7477 22:58:09.493176 [CA 3] Center 37 (8~67) winsize 60
7478 22:58:09.496574 [CA 4] Center 36 (6~66) winsize 61
7479 22:58:09.500282 [CA 5] Center 35 (6~64) winsize 59
7480 22:58:09.500364
7481 22:58:09.503338 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7482 22:58:09.503422
7483 22:58:09.506874 [CATrainingPosCal] consider 1 rank data
7484 22:58:09.509946 u2DelayCellTimex100 = 290/100 ps
7485 22:58:09.513682 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7486 22:58:09.520161 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7487 22:58:09.523716 CA2 delay=38 (8~68),Diff = 3 PI (10 cell)
7488 22:58:09.526542 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7489 22:58:09.530049 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7490 22:58:09.533162 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7491 22:58:09.533245
7492 22:58:09.536703 CA PerBit enable=1, Macro0, CA PI delay=35
7493 22:58:09.536785
7494 22:58:09.540056 [CBTSetCACLKResult] CA Dly = 35
7495 22:58:09.540139 CS Dly: 9 (0~40)
7496 22:58:09.546537 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7497 22:58:09.550083 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7498 22:58:09.550158 ==
7499 22:58:09.553515 Dram Type= 6, Freq= 0, CH_0, rank 1
7500 22:58:09.556377 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7501 22:58:09.556450 ==
7502 22:58:09.562973 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7503 22:58:09.566657 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7504 22:58:09.572900 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7505 22:58:09.576134 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7506 22:58:09.586574 [CA 0] Center 42 (12~73) winsize 62
7507 22:58:09.590175 [CA 1] Center 42 (12~73) winsize 62
7508 22:58:09.593574 [CA 2] Center 38 (8~68) winsize 61
7509 22:58:09.596877 [CA 3] Center 38 (8~68) winsize 61
7510 22:58:09.600179 [CA 4] Center 36 (6~66) winsize 61
7511 22:58:09.603483 [CA 5] Center 35 (5~65) winsize 61
7512 22:58:09.603554
7513 22:58:09.606804 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7514 22:58:09.606874
7515 22:58:09.609784 [CATrainingPosCal] consider 2 rank data
7516 22:58:09.613426 u2DelayCellTimex100 = 290/100 ps
7517 22:58:09.616281 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7518 22:58:09.623286 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7519 22:58:09.626622 CA2 delay=38 (8~68),Diff = 3 PI (10 cell)
7520 22:58:09.629562 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7521 22:58:09.632940 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7522 22:58:09.636268 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7523 22:58:09.636371
7524 22:58:09.639933 CA PerBit enable=1, Macro0, CA PI delay=35
7525 22:58:09.640005
7526 22:58:09.643078 [CBTSetCACLKResult] CA Dly = 35
7527 22:58:09.646241 CS Dly: 9 (0~41)
7528 22:58:09.649364 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7529 22:58:09.653387 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7530 22:58:09.653496
7531 22:58:09.656483 ----->DramcWriteLeveling(PI) begin...
7532 22:58:09.656588 ==
7533 22:58:09.659357 Dram Type= 6, Freq= 0, CH_0, rank 0
7534 22:58:09.662688 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7535 22:58:09.666072 ==
7536 22:58:09.666170 Write leveling (Byte 0): 35 => 35
7537 22:58:09.669529 Write leveling (Byte 1): 30 => 30
7538 22:58:09.673127 DramcWriteLeveling(PI) end<-----
7539 22:58:09.673197
7540 22:58:09.673257 ==
7541 22:58:09.676107 Dram Type= 6, Freq= 0, CH_0, rank 0
7542 22:58:09.683063 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7543 22:58:09.683146 ==
7544 22:58:09.686111 [Gating] SW mode calibration
7545 22:58:09.692820 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7546 22:58:09.696446 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7547 22:58:09.703121 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7548 22:58:09.706380 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7549 22:58:09.709741 1 4 8 | B1->B0 | 2323 2424 | 0 1 | (0 0) (0 0)
7550 22:58:09.713156 1 4 12 | B1->B0 | 2323 3535 | 0 0 | (0 0) (0 0)
7551 22:58:09.719410 1 4 16 | B1->B0 | 2424 3838 | 0 0 | (0 0) (0 0)
7552 22:58:09.722957 1 4 20 | B1->B0 | 3333 3737 | 1 0 | (1 1) (1 1)
7553 22:58:09.726622 1 4 24 | B1->B0 | 3434 3737 | 1 1 | (1 1) (1 1)
7554 22:58:09.732889 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7555 22:58:09.736559 1 5 0 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7556 22:58:09.739573 1 5 4 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7557 22:58:09.746267 1 5 8 | B1->B0 | 3434 d0d | 1 1 | (1 1) (1 1)
7558 22:58:09.749705 1 5 12 | B1->B0 | 3434 2828 | 1 0 | (1 1) (0 0)
7559 22:58:09.753228 1 5 16 | B1->B0 | 3434 2626 | 1 0 | (1 0) (1 0)
7560 22:58:09.759403 1 5 20 | B1->B0 | 2727 2625 | 0 1 | (1 0) (0 0)
7561 22:58:09.762621 1 5 24 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
7562 22:58:09.766173 1 5 28 | B1->B0 | 2323 2625 | 0 1 | (0 0) (1 1)
7563 22:58:09.773160 1 6 0 | B1->B0 | 2323 2726 | 0 1 | (0 0) (0 0)
7564 22:58:09.776570 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7565 22:58:09.779481 1 6 8 | B1->B0 | 2323 3a3a | 0 1 | (0 0) (0 0)
7566 22:58:09.786383 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7567 22:58:09.789694 1 6 16 | B1->B0 | 2626 4646 | 0 0 | (0 0) (0 0)
7568 22:58:09.792801 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7569 22:58:09.799687 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7570 22:58:09.803304 1 6 28 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
7571 22:58:09.805990 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7572 22:58:09.809509 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7573 22:58:09.816141 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7574 22:58:09.819218 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7575 22:58:09.822686 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7576 22:58:09.829674 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7577 22:58:09.832540 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7578 22:58:09.836036 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7579 22:58:09.842593 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7580 22:58:09.846557 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7581 22:58:09.849356 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7582 22:58:09.856210 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7583 22:58:09.859170 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7584 22:58:09.862712 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7585 22:58:09.869110 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7586 22:58:09.872985 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7587 22:58:09.875999 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7588 22:58:09.882485 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7589 22:58:09.885788 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7590 22:58:09.889270 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7591 22:58:09.895788 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7592 22:58:09.895876 Total UI for P1: 0, mck2ui 16
7593 22:58:09.902503 best dqsien dly found for B0: ( 1, 9, 10)
7594 22:58:09.906024 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7595 22:58:09.909128 Total UI for P1: 0, mck2ui 16
7596 22:58:09.912367 best dqsien dly found for B1: ( 1, 9, 16)
7597 22:58:09.915863 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7598 22:58:09.919297 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
7599 22:58:09.919379
7600 22:58:09.922635 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7601 22:58:09.925700 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
7602 22:58:09.929275 [Gating] SW calibration Done
7603 22:58:09.929358 ==
7604 22:58:09.932160 Dram Type= 6, Freq= 0, CH_0, rank 0
7605 22:58:09.935549 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7606 22:58:09.938948 ==
7607 22:58:09.939031 RX Vref Scan: 0
7608 22:58:09.939096
7609 22:58:09.942008 RX Vref 0 -> 0, step: 1
7610 22:58:09.942091
7611 22:58:09.942156 RX Delay 0 -> 252, step: 8
7612 22:58:09.949172 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
7613 22:58:09.952353 iDelay=200, Bit 1, Center 143 (88 ~ 199) 112
7614 22:58:09.955354 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7615 22:58:09.958783 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
7616 22:58:09.962150 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7617 22:58:09.968625 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7618 22:58:09.972024 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7619 22:58:09.975767 iDelay=200, Bit 7, Center 143 (96 ~ 191) 96
7620 22:58:09.979125 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
7621 22:58:09.982174 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
7622 22:58:09.988950 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
7623 22:58:09.992094 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7624 22:58:09.995327 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
7625 22:58:09.998463 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
7626 22:58:10.005192 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7627 22:58:10.008671 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7628 22:58:10.008755 ==
7629 22:58:10.011696 Dram Type= 6, Freq= 0, CH_0, rank 0
7630 22:58:10.015191 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7631 22:58:10.015313 ==
7632 22:58:10.015378 DQS Delay:
7633 22:58:10.018566 DQS0 = 0, DQS1 = 0
7634 22:58:10.018648 DQM Delay:
7635 22:58:10.021913 DQM0 = 136, DQM1 = 130
7636 22:58:10.021997 DQ Delay:
7637 22:58:10.025407 DQ0 =135, DQ1 =143, DQ2 =131, DQ3 =135
7638 22:58:10.028347 DQ4 =139, DQ5 =123, DQ6 =143, DQ7 =143
7639 22:58:10.031622 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =123
7640 22:58:10.038175 DQ12 =135, DQ13 =139, DQ14 =139, DQ15 =135
7641 22:58:10.038258
7642 22:58:10.038322
7643 22:58:10.038386 ==
7644 22:58:10.041445 Dram Type= 6, Freq= 0, CH_0, rank 0
7645 22:58:10.044856 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7646 22:58:10.044941 ==
7647 22:58:10.045008
7648 22:58:10.045069
7649 22:58:10.048482 TX Vref Scan disable
7650 22:58:10.048566 == TX Byte 0 ==
7651 22:58:10.054774 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7652 22:58:10.058215 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7653 22:58:10.058299 == TX Byte 1 ==
7654 22:58:10.064695 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7655 22:58:10.068197 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7656 22:58:10.068280 ==
7657 22:58:10.071735 Dram Type= 6, Freq= 0, CH_0, rank 0
7658 22:58:10.074644 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7659 22:58:10.074728 ==
7660 22:58:10.088922
7661 22:58:10.092024 TX Vref early break, caculate TX vref
7662 22:58:10.095595 TX Vref=16, minBit 0, minWin=23, winSum=379
7663 22:58:10.098776 TX Vref=18, minBit 7, minWin=23, winSum=386
7664 22:58:10.102094 TX Vref=20, minBit 7, minWin=23, winSum=400
7665 22:58:10.105310 TX Vref=22, minBit 0, minWin=25, winSum=413
7666 22:58:10.108906 TX Vref=24, minBit 8, minWin=25, winSum=419
7667 22:58:10.115764 TX Vref=26, minBit 0, minWin=25, winSum=425
7668 22:58:10.118794 TX Vref=28, minBit 1, minWin=25, winSum=426
7669 22:58:10.122241 TX Vref=30, minBit 6, minWin=25, winSum=419
7670 22:58:10.125737 TX Vref=32, minBit 0, minWin=24, winSum=405
7671 22:58:10.128587 TX Vref=34, minBit 1, minWin=23, winSum=395
7672 22:58:10.135408 [TxChooseVref] Worse bit 1, Min win 25, Win sum 426, Final Vref 28
7673 22:58:10.135491
7674 22:58:10.138795 Final TX Range 0 Vref 28
7675 22:58:10.138878
7676 22:58:10.138944 ==
7677 22:58:10.142172 Dram Type= 6, Freq= 0, CH_0, rank 0
7678 22:58:10.145144 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7679 22:58:10.145228 ==
7680 22:58:10.145293
7681 22:58:10.145353
7682 22:58:10.148765 TX Vref Scan disable
7683 22:58:10.155361 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7684 22:58:10.155444 == TX Byte 0 ==
7685 22:58:10.158867 u2DelayCellOfst[0]=10 cells (3 PI)
7686 22:58:10.162365 u2DelayCellOfst[1]=16 cells (5 PI)
7687 22:58:10.165195 u2DelayCellOfst[2]=10 cells (3 PI)
7688 22:58:10.168521 u2DelayCellOfst[3]=10 cells (3 PI)
7689 22:58:10.172048 u2DelayCellOfst[4]=6 cells (2 PI)
7690 22:58:10.175068 u2DelayCellOfst[5]=0 cells (0 PI)
7691 22:58:10.178863 u2DelayCellOfst[6]=16 cells (5 PI)
7692 22:58:10.178945 u2DelayCellOfst[7]=16 cells (5 PI)
7693 22:58:10.185155 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7694 22:58:10.188489 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7695 22:58:10.188571 == TX Byte 1 ==
7696 22:58:10.192095 u2DelayCellOfst[8]=0 cells (0 PI)
7697 22:58:10.195515 u2DelayCellOfst[9]=0 cells (0 PI)
7698 22:58:10.198697 u2DelayCellOfst[10]=6 cells (2 PI)
7699 22:58:10.202039 u2DelayCellOfst[11]=3 cells (1 PI)
7700 22:58:10.204935 u2DelayCellOfst[12]=10 cells (3 PI)
7701 22:58:10.208477 u2DelayCellOfst[13]=10 cells (3 PI)
7702 22:58:10.211827 u2DelayCellOfst[14]=16 cells (5 PI)
7703 22:58:10.215207 u2DelayCellOfst[15]=10 cells (3 PI)
7704 22:58:10.218587 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7705 22:58:10.225401 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7706 22:58:10.225533 DramC Write-DBI on
7707 22:58:10.225685 ==
7708 22:58:10.228432 Dram Type= 6, Freq= 0, CH_0, rank 0
7709 22:58:10.232027 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7710 22:58:10.232110 ==
7711 22:58:10.235371
7712 22:58:10.235453
7713 22:58:10.235518 TX Vref Scan disable
7714 22:58:10.238696 == TX Byte 0 ==
7715 22:58:10.241921 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7716 22:58:10.245472 == TX Byte 1 ==
7717 22:58:10.248659 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
7718 22:58:10.248743 DramC Write-DBI off
7719 22:58:10.251971
7720 22:58:10.252054 [DATLAT]
7721 22:58:10.252120 Freq=1600, CH0 RK0
7722 22:58:10.252181
7723 22:58:10.255218 DATLAT Default: 0xf
7724 22:58:10.255300 0, 0xFFFF, sum = 0
7725 22:58:10.258725 1, 0xFFFF, sum = 0
7726 22:58:10.258849 2, 0xFFFF, sum = 0
7727 22:58:10.261702 3, 0xFFFF, sum = 0
7728 22:58:10.265026 4, 0xFFFF, sum = 0
7729 22:58:10.265110 5, 0xFFFF, sum = 0
7730 22:58:10.268614 6, 0xFFFF, sum = 0
7731 22:58:10.268698 7, 0xFFFF, sum = 0
7732 22:58:10.271600 8, 0xFFFF, sum = 0
7733 22:58:10.271683 9, 0xFFFF, sum = 0
7734 22:58:10.275119 10, 0xFFFF, sum = 0
7735 22:58:10.275203 11, 0xFFFF, sum = 0
7736 22:58:10.278654 12, 0xFFFF, sum = 0
7737 22:58:10.278738 13, 0xFFFF, sum = 0
7738 22:58:10.281620 14, 0x0, sum = 1
7739 22:58:10.281718 15, 0x0, sum = 2
7740 22:58:10.285012 16, 0x0, sum = 3
7741 22:58:10.285096 17, 0x0, sum = 4
7742 22:58:10.287955 best_step = 15
7743 22:58:10.288037
7744 22:58:10.288102 ==
7745 22:58:10.291438 Dram Type= 6, Freq= 0, CH_0, rank 0
7746 22:58:10.294863 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7747 22:58:10.294946 ==
7748 22:58:10.298518 RX Vref Scan: 1
7749 22:58:10.298600
7750 22:58:10.298666 Set Vref Range= 24 -> 127
7751 22:58:10.298727
7752 22:58:10.301563 RX Vref 24 -> 127, step: 1
7753 22:58:10.301653
7754 22:58:10.304583 RX Delay 27 -> 252, step: 4
7755 22:58:10.304664
7756 22:58:10.308145 Set Vref, RX VrefLevel [Byte0]: 24
7757 22:58:10.311543 [Byte1]: 24
7758 22:58:10.311626
7759 22:58:10.314407 Set Vref, RX VrefLevel [Byte0]: 25
7760 22:58:10.317864 [Byte1]: 25
7761 22:58:10.317946
7762 22:58:10.321139 Set Vref, RX VrefLevel [Byte0]: 26
7763 22:58:10.324679 [Byte1]: 26
7764 22:58:10.328631
7765 22:58:10.328713 Set Vref, RX VrefLevel [Byte0]: 27
7766 22:58:10.331718 [Byte1]: 27
7767 22:58:10.336377
7768 22:58:10.336461 Set Vref, RX VrefLevel [Byte0]: 28
7769 22:58:10.339275 [Byte1]: 28
7770 22:58:10.343937
7771 22:58:10.344025 Set Vref, RX VrefLevel [Byte0]: 29
7772 22:58:10.346865 [Byte1]: 29
7773 22:58:10.351382
7774 22:58:10.351465 Set Vref, RX VrefLevel [Byte0]: 30
7775 22:58:10.354252 [Byte1]: 30
7776 22:58:10.358747
7777 22:58:10.358866 Set Vref, RX VrefLevel [Byte0]: 31
7778 22:58:10.361820 [Byte1]: 31
7779 22:58:10.366228
7780 22:58:10.366311 Set Vref, RX VrefLevel [Byte0]: 32
7781 22:58:10.369748 [Byte1]: 32
7782 22:58:10.373808
7783 22:58:10.373891 Set Vref, RX VrefLevel [Byte0]: 33
7784 22:58:10.377064 [Byte1]: 33
7785 22:58:10.381218
7786 22:58:10.381301 Set Vref, RX VrefLevel [Byte0]: 34
7787 22:58:10.384335 [Byte1]: 34
7788 22:58:10.388977
7789 22:58:10.389060 Set Vref, RX VrefLevel [Byte0]: 35
7790 22:58:10.391990 [Byte1]: 35
7791 22:58:10.396425
7792 22:58:10.396508 Set Vref, RX VrefLevel [Byte0]: 36
7793 22:58:10.399377 [Byte1]: 36
7794 22:58:10.404034
7795 22:58:10.404116 Set Vref, RX VrefLevel [Byte0]: 37
7796 22:58:10.406997 [Byte1]: 37
7797 22:58:10.411164
7798 22:58:10.411246 Set Vref, RX VrefLevel [Byte0]: 38
7799 22:58:10.414679 [Byte1]: 38
7800 22:58:10.419134
7801 22:58:10.419217 Set Vref, RX VrefLevel [Byte0]: 39
7802 22:58:10.421971 [Byte1]: 39
7803 22:58:10.426610
7804 22:58:10.426693 Set Vref, RX VrefLevel [Byte0]: 40
7805 22:58:10.429480 [Byte1]: 40
7806 22:58:10.434202
7807 22:58:10.434285 Set Vref, RX VrefLevel [Byte0]: 41
7808 22:58:10.437614 [Byte1]: 41
7809 22:58:10.441296
7810 22:58:10.441377 Set Vref, RX VrefLevel [Byte0]: 42
7811 22:58:10.444564 [Byte1]: 42
7812 22:58:10.449272
7813 22:58:10.449355 Set Vref, RX VrefLevel [Byte0]: 43
7814 22:58:10.452212 [Byte1]: 43
7815 22:58:10.456360
7816 22:58:10.456443 Set Vref, RX VrefLevel [Byte0]: 44
7817 22:58:10.459796 [Byte1]: 44
7818 22:58:10.463912
7819 22:58:10.463995 Set Vref, RX VrefLevel [Byte0]: 45
7820 22:58:10.467540 [Byte1]: 45
7821 22:58:10.471631
7822 22:58:10.471713 Set Vref, RX VrefLevel [Byte0]: 46
7823 22:58:10.474884 [Byte1]: 46
7824 22:58:10.479296
7825 22:58:10.479379 Set Vref, RX VrefLevel [Byte0]: 47
7826 22:58:10.482507 [Byte1]: 47
7827 22:58:10.486675
7828 22:58:10.486759 Set Vref, RX VrefLevel [Byte0]: 48
7829 22:58:10.489975 [Byte1]: 48
7830 22:58:10.494213
7831 22:58:10.494294 Set Vref, RX VrefLevel [Byte0]: 49
7832 22:58:10.497584 [Byte1]: 49
7833 22:58:10.501645
7834 22:58:10.501730 Set Vref, RX VrefLevel [Byte0]: 50
7835 22:58:10.505063 [Byte1]: 50
7836 22:58:10.509454
7837 22:58:10.509535 Set Vref, RX VrefLevel [Byte0]: 51
7838 22:58:10.513105 [Byte1]: 51
7839 22:58:10.516549
7840 22:58:10.516632 Set Vref, RX VrefLevel [Byte0]: 52
7841 22:58:10.520110 [Byte1]: 52
7842 22:58:10.524366
7843 22:58:10.524448 Set Vref, RX VrefLevel [Byte0]: 53
7844 22:58:10.527763 [Byte1]: 53
7845 22:58:10.531749
7846 22:58:10.531831 Set Vref, RX VrefLevel [Byte0]: 54
7847 22:58:10.535563 [Byte1]: 54
7848 22:58:10.539525
7849 22:58:10.539607 Set Vref, RX VrefLevel [Byte0]: 55
7850 22:58:10.543030 [Byte1]: 55
7851 22:58:10.546953
7852 22:58:10.547073 Set Vref, RX VrefLevel [Byte0]: 56
7853 22:58:10.550373 [Byte1]: 56
7854 22:58:10.554793
7855 22:58:10.554876 Set Vref, RX VrefLevel [Byte0]: 57
7856 22:58:10.557838 [Byte1]: 57
7857 22:58:10.561995
7858 22:58:10.562077 Set Vref, RX VrefLevel [Byte0]: 58
7859 22:58:10.565462 [Byte1]: 58
7860 22:58:10.569567
7861 22:58:10.569659 Set Vref, RX VrefLevel [Byte0]: 59
7862 22:58:10.573045 [Byte1]: 59
7863 22:58:10.576843
7864 22:58:10.576925 Set Vref, RX VrefLevel [Byte0]: 60
7865 22:58:10.580107 [Byte1]: 60
7866 22:58:10.584801
7867 22:58:10.584884 Set Vref, RX VrefLevel [Byte0]: 61
7868 22:58:10.588022 [Byte1]: 61
7869 22:58:10.592273
7870 22:58:10.592355 Set Vref, RX VrefLevel [Byte0]: 62
7871 22:58:10.595438 [Byte1]: 62
7872 22:58:10.599924
7873 22:58:10.600006 Set Vref, RX VrefLevel [Byte0]: 63
7874 22:58:10.603100 [Byte1]: 63
7875 22:58:10.607080
7876 22:58:10.607162 Set Vref, RX VrefLevel [Byte0]: 64
7877 22:58:10.611036 [Byte1]: 64
7878 22:58:10.615028
7879 22:58:10.615109 Set Vref, RX VrefLevel [Byte0]: 65
7880 22:58:10.618152 [Byte1]: 65
7881 22:58:10.622388
7882 22:58:10.622470 Set Vref, RX VrefLevel [Byte0]: 66
7883 22:58:10.625513 [Byte1]: 66
7884 22:58:10.629971
7885 22:58:10.630053 Set Vref, RX VrefLevel [Byte0]: 67
7886 22:58:10.633287 [Byte1]: 67
7887 22:58:10.637080
7888 22:58:10.637162 Set Vref, RX VrefLevel [Byte0]: 68
7889 22:58:10.640322 [Byte1]: 68
7890 22:58:10.645100
7891 22:58:10.645185 Set Vref, RX VrefLevel [Byte0]: 69
7892 22:58:10.648640 [Byte1]: 69
7893 22:58:10.652171
7894 22:58:10.652254 Set Vref, RX VrefLevel [Byte0]: 70
7895 22:58:10.655568 [Byte1]: 70
7896 22:58:10.660125
7897 22:58:10.660211 Set Vref, RX VrefLevel [Byte0]: 71
7898 22:58:10.663429 [Byte1]: 71
7899 22:58:10.667537
7900 22:58:10.667619 Set Vref, RX VrefLevel [Byte0]: 72
7901 22:58:10.671032 [Byte1]: 72
7902 22:58:10.675135
7903 22:58:10.675218 Set Vref, RX VrefLevel [Byte0]: 73
7904 22:58:10.678684 [Byte1]: 73
7905 22:58:10.682805
7906 22:58:10.682887 Final RX Vref Byte 0 = 57 to rank0
7907 22:58:10.686227 Final RX Vref Byte 1 = 61 to rank0
7908 22:58:10.688998 Final RX Vref Byte 0 = 57 to rank1
7909 22:58:10.692789 Final RX Vref Byte 1 = 61 to rank1==
7910 22:58:10.695668 Dram Type= 6, Freq= 0, CH_0, rank 0
7911 22:58:10.702397 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7912 22:58:10.702480 ==
7913 22:58:10.702546 DQS Delay:
7914 22:58:10.702607 DQS0 = 0, DQS1 = 0
7915 22:58:10.705806 DQM Delay:
7916 22:58:10.705888 DQM0 = 134, DQM1 = 127
7917 22:58:10.709538 DQ Delay:
7918 22:58:10.712794 DQ0 =134, DQ1 =138, DQ2 =134, DQ3 =130
7919 22:58:10.716005 DQ4 =132, DQ5 =124, DQ6 =142, DQ7 =138
7920 22:58:10.719144 DQ8 =116, DQ9 =118, DQ10 =130, DQ11 =120
7921 22:58:10.722473 DQ12 =132, DQ13 =132, DQ14 =138, DQ15 =136
7922 22:58:10.722557
7923 22:58:10.722621
7924 22:58:10.722681
7925 22:58:10.725597 [DramC_TX_OE_Calibration] TA2
7926 22:58:10.729343 Original DQ_B0 (3 6) =30, OEN = 27
7927 22:58:10.732669 Original DQ_B1 (3 6) =30, OEN = 27
7928 22:58:10.735577 24, 0x0, End_B0=24 End_B1=24
7929 22:58:10.735661 25, 0x0, End_B0=25 End_B1=25
7930 22:58:10.739023 26, 0x0, End_B0=26 End_B1=26
7931 22:58:10.742232 27, 0x0, End_B0=27 End_B1=27
7932 22:58:10.745635 28, 0x0, End_B0=28 End_B1=28
7933 22:58:10.745730 29, 0x0, End_B0=29 End_B1=29
7934 22:58:10.748870 30, 0x0, End_B0=30 End_B1=30
7935 22:58:10.752450 31, 0x4141, End_B0=30 End_B1=30
7936 22:58:10.755910 Byte0 end_step=30 best_step=27
7937 22:58:10.758851 Byte1 end_step=30 best_step=27
7938 22:58:10.762206 Byte0 TX OE(2T, 0.5T) = (3, 3)
7939 22:58:10.762288 Byte1 TX OE(2T, 0.5T) = (3, 3)
7940 22:58:10.765632
7941 22:58:10.765730
7942 22:58:10.772387 [DQSOSCAuto] RK0, (LSB)MR18= 0x241f, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 391 ps
7943 22:58:10.775376 CH0 RK0: MR19=303, MR18=241F
7944 22:58:10.782647 CH0_RK0: MR19=0x303, MR18=0x241F, DQSOSC=391, MR23=63, INC=24, DEC=16
7945 22:58:10.782731
7946 22:58:10.785656 ----->DramcWriteLeveling(PI) begin...
7947 22:58:10.785741 ==
7948 22:58:10.789110 Dram Type= 6, Freq= 0, CH_0, rank 1
7949 22:58:10.792671 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7950 22:58:10.792753 ==
7951 22:58:10.795535 Write leveling (Byte 0): 35 => 35
7952 22:58:10.799022 Write leveling (Byte 1): 29 => 29
7953 22:58:10.802605 DramcWriteLeveling(PI) end<-----
7954 22:58:10.802687
7955 22:58:10.802753 ==
7956 22:58:10.805300 Dram Type= 6, Freq= 0, CH_0, rank 1
7957 22:58:10.809094 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7958 22:58:10.809177 ==
7959 22:58:10.811998 [Gating] SW mode calibration
7960 22:58:10.818905 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7961 22:58:10.825245 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7962 22:58:10.828895 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7963 22:58:10.831948 1 4 4 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
7964 22:58:10.838742 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7965 22:58:10.842084 1 4 12 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7966 22:58:10.845560 1 4 16 | B1->B0 | 3232 3737 | 0 0 | (0 0) (0 0)
7967 22:58:10.851742 1 4 20 | B1->B0 | 3434 3737 | 1 0 | (1 1) (0 0)
7968 22:58:10.855330 1 4 24 | B1->B0 | 3434 3737 | 1 0 | (1 1) (0 0)
7969 22:58:10.858420 1 4 28 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
7970 22:58:10.865550 1 5 0 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
7971 22:58:10.868663 1 5 4 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7972 22:58:10.872179 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7973 22:58:10.878939 1 5 12 | B1->B0 | 3434 3030 | 1 1 | (1 0) (0 1)
7974 22:58:10.881819 1 5 16 | B1->B0 | 3030 2a29 | 0 1 | (1 1) (0 0)
7975 22:58:10.885397 1 5 20 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
7976 22:58:10.891919 1 5 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7977 22:58:10.895353 1 5 28 | B1->B0 | 2323 2727 | 0 0 | (0 0) (1 1)
7978 22:58:10.898951 1 6 0 | B1->B0 | 2323 2a29 | 0 1 | (0 0) (0 0)
7979 22:58:10.905199 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7980 22:58:10.908650 1 6 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7981 22:58:10.911663 1 6 12 | B1->B0 | 2626 3b3b | 0 1 | (0 0) (0 0)
7982 22:58:10.918512 1 6 16 | B1->B0 | 3d3d 4645 | 0 1 | (0 0) (0 0)
7983 22:58:10.921814 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7984 22:58:10.925238 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7985 22:58:10.928240 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7986 22:58:10.935416 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7987 22:58:10.938527 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7988 22:58:10.941827 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7989 22:58:10.948190 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7990 22:58:10.951611 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7991 22:58:10.955315 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7992 22:58:10.961778 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7993 22:58:10.965414 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7994 22:58:10.968529 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7995 22:58:10.975178 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7996 22:58:10.978741 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7997 22:58:10.981992 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7998 22:58:10.988566 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7999 22:58:10.992199 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8000 22:58:10.995007 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8001 22:58:11.001539 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8002 22:58:11.004928 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8003 22:58:11.008549 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8004 22:58:11.014826 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8005 22:58:11.018400 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8006 22:58:11.021937 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8007 22:58:11.028222 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8008 22:58:11.028297 Total UI for P1: 0, mck2ui 16
8009 22:58:11.031978 best dqsien dly found for B0: ( 1, 9, 12)
8010 22:58:11.034786 Total UI for P1: 0, mck2ui 16
8011 22:58:11.038395 best dqsien dly found for B1: ( 1, 9, 16)
8012 22:58:11.045012 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8013 22:58:11.048370 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8014 22:58:11.048451
8015 22:58:11.051288 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8016 22:58:11.054604 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8017 22:58:11.058119 [Gating] SW calibration Done
8018 22:58:11.058194 ==
8019 22:58:11.061140 Dram Type= 6, Freq= 0, CH_0, rank 1
8020 22:58:11.064569 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8021 22:58:11.064643 ==
8022 22:58:11.068193 RX Vref Scan: 0
8023 22:58:11.068271
8024 22:58:11.068335 RX Vref 0 -> 0, step: 1
8025 22:58:11.068404
8026 22:58:11.071539 RX Delay 0 -> 252, step: 8
8027 22:58:11.074543 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8028 22:58:11.081005 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8029 22:58:11.084806 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8030 22:58:11.087901 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8031 22:58:11.090989 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8032 22:58:11.094446 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8033 22:58:11.101402 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8034 22:58:11.104789 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8035 22:58:11.107854 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8036 22:58:11.110967 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8037 22:58:11.114585 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8038 22:58:11.121455 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8039 22:58:11.124507 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8040 22:58:11.127963 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8041 22:58:11.130871 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8042 22:58:11.134111 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8043 22:58:11.137665 ==
8044 22:58:11.140504 Dram Type= 6, Freq= 0, CH_0, rank 1
8045 22:58:11.144269 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8046 22:58:11.144360 ==
8047 22:58:11.144423 DQS Delay:
8048 22:58:11.147644 DQS0 = 0, DQS1 = 0
8049 22:58:11.147726 DQM Delay:
8050 22:58:11.150599 DQM0 = 137, DQM1 = 128
8051 22:58:11.150677 DQ Delay:
8052 22:58:11.154348 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
8053 22:58:11.157200 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8054 22:58:11.160589 DQ8 =119, DQ9 =119, DQ10 =127, DQ11 =119
8055 22:58:11.163960 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8056 22:58:11.164039
8057 22:58:11.164101
8058 22:58:11.164160 ==
8059 22:58:11.167331 Dram Type= 6, Freq= 0, CH_0, rank 1
8060 22:58:11.173505 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8061 22:58:11.173613 ==
8062 22:58:11.173693
8063 22:58:11.173752
8064 22:58:11.177167 TX Vref Scan disable
8065 22:58:11.177242 == TX Byte 0 ==
8066 22:58:11.180472 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8067 22:58:11.186937 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8068 22:58:11.187023 == TX Byte 1 ==
8069 22:58:11.190060 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8070 22:58:11.197108 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8071 22:58:11.197185 ==
8072 22:58:11.200176 Dram Type= 6, Freq= 0, CH_0, rank 1
8073 22:58:11.203503 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8074 22:58:11.203583 ==
8075 22:58:11.216145
8076 22:58:11.219387 TX Vref early break, caculate TX vref
8077 22:58:11.222781 TX Vref=16, minBit 1, minWin=23, winSum=386
8078 22:58:11.226176 TX Vref=18, minBit 1, minWin=22, winSum=397
8079 22:58:11.229094 TX Vref=20, minBit 1, minWin=24, winSum=405
8080 22:58:11.232747 TX Vref=22, minBit 1, minWin=24, winSum=412
8081 22:58:11.235655 TX Vref=24, minBit 1, minWin=25, winSum=425
8082 22:58:11.242473 TX Vref=26, minBit 1, minWin=25, winSum=429
8083 22:58:11.246075 TX Vref=28, minBit 3, minWin=24, winSum=424
8084 22:58:11.249631 TX Vref=30, minBit 0, minWin=25, winSum=419
8085 22:58:11.252562 TX Vref=32, minBit 4, minWin=24, winSum=406
8086 22:58:11.259139 [TxChooseVref] Worse bit 1, Min win 25, Win sum 429, Final Vref 26
8087 22:58:11.259253
8088 22:58:11.262561 Final TX Range 0 Vref 26
8089 22:58:11.262650
8090 22:58:11.262716 ==
8091 22:58:11.265870 Dram Type= 6, Freq= 0, CH_0, rank 1
8092 22:58:11.269393 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8093 22:58:11.269477 ==
8094 22:58:11.269543
8095 22:58:11.269668
8096 22:58:11.272239 TX Vref Scan disable
8097 22:58:11.275713 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8098 22:58:11.279524 == TX Byte 0 ==
8099 22:58:11.282725 u2DelayCellOfst[0]=10 cells (3 PI)
8100 22:58:11.285876 u2DelayCellOfst[1]=16 cells (5 PI)
8101 22:58:11.289186 u2DelayCellOfst[2]=10 cells (3 PI)
8102 22:58:11.292437 u2DelayCellOfst[3]=10 cells (3 PI)
8103 22:58:11.295889 u2DelayCellOfst[4]=6 cells (2 PI)
8104 22:58:11.295972 u2DelayCellOfst[5]=0 cells (0 PI)
8105 22:58:11.299464 u2DelayCellOfst[6]=13 cells (4 PI)
8106 22:58:11.302158 u2DelayCellOfst[7]=13 cells (4 PI)
8107 22:58:11.309007 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8108 22:58:11.312577 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8109 22:58:11.312678 == TX Byte 1 ==
8110 22:58:11.315876 u2DelayCellOfst[8]=3 cells (1 PI)
8111 22:58:11.319077 u2DelayCellOfst[9]=0 cells (0 PI)
8112 22:58:11.322458 u2DelayCellOfst[10]=6 cells (2 PI)
8113 22:58:11.325909 u2DelayCellOfst[11]=3 cells (1 PI)
8114 22:58:11.328696 u2DelayCellOfst[12]=10 cells (3 PI)
8115 22:58:11.332267 u2DelayCellOfst[13]=13 cells (4 PI)
8116 22:58:11.335617 u2DelayCellOfst[14]=13 cells (4 PI)
8117 22:58:11.338680 u2DelayCellOfst[15]=10 cells (3 PI)
8118 22:58:11.342193 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8119 22:58:11.345746 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8120 22:58:11.349088 DramC Write-DBI on
8121 22:58:11.349171 ==
8122 22:58:11.351962 Dram Type= 6, Freq= 0, CH_0, rank 1
8123 22:58:11.355384 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8124 22:58:11.355468 ==
8125 22:58:11.355532
8126 22:58:11.355592
8127 22:58:11.358919 TX Vref Scan disable
8128 22:58:11.361882 == TX Byte 0 ==
8129 22:58:11.365280 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
8130 22:58:11.368848 == TX Byte 1 ==
8131 22:58:11.371921 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8132 22:58:11.371994 DramC Write-DBI off
8133 22:58:11.372064
8134 22:58:11.375535 [DATLAT]
8135 22:58:11.375631 Freq=1600, CH0 RK1
8136 22:58:11.375720
8137 22:58:11.378980 DATLAT Default: 0xf
8138 22:58:11.379051 0, 0xFFFF, sum = 0
8139 22:58:11.382243 1, 0xFFFF, sum = 0
8140 22:58:11.382316 2, 0xFFFF, sum = 0
8141 22:58:11.385527 3, 0xFFFF, sum = 0
8142 22:58:11.385625 4, 0xFFFF, sum = 0
8143 22:58:11.388975 5, 0xFFFF, sum = 0
8144 22:58:11.389062 6, 0xFFFF, sum = 0
8145 22:58:11.391726 7, 0xFFFF, sum = 0
8146 22:58:11.391812 8, 0xFFFF, sum = 0
8147 22:58:11.395646 9, 0xFFFF, sum = 0
8148 22:58:11.398382 10, 0xFFFF, sum = 0
8149 22:58:11.398465 11, 0xFFFF, sum = 0
8150 22:58:11.402221 12, 0xFFFF, sum = 0
8151 22:58:11.402306 13, 0xFFFF, sum = 0
8152 22:58:11.405332 14, 0x0, sum = 1
8153 22:58:11.405416 15, 0x0, sum = 2
8154 22:58:11.408729 16, 0x0, sum = 3
8155 22:58:11.408821 17, 0x0, sum = 4
8156 22:58:11.408904 best_step = 15
8157 22:58:11.411935
8158 22:58:11.412035 ==
8159 22:58:11.415681 Dram Type= 6, Freq= 0, CH_0, rank 1
8160 22:58:11.418748 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8161 22:58:11.418834 ==
8162 22:58:11.418947 RX Vref Scan: 0
8163 22:58:11.419048
8164 22:58:11.421707 RX Vref 0 -> 0, step: 1
8165 22:58:11.421795
8166 22:58:11.425228 RX Delay 19 -> 252, step: 4
8167 22:58:11.428512 iDelay=191, Bit 0, Center 134 (83 ~ 186) 104
8168 22:58:11.431803 iDelay=191, Bit 1, Center 138 (91 ~ 186) 96
8169 22:58:11.438398 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8170 22:58:11.442297 iDelay=191, Bit 3, Center 132 (79 ~ 186) 108
8171 22:58:11.445149 iDelay=191, Bit 4, Center 136 (87 ~ 186) 100
8172 22:58:11.448498 iDelay=191, Bit 5, Center 124 (71 ~ 178) 108
8173 22:58:11.451976 iDelay=191, Bit 6, Center 138 (87 ~ 190) 104
8174 22:58:11.458531 iDelay=191, Bit 7, Center 140 (91 ~ 190) 100
8175 22:58:11.462088 iDelay=191, Bit 8, Center 118 (67 ~ 170) 104
8176 22:58:11.465065 iDelay=191, Bit 9, Center 116 (67 ~ 166) 100
8177 22:58:11.468571 iDelay=191, Bit 10, Center 128 (75 ~ 182) 108
8178 22:58:11.472205 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8179 22:58:11.478757 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
8180 22:58:11.481711 iDelay=191, Bit 13, Center 134 (83 ~ 186) 104
8181 22:58:11.485103 iDelay=191, Bit 14, Center 136 (83 ~ 190) 108
8182 22:58:11.488777 iDelay=191, Bit 15, Center 136 (87 ~ 186) 100
8183 22:58:11.488862 ==
8184 22:58:11.491787 Dram Type= 6, Freq= 0, CH_0, rank 1
8185 22:58:11.498606 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8186 22:58:11.498738 ==
8187 22:58:11.498809 DQS Delay:
8188 22:58:11.502185 DQS0 = 0, DQS1 = 0
8189 22:58:11.502266 DQM Delay:
8190 22:58:11.502331 DQM0 = 134, DQM1 = 127
8191 22:58:11.505307 DQ Delay:
8192 22:58:11.508442 DQ0 =134, DQ1 =138, DQ2 =130, DQ3 =132
8193 22:58:11.512064 DQ4 =136, DQ5 =124, DQ6 =138, DQ7 =140
8194 22:58:11.515376 DQ8 =118, DQ9 =116, DQ10 =128, DQ11 =118
8195 22:58:11.518403 DQ12 =134, DQ13 =134, DQ14 =136, DQ15 =136
8196 22:58:11.518515
8197 22:58:11.518602
8198 22:58:11.518686
8199 22:58:11.522075 [DramC_TX_OE_Calibration] TA2
8200 22:58:11.525164 Original DQ_B0 (3 6) =30, OEN = 27
8201 22:58:11.528619 Original DQ_B1 (3 6) =30, OEN = 27
8202 22:58:11.531805 24, 0x0, End_B0=24 End_B1=24
8203 22:58:11.531896 25, 0x0, End_B0=25 End_B1=25
8204 22:58:11.535303 26, 0x0, End_B0=26 End_B1=26
8205 22:58:11.538604 27, 0x0, End_B0=27 End_B1=27
8206 22:58:11.541496 28, 0x0, End_B0=28 End_B1=28
8207 22:58:11.545007 29, 0x0, End_B0=29 End_B1=29
8208 22:58:11.545096 30, 0x0, End_B0=30 End_B1=30
8209 22:58:11.548734 31, 0x4141, End_B0=30 End_B1=30
8210 22:58:11.551342 Byte0 end_step=30 best_step=27
8211 22:58:11.554691 Byte1 end_step=30 best_step=27
8212 22:58:11.557881 Byte0 TX OE(2T, 0.5T) = (3, 3)
8213 22:58:11.561682 Byte1 TX OE(2T, 0.5T) = (3, 3)
8214 22:58:11.561766
8215 22:58:11.561840
8216 22:58:11.567929 [DQSOSCAuto] RK1, (LSB)MR18= 0x2109, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 393 ps
8217 22:58:11.571867 CH0 RK1: MR19=303, MR18=2109
8218 22:58:11.578427 CH0_RK1: MR19=0x303, MR18=0x2109, DQSOSC=393, MR23=63, INC=23, DEC=15
8219 22:58:11.581428 [RxdqsGatingPostProcess] freq 1600
8220 22:58:11.584919 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8221 22:58:11.587881 best DQS0 dly(2T, 0.5T) = (1, 1)
8222 22:58:11.591210 best DQS1 dly(2T, 0.5T) = (1, 1)
8223 22:58:11.594719 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8224 22:58:11.598343 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8225 22:58:11.601402 best DQS0 dly(2T, 0.5T) = (1, 1)
8226 22:58:11.604808 best DQS1 dly(2T, 0.5T) = (1, 1)
8227 22:58:11.608343 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8228 22:58:11.611581 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8229 22:58:11.614766 Pre-setting of DQS Precalculation
8230 22:58:11.617874 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8231 22:58:11.617959 ==
8232 22:58:11.621381 Dram Type= 6, Freq= 0, CH_1, rank 0
8233 22:58:11.624661 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8234 22:58:11.624746 ==
8235 22:58:11.631687 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8236 22:58:11.634544 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8237 22:58:11.641726 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8238 22:58:11.644611 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8239 22:58:11.654564 [CA 0] Center 42 (13~72) winsize 60
8240 22:58:11.657972 [CA 1] Center 42 (12~72) winsize 61
8241 22:58:11.661189 [CA 2] Center 38 (9~68) winsize 60
8242 22:58:11.664582 [CA 3] Center 38 (9~67) winsize 59
8243 22:58:11.668067 [CA 4] Center 38 (9~68) winsize 60
8244 22:58:11.671531 [CA 5] Center 37 (8~67) winsize 60
8245 22:58:11.671640
8246 22:58:11.674578 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8247 22:58:11.674658
8248 22:58:11.677963 [CATrainingPosCal] consider 1 rank data
8249 22:58:11.680889 u2DelayCellTimex100 = 290/100 ps
8250 22:58:11.687501 CA0 delay=42 (13~72),Diff = 5 PI (16 cell)
8251 22:58:11.691068 CA1 delay=42 (12~72),Diff = 5 PI (16 cell)
8252 22:58:11.693893 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8253 22:58:11.697287 CA3 delay=38 (9~67),Diff = 1 PI (3 cell)
8254 22:58:11.700827 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8255 22:58:11.704342 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8256 22:58:11.704421
8257 22:58:11.707360 CA PerBit enable=1, Macro0, CA PI delay=37
8258 22:58:11.707437
8259 22:58:11.710833 [CBTSetCACLKResult] CA Dly = 37
8260 22:58:11.714393 CS Dly: 10 (0~41)
8261 22:58:11.717414 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8262 22:58:11.720720 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8263 22:58:11.720820 ==
8264 22:58:11.723838 Dram Type= 6, Freq= 0, CH_1, rank 1
8265 22:58:11.727478 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8266 22:58:11.730635 ==
8267 22:58:11.733881 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8268 22:58:11.737401 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8269 22:58:11.744117 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8270 22:58:11.750455 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8271 22:58:11.757573 [CA 0] Center 42 (13~72) winsize 60
8272 22:58:11.761033 [CA 1] Center 41 (12~71) winsize 60
8273 22:58:11.764820 [CA 2] Center 38 (9~68) winsize 60
8274 22:58:11.767740 [CA 3] Center 37 (8~67) winsize 60
8275 22:58:11.771432 [CA 4] Center 38 (8~68) winsize 61
8276 22:58:11.774517 [CA 5] Center 37 (8~67) winsize 60
8277 22:58:11.774624
8278 22:58:11.778061 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8279 22:58:11.778165
8280 22:58:11.781168 [CATrainingPosCal] consider 2 rank data
8281 22:58:11.784568 u2DelayCellTimex100 = 290/100 ps
8282 22:58:11.788159 CA0 delay=42 (13~72),Diff = 5 PI (16 cell)
8283 22:58:11.794873 CA1 delay=41 (12~71),Diff = 4 PI (13 cell)
8284 22:58:11.797982 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8285 22:58:11.801056 CA3 delay=38 (9~67),Diff = 1 PI (3 cell)
8286 22:58:11.804724 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8287 22:58:11.807783 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8288 22:58:11.807867
8289 22:58:11.810952 CA PerBit enable=1, Macro0, CA PI delay=37
8290 22:58:11.811036
8291 22:58:11.814596 [CBTSetCACLKResult] CA Dly = 37
8292 22:58:11.817933 CS Dly: 11 (0~44)
8293 22:58:11.821018 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8294 22:58:11.824457 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8295 22:58:11.824541
8296 22:58:11.827479 ----->DramcWriteLeveling(PI) begin...
8297 22:58:11.827564 ==
8298 22:58:11.831138 Dram Type= 6, Freq= 0, CH_1, rank 0
8299 22:58:11.834339 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8300 22:58:11.837426 ==
8301 22:58:11.837508 Write leveling (Byte 0): 25 => 25
8302 22:58:11.840926 Write leveling (Byte 1): 29 => 29
8303 22:58:11.844195 DramcWriteLeveling(PI) end<-----
8304 22:58:11.844322
8305 22:58:11.844438 ==
8306 22:58:11.847644 Dram Type= 6, Freq= 0, CH_1, rank 0
8307 22:58:11.854627 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8308 22:58:11.854749 ==
8309 22:58:11.854854 [Gating] SW mode calibration
8310 22:58:11.864152 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8311 22:58:11.867632 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8312 22:58:11.874157 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8313 22:58:11.877228 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8314 22:58:11.880760 1 4 8 | B1->B0 | 2323 2525 | 0 1 | (0 0) (1 1)
8315 22:58:11.887321 1 4 12 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
8316 22:58:11.890899 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8317 22:58:11.894519 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8318 22:58:11.897458 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8319 22:58:11.904212 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8320 22:58:11.907492 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8321 22:58:11.910859 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8322 22:58:11.917347 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 1)
8323 22:58:11.920666 1 5 12 | B1->B0 | 2525 2323 | 0 0 | (1 0) (1 0)
8324 22:58:11.923837 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8325 22:58:11.930968 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8326 22:58:11.933784 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8327 22:58:11.937360 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8328 22:58:11.943876 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8329 22:58:11.947213 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8330 22:58:11.950999 1 6 8 | B1->B0 | 2727 3939 | 0 1 | (1 1) (0 0)
8331 22:58:11.957113 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8332 22:58:11.960746 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8333 22:58:11.963792 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8334 22:58:11.970841 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8335 22:58:11.973713 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8336 22:58:11.977241 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8337 22:58:11.983536 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8338 22:58:11.986816 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8339 22:58:11.990653 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8340 22:58:11.997251 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8341 22:58:12.000264 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8342 22:58:12.003765 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8343 22:58:12.010372 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8344 22:58:12.014011 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8345 22:58:12.017039 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8346 22:58:12.023538 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8347 22:58:12.026920 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8348 22:58:12.030053 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8349 22:58:12.036628 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8350 22:58:12.040073 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8351 22:58:12.043581 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8352 22:58:12.046609 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8353 22:58:12.053656 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8354 22:58:12.056475 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8355 22:58:12.059835 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8356 22:58:12.066849 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8357 22:58:12.069631 Total UI for P1: 0, mck2ui 16
8358 22:58:12.073360 best dqsien dly found for B0: ( 1, 9, 10)
8359 22:58:12.076586 Total UI for P1: 0, mck2ui 16
8360 22:58:12.080081 best dqsien dly found for B1: ( 1, 9, 10)
8361 22:58:12.082954 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8362 22:58:12.086578 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8363 22:58:12.086686
8364 22:58:12.089464 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8365 22:58:12.092964 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8366 22:58:12.096567 [Gating] SW calibration Done
8367 22:58:12.096643 ==
8368 22:58:12.099934 Dram Type= 6, Freq= 0, CH_1, rank 0
8369 22:58:12.102934 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8370 22:58:12.103012 ==
8371 22:58:12.106535 RX Vref Scan: 0
8372 22:58:12.106606
8373 22:58:12.109585 RX Vref 0 -> 0, step: 1
8374 22:58:12.109655
8375 22:58:12.109714 RX Delay 0 -> 252, step: 8
8376 22:58:12.116005 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8377 22:58:12.119592 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8378 22:58:12.123052 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8379 22:58:12.126052 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8380 22:58:12.129532 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8381 22:58:12.135932 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8382 22:58:12.139088 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8383 22:58:12.142750 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8384 22:58:12.145826 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
8385 22:58:12.149194 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8386 22:58:12.155990 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8387 22:58:12.159067 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8388 22:58:12.162296 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8389 22:58:12.165550 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8390 22:58:12.172149 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8391 22:58:12.175395 iDelay=200, Bit 15, Center 143 (96 ~ 191) 96
8392 22:58:12.175477 ==
8393 22:58:12.178698 Dram Type= 6, Freq= 0, CH_1, rank 0
8394 22:58:12.181917 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8395 22:58:12.182071 ==
8396 22:58:12.182233 DQS Delay:
8397 22:58:12.185644 DQS0 = 0, DQS1 = 0
8398 22:58:12.185751 DQM Delay:
8399 22:58:12.188821 DQM0 = 136, DQM1 = 133
8400 22:58:12.188911 DQ Delay:
8401 22:58:12.191961 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8402 22:58:12.194996 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8403 22:58:12.198564 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =127
8404 22:58:12.205256 DQ12 =139, DQ13 =143, DQ14 =139, DQ15 =143
8405 22:58:12.205373
8406 22:58:12.205473
8407 22:58:12.205568 ==
8408 22:58:12.208729 Dram Type= 6, Freq= 0, CH_1, rank 0
8409 22:58:12.211687 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8410 22:58:12.211761 ==
8411 22:58:12.211822
8412 22:58:12.211880
8413 22:58:12.215330 TX Vref Scan disable
8414 22:58:12.215400 == TX Byte 0 ==
8415 22:58:12.221829 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8416 22:58:12.224775 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8417 22:58:12.224857 == TX Byte 1 ==
8418 22:58:12.231650 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
8419 22:58:12.235035 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8420 22:58:12.235144 ==
8421 22:58:12.238074 Dram Type= 6, Freq= 0, CH_1, rank 0
8422 22:58:12.241538 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8423 22:58:12.241680 ==
8424 22:58:12.256702
8425 22:58:12.259712 TX Vref early break, caculate TX vref
8426 22:58:12.263415 TX Vref=16, minBit 1, minWin=22, winSum=366
8427 22:58:12.266753 TX Vref=18, minBit 1, minWin=23, winSum=379
8428 22:58:12.269645 TX Vref=20, minBit 1, minWin=23, winSum=391
8429 22:58:12.273194 TX Vref=22, minBit 6, minWin=24, winSum=400
8430 22:58:12.276609 TX Vref=24, minBit 0, minWin=25, winSum=414
8431 22:58:12.283459 TX Vref=26, minBit 0, minWin=25, winSum=422
8432 22:58:12.286575 TX Vref=28, minBit 1, minWin=25, winSum=423
8433 22:58:12.290112 TX Vref=30, minBit 0, minWin=24, winSum=413
8434 22:58:12.293156 TX Vref=32, minBit 0, minWin=24, winSum=412
8435 22:58:12.296514 TX Vref=34, minBit 0, minWin=24, winSum=403
8436 22:58:12.300065 TX Vref=36, minBit 6, minWin=23, winSum=386
8437 22:58:12.306429 [TxChooseVref] Worse bit 1, Min win 25, Win sum 423, Final Vref 28
8438 22:58:12.306516
8439 22:58:12.309702 Final TX Range 0 Vref 28
8440 22:58:12.309786
8441 22:58:12.309851 ==
8442 22:58:12.313074 Dram Type= 6, Freq= 0, CH_1, rank 0
8443 22:58:12.316641 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8444 22:58:12.316724 ==
8445 22:58:12.316791
8446 22:58:12.316852
8447 22:58:12.319910 TX Vref Scan disable
8448 22:58:12.326588 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8449 22:58:12.326674 == TX Byte 0 ==
8450 22:58:12.330115 u2DelayCellOfst[0]=16 cells (5 PI)
8451 22:58:12.332960 u2DelayCellOfst[1]=10 cells (3 PI)
8452 22:58:12.336477 u2DelayCellOfst[2]=0 cells (0 PI)
8453 22:58:12.339470 u2DelayCellOfst[3]=6 cells (2 PI)
8454 22:58:12.343063 u2DelayCellOfst[4]=10 cells (3 PI)
8455 22:58:12.346464 u2DelayCellOfst[5]=16 cells (5 PI)
8456 22:58:12.349481 u2DelayCellOfst[6]=16 cells (5 PI)
8457 22:58:12.353285 u2DelayCellOfst[7]=3 cells (1 PI)
8458 22:58:12.356370 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8459 22:58:12.360138 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8460 22:58:12.363125 == TX Byte 1 ==
8461 22:58:12.363207 u2DelayCellOfst[8]=0 cells (0 PI)
8462 22:58:12.366490 u2DelayCellOfst[9]=6 cells (2 PI)
8463 22:58:12.369899 u2DelayCellOfst[10]=13 cells (4 PI)
8464 22:58:12.373147 u2DelayCellOfst[11]=6 cells (2 PI)
8465 22:58:12.376099 u2DelayCellOfst[12]=16 cells (5 PI)
8466 22:58:12.379831 u2DelayCellOfst[13]=20 cells (6 PI)
8467 22:58:12.383232 u2DelayCellOfst[14]=20 cells (6 PI)
8468 22:58:12.386241 u2DelayCellOfst[15]=20 cells (6 PI)
8469 22:58:12.389841 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8470 22:58:12.396385 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8471 22:58:12.396494 DramC Write-DBI on
8472 22:58:12.396574 ==
8473 22:58:12.399522 Dram Type= 6, Freq= 0, CH_1, rank 0
8474 22:58:12.405861 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8475 22:58:12.405972 ==
8476 22:58:12.406067
8477 22:58:12.406155
8478 22:58:12.406243 TX Vref Scan disable
8479 22:58:12.409897 == TX Byte 0 ==
8480 22:58:12.413246 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8481 22:58:12.416134 == TX Byte 1 ==
8482 22:58:12.419902 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8483 22:58:12.422810 DramC Write-DBI off
8484 22:58:12.422921
8485 22:58:12.423059 [DATLAT]
8486 22:58:12.423153 Freq=1600, CH1 RK0
8487 22:58:12.423241
8488 22:58:12.426281 DATLAT Default: 0xf
8489 22:58:12.426359 0, 0xFFFF, sum = 0
8490 22:58:12.429542 1, 0xFFFF, sum = 0
8491 22:58:12.433367 2, 0xFFFF, sum = 0
8492 22:58:12.433477 3, 0xFFFF, sum = 0
8493 22:58:12.436640 4, 0xFFFF, sum = 0
8494 22:58:12.436743 5, 0xFFFF, sum = 0
8495 22:58:12.439787 6, 0xFFFF, sum = 0
8496 22:58:12.439876 7, 0xFFFF, sum = 0
8497 22:58:12.443084 8, 0xFFFF, sum = 0
8498 22:58:12.443188 9, 0xFFFF, sum = 0
8499 22:58:12.446369 10, 0xFFFF, sum = 0
8500 22:58:12.446454 11, 0xFFFF, sum = 0
8501 22:58:12.449889 12, 0xFFFF, sum = 0
8502 22:58:12.449973 13, 0xFFFF, sum = 0
8503 22:58:12.452992 14, 0x0, sum = 1
8504 22:58:12.453076 15, 0x0, sum = 2
8505 22:58:12.456289 16, 0x0, sum = 3
8506 22:58:12.456374 17, 0x0, sum = 4
8507 22:58:12.459710 best_step = 15
8508 22:58:12.459792
8509 22:58:12.459857 ==
8510 22:58:12.463409 Dram Type= 6, Freq= 0, CH_1, rank 0
8511 22:58:12.466338 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8512 22:58:12.466421 ==
8513 22:58:12.466486 RX Vref Scan: 1
8514 22:58:12.470043
8515 22:58:12.470125 Set Vref Range= 24 -> 127
8516 22:58:12.470190
8517 22:58:12.473021 RX Vref 24 -> 127, step: 1
8518 22:58:12.473104
8519 22:58:12.476371 RX Delay 27 -> 252, step: 4
8520 22:58:12.476453
8521 22:58:12.479580 Set Vref, RX VrefLevel [Byte0]: 24
8522 22:58:12.483251 [Byte1]: 24
8523 22:58:12.483335
8524 22:58:12.486203 Set Vref, RX VrefLevel [Byte0]: 25
8525 22:58:12.489434 [Byte1]: 25
8526 22:58:12.489543
8527 22:58:12.493144 Set Vref, RX VrefLevel [Byte0]: 26
8528 22:58:12.496086 [Byte1]: 26
8529 22:58:12.500178
8530 22:58:12.500318 Set Vref, RX VrefLevel [Byte0]: 27
8531 22:58:12.503130 [Byte1]: 27
8532 22:58:12.507798
8533 22:58:12.507880 Set Vref, RX VrefLevel [Byte0]: 28
8534 22:58:12.510722 [Byte1]: 28
8535 22:58:12.514942
8536 22:58:12.515024 Set Vref, RX VrefLevel [Byte0]: 29
8537 22:58:12.518657 [Byte1]: 29
8538 22:58:12.522671
8539 22:58:12.522752 Set Vref, RX VrefLevel [Byte0]: 30
8540 22:58:12.526018 [Byte1]: 30
8541 22:58:12.530083
8542 22:58:12.530165 Set Vref, RX VrefLevel [Byte0]: 31
8543 22:58:12.533801 [Byte1]: 31
8544 22:58:12.537711
8545 22:58:12.537796 Set Vref, RX VrefLevel [Byte0]: 32
8546 22:58:12.540867 [Byte1]: 32
8547 22:58:12.544933
8548 22:58:12.545039 Set Vref, RX VrefLevel [Byte0]: 33
8549 22:58:12.548270 [Byte1]: 33
8550 22:58:12.553041
8551 22:58:12.553150 Set Vref, RX VrefLevel [Byte0]: 34
8552 22:58:12.556063 [Byte1]: 34
8553 22:58:12.560168
8554 22:58:12.560251 Set Vref, RX VrefLevel [Byte0]: 35
8555 22:58:12.563387 [Byte1]: 35
8556 22:58:12.567633
8557 22:58:12.567715 Set Vref, RX VrefLevel [Byte0]: 36
8558 22:58:12.571107 [Byte1]: 36
8559 22:58:12.575607
8560 22:58:12.575690 Set Vref, RX VrefLevel [Byte0]: 37
8561 22:58:12.578614 [Byte1]: 37
8562 22:58:12.583285
8563 22:58:12.583368 Set Vref, RX VrefLevel [Byte0]: 38
8564 22:58:12.585992 [Byte1]: 38
8565 22:58:12.590471
8566 22:58:12.590554 Set Vref, RX VrefLevel [Byte0]: 39
8567 22:58:12.593910 [Byte1]: 39
8568 22:58:12.598108
8569 22:58:12.598191 Set Vref, RX VrefLevel [Byte0]: 40
8570 22:58:12.601086 [Byte1]: 40
8571 22:58:12.605206
8572 22:58:12.605289 Set Vref, RX VrefLevel [Byte0]: 41
8573 22:58:12.608966 [Byte1]: 41
8574 22:58:12.613190
8575 22:58:12.613272 Set Vref, RX VrefLevel [Byte0]: 42
8576 22:58:12.616117 [Byte1]: 42
8577 22:58:12.620328
8578 22:58:12.623754 Set Vref, RX VrefLevel [Byte0]: 43
8579 22:58:12.626994 [Byte1]: 43
8580 22:58:12.627077
8581 22:58:12.630122 Set Vref, RX VrefLevel [Byte0]: 44
8582 22:58:12.633860 [Byte1]: 44
8583 22:58:12.633943
8584 22:58:12.636812 Set Vref, RX VrefLevel [Byte0]: 45
8585 22:58:12.640587 [Byte1]: 45
8586 22:58:12.640670
8587 22:58:12.643473 Set Vref, RX VrefLevel [Byte0]: 46
8588 22:58:12.647015 [Byte1]: 46
8589 22:58:12.650564
8590 22:58:12.650679 Set Vref, RX VrefLevel [Byte0]: 47
8591 22:58:12.653977 [Byte1]: 47
8592 22:58:12.658149
8593 22:58:12.658233 Set Vref, RX VrefLevel [Byte0]: 48
8594 22:58:12.661496 [Byte1]: 48
8595 22:58:12.665544
8596 22:58:12.665666 Set Vref, RX VrefLevel [Byte0]: 49
8597 22:58:12.669126 [Byte1]: 49
8598 22:58:12.673231
8599 22:58:12.673356 Set Vref, RX VrefLevel [Byte0]: 50
8600 22:58:12.676942 [Byte1]: 50
8601 22:58:12.680732
8602 22:58:12.680844 Set Vref, RX VrefLevel [Byte0]: 51
8603 22:58:12.684107 [Byte1]: 51
8604 22:58:12.688110
8605 22:58:12.688207 Set Vref, RX VrefLevel [Byte0]: 52
8606 22:58:12.691521 [Byte1]: 52
8607 22:58:12.695902
8608 22:58:12.695992 Set Vref, RX VrefLevel [Byte0]: 53
8609 22:58:12.699288 [Byte1]: 53
8610 22:58:12.703612
8611 22:58:12.703729 Set Vref, RX VrefLevel [Byte0]: 54
8612 22:58:12.706594 [Byte1]: 54
8613 22:58:12.711007
8614 22:58:12.711112 Set Vref, RX VrefLevel [Byte0]: 55
8615 22:58:12.714550 [Byte1]: 55
8616 22:58:12.718868
8617 22:58:12.718972 Set Vref, RX VrefLevel [Byte0]: 56
8618 22:58:12.721918 [Byte1]: 56
8619 22:58:12.726290
8620 22:58:12.726376 Set Vref, RX VrefLevel [Byte0]: 57
8621 22:58:12.729043 [Byte1]: 57
8622 22:58:12.733798
8623 22:58:12.733880 Set Vref, RX VrefLevel [Byte0]: 58
8624 22:58:12.737043 [Byte1]: 58
8625 22:58:12.740836
8626 22:58:12.740920 Set Vref, RX VrefLevel [Byte0]: 59
8627 22:58:12.744269 [Byte1]: 59
8628 22:58:12.748308
8629 22:58:12.748393 Set Vref, RX VrefLevel [Byte0]: 60
8630 22:58:12.751804 [Byte1]: 60
8631 22:58:12.756077
8632 22:58:12.756161 Set Vref, RX VrefLevel [Byte0]: 61
8633 22:58:12.759288 [Byte1]: 61
8634 22:58:12.763884
8635 22:58:12.763968 Set Vref, RX VrefLevel [Byte0]: 62
8636 22:58:12.766883 [Byte1]: 62
8637 22:58:12.770978
8638 22:58:12.771060 Set Vref, RX VrefLevel [Byte0]: 63
8639 22:58:12.774438 [Byte1]: 63
8640 22:58:12.779159
8641 22:58:12.779243 Set Vref, RX VrefLevel [Byte0]: 64
8642 22:58:12.781998 [Byte1]: 64
8643 22:58:12.786247
8644 22:58:12.786343 Set Vref, RX VrefLevel [Byte0]: 65
8645 22:58:12.789823 [Byte1]: 65
8646 22:58:12.793700
8647 22:58:12.793784 Set Vref, RX VrefLevel [Byte0]: 66
8648 22:58:12.797027 [Byte1]: 66
8649 22:58:12.801443
8650 22:58:12.801526 Set Vref, RX VrefLevel [Byte0]: 67
8651 22:58:12.804873 [Byte1]: 67
8652 22:58:12.809114
8653 22:58:12.809253 Set Vref, RX VrefLevel [Byte0]: 68
8654 22:58:12.812177 [Byte1]: 68
8655 22:58:12.816204
8656 22:58:12.816288 Set Vref, RX VrefLevel [Byte0]: 69
8657 22:58:12.819500 [Byte1]: 69
8658 22:58:12.823634
8659 22:58:12.823744 Set Vref, RX VrefLevel [Byte0]: 70
8660 22:58:12.827268 [Byte1]: 70
8661 22:58:12.831499
8662 22:58:12.831583 Set Vref, RX VrefLevel [Byte0]: 71
8663 22:58:12.834390 [Byte1]: 71
8664 22:58:12.839220
8665 22:58:12.839314 Set Vref, RX VrefLevel [Byte0]: 72
8666 22:58:12.842136 [Byte1]: 72
8667 22:58:12.846717
8668 22:58:12.846802 Set Vref, RX VrefLevel [Byte0]: 73
8669 22:58:12.849985 [Byte1]: 73
8670 22:58:12.854121
8671 22:58:12.854219 Set Vref, RX VrefLevel [Byte0]: 74
8672 22:58:12.857837 [Byte1]: 74
8673 22:58:12.861767
8674 22:58:12.861852 Set Vref, RX VrefLevel [Byte0]: 75
8675 22:58:12.864543 [Byte1]: 75
8676 22:58:12.869239
8677 22:58:12.869339 Set Vref, RX VrefLevel [Byte0]: 76
8678 22:58:12.872267 [Byte1]: 76
8679 22:58:12.876493
8680 22:58:12.876596 Set Vref, RX VrefLevel [Byte0]: 77
8681 22:58:12.879853 [Byte1]: 77
8682 22:58:12.884315
8683 22:58:12.884397 Final RX Vref Byte 0 = 57 to rank0
8684 22:58:12.887485 Final RX Vref Byte 1 = 56 to rank0
8685 22:58:12.890550 Final RX Vref Byte 0 = 57 to rank1
8686 22:58:12.894174 Final RX Vref Byte 1 = 56 to rank1==
8687 22:58:12.897386 Dram Type= 6, Freq= 0, CH_1, rank 0
8688 22:58:12.904116 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8689 22:58:12.904213 ==
8690 22:58:12.904285 DQS Delay:
8691 22:58:12.904384 DQS0 = 0, DQS1 = 0
8692 22:58:12.907348 DQM Delay:
8693 22:58:12.907436 DQM0 = 134, DQM1 = 131
8694 22:58:12.910792 DQ Delay:
8695 22:58:12.913940 DQ0 =140, DQ1 =128, DQ2 =124, DQ3 =130
8696 22:58:12.917226 DQ4 =132, DQ5 =144, DQ6 =142, DQ7 =132
8697 22:58:12.920896 DQ8 =116, DQ9 =122, DQ10 =132, DQ11 =124
8698 22:58:12.924105 DQ12 =140, DQ13 =140, DQ14 =140, DQ15 =140
8699 22:58:12.924189
8700 22:58:12.924254
8701 22:58:12.924316
8702 22:58:12.927398 [DramC_TX_OE_Calibration] TA2
8703 22:58:12.930852 Original DQ_B0 (3 6) =30, OEN = 27
8704 22:58:12.933964 Original DQ_B1 (3 6) =30, OEN = 27
8705 22:58:12.937149 24, 0x0, End_B0=24 End_B1=24
8706 22:58:12.937261 25, 0x0, End_B0=25 End_B1=25
8707 22:58:12.941031 26, 0x0, End_B0=26 End_B1=26
8708 22:58:12.943959 27, 0x0, End_B0=27 End_B1=27
8709 22:58:12.947414 28, 0x0, End_B0=28 End_B1=28
8710 22:58:12.947530 29, 0x0, End_B0=29 End_B1=29
8711 22:58:12.950991 30, 0x0, End_B0=30 End_B1=30
8712 22:58:12.953969 31, 0x4141, End_B0=30 End_B1=30
8713 22:58:12.957024 Byte0 end_step=30 best_step=27
8714 22:58:12.960464 Byte1 end_step=30 best_step=27
8715 22:58:12.964217 Byte0 TX OE(2T, 0.5T) = (3, 3)
8716 22:58:12.964301 Byte1 TX OE(2T, 0.5T) = (3, 3)
8717 22:58:12.967250
8718 22:58:12.967334
8719 22:58:12.973772 [DQSOSCAuto] RK0, (LSB)MR18= 0x1826, (MSB)MR19= 0x303, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
8720 22:58:12.976978 CH1 RK0: MR19=303, MR18=1826
8721 22:58:12.983690 CH1_RK0: MR19=0x303, MR18=0x1826, DQSOSC=390, MR23=63, INC=24, DEC=16
8722 22:58:12.983775
8723 22:58:12.987338 ----->DramcWriteLeveling(PI) begin...
8724 22:58:12.987424 ==
8725 22:58:12.990756 Dram Type= 6, Freq= 0, CH_1, rank 1
8726 22:58:12.993902 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8727 22:58:12.993987 ==
8728 22:58:12.996794 Write leveling (Byte 0): 27 => 27
8729 22:58:13.000335 Write leveling (Byte 1): 28 => 28
8730 22:58:13.003776 DramcWriteLeveling(PI) end<-----
8731 22:58:13.003887
8732 22:58:13.003987 ==
8733 22:58:13.006863 Dram Type= 6, Freq= 0, CH_1, rank 1
8734 22:58:13.010390 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8735 22:58:13.010474 ==
8736 22:58:13.013536 [Gating] SW mode calibration
8737 22:58:13.020151 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8738 22:58:13.026724 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8739 22:58:13.030325 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8740 22:58:13.033451 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8741 22:58:13.040026 1 4 8 | B1->B0 | 2929 2323 | 1 0 | (1 1) (0 0)
8742 22:58:13.043236 1 4 12 | B1->B0 | 3434 3232 | 0 0 | (0 0) (0 0)
8743 22:58:13.046879 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8744 22:58:13.053212 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8745 22:58:13.056722 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8746 22:58:13.059749 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8747 22:58:13.066487 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8748 22:58:13.069991 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8749 22:58:13.073520 1 5 8 | B1->B0 | 3434 3434 | 0 1 | (0 1) (1 0)
8750 22:58:13.079934 1 5 12 | B1->B0 | 2424 2d2d | 0 0 | (0 0) (0 0)
8751 22:58:13.083456 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8752 22:58:13.086831 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8753 22:58:13.093535 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8754 22:58:13.096687 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8755 22:58:13.099568 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8756 22:58:13.106442 1 6 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8757 22:58:13.110090 1 6 8 | B1->B0 | 2e2e 2323 | 0 0 | (0 0) (0 0)
8758 22:58:13.112962 1 6 12 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
8759 22:58:13.119624 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8760 22:58:13.123243 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8761 22:58:13.126228 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8762 22:58:13.133563 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8763 22:58:13.136537 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8764 22:58:13.140354 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8765 22:58:13.146276 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8766 22:58:13.149469 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8767 22:58:13.152889 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8768 22:58:13.159769 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8769 22:58:13.162804 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8770 22:58:13.166527 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8771 22:58:13.169859 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8772 22:58:13.176391 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8773 22:58:13.179611 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8774 22:58:13.183075 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8775 22:58:13.189810 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8776 22:58:13.193041 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8777 22:58:13.196345 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8778 22:58:13.202924 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8779 22:58:13.206169 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8780 22:58:13.209864 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8781 22:58:13.216337 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8782 22:58:13.219129 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8783 22:58:13.222874 Total UI for P1: 0, mck2ui 16
8784 22:58:13.225889 best dqsien dly found for B1: ( 1, 9, 6)
8785 22:58:13.229564 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8786 22:58:13.233075 Total UI for P1: 0, mck2ui 16
8787 22:58:13.236119 best dqsien dly found for B0: ( 1, 9, 12)
8788 22:58:13.239195 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8789 22:58:13.242827 best DQS1 dly(MCK, UI, PI) = (1, 9, 6)
8790 22:58:13.242930
8791 22:58:13.249243 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8792 22:58:13.252837 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 6)
8793 22:58:13.255720 [Gating] SW calibration Done
8794 22:58:13.255830 ==
8795 22:58:13.259250 Dram Type= 6, Freq= 0, CH_1, rank 1
8796 22:58:13.262427 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8797 22:58:13.262512 ==
8798 22:58:13.262604 RX Vref Scan: 0
8799 22:58:13.262695
8800 22:58:13.265994 RX Vref 0 -> 0, step: 1
8801 22:58:13.266076
8802 22:58:13.269092 RX Delay 0 -> 252, step: 8
8803 22:58:13.272387 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8804 22:58:13.275911 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8805 22:58:13.279199 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8806 22:58:13.285692 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8807 22:58:13.289618 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8808 22:58:13.292324 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8809 22:58:13.295864 iDelay=208, Bit 6, Center 143 (88 ~ 199) 112
8810 22:58:13.298878 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8811 22:58:13.305744 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8812 22:58:13.309156 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8813 22:58:13.312494 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8814 22:58:13.316150 iDelay=208, Bit 11, Center 127 (72 ~ 183) 112
8815 22:58:13.319048 iDelay=208, Bit 12, Center 143 (88 ~ 199) 112
8816 22:58:13.325762 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8817 22:58:13.329173 iDelay=208, Bit 14, Center 139 (88 ~ 191) 104
8818 22:58:13.332152 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8819 22:58:13.332260 ==
8820 22:58:13.336079 Dram Type= 6, Freq= 0, CH_1, rank 1
8821 22:58:13.339040 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8822 22:58:13.342504 ==
8823 22:58:13.342589 DQS Delay:
8824 22:58:13.342654 DQS0 = 0, DQS1 = 0
8825 22:58:13.345680 DQM Delay:
8826 22:58:13.345787 DQM0 = 136, DQM1 = 133
8827 22:58:13.348773 DQ Delay:
8828 22:58:13.352416 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =131
8829 22:58:13.355534 DQ4 =131, DQ5 =151, DQ6 =143, DQ7 =135
8830 22:58:13.358841 DQ8 =119, DQ9 =119, DQ10 =135, DQ11 =127
8831 22:58:13.362341 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8832 22:58:13.362441
8833 22:58:13.362540
8834 22:58:13.362602 ==
8835 22:58:13.365210 Dram Type= 6, Freq= 0, CH_1, rank 1
8836 22:58:13.368605 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8837 22:58:13.368688 ==
8838 22:58:13.368768
8839 22:58:13.371959
8840 22:58:13.372041 TX Vref Scan disable
8841 22:58:13.375296 == TX Byte 0 ==
8842 22:58:13.378718 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8843 22:58:13.381983 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8844 22:58:13.385307 == TX Byte 1 ==
8845 22:58:13.388931 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8846 22:58:13.391971 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8847 22:58:13.392080 ==
8848 22:58:13.395635 Dram Type= 6, Freq= 0, CH_1, rank 1
8849 22:58:13.401845 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8850 22:58:13.401963 ==
8851 22:58:13.413527
8852 22:58:13.416661 TX Vref early break, caculate TX vref
8853 22:58:13.420099 TX Vref=16, minBit 0, minWin=23, winSum=384
8854 22:58:13.423188 TX Vref=18, minBit 1, minWin=23, winSum=392
8855 22:58:13.426760 TX Vref=20, minBit 1, minWin=24, winSum=399
8856 22:58:13.430172 TX Vref=22, minBit 0, minWin=25, winSum=411
8857 22:58:13.433180 TX Vref=24, minBit 0, minWin=25, winSum=419
8858 22:58:13.439698 TX Vref=26, minBit 0, minWin=25, winSum=420
8859 22:58:13.443219 TX Vref=28, minBit 6, minWin=25, winSum=426
8860 22:58:13.446790 TX Vref=30, minBit 0, minWin=25, winSum=422
8861 22:58:13.449941 TX Vref=32, minBit 6, minWin=24, winSum=412
8862 22:58:13.453090 TX Vref=34, minBit 0, minWin=24, winSum=403
8863 22:58:13.459634 [TxChooseVref] Worse bit 6, Min win 25, Win sum 426, Final Vref 28
8864 22:58:13.459742
8865 22:58:13.462871 Final TX Range 0 Vref 28
8866 22:58:13.462958
8867 22:58:13.463032 ==
8868 22:58:13.466336 Dram Type= 6, Freq= 0, CH_1, rank 1
8869 22:58:13.469713 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8870 22:58:13.469824 ==
8871 22:58:13.469920
8872 22:58:13.470011
8873 22:58:13.473213 TX Vref Scan disable
8874 22:58:13.479572 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8875 22:58:13.479663 == TX Byte 0 ==
8876 22:58:13.483051 u2DelayCellOfst[0]=16 cells (5 PI)
8877 22:58:13.486341 u2DelayCellOfst[1]=10 cells (3 PI)
8878 22:58:13.490032 u2DelayCellOfst[2]=0 cells (0 PI)
8879 22:58:13.492992 u2DelayCellOfst[3]=6 cells (2 PI)
8880 22:58:13.496560 u2DelayCellOfst[4]=6 cells (2 PI)
8881 22:58:13.499387 u2DelayCellOfst[5]=16 cells (5 PI)
8882 22:58:13.502966 u2DelayCellOfst[6]=16 cells (5 PI)
8883 22:58:13.503051 u2DelayCellOfst[7]=6 cells (2 PI)
8884 22:58:13.509188 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8885 22:58:13.512652 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8886 22:58:13.512771 == TX Byte 1 ==
8887 22:58:13.516456 u2DelayCellOfst[8]=0 cells (0 PI)
8888 22:58:13.519390 u2DelayCellOfst[9]=3 cells (1 PI)
8889 22:58:13.522714 u2DelayCellOfst[10]=10 cells (3 PI)
8890 22:58:13.526384 u2DelayCellOfst[11]=6 cells (2 PI)
8891 22:58:13.529767 u2DelayCellOfst[12]=13 cells (4 PI)
8892 22:58:13.532849 u2DelayCellOfst[13]=16 cells (5 PI)
8893 22:58:13.536421 u2DelayCellOfst[14]=16 cells (5 PI)
8894 22:58:13.539260 u2DelayCellOfst[15]=20 cells (6 PI)
8895 22:58:13.542840 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8896 22:58:13.549231 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8897 22:58:13.549317 DramC Write-DBI on
8898 22:58:13.549386 ==
8899 22:58:13.552618 Dram Type= 6, Freq= 0, CH_1, rank 1
8900 22:58:13.556100 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8901 22:58:13.559526 ==
8902 22:58:13.559610
8903 22:58:13.559676
8904 22:58:13.559739 TX Vref Scan disable
8905 22:58:13.562444 == TX Byte 0 ==
8906 22:58:13.565699 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8907 22:58:13.569134 == TX Byte 1 ==
8908 22:58:13.572376 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8909 22:58:13.575907 DramC Write-DBI off
8910 22:58:13.575991
8911 22:58:13.576059 [DATLAT]
8912 22:58:13.576121 Freq=1600, CH1 RK1
8913 22:58:13.576181
8914 22:58:13.578877 DATLAT Default: 0xf
8915 22:58:13.582031 0, 0xFFFF, sum = 0
8916 22:58:13.582117 1, 0xFFFF, sum = 0
8917 22:58:13.585740 2, 0xFFFF, sum = 0
8918 22:58:13.585825 3, 0xFFFF, sum = 0
8919 22:58:13.589018 4, 0xFFFF, sum = 0
8920 22:58:13.589105 5, 0xFFFF, sum = 0
8921 22:58:13.592412 6, 0xFFFF, sum = 0
8922 22:58:13.592498 7, 0xFFFF, sum = 0
8923 22:58:13.595808 8, 0xFFFF, sum = 0
8924 22:58:13.595894 9, 0xFFFF, sum = 0
8925 22:58:13.599074 10, 0xFFFF, sum = 0
8926 22:58:13.599161 11, 0xFFFF, sum = 0
8927 22:58:13.602739 12, 0xFFFF, sum = 0
8928 22:58:13.602831 13, 0xFFFF, sum = 0
8929 22:58:13.605874 14, 0x0, sum = 1
8930 22:58:13.605990 15, 0x0, sum = 2
8931 22:58:13.608763 16, 0x0, sum = 3
8932 22:58:13.608848 17, 0x0, sum = 4
8933 22:58:13.612244 best_step = 15
8934 22:58:13.612328
8935 22:58:13.612395 ==
8936 22:58:13.615847 Dram Type= 6, Freq= 0, CH_1, rank 1
8937 22:58:13.619105 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8938 22:58:13.619216 ==
8939 22:58:13.622048 RX Vref Scan: 0
8940 22:58:13.622150
8941 22:58:13.622242 RX Vref 0 -> 0, step: 1
8942 22:58:13.622333
8943 22:58:13.625629 RX Delay 19 -> 252, step: 4
8944 22:58:13.628965 iDelay=195, Bit 0, Center 138 (91 ~ 186) 96
8945 22:58:13.635547 iDelay=195, Bit 1, Center 128 (79 ~ 178) 100
8946 22:58:13.638774 iDelay=195, Bit 2, Center 122 (71 ~ 174) 104
8947 22:58:13.642137 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
8948 22:58:13.645168 iDelay=195, Bit 4, Center 130 (83 ~ 178) 96
8949 22:58:13.648727 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
8950 22:58:13.655334 iDelay=195, Bit 6, Center 144 (95 ~ 194) 100
8951 22:58:13.658834 iDelay=195, Bit 7, Center 132 (79 ~ 186) 108
8952 22:58:13.662215 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8953 22:58:13.665215 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8954 22:58:13.668736 iDelay=195, Bit 10, Center 132 (83 ~ 182) 100
8955 22:58:13.675660 iDelay=195, Bit 11, Center 126 (75 ~ 178) 104
8956 22:58:13.678569 iDelay=195, Bit 12, Center 140 (87 ~ 194) 108
8957 22:58:13.682103 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
8958 22:58:13.685497 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
8959 22:58:13.688937 iDelay=195, Bit 15, Center 140 (91 ~ 190) 100
8960 22:58:13.691674 ==
8961 22:58:13.691758 Dram Type= 6, Freq= 0, CH_1, rank 1
8962 22:58:13.698696 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8963 22:58:13.698781 ==
8964 22:58:13.698848 DQS Delay:
8965 22:58:13.702150 DQS0 = 0, DQS1 = 0
8966 22:58:13.702235 DQM Delay:
8967 22:58:13.705364 DQM0 = 133, DQM1 = 130
8968 22:58:13.705446 DQ Delay:
8969 22:58:13.708510 DQ0 =138, DQ1 =128, DQ2 =122, DQ3 =130
8970 22:58:13.711570 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =132
8971 22:58:13.715004 DQ8 =116, DQ9 =118, DQ10 =132, DQ11 =126
8972 22:58:13.718710 DQ12 =140, DQ13 =138, DQ14 =136, DQ15 =140
8973 22:58:13.718819
8974 22:58:13.718912
8975 22:58:13.718998
8976 22:58:13.721559 [DramC_TX_OE_Calibration] TA2
8977 22:58:13.725115 Original DQ_B0 (3 6) =30, OEN = 27
8978 22:58:13.728643 Original DQ_B1 (3 6) =30, OEN = 27
8979 22:58:13.731804 24, 0x0, End_B0=24 End_B1=24
8980 22:58:13.734959 25, 0x0, End_B0=25 End_B1=25
8981 22:58:13.735043 26, 0x0, End_B0=26 End_B1=26
8982 22:58:13.738404 27, 0x0, End_B0=27 End_B1=27
8983 22:58:13.741529 28, 0x0, End_B0=28 End_B1=28
8984 22:58:13.745050 29, 0x0, End_B0=29 End_B1=29
8985 22:58:13.745135 30, 0x0, End_B0=30 End_B1=30
8986 22:58:13.748100 31, 0x4141, End_B0=30 End_B1=30
8987 22:58:13.751764 Byte0 end_step=30 best_step=27
8988 22:58:13.755443 Byte1 end_step=30 best_step=27
8989 22:58:13.758342 Byte0 TX OE(2T, 0.5T) = (3, 3)
8990 22:58:13.762039 Byte1 TX OE(2T, 0.5T) = (3, 3)
8991 22:58:13.762121
8992 22:58:13.762187
8993 22:58:13.768041 [DQSOSCAuto] RK1, (LSB)MR18= 0x2207, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 392 ps
8994 22:58:13.771873 CH1 RK1: MR19=303, MR18=2207
8995 22:58:13.778147 CH1_RK1: MR19=0x303, MR18=0x2207, DQSOSC=392, MR23=63, INC=24, DEC=16
8996 22:58:13.781758 [RxdqsGatingPostProcess] freq 1600
8997 22:58:13.788362 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8998 22:58:13.788445 best DQS0 dly(2T, 0.5T) = (1, 1)
8999 22:58:13.791521 best DQS1 dly(2T, 0.5T) = (1, 1)
9000 22:58:13.794779 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9001 22:58:13.798254 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9002 22:58:13.801765 best DQS0 dly(2T, 0.5T) = (1, 1)
9003 22:58:13.804610 best DQS1 dly(2T, 0.5T) = (1, 1)
9004 22:58:13.808177 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9005 22:58:13.811674 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9006 22:58:13.815128 Pre-setting of DQS Precalculation
9007 22:58:13.817895 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9008 22:58:13.824704 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9009 22:58:13.834519 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9010 22:58:13.834604
9011 22:58:13.834669
9012 22:58:13.838125 [Calibration Summary] 3200 Mbps
9013 22:58:13.838208 CH 0, Rank 0
9014 22:58:13.841026 SW Impedance : PASS
9015 22:58:13.841108 DUTY Scan : NO K
9016 22:58:13.844553 ZQ Calibration : PASS
9017 22:58:13.848134 Jitter Meter : NO K
9018 22:58:13.848217 CBT Training : PASS
9019 22:58:13.850968 Write leveling : PASS
9020 22:58:13.854320 RX DQS gating : PASS
9021 22:58:13.854403 RX DQ/DQS(RDDQC) : PASS
9022 22:58:13.857800 TX DQ/DQS : PASS
9023 22:58:13.857883 RX DATLAT : PASS
9024 22:58:13.861478 RX DQ/DQS(Engine): PASS
9025 22:58:13.864820 TX OE : PASS
9026 22:58:13.864903 All Pass.
9027 22:58:13.864969
9028 22:58:13.865030 CH 0, Rank 1
9029 22:58:13.868087 SW Impedance : PASS
9030 22:58:13.871316 DUTY Scan : NO K
9031 22:58:13.871398 ZQ Calibration : PASS
9032 22:58:13.874719 Jitter Meter : NO K
9033 22:58:13.878138 CBT Training : PASS
9034 22:58:13.878221 Write leveling : PASS
9035 22:58:13.880959 RX DQS gating : PASS
9036 22:58:13.884499 RX DQ/DQS(RDDQC) : PASS
9037 22:58:13.884581 TX DQ/DQS : PASS
9038 22:58:13.887564 RX DATLAT : PASS
9039 22:58:13.891061 RX DQ/DQS(Engine): PASS
9040 22:58:13.891144 TX OE : PASS
9041 22:58:13.894715 All Pass.
9042 22:58:13.894797
9043 22:58:13.894863 CH 1, Rank 0
9044 22:58:13.898062 SW Impedance : PASS
9045 22:58:13.898144 DUTY Scan : NO K
9046 22:58:13.900965 ZQ Calibration : PASS
9047 22:58:13.904291 Jitter Meter : NO K
9048 22:58:13.904374 CBT Training : PASS
9049 22:58:13.908003 Write leveling : PASS
9050 22:58:13.908086 RX DQS gating : PASS
9051 22:58:13.911393 RX DQ/DQS(RDDQC) : PASS
9052 22:58:13.914490 TX DQ/DQS : PASS
9053 22:58:13.914578 RX DATLAT : PASS
9054 22:58:13.917970 RX DQ/DQS(Engine): PASS
9055 22:58:13.921557 TX OE : PASS
9056 22:58:13.921664 All Pass.
9057 22:58:13.921740
9058 22:58:13.921810 CH 1, Rank 1
9059 22:58:13.924561 SW Impedance : PASS
9060 22:58:13.928042 DUTY Scan : NO K
9061 22:58:13.928146 ZQ Calibration : PASS
9062 22:58:13.931905 Jitter Meter : NO K
9063 22:58:13.934625 CBT Training : PASS
9064 22:58:13.934826 Write leveling : PASS
9065 22:58:13.938274 RX DQS gating : PASS
9066 22:58:13.941311 RX DQ/DQS(RDDQC) : PASS
9067 22:58:13.941511 TX DQ/DQS : PASS
9068 22:58:13.944777 RX DATLAT : PASS
9069 22:58:13.945034 RX DQ/DQS(Engine): PASS
9070 22:58:13.948027 TX OE : PASS
9071 22:58:13.948213 All Pass.
9072 22:58:13.948335
9073 22:58:13.951463 DramC Write-DBI on
9074 22:58:13.955109 PER_BANK_REFRESH: Hybrid Mode
9075 22:58:13.955399 TX_TRACKING: ON
9076 22:58:13.964816 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9077 22:58:13.971565 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9078 22:58:13.981351 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9079 22:58:13.984939 [FAST_K] Save calibration result to emmc
9080 22:58:13.985450 sync common calibartion params.
9081 22:58:13.987986 sync cbt_mode0:1, 1:1
9082 22:58:13.992012 dram_init: ddr_geometry: 2
9083 22:58:13.994631 dram_init: ddr_geometry: 2
9084 22:58:13.995053 dram_init: ddr_geometry: 2
9085 22:58:13.998179 0:dram_rank_size:100000000
9086 22:58:14.001702 1:dram_rank_size:100000000
9087 22:58:14.004891 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9088 22:58:14.008009 DFS_SHUFFLE_HW_MODE: ON
9089 22:58:14.011422 dramc_set_vcore_voltage set vcore to 725000
9090 22:58:14.014257 Read voltage for 1600, 0
9091 22:58:14.014678 Vio18 = 0
9092 22:58:14.017713 Vcore = 725000
9093 22:58:14.018133 Vdram = 0
9094 22:58:14.018471 Vddq = 0
9095 22:58:14.018785 Vmddr = 0
9096 22:58:14.021149 switch to 3200 Mbps bootup
9097 22:58:14.025047 [DramcRunTimeConfig]
9098 22:58:14.025656 PHYPLL
9099 22:58:14.027768 DPM_CONTROL_AFTERK: ON
9100 22:58:14.028396 PER_BANK_REFRESH: ON
9101 22:58:14.031684 REFRESH_OVERHEAD_REDUCTION: ON
9102 22:58:14.034281 CMD_PICG_NEW_MODE: OFF
9103 22:58:14.034746 XRTWTW_NEW_MODE: ON
9104 22:58:14.037998 XRTRTR_NEW_MODE: ON
9105 22:58:14.038527 TX_TRACKING: ON
9106 22:58:14.041032 RDSEL_TRACKING: OFF
9107 22:58:14.044503 DQS Precalculation for DVFS: ON
9108 22:58:14.044929 RX_TRACKING: OFF
9109 22:58:14.047484 HW_GATING DBG: ON
9110 22:58:14.047907 ZQCS_ENABLE_LP4: ON
9111 22:58:14.051195 RX_PICG_NEW_MODE: ON
9112 22:58:14.051660 TX_PICG_NEW_MODE: ON
9113 22:58:14.054167 ENABLE_RX_DCM_DPHY: ON
9114 22:58:14.057782 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9115 22:58:14.061207 DUMMY_READ_FOR_TRACKING: OFF
9116 22:58:14.061797 !!! SPM_CONTROL_AFTERK: OFF
9117 22:58:14.064544 !!! SPM could not control APHY
9118 22:58:14.068113 IMPEDANCE_TRACKING: ON
9119 22:58:14.068646 TEMP_SENSOR: ON
9120 22:58:14.070853 HW_SAVE_FOR_SR: OFF
9121 22:58:14.074638 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9122 22:58:14.077250 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9123 22:58:14.077724 Read ODT Tracking: ON
9124 22:58:14.081082 Refresh Rate DeBounce: ON
9125 22:58:14.084500 DFS_NO_QUEUE_FLUSH: ON
9126 22:58:14.087899 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9127 22:58:14.088430 ENABLE_DFS_RUNTIME_MRW: OFF
9128 22:58:14.091096 DDR_RESERVE_NEW_MODE: ON
9129 22:58:14.093941 MR_CBT_SWITCH_FREQ: ON
9130 22:58:14.094412 =========================
9131 22:58:14.114599 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9132 22:58:14.117490 dram_init: ddr_geometry: 2
9133 22:58:14.135921 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9134 22:58:14.139497 dram_init: dram init end (result: 0)
9135 22:58:14.146093 DRAM-K: Full calibration passed in 24453 msecs
9136 22:58:14.148992 MRC: failed to locate region type 0.
9137 22:58:14.149462 DRAM rank0 size:0x100000000,
9138 22:58:14.152411 DRAM rank1 size=0x100000000
9139 22:58:14.162364 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9140 22:58:14.169314 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9141 22:58:14.175696 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9142 22:58:14.182862 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9143 22:58:14.185729 DRAM rank0 size:0x100000000,
9144 22:58:14.189217 DRAM rank1 size=0x100000000
9145 22:58:14.189819 CBMEM:
9146 22:58:14.192976 IMD: root @ 0xfffff000 254 entries.
9147 22:58:14.195803 IMD: root @ 0xffffec00 62 entries.
9148 22:58:14.199498 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9149 22:58:14.202876 WARNING: RO_VPD is uninitialized or empty.
9150 22:58:14.209324 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9151 22:58:14.215824 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9152 22:58:14.228555 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9153 22:58:14.240494 BS: romstage times (exec / console): total (unknown) / 23986 ms
9154 22:58:14.241063
9155 22:58:14.241433
9156 22:58:14.249786 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9157 22:58:14.253263 ARM64: Exception handlers installed.
9158 22:58:14.256769 ARM64: Testing exception
9159 22:58:14.260455 ARM64: Done test exception
9160 22:58:14.261018 Enumerating buses...
9161 22:58:14.263173 Show all devs... Before device enumeration.
9162 22:58:14.266911 Root Device: enabled 1
9163 22:58:14.270552 CPU_CLUSTER: 0: enabled 1
9164 22:58:14.271119 CPU: 00: enabled 1
9165 22:58:14.273247 Compare with tree...
9166 22:58:14.273843 Root Device: enabled 1
9167 22:58:14.277206 CPU_CLUSTER: 0: enabled 1
9168 22:58:14.279801 CPU: 00: enabled 1
9169 22:58:14.280266 Root Device scanning...
9170 22:58:14.283357 scan_static_bus for Root Device
9171 22:58:14.286533 CPU_CLUSTER: 0 enabled
9172 22:58:14.290054 scan_static_bus for Root Device done
9173 22:58:14.293518 scan_bus: bus Root Device finished in 8 msecs
9174 22:58:14.294023 done
9175 22:58:14.300329 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9176 22:58:14.303291 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9177 22:58:14.309923 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9178 22:58:14.313695 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9179 22:58:14.316935 Allocating resources...
9180 22:58:14.319970 Reading resources...
9181 22:58:14.323088 Root Device read_resources bus 0 link: 0
9182 22:58:14.323617 DRAM rank0 size:0x100000000,
9183 22:58:14.326289 DRAM rank1 size=0x100000000
9184 22:58:14.329572 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9185 22:58:14.332907 CPU: 00 missing read_resources
9186 22:58:14.336510 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9187 22:58:14.342804 Root Device read_resources bus 0 link: 0 done
9188 22:58:14.343265 Done reading resources.
9189 22:58:14.349953 Show resources in subtree (Root Device)...After reading.
9190 22:58:14.352885 Root Device child on link 0 CPU_CLUSTER: 0
9191 22:58:14.356313 CPU_CLUSTER: 0 child on link 0 CPU: 00
9192 22:58:14.366526 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9193 22:58:14.367056 CPU: 00
9194 22:58:14.370018 Root Device assign_resources, bus 0 link: 0
9195 22:58:14.372695 CPU_CLUSTER: 0 missing set_resources
9196 22:58:14.376625 Root Device assign_resources, bus 0 link: 0 done
9197 22:58:14.379801 Done setting resources.
9198 22:58:14.386282 Show resources in subtree (Root Device)...After assigning values.
9199 22:58:14.389731 Root Device child on link 0 CPU_CLUSTER: 0
9200 22:58:14.393338 CPU_CLUSTER: 0 child on link 0 CPU: 00
9201 22:58:14.402950 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9202 22:58:14.403465 CPU: 00
9203 22:58:14.406132 Done allocating resources.
9204 22:58:14.409966 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9205 22:58:14.412843 Enabling resources...
9206 22:58:14.413364 done.
9207 22:58:14.419316 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9208 22:58:14.419744 Initializing devices...
9209 22:58:14.422416 Root Device init
9210 22:58:14.422839 init hardware done!
9211 22:58:14.426281 0x00000018: ctrlr->caps
9212 22:58:14.429638 52.000 MHz: ctrlr->f_max
9213 22:58:14.430163 0.400 MHz: ctrlr->f_min
9214 22:58:14.433193 0x40ff8080: ctrlr->voltages
9215 22:58:14.433779 sclk: 390625
9216 22:58:14.436570 Bus Width = 1
9217 22:58:14.436993 sclk: 390625
9218 22:58:14.437331 Bus Width = 1
9219 22:58:14.439383 Early init status = 3
9220 22:58:14.446196 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9221 22:58:14.449524 in-header: 03 fc 00 00 01 00 00 00
9222 22:58:14.449990 in-data: 00
9223 22:58:14.456204 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9224 22:58:14.459504 in-header: 03 fd 00 00 00 00 00 00
9225 22:58:14.459988 in-data:
9226 22:58:14.466080 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9227 22:58:14.469752 in-header: 03 fc 00 00 01 00 00 00
9228 22:58:14.472885 in-data: 00
9229 22:58:14.476310 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9230 22:58:14.480012 in-header: 03 fd 00 00 00 00 00 00
9231 22:58:14.483695 in-data:
9232 22:58:14.487427 [SSUSB] Setting up USB HOST controller...
9233 22:58:14.490282 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9234 22:58:14.493361 [SSUSB] phy power-on done.
9235 22:58:14.496708 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9236 22:58:14.503449 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9237 22:58:14.506864 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9238 22:58:14.513472 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9239 22:58:14.520396 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9240 22:58:14.526569 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9241 22:58:14.533124 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9242 22:58:14.540263 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9243 22:58:14.543076 SPM: binary array size = 0x9dc
9244 22:58:14.546247 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9245 22:58:14.552951 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9246 22:58:14.559487 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9247 22:58:14.563017 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9248 22:58:14.569665 configure_display: Starting display init
9249 22:58:14.603859 anx7625_power_on_init: Init interface.
9250 22:58:14.606514 anx7625_disable_pd_protocol: Disabled PD feature.
9251 22:58:14.609631 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9252 22:58:14.638122 anx7625_start_dp_work: Secure OCM version=00
9253 22:58:14.641667 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9254 22:58:14.655673 sp_tx_get_edid_block: EDID Block = 1
9255 22:58:14.758522 Extracted contents:
9256 22:58:14.761968 header: 00 ff ff ff ff ff ff 00
9257 22:58:14.765148 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9258 22:58:14.768837 version: 01 04
9259 22:58:14.771914 basic params: 95 1f 11 78 0a
9260 22:58:14.775105 chroma info: 76 90 94 55 54 90 27 21 50 54
9261 22:58:14.778559 established: 00 00 00
9262 22:58:14.785328 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9263 22:58:14.789016 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9264 22:58:14.795139 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9265 22:58:14.801899 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9266 22:58:14.808569 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9267 22:58:14.811886 extensions: 00
9268 22:58:14.812449 checksum: fb
9269 22:58:14.812826
9270 22:58:14.815266 Manufacturer: IVO Model 57d Serial Number 0
9271 22:58:14.818557 Made week 0 of 2020
9272 22:58:14.819025 EDID version: 1.4
9273 22:58:14.821364 Digital display
9274 22:58:14.824893 6 bits per primary color channel
9275 22:58:14.825369 DisplayPort interface
9276 22:58:14.828308 Maximum image size: 31 cm x 17 cm
9277 22:58:14.831413 Gamma: 220%
9278 22:58:14.831885 Check DPMS levels
9279 22:58:14.834562 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9280 22:58:14.837996 First detailed timing is preferred timing
9281 22:58:14.841256 Established timings supported:
9282 22:58:14.844397 Standard timings supported:
9283 22:58:14.847606 Detailed timings
9284 22:58:14.851460 Hex of detail: 383680a07038204018303c0035ae10000019
9285 22:58:14.854970 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9286 22:58:14.861101 0780 0798 07c8 0820 hborder 0
9287 22:58:14.864369 0438 043b 0447 0458 vborder 0
9288 22:58:14.868002 -hsync -vsync
9289 22:58:14.868562 Did detailed timing
9290 22:58:14.871444 Hex of detail: 000000000000000000000000000000000000
9291 22:58:14.874710 Manufacturer-specified data, tag 0
9292 22:58:14.880966 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9293 22:58:14.881419 ASCII string: InfoVision
9294 22:58:14.887950 Hex of detail: 000000fe00523134304e574635205248200a
9295 22:58:14.890839 ASCII string: R140NWF5 RH
9296 22:58:14.891279 Checksum
9297 22:58:14.894072 Checksum: 0xfb (valid)
9298 22:58:14.897285 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9299 22:58:14.901045 DSI data_rate: 832800000 bps
9300 22:58:14.907555 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9301 22:58:14.910940 anx7625_parse_edid: pixelclock(138800).
9302 22:58:14.914647 hactive(1920), hsync(48), hfp(24), hbp(88)
9303 22:58:14.917338 vactive(1080), vsync(12), vfp(3), vbp(17)
9304 22:58:14.920987 anx7625_dsi_config: config dsi.
9305 22:58:14.927477 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9306 22:58:14.940674 anx7625_dsi_config: success to config DSI
9307 22:58:14.944140 anx7625_dp_start: MIPI phy setup OK.
9308 22:58:14.947221 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9309 22:58:14.950509 mtk_ddp_mode_set invalid vrefresh 60
9310 22:58:14.953923 main_disp_path_setup
9311 22:58:14.954442 ovl_layer_smi_id_en
9312 22:58:14.957197 ovl_layer_smi_id_en
9313 22:58:14.957714 ccorr_config
9314 22:58:14.958089 aal_config
9315 22:58:14.960249 gamma_config
9316 22:58:14.960710 postmask_config
9317 22:58:14.963627 dither_config
9318 22:58:14.967103 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9319 22:58:14.973966 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9320 22:58:14.977079 Root Device init finished in 551 msecs
9321 22:58:14.977546 CPU_CLUSTER: 0 init
9322 22:58:14.987399 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9323 22:58:14.990464 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9324 22:58:14.993888 APU_MBOX 0x190000b0 = 0x10001
9325 22:58:14.997289 APU_MBOX 0x190001b0 = 0x10001
9326 22:58:15.000693 APU_MBOX 0x190005b0 = 0x10001
9327 22:58:15.003669 APU_MBOX 0x190006b0 = 0x10001
9328 22:58:15.006838 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9329 22:58:15.019669 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9330 22:58:15.032458 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9331 22:58:15.038485 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9332 22:58:15.050151 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9333 22:58:15.059191 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9334 22:58:15.062778 CPU_CLUSTER: 0 init finished in 81 msecs
9335 22:58:15.066214 Devices initialized
9336 22:58:15.069797 Show all devs... After init.
9337 22:58:15.070374 Root Device: enabled 1
9338 22:58:15.072750 CPU_CLUSTER: 0: enabled 1
9339 22:58:15.076338 CPU: 00: enabled 1
9340 22:58:15.079663 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9341 22:58:15.082525 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9342 22:58:15.085807 ELOG: NV offset 0x57f000 size 0x1000
9343 22:58:15.093014 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9344 22:58:15.099516 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9345 22:58:15.102973 ELOG: Event(17) added with size 13 at 2023-12-03 22:56:02 UTC
9346 22:58:15.106400 out: cmd=0x121: 03 db 21 01 00 00 00 00
9347 22:58:15.110076 in-header: 03 e6 00 00 2c 00 00 00
9348 22:58:15.123247 in-data: 79 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9349 22:58:15.129479 ELOG: Event(A1) added with size 10 at 2023-12-03 22:56:02 UTC
9350 22:58:15.136220 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9351 22:58:15.142524 ELOG: Event(A0) added with size 9 at 2023-12-03 22:56:02 UTC
9352 22:58:15.146201 elog_add_boot_reason: Logged dev mode boot
9353 22:58:15.149223 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9354 22:58:15.152982 Finalize devices...
9355 22:58:15.153542 Devices finalized
9356 22:58:15.159232 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9357 22:58:15.162357 Writing coreboot table at 0xffe64000
9358 22:58:15.165798 0. 000000000010a000-0000000000113fff: RAMSTAGE
9359 22:58:15.169708 1. 0000000040000000-00000000400fffff: RAM
9360 22:58:15.176138 2. 0000000040100000-000000004032afff: RAMSTAGE
9361 22:58:15.178899 3. 000000004032b000-00000000545fffff: RAM
9362 22:58:15.182241 4. 0000000054600000-000000005465ffff: BL31
9363 22:58:15.185819 5. 0000000054660000-00000000ffe63fff: RAM
9364 22:58:15.192455 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9365 22:58:15.195913 7. 0000000100000000-000000023fffffff: RAM
9366 22:58:15.196481 Passing 5 GPIOs to payload:
9367 22:58:15.202635 NAME | PORT | POLARITY | VALUE
9368 22:58:15.206078 EC in RW | 0x000000aa | low | undefined
9369 22:58:15.212534 EC interrupt | 0x00000005 | low | undefined
9370 22:58:15.215847 TPM interrupt | 0x000000ab | high | undefined
9371 22:58:15.218927 SD card detect | 0x00000011 | high | undefined
9372 22:58:15.225626 speaker enable | 0x00000093 | high | undefined
9373 22:58:15.228985 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9374 22:58:15.232513 in-header: 03 f9 00 00 02 00 00 00
9375 22:58:15.233075 in-data: 02 00
9376 22:58:15.235439 ADC[4]: Raw value=904357 ID=7
9377 22:58:15.238651 ADC[3]: Raw value=213441 ID=1
9378 22:58:15.239118 RAM Code: 0x71
9379 22:58:15.242608 ADC[6]: Raw value=75332 ID=0
9380 22:58:15.245801 ADC[5]: Raw value=212703 ID=1
9381 22:58:15.246365 SKU Code: 0x1
9382 22:58:15.252043 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 425c
9383 22:58:15.255421 coreboot table: 964 bytes.
9384 22:58:15.258858 IMD ROOT 0. 0xfffff000 0x00001000
9385 22:58:15.262324 IMD SMALL 1. 0xffffe000 0x00001000
9386 22:58:15.265709 RO MCACHE 2. 0xffffc000 0x00001104
9387 22:58:15.268963 CONSOLE 3. 0xfff7c000 0x00080000
9388 22:58:15.272268 FMAP 4. 0xfff7b000 0x00000452
9389 22:58:15.275514 TIME STAMP 5. 0xfff7a000 0x00000910
9390 22:58:15.279011 VBOOT WORK 6. 0xfff66000 0x00014000
9391 22:58:15.282300 RAMOOPS 7. 0xffe66000 0x00100000
9392 22:58:15.285929 COREBOOT 8. 0xffe64000 0x00002000
9393 22:58:15.286500 IMD small region:
9394 22:58:15.288943 IMD ROOT 0. 0xffffec00 0x00000400
9395 22:58:15.292203 VPD 1. 0xffffeb80 0x0000006c
9396 22:58:15.295679 MMC STATUS 2. 0xffffeb60 0x00000004
9397 22:58:15.302071 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9398 22:58:15.302626 Probing TPM: done!
9399 22:58:15.309434 Connected to device vid:did:rid of 1ae0:0028:00
9400 22:58:15.319384 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9401 22:58:15.323162 Initialized TPM device CR50 revision 0
9402 22:58:15.323739 Checking cr50 for pending updates
9403 22:58:15.329072 Reading cr50 TPM mode
9404 22:58:15.337846 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9405 22:58:15.344427 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9406 22:58:15.384395 read SPI 0x3990ec 0x4f1b0: 34847 us, 9298 KB/s, 74.384 Mbps
9407 22:58:15.387956 Checking segment from ROM address 0x40100000
9408 22:58:15.391136 Checking segment from ROM address 0x4010001c
9409 22:58:15.397760 Loading segment from ROM address 0x40100000
9410 22:58:15.398335 code (compression=0)
9411 22:58:15.404769 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9412 22:58:15.414282 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9413 22:58:15.414844 it's not compressed!
9414 22:58:15.421187 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9415 22:58:15.424613 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9416 22:58:15.445017 Loading segment from ROM address 0x4010001c
9417 22:58:15.445639 Entry Point 0x80000000
9418 22:58:15.448598 Loaded segments
9419 22:58:15.451285 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9420 22:58:15.458305 Jumping to boot code at 0x80000000(0xffe64000)
9421 22:58:15.464885 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9422 22:58:15.471347 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9423 22:58:15.479132 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9424 22:58:15.482713 Checking segment from ROM address 0x40100000
9425 22:58:15.485890 Checking segment from ROM address 0x4010001c
9426 22:58:15.489384 Loading segment from ROM address 0x40100000
9427 22:58:15.492699 code (compression=1)
9428 22:58:15.499302 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9429 22:58:15.509705 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9430 22:58:15.510251 using LZMA
9431 22:58:15.517507 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9432 22:58:15.523958 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9433 22:58:15.527788 Loading segment from ROM address 0x4010001c
9434 22:58:15.528209 Entry Point 0x54601000
9435 22:58:15.530981 Loaded segments
9436 22:58:15.534018 NOTICE: MT8192 bl31_setup
9437 22:58:15.541117 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9438 22:58:15.544548 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9439 22:58:15.547463 WARNING: region 0:
9440 22:58:15.550893 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9441 22:58:15.551317 WARNING: region 1:
9442 22:58:15.558086 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9443 22:58:15.560934 WARNING: region 2:
9444 22:58:15.564374 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9445 22:58:15.567684 WARNING: region 3:
9446 22:58:15.571169 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9447 22:58:15.574453 WARNING: region 4:
9448 22:58:15.577922 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9449 22:58:15.581293 WARNING: region 5:
9450 22:58:15.584683 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9451 22:58:15.588064 WARNING: region 6:
9452 22:58:15.591098 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9453 22:58:15.591525 WARNING: region 7:
9454 22:58:15.598457 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9455 22:58:15.604616 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9456 22:58:15.608025 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9457 22:58:15.610983 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9458 22:58:15.617624 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9459 22:58:15.621071 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9460 22:58:15.624599 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9461 22:58:15.631356 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9462 22:58:15.635060 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9463 22:58:15.637674 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9464 22:58:15.644692 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9465 22:58:15.647731 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9466 22:58:15.651539 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9467 22:58:15.658191 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9468 22:58:15.661451 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9469 22:58:15.668087 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9470 22:58:15.671527 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9471 22:58:15.675027 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9472 22:58:15.681499 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9473 22:58:15.684762 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9474 22:58:15.688096 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9475 22:58:15.694766 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9476 22:58:15.698092 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9477 22:58:15.704543 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9478 22:58:15.708340 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9479 22:58:15.711274 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9480 22:58:15.718289 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9481 22:58:15.721440 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9482 22:58:15.727887 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9483 22:58:15.731666 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9484 22:58:15.734639 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9485 22:58:15.741670 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9486 22:58:15.744711 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9487 22:58:15.748270 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9488 22:58:15.754940 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9489 22:58:15.758194 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9490 22:58:15.761861 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9491 22:58:15.764806 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9492 22:58:15.771623 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9493 22:58:15.774816 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9494 22:58:15.778015 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9495 22:58:15.781790 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9496 22:58:15.785085 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9497 22:58:15.791633 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9498 22:58:15.795214 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9499 22:58:15.798504 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9500 22:58:15.805055 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9501 22:58:15.808286 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9502 22:58:15.812039 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9503 22:58:15.818488 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9504 22:58:15.821706 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9505 22:58:15.825085 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9506 22:58:15.831671 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9507 22:58:15.835019 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9508 22:58:15.841663 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9509 22:58:15.845186 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9510 22:58:15.848484 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9511 22:58:15.855110 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9512 22:58:15.858712 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9513 22:58:15.865247 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9514 22:58:15.868557 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9515 22:58:15.875236 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9516 22:58:15.878253 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9517 22:58:15.884818 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9518 22:58:15.888486 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9519 22:58:15.891483 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9520 22:58:15.898367 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9521 22:58:15.901549 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9522 22:58:15.908329 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9523 22:58:15.911559 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9524 22:58:15.915093 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9525 22:58:15.921703 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9526 22:58:15.925196 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9527 22:58:15.931662 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9528 22:58:15.935210 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9529 22:58:15.941665 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9530 22:58:15.945318 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9531 22:58:15.951828 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9532 22:58:15.954923 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9533 22:58:15.958695 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9534 22:58:15.964944 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9535 22:58:15.968459 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9536 22:58:15.975000 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9537 22:58:15.978411 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9538 22:58:15.981982 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9539 22:58:15.988700 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9540 22:58:15.992303 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9541 22:58:15.998669 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9542 22:58:16.002105 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9543 22:58:16.008749 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9544 22:58:16.012118 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9545 22:58:16.015231 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9546 22:58:16.021845 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9547 22:58:16.025221 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9548 22:58:16.032355 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9549 22:58:16.035431 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9550 22:58:16.041907 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9551 22:58:16.045428 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9552 22:58:16.049028 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9553 22:58:16.051999 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9554 22:58:16.058965 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9555 22:58:16.062376 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9556 22:58:16.065210 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9557 22:58:16.072322 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9558 22:58:16.075258 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9559 22:58:16.082358 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9560 22:58:16.085488 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9561 22:58:16.088465 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9562 22:58:16.095046 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9563 22:58:16.099009 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9564 22:58:16.105299 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9565 22:58:16.108286 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9566 22:58:16.111719 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9567 22:58:16.118709 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9568 22:58:16.121908 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9569 22:58:16.128894 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9570 22:58:16.131956 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9571 22:58:16.135190 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9572 22:58:16.138605 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9573 22:58:16.145700 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9574 22:58:16.149101 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9575 22:58:16.152247 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9576 22:58:16.155784 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9577 22:58:16.162174 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9578 22:58:16.165479 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9579 22:58:16.168909 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9580 22:58:16.175417 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9581 22:58:16.178888 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9582 22:58:16.185096 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9583 22:58:16.188738 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9584 22:58:16.192321 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9585 22:58:16.199023 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9586 22:58:16.202051 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9587 22:58:16.205635 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9588 22:58:16.212193 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9589 22:58:16.215126 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9590 22:58:16.222106 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9591 22:58:16.225237 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9592 22:58:16.228725 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9593 22:58:16.235039 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9594 22:58:16.238527 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9595 22:58:16.242166 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9596 22:58:16.248861 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9597 22:58:16.251913 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9598 22:58:16.258570 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9599 22:58:16.262281 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9600 22:58:16.265105 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9601 22:58:16.271906 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9602 22:58:16.275259 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9603 22:58:16.281794 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9604 22:58:16.285536 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9605 22:58:16.288430 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9606 22:58:16.294997 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9607 22:58:16.298710 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9608 22:58:16.302388 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9609 22:58:16.308488 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9610 22:58:16.311913 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9611 22:58:16.318868 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9612 22:58:16.321830 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9613 22:58:16.325056 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9614 22:58:16.331856 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9615 22:58:16.335217 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9616 22:58:16.341712 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9617 22:58:16.345387 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9618 22:58:16.348878 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9619 22:58:16.355125 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9620 22:58:16.358423 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9621 22:58:16.361984 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9622 22:58:16.368647 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9623 22:58:16.371598 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9624 22:58:16.378318 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9625 22:58:16.381672 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9626 22:58:16.388330 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9627 22:58:16.391877 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9628 22:58:16.394870 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9629 22:58:16.401336 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9630 22:58:16.404821 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9631 22:58:16.408650 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9632 22:58:16.414927 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9633 22:58:16.418384 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9634 22:58:16.425033 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9635 22:58:16.428423 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9636 22:58:16.431947 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9637 22:58:16.438470 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9638 22:58:16.441444 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9639 22:58:16.448252 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9640 22:58:16.451778 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9641 22:58:16.454720 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9642 22:58:16.461959 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9643 22:58:16.464944 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9644 22:58:16.471175 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9645 22:58:16.474767 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9646 22:58:16.478324 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9647 22:58:16.484877 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9648 22:58:16.487966 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9649 22:58:16.494280 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9650 22:58:16.498095 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9651 22:58:16.501135 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9652 22:58:16.507598 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9653 22:58:16.511046 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9654 22:58:16.517718 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9655 22:58:16.521149 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9656 22:58:16.524334 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9657 22:58:16.530946 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9658 22:58:16.534326 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9659 22:58:16.540787 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9660 22:58:16.544255 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9661 22:58:16.551459 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9662 22:58:16.554246 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9663 22:58:16.557710 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9664 22:58:16.564350 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9665 22:58:16.567819 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9666 22:58:16.574144 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9667 22:58:16.577610 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9668 22:58:16.584435 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9669 22:58:16.587547 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9670 22:58:16.590745 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9671 22:58:16.597722 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9672 22:58:16.600590 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9673 22:58:16.607301 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9674 22:58:16.611481 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9675 22:58:16.614149 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9676 22:58:16.620891 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9677 22:58:16.624024 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9678 22:58:16.630484 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9679 22:58:16.634177 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9680 22:58:16.637465 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9681 22:58:16.643842 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9682 22:58:16.647465 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9683 22:58:16.654023 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9684 22:58:16.657787 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9685 22:58:16.660735 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9686 22:58:16.664270 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9687 22:58:16.670639 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9688 22:58:16.674142 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9689 22:58:16.677219 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9690 22:58:16.683828 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9691 22:58:16.687526 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9692 22:58:16.690781 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9693 22:58:16.697196 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9694 22:58:16.700646 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9695 22:58:16.703548 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9696 22:58:16.710444 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9697 22:58:16.713965 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9698 22:58:16.717464 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9699 22:58:16.723463 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9700 22:58:16.726986 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9701 22:58:16.734091 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9702 22:58:16.736907 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9703 22:58:16.740327 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9704 22:58:16.747481 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9705 22:58:16.750274 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9706 22:58:16.753833 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9707 22:58:16.760135 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9708 22:58:16.763494 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9709 22:58:16.766794 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9710 22:58:16.773712 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9711 22:58:16.776680 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9712 22:58:16.783312 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9713 22:58:16.786438 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9714 22:58:16.789921 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9715 22:58:16.796726 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9716 22:58:16.800168 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9717 22:58:16.806521 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9718 22:58:16.809692 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9719 22:58:16.813350 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9720 22:58:16.819847 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9721 22:58:16.823415 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9722 22:58:16.826352 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9723 22:58:16.833244 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9724 22:58:16.836764 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9725 22:58:16.839690 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9726 22:58:16.842960 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9727 22:58:16.846231 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9728 22:58:16.853269 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9729 22:58:16.856310 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9730 22:58:16.859640 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9731 22:58:16.862761 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9732 22:58:16.869475 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9733 22:58:16.872822 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9734 22:58:16.875980 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9735 22:58:16.883258 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9736 22:58:16.886159 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9737 22:58:16.889474 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9738 22:58:16.895929 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9739 22:58:16.899278 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9740 22:58:16.906528 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9741 22:58:16.909297 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9742 22:58:16.912935 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9743 22:58:16.919318 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9744 22:58:16.922596 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9745 22:58:16.929850 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9746 22:58:16.932671 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9747 22:58:16.936343 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9748 22:58:16.942847 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9749 22:58:16.945961 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9750 22:58:16.952590 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9751 22:58:16.956142 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9752 22:58:16.959911 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9753 22:58:16.966399 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9754 22:58:16.969485 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9755 22:58:16.976193 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9756 22:58:16.979670 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9757 22:58:16.982656 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9758 22:58:16.989240 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9759 22:58:16.993165 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9760 22:58:16.999466 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9761 22:58:17.002554 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9762 22:58:17.005960 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9763 22:58:17.012573 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9764 22:58:17.015982 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9765 22:58:17.022483 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9766 22:58:17.025778 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9767 22:58:17.032763 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9768 22:58:17.036184 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9769 22:58:17.039227 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9770 22:58:17.045591 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9771 22:58:17.049295 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9772 22:58:17.055808 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9773 22:58:17.059300 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9774 22:58:17.062751 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9775 22:58:17.069443 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9776 22:58:17.072791 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9777 22:58:17.075959 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9778 22:58:17.082399 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9779 22:58:17.086045 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9780 22:58:17.092616 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9781 22:58:17.095619 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9782 22:58:17.102623 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9783 22:58:17.105498 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9784 22:58:17.108893 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9785 22:58:17.115951 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9786 22:58:17.118887 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9787 22:58:17.125957 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9788 22:58:17.129219 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9789 22:58:17.132815 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9790 22:58:17.139047 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9791 22:58:17.142585 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9792 22:58:17.146188 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9793 22:58:17.152238 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9794 22:58:17.155555 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9795 22:58:17.162664 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9796 22:58:17.165594 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9797 22:58:17.172094 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9798 22:58:17.175748 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9799 22:58:17.182141 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9800 22:58:17.185324 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9801 22:58:17.188854 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9802 22:58:17.195241 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9803 22:58:17.198853 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9804 22:58:17.202515 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9805 22:58:17.208939 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9806 22:58:17.211801 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9807 22:58:17.218753 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9808 22:58:17.221955 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9809 22:58:17.228230 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9810 22:58:17.231829 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9811 22:58:17.235104 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9812 22:58:17.242397 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9813 22:58:17.245416 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9814 22:58:17.252273 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9815 22:58:17.255061 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9816 22:58:17.261887 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9817 22:58:17.265356 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9818 22:58:17.268132 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9819 22:58:17.275121 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9820 22:58:17.278154 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9821 22:58:17.285242 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9822 22:58:17.288133 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9823 22:58:17.295044 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9824 22:58:17.298005 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9825 22:58:17.301470 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9826 22:58:17.308340 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9827 22:58:17.311301 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9828 22:58:17.318397 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9829 22:58:17.321827 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9830 22:58:17.328223 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9831 22:58:17.331446 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9832 22:58:17.334572 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9833 22:58:17.341295 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9834 22:58:17.345017 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9835 22:58:17.351415 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9836 22:58:17.354848 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9837 22:58:17.361535 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9838 22:58:17.364564 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9839 22:58:17.371205 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9840 22:58:17.374779 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9841 22:58:17.378190 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9842 22:58:17.384699 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9843 22:58:17.388190 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9844 22:58:17.394681 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9845 22:58:17.398085 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9846 22:58:17.404337 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9847 22:58:17.407477 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9848 22:58:17.411178 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9849 22:58:17.417743 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9850 22:58:17.421299 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9851 22:58:17.427591 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9852 22:58:17.430517 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9853 22:58:17.437530 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9854 22:58:17.440369 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9855 22:58:17.447510 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9856 22:58:17.450917 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9857 22:58:17.454099 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9858 22:58:17.460792 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9859 22:58:17.463718 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9860 22:58:17.470678 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9861 22:58:17.473931 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9862 22:58:17.480331 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9863 22:58:17.483717 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9864 22:58:17.490522 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9865 22:58:17.493458 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9866 22:58:17.500102 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9867 22:58:17.503657 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9868 22:58:17.510445 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9869 22:58:17.513629 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9870 22:58:17.519873 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9871 22:58:17.523724 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9872 22:58:17.530023 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9873 22:58:17.533166 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9874 22:58:17.539698 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9875 22:58:17.543499 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9876 22:58:17.550017 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9877 22:58:17.553522 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9878 22:58:17.556629 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9879 22:58:17.562970 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9880 22:58:17.570054 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9881 22:58:17.573335 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9882 22:58:17.576744 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9883 22:58:17.583436 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9884 22:58:17.590151 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9885 22:58:17.593061 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9886 22:58:17.599605 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9887 22:58:17.603144 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9888 22:58:17.609875 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9889 22:58:17.613034 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9890 22:58:17.613116 INFO: [APUAPC] vio 0
9891 22:58:17.620564 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9892 22:58:17.623560 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9893 22:58:17.627066 INFO: [APUAPC] D0_APC_0: 0x400510
9894 22:58:17.630304 INFO: [APUAPC] D0_APC_1: 0x0
9895 22:58:17.634065 INFO: [APUAPC] D0_APC_2: 0x1540
9896 22:58:17.636854 INFO: [APUAPC] D0_APC_3: 0x0
9897 22:58:17.640455 INFO: [APUAPC] D1_APC_0: 0xffffffff
9898 22:58:17.643435 INFO: [APUAPC] D1_APC_1: 0xffffffff
9899 22:58:17.646910 INFO: [APUAPC] D1_APC_2: 0x3fffff
9900 22:58:17.650083 INFO: [APUAPC] D1_APC_3: 0x0
9901 22:58:17.653449 INFO: [APUAPC] D2_APC_0: 0xffffffff
9902 22:58:17.656686 INFO: [APUAPC] D2_APC_1: 0xffffffff
9903 22:58:17.660265 INFO: [APUAPC] D2_APC_2: 0x3fffff
9904 22:58:17.663705 INFO: [APUAPC] D2_APC_3: 0x0
9905 22:58:17.666713 INFO: [APUAPC] D3_APC_0: 0xffffffff
9906 22:58:17.670237 INFO: [APUAPC] D3_APC_1: 0xffffffff
9907 22:58:17.673553 INFO: [APUAPC] D3_APC_2: 0x3fffff
9908 22:58:17.676582 INFO: [APUAPC] D3_APC_3: 0x0
9909 22:58:17.679970 INFO: [APUAPC] D4_APC_0: 0xffffffff
9910 22:58:17.683488 INFO: [APUAPC] D4_APC_1: 0xffffffff
9911 22:58:17.686339 INFO: [APUAPC] D4_APC_2: 0x3fffff
9912 22:58:17.686420 INFO: [APUAPC] D4_APC_3: 0x0
9913 22:58:17.693020 INFO: [APUAPC] D5_APC_0: 0xffffffff
9914 22:58:17.696375 INFO: [APUAPC] D5_APC_1: 0xffffffff
9915 22:58:17.700085 INFO: [APUAPC] D5_APC_2: 0x3fffff
9916 22:58:17.700167 INFO: [APUAPC] D5_APC_3: 0x0
9917 22:58:17.702937 INFO: [APUAPC] D6_APC_0: 0xffffffff
9918 22:58:17.706253 INFO: [APUAPC] D6_APC_1: 0xffffffff
9919 22:58:17.709857 INFO: [APUAPC] D6_APC_2: 0x3fffff
9920 22:58:17.713194 INFO: [APUAPC] D6_APC_3: 0x0
9921 22:58:17.716547 INFO: [APUAPC] D7_APC_0: 0xffffffff
9922 22:58:17.719843 INFO: [APUAPC] D7_APC_1: 0xffffffff
9923 22:58:17.722882 INFO: [APUAPC] D7_APC_2: 0x3fffff
9924 22:58:17.726454 INFO: [APUAPC] D7_APC_3: 0x0
9925 22:58:17.729702 INFO: [APUAPC] D8_APC_0: 0xffffffff
9926 22:58:17.732951 INFO: [APUAPC] D8_APC_1: 0xffffffff
9927 22:58:17.736381 INFO: [APUAPC] D8_APC_2: 0x3fffff
9928 22:58:17.739349 INFO: [APUAPC] D8_APC_3: 0x0
9929 22:58:17.743000 INFO: [APUAPC] D9_APC_0: 0xffffffff
9930 22:58:17.746280 INFO: [APUAPC] D9_APC_1: 0xffffffff
9931 22:58:17.749340 INFO: [APUAPC] D9_APC_2: 0x3fffff
9932 22:58:17.752940 INFO: [APUAPC] D9_APC_3: 0x0
9933 22:58:17.756055 INFO: [APUAPC] D10_APC_0: 0xffffffff
9934 22:58:17.759457 INFO: [APUAPC] D10_APC_1: 0xffffffff
9935 22:58:17.762872 INFO: [APUAPC] D10_APC_2: 0x3fffff
9936 22:58:17.765904 INFO: [APUAPC] D10_APC_3: 0x0
9937 22:58:17.769283 INFO: [APUAPC] D11_APC_0: 0xffffffff
9938 22:58:17.772771 INFO: [APUAPC] D11_APC_1: 0xffffffff
9939 22:58:17.776086 INFO: [APUAPC] D11_APC_2: 0x3fffff
9940 22:58:17.779596 INFO: [APUAPC] D11_APC_3: 0x0
9941 22:58:17.782770 INFO: [APUAPC] D12_APC_0: 0xffffffff
9942 22:58:17.786024 INFO: [APUAPC] D12_APC_1: 0xffffffff
9943 22:58:17.789475 INFO: [APUAPC] D12_APC_2: 0x3fffff
9944 22:58:17.792976 INFO: [APUAPC] D12_APC_3: 0x0
9945 22:58:17.795918 INFO: [APUAPC] D13_APC_0: 0xffffffff
9946 22:58:17.799509 INFO: [APUAPC] D13_APC_1: 0xffffffff
9947 22:58:17.802375 INFO: [APUAPC] D13_APC_2: 0x3fffff
9948 22:58:17.805768 INFO: [APUAPC] D13_APC_3: 0x0
9949 22:58:17.809174 INFO: [APUAPC] D14_APC_0: 0xffffffff
9950 22:58:17.812642 INFO: [APUAPC] D14_APC_1: 0xffffffff
9951 22:58:17.815656 INFO: [APUAPC] D14_APC_2: 0x3fffff
9952 22:58:17.819067 INFO: [APUAPC] D14_APC_3: 0x0
9953 22:58:17.822840 INFO: [APUAPC] D15_APC_0: 0xffffffff
9954 22:58:17.825906 INFO: [APUAPC] D15_APC_1: 0xffffffff
9955 22:58:17.829111 INFO: [APUAPC] D15_APC_2: 0x3fffff
9956 22:58:17.832458 INFO: [APUAPC] D15_APC_3: 0x0
9957 22:58:17.835986 INFO: [APUAPC] APC_CON: 0x4
9958 22:58:17.839302 INFO: [NOCDAPC] D0_APC_0: 0x0
9959 22:58:17.842096 INFO: [NOCDAPC] D0_APC_1: 0x0
9960 22:58:17.845744 INFO: [NOCDAPC] D1_APC_0: 0x0
9961 22:58:17.849323 INFO: [NOCDAPC] D1_APC_1: 0xfff
9962 22:58:17.852179 INFO: [NOCDAPC] D2_APC_0: 0x0
9963 22:58:17.855836 INFO: [NOCDAPC] D2_APC_1: 0xfff
9964 22:58:17.855914 INFO: [NOCDAPC] D3_APC_0: 0x0
9965 22:58:17.858682 INFO: [NOCDAPC] D3_APC_1: 0xfff
9966 22:58:17.862167 INFO: [NOCDAPC] D4_APC_0: 0x0
9967 22:58:17.865767 INFO: [NOCDAPC] D4_APC_1: 0xfff
9968 22:58:17.868837 INFO: [NOCDAPC] D5_APC_0: 0x0
9969 22:58:17.872087 INFO: [NOCDAPC] D5_APC_1: 0xfff
9970 22:58:17.875290 INFO: [NOCDAPC] D6_APC_0: 0x0
9971 22:58:17.878842 INFO: [NOCDAPC] D6_APC_1: 0xfff
9972 22:58:17.881881 INFO: [NOCDAPC] D7_APC_0: 0x0
9973 22:58:17.885912 INFO: [NOCDAPC] D7_APC_1: 0xfff
9974 22:58:17.885990 INFO: [NOCDAPC] D8_APC_0: 0x0
9975 22:58:17.888644 INFO: [NOCDAPC] D8_APC_1: 0xfff
9976 22:58:17.891931 INFO: [NOCDAPC] D9_APC_0: 0x0
9977 22:58:17.895463 INFO: [NOCDAPC] D9_APC_1: 0xfff
9978 22:58:17.898473 INFO: [NOCDAPC] D10_APC_0: 0x0
9979 22:58:17.901976 INFO: [NOCDAPC] D10_APC_1: 0xfff
9980 22:58:17.905471 INFO: [NOCDAPC] D11_APC_0: 0x0
9981 22:58:17.908572 INFO: [NOCDAPC] D11_APC_1: 0xfff
9982 22:58:17.912105 INFO: [NOCDAPC] D12_APC_0: 0x0
9983 22:58:17.915318 INFO: [NOCDAPC] D12_APC_1: 0xfff
9984 22:58:17.918555 INFO: [NOCDAPC] D13_APC_0: 0x0
9985 22:58:17.922176 INFO: [NOCDAPC] D13_APC_1: 0xfff
9986 22:58:17.925490 INFO: [NOCDAPC] D14_APC_0: 0x0
9987 22:58:17.929070 INFO: [NOCDAPC] D14_APC_1: 0xfff
9988 22:58:17.929152 INFO: [NOCDAPC] D15_APC_0: 0x0
9989 22:58:17.931896 INFO: [NOCDAPC] D15_APC_1: 0xfff
9990 22:58:17.935173 INFO: [NOCDAPC] APC_CON: 0x4
9991 22:58:17.938728 INFO: [APUAPC] set_apusys_apc done
9992 22:58:17.942350 INFO: [DEVAPC] devapc_init done
9993 22:58:17.945332 INFO: GICv3 without legacy support detected.
9994 22:58:17.952016 INFO: ARM GICv3 driver initialized in EL3
9995 22:58:17.955671 INFO: Maximum SPI INTID supported: 639
9996 22:58:17.958727 INFO: BL31: Initializing runtime services
9997 22:58:17.965525 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9998 22:58:17.968577 INFO: SPM: enable CPC mode
9999 22:58:17.972110 INFO: mcdi ready for mcusys-off-idle and system suspend
10000 22:58:17.975678 INFO: BL31: Preparing for EL3 exit to normal world
10001 22:58:17.982242 INFO: Entry point address = 0x80000000
10002 22:58:17.982323 INFO: SPSR = 0x8
10003 22:58:17.988329
10004 22:58:17.988410
10005 22:58:17.988475
10006 22:58:17.991951 Starting depthcharge on Spherion...
10007 22:58:17.992060
10008 22:58:17.992157 Wipe memory regions:
10009 22:58:17.992237
10010 22:58:17.992903 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
10011 22:58:17.993004 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10012 22:58:17.993086 Setting prompt string to ['asurada:']
10013 22:58:17.993164 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10014 22:58:17.994913 [0x00000040000000, 0x00000054600000)
10015 22:58:18.117358
10016 22:58:18.117491 [0x00000054660000, 0x00000080000000)
10017 22:58:18.377768
10018 22:58:18.377899 [0x000000821a7280, 0x000000ffe64000)
10019 22:58:19.121998
10020 22:58:19.122142 [0x00000100000000, 0x00000240000000)
10021 22:58:21.011044
10022 22:58:21.014325 Initializing XHCI USB controller at 0x11200000.
10023 22:58:22.053426
10024 22:58:22.056800 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10025 22:58:22.056884
10026 22:58:22.056967
10027 22:58:22.057031
10028 22:58:22.057315 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10030 22:58:22.157626 asurada: tftpboot 192.168.201.1 12172390/tftp-deploy-rtufekp4/kernel/image.itb 12172390/tftp-deploy-rtufekp4/kernel/cmdline
10031 22:58:22.157816 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10032 22:58:22.157989 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10033 22:58:22.162653 tftpboot 192.168.201.1 12172390/tftp-deploy-rtufekp4/kernel/image.ittp-deploy-rtufekp4/kernel/cmdline
10034 22:58:22.162737
10035 22:58:22.162811 Waiting for link
10036 22:58:22.323037
10037 22:58:22.323174 R8152: Initializing
10038 22:58:22.323245
10039 22:58:22.326225 Version 9 (ocp_data = 6010)
10040 22:58:22.326302
10041 22:58:22.329654 R8152: Done initializing
10042 22:58:22.329737
10043 22:58:22.329803 Adding net device
10044 22:58:24.212088
10045 22:58:24.212248 done.
10046 22:58:24.212324
10047 22:58:24.212387 MAC: 00:e0:4c:78:7a:aa
10048 22:58:24.212451
10049 22:58:24.215418 Sending DHCP discover... done.
10050 22:58:24.215501
10051 22:58:24.219315 Waiting for reply... done.
10052 22:58:24.219403
10053 22:58:24.221938 Sending DHCP request... done.
10054 22:58:24.222027
10055 22:58:24.243679 Waiting for reply... done.
10056 22:58:24.243770
10057 22:58:24.243836 My ip is 192.168.201.12
10058 22:58:24.243899
10059 22:58:24.246329 The DHCP server ip is 192.168.201.1
10060 22:58:24.246416
10061 22:58:24.253052 TFTP server IP predefined by user: 192.168.201.1
10062 22:58:24.253182
10063 22:58:24.259848 Bootfile predefined by user: 12172390/tftp-deploy-rtufekp4/kernel/image.itb
10064 22:58:24.259940
10065 22:58:24.262850 Sending tftp read request... done.
10066 22:58:24.262938
10067 22:58:24.267039 Waiting for the transfer...
10068 22:58:24.267131
10069 22:58:24.526038 00000000 ################################################################
10070 22:58:24.526179
10071 22:58:24.786383 00080000 ################################################################
10072 22:58:24.786531
10073 22:58:25.043736 00100000 ################################################################
10074 22:58:25.043948
10075 22:58:25.300683 00180000 ################################################################
10076 22:58:25.300829
10077 22:58:25.556987 00200000 ################################################################
10078 22:58:25.557133
10079 22:58:25.819352 00280000 ################################################################
10080 22:58:25.819500
10081 22:58:26.075645 00300000 ################################################################
10082 22:58:26.075791
10083 22:58:26.332018 00380000 ################################################################
10084 22:58:26.332163
10085 22:58:26.589824 00400000 ################################################################
10086 22:58:26.589967
10087 22:58:26.849705 00480000 ################################################################
10088 22:58:26.849854
10089 22:58:27.107245 00500000 ################################################################
10090 22:58:27.107413
10091 22:58:27.365961 00580000 ################################################################
10092 22:58:27.366104
10093 22:58:27.622303 00600000 ################################################################
10094 22:58:27.622465
10095 22:58:27.877584 00680000 ################################################################
10096 22:58:27.877741
10097 22:58:28.134575 00700000 ################################################################
10098 22:58:28.134753
10099 22:58:28.390921 00780000 ################################################################
10100 22:58:28.391065
10101 22:58:28.648462 00800000 ################################################################
10102 22:58:28.648639
10103 22:58:28.905186 00880000 ################################################################
10104 22:58:28.905349
10105 22:58:29.163236 00900000 ################################################################
10106 22:58:29.163394
10107 22:58:29.418579 00980000 ################################################################
10108 22:58:29.418712
10109 22:58:29.674955 00a00000 ################################################################
10110 22:58:29.675098
10111 22:58:29.933604 00a80000 ################################################################
10112 22:58:29.933766
10113 22:58:30.189770 00b00000 ################################################################
10114 22:58:30.189932
10115 22:58:30.448281 00b80000 ################################################################
10116 22:58:30.448414
10117 22:58:30.713535 00c00000 ################################################################
10118 22:58:30.713710
10119 22:58:30.970328 00c80000 ################################################################
10120 22:58:30.970488
10121 22:58:31.224526 00d00000 ################################################################
10122 22:58:31.224661
10123 22:58:31.476663 00d80000 ################################################################
10124 22:58:31.476810
10125 22:58:31.727726 00e00000 ################################################################
10126 22:58:31.727865
10127 22:58:31.980407 00e80000 ################################################################
10128 22:58:31.980553
10129 22:58:32.244607 00f00000 ################################################################
10130 22:58:32.244749
10131 22:58:32.503071 00f80000 ################################################################
10132 22:58:32.503242
10133 22:58:32.756068 01000000 ################################################################
10134 22:58:32.756202
10135 22:58:33.015963 01080000 ################################################################
10136 22:58:33.016130
10137 22:58:33.275871 01100000 ################################################################
10138 22:58:33.276043
10139 22:58:33.534507 01180000 ################################################################
10140 22:58:33.534665
10141 22:58:33.789742 01200000 ################################################################
10142 22:58:33.789874
10143 22:58:34.048179 01280000 ################################################################
10144 22:58:34.048350
10145 22:58:34.302667 01300000 ################################################################
10146 22:58:34.302818
10147 22:58:34.558272 01380000 ################################################################
10148 22:58:34.558439
10149 22:58:34.813493 01400000 ################################################################
10150 22:58:34.813676
10151 22:58:35.070431 01480000 ################################################################
10152 22:58:35.070629
10153 22:58:35.329654 01500000 ################################################################
10154 22:58:35.329794
10155 22:58:35.583648 01580000 ################################################################
10156 22:58:35.583815
10157 22:58:35.840764 01600000 ################################################################
10158 22:58:35.840911
10159 22:58:36.112229 01680000 ################################################################
10160 22:58:36.112395
10161 22:58:36.378019 01700000 ################################################################
10162 22:58:36.378155
10163 22:58:36.634771 01780000 ################################################################
10164 22:58:36.634909
10165 22:58:36.891652 01800000 ################################################################
10166 22:58:36.891825
10167 22:58:37.147403 01880000 ################################################################
10168 22:58:37.147569
10169 22:58:37.408274 01900000 ################################################################
10170 22:58:37.408452
10171 22:58:37.666020 01980000 ################################################################
10172 22:58:37.666170
10173 22:58:37.917811 01a00000 ################################################################
10174 22:58:37.917960
10175 22:58:38.171938 01a80000 ################################################################
10176 22:58:38.172116
10177 22:58:38.426655 01b00000 ################################################################
10178 22:58:38.426810
10179 22:58:38.675373 01b80000 ################################################################
10180 22:58:38.675531
10181 22:58:38.927104 01c00000 ################################################################
10182 22:58:38.927247
10183 22:58:39.181719 01c80000 ################################################################
10184 22:58:39.181861
10185 22:58:39.438294 01d00000 ################################################################
10186 22:58:39.438459
10187 22:58:39.696075 01d80000 ################################################################
10188 22:58:39.696222
10189 22:58:39.952279 01e00000 ################################################################
10190 22:58:39.952440
10191 22:58:40.208198 01e80000 ################################################################
10192 22:58:40.208380
10193 22:58:40.463727 01f00000 ################################################################
10194 22:58:40.463877
10195 22:58:40.721163 01f80000 ################################################################
10196 22:58:40.721332
10197 22:58:40.976511 02000000 ################################################################
10198 22:58:40.976661
10199 22:58:41.233693 02080000 ################################################################
10200 22:58:41.233835
10201 22:58:41.495545 02100000 ################################################################
10202 22:58:41.495714
10203 22:58:41.759097 02180000 ################################################################
10204 22:58:41.759276
10205 22:58:42.011851 02200000 ################################################################
10206 22:58:42.011999
10207 22:58:42.264708 02280000 ################################################################
10208 22:58:42.264891
10209 22:58:42.517343 02300000 ################################################################
10210 22:58:42.517503
10211 22:58:42.769571 02380000 ################################################################
10212 22:58:42.769714
10213 22:58:43.020084 02400000 ################################################################
10214 22:58:43.020229
10215 22:58:43.278188 02480000 ################################################################
10216 22:58:43.278348
10217 22:58:43.531906 02500000 ################################################################
10218 22:58:43.532083
10219 22:58:43.787102 02580000 ################################################################
10220 22:58:43.787389
10221 22:58:44.046744 02600000 ################################################################
10222 22:58:44.046890
10223 22:58:44.305801 02680000 ################################################################
10224 22:58:44.305964
10225 22:58:44.591815 02700000 ################################################################
10226 22:58:44.591964
10227 22:58:44.879038 02780000 ################################################################
10228 22:58:44.879180
10229 22:58:45.129098 02800000 ################################################################
10230 22:58:45.129246
10231 22:58:45.384733 02880000 ################################################################
10232 22:58:45.384879
10233 22:58:45.635251 02900000 ################################################################
10234 22:58:45.635412
10235 22:58:45.885480 02980000 ################################################################
10236 22:58:45.885661
10237 22:58:46.135811 02a00000 ################################################################
10238 22:58:46.135950
10239 22:58:46.385269 02a80000 ################################################################
10240 22:58:46.385415
10241 22:58:46.635531 02b00000 ################################################################
10242 22:58:46.635673
10243 22:58:46.886019 02b80000 ################################################################
10244 22:58:46.886191
10245 22:58:47.135903 02c00000 ################################################################
10246 22:58:47.136038
10247 22:58:47.385021 02c80000 ################################################################
10248 22:58:47.385170
10249 22:58:47.634858 02d00000 ################################################################
10250 22:58:47.634998
10251 22:58:47.884579 02d80000 ################################################################
10252 22:58:47.884713
10253 22:58:48.156428 02e00000 ################################################################
10254 22:58:48.156565
10255 22:58:48.436281 02e80000 ################################################################
10256 22:58:48.436413
10257 22:58:48.723061 02f00000 ################################################################
10258 22:58:48.723223
10259 22:58:48.972707 02f80000 ################################################################
10260 22:58:48.972867
10261 22:58:49.031883 03000000 ############### done.
10262 22:58:49.032342
10263 22:58:49.035501 The bootfile was 50453538 bytes long.
10264 22:58:49.035927
10265 22:58:49.038579 Sending tftp read request... done.
10266 22:58:49.038960
10267 22:58:49.042267 Waiting for the transfer...
10268 22:58:49.042692
10269 22:58:49.043092 00000000 # done.
10270 22:58:49.043575
10271 22:58:49.049043 Command line loaded dynamically from TFTP file: 12172390/tftp-deploy-rtufekp4/kernel/cmdline
10272 22:58:49.049467
10273 22:58:49.062153 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10274 22:58:49.065902
10275 22:58:49.066317 Loading FIT.
10276 22:58:49.066656
10277 22:58:49.068672 Image ramdisk-1 has 39354878 bytes.
10278 22:58:49.069092
10279 22:58:49.072232 Image fdt-1 has 47278 bytes.
10280 22:58:49.072648
10281 22:58:49.075310 Image kernel-1 has 11049348 bytes.
10282 22:58:49.075726
10283 22:58:49.082292 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10284 22:58:49.082715
10285 22:58:49.101978 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10286 22:58:49.102517
10287 22:58:49.105614 Choosing best match conf-1 for compat google,spherion-rev2.
10288 22:58:49.110274
10289 22:58:49.114862 Connected to device vid:did:rid of 1ae0:0028:00
10290 22:58:49.122834
10291 22:58:49.126416 tpm_get_response: command 0x17b, return code 0x0
10292 22:58:49.126959
10293 22:58:49.129623 ec_init: CrosEC protocol v3 supported (256, 248)
10294 22:58:49.134858
10295 22:58:49.138069 tpm_cleanup: add release locality here.
10296 22:58:49.138489
10297 22:58:49.138823 Shutting down all USB controllers.
10298 22:58:49.141437
10299 22:58:49.142070 Removing current net device
10300 22:58:49.142432
10301 22:58:49.148028 Exiting depthcharge with code 4 at timestamp: 60428628
10302 22:58:49.148448
10303 22:58:49.151721 LZMA decompressing kernel-1 to 0x821a6718
10304 22:58:49.152259
10305 22:58:49.154479 LZMA decompressing kernel-1 to 0x40000000
10306 22:58:50.543108
10307 22:58:50.543665 jumping to kernel
10308 22:58:50.546951 end: 2.2.4 bootloader-commands (duration 00:00:33) [common]
10309 22:58:50.547682 start: 2.2.5 auto-login-action (timeout 00:03:53) [common]
10310 22:58:50.548290 Setting prompt string to ['Linux version [0-9]']
10311 22:58:50.548771 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10312 22:58:50.549165 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10313 22:58:50.625888
10314 22:58:50.629206 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10315 22:58:50.633522 start: 2.2.5.1 login-action (timeout 00:03:53) [common]
10316 22:58:50.634172 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10317 22:58:50.634573 Setting prompt string to []
10318 22:58:50.635048 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10319 22:58:50.635480 Using line separator: #'\n'#
10320 22:58:50.635821 No login prompt set.
10321 22:58:50.636160 Parsing kernel messages
10322 22:58:50.636471 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10323 22:58:50.637039 [login-action] Waiting for messages, (timeout 00:03:53)
10324 22:58:50.652708 [ 0.000000] Linux version 6.1.64-cip10-rt5 (KernelCI@build-j33605-arm64-gcc-10-defconfig-arm64-chromebook-7778h) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sun Dec 3 22:38:18 UTC 2023
10325 22:58:50.656224 [ 0.000000] random: crng init done
10326 22:58:50.662565 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10327 22:58:50.666277 [ 0.000000] efi: UEFI not found.
10328 22:58:50.672584 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10329 22:58:50.679318 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10330 22:58:50.689475 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10331 22:58:50.699192 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10332 22:58:50.705994 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10333 22:58:50.712869 [ 0.000000] printk: bootconsole [mtk8250] enabled
10334 22:58:50.718751 [ 0.000000] NUMA: No NUMA configuration found
10335 22:58:50.725554 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10336 22:58:50.728977 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10337 22:58:50.732523 [ 0.000000] Zone ranges:
10338 22:58:50.738748 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10339 22:58:50.742216 [ 0.000000] DMA32 empty
10340 22:58:50.748871 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10341 22:58:50.752555 [ 0.000000] Movable zone start for each node
10342 22:58:50.755382 [ 0.000000] Early memory node ranges
10343 22:58:50.762562 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10344 22:58:50.769351 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10345 22:58:50.775881 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10346 22:58:50.782072 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10347 22:58:50.785559 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10348 22:58:50.795572 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10349 22:58:50.849808 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10350 22:58:50.856572 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10351 22:58:50.863403 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10352 22:58:50.866406 [ 0.000000] psci: probing for conduit method from DT.
10353 22:58:50.873236 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10354 22:58:50.876437 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10355 22:58:50.882924 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10356 22:58:50.886280 [ 0.000000] psci: SMC Calling Convention v1.2
10357 22:58:50.892897 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10358 22:58:50.896001 [ 0.000000] Detected VIPT I-cache on CPU0
10359 22:58:50.903604 [ 0.000000] CPU features: detected: GIC system register CPU interface
10360 22:58:50.910055 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10361 22:58:50.916635 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10362 22:58:50.922910 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10363 22:58:50.929808 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10364 22:58:50.936592 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10365 22:58:50.942581 [ 0.000000] alternatives: applying boot alternatives
10366 22:58:50.949670 [ 0.000000] Fallback order for Node 0: 0
10367 22:58:50.956297 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10368 22:58:50.959753 [ 0.000000] Policy zone: Normal
10369 22:58:50.972500 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10370 22:58:50.982450 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10371 22:58:50.994334 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10372 22:58:51.004115 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10373 22:58:51.010616 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10374 22:58:51.014093 <6>[ 0.000000] software IO TLB: area num 8.
10375 22:58:51.070818 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10376 22:58:51.220281 <6>[ 0.000000] Memory: 7931124K/8385536K available (17984K kernel code, 4116K rwdata, 17316K rodata, 8448K init, 615K bss, 421644K reserved, 32768K cma-reserved)
10377 22:58:51.226343 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10378 22:58:51.233125 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10379 22:58:51.236339 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10380 22:58:51.242881 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10381 22:58:51.249362 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10382 22:58:51.252747 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10383 22:58:51.262872 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10384 22:58:51.269572 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10385 22:58:51.275900 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10386 22:58:51.282783 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10387 22:58:51.285903 <6>[ 0.000000] GICv3: 608 SPIs implemented
10388 22:58:51.289292 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10389 22:58:51.296058 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10390 22:58:51.299477 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10391 22:58:51.305696 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10392 22:58:51.318505 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10393 22:58:51.331615 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10394 22:58:51.338444 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10395 22:58:51.346353 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10396 22:58:51.360085 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10397 22:58:51.366442 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10398 22:58:51.373248 <6>[ 0.009181] Console: colour dummy device 80x25
10399 22:58:51.382998 <6>[ 0.013903] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10400 22:58:51.389684 <6>[ 0.024410] pid_max: default: 32768 minimum: 301
10401 22:58:51.392943 <6>[ 0.029282] LSM: Security Framework initializing
10402 22:58:51.399202 <6>[ 0.034252] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10403 22:58:51.409546 <6>[ 0.042068] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10404 22:58:51.416430 <6>[ 0.051469] cblist_init_generic: Setting adjustable number of callback queues.
10405 22:58:51.423126 <6>[ 0.058911] cblist_init_generic: Setting shift to 3 and lim to 1.
10406 22:58:51.433154 <6>[ 0.065289] cblist_init_generic: Setting adjustable number of callback queues.
10407 22:58:51.439162 <6>[ 0.072763] cblist_init_generic: Setting shift to 3 and lim to 1.
10408 22:58:51.442591 <6>[ 0.079202] rcu: Hierarchical SRCU implementation.
10409 22:58:51.449285 <6>[ 0.079204] rcu: Max phase no-delay instances is 1000.
10410 22:58:51.455963 <6>[ 0.079228] printk: bootconsole [mtk8250] printing thread started
10411 22:58:51.462509 <6>[ 0.097558] EFI services will not be available.
10412 22:58:51.465536 <6>[ 0.097757] smp: Bringing up secondary CPUs ...
10413 22:58:51.469010 <6>[ 0.098067] Detected VIPT I-cache on CPU1
10414 22:58:51.478822 <6>[ 0.098136] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10415 22:58:51.485515 <6>[ 0.098168] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10416 22:58:51.494845 <6>[ 0.126030] Detected VIPT I-cache on CPU2
10417 22:58:51.501157 <6>[ 0.126083] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10418 22:58:51.511214 <6>[ 0.126100] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10419 22:58:51.514435 <6>[ 0.126358] Detected VIPT I-cache on CPU3
10420 22:58:51.520675 <6>[ 0.126405] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10421 22:58:51.527723 <6>[ 0.126419] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10422 22:58:51.530805 <6>[ 0.126728] CPU features: detected: Spectre-v4
10423 22:58:51.537293 <6>[ 0.126734] CPU features: detected: Spectre-BHB
10424 22:58:51.540630 <6>[ 0.126739] Detected PIPT I-cache on CPU4
10425 22:58:51.547485 <6>[ 0.126797] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10426 22:58:51.554133 <6>[ 0.126813] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10427 22:58:51.560553 <6>[ 0.127104] Detected PIPT I-cache on CPU5
10428 22:58:51.567016 <6>[ 0.127163] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10429 22:58:51.574003 <6>[ 0.127179] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10430 22:58:51.577521 <6>[ 0.127457] Detected PIPT I-cache on CPU6
10431 22:58:51.587785 <6>[ 0.127520] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10432 22:58:51.594036 <6>[ 0.127536] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10433 22:58:51.597139 <6>[ 0.127828] Detected PIPT I-cache on CPU7
10434 22:58:51.604035 <6>[ 0.127892] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10435 22:58:51.610222 <6>[ 0.127908] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10436 22:58:51.613807 <6>[ 0.127954] smp: Brought up 1 node, 8 CPUs
10437 22:58:51.620239 <6>[ 0.127959] SMP: Total of 8 processors activated.
10438 22:58:51.627051 <6>[ 0.127961] CPU features: detected: 32-bit EL0 Support
10439 22:58:51.633381 <6>[ 0.127963] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10440 22:58:51.640295 <6>[ 0.127966] CPU features: detected: Common not Private translations
10441 22:58:51.646933 <6>[ 0.127967] CPU features: detected: CRC32 instructions
10442 22:58:51.650310 <6>[ 0.127970] CPU features: detected: RCpc load-acquire (LDAPR)
10443 22:58:51.656693 <6>[ 0.127971] CPU features: detected: LSE atomic instructions
10444 22:58:51.663497 <6>[ 0.127973] CPU features: detected: Privileged Access Never
10445 22:58:51.670058 <6>[ 0.127974] CPU features: detected: RAS Extension Support
10446 22:58:51.676598 <6>[ 0.127977] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10447 22:58:51.680541 <6>[ 0.128043] CPU: All CPU(s) started at EL2
10448 22:58:51.686674 <6>[ 0.128045] alternatives: applying system-wide alternatives
10449 22:58:51.690613 <6>[ 0.141085] devtmpfs: initialized
10450 22:58:51.700155 <6>[ 0.147304] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10451 22:58:51.728499 ��+kW��4*ԕʪ.�������2�����5S�<6>[ 0.364<315] printk: console [ttyS0] printing thread started
10452 22:58:51.734935 6<6>[ 0.364370] printk: console [ttyS0] enabled
10453 22:58:51.741957 >[ 0.228625] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10454 22:58:51.749343 <6>[ 0.364374] printk: bootconsole [mtk8250] disabled
10455 22:58:51.755671 <6>[ 0.382434] printk: bootconsole [mtk8250] printing thread stopped
10456 22:58:51.759506 <6>[ 0.383392] SuperH (H)SCI(F) driver initialized
10457 22:58:51.765693 <6>[ 0.383887] msm_serial: driver initialized
10458 22:58:51.772349 <6>[ 0.388421] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10459 22:58:51.781675 <6>[ 0.388448] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10460 22:58:51.788913 <6>[ 0.388477] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10461 22:58:51.802692 <6>[ 0.388507] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10462 22:58:51.812281 <6>[ 0.388528] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10463 22:58:51.821262 <6>[ 0.388555] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10464 22:58:51.837441 <6>[ 0.388584] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10465 22:58:51.838070 <6>[ 0.388693] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10466 22:58:51.845410 <6>[ 0.388722] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10467 22:58:51.850979 <6>[ 0.400367] loop: module loaded
10468 22:58:51.858869 <6>[ 0.402937] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10469 22:58:51.859442 <4>[ 0.419632] mtk-pmic-keys: Failed to locate of_node [id: -1]
10470 22:58:51.862294 <6>[ 0.420429] megasas: 07.719.03.00-rc1
10471 22:58:51.869150 <6>[ 0.436709] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10472 22:58:51.872692 <6>[ 0.441560] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10473 22:58:51.879152 <6>[ 0.448577] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10474 22:58:51.891918 <6>[ 0.501773] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10475 22:58:53.188967 <6>[ 1.824391] Freeing initrd memory: 38428K
10476 22:58:53.197025 <6>[ 1.830530] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10477 22:58:53.203238 <6>[ 1.835137] tun: Universal TUN/TAP device driver, 1.6
10478 22:58:53.206585 <6>[ 1.835883] thunder_xcv, ver 1.0
10479 22:58:53.210461 <6>[ 1.835903] thunder_bgx, ver 1.0
10480 22:58:53.213281 <6>[ 1.835919] nicpf, ver 1.0
10481 22:58:53.220478 <6>[ 1.836955] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10482 22:58:53.226942 <6>[ 1.836958] hns3: Copyright (c) 2017 Huawei Corporation.
10483 22:58:53.229866 <6>[ 1.836985] hclge is initializing
10484 22:58:53.236374 <6>[ 1.836998] e1000: Intel(R) PRO/1000 Network Driver
10485 22:58:53.239612 <6>[ 1.837000] e1000: Copyright (c) 1999-2006 Intel Corporation.
10486 22:58:53.246911 <6>[ 1.837018] e1000e: Intel(R) PRO/1000 Network Driver
10487 22:58:53.250919 <6>[ 1.837019] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10488 22:58:53.257443 <6>[ 1.837034] igb: Intel(R) Gigabit Ethernet Network Driver
10489 22:58:53.264387 <6>[ 1.837036] igb: Copyright (c) 2007-2014 Intel Corporation.
10490 22:58:53.271147 <6>[ 1.837050] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10491 22:58:53.277709 <6>[ 1.837052] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10492 22:58:53.281432 <6>[ 1.837371] sky2: driver version 1.30
10493 22:58:53.284344 <6>[ 1.838435] VFIO - User Level meta-driver version: 0.3
10494 22:58:53.290831 <6>[ 1.841218] usbcore: registered new interface driver usb-storage
10495 22:58:53.297739 <6>[ 1.841408] usbcore: registered new device driver onboard-usb-hub
10496 22:58:53.304447 <6>[ 1.844170] mt6397-rtc mt6359-rtc: registered as rtc0
10497 22:58:53.313930 <6>[ 1.844326] mt6397-rtc mt6359-rtc: setting system clock to 2023-12-03T22:56:41 UTC (1701644201)
10498 22:58:53.317693 <6>[ 1.844928] i2c_dev: i2c /dev entries driver
10499 22:58:53.324479 <6>[ 1.851946] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10500 22:58:53.331113 <6>[ 1.866920] cpu cpu0: EM: created perf domain
10501 22:58:53.334072 <6>[ 1.867233] cpu cpu4: EM: created perf domain
10502 22:58:53.340888 <6>[ 1.871535] sdhci: Secure Digital Host Controller Interface driver
10503 22:58:53.343753 <6>[ 1.871536] sdhci: Copyright(c) Pierre Ossman
10504 22:58:53.350459 <6>[ 1.871898] Synopsys Designware Multimedia Card Interface Driver
10505 22:58:53.356780 <6>[ 1.872275] sdhci-pltfm: SDHCI platform and OF driver helper
10506 22:58:53.363265 <6>[ 1.876552] ledtrig-cpu: registered to indicate activity on CPUs
10507 22:58:53.370363 <6>[ 1.877208] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10508 22:58:53.373380 <6>[ 1.877211] mmc0: CQHCI version 5.10
10509 22:58:53.380060 <6>[ 1.877487] usbcore: registered new interface driver usbhid
10510 22:58:53.383799 <6>[ 1.877489] usbhid: USB HID core driver
10511 22:58:53.390079 <6>[ 1.877610] spi_master spi0: will run message pump with realtime priority
10512 22:58:53.403131 <6>[ 1.907805] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10513 22:58:53.416343 <6>[ 1.909663] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10514 22:58:53.423253 <6>[ 1.910725] cros-ec-spi spi0.0: Chrome EC device registered
10515 22:58:53.433514 <6>[ 1.924569] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10516 22:58:53.436400 <6>[ 1.925505] NET: Registered PF_PACKET protocol family
10517 22:58:53.443508 <6>[ 1.925574] 9pnet: Installing 9P2000 support
10518 22:58:53.446428 <5>[ 1.925606] Key type dns_resolver registered
10519 22:58:53.449543 <6>[ 1.925947] registered taskstats version 1
10520 22:58:53.456288 <5>[ 1.925963] Loading compiled-in X.509 certificates
10521 22:58:53.466035 <4>[ 1.941652] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10522 22:58:53.475906 <4>[ 1.941827] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10523 22:58:53.483226 <3>[ 1.941837] debugfs: File 'uA_load' in directory '/' already present!
10524 22:58:53.489830 <3>[ 1.941845] debugfs: File 'min_uV' in directory '/' already present!
10525 22:58:53.495633 <3>[ 1.941848] debugfs: File 'max_uV' in directory '/' already present!
10526 22:58:53.506274 <3>[ 1.941851] debugfs: File 'constraint_flags' in directory '/' already present!
10527 22:58:53.512580 <3>[ 1.944022] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10528 22:58:53.519178 <6>[ 1.951334] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10529 22:58:53.525691 <6>[ 1.952031] xhci-mtk 11200000.usb: xHCI Host Controller
10530 22:58:53.532652 <6>[ 1.952045] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10531 22:58:53.542060 <6>[ 1.952259] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10532 22:58:53.549130 <6>[ 1.952306] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10533 22:58:53.552348 <6>[ 1.952395] xhci-mtk 11200000.usb: xHCI Host Controller
10534 22:58:53.562005 <6>[ 1.952402] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10535 22:58:53.568545 <6>[ 1.952408] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10536 22:58:53.572038 <6>[ 1.952841] hub 1-0:1.0: USB hub found
10537 22:58:53.575652 <6>[ 1.952865] hub 1-0:1.0: 1 port detected
10538 22:58:53.585234 <6>[ 1.953086] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10539 22:58:53.588882 <6>[ 1.953381] hub 2-0:1.0: USB hub found
10540 22:58:53.592579 <6>[ 1.953410] hub 2-0:1.0: 1 port detected
10541 22:58:53.598588 <6>[ 1.956407] mtk-msdc 11f70000.mmc: Got CD GPIO
10542 22:58:53.605447 <6>[ 1.970220] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10543 22:58:53.611960 <6>[ 1.970230] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10544 22:58:53.621850 <4>[ 1.970379] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10545 22:58:53.632166 <6>[ 1.971012] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10546 22:58:53.638303 <6>[ 1.971015] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10547 22:58:53.645136 <6>[ 1.971136] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10548 22:58:53.654876 <6>[ 1.971151] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10549 22:58:53.661601 <6>[ 1.971155] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10550 22:58:53.672096 <6>[ 1.971161] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10551 22:58:53.674866 <6>[ 1.971421] mmc0: Command Queue Engine enabled
10552 22:58:53.681522 <6>[ 1.971432] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10553 22:58:53.688425 <6>[ 1.972039] mmcblk0: mmc0:0001 DA4128 116 GiB
10554 22:58:53.695001 <6>[ 1.972994] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10555 22:58:53.704331 <6>[ 1.973016] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10556 22:58:53.711559 <6>[ 1.973023] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10557 22:58:53.721099 <6>[ 1.973029] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10558 22:58:53.728340 <6>[ 1.973036] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10559 22:58:53.738018 <6>[ 1.973042] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10560 22:58:53.744306 <6>[ 1.973049] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10561 22:58:53.754321 <6>[ 1.973055] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10562 22:58:53.761016 <6>[ 1.973062] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10563 22:58:53.771227 <6>[ 1.973068] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10564 22:58:53.777759 <6>[ 1.973074] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10565 22:58:53.788105 <6>[ 1.973080] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10566 22:58:53.794224 <6>[ 1.973087] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10567 22:58:53.804323 <6>[ 1.973093] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10568 22:58:53.810812 <6>[ 1.973099] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10569 22:58:53.817337 <6>[ 1.973846] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10570 22:58:53.824694 <6>[ 1.974766] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10571 22:58:53.831108 <6>[ 1.975313] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10572 22:58:53.837626 <6>[ 1.975609] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10573 22:58:53.844105 <6>[ 1.975951] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10574 22:58:53.850293 <6>[ 1.976597] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10575 22:58:53.857390 <6>[ 1.976639] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10576 22:58:53.863586 <6>[ 1.976839] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10577 22:58:53.873565 <6>[ 1.976856] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10578 22:58:53.883506 <6>[ 1.976865] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10579 22:58:53.893682 <6>[ 1.976871] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10580 22:58:53.903647 <6>[ 1.976877] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10581 22:58:53.913737 <6>[ 1.976883] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10582 22:58:53.919314 <6>[ 1.976889] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10583 22:58:53.929463 <6>[ 1.976893] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10584 22:58:53.939935 <6>[ 1.976898] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10585 22:58:53.949637 <6>[ 1.976906] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10586 22:58:53.959870 <6>[ 1.976911] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10587 22:58:53.965962 <6>[ 1.977549] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10588 22:58:53.973204 <6>[ 1.977689] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10589 22:58:53.979126 <6>[ 1.978400] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10590 22:58:53.985760 <6>[ 2.373418] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10591 22:58:53.989316 <6>[ 2.526224] hub 1-1:1.0: USB hub found
10592 22:58:53.995938 <6>[ 2.526626] hub 1-1:1.0: 4 ports detected
10593 22:58:53.998919 <6>[ 2.530880] hub 1-1:1.0: USB hub found
10594 22:58:54.002694 <6>[ 2.531196] hub 1-1:1.0: 4 ports detected
10595 22:58:54.019767 <6>[ 2.649681] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10596 22:58:54.040905 <6>[ 2.675210] hub 2-1:1.0: USB hub found
10597 22:58:54.044588 <6>[ 2.675649] hub 2-1:1.0: 3 ports detected
10598 22:58:54.047261 <6>[ 2.678872] hub 2-1:1.0: USB hub found
10599 22:58:54.050953 <6>[ 2.679265] hub 2-1:1.0: 3 ports detected
10600 22:58:54.215617 <6>[ 2.845624] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10601 22:58:54.336514 <6>[ 2.972964] hub 1-1.4:1.0: USB hub found
10602 22:58:54.339762 <6>[ 2.973318] hub 1-1.4:1.0: 2 ports detected
10603 22:58:54.343083 <6>[ 2.976885] hub 1-1.4:1.0: USB hub found
10604 22:58:54.349781 <6>[ 2.977241] hub 1-1.4:1.0: 2 ports detected
10605 22:58:54.420522 <6>[ 3.049696] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10606 22:58:54.636393 <6>[ 3.265643] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10607 22:58:54.819558 <6>[ 3.449625] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10608 22:59:05.636014 <6>[ 14.274620] ALSA device list:
10609 22:59:05.642522 <6>[ 14.274642] No soundcards found.
10610 22:59:05.646043 <6>[ 14.279119] Freeing unused kernel memory: 8448K
10611 22:59:05.648963 <6>[ 14.279284] Run /init as init process
10612 22:59:05.687522 <6>[ 14.321889] NET: Registered PF_INET6 protocol family
10613 22:59:05.690624 <6>[ 14.322988] Segment Routing with IPv6
10614 22:59:05.697190 <6>[ 14.323005] In-situ OAM (IOAM) with IPv6
10615 22:59:05.697821
10616 22:59:05.723620 Welcome to [1mDebian GNU/Linux <30>[ 14.339069] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10617 22:59:05.727080 <30>[ 14.339595] systemd[1]: Detected architecture arm64.
10618 22:59:05.730565 11 (bullseye)[0m!
10619 22:59:05.730992
10620 22:59:05.747217 <30>[ 14.381725] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10621 22:59:05.874509 <30>[ 14.506313] systemd[1]: Queued start job for default target Graphical Interface.
10622 22:59:05.908244 [[0;32m OK [0m] Created slic<30>[ 14.542638] systemd[1]: Created slice system-getty.slice.
10623 22:59:05.911626 e [0;1;39msystem-getty.slice[0m.
10624 22:59:05.936503 [[0;32m OK [0m] Created slic<30>[ 14.571055] systemd[1]: Created slice system-modprobe.slice.
10625 22:59:05.939626 e [0;1;39msystem-modprobe.slice[0m.
10626 22:59:05.963368 [[0;32m OK [0m] Created slice [0;1;39msyste<30>[ 14.594507] systemd[1]: Created slice system-serial\x2dgetty.slice.
10627 22:59:05.966171 m-serial\x2dgetty.slice[0m.
10628 22:59:05.984019 [[0;32m OK [0m] Created slic<30>[ 14.618715] systemd[1]: Created slice User and Session Slice.
10629 22:59:05.987119 e [0;1;39mUser and Session Slice[0m.
10630 22:59:06.011628 [[0;32m OK [0m] Started [0;<30>[ 14.642420] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10631 22:59:06.014566 1;39mDispatch Password …ts to Console Directory Watch[0m.
10632 22:59:06.039426 [[0;32m OK [0m] Started [0;1;39mForward Pas<30>[ 14.670401] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10633 22:59:06.042523 sword R…uests to Wall Directory Watch[0m.
10634 22:59:06.070538 [[0;32m OK [0m] Reached target [0;1;39mLoca<30>[ 14.698108] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10635 22:59:06.077527 <30>[ 14.698378] systemd[1]: Reached target Local Encrypted Volumes.
10636 22:59:06.080644 l Encrypted Volumes[0m.
10637 22:59:06.099911 [[0;32m OK [0m] Reached target [0;1;39mPath<30>[ 14.734183] systemd[1]: Reached target Paths.
10638 22:59:06.100500 s[0m.
10639 22:59:06.119352 [[0;32m OK [0m] Reached target [0;1;39mRemo<30>[ 14.753658] systemd[1]: Reached target Remote File Systems.
10640 22:59:06.122401 te File Systems[0m.
10641 22:59:06.143353 [[0;32m OK [0m] Reached target [0;1;39mSlic<30>[ 14.777985] systemd[1]: Reached target Slices.
10642 22:59:06.143821 es[0m.
10643 22:59:06.163273 [[0;32m OK [0m] Reached target [0;1;39mSwap<30>[ 14.798051] systemd[1]: Reached target Swap.
10644 22:59:06.163734 [0m.
10645 22:59:06.184131 [[0;32m OK [0m] Listening on<30>[ 14.818582] systemd[1]: Listening on initctl Compatibility Named Pipe.
10646 22:59:06.190771 [0;1;39minitctl Compatibility Named Pipe[0m.
10647 22:59:06.200619 [[0;32m OK [0m] Listening on [0;1;39mJourna<30>[ 14.834021] systemd[1]: Listening on Journal Audit Socket.
10648 22:59:06.203918 l Audit Socket[0m.
10649 22:59:06.226941 [[0;32m OK [0m] Listening on [0;1;39mJourna<30>[ 14.858239] systemd[1]: Listening on Journal Socket (/dev/log).
10650 22:59:06.227548 l Socket (/dev/log)[0m.
10651 22:59:06.248190 [[0;32m OK [0m] Listening on<30>[ 14.882843] systemd[1]: Listening on Journal Socket.
10652 22:59:06.251689 [0;1;39mJournal Socket[0m.
10653 22:59:06.271134 [[0;32m OK [0m] Listening on [0;1;39mNetwor<30>[ 14.902393] systemd[1]: Listening on Network Service Netlink Socket.
10654 22:59:06.274052 k Service Netlink Socket[0m.
10655 22:59:06.291604 [[0;32m OK [0m] Listening on [0;1;39mudev C<30>[ 14.926235] systemd[1]: Listening on udev Control Socket.
10656 22:59:06.295154 ontrol Socket[0m.
10657 22:59:06.316106 [[0;32m OK [0m] Listening on<30>[ 14.950735] systemd[1]: Listening on udev Kernel Socket.
10658 22:59:06.319377 [0;1;39mudev Kernel Socket[0m.
10659 22:59:06.378862 Mounting [0;1;39mHuge Pages File Syste<30>[ 15.009938] systemd[1]: Mounting Huge Pages File System...
10660 22:59:06.379385 m[0m...
10661 22:59:06.396821 Mounting [0;1;39mPOSIX<30>[ 15.031582] systemd[1]: Mounting POSIX Message Queue File System...
10662 22:59:06.400267 Message Queue File System[0m...
10663 22:59:06.421182 Mountin<30>[ 15.055960] systemd[1]: Mounting Kernel Debug File System...
10664 22:59:06.424908 g [0;1;39mKernel Debug File System[0m...
10665 22:59:06.449364 Startin<30>[ 15.078060] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10666 22:59:06.456000 <30>[ 15.080781] systemd[1]: Starting Create list of static device nodes for the current kernel...
10667 22:59:06.462379 g [0;1;39mCreate list of st…odes for the current kernel[0m...
10668 22:59:06.488345 Starting [0;1;39mLoad <30>[ 15.122444] systemd[1]: Starting Load Kernel Module configfs...
10669 22:59:06.491096 Kernel Module configfs[0m...
10670 22:59:06.518961 Starting [0;1;39mLoad Kernel Module dr<30>[ 15.150136] systemd[1]: Starting Load Kernel Module drm...
10671 22:59:06.519683 m[0m...
10672 22:59:06.538728 <30>[ 15.170033] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10673 22:59:06.551760 Starting [0;1;39mJourn<30>[ 15.186637] systemd[1]: Starting Journal Service...
10674 22:59:06.552181 al Service[0m...
10675 22:59:06.575715 Starting [0;1;39mLoad Kernel Modules[<30>[ 15.210392] systemd[1]: Starting Load Kernel Modules...
10676 22:59:06.578930 0m...
10677 22:59:06.602657 Starting [0;1;39mRemount Root and Kern<30>[ 15.234150] systemd[1]: Starting Remount Root and Kernel File Systems...
10678 22:59:06.606095 el File Systems[0m...
10679 22:59:06.628201 Starting [0;1;39mColdp<30>[ 15.262453] systemd[1]: Starting Coldplug All udev Devices...
10680 22:59:06.631936 lug All udev Devices[0m...
10681 22:59:06.656020 [[0;32m OK [0m] Started [0;<30>[ 15.290969] systemd[1]: Started Journal Service.
10682 22:59:06.659440 1;39mJournal Service[0m.
10683 22:59:06.675130 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10684 22:59:06.692980 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10685 22:59:06.708755 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10686 22:59:06.728246 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10687 22:59:06.745652 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10688 22:59:06.766165 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10689 22:59:06.785163 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10690 22:59:06.805799 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10691 22:59:06.819518 See 'systemctl status systemd-remount-fs.service' for details.
10692 22:59:06.864424 Mounting [0;1;39mKernel Configuration File System[0m...
10693 22:59:06.882567 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10694 22:59:06.902568 <46>[ 15.534984] systemd-journald[189]: Received client request to flush runtime journal.
10695 22:59:06.911071 Starting [0;1;39mLoad/Save Random Seed[0m...
10696 22:59:06.937399 Starting [0;1;39mApply Kernel Variables[0m...
10697 22:59:06.961133 Starting [0;1;39mCreate System Users[0m...
10698 22:59:06.980234 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10699 22:59:06.996343 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10700 22:59:07.016606 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10701 22:59:07.029373 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10702 22:59:07.049133 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10703 22:59:07.065143 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10704 22:59:07.099984 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10705 22:59:07.119980 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10706 22:59:07.131401 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10707 22:59:07.147460 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10708 22:59:07.180479 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10709 22:59:07.203388 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10710 22:59:07.224035 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10711 22:59:07.249475 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10712 22:59:07.314934 Starting [0;1;39mNetwork Service[0m...
10713 22:59:07.339961 Starting [0;1;39mNetwork Time Synchronization[0m...
10714 22:59:07.366782 <6>[ 15.997592] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10715 22:59:07.373472 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10716 22:59:07.398729 <6>[ 16.034018] remoteproc remoteproc0: scp is available
10717 22:59:07.406113 <6>[ 16.034180] remoteproc remoteproc0: powering up scp
10718 22:59:07.412376 <6>[ 16.034190] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10719 22:59:07.418611 [[0;32m OK [<6>[ 16.034224] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10720 22:59:07.428949 <6>[ 16.037958] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10721 22:59:07.438952 0m] Started [0;<6>[ 16.037998] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10722 22:59:07.449096 1;39mNetwork Ser<6>[ 16.038011] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10723 22:59:07.449185 vice[0m.
10724 22:59:07.458595 <3>[ 16.048375] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10725 22:59:07.465745 <3>[ 16.048406] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10726 22:59:07.472355 <3>[ 16.048412] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10727 22:59:07.485567 [[0;32m OK [0m] Found device [0;1;39m/dev/t<3>[ 16.120371] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10728 22:59:07.495721 <3>[ 16.120405] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10729 22:59:07.502029 <3>[ 16.120408] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10730 22:59:07.509197 <3>[ 16.120419] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10731 22:59:07.519160 <3>[ 16.120423] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10732 22:59:07.525280 <3>[ 16.134240] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10733 22:59:07.536155 <3>[ 16.138018] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10734 22:59:07.542475 <3>[ 16.138060] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10735 22:59:07.552445 <3>[ 16.138068] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10736 22:59:07.552873 tyS0[0m.
10737 22:59:07.558784 <6>[ 16.144869] usbcore: registered new interface driver r8152
10738 22:59:07.565067 <3>[ 16.157582] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10739 22:59:07.575268 <3>[ 16.157606] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10740 22:59:07.582096 <3>[ 16.157614] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10741 22:59:07.588463 <3>[ 16.157625] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10742 22:59:07.598945 [[0;32m OK [<3>[ 16.157632] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10743 22:59:07.608847 0m] Started [0;<6>[ 16.160321] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10744 22:59:07.618579 1;39mNetwork Tim<6>[ 16.160377] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10745 22:59:07.624974 e Synchronizatio<6>[ 16.160383] remoteproc remoteproc0: remote processor scp is now up
10746 22:59:07.635257 <3>[ 16.162465] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10747 22:59:07.641513 <6>[ 16.177663] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10748 22:59:07.648558 <6>[ 16.177678] pci_bus 0000:00: root bus resource [bus 00-ff]
10749 22:59:07.655025 <6>[ 16.177685] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10750 22:59:07.665217 <6>[ 16.177687] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10751 22:59:07.671495 <6>[ 16.177731] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10752 22:59:07.671919 n[0m.
10753 22:59:07.678370 <6>[ 16.177744] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10754 22:59:07.681130 <6>[ 16.177814] pci 0000:00:00.0: supports D1 D2
10755 22:59:07.687979 <6>[ 16.177816] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10756 22:59:07.698041 [[0;32m OK [<6>[ 16.228239] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10757 22:59:07.708506 0m] Finished [0<6>[ 16.232211] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10758 22:59:07.715646 <6>[ 16.232243] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10759 22:59:07.722060 <6>[ 16.232261] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10760 22:59:07.731813 ;1;39mUpdate UTM<6>[ 16.232276] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10761 22:59:07.735165 <6>[ 16.232390] pci 0000:01:00.0: supports D1 D2
10762 22:59:07.744996 P about System B<6>[ 16.232392] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10763 22:59:07.751530 <4>[ 16.238679] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10764 22:59:07.758419 <4>[ 16.241548] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10765 22:59:07.765374 <6>[ 16.241853] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10766 22:59:07.775068 <6>[ 16.258010] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10767 22:59:07.785515 oot/Shutdown[0m<6>[ 16.265792] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10768 22:59:07.795639 <4>[ 16.268670] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10769 22:59:07.802934 <4>[ 16.268688] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10770 22:59:07.803357 .
10771 22:59:07.809042 <6>[ 16.270106] mc: Linux media interface: v0.10
10772 22:59:07.816079 <6>[ 16.274475] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10773 22:59:07.822379 <6>[ 16.274524] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10774 22:59:07.832322 <6>[ 16.274529] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10775 22:59:07.839263 <6>[ 16.274538] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10776 22:59:07.846739 <6>[ 16.274551] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10777 22:59:07.853916 <6>[ 16.274564] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10778 22:59:07.860906 <6>[ 16.274578] pci 0000:00:00.0: PCI bridge to [bus 01]
10779 22:59:07.867729 <6>[ 16.274586] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10780 22:59:07.874660 <6>[ 16.282950] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10781 22:59:07.881971 <6>[ 16.300599] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10782 22:59:07.888359 <6>[ 16.307918] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10783 22:59:07.895529 <6>[ 16.310004] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10784 22:59:07.899100 [[0;32m OK [<6>[ 16.321461] r8152 2-1.3:1.0 eth0: v1.12.13
10785 22:59:07.905816 0m] Created slic<6>[ 16.323028] videodev: Linux video capture interface: v2.00
10786 22:59:07.916448 e [0;1;39msyste<4>[ 16.331641] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10787 22:59:07.923176 <4>[ 16.331641] Fallback method does not support PEC.
10788 22:59:07.933383 m-systemd\x2dbac<3>[ 16.346963] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10789 22:59:07.943943 klight.slice[0m<6>[ 16.352715] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10790 22:59:07.944103 .
10791 22:59:07.947299 <6>[ 16.380026] usbcore: registered new interface driver cdc_ether
10792 22:59:07.954066 <6>[ 16.394948] usbcore: registered new interface driver r8153_ecm
10793 22:59:07.964797 <3>[ 16.425645] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10794 22:59:07.974893 [[0;32m OK [0m] Reached targ<3>[ 16.426476] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10795 22:59:07.981498 et [0;1;39mBlue<6>[ 16.436607] Bluetooth: Core ver 2.22
10796 22:59:07.982098 tooth[0m.
10797 22:59:07.987917 <6>[ 16.439363] NET: Registered PF_BLUETOOTH protocol family
10798 22:59:07.995141 <6>[ 16.439373] Bluetooth: HCI device and connection manager initialized
10799 22:59:07.998562 <6>[ 16.439400] Bluetooth: HCI socket layer initialized
10800 22:59:08.008507 [[0;32m OK [0m] Reached target [0;1;39mSyst<6>[ 16.439406] Bluetooth: L2CAP socket layer initialized
10801 22:59:08.015808 em Time Set[0m.<6>[ 16.439430] Bluetooth: SCO socket layer initialized
10802 22:59:08.022513 <6>[ 16.454017] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10803 22:59:08.029115 <5>[ 16.454913] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10804 22:59:08.029549
10805 22:59:08.043338 <6>[ 16.464941] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10806 22:59:08.049697 <6>[ 16.465372] usbcore: registered new interface driver uvcvideo
10807 22:59:08.053023 <6>[ 16.468072] r8152 2-1.3:1.0 enx00e04c787aaa: renamed from eth0
10808 22:59:08.063239 <6>[ 16.468166] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10809 22:59:08.076223 [[0;32m OK [0m] Reached target [0;1;39mSyst<6>[ 16.479953] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10810 22:59:08.082877 em Time Synchron<5>[ 16.483516] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10811 22:59:08.090000 <6>[ 16.491212] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10812 22:59:08.099775 <3>[ 16.495148] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10813 22:59:08.109612 <3>[ 16.501593] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10814 22:59:08.116883 <3>[ 16.502357] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10815 22:59:08.123254 <6>[ 16.504556] usbcore: registered new interface driver btusb
10816 22:59:08.133326 <4>[ 16.505240] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10817 22:59:08.139822 <3>[ 16.505264] Bluetooth: hci0: Failed to load firmware file (-2)
10818 22:59:08.146395 <3>[ 16.505274] Bluetooth: hci0: Failed to set up firmware (-2)
10819 22:59:08.155670 <4>[ 16.505283] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10820 22:59:08.165700 <3>[ 16.523070] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10821 22:59:08.172652 <3>[ 16.544560] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10822 22:59:08.181771 <3>[ 16.564902] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10823 22:59:08.188357 <3>[ 16.586478] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10824 22:59:08.198890 <4>[ 16.654633] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10825 22:59:08.205260 <6>[ 16.654672] cfg80211: failed to load regulatory.db
10826 22:59:08.212166 <6>[ 16.734436] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10827 22:59:08.218634 <6>[ 16.734538] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10828 22:59:08.221872 <6>[ 16.753523] mt7921e 0000:01:00.0: ASIC revision: 79610010
10829 22:59:08.235712 <4>[ 16.848255] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10830 22:59:08.235870 ized[0m.
10831 22:59:08.255198 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10832 22:59:08.299699 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10833 22:59:08.325487 <4>[ 16.957285] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10834 22:59:08.340655 Starting [0;1;39mNetwork Name Resolution[0m...
10835 22:59:08.366524 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10836 22:59:08.401344 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10837 22:59:08.433542 [[0;32m OK [0m] Reached target [0;1;39mNetw<4>[ 17.064122] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10838 22:59:08.433916 ork[0m.
10839 22:59:08.455002 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10840 22:59:08.467311 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10841 22:59:08.487015 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10842 22:59:08.502335 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10843 22:59:08.515177 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10844 22:59:08.542708 [[0;32m OK [0m] Listening on<4>[ 17.171778] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10845 22:59:08.545682 [0;1;39mD-Bus System Message Bus Socket[0m.
10846 22:59:08.560187 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10847 22:59:08.575542 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10848 22:59:08.612150 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10849 22:59:08.653747 <4>[ 17.284376] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10850 22:59:08.660434 Starting [0;1;39mUser Login Management[0m...
10851 22:59:08.679832 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10852 22:59:08.706434 Starting [0;1;39mPermit User Sessions[0m...
10853 22:59:08.720985 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10854 22:59:08.737713 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10855 22:59:08.761828 <4>[ 17.391752] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10856 22:59:08.796288 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10857 22:59:08.816635 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10858 22:59:08.831683 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10859 22:59:08.849315 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10860 22:59:08.871877 [[0;32m OK [0m] Reached target [0;1;39mMult<4>[ 17.500381] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10861 22:59:08.874746 i-User System[0m.
10862 22:59:08.888119 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10863 22:59:08.943669 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10864 22:59:08.984043 <4>[ 17.612378] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10865 22:59:08.993697 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10866 22:59:09.039233
10867 22:59:09.039840
10868 22:59:09.042373 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10869 22:59:09.042794
10870 22:59:09.045946 debian-bullseye-arm64 login: root (automatic login)
10871 22:59:09.046373
10872 22:59:09.046705
10873 22:59:09.063464 Linux debian-bullseye-arm64 6.1.64-cip10-rt5 #1 SMP PREEMPT Sun Dec 3 22:38:18 UTC 2023 aarch64
10874 22:59:09.063897
10875 22:59:09.070037 The programs included with the Debian GNU/Linux system are free software;
10876 22:59:09.076722 the exact distribution terms for each program are described in the
10877 22:59:09.089520 individual files in /usr/shar<4>[ 17.721260] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10878 22:59:09.092612 e/doc/*/copyright.
10879 22:59:09.092696
10880 22:59:09.099827 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10881 22:59:09.099911 permitted by applicable law.
10882 22:59:09.100268 Matched prompt #10: / #
10884 22:59:09.100468 Setting prompt string to ['/ #']
10885 22:59:09.100561 end: 2.2.5.1 login-action (duration 00:00:18) [common]
10887 22:59:09.100765 end: 2.2.5 auto-login-action (duration 00:00:19) [common]
10888 22:59:09.100853 start: 2.2.6 expect-shell-connection (timeout 00:03:34) [common]
10889 22:59:09.100922 Setting prompt string to ['/ #']
10890 22:59:09.100982 Forcing a shell prompt, looking for ['/ #']
10892 22:59:09.151200 / #
10893 22:59:09.151319 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10894 22:59:09.151399 Waiting using forced prompt support (timeout 00:02:30)
10895 22:59:09.156457
10896 22:59:09.156732 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10897 22:59:09.156829 start: 2.2.7 export-device-env (timeout 00:03:34) [common]
10898 22:59:09.156923 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10899 22:59:09.157008 end: 2.2 depthcharge-retry (duration 00:01:26) [common]
10900 22:59:09.157091 end: 2 depthcharge-action (duration 00:01:26) [common]
10901 22:59:09.157180 start: 3 lava-test-retry (timeout 00:08:10) [common]
10902 22:59:09.157266 start: 3.1 lava-test-shell (timeout 00:08:10) [common]
10903 22:59:09.157339 Using namespace: common
10905 22:59:09.257669 / # #
10906 22:59:09.257813 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
10907 22:59:09.257928 <4>[ 17.828227] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10908 22:59:09.262891 #
10909 22:59:09.263161 Using /lava-12172390
10911 22:59:09.363622 / # export SHELL=/bin/sh
10912 22:59:09.364407 <3>[ 17.934066] mt7921e 0000:01:00.0: hardware init failed
10913 22:59:09.370754 export SHELL=/bin/sh
10915 22:59:09.472324 / # . /lava-12172390/environment
10916 22:59:09.473038 <6>[ 18.053962] IPv6: ADDRCONF(NETDEV_CHANGE): enx00e04c787aaa: link becomes ready
10917 22:59:09.473527 <6>[ 18.054470] r8152 2-1.3:1.0 enx00e04c787aaa: carrier on
10918 22:59:09.478100 . /lava-12172390/environment
10920 22:59:09.579524 / # /lava-12172390/bin/lava-test-runner /lava-12172390/0
10921 22:59:09.580046 Test shell timeout: 10s (minimum of the action and connection timeout)
10922 22:59:09.585865 /lava-12172390/bin/lava-test-runner /lava-12172390/0
10923 22:59:09.607050 + export TESTRUN_ID=0_v4l2-compliance-uvc
10924 22:59:09.610669 + cd /lava-12172390/0/tests/0_v4l2-compliance-uvc
10925 22:59:09.611096 + cat uuid
10926 22:59:09.613835 + UUID=12172390_1.5.2.3.1
10927 22:59:09.614263 + set +x
10928 22:59:09.620738 <LAVA_SIGNAL_STARTRUN 0_v4l2-compliance-uvc 12172390_1.5.2.3.1>
10929 22:59:09.621440 Received signal: <STARTRUN> 0_v4l2-compliance-uvc 12172390_1.5.2.3.1
10930 22:59:09.621862 Starting test lava.0_v4l2-compliance-uvc (12172390_1.5.2.3.1)
10931 22:59:09.622281 Skipping test definition patterns.
10932 22:59:09.623892 + /usr/bin/v4l2-parser.sh -d uvcvideo
10933 22:59:09.630400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=device-presence RESULT=pass>
10934 22:59:09.630826 device: /dev/video0
10935 22:59:09.631418 Received signal: <TESTCASE> TEST_CASE_ID=device-presence RESULT=pass
10937 22:59:16.112389 v4l2-compliance 1.25.0-1, 64 bits, 64-bit time_t
10938 22:59:16.123600 v4l2-compliance SHA: 16e70e28584c 2023-06-22 09:47:27
10939 22:59:16.135691
10940 22:59:16.148474 Compliance test for uvcvideo device /dev/video0:
10941 22:59:16.158415
10942 22:59:16.170308 Driver Info:
10943 22:59:16.180533 Driver name : uvcvideo
10944 22:59:16.194268 Card type : HD User Facing: HD User Facing
10945 22:59:16.204297 Bus info : usb-11200000.usb-1.4.1
10946 22:59:16.215848 Driver version : 6.1.64
10947 22:59:16.229737 Capabilities : 0x84a00001
10948 22:59:16.243567 Metadata Capture
10949 22:59:16.254334 Streaming
10950 22:59:16.267134 Extended Pix Format
10951 22:59:16.277843 Device Capabilities
10952 22:59:16.290639 Device Caps : 0x04200001
10953 22:59:16.304774 Streaming
10954 22:59:16.321313 Extended Pix Format
10955 22:59:16.332418 Media Driver Info:
10956 22:59:16.343223 Driver name : uvcvideo
10957 22:59:16.355475 Model : HD User Facing: HD User Facing
10958 22:59:16.365294 Serial : 200901010001
10959 22:59:16.382041 Bus info : usb-11200000.usb-1.4.1
10960 22:59:16.392893 Media version : 6.1.64
10961 22:59:16.407425 Hardware revision: 0x00009758 (38744)
10962 22:59:16.417512 Driver version : 6.1.64
10963 22:59:16.429618 Interface Info:
10964 22:59:16.447844 <LAVA_SIGNAL_TESTSET START Interface-Info>
10965 22:59:16.448273 ID : 0x03000002
10966 22:59:16.448875 Received signal: <TESTSET> START Interface-Info
10967 22:59:16.449227 Starting test_set Interface-Info
10968 22:59:16.460771 Type : V4L Video
10969 22:59:16.471862 Entity Info:
10970 22:59:16.480266 <LAVA_SIGNAL_TESTSET STOP>
10971 22:59:16.480942 Received signal: <TESTSET> STOP
10972 22:59:16.481316 Closing test_set Interface-Info
10973 22:59:16.489675 <LAVA_SIGNAL_TESTSET START Entity-Info>
10974 22:59:16.490358 Received signal: <TESTSET> START Entity-Info
10975 22:59:16.490710 Starting test_set Entity-Info
10976 22:59:16.492835 ID : 0x00000001 (1)
10977 22:59:16.503469 Name : HD User Facing: HD User Facing
10978 22:59:16.510604 Function : V4L2 I/O
10979 22:59:16.521455 Flags : default
10980 22:59:16.532842 Pad 0x01000007 : 0: Sink
10981 22:59:16.556898 Link 0x02000013: from remote pad 0x100000a of entity 'Realtek Extended Controls Unit' (Video Pixel Formatter): Data, Enabled, Immutable
10982 22:59:16.557341
10983 22:59:16.567606 Required ioctls:
10984 22:59:16.575771 <LAVA_SIGNAL_TESTSET STOP>
10985 22:59:16.576463 Received signal: <TESTSET> STOP
10986 22:59:16.576823 Closing test_set Entity-Info
10987 22:59:16.585633 <LAVA_SIGNAL_TESTSET START Required-ioctls>
10988 22:59:16.586370 Received signal: <TESTSET> START Required-ioctls
10989 22:59:16.586739 Starting test_set Required-ioctls
10990 22:59:16.589150 test MC information (see 'Media Driver Info' above): OK
10991 22:59:16.614769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MC-information-see-Media-Driver-Info-above RESULT=pass>
10992 22:59:16.615461 Received signal: <TESTCASE> TEST_CASE_ID=MC-information-see-Media-Driver-Info-above RESULT=pass
10994 22:59:16.618198 test VIDIOC_QUERYCAP: OK
10995 22:59:16.635975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
10996 22:59:16.636670 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
10998 22:59:16.638666 test invalid ioctls: OK
10999 22:59:16.661205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-ioctls RESULT=pass>
11000 22:59:16.661684
11001 22:59:16.662337 Received signal: <TESTCASE> TEST_CASE_ID=invalid-ioctls RESULT=pass
11003 22:59:16.672194 Allow for multiple opens:
11004 22:59:16.679821 <LAVA_SIGNAL_TESTSET STOP>
11005 22:59:16.680077 Received signal: <TESTSET> STOP
11006 22:59:16.680149 Closing test_set Required-ioctls
11007 22:59:16.691840 <LAVA_SIGNAL_TESTSET START Allow-for-multiple-opens>
11008 22:59:16.692097 Received signal: <TESTSET> START Allow-for-multiple-opens
11009 22:59:16.692168 Starting test_set Allow-for-multiple-opens
11010 22:59:16.695434 test second /dev/video0 open: OK
11011 22:59:16.716817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=second-/dev/video0-open RESULT=pass>
11012 22:59:16.717075 Received signal: <TESTCASE> TEST_CASE_ID=second-/dev/video0-open RESULT=pass
11014 22:59:16.720354 test VIDIOC_QUERYCAP: OK
11015 22:59:16.743778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11016 22:59:16.744049 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11018 22:59:16.746802 test VIDIOC_G/S_PRIORITY: OK
11019 22:59:16.766843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass>
11020 22:59:16.767113 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass
11022 22:59:16.769817 test for unlimited opens: OK
11023 22:59:16.790325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=for-unlimited-opens RESULT=pass>
11024 22:59:16.790463
11025 22:59:16.790753 Received signal: <TESTCASE> TEST_CASE_ID=for-unlimited-opens RESULT=pass
11027 22:59:16.800653 Debug ioctls:
11028 22:59:16.808353 <LAVA_SIGNAL_TESTSET STOP>
11029 22:59:16.809025 Received signal: <TESTSET> STOP
11030 22:59:16.809377 Closing test_set Allow-for-multiple-opens
11031 22:59:16.818092 <LAVA_SIGNAL_TESTSET START Debug-ioctls>
11032 22:59:16.818782 Received signal: <TESTSET> START Debug-ioctls
11033 22:59:16.819144 Starting test_set Debug-ioctls
11034 22:59:16.820911 test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
11035 22:59:16.845094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass>
11036 22:59:16.845788 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass
11038 22:59:16.851077 test VIDIOC_LOG_STATUS: OK (Not Supported)
11039 22:59:16.867688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass>
11040 22:59:16.868172
11041 22:59:16.868777 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass
11043 22:59:16.878505 Input ioctls:
11044 22:59:16.886031 <LAVA_SIGNAL_TESTSET STOP>
11045 22:59:16.887049 Received signal: <TESTSET> STOP
11046 22:59:16.887616 Closing test_set Debug-ioctls
11047 22:59:16.895086 <LAVA_SIGNAL_TESTSET START Input-ioctls>
11048 22:59:16.895792 Received signal: <TESTSET> START Input-ioctls
11049 22:59:16.896242 Starting test_set Input-ioctls
11050 22:59:16.898813 test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
11051 22:59:16.927760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass>
11052 22:59:16.928506 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass
11054 22:59:16.931150 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11055 22:59:16.949759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11056 22:59:16.950644 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11058 22:59:16.956292 test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
11059 22:59:16.980975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass>
11060 22:59:16.981791 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass
11062 22:59:16.987462 test VIDIOC_ENUMAUDIO: OK (Not Supported)
11063 22:59:17.005443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass>
11064 22:59:17.006309 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass
11066 22:59:17.008471 test VIDIOC_G/S/ENUMINPUT: OK
11067 22:59:17.032373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass>
11068 22:59:17.033216 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass
11070 22:59:17.035867 test VIDIOC_G/S_AUDIO: OK (Not Supported)
11071 22:59:17.060200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass>
11072 22:59:17.060935 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass
11074 22:59:17.063490 Inputs: 1 Audio Inputs: 0 Tuners: 0
11075 22:59:17.070983
11076 22:59:17.087523 test VIDIOC_G/S_MODULATOR: OK (Not Supported)
11077 22:59:17.112898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass>
11078 22:59:17.113627 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass
11080 22:59:17.119568 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11081 22:59:17.138462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11082 22:59:17.139393 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11084 22:59:17.141933 test VIDIOC_ENUMAUDOUT: OK (Not Supported)
11085 22:59:17.166540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass>
11086 22:59:17.167389 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass
11088 22:59:17.173015 test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
11089 22:59:17.191271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass>
11090 22:59:17.192400 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass
11092 22:59:17.197720 test VIDIOC_G/S_AUDOUT: OK (Not Supported)
11093 22:59:17.221215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass>
11094 22:59:17.221689
11095 22:59:17.222293 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass
11097 22:59:17.241014 test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
11098 22:59:17.263709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass>
11099 22:59:17.264415 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass
11101 22:59:17.270044 test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
11102 22:59:17.292437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass>
11103 22:59:17.293236 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass
11105 22:59:17.295992 test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
11106 22:59:17.320648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass>
11107 22:59:17.321481 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass
11109 22:59:17.323626 test VIDIOC_G/S_EDID: OK (Not Supported)
11110 22:59:17.346520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass>
11111 22:59:17.346958
11112 22:59:17.347766 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass
11114 22:59:17.357092 Control ioctls (Input 0):
11115 22:59:17.366425 <LAVA_SIGNAL_TESTSET STOP>
11116 22:59:17.367178 Received signal: <TESTSET> STOP
11117 22:59:17.367544 Closing test_set Input-ioctls
11118 22:59:17.377426 <LAVA_SIGNAL_TESTSET START Control-ioctls-Input-0>
11119 22:59:17.378188 Received signal: <TESTSET> START Control-ioctls-Input-0
11120 22:59:17.378575 Starting test_set Control-ioctls-Input-0
11121 22:59:17.381013 test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
11122 22:59:17.406191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass>
11123 22:59:17.406756 test VIDIOC_QUERYCTRL: OK
11124 22:59:17.407486 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass
11126 22:59:17.429528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass>
11127 22:59:17.429826 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass
11129 22:59:17.432491 test VIDIOC_G/S_CTRL: OK
11130 22:59:17.459949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass>
11131 22:59:17.460224 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass
11133 22:59:17.462901 test VIDIOC_G/S/TRY_EXT_CTRLS: OK
11134 22:59:17.484267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass>
11135 22:59:17.484531 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass
11137 22:59:17.490781 test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: OK
11138 22:59:17.513832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=pass>
11139 22:59:17.514184 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=pass
11141 22:59:17.516897 test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
11142 22:59:17.540950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass>
11143 22:59:17.541634 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass
11145 22:59:17.544517 Standard Controls: 16 Private Controls: 0
11146 22:59:17.552366
11147 22:59:17.566155 Format ioctls (Input 0):
11148 22:59:17.574473 <LAVA_SIGNAL_TESTSET STOP>
11149 22:59:17.575367 Received signal: <TESTSET> STOP
11150 22:59:17.575772 Closing test_set Control-ioctls-Input-0
11151 22:59:17.584499 <LAVA_SIGNAL_TESTSET START Format-ioctls-Input-0>
11152 22:59:17.585368 Received signal: <TESTSET> START Format-ioctls-Input-0
11153 22:59:17.585899 Starting test_set Format-ioctls-Input-0
11154 22:59:17.587389 test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
11155 22:59:17.616858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass>
11156 22:59:17.617550 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass
11158 22:59:17.619764 test VIDIOC_G/S_PARM: OK
11159 22:59:17.639986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass>
11160 22:59:17.640754 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass
11162 22:59:17.642933 test VIDIOC_G_FBUF: OK (Not Supported)
11163 22:59:17.667309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass>
11164 22:59:17.668060 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass
11166 22:59:17.670566 test VIDIOC_G_FMT: OK
11167 22:59:17.693136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass>
11168 22:59:17.693823 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass
11170 22:59:17.696531 test VIDIOC_TRY_FMT: OK
11171 22:59:17.717985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass>
11172 22:59:17.718873 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass
11174 22:59:17.724208 warn: ../utils/v4l2-compliance/v4l2-test-formats.cpp(1046): Could not set fmt2
11175 22:59:17.728988 test VIDIOC_S_FMT: OK
11176 22:59:17.753132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_FMT RESULT=pass>
11177 22:59:17.754059 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_FMT RESULT=pass
11179 22:59:17.756052 test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
11180 22:59:17.779921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass>
11181 22:59:17.780609 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass
11183 22:59:17.783369 test Cropping: OK (Not Supported)
11184 22:59:17.806039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Cropping RESULT=pass>
11185 22:59:17.806724 Received signal: <TESTCASE> TEST_CASE_ID=Cropping RESULT=pass
11187 22:59:17.809565 test Composing: OK (Not Supported)
11188 22:59:17.831265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Composing RESULT=pass>
11189 22:59:17.832068 Received signal: <TESTCASE> TEST_CASE_ID=Composing RESULT=pass
11191 22:59:17.834888 test Scaling: OK (Not Supported)
11192 22:59:17.855968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Scaling RESULT=pass>
11193 22:59:17.856406
11194 22:59:17.856997 Received signal: <TESTCASE> TEST_CASE_ID=Scaling RESULT=pass
11196 22:59:17.866501 Codec ioctls (Input 0):
11197 22:59:17.873016 <LAVA_SIGNAL_TESTSET STOP>
11198 22:59:17.873716 Received signal: <TESTSET> STOP
11199 22:59:17.874090 Closing test_set Format-ioctls-Input-0
11200 22:59:17.882834 <LAVA_SIGNAL_TESTSET START Codec-ioctls-Input-0>
11201 22:59:17.883539 Received signal: <TESTSET> START Codec-ioctls-Input-0
11202 22:59:17.883931 Starting test_set Codec-ioctls-Input-0
11203 22:59:17.886223 test VIDIOC_(TRY_)ENCODER_CMD: OK (Not Supported)
11204 22:59:17.907912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass>
11205 22:59:17.908619 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass
11207 22:59:17.914957 test VIDIOC_G_ENC_INDEX: OK (Not Supported)
11208 22:59:17.933272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass>
11209 22:59:17.934100 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass
11211 22:59:17.939543 test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
11212 22:59:17.959206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass>
11213 22:59:17.959639
11214 22:59:17.960238 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass
11216 22:59:17.969450 Buffer ioctls (Input 0):
11217 22:59:17.976885 <LAVA_SIGNAL_TESTSET STOP>
11218 22:59:17.977569 Received signal: <TESTSET> STOP
11219 22:59:17.978001 Closing test_set Codec-ioctls-Input-0
11220 22:59:17.985698 <LAVA_SIGNAL_TESTSET START Buffer-ioctls-Input-0>
11221 22:59:17.986385 Received signal: <TESTSET> START Buffer-ioctls-Input-0
11222 22:59:17.986745 Starting test_set Buffer-ioctls-Input-0
11223 22:59:17.989329 test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
11224 22:59:18.015925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass>
11225 22:59:18.016523 test VIDIOC_EXPBUF: OK
11226 22:59:18.017140 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass
11228 22:59:18.037886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass>
11229 22:59:18.038573 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass
11231 22:59:18.040731 test Requests: OK (Not Supported)
11232 22:59:18.064279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Requests RESULT=pass>
11233 22:59:18.064762
11234 22:59:18.065553 Received signal: <TESTCASE> TEST_CASE_ID=Requests RESULT=pass
11236 22:59:18.075257 Test input 0:
11237 22:59:18.087026
11238 22:59:18.097072 Streaming ioctls:
11239 22:59:18.103789 <LAVA_SIGNAL_TESTSET STOP>
11240 22:59:18.104477 Received signal: <TESTSET> STOP
11241 22:59:18.104838 Closing test_set Buffer-ioctls-Input-0
11242 22:59:18.113701 <LAVA_SIGNAL_TESTSET START Streaming-ioctls_Test-input-0>
11243 22:59:18.114386 Received signal: <TESTSET> START Streaming-ioctls_Test-input-0
11244 22:59:18.114750 Starting test_set Streaming-ioctls_Test-input-0
11245 22:59:18.116808 test read/write: OK (Not Supported)
11246 22:59:18.137929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=read/write RESULT=pass>
11247 22:59:18.138632 Received signal: <TESTCASE> TEST_CASE_ID=read/write RESULT=pass
11249 22:59:18.141102 test blocking wait: OK
11250 22:59:18.162077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blocking-wait RESULT=pass>
11251 22:59:18.162801 Received signal: <TESTCASE> TEST_CASE_ID=blocking-wait RESULT=pass
11253 22:59:18.171296 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1346): node->streamon(q.g_type()) != EINVAL
11254 22:59:18.174962 test MMAP (no poll): FAIL
11255 22:59:18.201280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-no-poll RESULT=fail>
11256 22:59:18.202204 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-no-poll RESULT=fail
11258 22:59:18.211316 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1346): node->streamon(q.g_type()) != EINVAL
11259 22:59:18.214367 test MMAP (select): FAIL
11260 22:59:18.238596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-select RESULT=fail>
11261 22:59:18.239288 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-select RESULT=fail
11263 22:59:18.248865 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1346): node->streamon(q.g_type()) != EINVAL
11264 22:59:18.249406 test MMAP (epoll): FAIL
11265 22:59:18.271293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-epoll RESULT=fail>
11266 22:59:18.271816
11267 22:59:18.272415 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-epoll RESULT=fail
11269 22:59:18.283835
11270 22:59:18.478221
11271 22:59:18.485421 test USERPTR (no poll): OK
11272 22:59:18.511796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-no-poll RESULT=pass>
11273 22:59:18.512361
11274 22:59:18.513009 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-no-poll RESULT=pass
11276 22:59:18.528181
11277 22:59:18.716860
11278 22:59:18.724506 test USERPTR (select): OK
11279 22:59:18.752623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-select RESULT=pass>
11280 22:59:18.753434 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-select RESULT=pass
11282 22:59:18.759244 test DMABUF: Cannot test, specify --expbuf-device
11283 22:59:18.764283
11284 22:59:18.782483 Total for uvcvideo device /dev/video0: 53, Succeeded: 50, Failed: 3, Warnings: 3
11285 22:59:18.788789 <LAVA_TEST_RUNNER EXIT>
11286 22:59:18.789708 ok: lava_test_shell seems to have completed
11287 22:59:18.790141 Marking unfinished test run as failed
11289 22:59:18.796087 Composing:
result: pass
set: Format-ioctls-Input-0
Cropping:
result: pass
set: Format-ioctls-Input-0
MC-information-see-Media-Driver-Info-above:
result: pass
set: Required-ioctls
MMAP-epoll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-no-poll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-select:
result: fail
set: Streaming-ioctls_Test-input-0
Requests:
result: pass
set: Buffer-ioctls-Input-0
Scaling:
result: pass
set: Format-ioctls-Input-0
USERPTR-no-poll:
result: pass
set: Streaming-ioctls_Test-input-0
USERPTR-select:
result: pass
set: Streaming-ioctls_Test-input-0
VIDIOC_DBG_G/S_REGISTER:
result: pass
set: Debug-ioctls
VIDIOC_DV_TIMINGS_CAP:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_STD:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDIO:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDOUT:
result: pass
set: Input-ioctls
VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS:
result: pass
set: Format-ioctls-Input-0
VIDIOC_EXPBUF:
result: pass
set: Buffer-ioctls-Input-0
VIDIOC_G/S/ENUMINPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/ENUMOUTPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/TRY_EXT_CTRLS:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_AUDIO:
result: pass
set: Input-ioctls
VIDIOC_G/S_AUDOUT:
result: pass
set: Input-ioctls
VIDIOC_G/S_CTRL:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_EDID:
result: pass
set: Input-ioctls
VIDIOC_G/S_FREQUENCY:
result: pass
set: Input-ioctls
VIDIOC_G/S_JPEGCOMP:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_MODULATOR:
result: pass
set: Input-ioctls
VIDIOC_G/S_PARM:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G/S_PRIORITY:
result: pass
set: Allow-for-multiple-opens
VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS:
result: pass
set: Input-ioctls
VIDIOC_G_ENC_INDEX:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_G_FBUF:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G_SLICED_VBI_CAP:
result: pass
set: Format-ioctls-Input-0
VIDIOC_LOG_STATUS:
result: pass
set: Debug-ioctls
VIDIOC_QUERYCAP:
result: pass
set: Allow-for-multiple-opens
VIDIOC_QUERYCTRL:
result: pass
set: Control-ioctls-Input-0
VIDIOC_QUERY_EXT_CTRL/QUERYMENU:
result: pass
set: Control-ioctls-Input-0
VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF:
result: pass
set: Buffer-ioctls-Input-0
VIDIOC_S_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_S_HW_FREQ_SEEK:
result: pass
set: Input-ioctls
VIDIOC_TRY_DECODER_CMD:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_TRY_ENCODER_CMD:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_TRY_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT:
result: pass
set: Control-ioctls-Input-0
blocking-wait:
result: pass
set: Streaming-ioctls_Test-input-0
device-presence: pass
for-unlimited-opens:
result: pass
set: Allow-for-multiple-opens
invalid-ioctls:
result: pass
set: Required-ioctls
read/write:
result: pass
set: Streaming-ioctls_Test-input-0
second-/dev/video0-open:
result: pass
set: Allow-for-multiple-opens
11290 22:59:18.796795 end: 3.1 lava-test-shell (duration 00:00:10) [common]
11291 22:59:18.797284 end: 3 lava-test-retry (duration 00:00:10) [common]
11292 22:59:18.797829 start: 4 finalize (timeout 00:08:00) [common]
11293 22:59:18.798339 start: 4.1 power-off (timeout 00:00:30) [common]
11294 22:59:18.799167 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=off'
11295 22:59:18.923369 >> Command sent successfully.
11296 22:59:18.933872 Returned 0 in 0 seconds
11297 22:59:19.035167 end: 4.1 power-off (duration 00:00:00) [common]
11299 22:59:19.036587 start: 4.2 read-feedback (timeout 00:08:00) [common]
11300 22:59:19.037852 Listened to connection for namespace 'common' for up to 1s
11301 22:59:20.037685 Finalising connection for namespace 'common'
11302 22:59:20.037868 Disconnecting from shell: Finalise
11303 22:59:20.037951 / #
11304 22:59:20.138402 end: 4.2 read-feedback (duration 00:00:01) [common]
11305 22:59:20.138754 end: 4 finalize (duration 00:00:01) [common]
11306 22:59:20.139023 Cleaning after the job
11307 22:59:20.139263 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12172390/tftp-deploy-rtufekp4/ramdisk
11308 22:59:20.147543 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12172390/tftp-deploy-rtufekp4/kernel
11309 22:59:20.155954 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12172390/tftp-deploy-rtufekp4/dtb
11310 22:59:20.156123 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12172390/tftp-deploy-rtufekp4/modules
11311 22:59:20.163552 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12172390
11312 22:59:20.230628 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12172390
11313 22:59:20.230811 Job finished correctly