Boot log: mt8192-asurada-spherion-r0
- Boot result: FAIL
- Warnings: 1
- Kernel Warnings: 13
- Kernel Errors: 27
- Errors: 4
1 23:05:51.800194 lava-dispatcher, installed at version: 2023.10
2 23:05:51.800410 start: 0 validate
3 23:05:51.800546 Start time: 2023-12-27 23:05:51.800538+00:00 (UTC)
4 23:05:51.800661 Using caching service: 'http://localhost/cache/?uri=%s'
5 23:05:51.800796 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 23:05:52.071460 Using caching service: 'http://localhost/cache/?uri=%s'
7 23:05:52.072145 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.66-cip11-rt6-10-g38253b8903b4%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 23:06:12.849010 Using caching service: 'http://localhost/cache/?uri=%s'
9 23:06:12.849200 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.66-cip11-rt6-10-g38253b8903b4%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 23:06:13.106425 Using caching service: 'http://localhost/cache/?uri=%s'
11 23:06:13.106604 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.66-cip11-rt6-10-g38253b8903b4%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 23:06:16.868875 validate duration: 25.07
14 23:06:16.870073 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 23:06:16.870595 start: 1.1 download-retry (timeout 00:10:00) [common]
16 23:06:16.871034 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 23:06:16.871664 Not decompressing ramdisk as can be used compressed.
18 23:06:16.872145 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230623.0/arm64/rootfs.cpio.gz
19 23:06:16.872518 saving as /var/lib/lava/dispatcher/tmp/12395373/tftp-deploy-dxcbkafh/ramdisk/rootfs.cpio.gz
20 23:06:16.872857 total size: 8181372 (7 MB)
21 23:06:17.133665 progress 0 % (0 MB)
22 23:06:17.136297 progress 5 % (0 MB)
23 23:06:17.138839 progress 10 % (0 MB)
24 23:06:17.141279 progress 15 % (1 MB)
25 23:06:17.143591 progress 20 % (1 MB)
26 23:06:17.146043 progress 25 % (1 MB)
27 23:06:17.148288 progress 30 % (2 MB)
28 23:06:17.150601 progress 35 % (2 MB)
29 23:06:17.152781 progress 40 % (3 MB)
30 23:06:17.155199 progress 45 % (3 MB)
31 23:06:17.157356 progress 50 % (3 MB)
32 23:06:17.159636 progress 55 % (4 MB)
33 23:06:17.161764 progress 60 % (4 MB)
34 23:06:17.164225 progress 65 % (5 MB)
35 23:06:17.166327 progress 70 % (5 MB)
36 23:06:17.168632 progress 75 % (5 MB)
37 23:06:17.170816 progress 80 % (6 MB)
38 23:06:17.173169 progress 85 % (6 MB)
39 23:06:17.175342 progress 90 % (7 MB)
40 23:06:17.177616 progress 95 % (7 MB)
41 23:06:17.179696 progress 100 % (7 MB)
42 23:06:17.179896 7 MB downloaded in 0.31 s (25.41 MB/s)
43 23:06:17.180055 end: 1.1.1 http-download (duration 00:00:00) [common]
45 23:06:17.180432 end: 1.1 download-retry (duration 00:00:00) [common]
46 23:06:17.180593 start: 1.2 download-retry (timeout 00:10:00) [common]
47 23:06:17.180712 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 23:06:17.180897 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.66-cip11-rt6-10-g38253b8903b4/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 23:06:17.180983 saving as /var/lib/lava/dispatcher/tmp/12395373/tftp-deploy-dxcbkafh/kernel/Image
50 23:06:17.181064 total size: 50024960 (47 MB)
51 23:06:17.181158 No compression specified
52 23:06:17.182359 progress 0 % (0 MB)
53 23:06:17.195835 progress 5 % (2 MB)
54 23:06:17.209148 progress 10 % (4 MB)
55 23:06:17.223537 progress 15 % (7 MB)
56 23:06:17.237255 progress 20 % (9 MB)
57 23:06:17.250715 progress 25 % (11 MB)
58 23:06:17.263897 progress 30 % (14 MB)
59 23:06:17.277318 progress 35 % (16 MB)
60 23:06:17.290991 progress 40 % (19 MB)
61 23:06:17.304304 progress 45 % (21 MB)
62 23:06:17.317757 progress 50 % (23 MB)
63 23:06:17.331060 progress 55 % (26 MB)
64 23:06:17.344401 progress 60 % (28 MB)
65 23:06:17.357817 progress 65 % (31 MB)
66 23:06:17.371760 progress 70 % (33 MB)
67 23:06:17.384993 progress 75 % (35 MB)
68 23:06:17.398472 progress 80 % (38 MB)
69 23:06:17.411857 progress 85 % (40 MB)
70 23:06:17.425080 progress 90 % (42 MB)
71 23:06:17.438395 progress 95 % (45 MB)
72 23:06:17.451340 progress 100 % (47 MB)
73 23:06:17.451620 47 MB downloaded in 0.27 s (176.34 MB/s)
74 23:06:17.451799 end: 1.2.1 http-download (duration 00:00:00) [common]
76 23:06:17.452059 end: 1.2 download-retry (duration 00:00:00) [common]
77 23:06:17.452149 start: 1.3 download-retry (timeout 00:09:59) [common]
78 23:06:17.452239 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 23:06:17.452383 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.66-cip11-rt6-10-g38253b8903b4/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 23:06:17.452455 saving as /var/lib/lava/dispatcher/tmp/12395373/tftp-deploy-dxcbkafh/dtb/mt8192-asurada-spherion-r0.dtb
81 23:06:17.452518 total size: 47278 (0 MB)
82 23:06:17.452581 No compression specified
83 23:06:17.453813 progress 69 % (0 MB)
84 23:06:17.454097 progress 100 % (0 MB)
85 23:06:17.454259 0 MB downloaded in 0.00 s (25.94 MB/s)
86 23:06:17.454387 end: 1.3.1 http-download (duration 00:00:00) [common]
88 23:06:17.454617 end: 1.3 download-retry (duration 00:00:00) [common]
89 23:06:17.454708 start: 1.4 download-retry (timeout 00:09:59) [common]
90 23:06:17.454792 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 23:06:17.454911 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.66-cip11-rt6-10-g38253b8903b4/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 23:06:17.454982 saving as /var/lib/lava/dispatcher/tmp/12395373/tftp-deploy-dxcbkafh/modules/modules.tar
93 23:06:17.455044 total size: 8633892 (8 MB)
94 23:06:17.455107 Using unxz to decompress xz
95 23:06:17.459402 progress 0 % (0 MB)
96 23:06:17.480851 progress 5 % (0 MB)
97 23:06:17.505473 progress 10 % (0 MB)
98 23:06:17.530873 progress 15 % (1 MB)
99 23:06:17.555712 progress 20 % (1 MB)
100 23:06:17.581406 progress 25 % (2 MB)
101 23:06:17.609737 progress 30 % (2 MB)
102 23:06:17.636357 progress 35 % (2 MB)
103 23:06:17.661841 progress 40 % (3 MB)
104 23:06:17.688050 progress 45 % (3 MB)
105 23:06:17.715412 progress 50 % (4 MB)
106 23:06:17.742125 progress 55 % (4 MB)
107 23:06:17.771030 progress 60 % (4 MB)
108 23:06:17.798642 progress 65 % (5 MB)
109 23:06:17.825813 progress 70 % (5 MB)
110 23:06:17.851744 progress 75 % (6 MB)
111 23:06:17.881557 progress 80 % (6 MB)
112 23:06:17.910065 progress 85 % (7 MB)
113 23:06:17.938666 progress 90 % (7 MB)
114 23:06:17.969487 progress 95 % (7 MB)
115 23:06:17.999545 progress 100 % (8 MB)
116 23:06:18.005336 8 MB downloaded in 0.55 s (14.96 MB/s)
117 23:06:18.005605 end: 1.4.1 http-download (duration 00:00:01) [common]
119 23:06:18.005904 end: 1.4 download-retry (duration 00:00:01) [common]
120 23:06:18.006031 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 23:06:18.006164 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 23:06:18.006279 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 23:06:18.006400 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 23:06:18.006682 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12395373/lava-overlay-c1vmpzir
125 23:06:18.006878 makedir: /var/lib/lava/dispatcher/tmp/12395373/lava-overlay-c1vmpzir/lava-12395373/bin
126 23:06:18.007023 makedir: /var/lib/lava/dispatcher/tmp/12395373/lava-overlay-c1vmpzir/lava-12395373/tests
127 23:06:18.007159 makedir: /var/lib/lava/dispatcher/tmp/12395373/lava-overlay-c1vmpzir/lava-12395373/results
128 23:06:18.007314 Creating /var/lib/lava/dispatcher/tmp/12395373/lava-overlay-c1vmpzir/lava-12395373/bin/lava-add-keys
129 23:06:18.007499 Creating /var/lib/lava/dispatcher/tmp/12395373/lava-overlay-c1vmpzir/lava-12395373/bin/lava-add-sources
130 23:06:18.007635 Creating /var/lib/lava/dispatcher/tmp/12395373/lava-overlay-c1vmpzir/lava-12395373/bin/lava-background-process-start
131 23:06:18.007770 Creating /var/lib/lava/dispatcher/tmp/12395373/lava-overlay-c1vmpzir/lava-12395373/bin/lava-background-process-stop
132 23:06:18.007927 Creating /var/lib/lava/dispatcher/tmp/12395373/lava-overlay-c1vmpzir/lava-12395373/bin/lava-common-functions
133 23:06:18.008058 Creating /var/lib/lava/dispatcher/tmp/12395373/lava-overlay-c1vmpzir/lava-12395373/bin/lava-echo-ipv4
134 23:06:18.008190 Creating /var/lib/lava/dispatcher/tmp/12395373/lava-overlay-c1vmpzir/lava-12395373/bin/lava-install-packages
135 23:06:18.008322 Creating /var/lib/lava/dispatcher/tmp/12395373/lava-overlay-c1vmpzir/lava-12395373/bin/lava-installed-packages
136 23:06:18.008460 Creating /var/lib/lava/dispatcher/tmp/12395373/lava-overlay-c1vmpzir/lava-12395373/bin/lava-os-build
137 23:06:18.008593 Creating /var/lib/lava/dispatcher/tmp/12395373/lava-overlay-c1vmpzir/lava-12395373/bin/lava-probe-channel
138 23:06:18.008723 Creating /var/lib/lava/dispatcher/tmp/12395373/lava-overlay-c1vmpzir/lava-12395373/bin/lava-probe-ip
139 23:06:18.008860 Creating /var/lib/lava/dispatcher/tmp/12395373/lava-overlay-c1vmpzir/lava-12395373/bin/lava-target-ip
140 23:06:18.009038 Creating /var/lib/lava/dispatcher/tmp/12395373/lava-overlay-c1vmpzir/lava-12395373/bin/lava-target-mac
141 23:06:18.009186 Creating /var/lib/lava/dispatcher/tmp/12395373/lava-overlay-c1vmpzir/lava-12395373/bin/lava-target-storage
142 23:06:18.009325 Creating /var/lib/lava/dispatcher/tmp/12395373/lava-overlay-c1vmpzir/lava-12395373/bin/lava-test-case
143 23:06:18.009456 Creating /var/lib/lava/dispatcher/tmp/12395373/lava-overlay-c1vmpzir/lava-12395373/bin/lava-test-event
144 23:06:18.009584 Creating /var/lib/lava/dispatcher/tmp/12395373/lava-overlay-c1vmpzir/lava-12395373/bin/lava-test-feedback
145 23:06:18.009718 Creating /var/lib/lava/dispatcher/tmp/12395373/lava-overlay-c1vmpzir/lava-12395373/bin/lava-test-raise
146 23:06:18.009855 Creating /var/lib/lava/dispatcher/tmp/12395373/lava-overlay-c1vmpzir/lava-12395373/bin/lava-test-reference
147 23:06:18.009985 Creating /var/lib/lava/dispatcher/tmp/12395373/lava-overlay-c1vmpzir/lava-12395373/bin/lava-test-runner
148 23:06:18.010112 Creating /var/lib/lava/dispatcher/tmp/12395373/lava-overlay-c1vmpzir/lava-12395373/bin/lava-test-set
149 23:06:18.010261 Creating /var/lib/lava/dispatcher/tmp/12395373/lava-overlay-c1vmpzir/lava-12395373/bin/lava-test-shell
150 23:06:18.010432 Updating /var/lib/lava/dispatcher/tmp/12395373/lava-overlay-c1vmpzir/lava-12395373/bin/lava-install-packages (oe)
151 23:06:18.010630 Updating /var/lib/lava/dispatcher/tmp/12395373/lava-overlay-c1vmpzir/lava-12395373/bin/lava-installed-packages (oe)
152 23:06:18.010809 Creating /var/lib/lava/dispatcher/tmp/12395373/lava-overlay-c1vmpzir/lava-12395373/environment
153 23:06:18.010946 LAVA metadata
154 23:06:18.011026 - LAVA_JOB_ID=12395373
155 23:06:18.011091 - LAVA_DISPATCHER_IP=192.168.201.1
156 23:06:18.011207 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 23:06:18.011278 skipped lava-vland-overlay
158 23:06:18.011355 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 23:06:18.011453 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 23:06:18.011516 skipped lava-multinode-overlay
161 23:06:18.011593 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 23:06:18.011702 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 23:06:18.011815 Loading test definitions
164 23:06:18.011914 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 23:06:18.011992 Using /lava-12395373 at stage 0
166 23:06:18.012336 uuid=12395373_1.5.2.3.1 testdef=None
167 23:06:18.012429 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 23:06:18.012514 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 23:06:18.013311 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 23:06:18.013675 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 23:06:18.014569 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 23:06:18.014805 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 23:06:18.015642 runner path: /var/lib/lava/dispatcher/tmp/12395373/lava-overlay-c1vmpzir/lava-12395373/0/tests/0_dmesg test_uuid 12395373_1.5.2.3.1
176 23:06:18.015807 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 23:06:18.016037 start: 1.5.2.3.5 inline-repo-action (timeout 00:09:59) [common]
179 23:06:18.016109 Using /lava-12395373 at stage 1
180 23:06:18.016437 uuid=12395373_1.5.2.3.5 testdef=None
181 23:06:18.016528 end: 1.5.2.3.5 inline-repo-action (duration 00:00:00) [common]
182 23:06:18.016613 start: 1.5.2.3.6 test-overlay (timeout 00:09:59) [common]
183 23:06:18.017114 end: 1.5.2.3.6 test-overlay (duration 00:00:00) [common]
185 23:06:18.017346 start: 1.5.2.3.7 test-install-overlay (timeout 00:09:59) [common]
186 23:06:18.018648 end: 1.5.2.3.7 test-install-overlay (duration 00:00:00) [common]
188 23:06:18.019024 start: 1.5.2.3.8 test-runscript-overlay (timeout 00:09:59) [common]
189 23:06:18.019817 runner path: /var/lib/lava/dispatcher/tmp/12395373/lava-overlay-c1vmpzir/lava-12395373/1/tests/1_bootrr test_uuid 12395373_1.5.2.3.5
190 23:06:18.019976 end: 1.5.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
192 23:06:18.020318 Creating lava-test-runner.conf files
193 23:06:18.020414 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12395373/lava-overlay-c1vmpzir/lava-12395373/0 for stage 0
194 23:06:18.020537 - 0_dmesg
195 23:06:18.020666 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12395373/lava-overlay-c1vmpzir/lava-12395373/1 for stage 1
196 23:06:18.020783 - 1_bootrr
197 23:06:18.020883 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
198 23:06:18.020970 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
199 23:06:18.029578 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
200 23:06:18.029720 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
201 23:06:18.029832 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
202 23:06:18.029962 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
203 23:06:18.030077 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
204 23:06:18.296294 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:00) [common]
205 23:06:18.296739 start: 1.5.4 extract-modules (timeout 00:09:59) [common]
206 23:06:18.296857 extracting modules file /var/lib/lava/dispatcher/tmp/12395373/tftp-deploy-dxcbkafh/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12395373/extract-overlay-ramdisk-xpx6fh92/ramdisk
207 23:06:18.533871 end: 1.5.4 extract-modules (duration 00:00:00) [common]
208 23:06:18.534044 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
209 23:06:18.534142 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12395373/compress-overlay-n6tvbty_/overlay-1.5.2.4.tar.gz to ramdisk
210 23:06:18.534213 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12395373/compress-overlay-n6tvbty_/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12395373/extract-overlay-ramdisk-xpx6fh92/ramdisk
211 23:06:18.542824 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
212 23:06:18.543021 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
213 23:06:18.543122 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
214 23:06:18.543213 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
215 23:06:18.543301 Building ramdisk /var/lib/lava/dispatcher/tmp/12395373/extract-overlay-ramdisk-xpx6fh92/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12395373/extract-overlay-ramdisk-xpx6fh92/ramdisk
216 23:06:18.965302 >> 145334 blocks
217 23:06:21.323313 rename /var/lib/lava/dispatcher/tmp/12395373/extract-overlay-ramdisk-xpx6fh92/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12395373/tftp-deploy-dxcbkafh/ramdisk/ramdisk.cpio.gz
218 23:06:21.323909 end: 1.5.7 compress-ramdisk (duration 00:00:03) [common]
219 23:06:21.324094 start: 1.5.8 prepare-kernel (timeout 00:09:56) [common]
220 23:06:21.324246 start: 1.5.8.1 prepare-fit (timeout 00:09:56) [common]
221 23:06:21.324411 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12395373/tftp-deploy-dxcbkafh/kernel/Image'
222 23:06:34.899193 Returned 0 in 13 seconds
223 23:06:34.999873 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12395373/tftp-deploy-dxcbkafh/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12395373/tftp-deploy-dxcbkafh/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12395373/tftp-deploy-dxcbkafh/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12395373/tftp-deploy-dxcbkafh/kernel/image.itb
224 23:06:35.426068 output: FIT description: Kernel Image image with one or more FDT blobs
225 23:06:35.426457 output: Created: Wed Dec 27 23:06:35 2023
226 23:06:35.426537 output: Image 0 (kernel-1)
227 23:06:35.426615 output: Description:
228 23:06:35.426679 output: Created: Wed Dec 27 23:06:35 2023
229 23:06:35.426742 output: Type: Kernel Image
230 23:06:35.426821 output: Compression: lzma compressed
231 23:06:35.426888 output: Data Size: 11480388 Bytes = 11211.32 KiB = 10.95 MiB
232 23:06:35.426972 output: Architecture: AArch64
233 23:06:35.427063 output: OS: Linux
234 23:06:35.427127 output: Load Address: 0x00000000
235 23:06:35.427230 output: Entry Point: 0x00000000
236 23:06:35.427322 output: Hash algo: crc32
237 23:06:35.427449 output: Hash value: a55b2f0b
238 23:06:35.427539 output: Image 1 (fdt-1)
239 23:06:35.427627 output: Description: mt8192-asurada-spherion-r0
240 23:06:35.427714 output: Created: Wed Dec 27 23:06:35 2023
241 23:06:35.427799 output: Type: Flat Device Tree
242 23:06:35.427883 output: Compression: uncompressed
243 23:06:35.427969 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
244 23:06:35.428054 output: Architecture: AArch64
245 23:06:35.428144 output: Hash algo: crc32
246 23:06:35.428236 output: Hash value: cc4352de
247 23:06:35.428320 output: Image 2 (ramdisk-1)
248 23:06:35.428409 output: Description: unavailable
249 23:06:35.428496 output: Created: Wed Dec 27 23:06:35 2023
250 23:06:35.428580 output: Type: RAMDisk Image
251 23:06:35.428669 output: Compression: Unknown Compression
252 23:06:35.428753 output: Data Size: 21388804 Bytes = 20887.50 KiB = 20.40 MiB
253 23:06:35.428841 output: Architecture: AArch64
254 23:06:35.428925 output: OS: Linux
255 23:06:35.429014 output: Load Address: unavailable
256 23:06:35.429099 output: Entry Point: unavailable
257 23:06:35.429186 output: Hash algo: crc32
258 23:06:35.429287 output: Hash value: 91404cbd
259 23:06:35.429374 output: Default Configuration: 'conf-1'
260 23:06:35.429460 output: Configuration 0 (conf-1)
261 23:06:35.429543 output: Description: mt8192-asurada-spherion-r0
262 23:06:35.429629 output: Kernel: kernel-1
263 23:06:35.429712 output: Init Ramdisk: ramdisk-1
264 23:06:35.429799 output: FDT: fdt-1
265 23:06:35.429882 output: Loadables: kernel-1
266 23:06:35.429971 output:
267 23:06:35.430230 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
268 23:06:35.430371 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
269 23:06:35.430492 end: 1.5 prepare-tftp-overlay (duration 00:00:17) [common]
270 23:06:35.430600 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:41) [common]
271 23:06:35.430716 No LXC device requested
272 23:06:35.430846 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
273 23:06:35.430971 start: 1.7 deploy-device-env (timeout 00:09:41) [common]
274 23:06:35.431083 end: 1.7 deploy-device-env (duration 00:00:00) [common]
275 23:06:35.431190 Checking files for TFTP limit of 4294967296 bytes.
276 23:06:35.431854 end: 1 tftp-deploy (duration 00:00:19) [common]
277 23:06:35.431995 start: 2 depthcharge-action (timeout 00:05:00) [common]
278 23:06:35.432122 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
279 23:06:35.432298 substitutions:
280 23:06:35.432394 - {DTB}: 12395373/tftp-deploy-dxcbkafh/dtb/mt8192-asurada-spherion-r0.dtb
281 23:06:35.432491 - {INITRD}: 12395373/tftp-deploy-dxcbkafh/ramdisk/ramdisk.cpio.gz
282 23:06:35.432582 - {KERNEL}: 12395373/tftp-deploy-dxcbkafh/kernel/Image
283 23:06:35.432672 - {LAVA_MAC}: None
284 23:06:35.432762 - {PRESEED_CONFIG}: None
285 23:06:35.432851 - {PRESEED_LOCAL}: None
286 23:06:35.432937 - {RAMDISK}: 12395373/tftp-deploy-dxcbkafh/ramdisk/ramdisk.cpio.gz
287 23:06:35.433023 - {ROOT_PART}: None
288 23:06:35.433109 - {ROOT}: None
289 23:06:35.433193 - {SERVER_IP}: 192.168.201.1
290 23:06:35.433278 - {TEE}: None
291 23:06:35.433362 Parsed boot commands:
292 23:06:35.433448 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
293 23:06:35.433687 Parsed boot commands: tftpboot 192.168.201.1 12395373/tftp-deploy-dxcbkafh/kernel/image.itb 12395373/tftp-deploy-dxcbkafh/kernel/cmdline
294 23:06:35.433811 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
295 23:06:35.433933 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
296 23:06:35.434048 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
297 23:06:35.434136 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
298 23:06:35.434234 Not connected, no need to disconnect.
299 23:06:35.434342 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
300 23:06:35.434460 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
301 23:06:35.434558 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-2'
302 23:06:35.438775 Setting prompt string to ['lava-test: # ']
303 23:06:35.439217 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
304 23:06:35.439358 end: 2.2.1 reset-connection (duration 00:00:00) [common]
305 23:06:35.439501 start: 2.2.2 reset-device (timeout 00:05:00) [common]
306 23:06:35.439829 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
307 23:06:35.440066 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-2' '--port=1' '--command=reboot'
308 23:06:40.582108 >> Command sent successfully.
309 23:06:40.585383 Returned 0 in 5 seconds
310 23:06:40.685819 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
312 23:06:40.686195 end: 2.2.2 reset-device (duration 00:00:05) [common]
313 23:06:40.686324 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
314 23:06:40.686449 Setting prompt string to 'Starting depthcharge on Spherion...'
315 23:06:40.686569 Changing prompt to 'Starting depthcharge on Spherion...'
316 23:06:40.686653 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
317 23:06:40.686936 [Enter `^Ec?' for help]
318 23:06:40.859722
319 23:06:40.859882
320 23:06:40.859955 F0: 102B 0000
321 23:06:40.860067
322 23:06:40.860147 F3: 1001 0000 [0200]
323 23:06:40.860238
324 23:06:40.862401 F3: 1001 0000
325 23:06:40.862490
326 23:06:40.862585 F7: 102D 0000
327 23:06:40.862648
328 23:06:40.862708 F1: 0000 0000
329 23:06:40.862768
330 23:06:40.866197 V0: 0000 0000 [0001]
331 23:06:40.866292
332 23:06:40.866391 00: 0007 8000
333 23:06:40.866486
334 23:06:40.870319 01: 0000 0000
335 23:06:40.870428
336 23:06:40.870526 BP: 0C00 0209 [0000]
337 23:06:40.870601
338 23:06:40.870691 G0: 1182 0000
339 23:06:40.873876
340 23:06:40.874028 EC: 0000 0021 [4000]
341 23:06:40.874099
342 23:06:40.877693 S7: 0000 0000 [0000]
343 23:06:40.877809
344 23:06:40.877915 CC: 0000 0000 [0001]
345 23:06:40.878004
346 23:06:40.878079 T0: 0000 0040 [010F]
347 23:06:40.880825
348 23:06:40.880984 Jump to BL
349 23:06:40.881054
350 23:06:40.905408
351 23:06:40.905558
352 23:06:40.905628
353 23:06:40.912181 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
354 23:06:40.915726 ARM64: Exception handlers installed.
355 23:06:40.919301 ARM64: Testing exception
356 23:06:40.922857 ARM64: Done test exception
357 23:06:40.930584 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
358 23:06:40.940779 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
359 23:06:40.947670 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
360 23:06:40.958069 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
361 23:06:40.964859 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
362 23:06:40.971029 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
363 23:06:40.981845 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
364 23:06:40.988651 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
365 23:06:41.008290 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
366 23:06:41.011530 WDT: Last reset was cold boot
367 23:06:41.014727 SPI1(PAD0) initialized at 2873684 Hz
368 23:06:41.017923 SPI5(PAD0) initialized at 992727 Hz
369 23:06:41.021314 VBOOT: Loading verstage.
370 23:06:41.028218 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
371 23:06:41.031881 FMAP: Found "FLASH" version 1.1 at 0x20000.
372 23:06:41.034979 FMAP: base = 0x0 size = 0x800000 #areas = 25
373 23:06:41.038180 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
374 23:06:41.045947 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
375 23:06:41.052063 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
376 23:06:41.063006 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
377 23:06:41.063188
378 23:06:41.063293
379 23:06:41.073007 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
380 23:06:41.076704 ARM64: Exception handlers installed.
381 23:06:41.079917 ARM64: Testing exception
382 23:06:41.080036 ARM64: Done test exception
383 23:06:41.087357 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
384 23:06:41.090595 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
385 23:06:41.104349 Probing TPM: . done!
386 23:06:41.104512 TPM ready after 0 ms
387 23:06:41.113976 Connected to device vid:did:rid of 1ae0:0028:00
388 23:06:41.119969 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
389 23:06:41.176653 Initialized TPM device CR50 revision 0
390 23:06:41.188112 tlcl_send_startup: Startup return code is 0
391 23:06:41.188273 TPM: setup succeeded
392 23:06:41.199851 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
393 23:06:41.208661 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
394 23:06:41.220597 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
395 23:06:41.230446 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
396 23:06:41.233780 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
397 23:06:41.239280 in-header: 03 07 00 00 08 00 00 00
398 23:06:41.243159 in-data: aa e4 47 04 13 02 00 00
399 23:06:41.246565 Chrome EC: UHEPI supported
400 23:06:41.253386 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
401 23:06:41.256554 in-header: 03 95 00 00 08 00 00 00
402 23:06:41.260768 in-data: 18 20 20 08 00 00 00 00
403 23:06:41.260852 Phase 1
404 23:06:41.263984 FMAP: area GBB found @ 3f5000 (12032 bytes)
405 23:06:41.271078 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
406 23:06:41.275215 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
407 23:06:41.278381 Recovery requested (1009000e)
408 23:06:41.288204 TPM: Extending digest for VBOOT: boot mode into PCR 0
409 23:06:41.293563 tlcl_extend: response is 0
410 23:06:41.303009 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
411 23:06:41.308566 tlcl_extend: response is 0
412 23:06:41.315753 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
413 23:06:41.335285 read SPI 0x210d4 0x2173b: 15140 us, 9050 KB/s, 72.400 Mbps
414 23:06:41.341778 BS: bootblock times (exec / console): total (unknown) / 148 ms
415 23:06:41.341936
416 23:06:41.342066
417 23:06:41.351996 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
418 23:06:41.355464 ARM64: Exception handlers installed.
419 23:06:41.358496 ARM64: Testing exception
420 23:06:41.358602 ARM64: Done test exception
421 23:06:41.380736 pmic_efuse_setting: Set efuses in 11 msecs
422 23:06:41.383729 pmwrap_interface_init: Select PMIF_VLD_RDY
423 23:06:41.391181 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
424 23:06:41.393775 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
425 23:06:41.400532 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
426 23:06:41.404349 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
427 23:06:41.407589 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
428 23:06:41.415152 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
429 23:06:41.418732 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
430 23:06:41.422170 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
431 23:06:41.430176 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
432 23:06:41.433445 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
433 23:06:41.437099 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
434 23:06:41.441526 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
435 23:06:41.447727 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
436 23:06:41.451940 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
437 23:06:41.459545 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
438 23:06:41.463929 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
439 23:06:41.470577 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
440 23:06:41.474174 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
441 23:06:41.481921 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
442 23:06:41.485401 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
443 23:06:41.492792 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
444 23:06:41.497025 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
445 23:06:41.504012 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
446 23:06:41.508392 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
447 23:06:41.515096 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
448 23:06:41.518879 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
449 23:06:41.526185 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
450 23:06:41.529800 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
451 23:06:41.533234 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
452 23:06:41.540798 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
453 23:06:41.544521 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
454 23:06:41.548402 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
455 23:06:41.555239 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
456 23:06:41.558908 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
457 23:06:41.566635 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
458 23:06:41.569848 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
459 23:06:41.574221 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
460 23:06:41.580937 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
461 23:06:41.584405 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
462 23:06:41.588125 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
463 23:06:41.591734 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
464 23:06:41.599087 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
465 23:06:41.603143 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
466 23:06:41.605997 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
467 23:06:41.609621 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
468 23:06:41.614014 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
469 23:06:41.621183 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
470 23:06:41.624393 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
471 23:06:41.628398 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
472 23:06:41.631669 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
473 23:06:41.635315 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
474 23:06:41.642954 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
475 23:06:41.653917 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
476 23:06:41.657495 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
477 23:06:41.664546 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
478 23:06:41.671967 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
479 23:06:41.679686 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
480 23:06:41.683538 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
481 23:06:41.686134 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
482 23:06:41.693916 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6b, sec=0x26
483 23:06:41.697394 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
484 23:06:41.705865 [RTC]rtc_osc_init,62: osc32con val = 0xde6b
485 23:06:41.709083 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
486 23:06:41.718695 [RTC]rtc_get_frequency_meter,154: input=15, output=853
487 23:06:41.727997 [RTC]rtc_get_frequency_meter,154: input=7, output=724
488 23:06:41.737189 [RTC]rtc_get_frequency_meter,154: input=11, output=789
489 23:06:41.746808 [RTC]rtc_get_frequency_meter,154: input=13, output=821
490 23:06:41.757125 [RTC]rtc_get_frequency_meter,154: input=12, output=805
491 23:06:41.765452 [RTC]rtc_get_frequency_meter,154: input=11, output=788
492 23:06:41.775671 [RTC]rtc_get_frequency_meter,154: input=12, output=805
493 23:06:41.779247 [RTC]rtc_eosc_cali,47: left: 11, middle: 11, right: 12
494 23:06:41.785704 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6b
495 23:06:41.789797 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
496 23:06:41.793496 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
497 23:06:41.797030 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
498 23:06:41.800233 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
499 23:06:41.803611 ADC[4]: Raw value=905541 ID=7
500 23:06:41.807467 ADC[3]: Raw value=213916 ID=1
501 23:06:41.807582 RAM Code: 0x71
502 23:06:41.811472 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
503 23:06:41.818582 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
504 23:06:41.825615 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
505 23:06:41.832813 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
506 23:06:41.836931 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
507 23:06:41.840113 in-header: 03 07 00 00 08 00 00 00
508 23:06:41.843980 in-data: aa e4 47 04 13 02 00 00
509 23:06:41.844095 Chrome EC: UHEPI supported
510 23:06:41.850478 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
511 23:06:41.854710 in-header: 03 95 00 00 08 00 00 00
512 23:06:41.858175 in-data: 18 20 20 08 00 00 00 00
513 23:06:41.861807 MRC: failed to locate region type 0.
514 23:06:41.868756 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
515 23:06:41.872937 DRAM-K: Running full calibration
516 23:06:41.876991 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
517 23:06:41.880217 header.status = 0x0
518 23:06:41.884156 header.version = 0x6 (expected: 0x6)
519 23:06:41.888248 header.size = 0xd00 (expected: 0xd00)
520 23:06:41.888384 header.flags = 0x0
521 23:06:41.894662 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
522 23:06:41.911891 read SPI 0x72590 0x1c583: 12501 us, 9287 KB/s, 74.296 Mbps
523 23:06:41.919696 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
524 23:06:41.923260 dram_init: ddr_geometry: 2
525 23:06:41.923395 [EMI] MDL number = 2
526 23:06:41.927105 [EMI] Get MDL freq = 0
527 23:06:41.927227 dram_init: ddr_type: 0
528 23:06:41.930273 is_discrete_lpddr4: 1
529 23:06:41.933750 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
530 23:06:41.933902
531 23:06:41.934003
532 23:06:41.937999 [Bian_co] ETT version 0.0.0.1
533 23:06:41.941353 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
534 23:06:41.941503
535 23:06:41.944937 dramc_set_vcore_voltage set vcore to 650000
536 23:06:41.948688 Read voltage for 800, 4
537 23:06:41.948811 Vio18 = 0
538 23:06:41.948885 Vcore = 650000
539 23:06:41.948948 Vdram = 0
540 23:06:41.952306 Vddq = 0
541 23:06:41.952412 Vmddr = 0
542 23:06:41.955628 dram_init: config_dvfs: 1
543 23:06:41.958905 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
544 23:06:41.966001 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
545 23:06:41.969369 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
546 23:06:41.972907 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
547 23:06:41.976211 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
548 23:06:41.979338 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
549 23:06:41.983852 MEM_TYPE=3, freq_sel=18
550 23:06:41.986552 sv_algorithm_assistance_LP4_1600
551 23:06:41.990413 ============ PULL DRAM RESETB DOWN ============
552 23:06:41.993999 ========== PULL DRAM RESETB DOWN end =========
553 23:06:41.997729 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
554 23:06:42.000863 ===================================
555 23:06:42.004271 LPDDR4 DRAM CONFIGURATION
556 23:06:42.008050 ===================================
557 23:06:42.008153 EX_ROW_EN[0] = 0x0
558 23:06:42.010958 EX_ROW_EN[1] = 0x0
559 23:06:42.011046 LP4Y_EN = 0x0
560 23:06:42.014266 WORK_FSP = 0x0
561 23:06:42.014357 WL = 0x2
562 23:06:42.017763 RL = 0x2
563 23:06:42.017877 BL = 0x2
564 23:06:42.021520 RPST = 0x0
565 23:06:42.021607 RD_PRE = 0x0
566 23:06:42.025063 WR_PRE = 0x1
567 23:06:42.025150 WR_PST = 0x0
568 23:06:42.028804 DBI_WR = 0x0
569 23:06:42.028892 DBI_RD = 0x0
570 23:06:42.032519 OTF = 0x1
571 23:06:42.035203 ===================================
572 23:06:42.039151 ===================================
573 23:06:42.039268 ANA top config
574 23:06:42.042223 ===================================
575 23:06:42.045788 DLL_ASYNC_EN = 0
576 23:06:42.048789 ALL_SLAVE_EN = 1
577 23:06:42.048905 NEW_RANK_MODE = 1
578 23:06:42.052350 DLL_IDLE_MODE = 1
579 23:06:42.055760 LP45_APHY_COMB_EN = 1
580 23:06:42.058412 TX_ODT_DIS = 1
581 23:06:42.061845 NEW_8X_MODE = 1
582 23:06:42.065845 ===================================
583 23:06:42.069134 ===================================
584 23:06:42.069232 data_rate = 1600
585 23:06:42.072048 CKR = 1
586 23:06:42.075186 DQ_P2S_RATIO = 8
587 23:06:42.078850 ===================================
588 23:06:42.082082 CA_P2S_RATIO = 8
589 23:06:42.086001 DQ_CA_OPEN = 0
590 23:06:42.086092 DQ_SEMI_OPEN = 0
591 23:06:42.089037 CA_SEMI_OPEN = 0
592 23:06:42.092314 CA_FULL_RATE = 0
593 23:06:42.095819 DQ_CKDIV4_EN = 1
594 23:06:42.099150 CA_CKDIV4_EN = 1
595 23:06:42.102404 CA_PREDIV_EN = 0
596 23:06:42.102499 PH8_DLY = 0
597 23:06:42.105609 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
598 23:06:42.109084 DQ_AAMCK_DIV = 4
599 23:06:42.112182 CA_AAMCK_DIV = 4
600 23:06:42.115556 CA_ADMCK_DIV = 4
601 23:06:42.118997 DQ_TRACK_CA_EN = 0
602 23:06:42.119124 CA_PICK = 800
603 23:06:42.122309 CA_MCKIO = 800
604 23:06:42.125437 MCKIO_SEMI = 0
605 23:06:42.129548 PLL_FREQ = 3068
606 23:06:42.132821 DQ_UI_PI_RATIO = 32
607 23:06:42.137007 CA_UI_PI_RATIO = 0
608 23:06:42.137126 ===================================
609 23:06:42.140625 ===================================
610 23:06:42.144510 memory_type:LPDDR4
611 23:06:42.144622 GP_NUM : 10
612 23:06:42.147875 SRAM_EN : 1
613 23:06:42.151785 MD32_EN : 0
614 23:06:42.151900 ===================================
615 23:06:42.155168 [ANA_INIT] >>>>>>>>>>>>>>
616 23:06:42.158959 <<<<<< [CONFIGURE PHASE]: ANA_TX
617 23:06:42.163227 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
618 23:06:42.166263 ===================================
619 23:06:42.166417 data_rate = 1600,PCW = 0X7600
620 23:06:42.170422 ===================================
621 23:06:42.173043 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
622 23:06:42.179491 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
623 23:06:42.186349 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
624 23:06:42.189522 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
625 23:06:42.193480 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
626 23:06:42.196171 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
627 23:06:42.199740 [ANA_INIT] flow start
628 23:06:42.203496 [ANA_INIT] PLL >>>>>>>>
629 23:06:42.203610 [ANA_INIT] PLL <<<<<<<<
630 23:06:42.206211 [ANA_INIT] MIDPI >>>>>>>>
631 23:06:42.209354 [ANA_INIT] MIDPI <<<<<<<<
632 23:06:42.209462 [ANA_INIT] DLL >>>>>>>>
633 23:06:42.212821 [ANA_INIT] flow end
634 23:06:42.215973 ============ LP4 DIFF to SE enter ============
635 23:06:42.219336 ============ LP4 DIFF to SE exit ============
636 23:06:42.222762 [ANA_INIT] <<<<<<<<<<<<<
637 23:06:42.225922 [Flow] Enable top DCM control >>>>>
638 23:06:42.229459 [Flow] Enable top DCM control <<<<<
639 23:06:42.233105 Enable DLL master slave shuffle
640 23:06:42.239078 ==============================================================
641 23:06:42.239252 Gating Mode config
642 23:06:42.246058 ==============================================================
643 23:06:42.246199 Config description:
644 23:06:42.255784 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
645 23:06:42.262324 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
646 23:06:42.269344 SELPH_MODE 0: By rank 1: By Phase
647 23:06:42.273120 ==============================================================
648 23:06:42.275830 GAT_TRACK_EN = 1
649 23:06:42.279405 RX_GATING_MODE = 2
650 23:06:42.282245 RX_GATING_TRACK_MODE = 2
651 23:06:42.286027 SELPH_MODE = 1
652 23:06:42.288935 PICG_EARLY_EN = 1
653 23:06:42.292231 VALID_LAT_VALUE = 1
654 23:06:42.299057 ==============================================================
655 23:06:42.302291 Enter into Gating configuration >>>>
656 23:06:42.305871 Exit from Gating configuration <<<<
657 23:06:42.308903 Enter into DVFS_PRE_config >>>>>
658 23:06:42.318792 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
659 23:06:42.322133 Exit from DVFS_PRE_config <<<<<
660 23:06:42.325684 Enter into PICG configuration >>>>
661 23:06:42.329280 Exit from PICG configuration <<<<
662 23:06:42.332306 [RX_INPUT] configuration >>>>>
663 23:06:42.332446 [RX_INPUT] configuration <<<<<
664 23:06:42.339182 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
665 23:06:42.345452 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
666 23:06:42.348657 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
667 23:06:42.355640 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
668 23:06:42.361975 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
669 23:06:42.369086 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
670 23:06:42.372375 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
671 23:06:42.375169 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
672 23:06:42.382309 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
673 23:06:42.385547 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
674 23:06:42.388506 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
675 23:06:42.395443 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
676 23:06:42.395581 ===================================
677 23:06:42.399019 LPDDR4 DRAM CONFIGURATION
678 23:06:42.401987 ===================================
679 23:06:42.405192 EX_ROW_EN[0] = 0x0
680 23:06:42.405338 EX_ROW_EN[1] = 0x0
681 23:06:42.408447 LP4Y_EN = 0x0
682 23:06:42.408552 WORK_FSP = 0x0
683 23:06:42.411803 WL = 0x2
684 23:06:42.411899 RL = 0x2
685 23:06:42.415256 BL = 0x2
686 23:06:42.418335 RPST = 0x0
687 23:06:42.418437 RD_PRE = 0x0
688 23:06:42.421639 WR_PRE = 0x1
689 23:06:42.421733 WR_PST = 0x0
690 23:06:42.425456 DBI_WR = 0x0
691 23:06:42.425552 DBI_RD = 0x0
692 23:06:42.428240 OTF = 0x1
693 23:06:42.431876 ===================================
694 23:06:42.435000 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
695 23:06:42.438451 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
696 23:06:42.441650 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
697 23:06:42.445374 ===================================
698 23:06:42.448357 LPDDR4 DRAM CONFIGURATION
699 23:06:42.451879 ===================================
700 23:06:42.455067 EX_ROW_EN[0] = 0x10
701 23:06:42.455171 EX_ROW_EN[1] = 0x0
702 23:06:42.458222 LP4Y_EN = 0x0
703 23:06:42.458318 WORK_FSP = 0x0
704 23:06:42.461472 WL = 0x2
705 23:06:42.461563 RL = 0x2
706 23:06:42.465136 BL = 0x2
707 23:06:42.465273 RPST = 0x0
708 23:06:42.468065 RD_PRE = 0x0
709 23:06:42.471400 WR_PRE = 0x1
710 23:06:42.471539 WR_PST = 0x0
711 23:06:42.474702 DBI_WR = 0x0
712 23:06:42.474823 DBI_RD = 0x0
713 23:06:42.478555 OTF = 0x1
714 23:06:42.481640 ===================================
715 23:06:42.484707 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
716 23:06:42.490251 nWR fixed to 40
717 23:06:42.493663 [ModeRegInit_LP4] CH0 RK0
718 23:06:42.493810 [ModeRegInit_LP4] CH0 RK1
719 23:06:42.496855 [ModeRegInit_LP4] CH1 RK0
720 23:06:42.500365 [ModeRegInit_LP4] CH1 RK1
721 23:06:42.500500 match AC timing 13
722 23:06:42.507054 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
723 23:06:42.509899 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
724 23:06:42.513477 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
725 23:06:42.519960 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
726 23:06:42.523329 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
727 23:06:42.523465 [EMI DOE] emi_dcm 0
728 23:06:42.530009 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
729 23:06:42.530127 ==
730 23:06:42.533279 Dram Type= 6, Freq= 0, CH_0, rank 0
731 23:06:42.536544 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
732 23:06:42.536662 ==
733 23:06:42.543229 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
734 23:06:42.550127 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
735 23:06:42.557827 [CA 0] Center 38 (7~69) winsize 63
736 23:06:42.561247 [CA 1] Center 37 (7~68) winsize 62
737 23:06:42.564089 [CA 2] Center 34 (4~65) winsize 62
738 23:06:42.568450 [CA 3] Center 35 (4~66) winsize 63
739 23:06:42.570937 [CA 4] Center 34 (3~65) winsize 63
740 23:06:42.574152 [CA 5] Center 33 (3~64) winsize 62
741 23:06:42.574294
742 23:06:42.577498 [CmdBusTrainingLP45] Vref(ca) range 1: 34
743 23:06:42.577641
744 23:06:42.581030 [CATrainingPosCal] consider 1 rank data
745 23:06:42.584146 u2DelayCellTimex100 = 270/100 ps
746 23:06:42.587340 CA0 delay=38 (7~69),Diff = 5 PI (36 cell)
747 23:06:42.590839 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
748 23:06:42.597308 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
749 23:06:42.600853 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
750 23:06:42.604075 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
751 23:06:42.607598 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
752 23:06:42.607745
753 23:06:42.610636 CA PerBit enable=1, Macro0, CA PI delay=33
754 23:06:42.610779
755 23:06:42.614049 [CBTSetCACLKResult] CA Dly = 33
756 23:06:42.614209 CS Dly: 6 (0~37)
757 23:06:42.617544 ==
758 23:06:42.620715 Dram Type= 6, Freq= 0, CH_0, rank 1
759 23:06:42.624664 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
760 23:06:42.624809 ==
761 23:06:42.627099 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
762 23:06:42.634112 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
763 23:06:42.644537 [CA 0] Center 38 (7~69) winsize 63
764 23:06:42.647307 [CA 1] Center 37 (7~68) winsize 62
765 23:06:42.650556 [CA 2] Center 35 (4~66) winsize 63
766 23:06:42.654181 [CA 3] Center 35 (4~66) winsize 63
767 23:06:42.657457 [CA 4] Center 34 (3~65) winsize 63
768 23:06:42.660379 [CA 5] Center 33 (3~64) winsize 62
769 23:06:42.660473
770 23:06:42.663987 [CmdBusTrainingLP45] Vref(ca) range 1: 34
771 23:06:42.664126
772 23:06:42.667223 [CATrainingPosCal] consider 2 rank data
773 23:06:42.670555 u2DelayCellTimex100 = 270/100 ps
774 23:06:42.673945 CA0 delay=38 (7~69),Diff = 5 PI (36 cell)
775 23:06:42.680560 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
776 23:06:42.683480 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
777 23:06:42.687026 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
778 23:06:42.690409 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
779 23:06:42.693810 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
780 23:06:42.693926
781 23:06:42.697353 CA PerBit enable=1, Macro0, CA PI delay=33
782 23:06:42.697466
783 23:06:42.700125 [CBTSetCACLKResult] CA Dly = 33
784 23:06:42.700211 CS Dly: 6 (0~38)
785 23:06:42.703651
786 23:06:42.707376 ----->DramcWriteLeveling(PI) begin...
787 23:06:42.707466 ==
788 23:06:42.711007 Dram Type= 6, Freq= 0, CH_0, rank 0
789 23:06:42.714348 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
790 23:06:42.714449 ==
791 23:06:42.718359 Write leveling (Byte 0): 32 => 32
792 23:06:42.718458 Write leveling (Byte 1): 25 => 25
793 23:06:42.721969 DramcWriteLeveling(PI) end<-----
794 23:06:42.722069
795 23:06:42.722173 ==
796 23:06:42.725518 Dram Type= 6, Freq= 0, CH_0, rank 0
797 23:06:42.728548 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
798 23:06:42.731971 ==
799 23:06:42.732119 [Gating] SW mode calibration
800 23:06:42.739265 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
801 23:06:42.746286 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
802 23:06:42.749173 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
803 23:06:42.752622 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
804 23:06:42.759164 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
805 23:06:42.762576 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 23:06:42.765729 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 23:06:42.772191 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 23:06:42.775496 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 23:06:42.779448 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 23:06:42.786169 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 23:06:42.789126 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 23:06:42.792241 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
813 23:06:42.798926 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
814 23:06:42.802324 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
815 23:06:42.805727 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
816 23:06:42.812375 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
817 23:06:42.815750 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
818 23:06:42.818701 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
819 23:06:42.826042 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
820 23:06:42.828961 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
821 23:06:42.832225 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
822 23:06:42.839281 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 23:06:42.842429 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 23:06:42.845528 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 23:06:42.852182 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 23:06:42.855404 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 23:06:42.858644 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 23:06:42.865680 0 9 8 | B1->B0 | 2322 3131 | 1 0 | (0 0) (0 0)
829 23:06:42.868560 0 9 12 | B1->B0 | 2e2e 3434 | 1 1 | (1 1) (1 1)
830 23:06:42.871950 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
831 23:06:42.878348 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
832 23:06:42.881982 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
833 23:06:42.884835 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
834 23:06:42.891864 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
835 23:06:42.895035 0 10 4 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 0)
836 23:06:42.898242 0 10 8 | B1->B0 | 3131 2424 | 1 0 | (1 0) (0 0)
837 23:06:42.905306 0 10 12 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
838 23:06:42.908116 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
839 23:06:42.911433 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
840 23:06:42.918137 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
841 23:06:42.922156 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
842 23:06:42.924851 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
843 23:06:42.931737 0 11 4 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
844 23:06:42.934730 0 11 8 | B1->B0 | 2828 4545 | 0 0 | (0 0) (0 0)
845 23:06:42.937956 0 11 12 | B1->B0 | 3b3b 4646 | 0 0 | (1 1) (0 0)
846 23:06:42.941418 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
847 23:06:42.948244 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
848 23:06:42.951895 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
849 23:06:42.955421 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
850 23:06:42.961156 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
851 23:06:42.964502 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
852 23:06:42.968212 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
853 23:06:42.974819 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
854 23:06:42.978030 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
855 23:06:42.982032 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
856 23:06:42.987904 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
857 23:06:42.991407 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
858 23:06:42.994770 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
859 23:06:43.001066 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
860 23:06:43.004598 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
861 23:06:43.007972 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
862 23:06:43.014789 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
863 23:06:43.017761 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
864 23:06:43.021611 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
865 23:06:43.027931 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
866 23:06:43.031054 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
867 23:06:43.034486 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
868 23:06:43.041146 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
869 23:06:43.041286 Total UI for P1: 0, mck2ui 16
870 23:06:43.048181 best dqsien dly found for B0: ( 0, 14, 4)
871 23:06:43.051412 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
872 23:06:43.054933 Total UI for P1: 0, mck2ui 16
873 23:06:43.057597 best dqsien dly found for B1: ( 0, 14, 8)
874 23:06:43.061116 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
875 23:06:43.064633 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
876 23:06:43.064815
877 23:06:43.067589 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
878 23:06:43.071335 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
879 23:06:43.074284 [Gating] SW calibration Done
880 23:06:43.074401 ==
881 23:06:43.077418 Dram Type= 6, Freq= 0, CH_0, rank 0
882 23:06:43.081156 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
883 23:06:43.081337 ==
884 23:06:43.085521 RX Vref Scan: 0
885 23:06:43.085661
886 23:06:43.085787 RX Vref 0 -> 0, step: 1
887 23:06:43.085909
888 23:06:43.088705 RX Delay -130 -> 252, step: 16
889 23:06:43.091762 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
890 23:06:43.098169 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
891 23:06:43.101421 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
892 23:06:43.105340 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
893 23:06:43.108303 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
894 23:06:43.111555 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
895 23:06:43.117933 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
896 23:06:43.122372 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
897 23:06:43.124955 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
898 23:06:43.127887 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
899 23:06:43.131300 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
900 23:06:43.138772 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
901 23:06:43.142049 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
902 23:06:43.144698 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
903 23:06:43.148052 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
904 23:06:43.154635 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
905 23:06:43.154753 ==
906 23:06:43.158328 Dram Type= 6, Freq= 0, CH_0, rank 0
907 23:06:43.161525 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
908 23:06:43.161653 ==
909 23:06:43.161748 DQS Delay:
910 23:06:43.164506 DQS0 = 0, DQS1 = 0
911 23:06:43.164623 DQM Delay:
912 23:06:43.168213 DQM0 = 87, DQM1 = 75
913 23:06:43.168342 DQ Delay:
914 23:06:43.171914 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
915 23:06:43.174308 DQ4 =85, DQ5 =77, DQ6 =101, DQ7 =93
916 23:06:43.177979 DQ8 =69, DQ9 =53, DQ10 =69, DQ11 =69
917 23:06:43.180894 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
918 23:06:43.181025
919 23:06:43.181124
920 23:06:43.181219 ==
921 23:06:43.184215 Dram Type= 6, Freq= 0, CH_0, rank 0
922 23:06:43.188052 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
923 23:06:43.188177 ==
924 23:06:43.188276
925 23:06:43.190792
926 23:06:43.190905 TX Vref Scan disable
927 23:06:43.194706 == TX Byte 0 ==
928 23:06:43.198188 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
929 23:06:43.200781 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
930 23:06:43.204021 == TX Byte 1 ==
931 23:06:43.207682 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
932 23:06:43.210999 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
933 23:06:43.211111 ==
934 23:06:43.214089 Dram Type= 6, Freq= 0, CH_0, rank 0
935 23:06:43.220699 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
936 23:06:43.220826 ==
937 23:06:43.233404 TX Vref=22, minBit 4, minWin=26, winSum=435
938 23:06:43.236913 TX Vref=24, minBit 0, minWin=27, winSum=440
939 23:06:43.240078 TX Vref=26, minBit 1, minWin=27, winSum=442
940 23:06:43.243544 TX Vref=28, minBit 1, minWin=27, winSum=446
941 23:06:43.246751 TX Vref=30, minBit 1, minWin=27, winSum=453
942 23:06:43.253668 TX Vref=32, minBit 0, minWin=28, winSum=452
943 23:06:43.257008 [TxChooseVref] Worse bit 0, Min win 28, Win sum 452, Final Vref 32
944 23:06:43.257130
945 23:06:43.259913 Final TX Range 1 Vref 32
946 23:06:43.260032
947 23:06:43.260123 ==
948 23:06:43.263281 Dram Type= 6, Freq= 0, CH_0, rank 0
949 23:06:43.266647 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
950 23:06:43.269701 ==
951 23:06:43.269832
952 23:06:43.269932
953 23:06:43.270026 TX Vref Scan disable
954 23:06:43.273983 == TX Byte 0 ==
955 23:06:43.277184 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
956 23:06:43.280113 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
957 23:06:43.283373 == TX Byte 1 ==
958 23:06:43.286970 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
959 23:06:43.293709 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
960 23:06:43.293826
961 23:06:43.293925 [DATLAT]
962 23:06:43.294019 Freq=800, CH0 RK0
963 23:06:43.294113
964 23:06:43.296954 DATLAT Default: 0xa
965 23:06:43.297070 0, 0xFFFF, sum = 0
966 23:06:43.300420 1, 0xFFFF, sum = 0
967 23:06:43.300536 2, 0xFFFF, sum = 0
968 23:06:43.303565 3, 0xFFFF, sum = 0
969 23:06:43.306805 4, 0xFFFF, sum = 0
970 23:06:43.306920 5, 0xFFFF, sum = 0
971 23:06:43.310297 6, 0xFFFF, sum = 0
972 23:06:43.310413 7, 0xFFFF, sum = 0
973 23:06:43.313450 8, 0xFFFF, sum = 0
974 23:06:43.313563 9, 0x0, sum = 1
975 23:06:43.316598 10, 0x0, sum = 2
976 23:06:43.316709 11, 0x0, sum = 3
977 23:06:43.316809 12, 0x0, sum = 4
978 23:06:43.319863 best_step = 10
979 23:06:43.319987
980 23:06:43.320086 ==
981 23:06:43.323289 Dram Type= 6, Freq= 0, CH_0, rank 0
982 23:06:43.326767 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
983 23:06:43.326880 ==
984 23:06:43.330055 RX Vref Scan: 1
985 23:06:43.330166
986 23:06:43.333276 Set Vref Range= 32 -> 127
987 23:06:43.333388
988 23:06:43.333484 RX Vref 32 -> 127, step: 1
989 23:06:43.333578
990 23:06:43.336629 RX Delay -111 -> 252, step: 8
991 23:06:43.336739
992 23:06:43.339696 Set Vref, RX VrefLevel [Byte0]: 32
993 23:06:43.343255 [Byte1]: 32
994 23:06:43.346341
995 23:06:43.346465 Set Vref, RX VrefLevel [Byte0]: 33
996 23:06:43.349656 [Byte1]: 33
997 23:06:43.354304
998 23:06:43.354430 Set Vref, RX VrefLevel [Byte0]: 34
999 23:06:43.357437 [Byte1]: 34
1000 23:06:43.362070
1001 23:06:43.362197 Set Vref, RX VrefLevel [Byte0]: 35
1002 23:06:43.365464 [Byte1]: 35
1003 23:06:43.369423
1004 23:06:43.369554 Set Vref, RX VrefLevel [Byte0]: 36
1005 23:06:43.372904 [Byte1]: 36
1006 23:06:43.377270
1007 23:06:43.377390 Set Vref, RX VrefLevel [Byte0]: 37
1008 23:06:43.381387 [Byte1]: 37
1009 23:06:43.385110
1010 23:06:43.385231 Set Vref, RX VrefLevel [Byte0]: 38
1011 23:06:43.388278 [Byte1]: 38
1012 23:06:43.393231
1013 23:06:43.393352 Set Vref, RX VrefLevel [Byte0]: 39
1014 23:06:43.396450 [Byte1]: 39
1015 23:06:43.400722
1016 23:06:43.400847 Set Vref, RX VrefLevel [Byte0]: 40
1017 23:06:43.403853 [Byte1]: 40
1018 23:06:43.407850
1019 23:06:43.407965 Set Vref, RX VrefLevel [Byte0]: 41
1020 23:06:43.411623 [Byte1]: 41
1021 23:06:43.415677
1022 23:06:43.415790 Set Vref, RX VrefLevel [Byte0]: 42
1023 23:06:43.418338 [Byte1]: 42
1024 23:06:43.422931
1025 23:06:43.423052 Set Vref, RX VrefLevel [Byte0]: 43
1026 23:06:43.426002 [Byte1]: 43
1027 23:06:43.430860
1028 23:06:43.430991 Set Vref, RX VrefLevel [Byte0]: 44
1029 23:06:43.433895 [Byte1]: 44
1030 23:06:43.438217
1031 23:06:43.438339 Set Vref, RX VrefLevel [Byte0]: 45
1032 23:06:43.441303 [Byte1]: 45
1033 23:06:43.445480
1034 23:06:43.445602 Set Vref, RX VrefLevel [Byte0]: 46
1035 23:06:43.449084 [Byte1]: 46
1036 23:06:43.453564
1037 23:06:43.453690 Set Vref, RX VrefLevel [Byte0]: 47
1038 23:06:43.456826 [Byte1]: 47
1039 23:06:43.461049
1040 23:06:43.461166 Set Vref, RX VrefLevel [Byte0]: 48
1041 23:06:43.464274 [Byte1]: 48
1042 23:06:43.468815
1043 23:06:43.468962 Set Vref, RX VrefLevel [Byte0]: 49
1044 23:06:43.471946 [Byte1]: 49
1045 23:06:43.476719
1046 23:06:43.476885 Set Vref, RX VrefLevel [Byte0]: 50
1047 23:06:43.480453 [Byte1]: 50
1048 23:06:43.484087
1049 23:06:43.484187 Set Vref, RX VrefLevel [Byte0]: 51
1050 23:06:43.487230 [Byte1]: 51
1051 23:06:43.491552
1052 23:06:43.491638 Set Vref, RX VrefLevel [Byte0]: 52
1053 23:06:43.495333 [Byte1]: 52
1054 23:06:43.499520
1055 23:06:43.499604 Set Vref, RX VrefLevel [Byte0]: 53
1056 23:06:43.502741 [Byte1]: 53
1057 23:06:43.506753
1058 23:06:43.506889 Set Vref, RX VrefLevel [Byte0]: 54
1059 23:06:43.510335 [Byte1]: 54
1060 23:06:43.515105
1061 23:06:43.515200 Set Vref, RX VrefLevel [Byte0]: 55
1062 23:06:43.517930 [Byte1]: 55
1063 23:06:43.522185
1064 23:06:43.522267 Set Vref, RX VrefLevel [Byte0]: 56
1065 23:06:43.525526 [Byte1]: 56
1066 23:06:43.529939
1067 23:06:43.530050 Set Vref, RX VrefLevel [Byte0]: 57
1068 23:06:43.533290 [Byte1]: 57
1069 23:06:43.537459
1070 23:06:43.537541 Set Vref, RX VrefLevel [Byte0]: 58
1071 23:06:43.540903 [Byte1]: 58
1072 23:06:43.545314
1073 23:06:43.545424 Set Vref, RX VrefLevel [Byte0]: 59
1074 23:06:43.548337 [Byte1]: 59
1075 23:06:43.552631
1076 23:06:43.552778 Set Vref, RX VrefLevel [Byte0]: 60
1077 23:06:43.555973 [Byte1]: 60
1078 23:06:43.560581
1079 23:06:43.560666 Set Vref, RX VrefLevel [Byte0]: 61
1080 23:06:43.563627 [Byte1]: 61
1081 23:06:43.568281
1082 23:06:43.568367 Set Vref, RX VrefLevel [Byte0]: 62
1083 23:06:43.571635 [Byte1]: 62
1084 23:06:43.575603
1085 23:06:43.575686 Set Vref, RX VrefLevel [Byte0]: 63
1086 23:06:43.579318 [Byte1]: 63
1087 23:06:43.583259
1088 23:06:43.583386 Set Vref, RX VrefLevel [Byte0]: 64
1089 23:06:43.586776 [Byte1]: 64
1090 23:06:43.590913
1091 23:06:43.590995 Set Vref, RX VrefLevel [Byte0]: 65
1092 23:06:43.594545 [Byte1]: 65
1093 23:06:43.598544
1094 23:06:43.598627 Set Vref, RX VrefLevel [Byte0]: 66
1095 23:06:43.601755 [Byte1]: 66
1096 23:06:43.607033
1097 23:06:43.607143 Set Vref, RX VrefLevel [Byte0]: 67
1098 23:06:43.609765 [Byte1]: 67
1099 23:06:43.614032
1100 23:06:43.614121 Set Vref, RX VrefLevel [Byte0]: 68
1101 23:06:43.618117 [Byte1]: 68
1102 23:06:43.621387
1103 23:06:43.621475 Set Vref, RX VrefLevel [Byte0]: 69
1104 23:06:43.624782 [Byte1]: 69
1105 23:06:43.629471
1106 23:06:43.629562 Set Vref, RX VrefLevel [Byte0]: 70
1107 23:06:43.632723 [Byte1]: 70
1108 23:06:43.637113
1109 23:06:43.637199 Set Vref, RX VrefLevel [Byte0]: 71
1110 23:06:43.640268 [Byte1]: 71
1111 23:06:43.644624
1112 23:06:43.644707 Set Vref, RX VrefLevel [Byte0]: 72
1113 23:06:43.647725 [Byte1]: 72
1114 23:06:43.652203
1115 23:06:43.652329 Set Vref, RX VrefLevel [Byte0]: 73
1116 23:06:43.655677 [Byte1]: 73
1117 23:06:43.659698
1118 23:06:43.659811 Set Vref, RX VrefLevel [Byte0]: 74
1119 23:06:43.663287 [Byte1]: 74
1120 23:06:43.667241
1121 23:06:43.667368 Final RX Vref Byte 0 = 58 to rank0
1122 23:06:43.671060 Final RX Vref Byte 1 = 59 to rank0
1123 23:06:43.674269 Final RX Vref Byte 0 = 58 to rank1
1124 23:06:43.677615 Final RX Vref Byte 1 = 59 to rank1==
1125 23:06:43.680839 Dram Type= 6, Freq= 0, CH_0, rank 0
1126 23:06:43.687802 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1127 23:06:43.687892 ==
1128 23:06:43.688031 DQS Delay:
1129 23:06:43.688095 DQS0 = 0, DQS1 = 0
1130 23:06:43.691049 DQM Delay:
1131 23:06:43.691155 DQM0 = 88, DQM1 = 77
1132 23:06:43.694041 DQ Delay:
1133 23:06:43.697358 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1134 23:06:43.697470 DQ4 =88, DQ5 =80, DQ6 =96, DQ7 =96
1135 23:06:43.700587 DQ8 =68, DQ9 =60, DQ10 =80, DQ11 =72
1136 23:06:43.704559 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =84
1137 23:06:43.707632
1138 23:06:43.707750
1139 23:06:43.713959 [DQSOSCAuto] RK0, (LSB)MR18= 0x3028, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 397 ps
1140 23:06:43.717458 CH0 RK0: MR19=606, MR18=3028
1141 23:06:43.724205 CH0_RK0: MR19=0x606, MR18=0x3028, DQSOSC=397, MR23=63, INC=93, DEC=62
1142 23:06:43.724324
1143 23:06:43.727417 ----->DramcWriteLeveling(PI) begin...
1144 23:06:43.727542 ==
1145 23:06:43.730546 Dram Type= 6, Freq= 0, CH_0, rank 1
1146 23:06:43.733967 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1147 23:06:43.734095 ==
1148 23:06:43.737258 Write leveling (Byte 0): 34 => 34
1149 23:06:43.740748 Write leveling (Byte 1): 27 => 27
1150 23:06:43.744256 DramcWriteLeveling(PI) end<-----
1151 23:06:43.744393
1152 23:06:43.744513 ==
1153 23:06:43.747764 Dram Type= 6, Freq= 0, CH_0, rank 1
1154 23:06:43.750952 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1155 23:06:43.751087 ==
1156 23:06:43.754771 [Gating] SW mode calibration
1157 23:06:43.760655 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1158 23:06:43.767246 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1159 23:06:43.770838 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1160 23:06:43.774236 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1161 23:06:43.818053 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1162 23:06:43.818501 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 23:06:43.819263 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 23:06:43.819515 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 23:06:43.819584 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 23:06:43.819889 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 23:06:43.820706 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 23:06:43.821032 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 23:06:43.822148 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 23:06:43.822237 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 23:06:43.845475 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 23:06:43.845933 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 23:06:43.846638 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 23:06:43.847025 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 23:06:43.847138 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1176 23:06:43.847398 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
1177 23:06:43.850248 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1178 23:06:43.853394 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 23:06:43.859786 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 23:06:43.863551 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 23:06:43.866804 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 23:06:43.873122 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1183 23:06:43.876564 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 23:06:43.879948 0 9 4 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
1185 23:06:43.886471 0 9 8 | B1->B0 | 2525 3333 | 1 1 | (1 1) (1 1)
1186 23:06:43.889771 0 9 12 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
1187 23:06:43.893493 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1188 23:06:43.899927 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1189 23:06:43.903026 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1190 23:06:43.906559 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1191 23:06:43.913290 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1192 23:06:43.916601 0 10 4 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
1193 23:06:43.919759 0 10 8 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
1194 23:06:43.923293 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1195 23:06:43.929430 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1196 23:06:43.933144 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1197 23:06:43.936447 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1198 23:06:43.943018 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1199 23:06:43.946953 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1200 23:06:43.949513 0 11 4 | B1->B0 | 2323 3232 | 0 1 | (0 0) (1 1)
1201 23:06:43.956785 0 11 8 | B1->B0 | 3131 4646 | 0 0 | (1 1) (0 0)
1202 23:06:43.960514 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1203 23:06:43.964092 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1204 23:06:43.967479 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1205 23:06:43.974291 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1206 23:06:43.977843 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1207 23:06:43.980823 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1208 23:06:43.984637 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1209 23:06:43.991356 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 23:06:43.994657 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 23:06:43.998268 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 23:06:44.004866 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 23:06:44.008319 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 23:06:44.011721 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 23:06:44.018023 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 23:06:44.021376 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 23:06:44.024295 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 23:06:44.031763 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1219 23:06:44.035001 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1220 23:06:44.037605 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1221 23:06:44.044556 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1222 23:06:44.048033 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1223 23:06:44.051867 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1224 23:06:44.057773 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1225 23:06:44.060892 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1226 23:06:44.065043 Total UI for P1: 0, mck2ui 16
1227 23:06:44.067659 best dqsien dly found for B0: ( 0, 14, 4)
1228 23:06:44.071208 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1229 23:06:44.074123 Total UI for P1: 0, mck2ui 16
1230 23:06:44.077521 best dqsien dly found for B1: ( 0, 14, 8)
1231 23:06:44.080834 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1232 23:06:44.084121 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1233 23:06:44.084225
1234 23:06:44.087839 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1235 23:06:44.094063 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1236 23:06:44.094195 [Gating] SW calibration Done
1237 23:06:44.094314 ==
1238 23:06:44.097406 Dram Type= 6, Freq= 0, CH_0, rank 1
1239 23:06:44.104194 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1240 23:06:44.104333 ==
1241 23:06:44.104450 RX Vref Scan: 0
1242 23:06:44.104563
1243 23:06:44.107655 RX Vref 0 -> 0, step: 1
1244 23:06:44.107814
1245 23:06:44.110499 RX Delay -130 -> 252, step: 16
1246 23:06:44.114622 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1247 23:06:44.117465 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1248 23:06:44.120875 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1249 23:06:44.128172 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1250 23:06:44.130653 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1251 23:06:44.133974 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
1252 23:06:44.137513 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1253 23:06:44.140457 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1254 23:06:44.147283 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1255 23:06:44.150585 iDelay=206, Bit 9, Center 53 (-66 ~ 173) 240
1256 23:06:44.153952 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1257 23:06:44.157647 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1258 23:06:44.160362 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1259 23:06:44.167270 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1260 23:06:44.170372 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1261 23:06:44.173741 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1262 23:06:44.173824 ==
1263 23:06:44.177234 Dram Type= 6, Freq= 0, CH_0, rank 1
1264 23:06:44.180514 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1265 23:06:44.183728 ==
1266 23:06:44.183815 DQS Delay:
1267 23:06:44.183881 DQS0 = 0, DQS1 = 0
1268 23:06:44.187010 DQM Delay:
1269 23:06:44.187095 DQM0 = 86, DQM1 = 77
1270 23:06:44.190339 DQ Delay:
1271 23:06:44.190426 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =85
1272 23:06:44.193489 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93
1273 23:06:44.196704 DQ8 =69, DQ9 =53, DQ10 =85, DQ11 =69
1274 23:06:44.200449 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1275 23:06:44.203206
1276 23:06:44.203277
1277 23:06:44.203343 ==
1278 23:06:44.206801 Dram Type= 6, Freq= 0, CH_0, rank 1
1279 23:06:44.209935 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1280 23:06:44.210074 ==
1281 23:06:44.210190
1282 23:06:44.210300
1283 23:06:44.213376 TX Vref Scan disable
1284 23:06:44.213504 == TX Byte 0 ==
1285 23:06:44.220115 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
1286 23:06:44.223211 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
1287 23:06:44.223345 == TX Byte 1 ==
1288 23:06:44.229927 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1289 23:06:44.233031 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1290 23:06:44.233160 ==
1291 23:06:44.236320 Dram Type= 6, Freq= 0, CH_0, rank 1
1292 23:06:44.239947 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1293 23:06:44.240037 ==
1294 23:06:44.254192 TX Vref=22, minBit 2, minWin=27, winSum=444
1295 23:06:44.257745 TX Vref=24, minBit 9, minWin=27, winSum=449
1296 23:06:44.261309 TX Vref=26, minBit 1, minWin=27, winSum=448
1297 23:06:44.264396 TX Vref=28, minBit 5, minWin=27, winSum=453
1298 23:06:44.267957 TX Vref=30, minBit 5, minWin=27, winSum=452
1299 23:06:44.274337 TX Vref=32, minBit 5, minWin=27, winSum=450
1300 23:06:44.277853 [TxChooseVref] Worse bit 5, Min win 27, Win sum 453, Final Vref 28
1301 23:06:44.278015
1302 23:06:44.280905 Final TX Range 1 Vref 28
1303 23:06:44.281007
1304 23:06:44.281079 ==
1305 23:06:44.284512 Dram Type= 6, Freq= 0, CH_0, rank 1
1306 23:06:44.287686 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1307 23:06:44.287842 ==
1308 23:06:44.291189
1309 23:06:44.291306
1310 23:06:44.291432 TX Vref Scan disable
1311 23:06:44.295131 == TX Byte 0 ==
1312 23:06:44.298160 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
1313 23:06:44.304218 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
1314 23:06:44.304361 == TX Byte 1 ==
1315 23:06:44.308109 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1316 23:06:44.314906 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1317 23:06:44.315025
1318 23:06:44.315120 [DATLAT]
1319 23:06:44.315221 Freq=800, CH0 RK1
1320 23:06:44.315311
1321 23:06:44.318238 DATLAT Default: 0xa
1322 23:06:44.318374 0, 0xFFFF, sum = 0
1323 23:06:44.320949 1, 0xFFFF, sum = 0
1324 23:06:44.324428 2, 0xFFFF, sum = 0
1325 23:06:44.324548 3, 0xFFFF, sum = 0
1326 23:06:44.327959 4, 0xFFFF, sum = 0
1327 23:06:44.328081 5, 0xFFFF, sum = 0
1328 23:06:44.330795 6, 0xFFFF, sum = 0
1329 23:06:44.330912 7, 0xFFFF, sum = 0
1330 23:06:44.334108 8, 0xFFFF, sum = 0
1331 23:06:44.334250 9, 0x0, sum = 1
1332 23:06:44.337480 10, 0x0, sum = 2
1333 23:06:44.337613 11, 0x0, sum = 3
1334 23:06:44.340797 12, 0x0, sum = 4
1335 23:06:44.340928 best_step = 10
1336 23:06:44.341047
1337 23:06:44.341159 ==
1338 23:06:44.344332 Dram Type= 6, Freq= 0, CH_0, rank 1
1339 23:06:44.347489 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1340 23:06:44.347601 ==
1341 23:06:44.350694 RX Vref Scan: 0
1342 23:06:44.350804
1343 23:06:44.354314 RX Vref 0 -> 0, step: 1
1344 23:06:44.354423
1345 23:06:44.354513 RX Delay -111 -> 252, step: 8
1346 23:06:44.361671 iDelay=209, Bit 0, Center 84 (-23 ~ 192) 216
1347 23:06:44.364527 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1348 23:06:44.367911 iDelay=209, Bit 2, Center 80 (-31 ~ 192) 224
1349 23:06:44.371523 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
1350 23:06:44.374276 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1351 23:06:44.381024 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1352 23:06:44.384734 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1353 23:06:44.388096 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1354 23:06:44.391477 iDelay=209, Bit 8, Center 64 (-47 ~ 176) 224
1355 23:06:44.394249 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
1356 23:06:44.401398 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1357 23:06:44.404324 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
1358 23:06:44.407851 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1359 23:06:44.411468 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1360 23:06:44.417709 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1361 23:06:44.420950 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1362 23:06:44.421067 ==
1363 23:06:44.424191 Dram Type= 6, Freq= 0, CH_0, rank 1
1364 23:06:44.427946 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1365 23:06:44.428061 ==
1366 23:06:44.428158 DQS Delay:
1367 23:06:44.430848 DQS0 = 0, DQS1 = 0
1368 23:06:44.430954 DQM Delay:
1369 23:06:44.434123 DQM0 = 86, DQM1 = 76
1370 23:06:44.434236 DQ Delay:
1371 23:06:44.437568 DQ0 =84, DQ1 =88, DQ2 =80, DQ3 =80
1372 23:06:44.441132 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1373 23:06:44.444670 DQ8 =64, DQ9 =64, DQ10 =80, DQ11 =68
1374 23:06:44.447793 DQ12 =84, DQ13 =80, DQ14 =88, DQ15 =84
1375 23:06:44.447908
1376 23:06:44.448007
1377 23:06:44.457562 [DQSOSCAuto] RK1, (LSB)MR18= 0x2e2a, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 398 ps
1378 23:06:44.457709 CH0 RK1: MR19=606, MR18=2E2A
1379 23:06:44.464471 CH0_RK1: MR19=0x606, MR18=0x2E2A, DQSOSC=398, MR23=63, INC=93, DEC=62
1380 23:06:44.468339 [RxdqsGatingPostProcess] freq 800
1381 23:06:44.474376 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1382 23:06:44.477480 Pre-setting of DQS Precalculation
1383 23:06:44.480562 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1384 23:06:44.480681 ==
1385 23:06:44.484204 Dram Type= 6, Freq= 0, CH_1, rank 0
1386 23:06:44.490827 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1387 23:06:44.490944 ==
1388 23:06:44.493963 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1389 23:06:44.500565 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1390 23:06:44.509536 [CA 0] Center 37 (6~68) winsize 63
1391 23:06:44.512771 [CA 1] Center 37 (6~68) winsize 63
1392 23:06:44.516234 [CA 2] Center 34 (4~65) winsize 62
1393 23:06:44.519642 [CA 3] Center 34 (4~65) winsize 62
1394 23:06:44.523271 [CA 4] Center 34 (4~65) winsize 62
1395 23:06:44.525956 [CA 5] Center 33 (3~64) winsize 62
1396 23:06:44.526088
1397 23:06:44.529617 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1398 23:06:44.529717
1399 23:06:44.533199 [CATrainingPosCal] consider 1 rank data
1400 23:06:44.536375 u2DelayCellTimex100 = 270/100 ps
1401 23:06:44.539808 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
1402 23:06:44.543083 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1403 23:06:44.549673 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1404 23:06:44.553000 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1405 23:06:44.556119 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1406 23:06:44.559346 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1407 23:06:44.559472
1408 23:06:44.563109 CA PerBit enable=1, Macro0, CA PI delay=33
1409 23:06:44.563230
1410 23:06:44.566891 [CBTSetCACLKResult] CA Dly = 33
1411 23:06:44.567011 CS Dly: 4 (0~35)
1412 23:06:44.567107 ==
1413 23:06:44.569386 Dram Type= 6, Freq= 0, CH_1, rank 1
1414 23:06:44.575945 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1415 23:06:44.576079 ==
1416 23:06:44.579267 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1417 23:06:44.586018 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1418 23:06:44.596137 [CA 0] Center 37 (6~68) winsize 63
1419 23:06:44.599034 [CA 1] Center 36 (6~67) winsize 62
1420 23:06:44.602264 [CA 2] Center 34 (4~65) winsize 62
1421 23:06:44.605722 [CA 3] Center 33 (3~64) winsize 62
1422 23:06:44.608837 [CA 4] Center 34 (3~65) winsize 63
1423 23:06:44.612883 [CA 5] Center 33 (3~64) winsize 62
1424 23:06:44.613009
1425 23:06:44.616147 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1426 23:06:44.616263
1427 23:06:44.619036 [CATrainingPosCal] consider 2 rank data
1428 23:06:44.622857 u2DelayCellTimex100 = 270/100 ps
1429 23:06:44.626414 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
1430 23:06:44.630541 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1431 23:06:44.633473 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1432 23:06:44.637471 CA3 delay=34 (4~64),Diff = 1 PI (7 cell)
1433 23:06:44.641133 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1434 23:06:44.645031 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1435 23:06:44.645201
1436 23:06:44.648632 CA PerBit enable=1, Macro0, CA PI delay=33
1437 23:06:44.648758
1438 23:06:44.652158 [CBTSetCACLKResult] CA Dly = 33
1439 23:06:44.652275 CS Dly: 5 (0~37)
1440 23:06:44.652371
1441 23:06:44.655826 ----->DramcWriteLeveling(PI) begin...
1442 23:06:44.659178 ==
1443 23:06:44.659294 Dram Type= 6, Freq= 0, CH_1, rank 0
1444 23:06:44.666515 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1445 23:06:44.666698 ==
1446 23:06:44.669397 Write leveling (Byte 0): 28 => 28
1447 23:06:44.672901 Write leveling (Byte 1): 29 => 29
1448 23:06:44.672991 DramcWriteLeveling(PI) end<-----
1449 23:06:44.675939
1450 23:06:44.676029 ==
1451 23:06:44.679528 Dram Type= 6, Freq= 0, CH_1, rank 0
1452 23:06:44.682774 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1453 23:06:44.682866 ==
1454 23:06:44.685826 [Gating] SW mode calibration
1455 23:06:44.692470 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1456 23:06:44.695643 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1457 23:06:44.702797 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1458 23:06:44.706271 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 23:06:44.709648 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1460 23:06:44.716066 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 23:06:44.719216 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 23:06:44.722676 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 23:06:44.729489 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 23:06:44.732366 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 23:06:44.735666 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 23:06:44.742585 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 23:06:44.745696 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 23:06:44.749645 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 23:06:44.755649 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 23:06:44.759178 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 23:06:44.762513 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 23:06:44.768633 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 23:06:44.772225 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1474 23:06:44.775496 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1475 23:06:44.782150 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 23:06:44.785454 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 23:06:44.788847 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 23:06:44.795206 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 23:06:44.799004 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1480 23:06:44.801993 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1481 23:06:44.805519 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1482 23:06:44.812388 0 9 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1483 23:06:44.815091 0 9 8 | B1->B0 | 2c2c 3232 | 0 1 | (0 0) (1 1)
1484 23:06:44.819084 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1485 23:06:44.825419 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1486 23:06:44.828578 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1487 23:06:44.831776 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1488 23:06:44.838403 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1489 23:06:44.841831 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1490 23:06:44.845089 0 10 4 | B1->B0 | 3131 3131 | 0 0 | (0 1) (1 1)
1491 23:06:44.851555 0 10 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1492 23:06:44.855817 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 23:06:44.858789 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1494 23:06:44.864748 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1495 23:06:44.868306 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1496 23:06:44.871710 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1497 23:06:44.878303 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1498 23:06:44.881638 0 11 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
1499 23:06:44.884742 0 11 8 | B1->B0 | 4040 4444 | 0 1 | (0 0) (0 0)
1500 23:06:44.891807 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1501 23:06:44.894630 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1502 23:06:44.898721 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1503 23:06:44.904927 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1504 23:06:44.908258 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1505 23:06:44.911934 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1506 23:06:44.917886 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1507 23:06:44.921220 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 23:06:44.924733 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 23:06:44.931542 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 23:06:44.935412 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 23:06:44.938451 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 23:06:44.944621 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 23:06:44.948061 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 23:06:44.951860 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 23:06:44.954607 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 23:06:44.961706 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1517 23:06:44.964655 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1518 23:06:44.968106 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1519 23:06:44.974560 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1520 23:06:44.977994 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1521 23:06:44.984524 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1522 23:06:44.988147 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1523 23:06:44.990847 Total UI for P1: 0, mck2ui 16
1524 23:06:44.994668 best dqsien dly found for B0: ( 0, 14, 0)
1525 23:06:44.997427 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1526 23:06:45.001076 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1527 23:06:45.004746 Total UI for P1: 0, mck2ui 16
1528 23:06:45.007793 best dqsien dly found for B1: ( 0, 14, 6)
1529 23:06:45.010979 best DQS0 dly(MCK, UI, PI) = (0, 14, 0)
1530 23:06:45.017683 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1531 23:06:45.017784
1532 23:06:45.021005 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 0)
1533 23:06:45.024234 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1534 23:06:45.027885 [Gating] SW calibration Done
1535 23:06:45.028000 ==
1536 23:06:45.030768 Dram Type= 6, Freq= 0, CH_1, rank 0
1537 23:06:45.034332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1538 23:06:45.034446 ==
1539 23:06:45.034547 RX Vref Scan: 0
1540 23:06:45.037205
1541 23:06:45.037317 RX Vref 0 -> 0, step: 1
1542 23:06:45.037417
1543 23:06:45.040395 RX Delay -130 -> 252, step: 16
1544 23:06:45.044090 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1545 23:06:45.051077 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1546 23:06:45.053801 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1547 23:06:45.057062 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1548 23:06:45.060151 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1549 23:06:45.063801 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1550 23:06:45.070600 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1551 23:06:45.073541 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1552 23:06:45.077015 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1553 23:06:45.080446 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1554 23:06:45.084005 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1555 23:06:45.090239 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1556 23:06:45.093759 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1557 23:06:45.097197 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1558 23:06:45.100189 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1559 23:06:45.103719 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1560 23:06:45.107002 ==
1561 23:06:45.107140 Dram Type= 6, Freq= 0, CH_1, rank 0
1562 23:06:45.113896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1563 23:06:45.114037 ==
1564 23:06:45.114150 DQS Delay:
1565 23:06:45.116619 DQS0 = 0, DQS1 = 0
1566 23:06:45.116736 DQM Delay:
1567 23:06:45.120167 DQM0 = 88, DQM1 = 86
1568 23:06:45.120289 DQ Delay:
1569 23:06:45.123413 DQ0 =93, DQ1 =85, DQ2 =69, DQ3 =85
1570 23:06:45.127121 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1571 23:06:45.130302 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =77
1572 23:06:45.133434 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1573 23:06:45.133635
1574 23:06:45.133768
1575 23:06:45.133893 ==
1576 23:06:45.137047 Dram Type= 6, Freq= 0, CH_1, rank 0
1577 23:06:45.140107 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1578 23:06:45.140248 ==
1579 23:06:45.140368
1580 23:06:45.140489
1581 23:06:45.143622 TX Vref Scan disable
1582 23:06:45.146962 == TX Byte 0 ==
1583 23:06:45.150342 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1584 23:06:45.153360 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1585 23:06:45.156576 == TX Byte 1 ==
1586 23:06:45.160431 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1587 23:06:45.163412 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1588 23:06:45.163574 ==
1589 23:06:45.166734 Dram Type= 6, Freq= 0, CH_1, rank 0
1590 23:06:45.173856 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1591 23:06:45.174065 ==
1592 23:06:45.184689 TX Vref=22, minBit 0, minWin=27, winSum=442
1593 23:06:45.188479 TX Vref=24, minBit 4, minWin=27, winSum=449
1594 23:06:45.191245 TX Vref=26, minBit 1, minWin=27, winSum=454
1595 23:06:45.195100 TX Vref=28, minBit 1, minWin=27, winSum=452
1596 23:06:45.198255 TX Vref=30, minBit 1, minWin=27, winSum=453
1597 23:06:45.201413 TX Vref=32, minBit 1, minWin=27, winSum=453
1598 23:06:45.208599 [TxChooseVref] Worse bit 1, Min win 27, Win sum 454, Final Vref 26
1599 23:06:45.208748
1600 23:06:45.212489 Final TX Range 1 Vref 26
1601 23:06:45.212596
1602 23:06:45.212686 ==
1603 23:06:45.215459 Dram Type= 6, Freq= 0, CH_1, rank 0
1604 23:06:45.218601 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1605 23:06:45.218723 ==
1606 23:06:45.218823
1607 23:06:45.218920
1608 23:06:45.221832 TX Vref Scan disable
1609 23:06:45.225048 == TX Byte 0 ==
1610 23:06:45.228458 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1611 23:06:45.232447 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1612 23:06:45.235525 == TX Byte 1 ==
1613 23:06:45.238735 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1614 23:06:45.241695 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1615 23:06:45.241807
1616 23:06:45.244993 [DATLAT]
1617 23:06:45.245083 Freq=800, CH1 RK0
1618 23:06:45.245170
1619 23:06:45.248736 DATLAT Default: 0xa
1620 23:06:45.248822 0, 0xFFFF, sum = 0
1621 23:06:45.252001 1, 0xFFFF, sum = 0
1622 23:06:45.252088 2, 0xFFFF, sum = 0
1623 23:06:45.255479 3, 0xFFFF, sum = 0
1624 23:06:45.255566 4, 0xFFFF, sum = 0
1625 23:06:45.258291 5, 0xFFFF, sum = 0
1626 23:06:45.258377 6, 0xFFFF, sum = 0
1627 23:06:45.262174 7, 0xFFFF, sum = 0
1628 23:06:45.262260 8, 0xFFFF, sum = 0
1629 23:06:45.264959 9, 0x0, sum = 1
1630 23:06:45.265045 10, 0x0, sum = 2
1631 23:06:45.268278 11, 0x0, sum = 3
1632 23:06:45.268363 12, 0x0, sum = 4
1633 23:06:45.271724 best_step = 10
1634 23:06:45.271846
1635 23:06:45.271931 ==
1636 23:06:45.275138 Dram Type= 6, Freq= 0, CH_1, rank 0
1637 23:06:45.278450 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1638 23:06:45.278534 ==
1639 23:06:45.281957 RX Vref Scan: 1
1640 23:06:45.282041
1641 23:06:45.282126 Set Vref Range= 32 -> 127
1642 23:06:45.282207
1643 23:06:45.285103 RX Vref 32 -> 127, step: 1
1644 23:06:45.285187
1645 23:06:45.288589 RX Delay -95 -> 252, step: 8
1646 23:06:45.288674
1647 23:06:45.291743 Set Vref, RX VrefLevel [Byte0]: 32
1648 23:06:45.295443 [Byte1]: 32
1649 23:06:45.295529
1650 23:06:45.298118 Set Vref, RX VrefLevel [Byte0]: 33
1651 23:06:45.301910 [Byte1]: 33
1652 23:06:45.304835
1653 23:06:45.304922 Set Vref, RX VrefLevel [Byte0]: 34
1654 23:06:45.308398 [Byte1]: 34
1655 23:06:45.312447
1656 23:06:45.312533 Set Vref, RX VrefLevel [Byte0]: 35
1657 23:06:45.315873 [Byte1]: 35
1658 23:06:45.319890
1659 23:06:45.319976 Set Vref, RX VrefLevel [Byte0]: 36
1660 23:06:45.323304 [Byte1]: 36
1661 23:06:45.327817
1662 23:06:45.327903 Set Vref, RX VrefLevel [Byte0]: 37
1663 23:06:45.330741 [Byte1]: 37
1664 23:06:45.335013
1665 23:06:45.335105 Set Vref, RX VrefLevel [Byte0]: 38
1666 23:06:45.338267 [Byte1]: 38
1667 23:06:45.343054
1668 23:06:45.343145 Set Vref, RX VrefLevel [Byte0]: 39
1669 23:06:45.346063 [Byte1]: 39
1670 23:06:45.350198
1671 23:06:45.350287 Set Vref, RX VrefLevel [Byte0]: 40
1672 23:06:45.354083 [Byte1]: 40
1673 23:06:45.357989
1674 23:06:45.358077 Set Vref, RX VrefLevel [Byte0]: 41
1675 23:06:45.361051 [Byte1]: 41
1676 23:06:45.365886
1677 23:06:45.365975 Set Vref, RX VrefLevel [Byte0]: 42
1678 23:06:45.368781 [Byte1]: 42
1679 23:06:45.373265
1680 23:06:45.373361 Set Vref, RX VrefLevel [Byte0]: 43
1681 23:06:45.376308 [Byte1]: 43
1682 23:06:45.381244
1683 23:06:45.381340 Set Vref, RX VrefLevel [Byte0]: 44
1684 23:06:45.384309 [Byte1]: 44
1685 23:06:45.388628
1686 23:06:45.388729 Set Vref, RX VrefLevel [Byte0]: 45
1687 23:06:45.391805 [Byte1]: 45
1688 23:06:45.396628
1689 23:06:45.396733 Set Vref, RX VrefLevel [Byte0]: 46
1690 23:06:45.399322 [Byte1]: 46
1691 23:06:45.403884
1692 23:06:45.403996 Set Vref, RX VrefLevel [Byte0]: 47
1693 23:06:45.407041 [Byte1]: 47
1694 23:06:45.411314
1695 23:06:45.411431 Set Vref, RX VrefLevel [Byte0]: 48
1696 23:06:45.414213 [Byte1]: 48
1697 23:06:45.418890
1698 23:06:45.418989 Set Vref, RX VrefLevel [Byte0]: 49
1699 23:06:45.422248 [Byte1]: 49
1700 23:06:45.426471
1701 23:06:45.426571 Set Vref, RX VrefLevel [Byte0]: 50
1702 23:06:45.429648 [Byte1]: 50
1703 23:06:45.433782
1704 23:06:45.433884 Set Vref, RX VrefLevel [Byte0]: 51
1705 23:06:45.437125 [Byte1]: 51
1706 23:06:45.441506
1707 23:06:45.441620 Set Vref, RX VrefLevel [Byte0]: 52
1708 23:06:45.444669 [Byte1]: 52
1709 23:06:45.449130
1710 23:06:45.449250 Set Vref, RX VrefLevel [Byte0]: 53
1711 23:06:45.452466 [Byte1]: 53
1712 23:06:45.456723
1713 23:06:45.456819 Set Vref, RX VrefLevel [Byte0]: 54
1714 23:06:45.460603 [Byte1]: 54
1715 23:06:45.464443
1716 23:06:45.464537 Set Vref, RX VrefLevel [Byte0]: 55
1717 23:06:45.468207 [Byte1]: 55
1718 23:06:45.471843
1719 23:06:45.471937 Set Vref, RX VrefLevel [Byte0]: 56
1720 23:06:45.475311 [Byte1]: 56
1721 23:06:45.479823
1722 23:06:45.479915 Set Vref, RX VrefLevel [Byte0]: 57
1723 23:06:45.483014 [Byte1]: 57
1724 23:06:45.487162
1725 23:06:45.487265 Set Vref, RX VrefLevel [Byte0]: 58
1726 23:06:45.490425 [Byte1]: 58
1727 23:06:45.494747
1728 23:06:45.494831 Set Vref, RX VrefLevel [Byte0]: 59
1729 23:06:45.498480 [Byte1]: 59
1730 23:06:45.502685
1731 23:06:45.502770 Set Vref, RX VrefLevel [Byte0]: 60
1732 23:06:45.505481 [Byte1]: 60
1733 23:06:45.509970
1734 23:06:45.510054 Set Vref, RX VrefLevel [Byte0]: 61
1735 23:06:45.513482 [Byte1]: 61
1736 23:06:45.517399
1737 23:06:45.517482 Set Vref, RX VrefLevel [Byte0]: 62
1738 23:06:45.521107 [Byte1]: 62
1739 23:06:45.525041
1740 23:06:45.525139 Set Vref, RX VrefLevel [Byte0]: 63
1741 23:06:45.528234 [Byte1]: 63
1742 23:06:45.532743
1743 23:06:45.532826 Set Vref, RX VrefLevel [Byte0]: 64
1744 23:06:45.536207 [Byte1]: 64
1745 23:06:45.540582
1746 23:06:45.540665 Set Vref, RX VrefLevel [Byte0]: 65
1747 23:06:45.543645 [Byte1]: 65
1748 23:06:45.548307
1749 23:06:45.548391 Set Vref, RX VrefLevel [Byte0]: 66
1750 23:06:45.551257 [Byte1]: 66
1751 23:06:45.555734
1752 23:06:45.555816 Set Vref, RX VrefLevel [Byte0]: 67
1753 23:06:45.559110 [Byte1]: 67
1754 23:06:45.563085
1755 23:06:45.563166 Set Vref, RX VrefLevel [Byte0]: 68
1756 23:06:45.566303 [Byte1]: 68
1757 23:06:45.570683
1758 23:06:45.570764 Set Vref, RX VrefLevel [Byte0]: 69
1759 23:06:45.573947 [Byte1]: 69
1760 23:06:45.578731
1761 23:06:45.578815 Set Vref, RX VrefLevel [Byte0]: 70
1762 23:06:45.581576 [Byte1]: 70
1763 23:06:45.585852
1764 23:06:45.585956 Set Vref, RX VrefLevel [Byte0]: 71
1765 23:06:45.589483 [Byte1]: 71
1766 23:06:45.593397
1767 23:06:45.593479 Set Vref, RX VrefLevel [Byte0]: 72
1768 23:06:45.596733 [Byte1]: 72
1769 23:06:45.601053
1770 23:06:45.601135 Set Vref, RX VrefLevel [Byte0]: 73
1771 23:06:45.604357 [Byte1]: 73
1772 23:06:45.608971
1773 23:06:45.609052 Set Vref, RX VrefLevel [Byte0]: 74
1774 23:06:45.612327 [Byte1]: 74
1775 23:06:45.616478
1776 23:06:45.616560 Final RX Vref Byte 0 = 52 to rank0
1777 23:06:45.620140 Final RX Vref Byte 1 = 52 to rank0
1778 23:06:45.622781 Final RX Vref Byte 0 = 52 to rank1
1779 23:06:45.626064 Final RX Vref Byte 1 = 52 to rank1==
1780 23:06:45.629457 Dram Type= 6, Freq= 0, CH_1, rank 0
1781 23:06:45.636675 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1782 23:06:45.636759 ==
1783 23:06:45.636824 DQS Delay:
1784 23:06:45.636885 DQS0 = 0, DQS1 = 0
1785 23:06:45.639926 DQM Delay:
1786 23:06:45.640007 DQM0 = 84, DQM1 = 80
1787 23:06:45.642924 DQ Delay:
1788 23:06:45.646511 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
1789 23:06:45.649366 DQ4 =80, DQ5 =92, DQ6 =96, DQ7 =76
1790 23:06:45.652676 DQ8 =64, DQ9 =68, DQ10 =80, DQ11 =76
1791 23:06:45.656020 DQ12 =88, DQ13 =88, DQ14 =88, DQ15 =88
1792 23:06:45.656105
1793 23:06:45.656169
1794 23:06:45.662797 [DQSOSCAuto] RK0, (LSB)MR18= 0x172a, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 404 ps
1795 23:06:45.666050 CH1 RK0: MR19=606, MR18=172A
1796 23:06:45.673045 CH1_RK0: MR19=0x606, MR18=0x172A, DQSOSC=399, MR23=63, INC=92, DEC=61
1797 23:06:45.673152
1798 23:06:45.675939 ----->DramcWriteLeveling(PI) begin...
1799 23:06:45.676026 ==
1800 23:06:45.679588 Dram Type= 6, Freq= 0, CH_1, rank 1
1801 23:06:45.682886 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1802 23:06:45.682974 ==
1803 23:06:45.686165 Write leveling (Byte 0): 25 => 25
1804 23:06:45.689121 Write leveling (Byte 1): 28 => 28
1805 23:06:45.692986 DramcWriteLeveling(PI) end<-----
1806 23:06:45.693075
1807 23:06:45.693161 ==
1808 23:06:45.695808 Dram Type= 6, Freq= 0, CH_1, rank 1
1809 23:06:45.699044 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1810 23:06:45.699160 ==
1811 23:06:45.702420 [Gating] SW mode calibration
1812 23:06:45.709368 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1813 23:06:45.715647 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1814 23:06:45.719121 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1815 23:06:45.722406 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1816 23:06:45.728870 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 23:06:45.732090 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 23:06:45.735701 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 23:06:45.742126 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 23:06:45.746075 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 23:06:45.748840 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 23:06:45.755636 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 23:06:45.759332 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 23:06:45.762244 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 23:06:45.768897 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 23:06:45.772205 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 23:06:45.775284 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 23:06:45.782097 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 23:06:45.785233 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 23:06:45.789135 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1831 23:06:45.795648 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1832 23:06:45.798785 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 23:06:45.802199 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 23:06:45.808810 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 23:06:45.812195 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 23:06:45.815252 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 23:06:45.822316 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 23:06:45.825829 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 23:06:45.828652 0 9 4 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (1 1)
1840 23:06:45.835027 0 9 8 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
1841 23:06:45.838961 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1842 23:06:45.841964 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1843 23:06:45.848358 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1844 23:06:45.852024 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1845 23:06:45.855047 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1846 23:06:45.862046 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1847 23:06:45.865335 0 10 4 | B1->B0 | 3030 2f2f | 0 0 | (0 1) (1 1)
1848 23:06:45.868770 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1849 23:06:45.875222 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1850 23:06:45.878107 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1851 23:06:45.881726 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1852 23:06:45.885095 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1853 23:06:45.891749 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1854 23:06:45.895095 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1855 23:06:45.898106 0 11 4 | B1->B0 | 2727 3333 | 0 0 | (0 0) (1 1)
1856 23:06:45.905002 0 11 8 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
1857 23:06:45.908456 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1858 23:06:45.911534 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1859 23:06:45.918243 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1860 23:06:45.921773 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1861 23:06:45.924859 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1862 23:06:45.931629 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1863 23:06:45.934805 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 23:06:45.937813 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1865 23:06:45.944812 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 23:06:45.948766 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 23:06:45.951600 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 23:06:45.958300 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 23:06:45.961096 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 23:06:45.964471 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 23:06:45.971550 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 23:06:45.974448 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 23:06:45.977930 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 23:06:45.984336 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 23:06:45.987570 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 23:06:45.991227 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 23:06:45.998350 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1878 23:06:46.001051 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1879 23:06:46.004761 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
1880 23:06:46.007717 Total UI for P1: 0, mck2ui 16
1881 23:06:46.010880 best dqsien dly found for B0: ( 0, 14, 2)
1882 23:06:46.017337 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1883 23:06:46.017437 Total UI for P1: 0, mck2ui 16
1884 23:06:46.023838 best dqsien dly found for B1: ( 0, 14, 6)
1885 23:06:46.027675 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1886 23:06:46.030695 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1887 23:06:46.030781
1888 23:06:46.033865 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1889 23:06:46.037304 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1890 23:06:46.040668 [Gating] SW calibration Done
1891 23:06:46.040753 ==
1892 23:06:46.044266 Dram Type= 6, Freq= 0, CH_1, rank 1
1893 23:06:46.047355 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1894 23:06:46.047482 ==
1895 23:06:46.050825 RX Vref Scan: 0
1896 23:06:46.050908
1897 23:06:46.050972 RX Vref 0 -> 0, step: 1
1898 23:06:46.051032
1899 23:06:46.053838 RX Delay -130 -> 252, step: 16
1900 23:06:46.057817 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1901 23:06:46.064150 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1902 23:06:46.066946 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1903 23:06:46.070519 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1904 23:06:46.073992 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1905 23:06:46.077124 iDelay=206, Bit 5, Center 85 (-34 ~ 205) 240
1906 23:06:46.084006 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1907 23:06:46.087518 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
1908 23:06:46.090481 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1909 23:06:46.094133 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1910 23:06:46.097510 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1911 23:06:46.104854 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1912 23:06:46.107214 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1913 23:06:46.110887 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1914 23:06:46.114105 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1915 23:06:46.117750 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1916 23:06:46.120880 ==
1917 23:06:46.120968 Dram Type= 6, Freq= 0, CH_1, rank 1
1918 23:06:46.127238 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1919 23:06:46.127328 ==
1920 23:06:46.127433 DQS Delay:
1921 23:06:46.130616 DQS0 = 0, DQS1 = 0
1922 23:06:46.130696 DQM Delay:
1923 23:06:46.133980 DQM0 = 83, DQM1 = 80
1924 23:06:46.134064 DQ Delay:
1925 23:06:46.137635 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85
1926 23:06:46.140748 DQ4 =85, DQ5 =85, DQ6 =85, DQ7 =85
1927 23:06:46.143876 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1928 23:06:46.147351 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1929 23:06:46.147494
1930 23:06:46.147687
1931 23:06:46.147817 ==
1932 23:06:46.150823 Dram Type= 6, Freq= 0, CH_1, rank 1
1933 23:06:46.154325 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1934 23:06:46.154409 ==
1935 23:06:46.154474
1936 23:06:46.154533
1937 23:06:46.157383 TX Vref Scan disable
1938 23:06:46.160714 == TX Byte 0 ==
1939 23:06:46.163689 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1940 23:06:46.167566 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1941 23:06:46.170659 == TX Byte 1 ==
1942 23:06:46.173727 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1943 23:06:46.177494 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1944 23:06:46.177579 ==
1945 23:06:46.180446 Dram Type= 6, Freq= 0, CH_1, rank 1
1946 23:06:46.183772 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1947 23:06:46.186883 ==
1948 23:06:46.198476 TX Vref=22, minBit 1, minWin=27, winSum=445
1949 23:06:46.201720 TX Vref=24, minBit 2, minWin=27, winSum=451
1950 23:06:46.204764 TX Vref=26, minBit 1, minWin=27, winSum=451
1951 23:06:46.208358 TX Vref=28, minBit 0, minWin=28, winSum=454
1952 23:06:46.211346 TX Vref=30, minBit 0, minWin=28, winSum=458
1953 23:06:46.218287 TX Vref=32, minBit 0, minWin=28, winSum=454
1954 23:06:46.221287 [TxChooseVref] Worse bit 0, Min win 28, Win sum 458, Final Vref 30
1955 23:06:46.221374
1956 23:06:46.224703 Final TX Range 1 Vref 30
1957 23:06:46.224826
1958 23:06:46.224891 ==
1959 23:06:46.228013 Dram Type= 6, Freq= 0, CH_1, rank 1
1960 23:06:46.231559 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1961 23:06:46.234580 ==
1962 23:06:46.234665
1963 23:06:46.234729
1964 23:06:46.234788 TX Vref Scan disable
1965 23:06:46.238783 == TX Byte 0 ==
1966 23:06:46.241442 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1967 23:06:46.248243 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1968 23:06:46.248333 == TX Byte 1 ==
1969 23:06:46.251256 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1970 23:06:46.258101 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1971 23:06:46.258204
1972 23:06:46.258271 [DATLAT]
1973 23:06:46.258332 Freq=800, CH1 RK1
1974 23:06:46.258407
1975 23:06:46.261212 DATLAT Default: 0xa
1976 23:06:46.261297 0, 0xFFFF, sum = 0
1977 23:06:46.264653 1, 0xFFFF, sum = 0
1978 23:06:46.268258 2, 0xFFFF, sum = 0
1979 23:06:46.268342 3, 0xFFFF, sum = 0
1980 23:06:46.271373 4, 0xFFFF, sum = 0
1981 23:06:46.271470 5, 0xFFFF, sum = 0
1982 23:06:46.275034 6, 0xFFFF, sum = 0
1983 23:06:46.275119 7, 0xFFFF, sum = 0
1984 23:06:46.277833 8, 0xFFFF, sum = 0
1985 23:06:46.277918 9, 0x0, sum = 1
1986 23:06:46.281403 10, 0x0, sum = 2
1987 23:06:46.281485 11, 0x0, sum = 3
1988 23:06:46.281566 12, 0x0, sum = 4
1989 23:06:46.284641 best_step = 10
1990 23:06:46.284740
1991 23:06:46.284832 ==
1992 23:06:46.288048 Dram Type= 6, Freq= 0, CH_1, rank 1
1993 23:06:46.291375 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1994 23:06:46.291472 ==
1995 23:06:46.294536 RX Vref Scan: 0
1996 23:06:46.294616
1997 23:06:46.294681 RX Vref 0 -> 0, step: 1
1998 23:06:46.297842
1999 23:06:46.297923 RX Delay -95 -> 252, step: 8
2000 23:06:46.305155 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
2001 23:06:46.308261 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
2002 23:06:46.311317 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
2003 23:06:46.315025 iDelay=209, Bit 3, Center 88 (-23 ~ 200) 224
2004 23:06:46.318340 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
2005 23:06:46.324716 iDelay=209, Bit 5, Center 96 (-15 ~ 208) 224
2006 23:06:46.327947 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
2007 23:06:46.331746 iDelay=209, Bit 7, Center 84 (-31 ~ 200) 232
2008 23:06:46.334631 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
2009 23:06:46.338087 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
2010 23:06:46.344768 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
2011 23:06:46.348168 iDelay=209, Bit 11, Center 72 (-39 ~ 184) 224
2012 23:06:46.351386 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
2013 23:06:46.354818 iDelay=209, Bit 13, Center 92 (-15 ~ 200) 216
2014 23:06:46.361069 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2015 23:06:46.364754 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
2016 23:06:46.364880 ==
2017 23:06:46.368087 Dram Type= 6, Freq= 0, CH_1, rank 1
2018 23:06:46.371481 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2019 23:06:46.371688 ==
2020 23:06:46.374540 DQS Delay:
2021 23:06:46.374638 DQS0 = 0, DQS1 = 0
2022 23:06:46.374745 DQM Delay:
2023 23:06:46.377925 DQM0 = 86, DQM1 = 82
2024 23:06:46.378051 DQ Delay:
2025 23:06:46.382124 DQ0 =88, DQ1 =84, DQ2 =76, DQ3 =88
2026 23:06:46.384473 DQ4 =84, DQ5 =96, DQ6 =92, DQ7 =84
2027 23:06:46.387628 DQ8 =68, DQ9 =72, DQ10 =84, DQ11 =72
2028 23:06:46.391325 DQ12 =92, DQ13 =92, DQ14 =88, DQ15 =88
2029 23:06:46.391475
2030 23:06:46.391559
2031 23:06:46.401184 [DQSOSCAuto] RK1, (LSB)MR18= 0x223d, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 401 ps
2032 23:06:46.401282 CH1 RK1: MR19=606, MR18=223D
2033 23:06:46.408023 CH1_RK1: MR19=0x606, MR18=0x223D, DQSOSC=394, MR23=63, INC=95, DEC=63
2034 23:06:46.411184 [RxdqsGatingPostProcess] freq 800
2035 23:06:46.417660 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2036 23:06:46.420956 Pre-setting of DQS Precalculation
2037 23:06:46.424072 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2038 23:06:46.430864 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2039 23:06:46.441086 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2040 23:06:46.441237
2041 23:06:46.441337
2042 23:06:46.444216 [Calibration Summary] 1600 Mbps
2043 23:06:46.444328 CH 0, Rank 0
2044 23:06:46.447245 SW Impedance : PASS
2045 23:06:46.447353 DUTY Scan : NO K
2046 23:06:46.450618 ZQ Calibration : PASS
2047 23:06:46.454016 Jitter Meter : NO K
2048 23:06:46.454121 CBT Training : PASS
2049 23:06:46.457334 Write leveling : PASS
2050 23:06:46.457438 RX DQS gating : PASS
2051 23:06:46.461237 RX DQ/DQS(RDDQC) : PASS
2052 23:06:46.463995 TX DQ/DQS : PASS
2053 23:06:46.464077 RX DATLAT : PASS
2054 23:06:46.467113 RX DQ/DQS(Engine): PASS
2055 23:06:46.470627 TX OE : NO K
2056 23:06:46.470707 All Pass.
2057 23:06:46.470772
2058 23:06:46.470831 CH 0, Rank 1
2059 23:06:46.473952 SW Impedance : PASS
2060 23:06:46.477514 DUTY Scan : NO K
2061 23:06:46.477595 ZQ Calibration : PASS
2062 23:06:46.480926 Jitter Meter : NO K
2063 23:06:46.484193 CBT Training : PASS
2064 23:06:46.484275 Write leveling : PASS
2065 23:06:46.487293 RX DQS gating : PASS
2066 23:06:46.490412 RX DQ/DQS(RDDQC) : PASS
2067 23:06:46.490494 TX DQ/DQS : PASS
2068 23:06:46.493607 RX DATLAT : PASS
2069 23:06:46.497248 RX DQ/DQS(Engine): PASS
2070 23:06:46.497356 TX OE : NO K
2071 23:06:46.500530 All Pass.
2072 23:06:46.500634
2073 23:06:46.500725 CH 1, Rank 0
2074 23:06:46.504209 SW Impedance : PASS
2075 23:06:46.504312 DUTY Scan : NO K
2076 23:06:46.507231 ZQ Calibration : PASS
2077 23:06:46.510470 Jitter Meter : NO K
2078 23:06:46.510575 CBT Training : PASS
2079 23:06:46.513612 Write leveling : PASS
2080 23:06:46.513717 RX DQS gating : PASS
2081 23:06:46.517063 RX DQ/DQS(RDDQC) : PASS
2082 23:06:46.520320 TX DQ/DQS : PASS
2083 23:06:46.520426 RX DATLAT : PASS
2084 23:06:46.523568 RX DQ/DQS(Engine): PASS
2085 23:06:46.526978 TX OE : NO K
2086 23:06:46.527091 All Pass.
2087 23:06:46.527185
2088 23:06:46.527274 CH 1, Rank 1
2089 23:06:46.530297 SW Impedance : PASS
2090 23:06:46.533571 DUTY Scan : NO K
2091 23:06:46.533719 ZQ Calibration : PASS
2092 23:06:46.537185 Jitter Meter : NO K
2093 23:06:46.540050 CBT Training : PASS
2094 23:06:46.540156 Write leveling : PASS
2095 23:06:46.543788 RX DQS gating : PASS
2096 23:06:46.547060 RX DQ/DQS(RDDQC) : PASS
2097 23:06:46.547140 TX DQ/DQS : PASS
2098 23:06:46.550278 RX DATLAT : PASS
2099 23:06:46.553633 RX DQ/DQS(Engine): PASS
2100 23:06:46.553715 TX OE : NO K
2101 23:06:46.553779 All Pass.
2102 23:06:46.557194
2103 23:06:46.557274 DramC Write-DBI off
2104 23:06:46.560209 PER_BANK_REFRESH: Hybrid Mode
2105 23:06:46.560290 TX_TRACKING: ON
2106 23:06:46.563394 [GetDramInforAfterCalByMRR] Vendor 6.
2107 23:06:46.567002 [GetDramInforAfterCalByMRR] Revision 606.
2108 23:06:46.573302 [GetDramInforAfterCalByMRR] Revision 2 0.
2109 23:06:46.573384 MR0 0x3b3b
2110 23:06:46.573449 MR8 0x5151
2111 23:06:46.576986 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2112 23:06:46.577067
2113 23:06:46.580459 MR0 0x3b3b
2114 23:06:46.580547 MR8 0x5151
2115 23:06:46.583615 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2116 23:06:46.583697
2117 23:06:46.593323 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2118 23:06:46.596618 [FAST_K] Save calibration result to emmc
2119 23:06:46.600099 [FAST_K] Save calibration result to emmc
2120 23:06:46.603408 dram_init: config_dvfs: 1
2121 23:06:46.606917 dramc_set_vcore_voltage set vcore to 662500
2122 23:06:46.609731 Read voltage for 1200, 2
2123 23:06:46.609813 Vio18 = 0
2124 23:06:46.609878 Vcore = 662500
2125 23:06:46.613099 Vdram = 0
2126 23:06:46.613179 Vddq = 0
2127 23:06:46.613243 Vmddr = 0
2128 23:06:46.619609 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2129 23:06:46.623011 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2130 23:06:46.626296 MEM_TYPE=3, freq_sel=15
2131 23:06:46.629617 sv_algorithm_assistance_LP4_1600
2132 23:06:46.632896 ============ PULL DRAM RESETB DOWN ============
2133 23:06:46.636344 ========== PULL DRAM RESETB DOWN end =========
2134 23:06:46.642523 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2135 23:06:46.646023 ===================================
2136 23:06:46.650252 LPDDR4 DRAM CONFIGURATION
2137 23:06:46.652854 ===================================
2138 23:06:46.652936 EX_ROW_EN[0] = 0x0
2139 23:06:46.655864 EX_ROW_EN[1] = 0x0
2140 23:06:46.655944 LP4Y_EN = 0x0
2141 23:06:46.659303 WORK_FSP = 0x0
2142 23:06:46.659406 WL = 0x4
2143 23:06:46.662422 RL = 0x4
2144 23:06:46.662503 BL = 0x2
2145 23:06:46.665989 RPST = 0x0
2146 23:06:46.666099 RD_PRE = 0x0
2147 23:06:46.669055 WR_PRE = 0x1
2148 23:06:46.669136 WR_PST = 0x0
2149 23:06:46.672709 DBI_WR = 0x0
2150 23:06:46.672790 DBI_RD = 0x0
2151 23:06:46.676131 OTF = 0x1
2152 23:06:46.678996 ===================================
2153 23:06:46.682403 ===================================
2154 23:06:46.682484 ANA top config
2155 23:06:46.686270 ===================================
2156 23:06:46.689112 DLL_ASYNC_EN = 0
2157 23:06:46.692255 ALL_SLAVE_EN = 0
2158 23:06:46.695794 NEW_RANK_MODE = 1
2159 23:06:46.695876 DLL_IDLE_MODE = 1
2160 23:06:46.698933 LP45_APHY_COMB_EN = 1
2161 23:06:46.702627 TX_ODT_DIS = 1
2162 23:06:46.705296 NEW_8X_MODE = 1
2163 23:06:46.709032 ===================================
2164 23:06:46.712145 ===================================
2165 23:06:46.715404 data_rate = 2400
2166 23:06:46.718945 CKR = 1
2167 23:06:46.719026 DQ_P2S_RATIO = 8
2168 23:06:46.722063 ===================================
2169 23:06:46.725256 CA_P2S_RATIO = 8
2170 23:06:46.728805 DQ_CA_OPEN = 0
2171 23:06:46.731821 DQ_SEMI_OPEN = 0
2172 23:06:46.735641 CA_SEMI_OPEN = 0
2173 23:06:46.739059 CA_FULL_RATE = 0
2174 23:06:46.739163 DQ_CKDIV4_EN = 0
2175 23:06:46.741621 CA_CKDIV4_EN = 0
2176 23:06:46.745122 CA_PREDIV_EN = 0
2177 23:06:46.748169 PH8_DLY = 17
2178 23:06:46.752045 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2179 23:06:46.755056 DQ_AAMCK_DIV = 4
2180 23:06:46.755160 CA_AAMCK_DIV = 4
2181 23:06:46.758288 CA_ADMCK_DIV = 4
2182 23:06:46.761871 DQ_TRACK_CA_EN = 0
2183 23:06:46.765397 CA_PICK = 1200
2184 23:06:46.768306 CA_MCKIO = 1200
2185 23:06:46.772360 MCKIO_SEMI = 0
2186 23:06:46.775150 PLL_FREQ = 2366
2187 23:06:46.775256 DQ_UI_PI_RATIO = 32
2188 23:06:46.778628 CA_UI_PI_RATIO = 0
2189 23:06:46.781607 ===================================
2190 23:06:46.784678 ===================================
2191 23:06:46.788351 memory_type:LPDDR4
2192 23:06:46.791553 GP_NUM : 10
2193 23:06:46.791658 SRAM_EN : 1
2194 23:06:46.795071 MD32_EN : 0
2195 23:06:46.798001 ===================================
2196 23:06:46.801331 [ANA_INIT] >>>>>>>>>>>>>>
2197 23:06:46.801435 <<<<<< [CONFIGURE PHASE]: ANA_TX
2198 23:06:46.808104 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2199 23:06:46.808211 ===================================
2200 23:06:46.811284 data_rate = 2400,PCW = 0X5b00
2201 23:06:46.815327 ===================================
2202 23:06:46.818438 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2203 23:06:46.825294 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2204 23:06:46.831434 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2205 23:06:46.834979 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2206 23:06:46.838018 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2207 23:06:46.841648 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2208 23:06:46.844821 [ANA_INIT] flow start
2209 23:06:46.844927 [ANA_INIT] PLL >>>>>>>>
2210 23:06:46.848306 [ANA_INIT] PLL <<<<<<<<
2211 23:06:46.851093 [ANA_INIT] MIDPI >>>>>>>>
2212 23:06:46.854488 [ANA_INIT] MIDPI <<<<<<<<
2213 23:06:46.854595 [ANA_INIT] DLL >>>>>>>>
2214 23:06:46.857865 [ANA_INIT] DLL <<<<<<<<
2215 23:06:46.857970 [ANA_INIT] flow end
2216 23:06:46.864876 ============ LP4 DIFF to SE enter ============
2217 23:06:46.868429 ============ LP4 DIFF to SE exit ============
2218 23:06:46.871350 [ANA_INIT] <<<<<<<<<<<<<
2219 23:06:46.874870 [Flow] Enable top DCM control >>>>>
2220 23:06:46.880605 [Flow] Enable top DCM control <<<<<
2221 23:06:46.880716 Enable DLL master slave shuffle
2222 23:06:46.884398 ==============================================================
2223 23:06:46.887924 Gating Mode config
2224 23:06:46.891334 ==============================================================
2225 23:06:46.894418 Config description:
2226 23:06:46.904542 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2227 23:06:46.911153 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2228 23:06:46.914625 SELPH_MODE 0: By rank 1: By Phase
2229 23:06:46.920832 ==============================================================
2230 23:06:46.924590 GAT_TRACK_EN = 1
2231 23:06:46.928430 RX_GATING_MODE = 2
2232 23:06:46.931121 RX_GATING_TRACK_MODE = 2
2233 23:06:46.934084 SELPH_MODE = 1
2234 23:06:46.934190 PICG_EARLY_EN = 1
2235 23:06:46.937797 VALID_LAT_VALUE = 1
2236 23:06:46.944446 ==============================================================
2237 23:06:46.947496 Enter into Gating configuration >>>>
2238 23:06:46.950951 Exit from Gating configuration <<<<
2239 23:06:46.954231 Enter into DVFS_PRE_config >>>>>
2240 23:06:46.964148 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2241 23:06:46.967519 Exit from DVFS_PRE_config <<<<<
2242 23:06:46.971202 Enter into PICG configuration >>>>
2243 23:06:46.973943 Exit from PICG configuration <<<<
2244 23:06:46.977302 [RX_INPUT] configuration >>>>>
2245 23:06:46.980429 [RX_INPUT] configuration <<<<<
2246 23:06:46.987050 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2247 23:06:46.990614 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2248 23:06:46.997149 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2249 23:06:47.003599 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2250 23:06:47.010281 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2251 23:06:47.017184 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2252 23:06:47.020284 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2253 23:06:47.023725 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2254 23:06:47.027062 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2255 23:06:47.033702 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2256 23:06:47.037241 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2257 23:06:47.040131 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2258 23:06:47.043704 ===================================
2259 23:06:47.047186 LPDDR4 DRAM CONFIGURATION
2260 23:06:47.050156 ===================================
2261 23:06:47.050236 EX_ROW_EN[0] = 0x0
2262 23:06:47.053657 EX_ROW_EN[1] = 0x0
2263 23:06:47.053785 LP4Y_EN = 0x0
2264 23:06:47.056972 WORK_FSP = 0x0
2265 23:06:47.060027 WL = 0x4
2266 23:06:47.060105 RL = 0x4
2267 23:06:47.063890 BL = 0x2
2268 23:06:47.063969 RPST = 0x0
2269 23:06:47.066791 RD_PRE = 0x0
2270 23:06:47.066870 WR_PRE = 0x1
2271 23:06:47.069951 WR_PST = 0x0
2272 23:06:47.070031 DBI_WR = 0x0
2273 23:06:47.073427 DBI_RD = 0x0
2274 23:06:47.073506 OTF = 0x1
2275 23:06:47.076706 ===================================
2276 23:06:47.080102 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2277 23:06:47.086729 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2278 23:06:47.090118 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2279 23:06:47.093524 ===================================
2280 23:06:47.096638 LPDDR4 DRAM CONFIGURATION
2281 23:06:47.100378 ===================================
2282 23:06:47.100456 EX_ROW_EN[0] = 0x10
2283 23:06:47.103097 EX_ROW_EN[1] = 0x0
2284 23:06:47.103176 LP4Y_EN = 0x0
2285 23:06:47.106783 WORK_FSP = 0x0
2286 23:06:47.106862 WL = 0x4
2287 23:06:47.109971 RL = 0x4
2288 23:06:47.113200 BL = 0x2
2289 23:06:47.113279 RPST = 0x0
2290 23:06:47.116577 RD_PRE = 0x0
2291 23:06:47.116656 WR_PRE = 0x1
2292 23:06:47.119599 WR_PST = 0x0
2293 23:06:47.119679 DBI_WR = 0x0
2294 23:06:47.122744 DBI_RD = 0x0
2295 23:06:47.122822 OTF = 0x1
2296 23:06:47.126228 ===================================
2297 23:06:47.133130 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2298 23:06:47.133209 ==
2299 23:06:47.135938 Dram Type= 6, Freq= 0, CH_0, rank 0
2300 23:06:47.139617 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2301 23:06:47.139697 ==
2302 23:06:47.142551 [Duty_Offset_Calibration]
2303 23:06:47.146212 B0:2 B1:0 CA:4
2304 23:06:47.146291
2305 23:06:47.149482 [DutyScan_Calibration_Flow] k_type=0
2306 23:06:47.157022
2307 23:06:47.157101 ==CLK 0==
2308 23:06:47.160235 Final CLK duty delay cell = -4
2309 23:06:47.163896 [-4] MAX Duty = 5031%(X100), DQS PI = 14
2310 23:06:47.166528 [-4] MIN Duty = 4844%(X100), DQS PI = 8
2311 23:06:47.170418 [-4] AVG Duty = 4937%(X100)
2312 23:06:47.170518
2313 23:06:47.173084 CH0 CLK Duty spec in!! Max-Min= 187%
2314 23:06:47.176735 [DutyScan_Calibration_Flow] ====Done====
2315 23:06:47.176814
2316 23:06:47.180076 [DutyScan_Calibration_Flow] k_type=1
2317 23:06:47.195630
2318 23:06:47.195710 ==DQS 0 ==
2319 23:06:47.199193 Final DQS duty delay cell = -4
2320 23:06:47.202202 [-4] MAX Duty = 4969%(X100), DQS PI = 54
2321 23:06:47.205357 [-4] MIN Duty = 4844%(X100), DQS PI = 28
2322 23:06:47.208691 [-4] AVG Duty = 4906%(X100)
2323 23:06:47.208799
2324 23:06:47.208861 ==DQS 1 ==
2325 23:06:47.211883 Final DQS duty delay cell = 0
2326 23:06:47.215769 [0] MAX Duty = 5125%(X100), DQS PI = 48
2327 23:06:47.218676 [0] MIN Duty = 4969%(X100), DQS PI = 16
2328 23:06:47.222124 [0] AVG Duty = 5047%(X100)
2329 23:06:47.222202
2330 23:06:47.225779 CH0 DQS 0 Duty spec in!! Max-Min= 125%
2331 23:06:47.225857
2332 23:06:47.228758 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2333 23:06:47.232457 [DutyScan_Calibration_Flow] ====Done====
2334 23:06:47.232560
2335 23:06:47.235319 [DutyScan_Calibration_Flow] k_type=3
2336 23:06:47.252362
2337 23:06:47.252440 ==DQM 0 ==
2338 23:06:47.255907 Final DQM duty delay cell = 0
2339 23:06:47.258959 [0] MAX Duty = 5125%(X100), DQS PI = 20
2340 23:06:47.262723 [0] MIN Duty = 4844%(X100), DQS PI = 52
2341 23:06:47.262802 [0] AVG Duty = 4984%(X100)
2342 23:06:47.265693
2343 23:06:47.265771 ==DQM 1 ==
2344 23:06:47.268889 Final DQM duty delay cell = 0
2345 23:06:47.272345 [0] MAX Duty = 5000%(X100), DQS PI = 8
2346 23:06:47.275584 [0] MIN Duty = 4875%(X100), DQS PI = 12
2347 23:06:47.279566 [0] AVG Duty = 4937%(X100)
2348 23:06:47.279644
2349 23:06:47.282697 CH0 DQM 0 Duty spec in!! Max-Min= 281%
2350 23:06:47.282776
2351 23:06:47.285956 CH0 DQM 1 Duty spec in!! Max-Min= 125%
2352 23:06:47.289292 [DutyScan_Calibration_Flow] ====Done====
2353 23:06:47.289370
2354 23:06:47.292371 [DutyScan_Calibration_Flow] k_type=2
2355 23:06:47.308731
2356 23:06:47.308813 ==DQ 0 ==
2357 23:06:47.312663 Final DQ duty delay cell = 0
2358 23:06:47.315678 [0] MAX Duty = 5156%(X100), DQS PI = 18
2359 23:06:47.318989 [0] MIN Duty = 4969%(X100), DQS PI = 50
2360 23:06:47.319068 [0] AVG Duty = 5062%(X100)
2361 23:06:47.322288
2362 23:06:47.322366 ==DQ 1 ==
2363 23:06:47.326297 Final DQ duty delay cell = 0
2364 23:06:47.328890 [0] MAX Duty = 5156%(X100), DQS PI = 4
2365 23:06:47.332513 [0] MIN Duty = 4938%(X100), DQS PI = 14
2366 23:06:47.332593 [0] AVG Duty = 5047%(X100)
2367 23:06:47.332656
2368 23:06:47.335803 CH0 DQ 0 Duty spec in!! Max-Min= 187%
2369 23:06:47.339002
2370 23:06:47.342137 CH0 DQ 1 Duty spec in!! Max-Min= 218%
2371 23:06:47.345178 [DutyScan_Calibration_Flow] ====Done====
2372 23:06:47.345256 ==
2373 23:06:47.348663 Dram Type= 6, Freq= 0, CH_1, rank 0
2374 23:06:47.352258 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2375 23:06:47.352338 ==
2376 23:06:47.355677 [Duty_Offset_Calibration]
2377 23:06:47.355755 B0:0 B1:-1 CA:3
2378 23:06:47.355818
2379 23:06:47.358879 [DutyScan_Calibration_Flow] k_type=0
2380 23:06:47.368045
2381 23:06:47.368153 ==CLK 0==
2382 23:06:47.371677 Final CLK duty delay cell = -4
2383 23:06:47.374496 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2384 23:06:47.378665 [-4] MIN Duty = 4876%(X100), DQS PI = 36
2385 23:06:47.381461 [-4] AVG Duty = 4938%(X100)
2386 23:06:47.381540
2387 23:06:47.384954 CH1 CLK Duty spec in!! Max-Min= 124%
2388 23:06:47.387923 [DutyScan_Calibration_Flow] ====Done====
2389 23:06:47.388002
2390 23:06:47.391417 [DutyScan_Calibration_Flow] k_type=1
2391 23:06:47.407658
2392 23:06:47.407740 ==DQS 0 ==
2393 23:06:47.411096 Final DQS duty delay cell = 0
2394 23:06:47.414319 [0] MAX Duty = 5187%(X100), DQS PI = 18
2395 23:06:47.417485 [0] MIN Duty = 4907%(X100), DQS PI = 38
2396 23:06:47.420851 [0] AVG Duty = 5047%(X100)
2397 23:06:47.420930
2398 23:06:47.420993 ==DQS 1 ==
2399 23:06:47.424338 Final DQS duty delay cell = 0
2400 23:06:47.427945 [0] MAX Duty = 5156%(X100), DQS PI = 8
2401 23:06:47.430845 [0] MIN Duty = 5031%(X100), DQS PI = 24
2402 23:06:47.434197 [0] AVG Duty = 5093%(X100)
2403 23:06:47.434276
2404 23:06:47.437486 CH1 DQS 0 Duty spec in!! Max-Min= 280%
2405 23:06:47.437565
2406 23:06:47.440995 CH1 DQS 1 Duty spec in!! Max-Min= 125%
2407 23:06:47.444414 [DutyScan_Calibration_Flow] ====Done====
2408 23:06:47.444503
2409 23:06:47.447702 [DutyScan_Calibration_Flow] k_type=3
2410 23:06:47.464173
2411 23:06:47.464253 ==DQM 0 ==
2412 23:06:47.467433 Final DQM duty delay cell = 0
2413 23:06:47.470826 [0] MAX Duty = 5031%(X100), DQS PI = 28
2414 23:06:47.474469 [0] MIN Duty = 4782%(X100), DQS PI = 38
2415 23:06:47.477303 [0] AVG Duty = 4906%(X100)
2416 23:06:47.477383
2417 23:06:47.477445 ==DQM 1 ==
2418 23:06:47.480820 Final DQM duty delay cell = 0
2419 23:06:47.483979 [0] MAX Duty = 4969%(X100), DQS PI = 32
2420 23:06:47.487689 [0] MIN Duty = 4844%(X100), DQS PI = 0
2421 23:06:47.490804 [0] AVG Duty = 4906%(X100)
2422 23:06:47.490908
2423 23:06:47.494155 CH1 DQM 0 Duty spec in!! Max-Min= 249%
2424 23:06:47.494234
2425 23:06:47.497424 CH1 DQM 1 Duty spec in!! Max-Min= 125%
2426 23:06:47.500907 [DutyScan_Calibration_Flow] ====Done====
2427 23:06:47.500987
2428 23:06:47.504291 [DutyScan_Calibration_Flow] k_type=2
2429 23:06:47.519810
2430 23:06:47.519890 ==DQ 0 ==
2431 23:06:47.523414 Final DQ duty delay cell = -4
2432 23:06:47.526574 [-4] MAX Duty = 5031%(X100), DQS PI = 30
2433 23:06:47.529834 [-4] MIN Duty = 4876%(X100), DQS PI = 18
2434 23:06:47.533466 [-4] AVG Duty = 4953%(X100)
2435 23:06:47.533545
2436 23:06:47.533608 ==DQ 1 ==
2437 23:06:47.537168 Final DQ duty delay cell = 0
2438 23:06:47.539501 [0] MAX Duty = 5031%(X100), DQS PI = 34
2439 23:06:47.542928 [0] MIN Duty = 4844%(X100), DQS PI = 62
2440 23:06:47.546356 [0] AVG Duty = 4937%(X100)
2441 23:06:47.546435
2442 23:06:47.549826 CH1 DQ 0 Duty spec in!! Max-Min= 155%
2443 23:06:47.549905
2444 23:06:47.553291 CH1 DQ 1 Duty spec in!! Max-Min= 187%
2445 23:06:47.556303 [DutyScan_Calibration_Flow] ====Done====
2446 23:06:47.559792 nWR fixed to 30
2447 23:06:47.563060 [ModeRegInit_LP4] CH0 RK0
2448 23:06:47.563140 [ModeRegInit_LP4] CH0 RK1
2449 23:06:47.566433 [ModeRegInit_LP4] CH1 RK0
2450 23:06:47.569716 [ModeRegInit_LP4] CH1 RK1
2451 23:06:47.569794 match AC timing 7
2452 23:06:47.576357 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2453 23:06:47.580078 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2454 23:06:47.582985 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2455 23:06:47.589639 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2456 23:06:47.592982 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2457 23:06:47.593061 ==
2458 23:06:47.596666 Dram Type= 6, Freq= 0, CH_0, rank 0
2459 23:06:47.599392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2460 23:06:47.599486 ==
2461 23:06:47.606231 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2462 23:06:47.613234 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2463 23:06:47.620069 [CA 0] Center 39 (9~70) winsize 62
2464 23:06:47.624475 [CA 1] Center 39 (9~70) winsize 62
2465 23:06:47.626895 [CA 2] Center 35 (5~66) winsize 62
2466 23:06:47.630452 [CA 3] Center 35 (5~66) winsize 62
2467 23:06:47.633527 [CA 4] Center 33 (3~64) winsize 62
2468 23:06:47.636758 [CA 5] Center 33 (3~64) winsize 62
2469 23:06:47.636837
2470 23:06:47.640455 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2471 23:06:47.640534
2472 23:06:47.643694 [CATrainingPosCal] consider 1 rank data
2473 23:06:47.646925 u2DelayCellTimex100 = 270/100 ps
2474 23:06:47.650121 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2475 23:06:47.653670 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2476 23:06:47.659952 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2477 23:06:47.664095 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2478 23:06:47.666505 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2479 23:06:47.669848 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2480 23:06:47.669927
2481 23:06:47.673281 CA PerBit enable=1, Macro0, CA PI delay=33
2482 23:06:47.673362
2483 23:06:47.676744 [CBTSetCACLKResult] CA Dly = 33
2484 23:06:47.676824 CS Dly: 7 (0~38)
2485 23:06:47.679967 ==
2486 23:06:47.683122 Dram Type= 6, Freq= 0, CH_0, rank 1
2487 23:06:47.686543 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2488 23:06:47.686625 ==
2489 23:06:47.690163 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2490 23:06:47.696616 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2491 23:06:47.705785 [CA 0] Center 39 (9~70) winsize 62
2492 23:06:47.709699 [CA 1] Center 39 (9~70) winsize 62
2493 23:06:47.713274 [CA 2] Center 35 (5~66) winsize 62
2494 23:06:47.715920 [CA 3] Center 35 (5~66) winsize 62
2495 23:06:47.719138 [CA 4] Center 34 (4~65) winsize 62
2496 23:06:47.722522 [CA 5] Center 33 (3~64) winsize 62
2497 23:06:47.722600
2498 23:06:47.726074 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2499 23:06:47.726153
2500 23:06:47.729151 [CATrainingPosCal] consider 2 rank data
2501 23:06:47.732708 u2DelayCellTimex100 = 270/100 ps
2502 23:06:47.736058 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2503 23:06:47.739009 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2504 23:06:47.745897 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2505 23:06:47.749268 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2506 23:06:47.752520 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
2507 23:06:47.756207 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2508 23:06:47.756285
2509 23:06:47.759065 CA PerBit enable=1, Macro0, CA PI delay=33
2510 23:06:47.759144
2511 23:06:47.762284 [CBTSetCACLKResult] CA Dly = 33
2512 23:06:47.762363 CS Dly: 8 (0~41)
2513 23:06:47.762427
2514 23:06:47.765643 ----->DramcWriteLeveling(PI) begin...
2515 23:06:47.768867 ==
2516 23:06:47.772254 Dram Type= 6, Freq= 0, CH_0, rank 0
2517 23:06:47.775658 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2518 23:06:47.775737 ==
2519 23:06:47.779025 Write leveling (Byte 0): 33 => 33
2520 23:06:47.782329 Write leveling (Byte 1): 27 => 27
2521 23:06:47.786139 DramcWriteLeveling(PI) end<-----
2522 23:06:47.786218
2523 23:06:47.786281 ==
2524 23:06:47.789084 Dram Type= 6, Freq= 0, CH_0, rank 0
2525 23:06:47.792277 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2526 23:06:47.792356 ==
2527 23:06:47.796079 [Gating] SW mode calibration
2528 23:06:47.802851 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2529 23:06:47.809231 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2530 23:06:47.812210 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2531 23:06:47.815408 0 15 4 | B1->B0 | 3131 3434 | 1 1 | (0 0) (1 1)
2532 23:06:47.822382 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2533 23:06:47.825297 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2534 23:06:47.828966 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2535 23:06:47.832213 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2536 23:06:47.839115 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2537 23:06:47.842282 0 15 28 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
2538 23:06:47.845179 1 0 0 | B1->B0 | 3333 2323 | 1 0 | (1 0) (0 0)
2539 23:06:47.852500 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2540 23:06:47.855498 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2541 23:06:47.858840 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2542 23:06:47.865125 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2543 23:06:47.868420 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2544 23:06:47.871799 1 0 24 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
2545 23:06:47.878758 1 0 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
2546 23:06:47.881670 1 1 0 | B1->B0 | 2626 4646 | 0 0 | (0 0) (0 0)
2547 23:06:47.885764 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2548 23:06:47.892033 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2549 23:06:47.895244 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2550 23:06:47.898947 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2551 23:06:47.905365 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2552 23:06:47.908595 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2553 23:06:47.912048 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2554 23:06:47.918176 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2555 23:06:47.921674 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2556 23:06:47.925181 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2557 23:06:47.931681 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2558 23:06:47.935085 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2559 23:06:47.938394 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 23:06:47.945204 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 23:06:47.948422 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2562 23:06:47.952071 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 23:06:47.955599 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 23:06:47.961691 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 23:06:47.965109 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 23:06:47.968702 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 23:06:47.975290 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2568 23:06:47.978414 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2569 23:06:47.981733 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2570 23:06:47.984847 Total UI for P1: 0, mck2ui 16
2571 23:06:47.988012 best dqsien dly found for B0: ( 1, 3, 26)
2572 23:06:47.995670 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2573 23:06:47.998091 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2574 23:06:48.001412 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2575 23:06:48.004740 Total UI for P1: 0, mck2ui 16
2576 23:06:48.008636 best dqsien dly found for B1: ( 1, 4, 0)
2577 23:06:48.011660 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2578 23:06:48.014920 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2579 23:06:48.014999
2580 23:06:48.021772 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2581 23:06:48.024971 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2582 23:06:48.028091 [Gating] SW calibration Done
2583 23:06:48.028170 ==
2584 23:06:48.031299 Dram Type= 6, Freq= 0, CH_0, rank 0
2585 23:06:48.034869 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2586 23:06:48.034949 ==
2587 23:06:48.035013 RX Vref Scan: 0
2588 23:06:48.035075
2589 23:06:48.038209 RX Vref 0 -> 0, step: 1
2590 23:06:48.038288
2591 23:06:48.041636 RX Delay -40 -> 252, step: 8
2592 23:06:48.044597 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2593 23:06:48.048426 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2594 23:06:48.055324 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2595 23:06:48.058287 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2596 23:06:48.061519 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
2597 23:06:48.064467 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2598 23:06:48.067985 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2599 23:06:48.071674 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2600 23:06:48.078284 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2601 23:06:48.081422 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2602 23:06:48.084839 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2603 23:06:48.087843 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2604 23:06:48.091111 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2605 23:06:48.098300 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2606 23:06:48.101265 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2607 23:06:48.104374 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2608 23:06:48.104454 ==
2609 23:06:48.107812 Dram Type= 6, Freq= 0, CH_0, rank 0
2610 23:06:48.111153 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2611 23:06:48.114399 ==
2612 23:06:48.114479 DQS Delay:
2613 23:06:48.114542 DQS0 = 0, DQS1 = 0
2614 23:06:48.117513 DQM Delay:
2615 23:06:48.117592 DQM0 = 119, DQM1 = 107
2616 23:06:48.121286 DQ Delay:
2617 23:06:48.124664 DQ0 =115, DQ1 =119, DQ2 =119, DQ3 =111
2618 23:06:48.127395 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =127
2619 23:06:48.130889 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2620 23:06:48.134275 DQ12 =119, DQ13 =111, DQ14 =119, DQ15 =111
2621 23:06:48.134355
2622 23:06:48.134417
2623 23:06:48.134475 ==
2624 23:06:48.137514 Dram Type= 6, Freq= 0, CH_0, rank 0
2625 23:06:48.140895 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2626 23:06:48.140974 ==
2627 23:06:48.144170
2628 23:06:48.144249
2629 23:06:48.144312 TX Vref Scan disable
2630 23:06:48.147285 == TX Byte 0 ==
2631 23:06:48.150946 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2632 23:06:48.154253 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2633 23:06:48.157617 == TX Byte 1 ==
2634 23:06:48.160841 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2635 23:06:48.164065 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2636 23:06:48.164144 ==
2637 23:06:48.167098 Dram Type= 6, Freq= 0, CH_0, rank 0
2638 23:06:48.174132 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2639 23:06:48.174211 ==
2640 23:06:48.185320 TX Vref=22, minBit 4, minWin=25, winSum=413
2641 23:06:48.188730 TX Vref=24, minBit 5, minWin=25, winSum=420
2642 23:06:48.191841 TX Vref=26, minBit 0, minWin=26, winSum=420
2643 23:06:48.195131 TX Vref=28, minBit 4, minWin=25, winSum=427
2644 23:06:48.198445 TX Vref=30, minBit 1, minWin=26, winSum=430
2645 23:06:48.201968 TX Vref=32, minBit 8, minWin=26, winSum=427
2646 23:06:48.209221 [TxChooseVref] Worse bit 1, Min win 26, Win sum 430, Final Vref 30
2647 23:06:48.209303
2648 23:06:48.212017 Final TX Range 1 Vref 30
2649 23:06:48.212098
2650 23:06:48.212162 ==
2651 23:06:48.214792 Dram Type= 6, Freq= 0, CH_0, rank 0
2652 23:06:48.218222 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2653 23:06:48.218303 ==
2654 23:06:48.221621
2655 23:06:48.221701
2656 23:06:48.221765 TX Vref Scan disable
2657 23:06:48.225244 == TX Byte 0 ==
2658 23:06:48.229034 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2659 23:06:48.232436 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2660 23:06:48.235138 == TX Byte 1 ==
2661 23:06:48.238384 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2662 23:06:48.241536 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2663 23:06:48.244976
2664 23:06:48.245057 [DATLAT]
2665 23:06:48.245120 Freq=1200, CH0 RK0
2666 23:06:48.245179
2667 23:06:48.248413 DATLAT Default: 0xd
2668 23:06:48.248493 0, 0xFFFF, sum = 0
2669 23:06:48.251523 1, 0xFFFF, sum = 0
2670 23:06:48.251605 2, 0xFFFF, sum = 0
2671 23:06:48.255107 3, 0xFFFF, sum = 0
2672 23:06:48.258112 4, 0xFFFF, sum = 0
2673 23:06:48.258194 5, 0xFFFF, sum = 0
2674 23:06:48.261206 6, 0xFFFF, sum = 0
2675 23:06:48.261288 7, 0xFFFF, sum = 0
2676 23:06:48.265086 8, 0xFFFF, sum = 0
2677 23:06:48.265168 9, 0xFFFF, sum = 0
2678 23:06:48.267968 10, 0xFFFF, sum = 0
2679 23:06:48.268049 11, 0xFFFF, sum = 0
2680 23:06:48.271600 12, 0x0, sum = 1
2681 23:06:48.271681 13, 0x0, sum = 2
2682 23:06:48.274896 14, 0x0, sum = 3
2683 23:06:48.274977 15, 0x0, sum = 4
2684 23:06:48.278149 best_step = 13
2685 23:06:48.278228
2686 23:06:48.278292 ==
2687 23:06:48.281382 Dram Type= 6, Freq= 0, CH_0, rank 0
2688 23:06:48.284808 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2689 23:06:48.284888 ==
2690 23:06:48.284952 RX Vref Scan: 1
2691 23:06:48.285011
2692 23:06:48.287897 Set Vref Range= 32 -> 127
2693 23:06:48.287976
2694 23:06:48.290987 RX Vref 32 -> 127, step: 1
2695 23:06:48.291065
2696 23:06:48.294413 RX Delay -21 -> 252, step: 4
2697 23:06:48.294492
2698 23:06:48.297878 Set Vref, RX VrefLevel [Byte0]: 32
2699 23:06:48.301277 [Byte1]: 32
2700 23:06:48.301356
2701 23:06:48.304400 Set Vref, RX VrefLevel [Byte0]: 33
2702 23:06:48.307911 [Byte1]: 33
2703 23:06:48.311546
2704 23:06:48.311625 Set Vref, RX VrefLevel [Byte0]: 34
2705 23:06:48.314761 [Byte1]: 34
2706 23:06:48.319432
2707 23:06:48.319511 Set Vref, RX VrefLevel [Byte0]: 35
2708 23:06:48.322977 [Byte1]: 35
2709 23:06:48.327219
2710 23:06:48.327298 Set Vref, RX VrefLevel [Byte0]: 36
2711 23:06:48.330629 [Byte1]: 36
2712 23:06:48.335210
2713 23:06:48.335314 Set Vref, RX VrefLevel [Byte0]: 37
2714 23:06:48.338294 [Byte1]: 37
2715 23:06:48.343193
2716 23:06:48.343286 Set Vref, RX VrefLevel [Byte0]: 38
2717 23:06:48.346550 [Byte1]: 38
2718 23:06:48.351414
2719 23:06:48.351507 Set Vref, RX VrefLevel [Byte0]: 39
2720 23:06:48.354205 [Byte1]: 39
2721 23:06:48.359066
2722 23:06:48.359146 Set Vref, RX VrefLevel [Byte0]: 40
2723 23:06:48.362344 [Byte1]: 40
2724 23:06:48.366988
2725 23:06:48.367069 Set Vref, RX VrefLevel [Byte0]: 41
2726 23:06:48.370215 [Byte1]: 41
2727 23:06:48.375001
2728 23:06:48.375081 Set Vref, RX VrefLevel [Byte0]: 42
2729 23:06:48.378285 [Byte1]: 42
2730 23:06:48.382644
2731 23:06:48.382726 Set Vref, RX VrefLevel [Byte0]: 43
2732 23:06:48.386290 [Byte1]: 43
2733 23:06:48.390514
2734 23:06:48.390616 Set Vref, RX VrefLevel [Byte0]: 44
2735 23:06:48.394291 [Byte1]: 44
2736 23:06:48.398572
2737 23:06:48.398656 Set Vref, RX VrefLevel [Byte0]: 45
2738 23:06:48.402280 [Byte1]: 45
2739 23:06:48.406581
2740 23:06:48.406681 Set Vref, RX VrefLevel [Byte0]: 46
2741 23:06:48.409760 [Byte1]: 46
2742 23:06:48.414486
2743 23:06:48.414578 Set Vref, RX VrefLevel [Byte0]: 47
2744 23:06:48.417966 [Byte1]: 47
2745 23:06:48.422580
2746 23:06:48.422714 Set Vref, RX VrefLevel [Byte0]: 48
2747 23:06:48.425858 [Byte1]: 48
2748 23:06:48.430369
2749 23:06:48.430504 Set Vref, RX VrefLevel [Byte0]: 49
2750 23:06:48.433512 [Byte1]: 49
2751 23:06:48.438199
2752 23:06:48.438332 Set Vref, RX VrefLevel [Byte0]: 50
2753 23:06:48.441409 [Byte1]: 50
2754 23:06:48.446214
2755 23:06:48.446302 Set Vref, RX VrefLevel [Byte0]: 51
2756 23:06:48.449827 [Byte1]: 51
2757 23:06:48.454665
2758 23:06:48.454753 Set Vref, RX VrefLevel [Byte0]: 52
2759 23:06:48.457434 [Byte1]: 52
2760 23:06:48.461851
2761 23:06:48.461945 Set Vref, RX VrefLevel [Byte0]: 53
2762 23:06:48.465385 [Byte1]: 53
2763 23:06:48.470058
2764 23:06:48.470153 Set Vref, RX VrefLevel [Byte0]: 54
2765 23:06:48.473668 [Byte1]: 54
2766 23:06:48.477884
2767 23:06:48.477989 Set Vref, RX VrefLevel [Byte0]: 55
2768 23:06:48.481994 [Byte1]: 55
2769 23:06:48.485906
2770 23:06:48.486005 Set Vref, RX VrefLevel [Byte0]: 56
2771 23:06:48.489318 [Byte1]: 56
2772 23:06:48.493852
2773 23:06:48.493972 Set Vref, RX VrefLevel [Byte0]: 57
2774 23:06:48.497461 [Byte1]: 57
2775 23:06:48.501857
2776 23:06:48.501994 Set Vref, RX VrefLevel [Byte0]: 58
2777 23:06:48.505115 [Byte1]: 58
2778 23:06:48.509873
2779 23:06:48.509994 Set Vref, RX VrefLevel [Byte0]: 59
2780 23:06:48.512797 [Byte1]: 59
2781 23:06:48.517517
2782 23:06:48.517615 Set Vref, RX VrefLevel [Byte0]: 60
2783 23:06:48.520986 [Byte1]: 60
2784 23:06:48.525804
2785 23:06:48.525929 Set Vref, RX VrefLevel [Byte0]: 61
2786 23:06:48.528783 [Byte1]: 61
2787 23:06:48.533584
2788 23:06:48.533681 Set Vref, RX VrefLevel [Byte0]: 62
2789 23:06:48.537199 [Byte1]: 62
2790 23:06:48.541196
2791 23:06:48.541291 Set Vref, RX VrefLevel [Byte0]: 63
2792 23:06:48.544964 [Byte1]: 63
2793 23:06:48.549358
2794 23:06:48.549472 Set Vref, RX VrefLevel [Byte0]: 64
2795 23:06:48.553305 [Byte1]: 64
2796 23:06:48.556997
2797 23:06:48.557094 Set Vref, RX VrefLevel [Byte0]: 65
2798 23:06:48.560908 [Byte1]: 65
2799 23:06:48.565376
2800 23:06:48.565474 Set Vref, RX VrefLevel [Byte0]: 66
2801 23:06:48.568721 [Byte1]: 66
2802 23:06:48.573806
2803 23:06:48.573911 Set Vref, RX VrefLevel [Byte0]: 67
2804 23:06:48.576715 [Byte1]: 67
2805 23:06:48.580818
2806 23:06:48.580923 Set Vref, RX VrefLevel [Byte0]: 68
2807 23:06:48.584502 [Byte1]: 68
2808 23:06:48.588812
2809 23:06:48.588940 Set Vref, RX VrefLevel [Byte0]: 69
2810 23:06:48.592387 [Byte1]: 69
2811 23:06:48.597030
2812 23:06:48.597156 Final RX Vref Byte 0 = 52 to rank0
2813 23:06:48.600453 Final RX Vref Byte 1 = 50 to rank0
2814 23:06:48.603276 Final RX Vref Byte 0 = 52 to rank1
2815 23:06:48.606931 Final RX Vref Byte 1 = 50 to rank1==
2816 23:06:48.610097 Dram Type= 6, Freq= 0, CH_0, rank 0
2817 23:06:48.617018 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2818 23:06:48.617154 ==
2819 23:06:48.617222 DQS Delay:
2820 23:06:48.617281 DQS0 = 0, DQS1 = 0
2821 23:06:48.620194 DQM Delay:
2822 23:06:48.620277 DQM0 = 117, DQM1 = 104
2823 23:06:48.623547 DQ Delay:
2824 23:06:48.626678 DQ0 =118, DQ1 =116, DQ2 =114, DQ3 =114
2825 23:06:48.629722 DQ4 =118, DQ5 =110, DQ6 =124, DQ7 =122
2826 23:06:48.633546 DQ8 =92, DQ9 =88, DQ10 =106, DQ11 =100
2827 23:06:48.636372 DQ12 =112, DQ13 =110, DQ14 =116, DQ15 =112
2828 23:06:48.636468
2829 23:06:48.636532
2830 23:06:48.643036 [DQSOSCAuto] RK0, (LSB)MR18= 0x3ff, (MSB)MR19= 0x403, tDQSOscB0 = 410 ps tDQSOscB1 = 408 ps
2831 23:06:48.646403 CH0 RK0: MR19=403, MR18=3FF
2832 23:06:48.653011 CH0_RK0: MR19=0x403, MR18=0x3FF, DQSOSC=408, MR23=63, INC=39, DEC=26
2833 23:06:48.653166
2834 23:06:48.656519 ----->DramcWriteLeveling(PI) begin...
2835 23:06:48.656650 ==
2836 23:06:48.659795 Dram Type= 6, Freq= 0, CH_0, rank 1
2837 23:06:48.663293 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2838 23:06:48.667182 ==
2839 23:06:48.667321 Write leveling (Byte 0): 33 => 33
2840 23:06:48.669470 Write leveling (Byte 1): 27 => 27
2841 23:06:48.673253 DramcWriteLeveling(PI) end<-----
2842 23:06:48.673416
2843 23:06:48.673484 ==
2844 23:06:48.676654 Dram Type= 6, Freq= 0, CH_0, rank 1
2845 23:06:48.683225 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2846 23:06:48.683425 ==
2847 23:06:48.686387 [Gating] SW mode calibration
2848 23:06:48.692982 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2849 23:06:48.696022 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2850 23:06:48.703031 0 15 0 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
2851 23:06:48.706060 0 15 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
2852 23:06:48.709604 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2853 23:06:48.716198 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2854 23:06:48.719797 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2855 23:06:48.722887 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2856 23:06:48.726402 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
2857 23:06:48.732625 0 15 28 | B1->B0 | 3434 2929 | 1 0 | (1 1) (0 1)
2858 23:06:48.736066 1 0 0 | B1->B0 | 2d2d 2323 | 1 0 | (1 0) (0 0)
2859 23:06:48.739550 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2860 23:06:48.745865 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2861 23:06:48.749577 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2862 23:06:48.752729 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2863 23:06:48.759466 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2864 23:06:48.762455 1 0 24 | B1->B0 | 2323 3535 | 0 0 | (0 0) (0 0)
2865 23:06:48.765929 1 0 28 | B1->B0 | 2d2d 4646 | 0 0 | (0 0) (0 0)
2866 23:06:48.772414 1 1 0 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
2867 23:06:48.776281 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2868 23:06:48.779162 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2869 23:06:48.785993 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2870 23:06:48.789137 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2871 23:06:48.792216 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2872 23:06:48.799255 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2873 23:06:48.802410 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2874 23:06:48.805465 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2875 23:06:48.812447 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2876 23:06:48.815644 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2877 23:06:48.818843 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2878 23:06:48.825731 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2879 23:06:48.828917 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2880 23:06:48.832145 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2881 23:06:48.838694 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2882 23:06:48.842256 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2883 23:06:48.845537 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2884 23:06:48.851811 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2885 23:06:48.855250 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2886 23:06:48.858330 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2887 23:06:48.865529 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2888 23:06:48.868647 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2889 23:06:48.872134 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2890 23:06:48.878505 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2891 23:06:48.878657 Total UI for P1: 0, mck2ui 16
2892 23:06:48.885176 best dqsien dly found for B0: ( 1, 3, 26)
2893 23:06:48.888399 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2894 23:06:48.891938 Total UI for P1: 0, mck2ui 16
2895 23:06:48.895853 best dqsien dly found for B1: ( 1, 4, 0)
2896 23:06:48.899142 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2897 23:06:48.901641 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2898 23:06:48.901796
2899 23:06:48.905110 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2900 23:06:48.908246 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2901 23:06:48.912318 [Gating] SW calibration Done
2902 23:06:48.912458 ==
2903 23:06:48.914780 Dram Type= 6, Freq= 0, CH_0, rank 1
2904 23:06:48.918911 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2905 23:06:48.919053 ==
2906 23:06:48.921526 RX Vref Scan: 0
2907 23:06:48.921628
2908 23:06:48.924804 RX Vref 0 -> 0, step: 1
2909 23:06:48.924918
2910 23:06:48.924986 RX Delay -40 -> 252, step: 8
2911 23:06:48.931336 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2912 23:06:48.935428 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2913 23:06:48.938487 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2914 23:06:48.942210 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2915 23:06:48.945096 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2916 23:06:48.951612 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2917 23:06:48.954973 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2918 23:06:48.958254 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
2919 23:06:48.961640 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2920 23:06:48.965023 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2921 23:06:48.971526 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2922 23:06:48.974957 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2923 23:06:48.978042 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2924 23:06:48.981607 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2925 23:06:48.985147 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2926 23:06:48.991321 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2927 23:06:48.991541 ==
2928 23:06:48.994953 Dram Type= 6, Freq= 0, CH_0, rank 1
2929 23:06:48.998056 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2930 23:06:48.998181 ==
2931 23:06:48.998249 DQS Delay:
2932 23:06:49.001821 DQS0 = 0, DQS1 = 0
2933 23:06:49.001947 DQM Delay:
2934 23:06:49.004594 DQM0 = 115, DQM1 = 106
2935 23:06:49.004697 DQ Delay:
2936 23:06:49.008225 DQ0 =111, DQ1 =119, DQ2 =111, DQ3 =111
2937 23:06:49.011288 DQ4 =119, DQ5 =103, DQ6 =127, DQ7 =119
2938 23:06:49.014521 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2939 23:06:49.018901 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2940 23:06:49.019046
2941 23:06:49.019113
2942 23:06:49.021430 ==
2943 23:06:49.025148 Dram Type= 6, Freq= 0, CH_0, rank 1
2944 23:06:49.028043 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2945 23:06:49.028163 ==
2946 23:06:49.028230
2947 23:06:49.028288
2948 23:06:49.031015 TX Vref Scan disable
2949 23:06:49.031115 == TX Byte 0 ==
2950 23:06:49.034500 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2951 23:06:49.041403 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2952 23:06:49.041560 == TX Byte 1 ==
2953 23:06:49.044554 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2954 23:06:49.051302 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2955 23:06:49.051504 ==
2956 23:06:49.054642 Dram Type= 6, Freq= 0, CH_0, rank 1
2957 23:06:49.058047 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2958 23:06:49.058173 ==
2959 23:06:49.070655 TX Vref=22, minBit 10, minWin=25, winSum=419
2960 23:06:49.073896 TX Vref=24, minBit 1, minWin=26, winSum=423
2961 23:06:49.077285 TX Vref=26, minBit 10, minWin=25, winSum=424
2962 23:06:49.080073 TX Vref=28, minBit 2, minWin=26, winSum=427
2963 23:06:49.083257 TX Vref=30, minBit 15, minWin=25, winSum=429
2964 23:06:49.090534 TX Vref=32, minBit 14, minWin=25, winSum=425
2965 23:06:49.093374 [TxChooseVref] Worse bit 2, Min win 26, Win sum 427, Final Vref 28
2966 23:06:49.093500
2967 23:06:49.096490 Final TX Range 1 Vref 28
2968 23:06:49.096604
2969 23:06:49.096671 ==
2970 23:06:49.099916 Dram Type= 6, Freq= 0, CH_0, rank 1
2971 23:06:49.107013 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2972 23:06:49.107208 ==
2973 23:06:49.107309
2974 23:06:49.107437
2975 23:06:49.107497 TX Vref Scan disable
2976 23:06:49.110755 == TX Byte 0 ==
2977 23:06:49.113885 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2978 23:06:49.117385 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2979 23:06:49.120946 == TX Byte 1 ==
2980 23:06:49.123922 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2981 23:06:49.127191 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2982 23:06:49.130386
2983 23:06:49.130520 [DATLAT]
2984 23:06:49.130588 Freq=1200, CH0 RK1
2985 23:06:49.130649
2986 23:06:49.134009 DATLAT Default: 0xd
2987 23:06:49.134118 0, 0xFFFF, sum = 0
2988 23:06:49.137426 1, 0xFFFF, sum = 0
2989 23:06:49.137545 2, 0xFFFF, sum = 0
2990 23:06:49.140792 3, 0xFFFF, sum = 0
2991 23:06:49.140906 4, 0xFFFF, sum = 0
2992 23:06:49.143873 5, 0xFFFF, sum = 0
2993 23:06:49.147280 6, 0xFFFF, sum = 0
2994 23:06:49.147466 7, 0xFFFF, sum = 0
2995 23:06:49.150541 8, 0xFFFF, sum = 0
2996 23:06:49.150699 9, 0xFFFF, sum = 0
2997 23:06:49.153624 10, 0xFFFF, sum = 0
2998 23:06:49.153737 11, 0xFFFF, sum = 0
2999 23:06:49.157153 12, 0x0, sum = 1
3000 23:06:49.157279 13, 0x0, sum = 2
3001 23:06:49.160388 14, 0x0, sum = 3
3002 23:06:49.160500 15, 0x0, sum = 4
3003 23:06:49.160569 best_step = 13
3004 23:06:49.163624
3005 23:06:49.163731 ==
3006 23:06:49.166760 Dram Type= 6, Freq= 0, CH_0, rank 1
3007 23:06:49.170125 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3008 23:06:49.170264 ==
3009 23:06:49.170369 RX Vref Scan: 0
3010 23:06:49.170443
3011 23:06:49.173246 RX Vref 0 -> 0, step: 1
3012 23:06:49.173346
3013 23:06:49.176765 RX Delay -21 -> 252, step: 4
3014 23:06:49.180647 iDelay=195, Bit 0, Center 114 (51 ~ 178) 128
3015 23:06:49.186845 iDelay=195, Bit 1, Center 116 (47 ~ 186) 140
3016 23:06:49.190441 iDelay=195, Bit 2, Center 112 (47 ~ 178) 132
3017 23:06:49.193367 iDelay=195, Bit 3, Center 112 (47 ~ 178) 132
3018 23:06:49.196977 iDelay=195, Bit 4, Center 118 (51 ~ 186) 136
3019 23:06:49.200151 iDelay=195, Bit 5, Center 108 (43 ~ 174) 132
3020 23:06:49.207302 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3021 23:06:49.209582 iDelay=195, Bit 7, Center 120 (55 ~ 186) 132
3022 23:06:49.213399 iDelay=195, Bit 8, Center 96 (27 ~ 166) 140
3023 23:06:49.216720 iDelay=195, Bit 9, Center 92 (23 ~ 162) 140
3024 23:06:49.219756 iDelay=195, Bit 10, Center 108 (39 ~ 178) 140
3025 23:06:49.226424 iDelay=195, Bit 11, Center 98 (31 ~ 166) 136
3026 23:06:49.229531 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
3027 23:06:49.233552 iDelay=195, Bit 13, Center 110 (43 ~ 178) 136
3028 23:06:49.236431 iDelay=195, Bit 14, Center 120 (55 ~ 186) 132
3029 23:06:49.243596 iDelay=195, Bit 15, Center 112 (47 ~ 178) 132
3030 23:06:49.243796 ==
3031 23:06:49.246532 Dram Type= 6, Freq= 0, CH_0, rank 1
3032 23:06:49.249645 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3033 23:06:49.249803 ==
3034 23:06:49.249908 DQS Delay:
3035 23:06:49.253396 DQS0 = 0, DQS1 = 0
3036 23:06:49.253551 DQM Delay:
3037 23:06:49.256248 DQM0 = 115, DQM1 = 106
3038 23:06:49.256377 DQ Delay:
3039 23:06:49.259655 DQ0 =114, DQ1 =116, DQ2 =112, DQ3 =112
3040 23:06:49.262722 DQ4 =118, DQ5 =108, DQ6 =126, DQ7 =120
3041 23:06:49.266420 DQ8 =96, DQ9 =92, DQ10 =108, DQ11 =98
3042 23:06:49.269308 DQ12 =112, DQ13 =110, DQ14 =120, DQ15 =112
3043 23:06:49.269468
3044 23:06:49.269571
3045 23:06:49.279020 [DQSOSCAuto] RK1, (LSB)MR18= 0xfffc, (MSB)MR19= 0x303, tDQSOscB0 = 411 ps tDQSOscB1 = 410 ps
3046 23:06:49.282880 CH0 RK1: MR19=303, MR18=FFFC
3047 23:06:49.286363 CH0_RK1: MR19=0x303, MR18=0xFFFC, DQSOSC=410, MR23=63, INC=39, DEC=26
3048 23:06:49.289840 [RxdqsGatingPostProcess] freq 1200
3049 23:06:49.295737 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3050 23:06:49.299580 best DQS0 dly(2T, 0.5T) = (0, 11)
3051 23:06:49.302928 best DQS1 dly(2T, 0.5T) = (0, 12)
3052 23:06:49.305807 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3053 23:06:49.309421 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3054 23:06:49.312788 best DQS0 dly(2T, 0.5T) = (0, 11)
3055 23:06:49.316938 best DQS1 dly(2T, 0.5T) = (0, 12)
3056 23:06:49.319024 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3057 23:06:49.322240 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3058 23:06:49.325559 Pre-setting of DQS Precalculation
3059 23:06:49.328808 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3060 23:06:49.328974 ==
3061 23:06:49.332074 Dram Type= 6, Freq= 0, CH_1, rank 0
3062 23:06:49.335839 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3063 23:06:49.336012 ==
3064 23:06:49.342046 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3065 23:06:49.349112 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3066 23:06:49.357000 [CA 0] Center 38 (8~68) winsize 61
3067 23:06:49.360030 [CA 1] Center 37 (7~68) winsize 62
3068 23:06:49.363387 [CA 2] Center 35 (5~65) winsize 61
3069 23:06:49.366922 [CA 3] Center 34 (5~64) winsize 60
3070 23:06:49.369910 [CA 4] Center 34 (4~65) winsize 62
3071 23:06:49.373244 [CA 5] Center 33 (3~64) winsize 62
3072 23:06:49.373417
3073 23:06:49.376414 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3074 23:06:49.376566
3075 23:06:49.379584 [CATrainingPosCal] consider 1 rank data
3076 23:06:49.383227 u2DelayCellTimex100 = 270/100 ps
3077 23:06:49.386192 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3078 23:06:49.393356 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3079 23:06:49.396345 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3080 23:06:49.399823 CA3 delay=34 (5~64),Diff = 1 PI (4 cell)
3081 23:06:49.403719 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3082 23:06:49.406267 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3083 23:06:49.406436
3084 23:06:49.409630 CA PerBit enable=1, Macro0, CA PI delay=33
3085 23:06:49.409785
3086 23:06:49.412907 [CBTSetCACLKResult] CA Dly = 33
3087 23:06:49.416265 CS Dly: 4 (0~35)
3088 23:06:49.416440 ==
3089 23:06:49.419680 Dram Type= 6, Freq= 0, CH_1, rank 1
3090 23:06:49.422718 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3091 23:06:49.422874 ==
3092 23:06:49.429601 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3093 23:06:49.432650 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3094 23:06:49.442289 [CA 0] Center 37 (7~68) winsize 62
3095 23:06:49.445574 [CA 1] Center 38 (8~68) winsize 61
3096 23:06:49.448867 [CA 2] Center 35 (5~65) winsize 61
3097 23:06:49.452957 [CA 3] Center 33 (3~64) winsize 62
3098 23:06:49.455577 [CA 4] Center 34 (4~64) winsize 61
3099 23:06:49.458847 [CA 5] Center 33 (3~63) winsize 61
3100 23:06:49.459008
3101 23:06:49.462107 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3102 23:06:49.462249
3103 23:06:49.465119 [CATrainingPosCal] consider 2 rank data
3104 23:06:49.469086 u2DelayCellTimex100 = 270/100 ps
3105 23:06:49.472104 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3106 23:06:49.478585 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3107 23:06:49.481920 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3108 23:06:49.484943 CA3 delay=34 (5~64),Diff = 1 PI (4 cell)
3109 23:06:49.488218 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3110 23:06:49.491833 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3111 23:06:49.492004
3112 23:06:49.494833 CA PerBit enable=1, Macro0, CA PI delay=33
3113 23:06:49.494982
3114 23:06:49.498571 [CBTSetCACLKResult] CA Dly = 33
3115 23:06:49.501788 CS Dly: 6 (0~39)
3116 23:06:49.501965
3117 23:06:49.504746 ----->DramcWriteLeveling(PI) begin...
3118 23:06:49.504884 ==
3119 23:06:49.508303 Dram Type= 6, Freq= 0, CH_1, rank 0
3120 23:06:49.511871 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3121 23:06:49.512046 ==
3122 23:06:49.514742 Write leveling (Byte 0): 24 => 24
3123 23:06:49.518290 Write leveling (Byte 1): 27 => 27
3124 23:06:49.521423 DramcWriteLeveling(PI) end<-----
3125 23:06:49.521581
3126 23:06:49.521684 ==
3127 23:06:49.524828 Dram Type= 6, Freq= 0, CH_1, rank 0
3128 23:06:49.528052 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3129 23:06:49.528182 ==
3130 23:06:49.531593 [Gating] SW mode calibration
3131 23:06:49.537814 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3132 23:06:49.544598 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3133 23:06:49.547786 0 15 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
3134 23:06:49.551039 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3135 23:06:49.557611 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3136 23:06:49.561313 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3137 23:06:49.564655 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3138 23:06:49.571145 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3139 23:06:49.574470 0 15 24 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
3140 23:06:49.577472 0 15 28 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (1 0)
3141 23:06:49.584542 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3142 23:06:49.587866 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3143 23:06:49.591485 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3144 23:06:49.597420 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3145 23:06:49.601104 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3146 23:06:49.604359 1 0 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3147 23:06:49.611325 1 0 24 | B1->B0 | 2525 2d2d | 0 0 | (0 0) (0 0)
3148 23:06:49.614653 1 0 28 | B1->B0 | 3d3d 4444 | 0 0 | (0 0) (0 0)
3149 23:06:49.617752 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3150 23:06:49.624361 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3151 23:06:49.627518 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3152 23:06:49.631259 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3153 23:06:49.637643 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3154 23:06:49.641315 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3155 23:06:49.644454 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3156 23:06:49.647264 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3157 23:06:49.654336 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3158 23:06:49.657475 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3159 23:06:49.661308 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3160 23:06:49.667773 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3161 23:06:49.670858 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3162 23:06:49.674247 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3163 23:06:49.681261 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3164 23:06:49.684609 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3165 23:06:49.687608 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3166 23:06:49.693850 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3167 23:06:49.697464 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3168 23:06:49.701103 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3169 23:06:49.707540 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3170 23:06:49.710660 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3171 23:06:49.714017 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3172 23:06:49.720771 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3173 23:06:49.723737 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3174 23:06:49.727948 Total UI for P1: 0, mck2ui 16
3175 23:06:49.730404 best dqsien dly found for B0: ( 1, 3, 26)
3176 23:06:49.733631 Total UI for P1: 0, mck2ui 16
3177 23:06:49.737367 best dqsien dly found for B1: ( 1, 3, 28)
3178 23:06:49.740294 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3179 23:06:49.744076 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3180 23:06:49.744216
3181 23:06:49.747310 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3182 23:06:49.750643 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3183 23:06:49.753862 [Gating] SW calibration Done
3184 23:06:49.753996 ==
3185 23:06:49.757340 Dram Type= 6, Freq= 0, CH_1, rank 0
3186 23:06:49.760379 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3187 23:06:49.763579 ==
3188 23:06:49.763716 RX Vref Scan: 0
3189 23:06:49.763786
3190 23:06:49.767089 RX Vref 0 -> 0, step: 1
3191 23:06:49.767209
3192 23:06:49.770395 RX Delay -40 -> 252, step: 8
3193 23:06:49.773781 iDelay=200, Bit 0, Center 123 (48 ~ 199) 152
3194 23:06:49.777318 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3195 23:06:49.780482 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3196 23:06:49.783639 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3197 23:06:49.790512 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3198 23:06:49.794055 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3199 23:06:49.796876 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3200 23:06:49.800355 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3201 23:06:49.803634 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3202 23:06:49.810635 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3203 23:06:49.813731 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3204 23:06:49.816736 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3205 23:06:49.820320 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3206 23:06:49.823560 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3207 23:06:49.830407 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3208 23:06:49.833508 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3209 23:06:49.833673 ==
3210 23:06:49.836684 Dram Type= 6, Freq= 0, CH_1, rank 0
3211 23:06:49.840001 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3212 23:06:49.840142 ==
3213 23:06:49.843358 DQS Delay:
3214 23:06:49.843496 DQS0 = 0, DQS1 = 0
3215 23:06:49.843563 DQM Delay:
3216 23:06:49.846854 DQM0 = 116, DQM1 = 112
3217 23:06:49.846994 DQ Delay:
3218 23:06:49.850401 DQ0 =123, DQ1 =111, DQ2 =107, DQ3 =115
3219 23:06:49.853516 DQ4 =111, DQ5 =127, DQ6 =123, DQ7 =111
3220 23:06:49.856576 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
3221 23:06:49.863335 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =119
3222 23:06:49.863528
3223 23:06:49.863597
3224 23:06:49.863657 ==
3225 23:06:49.867041 Dram Type= 6, Freq= 0, CH_1, rank 0
3226 23:06:49.869719 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3227 23:06:49.869876 ==
3228 23:06:49.869979
3229 23:06:49.870071
3230 23:06:49.873196 TX Vref Scan disable
3231 23:06:49.873347 == TX Byte 0 ==
3232 23:06:49.880025 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3233 23:06:49.882963 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3234 23:06:49.883135 == TX Byte 1 ==
3235 23:06:49.890134 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3236 23:06:49.892856 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3237 23:06:49.893035 ==
3238 23:06:49.896219 Dram Type= 6, Freq= 0, CH_1, rank 0
3239 23:06:49.899846 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3240 23:06:49.900028 ==
3241 23:06:49.912387 TX Vref=22, minBit 3, minWin=24, winSum=410
3242 23:06:49.915622 TX Vref=24, minBit 2, minWin=25, winSum=420
3243 23:06:49.919103 TX Vref=26, minBit 9, minWin=24, winSum=421
3244 23:06:49.922288 TX Vref=28, minBit 9, minWin=25, winSum=423
3245 23:06:49.926005 TX Vref=30, minBit 9, minWin=25, winSum=428
3246 23:06:49.932534 TX Vref=32, minBit 9, minWin=25, winSum=426
3247 23:06:49.935673 [TxChooseVref] Worse bit 9, Min win 25, Win sum 428, Final Vref 30
3248 23:06:49.935833
3249 23:06:49.939064 Final TX Range 1 Vref 30
3250 23:06:49.939212
3251 23:06:49.939316 ==
3252 23:06:49.942507 Dram Type= 6, Freq= 0, CH_1, rank 0
3253 23:06:49.945810 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3254 23:06:49.945969 ==
3255 23:06:49.949083
3256 23:06:49.949241
3257 23:06:49.949340 TX Vref Scan disable
3258 23:06:49.952148 == TX Byte 0 ==
3259 23:06:49.955626 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3260 23:06:49.958854 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3261 23:06:49.962014 == TX Byte 1 ==
3262 23:06:49.965243 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3263 23:06:49.972015 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3264 23:06:49.972210
3265 23:06:49.972314 [DATLAT]
3266 23:06:49.972404 Freq=1200, CH1 RK0
3267 23:06:49.972494
3268 23:06:49.975165 DATLAT Default: 0xd
3269 23:06:49.975295 0, 0xFFFF, sum = 0
3270 23:06:49.978830 1, 0xFFFF, sum = 0
3271 23:06:49.982117 2, 0xFFFF, sum = 0
3272 23:06:49.982295 3, 0xFFFF, sum = 0
3273 23:06:49.985027 4, 0xFFFF, sum = 0
3274 23:06:49.985193 5, 0xFFFF, sum = 0
3275 23:06:49.988471 6, 0xFFFF, sum = 0
3276 23:06:49.988624 7, 0xFFFF, sum = 0
3277 23:06:49.991616 8, 0xFFFF, sum = 0
3278 23:06:49.991772 9, 0xFFFF, sum = 0
3279 23:06:49.995573 10, 0xFFFF, sum = 0
3280 23:06:49.995743 11, 0xFFFF, sum = 0
3281 23:06:49.998425 12, 0x0, sum = 1
3282 23:06:49.998560 13, 0x0, sum = 2
3283 23:06:50.001537 14, 0x0, sum = 3
3284 23:06:50.001681 15, 0x0, sum = 4
3285 23:06:50.004969 best_step = 13
3286 23:06:50.005119
3287 23:06:50.005220 ==
3288 23:06:50.008167 Dram Type= 6, Freq= 0, CH_1, rank 0
3289 23:06:50.011499 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3290 23:06:50.011657 ==
3291 23:06:50.014783 RX Vref Scan: 1
3292 23:06:50.014926
3293 23:06:50.015027 Set Vref Range= 32 -> 127
3294 23:06:50.015119
3295 23:06:50.018420 RX Vref 32 -> 127, step: 1
3296 23:06:50.018572
3297 23:06:50.021217 RX Delay -13 -> 252, step: 4
3298 23:06:50.021351
3299 23:06:50.024949 Set Vref, RX VrefLevel [Byte0]: 32
3300 23:06:50.027935 [Byte1]: 32
3301 23:06:50.028081
3302 23:06:50.031159 Set Vref, RX VrefLevel [Byte0]: 33
3303 23:06:50.034716 [Byte1]: 33
3304 23:06:50.038296
3305 23:06:50.038458 Set Vref, RX VrefLevel [Byte0]: 34
3306 23:06:50.041593 [Byte1]: 34
3307 23:06:50.046661
3308 23:06:50.046831 Set Vref, RX VrefLevel [Byte0]: 35
3309 23:06:50.050058 [Byte1]: 35
3310 23:06:50.054469
3311 23:06:50.054638 Set Vref, RX VrefLevel [Byte0]: 36
3312 23:06:50.057690 [Byte1]: 36
3313 23:06:50.062180
3314 23:06:50.062359 Set Vref, RX VrefLevel [Byte0]: 37
3315 23:06:50.065457 [Byte1]: 37
3316 23:06:50.069928
3317 23:06:50.070098 Set Vref, RX VrefLevel [Byte0]: 38
3318 23:06:50.073341 [Byte1]: 38
3319 23:06:50.078242
3320 23:06:50.078423 Set Vref, RX VrefLevel [Byte0]: 39
3321 23:06:50.081231 [Byte1]: 39
3322 23:06:50.086156
3323 23:06:50.086346 Set Vref, RX VrefLevel [Byte0]: 40
3324 23:06:50.089157 [Byte1]: 40
3325 23:06:50.093598
3326 23:06:50.093778 Set Vref, RX VrefLevel [Byte0]: 41
3327 23:06:50.097130 [Byte1]: 41
3328 23:06:50.101943
3329 23:06:50.102105 Set Vref, RX VrefLevel [Byte0]: 42
3330 23:06:50.104984 [Byte1]: 42
3331 23:06:50.109423
3332 23:06:50.109588 Set Vref, RX VrefLevel [Byte0]: 43
3333 23:06:50.112791 [Byte1]: 43
3334 23:06:50.117751
3335 23:06:50.117921 Set Vref, RX VrefLevel [Byte0]: 44
3336 23:06:50.120866 [Byte1]: 44
3337 23:06:50.125038
3338 23:06:50.125203 Set Vref, RX VrefLevel [Byte0]: 45
3339 23:06:50.128535 [Byte1]: 45
3340 23:06:50.133104
3341 23:06:50.133286 Set Vref, RX VrefLevel [Byte0]: 46
3342 23:06:50.136615 [Byte1]: 46
3343 23:06:50.141405
3344 23:06:50.141569 Set Vref, RX VrefLevel [Byte0]: 47
3345 23:06:50.144709 [Byte1]: 47
3346 23:06:50.148811
3347 23:06:50.148967 Set Vref, RX VrefLevel [Byte0]: 48
3348 23:06:50.152114 [Byte1]: 48
3349 23:06:50.156629
3350 23:06:50.156808 Set Vref, RX VrefLevel [Byte0]: 49
3351 23:06:50.159907 [Byte1]: 49
3352 23:06:50.164861
3353 23:06:50.165055 Set Vref, RX VrefLevel [Byte0]: 50
3354 23:06:50.167735 [Byte1]: 50
3355 23:06:50.172323
3356 23:06:50.172469 Set Vref, RX VrefLevel [Byte0]: 51
3357 23:06:50.176002 [Byte1]: 51
3358 23:06:50.180232
3359 23:06:50.180409 Set Vref, RX VrefLevel [Byte0]: 52
3360 23:06:50.183577 [Byte1]: 52
3361 23:06:50.188261
3362 23:06:50.188407 Set Vref, RX VrefLevel [Byte0]: 53
3363 23:06:50.191412 [Byte1]: 53
3364 23:06:50.196095
3365 23:06:50.196242 Set Vref, RX VrefLevel [Byte0]: 54
3366 23:06:50.199554 [Byte1]: 54
3367 23:06:50.204105
3368 23:06:50.204246 Set Vref, RX VrefLevel [Byte0]: 55
3369 23:06:50.207430 [Byte1]: 55
3370 23:06:50.212022
3371 23:06:50.212169 Set Vref, RX VrefLevel [Byte0]: 56
3372 23:06:50.215302 [Byte1]: 56
3373 23:06:50.219976
3374 23:06:50.220111 Set Vref, RX VrefLevel [Byte0]: 57
3375 23:06:50.223214 [Byte1]: 57
3376 23:06:50.227590
3377 23:06:50.227733 Set Vref, RX VrefLevel [Byte0]: 58
3378 23:06:50.231281 [Byte1]: 58
3379 23:06:50.235627
3380 23:06:50.235763 Set Vref, RX VrefLevel [Byte0]: 59
3381 23:06:50.238688 [Byte1]: 59
3382 23:06:50.243546
3383 23:06:50.243727 Set Vref, RX VrefLevel [Byte0]: 60
3384 23:06:50.246805 [Byte1]: 60
3385 23:06:50.251298
3386 23:06:50.251516 Set Vref, RX VrefLevel [Byte0]: 61
3387 23:06:50.254529 [Byte1]: 61
3388 23:06:50.259291
3389 23:06:50.259498 Set Vref, RX VrefLevel [Byte0]: 62
3390 23:06:50.262239 [Byte1]: 62
3391 23:06:50.267266
3392 23:06:50.267476 Set Vref, RX VrefLevel [Byte0]: 63
3393 23:06:50.270078 [Byte1]: 63
3394 23:06:50.274736
3395 23:06:50.274904 Set Vref, RX VrefLevel [Byte0]: 64
3396 23:06:50.278172 [Byte1]: 64
3397 23:06:50.282881
3398 23:06:50.283076 Final RX Vref Byte 0 = 51 to rank0
3399 23:06:50.286539 Final RX Vref Byte 1 = 51 to rank0
3400 23:06:50.289720 Final RX Vref Byte 0 = 51 to rank1
3401 23:06:50.292813 Final RX Vref Byte 1 = 51 to rank1==
3402 23:06:50.296437 Dram Type= 6, Freq= 0, CH_1, rank 0
3403 23:06:50.302633 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3404 23:06:50.302774 ==
3405 23:06:50.302841 DQS Delay:
3406 23:06:50.302902 DQS0 = 0, DQS1 = 0
3407 23:06:50.306463 DQM Delay:
3408 23:06:50.306623 DQM0 = 115, DQM1 = 112
3409 23:06:50.309478 DQ Delay:
3410 23:06:50.312841 DQ0 =120, DQ1 =112, DQ2 =106, DQ3 =114
3411 23:06:50.316411 DQ4 =110, DQ5 =122, DQ6 =126, DQ7 =110
3412 23:06:50.319424 DQ8 =98, DQ9 =104, DQ10 =114, DQ11 =106
3413 23:06:50.322771 DQ12 =120, DQ13 =120, DQ14 =118, DQ15 =120
3414 23:06:50.322937
3415 23:06:50.323042
3416 23:06:50.332952 [DQSOSCAuto] RK0, (LSB)MR18= 0xf703, (MSB)MR19= 0x304, tDQSOscB0 = 408 ps tDQSOscB1 = 413 ps
3417 23:06:50.333111 CH1 RK0: MR19=304, MR18=F703
3418 23:06:50.339727 CH1_RK0: MR19=0x304, MR18=0xF703, DQSOSC=408, MR23=63, INC=39, DEC=26
3419 23:06:50.339888
3420 23:06:50.342732 ----->DramcWriteLeveling(PI) begin...
3421 23:06:50.342845 ==
3422 23:06:50.346197 Dram Type= 6, Freq= 0, CH_1, rank 1
3423 23:06:50.349402 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3424 23:06:50.352684 ==
3425 23:06:50.356240 Write leveling (Byte 0): 23 => 23
3426 23:06:50.356385 Write leveling (Byte 1): 26 => 26
3427 23:06:50.359412 DramcWriteLeveling(PI) end<-----
3428 23:06:50.359530
3429 23:06:50.359601 ==
3430 23:06:50.362628 Dram Type= 6, Freq= 0, CH_1, rank 1
3431 23:06:50.369695 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3432 23:06:50.369849 ==
3433 23:06:50.372629 [Gating] SW mode calibration
3434 23:06:50.379267 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3435 23:06:50.382735 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3436 23:06:50.389483 0 15 0 | B1->B0 | 3232 3434 | 1 1 | (0 0) (1 1)
3437 23:06:50.392437 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3438 23:06:50.396097 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3439 23:06:50.402794 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3440 23:06:50.405915 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3441 23:06:50.408916 0 15 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
3442 23:06:50.412509 0 15 24 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
3443 23:06:50.419285 0 15 28 | B1->B0 | 2d2d 2323 | 0 0 | (1 0) (0 0)
3444 23:06:50.423269 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3445 23:06:50.425645 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3446 23:06:50.432627 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3447 23:06:50.435586 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3448 23:06:50.439109 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3449 23:06:50.445871 1 0 20 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
3450 23:06:50.448949 1 0 24 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
3451 23:06:50.452962 1 0 28 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
3452 23:06:50.458794 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3453 23:06:50.462296 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3454 23:06:50.465253 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3455 23:06:50.472070 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3456 23:06:50.475277 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3457 23:06:50.478722 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3458 23:06:50.485169 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3459 23:06:50.488739 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3460 23:06:50.491861 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3461 23:06:50.498259 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3462 23:06:50.501779 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3463 23:06:50.505308 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3464 23:06:50.511719 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3465 23:06:50.515058 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3466 23:06:50.518538 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3467 23:06:50.525198 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3468 23:06:50.528368 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3469 23:06:50.531333 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3470 23:06:50.537859 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3471 23:06:50.541931 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3472 23:06:50.544472 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3473 23:06:50.551166 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3474 23:06:50.554844 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3475 23:06:50.557631 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3476 23:06:50.561268 Total UI for P1: 0, mck2ui 16
3477 23:06:50.564534 best dqsien dly found for B0: ( 1, 3, 24)
3478 23:06:50.570636 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3479 23:06:50.574127 Total UI for P1: 0, mck2ui 16
3480 23:06:50.577264 best dqsien dly found for B1: ( 1, 3, 26)
3481 23:06:50.580502 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3482 23:06:50.584358 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3483 23:06:50.584496
3484 23:06:50.587677 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3485 23:06:50.590386 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3486 23:06:50.593837 [Gating] SW calibration Done
3487 23:06:50.593972 ==
3488 23:06:50.597217 Dram Type= 6, Freq= 0, CH_1, rank 1
3489 23:06:50.600262 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3490 23:06:50.600386 ==
3491 23:06:50.603859 RX Vref Scan: 0
3492 23:06:50.604043
3493 23:06:50.607160 RX Vref 0 -> 0, step: 1
3494 23:06:50.607278
3495 23:06:50.607346 RX Delay -40 -> 252, step: 8
3496 23:06:50.613703 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3497 23:06:50.617422 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3498 23:06:50.620441 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3499 23:06:50.623263 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3500 23:06:50.626712 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3501 23:06:50.633681 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3502 23:06:50.636885 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
3503 23:06:50.640220 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3504 23:06:50.643754 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3505 23:06:50.646943 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3506 23:06:50.653620 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3507 23:06:50.656428 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3508 23:06:50.660308 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3509 23:06:50.663163 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3510 23:06:50.669880 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3511 23:06:50.672654 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3512 23:06:50.672788 ==
3513 23:06:50.676392 Dram Type= 6, Freq= 0, CH_1, rank 1
3514 23:06:50.679537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3515 23:06:50.679672 ==
3516 23:06:50.682841 DQS Delay:
3517 23:06:50.683041 DQS0 = 0, DQS1 = 0
3518 23:06:50.683110 DQM Delay:
3519 23:06:50.686460 DQM0 = 114, DQM1 = 111
3520 23:06:50.686610 DQ Delay:
3521 23:06:50.689585 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =111
3522 23:06:50.693256 DQ4 =115, DQ5 =123, DQ6 =119, DQ7 =115
3523 23:06:50.696166 DQ8 =99, DQ9 =99, DQ10 =111, DQ11 =107
3524 23:06:50.702446 DQ12 =123, DQ13 =119, DQ14 =115, DQ15 =119
3525 23:06:50.702588
3526 23:06:50.702656
3527 23:06:50.702716 ==
3528 23:06:50.705934 Dram Type= 6, Freq= 0, CH_1, rank 1
3529 23:06:50.709196 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3530 23:06:50.709329 ==
3531 23:06:50.709398
3532 23:06:50.709466
3533 23:06:50.712559 TX Vref Scan disable
3534 23:06:50.712678 == TX Byte 0 ==
3535 23:06:50.719177 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
3536 23:06:50.722396 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
3537 23:06:50.722526 == TX Byte 1 ==
3538 23:06:50.728883 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3539 23:06:50.732251 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3540 23:06:50.732385 ==
3541 23:06:50.735619 Dram Type= 6, Freq= 0, CH_1, rank 1
3542 23:06:50.738722 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3543 23:06:50.738857 ==
3544 23:06:50.751794 TX Vref=22, minBit 9, minWin=23, winSum=414
3545 23:06:50.755404 TX Vref=24, minBit 9, minWin=24, winSum=422
3546 23:06:50.758731 TX Vref=26, minBit 9, minWin=25, winSum=422
3547 23:06:50.762067 TX Vref=28, minBit 9, minWin=25, winSum=428
3548 23:06:50.765194 TX Vref=30, minBit 9, minWin=25, winSum=431
3549 23:06:50.771942 TX Vref=32, minBit 9, minWin=25, winSum=429
3550 23:06:50.775022 [TxChooseVref] Worse bit 9, Min win 25, Win sum 431, Final Vref 30
3551 23:06:50.775162
3552 23:06:50.778591 Final TX Range 1 Vref 30
3553 23:06:50.778733
3554 23:06:50.778805 ==
3555 23:06:50.782718 Dram Type= 6, Freq= 0, CH_1, rank 1
3556 23:06:50.784803 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3557 23:06:50.787868 ==
3558 23:06:50.787994
3559 23:06:50.788060
3560 23:06:50.788121 TX Vref Scan disable
3561 23:06:50.791572 == TX Byte 0 ==
3562 23:06:50.795054 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
3563 23:06:50.801576 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
3564 23:06:50.801733 == TX Byte 1 ==
3565 23:06:50.804762 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3566 23:06:50.811181 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3567 23:06:50.811334
3568 23:06:50.811448 [DATLAT]
3569 23:06:50.811509 Freq=1200, CH1 RK1
3570 23:06:50.811567
3571 23:06:50.814753 DATLAT Default: 0xd
3572 23:06:50.817823 0, 0xFFFF, sum = 0
3573 23:06:50.817951 1, 0xFFFF, sum = 0
3574 23:06:50.821387 2, 0xFFFF, sum = 0
3575 23:06:50.821522 3, 0xFFFF, sum = 0
3576 23:06:50.824696 4, 0xFFFF, sum = 0
3577 23:06:50.824815 5, 0xFFFF, sum = 0
3578 23:06:50.827755 6, 0xFFFF, sum = 0
3579 23:06:50.827868 7, 0xFFFF, sum = 0
3580 23:06:50.831175 8, 0xFFFF, sum = 0
3581 23:06:50.831289 9, 0xFFFF, sum = 0
3582 23:06:50.834770 10, 0xFFFF, sum = 0
3583 23:06:50.834893 11, 0xFFFF, sum = 0
3584 23:06:50.837574 12, 0x0, sum = 1
3585 23:06:50.837680 13, 0x0, sum = 2
3586 23:06:50.841341 14, 0x0, sum = 3
3587 23:06:50.841470 15, 0x0, sum = 4
3588 23:06:50.844130 best_step = 13
3589 23:06:50.844247
3590 23:06:50.844328 ==
3591 23:06:50.847825 Dram Type= 6, Freq= 0, CH_1, rank 1
3592 23:06:50.851131 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3593 23:06:50.851258 ==
3594 23:06:50.854070 RX Vref Scan: 0
3595 23:06:50.854195
3596 23:06:50.854262 RX Vref 0 -> 0, step: 1
3597 23:06:50.854322
3598 23:06:50.857962 RX Delay -13 -> 252, step: 4
3599 23:06:50.864067 iDelay=195, Bit 0, Center 116 (47 ~ 186) 140
3600 23:06:50.867326 iDelay=195, Bit 1, Center 112 (43 ~ 182) 140
3601 23:06:50.870749 iDelay=195, Bit 2, Center 106 (39 ~ 174) 136
3602 23:06:50.874144 iDelay=195, Bit 3, Center 112 (43 ~ 182) 140
3603 23:06:50.877643 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3604 23:06:50.883997 iDelay=195, Bit 5, Center 122 (51 ~ 194) 144
3605 23:06:50.887157 iDelay=195, Bit 6, Center 122 (55 ~ 190) 136
3606 23:06:50.890548 iDelay=195, Bit 7, Center 112 (43 ~ 182) 140
3607 23:06:50.893464 iDelay=195, Bit 8, Center 100 (39 ~ 162) 124
3608 23:06:50.900547 iDelay=195, Bit 9, Center 104 (43 ~ 166) 124
3609 23:06:50.903614 iDelay=195, Bit 10, Center 114 (51 ~ 178) 128
3610 23:06:50.906777 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3611 23:06:50.909856 iDelay=195, Bit 12, Center 120 (59 ~ 182) 124
3612 23:06:50.913419 iDelay=195, Bit 13, Center 120 (59 ~ 182) 124
3613 23:06:50.920412 iDelay=195, Bit 14, Center 118 (59 ~ 178) 120
3614 23:06:50.923132 iDelay=195, Bit 15, Center 122 (59 ~ 186) 128
3615 23:06:50.923261 ==
3616 23:06:50.926220 Dram Type= 6, Freq= 0, CH_1, rank 1
3617 23:06:50.929583 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3618 23:06:50.929717 ==
3619 23:06:50.933556 DQS Delay:
3620 23:06:50.933685 DQS0 = 0, DQS1 = 0
3621 23:06:50.933754 DQM Delay:
3622 23:06:50.936385 DQM0 = 114, DQM1 = 113
3623 23:06:50.936502 DQ Delay:
3624 23:06:50.939730 DQ0 =116, DQ1 =112, DQ2 =106, DQ3 =112
3625 23:06:50.943273 DQ4 =112, DQ5 =122, DQ6 =122, DQ7 =112
3626 23:06:50.949315 DQ8 =100, DQ9 =104, DQ10 =114, DQ11 =106
3627 23:06:50.952677 DQ12 =120, DQ13 =120, DQ14 =118, DQ15 =122
3628 23:06:50.952803
3629 23:06:50.952868
3630 23:06:50.959313 [DQSOSCAuto] RK1, (LSB)MR18= 0xf809, (MSB)MR19= 0x304, tDQSOscB0 = 406 ps tDQSOscB1 = 413 ps
3631 23:06:50.962848 CH1 RK1: MR19=304, MR18=F809
3632 23:06:50.969022 CH1_RK1: MR19=0x304, MR18=0xF809, DQSOSC=406, MR23=63, INC=39, DEC=26
3633 23:06:50.972244 [RxdqsGatingPostProcess] freq 1200
3634 23:06:50.978995 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3635 23:06:50.982218 best DQS0 dly(2T, 0.5T) = (0, 11)
3636 23:06:50.982352 best DQS1 dly(2T, 0.5T) = (0, 11)
3637 23:06:50.985393 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3638 23:06:50.989013 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3639 23:06:50.991908 best DQS0 dly(2T, 0.5T) = (0, 11)
3640 23:06:50.995293 best DQS1 dly(2T, 0.5T) = (0, 11)
3641 23:06:50.998686 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3642 23:06:51.002337 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3643 23:06:51.005442 Pre-setting of DQS Precalculation
3644 23:06:51.011890 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3645 23:06:51.018449 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3646 23:06:51.025580 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3647 23:06:51.025730
3648 23:06:51.025800
3649 23:06:51.028208 [Calibration Summary] 2400 Mbps
3650 23:06:51.028317 CH 0, Rank 0
3651 23:06:51.032006 SW Impedance : PASS
3652 23:06:51.034997 DUTY Scan : NO K
3653 23:06:51.035148 ZQ Calibration : PASS
3654 23:06:51.038360 Jitter Meter : NO K
3655 23:06:51.041659 CBT Training : PASS
3656 23:06:51.041810 Write leveling : PASS
3657 23:06:51.045039 RX DQS gating : PASS
3658 23:06:51.048102 RX DQ/DQS(RDDQC) : PASS
3659 23:06:51.048258 TX DQ/DQS : PASS
3660 23:06:51.051725 RX DATLAT : PASS
3661 23:06:51.054614 RX DQ/DQS(Engine): PASS
3662 23:06:51.054765 TX OE : NO K
3663 23:06:51.057838 All Pass.
3664 23:06:51.057982
3665 23:06:51.058082 CH 0, Rank 1
3666 23:06:51.061541 SW Impedance : PASS
3667 23:06:51.061695 DUTY Scan : NO K
3668 23:06:51.064728 ZQ Calibration : PASS
3669 23:06:51.068047 Jitter Meter : NO K
3670 23:06:51.068197 CBT Training : PASS
3671 23:06:51.071031 Write leveling : PASS
3672 23:06:51.074745 RX DQS gating : PASS
3673 23:06:51.074913 RX DQ/DQS(RDDQC) : PASS
3674 23:06:51.077723 TX DQ/DQS : PASS
3675 23:06:51.081245 RX DATLAT : PASS
3676 23:06:51.081421 RX DQ/DQS(Engine): PASS
3677 23:06:51.084606 TX OE : NO K
3678 23:06:51.084753 All Pass.
3679 23:06:51.084853
3680 23:06:51.087670 CH 1, Rank 0
3681 23:06:51.087815 SW Impedance : PASS
3682 23:06:51.091457 DUTY Scan : NO K
3683 23:06:51.094170 ZQ Calibration : PASS
3684 23:06:51.094341 Jitter Meter : NO K
3685 23:06:51.097666 CBT Training : PASS
3686 23:06:51.097828 Write leveling : PASS
3687 23:06:51.101226 RX DQS gating : PASS
3688 23:06:51.104395 RX DQ/DQS(RDDQC) : PASS
3689 23:06:51.104545 TX DQ/DQS : PASS
3690 23:06:51.107248 RX DATLAT : PASS
3691 23:06:51.111490 RX DQ/DQS(Engine): PASS
3692 23:06:51.111666 TX OE : NO K
3693 23:06:51.114072 All Pass.
3694 23:06:51.114221
3695 23:06:51.114350 CH 1, Rank 1
3696 23:06:51.117504 SW Impedance : PASS
3697 23:06:51.117648 DUTY Scan : NO K
3698 23:06:51.120689 ZQ Calibration : PASS
3699 23:06:51.123692 Jitter Meter : NO K
3700 23:06:51.123842 CBT Training : PASS
3701 23:06:51.127314 Write leveling : PASS
3702 23:06:51.130501 RX DQS gating : PASS
3703 23:06:51.130659 RX DQ/DQS(RDDQC) : PASS
3704 23:06:51.134067 TX DQ/DQS : PASS
3705 23:06:51.137252 RX DATLAT : PASS
3706 23:06:51.137418 RX DQ/DQS(Engine): PASS
3707 23:06:51.140574 TX OE : NO K
3708 23:06:51.140739 All Pass.
3709 23:06:51.140883
3710 23:06:51.143640 DramC Write-DBI off
3711 23:06:51.147250 PER_BANK_REFRESH: Hybrid Mode
3712 23:06:51.147451 TX_TRACKING: ON
3713 23:06:51.156590 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3714 23:06:51.159813 [FAST_K] Save calibration result to emmc
3715 23:06:51.163085 dramc_set_vcore_voltage set vcore to 650000
3716 23:06:51.166750 Read voltage for 600, 5
3717 23:06:51.166913 Vio18 = 0
3718 23:06:51.167017 Vcore = 650000
3719 23:06:51.169629 Vdram = 0
3720 23:06:51.169762 Vddq = 0
3721 23:06:51.169861 Vmddr = 0
3722 23:06:51.176851 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3723 23:06:51.179758 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3724 23:06:51.182882 MEM_TYPE=3, freq_sel=19
3725 23:06:51.186529 sv_algorithm_assistance_LP4_1600
3726 23:06:51.189534 ============ PULL DRAM RESETB DOWN ============
3727 23:06:51.196480 ========== PULL DRAM RESETB DOWN end =========
3728 23:06:51.199374 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3729 23:06:51.203236 ===================================
3730 23:06:51.206134 LPDDR4 DRAM CONFIGURATION
3731 23:06:51.209304 ===================================
3732 23:06:51.209460 EX_ROW_EN[0] = 0x0
3733 23:06:51.212798 EX_ROW_EN[1] = 0x0
3734 23:06:51.212920 LP4Y_EN = 0x0
3735 23:06:51.216027 WORK_FSP = 0x0
3736 23:06:51.216138 WL = 0x2
3737 23:06:51.219128 RL = 0x2
3738 23:06:51.219268 BL = 0x2
3739 23:06:51.222456 RPST = 0x0
3740 23:06:51.225617 RD_PRE = 0x0
3741 23:06:51.225737 WR_PRE = 0x1
3742 23:06:51.229017 WR_PST = 0x0
3743 23:06:51.229136 DBI_WR = 0x0
3744 23:06:51.232518 DBI_RD = 0x0
3745 23:06:51.232636 OTF = 0x1
3746 23:06:51.236087 ===================================
3747 23:06:51.239163 ===================================
3748 23:06:51.242449 ANA top config
3749 23:06:51.245732 ===================================
3750 23:06:51.245865 DLL_ASYNC_EN = 0
3751 23:06:51.249092 ALL_SLAVE_EN = 1
3752 23:06:51.252037 NEW_RANK_MODE = 1
3753 23:06:51.255786 DLL_IDLE_MODE = 1
3754 23:06:51.258707 LP45_APHY_COMB_EN = 1
3755 23:06:51.258830 TX_ODT_DIS = 1
3756 23:06:51.262042 NEW_8X_MODE = 1
3757 23:06:51.265263 ===================================
3758 23:06:51.268713 ===================================
3759 23:06:51.271884 data_rate = 1200
3760 23:06:51.275432 CKR = 1
3761 23:06:51.278736 DQ_P2S_RATIO = 8
3762 23:06:51.281499 ===================================
3763 23:06:51.285206 CA_P2S_RATIO = 8
3764 23:06:51.285352 DQ_CA_OPEN = 0
3765 23:06:51.288622 DQ_SEMI_OPEN = 0
3766 23:06:51.291707 CA_SEMI_OPEN = 0
3767 23:06:51.294822 CA_FULL_RATE = 0
3768 23:06:51.298521 DQ_CKDIV4_EN = 1
3769 23:06:51.301490 CA_CKDIV4_EN = 1
3770 23:06:51.301622 CA_PREDIV_EN = 0
3771 23:06:51.304775 PH8_DLY = 0
3772 23:06:51.308339 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3773 23:06:51.311692 DQ_AAMCK_DIV = 4
3774 23:06:51.314973 CA_AAMCK_DIV = 4
3775 23:06:51.317712 CA_ADMCK_DIV = 4
3776 23:06:51.317845 DQ_TRACK_CA_EN = 0
3777 23:06:51.321143 CA_PICK = 600
3778 23:06:51.324748 CA_MCKIO = 600
3779 23:06:51.327658 MCKIO_SEMI = 0
3780 23:06:51.330872 PLL_FREQ = 2288
3781 23:06:51.334277 DQ_UI_PI_RATIO = 32
3782 23:06:51.337473 CA_UI_PI_RATIO = 0
3783 23:06:51.341335 ===================================
3784 23:06:51.344477 ===================================
3785 23:06:51.344623 memory_type:LPDDR4
3786 23:06:51.348283 GP_NUM : 10
3787 23:06:51.350891 SRAM_EN : 1
3788 23:06:51.351011 MD32_EN : 0
3789 23:06:51.354611 ===================================
3790 23:06:51.357580 [ANA_INIT] >>>>>>>>>>>>>>
3791 23:06:51.360950 <<<<<< [CONFIGURE PHASE]: ANA_TX
3792 23:06:51.364505 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3793 23:06:51.367280 ===================================
3794 23:06:51.370517 data_rate = 1200,PCW = 0X5800
3795 23:06:51.373846 ===================================
3796 23:06:51.377343 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3797 23:06:51.380613 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3798 23:06:51.386842 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3799 23:06:51.390939 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3800 23:06:51.397096 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3801 23:06:51.400293 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3802 23:06:51.400430 [ANA_INIT] flow start
3803 23:06:51.403469 [ANA_INIT] PLL >>>>>>>>
3804 23:06:51.407040 [ANA_INIT] PLL <<<<<<<<
3805 23:06:51.407181 [ANA_INIT] MIDPI >>>>>>>>
3806 23:06:51.410224 [ANA_INIT] MIDPI <<<<<<<<
3807 23:06:51.413202 [ANA_INIT] DLL >>>>>>>>
3808 23:06:51.413331 [ANA_INIT] flow end
3809 23:06:51.420408 ============ LP4 DIFF to SE enter ============
3810 23:06:51.423292 ============ LP4 DIFF to SE exit ============
3811 23:06:51.426419 [ANA_INIT] <<<<<<<<<<<<<
3812 23:06:51.429645 [Flow] Enable top DCM control >>>>>
3813 23:06:51.433310 [Flow] Enable top DCM control <<<<<
3814 23:06:51.433450 Enable DLL master slave shuffle
3815 23:06:51.440133 ==============================================================
3816 23:06:51.443194 Gating Mode config
3817 23:06:51.445979 ==============================================================
3818 23:06:51.449698 Config description:
3819 23:06:51.459606 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3820 23:06:51.466325 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3821 23:06:51.469123 SELPH_MODE 0: By rank 1: By Phase
3822 23:06:51.476236 ==============================================================
3823 23:06:51.479204 GAT_TRACK_EN = 1
3824 23:06:51.482738 RX_GATING_MODE = 2
3825 23:06:51.485549 RX_GATING_TRACK_MODE = 2
3826 23:06:51.489256 SELPH_MODE = 1
3827 23:06:51.492206 PICG_EARLY_EN = 1
3828 23:06:51.492378 VALID_LAT_VALUE = 1
3829 23:06:51.499154 ==============================================================
3830 23:06:51.502313 Enter into Gating configuration >>>>
3831 23:06:51.505320 Exit from Gating configuration <<<<
3832 23:06:51.509056 Enter into DVFS_PRE_config >>>>>
3833 23:06:51.518481 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3834 23:06:51.522187 Exit from DVFS_PRE_config <<<<<
3835 23:06:51.524842 Enter into PICG configuration >>>>
3836 23:06:51.528755 Exit from PICG configuration <<<<
3837 23:06:51.531949 [RX_INPUT] configuration >>>>>
3838 23:06:51.535072 [RX_INPUT] configuration <<<<<
3839 23:06:51.541284 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3840 23:06:51.544940 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3841 23:06:51.551615 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3842 23:06:51.557753 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3843 23:06:51.564407 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3844 23:06:51.571041 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3845 23:06:51.574298 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3846 23:06:51.577741 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3847 23:06:51.581147 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3848 23:06:51.587525 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3849 23:06:51.591182 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3850 23:06:51.594467 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3851 23:06:51.598176 ===================================
3852 23:06:51.600750 LPDDR4 DRAM CONFIGURATION
3853 23:06:51.604088 ===================================
3854 23:06:51.607273 EX_ROW_EN[0] = 0x0
3855 23:06:51.607438 EX_ROW_EN[1] = 0x0
3856 23:06:51.611235 LP4Y_EN = 0x0
3857 23:06:51.611396 WORK_FSP = 0x0
3858 23:06:51.614329 WL = 0x2
3859 23:06:51.614442 RL = 0x2
3860 23:06:51.617533 BL = 0x2
3861 23:06:51.617652 RPST = 0x0
3862 23:06:51.620547 RD_PRE = 0x0
3863 23:06:51.620657 WR_PRE = 0x1
3864 23:06:51.623689 WR_PST = 0x0
3865 23:06:51.623800 DBI_WR = 0x0
3866 23:06:51.627222 DBI_RD = 0x0
3867 23:06:51.630467 OTF = 0x1
3868 23:06:51.633654 ===================================
3869 23:06:51.637282 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3870 23:06:51.640265 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3871 23:06:51.643667 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3872 23:06:51.646652 ===================================
3873 23:06:51.650797 LPDDR4 DRAM CONFIGURATION
3874 23:06:51.653404 ===================================
3875 23:06:51.656854 EX_ROW_EN[0] = 0x10
3876 23:06:51.656986 EX_ROW_EN[1] = 0x0
3877 23:06:51.660204 LP4Y_EN = 0x0
3878 23:06:51.660366 WORK_FSP = 0x0
3879 23:06:51.663582 WL = 0x2
3880 23:06:51.663700 RL = 0x2
3881 23:06:51.666840 BL = 0x2
3882 23:06:51.666954 RPST = 0x0
3883 23:06:51.670309 RD_PRE = 0x0
3884 23:06:51.672919 WR_PRE = 0x1
3885 23:06:51.673037 WR_PST = 0x0
3886 23:06:51.676168 DBI_WR = 0x0
3887 23:06:51.676312 DBI_RD = 0x0
3888 23:06:51.679466 OTF = 0x1
3889 23:06:51.683067 ===================================
3890 23:06:51.686122 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3891 23:06:51.692082 nWR fixed to 30
3892 23:06:51.695165 [ModeRegInit_LP4] CH0 RK0
3893 23:06:51.695299 [ModeRegInit_LP4] CH0 RK1
3894 23:06:51.698512 [ModeRegInit_LP4] CH1 RK0
3895 23:06:51.701353 [ModeRegInit_LP4] CH1 RK1
3896 23:06:51.701502 match AC timing 17
3897 23:06:51.708075 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3898 23:06:51.711855 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3899 23:06:51.714758 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3900 23:06:51.721215 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3901 23:06:51.724549 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3902 23:06:51.724686 ==
3903 23:06:51.727919 Dram Type= 6, Freq= 0, CH_0, rank 0
3904 23:06:51.731076 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3905 23:06:51.731209 ==
3906 23:06:51.737696 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3907 23:06:51.744745 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3908 23:06:51.747759 [CA 0] Center 36 (6~67) winsize 62
3909 23:06:51.750866 [CA 1] Center 36 (5~67) winsize 63
3910 23:06:51.754362 [CA 2] Center 34 (4~65) winsize 62
3911 23:06:51.757577 [CA 3] Center 34 (4~65) winsize 62
3912 23:06:51.761337 [CA 4] Center 33 (3~64) winsize 62
3913 23:06:51.764259 [CA 5] Center 33 (3~64) winsize 62
3914 23:06:51.764384
3915 23:06:51.767329 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3916 23:06:51.767495
3917 23:06:51.770790 [CATrainingPosCal] consider 1 rank data
3918 23:06:51.774012 u2DelayCellTimex100 = 270/100 ps
3919 23:06:51.777562 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3920 23:06:51.780942 CA1 delay=36 (5~67),Diff = 3 PI (28 cell)
3921 23:06:51.783889 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3922 23:06:51.790907 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3923 23:06:51.793681 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3924 23:06:51.797001 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3925 23:06:51.797139
3926 23:06:51.800212 CA PerBit enable=1, Macro0, CA PI delay=33
3927 23:06:51.800356
3928 23:06:51.803958 [CBTSetCACLKResult] CA Dly = 33
3929 23:06:51.804087 CS Dly: 4 (0~35)
3930 23:06:51.804179 ==
3931 23:06:51.807342 Dram Type= 6, Freq= 0, CH_0, rank 1
3932 23:06:51.813950 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3933 23:06:51.814100 ==
3934 23:06:51.817040 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3935 23:06:51.823674 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3936 23:06:51.827291 [CA 0] Center 36 (6~67) winsize 62
3937 23:06:51.830371 [CA 1] Center 36 (6~67) winsize 62
3938 23:06:51.833734 [CA 2] Center 34 (4~65) winsize 62
3939 23:06:51.836815 [CA 3] Center 34 (4~65) winsize 62
3940 23:06:51.840372 [CA 4] Center 33 (3~64) winsize 62
3941 23:06:51.843412 [CA 5] Center 33 (3~64) winsize 62
3942 23:06:51.843557
3943 23:06:51.846482 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3944 23:06:51.846590
3945 23:06:51.850448 [CATrainingPosCal] consider 2 rank data
3946 23:06:51.853164 u2DelayCellTimex100 = 270/100 ps
3947 23:06:51.856611 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3948 23:06:51.863330 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3949 23:06:51.866715 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3950 23:06:51.869994 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3951 23:06:51.873378 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3952 23:06:51.876597 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3953 23:06:51.876728
3954 23:06:51.879611 CA PerBit enable=1, Macro0, CA PI delay=33
3955 23:06:51.879722
3956 23:06:51.882888 [CBTSetCACLKResult] CA Dly = 33
3957 23:06:51.886025 CS Dly: 5 (0~37)
3958 23:06:51.886160
3959 23:06:51.889704 ----->DramcWriteLeveling(PI) begin...
3960 23:06:51.889828 ==
3961 23:06:51.892886 Dram Type= 6, Freq= 0, CH_0, rank 0
3962 23:06:51.896332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3963 23:06:51.896462 ==
3964 23:06:51.899526 Write leveling (Byte 0): 35 => 35
3965 23:06:51.902403 Write leveling (Byte 1): 29 => 29
3966 23:06:51.905904 DramcWriteLeveling(PI) end<-----
3967 23:06:51.906032
3968 23:06:51.906102 ==
3969 23:06:51.909291 Dram Type= 6, Freq= 0, CH_0, rank 0
3970 23:06:51.912499 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3971 23:06:51.912666 ==
3972 23:06:51.915785 [Gating] SW mode calibration
3973 23:06:51.922508 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3974 23:06:51.929142 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3975 23:06:51.932251 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3976 23:06:51.935605 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3977 23:06:51.942449 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3978 23:06:51.945534 0 9 12 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
3979 23:06:51.949100 0 9 16 | B1->B0 | 2f2f 2a2a | 0 0 | (0 0) (0 0)
3980 23:06:51.955626 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3981 23:06:51.958569 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3982 23:06:51.961857 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3983 23:06:51.969051 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3984 23:06:51.972089 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3985 23:06:51.975393 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3986 23:06:51.981829 0 10 12 | B1->B0 | 2626 2f2f | 0 0 | (0 0) (0 0)
3987 23:06:51.985553 0 10 16 | B1->B0 | 3636 4545 | 0 0 | (0 0) (0 0)
3988 23:06:51.988801 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3989 23:06:51.995214 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3990 23:06:51.998505 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3991 23:06:52.001755 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3992 23:06:52.008374 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3993 23:06:52.011971 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3994 23:06:52.014666 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3995 23:06:52.021936 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3996 23:06:52.024657 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3997 23:06:52.028068 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3998 23:06:52.035713 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3999 23:06:52.037760 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4000 23:06:52.041350 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4001 23:06:52.047749 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4002 23:06:52.051257 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4003 23:06:52.055035 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4004 23:06:52.060961 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4005 23:06:52.064561 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4006 23:06:52.067660 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4007 23:06:52.074170 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4008 23:06:52.077398 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4009 23:06:52.081322 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4010 23:06:52.087513 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4011 23:06:52.090751 Total UI for P1: 0, mck2ui 16
4012 23:06:52.094311 best dqsien dly found for B0: ( 0, 13, 10)
4013 23:06:52.098178 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4014 23:06:52.100903 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4015 23:06:52.104064 Total UI for P1: 0, mck2ui 16
4016 23:06:52.107753 best dqsien dly found for B1: ( 0, 13, 16)
4017 23:06:52.110183 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4018 23:06:52.117301 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4019 23:06:52.117470
4020 23:06:52.120117 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4021 23:06:52.123757 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4022 23:06:52.126961 [Gating] SW calibration Done
4023 23:06:52.127085 ==
4024 23:06:52.130150 Dram Type= 6, Freq= 0, CH_0, rank 0
4025 23:06:52.133395 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4026 23:06:52.133519 ==
4027 23:06:52.136801 RX Vref Scan: 0
4028 23:06:52.136937
4029 23:06:52.137006 RX Vref 0 -> 0, step: 1
4030 23:06:52.137068
4031 23:06:52.140722 RX Delay -230 -> 252, step: 16
4032 23:06:52.143506 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4033 23:06:52.150143 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4034 23:06:52.153170 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4035 23:06:52.156767 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4036 23:06:52.159617 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4037 23:06:52.166416 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4038 23:06:52.169970 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4039 23:06:52.173678 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4040 23:06:52.176185 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4041 23:06:52.182778 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4042 23:06:52.185927 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4043 23:06:52.189878 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4044 23:06:52.192613 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4045 23:06:52.199477 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4046 23:06:52.203182 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4047 23:06:52.206244 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4048 23:06:52.206378 ==
4049 23:06:52.208985 Dram Type= 6, Freq= 0, CH_0, rank 0
4050 23:06:52.212157 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4051 23:06:52.215627 ==
4052 23:06:52.215783 DQS Delay:
4053 23:06:52.215887 DQS0 = 0, DQS1 = 0
4054 23:06:52.218936 DQM Delay:
4055 23:06:52.219044 DQM0 = 43, DQM1 = 32
4056 23:06:52.222341 DQ Delay:
4057 23:06:52.225248 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4058 23:06:52.225372 DQ4 =41, DQ5 =33, DQ6 =57, DQ7 =49
4059 23:06:52.228836 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =33
4060 23:06:52.231946 DQ12 =33, DQ13 =41, DQ14 =41, DQ15 =41
4061 23:06:52.235632
4062 23:06:52.235767
4063 23:06:52.235876 ==
4064 23:06:52.238366 Dram Type= 6, Freq= 0, CH_0, rank 0
4065 23:06:52.242947 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4066 23:06:52.243105 ==
4067 23:06:52.243174
4068 23:06:52.243234
4069 23:06:52.245064 TX Vref Scan disable
4070 23:06:52.245151 == TX Byte 0 ==
4071 23:06:52.252325 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4072 23:06:52.255210 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4073 23:06:52.255345 == TX Byte 1 ==
4074 23:06:52.261659 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4075 23:06:52.265109 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4076 23:06:52.265242 ==
4077 23:06:52.268411 Dram Type= 6, Freq= 0, CH_0, rank 0
4078 23:06:52.271780 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4079 23:06:52.271913 ==
4080 23:06:52.271982
4081 23:06:52.275016
4082 23:06:52.275129 TX Vref Scan disable
4083 23:06:52.278749 == TX Byte 0 ==
4084 23:06:52.282177 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4085 23:06:52.288458 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4086 23:06:52.288628 == TX Byte 1 ==
4087 23:06:52.291738 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4088 23:06:52.298190 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4089 23:06:52.298362
4090 23:06:52.298462 [DATLAT]
4091 23:06:52.298524 Freq=600, CH0 RK0
4092 23:06:52.298615
4093 23:06:52.301848 DATLAT Default: 0x9
4094 23:06:52.305268 0, 0xFFFF, sum = 0
4095 23:06:52.305398 1, 0xFFFF, sum = 0
4096 23:06:52.308191 2, 0xFFFF, sum = 0
4097 23:06:52.308347 3, 0xFFFF, sum = 0
4098 23:06:52.311328 4, 0xFFFF, sum = 0
4099 23:06:52.311516 5, 0xFFFF, sum = 0
4100 23:06:52.315063 6, 0xFFFF, sum = 0
4101 23:06:52.315221 7, 0xFFFF, sum = 0
4102 23:06:52.317974 8, 0x0, sum = 1
4103 23:06:52.318084 9, 0x0, sum = 2
4104 23:06:52.321277 10, 0x0, sum = 3
4105 23:06:52.321395 11, 0x0, sum = 4
4106 23:06:52.321466 best_step = 9
4107 23:06:52.321542
4108 23:06:52.324499 ==
4109 23:06:52.324632 Dram Type= 6, Freq= 0, CH_0, rank 0
4110 23:06:52.331340 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4111 23:06:52.331535 ==
4112 23:06:52.331605 RX Vref Scan: 1
4113 23:06:52.331666
4114 23:06:52.334378 RX Vref 0 -> 0, step: 1
4115 23:06:52.334481
4116 23:06:52.337878 RX Delay -195 -> 252, step: 8
4117 23:06:52.338003
4118 23:06:52.340900 Set Vref, RX VrefLevel [Byte0]: 52
4119 23:06:52.344559 [Byte1]: 50
4120 23:06:52.344696
4121 23:06:52.347838 Final RX Vref Byte 0 = 52 to rank0
4122 23:06:52.351145 Final RX Vref Byte 1 = 50 to rank0
4123 23:06:52.354856 Final RX Vref Byte 0 = 52 to rank1
4124 23:06:52.358679 Final RX Vref Byte 1 = 50 to rank1==
4125 23:06:52.360695 Dram Type= 6, Freq= 0, CH_0, rank 0
4126 23:06:52.364381 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4127 23:06:52.367425 ==
4128 23:06:52.367549 DQS Delay:
4129 23:06:52.367616 DQS0 = 0, DQS1 = 0
4130 23:06:52.370785 DQM Delay:
4131 23:06:52.370901 DQM0 = 42, DQM1 = 34
4132 23:06:52.374308 DQ Delay:
4133 23:06:52.377278 DQ0 =44, DQ1 =44, DQ2 =36, DQ3 =36
4134 23:06:52.380543 DQ4 =44, DQ5 =32, DQ6 =52, DQ7 =48
4135 23:06:52.383551 DQ8 =24, DQ9 =20, DQ10 =36, DQ11 =28
4136 23:06:52.387039 DQ12 =40, DQ13 =44, DQ14 =44, DQ15 =40
4137 23:06:52.387182
4138 23:06:52.387257
4139 23:06:52.393696 [DQSOSCAuto] RK0, (LSB)MR18= 0x4b42, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 395 ps
4140 23:06:52.397030 CH0 RK0: MR19=808, MR18=4B42
4141 23:06:52.403653 CH0_RK0: MR19=0x808, MR18=0x4B42, DQSOSC=395, MR23=63, INC=168, DEC=112
4142 23:06:52.403793
4143 23:06:52.406845 ----->DramcWriteLeveling(PI) begin...
4144 23:06:52.406961 ==
4145 23:06:52.410471 Dram Type= 6, Freq= 0, CH_0, rank 1
4146 23:06:52.413394 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4147 23:06:52.413520 ==
4148 23:06:52.416941 Write leveling (Byte 0): 32 => 32
4149 23:06:52.421018 Write leveling (Byte 1): 30 => 30
4150 23:06:52.423122 DramcWriteLeveling(PI) end<-----
4151 23:06:52.423236
4152 23:06:52.423304 ==
4153 23:06:52.426887 Dram Type= 6, Freq= 0, CH_0, rank 1
4154 23:06:52.429842 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4155 23:06:52.432982 ==
4156 23:06:52.433105 [Gating] SW mode calibration
4157 23:06:52.443119 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4158 23:06:52.446653 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4159 23:06:52.449468 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4160 23:06:52.456571 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4161 23:06:52.459556 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4162 23:06:52.463054 0 9 12 | B1->B0 | 3434 3131 | 1 0 | (1 0) (1 1)
4163 23:06:52.469117 0 9 16 | B1->B0 | 2b2b 2525 | 1 0 | (1 0) (0 0)
4164 23:06:52.472595 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4165 23:06:52.476220 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4166 23:06:52.482700 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4167 23:06:52.485873 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4168 23:06:52.488891 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4169 23:06:52.495722 0 10 8 | B1->B0 | 2323 2525 | 0 1 | (0 0) (0 0)
4170 23:06:52.498703 0 10 12 | B1->B0 | 2828 3434 | 0 0 | (0 0) (0 0)
4171 23:06:52.502425 0 10 16 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
4172 23:06:52.508668 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4173 23:06:52.511889 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4174 23:06:52.515569 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4175 23:06:52.521807 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4176 23:06:52.524968 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4177 23:06:52.528437 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4178 23:06:52.535236 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4179 23:06:52.538273 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4180 23:06:52.541788 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4181 23:06:52.548683 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4182 23:06:52.551461 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4183 23:06:52.554692 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4184 23:06:52.561547 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4185 23:06:52.564623 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4186 23:06:52.571066 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4187 23:06:52.574324 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4188 23:06:52.578223 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4189 23:06:52.584729 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4190 23:06:52.587644 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4191 23:06:52.590697 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4192 23:06:52.597386 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4193 23:06:52.601161 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4194 23:06:52.603760 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4195 23:06:52.607276 Total UI for P1: 0, mck2ui 16
4196 23:06:52.610414 best dqsien dly found for B0: ( 0, 13, 10)
4197 23:06:52.617838 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4198 23:06:52.620334 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4199 23:06:52.624186 Total UI for P1: 0, mck2ui 16
4200 23:06:52.626964 best dqsien dly found for B1: ( 0, 13, 14)
4201 23:06:52.630297 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4202 23:06:52.633875 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4203 23:06:52.634012
4204 23:06:52.637503 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4205 23:06:52.640486 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4206 23:06:52.644052 [Gating] SW calibration Done
4207 23:06:52.644180 ==
4208 23:06:52.646961 Dram Type= 6, Freq= 0, CH_0, rank 1
4209 23:06:52.649957 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4210 23:06:52.653185 ==
4211 23:06:52.653316 RX Vref Scan: 0
4212 23:06:52.653384
4213 23:06:52.657754 RX Vref 0 -> 0, step: 1
4214 23:06:52.657892
4215 23:06:52.660159 RX Delay -230 -> 252, step: 16
4216 23:06:52.663243 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4217 23:06:52.667047 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4218 23:06:52.670222 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4219 23:06:52.676474 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4220 23:06:52.680428 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4221 23:06:52.682749 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4222 23:06:52.686426 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4223 23:06:52.693037 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4224 23:06:52.696423 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4225 23:06:52.699405 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4226 23:06:52.702792 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4227 23:06:52.710067 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4228 23:06:52.712815 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4229 23:06:52.715905 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4230 23:06:52.719666 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4231 23:06:52.725888 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4232 23:06:52.726039 ==
4233 23:06:52.729510 Dram Type= 6, Freq= 0, CH_0, rank 1
4234 23:06:52.732401 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4235 23:06:52.732528 ==
4236 23:06:52.732598 DQS Delay:
4237 23:06:52.735784 DQS0 = 0, DQS1 = 0
4238 23:06:52.735953 DQM Delay:
4239 23:06:52.739250 DQM0 = 40, DQM1 = 31
4240 23:06:52.739386 DQ Delay:
4241 23:06:52.742232 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33
4242 23:06:52.745294 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4243 23:06:52.748714 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4244 23:06:52.752349 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =41
4245 23:06:52.752484
4246 23:06:52.752554
4247 23:06:52.752613 ==
4248 23:06:52.755471 Dram Type= 6, Freq= 0, CH_0, rank 1
4249 23:06:52.758435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4250 23:06:52.758557 ==
4251 23:06:52.761929
4252 23:06:52.762050
4253 23:06:52.762120 TX Vref Scan disable
4254 23:06:52.765043 == TX Byte 0 ==
4255 23:06:52.768993 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4256 23:06:52.772041 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4257 23:06:52.775384 == TX Byte 1 ==
4258 23:06:52.778684 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4259 23:06:52.782054 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4260 23:06:52.784862 ==
4261 23:06:52.789098 Dram Type= 6, Freq= 0, CH_0, rank 1
4262 23:06:52.791512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4263 23:06:52.791637 ==
4264 23:06:52.791709
4265 23:06:52.791781
4266 23:06:52.795125 TX Vref Scan disable
4267 23:06:52.795273 == TX Byte 0 ==
4268 23:06:52.801855 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4269 23:06:52.804674 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4270 23:06:52.808140 == TX Byte 1 ==
4271 23:06:52.811429 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4272 23:06:52.814559 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4273 23:06:52.814691
4274 23:06:52.814759 [DATLAT]
4275 23:06:52.817854 Freq=600, CH0 RK1
4276 23:06:52.817969
4277 23:06:52.818037 DATLAT Default: 0x9
4278 23:06:52.821374 0, 0xFFFF, sum = 0
4279 23:06:52.824423 1, 0xFFFF, sum = 0
4280 23:06:52.824585 2, 0xFFFF, sum = 0
4281 23:06:52.827872 3, 0xFFFF, sum = 0
4282 23:06:52.827996 4, 0xFFFF, sum = 0
4283 23:06:52.831431 5, 0xFFFF, sum = 0
4284 23:06:52.831566 6, 0xFFFF, sum = 0
4285 23:06:52.834829 7, 0xFFFF, sum = 0
4286 23:06:52.834951 8, 0x0, sum = 1
4287 23:06:52.837525 9, 0x0, sum = 2
4288 23:06:52.837629 10, 0x0, sum = 3
4289 23:06:52.840875 11, 0x0, sum = 4
4290 23:06:52.840992 best_step = 9
4291 23:06:52.841059
4292 23:06:52.841120 ==
4293 23:06:52.844424 Dram Type= 6, Freq= 0, CH_0, rank 1
4294 23:06:52.847514 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4295 23:06:52.847635 ==
4296 23:06:52.850571 RX Vref Scan: 0
4297 23:06:52.850679
4298 23:06:52.854243 RX Vref 0 -> 0, step: 1
4299 23:06:52.854365
4300 23:06:52.854434 RX Delay -195 -> 252, step: 8
4301 23:06:52.861910 iDelay=197, Bit 0, Center 40 (-107 ~ 188) 296
4302 23:06:52.865405 iDelay=197, Bit 1, Center 44 (-107 ~ 196) 304
4303 23:06:52.868481 iDelay=197, Bit 2, Center 36 (-115 ~ 188) 304
4304 23:06:52.872068 iDelay=197, Bit 3, Center 40 (-107 ~ 188) 296
4305 23:06:52.878159 iDelay=197, Bit 4, Center 44 (-107 ~ 196) 304
4306 23:06:52.881763 iDelay=197, Bit 5, Center 28 (-123 ~ 180) 304
4307 23:06:52.885547 iDelay=197, Bit 6, Center 48 (-99 ~ 196) 296
4308 23:06:52.888101 iDelay=197, Bit 7, Center 44 (-107 ~ 196) 304
4309 23:06:52.894804 iDelay=197, Bit 8, Center 24 (-131 ~ 180) 312
4310 23:06:52.898303 iDelay=197, Bit 9, Center 20 (-139 ~ 180) 320
4311 23:06:52.901747 iDelay=197, Bit 10, Center 36 (-115 ~ 188) 304
4312 23:06:52.904834 iDelay=197, Bit 11, Center 28 (-123 ~ 180) 304
4313 23:06:52.908289 iDelay=197, Bit 12, Center 40 (-115 ~ 196) 312
4314 23:06:52.915044 iDelay=197, Bit 13, Center 36 (-115 ~ 188) 304
4315 23:06:52.918228 iDelay=197, Bit 14, Center 44 (-107 ~ 196) 304
4316 23:06:52.921562 iDelay=197, Bit 15, Center 40 (-115 ~ 196) 312
4317 23:06:52.921692 ==
4318 23:06:52.924862 Dram Type= 6, Freq= 0, CH_0, rank 1
4319 23:06:52.931071 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4320 23:06:52.931220 ==
4321 23:06:52.931292 DQS Delay:
4322 23:06:52.934690 DQS0 = 0, DQS1 = 0
4323 23:06:52.934813 DQM Delay:
4324 23:06:52.934880 DQM0 = 40, DQM1 = 33
4325 23:06:52.938089 DQ Delay:
4326 23:06:52.941049 DQ0 =40, DQ1 =44, DQ2 =36, DQ3 =40
4327 23:06:52.944455 DQ4 =44, DQ5 =28, DQ6 =48, DQ7 =44
4328 23:06:52.947998 DQ8 =24, DQ9 =20, DQ10 =36, DQ11 =28
4329 23:06:52.950851 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =40
4330 23:06:52.950974
4331 23:06:52.951043
4332 23:06:52.957632 [DQSOSCAuto] RK1, (LSB)MR18= 0x443f, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 396 ps
4333 23:06:52.960866 CH0 RK1: MR19=808, MR18=443F
4334 23:06:52.967511 CH0_RK1: MR19=0x808, MR18=0x443F, DQSOSC=396, MR23=63, INC=167, DEC=111
4335 23:06:52.971018 [RxdqsGatingPostProcess] freq 600
4336 23:06:52.974080 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4337 23:06:52.977964 Pre-setting of DQS Precalculation
4338 23:06:52.984136 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4339 23:06:52.984284 ==
4340 23:06:52.987638 Dram Type= 6, Freq= 0, CH_1, rank 0
4341 23:06:52.990387 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4342 23:06:52.990510 ==
4343 23:06:52.997144 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4344 23:06:53.003718 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4345 23:06:53.007194 [CA 0] Center 35 (5~66) winsize 62
4346 23:06:53.010309 [CA 1] Center 36 (6~66) winsize 61
4347 23:06:53.013745 [CA 2] Center 34 (4~65) winsize 62
4348 23:06:53.017191 [CA 3] Center 34 (4~65) winsize 62
4349 23:06:53.020392 [CA 4] Center 34 (4~65) winsize 62
4350 23:06:53.023416 [CA 5] Center 34 (3~65) winsize 63
4351 23:06:53.023543
4352 23:06:53.026560 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4353 23:06:53.026674
4354 23:06:53.030120 [CATrainingPosCal] consider 1 rank data
4355 23:06:53.033586 u2DelayCellTimex100 = 270/100 ps
4356 23:06:53.036687 CA0 delay=35 (5~66),Diff = 1 PI (9 cell)
4357 23:06:53.040251 CA1 delay=36 (6~66),Diff = 2 PI (19 cell)
4358 23:06:53.043509 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4359 23:06:53.046897 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4360 23:06:53.049735 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4361 23:06:53.053036 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4362 23:06:53.056306
4363 23:06:53.059567 CA PerBit enable=1, Macro0, CA PI delay=34
4364 23:06:53.059694
4365 23:06:53.063065 [CBTSetCACLKResult] CA Dly = 34
4366 23:06:53.063201 CS Dly: 4 (0~35)
4367 23:06:53.063269 ==
4368 23:06:53.066406 Dram Type= 6, Freq= 0, CH_1, rank 1
4369 23:06:53.069768 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4370 23:06:53.069897 ==
4371 23:06:53.076035 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4372 23:06:53.082756 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4373 23:06:53.086260 [CA 0] Center 35 (5~66) winsize 62
4374 23:06:53.089720 [CA 1] Center 35 (5~66) winsize 62
4375 23:06:53.092525 [CA 2] Center 34 (4~65) winsize 62
4376 23:06:53.096082 [CA 3] Center 34 (3~65) winsize 63
4377 23:06:53.099157 [CA 4] Center 34 (4~65) winsize 62
4378 23:06:53.102679 [CA 5] Center 34 (3~65) winsize 63
4379 23:06:53.102812
4380 23:06:53.105726 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4381 23:06:53.105839
4382 23:06:53.109200 [CATrainingPosCal] consider 2 rank data
4383 23:06:53.112432 u2DelayCellTimex100 = 270/100 ps
4384 23:06:53.115518 CA0 delay=35 (5~66),Diff = 1 PI (9 cell)
4385 23:06:53.119025 CA1 delay=36 (6~66),Diff = 2 PI (19 cell)
4386 23:06:53.122508 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4387 23:06:53.128890 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4388 23:06:53.132221 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4389 23:06:53.135423 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4390 23:06:53.135545
4391 23:06:53.138942 CA PerBit enable=1, Macro0, CA PI delay=34
4392 23:06:53.139059
4393 23:06:53.141977 [CBTSetCACLKResult] CA Dly = 34
4394 23:06:53.142089 CS Dly: 4 (0~35)
4395 23:06:53.142157
4396 23:06:53.145466 ----->DramcWriteLeveling(PI) begin...
4397 23:06:53.148558 ==
4398 23:06:53.148681 Dram Type= 6, Freq= 0, CH_1, rank 0
4399 23:06:53.155267 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4400 23:06:53.155464 ==
4401 23:06:53.158236 Write leveling (Byte 0): 28 => 28
4402 23:06:53.161770 Write leveling (Byte 1): 28 => 28
4403 23:06:53.165108 DramcWriteLeveling(PI) end<-----
4404 23:06:53.165236
4405 23:06:53.165303 ==
4406 23:06:53.168484 Dram Type= 6, Freq= 0, CH_1, rank 0
4407 23:06:53.171986 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4408 23:06:53.172116 ==
4409 23:06:53.175341 [Gating] SW mode calibration
4410 23:06:53.182078 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4411 23:06:53.188115 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4412 23:06:53.191757 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4413 23:06:53.195008 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4414 23:06:53.201557 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4415 23:06:53.204500 0 9 12 | B1->B0 | 2f2f 2f2f | 0 0 | (0 1) (0 1)
4416 23:06:53.208039 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4417 23:06:53.214804 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4418 23:06:53.217762 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4419 23:06:53.221128 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4420 23:06:53.228204 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4421 23:06:53.230876 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4422 23:06:53.234217 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4423 23:06:53.241279 0 10 12 | B1->B0 | 3131 3535 | 0 0 | (0 0) (1 1)
4424 23:06:53.244338 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4425 23:06:53.247411 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4426 23:06:53.254187 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4427 23:06:53.257390 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4428 23:06:53.260527 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4429 23:06:53.267210 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4430 23:06:53.270334 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4431 23:06:53.273838 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4432 23:06:53.280493 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4433 23:06:53.284169 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4434 23:06:53.287398 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4435 23:06:53.293665 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4436 23:06:53.297192 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4437 23:06:53.300083 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4438 23:06:53.306724 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4439 23:06:53.310226 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4440 23:06:53.313294 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4441 23:06:53.320274 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4442 23:06:53.323787 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4443 23:06:53.326315 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4444 23:06:53.333041 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4445 23:06:53.336487 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4446 23:06:53.340054 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4447 23:06:53.346445 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4448 23:06:53.350073 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4449 23:06:53.352667 Total UI for P1: 0, mck2ui 16
4450 23:06:53.356491 best dqsien dly found for B0: ( 0, 13, 12)
4451 23:06:53.359332 Total UI for P1: 0, mck2ui 16
4452 23:06:53.362971 best dqsien dly found for B1: ( 0, 13, 12)
4453 23:06:53.366350 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4454 23:06:53.369824 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4455 23:06:53.369992
4456 23:06:53.372678 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4457 23:06:53.375973 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4458 23:06:53.379387 [Gating] SW calibration Done
4459 23:06:53.379564 ==
4460 23:06:53.383019 Dram Type= 6, Freq= 0, CH_1, rank 0
4461 23:06:53.386336 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4462 23:06:53.389174 ==
4463 23:06:53.389334 RX Vref Scan: 0
4464 23:06:53.389437
4465 23:06:53.392245 RX Vref 0 -> 0, step: 1
4466 23:06:53.392379
4467 23:06:53.395784 RX Delay -230 -> 252, step: 16
4468 23:06:53.399046 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4469 23:06:53.402551 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4470 23:06:53.405598 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4471 23:06:53.412079 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4472 23:06:53.415619 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4473 23:06:53.419029 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4474 23:06:53.422201 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4475 23:06:53.428721 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4476 23:06:53.431764 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4477 23:06:53.435371 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4478 23:06:53.438388 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4479 23:06:53.441853 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4480 23:06:53.448372 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4481 23:06:53.451760 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4482 23:06:53.455138 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4483 23:06:53.458274 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4484 23:06:53.461536 ==
4485 23:06:53.466212 Dram Type= 6, Freq= 0, CH_1, rank 0
4486 23:06:53.468326 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4487 23:06:53.468468 ==
4488 23:06:53.468568 DQS Delay:
4489 23:06:53.471694 DQS0 = 0, DQS1 = 0
4490 23:06:53.471836 DQM Delay:
4491 23:06:53.474791 DQM0 = 43, DQM1 = 39
4492 23:06:53.474932 DQ Delay:
4493 23:06:53.477784 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =41
4494 23:06:53.481472 DQ4 =41, DQ5 =57, DQ6 =49, DQ7 =41
4495 23:06:53.485114 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4496 23:06:53.488475 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =41
4497 23:06:53.488640
4498 23:06:53.488744
4499 23:06:53.488834 ==
4500 23:06:53.491387 Dram Type= 6, Freq= 0, CH_1, rank 0
4501 23:06:53.494668 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4502 23:06:53.494824 ==
4503 23:06:53.494925
4504 23:06:53.498300
4505 23:06:53.498452 TX Vref Scan disable
4506 23:06:53.500974 == TX Byte 0 ==
4507 23:06:53.504531 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4508 23:06:53.507990 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4509 23:06:53.510928 == TX Byte 1 ==
4510 23:06:53.514383 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4511 23:06:53.517917 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4512 23:06:53.518083 ==
4513 23:06:53.520935 Dram Type= 6, Freq= 0, CH_1, rank 0
4514 23:06:53.527805 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4515 23:06:53.527990 ==
4516 23:06:53.528093
4517 23:06:53.528184
4518 23:06:53.530766 TX Vref Scan disable
4519 23:06:53.530895 == TX Byte 0 ==
4520 23:06:53.538281 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4521 23:06:53.540542 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4522 23:06:53.540686 == TX Byte 1 ==
4523 23:06:53.547491 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4524 23:06:53.550619 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4525 23:06:53.550781
4526 23:06:53.550887 [DATLAT]
4527 23:06:53.554122 Freq=600, CH1 RK0
4528 23:06:53.554271
4529 23:06:53.554370 DATLAT Default: 0x9
4530 23:06:53.557048 0, 0xFFFF, sum = 0
4531 23:06:53.557179 1, 0xFFFF, sum = 0
4532 23:06:53.560728 2, 0xFFFF, sum = 0
4533 23:06:53.560884 3, 0xFFFF, sum = 0
4534 23:06:53.563694 4, 0xFFFF, sum = 0
4535 23:06:53.567039 5, 0xFFFF, sum = 0
4536 23:06:53.567198 6, 0xFFFF, sum = 0
4537 23:06:53.570324 7, 0xFFFF, sum = 0
4538 23:06:53.570469 8, 0x0, sum = 1
4539 23:06:53.570570 9, 0x0, sum = 2
4540 23:06:53.573536 10, 0x0, sum = 3
4541 23:06:53.573674 11, 0x0, sum = 4
4542 23:06:53.576721 best_step = 9
4543 23:06:53.576866
4544 23:06:53.576965 ==
4545 23:06:53.579909 Dram Type= 6, Freq= 0, CH_1, rank 0
4546 23:06:53.583525 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4547 23:06:53.583688 ==
4548 23:06:53.586817 RX Vref Scan: 1
4549 23:06:53.586972
4550 23:06:53.587075 RX Vref 0 -> 0, step: 1
4551 23:06:53.587164
4552 23:06:53.589921 RX Delay -179 -> 252, step: 8
4553 23:06:53.590052
4554 23:06:53.593096 Set Vref, RX VrefLevel [Byte0]: 51
4555 23:06:53.596345 [Byte1]: 51
4556 23:06:53.601101
4557 23:06:53.601286 Final RX Vref Byte 0 = 51 to rank0
4558 23:06:53.604369 Final RX Vref Byte 1 = 51 to rank0
4559 23:06:53.607741 Final RX Vref Byte 0 = 51 to rank1
4560 23:06:53.610674 Final RX Vref Byte 1 = 51 to rank1==
4561 23:06:53.614513 Dram Type= 6, Freq= 0, CH_1, rank 0
4562 23:06:53.620854 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4563 23:06:53.621046 ==
4564 23:06:53.621151 DQS Delay:
4565 23:06:53.623771 DQS0 = 0, DQS1 = 0
4566 23:06:53.623905 DQM Delay:
4567 23:06:53.624003 DQM0 = 42, DQM1 = 33
4568 23:06:53.627191 DQ Delay:
4569 23:06:53.630239 DQ0 =48, DQ1 =40, DQ2 =32, DQ3 =40
4570 23:06:53.633492 DQ4 =36, DQ5 =48, DQ6 =56, DQ7 =36
4571 23:06:53.637150 DQ8 =16, DQ9 =20, DQ10 =36, DQ11 =28
4572 23:06:53.640525 DQ12 =44, DQ13 =44, DQ14 =40, DQ15 =40
4573 23:06:53.640687
4574 23:06:53.640789
4575 23:06:53.647029 [DQSOSCAuto] RK0, (LSB)MR18= 0x2c46, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 401 ps
4576 23:06:53.650301 CH1 RK0: MR19=808, MR18=2C46
4577 23:06:53.656523 CH1_RK0: MR19=0x808, MR18=0x2C46, DQSOSC=396, MR23=63, INC=167, DEC=111
4578 23:06:53.656717
4579 23:06:53.660267 ----->DramcWriteLeveling(PI) begin...
4580 23:06:53.660439 ==
4581 23:06:53.663290 Dram Type= 6, Freq= 0, CH_1, rank 1
4582 23:06:53.666347 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4583 23:06:53.666503 ==
4584 23:06:53.669725 Write leveling (Byte 0): 30 => 30
4585 23:06:53.672898 Write leveling (Byte 1): 30 => 30
4586 23:06:53.676530 DramcWriteLeveling(PI) end<-----
4587 23:06:53.676685
4588 23:06:53.676788 ==
4589 23:06:53.679389 Dram Type= 6, Freq= 0, CH_1, rank 1
4590 23:06:53.686210 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4591 23:06:53.686405 ==
4592 23:06:53.686517 [Gating] SW mode calibration
4593 23:06:53.696391 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4594 23:06:53.699331 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4595 23:06:53.702883 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4596 23:06:53.709681 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4597 23:06:53.712692 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4598 23:06:53.716128 0 9 12 | B1->B0 | 3030 2f2f | 0 0 | (0 1) (1 1)
4599 23:06:53.722784 0 9 16 | B1->B0 | 2525 2323 | 1 0 | (1 0) (0 0)
4600 23:06:53.726123 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4601 23:06:53.729031 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4602 23:06:53.735801 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4603 23:06:53.739337 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4604 23:06:53.745480 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4605 23:06:53.748801 0 10 8 | B1->B0 | 2323 2827 | 0 1 | (0 0) (0 0)
4606 23:06:53.752464 0 10 12 | B1->B0 | 2d2d 4141 | 0 1 | (0 0) (0 0)
4607 23:06:53.758739 0 10 16 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
4608 23:06:53.761861 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4609 23:06:53.765161 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4610 23:06:53.771693 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4611 23:06:53.774984 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4612 23:06:53.778585 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4613 23:06:53.784730 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4614 23:06:53.788430 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4615 23:06:53.791282 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4616 23:06:53.798217 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4617 23:06:53.801508 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4618 23:06:53.804370 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4619 23:06:53.811030 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4620 23:06:53.814384 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4621 23:06:53.817450 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4622 23:06:53.824062 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4623 23:06:53.827754 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4624 23:06:53.830410 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4625 23:06:53.837328 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4626 23:06:53.840496 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4627 23:06:53.843893 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4628 23:06:53.850785 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4629 23:06:53.854220 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4630 23:06:53.857341 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4631 23:06:53.860330 Total UI for P1: 0, mck2ui 16
4632 23:06:53.864337 best dqsien dly found for B0: ( 0, 13, 8)
4633 23:06:53.866991 Total UI for P1: 0, mck2ui 16
4634 23:06:53.869906 best dqsien dly found for B1: ( 0, 13, 10)
4635 23:06:53.873130 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4636 23:06:53.879966 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4637 23:06:53.880160
4638 23:06:53.883297 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4639 23:06:53.886671 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4640 23:06:53.889545 [Gating] SW calibration Done
4641 23:06:53.889707 ==
4642 23:06:53.893424 Dram Type= 6, Freq= 0, CH_1, rank 1
4643 23:06:53.896015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4644 23:06:53.896159 ==
4645 23:06:53.899841 RX Vref Scan: 0
4646 23:06:53.900008
4647 23:06:53.900109 RX Vref 0 -> 0, step: 1
4648 23:06:53.900199
4649 23:06:53.903131 RX Delay -230 -> 252, step: 16
4650 23:06:53.906024 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4651 23:06:53.913043 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4652 23:06:53.916134 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4653 23:06:53.919591 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4654 23:06:53.922663 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4655 23:06:53.929104 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4656 23:06:53.932532 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4657 23:06:53.936691 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4658 23:06:53.939485 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4659 23:06:53.942536 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4660 23:06:53.948862 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4661 23:06:53.952804 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4662 23:06:53.955640 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4663 23:06:53.959001 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4664 23:06:53.965805 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4665 23:06:53.969000 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4666 23:06:53.969173 ==
4667 23:06:53.972047 Dram Type= 6, Freq= 0, CH_1, rank 1
4668 23:06:53.975623 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4669 23:06:53.975795 ==
4670 23:06:53.978761 DQS Delay:
4671 23:06:53.978908 DQS0 = 0, DQS1 = 0
4672 23:06:53.981674 DQM Delay:
4673 23:06:53.981808 DQM0 = 40, DQM1 = 38
4674 23:06:53.981909 DQ Delay:
4675 23:06:53.985089 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =33
4676 23:06:53.988437 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =33
4677 23:06:53.991993 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4678 23:06:53.995127 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =49
4679 23:06:53.995289
4680 23:06:53.998308
4681 23:06:53.998453 ==
4682 23:06:54.001891 Dram Type= 6, Freq= 0, CH_1, rank 1
4683 23:06:54.005147 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4684 23:06:54.005309 ==
4685 23:06:54.005413
4686 23:06:54.005503
4687 23:06:54.008734 TX Vref Scan disable
4688 23:06:54.008878 == TX Byte 0 ==
4689 23:06:54.014769 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4690 23:06:54.018172 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4691 23:06:54.018349 == TX Byte 1 ==
4692 23:06:54.024962 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4693 23:06:54.028372 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4694 23:06:54.028545 ==
4695 23:06:54.031233 Dram Type= 6, Freq= 0, CH_1, rank 1
4696 23:06:54.034809 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4697 23:06:54.034975 ==
4698 23:06:54.035080
4699 23:06:54.035171
4700 23:06:54.037804 TX Vref Scan disable
4701 23:06:54.041283 == TX Byte 0 ==
4702 23:06:54.044620 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4703 23:06:54.047649 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4704 23:06:54.051164 == TX Byte 1 ==
4705 23:06:54.054072 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4706 23:06:54.061213 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4707 23:06:54.061414
4708 23:06:54.061523 [DATLAT]
4709 23:06:54.061616 Freq=600, CH1 RK1
4710 23:06:54.061707
4711 23:06:54.064102 DATLAT Default: 0x9
4712 23:06:54.064227 0, 0xFFFF, sum = 0
4713 23:06:54.067587 1, 0xFFFF, sum = 0
4714 23:06:54.067737 2, 0xFFFF, sum = 0
4715 23:06:54.070662 3, 0xFFFF, sum = 0
4716 23:06:54.074071 4, 0xFFFF, sum = 0
4717 23:06:54.074226 5, 0xFFFF, sum = 0
4718 23:06:54.077191 6, 0xFFFF, sum = 0
4719 23:06:54.077336 7, 0xFFFF, sum = 0
4720 23:06:54.080582 8, 0x0, sum = 1
4721 23:06:54.080731 9, 0x0, sum = 2
4722 23:06:54.080833 10, 0x0, sum = 3
4723 23:06:54.083749 11, 0x0, sum = 4
4724 23:06:54.083884 best_step = 9
4725 23:06:54.083980
4726 23:06:54.084070 ==
4727 23:06:54.087087 Dram Type= 6, Freq= 0, CH_1, rank 1
4728 23:06:54.093898 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4729 23:06:54.094092 ==
4730 23:06:54.094203 RX Vref Scan: 0
4731 23:06:54.094295
4732 23:06:54.097533 RX Vref 0 -> 0, step: 1
4733 23:06:54.097697
4734 23:06:54.100917 RX Delay -179 -> 252, step: 8
4735 23:06:54.103986 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4736 23:06:54.110252 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4737 23:06:54.113503 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4738 23:06:54.116785 iDelay=205, Bit 3, Center 36 (-123 ~ 196) 320
4739 23:06:54.120335 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4740 23:06:54.126570 iDelay=205, Bit 5, Center 44 (-115 ~ 204) 320
4741 23:06:54.129803 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4742 23:06:54.133565 iDelay=205, Bit 7, Center 36 (-123 ~ 196) 320
4743 23:06:54.136577 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4744 23:06:54.143286 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4745 23:06:54.146655 iDelay=205, Bit 10, Center 36 (-115 ~ 188) 304
4746 23:06:54.149732 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4747 23:06:54.153057 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4748 23:06:54.159964 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4749 23:06:54.163313 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4750 23:06:54.166722 iDelay=205, Bit 15, Center 44 (-115 ~ 204) 320
4751 23:06:54.166892 ==
4752 23:06:54.169274 Dram Type= 6, Freq= 0, CH_1, rank 1
4753 23:06:54.173042 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4754 23:06:54.176231 ==
4755 23:06:54.176384 DQS Delay:
4756 23:06:54.176505 DQS0 = 0, DQS1 = 0
4757 23:06:54.179543 DQM Delay:
4758 23:06:54.179690 DQM0 = 37, DQM1 = 34
4759 23:06:54.182508 DQ Delay:
4760 23:06:54.185749 DQ0 =40, DQ1 =36, DQ2 =24, DQ3 =36
4761 23:06:54.185907 DQ4 =36, DQ5 =44, DQ6 =48, DQ7 =36
4762 23:06:54.189070 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =24
4763 23:06:54.192731 DQ12 =44, DQ13 =40, DQ14 =40, DQ15 =44
4764 23:06:54.196289
4765 23:06:54.196460
4766 23:06:54.202780 [DQSOSCAuto] RK1, (LSB)MR18= 0x3c61, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
4767 23:06:54.205609 CH1 RK1: MR19=808, MR18=3C61
4768 23:06:54.212146 CH1_RK1: MR19=0x808, MR18=0x3C61, DQSOSC=391, MR23=63, INC=171, DEC=114
4769 23:06:54.215423 [RxdqsGatingPostProcess] freq 600
4770 23:06:54.218601 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4771 23:06:54.222427 Pre-setting of DQS Precalculation
4772 23:06:54.228677 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4773 23:06:54.235156 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4774 23:06:54.242355 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4775 23:06:54.242553
4776 23:06:54.242660
4777 23:06:54.244952 [Calibration Summary] 1200 Mbps
4778 23:06:54.245076 CH 0, Rank 0
4779 23:06:54.249103 SW Impedance : PASS
4780 23:06:54.252255 DUTY Scan : NO K
4781 23:06:54.252421 ZQ Calibration : PASS
4782 23:06:54.255301 Jitter Meter : NO K
4783 23:06:54.258442 CBT Training : PASS
4784 23:06:54.258606 Write leveling : PASS
4785 23:06:54.261694 RX DQS gating : PASS
4786 23:06:54.265554 RX DQ/DQS(RDDQC) : PASS
4787 23:06:54.265723 TX DQ/DQS : PASS
4788 23:06:54.268657 RX DATLAT : PASS
4789 23:06:54.271852 RX DQ/DQS(Engine): PASS
4790 23:06:54.272013 TX OE : NO K
4791 23:06:54.272121 All Pass.
4792 23:06:54.275440
4793 23:06:54.275589 CH 0, Rank 1
4794 23:06:54.278597 SW Impedance : PASS
4795 23:06:54.278703 DUTY Scan : NO K
4796 23:06:54.282044 ZQ Calibration : PASS
4797 23:06:54.282186 Jitter Meter : NO K
4798 23:06:54.284841 CBT Training : PASS
4799 23:06:54.288342 Write leveling : PASS
4800 23:06:54.288498 RX DQS gating : PASS
4801 23:06:54.291777 RX DQ/DQS(RDDQC) : PASS
4802 23:06:54.295529 TX DQ/DQS : PASS
4803 23:06:54.295697 RX DATLAT : PASS
4804 23:06:54.298281 RX DQ/DQS(Engine): PASS
4805 23:06:54.301592 TX OE : NO K
4806 23:06:54.301745 All Pass.
4807 23:06:54.301839
4808 23:06:54.301929 CH 1, Rank 0
4809 23:06:54.304628 SW Impedance : PASS
4810 23:06:54.308129 DUTY Scan : NO K
4811 23:06:54.308263 ZQ Calibration : PASS
4812 23:06:54.311070 Jitter Meter : NO K
4813 23:06:54.314301 CBT Training : PASS
4814 23:06:54.314437 Write leveling : PASS
4815 23:06:54.317591 RX DQS gating : PASS
4816 23:06:54.321098 RX DQ/DQS(RDDQC) : PASS
4817 23:06:54.321235 TX DQ/DQS : PASS
4818 23:06:54.324804 RX DATLAT : PASS
4819 23:06:54.327921 RX DQ/DQS(Engine): PASS
4820 23:06:54.328054 TX OE : NO K
4821 23:06:54.330777 All Pass.
4822 23:06:54.330895
4823 23:06:54.330965 CH 1, Rank 1
4824 23:06:54.333911 SW Impedance : PASS
4825 23:06:54.334040 DUTY Scan : NO K
4826 23:06:54.337743 ZQ Calibration : PASS
4827 23:06:54.340602 Jitter Meter : NO K
4828 23:06:54.340730 CBT Training : PASS
4829 23:06:54.344151 Write leveling : PASS
4830 23:06:54.347403 RX DQS gating : PASS
4831 23:06:54.347529 RX DQ/DQS(RDDQC) : PASS
4832 23:06:54.350735 TX DQ/DQS : PASS
4833 23:06:54.354084 RX DATLAT : PASS
4834 23:06:54.354220 RX DQ/DQS(Engine): PASS
4835 23:06:54.357130 TX OE : NO K
4836 23:06:54.357250 All Pass.
4837 23:06:54.357339
4838 23:06:54.360495 DramC Write-DBI off
4839 23:06:54.363932 PER_BANK_REFRESH: Hybrid Mode
4840 23:06:54.364074 TX_TRACKING: ON
4841 23:06:54.373730 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4842 23:06:54.376763 [FAST_K] Save calibration result to emmc
4843 23:06:54.380023 dramc_set_vcore_voltage set vcore to 662500
4844 23:06:54.383242 Read voltage for 933, 3
4845 23:06:54.383380 Vio18 = 0
4846 23:06:54.383487 Vcore = 662500
4847 23:06:54.386782 Vdram = 0
4848 23:06:54.386923 Vddq = 0
4849 23:06:54.387017 Vmddr = 0
4850 23:06:54.393751 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4851 23:06:54.396391 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4852 23:06:54.400093 MEM_TYPE=3, freq_sel=17
4853 23:06:54.403391 sv_algorithm_assistance_LP4_1600
4854 23:06:54.406891 ============ PULL DRAM RESETB DOWN ============
4855 23:06:54.410129 ========== PULL DRAM RESETB DOWN end =========
4856 23:06:54.416650 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4857 23:06:54.419854 ===================================
4858 23:06:54.423356 LPDDR4 DRAM CONFIGURATION
4859 23:06:54.426434 ===================================
4860 23:06:54.426592 EX_ROW_EN[0] = 0x0
4861 23:06:54.429586 EX_ROW_EN[1] = 0x0
4862 23:06:54.429708 LP4Y_EN = 0x0
4863 23:06:54.433094 WORK_FSP = 0x0
4864 23:06:54.433223 WL = 0x3
4865 23:06:54.436094 RL = 0x3
4866 23:06:54.436241 BL = 0x2
4867 23:06:54.440040 RPST = 0x0
4868 23:06:54.440179 RD_PRE = 0x0
4869 23:06:54.442998 WR_PRE = 0x1
4870 23:06:54.443144 WR_PST = 0x0
4871 23:06:54.446343 DBI_WR = 0x0
4872 23:06:54.449458 DBI_RD = 0x0
4873 23:06:54.449616 OTF = 0x1
4874 23:06:54.453163 ===================================
4875 23:06:54.456321 ===================================
4876 23:06:54.456470 ANA top config
4877 23:06:54.459497 ===================================
4878 23:06:54.462567 DLL_ASYNC_EN = 0
4879 23:06:54.465949 ALL_SLAVE_EN = 1
4880 23:06:54.469100 NEW_RANK_MODE = 1
4881 23:06:54.472527 DLL_IDLE_MODE = 1
4882 23:06:54.472696 LP45_APHY_COMB_EN = 1
4883 23:06:54.475500 TX_ODT_DIS = 1
4884 23:06:54.478757 NEW_8X_MODE = 1
4885 23:06:54.482417 ===================================
4886 23:06:54.485912 ===================================
4887 23:06:54.488706 data_rate = 1866
4888 23:06:54.492697 CKR = 1
4889 23:06:54.495251 DQ_P2S_RATIO = 8
4890 23:06:54.498816 ===================================
4891 23:06:54.498953 CA_P2S_RATIO = 8
4892 23:06:54.502043 DQ_CA_OPEN = 0
4893 23:06:54.505581 DQ_SEMI_OPEN = 0
4894 23:06:54.508778 CA_SEMI_OPEN = 0
4895 23:06:54.511730 CA_FULL_RATE = 0
4896 23:06:54.515633 DQ_CKDIV4_EN = 1
4897 23:06:54.515775 CA_CKDIV4_EN = 1
4898 23:06:54.518885 CA_PREDIV_EN = 0
4899 23:06:54.521785 PH8_DLY = 0
4900 23:06:54.525442 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4901 23:06:54.528561 DQ_AAMCK_DIV = 4
4902 23:06:54.531671 CA_AAMCK_DIV = 4
4903 23:06:54.531821 CA_ADMCK_DIV = 4
4904 23:06:54.534980 DQ_TRACK_CA_EN = 0
4905 23:06:54.539111 CA_PICK = 933
4906 23:06:54.542324 CA_MCKIO = 933
4907 23:06:54.544864 MCKIO_SEMI = 0
4908 23:06:54.548551 PLL_FREQ = 3732
4909 23:06:54.551511 DQ_UI_PI_RATIO = 32
4910 23:06:54.551658 CA_UI_PI_RATIO = 0
4911 23:06:54.554397 ===================================
4912 23:06:54.557732 ===================================
4913 23:06:54.561200 memory_type:LPDDR4
4914 23:06:54.564357 GP_NUM : 10
4915 23:06:54.564510 SRAM_EN : 1
4916 23:06:54.568088 MD32_EN : 0
4917 23:06:54.571125 ===================================
4918 23:06:54.574749 [ANA_INIT] >>>>>>>>>>>>>>
4919 23:06:54.577850 <<<<<< [CONFIGURE PHASE]: ANA_TX
4920 23:06:54.581066 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4921 23:06:54.584359 ===================================
4922 23:06:54.587510 data_rate = 1866,PCW = 0X8f00
4923 23:06:54.590774 ===================================
4924 23:06:54.593970 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4925 23:06:54.597438 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4926 23:06:54.604121 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4927 23:06:54.607312 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4928 23:06:54.611268 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4929 23:06:54.613661 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4930 23:06:54.617511 [ANA_INIT] flow start
4931 23:06:54.620442 [ANA_INIT] PLL >>>>>>>>
4932 23:06:54.620573 [ANA_INIT] PLL <<<<<<<<
4933 23:06:54.623470 [ANA_INIT] MIDPI >>>>>>>>
4934 23:06:54.627008 [ANA_INIT] MIDPI <<<<<<<<
4935 23:06:54.630011 [ANA_INIT] DLL >>>>>>>>
4936 23:06:54.630141 [ANA_INIT] flow end
4937 23:06:54.633600 ============ LP4 DIFF to SE enter ============
4938 23:06:54.640411 ============ LP4 DIFF to SE exit ============
4939 23:06:54.640555 [ANA_INIT] <<<<<<<<<<<<<
4940 23:06:54.643386 [Flow] Enable top DCM control >>>>>
4941 23:06:54.647503 [Flow] Enable top DCM control <<<<<
4942 23:06:54.650034 Enable DLL master slave shuffle
4943 23:06:54.656557 ==============================================================
4944 23:06:54.659919 Gating Mode config
4945 23:06:54.662939 ==============================================================
4946 23:06:54.666318 Config description:
4947 23:06:54.676124 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4948 23:06:54.682894 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4949 23:06:54.686020 SELPH_MODE 0: By rank 1: By Phase
4950 23:06:54.692773 ==============================================================
4951 23:06:54.695906 GAT_TRACK_EN = 1
4952 23:06:54.699534 RX_GATING_MODE = 2
4953 23:06:54.702820 RX_GATING_TRACK_MODE = 2
4954 23:06:54.705883 SELPH_MODE = 1
4955 23:06:54.706018 PICG_EARLY_EN = 1
4956 23:06:54.709130 VALID_LAT_VALUE = 1
4957 23:06:54.715997 ==============================================================
4958 23:06:54.719159 Enter into Gating configuration >>>>
4959 23:06:54.722119 Exit from Gating configuration <<<<
4960 23:06:54.725876 Enter into DVFS_PRE_config >>>>>
4961 23:06:54.735815 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4962 23:06:54.739123 Exit from DVFS_PRE_config <<<<<
4963 23:06:54.742254 Enter into PICG configuration >>>>
4964 23:06:54.745425 Exit from PICG configuration <<<<
4965 23:06:54.749143 [RX_INPUT] configuration >>>>>
4966 23:06:54.752178 [RX_INPUT] configuration <<<<<
4967 23:06:54.758875 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4968 23:06:54.762376 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4969 23:06:54.768655 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4970 23:06:54.775179 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4971 23:06:54.781461 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4972 23:06:54.788650 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4973 23:06:54.791575 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4974 23:06:54.794684 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4975 23:06:54.798121 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4976 23:06:54.804671 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4977 23:06:54.808145 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4978 23:06:54.811342 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4979 23:06:54.814315 ===================================
4980 23:06:54.817823 LPDDR4 DRAM CONFIGURATION
4981 23:06:54.821402 ===================================
4982 23:06:54.821536 EX_ROW_EN[0] = 0x0
4983 23:06:54.824461 EX_ROW_EN[1] = 0x0
4984 23:06:54.828634 LP4Y_EN = 0x0
4985 23:06:54.828776 WORK_FSP = 0x0
4986 23:06:54.831211 WL = 0x3
4987 23:06:54.831317 RL = 0x3
4988 23:06:54.834340 BL = 0x2
4989 23:06:54.834455 RPST = 0x0
4990 23:06:54.837814 RD_PRE = 0x0
4991 23:06:54.837935 WR_PRE = 0x1
4992 23:06:54.840967 WR_PST = 0x0
4993 23:06:54.841089 DBI_WR = 0x0
4994 23:06:54.844183 DBI_RD = 0x0
4995 23:06:54.844299 OTF = 0x1
4996 23:06:54.847772 ===================================
4997 23:06:54.854319 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4998 23:06:54.857783 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4999 23:06:54.860889 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5000 23:06:54.864253 ===================================
5001 23:06:54.867313 LPDDR4 DRAM CONFIGURATION
5002 23:06:54.870940 ===================================
5003 23:06:54.874031 EX_ROW_EN[0] = 0x10
5004 23:06:54.874162 EX_ROW_EN[1] = 0x0
5005 23:06:54.877619 LP4Y_EN = 0x0
5006 23:06:54.877746 WORK_FSP = 0x0
5007 23:06:54.880623 WL = 0x3
5008 23:06:54.880738 RL = 0x3
5009 23:06:54.883514 BL = 0x2
5010 23:06:54.883612 RPST = 0x0
5011 23:06:54.887495 RD_PRE = 0x0
5012 23:06:54.887620 WR_PRE = 0x1
5013 23:06:54.890554 WR_PST = 0x0
5014 23:06:54.890671 DBI_WR = 0x0
5015 23:06:54.894065 DBI_RD = 0x0
5016 23:06:54.894190 OTF = 0x1
5017 23:06:54.897353 ===================================
5018 23:06:54.903669 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5019 23:06:54.908600 nWR fixed to 30
5020 23:06:54.911429 [ModeRegInit_LP4] CH0 RK0
5021 23:06:54.911555 [ModeRegInit_LP4] CH0 RK1
5022 23:06:54.915016 [ModeRegInit_LP4] CH1 RK0
5023 23:06:54.918527 [ModeRegInit_LP4] CH1 RK1
5024 23:06:54.918674 match AC timing 9
5025 23:06:54.924874 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5026 23:06:54.927805 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5027 23:06:54.931138 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5028 23:06:54.937985 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5029 23:06:54.941169 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5030 23:06:54.941348 ==
5031 23:06:54.944226 Dram Type= 6, Freq= 0, CH_0, rank 0
5032 23:06:54.947566 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5033 23:06:54.951250 ==
5034 23:06:54.954228 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5035 23:06:54.961334 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5036 23:06:54.964378 [CA 0] Center 38 (8~68) winsize 61
5037 23:06:54.968697 [CA 1] Center 37 (7~68) winsize 62
5038 23:06:54.970527 [CA 2] Center 34 (4~65) winsize 62
5039 23:06:54.974032 [CA 3] Center 34 (4~65) winsize 62
5040 23:06:54.977265 [CA 4] Center 33 (3~63) winsize 61
5041 23:06:54.980515 [CA 5] Center 32 (2~63) winsize 62
5042 23:06:54.980684
5043 23:06:54.983868 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5044 23:06:54.984017
5045 23:06:54.987187 [CATrainingPosCal] consider 1 rank data
5046 23:06:54.990967 u2DelayCellTimex100 = 270/100 ps
5047 23:06:54.993921 CA0 delay=38 (8~68),Diff = 6 PI (37 cell)
5048 23:06:54.997204 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5049 23:06:55.000274 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5050 23:06:55.007111 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5051 23:06:55.010332 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5052 23:06:55.013885 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5053 23:06:55.014048
5054 23:06:55.017011 CA PerBit enable=1, Macro0, CA PI delay=32
5055 23:06:55.017155
5056 23:06:55.020381 [CBTSetCACLKResult] CA Dly = 32
5057 23:06:55.020535 CS Dly: 6 (0~37)
5058 23:06:55.020641 ==
5059 23:06:55.023736 Dram Type= 6, Freq= 0, CH_0, rank 1
5060 23:06:55.030087 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5061 23:06:55.030280 ==
5062 23:06:55.033499 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5063 23:06:55.039968 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5064 23:06:55.043174 [CA 0] Center 38 (8~68) winsize 61
5065 23:06:55.047062 [CA 1] Center 37 (7~68) winsize 62
5066 23:06:55.049735 [CA 2] Center 34 (4~65) winsize 62
5067 23:06:55.053275 [CA 3] Center 34 (4~65) winsize 62
5068 23:06:55.056551 [CA 4] Center 33 (3~64) winsize 62
5069 23:06:55.059671 [CA 5] Center 32 (2~63) winsize 62
5070 23:06:55.059839
5071 23:06:55.063124 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5072 23:06:55.063273
5073 23:06:55.066677 [CATrainingPosCal] consider 2 rank data
5074 23:06:55.069793 u2DelayCellTimex100 = 270/100 ps
5075 23:06:55.073407 CA0 delay=38 (8~68),Diff = 6 PI (37 cell)
5076 23:06:55.079585 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5077 23:06:55.082978 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5078 23:06:55.086644 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5079 23:06:55.089762 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5080 23:06:55.092557 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5081 23:06:55.092718
5082 23:06:55.096318 CA PerBit enable=1, Macro0, CA PI delay=32
5083 23:06:55.096484
5084 23:06:55.100093 [CBTSetCACLKResult] CA Dly = 32
5085 23:06:55.103116 CS Dly: 7 (0~39)
5086 23:06:55.103274
5087 23:06:55.106022 ----->DramcWriteLeveling(PI) begin...
5088 23:06:55.106170 ==
5089 23:06:55.109338 Dram Type= 6, Freq= 0, CH_0, rank 0
5090 23:06:55.112490 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5091 23:06:55.112652 ==
5092 23:06:55.116123 Write leveling (Byte 0): 33 => 33
5093 23:06:55.119234 Write leveling (Byte 1): 25 => 25
5094 23:06:55.122516 DramcWriteLeveling(PI) end<-----
5095 23:06:55.122683
5096 23:06:55.122789 ==
5097 23:06:55.125824 Dram Type= 6, Freq= 0, CH_0, rank 0
5098 23:06:55.128996 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5099 23:06:55.129155 ==
5100 23:06:55.132255 [Gating] SW mode calibration
5101 23:06:55.138850 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5102 23:06:55.145494 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5103 23:06:55.149285 0 14 0 | B1->B0 | 2525 3434 | 0 1 | (0 0) (1 1)
5104 23:06:55.155697 0 14 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5105 23:06:55.159345 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5106 23:06:55.162058 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5107 23:06:55.168623 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5108 23:06:55.171993 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5109 23:06:55.175315 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5110 23:06:55.181881 0 14 28 | B1->B0 | 3434 2929 | 1 1 | (1 1) (1 0)
5111 23:06:55.184909 0 15 0 | B1->B0 | 3131 2323 | 1 0 | (0 1) (0 0)
5112 23:06:55.188570 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5113 23:06:55.194969 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5114 23:06:55.198330 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5115 23:06:55.201608 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5116 23:06:55.208350 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5117 23:06:55.211533 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5118 23:06:55.214783 0 15 28 | B1->B0 | 2323 3a3a | 0 1 | (0 0) (0 0)
5119 23:06:55.221737 1 0 0 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
5120 23:06:55.224923 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5121 23:06:55.228046 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5122 23:06:55.231521 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5123 23:06:55.237987 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5124 23:06:55.241331 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5125 23:06:55.244806 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5126 23:06:55.251296 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5127 23:06:55.254294 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5128 23:06:55.261599 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5129 23:06:55.264069 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5130 23:06:55.267332 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5131 23:06:55.274015 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5132 23:06:55.277937 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5133 23:06:55.280485 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5134 23:06:55.287674 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5135 23:06:55.290253 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5136 23:06:55.293627 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5137 23:06:55.300338 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5138 23:06:55.303505 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5139 23:06:55.306857 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5140 23:06:55.313657 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5141 23:06:55.316794 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5142 23:06:55.320145 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5143 23:06:55.326507 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5144 23:06:55.326701 Total UI for P1: 0, mck2ui 16
5145 23:06:55.333418 best dqsien dly found for B0: ( 1, 2, 28)
5146 23:06:55.336500 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5147 23:06:55.339917 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5148 23:06:55.343500 Total UI for P1: 0, mck2ui 16
5149 23:06:55.346491 best dqsien dly found for B1: ( 1, 3, 2)
5150 23:06:55.349814 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5151 23:06:55.353247 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5152 23:06:55.353412
5153 23:06:55.360243 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5154 23:06:55.362626 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5155 23:06:55.362779 [Gating] SW calibration Done
5156 23:06:55.366020 ==
5157 23:06:55.366182 Dram Type= 6, Freq= 0, CH_0, rank 0
5158 23:06:55.372469 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5159 23:06:55.372657 ==
5160 23:06:55.372764 RX Vref Scan: 0
5161 23:06:55.372856
5162 23:06:55.375819 RX Vref 0 -> 0, step: 1
5163 23:06:55.375958
5164 23:06:55.379024 RX Delay -80 -> 252, step: 8
5165 23:06:55.382577 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5166 23:06:55.386003 iDelay=208, Bit 1, Center 103 (8 ~ 199) 192
5167 23:06:55.389229 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5168 23:06:55.395482 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5169 23:06:55.399073 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5170 23:06:55.402329 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5171 23:06:55.405776 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5172 23:06:55.408806 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5173 23:06:55.415992 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5174 23:06:55.418737 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5175 23:06:55.421901 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5176 23:06:55.425232 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5177 23:06:55.428444 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5178 23:06:55.435020 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5179 23:06:55.438312 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5180 23:06:55.441788 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5181 23:06:55.441931 ==
5182 23:06:55.444930 Dram Type= 6, Freq= 0, CH_0, rank 0
5183 23:06:55.447931 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5184 23:06:55.448068 ==
5185 23:06:55.451220 DQS Delay:
5186 23:06:55.451328 DQS0 = 0, DQS1 = 0
5187 23:06:55.451438 DQM Delay:
5188 23:06:55.454542 DQM0 = 101, DQM1 = 89
5189 23:06:55.454688 DQ Delay:
5190 23:06:55.458261 DQ0 =103, DQ1 =103, DQ2 =95, DQ3 =95
5191 23:06:55.461497 DQ4 =103, DQ5 =87, DQ6 =111, DQ7 =111
5192 23:06:55.464883 DQ8 =83, DQ9 =75, DQ10 =91, DQ11 =83
5193 23:06:55.467625 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5194 23:06:55.467743
5195 23:06:55.471088
5196 23:06:55.471199 ==
5197 23:06:55.474350 Dram Type= 6, Freq= 0, CH_0, rank 0
5198 23:06:55.477432 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5199 23:06:55.477558 ==
5200 23:06:55.477658
5201 23:06:55.477738
5202 23:06:55.481277 TX Vref Scan disable
5203 23:06:55.481405 == TX Byte 0 ==
5204 23:06:55.487849 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5205 23:06:55.490723 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5206 23:06:55.490854 == TX Byte 1 ==
5207 23:06:55.497421 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5208 23:06:55.501239 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5209 23:06:55.501388 ==
5210 23:06:55.503926 Dram Type= 6, Freq= 0, CH_0, rank 0
5211 23:06:55.507346 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5212 23:06:55.507490 ==
5213 23:06:55.507592
5214 23:06:55.507673
5215 23:06:55.510796 TX Vref Scan disable
5216 23:06:55.514116 == TX Byte 0 ==
5217 23:06:55.517089 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5218 23:06:55.520682 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5219 23:06:55.523691 == TX Byte 1 ==
5220 23:06:55.527059 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5221 23:06:55.533800 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5222 23:06:55.533996
5223 23:06:55.534104 [DATLAT]
5224 23:06:55.534198 Freq=933, CH0 RK0
5225 23:06:55.534291
5226 23:06:55.536938 DATLAT Default: 0xd
5227 23:06:55.537075 0, 0xFFFF, sum = 0
5228 23:06:55.540274 1, 0xFFFF, sum = 0
5229 23:06:55.543720 2, 0xFFFF, sum = 0
5230 23:06:55.543890 3, 0xFFFF, sum = 0
5231 23:06:55.546768 4, 0xFFFF, sum = 0
5232 23:06:55.546913 5, 0xFFFF, sum = 0
5233 23:06:55.549874 6, 0xFFFF, sum = 0
5234 23:06:55.550025 7, 0xFFFF, sum = 0
5235 23:06:55.553418 8, 0xFFFF, sum = 0
5236 23:06:55.553576 9, 0xFFFF, sum = 0
5237 23:06:55.556510 10, 0x0, sum = 1
5238 23:06:55.556653 11, 0x0, sum = 2
5239 23:06:55.560176 12, 0x0, sum = 3
5240 23:06:55.560332 13, 0x0, sum = 4
5241 23:06:55.560441 best_step = 11
5242 23:06:55.563308
5243 23:06:55.563463 ==
5244 23:06:55.566645 Dram Type= 6, Freq= 0, CH_0, rank 0
5245 23:06:55.569918 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5246 23:06:55.570083 ==
5247 23:06:55.570189 RX Vref Scan: 1
5248 23:06:55.570282
5249 23:06:55.573589 RX Vref 0 -> 0, step: 1
5250 23:06:55.573731
5251 23:06:55.576480 RX Delay -61 -> 252, step: 4
5252 23:06:55.576623
5253 23:06:55.579700 Set Vref, RX VrefLevel [Byte0]: 52
5254 23:06:55.583535 [Byte1]: 50
5255 23:06:55.586134
5256 23:06:55.586283 Final RX Vref Byte 0 = 52 to rank0
5257 23:06:55.589951 Final RX Vref Byte 1 = 50 to rank0
5258 23:06:55.592711 Final RX Vref Byte 0 = 52 to rank1
5259 23:06:55.596151 Final RX Vref Byte 1 = 50 to rank1==
5260 23:06:55.599719 Dram Type= 6, Freq= 0, CH_0, rank 0
5261 23:06:55.606267 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5262 23:06:55.606466 ==
5263 23:06:55.606576 DQS Delay:
5264 23:06:55.609312 DQS0 = 0, DQS1 = 0
5265 23:06:55.609455 DQM Delay:
5266 23:06:55.609558 DQM0 = 99, DQM1 = 87
5267 23:06:55.612926 DQ Delay:
5268 23:06:55.615982 DQ0 =100, DQ1 =100, DQ2 =94, DQ3 =96
5269 23:06:55.619666 DQ4 =100, DQ5 =92, DQ6 =110, DQ7 =106
5270 23:06:55.622724 DQ8 =80, DQ9 =74, DQ10 =88, DQ11 =82
5271 23:06:55.625742 DQ12 =94, DQ13 =92, DQ14 =98, DQ15 =94
5272 23:06:55.625909
5273 23:06:55.626014
5274 23:06:55.632799 [DQSOSCAuto] RK0, (LSB)MR18= 0x1913, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 413 ps
5275 23:06:55.635519 CH0 RK0: MR19=505, MR18=1913
5276 23:06:55.642482 CH0_RK0: MR19=0x505, MR18=0x1913, DQSOSC=413, MR23=63, INC=63, DEC=42
5277 23:06:55.642680
5278 23:06:55.645839 ----->DramcWriteLeveling(PI) begin...
5279 23:06:55.645995 ==
5280 23:06:55.649131 Dram Type= 6, Freq= 0, CH_0, rank 1
5281 23:06:55.652283 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5282 23:06:55.652422 ==
5283 23:06:55.655585 Write leveling (Byte 0): 31 => 31
5284 23:06:55.659052 Write leveling (Byte 1): 29 => 29
5285 23:06:55.662266 DramcWriteLeveling(PI) end<-----
5286 23:06:55.662392
5287 23:06:55.662471 ==
5288 23:06:55.665286 Dram Type= 6, Freq= 0, CH_0, rank 1
5289 23:06:55.671883 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5290 23:06:55.672038 ==
5291 23:06:55.672108 [Gating] SW mode calibration
5292 23:06:55.681601 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5293 23:06:55.685216 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5294 23:06:55.691531 0 14 0 | B1->B0 | 2928 3434 | 1 1 | (0 0) (1 1)
5295 23:06:55.695119 0 14 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5296 23:06:55.698406 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5297 23:06:55.701810 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5298 23:06:55.708295 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5299 23:06:55.711784 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5300 23:06:55.717910 0 14 24 | B1->B0 | 3434 3232 | 1 1 | (1 1) (0 0)
5301 23:06:55.721374 0 14 28 | B1->B0 | 3333 2a2a | 1 0 | (1 0) (0 0)
5302 23:06:55.724994 0 15 0 | B1->B0 | 2f2f 2323 | 0 0 | (0 1) (0 0)
5303 23:06:55.731498 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5304 23:06:55.734725 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5305 23:06:55.737935 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5306 23:06:55.744092 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5307 23:06:55.748060 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5308 23:06:55.751005 0 15 24 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
5309 23:06:55.757302 0 15 28 | B1->B0 | 2929 4040 | 0 0 | (0 0) (0 0)
5310 23:06:55.760519 1 0 0 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
5311 23:06:55.763767 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5312 23:06:55.770304 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5313 23:06:55.773819 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5314 23:06:55.776997 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5315 23:06:55.783533 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5316 23:06:55.787279 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5317 23:06:55.790362 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5318 23:06:55.796713 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5319 23:06:55.799839 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5320 23:06:55.803406 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5321 23:06:55.810048 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5322 23:06:55.813390 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5323 23:06:55.816607 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5324 23:06:55.823332 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5325 23:06:55.826317 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5326 23:06:55.829870 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5327 23:06:55.836240 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5328 23:06:55.839437 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5329 23:06:55.842770 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5330 23:06:55.849207 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5331 23:06:55.852835 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5332 23:06:55.855735 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5333 23:06:55.862780 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5334 23:06:55.866072 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5335 23:06:55.868748 Total UI for P1: 0, mck2ui 16
5336 23:06:55.872200 best dqsien dly found for B0: ( 1, 2, 28)
5337 23:06:55.875442 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5338 23:06:55.878659 Total UI for P1: 0, mck2ui 16
5339 23:06:55.881927 best dqsien dly found for B1: ( 1, 3, 0)
5340 23:06:55.885537 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5341 23:06:55.888904 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5342 23:06:55.889080
5343 23:06:55.895752 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5344 23:06:55.899061 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5345 23:06:55.901978 [Gating] SW calibration Done
5346 23:06:55.902149 ==
5347 23:06:55.905469 Dram Type= 6, Freq= 0, CH_0, rank 1
5348 23:06:55.908644 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5349 23:06:55.908809 ==
5350 23:06:55.908916 RX Vref Scan: 0
5351 23:06:55.909010
5352 23:06:55.911895 RX Vref 0 -> 0, step: 1
5353 23:06:55.912040
5354 23:06:55.915072 RX Delay -80 -> 252, step: 8
5355 23:06:55.918501 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5356 23:06:55.921768 iDelay=200, Bit 1, Center 99 (0 ~ 199) 200
5357 23:06:55.925029 iDelay=200, Bit 2, Center 95 (0 ~ 191) 192
5358 23:06:55.931811 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5359 23:06:55.935112 iDelay=200, Bit 4, Center 99 (0 ~ 199) 200
5360 23:06:55.938431 iDelay=200, Bit 5, Center 87 (-8 ~ 183) 192
5361 23:06:55.942422 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5362 23:06:55.944753 iDelay=200, Bit 7, Center 103 (8 ~ 199) 192
5363 23:06:55.951735 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5364 23:06:55.954626 iDelay=200, Bit 9, Center 75 (-16 ~ 167) 184
5365 23:06:55.958141 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5366 23:06:55.961282 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5367 23:06:55.964457 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5368 23:06:55.968297 iDelay=200, Bit 13, Center 91 (0 ~ 183) 184
5369 23:06:55.974664 iDelay=200, Bit 14, Center 99 (8 ~ 191) 184
5370 23:06:55.977775 iDelay=200, Bit 15, Center 91 (0 ~ 183) 184
5371 23:06:55.977915 ==
5372 23:06:55.981225 Dram Type= 6, Freq= 0, CH_0, rank 1
5373 23:06:55.984096 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5374 23:06:55.984249 ==
5375 23:06:55.987834 DQS Delay:
5376 23:06:55.987963 DQS0 = 0, DQS1 = 0
5377 23:06:55.988061 DQM Delay:
5378 23:06:55.990884 DQM0 = 97, DQM1 = 88
5379 23:06:55.990994 DQ Delay:
5380 23:06:55.994269 DQ0 =95, DQ1 =99, DQ2 =95, DQ3 =95
5381 23:06:55.997831 DQ4 =99, DQ5 =87, DQ6 =103, DQ7 =103
5382 23:06:56.000675 DQ8 =83, DQ9 =75, DQ10 =87, DQ11 =83
5383 23:06:56.004949 DQ12 =95, DQ13 =91, DQ14 =99, DQ15 =91
5384 23:06:56.005083
5385 23:06:56.005175
5386 23:06:56.005260 ==
5387 23:06:56.007842 Dram Type= 6, Freq= 0, CH_0, rank 1
5388 23:06:56.014231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5389 23:06:56.014375 ==
5390 23:06:56.014475
5391 23:06:56.014557
5392 23:06:56.014655 TX Vref Scan disable
5393 23:06:56.018019 == TX Byte 0 ==
5394 23:06:56.021039 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5395 23:06:56.027988 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5396 23:06:56.028148 == TX Byte 1 ==
5397 23:06:56.030982 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5398 23:06:56.037354 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5399 23:06:56.037513 ==
5400 23:06:56.040681 Dram Type= 6, Freq= 0, CH_0, rank 1
5401 23:06:56.044154 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5402 23:06:56.044264 ==
5403 23:06:56.044336
5404 23:06:56.044397
5405 23:06:56.047633 TX Vref Scan disable
5406 23:06:56.047718 == TX Byte 0 ==
5407 23:06:56.054036 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5408 23:06:56.057523 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5409 23:06:56.060846 == TX Byte 1 ==
5410 23:06:56.064343 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5411 23:06:56.067802 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5412 23:06:56.067922
5413 23:06:56.067991 [DATLAT]
5414 23:06:56.070521 Freq=933, CH0 RK1
5415 23:06:56.070616
5416 23:06:56.070683 DATLAT Default: 0xb
5417 23:06:56.074160 0, 0xFFFF, sum = 0
5418 23:06:56.077199 1, 0xFFFF, sum = 0
5419 23:06:56.077305 2, 0xFFFF, sum = 0
5420 23:06:56.080145 3, 0xFFFF, sum = 0
5421 23:06:56.080245 4, 0xFFFF, sum = 0
5422 23:06:56.083525 5, 0xFFFF, sum = 0
5423 23:06:56.083622 6, 0xFFFF, sum = 0
5424 23:06:56.086766 7, 0xFFFF, sum = 0
5425 23:06:56.086852 8, 0xFFFF, sum = 0
5426 23:06:56.090490 9, 0xFFFF, sum = 0
5427 23:06:56.090582 10, 0x0, sum = 1
5428 23:06:56.093915 11, 0x0, sum = 2
5429 23:06:56.094023 12, 0x0, sum = 3
5430 23:06:56.096948 13, 0x0, sum = 4
5431 23:06:56.097049 best_step = 11
5432 23:06:56.097136
5433 23:06:56.097216 ==
5434 23:06:56.100031 Dram Type= 6, Freq= 0, CH_0, rank 1
5435 23:06:56.103661 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5436 23:06:56.106679 ==
5437 23:06:56.106781 RX Vref Scan: 0
5438 23:06:56.106868
5439 23:06:56.109967 RX Vref 0 -> 0, step: 1
5440 23:06:56.110051
5441 23:06:56.113172 RX Delay -61 -> 252, step: 4
5442 23:06:56.116514 iDelay=195, Bit 0, Center 96 (11 ~ 182) 172
5443 23:06:56.119536 iDelay=195, Bit 1, Center 100 (11 ~ 190) 180
5444 23:06:56.126147 iDelay=195, Bit 2, Center 92 (3 ~ 182) 180
5445 23:06:56.129301 iDelay=195, Bit 3, Center 96 (7 ~ 186) 180
5446 23:06:56.132870 iDelay=195, Bit 4, Center 100 (11 ~ 190) 180
5447 23:06:56.136056 iDelay=195, Bit 5, Center 86 (-5 ~ 178) 184
5448 23:06:56.139810 iDelay=195, Bit 6, Center 106 (19 ~ 194) 176
5449 23:06:56.142711 iDelay=195, Bit 7, Center 104 (15 ~ 194) 180
5450 23:06:56.149617 iDelay=195, Bit 8, Center 80 (-9 ~ 170) 180
5451 23:06:56.152434 iDelay=195, Bit 9, Center 76 (-13 ~ 166) 180
5452 23:06:56.156086 iDelay=195, Bit 10, Center 88 (-1 ~ 178) 180
5453 23:06:56.158916 iDelay=195, Bit 11, Center 82 (-5 ~ 170) 176
5454 23:06:56.162464 iDelay=195, Bit 12, Center 92 (3 ~ 182) 180
5455 23:06:56.169203 iDelay=195, Bit 13, Center 92 (3 ~ 182) 180
5456 23:06:56.172653 iDelay=195, Bit 14, Center 100 (11 ~ 190) 180
5457 23:06:56.175672 iDelay=195, Bit 15, Center 92 (3 ~ 182) 180
5458 23:06:56.175772 ==
5459 23:06:56.178873 Dram Type= 6, Freq= 0, CH_0, rank 1
5460 23:06:56.181976 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5461 23:06:56.185320 ==
5462 23:06:56.185417 DQS Delay:
5463 23:06:56.185506 DQS0 = 0, DQS1 = 0
5464 23:06:56.188739 DQM Delay:
5465 23:06:56.188830 DQM0 = 97, DQM1 = 87
5466 23:06:56.192030 DQ Delay:
5467 23:06:56.195310 DQ0 =96, DQ1 =100, DQ2 =92, DQ3 =96
5468 23:06:56.198716 DQ4 =100, DQ5 =86, DQ6 =106, DQ7 =104
5469 23:06:56.202407 DQ8 =80, DQ9 =76, DQ10 =88, DQ11 =82
5470 23:06:56.205410 DQ12 =92, DQ13 =92, DQ14 =100, DQ15 =92
5471 23:06:56.205543
5472 23:06:56.205641
5473 23:06:56.212073 [DQSOSCAuto] RK1, (LSB)MR18= 0x1310, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 415 ps
5474 23:06:56.215110 CH0 RK1: MR19=505, MR18=1310
5475 23:06:56.221492 CH0_RK1: MR19=0x505, MR18=0x1310, DQSOSC=415, MR23=63, INC=62, DEC=41
5476 23:06:56.225049 [RxdqsGatingPostProcess] freq 933
5477 23:06:56.227951 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5478 23:06:56.232234 best DQS0 dly(2T, 0.5T) = (0, 10)
5479 23:06:56.234947 best DQS1 dly(2T, 0.5T) = (0, 11)
5480 23:06:56.238257 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5481 23:06:56.241266 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5482 23:06:56.244397 best DQS0 dly(2T, 0.5T) = (0, 10)
5483 23:06:56.247627 best DQS1 dly(2T, 0.5T) = (0, 11)
5484 23:06:56.251277 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5485 23:06:56.254526 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5486 23:06:56.257654 Pre-setting of DQS Precalculation
5487 23:06:56.261104 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5488 23:06:56.264191 ==
5489 23:06:56.267791 Dram Type= 6, Freq= 0, CH_1, rank 0
5490 23:06:56.271339 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5491 23:06:56.271493 ==
5492 23:06:56.274218 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5493 23:06:56.281199 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5494 23:06:56.284524 [CA 0] Center 36 (6~67) winsize 62
5495 23:06:56.287707 [CA 1] Center 36 (6~67) winsize 62
5496 23:06:56.291701 [CA 2] Center 35 (5~65) winsize 61
5497 23:06:56.295416 [CA 3] Center 34 (4~65) winsize 62
5498 23:06:56.297533 [CA 4] Center 34 (4~65) winsize 62
5499 23:06:56.301087 [CA 5] Center 33 (3~64) winsize 62
5500 23:06:56.301189
5501 23:06:56.304549 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5502 23:06:56.304633
5503 23:06:56.307718 [CATrainingPosCal] consider 1 rank data
5504 23:06:56.310991 u2DelayCellTimex100 = 270/100 ps
5505 23:06:56.314178 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5506 23:06:56.320660 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5507 23:06:56.324264 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5508 23:06:56.327371 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5509 23:06:56.330560 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5510 23:06:56.334223 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5511 23:06:56.334314
5512 23:06:56.337720 CA PerBit enable=1, Macro0, CA PI delay=33
5513 23:06:56.337808
5514 23:06:56.340893 [CBTSetCACLKResult] CA Dly = 33
5515 23:06:56.344175 CS Dly: 4 (0~35)
5516 23:06:56.344264 ==
5517 23:06:56.347292 Dram Type= 6, Freq= 0, CH_1, rank 1
5518 23:06:56.350470 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5519 23:06:56.350567 ==
5520 23:06:56.357423 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5521 23:06:56.363446 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5522 23:06:56.366588 [CA 0] Center 36 (6~67) winsize 62
5523 23:06:56.370395 [CA 1] Center 36 (6~67) winsize 62
5524 23:06:56.373103 [CA 2] Center 34 (4~65) winsize 62
5525 23:06:56.376739 [CA 3] Center 33 (3~64) winsize 62
5526 23:06:56.379907 [CA 4] Center 33 (3~64) winsize 62
5527 23:06:56.383395 [CA 5] Center 33 (3~64) winsize 62
5528 23:06:56.383480
5529 23:06:56.386516 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5530 23:06:56.386596
5531 23:06:56.389738 [CATrainingPosCal] consider 2 rank data
5532 23:06:56.393438 u2DelayCellTimex100 = 270/100 ps
5533 23:06:56.396296 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5534 23:06:56.399711 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5535 23:06:56.402960 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5536 23:06:56.406554 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5537 23:06:56.409502 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5538 23:06:56.412897 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5539 23:06:56.412985
5540 23:06:56.419915 CA PerBit enable=1, Macro0, CA PI delay=33
5541 23:06:56.420050
5542 23:06:56.420144 [CBTSetCACLKResult] CA Dly = 33
5543 23:06:56.423021 CS Dly: 5 (0~38)
5544 23:06:56.423120
5545 23:06:56.426243 ----->DramcWriteLeveling(PI) begin...
5546 23:06:56.426342 ==
5547 23:06:56.429520 Dram Type= 6, Freq= 0, CH_1, rank 0
5548 23:06:56.432542 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5549 23:06:56.432641 ==
5550 23:06:56.436122 Write leveling (Byte 0): 26 => 26
5551 23:06:56.439713 Write leveling (Byte 1): 25 => 25
5552 23:06:56.442640 DramcWriteLeveling(PI) end<-----
5553 23:06:56.442739
5554 23:06:56.442827 ==
5555 23:06:56.445710 Dram Type= 6, Freq= 0, CH_1, rank 0
5556 23:06:56.452658 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5557 23:06:56.452755 ==
5558 23:06:56.452841 [Gating] SW mode calibration
5559 23:06:56.462556 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5560 23:06:56.465711 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5561 23:06:56.472132 0 14 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5562 23:06:56.475287 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5563 23:06:56.478704 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5564 23:06:56.485401 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5565 23:06:56.488651 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5566 23:06:56.491694 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5567 23:06:56.498245 0 14 24 | B1->B0 | 3434 3030 | 0 1 | (0 0) (1 1)
5568 23:06:56.501620 0 14 28 | B1->B0 | 2c2c 2323 | 0 0 | (0 1) (0 0)
5569 23:06:56.504793 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5570 23:06:56.511302 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5571 23:06:56.514844 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5572 23:06:56.518271 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5573 23:06:56.524623 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5574 23:06:56.528068 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5575 23:06:56.531039 0 15 24 | B1->B0 | 2424 2c2c | 1 0 | (0 0) (0 0)
5576 23:06:56.537630 0 15 28 | B1->B0 | 3a3a 4040 | 1 1 | (0 0) (0 0)
5577 23:06:56.540699 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5578 23:06:56.544602 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5579 23:06:56.550667 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5580 23:06:56.554188 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5581 23:06:56.557320 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5582 23:06:56.563778 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5583 23:06:56.567013 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5584 23:06:56.570880 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5585 23:06:56.577253 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5586 23:06:56.580800 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5587 23:06:56.584050 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5588 23:06:56.590244 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5589 23:06:56.593603 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5590 23:06:56.596964 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5591 23:06:56.603368 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5592 23:06:56.606828 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5593 23:06:56.610389 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5594 23:06:56.616826 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5595 23:06:56.620180 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5596 23:06:56.623198 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5597 23:06:56.629639 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5598 23:06:56.633014 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5599 23:06:56.636453 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5600 23:06:56.642941 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5601 23:06:56.646459 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5602 23:06:56.649606 Total UI for P1: 0, mck2ui 16
5603 23:06:56.652889 best dqsien dly found for B0: ( 1, 2, 28)
5604 23:06:56.655847 Total UI for P1: 0, mck2ui 16
5605 23:06:56.659513 best dqsien dly found for B1: ( 1, 2, 28)
5606 23:06:56.662989 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5607 23:06:56.665959 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5608 23:06:56.666060
5609 23:06:56.669261 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5610 23:06:56.675678 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5611 23:06:56.675788 [Gating] SW calibration Done
5612 23:06:56.675879 ==
5613 23:06:56.678727 Dram Type= 6, Freq= 0, CH_1, rank 0
5614 23:06:56.685320 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5615 23:06:56.685415 ==
5616 23:06:56.685501 RX Vref Scan: 0
5617 23:06:56.685579
5618 23:06:56.688630 RX Vref 0 -> 0, step: 1
5619 23:06:56.688708
5620 23:06:56.692057 RX Delay -80 -> 252, step: 8
5621 23:06:56.695281 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5622 23:06:56.699016 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5623 23:06:56.702305 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5624 23:06:56.705833 iDelay=208, Bit 3, Center 99 (0 ~ 199) 200
5625 23:06:56.712187 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5626 23:06:56.715283 iDelay=208, Bit 5, Center 107 (16 ~ 199) 184
5627 23:06:56.718505 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5628 23:06:56.721853 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5629 23:06:56.724965 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5630 23:06:56.731599 iDelay=208, Bit 9, Center 87 (-8 ~ 183) 192
5631 23:06:56.734705 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5632 23:06:56.738136 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5633 23:06:56.741381 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5634 23:06:56.745281 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5635 23:06:56.751105 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5636 23:06:56.754497 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5637 23:06:56.754598 ==
5638 23:06:56.758129 Dram Type= 6, Freq= 0, CH_1, rank 0
5639 23:06:56.760983 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5640 23:06:56.761088 ==
5641 23:06:56.764235 DQS Delay:
5642 23:06:56.764326 DQS0 = 0, DQS1 = 0
5643 23:06:56.764411 DQM Delay:
5644 23:06:56.767917 DQM0 = 99, DQM1 = 95
5645 23:06:56.768004 DQ Delay:
5646 23:06:56.771136 DQ0 =103, DQ1 =95, DQ2 =87, DQ3 =99
5647 23:06:56.774558 DQ4 =95, DQ5 =107, DQ6 =111, DQ7 =95
5648 23:06:56.777734 DQ8 =83, DQ9 =87, DQ10 =91, DQ11 =87
5649 23:06:56.781205 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =103
5650 23:06:56.781312
5651 23:06:56.781401
5652 23:06:56.784483 ==
5653 23:06:56.787505 Dram Type= 6, Freq= 0, CH_1, rank 0
5654 23:06:56.790790 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5655 23:06:56.790880 ==
5656 23:06:56.790966
5657 23:06:56.791045
5658 23:06:56.793989 TX Vref Scan disable
5659 23:06:56.794086 == TX Byte 0 ==
5660 23:06:56.800549 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5661 23:06:56.804448 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5662 23:06:56.804557 == TX Byte 1 ==
5663 23:06:56.810318 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5664 23:06:56.813717 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5665 23:06:56.813827 ==
5666 23:06:56.817072 Dram Type= 6, Freq= 0, CH_1, rank 0
5667 23:06:56.820425 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5668 23:06:56.820539 ==
5669 23:06:56.820630
5670 23:06:56.820711
5671 23:06:56.823413 TX Vref Scan disable
5672 23:06:56.826878 == TX Byte 0 ==
5673 23:06:56.830338 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5674 23:06:56.833751 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5675 23:06:56.836862 == TX Byte 1 ==
5676 23:06:56.839903 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5677 23:06:56.843401 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5678 23:06:56.843496
5679 23:06:56.846831 [DATLAT]
5680 23:06:56.846922 Freq=933, CH1 RK0
5681 23:06:56.846986
5682 23:06:56.850325 DATLAT Default: 0xd
5683 23:06:56.850421 0, 0xFFFF, sum = 0
5684 23:06:56.853474 1, 0xFFFF, sum = 0
5685 23:06:56.853567 2, 0xFFFF, sum = 0
5686 23:06:56.856744 3, 0xFFFF, sum = 0
5687 23:06:56.856833 4, 0xFFFF, sum = 0
5688 23:06:56.860019 5, 0xFFFF, sum = 0
5689 23:06:56.860108 6, 0xFFFF, sum = 0
5690 23:06:56.863247 7, 0xFFFF, sum = 0
5691 23:06:56.863337 8, 0xFFFF, sum = 0
5692 23:06:56.867038 9, 0xFFFF, sum = 0
5693 23:06:56.867133 10, 0x0, sum = 1
5694 23:06:56.869730 11, 0x0, sum = 2
5695 23:06:56.869816 12, 0x0, sum = 3
5696 23:06:56.873110 13, 0x0, sum = 4
5697 23:06:56.873196 best_step = 11
5698 23:06:56.873264
5699 23:06:56.873324 ==
5700 23:06:56.876734 Dram Type= 6, Freq= 0, CH_1, rank 0
5701 23:06:56.883227 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5702 23:06:56.883358 ==
5703 23:06:56.883471 RX Vref Scan: 1
5704 23:06:56.883564
5705 23:06:56.886321 RX Vref 0 -> 0, step: 1
5706 23:06:56.886398
5707 23:06:56.889523 RX Delay -53 -> 252, step: 4
5708 23:06:56.889611
5709 23:06:56.892952 Set Vref, RX VrefLevel [Byte0]: 51
5710 23:06:56.896510 [Byte1]: 51
5711 23:06:56.896626
5712 23:06:56.899930 Final RX Vref Byte 0 = 51 to rank0
5713 23:06:56.902987 Final RX Vref Byte 1 = 51 to rank0
5714 23:06:56.905980 Final RX Vref Byte 0 = 51 to rank1
5715 23:06:56.909281 Final RX Vref Byte 1 = 51 to rank1==
5716 23:06:56.912574 Dram Type= 6, Freq= 0, CH_1, rank 0
5717 23:06:56.916541 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5718 23:06:56.916670 ==
5719 23:06:56.919454 DQS Delay:
5720 23:06:56.919561 DQS0 = 0, DQS1 = 0
5721 23:06:56.922438 DQM Delay:
5722 23:06:56.922543 DQM0 = 98, DQM1 = 94
5723 23:06:56.922608 DQ Delay:
5724 23:06:56.925789 DQ0 =102, DQ1 =92, DQ2 =86, DQ3 =100
5725 23:06:56.928950 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =92
5726 23:06:56.933249 DQ8 =80, DQ9 =84, DQ10 =94, DQ11 =88
5727 23:06:56.939032 DQ12 =102, DQ13 =104, DQ14 =100, DQ15 =104
5728 23:06:56.939176
5729 23:06:56.939249
5730 23:06:56.945885 [DQSOSCAuto] RK0, (LSB)MR18= 0xb1b, (MSB)MR19= 0x505, tDQSOscB0 = 413 ps tDQSOscB1 = 418 ps
5731 23:06:56.949301 CH1 RK0: MR19=505, MR18=B1B
5732 23:06:56.956002 CH1_RK0: MR19=0x505, MR18=0xB1B, DQSOSC=413, MR23=63, INC=63, DEC=42
5733 23:06:56.956157
5734 23:06:56.958991 ----->DramcWriteLeveling(PI) begin...
5735 23:06:56.959114 ==
5736 23:06:56.962085 Dram Type= 6, Freq= 0, CH_1, rank 1
5737 23:06:56.965275 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5738 23:06:56.965421 ==
5739 23:06:56.969035 Write leveling (Byte 0): 24 => 24
5740 23:06:56.972169 Write leveling (Byte 1): 30 => 30
5741 23:06:56.975349 DramcWriteLeveling(PI) end<-----
5742 23:06:56.975501
5743 23:06:56.975568 ==
5744 23:06:56.978674 Dram Type= 6, Freq= 0, CH_1, rank 1
5745 23:06:56.981769 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5746 23:06:56.981904 ==
5747 23:06:56.985130 [Gating] SW mode calibration
5748 23:06:56.991847 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5749 23:06:56.998686 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5750 23:06:57.001880 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5751 23:06:57.008716 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5752 23:06:57.011278 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5753 23:06:57.015008 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5754 23:06:57.021057 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5755 23:06:57.024710 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5756 23:06:57.028070 0 14 24 | B1->B0 | 3232 2f2f | 1 0 | (1 1) (0 0)
5757 23:06:57.034620 0 14 28 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
5758 23:06:57.037796 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5759 23:06:57.041720 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5760 23:06:57.047832 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5761 23:06:57.051069 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5762 23:06:57.054445 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5763 23:06:57.060837 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5764 23:06:57.064823 0 15 24 | B1->B0 | 2828 3838 | 0 0 | (0 0) (0 0)
5765 23:06:57.067609 0 15 28 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
5766 23:06:57.074346 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5767 23:06:57.077571 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5768 23:06:57.080965 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5769 23:06:57.087554 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5770 23:06:57.090646 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5771 23:06:57.093946 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5772 23:06:57.100640 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5773 23:06:57.103665 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5774 23:06:57.107563 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5775 23:06:57.113749 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5776 23:06:57.117494 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5777 23:06:57.120501 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5778 23:06:57.127056 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5779 23:06:57.130471 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5780 23:06:57.133750 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5781 23:06:57.140179 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5782 23:06:57.143571 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5783 23:06:57.147080 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5784 23:06:57.153170 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5785 23:06:57.156331 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5786 23:06:57.159811 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5787 23:06:57.166398 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5788 23:06:57.170074 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5789 23:06:57.173200 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5790 23:06:57.176059 Total UI for P1: 0, mck2ui 16
5791 23:06:57.179393 best dqsien dly found for B0: ( 1, 2, 24)
5792 23:06:57.182661 Total UI for P1: 0, mck2ui 16
5793 23:06:57.186085 best dqsien dly found for B1: ( 1, 2, 26)
5794 23:06:57.189926 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5795 23:06:57.193116 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5796 23:06:57.193227
5797 23:06:57.199497 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5798 23:06:57.202697 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5799 23:06:57.205649 [Gating] SW calibration Done
5800 23:06:57.205751 ==
5801 23:06:57.209030 Dram Type= 6, Freq= 0, CH_1, rank 1
5802 23:06:57.212602 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5803 23:06:57.212740 ==
5804 23:06:57.212816 RX Vref Scan: 0
5805 23:06:57.215949
5806 23:06:57.216068 RX Vref 0 -> 0, step: 1
5807 23:06:57.216137
5808 23:06:57.219294 RX Delay -80 -> 252, step: 8
5809 23:06:57.222449 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5810 23:06:57.225605 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5811 23:06:57.232231 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5812 23:06:57.235385 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5813 23:06:57.238816 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5814 23:06:57.242006 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5815 23:06:57.245497 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5816 23:06:57.248726 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5817 23:06:57.255292 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5818 23:06:57.258548 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5819 23:06:57.261656 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5820 23:06:57.264845 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5821 23:06:57.268545 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5822 23:06:57.275226 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5823 23:06:57.278110 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5824 23:06:57.281410 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5825 23:06:57.281534 ==
5826 23:06:57.285536 Dram Type= 6, Freq= 0, CH_1, rank 1
5827 23:06:57.288089 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5828 23:06:57.288202 ==
5829 23:06:57.291113 DQS Delay:
5830 23:06:57.291222 DQS0 = 0, DQS1 = 0
5831 23:06:57.294564 DQM Delay:
5832 23:06:57.294684 DQM0 = 97, DQM1 = 94
5833 23:06:57.294753 DQ Delay:
5834 23:06:57.297891 DQ0 =103, DQ1 =91, DQ2 =87, DQ3 =95
5835 23:06:57.302591 DQ4 =95, DQ5 =107, DQ6 =103, DQ7 =95
5836 23:06:57.304313 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =87
5837 23:06:57.307688 DQ12 =103, DQ13 =99, DQ14 =99, DQ15 =103
5838 23:06:57.307846
5839 23:06:57.311265
5840 23:06:57.311447 ==
5841 23:06:57.314462 Dram Type= 6, Freq= 0, CH_1, rank 1
5842 23:06:57.317767 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5843 23:06:57.317868 ==
5844 23:06:57.317951
5845 23:06:57.318026
5846 23:06:57.321158 TX Vref Scan disable
5847 23:06:57.321263 == TX Byte 0 ==
5848 23:06:57.327585 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5849 23:06:57.331488 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5850 23:06:57.331585 == TX Byte 1 ==
5851 23:06:57.337242 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5852 23:06:57.340942 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5853 23:06:57.341034 ==
5854 23:06:57.344112 Dram Type= 6, Freq= 0, CH_1, rank 1
5855 23:06:57.347231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5856 23:06:57.347349 ==
5857 23:06:57.347462
5858 23:06:57.347525
5859 23:06:57.350640 TX Vref Scan disable
5860 23:06:57.353848 == TX Byte 0 ==
5861 23:06:57.357565 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5862 23:06:57.360356 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5863 23:06:57.363592 == TX Byte 1 ==
5864 23:06:57.367197 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5865 23:06:57.370630 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5866 23:06:57.370747
5867 23:06:57.373524 [DATLAT]
5868 23:06:57.373610 Freq=933, CH1 RK1
5869 23:06:57.373691
5870 23:06:57.377648 DATLAT Default: 0xb
5871 23:06:57.377735 0, 0xFFFF, sum = 0
5872 23:06:57.380247 1, 0xFFFF, sum = 0
5873 23:06:57.380335 2, 0xFFFF, sum = 0
5874 23:06:57.383568 3, 0xFFFF, sum = 0
5875 23:06:57.383670 4, 0xFFFF, sum = 0
5876 23:06:57.386510 5, 0xFFFF, sum = 0
5877 23:06:57.389969 6, 0xFFFF, sum = 0
5878 23:06:57.390059 7, 0xFFFF, sum = 0
5879 23:06:57.393335 8, 0xFFFF, sum = 0
5880 23:06:57.393424 9, 0xFFFF, sum = 0
5881 23:06:57.396638 10, 0x0, sum = 1
5882 23:06:57.396727 11, 0x0, sum = 2
5883 23:06:57.399905 12, 0x0, sum = 3
5884 23:06:57.399995 13, 0x0, sum = 4
5885 23:06:57.400063 best_step = 11
5886 23:06:57.400124
5887 23:06:57.403437 ==
5888 23:06:57.406567 Dram Type= 6, Freq= 0, CH_1, rank 1
5889 23:06:57.409843 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5890 23:06:57.409935 ==
5891 23:06:57.410002 RX Vref Scan: 0
5892 23:06:57.410064
5893 23:06:57.413431 RX Vref 0 -> 0, step: 1
5894 23:06:57.413516
5895 23:06:57.416417 RX Delay -53 -> 252, step: 4
5896 23:06:57.423195 iDelay=203, Bit 0, Center 102 (11 ~ 194) 184
5897 23:06:57.426606 iDelay=203, Bit 1, Center 94 (-1 ~ 190) 192
5898 23:06:57.429361 iDelay=203, Bit 2, Center 86 (-5 ~ 178) 184
5899 23:06:57.433126 iDelay=203, Bit 3, Center 94 (3 ~ 186) 184
5900 23:06:57.436466 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5901 23:06:57.439297 iDelay=203, Bit 5, Center 108 (15 ~ 202) 188
5902 23:06:57.446546 iDelay=203, Bit 6, Center 106 (15 ~ 198) 184
5903 23:06:57.449683 iDelay=203, Bit 7, Center 92 (-1 ~ 186) 188
5904 23:06:57.452863 iDelay=203, Bit 8, Center 80 (-9 ~ 170) 180
5905 23:06:57.456105 iDelay=203, Bit 9, Center 82 (-9 ~ 174) 184
5906 23:06:57.459200 iDelay=203, Bit 10, Center 92 (-1 ~ 186) 188
5907 23:06:57.466437 iDelay=203, Bit 11, Center 86 (-5 ~ 178) 184
5908 23:06:57.469759 iDelay=203, Bit 12, Center 102 (15 ~ 190) 176
5909 23:06:57.472251 iDelay=203, Bit 13, Center 98 (7 ~ 190) 184
5910 23:06:57.475830 iDelay=203, Bit 14, Center 96 (7 ~ 186) 180
5911 23:06:57.479016 iDelay=203, Bit 15, Center 102 (11 ~ 194) 184
5912 23:06:57.479111 ==
5913 23:06:57.482436 Dram Type= 6, Freq= 0, CH_1, rank 1
5914 23:06:57.489170 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5915 23:06:57.489287 ==
5916 23:06:57.489354 DQS Delay:
5917 23:06:57.492356 DQS0 = 0, DQS1 = 0
5918 23:06:57.492458 DQM Delay:
5919 23:06:57.492536 DQM0 = 97, DQM1 = 92
5920 23:06:57.495588 DQ Delay:
5921 23:06:57.498932 DQ0 =102, DQ1 =94, DQ2 =86, DQ3 =94
5922 23:06:57.502022 DQ4 =96, DQ5 =108, DQ6 =106, DQ7 =92
5923 23:06:57.505836 DQ8 =80, DQ9 =82, DQ10 =92, DQ11 =86
5924 23:06:57.508845 DQ12 =102, DQ13 =98, DQ14 =96, DQ15 =102
5925 23:06:57.508938
5926 23:06:57.509003
5927 23:06:57.515615 [DQSOSCAuto] RK1, (LSB)MR18= 0xd23, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 417 ps
5928 23:06:57.518909 CH1 RK1: MR19=505, MR18=D23
5929 23:06:57.525127 CH1_RK1: MR19=0x505, MR18=0xD23, DQSOSC=410, MR23=63, INC=64, DEC=42
5930 23:06:57.529190 [RxdqsGatingPostProcess] freq 933
5931 23:06:57.535927 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5932 23:06:57.536034 best DQS0 dly(2T, 0.5T) = (0, 10)
5933 23:06:57.538555 best DQS1 dly(2T, 0.5T) = (0, 10)
5934 23:06:57.542573 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5935 23:06:57.544924 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5936 23:06:57.548746 best DQS0 dly(2T, 0.5T) = (0, 10)
5937 23:06:57.551616 best DQS1 dly(2T, 0.5T) = (0, 10)
5938 23:06:57.555224 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5939 23:06:57.558352 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5940 23:06:57.561679 Pre-setting of DQS Precalculation
5941 23:06:57.567896 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5942 23:06:57.574672 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5943 23:06:57.581379 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5944 23:06:57.581498
5945 23:06:57.581595
5946 23:06:57.584773 [Calibration Summary] 1866 Mbps
5947 23:06:57.584871 CH 0, Rank 0
5948 23:06:57.587981 SW Impedance : PASS
5949 23:06:57.591109 DUTY Scan : NO K
5950 23:06:57.591206 ZQ Calibration : PASS
5951 23:06:57.594347 Jitter Meter : NO K
5952 23:06:57.597887 CBT Training : PASS
5953 23:06:57.597975 Write leveling : PASS
5954 23:06:57.601059 RX DQS gating : PASS
5955 23:06:57.604408 RX DQ/DQS(RDDQC) : PASS
5956 23:06:57.604498 TX DQ/DQS : PASS
5957 23:06:57.607614 RX DATLAT : PASS
5958 23:06:57.607698 RX DQ/DQS(Engine): PASS
5959 23:06:57.611191 TX OE : NO K
5960 23:06:57.611301 All Pass.
5961 23:06:57.611442
5962 23:06:57.614047 CH 0, Rank 1
5963 23:06:57.614129 SW Impedance : PASS
5964 23:06:57.617438 DUTY Scan : NO K
5965 23:06:57.620661 ZQ Calibration : PASS
5966 23:06:57.620750 Jitter Meter : NO K
5967 23:06:57.623983 CBT Training : PASS
5968 23:06:57.627706 Write leveling : PASS
5969 23:06:57.627796 RX DQS gating : PASS
5970 23:06:57.631100 RX DQ/DQS(RDDQC) : PASS
5971 23:06:57.633904 TX DQ/DQS : PASS
5972 23:06:57.634044 RX DATLAT : PASS
5973 23:06:57.637450 RX DQ/DQS(Engine): PASS
5974 23:06:57.640665 TX OE : NO K
5975 23:06:57.640756 All Pass.
5976 23:06:57.640820
5977 23:06:57.640880 CH 1, Rank 0
5978 23:06:57.644605 SW Impedance : PASS
5979 23:06:57.647575 DUTY Scan : NO K
5980 23:06:57.647669 ZQ Calibration : PASS
5981 23:06:57.650509 Jitter Meter : NO K
5982 23:06:57.653959 CBT Training : PASS
5983 23:06:57.654079 Write leveling : PASS
5984 23:06:57.657284 RX DQS gating : PASS
5985 23:06:57.660487 RX DQ/DQS(RDDQC) : PASS
5986 23:06:57.660578 TX DQ/DQS : PASS
5987 23:06:57.663935 RX DATLAT : PASS
5988 23:06:57.667177 RX DQ/DQS(Engine): PASS
5989 23:06:57.667269 TX OE : NO K
5990 23:06:57.670611 All Pass.
5991 23:06:57.670699
5992 23:06:57.670763 CH 1, Rank 1
5993 23:06:57.673891 SW Impedance : PASS
5994 23:06:57.673979 DUTY Scan : NO K
5995 23:06:57.676950 ZQ Calibration : PASS
5996 23:06:57.680438 Jitter Meter : NO K
5997 23:06:57.680532 CBT Training : PASS
5998 23:06:57.683517 Write leveling : PASS
5999 23:06:57.683606 RX DQS gating : PASS
6000 23:06:57.686953 RX DQ/DQS(RDDQC) : PASS
6001 23:06:57.690356 TX DQ/DQS : PASS
6002 23:06:57.690451 RX DATLAT : PASS
6003 23:06:57.693856 RX DQ/DQS(Engine): PASS
6004 23:06:57.697243 TX OE : NO K
6005 23:06:57.697341 All Pass.
6006 23:06:57.697442
6007 23:06:57.700051 DramC Write-DBI off
6008 23:06:57.703464 PER_BANK_REFRESH: Hybrid Mode
6009 23:06:57.703572 TX_TRACKING: ON
6010 23:06:57.712942 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6011 23:06:57.716287 [FAST_K] Save calibration result to emmc
6012 23:06:57.719791 dramc_set_vcore_voltage set vcore to 650000
6013 23:06:57.722700 Read voltage for 400, 6
6014 23:06:57.722794 Vio18 = 0
6015 23:06:57.722859 Vcore = 650000
6016 23:06:57.726303 Vdram = 0
6017 23:06:57.726392 Vddq = 0
6018 23:06:57.726457 Vmddr = 0
6019 23:06:57.733409 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6020 23:06:57.736226 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6021 23:06:57.739270 MEM_TYPE=3, freq_sel=20
6022 23:06:57.743063 sv_algorithm_assistance_LP4_800
6023 23:06:57.745821 ============ PULL DRAM RESETB DOWN ============
6024 23:06:57.749691 ========== PULL DRAM RESETB DOWN end =========
6025 23:06:57.755923 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6026 23:06:57.759055 ===================================
6027 23:06:57.759155 LPDDR4 DRAM CONFIGURATION
6028 23:06:57.762451 ===================================
6029 23:06:57.765729 EX_ROW_EN[0] = 0x0
6030 23:06:57.769050 EX_ROW_EN[1] = 0x0
6031 23:06:57.769143 LP4Y_EN = 0x0
6032 23:06:57.772524 WORK_FSP = 0x0
6033 23:06:57.772633 WL = 0x2
6034 23:06:57.775577 RL = 0x2
6035 23:06:57.775664 BL = 0x2
6036 23:06:57.778799 RPST = 0x0
6037 23:06:57.778885 RD_PRE = 0x0
6038 23:06:57.782442 WR_PRE = 0x1
6039 23:06:57.782535 WR_PST = 0x0
6040 23:06:57.785330 DBI_WR = 0x0
6041 23:06:57.785406 DBI_RD = 0x0
6042 23:06:57.788845 OTF = 0x1
6043 23:06:57.791904 ===================================
6044 23:06:57.795235 ===================================
6045 23:06:57.795333 ANA top config
6046 23:06:57.798923 ===================================
6047 23:06:57.801818 DLL_ASYNC_EN = 0
6048 23:06:57.805238 ALL_SLAVE_EN = 1
6049 23:06:57.808420 NEW_RANK_MODE = 1
6050 23:06:57.808516 DLL_IDLE_MODE = 1
6051 23:06:57.811926 LP45_APHY_COMB_EN = 1
6052 23:06:57.815678 TX_ODT_DIS = 1
6053 23:06:57.819294 NEW_8X_MODE = 1
6054 23:06:57.821646 ===================================
6055 23:06:57.825331 ===================================
6056 23:06:57.828837 data_rate = 800
6057 23:06:57.831594 CKR = 1
6058 23:06:57.831684 DQ_P2S_RATIO = 4
6059 23:06:57.835033 ===================================
6060 23:06:57.838074 CA_P2S_RATIO = 4
6061 23:06:57.841985 DQ_CA_OPEN = 0
6062 23:06:57.844568 DQ_SEMI_OPEN = 1
6063 23:06:57.848622 CA_SEMI_OPEN = 1
6064 23:06:57.851758 CA_FULL_RATE = 0
6065 23:06:57.851882 DQ_CKDIV4_EN = 0
6066 23:06:57.854939 CA_CKDIV4_EN = 1
6067 23:06:57.858259 CA_PREDIV_EN = 0
6068 23:06:57.861186 PH8_DLY = 0
6069 23:06:57.865054 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6070 23:06:57.867995 DQ_AAMCK_DIV = 0
6071 23:06:57.868091 CA_AAMCK_DIV = 0
6072 23:06:57.871059 CA_ADMCK_DIV = 4
6073 23:06:57.874879 DQ_TRACK_CA_EN = 0
6074 23:06:57.878588 CA_PICK = 800
6075 23:06:57.881402 CA_MCKIO = 400
6076 23:06:57.884502 MCKIO_SEMI = 400
6077 23:06:57.887656 PLL_FREQ = 3016
6078 23:06:57.891619 DQ_UI_PI_RATIO = 32
6079 23:06:57.891721 CA_UI_PI_RATIO = 32
6080 23:06:57.894274 ===================================
6081 23:06:57.897377 ===================================
6082 23:06:57.901190 memory_type:LPDDR4
6083 23:06:57.904159 GP_NUM : 10
6084 23:06:57.904258 SRAM_EN : 1
6085 23:06:57.907397 MD32_EN : 0
6086 23:06:57.910978 ===================================
6087 23:06:57.914291 [ANA_INIT] >>>>>>>>>>>>>>
6088 23:06:57.917263 <<<<<< [CONFIGURE PHASE]: ANA_TX
6089 23:06:57.920615 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6090 23:06:57.924150 ===================================
6091 23:06:57.924259 data_rate = 800,PCW = 0X7400
6092 23:06:57.927144 ===================================
6093 23:06:57.930565 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6094 23:06:57.937269 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6095 23:06:57.950211 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6096 23:06:57.953824 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6097 23:06:57.957251 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6098 23:06:57.960070 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6099 23:06:57.963990 [ANA_INIT] flow start
6100 23:06:57.964117 [ANA_INIT] PLL >>>>>>>>
6101 23:06:57.966733 [ANA_INIT] PLL <<<<<<<<
6102 23:06:57.969996 [ANA_INIT] MIDPI >>>>>>>>
6103 23:06:57.973062 [ANA_INIT] MIDPI <<<<<<<<
6104 23:06:57.973162 [ANA_INIT] DLL >>>>>>>>
6105 23:06:57.976820 [ANA_INIT] flow end
6106 23:06:57.979916 ============ LP4 DIFF to SE enter ============
6107 23:06:57.983149 ============ LP4 DIFF to SE exit ============
6108 23:06:57.986362 [ANA_INIT] <<<<<<<<<<<<<
6109 23:06:57.989642 [Flow] Enable top DCM control >>>>>
6110 23:06:57.992904 [Flow] Enable top DCM control <<<<<
6111 23:06:57.996331 Enable DLL master slave shuffle
6112 23:06:58.002984 ==============================================================
6113 23:06:58.003123 Gating Mode config
6114 23:06:58.009595 ==============================================================
6115 23:06:58.009726 Config description:
6116 23:06:58.019257 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6117 23:06:58.025911 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6118 23:06:58.032226 SELPH_MODE 0: By rank 1: By Phase
6119 23:06:58.039035 ==============================================================
6120 23:06:58.042404 GAT_TRACK_EN = 0
6121 23:06:58.042521 RX_GATING_MODE = 2
6122 23:06:58.045468 RX_GATING_TRACK_MODE = 2
6123 23:06:58.048986 SELPH_MODE = 1
6124 23:06:58.052069 PICG_EARLY_EN = 1
6125 23:06:58.055307 VALID_LAT_VALUE = 1
6126 23:06:58.061787 ==============================================================
6127 23:06:58.065019 Enter into Gating configuration >>>>
6128 23:06:58.068401 Exit from Gating configuration <<<<
6129 23:06:58.071487 Enter into DVFS_PRE_config >>>>>
6130 23:06:58.081246 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6131 23:06:58.084679 Exit from DVFS_PRE_config <<<<<
6132 23:06:58.087801 Enter into PICG configuration >>>>
6133 23:06:58.091475 Exit from PICG configuration <<<<
6134 23:06:58.094525 [RX_INPUT] configuration >>>>>
6135 23:06:58.098019 [RX_INPUT] configuration <<<<<
6136 23:06:58.101597 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6137 23:06:58.108204 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6138 23:06:58.114412 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6139 23:06:58.121070 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6140 23:06:58.127423 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6141 23:06:58.130705 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6142 23:06:58.137480 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6143 23:06:58.140940 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6144 23:06:58.143792 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6145 23:06:58.147093 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6146 23:06:58.153840 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6147 23:06:58.157105 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6148 23:06:58.160968 ===================================
6149 23:06:58.163873 LPDDR4 DRAM CONFIGURATION
6150 23:06:58.167652 ===================================
6151 23:06:58.167771 EX_ROW_EN[0] = 0x0
6152 23:06:58.170410 EX_ROW_EN[1] = 0x0
6153 23:06:58.170501 LP4Y_EN = 0x0
6154 23:06:58.173887 WORK_FSP = 0x0
6155 23:06:58.173983 WL = 0x2
6156 23:06:58.177289 RL = 0x2
6157 23:06:58.180258 BL = 0x2
6158 23:06:58.180360 RPST = 0x0
6159 23:06:58.184022 RD_PRE = 0x0
6160 23:06:58.184118 WR_PRE = 0x1
6161 23:06:58.186754 WR_PST = 0x0
6162 23:06:58.186844 DBI_WR = 0x0
6163 23:06:58.190125 DBI_RD = 0x0
6164 23:06:58.190222 OTF = 0x1
6165 23:06:58.193426 ===================================
6166 23:06:58.196482 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6167 23:06:58.203261 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6168 23:06:58.206488 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6169 23:06:58.210465 ===================================
6170 23:06:58.213573 LPDDR4 DRAM CONFIGURATION
6171 23:06:58.216579 ===================================
6172 23:06:58.216690 EX_ROW_EN[0] = 0x10
6173 23:06:58.220255 EX_ROW_EN[1] = 0x0
6174 23:06:58.220388 LP4Y_EN = 0x0
6175 23:06:58.223135 WORK_FSP = 0x0
6176 23:06:58.223253 WL = 0x2
6177 23:06:58.226397 RL = 0x2
6178 23:06:58.229862 BL = 0x2
6179 23:06:58.229972 RPST = 0x0
6180 23:06:58.232702 RD_PRE = 0x0
6181 23:06:58.232792 WR_PRE = 0x1
6182 23:06:58.235928 WR_PST = 0x0
6183 23:06:58.236024 DBI_WR = 0x0
6184 23:06:58.239416 DBI_RD = 0x0
6185 23:06:58.239511 OTF = 0x1
6186 23:06:58.243169 ===================================
6187 23:06:58.249237 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6188 23:06:58.253556 nWR fixed to 30
6189 23:06:58.257117 [ModeRegInit_LP4] CH0 RK0
6190 23:06:58.257258 [ModeRegInit_LP4] CH0 RK1
6191 23:06:58.260967 [ModeRegInit_LP4] CH1 RK0
6192 23:06:58.263280 [ModeRegInit_LP4] CH1 RK1
6193 23:06:58.263385 match AC timing 19
6194 23:06:58.269961 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6195 23:06:58.273209 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6196 23:06:58.276417 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6197 23:06:58.282944 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6198 23:06:58.286617 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6199 23:06:58.286731 ==
6200 23:06:58.289764 Dram Type= 6, Freq= 0, CH_0, rank 0
6201 23:06:58.292747 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6202 23:06:58.292847 ==
6203 23:06:58.299692 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6204 23:06:58.306159 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6205 23:06:58.309204 [CA 0] Center 36 (8~64) winsize 57
6206 23:06:58.313619 [CA 1] Center 36 (8~64) winsize 57
6207 23:06:58.316255 [CA 2] Center 36 (8~64) winsize 57
6208 23:06:58.319322 [CA 3] Center 36 (8~64) winsize 57
6209 23:06:58.322326 [CA 4] Center 36 (8~64) winsize 57
6210 23:06:58.325613 [CA 5] Center 36 (8~64) winsize 57
6211 23:06:58.325720
6212 23:06:58.329239 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6213 23:06:58.329337
6214 23:06:58.332901 [CATrainingPosCal] consider 1 rank data
6215 23:06:58.335932 u2DelayCellTimex100 = 270/100 ps
6216 23:06:58.339174 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6217 23:06:58.342539 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6218 23:06:58.346413 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6219 23:06:58.349304 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6220 23:06:58.352378 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6221 23:06:58.355608 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6222 23:06:58.355721
6223 23:06:58.362323 CA PerBit enable=1, Macro0, CA PI delay=36
6224 23:06:58.362455
6225 23:06:58.362527 [CBTSetCACLKResult] CA Dly = 36
6226 23:06:58.365799 CS Dly: 1 (0~32)
6227 23:06:58.365900 ==
6228 23:06:58.368572 Dram Type= 6, Freq= 0, CH_0, rank 1
6229 23:06:58.372310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6230 23:06:58.372421 ==
6231 23:06:58.378595 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6232 23:06:58.385283 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6233 23:06:58.388964 [CA 0] Center 36 (8~64) winsize 57
6234 23:06:58.392300 [CA 1] Center 36 (8~64) winsize 57
6235 23:06:58.395238 [CA 2] Center 36 (8~64) winsize 57
6236 23:06:58.395338 [CA 3] Center 36 (8~64) winsize 57
6237 23:06:58.399002 [CA 4] Center 36 (8~64) winsize 57
6238 23:06:58.401896 [CA 5] Center 36 (8~64) winsize 57
6239 23:06:58.402000
6240 23:06:58.408432 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6241 23:06:58.408569
6242 23:06:58.411565 [CATrainingPosCal] consider 2 rank data
6243 23:06:58.415242 u2DelayCellTimex100 = 270/100 ps
6244 23:06:58.418700 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6245 23:06:58.421442 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6246 23:06:58.425116 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6247 23:06:58.428401 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6248 23:06:58.431629 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6249 23:06:58.435121 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6250 23:06:58.435253
6251 23:06:58.438135 CA PerBit enable=1, Macro0, CA PI delay=36
6252 23:06:58.438256
6253 23:06:58.441614 [CBTSetCACLKResult] CA Dly = 36
6254 23:06:58.444813 CS Dly: 1 (0~32)
6255 23:06:58.444919
6256 23:06:58.447951 ----->DramcWriteLeveling(PI) begin...
6257 23:06:58.448068 ==
6258 23:06:58.451155 Dram Type= 6, Freq= 0, CH_0, rank 0
6259 23:06:58.454466 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6260 23:06:58.454592 ==
6261 23:06:58.457931 Write leveling (Byte 0): 40 => 8
6262 23:06:58.461693 Write leveling (Byte 1): 40 => 8
6263 23:06:58.464888 DramcWriteLeveling(PI) end<-----
6264 23:06:58.464993
6265 23:06:58.465094 ==
6266 23:06:58.467957 Dram Type= 6, Freq= 0, CH_0, rank 0
6267 23:06:58.471306 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6268 23:06:58.471464 ==
6269 23:06:58.474339 [Gating] SW mode calibration
6270 23:06:58.480789 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6271 23:06:58.487448 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6272 23:06:58.491106 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6273 23:06:58.497953 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6274 23:06:58.500528 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6275 23:06:58.504155 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6276 23:06:58.510681 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6277 23:06:58.514124 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6278 23:06:58.517463 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6279 23:06:58.523834 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6280 23:06:58.527064 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6281 23:06:58.530260 Total UI for P1: 0, mck2ui 16
6282 23:06:58.534093 best dqsien dly found for B0: ( 0, 14, 24)
6283 23:06:58.537286 Total UI for P1: 0, mck2ui 16
6284 23:06:58.540412 best dqsien dly found for B1: ( 0, 14, 24)
6285 23:06:58.543604 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6286 23:06:58.547237 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6287 23:06:58.547350
6288 23:06:58.550101 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6289 23:06:58.553572 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6290 23:06:58.557206 [Gating] SW calibration Done
6291 23:06:58.557319 ==
6292 23:06:58.560870 Dram Type= 6, Freq= 0, CH_0, rank 0
6293 23:06:58.563703 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6294 23:06:58.566948 ==
6295 23:06:58.567068 RX Vref Scan: 0
6296 23:06:58.567138
6297 23:06:58.569941 RX Vref 0 -> 0, step: 1
6298 23:06:58.570040
6299 23:06:58.573428 RX Delay -410 -> 252, step: 16
6300 23:06:58.576446 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6301 23:06:58.579693 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6302 23:06:58.583102 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6303 23:06:58.589764 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6304 23:06:58.593130 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6305 23:06:58.596404 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6306 23:06:58.599941 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6307 23:06:58.606471 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6308 23:06:58.610131 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6309 23:06:58.613173 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6310 23:06:58.619658 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6311 23:06:58.623483 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6312 23:06:58.626587 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6313 23:06:58.629642 iDelay=230, Bit 13, Center -27 (-266 ~ 213) 480
6314 23:06:58.636197 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6315 23:06:58.639218 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6316 23:06:58.639332 ==
6317 23:06:58.643287 Dram Type= 6, Freq= 0, CH_0, rank 0
6318 23:06:58.645943 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6319 23:06:58.646075 ==
6320 23:06:58.648964 DQS Delay:
6321 23:06:58.649073 DQS0 = 35, DQS1 = 51
6322 23:06:58.652659 DQM Delay:
6323 23:06:58.652759 DQM0 = 7, DQM1 = 12
6324 23:06:58.652827 DQ Delay:
6325 23:06:58.655372 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =0
6326 23:06:58.659316 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6327 23:06:58.662069 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6328 23:06:58.665354 DQ12 =16, DQ13 =24, DQ14 =24, DQ15 =16
6329 23:06:58.665485
6330 23:06:58.665579
6331 23:06:58.665668 ==
6332 23:06:58.668733 Dram Type= 6, Freq= 0, CH_0, rank 0
6333 23:06:58.675705 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6334 23:06:58.675875 ==
6335 23:06:58.675971
6336 23:06:58.676059
6337 23:06:58.676122 TX Vref Scan disable
6338 23:06:58.678792 == TX Byte 0 ==
6339 23:06:58.682099 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6340 23:06:58.685203 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6341 23:06:58.688279 == TX Byte 1 ==
6342 23:06:58.692272 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6343 23:06:58.694956 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6344 23:06:58.698300 ==
6345 23:06:58.698434 Dram Type= 6, Freq= 0, CH_0, rank 0
6346 23:06:58.704898 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6347 23:06:58.705055 ==
6348 23:06:58.705170
6349 23:06:58.705234
6350 23:06:58.708011 TX Vref Scan disable
6351 23:06:58.708113 == TX Byte 0 ==
6352 23:06:58.711743 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6353 23:06:58.718109 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6354 23:06:58.718283 == TX Byte 1 ==
6355 23:06:58.721112 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6356 23:06:58.728406 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6357 23:06:58.728554
6358 23:06:58.728626 [DATLAT]
6359 23:06:58.728688 Freq=400, CH0 RK0
6360 23:06:58.728748
6361 23:06:58.731982 DATLAT Default: 0xf
6362 23:06:58.732094 0, 0xFFFF, sum = 0
6363 23:06:58.734676 1, 0xFFFF, sum = 0
6364 23:06:58.737827 2, 0xFFFF, sum = 0
6365 23:06:58.737947 3, 0xFFFF, sum = 0
6366 23:06:58.741687 4, 0xFFFF, sum = 0
6367 23:06:58.741802 5, 0xFFFF, sum = 0
6368 23:06:58.744426 6, 0xFFFF, sum = 0
6369 23:06:58.744530 7, 0xFFFF, sum = 0
6370 23:06:58.747818 8, 0xFFFF, sum = 0
6371 23:06:58.747929 9, 0xFFFF, sum = 0
6372 23:06:58.751480 10, 0xFFFF, sum = 0
6373 23:06:58.751634 11, 0xFFFF, sum = 0
6374 23:06:58.754104 12, 0xFFFF, sum = 0
6375 23:06:58.754194 13, 0x0, sum = 1
6376 23:06:58.757806 14, 0x0, sum = 2
6377 23:06:58.757920 15, 0x0, sum = 3
6378 23:06:58.761018 16, 0x0, sum = 4
6379 23:06:58.761130 best_step = 14
6380 23:06:58.761199
6381 23:06:58.761260 ==
6382 23:06:58.763933 Dram Type= 6, Freq= 0, CH_0, rank 0
6383 23:06:58.770525 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6384 23:06:58.770670 ==
6385 23:06:58.770740 RX Vref Scan: 1
6386 23:06:58.770800
6387 23:06:58.774217 RX Vref 0 -> 0, step: 1
6388 23:06:58.774327
6389 23:06:58.777421 RX Delay -343 -> 252, step: 8
6390 23:06:58.777539
6391 23:06:58.780357 Set Vref, RX VrefLevel [Byte0]: 52
6392 23:06:58.783838 [Byte1]: 50
6393 23:06:58.783991
6394 23:06:58.787076 Final RX Vref Byte 0 = 52 to rank0
6395 23:06:58.790231 Final RX Vref Byte 1 = 50 to rank0
6396 23:06:58.793947 Final RX Vref Byte 0 = 52 to rank1
6397 23:06:58.796826 Final RX Vref Byte 1 = 50 to rank1==
6398 23:06:58.799985 Dram Type= 6, Freq= 0, CH_0, rank 0
6399 23:06:58.803292 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6400 23:06:58.806658 ==
6401 23:06:58.806785 DQS Delay:
6402 23:06:58.806855 DQS0 = 44, DQS1 = 60
6403 23:06:58.810509 DQM Delay:
6404 23:06:58.810663 DQM0 = 10, DQM1 = 17
6405 23:06:58.813296 DQ Delay:
6406 23:06:58.817014 DQ0 =12, DQ1 =12, DQ2 =4, DQ3 =4
6407 23:06:58.817160 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6408 23:06:58.819982 DQ8 =8, DQ9 =0, DQ10 =20, DQ11 =12
6409 23:06:58.823224 DQ12 =24, DQ13 =20, DQ14 =28, DQ15 =24
6410 23:06:58.826923
6411 23:06:58.827052
6412 23:06:58.833411 [DQSOSCAuto] RK0, (LSB)MR18= 0x9083, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 391 ps
6413 23:06:58.836441 CH0 RK0: MR19=C0C, MR18=9083
6414 23:06:58.843051 CH0_RK0: MR19=0xC0C, MR18=0x9083, DQSOSC=391, MR23=63, INC=386, DEC=257
6415 23:06:58.843201 ==
6416 23:06:58.846279 Dram Type= 6, Freq= 0, CH_0, rank 1
6417 23:06:58.850073 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6418 23:06:58.850196 ==
6419 23:06:58.853154 [Gating] SW mode calibration
6420 23:06:58.859665 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6421 23:06:58.866371 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6422 23:06:58.869654 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6423 23:06:58.872547 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6424 23:06:58.879855 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6425 23:06:58.883120 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6426 23:06:58.885951 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6427 23:06:58.892386 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6428 23:06:58.895878 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6429 23:06:58.899207 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6430 23:06:58.905647 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6431 23:06:58.905796 Total UI for P1: 0, mck2ui 16
6432 23:06:58.912188 best dqsien dly found for B0: ( 0, 14, 24)
6433 23:06:58.912328 Total UI for P1: 0, mck2ui 16
6434 23:06:58.918849 best dqsien dly found for B1: ( 0, 14, 24)
6435 23:06:58.922072 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6436 23:06:58.925359 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6437 23:06:58.925471
6438 23:06:58.928632 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6439 23:06:58.931980 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6440 23:06:58.935182 [Gating] SW calibration Done
6441 23:06:58.935290 ==
6442 23:06:58.938798 Dram Type= 6, Freq= 0, CH_0, rank 1
6443 23:06:58.941651 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6444 23:06:58.941757 ==
6445 23:06:58.945128 RX Vref Scan: 0
6446 23:06:58.945225
6447 23:06:58.948618 RX Vref 0 -> 0, step: 1
6448 23:06:58.948721
6449 23:06:58.948790 RX Delay -410 -> 252, step: 16
6450 23:06:58.955130 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6451 23:06:58.958334 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6452 23:06:58.961989 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6453 23:06:58.965478 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6454 23:06:58.971828 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6455 23:06:58.975110 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6456 23:06:58.978675 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6457 23:06:58.981672 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6458 23:06:58.988341 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6459 23:06:58.991458 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6460 23:06:58.994820 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6461 23:06:59.001375 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6462 23:06:59.004643 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6463 23:06:59.007786 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6464 23:06:59.011188 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6465 23:06:59.018088 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6466 23:06:59.018270 ==
6467 23:06:59.021777 Dram Type= 6, Freq= 0, CH_0, rank 1
6468 23:06:59.024311 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6469 23:06:59.024441 ==
6470 23:06:59.024543 DQS Delay:
6471 23:06:59.028285 DQS0 = 35, DQS1 = 59
6472 23:06:59.028427 DQM Delay:
6473 23:06:59.031521 DQM0 = 6, DQM1 = 17
6474 23:06:59.031649 DQ Delay:
6475 23:06:59.034910 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =0
6476 23:06:59.037699 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6477 23:06:59.040682 DQ8 =8, DQ9 =0, DQ10 =24, DQ11 =8
6478 23:06:59.044045 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6479 23:06:59.044203
6480 23:06:59.044309
6481 23:06:59.044404 ==
6482 23:06:59.047533 Dram Type= 6, Freq= 0, CH_0, rank 1
6483 23:06:59.050556 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6484 23:06:59.050687 ==
6485 23:06:59.050788
6486 23:06:59.050879
6487 23:06:59.054487 TX Vref Scan disable
6488 23:06:59.057257 == TX Byte 0 ==
6489 23:06:59.060488 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6490 23:06:59.063717 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6491 23:06:59.067302 == TX Byte 1 ==
6492 23:06:59.070724 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6493 23:06:59.076207 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6494 23:06:59.076374 ==
6495 23:06:59.077349 Dram Type= 6, Freq= 0, CH_0, rank 1
6496 23:06:59.080331 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6497 23:06:59.080469 ==
6498 23:06:59.083764
6499 23:06:59.083893
6500 23:06:59.083995 TX Vref Scan disable
6501 23:06:59.087081 == TX Byte 0 ==
6502 23:06:59.090510 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6503 23:06:59.093770 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6504 23:06:59.097173 == TX Byte 1 ==
6505 23:06:59.100440 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6506 23:06:59.103894 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6507 23:06:59.104011
6508 23:06:59.104078 [DATLAT]
6509 23:06:59.106958 Freq=400, CH0 RK1
6510 23:06:59.107052
6511 23:06:59.110003 DATLAT Default: 0xe
6512 23:06:59.110101 0, 0xFFFF, sum = 0
6513 23:06:59.113147 1, 0xFFFF, sum = 0
6514 23:06:59.113239 2, 0xFFFF, sum = 0
6515 23:06:59.116768 3, 0xFFFF, sum = 0
6516 23:06:59.116874 4, 0xFFFF, sum = 0
6517 23:06:59.119895 5, 0xFFFF, sum = 0
6518 23:06:59.120031 6, 0xFFFF, sum = 0
6519 23:06:59.123195 7, 0xFFFF, sum = 0
6520 23:06:59.123331 8, 0xFFFF, sum = 0
6521 23:06:59.126624 9, 0xFFFF, sum = 0
6522 23:06:59.126756 10, 0xFFFF, sum = 0
6523 23:06:59.129879 11, 0xFFFF, sum = 0
6524 23:06:59.130009 12, 0xFFFF, sum = 0
6525 23:06:59.133441 13, 0x0, sum = 1
6526 23:06:59.133568 14, 0x0, sum = 2
6527 23:06:59.136285 15, 0x0, sum = 3
6528 23:06:59.136406 16, 0x0, sum = 4
6529 23:06:59.139679 best_step = 14
6530 23:06:59.139811
6531 23:06:59.139911 ==
6532 23:06:59.143200 Dram Type= 6, Freq= 0, CH_0, rank 1
6533 23:06:59.146570 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6534 23:06:59.146711 ==
6535 23:06:59.149519 RX Vref Scan: 0
6536 23:06:59.149639
6537 23:06:59.149736 RX Vref 0 -> 0, step: 1
6538 23:06:59.149828
6539 23:06:59.152441 RX Delay -359 -> 252, step: 8
6540 23:06:59.160951 iDelay=209, Bit 0, Center -36 (-271 ~ 200) 472
6541 23:06:59.164511 iDelay=209, Bit 1, Center -32 (-271 ~ 208) 480
6542 23:06:59.167489 iDelay=209, Bit 2, Center -40 (-279 ~ 200) 480
6543 23:06:59.174606 iDelay=209, Bit 3, Center -40 (-279 ~ 200) 480
6544 23:06:59.177773 iDelay=209, Bit 4, Center -32 (-271 ~ 208) 480
6545 23:06:59.181353 iDelay=209, Bit 5, Center -44 (-279 ~ 192) 472
6546 23:06:59.184689 iDelay=209, Bit 6, Center -28 (-263 ~ 208) 472
6547 23:06:59.191075 iDelay=209, Bit 7, Center -28 (-263 ~ 208) 472
6548 23:06:59.194344 iDelay=209, Bit 8, Center -56 (-303 ~ 192) 496
6549 23:06:59.197152 iDelay=209, Bit 9, Center -60 (-303 ~ 184) 488
6550 23:06:59.200701 iDelay=209, Bit 10, Center -44 (-287 ~ 200) 488
6551 23:06:59.207157 iDelay=209, Bit 11, Center -48 (-287 ~ 192) 480
6552 23:06:59.210728 iDelay=209, Bit 12, Center -40 (-279 ~ 200) 480
6553 23:06:59.213835 iDelay=209, Bit 13, Center -40 (-279 ~ 200) 480
6554 23:06:59.217240 iDelay=209, Bit 14, Center -36 (-279 ~ 208) 488
6555 23:06:59.224076 iDelay=209, Bit 15, Center -40 (-279 ~ 200) 480
6556 23:06:59.224215 ==
6557 23:06:59.226898 Dram Type= 6, Freq= 0, CH_0, rank 1
6558 23:06:59.230949 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6559 23:06:59.231080 ==
6560 23:06:59.231174 DQS Delay:
6561 23:06:59.233829 DQS0 = 44, DQS1 = 60
6562 23:06:59.233925 DQM Delay:
6563 23:06:59.237232 DQM0 = 9, DQM1 = 14
6564 23:06:59.237339 DQ Delay:
6565 23:06:59.240707 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =4
6566 23:06:59.243762 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =16
6567 23:06:59.247014 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =12
6568 23:06:59.250197 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6569 23:06:59.250303
6570 23:06:59.250392
6571 23:06:59.260097 [DQSOSCAuto] RK1, (LSB)MR18= 0x9088, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 391 ps
6572 23:06:59.260252 CH0 RK1: MR19=C0C, MR18=9088
6573 23:06:59.266319 CH0_RK1: MR19=0xC0C, MR18=0x9088, DQSOSC=391, MR23=63, INC=386, DEC=257
6574 23:06:59.269953 [RxdqsGatingPostProcess] freq 400
6575 23:06:59.276552 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6576 23:06:59.279666 best DQS0 dly(2T, 0.5T) = (0, 10)
6577 23:06:59.282757 best DQS1 dly(2T, 0.5T) = (0, 10)
6578 23:06:59.286084 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6579 23:06:59.289251 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6580 23:06:59.293103 best DQS0 dly(2T, 0.5T) = (0, 10)
6581 23:06:59.293239 best DQS1 dly(2T, 0.5T) = (0, 10)
6582 23:06:59.295900 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6583 23:06:59.299761 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6584 23:06:59.303325 Pre-setting of DQS Precalculation
6585 23:06:59.309215 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6586 23:06:59.309352 ==
6587 23:06:59.312556 Dram Type= 6, Freq= 0, CH_1, rank 0
6588 23:06:59.316082 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6589 23:06:59.316186 ==
6590 23:06:59.322492 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6591 23:06:59.329134 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6592 23:06:59.332514 [CA 0] Center 36 (8~64) winsize 57
6593 23:06:59.335725 [CA 1] Center 36 (8~64) winsize 57
6594 23:06:59.338999 [CA 2] Center 36 (8~64) winsize 57
6595 23:06:59.342101 [CA 3] Center 36 (8~64) winsize 57
6596 23:06:59.342181 [CA 4] Center 36 (8~64) winsize 57
6597 23:06:59.345365 [CA 5] Center 36 (8~64) winsize 57
6598 23:06:59.345447
6599 23:06:59.352119 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6600 23:06:59.352211
6601 23:06:59.355180 [CATrainingPosCal] consider 1 rank data
6602 23:06:59.358740 u2DelayCellTimex100 = 270/100 ps
6603 23:06:59.362147 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6604 23:06:59.365169 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6605 23:06:59.368536 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6606 23:06:59.371766 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6607 23:06:59.375117 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6608 23:06:59.378438 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6609 23:06:59.378531
6610 23:06:59.381401 CA PerBit enable=1, Macro0, CA PI delay=36
6611 23:06:59.381497
6612 23:06:59.384959 [CBTSetCACLKResult] CA Dly = 36
6613 23:06:59.388036 CS Dly: 1 (0~32)
6614 23:06:59.388141 ==
6615 23:06:59.391316 Dram Type= 6, Freq= 0, CH_1, rank 1
6616 23:06:59.395050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6617 23:06:59.395186 ==
6618 23:06:59.401354 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6619 23:06:59.408344 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6620 23:06:59.411307 [CA 0] Center 36 (8~64) winsize 57
6621 23:06:59.414501 [CA 1] Center 36 (8~64) winsize 57
6622 23:06:59.417901 [CA 2] Center 36 (8~64) winsize 57
6623 23:06:59.418046 [CA 3] Center 36 (8~64) winsize 57
6624 23:06:59.420960 [CA 4] Center 36 (8~64) winsize 57
6625 23:06:59.424387 [CA 5] Center 36 (8~64) winsize 57
6626 23:06:59.424506
6627 23:06:59.430907 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6628 23:06:59.431042
6629 23:06:59.434533 [CATrainingPosCal] consider 2 rank data
6630 23:06:59.437688 u2DelayCellTimex100 = 270/100 ps
6631 23:06:59.440769 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6632 23:06:59.444000 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6633 23:06:59.447314 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6634 23:06:59.450715 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6635 23:06:59.453746 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6636 23:06:59.457874 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6637 23:06:59.457994
6638 23:06:59.461296 CA PerBit enable=1, Macro0, CA PI delay=36
6639 23:06:59.461411
6640 23:06:59.464184 [CBTSetCACLKResult] CA Dly = 36
6641 23:06:59.467252 CS Dly: 1 (0~32)
6642 23:06:59.467386
6643 23:06:59.470463 ----->DramcWriteLeveling(PI) begin...
6644 23:06:59.470575 ==
6645 23:06:59.473951 Dram Type= 6, Freq= 0, CH_1, rank 0
6646 23:06:59.477320 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6647 23:06:59.477435 ==
6648 23:06:59.480221 Write leveling (Byte 0): 40 => 8
6649 23:06:59.484592 Write leveling (Byte 1): 40 => 8
6650 23:06:59.487964 DramcWriteLeveling(PI) end<-----
6651 23:06:59.488081
6652 23:06:59.488176 ==
6653 23:06:59.490272 Dram Type= 6, Freq= 0, CH_1, rank 0
6654 23:06:59.493498 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6655 23:06:59.493609 ==
6656 23:06:59.497053 [Gating] SW mode calibration
6657 23:06:59.503579 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6658 23:06:59.510039 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6659 23:06:59.513474 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6660 23:06:59.520026 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6661 23:06:59.523170 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6662 23:06:59.526737 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6663 23:06:59.533300 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6664 23:06:59.536437 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6665 23:06:59.540049 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6666 23:06:59.546155 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6667 23:06:59.549429 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6668 23:06:59.553187 Total UI for P1: 0, mck2ui 16
6669 23:06:59.555980 best dqsien dly found for B0: ( 0, 14, 24)
6670 23:06:59.559481 Total UI for P1: 0, mck2ui 16
6671 23:06:59.562769 best dqsien dly found for B1: ( 0, 14, 24)
6672 23:06:59.566119 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6673 23:06:59.569735 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6674 23:06:59.569864
6675 23:06:59.572515 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6676 23:06:59.576160 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6677 23:06:59.579453 [Gating] SW calibration Done
6678 23:06:59.579573 ==
6679 23:06:59.582750 Dram Type= 6, Freq= 0, CH_1, rank 0
6680 23:06:59.589109 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6681 23:06:59.589232 ==
6682 23:06:59.589336 RX Vref Scan: 0
6683 23:06:59.589429
6684 23:06:59.592565 RX Vref 0 -> 0, step: 1
6685 23:06:59.592671
6686 23:06:59.595808 RX Delay -410 -> 252, step: 16
6687 23:06:59.598996 iDelay=230, Bit 0, Center -19 (-266 ~ 229) 496
6688 23:06:59.602134 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6689 23:06:59.609103 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6690 23:06:59.611954 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6691 23:06:59.615596 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6692 23:06:59.619101 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6693 23:06:59.625599 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6694 23:06:59.628999 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6695 23:06:59.632047 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6696 23:06:59.635665 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6697 23:06:59.642367 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6698 23:06:59.645032 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6699 23:06:59.648517 iDelay=230, Bit 12, Center -19 (-266 ~ 229) 496
6700 23:06:59.651634 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6701 23:06:59.658759 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6702 23:06:59.661977 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6703 23:06:59.662108 ==
6704 23:06:59.665426 Dram Type= 6, Freq= 0, CH_1, rank 0
6705 23:06:59.668687 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6706 23:06:59.668807 ==
6707 23:06:59.671256 DQS Delay:
6708 23:06:59.671390 DQS0 = 35, DQS1 = 51
6709 23:06:59.674608 DQM Delay:
6710 23:06:59.674720 DQM0 = 6, DQM1 = 14
6711 23:06:59.674813 DQ Delay:
6712 23:06:59.678085 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6713 23:06:59.681443 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6714 23:06:59.685330 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6715 23:06:59.687917 DQ12 =32, DQ13 =24, DQ14 =16, DQ15 =16
6716 23:06:59.688031
6717 23:06:59.688122
6718 23:06:59.688210 ==
6719 23:06:59.691248 Dram Type= 6, Freq= 0, CH_1, rank 0
6720 23:06:59.697869 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6721 23:06:59.697986 ==
6722 23:06:59.698077
6723 23:06:59.698165
6724 23:06:59.698252 TX Vref Scan disable
6725 23:06:59.701103 == TX Byte 0 ==
6726 23:06:59.704448 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6727 23:06:59.707969 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6728 23:06:59.711505 == TX Byte 1 ==
6729 23:06:59.714172 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6730 23:06:59.717524 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6731 23:06:59.717638 ==
6732 23:06:59.721076 Dram Type= 6, Freq= 0, CH_1, rank 0
6733 23:06:59.727399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6734 23:06:59.727531 ==
6735 23:06:59.727629
6736 23:06:59.727718
6737 23:06:59.727805 TX Vref Scan disable
6738 23:06:59.731045 == TX Byte 0 ==
6739 23:06:59.734644 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6740 23:06:59.737917 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6741 23:06:59.741298 == TX Byte 1 ==
6742 23:06:59.744071 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6743 23:06:59.747893 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6744 23:06:59.748012
6745 23:06:59.751100 [DATLAT]
6746 23:06:59.751206 Freq=400, CH1 RK0
6747 23:06:59.751324
6748 23:06:59.753938 DATLAT Default: 0xf
6749 23:06:59.754040 0, 0xFFFF, sum = 0
6750 23:06:59.757263 1, 0xFFFF, sum = 0
6751 23:06:59.757375 2, 0xFFFF, sum = 0
6752 23:06:59.761009 3, 0xFFFF, sum = 0
6753 23:06:59.761119 4, 0xFFFF, sum = 0
6754 23:06:59.764008 5, 0xFFFF, sum = 0
6755 23:06:59.764116 6, 0xFFFF, sum = 0
6756 23:06:59.767481 7, 0xFFFF, sum = 0
6757 23:06:59.770517 8, 0xFFFF, sum = 0
6758 23:06:59.770661 9, 0xFFFF, sum = 0
6759 23:06:59.774108 10, 0xFFFF, sum = 0
6760 23:06:59.774217 11, 0xFFFF, sum = 0
6761 23:06:59.777252 12, 0xFFFF, sum = 0
6762 23:06:59.777362 13, 0x0, sum = 1
6763 23:06:59.780304 14, 0x0, sum = 2
6764 23:06:59.780414 15, 0x0, sum = 3
6765 23:06:59.783621 16, 0x0, sum = 4
6766 23:06:59.783728 best_step = 14
6767 23:06:59.783851
6768 23:06:59.783938 ==
6769 23:06:59.786858 Dram Type= 6, Freq= 0, CH_1, rank 0
6770 23:06:59.791003 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6771 23:06:59.791116 ==
6772 23:06:59.793919 RX Vref Scan: 1
6773 23:06:59.794054
6774 23:06:59.797175 RX Vref 0 -> 0, step: 1
6775 23:06:59.797282
6776 23:06:59.800459 RX Delay -343 -> 252, step: 8
6777 23:06:59.800568
6778 23:06:59.803359 Set Vref, RX VrefLevel [Byte0]: 51
6779 23:06:59.806869 [Byte1]: 51
6780 23:06:59.806978
6781 23:06:59.810027 Final RX Vref Byte 0 = 51 to rank0
6782 23:06:59.813177 Final RX Vref Byte 1 = 51 to rank0
6783 23:06:59.816714 Final RX Vref Byte 0 = 51 to rank1
6784 23:06:59.820273 Final RX Vref Byte 1 = 51 to rank1==
6785 23:06:59.823251 Dram Type= 6, Freq= 0, CH_1, rank 0
6786 23:06:59.826747 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6787 23:06:59.826858 ==
6788 23:06:59.830393 DQS Delay:
6789 23:06:59.830507 DQS0 = 44, DQS1 = 52
6790 23:06:59.833356 DQM Delay:
6791 23:06:59.833494 DQM0 = 10, DQM1 = 11
6792 23:06:59.836380 DQ Delay:
6793 23:06:59.836490 DQ0 =20, DQ1 =4, DQ2 =0, DQ3 =12
6794 23:06:59.840293 DQ4 =4, DQ5 =16, DQ6 =20, DQ7 =4
6795 23:06:59.843470 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =8
6796 23:06:59.846347 DQ12 =20, DQ13 =20, DQ14 =16, DQ15 =16
6797 23:06:59.846460
6798 23:06:59.846554
6799 23:06:59.856166 [DQSOSCAuto] RK0, (LSB)MR18= 0x6f96, (MSB)MR19= 0xc0c, tDQSOscB0 = 391 ps tDQSOscB1 = 395 ps
6800 23:06:59.859614 CH1 RK0: MR19=C0C, MR18=6F96
6801 23:06:59.862956 CH1_RK0: MR19=0xC0C, MR18=0x6F96, DQSOSC=391, MR23=63, INC=386, DEC=257
6802 23:06:59.866440 ==
6803 23:06:59.869480 Dram Type= 6, Freq= 0, CH_1, rank 1
6804 23:06:59.873227 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6805 23:06:59.873341 ==
6806 23:06:59.877126 [Gating] SW mode calibration
6807 23:06:59.882565 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6808 23:06:59.886290 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6809 23:06:59.892692 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6810 23:06:59.896407 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6811 23:06:59.899341 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6812 23:06:59.905999 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6813 23:06:59.909195 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6814 23:06:59.912465 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6815 23:06:59.919881 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6816 23:06:59.922425 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6817 23:06:59.925581 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6818 23:06:59.928866 Total UI for P1: 0, mck2ui 16
6819 23:06:59.932591 best dqsien dly found for B0: ( 0, 14, 24)
6820 23:06:59.935758 Total UI for P1: 0, mck2ui 16
6821 23:06:59.938742 best dqsien dly found for B1: ( 0, 14, 24)
6822 23:06:59.942017 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6823 23:06:59.946129 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6824 23:06:59.948658
6825 23:06:59.952054 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6826 23:06:59.955171 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6827 23:06:59.958519 [Gating] SW calibration Done
6828 23:06:59.958637 ==
6829 23:06:59.961886 Dram Type= 6, Freq= 0, CH_1, rank 1
6830 23:06:59.965533 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6831 23:06:59.965659 ==
6832 23:06:59.965758 RX Vref Scan: 0
6833 23:06:59.968542
6834 23:06:59.968653 RX Vref 0 -> 0, step: 1
6835 23:06:59.968747
6836 23:06:59.972118 RX Delay -410 -> 252, step: 16
6837 23:06:59.975075 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6838 23:06:59.981489 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6839 23:06:59.985271 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6840 23:06:59.988107 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6841 23:06:59.991324 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6842 23:06:59.998031 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6843 23:07:00.001545 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6844 23:07:00.004676 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6845 23:07:00.008229 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6846 23:07:00.014422 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6847 23:07:00.017919 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6848 23:07:00.021201 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6849 23:07:00.027772 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6850 23:07:00.031110 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6851 23:07:00.034261 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6852 23:07:00.037586 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6853 23:07:00.040906 ==
6854 23:07:00.044177 Dram Type= 6, Freq= 0, CH_1, rank 1
6855 23:07:00.047512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6856 23:07:00.047632 ==
6857 23:07:00.047729 DQS Delay:
6858 23:07:00.050783 DQS0 = 43, DQS1 = 51
6859 23:07:00.050895 DQM Delay:
6860 23:07:00.055640 DQM0 = 9, DQM1 = 14
6861 23:07:00.055765 DQ Delay:
6862 23:07:00.057817 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6863 23:07:00.060488 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6864 23:07:00.063890 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6865 23:07:00.067585 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =24
6866 23:07:00.067701
6867 23:07:00.067795
6868 23:07:00.067888 ==
6869 23:07:00.070791 Dram Type= 6, Freq= 0, CH_1, rank 1
6870 23:07:00.073775 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6871 23:07:00.073889 ==
6872 23:07:00.073986
6873 23:07:00.074079
6874 23:07:00.077031 TX Vref Scan disable
6875 23:07:00.077142 == TX Byte 0 ==
6876 23:07:00.084025 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6877 23:07:00.087182 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6878 23:07:00.087302 == TX Byte 1 ==
6879 23:07:00.093410 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6880 23:07:00.097126 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6881 23:07:00.097252 ==
6882 23:07:00.099966 Dram Type= 6, Freq= 0, CH_1, rank 1
6883 23:07:00.103579 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6884 23:07:00.103692 ==
6885 23:07:00.103786
6886 23:07:00.103875
6887 23:07:00.107003 TX Vref Scan disable
6888 23:07:00.107130 == TX Byte 0 ==
6889 23:07:00.113276 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6890 23:07:00.117166 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6891 23:07:00.117285 == TX Byte 1 ==
6892 23:07:00.123523 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6893 23:07:00.126519 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6894 23:07:00.126638
6895 23:07:00.126731 [DATLAT]
6896 23:07:00.130104 Freq=400, CH1 RK1
6897 23:07:00.130214
6898 23:07:00.130309 DATLAT Default: 0xe
6899 23:07:00.133499 0, 0xFFFF, sum = 0
6900 23:07:00.133608 1, 0xFFFF, sum = 0
6901 23:07:00.136681 2, 0xFFFF, sum = 0
6902 23:07:00.136789 3, 0xFFFF, sum = 0
6903 23:07:00.139720 4, 0xFFFF, sum = 0
6904 23:07:00.139829 5, 0xFFFF, sum = 0
6905 23:07:00.143059 6, 0xFFFF, sum = 0
6906 23:07:00.143167 7, 0xFFFF, sum = 0
6907 23:07:00.146479 8, 0xFFFF, sum = 0
6908 23:07:00.149916 9, 0xFFFF, sum = 0
6909 23:07:00.150030 10, 0xFFFF, sum = 0
6910 23:07:00.153214 11, 0xFFFF, sum = 0
6911 23:07:00.153327 12, 0xFFFF, sum = 0
6912 23:07:00.156173 13, 0x0, sum = 1
6913 23:07:00.156282 14, 0x0, sum = 2
6914 23:07:00.159500 15, 0x0, sum = 3
6915 23:07:00.159612 16, 0x0, sum = 4
6916 23:07:00.159707 best_step = 14
6917 23:07:00.163322
6918 23:07:00.163467 ==
6919 23:07:00.166729 Dram Type= 6, Freq= 0, CH_1, rank 1
6920 23:07:00.169571 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6921 23:07:00.169683 ==
6922 23:07:00.169776 RX Vref Scan: 0
6923 23:07:00.169866
6924 23:07:00.173080 RX Vref 0 -> 0, step: 1
6925 23:07:00.173190
6926 23:07:00.176260 RX Delay -343 -> 252, step: 8
6927 23:07:00.183105 iDelay=217, Bit 0, Center -32 (-271 ~ 208) 480
6928 23:07:00.186990 iDelay=217, Bit 1, Center -40 (-287 ~ 208) 496
6929 23:07:00.189942 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
6930 23:07:00.196274 iDelay=217, Bit 3, Center -40 (-287 ~ 208) 496
6931 23:07:00.199686 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6932 23:07:00.202775 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6933 23:07:00.206300 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6934 23:07:00.212527 iDelay=217, Bit 7, Center -40 (-287 ~ 208) 496
6935 23:07:00.215883 iDelay=217, Bit 8, Center -52 (-295 ~ 192) 488
6936 23:07:00.219118 iDelay=217, Bit 9, Center -52 (-295 ~ 192) 488
6937 23:07:00.222464 iDelay=217, Bit 10, Center -40 (-287 ~ 208) 496
6938 23:07:00.229317 iDelay=217, Bit 11, Center -48 (-287 ~ 192) 480
6939 23:07:00.232512 iDelay=217, Bit 12, Center -32 (-271 ~ 208) 480
6940 23:07:00.235650 iDelay=217, Bit 13, Center -36 (-279 ~ 208) 488
6941 23:07:00.242459 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6942 23:07:00.245541 iDelay=217, Bit 15, Center -32 (-279 ~ 216) 496
6943 23:07:00.245632 ==
6944 23:07:00.249688 Dram Type= 6, Freq= 0, CH_1, rank 1
6945 23:07:00.252377 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6946 23:07:00.252463 ==
6947 23:07:00.255978 DQS Delay:
6948 23:07:00.256080 DQS0 = 48, DQS1 = 52
6949 23:07:00.256147 DQM Delay:
6950 23:07:00.258597 DQM0 = 11, DQM1 = 11
6951 23:07:00.258680 DQ Delay:
6952 23:07:00.262356 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6953 23:07:00.265414 DQ4 =12, DQ5 =20, DQ6 =20, DQ7 =8
6954 23:07:00.268947 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6955 23:07:00.272298 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =20
6956 23:07:00.272417
6957 23:07:00.272510
6958 23:07:00.281865 [DQSOSCAuto] RK1, (LSB)MR18= 0x7ab3, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 394 ps
6959 23:07:00.282022 CH1 RK1: MR19=C0C, MR18=7AB3
6960 23:07:00.288549 CH1_RK1: MR19=0xC0C, MR18=0x7AB3, DQSOSC=387, MR23=63, INC=394, DEC=262
6961 23:07:00.291985 [RxdqsGatingPostProcess] freq 400
6962 23:07:00.298373 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6963 23:07:00.301686 best DQS0 dly(2T, 0.5T) = (0, 10)
6964 23:07:00.305007 best DQS1 dly(2T, 0.5T) = (0, 10)
6965 23:07:00.308161 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6966 23:07:00.311870 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6967 23:07:00.315427 best DQS0 dly(2T, 0.5T) = (0, 10)
6968 23:07:00.318120 best DQS1 dly(2T, 0.5T) = (0, 10)
6969 23:07:00.321987 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6970 23:07:00.324865 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6971 23:07:00.324964 Pre-setting of DQS Precalculation
6972 23:07:00.331290 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6973 23:07:00.337744 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6974 23:07:00.344223 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6975 23:07:00.344358
6976 23:07:00.344433
6977 23:07:00.348154 [Calibration Summary] 800 Mbps
6978 23:07:00.351194 CH 0, Rank 0
6979 23:07:00.351306 SW Impedance : PASS
6980 23:07:00.354158 DUTY Scan : NO K
6981 23:07:00.357498 ZQ Calibration : PASS
6982 23:07:00.357605 Jitter Meter : NO K
6983 23:07:00.360973 CBT Training : PASS
6984 23:07:00.364372 Write leveling : PASS
6985 23:07:00.364475 RX DQS gating : PASS
6986 23:07:00.367570 RX DQ/DQS(RDDQC) : PASS
6987 23:07:00.370446 TX DQ/DQS : PASS
6988 23:07:00.370560 RX DATLAT : PASS
6989 23:07:00.374457 RX DQ/DQS(Engine): PASS
6990 23:07:00.377732 TX OE : NO K
6991 23:07:00.377824 All Pass.
6992 23:07:00.377918
6993 23:07:00.377979 CH 0, Rank 1
6994 23:07:00.380331 SW Impedance : PASS
6995 23:07:00.384012 DUTY Scan : NO K
6996 23:07:00.384120 ZQ Calibration : PASS
6997 23:07:00.386919 Jitter Meter : NO K
6998 23:07:00.390174 CBT Training : PASS
6999 23:07:00.390269 Write leveling : NO K
7000 23:07:00.393791 RX DQS gating : PASS
7001 23:07:00.393882 RX DQ/DQS(RDDQC) : PASS
7002 23:07:00.397775 TX DQ/DQS : PASS
7003 23:07:00.400486 RX DATLAT : PASS
7004 23:07:00.400572 RX DQ/DQS(Engine): PASS
7005 23:07:00.403504 TX OE : NO K
7006 23:07:00.403591 All Pass.
7007 23:07:00.403658
7008 23:07:00.406994 CH 1, Rank 0
7009 23:07:00.407106 SW Impedance : PASS
7010 23:07:00.410541 DUTY Scan : NO K
7011 23:07:00.413373 ZQ Calibration : PASS
7012 23:07:00.413480 Jitter Meter : NO K
7013 23:07:00.416922 CBT Training : PASS
7014 23:07:00.420151 Write leveling : PASS
7015 23:07:00.420244 RX DQS gating : PASS
7016 23:07:00.423189 RX DQ/DQS(RDDQC) : PASS
7017 23:07:00.426477 TX DQ/DQS : PASS
7018 23:07:00.426565 RX DATLAT : PASS
7019 23:07:00.430251 RX DQ/DQS(Engine): PASS
7020 23:07:00.433178 TX OE : NO K
7021 23:07:00.433279 All Pass.
7022 23:07:00.433344
7023 23:07:00.433405 CH 1, Rank 1
7024 23:07:00.436535 SW Impedance : PASS
7025 23:07:00.439998 DUTY Scan : NO K
7026 23:07:00.440101 ZQ Calibration : PASS
7027 23:07:00.443009 Jitter Meter : NO K
7028 23:07:00.446288 CBT Training : PASS
7029 23:07:00.446374 Write leveling : NO K
7030 23:07:00.449448 RX DQS gating : PASS
7031 23:07:00.452682 RX DQ/DQS(RDDQC) : PASS
7032 23:07:00.452768 TX DQ/DQS : PASS
7033 23:07:00.456121 RX DATLAT : PASS
7034 23:07:00.459221 RX DQ/DQS(Engine): PASS
7035 23:07:00.459306 TX OE : NO K
7036 23:07:00.462912 All Pass.
7037 23:07:00.462996
7038 23:07:00.463061 DramC Write-DBI off
7039 23:07:00.466344 PER_BANK_REFRESH: Hybrid Mode
7040 23:07:00.466459 TX_TRACKING: ON
7041 23:07:00.475953 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7042 23:07:00.479092 [FAST_K] Save calibration result to emmc
7043 23:07:00.482263 dramc_set_vcore_voltage set vcore to 725000
7044 23:07:00.485511 Read voltage for 1600, 0
7045 23:07:00.485632 Vio18 = 0
7046 23:07:00.489288 Vcore = 725000
7047 23:07:00.489370 Vdram = 0
7048 23:07:00.489433 Vddq = 0
7049 23:07:00.492515 Vmddr = 0
7050 23:07:00.496405 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7051 23:07:00.502314 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7052 23:07:00.502417 MEM_TYPE=3, freq_sel=13
7053 23:07:00.506072 sv_algorithm_assistance_LP4_3733
7054 23:07:00.512313 ============ PULL DRAM RESETB DOWN ============
7055 23:07:00.515950 ========== PULL DRAM RESETB DOWN end =========
7056 23:07:00.518586 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7057 23:07:00.521945 ===================================
7058 23:07:00.525504 LPDDR4 DRAM CONFIGURATION
7059 23:07:00.528471 ===================================
7060 23:07:00.531785 EX_ROW_EN[0] = 0x0
7061 23:07:00.531874 EX_ROW_EN[1] = 0x0
7062 23:07:00.535371 LP4Y_EN = 0x0
7063 23:07:00.535463 WORK_FSP = 0x1
7064 23:07:00.538821 WL = 0x5
7065 23:07:00.538924 RL = 0x5
7066 23:07:00.541941 BL = 0x2
7067 23:07:00.542047 RPST = 0x0
7068 23:07:00.545082 RD_PRE = 0x0
7069 23:07:00.545182 WR_PRE = 0x1
7070 23:07:00.548350 WR_PST = 0x1
7071 23:07:00.548441 DBI_WR = 0x0
7072 23:07:00.551852 DBI_RD = 0x0
7073 23:07:00.551928 OTF = 0x1
7074 23:07:00.555169 ===================================
7075 23:07:00.558007 ===================================
7076 23:07:00.561815 ANA top config
7077 23:07:00.564711 ===================================
7078 23:07:00.568263 DLL_ASYNC_EN = 0
7079 23:07:00.568385 ALL_SLAVE_EN = 0
7080 23:07:00.571399 NEW_RANK_MODE = 1
7081 23:07:00.575195 DLL_IDLE_MODE = 1
7082 23:07:00.577675 LP45_APHY_COMB_EN = 1
7083 23:07:00.581104 TX_ODT_DIS = 0
7084 23:07:00.581193 NEW_8X_MODE = 1
7085 23:07:00.584711 ===================================
7086 23:07:00.587613 ===================================
7087 23:07:00.591236 data_rate = 3200
7088 23:07:00.594640 CKR = 1
7089 23:07:00.598201 DQ_P2S_RATIO = 8
7090 23:07:00.601028 ===================================
7091 23:07:00.604612 CA_P2S_RATIO = 8
7092 23:07:00.608146 DQ_CA_OPEN = 0
7093 23:07:00.608273 DQ_SEMI_OPEN = 0
7094 23:07:00.611054 CA_SEMI_OPEN = 0
7095 23:07:00.614926 CA_FULL_RATE = 0
7096 23:07:00.617441 DQ_CKDIV4_EN = 0
7097 23:07:00.621297 CA_CKDIV4_EN = 0
7098 23:07:00.624038 CA_PREDIV_EN = 0
7099 23:07:00.624147 PH8_DLY = 12
7100 23:07:00.627452 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7101 23:07:00.630452 DQ_AAMCK_DIV = 4
7102 23:07:00.634139 CA_AAMCK_DIV = 4
7103 23:07:00.637063 CA_ADMCK_DIV = 4
7104 23:07:00.640437 DQ_TRACK_CA_EN = 0
7105 23:07:00.643949 CA_PICK = 1600
7106 23:07:00.647092 CA_MCKIO = 1600
7107 23:07:00.647213 MCKIO_SEMI = 0
7108 23:07:00.650726 PLL_FREQ = 3068
7109 23:07:00.653477 DQ_UI_PI_RATIO = 32
7110 23:07:00.657698 CA_UI_PI_RATIO = 0
7111 23:07:00.660229 ===================================
7112 23:07:00.663911 ===================================
7113 23:07:00.667177 memory_type:LPDDR4
7114 23:07:00.667289 GP_NUM : 10
7115 23:07:00.670816 SRAM_EN : 1
7116 23:07:00.673709 MD32_EN : 0
7117 23:07:00.673793 ===================================
7118 23:07:00.677401 [ANA_INIT] >>>>>>>>>>>>>>
7119 23:07:00.679939 <<<<<< [CONFIGURE PHASE]: ANA_TX
7120 23:07:00.683563 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7121 23:07:00.686992 ===================================
7122 23:07:00.690433 data_rate = 3200,PCW = 0X7600
7123 23:07:00.693500 ===================================
7124 23:07:00.696374 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7125 23:07:00.703412 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7126 23:07:00.706454 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7127 23:07:00.712924 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7128 23:07:00.716194 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7129 23:07:00.719909 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7130 23:07:00.720012 [ANA_INIT] flow start
7131 23:07:00.722743 [ANA_INIT] PLL >>>>>>>>
7132 23:07:00.725885 [ANA_INIT] PLL <<<<<<<<
7133 23:07:00.729836 [ANA_INIT] MIDPI >>>>>>>>
7134 23:07:00.729936 [ANA_INIT] MIDPI <<<<<<<<
7135 23:07:00.732869 [ANA_INIT] DLL >>>>>>>>
7136 23:07:00.736211 [ANA_INIT] DLL <<<<<<<<
7137 23:07:00.736291 [ANA_INIT] flow end
7138 23:07:00.743156 ============ LP4 DIFF to SE enter ============
7139 23:07:00.745847 ============ LP4 DIFF to SE exit ============
7140 23:07:00.745935 [ANA_INIT] <<<<<<<<<<<<<
7141 23:07:00.749036 [Flow] Enable top DCM control >>>>>
7142 23:07:00.752480 [Flow] Enable top DCM control <<<<<
7143 23:07:00.756182 Enable DLL master slave shuffle
7144 23:07:00.762522 ==============================================================
7145 23:07:00.765472 Gating Mode config
7146 23:07:00.768950 ==============================================================
7147 23:07:00.772154 Config description:
7148 23:07:00.782632 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7149 23:07:00.788977 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7150 23:07:00.792438 SELPH_MODE 0: By rank 1: By Phase
7151 23:07:00.798689 ==============================================================
7152 23:07:00.802085 GAT_TRACK_EN = 1
7153 23:07:00.805760 RX_GATING_MODE = 2
7154 23:07:00.808677 RX_GATING_TRACK_MODE = 2
7155 23:07:00.811766 SELPH_MODE = 1
7156 23:07:00.811891 PICG_EARLY_EN = 1
7157 23:07:00.815175 VALID_LAT_VALUE = 1
7158 23:07:00.821547 ==============================================================
7159 23:07:00.825209 Enter into Gating configuration >>>>
7160 23:07:00.828084 Exit from Gating configuration <<<<
7161 23:07:00.831242 Enter into DVFS_PRE_config >>>>>
7162 23:07:00.841169 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7163 23:07:00.844638 Exit from DVFS_PRE_config <<<<<
7164 23:07:00.848124 Enter into PICG configuration >>>>
7165 23:07:00.851211 Exit from PICG configuration <<<<
7166 23:07:00.854445 [RX_INPUT] configuration >>>>>
7167 23:07:00.857768 [RX_INPUT] configuration <<<<<
7168 23:07:00.864386 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7169 23:07:00.867840 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7170 23:07:00.874270 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7171 23:07:00.880889 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7172 23:07:00.887475 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7173 23:07:00.894289 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7174 23:07:00.897745 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7175 23:07:00.901043 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7176 23:07:00.903691 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7177 23:07:00.910452 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7178 23:07:00.913636 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7179 23:07:00.917383 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7180 23:07:00.920386 ===================================
7181 23:07:00.923687 LPDDR4 DRAM CONFIGURATION
7182 23:07:00.926959 ===================================
7183 23:07:00.930502 EX_ROW_EN[0] = 0x0
7184 23:07:00.930613 EX_ROW_EN[1] = 0x0
7185 23:07:00.933346 LP4Y_EN = 0x0
7186 23:07:00.933447 WORK_FSP = 0x1
7187 23:07:00.936410 WL = 0x5
7188 23:07:00.936508 RL = 0x5
7189 23:07:00.940270 BL = 0x2
7190 23:07:00.940349 RPST = 0x0
7191 23:07:00.943532 RD_PRE = 0x0
7192 23:07:00.943605 WR_PRE = 0x1
7193 23:07:00.946517 WR_PST = 0x1
7194 23:07:00.946627 DBI_WR = 0x0
7195 23:07:00.949589 DBI_RD = 0x0
7196 23:07:00.953117 OTF = 0x1
7197 23:07:00.953221 ===================================
7198 23:07:00.960053 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7199 23:07:00.963203 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7200 23:07:00.966851 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7201 23:07:00.970066 ===================================
7202 23:07:00.973319 LPDDR4 DRAM CONFIGURATION
7203 23:07:00.976277 ===================================
7204 23:07:00.979703 EX_ROW_EN[0] = 0x10
7205 23:07:00.979790 EX_ROW_EN[1] = 0x0
7206 23:07:00.982736 LP4Y_EN = 0x0
7207 23:07:00.982822 WORK_FSP = 0x1
7208 23:07:00.986373 WL = 0x5
7209 23:07:00.986479 RL = 0x5
7210 23:07:00.989581 BL = 0x2
7211 23:07:00.989685 RPST = 0x0
7212 23:07:00.992611 RD_PRE = 0x0
7213 23:07:00.992701 WR_PRE = 0x1
7214 23:07:00.996091 WR_PST = 0x1
7215 23:07:00.996176 DBI_WR = 0x0
7216 23:07:00.999081 DBI_RD = 0x0
7217 23:07:01.002849 OTF = 0x1
7218 23:07:01.006012 ===================================
7219 23:07:01.009099 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7220 23:07:01.009238 ==
7221 23:07:01.012272 Dram Type= 6, Freq= 0, CH_0, rank 0
7222 23:07:01.019051 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7223 23:07:01.019195 ==
7224 23:07:01.022146 [Duty_Offset_Calibration]
7225 23:07:01.022268 B0:2 B1:0 CA:4
7226 23:07:01.022365
7227 23:07:01.025339 [DutyScan_Calibration_Flow] k_type=0
7228 23:07:01.034522
7229 23:07:01.034685 ==CLK 0==
7230 23:07:01.038413 Final CLK duty delay cell = -4
7231 23:07:01.041343 [-4] MAX Duty = 5031%(X100), DQS PI = 30
7232 23:07:01.044577 [-4] MIN Duty = 4844%(X100), DQS PI = 2
7233 23:07:01.048184 [-4] AVG Duty = 4937%(X100)
7234 23:07:01.048272
7235 23:07:01.051156 CH0 CLK Duty spec in!! Max-Min= 187%
7236 23:07:01.054580 [DutyScan_Calibration_Flow] ====Done====
7237 23:07:01.054688
7238 23:07:01.057794 [DutyScan_Calibration_Flow] k_type=1
7239 23:07:01.074800
7240 23:07:01.074979 ==DQS 0 ==
7241 23:07:01.078229 Final DQS duty delay cell = 0
7242 23:07:01.081422 [0] MAX Duty = 5249%(X100), DQS PI = 38
7243 23:07:01.084805 [0] MIN Duty = 5093%(X100), DQS PI = 10
7244 23:07:01.087921 [0] AVG Duty = 5171%(X100)
7245 23:07:01.088042
7246 23:07:01.088133 ==DQS 1 ==
7247 23:07:01.091151 Final DQS duty delay cell = 0
7248 23:07:01.094349 [0] MAX Duty = 5156%(X100), DQS PI = 0
7249 23:07:01.097790 [0] MIN Duty = 4969%(X100), DQS PI = 10
7250 23:07:01.101007 [0] AVG Duty = 5062%(X100)
7251 23:07:01.101094
7252 23:07:01.104353 CH0 DQS 0 Duty spec in!! Max-Min= 156%
7253 23:07:01.104443
7254 23:07:01.107515 CH0 DQS 1 Duty spec in!! Max-Min= 187%
7255 23:07:01.111093 [DutyScan_Calibration_Flow] ====Done====
7256 23:07:01.111210
7257 23:07:01.114769 [DutyScan_Calibration_Flow] k_type=3
7258 23:07:01.132012
7259 23:07:01.132192 ==DQM 0 ==
7260 23:07:01.135594 Final DQM duty delay cell = 0
7261 23:07:01.138546 [0] MAX Duty = 5124%(X100), DQS PI = 22
7262 23:07:01.142151 [0] MIN Duty = 4875%(X100), DQS PI = 56
7263 23:07:01.145241 [0] AVG Duty = 4999%(X100)
7264 23:07:01.145331
7265 23:07:01.145396 ==DQM 1 ==
7266 23:07:01.148541 Final DQM duty delay cell = 0
7267 23:07:01.152001 [0] MAX Duty = 5000%(X100), DQS PI = 2
7268 23:07:01.154788 [0] MIN Duty = 4844%(X100), DQS PI = 14
7269 23:07:01.158549 [0] AVG Duty = 4922%(X100)
7270 23:07:01.158658
7271 23:07:01.161589 CH0 DQM 0 Duty spec in!! Max-Min= 249%
7272 23:07:01.161689
7273 23:07:01.164955 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7274 23:07:01.168441 [DutyScan_Calibration_Flow] ====Done====
7275 23:07:01.168549
7276 23:07:01.171230 [DutyScan_Calibration_Flow] k_type=2
7277 23:07:01.188913
7278 23:07:01.189089 ==DQ 0 ==
7279 23:07:01.192149 Final DQ duty delay cell = 0
7280 23:07:01.195879 [0] MAX Duty = 5156%(X100), DQS PI = 22
7281 23:07:01.198950 [0] MIN Duty = 4969%(X100), DQS PI = 10
7282 23:07:01.202289 [0] AVG Duty = 5062%(X100)
7283 23:07:01.202386
7284 23:07:01.202454 ==DQ 1 ==
7285 23:07:01.205428 Final DQ duty delay cell = 0
7286 23:07:01.208902 [0] MAX Duty = 5218%(X100), DQS PI = 2
7287 23:07:01.212212 [0] MIN Duty = 4938%(X100), DQS PI = 12
7288 23:07:01.215066 [0] AVG Duty = 5078%(X100)
7289 23:07:01.215157
7290 23:07:01.218606 CH0 DQ 0 Duty spec in!! Max-Min= 187%
7291 23:07:01.218724
7292 23:07:01.221637 CH0 DQ 1 Duty spec in!! Max-Min= 280%
7293 23:07:01.225169 [DutyScan_Calibration_Flow] ====Done====
7294 23:07:01.225264 ==
7295 23:07:01.228153 Dram Type= 6, Freq= 0, CH_1, rank 0
7296 23:07:01.231662 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7297 23:07:01.231760 ==
7298 23:07:01.234918 [Duty_Offset_Calibration]
7299 23:07:01.235006 B0:0 B1:-1 CA:3
7300 23:07:01.235100
7301 23:07:01.238233 [DutyScan_Calibration_Flow] k_type=0
7302 23:07:01.248809
7303 23:07:01.248954 ==CLK 0==
7304 23:07:01.251804 Final CLK duty delay cell = -4
7305 23:07:01.255535 [-4] MAX Duty = 5000%(X100), DQS PI = 4
7306 23:07:01.259093 [-4] MIN Duty = 4844%(X100), DQS PI = 12
7307 23:07:01.261762 [-4] AVG Duty = 4922%(X100)
7308 23:07:01.261853
7309 23:07:01.265193 CH1 CLK Duty spec in!! Max-Min= 156%
7310 23:07:01.268327 [DutyScan_Calibration_Flow] ====Done====
7311 23:07:01.268419
7312 23:07:01.271601 [DutyScan_Calibration_Flow] k_type=1
7313 23:07:01.288054
7314 23:07:01.288201 ==DQS 0 ==
7315 23:07:01.291156 Final DQS duty delay cell = 0
7316 23:07:01.294686 [0] MAX Duty = 5250%(X100), DQS PI = 28
7317 23:07:01.297883 [0] MIN Duty = 4938%(X100), DQS PI = 40
7318 23:07:01.301120 [0] AVG Duty = 5094%(X100)
7319 23:07:01.301242
7320 23:07:01.301337 ==DQS 1 ==
7321 23:07:01.304099 Final DQS duty delay cell = -4
7322 23:07:01.307690 [-4] MAX Duty = 5031%(X100), DQS PI = 30
7323 23:07:01.310571 [-4] MIN Duty = 4844%(X100), DQS PI = 0
7324 23:07:01.314238 [-4] AVG Duty = 4937%(X100)
7325 23:07:01.314356
7326 23:07:01.317314 CH1 DQS 0 Duty spec in!! Max-Min= 312%
7327 23:07:01.317393
7328 23:07:01.320997 CH1 DQS 1 Duty spec in!! Max-Min= 187%
7329 23:07:01.324567 [DutyScan_Calibration_Flow] ====Done====
7330 23:07:01.324678
7331 23:07:01.327281 [DutyScan_Calibration_Flow] k_type=3
7332 23:07:01.345141
7333 23:07:01.345283 ==DQM 0 ==
7334 23:07:01.348425 Final DQM duty delay cell = 0
7335 23:07:01.351673 [0] MAX Duty = 5031%(X100), DQS PI = 30
7336 23:07:01.354895 [0] MIN Duty = 4750%(X100), DQS PI = 40
7337 23:07:01.358193 [0] AVG Duty = 4890%(X100)
7338 23:07:01.358288
7339 23:07:01.358351 ==DQM 1 ==
7340 23:07:01.361210 Final DQM duty delay cell = 0
7341 23:07:01.364495 [0] MAX Duty = 5000%(X100), DQS PI = 32
7342 23:07:01.368030 [0] MIN Duty = 4813%(X100), DQS PI = 0
7343 23:07:01.371429 [0] AVG Duty = 4906%(X100)
7344 23:07:01.371529
7345 23:07:01.374489 CH1 DQM 0 Duty spec in!! Max-Min= 281%
7346 23:07:01.374605
7347 23:07:01.377704 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7348 23:07:01.381120 [DutyScan_Calibration_Flow] ====Done====
7349 23:07:01.381241
7350 23:07:01.384471 [DutyScan_Calibration_Flow] k_type=2
7351 23:07:01.401273
7352 23:07:01.401450 ==DQ 0 ==
7353 23:07:01.404841 Final DQ duty delay cell = -4
7354 23:07:01.407442 [-4] MAX Duty = 4969%(X100), DQS PI = 30
7355 23:07:01.410914 [-4] MIN Duty = 4813%(X100), DQS PI = 38
7356 23:07:01.414048 [-4] AVG Duty = 4891%(X100)
7357 23:07:01.414141
7358 23:07:01.414206 ==DQ 1 ==
7359 23:07:01.417551 Final DQ duty delay cell = 0
7360 23:07:01.420555 [0] MAX Duty = 5031%(X100), DQS PI = 30
7361 23:07:01.423877 [0] MIN Duty = 4875%(X100), DQS PI = 58
7362 23:07:01.427614 [0] AVG Duty = 4953%(X100)
7363 23:07:01.427711
7364 23:07:01.430547 CH1 DQ 0 Duty spec in!! Max-Min= 156%
7365 23:07:01.430635
7366 23:07:01.433860 CH1 DQ 1 Duty spec in!! Max-Min= 156%
7367 23:07:01.437400 [DutyScan_Calibration_Flow] ====Done====
7368 23:07:01.440545 nWR fixed to 30
7369 23:07:01.444111 [ModeRegInit_LP4] CH0 RK0
7370 23:07:01.444207 [ModeRegInit_LP4] CH0 RK1
7371 23:07:01.446749 [ModeRegInit_LP4] CH1 RK0
7372 23:07:01.450176 [ModeRegInit_LP4] CH1 RK1
7373 23:07:01.450273 match AC timing 5
7374 23:07:01.456700 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7375 23:07:01.460103 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7376 23:07:01.463503 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7377 23:07:01.470436 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7378 23:07:01.473405 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7379 23:07:01.473507 [MiockJmeterHQA]
7380 23:07:01.476770
7381 23:07:01.480885 [DramcMiockJmeter] u1RxGatingPI = 0
7382 23:07:01.480987 0 : 4365, 4140
7383 23:07:01.481056 4 : 4252, 4026
7384 23:07:01.483368 8 : 4252, 4027
7385 23:07:01.483457 12 : 4262, 4032
7386 23:07:01.486675 16 : 4258, 4026
7387 23:07:01.486765 20 : 4249, 4027
7388 23:07:01.490252 24 : 4252, 4027
7389 23:07:01.490346 28 : 4252, 4027
7390 23:07:01.490414 32 : 4253, 4026
7391 23:07:01.493433 36 : 4252, 4027
7392 23:07:01.493528 40 : 4363, 4137
7393 23:07:01.496320 44 : 4360, 4138
7394 23:07:01.496412 48 : 4252, 4026
7395 23:07:01.499906 52 : 4250, 4026
7396 23:07:01.499995 56 : 4250, 4027
7397 23:07:01.503129 60 : 4250, 4026
7398 23:07:01.503222 64 : 4252, 4029
7399 23:07:01.503289 68 : 4250, 4026
7400 23:07:01.506548 72 : 4250, 4027
7401 23:07:01.506643 76 : 4249, 4027
7402 23:07:01.509515 80 : 4250, 4027
7403 23:07:01.509609 84 : 4253, 4026
7404 23:07:01.513852 88 : 4250, 4027
7405 23:07:01.513956 92 : 4361, 4138
7406 23:07:01.516477 96 : 4360, 3403
7407 23:07:01.516567 100 : 4360, 0
7408 23:07:01.516635 104 : 4366, 0
7409 23:07:01.519383 108 : 4252, 0
7410 23:07:01.519471 112 : 4252, 0
7411 23:07:01.522752 116 : 4250, 0
7412 23:07:01.522842 120 : 4250, 0
7413 23:07:01.522911 124 : 4250, 0
7414 23:07:01.526637 128 : 4250, 0
7415 23:07:01.526734 132 : 4255, 0
7416 23:07:01.526803 136 : 4250, 0
7417 23:07:01.529858 140 : 4250, 0
7418 23:07:01.529952 144 : 4250, 0
7419 23:07:01.532933 148 : 4360, 0
7420 23:07:01.533016 152 : 4361, 0
7421 23:07:01.533092 156 : 4363, 0
7422 23:07:01.536145 160 : 4250, 0
7423 23:07:01.536226 164 : 4250, 0
7424 23:07:01.539469 168 : 4255, 0
7425 23:07:01.539558 172 : 4255, 0
7426 23:07:01.539623 176 : 4250, 0
7427 23:07:01.542498 180 : 4250, 0
7428 23:07:01.542599 184 : 4253, 0
7429 23:07:01.545876 188 : 4250, 0
7430 23:07:01.545995 192 : 4250, 0
7431 23:07:01.546090 196 : 4253, 0
7432 23:07:01.549379 200 : 4360, 0
7433 23:07:01.549466 204 : 4250, 0
7434 23:07:01.553005 208 : 4363, 0
7435 23:07:01.553107 212 : 4255, 0
7436 23:07:01.553175 216 : 4249, 0
7437 23:07:01.556239 220 : 4250, 351
7438 23:07:01.556328 224 : 4252, 3925
7439 23:07:01.559192 228 : 4253, 4029
7440 23:07:01.559281 232 : 4363, 4140
7441 23:07:01.562826 236 : 4250, 4027
7442 23:07:01.562918 240 : 4250, 4027
7443 23:07:01.566664 244 : 4255, 4029
7444 23:07:01.566757 248 : 4252, 4029
7445 23:07:01.566825 252 : 4255, 4030
7446 23:07:01.569128 256 : 4361, 4138
7447 23:07:01.569221 260 : 4363, 4137
7448 23:07:01.573227 264 : 4250, 4027
7449 23:07:01.573318 268 : 4254, 4030
7450 23:07:01.575966 272 : 4252, 4029
7451 23:07:01.576077 276 : 4250, 4027
7452 23:07:01.579110 280 : 4250, 4026
7453 23:07:01.579195 284 : 4363, 4138
7454 23:07:01.582486 288 : 4250, 4027
7455 23:07:01.582595 292 : 4250, 4026
7456 23:07:01.585548 296 : 4360, 4137
7457 23:07:01.585654 300 : 4250, 4027
7458 23:07:01.588954 304 : 4250, 4027
7459 23:07:01.589061 308 : 4361, 4138
7460 23:07:01.592068 312 : 4363, 4137
7461 23:07:01.592148 316 : 4250, 4027
7462 23:07:01.595629 320 : 4255, 4030
7463 23:07:01.595736 324 : 4252, 4029
7464 23:07:01.595829 328 : 4250, 4026
7465 23:07:01.598801 332 : 4250, 3997
7466 23:07:01.598880 336 : 4363, 2117
7467 23:07:01.598943
7468 23:07:01.602129 MIOCK jitter meter ch=0
7469 23:07:01.602264
7470 23:07:01.605698 1T = (336-100) = 236 dly cells
7471 23:07:01.611790 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7472 23:07:01.611908 ==
7473 23:07:01.615621 Dram Type= 6, Freq= 0, CH_0, rank 0
7474 23:07:01.618676 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7475 23:07:01.618773 ==
7476 23:07:01.625071 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7477 23:07:01.628210 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7478 23:07:01.631903 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7479 23:07:01.638174 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7480 23:07:01.647794 [CA 0] Center 43 (13~74) winsize 62
7481 23:07:01.650815 [CA 1] Center 42 (12~73) winsize 62
7482 23:07:01.654181 [CA 2] Center 37 (8~67) winsize 60
7483 23:07:01.657546 [CA 3] Center 37 (8~67) winsize 60
7484 23:07:01.660535 [CA 4] Center 36 (6~66) winsize 61
7485 23:07:01.663952 [CA 5] Center 35 (5~66) winsize 62
7486 23:07:01.664036
7487 23:07:01.667513 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7488 23:07:01.667589
7489 23:07:01.673525 [CATrainingPosCal] consider 1 rank data
7490 23:07:01.673607 u2DelayCellTimex100 = 275/100 ps
7491 23:07:01.680614 CA0 delay=43 (13~74),Diff = 8 PI (28 cell)
7492 23:07:01.683573 CA1 delay=42 (12~73),Diff = 7 PI (24 cell)
7493 23:07:01.687105 CA2 delay=37 (8~67),Diff = 2 PI (7 cell)
7494 23:07:01.690212 CA3 delay=37 (8~67),Diff = 2 PI (7 cell)
7495 23:07:01.693509 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7496 23:07:01.696964 CA5 delay=35 (5~66),Diff = 0 PI (0 cell)
7497 23:07:01.697075
7498 23:07:01.700469 CA PerBit enable=1, Macro0, CA PI delay=35
7499 23:07:01.700569
7500 23:07:01.703384 [CBTSetCACLKResult] CA Dly = 35
7501 23:07:01.706629 CS Dly: 10 (0~41)
7502 23:07:01.710250 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7503 23:07:01.713374 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7504 23:07:01.713478 ==
7505 23:07:01.716438 Dram Type= 6, Freq= 0, CH_0, rank 1
7506 23:07:01.723002 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7507 23:07:01.723114 ==
7508 23:07:01.726653 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7509 23:07:01.732882 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7510 23:07:01.736671 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7511 23:07:01.742906 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7512 23:07:01.751050 [CA 0] Center 43 (13~74) winsize 62
7513 23:07:01.754494 [CA 1] Center 43 (13~73) winsize 61
7514 23:07:01.757951 [CA 2] Center 38 (9~68) winsize 60
7515 23:07:01.761129 [CA 3] Center 38 (9~68) winsize 60
7516 23:07:01.764413 [CA 4] Center 36 (6~67) winsize 62
7517 23:07:01.767478 [CA 5] Center 36 (6~66) winsize 61
7518 23:07:01.767576
7519 23:07:01.770782 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7520 23:07:01.770883
7521 23:07:01.777463 [CATrainingPosCal] consider 2 rank data
7522 23:07:01.777553 u2DelayCellTimex100 = 275/100 ps
7523 23:07:01.783903 CA0 delay=43 (13~74),Diff = 7 PI (24 cell)
7524 23:07:01.787397 CA1 delay=43 (13~73),Diff = 7 PI (24 cell)
7525 23:07:01.790528 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
7526 23:07:01.793979 CA3 delay=38 (9~67),Diff = 2 PI (7 cell)
7527 23:07:01.797187 CA4 delay=36 (6~66),Diff = 0 PI (0 cell)
7528 23:07:01.800203 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7529 23:07:01.800305
7530 23:07:01.803345 CA PerBit enable=1, Macro0, CA PI delay=36
7531 23:07:01.803462
7532 23:07:01.807474 [CBTSetCACLKResult] CA Dly = 36
7533 23:07:01.810103 CS Dly: 11 (0~44)
7534 23:07:01.813337 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7535 23:07:01.816572 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7536 23:07:01.816650
7537 23:07:01.819798 ----->DramcWriteLeveling(PI) begin...
7538 23:07:01.823480 ==
7539 23:07:01.823598 Dram Type= 6, Freq= 0, CH_0, rank 0
7540 23:07:01.829763 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7541 23:07:01.829913 ==
7542 23:07:01.833692 Write leveling (Byte 0): 34 => 34
7543 23:07:01.836495 Write leveling (Byte 1): 26 => 26
7544 23:07:01.840047 DramcWriteLeveling(PI) end<-----
7545 23:07:01.840153
7546 23:07:01.840241 ==
7547 23:07:01.842978 Dram Type= 6, Freq= 0, CH_0, rank 0
7548 23:07:01.846514 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7549 23:07:01.846621 ==
7550 23:07:01.849714 [Gating] SW mode calibration
7551 23:07:01.856409 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7552 23:07:01.862979 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7553 23:07:01.866159 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7554 23:07:01.869765 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7555 23:07:01.876105 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7556 23:07:01.879257 1 4 12 | B1->B0 | 2323 3232 | 0 1 | (0 0) (1 1)
7557 23:07:01.882522 1 4 16 | B1->B0 | 2322 3434 | 1 1 | (0 0) (1 1)
7558 23:07:01.889104 1 4 20 | B1->B0 | 2c2c 3434 | 0 1 | (1 1) (1 1)
7559 23:07:01.892727 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7560 23:07:01.896180 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7561 23:07:01.902652 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7562 23:07:01.905422 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7563 23:07:01.908675 1 5 8 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
7564 23:07:01.915556 1 5 12 | B1->B0 | 3434 2525 | 1 0 | (1 1) (1 1)
7565 23:07:01.919038 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7566 23:07:01.922201 1 5 20 | B1->B0 | 3030 2323 | 1 0 | (0 0) (0 0)
7567 23:07:01.929077 1 5 24 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
7568 23:07:01.931861 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7569 23:07:01.935132 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7570 23:07:01.941970 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7571 23:07:01.945258 1 6 8 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
7572 23:07:01.948382 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7573 23:07:01.954962 1 6 16 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
7574 23:07:01.958335 1 6 20 | B1->B0 | 3b3b 4646 | 0 0 | (1 1) (0 0)
7575 23:07:01.961757 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7576 23:07:01.968257 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7577 23:07:01.971526 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7578 23:07:01.975233 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7579 23:07:01.981440 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7580 23:07:01.984695 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7581 23:07:01.988313 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7582 23:07:01.994669 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7583 23:07:01.998003 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7584 23:07:02.001534 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7585 23:07:02.007643 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7586 23:07:02.011312 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7587 23:07:02.014240 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7588 23:07:02.020848 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7589 23:07:02.024444 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7590 23:07:02.027560 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7591 23:07:02.034328 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7592 23:07:02.038005 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7593 23:07:02.041144 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7594 23:07:02.047968 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7595 23:07:02.050997 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7596 23:07:02.054067 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7597 23:07:02.057289 Total UI for P1: 0, mck2ui 16
7598 23:07:02.060532 best dqsien dly found for B0: ( 1, 9, 10)
7599 23:07:02.066970 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7600 23:07:02.070305 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7601 23:07:02.073685 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7602 23:07:02.080444 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7603 23:07:02.080550 Total UI for P1: 0, mck2ui 16
7604 23:07:02.084025 best dqsien dly found for B1: ( 1, 9, 22)
7605 23:07:02.090596 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7606 23:07:02.093473 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7607 23:07:02.093555
7608 23:07:02.096985 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7609 23:07:02.100055 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7610 23:07:02.103970 [Gating] SW calibration Done
7611 23:07:02.104053 ==
7612 23:07:02.106700 Dram Type= 6, Freq= 0, CH_0, rank 0
7613 23:07:02.110025 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7614 23:07:02.110128 ==
7615 23:07:02.113269 RX Vref Scan: 0
7616 23:07:02.113370
7617 23:07:02.113469 RX Vref 0 -> 0, step: 1
7618 23:07:02.113566
7619 23:07:02.116561 RX Delay 0 -> 252, step: 8
7620 23:07:02.120007 iDelay=192, Bit 0, Center 131 (80 ~ 183) 104
7621 23:07:02.126314 iDelay=192, Bit 1, Center 135 (80 ~ 191) 112
7622 23:07:02.129592 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7623 23:07:02.133031 iDelay=192, Bit 3, Center 127 (72 ~ 183) 112
7624 23:07:02.136469 iDelay=192, Bit 4, Center 135 (80 ~ 191) 112
7625 23:07:02.139728 iDelay=192, Bit 5, Center 119 (64 ~ 175) 112
7626 23:07:02.146608 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
7627 23:07:02.149635 iDelay=192, Bit 7, Center 139 (88 ~ 191) 104
7628 23:07:02.152519 iDelay=192, Bit 8, Center 115 (64 ~ 167) 104
7629 23:07:02.156229 iDelay=192, Bit 9, Center 115 (64 ~ 167) 104
7630 23:07:02.159497 iDelay=192, Bit 10, Center 127 (80 ~ 175) 96
7631 23:07:02.165970 iDelay=192, Bit 11, Center 123 (72 ~ 175) 104
7632 23:07:02.169519 iDelay=192, Bit 12, Center 135 (80 ~ 191) 112
7633 23:07:02.172922 iDelay=192, Bit 13, Center 131 (80 ~ 183) 104
7634 23:07:02.175801 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
7635 23:07:02.182267 iDelay=192, Bit 15, Center 135 (80 ~ 191) 112
7636 23:07:02.182430 ==
7637 23:07:02.185672 Dram Type= 6, Freq= 0, CH_0, rank 0
7638 23:07:02.189044 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7639 23:07:02.189250 ==
7640 23:07:02.189326 DQS Delay:
7641 23:07:02.192392 DQS0 = 0, DQS1 = 0
7642 23:07:02.192542 DQM Delay:
7643 23:07:02.195270 DQM0 = 131, DQM1 = 127
7644 23:07:02.195430 DQ Delay:
7645 23:07:02.198907 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
7646 23:07:02.201999 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
7647 23:07:02.205469 DQ8 =115, DQ9 =115, DQ10 =127, DQ11 =123
7648 23:07:02.211756 DQ12 =135, DQ13 =131, DQ14 =135, DQ15 =135
7649 23:07:02.211958
7650 23:07:02.212069
7651 23:07:02.212184 ==
7652 23:07:02.214940 Dram Type= 6, Freq= 0, CH_0, rank 0
7653 23:07:02.218710 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7654 23:07:02.218874 ==
7655 23:07:02.219002
7656 23:07:02.219130
7657 23:07:02.221749 TX Vref Scan disable
7658 23:07:02.221871 == TX Byte 0 ==
7659 23:07:02.228270 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7660 23:07:02.231616 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7661 23:07:02.231740 == TX Byte 1 ==
7662 23:07:02.238214 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7663 23:07:02.241403 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7664 23:07:02.241516 ==
7665 23:07:02.244518 Dram Type= 6, Freq= 0, CH_0, rank 0
7666 23:07:02.248209 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7667 23:07:02.248312 ==
7668 23:07:02.262701
7669 23:07:02.265877 TX Vref early break, caculate TX vref
7670 23:07:02.269428 TX Vref=16, minBit 1, minWin=22, winSum=370
7671 23:07:02.272656 TX Vref=18, minBit 1, minWin=23, winSum=381
7672 23:07:02.276133 TX Vref=20, minBit 7, minWin=23, winSum=389
7673 23:07:02.279162 TX Vref=22, minBit 1, minWin=24, winSum=398
7674 23:07:02.282760 TX Vref=24, minBit 1, minWin=24, winSum=409
7675 23:07:02.288975 TX Vref=26, minBit 1, minWin=25, winSum=414
7676 23:07:02.292266 TX Vref=28, minBit 2, minWin=25, winSum=420
7677 23:07:02.295661 TX Vref=30, minBit 2, minWin=25, winSum=420
7678 23:07:02.298623 TX Vref=32, minBit 4, minWin=24, winSum=406
7679 23:07:02.302575 TX Vref=34, minBit 2, minWin=23, winSum=397
7680 23:07:02.308871 [TxChooseVref] Worse bit 2, Min win 25, Win sum 420, Final Vref 28
7681 23:07:02.308966
7682 23:07:02.311862 Final TX Range 0 Vref 28
7683 23:07:02.311964
7684 23:07:02.312031 ==
7685 23:07:02.315239 Dram Type= 6, Freq= 0, CH_0, rank 0
7686 23:07:02.318287 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7687 23:07:02.318399 ==
7688 23:07:02.318492
7689 23:07:02.318581
7690 23:07:02.322335 TX Vref Scan disable
7691 23:07:02.328334 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7692 23:07:02.328431 == TX Byte 0 ==
7693 23:07:02.332223 u2DelayCellOfst[0]=14 cells (4 PI)
7694 23:07:02.335154 u2DelayCellOfst[1]=17 cells (5 PI)
7695 23:07:02.338312 u2DelayCellOfst[2]=10 cells (3 PI)
7696 23:07:02.341372 u2DelayCellOfst[3]=10 cells (3 PI)
7697 23:07:02.345241 u2DelayCellOfst[4]=10 cells (3 PI)
7698 23:07:02.348361 u2DelayCellOfst[5]=0 cells (0 PI)
7699 23:07:02.351490 u2DelayCellOfst[6]=21 cells (6 PI)
7700 23:07:02.354665 u2DelayCellOfst[7]=17 cells (5 PI)
7701 23:07:02.358380 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
7702 23:07:02.361034 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7703 23:07:02.364554 == TX Byte 1 ==
7704 23:07:02.367746 u2DelayCellOfst[8]=0 cells (0 PI)
7705 23:07:02.371643 u2DelayCellOfst[9]=0 cells (0 PI)
7706 23:07:02.374184 u2DelayCellOfst[10]=7 cells (2 PI)
7707 23:07:02.377616 u2DelayCellOfst[11]=0 cells (0 PI)
7708 23:07:02.380664 u2DelayCellOfst[12]=10 cells (3 PI)
7709 23:07:02.384456 u2DelayCellOfst[13]=10 cells (3 PI)
7710 23:07:02.387838 u2DelayCellOfst[14]=14 cells (4 PI)
7711 23:07:02.391085 u2DelayCellOfst[15]=10 cells (3 PI)
7712 23:07:02.393966 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7713 23:07:02.397503 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7714 23:07:02.400748 DramC Write-DBI on
7715 23:07:02.400835 ==
7716 23:07:02.404093 Dram Type= 6, Freq= 0, CH_0, rank 0
7717 23:07:02.407182 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7718 23:07:02.407270 ==
7719 23:07:02.407384
7720 23:07:02.407477
7721 23:07:02.410553 TX Vref Scan disable
7722 23:07:02.413669 == TX Byte 0 ==
7723 23:07:02.416944 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
7724 23:07:02.417037 == TX Byte 1 ==
7725 23:07:02.423533 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
7726 23:07:02.423616 DramC Write-DBI off
7727 23:07:02.423690
7728 23:07:02.423758 [DATLAT]
7729 23:07:02.426728 Freq=1600, CH0 RK0
7730 23:07:02.426805
7731 23:07:02.430077 DATLAT Default: 0xf
7732 23:07:02.430187 0, 0xFFFF, sum = 0
7733 23:07:02.433444 1, 0xFFFF, sum = 0
7734 23:07:02.433558 2, 0xFFFF, sum = 0
7735 23:07:02.436713 3, 0xFFFF, sum = 0
7736 23:07:02.436798 4, 0xFFFF, sum = 0
7737 23:07:02.440269 5, 0xFFFF, sum = 0
7738 23:07:02.440361 6, 0xFFFF, sum = 0
7739 23:07:02.443288 7, 0xFFFF, sum = 0
7740 23:07:02.443405 8, 0xFFFF, sum = 0
7741 23:07:02.446709 9, 0xFFFF, sum = 0
7742 23:07:02.446789 10, 0xFFFF, sum = 0
7743 23:07:02.449791 11, 0xFFFF, sum = 0
7744 23:07:02.449870 12, 0xFFFF, sum = 0
7745 23:07:02.452945 13, 0xFFFF, sum = 0
7746 23:07:02.453052 14, 0x0, sum = 1
7747 23:07:02.456332 15, 0x0, sum = 2
7748 23:07:02.456446 16, 0x0, sum = 3
7749 23:07:02.459808 17, 0x0, sum = 4
7750 23:07:02.459885 best_step = 15
7751 23:07:02.459948
7752 23:07:02.460025 ==
7753 23:07:02.462804 Dram Type= 6, Freq= 0, CH_0, rank 0
7754 23:07:02.469797 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7755 23:07:02.469917 ==
7756 23:07:02.470013 RX Vref Scan: 1
7757 23:07:02.470103
7758 23:07:02.472761 Set Vref Range= 24 -> 127
7759 23:07:02.472838
7760 23:07:02.476880 RX Vref 24 -> 127, step: 1
7761 23:07:02.476973
7762 23:07:02.479334 RX Delay 19 -> 252, step: 4
7763 23:07:02.479441
7764 23:07:02.482588 Set Vref, RX VrefLevel [Byte0]: 24
7765 23:07:02.486504 [Byte1]: 24
7766 23:07:02.486610
7767 23:07:02.489202 Set Vref, RX VrefLevel [Byte0]: 25
7768 23:07:02.492959 [Byte1]: 25
7769 23:07:02.493071
7770 23:07:02.496131 Set Vref, RX VrefLevel [Byte0]: 26
7771 23:07:02.499153 [Byte1]: 26
7772 23:07:02.502620
7773 23:07:02.502700 Set Vref, RX VrefLevel [Byte0]: 27
7774 23:07:02.505705 [Byte1]: 27
7775 23:07:02.510347
7776 23:07:02.510463 Set Vref, RX VrefLevel [Byte0]: 28
7777 23:07:02.513893 [Byte1]: 28
7778 23:07:02.517906
7779 23:07:02.518018 Set Vref, RX VrefLevel [Byte0]: 29
7780 23:07:02.521130 [Byte1]: 29
7781 23:07:02.525411
7782 23:07:02.525495 Set Vref, RX VrefLevel [Byte0]: 30
7783 23:07:02.528872 [Byte1]: 30
7784 23:07:02.532747
7785 23:07:02.532825 Set Vref, RX VrefLevel [Byte0]: 31
7786 23:07:02.536855 [Byte1]: 31
7787 23:07:02.540713
7788 23:07:02.540816 Set Vref, RX VrefLevel [Byte0]: 32
7789 23:07:02.543692 [Byte1]: 32
7790 23:07:02.548162
7791 23:07:02.548243 Set Vref, RX VrefLevel [Byte0]: 33
7792 23:07:02.551299 [Byte1]: 33
7793 23:07:02.555542
7794 23:07:02.555644 Set Vref, RX VrefLevel [Byte0]: 34
7795 23:07:02.559045 [Byte1]: 34
7796 23:07:02.563107
7797 23:07:02.563213 Set Vref, RX VrefLevel [Byte0]: 35
7798 23:07:02.566435 [Byte1]: 35
7799 23:07:02.570946
7800 23:07:02.571079 Set Vref, RX VrefLevel [Byte0]: 36
7801 23:07:02.574648 [Byte1]: 36
7802 23:07:02.578437
7803 23:07:02.578583 Set Vref, RX VrefLevel [Byte0]: 37
7804 23:07:02.581552 [Byte1]: 37
7805 23:07:02.586143
7806 23:07:02.586261 Set Vref, RX VrefLevel [Byte0]: 38
7807 23:07:02.589186 [Byte1]: 38
7808 23:07:02.593820
7809 23:07:02.593925 Set Vref, RX VrefLevel [Byte0]: 39
7810 23:07:02.596846 [Byte1]: 39
7811 23:07:02.601266
7812 23:07:02.601358 Set Vref, RX VrefLevel [Byte0]: 40
7813 23:07:02.604648 [Byte1]: 40
7814 23:07:02.608684
7815 23:07:02.608770 Set Vref, RX VrefLevel [Byte0]: 41
7816 23:07:02.611765 [Byte1]: 41
7817 23:07:02.616460
7818 23:07:02.616541 Set Vref, RX VrefLevel [Byte0]: 42
7819 23:07:02.619255 [Byte1]: 42
7820 23:07:02.624100
7821 23:07:02.624242 Set Vref, RX VrefLevel [Byte0]: 43
7822 23:07:02.627062 [Byte1]: 43
7823 23:07:02.631760
7824 23:07:02.631908 Set Vref, RX VrefLevel [Byte0]: 44
7825 23:07:02.634629 [Byte1]: 44
7826 23:07:02.638985
7827 23:07:02.639085 Set Vref, RX VrefLevel [Byte0]: 45
7828 23:07:02.642435 [Byte1]: 45
7829 23:07:02.646524
7830 23:07:02.646630 Set Vref, RX VrefLevel [Byte0]: 46
7831 23:07:02.649768 [Byte1]: 46
7832 23:07:02.654244
7833 23:07:02.654346 Set Vref, RX VrefLevel [Byte0]: 47
7834 23:07:02.657639 [Byte1]: 47
7835 23:07:02.661603
7836 23:07:02.661677 Set Vref, RX VrefLevel [Byte0]: 48
7837 23:07:02.665157 [Byte1]: 48
7838 23:07:02.669659
7839 23:07:02.669774 Set Vref, RX VrefLevel [Byte0]: 49
7840 23:07:02.672697 [Byte1]: 49
7841 23:07:02.677234
7842 23:07:02.677331 Set Vref, RX VrefLevel [Byte0]: 50
7843 23:07:02.680368 [Byte1]: 50
7844 23:07:02.684766
7845 23:07:02.684840 Set Vref, RX VrefLevel [Byte0]: 51
7846 23:07:02.687864 [Byte1]: 51
7847 23:07:02.691749
7848 23:07:02.691822 Set Vref, RX VrefLevel [Byte0]: 52
7849 23:07:02.695680 [Byte1]: 52
7850 23:07:02.699607
7851 23:07:02.699678 Set Vref, RX VrefLevel [Byte0]: 53
7852 23:07:02.702809 [Byte1]: 53
7853 23:07:02.706913
7854 23:07:02.706990 Set Vref, RX VrefLevel [Byte0]: 54
7855 23:07:02.710804 [Byte1]: 54
7856 23:07:02.714690
7857 23:07:02.714762 Set Vref, RX VrefLevel [Byte0]: 55
7858 23:07:02.718239 [Byte1]: 55
7859 23:07:02.722275
7860 23:07:02.722345 Set Vref, RX VrefLevel [Byte0]: 56
7861 23:07:02.725638 [Byte1]: 56
7862 23:07:02.729767
7863 23:07:02.729836 Set Vref, RX VrefLevel [Byte0]: 57
7864 23:07:02.733650 [Byte1]: 57
7865 23:07:02.737603
7866 23:07:02.737672 Set Vref, RX VrefLevel [Byte0]: 58
7867 23:07:02.740435 [Byte1]: 58
7868 23:07:02.745312
7869 23:07:02.745380 Set Vref, RX VrefLevel [Byte0]: 59
7870 23:07:02.748320 [Byte1]: 59
7871 23:07:02.752700
7872 23:07:02.752769 Set Vref, RX VrefLevel [Byte0]: 60
7873 23:07:02.756015 [Byte1]: 60
7874 23:07:02.760625
7875 23:07:02.760703 Set Vref, RX VrefLevel [Byte0]: 61
7876 23:07:02.763238 [Byte1]: 61
7877 23:07:02.767712
7878 23:07:02.767782 Set Vref, RX VrefLevel [Byte0]: 62
7879 23:07:02.770743 [Byte1]: 62
7880 23:07:02.775343
7881 23:07:02.775435 Set Vref, RX VrefLevel [Byte0]: 63
7882 23:07:02.778612 [Byte1]: 63
7883 23:07:02.782713
7884 23:07:02.782785 Set Vref, RX VrefLevel [Byte0]: 64
7885 23:07:02.786132 [Byte1]: 64
7886 23:07:02.790766
7887 23:07:02.790835 Set Vref, RX VrefLevel [Byte0]: 65
7888 23:07:02.793807 [Byte1]: 65
7889 23:07:02.798415
7890 23:07:02.798484 Set Vref, RX VrefLevel [Byte0]: 66
7891 23:07:02.801596 [Byte1]: 66
7892 23:07:02.805717
7893 23:07:02.805799 Set Vref, RX VrefLevel [Byte0]: 67
7894 23:07:02.808790 [Byte1]: 67
7895 23:07:02.813204
7896 23:07:02.813273 Set Vref, RX VrefLevel [Byte0]: 68
7897 23:07:02.816418 [Byte1]: 68
7898 23:07:02.820698
7899 23:07:02.820769 Set Vref, RX VrefLevel [Byte0]: 69
7900 23:07:02.823976 [Byte1]: 69
7901 23:07:02.828115
7902 23:07:02.828186 Set Vref, RX VrefLevel [Byte0]: 70
7903 23:07:02.831584 [Byte1]: 70
7904 23:07:02.835786
7905 23:07:02.835861 Set Vref, RX VrefLevel [Byte0]: 71
7906 23:07:02.839233 [Byte1]: 71
7907 23:07:02.843494
7908 23:07:02.843562 Set Vref, RX VrefLevel [Byte0]: 72
7909 23:07:02.846730 [Byte1]: 72
7910 23:07:02.851082
7911 23:07:02.851181 Set Vref, RX VrefLevel [Byte0]: 73
7912 23:07:02.854185 [Byte1]: 73
7913 23:07:02.858358
7914 23:07:02.858430 Final RX Vref Byte 0 = 55 to rank0
7915 23:07:02.861705 Final RX Vref Byte 1 = 61 to rank0
7916 23:07:02.865326 Final RX Vref Byte 0 = 55 to rank1
7917 23:07:02.868125 Final RX Vref Byte 1 = 61 to rank1==
7918 23:07:02.871548 Dram Type= 6, Freq= 0, CH_0, rank 0
7919 23:07:02.878247 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7920 23:07:02.878321 ==
7921 23:07:02.878390 DQS Delay:
7922 23:07:02.881327 DQS0 = 0, DQS1 = 0
7923 23:07:02.881404 DQM Delay:
7924 23:07:02.884696 DQM0 = 128, DQM1 = 124
7925 23:07:02.884767 DQ Delay:
7926 23:07:02.888092 DQ0 =130, DQ1 =130, DQ2 =124, DQ3 =124
7927 23:07:02.891505 DQ4 =132, DQ5 =118, DQ6 =138, DQ7 =134
7928 23:07:02.894476 DQ8 =112, DQ9 =112, DQ10 =124, DQ11 =120
7929 23:07:02.898212 DQ12 =132, DQ13 =130, DQ14 =132, DQ15 =130
7930 23:07:02.898384
7931 23:07:02.898534
7932 23:07:02.898674
7933 23:07:02.901451 [DramC_TX_OE_Calibration] TA2
7934 23:07:02.904696 Original DQ_B0 (3 6) =30, OEN = 27
7935 23:07:02.908002 Original DQ_B1 (3 6) =30, OEN = 27
7936 23:07:02.911295 24, 0x0, End_B0=24 End_B1=24
7937 23:07:02.914339 25, 0x0, End_B0=25 End_B1=25
7938 23:07:02.914504 26, 0x0, End_B0=26 End_B1=26
7939 23:07:02.917702 27, 0x0, End_B0=27 End_B1=27
7940 23:07:02.921198 28, 0x0, End_B0=28 End_B1=28
7941 23:07:02.924401 29, 0x0, End_B0=29 End_B1=29
7942 23:07:02.924487 30, 0x0, End_B0=30 End_B1=30
7943 23:07:02.927734 31, 0x4141, End_B0=30 End_B1=30
7944 23:07:02.931105 Byte0 end_step=30 best_step=27
7945 23:07:02.933943 Byte1 end_step=30 best_step=27
7946 23:07:02.937723 Byte0 TX OE(2T, 0.5T) = (3, 3)
7947 23:07:02.940719 Byte1 TX OE(2T, 0.5T) = (3, 3)
7948 23:07:02.940817
7949 23:07:02.940910
7950 23:07:02.947280 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a17, (MSB)MR19= 0x303, tDQSOscB0 = 398 ps tDQSOscB1 = 396 ps
7951 23:07:02.950880 CH0 RK0: MR19=303, MR18=1A17
7952 23:07:02.957400 CH0_RK0: MR19=0x303, MR18=0x1A17, DQSOSC=396, MR23=63, INC=23, DEC=15
7953 23:07:02.957476
7954 23:07:02.960349 ----->DramcWriteLeveling(PI) begin...
7955 23:07:02.960423 ==
7956 23:07:02.964077 Dram Type= 6, Freq= 0, CH_0, rank 1
7957 23:07:02.966980 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7958 23:07:02.970299 ==
7959 23:07:02.970371 Write leveling (Byte 0): 36 => 36
7960 23:07:02.973648 Write leveling (Byte 1): 27 => 27
7961 23:07:02.977154 DramcWriteLeveling(PI) end<-----
7962 23:07:02.977233
7963 23:07:02.977294 ==
7964 23:07:02.980177 Dram Type= 6, Freq= 0, CH_0, rank 1
7965 23:07:02.986818 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7966 23:07:02.986895 ==
7967 23:07:02.989989 [Gating] SW mode calibration
7968 23:07:02.996351 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7969 23:07:02.999701 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7970 23:07:03.006370 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7971 23:07:03.009854 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7972 23:07:03.012831 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7973 23:07:03.019680 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7974 23:07:03.022564 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7975 23:07:03.026231 1 4 20 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
7976 23:07:03.032616 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7977 23:07:03.035782 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7978 23:07:03.039176 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7979 23:07:03.045846 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7980 23:07:03.048985 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
7981 23:07:03.052671 1 5 12 | B1->B0 | 3434 2626 | 1 0 | (1 1) (0 0)
7982 23:07:03.059266 1 5 16 | B1->B0 | 3232 2323 | 1 0 | (1 0) (0 0)
7983 23:07:03.062202 1 5 20 | B1->B0 | 2b2b 2323 | 0 0 | (1 0) (0 0)
7984 23:07:03.065915 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7985 23:07:03.072444 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7986 23:07:03.075406 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7987 23:07:03.078967 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7988 23:07:03.085554 1 6 8 | B1->B0 | 2323 3d3d | 0 0 | (0 0) (0 0)
7989 23:07:03.088687 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7990 23:07:03.092197 1 6 16 | B1->B0 | 3232 4646 | 0 0 | (0 0) (0 0)
7991 23:07:03.098555 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7992 23:07:03.101979 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7993 23:07:03.104902 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7994 23:07:03.111472 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7995 23:07:03.114974 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7996 23:07:03.118479 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7997 23:07:03.124601 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7998 23:07:03.128325 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7999 23:07:03.131401 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8000 23:07:03.137806 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8001 23:07:03.141185 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8002 23:07:03.144498 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8003 23:07:03.150856 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8004 23:07:03.154475 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8005 23:07:03.158003 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8006 23:07:03.164299 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8007 23:07:03.167950 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8008 23:07:03.171055 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8009 23:07:03.177384 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8010 23:07:03.180776 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8011 23:07:03.184359 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8012 23:07:03.190540 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8013 23:07:03.194128 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8014 23:07:03.197117 Total UI for P1: 0, mck2ui 16
8015 23:07:03.200406 best dqsien dly found for B0: ( 1, 9, 6)
8016 23:07:03.204066 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8017 23:07:03.210680 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8018 23:07:03.213898 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8019 23:07:03.217020 Total UI for P1: 0, mck2ui 16
8020 23:07:03.220592 best dqsien dly found for B1: ( 1, 9, 18)
8021 23:07:03.223856 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8022 23:07:03.226888 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8023 23:07:03.227236
8024 23:07:03.230025 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8025 23:07:03.236743 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8026 23:07:03.237101 [Gating] SW calibration Done
8027 23:07:03.237389 ==
8028 23:07:03.239960 Dram Type= 6, Freq= 0, CH_0, rank 1
8029 23:07:03.246778 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8030 23:07:03.247139 ==
8031 23:07:03.247483 RX Vref Scan: 0
8032 23:07:03.247764
8033 23:07:03.249931 RX Vref 0 -> 0, step: 1
8034 23:07:03.250286
8035 23:07:03.253274 RX Delay 0 -> 252, step: 8
8036 23:07:03.256859 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
8037 23:07:03.260096 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8038 23:07:03.263462 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8039 23:07:03.266606 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8040 23:07:03.273266 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8041 23:07:03.276753 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8042 23:07:03.280099 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
8043 23:07:03.283415 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8044 23:07:03.286649 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8045 23:07:03.293246 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8046 23:07:03.296304 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8047 23:07:03.299834 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8048 23:07:03.302681 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8049 23:07:03.309714 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8050 23:07:03.312626 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8051 23:07:03.316373 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8052 23:07:03.316750 ==
8053 23:07:03.319344 Dram Type= 6, Freq= 0, CH_0, rank 1
8054 23:07:03.322463 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8055 23:07:03.325939 ==
8056 23:07:03.326300 DQS Delay:
8057 23:07:03.326638 DQS0 = 0, DQS1 = 0
8058 23:07:03.329090 DQM Delay:
8059 23:07:03.329473 DQM0 = 131, DQM1 = 127
8060 23:07:03.332803 DQ Delay:
8061 23:07:03.336103 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
8062 23:07:03.339266 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
8063 23:07:03.342247 DQ8 =119, DQ9 =111, DQ10 =127, DQ11 =119
8064 23:07:03.345951 DQ12 =131, DQ13 =135, DQ14 =139, DQ15 =135
8065 23:07:03.346335
8066 23:07:03.346639
8067 23:07:03.346923 ==
8068 23:07:03.348886 Dram Type= 6, Freq= 0, CH_0, rank 1
8069 23:07:03.352483 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8070 23:07:03.352869 ==
8071 23:07:03.355652
8072 23:07:03.356031
8073 23:07:03.356332 TX Vref Scan disable
8074 23:07:03.358757 == TX Byte 0 ==
8075 23:07:03.362228 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8076 23:07:03.365447 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8077 23:07:03.368954 == TX Byte 1 ==
8078 23:07:03.371874 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8079 23:07:03.375454 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8080 23:07:03.378723 ==
8081 23:07:03.379104 Dram Type= 6, Freq= 0, CH_0, rank 1
8082 23:07:03.385057 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8083 23:07:03.385446 ==
8084 23:07:03.398096
8085 23:07:03.401348 TX Vref early break, caculate TX vref
8086 23:07:03.404647 TX Vref=16, minBit 1, minWin=23, winSum=382
8087 23:07:03.407993 TX Vref=18, minBit 0, minWin=24, winSum=392
8088 23:07:03.411431 TX Vref=20, minBit 9, minWin=23, winSum=395
8089 23:07:03.414745 TX Vref=22, minBit 0, minWin=25, winSum=407
8090 23:07:03.418465 TX Vref=24, minBit 1, minWin=25, winSum=414
8091 23:07:03.424526 TX Vref=26, minBit 4, minWin=25, winSum=422
8092 23:07:03.427523 TX Vref=28, minBit 4, minWin=25, winSum=420
8093 23:07:03.431169 TX Vref=30, minBit 1, minWin=25, winSum=419
8094 23:07:03.434134 TX Vref=32, minBit 7, minWin=24, winSum=409
8095 23:07:03.437508 TX Vref=34, minBit 0, minWin=24, winSum=398
8096 23:07:03.443951 [TxChooseVref] Worse bit 4, Min win 25, Win sum 422, Final Vref 26
8097 23:07:03.444360
8098 23:07:03.447595 Final TX Range 0 Vref 26
8099 23:07:03.447929
8100 23:07:03.448240 ==
8101 23:07:03.450784 Dram Type= 6, Freq= 0, CH_0, rank 1
8102 23:07:03.454250 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8103 23:07:03.454655 ==
8104 23:07:03.454982
8105 23:07:03.455265
8106 23:07:03.457635 TX Vref Scan disable
8107 23:07:03.463913 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8108 23:07:03.464328 == TX Byte 0 ==
8109 23:07:03.467506 u2DelayCellOfst[0]=14 cells (4 PI)
8110 23:07:03.470381 u2DelayCellOfst[1]=17 cells (5 PI)
8111 23:07:03.473849 u2DelayCellOfst[2]=10 cells (3 PI)
8112 23:07:03.477124 u2DelayCellOfst[3]=10 cells (3 PI)
8113 23:07:03.480366 u2DelayCellOfst[4]=10 cells (3 PI)
8114 23:07:03.483905 u2DelayCellOfst[5]=0 cells (0 PI)
8115 23:07:03.486998 u2DelayCellOfst[6]=17 cells (5 PI)
8116 23:07:03.490756 u2DelayCellOfst[7]=17 cells (5 PI)
8117 23:07:03.494198 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8118 23:07:03.496945 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8119 23:07:03.500010 == TX Byte 1 ==
8120 23:07:03.503632 u2DelayCellOfst[8]=0 cells (0 PI)
8121 23:07:03.506615 u2DelayCellOfst[9]=0 cells (0 PI)
8122 23:07:03.510180 u2DelayCellOfst[10]=3 cells (1 PI)
8123 23:07:03.513421 u2DelayCellOfst[11]=3 cells (1 PI)
8124 23:07:03.513885 u2DelayCellOfst[12]=10 cells (3 PI)
8125 23:07:03.516992 u2DelayCellOfst[13]=10 cells (3 PI)
8126 23:07:03.519738 u2DelayCellOfst[14]=17 cells (5 PI)
8127 23:07:03.523563 u2DelayCellOfst[15]=10 cells (3 PI)
8128 23:07:03.529732 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8129 23:07:03.533417 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8130 23:07:03.533820 DramC Write-DBI on
8131 23:07:03.536386 ==
8132 23:07:03.539496 Dram Type= 6, Freq= 0, CH_0, rank 1
8133 23:07:03.542944 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8134 23:07:03.543404 ==
8135 23:07:03.543929
8136 23:07:03.544288
8137 23:07:03.546374 TX Vref Scan disable
8138 23:07:03.546947 == TX Byte 0 ==
8139 23:07:03.553159 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
8140 23:07:03.553558 == TX Byte 1 ==
8141 23:07:03.556129 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8142 23:07:03.559664 DramC Write-DBI off
8143 23:07:03.560025
8144 23:07:03.560329 [DATLAT]
8145 23:07:03.562498 Freq=1600, CH0 RK1
8146 23:07:03.562857
8147 23:07:03.563168 DATLAT Default: 0xf
8148 23:07:03.565970 0, 0xFFFF, sum = 0
8149 23:07:03.569080 1, 0xFFFF, sum = 0
8150 23:07:03.569536 2, 0xFFFF, sum = 0
8151 23:07:03.572935 3, 0xFFFF, sum = 0
8152 23:07:03.573343 4, 0xFFFF, sum = 0
8153 23:07:03.575693 5, 0xFFFF, sum = 0
8154 23:07:03.576095 6, 0xFFFF, sum = 0
8155 23:07:03.578819 7, 0xFFFF, sum = 0
8156 23:07:03.579189 8, 0xFFFF, sum = 0
8157 23:07:03.582982 9, 0xFFFF, sum = 0
8158 23:07:03.583433 10, 0xFFFF, sum = 0
8159 23:07:03.585695 11, 0xFFFF, sum = 0
8160 23:07:03.586042 12, 0xFFFF, sum = 0
8161 23:07:03.589188 13, 0xFFFF, sum = 0
8162 23:07:03.589586 14, 0x0, sum = 1
8163 23:07:03.592532 15, 0x0, sum = 2
8164 23:07:03.592935 16, 0x0, sum = 3
8165 23:07:03.595621 17, 0x0, sum = 4
8166 23:07:03.596058 best_step = 15
8167 23:07:03.596388
8168 23:07:03.596687 ==
8169 23:07:03.598956 Dram Type= 6, Freq= 0, CH_0, rank 1
8170 23:07:03.605565 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8171 23:07:03.606030 ==
8172 23:07:03.606363 RX Vref Scan: 0
8173 23:07:03.606665
8174 23:07:03.608614 RX Vref 0 -> 0, step: 1
8175 23:07:03.609005
8176 23:07:03.612202 RX Delay 11 -> 252, step: 4
8177 23:07:03.615202 iDelay=187, Bit 0, Center 126 (75 ~ 178) 104
8178 23:07:03.618987 iDelay=187, Bit 1, Center 130 (79 ~ 182) 104
8179 23:07:03.622049 iDelay=187, Bit 2, Center 124 (71 ~ 178) 108
8180 23:07:03.628512 iDelay=187, Bit 3, Center 126 (75 ~ 178) 104
8181 23:07:03.631630 iDelay=187, Bit 4, Center 132 (83 ~ 182) 100
8182 23:07:03.635295 iDelay=187, Bit 5, Center 118 (63 ~ 174) 112
8183 23:07:03.638270 iDelay=187, Bit 6, Center 136 (87 ~ 186) 100
8184 23:07:03.642039 iDelay=187, Bit 7, Center 134 (83 ~ 186) 104
8185 23:07:03.648200 iDelay=187, Bit 8, Center 114 (63 ~ 166) 104
8186 23:07:03.651677 iDelay=187, Bit 9, Center 110 (59 ~ 162) 104
8187 23:07:03.654975 iDelay=187, Bit 10, Center 126 (71 ~ 182) 112
8188 23:07:03.657938 iDelay=187, Bit 11, Center 118 (67 ~ 170) 104
8189 23:07:03.664748 iDelay=187, Bit 12, Center 126 (75 ~ 178) 104
8190 23:07:03.667858 iDelay=187, Bit 13, Center 130 (79 ~ 182) 104
8191 23:07:03.671503 iDelay=187, Bit 14, Center 134 (83 ~ 186) 104
8192 23:07:03.674584 iDelay=187, Bit 15, Center 128 (75 ~ 182) 108
8193 23:07:03.674970 ==
8194 23:07:03.678187 Dram Type= 6, Freq= 0, CH_0, rank 1
8195 23:07:03.684734 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8196 23:07:03.685119 ==
8197 23:07:03.685425 DQS Delay:
8198 23:07:03.688136 DQS0 = 0, DQS1 = 0
8199 23:07:03.688519 DQM Delay:
8200 23:07:03.688829 DQM0 = 128, DQM1 = 123
8201 23:07:03.691034 DQ Delay:
8202 23:07:03.694414 DQ0 =126, DQ1 =130, DQ2 =124, DQ3 =126
8203 23:07:03.698030 DQ4 =132, DQ5 =118, DQ6 =136, DQ7 =134
8204 23:07:03.700872 DQ8 =114, DQ9 =110, DQ10 =126, DQ11 =118
8205 23:07:03.704478 DQ12 =126, DQ13 =130, DQ14 =134, DQ15 =128
8206 23:07:03.704935
8207 23:07:03.705319
8208 23:07:03.705680
8209 23:07:03.707923 [DramC_TX_OE_Calibration] TA2
8210 23:07:03.711007 Original DQ_B0 (3 6) =30, OEN = 27
8211 23:07:03.714413 Original DQ_B1 (3 6) =30, OEN = 27
8212 23:07:03.717752 24, 0x0, End_B0=24 End_B1=24
8213 23:07:03.718163 25, 0x0, End_B0=25 End_B1=25
8214 23:07:03.720916 26, 0x0, End_B0=26 End_B1=26
8215 23:07:03.724422 27, 0x0, End_B0=27 End_B1=27
8216 23:07:03.727505 28, 0x0, End_B0=28 End_B1=28
8217 23:07:03.731150 29, 0x0, End_B0=29 End_B1=29
8218 23:07:03.731597 30, 0x0, End_B0=30 End_B1=30
8219 23:07:03.734175 31, 0x4141, End_B0=30 End_B1=30
8220 23:07:03.737273 Byte0 end_step=30 best_step=27
8221 23:07:03.740869 Byte1 end_step=30 best_step=27
8222 23:07:03.744086 Byte0 TX OE(2T, 0.5T) = (3, 3)
8223 23:07:03.747905 Byte1 TX OE(2T, 0.5T) = (3, 3)
8224 23:07:03.748281
8225 23:07:03.748579
8226 23:07:03.753891 [DQSOSCAuto] RK1, (LSB)MR18= 0x1513, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 399 ps
8227 23:07:03.757265 CH0 RK1: MR19=303, MR18=1513
8228 23:07:03.764399 CH0_RK1: MR19=0x303, MR18=0x1513, DQSOSC=399, MR23=63, INC=23, DEC=15
8229 23:07:03.767239 [RxdqsGatingPostProcess] freq 1600
8230 23:07:03.770714 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8231 23:07:03.773588 best DQS0 dly(2T, 0.5T) = (1, 1)
8232 23:07:03.777281 best DQS1 dly(2T, 0.5T) = (1, 1)
8233 23:07:03.780276 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8234 23:07:03.783522 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8235 23:07:03.786968 best DQS0 dly(2T, 0.5T) = (1, 1)
8236 23:07:03.790329 best DQS1 dly(2T, 0.5T) = (1, 1)
8237 23:07:03.793812 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8238 23:07:03.797151 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8239 23:07:03.800057 Pre-setting of DQS Precalculation
8240 23:07:03.803548 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8241 23:07:03.803960 ==
8242 23:07:03.807070 Dram Type= 6, Freq= 0, CH_1, rank 0
8243 23:07:03.813589 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8244 23:07:03.813967 ==
8245 23:07:03.816464 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8246 23:07:03.823533 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8247 23:07:03.826202 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8248 23:07:03.832589 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8249 23:07:03.841103 [CA 0] Center 42 (12~72) winsize 61
8250 23:07:03.844226 [CA 1] Center 41 (11~72) winsize 62
8251 23:07:03.847391 [CA 2] Center 38 (9~67) winsize 59
8252 23:07:03.850972 [CA 3] Center 37 (8~66) winsize 59
8253 23:07:03.853965 [CA 4] Center 37 (7~68) winsize 62
8254 23:07:03.857035 [CA 5] Center 36 (7~66) winsize 60
8255 23:07:03.857408
8256 23:07:03.860470 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8257 23:07:03.860862
8258 23:07:03.866964 [CATrainingPosCal] consider 1 rank data
8259 23:07:03.867341 u2DelayCellTimex100 = 275/100 ps
8260 23:07:03.873822 CA0 delay=42 (12~72),Diff = 6 PI (21 cell)
8261 23:07:03.876949 CA1 delay=41 (11~72),Diff = 5 PI (17 cell)
8262 23:07:03.880409 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8263 23:07:03.883503 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8264 23:07:03.887100 CA4 delay=37 (7~68),Diff = 1 PI (3 cell)
8265 23:07:03.890001 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8266 23:07:03.890400
8267 23:07:03.893352 CA PerBit enable=1, Macro0, CA PI delay=36
8268 23:07:03.893747
8269 23:07:03.896940 [CBTSetCACLKResult] CA Dly = 36
8270 23:07:03.900196 CS Dly: 8 (0~39)
8271 23:07:03.903167 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8272 23:07:03.906631 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8273 23:07:03.907004 ==
8274 23:07:03.909906 Dram Type= 6, Freq= 0, CH_1, rank 1
8275 23:07:03.916263 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8276 23:07:03.916671 ==
8277 23:07:03.919624 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8278 23:07:03.926523 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8279 23:07:03.929521 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8280 23:07:03.936366 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8281 23:07:03.944011 [CA 0] Center 42 (12~72) winsize 61
8282 23:07:03.947315 [CA 1] Center 43 (14~72) winsize 59
8283 23:07:03.950821 [CA 2] Center 38 (9~68) winsize 60
8284 23:07:03.953683 [CA 3] Center 36 (7~66) winsize 60
8285 23:07:03.957411 [CA 4] Center 37 (7~68) winsize 62
8286 23:07:03.960467 [CA 5] Center 37 (8~67) winsize 60
8287 23:07:03.960904
8288 23:07:03.963880 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8289 23:07:03.964347
8290 23:07:03.970406 [CATrainingPosCal] consider 2 rank data
8291 23:07:03.970949 u2DelayCellTimex100 = 275/100 ps
8292 23:07:03.977077 CA0 delay=42 (12~72),Diff = 5 PI (17 cell)
8293 23:07:03.980158 CA1 delay=43 (14~72),Diff = 6 PI (21 cell)
8294 23:07:03.984246 CA2 delay=38 (9~67),Diff = 1 PI (3 cell)
8295 23:07:03.986974 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8296 23:07:03.990168 CA4 delay=37 (7~68),Diff = 0 PI (0 cell)
8297 23:07:03.993725 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8298 23:07:03.994188
8299 23:07:03.996647 CA PerBit enable=1, Macro0, CA PI delay=37
8300 23:07:03.997108
8301 23:07:04.000363 [CBTSetCACLKResult] CA Dly = 37
8302 23:07:04.003393 CS Dly: 9 (0~42)
8303 23:07:04.006976 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8304 23:07:04.010266 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8305 23:07:04.010832
8306 23:07:04.013304 ----->DramcWriteLeveling(PI) begin...
8307 23:07:04.013811 ==
8308 23:07:04.016190 Dram Type= 6, Freq= 0, CH_1, rank 0
8309 23:07:04.022994 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8310 23:07:04.023416 ==
8311 23:07:04.026470 Write leveling (Byte 0): 26 => 26
8312 23:07:04.029791 Write leveling (Byte 1): 30 => 30
8313 23:07:04.032902 DramcWriteLeveling(PI) end<-----
8314 23:07:04.033282
8315 23:07:04.033584 ==
8316 23:07:04.035912 Dram Type= 6, Freq= 0, CH_1, rank 0
8317 23:07:04.039637 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8318 23:07:04.040021 ==
8319 23:07:04.042780 [Gating] SW mode calibration
8320 23:07:04.049653 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8321 23:07:04.052842 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8322 23:07:04.059512 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8323 23:07:04.062715 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8324 23:07:04.066093 1 4 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8325 23:07:04.072583 1 4 12 | B1->B0 | 2424 3030 | 0 1 | (0 0) (1 1)
8326 23:07:04.075650 1 4 16 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
8327 23:07:04.079234 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8328 23:07:04.086104 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8329 23:07:04.089274 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8330 23:07:04.092174 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8331 23:07:04.098851 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8332 23:07:04.102048 1 5 8 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
8333 23:07:04.105347 1 5 12 | B1->B0 | 3030 2424 | 0 0 | (0 0) (1 0)
8334 23:07:04.112212 1 5 16 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
8335 23:07:04.115745 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8336 23:07:04.119168 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8337 23:07:04.125431 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8338 23:07:04.128702 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8339 23:07:04.131993 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8340 23:07:04.138680 1 6 8 | B1->B0 | 2323 2828 | 0 0 | (0 0) (1 1)
8341 23:07:04.141766 1 6 12 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
8342 23:07:04.144736 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8343 23:07:04.151467 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8344 23:07:04.154973 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8345 23:07:04.158133 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8346 23:07:04.164930 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8347 23:07:04.167923 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8348 23:07:04.171619 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8349 23:07:04.178188 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8350 23:07:04.181403 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8351 23:07:04.184848 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8352 23:07:04.190945 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8353 23:07:04.194403 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8354 23:07:04.197836 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8355 23:07:04.204490 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8356 23:07:04.207581 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8357 23:07:04.210784 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8358 23:07:04.217380 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8359 23:07:04.221111 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8360 23:07:04.224116 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8361 23:07:04.230802 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8362 23:07:04.233849 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8363 23:07:04.237576 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8364 23:07:04.243654 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8365 23:07:04.247439 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8366 23:07:04.250716 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8367 23:07:04.254059 Total UI for P1: 0, mck2ui 16
8368 23:07:04.257099 best dqsien dly found for B0: ( 1, 9, 10)
8369 23:07:04.263765 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8370 23:07:04.267434 Total UI for P1: 0, mck2ui 16
8371 23:07:04.270287 best dqsien dly found for B1: ( 1, 9, 14)
8372 23:07:04.273726 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8373 23:07:04.277296 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8374 23:07:04.277713
8375 23:07:04.280553 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8376 23:07:04.283317 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8377 23:07:04.286864 [Gating] SW calibration Done
8378 23:07:04.287275 ==
8379 23:07:04.290374 Dram Type= 6, Freq= 0, CH_1, rank 0
8380 23:07:04.293246 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8381 23:07:04.293662 ==
8382 23:07:04.296826 RX Vref Scan: 0
8383 23:07:04.297240
8384 23:07:04.300260 RX Vref 0 -> 0, step: 1
8385 23:07:04.300683
8386 23:07:04.301011 RX Delay 0 -> 252, step: 8
8387 23:07:04.306541 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8388 23:07:04.310362 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8389 23:07:04.313247 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8390 23:07:04.316390 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8391 23:07:04.319972 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8392 23:07:04.326135 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8393 23:07:04.329647 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8394 23:07:04.332689 iDelay=200, Bit 7, Center 131 (80 ~ 183) 104
8395 23:07:04.336467 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
8396 23:07:04.339469 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8397 23:07:04.346057 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8398 23:07:04.349659 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8399 23:07:04.352402 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8400 23:07:04.356247 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8401 23:07:04.362540 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8402 23:07:04.365799 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8403 23:07:04.366220 ==
8404 23:07:04.369143 Dram Type= 6, Freq= 0, CH_1, rank 0
8405 23:07:04.372721 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8406 23:07:04.373141 ==
8407 23:07:04.375789 DQS Delay:
8408 23:07:04.376203 DQS0 = 0, DQS1 = 0
8409 23:07:04.376536 DQM Delay:
8410 23:07:04.379317 DQM0 = 135, DQM1 = 132
8411 23:07:04.379792 DQ Delay:
8412 23:07:04.382321 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8413 23:07:04.385612 DQ4 =131, DQ5 =143, DQ6 =147, DQ7 =131
8414 23:07:04.389134 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =127
8415 23:07:04.395914 DQ12 =139, DQ13 =143, DQ14 =139, DQ15 =139
8416 23:07:04.396329
8417 23:07:04.396662
8418 23:07:04.396973 ==
8419 23:07:04.398754 Dram Type= 6, Freq= 0, CH_1, rank 0
8420 23:07:04.402164 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8421 23:07:04.402585 ==
8422 23:07:04.402918
8423 23:07:04.403227
8424 23:07:04.405372 TX Vref Scan disable
8425 23:07:04.405786 == TX Byte 0 ==
8426 23:07:04.412135 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8427 23:07:04.415091 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8428 23:07:04.415569 == TX Byte 1 ==
8429 23:07:04.421912 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
8430 23:07:04.424991 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
8431 23:07:04.425409 ==
8432 23:07:04.428636 Dram Type= 6, Freq= 0, CH_1, rank 0
8433 23:07:04.431761 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8434 23:07:04.432180 ==
8435 23:07:04.447484
8436 23:07:04.450473 TX Vref early break, caculate TX vref
8437 23:07:04.454049 TX Vref=16, minBit 8, minWin=22, winSum=370
8438 23:07:04.457097 TX Vref=18, minBit 3, minWin=23, winSum=380
8439 23:07:04.460730 TX Vref=20, minBit 6, minWin=23, winSum=387
8440 23:07:04.463520 TX Vref=22, minBit 1, minWin=24, winSum=397
8441 23:07:04.467283 TX Vref=24, minBit 15, minWin=24, winSum=408
8442 23:07:04.473993 TX Vref=26, minBit 5, minWin=25, winSum=415
8443 23:07:04.477189 TX Vref=28, minBit 3, minWin=25, winSum=417
8444 23:07:04.480553 TX Vref=30, minBit 0, minWin=25, winSum=412
8445 23:07:04.483586 TX Vref=32, minBit 0, minWin=25, winSum=409
8446 23:07:04.487191 TX Vref=34, minBit 0, minWin=23, winSum=399
8447 23:07:04.493591 TX Vref=36, minBit 9, minWin=23, winSum=386
8448 23:07:04.496970 [TxChooseVref] Worse bit 3, Min win 25, Win sum 417, Final Vref 28
8449 23:07:04.497390
8450 23:07:04.500648 Final TX Range 0 Vref 28
8451 23:07:04.501102
8452 23:07:04.501436 ==
8453 23:07:04.503667 Dram Type= 6, Freq= 0, CH_1, rank 0
8454 23:07:04.506560 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8455 23:07:04.507013 ==
8456 23:07:04.510003
8457 23:07:04.510418
8458 23:07:04.510751 TX Vref Scan disable
8459 23:07:04.516347 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8460 23:07:04.516765 == TX Byte 0 ==
8461 23:07:04.519762 u2DelayCellOfst[0]=17 cells (5 PI)
8462 23:07:04.522991 u2DelayCellOfst[1]=10 cells (3 PI)
8463 23:07:04.526816 u2DelayCellOfst[2]=0 cells (0 PI)
8464 23:07:04.529812 u2DelayCellOfst[3]=7 cells (2 PI)
8465 23:07:04.532999 u2DelayCellOfst[4]=10 cells (3 PI)
8466 23:07:04.536351 u2DelayCellOfst[5]=17 cells (5 PI)
8467 23:07:04.539993 u2DelayCellOfst[6]=17 cells (5 PI)
8468 23:07:04.543088 u2DelayCellOfst[7]=7 cells (2 PI)
8469 23:07:04.546101 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8470 23:07:04.549689 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8471 23:07:04.552785 == TX Byte 1 ==
8472 23:07:04.556069 u2DelayCellOfst[8]=0 cells (0 PI)
8473 23:07:04.559521 u2DelayCellOfst[9]=0 cells (0 PI)
8474 23:07:04.562584 u2DelayCellOfst[10]=10 cells (3 PI)
8475 23:07:04.566273 u2DelayCellOfst[11]=3 cells (1 PI)
8476 23:07:04.569507 u2DelayCellOfst[12]=14 cells (4 PI)
8477 23:07:04.572896 u2DelayCellOfst[13]=14 cells (4 PI)
8478 23:07:04.575668 u2DelayCellOfst[14]=17 cells (5 PI)
8479 23:07:04.599286 u2DelayCellOfst[15]=17 cells (5 PI)
8480 23:07:04.599869 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8481 23:07:04.600223 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
8482 23:07:04.600542 DramC Write-DBI on
8483 23:07:04.600906 ==
8484 23:07:04.601219 Dram Type= 6, Freq= 0, CH_1, rank 0
8485 23:07:04.601599 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8486 23:07:04.601897 ==
8487 23:07:04.602186
8488 23:07:04.602468
8489 23:07:04.602804 TX Vref Scan disable
8490 23:07:04.603193 == TX Byte 0 ==
8491 23:07:04.606194 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8492 23:07:04.606704 == TX Byte 1 ==
8493 23:07:04.611214 Update DQM dly =727 (2 ,6, 23) DQM OEN =(3 ,3)
8494 23:07:04.612227 DramC Write-DBI off
8495 23:07:04.612684
8496 23:07:04.613085 [DATLAT]
8497 23:07:04.615614 Freq=1600, CH1 RK0
8498 23:07:04.616120
8499 23:07:04.616530 DATLAT Default: 0xf
8500 23:07:04.618942 0, 0xFFFF, sum = 0
8501 23:07:04.622213 1, 0xFFFF, sum = 0
8502 23:07:04.622636 2, 0xFFFF, sum = 0
8503 23:07:04.625686 3, 0xFFFF, sum = 0
8504 23:07:04.626112 4, 0xFFFF, sum = 0
8505 23:07:04.628435 5, 0xFFFF, sum = 0
8506 23:07:04.628874 6, 0xFFFF, sum = 0
8507 23:07:04.631786 7, 0xFFFF, sum = 0
8508 23:07:04.632208 8, 0xFFFF, sum = 0
8509 23:07:04.635397 9, 0xFFFF, sum = 0
8510 23:07:04.635962 10, 0xFFFF, sum = 0
8511 23:07:04.638621 11, 0xFFFF, sum = 0
8512 23:07:04.639041 12, 0xFFFF, sum = 0
8513 23:07:04.642190 13, 0xFFFF, sum = 0
8514 23:07:04.642718 14, 0x0, sum = 1
8515 23:07:04.645222 15, 0x0, sum = 2
8516 23:07:04.645733 16, 0x0, sum = 3
8517 23:07:04.648354 17, 0x0, sum = 4
8518 23:07:04.648866 best_step = 15
8519 23:07:04.649275
8520 23:07:04.649657 ==
8521 23:07:04.651873 Dram Type= 6, Freq= 0, CH_1, rank 0
8522 23:07:04.658521 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8523 23:07:04.659147 ==
8524 23:07:04.659729 RX Vref Scan: 1
8525 23:07:04.660262
8526 23:07:04.661794 Set Vref Range= 24 -> 127
8527 23:07:04.662265
8528 23:07:04.664837 RX Vref 24 -> 127, step: 1
8529 23:07:04.665328
8530 23:07:04.665737 RX Delay 19 -> 252, step: 4
8531 23:07:04.668328
8532 23:07:04.668832 Set Vref, RX VrefLevel [Byte0]: 24
8533 23:07:04.671474 [Byte1]: 24
8534 23:07:04.675650
8535 23:07:04.676124 Set Vref, RX VrefLevel [Byte0]: 25
8536 23:07:04.679421 [Byte1]: 25
8537 23:07:04.683535
8538 23:07:04.684122 Set Vref, RX VrefLevel [Byte0]: 26
8539 23:07:04.686447 [Byte1]: 26
8540 23:07:04.691342
8541 23:07:04.691870 Set Vref, RX VrefLevel [Byte0]: 27
8542 23:07:04.693971 [Byte1]: 27
8543 23:07:04.698841
8544 23:07:04.699503 Set Vref, RX VrefLevel [Byte0]: 28
8545 23:07:04.701916 [Byte1]: 28
8546 23:07:04.706097
8547 23:07:04.706602 Set Vref, RX VrefLevel [Byte0]: 29
8548 23:07:04.709170 [Byte1]: 29
8549 23:07:04.713890
8550 23:07:04.714494 Set Vref, RX VrefLevel [Byte0]: 30
8551 23:07:04.716893 [Byte1]: 30
8552 23:07:04.721008
8553 23:07:04.721512 Set Vref, RX VrefLevel [Byte0]: 31
8554 23:07:04.724247 [Byte1]: 31
8555 23:07:04.728635
8556 23:07:04.729108 Set Vref, RX VrefLevel [Byte0]: 32
8557 23:07:04.731991 [Byte1]: 32
8558 23:07:04.736345
8559 23:07:04.736818 Set Vref, RX VrefLevel [Byte0]: 33
8560 23:07:04.739892 [Byte1]: 33
8561 23:07:04.744274
8562 23:07:04.744690 Set Vref, RX VrefLevel [Byte0]: 34
8563 23:07:04.747203 [Byte1]: 34
8564 23:07:04.751545
8565 23:07:04.751960 Set Vref, RX VrefLevel [Byte0]: 35
8566 23:07:04.755415 [Byte1]: 35
8567 23:07:04.759358
8568 23:07:04.759810 Set Vref, RX VrefLevel [Byte0]: 36
8569 23:07:04.762124 [Byte1]: 36
8570 23:07:04.767051
8571 23:07:04.767486 Set Vref, RX VrefLevel [Byte0]: 37
8572 23:07:04.770144 [Byte1]: 37
8573 23:07:04.774296
8574 23:07:04.774709 Set Vref, RX VrefLevel [Byte0]: 38
8575 23:07:04.777409 [Byte1]: 38
8576 23:07:04.781833
8577 23:07:04.782246 Set Vref, RX VrefLevel [Byte0]: 39
8578 23:07:04.785337 [Byte1]: 39
8579 23:07:04.789708
8580 23:07:04.790122 Set Vref, RX VrefLevel [Byte0]: 40
8581 23:07:04.792573 [Byte1]: 40
8582 23:07:04.796833
8583 23:07:04.797247 Set Vref, RX VrefLevel [Byte0]: 41
8584 23:07:04.800180 [Byte1]: 41
8585 23:07:04.804447
8586 23:07:04.804860 Set Vref, RX VrefLevel [Byte0]: 42
8587 23:07:04.807607 [Byte1]: 42
8588 23:07:04.812468
8589 23:07:04.812886 Set Vref, RX VrefLevel [Byte0]: 43
8590 23:07:04.815321 [Byte1]: 43
8591 23:07:04.819531
8592 23:07:04.819947 Set Vref, RX VrefLevel [Byte0]: 44
8593 23:07:04.822976 [Byte1]: 44
8594 23:07:04.827167
8595 23:07:04.827636 Set Vref, RX VrefLevel [Byte0]: 45
8596 23:07:04.831001 [Byte1]: 45
8597 23:07:04.834873
8598 23:07:04.835289 Set Vref, RX VrefLevel [Byte0]: 46
8599 23:07:04.838258 [Byte1]: 46
8600 23:07:04.842423
8601 23:07:04.842837 Set Vref, RX VrefLevel [Byte0]: 47
8602 23:07:04.845604 [Byte1]: 47
8603 23:07:04.850264
8604 23:07:04.850679 Set Vref, RX VrefLevel [Byte0]: 48
8605 23:07:04.853135 [Byte1]: 48
8606 23:07:04.857639
8607 23:07:04.858068 Set Vref, RX VrefLevel [Byte0]: 49
8608 23:07:04.861005 [Byte1]: 49
8609 23:07:04.865101
8610 23:07:04.865518 Set Vref, RX VrefLevel [Byte0]: 50
8611 23:07:04.868455 [Byte1]: 50
8612 23:07:04.872717
8613 23:07:04.873133 Set Vref, RX VrefLevel [Byte0]: 51
8614 23:07:04.875770 [Byte1]: 51
8615 23:07:04.880026
8616 23:07:04.880440 Set Vref, RX VrefLevel [Byte0]: 52
8617 23:07:04.883755 [Byte1]: 52
8618 23:07:04.887704
8619 23:07:04.888118 Set Vref, RX VrefLevel [Byte0]: 53
8620 23:07:04.891270 [Byte1]: 53
8621 23:07:04.895282
8622 23:07:04.895746 Set Vref, RX VrefLevel [Byte0]: 54
8623 23:07:04.898482 [Byte1]: 54
8624 23:07:04.903209
8625 23:07:04.903655 Set Vref, RX VrefLevel [Byte0]: 55
8626 23:07:04.906090 [Byte1]: 55
8627 23:07:04.910435
8628 23:07:04.910849 Set Vref, RX VrefLevel [Byte0]: 56
8629 23:07:04.914029 [Byte1]: 56
8630 23:07:04.918362
8631 23:07:04.918778 Set Vref, RX VrefLevel [Byte0]: 57
8632 23:07:04.921206 [Byte1]: 57
8633 23:07:04.925538
8634 23:07:04.925968 Set Vref, RX VrefLevel [Byte0]: 58
8635 23:07:04.929033 [Byte1]: 58
8636 23:07:04.933298
8637 23:07:04.933712 Set Vref, RX VrefLevel [Byte0]: 59
8638 23:07:04.936558 [Byte1]: 59
8639 23:07:04.940968
8640 23:07:04.941387 Set Vref, RX VrefLevel [Byte0]: 60
8641 23:07:04.944259 [Byte1]: 60
8642 23:07:04.948538
8643 23:07:04.948953 Set Vref, RX VrefLevel [Byte0]: 61
8644 23:07:04.951469 [Byte1]: 61
8645 23:07:04.956189
8646 23:07:04.956602 Set Vref, RX VrefLevel [Byte0]: 62
8647 23:07:04.958997 [Byte1]: 62
8648 23:07:04.963461
8649 23:07:04.963877 Set Vref, RX VrefLevel [Byte0]: 63
8650 23:07:04.966671 [Byte1]: 63
8651 23:07:04.971312
8652 23:07:04.971772 Set Vref, RX VrefLevel [Byte0]: 64
8653 23:07:04.974528 [Byte1]: 64
8654 23:07:04.979062
8655 23:07:04.979603 Set Vref, RX VrefLevel [Byte0]: 65
8656 23:07:04.981901 [Byte1]: 65
8657 23:07:04.986203
8658 23:07:04.986620 Set Vref, RX VrefLevel [Byte0]: 66
8659 23:07:04.989260 [Byte1]: 66
8660 23:07:04.993553
8661 23:07:04.993967 Set Vref, RX VrefLevel [Byte0]: 67
8662 23:07:04.997151 [Byte1]: 67
8663 23:07:05.001483
8664 23:07:05.001920 Set Vref, RX VrefLevel [Byte0]: 68
8665 23:07:05.004921 [Byte1]: 68
8666 23:07:05.008842
8667 23:07:05.009258 Set Vref, RX VrefLevel [Byte0]: 69
8668 23:07:05.012457 [Byte1]: 69
8669 23:07:05.016699
8670 23:07:05.017116 Set Vref, RX VrefLevel [Byte0]: 70
8671 23:07:05.020242 [Byte1]: 70
8672 23:07:05.023916
8673 23:07:05.024332 Final RX Vref Byte 0 = 56 to rank0
8674 23:07:05.027736 Final RX Vref Byte 1 = 64 to rank0
8675 23:07:05.030912 Final RX Vref Byte 0 = 56 to rank1
8676 23:07:05.034064 Final RX Vref Byte 1 = 64 to rank1==
8677 23:07:05.037636 Dram Type= 6, Freq= 0, CH_1, rank 0
8678 23:07:05.043677 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8679 23:07:05.043976 ==
8680 23:07:05.044216 DQS Delay:
8681 23:07:05.044439 DQS0 = 0, DQS1 = 0
8682 23:07:05.047153 DQM Delay:
8683 23:07:05.047484 DQM0 = 133, DQM1 = 130
8684 23:07:05.050149 DQ Delay:
8685 23:07:05.053539 DQ0 =142, DQ1 =130, DQ2 =118, DQ3 =130
8686 23:07:05.057190 DQ4 =130, DQ5 =144, DQ6 =146, DQ7 =126
8687 23:07:05.060076 DQ8 =114, DQ9 =118, DQ10 =132, DQ11 =122
8688 23:07:05.063719 DQ12 =140, DQ13 =140, DQ14 =138, DQ15 =140
8689 23:07:05.064031
8690 23:07:05.064293
8691 23:07:05.064518
8692 23:07:05.067162 [DramC_TX_OE_Calibration] TA2
8693 23:07:05.070070 Original DQ_B0 (3 6) =30, OEN = 27
8694 23:07:05.073733 Original DQ_B1 (3 6) =30, OEN = 27
8695 23:07:05.077450 24, 0x0, End_B0=24 End_B1=24
8696 23:07:05.077939 25, 0x0, End_B0=25 End_B1=25
8697 23:07:05.080414 26, 0x0, End_B0=26 End_B1=26
8698 23:07:05.083321 27, 0x0, End_B0=27 End_B1=27
8699 23:07:05.087032 28, 0x0, End_B0=28 End_B1=28
8700 23:07:05.090081 29, 0x0, End_B0=29 End_B1=29
8701 23:07:05.090674 30, 0x0, End_B0=30 End_B1=30
8702 23:07:05.093659 31, 0x4141, End_B0=30 End_B1=30
8703 23:07:05.096804 Byte0 end_step=30 best_step=27
8704 23:07:05.100408 Byte1 end_step=30 best_step=27
8705 23:07:05.103557 Byte0 TX OE(2T, 0.5T) = (3, 3)
8706 23:07:05.106589 Byte1 TX OE(2T, 0.5T) = (3, 3)
8707 23:07:05.107136
8708 23:07:05.107636
8709 23:07:05.113579 [DQSOSCAuto] RK0, (LSB)MR18= 0xb15, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 404 ps
8710 23:07:05.116334 CH1 RK0: MR19=303, MR18=B15
8711 23:07:05.123192 CH1_RK0: MR19=0x303, MR18=0xB15, DQSOSC=399, MR23=63, INC=23, DEC=15
8712 23:07:05.123690
8713 23:07:05.126759 ----->DramcWriteLeveling(PI) begin...
8714 23:07:05.127437 ==
8715 23:07:05.129408 Dram Type= 6, Freq= 0, CH_1, rank 1
8716 23:07:05.133042 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8717 23:07:05.133560 ==
8718 23:07:05.135919 Write leveling (Byte 0): 26 => 26
8719 23:07:05.139726 Write leveling (Byte 1): 26 => 26
8720 23:07:05.142714 DramcWriteLeveling(PI) end<-----
8721 23:07:05.143270
8722 23:07:05.143848 ==
8723 23:07:05.146564 Dram Type= 6, Freq= 0, CH_1, rank 1
8724 23:07:05.149591 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8725 23:07:05.150084 ==
8726 23:07:05.152654 [Gating] SW mode calibration
8727 23:07:05.159592 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8728 23:07:05.166450 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8729 23:07:05.169144 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8730 23:07:05.175764 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8731 23:07:05.179193 1 4 8 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
8732 23:07:05.182356 1 4 12 | B1->B0 | 2424 3434 | 0 1 | (1 1) (1 1)
8733 23:07:05.188948 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8734 23:07:05.192136 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8735 23:07:05.195186 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8736 23:07:05.202100 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8737 23:07:05.205078 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8738 23:07:05.208944 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8739 23:07:05.214950 1 5 8 | B1->B0 | 3434 2626 | 1 0 | (1 1) (0 1)
8740 23:07:05.218443 1 5 12 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
8741 23:07:05.221871 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8742 23:07:05.228767 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8743 23:07:05.231787 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8744 23:07:05.235164 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8745 23:07:05.241814 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8746 23:07:05.244763 1 6 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
8747 23:07:05.247853 1 6 8 | B1->B0 | 2323 4444 | 0 0 | (0 0) (0 0)
8748 23:07:05.254571 1 6 12 | B1->B0 | 2f2f 4646 | 1 0 | (0 0) (0 0)
8749 23:07:05.257830 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8750 23:07:05.261305 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8751 23:07:05.267900 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8752 23:07:05.271190 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8753 23:07:05.274497 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8754 23:07:05.281204 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8755 23:07:05.284531 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8756 23:07:05.288091 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8757 23:07:05.294164 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8758 23:07:05.297476 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8759 23:07:05.300703 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8760 23:07:05.307168 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8761 23:07:05.310734 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8762 23:07:05.313683 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8763 23:07:05.320085 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8764 23:07:05.323601 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8765 23:07:05.329845 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8766 23:07:05.333532 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8767 23:07:05.336611 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8768 23:07:05.343020 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8769 23:07:05.346699 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8770 23:07:05.349748 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8771 23:07:05.356600 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8772 23:07:05.359608 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8773 23:07:05.363257 Total UI for P1: 0, mck2ui 16
8774 23:07:05.366310 best dqsien dly found for B0: ( 1, 9, 8)
8775 23:07:05.369822 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8776 23:07:05.376542 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8777 23:07:05.377037 Total UI for P1: 0, mck2ui 16
8778 23:07:05.379577 best dqsien dly found for B1: ( 1, 9, 14)
8779 23:07:05.386421 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8780 23:07:05.389622 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8781 23:07:05.390177
8782 23:07:05.392768 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8783 23:07:05.395817 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8784 23:07:05.399099 [Gating] SW calibration Done
8785 23:07:05.399728 ==
8786 23:07:05.402297 Dram Type= 6, Freq= 0, CH_1, rank 1
8787 23:07:05.406082 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8788 23:07:05.406626 ==
8789 23:07:05.409336 RX Vref Scan: 0
8790 23:07:05.409837
8791 23:07:05.410287 RX Vref 0 -> 0, step: 1
8792 23:07:05.410706
8793 23:07:05.412448 RX Delay 0 -> 252, step: 8
8794 23:07:05.415580 iDelay=200, Bit 0, Center 143 (88 ~ 199) 112
8795 23:07:05.422654 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8796 23:07:05.425376 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8797 23:07:05.428888 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8798 23:07:05.432158 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8799 23:07:05.435595 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8800 23:07:05.442115 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8801 23:07:05.445652 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8802 23:07:05.448816 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8803 23:07:05.451653 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8804 23:07:05.455388 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8805 23:07:05.461648 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8806 23:07:05.465354 iDelay=200, Bit 12, Center 139 (80 ~ 199) 120
8807 23:07:05.468357 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8808 23:07:05.471428 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8809 23:07:05.478330 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8810 23:07:05.478776 ==
8811 23:07:05.481356 Dram Type= 6, Freq= 0, CH_1, rank 1
8812 23:07:05.484579 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8813 23:07:05.485022 ==
8814 23:07:05.485363 DQS Delay:
8815 23:07:05.488415 DQS0 = 0, DQS1 = 0
8816 23:07:05.488839 DQM Delay:
8817 23:07:05.491328 DQM0 = 137, DQM1 = 130
8818 23:07:05.491788 DQ Delay:
8819 23:07:05.494348 DQ0 =143, DQ1 =135, DQ2 =127, DQ3 =135
8820 23:07:05.497712 DQ4 =135, DQ5 =147, DQ6 =143, DQ7 =135
8821 23:07:05.501303 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
8822 23:07:05.504551 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =139
8823 23:07:05.507476
8824 23:07:05.507972
8825 23:07:05.508403 ==
8826 23:07:05.510849 Dram Type= 6, Freq= 0, CH_1, rank 1
8827 23:07:05.514165 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8828 23:07:05.514763 ==
8829 23:07:05.515311
8830 23:07:05.515775
8831 23:07:05.517800 TX Vref Scan disable
8832 23:07:05.518228 == TX Byte 0 ==
8833 23:07:05.523984 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8834 23:07:05.527489 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8835 23:07:05.527913 == TX Byte 1 ==
8836 23:07:05.534112 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8837 23:07:05.537248 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8838 23:07:05.537663 ==
8839 23:07:05.540985 Dram Type= 6, Freq= 0, CH_1, rank 1
8840 23:07:05.543794 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8841 23:07:05.544259 ==
8842 23:07:05.558337
8843 23:07:05.562002 TX Vref early break, caculate TX vref
8844 23:07:05.565104 TX Vref=16, minBit 9, minWin=22, winSum=383
8845 23:07:05.568107 TX Vref=18, minBit 9, minWin=22, winSum=387
8846 23:07:05.571689 TX Vref=20, minBit 9, minWin=22, winSum=396
8847 23:07:05.574791 TX Vref=22, minBit 9, minWin=22, winSum=404
8848 23:07:05.578557 TX Vref=24, minBit 9, minWin=24, winSum=411
8849 23:07:05.584609 TX Vref=26, minBit 1, minWin=25, winSum=418
8850 23:07:05.588462 TX Vref=28, minBit 3, minWin=25, winSum=420
8851 23:07:05.591239 TX Vref=30, minBit 9, minWin=25, winSum=422
8852 23:07:05.594872 TX Vref=32, minBit 14, minWin=24, winSum=411
8853 23:07:05.597834 TX Vref=34, minBit 9, minWin=23, winSum=402
8854 23:07:05.604354 TX Vref=36, minBit 9, minWin=23, winSum=390
8855 23:07:05.607973 [TxChooseVref] Worse bit 9, Min win 25, Win sum 422, Final Vref 30
8856 23:07:05.608391
8857 23:07:05.611138 Final TX Range 0 Vref 30
8858 23:07:05.611663
8859 23:07:05.612013 ==
8860 23:07:05.614340 Dram Type= 6, Freq= 0, CH_1, rank 1
8861 23:07:05.617746 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8862 23:07:05.621005 ==
8863 23:07:05.621515
8864 23:07:05.621995
8865 23:07:05.622449 TX Vref Scan disable
8866 23:07:05.627958 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8867 23:07:05.628375 == TX Byte 0 ==
8868 23:07:05.631440 u2DelayCellOfst[0]=14 cells (4 PI)
8869 23:07:05.634624 u2DelayCellOfst[1]=10 cells (3 PI)
8870 23:07:05.637642 u2DelayCellOfst[2]=0 cells (0 PI)
8871 23:07:05.641230 u2DelayCellOfst[3]=7 cells (2 PI)
8872 23:07:05.644354 u2DelayCellOfst[4]=7 cells (2 PI)
8873 23:07:05.647834 u2DelayCellOfst[5]=17 cells (5 PI)
8874 23:07:05.651282 u2DelayCellOfst[6]=17 cells (5 PI)
8875 23:07:05.654115 u2DelayCellOfst[7]=7 cells (2 PI)
8876 23:07:05.657315 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8877 23:07:05.660818 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8878 23:07:05.664343 == TX Byte 1 ==
8879 23:07:05.667680 u2DelayCellOfst[8]=0 cells (0 PI)
8880 23:07:05.670408 u2DelayCellOfst[9]=3 cells (1 PI)
8881 23:07:05.673722 u2DelayCellOfst[10]=14 cells (4 PI)
8882 23:07:05.677267 u2DelayCellOfst[11]=3 cells (1 PI)
8883 23:07:05.680409 u2DelayCellOfst[12]=14 cells (4 PI)
8884 23:07:05.683979 u2DelayCellOfst[13]=17 cells (5 PI)
8885 23:07:05.684398 u2DelayCellOfst[14]=17 cells (5 PI)
8886 23:07:05.687279 u2DelayCellOfst[15]=17 cells (5 PI)
8887 23:07:05.693877 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8888 23:07:05.696833 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8889 23:07:05.700545 DramC Write-DBI on
8890 23:07:05.700960 ==
8891 23:07:05.703342 Dram Type= 6, Freq= 0, CH_1, rank 1
8892 23:07:05.706909 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8893 23:07:05.707329 ==
8894 23:07:05.707715
8895 23:07:05.708028
8896 23:07:05.709949 TX Vref Scan disable
8897 23:07:05.710485 == TX Byte 0 ==
8898 23:07:05.716589 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8899 23:07:05.717033 == TX Byte 1 ==
8900 23:07:05.720533 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8901 23:07:05.723433 DramC Write-DBI off
8902 23:07:05.723849
8903 23:07:05.724185 [DATLAT]
8904 23:07:05.726754 Freq=1600, CH1 RK1
8905 23:07:05.727171
8906 23:07:05.727551 DATLAT Default: 0xf
8907 23:07:05.730070 0, 0xFFFF, sum = 0
8908 23:07:05.730494 1, 0xFFFF, sum = 0
8909 23:07:05.733092 2, 0xFFFF, sum = 0
8910 23:07:05.736356 3, 0xFFFF, sum = 0
8911 23:07:05.736778 4, 0xFFFF, sum = 0
8912 23:07:05.739993 5, 0xFFFF, sum = 0
8913 23:07:05.740417 6, 0xFFFF, sum = 0
8914 23:07:05.743324 7, 0xFFFF, sum = 0
8915 23:07:05.743787 8, 0xFFFF, sum = 0
8916 23:07:05.746439 9, 0xFFFF, sum = 0
8917 23:07:05.746861 10, 0xFFFF, sum = 0
8918 23:07:05.749473 11, 0xFFFF, sum = 0
8919 23:07:05.749898 12, 0xFFFF, sum = 0
8920 23:07:05.752712 13, 0xFFFF, sum = 0
8921 23:07:05.753191 14, 0x0, sum = 1
8922 23:07:05.756052 15, 0x0, sum = 2
8923 23:07:05.756455 16, 0x0, sum = 3
8924 23:07:05.759666 17, 0x0, sum = 4
8925 23:07:05.760059 best_step = 15
8926 23:07:05.760394
8927 23:07:05.760716 ==
8928 23:07:05.762940 Dram Type= 6, Freq= 0, CH_1, rank 1
8929 23:07:05.769417 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8930 23:07:05.769830 ==
8931 23:07:05.770180 RX Vref Scan: 0
8932 23:07:05.770507
8933 23:07:05.772798 RX Vref 0 -> 0, step: 1
8934 23:07:05.773175
8935 23:07:05.776217 RX Delay 19 -> 252, step: 4
8936 23:07:05.779025 iDelay=195, Bit 0, Center 138 (91 ~ 186) 96
8937 23:07:05.782480 iDelay=195, Bit 1, Center 132 (83 ~ 182) 100
8938 23:07:05.786088 iDelay=195, Bit 2, Center 122 (71 ~ 174) 104
8939 23:07:05.792064 iDelay=195, Bit 3, Center 130 (79 ~ 182) 104
8940 23:07:05.795913 iDelay=195, Bit 4, Center 132 (79 ~ 186) 108
8941 23:07:05.798888 iDelay=195, Bit 5, Center 144 (95 ~ 194) 100
8942 23:07:05.801989 iDelay=195, Bit 6, Center 142 (91 ~ 194) 104
8943 23:07:05.809130 iDelay=195, Bit 7, Center 130 (79 ~ 182) 104
8944 23:07:05.812137 iDelay=195, Bit 8, Center 114 (63 ~ 166) 104
8945 23:07:05.815220 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8946 23:07:05.818894 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8947 23:07:05.822034 iDelay=195, Bit 11, Center 122 (71 ~ 174) 104
8948 23:07:05.828562 iDelay=195, Bit 12, Center 136 (83 ~ 190) 108
8949 23:07:05.832032 iDelay=195, Bit 13, Center 136 (83 ~ 190) 108
8950 23:07:05.835055 iDelay=195, Bit 14, Center 132 (79 ~ 186) 108
8951 23:07:05.838669 iDelay=195, Bit 15, Center 138 (87 ~ 190) 104
8952 23:07:05.839139 ==
8953 23:07:05.841756 Dram Type= 6, Freq= 0, CH_1, rank 1
8954 23:07:05.848269 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8955 23:07:05.848719 ==
8956 23:07:05.849080 DQS Delay:
8957 23:07:05.851425 DQS0 = 0, DQS1 = 0
8958 23:07:05.851931 DQM Delay:
8959 23:07:05.854703 DQM0 = 133, DQM1 = 128
8960 23:07:05.855177 DQ Delay:
8961 23:07:05.857794 DQ0 =138, DQ1 =132, DQ2 =122, DQ3 =130
8962 23:07:05.861163 DQ4 =132, DQ5 =144, DQ6 =142, DQ7 =130
8963 23:07:05.864712 DQ8 =114, DQ9 =118, DQ10 =128, DQ11 =122
8964 23:07:05.867740 DQ12 =136, DQ13 =136, DQ14 =132, DQ15 =138
8965 23:07:05.868154
8966 23:07:05.868484
8967 23:07:05.868793
8968 23:07:05.871138 [DramC_TX_OE_Calibration] TA2
8969 23:07:05.874393 Original DQ_B0 (3 6) =30, OEN = 27
8970 23:07:05.878013 Original DQ_B1 (3 6) =30, OEN = 27
8971 23:07:05.880951 24, 0x0, End_B0=24 End_B1=24
8972 23:07:05.884417 25, 0x0, End_B0=25 End_B1=25
8973 23:07:05.884863 26, 0x0, End_B0=26 End_B1=26
8974 23:07:05.887336 27, 0x0, End_B0=27 End_B1=27
8975 23:07:05.890602 28, 0x0, End_B0=28 End_B1=28
8976 23:07:05.894100 29, 0x0, End_B0=29 End_B1=29
8977 23:07:05.897328 30, 0x0, End_B0=30 End_B1=30
8978 23:07:05.897755 31, 0x4545, End_B0=30 End_B1=30
8979 23:07:05.901008 Byte0 end_step=30 best_step=27
8980 23:07:05.904057 Byte1 end_step=30 best_step=27
8981 23:07:05.907297 Byte0 TX OE(2T, 0.5T) = (3, 3)
8982 23:07:05.910878 Byte1 TX OE(2T, 0.5T) = (3, 3)
8983 23:07:05.911304
8984 23:07:05.911807
8985 23:07:05.917354 [DQSOSCAuto] RK1, (LSB)MR18= 0xd1b, (MSB)MR19= 0x303, tDQSOscB0 = 396 ps tDQSOscB1 = 403 ps
8986 23:07:05.920391 CH1 RK1: MR19=303, MR18=D1B
8987 23:07:05.926869 CH1_RK1: MR19=0x303, MR18=0xD1B, DQSOSC=396, MR23=63, INC=23, DEC=15
8988 23:07:05.930433 [RxdqsGatingPostProcess] freq 1600
8989 23:07:05.936887 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8990 23:07:05.940181 best DQS0 dly(2T, 0.5T) = (1, 1)
8991 23:07:05.940616 best DQS1 dly(2T, 0.5T) = (1, 1)
8992 23:07:05.943736 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8993 23:07:05.946656 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8994 23:07:05.949826 best DQS0 dly(2T, 0.5T) = (1, 1)
8995 23:07:05.953794 best DQS1 dly(2T, 0.5T) = (1, 1)
8996 23:07:05.956591 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8997 23:07:05.960254 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8998 23:07:05.963174 Pre-setting of DQS Precalculation
8999 23:07:05.966685 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9000 23:07:05.976495 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9001 23:07:05.983343 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9002 23:07:05.983812
9003 23:07:05.984160
9004 23:07:05.986523 [Calibration Summary] 3200 Mbps
9005 23:07:05.986956 CH 0, Rank 0
9006 23:07:05.989831 SW Impedance : PASS
9007 23:07:05.990258 DUTY Scan : NO K
9008 23:07:05.992946 ZQ Calibration : PASS
9009 23:07:05.995961 Jitter Meter : NO K
9010 23:07:05.996522 CBT Training : PASS
9011 23:07:05.999470 Write leveling : PASS
9012 23:07:06.002632 RX DQS gating : PASS
9013 23:07:06.003059 RX DQ/DQS(RDDQC) : PASS
9014 23:07:06.006398 TX DQ/DQS : PASS
9015 23:07:06.009425 RX DATLAT : PASS
9016 23:07:06.009916 RX DQ/DQS(Engine): PASS
9017 23:07:06.012415 TX OE : PASS
9018 23:07:06.012843 All Pass.
9019 23:07:06.013172
9020 23:07:06.015930 CH 0, Rank 1
9021 23:07:06.016355 SW Impedance : PASS
9022 23:07:06.019497 DUTY Scan : NO K
9023 23:07:06.022538 ZQ Calibration : PASS
9024 23:07:06.022969 Jitter Meter : NO K
9025 23:07:06.025556 CBT Training : PASS
9026 23:07:06.029512 Write leveling : PASS
9027 23:07:06.029950 RX DQS gating : PASS
9028 23:07:06.032419 RX DQ/DQS(RDDQC) : PASS
9029 23:07:06.035880 TX DQ/DQS : PASS
9030 23:07:06.036311 RX DATLAT : PASS
9031 23:07:06.038944 RX DQ/DQS(Engine): PASS
9032 23:07:06.042412 TX OE : PASS
9033 23:07:06.042858 All Pass.
9034 23:07:06.043200
9035 23:07:06.043623 CH 1, Rank 0
9036 23:07:06.045348 SW Impedance : PASS
9037 23:07:06.048674 DUTY Scan : NO K
9038 23:07:06.049108 ZQ Calibration : PASS
9039 23:07:06.052193 Jitter Meter : NO K
9040 23:07:06.055314 CBT Training : PASS
9041 23:07:06.055829 Write leveling : PASS
9042 23:07:06.059044 RX DQS gating : PASS
9043 23:07:06.062065 RX DQ/DQS(RDDQC) : PASS
9044 23:07:06.062499 TX DQ/DQS : PASS
9045 23:07:06.065050 RX DATLAT : PASS
9046 23:07:06.068816 RX DQ/DQS(Engine): PASS
9047 23:07:06.069245 TX OE : PASS
9048 23:07:06.069604 All Pass.
9049 23:07:06.071968
9050 23:07:06.072413 CH 1, Rank 1
9051 23:07:06.074987 SW Impedance : PASS
9052 23:07:06.075478 DUTY Scan : NO K
9053 23:07:06.078619 ZQ Calibration : PASS
9054 23:07:06.081840 Jitter Meter : NO K
9055 23:07:06.082272 CBT Training : PASS
9056 23:07:06.085097 Write leveling : PASS
9057 23:07:06.085526 RX DQS gating : PASS
9058 23:07:06.088340 RX DQ/DQS(RDDQC) : PASS
9059 23:07:06.091900 TX DQ/DQS : PASS
9060 23:07:06.092331 RX DATLAT : PASS
9061 23:07:06.094727 RX DQ/DQS(Engine): PASS
9062 23:07:06.098207 TX OE : PASS
9063 23:07:06.098638 All Pass.
9064 23:07:06.099075
9065 23:07:06.101493 DramC Write-DBI on
9066 23:07:06.101921 PER_BANK_REFRESH: Hybrid Mode
9067 23:07:06.104599 TX_TRACKING: ON
9068 23:07:06.114317 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9069 23:07:06.121330 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9070 23:07:06.127865 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9071 23:07:06.130870 [FAST_K] Save calibration result to emmc
9072 23:07:06.134569 sync common calibartion params.
9073 23:07:06.137471 sync cbt_mode0:1, 1:1
9074 23:07:06.141059 dram_init: ddr_geometry: 2
9075 23:07:06.141474 dram_init: ddr_geometry: 2
9076 23:07:06.144053 dram_init: ddr_geometry: 2
9077 23:07:06.147299 0:dram_rank_size:100000000
9078 23:07:06.147767 1:dram_rank_size:100000000
9079 23:07:06.153832 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9080 23:07:06.157744 DFS_SHUFFLE_HW_MODE: ON
9081 23:07:06.160546 dramc_set_vcore_voltage set vcore to 725000
9082 23:07:06.163742 Read voltage for 1600, 0
9083 23:07:06.164156 Vio18 = 0
9084 23:07:06.164487 Vcore = 725000
9085 23:07:06.167257 Vdram = 0
9086 23:07:06.167705 Vddq = 0
9087 23:07:06.168039 Vmddr = 0
9088 23:07:06.170306 switch to 3200 Mbps bootup
9089 23:07:06.174160 [DramcRunTimeConfig]
9090 23:07:06.174573 PHYPLL
9091 23:07:06.174902 DPM_CONTROL_AFTERK: ON
9092 23:07:06.177259 PER_BANK_REFRESH: ON
9093 23:07:06.180100 REFRESH_OVERHEAD_REDUCTION: ON
9094 23:07:06.180522 CMD_PICG_NEW_MODE: OFF
9095 23:07:06.183880 XRTWTW_NEW_MODE: ON
9096 23:07:06.187316 XRTRTR_NEW_MODE: ON
9097 23:07:06.187765 TX_TRACKING: ON
9098 23:07:06.190433 RDSEL_TRACKING: OFF
9099 23:07:06.190845 DQS Precalculation for DVFS: ON
9100 23:07:06.193725 RX_TRACKING: OFF
9101 23:07:06.194140 HW_GATING DBG: ON
9102 23:07:06.197058 ZQCS_ENABLE_LP4: ON
9103 23:07:06.197473 RX_PICG_NEW_MODE: ON
9104 23:07:06.200382 TX_PICG_NEW_MODE: ON
9105 23:07:06.203434 ENABLE_RX_DCM_DPHY: ON
9106 23:07:06.206964 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9107 23:07:06.207420 DUMMY_READ_FOR_TRACKING: OFF
9108 23:07:06.210517 !!! SPM_CONTROL_AFTERK: OFF
9109 23:07:06.213588 !!! SPM could not control APHY
9110 23:07:06.216655 IMPEDANCE_TRACKING: ON
9111 23:07:06.217071 TEMP_SENSOR: ON
9112 23:07:06.220399 HW_SAVE_FOR_SR: OFF
9113 23:07:06.220810 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9114 23:07:06.226735 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9115 23:07:06.227152 Read ODT Tracking: ON
9116 23:07:06.229651 Refresh Rate DeBounce: ON
9117 23:07:06.233123 DFS_NO_QUEUE_FLUSH: ON
9118 23:07:06.236596 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9119 23:07:06.237010 ENABLE_DFS_RUNTIME_MRW: OFF
9120 23:07:06.239892 DDR_RESERVE_NEW_MODE: ON
9121 23:07:06.243304 MR_CBT_SWITCH_FREQ: ON
9122 23:07:06.243769 =========================
9123 23:07:06.262871 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9124 23:07:06.265958 dram_init: ddr_geometry: 2
9125 23:07:06.284277 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9126 23:07:06.287350 dram_init: dram init end (result: 0)
9127 23:07:06.294439 DRAM-K: Full calibration passed in 24410 msecs
9128 23:07:06.297501 MRC: failed to locate region type 0.
9129 23:07:06.297915 DRAM rank0 size:0x100000000,
9130 23:07:06.300572 DRAM rank1 size=0x100000000
9131 23:07:06.310428 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9132 23:07:06.316857 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9133 23:07:06.326879 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9134 23:07:06.333231 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9135 23:07:06.333758 DRAM rank0 size:0x100000000,
9136 23:07:06.336938 DRAM rank1 size=0x100000000
9137 23:07:06.337412 CBMEM:
9138 23:07:06.340088 IMD: root @ 0xfffff000 254 entries.
9139 23:07:06.343407 IMD: root @ 0xffffec00 62 entries.
9140 23:07:06.349909 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9141 23:07:06.353659 WARNING: RO_VPD is uninitialized or empty.
9142 23:07:06.356522 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9143 23:07:06.364213 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9144 23:07:06.377180 read SPI 0x42894 0xe01e: 6226 us, 9215 KB/s, 73.720 Mbps
9145 23:07:06.388599 BS: romstage times (exec / console): total (unknown) / 23944 ms
9146 23:07:06.389173
9147 23:07:06.389652
9148 23:07:06.398278 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9149 23:07:06.401841 ARM64: Exception handlers installed.
9150 23:07:06.404876 ARM64: Testing exception
9151 23:07:06.407840 ARM64: Done test exception
9152 23:07:06.408387 Enumerating buses...
9153 23:07:06.411573 Show all devs... Before device enumeration.
9154 23:07:06.414850 Root Device: enabled 1
9155 23:07:06.418148 CPU_CLUSTER: 0: enabled 1
9156 23:07:06.418563 CPU: 00: enabled 1
9157 23:07:06.421205 Compare with tree...
9158 23:07:06.421620 Root Device: enabled 1
9159 23:07:06.424289 CPU_CLUSTER: 0: enabled 1
9160 23:07:06.427611 CPU: 00: enabled 1
9161 23:07:06.428030 Root Device scanning...
9162 23:07:06.431024 scan_static_bus for Root Device
9163 23:07:06.434639 CPU_CLUSTER: 0 enabled
9164 23:07:06.437516 scan_static_bus for Root Device done
9165 23:07:06.441377 scan_bus: bus Root Device finished in 8 msecs
9166 23:07:06.441790 done
9167 23:07:06.447831 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9168 23:07:06.451048 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9169 23:07:06.457460 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9170 23:07:06.463846 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9171 23:07:06.464310 Allocating resources...
9172 23:07:06.467082 Reading resources...
9173 23:07:06.470439 Root Device read_resources bus 0 link: 0
9174 23:07:06.473685 DRAM rank0 size:0x100000000,
9175 23:07:06.474103 DRAM rank1 size=0x100000000
9176 23:07:06.480728 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9177 23:07:06.481145 CPU: 00 missing read_resources
9178 23:07:06.487258 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9179 23:07:06.490370 Root Device read_resources bus 0 link: 0 done
9180 23:07:06.493957 Done reading resources.
9181 23:07:06.497063 Show resources in subtree (Root Device)...After reading.
9182 23:07:06.500066 Root Device child on link 0 CPU_CLUSTER: 0
9183 23:07:06.503655 CPU_CLUSTER: 0 child on link 0 CPU: 00
9184 23:07:06.513944 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9185 23:07:06.514517 CPU: 00
9186 23:07:06.520041 Root Device assign_resources, bus 0 link: 0
9187 23:07:06.523556 CPU_CLUSTER: 0 missing set_resources
9188 23:07:06.526905 Root Device assign_resources, bus 0 link: 0 done
9189 23:07:06.529925 Done setting resources.
9190 23:07:06.533656 Show resources in subtree (Root Device)...After assigning values.
9191 23:07:06.536738 Root Device child on link 0 CPU_CLUSTER: 0
9192 23:07:06.543560 CPU_CLUSTER: 0 child on link 0 CPU: 00
9193 23:07:06.549499 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9194 23:07:06.553061 CPU: 00
9195 23:07:06.553506 Done allocating resources.
9196 23:07:06.559342 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9197 23:07:06.562804 Enabling resources...
9198 23:07:06.563193 done.
9199 23:07:06.565901 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9200 23:07:06.569590 Initializing devices...
9201 23:07:06.570046 Root Device init
9202 23:07:06.572734 init hardware done!
9203 23:07:06.575993 0x00000018: ctrlr->caps
9204 23:07:06.576519 52.000 MHz: ctrlr->f_max
9205 23:07:06.579173 0.400 MHz: ctrlr->f_min
9206 23:07:06.582499 0x40ff8080: ctrlr->voltages
9207 23:07:06.582941 sclk: 390625
9208 23:07:06.583413 Bus Width = 1
9209 23:07:06.585927 sclk: 390625
9210 23:07:06.586356 Bus Width = 1
9211 23:07:06.589041 Early init status = 3
9212 23:07:06.592246 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9213 23:07:06.596543 in-header: 03 fc 00 00 01 00 00 00
9214 23:07:06.600183 in-data: 00
9215 23:07:06.603449 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9216 23:07:06.608573 in-header: 03 fd 00 00 00 00 00 00
9217 23:07:06.612333 in-data:
9218 23:07:06.615466 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9219 23:07:06.619563 in-header: 03 fc 00 00 01 00 00 00
9220 23:07:06.622765 in-data: 00
9221 23:07:06.626544 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9222 23:07:06.631629 in-header: 03 fd 00 00 00 00 00 00
9223 23:07:06.635034 in-data:
9224 23:07:06.638472 [SSUSB] Setting up USB HOST controller...
9225 23:07:06.641490 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9226 23:07:06.645217 [SSUSB] phy power-on done.
9227 23:07:06.648079 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9228 23:07:06.654781 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9229 23:07:06.658396 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9230 23:07:06.665057 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9231 23:07:06.671424 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9232 23:07:06.677919 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9233 23:07:06.684637 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9234 23:07:06.691192 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9235 23:07:06.694846 SPM: binary array size = 0x9dc
9236 23:07:06.697941 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9237 23:07:06.704193 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9238 23:07:06.710951 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9239 23:07:06.717507 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9240 23:07:06.721144 configure_display: Starting display init
9241 23:07:06.754982 anx7625_power_on_init: Init interface.
9242 23:07:06.758055 anx7625_disable_pd_protocol: Disabled PD feature.
9243 23:07:06.761921 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9244 23:07:06.789332 anx7625_start_dp_work: Secure OCM version=00
9245 23:07:06.792794 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9246 23:07:06.807733 sp_tx_get_edid_block: EDID Block = 1
9247 23:07:06.909593 Extracted contents:
9248 23:07:06.912898 header: 00 ff ff ff ff ff ff 00
9249 23:07:06.916437 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9250 23:07:06.919585 version: 01 04
9251 23:07:06.922843 basic params: 95 1f 11 78 0a
9252 23:07:06.926129 chroma info: 76 90 94 55 54 90 27 21 50 54
9253 23:07:06.929713 established: 00 00 00
9254 23:07:06.935868 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9255 23:07:06.942527 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9256 23:07:06.946007 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9257 23:07:06.953019 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9258 23:07:06.959350 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9259 23:07:06.962321 extensions: 00
9260 23:07:06.962402 checksum: fb
9261 23:07:06.962467
9262 23:07:06.965719 Manufacturer: IVO Model 57d Serial Number 0
9263 23:07:06.969329 Made week 0 of 2020
9264 23:07:06.972324 EDID version: 1.4
9265 23:07:06.972404 Digital display
9266 23:07:06.976002 6 bits per primary color channel
9267 23:07:06.976085 DisplayPort interface
9268 23:07:06.979157 Maximum image size: 31 cm x 17 cm
9269 23:07:06.982435 Gamma: 220%
9270 23:07:06.982516 Check DPMS levels
9271 23:07:06.985512 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9272 23:07:06.992211 First detailed timing is preferred timing
9273 23:07:06.992293 Established timings supported:
9274 23:07:06.995991 Standard timings supported:
9275 23:07:06.998995 Detailed timings
9276 23:07:07.002059 Hex of detail: 383680a07038204018303c0035ae10000019
9277 23:07:07.008774 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9278 23:07:07.011801 0780 0798 07c8 0820 hborder 0
9279 23:07:07.015463 0438 043b 0447 0458 vborder 0
9280 23:07:07.018651 -hsync -vsync
9281 23:07:07.018732 Did detailed timing
9282 23:07:07.025083 Hex of detail: 000000000000000000000000000000000000
9283 23:07:07.028389 Manufacturer-specified data, tag 0
9284 23:07:07.031582 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9285 23:07:07.035351 ASCII string: InfoVision
9286 23:07:07.038068 Hex of detail: 000000fe00523134304e574635205248200a
9287 23:07:07.041393 ASCII string: R140NWF5 RH
9288 23:07:07.041475 Checksum
9289 23:07:07.045216 Checksum: 0xfb (valid)
9290 23:07:07.048033 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9291 23:07:07.051606 DSI data_rate: 832800000 bps
9292 23:07:07.057817 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9293 23:07:07.060993 anx7625_parse_edid: pixelclock(138800).
9294 23:07:07.064915 hactive(1920), hsync(48), hfp(24), hbp(88)
9295 23:07:07.068243 vactive(1080), vsync(12), vfp(3), vbp(17)
9296 23:07:07.070818 anx7625_dsi_config: config dsi.
9297 23:07:07.077515 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9298 23:07:07.091861 anx7625_dsi_config: success to config DSI
9299 23:07:07.095017 anx7625_dp_start: MIPI phy setup OK.
9300 23:07:07.098638 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9301 23:07:07.101761 mtk_ddp_mode_set invalid vrefresh 60
9302 23:07:07.104667 main_disp_path_setup
9303 23:07:07.104747 ovl_layer_smi_id_en
9304 23:07:07.108302 ovl_layer_smi_id_en
9305 23:07:07.108383 ccorr_config
9306 23:07:07.108447 aal_config
9307 23:07:07.111331 gamma_config
9308 23:07:07.111435 postmask_config
9309 23:07:07.114474 dither_config
9310 23:07:07.118190 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9311 23:07:07.124402 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9312 23:07:07.127996 Root Device init finished in 554 msecs
9313 23:07:07.130991 CPU_CLUSTER: 0 init
9314 23:07:07.137719 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9315 23:07:07.144189 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9316 23:07:07.144269 APU_MBOX 0x190000b0 = 0x10001
9317 23:07:07.147509 APU_MBOX 0x190001b0 = 0x10001
9318 23:07:07.150660 APU_MBOX 0x190005b0 = 0x10001
9319 23:07:07.154504 APU_MBOX 0x190006b0 = 0x10001
9320 23:07:07.160605 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9321 23:07:07.170952 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9322 23:07:07.183399 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9323 23:07:07.189512 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9324 23:07:07.201527 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9325 23:07:07.210288 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9326 23:07:07.213768 CPU_CLUSTER: 0 init finished in 81 msecs
9327 23:07:07.216881 Devices initialized
9328 23:07:07.220532 Show all devs... After init.
9329 23:07:07.220612 Root Device: enabled 1
9330 23:07:07.223495 CPU_CLUSTER: 0: enabled 1
9331 23:07:07.227259 CPU: 00: enabled 1
9332 23:07:07.230283 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9333 23:07:07.233341 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9334 23:07:07.237007 ELOG: NV offset 0x57f000 size 0x1000
9335 23:07:07.243722 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9336 23:07:07.250448 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9337 23:07:07.253519 ELOG: Event(17) added with size 13 at 2023-12-27 23:07:11 UTC
9338 23:07:07.260291 out: cmd=0x121: 03 db 21 01 00 00 00 00
9339 23:07:07.263240 in-header: 03 3a 00 00 2c 00 00 00
9340 23:07:07.273396 in-data: 25 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9341 23:07:07.279735 ELOG: Event(A1) added with size 10 at 2023-12-27 23:07:11 UTC
9342 23:07:07.286698 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9343 23:07:07.293293 ELOG: Event(A0) added with size 9 at 2023-12-27 23:07:11 UTC
9344 23:07:07.296342 elog_add_boot_reason: Logged dev mode boot
9345 23:07:07.302995 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9346 23:07:07.303076 Finalize devices...
9347 23:07:07.306140 Devices finalized
9348 23:07:07.309495 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9349 23:07:07.312803 Writing coreboot table at 0xffe64000
9350 23:07:07.316297 0. 000000000010a000-0000000000113fff: RAMSTAGE
9351 23:07:07.322479 1. 0000000040000000-00000000400fffff: RAM
9352 23:07:07.326050 2. 0000000040100000-000000004032afff: RAMSTAGE
9353 23:07:07.329089 3. 000000004032b000-00000000545fffff: RAM
9354 23:07:07.332491 4. 0000000054600000-000000005465ffff: BL31
9355 23:07:07.336182 5. 0000000054660000-00000000ffe63fff: RAM
9356 23:07:07.342254 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9357 23:07:07.345938 7. 0000000100000000-000000023fffffff: RAM
9358 23:07:07.348907 Passing 5 GPIOs to payload:
9359 23:07:07.352559 NAME | PORT | POLARITY | VALUE
9360 23:07:07.358768 EC in RW | 0x000000aa | low | undefined
9361 23:07:07.362513 EC interrupt | 0x00000005 | low | undefined
9362 23:07:07.365425 TPM interrupt | 0x000000ab | high | undefined
9363 23:07:07.372028 SD card detect | 0x00000011 | high | undefined
9364 23:07:07.375707 speaker enable | 0x00000093 | high | undefined
9365 23:07:07.378645 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9366 23:07:07.382550 in-header: 03 f9 00 00 02 00 00 00
9367 23:07:07.386117 in-data: 02 00
9368 23:07:07.389111 ADC[4]: Raw value=903694 ID=7
9369 23:07:07.392293 ADC[3]: Raw value=213546 ID=1
9370 23:07:07.392374 RAM Code: 0x71
9371 23:07:07.395581 ADC[6]: Raw value=74630 ID=0
9372 23:07:07.399239 ADC[5]: Raw value=213916 ID=1
9373 23:07:07.399320 SKU Code: 0x1
9374 23:07:07.406078 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum f720
9375 23:07:07.406159 coreboot table: 964 bytes.
9376 23:07:07.409333 IMD ROOT 0. 0xfffff000 0x00001000
9377 23:07:07.412159 IMD SMALL 1. 0xffffe000 0x00001000
9378 23:07:07.415899 RO MCACHE 2. 0xffffc000 0x00001104
9379 23:07:07.419021 CONSOLE 3. 0xfff7c000 0x00080000
9380 23:07:07.422157 FMAP 4. 0xfff7b000 0x00000452
9381 23:07:07.425759 TIME STAMP 5. 0xfff7a000 0x00000910
9382 23:07:07.429378 VBOOT WORK 6. 0xfff66000 0x00014000
9383 23:07:07.432514 RAMOOPS 7. 0xffe66000 0x00100000
9384 23:07:07.435852 COREBOOT 8. 0xffe64000 0x00002000
9385 23:07:07.439140 IMD small region:
9386 23:07:07.442449 IMD ROOT 0. 0xffffec00 0x00000400
9387 23:07:07.445857 VPD 1. 0xffffeb80 0x0000006c
9388 23:07:07.448892 MMC STATUS 2. 0xffffeb60 0x00000004
9389 23:07:07.452252 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9390 23:07:07.455260 Probing TPM: done!
9391 23:07:07.458834 Connected to device vid:did:rid of 1ae0:0028:00
9392 23:07:07.470100 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
9393 23:07:07.472937 Initialized TPM device CR50 revision 0
9394 23:07:07.476627 Checking cr50 for pending updates
9395 23:07:07.480988 Reading cr50 TPM mode
9396 23:07:07.489336 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9397 23:07:07.496203 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9398 23:07:07.536013 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9399 23:07:07.539494 Checking segment from ROM address 0x40100000
9400 23:07:07.542832 Checking segment from ROM address 0x4010001c
9401 23:07:07.549506 Loading segment from ROM address 0x40100000
9402 23:07:07.549584 code (compression=0)
9403 23:07:07.559714 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9404 23:07:07.566215 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9405 23:07:07.566318 it's not compressed!
9406 23:07:07.572982 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9407 23:07:07.576118 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9408 23:07:07.596502 Loading segment from ROM address 0x4010001c
9409 23:07:07.596590 Entry Point 0x80000000
9410 23:07:07.600005 Loaded segments
9411 23:07:07.603073 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9412 23:07:07.609937 Jumping to boot code at 0x80000000(0xffe64000)
9413 23:07:07.616690 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9414 23:07:07.623356 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9415 23:07:07.631346 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9416 23:07:07.634029 Checking segment from ROM address 0x40100000
9417 23:07:07.637557 Checking segment from ROM address 0x4010001c
9418 23:07:07.644242 Loading segment from ROM address 0x40100000
9419 23:07:07.644365 code (compression=1)
9420 23:07:07.651175 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9421 23:07:07.660739 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9422 23:07:07.660852 using LZMA
9423 23:07:07.669144 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9424 23:07:07.676052 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9425 23:07:07.679339 Loading segment from ROM address 0x4010001c
9426 23:07:07.679458 Entry Point 0x54601000
9427 23:07:07.682920 Loaded segments
9428 23:07:07.685722 NOTICE: MT8192 bl31_setup
9429 23:07:07.693168 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9430 23:07:07.696382 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9431 23:07:07.699719 WARNING: region 0:
9432 23:07:07.703106 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9433 23:07:07.703207 WARNING: region 1:
9434 23:07:07.709456 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9435 23:07:07.712674 WARNING: region 2:
9436 23:07:07.716115 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9437 23:07:07.719326 WARNING: region 3:
9438 23:07:07.722647 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9439 23:07:07.725960 WARNING: region 4:
9440 23:07:07.732824 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9441 23:07:07.732940 WARNING: region 5:
9442 23:07:07.735954 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9443 23:07:07.739115 WARNING: region 6:
9444 23:07:07.742856 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9445 23:07:07.746481 WARNING: region 7:
9446 23:07:07.749036 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9447 23:07:07.755843 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9448 23:07:07.759368 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9449 23:07:07.762480 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9450 23:07:07.769467 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9451 23:07:07.772456 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9452 23:07:07.776078 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9453 23:07:07.782424 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9454 23:07:07.786159 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9455 23:07:07.792284 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9456 23:07:07.795898 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9457 23:07:07.799090 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9458 23:07:07.805603 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9459 23:07:07.808930 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9460 23:07:07.812454 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9461 23:07:07.818804 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9462 23:07:07.822439 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9463 23:07:07.828760 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9464 23:07:07.832055 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9465 23:07:07.835378 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9466 23:07:07.842017 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9467 23:07:07.845450 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9468 23:07:07.851962 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9469 23:07:07.855547 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9470 23:07:07.858642 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9471 23:07:07.865400 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9472 23:07:07.869003 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9473 23:07:07.875445 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9474 23:07:07.878459 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9475 23:07:07.882100 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9476 23:07:07.888888 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9477 23:07:07.892077 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9478 23:07:07.899059 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9479 23:07:07.901840 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9480 23:07:07.905493 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9481 23:07:07.908459 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9482 23:07:07.915408 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9483 23:07:07.919068 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9484 23:07:07.922030 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9485 23:07:07.925547 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9486 23:07:07.928667 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9487 23:07:07.935520 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9488 23:07:07.938930 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9489 23:07:07.941857 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9490 23:07:07.948856 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9491 23:07:07.951754 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9492 23:07:07.955298 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9493 23:07:07.958450 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9494 23:07:07.965100 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9495 23:07:07.968689 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9496 23:07:07.971946 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9497 23:07:07.978237 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9498 23:07:07.981540 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9499 23:07:07.988188 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9500 23:07:07.991886 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9501 23:07:07.998522 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9502 23:07:08.001877 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9503 23:07:08.004721 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9504 23:07:08.011356 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9505 23:07:08.015122 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9506 23:07:08.021713 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9507 23:07:08.025164 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9508 23:07:08.031613 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9509 23:07:08.034713 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9510 23:07:08.041399 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9511 23:07:08.044966 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9512 23:07:08.051783 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9513 23:07:08.054776 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9514 23:07:08.057912 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9515 23:07:08.064818 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9516 23:07:08.068243 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9517 23:07:08.074555 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9518 23:07:08.077717 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9519 23:07:08.084604 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9520 23:07:08.088128 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9521 23:07:08.091299 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9522 23:07:08.097661 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9523 23:07:08.101515 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9524 23:07:08.107892 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9525 23:07:08.111472 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9526 23:07:08.117697 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9527 23:07:08.121355 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9528 23:07:08.124823 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9529 23:07:08.131167 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9530 23:07:08.134935 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9531 23:07:08.141453 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9532 23:07:08.144416 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9533 23:07:08.150994 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9534 23:07:08.154388 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9535 23:07:08.157785 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9536 23:07:08.164372 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9537 23:07:08.167961 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9538 23:07:08.174444 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9539 23:07:08.177597 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9540 23:07:08.184604 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9541 23:07:08.187659 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9542 23:07:08.194626 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9543 23:07:08.197504 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9544 23:07:08.200852 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9545 23:07:08.204235 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9546 23:07:08.210730 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9547 23:07:08.214045 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9548 23:07:08.217643 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9549 23:07:08.224191 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9550 23:07:08.227748 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9551 23:07:08.233894 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9552 23:07:08.237292 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9553 23:07:08.240889 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9554 23:07:08.247589 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9555 23:07:08.250707 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9556 23:07:08.256986 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9557 23:07:08.260657 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9558 23:07:08.263782 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9559 23:07:08.270082 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9560 23:07:08.273804 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9561 23:07:08.280390 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9562 23:07:08.283629 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9563 23:07:08.286801 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9564 23:07:08.293360 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9565 23:07:08.296592 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9566 23:07:08.300330 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9567 23:07:08.303225 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9568 23:07:08.310598 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9569 23:07:08.313829 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9570 23:07:08.316905 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9571 23:07:08.320632 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9572 23:07:08.326683 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9573 23:07:08.330070 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9574 23:07:08.336794 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9575 23:07:08.340267 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9576 23:07:08.343418 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9577 23:07:08.350013 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9578 23:07:08.353116 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9579 23:07:08.360275 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9580 23:07:08.363435 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9581 23:07:08.366479 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9582 23:07:08.373007 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9583 23:07:08.376640 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9584 23:07:08.383000 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9585 23:07:08.386616 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9586 23:07:08.389919 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9587 23:07:08.396570 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9588 23:07:08.399527 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9589 23:07:08.406462 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9590 23:07:08.409998 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9591 23:07:08.412952 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9592 23:07:08.419565 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9593 23:07:08.422767 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9594 23:07:08.429466 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9595 23:07:08.432926 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9596 23:07:08.436140 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9597 23:07:08.443006 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9598 23:07:08.446366 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9599 23:07:08.449373 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9600 23:07:08.456246 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9601 23:07:08.459855 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9602 23:07:08.466059 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9603 23:07:08.469323 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9604 23:07:08.472654 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9605 23:07:08.479648 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9606 23:07:08.482656 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9607 23:07:08.489235 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9608 23:07:08.492943 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9609 23:07:08.496052 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9610 23:07:08.502834 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9611 23:07:08.505990 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9612 23:07:08.512542 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9613 23:07:08.516107 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9614 23:07:08.519318 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9615 23:07:08.525814 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9616 23:07:08.529025 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9617 23:07:08.535242 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9618 23:07:08.539018 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9619 23:07:08.541798 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9620 23:07:08.549025 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9621 23:07:08.551989 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9622 23:07:08.558866 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9623 23:07:08.561922 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9624 23:07:08.565557 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9625 23:07:08.571798 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9626 23:07:08.574941 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9627 23:07:08.582255 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9628 23:07:08.584863 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9629 23:07:08.588417 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9630 23:07:08.595011 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9631 23:07:08.598059 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9632 23:07:08.604896 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9633 23:07:08.607961 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9634 23:07:08.611664 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9635 23:07:08.618061 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9636 23:07:08.621651 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9637 23:07:08.627887 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9638 23:07:08.631329 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9639 23:07:08.638149 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9640 23:07:08.641157 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9641 23:07:08.644919 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9642 23:07:08.651245 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9643 23:07:08.654371 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9644 23:07:08.661286 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9645 23:07:08.664406 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9646 23:07:08.671230 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9647 23:07:08.674239 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9648 23:07:08.677208 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9649 23:07:08.684051 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9650 23:07:08.687220 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9651 23:07:08.693968 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9652 23:07:08.697226 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9653 23:07:08.703679 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9654 23:07:08.706864 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9655 23:07:08.710468 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9656 23:07:08.716991 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9657 23:07:08.720266 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9658 23:07:08.726775 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9659 23:07:08.729902 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9660 23:07:08.736535 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9661 23:07:08.739801 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9662 23:07:08.743297 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9663 23:07:08.750088 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9664 23:07:08.753436 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9665 23:07:08.759684 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9666 23:07:08.763454 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9667 23:07:08.766381 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9668 23:07:08.773163 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9669 23:07:08.776626 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9670 23:07:08.783257 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9671 23:07:08.786405 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9672 23:07:08.792678 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9673 23:07:08.796152 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9674 23:07:08.799249 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9675 23:07:08.805946 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9676 23:07:08.809098 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9677 23:07:08.812695 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9678 23:07:08.818944 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9679 23:07:08.822230 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9680 23:07:08.825661 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9681 23:07:08.829349 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9682 23:07:08.835763 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9683 23:07:08.839077 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9684 23:07:08.845813 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9685 23:07:08.848866 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9686 23:07:08.852245 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9687 23:07:08.858817 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9688 23:07:08.861968 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9689 23:07:08.865608 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9690 23:07:08.871931 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9691 23:07:08.875339 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9692 23:07:08.881810 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9693 23:07:08.885097 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9694 23:07:08.888686 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9695 23:07:08.895102 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9696 23:07:08.898234 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9697 23:07:08.901822 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9698 23:07:08.908503 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9699 23:07:08.911674 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9700 23:07:08.914832 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9701 23:07:08.921775 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9702 23:07:08.924782 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9703 23:07:08.931592 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9704 23:07:08.934877 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9705 23:07:08.938115 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9706 23:07:08.944981 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9707 23:07:08.948126 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9708 23:07:08.951399 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9709 23:07:08.958034 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9710 23:07:08.961405 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9711 23:07:08.967584 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9712 23:07:08.971175 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9713 23:07:08.974407 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9714 23:07:08.980708 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9715 23:07:08.984257 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9716 23:07:08.987275 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9717 23:07:08.991109 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9718 23:07:08.997200 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9719 23:07:09.000900 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9720 23:07:09.003956 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9721 23:07:09.007479 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9722 23:07:09.014062 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9723 23:07:09.017315 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9724 23:07:09.020514 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9725 23:07:09.024175 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9726 23:07:09.030518 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9727 23:07:09.033959 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9728 23:07:09.037015 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9729 23:07:09.043808 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9730 23:07:09.046859 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9731 23:07:09.053865 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9732 23:07:09.056779 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9733 23:07:09.060162 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9734 23:07:09.067261 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9735 23:07:09.070090 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9736 23:07:09.077169 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9737 23:07:09.080090 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9738 23:07:09.083670 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9739 23:07:09.089952 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9740 23:07:09.093558 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9741 23:07:09.099955 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9742 23:07:09.102996 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9743 23:07:09.110055 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9744 23:07:09.112922 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9745 23:07:09.116478 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9746 23:07:09.123283 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9747 23:07:09.126416 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9748 23:07:09.132818 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9749 23:07:09.136364 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9750 23:07:09.142535 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9751 23:07:09.146005 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9752 23:07:09.149185 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9753 23:07:09.155790 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9754 23:07:09.159645 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9755 23:07:09.166080 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9756 23:07:09.169098 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9757 23:07:09.172702 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9758 23:07:09.179359 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9759 23:07:09.182337 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9760 23:07:09.188888 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9761 23:07:09.192489 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9762 23:07:09.195845 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9763 23:07:09.202077 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9764 23:07:09.205592 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9765 23:07:09.212244 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9766 23:07:09.215762 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9767 23:07:09.222085 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9768 23:07:09.225577 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9769 23:07:09.228615 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9770 23:07:09.235708 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9771 23:07:09.238557 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9772 23:07:09.245120 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9773 23:07:09.248774 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9774 23:07:09.255402 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9775 23:07:09.258353 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9776 23:07:09.261728 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9777 23:07:09.268306 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9778 23:07:09.271998 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9779 23:07:09.278410 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9780 23:07:09.281479 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9781 23:07:09.284658 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9782 23:07:09.291191 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9783 23:07:09.294794 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9784 23:07:09.301519 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9785 23:07:09.305079 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9786 23:07:09.308115 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9787 23:07:09.314734 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9788 23:07:09.317683 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9789 23:07:09.324522 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9790 23:07:09.327927 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9791 23:07:09.334276 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9792 23:07:09.337459 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9793 23:07:09.341197 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9794 23:07:09.347798 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9795 23:07:09.350874 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9796 23:07:09.357473 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9797 23:07:09.361047 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9798 23:07:09.364485 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9799 23:07:09.370845 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9800 23:07:09.374288 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9801 23:07:09.381004 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9802 23:07:09.383907 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9803 23:07:09.390695 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9804 23:07:09.393866 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9805 23:07:09.397285 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9806 23:07:09.404169 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9807 23:07:09.407088 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9808 23:07:09.413618 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9809 23:07:09.417219 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9810 23:07:09.424081 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9811 23:07:09.427151 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9812 23:07:09.433566 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9813 23:07:09.437040 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9814 23:07:09.440439 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9815 23:07:09.447197 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9816 23:07:09.450267 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9817 23:07:09.456816 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9818 23:07:09.460323 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9819 23:07:09.467121 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9820 23:07:09.469943 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9821 23:07:09.476692 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9822 23:07:09.480321 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9823 23:07:09.483181 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9824 23:07:09.489898 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9825 23:07:09.493065 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9826 23:07:09.499877 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9827 23:07:09.502978 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9828 23:07:09.509734 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9829 23:07:09.513340 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9830 23:07:09.516335 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9831 23:07:09.522912 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9832 23:07:09.526313 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9833 23:07:09.533258 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9834 23:07:09.535907 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9835 23:07:09.542610 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9836 23:07:09.545770 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9837 23:07:09.552544 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9838 23:07:09.556344 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9839 23:07:09.559233 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9840 23:07:09.565978 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9841 23:07:09.568908 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9842 23:07:09.575352 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9843 23:07:09.578940 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9844 23:07:09.585685 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9845 23:07:09.588862 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9846 23:07:09.595298 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9847 23:07:09.598996 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9848 23:07:09.602131 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9849 23:07:09.608849 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9850 23:07:09.611878 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9851 23:07:09.618428 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9852 23:07:09.621871 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9853 23:07:09.628341 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9854 23:07:09.631948 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9855 23:07:09.638545 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9856 23:07:09.641732 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9857 23:07:09.648408 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9858 23:07:09.651750 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9859 23:07:09.658537 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9860 23:07:09.661522 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9861 23:07:09.667735 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9862 23:07:09.671513 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9863 23:07:09.674614 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9864 23:07:09.681419 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9865 23:07:09.685052 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9866 23:07:09.691378 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9867 23:07:09.694432 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9868 23:07:09.701274 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9869 23:07:09.704346 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9870 23:07:09.711082 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9871 23:07:09.714255 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9872 23:07:09.720582 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9873 23:07:09.727294 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9874 23:07:09.730791 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9875 23:07:09.737258 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9876 23:07:09.740930 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9877 23:07:09.747568 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9878 23:07:09.750784 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9879 23:07:09.757690 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9880 23:07:09.760682 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9881 23:07:09.763909 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9882 23:07:09.767061 INFO: [APUAPC] vio 0
9883 23:07:09.770161 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9884 23:07:09.777903 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9885 23:07:09.780825 INFO: [APUAPC] D0_APC_0: 0x400510
9886 23:07:09.783943 INFO: [APUAPC] D0_APC_1: 0x0
9887 23:07:09.787046 INFO: [APUAPC] D0_APC_2: 0x1540
9888 23:07:09.787128 INFO: [APUAPC] D0_APC_3: 0x0
9889 23:07:09.793755 INFO: [APUAPC] D1_APC_0: 0xffffffff
9890 23:07:09.797344 INFO: [APUAPC] D1_APC_1: 0xffffffff
9891 23:07:09.800375 INFO: [APUAPC] D1_APC_2: 0x3fffff
9892 23:07:09.800459 INFO: [APUAPC] D1_APC_3: 0x0
9893 23:07:09.803390 INFO: [APUAPC] D2_APC_0: 0xffffffff
9894 23:07:09.807012 INFO: [APUAPC] D2_APC_1: 0xffffffff
9895 23:07:09.810754 INFO: [APUAPC] D2_APC_2: 0x3fffff
9896 23:07:09.813675 INFO: [APUAPC] D2_APC_3: 0x0
9897 23:07:09.816993 INFO: [APUAPC] D3_APC_0: 0xffffffff
9898 23:07:09.820550 INFO: [APUAPC] D3_APC_1: 0xffffffff
9899 23:07:09.823465 INFO: [APUAPC] D3_APC_2: 0x3fffff
9900 23:07:09.826631 INFO: [APUAPC] D3_APC_3: 0x0
9901 23:07:09.829799 INFO: [APUAPC] D4_APC_0: 0xffffffff
9902 23:07:09.833174 INFO: [APUAPC] D4_APC_1: 0xffffffff
9903 23:07:09.836343 INFO: [APUAPC] D4_APC_2: 0x3fffff
9904 23:07:09.839819 INFO: [APUAPC] D4_APC_3: 0x0
9905 23:07:09.843284 INFO: [APUAPC] D5_APC_0: 0xffffffff
9906 23:07:09.846519 INFO: [APUAPC] D5_APC_1: 0xffffffff
9907 23:07:09.849621 INFO: [APUAPC] D5_APC_2: 0x3fffff
9908 23:07:09.852790 INFO: [APUAPC] D5_APC_3: 0x0
9909 23:07:09.856257 INFO: [APUAPC] D6_APC_0: 0xffffffff
9910 23:07:09.859195 INFO: [APUAPC] D6_APC_1: 0xffffffff
9911 23:07:09.862859 INFO: [APUAPC] D6_APC_2: 0x3fffff
9912 23:07:09.865977 INFO: [APUAPC] D6_APC_3: 0x0
9913 23:07:09.869283 INFO: [APUAPC] D7_APC_0: 0xffffffff
9914 23:07:09.872766 INFO: [APUAPC] D7_APC_1: 0xffffffff
9915 23:07:09.875902 INFO: [APUAPC] D7_APC_2: 0x3fffff
9916 23:07:09.879553 INFO: [APUAPC] D7_APC_3: 0x0
9917 23:07:09.882604 INFO: [APUAPC] D8_APC_0: 0xffffffff
9918 23:07:09.885780 INFO: [APUAPC] D8_APC_1: 0xffffffff
9919 23:07:09.889579 INFO: [APUAPC] D8_APC_2: 0x3fffff
9920 23:07:09.892676 INFO: [APUAPC] D8_APC_3: 0x0
9921 23:07:09.895607 INFO: [APUAPC] D9_APC_0: 0xffffffff
9922 23:07:09.899385 INFO: [APUAPC] D9_APC_1: 0xffffffff
9923 23:07:09.902266 INFO: [APUAPC] D9_APC_2: 0x3fffff
9924 23:07:09.905898 INFO: [APUAPC] D9_APC_3: 0x0
9925 23:07:09.908840 INFO: [APUAPC] D10_APC_0: 0xffffffff
9926 23:07:09.912413 INFO: [APUAPC] D10_APC_1: 0xffffffff
9927 23:07:09.915979 INFO: [APUAPC] D10_APC_2: 0x3fffff
9928 23:07:09.918721 INFO: [APUAPC] D10_APC_3: 0x0
9929 23:07:09.922154 INFO: [APUAPC] D11_APC_0: 0xffffffff
9930 23:07:09.925591 INFO: [APUAPC] D11_APC_1: 0xffffffff
9931 23:07:09.928491 INFO: [APUAPC] D11_APC_2: 0x3fffff
9932 23:07:09.932226 INFO: [APUAPC] D11_APC_3: 0x0
9933 23:07:09.935237 INFO: [APUAPC] D12_APC_0: 0xffffffff
9934 23:07:09.938450 INFO: [APUAPC] D12_APC_1: 0xffffffff
9935 23:07:09.941948 INFO: [APUAPC] D12_APC_2: 0x3fffff
9936 23:07:09.944917 INFO: [APUAPC] D12_APC_3: 0x0
9937 23:07:09.948692 INFO: [APUAPC] D13_APC_0: 0xffffffff
9938 23:07:09.951575 INFO: [APUAPC] D13_APC_1: 0xffffffff
9939 23:07:09.955301 INFO: [APUAPC] D13_APC_2: 0x3fffff
9940 23:07:09.958246 INFO: [APUAPC] D13_APC_3: 0x0
9941 23:07:09.961440 INFO: [APUAPC] D14_APC_0: 0xffffffff
9942 23:07:09.964883 INFO: [APUAPC] D14_APC_1: 0xffffffff
9943 23:07:09.968200 INFO: [APUAPC] D14_APC_2: 0x3fffff
9944 23:07:09.971459 INFO: [APUAPC] D14_APC_3: 0x0
9945 23:07:09.974846 INFO: [APUAPC] D15_APC_0: 0xffffffff
9946 23:07:09.977981 INFO: [APUAPC] D15_APC_1: 0xffffffff
9947 23:07:09.981336 INFO: [APUAPC] D15_APC_2: 0x3fffff
9948 23:07:09.984510 INFO: [APUAPC] D15_APC_3: 0x0
9949 23:07:09.988046 INFO: [APUAPC] APC_CON: 0x4
9950 23:07:09.991595 INFO: [NOCDAPC] D0_APC_0: 0x0
9951 23:07:09.994786 INFO: [NOCDAPC] D0_APC_1: 0x0
9952 23:07:09.997708 INFO: [NOCDAPC] D1_APC_0: 0x0
9953 23:07:10.001346 INFO: [NOCDAPC] D1_APC_1: 0xfff
9954 23:07:10.004754 INFO: [NOCDAPC] D2_APC_0: 0x0
9955 23:07:10.007556 INFO: [NOCDAPC] D2_APC_1: 0xfff
9956 23:07:10.011303 INFO: [NOCDAPC] D3_APC_0: 0x0
9957 23:07:10.011425 INFO: [NOCDAPC] D3_APC_1: 0xfff
9958 23:07:10.014299 INFO: [NOCDAPC] D4_APC_0: 0x0
9959 23:07:10.017920 INFO: [NOCDAPC] D4_APC_1: 0xfff
9960 23:07:10.021274 INFO: [NOCDAPC] D5_APC_0: 0x0
9961 23:07:10.024128 INFO: [NOCDAPC] D5_APC_1: 0xfff
9962 23:07:10.027831 INFO: [NOCDAPC] D6_APC_0: 0x0
9963 23:07:10.030854 INFO: [NOCDAPC] D6_APC_1: 0xfff
9964 23:07:10.034515 INFO: [NOCDAPC] D7_APC_0: 0x0
9965 23:07:10.037732 INFO: [NOCDAPC] D7_APC_1: 0xfff
9966 23:07:10.040825 INFO: [NOCDAPC] D8_APC_0: 0x0
9967 23:07:10.043914 INFO: [NOCDAPC] D8_APC_1: 0xfff
9968 23:07:10.044000 INFO: [NOCDAPC] D9_APC_0: 0x0
9969 23:07:10.048070 INFO: [NOCDAPC] D9_APC_1: 0xfff
9970 23:07:10.050829 INFO: [NOCDAPC] D10_APC_0: 0x0
9971 23:07:10.054302 INFO: [NOCDAPC] D10_APC_1: 0xfff
9972 23:07:10.057364 INFO: [NOCDAPC] D11_APC_0: 0x0
9973 23:07:10.060505 INFO: [NOCDAPC] D11_APC_1: 0xfff
9974 23:07:10.064190 INFO: [NOCDAPC] D12_APC_0: 0x0
9975 23:07:10.067612 INFO: [NOCDAPC] D12_APC_1: 0xfff
9976 23:07:10.070605 INFO: [NOCDAPC] D13_APC_0: 0x0
9977 23:07:10.073704 INFO: [NOCDAPC] D13_APC_1: 0xfff
9978 23:07:10.077214 INFO: [NOCDAPC] D14_APC_0: 0x0
9979 23:07:10.080300 INFO: [NOCDAPC] D14_APC_1: 0xfff
9980 23:07:10.083716 INFO: [NOCDAPC] D15_APC_0: 0x0
9981 23:07:10.086874 INFO: [NOCDAPC] D15_APC_1: 0xfff
9982 23:07:10.090268 INFO: [NOCDAPC] APC_CON: 0x4
9983 23:07:10.093713 INFO: [APUAPC] set_apusys_apc done
9984 23:07:10.093801 INFO: [DEVAPC] devapc_init done
9985 23:07:10.100374 INFO: GICv3 without legacy support detected.
9986 23:07:10.103414 INFO: ARM GICv3 driver initialized in EL3
9987 23:07:10.107047 INFO: Maximum SPI INTID supported: 639
9988 23:07:10.110030 INFO: BL31: Initializing runtime services
9989 23:07:10.116615 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9990 23:07:10.120090 INFO: SPM: enable CPC mode
9991 23:07:10.123112 INFO: mcdi ready for mcusys-off-idle and system suspend
9992 23:07:10.129881 INFO: BL31: Preparing for EL3 exit to normal world
9993 23:07:10.133383 INFO: Entry point address = 0x80000000
9994 23:07:10.136355 INFO: SPSR = 0x8
9995 23:07:10.140884
9996 23:07:10.140966
9997 23:07:10.141031
9998 23:07:10.144226 Starting depthcharge on Spherion...
9999 23:07:10.144309
10000 23:07:10.144375 Wipe memory regions:
10001 23:07:10.144435
10002 23:07:10.145126 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
10003 23:07:10.145229 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10004 23:07:10.145310 Setting prompt string to ['asurada:']
10005 23:07:10.145393 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10006 23:07:10.147894 [0x00000040000000, 0x00000054600000)
10007 23:07:10.270130
10008 23:07:10.270253 [0x00000054660000, 0x00000080000000)
10009 23:07:10.530330
10010 23:07:10.530467 [0x000000821a7280, 0x000000ffe64000)
10011 23:07:11.275312
10012 23:07:11.275661 [0x00000100000000, 0x00000240000000)
10013 23:07:13.164914
10014 23:07:13.168314 Initializing XHCI USB controller at 0x11200000.
10015 23:07:14.206132
10016 23:07:14.209208 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10017 23:07:14.209325
10018 23:07:14.209427
10019 23:07:14.209533
10020 23:07:14.209858 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10022 23:07:14.310236 asurada: tftpboot 192.168.201.1 12395373/tftp-deploy-dxcbkafh/kernel/image.itb 12395373/tftp-deploy-dxcbkafh/kernel/cmdline
10023 23:07:14.310423 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10024 23:07:14.310537 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10025 23:07:14.314852 tftpboot 192.168.201.1 12395373/tftp-deploy-dxcbkafh/kernel/image.ittp-deploy-dxcbkafh/kernel/cmdline
10026 23:07:14.314936
10027 23:07:14.315000 Waiting for link
10028 23:07:14.475260
10029 23:07:14.475435 R8152: Initializing
10030 23:07:14.475507
10031 23:07:14.478363 Version 6 (ocp_data = 5c30)
10032 23:07:14.478473
10033 23:07:14.481298 R8152: Done initializing
10034 23:07:14.481400
10035 23:07:14.481500 Adding net device
10036 23:07:16.447237
10037 23:07:16.447783 done.
10038 23:07:16.448237
10039 23:07:16.448660 MAC: 00:24:32:30:7c:7b
10040 23:07:16.449207
10041 23:07:16.450709 Sending DHCP discover... done.
10042 23:07:16.451021
10043 23:07:16.453570 Waiting for reply... done.
10044 23:07:16.454035
10045 23:07:16.456956 Sending DHCP request... done.
10046 23:07:16.457196
10047 23:07:16.457437 Waiting for reply... done.
10048 23:07:16.460502
10049 23:07:16.460723 My ip is 192.168.201.14
10050 23:07:16.460916
10051 23:07:16.463385 The DHCP server ip is 192.168.201.1
10052 23:07:16.463482
10053 23:07:16.467079 TFTP server IP predefined by user: 192.168.201.1
10054 23:07:16.467161
10055 23:07:16.473823 Bootfile predefined by user: 12395373/tftp-deploy-dxcbkafh/kernel/image.itb
10056 23:07:16.473907
10057 23:07:16.476815 Sending tftp read request... done.
10058 23:07:16.476959
10059 23:07:16.482958 Waiting for the transfer...
10060 23:07:16.483046
10061 23:07:17.008092 00000000 ################################################################
10062 23:07:17.008227
10063 23:07:17.567766 00080000 ################################################################
10064 23:07:17.567906
10065 23:07:18.103484 00100000 ################################################################
10066 23:07:18.103621
10067 23:07:18.636791 00180000 ################################################################
10068 23:07:18.636931
10069 23:07:19.179078 00200000 ################################################################
10070 23:07:19.179221
10071 23:07:19.732592 00280000 ################################################################
10072 23:07:19.732731
10073 23:07:20.270784 00300000 ################################################################
10074 23:07:20.270932
10075 23:07:20.798599 00380000 ################################################################
10076 23:07:20.798742
10077 23:07:21.350626 00400000 ################################################################
10078 23:07:21.350765
10079 23:07:21.878076 00480000 ################################################################
10080 23:07:21.878213
10081 23:07:22.408014 00500000 ################################################################
10082 23:07:22.408150
10083 23:07:22.934349 00580000 ################################################################
10084 23:07:22.934502
10085 23:07:23.464409 00600000 ################################################################
10086 23:07:23.464569
10087 23:07:23.990148 00680000 ################################################################
10088 23:07:23.990311
10089 23:07:24.525300 00700000 ################################################################
10090 23:07:24.525435
10091 23:07:25.058219 00780000 ################################################################
10092 23:07:25.058353
10093 23:07:25.584479 00800000 ################################################################
10094 23:07:25.584618
10095 23:07:26.117582 00880000 ################################################################
10096 23:07:26.117770
10097 23:07:26.654168 00900000 ################################################################
10098 23:07:26.654309
10099 23:07:27.184583 00980000 ################################################################
10100 23:07:27.184729
10101 23:07:27.720768 00a00000 ################################################################
10102 23:07:27.720898
10103 23:07:28.247256 00a80000 ################################################################
10104 23:07:28.247530
10105 23:07:28.773817 00b00000 ################################################################
10106 23:07:28.773990
10107 23:07:29.308733 00b80000 ################################################################
10108 23:07:29.308874
10109 23:07:29.837583 00c00000 ################################################################
10110 23:07:29.837724
10111 23:07:30.380197 00c80000 ################################################################
10112 23:07:30.380345
10113 23:07:30.919474 00d00000 ################################################################
10114 23:07:30.919610
10115 23:07:31.465184 00d80000 ################################################################
10116 23:07:31.465324
10117 23:07:32.022607 00e00000 ################################################################
10118 23:07:32.022776
10119 23:07:32.566503 00e80000 ################################################################
10120 23:07:32.566667
10121 23:07:33.093865 00f00000 ################################################################
10122 23:07:33.094021
10123 23:07:33.630664 00f80000 ################################################################
10124 23:07:33.630828
10125 23:07:34.162467 01000000 ################################################################
10126 23:07:34.162600
10127 23:07:34.696018 01080000 ################################################################
10128 23:07:34.696170
10129 23:07:35.222438 01100000 ################################################################
10130 23:07:35.222583
10131 23:07:35.752815 01180000 ################################################################
10132 23:07:35.752963
10133 23:07:36.285758 01200000 ################################################################
10134 23:07:36.285924
10135 23:07:36.855151 01280000 ################################################################
10136 23:07:36.855287
10137 23:07:37.420642 01300000 ################################################################
10138 23:07:37.420779
10139 23:07:37.995556 01380000 ################################################################
10140 23:07:37.995706
10141 23:07:38.633110 01400000 ################################################################
10142 23:07:38.633758
10143 23:07:39.229514 01480000 ################################################################
10144 23:07:39.229649
10145 23:07:39.859804 01500000 ################################################################
10146 23:07:39.859944
10147 23:07:40.475928 01580000 ################################################################
10148 23:07:40.476422
10149 23:07:41.096904 01600000 ################################################################
10150 23:07:41.097040
10151 23:07:41.660284 01680000 ################################################################
10152 23:07:41.660419
10153 23:07:42.219808 01700000 ################################################################
10154 23:07:42.219940
10155 23:07:42.775356 01780000 ################################################################
10156 23:07:42.775498
10157 23:07:43.328178 01800000 ################################################################
10158 23:07:43.328324
10159 23:07:43.875557 01880000 ################################################################
10160 23:07:43.875690
10161 23:07:44.446279 01900000 ################################################################
10162 23:07:44.446434
10163 23:07:45.007059 01980000 ################################################################
10164 23:07:45.007217
10165 23:07:45.582010 01a00000 ################################################################
10166 23:07:45.582145
10167 23:07:46.168794 01a80000 ################################################################
10168 23:07:46.168932
10169 23:07:46.729456 01b00000 ################################################################
10170 23:07:46.729592
10171 23:07:47.389366 01b80000 ################################################################
10172 23:07:47.389857
10173 23:07:48.057564 01c00000 ################################################################
10174 23:07:48.058075
10175 23:07:48.771175 01c80000 ################################################################
10176 23:07:48.771705
10177 23:07:49.454950 01d00000 ################################################################
10178 23:07:49.455473
10179 23:07:50.047008 01d80000 ################################################################
10180 23:07:50.047559
10181 23:07:50.753343 01e00000 ################################################################
10182 23:07:50.754002
10183 23:07:51.457199 01e80000 ################################################################
10184 23:07:51.457708
10185 23:07:52.022094 01f00000 ################################################### done.
10186 23:07:52.022603
10187 23:07:52.024794 The bootfile was 32918502 bytes long.
10188 23:07:52.025212
10189 23:07:52.028477 Sending tftp read request... done.
10190 23:07:52.028890
10191 23:07:52.032092 Waiting for the transfer...
10192 23:07:52.032511
10193 23:07:52.032844 00000000 # done.
10194 23:07:52.033165
10195 23:07:52.038855 Command line loaded dynamically from TFTP file: 12395373/tftp-deploy-dxcbkafh/kernel/cmdline
10196 23:07:52.039276
10197 23:07:52.055250 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10198 23:07:52.055833
10199 23:07:52.056169 Loading FIT.
10200 23:07:52.056481
10201 23:07:52.058678 Image ramdisk-1 has 21388804 bytes.
10202 23:07:52.059091
10203 23:07:52.061637 Image fdt-1 has 47278 bytes.
10204 23:07:52.062102
10205 23:07:52.065206 Image kernel-1 has 11480388 bytes.
10206 23:07:52.065687
10207 23:07:52.071616 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10208 23:07:52.072171
10209 23:07:52.091339 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10210 23:07:52.091895
10211 23:07:52.094962 Choosing best match conf-1 for compat google,spherion-rev2.
10212 23:07:52.099923
10213 23:07:52.104438 Connected to device vid:did:rid of 1ae0:0028:00
10214 23:07:52.112465
10215 23:07:52.116408 tpm_get_response: command 0x17b, return code 0x0
10216 23:07:52.116949
10217 23:07:52.122286 ec_init: CrosEC protocol v3 supported (256, 248)
10218 23:07:52.122702
10219 23:07:52.125473 tpm_cleanup: add release locality here.
10220 23:07:52.125889
10221 23:07:52.129083 Shutting down all USB controllers.
10222 23:07:52.129499
10223 23:07:52.132050 Removing current net device
10224 23:07:52.132464
10225 23:07:52.135464 Exiting depthcharge with code 4 at timestamp: 71227545
10226 23:07:52.135884
10227 23:07:52.138890 LZMA decompressing kernel-1 to 0x821a6718
10228 23:07:52.139311
10229 23:07:52.142188 LZMA decompressing kernel-1 to 0x40000000
10230 23:07:53.579558
10231 23:07:53.580095 jumping to kernel
10232 23:07:53.582053 end: 2.2.4 bootloader-commands (duration 00:00:43) [common]
10233 23:07:53.582615 start: 2.2.5 auto-login-action (timeout 00:03:42) [common]
10234 23:07:53.583079 Setting prompt string to ['Linux version [0-9]']
10235 23:07:53.583563 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10236 23:07:53.584027 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10237 23:07:53.660961
10238 23:07:53.664650 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10239 23:07:53.668461 start: 2.2.5.1 login-action (timeout 00:03:42) [common]
10240 23:07:53.668973 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10241 23:07:53.669437 Setting prompt string to []
10242 23:07:53.669910 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10243 23:07:53.670343 Using line separator: #'\n'#
10244 23:07:53.670710 No login prompt set.
10245 23:07:53.671040 Parsing kernel messages
10246 23:07:53.671555 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10247 23:07:53.672144 [login-action] Waiting for messages, (timeout 00:03:42)
10248 23:07:53.687650 [ 0.000000] Linux version 6.1.67-cip12-rt7 (KernelCI@build-j59954-arm64-gcc-10-defconfig-arm64-chromebook-nblph) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Wed Dec 27 22:50:56 UTC 2023
10249 23:07:53.690892 [ 0.000000] random: crng init done
10250 23:07:53.697593 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10251 23:07:53.700633 [ 0.000000] efi: UEFI not found.
10252 23:07:53.707326 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10253 23:07:53.717727 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10254 23:07:53.727057 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10255 23:07:53.733457 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10256 23:07:53.740578 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10257 23:07:53.747133 [ 0.000000] printk: bootconsole [mtk8250] enabled
10258 23:07:53.753377 [ 0.000000] NUMA: No NUMA configuration found
10259 23:07:53.759791 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10260 23:07:53.766538 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcfa00-0x23efd1fff]
10261 23:07:53.766954 [ 0.000000] Zone ranges:
10262 23:07:53.773498 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10263 23:07:53.776372 [ 0.000000] DMA32 empty
10264 23:07:53.783584 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10265 23:07:53.786651 [ 0.000000] Movable zone start for each node
10266 23:07:53.790063 [ 0.000000] Early memory node ranges
10267 23:07:53.796232 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10268 23:07:53.803193 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10269 23:07:53.809515 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10270 23:07:53.816058 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10271 23:07:53.822489 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10272 23:07:53.829409 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10273 23:07:53.885847 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10274 23:07:53.892674 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10275 23:07:53.899341 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10276 23:07:53.902473 [ 0.000000] psci: probing for conduit method from DT.
10277 23:07:53.909420 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10278 23:07:53.912421 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10279 23:07:53.919827 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10280 23:07:53.922664 [ 0.000000] psci: SMC Calling Convention v1.2
10281 23:07:53.928839 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10282 23:07:53.932342 [ 0.000000] Detected VIPT I-cache on CPU0
10283 23:07:53.938730 [ 0.000000] CPU features: detected: GIC system register CPU interface
10284 23:07:53.945432 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10285 23:07:53.951745 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10286 23:07:53.958682 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10287 23:07:53.968736 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10288 23:07:53.975035 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10289 23:07:53.978497 [ 0.000000] alternatives: applying boot alternatives
10290 23:07:53.984945 [ 0.000000] Fallback order for Node 0: 0
10291 23:07:53.991776 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10292 23:07:53.994690 [ 0.000000] Policy zone: Normal
10293 23:07:54.008181 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10294 23:07:54.017904 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10295 23:07:54.030342 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10296 23:07:54.040979 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10297 23:07:54.046845 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10298 23:07:54.050361 <6>[ 0.000000] software IO TLB: area num 8.
10299 23:07:54.106471 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10300 23:07:54.255647 <6>[ 0.000000] Memory: 7947832K/8385536K available (17984K kernel code, 4116K rwdata, 18184K rodata, 8448K init, 615K bss, 404936K reserved, 32768K cma-reserved)
10301 23:07:54.262597 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10302 23:07:54.269180 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10303 23:07:54.272882 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10304 23:07:54.279155 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10305 23:07:54.285694 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10306 23:07:54.288678 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10307 23:07:54.298595 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10308 23:07:54.305391 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10309 23:07:54.311907 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10310 23:07:54.318657 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10311 23:07:54.321597 <6>[ 0.000000] GICv3: 608 SPIs implemented
10312 23:07:54.324928 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10313 23:07:54.331764 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10314 23:07:54.335099 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10315 23:07:54.341487 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10316 23:07:54.354556 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10317 23:07:54.367895 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10318 23:07:54.374641 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10319 23:07:54.382411 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10320 23:07:54.395841 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10321 23:07:54.402211 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10322 23:07:54.408782 <6>[ 0.009232] Console: colour dummy device 80x25
10323 23:07:54.418464 <6>[ 0.013958] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10324 23:07:54.425492 <6>[ 0.024402] pid_max: default: 32768 minimum: 301
10325 23:07:54.428435 <6>[ 0.029274] LSM: Security Framework initializing
10326 23:07:54.435327 <6>[ 0.034242] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10327 23:07:54.445134 <6>[ 0.042057] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10328 23:07:54.454868 <6>[ 0.051503] cblist_init_generic: Setting adjustable number of callback queues.
10329 23:07:54.458239 <6>[ 0.058945] cblist_init_generic: Setting shift to 3 and lim to 1.
10330 23:07:54.467922 <6>[ 0.065282] cblist_init_generic: Setting adjustable number of callback queues.
10331 23:07:54.475003 <6>[ 0.072710] cblist_init_generic: Setting shift to 3 and lim to 1.
10332 23:07:54.478228 <6>[ 0.079188] rcu: Hierarchical SRCU implementation.
10333 23:07:54.484525 <6>[ 0.079190] rcu: Max phase no-delay instances is 1000.
10334 23:07:54.491468 <6>[ 0.079215] printk: bootconsole [mtk8250] printing thread started
10335 23:07:54.497710 <6>[ 0.097568] EFI services will not be available.
10336 23:07:54.501036 <6>[ 0.097769] smp: Bringing up secondary CPUs ...
10337 23:07:54.507729 <6>[ 0.098077] Detected VIPT I-cache on CPU1
10338 23:07:54.514698 <6>[ 0.098144] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10339 23:07:54.521214 <6>[ 0.098174] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10340 23:07:54.530294 <6>[ 0.126038] Detected VIPT I-cache on CPU2
10341 23:07:54.537136 <6>[ 0.126088] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10342 23:07:54.547085 <6>[ 0.126104] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10343 23:07:54.550246 <6>[ 0.126361] Detected VIPT I-cache on CPU3
10344 23:07:54.556706 <6>[ 0.126407] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10345 23:07:54.563741 <6>[ 0.126421] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10346 23:07:54.567025 <6>[ 0.126730] CPU features: detected: Spectre-v4
10347 23:07:54.573369 <6>[ 0.126736] CPU features: detected: Spectre-BHB
10348 23:07:54.576722 <6>[ 0.126741] Detected PIPT I-cache on CPU4
10349 23:07:54.583159 <6>[ 0.126798] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10350 23:07:54.589471 <6>[ 0.126815] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10351 23:07:54.595973 <6>[ 0.127108] Detected PIPT I-cache on CPU5
10352 23:07:54.602755 <6>[ 0.127168] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10353 23:07:54.609086 <6>[ 0.127185] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10354 23:07:54.612956 <6>[ 0.127458] Detected PIPT I-cache on CPU6
10355 23:07:54.622491 <6>[ 0.127522] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10356 23:07:54.629117 <6>[ 0.127538] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10357 23:07:54.632313 <6>[ 0.127831] Detected PIPT I-cache on CPU7
10358 23:07:54.638757 <6>[ 0.127894] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10359 23:07:54.645383 <6>[ 0.127910] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10360 23:07:54.649014 <6>[ 0.127957] smp: Brought up 1 node, 8 CPUs
10361 23:07:54.655222 <6>[ 0.127962] SMP: Total of 8 processors activated.
10362 23:07:54.661736 <6>[ 0.127964] CPU features: detected: 32-bit EL0 Support
10363 23:07:54.668431 <6>[ 0.127967] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10364 23:07:54.675094 <6>[ 0.127969] CPU features: detected: Common not Private translations
10365 23:07:54.681763 <6>[ 0.127971] CPU features: detected: CRC32 instructions
10366 23:07:54.688494 <6>[ 0.127973] CPU features: detected: RCpc load-acquire (LDAPR)
10367 23:07:54.691708 <6>[ 0.127975] CPU features: detected: LSE atomic instructions
10368 23:07:54.698360 <6>[ 0.127976] CPU features: detected: Privileged Access Never
10369 23:07:54.704679 <6>[ 0.127978] CPU features: detected: RAS Extension Support
10370 23:07:54.711602 <6>[ 0.127981] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10371 23:07:54.714880 <6>[ 0.128048] CPU: All CPU(s) started at EL2
10372 23:07:54.721029 <6>[ 0.128050] alternatives: applying system-wide alternatives
10373 23:07:54.749965 �S�er�r�j��<6>[ < 0.348955] printk: console [ttyS0] printing thread started
10374 23:07:54.753518 6>[<6>[ 0.348988] printk: console [ttyS0] enabled
10375 23:07:54.760093 0.225531] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10376 23:07:54.763560 <6>[ 0.225625] pnp: PnP ACPI: disabled
10377 23:07:54.772305 <6>[ 0.348993] printk: bootconsole [mtk8250] disabled
10378 23:07:54.779037 <6>[ 0.370124] printk: bootconsole [mtk8250] printing thread stopped
10379 23:07:54.782211 <6>[ 0.371151] SuperH (H)SCI(F) driver initialized
10380 23:07:54.789058 <6>[ 0.371641] msm_serial: driver initialized
10381 23:07:54.795530 <6>[ 0.376229] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10382 23:07:54.805758 <6>[ 0.376261] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10383 23:07:54.815190 <6>[ 0.376291] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10384 23:07:54.824983 <6>[ 0.376319] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10385 23:07:54.830597 <6>[ 0.376340] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10386 23:07:54.839953 <6>[ 0.376367] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10387 23:07:54.853586 <6>[ 0.376395] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10388 23:07:54.864488 <6>[ 0.376501] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10389 23:07:54.869189 <6>[ 0.376529] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10390 23:07:54.869275 <6>[ 0.393133] loop: module loaded
10391 23:07:54.883395 <6>[ 0.395688] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10392 23:07:54.886690 <4>[ 0.412418] mtk-pmic-keys: Failed to locate of_node [id: -1]
10393 23:07:54.886777 <6>[ 0.413207] megasas: 07.719.03.00-rc1
10394 23:07:54.889802 <6>[ 0.420944] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10395 23:07:54.896680 <6>[ 0.428792] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10396 23:07:54.903547 <6>[ 0.440816] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10397 23:07:54.913080 <6>[ 0.493058] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9
10398 23:07:55.536758 <6>[ 1.133714] Freeing initrd memory: 20884K
10399 23:07:55.545111 <6>[ 1.145028] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10400 23:07:55.551428 <6>[ 1.149681] tun: Universal TUN/TAP device driver, 1.6
10401 23:07:55.554557 <6>[ 1.150420] thunder_xcv, ver 1.0
10402 23:07:55.557861 <6>[ 1.150455] thunder_bgx, ver 1.0
10403 23:07:55.561245 <6>[ 1.150468] nicpf, ver 1.0
10404 23:07:55.567615 <6>[ 1.151509] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10405 23:07:55.574415 <6>[ 1.151512] hns3: Copyright (c) 2017 Huawei Corporation.
10406 23:07:55.577367 <6>[ 1.151537] hclge is initializing
10407 23:07:55.583999 <6>[ 1.151550] e1000: Intel(R) PRO/1000 Network Driver
10408 23:07:55.588412 <6>[ 1.151552] e1000: Copyright (c) 1999-2006 Intel Corporation.
10409 23:07:55.595028 <6>[ 1.151568] e1000e: Intel(R) PRO/1000 Network Driver
10410 23:07:55.598387 <6>[ 1.151570] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10411 23:07:55.605634 <6>[ 1.151584] igb: Intel(R) Gigabit Ethernet Network Driver
10412 23:07:55.611905 <6>[ 1.151586] igb: Copyright (c) 2007-2014 Intel Corporation.
10413 23:07:55.618763 <6>[ 1.151602] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10414 23:07:55.625880 <6>[ 1.151604] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10415 23:07:55.628932 <6>[ 1.151891] sky2: driver version 1.30
10416 23:07:55.632225 <6>[ 1.152947] VFIO - User Level meta-driver version: 0.3
10417 23:07:55.638964 <6>[ 1.155801] usbcore: registered new interface driver usb-storage
10418 23:07:55.646073 <6>[ 1.155982] usbcore: registered new device driver onboard-usb-hub
10419 23:07:55.652283 <6>[ 1.158768] mt6397-rtc mt6359-rtc: registered as rtc0
10420 23:07:55.658903 <6>[ 1.158923] mt6397-rtc mt6359-rtc: setting system clock to 2023-12-27T23:08:00 UTC (1703718480)
10421 23:07:55.665678 <6>[ 1.159529] i2c_dev: i2c /dev entries driver
10422 23:07:55.672575 <6>[ 1.166636] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10423 23:07:55.679462 <6>[ 1.181623] cpu cpu0: EM: created perf domain
10424 23:07:55.682590 <6>[ 1.181919] cpu cpu4: EM: created perf domain
10425 23:07:55.689128 <6>[ 1.183643] sdhci: Secure Digital Host Controller Interface driver
10426 23:07:55.692308 <6>[ 1.183644] sdhci: Copyright(c) Pierre Ossman
10427 23:07:55.699212 <6>[ 1.184006] Synopsys Designware Multimedia Card Interface Driver
10428 23:07:55.705462 <6>[ 1.184388] sdhci-pltfm: SDHCI platform and OF driver helper
10429 23:07:55.711874 <6>[ 1.188651] ledtrig-cpu: registered to indicate activity on CPUs
10430 23:07:55.715208 <6>[ 1.189252] mmc0: CQHCI version 5.10
10431 23:07:55.721800 <6>[ 1.189345] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10432 23:07:55.729103 <6>[ 1.189628] usbcore: registered new interface driver usbhid
10433 23:07:55.731909 <6>[ 1.189630] usbhid: USB HID core driver
10434 23:07:55.738617 <6>[ 1.189748] spi_master spi0: will run message pump with realtime priority
10435 23:07:55.751802 <6>[ 1.224011] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10436 23:07:55.764882 <6>[ 1.227019] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10437 23:07:55.771845 <6>[ 1.228353] cros-ec-spi spi0.0: Chrome EC device registered
10438 23:07:55.781520 <6>[ 1.248242] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10439 23:07:55.784496 <6>[ 1.250588] NET: Registered PF_PACKET protocol family
10440 23:07:55.791630 <6>[ 1.250685] 9pnet: Installing 9P2000 support
10441 23:07:55.794945 <5>[ 1.250723] Key type dns_resolver registered
10442 23:07:55.798080 <6>[ 1.251057] registered taskstats version 1
10443 23:07:55.804773 <5>[ 1.251078] Loading compiled-in X.509 certificates
10444 23:07:55.814956 <4>[ 1.268479] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10445 23:07:55.824551 <4>[ 1.268742] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10446 23:07:55.830801 <3>[ 1.268764] debugfs: File 'uA_load' in directory '/' already present!
10447 23:07:55.837474 <3>[ 1.268777] debugfs: File 'min_uV' in directory '/' already present!
10448 23:07:55.844132 <3>[ 1.268784] debugfs: File 'max_uV' in directory '/' already present!
10449 23:07:55.850718 <3>[ 1.268791] debugfs: File 'constraint_flags' in directory '/' already present!
10450 23:07:55.860527 <3>[ 1.272389] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10451 23:07:55.867727 <6>[ 1.280865] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10452 23:07:55.873850 <6>[ 1.281492] xhci-mtk 11200000.usb: xHCI Host Controller
10453 23:07:55.880413 <6>[ 1.281541] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10454 23:07:55.890983 <6>[ 1.281756] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10455 23:07:55.894162 <6>[ 1.281805] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10456 23:07:55.900711 <6>[ 1.281892] xhci-mtk 11200000.usb: xHCI Host Controller
10457 23:07:55.907218 <6>[ 1.281903] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10458 23:07:55.917432 <6>[ 1.281910] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10459 23:07:55.920867 <6>[ 1.282273] hub 1-0:1.0: USB hub found
10460 23:07:55.923732 <6>[ 1.282290] hub 1-0:1.0: 1 port detected
10461 23:07:55.933835 <6>[ 1.282468] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10462 23:07:55.936993 <6>[ 1.282678] hub 2-0:1.0: USB hub found
10463 23:07:55.940193 <6>[ 1.282691] hub 2-0:1.0: 1 port detected
10464 23:07:55.946814 <6>[ 1.283476] mmc0: Command Queue Engine enabled
10465 23:07:55.953221 <6>[ 1.283486] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10466 23:07:55.956662 <6>[ 1.283959] mmcblk0: mmc0:0001 DA4128 116 GiB
10467 23:07:55.960003 <6>[ 1.285933] mtk-msdc 11f70000.mmc: Got CD GPIO
10468 23:07:55.966683 <6>[ 1.289868] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10469 23:07:55.973358 <6>[ 1.292236] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10470 23:07:55.976533 <6>[ 1.293169] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10471 23:07:55.983263 <6>[ 1.294200] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10472 23:07:55.992827 <6>[ 1.301250] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10473 23:07:55.999700 <6>[ 1.301256] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10474 23:07:56.009188 <4>[ 1.301432] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10475 23:07:56.016062 <6>[ 1.302082] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10476 23:07:56.025884 <6>[ 1.302085] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10477 23:07:56.032396 <6>[ 1.302204] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10478 23:07:56.039713 <6>[ 1.302215] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10479 23:07:56.049439 <6>[ 1.302220] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10480 23:07:56.058939 <6>[ 1.302229] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10481 23:07:56.065487 <6>[ 1.303631] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10482 23:07:56.075556 <6>[ 1.303647] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10483 23:07:56.082649 <6>[ 1.303653] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10484 23:07:56.091933 <6>[ 1.303659] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10485 23:07:56.098810 <6>[ 1.303666] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10486 23:07:56.108718 <6>[ 1.303672] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10487 23:07:56.115637 <6>[ 1.303678] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10488 23:07:56.125659 <6>[ 1.303684] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10489 23:07:56.131641 <6>[ 1.303691] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10490 23:07:56.141788 <6>[ 1.303697] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10491 23:07:56.148797 <6>[ 1.303703] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10492 23:07:56.158711 <6>[ 1.303709] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10493 23:07:56.165041 <6>[ 1.303715] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10494 23:07:56.174460 <6>[ 1.303721] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10495 23:07:56.181705 <6>[ 1.303727] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10496 23:07:56.187812 <6>[ 1.304215] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10497 23:07:56.195028 <6>[ 1.305037] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10498 23:07:56.201086 <6>[ 1.305621] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10499 23:07:56.207692 <6>[ 1.306249] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10500 23:07:56.214425 <6>[ 1.306876] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10501 23:07:56.224707 <6>[ 1.307080] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10502 23:07:56.234243 <6>[ 1.307094] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10503 23:07:56.244435 <6>[ 1.307099] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10504 23:07:56.254043 <6>[ 1.307105] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10505 23:07:56.260727 <6>[ 1.307110] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10506 23:07:56.270593 <6>[ 1.307115] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10507 23:07:56.281236 <6>[ 1.307121] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10508 23:07:56.290444 <6>[ 1.307126] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10509 23:07:56.299925 <6>[ 1.307130] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10510 23:07:56.309815 <6>[ 1.307136] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10511 23:07:56.319934 <6>[ 1.307141] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10512 23:07:56.326336 <6>[ 1.307821] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10513 23:07:56.333066 <6>[ 1.717539] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10514 23:07:56.339536 <6>[ 1.873792] hub 1-1:1.0: USB hub found
10515 23:07:56.342793 <6>[ 1.874128] hub 1-1:1.0: 4 ports detected
10516 23:07:56.346183 <6>[ 1.877316] hub 1-1:1.0: USB hub found
10517 23:07:56.349559 <6>[ 1.877630] hub 1-1:1.0: 4 ports detected
10518 23:07:56.407772 <6>[ 2.001865] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10519 23:07:56.428490 <6>[ 2.026299] hub 2-1:1.0: USB hub found
10520 23:07:56.431865 <6>[ 2.026684] hub 2-1:1.0: 3 ports detected
10521 23:07:56.435009 <6>[ 2.029208] hub 2-1:1.0: USB hub found
10522 23:07:56.438310 <6>[ 2.029562] hub 2-1:1.0: 3 ports detected
10523 23:07:56.596204 <6>[ 2.189707] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10524 23:07:56.716635 <6>[ 2.316686] hub 1-1.4:1.0: USB hub found
10525 23:07:56.719749 <6>[ 2.317024] hub 1-1.4:1.0: 2 ports detected
10526 23:07:56.722998 <6>[ 2.320190] hub 1-1.4:1.0: USB hub found
10527 23:07:56.729640 <6>[ 2.320522] hub 1-1.4:1.0: 2 ports detected
10528 23:07:56.799399 <6>[ 2.393813] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10529 23:07:57.015750 <6>[ 2.609679] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10530 23:07:57.199410 <6>[ 2.793684] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10531 23:08:08.000241 <6>[ 13.602739] ALSA device list:
10532 23:08:08.006790 <6>[ 13.602761] No soundcards found.
10533 23:08:08.010413 <6>[ 13.607122] Freeing unused kernel memory: 8448K
10534 23:08:08.013125 <6>[ 13.607254] Run /init as init process
10535 23:08:08.024398 Starting syslogd: OK
10536 23:08:08.029267 Starting klogd: OK
10537 23:08:08.038065 Running sysctl: OK
10538 23:08:08.048144 Populating /dev using udev: <30>[ 13.649295] udevd[202]: starting version 3.2.9
10539 23:08:08.051568 <27>[ 13.652891] udevd[202]: specified user 'tss' unknown
10540 23:08:08.058295 <27>[ 13.652936] udevd[202]: specified group 'tss' unknown
10541 23:08:08.061644 <30>[ 13.654152] udevd[203]: starting eudev-3.2.9
10542 23:08:08.071266 <27>[ 13.672166] udevd[203]: specified user 'tss' unknown
10543 23:08:08.077814 <27>[ 13.672196] udevd[203]: specified group 'tss' unknown
10544 23:08:08.190804 <6>[ 13.786904] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10545 23:08:08.197388 <6>[ 13.786986] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10546 23:08:08.206647 <6>[ 13.786997] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10547 23:08:08.230617 <6>[ 13.825851] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10548 23:08:08.233556 <6>[ 13.830019] remoteproc remoteproc0: scp is available
10549 23:08:08.242988 <6>[ 13.830401] remoteproc remoteproc0: powering up scp
10550 23:08:08.253290 <6>[ 13.830408] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10551 23:08:08.256303 <6>[ 13.830441] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10552 23:08:08.263351 <6>[ 13.848918] mc: Linux media interface: v0.10
10553 23:08:08.269820 <6>[ 13.851661] usbcore: registered new interface driver r8152
10554 23:08:08.279437 <3>[ 13.876228] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10555 23:08:08.285980 <3>[ 13.876245] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10556 23:08:08.296038 <3>[ 13.876249] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10557 23:08:08.299463 <6>[ 13.876868] videodev: Linux video capture interface: v2.00
10558 23:08:08.309125 <4>[ 13.877850] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10559 23:08:08.316619 <4>[ 13.878521] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10560 23:08:08.322600 <3>[ 13.883367] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10561 23:08:08.332499 <3>[ 13.883400] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10562 23:08:08.339154 <3>[ 13.883406] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10563 23:08:08.349001 <3>[ 13.883416] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10564 23:08:08.355769 <3>[ 13.883422] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10565 23:08:08.362102 <3>[ 13.895130] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10566 23:08:08.372543 <6>[ 13.900337] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10567 23:08:08.379084 <3>[ 13.909637] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10568 23:08:08.389295 <3>[ 13.909649] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10569 23:08:08.396027 <3>[ 13.909653] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10570 23:08:08.402549 <6>[ 13.910469] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10571 23:08:08.409346 <6>[ 13.910487] pci_bus 0000:00: root bus resource [bus 00-ff]
10572 23:08:08.415920 <6>[ 13.910496] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10573 23:08:08.425862 <6>[ 13.910499] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10574 23:08:08.432676 <6>[ 13.910566] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10575 23:08:08.439060 <6>[ 13.910587] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10576 23:08:08.442212 <6>[ 13.910687] pci 0000:00:00.0: supports D1 D2
10577 23:08:08.448666 <6>[ 13.910690] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10578 23:08:08.458742 <6>[ 13.911810] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10579 23:08:08.465509 <6>[ 13.911886] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10580 23:08:08.472036 <6>[ 13.911911] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10581 23:08:08.478768 <6>[ 13.911926] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10582 23:08:08.488528 <6>[ 13.911941] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10583 23:08:08.491612 <6>[ 13.912045] pci 0000:01:00.0: supports D1 D2
10584 23:08:08.498797 <6>[ 13.912046] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10585 23:08:08.505244 <3>[ 13.912468] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10586 23:08:08.514604 <3>[ 13.912483] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10587 23:08:08.521299 <3>[ 13.912493] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10588 23:08:08.531890 <3>[ 13.912503] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10589 23:08:08.538137 <3>[ 13.912511] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10590 23:08:08.547991 <3>[ 13.912574] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10591 23:08:08.554680 <6>[ 13.921517] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10592 23:08:08.561053 <6>[ 13.921564] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10593 23:08:08.570682 <6>[ 13.921567] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10594 23:08:08.577610 <6>[ 13.921575] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10595 23:08:08.584282 <6>[ 13.921587] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10596 23:08:08.594004 <6>[ 13.921600] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10597 23:08:08.597335 <6>[ 13.921612] pci 0000:00:00.0: PCI bridge to [bus 01]
10598 23:08:08.607787 <6>[ 13.921618] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10599 23:08:08.613957 <6>[ 13.921801] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10600 23:08:08.620887 <6>[ 13.922404] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10601 23:08:08.623810 <6>[ 13.925749] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10602 23:08:08.634019 <6>[ 13.949731] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10603 23:08:08.640319 <6>[ 13.956026] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10604 23:08:08.646908 <6>[ 13.956029] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10605 23:08:08.653626 <6>[ 13.956044] remoteproc remoteproc0: remote processor scp is now up
10606 23:08:08.663352 <4>[ 13.957679] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10607 23:08:08.667141 <4>[ 13.957679] Fallback method does not support PEC.
10608 23:08:08.676923 <4>[ 13.977329] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10609 23:08:08.686963 <4>[ 13.977344] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10610 23:08:08.693002 <3>[ 13.979318] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10611 23:08:08.702932 <6>[ 13.984423] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10612 23:08:08.713750 <3>[ 14.002072] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10613 23:08:08.719836 <6>[ 14.010634] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10614 23:08:08.729465 <6>[ 14.012329] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10615 23:08:08.732773 <6>[ 14.025649] r8152 2-1.3:1.0 eth0: v1.12.13
10616 23:08:08.743220 <6>[ 14.030055] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10617 23:08:08.752419 <6>[ 14.030551] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10618 23:08:08.759340 <6>[ 14.046408] usbcore: registered new interface driver cdc_ether
10619 23:08:08.766196 <5>[ 14.052361] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10620 23:08:08.772793 <6>[ 14.057992] usbcore: registered new interface driver r8153_ecm
10621 23:08:08.779278 <5>[ 14.079240] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10622 23:08:08.789105 <4>[ 14.079326] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10623 23:08:08.792457 <6>[ 14.079335] cfg80211: failed to load regulatory.db
10624 23:08:08.795707 <6>[ 14.079937] Bluetooth: Core ver 2.22
10625 23:08:08.802481 <6>[ 14.080012] NET: Registered PF_BLUETOOTH protocol family
10626 23:08:08.808788 <6>[ 14.080014] Bluetooth: HCI device and connection manager initialized
10627 23:08:08.815640 <6>[ 14.080030] Bluetooth: HCI socket layer initialized
10628 23:08:08.818946 <6>[ 14.080033] Bluetooth: L2CAP socket layer initialized
10629 23:08:08.825518 <6>[ 14.080041] Bluetooth: SCO socket layer initialized
10630 23:08:08.832039 <6>[ 14.087614] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10631 23:08:08.845355 <6>[ 14.088608] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10632 23:08:08.848401 <6>[ 14.088688] usbcore: registered new interface driver uvcvideo
10633 23:08:08.854898 <6>[ 14.122271] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10634 23:08:08.861475 <6>[ 14.147178] usbcore: registered new interface driver btusb
10635 23:08:08.871314 <4>[ 14.148012] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10636 23:08:08.878206 <3>[ 14.148025] Bluetooth: hci0: Failed to load firmware file (-2)
10637 23:08:08.885121 <3>[ 14.148028] Bluetooth: hci0: Failed to set up firmware (-2)
10638 23:08:08.894649 <4>[ 14.148031] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10639 23:08:08.900955 <6>[ 14.203684] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10640 23:08:08.908251 <6>[ 14.203784] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10641 23:08:08.914085 <6>[ 14.221507] mt7921e 0000:01:00.0: ASIC revision: 79610010
10642 23:08:08.920520 <6>[ 14.316465] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
10643 23:08:08.923778 <6>[ 14.316465]
10644 23:08:08.951670 done
10645 23:08:08.960274 Saving random seed: OK
10646 23:08:08.978904 Starting network: <6>[ 14.576399] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
10647 23:08:08.983269 OK
10648 23:08:09.019232 Starting dropbear sshd: <6>[ 14.620770] NET: Registered PF_INET6 protocol family
10649 23:08:09.022528 <6>[ 14.621753] Segment Routing with IPv6
10650 23:08:09.029564 <6>[ 14.621767] In-situ OAM (IOAM) with IPv6
10651 23:08:09.029991 OK
10652 23:08:09.038335 /bin/sh: can't access tty; job control turned off
10653 23:08:09.039528 Matched prompt #10: / #
10655 23:08:09.040547 Setting prompt string to ['/ #']
10656 23:08:09.040975 end: 2.2.5.1 login-action (duration 00:00:15) [common]
10658 23:08:09.041965 end: 2.2.5 auto-login-action (duration 00:00:15) [common]
10659 23:08:09.042398 start: 2.2.6 expect-shell-connection (timeout 00:03:26) [common]
10660 23:08:09.042751 Setting prompt string to ['/ #']
10661 23:08:09.043065 Forcing a shell prompt, looking for ['/ #']
10663 23:08:09.093943 / #
10664 23:08:09.094460 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10665 23:08:09.094976 Waiting using forced prompt support (timeout 00:02:30)
10666 23:08:09.100313
10667 23:08:09.101113 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10668 23:08:09.101598 start: 2.2.7 export-device-env (timeout 00:03:26) [common]
10669 23:08:09.102075 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10670 23:08:09.102531 end: 2.2 depthcharge-retry (duration 00:01:34) [common]
10671 23:08:09.102997 end: 2 depthcharge-action (duration 00:01:34) [common]
10672 23:08:09.103515 start: 3 lava-test-retry (timeout 00:01:00) [common]
10673 23:08:09.103950 start: 3.1 lava-test-shell (timeout 00:01:00) [common]
10674 23:08:09.104342 Using namespace: common
10676 23:08:09.205370 / # #
10677 23:08:09.206002 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
10678 23:08:09.211632 #
10679 23:08:09.212492 Using /lava-12395373
10681 23:08:09.313709 / # export SHELL=/bin/sh
10682 23:08:09.319920 export SHELL=/bin/sh
10684 23:08:09.421313 / # . /lava-12395373/environment
10685 23:08:09.427672 . /lava-12395373/environment
10687 23:08:09.529224 / # /lava-12395373/bin/lava-test-runner /lava-12395373/0
10688 23:08:09.529779 Test shell timeout: 10s (minimum of the action and connection timeout)
10689 23:08:09.535704 /lava-12395373/bin/lava-test-runner /lava-12395373/0
10690 23:08:09.554713 + export 'TESTRUN_ID=0_dmesg'
10691 23:08:09.558301 + cd /lava-12395373/0/tests/0_dmesg
10692 23:08:09.561789 + cat uuid
10693 23:08:09.564556 <8>[ 15.162918] <LAVA_SIGNAL_STARTRUN 0_dmesg 12395373_1.5.2.3.1>
10694 23:08:09.565254 Received signal: <STARTRUN> 0_dmesg 12395373_1.5.2.3.1
10695 23:08:09.565646 Starting test lava.0_dmesg (12395373_1.5.2.3.1)
10696 23:08:09.566072 Skipping test definition patterns.
10697 23:08:09.567989 + UUID=12395373_1.5.2.3.1
10698 23:08:09.568413 + set +x
10699 23:08:09.574774 + KERNELCI_LAVA=y /bin/sh /opt/kernelci/dmesg.sh
10700 23:08:09.586988 <8>[ 15.181950] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0>
10701 23:08:09.587695 Received signal: <TESTCASE> TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0
10703 23:08:09.596985 <8>[ 15.193377] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0>
10704 23:08:09.597668 Received signal: <TESTCASE> TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0
10706 23:08:09.606739 <8>[ 15.205271] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0>
10707 23:08:09.607162 + set +x
10708 23:08:09.607801 Received signal: <TESTCASE> TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0
10710 23:08:09.610613 <LAVA_TEST_RUNNER EXIT>
10711 23:08:09.611284 ok: lava_test_shell seems to have completed
10712 23:08:09.611709 Marking unfinished test run as failed
10714 23:08:09.612660 alert: pass
crit: pass
emerg: pass
10715 23:08:09.613056 end: 3.1 lava-test-shell (duration 00:00:01) [common]
10716 23:08:09.613463 end: 3 lava-test-retry (duration 00:00:01) [common]
10717 23:08:09.613877 start: 4 lava-test-retry (timeout 00:01:00) [common]
10718 23:08:09.614293 start: 4.1 lava-test-shell (timeout 00:01:00) [common]
10719 23:08:09.614618 Using namespace: common
10721 23:08:09.715638 / # <8>[ 15.214#
10722 23:08:09.716237 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
10723 23:08:09.716856 Using /lava-12395373
10725 23:08:09.817895 export SHELL=/bin/sh
10726 23:08:09.818671 230] <LAVA_SIGNAL_ENDRUN 0_dmesg 12395373_1.5.2.3.1>
10727 23:08:09.819141 #
10728 23:08:09.819694 / # export SHELL=/bin/sh<6>[ 15.414459] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10730 23:08:09.921079 . /lava-12395373/environment
10731 23:08:09.921279
10733 23:08:10.021793 / # . /lava-12395373/environment/lava-12395373/bin/lava-test-runner /lava-12395373/1
10734 23:08:10.022008 Test shell timeout: 10s (minimum of the action and connection timeout)
10735 23:08:10.022246
10736 23:08:10.027498 / # /lava-12395373/bin/lava-test-runner /lava-12395373/1
10737 23:08:10.045655 + export 'TESTRUN_ID=1_bootrr'
10738 23:08:10.052279 <8>[ 15.652904] <LAVA_SIGNAL_STARTRUN 1_bootrr 12395373_1.5.2.3.5>
10739 23:08:10.052538 Received signal: <STARTRUN> 1_bootrr 12395373_1.5.2.3.5
10740 23:08:10.052617 Starting test lava.1_bootrr (12395373_1.5.2.3.5)
10741 23:08:10.052724 Skipping test definition patterns.
10742 23:08:10.055368 + cd /lava-12395373/1/tests/1_bootrr
10743 23:08:10.058849 + cat uuid
10744 23:08:10.058926 + UUID=12395373_1.5.2.3.5
10745 23:08:10.059007 + set +x
10746 23:08:10.068901 + export 'PATH=/opt/bootr<8>[ 15.668962] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=deferred-probe-empty RESULT=pass>
10747 23:08:10.069154 Received signal: <TESTCASE> TEST_CASE_ID=deferred-probe-empty RESULT=pass
10749 23:08:10.082109 r/libexec/bootrr/helpers:/lava-12395373/1/../bin<8>[ 15.680971] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=all-cpus-are-online RESULT=pass>
10750 23:08:10.082366 Received signal: <TESTCASE> TEST_CASE_ID=all-cpus-are-online RESULT=pass
10752 23:08:10.085479 :/sbin:/usr/sbin:/bin:/usr/bin'
10753 23:08:10.088986 + cd /opt/bootrr/libexec/bootrr
10754 23:08:10.089077 + sh helpers/bootrr-auto
10755 23:08:10.104938 /lava-12395373/1/../bin/lava-test-case
10756 23:08:10.105142 /lava-12395373/1/../bin/lava-test-case
10757 23:08:10.105288 /usr/bin/tpm2_getcap
10758 23:08:10.119315 /lava-12395373/1/../bin/lava-test-case
10759 23:08:10.124965 <8>[ 15.724889] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm-chip-is-online RESULT=pass>
10760 23:08:10.125223 Received signal: <TESTCASE> TEST_CASE_ID=tpm-chip-is-online RESULT=pass
10762 23:08:10.137743 /lava-12395373/1/../bin/lava-test-case
10763 23:08:10.147324 <8>[ 15.743291] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass>
10764 23:08:10.147625 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass
10766 23:08:10.150692 /lava-12395373/1/../bin/lava-test-case
10767 23:08:10.157850 <8>[ 15.756646] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass>
10768 23:08:10.158114 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass
10770 23:08:10.160520 /lava-12395373/1/../bin/lava-test-case
10771 23:08:10.170636 <8>[ 15.768754] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass>
10772 23:08:10.170909 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass
10774 23:08:10.174122 /lava-12395373/1/../bin/lava-test-case
10775 23:08:10.186595 <8>[ 15.782263] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass>
10776 23:08:10.186967 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass
10778 23:08:10.189774 /lava-12395373/1/../bin/lava-test-case
10779 23:08:10.202385 <8>[ 15.797930] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass>
10780 23:08:10.202665 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass
10782 23:08:10.205831 /lava-12395373/1/../bin/lava-test-case
10783 23:08:10.215770 <8>[ 15.812708] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass>
10784 23:08:10.216023 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass
10786 23:08:10.218585 /lava-12395373/1/../bin/lava-test-case
10787 23:08:10.230178 <8>[ 15.825599] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass>
10788 23:08:10.230431 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass
10790 23:08:10.233646 /lava-12395373/1/../bin/lava-test-case
10791 23:08:10.243868 <8>[ 15.840797] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass>
10792 23:08:10.244121 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass
10794 23:08:10.253303 /lava-12395373/1/../bin/lava-tes<8>[ 15.853358] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass>
10795 23:08:10.253555 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass
10797 23:08:10.257412 t-case
10798 23:08:10.260259 /lava-12395373/1/../bin/lava-test-case
10799 23:08:10.270537 <8>[ 15.865893] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass>
10800 23:08:10.271213 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass
10802 23:08:10.273955 /lava-12395373/1/../bin/lava-test-case
10803 23:08:10.283886 <8>[ 15.881102] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass>
10804 23:08:10.284703 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass
10806 23:08:10.294499 /lava-12395373/1/../bin/lava-tes<8>[ 15.893367] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass>
10807 23:08:10.295353 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass
10809 23:08:10.297075 t-case
10810 23:08:10.300478 /lava-12395373/1/../bin/lava-test-case
10811 23:08:10.307004 <8>[ 15.905146] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass>
10812 23:08:10.307737 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass
10814 23:08:10.310645 /lava-12395373/1/../bin/lava-test-case
10815 23:08:10.322698 <8>[ 15.918992] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass>
10816 23:08:10.323411 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass
10818 23:08:10.326048 /lava-12395373/1/../bin/lava-test-case
10819 23:08:10.335869 <8>[ 15.933147] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass>
10820 23:08:10.336590 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass
10822 23:08:10.339013 /lava-12395373/1/../bin/lava-test-case
10823 23:08:10.350922 <8>[ 15.946320] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass>
10824 23:08:10.351605 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass
10826 23:08:10.354732 /lava-12395373/1/../bin/lava-test-case
10827 23:08:10.360490 <8>[ 15.960074] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass>
10828 23:08:10.360743 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass
10830 23:08:10.366877 /lava-12395373/1/../bin/lava-test-case
10831 23:08:10.373697 <8>[ 15.972434] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-probed RESULT=pass>
10832 23:08:10.373973 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-probed RESULT=pass
10834 23:08:10.377468 /lava-12395373/1/../bin/lava-test-case
10835 23:08:10.387090 <8>[ 15.984646] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass>
10836 23:08:10.387354 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass
10838 23:08:10.390065 /lava-12395373/1/../bin/lava-test-case
10839 23:08:10.402210 /lava-12395373/1<8>[ 15.998017] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass>
10840 23:08:10.402464 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass
10842 23:08:10.412645 <8>[ 16.006498] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass>
10843 23:08:10.412743 /../bin/lava-test-case
10844 23:08:10.412993 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass
10846 23:08:10.419093 /lava-12395373/1/../bin/lava-test-case
10847 23:08:10.426103 <8>[ 16.023464] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass>
10848 23:08:10.426407 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass
10850 23:08:10.428779 /lava-12395373/1/../bin/lava-test-case
10851 23:08:10.442362 <8>[ 16.038141] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass>
10852 23:08:10.442616 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass
10854 23:08:10.445880 /lava-12395373/1/../bin/lava-test-case
10855 23:08:10.455662 <8>[ 16.053239] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass>
10856 23:08:10.455916 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass
10858 23:08:10.458738 /lava-12395373/1/../bin/lava-test-case
10859 23:08:10.470464 <8>[ 16.065574] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass>
10860 23:08:10.470716 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass
10862 23:08:10.473487 /lava-12395373/1/../bin/lava-test-case
10863 23:08:10.483207 <8>[ 16.080450] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass>
10864 23:08:10.483487 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass
10866 23:08:10.486755 /lava-12395373/1/../bin/lava-test-case
10867 23:08:10.493650 <8>[ 16.092718] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass>
10868 23:08:10.493917 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass
10870 23:08:10.496902 /lava-12395373/1/../bin/lava-test-case
10871 23:08:10.506694 <8>[ 16.104760] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass>
10872 23:08:10.506997 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass
10874 23:08:10.510187 /lava-12395373/1/../bin/lava-test-case
10875 23:08:10.522345 <8>[ 16.117488] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass>
10876 23:08:10.522724 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass
10878 23:08:10.526296 /lava-12395373/1/../bin/lava-test-case
10879 23:08:10.532312 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass
10881 23:08:10.535641 <8>[ 16.132717] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass>
10882 23:08:10.539131 /lava-12395373/1/../bin/lava-test-case
10883 23:08:10.545268 <8>[ 16.144441] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass>
10884 23:08:10.545521 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass
10886 23:08:10.549074 /lava-12395373/1/../bin/lava-test-case
10887 23:08:10.558576 <8>[ 16.156912] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass>
10888 23:08:10.558829 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass
10890 23:08:10.562296 /lava-12395373/1/../bin/lava-test-case
10891 23:08:10.568839 <8>[ 16.169119] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass>
10892 23:08:10.569093 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass
10894 23:08:10.571963 /lava-12395373/1/../bin/lava-test-case
10895 23:08:10.582283 <8>[ 16.180279] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass>
10896 23:08:10.582537 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass
10898 23:08:10.585427 /lava-12395373/1/../bin/lava-test-case
10899 23:08:10.592223 <8>[ 16.192901] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass>
10900 23:08:10.592476 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass
10902 23:08:10.598749 /lava-12395373/1/../bin/lava-test-case
10903 23:08:10.605098 <8>[ 16.204305] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass>
10904 23:08:10.605355 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass
10906 23:08:10.608999 /lava-12395373/1/../bin/lava-test-case
10907 23:08:10.622135 <8>[ 16.217598] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass>
10908 23:08:10.622388 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass
10910 23:08:10.625521 /lava-12395373/1/../bin/lava-test-case
10911 23:08:10.635719 <8>[ 16.232297] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass>
10912 23:08:10.635989 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass
10914 23:08:10.639095 /lava-12395373/1/../bin/lava-test-case
10915 23:08:10.650092 <8>[ 16.245946] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass>
10916 23:08:10.650345 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass
10918 23:08:10.653522 /lava-12395373/1/../bin/lava-test-case
10919 23:08:10.664129 <8>[ 16.260228] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass>
10920 23:08:10.664382 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass
10922 23:08:10.666643 /lava-12395373/1/../bin/lava-test-case
10923 23:08:10.678598 <8>[ 16.273396] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-probed RESULT=pass>
10924 23:08:10.678853 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-probed RESULT=pass
10926 23:08:10.681520 /lava-12395373/1/../bin/lava-test-case
10927 23:08:10.694240 <8>[ 16.290498] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass>
10928 23:08:10.694496 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass
10930 23:08:10.697548 /lava-12395373/1/../bin/lava-test-case
10931 23:08:10.710197 /lava-12395373/1<8>[ 16.305983] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass>
10932 23:08:10.710451 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass
10934 23:08:10.720059 /../bin/lava-tes<8>[ 16.314525] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass>
10935 23:08:10.720141 t-case
10936 23:08:10.720376 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass
10938 23:08:10.723210 /lava-12395373/1/../bin/lava-test-case
10939 23:08:10.734274 <8>[ 16.331600] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-probed RESULT=pass>
10940 23:08:10.734555 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-probed RESULT=pass
10942 23:08:10.737875 /lava-12395373/1/../bin/lava-test-case
10943 23:08:10.747228 <8>[ 16.343556] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass>
10944 23:08:10.747475 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass
10946 23:08:10.750677 /lava-12395373/1/../bin/lava-test-case
10947 23:08:10.757460 <8>[ 16.357157] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass>
10948 23:08:10.757717 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass
10950 23:08:10.760870 /lava-12395373/1/../bin/lava-test-case
10951 23:08:10.770799 <8>[ 16.369292] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass>
10952 23:08:10.771047 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass
10954 23:08:10.774267 /lava-12395373/1/../bin/lava-test-case
10955 23:08:10.781011 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=pass
10957 23:08:10.783738 <8>[ 16.380306] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=pass>
10958 23:08:10.787228 /lava-12395373/1/../bin/lava-test-case
10959 23:08:10.798016 /lava-12395373/1<8>[ 16.393805] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=pass>
10960 23:08:10.798263 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=pass
10962 23:08:10.808350 <8>[ 16.401150] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass>
10963 23:08:10.808428 /../bin/lava-test-case
10964 23:08:10.808661 Received signal: <TESTCASE> TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass
10966 23:08:10.811320 /lava-12395373/1/../bin/lava-test-case
10967 23:08:10.822207 <8>[ 16.418217] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass>
10968 23:08:10.822457 Received signal: <TESTCASE> TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass
10970 23:08:10.825709 /lava-12395373/1/../bin/lava-test-case
10971 23:08:10.832329 <8>[ 16.432790] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass>
10972 23:08:10.832590 Received signal: <TESTCASE> TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass
10974 23:08:10.835714 /lava-12395373/1/../bin/lava-test-case
10975 23:08:10.846126 <8>[ 16.443851] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass>
10976 23:08:10.846421 Received signal: <TESTCASE> TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass
10978 23:08:10.849434 /lava-12395373/1/../bin/lava-test-case
10979 23:08:10.856437 <8>[ 16.455867] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass>
10980 23:08:10.856777 Received signal: <TESTCASE> TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass
10982 23:08:10.859167 /lava-12395373/1/../bin/lava-test-case
10983 23:08:10.869869 <8>[ 16.469002] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass>
10984 23:08:10.870159 Received signal: <TESTCASE> TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass
10986 23:08:10.873129 /lava-12395373/1/../bin/lava-test-case
10987 23:08:10.880036 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-driver-present RESULT=pass
10989 23:08:10.883325 <8>[ 16.479659] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-driver-present RESULT=pass>
10990 23:08:10.886362 /lava-12395373/1/../bin/lava-test-case
10991 23:08:10.893040 <8>[ 16.492378] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi1-probed RESULT=pass>
10992 23:08:10.893290 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi1-probed RESULT=pass
10994 23:08:10.896817 /lava-12395373/1/../bin/lava-test-case
10995 23:08:10.906293 <8>[ 16.503644] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi5-probed RESULT=pass>
10996 23:08:10.906554 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi5-probed RESULT=pass
10998 23:08:10.909866 /lava-12395373/1/../bin/lava-test-case
10999 23:08:10.916318 <8>[ 16.516884] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass>
11000 23:08:10.916576 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass
11002 23:08:10.923475 /lava-12395373/1/../bin/lava-test-case
11003 23:08:10.929876 <8>[ 16.528578] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-probed RESULT=pass>
11004 23:08:10.930133 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-probed RESULT=pass
11006 23:08:10.933149 /lava-12395373/1/../bin/lava-test-case
11007 23:08:10.943114 <8>[ 16.539854] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass>
11008 23:08:10.943419 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass
11010 23:08:10.946435 /lava-12395373/1/../bin/lava-test-case
11011 23:08:10.958512 <8>[ 16.553595] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-probed RESULT=pass>
11012 23:08:10.958788 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-probed RESULT=pass
11014 23:08:10.961693 /lava-12395373/1/../bin/lava-test-case
11015 23:08:10.968732 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass
11017 23:08:10.971580 <8>[ 16.568281] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass>
11018 23:08:10.974613 /lava-12395373/1/../bin/lava-test-case
11019 23:08:10.981899 <8>[ 16.580615] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass>
11020 23:08:10.982158 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass
11022 23:08:10.984811 /lava-12395373/1/../bin/lava-test-case
11023 23:08:10.994927 <8>[ 16.592914] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass>
11024 23:08:10.995187 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass
11026 23:08:10.998569 /lava-12395373/1/../bin/lava-test-case
11027 23:08:11.004826 <8>[ 16.603951] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass>
11028 23:08:11.005080 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass
11030 23:08:11.008448 /lava-12395373/1/../bin/lava-test-case
11031 23:08:11.018464 <8>[ 16.616308] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass>
11032 23:08:11.018723 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass
11034 23:08:11.021588 /lava-12395373/1/../bin/lava-test-case
11035 23:08:11.028317 <8>[ 16.628204] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass>
11036 23:08:11.028576 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass
11038 23:08:11.031309 /lava-12395373/1/../bin/lava-test-case
11039 23:08:11.042287 <8>[ 16.639694] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass>
11040 23:08:11.042544 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass
11042 23:08:11.045685 /lava-12395373/1/../bin/lava-test-case
11043 23:08:11.055479 <8>[ 16.652751] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass>
11044 23:08:11.055734 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass
11046 23:08:11.058507 /lava-12395373/1/../bin/lava-test-case
11047 23:08:11.065111 <8>[ 16.664564] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass>
11048 23:08:11.065366 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass
11050 23:08:11.068449 /lava-12395373/1/../bin/lava-test-case
11051 23:08:11.082071 <8>[ 16.678079] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass>
11052 23:08:11.082324 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass
11054 23:08:11.085381 /lava-12395373/1/../bin/lava-test-case
11055 23:08:11.092189 <8>[ 16.692060] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass>
11056 23:08:11.092468 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass
11058 23:08:11.096139 /lava-12395373/1/../bin/lava-test-case
11059 23:08:11.106147 <8>[ 16.704246] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass>
11060 23:08:11.106402 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass
11062 23:08:11.109488 /lava-12395373/1/../bin/lava-test-case
11063 23:08:11.115784 <8>[ 16.717100] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass>
11064 23:08:11.116043 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass
11066 23:08:11.126795 /lava-12395373/1/../bin/lava-test-case
11067 23:08:11.133398 <8>[ 16.732644] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass>
11068 23:08:11.133658 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass
11070 23:08:11.136720 /lava-12395373/1/../bin/lava-test-case
11071 23:08:11.147005 <8>[ 16.744053] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass>
11072 23:08:11.147268 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass
11074 23:08:11.150328 /lava-12395373/1/../bin/lava-test-case
11075 23:08:11.156433 <8>[ 16.756297] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass>
11076 23:08:11.156684 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass
11078 23:08:11.160066 /lava-12395373/1/../bin/lava-test-case
11079 23:08:11.170473 <8>[ 16.768884] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass>
11080 23:08:11.171251 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass
11082 23:08:11.179997 /lava-12395373/1/../bin/lava-test-case
11083 23:08:11.191005 <8>[ 16.785783] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-probed RESULT=pass>
11084 23:08:11.191913 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-probed RESULT=pass
11086 23:08:11.194389 /lava-12395373/1/../bin/lava-test-case
11087 23:08:11.204085 <8>[ 16.799955] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass>
11088 23:08:11.204949 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass
11090 23:08:11.207039 /lava-12395373/1/../bin/lava-test-case
11091 23:08:11.218869 <8>[ 16.814821] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-probed RESULT=pass>
11092 23:08:11.219701 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-probed RESULT=pass
11094 23:08:11.221796 /lava-12395373/1/../bin/lava-test-case
11095 23:08:11.231488 <8>[ 16.828019] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass>
11096 23:08:11.232214 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass
11098 23:08:11.235131 /lava-12395373/1/../bin/lava-test-case
11099 23:08:11.241633 <8>[ 16.841047] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass>
11100 23:08:11.242435 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass
11102 23:08:11.252931 /lava-12395373/1/../bin/lava-test-case
11103 23:08:11.262901 <8>[ 16.858957] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass>
11104 23:08:11.263379 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass
11106 23:08:11.266306 /lava-12395373/1/../bin/lava-test-case
11107 23:08:11.277970 <8>[ 16.873614] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-probed RESULT=pass>
11108 23:08:11.278234 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-probed RESULT=pass
11110 23:08:11.281344 /lava-12395373/1/../bin/lava-test-case
11111 23:08:11.291277 <8>[ 16.888148] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass>
11112 23:08:11.291556 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass
11114 23:08:11.295185 /lava-12395373/1/../bin/lava-test-case
11115 23:08:11.306337 <8>[ 16.902346] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass>
11116 23:08:11.306589 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass
11118 23:08:11.309763 /lava-12395373/1/../bin/lava-test-case
11119 23:08:11.319332 <8>[ 16.916794] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass>
11120 23:08:11.319619 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass
11122 23:08:11.322850 /lava-12395373/1/../bin/lava-test-case
11123 23:08:11.334193 <8>[ 16.929876] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass>
11124 23:08:11.334463 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass
11126 23:08:11.337623 /lava-12395373/1/../bin/lava-test-case
11127 23:08:11.349753 /lava-12395373/1<8>[ 16.945475] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass>
11128 23:08:11.350018 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass
11130 23:08:11.359454 <8>[ 16.952823] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass>
11131 23:08:11.359543 /../bin/lava-test-case
11132 23:08:11.359804 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass
11134 23:08:11.366225 /lava-12395373/1/../bin/lava-test-case
11135 23:08:11.372720 <8>[ 16.969603] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass>
11136 23:08:11.372973 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass
11138 23:08:11.376061 /lava-12395373/1/../bin/lava-test-case
11139 23:08:11.386297 <8>[ 16.984974] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-driver-present RESULT=pass>
11140 23:08:11.386558 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-driver-present RESULT=pass
11142 23:08:11.389595 /lava-12395373/1/../bin/lava-test-case
11143 23:08:11.395748 <8>[ 16.996944] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-probed RESULT=pass>
11144 23:08:11.396003 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-probed RESULT=pass
11146 23:08:11.399655 /lava-12395373/1/../bin/lava-test-case
11147 23:08:11.409959 <8>[ 17.008287] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-driver-present RESULT=pass>
11148 23:08:11.410212 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-driver-present RESULT=pass
11150 23:08:12.414051 /lava-12395373/1/../bin/lava-test-case
11151 23:08:12.420824 <8>[ 18.020478] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-probed RESULT=fail>
11152 23:08:12.421092 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-probed RESULT=fail
11154 23:08:12.423675 /lava-12395373/1/../bin/lava-test-case
11155 23:08:12.434232 <8>[ 18.031864] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-driver-present RESULT=pass>
11156 23:08:12.434485 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-driver-present RESULT=pass
11158 23:08:13.436927 /lava-12395373/1/../bin/lava-test-case
11159 23:08:13.450006 <8>[ 19.045650] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-probed RESULT=fail>
11160 23:08:13.450286 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-probed RESULT=fail
11162 23:08:13.452905 /lava-12395373/1/../bin/lava-test-case
11163 23:08:13.463164 <8>[ 19.059848] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass>
11164 23:08:13.463419 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass
11166 23:08:14.465021 /lava-12395373/1/../bin/lava-test-case
11167 23:08:14.471596 <8>[ 20.072679] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail>
11168 23:08:14.471865 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail
11170 23:08:14.478336 /lava-12395373/1/../bin/lava-test-case
11171 23:08:14.485136 <8>[ 20.084297] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass>
11172 23:08:14.485389 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass
11174 23:08:15.490547 /lava-12395373/1/../bin/lava-test-case
11175 23:08:15.497035 <8>[ 21.097011] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-probed RESULT=fail>
11176 23:08:15.497300 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-probed RESULT=fail
11178 23:08:15.500369 /lava-12395373/1/../bin/lava-test-case
11179 23:08:15.510283 <8>[ 21.108421] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-driver-present RESULT=pass>
11180 23:08:15.510570 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-driver-present RESULT=pass
11182 23:08:16.513233 /lava-12395373/1/../bin/lava-test-case
11183 23:08:16.525245 <8>[ 22.122141] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-3-probed RESULT=fail>
11184 23:08:16.525519 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-3-probed RESULT=fail
11186 23:08:16.528538 /lava-12395373/1/../bin/lava-test-case
11187 23:08:16.538407 <8>[ 22.136571] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass>
11188 23:08:16.538661 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass
11190 23:08:17.542573 /lava-12395373/1/../bin/lava-test-case
11191 23:08:17.548666 <8>[ 23.148537] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail>
11192 23:08:17.548937 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail
11194 23:08:17.551686 /lava-12395373/1/../bin/lava-test-case
11195 23:08:17.561505 <8>[ 23.161076] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass>
11196 23:08:17.561764 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass
11198 23:08:18.565393 /lava-12395373/1/../bin/lava-test-case
11199 23:08:18.577376 <8>[ 24.174093] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-probed RESULT=fail>
11200 23:08:18.577747 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-probed RESULT=fail
11202 23:08:18.580458 /lava-12395373/1/../bin/lava-test-case
11203 23:08:18.587257 <8>[ 24.188728] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-edp-driver-present RESULT=pass>
11204 23:08:18.587583 Received signal: <TESTCASE> TEST_CASE_ID=panel-edp-driver-present RESULT=pass
11206 23:08:18.594290 /lava-12395373/1/../bin/lava-test-case
11207 23:08:18.600353 <8>[ 24.201019] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass>
11208 23:08:18.600712 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass
11210 23:08:19.605598 /lava-12395373/1/../bin/lava-test-case
11211 23:08:19.611894 <8>[ 25.212205] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail>
11212 23:08:19.612168 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail
11214 23:08:19.615044 /lava-12395373/1/../bin/lava-test-case
11215 23:08:19.625155 <8>[ 25.224652] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass>
11216 23:08:19.625417 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass
11218 23:08:19.628103 /lava-12395373/1/../bin/lava-test-case
11219 23:08:19.641988 <8>[ 25.238477] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-probed RESULT=pass>
11220 23:08:19.642263 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-probed RESULT=pass
11222 23:08:19.644939 /lava-12395373/1/../bin/lava-test-case
11223 23:08:19.654525 <8>[ 25.252260] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass>
11224 23:08:19.654901 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass
11226 23:08:19.657906 /lava-12395373/1/../bin/lava-test-case
11227 23:08:19.664640 <8>[ 25.265045] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass>
11228 23:08:19.664982 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass
11230 23:08:19.668171 /lava-12395373/1/../bin/lava-test-case
11231 23:08:19.677768 <8>[ 25.276744] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass>
11232 23:08:19.678171 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass
11234 23:08:19.681018 /lava-12395373/1/../bin/lava-test-case
11235 23:08:19.693637 <8>[ 25.291114] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass>
11236 23:08:19.694298 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass
11238 23:08:19.696716 /lava-12395373/1/../bin/lava-test-case
11239 23:08:19.707469 <8>[ 25.304723] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass>
11240 23:08:19.708212 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass
11242 23:08:19.710270 /lava-12395373/1/../bin/lava-test-case
11243 23:08:19.716676 <8>[ 25.316981] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass>
11244 23:08:19.717392 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass
11246 23:08:19.720733 /lava-12395373/1/../bin/lava-test-case
11247 23:08:19.733544 <8>[ 25.329841] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass>
11248 23:08:19.734442 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass
11250 23:08:19.736951 /lava-12395373/1/../bin/lava-test-case
11251 23:08:19.749500 <8>[ 25.345806] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass>
11252 23:08:19.750297 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass
11254 23:08:19.752702 /lava-12395373/1/../bin/lava-test-case
11255 23:08:19.765354 <8>[ 25.361975] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass>
11256 23:08:19.766223 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass
11258 23:08:19.768661 /lava-12395373/1/../bin/lava-test-case
11259 23:08:19.781939 <8>[ 25.378016] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass>
11260 23:08:19.782824 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass
11262 23:08:19.784686 /lava-12395373/1/../bin/lava-test-case
11263 23:08:19.797499 <8>[ 25.394345] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass>
11264 23:08:19.798284 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass
11266 23:08:19.800737 /lava-12395373/1/../bin/lava-test-case
11267 23:08:19.810770 <8>[ 25.408541] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass>
11268 23:08:19.811572 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass
11270 23:08:19.814044 /lava-12395373/1/../bin/lava-test-case
11271 23:08:19.825766 <8>[ 25.422156] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass>
11272 23:08:19.826441 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass
11274 23:08:19.829339 /lava-12395373/1/../bin/lava-test-case
11275 23:08:19.838890 <8>[ 25.437170] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass>
11276 23:08:19.839567 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass
11278 23:08:19.842293 /lava-12395373/1/../bin/lava-test-case
11279 23:08:19.848550 <8>[ 25.449117] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass>
11280 23:08:19.849217 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass
11282 23:08:19.852158 /lava-12395373/1/../bin/lava-test-case
11283 23:08:19.862101 <8>[ 25.460858] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass>
11284 23:08:19.862810 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass
11286 23:08:19.865115 /lava-12395373/1/../bin/lava-test-case
11287 23:08:19.878142 <8>[ 25.473572] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-probed RESULT=pass>
11288 23:08:19.878962 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-probed RESULT=pass
11290 23:08:19.880875 /lava-12395373/1/../bin/lava-test-case
11291 23:08:19.890651 <8>[ 25.488141] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass>
11292 23:08:19.891472 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass
11294 23:08:20.893177 /lava-12395373/1/../bin/lava-test-case
11295 23:08:20.899445 <8>[ 26.500134] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-probed RESULT=fail>
11296 23:08:20.900204 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-probed RESULT=fail
11298 23:08:21.905863 /lava-12395373/1/../bin/lava-test-case
11299 23:08:21.917815 <8>[ 27.514216] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-7-probed RESULT=fail>
11300 23:08:21.918577 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-7-probed RESULT=fail
11302 23:08:21.921124 /lava-12395373/1/../bin/lava-test-case
11303 23:08:21.927829 <8>[ 27.528681] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-driver-present RESULT=pass>
11304 23:08:21.928535 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-driver-present RESULT=pass
11306 23:08:21.934506 /lava-12395373/1/../bin/lava-test-case
11307 23:08:21.940504 <8>[ 27.540682] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-probed RESULT=pass>
11308 23:08:21.941174 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-probed RESULT=pass
11310 23:08:21.944213 /lava-12395373/1/../bin/lava-test-case
11311 23:08:21.954006 <8>[ 27.551858] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass>
11312 23:08:21.954694 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass
11314 23:08:21.957747 /lava-12395373/1/../bin/lava-test-case
11315 23:08:21.969564 <8>[ 27.566469] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass>
11316 23:08:21.970239 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass
11318 23:08:21.973029 /lava-12395373/1/../bin/lava-test-case
11319 23:08:21.979528 <8>[ 27.580292] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-driver-present RESULT=pass>
11320 23:08:21.980243 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-driver-present RESULT=pass
11322 23:08:21.986550 /lava-12395373/1/../bin/lava-test-case
11323 23:08:21.992905 <8>[ 27.592394] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-probed RESULT=pass>
11324 23:08:21.993718 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-probed RESULT=pass
11326 23:08:21.995715 /lava-12395373/1/../bin/lava-test-case
11327 23:08:22.005762 <8>[ 27.603640] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass>
11328 23:08:22.006564 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass
11330 23:08:22.009273 /lava-12395373/1/../bin/lava-test-case
11331 23:08:22.021340 <8>[ 27.618926] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass>
11332 23:08:22.022020 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass
11334 23:08:22.025134 /lava-12395373/1/../bin/lava-test-case
11335 23:08:22.037510 <8>[ 27.633998] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass>
11336 23:08:22.038180 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass
11338 23:08:22.041018 /lava-12395373/1/../bin/lava-test-case
11339 23:08:22.047067 <8>[ 27.649205] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-probed RESULT=pass>
11340 23:08:22.047788 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-probed RESULT=pass
11342 23:08:22.050900 /lava-12395373/1/../bin/lava-test-case
11343 23:08:22.061236 <8>[ 27.660801] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass>
11344 23:08:22.061982 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass
11346 23:08:22.064582 /lava-12395373/1/../bin/lava-test-case
11347 23:08:22.070490 <8>[ 27.672629] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass>
11348 23:08:22.070751 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass
11350 23:08:22.074145 /lava-12395373/1/../bin/lava-test-case
11351 23:08:22.085229 <8>[ 27.683732] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass>
11352 23:08:22.085481 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass
11354 23:08:22.088573 /lava-12395373/1/../bin/lava-test-case
11355 23:08:22.095074 <8>[ 27.697026] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-probed RESULT=pass>
11356 23:08:22.095400 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-probed RESULT=pass
11358 23:08:22.098524 /lava-12395373/1/../bin/lava-test-case
11359 23:08:22.108998 <8>[ 27.707536] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass>
11360 23:08:22.109364 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass
11362 23:08:22.112495 /lava-12395373/1/../bin/lava-test-case
11363 23:08:22.125774 /lava-12395373/1<8>[ 27.721920] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-probed RESULT=pass>
11364 23:08:22.126535 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-probed RESULT=pass
11366 23:08:22.135420 /../bin/lava-tes<8>[ 27.729150] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-driver-present RESULT=pass>
11367 23:08:22.135843 t-case
11368 23:08:22.136424 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-driver-present RESULT=pass
11370 23:08:22.138993 /lava-12395373/1/../bin/lava-test-case
11371 23:08:22.149268 <8>[ 27.747504] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-probed RESULT=pass>
11372 23:08:22.149964 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-probed RESULT=pass
11374 23:08:22.152380 /lava-12395373/1/../bin/lava-test-case
11375 23:08:22.162449 <8>[ 27.759412] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass>
11376 23:08:22.163117 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass
11378 23:08:22.165645 /lava-12395373/1/../bin/lava-test-case
11379 23:08:22.177357 <8>[ 27.773845] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass>
11380 23:08:22.178065 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass
11382 23:08:23.177102 /lava-12395373/1/../bin/lava-test-case
11383 23:08:23.188602 <8>[ 28.786320] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail>
11384 23:08:23.188885 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail
11386 23:08:24.189082 /lava-12395373/1/../bin/lava-test-case
11387 23:08:24.195643 <8>[ 29.796672] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked>
11388 23:08:24.195907 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked
11389 23:08:24.195992 Bad test result: blocked
11390 23:08:24.198723 /lava-12395373/1/../bin/lava-test-case
11391 23:08:24.208573 <8>[ 29.808426] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-driver-present RESULT=pass>
11392 23:08:24.208849 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-driver-present RESULT=pass
11394 23:08:25.215813 /lava-12395373/1/../bin/lava-test-case
11395 23:08:25.222012 <8>[ 30.824171] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-probed RESULT=fail>
11396 23:08:25.222276 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-probed RESULT=fail
11398 23:08:25.228598 /lava-12395373/1/../bin/lava-test-case
11399 23:08:25.235277 <8>[ 30.836269] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo-driver-present RESULT=pass>
11400 23:08:25.235587 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo-driver-present RESULT=pass
11402 23:08:25.238630 /lava-12395373/1/../bin/lava-test-case
11403 23:08:25.252469 <8>[ 30.850256] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo0-probed RESULT=pass>
11404 23:08:25.252714 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo0-probed RESULT=pass
11406 23:08:25.256055 /lava-12395373/1/../bin/lava-test-case
11407 23:08:25.262569 <8>[ 30.864370] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo1-probed RESULT=pass>
11408 23:08:25.262811 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo1-probed RESULT=pass
11410 23:08:25.265574 /lava-12395373/1/../bin/lava-test-case
11411 23:08:25.276586 <8>[ 30.876731] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass>
11412 23:08:25.276837 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass
11414 23:08:25.280062 /lava-12395373/1/../bin/lava-test-case
11415 23:08:25.292729 <8>[ 30.889372] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-probed RESULT=pass>
11416 23:08:25.292980 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-probed RESULT=pass
11418 23:08:25.295801 /lava-12395373/1/../bin/lava-test-case
11419 23:08:25.302510 <8>[ 30.904874] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-driver-present RESULT=pass>
11420 23:08:25.302798 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-driver-present RESULT=pass
11422 23:08:26.307738 /lava-12395373/1/../bin/lava-test-case
11423 23:08:26.314401 <8>[ 31.915323] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-probed RESULT=fail>
11424 23:08:26.315076 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-probed RESULT=fail
11426 23:08:26.318066 /lava-12395373/1/../bin/lava-test-case
11427 23:08:26.329111 <8>[ 31.928743] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-driver-present RESULT=pass>
11428 23:08:26.329788 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-driver-present RESULT=pass
11430 23:08:27.332028 /lava-12395373/1/../bin/lava-test-case
11431 23:08:27.339015 <8>[ 32.940477] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-probed RESULT=fail>
11432 23:08:27.339334 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-probed RESULT=fail
11434 23:08:27.342255 /lava-12395373/1/../bin/lava-test-case
11435 23:08:27.352372 <8>[ 32.952885] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-driver-present RESULT=pass>
11436 23:08:27.352634 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-driver-present RESULT=pass
11438 23:08:28.356535 /lava-12395373/1/../bin/lava-test-case
11439 23:08:28.363287 <8>[ 33.964599] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-probed RESULT=fail>
11440 23:08:28.363666 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-probed RESULT=fail
11442 23:08:28.365993 /lava-12395373/1/../bin/lava-test-case
11443 23:08:28.376389 <8>[ 33.976149] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass>
11444 23:08:28.376691 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass
11446 23:08:29.380169 /lava-12395373/1/../bin/lava-test-case
11447 23:08:29.392343 <8>[ 34.989742] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail>
11448 23:08:29.393022 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail
11450 23:08:29.395965 /lava-12395373/1/../bin/lava-test-case
11451 23:08:29.402402 <8>[ 35.004097] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb-driver-present RESULT=pass>
11452 23:08:29.403179 Received signal: <TESTCASE> TEST_CASE_ID=btusb-driver-present RESULT=pass
11454 23:08:29.405972 /lava-12395373/1/../bin/lava-test-case
11455 23:08:29.416396 <8>[ 35.017019] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb0-probed RESULT=pass>
11456 23:08:29.417096 Received signal: <TESTCASE> TEST_CASE_ID=btusb0-probed RESULT=pass
11458 23:08:29.419599 /lava-12395373/1/../bin/lava-test-case
11459 23:08:29.426263 <8>[ 35.027450] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb1-probed RESULT=pass>
11460 23:08:29.426947 Received signal: <TESTCASE> TEST_CASE_ID=btusb1-probed RESULT=pass
11462 23:08:29.430140 /lava-12395373/1/../bin/lava-test-case
11463 23:08:29.440229 <8>[ 35.040236] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass>
11464 23:08:29.440937 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass
11466 23:08:29.443839 /lava-12395373/1/../bin/lava-test-case
11467 23:08:29.456289 <8>[ 35.053834] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-probed RESULT=pass>
11468 23:08:29.456976 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-probed RESULT=pass
11470 23:08:29.459617 /lava-12395373/1/../bin/lava-test-case
11471 23:08:29.469847 <8>[ 35.069364] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass>
11472 23:08:29.470546 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass
11474 23:08:29.473135 /lava-12395373/1/../bin/lava-test-case
11475 23:08:29.484531 <8>[ 35.081579] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-probed RESULT=pass>
11476 23:08:29.485226 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-probed RESULT=pass
11478 23:08:29.487840 /lava-12395373/1/../bin/lava-test-case
11479 23:08:29.498280 <8>[ 35.096350] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass>
11480 23:08:29.498989 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass
11482 23:08:29.501027 /lava-12395373/1/../bin/lava-test-case
11483 23:08:29.504600 + set +x
11484 23:08:29.511249 <LAVA_TEST_RUNNE<8>[ 35.109751] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=pass>
11485 23:08:29.512074 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=pass
11487 23:08:29.514699 R EXIT>
11488 23:08:29.520950 / # <8>[ 35.111952] <LAVA_SIGNAL_ENDRUN 1_bootrr 12395373_1.5.2.3.5>
11489 23:08:29.521615 Received signal: <ENDRUN> 1_bootrr 12395373_1.5.2.3.5
11490 23:08:29.522018 Ending use of test pattern.
11491 23:08:29.522335 Ending test lava.1_bootrr (12395373_1.5.2.3.5), duration 19.47
11493 23:08:38.428533 <6>[ 44.034072] vpu: disabling
11494 23:08:38.431736 <6>[ 44.034204] vproc2: disabling
11495 23:08:38.434919 <6>[ 44.034260] vproc1: disabling
11496 23:08:38.438026 <6>[ 44.034316] vaud18: disabling
11497 23:08:38.441556 <6>[ 44.034570] vsram_others: disabling
11498 23:08:38.444778 <6>[ 44.034753] va09: disabling
11499 23:08:38.448395 <6>[ 44.034836] vsram_md: disabling
11500 23:08:38.451140 <6>[ 44.034968] Vgpu: disabling
11502 23:09:09.614558 end: 4.1 lava-test-shell (duration 00:01:00) [common]
11504 23:09:09.614850 lava-test-retry failed: 1 of 5 attempts. 'lava-test-shell timed out after 60 seconds'
11506 23:09:09.615058 end: 4 lava-test-retry (duration 00:01:00) [common]
11508 23:09:09.615407 Cleaning after the job
11509 23:09:09.615526 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12395373/tftp-deploy-dxcbkafh/ramdisk
11510 23:09:09.618569 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12395373/tftp-deploy-dxcbkafh/kernel
11511 23:09:09.631543 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12395373/tftp-deploy-dxcbkafh/dtb
11512 23:09:09.631768 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12395373/tftp-deploy-dxcbkafh/modules
11513 23:09:09.638838 start: 5.1 power-off (timeout 00:00:30) [common]
11514 23:09:09.639008 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-2' '--port=1' '--command=off'
11515 23:09:09.709368 >> Command sent successfully.
11516 23:09:09.711927 Returned 0 in 0 seconds
11517 23:09:09.812347 end: 5.1 power-off (duration 00:00:00) [common]
11519 23:09:09.812685 start: 5.2 read-feedback (timeout 00:10:00) [common]
11520 23:09:09.812953 Listened to connection for namespace 'common' for up to 1s
11521 23:09:10.813907 Finalising connection for namespace 'common'
11522 23:09:10.814086 Disconnecting from shell: Finalise
11523 23:09:10.914493 end: 5.2 read-feedback (duration 00:00:01) [common]
11524 23:09:10.914650 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12395373
11525 23:09:10.961691 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12395373
11526 23:09:10.961886 TestError: A test failed to run, look at the error message.