Boot log: mt8192-asurada-spherion-r0
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 14
- Kernel Errors: 38
- Errors: 1
1 23:06:02.273989 lava-dispatcher, installed at version: 2023.10
2 23:06:02.274206 start: 0 validate
3 23:06:02.274339 Start time: 2023-12-27 23:06:02.274331+00:00 (UTC)
4 23:06:02.274456 Using caching service: 'http://localhost/cache/?uri=%s'
5 23:06:02.274588 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230623.0%2Farm64%2Finitrd.cpio.gz exists
6 23:06:02.534711 Using caching service: 'http://localhost/cache/?uri=%s'
7 23:06:02.534888 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.66-cip11-rt6-10-g38253b8903b4%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 23:06:02.803008 Using caching service: 'http://localhost/cache/?uri=%s'
9 23:06:02.803707 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.66-cip11-rt6-10-g38253b8903b4%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 23:06:30.567548 Using caching service: 'http://localhost/cache/?uri=%s'
11 23:06:30.568283 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230623.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 23:06:31.081947 Using caching service: 'http://localhost/cache/?uri=%s'
13 23:06:31.082699 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.66-cip11-rt6-10-g38253b8903b4%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 23:06:38.588939 validate duration: 36.31
16 23:06:38.589193 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 23:06:38.589291 start: 1.1 download-retry (timeout 00:10:00) [common]
18 23:06:38.589393 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 23:06:38.589554 Not decompressing ramdisk as can be used compressed.
20 23:06:38.589637 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230623.0/arm64/initrd.cpio.gz
21 23:06:38.589701 saving as /var/lib/lava/dispatcher/tmp/12395343/tftp-deploy-8402ppx3/ramdisk/initrd.cpio.gz
22 23:06:38.589763 total size: 4665412 (4 MB)
23 23:06:38.847720 progress 0 % (0 MB)
24 23:06:38.850978 progress 5 % (0 MB)
25 23:06:38.852302 progress 10 % (0 MB)
26 23:06:38.853628 progress 15 % (0 MB)
27 23:06:38.854875 progress 20 % (0 MB)
28 23:06:38.856108 progress 25 % (1 MB)
29 23:06:38.857345 progress 30 % (1 MB)
30 23:06:38.858616 progress 35 % (1 MB)
31 23:06:38.859890 progress 40 % (1 MB)
32 23:06:38.861279 progress 45 % (2 MB)
33 23:06:38.862508 progress 50 % (2 MB)
34 23:06:38.863747 progress 55 % (2 MB)
35 23:06:38.865024 progress 60 % (2 MB)
36 23:06:38.866294 progress 65 % (2 MB)
37 23:06:38.867558 progress 70 % (3 MB)
38 23:06:38.868884 progress 75 % (3 MB)
39 23:06:38.870152 progress 80 % (3 MB)
40 23:06:38.871589 progress 85 % (3 MB)
41 23:06:38.872896 progress 90 % (4 MB)
42 23:06:38.874136 progress 95 % (4 MB)
43 23:06:38.875452 progress 100 % (4 MB)
44 23:06:38.875642 4 MB downloaded in 0.29 s (15.56 MB/s)
45 23:06:38.875837 end: 1.1.1 http-download (duration 00:00:00) [common]
47 23:06:38.876081 end: 1.1 download-retry (duration 00:00:00) [common]
48 23:06:38.876228 start: 1.2 download-retry (timeout 00:10:00) [common]
49 23:06:38.876376 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 23:06:38.876511 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.66-cip11-rt6-10-g38253b8903b4/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 23:06:38.876580 saving as /var/lib/lava/dispatcher/tmp/12395343/tftp-deploy-8402ppx3/kernel/Image
52 23:06:38.876642 total size: 50024960 (47 MB)
53 23:06:38.876703 No compression specified
54 23:06:38.877907 progress 0 % (0 MB)
55 23:06:38.891330 progress 5 % (2 MB)
56 23:06:38.904366 progress 10 % (4 MB)
57 23:06:38.917429 progress 15 % (7 MB)
58 23:06:38.930639 progress 20 % (9 MB)
59 23:06:38.943601 progress 25 % (11 MB)
60 23:06:38.956504 progress 30 % (14 MB)
61 23:06:38.969630 progress 35 % (16 MB)
62 23:06:38.982690 progress 40 % (19 MB)
63 23:06:38.995756 progress 45 % (21 MB)
64 23:06:39.008759 progress 50 % (23 MB)
65 23:06:39.021737 progress 55 % (26 MB)
66 23:06:39.034954 progress 60 % (28 MB)
67 23:06:39.048074 progress 65 % (31 MB)
68 23:06:39.060953 progress 70 % (33 MB)
69 23:06:39.073728 progress 75 % (35 MB)
70 23:06:39.086695 progress 80 % (38 MB)
71 23:06:39.099549 progress 85 % (40 MB)
72 23:06:39.112461 progress 90 % (42 MB)
73 23:06:39.125441 progress 95 % (45 MB)
74 23:06:39.138313 progress 100 % (47 MB)
75 23:06:39.138550 47 MB downloaded in 0.26 s (182.16 MB/s)
76 23:06:39.138761 end: 1.2.1 http-download (duration 00:00:00) [common]
78 23:06:39.138998 end: 1.2 download-retry (duration 00:00:00) [common]
79 23:06:39.139085 start: 1.3 download-retry (timeout 00:09:59) [common]
80 23:06:39.139174 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 23:06:39.139311 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.66-cip11-rt6-10-g38253b8903b4/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 23:06:39.139382 saving as /var/lib/lava/dispatcher/tmp/12395343/tftp-deploy-8402ppx3/dtb/mt8192-asurada-spherion-r0.dtb
83 23:06:39.139460 total size: 47278 (0 MB)
84 23:06:39.139523 No compression specified
85 23:06:39.140708 progress 69 % (0 MB)
86 23:06:39.140985 progress 100 % (0 MB)
87 23:06:39.141143 0 MB downloaded in 0.00 s (26.84 MB/s)
88 23:06:39.141265 end: 1.3.1 http-download (duration 00:00:00) [common]
90 23:06:39.141525 end: 1.3 download-retry (duration 00:00:00) [common]
91 23:06:39.141627 start: 1.4 download-retry (timeout 00:09:59) [common]
92 23:06:39.141713 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 23:06:39.141826 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230623.0/arm64/full.rootfs.tar.xz
94 23:06:39.141894 saving as /var/lib/lava/dispatcher/tmp/12395343/tftp-deploy-8402ppx3/nfsrootfs/full.rootfs.tar
95 23:06:39.141956 total size: 125290964 (119 MB)
96 23:06:39.142018 Using unxz to decompress xz
97 23:06:39.146162 progress 0 % (0 MB)
98 23:06:39.477133 progress 5 % (6 MB)
99 23:06:39.821848 progress 10 % (11 MB)
100 23:06:40.150778 progress 15 % (17 MB)
101 23:06:40.333845 progress 20 % (23 MB)
102 23:06:40.515264 progress 25 % (29 MB)
103 23:06:40.862066 progress 30 % (35 MB)
104 23:06:41.218921 progress 35 % (41 MB)
105 23:06:41.608208 progress 40 % (47 MB)
106 23:06:41.987643 progress 45 % (53 MB)
107 23:06:42.373096 progress 50 % (59 MB)
108 23:06:42.721516 progress 55 % (65 MB)
109 23:06:43.081249 progress 60 % (71 MB)
110 23:06:43.416735 progress 65 % (77 MB)
111 23:06:43.778707 progress 70 % (83 MB)
112 23:06:44.155324 progress 75 % (89 MB)
113 23:06:44.571537 progress 80 % (95 MB)
114 23:06:44.988226 progress 85 % (101 MB)
115 23:06:45.230601 progress 90 % (107 MB)
116 23:06:45.573435 progress 95 % (113 MB)
117 23:06:45.940248 progress 100 % (119 MB)
118 23:06:45.945981 119 MB downloaded in 6.80 s (17.56 MB/s)
119 23:06:45.946248 end: 1.4.1 http-download (duration 00:00:07) [common]
121 23:06:45.946512 end: 1.4 download-retry (duration 00:00:07) [common]
122 23:06:45.946604 start: 1.5 download-retry (timeout 00:09:53) [common]
123 23:06:45.946740 start: 1.5.1 http-download (timeout 00:09:53) [common]
124 23:06:45.946904 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.66-cip11-rt6-10-g38253b8903b4/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 23:06:45.946976 saving as /var/lib/lava/dispatcher/tmp/12395343/tftp-deploy-8402ppx3/modules/modules.tar
126 23:06:45.947037 total size: 8633892 (8 MB)
127 23:06:45.947102 Using unxz to decompress xz
128 23:06:46.216017 progress 0 % (0 MB)
129 23:06:46.236792 progress 5 % (0 MB)
130 23:06:46.260467 progress 10 % (0 MB)
131 23:06:46.283851 progress 15 % (1 MB)
132 23:06:46.306813 progress 20 % (1 MB)
133 23:06:46.330808 progress 25 % (2 MB)
134 23:06:46.358629 progress 30 % (2 MB)
135 23:06:46.382891 progress 35 % (2 MB)
136 23:06:46.406058 progress 40 % (3 MB)
137 23:06:46.429986 progress 45 % (3 MB)
138 23:06:46.455143 progress 50 % (4 MB)
139 23:06:46.479559 progress 55 % (4 MB)
140 23:06:46.506118 progress 60 % (4 MB)
141 23:06:46.531393 progress 65 % (5 MB)
142 23:06:46.556270 progress 70 % (5 MB)
143 23:06:46.579718 progress 75 % (6 MB)
144 23:06:46.606983 progress 80 % (6 MB)
145 23:06:46.632500 progress 85 % (7 MB)
146 23:06:46.659260 progress 90 % (7 MB)
147 23:06:46.688840 progress 95 % (7 MB)
148 23:06:46.716535 progress 100 % (8 MB)
149 23:06:46.722094 8 MB downloaded in 0.78 s (10.62 MB/s)
150 23:06:46.722338 end: 1.5.1 http-download (duration 00:00:01) [common]
152 23:06:46.722604 end: 1.5 download-retry (duration 00:00:01) [common]
153 23:06:46.722696 start: 1.6 prepare-tftp-overlay (timeout 00:09:52) [common]
154 23:06:46.722794 start: 1.6.1 extract-nfsrootfs (timeout 00:09:52) [common]
155 23:06:48.870501 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/12395343/extract-nfsrootfs-kd_xsd9a
156 23:06:48.870701 end: 1.6.1 extract-nfsrootfs (duration 00:00:02) [common]
157 23:06:48.870803 start: 1.6.2 lava-overlay (timeout 00:09:50) [common]
158 23:06:48.870970 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12395343/lava-overlay-bdxy3yps
159 23:06:48.871102 makedir: /var/lib/lava/dispatcher/tmp/12395343/lava-overlay-bdxy3yps/lava-12395343/bin
160 23:06:48.871205 makedir: /var/lib/lava/dispatcher/tmp/12395343/lava-overlay-bdxy3yps/lava-12395343/tests
161 23:06:48.871304 makedir: /var/lib/lava/dispatcher/tmp/12395343/lava-overlay-bdxy3yps/lava-12395343/results
162 23:06:48.871408 Creating /var/lib/lava/dispatcher/tmp/12395343/lava-overlay-bdxy3yps/lava-12395343/bin/lava-add-keys
163 23:06:48.871559 Creating /var/lib/lava/dispatcher/tmp/12395343/lava-overlay-bdxy3yps/lava-12395343/bin/lava-add-sources
164 23:06:48.871689 Creating /var/lib/lava/dispatcher/tmp/12395343/lava-overlay-bdxy3yps/lava-12395343/bin/lava-background-process-start
165 23:06:48.871822 Creating /var/lib/lava/dispatcher/tmp/12395343/lava-overlay-bdxy3yps/lava-12395343/bin/lava-background-process-stop
166 23:06:48.871948 Creating /var/lib/lava/dispatcher/tmp/12395343/lava-overlay-bdxy3yps/lava-12395343/bin/lava-common-functions
167 23:06:48.872073 Creating /var/lib/lava/dispatcher/tmp/12395343/lava-overlay-bdxy3yps/lava-12395343/bin/lava-echo-ipv4
168 23:06:48.872201 Creating /var/lib/lava/dispatcher/tmp/12395343/lava-overlay-bdxy3yps/lava-12395343/bin/lava-install-packages
169 23:06:48.872332 Creating /var/lib/lava/dispatcher/tmp/12395343/lava-overlay-bdxy3yps/lava-12395343/bin/lava-installed-packages
170 23:06:48.872457 Creating /var/lib/lava/dispatcher/tmp/12395343/lava-overlay-bdxy3yps/lava-12395343/bin/lava-os-build
171 23:06:48.872586 Creating /var/lib/lava/dispatcher/tmp/12395343/lava-overlay-bdxy3yps/lava-12395343/bin/lava-probe-channel
172 23:06:48.872714 Creating /var/lib/lava/dispatcher/tmp/12395343/lava-overlay-bdxy3yps/lava-12395343/bin/lava-probe-ip
173 23:06:48.872847 Creating /var/lib/lava/dispatcher/tmp/12395343/lava-overlay-bdxy3yps/lava-12395343/bin/lava-target-ip
174 23:06:48.872971 Creating /var/lib/lava/dispatcher/tmp/12395343/lava-overlay-bdxy3yps/lava-12395343/bin/lava-target-mac
175 23:06:48.873096 Creating /var/lib/lava/dispatcher/tmp/12395343/lava-overlay-bdxy3yps/lava-12395343/bin/lava-target-storage
176 23:06:48.873222 Creating /var/lib/lava/dispatcher/tmp/12395343/lava-overlay-bdxy3yps/lava-12395343/bin/lava-test-case
177 23:06:48.873350 Creating /var/lib/lava/dispatcher/tmp/12395343/lava-overlay-bdxy3yps/lava-12395343/bin/lava-test-event
178 23:06:48.873481 Creating /var/lib/lava/dispatcher/tmp/12395343/lava-overlay-bdxy3yps/lava-12395343/bin/lava-test-feedback
179 23:06:48.873614 Creating /var/lib/lava/dispatcher/tmp/12395343/lava-overlay-bdxy3yps/lava-12395343/bin/lava-test-raise
180 23:06:48.873754 Creating /var/lib/lava/dispatcher/tmp/12395343/lava-overlay-bdxy3yps/lava-12395343/bin/lava-test-reference
181 23:06:48.873905 Creating /var/lib/lava/dispatcher/tmp/12395343/lava-overlay-bdxy3yps/lava-12395343/bin/lava-test-runner
182 23:06:48.874062 Creating /var/lib/lava/dispatcher/tmp/12395343/lava-overlay-bdxy3yps/lava-12395343/bin/lava-test-set
183 23:06:48.874220 Creating /var/lib/lava/dispatcher/tmp/12395343/lava-overlay-bdxy3yps/lava-12395343/bin/lava-test-shell
184 23:06:48.874381 Updating /var/lib/lava/dispatcher/tmp/12395343/lava-overlay-bdxy3yps/lava-12395343/bin/lava-install-packages (oe)
185 23:06:48.874556 Updating /var/lib/lava/dispatcher/tmp/12395343/lava-overlay-bdxy3yps/lava-12395343/bin/lava-installed-packages (oe)
186 23:06:48.874703 Creating /var/lib/lava/dispatcher/tmp/12395343/lava-overlay-bdxy3yps/lava-12395343/environment
187 23:06:48.874828 LAVA metadata
188 23:06:48.874928 - LAVA_JOB_ID=12395343
189 23:06:48.875021 - LAVA_DISPATCHER_IP=192.168.201.1
190 23:06:48.875150 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:50) [common]
191 23:06:48.875218 skipped lava-vland-overlay
192 23:06:48.875293 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
193 23:06:48.875413 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:50) [common]
194 23:06:48.875506 skipped lava-multinode-overlay
195 23:06:48.875611 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
196 23:06:48.875725 start: 1.6.2.3 test-definition (timeout 00:09:50) [common]
197 23:06:48.875840 Loading test definitions
198 23:06:48.875965 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:50) [common]
199 23:06:48.876067 Using /lava-12395343 at stage 0
200 23:06:48.876494 uuid=12395343_1.6.2.3.1 testdef=None
201 23:06:48.876614 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
202 23:06:48.876735 start: 1.6.2.3.2 test-overlay (timeout 00:09:50) [common]
203 23:06:48.877442 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
205 23:06:48.877726 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:50) [common]
206 23:06:48.878379 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
208 23:06:48.878612 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:50) [common]
209 23:06:48.879234 runner path: /var/lib/lava/dispatcher/tmp/12395343/lava-overlay-bdxy3yps/lava-12395343/0/tests/0_dmesg test_uuid 12395343_1.6.2.3.1
210 23:06:48.879389 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
212 23:06:48.879617 start: 1.6.2.3.5 inline-repo-action (timeout 00:09:50) [common]
213 23:06:48.879689 Using /lava-12395343 at stage 1
214 23:06:48.879995 uuid=12395343_1.6.2.3.5 testdef=None
215 23:06:48.880083 end: 1.6.2.3.5 inline-repo-action (duration 00:00:00) [common]
216 23:06:48.880168 start: 1.6.2.3.6 test-overlay (timeout 00:09:50) [common]
217 23:06:48.880673 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
219 23:06:48.880891 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:50) [common]
220 23:06:48.881647 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
222 23:06:48.881878 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:50) [common]
223 23:06:48.882505 runner path: /var/lib/lava/dispatcher/tmp/12395343/lava-overlay-bdxy3yps/lava-12395343/1/tests/1_bootrr test_uuid 12395343_1.6.2.3.5
224 23:06:48.882658 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
226 23:06:48.882864 Creating lava-test-runner.conf files
227 23:06:48.882929 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12395343/lava-overlay-bdxy3yps/lava-12395343/0 for stage 0
228 23:06:48.883024 - 0_dmesg
229 23:06:48.883103 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12395343/lava-overlay-bdxy3yps/lava-12395343/1 for stage 1
230 23:06:48.883194 - 1_bootrr
231 23:06:48.883288 end: 1.6.2.3 test-definition (duration 00:00:00) [common]
232 23:06:48.883373 start: 1.6.2.4 compress-overlay (timeout 00:09:50) [common]
233 23:06:48.890732 end: 1.6.2.4 compress-overlay (duration 00:00:00) [common]
234 23:06:48.890833 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:50) [common]
235 23:06:48.890918 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
236 23:06:48.891002 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
237 23:06:48.891086 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:50) [common]
238 23:06:49.012244 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
239 23:06:49.012639 start: 1.6.4 extract-modules (timeout 00:09:50) [common]
240 23:06:49.012758 extracting modules file /var/lib/lava/dispatcher/tmp/12395343/tftp-deploy-8402ppx3/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12395343/extract-nfsrootfs-kd_xsd9a
241 23:06:49.241903 extracting modules file /var/lib/lava/dispatcher/tmp/12395343/tftp-deploy-8402ppx3/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12395343/extract-overlay-ramdisk-lhqwmkjk/ramdisk
242 23:06:49.466744 end: 1.6.4 extract-modules (duration 00:00:00) [common]
243 23:06:49.466917 start: 1.6.5 apply-overlay-tftp (timeout 00:09:49) [common]
244 23:06:49.467017 [common] Applying overlay to NFS
245 23:06:49.467090 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12395343/compress-overlay-lihcuo09/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12395343/extract-nfsrootfs-kd_xsd9a
246 23:06:49.475282 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
247 23:06:49.475393 start: 1.6.6 configure-preseed-file (timeout 00:09:49) [common]
248 23:06:49.475481 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
249 23:06:49.475569 start: 1.6.7 compress-ramdisk (timeout 00:09:49) [common]
250 23:06:49.475647 Building ramdisk /var/lib/lava/dispatcher/tmp/12395343/extract-overlay-ramdisk-lhqwmkjk/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12395343/extract-overlay-ramdisk-lhqwmkjk/ramdisk
251 23:06:49.811641 >> 119421 blocks
252 23:06:51.726314 rename /var/lib/lava/dispatcher/tmp/12395343/extract-overlay-ramdisk-lhqwmkjk/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12395343/tftp-deploy-8402ppx3/ramdisk/ramdisk.cpio.gz
253 23:06:51.726776 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
254 23:06:51.726899 start: 1.6.8 prepare-kernel (timeout 00:09:47) [common]
255 23:06:51.727006 start: 1.6.8.1 prepare-fit (timeout 00:09:47) [common]
256 23:06:51.727112 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12395343/tftp-deploy-8402ppx3/kernel/Image'
257 23:07:04.432257 Returned 0 in 12 seconds
258 23:07:04.532897 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12395343/tftp-deploy-8402ppx3/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12395343/tftp-deploy-8402ppx3/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12395343/tftp-deploy-8402ppx3/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12395343/tftp-deploy-8402ppx3/kernel/image.itb
259 23:07:04.898843 output: FIT description: Kernel Image image with one or more FDT blobs
260 23:07:04.899241 output: Created: Wed Dec 27 23:07:04 2023
261 23:07:04.899316 output: Image 0 (kernel-1)
262 23:07:04.899381 output: Description:
263 23:07:04.899443 output: Created: Wed Dec 27 23:07:04 2023
264 23:07:04.899503 output: Type: Kernel Image
265 23:07:04.899563 output: Compression: lzma compressed
266 23:07:04.899620 output: Data Size: 11480388 Bytes = 11211.32 KiB = 10.95 MiB
267 23:07:04.899680 output: Architecture: AArch64
268 23:07:04.899735 output: OS: Linux
269 23:07:04.899791 output: Load Address: 0x00000000
270 23:07:04.899850 output: Entry Point: 0x00000000
271 23:07:04.899908 output: Hash algo: crc32
272 23:07:04.899967 output: Hash value: a55b2f0b
273 23:07:04.900025 output: Image 1 (fdt-1)
274 23:07:04.900080 output: Description: mt8192-asurada-spherion-r0
275 23:07:04.900134 output: Created: Wed Dec 27 23:07:04 2023
276 23:07:04.900188 output: Type: Flat Device Tree
277 23:07:04.900242 output: Compression: uncompressed
278 23:07:04.900295 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
279 23:07:04.900348 output: Architecture: AArch64
280 23:07:04.900401 output: Hash algo: crc32
281 23:07:04.900453 output: Hash value: cc4352de
282 23:07:04.900507 output: Image 2 (ramdisk-1)
283 23:07:04.900560 output: Description: unavailable
284 23:07:04.900613 output: Created: Wed Dec 27 23:07:04 2023
285 23:07:04.900666 output: Type: RAMDisk Image
286 23:07:04.900719 output: Compression: Unknown Compression
287 23:07:04.900771 output: Data Size: 17797497 Bytes = 17380.37 KiB = 16.97 MiB
288 23:07:04.900825 output: Architecture: AArch64
289 23:07:04.900877 output: OS: Linux
290 23:07:04.900930 output: Load Address: unavailable
291 23:07:04.900982 output: Entry Point: unavailable
292 23:07:04.901034 output: Hash algo: crc32
293 23:07:04.901087 output: Hash value: 8940d885
294 23:07:04.901139 output: Default Configuration: 'conf-1'
295 23:07:04.901191 output: Configuration 0 (conf-1)
296 23:07:04.901244 output: Description: mt8192-asurada-spherion-r0
297 23:07:04.901297 output: Kernel: kernel-1
298 23:07:04.901350 output: Init Ramdisk: ramdisk-1
299 23:07:04.901402 output: FDT: fdt-1
300 23:07:04.901455 output: Loadables: kernel-1
301 23:07:04.901552 output:
302 23:07:04.901759 end: 1.6.8.1 prepare-fit (duration 00:00:13) [common]
303 23:07:04.901859 end: 1.6.8 prepare-kernel (duration 00:00:13) [common]
304 23:07:04.901962 end: 1.6 prepare-tftp-overlay (duration 00:00:18) [common]
305 23:07:04.902058 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:34) [common]
306 23:07:04.902136 No LXC device requested
307 23:07:04.902214 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
308 23:07:04.902297 start: 1.8 deploy-device-env (timeout 00:09:34) [common]
309 23:07:04.902375 end: 1.8 deploy-device-env (duration 00:00:00) [common]
310 23:07:04.902443 Checking files for TFTP limit of 4294967296 bytes.
311 23:07:04.902943 end: 1 tftp-deploy (duration 00:00:26) [common]
312 23:07:04.903046 start: 2 depthcharge-action (timeout 00:05:00) [common]
313 23:07:04.903138 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
314 23:07:04.903268 substitutions:
315 23:07:04.903335 - {DTB}: 12395343/tftp-deploy-8402ppx3/dtb/mt8192-asurada-spherion-r0.dtb
316 23:07:04.903400 - {INITRD}: 12395343/tftp-deploy-8402ppx3/ramdisk/ramdisk.cpio.gz
317 23:07:04.903459 - {KERNEL}: 12395343/tftp-deploy-8402ppx3/kernel/Image
318 23:07:04.903516 - {LAVA_MAC}: None
319 23:07:04.903573 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/12395343/extract-nfsrootfs-kd_xsd9a
320 23:07:04.903628 - {NFS_SERVER_IP}: 192.168.201.1
321 23:07:04.903683 - {PRESEED_CONFIG}: None
322 23:07:04.903737 - {PRESEED_LOCAL}: None
323 23:07:04.903791 - {RAMDISK}: 12395343/tftp-deploy-8402ppx3/ramdisk/ramdisk.cpio.gz
324 23:07:04.903846 - {ROOT_PART}: None
325 23:07:04.903901 - {ROOT}: None
326 23:07:04.903956 - {SERVER_IP}: 192.168.201.1
327 23:07:04.904010 - {TEE}: None
328 23:07:04.904064 Parsed boot commands:
329 23:07:04.904119 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
330 23:07:04.904303 Parsed boot commands: tftpboot 192.168.201.1 12395343/tftp-deploy-8402ppx3/kernel/image.itb 12395343/tftp-deploy-8402ppx3/kernel/cmdline
331 23:07:04.904392 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
332 23:07:04.904477 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
333 23:07:04.904569 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
334 23:07:04.904655 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
335 23:07:04.904727 Not connected, no need to disconnect.
336 23:07:04.904803 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
337 23:07:04.904885 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
338 23:07:04.904950 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-8'
339 23:07:04.909005 Setting prompt string to ['lava-test: # ']
340 23:07:04.909385 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
341 23:07:04.909532 end: 2.2.1 reset-connection (duration 00:00:00) [common]
342 23:07:04.909634 start: 2.2.2 reset-device (timeout 00:05:00) [common]
343 23:07:04.909726 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
344 23:07:04.909961 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=reboot'
345 23:07:10.054391 >> Command sent successfully.
346 23:07:10.065322 Returned 0 in 5 seconds
347 23:07:10.166735 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
349 23:07:10.168350 end: 2.2.2 reset-device (duration 00:00:05) [common]
350 23:07:10.168947 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
351 23:07:10.169450 Setting prompt string to 'Starting depthcharge on Spherion...'
352 23:07:10.169899 Changing prompt to 'Starting depthcharge on Spherion...'
353 23:07:10.170362 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
354 23:07:10.171767 [Enter `^Ec?' for help]
355 23:07:10.337169
356 23:07:10.337750
357 23:07:10.338119 F0: 102B 0000
358 23:07:10.338468
359 23:07:10.338788 F3: 1001 0000 [0200]
360 23:07:10.341176
361 23:07:10.341744 F3: 1001 0000
362 23:07:10.342091
363 23:07:10.342405 F7: 102D 0000
364 23:07:10.342710
365 23:07:10.344389 F1: 0000 0000
366 23:07:10.344915
367 23:07:10.345254 V0: 0000 0000 [0001]
368 23:07:10.345637
369 23:07:10.347515 00: 0007 8000
370 23:07:10.348062
371 23:07:10.348405 01: 0000 0000
372 23:07:10.348731
373 23:07:10.350563 BP: 0C00 0209 [0000]
374 23:07:10.350994
375 23:07:10.351334 G0: 1182 0000
376 23:07:10.351651
377 23:07:10.354276 EC: 0000 0021 [4000]
378 23:07:10.354702
379 23:07:10.355042 S7: 0000 0000 [0000]
380 23:07:10.355358
381 23:07:10.357815 CC: 0000 0000 [0001]
382 23:07:10.358244
383 23:07:10.358582 T0: 0000 0040 [010F]
384 23:07:10.358898
385 23:07:10.359201 Jump to BL
386 23:07:10.359514
387 23:07:10.383937
388 23:07:10.384498
389 23:07:10.384844
390 23:07:10.390849 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
391 23:07:10.394407 ARM64: Exception handlers installed.
392 23:07:10.398195 ARM64: Testing exception
393 23:07:10.401724 ARM64: Done test exception
394 23:07:10.408701 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
395 23:07:10.419251 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
396 23:07:10.425439 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
397 23:07:10.435347 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
398 23:07:10.442408 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
399 23:07:10.452581 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
400 23:07:10.463237 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
401 23:07:10.469730 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
402 23:07:10.487745 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
403 23:07:10.490702 WDT: Last reset was cold boot
404 23:07:10.494084 SPI1(PAD0) initialized at 2873684 Hz
405 23:07:10.497437 SPI5(PAD0) initialized at 992727 Hz
406 23:07:10.500778 VBOOT: Loading verstage.
407 23:07:10.507386 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
408 23:07:10.510302 FMAP: Found "FLASH" version 1.1 at 0x20000.
409 23:07:10.513939 FMAP: base = 0x0 size = 0x800000 #areas = 25
410 23:07:10.517070 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
411 23:07:10.524489 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
412 23:07:10.531651 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
413 23:07:10.542563 read SPI 0x96554 0xa1eb: 4594 us, 9022 KB/s, 72.176 Mbps
414 23:07:10.543130
415 23:07:10.543511
416 23:07:10.552559 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
417 23:07:10.555770 ARM64: Exception handlers installed.
418 23:07:10.559202 ARM64: Testing exception
419 23:07:10.559776 ARM64: Done test exception
420 23:07:10.566061 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
421 23:07:10.569364 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 23:07:10.583188 Probing TPM: . done!
423 23:07:10.583761 TPM ready after 0 ms
424 23:07:10.590227 Connected to device vid:did:rid of 1ae0:0028:00
425 23:07:10.597136 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
426 23:07:10.637823 Initialized TPM device CR50 revision 0
427 23:07:10.648943 tlcl_send_startup: Startup return code is 0
428 23:07:10.649592 TPM: setup succeeded
429 23:07:10.660453 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
430 23:07:10.669249 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
431 23:07:10.681639 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
432 23:07:10.690240 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
433 23:07:10.693313 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
434 23:07:10.697630 in-header: 03 07 00 00 08 00 00 00
435 23:07:10.701405 in-data: aa e4 47 04 13 02 00 00
436 23:07:10.704669 Chrome EC: UHEPI supported
437 23:07:10.711737 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
438 23:07:10.715629 in-header: 03 9d 00 00 08 00 00 00
439 23:07:10.719424 in-data: 10 20 20 08 00 00 00 00
440 23:07:10.720080 Phase 1
441 23:07:10.722955 FMAP: area GBB found @ 3f5000 (12032 bytes)
442 23:07:10.730236 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
443 23:07:10.737405 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
444 23:07:10.737952 Recovery requested (1009000e)
445 23:07:10.746683 TPM: Extending digest for VBOOT: boot mode into PCR 0
446 23:07:10.752023 tlcl_extend: response is 0
447 23:07:10.759963 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
448 23:07:10.765245 tlcl_extend: response is 0
449 23:07:10.771878 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
450 23:07:10.792935 read SPI 0x210d4 0x2173b: 15145 us, 9047 KB/s, 72.376 Mbps
451 23:07:10.799977 BS: bootblock times (exec / console): total (unknown) / 149 ms
452 23:07:10.800441
453 23:07:10.800970
454 23:07:10.811323 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
455 23:07:10.811863 ARM64: Exception handlers installed.
456 23:07:10.815185 ARM64: Testing exception
457 23:07:10.818209 ARM64: Done test exception
458 23:07:10.838356 pmic_efuse_setting: Set efuses in 11 msecs
459 23:07:10.842511 pmwrap_interface_init: Select PMIF_VLD_RDY
460 23:07:10.846064 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
461 23:07:10.853322 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
462 23:07:10.856878 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
463 23:07:10.860529 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
464 23:07:10.868036 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
465 23:07:10.872139 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
466 23:07:10.875951 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
467 23:07:10.879384 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
468 23:07:10.886683 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
469 23:07:10.889353 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
470 23:07:10.896229 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
471 23:07:10.899612 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
472 23:07:10.902380 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
473 23:07:10.909664 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
474 23:07:10.916106 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
475 23:07:10.922737 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
476 23:07:10.926201 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
477 23:07:10.933067 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
478 23:07:10.939839 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
479 23:07:10.943737 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
480 23:07:10.951056 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
481 23:07:10.954883 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
482 23:07:10.961410 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
483 23:07:10.964710 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
484 23:07:10.972349 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
485 23:07:10.979604 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
486 23:07:10.982611 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
487 23:07:10.987077 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
488 23:07:10.993594 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
489 23:07:10.996783 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
490 23:07:11.000260 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
491 23:07:11.007692 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
492 23:07:11.011533 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
493 23:07:11.015269 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
494 23:07:11.022620 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
495 23:07:11.026248 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
496 23:07:11.033257 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
497 23:07:11.037063 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
498 23:07:11.040118 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
499 23:07:11.046503 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
500 23:07:11.049910 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
501 23:07:11.053220 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
502 23:07:11.060271 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
503 23:07:11.063447 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
504 23:07:11.066320 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
505 23:07:11.073587 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
506 23:07:11.076711 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
507 23:07:11.079940 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
508 23:07:11.083398 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
509 23:07:11.089907 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
510 23:07:11.093142 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
511 23:07:11.100242 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
512 23:07:11.110044 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
513 23:07:11.113179 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
514 23:07:11.122884 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
515 23:07:11.129930 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
516 23:07:11.136375 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
517 23:07:11.139775 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
518 23:07:11.143021 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
519 23:07:11.150795 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x34
520 23:07:11.156903 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
521 23:07:11.160541 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
522 23:07:11.167174 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
523 23:07:11.175415 [RTC]rtc_get_frequency_meter,154: input=15, output=794
524 23:07:11.178425 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
525 23:07:11.185330 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
526 23:07:11.188618 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
527 23:07:11.191795 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
528 23:07:11.194950 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
529 23:07:11.198972 ADC[4]: Raw value=894821 ID=7
530 23:07:11.202023 ADC[3]: Raw value=213070 ID=1
531 23:07:11.205594 RAM Code: 0x71
532 23:07:11.208734 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
533 23:07:11.212148 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
534 23:07:11.221794 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
535 23:07:11.229053 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
536 23:07:11.232557 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
537 23:07:11.235424 in-header: 03 07 00 00 08 00 00 00
538 23:07:11.238812 in-data: aa e4 47 04 13 02 00 00
539 23:07:11.242409 Chrome EC: UHEPI supported
540 23:07:11.249174 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
541 23:07:11.252997 in-header: 03 95 00 00 08 00 00 00
542 23:07:11.253586 in-data: 18 20 20 08 00 00 00 00
543 23:07:11.257180 MRC: failed to locate region type 0.
544 23:07:11.264307 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
545 23:07:11.268145 DRAM-K: Running full calibration
546 23:07:11.272191 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
547 23:07:11.275717 header.status = 0x0
548 23:07:11.279478 header.version = 0x6 (expected: 0x6)
549 23:07:11.283159 header.size = 0xd00 (expected: 0xd00)
550 23:07:11.283604 header.flags = 0x0
551 23:07:11.290424 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
552 23:07:11.307485 read SPI 0x72590 0x1c583: 12503 us, 9285 KB/s, 74.280 Mbps
553 23:07:11.314953 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
554 23:07:11.318499 dram_init: ddr_geometry: 2
555 23:07:11.318932 [EMI] MDL number = 2
556 23:07:11.322282 [EMI] Get MDL freq = 0
557 23:07:11.322714 dram_init: ddr_type: 0
558 23:07:11.326275 is_discrete_lpddr4: 1
559 23:07:11.329776 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
560 23:07:11.330208
561 23:07:11.330550
562 23:07:11.330868 [Bian_co] ETT version 0.0.0.1
563 23:07:11.337053 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
564 23:07:11.337759
565 23:07:11.340636 dramc_set_vcore_voltage set vcore to 650000
566 23:07:11.341078 Read voltage for 800, 4
567 23:07:11.344672 Vio18 = 0
568 23:07:11.345277 Vcore = 650000
569 23:07:11.345715 Vdram = 0
570 23:07:11.348369 Vddq = 0
571 23:07:11.348800 Vmddr = 0
572 23:07:11.349139 dram_init: config_dvfs: 1
573 23:07:11.355202 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
574 23:07:11.359439 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
575 23:07:11.362769 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=9
576 23:07:11.366702 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=9
577 23:07:11.369751 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
578 23:07:11.376676 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
579 23:07:11.377225 MEM_TYPE=3, freq_sel=18
580 23:07:11.379813 sv_algorithm_assistance_LP4_1600
581 23:07:11.383564 ============ PULL DRAM RESETB DOWN ============
582 23:07:11.390097 ========== PULL DRAM RESETB DOWN end =========
583 23:07:11.393818 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
584 23:07:11.396638 ===================================
585 23:07:11.399517 LPDDR4 DRAM CONFIGURATION
586 23:07:11.402767 ===================================
587 23:07:11.403204 EX_ROW_EN[0] = 0x0
588 23:07:11.406752 EX_ROW_EN[1] = 0x0
589 23:07:11.407286 LP4Y_EN = 0x0
590 23:07:11.409732 WORK_FSP = 0x0
591 23:07:11.410164 WL = 0x2
592 23:07:11.413542 RL = 0x2
593 23:07:11.414085 BL = 0x2
594 23:07:11.416818 RPST = 0x0
595 23:07:11.419949 RD_PRE = 0x0
596 23:07:11.420478 WR_PRE = 0x1
597 23:07:11.423261 WR_PST = 0x0
598 23:07:11.423797 DBI_WR = 0x0
599 23:07:11.426585 DBI_RD = 0x0
600 23:07:11.427013 OTF = 0x1
601 23:07:11.429863 ===================================
602 23:07:11.433517 ===================================
603 23:07:11.434055 ANA top config
604 23:07:11.436767 ===================================
605 23:07:11.440033 DLL_ASYNC_EN = 0
606 23:07:11.443226 ALL_SLAVE_EN = 1
607 23:07:11.446751 NEW_RANK_MODE = 1
608 23:07:11.450255 DLL_IDLE_MODE = 1
609 23:07:11.450794 LP45_APHY_COMB_EN = 1
610 23:07:11.453564 TX_ODT_DIS = 1
611 23:07:11.457136 NEW_8X_MODE = 1
612 23:07:11.460109 ===================================
613 23:07:11.463460 ===================================
614 23:07:11.466536 data_rate = 1600
615 23:07:11.469785 CKR = 1
616 23:07:11.470341 DQ_P2S_RATIO = 8
617 23:07:11.473634 ===================================
618 23:07:11.476573 CA_P2S_RATIO = 8
619 23:07:11.479961 DQ_CA_OPEN = 0
620 23:07:11.483625 DQ_SEMI_OPEN = 0
621 23:07:11.486765 CA_SEMI_OPEN = 0
622 23:07:11.487213 CA_FULL_RATE = 0
623 23:07:11.489653 DQ_CKDIV4_EN = 1
624 23:07:11.494105 CA_CKDIV4_EN = 1
625 23:07:11.496804 CA_PREDIV_EN = 0
626 23:07:11.500409 PH8_DLY = 0
627 23:07:11.503459 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
628 23:07:11.503956 DQ_AAMCK_DIV = 4
629 23:07:11.506911 CA_AAMCK_DIV = 4
630 23:07:11.509931 CA_ADMCK_DIV = 4
631 23:07:11.513805 DQ_TRACK_CA_EN = 0
632 23:07:11.517277 CA_PICK = 800
633 23:07:11.520446 CA_MCKIO = 800
634 23:07:11.520991 MCKIO_SEMI = 0
635 23:07:11.523828 PLL_FREQ = 3068
636 23:07:11.527011 DQ_UI_PI_RATIO = 32
637 23:07:11.530184 CA_UI_PI_RATIO = 0
638 23:07:11.533642 ===================================
639 23:07:11.536648 ===================================
640 23:07:11.540347 memory_type:LPDDR4
641 23:07:11.540897 GP_NUM : 10
642 23:07:11.543320 SRAM_EN : 1
643 23:07:11.547321 MD32_EN : 0
644 23:07:11.550056 ===================================
645 23:07:11.550544 [ANA_INIT] >>>>>>>>>>>>>>
646 23:07:11.553353 <<<<<< [CONFIGURE PHASE]: ANA_TX
647 23:07:11.557160 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
648 23:07:11.559988 ===================================
649 23:07:11.563503 data_rate = 1600,PCW = 0X7600
650 23:07:11.567118 ===================================
651 23:07:11.570015 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
652 23:07:11.576761 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
653 23:07:11.580383 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
654 23:07:11.586911 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
655 23:07:11.590414 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
656 23:07:11.594051 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
657 23:07:11.594498 [ANA_INIT] flow start
658 23:07:11.598208 [ANA_INIT] PLL >>>>>>>>
659 23:07:11.598654 [ANA_INIT] PLL <<<<<<<<
660 23:07:11.601407 [ANA_INIT] MIDPI >>>>>>>>
661 23:07:11.605330 [ANA_INIT] MIDPI <<<<<<<<
662 23:07:11.605816 [ANA_INIT] DLL >>>>>>>>
663 23:07:11.609350 [ANA_INIT] flow end
664 23:07:11.612792 ============ LP4 DIFF to SE enter ============
665 23:07:11.616630 ============ LP4 DIFF to SE exit ============
666 23:07:11.619709 [ANA_INIT] <<<<<<<<<<<<<
667 23:07:11.623985 [Flow] Enable top DCM control >>>>>
668 23:07:11.624429 [Flow] Enable top DCM control <<<<<
669 23:07:11.627972 Enable DLL master slave shuffle
670 23:07:11.635102 ==============================================================
671 23:07:11.635685 Gating Mode config
672 23:07:11.641743 ==============================================================
673 23:07:11.642302 Config description:
674 23:07:11.651934 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
675 23:07:11.658430 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
676 23:07:11.665365 SELPH_MODE 0: By rank 1: By Phase
677 23:07:11.668610 ==============================================================
678 23:07:11.672110 GAT_TRACK_EN = 1
679 23:07:11.675390 RX_GATING_MODE = 2
680 23:07:11.678529 RX_GATING_TRACK_MODE = 2
681 23:07:11.681636 SELPH_MODE = 1
682 23:07:11.685266 PICG_EARLY_EN = 1
683 23:07:11.688888 VALID_LAT_VALUE = 1
684 23:07:11.691587 ==============================================================
685 23:07:11.695279 Enter into Gating configuration >>>>
686 23:07:11.698260 Exit from Gating configuration <<<<
687 23:07:11.701682 Enter into DVFS_PRE_config >>>>>
688 23:07:11.715299 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
689 23:07:11.718272 Exit from DVFS_PRE_config <<<<<
690 23:07:11.722407 Enter into PICG configuration >>>>
691 23:07:11.722955 Exit from PICG configuration <<<<
692 23:07:11.725092 [RX_INPUT] configuration >>>>>
693 23:07:11.728899 [RX_INPUT] configuration <<<<<
694 23:07:11.735418 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
695 23:07:11.738447 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
696 23:07:11.745557 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
697 23:07:11.752363 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
698 23:07:11.759093 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
699 23:07:11.765267 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
700 23:07:11.768865 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
701 23:07:11.771857 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
702 23:07:11.774972 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
703 23:07:11.781704 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
704 23:07:11.785626 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
705 23:07:11.788684 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
706 23:07:11.792153 ===================================
707 23:07:11.795018 LPDDR4 DRAM CONFIGURATION
708 23:07:11.798509 ===================================
709 23:07:11.798943 EX_ROW_EN[0] = 0x0
710 23:07:11.801851 EX_ROW_EN[1] = 0x0
711 23:07:11.805299 LP4Y_EN = 0x0
712 23:07:11.805866 WORK_FSP = 0x0
713 23:07:11.808940 WL = 0x2
714 23:07:11.809470 RL = 0x2
715 23:07:11.812366 BL = 0x2
716 23:07:11.812926 RPST = 0x0
717 23:07:11.816114 RD_PRE = 0x0
718 23:07:11.816643 WR_PRE = 0x1
719 23:07:11.818647 WR_PST = 0x0
720 23:07:11.819074 DBI_WR = 0x0
721 23:07:11.822178 DBI_RD = 0x0
722 23:07:11.822709 OTF = 0x1
723 23:07:11.825655 ===================================
724 23:07:11.828891 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
725 23:07:11.832794 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
726 23:07:11.840405 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
727 23:07:11.844015 ===================================
728 23:07:11.844552 LPDDR4 DRAM CONFIGURATION
729 23:07:11.847503 ===================================
730 23:07:11.850541 EX_ROW_EN[0] = 0x10
731 23:07:11.851003 EX_ROW_EN[1] = 0x0
732 23:07:11.855052 LP4Y_EN = 0x0
733 23:07:11.855581 WORK_FSP = 0x0
734 23:07:11.858436 WL = 0x2
735 23:07:11.858996 RL = 0x2
736 23:07:11.861957 BL = 0x2
737 23:07:11.862487 RPST = 0x0
738 23:07:11.865744 RD_PRE = 0x0
739 23:07:11.866274 WR_PRE = 0x1
740 23:07:11.866620 WR_PST = 0x0
741 23:07:11.868844 DBI_WR = 0x0
742 23:07:11.869315 DBI_RD = 0x0
743 23:07:11.872751 OTF = 0x1
744 23:07:11.876788 ===================================
745 23:07:11.883253 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
746 23:07:11.886867 nWR fixed to 40
747 23:07:11.887330 [ModeRegInit_LP4] CH0 RK0
748 23:07:11.890875 [ModeRegInit_LP4] CH0 RK1
749 23:07:11.893983 [ModeRegInit_LP4] CH1 RK0
750 23:07:11.894516 [ModeRegInit_LP4] CH1 RK1
751 23:07:11.897833 match AC timing 13
752 23:07:11.900998 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
753 23:07:11.905193 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
754 23:07:11.908979 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
755 23:07:11.919302 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
756 23:07:11.920262 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
757 23:07:11.920652 [EMI DOE] emi_dcm 0
758 23:07:11.923163 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
759 23:07:11.926950 ==
760 23:07:11.927492 Dram Type= 6, Freq= 0, CH_0, rank 0
761 23:07:11.930825 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
762 23:07:11.934552 ==
763 23:07:11.938436 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
764 23:07:11.945142 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
765 23:07:11.953943 [CA 0] Center 38 (7~69) winsize 63
766 23:07:11.956746 [CA 1] Center 37 (7~68) winsize 62
767 23:07:11.960726 [CA 2] Center 35 (5~66) winsize 62
768 23:07:11.964443 [CA 3] Center 35 (5~66) winsize 62
769 23:07:11.968319 [CA 4] Center 34 (4~65) winsize 62
770 23:07:11.971521 [CA 5] Center 34 (3~65) winsize 63
771 23:07:11.971952
772 23:07:11.975399 [CmdBusTrainingLP45] Vref(ca) range 1: 34
773 23:07:11.975835
774 23:07:11.979371 [CATrainingPosCal] consider 1 rank data
775 23:07:11.979901 u2DelayCellTimex100 = 270/100 ps
776 23:07:11.982698 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
777 23:07:11.989788 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
778 23:07:11.993620 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
779 23:07:11.996692 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
780 23:07:12.000861 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
781 23:07:12.004019 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
782 23:07:12.004539
783 23:07:12.007688 CA PerBit enable=1, Macro0, CA PI delay=34
784 23:07:12.008194
785 23:07:12.008541 [CBTSetCACLKResult] CA Dly = 34
786 23:07:12.011473 CS Dly: 6 (0~37)
787 23:07:12.011989 ==
788 23:07:12.014979 Dram Type= 6, Freq= 0, CH_0, rank 1
789 23:07:12.018884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
790 23:07:12.019402 ==
791 23:07:12.022339 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
792 23:07:12.029637 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
793 23:07:12.040160 [CA 0] Center 38 (7~69) winsize 63
794 23:07:12.043937 [CA 1] Center 38 (7~69) winsize 63
795 23:07:12.047384 [CA 2] Center 35 (5~66) winsize 62
796 23:07:12.050948 [CA 3] Center 35 (5~66) winsize 62
797 23:07:12.054500 [CA 4] Center 34 (4~65) winsize 62
798 23:07:12.054930 [CA 5] Center 34 (4~65) winsize 62
799 23:07:12.058196
800 23:07:12.061812 [CmdBusTrainingLP45] Vref(ca) range 1: 34
801 23:07:12.062339
802 23:07:12.065828 [CATrainingPosCal] consider 2 rank data
803 23:07:12.066263 u2DelayCellTimex100 = 270/100 ps
804 23:07:12.069088 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
805 23:07:12.073155 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
806 23:07:12.076686 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
807 23:07:12.080462 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
808 23:07:12.083865 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
809 23:07:12.087786 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
810 23:07:12.088240
811 23:07:12.091932 CA PerBit enable=1, Macro0, CA PI delay=34
812 23:07:12.092454
813 23:07:12.095100 [CBTSetCACLKResult] CA Dly = 34
814 23:07:12.098801 CS Dly: 6 (0~37)
815 23:07:12.099440
816 23:07:12.102606 ----->DramcWriteLeveling(PI) begin...
817 23:07:12.103051 ==
818 23:07:12.105770 Dram Type= 6, Freq= 0, CH_0, rank 0
819 23:07:12.109000 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
820 23:07:12.109430 ==
821 23:07:12.112337 Write leveling (Byte 0): 31 => 31
822 23:07:12.115685 Write leveling (Byte 1): 31 => 31
823 23:07:12.119007 DramcWriteLeveling(PI) end<-----
824 23:07:12.119432
825 23:07:12.119821 ==
826 23:07:12.122452 Dram Type= 6, Freq= 0, CH_0, rank 0
827 23:07:12.125944 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
828 23:07:12.126380 ==
829 23:07:12.129165 [Gating] SW mode calibration
830 23:07:12.135810 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
831 23:07:12.142415 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
832 23:07:12.146040 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
833 23:07:12.148917 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
834 23:07:12.152587 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
835 23:07:12.159267 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
836 23:07:12.162179 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
837 23:07:12.165116 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
838 23:07:12.171830 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
839 23:07:12.175722 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
840 23:07:12.179742 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
841 23:07:12.186755 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
842 23:07:12.190112 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
843 23:07:12.193689 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
844 23:07:12.196969 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
845 23:07:12.203860 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
846 23:07:12.207714 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
847 23:07:12.211085 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
848 23:07:12.214255 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
849 23:07:12.221113 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
850 23:07:12.224619 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
851 23:07:12.227985 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
852 23:07:12.234212 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
853 23:07:12.237658 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
854 23:07:12.241215 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
855 23:07:12.247531 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 23:07:12.251192 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 23:07:12.254243 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 23:07:12.257552 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 23:07:12.264649 0 9 12 | B1->B0 | 2a2a 3030 | 0 1 | (0 0) (1 1)
860 23:07:12.267787 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
861 23:07:12.271030 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
862 23:07:12.278154 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
863 23:07:12.281249 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
864 23:07:12.284855 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
865 23:07:12.291589 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
866 23:07:12.294782 0 10 8 | B1->B0 | 3434 3030 | 0 0 | (0 0) (0 1)
867 23:07:12.298157 0 10 12 | B1->B0 | 2e2e 2525 | 0 0 | (0 1) (0 0)
868 23:07:12.304678 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 23:07:12.307787 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 23:07:12.311434 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
871 23:07:12.317957 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
872 23:07:12.321305 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 23:07:12.324656 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 23:07:12.331215 0 11 8 | B1->B0 | 2424 2d2d | 0 0 | (0 0) (0 0)
875 23:07:12.334303 0 11 12 | B1->B0 | 3434 4141 | 0 0 | (0 0) (0 0)
876 23:07:12.337536 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
877 23:07:12.344578 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
878 23:07:12.347756 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
879 23:07:12.351689 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
880 23:07:12.354566 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
881 23:07:12.361460 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
882 23:07:12.364680 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
883 23:07:12.368128 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
884 23:07:12.374264 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
885 23:07:12.377736 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
886 23:07:12.381183 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
887 23:07:12.388182 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
888 23:07:12.391314 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
889 23:07:12.394461 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
890 23:07:12.401097 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
891 23:07:12.404620 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
892 23:07:12.408010 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
893 23:07:12.414640 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
894 23:07:12.418172 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
895 23:07:12.420870 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
896 23:07:12.427873 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
897 23:07:12.431124 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
898 23:07:12.434675 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
899 23:07:12.441323 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
900 23:07:12.441903 Total UI for P1: 0, mck2ui 16
901 23:07:12.444920 best dqsien dly found for B0: ( 0, 14, 8)
902 23:07:12.451518 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
903 23:07:12.454458 Total UI for P1: 0, mck2ui 16
904 23:07:12.458037 best dqsien dly found for B1: ( 0, 14, 12)
905 23:07:12.461498 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
906 23:07:12.464627 best DQS1 dly(MCK, UI, PI) = (0, 14, 12)
907 23:07:12.465156
908 23:07:12.467879 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
909 23:07:12.470919 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 12)
910 23:07:12.474238 [Gating] SW calibration Done
911 23:07:12.474665 ==
912 23:07:12.478093 Dram Type= 6, Freq= 0, CH_0, rank 0
913 23:07:12.481366 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
914 23:07:12.481939 ==
915 23:07:12.484254 RX Vref Scan: 0
916 23:07:12.484676
917 23:07:12.485012 RX Vref 0 -> 0, step: 1
918 23:07:12.487808
919 23:07:12.488335 RX Delay -130 -> 252, step: 16
920 23:07:12.494396 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
921 23:07:12.497791 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
922 23:07:12.500960 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
923 23:07:12.504429 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
924 23:07:12.507730 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
925 23:07:12.514446 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
926 23:07:12.517758 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
927 23:07:12.521049 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
928 23:07:12.524408 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
929 23:07:12.527836 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
930 23:07:12.531495 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
931 23:07:12.537984 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
932 23:07:12.541587 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
933 23:07:12.544814 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
934 23:07:12.548091 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
935 23:07:12.554657 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
936 23:07:12.555173 ==
937 23:07:12.558003 Dram Type= 6, Freq= 0, CH_0, rank 0
938 23:07:12.561192 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
939 23:07:12.561897 ==
940 23:07:12.562255 DQS Delay:
941 23:07:12.564760 DQS0 = 0, DQS1 = 0
942 23:07:12.565183 DQM Delay:
943 23:07:12.568072 DQM0 = 80, DQM1 = 70
944 23:07:12.568601 DQ Delay:
945 23:07:12.571016 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
946 23:07:12.574336 DQ4 =77, DQ5 =69, DQ6 =85, DQ7 =93
947 23:07:12.577569 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =61
948 23:07:12.581460 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
949 23:07:12.582054
950 23:07:12.582395
951 23:07:12.582710 ==
952 23:07:12.584749 Dram Type= 6, Freq= 0, CH_0, rank 0
953 23:07:12.588898 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
954 23:07:12.589442 ==
955 23:07:12.589858
956 23:07:12.590174
957 23:07:12.591238 TX Vref Scan disable
958 23:07:12.595091 == TX Byte 0 ==
959 23:07:12.598002 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
960 23:07:12.601233 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
961 23:07:12.605169 == TX Byte 1 ==
962 23:07:12.608266 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
963 23:07:12.611563 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
964 23:07:12.612091 ==
965 23:07:12.614813 Dram Type= 6, Freq= 0, CH_0, rank 0
966 23:07:12.617977 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
967 23:07:12.621100 ==
968 23:07:12.632464 TX Vref=22, minBit 10, minWin=26, winSum=432
969 23:07:12.635851 TX Vref=24, minBit 9, minWin=26, winSum=434
970 23:07:12.639179 TX Vref=26, minBit 7, minWin=27, winSum=441
971 23:07:12.642457 TX Vref=28, minBit 9, minWin=27, winSum=442
972 23:07:12.646089 TX Vref=30, minBit 9, minWin=27, winSum=441
973 23:07:12.652567 TX Vref=32, minBit 12, minWin=26, winSum=437
974 23:07:12.655683 [TxChooseVref] Worse bit 9, Min win 27, Win sum 442, Final Vref 28
975 23:07:12.656113
976 23:07:12.659161 Final TX Range 1 Vref 28
977 23:07:12.659688
978 23:07:12.660024 ==
979 23:07:12.662742 Dram Type= 6, Freq= 0, CH_0, rank 0
980 23:07:12.665850 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
981 23:07:12.666406 ==
982 23:07:12.668974
983 23:07:12.669395
984 23:07:12.669806 TX Vref Scan disable
985 23:07:12.672574 == TX Byte 0 ==
986 23:07:12.675934 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
987 23:07:12.679706 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
988 23:07:12.682958 == TX Byte 1 ==
989 23:07:12.685854 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
990 23:07:12.689346 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
991 23:07:12.692604
992 23:07:12.693127 [DATLAT]
993 23:07:12.693465 Freq=800, CH0 RK0
994 23:07:12.693821
995 23:07:12.696231 DATLAT Default: 0xa
996 23:07:12.696756 0, 0xFFFF, sum = 0
997 23:07:12.698939 1, 0xFFFF, sum = 0
998 23:07:12.699372 2, 0xFFFF, sum = 0
999 23:07:12.702237 3, 0xFFFF, sum = 0
1000 23:07:12.702762 4, 0xFFFF, sum = 0
1001 23:07:12.705944 5, 0xFFFF, sum = 0
1002 23:07:12.706374 6, 0xFFFF, sum = 0
1003 23:07:12.709157 7, 0xFFFF, sum = 0
1004 23:07:12.712670 8, 0xFFFF, sum = 0
1005 23:07:12.713204 9, 0x0, sum = 1
1006 23:07:12.713613 10, 0x0, sum = 2
1007 23:07:12.715637 11, 0x0, sum = 3
1008 23:07:12.716071 12, 0x0, sum = 4
1009 23:07:12.719063 best_step = 10
1010 23:07:12.719596
1011 23:07:12.719937 ==
1012 23:07:12.722577 Dram Type= 6, Freq= 0, CH_0, rank 0
1013 23:07:12.725470 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1014 23:07:12.725949 ==
1015 23:07:12.729062 RX Vref Scan: 1
1016 23:07:12.729530
1017 23:07:12.729903 Set Vref Range= 32 -> 127
1018 23:07:12.730222
1019 23:07:12.732310 RX Vref 32 -> 127, step: 1
1020 23:07:12.732737
1021 23:07:12.735826 RX Delay -111 -> 252, step: 8
1022 23:07:12.736251
1023 23:07:12.739341 Set Vref, RX VrefLevel [Byte0]: 32
1024 23:07:12.742502 [Byte1]: 32
1025 23:07:12.742969
1026 23:07:12.745862 Set Vref, RX VrefLevel [Byte0]: 33
1027 23:07:12.748993 [Byte1]: 33
1028 23:07:12.752826
1029 23:07:12.753349 Set Vref, RX VrefLevel [Byte0]: 34
1030 23:07:12.756312 [Byte1]: 34
1031 23:07:12.760463
1032 23:07:12.760983 Set Vref, RX VrefLevel [Byte0]: 35
1033 23:07:12.763787 [Byte1]: 35
1034 23:07:12.768245
1035 23:07:12.768845 Set Vref, RX VrefLevel [Byte0]: 36
1036 23:07:12.772054 [Byte1]: 36
1037 23:07:12.776107
1038 23:07:12.776639 Set Vref, RX VrefLevel [Byte0]: 37
1039 23:07:12.779613 [Byte1]: 37
1040 23:07:12.783888
1041 23:07:12.784429 Set Vref, RX VrefLevel [Byte0]: 38
1042 23:07:12.786768 [Byte1]: 38
1043 23:07:12.791414
1044 23:07:12.791929 Set Vref, RX VrefLevel [Byte0]: 39
1045 23:07:12.794480 [Byte1]: 39
1046 23:07:12.799196
1047 23:07:12.799736 Set Vref, RX VrefLevel [Byte0]: 40
1048 23:07:12.802083 [Byte1]: 40
1049 23:07:12.806803
1050 23:07:12.807318 Set Vref, RX VrefLevel [Byte0]: 41
1051 23:07:12.809846 [Byte1]: 41
1052 23:07:12.814307
1053 23:07:12.814826 Set Vref, RX VrefLevel [Byte0]: 42
1054 23:07:12.817820 [Byte1]: 42
1055 23:07:12.821939
1056 23:07:12.822459 Set Vref, RX VrefLevel [Byte0]: 43
1057 23:07:12.825410 [Byte1]: 43
1058 23:07:12.829643
1059 23:07:12.830070 Set Vref, RX VrefLevel [Byte0]: 44
1060 23:07:12.832748 [Byte1]: 44
1061 23:07:12.837582
1062 23:07:12.838100 Set Vref, RX VrefLevel [Byte0]: 45
1063 23:07:12.840758 [Byte1]: 45
1064 23:07:12.844603
1065 23:07:12.845029 Set Vref, RX VrefLevel [Byte0]: 46
1066 23:07:12.848141 [Byte1]: 46
1067 23:07:12.852934
1068 23:07:12.853358 Set Vref, RX VrefLevel [Byte0]: 47
1069 23:07:12.856031 [Byte1]: 47
1070 23:07:12.860089
1071 23:07:12.860516 Set Vref, RX VrefLevel [Byte0]: 48
1072 23:07:12.863413 [Byte1]: 48
1073 23:07:12.868106
1074 23:07:12.868533 Set Vref, RX VrefLevel [Byte0]: 49
1075 23:07:12.871413 [Byte1]: 49
1076 23:07:12.875061
1077 23:07:12.875484 Set Vref, RX VrefLevel [Byte0]: 50
1078 23:07:12.878921 [Byte1]: 50
1079 23:07:12.882623
1080 23:07:12.883087 Set Vref, RX VrefLevel [Byte0]: 51
1081 23:07:12.885916 [Byte1]: 51
1082 23:07:12.890844
1083 23:07:12.891361 Set Vref, RX VrefLevel [Byte0]: 52
1084 23:07:12.893772 [Byte1]: 52
1085 23:07:12.898388
1086 23:07:12.898920 Set Vref, RX VrefLevel [Byte0]: 53
1087 23:07:12.901699 [Byte1]: 53
1088 23:07:12.905719
1089 23:07:12.906182 Set Vref, RX VrefLevel [Byte0]: 54
1090 23:07:12.909270 [Byte1]: 54
1091 23:07:12.913700
1092 23:07:12.914212 Set Vref, RX VrefLevel [Byte0]: 55
1093 23:07:12.916920 [Byte1]: 55
1094 23:07:12.921203
1095 23:07:12.921797 Set Vref, RX VrefLevel [Byte0]: 56
1096 23:07:12.925099 [Byte1]: 56
1097 23:07:12.928949
1098 23:07:12.929464 Set Vref, RX VrefLevel [Byte0]: 57
1099 23:07:12.932264 [Byte1]: 57
1100 23:07:12.936675
1101 23:07:12.937196 Set Vref, RX VrefLevel [Byte0]: 58
1102 23:07:12.939561 [Byte1]: 58
1103 23:07:12.943851
1104 23:07:12.944279 Set Vref, RX VrefLevel [Byte0]: 59
1105 23:07:12.947428 [Byte1]: 59
1106 23:07:12.951586
1107 23:07:12.952104 Set Vref, RX VrefLevel [Byte0]: 60
1108 23:07:12.958128 [Byte1]: 60
1109 23:07:12.958650
1110 23:07:12.961462 Set Vref, RX VrefLevel [Byte0]: 61
1111 23:07:12.964957 [Byte1]: 61
1112 23:07:12.965581
1113 23:07:12.968095 Set Vref, RX VrefLevel [Byte0]: 62
1114 23:07:12.971614 [Byte1]: 62
1115 23:07:12.972174
1116 23:07:12.974975 Set Vref, RX VrefLevel [Byte0]: 63
1117 23:07:12.978155 [Byte1]: 63
1118 23:07:12.981943
1119 23:07:12.982402 Set Vref, RX VrefLevel [Byte0]: 64
1120 23:07:12.985387 [Byte1]: 64
1121 23:07:12.989754
1122 23:07:12.990176 Set Vref, RX VrefLevel [Byte0]: 65
1123 23:07:12.993120 [Byte1]: 65
1124 23:07:12.997358
1125 23:07:12.997927 Set Vref, RX VrefLevel [Byte0]: 66
1126 23:07:13.000999 [Byte1]: 66
1127 23:07:13.005130
1128 23:07:13.005615 Set Vref, RX VrefLevel [Byte0]: 67
1129 23:07:13.008327 [Byte1]: 67
1130 23:07:13.012574
1131 23:07:13.013004 Set Vref, RX VrefLevel [Byte0]: 68
1132 23:07:13.016348 [Byte1]: 68
1133 23:07:13.020742
1134 23:07:13.021189 Set Vref, RX VrefLevel [Byte0]: 69
1135 23:07:13.023808 [Byte1]: 69
1136 23:07:13.028146
1137 23:07:13.028705 Set Vref, RX VrefLevel [Byte0]: 70
1138 23:07:13.031524 [Byte1]: 70
1139 23:07:13.035916
1140 23:07:13.036333 Set Vref, RX VrefLevel [Byte0]: 71
1141 23:07:13.039101 [Byte1]: 71
1142 23:07:13.043412
1143 23:07:13.043838 Set Vref, RX VrefLevel [Byte0]: 72
1144 23:07:13.046954 [Byte1]: 72
1145 23:07:13.051207
1146 23:07:13.051645 Set Vref, RX VrefLevel [Byte0]: 73
1147 23:07:13.057303 [Byte1]: 73
1148 23:07:13.057783
1149 23:07:13.060655 Set Vref, RX VrefLevel [Byte0]: 74
1150 23:07:13.064464 [Byte1]: 74
1151 23:07:13.064986
1152 23:07:13.067505 Set Vref, RX VrefLevel [Byte0]: 75
1153 23:07:13.070959 [Byte1]: 75
1154 23:07:13.071510
1155 23:07:13.074333 Set Vref, RX VrefLevel [Byte0]: 76
1156 23:07:13.077660 [Byte1]: 76
1157 23:07:13.081400
1158 23:07:13.081873 Set Vref, RX VrefLevel [Byte0]: 77
1159 23:07:13.084945 [Byte1]: 77
1160 23:07:13.089367
1161 23:07:13.089817 Set Vref, RX VrefLevel [Byte0]: 78
1162 23:07:13.092987 [Byte1]: 78
1163 23:07:13.097175
1164 23:07:13.097651 Final RX Vref Byte 0 = 64 to rank0
1165 23:07:13.100511 Final RX Vref Byte 1 = 58 to rank0
1166 23:07:13.103327 Final RX Vref Byte 0 = 64 to rank1
1167 23:07:13.107347 Final RX Vref Byte 1 = 58 to rank1==
1168 23:07:13.110008 Dram Type= 6, Freq= 0, CH_0, rank 0
1169 23:07:13.116897 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1170 23:07:13.117414 ==
1171 23:07:13.117796 DQS Delay:
1172 23:07:13.118145 DQS0 = 0, DQS1 = 0
1173 23:07:13.120026 DQM Delay:
1174 23:07:13.120444 DQM0 = 81, DQM1 = 68
1175 23:07:13.123538 DQ Delay:
1176 23:07:13.127236 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1177 23:07:13.130245 DQ4 =80, DQ5 =68, DQ6 =88, DQ7 =92
1178 23:07:13.130667 DQ8 =60, DQ9 =56, DQ10 =68, DQ11 =60
1179 23:07:13.136804 DQ12 =76, DQ13 =72, DQ14 =76, DQ15 =76
1180 23:07:13.137223
1181 23:07:13.137590
1182 23:07:13.144038 [DQSOSCAuto] RK0, (LSB)MR18= 0x2928, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 399 ps
1183 23:07:13.147132 CH0 RK0: MR19=606, MR18=2928
1184 23:07:13.153376 CH0_RK0: MR19=0x606, MR18=0x2928, DQSOSC=399, MR23=63, INC=92, DEC=61
1185 23:07:13.153977
1186 23:07:13.156833 ----->DramcWriteLeveling(PI) begin...
1187 23:07:13.157276 ==
1188 23:07:13.160220 Dram Type= 6, Freq= 0, CH_0, rank 1
1189 23:07:13.163706 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1190 23:07:13.164231 ==
1191 23:07:13.167192 Write leveling (Byte 0): 31 => 31
1192 23:07:13.170258 Write leveling (Byte 1): 28 => 28
1193 23:07:13.173921 DramcWriteLeveling(PI) end<-----
1194 23:07:13.174402
1195 23:07:13.174839 ==
1196 23:07:13.176938 Dram Type= 6, Freq= 0, CH_0, rank 1
1197 23:07:13.180170 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1198 23:07:13.180591 ==
1199 23:07:13.183408 [Gating] SW mode calibration
1200 23:07:13.190463 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1201 23:07:13.197097 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1202 23:07:13.199990 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1203 23:07:13.203431 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1204 23:07:13.210454 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1205 23:07:13.213244 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1206 23:07:13.217173 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1207 23:07:13.223749 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1208 23:07:13.226929 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1209 23:07:13.230002 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1210 23:07:13.237117 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1211 23:07:13.240256 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1212 23:07:13.243249 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1213 23:07:13.250209 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1214 23:07:13.253333 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1215 23:07:13.256758 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1216 23:07:13.260236 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1217 23:07:13.304196 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1218 23:07:13.304959 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1219 23:07:13.305588 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1220 23:07:13.306449 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1221 23:07:13.307001 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1222 23:07:13.307493 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 23:07:13.307964 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 23:07:13.308413 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 23:07:13.308856 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 23:07:13.309296 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 23:07:13.348806 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 23:07:13.349677 0 9 8 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (1 1)
1229 23:07:13.350043 0 9 12 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
1230 23:07:13.350362 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1231 23:07:13.350669 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1232 23:07:13.350966 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1233 23:07:13.351258 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1234 23:07:13.351604 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1235 23:07:13.351902 0 10 4 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
1236 23:07:13.352188 0 10 8 | B1->B0 | 2d2d 2626 | 0 0 | (0 1) (0 0)
1237 23:07:13.359529 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
1238 23:07:13.363076 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 23:07:13.366035 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1240 23:07:13.369629 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1241 23:07:13.373144 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 23:07:13.376626 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1243 23:07:13.379383 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 23:07:13.386153 0 11 8 | B1->B0 | 2f2f 3939 | 0 0 | (0 0) (0 0)
1245 23:07:13.389561 0 11 12 | B1->B0 | 4040 4646 | 1 0 | (0 0) (0 0)
1246 23:07:13.392804 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1247 23:07:13.399666 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1248 23:07:13.402676 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1249 23:07:13.406112 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1250 23:07:13.412736 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1251 23:07:13.416808 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1252 23:07:13.419883 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1253 23:07:13.423880 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1254 23:07:13.427616 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1255 23:07:13.434304 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1256 23:07:13.437453 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1257 23:07:13.440934 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1258 23:07:13.444555 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1259 23:07:13.452032 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1260 23:07:13.455434 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1261 23:07:13.458513 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1262 23:07:13.465430 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1263 23:07:13.469020 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1264 23:07:13.472319 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1265 23:07:13.479290 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1266 23:07:13.482146 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1267 23:07:13.485663 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1268 23:07:13.488883 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1269 23:07:13.495426 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1270 23:07:13.499028 Total UI for P1: 0, mck2ui 16
1271 23:07:13.502412 best dqsien dly found for B0: ( 0, 14, 8)
1272 23:07:13.502929 Total UI for P1: 0, mck2ui 16
1273 23:07:13.508776 best dqsien dly found for B1: ( 0, 14, 10)
1274 23:07:13.511921 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1275 23:07:13.515381 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1276 23:07:13.515902
1277 23:07:13.518836 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1278 23:07:13.522232 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1279 23:07:13.525670 [Gating] SW calibration Done
1280 23:07:13.526089 ==
1281 23:07:13.529116 Dram Type= 6, Freq= 0, CH_0, rank 1
1282 23:07:13.532412 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1283 23:07:13.532832 ==
1284 23:07:13.535153 RX Vref Scan: 0
1285 23:07:13.535567
1286 23:07:13.535897 RX Vref 0 -> 0, step: 1
1287 23:07:13.536204
1288 23:07:13.539304 RX Delay -130 -> 252, step: 16
1289 23:07:13.542415 iDelay=222, Bit 0, Center 69 (-50 ~ 189) 240
1290 23:07:13.548801 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1291 23:07:13.552318 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1292 23:07:13.555619 iDelay=222, Bit 3, Center 69 (-50 ~ 189) 240
1293 23:07:13.559527 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1294 23:07:13.562371 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1295 23:07:13.568825 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1296 23:07:13.572485 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1297 23:07:13.575477 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1298 23:07:13.578743 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1299 23:07:13.581518 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1300 23:07:13.589231 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1301 23:07:13.592292 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1302 23:07:13.595700 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1303 23:07:13.598528 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1304 23:07:13.605108 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1305 23:07:13.605673 ==
1306 23:07:13.608366 Dram Type= 6, Freq= 0, CH_0, rank 1
1307 23:07:13.611715 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1308 23:07:13.612136 ==
1309 23:07:13.612468 DQS Delay:
1310 23:07:13.615028 DQS0 = 0, DQS1 = 0
1311 23:07:13.615448 DQM Delay:
1312 23:07:13.618770 DQM0 = 76, DQM1 = 69
1313 23:07:13.619482 DQ Delay:
1314 23:07:13.621922 DQ0 =69, DQ1 =77, DQ2 =69, DQ3 =69
1315 23:07:13.625275 DQ4 =77, DQ5 =69, DQ6 =85, DQ7 =93
1316 23:07:13.628614 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
1317 23:07:13.631945 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1318 23:07:13.632389
1319 23:07:13.632838
1320 23:07:13.633258 ==
1321 23:07:13.635031 Dram Type= 6, Freq= 0, CH_0, rank 1
1322 23:07:13.638416 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1323 23:07:13.638860 ==
1324 23:07:13.639315
1325 23:07:13.639744
1326 23:07:13.642174 TX Vref Scan disable
1327 23:07:13.645330 == TX Byte 0 ==
1328 23:07:13.648896 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1329 23:07:13.652165 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1330 23:07:13.655092 == TX Byte 1 ==
1331 23:07:13.658262 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1332 23:07:13.662314 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1333 23:07:13.662858 ==
1334 23:07:13.665586 Dram Type= 6, Freq= 0, CH_0, rank 1
1335 23:07:13.668838 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1336 23:07:13.671883 ==
1337 23:07:13.683726 TX Vref=22, minBit 0, minWin=27, winSum=437
1338 23:07:13.687107 TX Vref=24, minBit 0, minWin=27, winSum=445
1339 23:07:13.690376 TX Vref=26, minBit 1, minWin=27, winSum=447
1340 23:07:13.693885 TX Vref=28, minBit 3, minWin=27, winSum=447
1341 23:07:13.697160 TX Vref=30, minBit 3, minWin=27, winSum=447
1342 23:07:13.700259 TX Vref=32, minBit 11, minWin=27, winSum=447
1343 23:07:13.706798 [TxChooseVref] Worse bit 1, Min win 27, Win sum 447, Final Vref 26
1344 23:07:13.707583
1345 23:07:13.709995 Final TX Range 1 Vref 26
1346 23:07:13.710419
1347 23:07:13.710749 ==
1348 23:07:13.713346 Dram Type= 6, Freq= 0, CH_0, rank 1
1349 23:07:13.716567 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1350 23:07:13.716992 ==
1351 23:07:13.717331
1352 23:07:13.719880
1353 23:07:13.720298 TX Vref Scan disable
1354 23:07:13.723097 == TX Byte 0 ==
1355 23:07:13.726755 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1356 23:07:13.733589 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1357 23:07:13.734016 == TX Byte 1 ==
1358 23:07:13.736720 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1359 23:07:13.740177 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1360 23:07:13.743788
1361 23:07:13.744321 [DATLAT]
1362 23:07:13.744659 Freq=800, CH0 RK1
1363 23:07:13.744974
1364 23:07:13.746899 DATLAT Default: 0xa
1365 23:07:13.747412 0, 0xFFFF, sum = 0
1366 23:07:13.750316 1, 0xFFFF, sum = 0
1367 23:07:13.750739 2, 0xFFFF, sum = 0
1368 23:07:13.753761 3, 0xFFFF, sum = 0
1369 23:07:13.754274 4, 0xFFFF, sum = 0
1370 23:07:13.757079 5, 0xFFFF, sum = 0
1371 23:07:13.757653 6, 0xFFFF, sum = 0
1372 23:07:13.760190 7, 0xFFFF, sum = 0
1373 23:07:13.763540 8, 0xFFFF, sum = 0
1374 23:07:13.764059 9, 0x0, sum = 1
1375 23:07:13.764401 10, 0x0, sum = 2
1376 23:07:13.766647 11, 0x0, sum = 3
1377 23:07:13.767068 12, 0x0, sum = 4
1378 23:07:13.770563 best_step = 10
1379 23:07:13.771075
1380 23:07:13.771406 ==
1381 23:07:13.773692 Dram Type= 6, Freq= 0, CH_0, rank 1
1382 23:07:13.776860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1383 23:07:13.777326 ==
1384 23:07:13.780039 RX Vref Scan: 0
1385 23:07:13.780452
1386 23:07:13.780777 RX Vref 0 -> 0, step: 1
1387 23:07:13.781076
1388 23:07:13.783349 RX Delay -111 -> 252, step: 8
1389 23:07:13.790140 iDelay=209, Bit 0, Center 80 (-31 ~ 192) 224
1390 23:07:13.793924 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1391 23:07:13.797032 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1392 23:07:13.800396 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
1393 23:07:13.804040 iDelay=209, Bit 4, Center 80 (-31 ~ 192) 224
1394 23:07:13.809918 iDelay=209, Bit 5, Center 60 (-55 ~ 176) 232
1395 23:07:13.813774 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1396 23:07:13.816848 iDelay=209, Bit 7, Center 92 (-23 ~ 208) 232
1397 23:07:13.820430 iDelay=209, Bit 8, Center 60 (-55 ~ 176) 232
1398 23:07:13.823196 iDelay=209, Bit 9, Center 56 (-63 ~ 176) 240
1399 23:07:13.830316 iDelay=209, Bit 10, Center 72 (-47 ~ 192) 240
1400 23:07:13.833632 iDelay=209, Bit 11, Center 64 (-55 ~ 184) 240
1401 23:07:13.836857 iDelay=209, Bit 12, Center 76 (-47 ~ 200) 248
1402 23:07:13.840214 iDelay=209, Bit 13, Center 76 (-39 ~ 192) 232
1403 23:07:13.843086 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
1404 23:07:13.849574 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
1405 23:07:13.849813 ==
1406 23:07:13.853159 Dram Type= 6, Freq= 0, CH_0, rank 1
1407 23:07:13.856602 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1408 23:07:13.856786 ==
1409 23:07:13.856929 DQS Delay:
1410 23:07:13.859619 DQS0 = 0, DQS1 = 0
1411 23:07:13.859770 DQM Delay:
1412 23:07:13.862987 DQM0 = 80, DQM1 = 70
1413 23:07:13.863138 DQ Delay:
1414 23:07:13.866266 DQ0 =80, DQ1 =88, DQ2 =76, DQ3 =72
1415 23:07:13.869916 DQ4 =80, DQ5 =60, DQ6 =92, DQ7 =92
1416 23:07:13.873248 DQ8 =60, DQ9 =56, DQ10 =72, DQ11 =64
1417 23:07:13.876378 DQ12 =76, DQ13 =76, DQ14 =80, DQ15 =80
1418 23:07:13.876492
1419 23:07:13.876582
1420 23:07:13.886187 [DQSOSCAuto] RK1, (LSB)MR18= 0x4923, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 391 ps
1421 23:07:13.886345 CH0 RK1: MR19=606, MR18=4923
1422 23:07:13.893219 CH0_RK1: MR19=0x606, MR18=0x4923, DQSOSC=391, MR23=63, INC=96, DEC=64
1423 23:07:13.896496 [RxdqsGatingPostProcess] freq 800
1424 23:07:13.903075 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1425 23:07:13.906366 Pre-setting of DQS Precalculation
1426 23:07:13.909654 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1427 23:07:13.909741 ==
1428 23:07:13.913324 Dram Type= 6, Freq= 0, CH_1, rank 0
1429 23:07:13.916343 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1430 23:07:13.916433 ==
1431 23:07:13.922825 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1432 23:07:13.929380 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1433 23:07:13.938081 [CA 0] Center 36 (6~66) winsize 61
1434 23:07:13.941346 [CA 1] Center 36 (6~67) winsize 62
1435 23:07:13.944937 [CA 2] Center 34 (5~64) winsize 60
1436 23:07:13.948267 [CA 3] Center 34 (4~64) winsize 61
1437 23:07:13.951561 [CA 4] Center 34 (4~65) winsize 62
1438 23:07:13.954849 [CA 5] Center 34 (4~64) winsize 61
1439 23:07:13.954927
1440 23:07:13.958145 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1441 23:07:13.958235
1442 23:07:13.961387 [CATrainingPosCal] consider 1 rank data
1443 23:07:13.964988 u2DelayCellTimex100 = 270/100 ps
1444 23:07:13.968277 CA0 delay=36 (6~66),Diff = 2 PI (14 cell)
1445 23:07:13.971432 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1446 23:07:13.975146 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
1447 23:07:13.981248 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1448 23:07:13.984933 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1449 23:07:13.988349 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1450 23:07:13.988438
1451 23:07:13.991608 CA PerBit enable=1, Macro0, CA PI delay=34
1452 23:07:13.991705
1453 23:07:13.994767 [CBTSetCACLKResult] CA Dly = 34
1454 23:07:13.994850 CS Dly: 5 (0~36)
1455 23:07:13.994915 ==
1456 23:07:13.998018 Dram Type= 6, Freq= 0, CH_1, rank 1
1457 23:07:14.004962 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1458 23:07:14.005046 ==
1459 23:07:14.007977 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1460 23:07:14.014666 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1461 23:07:14.024544 [CA 0] Center 37 (7~67) winsize 61
1462 23:07:14.027728 [CA 1] Center 36 (6~67) winsize 62
1463 23:07:14.031063 [CA 2] Center 35 (5~65) winsize 61
1464 23:07:14.034286 [CA 3] Center 34 (4~64) winsize 61
1465 23:07:14.037662 [CA 4] Center 34 (4~65) winsize 62
1466 23:07:14.040966 [CA 5] Center 33 (3~64) winsize 62
1467 23:07:14.041050
1468 23:07:14.044076 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1469 23:07:14.044162
1470 23:07:14.047756 [CATrainingPosCal] consider 2 rank data
1471 23:07:14.051424 u2DelayCellTimex100 = 270/100 ps
1472 23:07:14.054471 CA0 delay=36 (7~66),Diff = 2 PI (14 cell)
1473 23:07:14.058040 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1474 23:07:14.061464 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
1475 23:07:14.067902 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1476 23:07:14.070967 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1477 23:07:14.074225 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1478 23:07:14.074461
1479 23:07:14.077910 CA PerBit enable=1, Macro0, CA PI delay=34
1480 23:07:14.078146
1481 23:07:14.082271 [CBTSetCACLKResult] CA Dly = 34
1482 23:07:14.082468 CS Dly: 5 (0~37)
1483 23:07:14.082662
1484 23:07:14.085650 ----->DramcWriteLeveling(PI) begin...
1485 23:07:14.085812 ==
1486 23:07:14.089005 Dram Type= 6, Freq= 0, CH_1, rank 0
1487 23:07:14.092789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1488 23:07:14.092927 ==
1489 23:07:14.096633 Write leveling (Byte 0): 29 => 29
1490 23:07:14.099887 Write leveling (Byte 1): 30 => 30
1491 23:07:14.103695 DramcWriteLeveling(PI) end<-----
1492 23:07:14.103803
1493 23:07:14.103919 ==
1494 23:07:14.107466 Dram Type= 6, Freq= 0, CH_1, rank 0
1495 23:07:14.111052 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1496 23:07:14.111150 ==
1497 23:07:14.114860 [Gating] SW mode calibration
1498 23:07:14.121275 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1499 23:07:14.124545 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1500 23:07:14.131509 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1501 23:07:14.134759 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1502 23:07:14.137894 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1503 23:07:14.144337 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1504 23:07:14.147683 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1505 23:07:14.150891 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1506 23:07:14.157457 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1507 23:07:14.161015 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1508 23:07:14.164295 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1509 23:07:14.170815 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1510 23:07:14.174232 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1511 23:07:14.177846 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1512 23:07:14.181043 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1513 23:07:14.187474 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1514 23:07:14.190871 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1515 23:07:14.194236 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1516 23:07:14.201240 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1517 23:07:14.204530 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1518 23:07:14.207783 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1519 23:07:14.214267 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 23:07:14.217881 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 23:07:14.221262 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 23:07:14.228080 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 23:07:14.231459 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 23:07:14.234641 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 23:07:14.241256 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 23:07:14.244556 0 9 8 | B1->B0 | 2727 2626 | 1 1 | (1 1) (1 1)
1527 23:07:14.247908 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1528 23:07:14.254724 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1529 23:07:14.258018 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1530 23:07:14.261570 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1531 23:07:14.267959 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1532 23:07:14.271548 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1533 23:07:14.274355 0 10 4 | B1->B0 | 3434 3434 | 0 1 | (0 1) (1 1)
1534 23:07:14.281046 0 10 8 | B1->B0 | 2e2e 2a2a | 0 0 | (0 1) (0 1)
1535 23:07:14.284909 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 23:07:14.287646 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 23:07:14.291128 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 23:07:14.297642 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 23:07:14.301009 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 23:07:14.304404 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 23:07:14.311095 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1542 23:07:14.314131 0 11 8 | B1->B0 | 3434 3636 | 0 0 | (1 1) (1 1)
1543 23:07:14.318022 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1544 23:07:14.324129 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1545 23:07:14.327763 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1546 23:07:14.331179 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1547 23:07:14.337791 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1548 23:07:14.341180 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1549 23:07:14.344033 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1550 23:07:14.351172 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1551 23:07:14.354421 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1552 23:07:14.357623 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1553 23:07:14.364539 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1554 23:07:14.367874 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1555 23:07:14.371481 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1556 23:07:14.375278 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1557 23:07:14.381766 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1558 23:07:14.384766 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1559 23:07:14.388376 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1560 23:07:14.394582 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1561 23:07:14.397790 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1562 23:07:14.401638 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1563 23:07:14.407842 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1564 23:07:14.411536 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1565 23:07:14.414567 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1566 23:07:14.421379 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1567 23:07:14.424491 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1568 23:07:14.428176 Total UI for P1: 0, mck2ui 16
1569 23:07:14.431134 best dqsien dly found for B0: ( 0, 14, 6)
1570 23:07:14.434394 Total UI for P1: 0, mck2ui 16
1571 23:07:14.438215 best dqsien dly found for B1: ( 0, 14, 6)
1572 23:07:14.441328 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1573 23:07:14.444515 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1574 23:07:14.444678
1575 23:07:14.447894 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1576 23:07:14.451429 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1577 23:07:14.454501 [Gating] SW calibration Done
1578 23:07:14.454623 ==
1579 23:07:14.457740 Dram Type= 6, Freq= 0, CH_1, rank 0
1580 23:07:14.461792 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1581 23:07:14.462239 ==
1582 23:07:14.465031 RX Vref Scan: 0
1583 23:07:14.465672
1584 23:07:14.468265 RX Vref 0 -> 0, step: 1
1585 23:07:14.468870
1586 23:07:14.469324 RX Delay -130 -> 252, step: 16
1587 23:07:14.474859 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1588 23:07:14.478156 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1589 23:07:14.481388 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1590 23:07:14.485133 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1591 23:07:14.488230 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1592 23:07:14.494668 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1593 23:07:14.498376 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1594 23:07:14.501341 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1595 23:07:14.504568 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1596 23:07:14.507994 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1597 23:07:14.514604 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1598 23:07:14.518076 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1599 23:07:14.521470 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1600 23:07:14.524625 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1601 23:07:14.528246 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1602 23:07:14.534587 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1603 23:07:14.535082 ==
1604 23:07:14.538183 Dram Type= 6, Freq= 0, CH_1, rank 0
1605 23:07:14.541344 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1606 23:07:14.541943 ==
1607 23:07:14.542377 DQS Delay:
1608 23:07:14.544531 DQS0 = 0, DQS1 = 0
1609 23:07:14.545187 DQM Delay:
1610 23:07:14.547952 DQM0 = 82, DQM1 = 75
1611 23:07:14.548557 DQ Delay:
1612 23:07:14.551113 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1613 23:07:14.554595 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =77
1614 23:07:14.557986 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
1615 23:07:14.561255 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1616 23:07:14.561885
1617 23:07:14.562447
1618 23:07:14.562983 ==
1619 23:07:14.564656 Dram Type= 6, Freq= 0, CH_1, rank 0
1620 23:07:14.567781 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1621 23:07:14.568276 ==
1622 23:07:14.571087
1623 23:07:14.571592
1624 23:07:14.571929 TX Vref Scan disable
1625 23:07:14.574550 == TX Byte 0 ==
1626 23:07:14.577918 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1627 23:07:14.581264 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1628 23:07:14.584913 == TX Byte 1 ==
1629 23:07:14.588215 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1630 23:07:14.591324 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1631 23:07:14.591744 ==
1632 23:07:14.595267 Dram Type= 6, Freq= 0, CH_1, rank 0
1633 23:07:14.601065 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1634 23:07:14.601718 ==
1635 23:07:14.613037 TX Vref=22, minBit 0, minWin=27, winSum=439
1636 23:07:14.616277 TX Vref=24, minBit 0, minWin=27, winSum=440
1637 23:07:14.619867 TX Vref=26, minBit 1, minWin=27, winSum=442
1638 23:07:14.623426 TX Vref=28, minBit 1, minWin=27, winSum=445
1639 23:07:14.626267 TX Vref=30, minBit 5, minWin=27, winSum=447
1640 23:07:14.629935 TX Vref=32, minBit 0, minWin=27, winSum=444
1641 23:07:14.636439 [TxChooseVref] Worse bit 5, Min win 27, Win sum 447, Final Vref 30
1642 23:07:14.636898
1643 23:07:14.639685 Final TX Range 1 Vref 30
1644 23:07:14.640106
1645 23:07:14.640433 ==
1646 23:07:14.643302 Dram Type= 6, Freq= 0, CH_1, rank 0
1647 23:07:14.646602 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1648 23:07:14.647167 ==
1649 23:07:14.647650
1650 23:07:14.648104
1651 23:07:14.649895 TX Vref Scan disable
1652 23:07:14.653135 == TX Byte 0 ==
1653 23:07:14.656993 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1654 23:07:14.660572 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1655 23:07:14.664225 == TX Byte 1 ==
1656 23:07:14.667532 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1657 23:07:14.671113 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1658 23:07:14.671668
1659 23:07:14.673839 [DATLAT]
1660 23:07:14.674353 Freq=800, CH1 RK0
1661 23:07:14.674697
1662 23:07:14.677236 DATLAT Default: 0xa
1663 23:07:14.677710 0, 0xFFFF, sum = 0
1664 23:07:14.680656 1, 0xFFFF, sum = 0
1665 23:07:14.681183 2, 0xFFFF, sum = 0
1666 23:07:14.683784 3, 0xFFFF, sum = 0
1667 23:07:14.684209 4, 0xFFFF, sum = 0
1668 23:07:14.686931 5, 0xFFFF, sum = 0
1669 23:07:14.687357 6, 0xFFFF, sum = 0
1670 23:07:14.690764 7, 0xFFFF, sum = 0
1671 23:07:14.691193 8, 0xFFFF, sum = 0
1672 23:07:14.694042 9, 0x0, sum = 1
1673 23:07:14.694469 10, 0x0, sum = 2
1674 23:07:14.697512 11, 0x0, sum = 3
1675 23:07:14.698044 12, 0x0, sum = 4
1676 23:07:14.700833 best_step = 10
1677 23:07:14.701276
1678 23:07:14.701652 ==
1679 23:07:14.703970 Dram Type= 6, Freq= 0, CH_1, rank 0
1680 23:07:14.707221 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1681 23:07:14.707643 ==
1682 23:07:14.707974 RX Vref Scan: 1
1683 23:07:14.710241
1684 23:07:14.710855 Set Vref Range= 32 -> 127
1685 23:07:14.711439
1686 23:07:14.713564 RX Vref 32 -> 127, step: 1
1687 23:07:14.713991
1688 23:07:14.717260 RX Delay -111 -> 252, step: 8
1689 23:07:14.717809
1690 23:07:14.720305 Set Vref, RX VrefLevel [Byte0]: 32
1691 23:07:14.723967 [Byte1]: 32
1692 23:07:14.724557
1693 23:07:14.726997 Set Vref, RX VrefLevel [Byte0]: 33
1694 23:07:14.730089 [Byte1]: 33
1695 23:07:14.730527
1696 23:07:14.733693 Set Vref, RX VrefLevel [Byte0]: 34
1697 23:07:14.736831 [Byte1]: 34
1698 23:07:14.740895
1699 23:07:14.741311 Set Vref, RX VrefLevel [Byte0]: 35
1700 23:07:14.744148 [Byte1]: 35
1701 23:07:14.748755
1702 23:07:14.749172 Set Vref, RX VrefLevel [Byte0]: 36
1703 23:07:14.751887 [Byte1]: 36
1704 23:07:14.756220
1705 23:07:14.756639 Set Vref, RX VrefLevel [Byte0]: 37
1706 23:07:14.759531 [Byte1]: 37
1707 23:07:14.764144
1708 23:07:14.764778 Set Vref, RX VrefLevel [Byte0]: 38
1709 23:07:14.767210 [Byte1]: 38
1710 23:07:14.771917
1711 23:07:14.772480 Set Vref, RX VrefLevel [Byte0]: 39
1712 23:07:14.775606 [Byte1]: 39
1713 23:07:14.779372
1714 23:07:14.779791 Set Vref, RX VrefLevel [Byte0]: 40
1715 23:07:14.782724 [Byte1]: 40
1716 23:07:14.786921
1717 23:07:14.787464 Set Vref, RX VrefLevel [Byte0]: 41
1718 23:07:14.790250 [Byte1]: 41
1719 23:07:14.794809
1720 23:07:14.795251 Set Vref, RX VrefLevel [Byte0]: 42
1721 23:07:14.797873 [Byte1]: 42
1722 23:07:14.802765
1723 23:07:14.803261 Set Vref, RX VrefLevel [Byte0]: 43
1724 23:07:14.805786 [Byte1]: 43
1725 23:07:14.809909
1726 23:07:14.810425 Set Vref, RX VrefLevel [Byte0]: 44
1727 23:07:14.813146 [Byte1]: 44
1728 23:07:14.817615
1729 23:07:14.818037 Set Vref, RX VrefLevel [Byte0]: 45
1730 23:07:14.821035 [Byte1]: 45
1731 23:07:14.825323
1732 23:07:14.825819 Set Vref, RX VrefLevel [Byte0]: 46
1733 23:07:14.828734 [Byte1]: 46
1734 23:07:14.832875
1735 23:07:14.833385 Set Vref, RX VrefLevel [Byte0]: 47
1736 23:07:14.836553 [Byte1]: 47
1737 23:07:14.840964
1738 23:07:14.841510 Set Vref, RX VrefLevel [Byte0]: 48
1739 23:07:14.844346 [Byte1]: 48
1740 23:07:14.848954
1741 23:07:14.849513 Set Vref, RX VrefLevel [Byte0]: 49
1742 23:07:14.851436 [Byte1]: 49
1743 23:07:14.856017
1744 23:07:14.856433 Set Vref, RX VrefLevel [Byte0]: 50
1745 23:07:14.859240 [Byte1]: 50
1746 23:07:14.863654
1747 23:07:14.864173 Set Vref, RX VrefLevel [Byte0]: 51
1748 23:07:14.867546 [Byte1]: 51
1749 23:07:14.871483
1750 23:07:14.871986 Set Vref, RX VrefLevel [Byte0]: 52
1751 23:07:14.874731 [Byte1]: 52
1752 23:07:14.878646
1753 23:07:14.879077 Set Vref, RX VrefLevel [Byte0]: 53
1754 23:07:14.882030 [Byte1]: 53
1755 23:07:14.887221
1756 23:07:14.887735 Set Vref, RX VrefLevel [Byte0]: 54
1757 23:07:14.890386 [Byte1]: 54
1758 23:07:14.894046
1759 23:07:14.894599 Set Vref, RX VrefLevel [Byte0]: 55
1760 23:07:14.897891 [Byte1]: 55
1761 23:07:14.902059
1762 23:07:14.902572 Set Vref, RX VrefLevel [Byte0]: 56
1763 23:07:14.905157 [Byte1]: 56
1764 23:07:14.909616
1765 23:07:14.910177 Set Vref, RX VrefLevel [Byte0]: 57
1766 23:07:14.912803 [Byte1]: 57
1767 23:07:14.917103
1768 23:07:14.917665 Set Vref, RX VrefLevel [Byte0]: 58
1769 23:07:14.920756 [Byte1]: 58
1770 23:07:14.924740
1771 23:07:14.925156 Set Vref, RX VrefLevel [Byte0]: 59
1772 23:07:14.928159 [Byte1]: 59
1773 23:07:14.932297
1774 23:07:14.932785 Set Vref, RX VrefLevel [Byte0]: 60
1775 23:07:14.935417 [Byte1]: 60
1776 23:07:14.939904
1777 23:07:14.940323 Set Vref, RX VrefLevel [Byte0]: 61
1778 23:07:14.943815 [Byte1]: 61
1779 23:07:14.947662
1780 23:07:14.948099 Set Vref, RX VrefLevel [Byte0]: 62
1781 23:07:14.951348 [Byte1]: 62
1782 23:07:14.955266
1783 23:07:14.955682 Set Vref, RX VrefLevel [Byte0]: 63
1784 23:07:14.958362 [Byte1]: 63
1785 23:07:14.962572
1786 23:07:14.963063 Set Vref, RX VrefLevel [Byte0]: 64
1787 23:07:14.966453 [Byte1]: 64
1788 23:07:14.970887
1789 23:07:14.971324 Set Vref, RX VrefLevel [Byte0]: 65
1790 23:07:14.974076 [Byte1]: 65
1791 23:07:14.978422
1792 23:07:14.978870 Set Vref, RX VrefLevel [Byte0]: 66
1793 23:07:14.981759 [Byte1]: 66
1794 23:07:14.985669
1795 23:07:14.986262 Set Vref, RX VrefLevel [Byte0]: 67
1796 23:07:14.989047 [Byte1]: 67
1797 23:07:14.993680
1798 23:07:14.994111 Set Vref, RX VrefLevel [Byte0]: 68
1799 23:07:14.996724 [Byte1]: 68
1800 23:07:15.001577
1801 23:07:15.002103 Set Vref, RX VrefLevel [Byte0]: 69
1802 23:07:15.004815 [Byte1]: 69
1803 23:07:15.008647
1804 23:07:15.009208 Set Vref, RX VrefLevel [Byte0]: 70
1805 23:07:15.011988 [Byte1]: 70
1806 23:07:15.016178
1807 23:07:15.016740 Set Vref, RX VrefLevel [Byte0]: 71
1808 23:07:15.019663 [Byte1]: 71
1809 23:07:15.024138
1810 23:07:15.024556 Set Vref, RX VrefLevel [Byte0]: 72
1811 23:07:15.027255 [Byte1]: 72
1812 23:07:15.031746
1813 23:07:15.032191 Set Vref, RX VrefLevel [Byte0]: 73
1814 23:07:15.035078 [Byte1]: 73
1815 23:07:15.039398
1816 23:07:15.039840 Set Vref, RX VrefLevel [Byte0]: 74
1817 23:07:15.042490 [Byte1]: 74
1818 23:07:15.046932
1819 23:07:15.047512 Set Vref, RX VrefLevel [Byte0]: 75
1820 23:07:15.050315 [Byte1]: 75
1821 23:07:15.054367
1822 23:07:15.054787 Final RX Vref Byte 0 = 57 to rank0
1823 23:07:15.057869 Final RX Vref Byte 1 = 57 to rank0
1824 23:07:15.061205 Final RX Vref Byte 0 = 57 to rank1
1825 23:07:15.064852 Final RX Vref Byte 1 = 57 to rank1==
1826 23:07:15.067802 Dram Type= 6, Freq= 0, CH_1, rank 0
1827 23:07:15.074273 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1828 23:07:15.074748 ==
1829 23:07:15.075091 DQS Delay:
1830 23:07:15.075403 DQS0 = 0, DQS1 = 0
1831 23:07:15.077703 DQM Delay:
1832 23:07:15.078126 DQM0 = 81, DQM1 = 71
1833 23:07:15.080856 DQ Delay:
1834 23:07:15.084152 DQ0 =88, DQ1 =76, DQ2 =72, DQ3 =76
1835 23:07:15.087474 DQ4 =80, DQ5 =92, DQ6 =92, DQ7 =76
1836 23:07:15.091491 DQ8 =56, DQ9 =64, DQ10 =72, DQ11 =68
1837 23:07:15.094756 DQ12 =80, DQ13 =76, DQ14 =76, DQ15 =76
1838 23:07:15.095178
1839 23:07:15.095511
1840 23:07:15.101090 [DQSOSCAuto] RK0, (LSB)MR18= 0x111b, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 405 ps
1841 23:07:15.104412 CH1 RK0: MR19=606, MR18=111B
1842 23:07:15.111024 CH1_RK0: MR19=0x606, MR18=0x111B, DQSOSC=403, MR23=63, INC=90, DEC=60
1843 23:07:15.111617
1844 23:07:15.114454 ----->DramcWriteLeveling(PI) begin...
1845 23:07:15.114994 ==
1846 23:07:15.117706 Dram Type= 6, Freq= 0, CH_1, rank 1
1847 23:07:15.121427 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1848 23:07:15.121955 ==
1849 23:07:15.124787 Write leveling (Byte 0): 26 => 26
1850 23:07:15.128040 Write leveling (Byte 1): 28 => 28
1851 23:07:15.131156 DramcWriteLeveling(PI) end<-----
1852 23:07:15.131600
1853 23:07:15.132050 ==
1854 23:07:15.134684 Dram Type= 6, Freq= 0, CH_1, rank 1
1855 23:07:15.137543 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1856 23:07:15.137981 ==
1857 23:07:15.141419 [Gating] SW mode calibration
1858 23:07:15.147733 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1859 23:07:15.154377 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1860 23:07:15.157812 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1861 23:07:15.160995 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1862 23:07:15.167541 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1863 23:07:15.170890 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1864 23:07:15.174371 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1865 23:07:15.181073 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1866 23:07:15.184311 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1867 23:07:15.187833 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1868 23:07:15.194800 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1869 23:07:15.197757 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1870 23:07:15.200995 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1871 23:07:15.207305 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1872 23:07:15.211116 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1873 23:07:15.214191 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 23:07:15.220519 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 23:07:15.224100 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 23:07:15.227699 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1877 23:07:15.234118 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1878 23:07:15.237306 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 23:07:15.240730 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 23:07:15.247495 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 23:07:15.250756 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 23:07:15.254004 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 23:07:15.257443 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 23:07:15.263784 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 23:07:15.266940 0 9 4 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
1886 23:07:15.270715 0 9 8 | B1->B0 | 2c2c 3434 | 1 1 | (1 1) (1 1)
1887 23:07:15.276966 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1888 23:07:15.280371 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1889 23:07:15.283743 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1890 23:07:15.290485 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1891 23:07:15.294075 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1892 23:07:15.296763 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1893 23:07:15.303760 0 10 4 | B1->B0 | 3131 2d2d | 1 0 | (0 0) (0 1)
1894 23:07:15.306779 0 10 8 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1895 23:07:15.310212 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 23:07:15.317000 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1897 23:07:15.320320 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1898 23:07:15.323428 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1899 23:07:15.329954 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1900 23:07:15.333367 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1901 23:07:15.337213 0 11 4 | B1->B0 | 2a2a 3737 | 1 0 | (0 0) (0 0)
1902 23:07:15.343641 0 11 8 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
1903 23:07:15.346802 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1904 23:07:15.350478 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1905 23:07:15.356930 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1906 23:07:15.359968 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1907 23:07:15.363562 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1908 23:07:15.370478 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1909 23:07:15.373924 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1910 23:07:15.377147 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1911 23:07:15.380767 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1912 23:07:15.387446 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1913 23:07:15.390345 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1914 23:07:15.393956 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1915 23:07:15.400350 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1916 23:07:15.404259 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1917 23:07:15.407244 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1918 23:07:15.413596 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1919 23:07:15.417401 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1920 23:07:15.420452 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1921 23:07:15.427067 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1922 23:07:15.430314 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1923 23:07:15.433862 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1924 23:07:15.440876 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1925 23:07:15.443964 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1926 23:07:15.447277 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1927 23:07:15.450619 Total UI for P1: 0, mck2ui 16
1928 23:07:15.453460 best dqsien dly found for B0: ( 0, 14, 4)
1929 23:07:15.460542 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1930 23:07:15.460969 Total UI for P1: 0, mck2ui 16
1931 23:07:15.463852 best dqsien dly found for B1: ( 0, 14, 8)
1932 23:07:15.470654 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1933 23:07:15.474467 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1934 23:07:15.475011
1935 23:07:15.477760 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1936 23:07:15.480994 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1937 23:07:15.484195 [Gating] SW calibration Done
1938 23:07:15.484721 ==
1939 23:07:15.487615 Dram Type= 6, Freq= 0, CH_1, rank 1
1940 23:07:15.490595 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1941 23:07:15.491037 ==
1942 23:07:15.493677 RX Vref Scan: 0
1943 23:07:15.494106
1944 23:07:15.494443 RX Vref 0 -> 0, step: 1
1945 23:07:15.494799
1946 23:07:15.497265 RX Delay -130 -> 252, step: 16
1947 23:07:15.500539 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1948 23:07:15.506690 iDelay=222, Bit 1, Center 69 (-50 ~ 189) 240
1949 23:07:15.510496 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1950 23:07:15.513450 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1951 23:07:15.517070 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1952 23:07:15.520307 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1953 23:07:15.523985 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1954 23:07:15.530356 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1955 23:07:15.533974 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1956 23:07:15.537208 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1957 23:07:15.540435 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1958 23:07:15.543725 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1959 23:07:15.550751 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1960 23:07:15.554138 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1961 23:07:15.557225 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1962 23:07:15.560572 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1963 23:07:15.561103 ==
1964 23:07:15.563737 Dram Type= 6, Freq= 0, CH_1, rank 1
1965 23:07:15.570796 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1966 23:07:15.571372 ==
1967 23:07:15.571750 DQS Delay:
1968 23:07:15.573847 DQS0 = 0, DQS1 = 0
1969 23:07:15.574337 DQM Delay:
1970 23:07:15.574709 DQM0 = 80, DQM1 = 74
1971 23:07:15.577102 DQ Delay:
1972 23:07:15.580341 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =77
1973 23:07:15.584272 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1974 23:07:15.587446 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1975 23:07:15.590337 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1976 23:07:15.590768
1977 23:07:15.591104
1978 23:07:15.591413 ==
1979 23:07:15.593445 Dram Type= 6, Freq= 0, CH_1, rank 1
1980 23:07:15.597271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1981 23:07:15.597735 ==
1982 23:07:15.598078
1983 23:07:15.598390
1984 23:07:15.600302 TX Vref Scan disable
1985 23:07:15.600727 == TX Byte 0 ==
1986 23:07:15.607130 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1987 23:07:15.610461 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1988 23:07:15.610995 == TX Byte 1 ==
1989 23:07:15.616955 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1990 23:07:15.620568 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1991 23:07:15.621096 ==
1992 23:07:15.623781 Dram Type= 6, Freq= 0, CH_1, rank 1
1993 23:07:15.626840 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1994 23:07:15.627269 ==
1995 23:07:15.640703 TX Vref=22, minBit 1, minWin=28, winSum=452
1996 23:07:15.644557 TX Vref=24, minBit 1, minWin=28, winSum=454
1997 23:07:15.647500 TX Vref=26, minBit 0, minWin=28, winSum=458
1998 23:07:15.651148 TX Vref=28, minBit 1, minWin=28, winSum=462
1999 23:07:15.654092 TX Vref=30, minBit 1, minWin=28, winSum=462
2000 23:07:15.657944 TX Vref=32, minBit 0, minWin=28, winSum=463
2001 23:07:15.664321 [TxChooseVref] Worse bit 0, Min win 28, Win sum 463, Final Vref 32
2002 23:07:15.664838
2003 23:07:15.668413 Final TX Range 1 Vref 32
2004 23:07:15.668944
2005 23:07:15.669282 ==
2006 23:07:15.671398 Dram Type= 6, Freq= 0, CH_1, rank 1
2007 23:07:15.674430 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2008 23:07:15.674982 ==
2009 23:07:15.675329
2010 23:07:15.677586
2011 23:07:15.678011 TX Vref Scan disable
2012 23:07:15.681444 == TX Byte 0 ==
2013 23:07:15.684567 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
2014 23:07:15.688228 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
2015 23:07:15.691199 == TX Byte 1 ==
2016 23:07:15.694520 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2017 23:07:15.698118 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2018 23:07:15.700866
2019 23:07:15.701327 [DATLAT]
2020 23:07:15.701771 Freq=800, CH1 RK1
2021 23:07:15.702126
2022 23:07:15.704255 DATLAT Default: 0xa
2023 23:07:15.704705 0, 0xFFFF, sum = 0
2024 23:07:15.707380 1, 0xFFFF, sum = 0
2025 23:07:15.707827 2, 0xFFFF, sum = 0
2026 23:07:15.710609 3, 0xFFFF, sum = 0
2027 23:07:15.711103 4, 0xFFFF, sum = 0
2028 23:07:15.713879 5, 0xFFFF, sum = 0
2029 23:07:15.717928 6, 0xFFFF, sum = 0
2030 23:07:15.718518 7, 0xFFFF, sum = 0
2031 23:07:15.721129 8, 0xFFFF, sum = 0
2032 23:07:15.721751 9, 0x0, sum = 1
2033 23:07:15.722298 10, 0x0, sum = 2
2034 23:07:15.724129 11, 0x0, sum = 3
2035 23:07:15.724675 12, 0x0, sum = 4
2036 23:07:15.727137 best_step = 10
2037 23:07:15.727685
2038 23:07:15.728182 ==
2039 23:07:15.730928 Dram Type= 6, Freq= 0, CH_1, rank 1
2040 23:07:15.734219 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2041 23:07:15.734673 ==
2042 23:07:15.737329 RX Vref Scan: 0
2043 23:07:15.737826
2044 23:07:15.738168 RX Vref 0 -> 0, step: 1
2045 23:07:15.738483
2046 23:07:15.740791 RX Delay -95 -> 252, step: 8
2047 23:07:15.747594 iDelay=209, Bit 0, Center 80 (-39 ~ 200) 240
2048 23:07:15.750751 iDelay=209, Bit 1, Center 72 (-47 ~ 192) 240
2049 23:07:15.754293 iDelay=209, Bit 2, Center 64 (-55 ~ 184) 240
2050 23:07:15.757207 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
2051 23:07:15.760870 iDelay=209, Bit 4, Center 76 (-47 ~ 200) 248
2052 23:07:15.767473 iDelay=209, Bit 5, Center 88 (-31 ~ 208) 240
2053 23:07:15.770837 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
2054 23:07:15.773980 iDelay=209, Bit 7, Center 76 (-47 ~ 200) 248
2055 23:07:15.777235 iDelay=209, Bit 8, Center 60 (-63 ~ 184) 248
2056 23:07:15.780691 iDelay=209, Bit 9, Center 64 (-55 ~ 184) 240
2057 23:07:15.787504 iDelay=209, Bit 10, Center 76 (-47 ~ 200) 248
2058 23:07:15.790383 iDelay=209, Bit 11, Center 68 (-55 ~ 192) 248
2059 23:07:15.793785 iDelay=209, Bit 12, Center 80 (-39 ~ 200) 240
2060 23:07:15.796989 iDelay=209, Bit 13, Center 80 (-39 ~ 200) 240
2061 23:07:15.803531 iDelay=209, Bit 14, Center 84 (-31 ~ 200) 232
2062 23:07:15.807122 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
2063 23:07:15.807358 ==
2064 23:07:15.810453 Dram Type= 6, Freq= 0, CH_1, rank 1
2065 23:07:15.813732 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2066 23:07:15.813963 ==
2067 23:07:15.814167 DQS Delay:
2068 23:07:15.817255 DQS0 = 0, DQS1 = 0
2069 23:07:15.817578 DQM Delay:
2070 23:07:15.820389 DQM0 = 77, DQM1 = 74
2071 23:07:15.820693 DQ Delay:
2072 23:07:15.823658 DQ0 =80, DQ1 =72, DQ2 =64, DQ3 =72
2073 23:07:15.826873 DQ4 =76, DQ5 =88, DQ6 =88, DQ7 =76
2074 23:07:15.830424 DQ8 =60, DQ9 =64, DQ10 =76, DQ11 =68
2075 23:07:15.834278 DQ12 =80, DQ13 =80, DQ14 =84, DQ15 =80
2076 23:07:15.834506
2077 23:07:15.834687
2078 23:07:15.843857 [DQSOSCAuto] RK1, (LSB)MR18= 0x263e, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 400 ps
2079 23:07:15.844089 CH1 RK1: MR19=606, MR18=263E
2080 23:07:15.850436 CH1_RK1: MR19=0x606, MR18=0x263E, DQSOSC=394, MR23=63, INC=95, DEC=63
2081 23:07:15.853399 [RxdqsGatingPostProcess] freq 800
2082 23:07:15.860415 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2083 23:07:15.863711 Pre-setting of DQS Precalculation
2084 23:07:15.866744 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2085 23:07:15.873942 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2086 23:07:15.880090 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2087 23:07:15.880328
2088 23:07:15.883456
2089 23:07:15.883685 [Calibration Summary] 1600 Mbps
2090 23:07:15.886771 CH 0, Rank 0
2091 23:07:15.887001 SW Impedance : PASS
2092 23:07:15.890403 DUTY Scan : NO K
2093 23:07:15.893418 ZQ Calibration : PASS
2094 23:07:15.893684 Jitter Meter : NO K
2095 23:07:15.897169 CBT Training : PASS
2096 23:07:15.900604 Write leveling : PASS
2097 23:07:15.900906 RX DQS gating : PASS
2098 23:07:15.903666 RX DQ/DQS(RDDQC) : PASS
2099 23:07:15.906933 TX DQ/DQS : PASS
2100 23:07:15.907218 RX DATLAT : PASS
2101 23:07:15.910222 RX DQ/DQS(Engine): PASS
2102 23:07:15.910449 TX OE : NO K
2103 23:07:15.913924 All Pass.
2104 23:07:15.914153
2105 23:07:15.914332 CH 0, Rank 1
2106 23:07:15.916856 SW Impedance : PASS
2107 23:07:15.917116 DUTY Scan : NO K
2108 23:07:15.920205 ZQ Calibration : PASS
2109 23:07:15.923669 Jitter Meter : NO K
2110 23:07:15.923986 CBT Training : PASS
2111 23:07:15.927196 Write leveling : PASS
2112 23:07:15.930151 RX DQS gating : PASS
2113 23:07:15.930380 RX DQ/DQS(RDDQC) : PASS
2114 23:07:15.933446 TX DQ/DQS : PASS
2115 23:07:15.936961 RX DATLAT : PASS
2116 23:07:15.937283 RX DQ/DQS(Engine): PASS
2117 23:07:15.939891 TX OE : NO K
2118 23:07:15.940172 All Pass.
2119 23:07:15.940422
2120 23:07:15.943782 CH 1, Rank 0
2121 23:07:15.944010 SW Impedance : PASS
2122 23:07:15.946891 DUTY Scan : NO K
2123 23:07:15.949900 ZQ Calibration : PASS
2124 23:07:15.949982 Jitter Meter : NO K
2125 23:07:15.953228 CBT Training : PASS
2126 23:07:15.956873 Write leveling : PASS
2127 23:07:15.956956 RX DQS gating : PASS
2128 23:07:15.960034 RX DQ/DQS(RDDQC) : PASS
2129 23:07:15.963064 TX DQ/DQS : PASS
2130 23:07:15.963147 RX DATLAT : PASS
2131 23:07:15.967056 RX DQ/DQS(Engine): PASS
2132 23:07:15.967138 TX OE : NO K
2133 23:07:15.970117 All Pass.
2134 23:07:15.970200
2135 23:07:15.970264 CH 1, Rank 1
2136 23:07:15.973108 SW Impedance : PASS
2137 23:07:15.973190 DUTY Scan : NO K
2138 23:07:15.976352 ZQ Calibration : PASS
2139 23:07:15.979889 Jitter Meter : NO K
2140 23:07:15.979971 CBT Training : PASS
2141 23:07:15.983388 Write leveling : PASS
2142 23:07:15.986602 RX DQS gating : PASS
2143 23:07:15.986685 RX DQ/DQS(RDDQC) : PASS
2144 23:07:15.990081 TX DQ/DQS : PASS
2145 23:07:15.993189 RX DATLAT : PASS
2146 23:07:15.993271 RX DQ/DQS(Engine): PASS
2147 23:07:15.996285 TX OE : NO K
2148 23:07:15.996368 All Pass.
2149 23:07:15.996433
2150 23:07:15.999857 DramC Write-DBI off
2151 23:07:16.003225 PER_BANK_REFRESH: Hybrid Mode
2152 23:07:16.003307 TX_TRACKING: ON
2153 23:07:16.006373 [GetDramInforAfterCalByMRR] Vendor 6.
2154 23:07:16.009921 [GetDramInforAfterCalByMRR] Revision 606.
2155 23:07:16.013345 [GetDramInforAfterCalByMRR] Revision 2 0.
2156 23:07:16.016793 MR0 0x3b3b
2157 23:07:16.016878 MR8 0x5151
2158 23:07:16.019962 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2159 23:07:16.020047
2160 23:07:16.020113 MR0 0x3b3b
2161 23:07:16.022905 MR8 0x5151
2162 23:07:16.026713 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2163 23:07:16.026798
2164 23:07:16.036412 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2165 23:07:16.039837 [FAST_K] Save calibration result to emmc
2166 23:07:16.043228 [FAST_K] Save calibration result to emmc
2167 23:07:16.043314 dram_init: config_dvfs: 1
2168 23:07:16.050064 dramc_set_vcore_voltage set vcore to 662500
2169 23:07:16.050148 Read voltage for 1200, 2
2170 23:07:16.053333 Vio18 = 0
2171 23:07:16.053416 Vcore = 662500
2172 23:07:16.053506 Vdram = 0
2173 23:07:16.053583 Vddq = 0
2174 23:07:16.056777 Vmddr = 0
2175 23:07:16.059997 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2176 23:07:16.066393 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2177 23:07:16.070093 MEM_TYPE=3, freq_sel=15
2178 23:07:16.070175 sv_algorithm_assistance_LP4_1600
2179 23:07:16.076625 ============ PULL DRAM RESETB DOWN ============
2180 23:07:16.079837 ========== PULL DRAM RESETB DOWN end =========
2181 23:07:16.083409 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2182 23:07:16.086470 ===================================
2183 23:07:16.089867 LPDDR4 DRAM CONFIGURATION
2184 23:07:16.093013 ===================================
2185 23:07:16.096385 EX_ROW_EN[0] = 0x0
2186 23:07:16.096482 EX_ROW_EN[1] = 0x0
2187 23:07:16.099812 LP4Y_EN = 0x0
2188 23:07:16.099894 WORK_FSP = 0x0
2189 23:07:16.102806 WL = 0x4
2190 23:07:16.102889 RL = 0x4
2191 23:07:16.106240 BL = 0x2
2192 23:07:16.106354 RPST = 0x0
2193 23:07:16.109633 RD_PRE = 0x0
2194 23:07:16.109715 WR_PRE = 0x1
2195 23:07:16.113264 WR_PST = 0x0
2196 23:07:16.113376 DBI_WR = 0x0
2197 23:07:16.116612 DBI_RD = 0x0
2198 23:07:16.116763 OTF = 0x1
2199 23:07:16.119570 ===================================
2200 23:07:16.122880 ===================================
2201 23:07:16.126761 ANA top config
2202 23:07:16.129448 ===================================
2203 23:07:16.133286 DLL_ASYNC_EN = 0
2204 23:07:16.133411 ALL_SLAVE_EN = 0
2205 23:07:16.136160 NEW_RANK_MODE = 1
2206 23:07:16.139813 DLL_IDLE_MODE = 1
2207 23:07:16.142918 LP45_APHY_COMB_EN = 1
2208 23:07:16.143001 TX_ODT_DIS = 1
2209 23:07:16.146282 NEW_8X_MODE = 1
2210 23:07:16.149677 ===================================
2211 23:07:16.153277 ===================================
2212 23:07:16.156313 data_rate = 2400
2213 23:07:16.159929 CKR = 1
2214 23:07:16.163236 DQ_P2S_RATIO = 8
2215 23:07:16.166428 ===================================
2216 23:07:16.169722 CA_P2S_RATIO = 8
2217 23:07:16.169822 DQ_CA_OPEN = 0
2218 23:07:16.172860 DQ_SEMI_OPEN = 0
2219 23:07:16.176566 CA_SEMI_OPEN = 0
2220 23:07:16.179598 CA_FULL_RATE = 0
2221 23:07:16.183064 DQ_CKDIV4_EN = 0
2222 23:07:16.186386 CA_CKDIV4_EN = 0
2223 23:07:16.186469 CA_PREDIV_EN = 0
2224 23:07:16.189722 PH8_DLY = 17
2225 23:07:16.193221 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2226 23:07:16.196525 DQ_AAMCK_DIV = 4
2227 23:07:16.199972 CA_AAMCK_DIV = 4
2228 23:07:16.200054 CA_ADMCK_DIV = 4
2229 23:07:16.203227 DQ_TRACK_CA_EN = 0
2230 23:07:16.206435 CA_PICK = 1200
2231 23:07:16.209833 CA_MCKIO = 1200
2232 23:07:16.213033 MCKIO_SEMI = 0
2233 23:07:16.216644 PLL_FREQ = 2366
2234 23:07:16.219868 DQ_UI_PI_RATIO = 32
2235 23:07:16.223195 CA_UI_PI_RATIO = 0
2236 23:07:16.226503 ===================================
2237 23:07:16.226628 ===================================
2238 23:07:16.230030 memory_type:LPDDR4
2239 23:07:16.233400 GP_NUM : 10
2240 23:07:16.233555 SRAM_EN : 1
2241 23:07:16.237046 MD32_EN : 0
2242 23:07:16.240199 ===================================
2243 23:07:16.243729 [ANA_INIT] >>>>>>>>>>>>>>
2244 23:07:16.246737 <<<<<< [CONFIGURE PHASE]: ANA_TX
2245 23:07:16.249819 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2246 23:07:16.253590 ===================================
2247 23:07:16.254016 data_rate = 2400,PCW = 0X5b00
2248 23:07:16.256683 ===================================
2249 23:07:16.260438 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2250 23:07:16.267228 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2251 23:07:16.273576 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2252 23:07:16.277308 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2253 23:07:16.280455 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2254 23:07:16.283753 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2255 23:07:16.287041 [ANA_INIT] flow start
2256 23:07:16.287467 [ANA_INIT] PLL >>>>>>>>
2257 23:07:16.290249 [ANA_INIT] PLL <<<<<<<<
2258 23:07:16.301892 [ANA_INIT] MIDPI >>>>>>>>
2259 23:07:16.302522 [ANA_INIT] MIDPI <<<<<<<<
2260 23:07:16.303028 [ANA_INIT] DLL >>>>>>>>
2261 23:07:16.303485 [ANA_INIT] DLL <<<<<<<<
2262 23:07:16.304343 [ANA_INIT] flow end
2263 23:07:16.307220 ============ LP4 DIFF to SE enter ============
2264 23:07:16.310093 ============ LP4 DIFF to SE exit ============
2265 23:07:16.313815 [ANA_INIT] <<<<<<<<<<<<<
2266 23:07:16.316947 [Flow] Enable top DCM control >>>>>
2267 23:07:16.319950 [Flow] Enable top DCM control <<<<<
2268 23:07:16.323986 Enable DLL master slave shuffle
2269 23:07:16.327060 ==============================================================
2270 23:07:16.330199 Gating Mode config
2271 23:07:16.333539 ==============================================================
2272 23:07:16.336985 Config description:
2273 23:07:16.347166 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2274 23:07:16.353612 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2275 23:07:16.356857 SELPH_MODE 0: By rank 1: By Phase
2276 23:07:16.363595 ==============================================================
2277 23:07:16.366947 GAT_TRACK_EN = 1
2278 23:07:16.369964 RX_GATING_MODE = 2
2279 23:07:16.373457 RX_GATING_TRACK_MODE = 2
2280 23:07:16.376862 SELPH_MODE = 1
2281 23:07:16.377165 PICG_EARLY_EN = 1
2282 23:07:16.380113 VALID_LAT_VALUE = 1
2283 23:07:16.386650 ==============================================================
2284 23:07:16.389964 Enter into Gating configuration >>>>
2285 23:07:16.393169 Exit from Gating configuration <<<<
2286 23:07:16.397043 Enter into DVFS_PRE_config >>>>>
2287 23:07:16.407035 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2288 23:07:16.410463 Exit from DVFS_PRE_config <<<<<
2289 23:07:16.413728 Enter into PICG configuration >>>>
2290 23:07:16.416862 Exit from PICG configuration <<<<
2291 23:07:16.420302 [RX_INPUT] configuration >>>>>
2292 23:07:16.423685 [RX_INPUT] configuration <<<<<
2293 23:07:16.427024 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2294 23:07:16.433885 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2295 23:07:16.440364 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2296 23:07:16.446992 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2297 23:07:16.450215 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2298 23:07:16.456848 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2299 23:07:16.460308 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2300 23:07:16.467337 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2301 23:07:16.470453 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2302 23:07:16.473499 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2303 23:07:16.477120 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2304 23:07:16.483667 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2305 23:07:16.486794 ===================================
2306 23:07:16.490142 LPDDR4 DRAM CONFIGURATION
2307 23:07:16.493971 ===================================
2308 23:07:16.494400 EX_ROW_EN[0] = 0x0
2309 23:07:16.497224 EX_ROW_EN[1] = 0x0
2310 23:07:16.497683 LP4Y_EN = 0x0
2311 23:07:16.500533 WORK_FSP = 0x0
2312 23:07:16.501054 WL = 0x4
2313 23:07:16.503620 RL = 0x4
2314 23:07:16.504046 BL = 0x2
2315 23:07:16.507386 RPST = 0x0
2316 23:07:16.507908 RD_PRE = 0x0
2317 23:07:16.510494 WR_PRE = 0x1
2318 23:07:16.510918 WR_PST = 0x0
2319 23:07:16.513997 DBI_WR = 0x0
2320 23:07:16.514522 DBI_RD = 0x0
2321 23:07:16.517000 OTF = 0x1
2322 23:07:16.520389 ===================================
2323 23:07:16.523729 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2324 23:07:16.527008 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2325 23:07:16.533702 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2326 23:07:16.537068 ===================================
2327 23:07:16.537554 LPDDR4 DRAM CONFIGURATION
2328 23:07:16.540160 ===================================
2329 23:07:16.543447 EX_ROW_EN[0] = 0x10
2330 23:07:16.546765 EX_ROW_EN[1] = 0x0
2331 23:07:16.547193 LP4Y_EN = 0x0
2332 23:07:16.550464 WORK_FSP = 0x0
2333 23:07:16.550890 WL = 0x4
2334 23:07:16.553366 RL = 0x4
2335 23:07:16.553815 BL = 0x2
2336 23:07:16.556958 RPST = 0x0
2337 23:07:16.557421 RD_PRE = 0x0
2338 23:07:16.560264 WR_PRE = 0x1
2339 23:07:16.560690 WR_PST = 0x0
2340 23:07:16.563602 DBI_WR = 0x0
2341 23:07:16.564049 DBI_RD = 0x0
2342 23:07:16.566894 OTF = 0x1
2343 23:07:16.570360 ===================================
2344 23:07:16.576783 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2345 23:07:16.577212 ==
2346 23:07:16.579987 Dram Type= 6, Freq= 0, CH_0, rank 0
2347 23:07:16.583501 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2348 23:07:16.583931 ==
2349 23:07:16.586491 [Duty_Offset_Calibration]
2350 23:07:16.586913 B0:2 B1:0 CA:3
2351 23:07:16.587247
2352 23:07:16.590254 [DutyScan_Calibration_Flow] k_type=0
2353 23:07:16.600245
2354 23:07:16.600667 ==CLK 0==
2355 23:07:16.603718 Final CLK duty delay cell = 0
2356 23:07:16.606907 [0] MAX Duty = 5031%(X100), DQS PI = 12
2357 23:07:16.610112 [0] MIN Duty = 4906%(X100), DQS PI = 54
2358 23:07:16.610532 [0] AVG Duty = 4968%(X100)
2359 23:07:16.613810
2360 23:07:16.616890 CH0 CLK Duty spec in!! Max-Min= 125%
2361 23:07:16.620166 [DutyScan_Calibration_Flow] ====Done====
2362 23:07:16.620588
2363 23:07:16.623423 [DutyScan_Calibration_Flow] k_type=1
2364 23:07:16.638762
2365 23:07:16.639311 ==DQS 0 ==
2366 23:07:16.641666 Final DQS duty delay cell = 0
2367 23:07:16.645229 [0] MAX Duty = 5062%(X100), DQS PI = 14
2368 23:07:16.648712 [0] MIN Duty = 4907%(X100), DQS PI = 46
2369 23:07:16.651958 [0] AVG Duty = 4984%(X100)
2370 23:07:16.652377
2371 23:07:16.652708 ==DQS 1 ==
2372 23:07:16.655141 Final DQS duty delay cell = -4
2373 23:07:16.658882 [-4] MAX Duty = 5000%(X100), DQS PI = 36
2374 23:07:16.662036 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2375 23:07:16.665320 [-4] AVG Duty = 4953%(X100)
2376 23:07:16.665777
2377 23:07:16.668728 CH0 DQS 0 Duty spec in!! Max-Min= 155%
2378 23:07:16.669150
2379 23:07:16.671773 CH0 DQS 1 Duty spec in!! Max-Min= 93%
2380 23:07:16.675096 [DutyScan_Calibration_Flow] ====Done====
2381 23:07:16.675511
2382 23:07:16.678678 [DutyScan_Calibration_Flow] k_type=3
2383 23:07:16.696185
2384 23:07:16.696700 ==DQM 0 ==
2385 23:07:16.699717 Final DQM duty delay cell = 0
2386 23:07:16.702986 [0] MAX Duty = 5124%(X100), DQS PI = 12
2387 23:07:16.706166 [0] MIN Duty = 4876%(X100), DQS PI = 0
2388 23:07:16.706701 [0] AVG Duty = 5000%(X100)
2389 23:07:16.709435
2390 23:07:16.709880 ==DQM 1 ==
2391 23:07:16.712732 Final DQM duty delay cell = 4
2392 23:07:16.716545 [4] MAX Duty = 5124%(X100), DQS PI = 50
2393 23:07:16.719591 [4] MIN Duty = 5000%(X100), DQS PI = 12
2394 23:07:16.720105 [4] AVG Duty = 5062%(X100)
2395 23:07:16.722707
2396 23:07:16.726433 CH0 DQM 0 Duty spec in!! Max-Min= 248%
2397 23:07:16.726850
2398 23:07:16.729676 CH0 DQM 1 Duty spec in!! Max-Min= 124%
2399 23:07:16.732924 [DutyScan_Calibration_Flow] ====Done====
2400 23:07:16.733339
2401 23:07:16.736147 [DutyScan_Calibration_Flow] k_type=2
2402 23:07:16.751110
2403 23:07:16.751524 ==DQ 0 ==
2404 23:07:16.754237 Final DQ duty delay cell = -4
2405 23:07:16.757593 [-4] MAX Duty = 5031%(X100), DQS PI = 20
2406 23:07:16.760928 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2407 23:07:16.764306 [-4] AVG Duty = 4969%(X100)
2408 23:07:16.764725
2409 23:07:16.765054 ==DQ 1 ==
2410 23:07:16.767464 Final DQ duty delay cell = -4
2411 23:07:16.771249 [-4] MAX Duty = 5000%(X100), DQS PI = 62
2412 23:07:16.774682 [-4] MIN Duty = 4907%(X100), DQS PI = 16
2413 23:07:16.777594 [-4] AVG Duty = 4953%(X100)
2414 23:07:16.778153
2415 23:07:16.780801 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2416 23:07:16.781221
2417 23:07:16.784154 CH0 DQ 1 Duty spec in!! Max-Min= 93%
2418 23:07:16.787575 [DutyScan_Calibration_Flow] ====Done====
2419 23:07:16.787994 ==
2420 23:07:16.790998 Dram Type= 6, Freq= 0, CH_1, rank 0
2421 23:07:16.794288 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2422 23:07:16.794714 ==
2423 23:07:16.797518 [Duty_Offset_Calibration]
2424 23:07:16.797944 B0:1 B1:-2 CA:0
2425 23:07:16.798270
2426 23:07:16.800585 [DutyScan_Calibration_Flow] k_type=0
2427 23:07:16.811550
2428 23:07:16.812070 ==CLK 0==
2429 23:07:16.814719 Final CLK duty delay cell = 0
2430 23:07:16.818629 [0] MAX Duty = 5031%(X100), DQS PI = 16
2431 23:07:16.821684 [0] MIN Duty = 4844%(X100), DQS PI = 58
2432 23:07:16.822115 [0] AVG Duty = 4937%(X100)
2433 23:07:16.825040
2434 23:07:16.828858 CH1 CLK Duty spec in!! Max-Min= 187%
2435 23:07:16.831718 [DutyScan_Calibration_Flow] ====Done====
2436 23:07:16.832137
2437 23:07:16.834788 [DutyScan_Calibration_Flow] k_type=1
2438 23:07:16.850253
2439 23:07:16.850760 ==DQS 0 ==
2440 23:07:16.853253 Final DQS duty delay cell = -4
2441 23:07:16.857138 [-4] MAX Duty = 5031%(X100), DQS PI = 24
2442 23:07:16.860295 [-4] MIN Duty = 4907%(X100), DQS PI = 2
2443 23:07:16.863736 [-4] AVG Duty = 4969%(X100)
2444 23:07:16.864163
2445 23:07:16.864495 ==DQS 1 ==
2446 23:07:16.866846 Final DQS duty delay cell = 0
2447 23:07:16.870340 [0] MAX Duty = 5093%(X100), DQS PI = 0
2448 23:07:16.873390 [0] MIN Duty = 4844%(X100), DQS PI = 26
2449 23:07:16.876627 [0] AVG Duty = 4968%(X100)
2450 23:07:16.877046
2451 23:07:16.879926 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2452 23:07:16.880459
2453 23:07:16.883206 CH1 DQS 1 Duty spec in!! Max-Min= 249%
2454 23:07:16.886868 [DutyScan_Calibration_Flow] ====Done====
2455 23:07:16.887289
2456 23:07:16.889857 [DutyScan_Calibration_Flow] k_type=3
2457 23:07:16.906873
2458 23:07:16.907387 ==DQM 0 ==
2459 23:07:16.910303 Final DQM duty delay cell = 0
2460 23:07:16.913786 [0] MAX Duty = 5000%(X100), DQS PI = 22
2461 23:07:16.917057 [0] MIN Duty = 4876%(X100), DQS PI = 2
2462 23:07:16.917535 [0] AVG Duty = 4938%(X100)
2463 23:07:16.920142
2464 23:07:16.920579 ==DQM 1 ==
2465 23:07:16.923573 Final DQM duty delay cell = 0
2466 23:07:16.926502 [0] MAX Duty = 5031%(X100), DQS PI = 36
2467 23:07:16.929693 [0] MIN Duty = 4907%(X100), DQS PI = 0
2468 23:07:16.933827 [0] AVG Duty = 4969%(X100)
2469 23:07:16.934361
2470 23:07:16.936789 CH1 DQM 0 Duty spec in!! Max-Min= 124%
2471 23:07:16.937225
2472 23:07:16.940017 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2473 23:07:16.943055 [DutyScan_Calibration_Flow] ====Done====
2474 23:07:16.943489
2475 23:07:16.946487 [DutyScan_Calibration_Flow] k_type=2
2476 23:07:16.963087
2477 23:07:16.963622 ==DQ 0 ==
2478 23:07:16.966452 Final DQ duty delay cell = 0
2479 23:07:16.969685 [0] MAX Duty = 5062%(X100), DQS PI = 18
2480 23:07:16.973564 [0] MIN Duty = 4907%(X100), DQS PI = 56
2481 23:07:16.973992 [0] AVG Duty = 4984%(X100)
2482 23:07:16.976672
2483 23:07:16.977191 ==DQ 1 ==
2484 23:07:16.979792 Final DQ duty delay cell = 0
2485 23:07:16.982948 [0] MAX Duty = 5093%(X100), DQS PI = 20
2486 23:07:16.987048 [0] MIN Duty = 4969%(X100), DQS PI = 26
2487 23:07:16.987467 [0] AVG Duty = 5031%(X100)
2488 23:07:16.987801
2489 23:07:16.990158 CH1 DQ 0 Duty spec in!! Max-Min= 155%
2490 23:07:16.990580
2491 23:07:16.993077 CH1 DQ 1 Duty spec in!! Max-Min= 124%
2492 23:07:16.999822 [DutyScan_Calibration_Flow] ====Done====
2493 23:07:17.003392 nWR fixed to 30
2494 23:07:17.003816 [ModeRegInit_LP4] CH0 RK0
2495 23:07:17.006411 [ModeRegInit_LP4] CH0 RK1
2496 23:07:17.009870 [ModeRegInit_LP4] CH1 RK0
2497 23:07:17.010304 [ModeRegInit_LP4] CH1 RK1
2498 23:07:17.013280 match AC timing 7
2499 23:07:17.016683 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2500 23:07:17.019707 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2501 23:07:17.026361 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2502 23:07:17.029854 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2503 23:07:17.036827 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2504 23:07:17.037349 ==
2505 23:07:17.040116 Dram Type= 6, Freq= 0, CH_0, rank 0
2506 23:07:17.043104 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2507 23:07:17.043531 ==
2508 23:07:17.050125 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2509 23:07:17.053309 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2510 23:07:17.063561 [CA 0] Center 40 (10~71) winsize 62
2511 23:07:17.066700 [CA 1] Center 39 (9~70) winsize 62
2512 23:07:17.069983 [CA 2] Center 36 (6~66) winsize 61
2513 23:07:17.073037 [CA 3] Center 35 (5~66) winsize 62
2514 23:07:17.076785 [CA 4] Center 34 (4~64) winsize 61
2515 23:07:17.080167 [CA 5] Center 33 (3~64) winsize 62
2516 23:07:17.080687
2517 23:07:17.083148 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2518 23:07:17.083585
2519 23:07:17.086758 [CATrainingPosCal] consider 1 rank data
2520 23:07:17.089644 u2DelayCellTimex100 = 270/100 ps
2521 23:07:17.093265 CA0 delay=40 (10~71),Diff = 7 PI (33 cell)
2522 23:07:17.100196 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2523 23:07:17.103058 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2524 23:07:17.106535 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2525 23:07:17.109666 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
2526 23:07:17.113616 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2527 23:07:17.114147
2528 23:07:17.116759 CA PerBit enable=1, Macro0, CA PI delay=33
2529 23:07:17.117205
2530 23:07:17.119949 [CBTSetCACLKResult] CA Dly = 33
2531 23:07:17.120506 CS Dly: 7 (0~38)
2532 23:07:17.123406 ==
2533 23:07:17.123844 Dram Type= 6, Freq= 0, CH_0, rank 1
2534 23:07:17.129782 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2535 23:07:17.130350 ==
2536 23:07:17.133252 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2537 23:07:17.140294 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2538 23:07:17.149190 [CA 0] Center 40 (10~70) winsize 61
2539 23:07:17.152441 [CA 1] Center 40 (10~70) winsize 61
2540 23:07:17.156010 [CA 2] Center 35 (5~66) winsize 62
2541 23:07:17.158940 [CA 3] Center 35 (5~66) winsize 62
2542 23:07:17.162833 [CA 4] Center 34 (3~65) winsize 63
2543 23:07:17.165954 [CA 5] Center 33 (3~64) winsize 62
2544 23:07:17.166395
2545 23:07:17.169151 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2546 23:07:17.169622
2547 23:07:17.172545 [CATrainingPosCal] consider 2 rank data
2548 23:07:17.175697 u2DelayCellTimex100 = 270/100 ps
2549 23:07:17.178875 CA0 delay=40 (10~70),Diff = 7 PI (33 cell)
2550 23:07:17.185934 CA1 delay=40 (10~70),Diff = 7 PI (33 cell)
2551 23:07:17.189195 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2552 23:07:17.192428 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2553 23:07:17.195526 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
2554 23:07:17.199220 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2555 23:07:17.199644
2556 23:07:17.202433 CA PerBit enable=1, Macro0, CA PI delay=33
2557 23:07:17.202854
2558 23:07:17.205876 [CBTSetCACLKResult] CA Dly = 33
2559 23:07:17.209570 CS Dly: 8 (0~40)
2560 23:07:17.209997
2561 23:07:17.212545 ----->DramcWriteLeveling(PI) begin...
2562 23:07:17.212970 ==
2563 23:07:17.215768 Dram Type= 6, Freq= 0, CH_0, rank 0
2564 23:07:17.218790 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2565 23:07:17.219216 ==
2566 23:07:17.222299 Write leveling (Byte 0): 33 => 33
2567 23:07:17.225451 Write leveling (Byte 1): 29 => 29
2568 23:07:17.228834 DramcWriteLeveling(PI) end<-----
2569 23:07:17.229253
2570 23:07:17.229627 ==
2571 23:07:17.232268 Dram Type= 6, Freq= 0, CH_0, rank 0
2572 23:07:17.235630 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2573 23:07:17.236055 ==
2574 23:07:17.239138 [Gating] SW mode calibration
2575 23:07:17.245847 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2576 23:07:17.252581 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2577 23:07:17.255857 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2578 23:07:17.259046 0 15 4 | B1->B0 | 2a2a 3434 | 1 0 | (0 0) (0 0)
2579 23:07:17.266180 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2580 23:07:17.269154 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2581 23:07:17.272843 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2582 23:07:17.279117 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2583 23:07:17.282456 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2584 23:07:17.285976 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2585 23:07:17.289117 1 0 0 | B1->B0 | 3131 2323 | 0 0 | (0 0) (1 0)
2586 23:07:17.296014 1 0 4 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
2587 23:07:17.299259 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2588 23:07:17.302660 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2589 23:07:17.309599 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2590 23:07:17.312513 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2591 23:07:17.315731 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2592 23:07:17.322733 1 0 28 | B1->B0 | 2323 2424 | 0 1 | (0 0) (0 0)
2593 23:07:17.325750 1 1 0 | B1->B0 | 2727 3434 | 0 0 | (0 0) (0 0)
2594 23:07:17.329000 1 1 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
2595 23:07:17.336125 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2596 23:07:17.339397 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2597 23:07:17.342565 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2598 23:07:17.349303 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2599 23:07:17.352574 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2600 23:07:17.356054 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2601 23:07:17.362488 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2602 23:07:17.366015 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2603 23:07:17.369410 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2604 23:07:17.372964 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2605 23:07:17.379529 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2606 23:07:17.382855 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2607 23:07:17.386005 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2608 23:07:17.392914 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2609 23:07:17.395897 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2610 23:07:17.399056 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2611 23:07:17.406253 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2612 23:07:17.409559 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2613 23:07:17.412681 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2614 23:07:17.419511 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2615 23:07:17.422729 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2616 23:07:17.425983 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2617 23:07:17.432811 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2618 23:07:17.433239 Total UI for P1: 0, mck2ui 16
2619 23:07:17.439368 best dqsien dly found for B0: ( 1, 3, 28)
2620 23:07:17.442537 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2621 23:07:17.445850 Total UI for P1: 0, mck2ui 16
2622 23:07:17.448978 best dqsien dly found for B1: ( 1, 4, 0)
2623 23:07:17.452960 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2624 23:07:17.456085 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2625 23:07:17.456602
2626 23:07:17.459349 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2627 23:07:17.462798 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2628 23:07:17.465704 [Gating] SW calibration Done
2629 23:07:17.466157 ==
2630 23:07:17.469014 Dram Type= 6, Freq= 0, CH_0, rank 0
2631 23:07:17.472717 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2632 23:07:17.473158 ==
2633 23:07:17.475988 RX Vref Scan: 0
2634 23:07:17.476448
2635 23:07:17.479315 RX Vref 0 -> 0, step: 1
2636 23:07:17.479742
2637 23:07:17.480077 RX Delay -40 -> 252, step: 8
2638 23:07:17.485875 iDelay=200, Bit 0, Center 111 (32 ~ 191) 160
2639 23:07:17.489217 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2640 23:07:17.492333 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2641 23:07:17.496131 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2642 23:07:17.499184 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2643 23:07:17.506121 iDelay=200, Bit 5, Center 99 (24 ~ 175) 152
2644 23:07:17.509457 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
2645 23:07:17.512454 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2646 23:07:17.515943 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2647 23:07:17.519407 iDelay=200, Bit 9, Center 83 (8 ~ 159) 152
2648 23:07:17.522453 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2649 23:07:17.528962 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2650 23:07:17.532592 iDelay=200, Bit 12, Center 103 (32 ~ 175) 144
2651 23:07:17.535852 iDelay=200, Bit 13, Center 107 (32 ~ 183) 152
2652 23:07:17.539017 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
2653 23:07:17.542169 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2654 23:07:17.546111 ==
2655 23:07:17.549154 Dram Type= 6, Freq= 0, CH_0, rank 0
2656 23:07:17.552345 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2657 23:07:17.552766 ==
2658 23:07:17.553279 DQS Delay:
2659 23:07:17.555698 DQS0 = 0, DQS1 = 0
2660 23:07:17.556113 DQM Delay:
2661 23:07:17.559311 DQM0 = 113, DQM1 = 101
2662 23:07:17.559728 DQ Delay:
2663 23:07:17.562530 DQ0 =111, DQ1 =115, DQ2 =115, DQ3 =107
2664 23:07:17.565642 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123
2665 23:07:17.569052 DQ8 =91, DQ9 =83, DQ10 =103, DQ11 =95
2666 23:07:17.572551 DQ12 =103, DQ13 =107, DQ14 =115, DQ15 =111
2667 23:07:17.573017
2668 23:07:17.573352
2669 23:07:17.573731 ==
2670 23:07:17.576286 Dram Type= 6, Freq= 0, CH_0, rank 0
2671 23:07:17.582300 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2672 23:07:17.582923 ==
2673 23:07:17.583293
2674 23:07:17.583625
2675 23:07:17.584143 TX Vref Scan disable
2676 23:07:17.585737 == TX Byte 0 ==
2677 23:07:17.589054 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2678 23:07:17.592356 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2679 23:07:17.595798 == TX Byte 1 ==
2680 23:07:17.598900 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2681 23:07:17.605616 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2682 23:07:17.606042 ==
2683 23:07:17.609024 Dram Type= 6, Freq= 0, CH_0, rank 0
2684 23:07:17.612093 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2685 23:07:17.612525 ==
2686 23:07:17.623758 TX Vref=22, minBit 7, minWin=25, winSum=417
2687 23:07:17.627102 TX Vref=24, minBit 0, minWin=26, winSum=422
2688 23:07:17.630568 TX Vref=26, minBit 2, minWin=26, winSum=429
2689 23:07:17.633674 TX Vref=28, minBit 0, minWin=27, winSum=435
2690 23:07:17.637235 TX Vref=30, minBit 2, minWin=26, winSum=431
2691 23:07:17.640394 TX Vref=32, minBit 2, minWin=26, winSum=430
2692 23:07:17.647491 [TxChooseVref] Worse bit 0, Min win 27, Win sum 435, Final Vref 28
2693 23:07:17.647942
2694 23:07:17.650813 Final TX Range 1 Vref 28
2695 23:07:17.651344
2696 23:07:17.651682 ==
2697 23:07:17.653890 Dram Type= 6, Freq= 0, CH_0, rank 0
2698 23:07:17.657162 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2699 23:07:17.657627 ==
2700 23:07:17.657962
2701 23:07:17.660777
2702 23:07:17.661194 TX Vref Scan disable
2703 23:07:17.664079 == TX Byte 0 ==
2704 23:07:17.667301 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2705 23:07:17.670502 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2706 23:07:17.673668 == TX Byte 1 ==
2707 23:07:17.677322 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2708 23:07:17.680778 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2709 23:07:17.681227
2710 23:07:17.683599 [DATLAT]
2711 23:07:17.684131 Freq=1200, CH0 RK0
2712 23:07:17.684471
2713 23:07:17.686875 DATLAT Default: 0xd
2714 23:07:17.687289 0, 0xFFFF, sum = 0
2715 23:07:17.690233 1, 0xFFFF, sum = 0
2716 23:07:17.690659 2, 0xFFFF, sum = 0
2717 23:07:17.693507 3, 0xFFFF, sum = 0
2718 23:07:17.693931 4, 0xFFFF, sum = 0
2719 23:07:17.697345 5, 0xFFFF, sum = 0
2720 23:07:17.697812 6, 0xFFFF, sum = 0
2721 23:07:17.700851 7, 0xFFFF, sum = 0
2722 23:07:17.701367 8, 0xFFFF, sum = 0
2723 23:07:17.704215 9, 0xFFFF, sum = 0
2724 23:07:17.707418 10, 0xFFFF, sum = 0
2725 23:07:17.707938 11, 0xFFFF, sum = 0
2726 23:07:17.710832 12, 0x0, sum = 1
2727 23:07:17.711370 13, 0x0, sum = 2
2728 23:07:17.714027 14, 0x0, sum = 3
2729 23:07:17.714559 15, 0x0, sum = 4
2730 23:07:17.715067 best_step = 13
2731 23:07:17.715458
2732 23:07:17.717165 ==
2733 23:07:17.717619 Dram Type= 6, Freq= 0, CH_0, rank 0
2734 23:07:17.723726 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2735 23:07:17.724146 ==
2736 23:07:17.724659 RX Vref Scan: 1
2737 23:07:17.725063
2738 23:07:17.727064 Set Vref Range= 32 -> 127
2739 23:07:17.727491
2740 23:07:17.730689 RX Vref 32 -> 127, step: 1
2741 23:07:17.731310
2742 23:07:17.733724 RX Delay -37 -> 252, step: 4
2743 23:07:17.734149
2744 23:07:17.737276 Set Vref, RX VrefLevel [Byte0]: 32
2745 23:07:17.740539 [Byte1]: 32
2746 23:07:17.741076
2747 23:07:17.743765 Set Vref, RX VrefLevel [Byte0]: 33
2748 23:07:17.747347 [Byte1]: 33
2749 23:07:17.747877
2750 23:07:17.750410 Set Vref, RX VrefLevel [Byte0]: 34
2751 23:07:17.753602 [Byte1]: 34
2752 23:07:17.758537
2753 23:07:17.759064 Set Vref, RX VrefLevel [Byte0]: 35
2754 23:07:17.761782 [Byte1]: 35
2755 23:07:17.766459
2756 23:07:17.766882 Set Vref, RX VrefLevel [Byte0]: 36
2757 23:07:17.769583 [Byte1]: 36
2758 23:07:17.774723
2759 23:07:17.775247 Set Vref, RX VrefLevel [Byte0]: 37
2760 23:07:17.777855 [Byte1]: 37
2761 23:07:17.782275
2762 23:07:17.782804 Set Vref, RX VrefLevel [Byte0]: 38
2763 23:07:17.785397 [Byte1]: 38
2764 23:07:17.790528
2765 23:07:17.791052 Set Vref, RX VrefLevel [Byte0]: 39
2766 23:07:17.793435 [Byte1]: 39
2767 23:07:17.798379
2768 23:07:17.798892 Set Vref, RX VrefLevel [Byte0]: 40
2769 23:07:17.801832 [Byte1]: 40
2770 23:07:17.806487
2771 23:07:17.807007 Set Vref, RX VrefLevel [Byte0]: 41
2772 23:07:17.809611 [Byte1]: 41
2773 23:07:17.814649
2774 23:07:17.815173 Set Vref, RX VrefLevel [Byte0]: 42
2775 23:07:17.817445 [Byte1]: 42
2776 23:07:17.822430
2777 23:07:17.822941 Set Vref, RX VrefLevel [Byte0]: 43
2778 23:07:17.825349 [Byte1]: 43
2779 23:07:17.830340
2780 23:07:17.830854 Set Vref, RX VrefLevel [Byte0]: 44
2781 23:07:17.833819 [Byte1]: 44
2782 23:07:17.838224
2783 23:07:17.838745 Set Vref, RX VrefLevel [Byte0]: 45
2784 23:07:17.841579 [Byte1]: 45
2785 23:07:17.846244
2786 23:07:17.846705 Set Vref, RX VrefLevel [Byte0]: 46
2787 23:07:17.849558 [Byte1]: 46
2788 23:07:17.854150
2789 23:07:17.854656 Set Vref, RX VrefLevel [Byte0]: 47
2790 23:07:17.857565 [Byte1]: 47
2791 23:07:17.862184
2792 23:07:17.862693 Set Vref, RX VrefLevel [Byte0]: 48
2793 23:07:17.865568 [Byte1]: 48
2794 23:07:17.870117
2795 23:07:17.870625 Set Vref, RX VrefLevel [Byte0]: 49
2796 23:07:17.873844 [Byte1]: 49
2797 23:07:17.878375
2798 23:07:17.878887 Set Vref, RX VrefLevel [Byte0]: 50
2799 23:07:17.881469 [Byte1]: 50
2800 23:07:17.886375
2801 23:07:17.886900 Set Vref, RX VrefLevel [Byte0]: 51
2802 23:07:17.889595 [Byte1]: 51
2803 23:07:17.894341
2804 23:07:17.894860 Set Vref, RX VrefLevel [Byte0]: 52
2805 23:07:17.897588 [Byte1]: 52
2806 23:07:17.902349
2807 23:07:17.902903 Set Vref, RX VrefLevel [Byte0]: 53
2808 23:07:17.905938 [Byte1]: 53
2809 23:07:17.910553
2810 23:07:17.911126 Set Vref, RX VrefLevel [Byte0]: 54
2811 23:07:17.913855 [Byte1]: 54
2812 23:07:17.918145
2813 23:07:17.918702 Set Vref, RX VrefLevel [Byte0]: 55
2814 23:07:17.921841 [Byte1]: 55
2815 23:07:17.925944
2816 23:07:17.926362 Set Vref, RX VrefLevel [Byte0]: 56
2817 23:07:17.929718 [Byte1]: 56
2818 23:07:17.934197
2819 23:07:17.934748 Set Vref, RX VrefLevel [Byte0]: 57
2820 23:07:17.937618 [Byte1]: 57
2821 23:07:17.942332
2822 23:07:17.942755 Set Vref, RX VrefLevel [Byte0]: 58
2823 23:07:17.945703 [Byte1]: 58
2824 23:07:17.950339
2825 23:07:17.950757 Set Vref, RX VrefLevel [Byte0]: 59
2826 23:07:17.953649 [Byte1]: 59
2827 23:07:17.958489
2828 23:07:17.959007 Set Vref, RX VrefLevel [Byte0]: 60
2829 23:07:17.961736 [Byte1]: 60
2830 23:07:17.966610
2831 23:07:17.967132 Set Vref, RX VrefLevel [Byte0]: 61
2832 23:07:17.969593 [Byte1]: 61
2833 23:07:17.974042
2834 23:07:17.974484 Set Vref, RX VrefLevel [Byte0]: 62
2835 23:07:17.977852 [Byte1]: 62
2836 23:07:17.982561
2837 23:07:17.983074 Set Vref, RX VrefLevel [Byte0]: 63
2838 23:07:17.985635 [Byte1]: 63
2839 23:07:17.990682
2840 23:07:17.991197 Set Vref, RX VrefLevel [Byte0]: 64
2841 23:07:17.994046 [Byte1]: 64
2842 23:07:17.998470
2843 23:07:17.998991 Set Vref, RX VrefLevel [Byte0]: 65
2844 23:07:18.001747 [Byte1]: 65
2845 23:07:18.006403
2846 23:07:18.006920 Set Vref, RX VrefLevel [Byte0]: 66
2847 23:07:18.009520 [Byte1]: 66
2848 23:07:18.014637
2849 23:07:18.015161 Set Vref, RX VrefLevel [Byte0]: 67
2850 23:07:18.017311 [Byte1]: 67
2851 23:07:18.022429
2852 23:07:18.022947 Set Vref, RX VrefLevel [Byte0]: 68
2853 23:07:18.025369 [Byte1]: 68
2854 23:07:18.030196
2855 23:07:18.030615 Set Vref, RX VrefLevel [Byte0]: 69
2856 23:07:18.033391 [Byte1]: 69
2857 23:07:18.038361
2858 23:07:18.038882 Set Vref, RX VrefLevel [Byte0]: 70
2859 23:07:18.041768 [Byte1]: 70
2860 23:07:18.046519
2861 23:07:18.047037 Set Vref, RX VrefLevel [Byte0]: 71
2862 23:07:18.049623 [Byte1]: 71
2863 23:07:18.054717
2864 23:07:18.055241 Set Vref, RX VrefLevel [Byte0]: 72
2865 23:07:18.057954 [Byte1]: 72
2866 23:07:18.062223
2867 23:07:18.062739 Set Vref, RX VrefLevel [Byte0]: 73
2868 23:07:18.065235 [Byte1]: 73
2869 23:07:18.069956
2870 23:07:18.070385 Set Vref, RX VrefLevel [Byte0]: 74
2871 23:07:18.073347 [Byte1]: 74
2872 23:07:18.078453
2873 23:07:18.078885 Final RX Vref Byte 0 = 60 to rank0
2874 23:07:18.081559 Final RX Vref Byte 1 = 58 to rank0
2875 23:07:18.084944 Final RX Vref Byte 0 = 60 to rank1
2876 23:07:18.088575 Final RX Vref Byte 1 = 58 to rank1==
2877 23:07:18.091520 Dram Type= 6, Freq= 0, CH_0, rank 0
2878 23:07:18.095002 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2879 23:07:18.098318 ==
2880 23:07:18.098739 DQS Delay:
2881 23:07:18.099209 DQS0 = 0, DQS1 = 0
2882 23:07:18.101374 DQM Delay:
2883 23:07:18.101872 DQM0 = 112, DQM1 = 102
2884 23:07:18.105077 DQ Delay:
2885 23:07:18.108362 DQ0 =110, DQ1 =114, DQ2 =110, DQ3 =108
2886 23:07:18.111380 DQ4 =112, DQ5 =104, DQ6 =118, DQ7 =120
2887 23:07:18.114598 DQ8 =94, DQ9 =86, DQ10 =104, DQ11 =94
2888 23:07:18.118287 DQ12 =108, DQ13 =108, DQ14 =116, DQ15 =108
2889 23:07:18.118728
2890 23:07:18.119104
2891 23:07:18.124615 [DQSOSCAuto] RK0, (LSB)MR18= 0xff, (MSB)MR19= 0x403, tDQSOscB0 = 410 ps tDQSOscB1 = 410 ps
2892 23:07:18.128382 CH0 RK0: MR19=403, MR18=FF
2893 23:07:18.134943 CH0_RK0: MR19=0x403, MR18=0xFF, DQSOSC=410, MR23=63, INC=39, DEC=26
2894 23:07:18.135580
2895 23:07:18.138068 ----->DramcWriteLeveling(PI) begin...
2896 23:07:18.138591 ==
2897 23:07:18.141140 Dram Type= 6, Freq= 0, CH_0, rank 1
2898 23:07:18.144250 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2899 23:07:18.144796 ==
2900 23:07:18.148085 Write leveling (Byte 0): 31 => 31
2901 23:07:18.151519 Write leveling (Byte 1): 29 => 29
2902 23:07:18.154684 DramcWriteLeveling(PI) end<-----
2903 23:07:18.155121
2904 23:07:18.155478 ==
2905 23:07:18.158032 Dram Type= 6, Freq= 0, CH_0, rank 1
2906 23:07:18.161377 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2907 23:07:18.164599 ==
2908 23:07:18.165046 [Gating] SW mode calibration
2909 23:07:18.174253 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2910 23:07:18.177966 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2911 23:07:18.181219 0 15 0 | B1->B0 | 2929 3434 | 0 1 | (0 0) (1 1)
2912 23:07:18.187948 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2913 23:07:18.191209 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2914 23:07:18.194655 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2915 23:07:18.200865 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2916 23:07:18.204257 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2917 23:07:18.207624 0 15 24 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 0)
2918 23:07:18.214015 0 15 28 | B1->B0 | 3434 2626 | 1 0 | (1 0) (0 0)
2919 23:07:18.217369 1 0 0 | B1->B0 | 2626 2323 | 0 0 | (1 0) (0 0)
2920 23:07:18.220883 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2921 23:07:18.227748 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2922 23:07:18.230952 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2923 23:07:18.234198 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2924 23:07:18.240601 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2925 23:07:18.243841 1 0 24 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
2926 23:07:18.247683 1 0 28 | B1->B0 | 2525 4646 | 0 0 | (0 0) (0 0)
2927 23:07:18.254088 1 1 0 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
2928 23:07:18.257089 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2929 23:07:18.260884 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2930 23:07:18.267320 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2931 23:07:18.270450 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2932 23:07:18.274120 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2933 23:07:18.280493 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2934 23:07:18.284046 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2935 23:07:18.287102 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2936 23:07:18.290759 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2937 23:07:18.297179 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2938 23:07:18.300805 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2939 23:07:18.303981 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2940 23:07:18.310436 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2941 23:07:18.314304 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2942 23:07:18.317538 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2943 23:07:18.323806 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2944 23:07:18.327025 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2945 23:07:18.330369 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2946 23:07:18.337327 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2947 23:07:18.340968 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2948 23:07:18.343766 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2949 23:07:18.350942 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2950 23:07:18.354039 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
2951 23:07:18.357193 Total UI for P1: 0, mck2ui 16
2952 23:07:18.361051 best dqsien dly found for B0: ( 1, 3, 26)
2953 23:07:18.363983 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2954 23:07:18.370268 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2955 23:07:18.370351 Total UI for P1: 0, mck2ui 16
2956 23:07:18.373814 best dqsien dly found for B1: ( 1, 4, 0)
2957 23:07:18.380062 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2958 23:07:18.383738 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2959 23:07:18.383842
2960 23:07:18.386896 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2961 23:07:18.390317 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2962 23:07:18.393707 [Gating] SW calibration Done
2963 23:07:18.393780 ==
2964 23:07:18.396858 Dram Type= 6, Freq= 0, CH_0, rank 1
2965 23:07:18.400205 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2966 23:07:18.400286 ==
2967 23:07:18.400349 RX Vref Scan: 0
2968 23:07:18.403782
2969 23:07:18.403880 RX Vref 0 -> 0, step: 1
2970 23:07:18.403968
2971 23:07:18.407049 RX Delay -40 -> 252, step: 8
2972 23:07:18.410189 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2973 23:07:18.413346 iDelay=200, Bit 1, Center 111 (32 ~ 191) 160
2974 23:07:18.419926 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2975 23:07:18.423527 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2976 23:07:18.426693 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2977 23:07:18.429908 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2978 23:07:18.433764 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2979 23:07:18.440132 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2980 23:07:18.443673 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2981 23:07:18.446693 iDelay=200, Bit 9, Center 83 (8 ~ 159) 152
2982 23:07:18.450245 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
2983 23:07:18.453377 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2984 23:07:18.459866 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2985 23:07:18.463506 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2986 23:07:18.466735 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
2987 23:07:18.470241 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2988 23:07:18.470328 ==
2989 23:07:18.473327 Dram Type= 6, Freq= 0, CH_0, rank 1
2990 23:07:18.476735 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2991 23:07:18.480077 ==
2992 23:07:18.480159 DQS Delay:
2993 23:07:18.480224 DQS0 = 0, DQS1 = 0
2994 23:07:18.483621 DQM Delay:
2995 23:07:18.483704 DQM0 = 113, DQM1 = 102
2996 23:07:18.486818 DQ Delay:
2997 23:07:18.490186 DQ0 =111, DQ1 =111, DQ2 =111, DQ3 =107
2998 23:07:18.493443 DQ4 =115, DQ5 =103, DQ6 =123, DQ7 =123
2999 23:07:18.496584 DQ8 =91, DQ9 =83, DQ10 =107, DQ11 =95
3000 23:07:18.500392 DQ12 =111, DQ13 =111, DQ14 =111, DQ15 =111
3001 23:07:18.500475
3002 23:07:18.500540
3003 23:07:18.500601 ==
3004 23:07:18.503537 Dram Type= 6, Freq= 0, CH_0, rank 1
3005 23:07:18.506563 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3006 23:07:18.506671 ==
3007 23:07:18.506737
3008 23:07:18.506798
3009 23:07:18.509897 TX Vref Scan disable
3010 23:07:18.513615 == TX Byte 0 ==
3011 23:07:18.516939 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
3012 23:07:18.520194 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
3013 23:07:18.523424 == TX Byte 1 ==
3014 23:07:18.526745 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3015 23:07:18.530389 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3016 23:07:18.530472 ==
3017 23:07:18.533379 Dram Type= 6, Freq= 0, CH_0, rank 1
3018 23:07:18.537104 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3019 23:07:18.539752 ==
3020 23:07:18.550156 TX Vref=22, minBit 1, minWin=26, winSum=430
3021 23:07:18.553810 TX Vref=24, minBit 0, minWin=27, winSum=434
3022 23:07:18.557013 TX Vref=26, minBit 5, minWin=26, winSum=435
3023 23:07:18.560327 TX Vref=28, minBit 2, minWin=27, winSum=442
3024 23:07:18.563599 TX Vref=30, minBit 1, minWin=27, winSum=441
3025 23:07:18.566955 TX Vref=32, minBit 8, minWin=26, winSum=439
3026 23:07:18.573685 [TxChooseVref] Worse bit 2, Min win 27, Win sum 442, Final Vref 28
3027 23:07:18.573768
3028 23:07:18.576789 Final TX Range 1 Vref 28
3029 23:07:18.576872
3030 23:07:18.576938 ==
3031 23:07:18.580035 Dram Type= 6, Freq= 0, CH_0, rank 1
3032 23:07:18.583639 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3033 23:07:18.583723 ==
3034 23:07:18.583788
3035 23:07:18.586689
3036 23:07:18.586771 TX Vref Scan disable
3037 23:07:18.590219 == TX Byte 0 ==
3038 23:07:18.593616 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
3039 23:07:18.596889 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
3040 23:07:18.600190 == TX Byte 1 ==
3041 23:07:18.603841 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3042 23:07:18.606879 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3043 23:07:18.606962
3044 23:07:18.610487 [DATLAT]
3045 23:07:18.610569 Freq=1200, CH0 RK1
3046 23:07:18.610665
3047 23:07:18.613833 DATLAT Default: 0xd
3048 23:07:18.613916 0, 0xFFFF, sum = 0
3049 23:07:18.616967 1, 0xFFFF, sum = 0
3050 23:07:18.617051 2, 0xFFFF, sum = 0
3051 23:07:18.620181 3, 0xFFFF, sum = 0
3052 23:07:18.620278 4, 0xFFFF, sum = 0
3053 23:07:18.623323 5, 0xFFFF, sum = 0
3054 23:07:18.623407 6, 0xFFFF, sum = 0
3055 23:07:18.627220 7, 0xFFFF, sum = 0
3056 23:07:18.627304 8, 0xFFFF, sum = 0
3057 23:07:18.630361 9, 0xFFFF, sum = 0
3058 23:07:18.633581 10, 0xFFFF, sum = 0
3059 23:07:18.633659 11, 0xFFFF, sum = 0
3060 23:07:18.636763 12, 0x0, sum = 1
3061 23:07:18.636847 13, 0x0, sum = 2
3062 23:07:18.636913 14, 0x0, sum = 3
3063 23:07:18.640501 15, 0x0, sum = 4
3064 23:07:18.640585 best_step = 13
3065 23:07:18.640651
3066 23:07:18.643676 ==
3067 23:07:18.643761 Dram Type= 6, Freq= 0, CH_0, rank 1
3068 23:07:18.650184 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3069 23:07:18.650266 ==
3070 23:07:18.650332 RX Vref Scan: 0
3071 23:07:18.650394
3072 23:07:18.653723 RX Vref 0 -> 0, step: 1
3073 23:07:18.653806
3074 23:07:18.656973 RX Delay -37 -> 252, step: 4
3075 23:07:18.660061 iDelay=195, Bit 0, Center 108 (39 ~ 178) 140
3076 23:07:18.667207 iDelay=195, Bit 1, Center 110 (39 ~ 182) 144
3077 23:07:18.670360 iDelay=195, Bit 2, Center 108 (39 ~ 178) 140
3078 23:07:18.673777 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3079 23:07:18.676942 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3080 23:07:18.680356 iDelay=195, Bit 5, Center 100 (35 ~ 166) 132
3081 23:07:18.683814 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3082 23:07:18.690383 iDelay=195, Bit 7, Center 120 (47 ~ 194) 148
3083 23:07:18.693993 iDelay=195, Bit 8, Center 90 (19 ~ 162) 144
3084 23:07:18.697110 iDelay=195, Bit 9, Center 84 (15 ~ 154) 140
3085 23:07:18.700188 iDelay=195, Bit 10, Center 102 (35 ~ 170) 136
3086 23:07:18.703392 iDelay=195, Bit 11, Center 94 (27 ~ 162) 136
3087 23:07:18.709919 iDelay=195, Bit 12, Center 110 (43 ~ 178) 136
3088 23:07:18.713367 iDelay=195, Bit 13, Center 106 (39 ~ 174) 136
3089 23:07:18.716967 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3090 23:07:18.720150 iDelay=195, Bit 15, Center 110 (43 ~ 178) 136
3091 23:07:18.720232 ==
3092 23:07:18.723405 Dram Type= 6, Freq= 0, CH_0, rank 1
3093 23:07:18.729919 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3094 23:07:18.730002 ==
3095 23:07:18.730068 DQS Delay:
3096 23:07:18.730129 DQS0 = 0, DQS1 = 0
3097 23:07:18.733213 DQM Delay:
3098 23:07:18.733296 DQM0 = 110, DQM1 = 101
3099 23:07:18.736904 DQ Delay:
3100 23:07:18.740053 DQ0 =108, DQ1 =110, DQ2 =108, DQ3 =108
3101 23:07:18.743321 DQ4 =112, DQ5 =100, DQ6 =120, DQ7 =120
3102 23:07:18.746609 DQ8 =90, DQ9 =84, DQ10 =102, DQ11 =94
3103 23:07:18.749894 DQ12 =110, DQ13 =106, DQ14 =116, DQ15 =110
3104 23:07:18.749977
3105 23:07:18.750042
3106 23:07:18.756757 [DQSOSCAuto] RK1, (LSB)MR18= 0x13fc, (MSB)MR19= 0x403, tDQSOscB0 = 411 ps tDQSOscB1 = 402 ps
3107 23:07:18.759955 CH0 RK1: MR19=403, MR18=13FC
3108 23:07:18.766624 CH0_RK1: MR19=0x403, MR18=0x13FC, DQSOSC=402, MR23=63, INC=40, DEC=27
3109 23:07:18.770049 [RxdqsGatingPostProcess] freq 1200
3110 23:07:18.777043 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3111 23:07:18.779799 best DQS0 dly(2T, 0.5T) = (0, 11)
3112 23:07:18.783126 best DQS1 dly(2T, 0.5T) = (0, 12)
3113 23:07:18.783235 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3114 23:07:18.786880 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3115 23:07:18.790005 best DQS0 dly(2T, 0.5T) = (0, 11)
3116 23:07:18.793120 best DQS1 dly(2T, 0.5T) = (0, 12)
3117 23:07:18.796855 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3118 23:07:18.800086 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3119 23:07:18.803246 Pre-setting of DQS Precalculation
3120 23:07:18.810412 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3121 23:07:18.810495 ==
3122 23:07:18.813095 Dram Type= 6, Freq= 0, CH_1, rank 0
3123 23:07:18.816504 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3124 23:07:18.816588 ==
3125 23:07:18.823087 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3126 23:07:18.826306 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3127 23:07:18.836300 [CA 0] Center 37 (7~67) winsize 61
3128 23:07:18.839699 [CA 1] Center 37 (7~68) winsize 62
3129 23:07:18.842795 [CA 2] Center 34 (4~64) winsize 61
3130 23:07:18.846562 [CA 3] Center 34 (4~64) winsize 61
3131 23:07:18.849743 [CA 4] Center 34 (4~64) winsize 61
3132 23:07:18.852973 [CA 5] Center 33 (3~63) winsize 61
3133 23:07:18.853056
3134 23:07:18.856112 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3135 23:07:18.856195
3136 23:07:18.859380 [CATrainingPosCal] consider 1 rank data
3137 23:07:18.862679 u2DelayCellTimex100 = 270/100 ps
3138 23:07:18.865957 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3139 23:07:18.869421 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3140 23:07:18.876210 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3141 23:07:18.879302 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3142 23:07:18.883206 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3143 23:07:18.886448 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3144 23:07:18.886532
3145 23:07:18.889514 CA PerBit enable=1, Macro0, CA PI delay=33
3146 23:07:18.889597
3147 23:07:18.892730 [CBTSetCACLKResult] CA Dly = 33
3148 23:07:18.892812 CS Dly: 6 (0~37)
3149 23:07:18.892878 ==
3150 23:07:18.895963 Dram Type= 6, Freq= 0, CH_1, rank 1
3151 23:07:18.902835 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3152 23:07:18.902918 ==
3153 23:07:18.906298 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3154 23:07:18.913029 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3155 23:07:18.921662 [CA 0] Center 37 (8~67) winsize 60
3156 23:07:18.925109 [CA 1] Center 37 (7~68) winsize 62
3157 23:07:18.928606 [CA 2] Center 34 (4~65) winsize 62
3158 23:07:18.931651 [CA 3] Center 33 (3~64) winsize 62
3159 23:07:18.935305 [CA 4] Center 34 (4~65) winsize 62
3160 23:07:18.938470 [CA 5] Center 33 (3~63) winsize 61
3161 23:07:18.938547
3162 23:07:18.941634 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3163 23:07:18.941708
3164 23:07:18.945180 [CATrainingPosCal] consider 2 rank data
3165 23:07:18.948285 u2DelayCellTimex100 = 270/100 ps
3166 23:07:18.951845 CA0 delay=37 (8~67),Diff = 4 PI (19 cell)
3167 23:07:18.955299 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3168 23:07:18.961916 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3169 23:07:18.965254 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3170 23:07:18.968520 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3171 23:07:18.971778 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3172 23:07:18.971876
3173 23:07:18.975457 CA PerBit enable=1, Macro0, CA PI delay=33
3174 23:07:18.975535
3175 23:07:18.978404 [CBTSetCACLKResult] CA Dly = 33
3176 23:07:18.978504 CS Dly: 7 (0~39)
3177 23:07:18.978593
3178 23:07:18.981718 ----->DramcWriteLeveling(PI) begin...
3179 23:07:18.985003 ==
3180 23:07:18.985107 Dram Type= 6, Freq= 0, CH_1, rank 0
3181 23:07:18.991538 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3182 23:07:18.991645 ==
3183 23:07:18.995312 Write leveling (Byte 0): 25 => 25
3184 23:07:18.998596 Write leveling (Byte 1): 29 => 29
3185 23:07:19.001799 DramcWriteLeveling(PI) end<-----
3186 23:07:19.001905
3187 23:07:19.001999 ==
3188 23:07:19.005029 Dram Type= 6, Freq= 0, CH_1, rank 0
3189 23:07:19.008183 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3190 23:07:19.008283 ==
3191 23:07:19.011857 [Gating] SW mode calibration
3192 23:07:19.018669 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3193 23:07:19.021889 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3194 23:07:19.028258 0 15 0 | B1->B0 | 2f2f 2525 | 1 1 | (0 0) (0 0)
3195 23:07:19.031441 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3196 23:07:19.035228 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3197 23:07:19.041832 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3198 23:07:19.045292 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3199 23:07:19.048728 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3200 23:07:19.055197 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3201 23:07:19.058488 0 15 28 | B1->B0 | 2f2f 2c2c | 0 0 | (1 0) (0 0)
3202 23:07:19.061929 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
3203 23:07:19.068256 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3204 23:07:19.071521 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3205 23:07:19.075315 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3206 23:07:19.081861 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3207 23:07:19.085046 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3208 23:07:19.088596 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3209 23:07:19.095090 1 0 28 | B1->B0 | 3a3a 3b3b | 1 0 | (0 0) (0 0)
3210 23:07:19.098239 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3211 23:07:19.101928 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3212 23:07:19.105212 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3213 23:07:19.112269 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3214 23:07:19.115495 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3215 23:07:19.118786 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3216 23:07:19.125427 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3217 23:07:19.128746 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3218 23:07:19.131962 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3219 23:07:19.138450 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3220 23:07:19.141798 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3221 23:07:19.144849 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3222 23:07:19.151364 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3223 23:07:19.154728 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3224 23:07:19.158439 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3225 23:07:19.164638 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3226 23:07:19.167942 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3227 23:07:19.171446 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3228 23:07:19.178196 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3229 23:07:19.181362 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3230 23:07:19.184684 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3231 23:07:19.191409 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3232 23:07:19.194714 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3233 23:07:19.198346 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3234 23:07:19.204537 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3235 23:07:19.204634 Total UI for P1: 0, mck2ui 16
3236 23:07:19.211215 best dqsien dly found for B0: ( 1, 3, 28)
3237 23:07:19.211298 Total UI for P1: 0, mck2ui 16
3238 23:07:19.217833 best dqsien dly found for B1: ( 1, 3, 28)
3239 23:07:19.221463 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3240 23:07:19.224785 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3241 23:07:19.224867
3242 23:07:19.228383 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3243 23:07:19.231434 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3244 23:07:19.234615 [Gating] SW calibration Done
3245 23:07:19.234698 ==
3246 23:07:19.237814 Dram Type= 6, Freq= 0, CH_1, rank 0
3247 23:07:19.241195 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3248 23:07:19.241278 ==
3249 23:07:19.244354 RX Vref Scan: 0
3250 23:07:19.244437
3251 23:07:19.244502 RX Vref 0 -> 0, step: 1
3252 23:07:19.244564
3253 23:07:19.248214 RX Delay -40 -> 252, step: 8
3254 23:07:19.250973 iDelay=200, Bit 0, Center 123 (48 ~ 199) 152
3255 23:07:19.257909 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3256 23:07:19.261374 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3257 23:07:19.264563 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3258 23:07:19.267705 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3259 23:07:19.271529 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3260 23:07:19.277888 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3261 23:07:19.281366 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3262 23:07:19.284458 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3263 23:07:19.287577 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3264 23:07:19.290941 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
3265 23:07:19.294613 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
3266 23:07:19.301105 iDelay=200, Bit 12, Center 115 (40 ~ 191) 152
3267 23:07:19.304243 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
3268 23:07:19.307959 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3269 23:07:19.310849 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3270 23:07:19.310932 ==
3271 23:07:19.314681 Dram Type= 6, Freq= 0, CH_1, rank 0
3272 23:07:19.321342 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3273 23:07:19.321426 ==
3274 23:07:19.321521 DQS Delay:
3275 23:07:19.324636 DQS0 = 0, DQS1 = 0
3276 23:07:19.324718 DQM Delay:
3277 23:07:19.324784 DQM0 = 114, DQM1 = 106
3278 23:07:19.327874 DQ Delay:
3279 23:07:19.331139 DQ0 =123, DQ1 =107, DQ2 =103, DQ3 =115
3280 23:07:19.334357 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =111
3281 23:07:19.337732 DQ8 =95, DQ9 =99, DQ10 =103, DQ11 =99
3282 23:07:19.341041 DQ12 =115, DQ13 =115, DQ14 =111, DQ15 =111
3283 23:07:19.341123
3284 23:07:19.341187
3285 23:07:19.341247 ==
3286 23:07:19.344755 Dram Type= 6, Freq= 0, CH_1, rank 0
3287 23:07:19.347937 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3288 23:07:19.348023 ==
3289 23:07:19.351014
3290 23:07:19.351119
3291 23:07:19.351186 TX Vref Scan disable
3292 23:07:19.354623 == TX Byte 0 ==
3293 23:07:19.357745 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3294 23:07:19.361323 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3295 23:07:19.364595 == TX Byte 1 ==
3296 23:07:19.367594 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3297 23:07:19.371035 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3298 23:07:19.371118 ==
3299 23:07:19.374245 Dram Type= 6, Freq= 0, CH_1, rank 0
3300 23:07:19.381353 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3301 23:07:19.381436 ==
3302 23:07:19.392096 TX Vref=22, minBit 1, minWin=25, winSum=413
3303 23:07:19.395323 TX Vref=24, minBit 11, minWin=24, winSum=413
3304 23:07:19.398562 TX Vref=26, minBit 8, minWin=25, winSum=421
3305 23:07:19.401621 TX Vref=28, minBit 9, minWin=25, winSum=425
3306 23:07:19.404857 TX Vref=30, minBit 9, minWin=25, winSum=426
3307 23:07:19.411927 TX Vref=32, minBit 8, minWin=25, winSum=424
3308 23:07:19.415204 [TxChooseVref] Worse bit 9, Min win 25, Win sum 426, Final Vref 30
3309 23:07:19.415287
3310 23:07:19.418299 Final TX Range 1 Vref 30
3311 23:07:19.418382
3312 23:07:19.418446 ==
3313 23:07:19.421733 Dram Type= 6, Freq= 0, CH_1, rank 0
3314 23:07:19.425296 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3315 23:07:19.425427 ==
3316 23:07:19.428646
3317 23:07:19.428727
3318 23:07:19.428793 TX Vref Scan disable
3319 23:07:19.431899 == TX Byte 0 ==
3320 23:07:19.435088 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3321 23:07:19.438300 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3322 23:07:19.441952 == TX Byte 1 ==
3323 23:07:19.445049 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3324 23:07:19.448334 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3325 23:07:19.448436
3326 23:07:19.451655 [DATLAT]
3327 23:07:19.451762 Freq=1200, CH1 RK0
3328 23:07:19.451855
3329 23:07:19.455243 DATLAT Default: 0xd
3330 23:07:19.455342 0, 0xFFFF, sum = 0
3331 23:07:19.458403 1, 0xFFFF, sum = 0
3332 23:07:19.458502 2, 0xFFFF, sum = 0
3333 23:07:19.461456 3, 0xFFFF, sum = 0
3334 23:07:19.461599 4, 0xFFFF, sum = 0
3335 23:07:19.465043 5, 0xFFFF, sum = 0
3336 23:07:19.465149 6, 0xFFFF, sum = 0
3337 23:07:19.468491 7, 0xFFFF, sum = 0
3338 23:07:19.471655 8, 0xFFFF, sum = 0
3339 23:07:19.471730 9, 0xFFFF, sum = 0
3340 23:07:19.474977 10, 0xFFFF, sum = 0
3341 23:07:19.475052 11, 0xFFFF, sum = 0
3342 23:07:19.478483 12, 0x0, sum = 1
3343 23:07:19.478590 13, 0x0, sum = 2
3344 23:07:19.481743 14, 0x0, sum = 3
3345 23:07:19.481816 15, 0x0, sum = 4
3346 23:07:19.481885 best_step = 13
3347 23:07:19.481952
3348 23:07:19.485235 ==
3349 23:07:19.488577 Dram Type= 6, Freq= 0, CH_1, rank 0
3350 23:07:19.491731 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3351 23:07:19.491833 ==
3352 23:07:19.491923 RX Vref Scan: 1
3353 23:07:19.492013
3354 23:07:19.495309 Set Vref Range= 32 -> 127
3355 23:07:19.495407
3356 23:07:19.498362 RX Vref 32 -> 127, step: 1
3357 23:07:19.498438
3358 23:07:19.501580 RX Delay -21 -> 252, step: 4
3359 23:07:19.501652
3360 23:07:19.505148 Set Vref, RX VrefLevel [Byte0]: 32
3361 23:07:19.508348 [Byte1]: 32
3362 23:07:19.508450
3363 23:07:19.511718 Set Vref, RX VrefLevel [Byte0]: 33
3364 23:07:19.514841 [Byte1]: 33
3365 23:07:19.514952
3366 23:07:19.518213 Set Vref, RX VrefLevel [Byte0]: 34
3367 23:07:19.521864 [Byte1]: 34
3368 23:07:19.525634
3369 23:07:19.525720 Set Vref, RX VrefLevel [Byte0]: 35
3370 23:07:19.529368 [Byte1]: 35
3371 23:07:19.533861
3372 23:07:19.533982 Set Vref, RX VrefLevel [Byte0]: 36
3373 23:07:19.537198 [Byte1]: 36
3374 23:07:19.541864
3375 23:07:19.541970 Set Vref, RX VrefLevel [Byte0]: 37
3376 23:07:19.545110 [Byte1]: 37
3377 23:07:19.549778
3378 23:07:19.549919 Set Vref, RX VrefLevel [Byte0]: 38
3379 23:07:19.553235 [Byte1]: 38
3380 23:07:19.557441
3381 23:07:19.557595 Set Vref, RX VrefLevel [Byte0]: 39
3382 23:07:19.560612 [Byte1]: 39
3383 23:07:19.565415
3384 23:07:19.565546 Set Vref, RX VrefLevel [Byte0]: 40
3385 23:07:19.569141 [Byte1]: 40
3386 23:07:19.573288
3387 23:07:19.573400 Set Vref, RX VrefLevel [Byte0]: 41
3388 23:07:19.576462 [Byte1]: 41
3389 23:07:19.581185
3390 23:07:19.581321 Set Vref, RX VrefLevel [Byte0]: 42
3391 23:07:19.584569 [Byte1]: 42
3392 23:07:19.589213
3393 23:07:19.589366 Set Vref, RX VrefLevel [Byte0]: 43
3394 23:07:19.592382 [Byte1]: 43
3395 23:07:19.597054
3396 23:07:19.597191 Set Vref, RX VrefLevel [Byte0]: 44
3397 23:07:19.600345 [Byte1]: 44
3398 23:07:19.605206
3399 23:07:19.605344 Set Vref, RX VrefLevel [Byte0]: 45
3400 23:07:19.608308 [Byte1]: 45
3401 23:07:19.612891
3402 23:07:19.613025 Set Vref, RX VrefLevel [Byte0]: 46
3403 23:07:19.616264 [Byte1]: 46
3404 23:07:19.620990
3405 23:07:19.621130 Set Vref, RX VrefLevel [Byte0]: 47
3406 23:07:19.624274 [Byte1]: 47
3407 23:07:19.629060
3408 23:07:19.629167 Set Vref, RX VrefLevel [Byte0]: 48
3409 23:07:19.632505 [Byte1]: 48
3410 23:07:19.637058
3411 23:07:19.637168 Set Vref, RX VrefLevel [Byte0]: 49
3412 23:07:19.639983 [Byte1]: 49
3413 23:07:19.644781
3414 23:07:19.644889 Set Vref, RX VrefLevel [Byte0]: 50
3415 23:07:19.647781 [Byte1]: 50
3416 23:07:19.652674
3417 23:07:19.652779 Set Vref, RX VrefLevel [Byte0]: 51
3418 23:07:19.656208 [Byte1]: 51
3419 23:07:19.660864
3420 23:07:19.660966 Set Vref, RX VrefLevel [Byte0]: 52
3421 23:07:19.663889 [Byte1]: 52
3422 23:07:19.668675
3423 23:07:19.668776 Set Vref, RX VrefLevel [Byte0]: 53
3424 23:07:19.671852 [Byte1]: 53
3425 23:07:19.676642
3426 23:07:19.676757 Set Vref, RX VrefLevel [Byte0]: 54
3427 23:07:19.679951 [Byte1]: 54
3428 23:07:19.684207
3429 23:07:19.684313 Set Vref, RX VrefLevel [Byte0]: 55
3430 23:07:19.687990 [Byte1]: 55
3431 23:07:19.692551
3432 23:07:19.692658 Set Vref, RX VrefLevel [Byte0]: 56
3433 23:07:19.695930 [Byte1]: 56
3434 23:07:19.700267
3435 23:07:19.700398 Set Vref, RX VrefLevel [Byte0]: 57
3436 23:07:19.703386 [Byte1]: 57
3437 23:07:19.708099
3438 23:07:19.708249 Set Vref, RX VrefLevel [Byte0]: 58
3439 23:07:19.711480 [Byte1]: 58
3440 23:07:19.716146
3441 23:07:19.716308 Set Vref, RX VrefLevel [Byte0]: 59
3442 23:07:19.719135 [Byte1]: 59
3443 23:07:19.724132
3444 23:07:19.724270 Set Vref, RX VrefLevel [Byte0]: 60
3445 23:07:19.727333 [Byte1]: 60
3446 23:07:19.732110
3447 23:07:19.732242 Set Vref, RX VrefLevel [Byte0]: 61
3448 23:07:19.735510 [Byte1]: 61
3449 23:07:19.739755
3450 23:07:19.739857 Set Vref, RX VrefLevel [Byte0]: 62
3451 23:07:19.743000 [Byte1]: 62
3452 23:07:19.747738
3453 23:07:19.747840 Set Vref, RX VrefLevel [Byte0]: 63
3454 23:07:19.750736 [Byte1]: 63
3455 23:07:19.755630
3456 23:07:19.755734 Set Vref, RX VrefLevel [Byte0]: 64
3457 23:07:19.758894 [Byte1]: 64
3458 23:07:19.763468
3459 23:07:19.763571 Set Vref, RX VrefLevel [Byte0]: 65
3460 23:07:19.767030 [Byte1]: 65
3461 23:07:19.771589
3462 23:07:19.771693 Set Vref, RX VrefLevel [Byte0]: 66
3463 23:07:19.774915 [Byte1]: 66
3464 23:07:19.779581
3465 23:07:19.779689 Set Vref, RX VrefLevel [Byte0]: 67
3466 23:07:19.782702 [Byte1]: 67
3467 23:07:19.787212
3468 23:07:19.787316 Final RX Vref Byte 0 = 60 to rank0
3469 23:07:19.790422 Final RX Vref Byte 1 = 50 to rank0
3470 23:07:19.794283 Final RX Vref Byte 0 = 60 to rank1
3471 23:07:19.797254 Final RX Vref Byte 1 = 50 to rank1==
3472 23:07:19.800656 Dram Type= 6, Freq= 0, CH_1, rank 0
3473 23:07:19.807261 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3474 23:07:19.807415 ==
3475 23:07:19.807539 DQS Delay:
3476 23:07:19.807653 DQS0 = 0, DQS1 = 0
3477 23:07:19.810670 DQM Delay:
3478 23:07:19.810800 DQM0 = 115, DQM1 = 105
3479 23:07:19.814176 DQ Delay:
3480 23:07:19.817412 DQ0 =118, DQ1 =108, DQ2 =106, DQ3 =112
3481 23:07:19.820619 DQ4 =112, DQ5 =126, DQ6 =126, DQ7 =112
3482 23:07:19.823937 DQ8 =94, DQ9 =100, DQ10 =104, DQ11 =100
3483 23:07:19.827591 DQ12 =112, DQ13 =110, DQ14 =114, DQ15 =112
3484 23:07:19.827731
3485 23:07:19.827847
3486 23:07:19.833881 [DQSOSCAuto] RK0, (LSB)MR18= 0xf2f9, (MSB)MR19= 0x303, tDQSOscB0 = 412 ps tDQSOscB1 = 415 ps
3487 23:07:19.837187 CH1 RK0: MR19=303, MR18=F2F9
3488 23:07:19.844198 CH1_RK0: MR19=0x303, MR18=0xF2F9, DQSOSC=412, MR23=63, INC=38, DEC=25
3489 23:07:19.844302
3490 23:07:19.847308 ----->DramcWriteLeveling(PI) begin...
3491 23:07:19.847412 ==
3492 23:07:19.850897 Dram Type= 6, Freq= 0, CH_1, rank 1
3493 23:07:19.854075 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3494 23:07:19.857310 ==
3495 23:07:19.857423 Write leveling (Byte 0): 26 => 26
3496 23:07:19.860540 Write leveling (Byte 1): 29 => 29
3497 23:07:19.863924 DramcWriteLeveling(PI) end<-----
3498 23:07:19.864035
3499 23:07:19.864132 ==
3500 23:07:19.867124 Dram Type= 6, Freq= 0, CH_1, rank 1
3501 23:07:19.874109 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3502 23:07:19.874219 ==
3503 23:07:19.874312 [Gating] SW mode calibration
3504 23:07:19.883884 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3505 23:07:19.887173 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3506 23:07:19.893542 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3507 23:07:19.897308 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3508 23:07:19.900609 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3509 23:07:19.903804 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3510 23:07:19.910257 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3511 23:07:19.913829 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3512 23:07:19.917009 0 15 24 | B1->B0 | 3434 2828 | 0 0 | (0 1) (1 0)
3513 23:07:19.923841 0 15 28 | B1->B0 | 2626 2323 | 0 0 | (1 0) (0 0)
3514 23:07:19.926963 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3515 23:07:19.930459 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3516 23:07:19.937045 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3517 23:07:19.940420 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3518 23:07:19.943697 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3519 23:07:19.950172 1 0 20 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
3520 23:07:19.953754 1 0 24 | B1->B0 | 2b2b 4545 | 0 0 | (1 1) (0 0)
3521 23:07:19.956825 1 0 28 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
3522 23:07:19.963980 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3523 23:07:19.967028 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3524 23:07:19.970607 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3525 23:07:19.976830 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3526 23:07:19.980334 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3527 23:07:19.983563 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3528 23:07:19.990333 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3529 23:07:19.993679 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3530 23:07:19.996837 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3531 23:07:20.004028 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3532 23:07:20.007241 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3533 23:07:20.010564 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3534 23:07:20.013512 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3535 23:07:20.020423 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3536 23:07:20.023713 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3537 23:07:20.026679 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3538 23:07:20.033445 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3539 23:07:20.036698 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3540 23:07:20.040512 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3541 23:07:20.046750 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3542 23:07:20.050032 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3543 23:07:20.053701 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3544 23:07:20.059816 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3545 23:07:20.063205 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3546 23:07:20.066453 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3547 23:07:20.070121 Total UI for P1: 0, mck2ui 16
3548 23:07:20.073425 best dqsien dly found for B0: ( 1, 3, 24)
3549 23:07:20.076427 Total UI for P1: 0, mck2ui 16
3550 23:07:20.079807 best dqsien dly found for B1: ( 1, 3, 26)
3551 23:07:20.083322 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3552 23:07:20.086688 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3553 23:07:20.089806
3554 23:07:20.093400 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3555 23:07:20.096535 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3556 23:07:20.100058 [Gating] SW calibration Done
3557 23:07:20.100157 ==
3558 23:07:20.102849 Dram Type= 6, Freq= 0, CH_1, rank 1
3559 23:07:20.106166 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3560 23:07:20.106246 ==
3561 23:07:20.106308 RX Vref Scan: 0
3562 23:07:20.109731
3563 23:07:20.109801 RX Vref 0 -> 0, step: 1
3564 23:07:20.109867
3565 23:07:20.112909 RX Delay -40 -> 252, step: 8
3566 23:07:20.116273 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3567 23:07:20.119617 iDelay=200, Bit 1, Center 107 (40 ~ 175) 136
3568 23:07:20.126023 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3569 23:07:20.129367 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3570 23:07:20.132875 iDelay=200, Bit 4, Center 107 (32 ~ 183) 152
3571 23:07:20.136175 iDelay=200, Bit 5, Center 119 (40 ~ 199) 160
3572 23:07:20.139393 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
3573 23:07:20.145850 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3574 23:07:20.149626 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3575 23:07:20.152463 iDelay=200, Bit 9, Center 99 (24 ~ 175) 152
3576 23:07:20.156193 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3577 23:07:20.159077 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
3578 23:07:20.165705 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
3579 23:07:20.169180 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
3580 23:07:20.172337 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3581 23:07:20.175752 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3582 23:07:20.175829 ==
3583 23:07:20.179414 Dram Type= 6, Freq= 0, CH_1, rank 1
3584 23:07:20.185620 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3585 23:07:20.185698 ==
3586 23:07:20.185762 DQS Delay:
3587 23:07:20.185821 DQS0 = 0, DQS1 = 0
3588 23:07:20.188958 DQM Delay:
3589 23:07:20.189028 DQM0 = 111, DQM1 = 106
3590 23:07:20.192204 DQ Delay:
3591 23:07:20.195839 DQ0 =115, DQ1 =107, DQ2 =99, DQ3 =111
3592 23:07:20.199225 DQ4 =107, DQ5 =119, DQ6 =119, DQ7 =111
3593 23:07:20.202268 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =99
3594 23:07:20.205895 DQ12 =111, DQ13 =111, DQ14 =111, DQ15 =111
3595 23:07:20.205966
3596 23:07:20.206031
3597 23:07:20.206090 ==
3598 23:07:20.209253 Dram Type= 6, Freq= 0, CH_1, rank 1
3599 23:07:20.212267 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3600 23:07:20.212367 ==
3601 23:07:20.215554
3602 23:07:20.215628
3603 23:07:20.215690 TX Vref Scan disable
3604 23:07:20.218766 == TX Byte 0 ==
3605 23:07:20.222011 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3606 23:07:20.225373 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3607 23:07:20.228627 == TX Byte 1 ==
3608 23:07:20.232278 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3609 23:07:20.235575 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3610 23:07:20.235672 ==
3611 23:07:20.238660 Dram Type= 6, Freq= 0, CH_1, rank 1
3612 23:07:20.245331 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3613 23:07:20.245442 ==
3614 23:07:20.256073 TX Vref=22, minBit 1, minWin=26, winSum=425
3615 23:07:20.259678 TX Vref=24, minBit 0, minWin=26, winSum=430
3616 23:07:20.263105 TX Vref=26, minBit 6, minWin=26, winSum=433
3617 23:07:20.266282 TX Vref=28, minBit 8, minWin=26, winSum=433
3618 23:07:20.269208 TX Vref=30, minBit 9, minWin=26, winSum=438
3619 23:07:20.273045 TX Vref=32, minBit 1, minWin=26, winSum=434
3620 23:07:20.279706 [TxChooseVref] Worse bit 9, Min win 26, Win sum 438, Final Vref 30
3621 23:07:20.279811
3622 23:07:20.282732 Final TX Range 1 Vref 30
3623 23:07:20.282810
3624 23:07:20.282872 ==
3625 23:07:20.285872 Dram Type= 6, Freq= 0, CH_1, rank 1
3626 23:07:20.289699 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3627 23:07:20.289773 ==
3628 23:07:20.289835
3629 23:07:20.292660
3630 23:07:20.292757 TX Vref Scan disable
3631 23:07:20.296063 == TX Byte 0 ==
3632 23:07:20.299601 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3633 23:07:20.302931 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3634 23:07:20.306192 == TX Byte 1 ==
3635 23:07:20.309326 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3636 23:07:20.312888 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3637 23:07:20.316241
3638 23:07:20.316339 [DATLAT]
3639 23:07:20.316432 Freq=1200, CH1 RK1
3640 23:07:20.316520
3641 23:07:20.319578 DATLAT Default: 0xd
3642 23:07:20.319651 0, 0xFFFF, sum = 0
3643 23:07:20.322412 1, 0xFFFF, sum = 0
3644 23:07:20.322485 2, 0xFFFF, sum = 0
3645 23:07:20.326107 3, 0xFFFF, sum = 0
3646 23:07:20.326182 4, 0xFFFF, sum = 0
3647 23:07:20.329454 5, 0xFFFF, sum = 0
3648 23:07:20.332645 6, 0xFFFF, sum = 0
3649 23:07:20.332746 7, 0xFFFF, sum = 0
3650 23:07:20.335958 8, 0xFFFF, sum = 0
3651 23:07:20.336059 9, 0xFFFF, sum = 0
3652 23:07:20.339308 10, 0xFFFF, sum = 0
3653 23:07:20.339410 11, 0xFFFF, sum = 0
3654 23:07:20.342481 12, 0x0, sum = 1
3655 23:07:20.342582 13, 0x0, sum = 2
3656 23:07:20.345691 14, 0x0, sum = 3
3657 23:07:20.345791 15, 0x0, sum = 4
3658 23:07:20.345893 best_step = 13
3659 23:07:20.349372
3660 23:07:20.349498 ==
3661 23:07:20.352377 Dram Type= 6, Freq= 0, CH_1, rank 1
3662 23:07:20.355664 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3663 23:07:20.355770 ==
3664 23:07:20.355864 RX Vref Scan: 0
3665 23:07:20.355951
3666 23:07:20.358828 RX Vref 0 -> 0, step: 1
3667 23:07:20.358903
3668 23:07:20.362467 RX Delay -21 -> 252, step: 4
3669 23:07:20.365754 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3670 23:07:20.372210 iDelay=195, Bit 1, Center 108 (43 ~ 174) 132
3671 23:07:20.375467 iDelay=195, Bit 2, Center 102 (31 ~ 174) 144
3672 23:07:20.378746 iDelay=195, Bit 3, Center 110 (43 ~ 178) 136
3673 23:07:20.382263 iDelay=195, Bit 4, Center 110 (43 ~ 178) 136
3674 23:07:20.385376 iDelay=195, Bit 5, Center 122 (51 ~ 194) 144
3675 23:07:20.391986 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3676 23:07:20.395225 iDelay=195, Bit 7, Center 110 (43 ~ 178) 136
3677 23:07:20.398257 iDelay=195, Bit 8, Center 94 (31 ~ 158) 128
3678 23:07:20.401715 iDelay=195, Bit 9, Center 104 (39 ~ 170) 132
3679 23:07:20.408209 iDelay=195, Bit 10, Center 112 (47 ~ 178) 132
3680 23:07:20.411573 iDelay=195, Bit 11, Center 104 (39 ~ 170) 132
3681 23:07:20.414937 iDelay=195, Bit 12, Center 116 (51 ~ 182) 132
3682 23:07:20.418197 iDelay=195, Bit 13, Center 116 (51 ~ 182) 132
3683 23:07:20.421648 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3684 23:07:20.428347 iDelay=195, Bit 15, Center 116 (51 ~ 182) 132
3685 23:07:20.428450 ==
3686 23:07:20.431676 Dram Type= 6, Freq= 0, CH_1, rank 1
3687 23:07:20.434856 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3688 23:07:20.434929 ==
3689 23:07:20.435010 DQS Delay:
3690 23:07:20.438206 DQS0 = 0, DQS1 = 0
3691 23:07:20.438283 DQM Delay:
3692 23:07:20.441378 DQM0 = 112, DQM1 = 109
3693 23:07:20.441483 DQ Delay:
3694 23:07:20.444658 DQ0 =114, DQ1 =108, DQ2 =102, DQ3 =110
3695 23:07:20.448354 DQ4 =110, DQ5 =122, DQ6 =122, DQ7 =110
3696 23:07:20.451532 DQ8 =94, DQ9 =104, DQ10 =112, DQ11 =104
3697 23:07:20.454575 DQ12 =116, DQ13 =116, DQ14 =116, DQ15 =116
3698 23:07:20.457848
3699 23:07:20.457923
3700 23:07:20.464348 [DQSOSCAuto] RK1, (LSB)MR18= 0xf807, (MSB)MR19= 0x304, tDQSOscB0 = 407 ps tDQSOscB1 = 413 ps
3701 23:07:20.467840 CH1 RK1: MR19=304, MR18=F807
3702 23:07:20.474276 CH1_RK1: MR19=0x304, MR18=0xF807, DQSOSC=407, MR23=63, INC=39, DEC=26
3703 23:07:20.478108 [RxdqsGatingPostProcess] freq 1200
3704 23:07:20.480866 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3705 23:07:20.484763 best DQS0 dly(2T, 0.5T) = (0, 11)
3706 23:07:20.487978 best DQS1 dly(2T, 0.5T) = (0, 11)
3707 23:07:20.491294 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3708 23:07:20.494354 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3709 23:07:20.497728 best DQS0 dly(2T, 0.5T) = (0, 11)
3710 23:07:20.500954 best DQS1 dly(2T, 0.5T) = (0, 11)
3711 23:07:20.504200 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3712 23:07:20.507412 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3713 23:07:20.511068 Pre-setting of DQS Precalculation
3714 23:07:20.514323 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3715 23:07:20.521038 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3716 23:07:20.530996 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3717 23:07:20.531092
3718 23:07:20.531185
3719 23:07:20.534038 [Calibration Summary] 2400 Mbps
3720 23:07:20.534160 CH 0, Rank 0
3721 23:07:20.537367 SW Impedance : PASS
3722 23:07:20.537449 DUTY Scan : NO K
3723 23:07:20.540580 ZQ Calibration : PASS
3724 23:07:20.543921 Jitter Meter : NO K
3725 23:07:20.544002 CBT Training : PASS
3726 23:07:20.547185 Write leveling : PASS
3727 23:07:20.547266 RX DQS gating : PASS
3728 23:07:20.550848 RX DQ/DQS(RDDQC) : PASS
3729 23:07:20.554035 TX DQ/DQS : PASS
3730 23:07:20.554116 RX DATLAT : PASS
3731 23:07:20.557355 RX DQ/DQS(Engine): PASS
3732 23:07:20.560446 TX OE : NO K
3733 23:07:20.560544 All Pass.
3734 23:07:20.560609
3735 23:07:20.560670 CH 0, Rank 1
3736 23:07:20.563933 SW Impedance : PASS
3737 23:07:20.566983 DUTY Scan : NO K
3738 23:07:20.567064 ZQ Calibration : PASS
3739 23:07:20.570713 Jitter Meter : NO K
3740 23:07:20.573525 CBT Training : PASS
3741 23:07:20.573608 Write leveling : PASS
3742 23:07:20.576733 RX DQS gating : PASS
3743 23:07:20.580586 RX DQ/DQS(RDDQC) : PASS
3744 23:07:20.580667 TX DQ/DQS : PASS
3745 23:07:20.583837 RX DATLAT : PASS
3746 23:07:20.586925 RX DQ/DQS(Engine): PASS
3747 23:07:20.587008 TX OE : NO K
3748 23:07:20.590199 All Pass.
3749 23:07:20.590281
3750 23:07:20.590345 CH 1, Rank 0
3751 23:07:20.593388 SW Impedance : PASS
3752 23:07:20.593470 DUTY Scan : NO K
3753 23:07:20.596564 ZQ Calibration : PASS
3754 23:07:20.600405 Jitter Meter : NO K
3755 23:07:20.600486 CBT Training : PASS
3756 23:07:20.603611 Write leveling : PASS
3757 23:07:20.606550 RX DQS gating : PASS
3758 23:07:20.606644 RX DQ/DQS(RDDQC) : PASS
3759 23:07:20.609943 TX DQ/DQS : PASS
3760 23:07:20.613386 RX DATLAT : PASS
3761 23:07:20.613469 RX DQ/DQS(Engine): PASS
3762 23:07:20.617032 TX OE : NO K
3763 23:07:20.617116 All Pass.
3764 23:07:20.617180
3765 23:07:20.620040 CH 1, Rank 1
3766 23:07:20.620123 SW Impedance : PASS
3767 23:07:20.623795 DUTY Scan : NO K
3768 23:07:20.623877 ZQ Calibration : PASS
3769 23:07:20.626846 Jitter Meter : NO K
3770 23:07:20.630114 CBT Training : PASS
3771 23:07:20.630197 Write leveling : PASS
3772 23:07:20.633577 RX DQS gating : PASS
3773 23:07:20.637025 RX DQ/DQS(RDDQC) : PASS
3774 23:07:20.637140 TX DQ/DQS : PASS
3775 23:07:20.640026 RX DATLAT : PASS
3776 23:07:20.643348 RX DQ/DQS(Engine): PASS
3777 23:07:20.643430 TX OE : NO K
3778 23:07:20.646523 All Pass.
3779 23:07:20.646605
3780 23:07:20.646670 DramC Write-DBI off
3781 23:07:20.650280 PER_BANK_REFRESH: Hybrid Mode
3782 23:07:20.650363 TX_TRACKING: ON
3783 23:07:20.659843 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3784 23:07:20.663122 [FAST_K] Save calibration result to emmc
3785 23:07:20.666606 dramc_set_vcore_voltage set vcore to 650000
3786 23:07:20.669967 Read voltage for 600, 5
3787 23:07:20.670050 Vio18 = 0
3788 23:07:20.673128 Vcore = 650000
3789 23:07:20.673211 Vdram = 0
3790 23:07:20.673276 Vddq = 0
3791 23:07:20.676685 Vmddr = 0
3792 23:07:20.680019 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3793 23:07:20.686698 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3794 23:07:20.686782 MEM_TYPE=3, freq_sel=19
3795 23:07:20.689925 sv_algorithm_assistance_LP4_1600
3796 23:07:20.696478 ============ PULL DRAM RESETB DOWN ============
3797 23:07:20.699848 ========== PULL DRAM RESETB DOWN end =========
3798 23:07:20.702960 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3799 23:07:20.706136 ===================================
3800 23:07:20.709810 LPDDR4 DRAM CONFIGURATION
3801 23:07:20.713019 ===================================
3802 23:07:20.713106 EX_ROW_EN[0] = 0x0
3803 23:07:20.716305 EX_ROW_EN[1] = 0x0
3804 23:07:20.719706 LP4Y_EN = 0x0
3805 23:07:20.719851 WORK_FSP = 0x0
3806 23:07:20.722624 WL = 0x2
3807 23:07:20.722742 RL = 0x2
3808 23:07:20.725873 BL = 0x2
3809 23:07:20.725960 RPST = 0x0
3810 23:07:20.729544 RD_PRE = 0x0
3811 23:07:20.729620 WR_PRE = 0x1
3812 23:07:20.732481 WR_PST = 0x0
3813 23:07:20.732581 DBI_WR = 0x0
3814 23:07:20.735848 DBI_RD = 0x0
3815 23:07:20.735947 OTF = 0x1
3816 23:07:20.739093 ===================================
3817 23:07:20.742824 ===================================
3818 23:07:20.745973 ANA top config
3819 23:07:20.749131 ===================================
3820 23:07:20.749208 DLL_ASYNC_EN = 0
3821 23:07:20.752504 ALL_SLAVE_EN = 1
3822 23:07:20.755729 NEW_RANK_MODE = 1
3823 23:07:20.758981 DLL_IDLE_MODE = 1
3824 23:07:20.762301 LP45_APHY_COMB_EN = 1
3825 23:07:20.762374 TX_ODT_DIS = 1
3826 23:07:20.766052 NEW_8X_MODE = 1
3827 23:07:20.769171 ===================================
3828 23:07:20.772489 ===================================
3829 23:07:20.775625 data_rate = 1200
3830 23:07:20.778999 CKR = 1
3831 23:07:20.782182 DQ_P2S_RATIO = 8
3832 23:07:20.785675 ===================================
3833 23:07:20.789115 CA_P2S_RATIO = 8
3834 23:07:20.789190 DQ_CA_OPEN = 0
3835 23:07:20.792307 DQ_SEMI_OPEN = 0
3836 23:07:20.795634 CA_SEMI_OPEN = 0
3837 23:07:20.798779 CA_FULL_RATE = 0
3838 23:07:20.802637 DQ_CKDIV4_EN = 1
3839 23:07:20.805413 CA_CKDIV4_EN = 1
3840 23:07:20.805515 CA_PREDIV_EN = 0
3841 23:07:20.809154 PH8_DLY = 0
3842 23:07:20.812245 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3843 23:07:20.815348 DQ_AAMCK_DIV = 4
3844 23:07:20.818715 CA_AAMCK_DIV = 4
3845 23:07:20.818791 CA_ADMCK_DIV = 4
3846 23:07:20.821962 DQ_TRACK_CA_EN = 0
3847 23:07:20.825630 CA_PICK = 600
3848 23:07:20.828651 CA_MCKIO = 600
3849 23:07:20.832266 MCKIO_SEMI = 0
3850 23:07:20.835449 PLL_FREQ = 2288
3851 23:07:20.839187 DQ_UI_PI_RATIO = 32
3852 23:07:20.839264 CA_UI_PI_RATIO = 0
3853 23:07:20.842419 ===================================
3854 23:07:20.845581 ===================================
3855 23:07:20.848742 memory_type:LPDDR4
3856 23:07:20.852174 GP_NUM : 10
3857 23:07:20.852248 SRAM_EN : 1
3858 23:07:20.855502 MD32_EN : 0
3859 23:07:20.858675 ===================================
3860 23:07:20.862059 [ANA_INIT] >>>>>>>>>>>>>>
3861 23:07:20.865602 <<<<<< [CONFIGURE PHASE]: ANA_TX
3862 23:07:20.868673 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3863 23:07:20.872300 ===================================
3864 23:07:20.872401 data_rate = 1200,PCW = 0X5800
3865 23:07:20.875453 ===================================
3866 23:07:20.882157 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3867 23:07:20.885328 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3868 23:07:20.891957 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3869 23:07:20.895698 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3870 23:07:20.898437 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3871 23:07:20.901987 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3872 23:07:20.905424 [ANA_INIT] flow start
3873 23:07:20.908571 [ANA_INIT] PLL >>>>>>>>
3874 23:07:20.908675 [ANA_INIT] PLL <<<<<<<<
3875 23:07:20.911876 [ANA_INIT] MIDPI >>>>>>>>
3876 23:07:20.915017 [ANA_INIT] MIDPI <<<<<<<<
3877 23:07:20.915092 [ANA_INIT] DLL >>>>>>>>
3878 23:07:20.918681 [ANA_INIT] flow end
3879 23:07:20.921917 ============ LP4 DIFF to SE enter ============
3880 23:07:20.925253 ============ LP4 DIFF to SE exit ============
3881 23:07:20.928400 [ANA_INIT] <<<<<<<<<<<<<
3882 23:07:20.931689 [Flow] Enable top DCM control >>>>>
3883 23:07:20.935044 [Flow] Enable top DCM control <<<<<
3884 23:07:20.938221 Enable DLL master slave shuffle
3885 23:07:20.945113 ==============================================================
3886 23:07:20.945216 Gating Mode config
3887 23:07:20.951598 ==============================================================
3888 23:07:20.954851 Config description:
3889 23:07:20.961549 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3890 23:07:20.968252 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3891 23:07:20.974568 SELPH_MODE 0: By rank 1: By Phase
3892 23:07:20.981416 ==============================================================
3893 23:07:20.981530 GAT_TRACK_EN = 1
3894 23:07:20.984766 RX_GATING_MODE = 2
3895 23:07:20.987996 RX_GATING_TRACK_MODE = 2
3896 23:07:20.991192 SELPH_MODE = 1
3897 23:07:20.994375 PICG_EARLY_EN = 1
3898 23:07:20.998024 VALID_LAT_VALUE = 1
3899 23:07:21.004347 ==============================================================
3900 23:07:21.007382 Enter into Gating configuration >>>>
3901 23:07:21.011121 Exit from Gating configuration <<<<
3902 23:07:21.014244 Enter into DVFS_PRE_config >>>>>
3903 23:07:21.024261 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3904 23:07:21.027549 Exit from DVFS_PRE_config <<<<<
3905 23:07:21.030823 Enter into PICG configuration >>>>
3906 23:07:21.034177 Exit from PICG configuration <<<<
3907 23:07:21.037355 [RX_INPUT] configuration >>>>>
3908 23:07:21.040560 [RX_INPUT] configuration <<<<<
3909 23:07:21.043825 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3910 23:07:21.050361 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3911 23:07:21.057244 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3912 23:07:21.060728 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3913 23:07:21.067215 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3914 23:07:21.073515 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3915 23:07:21.077151 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3916 23:07:21.083518 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3917 23:07:21.086941 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3918 23:07:21.090347 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3919 23:07:21.093562 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3920 23:07:21.100189 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3921 23:07:21.103402 ===================================
3922 23:07:21.103512 LPDDR4 DRAM CONFIGURATION
3923 23:07:21.107202 ===================================
3924 23:07:21.110258 EX_ROW_EN[0] = 0x0
3925 23:07:21.113362 EX_ROW_EN[1] = 0x0
3926 23:07:21.113461 LP4Y_EN = 0x0
3927 23:07:21.117018 WORK_FSP = 0x0
3928 23:07:21.117091 WL = 0x2
3929 23:07:21.120136 RL = 0x2
3930 23:07:21.120216 BL = 0x2
3931 23:07:21.123523 RPST = 0x0
3932 23:07:21.123599 RD_PRE = 0x0
3933 23:07:21.126672 WR_PRE = 0x1
3934 23:07:21.126745 WR_PST = 0x0
3935 23:07:21.129960 DBI_WR = 0x0
3936 23:07:21.130032 DBI_RD = 0x0
3937 23:07:21.133275 OTF = 0x1
3938 23:07:21.137003 ===================================
3939 23:07:21.140227 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3940 23:07:21.143429 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3941 23:07:21.150001 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3942 23:07:21.153192 ===================================
3943 23:07:21.153302 LPDDR4 DRAM CONFIGURATION
3944 23:07:21.156670 ===================================
3945 23:07:21.160124 EX_ROW_EN[0] = 0x10
3946 23:07:21.163274 EX_ROW_EN[1] = 0x0
3947 23:07:21.163349 LP4Y_EN = 0x0
3948 23:07:21.166636 WORK_FSP = 0x0
3949 23:07:21.166708 WL = 0x2
3950 23:07:21.169728 RL = 0x2
3951 23:07:21.169835 BL = 0x2
3952 23:07:21.172951 RPST = 0x0
3953 23:07:21.173057 RD_PRE = 0x0
3954 23:07:21.176344 WR_PRE = 0x1
3955 23:07:21.176450 WR_PST = 0x0
3956 23:07:21.179789 DBI_WR = 0x0
3957 23:07:21.179898 DBI_RD = 0x0
3958 23:07:21.182960 OTF = 0x1
3959 23:07:21.186173 ===================================
3960 23:07:21.192986 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3961 23:07:21.196058 nWR fixed to 30
3962 23:07:21.199679 [ModeRegInit_LP4] CH0 RK0
3963 23:07:21.199781 [ModeRegInit_LP4] CH0 RK1
3964 23:07:21.202792 [ModeRegInit_LP4] CH1 RK0
3965 23:07:21.206063 [ModeRegInit_LP4] CH1 RK1
3966 23:07:21.206134 match AC timing 17
3967 23:07:21.212841 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3968 23:07:21.215907 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3969 23:07:21.219143 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3970 23:07:21.225794 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3971 23:07:21.229140 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3972 23:07:21.229214 ==
3973 23:07:21.232312 Dram Type= 6, Freq= 0, CH_0, rank 0
3974 23:07:21.235730 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3975 23:07:21.235803 ==
3976 23:07:21.242695 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3977 23:07:21.249061 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3978 23:07:21.252418 [CA 0] Center 37 (7~67) winsize 61
3979 23:07:21.255661 [CA 1] Center 37 (7~67) winsize 61
3980 23:07:21.259413 [CA 2] Center 35 (5~65) winsize 61
3981 23:07:21.262356 [CA 3] Center 35 (5~65) winsize 61
3982 23:07:21.265800 [CA 4] Center 34 (4~65) winsize 62
3983 23:07:21.269071 [CA 5] Center 34 (4~64) winsize 61
3984 23:07:21.269149
3985 23:07:21.272202 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3986 23:07:21.272299
3987 23:07:21.275803 [CATrainingPosCal] consider 1 rank data
3988 23:07:21.278950 u2DelayCellTimex100 = 270/100 ps
3989 23:07:21.282270 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
3990 23:07:21.285725 CA1 delay=37 (7~67),Diff = 3 PI (28 cell)
3991 23:07:21.289124 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
3992 23:07:21.292437 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
3993 23:07:21.295533 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3994 23:07:21.299051 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3995 23:07:21.299125
3996 23:07:21.305409 CA PerBit enable=1, Macro0, CA PI delay=34
3997 23:07:21.305544
3998 23:07:21.308973 [CBTSetCACLKResult] CA Dly = 34
3999 23:07:21.309044 CS Dly: 5 (0~36)
4000 23:07:21.309105 ==
4001 23:07:21.311985 Dram Type= 6, Freq= 0, CH_0, rank 1
4002 23:07:21.315225 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4003 23:07:21.315298 ==
4004 23:07:21.322024 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4005 23:07:21.328547 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4006 23:07:21.332326 [CA 0] Center 37 (7~67) winsize 61
4007 23:07:21.335430 [CA 1] Center 37 (7~67) winsize 61
4008 23:07:21.338527 [CA 2] Center 35 (5~65) winsize 61
4009 23:07:21.342062 [CA 3] Center 35 (5~65) winsize 61
4010 23:07:21.345169 [CA 4] Center 34 (4~65) winsize 62
4011 23:07:21.348403 [CA 5] Center 34 (4~64) winsize 61
4012 23:07:21.348504
4013 23:07:21.351751 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4014 23:07:21.351822
4015 23:07:21.354882 [CATrainingPosCal] consider 2 rank data
4016 23:07:21.358608 u2DelayCellTimex100 = 270/100 ps
4017 23:07:21.362007 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
4018 23:07:21.365140 CA1 delay=37 (7~67),Diff = 3 PI (28 cell)
4019 23:07:21.368265 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
4020 23:07:21.371623 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
4021 23:07:21.378394 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4022 23:07:21.381909 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4023 23:07:21.382019
4024 23:07:21.385202 CA PerBit enable=1, Macro0, CA PI delay=34
4025 23:07:21.385300
4026 23:07:21.388370 [CBTSetCACLKResult] CA Dly = 34
4027 23:07:21.388447 CS Dly: 5 (0~36)
4028 23:07:21.388511
4029 23:07:21.391617 ----->DramcWriteLeveling(PI) begin...
4030 23:07:21.391720 ==
4031 23:07:21.394884 Dram Type= 6, Freq= 0, CH_0, rank 0
4032 23:07:21.401722 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4033 23:07:21.401825 ==
4034 23:07:21.404814 Write leveling (Byte 0): 33 => 33
4035 23:07:21.408169 Write leveling (Byte 1): 33 => 33
4036 23:07:21.408269 DramcWriteLeveling(PI) end<-----
4037 23:07:21.408360
4038 23:07:21.411508 ==
4039 23:07:21.414520 Dram Type= 6, Freq= 0, CH_0, rank 0
4040 23:07:21.417977 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4041 23:07:21.418115 ==
4042 23:07:21.421044 [Gating] SW mode calibration
4043 23:07:21.427887 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4044 23:07:21.431058 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4045 23:07:21.437958 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4046 23:07:21.441324 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4047 23:07:21.444656 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4048 23:07:21.451042 0 9 12 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
4049 23:07:21.454291 0 9 16 | B1->B0 | 2f2f 2c2c | 1 0 | (1 0) (0 0)
4050 23:07:21.457861 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4051 23:07:21.464326 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4052 23:07:21.467581 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4053 23:07:21.470977 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4054 23:07:21.477364 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4055 23:07:21.481019 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4056 23:07:21.484162 0 10 12 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
4057 23:07:21.491016 0 10 16 | B1->B0 | 3434 3838 | 0 1 | (0 0) (0 0)
4058 23:07:21.493954 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4059 23:07:21.497311 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4060 23:07:21.504151 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4061 23:07:21.507410 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4062 23:07:21.510594 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4063 23:07:21.517173 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4064 23:07:21.520495 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4065 23:07:21.523669 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4066 23:07:21.530633 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4067 23:07:21.534034 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4068 23:07:21.536981 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4069 23:07:21.543560 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4070 23:07:21.546890 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4071 23:07:21.550139 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4072 23:07:21.557196 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4073 23:07:21.560190 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4074 23:07:21.563563 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4075 23:07:21.569968 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4076 23:07:21.573844 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4077 23:07:21.576563 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4078 23:07:21.583519 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4079 23:07:21.586786 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4080 23:07:21.589981 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4081 23:07:21.593595 Total UI for P1: 0, mck2ui 16
4082 23:07:21.596801 best dqsien dly found for B0: ( 0, 13, 10)
4083 23:07:21.599825 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4084 23:07:21.606527 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4085 23:07:21.610176 Total UI for P1: 0, mck2ui 16
4086 23:07:21.613373 best dqsien dly found for B1: ( 0, 13, 16)
4087 23:07:21.616706 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4088 23:07:21.619986 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4089 23:07:21.620061
4090 23:07:21.623080 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4091 23:07:21.626737 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4092 23:07:21.629661 [Gating] SW calibration Done
4093 23:07:21.629735 ==
4094 23:07:21.633266 Dram Type= 6, Freq= 0, CH_0, rank 0
4095 23:07:21.636738 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4096 23:07:21.636843 ==
4097 23:07:21.639769 RX Vref Scan: 0
4098 23:07:21.639868
4099 23:07:21.643046 RX Vref 0 -> 0, step: 1
4100 23:07:21.643145
4101 23:07:21.643246 RX Delay -230 -> 252, step: 16
4102 23:07:21.649721 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4103 23:07:21.652937 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4104 23:07:21.656267 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4105 23:07:21.659890 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4106 23:07:21.666571 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4107 23:07:21.669957 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4108 23:07:21.673376 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4109 23:07:21.676575 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4110 23:07:21.679734 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4111 23:07:21.686356 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4112 23:07:21.689822 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4113 23:07:21.692904 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4114 23:07:21.696194 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4115 23:07:21.703175 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4116 23:07:21.706436 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4117 23:07:21.709679 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4118 23:07:21.709758 ==
4119 23:07:21.712855 Dram Type= 6, Freq= 0, CH_0, rank 0
4120 23:07:21.716124 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4121 23:07:21.719460 ==
4122 23:07:21.719541 DQS Delay:
4123 23:07:21.719639 DQS0 = 0, DQS1 = 0
4124 23:07:21.722971 DQM Delay:
4125 23:07:21.723060 DQM0 = 40, DQM1 = 30
4126 23:07:21.726317 DQ Delay:
4127 23:07:21.729463 DQ0 =33, DQ1 =41, DQ2 =41, DQ3 =41
4128 23:07:21.732698 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4129 23:07:21.735817 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4130 23:07:21.739411 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =41
4131 23:07:21.739520
4132 23:07:21.739612
4133 23:07:21.739710 ==
4134 23:07:21.742672 Dram Type= 6, Freq= 0, CH_0, rank 0
4135 23:07:21.745698 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4136 23:07:21.745807 ==
4137 23:07:21.745898
4138 23:07:21.745995
4139 23:07:21.749232 TX Vref Scan disable
4140 23:07:21.749329 == TX Byte 0 ==
4141 23:07:21.755984 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4142 23:07:21.759257 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4143 23:07:21.759348 == TX Byte 1 ==
4144 23:07:21.765755 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4145 23:07:21.769074 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4146 23:07:21.769175 ==
4147 23:07:21.772245 Dram Type= 6, Freq= 0, CH_0, rank 0
4148 23:07:21.775526 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4149 23:07:21.775617 ==
4150 23:07:21.775710
4151 23:07:21.778696
4152 23:07:21.778806 TX Vref Scan disable
4153 23:07:21.782667 == TX Byte 0 ==
4154 23:07:21.785664 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4155 23:07:21.788877 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4156 23:07:21.792540 == TX Byte 1 ==
4157 23:07:21.795839 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4158 23:07:21.802359 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4159 23:07:21.802452
4160 23:07:21.802517 [DATLAT]
4161 23:07:21.802577 Freq=600, CH0 RK0
4162 23:07:21.802638
4163 23:07:21.805939 DATLAT Default: 0x9
4164 23:07:21.806015 0, 0xFFFF, sum = 0
4165 23:07:21.809362 1, 0xFFFF, sum = 0
4166 23:07:21.809463 2, 0xFFFF, sum = 0
4167 23:07:21.812677 3, 0xFFFF, sum = 0
4168 23:07:21.812785 4, 0xFFFF, sum = 0
4169 23:07:21.815846 5, 0xFFFF, sum = 0
4170 23:07:21.818984 6, 0xFFFF, sum = 0
4171 23:07:21.819059 7, 0xFFFF, sum = 0
4172 23:07:21.819122 8, 0x0, sum = 1
4173 23:07:21.822537 9, 0x0, sum = 2
4174 23:07:21.822616 10, 0x0, sum = 3
4175 23:07:21.825964 11, 0x0, sum = 4
4176 23:07:21.826039 best_step = 9
4177 23:07:21.826120
4178 23:07:21.826181 ==
4179 23:07:21.829309 Dram Type= 6, Freq= 0, CH_0, rank 0
4180 23:07:21.835989 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4181 23:07:21.836096 ==
4182 23:07:21.836190 RX Vref Scan: 1
4183 23:07:21.836282
4184 23:07:21.839031 RX Vref 0 -> 0, step: 1
4185 23:07:21.839128
4186 23:07:21.842144 RX Delay -195 -> 252, step: 8
4187 23:07:21.842222
4188 23:07:21.845891 Set Vref, RX VrefLevel [Byte0]: 60
4189 23:07:21.849118 [Byte1]: 58
4190 23:07:21.849216
4191 23:07:21.852377 Final RX Vref Byte 0 = 60 to rank0
4192 23:07:21.855702 Final RX Vref Byte 1 = 58 to rank0
4193 23:07:21.858905 Final RX Vref Byte 0 = 60 to rank1
4194 23:07:21.862265 Final RX Vref Byte 1 = 58 to rank1==
4195 23:07:21.865323 Dram Type= 6, Freq= 0, CH_0, rank 0
4196 23:07:21.868645 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4197 23:07:21.868742 ==
4198 23:07:21.872333 DQS Delay:
4199 23:07:21.872431 DQS0 = 0, DQS1 = 0
4200 23:07:21.875540 DQM Delay:
4201 23:07:21.875639 DQM0 = 34, DQM1 = 29
4202 23:07:21.875739 DQ Delay:
4203 23:07:21.878859 DQ0 =36, DQ1 =36, DQ2 =32, DQ3 =32
4204 23:07:21.882069 DQ4 =32, DQ5 =20, DQ6 =40, DQ7 =44
4205 23:07:21.885209 DQ8 =20, DQ9 =16, DQ10 =28, DQ11 =20
4206 23:07:21.888556 DQ12 =36, DQ13 =36, DQ14 =44, DQ15 =36
4207 23:07:21.888656
4208 23:07:21.888745
4209 23:07:21.898354 [DQSOSCAuto] RK0, (LSB)MR18= 0x3e3c, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 398 ps
4210 23:07:21.902067 CH0 RK0: MR19=808, MR18=3E3C
4211 23:07:21.908397 CH0_RK0: MR19=0x808, MR18=0x3E3C, DQSOSC=398, MR23=63, INC=165, DEC=110
4212 23:07:21.908501
4213 23:07:21.912031 ----->DramcWriteLeveling(PI) begin...
4214 23:07:21.912132 ==
4215 23:07:21.915325 Dram Type= 6, Freq= 0, CH_0, rank 1
4216 23:07:21.918588 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4217 23:07:21.918666 ==
4218 23:07:21.922044 Write leveling (Byte 0): 33 => 33
4219 23:07:21.925157 Write leveling (Byte 1): 29 => 29
4220 23:07:21.928222 DramcWriteLeveling(PI) end<-----
4221 23:07:21.928322
4222 23:07:21.928412 ==
4223 23:07:21.931930 Dram Type= 6, Freq= 0, CH_0, rank 1
4224 23:07:21.935038 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4225 23:07:21.935114 ==
4226 23:07:21.938341 [Gating] SW mode calibration
4227 23:07:21.944769 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4228 23:07:21.951344 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4229 23:07:21.954592 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4230 23:07:21.958192 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4231 23:07:21.964717 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4232 23:07:21.967998 0 9 12 | B1->B0 | 3434 2e2e | 1 1 | (1 1) (1 0)
4233 23:07:21.971283 0 9 16 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
4234 23:07:21.978041 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4235 23:07:21.981270 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4236 23:07:21.984633 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4237 23:07:21.991160 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4238 23:07:21.994906 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4239 23:07:21.997728 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4240 23:07:22.004720 0 10 12 | B1->B0 | 2323 3535 | 0 1 | (0 0) (0 0)
4241 23:07:22.007801 0 10 16 | B1->B0 | 3838 4343 | 0 0 | (0 0) (0 0)
4242 23:07:22.011192 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4243 23:07:22.017846 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4244 23:07:22.021361 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4245 23:07:22.024757 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4246 23:07:22.030947 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4247 23:07:22.034164 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4248 23:07:22.037353 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4249 23:07:22.044385 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4250 23:07:22.047765 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4251 23:07:22.051034 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4252 23:07:22.054350 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4253 23:07:22.060811 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4254 23:07:22.064259 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4255 23:07:22.067407 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4256 23:07:22.073919 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4257 23:07:22.077471 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4258 23:07:22.080600 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4259 23:07:22.087200 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4260 23:07:22.090993 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4261 23:07:22.093820 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4262 23:07:22.100867 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4263 23:07:22.104135 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4264 23:07:22.107301 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4265 23:07:22.110469 Total UI for P1: 0, mck2ui 16
4266 23:07:22.114212 best dqsien dly found for B0: ( 0, 13, 10)
4267 23:07:22.120400 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4268 23:07:22.123959 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4269 23:07:22.127452 Total UI for P1: 0, mck2ui 16
4270 23:07:22.130423 best dqsien dly found for B1: ( 0, 13, 16)
4271 23:07:22.134074 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4272 23:07:22.137229 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4273 23:07:22.137334
4274 23:07:22.140625 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4275 23:07:22.143760 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4276 23:07:22.147011 [Gating] SW calibration Done
4277 23:07:22.147111 ==
4278 23:07:22.150830 Dram Type= 6, Freq= 0, CH_0, rank 1
4279 23:07:22.154063 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4280 23:07:22.157230 ==
4281 23:07:22.157332 RX Vref Scan: 0
4282 23:07:22.157433
4283 23:07:22.160615 RX Vref 0 -> 0, step: 1
4284 23:07:22.160716
4285 23:07:22.163911 RX Delay -230 -> 252, step: 16
4286 23:07:22.167018 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4287 23:07:22.170441 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4288 23:07:22.173633 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4289 23:07:22.180363 iDelay=218, Bit 3, Center 25 (-150 ~ 201) 352
4290 23:07:22.183747 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4291 23:07:22.187075 iDelay=218, Bit 5, Center 17 (-150 ~ 185) 336
4292 23:07:22.190500 iDelay=218, Bit 6, Center 41 (-134 ~ 217) 352
4293 23:07:22.193763 iDelay=218, Bit 7, Center 41 (-134 ~ 217) 352
4294 23:07:22.200259 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4295 23:07:22.203817 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4296 23:07:22.206743 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4297 23:07:22.210362 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4298 23:07:22.216977 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4299 23:07:22.219956 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4300 23:07:22.223494 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4301 23:07:22.226642 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4302 23:07:22.230166 ==
4303 23:07:22.230274 Dram Type= 6, Freq= 0, CH_0, rank 1
4304 23:07:22.236652 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4305 23:07:22.236730 ==
4306 23:07:22.236794 DQS Delay:
4307 23:07:22.239923 DQS0 = 0, DQS1 = 0
4308 23:07:22.240024 DQM Delay:
4309 23:07:22.243133 DQM0 = 32, DQM1 = 27
4310 23:07:22.243235 DQ Delay:
4311 23:07:22.246411 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =25
4312 23:07:22.250164 DQ4 =33, DQ5 =17, DQ6 =41, DQ7 =41
4313 23:07:22.253387 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4314 23:07:22.256682 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4315 23:07:22.256773
4316 23:07:22.256837
4317 23:07:22.256895 ==
4318 23:07:22.259735 Dram Type= 6, Freq= 0, CH_0, rank 1
4319 23:07:22.263391 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4320 23:07:22.263495 ==
4321 23:07:22.263586
4322 23:07:22.263684
4323 23:07:22.266342 TX Vref Scan disable
4324 23:07:22.270034 == TX Byte 0 ==
4325 23:07:22.273297 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4326 23:07:22.276485 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4327 23:07:22.279658 == TX Byte 1 ==
4328 23:07:22.283172 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4329 23:07:22.286389 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4330 23:07:22.286499 ==
4331 23:07:22.289403 Dram Type= 6, Freq= 0, CH_0, rank 1
4332 23:07:22.296290 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4333 23:07:22.296367 ==
4334 23:07:22.296431
4335 23:07:22.296489
4336 23:07:22.296569 TX Vref Scan disable
4337 23:07:22.300692 == TX Byte 0 ==
4338 23:07:22.304086 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4339 23:07:22.310478 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4340 23:07:22.310567 == TX Byte 1 ==
4341 23:07:22.313701 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4342 23:07:22.320256 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4343 23:07:22.320358
4344 23:07:22.320460 [DATLAT]
4345 23:07:22.320550 Freq=600, CH0 RK1
4346 23:07:22.320636
4347 23:07:22.323527 DATLAT Default: 0x9
4348 23:07:22.323636 0, 0xFFFF, sum = 0
4349 23:07:22.327167 1, 0xFFFF, sum = 0
4350 23:07:22.327244 2, 0xFFFF, sum = 0
4351 23:07:22.330297 3, 0xFFFF, sum = 0
4352 23:07:22.333511 4, 0xFFFF, sum = 0
4353 23:07:22.333661 5, 0xFFFF, sum = 0
4354 23:07:22.336855 6, 0xFFFF, sum = 0
4355 23:07:22.336965 7, 0xFFFF, sum = 0
4356 23:07:22.340057 8, 0x0, sum = 1
4357 23:07:22.340160 9, 0x0, sum = 2
4358 23:07:22.340252 10, 0x0, sum = 3
4359 23:07:22.343758 11, 0x0, sum = 4
4360 23:07:22.343861 best_step = 9
4361 23:07:22.343953
4362 23:07:22.344043 ==
4363 23:07:22.347015 Dram Type= 6, Freq= 0, CH_0, rank 1
4364 23:07:22.353369 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4365 23:07:22.353482 ==
4366 23:07:22.353596 RX Vref Scan: 0
4367 23:07:22.353692
4368 23:07:22.356535 RX Vref 0 -> 0, step: 1
4369 23:07:22.356623
4370 23:07:22.359802 RX Delay -195 -> 252, step: 8
4371 23:07:22.366426 iDelay=205, Bit 0, Center 28 (-131 ~ 188) 320
4372 23:07:22.369926 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4373 23:07:22.372942 iDelay=205, Bit 2, Center 32 (-123 ~ 188) 312
4374 23:07:22.376572 iDelay=205, Bit 3, Center 28 (-131 ~ 188) 320
4375 23:07:22.379666 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4376 23:07:22.386436 iDelay=205, Bit 5, Center 24 (-131 ~ 180) 312
4377 23:07:22.389962 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4378 23:07:22.393250 iDelay=205, Bit 7, Center 44 (-115 ~ 204) 320
4379 23:07:22.396347 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4380 23:07:22.403140 iDelay=205, Bit 9, Center 12 (-147 ~ 172) 320
4381 23:07:22.406420 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4382 23:07:22.409404 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4383 23:07:22.413214 iDelay=205, Bit 12, Center 32 (-131 ~ 196) 328
4384 23:07:22.419476 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4385 23:07:22.422837 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4386 23:07:22.426067 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4387 23:07:22.426141 ==
4388 23:07:22.429300 Dram Type= 6, Freq= 0, CH_0, rank 1
4389 23:07:22.432880 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4390 23:07:22.432986 ==
4391 23:07:22.436062 DQS Delay:
4392 23:07:22.436165 DQS0 = 0, DQS1 = 0
4393 23:07:22.439335 DQM Delay:
4394 23:07:22.439419 DQM0 = 34, DQM1 = 27
4395 23:07:22.439508 DQ Delay:
4396 23:07:22.442408 DQ0 =28, DQ1 =36, DQ2 =32, DQ3 =28
4397 23:07:22.446229 DQ4 =36, DQ5 =24, DQ6 =44, DQ7 =44
4398 23:07:22.449530 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =20
4399 23:07:22.452561 DQ12 =32, DQ13 =36, DQ14 =36, DQ15 =36
4400 23:07:22.452634
4401 23:07:22.452695
4402 23:07:22.462462 [DQSOSCAuto] RK1, (LSB)MR18= 0x6736, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 390 ps
4403 23:07:22.465875 CH0 RK1: MR19=808, MR18=6736
4404 23:07:22.472458 CH0_RK1: MR19=0x808, MR18=0x6736, DQSOSC=390, MR23=63, INC=172, DEC=114
4405 23:07:22.472560 [RxdqsGatingPostProcess] freq 600
4406 23:07:22.479010 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4407 23:07:22.482145 Pre-setting of DQS Precalculation
4408 23:07:22.485640 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4409 23:07:22.488788 ==
4410 23:07:22.492399 Dram Type= 6, Freq= 0, CH_1, rank 0
4411 23:07:22.495699 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4412 23:07:22.495809 ==
4413 23:07:22.498790 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4414 23:07:22.505842 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4415 23:07:22.509433 [CA 0] Center 35 (5~66) winsize 62
4416 23:07:22.512777 [CA 1] Center 36 (6~66) winsize 61
4417 23:07:22.515943 [CA 2] Center 34 (4~65) winsize 62
4418 23:07:22.519303 [CA 3] Center 34 (4~65) winsize 62
4419 23:07:22.522777 [CA 4] Center 34 (4~65) winsize 62
4420 23:07:22.526278 [CA 5] Center 33 (3~64) winsize 62
4421 23:07:22.526371
4422 23:07:22.529129 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4423 23:07:22.529228
4424 23:07:22.532528 [CATrainingPosCal] consider 1 rank data
4425 23:07:22.536188 u2DelayCellTimex100 = 270/100 ps
4426 23:07:22.539161 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4427 23:07:22.546037 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4428 23:07:22.549160 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4429 23:07:22.552549 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4430 23:07:22.555782 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4431 23:07:22.559043 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4432 23:07:22.559117
4433 23:07:22.562613 CA PerBit enable=1, Macro0, CA PI delay=33
4434 23:07:22.562689
4435 23:07:22.565696 [CBTSetCACLKResult] CA Dly = 33
4436 23:07:22.565770 CS Dly: 4 (0~35)
4437 23:07:22.569066 ==
4438 23:07:22.572513 Dram Type= 6, Freq= 0, CH_1, rank 1
4439 23:07:22.575444 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4440 23:07:22.575545 ==
4441 23:07:22.579345 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4442 23:07:22.585421 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4443 23:07:22.589464 [CA 0] Center 36 (6~66) winsize 61
4444 23:07:22.592720 [CA 1] Center 36 (6~66) winsize 61
4445 23:07:22.596281 [CA 2] Center 34 (4~65) winsize 62
4446 23:07:22.599658 [CA 3] Center 34 (3~65) winsize 63
4447 23:07:22.602791 [CA 4] Center 34 (4~65) winsize 62
4448 23:07:22.605902 [CA 5] Center 33 (3~64) winsize 62
4449 23:07:22.606002
4450 23:07:22.609547 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4451 23:07:22.609621
4452 23:07:22.612552 [CATrainingPosCal] consider 2 rank data
4453 23:07:22.616334 u2DelayCellTimex100 = 270/100 ps
4454 23:07:22.619658 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4455 23:07:22.626075 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4456 23:07:22.629237 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4457 23:07:22.632517 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4458 23:07:22.636281 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4459 23:07:22.639251 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4460 23:07:22.639329
4461 23:07:22.642612 CA PerBit enable=1, Macro0, CA PI delay=33
4462 23:07:22.642682
4463 23:07:22.645905 [CBTSetCACLKResult] CA Dly = 33
4464 23:07:22.646003 CS Dly: 4 (0~36)
4465 23:07:22.649400
4466 23:07:22.652495 ----->DramcWriteLeveling(PI) begin...
4467 23:07:22.652566 ==
4468 23:07:22.655564 Dram Type= 6, Freq= 0, CH_1, rank 0
4469 23:07:22.658957 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4470 23:07:22.659066 ==
4471 23:07:22.662632 Write leveling (Byte 0): 27 => 27
4472 23:07:22.665904 Write leveling (Byte 1): 30 => 30
4473 23:07:22.668723 DramcWriteLeveling(PI) end<-----
4474 23:07:22.668823
4475 23:07:22.668914 ==
4476 23:07:22.672392 Dram Type= 6, Freq= 0, CH_1, rank 0
4477 23:07:22.675612 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4478 23:07:22.675685 ==
4479 23:07:22.678652 [Gating] SW mode calibration
4480 23:07:22.685733 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4481 23:07:22.692357 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4482 23:07:22.695755 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4483 23:07:22.698564 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4484 23:07:22.705561 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4485 23:07:22.708610 0 9 12 | B1->B0 | 3434 3434 | 0 0 | (0 1) (0 0)
4486 23:07:22.711875 0 9 16 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
4487 23:07:22.718712 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4488 23:07:22.721831 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4489 23:07:22.725247 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4490 23:07:22.731703 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4491 23:07:22.734849 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4492 23:07:22.738733 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4493 23:07:22.745060 0 10 12 | B1->B0 | 2727 2f2f | 0 1 | (0 0) (1 1)
4494 23:07:22.748218 0 10 16 | B1->B0 | 3f3f 4040 | 0 0 | (0 0) (0 0)
4495 23:07:22.751617 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4496 23:07:22.758393 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4497 23:07:22.761307 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4498 23:07:22.764640 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4499 23:07:22.771212 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4500 23:07:22.774768 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4501 23:07:22.777936 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4502 23:07:22.784406 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4503 23:07:22.787745 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4504 23:07:22.791152 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4505 23:07:22.797874 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4506 23:07:22.801352 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4507 23:07:22.804606 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4508 23:07:22.811254 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4509 23:07:22.814352 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4510 23:07:22.817603 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4511 23:07:22.824435 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4512 23:07:22.827632 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4513 23:07:22.831005 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4514 23:07:22.837481 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4515 23:07:22.840855 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4516 23:07:22.843995 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4517 23:07:22.850626 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4518 23:07:22.850730 Total UI for P1: 0, mck2ui 16
4519 23:07:22.854484 best dqsien dly found for B0: ( 0, 13, 10)
4520 23:07:22.860428 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4521 23:07:22.864175 Total UI for P1: 0, mck2ui 16
4522 23:07:22.867342 best dqsien dly found for B1: ( 0, 13, 12)
4523 23:07:22.870779 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4524 23:07:22.873734 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4525 23:07:22.873811
4526 23:07:22.877340 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4527 23:07:22.880501 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4528 23:07:22.883925 [Gating] SW calibration Done
4529 23:07:22.884028 ==
4530 23:07:22.887614 Dram Type= 6, Freq= 0, CH_1, rank 0
4531 23:07:22.890588 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4532 23:07:22.890661 ==
4533 23:07:22.893668 RX Vref Scan: 0
4534 23:07:22.893738
4535 23:07:22.896930 RX Vref 0 -> 0, step: 1
4536 23:07:22.897027
4537 23:07:22.900096 RX Delay -230 -> 252, step: 16
4538 23:07:22.903784 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4539 23:07:22.906927 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4540 23:07:22.910164 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4541 23:07:22.913626 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4542 23:07:22.920379 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4543 23:07:22.923354 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4544 23:07:22.926566 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4545 23:07:22.930320 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4546 23:07:22.936761 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4547 23:07:22.939921 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4548 23:07:22.943365 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4549 23:07:22.946445 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4550 23:07:22.953583 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4551 23:07:22.956969 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4552 23:07:22.960068 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4553 23:07:22.963201 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4554 23:07:22.963301 ==
4555 23:07:22.966539 Dram Type= 6, Freq= 0, CH_1, rank 0
4556 23:07:22.973126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4557 23:07:22.973227 ==
4558 23:07:22.973330 DQS Delay:
4559 23:07:22.976418 DQS0 = 0, DQS1 = 0
4560 23:07:22.976527 DQM Delay:
4561 23:07:22.976619 DQM0 = 39, DQM1 = 28
4562 23:07:22.979543 DQ Delay:
4563 23:07:22.983084 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =33
4564 23:07:22.986136 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4565 23:07:22.989785 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4566 23:07:22.993015 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4567 23:07:22.993116
4568 23:07:22.993207
4569 23:07:22.993304 ==
4570 23:07:22.996225 Dram Type= 6, Freq= 0, CH_1, rank 0
4571 23:07:22.999898 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4572 23:07:22.999973 ==
4573 23:07:23.000035
4574 23:07:23.000116
4575 23:07:23.003092 TX Vref Scan disable
4576 23:07:23.006016 == TX Byte 0 ==
4577 23:07:23.009669 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4578 23:07:23.012760 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4579 23:07:23.016082 == TX Byte 1 ==
4580 23:07:23.019247 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4581 23:07:23.022898 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4582 23:07:23.022973 ==
4583 23:07:23.026246 Dram Type= 6, Freq= 0, CH_1, rank 0
4584 23:07:23.029333 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4585 23:07:23.032796 ==
4586 23:07:23.032897
4587 23:07:23.032986
4588 23:07:23.033073 TX Vref Scan disable
4589 23:07:23.036456 == TX Byte 0 ==
4590 23:07:23.039839 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4591 23:07:23.046569 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4592 23:07:23.046678 == TX Byte 1 ==
4593 23:07:23.049868 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4594 23:07:23.056380 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4595 23:07:23.056482
4596 23:07:23.056577 [DATLAT]
4597 23:07:23.056665 Freq=600, CH1 RK0
4598 23:07:23.056755
4599 23:07:23.059696 DATLAT Default: 0x9
4600 23:07:23.059803 0, 0xFFFF, sum = 0
4601 23:07:23.062981 1, 0xFFFF, sum = 0
4602 23:07:23.063082 2, 0xFFFF, sum = 0
4603 23:07:23.066170 3, 0xFFFF, sum = 0
4604 23:07:23.069967 4, 0xFFFF, sum = 0
4605 23:07:23.070043 5, 0xFFFF, sum = 0
4606 23:07:23.073242 6, 0xFFFF, sum = 0
4607 23:07:23.073316 7, 0xFFFF, sum = 0
4608 23:07:23.077962 8, 0x0, sum = 1
4609 23:07:23.078089 9, 0x0, sum = 2
4610 23:07:23.078184 10, 0x0, sum = 3
4611 23:07:23.079818 11, 0x0, sum = 4
4612 23:07:23.079926 best_step = 9
4613 23:07:23.080015
4614 23:07:23.080112 ==
4615 23:07:23.082946 Dram Type= 6, Freq= 0, CH_1, rank 0
4616 23:07:23.089419 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4617 23:07:23.089541 ==
4618 23:07:23.089607 RX Vref Scan: 1
4619 23:07:23.089673
4620 23:07:23.093152 RX Vref 0 -> 0, step: 1
4621 23:07:23.093251
4622 23:07:23.096183 RX Delay -195 -> 252, step: 8
4623 23:07:23.096282
4624 23:07:23.099325 Set Vref, RX VrefLevel [Byte0]: 60
4625 23:07:23.103182 [Byte1]: 50
4626 23:07:23.103261
4627 23:07:23.106313 Final RX Vref Byte 0 = 60 to rank0
4628 23:07:23.109596 Final RX Vref Byte 1 = 50 to rank0
4629 23:07:23.112623 Final RX Vref Byte 0 = 60 to rank1
4630 23:07:23.115994 Final RX Vref Byte 1 = 50 to rank1==
4631 23:07:23.119354 Dram Type= 6, Freq= 0, CH_1, rank 0
4632 23:07:23.122643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4633 23:07:23.122753 ==
4634 23:07:23.126030 DQS Delay:
4635 23:07:23.126104 DQS0 = 0, DQS1 = 0
4636 23:07:23.129371 DQM Delay:
4637 23:07:23.129493 DQM0 = 38, DQM1 = 29
4638 23:07:23.129588 DQ Delay:
4639 23:07:23.132528 DQ0 =44, DQ1 =32, DQ2 =28, DQ3 =36
4640 23:07:23.135910 DQ4 =36, DQ5 =48, DQ6 =48, DQ7 =36
4641 23:07:23.139502 DQ8 =16, DQ9 =16, DQ10 =32, DQ11 =20
4642 23:07:23.142729 DQ12 =40, DQ13 =36, DQ14 =36, DQ15 =36
4643 23:07:23.142836
4644 23:07:23.142931
4645 23:07:23.152664 [DQSOSCAuto] RK0, (LSB)MR18= 0x2835, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 402 ps
4646 23:07:23.156114 CH1 RK0: MR19=808, MR18=2835
4647 23:07:23.162674 CH1_RK0: MR19=0x808, MR18=0x2835, DQSOSC=399, MR23=63, INC=164, DEC=109
4648 23:07:23.162753
4649 23:07:23.165810 ----->DramcWriteLeveling(PI) begin...
4650 23:07:23.165885 ==
4651 23:07:23.169018 Dram Type= 6, Freq= 0, CH_1, rank 1
4652 23:07:23.172322 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4653 23:07:23.172426 ==
4654 23:07:23.175588 Write leveling (Byte 0): 29 => 29
4655 23:07:23.179310 Write leveling (Byte 1): 31 => 31
4656 23:07:23.182629 DramcWriteLeveling(PI) end<-----
4657 23:07:23.182730
4658 23:07:23.182819 ==
4659 23:07:23.185857 Dram Type= 6, Freq= 0, CH_1, rank 1
4660 23:07:23.189197 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4661 23:07:23.189304 ==
4662 23:07:23.192225 [Gating] SW mode calibration
4663 23:07:23.198914 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4664 23:07:23.205429 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4665 23:07:23.208737 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4666 23:07:23.212216 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4667 23:07:23.218828 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4668 23:07:23.222033 0 9 12 | B1->B0 | 3131 2b2b | 1 1 | (1 1) (1 1)
4669 23:07:23.225377 0 9 16 | B1->B0 | 2d2d 2323 | 0 0 | (0 0) (0 0)
4670 23:07:23.232299 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4671 23:07:23.235546 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4672 23:07:23.238696 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4673 23:07:23.245214 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4674 23:07:23.248520 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4675 23:07:23.252266 0 10 8 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
4676 23:07:23.258595 0 10 12 | B1->B0 | 2d2d 3b3b | 0 0 | (0 0) (0 0)
4677 23:07:23.262210 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4678 23:07:23.265343 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4679 23:07:23.272053 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4680 23:07:23.275010 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4681 23:07:23.278661 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4682 23:07:23.285359 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4683 23:07:23.288164 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4684 23:07:23.291807 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4685 23:07:23.298450 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4686 23:07:23.301619 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4687 23:07:23.304886 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4688 23:07:23.311851 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4689 23:07:23.314755 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4690 23:07:23.318090 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4691 23:07:23.321423 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4692 23:07:23.328404 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4693 23:07:23.331161 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4694 23:07:23.334910 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4695 23:07:23.341373 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4696 23:07:23.344438 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4697 23:07:23.347718 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4698 23:07:23.354534 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4699 23:07:23.357573 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4700 23:07:23.361256 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4701 23:07:23.367845 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4702 23:07:23.371615 Total UI for P1: 0, mck2ui 16
4703 23:07:23.374560 best dqsien dly found for B0: ( 0, 13, 12)
4704 23:07:23.377680 Total UI for P1: 0, mck2ui 16
4705 23:07:23.380910 best dqsien dly found for B1: ( 0, 13, 14)
4706 23:07:23.384386 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4707 23:07:23.387639 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4708 23:07:23.387739
4709 23:07:23.390975 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4710 23:07:23.394094 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4711 23:07:23.397681 [Gating] SW calibration Done
4712 23:07:23.397783 ==
4713 23:07:23.400749 Dram Type= 6, Freq= 0, CH_1, rank 1
4714 23:07:23.404226 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4715 23:07:23.404299 ==
4716 23:07:23.407321 RX Vref Scan: 0
4717 23:07:23.407396
4718 23:07:23.410764 RX Vref 0 -> 0, step: 1
4719 23:07:23.410833
4720 23:07:23.410891 RX Delay -230 -> 252, step: 16
4721 23:07:23.417565 iDelay=218, Bit 0, Center 41 (-134 ~ 217) 352
4722 23:07:23.420945 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4723 23:07:23.424134 iDelay=218, Bit 2, Center 17 (-150 ~ 185) 336
4724 23:07:23.427285 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4725 23:07:23.434039 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4726 23:07:23.437081 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4727 23:07:23.440377 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4728 23:07:23.444291 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4729 23:07:23.447270 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4730 23:07:23.453807 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4731 23:07:23.457351 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4732 23:07:23.460471 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4733 23:07:23.463727 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4734 23:07:23.470356 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4735 23:07:23.473602 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4736 23:07:23.477068 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4737 23:07:23.477139 ==
4738 23:07:23.480706 Dram Type= 6, Freq= 0, CH_1, rank 1
4739 23:07:23.486984 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4740 23:07:23.487092 ==
4741 23:07:23.487188 DQS Delay:
4742 23:07:23.487278 DQS0 = 0, DQS1 = 0
4743 23:07:23.490302 DQM Delay:
4744 23:07:23.490403 DQM0 = 37, DQM1 = 28
4745 23:07:23.493644 DQ Delay:
4746 23:07:23.496939 DQ0 =41, DQ1 =33, DQ2 =17, DQ3 =33
4747 23:07:23.500219 DQ4 =33, DQ5 =57, DQ6 =49, DQ7 =33
4748 23:07:23.503621 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4749 23:07:23.507151 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4750 23:07:23.507226
4751 23:07:23.507289
4752 23:07:23.507349 ==
4753 23:07:23.510095 Dram Type= 6, Freq= 0, CH_1, rank 1
4754 23:07:23.513617 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4755 23:07:23.513690 ==
4756 23:07:23.513753
4757 23:07:23.513813
4758 23:07:23.516824 TX Vref Scan disable
4759 23:07:23.516903 == TX Byte 0 ==
4760 23:07:23.523583 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4761 23:07:23.526526 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4762 23:07:23.526603 == TX Byte 1 ==
4763 23:07:23.533488 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4764 23:07:23.536598 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4765 23:07:23.536680 ==
4766 23:07:23.539809 Dram Type= 6, Freq= 0, CH_1, rank 1
4767 23:07:23.543004 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4768 23:07:23.543087 ==
4769 23:07:23.546344
4770 23:07:23.546424
4771 23:07:23.546489 TX Vref Scan disable
4772 23:07:23.550155 == TX Byte 0 ==
4773 23:07:23.553692 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4774 23:07:23.560118 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4775 23:07:23.560201 == TX Byte 1 ==
4776 23:07:23.563035 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4777 23:07:23.570046 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4778 23:07:23.570129
4779 23:07:23.570193 [DATLAT]
4780 23:07:23.570252 Freq=600, CH1 RK1
4781 23:07:23.570310
4782 23:07:23.573210 DATLAT Default: 0x9
4783 23:07:23.573292 0, 0xFFFF, sum = 0
4784 23:07:23.576400 1, 0xFFFF, sum = 0
4785 23:07:23.576483 2, 0xFFFF, sum = 0
4786 23:07:23.579696 3, 0xFFFF, sum = 0
4787 23:07:23.583160 4, 0xFFFF, sum = 0
4788 23:07:23.583243 5, 0xFFFF, sum = 0
4789 23:07:23.586354 6, 0xFFFF, sum = 0
4790 23:07:23.586456 7, 0xFFFF, sum = 0
4791 23:07:23.589765 8, 0x0, sum = 1
4792 23:07:23.589848 9, 0x0, sum = 2
4793 23:07:23.589915 10, 0x0, sum = 3
4794 23:07:23.593032 11, 0x0, sum = 4
4795 23:07:23.593114 best_step = 9
4796 23:07:23.593178
4797 23:07:23.593251 ==
4798 23:07:23.596743 Dram Type= 6, Freq= 0, CH_1, rank 1
4799 23:07:23.603293 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4800 23:07:23.603373 ==
4801 23:07:23.603439 RX Vref Scan: 0
4802 23:07:23.603499
4803 23:07:23.606374 RX Vref 0 -> 0, step: 1
4804 23:07:23.606446
4805 23:07:23.609631 RX Delay -195 -> 252, step: 8
4806 23:07:23.613209 iDelay=205, Bit 0, Center 36 (-123 ~ 196) 320
4807 23:07:23.619658 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4808 23:07:23.623028 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4809 23:07:23.626290 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4810 23:07:23.629612 iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312
4811 23:07:23.636200 iDelay=205, Bit 5, Center 44 (-115 ~ 204) 320
4812 23:07:23.639607 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4813 23:07:23.643286 iDelay=205, Bit 7, Center 36 (-123 ~ 196) 320
4814 23:07:23.646524 iDelay=205, Bit 8, Center 16 (-147 ~ 180) 328
4815 23:07:23.649751 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4816 23:07:23.655972 iDelay=205, Bit 10, Center 32 (-131 ~ 196) 328
4817 23:07:23.659275 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4818 23:07:23.663128 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4819 23:07:23.666237 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4820 23:07:23.672704 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4821 23:07:23.676261 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4822 23:07:23.676360 ==
4823 23:07:23.679321 Dram Type= 6, Freq= 0, CH_1, rank 1
4824 23:07:23.682560 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4825 23:07:23.682645 ==
4826 23:07:23.685967 DQS Delay:
4827 23:07:23.686036 DQS0 = 0, DQS1 = 0
4828 23:07:23.686114 DQM Delay:
4829 23:07:23.689206 DQM0 = 35, DQM1 = 29
4830 23:07:23.689276 DQ Delay:
4831 23:07:23.692486 DQ0 =36, DQ1 =32, DQ2 =24, DQ3 =32
4832 23:07:23.695694 DQ4 =32, DQ5 =44, DQ6 =48, DQ7 =36
4833 23:07:23.699135 DQ8 =16, DQ9 =20, DQ10 =32, DQ11 =20
4834 23:07:23.702441 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4835 23:07:23.702512
4836 23:07:23.702583
4837 23:07:23.712592 [DQSOSCAuto] RK1, (LSB)MR18= 0x3c5b, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 398 ps
4838 23:07:23.715583 CH1 RK1: MR19=808, MR18=3C5B
4839 23:07:23.721949 CH1_RK1: MR19=0x808, MR18=0x3C5B, DQSOSC=392, MR23=63, INC=170, DEC=113
4840 23:07:23.722023 [RxdqsGatingPostProcess] freq 600
4841 23:07:23.728982 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4842 23:07:23.732062 Pre-setting of DQS Precalculation
4843 23:07:23.735331 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4844 23:07:23.745402 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4845 23:07:23.751989 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4846 23:07:23.752093
4847 23:07:23.752186
4848 23:07:23.755140 [Calibration Summary] 1200 Mbps
4849 23:07:23.755208 CH 0, Rank 0
4850 23:07:23.758298 SW Impedance : PASS
4851 23:07:23.758368 DUTY Scan : NO K
4852 23:07:23.761656 ZQ Calibration : PASS
4853 23:07:23.765216 Jitter Meter : NO K
4854 23:07:23.765317 CBT Training : PASS
4855 23:07:23.768530 Write leveling : PASS
4856 23:07:23.771678 RX DQS gating : PASS
4857 23:07:23.771776 RX DQ/DQS(RDDQC) : PASS
4858 23:07:23.775312 TX DQ/DQS : PASS
4859 23:07:23.778541 RX DATLAT : PASS
4860 23:07:23.778639 RX DQ/DQS(Engine): PASS
4861 23:07:23.781525 TX OE : NO K
4862 23:07:23.781597 All Pass.
4863 23:07:23.781658
4864 23:07:23.784737 CH 0, Rank 1
4865 23:07:23.784833 SW Impedance : PASS
4866 23:07:23.788588 DUTY Scan : NO K
4867 23:07:23.791733 ZQ Calibration : PASS
4868 23:07:23.791838 Jitter Meter : NO K
4869 23:07:23.795247 CBT Training : PASS
4870 23:07:23.798399 Write leveling : PASS
4871 23:07:23.798505 RX DQS gating : PASS
4872 23:07:23.801599 RX DQ/DQS(RDDQC) : PASS
4873 23:07:23.804861 TX DQ/DQS : PASS
4874 23:07:23.804966 RX DATLAT : PASS
4875 23:07:23.807962 RX DQ/DQS(Engine): PASS
4876 23:07:23.808060 TX OE : NO K
4877 23:07:23.811871 All Pass.
4878 23:07:23.811969
4879 23:07:23.812069 CH 1, Rank 0
4880 23:07:23.814724 SW Impedance : PASS
4881 23:07:23.814821 DUTY Scan : NO K
4882 23:07:23.818101 ZQ Calibration : PASS
4883 23:07:23.821212 Jitter Meter : NO K
4884 23:07:23.821309 CBT Training : PASS
4885 23:07:23.824333 Write leveling : PASS
4886 23:07:23.827716 RX DQS gating : PASS
4887 23:07:23.827818 RX DQ/DQS(RDDQC) : PASS
4888 23:07:23.831358 TX DQ/DQS : PASS
4889 23:07:23.834499 RX DATLAT : PASS
4890 23:07:23.834595 RX DQ/DQS(Engine): PASS
4891 23:07:23.837488 TX OE : NO K
4892 23:07:23.837599 All Pass.
4893 23:07:23.837677
4894 23:07:23.840775 CH 1, Rank 1
4895 23:07:23.840857 SW Impedance : PASS
4896 23:07:23.844153 DUTY Scan : NO K
4897 23:07:23.847830 ZQ Calibration : PASS
4898 23:07:23.847926 Jitter Meter : NO K
4899 23:07:23.851038 CBT Training : PASS
4900 23:07:23.854339 Write leveling : PASS
4901 23:07:23.854415 RX DQS gating : PASS
4902 23:07:23.857627 RX DQ/DQS(RDDQC) : PASS
4903 23:07:23.860592 TX DQ/DQS : PASS
4904 23:07:23.860688 RX DATLAT : PASS
4905 23:07:23.864189 RX DQ/DQS(Engine): PASS
4906 23:07:23.867410 TX OE : NO K
4907 23:07:23.867514 All Pass.
4908 23:07:23.867604
4909 23:07:23.870600 DramC Write-DBI off
4910 23:07:23.870709 PER_BANK_REFRESH: Hybrid Mode
4911 23:07:23.874011 TX_TRACKING: ON
4912 23:07:23.880621 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4913 23:07:23.883742 [FAST_K] Save calibration result to emmc
4914 23:07:23.890595 dramc_set_vcore_voltage set vcore to 662500
4915 23:07:23.890677 Read voltage for 933, 3
4916 23:07:23.893851 Vio18 = 0
4917 23:07:23.893923 Vcore = 662500
4918 23:07:23.894002 Vdram = 0
4919 23:07:23.897095 Vddq = 0
4920 23:07:23.897191 Vmddr = 0
4921 23:07:23.900463 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4922 23:07:23.906917 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4923 23:07:23.910224 MEM_TYPE=3, freq_sel=17
4924 23:07:23.913609 sv_algorithm_assistance_LP4_1600
4925 23:07:23.916673 ============ PULL DRAM RESETB DOWN ============
4926 23:07:23.920383 ========== PULL DRAM RESETB DOWN end =========
4927 23:07:23.926818 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4928 23:07:23.930188 ===================================
4929 23:07:23.930264 LPDDR4 DRAM CONFIGURATION
4930 23:07:23.933443 ===================================
4931 23:07:23.936586 EX_ROW_EN[0] = 0x0
4932 23:07:23.936689 EX_ROW_EN[1] = 0x0
4933 23:07:23.940159 LP4Y_EN = 0x0
4934 23:07:23.940265 WORK_FSP = 0x0
4935 23:07:23.943377 WL = 0x3
4936 23:07:23.943478 RL = 0x3
4937 23:07:23.946596 BL = 0x2
4938 23:07:23.949895 RPST = 0x0
4939 23:07:23.950006 RD_PRE = 0x0
4940 23:07:23.953084 WR_PRE = 0x1
4941 23:07:23.953187 WR_PST = 0x0
4942 23:07:23.956854 DBI_WR = 0x0
4943 23:07:23.956932 DBI_RD = 0x0
4944 23:07:23.960190 OTF = 0x1
4945 23:07:23.963426 ===================================
4946 23:07:23.966679 ===================================
4947 23:07:23.966754 ANA top config
4948 23:07:23.969803 ===================================
4949 23:07:23.973615 DLL_ASYNC_EN = 0
4950 23:07:23.976593 ALL_SLAVE_EN = 1
4951 23:07:23.976695 NEW_RANK_MODE = 1
4952 23:07:23.979561 DLL_IDLE_MODE = 1
4953 23:07:23.982910 LP45_APHY_COMB_EN = 1
4954 23:07:23.986366 TX_ODT_DIS = 1
4955 23:07:23.989597 NEW_8X_MODE = 1
4956 23:07:23.992896 ===================================
4957 23:07:23.996147 ===================================
4958 23:07:23.996251 data_rate = 1866
4959 23:07:23.999411 CKR = 1
4960 23:07:24.002582 DQ_P2S_RATIO = 8
4961 23:07:24.006150 ===================================
4962 23:07:24.009319 CA_P2S_RATIO = 8
4963 23:07:24.012461 DQ_CA_OPEN = 0
4964 23:07:24.015867 DQ_SEMI_OPEN = 0
4965 23:07:24.015970 CA_SEMI_OPEN = 0
4966 23:07:24.019043 CA_FULL_RATE = 0
4967 23:07:24.022709 DQ_CKDIV4_EN = 1
4968 23:07:24.025948 CA_CKDIV4_EN = 1
4969 23:07:24.029190 CA_PREDIV_EN = 0
4970 23:07:24.033045 PH8_DLY = 0
4971 23:07:24.033127 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4972 23:07:24.035614 DQ_AAMCK_DIV = 4
4973 23:07:24.039256 CA_AAMCK_DIV = 4
4974 23:07:24.042533 CA_ADMCK_DIV = 4
4975 23:07:24.045686 DQ_TRACK_CA_EN = 0
4976 23:07:24.048880 CA_PICK = 933
4977 23:07:24.052319 CA_MCKIO = 933
4978 23:07:24.052400 MCKIO_SEMI = 0
4979 23:07:24.056045 PLL_FREQ = 3732
4980 23:07:24.059228 DQ_UI_PI_RATIO = 32
4981 23:07:24.062457 CA_UI_PI_RATIO = 0
4982 23:07:24.065710 ===================================
4983 23:07:24.068943 ===================================
4984 23:07:24.072196 memory_type:LPDDR4
4985 23:07:24.072277 GP_NUM : 10
4986 23:07:24.075443 SRAM_EN : 1
4987 23:07:24.078817 MD32_EN : 0
4988 23:07:24.081925 ===================================
4989 23:07:24.082007 [ANA_INIT] >>>>>>>>>>>>>>
4990 23:07:24.085252 <<<<<< [CONFIGURE PHASE]: ANA_TX
4991 23:07:24.088697 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4992 23:07:24.092316 ===================================
4993 23:07:24.095132 data_rate = 1866,PCW = 0X8f00
4994 23:07:24.098516 ===================================
4995 23:07:24.101696 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4996 23:07:24.108336 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4997 23:07:24.111576 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4998 23:07:24.118832 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4999 23:07:24.122014 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5000 23:07:24.125193 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5001 23:07:24.125275 [ANA_INIT] flow start
5002 23:07:24.128437 [ANA_INIT] PLL >>>>>>>>
5003 23:07:24.131880 [ANA_INIT] PLL <<<<<<<<
5004 23:07:24.135076 [ANA_INIT] MIDPI >>>>>>>>
5005 23:07:24.135157 [ANA_INIT] MIDPI <<<<<<<<
5006 23:07:24.138423 [ANA_INIT] DLL >>>>>>>>
5007 23:07:24.141661 [ANA_INIT] flow end
5008 23:07:24.144851 ============ LP4 DIFF to SE enter ============
5009 23:07:24.148438 ============ LP4 DIFF to SE exit ============
5010 23:07:24.151803 [ANA_INIT] <<<<<<<<<<<<<
5011 23:07:24.154944 [Flow] Enable top DCM control >>>>>
5012 23:07:24.158447 [Flow] Enable top DCM control <<<<<
5013 23:07:24.161777 Enable DLL master slave shuffle
5014 23:07:24.164897 ==============================================================
5015 23:07:24.168416 Gating Mode config
5016 23:07:24.171759 ==============================================================
5017 23:07:24.174927 Config description:
5018 23:07:24.184702 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5019 23:07:24.191731 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5020 23:07:24.194498 SELPH_MODE 0: By rank 1: By Phase
5021 23:07:24.201324 ==============================================================
5022 23:07:24.204918 GAT_TRACK_EN = 1
5023 23:07:24.207862 RX_GATING_MODE = 2
5024 23:07:24.211519 RX_GATING_TRACK_MODE = 2
5025 23:07:24.214675 SELPH_MODE = 1
5026 23:07:24.217764 PICG_EARLY_EN = 1
5027 23:07:24.221240 VALID_LAT_VALUE = 1
5028 23:07:24.224461 ==============================================================
5029 23:07:24.227618 Enter into Gating configuration >>>>
5030 23:07:24.231330 Exit from Gating configuration <<<<
5031 23:07:24.234533 Enter into DVFS_PRE_config >>>>>
5032 23:07:24.244316 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5033 23:07:24.247648 Exit from DVFS_PRE_config <<<<<
5034 23:07:24.250850 Enter into PICG configuration >>>>
5035 23:07:24.254130 Exit from PICG configuration <<<<
5036 23:07:24.257733 [RX_INPUT] configuration >>>>>
5037 23:07:24.261404 [RX_INPUT] configuration <<<<<
5038 23:07:24.267864 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5039 23:07:24.271290 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5040 23:07:24.277718 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5041 23:07:24.284183 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5042 23:07:24.291236 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5043 23:07:24.297760 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5044 23:07:24.300745 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5045 23:07:24.304295 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5046 23:07:24.307732 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5047 23:07:24.314064 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5048 23:07:24.317383 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5049 23:07:24.320678 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5050 23:07:24.324023 ===================================
5051 23:07:24.327282 LPDDR4 DRAM CONFIGURATION
5052 23:07:24.330576 ===================================
5053 23:07:24.330659 EX_ROW_EN[0] = 0x0
5054 23:07:24.333917 EX_ROW_EN[1] = 0x0
5055 23:07:24.337309 LP4Y_EN = 0x0
5056 23:07:24.337390 WORK_FSP = 0x0
5057 23:07:24.340635 WL = 0x3
5058 23:07:24.340717 RL = 0x3
5059 23:07:24.343724 BL = 0x2
5060 23:07:24.343805 RPST = 0x0
5061 23:07:24.347442 RD_PRE = 0x0
5062 23:07:24.347524 WR_PRE = 0x1
5063 23:07:24.350926 WR_PST = 0x0
5064 23:07:24.351007 DBI_WR = 0x0
5065 23:07:24.354122 DBI_RD = 0x0
5066 23:07:24.354203 OTF = 0x1
5067 23:07:24.357267 ===================================
5068 23:07:24.360544 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5069 23:07:24.367331 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5070 23:07:24.370511 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5071 23:07:24.374267 ===================================
5072 23:07:24.377320 LPDDR4 DRAM CONFIGURATION
5073 23:07:24.380419 ===================================
5074 23:07:24.380501 EX_ROW_EN[0] = 0x10
5075 23:07:24.383848 EX_ROW_EN[1] = 0x0
5076 23:07:24.383938 LP4Y_EN = 0x0
5077 23:07:24.387139 WORK_FSP = 0x0
5078 23:07:24.387221 WL = 0x3
5079 23:07:24.390453 RL = 0x3
5080 23:07:24.393664 BL = 0x2
5081 23:07:24.393746 RPST = 0x0
5082 23:07:24.396794 RD_PRE = 0x0
5083 23:07:24.396876 WR_PRE = 0x1
5084 23:07:24.400451 WR_PST = 0x0
5085 23:07:24.400532 DBI_WR = 0x0
5086 23:07:24.403879 DBI_RD = 0x0
5087 23:07:24.403960 OTF = 0x1
5088 23:07:24.407290 ===================================
5089 23:07:24.413833 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5090 23:07:24.417623 nWR fixed to 30
5091 23:07:24.420806 [ModeRegInit_LP4] CH0 RK0
5092 23:07:24.420887 [ModeRegInit_LP4] CH0 RK1
5093 23:07:24.423996 [ModeRegInit_LP4] CH1 RK0
5094 23:07:24.427486 [ModeRegInit_LP4] CH1 RK1
5095 23:07:24.427567 match AC timing 9
5096 23:07:24.434274 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5097 23:07:24.437513 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5098 23:07:24.440793 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5099 23:07:24.447269 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5100 23:07:24.450728 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5101 23:07:24.450819 ==
5102 23:07:24.453961 Dram Type= 6, Freq= 0, CH_0, rank 0
5103 23:07:24.457152 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5104 23:07:24.457234 ==
5105 23:07:24.463820 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5106 23:07:24.470733 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5107 23:07:24.473887 [CA 0] Center 38 (7~69) winsize 63
5108 23:07:24.477215 [CA 1] Center 38 (8~69) winsize 62
5109 23:07:24.480822 [CA 2] Center 35 (5~66) winsize 62
5110 23:07:24.483938 [CA 3] Center 35 (5~65) winsize 61
5111 23:07:24.487330 [CA 4] Center 34 (4~65) winsize 62
5112 23:07:24.490455 [CA 5] Center 33 (3~64) winsize 62
5113 23:07:24.490545
5114 23:07:24.493906 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5115 23:07:24.493987
5116 23:07:24.497164 [CATrainingPosCal] consider 1 rank data
5117 23:07:24.500302 u2DelayCellTimex100 = 270/100 ps
5118 23:07:24.503441 CA0 delay=38 (7~69),Diff = 5 PI (31 cell)
5119 23:07:24.506630 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5120 23:07:24.510385 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5121 23:07:24.513401 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5122 23:07:24.516643 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5123 23:07:24.523741 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5124 23:07:24.523844
5125 23:07:24.526925 CA PerBit enable=1, Macro0, CA PI delay=33
5126 23:07:24.527000
5127 23:07:24.530310 [CBTSetCACLKResult] CA Dly = 33
5128 23:07:24.530401 CS Dly: 7 (0~38)
5129 23:07:24.530464 ==
5130 23:07:24.533248 Dram Type= 6, Freq= 0, CH_0, rank 1
5131 23:07:24.536730 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5132 23:07:24.540134 ==
5133 23:07:24.543377 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5134 23:07:24.550292 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5135 23:07:24.553356 [CA 0] Center 38 (8~69) winsize 62
5136 23:07:24.556832 [CA 1] Center 38 (8~69) winsize 62
5137 23:07:24.560280 [CA 2] Center 35 (5~66) winsize 62
5138 23:07:24.563385 [CA 3] Center 35 (4~66) winsize 63
5139 23:07:24.566623 [CA 4] Center 34 (4~65) winsize 62
5140 23:07:24.569851 [CA 5] Center 34 (4~64) winsize 61
5141 23:07:24.569926
5142 23:07:24.573257 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5143 23:07:24.573356
5144 23:07:24.576260 [CATrainingPosCal] consider 2 rank data
5145 23:07:24.580048 u2DelayCellTimex100 = 270/100 ps
5146 23:07:24.583364 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5147 23:07:24.586854 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5148 23:07:24.589407 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5149 23:07:24.596122 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5150 23:07:24.599790 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5151 23:07:24.602719 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5152 23:07:24.602794
5153 23:07:24.606036 CA PerBit enable=1, Macro0, CA PI delay=34
5154 23:07:24.606110
5155 23:07:24.609529 [CBTSetCACLKResult] CA Dly = 34
5156 23:07:24.609643 CS Dly: 7 (0~39)
5157 23:07:24.609732
5158 23:07:24.612975 ----->DramcWriteLeveling(PI) begin...
5159 23:07:24.616302 ==
5160 23:07:24.616412 Dram Type= 6, Freq= 0, CH_0, rank 0
5161 23:07:24.622619 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5162 23:07:24.622696 ==
5163 23:07:24.625871 Write leveling (Byte 0): 34 => 34
5164 23:07:24.629607 Write leveling (Byte 1): 31 => 31
5165 23:07:24.632932 DramcWriteLeveling(PI) end<-----
5166 23:07:24.633033
5167 23:07:24.633131 ==
5168 23:07:24.636234 Dram Type= 6, Freq= 0, CH_0, rank 0
5169 23:07:24.639261 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5170 23:07:24.639369 ==
5171 23:07:24.642532 [Gating] SW mode calibration
5172 23:07:24.649649 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5173 23:07:24.652445 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5174 23:07:24.659668 0 14 0 | B1->B0 | 2323 2b2b | 1 1 | (0 0) (1 1)
5175 23:07:24.662787 0 14 4 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
5176 23:07:24.666396 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5177 23:07:24.672856 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5178 23:07:24.676129 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5179 23:07:24.679132 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5180 23:07:24.685720 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5181 23:07:24.689379 0 14 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5182 23:07:24.692421 0 15 0 | B1->B0 | 3333 2f2f | 0 0 | (0 0) (0 0)
5183 23:07:24.698855 0 15 4 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
5184 23:07:24.702106 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5185 23:07:24.705367 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5186 23:07:24.712088 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5187 23:07:24.715742 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5188 23:07:24.719106 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5189 23:07:24.725267 0 15 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5190 23:07:24.728871 1 0 0 | B1->B0 | 2e2d 3b3b | 1 0 | (1 1) (0 0)
5191 23:07:24.732175 1 0 4 | B1->B0 | 4343 4646 | 0 0 | (1 1) (0 0)
5192 23:07:24.739088 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5193 23:07:24.742246 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5194 23:07:24.745436 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5195 23:07:24.751793 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5196 23:07:24.755223 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5197 23:07:24.758600 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5198 23:07:24.765383 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5199 23:07:24.768611 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5200 23:07:24.772175 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5201 23:07:24.778395 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5202 23:07:24.782194 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5203 23:07:24.785388 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5204 23:07:24.791911 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5205 23:07:24.795001 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5206 23:07:24.798579 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5207 23:07:24.805072 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5208 23:07:24.808397 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5209 23:07:24.811700 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5210 23:07:24.815315 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5211 23:07:24.822133 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5212 23:07:24.825464 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5213 23:07:24.828390 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5214 23:07:24.834967 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5215 23:07:24.838686 Total UI for P1: 0, mck2ui 16
5216 23:07:24.841867 best dqsien dly found for B0: ( 1, 2, 28)
5217 23:07:24.845151 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5218 23:07:24.848596 Total UI for P1: 0, mck2ui 16
5219 23:07:24.851860 best dqsien dly found for B1: ( 1, 3, 0)
5220 23:07:24.855145 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5221 23:07:24.858437 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5222 23:07:24.858539
5223 23:07:24.861629 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5224 23:07:24.864829 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5225 23:07:24.868505 [Gating] SW calibration Done
5226 23:07:24.868604 ==
5227 23:07:24.871499 Dram Type= 6, Freq= 0, CH_0, rank 0
5228 23:07:24.878388 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5229 23:07:24.878467 ==
5230 23:07:24.878531 RX Vref Scan: 0
5231 23:07:24.878599
5232 23:07:24.881253 RX Vref 0 -> 0, step: 1
5233 23:07:24.881330
5234 23:07:24.884696 RX Delay -80 -> 252, step: 8
5235 23:07:24.888149 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5236 23:07:24.891511 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5237 23:07:24.894655 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5238 23:07:24.897820 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5239 23:07:24.901630 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5240 23:07:24.907782 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5241 23:07:24.911649 iDelay=208, Bit 6, Center 99 (0 ~ 199) 200
5242 23:07:24.914864 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5243 23:07:24.917946 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5244 23:07:24.921115 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5245 23:07:24.927725 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5246 23:07:24.931494 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5247 23:07:24.934356 iDelay=208, Bit 12, Center 87 (-16 ~ 191) 208
5248 23:07:24.938029 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5249 23:07:24.941262 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5250 23:07:24.947807 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5251 23:07:24.947913 ==
5252 23:07:24.950931 Dram Type= 6, Freq= 0, CH_0, rank 0
5253 23:07:24.954216 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5254 23:07:24.954322 ==
5255 23:07:24.954414 DQS Delay:
5256 23:07:24.957970 DQS0 = 0, DQS1 = 0
5257 23:07:24.958072 DQM Delay:
5258 23:07:24.961180 DQM0 = 93, DQM1 = 83
5259 23:07:24.961283 DQ Delay:
5260 23:07:24.964477 DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =91
5261 23:07:24.967651 DQ4 =95, DQ5 =79, DQ6 =99, DQ7 =107
5262 23:07:24.971331 DQ8 =79, DQ9 =71, DQ10 =83, DQ11 =75
5263 23:07:24.974108 DQ12 =87, DQ13 =91, DQ14 =91, DQ15 =91
5264 23:07:24.974210
5265 23:07:24.974312
5266 23:07:24.974403 ==
5267 23:07:24.977637 Dram Type= 6, Freq= 0, CH_0, rank 0
5268 23:07:24.980738 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5269 23:07:24.980848 ==
5270 23:07:24.984029
5271 23:07:24.984139
5272 23:07:24.984233 TX Vref Scan disable
5273 23:07:24.987519 == TX Byte 0 ==
5274 23:07:24.990793 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5275 23:07:24.994133 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5276 23:07:24.997469 == TX Byte 1 ==
5277 23:07:25.000567 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5278 23:07:25.003874 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5279 23:07:25.007225 ==
5280 23:07:25.007331 Dram Type= 6, Freq= 0, CH_0, rank 0
5281 23:07:25.013824 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5282 23:07:25.013913 ==
5283 23:07:25.013977
5284 23:07:25.014037
5285 23:07:25.017126 TX Vref Scan disable
5286 23:07:25.017232 == TX Byte 0 ==
5287 23:07:25.024242 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5288 23:07:25.027194 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5289 23:07:25.027295 == TX Byte 1 ==
5290 23:07:25.033710 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5291 23:07:25.037032 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5292 23:07:25.037135
5293 23:07:25.037247 [DATLAT]
5294 23:07:25.040795 Freq=933, CH0 RK0
5295 23:07:25.040906
5296 23:07:25.040998 DATLAT Default: 0xd
5297 23:07:25.044132 0, 0xFFFF, sum = 0
5298 23:07:25.044217 1, 0xFFFF, sum = 0
5299 23:07:25.047413 2, 0xFFFF, sum = 0
5300 23:07:25.047513 3, 0xFFFF, sum = 0
5301 23:07:25.050235 4, 0xFFFF, sum = 0
5302 23:07:25.050319 5, 0xFFFF, sum = 0
5303 23:07:25.053669 6, 0xFFFF, sum = 0
5304 23:07:25.053752 7, 0xFFFF, sum = 0
5305 23:07:25.057167 8, 0xFFFF, sum = 0
5306 23:07:25.057250 9, 0xFFFF, sum = 0
5307 23:07:25.060345 10, 0x0, sum = 1
5308 23:07:25.060429 11, 0x0, sum = 2
5309 23:07:25.063634 12, 0x0, sum = 3
5310 23:07:25.063771 13, 0x0, sum = 4
5311 23:07:25.067480 best_step = 11
5312 23:07:25.067562
5313 23:07:25.067627 ==
5314 23:07:25.070599 Dram Type= 6, Freq= 0, CH_0, rank 0
5315 23:07:25.073712 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5316 23:07:25.073794 ==
5317 23:07:25.077045 RX Vref Scan: 1
5318 23:07:25.077127
5319 23:07:25.077191 RX Vref 0 -> 0, step: 1
5320 23:07:25.077251
5321 23:07:25.080384 RX Delay -69 -> 252, step: 4
5322 23:07:25.080465
5323 23:07:25.083615 Set Vref, RX VrefLevel [Byte0]: 60
5324 23:07:25.086798 [Byte1]: 58
5325 23:07:25.091058
5326 23:07:25.091139 Final RX Vref Byte 0 = 60 to rank0
5327 23:07:25.094524 Final RX Vref Byte 1 = 58 to rank0
5328 23:07:25.097639 Final RX Vref Byte 0 = 60 to rank1
5329 23:07:25.100920 Final RX Vref Byte 1 = 58 to rank1==
5330 23:07:25.104337 Dram Type= 6, Freq= 0, CH_0, rank 0
5331 23:07:25.111155 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5332 23:07:25.111237 ==
5333 23:07:25.111302 DQS Delay:
5334 23:07:25.111361 DQS0 = 0, DQS1 = 0
5335 23:07:25.114424 DQM Delay:
5336 23:07:25.114506 DQM0 = 95, DQM1 = 84
5337 23:07:25.117834 DQ Delay:
5338 23:07:25.121156 DQ0 =94, DQ1 =96, DQ2 =92, DQ3 =92
5339 23:07:25.124510 DQ4 =96, DQ5 =84, DQ6 =102, DQ7 =108
5340 23:07:25.127675 DQ8 =78, DQ9 =72, DQ10 =84, DQ11 =80
5341 23:07:25.130860 DQ12 =90, DQ13 =88, DQ14 =92, DQ15 =90
5342 23:07:25.130942
5343 23:07:25.131006
5344 23:07:25.137728 [DQSOSCAuto] RK0, (LSB)MR18= 0x1212, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 416 ps
5345 23:07:25.140849 CH0 RK0: MR19=505, MR18=1212
5346 23:07:25.147371 CH0_RK0: MR19=0x505, MR18=0x1212, DQSOSC=416, MR23=63, INC=62, DEC=41
5347 23:07:25.147455
5348 23:07:25.151028 ----->DramcWriteLeveling(PI) begin...
5349 23:07:25.151111 ==
5350 23:07:25.154184 Dram Type= 6, Freq= 0, CH_0, rank 1
5351 23:07:25.157674 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5352 23:07:25.157755 ==
5353 23:07:25.160898 Write leveling (Byte 0): 30 => 30
5354 23:07:25.164109 Write leveling (Byte 1): 29 => 29
5355 23:07:25.167395 DramcWriteLeveling(PI) end<-----
5356 23:07:25.167476
5357 23:07:25.167539 ==
5358 23:07:25.171271 Dram Type= 6, Freq= 0, CH_0, rank 1
5359 23:07:25.174468 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5360 23:07:25.174564 ==
5361 23:07:25.177523 [Gating] SW mode calibration
5362 23:07:25.184094 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5363 23:07:25.190464 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5364 23:07:25.194068 0 14 0 | B1->B0 | 2828 3434 | 0 1 | (1 1) (1 1)
5365 23:07:25.200469 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5366 23:07:25.204057 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5367 23:07:25.207068 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5368 23:07:25.210789 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5369 23:07:25.217355 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5370 23:07:25.220572 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5371 23:07:25.224038 0 14 28 | B1->B0 | 3434 2d2d | 1 0 | (1 1) (0 0)
5372 23:07:25.230595 0 15 0 | B1->B0 | 2e2e 2323 | 0 0 | (1 1) (0 0)
5373 23:07:25.233606 0 15 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5374 23:07:25.237439 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5375 23:07:25.244061 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5376 23:07:25.247195 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5377 23:07:25.250347 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5378 23:07:25.257189 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5379 23:07:25.260436 0 15 28 | B1->B0 | 2727 3333 | 0 0 | (0 0) (0 0)
5380 23:07:25.263632 1 0 0 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
5381 23:07:25.270567 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5382 23:07:25.273651 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5383 23:07:25.276705 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5384 23:07:25.283391 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5385 23:07:25.286774 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5386 23:07:25.290409 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5387 23:07:25.296837 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
5388 23:07:25.300156 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5389 23:07:25.303821 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5390 23:07:25.310335 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5391 23:07:25.313182 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5392 23:07:25.316661 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5393 23:07:25.323255 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5394 23:07:25.326879 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5395 23:07:25.330059 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5396 23:07:25.336504 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5397 23:07:25.339668 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5398 23:07:25.342925 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5399 23:07:25.349470 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5400 23:07:25.353337 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5401 23:07:25.356632 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5402 23:07:25.362718 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5403 23:07:25.366135 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5404 23:07:25.369862 Total UI for P1: 0, mck2ui 16
5405 23:07:25.372626 best dqsien dly found for B0: ( 1, 2, 24)
5406 23:07:25.376408 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5407 23:07:25.382959 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5408 23:07:25.383040 Total UI for P1: 0, mck2ui 16
5409 23:07:25.386016 best dqsien dly found for B1: ( 1, 2, 30)
5410 23:07:25.392665 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5411 23:07:25.395822 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5412 23:07:25.395904
5413 23:07:25.399552 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5414 23:07:25.402736 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5415 23:07:25.406016 [Gating] SW calibration Done
5416 23:07:25.406097 ==
5417 23:07:25.409250 Dram Type= 6, Freq= 0, CH_0, rank 1
5418 23:07:25.413205 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5419 23:07:25.413286 ==
5420 23:07:25.415760 RX Vref Scan: 0
5421 23:07:25.415846
5422 23:07:25.415932 RX Vref 0 -> 0, step: 1
5423 23:07:25.416013
5424 23:07:25.419066 RX Delay -80 -> 252, step: 8
5425 23:07:25.422614 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5426 23:07:25.429166 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5427 23:07:25.432640 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5428 23:07:25.435885 iDelay=208, Bit 3, Center 87 (-16 ~ 191) 208
5429 23:07:25.439228 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5430 23:07:25.442560 iDelay=208, Bit 5, Center 75 (-24 ~ 175) 200
5431 23:07:25.445889 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5432 23:07:25.452738 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5433 23:07:25.455678 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5434 23:07:25.458876 iDelay=208, Bit 9, Center 67 (-32 ~ 167) 200
5435 23:07:25.462392 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5436 23:07:25.465670 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5437 23:07:25.472258 iDelay=208, Bit 12, Center 87 (-16 ~ 191) 208
5438 23:07:25.475440 iDelay=208, Bit 13, Center 87 (-16 ~ 191) 208
5439 23:07:25.479224 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5440 23:07:25.482267 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5441 23:07:25.482348 ==
5442 23:07:25.485470 Dram Type= 6, Freq= 0, CH_0, rank 1
5443 23:07:25.492223 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5444 23:07:25.492305 ==
5445 23:07:25.492368 DQS Delay:
5446 23:07:25.495621 DQS0 = 0, DQS1 = 0
5447 23:07:25.495701 DQM Delay:
5448 23:07:25.495766 DQM0 = 92, DQM1 = 82
5449 23:07:25.498834 DQ Delay:
5450 23:07:25.502162 DQ0 =91, DQ1 =91, DQ2 =87, DQ3 =87
5451 23:07:25.505633 DQ4 =91, DQ5 =75, DQ6 =107, DQ7 =107
5452 23:07:25.508851 DQ8 =75, DQ9 =67, DQ10 =83, DQ11 =75
5453 23:07:25.512148 DQ12 =87, DQ13 =87, DQ14 =91, DQ15 =91
5454 23:07:25.512229
5455 23:07:25.512292
5456 23:07:25.512351 ==
5457 23:07:25.515434 Dram Type= 6, Freq= 0, CH_0, rank 1
5458 23:07:25.518678 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5459 23:07:25.518759 ==
5460 23:07:25.518823
5461 23:07:25.518882
5462 23:07:25.522230 TX Vref Scan disable
5463 23:07:25.522312 == TX Byte 0 ==
5464 23:07:25.528723 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5465 23:07:25.531897 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5466 23:07:25.531979 == TX Byte 1 ==
5467 23:07:25.538722 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5468 23:07:25.542129 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5469 23:07:25.542210 ==
5470 23:07:25.545657 Dram Type= 6, Freq= 0, CH_0, rank 1
5471 23:07:25.548731 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5472 23:07:25.548816 ==
5473 23:07:25.551858
5474 23:07:25.551943
5475 23:07:25.552028 TX Vref Scan disable
5476 23:07:25.555154 == TX Byte 0 ==
5477 23:07:25.558770 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5478 23:07:25.565407 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5479 23:07:25.565503 == TX Byte 1 ==
5480 23:07:25.568319 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5481 23:07:25.574928 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5482 23:07:25.575013
5483 23:07:25.575099 [DATLAT]
5484 23:07:25.575183 Freq=933, CH0 RK1
5485 23:07:25.575262
5486 23:07:25.578267 DATLAT Default: 0xb
5487 23:07:25.578352 0, 0xFFFF, sum = 0
5488 23:07:25.581588 1, 0xFFFF, sum = 0
5489 23:07:25.581675 2, 0xFFFF, sum = 0
5490 23:07:25.585183 3, 0xFFFF, sum = 0
5491 23:07:25.588401 4, 0xFFFF, sum = 0
5492 23:07:25.588488 5, 0xFFFF, sum = 0
5493 23:07:25.591703 6, 0xFFFF, sum = 0
5494 23:07:25.591789 7, 0xFFFF, sum = 0
5495 23:07:25.595333 8, 0xFFFF, sum = 0
5496 23:07:25.595420 9, 0xFFFF, sum = 0
5497 23:07:25.598331 10, 0x0, sum = 1
5498 23:07:25.598417 11, 0x0, sum = 2
5499 23:07:25.601451 12, 0x0, sum = 3
5500 23:07:25.601581 13, 0x0, sum = 4
5501 23:07:25.601669 best_step = 11
5502 23:07:25.601750
5503 23:07:25.604956 ==
5504 23:07:25.608216 Dram Type= 6, Freq= 0, CH_0, rank 1
5505 23:07:25.611415 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5506 23:07:25.611501 ==
5507 23:07:25.611587 RX Vref Scan: 0
5508 23:07:25.611668
5509 23:07:25.614734 RX Vref 0 -> 0, step: 1
5510 23:07:25.614819
5511 23:07:25.617964 RX Delay -77 -> 252, step: 4
5512 23:07:25.621827 iDelay=199, Bit 0, Center 92 (-1 ~ 186) 188
5513 23:07:25.628148 iDelay=199, Bit 1, Center 94 (3 ~ 186) 184
5514 23:07:25.631368 iDelay=199, Bit 2, Center 90 (-1 ~ 182) 184
5515 23:07:25.634702 iDelay=199, Bit 3, Center 88 (-5 ~ 182) 188
5516 23:07:25.638289 iDelay=199, Bit 4, Center 92 (-1 ~ 186) 188
5517 23:07:25.641517 iDelay=199, Bit 5, Center 80 (-13 ~ 174) 188
5518 23:07:25.648456 iDelay=199, Bit 6, Center 106 (15 ~ 198) 184
5519 23:07:25.651345 iDelay=199, Bit 7, Center 104 (11 ~ 198) 188
5520 23:07:25.654963 iDelay=199, Bit 8, Center 80 (-9 ~ 170) 180
5521 23:07:25.658096 iDelay=199, Bit 9, Center 72 (-17 ~ 162) 180
5522 23:07:25.661291 iDelay=199, Bit 10, Center 84 (-9 ~ 178) 188
5523 23:07:25.664919 iDelay=199, Bit 11, Center 80 (-9 ~ 170) 180
5524 23:07:25.671107 iDelay=199, Bit 12, Center 90 (-1 ~ 182) 184
5525 23:07:25.674553 iDelay=199, Bit 13, Center 90 (-1 ~ 182) 184
5526 23:07:25.677680 iDelay=199, Bit 14, Center 92 (-1 ~ 186) 188
5527 23:07:25.681111 iDelay=199, Bit 15, Center 92 (-1 ~ 186) 188
5528 23:07:25.681210 ==
5529 23:07:25.684186 Dram Type= 6, Freq= 0, CH_0, rank 1
5530 23:07:25.691137 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5531 23:07:25.691208 ==
5532 23:07:25.691270 DQS Delay:
5533 23:07:25.694341 DQS0 = 0, DQS1 = 0
5534 23:07:25.694410 DQM Delay:
5535 23:07:25.694470 DQM0 = 93, DQM1 = 85
5536 23:07:25.697600 DQ Delay:
5537 23:07:25.701134 DQ0 =92, DQ1 =94, DQ2 =90, DQ3 =88
5538 23:07:25.704756 DQ4 =92, DQ5 =80, DQ6 =106, DQ7 =104
5539 23:07:25.707701 DQ8 =80, DQ9 =72, DQ10 =84, DQ11 =80
5540 23:07:25.711187 DQ12 =90, DQ13 =90, DQ14 =92, DQ15 =92
5541 23:07:25.711254
5542 23:07:25.711320
5543 23:07:25.717465 [DQSOSCAuto] RK1, (LSB)MR18= 0x2d0f, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 407 ps
5544 23:07:25.721347 CH0 RK1: MR19=505, MR18=2D0F
5545 23:07:25.727687 CH0_RK1: MR19=0x505, MR18=0x2D0F, DQSOSC=407, MR23=63, INC=65, DEC=43
5546 23:07:25.730892 [RxdqsGatingPostProcess] freq 933
5547 23:07:25.734593 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5548 23:07:25.737726 best DQS0 dly(2T, 0.5T) = (0, 10)
5549 23:07:25.741094 best DQS1 dly(2T, 0.5T) = (0, 11)
5550 23:07:25.744181 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5551 23:07:25.747562 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5552 23:07:25.750826 best DQS0 dly(2T, 0.5T) = (0, 10)
5553 23:07:25.754348 best DQS1 dly(2T, 0.5T) = (0, 10)
5554 23:07:25.757779 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5555 23:07:25.761041 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5556 23:07:25.764117 Pre-setting of DQS Precalculation
5557 23:07:25.767877 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5558 23:07:25.767972 ==
5559 23:07:25.771124 Dram Type= 6, Freq= 0, CH_1, rank 0
5560 23:07:25.777596 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5561 23:07:25.777687 ==
5562 23:07:25.781162 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5563 23:07:25.787566 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5564 23:07:25.790637 [CA 0] Center 37 (7~67) winsize 61
5565 23:07:25.793871 [CA 1] Center 37 (7~68) winsize 62
5566 23:07:25.797643 [CA 2] Center 34 (5~64) winsize 60
5567 23:07:25.800461 [CA 3] Center 34 (5~64) winsize 60
5568 23:07:25.803986 [CA 4] Center 34 (5~64) winsize 60
5569 23:07:25.807155 [CA 5] Center 34 (4~64) winsize 61
5570 23:07:25.807249
5571 23:07:25.810457 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5572 23:07:25.810523
5573 23:07:25.814127 [CATrainingPosCal] consider 1 rank data
5574 23:07:25.817579 u2DelayCellTimex100 = 270/100 ps
5575 23:07:25.820569 CA0 delay=37 (7~67),Diff = 3 PI (18 cell)
5576 23:07:25.827417 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5577 23:07:25.830771 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
5578 23:07:25.833704 CA3 delay=34 (5~64),Diff = 0 PI (0 cell)
5579 23:07:25.836872 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
5580 23:07:25.840537 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5581 23:07:25.840639
5582 23:07:25.843668 CA PerBit enable=1, Macro0, CA PI delay=34
5583 23:07:25.843762
5584 23:07:25.847267 [CBTSetCACLKResult] CA Dly = 34
5585 23:07:25.847365 CS Dly: 6 (0~37)
5586 23:07:25.850160 ==
5587 23:07:25.853875 Dram Type= 6, Freq= 0, CH_1, rank 1
5588 23:07:25.856986 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5589 23:07:25.857084 ==
5590 23:07:25.860323 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5591 23:07:25.866657 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5592 23:07:25.870551 [CA 0] Center 37 (7~68) winsize 62
5593 23:07:25.874341 [CA 1] Center 37 (7~68) winsize 62
5594 23:07:25.877202 [CA 2] Center 35 (5~65) winsize 61
5595 23:07:25.880318 [CA 3] Center 34 (4~64) winsize 61
5596 23:07:25.883752 [CA 4] Center 35 (5~65) winsize 61
5597 23:07:25.887187 [CA 5] Center 33 (3~64) winsize 62
5598 23:07:25.887282
5599 23:07:25.890729 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5600 23:07:25.890798
5601 23:07:25.893611 [CATrainingPosCal] consider 2 rank data
5602 23:07:25.897254 u2DelayCellTimex100 = 270/100 ps
5603 23:07:25.900140 CA0 delay=37 (7~67),Diff = 3 PI (18 cell)
5604 23:07:25.907210 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5605 23:07:25.910333 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
5606 23:07:25.913613 CA3 delay=34 (5~64),Diff = 0 PI (0 cell)
5607 23:07:25.916731 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
5608 23:07:25.920130 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5609 23:07:25.920227
5610 23:07:25.923258 CA PerBit enable=1, Macro0, CA PI delay=34
5611 23:07:25.923344
5612 23:07:25.927025 [CBTSetCACLKResult] CA Dly = 34
5613 23:07:25.930226 CS Dly: 6 (0~38)
5614 23:07:25.930323
5615 23:07:25.933127 ----->DramcWriteLeveling(PI) begin...
5616 23:07:25.933235 ==
5617 23:07:25.936962 Dram Type= 6, Freq= 0, CH_1, rank 0
5618 23:07:25.939897 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5619 23:07:25.939999 ==
5620 23:07:25.943152 Write leveling (Byte 0): 25 => 25
5621 23:07:25.946946 Write leveling (Byte 1): 30 => 30
5622 23:07:25.950213 DramcWriteLeveling(PI) end<-----
5623 23:07:25.950282
5624 23:07:25.950341 ==
5625 23:07:25.953340 Dram Type= 6, Freq= 0, CH_1, rank 0
5626 23:07:25.956739 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5627 23:07:25.956831 ==
5628 23:07:25.960322 [Gating] SW mode calibration
5629 23:07:25.966209 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5630 23:07:25.972956 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5631 23:07:25.976202 0 14 0 | B1->B0 | 3332 3333 | 1 0 | (0 0) (0 0)
5632 23:07:25.979724 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5633 23:07:25.986299 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5634 23:07:25.989320 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5635 23:07:25.992748 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5636 23:07:25.999189 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5637 23:07:26.002967 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
5638 23:07:26.006090 0 14 28 | B1->B0 | 2f2f 3030 | 0 0 | (0 1) (0 1)
5639 23:07:26.012336 0 15 0 | B1->B0 | 2727 2424 | 0 0 | (1 0) (0 0)
5640 23:07:26.016003 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5641 23:07:26.019235 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5642 23:07:26.025835 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5643 23:07:26.029072 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5644 23:07:26.032368 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5645 23:07:26.039156 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5646 23:07:26.042153 0 15 28 | B1->B0 | 2f2f 2f2f | 0 0 | (0 0) (0 0)
5647 23:07:26.045810 1 0 0 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5648 23:07:26.052282 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5649 23:07:26.055517 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5650 23:07:26.058830 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5651 23:07:26.065260 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5652 23:07:26.068832 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5653 23:07:26.072120 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5654 23:07:26.078608 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5655 23:07:26.082089 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5656 23:07:26.085057 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5657 23:07:26.091933 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5658 23:07:26.095088 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5659 23:07:26.098864 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5660 23:07:26.105132 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5661 23:07:26.108346 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5662 23:07:26.112157 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5663 23:07:26.118216 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5664 23:07:26.121523 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5665 23:07:26.124900 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5666 23:07:26.131437 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5667 23:07:26.135103 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5668 23:07:26.138297 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5669 23:07:26.144605 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5670 23:07:26.148302 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5671 23:07:26.151691 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5672 23:07:26.158113 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5673 23:07:26.158196 Total UI for P1: 0, mck2ui 16
5674 23:07:26.164598 best dqsien dly found for B0: ( 1, 3, 0)
5675 23:07:26.164681 Total UI for P1: 0, mck2ui 16
5676 23:07:26.171238 best dqsien dly found for B1: ( 1, 3, 0)
5677 23:07:26.174215 best DQS0 dly(MCK, UI, PI) = (1, 3, 0)
5678 23:07:26.177661 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5679 23:07:26.177773
5680 23:07:26.180892 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 0)
5681 23:07:26.184279 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5682 23:07:26.187905 [Gating] SW calibration Done
5683 23:07:26.187988 ==
5684 23:07:26.191323 Dram Type= 6, Freq= 0, CH_1, rank 0
5685 23:07:26.194198 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5686 23:07:26.194282 ==
5687 23:07:26.197433 RX Vref Scan: 0
5688 23:07:26.197559
5689 23:07:26.197647 RX Vref 0 -> 0, step: 1
5690 23:07:26.197729
5691 23:07:26.201089 RX Delay -80 -> 252, step: 8
5692 23:07:26.204223 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5693 23:07:26.207816 iDelay=208, Bit 1, Center 87 (-16 ~ 191) 208
5694 23:07:26.214538 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5695 23:07:26.217669 iDelay=208, Bit 3, Center 91 (-16 ~ 199) 216
5696 23:07:26.220853 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5697 23:07:26.223991 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5698 23:07:26.227235 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5699 23:07:26.233713 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5700 23:07:26.237554 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5701 23:07:26.240848 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5702 23:07:26.243848 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5703 23:07:26.246977 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5704 23:07:26.253905 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5705 23:07:26.257348 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5706 23:07:26.260574 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5707 23:07:26.263745 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5708 23:07:26.263831 ==
5709 23:07:26.267020 Dram Type= 6, Freq= 0, CH_1, rank 0
5710 23:07:26.273626 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5711 23:07:26.273712 ==
5712 23:07:26.273799 DQS Delay:
5713 23:07:26.273881 DQS0 = 0, DQS1 = 0
5714 23:07:26.277127 DQM Delay:
5715 23:07:26.277212 DQM0 = 94, DQM1 = 86
5716 23:07:26.280014 DQ Delay:
5717 23:07:26.283347 DQ0 =99, DQ1 =87, DQ2 =83, DQ3 =91
5718 23:07:26.287119 DQ4 =91, DQ5 =107, DQ6 =107, DQ7 =91
5719 23:07:26.290333 DQ8 =75, DQ9 =75, DQ10 =87, DQ11 =83
5720 23:07:26.293585 DQ12 =95, DQ13 =95, DQ14 =91, DQ15 =91
5721 23:07:26.293670
5722 23:07:26.293756
5723 23:07:26.293837 ==
5724 23:07:26.296715 Dram Type= 6, Freq= 0, CH_1, rank 0
5725 23:07:26.299789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5726 23:07:26.299875 ==
5727 23:07:26.299962
5728 23:07:26.300044
5729 23:07:26.303549 TX Vref Scan disable
5730 23:07:26.303634 == TX Byte 0 ==
5731 23:07:26.310182 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5732 23:07:26.313437 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5733 23:07:26.313563 == TX Byte 1 ==
5734 23:07:26.320052 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5735 23:07:26.323087 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5736 23:07:26.323173 ==
5737 23:07:26.326469 Dram Type= 6, Freq= 0, CH_1, rank 0
5738 23:07:26.329870 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5739 23:07:26.329972 ==
5740 23:07:26.332919
5741 23:07:26.333017
5742 23:07:26.333104 TX Vref Scan disable
5743 23:07:26.336290 == TX Byte 0 ==
5744 23:07:26.339932 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5745 23:07:26.346434 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5746 23:07:26.346520 == TX Byte 1 ==
5747 23:07:26.349988 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5748 23:07:26.356528 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5749 23:07:26.356611
5750 23:07:26.356676 [DATLAT]
5751 23:07:26.356736 Freq=933, CH1 RK0
5752 23:07:26.356797
5753 23:07:26.359642 DATLAT Default: 0xd
5754 23:07:26.359724 0, 0xFFFF, sum = 0
5755 23:07:26.362841 1, 0xFFFF, sum = 0
5756 23:07:26.365947 2, 0xFFFF, sum = 0
5757 23:07:26.366031 3, 0xFFFF, sum = 0
5758 23:07:26.369726 4, 0xFFFF, sum = 0
5759 23:07:26.369810 5, 0xFFFF, sum = 0
5760 23:07:26.372872 6, 0xFFFF, sum = 0
5761 23:07:26.372956 7, 0xFFFF, sum = 0
5762 23:07:26.376139 8, 0xFFFF, sum = 0
5763 23:07:26.376223 9, 0xFFFF, sum = 0
5764 23:07:26.379153 10, 0x0, sum = 1
5765 23:07:26.379236 11, 0x0, sum = 2
5766 23:07:26.382839 12, 0x0, sum = 3
5767 23:07:26.382922 13, 0x0, sum = 4
5768 23:07:26.382988 best_step = 11
5769 23:07:26.385856
5770 23:07:26.385937 ==
5771 23:07:26.389318 Dram Type= 6, Freq= 0, CH_1, rank 0
5772 23:07:26.392682 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5773 23:07:26.392765 ==
5774 23:07:26.392830 RX Vref Scan: 1
5775 23:07:26.392891
5776 23:07:26.395770 RX Vref 0 -> 0, step: 1
5777 23:07:26.395852
5778 23:07:26.399191 RX Delay -69 -> 252, step: 4
5779 23:07:26.399274
5780 23:07:26.402937 Set Vref, RX VrefLevel [Byte0]: 60
5781 23:07:26.406073 [Byte1]: 50
5782 23:07:26.406156
5783 23:07:26.409464 Final RX Vref Byte 0 = 60 to rank0
5784 23:07:26.412716 Final RX Vref Byte 1 = 50 to rank0
5785 23:07:26.415681 Final RX Vref Byte 0 = 60 to rank1
5786 23:07:26.419144 Final RX Vref Byte 1 = 50 to rank1==
5787 23:07:26.422361 Dram Type= 6, Freq= 0, CH_1, rank 0
5788 23:07:26.425691 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5789 23:07:26.428957 ==
5790 23:07:26.429038 DQS Delay:
5791 23:07:26.429103 DQS0 = 0, DQS1 = 0
5792 23:07:26.432502 DQM Delay:
5793 23:07:26.432587 DQM0 = 96, DQM1 = 88
5794 23:07:26.435731 DQ Delay:
5795 23:07:26.439056 DQ0 =102, DQ1 =92, DQ2 =84, DQ3 =92
5796 23:07:26.442649 DQ4 =94, DQ5 =106, DQ6 =108, DQ7 =94
5797 23:07:26.442732 DQ8 =76, DQ9 =80, DQ10 =88, DQ11 =80
5798 23:07:26.448962 DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =94
5799 23:07:26.449045
5800 23:07:26.449110
5801 23:07:26.455814 [DQSOSCAuto] RK0, (LSB)MR18= 0x20b, (MSB)MR19= 0x505, tDQSOscB0 = 418 ps tDQSOscB1 = 421 ps
5802 23:07:26.459031 CH1 RK0: MR19=505, MR18=20B
5803 23:07:26.465433 CH1_RK0: MR19=0x505, MR18=0x20B, DQSOSC=418, MR23=63, INC=62, DEC=41
5804 23:07:26.465527
5805 23:07:26.468659 ----->DramcWriteLeveling(PI) begin...
5806 23:07:26.468742 ==
5807 23:07:26.472046 Dram Type= 6, Freq= 0, CH_1, rank 1
5808 23:07:26.475790 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5809 23:07:26.475874 ==
5810 23:07:26.478513 Write leveling (Byte 0): 24 => 24
5811 23:07:26.482328 Write leveling (Byte 1): 26 => 26
5812 23:07:26.485584 DramcWriteLeveling(PI) end<-----
5813 23:07:26.485667
5814 23:07:26.485731 ==
5815 23:07:26.488689 Dram Type= 6, Freq= 0, CH_1, rank 1
5816 23:07:26.491831 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5817 23:07:26.491914 ==
5818 23:07:26.495200 [Gating] SW mode calibration
5819 23:07:26.502034 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5820 23:07:26.508342 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5821 23:07:26.512133 0 14 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
5822 23:07:26.515270 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5823 23:07:26.522049 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5824 23:07:26.525177 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5825 23:07:26.528518 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5826 23:07:26.535028 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5827 23:07:26.538487 0 14 24 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 1)
5828 23:07:26.541720 0 14 28 | B1->B0 | 2e2e 2424 | 0 0 | (1 0) (0 0)
5829 23:07:26.548197 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5830 23:07:26.551472 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5831 23:07:26.554940 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5832 23:07:26.561774 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5833 23:07:26.564579 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5834 23:07:26.568193 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5835 23:07:26.575113 0 15 24 | B1->B0 | 2525 2929 | 0 1 | (0 0) (0 0)
5836 23:07:26.578438 0 15 28 | B1->B0 | 3434 4343 | 0 0 | (0 0) (1 1)
5837 23:07:26.581440 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5838 23:07:26.587899 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5839 23:07:26.591216 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5840 23:07:26.594384 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5841 23:07:26.601148 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5842 23:07:26.604695 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5843 23:07:26.607863 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5844 23:07:26.614426 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
5845 23:07:26.617596 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5846 23:07:26.620941 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5847 23:07:26.627845 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5848 23:07:26.631040 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5849 23:07:26.634551 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5850 23:07:26.641165 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5851 23:07:26.644191 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5852 23:07:26.647768 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5853 23:07:26.654284 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5854 23:07:26.657505 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5855 23:07:26.660886 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5856 23:07:26.667718 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5857 23:07:26.670743 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5858 23:07:26.674070 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5859 23:07:26.680638 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5860 23:07:26.683872 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5861 23:07:26.687337 Total UI for P1: 0, mck2ui 16
5862 23:07:26.690541 best dqsien dly found for B0: ( 1, 2, 24)
5863 23:07:26.694342 Total UI for P1: 0, mck2ui 16
5864 23:07:26.697533 best dqsien dly found for B1: ( 1, 2, 26)
5865 23:07:26.700808 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5866 23:07:26.703912 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5867 23:07:26.703982
5868 23:07:26.707552 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5869 23:07:26.710674 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5870 23:07:26.714042 [Gating] SW calibration Done
5871 23:07:26.714136 ==
5872 23:07:26.717240 Dram Type= 6, Freq= 0, CH_1, rank 1
5873 23:07:26.720569 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5874 23:07:26.720653 ==
5875 23:07:26.723800 RX Vref Scan: 0
5876 23:07:26.723883
5877 23:07:26.726972 RX Vref 0 -> 0, step: 1
5878 23:07:26.727054
5879 23:07:26.727118 RX Delay -80 -> 252, step: 8
5880 23:07:26.733982 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5881 23:07:26.737241 iDelay=208, Bit 1, Center 87 (-8 ~ 183) 192
5882 23:07:26.740973 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5883 23:07:26.743934 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5884 23:07:26.747139 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5885 23:07:26.753891 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5886 23:07:26.757041 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5887 23:07:26.760319 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5888 23:07:26.763564 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5889 23:07:26.766899 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5890 23:07:26.770572 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5891 23:07:26.777140 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5892 23:07:26.780404 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5893 23:07:26.783674 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5894 23:07:26.786922 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5895 23:07:26.790250 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5896 23:07:26.790376 ==
5897 23:07:26.793329 Dram Type= 6, Freq= 0, CH_1, rank 1
5898 23:07:26.800120 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5899 23:07:26.800204 ==
5900 23:07:26.800270 DQS Delay:
5901 23:07:26.803447 DQS0 = 0, DQS1 = 0
5902 23:07:26.803529 DQM Delay:
5903 23:07:26.803594 DQM0 = 93, DQM1 = 89
5904 23:07:26.806627 DQ Delay:
5905 23:07:26.809990 DQ0 =99, DQ1 =87, DQ2 =83, DQ3 =91
5906 23:07:26.813299 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91
5907 23:07:26.816710 DQ8 =75, DQ9 =79, DQ10 =95, DQ11 =83
5908 23:07:26.819795 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5909 23:07:26.819883
5910 23:07:26.819949
5911 23:07:26.820010 ==
5912 23:07:26.823154 Dram Type= 6, Freq= 0, CH_1, rank 1
5913 23:07:26.826416 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5914 23:07:26.826499 ==
5915 23:07:26.826564
5916 23:07:26.826625
5917 23:07:26.830261 TX Vref Scan disable
5918 23:07:26.833446 == TX Byte 0 ==
5919 23:07:26.836611 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5920 23:07:26.839837 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5921 23:07:26.843119 == TX Byte 1 ==
5922 23:07:26.846286 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5923 23:07:26.849686 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5924 23:07:26.849796 ==
5925 23:07:26.853288 Dram Type= 6, Freq= 0, CH_1, rank 1
5926 23:07:26.856309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5927 23:07:26.859900 ==
5928 23:07:26.860006
5929 23:07:26.860102
5930 23:07:26.860191 TX Vref Scan disable
5931 23:07:26.863323 == TX Byte 0 ==
5932 23:07:26.866672 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5933 23:07:26.873109 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5934 23:07:26.873185 == TX Byte 1 ==
5935 23:07:26.876616 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5936 23:07:26.883006 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5937 23:07:26.883107
5938 23:07:26.883200 [DATLAT]
5939 23:07:26.883290 Freq=933, CH1 RK1
5940 23:07:26.883375
5941 23:07:26.886859 DATLAT Default: 0xb
5942 23:07:26.886932 0, 0xFFFF, sum = 0
5943 23:07:26.889725 1, 0xFFFF, sum = 0
5944 23:07:26.893017 2, 0xFFFF, sum = 0
5945 23:07:26.893117 3, 0xFFFF, sum = 0
5946 23:07:26.896621 4, 0xFFFF, sum = 0
5947 23:07:26.896723 5, 0xFFFF, sum = 0
5948 23:07:26.899695 6, 0xFFFF, sum = 0
5949 23:07:26.899770 7, 0xFFFF, sum = 0
5950 23:07:26.902766 8, 0xFFFF, sum = 0
5951 23:07:26.902865 9, 0xFFFF, sum = 0
5952 23:07:26.906383 10, 0x0, sum = 1
5953 23:07:26.906461 11, 0x0, sum = 2
5954 23:07:26.909423 12, 0x0, sum = 3
5955 23:07:26.909545 13, 0x0, sum = 4
5956 23:07:26.909611 best_step = 11
5957 23:07:26.912771
5958 23:07:26.912844 ==
5959 23:07:26.916059 Dram Type= 6, Freq= 0, CH_1, rank 1
5960 23:07:26.919227 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5961 23:07:26.919326 ==
5962 23:07:26.919426 RX Vref Scan: 0
5963 23:07:26.919488
5964 23:07:26.922511 RX Vref 0 -> 0, step: 1
5965 23:07:26.922582
5966 23:07:26.926010 RX Delay -69 -> 252, step: 4
5967 23:07:26.932646 iDelay=203, Bit 0, Center 94 (-5 ~ 194) 200
5968 23:07:26.935731 iDelay=203, Bit 1, Center 88 (-5 ~ 182) 188
5969 23:07:26.939518 iDelay=203, Bit 2, Center 82 (-13 ~ 178) 192
5970 23:07:26.942615 iDelay=203, Bit 3, Center 88 (-9 ~ 186) 196
5971 23:07:26.945844 iDelay=203, Bit 4, Center 90 (-5 ~ 186) 192
5972 23:07:26.949135 iDelay=203, Bit 5, Center 104 (7 ~ 202) 196
5973 23:07:26.955976 iDelay=203, Bit 6, Center 104 (7 ~ 202) 196
5974 23:07:26.959216 iDelay=203, Bit 7, Center 90 (-5 ~ 186) 192
5975 23:07:26.962527 iDelay=203, Bit 8, Center 78 (-13 ~ 170) 184
5976 23:07:26.966144 iDelay=203, Bit 9, Center 84 (-9 ~ 178) 188
5977 23:07:26.969158 iDelay=203, Bit 10, Center 90 (-5 ~ 186) 192
5978 23:07:26.972983 iDelay=203, Bit 11, Center 84 (-9 ~ 178) 188
5979 23:07:26.979139 iDelay=203, Bit 12, Center 98 (7 ~ 190) 184
5980 23:07:26.982972 iDelay=203, Bit 13, Center 98 (7 ~ 190) 184
5981 23:07:26.985804 iDelay=203, Bit 14, Center 98 (7 ~ 190) 184
5982 23:07:26.988983 iDelay=203, Bit 15, Center 98 (7 ~ 190) 184
5983 23:07:26.989065 ==
5984 23:07:26.992728 Dram Type= 6, Freq= 0, CH_1, rank 1
5985 23:07:26.995779 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5986 23:07:26.999047 ==
5987 23:07:26.999129 DQS Delay:
5988 23:07:26.999194 DQS0 = 0, DQS1 = 0
5989 23:07:27.002555 DQM Delay:
5990 23:07:27.002638 DQM0 = 92, DQM1 = 91
5991 23:07:27.005966 DQ Delay:
5992 23:07:27.008979 DQ0 =94, DQ1 =88, DQ2 =82, DQ3 =88
5993 23:07:27.012306 DQ4 =90, DQ5 =104, DQ6 =104, DQ7 =90
5994 23:07:27.015352 DQ8 =78, DQ9 =84, DQ10 =90, DQ11 =84
5995 23:07:27.019000 DQ12 =98, DQ13 =98, DQ14 =98, DQ15 =98
5996 23:07:27.019083
5997 23:07:27.019147
5998 23:07:27.025645 [DQSOSCAuto] RK1, (LSB)MR18= 0x1125, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 416 ps
5999 23:07:27.029238 CH1 RK1: MR19=505, MR18=1125
6000 23:07:27.035429 CH1_RK1: MR19=0x505, MR18=0x1125, DQSOSC=410, MR23=63, INC=64, DEC=42
6001 23:07:27.038788 [RxdqsGatingPostProcess] freq 933
6002 23:07:27.041873 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6003 23:07:27.045620 best DQS0 dly(2T, 0.5T) = (0, 11)
6004 23:07:27.048841 best DQS1 dly(2T, 0.5T) = (0, 11)
6005 23:07:27.052021 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
6006 23:07:27.055237 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
6007 23:07:27.058496 best DQS0 dly(2T, 0.5T) = (0, 10)
6008 23:07:27.061826 best DQS1 dly(2T, 0.5T) = (0, 10)
6009 23:07:27.065201 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6010 23:07:27.068310 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6011 23:07:27.071691 Pre-setting of DQS Precalculation
6012 23:07:27.075070 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6013 23:07:27.084948 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6014 23:07:27.091804 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6015 23:07:27.091887
6016 23:07:27.091953
6017 23:07:27.095021 [Calibration Summary] 1866 Mbps
6018 23:07:27.095104 CH 0, Rank 0
6019 23:07:27.098360 SW Impedance : PASS
6020 23:07:27.098443 DUTY Scan : NO K
6021 23:07:27.101588 ZQ Calibration : PASS
6022 23:07:27.104792 Jitter Meter : NO K
6023 23:07:27.104875 CBT Training : PASS
6024 23:07:27.107963 Write leveling : PASS
6025 23:07:27.111253 RX DQS gating : PASS
6026 23:07:27.111336 RX DQ/DQS(RDDQC) : PASS
6027 23:07:27.114985 TX DQ/DQS : PASS
6028 23:07:27.118306 RX DATLAT : PASS
6029 23:07:27.118389 RX DQ/DQS(Engine): PASS
6030 23:07:27.121630 TX OE : NO K
6031 23:07:27.121713 All Pass.
6032 23:07:27.121778
6033 23:07:27.124813 CH 0, Rank 1
6034 23:07:27.124895 SW Impedance : PASS
6035 23:07:27.127979 DUTY Scan : NO K
6036 23:07:27.131421 ZQ Calibration : PASS
6037 23:07:27.131504 Jitter Meter : NO K
6038 23:07:27.134893 CBT Training : PASS
6039 23:07:27.134975 Write leveling : PASS
6040 23:07:27.138239 RX DQS gating : PASS
6041 23:07:27.141739 RX DQ/DQS(RDDQC) : PASS
6042 23:07:27.141820 TX DQ/DQS : PASS
6043 23:07:27.144624 RX DATLAT : PASS
6044 23:07:27.148079 RX DQ/DQS(Engine): PASS
6045 23:07:27.148182 TX OE : NO K
6046 23:07:27.151177 All Pass.
6047 23:07:27.151287
6048 23:07:27.151379 CH 1, Rank 0
6049 23:07:27.154347 SW Impedance : PASS
6050 23:07:27.154452 DUTY Scan : NO K
6051 23:07:27.157633 ZQ Calibration : PASS
6052 23:07:27.160801 Jitter Meter : NO K
6053 23:07:27.160880 CBT Training : PASS
6054 23:07:27.164111 Write leveling : PASS
6055 23:07:27.167460 RX DQS gating : PASS
6056 23:07:27.167561 RX DQ/DQS(RDDQC) : PASS
6057 23:07:27.171239 TX DQ/DQS : PASS
6058 23:07:27.174044 RX DATLAT : PASS
6059 23:07:27.174145 RX DQ/DQS(Engine): PASS
6060 23:07:27.177693 TX OE : NO K
6061 23:07:27.177769 All Pass.
6062 23:07:27.177831
6063 23:07:27.180682 CH 1, Rank 1
6064 23:07:27.180756 SW Impedance : PASS
6065 23:07:27.184327 DUTY Scan : NO K
6066 23:07:27.187637 ZQ Calibration : PASS
6067 23:07:27.187828 Jitter Meter : NO K
6068 23:07:27.190663 CBT Training : PASS
6069 23:07:27.194048 Write leveling : PASS
6070 23:07:27.194147 RX DQS gating : PASS
6071 23:07:27.197128 RX DQ/DQS(RDDQC) : PASS
6072 23:07:27.200800 TX DQ/DQS : PASS
6073 23:07:27.200877 RX DATLAT : PASS
6074 23:07:27.203982 RX DQ/DQS(Engine): PASS
6075 23:07:27.204078 TX OE : NO K
6076 23:07:27.207214 All Pass.
6077 23:07:27.207308
6078 23:07:27.207405 DramC Write-DBI off
6079 23:07:27.210360 PER_BANK_REFRESH: Hybrid Mode
6080 23:07:27.214128 TX_TRACKING: ON
6081 23:07:27.220411 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6082 23:07:27.223778 [FAST_K] Save calibration result to emmc
6083 23:07:27.230592 dramc_set_vcore_voltage set vcore to 650000
6084 23:07:27.230663 Read voltage for 400, 6
6085 23:07:27.230724 Vio18 = 0
6086 23:07:27.233766 Vcore = 650000
6087 23:07:27.233837 Vdram = 0
6088 23:07:27.233897 Vddq = 0
6089 23:07:27.236866 Vmddr = 0
6090 23:07:27.240204 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6091 23:07:27.246763 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6092 23:07:27.250125 MEM_TYPE=3, freq_sel=20
6093 23:07:27.250197 sv_algorithm_assistance_LP4_800
6094 23:07:27.256704 ============ PULL DRAM RESETB DOWN ============
6095 23:07:27.260130 ========== PULL DRAM RESETB DOWN end =========
6096 23:07:27.263670 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6097 23:07:27.266876 ===================================
6098 23:07:27.270089 LPDDR4 DRAM CONFIGURATION
6099 23:07:27.273379 ===================================
6100 23:07:27.276661 EX_ROW_EN[0] = 0x0
6101 23:07:27.276744 EX_ROW_EN[1] = 0x0
6102 23:07:27.279802 LP4Y_EN = 0x0
6103 23:07:27.279885 WORK_FSP = 0x0
6104 23:07:27.283082 WL = 0x2
6105 23:07:27.283164 RL = 0x2
6106 23:07:27.286427 BL = 0x2
6107 23:07:27.286508 RPST = 0x0
6108 23:07:27.289669 RD_PRE = 0x0
6109 23:07:27.289751 WR_PRE = 0x1
6110 23:07:27.293538 WR_PST = 0x0
6111 23:07:27.293635 DBI_WR = 0x0
6112 23:07:27.296578 DBI_RD = 0x0
6113 23:07:27.300078 OTF = 0x1
6114 23:07:27.303356 ===================================
6115 23:07:27.303459 ===================================
6116 23:07:27.306688 ANA top config
6117 23:07:27.309882 ===================================
6118 23:07:27.313079 DLL_ASYNC_EN = 0
6119 23:07:27.313165 ALL_SLAVE_EN = 1
6120 23:07:27.316239 NEW_RANK_MODE = 1
6121 23:07:27.319381 DLL_IDLE_MODE = 1
6122 23:07:27.323157 LP45_APHY_COMB_EN = 1
6123 23:07:27.326256 TX_ODT_DIS = 1
6124 23:07:27.326327 NEW_8X_MODE = 1
6125 23:07:27.329661 ===================================
6126 23:07:27.332759 ===================================
6127 23:07:27.336134 data_rate = 800
6128 23:07:27.339382 CKR = 1
6129 23:07:27.342469 DQ_P2S_RATIO = 4
6130 23:07:27.346092 ===================================
6131 23:07:27.349527 CA_P2S_RATIO = 4
6132 23:07:27.352398 DQ_CA_OPEN = 0
6133 23:07:27.352499 DQ_SEMI_OPEN = 1
6134 23:07:27.355952 CA_SEMI_OPEN = 1
6135 23:07:27.359222 CA_FULL_RATE = 0
6136 23:07:27.362735 DQ_CKDIV4_EN = 0
6137 23:07:27.365938 CA_CKDIV4_EN = 1
6138 23:07:27.369062 CA_PREDIV_EN = 0
6139 23:07:27.369195 PH8_DLY = 0
6140 23:07:27.372471 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6141 23:07:27.375782 DQ_AAMCK_DIV = 0
6142 23:07:27.379078 CA_AAMCK_DIV = 0
6143 23:07:27.382274 CA_ADMCK_DIV = 4
6144 23:07:27.385447 DQ_TRACK_CA_EN = 0
6145 23:07:27.388913 CA_PICK = 800
6146 23:07:27.389020 CA_MCKIO = 400
6147 23:07:27.392619 MCKIO_SEMI = 400
6148 23:07:27.395684 PLL_FREQ = 3016
6149 23:07:27.398916 DQ_UI_PI_RATIO = 32
6150 23:07:27.402280 CA_UI_PI_RATIO = 32
6151 23:07:27.405594 ===================================
6152 23:07:27.408603 ===================================
6153 23:07:27.412151 memory_type:LPDDR4
6154 23:07:27.412256 GP_NUM : 10
6155 23:07:27.415389 SRAM_EN : 1
6156 23:07:27.415500 MD32_EN : 0
6157 23:07:27.418818 ===================================
6158 23:07:27.421826 [ANA_INIT] >>>>>>>>>>>>>>
6159 23:07:27.425553 <<<<<< [CONFIGURE PHASE]: ANA_TX
6160 23:07:27.428736 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6161 23:07:27.431986 ===================================
6162 23:07:27.435308 data_rate = 800,PCW = 0X7400
6163 23:07:27.438420 ===================================
6164 23:07:27.441781 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6165 23:07:27.448513 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6166 23:07:27.458494 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6167 23:07:27.464736 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6168 23:07:27.467945 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6169 23:07:27.471883 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6170 23:07:27.471955 [ANA_INIT] flow start
6171 23:07:27.474552 [ANA_INIT] PLL >>>>>>>>
6172 23:07:27.478131 [ANA_INIT] PLL <<<<<<<<
6173 23:07:27.478231 [ANA_INIT] MIDPI >>>>>>>>
6174 23:07:27.481456 [ANA_INIT] MIDPI <<<<<<<<
6175 23:07:27.484588 [ANA_INIT] DLL >>>>>>>>
6176 23:07:27.484661 [ANA_INIT] flow end
6177 23:07:27.491129 ============ LP4 DIFF to SE enter ============
6178 23:07:27.494844 ============ LP4 DIFF to SE exit ============
6179 23:07:27.494955 [ANA_INIT] <<<<<<<<<<<<<
6180 23:07:27.497883 [Flow] Enable top DCM control >>>>>
6181 23:07:27.501113 [Flow] Enable top DCM control <<<<<
6182 23:07:27.504599 Enable DLL master slave shuffle
6183 23:07:27.511460 ==============================================================
6184 23:07:27.514669 Gating Mode config
6185 23:07:27.517753 ==============================================================
6186 23:07:27.521371 Config description:
6187 23:07:27.530920 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6188 23:07:27.537877 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6189 23:07:27.541270 SELPH_MODE 0: By rank 1: By Phase
6190 23:07:27.547697 ==============================================================
6191 23:07:27.550959 GAT_TRACK_EN = 0
6192 23:07:27.554176 RX_GATING_MODE = 2
6193 23:07:27.557806 RX_GATING_TRACK_MODE = 2
6194 23:07:27.557879 SELPH_MODE = 1
6195 23:07:27.560960 PICG_EARLY_EN = 1
6196 23:07:27.564168 VALID_LAT_VALUE = 1
6197 23:07:27.571161 ==============================================================
6198 23:07:27.574515 Enter into Gating configuration >>>>
6199 23:07:27.577680 Exit from Gating configuration <<<<
6200 23:07:27.580953 Enter into DVFS_PRE_config >>>>>
6201 23:07:27.590415 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6202 23:07:27.593933 Exit from DVFS_PRE_config <<<<<
6203 23:07:27.597096 Enter into PICG configuration >>>>
6204 23:07:27.600633 Exit from PICG configuration <<<<
6205 23:07:27.603704 [RX_INPUT] configuration >>>>>
6206 23:07:27.607536 [RX_INPUT] configuration <<<<<
6207 23:07:27.610501 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6208 23:07:27.616779 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6209 23:07:27.623438 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6210 23:07:27.630231 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6211 23:07:27.636734 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6212 23:07:27.643304 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6213 23:07:27.646699 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6214 23:07:27.650179 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6215 23:07:27.653603 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6216 23:07:27.656625 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6217 23:07:27.663484 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6218 23:07:27.666817 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6219 23:07:27.670229 ===================================
6220 23:07:27.673337 LPDDR4 DRAM CONFIGURATION
6221 23:07:27.676635 ===================================
6222 23:07:27.676718 EX_ROW_EN[0] = 0x0
6223 23:07:27.679746 EX_ROW_EN[1] = 0x0
6224 23:07:27.679829 LP4Y_EN = 0x0
6225 23:07:27.683012 WORK_FSP = 0x0
6226 23:07:27.686217 WL = 0x2
6227 23:07:27.686300 RL = 0x2
6228 23:07:27.689607 BL = 0x2
6229 23:07:27.689689 RPST = 0x0
6230 23:07:27.693239 RD_PRE = 0x0
6231 23:07:27.693323 WR_PRE = 0x1
6232 23:07:27.696476 WR_PST = 0x0
6233 23:07:27.696558 DBI_WR = 0x0
6234 23:07:27.699764 DBI_RD = 0x0
6235 23:07:27.699846 OTF = 0x1
6236 23:07:27.702882 ===================================
6237 23:07:27.706492 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6238 23:07:27.712938 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6239 23:07:27.716008 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6240 23:07:27.719292 ===================================
6241 23:07:27.722757 LPDDR4 DRAM CONFIGURATION
6242 23:07:27.725937 ===================================
6243 23:07:27.726020 EX_ROW_EN[0] = 0x10
6244 23:07:27.729212 EX_ROW_EN[1] = 0x0
6245 23:07:27.729294 LP4Y_EN = 0x0
6246 23:07:27.732729 WORK_FSP = 0x0
6247 23:07:27.736401 WL = 0x2
6248 23:07:27.736483 RL = 0x2
6249 23:07:27.739571 BL = 0x2
6250 23:07:27.739653 RPST = 0x0
6251 23:07:27.742519 RD_PRE = 0x0
6252 23:07:27.742602 WR_PRE = 0x1
6253 23:07:27.745990 WR_PST = 0x0
6254 23:07:27.746073 DBI_WR = 0x0
6255 23:07:27.749226 DBI_RD = 0x0
6256 23:07:27.749308 OTF = 0x1
6257 23:07:27.752284 ===================================
6258 23:07:27.758749 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6259 23:07:27.763023 nWR fixed to 30
6260 23:07:27.766769 [ModeRegInit_LP4] CH0 RK0
6261 23:07:27.766851 [ModeRegInit_LP4] CH0 RK1
6262 23:07:27.770039 [ModeRegInit_LP4] CH1 RK0
6263 23:07:27.773348 [ModeRegInit_LP4] CH1 RK1
6264 23:07:27.773431 match AC timing 19
6265 23:07:27.779803 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6266 23:07:27.783273 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6267 23:07:27.786610 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6268 23:07:27.793265 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6269 23:07:27.796315 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6270 23:07:27.796398 ==
6271 23:07:27.799718 Dram Type= 6, Freq= 0, CH_0, rank 0
6272 23:07:27.802776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6273 23:07:27.802860 ==
6274 23:07:27.809634 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6275 23:07:27.815999 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6276 23:07:27.819620 [CA 0] Center 36 (8~64) winsize 57
6277 23:07:27.822649 [CA 1] Center 36 (8~64) winsize 57
6278 23:07:27.826359 [CA 2] Center 36 (8~64) winsize 57
6279 23:07:27.829786 [CA 3] Center 36 (8~64) winsize 57
6280 23:07:27.829868 [CA 4] Center 36 (8~64) winsize 57
6281 23:07:27.832885 [CA 5] Center 36 (8~64) winsize 57
6282 23:07:27.832967
6283 23:07:27.839814 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6284 23:07:27.839897
6285 23:07:27.842714 [CATrainingPosCal] consider 1 rank data
6286 23:07:27.846048 u2DelayCellTimex100 = 270/100 ps
6287 23:07:27.849382 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6288 23:07:27.853091 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6289 23:07:27.856069 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6290 23:07:27.859218 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6291 23:07:27.862826 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6292 23:07:27.866027 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6293 23:07:27.866110
6294 23:07:27.869744 CA PerBit enable=1, Macro0, CA PI delay=36
6295 23:07:27.869827
6296 23:07:27.872896 [CBTSetCACLKResult] CA Dly = 36
6297 23:07:27.876284 CS Dly: 1 (0~32)
6298 23:07:27.876366 ==
6299 23:07:27.879454 Dram Type= 6, Freq= 0, CH_0, rank 1
6300 23:07:27.882790 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6301 23:07:27.882877 ==
6302 23:07:27.889144 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6303 23:07:27.892524 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6304 23:07:27.895684 [CA 0] Center 36 (8~64) winsize 57
6305 23:07:27.899274 [CA 1] Center 36 (8~64) winsize 57
6306 23:07:27.902617 [CA 2] Center 36 (8~64) winsize 57
6307 23:07:27.905895 [CA 3] Center 36 (8~64) winsize 57
6308 23:07:27.909231 [CA 4] Center 36 (8~64) winsize 57
6309 23:07:27.912786 [CA 5] Center 36 (8~64) winsize 57
6310 23:07:27.912869
6311 23:07:27.916139 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6312 23:07:27.916221
6313 23:07:27.919479 [CATrainingPosCal] consider 2 rank data
6314 23:07:27.922529 u2DelayCellTimex100 = 270/100 ps
6315 23:07:27.925963 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6316 23:07:27.929009 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6317 23:07:27.935926 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6318 23:07:27.939350 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6319 23:07:27.942502 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6320 23:07:27.945607 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6321 23:07:27.945710
6322 23:07:27.948870 CA PerBit enable=1, Macro0, CA PI delay=36
6323 23:07:27.948945
6324 23:07:27.952562 [CBTSetCACLKResult] CA Dly = 36
6325 23:07:27.952660 CS Dly: 1 (0~32)
6326 23:07:27.952725
6327 23:07:27.955745 ----->DramcWriteLeveling(PI) begin...
6328 23:07:27.959155 ==
6329 23:07:27.959256 Dram Type= 6, Freq= 0, CH_0, rank 0
6330 23:07:27.965706 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6331 23:07:27.965812 ==
6332 23:07:27.968903 Write leveling (Byte 0): 40 => 8
6333 23:07:27.972149 Write leveling (Byte 1): 32 => 0
6334 23:07:27.972250 DramcWriteLeveling(PI) end<-----
6335 23:07:27.975886
6336 23:07:27.975984 ==
6337 23:07:27.978729 Dram Type= 6, Freq= 0, CH_0, rank 0
6338 23:07:27.982548 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6339 23:07:27.982646 ==
6340 23:07:27.985865 [Gating] SW mode calibration
6341 23:07:27.992376 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6342 23:07:27.995448 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6343 23:07:28.001925 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6344 23:07:28.005118 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6345 23:07:28.008776 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6346 23:07:28.015306 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6347 23:07:28.018431 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6348 23:07:28.022286 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6349 23:07:28.028627 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6350 23:07:28.031766 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6351 23:07:28.035337 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6352 23:07:28.038283 Total UI for P1: 0, mck2ui 16
6353 23:07:28.041550 best dqsien dly found for B0: ( 0, 14, 24)
6354 23:07:28.044942 Total UI for P1: 0, mck2ui 16
6355 23:07:28.048727 best dqsien dly found for B1: ( 0, 14, 24)
6356 23:07:28.051806 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6357 23:07:28.058436 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6358 23:07:28.058547
6359 23:07:28.061385 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6360 23:07:28.064944 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6361 23:07:28.068243 [Gating] SW calibration Done
6362 23:07:28.068317 ==
6363 23:07:28.071755 Dram Type= 6, Freq= 0, CH_0, rank 0
6364 23:07:28.075629 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6365 23:07:28.075700 ==
6366 23:07:28.075778 RX Vref Scan: 0
6367 23:07:28.078199
6368 23:07:28.078269 RX Vref 0 -> 0, step: 1
6369 23:07:28.078328
6370 23:07:28.081766 RX Delay -410 -> 252, step: 16
6371 23:07:28.085102 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6372 23:07:28.091567 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6373 23:07:28.094903 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6374 23:07:28.097730 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6375 23:07:28.101389 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6376 23:07:28.108141 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6377 23:07:28.111005 iDelay=230, Bit 6, Center -35 (-282 ~ 213) 496
6378 23:07:28.114771 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6379 23:07:28.118092 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6380 23:07:28.124454 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6381 23:07:28.127786 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6382 23:07:28.130956 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6383 23:07:28.137901 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6384 23:07:28.141243 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6385 23:07:28.144269 iDelay=230, Bit 14, Center -35 (-298 ~ 229) 528
6386 23:07:28.147676 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6387 23:07:28.147775 ==
6388 23:07:28.151122 Dram Type= 6, Freq= 0, CH_0, rank 0
6389 23:07:28.157427 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6390 23:07:28.157570 ==
6391 23:07:28.157635 DQS Delay:
6392 23:07:28.160925 DQS0 = 59, DQS1 = 59
6393 23:07:28.161025 DQM Delay:
6394 23:07:28.164196 DQM0 = 17, DQM1 = 10
6395 23:07:28.164297 DQ Delay:
6396 23:07:28.167365 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6397 23:07:28.170487 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =32
6398 23:07:28.174101 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6399 23:07:28.177412 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6400 23:07:28.177549
6401 23:07:28.177613
6402 23:07:28.177679 ==
6403 23:07:28.180939 Dram Type= 6, Freq= 0, CH_0, rank 0
6404 23:07:28.183724 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6405 23:07:28.183825 ==
6406 23:07:28.183916
6407 23:07:28.184004
6408 23:07:28.187103 TX Vref Scan disable
6409 23:07:28.187175 == TX Byte 0 ==
6410 23:07:28.193950 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6411 23:07:28.197119 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6412 23:07:28.197220 == TX Byte 1 ==
6413 23:07:28.203644 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6414 23:07:28.206854 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6415 23:07:28.206925 ==
6416 23:07:28.210288 Dram Type= 6, Freq= 0, CH_0, rank 0
6417 23:07:28.213851 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6418 23:07:28.213919 ==
6419 23:07:28.213979
6420 23:07:28.214041
6421 23:07:28.216759 TX Vref Scan disable
6422 23:07:28.216823 == TX Byte 0 ==
6423 23:07:28.223817 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6424 23:07:28.226920 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6425 23:07:28.227021 == TX Byte 1 ==
6426 23:07:28.233356 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6427 23:07:28.237014 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6428 23:07:28.237116
6429 23:07:28.237207 [DATLAT]
6430 23:07:28.240319 Freq=400, CH0 RK0
6431 23:07:28.240420
6432 23:07:28.240515 DATLAT Default: 0xf
6433 23:07:28.243626 0, 0xFFFF, sum = 0
6434 23:07:28.243730 1, 0xFFFF, sum = 0
6435 23:07:28.246828 2, 0xFFFF, sum = 0
6436 23:07:28.246903 3, 0xFFFF, sum = 0
6437 23:07:28.249955 4, 0xFFFF, sum = 0
6438 23:07:28.253844 5, 0xFFFF, sum = 0
6439 23:07:28.253936 6, 0xFFFF, sum = 0
6440 23:07:28.256753 7, 0xFFFF, sum = 0
6441 23:07:28.256837 8, 0xFFFF, sum = 0
6442 23:07:28.260371 9, 0xFFFF, sum = 0
6443 23:07:28.260455 10, 0xFFFF, sum = 0
6444 23:07:28.263576 11, 0xFFFF, sum = 0
6445 23:07:28.263660 12, 0xFFFF, sum = 0
6446 23:07:28.266752 13, 0x0, sum = 1
6447 23:07:28.266835 14, 0x0, sum = 2
6448 23:07:28.270051 15, 0x0, sum = 3
6449 23:07:28.270135 16, 0x0, sum = 4
6450 23:07:28.273455 best_step = 14
6451 23:07:28.273578
6452 23:07:28.273643 ==
6453 23:07:28.276663 Dram Type= 6, Freq= 0, CH_0, rank 0
6454 23:07:28.280478 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6455 23:07:28.280561 ==
6456 23:07:28.280626 RX Vref Scan: 1
6457 23:07:28.280685
6458 23:07:28.283463 RX Vref 0 -> 0, step: 1
6459 23:07:28.283545
6460 23:07:28.286726 RX Delay -359 -> 252, step: 8
6461 23:07:28.286809
6462 23:07:28.290259 Set Vref, RX VrefLevel [Byte0]: 60
6463 23:07:28.293203 [Byte1]: 58
6464 23:07:28.297279
6465 23:07:28.297361 Final RX Vref Byte 0 = 60 to rank0
6466 23:07:28.300823 Final RX Vref Byte 1 = 58 to rank0
6467 23:07:28.303808 Final RX Vref Byte 0 = 60 to rank1
6468 23:07:28.307035 Final RX Vref Byte 1 = 58 to rank1==
6469 23:07:28.310700 Dram Type= 6, Freq= 0, CH_0, rank 0
6470 23:07:28.317288 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6471 23:07:28.317371 ==
6472 23:07:28.317437 DQS Delay:
6473 23:07:28.320414 DQS0 = 60, DQS1 = 68
6474 23:07:28.320496 DQM Delay:
6475 23:07:28.320561 DQM0 = 14, DQM1 = 14
6476 23:07:28.323817 DQ Delay:
6477 23:07:28.327299 DQ0 =12, DQ1 =16, DQ2 =8, DQ3 =12
6478 23:07:28.330638 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6479 23:07:28.330721 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6480 23:07:28.333984 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6481 23:07:28.337233
6482 23:07:28.337315
6483 23:07:28.344079 [DQSOSCAuto] RK0, (LSB)MR18= 0x7d7b, (MSB)MR19= 0xc0c, tDQSOscB0 = 394 ps tDQSOscB1 = 394 ps
6484 23:07:28.347318 CH0 RK0: MR19=C0C, MR18=7D7B
6485 23:07:28.353694 CH0_RK0: MR19=0xC0C, MR18=0x7D7B, DQSOSC=394, MR23=63, INC=380, DEC=253
6486 23:07:28.353777 ==
6487 23:07:28.357042 Dram Type= 6, Freq= 0, CH_0, rank 1
6488 23:07:28.360173 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6489 23:07:28.360256 ==
6490 23:07:28.363628 [Gating] SW mode calibration
6491 23:07:28.370308 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6492 23:07:28.376789 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6493 23:07:28.380365 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6494 23:07:28.383460 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6495 23:07:28.390215 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6496 23:07:28.393631 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6497 23:07:28.396802 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6498 23:07:28.403201 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6499 23:07:28.406573 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6500 23:07:28.409761 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6501 23:07:28.416664 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6502 23:07:28.416778 Total UI for P1: 0, mck2ui 16
6503 23:07:28.423130 best dqsien dly found for B0: ( 0, 14, 24)
6504 23:07:28.423212 Total UI for P1: 0, mck2ui 16
6505 23:07:28.429634 best dqsien dly found for B1: ( 0, 14, 24)
6506 23:07:28.433161 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6507 23:07:28.436382 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6508 23:07:28.436524
6509 23:07:28.439509 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6510 23:07:28.443254 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6511 23:07:28.446291 [Gating] SW calibration Done
6512 23:07:28.446374 ==
6513 23:07:28.449619 Dram Type= 6, Freq= 0, CH_0, rank 1
6514 23:07:28.452746 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6515 23:07:28.452856 ==
6516 23:07:28.456128 RX Vref Scan: 0
6517 23:07:28.456211
6518 23:07:28.456276 RX Vref 0 -> 0, step: 1
6519 23:07:28.456336
6520 23:07:28.459356 RX Delay -410 -> 252, step: 16
6521 23:07:28.466381 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6522 23:07:28.469968 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6523 23:07:28.472902 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6524 23:07:28.475956 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6525 23:07:28.482748 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6526 23:07:28.486001 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6527 23:07:28.489286 iDelay=230, Bit 6, Center -35 (-298 ~ 229) 528
6528 23:07:28.492694 iDelay=230, Bit 7, Center -35 (-298 ~ 229) 528
6529 23:07:28.499184 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6530 23:07:28.502429 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6531 23:07:28.505752 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6532 23:07:28.509429 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6533 23:07:28.515874 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6534 23:07:28.519281 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6535 23:07:28.522612 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6536 23:07:28.525786 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6537 23:07:28.529154 ==
6538 23:07:28.532989 Dram Type= 6, Freq= 0, CH_0, rank 1
6539 23:07:28.535604 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6540 23:07:28.535687 ==
6541 23:07:28.535753 DQS Delay:
6542 23:07:28.539366 DQS0 = 59, DQS1 = 59
6543 23:07:28.539448 DQM Delay:
6544 23:07:28.542385 DQM0 = 16, DQM1 = 10
6545 23:07:28.542467 DQ Delay:
6546 23:07:28.545976 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6547 23:07:28.549082 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6548 23:07:28.552235 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6549 23:07:28.555901 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6550 23:07:28.555984
6551 23:07:28.556049
6552 23:07:28.556109 ==
6553 23:07:28.558808 Dram Type= 6, Freq= 0, CH_0, rank 1
6554 23:07:28.562137 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6555 23:07:28.562221 ==
6556 23:07:28.562286
6557 23:07:28.562346
6558 23:07:28.565949 TX Vref Scan disable
6559 23:07:28.566032 == TX Byte 0 ==
6560 23:07:28.572421 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6561 23:07:28.575760 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6562 23:07:28.575843 == TX Byte 1 ==
6563 23:07:28.582568 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6564 23:07:28.585638 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6565 23:07:28.585721 ==
6566 23:07:28.588657 Dram Type= 6, Freq= 0, CH_0, rank 1
6567 23:07:28.592308 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6568 23:07:28.592391 ==
6569 23:07:28.592457
6570 23:07:28.592525
6571 23:07:28.595376 TX Vref Scan disable
6572 23:07:28.595459 == TX Byte 0 ==
6573 23:07:28.601987 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6574 23:07:28.605234 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6575 23:07:28.605317 == TX Byte 1 ==
6576 23:07:28.612220 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6577 23:07:28.615388 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6578 23:07:28.615475
6579 23:07:28.615540 [DATLAT]
6580 23:07:28.618929 Freq=400, CH0 RK1
6581 23:07:28.619013
6582 23:07:28.619077 DATLAT Default: 0xe
6583 23:07:28.622224 0, 0xFFFF, sum = 0
6584 23:07:28.622308 1, 0xFFFF, sum = 0
6585 23:07:28.625415 2, 0xFFFF, sum = 0
6586 23:07:28.625562 3, 0xFFFF, sum = 0
6587 23:07:28.628599 4, 0xFFFF, sum = 0
6588 23:07:28.628683 5, 0xFFFF, sum = 0
6589 23:07:28.632160 6, 0xFFFF, sum = 0
6590 23:07:28.632243 7, 0xFFFF, sum = 0
6591 23:07:28.635407 8, 0xFFFF, sum = 0
6592 23:07:28.638503 9, 0xFFFF, sum = 0
6593 23:07:28.638587 10, 0xFFFF, sum = 0
6594 23:07:28.641802 11, 0xFFFF, sum = 0
6595 23:07:28.641886 12, 0xFFFF, sum = 0
6596 23:07:28.645413 13, 0x0, sum = 1
6597 23:07:28.645553 14, 0x0, sum = 2
6598 23:07:28.648757 15, 0x0, sum = 3
6599 23:07:28.648841 16, 0x0, sum = 4
6600 23:07:28.648907 best_step = 14
6601 23:07:28.648968
6602 23:07:28.651797 ==
6603 23:07:28.655242 Dram Type= 6, Freq= 0, CH_0, rank 1
6604 23:07:28.658673 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6605 23:07:28.658756 ==
6606 23:07:28.658822 RX Vref Scan: 0
6607 23:07:28.658883
6608 23:07:28.661708 RX Vref 0 -> 0, step: 1
6609 23:07:28.661791
6610 23:07:28.665266 RX Delay -359 -> 252, step: 8
6611 23:07:28.672191 iDelay=217, Bit 0, Center -52 (-303 ~ 200) 504
6612 23:07:28.675523 iDelay=217, Bit 1, Center -44 (-295 ~ 208) 504
6613 23:07:28.678589 iDelay=217, Bit 2, Center -52 (-303 ~ 200) 504
6614 23:07:28.681912 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6615 23:07:28.688651 iDelay=217, Bit 4, Center -52 (-303 ~ 200) 504
6616 23:07:28.692109 iDelay=217, Bit 5, Center -60 (-311 ~ 192) 504
6617 23:07:28.695439 iDelay=217, Bit 6, Center -40 (-295 ~ 216) 512
6618 23:07:28.701749 iDelay=217, Bit 7, Center -36 (-287 ~ 216) 504
6619 23:07:28.705586 iDelay=217, Bit 8, Center -60 (-311 ~ 192) 504
6620 23:07:28.708438 iDelay=217, Bit 9, Center -68 (-319 ~ 184) 504
6621 23:07:28.712050 iDelay=217, Bit 10, Center -52 (-303 ~ 200) 504
6622 23:07:28.718731 iDelay=217, Bit 11, Center -60 (-311 ~ 192) 504
6623 23:07:28.722174 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
6624 23:07:28.725460 iDelay=217, Bit 13, Center -52 (-303 ~ 200) 504
6625 23:07:28.728656 iDelay=217, Bit 14, Center -44 (-295 ~ 208) 504
6626 23:07:28.735088 iDelay=217, Bit 15, Center -48 (-303 ~ 208) 512
6627 23:07:28.735171 ==
6628 23:07:28.738438 Dram Type= 6, Freq= 0, CH_0, rank 1
6629 23:07:28.741676 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6630 23:07:28.741759 ==
6631 23:07:28.741824 DQS Delay:
6632 23:07:28.745056 DQS0 = 60, DQS1 = 68
6633 23:07:28.745169 DQM Delay:
6634 23:07:28.748281 DQM0 = 11, DQM1 = 14
6635 23:07:28.748384 DQ Delay:
6636 23:07:28.751460 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6637 23:07:28.754655 DQ4 =8, DQ5 =0, DQ6 =20, DQ7 =24
6638 23:07:28.758410 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6639 23:07:28.761652 DQ12 =20, DQ13 =16, DQ14 =24, DQ15 =20
6640 23:07:28.761725
6641 23:07:28.761787
6642 23:07:28.767824 [DQSOSCAuto] RK1, (LSB)MR18= 0xc378, (MSB)MR19= 0xc0c, tDQSOscB0 = 394 ps tDQSOscB1 = 385 ps
6643 23:07:28.771252 CH0 RK1: MR19=C0C, MR18=C378
6644 23:07:28.777900 CH0_RK1: MR19=0xC0C, MR18=0xC378, DQSOSC=385, MR23=63, INC=398, DEC=265
6645 23:07:28.781135 [RxdqsGatingPostProcess] freq 400
6646 23:07:28.787854 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6647 23:07:28.791042 best DQS0 dly(2T, 0.5T) = (0, 10)
6648 23:07:28.791113 best DQS1 dly(2T, 0.5T) = (0, 10)
6649 23:07:28.794788 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6650 23:07:28.797662 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6651 23:07:28.801049 best DQS0 dly(2T, 0.5T) = (0, 10)
6652 23:07:28.804446 best DQS1 dly(2T, 0.5T) = (0, 10)
6653 23:07:28.807527 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6654 23:07:28.811212 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6655 23:07:28.814559 Pre-setting of DQS Precalculation
6656 23:07:28.820880 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6657 23:07:28.820964 ==
6658 23:07:28.824122 Dram Type= 6, Freq= 0, CH_1, rank 0
6659 23:07:28.827618 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6660 23:07:28.827702 ==
6661 23:07:28.834165 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6662 23:07:28.837511 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6663 23:07:28.840844 [CA 0] Center 36 (8~64) winsize 57
6664 23:07:28.843957 [CA 1] Center 36 (8~64) winsize 57
6665 23:07:28.847827 [CA 2] Center 36 (8~64) winsize 57
6666 23:07:28.850928 [CA 3] Center 36 (8~64) winsize 57
6667 23:07:28.854131 [CA 4] Center 36 (8~64) winsize 57
6668 23:07:28.857542 [CA 5] Center 36 (8~64) winsize 57
6669 23:07:28.857658
6670 23:07:28.860822 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6671 23:07:28.860905
6672 23:07:28.864175 [CATrainingPosCal] consider 1 rank data
6673 23:07:28.867436 u2DelayCellTimex100 = 270/100 ps
6674 23:07:28.870503 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6675 23:07:28.873815 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6676 23:07:28.880695 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6677 23:07:28.884006 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6678 23:07:28.887204 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6679 23:07:28.890361 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6680 23:07:28.890444
6681 23:07:28.893619 CA PerBit enable=1, Macro0, CA PI delay=36
6682 23:07:28.893701
6683 23:07:28.897385 [CBTSetCACLKResult] CA Dly = 36
6684 23:07:28.897468 CS Dly: 1 (0~32)
6685 23:07:28.900544 ==
6686 23:07:28.903549 Dram Type= 6, Freq= 0, CH_1, rank 1
6687 23:07:28.907158 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6688 23:07:28.907261 ==
6689 23:07:28.910479 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6690 23:07:28.917182 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6691 23:07:28.920159 [CA 0] Center 36 (8~64) winsize 57
6692 23:07:28.924088 [CA 1] Center 36 (8~64) winsize 57
6693 23:07:28.927082 [CA 2] Center 36 (8~64) winsize 57
6694 23:07:28.930101 [CA 3] Center 36 (8~64) winsize 57
6695 23:07:28.933739 [CA 4] Center 36 (8~64) winsize 57
6696 23:07:28.936881 [CA 5] Center 36 (8~64) winsize 57
6697 23:07:28.936975
6698 23:07:28.940100 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6699 23:07:28.940194
6700 23:07:28.943399 [CATrainingPosCal] consider 2 rank data
6701 23:07:28.947215 u2DelayCellTimex100 = 270/100 ps
6702 23:07:28.950428 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6703 23:07:28.953755 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6704 23:07:28.956849 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6705 23:07:28.960210 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6706 23:07:28.966671 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6707 23:07:28.970282 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6708 23:07:28.970360
6709 23:07:28.973636 CA PerBit enable=1, Macro0, CA PI delay=36
6710 23:07:28.973744
6711 23:07:28.976975 [CBTSetCACLKResult] CA Dly = 36
6712 23:07:28.977073 CS Dly: 1 (0~32)
6713 23:07:28.977172
6714 23:07:28.980188 ----->DramcWriteLeveling(PI) begin...
6715 23:07:28.980295 ==
6716 23:07:28.983339 Dram Type= 6, Freq= 0, CH_1, rank 0
6717 23:07:28.990077 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6718 23:07:28.990186 ==
6719 23:07:28.993255 Write leveling (Byte 0): 40 => 8
6720 23:07:28.993354 Write leveling (Byte 1): 40 => 8
6721 23:07:28.996505 DramcWriteLeveling(PI) end<-----
6722 23:07:28.996604
6723 23:07:28.996706 ==
6724 23:07:28.999666 Dram Type= 6, Freq= 0, CH_1, rank 0
6725 23:07:29.006504 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6726 23:07:29.006611 ==
6727 23:07:29.009541 [Gating] SW mode calibration
6728 23:07:29.016421 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6729 23:07:29.019671 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6730 23:07:29.026385 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6731 23:07:29.029592 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6732 23:07:29.033077 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6733 23:07:29.039358 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6734 23:07:29.043117 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6735 23:07:29.046308 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6736 23:07:29.052870 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6737 23:07:29.056147 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6738 23:07:29.059583 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6739 23:07:29.062695 Total UI for P1: 0, mck2ui 16
6740 23:07:29.066041 best dqsien dly found for B0: ( 0, 14, 24)
6741 23:07:29.069632 Total UI for P1: 0, mck2ui 16
6742 23:07:29.073083 best dqsien dly found for B1: ( 0, 14, 24)
6743 23:07:29.076129 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6744 23:07:29.079325 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6745 23:07:29.079422
6746 23:07:29.082915 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6747 23:07:29.089826 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6748 23:07:29.089916 [Gating] SW calibration Done
6749 23:07:29.089980 ==
6750 23:07:29.092680 Dram Type= 6, Freq= 0, CH_1, rank 0
6751 23:07:29.099388 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6752 23:07:29.099471 ==
6753 23:07:29.099536 RX Vref Scan: 0
6754 23:07:29.099596
6755 23:07:29.102719 RX Vref 0 -> 0, step: 1
6756 23:07:29.102813
6757 23:07:29.106116 RX Delay -410 -> 252, step: 16
6758 23:07:29.109458 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6759 23:07:29.112505 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6760 23:07:29.119383 iDelay=230, Bit 2, Center -51 (-314 ~ 213) 528
6761 23:07:29.122505 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6762 23:07:29.125973 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6763 23:07:29.129383 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6764 23:07:29.135942 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6765 23:07:29.138925 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6766 23:07:29.142279 iDelay=230, Bit 8, Center -67 (-330 ~ 197) 528
6767 23:07:29.145805 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6768 23:07:29.152121 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6769 23:07:29.155523 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6770 23:07:29.159203 iDelay=230, Bit 12, Center -35 (-298 ~ 229) 528
6771 23:07:29.165921 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6772 23:07:29.169010 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6773 23:07:29.172244 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6774 23:07:29.172339 ==
6775 23:07:29.175613 Dram Type= 6, Freq= 0, CH_1, rank 0
6776 23:07:29.178960 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6777 23:07:29.179057 ==
6778 23:07:29.182129 DQS Delay:
6779 23:07:29.182228 DQS0 = 51, DQS1 = 67
6780 23:07:29.185886 DQM Delay:
6781 23:07:29.185989 DQM0 = 12, DQM1 = 18
6782 23:07:29.188985 DQ Delay:
6783 23:07:29.189082 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6784 23:07:29.192276 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6785 23:07:29.195543 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6786 23:07:29.198683 DQ12 =32, DQ13 =24, DQ14 =24, DQ15 =24
6787 23:07:29.198791
6788 23:07:29.198885
6789 23:07:29.198974 ==
6790 23:07:29.202195 Dram Type= 6, Freq= 0, CH_1, rank 0
6791 23:07:29.208724 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6792 23:07:29.208825 ==
6793 23:07:29.208919
6794 23:07:29.209018
6795 23:07:29.209107 TX Vref Scan disable
6796 23:07:29.211981 == TX Byte 0 ==
6797 23:07:29.215193 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6798 23:07:29.218488 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6799 23:07:29.222032 == TX Byte 1 ==
6800 23:07:29.225456 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6801 23:07:29.228693 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6802 23:07:29.232041 ==
6803 23:07:29.232143 Dram Type= 6, Freq= 0, CH_1, rank 0
6804 23:07:29.238456 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6805 23:07:29.238562 ==
6806 23:07:29.238668
6807 23:07:29.238759
6808 23:07:29.241858 TX Vref Scan disable
6809 23:07:29.241968 == TX Byte 0 ==
6810 23:07:29.245081 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6811 23:07:29.251879 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6812 23:07:29.251994 == TX Byte 1 ==
6813 23:07:29.255313 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6814 23:07:29.261783 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6815 23:07:29.261886
6816 23:07:29.261988 [DATLAT]
6817 23:07:29.262082 Freq=400, CH1 RK0
6818 23:07:29.262169
6819 23:07:29.264953 DATLAT Default: 0xf
6820 23:07:29.265054 0, 0xFFFF, sum = 0
6821 23:07:29.268254 1, 0xFFFF, sum = 0
6822 23:07:29.271502 2, 0xFFFF, sum = 0
6823 23:07:29.271604 3, 0xFFFF, sum = 0
6824 23:07:29.274696 4, 0xFFFF, sum = 0
6825 23:07:29.274781 5, 0xFFFF, sum = 0
6826 23:07:29.277919 6, 0xFFFF, sum = 0
6827 23:07:29.278009 7, 0xFFFF, sum = 0
6828 23:07:29.281192 8, 0xFFFF, sum = 0
6829 23:07:29.281294 9, 0xFFFF, sum = 0
6830 23:07:29.284905 10, 0xFFFF, sum = 0
6831 23:07:29.285017 11, 0xFFFF, sum = 0
6832 23:07:29.288138 12, 0xFFFF, sum = 0
6833 23:07:29.288250 13, 0x0, sum = 1
6834 23:07:29.291321 14, 0x0, sum = 2
6835 23:07:29.291427 15, 0x0, sum = 3
6836 23:07:29.294739 16, 0x0, sum = 4
6837 23:07:29.294846 best_step = 14
6838 23:07:29.294940
6839 23:07:29.295030 ==
6840 23:07:29.297904 Dram Type= 6, Freq= 0, CH_1, rank 0
6841 23:07:29.304509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6842 23:07:29.304615 ==
6843 23:07:29.304710 RX Vref Scan: 1
6844 23:07:29.304810
6845 23:07:29.307630 RX Vref 0 -> 0, step: 1
6846 23:07:29.307733
6847 23:07:29.311355 RX Delay -375 -> 252, step: 8
6848 23:07:29.311459
6849 23:07:29.314340 Set Vref, RX VrefLevel [Byte0]: 60
6850 23:07:29.317659 [Byte1]: 50
6851 23:07:29.317768
6852 23:07:29.321257 Final RX Vref Byte 0 = 60 to rank0
6853 23:07:29.324468 Final RX Vref Byte 1 = 50 to rank0
6854 23:07:29.327722 Final RX Vref Byte 0 = 60 to rank1
6855 23:07:29.331011 Final RX Vref Byte 1 = 50 to rank1==
6856 23:07:29.334227 Dram Type= 6, Freq= 0, CH_1, rank 0
6857 23:07:29.337238 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6858 23:07:29.341023 ==
6859 23:07:29.341127 DQS Delay:
6860 23:07:29.341220 DQS0 = 56, DQS1 = 64
6861 23:07:29.344099 DQM Delay:
6862 23:07:29.344207 DQM0 = 12, DQM1 = 10
6863 23:07:29.347579 DQ Delay:
6864 23:07:29.350772 DQ0 =20, DQ1 =4, DQ2 =0, DQ3 =8
6865 23:07:29.350846 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6866 23:07:29.353922 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6867 23:07:29.357213 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =16
6868 23:07:29.357314
6869 23:07:29.357405
6870 23:07:29.367431 [DQSOSCAuto] RK0, (LSB)MR18= 0x596c, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 398 ps
6871 23:07:29.370625 CH1 RK0: MR19=C0C, MR18=596C
6872 23:07:29.376786 CH1_RK0: MR19=0xC0C, MR18=0x596C, DQSOSC=396, MR23=63, INC=376, DEC=251
6873 23:07:29.376871 ==
6874 23:07:29.380579 Dram Type= 6, Freq= 0, CH_1, rank 1
6875 23:07:29.383821 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6876 23:07:29.383905 ==
6877 23:07:29.387152 [Gating] SW mode calibration
6878 23:07:29.393641 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6879 23:07:29.399890 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6880 23:07:29.403725 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6881 23:07:29.406865 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6882 23:07:29.413342 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6883 23:07:29.416610 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6884 23:07:29.419828 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6885 23:07:29.426546 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6886 23:07:29.429932 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6887 23:07:29.433232 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6888 23:07:29.439637 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6889 23:07:29.439721 Total UI for P1: 0, mck2ui 16
6890 23:07:29.446161 best dqsien dly found for B0: ( 0, 14, 24)
6891 23:07:29.446255 Total UI for P1: 0, mck2ui 16
6892 23:07:29.449387 best dqsien dly found for B1: ( 0, 14, 24)
6893 23:07:29.456260 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6894 23:07:29.459727 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6895 23:07:29.459828
6896 23:07:29.462993 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6897 23:07:29.465982 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6898 23:07:29.469422 [Gating] SW calibration Done
6899 23:07:29.469566 ==
6900 23:07:29.472874 Dram Type= 6, Freq= 0, CH_1, rank 1
6901 23:07:29.475848 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6902 23:07:29.475946 ==
6903 23:07:29.479282 RX Vref Scan: 0
6904 23:07:29.479381
6905 23:07:29.479472 RX Vref 0 -> 0, step: 1
6906 23:07:29.479559
6907 23:07:29.482849 RX Delay -410 -> 252, step: 16
6908 23:07:29.489325 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6909 23:07:29.492743 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6910 23:07:29.495643 iDelay=230, Bit 2, Center -59 (-314 ~ 197) 512
6911 23:07:29.499382 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6912 23:07:29.505906 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6913 23:07:29.508882 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6914 23:07:29.512716 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6915 23:07:29.515517 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6916 23:07:29.522118 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6917 23:07:29.525398 iDelay=230, Bit 9, Center -51 (-314 ~ 213) 528
6918 23:07:29.529146 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6919 23:07:29.532396 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6920 23:07:29.538669 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6921 23:07:29.541884 iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528
6922 23:07:29.545354 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6923 23:07:29.551909 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6924 23:07:29.552011 ==
6925 23:07:29.555523 Dram Type= 6, Freq= 0, CH_1, rank 1
6926 23:07:29.558890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6927 23:07:29.558987 ==
6928 23:07:29.559073 DQS Delay:
6929 23:07:29.562142 DQS0 = 59, DQS1 = 59
6930 23:07:29.562212 DQM Delay:
6931 23:07:29.565295 DQM0 = 19, DQM1 = 13
6932 23:07:29.565392 DQ Delay:
6933 23:07:29.568402 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6934 23:07:29.571720 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6935 23:07:29.575324 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6936 23:07:29.578403 DQ12 =16, DQ13 =24, DQ14 =16, DQ15 =16
6937 23:07:29.578504
6938 23:07:29.578594
6939 23:07:29.578684 ==
6940 23:07:29.581666 Dram Type= 6, Freq= 0, CH_1, rank 1
6941 23:07:29.585371 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6942 23:07:29.585468 ==
6943 23:07:29.585569
6944 23:07:29.585657
6945 23:07:29.588384 TX Vref Scan disable
6946 23:07:29.588453 == TX Byte 0 ==
6947 23:07:29.595205 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6948 23:07:29.598330 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6949 23:07:29.598421 == TX Byte 1 ==
6950 23:07:29.604650 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6951 23:07:29.608028 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6952 23:07:29.608128 ==
6953 23:07:29.611467 Dram Type= 6, Freq= 0, CH_1, rank 1
6954 23:07:29.614856 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6955 23:07:29.614934 ==
6956 23:07:29.614998
6957 23:07:29.615057
6958 23:07:29.618364 TX Vref Scan disable
6959 23:07:29.621746 == TX Byte 0 ==
6960 23:07:29.624949 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6961 23:07:29.628241 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6962 23:07:29.631387 == TX Byte 1 ==
6963 23:07:29.634621 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6964 23:07:29.637903 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6965 23:07:29.638000
6966 23:07:29.638090 [DATLAT]
6967 23:07:29.641223 Freq=400, CH1 RK1
6968 23:07:29.641292
6969 23:07:29.641352 DATLAT Default: 0xe
6970 23:07:29.644790 0, 0xFFFF, sum = 0
6971 23:07:29.644867 1, 0xFFFF, sum = 0
6972 23:07:29.648157 2, 0xFFFF, sum = 0
6973 23:07:29.651380 3, 0xFFFF, sum = 0
6974 23:07:29.651482 4, 0xFFFF, sum = 0
6975 23:07:29.654630 5, 0xFFFF, sum = 0
6976 23:07:29.654705 6, 0xFFFF, sum = 0
6977 23:07:29.657989 7, 0xFFFF, sum = 0
6978 23:07:29.658088 8, 0xFFFF, sum = 0
6979 23:07:29.661397 9, 0xFFFF, sum = 0
6980 23:07:29.661531 10, 0xFFFF, sum = 0
6981 23:07:29.664334 11, 0xFFFF, sum = 0
6982 23:07:29.664405 12, 0xFFFF, sum = 0
6983 23:07:29.668243 13, 0x0, sum = 1
6984 23:07:29.668346 14, 0x0, sum = 2
6985 23:07:29.671286 15, 0x0, sum = 3
6986 23:07:29.671372 16, 0x0, sum = 4
6987 23:07:29.674445 best_step = 14
6988 23:07:29.674515
6989 23:07:29.674575 ==
6990 23:07:29.677620 Dram Type= 6, Freq= 0, CH_1, rank 1
6991 23:07:29.681052 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6992 23:07:29.681122 ==
6993 23:07:29.684580 RX Vref Scan: 0
6994 23:07:29.684650
6995 23:07:29.684715 RX Vref 0 -> 0, step: 1
6996 23:07:29.684773
6997 23:07:29.687560 RX Delay -359 -> 252, step: 8
6998 23:07:29.695443 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
6999 23:07:29.698802 iDelay=217, Bit 1, Center -52 (-303 ~ 200) 504
7000 23:07:29.701812 iDelay=217, Bit 2, Center -60 (-311 ~ 192) 504
7001 23:07:29.705257 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
7002 23:07:29.711662 iDelay=217, Bit 4, Center -48 (-303 ~ 208) 512
7003 23:07:29.715015 iDelay=217, Bit 5, Center -36 (-287 ~ 216) 504
7004 23:07:29.718316 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
7005 23:07:29.721643 iDelay=217, Bit 7, Center -48 (-303 ~ 208) 512
7006 23:07:29.728278 iDelay=217, Bit 8, Center -64 (-319 ~ 192) 512
7007 23:07:29.731653 iDelay=217, Bit 9, Center -60 (-319 ~ 200) 520
7008 23:07:29.735259 iDelay=217, Bit 10, Center -48 (-303 ~ 208) 512
7009 23:07:29.738200 iDelay=217, Bit 11, Center -60 (-311 ~ 192) 504
7010 23:07:29.745129 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
7011 23:07:29.748430 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
7012 23:07:29.751734 iDelay=217, Bit 14, Center -48 (-303 ~ 208) 512
7013 23:07:29.758290 iDelay=217, Bit 15, Center -48 (-303 ~ 208) 512
7014 23:07:29.758362 ==
7015 23:07:29.761598 Dram Type= 6, Freq= 0, CH_1, rank 1
7016 23:07:29.764754 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7017 23:07:29.764826 ==
7018 23:07:29.764895 DQS Delay:
7019 23:07:29.768417 DQS0 = 60, DQS1 = 64
7020 23:07:29.768486 DQM Delay:
7021 23:07:29.771540 DQM0 = 13, DQM1 = 11
7022 23:07:29.771624 DQ Delay:
7023 23:07:29.775076 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
7024 23:07:29.778166 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =12
7025 23:07:29.781935 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =4
7026 23:07:29.785198 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
7027 23:07:29.785281
7028 23:07:29.785345
7029 23:07:29.791667 [DQSOSCAuto] RK1, (LSB)MR18= 0x74a5, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 395 ps
7030 23:07:29.794652 CH1 RK1: MR19=C0C, MR18=74A5
7031 23:07:29.801357 CH1_RK1: MR19=0xC0C, MR18=0x74A5, DQSOSC=389, MR23=63, INC=390, DEC=260
7032 23:07:29.804750 [RxdqsGatingPostProcess] freq 400
7033 23:07:29.811446 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7034 23:07:29.814632 best DQS0 dly(2T, 0.5T) = (0, 10)
7035 23:07:29.814740 best DQS1 dly(2T, 0.5T) = (0, 10)
7036 23:07:29.817836 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7037 23:07:29.821430 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7038 23:07:29.824895 best DQS0 dly(2T, 0.5T) = (0, 10)
7039 23:07:29.828160 best DQS1 dly(2T, 0.5T) = (0, 10)
7040 23:07:29.831019 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7041 23:07:29.834342 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7042 23:07:29.838074 Pre-setting of DQS Precalculation
7043 23:07:29.844278 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7044 23:07:29.851449 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7045 23:07:29.858099 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7046 23:07:29.858182
7047 23:07:29.858247
7048 23:07:29.861337 [Calibration Summary] 800 Mbps
7049 23:07:29.861444 CH 0, Rank 0
7050 23:07:29.864742 SW Impedance : PASS
7051 23:07:29.867978 DUTY Scan : NO K
7052 23:07:29.868060 ZQ Calibration : PASS
7053 23:07:29.871189 Jitter Meter : NO K
7054 23:07:29.874219 CBT Training : PASS
7055 23:07:29.874302 Write leveling : PASS
7056 23:07:29.877431 RX DQS gating : PASS
7057 23:07:29.877541 RX DQ/DQS(RDDQC) : PASS
7058 23:07:29.881288 TX DQ/DQS : PASS
7059 23:07:29.884343 RX DATLAT : PASS
7060 23:07:29.884425 RX DQ/DQS(Engine): PASS
7061 23:07:29.887766 TX OE : NO K
7062 23:07:29.887848 All Pass.
7063 23:07:29.887913
7064 23:07:29.891049 CH 0, Rank 1
7065 23:07:29.891131 SW Impedance : PASS
7066 23:07:29.894350 DUTY Scan : NO K
7067 23:07:29.897720 ZQ Calibration : PASS
7068 23:07:29.897803 Jitter Meter : NO K
7069 23:07:29.900984 CBT Training : PASS
7070 23:07:29.904187 Write leveling : NO K
7071 23:07:29.904270 RX DQS gating : PASS
7072 23:07:29.907356 RX DQ/DQS(RDDQC) : PASS
7073 23:07:29.910701 TX DQ/DQS : PASS
7074 23:07:29.910785 RX DATLAT : PASS
7075 23:07:29.914392 RX DQ/DQS(Engine): PASS
7076 23:07:29.917443 TX OE : NO K
7077 23:07:29.917564 All Pass.
7078 23:07:29.917629
7079 23:07:29.917690 CH 1, Rank 0
7080 23:07:29.921167 SW Impedance : PASS
7081 23:07:29.924162 DUTY Scan : NO K
7082 23:07:29.924245 ZQ Calibration : PASS
7083 23:07:29.927317 Jitter Meter : NO K
7084 23:07:29.927396 CBT Training : PASS
7085 23:07:29.930596 Write leveling : PASS
7086 23:07:29.933854 RX DQS gating : PASS
7087 23:07:29.933937 RX DQ/DQS(RDDQC) : PASS
7088 23:07:29.937150 TX DQ/DQS : PASS
7089 23:07:29.940568 RX DATLAT : PASS
7090 23:07:29.940651 RX DQ/DQS(Engine): PASS
7091 23:07:29.944265 TX OE : NO K
7092 23:07:29.944347 All Pass.
7093 23:07:29.944412
7094 23:07:29.947342 CH 1, Rank 1
7095 23:07:29.947424 SW Impedance : PASS
7096 23:07:29.950499 DUTY Scan : NO K
7097 23:07:29.953668 ZQ Calibration : PASS
7098 23:07:29.953750 Jitter Meter : NO K
7099 23:07:29.957409 CBT Training : PASS
7100 23:07:29.960577 Write leveling : NO K
7101 23:07:29.960659 RX DQS gating : PASS
7102 23:07:29.963761 RX DQ/DQS(RDDQC) : PASS
7103 23:07:29.966886 TX DQ/DQS : PASS
7104 23:07:29.966969 RX DATLAT : PASS
7105 23:07:29.970287 RX DQ/DQS(Engine): PASS
7106 23:07:29.974020 TX OE : NO K
7107 23:07:29.974103 All Pass.
7108 23:07:29.974200
7109 23:07:29.974293 DramC Write-DBI off
7110 23:07:29.976976 PER_BANK_REFRESH: Hybrid Mode
7111 23:07:29.980286 TX_TRACKING: ON
7112 23:07:29.987240 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7113 23:07:29.990366 [FAST_K] Save calibration result to emmc
7114 23:07:29.997192 dramc_set_vcore_voltage set vcore to 725000
7115 23:07:29.997277 Read voltage for 1600, 0
7116 23:07:30.000165 Vio18 = 0
7117 23:07:30.000248 Vcore = 725000
7118 23:07:30.000313 Vdram = 0
7119 23:07:30.003343 Vddq = 0
7120 23:07:30.003425 Vmddr = 0
7121 23:07:30.006896 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7122 23:07:30.013288 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7123 23:07:30.016599 MEM_TYPE=3, freq_sel=13
7124 23:07:30.020437 sv_algorithm_assistance_LP4_3733
7125 23:07:30.023333 ============ PULL DRAM RESETB DOWN ============
7126 23:07:30.026635 ========== PULL DRAM RESETB DOWN end =========
7127 23:07:30.029860 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7128 23:07:30.033551 ===================================
7129 23:07:30.036799 LPDDR4 DRAM CONFIGURATION
7130 23:07:30.040029 ===================================
7131 23:07:30.043198 EX_ROW_EN[0] = 0x0
7132 23:07:30.043280 EX_ROW_EN[1] = 0x0
7133 23:07:30.046539 LP4Y_EN = 0x0
7134 23:07:30.046622 WORK_FSP = 0x1
7135 23:07:30.049765 WL = 0x5
7136 23:07:30.049847 RL = 0x5
7137 23:07:30.053337 BL = 0x2
7138 23:07:30.053420 RPST = 0x0
7139 23:07:30.056654 RD_PRE = 0x0
7140 23:07:30.060211 WR_PRE = 0x1
7141 23:07:30.060293 WR_PST = 0x1
7142 23:07:30.060358 DBI_WR = 0x0
7143 23:07:30.063364 DBI_RD = 0x0
7144 23:07:30.066772 OTF = 0x1
7145 23:07:30.069950 ===================================
7146 23:07:30.073264 ===================================
7147 23:07:30.073347 ANA top config
7148 23:07:30.076547 ===================================
7149 23:07:30.080162 DLL_ASYNC_EN = 0
7150 23:07:30.080245 ALL_SLAVE_EN = 0
7151 23:07:30.083309 NEW_RANK_MODE = 1
7152 23:07:30.086491 DLL_IDLE_MODE = 1
7153 23:07:30.089878 LP45_APHY_COMB_EN = 1
7154 23:07:30.093080 TX_ODT_DIS = 0
7155 23:07:30.093163 NEW_8X_MODE = 1
7156 23:07:30.096960 ===================================
7157 23:07:30.100223 ===================================
7158 23:07:30.103408 data_rate = 3200
7159 23:07:30.106582 CKR = 1
7160 23:07:30.109667 DQ_P2S_RATIO = 8
7161 23:07:30.113266 ===================================
7162 23:07:30.116408 CA_P2S_RATIO = 8
7163 23:07:30.119487 DQ_CA_OPEN = 0
7164 23:07:30.119573 DQ_SEMI_OPEN = 0
7165 23:07:30.123248 CA_SEMI_OPEN = 0
7166 23:07:30.126455 CA_FULL_RATE = 0
7167 23:07:30.129646 DQ_CKDIV4_EN = 0
7168 23:07:30.132860 CA_CKDIV4_EN = 0
7169 23:07:30.136459 CA_PREDIV_EN = 0
7170 23:07:30.136541 PH8_DLY = 12
7171 23:07:30.139465 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7172 23:07:30.143160 DQ_AAMCK_DIV = 4
7173 23:07:30.146167 CA_AAMCK_DIV = 4
7174 23:07:30.149637 CA_ADMCK_DIV = 4
7175 23:07:30.152628 DQ_TRACK_CA_EN = 0
7176 23:07:30.155916 CA_PICK = 1600
7177 23:07:30.155996 CA_MCKIO = 1600
7178 23:07:30.159232 MCKIO_SEMI = 0
7179 23:07:30.162807 PLL_FREQ = 3068
7180 23:07:30.165923 DQ_UI_PI_RATIO = 32
7181 23:07:30.169423 CA_UI_PI_RATIO = 0
7182 23:07:30.172781 ===================================
7183 23:07:30.175724 ===================================
7184 23:07:30.179122 memory_type:LPDDR4
7185 23:07:30.179197 GP_NUM : 10
7186 23:07:30.182478 SRAM_EN : 1
7187 23:07:30.182548 MD32_EN : 0
7188 23:07:30.186132 ===================================
7189 23:07:30.188890 [ANA_INIT] >>>>>>>>>>>>>>
7190 23:07:30.192529 <<<<<< [CONFIGURE PHASE]: ANA_TX
7191 23:07:30.195401 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7192 23:07:30.199155 ===================================
7193 23:07:30.202342 data_rate = 3200,PCW = 0X7600
7194 23:07:30.205617 ===================================
7195 23:07:30.209026 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7196 23:07:30.215331 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7197 23:07:30.218633 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7198 23:07:30.225345 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7199 23:07:30.229029 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7200 23:07:30.232344 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7201 23:07:30.232418 [ANA_INIT] flow start
7202 23:07:30.235570 [ANA_INIT] PLL >>>>>>>>
7203 23:07:30.238776 [ANA_INIT] PLL <<<<<<<<
7204 23:07:30.238850 [ANA_INIT] MIDPI >>>>>>>>
7205 23:07:30.241913 [ANA_INIT] MIDPI <<<<<<<<
7206 23:07:30.245692 [ANA_INIT] DLL >>>>>>>>
7207 23:07:30.245767 [ANA_INIT] DLL <<<<<<<<
7208 23:07:30.248422 [ANA_INIT] flow end
7209 23:07:30.252024 ============ LP4 DIFF to SE enter ============
7210 23:07:30.258342 ============ LP4 DIFF to SE exit ============
7211 23:07:30.258420 [ANA_INIT] <<<<<<<<<<<<<
7212 23:07:30.261658 [Flow] Enable top DCM control >>>>>
7213 23:07:30.265285 [Flow] Enable top DCM control <<<<<
7214 23:07:30.268516 Enable DLL master slave shuffle
7215 23:07:30.275241 ==============================================================
7216 23:07:30.275320 Gating Mode config
7217 23:07:30.281730 ==============================================================
7218 23:07:30.284744 Config description:
7219 23:07:30.294741 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7220 23:07:30.301463 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7221 23:07:30.304586 SELPH_MODE 0: By rank 1: By Phase
7222 23:07:30.311239 ==============================================================
7223 23:07:30.314941 GAT_TRACK_EN = 1
7224 23:07:30.318217 RX_GATING_MODE = 2
7225 23:07:30.318286 RX_GATING_TRACK_MODE = 2
7226 23:07:30.321553 SELPH_MODE = 1
7227 23:07:30.324639 PICG_EARLY_EN = 1
7228 23:07:30.327881 VALID_LAT_VALUE = 1
7229 23:07:30.334483 ==============================================================
7230 23:07:30.337904 Enter into Gating configuration >>>>
7231 23:07:30.341067 Exit from Gating configuration <<<<
7232 23:07:30.344609 Enter into DVFS_PRE_config >>>>>
7233 23:07:30.354514 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7234 23:07:30.357822 Exit from DVFS_PRE_config <<<<<
7235 23:07:30.361167 Enter into PICG configuration >>>>
7236 23:07:30.364215 Exit from PICG configuration <<<<
7237 23:07:30.367507 [RX_INPUT] configuration >>>>>
7238 23:07:30.370823 [RX_INPUT] configuration <<<<<
7239 23:07:30.374179 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7240 23:07:30.380810 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7241 23:07:30.387510 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7242 23:07:30.394253 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7243 23:07:30.397282 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7244 23:07:30.404259 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7245 23:07:30.407242 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7246 23:07:30.414274 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7247 23:07:30.417418 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7248 23:07:30.420795 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7249 23:07:30.423960 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7250 23:07:30.430566 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7251 23:07:30.433733 ===================================
7252 23:07:30.437001 LPDDR4 DRAM CONFIGURATION
7253 23:07:30.440683 ===================================
7254 23:07:30.440765 EX_ROW_EN[0] = 0x0
7255 23:07:30.443839 EX_ROW_EN[1] = 0x0
7256 23:07:30.443921 LP4Y_EN = 0x0
7257 23:07:30.447133 WORK_FSP = 0x1
7258 23:07:30.447241 WL = 0x5
7259 23:07:30.450438 RL = 0x5
7260 23:07:30.450543 BL = 0x2
7261 23:07:30.453897 RPST = 0x0
7262 23:07:30.453980 RD_PRE = 0x0
7263 23:07:30.456961 WR_PRE = 0x1
7264 23:07:30.457043 WR_PST = 0x1
7265 23:07:30.460676 DBI_WR = 0x0
7266 23:07:30.460758 DBI_RD = 0x0
7267 23:07:30.463776 OTF = 0x1
7268 23:07:30.466943 ===================================
7269 23:07:30.470219 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7270 23:07:30.473422 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7271 23:07:30.480517 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7272 23:07:30.483862 ===================================
7273 23:07:30.483945 LPDDR4 DRAM CONFIGURATION
7274 23:07:30.486814 ===================================
7275 23:07:30.490184 EX_ROW_EN[0] = 0x10
7276 23:07:30.493981 EX_ROW_EN[1] = 0x0
7277 23:07:30.494064 LP4Y_EN = 0x0
7278 23:07:30.497017 WORK_FSP = 0x1
7279 23:07:30.497102 WL = 0x5
7280 23:07:30.500109 RL = 0x5
7281 23:07:30.500192 BL = 0x2
7282 23:07:30.503617 RPST = 0x0
7283 23:07:30.503700 RD_PRE = 0x0
7284 23:07:30.506709 WR_PRE = 0x1
7285 23:07:30.506792 WR_PST = 0x1
7286 23:07:30.510101 DBI_WR = 0x0
7287 23:07:30.510184 DBI_RD = 0x0
7288 23:07:30.513615 OTF = 0x1
7289 23:07:30.516754 ===================================
7290 23:07:30.523137 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7291 23:07:30.523220 ==
7292 23:07:30.526986 Dram Type= 6, Freq= 0, CH_0, rank 0
7293 23:07:30.530115 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7294 23:07:30.530199 ==
7295 23:07:30.533368 [Duty_Offset_Calibration]
7296 23:07:30.533517 B0:2 B1:0 CA:3
7297 23:07:30.533612
7298 23:07:30.536540 [DutyScan_Calibration_Flow] k_type=0
7299 23:07:30.547368
7300 23:07:30.547476 ==CLK 0==
7301 23:07:30.550597 Final CLK duty delay cell = 0
7302 23:07:30.553747 [0] MAX Duty = 5031%(X100), DQS PI = 12
7303 23:07:30.557098 [0] MIN Duty = 4907%(X100), DQS PI = 4
7304 23:07:30.557207 [0] AVG Duty = 4969%(X100)
7305 23:07:30.560808
7306 23:07:30.564113 CH0 CLK Duty spec in!! Max-Min= 124%
7307 23:07:30.567053 [DutyScan_Calibration_Flow] ====Done====
7308 23:07:30.567135
7309 23:07:30.570451 [DutyScan_Calibration_Flow] k_type=1
7310 23:07:30.587318
7311 23:07:30.587401 ==DQS 0 ==
7312 23:07:30.590321 Final DQS duty delay cell = 0
7313 23:07:30.593981 [0] MAX Duty = 5125%(X100), DQS PI = 32
7314 23:07:30.597160 [0] MIN Duty = 4906%(X100), DQS PI = 48
7315 23:07:30.600339 [0] AVG Duty = 5015%(X100)
7316 23:07:30.600422
7317 23:07:30.600487 ==DQS 1 ==
7318 23:07:30.603815 Final DQS duty delay cell = 0
7319 23:07:30.607142 [0] MAX Duty = 5156%(X100), DQS PI = 32
7320 23:07:30.610266 [0] MIN Duty = 5062%(X100), DQS PI = 8
7321 23:07:30.613378 [0] AVG Duty = 5109%(X100)
7322 23:07:30.613515
7323 23:07:30.616974 CH0 DQS 0 Duty spec in!! Max-Min= 219%
7324 23:07:30.617057
7325 23:07:30.620255 CH0 DQS 1 Duty spec in!! Max-Min= 94%
7326 23:07:30.623382 [DutyScan_Calibration_Flow] ====Done====
7327 23:07:30.623465
7328 23:07:30.626607 [DutyScan_Calibration_Flow] k_type=3
7329 23:07:30.643956
7330 23:07:30.644038 ==DQM 0 ==
7331 23:07:30.647313 Final DQM duty delay cell = 0
7332 23:07:30.650512 [0] MAX Duty = 5156%(X100), DQS PI = 30
7333 23:07:30.654294 [0] MIN Duty = 4844%(X100), DQS PI = 50
7334 23:07:30.654366 [0] AVG Duty = 5000%(X100)
7335 23:07:30.657804
7336 23:07:30.657878 ==DQM 1 ==
7337 23:07:30.660861 Final DQM duty delay cell = 0
7338 23:07:30.664233 [0] MAX Duty = 4938%(X100), DQS PI = 60
7339 23:07:30.667337 [0] MIN Duty = 4813%(X100), DQS PI = 18
7340 23:07:30.667404 [0] AVG Duty = 4875%(X100)
7341 23:07:30.671040
7342 23:07:30.674267 CH0 DQM 0 Duty spec in!! Max-Min= 312%
7343 23:07:30.674341
7344 23:07:30.677154 CH0 DQM 1 Duty spec in!! Max-Min= 125%
7345 23:07:30.680751 [DutyScan_Calibration_Flow] ====Done====
7346 23:07:30.680823
7347 23:07:30.684222 [DutyScan_Calibration_Flow] k_type=2
7348 23:07:30.700462
7349 23:07:30.700542 ==DQ 0 ==
7350 23:07:30.703751 Final DQ duty delay cell = -4
7351 23:07:30.707117 [-4] MAX Duty = 5000%(X100), DQS PI = 14
7352 23:07:30.710239 [-4] MIN Duty = 4876%(X100), DQS PI = 0
7353 23:07:30.713552 [-4] AVG Duty = 4938%(X100)
7354 23:07:30.713632
7355 23:07:30.713694 ==DQ 1 ==
7356 23:07:30.716713 Final DQ duty delay cell = 0
7357 23:07:30.720212 [0] MAX Duty = 5156%(X100), DQS PI = 60
7358 23:07:30.723187 [0] MIN Duty = 5000%(X100), DQS PI = 18
7359 23:07:30.726900 [0] AVG Duty = 5078%(X100)
7360 23:07:30.726969
7361 23:07:30.730197 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7362 23:07:30.730269
7363 23:07:30.733123 CH0 DQ 1 Duty spec in!! Max-Min= 156%
7364 23:07:30.736568 [DutyScan_Calibration_Flow] ====Done====
7365 23:07:30.736643 ==
7366 23:07:30.740219 Dram Type= 6, Freq= 0, CH_1, rank 0
7367 23:07:30.743124 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7368 23:07:30.743194 ==
7369 23:07:30.746557 [Duty_Offset_Calibration]
7370 23:07:30.746640 B0:1 B1:-2 CA:1
7371 23:07:30.746704
7372 23:07:30.749719 [DutyScan_Calibration_Flow] k_type=0
7373 23:07:30.760987
7374 23:07:30.761062 ==CLK 0==
7375 23:07:30.764242 Final CLK duty delay cell = 0
7376 23:07:30.767326 [0] MAX Duty = 5031%(X100), DQS PI = 0
7377 23:07:30.770610 [0] MIN Duty = 4875%(X100), DQS PI = 26
7378 23:07:30.770679 [0] AVG Duty = 4953%(X100)
7379 23:07:30.773949
7380 23:07:30.777020 CH1 CLK Duty spec in!! Max-Min= 156%
7381 23:07:30.780740 [DutyScan_Calibration_Flow] ====Done====
7382 23:07:30.780818
7383 23:07:30.783958 [DutyScan_Calibration_Flow] k_type=1
7384 23:07:30.799590
7385 23:07:30.799670 ==DQS 0 ==
7386 23:07:30.803259 Final DQS duty delay cell = -4
7387 23:07:30.806051 [-4] MAX Duty = 4938%(X100), DQS PI = 56
7388 23:07:30.809645 [-4] MIN Duty = 4844%(X100), DQS PI = 14
7389 23:07:30.812968 [-4] AVG Duty = 4891%(X100)
7390 23:07:30.813049
7391 23:07:30.813113 ==DQS 1 ==
7392 23:07:30.816345 Final DQS duty delay cell = 0
7393 23:07:30.819504 [0] MAX Duty = 5124%(X100), DQS PI = 28
7394 23:07:30.822903 [0] MIN Duty = 4813%(X100), DQS PI = 58
7395 23:07:30.826419 [0] AVG Duty = 4968%(X100)
7396 23:07:30.826500
7397 23:07:30.829549 CH1 DQS 0 Duty spec in!! Max-Min= 94%
7398 23:07:30.829631
7399 23:07:30.832923 CH1 DQS 1 Duty spec in!! Max-Min= 311%
7400 23:07:30.836042 [DutyScan_Calibration_Flow] ====Done====
7401 23:07:30.836125
7402 23:07:30.839145 [DutyScan_Calibration_Flow] k_type=3
7403 23:07:30.856593
7404 23:07:30.856676 ==DQM 0 ==
7405 23:07:30.859907 Final DQM duty delay cell = 0
7406 23:07:30.863238 [0] MAX Duty = 5031%(X100), DQS PI = 60
7407 23:07:30.866727 [0] MIN Duty = 4813%(X100), DQS PI = 26
7408 23:07:30.870044 [0] AVG Duty = 4922%(X100)
7409 23:07:30.870127
7410 23:07:30.870191 ==DQM 1 ==
7411 23:07:30.873301 Final DQM duty delay cell = 0
7412 23:07:30.876600 [0] MAX Duty = 5062%(X100), DQS PI = 2
7413 23:07:30.879758 [0] MIN Duty = 4875%(X100), DQS PI = 34
7414 23:07:30.882944 [0] AVG Duty = 4968%(X100)
7415 23:07:30.883025
7416 23:07:30.886213 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7417 23:07:30.886295
7418 23:07:30.889928 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7419 23:07:30.893218 [DutyScan_Calibration_Flow] ====Done====
7420 23:07:30.893299
7421 23:07:30.896345 [DutyScan_Calibration_Flow] k_type=2
7422 23:07:30.913752
7423 23:07:30.913834 ==DQ 0 ==
7424 23:07:30.916962 Final DQ duty delay cell = 0
7425 23:07:30.919880 [0] MAX Duty = 5062%(X100), DQS PI = 0
7426 23:07:30.923128 [0] MIN Duty = 4938%(X100), DQS PI = 14
7427 23:07:30.923210 [0] AVG Duty = 5000%(X100)
7428 23:07:30.923275
7429 23:07:30.926666 ==DQ 1 ==
7430 23:07:30.930108 Final DQ duty delay cell = 0
7431 23:07:30.933532 [0] MAX Duty = 5156%(X100), DQS PI = 4
7432 23:07:30.936613 [0] MIN Duty = 4938%(X100), DQS PI = 56
7433 23:07:30.936726 [0] AVG Duty = 5047%(X100)
7434 23:07:30.936819
7435 23:07:30.939863 CH1 DQ 0 Duty spec in!! Max-Min= 124%
7436 23:07:30.943234
7437 23:07:30.946485 CH1 DQ 1 Duty spec in!! Max-Min= 218%
7438 23:07:30.949817 [DutyScan_Calibration_Flow] ====Done====
7439 23:07:30.953086 nWR fixed to 30
7440 23:07:30.953160 [ModeRegInit_LP4] CH0 RK0
7441 23:07:30.956343 [ModeRegInit_LP4] CH0 RK1
7442 23:07:30.959856 [ModeRegInit_LP4] CH1 RK0
7443 23:07:30.959931 [ModeRegInit_LP4] CH1 RK1
7444 23:07:30.963013 match AC timing 5
7445 23:07:30.966593 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7446 23:07:30.973099 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7447 23:07:30.976029 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7448 23:07:30.982883 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7449 23:07:30.986189 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7450 23:07:30.986290 [MiockJmeterHQA]
7451 23:07:30.986374
7452 23:07:30.989375 [DramcMiockJmeter] u1RxGatingPI = 0
7453 23:07:30.992634 0 : 4366, 4140
7454 23:07:30.992734 4 : 4366, 4139
7455 23:07:30.996349 8 : 4368, 4140
7456 23:07:30.996435 12 : 4371, 4143
7457 23:07:30.996498 16 : 4368, 4140
7458 23:07:30.999124 20 : 4257, 4029
7459 23:07:30.999229 24 : 4255, 4029
7460 23:07:31.002888 28 : 4257, 4029
7461 23:07:31.002970 32 : 4258, 4029
7462 23:07:31.006007 36 : 4365, 4138
7463 23:07:31.006081 40 : 4257, 4029
7464 23:07:31.009231 44 : 4258, 4030
7465 23:07:31.009336 48 : 4257, 4030
7466 23:07:31.009427 52 : 4260, 4032
7467 23:07:31.012601 56 : 4365, 4140
7468 23:07:31.012707 60 : 4249, 4027
7469 23:07:31.015861 64 : 4252, 4027
7470 23:07:31.015933 68 : 4252, 4029
7471 23:07:31.019131 72 : 4257, 4031
7472 23:07:31.019202 76 : 4253, 4029
7473 23:07:31.019264 80 : 4252, 4030
7474 23:07:31.022738 84 : 4252, 4030
7475 23:07:31.022819 88 : 4253, 4029
7476 23:07:31.025843 92 : 4257, 4031
7477 23:07:31.025915 96 : 4366, 4140
7478 23:07:31.029219 100 : 4252, 4029
7479 23:07:31.029318 104 : 4255, 3724
7480 23:07:31.032572 108 : 4368, 2
7481 23:07:31.032678 112 : 4254, 0
7482 23:07:31.032774 116 : 4253, 0
7483 23:07:31.035803 120 : 4252, 0
7484 23:07:31.035903 124 : 4252, 0
7485 23:07:31.039123 128 : 4253, 0
7486 23:07:31.039195 132 : 4255, 0
7487 23:07:31.039266 136 : 4257, 0
7488 23:07:31.042469 140 : 4250, 0
7489 23:07:31.042540 144 : 4253, 0
7490 23:07:31.042601 148 : 4257, 0
7491 23:07:31.045665 152 : 4363, 0
7492 23:07:31.045764 156 : 4253, 0
7493 23:07:31.049032 160 : 4255, 0
7494 23:07:31.049111 164 : 4253, 0
7495 23:07:31.049175 168 : 4252, 0
7496 23:07:31.052744 172 : 4255, 0
7497 23:07:31.052819 176 : 4257, 0
7498 23:07:31.055969 180 : 4252, 0
7499 23:07:31.056043 184 : 4255, 0
7500 23:07:31.056105 188 : 4257, 0
7501 23:07:31.059206 192 : 4363, 0
7502 23:07:31.059290 196 : 4253, 0
7503 23:07:31.062525 200 : 4365, 0
7504 23:07:31.062609 204 : 4252, 0
7505 23:07:31.062676 208 : 4366, 0
7506 23:07:31.065809 212 : 4363, 0
7507 23:07:31.065892 216 : 4253, 0
7508 23:07:31.065958 220 : 4365, 0
7509 23:07:31.069134 224 : 4250, 0
7510 23:07:31.069218 228 : 4252, 0
7511 23:07:31.072167 232 : 4252, 0
7512 23:07:31.072253 236 : 4252, 1185
7513 23:07:31.075961 240 : 4253, 4029
7514 23:07:31.076045 244 : 4363, 4140
7515 23:07:31.079155 248 : 4253, 4029
7516 23:07:31.079239 252 : 4255, 4029
7517 23:07:31.079306 256 : 4250, 4027
7518 23:07:31.082241 260 : 4364, 4140
7519 23:07:31.082325 264 : 4253, 4029
7520 23:07:31.085836 268 : 4363, 4138
7521 23:07:31.085920 272 : 4363, 4140
7522 23:07:31.088744 276 : 4252, 4030
7523 23:07:31.088828 280 : 4252, 4030
7524 23:07:31.092265 284 : 4255, 4030
7525 23:07:31.092348 288 : 4252, 4030
7526 23:07:31.095401 292 : 4360, 4137
7527 23:07:31.095485 296 : 4254, 4029
7528 23:07:31.098605 300 : 4255, 4029
7529 23:07:31.098689 304 : 4252, 4030
7530 23:07:31.102466 308 : 4249, 4027
7531 23:07:31.102550 312 : 4252, 4030
7532 23:07:31.102616 316 : 4257, 4032
7533 23:07:31.105668 320 : 4365, 4140
7534 23:07:31.105752 324 : 4363, 4140
7535 23:07:31.109038 328 : 4252, 4029
7536 23:07:31.109121 332 : 4254, 4029
7537 23:07:31.112244 336 : 4255, 4029
7538 23:07:31.112328 340 : 4250, 4027
7539 23:07:31.115377 344 : 4253, 4029
7540 23:07:31.115461 348 : 4363, 4140
7541 23:07:31.118963 352 : 4255, 4012
7542 23:07:31.119047 356 : 4366, 2798
7543 23:07:31.122238 360 : 4253, 1
7544 23:07:31.122322
7545 23:07:31.122387 MIOCK jitter meter ch=0
7546 23:07:31.122447
7547 23:07:31.125468 1T = (360-108) = 252 dly cells
7548 23:07:31.132354 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7549 23:07:31.132436 ==
7550 23:07:31.135599 Dram Type= 6, Freq= 0, CH_0, rank 0
7551 23:07:31.138711 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7552 23:07:31.138794 ==
7553 23:07:31.145113 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7554 23:07:31.148415 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7555 23:07:31.151841 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7556 23:07:31.158558 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7557 23:07:31.168052 [CA 0] Center 43 (13~74) winsize 62
7558 23:07:31.171721 [CA 1] Center 43 (13~74) winsize 62
7559 23:07:31.174576 [CA 2] Center 39 (10~68) winsize 59
7560 23:07:31.178164 [CA 3] Center 38 (9~68) winsize 60
7561 23:07:31.181387 [CA 4] Center 36 (7~66) winsize 60
7562 23:07:31.184790 [CA 5] Center 36 (7~66) winsize 60
7563 23:07:31.184865
7564 23:07:31.187866 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7565 23:07:31.187946
7566 23:07:31.191566 [CATrainingPosCal] consider 1 rank data
7567 23:07:31.194765 u2DelayCellTimex100 = 258/100 ps
7568 23:07:31.198176 CA0 delay=43 (13~74),Diff = 7 PI (26 cell)
7569 23:07:31.204745 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7570 23:07:31.207672 CA2 delay=39 (10~68),Diff = 3 PI (11 cell)
7571 23:07:31.211062 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7572 23:07:31.214804 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7573 23:07:31.218129 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7574 23:07:31.218198
7575 23:07:31.221416 CA PerBit enable=1, Macro0, CA PI delay=36
7576 23:07:31.221493
7577 23:07:31.224618 [CBTSetCACLKResult] CA Dly = 36
7578 23:07:31.227780 CS Dly: 11 (0~42)
7579 23:07:31.231439 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7580 23:07:31.234418 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7581 23:07:31.234488 ==
7582 23:07:31.237805 Dram Type= 6, Freq= 0, CH_0, rank 1
7583 23:07:31.244278 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7584 23:07:31.244353 ==
7585 23:07:31.247718 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7586 23:07:31.251036 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7587 23:07:31.258077 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7588 23:07:31.264332 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7589 23:07:31.271808 [CA 0] Center 43 (13~74) winsize 62
7590 23:07:31.275118 [CA 1] Center 43 (13~74) winsize 62
7591 23:07:31.278529 [CA 2] Center 38 (9~68) winsize 60
7592 23:07:31.281737 [CA 3] Center 39 (10~68) winsize 59
7593 23:07:31.284821 [CA 4] Center 36 (6~66) winsize 61
7594 23:07:31.288793 [CA 5] Center 36 (6~66) winsize 61
7595 23:07:31.288876
7596 23:07:31.291726 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7597 23:07:31.291827
7598 23:07:31.298540 [CATrainingPosCal] consider 2 rank data
7599 23:07:31.298623 u2DelayCellTimex100 = 258/100 ps
7600 23:07:31.304967 CA0 delay=43 (13~74),Diff = 7 PI (26 cell)
7601 23:07:31.308381 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7602 23:07:31.311383 CA2 delay=39 (10~68),Diff = 3 PI (11 cell)
7603 23:07:31.314911 CA3 delay=39 (10~68),Diff = 3 PI (11 cell)
7604 23:07:31.318258 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7605 23:07:31.321705 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7606 23:07:31.321788
7607 23:07:31.324789 CA PerBit enable=1, Macro0, CA PI delay=36
7608 23:07:31.324872
7609 23:07:31.328250 [CBTSetCACLKResult] CA Dly = 36
7610 23:07:31.331518 CS Dly: 11 (0~43)
7611 23:07:31.334654 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7612 23:07:31.338186 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7613 23:07:31.338269
7614 23:07:31.341634 ----->DramcWriteLeveling(PI) begin...
7615 23:07:31.341718 ==
7616 23:07:31.344830 Dram Type= 6, Freq= 0, CH_0, rank 0
7617 23:07:31.351296 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7618 23:07:31.351379 ==
7619 23:07:31.354515 Write leveling (Byte 0): 37 => 37
7620 23:07:31.357947 Write leveling (Byte 1): 28 => 28
7621 23:07:31.361186 DramcWriteLeveling(PI) end<-----
7622 23:07:31.361268
7623 23:07:31.361333 ==
7624 23:07:31.364309 Dram Type= 6, Freq= 0, CH_0, rank 0
7625 23:07:31.367602 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7626 23:07:31.367688 ==
7627 23:07:31.371227 [Gating] SW mode calibration
7628 23:07:31.377578 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7629 23:07:31.384101 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7630 23:07:31.387581 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7631 23:07:31.390889 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7632 23:07:31.394531 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7633 23:07:31.400715 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7634 23:07:31.404102 1 4 16 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (1 1)
7635 23:07:31.407354 1 4 20 | B1->B0 | 2424 3434 | 0 0 | (0 0) (0 0)
7636 23:07:31.414145 1 4 24 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
7637 23:07:31.417251 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7638 23:07:31.420909 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7639 23:07:31.427500 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7640 23:07:31.430783 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7641 23:07:31.433846 1 5 12 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
7642 23:07:31.440731 1 5 16 | B1->B0 | 3434 2c2c | 1 0 | (1 1) (1 0)
7643 23:07:31.443908 1 5 20 | B1->B0 | 3333 2323 | 1 0 | (1 1) (1 0)
7644 23:07:31.447271 1 5 24 | B1->B0 | 2b2b 2323 | 1 0 | (1 0) (0 0)
7645 23:07:31.453681 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7646 23:07:31.457136 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7647 23:07:31.460645 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7648 23:07:31.467154 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7649 23:07:31.470445 1 6 12 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7650 23:07:31.474128 1 6 16 | B1->B0 | 2323 3535 | 0 1 | (0 0) (0 0)
7651 23:07:31.480293 1 6 20 | B1->B0 | 2828 4646 | 0 0 | (0 0) (0 0)
7652 23:07:31.483514 1 6 24 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
7653 23:07:31.487279 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7654 23:07:31.493754 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7655 23:07:31.497204 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7656 23:07:31.500263 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7657 23:07:31.506763 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7658 23:07:31.510310 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7659 23:07:31.513464 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7660 23:07:31.519979 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7661 23:07:31.523393 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7662 23:07:31.527040 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7663 23:07:31.533378 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7664 23:07:31.536917 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7665 23:07:31.539933 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7666 23:07:31.546939 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7667 23:07:31.550095 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7668 23:07:31.553279 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7669 23:07:31.559931 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7670 23:07:31.563528 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7671 23:07:31.566343 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7672 23:07:31.573410 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7673 23:07:31.576133 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7674 23:07:31.579803 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7675 23:07:31.586103 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7676 23:07:31.586186 Total UI for P1: 0, mck2ui 16
7677 23:07:31.589557 best dqsien dly found for B0: ( 1, 9, 16)
7678 23:07:31.596705 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7679 23:07:31.599363 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7680 23:07:31.603077 Total UI for P1: 0, mck2ui 16
7681 23:07:31.606109 best dqsien dly found for B1: ( 1, 9, 24)
7682 23:07:31.609371 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
7683 23:07:31.612531 best DQS1 dly(MCK, UI, PI) = (1, 9, 24)
7684 23:07:31.612615
7685 23:07:31.615872 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
7686 23:07:31.622946 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 24)
7687 23:07:31.623030 [Gating] SW calibration Done
7688 23:07:31.623096 ==
7689 23:07:31.626109 Dram Type= 6, Freq= 0, CH_0, rank 0
7690 23:07:31.632966 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7691 23:07:31.633050 ==
7692 23:07:31.633116 RX Vref Scan: 0
7693 23:07:31.633177
7694 23:07:31.635782 RX Vref 0 -> 0, step: 1
7695 23:07:31.635865
7696 23:07:31.639498 RX Delay 0 -> 252, step: 8
7697 23:07:31.642521 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7698 23:07:31.646071 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
7699 23:07:31.649617 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7700 23:07:31.655873 iDelay=200, Bit 3, Center 123 (72 ~ 175) 104
7701 23:07:31.659132 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
7702 23:07:31.662261 iDelay=200, Bit 5, Center 111 (56 ~ 167) 112
7703 23:07:31.665464 iDelay=200, Bit 6, Center 135 (80 ~ 191) 112
7704 23:07:31.669272 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7705 23:07:31.675543 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
7706 23:07:31.678927 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7707 23:07:31.682159 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7708 23:07:31.685668 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
7709 23:07:31.688856 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
7710 23:07:31.695658 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7711 23:07:31.699067 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7712 23:07:31.702258 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7713 23:07:31.702342 ==
7714 23:07:31.705490 Dram Type= 6, Freq= 0, CH_0, rank 0
7715 23:07:31.708697 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7716 23:07:31.711840 ==
7717 23:07:31.711922 DQS Delay:
7718 23:07:31.711988 DQS0 = 0, DQS1 = 0
7719 23:07:31.715567 DQM Delay:
7720 23:07:31.715649 DQM0 = 127, DQM1 = 123
7721 23:07:31.718938 DQ Delay:
7722 23:07:31.722157 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =123
7723 23:07:31.725097 DQ4 =127, DQ5 =111, DQ6 =135, DQ7 =139
7724 23:07:31.728540 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =115
7725 23:07:31.731968 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131
7726 23:07:31.732051
7727 23:07:31.732116
7728 23:07:31.732176 ==
7729 23:07:31.735101 Dram Type= 6, Freq= 0, CH_0, rank 0
7730 23:07:31.738362 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7731 23:07:31.738445 ==
7732 23:07:31.738511
7733 23:07:31.738572
7734 23:07:31.742133 TX Vref Scan disable
7735 23:07:31.745319 == TX Byte 0 ==
7736 23:07:31.748426 Update DQ dly =994 (3 ,6, 34) DQ OEN =(3 ,3)
7737 23:07:31.751848 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
7738 23:07:31.755126 == TX Byte 1 ==
7739 23:07:31.758669 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7740 23:07:31.761816 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7741 23:07:31.761899 ==
7742 23:07:31.765515 Dram Type= 6, Freq= 0, CH_0, rank 0
7743 23:07:31.771870 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7744 23:07:31.771954 ==
7745 23:07:31.784417
7746 23:07:31.787676 TX Vref early break, caculate TX vref
7747 23:07:31.790851 TX Vref=16, minBit 8, minWin=21, winSum=365
7748 23:07:31.794241 TX Vref=18, minBit 8, minWin=22, winSum=379
7749 23:07:31.797927 TX Vref=20, minBit 8, minWin=21, winSum=382
7750 23:07:31.800682 TX Vref=22, minBit 8, minWin=23, winSum=395
7751 23:07:31.804297 TX Vref=24, minBit 8, minWin=23, winSum=403
7752 23:07:31.810777 TX Vref=26, minBit 9, minWin=24, winSum=411
7753 23:07:31.814320 TX Vref=28, minBit 10, minWin=24, winSum=412
7754 23:07:31.817453 TX Vref=30, minBit 8, minWin=23, winSum=402
7755 23:07:31.820677 TX Vref=32, minBit 8, minWin=23, winSum=395
7756 23:07:31.824086 TX Vref=34, minBit 8, minWin=21, winSum=385
7757 23:07:31.830348 [TxChooseVref] Worse bit 10, Min win 24, Win sum 412, Final Vref 28
7758 23:07:31.830431
7759 23:07:31.833929 Final TX Range 0 Vref 28
7760 23:07:31.834011
7761 23:07:31.834078 ==
7762 23:07:31.837220 Dram Type= 6, Freq= 0, CH_0, rank 0
7763 23:07:31.840386 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7764 23:07:31.840471 ==
7765 23:07:31.840571
7766 23:07:31.840667
7767 23:07:31.843850 TX Vref Scan disable
7768 23:07:31.850620 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7769 23:07:31.850704 == TX Byte 0 ==
7770 23:07:31.853495 u2DelayCellOfst[0]=11 cells (3 PI)
7771 23:07:31.857176 u2DelayCellOfst[1]=15 cells (4 PI)
7772 23:07:31.860245 u2DelayCellOfst[2]=11 cells (3 PI)
7773 23:07:31.863517 u2DelayCellOfst[3]=11 cells (3 PI)
7774 23:07:31.867261 u2DelayCellOfst[4]=7 cells (2 PI)
7775 23:07:31.870309 u2DelayCellOfst[5]=0 cells (0 PI)
7776 23:07:31.873456 u2DelayCellOfst[6]=15 cells (4 PI)
7777 23:07:31.876606 u2DelayCellOfst[7]=15 cells (4 PI)
7778 23:07:31.880592 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7779 23:07:31.883581 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
7780 23:07:31.886858 == TX Byte 1 ==
7781 23:07:31.890405 u2DelayCellOfst[8]=0 cells (0 PI)
7782 23:07:31.893376 u2DelayCellOfst[9]=3 cells (1 PI)
7783 23:07:31.893505 u2DelayCellOfst[10]=7 cells (2 PI)
7784 23:07:31.896688 u2DelayCellOfst[11]=7 cells (2 PI)
7785 23:07:31.900448 u2DelayCellOfst[12]=15 cells (4 PI)
7786 23:07:31.903197 u2DelayCellOfst[13]=11 cells (3 PI)
7787 23:07:31.906406 u2DelayCellOfst[14]=15 cells (4 PI)
7788 23:07:31.910280 u2DelayCellOfst[15]=11 cells (3 PI)
7789 23:07:31.916639 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7790 23:07:31.919633 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7791 23:07:31.919717 DramC Write-DBI on
7792 23:07:31.919783 ==
7793 23:07:31.923561 Dram Type= 6, Freq= 0, CH_0, rank 0
7794 23:07:31.929615 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7795 23:07:31.929698 ==
7796 23:07:31.929764
7797 23:07:31.929824
7798 23:07:31.929882 TX Vref Scan disable
7799 23:07:31.933863 == TX Byte 0 ==
7800 23:07:31.937636 Update DQM dly =738 (2 ,6, 34) DQM OEN =(3 ,3)
7801 23:07:31.940787 == TX Byte 1 ==
7802 23:07:31.943994 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7803 23:07:31.944078 DramC Write-DBI off
7804 23:07:31.947909
7805 23:07:31.947992 [DATLAT]
7806 23:07:31.948057 Freq=1600, CH0 RK0
7807 23:07:31.948118
7808 23:07:31.950865 DATLAT Default: 0xf
7809 23:07:31.950948 0, 0xFFFF, sum = 0
7810 23:07:31.954070 1, 0xFFFF, sum = 0
7811 23:07:31.954154 2, 0xFFFF, sum = 0
7812 23:07:31.957563 3, 0xFFFF, sum = 0
7813 23:07:31.960584 4, 0xFFFF, sum = 0
7814 23:07:31.960668 5, 0xFFFF, sum = 0
7815 23:07:31.963990 6, 0xFFFF, sum = 0
7816 23:07:31.964074 7, 0xFFFF, sum = 0
7817 23:07:31.966966 8, 0xFFFF, sum = 0
7818 23:07:31.967050 9, 0xFFFF, sum = 0
7819 23:07:31.970559 10, 0xFFFF, sum = 0
7820 23:07:31.970643 11, 0xFFFF, sum = 0
7821 23:07:31.974098 12, 0xFFFF, sum = 0
7822 23:07:31.974183 13, 0xEFFF, sum = 0
7823 23:07:31.977244 14, 0x0, sum = 1
7824 23:07:31.977356 15, 0x0, sum = 2
7825 23:07:31.980335 16, 0x0, sum = 3
7826 23:07:31.980419 17, 0x0, sum = 4
7827 23:07:31.984007 best_step = 15
7828 23:07:31.984089
7829 23:07:31.984154 ==
7830 23:07:31.987405 Dram Type= 6, Freq= 0, CH_0, rank 0
7831 23:07:31.990689 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7832 23:07:31.990773 ==
7833 23:07:31.994108 RX Vref Scan: 1
7834 23:07:31.994191
7835 23:07:31.994255 Set Vref Range= 24 -> 127
7836 23:07:31.994317
7837 23:07:31.996978 RX Vref 24 -> 127, step: 1
7838 23:07:31.997087
7839 23:07:32.000312 RX Delay 11 -> 252, step: 4
7840 23:07:32.000395
7841 23:07:32.003503 Set Vref, RX VrefLevel [Byte0]: 24
7842 23:07:32.006802 [Byte1]: 24
7843 23:07:32.006885
7844 23:07:32.009833 Set Vref, RX VrefLevel [Byte0]: 25
7845 23:07:32.013069 [Byte1]: 25
7846 23:07:32.016830
7847 23:07:32.016912 Set Vref, RX VrefLevel [Byte0]: 26
7848 23:07:32.019972 [Byte1]: 26
7849 23:07:32.024192
7850 23:07:32.024274 Set Vref, RX VrefLevel [Byte0]: 27
7851 23:07:32.027470 [Byte1]: 27
7852 23:07:32.032323
7853 23:07:32.032406 Set Vref, RX VrefLevel [Byte0]: 28
7854 23:07:32.035103 [Byte1]: 28
7855 23:07:32.039873
7856 23:07:32.039955 Set Vref, RX VrefLevel [Byte0]: 29
7857 23:07:32.043116 [Byte1]: 29
7858 23:07:32.047385
7859 23:07:32.047468 Set Vref, RX VrefLevel [Byte0]: 30
7860 23:07:32.050626 [Byte1]: 30
7861 23:07:32.054941
7862 23:07:32.055023 Set Vref, RX VrefLevel [Byte0]: 31
7863 23:07:32.058139 [Byte1]: 31
7864 23:07:32.062593
7865 23:07:32.062675 Set Vref, RX VrefLevel [Byte0]: 32
7866 23:07:32.065991 [Byte1]: 32
7867 23:07:32.070245
7868 23:07:32.070328 Set Vref, RX VrefLevel [Byte0]: 33
7869 23:07:32.073571 [Byte1]: 33
7870 23:07:32.077663
7871 23:07:32.077746 Set Vref, RX VrefLevel [Byte0]: 34
7872 23:07:32.081152 [Byte1]: 34
7873 23:07:32.085120
7874 23:07:32.085202 Set Vref, RX VrefLevel [Byte0]: 35
7875 23:07:32.088649 [Byte1]: 35
7876 23:07:32.093081
7877 23:07:32.093164 Set Vref, RX VrefLevel [Byte0]: 36
7878 23:07:32.096251 [Byte1]: 36
7879 23:07:32.100409
7880 23:07:32.100494 Set Vref, RX VrefLevel [Byte0]: 37
7881 23:07:32.103643 [Byte1]: 37
7882 23:07:32.107941
7883 23:07:32.108024 Set Vref, RX VrefLevel [Byte0]: 38
7884 23:07:32.111595 [Byte1]: 38
7885 23:07:32.115660
7886 23:07:32.115743 Set Vref, RX VrefLevel [Byte0]: 39
7887 23:07:32.119074 [Byte1]: 39
7888 23:07:32.123800
7889 23:07:32.123883 Set Vref, RX VrefLevel [Byte0]: 40
7890 23:07:32.126713 [Byte1]: 40
7891 23:07:32.130857
7892 23:07:32.130940 Set Vref, RX VrefLevel [Byte0]: 41
7893 23:07:32.134191 [Byte1]: 41
7894 23:07:32.138510
7895 23:07:32.138593 Set Vref, RX VrefLevel [Byte0]: 42
7896 23:07:32.141771 [Byte1]: 42
7897 23:07:32.146401
7898 23:07:32.146484 Set Vref, RX VrefLevel [Byte0]: 43
7899 23:07:32.149720 [Byte1]: 43
7900 23:07:32.153973
7901 23:07:32.154056 Set Vref, RX VrefLevel [Byte0]: 44
7902 23:07:32.157310 [Byte1]: 44
7903 23:07:32.161540
7904 23:07:32.161623 Set Vref, RX VrefLevel [Byte0]: 45
7905 23:07:32.164767 [Byte1]: 45
7906 23:07:32.169114
7907 23:07:32.169197 Set Vref, RX VrefLevel [Byte0]: 46
7908 23:07:32.172719 [Byte1]: 46
7909 23:07:32.176669
7910 23:07:32.176752 Set Vref, RX VrefLevel [Byte0]: 47
7911 23:07:32.179698 [Byte1]: 47
7912 23:07:32.184096
7913 23:07:32.184179 Set Vref, RX VrefLevel [Byte0]: 48
7914 23:07:32.187802 [Byte1]: 48
7915 23:07:32.192110
7916 23:07:32.192193 Set Vref, RX VrefLevel [Byte0]: 49
7917 23:07:32.195453 [Byte1]: 49
7918 23:07:32.199619
7919 23:07:32.199702 Set Vref, RX VrefLevel [Byte0]: 50
7920 23:07:32.203262 [Byte1]: 50
7921 23:07:32.207053
7922 23:07:32.207135 Set Vref, RX VrefLevel [Byte0]: 51
7923 23:07:32.210690 [Byte1]: 51
7924 23:07:32.215048
7925 23:07:32.215130 Set Vref, RX VrefLevel [Byte0]: 52
7926 23:07:32.218267 [Byte1]: 52
7927 23:07:32.222451
7928 23:07:32.222534 Set Vref, RX VrefLevel [Byte0]: 53
7929 23:07:32.226051 [Byte1]: 53
7930 23:07:32.230604
7931 23:07:32.230687 Set Vref, RX VrefLevel [Byte0]: 54
7932 23:07:32.233580 [Byte1]: 54
7933 23:07:32.237718
7934 23:07:32.237801 Set Vref, RX VrefLevel [Byte0]: 55
7935 23:07:32.240993 [Byte1]: 55
7936 23:07:32.245282
7937 23:07:32.245364 Set Vref, RX VrefLevel [Byte0]: 56
7938 23:07:32.248926 [Byte1]: 56
7939 23:07:32.252687
7940 23:07:32.252769 Set Vref, RX VrefLevel [Byte0]: 57
7941 23:07:32.256451 [Byte1]: 57
7942 23:07:32.260320
7943 23:07:32.260406 Set Vref, RX VrefLevel [Byte0]: 58
7944 23:07:32.263594 [Byte1]: 58
7945 23:07:32.267983
7946 23:07:32.268064 Set Vref, RX VrefLevel [Byte0]: 59
7947 23:07:32.271164 [Byte1]: 59
7948 23:07:32.275674
7949 23:07:32.275757 Set Vref, RX VrefLevel [Byte0]: 60
7950 23:07:32.278786 [Byte1]: 60
7951 23:07:32.283152
7952 23:07:32.283234 Set Vref, RX VrefLevel [Byte0]: 61
7953 23:07:32.286504 [Byte1]: 61
7954 23:07:32.290883
7955 23:07:32.290965 Set Vref, RX VrefLevel [Byte0]: 62
7956 23:07:32.294067 [Byte1]: 62
7957 23:07:32.298532
7958 23:07:32.298615 Set Vref, RX VrefLevel [Byte0]: 63
7959 23:07:32.301736 [Byte1]: 63
7960 23:07:32.305966
7961 23:07:32.306049 Set Vref, RX VrefLevel [Byte0]: 64
7962 23:07:32.309242 [Byte1]: 64
7963 23:07:32.313810
7964 23:07:32.313892 Set Vref, RX VrefLevel [Byte0]: 65
7965 23:07:32.317122 [Byte1]: 65
7966 23:07:32.321374
7967 23:07:32.321456 Set Vref, RX VrefLevel [Byte0]: 66
7968 23:07:32.324506 [Byte1]: 66
7969 23:07:32.328802
7970 23:07:32.328885 Set Vref, RX VrefLevel [Byte0]: 67
7971 23:07:32.332474 [Byte1]: 67
7972 23:07:32.336691
7973 23:07:32.336773 Set Vref, RX VrefLevel [Byte0]: 68
7974 23:07:32.339869 [Byte1]: 68
7975 23:07:32.344175
7976 23:07:32.344257 Set Vref, RX VrefLevel [Byte0]: 69
7977 23:07:32.347434 [Byte1]: 69
7978 23:07:32.351867
7979 23:07:32.351950 Set Vref, RX VrefLevel [Byte0]: 70
7980 23:07:32.354932 [Byte1]: 70
7981 23:07:32.359241
7982 23:07:32.359333 Set Vref, RX VrefLevel [Byte0]: 71
7983 23:07:32.362766 [Byte1]: 71
7984 23:07:32.367141
7985 23:07:32.367322 Set Vref, RX VrefLevel [Byte0]: 72
7986 23:07:32.370277 [Byte1]: 72
7987 23:07:32.374612
7988 23:07:32.374694 Set Vref, RX VrefLevel [Byte0]: 73
7989 23:07:32.377861 [Byte1]: 73
7990 23:07:32.382188
7991 23:07:32.382270 Set Vref, RX VrefLevel [Byte0]: 74
7992 23:07:32.385459 [Byte1]: 74
7993 23:07:32.389720
7994 23:07:32.389802 Set Vref, RX VrefLevel [Byte0]: 75
7995 23:07:32.393021 [Byte1]: 75
7996 23:07:32.397694
7997 23:07:32.397777 Set Vref, RX VrefLevel [Byte0]: 76
7998 23:07:32.400799 [Byte1]: 76
7999 23:07:32.405368
8000 23:07:32.405450 Set Vref, RX VrefLevel [Byte0]: 77
8001 23:07:32.408171 [Byte1]: 77
8002 23:07:32.412503
8003 23:07:32.412585 Final RX Vref Byte 0 = 64 to rank0
8004 23:07:32.416114 Final RX Vref Byte 1 = 61 to rank0
8005 23:07:32.419242 Final RX Vref Byte 0 = 64 to rank1
8006 23:07:32.422722 Final RX Vref Byte 1 = 61 to rank1==
8007 23:07:32.425973 Dram Type= 6, Freq= 0, CH_0, rank 0
8008 23:07:32.432695 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8009 23:07:32.432781 ==
8010 23:07:32.432847 DQS Delay:
8011 23:07:32.435788 DQS0 = 0, DQS1 = 0
8012 23:07:32.435870 DQM Delay:
8013 23:07:32.435935 DQM0 = 126, DQM1 = 119
8014 23:07:32.439068 DQ Delay:
8015 23:07:32.442318 DQ0 =126, DQ1 =128, DQ2 =126, DQ3 =122
8016 23:07:32.445663 DQ4 =126, DQ5 =114, DQ6 =134, DQ7 =138
8017 23:07:32.448949 DQ8 =112, DQ9 =106, DQ10 =120, DQ11 =114
8018 23:07:32.452470 DQ12 =126, DQ13 =124, DQ14 =130, DQ15 =126
8019 23:07:32.452553
8020 23:07:32.452618
8021 23:07:32.452678
8022 23:07:32.455854 [DramC_TX_OE_Calibration] TA2
8023 23:07:32.458912 Original DQ_B0 (3 6) =30, OEN = 27
8024 23:07:32.462263 Original DQ_B1 (3 6) =30, OEN = 27
8025 23:07:32.465485 24, 0x0, End_B0=24 End_B1=24
8026 23:07:32.465584 25, 0x0, End_B0=25 End_B1=25
8027 23:07:32.468986 26, 0x0, End_B0=26 End_B1=26
8028 23:07:32.471975 27, 0x0, End_B0=27 End_B1=27
8029 23:07:32.475386 28, 0x0, End_B0=28 End_B1=28
8030 23:07:32.478558 29, 0x0, End_B0=29 End_B1=29
8031 23:07:32.478643 30, 0x0, End_B0=30 End_B1=30
8032 23:07:32.481937 31, 0x4141, End_B0=30 End_B1=30
8033 23:07:32.485065 Byte0 end_step=30 best_step=27
8034 23:07:32.488366 Byte1 end_step=30 best_step=27
8035 23:07:32.491587 Byte0 TX OE(2T, 0.5T) = (3, 3)
8036 23:07:32.495315 Byte1 TX OE(2T, 0.5T) = (3, 3)
8037 23:07:32.495397
8038 23:07:32.495463
8039 23:07:32.501835 [DQSOSCAuto] RK0, (LSB)MR18= 0x1514, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 399 ps
8040 23:07:32.505200 CH0 RK0: MR19=303, MR18=1514
8041 23:07:32.511518 CH0_RK0: MR19=0x303, MR18=0x1514, DQSOSC=399, MR23=63, INC=23, DEC=15
8042 23:07:32.511602
8043 23:07:32.515217 ----->DramcWriteLeveling(PI) begin...
8044 23:07:32.515301 ==
8045 23:07:32.518445 Dram Type= 6, Freq= 0, CH_0, rank 1
8046 23:07:32.521613 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8047 23:07:32.521697 ==
8048 23:07:32.525144 Write leveling (Byte 0): 33 => 33
8049 23:07:32.528450 Write leveling (Byte 1): 29 => 29
8050 23:07:32.531704 DramcWriteLeveling(PI) end<-----
8051 23:07:32.531790
8052 23:07:32.531855 ==
8053 23:07:32.534734 Dram Type= 6, Freq= 0, CH_0, rank 1
8054 23:07:32.538375 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8055 23:07:32.541520 ==
8056 23:07:32.541603 [Gating] SW mode calibration
8057 23:07:32.551159 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8058 23:07:32.554797 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8059 23:07:32.558009 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8060 23:07:32.564312 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8061 23:07:32.567800 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8062 23:07:32.571438 1 4 12 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
8063 23:07:32.577917 1 4 16 | B1->B0 | 2828 3434 | 0 1 | (0 0) (1 1)
8064 23:07:32.581143 1 4 20 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
8065 23:07:32.584940 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8066 23:07:32.591200 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8067 23:07:32.594418 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8068 23:07:32.597637 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8069 23:07:32.604621 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
8070 23:07:32.607470 1 5 12 | B1->B0 | 3434 2727 | 1 0 | (1 1) (1 0)
8071 23:07:32.610848 1 5 16 | B1->B0 | 3232 2323 | 0 0 | (0 1) (0 0)
8072 23:07:32.617514 1 5 20 | B1->B0 | 2626 2323 | 0 0 | (1 0) (0 0)
8073 23:07:32.620747 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8074 23:07:32.624340 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8075 23:07:32.630756 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8076 23:07:32.633983 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8077 23:07:32.637172 1 6 8 | B1->B0 | 2323 2727 | 0 1 | (0 0) (0 0)
8078 23:07:32.643843 1 6 12 | B1->B0 | 2424 4444 | 0 0 | (0 0) (1 1)
8079 23:07:32.646890 1 6 16 | B1->B0 | 3636 4646 | 0 0 | (0 0) (0 0)
8080 23:07:32.650182 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8081 23:07:32.656877 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8082 23:07:32.660474 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8083 23:07:32.663774 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8084 23:07:32.670086 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8085 23:07:32.673344 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8086 23:07:32.676880 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8087 23:07:32.683264 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8088 23:07:32.686799 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8089 23:07:32.690089 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8090 23:07:32.696858 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8091 23:07:32.699946 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8092 23:07:32.703559 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8093 23:07:32.710133 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8094 23:07:32.713126 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8095 23:07:32.716351 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8096 23:07:32.723243 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8097 23:07:32.726455 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8098 23:07:32.729479 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8099 23:07:32.736383 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8100 23:07:32.739195 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8101 23:07:32.742800 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8102 23:07:32.749283 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8103 23:07:32.752511 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8104 23:07:32.756204 Total UI for P1: 0, mck2ui 16
8105 23:07:32.759120 best dqsien dly found for B0: ( 1, 9, 10)
8106 23:07:32.762460 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8107 23:07:32.766213 Total UI for P1: 0, mck2ui 16
8108 23:07:32.769440 best dqsien dly found for B1: ( 1, 9, 16)
8109 23:07:32.772695 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8110 23:07:32.776135 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8111 23:07:32.776218
8112 23:07:32.782548 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8113 23:07:32.785681 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8114 23:07:32.785764 [Gating] SW calibration Done
8115 23:07:32.789248 ==
8116 23:07:32.792437 Dram Type= 6, Freq= 0, CH_0, rank 1
8117 23:07:32.795754 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8118 23:07:32.795837 ==
8119 23:07:32.795903 RX Vref Scan: 0
8120 23:07:32.795963
8121 23:07:32.798872 RX Vref 0 -> 0, step: 1
8122 23:07:32.798955
8123 23:07:32.802267 RX Delay 0 -> 252, step: 8
8124 23:07:32.805934 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8125 23:07:32.809594 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8126 23:07:32.812106 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8127 23:07:32.819033 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
8128 23:07:32.822321 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8129 23:07:32.825551 iDelay=200, Bit 5, Center 111 (56 ~ 167) 112
8130 23:07:32.828683 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8131 23:07:32.831991 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8132 23:07:32.838523 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8133 23:07:32.841882 iDelay=200, Bit 9, Center 107 (48 ~ 167) 120
8134 23:07:32.845085 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8135 23:07:32.848663 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8136 23:07:32.855156 iDelay=200, Bit 12, Center 127 (64 ~ 191) 128
8137 23:07:32.858412 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8138 23:07:32.862050 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8139 23:07:32.865091 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
8140 23:07:32.865174 ==
8141 23:07:32.868665 Dram Type= 6, Freq= 0, CH_0, rank 1
8142 23:07:32.875124 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8143 23:07:32.875208 ==
8144 23:07:32.875274 DQS Delay:
8145 23:07:32.875334 DQS0 = 0, DQS1 = 0
8146 23:07:32.878205 DQM Delay:
8147 23:07:32.878287 DQM0 = 127, DQM1 = 122
8148 23:07:32.882025 DQ Delay:
8149 23:07:32.885246 DQ0 =127, DQ1 =131, DQ2 =123, DQ3 =123
8150 23:07:32.888334 DQ4 =127, DQ5 =111, DQ6 =139, DQ7 =139
8151 23:07:32.891547 DQ8 =115, DQ9 =107, DQ10 =123, DQ11 =115
8152 23:07:32.894565 DQ12 =127, DQ13 =131, DQ14 =131, DQ15 =127
8153 23:07:32.894648
8154 23:07:32.894713
8155 23:07:32.894773 ==
8156 23:07:32.897952 Dram Type= 6, Freq= 0, CH_0, rank 1
8157 23:07:32.901645 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8158 23:07:32.904850 ==
8159 23:07:32.904932
8160 23:07:32.904996
8161 23:07:32.905056 TX Vref Scan disable
8162 23:07:32.908201 == TX Byte 0 ==
8163 23:07:32.911361 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8164 23:07:32.914699 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8165 23:07:32.917760 == TX Byte 1 ==
8166 23:07:32.921247 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8167 23:07:32.927742 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8168 23:07:32.927852 ==
8169 23:07:32.931167 Dram Type= 6, Freq= 0, CH_0, rank 1
8170 23:07:32.934315 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8171 23:07:32.934398 ==
8172 23:07:32.947962
8173 23:07:32.951451 TX Vref early break, caculate TX vref
8174 23:07:32.954773 TX Vref=16, minBit 0, minWin=22, winSum=367
8175 23:07:32.957904 TX Vref=18, minBit 9, minWin=22, winSum=374
8176 23:07:32.961240 TX Vref=20, minBit 0, minWin=22, winSum=381
8177 23:07:32.964437 TX Vref=22, minBit 0, minWin=24, winSum=392
8178 23:07:32.967595 TX Vref=24, minBit 0, minWin=25, winSum=403
8179 23:07:32.974577 TX Vref=26, minBit 0, minWin=25, winSum=407
8180 23:07:32.977533 TX Vref=28, minBit 0, minWin=24, winSum=405
8181 23:07:32.980903 TX Vref=30, minBit 0, minWin=25, winSum=408
8182 23:07:32.984277 TX Vref=32, minBit 3, minWin=24, winSum=401
8183 23:07:32.987551 TX Vref=34, minBit 8, minWin=23, winSum=392
8184 23:07:32.990703 TX Vref=36, minBit 8, minWin=22, winSum=383
8185 23:07:32.997664 [TxChooseVref] Worse bit 0, Min win 25, Win sum 408, Final Vref 30
8186 23:07:32.997748
8187 23:07:33.000868 Final TX Range 0 Vref 30
8188 23:07:33.000950
8189 23:07:33.001015 ==
8190 23:07:33.004142 Dram Type= 6, Freq= 0, CH_0, rank 1
8191 23:07:33.007264 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8192 23:07:33.007347 ==
8193 23:07:33.010627
8194 23:07:33.010709
8195 23:07:33.010774 TX Vref Scan disable
8196 23:07:33.017194 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8197 23:07:33.017277 == TX Byte 0 ==
8198 23:07:33.020953 u2DelayCellOfst[0]=18 cells (5 PI)
8199 23:07:33.024170 u2DelayCellOfst[1]=22 cells (6 PI)
8200 23:07:33.027522 u2DelayCellOfst[2]=15 cells (4 PI)
8201 23:07:33.030605 u2DelayCellOfst[3]=15 cells (4 PI)
8202 23:07:33.033847 u2DelayCellOfst[4]=11 cells (3 PI)
8203 23:07:33.037107 u2DelayCellOfst[5]=0 cells (0 PI)
8204 23:07:33.040336 u2DelayCellOfst[6]=22 cells (6 PI)
8205 23:07:33.043731 u2DelayCellOfst[7]=18 cells (5 PI)
8206 23:07:33.047307 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
8207 23:07:33.050562 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8208 23:07:33.053847 == TX Byte 1 ==
8209 23:07:33.057025 u2DelayCellOfst[8]=0 cells (0 PI)
8210 23:07:33.060281 u2DelayCellOfst[9]=0 cells (0 PI)
8211 23:07:33.063895 u2DelayCellOfst[10]=7 cells (2 PI)
8212 23:07:33.066961 u2DelayCellOfst[11]=3 cells (1 PI)
8213 23:07:33.070335 u2DelayCellOfst[12]=11 cells (3 PI)
8214 23:07:33.070418 u2DelayCellOfst[13]=11 cells (3 PI)
8215 23:07:33.073668 u2DelayCellOfst[14]=11 cells (3 PI)
8216 23:07:33.077099 u2DelayCellOfst[15]=7 cells (2 PI)
8217 23:07:33.083585 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8218 23:07:33.086919 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8219 23:07:33.087002 DramC Write-DBI on
8220 23:07:33.090227 ==
8221 23:07:33.093775 Dram Type= 6, Freq= 0, CH_0, rank 1
8222 23:07:33.096736 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8223 23:07:33.096819 ==
8224 23:07:33.096885
8225 23:07:33.096944
8226 23:07:33.100123 TX Vref Scan disable
8227 23:07:33.100206 == TX Byte 0 ==
8228 23:07:33.107216 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
8229 23:07:33.107300 == TX Byte 1 ==
8230 23:07:33.110473 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8231 23:07:33.113526 DramC Write-DBI off
8232 23:07:33.113609
8233 23:07:33.113674 [DATLAT]
8234 23:07:33.116845 Freq=1600, CH0 RK1
8235 23:07:33.116928
8236 23:07:33.116993 DATLAT Default: 0xf
8237 23:07:33.120153 0, 0xFFFF, sum = 0
8238 23:07:33.120237 1, 0xFFFF, sum = 0
8239 23:07:33.123324 2, 0xFFFF, sum = 0
8240 23:07:33.123408 3, 0xFFFF, sum = 0
8241 23:07:33.127150 4, 0xFFFF, sum = 0
8242 23:07:33.127235 5, 0xFFFF, sum = 0
8243 23:07:33.130252 6, 0xFFFF, sum = 0
8244 23:07:33.130336 7, 0xFFFF, sum = 0
8245 23:07:33.133616 8, 0xFFFF, sum = 0
8246 23:07:33.133700 9, 0xFFFF, sum = 0
8247 23:07:33.136690 10, 0xFFFF, sum = 0
8248 23:07:33.140010 11, 0xFFFF, sum = 0
8249 23:07:33.140094 12, 0xFFFF, sum = 0
8250 23:07:33.143276 13, 0xCFFF, sum = 0
8251 23:07:33.143360 14, 0x0, sum = 1
8252 23:07:33.146786 15, 0x0, sum = 2
8253 23:07:33.146870 16, 0x0, sum = 3
8254 23:07:33.150045 17, 0x0, sum = 4
8255 23:07:33.150129 best_step = 15
8256 23:07:33.150194
8257 23:07:33.150254 ==
8258 23:07:33.153270 Dram Type= 6, Freq= 0, CH_0, rank 1
8259 23:07:33.157111 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8260 23:07:33.157204 ==
8261 23:07:33.159740 RX Vref Scan: 0
8262 23:07:33.159823
8263 23:07:33.163574 RX Vref 0 -> 0, step: 1
8264 23:07:33.163657
8265 23:07:33.163721 RX Delay 3 -> 252, step: 4
8266 23:07:33.170557 iDelay=191, Bit 0, Center 124 (71 ~ 178) 108
8267 23:07:33.173352 iDelay=191, Bit 1, Center 126 (75 ~ 178) 104
8268 23:07:33.177175 iDelay=191, Bit 2, Center 120 (67 ~ 174) 108
8269 23:07:33.180152 iDelay=191, Bit 3, Center 122 (67 ~ 178) 112
8270 23:07:33.183500 iDelay=191, Bit 4, Center 124 (71 ~ 178) 108
8271 23:07:33.190200 iDelay=191, Bit 5, Center 112 (59 ~ 166) 108
8272 23:07:33.193456 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8273 23:07:33.196702 iDelay=191, Bit 7, Center 134 (79 ~ 190) 112
8274 23:07:33.200180 iDelay=191, Bit 8, Center 110 (55 ~ 166) 112
8275 23:07:33.203271 iDelay=191, Bit 9, Center 104 (47 ~ 162) 116
8276 23:07:33.210180 iDelay=191, Bit 10, Center 118 (63 ~ 174) 112
8277 23:07:33.213344 iDelay=191, Bit 11, Center 112 (55 ~ 170) 116
8278 23:07:33.216721 iDelay=191, Bit 12, Center 124 (67 ~ 182) 116
8279 23:07:33.220091 iDelay=191, Bit 13, Center 122 (67 ~ 178) 112
8280 23:07:33.226512 iDelay=191, Bit 14, Center 128 (71 ~ 186) 116
8281 23:07:33.229849 iDelay=191, Bit 15, Center 124 (67 ~ 182) 116
8282 23:07:33.229933 ==
8283 23:07:33.233147 Dram Type= 6, Freq= 0, CH_0, rank 1
8284 23:07:33.236445 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8285 23:07:33.236529 ==
8286 23:07:33.240173 DQS Delay:
8287 23:07:33.240255 DQS0 = 0, DQS1 = 0
8288 23:07:33.240320 DQM Delay:
8289 23:07:33.243468 DQM0 = 124, DQM1 = 117
8290 23:07:33.243550 DQ Delay:
8291 23:07:33.246586 DQ0 =124, DQ1 =126, DQ2 =120, DQ3 =122
8292 23:07:33.249804 DQ4 =124, DQ5 =112, DQ6 =134, DQ7 =134
8293 23:07:33.253317 DQ8 =110, DQ9 =104, DQ10 =118, DQ11 =112
8294 23:07:33.259784 DQ12 =124, DQ13 =122, DQ14 =128, DQ15 =124
8295 23:07:33.259867
8296 23:07:33.259932
8297 23:07:33.259992
8298 23:07:33.263051 [DramC_TX_OE_Calibration] TA2
8299 23:07:33.263169 Original DQ_B0 (3 6) =30, OEN = 27
8300 23:07:33.266521 Original DQ_B1 (3 6) =30, OEN = 27
8301 23:07:33.270038 24, 0x0, End_B0=24 End_B1=24
8302 23:07:33.272960 25, 0x0, End_B0=25 End_B1=25
8303 23:07:33.276370 26, 0x0, End_B0=26 End_B1=26
8304 23:07:33.279507 27, 0x0, End_B0=27 End_B1=27
8305 23:07:33.279591 28, 0x0, End_B0=28 End_B1=28
8306 23:07:33.283193 29, 0x0, End_B0=29 End_B1=29
8307 23:07:33.286155 30, 0x0, End_B0=30 End_B1=30
8308 23:07:33.289671 31, 0x4141, End_B0=30 End_B1=30
8309 23:07:33.292723 Byte0 end_step=30 best_step=27
8310 23:07:33.292805 Byte1 end_step=30 best_step=27
8311 23:07:33.295952 Byte0 TX OE(2T, 0.5T) = (3, 3)
8312 23:07:33.299377 Byte1 TX OE(2T, 0.5T) = (3, 3)
8313 23:07:33.299460
8314 23:07:33.299524
8315 23:07:33.309408 [DQSOSCAuto] RK1, (LSB)MR18= 0x2210, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 392 ps
8316 23:07:33.309534 CH0 RK1: MR19=303, MR18=2210
8317 23:07:33.315895 CH0_RK1: MR19=0x303, MR18=0x2210, DQSOSC=392, MR23=63, INC=24, DEC=16
8318 23:07:33.319150 [RxdqsGatingPostProcess] freq 1600
8319 23:07:33.326100 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8320 23:07:33.329126 best DQS0 dly(2T, 0.5T) = (1, 1)
8321 23:07:33.332714 best DQS1 dly(2T, 0.5T) = (1, 1)
8322 23:07:33.335929 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8323 23:07:33.339188 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8324 23:07:33.342543 best DQS0 dly(2T, 0.5T) = (1, 1)
8325 23:07:33.342625 best DQS1 dly(2T, 0.5T) = (1, 1)
8326 23:07:33.345724 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8327 23:07:33.349038 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8328 23:07:33.352239 Pre-setting of DQS Precalculation
8329 23:07:33.359273 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8330 23:07:33.359357 ==
8331 23:07:33.362347 Dram Type= 6, Freq= 0, CH_1, rank 0
8332 23:07:33.365725 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8333 23:07:33.365808 ==
8334 23:07:33.371952 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8335 23:07:33.375415 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8336 23:07:33.378886 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8337 23:07:33.385099 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8338 23:07:33.394521 [CA 0] Center 42 (13~71) winsize 59
8339 23:07:33.397586 [CA 1] Center 42 (12~72) winsize 61
8340 23:07:33.401379 [CA 2] Center 38 (9~67) winsize 59
8341 23:07:33.404544 [CA 3] Center 37 (8~67) winsize 60
8342 23:07:33.407606 [CA 4] Center 38 (9~67) winsize 59
8343 23:07:33.411156 [CA 5] Center 37 (8~66) winsize 59
8344 23:07:33.411238
8345 23:07:33.414439 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8346 23:07:33.414522
8347 23:07:33.417514 [CATrainingPosCal] consider 1 rank data
8348 23:07:33.420899 u2DelayCellTimex100 = 258/100 ps
8349 23:07:33.424534 CA0 delay=42 (13~71),Diff = 5 PI (18 cell)
8350 23:07:33.430831 CA1 delay=42 (12~72),Diff = 5 PI (18 cell)
8351 23:07:33.434312 CA2 delay=38 (9~67),Diff = 1 PI (3 cell)
8352 23:07:33.437426 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8353 23:07:33.440967 CA4 delay=38 (9~67),Diff = 1 PI (3 cell)
8354 23:07:33.444399 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8355 23:07:33.444482
8356 23:07:33.447578 CA PerBit enable=1, Macro0, CA PI delay=37
8357 23:07:33.447670
8358 23:07:33.450921 [CBTSetCACLKResult] CA Dly = 37
8359 23:07:33.454203 CS Dly: 9 (0~40)
8360 23:07:33.457442 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8361 23:07:33.460733 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8362 23:07:33.460830 ==
8363 23:07:33.464555 Dram Type= 6, Freq= 0, CH_1, rank 1
8364 23:07:33.467591 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8365 23:07:33.467673 ==
8366 23:07:33.473964 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8367 23:07:33.477210 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8368 23:07:33.484292 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8369 23:07:33.487414 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8370 23:07:33.497826 [CA 0] Center 41 (12~71) winsize 60
8371 23:07:33.500774 [CA 1] Center 42 (12~72) winsize 61
8372 23:07:33.504133 [CA 2] Center 38 (9~68) winsize 60
8373 23:07:33.507841 [CA 3] Center 37 (8~66) winsize 59
8374 23:07:33.511232 [CA 4] Center 38 (8~68) winsize 61
8375 23:07:33.514316 [CA 5] Center 37 (7~67) winsize 61
8376 23:07:33.514397
8377 23:07:33.517275 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8378 23:07:33.517365
8379 23:07:33.520672 [CATrainingPosCal] consider 2 rank data
8380 23:07:33.524293 u2DelayCellTimex100 = 258/100 ps
8381 23:07:33.527704 CA0 delay=42 (13~71),Diff = 5 PI (18 cell)
8382 23:07:33.534142 CA1 delay=42 (12~72),Diff = 5 PI (18 cell)
8383 23:07:33.537436 CA2 delay=38 (9~67),Diff = 1 PI (3 cell)
8384 23:07:33.540787 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8385 23:07:33.543778 CA4 delay=38 (9~67),Diff = 1 PI (3 cell)
8386 23:07:33.547198 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8387 23:07:33.547305
8388 23:07:33.550492 CA PerBit enable=1, Macro0, CA PI delay=37
8389 23:07:33.550591
8390 23:07:33.553837 [CBTSetCACLKResult] CA Dly = 37
8391 23:07:33.557173 CS Dly: 10 (0~43)
8392 23:07:33.560378 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8393 23:07:33.564226 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8394 23:07:33.564308
8395 23:07:33.567205 ----->DramcWriteLeveling(PI) begin...
8396 23:07:33.567289 ==
8397 23:07:33.570541 Dram Type= 6, Freq= 0, CH_1, rank 0
8398 23:07:33.577113 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8399 23:07:33.577196 ==
8400 23:07:33.580482 Write leveling (Byte 0): 25 => 25
8401 23:07:33.580565 Write leveling (Byte 1): 28 => 28
8402 23:07:33.583680 DramcWriteLeveling(PI) end<-----
8403 23:07:33.583762
8404 23:07:33.583827 ==
8405 23:07:33.586988 Dram Type= 6, Freq= 0, CH_1, rank 0
8406 23:07:33.593897 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8407 23:07:33.593980 ==
8408 23:07:33.597121 [Gating] SW mode calibration
8409 23:07:33.604073 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8410 23:07:33.607432 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8411 23:07:33.613471 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8412 23:07:33.616924 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8413 23:07:33.620620 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8414 23:07:33.627128 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8415 23:07:33.630534 1 4 16 | B1->B0 | 3434 3333 | 1 1 | (0 0) (0 0)
8416 23:07:33.633678 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8417 23:07:33.640421 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8418 23:07:33.643639 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8419 23:07:33.646799 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8420 23:07:33.653624 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8421 23:07:33.656952 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8422 23:07:33.660341 1 5 12 | B1->B0 | 3434 3434 | 0 0 | (0 0) (0 0)
8423 23:07:33.663500 1 5 16 | B1->B0 | 2727 2727 | 0 0 | (0 0) (1 0)
8424 23:07:33.670369 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8425 23:07:33.673637 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8426 23:07:33.676860 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8427 23:07:33.683749 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8428 23:07:33.686959 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8429 23:07:33.690098 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8430 23:07:33.696556 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8431 23:07:33.699948 1 6 16 | B1->B0 | 4545 4343 | 0 0 | (0 0) (0 0)
8432 23:07:33.703193 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8433 23:07:33.710275 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8434 23:07:33.713469 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8435 23:07:33.716913 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8436 23:07:33.723381 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8437 23:07:33.726800 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8438 23:07:33.729818 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8439 23:07:33.736574 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8440 23:07:33.739531 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8441 23:07:33.742830 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8442 23:07:33.749848 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8443 23:07:33.753142 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8444 23:07:33.756147 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8445 23:07:33.762697 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8446 23:07:33.766115 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8447 23:07:33.769349 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8448 23:07:33.776178 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8449 23:07:33.779435 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8450 23:07:33.782604 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8451 23:07:33.789001 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8452 23:07:33.792200 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8453 23:07:33.795803 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8454 23:07:33.802319 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8455 23:07:33.805653 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8456 23:07:33.808736 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8457 23:07:33.812177 Total UI for P1: 0, mck2ui 16
8458 23:07:33.815827 best dqsien dly found for B0: ( 1, 9, 16)
8459 23:07:33.819271 Total UI for P1: 0, mck2ui 16
8460 23:07:33.822555 best dqsien dly found for B1: ( 1, 9, 16)
8461 23:07:33.825833 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
8462 23:07:33.828984 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8463 23:07:33.829080
8464 23:07:33.835714 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
8465 23:07:33.838717 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8466 23:07:33.842557 [Gating] SW calibration Done
8467 23:07:33.842658 ==
8468 23:07:33.845355 Dram Type= 6, Freq= 0, CH_1, rank 0
8469 23:07:33.848696 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8470 23:07:33.848773 ==
8471 23:07:33.848849 RX Vref Scan: 0
8472 23:07:33.848940
8473 23:07:33.852066 RX Vref 0 -> 0, step: 1
8474 23:07:33.852166
8475 23:07:33.855252 RX Delay 0 -> 252, step: 8
8476 23:07:33.858519 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8477 23:07:33.861860 iDelay=200, Bit 1, Center 127 (64 ~ 191) 128
8478 23:07:33.868431 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8479 23:07:33.871724 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8480 23:07:33.875169 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8481 23:07:33.878421 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8482 23:07:33.881808 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8483 23:07:33.888245 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8484 23:07:33.891636 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8485 23:07:33.894719 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8486 23:07:33.898170 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8487 23:07:33.901577 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8488 23:07:33.907856 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8489 23:07:33.911146 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8490 23:07:33.914383 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8491 23:07:33.918118 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8492 23:07:33.918202 ==
8493 23:07:33.921318 Dram Type= 6, Freq= 0, CH_1, rank 0
8494 23:07:33.927938 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8495 23:07:33.928045 ==
8496 23:07:33.928136 DQS Delay:
8497 23:07:33.931115 DQS0 = 0, DQS1 = 0
8498 23:07:33.931217 DQM Delay:
8499 23:07:33.934316 DQM0 = 132, DQM1 = 126
8500 23:07:33.934420 DQ Delay:
8501 23:07:33.937447 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8502 23:07:33.941278 DQ4 =127, DQ5 =143, DQ6 =143, DQ7 =131
8503 23:07:33.944363 DQ8 =111, DQ9 =115, DQ10 =123, DQ11 =119
8504 23:07:33.947568 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8505 23:07:33.947664
8506 23:07:33.947764
8507 23:07:33.947852 ==
8508 23:07:33.950790 Dram Type= 6, Freq= 0, CH_1, rank 0
8509 23:07:33.957684 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8510 23:07:33.957762 ==
8511 23:07:33.957836
8512 23:07:33.957901
8513 23:07:33.957959 TX Vref Scan disable
8514 23:07:33.960944 == TX Byte 0 ==
8515 23:07:33.964262 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8516 23:07:33.970910 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8517 23:07:33.971020 == TX Byte 1 ==
8518 23:07:33.974205 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8519 23:07:33.980752 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8520 23:07:33.980833 ==
8521 23:07:33.984202 Dram Type= 6, Freq= 0, CH_1, rank 0
8522 23:07:33.987067 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8523 23:07:33.987165 ==
8524 23:07:34.000783
8525 23:07:34.004263 TX Vref early break, caculate TX vref
8526 23:07:34.007411 TX Vref=16, minBit 11, minWin=20, winSum=360
8527 23:07:34.010743 TX Vref=18, minBit 11, minWin=22, winSum=371
8528 23:07:34.014494 TX Vref=20, minBit 0, minWin=23, winSum=383
8529 23:07:34.017721 TX Vref=22, minBit 5, minWin=23, winSum=394
8530 23:07:34.020883 TX Vref=24, minBit 5, minWin=24, winSum=404
8531 23:07:34.027570 TX Vref=26, minBit 5, minWin=24, winSum=411
8532 23:07:34.030820 TX Vref=28, minBit 0, minWin=25, winSum=418
8533 23:07:34.034033 TX Vref=30, minBit 1, minWin=24, winSum=412
8534 23:07:34.037689 TX Vref=32, minBit 0, minWin=24, winSum=405
8535 23:07:34.040829 TX Vref=34, minBit 0, minWin=24, winSum=397
8536 23:07:34.044116 TX Vref=36, minBit 0, minWin=23, winSum=387
8537 23:07:34.050990 [TxChooseVref] Worse bit 0, Min win 25, Win sum 418, Final Vref 28
8538 23:07:34.051099
8539 23:07:34.054109 Final TX Range 0 Vref 28
8540 23:07:34.054196
8541 23:07:34.054258 ==
8542 23:07:34.057327 Dram Type= 6, Freq= 0, CH_1, rank 0
8543 23:07:34.060503 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8544 23:07:34.060600 ==
8545 23:07:34.060689
8546 23:07:34.063857
8547 23:07:34.063952 TX Vref Scan disable
8548 23:07:34.070196 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8549 23:07:34.070272 == TX Byte 0 ==
8550 23:07:34.073744 u2DelayCellOfst[0]=22 cells (6 PI)
8551 23:07:34.076806 u2DelayCellOfst[1]=18 cells (5 PI)
8552 23:07:34.080551 u2DelayCellOfst[2]=0 cells (0 PI)
8553 23:07:34.083891 u2DelayCellOfst[3]=7 cells (2 PI)
8554 23:07:34.086890 u2DelayCellOfst[4]=11 cells (3 PI)
8555 23:07:34.090251 u2DelayCellOfst[5]=26 cells (7 PI)
8556 23:07:34.093787 u2DelayCellOfst[6]=22 cells (6 PI)
8557 23:07:34.096812 u2DelayCellOfst[7]=7 cells (2 PI)
8558 23:07:34.099873 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8559 23:07:34.103491 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8560 23:07:34.106945 == TX Byte 1 ==
8561 23:07:34.110221 u2DelayCellOfst[8]=0 cells (0 PI)
8562 23:07:34.113167 u2DelayCellOfst[9]=3 cells (1 PI)
8563 23:07:34.116841 u2DelayCellOfst[10]=15 cells (4 PI)
8564 23:07:34.116937 u2DelayCellOfst[11]=7 cells (2 PI)
8565 23:07:34.120240 u2DelayCellOfst[12]=15 cells (4 PI)
8566 23:07:34.123368 u2DelayCellOfst[13]=18 cells (5 PI)
8567 23:07:34.126629 u2DelayCellOfst[14]=18 cells (5 PI)
8568 23:07:34.129801 u2DelayCellOfst[15]=18 cells (5 PI)
8569 23:07:34.136321 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8570 23:07:34.140128 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8571 23:07:34.140226 DramC Write-DBI on
8572 23:07:34.143457 ==
8573 23:07:34.146650 Dram Type= 6, Freq= 0, CH_1, rank 0
8574 23:07:34.149825 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8575 23:07:34.149939 ==
8576 23:07:34.150027
8577 23:07:34.150088
8578 23:07:34.153389 TX Vref Scan disable
8579 23:07:34.153512 == TX Byte 0 ==
8580 23:07:34.159841 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8581 23:07:34.159940 == TX Byte 1 ==
8582 23:07:34.162992 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8583 23:07:34.166821 DramC Write-DBI off
8584 23:07:34.166919
8585 23:07:34.167018 [DATLAT]
8586 23:07:34.170134 Freq=1600, CH1 RK0
8587 23:07:34.170218
8588 23:07:34.170281 DATLAT Default: 0xf
8589 23:07:34.173297 0, 0xFFFF, sum = 0
8590 23:07:34.173401 1, 0xFFFF, sum = 0
8591 23:07:34.176590 2, 0xFFFF, sum = 0
8592 23:07:34.176670 3, 0xFFFF, sum = 0
8593 23:07:34.180114 4, 0xFFFF, sum = 0
8594 23:07:34.180214 5, 0xFFFF, sum = 0
8595 23:07:34.183283 6, 0xFFFF, sum = 0
8596 23:07:34.183381 7, 0xFFFF, sum = 0
8597 23:07:34.186494 8, 0xFFFF, sum = 0
8598 23:07:34.186564 9, 0xFFFF, sum = 0
8599 23:07:34.189800 10, 0xFFFF, sum = 0
8600 23:07:34.193388 11, 0xFFFF, sum = 0
8601 23:07:34.193514 12, 0xFFFF, sum = 0
8602 23:07:34.196353 13, 0x8FFF, sum = 0
8603 23:07:34.196451 14, 0x0, sum = 1
8604 23:07:34.199798 15, 0x0, sum = 2
8605 23:07:34.199897 16, 0x0, sum = 3
8606 23:07:34.202700 17, 0x0, sum = 4
8607 23:07:34.202771 best_step = 15
8608 23:07:34.202831
8609 23:07:34.202888 ==
8610 23:07:34.205971 Dram Type= 6, Freq= 0, CH_1, rank 0
8611 23:07:34.209240 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8612 23:07:34.209340 ==
8613 23:07:34.212952 RX Vref Scan: 1
8614 23:07:34.213022
8615 23:07:34.216306 Set Vref Range= 24 -> 127
8616 23:07:34.216376
8617 23:07:34.216437 RX Vref 24 -> 127, step: 1
8618 23:07:34.216495
8619 23:07:34.219486 RX Delay 11 -> 252, step: 4
8620 23:07:34.219555
8621 23:07:34.222549 Set Vref, RX VrefLevel [Byte0]: 24
8622 23:07:34.225861 [Byte1]: 24
8623 23:07:34.229327
8624 23:07:34.229434 Set Vref, RX VrefLevel [Byte0]: 25
8625 23:07:34.232772 [Byte1]: 25
8626 23:07:34.237158
8627 23:07:34.237241 Set Vref, RX VrefLevel [Byte0]: 26
8628 23:07:34.240520 [Byte1]: 26
8629 23:07:34.244805
8630 23:07:34.244883 Set Vref, RX VrefLevel [Byte0]: 27
8631 23:07:34.247906 [Byte1]: 27
8632 23:07:34.252182
8633 23:07:34.252288 Set Vref, RX VrefLevel [Byte0]: 28
8634 23:07:34.255303 [Byte1]: 28
8635 23:07:34.259726
8636 23:07:34.259839 Set Vref, RX VrefLevel [Byte0]: 29
8637 23:07:34.263039 [Byte1]: 29
8638 23:07:34.267232
8639 23:07:34.267306 Set Vref, RX VrefLevel [Byte0]: 30
8640 23:07:34.270550 [Byte1]: 30
8641 23:07:34.274843
8642 23:07:34.274918 Set Vref, RX VrefLevel [Byte0]: 31
8643 23:07:34.278597 [Byte1]: 31
8644 23:07:34.282620
8645 23:07:34.282694 Set Vref, RX VrefLevel [Byte0]: 32
8646 23:07:34.286233 [Byte1]: 32
8647 23:07:34.290506
8648 23:07:34.290608 Set Vref, RX VrefLevel [Byte0]: 33
8649 23:07:34.293897 [Byte1]: 33
8650 23:07:34.297968
8651 23:07:34.298044 Set Vref, RX VrefLevel [Byte0]: 34
8652 23:07:34.301411 [Byte1]: 34
8653 23:07:34.305607
8654 23:07:34.305681 Set Vref, RX VrefLevel [Byte0]: 35
8655 23:07:34.308806 [Byte1]: 35
8656 23:07:34.313187
8657 23:07:34.313293 Set Vref, RX VrefLevel [Byte0]: 36
8658 23:07:34.316483 [Byte1]: 36
8659 23:07:34.320723
8660 23:07:34.320818 Set Vref, RX VrefLevel [Byte0]: 37
8661 23:07:34.323950 [Byte1]: 37
8662 23:07:34.328689
8663 23:07:34.328794 Set Vref, RX VrefLevel [Byte0]: 38
8664 23:07:34.331581 [Byte1]: 38
8665 23:07:34.336326
8666 23:07:34.336430 Set Vref, RX VrefLevel [Byte0]: 39
8667 23:07:34.339307 [Byte1]: 39
8668 23:07:34.343694
8669 23:07:34.343797 Set Vref, RX VrefLevel [Byte0]: 40
8670 23:07:34.346738 [Byte1]: 40
8671 23:07:34.351432
8672 23:07:34.351534 Set Vref, RX VrefLevel [Byte0]: 41
8673 23:07:34.354467 [Byte1]: 41
8674 23:07:34.359001
8675 23:07:34.359102 Set Vref, RX VrefLevel [Byte0]: 42
8676 23:07:34.361902 [Byte1]: 42
8677 23:07:34.366227
8678 23:07:34.366298 Set Vref, RX VrefLevel [Byte0]: 43
8679 23:07:34.369890 [Byte1]: 43
8680 23:07:34.374075
8681 23:07:34.374175 Set Vref, RX VrefLevel [Byte0]: 44
8682 23:07:34.377284 [Byte1]: 44
8683 23:07:34.381746
8684 23:07:34.381818 Set Vref, RX VrefLevel [Byte0]: 45
8685 23:07:34.384921 [Byte1]: 45
8686 23:07:34.389271
8687 23:07:34.389369 Set Vref, RX VrefLevel [Byte0]: 46
8688 23:07:34.392694 [Byte1]: 46
8689 23:07:34.396962
8690 23:07:34.397059 Set Vref, RX VrefLevel [Byte0]: 47
8691 23:07:34.400135 [Byte1]: 47
8692 23:07:34.404558
8693 23:07:34.404655 Set Vref, RX VrefLevel [Byte0]: 48
8694 23:07:34.407714 [Byte1]: 48
8695 23:07:34.411965
8696 23:07:34.412061 Set Vref, RX VrefLevel [Byte0]: 49
8697 23:07:34.415478 [Byte1]: 49
8698 23:07:34.419581
8699 23:07:34.419678 Set Vref, RX VrefLevel [Byte0]: 50
8700 23:07:34.423142 [Byte1]: 50
8701 23:07:34.427502
8702 23:07:34.427599 Set Vref, RX VrefLevel [Byte0]: 51
8703 23:07:34.431033 [Byte1]: 51
8704 23:07:34.434751
8705 23:07:34.434836 Set Vref, RX VrefLevel [Byte0]: 52
8706 23:07:34.438098 [Byte1]: 52
8707 23:07:34.442444
8708 23:07:34.442540 Set Vref, RX VrefLevel [Byte0]: 53
8709 23:07:34.446012 [Byte1]: 53
8710 23:07:34.450131
8711 23:07:34.450227 Set Vref, RX VrefLevel [Byte0]: 54
8712 23:07:34.453346 [Byte1]: 54
8713 23:07:34.457923
8714 23:07:34.458011 Set Vref, RX VrefLevel [Byte0]: 55
8715 23:07:34.461099 [Byte1]: 55
8716 23:07:34.465295
8717 23:07:34.465401 Set Vref, RX VrefLevel [Byte0]: 56
8718 23:07:34.468538 [Byte1]: 56
8719 23:07:34.472846
8720 23:07:34.472944 Set Vref, RX VrefLevel [Byte0]: 57
8721 23:07:34.476149 [Byte1]: 57
8722 23:07:34.480549
8723 23:07:34.480652 Set Vref, RX VrefLevel [Byte0]: 58
8724 23:07:34.483785 [Byte1]: 58
8725 23:07:34.488024
8726 23:07:34.488129 Set Vref, RX VrefLevel [Byte0]: 59
8727 23:07:34.491275 [Byte1]: 59
8728 23:07:34.496165
8729 23:07:34.496270 Set Vref, RX VrefLevel [Byte0]: 60
8730 23:07:34.499070 [Byte1]: 60
8731 23:07:34.503263
8732 23:07:34.503333 Set Vref, RX VrefLevel [Byte0]: 61
8733 23:07:34.506704 [Byte1]: 61
8734 23:07:34.511101
8735 23:07:34.511202 Set Vref, RX VrefLevel [Byte0]: 62
8736 23:07:34.514180 [Byte1]: 62
8737 23:07:34.518433
8738 23:07:34.518503 Set Vref, RX VrefLevel [Byte0]: 63
8739 23:07:34.522245 [Byte1]: 63
8740 23:07:34.526335
8741 23:07:34.526405 Set Vref, RX VrefLevel [Byte0]: 64
8742 23:07:34.529598 [Byte1]: 64
8743 23:07:34.534478
8744 23:07:34.534550 Set Vref, RX VrefLevel [Byte0]: 65
8745 23:07:34.537230 [Byte1]: 65
8746 23:07:34.541786
8747 23:07:34.541856 Set Vref, RX VrefLevel [Byte0]: 66
8748 23:07:34.544923 [Byte1]: 66
8749 23:07:34.549117
8750 23:07:34.549220 Set Vref, RX VrefLevel [Byte0]: 67
8751 23:07:34.552625 [Byte1]: 67
8752 23:07:34.556759
8753 23:07:34.556831 Set Vref, RX VrefLevel [Byte0]: 68
8754 23:07:34.559877 [Byte1]: 68
8755 23:07:34.564299
8756 23:07:34.564371 Set Vref, RX VrefLevel [Byte0]: 69
8757 23:07:34.567575 [Byte1]: 69
8758 23:07:34.572003
8759 23:07:34.572100 Set Vref, RX VrefLevel [Byte0]: 70
8760 23:07:34.575089 [Byte1]: 70
8761 23:07:34.579621
8762 23:07:34.579728 Set Vref, RX VrefLevel [Byte0]: 71
8763 23:07:34.583016 [Byte1]: 71
8764 23:07:34.587393
8765 23:07:34.587506 Final RX Vref Byte 0 = 55 to rank0
8766 23:07:34.590570 Final RX Vref Byte 1 = 54 to rank0
8767 23:07:34.593789 Final RX Vref Byte 0 = 55 to rank1
8768 23:07:34.597181 Final RX Vref Byte 1 = 54 to rank1==
8769 23:07:34.600782 Dram Type= 6, Freq= 0, CH_1, rank 0
8770 23:07:34.607119 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8771 23:07:34.607227 ==
8772 23:07:34.607330 DQS Delay:
8773 23:07:34.607424 DQS0 = 0, DQS1 = 0
8774 23:07:34.610295 DQM Delay:
8775 23:07:34.610394 DQM0 = 130, DQM1 = 123
8776 23:07:34.613537 DQ Delay:
8777 23:07:34.617290 DQ0 =134, DQ1 =126, DQ2 =120, DQ3 =128
8778 23:07:34.620620 DQ4 =126, DQ5 =142, DQ6 =142, DQ7 =128
8779 23:07:34.623871 DQ8 =108, DQ9 =112, DQ10 =122, DQ11 =116
8780 23:07:34.627025 DQ12 =132, DQ13 =132, DQ14 =132, DQ15 =130
8781 23:07:34.627124
8782 23:07:34.627225
8783 23:07:34.627315
8784 23:07:34.630129 [DramC_TX_OE_Calibration] TA2
8785 23:07:34.633657 Original DQ_B0 (3 6) =30, OEN = 27
8786 23:07:34.636704 Original DQ_B1 (3 6) =30, OEN = 27
8787 23:07:34.639994 24, 0x0, End_B0=24 End_B1=24
8788 23:07:34.640104 25, 0x0, End_B0=25 End_B1=25
8789 23:07:34.643962 26, 0x0, End_B0=26 End_B1=26
8790 23:07:34.646661 27, 0x0, End_B0=27 End_B1=27
8791 23:07:34.650125 28, 0x0, End_B0=28 End_B1=28
8792 23:07:34.653274 29, 0x0, End_B0=29 End_B1=29
8793 23:07:34.653380 30, 0x0, End_B0=30 End_B1=30
8794 23:07:34.656896 31, 0x4141, End_B0=30 End_B1=30
8795 23:07:34.659857 Byte0 end_step=30 best_step=27
8796 23:07:34.663443 Byte1 end_step=30 best_step=27
8797 23:07:34.666708 Byte0 TX OE(2T, 0.5T) = (3, 3)
8798 23:07:34.669935 Byte1 TX OE(2T, 0.5T) = (3, 3)
8799 23:07:34.670036
8800 23:07:34.670132
8801 23:07:34.676309 [DQSOSCAuto] RK0, (LSB)MR18= 0xc10, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 403 ps
8802 23:07:34.680042 CH1 RK0: MR19=303, MR18=C10
8803 23:07:34.686356 CH1_RK0: MR19=0x303, MR18=0xC10, DQSOSC=401, MR23=63, INC=22, DEC=15
8804 23:07:34.686459
8805 23:07:34.689803 ----->DramcWriteLeveling(PI) begin...
8806 23:07:34.689909 ==
8807 23:07:34.693259 Dram Type= 6, Freq= 0, CH_1, rank 1
8808 23:07:34.696394 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8809 23:07:34.696505 ==
8810 23:07:34.699542 Write leveling (Byte 0): 23 => 23
8811 23:07:34.702826 Write leveling (Byte 1): 25 => 25
8812 23:07:34.706564 DramcWriteLeveling(PI) end<-----
8813 23:07:34.706662
8814 23:07:34.706762 ==
8815 23:07:34.709634 Dram Type= 6, Freq= 0, CH_1, rank 1
8816 23:07:34.713177 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8817 23:07:34.713265 ==
8818 23:07:34.716384 [Gating] SW mode calibration
8819 23:07:34.723107 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8820 23:07:34.729429 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8821 23:07:34.732802 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8822 23:07:34.739091 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8823 23:07:34.742778 1 4 8 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
8824 23:07:34.745858 1 4 12 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
8825 23:07:34.752790 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8826 23:07:34.756079 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8827 23:07:34.759107 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8828 23:07:34.765831 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8829 23:07:34.769011 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8830 23:07:34.772623 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8831 23:07:34.775861 1 5 8 | B1->B0 | 3333 2929 | 1 0 | (1 1) (1 0)
8832 23:07:34.782367 1 5 12 | B1->B0 | 2626 2323 | 0 0 | (1 0) (0 0)
8833 23:07:34.785317 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8834 23:07:34.792153 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8835 23:07:34.795828 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8836 23:07:34.798796 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8837 23:07:34.802221 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8838 23:07:34.808920 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8839 23:07:34.812121 1 6 8 | B1->B0 | 2d2c 4545 | 1 0 | (0 0) (0 0)
8840 23:07:34.815373 1 6 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8841 23:07:34.822019 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8842 23:07:34.825251 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8843 23:07:34.828488 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8844 23:07:34.835480 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8845 23:07:34.838634 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8846 23:07:34.841725 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8847 23:07:34.848305 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8848 23:07:34.851683 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8849 23:07:34.855508 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8850 23:07:34.861581 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8851 23:07:34.865183 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8852 23:07:34.868405 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8853 23:07:34.875055 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8854 23:07:34.878036 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8855 23:07:34.881780 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8856 23:07:34.888443 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8857 23:07:34.891636 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8858 23:07:34.895070 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8859 23:07:34.901805 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8860 23:07:34.904962 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8861 23:07:34.908401 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8862 23:07:34.914985 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8863 23:07:34.918247 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8864 23:07:34.921515 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8865 23:07:34.924828 Total UI for P1: 0, mck2ui 16
8866 23:07:34.928252 best dqsien dly found for B0: ( 1, 9, 8)
8867 23:07:34.934601 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8868 23:07:34.934703 Total UI for P1: 0, mck2ui 16
8869 23:07:34.941245 best dqsien dly found for B1: ( 1, 9, 10)
8870 23:07:34.944427 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8871 23:07:34.948036 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8872 23:07:34.948142
8873 23:07:34.951196 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8874 23:07:34.954878 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8875 23:07:34.958186 [Gating] SW calibration Done
8876 23:07:34.958258 ==
8877 23:07:34.961148 Dram Type= 6, Freq= 0, CH_1, rank 1
8878 23:07:34.964261 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8879 23:07:34.964358 ==
8880 23:07:34.967960 RX Vref Scan: 0
8881 23:07:34.968058
8882 23:07:34.968147 RX Vref 0 -> 0, step: 1
8883 23:07:34.968246
8884 23:07:34.971540 RX Delay 0 -> 252, step: 8
8885 23:07:34.974573 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8886 23:07:34.981176 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8887 23:07:34.984127 iDelay=200, Bit 2, Center 115 (56 ~ 175) 120
8888 23:07:34.987432 iDelay=200, Bit 3, Center 127 (64 ~ 191) 128
8889 23:07:34.991330 iDelay=200, Bit 4, Center 127 (64 ~ 191) 128
8890 23:07:34.994532 iDelay=200, Bit 5, Center 139 (80 ~ 199) 120
8891 23:07:35.000941 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8892 23:07:35.004024 iDelay=200, Bit 7, Center 127 (64 ~ 191) 128
8893 23:07:35.007484 iDelay=200, Bit 8, Center 111 (48 ~ 175) 128
8894 23:07:35.010704 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8895 23:07:35.014155 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8896 23:07:35.020680 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8897 23:07:35.023990 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8898 23:07:35.027132 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8899 23:07:35.030586 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8900 23:07:35.037296 iDelay=200, Bit 15, Center 135 (72 ~ 199) 128
8901 23:07:35.037373 ==
8902 23:07:35.040614 Dram Type= 6, Freq= 0, CH_1, rank 1
8903 23:07:35.043984 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8904 23:07:35.044084 ==
8905 23:07:35.044186 DQS Delay:
8906 23:07:35.047146 DQS0 = 0, DQS1 = 0
8907 23:07:35.047222 DQM Delay:
8908 23:07:35.050298 DQM0 = 129, DQM1 = 127
8909 23:07:35.050370 DQ Delay:
8910 23:07:35.053824 DQ0 =131, DQ1 =127, DQ2 =115, DQ3 =127
8911 23:07:35.056980 DQ4 =127, DQ5 =139, DQ6 =139, DQ7 =127
8912 23:07:35.060147 DQ8 =111, DQ9 =115, DQ10 =131, DQ11 =123
8913 23:07:35.063895 DQ12 =131, DQ13 =139, DQ14 =131, DQ15 =135
8914 23:07:35.063992
8915 23:07:35.064081
8916 23:07:35.064179 ==
8917 23:07:35.067115 Dram Type= 6, Freq= 0, CH_1, rank 1
8918 23:07:35.073561 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8919 23:07:35.073674 ==
8920 23:07:35.073773
8921 23:07:35.073862
8922 23:07:35.076939 TX Vref Scan disable
8923 23:07:35.077015 == TX Byte 0 ==
8924 23:07:35.080537 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8925 23:07:35.087225 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8926 23:07:35.087313 == TX Byte 1 ==
8927 23:07:35.090141 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8928 23:07:35.096765 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8929 23:07:35.096873 ==
8930 23:07:35.099875 Dram Type= 6, Freq= 0, CH_1, rank 1
8931 23:07:35.103237 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8932 23:07:35.103339 ==
8933 23:07:35.117439
8934 23:07:35.120570 TX Vref early break, caculate TX vref
8935 23:07:35.123996 TX Vref=16, minBit 5, minWin=22, winSum=385
8936 23:07:35.127248 TX Vref=18, minBit 0, minWin=23, winSum=392
8937 23:07:35.130696 TX Vref=20, minBit 0, minWin=23, winSum=400
8938 23:07:35.133625 TX Vref=22, minBit 0, minWin=23, winSum=407
8939 23:07:35.137323 TX Vref=24, minBit 5, minWin=24, winSum=415
8940 23:07:35.143989 TX Vref=26, minBit 0, minWin=25, winSum=422
8941 23:07:35.147147 TX Vref=28, minBit 5, minWin=24, winSum=424
8942 23:07:35.150365 TX Vref=30, minBit 0, minWin=24, winSum=416
8943 23:07:35.153985 TX Vref=32, minBit 5, minWin=23, winSum=407
8944 23:07:35.156998 TX Vref=34, minBit 1, minWin=23, winSum=402
8945 23:07:35.160606 TX Vref=36, minBit 5, minWin=22, winSum=394
8946 23:07:35.167123 [TxChooseVref] Worse bit 0, Min win 25, Win sum 422, Final Vref 26
8947 23:07:35.167205
8948 23:07:35.170434 Final TX Range 0 Vref 26
8949 23:07:35.170515
8950 23:07:35.170579 ==
8951 23:07:35.173599 Dram Type= 6, Freq= 0, CH_1, rank 1
8952 23:07:35.176769 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8953 23:07:35.176866 ==
8954 23:07:35.176931
8955 23:07:35.180396
8956 23:07:35.180476 TX Vref Scan disable
8957 23:07:35.187178 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8958 23:07:35.187259 == TX Byte 0 ==
8959 23:07:35.190084 u2DelayCellOfst[0]=18 cells (5 PI)
8960 23:07:35.193665 u2DelayCellOfst[1]=15 cells (4 PI)
8961 23:07:35.196664 u2DelayCellOfst[2]=0 cells (0 PI)
8962 23:07:35.200219 u2DelayCellOfst[3]=3 cells (1 PI)
8963 23:07:35.203693 u2DelayCellOfst[4]=7 cells (2 PI)
8964 23:07:35.206981 u2DelayCellOfst[5]=22 cells (6 PI)
8965 23:07:35.210321 u2DelayCellOfst[6]=18 cells (5 PI)
8966 23:07:35.213316 u2DelayCellOfst[7]=3 cells (1 PI)
8967 23:07:35.216698 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8968 23:07:35.220103 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8969 23:07:35.223596 == TX Byte 1 ==
8970 23:07:35.226794 u2DelayCellOfst[8]=0 cells (0 PI)
8971 23:07:35.229834 u2DelayCellOfst[9]=7 cells (2 PI)
8972 23:07:35.229916 u2DelayCellOfst[10]=15 cells (4 PI)
8973 23:07:35.233434 u2DelayCellOfst[11]=7 cells (2 PI)
8974 23:07:35.236734 u2DelayCellOfst[12]=18 cells (5 PI)
8975 23:07:35.240087 u2DelayCellOfst[13]=18 cells (5 PI)
8976 23:07:35.243362 u2DelayCellOfst[14]=18 cells (5 PI)
8977 23:07:35.246326 u2DelayCellOfst[15]=18 cells (5 PI)
8978 23:07:35.253234 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8979 23:07:35.256537 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8980 23:07:35.256618 DramC Write-DBI on
8981 23:07:35.256683 ==
8982 23:07:35.259693 Dram Type= 6, Freq= 0, CH_1, rank 1
8983 23:07:35.266298 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8984 23:07:35.266380 ==
8985 23:07:35.266444
8986 23:07:35.266503
8987 23:07:35.269597 TX Vref Scan disable
8988 23:07:35.269678 == TX Byte 0 ==
8989 23:07:35.276434 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8990 23:07:35.276515 == TX Byte 1 ==
8991 23:07:35.279640 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8992 23:07:35.282875 DramC Write-DBI off
8993 23:07:35.282955
8994 23:07:35.283020 [DATLAT]
8995 23:07:35.286169 Freq=1600, CH1 RK1
8996 23:07:35.286250
8997 23:07:35.286315 DATLAT Default: 0xf
8998 23:07:35.289438 0, 0xFFFF, sum = 0
8999 23:07:35.289559 1, 0xFFFF, sum = 0
9000 23:07:35.293069 2, 0xFFFF, sum = 0
9001 23:07:35.293151 3, 0xFFFF, sum = 0
9002 23:07:35.296165 4, 0xFFFF, sum = 0
9003 23:07:35.296248 5, 0xFFFF, sum = 0
9004 23:07:35.299483 6, 0xFFFF, sum = 0
9005 23:07:35.299565 7, 0xFFFF, sum = 0
9006 23:07:35.302700 8, 0xFFFF, sum = 0
9007 23:07:35.302783 9, 0xFFFF, sum = 0
9008 23:07:35.306302 10, 0xFFFF, sum = 0
9009 23:07:35.309468 11, 0xFFFF, sum = 0
9010 23:07:35.309559 12, 0xFFFF, sum = 0
9011 23:07:35.312723 13, 0x8FFF, sum = 0
9012 23:07:35.312806 14, 0x0, sum = 1
9013 23:07:35.315972 15, 0x0, sum = 2
9014 23:07:35.316054 16, 0x0, sum = 3
9015 23:07:35.316120 17, 0x0, sum = 4
9016 23:07:35.319199 best_step = 15
9017 23:07:35.319281
9018 23:07:35.319346 ==
9019 23:07:35.322410 Dram Type= 6, Freq= 0, CH_1, rank 1
9020 23:07:35.326150 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9021 23:07:35.326237 ==
9022 23:07:35.329319 RX Vref Scan: 0
9023 23:07:35.329400
9024 23:07:35.332557 RX Vref 0 -> 0, step: 1
9025 23:07:35.332639
9026 23:07:35.332703 RX Delay 3 -> 252, step: 4
9027 23:07:35.339333 iDelay=195, Bit 0, Center 132 (79 ~ 186) 108
9028 23:07:35.343110 iDelay=195, Bit 1, Center 126 (75 ~ 178) 104
9029 23:07:35.346119 iDelay=195, Bit 2, Center 116 (63 ~ 170) 108
9030 23:07:35.349263 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
9031 23:07:35.352806 iDelay=195, Bit 4, Center 124 (67 ~ 182) 116
9032 23:07:35.359298 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112
9033 23:07:35.362668 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
9034 23:07:35.365944 iDelay=195, Bit 7, Center 122 (67 ~ 178) 112
9035 23:07:35.369251 iDelay=195, Bit 8, Center 110 (51 ~ 170) 120
9036 23:07:35.372540 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
9037 23:07:35.379392 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
9038 23:07:35.382517 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
9039 23:07:35.386285 iDelay=195, Bit 12, Center 132 (79 ~ 186) 108
9040 23:07:35.388993 iDelay=195, Bit 13, Center 134 (79 ~ 190) 112
9041 23:07:35.395918 iDelay=195, Bit 14, Center 130 (75 ~ 186) 112
9042 23:07:35.399265 iDelay=195, Bit 15, Center 134 (79 ~ 190) 112
9043 23:07:35.399348 ==
9044 23:07:35.402352 Dram Type= 6, Freq= 0, CH_1, rank 1
9045 23:07:35.405471 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9046 23:07:35.405595 ==
9047 23:07:35.408681 DQS Delay:
9048 23:07:35.408789 DQS0 = 0, DQS1 = 0
9049 23:07:35.408882 DQM Delay:
9050 23:07:35.412368 DQM0 = 127, DQM1 = 125
9051 23:07:35.412450 DQ Delay:
9052 23:07:35.415831 DQ0 =132, DQ1 =126, DQ2 =116, DQ3 =124
9053 23:07:35.419018 DQ4 =124, DQ5 =138, DQ6 =138, DQ7 =122
9054 23:07:35.422322 DQ8 =110, DQ9 =112, DQ10 =128, DQ11 =120
9055 23:07:35.428701 DQ12 =132, DQ13 =134, DQ14 =130, DQ15 =134
9056 23:07:35.428782
9057 23:07:35.428846
9058 23:07:35.428905
9059 23:07:35.432387 [DramC_TX_OE_Calibration] TA2
9060 23:07:35.432468 Original DQ_B0 (3 6) =30, OEN = 27
9061 23:07:35.435659 Original DQ_B1 (3 6) =30, OEN = 27
9062 23:07:35.438772 24, 0x0, End_B0=24 End_B1=24
9063 23:07:35.442279 25, 0x0, End_B0=25 End_B1=25
9064 23:07:35.445425 26, 0x0, End_B0=26 End_B1=26
9065 23:07:35.448557 27, 0x0, End_B0=27 End_B1=27
9066 23:07:35.448640 28, 0x0, End_B0=28 End_B1=28
9067 23:07:35.452150 29, 0x0, End_B0=29 End_B1=29
9068 23:07:35.455211 30, 0x0, End_B0=30 End_B1=30
9069 23:07:35.458521 31, 0x4141, End_B0=30 End_B1=30
9070 23:07:35.462249 Byte0 end_step=30 best_step=27
9071 23:07:35.462336 Byte1 end_step=30 best_step=27
9072 23:07:35.465093 Byte0 TX OE(2T, 0.5T) = (3, 3)
9073 23:07:35.468877 Byte1 TX OE(2T, 0.5T) = (3, 3)
9074 23:07:35.468959
9075 23:07:35.469024
9076 23:07:35.478566 [DQSOSCAuto] RK1, (LSB)MR18= 0xf1b, (MSB)MR19= 0x303, tDQSOscB0 = 396 ps tDQSOscB1 = 402 ps
9077 23:07:35.478650 CH1 RK1: MR19=303, MR18=F1B
9078 23:07:35.485159 CH1_RK1: MR19=0x303, MR18=0xF1B, DQSOSC=396, MR23=63, INC=23, DEC=15
9079 23:07:35.488489 [RxdqsGatingPostProcess] freq 1600
9080 23:07:35.494889 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9081 23:07:35.498203 best DQS0 dly(2T, 0.5T) = (1, 1)
9082 23:07:35.501388 best DQS1 dly(2T, 0.5T) = (1, 1)
9083 23:07:35.504662 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9084 23:07:35.507965 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9085 23:07:35.508048 best DQS0 dly(2T, 0.5T) = (1, 1)
9086 23:07:35.511718 best DQS1 dly(2T, 0.5T) = (1, 1)
9087 23:07:35.514972 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9088 23:07:35.517966 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9089 23:07:35.521556 Pre-setting of DQS Precalculation
9090 23:07:35.528107 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9091 23:07:35.534542 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9092 23:07:35.541317 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9093 23:07:35.541426
9094 23:07:35.541519
9095 23:07:35.544538 [Calibration Summary] 3200 Mbps
9096 23:07:35.544621 CH 0, Rank 0
9097 23:07:35.547714 SW Impedance : PASS
9098 23:07:35.551399 DUTY Scan : NO K
9099 23:07:35.551482 ZQ Calibration : PASS
9100 23:07:35.554675 Jitter Meter : NO K
9101 23:07:35.557691 CBT Training : PASS
9102 23:07:35.557774 Write leveling : PASS
9103 23:07:35.561353 RX DQS gating : PASS
9104 23:07:35.564557 RX DQ/DQS(RDDQC) : PASS
9105 23:07:35.564638 TX DQ/DQS : PASS
9106 23:07:35.567719 RX DATLAT : PASS
9107 23:07:35.570788 RX DQ/DQS(Engine): PASS
9108 23:07:35.570870 TX OE : PASS
9109 23:07:35.574348 All Pass.
9110 23:07:35.574429
9111 23:07:35.574494 CH 0, Rank 1
9112 23:07:35.577738 SW Impedance : PASS
9113 23:07:35.577830 DUTY Scan : NO K
9114 23:07:35.580667 ZQ Calibration : PASS
9115 23:07:35.583926 Jitter Meter : NO K
9116 23:07:35.584008 CBT Training : PASS
9117 23:07:35.587528 Write leveling : PASS
9118 23:07:35.591060 RX DQS gating : PASS
9119 23:07:35.591142 RX DQ/DQS(RDDQC) : PASS
9120 23:07:35.594236 TX DQ/DQS : PASS
9121 23:07:35.594318 RX DATLAT : PASS
9122 23:07:35.597534 RX DQ/DQS(Engine): PASS
9123 23:07:35.600678 TX OE : PASS
9124 23:07:35.600760 All Pass.
9125 23:07:35.600826
9126 23:07:35.600886 CH 1, Rank 0
9127 23:07:35.604444 SW Impedance : PASS
9128 23:07:35.607191 DUTY Scan : NO K
9129 23:07:35.607274 ZQ Calibration : PASS
9130 23:07:35.610786 Jitter Meter : NO K
9131 23:07:35.614120 CBT Training : PASS
9132 23:07:35.614203 Write leveling : PASS
9133 23:07:35.617287 RX DQS gating : PASS
9134 23:07:35.620641 RX DQ/DQS(RDDQC) : PASS
9135 23:07:35.620723 TX DQ/DQS : PASS
9136 23:07:35.623821 RX DATLAT : PASS
9137 23:07:35.627122 RX DQ/DQS(Engine): PASS
9138 23:07:35.627205 TX OE : PASS
9139 23:07:35.630627 All Pass.
9140 23:07:35.630709
9141 23:07:35.630773 CH 1, Rank 1
9142 23:07:35.634026 SW Impedance : PASS
9143 23:07:35.634109 DUTY Scan : NO K
9144 23:07:35.636937 ZQ Calibration : PASS
9145 23:07:35.640242 Jitter Meter : NO K
9146 23:07:35.640324 CBT Training : PASS
9147 23:07:35.643713 Write leveling : PASS
9148 23:07:35.647213 RX DQS gating : PASS
9149 23:07:35.647296 RX DQ/DQS(RDDQC) : PASS
9150 23:07:35.650221 TX DQ/DQS : PASS
9151 23:07:35.650305 RX DATLAT : PASS
9152 23:07:35.653762 RX DQ/DQS(Engine): PASS
9153 23:07:35.656935 TX OE : PASS
9154 23:07:35.657018 All Pass.
9155 23:07:35.657083
9156 23:07:35.660166 DramC Write-DBI on
9157 23:07:35.660248 PER_BANK_REFRESH: Hybrid Mode
9158 23:07:35.663650 TX_TRACKING: ON
9159 23:07:35.673838 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9160 23:07:35.680107 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9161 23:07:35.687091 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9162 23:07:35.690019 [FAST_K] Save calibration result to emmc
9163 23:07:35.693652 sync common calibartion params.
9164 23:07:35.696599 sync cbt_mode0:1, 1:1
9165 23:07:35.696684 dram_init: ddr_geometry: 2
9166 23:07:35.700074 dram_init: ddr_geometry: 2
9167 23:07:35.703581 dram_init: ddr_geometry: 2
9168 23:07:35.706693 0:dram_rank_size:100000000
9169 23:07:35.706777 1:dram_rank_size:100000000
9170 23:07:35.713426 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9171 23:07:35.716672 DFS_SHUFFLE_HW_MODE: ON
9172 23:07:35.719970 dramc_set_vcore_voltage set vcore to 725000
9173 23:07:35.723174 Read voltage for 1600, 0
9174 23:07:35.723255 Vio18 = 0
9175 23:07:35.723320 Vcore = 725000
9176 23:07:35.726454 Vdram = 0
9177 23:07:35.726536 Vddq = 0
9178 23:07:35.726600 Vmddr = 0
9179 23:07:35.729821 switch to 3200 Mbps bootup
9180 23:07:35.729903 [DramcRunTimeConfig]
9181 23:07:35.732989 PHYPLL
9182 23:07:35.733069 DPM_CONTROL_AFTERK: ON
9183 23:07:35.736795 PER_BANK_REFRESH: ON
9184 23:07:35.740015 REFRESH_OVERHEAD_REDUCTION: ON
9185 23:07:35.740097 CMD_PICG_NEW_MODE: OFF
9186 23:07:35.743147 XRTWTW_NEW_MODE: ON
9187 23:07:35.743229 XRTRTR_NEW_MODE: ON
9188 23:07:35.746543 TX_TRACKING: ON
9189 23:07:35.746625 RDSEL_TRACKING: OFF
9190 23:07:35.750005 DQS Precalculation for DVFS: ON
9191 23:07:35.753236 RX_TRACKING: OFF
9192 23:07:35.753318 HW_GATING DBG: ON
9193 23:07:35.756308 ZQCS_ENABLE_LP4: ON
9194 23:07:35.756389 RX_PICG_NEW_MODE: ON
9195 23:07:35.759592 TX_PICG_NEW_MODE: ON
9196 23:07:35.759675 ENABLE_RX_DCM_DPHY: ON
9197 23:07:35.763082 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9198 23:07:35.766260 DUMMY_READ_FOR_TRACKING: OFF
9199 23:07:35.769816 !!! SPM_CONTROL_AFTERK: OFF
9200 23:07:35.772822 !!! SPM could not control APHY
9201 23:07:35.772904 IMPEDANCE_TRACKING: ON
9202 23:07:35.776148 TEMP_SENSOR: ON
9203 23:07:35.776230 HW_SAVE_FOR_SR: OFF
9204 23:07:35.779915 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9205 23:07:35.782993 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9206 23:07:35.786105 Read ODT Tracking: ON
9207 23:07:35.789755 Refresh Rate DeBounce: ON
9208 23:07:35.789863 DFS_NO_QUEUE_FLUSH: ON
9209 23:07:35.792892 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9210 23:07:35.796351 ENABLE_DFS_RUNTIME_MRW: OFF
9211 23:07:35.799233 DDR_RESERVE_NEW_MODE: ON
9212 23:07:35.799315 MR_CBT_SWITCH_FREQ: ON
9213 23:07:35.802940 =========================
9214 23:07:35.821752 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9215 23:07:35.824873 dram_init: ddr_geometry: 2
9216 23:07:35.843209 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9217 23:07:35.846780 dram_init: dram init end (result: 0)
9218 23:07:35.853146 DRAM-K: Full calibration passed in 24575 msecs
9219 23:07:35.856360 MRC: failed to locate region type 0.
9220 23:07:35.856443 DRAM rank0 size:0x100000000,
9221 23:07:35.860096 DRAM rank1 size=0x100000000
9222 23:07:35.870140 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9223 23:07:35.876494 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9224 23:07:35.883226 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9225 23:07:35.889766 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9226 23:07:35.892922 DRAM rank0 size:0x100000000,
9227 23:07:35.896167 DRAM rank1 size=0x100000000
9228 23:07:35.896250 CBMEM:
9229 23:07:35.900100 IMD: root @ 0xfffff000 254 entries.
9230 23:07:35.903023 IMD: root @ 0xffffec00 62 entries.
9231 23:07:35.906035 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9232 23:07:35.913233 WARNING: RO_VPD is uninitialized or empty.
9233 23:07:35.916364 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9234 23:07:35.923281 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9235 23:07:35.936333 read SPI 0x42894 0xe01e: 6228 us, 9212 KB/s, 73.696 Mbps
9236 23:07:35.947305 BS: romstage times (exec / console): total (unknown) / 24039 ms
9237 23:07:35.947388
9238 23:07:35.947453
9239 23:07:35.957714 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9240 23:07:35.960983 ARM64: Exception handlers installed.
9241 23:07:35.964162 ARM64: Testing exception
9242 23:07:35.967323 ARM64: Done test exception
9243 23:07:35.967405 Enumerating buses...
9244 23:07:35.970549 Show all devs... Before device enumeration.
9245 23:07:35.974201 Root Device: enabled 1
9246 23:07:35.977320 CPU_CLUSTER: 0: enabled 1
9247 23:07:35.977402 CPU: 00: enabled 1
9248 23:07:35.980865 Compare with tree...
9249 23:07:35.980948 Root Device: enabled 1
9250 23:07:35.984021 CPU_CLUSTER: 0: enabled 1
9251 23:07:35.987238 CPU: 00: enabled 1
9252 23:07:35.987320 Root Device scanning...
9253 23:07:35.990729 scan_static_bus for Root Device
9254 23:07:35.993844 CPU_CLUSTER: 0 enabled
9255 23:07:35.997085 scan_static_bus for Root Device done
9256 23:07:36.000380 scan_bus: bus Root Device finished in 8 msecs
9257 23:07:36.000462 done
9258 23:07:36.006840 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9259 23:07:36.010126 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9260 23:07:36.016957 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9261 23:07:36.020127 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9262 23:07:36.023585 Allocating resources...
9263 23:07:36.026587 Reading resources...
9264 23:07:36.030313 Root Device read_resources bus 0 link: 0
9265 23:07:36.033100 DRAM rank0 size:0x100000000,
9266 23:07:36.033184 DRAM rank1 size=0x100000000
9267 23:07:36.036771 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9268 23:07:36.040090 CPU: 00 missing read_resources
9269 23:07:36.046569 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9270 23:07:36.049624 Root Device read_resources bus 0 link: 0 done
9271 23:07:36.053250 Done reading resources.
9272 23:07:36.056436 Show resources in subtree (Root Device)...After reading.
9273 23:07:36.059667 Root Device child on link 0 CPU_CLUSTER: 0
9274 23:07:36.063094 CPU_CLUSTER: 0 child on link 0 CPU: 00
9275 23:07:36.073235 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9276 23:07:36.073318 CPU: 00
9277 23:07:36.076234 Root Device assign_resources, bus 0 link: 0
9278 23:07:36.079525 CPU_CLUSTER: 0 missing set_resources
9279 23:07:36.086624 Root Device assign_resources, bus 0 link: 0 done
9280 23:07:36.086708 Done setting resources.
9281 23:07:36.092815 Show resources in subtree (Root Device)...After assigning values.
9282 23:07:36.096288 Root Device child on link 0 CPU_CLUSTER: 0
9283 23:07:36.099683 CPU_CLUSTER: 0 child on link 0 CPU: 00
9284 23:07:36.109793 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9285 23:07:36.109876 CPU: 00
9286 23:07:36.113135 Done allocating resources.
9287 23:07:36.119654 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9288 23:07:36.119738 Enabling resources...
9289 23:07:36.119803 done.
9290 23:07:36.125761 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9291 23:07:36.129245 Initializing devices...
9292 23:07:36.129327 Root Device init
9293 23:07:36.132415 init hardware done!
9294 23:07:36.132498 0x00000018: ctrlr->caps
9295 23:07:36.135734 52.000 MHz: ctrlr->f_max
9296 23:07:36.139428 0.400 MHz: ctrlr->f_min
9297 23:07:36.139512 0x40ff8080: ctrlr->voltages
9298 23:07:36.142753 sclk: 390625
9299 23:07:36.142836 Bus Width = 1
9300 23:07:36.142920 sclk: 390625
9301 23:07:36.146084 Bus Width = 1
9302 23:07:36.146167 Early init status = 3
9303 23:07:36.152574 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9304 23:07:36.156177 in-header: 03 fc 00 00 01 00 00 00
9305 23:07:36.159366 in-data: 00
9306 23:07:36.162531 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9307 23:07:36.168088 in-header: 03 fd 00 00 00 00 00 00
9308 23:07:36.171673 in-data:
9309 23:07:36.174807 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9310 23:07:36.179023 in-header: 03 fc 00 00 01 00 00 00
9311 23:07:36.182641 in-data: 00
9312 23:07:36.185929 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9313 23:07:36.191333 in-header: 03 fd 00 00 00 00 00 00
9314 23:07:36.194577 in-data:
9315 23:07:36.197845 [SSUSB] Setting up USB HOST controller...
9316 23:07:36.201285 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9317 23:07:36.204892 [SSUSB] phy power-on done.
9318 23:07:36.207962 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9319 23:07:36.214262 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9320 23:07:36.217946 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9321 23:07:36.224433 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9322 23:07:36.231135 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
9323 23:07:36.237709 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9324 23:07:36.244267 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9325 23:07:36.250722 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9326 23:07:36.254568 SPM: binary array size = 0x9dc
9327 23:07:36.257791 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9328 23:07:36.263990 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9329 23:07:36.270931 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9330 23:07:36.277297 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9331 23:07:36.280915 configure_display: Starting display init
9332 23:07:36.314843 anx7625_power_on_init: Init interface.
9333 23:07:36.317935 anx7625_disable_pd_protocol: Disabled PD feature.
9334 23:07:36.321051 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9335 23:07:36.349412 anx7625_start_dp_work: Secure OCM version=00
9336 23:07:36.352274 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9337 23:07:36.367193 sp_tx_get_edid_block: EDID Block = 1
9338 23:07:36.469564 Extracted contents:
9339 23:07:36.473386 header: 00 ff ff ff ff ff ff 00
9340 23:07:36.476383 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9341 23:07:36.479699 version: 01 04
9342 23:07:36.483295 basic params: 95 1f 11 78 0a
9343 23:07:36.486363 chroma info: 76 90 94 55 54 90 27 21 50 54
9344 23:07:36.489270 established: 00 00 00
9345 23:07:36.496231 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9346 23:07:36.502676 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9347 23:07:36.505990 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9348 23:07:36.512478 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9349 23:07:36.519352 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9350 23:07:36.522608 extensions: 00
9351 23:07:36.522716 checksum: fb
9352 23:07:36.522811
9353 23:07:36.525889 Manufacturer: IVO Model 57d Serial Number 0
9354 23:07:36.529134 Made week 0 of 2020
9355 23:07:36.532389 EDID version: 1.4
9356 23:07:36.532471 Digital display
9357 23:07:36.535750 6 bits per primary color channel
9358 23:07:36.535833 DisplayPort interface
9359 23:07:36.539363 Maximum image size: 31 cm x 17 cm
9360 23:07:36.542367 Gamma: 220%
9361 23:07:36.542476 Check DPMS levels
9362 23:07:36.545463 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9363 23:07:36.552453 First detailed timing is preferred timing
9364 23:07:36.552536 Established timings supported:
9365 23:07:36.555474 Standard timings supported:
9366 23:07:36.559012 Detailed timings
9367 23:07:36.562390 Hex of detail: 383680a07038204018303c0035ae10000019
9368 23:07:36.568721 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9369 23:07:36.572004 0780 0798 07c8 0820 hborder 0
9370 23:07:36.575672 0438 043b 0447 0458 vborder 0
9371 23:07:36.578769 -hsync -vsync
9372 23:07:36.578850 Did detailed timing
9373 23:07:36.585220 Hex of detail: 000000000000000000000000000000000000
9374 23:07:36.588737 Manufacturer-specified data, tag 0
9375 23:07:36.592294 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9376 23:07:36.595235 ASCII string: InfoVision
9377 23:07:36.598355 Hex of detail: 000000fe00523134304e574635205248200a
9378 23:07:36.601988 ASCII string: R140NWF5 RH
9379 23:07:36.602070 Checksum
9380 23:07:36.605348 Checksum: 0xfb (valid)
9381 23:07:36.608817 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9382 23:07:36.611897 DSI data_rate: 832800000 bps
9383 23:07:36.618460 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9384 23:07:36.621656 anx7625_parse_edid: pixelclock(138800).
9385 23:07:36.624980 hactive(1920), hsync(48), hfp(24), hbp(88)
9386 23:07:36.628134 vactive(1080), vsync(12), vfp(3), vbp(17)
9387 23:07:36.631359 anx7625_dsi_config: config dsi.
9388 23:07:36.638357 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9389 23:07:36.651604 anx7625_dsi_config: success to config DSI
9390 23:07:36.655341 anx7625_dp_start: MIPI phy setup OK.
9391 23:07:36.658681 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9392 23:07:36.661788 mtk_ddp_mode_set invalid vrefresh 60
9393 23:07:36.665146 main_disp_path_setup
9394 23:07:36.665253 ovl_layer_smi_id_en
9395 23:07:36.668739 ovl_layer_smi_id_en
9396 23:07:36.668831 ccorr_config
9397 23:07:36.668928 aal_config
9398 23:07:36.671895 gamma_config
9399 23:07:36.671978 postmask_config
9400 23:07:36.675043 dither_config
9401 23:07:36.678367 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9402 23:07:36.685242 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9403 23:07:36.688064 Root Device init finished in 555 msecs
9404 23:07:36.691380 CPU_CLUSTER: 0 init
9405 23:07:36.698099 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9406 23:07:36.704490 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9407 23:07:36.704574 APU_MBOX 0x190000b0 = 0x10001
9408 23:07:36.708145 APU_MBOX 0x190001b0 = 0x10001
9409 23:07:36.711304 APU_MBOX 0x190005b0 = 0x10001
9410 23:07:36.714361 APU_MBOX 0x190006b0 = 0x10001
9411 23:07:36.720899 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9412 23:07:36.730919 read SPI 0x539f4 0xe237: 6249 us, 9267 KB/s, 74.136 Mbps
9413 23:07:36.743185 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9414 23:07:36.749997 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9415 23:07:36.761367 read SPI 0x61c74 0xe8ef: 6412 us, 9299 KB/s, 74.392 Mbps
9416 23:07:36.770632 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9417 23:07:36.774013 CPU_CLUSTER: 0 init finished in 81 msecs
9418 23:07:36.777362 Devices initialized
9419 23:07:36.780491 Show all devs... After init.
9420 23:07:36.780574 Root Device: enabled 1
9421 23:07:36.783817 CPU_CLUSTER: 0: enabled 1
9422 23:07:36.787423 CPU: 00: enabled 1
9423 23:07:36.790079 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9424 23:07:36.793802 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9425 23:07:36.796689 ELOG: NV offset 0x57f000 size 0x1000
9426 23:07:36.803439 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9427 23:07:36.810129 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9428 23:07:36.813288 ELOG: Event(17) added with size 13 at 2023-12-27 23:07:41 UTC
9429 23:07:36.820119 out: cmd=0x121: 03 db 21 01 00 00 00 00
9430 23:07:36.823644 in-header: 03 56 00 00 2c 00 00 00
9431 23:07:36.833291 in-data: 08 69 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9432 23:07:36.840098 ELOG: Event(A1) added with size 10 at 2023-12-27 23:07:41 UTC
9433 23:07:36.846636 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9434 23:07:36.853342 ELOG: Event(A0) added with size 9 at 2023-12-27 23:07:41 UTC
9435 23:07:36.856626 elog_add_boot_reason: Logged dev mode boot
9436 23:07:36.863137 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9437 23:07:36.863236 Finalize devices...
9438 23:07:36.866405 Devices finalized
9439 23:07:36.869622 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9440 23:07:36.872877 Writing coreboot table at 0xffe64000
9441 23:07:36.876645 0. 000000000010a000-0000000000113fff: RAMSTAGE
9442 23:07:36.879572 1. 0000000040000000-00000000400fffff: RAM
9443 23:07:36.886559 2. 0000000040100000-000000004032afff: RAMSTAGE
9444 23:07:36.889640 3. 000000004032b000-00000000545fffff: RAM
9445 23:07:36.892952 4. 0000000054600000-000000005465ffff: BL31
9446 23:07:36.896160 5. 0000000054660000-00000000ffe63fff: RAM
9447 23:07:36.902957 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9448 23:07:36.906690 7. 0000000100000000-000000023fffffff: RAM
9449 23:07:36.909612 Passing 5 GPIOs to payload:
9450 23:07:36.913071 NAME | PORT | POLARITY | VALUE
9451 23:07:36.916382 EC in RW | 0x000000aa | low | undefined
9452 23:07:36.922874 EC interrupt | 0x00000005 | low | undefined
9453 23:07:36.926253 TPM interrupt | 0x000000ab | high | undefined
9454 23:07:36.932839 SD card detect | 0x00000011 | high | undefined
9455 23:07:36.936440 speaker enable | 0x00000093 | high | undefined
9456 23:07:36.939733 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9457 23:07:36.942832 in-header: 03 f9 00 00 02 00 00 00
9458 23:07:36.946102 in-data: 02 00
9459 23:07:36.949804 ADC[4]: Raw value=895930 ID=7
9460 23:07:36.949886 ADC[3]: Raw value=212330 ID=1
9461 23:07:36.952880 RAM Code: 0x71
9462 23:07:36.956064 ADC[6]: Raw value=74722 ID=0
9463 23:07:36.956151 ADC[5]: Raw value=211590 ID=1
9464 23:07:36.959563 SKU Code: 0x1
9465 23:07:36.962791 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 5987
9466 23:07:36.966058 coreboot table: 964 bytes.
9467 23:07:36.969254 IMD ROOT 0. 0xfffff000 0x00001000
9468 23:07:36.972491 IMD SMALL 1. 0xffffe000 0x00001000
9469 23:07:36.975806 RO MCACHE 2. 0xffffc000 0x00001104
9470 23:07:36.979420 CONSOLE 3. 0xfff7c000 0x00080000
9471 23:07:36.982768 FMAP 4. 0xfff7b000 0x00000452
9472 23:07:36.985812 TIME STAMP 5. 0xfff7a000 0x00000910
9473 23:07:36.989688 VBOOT WORK 6. 0xfff66000 0x00014000
9474 23:07:36.992433 RAMOOPS 7. 0xffe66000 0x00100000
9475 23:07:36.995772 COREBOOT 8. 0xffe64000 0x00002000
9476 23:07:36.999146 IMD small region:
9477 23:07:37.002176 IMD ROOT 0. 0xffffec00 0x00000400
9478 23:07:37.005846 VPD 1. 0xffffeb80 0x0000006c
9479 23:07:37.009138 MMC STATUS 2. 0xffffeb60 0x00000004
9480 23:07:37.012372 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9481 23:07:37.015589 Probing TPM: done!
9482 23:07:37.018779 Connected to device vid:did:rid of 1ae0:0028:00
9483 23:07:37.029553 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9484 23:07:37.033086 Initialized TPM device CR50 revision 0
9485 23:07:37.036796 Checking cr50 for pending updates
9486 23:07:37.040341 Reading cr50 TPM mode
9487 23:07:37.049110 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9488 23:07:37.055538 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9489 23:07:37.095540 read SPI 0x3990ec 0x4f1b0: 34858 us, 9295 KB/s, 74.360 Mbps
9490 23:07:37.099164 Checking segment from ROM address 0x40100000
9491 23:07:37.102334 Checking segment from ROM address 0x4010001c
9492 23:07:37.109133 Loading segment from ROM address 0x40100000
9493 23:07:37.109211 code (compression=0)
9494 23:07:37.119194 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9495 23:07:37.125587 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9496 23:07:37.125671 it's not compressed!
9497 23:07:37.132430 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9498 23:07:37.135544 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9499 23:07:37.156272 Loading segment from ROM address 0x4010001c
9500 23:07:37.156357 Entry Point 0x80000000
9501 23:07:37.159581 Loaded segments
9502 23:07:37.162891 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9503 23:07:37.169815 Jumping to boot code at 0x80000000(0xffe64000)
9504 23:07:37.176341 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9505 23:07:37.182746 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9506 23:07:37.190465 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9507 23:07:37.194157 Checking segment from ROM address 0x40100000
9508 23:07:37.197294 Checking segment from ROM address 0x4010001c
9509 23:07:37.203946 Loading segment from ROM address 0x40100000
9510 23:07:37.204054 code (compression=1)
9511 23:07:37.210439 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9512 23:07:37.221156 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9513 23:07:37.221236 using LZMA
9514 23:07:37.228903 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9515 23:07:37.235973 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9516 23:07:37.239247 Loading segment from ROM address 0x4010001c
9517 23:07:37.239328 Entry Point 0x54601000
9518 23:07:37.242355 Loaded segments
9519 23:07:37.245681 NOTICE: MT8192 bl31_setup
9520 23:07:37.252394 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9521 23:07:37.255860 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9522 23:07:37.259526 WARNING: region 0:
9523 23:07:37.262696 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9524 23:07:37.262771 WARNING: region 1:
9525 23:07:37.269401 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9526 23:07:37.272709 WARNING: region 2:
9527 23:07:37.276131 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9528 23:07:37.279320 WARNING: region 3:
9529 23:07:37.282590 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9530 23:07:37.286311 WARNING: region 4:
9531 23:07:37.289698 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9532 23:07:37.292957 WARNING: region 5:
9533 23:07:37.296135 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9534 23:07:37.299317 WARNING: region 6:
9535 23:07:37.302569 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9536 23:07:37.302641 WARNING: region 7:
9537 23:07:37.309511 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9538 23:07:37.315897 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9539 23:07:37.319088 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9540 23:07:37.322891 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9541 23:07:37.329325 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9542 23:07:37.332732 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9543 23:07:37.336036 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9544 23:07:37.342568 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9545 23:07:37.345754 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9546 23:07:37.352589 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9547 23:07:37.356101 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9548 23:07:37.359499 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9549 23:07:37.366198 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9550 23:07:37.369153 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9551 23:07:37.372433 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9552 23:07:37.379376 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9553 23:07:37.382687 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9554 23:07:37.389308 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9555 23:07:37.392533 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9556 23:07:37.395761 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9557 23:07:37.402367 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9558 23:07:37.406196 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9559 23:07:37.409379 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9560 23:07:37.416102 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9561 23:07:37.419157 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9562 23:07:37.425884 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9563 23:07:37.429143 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9564 23:07:37.432765 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9565 23:07:37.439177 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9566 23:07:37.442341 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9567 23:07:37.448959 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9568 23:07:37.452771 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9569 23:07:37.455994 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9570 23:07:37.462739 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9571 23:07:37.466107 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9572 23:07:37.469167 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9573 23:07:37.472435 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9574 23:07:37.479475 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9575 23:07:37.482348 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9576 23:07:37.485810 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9577 23:07:37.489286 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9578 23:07:37.492477 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9579 23:07:37.499374 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9580 23:07:37.502498 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9581 23:07:37.505626 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9582 23:07:37.512812 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9583 23:07:37.515952 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9584 23:07:37.519105 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9585 23:07:37.522570 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9586 23:07:37.529357 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9587 23:07:37.532282 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9588 23:07:37.539044 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9589 23:07:37.542634 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9590 23:07:37.545648 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9591 23:07:37.552773 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9592 23:07:37.555947 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9593 23:07:37.562746 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9594 23:07:37.566127 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9595 23:07:37.572454 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9596 23:07:37.575711 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9597 23:07:37.579286 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9598 23:07:37.585929 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9599 23:07:37.589296 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9600 23:07:37.596205 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9601 23:07:37.599496 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9602 23:07:37.605702 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9603 23:07:37.609461 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9604 23:07:37.612772 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9605 23:07:37.619208 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9606 23:07:37.622416 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9607 23:07:37.629430 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9608 23:07:37.632783 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9609 23:07:37.639173 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9610 23:07:37.642912 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9611 23:07:37.645644 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9612 23:07:37.652803 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9613 23:07:37.656042 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9614 23:07:37.662482 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9615 23:07:37.665661 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9616 23:07:37.672675 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9617 23:07:37.675601 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9618 23:07:37.682678 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9619 23:07:37.685719 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9620 23:07:37.689156 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9621 23:07:37.695854 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9622 23:07:37.698966 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9623 23:07:37.705785 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9624 23:07:37.709124 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9625 23:07:37.716104 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9626 23:07:37.719176 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9627 23:07:37.722417 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9628 23:07:37.729480 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9629 23:07:37.732231 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9630 23:07:37.739149 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9631 23:07:37.742507 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9632 23:07:37.749287 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9633 23:07:37.752332 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9634 23:07:37.756028 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9635 23:07:37.762738 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9636 23:07:37.766042 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9637 23:07:37.769082 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9638 23:07:37.772335 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9639 23:07:37.779324 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9640 23:07:37.782545 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9641 23:07:37.789077 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9642 23:07:37.792432 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9643 23:07:37.795912 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9644 23:07:37.802629 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9645 23:07:37.806068 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9646 23:07:37.809339 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9647 23:07:37.815900 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9648 23:07:37.819341 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9649 23:07:37.825840 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9650 23:07:37.829078 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9651 23:07:37.832927 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9652 23:07:37.839376 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9653 23:07:37.842504 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9654 23:07:37.845821 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9655 23:07:37.852582 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9656 23:07:37.856125 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9657 23:07:37.858995 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9658 23:07:37.866153 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9659 23:07:37.869647 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9660 23:07:37.872645 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9661 23:07:37.876036 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9662 23:07:37.882497 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9663 23:07:37.885721 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9664 23:07:37.889368 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9665 23:07:37.895870 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9666 23:07:37.899399 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9667 23:07:37.905917 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9668 23:07:37.909136 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9669 23:07:37.912261 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9670 23:07:37.919173 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9671 23:07:37.922581 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9672 23:07:37.929020 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9673 23:07:37.932256 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9674 23:07:37.935602 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9675 23:07:37.942352 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9676 23:07:37.945617 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9677 23:07:37.949415 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9678 23:07:37.955774 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9679 23:07:37.959370 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9680 23:07:37.965981 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9681 23:07:37.969346 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9682 23:07:37.972626 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9683 23:07:37.979281 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9684 23:07:37.982477 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9685 23:07:37.989612 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9686 23:07:37.992468 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9687 23:07:37.996228 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9688 23:07:38.002670 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9689 23:07:38.005815 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9690 23:07:38.009481 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9691 23:07:38.016117 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9692 23:07:38.019183 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9693 23:07:38.026138 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9694 23:07:38.029185 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9695 23:07:38.032491 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9696 23:07:38.039292 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9697 23:07:38.042562 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9698 23:07:38.049322 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9699 23:07:38.052530 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9700 23:07:38.055750 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9701 23:07:38.062033 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9702 23:07:38.065755 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9703 23:07:38.072164 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9704 23:07:38.077063 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9705 23:07:38.078778 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9706 23:07:38.085073 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9707 23:07:38.088795 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9708 23:07:38.095362 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9709 23:07:38.098692 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9710 23:07:38.101710 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9711 23:07:38.108631 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9712 23:07:38.111873 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9713 23:07:38.118671 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9714 23:07:38.122059 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9715 23:07:38.125104 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9716 23:07:38.131962 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9717 23:07:38.135256 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9718 23:07:38.138327 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9719 23:07:38.145060 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9720 23:07:38.148543 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9721 23:07:38.155395 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9722 23:07:38.158200 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9723 23:07:38.161674 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9724 23:07:38.168591 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9725 23:07:38.172166 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9726 23:07:38.178417 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9727 23:07:38.181751 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9728 23:07:38.188326 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9729 23:07:38.191626 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9730 23:07:38.194770 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9731 23:07:38.201939 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9732 23:07:38.204672 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9733 23:07:38.211405 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9734 23:07:38.214710 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9735 23:07:38.218404 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9736 23:07:38.225020 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9737 23:07:38.227853 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9738 23:07:38.234518 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9739 23:07:38.237686 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9740 23:07:38.244304 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9741 23:07:38.247837 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9742 23:07:38.250903 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9743 23:07:38.257839 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9744 23:07:38.261077 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9745 23:07:38.267726 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9746 23:07:38.270720 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9747 23:07:38.274360 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9748 23:07:38.280767 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9749 23:07:38.284093 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9750 23:07:38.290782 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9751 23:07:38.294101 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9752 23:07:38.300691 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9753 23:07:38.304138 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9754 23:07:38.307359 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9755 23:07:38.313923 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9756 23:07:38.317461 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9757 23:07:38.323991 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9758 23:07:38.327064 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9759 23:07:38.330504 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9760 23:07:38.337157 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9761 23:07:38.340397 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9762 23:07:38.347053 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9763 23:07:38.350822 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9764 23:07:38.357076 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9765 23:07:38.360348 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9766 23:07:38.363788 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9767 23:07:38.370359 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9768 23:07:38.373750 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9769 23:07:38.377161 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9770 23:07:38.380540 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9771 23:07:38.383882 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9772 23:07:38.390230 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9773 23:07:38.393619 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9774 23:07:38.400293 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9775 23:07:38.403833 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9776 23:07:38.406976 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9777 23:07:38.413766 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9778 23:07:38.417073 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9779 23:07:38.423427 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9780 23:07:38.426710 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9781 23:07:38.430537 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9782 23:07:38.437084 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9783 23:07:38.440347 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9784 23:07:38.443604 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9785 23:07:38.450087 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9786 23:07:38.453554 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9787 23:07:38.456571 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9788 23:07:38.463597 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9789 23:07:38.466584 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9790 23:07:38.473227 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9791 23:07:38.476478 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9792 23:07:38.480178 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9793 23:07:38.486543 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9794 23:07:38.489875 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9795 23:07:38.493462 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9796 23:07:38.500095 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9797 23:07:38.503246 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9798 23:07:38.506596 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9799 23:07:38.513061 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9800 23:07:38.516565 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9801 23:07:38.520079 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9802 23:07:38.526413 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9803 23:07:38.529607 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9804 23:07:38.536295 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9805 23:07:38.539412 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9806 23:07:38.542685 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9807 23:07:38.549668 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9808 23:07:38.552940 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9809 23:07:38.556195 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9810 23:07:38.559615 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9811 23:07:38.562941 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9812 23:07:38.569260 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9813 23:07:38.572799 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9814 23:07:38.575776 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9815 23:07:38.579601 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9816 23:07:38.586220 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9817 23:07:38.589142 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9818 23:07:38.593073 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9819 23:07:38.599001 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9820 23:07:38.602303 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9821 23:07:38.606144 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9822 23:07:38.612617 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9823 23:07:38.615824 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9824 23:07:38.622133 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9825 23:07:38.625616 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9826 23:07:38.632206 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9827 23:07:38.635425 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9828 23:07:38.638608 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9829 23:07:38.645621 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9830 23:07:38.648845 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9831 23:07:38.655389 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9832 23:07:38.658600 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9833 23:07:38.665033 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9834 23:07:38.668426 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9835 23:07:38.671926 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9836 23:07:38.678431 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9837 23:07:38.681956 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9838 23:07:38.688373 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9839 23:07:38.691562 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9840 23:07:38.695089 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9841 23:07:38.701644 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9842 23:07:38.705053 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9843 23:07:38.711639 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9844 23:07:38.714837 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9845 23:07:38.718617 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9846 23:07:38.725165 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9847 23:07:38.728481 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9848 23:07:38.735123 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9849 23:07:38.738139 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9850 23:07:38.741439 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9851 23:07:38.748493 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9852 23:07:38.751910 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9853 23:07:38.758487 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9854 23:07:38.761668 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9855 23:07:38.765031 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9856 23:07:38.771633 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9857 23:07:38.774753 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9858 23:07:38.781243 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9859 23:07:38.784756 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9860 23:07:38.788015 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9861 23:07:38.794628 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9862 23:07:38.798128 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9863 23:07:38.804883 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9864 23:07:38.807974 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9865 23:07:38.814747 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9866 23:07:38.817714 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9867 23:07:38.821326 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9868 23:07:38.827828 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9869 23:07:38.830953 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9870 23:07:38.837670 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9871 23:07:38.841247 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9872 23:07:38.844266 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9873 23:07:38.851085 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9874 23:07:38.854285 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9875 23:07:38.860833 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9876 23:07:38.864587 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9877 23:07:38.867851 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9878 23:07:38.874434 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9879 23:07:38.877607 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9880 23:07:38.884110 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9881 23:07:38.887543 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9882 23:07:38.894291 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9883 23:07:38.897293 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9884 23:07:38.900924 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9885 23:07:38.907569 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9886 23:07:38.910661 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9887 23:07:38.917471 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9888 23:07:38.920716 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9889 23:07:38.923887 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9890 23:07:38.930309 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9891 23:07:38.934090 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9892 23:07:38.940548 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9893 23:07:38.943758 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9894 23:07:38.950250 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9895 23:07:38.953785 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9896 23:07:38.957133 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9897 23:07:38.963680 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9898 23:07:38.966834 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9899 23:07:38.973709 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9900 23:07:38.976908 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9901 23:07:38.983309 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9902 23:07:38.986985 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9903 23:07:38.993111 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9904 23:07:38.996985 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9905 23:07:39.000115 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9906 23:07:39.006553 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9907 23:07:39.009699 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9908 23:07:39.016237 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9909 23:07:39.019783 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9910 23:07:39.026309 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9911 23:07:39.029711 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9912 23:07:39.036206 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9913 23:07:39.039293 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9914 23:07:39.045882 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9915 23:07:39.049350 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9916 23:07:39.052893 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9917 23:07:39.059172 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9918 23:07:39.062703 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9919 23:07:39.068905 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9920 23:07:39.072820 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9921 23:07:39.078767 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9922 23:07:39.082630 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9923 23:07:39.085717 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9924 23:07:39.092158 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9925 23:07:39.095815 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9926 23:07:39.102329 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9927 23:07:39.105711 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9928 23:07:39.112126 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9929 23:07:39.115451 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9930 23:07:39.122428 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9931 23:07:39.125442 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9932 23:07:39.128984 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9933 23:07:39.135132 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9934 23:07:39.138731 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9935 23:07:39.145204 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9936 23:07:39.148492 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9937 23:07:39.155147 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9938 23:07:39.158641 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9939 23:07:39.161743 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9940 23:07:39.168464 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9941 23:07:39.171585 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9942 23:07:39.178078 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9943 23:07:39.181334 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9944 23:07:39.188273 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9945 23:07:39.191631 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9946 23:07:39.198184 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9947 23:07:39.201278 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9948 23:07:39.207920 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9949 23:07:39.211237 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9950 23:07:39.218127 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9951 23:07:39.221261 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9952 23:07:39.224603 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9953 23:07:39.231301 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9954 23:07:39.234597 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9955 23:07:39.241338 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9956 23:07:39.244622 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9957 23:07:39.251156 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9958 23:07:39.254630 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9959 23:07:39.261123 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9960 23:07:39.264453 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9961 23:07:39.271300 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9962 23:07:39.274479 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9963 23:07:39.280939 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9964 23:07:39.284372 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9965 23:07:39.290815 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9966 23:07:39.294285 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9967 23:07:39.300800 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9968 23:07:39.304176 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9969 23:07:39.310750 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9970 23:07:39.314046 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9971 23:07:39.320555 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9972 23:07:39.323870 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9973 23:07:39.327133 INFO: [APUAPC] vio 0
9974 23:07:39.330843 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9975 23:07:39.337279 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9976 23:07:39.340389 INFO: [APUAPC] D0_APC_0: 0x400510
9977 23:07:39.343685 INFO: [APUAPC] D0_APC_1: 0x0
9978 23:07:39.347488 INFO: [APUAPC] D0_APC_2: 0x1540
9979 23:07:39.347571 INFO: [APUAPC] D0_APC_3: 0x0
9980 23:07:39.350638 INFO: [APUAPC] D1_APC_0: 0xffffffff
9981 23:07:39.353683 INFO: [APUAPC] D1_APC_1: 0xffffffff
9982 23:07:39.357038 INFO: [APUAPC] D1_APC_2: 0x3fffff
9983 23:07:39.360676 INFO: [APUAPC] D1_APC_3: 0x0
9984 23:07:39.363735 INFO: [APUAPC] D2_APC_0: 0xffffffff
9985 23:07:39.367059 INFO: [APUAPC] D2_APC_1: 0xffffffff
9986 23:07:39.370541 INFO: [APUAPC] D2_APC_2: 0x3fffff
9987 23:07:39.373829 INFO: [APUAPC] D2_APC_3: 0x0
9988 23:07:39.376931 INFO: [APUAPC] D3_APC_0: 0xffffffff
9989 23:07:39.380438 INFO: [APUAPC] D3_APC_1: 0xffffffff
9990 23:07:39.383727 INFO: [APUAPC] D3_APC_2: 0x3fffff
9991 23:07:39.386884 INFO: [APUAPC] D3_APC_3: 0x0
9992 23:07:39.390157 INFO: [APUAPC] D4_APC_0: 0xffffffff
9993 23:07:39.393744 INFO: [APUAPC] D4_APC_1: 0xffffffff
9994 23:07:39.396591 INFO: [APUAPC] D4_APC_2: 0x3fffff
9995 23:07:39.400014 INFO: [APUAPC] D4_APC_3: 0x0
9996 23:07:39.403252 INFO: [APUAPC] D5_APC_0: 0xffffffff
9997 23:07:39.406779 INFO: [APUAPC] D5_APC_1: 0xffffffff
9998 23:07:39.410229 INFO: [APUAPC] D5_APC_2: 0x3fffff
9999 23:07:39.413482 INFO: [APUAPC] D5_APC_3: 0x0
10000 23:07:39.416823 INFO: [APUAPC] D6_APC_0: 0xffffffff
10001 23:07:39.419899 INFO: [APUAPC] D6_APC_1: 0xffffffff
10002 23:07:39.423228 INFO: [APUAPC] D6_APC_2: 0x3fffff
10003 23:07:39.426596 INFO: [APUAPC] D6_APC_3: 0x0
10004 23:07:39.429923 INFO: [APUAPC] D7_APC_0: 0xffffffff
10005 23:07:39.433037 INFO: [APUAPC] D7_APC_1: 0xffffffff
10006 23:07:39.436580 INFO: [APUAPC] D7_APC_2: 0x3fffff
10007 23:07:39.439882 INFO: [APUAPC] D7_APC_3: 0x0
10008 23:07:39.443166 INFO: [APUAPC] D8_APC_0: 0xffffffff
10009 23:07:39.446331 INFO: [APUAPC] D8_APC_1: 0xffffffff
10010 23:07:39.449484 INFO: [APUAPC] D8_APC_2: 0x3fffff
10011 23:07:39.453426 INFO: [APUAPC] D8_APC_3: 0x0
10012 23:07:39.456654 INFO: [APUAPC] D9_APC_0: 0xffffffff
10013 23:07:39.459673 INFO: [APUAPC] D9_APC_1: 0xffffffff
10014 23:07:39.462913 INFO: [APUAPC] D9_APC_2: 0x3fffff
10015 23:07:39.466090 INFO: [APUAPC] D9_APC_3: 0x0
10016 23:07:39.469674 INFO: [APUAPC] D10_APC_0: 0xffffffff
10017 23:07:39.472814 INFO: [APUAPC] D10_APC_1: 0xffffffff
10018 23:07:39.476607 INFO: [APUAPC] D10_APC_2: 0x3fffff
10019 23:07:39.479364 INFO: [APUAPC] D10_APC_3: 0x0
10020 23:07:39.482842 INFO: [APUAPC] D11_APC_0: 0xffffffff
10021 23:07:39.485956 INFO: [APUAPC] D11_APC_1: 0xffffffff
10022 23:07:39.489554 INFO: [APUAPC] D11_APC_2: 0x3fffff
10023 23:07:39.492919 INFO: [APUAPC] D11_APC_3: 0x0
10024 23:07:39.495908 INFO: [APUAPC] D12_APC_0: 0xffffffff
10025 23:07:39.499584 INFO: [APUAPC] D12_APC_1: 0xffffffff
10026 23:07:39.502622 INFO: [APUAPC] D12_APC_2: 0x3fffff
10027 23:07:39.506208 INFO: [APUAPC] D12_APC_3: 0x0
10028 23:07:39.509682 INFO: [APUAPC] D13_APC_0: 0xffffffff
10029 23:07:39.512635 INFO: [APUAPC] D13_APC_1: 0xffffffff
10030 23:07:39.516120 INFO: [APUAPC] D13_APC_2: 0x3fffff
10031 23:07:39.519314 INFO: [APUAPC] D13_APC_3: 0x0
10032 23:07:39.522866 INFO: [APUAPC] D14_APC_0: 0xffffffff
10033 23:07:39.525740 INFO: [APUAPC] D14_APC_1: 0xffffffff
10034 23:07:39.529429 INFO: [APUAPC] D14_APC_2: 0x3fffff
10035 23:07:39.532730 INFO: [APUAPC] D14_APC_3: 0x0
10036 23:07:39.536089 INFO: [APUAPC] D15_APC_0: 0xffffffff
10037 23:07:39.539162 INFO: [APUAPC] D15_APC_1: 0xffffffff
10038 23:07:39.542478 INFO: [APUAPC] D15_APC_2: 0x3fffff
10039 23:07:39.545753 INFO: [APUAPC] D15_APC_3: 0x0
10040 23:07:39.548988 INFO: [APUAPC] APC_CON: 0x4
10041 23:07:39.552309 INFO: [NOCDAPC] D0_APC_0: 0x0
10042 23:07:39.555560 INFO: [NOCDAPC] D0_APC_1: 0x0
10043 23:07:39.555644 INFO: [NOCDAPC] D1_APC_0: 0x0
10044 23:07:39.558868 INFO: [NOCDAPC] D1_APC_1: 0xfff
10045 23:07:39.562572 INFO: [NOCDAPC] D2_APC_0: 0x0
10046 23:07:39.565739 INFO: [NOCDAPC] D2_APC_1: 0xfff
10047 23:07:39.568811 INFO: [NOCDAPC] D3_APC_0: 0x0
10048 23:07:39.572162 INFO: [NOCDAPC] D3_APC_1: 0xfff
10049 23:07:39.575343 INFO: [NOCDAPC] D4_APC_0: 0x0
10050 23:07:39.578989 INFO: [NOCDAPC] D4_APC_1: 0xfff
10051 23:07:39.582312 INFO: [NOCDAPC] D5_APC_0: 0x0
10052 23:07:39.585727 INFO: [NOCDAPC] D5_APC_1: 0xfff
10053 23:07:39.588760 INFO: [NOCDAPC] D6_APC_0: 0x0
10054 23:07:39.591840 INFO: [NOCDAPC] D6_APC_1: 0xfff
10055 23:07:39.591928 INFO: [NOCDAPC] D7_APC_0: 0x0
10056 23:07:39.595233 INFO: [NOCDAPC] D7_APC_1: 0xfff
10057 23:07:39.598655 INFO: [NOCDAPC] D8_APC_0: 0x0
10058 23:07:39.601910 INFO: [NOCDAPC] D8_APC_1: 0xfff
10059 23:07:39.605395 INFO: [NOCDAPC] D9_APC_0: 0x0
10060 23:07:39.608999 INFO: [NOCDAPC] D9_APC_1: 0xfff
10061 23:07:39.611987 INFO: [NOCDAPC] D10_APC_0: 0x0
10062 23:07:39.615212 INFO: [NOCDAPC] D10_APC_1: 0xfff
10063 23:07:39.618751 INFO: [NOCDAPC] D11_APC_0: 0x0
10064 23:07:39.622081 INFO: [NOCDAPC] D11_APC_1: 0xfff
10065 23:07:39.625182 INFO: [NOCDAPC] D12_APC_0: 0x0
10066 23:07:39.628681 INFO: [NOCDAPC] D12_APC_1: 0xfff
10067 23:07:39.632096 INFO: [NOCDAPC] D13_APC_0: 0x0
10068 23:07:39.632180 INFO: [NOCDAPC] D13_APC_1: 0xfff
10069 23:07:39.635160 INFO: [NOCDAPC] D14_APC_0: 0x0
10070 23:07:39.638499 INFO: [NOCDAPC] D14_APC_1: 0xfff
10071 23:07:39.641674 INFO: [NOCDAPC] D15_APC_0: 0x0
10072 23:07:39.645115 INFO: [NOCDAPC] D15_APC_1: 0xfff
10073 23:07:39.648372 INFO: [NOCDAPC] APC_CON: 0x4
10074 23:07:39.651982 INFO: [APUAPC] set_apusys_apc done
10075 23:07:39.655373 INFO: [DEVAPC] devapc_init done
10076 23:07:39.658721 INFO: GICv3 without legacy support detected.
10077 23:07:39.661912 INFO: ARM GICv3 driver initialized in EL3
10078 23:07:39.668353 INFO: Maximum SPI INTID supported: 639
10079 23:07:39.671600 INFO: BL31: Initializing runtime services
10080 23:07:39.678504 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10081 23:07:39.678587 INFO: SPM: enable CPC mode
10082 23:07:39.684909 INFO: mcdi ready for mcusys-off-idle and system suspend
10083 23:07:39.688386 INFO: BL31: Preparing for EL3 exit to normal world
10084 23:07:39.691625 INFO: Entry point address = 0x80000000
10085 23:07:39.695099 INFO: SPSR = 0x8
10086 23:07:39.701106
10087 23:07:39.701189
10088 23:07:39.701255
10089 23:07:39.704133 Starting depthcharge on Spherion...
10090 23:07:39.704216
10091 23:07:39.704282 Wipe memory regions:
10092 23:07:39.704344
10093 23:07:39.704994 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10094 23:07:39.705092 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10095 23:07:39.705419 Setting prompt string to ['asurada:']
10096 23:07:39.705510 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10097 23:07:39.707682 [0x00000040000000, 0x00000054600000)
10098 23:07:39.829633
10099 23:07:39.829735 [0x00000054660000, 0x00000080000000)
10100 23:07:40.090139
10101 23:07:40.090273 [0x000000821a7280, 0x000000ffe64000)
10102 23:07:40.835177
10103 23:07:40.835323 [0x00000100000000, 0x00000240000000)
10104 23:07:42.725050
10105 23:07:42.728741 Initializing XHCI USB controller at 0x11200000.
10106 23:07:43.766252
10107 23:07:43.769437 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10108 23:07:43.769590
10109 23:07:43.769677
10110 23:07:43.769757
10111 23:07:43.770114 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10113 23:07:43.870491 asurada: tftpboot 192.168.201.1 12395343/tftp-deploy-8402ppx3/kernel/image.itb 12395343/tftp-deploy-8402ppx3/kernel/cmdline
10114 23:07:43.870611 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10115 23:07:43.870710 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10116 23:07:43.874969 tftpboot 192.168.201.1 12395343/tftp-deploy-8402ppx3/kernel/image.ittp-deploy-8402ppx3/kernel/cmdline
10117 23:07:43.875057
10118 23:07:43.875149 Waiting for link
10119 23:07:44.035311
10120 23:07:44.035428 R8152: Initializing
10121 23:07:44.035525
10122 23:07:44.039106 Version 6 (ocp_data = 5c30)
10123 23:07:44.039181
10124 23:07:44.042255 R8152: Done initializing
10125 23:07:44.042329
10126 23:07:44.042410 Adding net device
10127 23:07:46.087479
10128 23:07:46.087625 done.
10129 23:07:46.087722
10130 23:07:46.087805 MAC: 00:24:32:30:78:ff
10131 23:07:46.087905
10132 23:07:46.090616 Sending DHCP discover... done.
10133 23:07:46.090696
10134 23:07:56.625806 Waiting for reply... R8152: Bulk read error 0xffffffbf
10135 23:07:56.625956
10136 23:07:56.628959 Receive failed.
10137 23:07:56.629045
10138 23:07:56.629110 done.
10139 23:07:56.629171
10140 23:07:56.632695 Sending DHCP request... done.
10141 23:07:56.632778
10142 23:07:56.635904 Waiting for reply... done.
10143 23:07:56.635987
10144 23:07:56.636052 My ip is 192.168.201.21
10145 23:07:56.636114
10146 23:07:56.638937 The DHCP server ip is 192.168.201.1
10147 23:07:56.639051
10148 23:07:56.645948 TFTP server IP predefined by user: 192.168.201.1
10149 23:07:56.646026
10150 23:07:56.652704 Bootfile predefined by user: 12395343/tftp-deploy-8402ppx3/kernel/image.itb
10151 23:07:56.652788
10152 23:07:56.655839 Sending tftp read request... done.
10153 23:07:56.655922
10154 23:07:56.659799 Waiting for the transfer...
10155 23:07:56.659880
10156 23:07:57.183335 00000000 ################################################################
10157 23:07:57.183484
10158 23:07:57.705240 00080000 ################################################################
10159 23:07:57.705389
10160 23:07:58.250878 00100000 ################################################################
10161 23:07:58.251018
10162 23:07:58.781797 00180000 ################################################################
10163 23:07:58.781936
10164 23:07:59.303739 00200000 ################################################################
10165 23:07:59.303879
10166 23:07:59.828129 00280000 ################################################################
10167 23:07:59.828274
10168 23:08:00.375727 00300000 ################################################################
10169 23:08:00.375872
10170 23:08:00.897564 00380000 ################################################################
10171 23:08:00.897723
10172 23:08:01.415418 00400000 ################################################################
10173 23:08:01.415561
10174 23:08:01.938663 00480000 ################################################################
10175 23:08:01.938809
10176 23:08:02.463183 00500000 ################################################################
10177 23:08:02.463328
10178 23:08:02.988891 00580000 ################################################################
10179 23:08:02.989037
10180 23:08:03.513539 00600000 ################################################################
10181 23:08:03.513682
10182 23:08:04.038187 00680000 ################################################################
10183 23:08:04.038334
10184 23:08:04.624108 00700000 ################################################################
10185 23:08:04.624248
10186 23:08:05.147672 00780000 ################################################################
10187 23:08:05.147818
10188 23:08:05.673656 00800000 ################################################################
10189 23:08:05.673797
10190 23:08:06.185387 00880000 ################################################################
10191 23:08:06.185563
10192 23:08:06.710721 00900000 ################################################################
10193 23:08:06.710863
10194 23:08:07.227030 00980000 ################################################################
10195 23:08:07.227171
10196 23:08:07.746195 00a00000 ################################################################
10197 23:08:07.746338
10198 23:08:08.259564 00a80000 ################################################################
10199 23:08:08.259708
10200 23:08:08.784169 00b00000 ################################################################
10201 23:08:08.784308
10202 23:08:09.333500 00b80000 ################################################################
10203 23:08:09.333658
10204 23:08:09.853179 00c00000 ################################################################
10205 23:08:09.853324
10206 23:08:10.396801 00c80000 ################################################################
10207 23:08:10.396946
10208 23:08:10.954255 00d00000 ################################################################
10209 23:08:10.954400
10210 23:08:11.469858 00d80000 ################################################################
10211 23:08:11.470000
10212 23:08:12.017225 00e00000 ################################################################
10213 23:08:12.017396
10214 23:08:12.633975 00e80000 ################################################################
10215 23:08:12.634536
10216 23:08:13.364553 00f00000 ################################################################
10217 23:08:13.365136
10218 23:08:14.106620 00f80000 ################################################################
10219 23:08:14.107155
10220 23:08:14.722534 01000000 ################################################################
10221 23:08:14.723036
10222 23:08:15.270409 01080000 ################################################################
10223 23:08:15.270545
10224 23:08:15.936129 01100000 ################################################################
10225 23:08:15.936654
10226 23:08:16.639245 01180000 ################################################################
10227 23:08:16.639818
10228 23:08:17.347698 01200000 ################################################################
10229 23:08:17.348231
10230 23:08:18.073188 01280000 ################################################################
10231 23:08:18.073560
10232 23:08:18.690801 01300000 ################################################################
10233 23:08:18.691468
10234 23:08:19.246091 01380000 ################################################################
10235 23:08:19.246221
10236 23:08:19.942811 01400000 ################################################################
10237 23:08:19.943456
10238 23:08:20.656183 01480000 ################################################################
10239 23:08:20.656701
10240 23:08:21.369602 01500000 ################################################################
10241 23:08:21.370166
10242 23:08:22.105329 01580000 ################################################################
10243 23:08:22.105891
10244 23:08:22.801216 01600000 ################################################################
10245 23:08:22.801847
10246 23:08:23.517276 01680000 ################################################################
10247 23:08:23.517863
10248 23:08:24.234674 01700000 ################################################################
10249 23:08:24.235263
10250 23:08:24.962017 01780000 ################################################################
10251 23:08:24.962545
10252 23:08:25.700359 01800000 ################################################################
10253 23:08:25.701011
10254 23:08:26.399523 01880000 ################################################################
10255 23:08:26.400033
10256 23:08:27.126108 01900000 ################################################################
10257 23:08:27.126657
10258 23:08:27.866099 01980000 ################################################################
10259 23:08:27.866618
10260 23:08:28.606337 01a00000 ################################################################
10261 23:08:28.606875
10262 23:08:29.346583 01a80000 ################################################################
10263 23:08:29.347135
10264 23:08:30.099662 01b00000 ################################################################
10265 23:08:30.100240
10266 23:08:30.784079 01b80000 ############################################################ done.
10267 23:08:30.784626
10268 23:08:30.787065 The bootfile was 29327198 bytes long.
10269 23:08:30.787499
10270 23:08:30.790556 Sending tftp read request... done.
10271 23:08:30.790985
10272 23:08:30.794903 Waiting for the transfer...
10273 23:08:30.795331
10274 23:08:30.795670 00000000 # done.
10275 23:08:30.795993
10276 23:08:30.801372 Command line loaded dynamically from TFTP file: 12395343/tftp-deploy-8402ppx3/kernel/cmdline
10277 23:08:30.804567
10278 23:08:30.824672 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12395343/extract-nfsrootfs-kd_xsd9a,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10279 23:08:30.825222
10280 23:08:30.825619 Loading FIT.
10281 23:08:30.825950
10282 23:08:30.827487 Image ramdisk-1 has 17797497 bytes.
10283 23:08:30.827832
10284 23:08:30.831257 Image fdt-1 has 47278 bytes.
10285 23:08:30.831785
10286 23:08:30.834652 Image kernel-1 has 11480388 bytes.
10287 23:08:30.835084
10288 23:08:30.844857 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10289 23:08:30.845395
10290 23:08:30.861470 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10291 23:08:30.862173
10292 23:08:30.867732 Choosing best match conf-1 for compat google,spherion-rev2.
10293 23:08:30.868187
10294 23:08:30.875488 Connected to device vid:did:rid of 1ae0:0028:00
10295 23:08:30.882029
10296 23:08:30.885720 tpm_get_response: command 0x17b, return code 0x0
10297 23:08:30.886302
10298 23:08:30.892197 ec_init: CrosEC protocol v3 supported (256, 248)
10299 23:08:30.892726
10300 23:08:30.895058 tpm_cleanup: add release locality here.
10301 23:08:30.895488
10302 23:08:30.898643 Shutting down all USB controllers.
10303 23:08:30.899073
10304 23:08:30.901868 Removing current net device
10305 23:08:30.902296
10306 23:08:30.905092 Exiting depthcharge with code 4 at timestamp: 80519735
10307 23:08:30.905551
10308 23:08:30.911968 LZMA decompressing kernel-1 to 0x821a6718
10309 23:08:30.912489
10310 23:08:30.914894 LZMA decompressing kernel-1 to 0x40000000
10311 23:08:32.350207
10312 23:08:32.350776 jumping to kernel
10313 23:08:32.352977 end: 2.2.4 bootloader-commands (duration 00:00:53) [common]
10314 23:08:32.353558 start: 2.2.5 auto-login-action (timeout 00:03:33) [common]
10315 23:08:32.353982 Setting prompt string to ['Linux version [0-9]']
10316 23:08:32.354365 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10317 23:08:32.354749 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10318 23:08:32.431839
10319 23:08:32.434831 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10320 23:08:32.439034 start: 2.2.5.1 login-action (timeout 00:03:32) [common]
10321 23:08:32.439562 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10322 23:08:32.440024 Setting prompt string to []
10323 23:08:32.440427 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10324 23:08:32.440801 Using line separator: #'\n'#
10325 23:08:32.441115 No login prompt set.
10326 23:08:32.441437 Parsing kernel messages
10327 23:08:32.441795 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10328 23:08:32.442413 [login-action] Waiting for messages, (timeout 00:03:32)
10329 23:08:32.458213 [ 0.000000] Linux version 6.1.67-cip12-rt7 (KernelCI@build-j59954-arm64-gcc-10-defconfig-arm64-chromebook-nblph) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Wed Dec 27 22:50:56 UTC 2023
10330 23:08:32.461372 [ 0.000000] random: crng init done
10331 23:08:32.468403 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10332 23:08:32.471460 [ 0.000000] efi: UEFI not found.
10333 23:08:32.477888 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10334 23:08:32.484694 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10335 23:08:32.494972 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10336 23:08:32.504471 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10337 23:08:32.511287 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10338 23:08:32.517370 [ 0.000000] printk: bootconsole [mtk8250] enabled
10339 23:08:32.524072 [ 0.000000] NUMA: No NUMA configuration found
10340 23:08:32.531090 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10341 23:08:32.533961 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcfa00-0x23efd1fff]
10342 23:08:32.537428 [ 0.000000] Zone ranges:
10343 23:08:32.544568 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10344 23:08:32.547336 [ 0.000000] DMA32 empty
10345 23:08:32.554333 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10346 23:08:32.557770 [ 0.000000] Movable zone start for each node
10347 23:08:32.561083 [ 0.000000] Early memory node ranges
10348 23:08:32.567500 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10349 23:08:32.574526 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10350 23:08:32.580882 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10351 23:08:32.587575 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10352 23:08:32.590614 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10353 23:08:32.600758 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10354 23:08:32.655779 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10355 23:08:32.662329 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10356 23:08:32.668840 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10357 23:08:32.672133 [ 0.000000] psci: probing for conduit method from DT.
10358 23:08:32.678883 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10359 23:08:32.682387 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10360 23:08:32.688583 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10361 23:08:32.691950 [ 0.000000] psci: SMC Calling Convention v1.2
10362 23:08:32.698671 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10363 23:08:32.701805 [ 0.000000] Detected VIPT I-cache on CPU0
10364 23:08:32.708516 [ 0.000000] CPU features: detected: GIC system register CPU interface
10365 23:08:32.715111 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10366 23:08:32.721541 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10367 23:08:32.728365 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10368 23:08:32.738503 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10369 23:08:32.744992 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10370 23:08:32.748231 [ 0.000000] alternatives: applying boot alternatives
10371 23:08:32.754828 [ 0.000000] Fallback order for Node 0: 0
10372 23:08:32.761282 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10373 23:08:32.765052 [ 0.000000] Policy zone: Normal
10374 23:08:32.787848 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12395343/extract-nfsrootfs-kd_xsd9a,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10375 23:08:32.798256 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10376 23:08:32.807946 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10377 23:08:32.818408 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10378 23:08:32.824508 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10379 23:08:32.828098 <6>[ 0.000000] software IO TLB: area num 8.
10380 23:08:32.884403 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10381 23:08:33.033743 <6>[ 0.000000] Memory: 7951340K/8385536K available (17984K kernel code, 4116K rwdata, 18184K rodata, 8448K init, 615K bss, 401428K reserved, 32768K cma-reserved)
10382 23:08:33.040832 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10383 23:08:33.047123 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10384 23:08:33.050499 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10385 23:08:33.057160 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10386 23:08:33.063505 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10387 23:08:33.067210 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10388 23:08:33.077048 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10389 23:08:33.083850 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10390 23:08:33.090090 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10391 23:08:33.096485 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10392 23:08:33.100013 <6>[ 0.000000] GICv3: 608 SPIs implemented
10393 23:08:33.103127 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10394 23:08:33.110121 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10395 23:08:33.113382 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10396 23:08:33.120247 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10397 23:08:33.133545 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10398 23:08:33.143080 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10399 23:08:33.153340 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10400 23:08:33.160555 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10401 23:08:33.173765 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10402 23:08:33.180483 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10403 23:08:33.186870 <6>[ 0.009234] Console: colour dummy device 80x25
10404 23:08:33.197272 <6>[ 0.013956] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10405 23:08:33.203834 <6>[ 0.024399] pid_max: default: 32768 minimum: 301
10406 23:08:33.207042 <6>[ 0.029270] LSM: Security Framework initializing
10407 23:08:33.213238 <6>[ 0.034207] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10408 23:08:33.223501 <6>[ 0.042020] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10409 23:08:33.233189 <6>[ 0.051431] cblist_init_generic: Setting adjustable number of callback queues.
10410 23:08:33.236311 <6>[ 0.058918] cblist_init_generic: Setting shift to 3 and lim to 1.
10411 23:08:33.246025 <6>[ 0.065256] cblist_init_generic: Setting adjustable number of callback queues.
10412 23:08:33.252435 <6>[ 0.072683] cblist_init_generic: Setting shift to 3 and lim to 1.
10413 23:08:33.256092 <6>[ 0.079124] rcu: Hierarchical SRCU implementation.
10414 23:08:33.262819 <6>[ 0.079126] rcu: Max phase no-delay instances is 1000.
10415 23:08:33.269508 <6>[ 0.079150] printk: bootconsole [mtk8250] printing thread started
10416 23:08:33.276294 <6>[ 0.097488] EFI services will not be available.
10417 23:08:33.279319 <6>[ 0.097689] smp: Bringing up secondary CPUs ...
10418 23:08:33.285864 <6>[ 0.097999] Detected VIPT I-cache on CPU1
10419 23:08:33.292964 <6>[ 0.098067] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10420 23:08:33.298866 <6>[ 0.098098] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10421 23:08:33.308794 <6>[ 0.125979] Detected VIPT I-cache on CPU2
10422 23:08:33.318745 <6>[ 0.126025] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10423 23:08:33.325065 <6>[ 0.126039] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10424 23:08:33.328275 <6>[ 0.126295] Detected VIPT I-cache on CPU3
10425 23:08:33.335384 <6>[ 0.126340] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10426 23:08:33.341690 <6>[ 0.126354] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10427 23:08:33.345045 <6>[ 0.126663] CPU features: detected: Spectre-v4
10428 23:08:33.351509 <6>[ 0.126669] CPU features: detected: Spectre-BHB
10429 23:08:33.354576 <6>[ 0.126674] Detected PIPT I-cache on CPU4
10430 23:08:33.361306 <6>[ 0.126732] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10431 23:08:33.367706 <6>[ 0.126748] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10432 23:08:33.374406 <6>[ 0.127042] Detected PIPT I-cache on CPU5
10433 23:08:33.381123 <6>[ 0.127103] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10434 23:08:33.387992 <6>[ 0.127119] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10435 23:08:33.391089 <6>[ 0.127394] Detected PIPT I-cache on CPU6
10436 23:08:33.401278 <6>[ 0.127456] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10437 23:08:33.407666 <6>[ 0.127473] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10438 23:08:33.410681 <6>[ 0.127767] Detected PIPT I-cache on CPU7
10439 23:08:33.417303 <6>[ 0.127829] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10440 23:08:33.423981 <6>[ 0.127846] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10441 23:08:33.427090 <6>[ 0.127892] smp: Brought up 1 node, 8 CPUs
10442 23:08:33.433643 <6>[ 0.127897] SMP: Total of 8 processors activated.
10443 23:08:33.440128 <6>[ 0.127900] CPU features: detected: 32-bit EL0 Support
10444 23:08:33.447054 <6>[ 0.127902] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10445 23:08:33.453695 <6>[ 0.127904] CPU features: detected: Common not Private translations
10446 23:08:33.460389 <6>[ 0.127906] CPU features: detected: CRC32 instructions
10447 23:08:33.466807 <6>[ 0.127908] CPU features: detected: RCpc load-acquire (LDAPR)
10448 23:08:33.469934 <6>[ 0.127909] CPU features: detected: LSE atomic instructions
10449 23:08:33.476530 <6>[ 0.127911] CPU features: detected: Privileged Access Never
10450 23:08:33.483658 <6>[ 0.127913] CPU features: detected: RAS Extension Support
10451 23:08:33.489677 <6>[ 0.127916] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10452 23:08:33.492939 <6>[ 0.127987] CPU: All CPU(s) started at EL2
10453 23:08:33.500064 <6>[ 0.127989] alternatives: applying system-wide alternatives
10454 23:08:33.503370 <6>[ 0.141032] devtmpfs: initialized
10455 23:08:33.512983 <6>[ 0.147248] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10456 23:08:33.538656 �p3] NET: Registered PF_INET protocol family
10457 23:08:33.545154 <6><[ 0.365310] printk: console [ttyS0] printing thread started
10458 23:08:33.552467 6>[ 0.228752] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10459 23:08:33.559096 <6>[ 0.365319] printk: console [ttyS0] enabled
10460 23:08:33.562407 <6>[ 0.365324] printk: bootconsole [mtk8250] disabled
10461 23:08:33.569169 <6>[ 0.378997] printk: bootconsole [mtk8250] printing thread stopped
10462 23:08:33.575705 <6>[ 0.380288] SuperH (H)SCI(F) driver initialized
10463 23:08:33.578979 <6>[ 0.380777] msm_serial: driver initialized
10464 23:08:33.588776 <6>[ 0.385499] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10465 23:08:33.595719 <6>[ 0.385528] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10466 23:08:33.608650 <6>[ 0.385557] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10467 23:08:33.618131 <6>[ 0.385587] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10468 23:08:33.626881 <6>[ 0.385608] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10469 23:08:33.643384 <6>[ 0.385635] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10470 23:08:33.643954 <6>[ 0.385663] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10471 23:08:33.653032 <6>[ 0.385797] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10472 23:08:33.662986 <6>[ 0.385826] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10473 23:08:33.663409 <6>[ 0.394743] loop: module loaded
10474 23:08:33.666914 <6>[ 0.397230] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10475 23:08:33.673292 <4>[ 0.413787] mtk-pmic-keys: Failed to locate of_node [id: -1]
10476 23:08:33.676467 <6>[ 0.414638] megasas: 07.719.03.00-rc1
10477 23:08:33.679694 <6>[ 0.424828] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10478 23:08:33.686667 <6>[ 0.428824] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10479 23:08:33.693507 <6>[ 0.440509] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10480 23:08:33.706545 <6>[ 0.493801] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10481 23:08:34.187538 <6>[ 1.006395] Freeing initrd memory: 17376K
10482 23:08:34.194082 <6>[ 1.012337] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10483 23:08:34.197098 <6>[ 1.016990] tun: Universal TUN/TAP device driver, 1.6
10484 23:08:34.200699 <6>[ 1.017733] thunder_xcv, ver 1.0
10485 23:08:34.203642 <6>[ 1.017752] thunder_bgx, ver 1.0
10486 23:08:34.206878 <6>[ 1.017770] nicpf, ver 1.0
10487 23:08:34.213996 <6>[ 1.018818] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10488 23:08:34.220030 <6>[ 1.018821] hns3: Copyright (c) 2017 Huawei Corporation.
10489 23:08:34.224093 <6>[ 1.018848] hclge is initializing
10490 23:08:34.230221 <6>[ 1.018860] e1000: Intel(R) PRO/1000 Network Driver
10491 23:08:34.236995 <6>[ 1.018862] e1000: Copyright (c) 1999-2006 Intel Corporation.
10492 23:08:34.240315 <6>[ 1.018881] e1000e: Intel(R) PRO/1000 Network Driver
10493 23:08:34.248121 <6>[ 1.018882] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10494 23:08:34.250964 <6>[ 1.018897] igb: Intel(R) Gigabit Ethernet Network Driver
10495 23:08:34.257942 <6>[ 1.018899] igb: Copyright (c) 2007-2014 Intel Corporation.
10496 23:08:34.264894 <6>[ 1.018913] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10497 23:08:34.271368 <6>[ 1.018915] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10498 23:08:34.274717 <6>[ 1.019206] sky2: driver version 1.30
10499 23:08:34.281520 <6>[ 1.020279] VFIO - User Level meta-driver version: 0.3
10500 23:08:34.284764 <6>[ 1.023123] usbcore: registered new interface driver usb-storage
10501 23:08:34.291613 <6>[ 1.023307] usbcore: registered new device driver onboard-usb-hub
10502 23:08:34.298609 <6>[ 1.026080] mt6397-rtc mt6359-rtc: registered as rtc0
10503 23:08:34.308534 <6>[ 1.026235] mt6397-rtc mt6359-rtc: setting system clock to 2023-12-27T23:08:38 UTC (1703718518)
10504 23:08:34.311564 <6>[ 1.026843] i2c_dev: i2c /dev entries driver
10505 23:08:34.317929 <6>[ 1.033972] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10506 23:08:34.324787 <6>[ 1.048962] cpu cpu0: EM: created perf domain
10507 23:08:34.328369 <6>[ 1.049276] cpu cpu4: EM: created perf domain
10508 23:08:34.334400 <6>[ 1.052006] sdhci: Secure Digital Host Controller Interface driver
10509 23:08:34.341173 <6>[ 1.052007] sdhci: Copyright(c) Pierre Ossman
10510 23:08:34.344557 <6>[ 1.052363] Synopsys Designware Multimedia Card Interface Driver
10511 23:08:34.351495 <6>[ 1.052731] sdhci-pltfm: SDHCI platform and OF driver helper
10512 23:08:34.354525 <6>[ 1.057306] mmc0: CQHCI version 5.10
10513 23:08:34.361563 <6>[ 1.063147] ledtrig-cpu: registered to indicate activity on CPUs
10514 23:08:34.367950 <6>[ 1.063903] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10515 23:08:34.374383 <6>[ 1.064176] usbcore: registered new interface driver usbhid
10516 23:08:34.377587 <6>[ 1.064178] usbhid: USB HID core driver
10517 23:08:34.384520 <6>[ 1.064308] spi_master spi0: will run message pump with realtime priority
10518 23:08:34.397591 <6>[ 1.095293] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10519 23:08:34.410707 <6>[ 1.097170] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10520 23:08:34.417168 <6>[ 1.099084] cros-ec-spi spi0.0: Chrome EC device registered
10521 23:08:34.427280 <6>[ 1.111755] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10522 23:08:34.431159 <6>[ 1.112746] NET: Registered PF_PACKET protocol family
10523 23:08:34.437539 <6>[ 1.112821] 9pnet: Installing 9P2000 support
10524 23:08:34.440969 <5>[ 1.112857] Key type dns_resolver registered
10525 23:08:34.444129 <6>[ 1.113139] registered taskstats version 1
10526 23:08:34.450682 <5>[ 1.113153] Loading compiled-in X.509 certificates
10527 23:08:34.460938 <4>[ 1.129385] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10528 23:08:34.470835 <4>[ 1.129651] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10529 23:08:34.477216 <3>[ 1.129668] debugfs: File 'uA_load' in directory '/' already present!
10530 23:08:34.483635 <3>[ 1.129679] debugfs: File 'min_uV' in directory '/' already present!
10531 23:08:34.490175 <3>[ 1.129685] debugfs: File 'max_uV' in directory '/' already present!
10532 23:08:34.500131 <3>[ 1.129691] debugfs: File 'constraint_flags' in directory '/' already present!
10533 23:08:34.506905 <3>[ 1.132405] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10534 23:08:34.513625 <6>[ 1.139978] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10535 23:08:34.520252 <6>[ 1.140553] xhci-mtk 11200000.usb: xHCI Host Controller
10536 23:08:34.526993 <6>[ 1.140572] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10537 23:08:34.536943 <6>[ 1.140801] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10538 23:08:34.543374 <6>[ 1.140854] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10539 23:08:34.547279 <6>[ 1.140950] xhci-mtk 11200000.usb: xHCI Host Controller
10540 23:08:34.556995 <6>[ 1.140957] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10541 23:08:34.563417 <6>[ 1.140964] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10542 23:08:34.566692 <6>[ 1.141608] hub 1-0:1.0: USB hub found
10543 23:08:34.569887 <6>[ 1.141627] hub 1-0:1.0: 1 port detected
10544 23:08:34.580143 <6>[ 1.141845] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10545 23:08:34.583234 <6>[ 1.142160] hub 2-0:1.0: USB hub found
10546 23:08:34.586758 <6>[ 1.142173] hub 2-0:1.0: 1 port detected
10547 23:08:34.593375 <6>[ 1.144897] mtk-msdc 11f70000.mmc: Got CD GPIO
10548 23:08:34.596564 <6>[ 1.151834] mmc0: Command Queue Engine enabled
10549 23:08:34.603260 <6>[ 1.151849] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10550 23:08:34.606369 <6>[ 1.152620] mmcblk0: mmc0:0001 DA4128 116 GiB
10551 23:08:34.613078 <6>[ 1.156565] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10552 23:08:34.620023 <6>[ 1.157759] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10553 23:08:34.623700 <6>[ 1.158505] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10554 23:08:34.629864 <6>[ 1.159152] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10555 23:08:34.640190 <6>[ 1.161047] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10556 23:08:34.646638 <6>[ 1.161053] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10557 23:08:34.656635 <4>[ 1.161208] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10558 23:08:34.663001 <6>[ 1.162286] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10559 23:08:34.673539 <6>[ 1.162291] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10560 23:08:34.679979 <6>[ 1.162410] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10561 23:08:34.686794 <6>[ 1.162422] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10562 23:08:34.696112 <6>[ 1.162426] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10563 23:08:34.703155 <6>[ 1.162432] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10564 23:08:34.712954 <6>[ 1.163888] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10565 23:08:34.719260 <6>[ 1.163906] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10566 23:08:34.729150 <6>[ 1.163913] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10567 23:08:34.736037 <6>[ 1.163919] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10568 23:08:34.745855 <6>[ 1.163925] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10569 23:08:34.755652 <6>[ 1.163932] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10570 23:08:34.762937 <6>[ 1.163938] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10571 23:08:34.772266 <6>[ 1.163944] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10572 23:08:34.778969 <6>[ 1.163951] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10573 23:08:34.788678 <6>[ 1.163957] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10574 23:08:34.795093 <6>[ 1.163963] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10575 23:08:34.805041 <6>[ 1.163969] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10576 23:08:34.812154 <6>[ 1.163976] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10577 23:08:34.821930 <6>[ 1.163982] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10578 23:08:34.828966 <6>[ 1.163988] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10579 23:08:34.834794 <6>[ 1.164481] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10580 23:08:34.841637 <6>[ 1.165309] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10581 23:08:34.848113 <6>[ 1.165900] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10582 23:08:34.854840 <6>[ 1.166530] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10583 23:08:34.861316 <6>[ 1.167162] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10584 23:08:34.871644 <6>[ 1.167360] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10585 23:08:34.881234 <6>[ 1.167374] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10586 23:08:34.891480 <6>[ 1.167379] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10587 23:08:34.898095 <6>[ 1.167385] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10588 23:08:34.907554 <6>[ 1.167390] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10589 23:08:34.917693 <6>[ 1.167396] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10590 23:08:34.927609 <6>[ 1.167401] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10591 23:08:34.937421 <6>[ 1.167406] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10592 23:08:34.943913 <6>[ 1.167410] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10593 23:08:34.957569 <6>[ 1.167417] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10594 23:08:34.967273 <6>[ 1.167422] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10595 23:08:34.974225 <6>[ 1.168102] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10596 23:08:34.980916 <6>[ 1.177942] Trying to probe devices needed for running init ...
10597 23:08:34.987439 <6>[ 1.565644] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10598 23:08:34.990521 <6>[ 1.718392] hub 1-1:1.0: USB hub found
10599 23:08:34.996979 <6>[ 1.718797] hub 1-1:1.0: 4 ports detected
10600 23:08:35.000332 <6>[ 1.722831] hub 1-1:1.0: USB hub found
10601 23:08:35.003556 <6>[ 1.723187] hub 1-1:1.0: 4 ports detected
10602 23:08:35.026305 <6>[ 1.841854] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10603 23:08:35.047047 <6>[ 1.867335] hub 2-1:1.0: USB hub found
10604 23:08:35.050796 <6>[ 1.867783] hub 2-1:1.0: 3 ports detected
10605 23:08:35.053578 <6>[ 1.870575] hub 2-1:1.0: USB hub found
10606 23:08:35.056914 <6>[ 1.870995] hub 2-1:1.0: 3 ports detected
10607 23:08:35.218007 <6>[ 2.033761] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10608 23:08:35.338798 <6>[ 2.160501] hub 1-1.4:1.0: USB hub found
10609 23:08:35.342009 <6>[ 2.160808] hub 1-1.4:1.0: 2 ports detected
10610 23:08:35.345553 <6>[ 2.163846] hub 1-1.4:1.0: USB hub found
10611 23:08:35.352674 <6>[ 2.164198] hub 1-1.4:1.0: 2 ports detected
10612 23:08:35.422076 <6>[ 2.237872] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10613 23:08:35.638440 <6>[ 2.453736] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10614 23:08:35.822139 <6>[ 2.637740] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10615 23:08:46.649934 <6>[ 13.474679] ALSA device list:
10616 23:08:46.657135 <6>[ 13.474699] No soundcards found.
10617 23:08:46.660598 <6>[ 13.478991] Freeing unused kernel memory: 8448K
10618 23:08:46.664146 <6>[ 13.479240] Run /init as init process
10619 23:08:46.666895 Loading, please wait...
10620 23:08:46.683585 Starting version 247.3-7+deb11u2
10621 23:08:46.924865 <6>[ 13.742407] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10622 23:08:46.940889 <3>[ 13.757637] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10623 23:08:46.947645 <3>[ 13.757706] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10624 23:08:46.957294 <3>[ 13.757718] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10625 23:08:46.960488 <6>[ 13.757756] remoteproc remoteproc0: scp is available
10626 23:08:46.967057 <6>[ 13.757880] remoteproc remoteproc0: powering up scp
10627 23:08:46.977095 <6>[ 13.757889] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10628 23:08:46.980303 <6>[ 13.757909] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10629 23:08:46.990519 <6>[ 13.759483] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10630 23:08:46.997107 <6>[ 13.759508] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10631 23:08:47.006943 <6>[ 13.759515] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10632 23:08:47.014156 <3>[ 13.761578] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10633 23:08:47.023823 <3>[ 13.761587] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10634 23:08:47.030260 <3>[ 13.761589] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10635 23:08:47.040517 <3>[ 13.761594] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10636 23:08:47.046733 <3>[ 13.761596] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10637 23:08:47.053379 <3>[ 13.761620] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10638 23:08:47.064210 <3>[ 13.761647] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10639 23:08:47.070333 <3>[ 13.761649] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10640 23:08:47.080883 <3>[ 13.761652] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10641 23:08:47.087378 <3>[ 13.761670] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10642 23:08:47.097243 <3>[ 13.761673] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10643 23:08:47.103773 <3>[ 13.761675] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10644 23:08:47.110082 <3>[ 13.761677] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10645 23:08:47.120244 <3>[ 13.761679] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10646 23:08:47.126676 <3>[ 13.761695] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10647 23:08:47.133867 <6>[ 13.796645] mc: Linux media interface: v0.10
10648 23:08:47.140461 <6>[ 13.807613] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10649 23:08:47.147055 <4>[ 13.810742] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10650 23:08:47.153241 <4>[ 13.810861] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10651 23:08:47.160118 <6>[ 13.813586] videodev: Linux video capture interface: v2.00
10652 23:08:47.167087 <6>[ 13.829026] usbcore: registered new interface driver r8152
10653 23:08:47.176990 <4>[ 13.845030] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10654 23:08:47.180187 <4>[ 13.845030] Fallback method does not support PEC.
10655 23:08:47.189630 <3>[ 13.860454] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10656 23:08:47.196183 <6>[ 13.881140] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10657 23:08:47.202817 <6>[ 13.881156] pci_bus 0000:00: root bus resource [bus 00-ff]
10658 23:08:47.209847 <6>[ 13.881164] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10659 23:08:47.219398 <6>[ 13.881166] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10660 23:08:47.226585 <6>[ 13.881206] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10661 23:08:47.233379 <6>[ 13.881223] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10662 23:08:47.235991 <6>[ 13.881288] pci 0000:00:00.0: supports D1 D2
10663 23:08:47.242731 <6>[ 13.881290] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10664 23:08:47.252948 <6>[ 13.882207] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10665 23:08:47.259519 <6>[ 13.882285] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10666 23:08:47.266171 <6>[ 13.882309] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10667 23:08:47.272776 <6>[ 13.882327] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10668 23:08:47.279166 <6>[ 13.882342] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10669 23:08:47.285914 <6>[ 13.882443] pci 0000:01:00.0: supports D1 D2
10670 23:08:47.292714 <6>[ 13.882444] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10671 23:08:47.299219 <6>[ 13.883828] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10672 23:08:47.309253 <6>[ 13.883858] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10673 23:08:47.312654 <6>[ 13.883865] remoteproc remoteproc0: remote processor scp is now up
10674 23:08:47.321935 <3>[ 13.890256] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10675 23:08:47.328879 <6>[ 13.893525] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10676 23:08:47.339086 <6>[ 13.893557] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10677 23:08:47.345512 <6>[ 13.893561] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10678 23:08:47.355084 <6>[ 13.893569] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10679 23:08:47.362232 <6>[ 13.893582] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10680 23:08:47.368661 <6>[ 13.893595] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10681 23:08:47.375127 <6>[ 13.893608] pci 0000:00:00.0: PCI bridge to [bus 01]
10682 23:08:47.381571 <6>[ 13.893613] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10683 23:08:47.391757 <6>[ 13.893647] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10684 23:08:47.398060 <6>[ 13.893737] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10685 23:08:47.405092 <6>[ 13.894278] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10686 23:08:47.408555 <6>[ 13.894689] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10687 23:08:47.418182 <6>[ 13.896442] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10688 23:08:47.428257 <6>[ 13.920759] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10689 23:08:47.434377 <6>[ 13.929907] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10690 23:08:47.444236 <6>[ 13.938115] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10691 23:08:47.454348 <6>[ 13.938439] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10692 23:08:47.458074 <6>[ 13.958482] Bluetooth: Core ver 2.22
10693 23:08:47.461275 <6>[ 13.958584] NET: Registered PF_BLUETOOTH protocol family
10694 23:08:47.467859 <6>[ 13.958587] Bluetooth: HCI device and connection manager initialized
10695 23:08:47.474165 <6>[ 13.958617] Bluetooth: HCI socket layer initialized
10696 23:08:47.480831 <6>[ 13.958623] Bluetooth: L2CAP socket layer initialized
10697 23:08:47.484473 <6>[ 13.958632] Bluetooth: SCO socket layer initialized
10698 23:08:47.490747 <6>[ 13.961864] usbcore: registered new interface driver cdc_ether
10699 23:08:47.501183 <4>[ 13.970599] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10700 23:08:47.507379 <4>[ 13.970613] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10701 23:08:47.514455 <6>[ 13.970671] usbcore: registered new interface driver r8153_ecm
10702 23:08:47.520784 <5>[ 13.974300] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10703 23:08:47.527238 <5>[ 13.985337] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10704 23:08:47.536943 <4>[ 13.985516] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10705 23:08:47.543442 <6>[ 13.985525] cfg80211: failed to load regulatory.db
10706 23:08:47.549958 <6>[ 14.020428] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10707 23:08:47.563456 <6>[ 14.021668] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10708 23:08:47.566807 <6>[ 14.021843] usbcore: registered new interface driver uvcvideo
10709 23:08:47.573046 <6>[ 14.032043] usbcore: registered new interface driver btusb
10710 23:08:47.583319 <4>[ 14.032656] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10711 23:08:47.589545 <3>[ 14.032664] Bluetooth: hci0: Failed to load firmware file (-2)
10712 23:08:47.596506 <3>[ 14.032667] Bluetooth: hci0: Failed to set up firmware (-2)
10713 23:08:47.605856 <4>[ 14.032670] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10714 23:08:47.612379 <6>[ 14.048541] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10715 23:08:47.616110 <6>[ 14.053738] r8152 2-1.3:1.0 eth0: v1.12.13
10716 23:08:47.622640 <6>[ 14.058190] r8152 2-1.3:1.0 enx0024323078ff: renamed from eth0
10717 23:08:47.629371 <6>[ 14.099210] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10718 23:08:47.635761 <6>[ 14.099305] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10719 23:08:47.642444 <6>[ 14.117626] mt7921e 0000:01:00.0: ASIC revision: 79610010
10720 23:08:47.652117 <6>[ 14.212816] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
10721 23:08:47.652557 <6>[ 14.212816]
10722 23:08:47.662028 <6>[ 14.470724] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
10723 23:08:47.665783 Begin: Loading essential drivers ... done.
10724 23:08:47.668785 Begin: Running /scripts/init-premount ... done.
10725 23:08:47.675322 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10726 23:08:47.685271 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10727 23:08:47.688474 Device /sys/class/net/enx0024323078ff found
10728 23:08:47.689000 done.
10729 23:08:47.740591 IP-Config: enx0024323078ff hardware address 00:24:32:30:78:ff mtu 1500 DHCP
10730 23:08:48.493781 <6>[ 15.314717] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10731 23:08:48.929375 <6>[ 15.752214] r8152 2-1.3:1.0 enx0024323078ff: carrier on
10732 23:08:49.701880 IP-Config: no response after 2 secs - giving up
10733 23:08:49.740360 IP-Config: enx0024323078ff hardware address 00:24:32:30:78:ff mtu 1500 DHCP
10734 23:08:49.753123 IP-Config: wlp1s0 hardware address d8:f3:bc:78:28:07 mtu 1500 DHCP
10735 23:08:50.469873 IP-Config: enx0024323078ff complete (dhcp from 192.168.201.1):
10736 23:08:50.476367 address: 192.168.201.21 broadcast: 192.168.201.255 netmask: 255.255.255.0
10737 23:08:50.483498 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10738 23:08:50.490028 host : mt8192-asurada-spherion-r0-cbg-8
10739 23:08:50.496419 domain : lava-rack
10740 23:08:50.499601 rootserver: 192.168.201.1 rootpath:
10741 23:08:50.503083 filename :
10742 23:08:50.616677 done.
10743 23:08:50.625654 Begin: Running /scripts/nfs-bottom ... done.
10744 23:08:50.645514 Begin: Running /scripts/init-bottom ... done.
10745 23:08:51.933087 <6>[ 18.753763] NET: Registered PF_INET6 protocol family
10746 23:08:51.935924 <6>[ 18.755995] Segment Routing with IPv6
10747 23:08:51.939520 <6>[ 18.756044] In-situ OAM (IOAM) with IPv6
10748 23:08:52.084889 <30>[ 18.886189] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10749 23:08:52.085535
10750 23:08:52.091562 Welcome to [1<30>[ 18.887180] systemd[1]: Detected architecture arm64.
10751 23:08:52.094759 mDebian GNU/Linux 11 (bullseye)[0m!
10752 23:08:52.095188
10753 23:08:52.117180 <30>[ 18.940744] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10754 23:08:53.136127 <30>[ 19.955952] systemd[1]: Queued start job for default target Graphical Interface.
10755 23:08:53.159485 [[0;32m OK [<30>[ 19.980113] systemd[1]: Created slice system-getty.slice.
10756 23:08:53.162451 0m] Created slice [0;1;39msystem-getty.slice[0m.
10757 23:08:53.182398 [[0;32m OK [0m] Created slic<30>[ 20.003156] systemd[1]: Created slice system-modprobe.slice.
10758 23:08:53.185663 e [0;1;39msystem-modprobe.slice[0m.
10759 23:08:53.205837 [[0;32m OK [0m] Created slic<30>[ 20.026955] systemd[1]: Created slice system-serial\x2dgetty.slice.
10760 23:08:53.212300 e [0;1;39msystem-serial\x2dgetty.slice[0m.
10761 23:08:53.230390 [[0;32m OK [0m] Created slic<30>[ 20.051565] systemd[1]: Created slice User and Session Slice.
10762 23:08:53.233556 e [0;1;39mUser and Session Slice[0m.
10763 23:08:53.256701 [[0;32m OK [0m] Started [0;1;39mDispatch Pa<30>[ 20.074489] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10764 23:08:53.259993 ssword …ts to Console Directory Watch[0m.
10765 23:08:53.285181 [[0;32m OK [0m] Started [0;1;39mForward Pas<30>[ 20.102493] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10766 23:08:53.288361 sword R…uests to Wall Directory Watch[0m.
10767 23:08:53.315861 [[0;32m OK [0m] Reached targ<30>[ 20.130276] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10768 23:08:53.322643 <30>[ 20.130540] systemd[1]: Reached target Local Encrypted Volumes.
10769 23:08:53.326107 et [0;1;39mLocal Encrypted Volumes[0m.
10770 23:08:53.344435 [[0;32m OK [0m] Reached target [0;1;39mPath<30>[ 20.165859] systemd[1]: Reached target Paths.
10771 23:08:53.345005 s[0m.
10772 23:08:53.367493 [[0;32m OK [0m] Reached target [0;1;39mRemo<30>[ 20.185731] systemd[1]: Reached target Remote File Systems.
10773 23:08:53.368048 te File Systems[0m.
10774 23:08:53.384539 [[0;32m OK [0m] Reached target [0;1;39mSlic<30>[ 20.205707] systemd[1]: Reached target Slices.
10775 23:08:53.385104 es[0m.
10776 23:08:53.404927 [[0;32m OK [0m] Reached target [0;1;39mSwap<30>[ 20.225740] systemd[1]: Reached target Swap.
10777 23:08:53.405559 [0m.
10778 23:08:53.428604 [[0;32m OK [0m] Listening on [0;1;39minitct<30>[ 20.246158] systemd[1]: Listening on initctl Compatibility Named Pipe.
10779 23:08:53.431744 l Compatibility Named Pipe[0m.
10780 23:08:53.441801 [[0;32m OK [0m] Listening on [0;1;39mJourna<30>[ 20.262465] systemd[1]: Listening on Journal Audit Socket.
10781 23:08:53.444669 l Audit Socket[0m.
10782 23:08:53.466032 [[0;32m OK [0m] Listening on<30>[ 20.287256] systemd[1]: Listening on Journal Socket (/dev/log).
10783 23:08:53.469577 [0;1;39mJournal Socket (/dev/log)[0m.
10784 23:08:53.490074 [[0;32m OK [0m] Listening on<30>[ 20.310997] systemd[1]: Listening on Journal Socket.
10785 23:08:53.493168 [0;1;39mJournal Socket[0m.
10786 23:08:53.510997 [[0;32m OK [0m] Listening on<30>[ 20.331712] systemd[1]: Listening on Network Service Netlink Socket.
10787 23:08:53.517235 [0;1;39mNetwork Service Netlink Socket[0m.
10788 23:08:53.536333 [[0;32m OK [0m] Listening on [0;1;39mudev C<30>[ 20.357584] systemd[1]: Listening on udev Control Socket.
10789 23:08:53.539798 ontrol Socket[0m.
10790 23:08:53.557303 [[0;32m OK [0m] Listening on [0;1;39mudev K<30>[ 20.378168] systemd[1]: Listening on udev Kernel Socket.
10791 23:08:53.560500 ernel Socket[0m.
10792 23:08:53.607937 Mounting [0;1;39mHuge Pages File Syste<30>[ 20.425828] systemd[1]: Mounting Huge Pages File System...
10793 23:08:53.608518 m[0m...
10794 23:08:53.631756 Mounting [0;1;39mPOSIX Message Queue F<30>[ 20.449525] systemd[1]: Mounting POSIX Message Queue File System...
10795 23:08:53.632327 ile System[0m...
10796 23:08:53.660452 Mounting [0;1;39mKernel Debug File Sys<30>[ 20.478344] systemd[1]: Mounting Kernel Debug File System...
10797 23:08:53.660889 tem[0m...
10798 23:08:53.683400 Startin<30>[ 20.497979] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10799 23:08:53.692887 g [0;1;39mCreat<30>[ 20.501352] systemd[1]: Starting Create list of static device nodes for the current kernel...
10800 23:08:53.696100 e list of st…odes for the current kernel[0m...
10801 23:08:53.723259 Startin<30>[ 20.544724] systemd[1]: Starting Load Kernel Module configfs...
10802 23:08:53.726197 g [0;1;39mLoad Kernel Module configfs[0m...
10803 23:08:53.751865 Startin<30>[ 20.572935] systemd[1]: Starting Load Kernel Module drm...
10804 23:08:53.754940 g [0;1;39mLoad Kernel Module drm[0m...
10805 23:08:53.781615 Starting [0;1;39mLoad <30>[ 20.602671] systemd[1]: Starting Load Kernel Module fuse...
10806 23:08:53.784652 Kernel Module fuse[0m...
10807 23:08:53.824863 <6>[ 20.647238] fuse: init (API version 7.37)
10808 23:08:53.834441 <30>[ 20.647582] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10809 23:08:53.869009 Starting [0;1;39mJournal Service[0m..<30>[ 20.690253] systemd[1]: Starting Journal Service...
10810 23:08:53.869623 .
10811 23:08:53.901850 Starting [0;1;39mLoad <30>[ 20.723132] systemd[1]: Starting Load Kernel Modules...
10812 23:08:53.905002 Kernel Modules[0m...
10813 23:08:53.928152 <30>[ 20.749089] systemd[1]: Starting Remount Root and Kernel File Systems...
10814 23:08:53.934974 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10815 23:08:53.959199 Startin<30>[ 20.780401] systemd[1]: Starting Coldplug All udev Devices...
10816 23:08:53.962701 g [0;1;39mColdplug All udev Devices[0m...
10817 23:08:53.984948 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages <30>[ 20.806468] systemd[1]: Mounted Huge Pages File System.
10818 23:08:53.988129 File System[0m.
10819 23:08:54.008814 [[0;32m OK [0m] Mounted [0;<30>[ 20.830767] systemd[1]: Mounted POSIX Message Queue File System.
10820 23:08:54.012471 1;39mPOSIX Message Queue File System[0m.
10821 23:08:54.032636 [[0;32m OK [0m] Mounted [0;1;39mKernel Debu<30>[ 20.854369] systemd[1]: Mounted Kernel Debug File System.
10822 23:08:54.035687 g File System[0m.
10823 23:08:54.063094 [[0;32m OK [<30>[ 20.881105] systemd[1]: Finished Create list of static device nodes for the current kernel.
10824 23:08:54.069697 0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10825 23:08:54.084673 <30>[ 20.908431] systemd[1]: modprobe@configfs.service: Succeeded.
10826 23:08:54.090692 <30>[ 20.910576] systemd[1]: Finished Load Kernel Module configfs.
10827 23:08:54.097333 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10828 23:08:54.118289 [[0;32m OK [0m] Finished [0<30>[ 20.938608] systemd[1]: modprobe@drm.service: Succeeded.
10829 23:08:54.125030 ;1;39mLoad Kerne<30>[ 20.939518] systemd[1]: Finished Load Kernel Module drm.
10830 23:08:54.128141 l Module drm[0m.
10831 23:08:54.146194 [[0;32m OK [0m] Finished [0<30>[ 20.966628] systemd[1]: modprobe@fuse.service: Succeeded.
10832 23:08:54.153052 ;1;39mLoad Kerne<30>[ 20.967324] systemd[1]: Finished Load Kernel Module fuse.
10833 23:08:54.156316 l Module fuse[0m.
10834 23:08:54.173852 [[0;32m OK [0m] Finished [0<30>[ 20.994973] systemd[1]: Finished Load Kernel Modules.
10835 23:08:54.177529 ;1;39mLoad Kernel Modules[0m.
10836 23:08:54.187933 <3>[ 21.009259] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10837 23:08:54.198858 [[0;32m OK [0m] Finished [0<30>[ 21.019871] systemd[1]: Finished Remount Root and Kernel File Systems.
10838 23:08:54.205385 ;1;39mRemount Root and Kernel File Systems[0m.
10839 23:08:54.220106 <3>[ 21.038557] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10840 23:08:54.249971 Mounting [0;1;39mFUSE Control File Sys<30>[ 21.070277] systemd[1]: Mounting FUSE Control File System...
10841 23:08:54.253449 tem[0m...
10842 23:08:54.260064 <3>[ 21.079814] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10843 23:08:54.273347 Mounting [0;1;39mKerne<30>[ 21.094494] systemd[1]: Mounting Kernel Configuration File System...
10844 23:08:54.276276 l Configuration File System[0m...
10845 23:08:54.291472 <3>[ 21.109560] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10846 23:08:54.308259 <30>[ 21.127836] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10847 23:08:54.318103 <30>[ 21.128010] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10848 23:08:54.325176 <3>[ 21.134612] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10849 23:08:54.335396 <3>[ 21.156216] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10850 23:08:54.342276 <30>[ 21.158394] systemd[1]: Starting Load/Save Random Seed...
10851 23:08:54.345295 Starting [0;1;39mLoad/Save Random Seed[0m...
10852 23:08:54.355705 <3>[ 21.176496] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10853 23:08:54.364292 <30>[ 21.189367] systemd[1]: Starting Apply Kernel Variables...
10854 23:08:54.371079 Starting [0;1;39mApply Kernel Variables[0m...
10855 23:08:54.391896 <3>[ 21.209697] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10856 23:08:54.411750 <3>[ 21.229868] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10857 23:08:54.418967 <30>[ 21.234312] systemd[1]: Starting Create System Users...
10858 23:08:54.422237 Starting [0;1;39mCreate System Users[0m...
10859 23:08:54.432260 <3>[ 21.251574] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10860 23:08:54.447139 [[0;32m OK [<30>[ 21.268153] systemd[1]: Mounted FUSE Control File System.
10861 23:08:54.450209 0m] Mounted [0;1;39mFUSE Control File System[0m.
10862 23:08:54.472769 [[0;32m OK [0m] Mounted [0;1;39mKernel Conf<30>[ 21.290592] systemd[1]: Mounted Kernel Configuration File System.
10863 23:08:54.473225 iguration File System[0m.
10864 23:08:54.492757 [[0;32m OK [0m] Started [0;1;39mJournal Ser<30>[ 21.314253] systemd[1]: Started Journal Service.
10865 23:08:54.495956 vice[0m.
10866 23:08:54.511964 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10867 23:08:54.530205 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10868 23:08:54.590935 <4>[ 21.401534] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10869 23:08:54.597719 <3>[ 21.401550] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10870 23:08:54.604350 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10871 23:08:54.622385 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10872 23:08:54.639892 <46>[ 21.461062] systemd-journald[306]: Received client request to flush runtime journal.
10873 23:08:54.650480 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10874 23:08:54.664827 See 'systemctl status systemd-udev-trigger.service' for details.
10875 23:08:54.705317 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10876 23:08:56.038456 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10877 23:08:56.096959 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10878 23:08:56.109209 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10879 23:08:56.125015 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10880 23:08:56.185858 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10881 23:08:56.208584 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10882 23:08:56.409869 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10883 23:08:56.457424 Starting [0;1;39mNetwork Service[0m...
10884 23:08:56.759715 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10885 23:08:56.785860 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10886 23:08:56.834330 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10887 23:08:57.126914 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10888 23:08:57.175856 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10889 23:08:57.195833 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10890 23:08:57.248868 Starting [0;1;39mNetwork Time Synchronization[0m...
10891 23:08:57.269373 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10892 23:08:57.285047 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10893 23:08:57.305683 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10894 23:08:57.374074 Starting [0;1;39mNetwork Name Resolution[0m...
10895 23:08:57.392136 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10896 23:08:57.419741 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10897 23:08:57.454782 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10898 23:08:57.474537 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10899 23:08:57.496593 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10900 23:08:57.518449 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10901 23:08:57.534275 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10902 23:08:57.548774 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10903 23:08:57.588432 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10904 23:08:57.700819 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10905 23:08:58.146947 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10906 23:08:58.327519 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10907 23:08:58.340489 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10908 23:08:58.454914 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10909 23:08:58.468123 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10910 23:08:58.484077 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10911 23:08:58.545447 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10912 23:08:58.764271 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
10913 23:08:58.876831 Starting [0;1;39mUser Login Management[0m...
10914 23:08:59.320642 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10915 23:08:59.353999 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
10916 23:08:59.369746 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10917 23:08:59.387462 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10918 23:08:59.445711 Starting [0;1;39mPermit User Sessions[0m...
10919 23:08:59.462383 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10920 23:08:59.494272 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10921 23:08:59.537648 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10922 23:08:59.577901 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10923 23:08:59.593872 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10924 23:08:59.609617 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10925 23:08:59.625004 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10926 23:08:59.674104 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10927 23:08:59.729649 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10928 23:08:59.835960
10929 23:08:59.836521
10930 23:08:59.838980 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10931 23:08:59.839651
10932 23:08:59.842081 debian-bullseye-arm64 login: root (automatic login)
10933 23:08:59.842548
10934 23:08:59.842913
10935 23:09:00.231590 Linux debian-bullseye-arm64 6.1.67-cip12-rt7 #1 SMP PREEMPT Wed Dec 27 22:50:56 UTC 2023 aarch64
10936 23:09:00.232144
10937 23:09:00.238446 The programs included with the Debian GNU/Linux system are free software;
10938 23:09:00.244848 the exact distribution terms for each program are described in the
10939 23:09:00.248291 individual files in /usr/share/doc/*/copyright.
10940 23:09:00.248715
10941 23:09:00.254749 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10942 23:09:00.257918 permitted by applicable law.
10943 23:09:00.388885 Matched prompt #10: / #
10945 23:09:00.390294 Setting prompt string to ['/ #']
10946 23:09:00.390736 end: 2.2.5.1 login-action (duration 00:00:28) [common]
10948 23:09:00.391820 end: 2.2.5 auto-login-action (duration 00:00:28) [common]
10949 23:09:00.392263 start: 2.2.6 expect-shell-connection (timeout 00:03:05) [common]
10950 23:09:00.392618 Setting prompt string to ['/ #']
10951 23:09:00.392930 Forcing a shell prompt, looking for ['/ #']
10953 23:09:00.443889 / #
10954 23:09:00.444569 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10955 23:09:00.445032 Waiting using forced prompt support (timeout 00:02:30)
10956 23:09:00.450872
10957 23:09:00.451816 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10958 23:09:00.452353 start: 2.2.7 export-device-env (timeout 00:03:04) [common]
10960 23:09:00.553685 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12395343/extract-nfsrootfs-kd_xsd9a'
10961 23:09:00.560309 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12395343/extract-nfsrootfs-kd_xsd9a'
10963 23:09:00.662208 / # export NFS_SERVER_IP='192.168.201.1'
10964 23:09:00.668746 export NFS_SERVER_IP='192.168.201.1'
10965 23:09:00.669736 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10966 23:09:00.670271 end: 2.2 depthcharge-retry (duration 00:01:56) [common]
10967 23:09:00.670777 end: 2 depthcharge-action (duration 00:01:56) [common]
10968 23:09:00.671379 start: 3 lava-test-retry (timeout 00:01:00) [common]
10969 23:09:00.671884 start: 3.1 lava-test-shell (timeout 00:01:00) [common]
10970 23:09:00.672315 Using namespace: common
10972 23:09:00.773444 / # #
10973 23:09:00.774073 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
10974 23:09:00.779776 #
10975 23:09:00.780502 Using /lava-12395343
10977 23:09:00.881678 / # export SHELL=/bin/sh
10978 23:09:00.888268 export SHELL=/bin/sh
10980 23:09:00.990088 / # . /lava-12395343/environment
10981 23:09:00.996420 . /lava-12395343/environment
10983 23:09:01.105375 / # /lava-12395343/bin/lava-test-runner /lava-12395343/0
10984 23:09:01.106059 Test shell timeout: 10s (minimum of the action and connection timeout)
10985 23:09:01.111864 /lava-12395343/bin/lava-test-runner /lava-12395343/0
10986 23:09:01.419780 + export TESTRUN_ID=0_dmesg
10987 23:09:01.423506 + cd /lava-12395343/0/tests/0_dmesg
10988 23:09:01.426214 + cat uuid
10989 23:09:01.446592 + UUID=12395343_<8>[ 28.268769] <LAVA_SIGNAL_STARTRUN 0_dmesg 12395343_1.6.2.3.1>
10990 23:09:01.447091 1.6.2.3.1
10991 23:09:01.447447 + set +x
10992 23:09:01.448121 Received signal: <STARTRUN> 0_dmesg 12395343_1.6.2.3.1
10993 23:09:01.448533 Starting test lava.0_dmesg (12395343_1.6.2.3.1)
10994 23:09:01.448962 Skipping test definition patterns.
10995 23:09:01.452977 + KERNELCI_LAVA=y /bin/sh /opt/kernelci/dmesg.sh
10996 23:09:01.583101 <8>[ 28.404633] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0>
10997 23:09:01.583893 Received signal: <TESTCASE> TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0
10999 23:09:01.691301 <8>[ 28.512478] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0>
11000 23:09:01.692101 Received signal: <TESTCASE> TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0
11002 23:09:01.787473 <8>[ 28.609247] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0>
11003 23:09:01.787630 + set +x
11004 23:09:01.787881 Received signal: <TESTCASE> TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0
11006 23:09:01.794143 <8>[ 28.619147] <LAVA_SIGNAL_ENDRUN 0_dmesg 12395343_1.6.2.3.1>
11007 23:09:01.794412 Received signal: <ENDRUN> 0_dmesg 12395343_1.6.2.3.1
11008 23:09:01.794508 Ending use of test pattern.
11009 23:09:01.794581 Ending test lava.0_dmesg (12395343_1.6.2.3.1), duration 0.35
11011 23:09:01.798066 <LAVA_TEST_RUNNER EXIT>
11012 23:09:01.798443 ok: lava_test_shell seems to have completed
11013 23:09:01.798594 alert: pass
crit: pass
emerg: pass
11014 23:09:01.798710 end: 3.1 lava-test-shell (duration 00:00:01) [common]
11015 23:09:01.798824 end: 3 lava-test-retry (duration 00:00:01) [common]
11016 23:09:01.798933 start: 4 lava-test-retry (timeout 00:01:00) [common]
11017 23:09:01.799035 start: 4.1 lava-test-shell (timeout 00:01:00) [common]
11018 23:09:01.799115 Using namespace: common
11020 23:09:01.899724 / # #
11021 23:09:01.900328 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
11022 23:09:01.900918 Using /lava-12395343
11024 23:09:02.001999 export SHELL=/bin/sh
11025 23:09:02.002779 #
11027 23:09:02.104342 / # export SHELL=/bin/sh. /lava-12395343/environment
11028 23:09:02.105227
11030 23:09:02.207047 / # . /lava-12395343/environment/lava-12395343/bin/lava-test-runner /lava-12395343/1
11031 23:09:02.207710 Test shell timeout: 10s (minimum of the action and connection timeout)
11032 23:09:02.208584
11033 23:09:02.213292 / # /lava-12395343/bin/lava-test-runner /lava-12395343/1
11034 23:09:02.402530 + export TESTRUN_ID=1_bootrr
11035 23:09:02.405648 + cd /lava-12395343/1/tests/1_bootrr
11036 23:09:02.408794 + cat uuid
11037 23:09:02.422883 + UUID=12395343_1.6.2.3.5
11038 23:09:02.429576 + set<8>[ 29.252058] <LAVA_SIGNAL_STARTRUN 1_bootrr 12395343_1.6.2.3.5>
11039 23:09:02.430008 +x
11040 23:09:02.430606 Received signal: <STARTRUN> 1_bootrr 12395343_1.6.2.3.5
11041 23:09:02.430954 Starting test lava.1_bootrr (12395343_1.6.2.3.5)
11042 23:09:02.431342 Skipping test definition patterns.
11043 23:09:02.443055 + export PATH=/opt/bootrr/libexec/bootrr/helpers:/lava-12395343/1/../bin:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin
11044 23:09:02.446283 + cd /opt/bootrr/libexec/bootrr
11045 23:09:02.446713 + sh helpers/bootrr-auto
11046 23:09:02.557354 /lava-12395343/1/../bin/lava-test-case
11047 23:09:02.603358 <8>[ 29.422393] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=deferred-probe-empty RESULT=pass>
11048 23:09:02.604274 Received signal: <TESTCASE> TEST_CASE_ID=deferred-probe-empty RESULT=pass
11050 23:09:02.654906 /lava-12395343/1/../bin/lava-test-case
11051 23:09:02.695765 <8>[ 29.515006] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=all-cpus-are-online RESULT=pass>
11052 23:09:02.696473 Received signal: <TESTCASE> TEST_CASE_ID=all-cpus-are-online RESULT=pass
11054 23:09:02.724295 /lava-12395343/1/../bin/lava-test-case
11055 23:09:02.763395 <8>[ 29.583671] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm-chip-is-online RESULT=skip>
11056 23:09:02.764091 Received signal: <TESTCASE> TEST_CASE_ID=tpm-chip-is-online RESULT=skip
11058 23:09:02.833712 /lava-12395343/1/../bin/lava-test-case
11059 23:09:02.875460 <8>[ 29.694822] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass>
11060 23:09:02.876269 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass
11062 23:09:02.917823 /lava-12395343/1/../bin/lava-test-case
11063 23:09:02.963700 <8>[ 29.782113] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass>
11064 23:09:02.964855 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass
11066 23:09:02.997787 /lava-12395343/1/../bin/lava-test-case
11067 23:09:03.039987 <8>[ 29.858113] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass>
11068 23:09:03.040930 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass
11070 23:09:03.077864 /lava-12395343/1/../bin/lava-test-case
11071 23:09:03.119802 <8>[ 29.940059] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass>
11072 23:09:03.120587 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass
11074 23:09:03.154912 /lava-12395343/1/../bin/lava-test-case
11075 23:09:03.195653 <8>[ 30.016682] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass>
11076 23:09:03.196347 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass
11078 23:09:03.216535 /lava-12395343/1/../bin/lava-test-case
11079 23:09:03.259450 <8>[ 30.077850] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass>
11080 23:09:03.260261 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass
11082 23:09:03.296459 /lava-12395343/1/../bin/lava-test-case
11083 23:09:03.339705 <8>[ 30.157866] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass>
11084 23:09:03.340398 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass
11086 23:09:03.363137 /lava-12395343/1/../bin/lava-test-case
11087 23:09:03.407644 <8>[ 30.226377] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass>
11088 23:09:03.408357 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass
11090 23:09:03.446190 /lava-12395343/1/../bin/lava-test-case
11091 23:09:03.491432 <8>[ 30.312126] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass>
11092 23:09:03.492176 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass
11094 23:09:03.530121 /lava-12395343/1/../bin/lava-test-case
11095 23:09:03.575236 <8>[ 30.395917] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass>
11096 23:09:03.575934 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass
11098 23:09:03.614462 /lava-12395343/1/../bin/lava-test-case
11099 23:09:03.659652 <8>[ 30.477594] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass>
11100 23:09:03.660380 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass
11102 23:09:03.693913 /lava-12395343/1/../bin/lava-test-case
11103 23:09:03.735080 <8>[ 30.553587] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass>
11104 23:09:03.735777 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass
11106 23:09:03.752727 /lava-12395343/1/../bin/lava-test-case
11107 23:09:03.790453 <8>[ 30.612543] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass>
11108 23:09:03.790821 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass
11110 23:09:03.839533 /lava-12395343/1/../bin/lava-test-case
11111 23:09:03.886789 <8>[ 30.706901] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass>
11112 23:09:03.887498 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass
11114 23:09:03.914805 /lava-12395343/1/../bin/lava-test-case
11115 23:09:03.955410 <8>[ 30.773877] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass>
11116 23:09:03.956208 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass
11118 23:09:03.998566 /lava-12395343/1/../bin/lava-test-case
11119 23:09:04.038910 <8>[ 30.860501] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass>
11120 23:09:04.039694 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass
11122 23:09:04.066103 /lava-12395343/1/../bin/lava-test-case
11123 23:09:04.111158 <8>[ 30.930584] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass>
11124 23:09:04.111873 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass
11126 23:09:04.148934 /lava-12395343/1/../bin/lava-test-case
11127 23:09:04.195361 <8>[ 31.014106] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-probed RESULT=pass>
11128 23:09:04.196137 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-probed RESULT=pass
11130 23:09:04.226879 /lava-12395343/1/../bin/lava-test-case
11131 23:09:04.266927 <8>[ 31.088449] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass>
11132 23:09:04.267758 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass
11134 23:09:04.315842 /lava-12395343/1/../bin/lava-test-case
11135 23:09:04.358982 <8>[ 31.179374] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass>
11136 23:09:04.359762 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass
11138 23:09:04.389372 /lava-12395343/1/../bin/lava-test-case
11139 23:09:04.438782 <8>[ 31.259047] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass>
11140 23:09:04.439571 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass
11142 23:09:04.478564 /lava-12395343/1/../bin/lava-test-case
11143 23:09:04.522934 <8>[ 31.342975] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass>
11144 23:09:04.523631 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass
11146 23:09:04.566670 /lava-12395343/1/../bin/lava-test-case
11147 23:09:04.606942 <8>[ 31.427339] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass>
11148 23:09:04.607725 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass
11150 23:09:04.628874 /lava-12395343/1/../bin/lava-test-case
11151 23:09:04.675199 <8>[ 31.494045] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass>
11152 23:09:04.675956 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass
11154 23:09:04.726106 /lava-12395343/1/../bin/lava-test-case
11155 23:09:04.770600 <8>[ 31.590142] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass>
11156 23:09:04.771310 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass
11158 23:09:04.790360 /lava-12395343/1/../bin/lava-test-case
11159 23:09:04.834962 <8>[ 31.656239] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass>
11160 23:09:04.835771 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass
11162 23:09:04.882684 /lava-12395343/1/../bin/lava-test-case
11163 23:09:04.922899 <8>[ 31.742823] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass>
11164 23:09:04.923730 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass
11166 23:09:04.970885 /lava-12395343/1/../bin/lava-test-case
11167 23:09:05.018923 <8>[ 31.838215] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass>
11168 23:09:05.019742 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass
11170 23:09:05.066698 /lava-12395343/1/../bin/lava-test-case
11171 23:09:05.106607 <8>[ 31.929185] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass>
11172 23:09:05.107438 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass
11174 23:09:05.155632 /lava-12395343/1/../bin/lava-test-case
11175 23:09:05.199032 <8>[ 32.020288] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass>
11176 23:09:05.199853 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass
11178 23:09:05.228069 /lava-12395343/1/../bin/lava-test-case
11179 23:09:05.266686 <8>[ 32.089149] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass>
11180 23:09:05.267467 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass
11182 23:09:05.315763 /lava-12395343/1/../bin/lava-test-case
11183 23:09:05.358477 <8>[ 32.179889] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass>
11184 23:09:05.359289 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass
11186 23:09:05.404519 /lava-12395343/1/../bin/lava-test-case
11187 23:09:05.446714 <8>[ 32.268521] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass>
11188 23:09:05.447539 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass
11190 23:09:05.474984 /lava-12395343/1/../bin/lava-test-case
11191 23:09:05.518712 <8>[ 32.340945] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass>
11192 23:09:05.519572 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass
11194 23:09:05.563604 /lava-12395343/1/../bin/lava-test-case
11195 23:09:05.611190 <8>[ 32.429477] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass>
11196 23:09:05.611890 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass
11198 23:09:05.632684 /lava-12395343/1/../bin/lava-test-case
11199 23:09:05.674469 <8>[ 32.496188] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass>
11200 23:09:05.675316 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass
11202 23:09:05.724501 /lava-12395343/1/../bin/lava-test-case
11203 23:09:05.774685 <8>[ 32.594250] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass>
11204 23:09:05.775538 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass
11206 23:09:05.802272 /lava-12395343/1/../bin/lava-test-case
11207 23:09:05.846863 <8>[ 32.665989] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass>
11208 23:09:05.847726 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass
11210 23:09:05.880268 /lava-12395343/1/../bin/lava-test-case
11211 23:09:05.922779 <8>[ 32.743138] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass>
11212 23:09:05.923579 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass
11214 23:09:05.952170 /lava-12395343/1/../bin/lava-test-case
11215 23:09:05.999220 <8>[ 32.819353] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass>
11216 23:09:05.999996 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass
11218 23:09:06.049049 /lava-12395343/1/../bin/lava-test-case
11219 23:09:06.090879 <8>[ 32.910516] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-probed RESULT=pass>
11220 23:09:06.091661 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-probed RESULT=pass
11222 23:09:06.109746 /lava-12395343/1/../bin/lava-test-case
11223 23:09:06.154782 <8>[ 32.974252] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass>
11224 23:09:06.155686 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass
11226 23:09:06.191609 /lava-12395343/1/../bin/lava-test-case
11227 23:09:06.234698 <8>[ 33.056418] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass>
11228 23:09:06.235393 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass
11230 23:09:06.254690 /lava-12395343/1/../bin/lava-test-case
11231 23:09:06.298477 <8>[ 33.119277] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass>
11232 23:09:06.299187 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass
11234 23:09:06.335746 /lava-12395343/1/../bin/lava-test-case
11235 23:09:06.378579 <8>[ 33.198048] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-probed RESULT=pass>
11236 23:09:06.379280 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-probed RESULT=pass
11238 23:09:06.402616 /lava-12395343/1/../bin/lava-test-case
11239 23:09:06.446828 <8>[ 33.268422] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass>
11240 23:09:06.447629 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass
11242 23:09:06.491820 /lava-12395343/1/../bin/lava-test-case
11243 23:09:06.538595 <8>[ 33.360531] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass>
11244 23:09:06.539366 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass
11246 23:09:06.578149 /lava-12395343/1/../bin/lava-test-case
11247 23:09:06.622825 <8>[ 33.445282] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass>
11248 23:09:06.623684 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass
11250 23:09:06.644547 /lava-12395343/1/../bin/lava-test-case
11251 23:09:06.690493 <8>[ 33.510876] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=pass>
11252 23:09:06.691335 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=pass
11254 23:09:06.740340 /lava-12395343/1/../bin/lava-test-case
11255 23:09:06.782190 <8>[ 33.605045] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=pass>
11256 23:09:06.782969 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=pass
11258 23:09:06.810128 /lava-12395343/1/../bin/lava-test-case
11259 23:09:06.850949 <8>[ 33.673002] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass>
11260 23:09:06.851799 Received signal: <TESTCASE> TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass
11262 23:09:06.899051 /lava-12395343/1/../bin/lava-test-case
11263 23:09:06.942766 <8>[ 33.761958] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass>
11264 23:09:06.943628 Received signal: <TESTCASE> TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass
11266 23:09:06.986801 /lava-12395343/1/../bin/lava-test-case
11267 23:09:07.030582 <8>[ 33.853414] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass>
11268 23:09:07.031401 Received signal: <TESTCASE> TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass
11270 23:09:07.070169 /lava-12395343/1/../bin/lava-test-case
11271 23:09:07.119003 <8>[ 33.938390] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass>
11272 23:09:07.119833 Received signal: <TESTCASE> TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass
11274 23:09:07.168567 /lava-12395343/1/../bin/lava-test-case
11275 23:09:07.210560 <8>[ 34.031047] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass>
11276 23:09:07.211335 Received signal: <TESTCASE> TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass
11278 23:09:07.248455 /lava-12395343/1/../bin/lava-test-case
11279 23:09:07.290657 <8>[ 34.112824] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass>
11280 23:09:07.291436 Received signal: <TESTCASE> TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass
11282 23:09:07.318557 /lava-12395343/1/../bin/lava-test-case
11283 23:09:07.362409 <8>[ 34.181975] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-driver-present RESULT=pass>
11284 23:09:07.363189 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-driver-present RESULT=pass
11286 23:09:07.398103 /lava-12395343/1/../bin/lava-test-case
11287 23:09:07.442719 <8>[ 34.264399] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi1-probed RESULT=pass>
11288 23:09:07.443495 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi1-probed RESULT=pass
11290 23:09:07.486718 /lava-12395343/1/../bin/lava-test-case
11291 23:09:07.530432 <8>[ 34.350828] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi5-probed RESULT=pass>
11292 23:09:07.531204 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi5-probed RESULT=pass
11294 23:09:07.553820 /lava-12395343/1/../bin/lava-test-case
11295 23:09:07.594396 <8>[ 34.416292] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass>
11296 23:09:07.595191 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass
11298 23:09:07.640519 /lava-12395343/1/../bin/lava-test-case
11299 23:09:07.690279 <8>[ 34.509763] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-probed RESULT=pass>
11300 23:09:07.691098 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-probed RESULT=pass
11302 23:09:07.709779 /lava-12395343/1/../bin/lava-test-case
11303 23:09:07.750562 <8>[ 34.573419] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass>
11304 23:09:07.751408 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass
11306 23:09:07.804885 /lava-12395343/1/../bin/lava-test-case
11307 23:09:07.854588 <8>[ 34.673565] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-probed RESULT=pass>
11308 23:09:07.855369 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-probed RESULT=pass
11310 23:09:07.878877 /lava-12395343/1/../bin/lava-test-case
11311 23:09:07.922453 <8>[ 34.745046] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass>
11312 23:09:07.923300 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass
11314 23:09:07.971625 /lava-12395343/1/../bin/lava-test-case
11315 23:09:08.018637 <8>[ 34.837679] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass>
11316 23:09:08.019414 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass
11318 23:09:08.058631 /lava-12395343/1/../bin/lava-test-case
11319 23:09:08.102298 <8>[ 34.922038] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass>
11320 23:09:08.103076 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass
11322 23:09:08.148552 /lava-12395343/1/../bin/lava-test-case
11323 23:09:08.194233 <8>[ 35.016656] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass>
11324 23:09:08.195010 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass
11326 23:09:08.239822 /lava-12395343/1/../bin/lava-test-case
11327 23:09:08.282137 <8>[ 35.103438] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass>
11328 23:09:08.282414 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass
11330 23:09:08.323464 /lava-12395343/1/../bin/lava-test-case
11331 23:09:08.365867 <8>[ 35.186072] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass>
11332 23:09:08.366153 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass
11334 23:09:08.402141 /lava-12395343/1/../bin/lava-test-case
11335 23:09:08.442458 <8>[ 35.263768] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass>
11336 23:09:08.443184 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass
11338 23:09:08.479699 /lava-12395343/1/../bin/lava-test-case
11339 23:09:08.522212 <8>[ 35.343909] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass>
11340 23:09:08.522942 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass
11342 23:09:08.574208 /lava-12395343/1/../bin/lava-test-case
11343 23:09:08.614322 <8>[ 35.434419] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass>
11344 23:09:08.615060 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass
11346 23:09:08.647715 /lava-12395343/1/../bin/lava-test-case
11347 23:09:08.690131 <8>[ 35.509667] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass>
11348 23:09:08.690996 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass
11350 23:09:08.725006 /lava-12395343/1/../bin/lava-test-case
11351 23:09:08.766155 <8>[ 35.587434] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass>
11352 23:09:08.766859 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass
11354 23:09:08.809049 /lava-12395343/1/../bin/lava-test-case
11355 23:09:08.850190 <8>[ 35.672606] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass>
11356 23:09:08.850969 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass
11358 23:09:08.898342 /lava-12395343/1/../bin/lava-test-case
11359 23:09:08.942523 <8>[ 35.764777] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass>
11360 23:09:08.943308 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass
11362 23:09:08.992550 /lava-12395343/1/../bin/lava-test-case
11363 23:09:09.038161 <8>[ 35.859152] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass>
11364 23:09:09.038880 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass
11366 23:09:09.083712 /lava-12395343/1/../bin/lava-test-case
11367 23:09:09.130443 <8>[ 35.952418] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass>
11368 23:09:09.131250 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass
11370 23:09:09.181156 /lava-12395343/1/../bin/lava-test-case
11371 23:09:09.226612 <8>[ 36.047076] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass>
11372 23:09:09.227520 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass
11374 23:09:09.252640 /lava-12395343/1/../bin/lava-test-case
11375 23:09:09.293986 <8>[ 36.113822] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass>
11376 23:09:09.294488 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass
11378 23:09:09.342281 /lava-12395343/1/../bin/lava-test-case
11379 23:09:09.386406 <8>[ 36.208583] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-probed RESULT=pass>
11380 23:09:09.387193 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-probed RESULT=pass
11382 23:09:09.414061 /lava-12395343/1/../bin/lava-test-case
11383 23:09:09.458425 <8>[ 36.279369] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass>
11384 23:09:09.459285 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass
11386 23:09:09.503789 /lava-12395343/1/../bin/lava-test-case
11387 23:09:09.550459 <8>[ 36.370133] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-probed RESULT=pass>
11388 23:09:09.551163 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-probed RESULT=pass
11390 23:09:09.573845 /lava-12395343/1/../bin/lava-test-case
11391 23:09:09.618245 <8>[ 36.439518] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass>
11392 23:09:09.619043 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass
11394 23:09:09.664424 /lava-12395343/1/../bin/lava-test-case
11395 23:09:09.706409 <8>[ 36.527352] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass>
11396 23:09:09.707196 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass
11398 23:09:09.739174 /lava-12395343/1/../bin/lava-test-case
11399 23:09:09.782526 <8>[ 36.604095] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass>
11400 23:09:09.783308 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass
11402 23:09:09.827993 /lava-12395343/1/../bin/lava-test-case
11403 23:09:09.873874 <8>[ 36.695869] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-probed RESULT=pass>
11404 23:09:09.874653 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-probed RESULT=pass
11406 23:09:09.901843 /lava-12395343/1/../bin/lava-test-case
11407 23:09:09.946389 <8>[ 36.767168] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass>
11408 23:09:09.947244 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass
11410 23:09:09.990129 /lava-12395343/1/../bin/lava-test-case
11411 23:09:10.034259 <8>[ 36.855283] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass>
11412 23:09:10.035098 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass
11414 23:09:10.065367 /lava-12395343/1/../bin/lava-test-case
11415 23:09:10.114117 <8>[ 36.935136] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass>
11416 23:09:10.114967 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass
11418 23:09:10.162471 /lava-12395343/1/../bin/lava-test-case
11419 23:09:10.202111 <8>[ 37.025255] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass>
11420 23:09:10.202927 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass
11422 23:09:10.249635 /lava-12395343/1/../bin/lava-test-case
11423 23:09:10.294394 <8>[ 37.114622] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass>
11424 23:09:10.295223 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass
11426 23:09:10.323348 /lava-12395343/1/../bin/lava-test-case
11427 23:09:10.370542 <8>[ 37.189615] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass>
11428 23:09:10.371316 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass
11430 23:09:10.411261 /lava-12395343/1/../bin/lava-test-case
11431 23:09:10.454006 <8>[ 37.276320] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass>
11432 23:09:10.454786 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass
11434 23:09:10.481554 /lava-12395343/1/../bin/lava-test-case
11435 23:09:10.526182 <8>[ 37.347994] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-driver-present RESULT=pass>
11436 23:09:10.526969 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-driver-present RESULT=pass
11438 23:09:10.565519 /lava-12395343/1/../bin/lava-test-case
11439 23:09:10.606044 <8>[ 37.428785] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-probed RESULT=pass>
11440 23:09:10.606758 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-probed RESULT=pass
11442 23:09:10.633588 /lava-12395343/1/../bin/lava-test-case
11443 23:09:10.678247 <8>[ 37.501296] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-driver-present RESULT=pass>
11444 23:09:10.678943 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-driver-present RESULT=pass
11446 23:09:11.753510 /lava-12395343/1/../bin/lava-test-case
11447 23:09:11.801974 <8>[ 38.621605] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-probed RESULT=fail>
11448 23:09:11.802759 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-probed RESULT=fail
11450 23:09:11.820867 /lava-12395343/1/../bin/lava-test-case
11451 23:09:11.866317 <8>[ 38.686177] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-driver-present RESULT=pass>
11452 23:09:11.867044 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-driver-present RESULT=pass
11454 23:09:12.919446 /lava-12395343/1/../bin/lava-test-case
11455 23:09:12.969566 <8>[ 39.790422] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-probed RESULT=fail>
11456 23:09:12.970376 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-probed RESULT=fail
11458 23:09:12.987936 /lava-12395343/1/../bin/lava-test-case
11459 23:09:13.030116 <8>[ 39.851634] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass>
11460 23:09:13.030810 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass
11462 23:09:14.087697 /lava-12395343/1/../bin/lava-test-case
11463 23:09:14.130024 <8>[ 40.950145] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail>
11464 23:09:14.130782 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail
11466 23:09:14.146656 /lava-12395343/1/../bin/lava-test-case
11467 23:09:14.185643 <8>[ 41.008596] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass>
11468 23:09:14.186335 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass
11470 23:09:15.252061 /lava-12395343/1/../bin/lava-test-case
11471 23:09:15.297573 <8>[ 42.118427] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-probed RESULT=fail>
11472 23:09:15.298296 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-probed RESULT=fail
11474 23:09:15.316399 /lava-12395343/1/../bin/lava-test-case
11475 23:09:15.357808 <8>[ 42.178088] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-driver-present RESULT=pass>
11476 23:09:15.358708 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-driver-present RESULT=pass
11478 23:09:16.418876 /lava-12395343/1/../bin/lava-test-case
11479 23:09:16.461798 <8>[ 43.283388] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-3-probed RESULT=fail>
11480 23:09:16.462641 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-3-probed RESULT=fail
11482 23:09:16.488279 /lava-12395343/1/../bin/lava-test-case
11483 23:09:16.533434 <8>[ 43.353684] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass>
11484 23:09:16.534259 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass
11486 23:09:17.207101 <6>[ 44.033888] vpu: disabling
11487 23:09:17.210251 <6>[ 44.034030] vproc2: disabling
11488 23:09:17.213079 <6>[ 44.034085] vproc1: disabling
11489 23:09:17.216656 <6>[ 44.034141] vaud18: disabling
11490 23:09:17.219838 <6>[ 44.034395] vsram_others: disabling
11491 23:09:17.223452 <6>[ 44.034578] va09: disabling
11492 23:09:17.226439 <6>[ 44.034657] vsram_md: disabling
11493 23:09:17.229918 <6>[ 44.034790] Vgpu: disabling
11494 23:09:17.595600 /lava-12395343/1/../bin/lava-test-case
11495 23:09:17.637287 <8>[ 44.460304] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail>
11496 23:09:17.638163 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail
11498 23:09:17.658541 /lava-12395343/1/../bin/lava-test-case
11499 23:09:17.701018 <8>[ 44.524015] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass>
11500 23:09:17.701715 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass
11502 23:09:18.768775 /lava-12395343/1/../bin/lava-test-case
11503 23:09:18.812882 <8>[ 45.636821] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-probed RESULT=fail>
11504 23:09:18.813603 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-probed RESULT=fail
11506 23:09:18.840549 /lava-12395343/1/../bin/lava-test-case
11507 23:09:18.881204 <8>[ 45.704204] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-edp-driver-present RESULT=pass>
11508 23:09:18.881978 Received signal: <TESTCASE> TEST_CASE_ID=panel-edp-driver-present RESULT=pass
11510 23:09:18.908972 /lava-12395343/1/../bin/lava-test-case
11511 23:09:18.953320 <8>[ 45.777282] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass>
11512 23:09:18.954131 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass
11514 23:09:20.017443 /lava-12395343/1/../bin/lava-test-case
11515 23:09:20.065324 <8>[ 46.885513] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail>
11516 23:09:20.066317 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail
11518 23:09:20.091186 /lava-12395343/1/../bin/lava-test-case
11519 23:09:20.133129 <8>[ 46.955904] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass>
11520 23:09:20.134081 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass
11522 23:09:20.182208 /lava-12395343/1/../bin/lava-test-case
11523 23:09:20.229151 <8>[ 47.051235] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-probed RESULT=pass>
11524 23:09:20.229971 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-probed RESULT=pass
11526 23:09:20.255923 /lava-12395343/1/../bin/lava-test-case
11527 23:09:20.300933 <8>[ 47.122723] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass>
11528 23:09:20.301766 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass
11530 23:09:20.349426 /lava-12395343/1/../bin/lava-test-case
11531 23:09:20.393305 <8>[ 47.215255] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass>
11532 23:09:20.394107 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass
11534 23:09:20.436618 /lava-12395343/1/../bin/lava-test-case
11535 23:09:20.477082 <8>[ 47.299770] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass>
11536 23:09:20.477880 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass
11538 23:09:20.524495 /lava-12395343/1/../bin/lava-test-case
11539 23:09:20.564889 <8>[ 47.385746] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass>
11540 23:09:20.565206 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass
11542 23:09:20.586765 /lava-12395343/1/../bin/lava-test-case
11543 23:09:20.620928 <8>[ 47.444880] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass>
11544 23:09:20.621208 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass
11546 23:09:20.656770 /lava-12395343/1/../bin/lava-test-case
11547 23:09:20.692995 <8>[ 47.514501] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass>
11548 23:09:20.693786 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass
11550 23:09:20.739894 /lava-12395343/1/../bin/lava-test-case
11551 23:09:20.781141 <8>[ 47.602265] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass>
11552 23:09:20.781878 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass
11554 23:09:20.807480 /lava-12395343/1/../bin/lava-test-case
11555 23:09:20.853231 <8>[ 47.674107] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass>
11556 23:09:20.854090 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass
11558 23:09:20.900652 /lava-12395343/1/../bin/lava-test-case
11559 23:09:20.945352 <8>[ 47.768383] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass>
11560 23:09:20.946215 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass
11562 23:09:20.973359 /lava-12395343/1/../bin/lava-test-case
11563 23:09:21.016807 <8>[ 47.840384] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass>
11564 23:09:21.017612 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass
11566 23:09:21.062694 /lava-12395343/1/../bin/lava-test-case
11567 23:09:21.113144 <8>[ 47.935421] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass>
11568 23:09:21.114085 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass
11570 23:09:21.141088 /lava-12395343/1/../bin/lava-test-case
11571 23:09:21.185024 <8>[ 48.008393] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass>
11572 23:09:21.185883 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass
11574 23:09:21.235424 /lava-12395343/1/../bin/lava-test-case
11575 23:09:21.276866 <8>[ 48.101391] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass>
11576 23:09:21.277733 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass
11578 23:09:21.307891 /lava-12395343/1/../bin/lava-test-case
11579 23:09:21.357039 <8>[ 48.179392] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass>
11580 23:09:21.357951 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass
11582 23:09:21.405149 /lava-12395343/1/../bin/lava-test-case
11583 23:09:21.452909 <8>[ 48.274061] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass>
11584 23:09:21.453962 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass
11586 23:09:21.485099 /lava-12395343/1/../bin/lava-test-case
11587 23:09:21.529093 <8>[ 48.350641] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass>
11588 23:09:21.529913 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass
11590 23:09:21.573947 /lava-12395343/1/../bin/lava-test-case
11591 23:09:21.620947 <8>[ 48.441654] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-probed RESULT=pass>
11592 23:09:21.621641 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-probed RESULT=pass
11594 23:09:21.644759 /lava-12395343/1/../bin/lava-test-case
11595 23:09:21.689438 <8>[ 48.510202] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass>
11596 23:09:21.690232 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass
11598 23:09:22.750905 /lava-12395343/1/../bin/lava-test-case
11599 23:09:22.797123 <8>[ 49.618178] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-probed RESULT=fail>
11600 23:09:22.797892 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-probed RESULT=fail
11602 23:09:23.861450 /lava-12395343/1/../bin/lava-test-case
11603 23:09:23.900322 <8>[ 50.725373] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-7-probed RESULT=fail>
11604 23:09:23.900786 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-7-probed RESULT=fail
11606 23:09:23.919047 /lava-12395343/1/../bin/lava-test-case
11607 23:09:23.960551 <8>[ 50.784383] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-driver-present RESULT=pass>
11608 23:09:23.961324 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-driver-present RESULT=pass
11610 23:09:24.000827 /lava-12395343/1/../bin/lava-test-case
11611 23:09:24.044522 <8>[ 50.867022] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-probed RESULT=pass>
11612 23:09:24.045290 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-probed RESULT=pass
11614 23:09:24.062512 /lava-12395343/1/../bin/lava-test-case
11615 23:09:24.104850 <8>[ 50.926377] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass>
11616 23:09:24.105597 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass
11618 23:09:24.142195 /lava-12395343/1/../bin/lava-test-case
11619 23:09:24.188737 <8>[ 51.010188] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass>
11620 23:09:24.189590 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass
11622 23:09:24.214114 /lava-12395343/1/../bin/lava-test-case
11623 23:09:24.260616 <8>[ 51.082644] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-driver-present RESULT=pass>
11624 23:09:24.261308 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-driver-present RESULT=pass
11626 23:09:24.294029 /lava-12395343/1/../bin/lava-test-case
11627 23:09:24.340639 <8>[ 51.163443] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-probed RESULT=pass>
11628 23:09:24.341469 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-probed RESULT=pass
11630 23:09:24.367105 /lava-12395343/1/../bin/lava-test-case
11631 23:09:24.408248 <8>[ 51.233193] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass>
11632 23:09:24.408989 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass
11634 23:09:24.447096 /lava-12395343/1/../bin/lava-test-case
11635 23:09:24.488284 <8>[ 51.311180] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass>
11636 23:09:24.488598 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass
11638 23:09:24.516579 /lava-12395343/1/../bin/lava-test-case
11639 23:09:24.559865 <8>[ 51.382074] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass>
11640 23:09:24.560216 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass
11642 23:09:24.600367 /lava-12395343/1/../bin/lava-test-case
11643 23:09:24.644715 <8>[ 51.466921] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-probed RESULT=pass>
11644 23:09:24.645549 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-probed RESULT=pass
11646 23:09:24.662790 /lava-12395343/1/../bin/lava-test-case
11647 23:09:24.704309 <8>[ 51.526483] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass>
11648 23:09:24.705076 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass
11650 23:09:24.748751 /lava-12395343/1/../bin/lava-test-case
11651 23:09:24.792947 <8>[ 51.616286] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass>
11652 23:09:24.793798 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass
11654 23:09:24.812023 /lava-12395343/1/../bin/lava-test-case
11655 23:09:24.856559 <8>[ 51.679417] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass>
11656 23:09:24.857392 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass
11658 23:09:24.905165 /lava-12395343/1/../bin/lava-test-case
11659 23:09:24.952577 <8>[ 51.774411] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-probed RESULT=pass>
11660 23:09:24.953274 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-probed RESULT=pass
11662 23:09:24.979572 /lava-12395343/1/../bin/lava-test-case
11663 23:09:25.024228 <8>[ 51.848107] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass>
11664 23:09:25.024905 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass
11666 23:09:25.065520 /lava-12395343/1/../bin/lava-test-case
11667 23:09:25.108405 <8>[ 51.932465] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-probed RESULT=pass>
11668 23:09:25.109179 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-probed RESULT=pass
11670 23:09:25.132231 /lava-12395343/1/../bin/lava-test-case
11671 23:09:25.176791 <8>[ 51.999324] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-driver-present RESULT=pass>
11672 23:09:25.177601 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-driver-present RESULT=pass
11674 23:09:25.212564 /lava-12395343/1/../bin/lava-test-case
11675 23:09:25.260445 <8>[ 52.082072] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-probed RESULT=pass>
11676 23:09:25.261219 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-probed RESULT=pass
11678 23:09:25.287694 /lava-12395343/1/../bin/lava-test-case
11679 23:09:25.336682 <8>[ 52.159762] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass>
11680 23:09:25.337500 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass
11682 23:09:25.386038 /lava-12395343/1/../bin/lava-test-case
11683 23:09:25.428701 <8>[ 52.250773] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass>
11684 23:09:25.429399 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass
11686 23:09:26.467660 /lava-12395343/1/../bin/lava-test-case
11687 23:09:26.512201 <8>[ 53.335602] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail>
11688 23:09:26.512891 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail
11690 23:09:27.550216 /lava-12395343/1/../bin/lava-test-case
11691 23:09:27.596431 <8>[ 54.418764] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked>
11692 23:09:27.597218 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked
11693 23:09:27.597687 Bad test result: blocked
11694 23:09:27.623701 /lava-12395343/1/../bin/lava-test-case
11695 23:09:27.663641 <8>[ 54.488127] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-driver-present RESULT=pass>
11696 23:09:27.664005 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-driver-present RESULT=pass
11698 23:09:28.716780 /lava-12395343/1/../bin/lava-test-case
11699 23:09:28.764347 <8>[ 55.586924] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-probed RESULT=fail>
11700 23:09:28.765143 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-probed RESULT=fail
11702 23:09:28.783887 /lava-12395343/1/../bin/lava-test-case
11703 23:09:28.823739 <8>[ 55.649190] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo-driver-present RESULT=pass>
11704 23:09:28.824458 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo-driver-present RESULT=pass
11706 23:09:28.869445 /lava-12395343/1/../bin/lava-test-case
11707 23:09:28.911906 <8>[ 55.736221] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo0-probed RESULT=pass>
11708 23:09:28.912287 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo0-probed RESULT=pass
11710 23:09:28.942816 /lava-12395343/1/../bin/lava-test-case
11711 23:09:28.983558 <8>[ 55.807589] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo1-probed RESULT=pass>
11712 23:09:28.984061 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo1-probed RESULT=pass
11714 23:09:29.009531 /lava-12395343/1/../bin/lava-test-case
11715 23:09:29.052268 <8>[ 55.875406] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass>
11716 23:09:29.053132 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass
11718 23:09:29.096159 /lava-12395343/1/../bin/lava-test-case
11719 23:09:29.135567 <8>[ 55.961296] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-probed RESULT=pass>
11720 23:09:29.136379 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-probed RESULT=pass
11722 23:09:29.162988 /lava-12395343/1/../bin/lava-test-case
11723 23:09:29.208389 <8>[ 56.030521] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-driver-present RESULT=pass>
11724 23:09:29.209214 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-driver-present RESULT=pass
11726 23:09:30.261613 /lava-12395343/1/../bin/lava-test-case
11727 23:09:30.311825 <8>[ 57.135126] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-probed RESULT=fail>
11728 23:09:30.312596 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-probed RESULT=fail
11730 23:09:30.335359 /lava-12395343/1/../bin/lava-test-case
11731 23:09:30.379970 <8>[ 57.203715] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-driver-present RESULT=pass>
11732 23:09:30.380663 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-driver-present RESULT=pass
11734 23:09:31.436375 /lava-12395343/1/../bin/lava-test-case
11735 23:09:31.480060 <8>[ 58.303808] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-probed RESULT=fail>
11736 23:09:31.480905 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-probed RESULT=fail
11738 23:09:31.506557 /lava-12395343/1/../bin/lava-test-case
11739 23:09:31.552396 <8>[ 58.374603] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-driver-present RESULT=pass>
11740 23:09:31.553240 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-driver-present RESULT=pass
11742 23:09:32.618098 /lava-12395343/1/../bin/lava-test-case
11743 23:09:32.655569 <8>[ 59.480270] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-probed RESULT=fail>
11744 23:09:32.655845 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-probed RESULT=fail
11746 23:09:32.679407 /lava-12395343/1/../bin/lava-test-case
11747 23:09:32.715949 <8>[ 59.538851] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass>
11748 23:09:32.716252 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass
11750 23:09:33.770146 /lava-12395343/1/../bin/lava-test-case
11751 23:09:33.812223 <8>[ 60.636437] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail>
11752 23:09:33.813031 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail
11754 23:09:33.840325 /lava-12395343/1/../bin/lava-test-case
11755 23:09:33.884676 <8>[ 60.709520] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb-driver-present RESULT=pass>
11756 23:09:33.885472 Received signal: <TESTCASE> TEST_CASE_ID=btusb-driver-present RESULT=pass
11758 23:09:33.931664 /lava-12395343/1/../bin/lava-test-case
11759 23:09:33.980165 <8>[ 60.802535] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb0-probed RESULT=pass>
11760 23:09:33.980977 Received signal: <TESTCASE> TEST_CASE_ID=btusb0-probed RESULT=pass
11762 23:09:34.024574 /lava-12395343/1/../bin/lava-test-case
11763 23:09:34.068402 <8>[ 60.891463] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb1-probed RESULT=pass>
11764 23:09:34.069355 Received signal: <TESTCASE> TEST_CASE_ID=btusb1-probed RESULT=pass
11766 23:09:34.097356 /lava-12395343/1/../bin/lava-test-case
11767 23:09:34.140653 <8>[ 60.965587] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass>
11768 23:09:34.141526 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass
11770 23:09:34.184539 /lava-12395343/1/../bin/lava-test-case
11771 23:09:34.228467 <8>[ 61.051398] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-probed RESULT=pass>
11772 23:09:34.229285 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-probed RESULT=pass
11774 23:09:34.253552 /lava-12395343/1/../bin/lava-test-case
11775 23:09:34.296480 <8>[ 61.119701] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass>
11776 23:09:34.297167 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass
11778 23:09:34.340684 /lava-12395343/1/../bin/lava-test-case
11779 23:09:34.388643 <8>[ 61.212712] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-probed RESULT=pass>
11780 23:09:34.389451 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-probed RESULT=pass
11782 23:09:34.417029 /lava-12395343/1/../bin/lava-test-case
11783 23:09:34.464008 <8>[ 61.287172] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass>
11784 23:09:34.464737 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass
11786 23:09:34.518145 /lava-12395343/1/../bin/lava-test-case
11787 23:09:34.564199 <8>[ 61.387347] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=pass>
11788 23:09:34.565060 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=pass
11790 23:09:34.568875 + set +x
11791 23:09:34.575012 <8>[ 61.401150] <LAVA_SIGNAL_ENDRUN 1_bootrr 12395343_1.6.2.3.5>
11792 23:09:34.575805 Received signal: <ENDRUN> 1_bootrr 12395343_1.6.2.3.5
11793 23:09:34.576251 Ending use of test pattern.
11794 23:09:34.576662 Ending test lava.1_bootrr (12395343_1.6.2.3.5), duration 32.15
11796 23:09:34.580006 <LAVA_TEST_RUNNER EXIT>
11797 23:09:34.580670 ok: lava_test_shell seems to have completed
11798 23:09:34.585792 all-cpus-are-online: pass
anx7625-3-probed: fail
anx7625-7-probed: fail
anx7625-driver-present: pass
btusb-driver-present: pass
btusb0-probed: pass
btusb1-probed: pass
clk-mt8192-apmixedsys-probed: pass
clk-mt8192-aud-driver-present: pass
clk-mt8192-aud-probed: pass
clk-mt8192-cam-driver-present: pass
clk-mt8192-cam-probed: pass
clk-mt8192-cam_rawa-probed: pass
clk-mt8192-cam_rawb-probed: pass
clk-mt8192-cam_rawc-probed: pass
clk-mt8192-driver-present: pass
clk-mt8192-img-driver-present: pass
clk-mt8192-img-probed: pass
clk-mt8192-img2-probed: pass
clk-mt8192-imp_iic_wrap-driver-present: pass
clk-mt8192-imp_iic_wrap_e-probed: pass
clk-mt8192-imp_iic_wrap_n-probed: pass
clk-mt8192-imp_iic_wrap_s-probed: pass
clk-mt8192-imp_iic_wrap_ws-probed: pass
clk-mt8192-infracfg-probed: pass
clk-mt8192-ipe-driver-present: pass
clk-mt8192-ipe-probed: pass
clk-mt8192-mdp-driver-present: pass
clk-mt8192-mdp-probed: pass
clk-mt8192-mfg-driver-present: pass
clk-mt8192-mfg-probed: pass
clk-mt8192-mm-driver-present: pass
clk-mt8192-mm-probed: pass
clk-mt8192-msdc-driver-present: pass
clk-mt8192-msdc-probed: pass
clk-mt8192-pericfg-probed: pass
clk-mt8192-topckgen-probed: pass
clk-mt8192-vdec-driver-present: pass
clk-mt8192-vdec-probed: pass
clk-mt8192-vdec_soc-probed: pass
clk-mt8192-venc-driver-present: pass
clk-mt8192-venc-probed: pass
cros-ec-i2c-tunnel-driver-present: pass
cros-ec-i2c-tunnel-probed: pass
cros-ec-keyb-driver-present: pass
cros-ec-keyb-probed: pass
cros-ec-pwm-driver-present: pass
cros-ec-pwm-probed: pass
cros-ec-regulator-driver-present: pass
cros-ec-regulator0-probed: pass
cros-ec-regulator1-probed: pass
cros-ec-rpmsg-driver-present: pass
cros-ec-rpmsg-probed: pass
cros-ec-spi-driver-present: pass
cros-ec-spi-probed: pass
cros-ec-typec-driver-present: pass
cros-ec-typec-probed: pass
deferred-probe-empty: pass
dmic-codec-driver-present: pass
dmic-codec-probed: fail
elan_i2c-driver-present: pass
elan_i2c-probed: fail
elants_i2c-driver-present: pass
elants_i2c-probed: fail
i2c-mt65xx-driver-present: pass
i2c0-mt65xx-probed: pass
i2c1-mt65xx-probed: pass
i2c2-mt65xx-probed: pass
i2c3-mt65xx-probed: pass
i2c7-mt65xx-probed: pass
leds_pwm-driver-present: pass
leds_pwm-probed: pass
mediatek,efuse-driver-present: pass
mediatek,efuse-probed: pass
mediatek-disp-aal-driver-present: pass
mediatek-disp-aal-probed: pass
mediatek-disp-ccorr-driver-present: pass
mediatek-disp-ccorr-probed: pass
mediatek-disp-color-driver-present: pass
mediatek-disp-color-probed: pass
mediatek-disp-gamma-driver-present: pass
mediatek-disp-gamma-probed: pass
mediatek-disp-ovl-driver-present: pass
mediatek-disp-ovl0-probed: pass
mediatek-disp-ovl2l0-probed: pass
mediatek-disp-ovl2l2-probed: pass
mediatek-disp-pwm-driver-present: pass
mediatek-disp-pwm-probed: fail
mediatek-disp-rdma-driver-present: pass
mediatek-disp-rdma0-probed: pass
mediatek-disp-rdma4-probed: pass
mediatek-dpi-driver-present: pass
mediatek-dpi-probed: fail
mediatek-drm-driver-present: pass
mediatek-drm-probed: pass
mediatek-mipi-tx-driver-present: pass
mediatek-mipi-tx-probed: fail
mediatek-mutex-driver-present: pass
mediatek-mutex-probed: pass
mt-pmic-pwrap-driver-present: pass
mt-pmic-pwrap-probed: pass
mt6315-regulator-driver-present: pass
mt6315-regulator6-probed: pass
mt6315-regulator7-probed: pass
mt6577-uart-driver-present: pass
mt6577-uart-probed: pass
mt7921e-driver-present: pass
mt7921e-probed: pass
mt8192-audio-driver-present: pass
mt8192-audio-probed: pass
mt8192-pinctrl-driver-present: pass
mt8192-pinctrl-probed: pass
mt8192_mt6359-driver-present: pass
mt8192_mt6359-probed: fail
mtk-cpufreq-hw-driver-present: pass
mtk-cpufreq-hw-probed: pass
mtk-dsi-driver-present: pass
mtk-dsi-probed: fail
mtk-iommu-driver-present: pass
mtk-iommu-probed: pass
mtk-mmsys-driver-present: pass
mtk-mmsys-probed: pass
mtk-msdc-driver-present: pass
mtk-msdc-probed: pass
mtk-pcie-gen3-driver-present: pass
mtk-pcie-gen3-probed: pass
mtk-power-controller-driver-present: pass
mtk-power-controller-probed: pass
mtk-scp-driver-present: pass
mtk-scp-probed: pass
mtk-smi-common-driver-present: pass
mtk-smi-common-probed: pass
mtk-smi-larb-driver-present: pass
mtk-smi-larb0-probed: pass
mtk-smi-larb1-probed: pass
mtk-smi-larb11-probed: pass
mtk-smi-larb13-probed: pass
mtk-smi-larb14-probed: pass
mtk-smi-larb16-probed: pass
mtk-smi-larb17-probed: pass
mtk-smi-larb18-probed: pass
mtk-smi-larb19-probed: pass
mtk-smi-larb2-probed: pass
mtk-smi-larb20-probed: pass
mtk-smi-larb4-probed: pass
mtk-smi-larb5-probed: pass
mtk-smi-larb7-probed: pass
mtk-smi-larb9-probed: pass
mtk-spi-driver-present: pass
mtk-spi-nor-driver-present: pass
mtk-spi-nor-probed: pass
mtk-spi1-probed: pass
mtk-spi5-probed: pass
mtk-tphy-driver-present: pass
mtk-tphy-probed: pass
mtk-vcodec-dec-driver-present: fail
mtk-vcodec-enc-driver-present: pass
mtk-vcodec-enc-probed: pass
mtk-wdt-driver-present: pass
mtk-wdt-probed: pass
panel-edp-driver-present: pass
panel-simple-dp-aux-driver-present: pass
panel-simple-dp-aux-probed: fail
panfrost-driver-present: pass
panfrost-probed: fail
pwm-backlight-driver-present: pass
pwm-backlight-probed: fail
rt1015p-driver-present: pass
rt1015p-probed: fail
rt5682-driver-present: pass
rt5682-probed: fail
sbs-battery-driver-present: pass
sbs-battery-probed: pass
spmi-mtk-driver-present: pass
spmi-mtk-probed: pass
tpm-chip-is-online: skip
tpm_tis_spi-driver-present: pass
tpm_tis_spi-probed: pass
uvcvideo-driver-present: pass
uvcvideo0-probed: pass
uvcvideo1-probed: pass
xhci-mtk-driver-present: pass
xhci-mtk-probed: pass
11799 23:09:34.586498 end: 4.1 lava-test-shell (duration 00:00:33) [common]
11800 23:09:34.586935 end: 4 lava-test-retry (duration 00:00:33) [common]
11801 23:09:34.587388 start: 5 finalize (timeout 00:07:04) [common]
11802 23:09:34.587841 start: 5.1 power-off (timeout 00:00:30) [common]
11803 23:09:34.588565 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=off'
11804 23:09:34.708100 >> Command sent successfully.
11805 23:09:34.712012 Returned 0 in 0 seconds
11806 23:09:34.812957 end: 5.1 power-off (duration 00:00:00) [common]
11808 23:09:34.814805 start: 5.2 read-feedback (timeout 00:07:04) [common]
11809 23:09:34.816240 Listened to connection for namespace 'common' for up to 1s
11810 23:09:35.816694 Finalising connection for namespace 'common'
11811 23:09:35.816883 Disconnecting from shell: Finalise
11812 23:09:35.816985 / #
11813 23:09:35.917316 end: 5.2 read-feedback (duration 00:00:01) [common]
11814 23:09:35.917512 end: 5 finalize (duration 00:00:01) [common]
11815 23:09:35.917670 Cleaning after the job
11816 23:09:35.917788 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12395343/tftp-deploy-8402ppx3/ramdisk
11817 23:09:35.920374 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12395343/tftp-deploy-8402ppx3/kernel
11818 23:09:35.932938 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12395343/tftp-deploy-8402ppx3/dtb
11819 23:09:35.933129 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12395343/tftp-deploy-8402ppx3/nfsrootfs
11820 23:09:36.007307 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12395343/tftp-deploy-8402ppx3/modules
11821 23:09:36.014805 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12395343
11822 23:09:36.390255 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12395343
11823 23:09:36.390443 Job finished correctly