Boot log: mt8192-asurada-spherion-r0

    1 23:05:51.982845  lava-dispatcher, installed at version: 2023.10
    2 23:05:51.983084  start: 0 validate
    3 23:05:51.983233  Start time: 2023-12-27 23:05:51.983224+00:00 (UTC)
    4 23:05:51.983364  Using caching service: 'http://localhost/cache/?uri=%s'
    5 23:05:51.983500  Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-cros-ec%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
    6 23:05:52.250050  Using caching service: 'http://localhost/cache/?uri=%s'
    7 23:05:52.250235  Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.66-cip11-rt6-10-g38253b8903b4%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
    8 23:05:52.508293  Using caching service: 'http://localhost/cache/?uri=%s'
    9 23:05:52.508471  Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.66-cip11-rt6-10-g38253b8903b4%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
   10 23:06:12.485511  Using caching service: 'http://localhost/cache/?uri=%s'
   11 23:06:12.486267  Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.66-cip11-rt6-10-g38253b8903b4%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
   12 23:06:13.004402  validate duration: 21.02
   14 23:06:13.005708  start: 1 tftp-deploy (timeout 00:10:00) [common]
   15 23:06:13.006252  start: 1.1 download-retry (timeout 00:10:00) [common]
   16 23:06:13.006785  start: 1.1.1 http-download (timeout 00:10:00) [common]
   17 23:06:13.007436  Not decompressing ramdisk as can be used compressed.
   18 23:06:13.007986  downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-cros-ec/20230623.0/arm64/rootfs.cpio.gz
   19 23:06:13.008370  saving as /var/lib/lava/dispatcher/tmp/12395354/tftp-deploy-z6ayw89f/ramdisk/rootfs.cpio.gz
   20 23:06:13.008735  total size: 34390042 (32 MB)
   21 23:06:17.997622  progress   0 % (0 MB)
   22 23:06:18.007835  progress   5 % (1 MB)
   23 23:06:18.016836  progress  10 % (3 MB)
   24 23:06:18.025750  progress  15 % (4 MB)
   25 23:06:18.034630  progress  20 % (6 MB)
   26 23:06:18.043513  progress  25 % (8 MB)
   27 23:06:18.052190  progress  30 % (9 MB)
   28 23:06:18.061185  progress  35 % (11 MB)
   29 23:06:18.070007  progress  40 % (13 MB)
   30 23:06:18.079055  progress  45 % (14 MB)
   31 23:06:18.088017  progress  50 % (16 MB)
   32 23:06:18.097129  progress  55 % (18 MB)
   33 23:06:18.106021  progress  60 % (19 MB)
   34 23:06:18.115067  progress  65 % (21 MB)
   35 23:06:18.123920  progress  70 % (22 MB)
   36 23:06:18.132876  progress  75 % (24 MB)
   37 23:06:18.141670  progress  80 % (26 MB)
   38 23:06:18.150670  progress  85 % (27 MB)
   39 23:06:18.159368  progress  90 % (29 MB)
   40 23:06:18.168073  progress  95 % (31 MB)
   41 23:06:18.176655  progress 100 % (32 MB)
   42 23:06:18.176834  32 MB downloaded in 5.17 s (6.35 MB/s)
   43 23:06:18.176986  end: 1.1.1 http-download (duration 00:00:05) [common]
   45 23:06:18.177227  end: 1.1 download-retry (duration 00:00:05) [common]
   46 23:06:18.177321  start: 1.2 download-retry (timeout 00:09:55) [common]
   47 23:06:18.177407  start: 1.2.1 http-download (timeout 00:09:55) [common]
   48 23:06:18.177541  downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.66-cip11-rt6-10-g38253b8903b4/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
   49 23:06:18.177611  saving as /var/lib/lava/dispatcher/tmp/12395354/tftp-deploy-z6ayw89f/kernel/Image
   50 23:06:18.177676  total size: 50024960 (47 MB)
   51 23:06:18.177738  No compression specified
   52 23:06:18.178844  progress   0 % (0 MB)
   53 23:06:18.192073  progress   5 % (2 MB)
   54 23:06:18.205256  progress  10 % (4 MB)
   55 23:06:18.218025  progress  15 % (7 MB)
   56 23:06:18.231256  progress  20 % (9 MB)
   57 23:06:18.244457  progress  25 % (11 MB)
   58 23:06:18.257746  progress  30 % (14 MB)
   59 23:06:18.271209  progress  35 % (16 MB)
   60 23:06:18.284318  progress  40 % (19 MB)
   61 23:06:18.297390  progress  45 % (21 MB)
   62 23:06:18.310595  progress  50 % (23 MB)
   63 23:06:18.323563  progress  55 % (26 MB)
   64 23:06:18.336556  progress  60 % (28 MB)
   65 23:06:18.349572  progress  65 % (31 MB)
   66 23:06:18.362482  progress  70 % (33 MB)
   67 23:06:18.375666  progress  75 % (35 MB)
   68 23:06:18.388953  progress  80 % (38 MB)
   69 23:06:18.402066  progress  85 % (40 MB)
   70 23:06:18.415097  progress  90 % (42 MB)
   71 23:06:18.428091  progress  95 % (45 MB)
   72 23:06:18.440997  progress 100 % (47 MB)
   73 23:06:18.441240  47 MB downloaded in 0.26 s (181.01 MB/s)
   74 23:06:18.441399  end: 1.2.1 http-download (duration 00:00:00) [common]
   76 23:06:18.441633  end: 1.2 download-retry (duration 00:00:00) [common]
   77 23:06:18.441728  start: 1.3 download-retry (timeout 00:09:55) [common]
   78 23:06:18.441820  start: 1.3.1 http-download (timeout 00:09:55) [common]
   79 23:06:18.441966  downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.66-cip11-rt6-10-g38253b8903b4/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
   80 23:06:18.442038  saving as /var/lib/lava/dispatcher/tmp/12395354/tftp-deploy-z6ayw89f/dtb/mt8192-asurada-spherion-r0.dtb
   81 23:06:18.442100  total size: 47278 (0 MB)
   82 23:06:18.442164  No compression specified
   83 23:06:18.443349  progress  69 % (0 MB)
   84 23:06:18.443630  progress 100 % (0 MB)
   85 23:06:18.443787  0 MB downloaded in 0.00 s (26.77 MB/s)
   86 23:06:18.443912  end: 1.3.1 http-download (duration 00:00:00) [common]
   88 23:06:18.444135  end: 1.3 download-retry (duration 00:00:00) [common]
   89 23:06:18.444220  start: 1.4 download-retry (timeout 00:09:55) [common]
   90 23:06:18.444306  start: 1.4.1 http-download (timeout 00:09:55) [common]
   91 23:06:18.444427  downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.66-cip11-rt6-10-g38253b8903b4/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
   92 23:06:18.444497  saving as /var/lib/lava/dispatcher/tmp/12395354/tftp-deploy-z6ayw89f/modules/modules.tar
   93 23:06:18.444561  total size: 8633892 (8 MB)
   94 23:06:18.444622  Using unxz to decompress xz
   95 23:06:18.448953  progress   0 % (0 MB)
   96 23:06:18.470833  progress   5 % (0 MB)
   97 23:06:18.495466  progress  10 % (0 MB)
   98 23:06:18.520577  progress  15 % (1 MB)
   99 23:06:18.545493  progress  20 % (1 MB)
  100 23:06:18.571118  progress  25 % (2 MB)
  101 23:06:18.600485  progress  30 % (2 MB)
  102 23:06:18.626327  progress  35 % (2 MB)
  103 23:06:18.650690  progress  40 % (3 MB)
  104 23:06:18.675786  progress  45 % (3 MB)
  105 23:06:18.702286  progress  50 % (4 MB)
  106 23:06:18.727785  progress  55 % (4 MB)
  107 23:06:18.755404  progress  60 % (4 MB)
  108 23:06:18.781939  progress  65 % (5 MB)
  109 23:06:18.808182  progress  70 % (5 MB)
  110 23:06:18.832729  progress  75 % (6 MB)
  111 23:06:18.860550  progress  80 % (6 MB)
  112 23:06:18.888093  progress  85 % (7 MB)
  113 23:06:18.917286  progress  90 % (7 MB)
  114 23:06:18.947931  progress  95 % (7 MB)
  115 23:06:18.976237  progress 100 % (8 MB)
  116 23:06:18.982299  8 MB downloaded in 0.54 s (15.31 MB/s)
  117 23:06:18.982657  end: 1.4.1 http-download (duration 00:00:01) [common]
  119 23:06:18.982925  end: 1.4 download-retry (duration 00:00:01) [common]
  120 23:06:18.983051  start: 1.5 prepare-tftp-overlay (timeout 00:09:54) [common]
  121 23:06:18.983215  start: 1.5.1 extract-nfsrootfs (timeout 00:09:54) [common]
  122 23:06:18.983394  end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
  123 23:06:18.983506  start: 1.5.2 lava-overlay (timeout 00:09:54) [common]
  124 23:06:18.983848  [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12395354/lava-overlay-gte7n27_
  125 23:06:18.984052  makedir: /var/lib/lava/dispatcher/tmp/12395354/lava-overlay-gte7n27_/lava-12395354/bin
  126 23:06:18.984161  makedir: /var/lib/lava/dispatcher/tmp/12395354/lava-overlay-gte7n27_/lava-12395354/tests
  127 23:06:18.984261  makedir: /var/lib/lava/dispatcher/tmp/12395354/lava-overlay-gte7n27_/lava-12395354/results
  128 23:06:18.984381  Creating /var/lib/lava/dispatcher/tmp/12395354/lava-overlay-gte7n27_/lava-12395354/bin/lava-add-keys
  129 23:06:18.984577  Creating /var/lib/lava/dispatcher/tmp/12395354/lava-overlay-gte7n27_/lava-12395354/bin/lava-add-sources
  130 23:06:18.984726  Creating /var/lib/lava/dispatcher/tmp/12395354/lava-overlay-gte7n27_/lava-12395354/bin/lava-background-process-start
  131 23:06:18.984887  Creating /var/lib/lava/dispatcher/tmp/12395354/lava-overlay-gte7n27_/lava-12395354/bin/lava-background-process-stop
  132 23:06:18.985060  Creating /var/lib/lava/dispatcher/tmp/12395354/lava-overlay-gte7n27_/lava-12395354/bin/lava-common-functions
  133 23:06:18.985204  Creating /var/lib/lava/dispatcher/tmp/12395354/lava-overlay-gte7n27_/lava-12395354/bin/lava-echo-ipv4
  134 23:06:18.985345  Creating /var/lib/lava/dispatcher/tmp/12395354/lava-overlay-gte7n27_/lava-12395354/bin/lava-install-packages
  135 23:06:18.985491  Creating /var/lib/lava/dispatcher/tmp/12395354/lava-overlay-gte7n27_/lava-12395354/bin/lava-installed-packages
  136 23:06:18.985686  Creating /var/lib/lava/dispatcher/tmp/12395354/lava-overlay-gte7n27_/lava-12395354/bin/lava-os-build
  137 23:06:18.985837  Creating /var/lib/lava/dispatcher/tmp/12395354/lava-overlay-gte7n27_/lava-12395354/bin/lava-probe-channel
  138 23:06:18.985966  Creating /var/lib/lava/dispatcher/tmp/12395354/lava-overlay-gte7n27_/lava-12395354/bin/lava-probe-ip
  139 23:06:18.986099  Creating /var/lib/lava/dispatcher/tmp/12395354/lava-overlay-gte7n27_/lava-12395354/bin/lava-target-ip
  140 23:06:18.986228  Creating /var/lib/lava/dispatcher/tmp/12395354/lava-overlay-gte7n27_/lava-12395354/bin/lava-target-mac
  141 23:06:18.986376  Creating /var/lib/lava/dispatcher/tmp/12395354/lava-overlay-gte7n27_/lava-12395354/bin/lava-target-storage
  142 23:06:18.986534  Creating /var/lib/lava/dispatcher/tmp/12395354/lava-overlay-gte7n27_/lava-12395354/bin/lava-test-case
  143 23:06:18.986668  Creating /var/lib/lava/dispatcher/tmp/12395354/lava-overlay-gte7n27_/lava-12395354/bin/lava-test-event
  144 23:06:18.986827  Creating /var/lib/lava/dispatcher/tmp/12395354/lava-overlay-gte7n27_/lava-12395354/bin/lava-test-feedback
  145 23:06:18.986953  Creating /var/lib/lava/dispatcher/tmp/12395354/lava-overlay-gte7n27_/lava-12395354/bin/lava-test-raise
  146 23:06:18.987080  Creating /var/lib/lava/dispatcher/tmp/12395354/lava-overlay-gte7n27_/lava-12395354/bin/lava-test-reference
  147 23:06:18.987211  Creating /var/lib/lava/dispatcher/tmp/12395354/lava-overlay-gte7n27_/lava-12395354/bin/lava-test-runner
  148 23:06:18.987404  Creating /var/lib/lava/dispatcher/tmp/12395354/lava-overlay-gte7n27_/lava-12395354/bin/lava-test-set
  149 23:06:18.987560  Creating /var/lib/lava/dispatcher/tmp/12395354/lava-overlay-gte7n27_/lava-12395354/bin/lava-test-shell
  150 23:06:18.987690  Updating /var/lib/lava/dispatcher/tmp/12395354/lava-overlay-gte7n27_/lava-12395354/bin/lava-install-packages (oe)
  151 23:06:18.987845  Updating /var/lib/lava/dispatcher/tmp/12395354/lava-overlay-gte7n27_/lava-12395354/bin/lava-installed-packages (oe)
  152 23:06:18.988009  Creating /var/lib/lava/dispatcher/tmp/12395354/lava-overlay-gte7n27_/lava-12395354/environment
  153 23:06:18.988143  LAVA metadata
  154 23:06:18.988247  - LAVA_JOB_ID=12395354
  155 23:06:18.988313  - LAVA_DISPATCHER_IP=192.168.201.1
  156 23:06:18.988420  start: 1.5.2.1 lava-vland-overlay (timeout 00:09:54) [common]
  157 23:06:18.988493  skipped lava-vland-overlay
  158 23:06:18.988568  end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
  159 23:06:18.988679  start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:54) [common]
  160 23:06:18.988747  skipped lava-multinode-overlay
  161 23:06:18.988820  end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
  162 23:06:18.988910  start: 1.5.2.3 test-definition (timeout 00:09:54) [common]
  163 23:06:18.988988  Loading test definitions
  164 23:06:18.989113  start: 1.5.2.3.1 inline-repo-action (timeout 00:09:54) [common]
  165 23:06:18.989199  Using /lava-12395354 at stage 0
  166 23:06:18.989564  uuid=12395354_1.5.2.3.1 testdef=None
  167 23:06:18.989652  end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
  168 23:06:18.989739  start: 1.5.2.3.2 test-overlay (timeout 00:09:54) [common]
  169 23:06:18.990392  end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
  171 23:06:18.990661  start: 1.5.2.3.3 test-install-overlay (timeout 00:09:54) [common]
  172 23:06:18.991440  end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
  174 23:06:18.991670  start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:54) [common]
  175 23:06:18.992545  runner path: /var/lib/lava/dispatcher/tmp/12395354/lava-overlay-gte7n27_/lava-12395354/0/tests/0_cros-ec test_uuid 12395354_1.5.2.3.1
  176 23:06:18.992737  end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
  178 23:06:18.993008  Creating lava-test-runner.conf files
  179 23:06:18.993072  Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12395354/lava-overlay-gte7n27_/lava-12395354/0 for stage 0
  180 23:06:18.993162  - 0_cros-ec
  181 23:06:18.993317  end: 1.5.2.3 test-definition (duration 00:00:00) [common]
  182 23:06:18.993422  start: 1.5.2.4 compress-overlay (timeout 00:09:54) [common]
  183 23:06:19.001251  end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
  184 23:06:19.001384  start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:54) [common]
  185 23:06:19.001500  end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
  186 23:06:19.001610  end: 1.5.2 lava-overlay (duration 00:00:00) [common]
  187 23:06:19.001701  start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:54) [common]
  188 23:06:20.042002  end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
  189 23:06:20.042445  start: 1.5.4 extract-modules (timeout 00:09:53) [common]
  190 23:06:20.042568  extracting modules file /var/lib/lava/dispatcher/tmp/12395354/tftp-deploy-z6ayw89f/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12395354/extract-overlay-ramdisk-96l8pz8d/ramdisk
  191 23:06:20.275030  end: 1.5.4 extract-modules (duration 00:00:00) [common]
  192 23:06:20.275204  start: 1.5.5 apply-overlay-tftp (timeout 00:09:53) [common]
  193 23:06:20.275329  [common] Applying overlay /var/lib/lava/dispatcher/tmp/12395354/compress-overlay-st1xq2rp/overlay-1.5.2.4.tar.gz to ramdisk
  194 23:06:20.275412  [common] Applying overlay /var/lib/lava/dispatcher/tmp/12395354/compress-overlay-st1xq2rp/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12395354/extract-overlay-ramdisk-96l8pz8d/ramdisk
  195 23:06:20.282050  end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
  196 23:06:20.282179  start: 1.5.6 configure-preseed-file (timeout 00:09:53) [common]
  197 23:06:20.282288  end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
  198 23:06:20.282393  start: 1.5.7 compress-ramdisk (timeout 00:09:53) [common]
  199 23:06:20.282548  Building ramdisk /var/lib/lava/dispatcher/tmp/12395354/extract-overlay-ramdisk-96l8pz8d/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12395354/extract-overlay-ramdisk-96l8pz8d/ramdisk
  200 23:06:21.033757  >> 271090 blocks

  201 23:06:25.855109  rename /var/lib/lava/dispatcher/tmp/12395354/extract-overlay-ramdisk-96l8pz8d/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12395354/tftp-deploy-z6ayw89f/ramdisk/ramdisk.cpio.gz
  202 23:06:25.855686  end: 1.5.7 compress-ramdisk (duration 00:00:06) [common]
  203 23:06:25.855864  start: 1.5.8 prepare-kernel (timeout 00:09:47) [common]
  204 23:06:25.856007  start: 1.5.8.1 prepare-fit (timeout 00:09:47) [common]
  205 23:06:25.856159  Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12395354/tftp-deploy-z6ayw89f/kernel/Image'
  206 23:06:39.261175  Returned 0 in 13 seconds
  207 23:06:39.361821  mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12395354/tftp-deploy-z6ayw89f/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12395354/tftp-deploy-z6ayw89f/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12395354/tftp-deploy-z6ayw89f/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12395354/tftp-deploy-z6ayw89f/kernel/image.itb
  208 23:06:40.090440  output: FIT description: Kernel Image image with one or more FDT blobs
  209 23:06:40.090824  output: Created:         Wed Dec 27 23:06:39 2023
  210 23:06:40.090910  output:  Image 0 (kernel-1)
  211 23:06:40.090977  output:   Description:  
  212 23:06:40.091045  output:   Created:      Wed Dec 27 23:06:39 2023
  213 23:06:40.091108  output:   Type:         Kernel Image
  214 23:06:40.091167  output:   Compression:  lzma compressed
  215 23:06:40.091227  output:   Data Size:    11480388 Bytes = 11211.32 KiB = 10.95 MiB
  216 23:06:40.091283  output:   Architecture: AArch64
  217 23:06:40.091340  output:   OS:           Linux
  218 23:06:40.091396  output:   Load Address: 0x00000000
  219 23:06:40.091454  output:   Entry Point:  0x00000000
  220 23:06:40.091510  output:   Hash algo:    crc32
  221 23:06:40.091568  output:   Hash value:   a55b2f0b
  222 23:06:40.091623  output:  Image 1 (fdt-1)
  223 23:06:40.091678  output:   Description:  mt8192-asurada-spherion-r0
  224 23:06:40.091732  output:   Created:      Wed Dec 27 23:06:39 2023
  225 23:06:40.091786  output:   Type:         Flat Device Tree
  226 23:06:40.091839  output:   Compression:  uncompressed
  227 23:06:40.091892  output:   Data Size:    47278 Bytes = 46.17 KiB = 0.05 MiB
  228 23:06:40.091945  output:   Architecture: AArch64
  229 23:06:40.091998  output:   Hash algo:    crc32
  230 23:06:40.092050  output:   Hash value:   cc4352de
  231 23:06:40.092103  output:  Image 2 (ramdisk-1)
  232 23:06:40.092156  output:   Description:  unavailable
  233 23:06:40.092209  output:   Created:      Wed Dec 27 23:06:39 2023
  234 23:06:40.092262  output:   Type:         RAMDisk Image
  235 23:06:40.092315  output:   Compression:  Unknown Compression
  236 23:06:40.092368  output:   Data Size:    47536951 Bytes = 46422.80 KiB = 45.33 MiB
  237 23:06:40.092421  output:   Architecture: AArch64
  238 23:06:40.092474  output:   OS:           Linux
  239 23:06:40.092526  output:   Load Address: unavailable
  240 23:06:40.092579  output:   Entry Point:  unavailable
  241 23:06:40.092631  output:   Hash algo:    crc32
  242 23:06:40.092684  output:   Hash value:   56936ddb
  243 23:06:40.092737  output:  Default Configuration: 'conf-1'
  244 23:06:40.092789  output:  Configuration 0 (conf-1)
  245 23:06:40.092842  output:   Description:  mt8192-asurada-spherion-r0
  246 23:06:40.092895  output:   Kernel:       kernel-1
  247 23:06:40.092947  output:   Init Ramdisk: ramdisk-1
  248 23:06:40.093000  output:   FDT:          fdt-1
  249 23:06:40.093052  output:   Loadables:    kernel-1
  250 23:06:40.093105  output: 
  251 23:06:40.093311  end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
  252 23:06:40.093410  end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
  253 23:06:40.093512  end: 1.5 prepare-tftp-overlay (duration 00:00:21) [common]
  254 23:06:40.093610  start: 1.6 lxc-create-udev-rule-action (timeout 00:09:33) [common]
  255 23:06:40.093687  No LXC device requested
  256 23:06:40.093768  end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
  257 23:06:40.093851  start: 1.7 deploy-device-env (timeout 00:09:33) [common]
  258 23:06:40.093929  end: 1.7 deploy-device-env (duration 00:00:00) [common]
  259 23:06:40.094001  Checking files for TFTP limit of 4294967296 bytes.
  260 23:06:40.094509  end: 1 tftp-deploy (duration 00:00:27) [common]
  261 23:06:40.094615  start: 2 depthcharge-action (timeout 00:05:00) [common]
  262 23:06:40.094706  start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
  263 23:06:40.094832  substitutions:
  264 23:06:40.094898  - {DTB}: 12395354/tftp-deploy-z6ayw89f/dtb/mt8192-asurada-spherion-r0.dtb
  265 23:06:40.094964  - {INITRD}: 12395354/tftp-deploy-z6ayw89f/ramdisk/ramdisk.cpio.gz
  266 23:06:40.095024  - {KERNEL}: 12395354/tftp-deploy-z6ayw89f/kernel/Image
  267 23:06:40.095081  - {LAVA_MAC}: None
  268 23:06:40.095137  - {PRESEED_CONFIG}: None
  269 23:06:40.095199  - {PRESEED_LOCAL}: None
  270 23:06:40.095267  - {RAMDISK}: 12395354/tftp-deploy-z6ayw89f/ramdisk/ramdisk.cpio.gz
  271 23:06:40.095323  - {ROOT_PART}: None
  272 23:06:40.095379  - {ROOT}: None
  273 23:06:40.095433  - {SERVER_IP}: 192.168.201.1
  274 23:06:40.095487  - {TEE}: None
  275 23:06:40.095541  Parsed boot commands:
  276 23:06:40.095595  - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
  277 23:06:40.095777  Parsed boot commands: tftpboot 192.168.201.1 12395354/tftp-deploy-z6ayw89f/kernel/image.itb 12395354/tftp-deploy-z6ayw89f/kernel/cmdline 
  278 23:06:40.095868  end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
  279 23:06:40.095957  start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
  280 23:06:40.096059  start: 2.2.1 reset-connection (timeout 00:05:00) [common]
  281 23:06:40.096143  start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
  282 23:06:40.096212  Not connected, no need to disconnect.
  283 23:06:40.096285  end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
  284 23:06:40.096364  start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
  285 23:06:40.096427  [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-3'
  286 23:06:40.100457  Setting prompt string to ['lava-test: # ']
  287 23:06:40.100822  end: 2.2.1.2 connect-device (duration 00:00:00) [common]
  288 23:06:40.100932  end: 2.2.1 reset-connection (duration 00:00:00) [common]
  289 23:06:40.101031  start: 2.2.2 reset-device (timeout 00:05:00) [common]
  290 23:06:40.101125  start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
  291 23:06:40.101359  Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=reboot'
  292 23:06:45.237972  >> Command sent successfully.

  293 23:06:45.240365  Returned 0 in 5 seconds
  294 23:06:45.340740  end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
  296 23:06:45.341072  end: 2.2.2 reset-device (duration 00:00:05) [common]
  297 23:06:45.341214  start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
  298 23:06:45.341312  Setting prompt string to 'Starting depthcharge on Spherion...'
  299 23:06:45.341380  Changing prompt to 'Starting depthcharge on Spherion...'
  300 23:06:45.341452  depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
  301 23:06:45.341717  [Enter `^Ec?' for help]

  302 23:06:45.516375  

  303 23:06:45.516526  

  304 23:06:45.516601  F0: 102B 0000

  305 23:06:45.516667  

  306 23:06:45.516727  F3: 1001 0000 [0200]

  307 23:06:45.516787  

  308 23:06:45.519746  F3: 1001 0000

  309 23:06:45.519848  

  310 23:06:45.519966  F7: 102D 0000

  311 23:06:45.520077  

  312 23:06:45.520156  F1: 0000 0000

  313 23:06:45.520220  

  314 23:06:45.524104  V0: 0000 0000 [0001]

  315 23:06:45.524191  

  316 23:06:45.524258  00: 0007 8000

  317 23:06:45.524324  

  318 23:06:45.527375  01: 0000 0000

  319 23:06:45.527461  

  320 23:06:45.527528  BP: 0C00 0209 [0000]

  321 23:06:45.527590  

  322 23:06:45.527649  G0: 1182 0000

  323 23:06:45.527708  

  324 23:06:45.531819  EC: 0000 0021 [4000]

  325 23:06:45.531903  

  326 23:06:45.531970  S7: 0000 0000 [0000]

  327 23:06:45.532032  

  328 23:06:45.534973  CC: 0000 0000 [0001]

  329 23:06:45.535057  

  330 23:06:45.535124  T0: 0000 0040 [010F]

  331 23:06:45.537937  

  332 23:06:45.538064  Jump to BL

  333 23:06:45.538166  

  334 23:06:45.562357  

  335 23:06:45.562492  

  336 23:06:45.562560  

  337 23:06:45.569765  coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...

  338 23:06:45.573736  ARM64: Exception handlers installed.

  339 23:06:45.577125  ARM64: Testing exception

  340 23:06:45.581939  ARM64: Done test exception

  341 23:06:45.587948  Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000

  342 23:06:45.595705  Mapping address range [0x00000000:0x200000000) as     cacheable | read-write |     secure | device

  343 23:06:45.603006  Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000

  344 23:06:45.614003  Mapping address range [0x00100000:0x00120000) as     cacheable | read-write |     secure | normal

  345 23:06:45.619913  Backing address range [0x00000000:0x40000000) with new page table @0x0010f000

  346 23:06:45.630325  Backing address range [0x00000000:0x00200000) with new page table @0x00110000

  347 23:06:45.640753  Mapping address range [0x00200000:0x00300000) as     cacheable | read-write |     secure | normal

  348 23:06:45.647847  Backing address range [0x00200000:0x00400000) with new page table @0x00111000

  349 23:06:45.665646  Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write |     secure | normal

  350 23:06:45.668608  WDT: Last reset was cold boot

  351 23:06:45.672333  SPI1(PAD0) initialized at 2873684 Hz

  352 23:06:45.675372  SPI5(PAD0) initialized at 992727 Hz

  353 23:06:45.678868  VBOOT: Loading verstage.

  354 23:06:45.685325  SF: Detected 00 0000 with sector size 0x1000, total 0x800000

  355 23:06:45.688870  FMAP: Found "FLASH" version 1.1 at 0x20000.

  356 23:06:45.692250  FMAP: base = 0x0 size = 0x800000 #areas = 25

  357 23:06:45.695730  FMAP: area COREBOOT found @ 21000 (4014080 bytes)

  358 23:06:45.702970  CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes

  359 23:06:45.709814  CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150

  360 23:06:45.720416  read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps

  361 23:06:45.720552  

  362 23:06:45.720621  

  363 23:06:45.730388  coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...

  364 23:06:45.733683  ARM64: Exception handlers installed.

  365 23:06:45.737307  ARM64: Testing exception

  366 23:06:45.737394  ARM64: Done test exception

  367 23:06:45.744253  FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)

  368 23:06:45.747713  SF: Detected 00 0000 with sector size 0x1000, total 0x800000

  369 23:06:45.761336  Probing TPM: . done!

  370 23:06:45.761464  TPM ready after 0 ms

  371 23:06:45.768549  Connected to device vid:did:rid of 1ae0:0028:00

  372 23:06:45.776411  Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c

  373 23:06:45.832395  Initialized TPM device CR50 revision 0

  374 23:06:45.844002  tlcl_send_startup: Startup return code is 0

  375 23:06:45.844110  TPM: setup succeeded

  376 23:06:45.856080  src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0

  377 23:06:45.864986  src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0

  378 23:06:45.875847  VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)

  379 23:06:45.886298  src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0

  380 23:06:45.889161  out: cmd=0xd: 03 f0 0d 00 00 00 00 00 

  381 23:06:45.898351  in-header: 03 07 00 00 08 00 00 00 

  382 23:06:45.901519  in-data: aa e4 47 04 13 02 00 00 

  383 23:06:45.904772  Chrome EC: UHEPI supported

  384 23:06:45.912279  out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00 

  385 23:06:45.915169  in-header: 03 ad 00 00 08 00 00 00 

  386 23:06:45.919549  in-data: 00 20 20 08 00 00 00 00 

  387 23:06:45.919635  Phase 1

  388 23:06:45.922866  FMAP: area GBB found @ 3f5000 (12032 bytes)

  389 23:06:45.930520  VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7

  390 23:06:45.934049  VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7

  391 23:06:45.937455  Recovery requested (1009000e)

  392 23:06:45.946076  TPM: Extending digest for VBOOT: boot mode into PCR 0

  393 23:06:45.952045  tlcl_extend: response is 0

  394 23:06:45.961381  TPM: Extending digest for VBOOT: GBB HWID into PCR 1

  395 23:06:45.967607  tlcl_extend: response is 0

  396 23:06:45.973917  CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c

  397 23:06:45.993701  read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps

  398 23:06:46.000553  BS: bootblock times (exec / console): total (unknown) / 148 ms

  399 23:06:46.000666  

  400 23:06:46.000736  

  401 23:06:46.010971  coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...

  402 23:06:46.014850  ARM64: Exception handlers installed.

  403 23:06:46.014936  ARM64: Testing exception

  404 23:06:46.018197  ARM64: Done test exception

  405 23:06:46.038822  pmic_efuse_setting: Set efuses in 11 msecs

  406 23:06:46.042551  pmwrap_interface_init: Select PMIF_VLD_RDY

  407 23:06:46.049013  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a

  408 23:06:46.052290  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a

  409 23:06:46.059083  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a

  410 23:06:46.063575  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a

  411 23:06:46.066947  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a

  412 23:06:46.070617  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a

  413 23:06:46.078402  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a

  414 23:06:46.081597  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a

  415 23:06:46.085686  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c

  416 23:06:46.093667  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a

  417 23:06:46.096673  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a

  418 23:06:46.100594  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c

  419 23:06:46.104458  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c

  420 23:06:46.111624  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a

  421 23:06:46.115758  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a

  422 23:06:46.122659  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a

  423 23:06:46.130634  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a

  424 23:06:46.133960  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a

  425 23:06:46.138616  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a

  426 23:06:46.145079  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a

  427 23:06:46.148622  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c

  428 23:06:46.156269  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a

  429 23:06:46.163815  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a

  430 23:06:46.167507  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c

  431 23:06:46.171808  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c

  432 23:06:46.179222  [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa

  433 23:06:46.183258  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92

  434 23:06:46.186652  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2

  435 23:06:46.194476  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82

  436 23:06:46.197218  [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10

  437 23:06:46.201572  [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425

  438 23:06:46.208813  [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010

  439 23:06:46.212540  [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f

  440 23:06:46.219113  [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000

  441 23:06:46.223263  [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8

  442 23:06:46.227138  [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb

  443 23:06:46.234980  [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698

  444 23:06:46.238484  [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3

  445 23:06:46.242831  [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92

  446 23:06:46.246237  [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a

  447 23:06:46.250358  [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2

  448 23:06:46.257266  [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a

  449 23:06:46.261052  [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a

  450 23:06:46.265080  [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a

  451 23:06:46.268611  [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a

  452 23:06:46.271860  [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82

  453 23:06:46.276229  [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c

  454 23:06:46.283532  [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a

  455 23:06:46.287294  [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a

  456 23:06:46.291176  [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c

  457 23:06:46.294307  [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c

  458 23:06:46.302125  [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248

  459 23:06:46.309489  [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1

  460 23:06:46.313458  [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0

  461 23:06:46.324847  [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248

  462 23:06:46.331984  [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0

  463 23:06:46.335810  [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0

  464 23:06:46.339598  [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1

  465 23:06:46.346236  [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1

  466 23:06:46.354682  [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x21

  467 23:06:46.357220  [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2

  468 23:06:46.361210  [RTC]rtc_osc_init,62: osc32con val = 0xde6f

  469 23:06:46.368213  [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a

  470 23:06:46.376939  [RTC]rtc_get_frequency_meter,154: input=15, output=790

  471 23:06:46.385704  [RTC]rtc_get_frequency_meter,154: input=23, output=979

  472 23:06:46.395923  [RTC]rtc_get_frequency_meter,154: input=19, output=885

  473 23:06:46.405082  [RTC]rtc_get_frequency_meter,154: input=17, output=837

  474 23:06:46.414392  [RTC]rtc_get_frequency_meter,154: input=16, output=815

  475 23:06:46.424128  [RTC]rtc_get_frequency_meter,154: input=15, output=790

  476 23:06:46.434575  [RTC]rtc_get_frequency_meter,154: input=16, output=813

  477 23:06:46.438392  [RTC]rtc_eosc_cali,47: left: 15, middle: 15, right: 16

  478 23:06:46.441584  [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f

  479 23:06:46.445259  [RTC]rtc_boot_common,202: RTC_STATE_REBOOT

  480 23:06:46.452863  [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486

  481 23:06:46.455792  [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1

  482 23:06:46.459863  [RTC]rtc_bbpu_power_on,300: done BBPU=0x81

  483 23:06:46.463886  ADC[4]: Raw value=900959 ID=7

  484 23:06:46.463974  ADC[3]: Raw value=213336 ID=1

  485 23:06:46.467765  RAM Code: 0x71

  486 23:06:46.471081  FMAP: area COREBOOT found @ 21000 (4014080 bytes)

  487 23:06:46.474984  SF: Detected 00 0000 with sector size 0x1000, total 0x800000

  488 23:06:46.486124  CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014

  489 23:06:46.489955  DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE

  490 23:06:46.493170  out: cmd=0xd: 03 f0 0d 00 00 00 00 00 

  491 23:06:46.496957  in-header: 03 07 00 00 08 00 00 00 

  492 23:06:46.500668  in-data: aa e4 47 04 13 02 00 00 

  493 23:06:46.504684  Chrome EC: UHEPI supported

  494 23:06:46.511517  out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00 

  495 23:06:46.515385  in-header: 03 ed 00 00 08 00 00 00 

  496 23:06:46.520305  in-data: 80 20 60 08 00 00 00 00 

  497 23:06:46.520392  MRC: failed to locate region type 0.

  498 23:06:46.527277  DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)

  499 23:06:46.531262  DRAM-K: Running full calibration

  500 23:06:46.538578  DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE

  501 23:06:46.538665  header.status = 0x0

  502 23:06:46.542811  header.version = 0x6 (expected: 0x6)

  503 23:06:46.546419  header.size = 0xd00 (expected: 0xd00)

  504 23:06:46.546518  header.flags = 0x0

  505 23:06:46.553932  CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40

  506 23:06:46.572215  read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps

  507 23:06:46.578675  dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6

  508 23:06:46.582708  dram_init: ddr_geometry: 2

  509 23:06:46.582794  [EMI] MDL number = 2

  510 23:06:46.586756  [EMI] Get MDL freq = 0

  511 23:06:46.586841  dram_init: ddr_type: 0

  512 23:06:46.590111  is_discrete_lpddr4: 1

  513 23:06:46.590195  [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0

  514 23:06:46.593915  

  515 23:06:46.593986  

  516 23:06:46.594049  [Bian_co] ETT version 0.0.0.1

  517 23:06:46.601542   dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6

  518 23:06:46.601626  

  519 23:06:46.605247  dramc_set_vcore_voltage set vcore to 650000

  520 23:06:46.605331  Read voltage for 800, 4

  521 23:06:46.608731  Vio18 = 0

  522 23:06:46.608815  Vcore = 650000

  523 23:06:46.608881  Vdram = 0

  524 23:06:46.608943  Vddq = 0

  525 23:06:46.612494  Vmddr = 0

  526 23:06:46.612625  dram_init: config_dvfs: 1

  527 23:06:46.618757  [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0

  528 23:06:46.623259  [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0

  529 23:06:46.628765  [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=10

  530 23:06:46.632332  freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=10

  531 23:06:46.635609  [SwImpedanceCal] DRVP=12, DRVN=25, ODTN=9

  532 23:06:46.638811  freq_region=1, Reg: DRVP=12, DRVN=25, ODTN=9

  533 23:06:46.642512  MEM_TYPE=3, freq_sel=18

  534 23:06:46.646615  sv_algorithm_assistance_LP4_1600 

  535 23:06:46.649095  ============ PULL DRAM RESETB DOWN ============

  536 23:06:46.652406  ========== PULL DRAM RESETB DOWN end =========

  537 23:06:46.656232  [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2

  538 23:06:46.658926  =================================== 

  539 23:06:46.662297  LPDDR4 DRAM CONFIGURATION

  540 23:06:46.666200  =================================== 

  541 23:06:46.669095  EX_ROW_EN[0]    = 0x0

  542 23:06:46.669183  EX_ROW_EN[1]    = 0x0

  543 23:06:46.672749  LP4Y_EN      = 0x0

  544 23:06:46.672835  WORK_FSP     = 0x0

  545 23:06:46.676052  WL           = 0x2

  546 23:06:46.676137  RL           = 0x2

  547 23:06:46.679254  BL           = 0x2

  548 23:06:46.679339  RPST         = 0x0

  549 23:06:46.683128  RD_PRE       = 0x0

  550 23:06:46.683214  WR_PRE       = 0x1

  551 23:06:46.686498  WR_PST       = 0x0

  552 23:06:46.686582  DBI_WR       = 0x0

  553 23:06:46.689664  DBI_RD       = 0x0

  554 23:06:46.689749  OTF          = 0x1

  555 23:06:46.693338  =================================== 

  556 23:06:46.696472  =================================== 

  557 23:06:46.699596  ANA top config

  558 23:06:46.702807  =================================== 

  559 23:06:46.702893  DLL_ASYNC_EN            =  0

  560 23:06:46.706361  ALL_SLAVE_EN            =  1

  561 23:06:46.709375  NEW_RANK_MODE           =  1

  562 23:06:46.712819  DLL_IDLE_MODE           =  1

  563 23:06:46.716237  LP45_APHY_COMB_EN       =  1

  564 23:06:46.716327  TX_ODT_DIS              =  1

  565 23:06:46.719426  NEW_8X_MODE             =  1

  566 23:06:46.722990  =================================== 

  567 23:06:46.726555  =================================== 

  568 23:06:46.729736  data_rate                  = 1600

  569 23:06:46.733461  CKR                        = 1

  570 23:06:46.736326  DQ_P2S_RATIO               = 8

  571 23:06:46.739553  =================================== 

  572 23:06:46.739637  CA_P2S_RATIO               = 8

  573 23:06:46.742987  DQ_CA_OPEN                 = 0

  574 23:06:46.746366  DQ_SEMI_OPEN               = 0

  575 23:06:46.749751  CA_SEMI_OPEN               = 0

  576 23:06:46.752981  CA_FULL_RATE               = 0

  577 23:06:46.753066  DQ_CKDIV4_EN               = 1

  578 23:06:46.756386  CA_CKDIV4_EN               = 1

  579 23:06:46.759795  CA_PREDIV_EN               = 0

  580 23:06:46.763106  PH8_DLY                    = 0

  581 23:06:46.766578  SEMI_OPEN_CA_PICK_MCK_RATIO= 0

  582 23:06:46.770097  DQ_AAMCK_DIV               = 4

  583 23:06:46.770182  CA_AAMCK_DIV               = 4

  584 23:06:46.773271  CA_ADMCK_DIV               = 4

  585 23:06:46.777188  DQ_TRACK_CA_EN             = 0

  586 23:06:46.780564  CA_PICK                    = 800

  587 23:06:46.783312  CA_MCKIO                   = 800

  588 23:06:46.786587  MCKIO_SEMI                 = 0

  589 23:06:46.790597  PLL_FREQ                   = 3068

  590 23:06:46.790721  DQ_UI_PI_RATIO             = 32

  591 23:06:46.794342  CA_UI_PI_RATIO             = 0

  592 23:06:46.798407  =================================== 

  593 23:06:46.802062  =================================== 

  594 23:06:46.802147  memory_type:LPDDR4         

  595 23:06:46.806328  GP_NUM     : 10       

  596 23:06:46.806449  SRAM_EN    : 1       

  597 23:06:46.809477  MD32_EN    : 0       

  598 23:06:46.813066  =================================== 

  599 23:06:46.813150  [ANA_INIT] >>>>>>>>>>>>>> 

  600 23:06:46.817128  <<<<<< [CONFIGURE PHASE]: ANA_TX

  601 23:06:46.821157  >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL

  602 23:06:46.824404  =================================== 

  603 23:06:46.827612  data_rate = 1600,PCW = 0X7600

  604 23:06:46.831203  =================================== 

  605 23:06:46.834562  <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL

  606 23:06:46.837891  >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

  607 23:06:46.844281  <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

  608 23:06:46.847629  >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2

  609 23:06:46.855056  >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL

  610 23:06:46.857722  <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL

  611 23:06:46.857816  [ANA_INIT] flow start 

  612 23:06:46.861565  [ANA_INIT] PLL >>>>>>>> 

  613 23:06:46.865107  [ANA_INIT] PLL <<<<<<<< 

  614 23:06:46.865191  [ANA_INIT] MIDPI >>>>>>>> 

  615 23:06:46.868107  [ANA_INIT] MIDPI <<<<<<<< 

  616 23:06:46.871261  [ANA_INIT] DLL >>>>>>>> 

  617 23:06:46.871378  [ANA_INIT] flow end 

  618 23:06:46.874656  ============ LP4 DIFF to SE enter ============

  619 23:06:46.881822  ============ LP4 DIFF to SE exit  ============

  620 23:06:46.881931  [ANA_INIT] <<<<<<<<<<<<< 

  621 23:06:46.885181  [Flow] Enable top DCM control >>>>> 

  622 23:06:46.888059  [Flow] Enable top DCM control <<<<< 

  623 23:06:46.891366  Enable DLL master slave shuffle 

  624 23:06:46.898029  ============================================================== 

  625 23:06:46.898121  Gating Mode config

  626 23:06:46.904642  ============================================================== 

  627 23:06:46.907919  Config description: 

  628 23:06:46.914635  RX_GATING_MODE        0: Pulse Mode      1: Burst Mode(8UI)        2: Burst Mode(7UI)  3: Original Burst Mode

  629 23:06:46.921298  RX_GATING_TRACK_MODE  0: Valid DLY Mode  1: Valid Mode (-like) 2: FIFO mode

  630 23:06:46.928836  SELPH_MODE            0: By rank         1: By Phase 

  631 23:06:46.935461  ============================================================== 

  632 23:06:46.935558  GAT_TRACK_EN                 =  1

  633 23:06:46.938591  RX_GATING_MODE               =  2

  634 23:06:46.941497  RX_GATING_TRACK_MODE         =  2

  635 23:06:46.945405  SELPH_MODE                   =  1

  636 23:06:46.948286  PICG_EARLY_EN                =  1

  637 23:06:46.952247  VALID_LAT_VALUE              =  1

  638 23:06:46.958517  ============================================================== 

  639 23:06:46.962226  Enter into Gating configuration >>>> 

  640 23:06:46.965510  Exit from Gating configuration <<<< 

  641 23:06:46.965596  Enter into  DVFS_PRE_config >>>>> 

  642 23:06:46.978382  Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. 

  643 23:06:46.982180  Exit from  DVFS_PRE_config <<<<< 

  644 23:06:46.985165  Enter into PICG configuration >>>> 

  645 23:06:46.989139  Exit from PICG configuration <<<< 

  646 23:06:46.989223  [RX_INPUT] configuration >>>>> 

  647 23:06:46.992297  [RX_INPUT] configuration <<<<< 

  648 23:06:46.998885  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>

  649 23:06:47.002299  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<

  650 23:06:47.009852  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>

  651 23:06:47.015924  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<

  652 23:06:47.022948  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>

  653 23:06:47.030229  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<

  654 23:06:47.033694  [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 

  655 23:06:47.036373  [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 

  656 23:06:47.039938  [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 

  657 23:06:47.043927  [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 

  658 23:06:47.050257  [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 

  659 23:06:47.054209  [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2

  660 23:06:47.056974  =================================== 

  661 23:06:47.060040  LPDDR4 DRAM CONFIGURATION

  662 23:06:47.063965  =================================== 

  663 23:06:47.064049  EX_ROW_EN[0]    = 0x0

  664 23:06:47.066523  EX_ROW_EN[1]    = 0x0

  665 23:06:47.066607  LP4Y_EN      = 0x0

  666 23:06:47.070065  WORK_FSP     = 0x0

  667 23:06:47.070150  WL           = 0x2

  668 23:06:47.073380  RL           = 0x2

  669 23:06:47.073465  BL           = 0x2

  670 23:06:47.076714  RPST         = 0x0

  671 23:06:47.076798  RD_PRE       = 0x0

  672 23:06:47.080561  WR_PRE       = 0x1

  673 23:06:47.080644  WR_PST       = 0x0

  674 23:06:47.083716  DBI_WR       = 0x0

  675 23:06:47.083799  DBI_RD       = 0x0

  676 23:06:47.086814  OTF          = 0x1

  677 23:06:47.090991  =================================== 

  678 23:06:47.094338  [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 

  679 23:06:47.098350  [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 

  680 23:06:47.103893  [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2

  681 23:06:47.107651  =================================== 

  682 23:06:47.107735  LPDDR4 DRAM CONFIGURATION

  683 23:06:47.110236  =================================== 

  684 23:06:47.113542  EX_ROW_EN[0]    = 0x10

  685 23:06:47.113625  EX_ROW_EN[1]    = 0x0

  686 23:06:47.117171  LP4Y_EN      = 0x0

  687 23:06:47.121118  WORK_FSP     = 0x0

  688 23:06:47.121202  WL           = 0x2

  689 23:06:47.124264  RL           = 0x2

  690 23:06:47.124347  BL           = 0x2

  691 23:06:47.127285  RPST         = 0x0

  692 23:06:47.127369  RD_PRE       = 0x0

  693 23:06:47.130898  WR_PRE       = 0x1

  694 23:06:47.130982  WR_PST       = 0x0

  695 23:06:47.133785  DBI_WR       = 0x0

  696 23:06:47.133869  DBI_RD       = 0x0

  697 23:06:47.137592  OTF          = 0x1

  698 23:06:47.140899  =================================== 

  699 23:06:47.143870  [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit

  700 23:06:47.149355  nWR fixed to 40

  701 23:06:47.152501  [ModeRegInit_LP4] CH0 RK0

  702 23:06:47.152585  [ModeRegInit_LP4] CH0 RK1

  703 23:06:47.156321  [ModeRegInit_LP4] CH1 RK0

  704 23:06:47.159755  [ModeRegInit_LP4] CH1 RK1

  705 23:06:47.159839  match AC timing 13

  706 23:06:47.166496  dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1

  707 23:06:47.170187  SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON

  708 23:06:47.173485  [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8

  709 23:06:47.180221  [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17

  710 23:06:47.183383  [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)

  711 23:06:47.183467  [EMI DOE] emi_dcm 0

  712 23:06:47.190028  [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600

  713 23:06:47.190113  ==

  714 23:06:47.193079  Dram Type= 6, Freq= 0, CH_0, rank 0

  715 23:06:47.196543  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  716 23:06:47.196628  ==

  717 23:06:47.203400  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

  718 23:06:47.206729  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34

  719 23:06:47.216853  [CA 0] Center 37 (7~68) winsize 62

  720 23:06:47.220415  [CA 1] Center 37 (6~68) winsize 63

  721 23:06:47.223636  [CA 2] Center 35 (4~66) winsize 63

  722 23:06:47.226662  [CA 3] Center 34 (4~65) winsize 62

  723 23:06:47.230529  [CA 4] Center 34 (3~65) winsize 63

  724 23:06:47.234160  [CA 5] Center 33 (3~64) winsize 62

  725 23:06:47.234244  

  726 23:06:47.236792  [CmdBusTrainingLP45] Vref(ca) range 1: 34

  727 23:06:47.236877  

  728 23:06:47.240315  [CATrainingPosCal] consider 1 rank data

  729 23:06:47.244001  u2DelayCellTimex100 = 270/100 ps

  730 23:06:47.247727  CA0 delay=37 (7~68),Diff = 4 PI (28 cell)

  731 23:06:47.250558  CA1 delay=37 (6~68),Diff = 4 PI (28 cell)

  732 23:06:47.254011  CA2 delay=35 (4~66),Diff = 2 PI (14 cell)

  733 23:06:47.260993  CA3 delay=34 (4~65),Diff = 1 PI (7 cell)

  734 23:06:47.263798  CA4 delay=34 (3~65),Diff = 1 PI (7 cell)

  735 23:06:47.267505  CA5 delay=33 (3~64),Diff = 0 PI (0 cell)

  736 23:06:47.267589  

  737 23:06:47.271370  CA PerBit enable=1, Macro0, CA PI delay=33

  738 23:06:47.271455  

  739 23:06:47.274337  [CBTSetCACLKResult] CA Dly = 33

  740 23:06:47.274463  CS Dly: 5 (0~36)

  741 23:06:47.274532  ==

  742 23:06:47.277631  Dram Type= 6, Freq= 0, CH_0, rank 1

  743 23:06:47.284760  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  744 23:06:47.284844  ==

  745 23:06:47.287921  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

  746 23:06:47.293990  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34

  747 23:06:47.302976  [CA 0] Center 37 (7~68) winsize 62

  748 23:06:47.306843  [CA 1] Center 37 (7~68) winsize 62

  749 23:06:47.310382  [CA 2] Center 35 (5~66) winsize 62

  750 23:06:47.313017  [CA 3] Center 35 (4~66) winsize 63

  751 23:06:47.316327  [CA 4] Center 34 (3~65) winsize 63

  752 23:06:47.319933  [CA 5] Center 33 (3~64) winsize 62

  753 23:06:47.320017  

  754 23:06:47.323158  [CmdBusTrainingLP45] Vref(ca) range 1: 34

  755 23:06:47.323242  

  756 23:06:47.326756  [CATrainingPosCal] consider 2 rank data

  757 23:06:47.330156  u2DelayCellTimex100 = 270/100 ps

  758 23:06:47.333643  CA0 delay=37 (7~68),Diff = 4 PI (28 cell)

  759 23:06:47.336767  CA1 delay=37 (7~68),Diff = 4 PI (28 cell)

  760 23:06:47.340814  CA2 delay=35 (5~66),Diff = 2 PI (14 cell)

  761 23:06:47.346768  CA3 delay=34 (4~65),Diff = 1 PI (7 cell)

  762 23:06:47.350379  CA4 delay=34 (3~65),Diff = 1 PI (7 cell)

  763 23:06:47.353266  CA5 delay=33 (3~64),Diff = 0 PI (0 cell)

  764 23:06:47.353349  

  765 23:06:47.357476  CA PerBit enable=1, Macro0, CA PI delay=33

  766 23:06:47.357559  

  767 23:06:47.360011  [CBTSetCACLKResult] CA Dly = 33

  768 23:06:47.360094  CS Dly: 5 (0~37)

  769 23:06:47.360160  

  770 23:06:47.364222  ----->DramcWriteLeveling(PI) begin...

  771 23:06:47.364311  ==

  772 23:06:47.367033  Dram Type= 6, Freq= 0, CH_0, rank 0

  773 23:06:47.374591  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  774 23:06:47.374676  ==

  775 23:06:47.374741  Write leveling (Byte 0): 28 => 28

  776 23:06:47.378122  Write leveling (Byte 1): 27 => 27

  777 23:06:47.381966  DramcWriteLeveling(PI) end<-----

  778 23:06:47.382050  

  779 23:06:47.382116  ==

  780 23:06:47.385261  Dram Type= 6, Freq= 0, CH_0, rank 0

  781 23:06:47.389775  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  782 23:06:47.389859  ==

  783 23:06:47.392475  [Gating] SW mode calibration

  784 23:06:47.400232  [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

  785 23:06:47.403752  RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)

  786 23:06:47.410375   0  6  0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)

  787 23:06:47.413143   0  6  4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)

  788 23:06:47.416861   0  6  8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)

  789 23:06:47.423276   0  6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  790 23:06:47.426821   0  6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  791 23:06:47.430297   0  6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  792 23:06:47.436819   0  6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  793 23:06:47.440320   0  6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  794 23:06:47.443280   0  7  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  795 23:06:47.447137   0  7  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  796 23:06:47.454332   0  7  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  797 23:06:47.457120   0  7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  798 23:06:47.460567   0  7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  799 23:06:47.466923   0  7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  800 23:06:47.470602   0  7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  801 23:06:47.473938   0  7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  802 23:06:47.480537   0  8  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  803 23:06:47.483804   0  8  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  804 23:06:47.487001   0  8  8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)

  805 23:06:47.494527   0  8 12 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)

  806 23:06:47.497135   0  8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  807 23:06:47.500676   0  8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  808 23:06:47.507759   0  8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  809 23:06:47.511144   0  8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  810 23:06:47.514237   0  9  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  811 23:06:47.517363   0  9  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  812 23:06:47.524275   0  9  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  813 23:06:47.527483   0  9 12 | B1->B0 | 2626 2e2e | 0 1 | (0 0) (1 1)

  814 23:06:47.530773   0  9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

  815 23:06:47.537447   0  9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

  816 23:06:47.541001   0  9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

  817 23:06:47.543940   0  9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

  818 23:06:47.550586   0 10  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

  819 23:06:47.554592   0 10  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)

  820 23:06:47.557087   0 10  8 | B1->B0 | 3333 2f2f | 1 1 | (1 1) (1 0)

  821 23:06:47.564268   0 10 12 | B1->B0 | 2c2c 2424 | 1 0 | (1 0) (0 0)

  822 23:06:47.567863   0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  823 23:06:47.570983   0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  824 23:06:47.574936   0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  825 23:06:47.580948   0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  826 23:06:47.584556   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  827 23:06:47.588301   0 11  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  828 23:06:47.594302   0 11  8 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)

  829 23:06:47.597680   0 11 12 | B1->B0 | 3636 4545 | 0 1 | (0 0) (0 0)

  830 23:06:47.601173   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

  831 23:06:47.607782   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

  832 23:06:47.612035   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

  833 23:06:47.614472   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

  834 23:06:47.621123   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

  835 23:06:47.624348   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

  836 23:06:47.627844   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

  837 23:06:47.634813   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

  838 23:06:47.638700   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  839 23:06:47.641816   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  840 23:06:47.644655   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  841 23:06:47.651377   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  842 23:06:47.654889   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  843 23:06:47.658460   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  844 23:06:47.665029   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  845 23:06:47.667748   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  846 23:06:47.671645   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  847 23:06:47.678336   0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  848 23:06:47.681345   0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  849 23:06:47.684907   0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  850 23:06:47.691675   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  851 23:06:47.694566   0 14  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

  852 23:06:47.698042   0 14  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

  853 23:06:47.705698   0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

  854 23:06:47.705781  Total UI for P1: 0, mck2ui 16

  855 23:06:47.708255  best dqsien dly found for B0: ( 0, 14,  6)

  856 23:06:47.711921  Total UI for P1: 0, mck2ui 16

  857 23:06:47.714643  best dqsien dly found for B1: ( 0, 14, 10)

  858 23:06:47.718706  best DQS0 dly(MCK, UI, PI) = (0, 14, 6)

  859 23:06:47.725972  best DQS1 dly(MCK, UI, PI) = (0, 14, 10)

  860 23:06:47.726076  

  861 23:06:47.728806  best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)

  862 23:06:47.731661  best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)

  863 23:06:47.735668  [Gating] SW calibration Done

  864 23:06:47.735750  ==

  865 23:06:47.738656  Dram Type= 6, Freq= 0, CH_0, rank 0

  866 23:06:47.742130  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  867 23:06:47.742214  ==

  868 23:06:47.742280  RX Vref Scan: 0

  869 23:06:47.742341  

  870 23:06:47.745098  RX Vref 0 -> 0, step: 1

  871 23:06:47.745181  

  872 23:06:47.749276  RX Delay -130 -> 252, step: 16

  873 23:06:47.751734  iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240

  874 23:06:47.755627  iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240

  875 23:06:47.759041  iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240

  876 23:06:47.765435  iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240

  877 23:06:47.768836  iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240

  878 23:06:47.772653  iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224

  879 23:06:47.775645  iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256

  880 23:06:47.778814  iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240

  881 23:06:47.786207  iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240

  882 23:06:47.788898  iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240

  883 23:06:47.792176  iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224

  884 23:06:47.795811  iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224

  885 23:06:47.799287  iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240

  886 23:06:47.806229  iDelay=222, Bit 13, Center 77 (-34 ~ 189) 224

  887 23:06:47.809161  iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240

  888 23:06:47.812896  iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240

  889 23:06:47.812979  ==

  890 23:06:47.815629  Dram Type= 6, Freq= 0, CH_0, rank 0

  891 23:06:47.819503  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  892 23:06:47.819592  ==

  893 23:06:47.822540  DQS Delay:

  894 23:06:47.822624  DQS0 = 0, DQS1 = 0

  895 23:06:47.825602  DQM Delay:

  896 23:06:47.825685  DQM0 = 85, DQM1 = 78

  897 23:06:47.825751  DQ Delay:

  898 23:06:47.829361  DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85

  899 23:06:47.832963  DQ4 =85, DQ5 =77, DQ6 =93, DQ7 =85

  900 23:06:47.835997  DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =77

  901 23:06:47.839451  DQ12 =85, DQ13 =77, DQ14 =85, DQ15 =85

  902 23:06:47.839535  

  903 23:06:47.839600  

  904 23:06:47.839660  ==

  905 23:06:47.842592  Dram Type= 6, Freq= 0, CH_0, rank 0

  906 23:06:47.849252  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  907 23:06:47.849338  ==

  908 23:06:47.849404  

  909 23:06:47.849485  

  910 23:06:47.849559  	TX Vref Scan disable

  911 23:06:47.852836   == TX Byte 0 ==

  912 23:06:47.856033  Update DQ  dly =581 (2 ,1, 37)  DQ  OEN =(1 ,6)

  913 23:06:47.859788  Update DQM dly =581 (2 ,1, 37)  DQM OEN =(1 ,6)

  914 23:06:47.862958   == TX Byte 1 ==

  915 23:06:47.866381  Update DQ  dly =577 (2 ,1, 33)  DQ  OEN =(1 ,6)

  916 23:06:47.870315  Update DQM dly =577 (2 ,1, 33)  DQM OEN =(1 ,6)

  917 23:06:47.873545  ==

  918 23:06:47.876901  Dram Type= 6, Freq= 0, CH_0, rank 0

  919 23:06:47.879908  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  920 23:06:47.879993  ==

  921 23:06:47.892255  TX Vref=22, minBit 9, minWin=26, winSum=432

  922 23:06:47.895390  TX Vref=24, minBit 3, minWin=27, winSum=440

  923 23:06:47.898634  TX Vref=26, minBit 3, minWin=27, winSum=445

  924 23:06:47.902360  TX Vref=28, minBit 8, minWin=27, winSum=447

  925 23:06:47.905980  TX Vref=30, minBit 1, minWin=28, winSum=450

  926 23:06:47.908860  TX Vref=32, minBit 3, minWin=27, winSum=446

  927 23:06:47.915598  [TxChooseVref] Worse bit 1, Min win 28, Win sum 450, Final Vref 30

  928 23:06:47.915688  

  929 23:06:47.919167  Final TX Range 1 Vref 30

  930 23:06:47.919253  

  931 23:06:47.919319  ==

  932 23:06:47.922045  Dram Type= 6, Freq= 0, CH_0, rank 0

  933 23:06:47.925872  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  934 23:06:47.925958  ==

  935 23:06:47.926046  

  936 23:06:47.926150  

  937 23:06:47.929266  	TX Vref Scan disable

  938 23:06:47.932977   == TX Byte 0 ==

  939 23:06:47.936112  Update DQ  dly =580 (2 ,1, 36)  DQ  OEN =(1 ,6)

  940 23:06:47.938964  Update DQM dly =580 (2 ,1, 36)  DQM OEN =(1 ,6)

  941 23:06:47.943044   == TX Byte 1 ==

  942 23:06:47.945996  Update DQ  dly =577 (2 ,1, 33)  DQ  OEN =(1 ,6)

  943 23:06:47.949515  Update DQM dly =577 (2 ,1, 33)  DQM OEN =(1 ,6)

  944 23:06:47.949598  

  945 23:06:47.952225  [DATLAT]

  946 23:06:47.952308  Freq=800, CH0 RK0

  947 23:06:47.952373  

  948 23:06:47.956108  DATLAT Default: 0xa

  949 23:06:47.956190  0, 0xFFFF, sum = 0

  950 23:06:47.959046  1, 0xFFFF, sum = 0

  951 23:06:47.959133  2, 0xFFFF, sum = 0

  952 23:06:47.962866  3, 0xFFFF, sum = 0

  953 23:06:47.962952  4, 0xFFFF, sum = 0

  954 23:06:47.965472  5, 0xFFFF, sum = 0

  955 23:06:47.965556  6, 0xFFFF, sum = 0

  956 23:06:47.968878  7, 0xFFFF, sum = 0

  957 23:06:47.968963  8, 0xFFFF, sum = 0

  958 23:06:47.972759  9, 0x0, sum = 1

  959 23:06:47.972843  10, 0x0, sum = 2

  960 23:06:47.976230  11, 0x0, sum = 3

  961 23:06:47.976314  12, 0x0, sum = 4

  962 23:06:47.979375  best_step = 10

  963 23:06:47.979458  

  964 23:06:47.979523  ==

  965 23:06:47.982691  Dram Type= 6, Freq= 0, CH_0, rank 0

  966 23:06:47.985902  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  967 23:06:47.985985  ==

  968 23:06:47.989281  RX Vref Scan: 1

  969 23:06:47.989364  

  970 23:06:47.989428  Set Vref Range= 32 -> 127

  971 23:06:47.989488  

  972 23:06:47.992776  RX Vref 32 -> 127, step: 1

  973 23:06:47.992859  

  974 23:06:47.996505  RX Delay -95 -> 252, step: 8

  975 23:06:47.996588  

  976 23:06:48.000361  Set Vref, RX VrefLevel [Byte0]: 32

  977 23:06:48.002350                           [Byte1]: 32

  978 23:06:48.002440  

  979 23:06:48.005777  Set Vref, RX VrefLevel [Byte0]: 33

  980 23:06:48.009749                           [Byte1]: 33

  981 23:06:48.009832  

  982 23:06:48.013997  Set Vref, RX VrefLevel [Byte0]: 34

  983 23:06:48.016916                           [Byte1]: 34

  984 23:06:48.016999  

  985 23:06:48.020618  Set Vref, RX VrefLevel [Byte0]: 35

  986 23:06:48.023211                           [Byte1]: 35

  987 23:06:48.027346  

  988 23:06:48.027428  Set Vref, RX VrefLevel [Byte0]: 36

  989 23:06:48.030650                           [Byte1]: 36

  990 23:06:48.034855  

  991 23:06:48.034937  Set Vref, RX VrefLevel [Byte0]: 37

  992 23:06:48.039420                           [Byte1]: 37

  993 23:06:48.043387  

  994 23:06:48.043469  Set Vref, RX VrefLevel [Byte0]: 38

  995 23:06:48.046637                           [Byte1]: 38

  996 23:06:48.050370  

  997 23:06:48.050492  Set Vref, RX VrefLevel [Byte0]: 39

  998 23:06:48.054219                           [Byte1]: 39

  999 23:06:48.058309  

 1000 23:06:48.058392  Set Vref, RX VrefLevel [Byte0]: 40

 1001 23:06:48.061573                           [Byte1]: 40

 1002 23:06:48.065949  

 1003 23:06:48.066032  Set Vref, RX VrefLevel [Byte0]: 41

 1004 23:06:48.069499                           [Byte1]: 41

 1005 23:06:48.073780  

 1006 23:06:48.073892  Set Vref, RX VrefLevel [Byte0]: 42

 1007 23:06:48.076950                           [Byte1]: 42

 1008 23:06:48.080636  

 1009 23:06:48.080719  Set Vref, RX VrefLevel [Byte0]: 43

 1010 23:06:48.084364                           [Byte1]: 43

 1011 23:06:48.088616  

 1012 23:06:48.088698  Set Vref, RX VrefLevel [Byte0]: 44

 1013 23:06:48.092028                           [Byte1]: 44

 1014 23:06:48.095596  

 1015 23:06:48.095678  Set Vref, RX VrefLevel [Byte0]: 45

 1016 23:06:48.099165                           [Byte1]: 45

 1017 23:06:48.103405  

 1018 23:06:48.103488  Set Vref, RX VrefLevel [Byte0]: 46

 1019 23:06:48.106607                           [Byte1]: 46

 1020 23:06:48.111438  

 1021 23:06:48.111520  Set Vref, RX VrefLevel [Byte0]: 47

 1022 23:06:48.114190                           [Byte1]: 47

 1023 23:06:48.118630  

 1024 23:06:48.118712  Set Vref, RX VrefLevel [Byte0]: 48

 1025 23:06:48.122210                           [Byte1]: 48

 1026 23:06:48.126541  

 1027 23:06:48.126638  Set Vref, RX VrefLevel [Byte0]: 49

 1028 23:06:48.129384                           [Byte1]: 49

 1029 23:06:48.133699  

 1030 23:06:48.133780  Set Vref, RX VrefLevel [Byte0]: 50

 1031 23:06:48.137644                           [Byte1]: 50

 1032 23:06:48.141182  

 1033 23:06:48.141263  Set Vref, RX VrefLevel [Byte0]: 51

 1034 23:06:48.145274                           [Byte1]: 51

 1035 23:06:48.149109  

 1036 23:06:48.149190  Set Vref, RX VrefLevel [Byte0]: 52

 1037 23:06:48.152530                           [Byte1]: 52

 1038 23:06:48.156747  

 1039 23:06:48.156828  Set Vref, RX VrefLevel [Byte0]: 53

 1040 23:06:48.160690                           [Byte1]: 53

 1041 23:06:48.164316  

 1042 23:06:48.164398  Set Vref, RX VrefLevel [Byte0]: 54

 1043 23:06:48.168224                           [Byte1]: 54

 1044 23:06:48.172113  

 1045 23:06:48.172194  Set Vref, RX VrefLevel [Byte0]: 55

 1046 23:06:48.175135                           [Byte1]: 55

 1047 23:06:48.179199  

 1048 23:06:48.179280  Set Vref, RX VrefLevel [Byte0]: 56

 1049 23:06:48.182870                           [Byte1]: 56

 1050 23:06:48.187207  

 1051 23:06:48.187289  Set Vref, RX VrefLevel [Byte0]: 57

 1052 23:06:48.190150                           [Byte1]: 57

 1053 23:06:48.194432  

 1054 23:06:48.194526  Set Vref, RX VrefLevel [Byte0]: 58

 1055 23:06:48.197777                           [Byte1]: 58

 1056 23:06:48.203187  

 1057 23:06:48.203268  Set Vref, RX VrefLevel [Byte0]: 59

 1058 23:06:48.206382                           [Byte1]: 59

 1059 23:06:48.210166  

 1060 23:06:48.210247  Set Vref, RX VrefLevel [Byte0]: 60

 1061 23:06:48.213224                           [Byte1]: 60

 1062 23:06:48.217476  

 1063 23:06:48.217556  Set Vref, RX VrefLevel [Byte0]: 61

 1064 23:06:48.220427                           [Byte1]: 61

 1065 23:06:48.224956  

 1066 23:06:48.225036  Set Vref, RX VrefLevel [Byte0]: 62

 1067 23:06:48.228353                           [Byte1]: 62

 1068 23:06:48.232692  

 1069 23:06:48.232773  Set Vref, RX VrefLevel [Byte0]: 63

 1070 23:06:48.235978                           [Byte1]: 63

 1071 23:06:48.240263  

 1072 23:06:48.240344  Set Vref, RX VrefLevel [Byte0]: 64

 1073 23:06:48.243746                           [Byte1]: 64

 1074 23:06:48.248149  

 1075 23:06:48.248229  Set Vref, RX VrefLevel [Byte0]: 65

 1076 23:06:48.251297                           [Byte1]: 65

 1077 23:06:48.255498  

 1078 23:06:48.255579  Set Vref, RX VrefLevel [Byte0]: 66

 1079 23:06:48.258651                           [Byte1]: 66

 1080 23:06:48.262885  

 1081 23:06:48.262965  Set Vref, RX VrefLevel [Byte0]: 67

 1082 23:06:48.266583                           [Byte1]: 67

 1083 23:06:48.270439  

 1084 23:06:48.270538  Set Vref, RX VrefLevel [Byte0]: 68

 1085 23:06:48.273695                           [Byte1]: 68

 1086 23:06:48.278533  

 1087 23:06:48.278613  Set Vref, RX VrefLevel [Byte0]: 69

 1088 23:06:48.281703                           [Byte1]: 69

 1089 23:06:48.285963  

 1090 23:06:48.286043  Set Vref, RX VrefLevel [Byte0]: 70

 1091 23:06:48.289467                           [Byte1]: 70

 1092 23:06:48.293603  

 1093 23:06:48.293684  Set Vref, RX VrefLevel [Byte0]: 71

 1094 23:06:48.297063                           [Byte1]: 71

 1095 23:06:48.301003  

 1096 23:06:48.301083  Set Vref, RX VrefLevel [Byte0]: 72

 1097 23:06:48.304715                           [Byte1]: 72

 1098 23:06:48.308651  

 1099 23:06:48.308731  Set Vref, RX VrefLevel [Byte0]: 73

 1100 23:06:48.311589                           [Byte1]: 73

 1101 23:06:48.316541  

 1102 23:06:48.316623  Set Vref, RX VrefLevel [Byte0]: 74

 1103 23:06:48.319554                           [Byte1]: 74

 1104 23:06:48.323991  

 1105 23:06:48.324071  Set Vref, RX VrefLevel [Byte0]: 75

 1106 23:06:48.327006                           [Byte1]: 75

 1107 23:06:48.331272  

 1108 23:06:48.331353  Set Vref, RX VrefLevel [Byte0]: 76

 1109 23:06:48.334638                           [Byte1]: 76

 1110 23:06:48.338937  

 1111 23:06:48.339018  Final RX Vref Byte 0 = 61 to rank0

 1112 23:06:48.342559  Final RX Vref Byte 1 = 57 to rank0

 1113 23:06:48.345327  Final RX Vref Byte 0 = 61 to rank1

 1114 23:06:48.349067  Final RX Vref Byte 1 = 57 to rank1==

 1115 23:06:48.352142  Dram Type= 6, Freq= 0, CH_0, rank 0

 1116 23:06:48.355900  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1117 23:06:48.359155  ==

 1118 23:06:48.359237  DQS Delay:

 1119 23:06:48.359301  DQS0 = 0, DQS1 = 0

 1120 23:06:48.362519  DQM Delay:

 1121 23:06:48.362600  DQM0 = 87, DQM1 = 80

 1122 23:06:48.365438  DQ Delay:

 1123 23:06:48.369591  DQ0 =88, DQ1 =92, DQ2 =84, DQ3 =84

 1124 23:06:48.369673  DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =96

 1125 23:06:48.372459  DQ8 =68, DQ9 =64, DQ10 =80, DQ11 =76

 1126 23:06:48.376127  DQ12 =88, DQ13 =84, DQ14 =92, DQ15 =88

 1127 23:06:48.376210  

 1128 23:06:48.379095  

 1129 23:06:48.385945  [DQSOSCAuto] RK0, (LSB)MR18= 0x2a11, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 399 ps

 1130 23:06:48.389603  CH0 RK0: MR19=606, MR18=2A11

 1131 23:06:48.396991  CH0_RK0: MR19=0x606, MR18=0x2A11, DQSOSC=399, MR23=63, INC=92, DEC=61

 1132 23:06:48.397076  

 1133 23:06:48.399607  ----->DramcWriteLeveling(PI) begin...

 1134 23:06:48.399689  ==

 1135 23:06:48.402908  Dram Type= 6, Freq= 0, CH_0, rank 1

 1136 23:06:48.406010  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1137 23:06:48.406094  ==

 1138 23:06:48.409202  Write leveling (Byte 0): 30 => 30

 1139 23:06:48.412844  Write leveling (Byte 1): 30 => 30

 1140 23:06:48.416617  DramcWriteLeveling(PI) end<-----

 1141 23:06:48.416701  

 1142 23:06:48.416765  ==

 1143 23:06:48.419706  Dram Type= 6, Freq= 0, CH_0, rank 1

 1144 23:06:48.422811  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1145 23:06:48.422898  ==

 1146 23:06:48.426109  [Gating] SW mode calibration

 1147 23:06:48.433738  [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

 1148 23:06:48.436432  RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)

 1149 23:06:48.442754   0  6  0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)

 1150 23:06:48.446552   0  6  4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)

 1151 23:06:48.449792   0  6  8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)

 1152 23:06:48.493721   0  6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)

 1153 23:06:48.494098   0  6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1154 23:06:48.494375   0  6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1155 23:06:48.494488   0  6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1156 23:06:48.494550   0  6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1157 23:06:48.494851   0  7  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1158 23:06:48.495549   0  7  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1159 23:06:48.495876   0  7  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1160 23:06:48.496214   0  7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1161 23:06:48.496315   0  7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1162 23:06:48.516276   0  7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1163 23:06:48.516657   0  7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1164 23:06:48.517155   0  7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1165 23:06:48.517584   0  8  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1166 23:06:48.517705   0  8  4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)

 1167 23:06:48.520394   0  8  8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)

 1168 23:06:48.526665   0  8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1169 23:06:48.530288   0  8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1170 23:06:48.533648   0  8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1171 23:06:48.540897   0  8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1172 23:06:48.543770   0  8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1173 23:06:48.547420   0  9  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1174 23:06:48.553973   0  9  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1175 23:06:48.557512   0  9  8 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)

 1176 23:06:48.560889   0  9 12 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)

 1177 23:06:48.564038   0  9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1178 23:06:48.570704   0  9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1179 23:06:48.574263   0  9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1180 23:06:48.577044   0  9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1181 23:06:48.584850   0 10  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)

 1182 23:06:48.587609   0 10  4 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)

 1183 23:06:48.590578   0 10  8 | B1->B0 | 3333 2626 | 0 0 | (0 0) (0 0)

 1184 23:06:48.597081   0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1185 23:06:48.600716   0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1186 23:06:48.604647   0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1187 23:06:48.610958   0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1188 23:06:48.614533   0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1189 23:06:48.617483   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1190 23:06:48.621097   0 11  4 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)

 1191 23:06:48.628892   0 11  8 | B1->B0 | 2e2e 4343 | 0 0 | (0 0) (0 0)

 1192 23:06:48.632827   0 11 12 | B1->B0 | 4040 4646 | 1 0 | (0 0) (0 0)

 1193 23:06:48.636292   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1194 23:06:48.640365   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1195 23:06:48.643407   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1196 23:06:48.649510   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1197 23:06:48.654308   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1198 23:06:48.657006   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)

 1199 23:06:48.664017   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 1200 23:06:48.667075   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1201 23:06:48.670538   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1202 23:06:48.673826   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1203 23:06:48.680297   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1204 23:06:48.684194   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1205 23:06:48.687259   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1206 23:06:48.694194   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1207 23:06:48.697869   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1208 23:06:48.700791   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1209 23:06:48.707062   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1210 23:06:48.710644   0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1211 23:06:48.714866   0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1212 23:06:48.720810   0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1213 23:06:48.724059   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1214 23:06:48.727463   0 14  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 1215 23:06:48.730882   0 14  8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 1216 23:06:48.734166  Total UI for P1: 0, mck2ui 16

 1217 23:06:48.737752  best dqsien dly found for B0: ( 0, 14,  4)

 1218 23:06:48.744428   0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1219 23:06:48.744534  Total UI for P1: 0, mck2ui 16

 1220 23:06:48.751385  best dqsien dly found for B1: ( 0, 14,  8)

 1221 23:06:48.754147  best DQS0 dly(MCK, UI, PI) = (0, 14, 4)

 1222 23:06:48.758241  best DQS1 dly(MCK, UI, PI) = (0, 14, 8)

 1223 23:06:48.758354  

 1224 23:06:48.760925  best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)

 1225 23:06:48.764627  best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)

 1226 23:06:48.768704  [Gating] SW calibration Done

 1227 23:06:48.768793  ==

 1228 23:06:48.770956  Dram Type= 6, Freq= 0, CH_0, rank 1

 1229 23:06:48.774556  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1230 23:06:48.774641  ==

 1231 23:06:48.777981  RX Vref Scan: 0

 1232 23:06:48.778066  

 1233 23:06:48.778131  RX Vref 0 -> 0, step: 1

 1234 23:06:48.778195  

 1235 23:06:48.781369  RX Delay -130 -> 252, step: 16

 1236 23:06:48.784455  iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240

 1237 23:06:48.788732  iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240

 1238 23:06:48.794713  iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240

 1239 23:06:48.798184  iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240

 1240 23:06:48.801409  iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240

 1241 23:06:48.804823  iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240

 1242 23:06:48.808243  iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256

 1243 23:06:48.814651  iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224

 1244 23:06:48.818235  iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240

 1245 23:06:48.821418  iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240

 1246 23:06:48.824689  iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240

 1247 23:06:48.828413  iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240

 1248 23:06:48.835316  iDelay=222, Bit 12, Center 69 (-50 ~ 189) 240

 1249 23:06:48.838610  iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240

 1250 23:06:48.841665  iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240

 1251 23:06:48.844724  iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240

 1252 23:06:48.844811  ==

 1253 23:06:48.848726  Dram Type= 6, Freq= 0, CH_0, rank 1

 1254 23:06:48.851582  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1255 23:06:48.855149  ==

 1256 23:06:48.855238  DQS Delay:

 1257 23:06:48.855304  DQS0 = 0, DQS1 = 0

 1258 23:06:48.858436  DQM Delay:

 1259 23:06:48.858534  DQM0 = 85, DQM1 = 75

 1260 23:06:48.861828  DQ Delay:

 1261 23:06:48.861912  DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85

 1262 23:06:48.865165  DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93

 1263 23:06:48.868654  DQ8 =69, DQ9 =69, DQ10 =69, DQ11 =69

 1264 23:06:48.871472  DQ12 =69, DQ13 =85, DQ14 =85, DQ15 =85

 1265 23:06:48.871574  

 1266 23:06:48.875646  

 1267 23:06:48.875735  ==

 1268 23:06:48.879211  Dram Type= 6, Freq= 0, CH_0, rank 1

 1269 23:06:48.881755  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1270 23:06:48.881841  ==

 1271 23:06:48.881907  

 1272 23:06:48.881968  

 1273 23:06:48.884932  	TX Vref Scan disable

 1274 23:06:48.885018   == TX Byte 0 ==

 1275 23:06:48.892103  Update DQ  dly =582 (2 ,1, 38)  DQ  OEN =(1 ,6)

 1276 23:06:48.895528  Update DQM dly =582 (2 ,1, 38)  DQM OEN =(1 ,6)

 1277 23:06:48.895620   == TX Byte 1 ==

 1278 23:06:48.898393  Update DQ  dly =580 (2 ,1, 36)  DQ  OEN =(1 ,6)

 1279 23:06:48.905476  Update DQM dly =580 (2 ,1, 36)  DQM OEN =(1 ,6)

 1280 23:06:48.905567  ==

 1281 23:06:48.909214  Dram Type= 6, Freq= 0, CH_0, rank 1

 1282 23:06:48.912102  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1283 23:06:48.912187  ==

 1284 23:06:48.925266  TX Vref=22, minBit 2, minWin=27, winSum=443

 1285 23:06:48.928411  TX Vref=24, minBit 2, minWin=27, winSum=446

 1286 23:06:48.931983  TX Vref=26, minBit 3, minWin=27, winSum=447

 1287 23:06:48.935806  TX Vref=28, minBit 3, minWin=27, winSum=454

 1288 23:06:48.938355  TX Vref=30, minBit 3, minWin=28, winSum=457

 1289 23:06:48.942017  TX Vref=32, minBit 0, minWin=28, winSum=453

 1290 23:06:48.948915  [TxChooseVref] Worse bit 3, Min win 28, Win sum 457, Final Vref 30

 1291 23:06:48.949013  

 1292 23:06:48.952329  Final TX Range 1 Vref 30

 1293 23:06:48.952431  

 1294 23:06:48.952497  ==

 1295 23:06:48.955544  Dram Type= 6, Freq= 0, CH_0, rank 1

 1296 23:06:48.959515  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1297 23:06:48.959608  ==

 1298 23:06:48.959673  

 1299 23:06:48.959732  

 1300 23:06:48.962141  	TX Vref Scan disable

 1301 23:06:48.965280   == TX Byte 0 ==

 1302 23:06:48.968693  Update DQ  dly =581 (2 ,1, 37)  DQ  OEN =(1 ,6)

 1303 23:06:48.972144  Update DQM dly =581 (2 ,1, 37)  DQM OEN =(1 ,6)

 1304 23:06:48.975460   == TX Byte 1 ==

 1305 23:06:48.979019  Update DQ  dly =580 (2 ,1, 36)  DQ  OEN =(1 ,6)

 1306 23:06:48.982365  Update DQM dly =580 (2 ,1, 36)  DQM OEN =(1 ,6)

 1307 23:06:48.982491  

 1308 23:06:48.985711  [DATLAT]

 1309 23:06:48.985794  Freq=800, CH0 RK1

 1310 23:06:48.985858  

 1311 23:06:48.989163  DATLAT Default: 0xa

 1312 23:06:48.989245  0, 0xFFFF, sum = 0

 1313 23:06:48.992139  1, 0xFFFF, sum = 0

 1314 23:06:48.992222  2, 0xFFFF, sum = 0

 1315 23:06:48.995846  3, 0xFFFF, sum = 0

 1316 23:06:48.995931  4, 0xFFFF, sum = 0

 1317 23:06:48.999312  5, 0xFFFF, sum = 0

 1318 23:06:48.999396  6, 0xFFFF, sum = 0

 1319 23:06:49.002340  7, 0xFFFF, sum = 0

 1320 23:06:49.002484  8, 0xFFFF, sum = 0

 1321 23:06:49.005574  9, 0x0, sum = 1

 1322 23:06:49.005664  10, 0x0, sum = 2

 1323 23:06:49.009232  11, 0x0, sum = 3

 1324 23:06:49.009317  12, 0x0, sum = 4

 1325 23:06:49.012864  best_step = 10

 1326 23:06:49.012947  

 1327 23:06:49.013010  ==

 1328 23:06:49.016002  Dram Type= 6, Freq= 0, CH_0, rank 1

 1329 23:06:49.019496  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1330 23:06:49.019580  ==

 1331 23:06:49.019644  RX Vref Scan: 0

 1332 23:06:49.019705  

 1333 23:06:49.022773  RX Vref 0 -> 0, step: 1

 1334 23:06:49.022854  

 1335 23:06:49.026347  RX Delay -95 -> 252, step: 8

 1336 23:06:49.029689  iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224

 1337 23:06:49.036346  iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224

 1338 23:06:49.039493  iDelay=209, Bit 2, Center 84 (-31 ~ 200) 232

 1339 23:06:49.042951  iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232

 1340 23:06:49.046222  iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224

 1341 23:06:49.049164  iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232

 1342 23:06:49.052774  iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224

 1343 23:06:49.059343  iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224

 1344 23:06:49.062710  iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216

 1345 23:06:49.066367  iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216

 1346 23:06:49.069491  iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224

 1347 23:06:49.072968  iDelay=209, Bit 11, Center 68 (-39 ~ 176) 216

 1348 23:06:49.079367  iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224

 1349 23:06:49.082427  iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216

 1350 23:06:49.086215  iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224

 1351 23:06:49.089709  iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224

 1352 23:06:49.089802  ==

 1353 23:06:49.092608  Dram Type= 6, Freq= 0, CH_0, rank 1

 1354 23:06:49.099847  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1355 23:06:49.099963  ==

 1356 23:06:49.100029  DQS Delay:

 1357 23:06:49.100089  DQS0 = 0, DQS1 = 0

 1358 23:06:49.102758  DQM Delay:

 1359 23:06:49.102841  DQM0 = 87, DQM1 = 78

 1360 23:06:49.106586  DQ Delay:

 1361 23:06:49.109509  DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84

 1362 23:06:49.109595  DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96

 1363 23:06:49.116061  DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68

 1364 23:06:49.120068  DQ12 =80, DQ13 =84, DQ14 =88, DQ15 =88

 1365 23:06:49.120167  

 1366 23:06:49.120233  

 1367 23:06:49.126796  [DQSOSCAuto] RK1, (LSB)MR18= 0x2d16, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 398 ps

 1368 23:06:49.129964  CH0 RK1: MR19=606, MR18=2D16

 1369 23:06:49.136690  CH0_RK1: MR19=0x606, MR18=0x2D16, DQSOSC=398, MR23=63, INC=93, DEC=62

 1370 23:06:49.140422  [RxdqsGatingPostProcess] freq 800

 1371 23:06:49.143851  ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1

 1372 23:06:49.146609  Pre-setting of DQS Precalculation

 1373 23:06:49.152950  [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10

 1374 23:06:49.153059  ==

 1375 23:06:49.156899  Dram Type= 6, Freq= 0, CH_1, rank 0

 1376 23:06:49.159866  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1377 23:06:49.159955  ==

 1378 23:06:49.166564  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 1379 23:06:49.169637  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34

 1380 23:06:49.179722  [CA 0] Center 36 (6~67) winsize 62

 1381 23:06:49.184450  [CA 1] Center 36 (6~67) winsize 62

 1382 23:06:49.186653  [CA 2] Center 34 (4~64) winsize 61

 1383 23:06:49.190390  [CA 3] Center 33 (3~64) winsize 62

 1384 23:06:49.193439  [CA 4] Center 34 (3~65) winsize 63

 1385 23:06:49.196648  [CA 5] Center 33 (3~64) winsize 62

 1386 23:06:49.196737  

 1387 23:06:49.200266  [CmdBusTrainingLP45] Vref(ca) range 1: 34

 1388 23:06:49.200351  

 1389 23:06:49.203589  [CATrainingPosCal] consider 1 rank data

 1390 23:06:49.206695  u2DelayCellTimex100 = 270/100 ps

 1391 23:06:49.210245  CA0 delay=36 (6~67),Diff = 3 PI (21 cell)

 1392 23:06:49.213439  CA1 delay=36 (6~67),Diff = 3 PI (21 cell)

 1393 23:06:49.217084  CA2 delay=34 (4~64),Diff = 1 PI (7 cell)

 1394 23:06:49.224039  CA3 delay=33 (3~64),Diff = 0 PI (0 cell)

 1395 23:06:49.226992  CA4 delay=34 (3~65),Diff = 1 PI (7 cell)

 1396 23:06:49.230107  CA5 delay=33 (3~64),Diff = 0 PI (0 cell)

 1397 23:06:49.230196  

 1398 23:06:49.233813  CA PerBit enable=1, Macro0, CA PI delay=33

 1399 23:06:49.233932  

 1400 23:06:49.237249  [CBTSetCACLKResult] CA Dly = 33

 1401 23:06:49.237361  CS Dly: 4 (0~35)

 1402 23:06:49.237456  ==

 1403 23:06:49.240573  Dram Type= 6, Freq= 0, CH_1, rank 1

 1404 23:06:49.247118  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1405 23:06:49.247245  ==

 1406 23:06:49.250971  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 1407 23:06:49.257822  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34

 1408 23:06:49.266247  [CA 0] Center 36 (6~67) winsize 62

 1409 23:06:49.269345  [CA 1] Center 36 (6~67) winsize 62

 1410 23:06:49.272941  [CA 2] Center 34 (3~65) winsize 63

 1411 23:06:49.276754  [CA 3] Center 33 (3~64) winsize 62

 1412 23:06:49.279096  [CA 4] Center 34 (3~65) winsize 63

 1413 23:06:49.282946  [CA 5] Center 33 (3~64) winsize 62

 1414 23:06:49.283062  

 1415 23:06:49.286629  [CmdBusTrainingLP45] Vref(ca) range 1: 32

 1416 23:06:49.286746  

 1417 23:06:49.289953  [CATrainingPosCal] consider 2 rank data

 1418 23:06:49.293455  u2DelayCellTimex100 = 270/100 ps

 1419 23:06:49.296820  CA0 delay=36 (6~67),Diff = 3 PI (21 cell)

 1420 23:06:49.300920  CA1 delay=36 (6~67),Diff = 3 PI (21 cell)

 1421 23:06:49.304673  CA2 delay=34 (4~64),Diff = 1 PI (7 cell)

 1422 23:06:49.308207  CA3 delay=33 (3~64),Diff = 0 PI (0 cell)

 1423 23:06:49.311807  CA4 delay=34 (3~65),Diff = 1 PI (7 cell)

 1424 23:06:49.316386  CA5 delay=33 (3~64),Diff = 0 PI (0 cell)

 1425 23:06:49.316518  

 1426 23:06:49.319964  CA PerBit enable=1, Macro0, CA PI delay=33

 1427 23:06:49.320079  

 1428 23:06:49.324006  [CBTSetCACLKResult] CA Dly = 33

 1429 23:06:49.324122  CS Dly: 5 (0~37)

 1430 23:06:49.324218  

 1431 23:06:49.327205  ----->DramcWriteLeveling(PI) begin...

 1432 23:06:49.327318  ==

 1433 23:06:49.330165  Dram Type= 6, Freq= 0, CH_1, rank 0

 1434 23:06:49.333979  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1435 23:06:49.334093  ==

 1436 23:06:49.337917  Write leveling (Byte 0): 26 => 26

 1437 23:06:49.340103  Write leveling (Byte 1): 29 => 29

 1438 23:06:49.343997  DramcWriteLeveling(PI) end<-----

 1439 23:06:49.344110  

 1440 23:06:49.344202  ==

 1441 23:06:49.348143  Dram Type= 6, Freq= 0, CH_1, rank 0

 1442 23:06:49.350684  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1443 23:06:49.353895  ==

 1444 23:06:49.354012  [Gating] SW mode calibration

 1445 23:06:49.361647  [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

 1446 23:06:49.367471  RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)

 1447 23:06:49.371219   0  6  0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)

 1448 23:06:49.377531   0  6  4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)

 1449 23:06:49.381006   0  6  8 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)

 1450 23:06:49.384126   0  6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1451 23:06:49.387358   0  6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1452 23:06:49.394742   0  6 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)

 1453 23:06:49.397838   0  6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1454 23:06:49.401456   0  6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1455 23:06:49.407597   0  7  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1456 23:06:49.411032   0  7  4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)

 1457 23:06:49.414121   0  7  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1458 23:06:49.421612   0  7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1459 23:06:49.425353   0  7 16 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)

 1460 23:06:49.427973   0  7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1461 23:06:49.434890   0  7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1462 23:06:49.437956   0  7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1463 23:06:49.441273   0  8  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1464 23:06:49.445204   0  8  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1465 23:06:49.451753   0  8  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)

 1466 23:06:49.454939   0  8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1467 23:06:49.458313   0  8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1468 23:06:49.465410   0  8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1469 23:06:49.468581   0  8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1470 23:06:49.471599   0  8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1471 23:06:49.478123   0  9  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1472 23:06:49.481650   0  9  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1473 23:06:49.484648   0  9  8 | B1->B0 | 2828 2525 | 1 1 | (0 0) (0 0)

 1474 23:06:49.491808   0  9 12 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)

 1475 23:06:49.495479   0  9 16 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)

 1476 23:06:49.498166   0  9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1477 23:06:49.505218   0  9 24 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)

 1478 23:06:49.508290   0  9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1479 23:06:49.511895   0 10  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1480 23:06:49.515133   0 10  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1481 23:06:49.521627   0 10  8 | B1->B0 | 2e2e 3232 | 0 0 | (0 0) (0 1)

 1482 23:06:49.525736   0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1483 23:06:49.528390   0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1484 23:06:49.535353   0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1485 23:06:49.538323   0 10 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)

 1486 23:06:49.542220   0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1487 23:06:49.548498   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1488 23:06:49.552077   0 11  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1489 23:06:49.555553   0 11  8 | B1->B0 | 3434 3535 | 0 0 | (0 0) (0 0)

 1490 23:06:49.562601   0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1491 23:06:49.565344   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1492 23:06:49.568740   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1493 23:06:49.572087   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1494 23:06:49.578787   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1495 23:06:49.582210   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1496 23:06:49.585781   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1497 23:06:49.592576   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 1498 23:06:49.595938   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1499 23:06:49.598861   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1500 23:06:49.605758   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1501 23:06:49.609323   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1502 23:06:49.612286   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1503 23:06:49.619597   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1504 23:06:49.622331   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1505 23:06:49.625790   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1506 23:06:49.632988   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1507 23:06:49.636178   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1508 23:06:49.639027   0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1509 23:06:49.642693   0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1510 23:06:49.649347   0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1511 23:06:49.653056   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1512 23:06:49.656309   0 14  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1513 23:06:49.663162   0 14  8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 1514 23:06:49.666351   0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1515 23:06:49.669462  Total UI for P1: 0, mck2ui 16

 1516 23:06:49.672842  best dqsien dly found for B0: ( 0, 14,  8)

 1517 23:06:49.676119  Total UI for P1: 0, mck2ui 16

 1518 23:06:49.679689  best dqsien dly found for B1: ( 0, 14,  8)

 1519 23:06:49.683259  best DQS0 dly(MCK, UI, PI) = (0, 14, 8)

 1520 23:06:49.686367  best DQS1 dly(MCK, UI, PI) = (0, 14, 8)

 1521 23:06:49.686496  

 1522 23:06:49.689709  best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)

 1523 23:06:49.693085  best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)

 1524 23:06:49.696842  [Gating] SW calibration Done

 1525 23:06:49.696960  ==

 1526 23:06:49.699884  Dram Type= 6, Freq= 0, CH_1, rank 0

 1527 23:06:49.702940  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1528 23:06:49.703057  ==

 1529 23:06:49.706168  RX Vref Scan: 0

 1530 23:06:49.706281  

 1531 23:06:49.706376  RX Vref 0 -> 0, step: 1

 1532 23:06:49.710106  

 1533 23:06:49.710218  RX Delay -130 -> 252, step: 16

 1534 23:06:49.716215  iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240

 1535 23:06:49.719913  iDelay=206, Bit 1, Center 69 (-50 ~ 189) 240

 1536 23:06:49.722999  iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240

 1537 23:06:49.726869  iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240

 1538 23:06:49.729591  iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240

 1539 23:06:49.737194  iDelay=206, Bit 5, Center 85 (-34 ~ 205) 240

 1540 23:06:49.739964  iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224

 1541 23:06:49.743307  iDelay=206, Bit 7, Center 69 (-50 ~ 189) 240

 1542 23:06:49.746628  iDelay=206, Bit 8, Center 61 (-66 ~ 189) 256

 1543 23:06:49.749851  iDelay=206, Bit 9, Center 53 (-66 ~ 173) 240

 1544 23:06:49.753065  iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240

 1545 23:06:49.759757  iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240

 1546 23:06:49.763189  iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240

 1547 23:06:49.766950  iDelay=206, Bit 13, Center 77 (-50 ~ 205) 256

 1548 23:06:49.770332  iDelay=206, Bit 14, Center 77 (-50 ~ 205) 256

 1549 23:06:49.773613  iDelay=206, Bit 15, Center 77 (-50 ~ 205) 256

 1550 23:06:49.777145  ==

 1551 23:06:49.780423  Dram Type= 6, Freq= 0, CH_1, rank 0

 1552 23:06:49.784101  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1553 23:06:49.784224  ==

 1554 23:06:49.784321  DQS Delay:

 1555 23:06:49.786645  DQS0 = 0, DQS1 = 0

 1556 23:06:49.786756  DQM Delay:

 1557 23:06:49.790999  DQM0 = 80, DQM1 = 71

 1558 23:06:49.791113  DQ Delay:

 1559 23:06:49.793714  DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =85

 1560 23:06:49.796844  DQ4 =85, DQ5 =85, DQ6 =93, DQ7 =69

 1561 23:06:49.800368  DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =69

 1562 23:06:49.804021  DQ12 =85, DQ13 =77, DQ14 =77, DQ15 =77

 1563 23:06:49.804140  

 1564 23:06:49.804231  

 1565 23:06:49.804320  ==

 1566 23:06:49.807397  Dram Type= 6, Freq= 0, CH_1, rank 0

 1567 23:06:49.810218  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1568 23:06:49.810342  ==

 1569 23:06:49.810446  

 1570 23:06:49.810538  

 1571 23:06:49.814096  	TX Vref Scan disable

 1572 23:06:49.814210   == TX Byte 0 ==

 1573 23:06:49.820351  Update DQ  dly =577 (2 ,1, 33)  DQ  OEN =(1 ,6)

 1574 23:06:49.824228  Update DQM dly =577 (2 ,1, 33)  DQM OEN =(1 ,6)

 1575 23:06:49.824344   == TX Byte 1 ==

 1576 23:06:49.830372  Update DQ  dly =580 (2 ,1, 36)  DQ  OEN =(1 ,6)

 1577 23:06:49.834244  Update DQM dly =580 (2 ,1, 36)  DQM OEN =(1 ,6)

 1578 23:06:49.834367  ==

 1579 23:06:49.837368  Dram Type= 6, Freq= 0, CH_1, rank 0

 1580 23:06:49.840812  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1581 23:06:49.840929  ==

 1582 23:06:49.854982  TX Vref=22, minBit 8, minWin=26, winSum=434

 1583 23:06:49.858277  TX Vref=24, minBit 11, minWin=26, winSum=437

 1584 23:06:49.861655  TX Vref=26, minBit 8, minWin=27, winSum=443

 1585 23:06:49.864752  TX Vref=28, minBit 8, minWin=27, winSum=446

 1586 23:06:49.868354  TX Vref=30, minBit 10, minWin=27, winSum=450

 1587 23:06:49.872045  TX Vref=32, minBit 0, minWin=28, winSum=451

 1588 23:06:49.879219  [TxChooseVref] Worse bit 0, Min win 28, Win sum 451, Final Vref 32

 1589 23:06:49.879374  

 1590 23:06:49.883045  Final TX Range 1 Vref 32

 1591 23:06:49.883170  

 1592 23:06:49.883265  ==

 1593 23:06:49.886074  Dram Type= 6, Freq= 0, CH_1, rank 0

 1594 23:06:49.889483  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1595 23:06:49.889599  ==

 1596 23:06:49.889697  

 1597 23:06:49.889789  

 1598 23:06:49.892921  	TX Vref Scan disable

 1599 23:06:49.896595   == TX Byte 0 ==

 1600 23:06:49.899043  Update DQ  dly =577 (2 ,1, 33)  DQ  OEN =(1 ,6)

 1601 23:06:49.902570  Update DQM dly =577 (2 ,1, 33)  DQM OEN =(1 ,6)

 1602 23:06:49.906211   == TX Byte 1 ==

 1603 23:06:49.908931  Update DQ  dly =579 (2 ,1, 35)  DQ  OEN =(1 ,6)

 1604 23:06:49.912333  Update DQM dly =579 (2 ,1, 35)  DQM OEN =(1 ,6)

 1605 23:06:49.912448  

 1606 23:06:49.915881  [DATLAT]

 1607 23:06:49.915990  Freq=800, CH1 RK0

 1608 23:06:49.916084  

 1609 23:06:49.919553  DATLAT Default: 0xa

 1610 23:06:49.919666  0, 0xFFFF, sum = 0

 1611 23:06:49.922603  1, 0xFFFF, sum = 0

 1612 23:06:49.922718  2, 0xFFFF, sum = 0

 1613 23:06:49.925690  3, 0xFFFF, sum = 0

 1614 23:06:49.925804  4, 0xFFFF, sum = 0

 1615 23:06:49.929233  5, 0xFFFF, sum = 0

 1616 23:06:49.929346  6, 0xFFFF, sum = 0

 1617 23:06:49.933597  7, 0xFFFF, sum = 0

 1618 23:06:49.933715  8, 0xFFFF, sum = 0

 1619 23:06:49.936324  9, 0x0, sum = 1

 1620 23:06:49.936434  10, 0x0, sum = 2

 1621 23:06:49.939992  11, 0x0, sum = 3

 1622 23:06:49.940117  12, 0x0, sum = 4

 1623 23:06:49.940218  best_step = 10

 1624 23:06:49.942615  

 1625 23:06:49.942725  ==

 1626 23:06:49.946177  Dram Type= 6, Freq= 0, CH_1, rank 0

 1627 23:06:49.949329  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1628 23:06:49.949448  ==

 1629 23:06:49.949544  RX Vref Scan: 1

 1630 23:06:49.949636  

 1631 23:06:49.952379  Set Vref Range= 32 -> 127

 1632 23:06:49.952488  

 1633 23:06:49.956116  RX Vref 32 -> 127, step: 1

 1634 23:06:49.956227  

 1635 23:06:49.959765  RX Delay -111 -> 252, step: 8

 1636 23:06:49.959878  

 1637 23:06:49.963304  Set Vref, RX VrefLevel [Byte0]: 32

 1638 23:06:49.965808                           [Byte1]: 32

 1639 23:06:49.965916  

 1640 23:06:49.969610  Set Vref, RX VrefLevel [Byte0]: 33

 1641 23:06:49.972557                           [Byte1]: 33

 1642 23:06:49.972670  

 1643 23:06:49.976715  Set Vref, RX VrefLevel [Byte0]: 34

 1644 23:06:49.980112                           [Byte1]: 34

 1645 23:06:49.982696  

 1646 23:06:49.982812  Set Vref, RX VrefLevel [Byte0]: 35

 1647 23:06:49.986227                           [Byte1]: 35

 1648 23:06:49.991316  

 1649 23:06:49.991443  Set Vref, RX VrefLevel [Byte0]: 36

 1650 23:06:49.993628                           [Byte1]: 36

 1651 23:06:49.998161  

 1652 23:06:49.998281  Set Vref, RX VrefLevel [Byte0]: 37

 1653 23:06:50.001593                           [Byte1]: 37

 1654 23:06:50.005863  

 1655 23:06:50.005976  Set Vref, RX VrefLevel [Byte0]: 38

 1656 23:06:50.009584                           [Byte1]: 38

 1657 23:06:50.013833  

 1658 23:06:50.013947  Set Vref, RX VrefLevel [Byte0]: 39

 1659 23:06:50.017135                           [Byte1]: 39

 1660 23:06:50.021454  

 1661 23:06:50.021568  Set Vref, RX VrefLevel [Byte0]: 40

 1662 23:06:50.024586                           [Byte1]: 40

 1663 23:06:50.028916  

 1664 23:06:50.029033  Set Vref, RX VrefLevel [Byte0]: 41

 1665 23:06:50.032534                           [Byte1]: 41

 1666 23:06:50.036437  

 1667 23:06:50.036556  Set Vref, RX VrefLevel [Byte0]: 42

 1668 23:06:50.039950                           [Byte1]: 42

 1669 23:06:50.044572  

 1670 23:06:50.044690  Set Vref, RX VrefLevel [Byte0]: 43

 1671 23:06:50.048064                           [Byte1]: 43

 1672 23:06:50.051762  

 1673 23:06:50.051871  Set Vref, RX VrefLevel [Byte0]: 44

 1674 23:06:50.055131                           [Byte1]: 44

 1675 23:06:50.060079  

 1676 23:06:50.060204  Set Vref, RX VrefLevel [Byte0]: 45

 1677 23:06:50.062856                           [Byte1]: 45

 1678 23:06:50.067365  

 1679 23:06:50.067486  Set Vref, RX VrefLevel [Byte0]: 46

 1680 23:06:50.071142                           [Byte1]: 46

 1681 23:06:50.074649  

 1682 23:06:50.077991  Set Vref, RX VrefLevel [Byte0]: 47

 1683 23:06:50.078106                           [Byte1]: 47

 1684 23:06:50.082705  

 1685 23:06:50.082827  Set Vref, RX VrefLevel [Byte0]: 48

 1686 23:06:50.085758                           [Byte1]: 48

 1687 23:06:50.090701  

 1688 23:06:50.090823  Set Vref, RX VrefLevel [Byte0]: 49

 1689 23:06:50.093061                           [Byte1]: 49

 1690 23:06:50.097747  

 1691 23:06:50.097870  Set Vref, RX VrefLevel [Byte0]: 50

 1692 23:06:50.101632                           [Byte1]: 50

 1693 23:06:50.105454  

 1694 23:06:50.105570  Set Vref, RX VrefLevel [Byte0]: 51

 1695 23:06:50.108735                           [Byte1]: 51

 1696 23:06:50.112933  

 1697 23:06:50.113050  Set Vref, RX VrefLevel [Byte0]: 52

 1698 23:06:50.116561                           [Byte1]: 52

 1699 23:06:50.120869  

 1700 23:06:50.120985  Set Vref, RX VrefLevel [Byte0]: 53

 1701 23:06:50.123621                           [Byte1]: 53

 1702 23:06:50.128643  

 1703 23:06:50.128775  Set Vref, RX VrefLevel [Byte0]: 54

 1704 23:06:50.132089                           [Byte1]: 54

 1705 23:06:50.136106  

 1706 23:06:50.136225  Set Vref, RX VrefLevel [Byte0]: 55

 1707 23:06:50.139269                           [Byte1]: 55

 1708 23:06:50.143646  

 1709 23:06:50.143763  Set Vref, RX VrefLevel [Byte0]: 56

 1710 23:06:50.147211                           [Byte1]: 56

 1711 23:06:50.151599  

 1712 23:06:50.151714  Set Vref, RX VrefLevel [Byte0]: 57

 1713 23:06:50.154338                           [Byte1]: 57

 1714 23:06:50.158884  

 1715 23:06:50.159001  Set Vref, RX VrefLevel [Byte0]: 58

 1716 23:06:50.162149                           [Byte1]: 58

 1717 23:06:50.166305  

 1718 23:06:50.166478  Set Vref, RX VrefLevel [Byte0]: 59

 1719 23:06:50.169941                           [Byte1]: 59

 1720 23:06:50.174128  

 1721 23:06:50.174245  Set Vref, RX VrefLevel [Byte0]: 60

 1722 23:06:50.177479                           [Byte1]: 60

 1723 23:06:50.182007  

 1724 23:06:50.182138  Set Vref, RX VrefLevel [Byte0]: 61

 1725 23:06:50.185247                           [Byte1]: 61

 1726 23:06:50.189430  

 1727 23:06:50.189552  Set Vref, RX VrefLevel [Byte0]: 62

 1728 23:06:50.193044                           [Byte1]: 62

 1729 23:06:50.197824  

 1730 23:06:50.197923  Set Vref, RX VrefLevel [Byte0]: 63

 1731 23:06:50.200105                           [Byte1]: 63

 1732 23:06:50.204516  

 1733 23:06:50.204618  Set Vref, RX VrefLevel [Byte0]: 64

 1734 23:06:50.207795                           [Byte1]: 64

 1735 23:06:50.212176  

 1736 23:06:50.212279  Set Vref, RX VrefLevel [Byte0]: 65

 1737 23:06:50.215655                           [Byte1]: 65

 1738 23:06:50.220166  

 1739 23:06:50.220281  Set Vref, RX VrefLevel [Byte0]: 66

 1740 23:06:50.223194                           [Byte1]: 66

 1741 23:06:50.227428  

 1742 23:06:50.227528  Set Vref, RX VrefLevel [Byte0]: 67

 1743 23:06:50.230704                           [Byte1]: 67

 1744 23:06:50.235746  

 1745 23:06:50.235859  Set Vref, RX VrefLevel [Byte0]: 68

 1746 23:06:50.238615                           [Byte1]: 68

 1747 23:06:50.243107  

 1748 23:06:50.243225  Set Vref, RX VrefLevel [Byte0]: 69

 1749 23:06:50.246208                           [Byte1]: 69

 1750 23:06:50.250638  

 1751 23:06:50.250743  Set Vref, RX VrefLevel [Byte0]: 70

 1752 23:06:50.253865                           [Byte1]: 70

 1753 23:06:50.258291  

 1754 23:06:50.258475  Set Vref, RX VrefLevel [Byte0]: 71

 1755 23:06:50.262020                           [Byte1]: 71

 1756 23:06:50.266130  

 1757 23:06:50.266260  Set Vref, RX VrefLevel [Byte0]: 72

 1758 23:06:50.269691                           [Byte1]: 72

 1759 23:06:50.273285  

 1760 23:06:50.273382  Set Vref, RX VrefLevel [Byte0]: 73

 1761 23:06:50.276502                           [Byte1]: 73

 1762 23:06:50.281989  

 1763 23:06:50.282114  Set Vref, RX VrefLevel [Byte0]: 74

 1764 23:06:50.284481                           [Byte1]: 74

 1765 23:06:50.288910  

 1766 23:06:50.289026  Set Vref, RX VrefLevel [Byte0]: 75

 1767 23:06:50.292171                           [Byte1]: 75

 1768 23:06:50.296757  

 1769 23:06:50.296879  Set Vref, RX VrefLevel [Byte0]: 76

 1770 23:06:50.299874                           [Byte1]: 76

 1771 23:06:50.304536  

 1772 23:06:50.304656  Set Vref, RX VrefLevel [Byte0]: 77

 1773 23:06:50.307325                           [Byte1]: 77

 1774 23:06:50.312108  

 1775 23:06:50.312226  Final RX Vref Byte 0 = 60 to rank0

 1776 23:06:50.315307  Final RX Vref Byte 1 = 60 to rank0

 1777 23:06:50.318833  Final RX Vref Byte 0 = 60 to rank1

 1778 23:06:50.322226  Final RX Vref Byte 1 = 60 to rank1==

 1779 23:06:50.325018  Dram Type= 6, Freq= 0, CH_1, rank 0

 1780 23:06:50.328751  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1781 23:06:50.331728  ==

 1782 23:06:50.331827  DQS Delay:

 1783 23:06:50.331893  DQS0 = 0, DQS1 = 0

 1784 23:06:50.335297  DQM Delay:

 1785 23:06:50.335387  DQM0 = 82, DQM1 = 73

 1786 23:06:50.339346  DQ Delay:

 1787 23:06:50.341698  DQ0 =84, DQ1 =76, DQ2 =72, DQ3 =84

 1788 23:06:50.341789  DQ4 =80, DQ5 =92, DQ6 =92, DQ7 =80

 1789 23:06:50.345766  DQ8 =60, DQ9 =60, DQ10 =76, DQ11 =72

 1790 23:06:50.348567  DQ12 =84, DQ13 =80, DQ14 =80, DQ15 =76

 1791 23:06:50.348662  

 1792 23:06:50.352547  

 1793 23:06:50.358609  [DQSOSCAuto] RK0, (LSB)MR18= 0x28fe, (MSB)MR19= 0x605, tDQSOscB0 = 410 ps tDQSOscB1 = 399 ps

 1794 23:06:50.362305  CH1 RK0: MR19=605, MR18=28FE

 1795 23:06:50.368543  CH1_RK0: MR19=0x605, MR18=0x28FE, DQSOSC=399, MR23=63, INC=92, DEC=61

 1796 23:06:50.368685  

 1797 23:06:50.372541  ----->DramcWriteLeveling(PI) begin...

 1798 23:06:50.372640  ==

 1799 23:06:50.375532  Dram Type= 6, Freq= 0, CH_1, rank 1

 1800 23:06:50.379664  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1801 23:06:50.379768  ==

 1802 23:06:50.382583  Write leveling (Byte 0): 26 => 26

 1803 23:06:50.385489  Write leveling (Byte 1): 28 => 28

 1804 23:06:50.389309  DramcWriteLeveling(PI) end<-----

 1805 23:06:50.389421  

 1806 23:06:50.389488  ==

 1807 23:06:50.392512  Dram Type= 6, Freq= 0, CH_1, rank 1

 1808 23:06:50.395467  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1809 23:06:50.395565  ==

 1810 23:06:50.398844  [Gating] SW mode calibration

 1811 23:06:50.405947  [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

 1812 23:06:50.412591  RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)

 1813 23:06:50.416023   0  6  0 | B1->B0 | 2323 2323 | 1 0 | (1 1) (1 1)

 1814 23:06:50.419111   0  6  4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)

 1815 23:06:50.422174   0  6  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1816 23:06:50.429751   0  6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1817 23:06:50.432344   0  6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1818 23:06:50.435984   0  6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1819 23:06:50.442436   0  6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1820 23:06:50.445645   0  6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1821 23:06:50.449288   0  7  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1822 23:06:50.455859   0  7  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1823 23:06:50.459281   0  7  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1824 23:06:50.462482   0  7 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)

 1825 23:06:50.469193   0  7 16 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)

 1826 23:06:50.473556   0  7 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)

 1827 23:06:50.475996   0  7 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)

 1828 23:06:50.483000   0  7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1829 23:06:50.485809   0  8  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)

 1830 23:06:50.489160   0  8  4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)

 1831 23:06:50.492756   0  8  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1832 23:06:50.499589   0  8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1833 23:06:50.503054   0  8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1834 23:06:50.505998   0  8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1835 23:06:50.512796   0  8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1836 23:06:50.516738   0  8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1837 23:06:50.519787   0  9  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1838 23:06:50.526178   0  9  4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)

 1839 23:06:50.529934   0  9  8 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)

 1840 23:06:50.533431   0  9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1841 23:06:50.539966   0  9 16 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)

 1842 23:06:50.543267   0  9 20 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)

 1843 23:06:50.546334   0  9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1844 23:06:50.549505   0  9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1845 23:06:50.556723   0 10  0 | B1->B0 | 3535 3434 | 0 0 | (0 0) (0 0)

 1846 23:06:50.560507   0 10  4 | B1->B0 | 3131 2f2f | 0 0 | (0 0) (0 1)

 1847 23:06:50.563697   0 10  8 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)

 1848 23:06:50.570061   0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1849 23:06:50.573744   0 10 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)

 1850 23:06:50.576377   0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1851 23:06:50.583653   0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1852 23:06:50.587034   0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1853 23:06:50.590339   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1854 23:06:50.596853   0 11  4 | B1->B0 | 2b2b 3737 | 0 0 | (0 0) (0 0)

 1855 23:06:50.600177   0 11  8 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)

 1856 23:06:50.603450   0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1857 23:06:50.609948   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1858 23:06:50.613287   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1859 23:06:50.616751   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1860 23:06:50.621039   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1861 23:06:50.627549   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 1862 23:06:50.630929   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)

 1863 23:06:50.633476   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 1864 23:06:50.640339   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1865 23:06:50.643739   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1866 23:06:50.646838   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1867 23:06:50.654152   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1868 23:06:50.657554   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1869 23:06:50.660180   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1870 23:06:50.667837   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1871 23:06:50.670408   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1872 23:06:50.674049   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1873 23:06:50.677516   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1874 23:06:50.685186   0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1875 23:06:50.687355   0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1876 23:06:50.690427   0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1877 23:06:50.697557   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1878 23:06:50.701208   0 14  4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 1879 23:06:50.703987   0 14  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1880 23:06:50.707417  Total UI for P1: 0, mck2ui 16

 1881 23:06:50.711244  best dqsien dly found for B0: ( 0, 14,  4)

 1882 23:06:50.714726  Total UI for P1: 0, mck2ui 16

 1883 23:06:50.717674  best dqsien dly found for B1: ( 0, 14,  4)

 1884 23:06:50.721078  best DQS0 dly(MCK, UI, PI) = (0, 14, 4)

 1885 23:06:50.724523  best DQS1 dly(MCK, UI, PI) = (0, 14, 4)

 1886 23:06:50.724643  

 1887 23:06:50.727453  best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)

 1888 23:06:50.734233  best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)

 1889 23:06:50.734372  [Gating] SW calibration Done

 1890 23:06:50.734505  ==

 1891 23:06:50.737864  Dram Type= 6, Freq= 0, CH_1, rank 1

 1892 23:06:50.744424  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1893 23:06:50.744561  ==

 1894 23:06:50.744628  RX Vref Scan: 0

 1895 23:06:50.744689  

 1896 23:06:50.747679  RX Vref 0 -> 0, step: 1

 1897 23:06:50.747773  

 1898 23:06:50.751179  RX Delay -130 -> 252, step: 16

 1899 23:06:50.754593  iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240

 1900 23:06:50.757708  iDelay=206, Bit 1, Center 69 (-50 ~ 189) 240

 1901 23:06:50.761284  iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240

 1902 23:06:50.764400  iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240

 1903 23:06:50.771420  iDelay=206, Bit 4, Center 77 (-50 ~ 205) 256

 1904 23:06:50.774681  iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224

 1905 23:06:50.778204  iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240

 1906 23:06:50.781340  iDelay=206, Bit 7, Center 69 (-50 ~ 189) 240

 1907 23:06:50.784320  iDelay=206, Bit 8, Center 61 (-66 ~ 189) 256

 1908 23:06:50.791488  iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240

 1909 23:06:50.794870  iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240

 1910 23:06:50.797868  iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240

 1911 23:06:50.801654  iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240

 1912 23:06:50.804985  iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240

 1913 23:06:50.811619  iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240

 1914 23:06:50.815039  iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240

 1915 23:06:50.815156  ==

 1916 23:06:50.817875  Dram Type= 6, Freq= 0, CH_1, rank 1

 1917 23:06:50.821650  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1918 23:06:50.821771  ==

 1919 23:06:50.821839  DQS Delay:

 1920 23:06:50.825012  DQS0 = 0, DQS1 = 0

 1921 23:06:50.825106  DQM Delay:

 1922 23:06:50.827939  DQM0 = 79, DQM1 = 76

 1923 23:06:50.828033  DQ Delay:

 1924 23:06:50.831681  DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =85

 1925 23:06:50.835152  DQ4 =77, DQ5 =93, DQ6 =85, DQ7 =69

 1926 23:06:50.838746  DQ8 =61, DQ9 =69, DQ10 =69, DQ11 =69

 1927 23:06:50.842361  DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85

 1928 23:06:50.842515  

 1929 23:06:50.842582  

 1930 23:06:50.842644  ==

 1931 23:06:50.845105  Dram Type= 6, Freq= 0, CH_1, rank 1

 1932 23:06:50.848605  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1933 23:06:50.851434  ==

 1934 23:06:50.851539  

 1935 23:06:50.851605  

 1936 23:06:50.851666  	TX Vref Scan disable

 1937 23:06:50.855371   == TX Byte 0 ==

 1938 23:06:50.858733  Update DQ  dly =576 (2 ,1, 32)  DQ  OEN =(1 ,6)

 1939 23:06:50.862190  Update DQM dly =576 (2 ,1, 32)  DQM OEN =(1 ,6)

 1940 23:06:50.865064   == TX Byte 1 ==

 1941 23:06:50.868787  Update DQ  dly =578 (2 ,1, 34)  DQ  OEN =(1 ,6)

 1942 23:06:50.872415  Update DQM dly =578 (2 ,1, 34)  DQM OEN =(1 ,6)

 1943 23:06:50.872536  ==

 1944 23:06:50.876087  Dram Type= 6, Freq= 0, CH_1, rank 1

 1945 23:06:50.882363  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1946 23:06:50.882534  ==

 1947 23:06:50.893424  TX Vref=22, minBit 5, minWin=27, winSum=441

 1948 23:06:50.896822  TX Vref=24, minBit 5, minWin=27, winSum=441

 1949 23:06:50.900546  TX Vref=26, minBit 5, minWin=27, winSum=445

 1950 23:06:50.904248  TX Vref=28, minBit 0, minWin=27, winSum=450

 1951 23:06:50.906995  TX Vref=30, minBit 10, minWin=27, winSum=449

 1952 23:06:50.910634  TX Vref=32, minBit 0, minWin=28, winSum=455

 1953 23:06:50.917798  [TxChooseVref] Worse bit 0, Min win 28, Win sum 455, Final Vref 32

 1954 23:06:50.917948  

 1955 23:06:50.920839  Final TX Range 1 Vref 32

 1956 23:06:50.920936  

 1957 23:06:50.921002  ==

 1958 23:06:50.923814  Dram Type= 6, Freq= 0, CH_1, rank 1

 1959 23:06:50.927321  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1960 23:06:50.927435  ==

 1961 23:06:50.927501  

 1962 23:06:50.927562  

 1963 23:06:50.930454  	TX Vref Scan disable

 1964 23:06:50.934188   == TX Byte 0 ==

 1965 23:06:50.937201  Update DQ  dly =576 (2 ,1, 32)  DQ  OEN =(1 ,6)

 1966 23:06:50.941073  Update DQM dly =576 (2 ,1, 32)  DQM OEN =(1 ,6)

 1967 23:06:50.943937   == TX Byte 1 ==

 1968 23:06:50.947119  Update DQ  dly =578 (2 ,1, 34)  DQ  OEN =(1 ,6)

 1969 23:06:50.950775  Update DQM dly =578 (2 ,1, 34)  DQM OEN =(1 ,6)

 1970 23:06:50.950891  

 1971 23:06:50.954551  [DATLAT]

 1972 23:06:50.954679  Freq=800, CH1 RK1

 1973 23:06:50.954747  

 1974 23:06:50.957178  DATLAT Default: 0xa

 1975 23:06:50.957275  0, 0xFFFF, sum = 0

 1976 23:06:50.960464  1, 0xFFFF, sum = 0

 1977 23:06:50.960565  2, 0xFFFF, sum = 0

 1978 23:06:50.963945  3, 0xFFFF, sum = 0

 1979 23:06:50.964046  4, 0xFFFF, sum = 0

 1980 23:06:50.967628  5, 0xFFFF, sum = 0

 1981 23:06:50.967726  6, 0xFFFF, sum = 0

 1982 23:06:50.971230  7, 0xFFFF, sum = 0

 1983 23:06:50.971331  8, 0xFFFF, sum = 0

 1984 23:06:50.974381  9, 0x0, sum = 1

 1985 23:06:50.974521  10, 0x0, sum = 2

 1986 23:06:50.978211  11, 0x0, sum = 3

 1987 23:06:50.978338  12, 0x0, sum = 4

 1988 23:06:50.980972  best_step = 10

 1989 23:06:50.981063  

 1990 23:06:50.981130  ==

 1991 23:06:50.984026  Dram Type= 6, Freq= 0, CH_1, rank 1

 1992 23:06:50.987888  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1993 23:06:50.988002  ==

 1994 23:06:50.988070  RX Vref Scan: 0

 1995 23:06:50.991028  

 1996 23:06:50.991122  RX Vref 0 -> 0, step: 1

 1997 23:06:50.991190  

 1998 23:06:50.994885  RX Delay -111 -> 252, step: 8

 1999 23:06:51.000709  iDelay=209, Bit 0, Center 84 (-31 ~ 200) 232

 2000 23:06:51.005048  iDelay=209, Bit 1, Center 76 (-39 ~ 192) 232

 2001 23:06:51.007620  iDelay=209, Bit 2, Center 68 (-47 ~ 184) 232

 2002 23:06:51.011075  iDelay=209, Bit 3, Center 76 (-39 ~ 192) 232

 2003 23:06:51.014874  iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232

 2004 23:06:51.017495  iDelay=209, Bit 5, Center 92 (-23 ~ 208) 232

 2005 23:06:51.024602  iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232

 2006 23:06:51.028068  iDelay=209, Bit 7, Center 76 (-39 ~ 192) 232

 2007 23:06:51.031151  iDelay=209, Bit 8, Center 64 (-55 ~ 184) 240

 2008 23:06:51.034339  iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224

 2009 23:06:51.038070  iDelay=209, Bit 10, Center 76 (-39 ~ 192) 232

 2010 23:06:51.045064  iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232

 2011 23:06:51.048012  iDelay=209, Bit 12, Center 84 (-31 ~ 200) 232

 2012 23:06:51.051481  iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232

 2013 23:06:51.054565  iDelay=209, Bit 14, Center 84 (-31 ~ 200) 232

 2014 23:06:51.058754  iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232

 2015 23:06:51.058896  ==

 2016 23:06:51.061427  Dram Type= 6, Freq= 0, CH_1, rank 1

 2017 23:06:51.067889  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2018 23:06:51.068039  ==

 2019 23:06:51.068109  DQS Delay:

 2020 23:06:51.071348  DQS0 = 0, DQS1 = 0

 2021 23:06:51.071450  DQM Delay:

 2022 23:06:51.071519  DQM0 = 81, DQM1 = 76

 2023 23:06:51.075099  DQ Delay:

 2024 23:06:51.078486  DQ0 =84, DQ1 =76, DQ2 =68, DQ3 =76

 2025 23:06:51.081422  DQ4 =84, DQ5 =92, DQ6 =92, DQ7 =76

 2026 23:06:51.085064  DQ8 =64, DQ9 =64, DQ10 =76, DQ11 =68

 2027 23:06:51.088106  DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =84

 2028 23:06:51.088225  

 2029 23:06:51.088294  

 2030 23:06:51.095014  [DQSOSCAuto] RK1, (LSB)MR18= 0x2530, (MSB)MR19= 0x606, tDQSOscB0 = 397 ps tDQSOscB1 = 400 ps

 2031 23:06:51.098450  CH1 RK1: MR19=606, MR18=2530

 2032 23:06:51.105151  CH1_RK1: MR19=0x606, MR18=0x2530, DQSOSC=397, MR23=63, INC=93, DEC=62

 2033 23:06:51.108394  [RxdqsGatingPostProcess] freq 800

 2034 23:06:51.111886  ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1

 2035 23:06:51.114916  Pre-setting of DQS Precalculation

 2036 23:06:51.121822  [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10

 2037 23:06:51.128993  sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4

 2038 23:06:51.134925  calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464

 2039 23:06:51.135073  

 2040 23:06:51.135144  

 2041 23:06:51.138347  [Calibration Summary] 1600 Mbps

 2042 23:06:51.138483  CH 0, Rank 0

 2043 23:06:51.141661  SW Impedance     : PASS

 2044 23:06:51.144951  DUTY Scan        : NO K

 2045 23:06:51.145065  ZQ Calibration   : PASS

 2046 23:06:51.148261  Jitter Meter     : NO K

 2047 23:06:51.151370  CBT Training     : PASS

 2048 23:06:51.151473  Write leveling   : PASS

 2049 23:06:51.154952  RX DQS gating    : PASS

 2050 23:06:51.155065  RX DQ/DQS(RDDQC) : PASS

 2051 23:06:51.158184  TX DQ/DQS        : PASS

 2052 23:06:51.162090  RX DATLAT        : PASS

 2053 23:06:51.162206  RX DQ/DQS(Engine): PASS

 2054 23:06:51.165410  TX OE            : NO K

 2055 23:06:51.165514  All Pass.

 2056 23:06:51.165585  

 2057 23:06:51.168697  CH 0, Rank 1

 2058 23:06:51.168791  SW Impedance     : PASS

 2059 23:06:51.171751  DUTY Scan        : NO K

 2060 23:06:51.175183  ZQ Calibration   : PASS

 2061 23:06:51.175286  Jitter Meter     : NO K

 2062 23:06:51.178107  CBT Training     : PASS

 2063 23:06:51.181819  Write leveling   : PASS

 2064 23:06:51.181932  RX DQS gating    : PASS

 2065 23:06:51.185633  RX DQ/DQS(RDDQC) : PASS

 2066 23:06:51.188765  TX DQ/DQS        : PASS

 2067 23:06:51.188880  RX DATLAT        : PASS

 2068 23:06:51.191924  RX DQ/DQS(Engine): PASS

 2069 23:06:51.192022  TX OE            : NO K

 2070 23:06:51.195308  All Pass.

 2071 23:06:51.195405  

 2072 23:06:51.195474  CH 1, Rank 0

 2073 23:06:51.198291  SW Impedance     : PASS

 2074 23:06:51.198382  DUTY Scan        : NO K

 2075 23:06:51.201711  ZQ Calibration   : PASS

 2076 23:06:51.205055  Jitter Meter     : NO K

 2077 23:06:51.205160  CBT Training     : PASS

 2078 23:06:51.208488  Write leveling   : PASS

 2079 23:06:51.211926  RX DQS gating    : PASS

 2080 23:06:51.212033  RX DQ/DQS(RDDQC) : PASS

 2081 23:06:51.215452  TX DQ/DQS        : PASS

 2082 23:06:51.218322  RX DATLAT        : PASS

 2083 23:06:51.218473  RX DQ/DQS(Engine): PASS

 2084 23:06:51.222071  TX OE            : NO K

 2085 23:06:51.222174  All Pass.

 2086 23:06:51.222240  

 2087 23:06:51.225212  CH 1, Rank 1

 2088 23:06:51.225340  SW Impedance     : PASS

 2089 23:06:51.228380  DUTY Scan        : NO K

 2090 23:06:51.228475  ZQ Calibration   : PASS

 2091 23:06:51.231767  Jitter Meter     : NO K

 2092 23:06:51.235612  CBT Training     : PASS

 2093 23:06:51.235724  Write leveling   : PASS

 2094 23:06:51.238803  RX DQS gating    : PASS

 2095 23:06:51.241770  RX DQ/DQS(RDDQC) : PASS

 2096 23:06:51.241869  TX DQ/DQS        : PASS

 2097 23:06:51.245440  RX DATLAT        : PASS

 2098 23:06:51.248770  RX DQ/DQS(Engine): PASS

 2099 23:06:51.248873  TX OE            : NO K

 2100 23:06:51.251924  All Pass.

 2101 23:06:51.252019  

 2102 23:06:51.252085  DramC Write-DBI off

 2103 23:06:51.255643  	PER_BANK_REFRESH: Hybrid Mode

 2104 23:06:51.255753  TX_TRACKING: ON

 2105 23:06:51.258707  [GetDramInforAfterCalByMRR] Vendor 6.

 2106 23:06:51.262461  [GetDramInforAfterCalByMRR] Revision 606.

 2107 23:06:51.269877  [GetDramInforAfterCalByMRR] Revision 2 0.

 2108 23:06:51.270022  MR0 0x3b3b

 2109 23:06:51.270091  MR8 0x5151

 2110 23:06:51.272511  RK0, DieNum 2, Density 16Gb, RKsize 32Gb.

 2111 23:06:51.272602  

 2112 23:06:51.275798  MR0 0x3b3b

 2113 23:06:51.275896  MR8 0x5151

 2114 23:06:51.278917  RK1, DieNum 2, Density 16Gb, RKsize 32Gb.

 2115 23:06:51.279035  

 2116 23:06:51.289272  [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0

 2117 23:06:51.292478  [FAST_K] Save calibration result to emmc

 2118 23:06:51.295814  [FAST_K] Save calibration result to emmc

 2119 23:06:51.299461  dram_init: config_dvfs: 1

 2120 23:06:51.302759  dramc_set_vcore_voltage set vcore to 662500

 2121 23:06:51.302869  Read voltage for 1200, 2

 2122 23:06:51.306043  Vio18 = 0

 2123 23:06:51.306140  Vcore = 662500

 2124 23:06:51.306205  Vdram = 0

 2125 23:06:51.309753  Vddq = 0

 2126 23:06:51.309855  Vmddr = 0

 2127 23:06:51.312949  [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0

 2128 23:06:51.319434  [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0

 2129 23:06:51.323415  MEM_TYPE=3, freq_sel=15

 2130 23:06:51.326875  sv_algorithm_assistance_LP4_1600 

 2131 23:06:51.329681  ============ PULL DRAM RESETB DOWN ============

 2132 23:06:51.332843  ========== PULL DRAM RESETB DOWN end =========

 2133 23:06:51.336597  [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4

 2134 23:06:51.340442  =================================== 

 2135 23:06:51.342867  LPDDR4 DRAM CONFIGURATION

 2136 23:06:51.346765  =================================== 

 2137 23:06:51.350283  EX_ROW_EN[0]    = 0x0

 2138 23:06:51.350422  EX_ROW_EN[1]    = 0x0

 2139 23:06:51.353378  LP4Y_EN      = 0x0

 2140 23:06:51.353472  WORK_FSP     = 0x0

 2141 23:06:51.356661  WL           = 0x4

 2142 23:06:51.356792  RL           = 0x4

 2143 23:06:51.359720  BL           = 0x2

 2144 23:06:51.359819  RPST         = 0x0

 2145 23:06:51.363191  RD_PRE       = 0x0

 2146 23:06:51.363293  WR_PRE       = 0x1

 2147 23:06:51.367203  WR_PST       = 0x0

 2148 23:06:51.367301  DBI_WR       = 0x0

 2149 23:06:51.369949  DBI_RD       = 0x0

 2150 23:06:51.370068  OTF          = 0x1

 2151 23:06:51.373552  =================================== 

 2152 23:06:51.376812  =================================== 

 2153 23:06:51.380426  ANA top config

 2154 23:06:51.383193  =================================== 

 2155 23:06:51.383356  DLL_ASYNC_EN            =  0

 2156 23:06:51.387004  ALL_SLAVE_EN            =  0

 2157 23:06:51.389876  NEW_RANK_MODE           =  1

 2158 23:06:51.393558  DLL_IDLE_MODE           =  1

 2159 23:06:51.397174  LP45_APHY_COMB_EN       =  1

 2160 23:06:51.397293  TX_ODT_DIS              =  1

 2161 23:06:51.400987  NEW_8X_MODE             =  1

 2162 23:06:51.404033  =================================== 

 2163 23:06:51.407625  =================================== 

 2164 23:06:51.410917  data_rate                  = 2400

 2165 23:06:51.413580  CKR                        = 1

 2166 23:06:51.417219  DQ_P2S_RATIO               = 8

 2167 23:06:51.421536  =================================== 

 2168 23:06:51.421662  CA_P2S_RATIO               = 8

 2169 23:06:51.424038  DQ_CA_OPEN                 = 0

 2170 23:06:51.426954  DQ_SEMI_OPEN               = 0

 2171 23:06:51.430473  CA_SEMI_OPEN               = 0

 2172 23:06:51.433816  CA_FULL_RATE               = 0

 2173 23:06:51.433931  DQ_CKDIV4_EN               = 0

 2174 23:06:51.437325  CA_CKDIV4_EN               = 0

 2175 23:06:51.440883  CA_PREDIV_EN               = 0

 2176 23:06:51.443835  PH8_DLY                    = 17

 2177 23:06:51.446916  SEMI_OPEN_CA_PICK_MCK_RATIO= 0

 2178 23:06:51.450385  DQ_AAMCK_DIV               = 4

 2179 23:06:51.450535  CA_AAMCK_DIV               = 4

 2180 23:06:51.454290  CA_ADMCK_DIV               = 4

 2181 23:06:51.457246  DQ_TRACK_CA_EN             = 0

 2182 23:06:51.460826  CA_PICK                    = 1200

 2183 23:06:51.464075  CA_MCKIO                   = 1200

 2184 23:06:51.467485  MCKIO_SEMI                 = 0

 2185 23:06:51.470701  PLL_FREQ                   = 2366

 2186 23:06:51.470813  DQ_UI_PI_RATIO             = 32

 2187 23:06:51.474208  CA_UI_PI_RATIO             = 0

 2188 23:06:51.478425  =================================== 

 2189 23:06:51.481111  =================================== 

 2190 23:06:51.484349  memory_type:LPDDR4         

 2191 23:06:51.487747  GP_NUM     : 10       

 2192 23:06:51.487866  SRAM_EN    : 1       

 2193 23:06:51.491005  MD32_EN    : 0       

 2194 23:06:51.494387  =================================== 

 2195 23:06:51.494537  [ANA_INIT] >>>>>>>>>>>>>> 

 2196 23:06:51.497473  <<<<<< [CONFIGURE PHASE]: ANA_TX

 2197 23:06:51.500996  >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL

 2198 23:06:51.504316  =================================== 

 2199 23:06:51.507947  data_rate = 2400,PCW = 0X5b00

 2200 23:06:51.511201  =================================== 

 2201 23:06:51.514343  <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL

 2202 23:06:51.521374  >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 2203 23:06:51.524913  <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 2204 23:06:51.531388  >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2

 2205 23:06:51.534429  >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL

 2206 23:06:51.537678  <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL

 2207 23:06:51.537801  [ANA_INIT] flow start 

 2208 23:06:51.541174  [ANA_INIT] PLL >>>>>>>> 

 2209 23:06:51.544672  [ANA_INIT] PLL <<<<<<<< 

 2210 23:06:51.544790  [ANA_INIT] MIDPI >>>>>>>> 

 2211 23:06:51.547687  [ANA_INIT] MIDPI <<<<<<<< 

 2212 23:06:51.551354  [ANA_INIT] DLL >>>>>>>> 

 2213 23:06:51.554772  [ANA_INIT] DLL <<<<<<<< 

 2214 23:06:51.554886  [ANA_INIT] flow end 

 2215 23:06:51.557764  ============ LP4 DIFF to SE enter ============

 2216 23:06:51.564917  ============ LP4 DIFF to SE exit  ============

 2217 23:06:51.565069  [ANA_INIT] <<<<<<<<<<<<< 

 2218 23:06:51.568053  [Flow] Enable top DCM control >>>>> 

 2219 23:06:51.571842  [Flow] Enable top DCM control <<<<< 

 2220 23:06:51.575321  Enable DLL master slave shuffle 

 2221 23:06:51.581345  ============================================================== 

 2222 23:06:51.581487  Gating Mode config

 2223 23:06:51.588778  ============================================================== 

 2224 23:06:51.591434  Config description: 

 2225 23:06:51.598433  RX_GATING_MODE        0: Pulse Mode      1: Burst Mode(8UI)        2: Burst Mode(7UI)  3: Original Burst Mode

 2226 23:06:51.605105  RX_GATING_TRACK_MODE  0: Valid DLY Mode  1: Valid Mode (-like) 2: FIFO mode

 2227 23:06:51.611823  SELPH_MODE            0: By rank         1: By Phase 

 2228 23:06:51.615508  ============================================================== 

 2229 23:06:51.618273  GAT_TRACK_EN                 =  1

 2230 23:06:51.622586  RX_GATING_MODE               =  2

 2231 23:06:51.625226  RX_GATING_TRACK_MODE         =  2

 2232 23:06:51.628540  SELPH_MODE                   =  1

 2233 23:06:51.631842  PICG_EARLY_EN                =  1

 2234 23:06:51.635947  VALID_LAT_VALUE              =  1

 2235 23:06:51.638447  ============================================================== 

 2236 23:06:51.641773  Enter into Gating configuration >>>> 

 2237 23:06:51.645501  Exit from Gating configuration <<<< 

 2238 23:06:51.649262  Enter into  DVFS_PRE_config >>>>> 

 2239 23:06:51.662250  Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. 

 2240 23:06:51.665805  Exit from  DVFS_PRE_config <<<<< 

 2241 23:06:51.665933  Enter into PICG configuration >>>> 

 2242 23:06:51.668864  Exit from PICG configuration <<<< 

 2243 23:06:51.672006  [RX_INPUT] configuration >>>>> 

 2244 23:06:51.675388  [RX_INPUT] configuration <<<<< 

 2245 23:06:51.682301  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>

 2246 23:06:51.685362  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<

 2247 23:06:51.692307  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>

 2248 23:06:51.699022  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<

 2249 23:06:51.705570  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>

 2250 23:06:51.712013  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<

 2251 23:06:51.715976  [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 

 2252 23:06:51.718760  [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 

 2253 23:06:51.722293  [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 

 2254 23:06:51.729244  [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 

 2255 23:06:51.732428  [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 

 2256 23:06:51.735548  [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4

 2257 23:06:51.739066  =================================== 

 2258 23:06:51.742870  LPDDR4 DRAM CONFIGURATION

 2259 23:06:51.745530  =================================== 

 2260 23:06:51.745636  EX_ROW_EN[0]    = 0x0

 2261 23:06:51.749469  EX_ROW_EN[1]    = 0x0

 2262 23:06:51.749572  LP4Y_EN      = 0x0

 2263 23:06:51.752855  WORK_FSP     = 0x0

 2264 23:06:51.752954  WL           = 0x4

 2265 23:06:51.755900  RL           = 0x4

 2266 23:06:51.755997  BL           = 0x2

 2267 23:06:51.759708  RPST         = 0x0

 2268 23:06:51.759821  RD_PRE       = 0x0

 2269 23:06:51.762694  WR_PRE       = 0x1

 2270 23:06:51.762795  WR_PST       = 0x0

 2271 23:06:51.765872  DBI_WR       = 0x0

 2272 23:06:51.769974  DBI_RD       = 0x0

 2273 23:06:51.770100  OTF          = 0x1

 2274 23:06:51.772624  =================================== 

 2275 23:06:51.776148  [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 

 2276 23:06:51.779909  [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 

 2277 23:06:51.786093  [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4

 2278 23:06:51.789905  =================================== 

 2279 23:06:51.790037  LPDDR4 DRAM CONFIGURATION

 2280 23:06:51.793637  =================================== 

 2281 23:06:51.796010  EX_ROW_EN[0]    = 0x10

 2282 23:06:51.799938  EX_ROW_EN[1]    = 0x0

 2283 23:06:51.800058  LP4Y_EN      = 0x0

 2284 23:06:51.802860  WORK_FSP     = 0x0

 2285 23:06:51.802956  WL           = 0x4

 2286 23:06:51.806077  RL           = 0x4

 2287 23:06:51.806189  BL           = 0x2

 2288 23:06:51.810020  RPST         = 0x0

 2289 23:06:51.810130  RD_PRE       = 0x0

 2290 23:06:51.813516  WR_PRE       = 0x1

 2291 23:06:51.813635  WR_PST       = 0x0

 2292 23:06:51.816577  DBI_WR       = 0x0

 2293 23:06:51.816707  DBI_RD       = 0x0

 2294 23:06:51.819331  OTF          = 0x1

 2295 23:06:51.823229  =================================== 

 2296 23:06:51.830407  [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit

 2297 23:06:51.830566  ==

 2298 23:06:51.833428  Dram Type= 6, Freq= 0, CH_0, rank 0

 2299 23:06:51.837706  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2300 23:06:51.837833  ==

 2301 23:06:51.840597  [Duty_Offset_Calibration]

 2302 23:06:51.840691  	B0:2	B1:-1	CA:1

 2303 23:06:51.840757  

 2304 23:06:51.842983  [DutyScan_Calibration_Flow] k_type=0

 2305 23:06:51.852813  

 2306 23:06:51.852971  ==CLK 0==

 2307 23:06:51.855486  Final CLK duty delay cell = -4

 2308 23:06:51.859892  [-4] MAX Duty = 5031%(X100), DQS PI = 4

 2309 23:06:51.862737  [-4] MIN Duty = 4875%(X100), DQS PI = 32

 2310 23:06:51.865593  [-4] AVG Duty = 4953%(X100)

 2311 23:06:51.865697  

 2312 23:06:51.869205  CH0 CLK Duty spec in!! Max-Min= 156%

 2313 23:06:51.872706  [DutyScan_Calibration_Flow] ====Done====

 2314 23:06:51.872822  

 2315 23:06:51.875895  [DutyScan_Calibration_Flow] k_type=1

 2316 23:06:51.890555  

 2317 23:06:51.890713  ==DQS 0 ==

 2318 23:06:51.894337  Final DQS duty delay cell = -4

 2319 23:06:51.896992  [-4] MAX Duty = 5000%(X100), DQS PI = 44

 2320 23:06:51.900197  [-4] MIN Duty = 4876%(X100), DQS PI = 10

 2321 23:06:51.903751  [-4] AVG Duty = 4938%(X100)

 2322 23:06:51.903865  

 2323 23:06:51.903939  ==DQS 1 ==

 2324 23:06:51.906911  Final DQS duty delay cell = -4

 2325 23:06:51.910630  [-4] MAX Duty = 5124%(X100), DQS PI = 16

 2326 23:06:51.913786  [-4] MIN Duty = 5000%(X100), DQS PI = 44

 2327 23:06:51.917288  [-4] AVG Duty = 5062%(X100)

 2328 23:06:51.917401  

 2329 23:06:51.921331  CH0 DQS 0 Duty spec in!! Max-Min= 124%

 2330 23:06:51.921438  

 2331 23:06:51.923727  CH0 DQS 1 Duty spec in!! Max-Min= 124%

 2332 23:06:51.927629  [DutyScan_Calibration_Flow] ====Done====

 2333 23:06:51.927746  

 2334 23:06:51.930328  [DutyScan_Calibration_Flow] k_type=3

 2335 23:06:51.948273  

 2336 23:06:51.948478  ==DQM 0 ==

 2337 23:06:51.951767  Final DQM duty delay cell = 0

 2338 23:06:51.954854  [0] MAX Duty = 5031%(X100), DQS PI = 54

 2339 23:06:51.957612  [0] MIN Duty = 4907%(X100), DQS PI = 2

 2340 23:06:51.957754  [0] AVG Duty = 4969%(X100)

 2341 23:06:51.961196  

 2342 23:06:51.961328  ==DQM 1 ==

 2343 23:06:51.964574  Final DQM duty delay cell = 0

 2344 23:06:51.968334  [0] MAX Duty = 5156%(X100), DQS PI = 62

 2345 23:06:51.971479  [0] MIN Duty = 4969%(X100), DQS PI = 8

 2346 23:06:51.971613  [0] AVG Duty = 5062%(X100)

 2347 23:06:51.971708  

 2348 23:06:51.974626  CH0 DQM 0 Duty spec in!! Max-Min= 124%

 2349 23:06:51.977634  

 2350 23:06:51.981284  CH0 DQM 1 Duty spec in!! Max-Min= 187%

 2351 23:06:51.984731  [DutyScan_Calibration_Flow] ====Done====

 2352 23:06:51.984880  

 2353 23:06:51.988228  [DutyScan_Calibration_Flow] k_type=2

 2354 23:06:52.003880  

 2355 23:06:52.004080  ==DQ 0 ==

 2356 23:06:52.006572  Final DQ duty delay cell = -4

 2357 23:06:52.010206  [-4] MAX Duty = 5093%(X100), DQS PI = 54

 2358 23:06:52.013415  [-4] MIN Duty = 4876%(X100), DQS PI = 18

 2359 23:06:52.016651  [-4] AVG Duty = 4984%(X100)

 2360 23:06:52.016812  

 2361 23:06:52.016908  ==DQ 1 ==

 2362 23:06:52.020120  Final DQ duty delay cell = 0

 2363 23:06:52.023158  [0] MAX Duty = 5031%(X100), DQS PI = 18

 2364 23:06:52.027165  [0] MIN Duty = 4907%(X100), DQS PI = 46

 2365 23:06:52.027309  [0] AVG Duty = 4969%(X100)

 2366 23:06:52.030793  

 2367 23:06:52.033520  CH0 DQ 0 Duty spec in!! Max-Min= 217%

 2368 23:06:52.033645  

 2369 23:06:52.037129  CH0 DQ 1 Duty spec in!! Max-Min= 124%

 2370 23:06:52.040470  [DutyScan_Calibration_Flow] ====Done====

 2371 23:06:52.040597  ==

 2372 23:06:52.043497  Dram Type= 6, Freq= 0, CH_1, rank 0

 2373 23:06:52.047655  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2374 23:06:52.047798  ==

 2375 23:06:52.050881  [Duty_Offset_Calibration]

 2376 23:06:52.051001  	B0:1	B1:1	CA:2

 2377 23:06:52.051095  

 2378 23:06:52.053505  [DutyScan_Calibration_Flow] k_type=0

 2379 23:06:52.063645  

 2380 23:06:52.063840  ==CLK 0==

 2381 23:06:52.067415  Final CLK duty delay cell = 0

 2382 23:06:52.070218  [0] MAX Duty = 5156%(X100), DQS PI = 24

 2383 23:06:52.073726  [0] MIN Duty = 4969%(X100), DQS PI = 40

 2384 23:06:52.073865  [0] AVG Duty = 5062%(X100)

 2385 23:06:52.077931  

 2386 23:06:52.078075  CH1 CLK Duty spec in!! Max-Min= 187%

 2387 23:06:52.083761  [DutyScan_Calibration_Flow] ====Done====

 2388 23:06:52.083915  

 2389 23:06:52.087024  [DutyScan_Calibration_Flow] k_type=1

 2390 23:06:52.103189  

 2391 23:06:52.103389  ==DQS 0 ==

 2392 23:06:52.106781  Final DQS duty delay cell = 0

 2393 23:06:52.109738  [0] MAX Duty = 5031%(X100), DQS PI = 18

 2394 23:06:52.113155  [0] MIN Duty = 4875%(X100), DQS PI = 30

 2395 23:06:52.113273  [0] AVG Duty = 4953%(X100)

 2396 23:06:52.116439  

 2397 23:06:52.116554  ==DQS 1 ==

 2398 23:06:52.119979  Final DQS duty delay cell = 0

 2399 23:06:52.123734  [0] MAX Duty = 5062%(X100), DQS PI = 36

 2400 23:06:52.126895  [0] MIN Duty = 4907%(X100), DQS PI = 8

 2401 23:06:52.127007  [0] AVG Duty = 4984%(X100)

 2402 23:06:52.127073  

 2403 23:06:52.129809  CH1 DQS 0 Duty spec in!! Max-Min= 156%

 2404 23:06:52.133084  

 2405 23:06:52.136664  CH1 DQS 1 Duty spec in!! Max-Min= 155%

 2406 23:06:52.140153  [DutyScan_Calibration_Flow] ====Done====

 2407 23:06:52.140267  

 2408 23:06:52.143028  [DutyScan_Calibration_Flow] k_type=3

 2409 23:06:52.159647  

 2410 23:06:52.159804  ==DQM 0 ==

 2411 23:06:52.163030  Final DQM duty delay cell = 0

 2412 23:06:52.166260  [0] MAX Duty = 5093%(X100), DQS PI = 18

 2413 23:06:52.169316  [0] MIN Duty = 4875%(X100), DQS PI = 48

 2414 23:06:52.169424  [0] AVG Duty = 4984%(X100)

 2415 23:06:52.173150  

 2416 23:06:52.173259  ==DQM 1 ==

 2417 23:06:52.176042  Final DQM duty delay cell = 0

 2418 23:06:52.179411  [0] MAX Duty = 5156%(X100), DQS PI = 62

 2419 23:06:52.183016  [0] MIN Duty = 4938%(X100), DQS PI = 22

 2420 23:06:52.183133  [0] AVG Duty = 5047%(X100)

 2421 23:06:52.186251  

 2422 23:06:52.189530  CH1 DQM 0 Duty spec in!! Max-Min= 218%

 2423 23:06:52.189646  

 2424 23:06:52.193472  CH1 DQM 1 Duty spec in!! Max-Min= 218%

 2425 23:06:52.196741  [DutyScan_Calibration_Flow] ====Done====

 2426 23:06:52.196849  

 2427 23:06:52.199885  [DutyScan_Calibration_Flow] k_type=2

 2428 23:06:52.215745  

 2429 23:06:52.215904  ==DQ 0 ==

 2430 23:06:52.220054  Final DQ duty delay cell = 0

 2431 23:06:52.222782  [0] MAX Duty = 5124%(X100), DQS PI = 18

 2432 23:06:52.226363  [0] MIN Duty = 4938%(X100), DQS PI = 50

 2433 23:06:52.226525  [0] AVG Duty = 5031%(X100)

 2434 23:06:52.226593  

 2435 23:06:52.229341  ==DQ 1 ==

 2436 23:06:52.229432  Final DQ duty delay cell = 0

 2437 23:06:52.236267  [0] MAX Duty = 5093%(X100), DQS PI = 10

 2438 23:06:52.239295  [0] MIN Duty = 5031%(X100), DQS PI = 2

 2439 23:06:52.239406  [0] AVG Duty = 5062%(X100)

 2440 23:06:52.239472  

 2441 23:06:52.242698  CH1 DQ 0 Duty spec in!! Max-Min= 186%

 2442 23:06:52.242848  

 2443 23:06:52.246169  CH1 DQ 1 Duty spec in!! Max-Min= 62%

 2444 23:06:52.249364  [DutyScan_Calibration_Flow] ====Done====

 2445 23:06:52.254949  nWR fixed to 30

 2446 23:06:52.258213  [ModeRegInit_LP4] CH0 RK0

 2447 23:06:52.258360  [ModeRegInit_LP4] CH0 RK1

 2448 23:06:52.261705  [ModeRegInit_LP4] CH1 RK0

 2449 23:06:52.265622  [ModeRegInit_LP4] CH1 RK1

 2450 23:06:52.265741  match AC timing 7

 2451 23:06:52.271907  dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1

 2452 23:06:52.275248  SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON

 2453 23:06:52.278575  [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12

 2454 23:06:52.285275  [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25

 2455 23:06:52.288148  [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)

 2456 23:06:52.288261  ==

 2457 23:06:52.291971  Dram Type= 6, Freq= 0, CH_0, rank 0

 2458 23:06:52.295462  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2459 23:06:52.295587  ==

 2460 23:06:52.301723  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 2461 23:06:52.308373  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39

 2462 23:06:52.316431  [CA 0] Center 40 (10~71) winsize 62

 2463 23:06:52.319346  [CA 1] Center 39 (9~70) winsize 62

 2464 23:06:52.322780  [CA 2] Center 36 (6~67) winsize 62

 2465 23:06:52.326055  [CA 3] Center 35 (5~66) winsize 62

 2466 23:06:52.329727  [CA 4] Center 34 (4~65) winsize 62

 2467 23:06:52.332589  [CA 5] Center 34 (4~64) winsize 61

 2468 23:06:52.332702  

 2469 23:06:52.336305  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 2470 23:06:52.336416  

 2471 23:06:52.339426  [CATrainingPosCal] consider 1 rank data

 2472 23:06:52.343248  u2DelayCellTimex100 = 270/100 ps

 2473 23:06:52.346148  CA0 delay=40 (10~71),Diff = 6 PI (28 cell)

 2474 23:06:52.349402  CA1 delay=39 (9~70),Diff = 5 PI (24 cell)

 2475 23:06:52.356308  CA2 delay=36 (6~67),Diff = 2 PI (9 cell)

 2476 23:06:52.359867  CA3 delay=35 (5~66),Diff = 1 PI (4 cell)

 2477 23:06:52.363031  CA4 delay=34 (4~65),Diff = 0 PI (0 cell)

 2478 23:06:52.366464  CA5 delay=34 (4~64),Diff = 0 PI (0 cell)

 2479 23:06:52.366578  

 2480 23:06:52.369682  CA PerBit enable=1, Macro0, CA PI delay=34

 2481 23:06:52.369774  

 2482 23:06:52.373143  [CBTSetCACLKResult] CA Dly = 34

 2483 23:06:52.373253  CS Dly: 7 (0~38)

 2484 23:06:52.373321  ==

 2485 23:06:52.376677  Dram Type= 6, Freq= 0, CH_0, rank 1

 2486 23:06:52.383382  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2487 23:06:52.383518  ==

 2488 23:06:52.386652  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 2489 23:06:52.393133  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39

 2490 23:06:52.401668  [CA 0] Center 39 (9~70) winsize 62

 2491 23:06:52.404789  [CA 1] Center 40 (10~70) winsize 61

 2492 23:06:52.408312  [CA 2] Center 36 (6~67) winsize 62

 2493 23:06:52.412455  [CA 3] Center 36 (5~67) winsize 63

 2494 23:06:52.414828  [CA 4] Center 34 (4~65) winsize 62

 2495 23:06:52.418108  [CA 5] Center 34 (4~64) winsize 61

 2496 23:06:52.418248  

 2497 23:06:52.421601  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 2498 23:06:52.421734  

 2499 23:06:52.425290  [CATrainingPosCal] consider 2 rank data

 2500 23:06:52.428752  u2DelayCellTimex100 = 270/100 ps

 2501 23:06:52.432667  CA0 delay=40 (10~70),Diff = 6 PI (28 cell)

 2502 23:06:52.435341  CA1 delay=40 (10~70),Diff = 6 PI (28 cell)

 2503 23:06:52.442364  CA2 delay=36 (6~67),Diff = 2 PI (9 cell)

 2504 23:06:52.445445  CA3 delay=35 (5~66),Diff = 1 PI (4 cell)

 2505 23:06:52.448562  CA4 delay=34 (4~65),Diff = 0 PI (0 cell)

 2506 23:06:52.451999  CA5 delay=34 (4~64),Diff = 0 PI (0 cell)

 2507 23:06:52.452137  

 2508 23:06:52.455364  CA PerBit enable=1, Macro0, CA PI delay=34

 2509 23:06:52.455493  

 2510 23:06:52.458554  [CBTSetCACLKResult] CA Dly = 34

 2511 23:06:52.458690  CS Dly: 8 (0~41)

 2512 23:06:52.458789  

 2513 23:06:52.461951  ----->DramcWriteLeveling(PI) begin...

 2514 23:06:52.465490  ==

 2515 23:06:52.465624  Dram Type= 6, Freq= 0, CH_0, rank 0

 2516 23:06:52.471948  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2517 23:06:52.472114  ==

 2518 23:06:52.475277  Write leveling (Byte 0): 32 => 32

 2519 23:06:52.479412  Write leveling (Byte 1): 29 => 29

 2520 23:06:52.479559  DramcWriteLeveling(PI) end<-----

 2521 23:06:52.482722  

 2522 23:06:52.482851  ==

 2523 23:06:52.485520  Dram Type= 6, Freq= 0, CH_0, rank 0

 2524 23:06:52.488588  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2525 23:06:52.488724  ==

 2526 23:06:52.492700  [Gating] SW mode calibration

 2527 23:06:52.499138  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0

 2528 23:06:52.503563  RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)

 2529 23:06:52.509832   0 15  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2530 23:06:52.512202   0 15  4 | B1->B0 | 2323 3131 | 1 1 | (1 1) (1 1)

 2531 23:06:52.515832   0 15  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2532 23:06:52.523262   0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2533 23:06:52.526060   0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2534 23:06:52.529970   0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2535 23:06:52.532708   0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2536 23:06:52.539156   0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2537 23:06:52.542697   1  0  0 | B1->B0 | 3434 3131 | 1 0 | (1 0) (1 0)

 2538 23:06:52.546599   1  0  4 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)

 2539 23:06:52.553728   1  0  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2540 23:06:52.556277   1  0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2541 23:06:52.559636   1  0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2542 23:06:52.566628   1  0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2543 23:06:52.569708   1  0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2544 23:06:52.573871   1  0 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2545 23:06:52.579450   1  1  0 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)

 2546 23:06:52.583096   1  1  4 | B1->B0 | 4141 4545 | 0 0 | (0 0) (0 0)

 2547 23:06:52.586506   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2548 23:06:52.590099   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2549 23:06:52.597550   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2550 23:06:52.599981   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2551 23:06:52.603480   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2552 23:06:52.609825   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2553 23:06:52.613620   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 2554 23:06:52.617358   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 2555 23:06:52.623860   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2556 23:06:52.626730   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2557 23:06:52.630349   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2558 23:06:52.633508   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2559 23:06:52.640992   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2560 23:06:52.643626   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2561 23:06:52.646810   1  3  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2562 23:06:52.653690   1  3  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2563 23:06:52.657434   1  3  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2564 23:06:52.661149   1  3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2565 23:06:52.667721   1  3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2566 23:06:52.670340   1  3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2567 23:06:52.674369   1  3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2568 23:06:52.680488   1  3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2569 23:06:52.683886   1  4  0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 2570 23:06:52.687377   1  4  4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 2571 23:06:52.690852  Total UI for P1: 0, mck2ui 16

 2572 23:06:52.694415  best dqsien dly found for B0: ( 1,  4,  0)

 2573 23:06:52.697889   1  4  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2574 23:06:52.700968  Total UI for P1: 0, mck2ui 16

 2575 23:06:52.704429  best dqsien dly found for B1: ( 1,  4,  2)

 2576 23:06:52.707353  best DQS0 dly(MCK, UI, PI) = (1, 4, 0)

 2577 23:06:52.711705  best DQS1 dly(MCK, UI, PI) = (1, 4, 2)

 2578 23:06:52.711828  

 2579 23:06:52.717501  best DQS0 P1 dly(MCK, UI, PI) = (1, 8, 0)

 2580 23:06:52.720994  best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)

 2581 23:06:52.721112  [Gating] SW calibration Done

 2582 23:06:52.724776  ==

 2583 23:06:52.724881  Dram Type= 6, Freq= 0, CH_0, rank 0

 2584 23:06:52.731180  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2585 23:06:52.731316  ==

 2586 23:06:52.731387  RX Vref Scan: 0

 2587 23:06:52.731448  

 2588 23:06:52.734384  RX Vref 0 -> 0, step: 1

 2589 23:06:52.734503  

 2590 23:06:52.737590  RX Delay -40 -> 252, step: 8

 2591 23:06:52.741306  iDelay=200, Bit 0, Center 115 (40 ~ 191) 152

 2592 23:06:52.744623  iDelay=200, Bit 1, Center 115 (40 ~ 191) 152

 2593 23:06:52.747903  iDelay=200, Bit 2, Center 111 (40 ~ 183) 144

 2594 23:06:52.754880  iDelay=200, Bit 3, Center 111 (40 ~ 183) 144

 2595 23:06:52.757948  iDelay=200, Bit 4, Center 115 (40 ~ 191) 152

 2596 23:06:52.761893  iDelay=200, Bit 5, Center 107 (40 ~ 175) 136

 2597 23:06:52.764919  iDelay=200, Bit 6, Center 123 (48 ~ 199) 152

 2598 23:06:52.767836  iDelay=200, Bit 7, Center 123 (48 ~ 199) 152

 2599 23:06:52.771101  iDelay=200, Bit 8, Center 95 (24 ~ 167) 144

 2600 23:06:52.777803  iDelay=200, Bit 9, Center 95 (24 ~ 167) 144

 2601 23:06:52.781463  iDelay=200, Bit 10, Center 107 (40 ~ 175) 136

 2602 23:06:52.784533  iDelay=200, Bit 11, Center 99 (32 ~ 167) 136

 2603 23:06:52.788684  iDelay=200, Bit 12, Center 111 (40 ~ 183) 144

 2604 23:06:52.791877  iDelay=200, Bit 13, Center 115 (48 ~ 183) 136

 2605 23:06:52.798407  iDelay=200, Bit 14, Center 119 (48 ~ 191) 144

 2606 23:06:52.801326  iDelay=200, Bit 15, Center 115 (48 ~ 183) 136

 2607 23:06:52.801441  ==

 2608 23:06:52.805012  Dram Type= 6, Freq= 0, CH_0, rank 0

 2609 23:06:52.807933  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2610 23:06:52.808037  ==

 2611 23:06:52.808103  DQS Delay:

 2612 23:06:52.811797  DQS0 = 0, DQS1 = 0

 2613 23:06:52.811903  DQM Delay:

 2614 23:06:52.814792  DQM0 = 115, DQM1 = 107

 2615 23:06:52.814888  DQ Delay:

 2616 23:06:52.819215  DQ0 =115, DQ1 =115, DQ2 =111, DQ3 =111

 2617 23:06:52.821798  DQ4 =115, DQ5 =107, DQ6 =123, DQ7 =123

 2618 23:06:52.825775  DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =99

 2619 23:06:52.828756  DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =115

 2620 23:06:52.828864  

 2621 23:06:52.831456  

 2622 23:06:52.831550  ==

 2623 23:06:52.835494  Dram Type= 6, Freq= 0, CH_0, rank 0

 2624 23:06:52.838412  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2625 23:06:52.838530  ==

 2626 23:06:52.838596  

 2627 23:06:52.838656  

 2628 23:06:52.841644  	TX Vref Scan disable

 2629 23:06:52.841737   == TX Byte 0 ==

 2630 23:06:52.845513  Update DQ  dly =851 (3 ,2, 19)  DQ  OEN =(2 ,7)

 2631 23:06:52.852299  Update DQM dly =851 (3 ,2, 19)  DQM OEN =(2 ,7)

 2632 23:06:52.852443   == TX Byte 1 ==

 2633 23:06:52.855753  Update DQ  dly =846 (3 ,2, 14)  DQ  OEN =(2 ,7)

 2634 23:06:52.861909  Update DQM dly =846 (3 ,2, 14)  DQM OEN =(2 ,7)

 2635 23:06:52.862059  ==

 2636 23:06:52.865059  Dram Type= 6, Freq= 0, CH_0, rank 0

 2637 23:06:52.869205  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2638 23:06:52.869330  ==

 2639 23:06:52.880451  TX Vref=22, minBit 7, minWin=24, winSum=414

 2640 23:06:52.883850  TX Vref=24, minBit 1, minWin=24, winSum=418

 2641 23:06:52.887944  TX Vref=26, minBit 7, minWin=25, winSum=428

 2642 23:06:52.890842  TX Vref=28, minBit 0, minWin=26, winSum=430

 2643 23:06:52.894591  TX Vref=30, minBit 0, minWin=26, winSum=432

 2644 23:06:52.897220  TX Vref=32, minBit 0, minWin=26, winSum=430

 2645 23:06:52.904450  [TxChooseVref] Worse bit 0, Min win 26, Win sum 432, Final Vref 30

 2646 23:06:52.904598  

 2647 23:06:52.907358  Final TX Range 1 Vref 30

 2648 23:06:52.907458  

 2649 23:06:52.907545  ==

 2650 23:06:52.910841  Dram Type= 6, Freq= 0, CH_0, rank 0

 2651 23:06:52.914198  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2652 23:06:52.914304  ==

 2653 23:06:52.914437  

 2654 23:06:52.914533  

 2655 23:06:52.917639  	TX Vref Scan disable

 2656 23:06:52.921002   == TX Byte 0 ==

 2657 23:06:52.924175  Update DQ  dly =851 (3 ,2, 19)  DQ  OEN =(2 ,7)

 2658 23:06:52.927901  Update DQM dly =851 (3 ,2, 19)  DQM OEN =(2 ,7)

 2659 23:06:52.930861   == TX Byte 1 ==

 2660 23:06:52.934766  Update DQ  dly =846 (3 ,2, 14)  DQ  OEN =(2 ,7)

 2661 23:06:52.937769  Update DQM dly =846 (3 ,2, 14)  DQM OEN =(2 ,7)

 2662 23:06:52.937880  

 2663 23:06:52.941732  [DATLAT]

 2664 23:06:52.941837  Freq=1200, CH0 RK0

 2665 23:06:52.941927  

 2666 23:06:52.944588  DATLAT Default: 0xd

 2667 23:06:52.944679  0, 0xFFFF, sum = 0

 2668 23:06:52.947967  1, 0xFFFF, sum = 0

 2669 23:06:52.948070  2, 0xFFFF, sum = 0

 2670 23:06:52.952458  3, 0xFFFF, sum = 0

 2671 23:06:52.952572  4, 0xFFFF, sum = 0

 2672 23:06:52.954364  5, 0xFFFF, sum = 0

 2673 23:06:52.954492  6, 0xFFFF, sum = 0

 2674 23:06:52.958079  7, 0xFFFF, sum = 0

 2675 23:06:52.958183  8, 0xFFFF, sum = 0

 2676 23:06:52.961146  9, 0xFFFF, sum = 0

 2677 23:06:52.961252  10, 0xFFFF, sum = 0

 2678 23:06:52.965151  11, 0xFFFF, sum = 0

 2679 23:06:52.965260  12, 0x0, sum = 1

 2680 23:06:52.967931  13, 0x0, sum = 2

 2681 23:06:52.968027  14, 0x0, sum = 3

 2682 23:06:52.971380  15, 0x0, sum = 4

 2683 23:06:52.971486  best_step = 13

 2684 23:06:52.971575  

 2685 23:06:52.971655  ==

 2686 23:06:52.974724  Dram Type= 6, Freq= 0, CH_0, rank 0

 2687 23:06:52.978241  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2688 23:06:52.981779  ==

 2689 23:06:52.981893  RX Vref Scan: 1

 2690 23:06:52.981986  

 2691 23:06:52.984700  Set Vref Range= 32 -> 127

 2692 23:06:52.984791  

 2693 23:06:52.988373  RX Vref 32 -> 127, step: 1

 2694 23:06:52.988508  

 2695 23:06:52.988605  RX Delay -21 -> 252, step: 4

 2696 23:06:52.988696  

 2697 23:06:52.991468  Set Vref, RX VrefLevel [Byte0]: 32

 2698 23:06:52.995072                           [Byte1]: 32

 2699 23:06:52.998607  

 2700 23:06:52.998748  Set Vref, RX VrefLevel [Byte0]: 33

 2701 23:06:53.002294                           [Byte1]: 33

 2702 23:06:53.007008  

 2703 23:06:53.007142  Set Vref, RX VrefLevel [Byte0]: 34

 2704 23:06:53.010259                           [Byte1]: 34

 2705 23:06:53.015209  

 2706 23:06:53.015339  Set Vref, RX VrefLevel [Byte0]: 35

 2707 23:06:53.018052                           [Byte1]: 35

 2708 23:06:53.022590  

 2709 23:06:53.022711  Set Vref, RX VrefLevel [Byte0]: 36

 2710 23:06:53.026171                           [Byte1]: 36

 2711 23:06:53.030584  

 2712 23:06:53.030710  Set Vref, RX VrefLevel [Byte0]: 37

 2713 23:06:53.033806                           [Byte1]: 37

 2714 23:06:53.038215  

 2715 23:06:53.038381  Set Vref, RX VrefLevel [Byte0]: 38

 2716 23:06:53.042273                           [Byte1]: 38

 2717 23:06:53.046077  

 2718 23:06:53.046222  Set Vref, RX VrefLevel [Byte0]: 39

 2719 23:06:53.050025                           [Byte1]: 39

 2720 23:06:53.054011  

 2721 23:06:53.054157  Set Vref, RX VrefLevel [Byte0]: 40

 2722 23:06:53.057648                           [Byte1]: 40

 2723 23:06:53.062533  

 2724 23:06:53.062704  Set Vref, RX VrefLevel [Byte0]: 41

 2725 23:06:53.065266                           [Byte1]: 41

 2726 23:06:53.070271  

 2727 23:06:53.070498  Set Vref, RX VrefLevel [Byte0]: 42

 2728 23:06:53.074231                           [Byte1]: 42

 2729 23:06:53.078014  

 2730 23:06:53.078127  Set Vref, RX VrefLevel [Byte0]: 43

 2731 23:06:53.081538                           [Byte1]: 43

 2732 23:06:53.086371  

 2733 23:06:53.086582  Set Vref, RX VrefLevel [Byte0]: 44

 2734 23:06:53.092466                           [Byte1]: 44

 2735 23:06:53.092614  

 2736 23:06:53.095573  Set Vref, RX VrefLevel [Byte0]: 45

 2737 23:06:53.099036                           [Byte1]: 45

 2738 23:06:53.099146  

 2739 23:06:53.102665  Set Vref, RX VrefLevel [Byte0]: 46

 2740 23:06:53.105870                           [Byte1]: 46

 2741 23:06:53.109747  

 2742 23:06:53.109868  Set Vref, RX VrefLevel [Byte0]: 47

 2743 23:06:53.112868                           [Byte1]: 47

 2744 23:06:53.117655  

 2745 23:06:53.117782  Set Vref, RX VrefLevel [Byte0]: 48

 2746 23:06:53.120769                           [Byte1]: 48

 2747 23:06:53.125591  

 2748 23:06:53.125748  Set Vref, RX VrefLevel [Byte0]: 49

 2749 23:06:53.129341                           [Byte1]: 49

 2750 23:06:53.133297  

 2751 23:06:53.133438  Set Vref, RX VrefLevel [Byte0]: 50

 2752 23:06:53.136849                           [Byte1]: 50

 2753 23:06:53.141582  

 2754 23:06:53.141707  Set Vref, RX VrefLevel [Byte0]: 51

 2755 23:06:53.144525                           [Byte1]: 51

 2756 23:06:53.149588  

 2757 23:06:53.149714  Set Vref, RX VrefLevel [Byte0]: 52

 2758 23:06:53.152700                           [Byte1]: 52

 2759 23:06:53.157552  

 2760 23:06:53.157677  Set Vref, RX VrefLevel [Byte0]: 53

 2761 23:06:53.160429                           [Byte1]: 53

 2762 23:06:53.164998  

 2763 23:06:53.165122  Set Vref, RX VrefLevel [Byte0]: 54

 2764 23:06:53.168679                           [Byte1]: 54

 2765 23:06:53.173816  

 2766 23:06:53.173942  Set Vref, RX VrefLevel [Byte0]: 55

 2767 23:06:53.176496                           [Byte1]: 55

 2768 23:06:53.181306  

 2769 23:06:53.181432  Set Vref, RX VrefLevel [Byte0]: 56

 2770 23:06:53.184389                           [Byte1]: 56

 2771 23:06:53.189894  

 2772 23:06:53.190027  Set Vref, RX VrefLevel [Byte0]: 57

 2773 23:06:53.192244                           [Byte1]: 57

 2774 23:06:53.197371  

 2775 23:06:53.197497  Set Vref, RX VrefLevel [Byte0]: 58

 2776 23:06:53.200507                           [Byte1]: 58

 2777 23:06:53.204594  

 2778 23:06:53.204728  Set Vref, RX VrefLevel [Byte0]: 59

 2779 23:06:53.208612                           [Byte1]: 59

 2780 23:06:53.212595  

 2781 23:06:53.212739  Set Vref, RX VrefLevel [Byte0]: 60

 2782 23:06:53.216317                           [Byte1]: 60

 2783 23:06:53.220437  

 2784 23:06:53.220555  Set Vref, RX VrefLevel [Byte0]: 61

 2785 23:06:53.224083                           [Byte1]: 61

 2786 23:06:53.228811  

 2787 23:06:53.228934  Set Vref, RX VrefLevel [Byte0]: 62

 2788 23:06:53.231828                           [Byte1]: 62

 2789 23:06:53.236352  

 2790 23:06:53.236473  Set Vref, RX VrefLevel [Byte0]: 63

 2791 23:06:53.239824                           [Byte1]: 63

 2792 23:06:53.244477  

 2793 23:06:53.244603  Set Vref, RX VrefLevel [Byte0]: 64

 2794 23:06:53.248504                           [Byte1]: 64

 2795 23:06:53.252690  

 2796 23:06:53.252822  Set Vref, RX VrefLevel [Byte0]: 65

 2797 23:06:53.255719                           [Byte1]: 65

 2798 23:06:53.260302  

 2799 23:06:53.260436  Set Vref, RX VrefLevel [Byte0]: 66

 2800 23:06:53.263836                           [Byte1]: 66

 2801 23:06:53.268653  

 2802 23:06:53.268784  Set Vref, RX VrefLevel [Byte0]: 67

 2803 23:06:53.272026                           [Byte1]: 67

 2804 23:06:53.276050  

 2805 23:06:53.276169  Set Vref, RX VrefLevel [Byte0]: 68

 2806 23:06:53.279565                           [Byte1]: 68

 2807 23:06:53.284125  

 2808 23:06:53.284252  Set Vref, RX VrefLevel [Byte0]: 69

 2809 23:06:53.287254                           [Byte1]: 69

 2810 23:06:53.292343  

 2811 23:06:53.292479  Set Vref, RX VrefLevel [Byte0]: 70

 2812 23:06:53.295567                           [Byte1]: 70

 2813 23:06:53.299946  

 2814 23:06:53.300070  Final RX Vref Byte 0 = 53 to rank0

 2815 23:06:53.303070  Final RX Vref Byte 1 = 52 to rank0

 2816 23:06:53.307168  Final RX Vref Byte 0 = 53 to rank1

 2817 23:06:53.310239  Final RX Vref Byte 1 = 52 to rank1==

 2818 23:06:53.313647  Dram Type= 6, Freq= 0, CH_0, rank 0

 2819 23:06:53.317468  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2820 23:06:53.320574  ==

 2821 23:06:53.320691  DQS Delay:

 2822 23:06:53.320759  DQS0 = 0, DQS1 = 0

 2823 23:06:53.323519  DQM Delay:

 2824 23:06:53.323610  DQM0 = 115, DQM1 = 105

 2825 23:06:53.327025  DQ Delay:

 2826 23:06:53.330050  DQ0 =116, DQ1 =114, DQ2 =112, DQ3 =114

 2827 23:06:53.333930  DQ4 =116, DQ5 =108, DQ6 =122, DQ7 =120

 2828 23:06:53.337238  DQ8 =92, DQ9 =90, DQ10 =106, DQ11 =96

 2829 23:06:53.340688  DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =114

 2830 23:06:53.340809  

 2831 23:06:53.340878  

 2832 23:06:53.347148  [DQSOSCAuto] RK0, (LSB)MR18= 0x1f1, (MSB)MR19= 0x403, tDQSOscB0 = 416 ps tDQSOscB1 = 409 ps

 2833 23:06:53.350127  CH0 RK0: MR19=403, MR18=1F1

 2834 23:06:53.356813  CH0_RK0: MR19=0x403, MR18=0x1F1, DQSOSC=409, MR23=63, INC=39, DEC=26

 2835 23:06:53.356956  

 2836 23:06:53.360357  ----->DramcWriteLeveling(PI) begin...

 2837 23:06:53.360471  ==

 2838 23:06:53.363923  Dram Type= 6, Freq= 0, CH_0, rank 1

 2839 23:06:53.367059  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2840 23:06:53.367168  ==

 2841 23:06:53.370269  Write leveling (Byte 0): 33 => 33

 2842 23:06:53.373646  Write leveling (Byte 1): 28 => 28

 2843 23:06:53.377111  DramcWriteLeveling(PI) end<-----

 2844 23:06:53.377224  

 2845 23:06:53.377292  ==

 2846 23:06:53.380346  Dram Type= 6, Freq= 0, CH_0, rank 1

 2847 23:06:53.384683  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2848 23:06:53.384800  ==

 2849 23:06:53.387059  [Gating] SW mode calibration

 2850 23:06:53.393761  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0

 2851 23:06:53.400997  RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)

 2852 23:06:53.404181   0 15  0 | B1->B0 | 2323 2a2a | 0 1 | (0 0) (0 0)

 2853 23:06:53.407117   0 15  4 | B1->B0 | 2b2b 3434 | 1 1 | (0 0) (1 1)

 2854 23:06:53.414571   0 15  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2855 23:06:53.417381   0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2856 23:06:53.420909   0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2857 23:06:53.427427   0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2858 23:06:53.430589   0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)

 2859 23:06:53.434545   0 15 28 | B1->B0 | 3434 2626 | 1 1 | (1 1) (1 0)

 2860 23:06:53.441206   1  0  0 | B1->B0 | 2b2b 2323 | 0 0 | (0 1) (0 0)

 2861 23:06:53.444003   1  0  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2862 23:06:53.447699   1  0  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2863 23:06:53.454386   1  0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2864 23:06:53.457374   1  0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2865 23:06:53.461461   1  0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2866 23:06:53.464098   1  0 24 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)

 2867 23:06:53.471052   1  0 28 | B1->B0 | 2323 4545 | 0 1 | (0 0) (0 0)

 2868 23:06:53.474358   1  1  0 | B1->B0 | 3939 4646 | 1 0 | (0 0) (0 0)

 2869 23:06:53.477698   1  1  4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)

 2870 23:06:53.484766   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2871 23:06:53.487668   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2872 23:06:53.491182   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2873 23:06:53.498354   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2874 23:06:53.501655   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 2875 23:06:53.504569   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 2876 23:06:53.511828   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 2877 23:06:53.514570   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 2878 23:06:53.518063   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2879 23:06:53.521204   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2880 23:06:53.528828   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2881 23:06:53.531924   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2882 23:06:53.535439   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2883 23:06:53.541730   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2884 23:06:53.545065   1  3  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2885 23:06:53.548676   1  3  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2886 23:06:53.554830   1  3  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2887 23:06:53.558647   1  3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2888 23:06:53.562329   1  3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2889 23:06:53.568396   1  3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2890 23:06:53.571971   1  3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 2891 23:06:53.575615   1  3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 2892 23:06:53.581843   1  4  0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 2893 23:06:53.582033  Total UI for P1: 0, mck2ui 16

 2894 23:06:53.585146  best dqsien dly found for B0: ( 1,  3, 26)

 2895 23:06:53.592062   1  4  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2896 23:06:53.595728  Total UI for P1: 0, mck2ui 16

 2897 23:06:53.598746  best dqsien dly found for B1: ( 1,  4,  0)

 2898 23:06:53.602261  best DQS0 dly(MCK, UI, PI) = (1, 3, 26)

 2899 23:06:53.605799  best DQS1 dly(MCK, UI, PI) = (1, 4, 0)

 2900 23:06:53.605977  

 2901 23:06:53.609396  best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)

 2902 23:06:53.612013  best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)

 2903 23:06:53.615712  [Gating] SW calibration Done

 2904 23:06:53.615867  ==

 2905 23:06:53.618268  Dram Type= 6, Freq= 0, CH_0, rank 1

 2906 23:06:53.622150  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2907 23:06:53.622330  ==

 2908 23:06:53.625372  RX Vref Scan: 0

 2909 23:06:53.625498  

 2910 23:06:53.625640  RX Vref 0 -> 0, step: 1

 2911 23:06:53.625773  

 2912 23:06:53.628526  RX Delay -40 -> 252, step: 8

 2913 23:06:53.632307  iDelay=200, Bit 0, Center 115 (40 ~ 191) 152

 2914 23:06:53.638903  iDelay=200, Bit 1, Center 115 (40 ~ 191) 152

 2915 23:06:53.642244  iDelay=200, Bit 2, Center 111 (40 ~ 183) 144

 2916 23:06:53.645165  iDelay=200, Bit 3, Center 115 (40 ~ 191) 152

 2917 23:06:53.649228  iDelay=200, Bit 4, Center 115 (40 ~ 191) 152

 2918 23:06:53.653064  iDelay=200, Bit 5, Center 107 (32 ~ 183) 152

 2919 23:06:53.659290  iDelay=200, Bit 6, Center 123 (48 ~ 199) 152

 2920 23:06:53.662346  iDelay=200, Bit 7, Center 123 (48 ~ 199) 152

 2921 23:06:53.665683  iDelay=200, Bit 8, Center 95 (24 ~ 167) 144

 2922 23:06:53.669000  iDelay=200, Bit 9, Center 95 (24 ~ 167) 144

 2923 23:06:53.672431  iDelay=200, Bit 10, Center 103 (32 ~ 175) 144

 2924 23:06:53.675733  iDelay=200, Bit 11, Center 99 (32 ~ 167) 136

 2925 23:06:53.682738  iDelay=200, Bit 12, Center 111 (40 ~ 183) 144

 2926 23:06:53.685920  iDelay=200, Bit 13, Center 115 (48 ~ 183) 136

 2927 23:06:53.689612  iDelay=200, Bit 14, Center 119 (48 ~ 191) 144

 2928 23:06:53.692684  iDelay=200, Bit 15, Center 111 (40 ~ 183) 144

 2929 23:06:53.692839  ==

 2930 23:06:53.695915  Dram Type= 6, Freq= 0, CH_0, rank 1

 2931 23:06:53.699283  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2932 23:06:53.702528  ==

 2933 23:06:53.702668  DQS Delay:

 2934 23:06:53.702766  DQS0 = 0, DQS1 = 0

 2935 23:06:53.706169  DQM Delay:

 2936 23:06:53.706297  DQM0 = 115, DQM1 = 106

 2937 23:06:53.709268  DQ Delay:

 2938 23:06:53.712646  DQ0 =115, DQ1 =115, DQ2 =111, DQ3 =115

 2939 23:06:53.716544  DQ4 =115, DQ5 =107, DQ6 =123, DQ7 =123

 2940 23:06:53.719718  DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =99

 2941 23:06:53.723392  DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =111

 2942 23:06:53.723511  

 2943 23:06:53.723577  

 2944 23:06:53.723638  ==

 2945 23:06:53.725929  Dram Type= 6, Freq= 0, CH_0, rank 1

 2946 23:06:53.729749  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2947 23:06:53.729862  ==

 2948 23:06:53.729931  

 2949 23:06:53.729991  

 2950 23:06:53.732807  	TX Vref Scan disable

 2951 23:06:53.736289   == TX Byte 0 ==

 2952 23:06:53.739594  Update DQ  dly =852 (3 ,2, 20)  DQ  OEN =(2 ,7)

 2953 23:06:53.742604  Update DQM dly =852 (3 ,2, 20)  DQM OEN =(2 ,7)

 2954 23:06:53.746564   == TX Byte 1 ==

 2955 23:06:53.750020  Update DQ  dly =845 (3 ,2, 13)  DQ  OEN =(2 ,7)

 2956 23:06:53.753107  Update DQM dly =845 (3 ,2, 13)  DQM OEN =(2 ,7)

 2957 23:06:53.753231  ==

 2958 23:06:53.756419  Dram Type= 6, Freq= 0, CH_0, rank 1

 2959 23:06:53.760189  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2960 23:06:53.760318  ==

 2961 23:06:53.772934  TX Vref=22, minBit 1, minWin=25, winSum=420

 2962 23:06:53.776602  TX Vref=24, minBit 3, minWin=25, winSum=430

 2963 23:06:53.780058  TX Vref=26, minBit 1, minWin=25, winSum=433

 2964 23:06:53.783239  TX Vref=28, minBit 3, minWin=25, winSum=435

 2965 23:06:53.786676  TX Vref=30, minBit 0, minWin=27, winSum=438

 2966 23:06:53.790093  TX Vref=32, minBit 12, minWin=26, winSum=436

 2967 23:06:53.796735  [TxChooseVref] Worse bit 0, Min win 27, Win sum 438, Final Vref 30

 2968 23:06:53.796888  

 2969 23:06:53.800308  Final TX Range 1 Vref 30

 2970 23:06:53.800413  

 2971 23:06:53.800479  ==

 2972 23:06:53.803385  Dram Type= 6, Freq= 0, CH_0, rank 1

 2973 23:06:53.806902  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2974 23:06:53.807043  ==

 2975 23:06:53.807113  

 2976 23:06:53.807173  

 2977 23:06:53.810291  	TX Vref Scan disable

 2978 23:06:53.813962   == TX Byte 0 ==

 2979 23:06:53.816687  Update DQ  dly =852 (3 ,2, 20)  DQ  OEN =(2 ,7)

 2980 23:06:53.820096  Update DQM dly =852 (3 ,2, 20)  DQM OEN =(2 ,7)

 2981 23:06:53.823258   == TX Byte 1 ==

 2982 23:06:53.826988  Update DQ  dly =845 (3 ,2, 13)  DQ  OEN =(2 ,7)

 2983 23:06:53.830249  Update DQM dly =845 (3 ,2, 13)  DQM OEN =(2 ,7)

 2984 23:06:53.830435  

 2985 23:06:53.833269  [DATLAT]

 2986 23:06:53.833392  Freq=1200, CH0 RK1

 2987 23:06:53.833487  

 2988 23:06:53.837073  DATLAT Default: 0xd

 2989 23:06:53.837213  0, 0xFFFF, sum = 0

 2990 23:06:53.840551  1, 0xFFFF, sum = 0

 2991 23:06:53.840684  2, 0xFFFF, sum = 0

 2992 23:06:53.843574  3, 0xFFFF, sum = 0

 2993 23:06:53.843734  4, 0xFFFF, sum = 0

 2994 23:06:53.846583  5, 0xFFFF, sum = 0

 2995 23:06:53.846700  6, 0xFFFF, sum = 0

 2996 23:06:53.850144  7, 0xFFFF, sum = 0

 2997 23:06:53.850266  8, 0xFFFF, sum = 0

 2998 23:06:53.853398  9, 0xFFFF, sum = 0

 2999 23:06:53.853532  10, 0xFFFF, sum = 0

 3000 23:06:53.856864  11, 0xFFFF, sum = 0

 3001 23:06:53.857028  12, 0x0, sum = 1

 3002 23:06:53.860527  13, 0x0, sum = 2

 3003 23:06:53.860671  14, 0x0, sum = 3

 3004 23:06:53.863595  15, 0x0, sum = 4

 3005 23:06:53.863808  best_step = 13

 3006 23:06:53.863887  

 3007 23:06:53.863949  ==

 3008 23:06:53.867147  Dram Type= 6, Freq= 0, CH_0, rank 1

 3009 23:06:53.874414  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3010 23:06:53.874597  ==

 3011 23:06:53.874668  RX Vref Scan: 0

 3012 23:06:53.874768  

 3013 23:06:53.877145  RX Vref 0 -> 0, step: 1

 3014 23:06:53.877235  

 3015 23:06:53.880014  RX Delay -21 -> 252, step: 4

 3016 23:06:53.883802  iDelay=195, Bit 0, Center 114 (43 ~ 186) 144

 3017 23:06:53.887226  iDelay=195, Bit 1, Center 114 (43 ~ 186) 144

 3018 23:06:53.893732  iDelay=195, Bit 2, Center 110 (39 ~ 182) 144

 3019 23:06:53.897520  iDelay=195, Bit 3, Center 114 (43 ~ 186) 144

 3020 23:06:53.900395  iDelay=195, Bit 4, Center 112 (43 ~ 182) 140

 3021 23:06:53.904650  iDelay=195, Bit 5, Center 104 (35 ~ 174) 140

 3022 23:06:53.907524  iDelay=195, Bit 6, Center 122 (51 ~ 194) 144

 3023 23:06:53.910309  iDelay=195, Bit 7, Center 122 (51 ~ 194) 144

 3024 23:06:53.918230  iDelay=195, Bit 8, Center 94 (27 ~ 162) 136

 3025 23:06:53.921253  iDelay=195, Bit 9, Center 92 (23 ~ 162) 140

 3026 23:06:53.923956  iDelay=195, Bit 10, Center 106 (39 ~ 174) 136

 3027 23:06:53.926888  iDelay=195, Bit 11, Center 94 (27 ~ 162) 136

 3028 23:06:53.930799  iDelay=195, Bit 12, Center 110 (43 ~ 178) 136

 3029 23:06:53.937051  iDelay=195, Bit 13, Center 110 (43 ~ 178) 136

 3030 23:06:53.940261  iDelay=195, Bit 14, Center 116 (51 ~ 182) 132

 3031 23:06:53.944127  iDelay=195, Bit 15, Center 114 (47 ~ 182) 136

 3032 23:06:53.944265  ==

 3033 23:06:53.947514  Dram Type= 6, Freq= 0, CH_0, rank 1

 3034 23:06:53.950776  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3035 23:06:53.950918  ==

 3036 23:06:53.953983  DQS Delay:

 3037 23:06:53.954081  DQS0 = 0, DQS1 = 0

 3038 23:06:53.957187  DQM Delay:

 3039 23:06:53.957283  DQM0 = 114, DQM1 = 104

 3040 23:06:53.957350  DQ Delay:

 3041 23:06:53.960640  DQ0 =114, DQ1 =114, DQ2 =110, DQ3 =114

 3042 23:06:53.967334  DQ4 =112, DQ5 =104, DQ6 =122, DQ7 =122

 3043 23:06:53.970306  DQ8 =94, DQ9 =92, DQ10 =106, DQ11 =94

 3044 23:06:53.973871  DQ12 =110, DQ13 =110, DQ14 =116, DQ15 =114

 3045 23:06:53.974025  

 3046 23:06:53.974126  

 3047 23:06:53.980805  [DQSOSCAuto] RK1, (LSB)MR18= 0x5f7, (MSB)MR19= 0x403, tDQSOscB0 = 413 ps tDQSOscB1 = 408 ps

 3048 23:06:53.984393  CH0 RK1: MR19=403, MR18=5F7

 3049 23:06:53.991215  CH0_RK1: MR19=0x403, MR18=0x5F7, DQSOSC=408, MR23=63, INC=39, DEC=26

 3050 23:06:53.993830  [RxdqsGatingPostProcess] freq 1200

 3051 23:06:53.997898  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2

 3052 23:06:54.001093  best DQS0 dly(2T, 0.5T) = (0, 12)

 3053 23:06:54.004248  best DQS1 dly(2T, 0.5T) = (0, 12)

 3054 23:06:54.007332  best DQS0 P1 dly(2T, 0.5T) = (1, 0)

 3055 23:06:54.010896  best DQS1 P1 dly(2T, 0.5T) = (1, 0)

 3056 23:06:54.014412  best DQS0 dly(2T, 0.5T) = (0, 11)

 3057 23:06:54.017688  best DQS1 dly(2T, 0.5T) = (0, 12)

 3058 23:06:54.020667  best DQS0 P1 dly(2T, 0.5T) = (0, 15)

 3059 23:06:54.024657  best DQS1 P1 dly(2T, 0.5T) = (1, 0)

 3060 23:06:54.027841  Pre-setting of DQS Precalculation

 3061 23:06:54.031233  [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13

 3062 23:06:54.031392  ==

 3063 23:06:54.034844  Dram Type= 6, Freq= 0, CH_1, rank 0

 3064 23:06:54.038354  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3065 23:06:54.038555  ==

 3066 23:06:54.044134  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 3067 23:06:54.050922  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39

 3068 23:06:54.058708  [CA 0] Center 38 (9~68) winsize 60

 3069 23:06:54.062184  [CA 1] Center 38 (8~68) winsize 61

 3070 23:06:54.065497  [CA 2] Center 35 (5~65) winsize 61

 3071 23:06:54.069019  [CA 3] Center 34 (4~65) winsize 62

 3072 23:06:54.072351  [CA 4] Center 34 (4~65) winsize 62

 3073 23:06:54.075485  [CA 5] Center 34 (4~64) winsize 61

 3074 23:06:54.075626  

 3075 23:06:54.078790  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 3076 23:06:54.078919  

 3077 23:06:54.082725  [CATrainingPosCal] consider 1 rank data

 3078 23:06:54.086403  u2DelayCellTimex100 = 270/100 ps

 3079 23:06:54.089365  CA0 delay=38 (9~68),Diff = 4 PI (19 cell)

 3080 23:06:54.092442  CA1 delay=38 (8~68),Diff = 4 PI (19 cell)

 3081 23:06:54.096089  CA2 delay=35 (5~65),Diff = 1 PI (4 cell)

 3082 23:06:54.102247  CA3 delay=34 (4~65),Diff = 0 PI (0 cell)

 3083 23:06:54.105938  CA4 delay=34 (4~65),Diff = 0 PI (0 cell)

 3084 23:06:54.109401  CA5 delay=34 (4~64),Diff = 0 PI (0 cell)

 3085 23:06:54.109551  

 3086 23:06:54.112657  CA PerBit enable=1, Macro0, CA PI delay=34

 3087 23:06:54.112782  

 3088 23:06:54.115638  [CBTSetCACLKResult] CA Dly = 34

 3089 23:06:54.115757  CS Dly: 6 (0~37)

 3090 23:06:54.115853  ==

 3091 23:06:54.119368  Dram Type= 6, Freq= 0, CH_1, rank 1

 3092 23:06:54.126749  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3093 23:06:54.126935  ==

 3094 23:06:54.129279  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 3095 23:06:54.136051  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37

 3096 23:06:54.144316  [CA 0] Center 38 (8~68) winsize 61

 3097 23:06:54.147612  [CA 1] Center 38 (9~67) winsize 59

 3098 23:06:54.151046  [CA 2] Center 34 (4~65) winsize 62

 3099 23:06:54.154307  [CA 3] Center 34 (4~65) winsize 62

 3100 23:06:54.158287  [CA 4] Center 34 (4~65) winsize 62

 3101 23:06:54.160808  [CA 5] Center 33 (3~64) winsize 62

 3102 23:06:54.160965  

 3103 23:06:54.164258  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 3104 23:06:54.164391  

 3105 23:06:54.167630  [CATrainingPosCal] consider 2 rank data

 3106 23:06:54.171520  u2DelayCellTimex100 = 270/100 ps

 3107 23:06:54.174793  CA0 delay=38 (9~68),Diff = 4 PI (19 cell)

 3108 23:06:54.178022  CA1 delay=38 (9~67),Diff = 4 PI (19 cell)

 3109 23:06:54.180928  CA2 delay=35 (5~65),Diff = 1 PI (4 cell)

 3110 23:06:54.188340  CA3 delay=34 (4~65),Diff = 0 PI (0 cell)

 3111 23:06:54.191633  CA4 delay=34 (4~65),Diff = 0 PI (0 cell)

 3112 23:06:54.194640  CA5 delay=34 (4~64),Diff = 0 PI (0 cell)

 3113 23:06:54.194764  

 3114 23:06:54.198367  CA PerBit enable=1, Macro0, CA PI delay=34

 3115 23:06:54.198507  

 3116 23:06:54.201350  [CBTSetCACLKResult] CA Dly = 34

 3117 23:06:54.201446  CS Dly: 7 (0~40)

 3118 23:06:54.201513  

 3119 23:06:54.205427  ----->DramcWriteLeveling(PI) begin...

 3120 23:06:54.205546  ==

 3121 23:06:54.207953  Dram Type= 6, Freq= 0, CH_1, rank 0

 3122 23:06:54.214658  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3123 23:06:54.214802  ==

 3124 23:06:54.219501  Write leveling (Byte 0): 29 => 29

 3125 23:06:54.221382  Write leveling (Byte 1): 29 => 29

 3126 23:06:54.221481  DramcWriteLeveling(PI) end<-----

 3127 23:06:54.221547  

 3128 23:06:54.224934  ==

 3129 23:06:54.225035  Dram Type= 6, Freq= 0, CH_1, rank 0

 3130 23:06:54.231730  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3131 23:06:54.231870  ==

 3132 23:06:54.234757  [Gating] SW mode calibration

 3133 23:06:54.242001  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0

 3134 23:06:54.245152  RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)

 3135 23:06:54.252016   0 15  0 | B1->B0 | 2727 2424 | 0 0 | (0 0) (0 0)

 3136 23:06:54.254840   0 15  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3137 23:06:54.258344   0 15  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3138 23:06:54.261456   0 15 12 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)

 3139 23:06:54.268828   0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3140 23:06:54.271470   0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3141 23:06:54.275092   0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3142 23:06:54.282034   0 15 28 | B1->B0 | 3434 3434 | 0 0 | (0 0) (1 0)

 3143 23:06:54.285469   1  0  0 | B1->B0 | 2525 2a2a | 0 0 | (0 0) (0 0)

 3144 23:06:54.288532   1  0  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3145 23:06:54.295497   1  0  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3146 23:06:54.298810   1  0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3147 23:06:54.302331   1  0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3148 23:06:54.309118   1  0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3149 23:06:54.312741   1  0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3150 23:06:54.315565   1  0 28 | B1->B0 | 2727 2525 | 0 0 | (0 0) (0 0)

 3151 23:06:54.322410   1  1  0 | B1->B0 | 4040 3535 | 0 1 | (0 0) (0 0)

 3152 23:06:54.326062   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3153 23:06:54.329158   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3154 23:06:54.332091   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3155 23:06:54.339087   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3156 23:06:54.342149   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3157 23:06:54.345441   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3158 23:06:54.352697   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3159 23:06:54.355410   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 3160 23:06:54.359060   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3161 23:06:54.365810   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3162 23:06:54.369566   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3163 23:06:54.372895   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3164 23:06:54.378977   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3165 23:06:54.382839   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3166 23:06:54.385660   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3167 23:06:54.389291   1  3  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3168 23:06:54.396019   1  3  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3169 23:06:54.399370   1  3  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3170 23:06:54.402576   1  3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3171 23:06:54.409309   1  3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3172 23:06:54.412503   1  3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3173 23:06:54.416439   1  3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3174 23:06:54.423068   1  3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 3175 23:06:54.425835   1  4  0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 3176 23:06:54.429510   1  4  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3177 23:06:54.432885  Total UI for P1: 0, mck2ui 16

 3178 23:06:54.436070  best dqsien dly found for B0: ( 1,  3, 30)

 3179 23:06:54.439670  Total UI for P1: 0, mck2ui 16

 3180 23:06:54.442952  best dqsien dly found for B1: ( 1,  4,  0)

 3181 23:06:54.445986  best DQS0 dly(MCK, UI, PI) = (1, 3, 30)

 3182 23:06:54.449478  best DQS1 dly(MCK, UI, PI) = (1, 4, 0)

 3183 23:06:54.449610  

 3184 23:06:54.452712  best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)

 3185 23:06:54.459359  best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)

 3186 23:06:54.459506  [Gating] SW calibration Done

 3187 23:06:54.459573  ==

 3188 23:06:54.462878  Dram Type= 6, Freq= 0, CH_1, rank 0

 3189 23:06:54.469563  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3190 23:06:54.469719  ==

 3191 23:06:54.469788  RX Vref Scan: 0

 3192 23:06:54.469848  

 3193 23:06:54.472873  RX Vref 0 -> 0, step: 1

 3194 23:06:54.473030  

 3195 23:06:54.476091  RX Delay -40 -> 252, step: 8

 3196 23:06:54.480175  iDelay=200, Bit 0, Center 119 (48 ~ 191) 144

 3197 23:06:54.483612  iDelay=200, Bit 1, Center 111 (40 ~ 183) 144

 3198 23:06:54.486729  iDelay=200, Bit 2, Center 103 (32 ~ 175) 144

 3199 23:06:54.490061  iDelay=200, Bit 3, Center 119 (48 ~ 191) 144

 3200 23:06:54.496623  iDelay=200, Bit 4, Center 111 (40 ~ 183) 144

 3201 23:06:54.499769  iDelay=200, Bit 5, Center 127 (56 ~ 199) 144

 3202 23:06:54.503367  iDelay=200, Bit 6, Center 127 (64 ~ 191) 128

 3203 23:06:54.506290  iDelay=200, Bit 7, Center 115 (48 ~ 183) 136

 3204 23:06:54.510059  iDelay=200, Bit 8, Center 99 (32 ~ 167) 136

 3205 23:06:54.513537  iDelay=200, Bit 9, Center 95 (24 ~ 167) 144

 3206 23:06:54.520940  iDelay=200, Bit 10, Center 107 (40 ~ 175) 136

 3207 23:06:54.523079  iDelay=200, Bit 11, Center 107 (40 ~ 175) 136

 3208 23:06:54.527283  iDelay=200, Bit 12, Center 119 (48 ~ 191) 144

 3209 23:06:54.529995  iDelay=200, Bit 13, Center 115 (48 ~ 183) 136

 3210 23:06:54.533584  iDelay=200, Bit 14, Center 111 (40 ~ 183) 144

 3211 23:06:54.540512  iDelay=200, Bit 15, Center 115 (48 ~ 183) 136

 3212 23:06:54.540664  ==

 3213 23:06:54.544841  Dram Type= 6, Freq= 0, CH_1, rank 0

 3214 23:06:54.546685  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3215 23:06:54.546789  ==

 3216 23:06:54.546855  DQS Delay:

 3217 23:06:54.549974  DQS0 = 0, DQS1 = 0

 3218 23:06:54.550072  DQM Delay:

 3219 23:06:54.553454  DQM0 = 116, DQM1 = 108

 3220 23:06:54.553550  DQ Delay:

 3221 23:06:54.557086  DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =119

 3222 23:06:54.560291  DQ4 =111, DQ5 =127, DQ6 =127, DQ7 =115

 3223 23:06:54.563219  DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107

 3224 23:06:54.566951  DQ12 =119, DQ13 =115, DQ14 =111, DQ15 =115

 3225 23:06:54.567070  

 3226 23:06:54.567139  

 3227 23:06:54.570417  ==

 3228 23:06:54.570526  Dram Type= 6, Freq= 0, CH_1, rank 0

 3229 23:06:54.576845  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3230 23:06:54.576981  ==

 3231 23:06:54.577048  

 3232 23:06:54.577108  

 3233 23:06:54.580426  	TX Vref Scan disable

 3234 23:06:54.580522   == TX Byte 0 ==

 3235 23:06:54.583773  Update DQ  dly =848 (3 ,2, 16)  DQ  OEN =(2 ,7)

 3236 23:06:54.590312  Update DQM dly =848 (3 ,2, 16)  DQM OEN =(2 ,7)

 3237 23:06:54.590495   == TX Byte 1 ==

 3238 23:06:54.593656  Update DQ  dly =846 (3 ,2, 14)  DQ  OEN =(2 ,7)

 3239 23:06:54.600270  Update DQM dly =846 (3 ,2, 14)  DQM OEN =(2 ,7)

 3240 23:06:54.600416  ==

 3241 23:06:54.603419  Dram Type= 6, Freq= 0, CH_1, rank 0

 3242 23:06:54.606731  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3243 23:06:54.606843  ==

 3244 23:06:54.618607  TX Vref=22, minBit 1, minWin=25, winSum=412

 3245 23:06:54.622382  TX Vref=24, minBit 2, minWin=25, winSum=420

 3246 23:06:54.625482  TX Vref=26, minBit 2, minWin=25, winSum=427

 3247 23:06:54.628812  TX Vref=28, minBit 2, minWin=26, winSum=431

 3248 23:06:54.632325  TX Vref=30, minBit 2, minWin=26, winSum=433

 3249 23:06:54.635630  TX Vref=32, minBit 2, minWin=26, winSum=429

 3250 23:06:54.642341  [TxChooseVref] Worse bit 2, Min win 26, Win sum 433, Final Vref 30

 3251 23:06:54.642529  

 3252 23:06:54.645628  Final TX Range 1 Vref 30

 3253 23:06:54.645726  

 3254 23:06:54.645793  ==

 3255 23:06:54.649896  Dram Type= 6, Freq= 0, CH_1, rank 0

 3256 23:06:54.652190  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3257 23:06:54.652292  ==

 3258 23:06:54.652360  

 3259 23:06:54.652420  

 3260 23:06:54.656262  	TX Vref Scan disable

 3261 23:06:54.659426   == TX Byte 0 ==

 3262 23:06:54.662216  Update DQ  dly =847 (3 ,2, 15)  DQ  OEN =(2 ,7)

 3263 23:06:54.665441  Update DQM dly =847 (3 ,2, 15)  DQM OEN =(2 ,7)

 3264 23:06:54.669938   == TX Byte 1 ==

 3265 23:06:54.672591  Update DQ  dly =846 (3 ,2, 14)  DQ  OEN =(2 ,7)

 3266 23:06:54.675655  Update DQM dly =846 (3 ,2, 14)  DQM OEN =(2 ,7)

 3267 23:06:54.675769  

 3268 23:06:54.679443  [DATLAT]

 3269 23:06:54.679549  Freq=1200, CH1 RK0

 3270 23:06:54.679616  

 3271 23:06:54.682392  DATLAT Default: 0xd

 3272 23:06:54.682507  0, 0xFFFF, sum = 0

 3273 23:06:54.686150  1, 0xFFFF, sum = 0

 3274 23:06:54.686255  2, 0xFFFF, sum = 0

 3275 23:06:54.689276  3, 0xFFFF, sum = 0

 3276 23:06:54.689376  4, 0xFFFF, sum = 0

 3277 23:06:54.692367  5, 0xFFFF, sum = 0

 3278 23:06:54.692471  6, 0xFFFF, sum = 0

 3279 23:06:54.696065  7, 0xFFFF, sum = 0

 3280 23:06:54.696176  8, 0xFFFF, sum = 0

 3281 23:06:54.699685  9, 0xFFFF, sum = 0

 3282 23:06:54.699795  10, 0xFFFF, sum = 0

 3283 23:06:54.702940  11, 0xFFFF, sum = 0

 3284 23:06:54.703042  12, 0x0, sum = 1

 3285 23:06:54.707202  13, 0x0, sum = 2

 3286 23:06:54.707311  14, 0x0, sum = 3

 3287 23:06:54.709542  15, 0x0, sum = 4

 3288 23:06:54.709632  best_step = 13

 3289 23:06:54.709697  

 3290 23:06:54.709758  ==

 3291 23:06:54.712785  Dram Type= 6, Freq= 0, CH_1, rank 0

 3292 23:06:54.716229  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3293 23:06:54.719873  ==

 3294 23:06:54.719998  RX Vref Scan: 1

 3295 23:06:54.720067  

 3296 23:06:54.723367  Set Vref Range= 32 -> 127

 3297 23:06:54.723464  

 3298 23:06:54.726038  RX Vref 32 -> 127, step: 1

 3299 23:06:54.726127  

 3300 23:06:54.726192  RX Delay -21 -> 252, step: 4

 3301 23:06:54.726254  

 3302 23:06:54.729961  Set Vref, RX VrefLevel [Byte0]: 32

 3303 23:06:54.732758                           [Byte1]: 32

 3304 23:06:54.737150  

 3305 23:06:54.737278  Set Vref, RX VrefLevel [Byte0]: 33

 3306 23:06:54.740226                           [Byte1]: 33

 3307 23:06:54.745012  

 3308 23:06:54.745135  Set Vref, RX VrefLevel [Byte0]: 34

 3309 23:06:54.748262                           [Byte1]: 34

 3310 23:06:54.753312  

 3311 23:06:54.753451  Set Vref, RX VrefLevel [Byte0]: 35

 3312 23:06:54.756581                           [Byte1]: 35

 3313 23:06:54.760792  

 3314 23:06:54.760909  Set Vref, RX VrefLevel [Byte0]: 36

 3315 23:06:54.764799                           [Byte1]: 36

 3316 23:06:54.769135  

 3317 23:06:54.769266  Set Vref, RX VrefLevel [Byte0]: 37

 3318 23:06:54.771473                           [Byte1]: 37

 3319 23:06:54.776924  

 3320 23:06:54.777067  Set Vref, RX VrefLevel [Byte0]: 38

 3321 23:06:54.779510                           [Byte1]: 38

 3322 23:06:54.784633  

 3323 23:06:54.784766  Set Vref, RX VrefLevel [Byte0]: 39

 3324 23:06:54.788021                           [Byte1]: 39

 3325 23:06:54.791982  

 3326 23:06:54.792106  Set Vref, RX VrefLevel [Byte0]: 40

 3327 23:06:54.795911                           [Byte1]: 40

 3328 23:06:54.799900  

 3329 23:06:54.800022  Set Vref, RX VrefLevel [Byte0]: 41

 3330 23:06:54.804251                           [Byte1]: 41

 3331 23:06:54.808261  

 3332 23:06:54.808381  Set Vref, RX VrefLevel [Byte0]: 42

 3333 23:06:54.811606                           [Byte1]: 42

 3334 23:06:54.816227  

 3335 23:06:54.816351  Set Vref, RX VrefLevel [Byte0]: 43

 3336 23:06:54.819780                           [Byte1]: 43

 3337 23:06:54.823871  

 3338 23:06:54.823988  Set Vref, RX VrefLevel [Byte0]: 44

 3339 23:06:54.827165                           [Byte1]: 44

 3340 23:06:54.831842  

 3341 23:06:54.831963  Set Vref, RX VrefLevel [Byte0]: 45

 3342 23:06:54.835017                           [Byte1]: 45

 3343 23:06:54.839972  

 3344 23:06:54.840103  Set Vref, RX VrefLevel [Byte0]: 46

 3345 23:06:54.843079                           [Byte1]: 46

 3346 23:06:54.848018  

 3347 23:06:54.848143  Set Vref, RX VrefLevel [Byte0]: 47

 3348 23:06:54.851519                           [Byte1]: 47

 3349 23:06:54.856470  

 3350 23:06:54.856596  Set Vref, RX VrefLevel [Byte0]: 48

 3351 23:06:54.858960                           [Byte1]: 48

 3352 23:06:54.863380  

 3353 23:06:54.863508  Set Vref, RX VrefLevel [Byte0]: 49

 3354 23:06:54.866607                           [Byte1]: 49

 3355 23:06:54.871993  

 3356 23:06:54.872128  Set Vref, RX VrefLevel [Byte0]: 50

 3357 23:06:54.875190                           [Byte1]: 50

 3358 23:06:54.879371  

 3359 23:06:54.879505  Set Vref, RX VrefLevel [Byte0]: 51

 3360 23:06:54.882857                           [Byte1]: 51

 3361 23:06:54.887221  

 3362 23:06:54.887353  Set Vref, RX VrefLevel [Byte0]: 52

 3363 23:06:54.891471                           [Byte1]: 52

 3364 23:06:54.895133  

 3365 23:06:54.895280  Set Vref, RX VrefLevel [Byte0]: 53

 3366 23:06:54.899358                           [Byte1]: 53

 3367 23:06:54.903422  

 3368 23:06:54.903550  Set Vref, RX VrefLevel [Byte0]: 54

 3369 23:06:54.906761                           [Byte1]: 54

 3370 23:06:54.911840  

 3371 23:06:54.911973  Set Vref, RX VrefLevel [Byte0]: 55

 3372 23:06:54.915304                           [Byte1]: 55

 3373 23:06:54.918786  

 3374 23:06:54.918895  Set Vref, RX VrefLevel [Byte0]: 56

 3375 23:06:54.922089                           [Byte1]: 56

 3376 23:06:54.926885  

 3377 23:06:54.927015  Set Vref, RX VrefLevel [Byte0]: 57

 3378 23:06:54.930098                           [Byte1]: 57

 3379 23:06:54.934755  

 3380 23:06:54.934882  Set Vref, RX VrefLevel [Byte0]: 58

 3381 23:06:54.938747                           [Byte1]: 58

 3382 23:06:54.942921  

 3383 23:06:54.943050  Set Vref, RX VrefLevel [Byte0]: 59

 3384 23:06:54.945886                           [Byte1]: 59

 3385 23:06:54.950563  

 3386 23:06:54.950690  Set Vref, RX VrefLevel [Byte0]: 60

 3387 23:06:54.954253                           [Byte1]: 60

 3388 23:06:54.958839  

 3389 23:06:54.958959  Set Vref, RX VrefLevel [Byte0]: 61

 3390 23:06:54.962241                           [Byte1]: 61

 3391 23:06:54.966884  

 3392 23:06:54.967021  Set Vref, RX VrefLevel [Byte0]: 62

 3393 23:06:54.969828                           [Byte1]: 62

 3394 23:06:54.974609  

 3395 23:06:54.974732  Set Vref, RX VrefLevel [Byte0]: 63

 3396 23:06:54.977438                           [Byte1]: 63

 3397 23:06:54.982137  

 3398 23:06:54.982263  Set Vref, RX VrefLevel [Byte0]: 64

 3399 23:06:54.985806                           [Byte1]: 64

 3400 23:06:54.990589  

 3401 23:06:54.990783  Set Vref, RX VrefLevel [Byte0]: 65

 3402 23:06:54.994615                           [Byte1]: 65

 3403 23:06:54.998214  

 3404 23:06:54.998334  Set Vref, RX VrefLevel [Byte0]: 66

 3405 23:06:55.001639                           [Byte1]: 66

 3406 23:06:55.006222  

 3407 23:06:55.006351  Set Vref, RX VrefLevel [Byte0]: 67

 3408 23:06:55.009995                           [Byte1]: 67

 3409 23:06:55.014385  

 3410 23:06:55.014534  Set Vref, RX VrefLevel [Byte0]: 68

 3411 23:06:55.017243                           [Byte1]: 68

 3412 23:06:55.022183  

 3413 23:06:55.022318  Final RX Vref Byte 0 = 57 to rank0

 3414 23:06:55.025446  Final RX Vref Byte 1 = 51 to rank0

 3415 23:06:55.028910  Final RX Vref Byte 0 = 57 to rank1

 3416 23:06:55.032345  Final RX Vref Byte 1 = 51 to rank1==

 3417 23:06:55.035212  Dram Type= 6, Freq= 0, CH_1, rank 0

 3418 23:06:55.041964  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3419 23:06:55.042109  ==

 3420 23:06:55.042182  DQS Delay:

 3421 23:06:55.042243  DQS0 = 0, DQS1 = 0

 3422 23:06:55.045619  DQM Delay:

 3423 23:06:55.045717  DQM0 = 115, DQM1 = 109

 3424 23:06:55.048809  DQ Delay:

 3425 23:06:55.052135  DQ0 =116, DQ1 =108, DQ2 =106, DQ3 =114

 3426 23:06:55.055448  DQ4 =114, DQ5 =126, DQ6 =126, DQ7 =114

 3427 23:06:55.058880  DQ8 =98, DQ9 =98, DQ10 =110, DQ11 =104

 3428 23:06:55.062007  DQ12 =116, DQ13 =116, DQ14 =116, DQ15 =114

 3429 23:06:55.062118  

 3430 23:06:55.062187  

 3431 23:06:55.069483  [DQSOSCAuto] RK0, (LSB)MR18= 0xfce1, (MSB)MR19= 0x303, tDQSOscB0 = 422 ps tDQSOscB1 = 411 ps

 3432 23:06:55.072119  CH1 RK0: MR19=303, MR18=FCE1

 3433 23:06:55.079683  CH1_RK0: MR19=0x303, MR18=0xFCE1, DQSOSC=411, MR23=63, INC=38, DEC=25

 3434 23:06:55.079829  

 3435 23:06:55.083030  ----->DramcWriteLeveling(PI) begin...

 3436 23:06:55.083132  ==

 3437 23:06:55.085938  Dram Type= 6, Freq= 0, CH_1, rank 1

 3438 23:06:55.089437  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3439 23:06:55.089553  ==

 3440 23:06:55.092942  Write leveling (Byte 0): 27 => 27

 3441 23:06:55.095804  Write leveling (Byte 1): 28 => 28

 3442 23:06:55.099171  DramcWriteLeveling(PI) end<-----

 3443 23:06:55.099289  

 3444 23:06:55.099355  ==

 3445 23:06:55.102630  Dram Type= 6, Freq= 0, CH_1, rank 1

 3446 23:06:55.106274  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3447 23:06:55.106392  ==

 3448 23:06:55.109314  [Gating] SW mode calibration

 3449 23:06:55.116541  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0

 3450 23:06:55.123085  RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)

 3451 23:06:55.126699   0 15  0 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)

 3452 23:06:55.130253   0 15  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3453 23:06:55.136464   0 15  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3454 23:06:55.140427   0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3455 23:06:55.143354   0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3456 23:06:55.149797   0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)

 3457 23:06:55.152976   0 15 24 | B1->B0 | 3434 2b2b | 0 0 | (0 0) (0 1)

 3458 23:06:55.157432   0 15 28 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)

 3459 23:06:55.162996   1  0  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3460 23:06:55.166519   1  0  4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)

 3461 23:06:55.170080   1  0  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3462 23:06:55.176198   1  0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3463 23:06:55.179590   1  0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3464 23:06:55.183188   1  0 20 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)

 3465 23:06:55.189723   1  0 24 | B1->B0 | 2929 4141 | 0 0 | (0 0) (0 0)

 3466 23:06:55.193802   1  0 28 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)

 3467 23:06:55.196292   1  1  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3468 23:06:55.199945   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3469 23:06:55.206655   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3470 23:06:55.209606   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3471 23:06:55.213548   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3472 23:06:55.220028   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 3473 23:06:55.223374   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 3474 23:06:55.226344   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 3475 23:06:55.233274   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3476 23:06:55.236787   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3477 23:06:55.240249   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3478 23:06:55.246461   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3479 23:06:55.250875   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3480 23:06:55.253087   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3481 23:06:55.259995   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3482 23:06:55.263668   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3483 23:06:55.266923   1  3  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3484 23:06:55.271232   1  3  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3485 23:06:55.277798   1  3  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3486 23:06:55.279992   1  3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3487 23:06:55.284213   1  3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3488 23:06:55.290138   1  3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 3489 23:06:55.293512   1  3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 3490 23:06:55.297313   1  3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 3491 23:06:55.300583  Total UI for P1: 0, mck2ui 16

 3492 23:06:55.303285  best dqsien dly found for B0: ( 1,  3, 22)

 3493 23:06:55.310311   1  4  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3494 23:06:55.310515  Total UI for P1: 0, mck2ui 16

 3495 23:06:55.316570  best dqsien dly found for B1: ( 1,  3, 28)

 3496 23:06:55.320293  best DQS0 dly(MCK, UI, PI) = (1, 3, 22)

 3497 23:06:55.323375  best DQS1 dly(MCK, UI, PI) = (1, 3, 28)

 3498 23:06:55.323493  

 3499 23:06:55.326760  best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)

 3500 23:06:55.330162  best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)

 3501 23:06:55.333759  [Gating] SW calibration Done

 3502 23:06:55.333877  ==

 3503 23:06:55.337307  Dram Type= 6, Freq= 0, CH_1, rank 1

 3504 23:06:55.340527  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3505 23:06:55.340636  ==

 3506 23:06:55.343317  RX Vref Scan: 0

 3507 23:06:55.343418  

 3508 23:06:55.343485  RX Vref 0 -> 0, step: 1

 3509 23:06:55.343547  

 3510 23:06:55.346641  RX Delay -40 -> 252, step: 8

 3511 23:06:55.350324  iDelay=200, Bit 0, Center 115 (40 ~ 191) 152

 3512 23:06:55.356581  iDelay=200, Bit 1, Center 111 (40 ~ 183) 144

 3513 23:06:55.360290  iDelay=200, Bit 2, Center 103 (32 ~ 175) 144

 3514 23:06:55.363687  iDelay=200, Bit 3, Center 111 (40 ~ 183) 144

 3515 23:06:55.366832  iDelay=200, Bit 4, Center 111 (40 ~ 183) 144

 3516 23:06:55.370568  iDelay=200, Bit 5, Center 127 (56 ~ 199) 144

 3517 23:06:55.377003  iDelay=200, Bit 6, Center 123 (48 ~ 199) 152

 3518 23:06:55.379905  iDelay=200, Bit 7, Center 107 (40 ~ 175) 136

 3519 23:06:55.383203  iDelay=200, Bit 8, Center 99 (24 ~ 175) 152

 3520 23:06:55.386943  iDelay=200, Bit 9, Center 95 (24 ~ 167) 144

 3521 23:06:55.390095  iDelay=200, Bit 10, Center 111 (40 ~ 183) 144

 3522 23:06:55.396609  iDelay=200, Bit 11, Center 103 (32 ~ 175) 144

 3523 23:06:55.399738  iDelay=200, Bit 12, Center 115 (48 ~ 183) 136

 3524 23:06:55.403264  iDelay=200, Bit 13, Center 119 (48 ~ 191) 144

 3525 23:06:55.406852  iDelay=200, Bit 14, Center 119 (48 ~ 191) 144

 3526 23:06:55.410276  iDelay=200, Bit 15, Center 115 (48 ~ 183) 136

 3527 23:06:55.410462  ==

 3528 23:06:55.413636  Dram Type= 6, Freq= 0, CH_1, rank 1

 3529 23:06:55.420737  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3530 23:06:55.420886  ==

 3531 23:06:55.420959  DQS Delay:

 3532 23:06:55.423507  DQS0 = 0, DQS1 = 0

 3533 23:06:55.423597  DQM Delay:

 3534 23:06:55.427276  DQM0 = 113, DQM1 = 109

 3535 23:06:55.427383  DQ Delay:

 3536 23:06:55.429942  DQ0 =115, DQ1 =111, DQ2 =103, DQ3 =111

 3537 23:06:55.433863  DQ4 =111, DQ5 =127, DQ6 =123, DQ7 =107

 3538 23:06:55.437268  DQ8 =99, DQ9 =95, DQ10 =111, DQ11 =103

 3539 23:06:55.440712  DQ12 =115, DQ13 =119, DQ14 =119, DQ15 =115

 3540 23:06:55.440835  

 3541 23:06:55.440906  

 3542 23:06:55.440996  ==

 3543 23:06:55.443894  Dram Type= 6, Freq= 0, CH_1, rank 1

 3544 23:06:55.447265  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3545 23:06:55.447394  ==

 3546 23:06:55.450384  

 3547 23:06:55.450521  

 3548 23:06:55.450592  	TX Vref Scan disable

 3549 23:06:55.453545   == TX Byte 0 ==

 3550 23:06:55.457403  Update DQ  dly =846 (3 ,2, 14)  DQ  OEN =(2 ,7)

 3551 23:06:55.460667  Update DQM dly =846 (3 ,2, 14)  DQM OEN =(2 ,7)

 3552 23:06:55.463735   == TX Byte 1 ==

 3553 23:06:55.466638  Update DQ  dly =846 (3 ,2, 14)  DQ  OEN =(2 ,7)

 3554 23:06:55.469950  Update DQM dly =846 (3 ,2, 14)  DQM OEN =(2 ,7)

 3555 23:06:55.470100  ==

 3556 23:06:55.473498  Dram Type= 6, Freq= 0, CH_1, rank 1

 3557 23:06:55.479876  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3558 23:06:55.480039  ==

 3559 23:06:55.491263  TX Vref=22, minBit 1, minWin=25, winSum=420

 3560 23:06:55.494012  TX Vref=24, minBit 7, minWin=25, winSum=424

 3561 23:06:55.497465  TX Vref=26, minBit 0, minWin=26, winSum=431

 3562 23:06:55.501162  TX Vref=28, minBit 2, minWin=26, winSum=430

 3563 23:06:55.504075  TX Vref=30, minBit 2, minWin=26, winSum=434

 3564 23:06:55.507611  TX Vref=32, minBit 2, minWin=26, winSum=429

 3565 23:06:55.514197  [TxChooseVref] Worse bit 2, Min win 26, Win sum 434, Final Vref 30

 3566 23:06:55.514350  

 3567 23:06:55.518147  Final TX Range 1 Vref 30

 3568 23:06:55.518274  

 3569 23:06:55.518346  ==

 3570 23:06:55.520526  Dram Type= 6, Freq= 0, CH_1, rank 1

 3571 23:06:55.523775  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3572 23:06:55.523884  ==

 3573 23:06:55.523970  

 3574 23:06:55.527108  

 3575 23:06:55.527223  	TX Vref Scan disable

 3576 23:06:55.530914   == TX Byte 0 ==

 3577 23:06:55.533740  Update DQ  dly =845 (3 ,2, 13)  DQ  OEN =(2 ,7)

 3578 23:06:55.537091  Update DQM dly =845 (3 ,2, 13)  DQM OEN =(2 ,7)

 3579 23:06:55.541205   == TX Byte 1 ==

 3580 23:06:55.543806  Update DQ  dly =845 (3 ,2, 13)  DQ  OEN =(2 ,7)

 3581 23:06:55.547520  Update DQM dly =845 (3 ,2, 13)  DQM OEN =(2 ,7)

 3582 23:06:55.547682  

 3583 23:06:55.550517  [DATLAT]

 3584 23:06:55.550641  Freq=1200, CH1 RK1

 3585 23:06:55.550770  

 3586 23:06:55.553874  DATLAT Default: 0xd

 3587 23:06:55.553977  0, 0xFFFF, sum = 0

 3588 23:06:55.557763  1, 0xFFFF, sum = 0

 3589 23:06:55.557874  2, 0xFFFF, sum = 0

 3590 23:06:55.560409  3, 0xFFFF, sum = 0

 3591 23:06:55.560515  4, 0xFFFF, sum = 0

 3592 23:06:55.563878  5, 0xFFFF, sum = 0

 3593 23:06:55.564004  6, 0xFFFF, sum = 0

 3594 23:06:55.567372  7, 0xFFFF, sum = 0

 3595 23:06:55.567462  8, 0xFFFF, sum = 0

 3596 23:06:55.570601  9, 0xFFFF, sum = 0

 3597 23:06:55.573868  10, 0xFFFF, sum = 0

 3598 23:06:55.573960  11, 0xFFFF, sum = 0

 3599 23:06:55.577556  12, 0x0, sum = 1

 3600 23:06:55.577652  13, 0x0, sum = 2

 3601 23:06:55.577720  14, 0x0, sum = 3

 3602 23:06:55.581204  15, 0x0, sum = 4

 3603 23:06:55.581299  best_step = 13

 3604 23:06:55.581366  

 3605 23:06:55.584135  ==

 3606 23:06:55.584224  Dram Type= 6, Freq= 0, CH_1, rank 1

 3607 23:06:55.590859  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3608 23:06:55.590981  ==

 3609 23:06:55.591049  RX Vref Scan: 0

 3610 23:06:55.591112  

 3611 23:06:55.594594  RX Vref 0 -> 0, step: 1

 3612 23:06:55.594686  

 3613 23:06:55.597373  RX Delay -21 -> 252, step: 4

 3614 23:06:55.600674  iDelay=191, Bit 0, Center 112 (43 ~ 182) 140

 3615 23:06:55.604131  iDelay=191, Bit 1, Center 110 (43 ~ 178) 136

 3616 23:06:55.610802  iDelay=191, Bit 2, Center 104 (39 ~ 170) 132

 3617 23:06:55.614370  iDelay=191, Bit 3, Center 112 (47 ~ 178) 132

 3618 23:06:55.617120  iDelay=191, Bit 4, Center 114 (47 ~ 182) 136

 3619 23:06:55.620497  iDelay=191, Bit 5, Center 124 (59 ~ 190) 132

 3620 23:06:55.624053  iDelay=191, Bit 6, Center 122 (55 ~ 190) 136

 3621 23:06:55.631721  iDelay=191, Bit 7, Center 110 (47 ~ 174) 128

 3622 23:06:55.634131  iDelay=191, Bit 8, Center 98 (31 ~ 166) 136

 3623 23:06:55.637501  iDelay=191, Bit 9, Center 98 (35 ~ 162) 128

 3624 23:06:55.640808  iDelay=191, Bit 10, Center 110 (43 ~ 178) 136

 3625 23:06:55.644087  iDelay=191, Bit 11, Center 102 (35 ~ 170) 136

 3626 23:06:55.651008  iDelay=191, Bit 12, Center 114 (51 ~ 178) 128

 3627 23:06:55.654297  iDelay=191, Bit 13, Center 120 (55 ~ 186) 132

 3628 23:06:55.657174  iDelay=191, Bit 14, Center 118 (55 ~ 182) 128

 3629 23:06:55.661252  iDelay=191, Bit 15, Center 116 (51 ~ 182) 132

 3630 23:06:55.661357  ==

 3631 23:06:55.664828  Dram Type= 6, Freq= 0, CH_1, rank 1

 3632 23:06:55.668638  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3633 23:06:55.671033  ==

 3634 23:06:55.671124  DQS Delay:

 3635 23:06:55.671189  DQS0 = 0, DQS1 = 0

 3636 23:06:55.674632  DQM Delay:

 3637 23:06:55.674748  DQM0 = 113, DQM1 = 109

 3638 23:06:55.677712  DQ Delay:

 3639 23:06:55.681240  DQ0 =112, DQ1 =110, DQ2 =104, DQ3 =112

 3640 23:06:55.684199  DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =110

 3641 23:06:55.687364  DQ8 =98, DQ9 =98, DQ10 =110, DQ11 =102

 3642 23:06:55.691210  DQ12 =114, DQ13 =120, DQ14 =118, DQ15 =116

 3643 23:06:55.691309  

 3644 23:06:55.691375  

 3645 23:06:55.697396  [DQSOSCAuto] RK1, (LSB)MR18= 0xf6fd, (MSB)MR19= 0x303, tDQSOscB0 = 411 ps tDQSOscB1 = 414 ps

 3646 23:06:55.701228  CH1 RK1: MR19=303, MR18=F6FD

 3647 23:06:55.707885  CH1_RK1: MR19=0x303, MR18=0xF6FD, DQSOSC=411, MR23=63, INC=38, DEC=25

 3648 23:06:55.711515  [RxdqsGatingPostProcess] freq 1200

 3649 23:06:55.717808  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2

 3650 23:06:55.717954  best DQS0 dly(2T, 0.5T) = (0, 11)

 3651 23:06:55.720905  best DQS1 dly(2T, 0.5T) = (0, 12)

 3652 23:06:55.724369  best DQS0 P1 dly(2T, 0.5T) = (0, 15)

 3653 23:06:55.727946  best DQS1 P1 dly(2T, 0.5T) = (1, 0)

 3654 23:06:55.731045  best DQS0 dly(2T, 0.5T) = (0, 11)

 3655 23:06:55.734350  best DQS1 dly(2T, 0.5T) = (0, 11)

 3656 23:06:55.737868  best DQS0 P1 dly(2T, 0.5T) = (0, 15)

 3657 23:06:55.740983  best DQS1 P1 dly(2T, 0.5T) = (0, 15)

 3658 23:06:55.744603  Pre-setting of DQS Precalculation

 3659 23:06:55.747876  [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13

 3660 23:06:55.757903  sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2

 3661 23:06:55.764853  calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464

 3662 23:06:55.764994  

 3663 23:06:55.765062  

 3664 23:06:55.768250  [Calibration Summary] 2400 Mbps

 3665 23:06:55.768341  CH 0, Rank 0

 3666 23:06:55.770885  SW Impedance     : PASS

 3667 23:06:55.770971  DUTY Scan        : NO K

 3668 23:06:55.774373  ZQ Calibration   : PASS

 3669 23:06:55.777609  Jitter Meter     : NO K

 3670 23:06:55.777709  CBT Training     : PASS

 3671 23:06:55.781171  Write leveling   : PASS

 3672 23:06:55.784695  RX DQS gating    : PASS

 3673 23:06:55.784798  RX DQ/DQS(RDDQC) : PASS

 3674 23:06:55.788490  TX DQ/DQS        : PASS

 3675 23:06:55.791608  RX DATLAT        : PASS

 3676 23:06:55.791713  RX DQ/DQS(Engine): PASS

 3677 23:06:55.794912  TX OE            : NO K

 3678 23:06:55.795007  All Pass.

 3679 23:06:55.795074  

 3680 23:06:55.797514  CH 0, Rank 1

 3681 23:06:55.797602  SW Impedance     : PASS

 3682 23:06:55.801079  DUTY Scan        : NO K

 3683 23:06:55.801172  ZQ Calibration   : PASS

 3684 23:06:55.804683  Jitter Meter     : NO K

 3685 23:06:55.807799  CBT Training     : PASS

 3686 23:06:55.807899  Write leveling   : PASS

 3687 23:06:55.811343  RX DQS gating    : PASS

 3688 23:06:55.815500  RX DQ/DQS(RDDQC) : PASS

 3689 23:06:55.815609  TX DQ/DQS        : PASS

 3690 23:06:55.818984  RX DATLAT        : PASS

 3691 23:06:55.821003  RX DQ/DQS(Engine): PASS

 3692 23:06:55.821094  TX OE            : NO K

 3693 23:06:55.824466  All Pass.

 3694 23:06:55.824556  

 3695 23:06:55.824623  CH 1, Rank 0

 3696 23:06:55.828146  SW Impedance     : PASS

 3697 23:06:55.828257  DUTY Scan        : NO K

 3698 23:06:55.831112  ZQ Calibration   : PASS

 3699 23:06:55.834555  Jitter Meter     : NO K

 3700 23:06:55.834640  CBT Training     : PASS

 3701 23:06:55.838348  Write leveling   : PASS

 3702 23:06:55.838490  RX DQS gating    : PASS

 3703 23:06:55.842052  RX DQ/DQS(RDDQC) : PASS

 3704 23:06:55.844947  TX DQ/DQS        : PASS

 3705 23:06:55.845060  RX DATLAT        : PASS

 3706 23:06:55.847942  RX DQ/DQS(Engine): PASS

 3707 23:06:55.851472  TX OE            : NO K

 3708 23:06:55.851589  All Pass.

 3709 23:06:55.851688  

 3710 23:06:55.851776  CH 1, Rank 1

 3711 23:06:55.854548  SW Impedance     : PASS

 3712 23:06:55.858405  DUTY Scan        : NO K

 3713 23:06:55.858523  ZQ Calibration   : PASS

 3714 23:06:55.861662  Jitter Meter     : NO K

 3715 23:06:55.865779  CBT Training     : PASS

 3716 23:06:55.865895  Write leveling   : PASS

 3717 23:06:55.869032  RX DQS gating    : PASS

 3718 23:06:55.871479  RX DQ/DQS(RDDQC) : PASS

 3719 23:06:55.871568  TX DQ/DQS        : PASS

 3720 23:06:55.874548  RX DATLAT        : PASS

 3721 23:06:55.878278  RX DQ/DQS(Engine): PASS

 3722 23:06:55.878391  TX OE            : NO K

 3723 23:06:55.878487  All Pass.

 3724 23:06:55.878549  

 3725 23:06:55.881691  DramC Write-DBI off

 3726 23:06:55.884545  	PER_BANK_REFRESH: Hybrid Mode

 3727 23:06:55.884637  TX_TRACKING: ON

 3728 23:06:55.894985  [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1

 3729 23:06:55.898635  [FAST_K] Save calibration result to emmc

 3730 23:06:55.901817  dramc_set_vcore_voltage set vcore to 650000

 3731 23:06:55.904646  Read voltage for 600, 5

 3732 23:06:55.904739  Vio18 = 0

 3733 23:06:55.904807  Vcore = 650000

 3734 23:06:55.908722  Vdram = 0

 3735 23:06:55.908815  Vddq = 0

 3736 23:06:55.908880  Vmddr = 0

 3737 23:06:55.915244  [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0

 3738 23:06:55.917809  [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0

 3739 23:06:55.921329  MEM_TYPE=3, freq_sel=19

 3740 23:06:55.924738  sv_algorithm_assistance_LP4_1600 

 3741 23:06:55.928218  ============ PULL DRAM RESETB DOWN ============

 3742 23:06:55.931530  ========== PULL DRAM RESETB DOWN end =========

 3743 23:06:55.938217  [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2

 3744 23:06:55.941907  =================================== 

 3745 23:06:55.944857  LPDDR4 DRAM CONFIGURATION

 3746 23:06:55.948031  =================================== 

 3747 23:06:55.948146  EX_ROW_EN[0]    = 0x0

 3748 23:06:55.951820  EX_ROW_EN[1]    = 0x0

 3749 23:06:55.951904  LP4Y_EN      = 0x0

 3750 23:06:55.954881  WORK_FSP     = 0x0

 3751 23:06:55.954980  WL           = 0x2

 3752 23:06:55.958172  RL           = 0x2

 3753 23:06:55.958265  BL           = 0x2

 3754 23:06:55.961347  RPST         = 0x0

 3755 23:06:55.961438  RD_PRE       = 0x0

 3756 23:06:55.965432  WR_PRE       = 0x1

 3757 23:06:55.965536  WR_PST       = 0x0

 3758 23:06:55.969025  DBI_WR       = 0x0

 3759 23:06:55.969121  DBI_RD       = 0x0

 3760 23:06:55.971884  OTF          = 0x1

 3761 23:06:55.974590  =================================== 

 3762 23:06:55.978299  =================================== 

 3763 23:06:55.978447  ANA top config

 3764 23:06:55.982262  =================================== 

 3765 23:06:55.985154  DLL_ASYNC_EN            =  0

 3766 23:06:55.988157  ALL_SLAVE_EN            =  1

 3767 23:06:55.991828  NEW_RANK_MODE           =  1

 3768 23:06:55.991961  DLL_IDLE_MODE           =  1

 3769 23:06:55.994766  LP45_APHY_COMB_EN       =  1

 3770 23:06:55.998349  TX_ODT_DIS              =  1

 3771 23:06:56.001764  NEW_8X_MODE             =  1

 3772 23:06:56.005488  =================================== 

 3773 23:06:56.009149  =================================== 

 3774 23:06:56.013210  data_rate                  = 1200

 3775 23:06:56.013336  CKR                        = 1

 3776 23:06:56.015365  DQ_P2S_RATIO               = 8

 3777 23:06:56.018278  =================================== 

 3778 23:06:56.021773  CA_P2S_RATIO               = 8

 3779 23:06:56.025508  DQ_CA_OPEN                 = 0

 3780 23:06:56.028861  DQ_SEMI_OPEN               = 0

 3781 23:06:56.028962  CA_SEMI_OPEN               = 0

 3782 23:06:56.031760  CA_FULL_RATE               = 0

 3783 23:06:56.035605  DQ_CKDIV4_EN               = 1

 3784 23:06:56.038229  CA_CKDIV4_EN               = 1

 3785 23:06:56.041839  CA_PREDIV_EN               = 0

 3786 23:06:56.045563  PH8_DLY                    = 0

 3787 23:06:56.045652  SEMI_OPEN_CA_PICK_MCK_RATIO= 0

 3788 23:06:56.049118  DQ_AAMCK_DIV               = 4

 3789 23:06:56.052116  CA_AAMCK_DIV               = 4

 3790 23:06:56.055582  CA_ADMCK_DIV               = 4

 3791 23:06:56.058183  DQ_TRACK_CA_EN             = 0

 3792 23:06:56.061761  CA_PICK                    = 600

 3793 23:06:56.061880  CA_MCKIO                   = 600

 3794 23:06:56.065282  MCKIO_SEMI                 = 0

 3795 23:06:56.068756  PLL_FREQ                   = 2288

 3796 23:06:56.071916  DQ_UI_PI_RATIO             = 32

 3797 23:06:56.074851  CA_UI_PI_RATIO             = 0

 3798 23:06:56.078321  =================================== 

 3799 23:06:56.081648  =================================== 

 3800 23:06:56.085034  memory_type:LPDDR4         

 3801 23:06:56.085151  GP_NUM     : 10       

 3802 23:06:56.088952  SRAM_EN    : 1       

 3803 23:06:56.089061  MD32_EN    : 0       

 3804 23:06:56.091597  =================================== 

 3805 23:06:56.095590  [ANA_INIT] >>>>>>>>>>>>>> 

 3806 23:06:56.098806  <<<<<< [CONFIGURE PHASE]: ANA_TX

 3807 23:06:56.102052  >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL

 3808 23:06:56.105552  =================================== 

 3809 23:06:56.108474  data_rate = 1200,PCW = 0X5800

 3810 23:06:56.112443  =================================== 

 3811 23:06:56.115427  <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL

 3812 23:06:56.118972  >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 3813 23:06:56.125412  <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 3814 23:06:56.128719  >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2

 3815 23:06:56.135475  >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL

 3816 23:06:56.138588  <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL

 3817 23:06:56.138714  [ANA_INIT] flow start 

 3818 23:06:56.142015  [ANA_INIT] PLL >>>>>>>> 

 3819 23:06:56.145193  [ANA_INIT] PLL <<<<<<<< 

 3820 23:06:56.145286  [ANA_INIT] MIDPI >>>>>>>> 

 3821 23:06:56.148763  [ANA_INIT] MIDPI <<<<<<<< 

 3822 23:06:56.152399  [ANA_INIT] DLL >>>>>>>> 

 3823 23:06:56.152495  [ANA_INIT] flow end 

 3824 23:06:56.155450  ============ LP4 DIFF to SE enter ============

 3825 23:06:56.161768  ============ LP4 DIFF to SE exit  ============

 3826 23:06:56.161889  [ANA_INIT] <<<<<<<<<<<<< 

 3827 23:06:56.164988  [Flow] Enable top DCM control >>>>> 

 3828 23:06:56.169025  [Flow] Enable top DCM control <<<<< 

 3829 23:06:56.172374  Enable DLL master slave shuffle 

 3830 23:06:56.179296  ============================================================== 

 3831 23:06:56.179419  Gating Mode config

 3832 23:06:56.185664  ============================================================== 

 3833 23:06:56.189013  Config description: 

 3834 23:06:56.198648  RX_GATING_MODE        0: Pulse Mode      1: Burst Mode(8UI)        2: Burst Mode(7UI)  3: Original Burst Mode

 3835 23:06:56.202225  RX_GATING_TRACK_MODE  0: Valid DLY Mode  1: Valid Mode (-like) 2: FIFO mode

 3836 23:06:56.208919  SELPH_MODE            0: By rank         1: By Phase 

 3837 23:06:56.215484  ============================================================== 

 3838 23:06:56.215610  GAT_TRACK_EN                 =  1

 3839 23:06:56.218712  RX_GATING_MODE               =  2

 3840 23:06:56.222002  RX_GATING_TRACK_MODE         =  2

 3841 23:06:56.226005  SELPH_MODE                   =  1

 3842 23:06:56.228716  PICG_EARLY_EN                =  1

 3843 23:06:56.232134  VALID_LAT_VALUE              =  1

 3844 23:06:56.238609  ============================================================== 

 3845 23:06:56.241775  Enter into Gating configuration >>>> 

 3846 23:06:56.245377  Exit from Gating configuration <<<< 

 3847 23:06:56.248872  Enter into  DVFS_PRE_config >>>>> 

 3848 23:06:56.258647  Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. 

 3849 23:06:56.261923  Exit from  DVFS_PRE_config <<<<< 

 3850 23:06:56.265542  Enter into PICG configuration >>>> 

 3851 23:06:56.268387  Exit from PICG configuration <<<< 

 3852 23:06:56.271818  [RX_INPUT] configuration >>>>> 

 3853 23:06:56.271926  [RX_INPUT] configuration <<<<< 

 3854 23:06:56.279109  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>

 3855 23:06:56.285107  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<

 3856 23:06:56.288683  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>

 3857 23:06:56.295218  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<

 3858 23:06:56.301962  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>

 3859 23:06:56.308658  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<

 3860 23:06:56.312841  [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 

 3861 23:06:56.315761  [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 

 3862 23:06:56.322540  [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 

 3863 23:06:56.324906  [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 

 3864 23:06:56.328626  [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 

 3865 23:06:56.335743  [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2

 3866 23:06:56.335882  =================================== 

 3867 23:06:56.338302  LPDDR4 DRAM CONFIGURATION

 3868 23:06:56.341901  =================================== 

 3869 23:06:56.345653  EX_ROW_EN[0]    = 0x0

 3870 23:06:56.345767  EX_ROW_EN[1]    = 0x0

 3871 23:06:56.348892  LP4Y_EN      = 0x0

 3872 23:06:56.348990  WORK_FSP     = 0x0

 3873 23:06:56.351906  WL           = 0x2

 3874 23:06:56.352001  RL           = 0x2

 3875 23:06:56.355899  BL           = 0x2

 3876 23:06:56.356003  RPST         = 0x0

 3877 23:06:56.358611  RD_PRE       = 0x0

 3878 23:06:56.358719  WR_PRE       = 0x1

 3879 23:06:56.362800  WR_PST       = 0x0

 3880 23:06:56.365051  DBI_WR       = 0x0

 3881 23:06:56.365157  DBI_RD       = 0x0

 3882 23:06:56.368860  OTF          = 0x1

 3883 23:06:56.372325  =================================== 

 3884 23:06:56.375377  [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 

 3885 23:06:56.378444  [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 

 3886 23:06:56.382201  [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2

 3887 23:06:56.385251  =================================== 

 3888 23:06:56.388891  LPDDR4 DRAM CONFIGURATION

 3889 23:06:56.392532  =================================== 

 3890 23:06:56.395338  EX_ROW_EN[0]    = 0x10

 3891 23:06:56.395445  EX_ROW_EN[1]    = 0x0

 3892 23:06:56.398719  LP4Y_EN      = 0x0

 3893 23:06:56.398844  WORK_FSP     = 0x0

 3894 23:06:56.401739  WL           = 0x2

 3895 23:06:56.401833  RL           = 0x2

 3896 23:06:56.406240  BL           = 0x2

 3897 23:06:56.406350  RPST         = 0x0

 3898 23:06:56.408385  RD_PRE       = 0x0

 3899 23:06:56.408477  WR_PRE       = 0x1

 3900 23:06:56.412823  WR_PST       = 0x0

 3901 23:06:56.412932  DBI_WR       = 0x0

 3902 23:06:56.415420  DBI_RD       = 0x0

 3903 23:06:56.415514  OTF          = 0x1

 3904 23:06:56.418868  =================================== 

 3905 23:06:56.425440  [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit

 3906 23:06:56.430139  nWR fixed to 30

 3907 23:06:56.433867  [ModeRegInit_LP4] CH0 RK0

 3908 23:06:56.433986  [ModeRegInit_LP4] CH0 RK1

 3909 23:06:56.436765  [ModeRegInit_LP4] CH1 RK0

 3910 23:06:56.439885  [ModeRegInit_LP4] CH1 RK1

 3911 23:06:56.439988  match AC timing 17

 3912 23:06:56.447022  dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1

 3913 23:06:56.450310  SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON

 3914 23:06:56.453972  [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8

 3915 23:06:56.460224  [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17

 3916 23:06:56.463535  [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)

 3917 23:06:56.463667  ==

 3918 23:06:56.467331  Dram Type= 6, Freq= 0, CH_0, rank 0

 3919 23:06:56.470338  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3920 23:06:56.470492  ==

 3921 23:06:56.477106  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 3922 23:06:56.483881  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35

 3923 23:06:56.487886  [CA 0] Center 36 (6~66) winsize 61

 3924 23:06:56.490361  [CA 1] Center 36 (6~66) winsize 61

 3925 23:06:56.493775  [CA 2] Center 34 (4~65) winsize 62

 3926 23:06:56.496938  [CA 3] Center 34 (4~64) winsize 61

 3927 23:06:56.500563  [CA 4] Center 33 (3~64) winsize 62

 3928 23:06:56.503521  [CA 5] Center 33 (3~64) winsize 62

 3929 23:06:56.503639  

 3930 23:06:56.506999  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 3931 23:06:56.507106  

 3932 23:06:56.510258  [CATrainingPosCal] consider 1 rank data

 3933 23:06:56.513539  u2DelayCellTimex100 = 270/100 ps

 3934 23:06:56.517967  CA0 delay=36 (6~66),Diff = 3 PI (28 cell)

 3935 23:06:56.520794  CA1 delay=36 (6~66),Diff = 3 PI (28 cell)

 3936 23:06:56.523525  CA2 delay=34 (4~65),Diff = 1 PI (9 cell)

 3937 23:06:56.527007  CA3 delay=34 (4~64),Diff = 1 PI (9 cell)

 3938 23:06:56.530437  CA4 delay=33 (3~64),Diff = 0 PI (0 cell)

 3939 23:06:56.533438  CA5 delay=33 (3~64),Diff = 0 PI (0 cell)

 3940 23:06:56.533550  

 3941 23:06:56.537017  CA PerBit enable=1, Macro0, CA PI delay=33

 3942 23:06:56.540950  

 3943 23:06:56.541104  [CBTSetCACLKResult] CA Dly = 33

 3944 23:06:56.544223  CS Dly: 5 (0~36)

 3945 23:06:56.544408  ==

 3946 23:06:56.546704  Dram Type= 6, Freq= 0, CH_0, rank 1

 3947 23:06:56.550788  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3948 23:06:56.550967  ==

 3949 23:06:56.557296  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 3950 23:06:56.563818  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35

 3951 23:06:56.566787  [CA 0] Center 36 (6~66) winsize 61

 3952 23:06:56.571004  [CA 1] Center 36 (6~66) winsize 61

 3953 23:06:56.573479  [CA 2] Center 34 (4~65) winsize 62

 3954 23:06:56.577143  [CA 3] Center 34 (4~64) winsize 61

 3955 23:06:56.580431  [CA 4] Center 33 (3~64) winsize 62

 3956 23:06:56.583360  [CA 5] Center 33 (3~64) winsize 62

 3957 23:06:56.583457  

 3958 23:06:56.586816  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 3959 23:06:56.586908  

 3960 23:06:56.590422  [CATrainingPosCal] consider 2 rank data

 3961 23:06:56.593870  u2DelayCellTimex100 = 270/100 ps

 3962 23:06:56.597438  CA0 delay=36 (6~66),Diff = 3 PI (28 cell)

 3963 23:06:56.600131  CA1 delay=36 (6~66),Diff = 3 PI (28 cell)

 3964 23:06:56.604200  CA2 delay=34 (4~65),Diff = 1 PI (9 cell)

 3965 23:06:56.607099  CA3 delay=34 (4~64),Diff = 1 PI (9 cell)

 3966 23:06:56.610517  CA4 delay=33 (3~64),Diff = 0 PI (0 cell)

 3967 23:06:56.614267  CA5 delay=33 (3~64),Diff = 0 PI (0 cell)

 3968 23:06:56.614371  

 3969 23:06:56.617900  CA PerBit enable=1, Macro0, CA PI delay=33

 3970 23:06:56.620676  

 3971 23:06:56.620770  [CBTSetCACLKResult] CA Dly = 33

 3972 23:06:56.623867  CS Dly: 5 (0~36)

 3973 23:06:56.623959  

 3974 23:06:56.627235  ----->DramcWriteLeveling(PI) begin...

 3975 23:06:56.627326  ==

 3976 23:06:56.630295  Dram Type= 6, Freq= 0, CH_0, rank 0

 3977 23:06:56.634298  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3978 23:06:56.634422  ==

 3979 23:06:56.637862  Write leveling (Byte 0): 34 => 34

 3980 23:06:56.640438  Write leveling (Byte 1): 31 => 31

 3981 23:06:56.643670  DramcWriteLeveling(PI) end<-----

 3982 23:06:56.643765  

 3983 23:06:56.643832  ==

 3984 23:06:56.647144  Dram Type= 6, Freq= 0, CH_0, rank 0

 3985 23:06:56.650640  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3986 23:06:56.650732  ==

 3987 23:06:56.653754  [Gating] SW mode calibration

 3988 23:06:56.660914  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0

 3989 23:06:56.667329  RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)

 3990 23:06:56.670583   0  9  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3991 23:06:56.673728   0  9  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3992 23:06:56.680938   0  9  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3993 23:06:56.684059   0  9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3994 23:06:56.687739   0  9 16 | B1->B0 | 3030 2929 | 0 0 | (0 1) (0 0)

 3995 23:06:56.693658   0  9 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)

 3996 23:06:56.697260   0  9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3997 23:06:56.700537   0  9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3998 23:06:56.707097   0 10  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3999 23:06:56.710853   0 10  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4000 23:06:56.714707   0 10  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4001 23:06:56.721500   0 10 12 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)

 4002 23:06:56.724644   0 10 16 | B1->B0 | 2b2b 3838 | 0 0 | (1 1) (1 1)

 4003 23:06:56.727577   0 10 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)

 4004 23:06:56.734112   0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4005 23:06:56.737271   0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4006 23:06:56.740479   0 11  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4007 23:06:56.747500   0 11  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4008 23:06:56.750689   0 11  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4009 23:06:56.753887   0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4010 23:06:56.757714   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 4011 23:06:56.764498   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4012 23:06:56.767033   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4013 23:06:56.770629   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4014 23:06:56.777530   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4015 23:06:56.780637   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4016 23:06:56.784431   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4017 23:06:56.790822   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4018 23:06:56.793869   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4019 23:06:56.797134   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4020 23:06:56.804418   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4021 23:06:56.808125   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4022 23:06:56.811064   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4023 23:06:56.818275   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4024 23:06:56.820724   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4025 23:06:56.824332   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4026 23:06:56.831504   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4027 23:06:56.831655  Total UI for P1: 0, mck2ui 16

 4028 23:06:56.834380  best dqsien dly found for B0: ( 0, 13, 14)

 4029 23:06:56.837978  Total UI for P1: 0, mck2ui 16

 4030 23:06:56.842105  best dqsien dly found for B1: ( 0, 13, 14)

 4031 23:06:56.844927  best DQS0 dly(MCK, UI, PI) = (0, 13, 14)

 4032 23:06:56.852153  best DQS1 dly(MCK, UI, PI) = (0, 13, 14)

 4033 23:06:56.852284  

 4034 23:06:56.854619  best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)

 4035 23:06:56.857782  best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)

 4036 23:06:56.861080  [Gating] SW calibration Done

 4037 23:06:56.861181  ==

 4038 23:06:56.864935  Dram Type= 6, Freq= 0, CH_0, rank 0

 4039 23:06:56.868319  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4040 23:06:56.868430  ==

 4041 23:06:56.868501  RX Vref Scan: 0

 4042 23:06:56.868562  

 4043 23:06:56.871467  RX Vref 0 -> 0, step: 1

 4044 23:06:56.871555  

 4045 23:06:56.874560  RX Delay -230 -> 252, step: 16

 4046 23:06:56.877642  iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320

 4047 23:06:56.881436  iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320

 4048 23:06:56.888219  iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336

 4049 23:06:56.891197  iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320

 4050 23:06:56.894775  iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320

 4051 23:06:56.897708  iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336

 4052 23:06:56.904290  iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336

 4053 23:06:56.907743  iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336

 4054 23:06:56.911143  iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320

 4055 23:06:56.915018  iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336

 4056 23:06:56.921994  iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336

 4057 23:06:56.924091  iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320

 4058 23:06:56.927526  iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336

 4059 23:06:56.931140  iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336

 4060 23:06:56.934562  iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336

 4061 23:06:56.941407  iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320

 4062 23:06:56.941565  ==

 4063 23:06:56.945094  Dram Type= 6, Freq= 0, CH_0, rank 0

 4064 23:06:56.947484  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4065 23:06:56.947572  ==

 4066 23:06:56.947637  DQS Delay:

 4067 23:06:56.951396  DQS0 = 0, DQS1 = 0

 4068 23:06:56.951484  DQM Delay:

 4069 23:06:56.954858  DQM0 = 41, DQM1 = 32

 4070 23:06:56.954949  DQ Delay:

 4071 23:06:56.957930  DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =41

 4072 23:06:56.961329  DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49

 4073 23:06:56.964529  DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25

 4074 23:06:56.967451  DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =41

 4075 23:06:56.967569  

 4076 23:06:56.967635  

 4077 23:06:56.967696  ==

 4078 23:06:56.970675  Dram Type= 6, Freq= 0, CH_0, rank 0

 4079 23:06:56.974476  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4080 23:06:56.978133  ==

 4081 23:06:56.978261  

 4082 23:06:56.978363  

 4083 23:06:56.978463  	TX Vref Scan disable

 4084 23:06:56.980762   == TX Byte 0 ==

 4085 23:06:56.984345  Update DQ  dly =580 (2 ,1, 36)  DQ  OEN =(1 ,6)

 4086 23:06:56.987639  Update DQM dly =580 (2 ,1, 36)  DQM OEN =(1 ,6)

 4087 23:06:56.991185   == TX Byte 1 ==

 4088 23:06:56.994264  Update DQ  dly =576 (2 ,1, 32)  DQ  OEN =(1 ,6)

 4089 23:06:56.997637  Update DQM dly =576 (2 ,1, 32)  DQM OEN =(1 ,6)

 4090 23:06:57.000571  ==

 4091 23:06:57.000671  Dram Type= 6, Freq= 0, CH_0, rank 0

 4092 23:06:57.007308  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4093 23:06:57.007422  ==

 4094 23:06:57.007508  

 4095 23:06:57.007622  

 4096 23:06:57.011493  	TX Vref Scan disable

 4097 23:06:57.011605   == TX Byte 0 ==

 4098 23:06:57.017791  Update DQ  dly =580 (2 ,1, 36)  DQ  OEN =(1 ,6)

 4099 23:06:57.020820  Update DQM dly =580 (2 ,1, 36)  DQM OEN =(1 ,6)

 4100 23:06:57.020911   == TX Byte 1 ==

 4101 23:06:57.027886  Update DQ  dly =576 (2 ,1, 32)  DQ  OEN =(1 ,6)

 4102 23:06:57.031246  Update DQM dly =576 (2 ,1, 32)  DQM OEN =(1 ,6)

 4103 23:06:57.031350  

 4104 23:06:57.031417  [DATLAT]

 4105 23:06:57.034509  Freq=600, CH0 RK0

 4106 23:06:57.034599  

 4107 23:06:57.034664  DATLAT Default: 0x9

 4108 23:06:57.037686  0, 0xFFFF, sum = 0

 4109 23:06:57.037776  1, 0xFFFF, sum = 0

 4110 23:06:57.041227  2, 0xFFFF, sum = 0

 4111 23:06:57.041318  3, 0xFFFF, sum = 0

 4112 23:06:57.044655  4, 0xFFFF, sum = 0

 4113 23:06:57.044745  5, 0xFFFF, sum = 0

 4114 23:06:57.047738  6, 0xFFFF, sum = 0

 4115 23:06:57.047828  7, 0xFFFF, sum = 0

 4116 23:06:57.051361  8, 0x0, sum = 1

 4117 23:06:57.051454  9, 0x0, sum = 2

 4118 23:06:57.054501  10, 0x0, sum = 3

 4119 23:06:57.054590  11, 0x0, sum = 4

 4120 23:06:57.058387  best_step = 9

 4121 23:06:57.058518  

 4122 23:06:57.058585  ==

 4123 23:06:57.061153  Dram Type= 6, Freq= 0, CH_0, rank 0

 4124 23:06:57.064960  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4125 23:06:57.065053  ==

 4126 23:06:57.065120  RX Vref Scan: 1

 4127 23:06:57.067733  

 4128 23:06:57.067819  RX Vref 0 -> 0, step: 1

 4129 23:06:57.067884  

 4130 23:06:57.071345  RX Delay -195 -> 252, step: 8

 4131 23:06:57.071433  

 4132 23:06:57.074585  Set Vref, RX VrefLevel [Byte0]: 53

 4133 23:06:57.077922                           [Byte1]: 52

 4134 23:06:57.080908  

 4135 23:06:57.080996  Final RX Vref Byte 0 = 53 to rank0

 4136 23:06:57.084525  Final RX Vref Byte 1 = 52 to rank0

 4137 23:06:57.087638  Final RX Vref Byte 0 = 53 to rank1

 4138 23:06:57.091138  Final RX Vref Byte 1 = 52 to rank1==

 4139 23:06:57.094259  Dram Type= 6, Freq= 0, CH_0, rank 0

 4140 23:06:57.101463  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4141 23:06:57.101612  ==

 4142 23:06:57.101682  DQS Delay:

 4143 23:06:57.101774  DQS0 = 0, DQS1 = 0

 4144 23:06:57.104355  DQM Delay:

 4145 23:06:57.104498  DQM0 = 42, DQM1 = 33

 4146 23:06:57.107980  DQ Delay:

 4147 23:06:57.111235  DQ0 =44, DQ1 =44, DQ2 =36, DQ3 =40

 4148 23:06:57.111331  DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =52

 4149 23:06:57.114723  DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =28

 4150 23:06:57.118759  DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =44

 4151 23:06:57.121370  

 4152 23:06:57.121480  

 4153 23:06:57.127699  [DQSOSCAuto] RK0, (LSB)MR18= 0x4322, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 397 ps

 4154 23:06:57.130982  CH0 RK0: MR19=808, MR18=4322

 4155 23:06:57.138335  CH0_RK0: MR19=0x808, MR18=0x4322, DQSOSC=397, MR23=63, INC=166, DEC=110

 4156 23:06:57.138528  

 4157 23:06:57.141180  ----->DramcWriteLeveling(PI) begin...

 4158 23:06:57.141331  ==

 4159 23:06:57.145069  Dram Type= 6, Freq= 0, CH_0, rank 1

 4160 23:06:57.148410  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4161 23:06:57.148507  ==

 4162 23:06:57.151227  Write leveling (Byte 0): 30 => 30

 4163 23:06:57.154389  Write leveling (Byte 1): 30 => 30

 4164 23:06:57.158300  DramcWriteLeveling(PI) end<-----

 4165 23:06:57.158466  

 4166 23:06:57.158536  ==

 4167 23:06:57.162261  Dram Type= 6, Freq= 0, CH_0, rank 1

 4168 23:06:57.164983  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4169 23:06:57.165079  ==

 4170 23:06:57.167907  [Gating] SW mode calibration

 4171 23:06:57.174949  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0

 4172 23:06:57.181666  RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)

 4173 23:06:57.184886   0  9  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4174 23:06:57.188091   0  9  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4175 23:06:57.194874   0  9  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)

 4176 23:06:57.197972   0  9 12 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (1 0)

 4177 23:06:57.201552   0  9 16 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)

 4178 23:06:57.208354   0  9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4179 23:06:57.212484   0  9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4180 23:06:57.215360   0  9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4181 23:06:57.221258   0 10  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4182 23:06:57.225138   0 10  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4183 23:06:57.228083   0 10  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4184 23:06:57.234648   0 10 12 | B1->B0 | 2323 3939 | 0 0 | (0 0) (0 0)

 4185 23:06:57.237975   0 10 16 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)

 4186 23:06:57.241198   0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4187 23:06:57.245352   0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4188 23:06:57.251715   0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4189 23:06:57.255169   0 11  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4190 23:06:57.258146   0 11  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4191 23:06:57.265233   0 11  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4192 23:06:57.268771   0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 4193 23:06:57.271511   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)

 4194 23:06:57.278032   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4195 23:06:57.281351   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4196 23:06:57.285135   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4197 23:06:57.291629   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4198 23:06:57.294549   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4199 23:06:57.298276   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4200 23:06:57.304852   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4201 23:06:57.308775   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4202 23:06:57.311647   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4203 23:06:57.318164   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4204 23:06:57.321810   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4205 23:06:57.325238   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4206 23:06:57.328528   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4207 23:06:57.335033   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4208 23:06:57.339301   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 4209 23:06:57.341557   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4210 23:06:57.345474  Total UI for P1: 0, mck2ui 16

 4211 23:06:57.348613  best dqsien dly found for B0: ( 0, 13, 12)

 4212 23:06:57.352024  Total UI for P1: 0, mck2ui 16

 4213 23:06:57.355554  best dqsien dly found for B1: ( 0, 13, 14)

 4214 23:06:57.358789  best DQS0 dly(MCK, UI, PI) = (0, 13, 12)

 4215 23:06:57.361898  best DQS1 dly(MCK, UI, PI) = (0, 13, 14)

 4216 23:06:57.362003  

 4217 23:06:57.368508  best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)

 4218 23:06:57.372164  best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)

 4219 23:06:57.372280  [Gating] SW calibration Done

 4220 23:06:57.374894  ==

 4221 23:06:57.378678  Dram Type= 6, Freq= 0, CH_0, rank 1

 4222 23:06:57.381784  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4223 23:06:57.381887  ==

 4224 23:06:57.381975  RX Vref Scan: 0

 4225 23:06:57.382058  

 4226 23:06:57.385132  RX Vref 0 -> 0, step: 1

 4227 23:06:57.385221  

 4228 23:06:57.388584  RX Delay -230 -> 252, step: 16

 4229 23:06:57.392648  iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320

 4230 23:06:57.395895  iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320

 4231 23:06:57.402096  iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320

 4232 23:06:57.405453  iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320

 4233 23:06:57.408353  iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320

 4234 23:06:57.411970  iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320

 4235 23:06:57.415350  iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336

 4236 23:06:57.421899  iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336

 4237 23:06:57.425076  iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320

 4238 23:06:57.429164  iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336

 4239 23:06:57.432469  iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336

 4240 23:06:57.438565  iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320

 4241 23:06:57.442754  iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336

 4242 23:06:57.445547  iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336

 4243 23:06:57.448720  iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336

 4244 23:06:57.455261  iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320

 4245 23:06:57.455392  ==

 4246 23:06:57.458974  Dram Type= 6, Freq= 0, CH_0, rank 1

 4247 23:06:57.462221  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4248 23:06:57.462379  ==

 4249 23:06:57.462509  DQS Delay:

 4250 23:06:57.465184  DQS0 = 0, DQS1 = 0

 4251 23:06:57.465287  DQM Delay:

 4252 23:06:57.468629  DQM0 = 41, DQM1 = 32

 4253 23:06:57.468729  DQ Delay:

 4254 23:06:57.471721  DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41

 4255 23:06:57.475248  DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49

 4256 23:06:57.478802  DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25

 4257 23:06:57.482354  DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =41

 4258 23:06:57.482485  

 4259 23:06:57.482553  

 4260 23:06:57.482625  ==

 4261 23:06:57.485125  Dram Type= 6, Freq= 0, CH_0, rank 1

 4262 23:06:57.488508  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4263 23:06:57.488632  ==

 4264 23:06:57.488724  

 4265 23:06:57.488818  

 4266 23:06:57.491882  	TX Vref Scan disable

 4267 23:06:57.495470   == TX Byte 0 ==

 4268 23:06:57.498781  Update DQ  dly =576 (2 ,1, 32)  DQ  OEN =(1 ,6)

 4269 23:06:57.501934  Update DQM dly =576 (2 ,1, 32)  DQM OEN =(1 ,6)

 4270 23:06:57.505228   == TX Byte 1 ==

 4271 23:06:57.508478  Update DQ  dly =575 (2 ,1, 31)  DQ  OEN =(1 ,6)

 4272 23:06:57.511660  Update DQM dly =575 (2 ,1, 31)  DQM OEN =(1 ,6)

 4273 23:06:57.511763  ==

 4274 23:06:57.515103  Dram Type= 6, Freq= 0, CH_0, rank 1

 4275 23:06:57.521938  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4276 23:06:57.522095  ==

 4277 23:06:57.522194  

 4278 23:06:57.522283  

 4279 23:06:57.522379  	TX Vref Scan disable

 4280 23:06:57.525671   == TX Byte 0 ==

 4281 23:06:57.528900  Update DQ  dly =576 (2 ,1, 32)  DQ  OEN =(1 ,6)

 4282 23:06:57.536180  Update DQM dly =576 (2 ,1, 32)  DQM OEN =(1 ,6)

 4283 23:06:57.536320   == TX Byte 1 ==

 4284 23:06:57.539405  Update DQ  dly =575 (2 ,1, 31)  DQ  OEN =(1 ,6)

 4285 23:06:57.542555  Update DQM dly =575 (2 ,1, 31)  DQM OEN =(1 ,6)

 4286 23:06:57.546177  

 4287 23:06:57.546318  [DATLAT]

 4288 23:06:57.546445  Freq=600, CH0 RK1

 4289 23:06:57.546535  

 4290 23:06:57.549294  DATLAT Default: 0x9

 4291 23:06:57.549406  0, 0xFFFF, sum = 0

 4292 23:06:57.552769  1, 0xFFFF, sum = 0

 4293 23:06:57.552889  2, 0xFFFF, sum = 0

 4294 23:06:57.556433  3, 0xFFFF, sum = 0

 4295 23:06:57.556548  4, 0xFFFF, sum = 0

 4296 23:06:57.559530  5, 0xFFFF, sum = 0

 4297 23:06:57.559626  6, 0xFFFF, sum = 0

 4298 23:06:57.562712  7, 0xFFFF, sum = 0

 4299 23:06:57.562826  8, 0x0, sum = 1

 4300 23:06:57.565697  9, 0x0, sum = 2

 4301 23:06:57.565802  10, 0x0, sum = 3

 4302 23:06:57.569239  11, 0x0, sum = 4

 4303 23:06:57.569368  best_step = 9

 4304 23:06:57.569460  

 4305 23:06:57.569548  ==

 4306 23:06:57.572277  Dram Type= 6, Freq= 0, CH_0, rank 1

 4307 23:06:57.579497  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4308 23:06:57.579607  ==

 4309 23:06:57.579674  RX Vref Scan: 0

 4310 23:06:57.579734  

 4311 23:06:57.582821  RX Vref 0 -> 0, step: 1

 4312 23:06:57.582905  

 4313 23:06:57.586120  RX Delay -195 -> 252, step: 8

 4314 23:06:57.589493  iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312

 4315 23:06:57.592856  iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312

 4316 23:06:57.599389  iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304

 4317 23:06:57.603224  iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312

 4318 23:06:57.606077  iDelay=205, Bit 4, Center 40 (-107 ~ 188) 296

 4319 23:06:57.609449  iDelay=205, Bit 5, Center 28 (-123 ~ 180) 304

 4320 23:06:57.613147  iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312

 4321 23:06:57.620260  iDelay=205, Bit 7, Center 44 (-107 ~ 196) 304

 4322 23:06:57.623351  iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312

 4323 23:06:57.626227  iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312

 4324 23:06:57.629855  iDelay=205, Bit 10, Center 36 (-115 ~ 188) 304

 4325 23:06:57.637123  iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304

 4326 23:06:57.640059  iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320

 4327 23:06:57.643265  iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312

 4328 23:06:57.646737  iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312

 4329 23:06:57.650131  iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312

 4330 23:06:57.653354  ==

 4331 23:06:57.657011  Dram Type= 6, Freq= 0, CH_0, rank 1

 4332 23:06:57.660391  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4333 23:06:57.660479  ==

 4334 23:06:57.660545  DQS Delay:

 4335 23:06:57.663849  DQS0 = 0, DQS1 = 0

 4336 23:06:57.663932  DQM Delay:

 4337 23:06:57.666826  DQM0 = 39, DQM1 = 33

 4338 23:06:57.666908  DQ Delay:

 4339 23:06:57.670102  DQ0 =40, DQ1 =40, DQ2 =36, DQ3 =40

 4340 23:06:57.673056  DQ4 =40, DQ5 =28, DQ6 =48, DQ7 =44

 4341 23:06:57.676671  DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =28

 4342 23:06:57.680026  DQ12 =36, DQ13 =40, DQ14 =40, DQ15 =40

 4343 23:06:57.680139  

 4344 23:06:57.680231  

 4345 23:06:57.686960  [DQSOSCAuto] RK1, (LSB)MR18= 0x5033, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 394 ps

 4346 23:06:57.690376  CH0 RK1: MR19=808, MR18=5033

 4347 23:06:57.696882  CH0_RK1: MR19=0x808, MR18=0x5033, DQSOSC=394, MR23=63, INC=168, DEC=112

 4348 23:06:57.700355  [RxdqsGatingPostProcess] freq 600

 4349 23:06:57.703715  ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1

 4350 23:06:57.707318  Pre-setting of DQS Precalculation

 4351 23:06:57.713754  [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9

 4352 23:06:57.713856  ==

 4353 23:06:57.716657  Dram Type= 6, Freq= 0, CH_1, rank 0

 4354 23:06:57.720236  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4355 23:06:57.720323  ==

 4356 23:06:57.727286  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 4357 23:06:57.734146  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35

 4358 23:06:57.736761  [CA 0] Center 35 (5~65) winsize 61

 4359 23:06:57.739810  [CA 1] Center 35 (5~66) winsize 62

 4360 23:06:57.743464  [CA 2] Center 33 (3~64) winsize 62

 4361 23:06:57.746590  [CA 3] Center 33 (3~64) winsize 62

 4362 23:06:57.750150  [CA 4] Center 34 (3~65) winsize 63

 4363 23:06:57.753819  [CA 5] Center 33 (3~64) winsize 62

 4364 23:06:57.753906  

 4365 23:06:57.757328  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 4366 23:06:57.757412  

 4367 23:06:57.760702  [CATrainingPosCal] consider 1 rank data

 4368 23:06:57.763323  u2DelayCellTimex100 = 270/100 ps

 4369 23:06:57.766718  CA0 delay=35 (5~65),Diff = 2 PI (19 cell)

 4370 23:06:57.770114  CA1 delay=35 (5~66),Diff = 2 PI (19 cell)

 4371 23:06:57.773374  CA2 delay=33 (3~64),Diff = 0 PI (0 cell)

 4372 23:06:57.776531  CA3 delay=33 (3~64),Diff = 0 PI (0 cell)

 4373 23:06:57.779795  CA4 delay=34 (3~65),Diff = 1 PI (9 cell)

 4374 23:06:57.783445  CA5 delay=33 (3~64),Diff = 0 PI (0 cell)

 4375 23:06:57.783530  

 4376 23:06:57.786762  CA PerBit enable=1, Macro0, CA PI delay=33

 4377 23:06:57.786848  

 4378 23:06:57.790376  [CBTSetCACLKResult] CA Dly = 33

 4379 23:06:57.793405  CS Dly: 5 (0~36)

 4380 23:06:57.793490  ==

 4381 23:06:57.796809  Dram Type= 6, Freq= 0, CH_1, rank 1

 4382 23:06:57.800082  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4383 23:06:57.800170  ==

 4384 23:06:57.806992  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 4385 23:06:57.813594  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35

 4386 23:06:57.816489  [CA 0] Center 35 (5~66) winsize 62

 4387 23:06:57.820597  [CA 1] Center 36 (6~66) winsize 61

 4388 23:06:57.823213  [CA 2] Center 34 (4~65) winsize 62

 4389 23:06:57.827247  [CA 3] Center 34 (3~65) winsize 63

 4390 23:06:57.831576  [CA 4] Center 34 (4~65) winsize 62

 4391 23:06:57.833752  [CA 5] Center 33 (3~64) winsize 62

 4392 23:06:57.833862  

 4393 23:06:57.836576  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 4394 23:06:57.836662  

 4395 23:06:57.839735  [CATrainingPosCal] consider 2 rank data

 4396 23:06:57.843477  u2DelayCellTimex100 = 270/100 ps

 4397 23:06:57.846692  CA0 delay=35 (5~65),Diff = 2 PI (19 cell)

 4398 23:06:57.850216  CA1 delay=36 (6~66),Diff = 3 PI (28 cell)

 4399 23:06:57.853532  CA2 delay=34 (4~64),Diff = 1 PI (9 cell)

 4400 23:06:57.856785  CA3 delay=33 (3~64),Diff = 0 PI (0 cell)

 4401 23:06:57.860591  CA4 delay=34 (4~65),Diff = 1 PI (9 cell)

 4402 23:06:57.863218  CA5 delay=33 (3~64),Diff = 0 PI (0 cell)

 4403 23:06:57.863305  

 4404 23:06:57.866960  CA PerBit enable=1, Macro0, CA PI delay=33

 4405 23:06:57.869869  

 4406 23:06:57.869959  [CBTSetCACLKResult] CA Dly = 33

 4407 23:06:57.873368  CS Dly: 4 (0~35)

 4408 23:06:57.873456  

 4409 23:06:57.877035  ----->DramcWriteLeveling(PI) begin...

 4410 23:06:57.877125  ==

 4411 23:06:57.880075  Dram Type= 6, Freq= 0, CH_1, rank 0

 4412 23:06:57.884091  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4413 23:06:57.884180  ==

 4414 23:06:57.886420  Write leveling (Byte 0): 28 => 28

 4415 23:06:57.890233  Write leveling (Byte 1): 31 => 31

 4416 23:06:57.893132  DramcWriteLeveling(PI) end<-----

 4417 23:06:57.893240  

 4418 23:06:57.893307  ==

 4419 23:06:57.896633  Dram Type= 6, Freq= 0, CH_1, rank 0

 4420 23:06:57.899716  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4421 23:06:57.899807  ==

 4422 23:06:57.903168  [Gating] SW mode calibration

 4423 23:06:57.909900  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0

 4424 23:06:57.916568  RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)

 4425 23:06:57.920007   0  9  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4426 23:06:57.927461   0  9  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4427 23:06:57.929850   0  9  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4428 23:06:57.933323   0  9 12 | B1->B0 | 3434 3333 | 0 1 | (0 0) (1 1)

 4429 23:06:57.936631   0  9 16 | B1->B0 | 2c2c 2727 | 0 0 | (0 0) (1 0)

 4430 23:06:57.943781   0  9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4431 23:06:57.947594   0  9 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)

 4432 23:06:57.950492   0  9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4433 23:06:57.957333   0 10  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4434 23:06:57.960587   0 10  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4435 23:06:57.963845   0 10  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4436 23:06:57.970737   0 10 12 | B1->B0 | 2626 2929 | 1 0 | (0 0) (0 0)

 4437 23:06:57.973780   0 10 16 | B1->B0 | 3838 3f3f | 0 0 | (0 0) (0 0)

 4438 23:06:57.976653   0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4439 23:06:57.983844   0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4440 23:06:57.987349   0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4441 23:06:57.990112   0 11  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4442 23:06:57.996937   0 11  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4443 23:06:58.000627   0 11  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4444 23:06:58.003476   0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 4445 23:06:58.009979   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4446 23:06:58.013412   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4447 23:06:58.017448   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4448 23:06:58.020571   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4449 23:06:58.027097   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4450 23:06:58.030280   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4451 23:06:58.033214   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4452 23:06:58.040004   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4453 23:06:58.043243   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4454 23:06:58.047357   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4455 23:06:58.053719   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4456 23:06:58.056769   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4457 23:06:58.060102   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4458 23:06:58.066857   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4459 23:06:58.070267   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4460 23:06:58.073499   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)

 4461 23:06:58.076825  Total UI for P1: 0, mck2ui 16

 4462 23:06:58.080228  best dqsien dly found for B1: ( 0, 13, 10)

 4463 23:06:58.087126   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)

 4464 23:06:58.090204   0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4465 23:06:58.094234  Total UI for P1: 0, mck2ui 16

 4466 23:06:58.096789  best dqsien dly found for B0: ( 0, 13, 16)

 4467 23:06:58.100380  best DQS0 dly(MCK, UI, PI) = (0, 13, 16)

 4468 23:06:58.103579  best DQS1 dly(MCK, UI, PI) = (0, 13, 10)

 4469 23:06:58.103686  

 4470 23:06:58.106546  best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 16)

 4471 23:06:58.109803  best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)

 4472 23:06:58.113602  [Gating] SW calibration Done

 4473 23:06:58.113743  ==

 4474 23:06:58.116662  Dram Type= 6, Freq= 0, CH_1, rank 0

 4475 23:06:58.119895  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4476 23:06:58.123065  ==

 4477 23:06:58.123147  RX Vref Scan: 0

 4478 23:06:58.123211  

 4479 23:06:58.126452  RX Vref 0 -> 0, step: 1

 4480 23:06:58.126529  

 4481 23:06:58.129855  RX Delay -230 -> 252, step: 16

 4482 23:06:58.132944  iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304

 4483 23:06:58.137360  iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320

 4484 23:06:58.139937  iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304

 4485 23:06:58.146189  iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320

 4486 23:06:58.149980  iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304

 4487 23:06:58.153891  iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320

 4488 23:06:58.156386  iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320

 4489 23:06:58.159771  iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320

 4490 23:06:58.167128  iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336

 4491 23:06:58.169488  iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320

 4492 23:06:58.172904  iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320

 4493 23:06:58.176341  iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336

 4494 23:06:58.183049  iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336

 4495 23:06:58.187065  iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320

 4496 23:06:58.189676  iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320

 4497 23:06:58.193004  iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320

 4498 23:06:58.193106  ==

 4499 23:06:58.196228  Dram Type= 6, Freq= 0, CH_1, rank 0

 4500 23:06:58.203360  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4501 23:06:58.203480  ==

 4502 23:06:58.203550  DQS Delay:

 4503 23:06:58.206617  DQS0 = 0, DQS1 = 0

 4504 23:06:58.206721  DQM Delay:

 4505 23:06:58.206817  DQM0 = 46, DQM1 = 36

 4506 23:06:58.209478  DQ Delay:

 4507 23:06:58.212816  DQ0 =49, DQ1 =41, DQ2 =33, DQ3 =41

 4508 23:06:58.216271  DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =41

 4509 23:06:58.219802  DQ8 =17, DQ9 =25, DQ10 =41, DQ11 =33

 4510 23:06:58.223029  DQ12 =49, DQ13 =41, DQ14 =41, DQ15 =41

 4511 23:06:58.223125  

 4512 23:06:58.223191  

 4513 23:06:58.223253  ==

 4514 23:06:58.226534  Dram Type= 6, Freq= 0, CH_1, rank 0

 4515 23:06:58.229909  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4516 23:06:58.230006  ==

 4517 23:06:58.230075  

 4518 23:06:58.230137  

 4519 23:06:58.232945  	TX Vref Scan disable

 4520 23:06:58.233036   == TX Byte 0 ==

 4521 23:06:58.240619  Update DQ  dly =574 (2 ,1, 30)  DQ  OEN =(1 ,6)

 4522 23:06:58.244020  Update DQM dly =574 (2 ,1, 30)  DQM OEN =(1 ,6)

 4523 23:06:58.244129   == TX Byte 1 ==

 4524 23:06:58.250597  Update DQ  dly =575 (2 ,1, 31)  DQ  OEN =(1 ,6)

 4525 23:06:58.253861  Update DQM dly =575 (2 ,1, 31)  DQM OEN =(1 ,6)

 4526 23:06:58.253977  ==

 4527 23:06:58.256726  Dram Type= 6, Freq= 0, CH_1, rank 0

 4528 23:06:58.260512  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4529 23:06:58.260613  ==

 4530 23:06:58.260680  

 4531 23:06:58.260741  

 4532 23:06:58.263388  	TX Vref Scan disable

 4533 23:06:58.266997   == TX Byte 0 ==

 4534 23:06:58.270271  Update DQ  dly =574 (2 ,1, 30)  DQ  OEN =(1 ,6)

 4535 23:06:58.273222  Update DQM dly =574 (2 ,1, 30)  DQM OEN =(1 ,6)

 4536 23:06:58.276492   == TX Byte 1 ==

 4537 23:06:58.280841  Update DQ  dly =575 (2 ,1, 31)  DQ  OEN =(1 ,6)

 4538 23:06:58.283389  Update DQM dly =575 (2 ,1, 31)  DQM OEN =(1 ,6)

 4539 23:06:58.283491  

 4540 23:06:58.286723  [DATLAT]

 4541 23:06:58.286821  Freq=600, CH1 RK0

 4542 23:06:58.286922  

 4543 23:06:58.290527  DATLAT Default: 0x9

 4544 23:06:58.290620  0, 0xFFFF, sum = 0

 4545 23:06:58.293278  1, 0xFFFF, sum = 0

 4546 23:06:58.293370  2, 0xFFFF, sum = 0

 4547 23:06:58.297153  3, 0xFFFF, sum = 0

 4548 23:06:58.297258  4, 0xFFFF, sum = 0

 4549 23:06:58.300681  5, 0xFFFF, sum = 0

 4550 23:06:58.300779  6, 0xFFFF, sum = 0

 4551 23:06:58.303746  7, 0xFFFF, sum = 0

 4552 23:06:58.303862  8, 0x0, sum = 1

 4553 23:06:58.306608  9, 0x0, sum = 2

 4554 23:06:58.306730  10, 0x0, sum = 3

 4555 23:06:58.309903  11, 0x0, sum = 4

 4556 23:06:58.310021  best_step = 9

 4557 23:06:58.310137  

 4558 23:06:58.310227  ==

 4559 23:06:58.313394  Dram Type= 6, Freq= 0, CH_1, rank 0

 4560 23:06:58.317248  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4561 23:06:58.319845  ==

 4562 23:06:58.319943  RX Vref Scan: 1

 4563 23:06:58.320011  

 4564 23:06:58.323589  RX Vref 0 -> 0, step: 1

 4565 23:06:58.323686  

 4566 23:06:58.326864  RX Delay -195 -> 252, step: 8

 4567 23:06:58.326959  

 4568 23:06:58.329850  Set Vref, RX VrefLevel [Byte0]: 57

 4569 23:06:58.329940                           [Byte1]: 51

 4570 23:06:58.334933  

 4571 23:06:58.335046  Final RX Vref Byte 0 = 57 to rank0

 4572 23:06:58.338729  Final RX Vref Byte 1 = 51 to rank0

 4573 23:06:58.342101  Final RX Vref Byte 0 = 57 to rank1

 4574 23:06:58.345334  Final RX Vref Byte 1 = 51 to rank1==

 4575 23:06:58.348353  Dram Type= 6, Freq= 0, CH_1, rank 0

 4576 23:06:58.351620  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4577 23:06:58.355733  ==

 4578 23:06:58.355834  DQS Delay:

 4579 23:06:58.355902  DQS0 = 0, DQS1 = 0

 4580 23:06:58.358195  DQM Delay:

 4581 23:06:58.358327  DQM0 = 41, DQM1 = 33

 4582 23:06:58.361888  DQ Delay:

 4583 23:06:58.365078  DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =40

 4584 23:06:58.365177  DQ4 =44, DQ5 =48, DQ6 =52, DQ7 =36

 4585 23:06:58.368238  DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =28

 4586 23:06:58.372300  DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =40

 4587 23:06:58.375483  

 4588 23:06:58.375630  

 4589 23:06:58.381690  [DQSOSCAuto] RK0, (LSB)MR18= 0x440a, (MSB)MR19= 0x808, tDQSOscB0 = 408 ps tDQSOscB1 = 396 ps

 4590 23:06:58.385149  CH1 RK0: MR19=808, MR18=440A

 4591 23:06:58.391929  CH1_RK0: MR19=0x808, MR18=0x440A, DQSOSC=396, MR23=63, INC=167, DEC=111

 4592 23:06:58.392043  

 4593 23:06:58.395887  ----->DramcWriteLeveling(PI) begin...

 4594 23:06:58.395973  ==

 4595 23:06:58.398603  Dram Type= 6, Freq= 0, CH_1, rank 1

 4596 23:06:58.401838  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4597 23:06:58.401917  ==

 4598 23:06:58.405121  Write leveling (Byte 0): 29 => 29

 4599 23:06:58.408597  Write leveling (Byte 1): 31 => 31

 4600 23:06:58.412813  DramcWriteLeveling(PI) end<-----

 4601 23:06:58.412901  

 4602 23:06:58.412963  ==

 4603 23:06:58.415557  Dram Type= 6, Freq= 0, CH_1, rank 1

 4604 23:06:58.418721  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4605 23:06:58.418838  ==

 4606 23:06:58.422979  [Gating] SW mode calibration

 4607 23:06:58.428729  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0

 4608 23:06:58.435499  RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)

 4609 23:06:58.438746   0  9  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4610 23:06:58.442010   0  9  4 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)

 4611 23:06:58.448824   0  9  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4612 23:06:58.452239   0  9 12 | B1->B0 | 3333 2c2c | 0 1 | (0 0) (1 0)

 4613 23:06:58.455716   0  9 16 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)

 4614 23:06:58.462150   0  9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4615 23:06:58.465315   0  9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4616 23:06:58.468964   0  9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4617 23:06:58.472531   0 10  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4618 23:06:58.478963   0 10  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4619 23:06:58.482812   0 10  8 | B1->B0 | 2424 2525 | 0 0 | (0 0) (1 1)

 4620 23:06:58.485887   0 10 12 | B1->B0 | 3030 3a3a | 0 0 | (0 0) (0 0)

 4621 23:06:58.492713   0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4622 23:06:58.495887   0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4623 23:06:58.499259   0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4624 23:06:58.505565   0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4625 23:06:58.508615   0 11  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4626 23:06:58.512590   0 11  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4627 23:06:58.518597   0 11  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4628 23:06:58.522314   0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 4629 23:06:58.525831   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4630 23:06:58.531979   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4631 23:06:58.535972   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4632 23:06:58.539218   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4633 23:06:58.545308   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4634 23:06:58.549270   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4635 23:06:58.552271   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4636 23:06:58.559078   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4637 23:06:58.562355   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4638 23:06:58.565576   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4639 23:06:58.569783   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4640 23:06:58.575648   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4641 23:06:58.579207   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4642 23:06:58.582591   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4643 23:06:58.588743   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4644 23:06:58.592277   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4645 23:06:58.595700  Total UI for P1: 0, mck2ui 16

 4646 23:06:58.599093  best dqsien dly found for B0: ( 0, 13, 10)

 4647 23:06:58.602840  Total UI for P1: 0, mck2ui 16

 4648 23:06:58.606164  best dqsien dly found for B1: ( 0, 13, 10)

 4649 23:06:58.608805  best DQS0 dly(MCK, UI, PI) = (0, 13, 10)

 4650 23:06:58.612544  best DQS1 dly(MCK, UI, PI) = (0, 13, 10)

 4651 23:06:58.612672  

 4652 23:06:58.616167  best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)

 4653 23:06:58.619211  best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)

 4654 23:06:58.622384  [Gating] SW calibration Done

 4655 23:06:58.622543  ==

 4656 23:06:58.625880  Dram Type= 6, Freq= 0, CH_1, rank 1

 4657 23:06:58.629220  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4658 23:06:58.632633  ==

 4659 23:06:58.632749  RX Vref Scan: 0

 4660 23:06:58.632849  

 4661 23:06:58.635767  RX Vref 0 -> 0, step: 1

 4662 23:06:58.635874  

 4663 23:06:58.639589  RX Delay -230 -> 252, step: 16

 4664 23:06:58.642438  iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320

 4665 23:06:58.645459  iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336

 4666 23:06:58.648576  iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320

 4667 23:06:58.652730  iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320

 4668 23:06:58.659259  iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320

 4669 23:06:58.662048  iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336

 4670 23:06:58.666187  iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336

 4671 23:06:58.669038  iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320

 4672 23:06:58.675594  iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320

 4673 23:06:58.679106  iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320

 4674 23:06:58.682192  iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320

 4675 23:06:58.685654  iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320

 4676 23:06:58.692084  iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320

 4677 23:06:58.695581  iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336

 4678 23:06:58.698963  iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336

 4679 23:06:58.702073  iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320

 4680 23:06:58.702186  ==

 4681 23:06:58.705878  Dram Type= 6, Freq= 0, CH_1, rank 1

 4682 23:06:58.713214  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4683 23:06:58.713355  ==

 4684 23:06:58.713453  DQS Delay:

 4685 23:06:58.713548  DQS0 = 0, DQS1 = 0

 4686 23:06:58.715925  DQM Delay:

 4687 23:06:58.716038  DQM0 = 40, DQM1 = 37

 4688 23:06:58.719055  DQ Delay:

 4689 23:06:58.721962  DQ0 =41, DQ1 =33, DQ2 =25, DQ3 =41

 4690 23:06:58.726495  DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41

 4691 23:06:58.726616  DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =25

 4692 23:06:58.732342  DQ12 =41, DQ13 =49, DQ14 =49, DQ15 =41

 4693 23:06:58.732467  

 4694 23:06:58.732567  

 4695 23:06:58.732655  ==

 4696 23:06:58.735998  Dram Type= 6, Freq= 0, CH_1, rank 1

 4697 23:06:58.738607  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4698 23:06:58.738719  ==

 4699 23:06:58.738811  

 4700 23:06:58.738898  

 4701 23:06:58.742139  	TX Vref Scan disable

 4702 23:06:58.742248   == TX Byte 0 ==

 4703 23:06:58.748979  Update DQ  dly =574 (2 ,1, 30)  DQ  OEN =(1 ,6)

 4704 23:06:58.752192  Update DQM dly =574 (2 ,1, 30)  DQM OEN =(1 ,6)

 4705 23:06:58.752301   == TX Byte 1 ==

 4706 23:06:58.759260  Update DQ  dly =576 (2 ,1, 32)  DQ  OEN =(1 ,6)

 4707 23:06:58.762600  Update DQM dly =576 (2 ,1, 32)  DQM OEN =(1 ,6)

 4708 23:06:58.762720  ==

 4709 23:06:58.765606  Dram Type= 6, Freq= 0, CH_1, rank 1

 4710 23:06:58.768863  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4711 23:06:58.768970  ==

 4712 23:06:58.769060  

 4713 23:06:58.769157  

 4714 23:06:58.772956  	TX Vref Scan disable

 4715 23:06:58.775918   == TX Byte 0 ==

 4716 23:06:58.779622  Update DQ  dly =574 (2 ,1, 30)  DQ  OEN =(1 ,6)

 4717 23:06:58.782226  Update DQM dly =574 (2 ,1, 30)  DQM OEN =(1 ,6)

 4718 23:06:58.785727   == TX Byte 1 ==

 4719 23:06:58.789564  Update DQ  dly =576 (2 ,1, 32)  DQ  OEN =(1 ,6)

 4720 23:06:58.792785  Update DQM dly =576 (2 ,1, 32)  DQM OEN =(1 ,6)

 4721 23:06:58.792899  

 4722 23:06:58.795685  [DATLAT]

 4723 23:06:58.795792  Freq=600, CH1 RK1

 4724 23:06:58.795885  

 4725 23:06:58.799346  DATLAT Default: 0x9

 4726 23:06:58.799449  0, 0xFFFF, sum = 0

 4727 23:06:58.802340  1, 0xFFFF, sum = 0

 4728 23:06:58.802481  2, 0xFFFF, sum = 0

 4729 23:06:58.805458  3, 0xFFFF, sum = 0

 4730 23:06:58.805563  4, 0xFFFF, sum = 0

 4731 23:06:58.809480  5, 0xFFFF, sum = 0

 4732 23:06:58.809592  6, 0xFFFF, sum = 0

 4733 23:06:58.812336  7, 0xFFFF, sum = 0

 4734 23:06:58.812444  8, 0x0, sum = 1

 4735 23:06:58.816074  9, 0x0, sum = 2

 4736 23:06:58.816185  10, 0x0, sum = 3

 4737 23:06:58.818854  11, 0x0, sum = 4

 4738 23:06:58.818960  best_step = 9

 4739 23:06:58.819052  

 4740 23:06:58.819143  ==

 4741 23:06:58.822097  Dram Type= 6, Freq= 0, CH_1, rank 1

 4742 23:06:58.829347  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4743 23:06:58.829458  ==

 4744 23:06:58.829551  RX Vref Scan: 0

 4745 23:06:58.829646  

 4746 23:06:58.832381  RX Vref 0 -> 0, step: 1

 4747 23:06:58.832484  

 4748 23:06:58.835978  RX Delay -179 -> 252, step: 8

 4749 23:06:58.838699  iDelay=205, Bit 0, Center 44 (-107 ~ 196) 304

 4750 23:06:58.842316  iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312

 4751 23:06:58.848759  iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312

 4752 23:06:58.852063  iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304

 4753 23:06:58.855604  iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312

 4754 23:06:58.858755  iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312

 4755 23:06:58.866025  iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312

 4756 23:06:58.869106  iDelay=205, Bit 7, Center 36 (-115 ~ 188) 304

 4757 23:06:58.872560  iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320

 4758 23:06:58.875343  iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320

 4759 23:06:58.878974  iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320

 4760 23:06:58.886021  iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312

 4761 23:06:58.888752  iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312

 4762 23:06:58.892134  iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312

 4763 23:06:58.896098  iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312

 4764 23:06:58.902128  iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312

 4765 23:06:58.902244  ==

 4766 23:06:58.905587  Dram Type= 6, Freq= 0, CH_1, rank 1

 4767 23:06:58.908989  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4768 23:06:58.909102  ==

 4769 23:06:58.909199  DQS Delay:

 4770 23:06:58.912374  DQS0 = 0, DQS1 = 0

 4771 23:06:58.912482  DQM Delay:

 4772 23:06:58.915438  DQM0 = 38, DQM1 = 32

 4773 23:06:58.915542  DQ Delay:

 4774 23:06:58.918938  DQ0 =44, DQ1 =32, DQ2 =24, DQ3 =36

 4775 23:06:58.922334  DQ4 =40, DQ5 =48, DQ6 =48, DQ7 =36

 4776 23:06:58.925717  DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =24

 4777 23:06:58.929331  DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40

 4778 23:06:58.929440  

 4779 23:06:58.929531  

 4780 23:06:58.935803  [DQSOSCAuto] RK1, (LSB)MR18= 0x3847, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 399 ps

 4781 23:06:58.939157  CH1 RK1: MR19=808, MR18=3847

 4782 23:06:58.945661  CH1_RK1: MR19=0x808, MR18=0x3847, DQSOSC=396, MR23=63, INC=167, DEC=111

 4783 23:06:58.948899  [RxdqsGatingPostProcess] freq 600

 4784 23:06:58.955657  ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1

 4785 23:06:58.958796  Pre-setting of DQS Precalculation

 4786 23:06:58.962454  [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9

 4787 23:06:58.968944  sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5

 4788 23:06:58.975658  calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464

 4789 23:06:58.975797  

 4790 23:06:58.975893  

 4791 23:06:58.978995  [Calibration Summary] 1200 Mbps

 4792 23:06:58.982389  CH 0, Rank 0

 4793 23:06:58.982515  SW Impedance     : PASS

 4794 23:06:58.986222  DUTY Scan        : NO K

 4795 23:06:58.986328  ZQ Calibration   : PASS

 4796 23:06:58.988975  Jitter Meter     : NO K

 4797 23:06:58.992685  CBT Training     : PASS

 4798 23:06:58.992792  Write leveling   : PASS

 4799 23:06:58.995912  RX DQS gating    : PASS

 4800 23:06:58.999934  RX DQ/DQS(RDDQC) : PASS

 4801 23:06:59.000040  TX DQ/DQS        : PASS

 4802 23:06:59.002822  RX DATLAT        : PASS

 4803 23:06:59.006059  RX DQ/DQS(Engine): PASS

 4804 23:06:59.006171  TX OE            : NO K

 4805 23:06:59.009655  All Pass.

 4806 23:06:59.009761  

 4807 23:06:59.009850  CH 0, Rank 1

 4808 23:06:59.012348  SW Impedance     : PASS

 4809 23:06:59.012459  DUTY Scan        : NO K

 4810 23:06:59.016548  ZQ Calibration   : PASS

 4811 23:06:59.019344  Jitter Meter     : NO K

 4812 23:06:59.019450  CBT Training     : PASS

 4813 23:06:59.022768  Write leveling   : PASS

 4814 23:06:59.026526  RX DQS gating    : PASS

 4815 23:06:59.026633  RX DQ/DQS(RDDQC) : PASS

 4816 23:06:59.029900  TX DQ/DQS        : PASS

 4817 23:06:59.030007  RX DATLAT        : PASS

 4818 23:06:59.033129  RX DQ/DQS(Engine): PASS

 4819 23:06:59.035897  TX OE            : NO K

 4820 23:06:59.036006  All Pass.

 4821 23:06:59.036095  

 4822 23:06:59.036179  CH 1, Rank 0

 4823 23:06:59.039026  SW Impedance     : PASS

 4824 23:06:59.042643  DUTY Scan        : NO K

 4825 23:06:59.042753  ZQ Calibration   : PASS

 4826 23:06:59.046224  Jitter Meter     : NO K

 4827 23:06:59.049330  CBT Training     : PASS

 4828 23:06:59.049434  Write leveling   : PASS

 4829 23:06:59.053554  RX DQS gating    : PASS

 4830 23:06:59.056233  RX DQ/DQS(RDDQC) : PASS

 4831 23:06:59.056339  TX DQ/DQS        : PASS

 4832 23:06:59.059709  RX DATLAT        : PASS

 4833 23:06:59.062556  RX DQ/DQS(Engine): PASS

 4834 23:06:59.062660  TX OE            : NO K

 4835 23:06:59.062755  All Pass.

 4836 23:06:59.062844  

 4837 23:06:59.066059  CH 1, Rank 1

 4838 23:06:59.066163  SW Impedance     : PASS

 4839 23:06:59.069947  DUTY Scan        : NO K

 4840 23:06:59.073183  ZQ Calibration   : PASS

 4841 23:06:59.073301  Jitter Meter     : NO K

 4842 23:06:59.076114  CBT Training     : PASS

 4843 23:06:59.079277  Write leveling   : PASS

 4844 23:06:59.079383  RX DQS gating    : PASS

 4845 23:06:59.082591  RX DQ/DQS(RDDQC) : PASS

 4846 23:06:59.086443  TX DQ/DQS        : PASS

 4847 23:06:59.086568  RX DATLAT        : PASS

 4848 23:06:59.089352  RX DQ/DQS(Engine): PASS

 4849 23:06:59.092896  TX OE            : NO K

 4850 23:06:59.093005  All Pass.

 4851 23:06:59.093095  

 4852 23:06:59.093183  DramC Write-DBI off

 4853 23:06:59.096371  	PER_BANK_REFRESH: Hybrid Mode

 4854 23:06:59.099723  TX_TRACKING: ON

 4855 23:06:59.106061  [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1

 4856 23:06:59.109348  [FAST_K] Save calibration result to emmc

 4857 23:06:59.116192  dramc_set_vcore_voltage set vcore to 662500

 4858 23:06:59.116306  Read voltage for 933, 3

 4859 23:06:59.119523  Vio18 = 0

 4860 23:06:59.119624  Vcore = 662500

 4861 23:06:59.119713  Vdram = 0

 4862 23:06:59.119799  Vddq = 0

 4863 23:06:59.122861  Vmddr = 0

 4864 23:06:59.125794  [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0

 4865 23:06:59.133758  [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0

 4866 23:06:59.137123  MEM_TYPE=3, freq_sel=17

 4867 23:06:59.137232  sv_algorithm_assistance_LP4_1600 

 4868 23:06:59.142540  ============ PULL DRAM RESETB DOWN ============

 4869 23:06:59.146228  ========== PULL DRAM RESETB DOWN end =========

 4870 23:06:59.149818  [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3

 4871 23:06:59.152462  =================================== 

 4872 23:06:59.156335  LPDDR4 DRAM CONFIGURATION

 4873 23:06:59.159050  =================================== 

 4874 23:06:59.162560  EX_ROW_EN[0]    = 0x0

 4875 23:06:59.162660  EX_ROW_EN[1]    = 0x0

 4876 23:06:59.166177  LP4Y_EN      = 0x0

 4877 23:06:59.166286  WORK_FSP     = 0x0

 4878 23:06:59.169279  WL           = 0x3

 4879 23:06:59.169380  RL           = 0x3

 4880 23:06:59.172845  BL           = 0x2

 4881 23:06:59.172945  RPST         = 0x0

 4882 23:06:59.176148  RD_PRE       = 0x0

 4883 23:06:59.176257  WR_PRE       = 0x1

 4884 23:06:59.180324  WR_PST       = 0x0

 4885 23:06:59.180431  DBI_WR       = 0x0

 4886 23:06:59.182523  DBI_RD       = 0x0

 4887 23:06:59.182631  OTF          = 0x1

 4888 23:06:59.186046  =================================== 

 4889 23:06:59.189213  =================================== 

 4890 23:06:59.193034  ANA top config

 4891 23:06:59.196121  =================================== 

 4892 23:06:59.199163  DLL_ASYNC_EN            =  0

 4893 23:06:59.199369  ALL_SLAVE_EN            =  1

 4894 23:06:59.202978  NEW_RANK_MODE           =  1

 4895 23:06:59.206525  DLL_IDLE_MODE           =  1

 4896 23:06:59.209656  LP45_APHY_COMB_EN       =  1

 4897 23:06:59.209767  TX_ODT_DIS              =  1

 4898 23:06:59.213226  NEW_8X_MODE             =  1

 4899 23:06:59.216173  =================================== 

 4900 23:06:59.219417  =================================== 

 4901 23:06:59.223328  data_rate                  = 1866

 4902 23:06:59.226201  CKR                        = 1

 4903 23:06:59.229242  DQ_P2S_RATIO               = 8

 4904 23:06:59.233161  =================================== 

 4905 23:06:59.236544  CA_P2S_RATIO               = 8

 4906 23:06:59.236643  DQ_CA_OPEN                 = 0

 4907 23:06:59.239246  DQ_SEMI_OPEN               = 0

 4908 23:06:59.242503  CA_SEMI_OPEN               = 0

 4909 23:06:59.246137  CA_FULL_RATE               = 0

 4910 23:06:59.249568  DQ_CKDIV4_EN               = 1

 4911 23:06:59.253112  CA_CKDIV4_EN               = 1

 4912 23:06:59.253220  CA_PREDIV_EN               = 0

 4913 23:06:59.255865  PH8_DLY                    = 0

 4914 23:06:59.259560  SEMI_OPEN_CA_PICK_MCK_RATIO= 0

 4915 23:06:59.263084  DQ_AAMCK_DIV               = 4

 4916 23:06:59.265921  CA_AAMCK_DIV               = 4

 4917 23:06:59.266032  CA_ADMCK_DIV               = 4

 4918 23:06:59.269821  DQ_TRACK_CA_EN             = 0

 4919 23:06:59.273216  CA_PICK                    = 933

 4920 23:06:59.276602  CA_MCKIO                   = 933

 4921 23:06:59.279455  MCKIO_SEMI                 = 0

 4922 23:06:59.282790  PLL_FREQ                   = 3732

 4923 23:06:59.286564  DQ_UI_PI_RATIO             = 32

 4924 23:06:59.286681  CA_UI_PI_RATIO             = 0

 4925 23:06:59.289503  =================================== 

 4926 23:06:59.292722  =================================== 

 4927 23:06:59.296400  memory_type:LPDDR4         

 4928 23:06:59.299741  GP_NUM     : 10       

 4929 23:06:59.299852  SRAM_EN    : 1       

 4930 23:06:59.302794  MD32_EN    : 0       

 4931 23:06:59.306019  =================================== 

 4932 23:06:59.309700  [ANA_INIT] >>>>>>>>>>>>>> 

 4933 23:06:59.312814  <<<<<< [CONFIGURE PHASE]: ANA_TX

 4934 23:06:59.316196  >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL

 4935 23:06:59.319960  =================================== 

 4936 23:06:59.320071  data_rate = 1866,PCW = 0X8f00

 4937 23:06:59.323199  =================================== 

 4938 23:06:59.326219  <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL

 4939 23:06:59.333298  >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 4940 23:06:59.340964  <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 4941 23:06:59.343254  >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2

 4942 23:06:59.346140  >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL

 4943 23:06:59.349720  <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL

 4944 23:06:59.353386  [ANA_INIT] flow start 

 4945 23:06:59.353501  [ANA_INIT] PLL >>>>>>>> 

 4946 23:06:59.356165  [ANA_INIT] PLL <<<<<<<< 

 4947 23:06:59.359424  [ANA_INIT] MIDPI >>>>>>>> 

 4948 23:06:59.362740  [ANA_INIT] MIDPI <<<<<<<< 

 4949 23:06:59.362848  [ANA_INIT] DLL >>>>>>>> 

 4950 23:06:59.366260  [ANA_INIT] flow end 

 4951 23:06:59.369217  ============ LP4 DIFF to SE enter ============

 4952 23:06:59.372730  ============ LP4 DIFF to SE exit  ============

 4953 23:06:59.376160  [ANA_INIT] <<<<<<<<<<<<< 

 4954 23:06:59.379314  [Flow] Enable top DCM control >>>>> 

 4955 23:06:59.383223  [Flow] Enable top DCM control <<<<< 

 4956 23:06:59.386190  Enable DLL master slave shuffle 

 4957 23:06:59.389301  ============================================================== 

 4958 23:06:59.393224  Gating Mode config

 4959 23:06:59.399218  ============================================================== 

 4960 23:06:59.399353  Config description: 

 4961 23:06:59.409639  RX_GATING_MODE        0: Pulse Mode      1: Burst Mode(8UI)        2: Burst Mode(7UI)  3: Original Burst Mode

 4962 23:06:59.416226  RX_GATING_TRACK_MODE  0: Valid DLY Mode  1: Valid Mode (-like) 2: FIFO mode

 4963 23:06:59.422936  SELPH_MODE            0: By rank         1: By Phase 

 4964 23:06:59.426237  ============================================================== 

 4965 23:06:59.429729  GAT_TRACK_EN                 =  1

 4966 23:06:59.432641  RX_GATING_MODE               =  2

 4967 23:06:59.436359  RX_GATING_TRACK_MODE         =  2

 4968 23:06:59.439403  SELPH_MODE                   =  1

 4969 23:06:59.442547  PICG_EARLY_EN                =  1

 4970 23:06:59.446000  VALID_LAT_VALUE              =  1

 4971 23:06:59.449243  ============================================================== 

 4972 23:06:59.452727  Enter into Gating configuration >>>> 

 4973 23:06:59.456226  Exit from Gating configuration <<<< 

 4974 23:06:59.459957  Enter into  DVFS_PRE_config >>>>> 

 4975 23:06:59.473518  Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. 

 4976 23:06:59.473694  Exit from  DVFS_PRE_config <<<<< 

 4977 23:06:59.476149  Enter into PICG configuration >>>> 

 4978 23:06:59.479384  Exit from PICG configuration <<<< 

 4979 23:06:59.484327  [RX_INPUT] configuration >>>>> 

 4980 23:06:59.486357  [RX_INPUT] configuration <<<<< 

 4981 23:06:59.493462  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>

 4982 23:06:59.495882  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<

 4983 23:06:59.503350  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>

 4984 23:06:59.509989  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<

 4985 23:06:59.517161  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>

 4986 23:06:59.522996  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<

 4987 23:06:59.526419  [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 

 4988 23:06:59.529657  [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 

 4989 23:06:59.533481  [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 

 4990 23:06:59.536331  [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 

 4991 23:06:59.543519  [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 

 4992 23:06:59.547239  [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3

 4993 23:06:59.550241  =================================== 

 4994 23:06:59.553013  LPDDR4 DRAM CONFIGURATION

 4995 23:06:59.556868  =================================== 

 4996 23:06:59.556989  EX_ROW_EN[0]    = 0x0

 4997 23:06:59.560158  EX_ROW_EN[1]    = 0x0

 4998 23:06:59.560271  LP4Y_EN      = 0x0

 4999 23:06:59.563424  WORK_FSP     = 0x0

 5000 23:06:59.563535  WL           = 0x3

 5001 23:06:59.566375  RL           = 0x3

 5002 23:06:59.566507  BL           = 0x2

 5003 23:06:59.569587  RPST         = 0x0

 5004 23:06:59.569696  RD_PRE       = 0x0

 5005 23:06:59.573328  WR_PRE       = 0x1

 5006 23:06:59.576381  WR_PST       = 0x0

 5007 23:06:59.576500  DBI_WR       = 0x0

 5008 23:06:59.579560  DBI_RD       = 0x0

 5009 23:06:59.579671  OTF          = 0x1

 5010 23:06:59.583053  =================================== 

 5011 23:06:59.586318  [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 

 5012 23:06:59.589761  [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 

 5013 23:06:59.596594  [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3

 5014 23:06:59.599623  =================================== 

 5015 23:06:59.603847  LPDDR4 DRAM CONFIGURATION

 5016 23:06:59.606987  =================================== 

 5017 23:06:59.607110  EX_ROW_EN[0]    = 0x10

 5018 23:06:59.609518  EX_ROW_EN[1]    = 0x0

 5019 23:06:59.609653  LP4Y_EN      = 0x0

 5020 23:06:59.612818  WORK_FSP     = 0x0

 5021 23:06:59.612928  WL           = 0x3

 5022 23:06:59.616637  RL           = 0x3

 5023 23:06:59.616787  BL           = 0x2

 5024 23:06:59.619815  RPST         = 0x0

 5025 23:06:59.619923  RD_PRE       = 0x0

 5026 23:06:59.623246  WR_PRE       = 0x1

 5027 23:06:59.623357  WR_PST       = 0x0

 5028 23:06:59.627088  DBI_WR       = 0x0

 5029 23:06:59.627202  DBI_RD       = 0x0

 5030 23:06:59.630038  OTF          = 0x1

 5031 23:06:59.633241  =================================== 

 5032 23:06:59.639960  [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit

 5033 23:06:59.643110  nWR fixed to 30

 5034 23:06:59.643237  [ModeRegInit_LP4] CH0 RK0

 5035 23:06:59.646632  [ModeRegInit_LP4] CH0 RK1

 5036 23:06:59.650308  [ModeRegInit_LP4] CH1 RK0

 5037 23:06:59.653467  [ModeRegInit_LP4] CH1 RK1

 5038 23:06:59.653600  match AC timing 9

 5039 23:06:59.656849  dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1

 5040 23:06:59.663294  SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON

 5041 23:06:59.666834  [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10

 5042 23:06:59.673335  [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21

 5043 23:06:59.676343  [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)

 5044 23:06:59.676509  ==

 5045 23:06:59.679676  Dram Type= 6, Freq= 0, CH_0, rank 0

 5046 23:06:59.683507  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5047 23:06:59.683667  ==

 5048 23:06:59.690097  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 5049 23:06:59.696601  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35

 5050 23:06:59.699748  [CA 0] Center 38 (8~69) winsize 62

 5051 23:06:59.703506  [CA 1] Center 38 (7~69) winsize 63

 5052 23:06:59.706364  [CA 2] Center 35 (5~66) winsize 62

 5053 23:06:59.709918  [CA 3] Center 35 (5~65) winsize 61

 5054 23:06:59.713328  [CA 4] Center 34 (4~64) winsize 61

 5055 23:06:59.716109  [CA 5] Center 33 (3~64) winsize 62

 5056 23:06:59.716242  

 5057 23:06:59.719428  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 5058 23:06:59.719563  

 5059 23:06:59.723457  [CATrainingPosCal] consider 1 rank data

 5060 23:06:59.726463  u2DelayCellTimex100 = 270/100 ps

 5061 23:06:59.730010  CA0 delay=38 (8~69),Diff = 5 PI (31 cell)

 5062 23:06:59.732942  CA1 delay=38 (7~69),Diff = 5 PI (31 cell)

 5063 23:06:59.736818  CA2 delay=35 (5~66),Diff = 2 PI (12 cell)

 5064 23:06:59.739466  CA3 delay=35 (5~65),Diff = 2 PI (12 cell)

 5065 23:06:59.743122  CA4 delay=34 (4~64),Diff = 1 PI (6 cell)

 5066 23:06:59.746473  CA5 delay=33 (3~64),Diff = 0 PI (0 cell)

 5067 23:06:59.746592  

 5068 23:06:59.749883  CA PerBit enable=1, Macro0, CA PI delay=33

 5069 23:06:59.753462  

 5070 23:06:59.753576  [CBTSetCACLKResult] CA Dly = 33

 5071 23:06:59.756513  CS Dly: 6 (0~37)

 5072 23:06:59.756629  ==

 5073 23:06:59.759619  Dram Type= 6, Freq= 0, CH_0, rank 1

 5074 23:06:59.763688  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5075 23:06:59.763801  ==

 5076 23:06:59.769959  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 5077 23:06:59.776616  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35

 5078 23:06:59.779884  [CA 0] Center 38 (7~69) winsize 63

 5079 23:06:59.782749  [CA 1] Center 37 (7~68) winsize 62

 5080 23:06:59.786031  [CA 2] Center 35 (5~66) winsize 62

 5081 23:06:59.789707  [CA 3] Center 34 (4~65) winsize 62

 5082 23:06:59.793386  [CA 4] Center 34 (4~65) winsize 62

 5083 23:06:59.796265  [CA 5] Center 33 (3~64) winsize 62

 5084 23:06:59.796380  

 5085 23:06:59.800024  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 5086 23:06:59.800141  

 5087 23:06:59.803238  [CATrainingPosCal] consider 2 rank data

 5088 23:06:59.806696  u2DelayCellTimex100 = 270/100 ps

 5089 23:06:59.810054  CA0 delay=38 (8~69),Diff = 5 PI (31 cell)

 5090 23:06:59.813351  CA1 delay=37 (7~68),Diff = 4 PI (24 cell)

 5091 23:06:59.816438  CA2 delay=35 (5~66),Diff = 2 PI (12 cell)

 5092 23:06:59.820374  CA3 delay=35 (5~65),Diff = 2 PI (12 cell)

 5093 23:06:59.823146  CA4 delay=34 (4~64),Diff = 1 PI (6 cell)

 5094 23:06:59.826590  CA5 delay=33 (3~64),Diff = 0 PI (0 cell)

 5095 23:06:59.826698  

 5096 23:06:59.833258  CA PerBit enable=1, Macro0, CA PI delay=33

 5097 23:06:59.833375  

 5098 23:06:59.833465  [CBTSetCACLKResult] CA Dly = 33

 5099 23:06:59.836224  CS Dly: 7 (0~39)

 5100 23:06:59.836345  

 5101 23:06:59.839902  ----->DramcWriteLeveling(PI) begin...

 5102 23:06:59.840012  ==

 5103 23:06:59.843264  Dram Type= 6, Freq= 0, CH_0, rank 0

 5104 23:06:59.846191  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5105 23:06:59.846301  ==

 5106 23:06:59.849646  Write leveling (Byte 0): 32 => 32

 5107 23:06:59.853041  Write leveling (Byte 1): 27 => 27

 5108 23:06:59.856429  DramcWriteLeveling(PI) end<-----

 5109 23:06:59.856541  

 5110 23:06:59.856633  ==

 5111 23:06:59.859601  Dram Type= 6, Freq= 0, CH_0, rank 0

 5112 23:06:59.863163  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5113 23:06:59.863274  ==

 5114 23:06:59.866324  [Gating] SW mode calibration

 5115 23:06:59.873612  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

 5116 23:06:59.881037  RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)

 5117 23:06:59.882972   0 14  0 | B1->B0 | 2323 2b2b | 0 0 | (1 1) (0 0)

 5118 23:06:59.889938   0 14  4 | B1->B0 | 2e2e 3434 | 0 1 | (0 0) (1 1)

 5119 23:06:59.893167   0 14  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5120 23:06:59.896677   0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5121 23:06:59.903780   0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5122 23:06:59.906673   0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5123 23:06:59.910344   0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5124 23:06:59.913267   0 14 28 | B1->B0 | 3434 3333 | 0 1 | (0 0) (0 0)

 5125 23:06:59.919825   0 15  0 | B1->B0 | 3232 2e2e | 0 0 | (0 0) (0 0)

 5126 23:06:59.923329   0 15  4 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)

 5127 23:06:59.927182   0 15  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5128 23:06:59.933068   0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5129 23:06:59.936968   0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5130 23:06:59.940234   0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5131 23:06:59.946808   0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5132 23:06:59.950347   0 15 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)

 5133 23:06:59.953557   1  0  0 | B1->B0 | 3636 4343 | 0 0 | (0 0) (0 0)

 5134 23:06:59.960018   1  0  4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)

 5135 23:06:59.963047   1  0  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5136 23:06:59.966331   1  0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5137 23:06:59.973218   1  0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5138 23:06:59.976282   1  0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5139 23:06:59.980059   1  0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5140 23:06:59.986330   1  0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 5141 23:06:59.990010   1  1  0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 5142 23:06:59.993208   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 5143 23:06:59.999961   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5144 23:07:00.003290   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5145 23:07:00.006708   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5146 23:07:00.010092   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5147 23:07:00.016702   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5148 23:07:00.019952   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5149 23:07:00.023257   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5150 23:07:00.029993   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5151 23:07:00.033021   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5152 23:07:00.036700   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5153 23:07:00.043361   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5154 23:07:00.046600   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5155 23:07:00.050172   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 5156 23:07:00.057062   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5157 23:07:00.060036   1  3  0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 5158 23:07:00.063515   1  3  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5159 23:07:00.066498  Total UI for P1: 0, mck2ui 16

 5160 23:07:00.070346  best dqsien dly found for B0: ( 1,  3,  0)

 5161 23:07:00.073417  Total UI for P1: 0, mck2ui 16

 5162 23:07:00.077432  best dqsien dly found for B1: ( 1,  3,  0)

 5163 23:07:00.080363  best DQS0 dly(MCK, UI, PI) = (1, 3, 0)

 5164 23:07:00.084393  best DQS1 dly(MCK, UI, PI) = (1, 3, 0)

 5165 23:07:00.084516  

 5166 23:07:00.087273  best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 0)

 5167 23:07:00.091014  best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)

 5168 23:07:00.094084  [Gating] SW calibration Done

 5169 23:07:00.094208  ==

 5170 23:07:00.097143  Dram Type= 6, Freq= 0, CH_0, rank 0

 5171 23:07:00.100203  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5172 23:07:00.103669  ==

 5173 23:07:00.103785  RX Vref Scan: 0

 5174 23:07:00.103880  

 5175 23:07:00.107315  RX Vref 0 -> 0, step: 1

 5176 23:07:00.107429  

 5177 23:07:00.107523  RX Delay -80 -> 252, step: 8

 5178 23:07:00.114239  iDelay=208, Bit 0, Center 99 (8 ~ 191) 184

 5179 23:07:00.117433  iDelay=208, Bit 1, Center 103 (8 ~ 199) 192

 5180 23:07:00.120768  iDelay=208, Bit 2, Center 95 (0 ~ 191) 192

 5181 23:07:00.124857  iDelay=208, Bit 3, Center 95 (0 ~ 191) 192

 5182 23:07:00.126934  iDelay=208, Bit 4, Center 103 (8 ~ 199) 192

 5183 23:07:00.130595  iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192

 5184 23:07:00.137686  iDelay=208, Bit 6, Center 107 (8 ~ 207) 200

 5185 23:07:00.140619  iDelay=208, Bit 7, Center 103 (8 ~ 199) 192

 5186 23:07:00.144059  iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192

 5187 23:07:00.147270  iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192

 5188 23:07:00.150081  iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192

 5189 23:07:00.156932  iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192

 5190 23:07:00.160916  iDelay=208, Bit 12, Center 95 (0 ~ 191) 192

 5191 23:07:00.164518  iDelay=208, Bit 13, Center 95 (0 ~ 191) 192

 5192 23:07:00.167410  iDelay=208, Bit 14, Center 95 (0 ~ 191) 192

 5193 23:07:00.170772  iDelay=208, Bit 15, Center 95 (0 ~ 191) 192

 5194 23:07:00.170897  ==

 5195 23:07:00.173939  Dram Type= 6, Freq= 0, CH_0, rank 0

 5196 23:07:00.180555  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5197 23:07:00.180701  ==

 5198 23:07:00.180800  DQS Delay:

 5199 23:07:00.180895  DQS0 = 0, DQS1 = 0

 5200 23:07:00.183653  DQM Delay:

 5201 23:07:00.183743  DQM0 = 99, DQM1 = 88

 5202 23:07:00.187260  DQ Delay:

 5203 23:07:00.190326  DQ0 =99, DQ1 =103, DQ2 =95, DQ3 =95

 5204 23:07:00.193843  DQ4 =103, DQ5 =87, DQ6 =107, DQ7 =103

 5205 23:07:00.197050  DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =79

 5206 23:07:00.200382  DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95

 5207 23:07:00.200495  

 5208 23:07:00.200563  

 5209 23:07:00.200623  ==

 5210 23:07:00.203625  Dram Type= 6, Freq= 0, CH_0, rank 0

 5211 23:07:00.207257  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5212 23:07:00.207351  ==

 5213 23:07:00.207419  

 5214 23:07:00.207481  

 5215 23:07:00.210332  	TX Vref Scan disable

 5216 23:07:00.210448   == TX Byte 0 ==

 5217 23:07:00.217722  Update DQ  dly =716 (2 ,6, 12)  DQ  OEN =(2 ,3)

 5218 23:07:00.220527  Update DQM dly =716 (2 ,6, 12)  DQM OEN =(2 ,3)

 5219 23:07:00.220625   == TX Byte 1 ==

 5220 23:07:00.227424  Update DQ  dly =709 (2 ,5, 37)  DQ  OEN =(2 ,2)

 5221 23:07:00.230625  Update DQM dly =709 (2 ,5, 37)  DQM OEN =(2 ,2)

 5222 23:07:00.230725  ==

 5223 23:07:00.234109  Dram Type= 6, Freq= 0, CH_0, rank 0

 5224 23:07:00.237265  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5225 23:07:00.237363  ==

 5226 23:07:00.237430  

 5227 23:07:00.237491  

 5228 23:07:00.240404  	TX Vref Scan disable

 5229 23:07:00.244040   == TX Byte 0 ==

 5230 23:07:00.247180  Update DQ  dly =716 (2 ,6, 12)  DQ  OEN =(2 ,3)

 5231 23:07:00.250159  Update DQM dly =716 (2 ,6, 12)  DQM OEN =(2 ,3)

 5232 23:07:00.253817   == TX Byte 1 ==

 5233 23:07:00.258174  Update DQ  dly =709 (2 ,5, 37)  DQ  OEN =(2 ,2)

 5234 23:07:00.260435  Update DQM dly =709 (2 ,5, 37)  DQM OEN =(2 ,2)

 5235 23:07:00.260552  

 5236 23:07:00.263619  [DATLAT]

 5237 23:07:00.263735  Freq=933, CH0 RK0

 5238 23:07:00.263831  

 5239 23:07:00.266925  DATLAT Default: 0xd

 5240 23:07:00.267040  0, 0xFFFF, sum = 0

 5241 23:07:00.270999  1, 0xFFFF, sum = 0

 5242 23:07:00.271121  2, 0xFFFF, sum = 0

 5243 23:07:00.274010  3, 0xFFFF, sum = 0

 5244 23:07:00.274129  4, 0xFFFF, sum = 0

 5245 23:07:00.276979  5, 0xFFFF, sum = 0

 5246 23:07:00.277093  6, 0xFFFF, sum = 0

 5247 23:07:00.281114  7, 0xFFFF, sum = 0

 5248 23:07:00.281212  8, 0xFFFF, sum = 0

 5249 23:07:00.283784  9, 0xFFFF, sum = 0

 5250 23:07:00.283872  10, 0x0, sum = 1

 5251 23:07:00.287892  11, 0x0, sum = 2

 5252 23:07:00.287993  12, 0x0, sum = 3

 5253 23:07:00.290884  13, 0x0, sum = 4

 5254 23:07:00.290973  best_step = 11

 5255 23:07:00.291039  

 5256 23:07:00.291101  ==

 5257 23:07:00.293865  Dram Type= 6, Freq= 0, CH_0, rank 0

 5258 23:07:00.301335  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5259 23:07:00.301477  ==

 5260 23:07:00.301548  RX Vref Scan: 1

 5261 23:07:00.301611  

 5262 23:07:00.303837  RX Vref 0 -> 0, step: 1

 5263 23:07:00.303914  

 5264 23:07:00.307889  RX Delay -61 -> 252, step: 4

 5265 23:07:00.307982  

 5266 23:07:00.310703  Set Vref, RX VrefLevel [Byte0]: 53

 5267 23:07:00.313966                           [Byte1]: 52

 5268 23:07:00.314083  

 5269 23:07:00.317079  Final RX Vref Byte 0 = 53 to rank0

 5270 23:07:00.321063  Final RX Vref Byte 1 = 52 to rank0

 5271 23:07:00.324038  Final RX Vref Byte 0 = 53 to rank1

 5272 23:07:00.327308  Final RX Vref Byte 1 = 52 to rank1==

 5273 23:07:00.330637  Dram Type= 6, Freq= 0, CH_0, rank 0

 5274 23:07:00.333978  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5275 23:07:00.334071  ==

 5276 23:07:00.337478  DQS Delay:

 5277 23:07:00.337573  DQS0 = 0, DQS1 = 0

 5278 23:07:00.337641  DQM Delay:

 5279 23:07:00.340581  DQM0 = 97, DQM1 = 88

 5280 23:07:00.340668  DQ Delay:

 5281 23:07:00.344684  DQ0 =98, DQ1 =98, DQ2 =94, DQ3 =94

 5282 23:07:00.347931  DQ4 =98, DQ5 =86, DQ6 =106, DQ7 =102

 5283 23:07:00.350703  DQ8 =78, DQ9 =76, DQ10 =92, DQ11 =82

 5284 23:07:00.354432  DQ12 =94, DQ13 =92, DQ14 =96, DQ15 =96

 5285 23:07:00.354539  

 5286 23:07:00.354606  

 5287 23:07:00.363842  [DQSOSCAuto] RK0, (LSB)MR18= 0x1702, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 414 ps

 5288 23:07:00.363965  CH0 RK0: MR19=505, MR18=1702

 5289 23:07:00.371319  CH0_RK0: MR19=0x505, MR18=0x1702, DQSOSC=414, MR23=63, INC=63, DEC=42

 5290 23:07:00.371433  

 5291 23:07:00.373991  ----->DramcWriteLeveling(PI) begin...

 5292 23:07:00.374137  ==

 5293 23:07:00.377391  Dram Type= 6, Freq= 0, CH_0, rank 1

 5294 23:07:00.384368  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5295 23:07:00.384495  ==

 5296 23:07:00.387494  Write leveling (Byte 0): 28 => 28

 5297 23:07:00.391383  Write leveling (Byte 1): 27 => 27

 5298 23:07:00.391484  DramcWriteLeveling(PI) end<-----

 5299 23:07:00.391550  

 5300 23:07:00.394929  ==

 5301 23:07:00.397721  Dram Type= 6, Freq= 0, CH_0, rank 1

 5302 23:07:00.401182  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5303 23:07:00.401282  ==

 5304 23:07:00.404380  [Gating] SW mode calibration

 5305 23:07:00.410962  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

 5306 23:07:00.414393  RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)

 5307 23:07:00.420938   0 14  0 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)

 5308 23:07:00.423908   0 14  4 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)

 5309 23:07:00.427574   0 14  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5310 23:07:00.434553   0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5311 23:07:00.437336   0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5312 23:07:00.441868   0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5313 23:07:00.447880   0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)

 5314 23:07:00.450838   0 14 28 | B1->B0 | 3434 3030 | 1 0 | (1 0) (0 0)

 5315 23:07:00.454510   0 15  0 | B1->B0 | 2f2f 2323 | 0 0 | (0 1) (0 0)

 5316 23:07:00.457536   0 15  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5317 23:07:00.464165   0 15  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5318 23:07:00.467729   0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5319 23:07:00.470891   0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5320 23:07:00.477847   0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5321 23:07:00.480863   0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5322 23:07:00.484028   0 15 28 | B1->B0 | 2b2b 3a3a | 0 0 | (0 0) (0 0)

 5323 23:07:00.491694   1  0  0 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)

 5324 23:07:00.494281   1  0  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5325 23:07:00.497449   1  0  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5326 23:07:00.504155   1  0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5327 23:07:00.507987   1  0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5328 23:07:00.511167   1  0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5329 23:07:00.518801   1  0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 5330 23:07:00.521138   1  0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 5331 23:07:00.525119   1  1  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 5332 23:07:00.527733   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5333 23:07:00.534725   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5334 23:07:00.538428   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5335 23:07:00.541088   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5336 23:07:00.548051   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5337 23:07:00.551694   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5338 23:07:00.554800   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5339 23:07:00.561001   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5340 23:07:00.564525   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5341 23:07:00.568459   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5342 23:07:00.574218   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5343 23:07:00.577627   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5344 23:07:00.581074   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5345 23:07:00.587994   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5346 23:07:00.591030   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 5347 23:07:00.594499   1  3  0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 5348 23:07:00.598070  Total UI for P1: 0, mck2ui 16

 5349 23:07:00.600948  best dqsien dly found for B0: ( 1,  2, 28)

 5350 23:07:00.604509   1  3  4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 5351 23:07:00.611193   1  3  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5352 23:07:00.615105  Total UI for P1: 0, mck2ui 16

 5353 23:07:00.618508  best dqsien dly found for B1: ( 1,  3,  2)

 5354 23:07:00.620887  best DQS0 dly(MCK, UI, PI) = (1, 2, 28)

 5355 23:07:00.624320  best DQS1 dly(MCK, UI, PI) = (1, 3, 2)

 5356 23:07:00.624439  

 5357 23:07:00.628124  best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)

 5358 23:07:00.631513  best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)

 5359 23:07:00.634230  [Gating] SW calibration Done

 5360 23:07:00.634348  ==

 5361 23:07:00.638380  Dram Type= 6, Freq= 0, CH_0, rank 1

 5362 23:07:00.641050  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5363 23:07:00.641166  ==

 5364 23:07:00.644572  RX Vref Scan: 0

 5365 23:07:00.644713  

 5366 23:07:00.644808  RX Vref 0 -> 0, step: 1

 5367 23:07:00.647561  

 5368 23:07:00.647671  RX Delay -80 -> 252, step: 8

 5369 23:07:00.654742  iDelay=208, Bit 0, Center 95 (0 ~ 191) 192

 5370 23:07:00.658286  iDelay=208, Bit 1, Center 99 (0 ~ 199) 200

 5371 23:07:00.661239  iDelay=208, Bit 2, Center 95 (0 ~ 191) 192

 5372 23:07:00.664984  iDelay=208, Bit 3, Center 95 (0 ~ 191) 192

 5373 23:07:00.668511  iDelay=208, Bit 4, Center 95 (0 ~ 191) 192

 5374 23:07:00.671442  iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192

 5375 23:07:00.674753  iDelay=208, Bit 6, Center 107 (8 ~ 207) 200

 5376 23:07:00.681516  iDelay=208, Bit 7, Center 103 (8 ~ 199) 192

 5377 23:07:00.684475  iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184

 5378 23:07:00.688166  iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192

 5379 23:07:00.691413  iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192

 5380 23:07:00.694841  iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192

 5381 23:07:00.697897  iDelay=208, Bit 12, Center 91 (0 ~ 183) 184

 5382 23:07:00.704339  iDelay=208, Bit 13, Center 95 (0 ~ 191) 192

 5383 23:07:00.707935  iDelay=208, Bit 14, Center 95 (0 ~ 191) 192

 5384 23:07:00.711251  iDelay=208, Bit 15, Center 95 (0 ~ 191) 192

 5385 23:07:00.711372  ==

 5386 23:07:00.714869  Dram Type= 6, Freq= 0, CH_0, rank 1

 5387 23:07:00.718251  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5388 23:07:00.718370  ==

 5389 23:07:00.721831  DQS Delay:

 5390 23:07:00.721942  DQS0 = 0, DQS1 = 0

 5391 23:07:00.722036  DQM Delay:

 5392 23:07:00.724746  DQM0 = 97, DQM1 = 88

 5393 23:07:00.724860  DQ Delay:

 5394 23:07:00.728023  DQ0 =95, DQ1 =99, DQ2 =95, DQ3 =95

 5395 23:07:00.731545  DQ4 =95, DQ5 =87, DQ6 =107, DQ7 =103

 5396 23:07:00.734640  DQ8 =83, DQ9 =79, DQ10 =87, DQ11 =79

 5397 23:07:00.738060  DQ12 =91, DQ13 =95, DQ14 =95, DQ15 =95

 5398 23:07:00.738178  

 5399 23:07:00.738273  

 5400 23:07:00.738368  ==

 5401 23:07:00.741853  Dram Type= 6, Freq= 0, CH_0, rank 1

 5402 23:07:00.748056  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5403 23:07:00.748191  ==

 5404 23:07:00.748289  

 5405 23:07:00.748384  

 5406 23:07:00.748473  	TX Vref Scan disable

 5407 23:07:00.751919   == TX Byte 0 ==

 5408 23:07:00.755064  Update DQ  dly =712 (2 ,5, 40)  DQ  OEN =(2 ,2)

 5409 23:07:00.761825  Update DQM dly =712 (2 ,5, 40)  DQM OEN =(2 ,2)

 5410 23:07:00.761957   == TX Byte 1 ==

 5411 23:07:00.764738  Update DQ  dly =709 (2 ,5, 37)  DQ  OEN =(2 ,2)

 5412 23:07:00.768407  Update DQM dly =709 (2 ,5, 37)  DQM OEN =(2 ,2)

 5413 23:07:00.772139  ==

 5414 23:07:00.774960  Dram Type= 6, Freq= 0, CH_0, rank 1

 5415 23:07:00.778285  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5416 23:07:00.778408  ==

 5417 23:07:00.778535  

 5418 23:07:00.778632  

 5419 23:07:00.782379  	TX Vref Scan disable

 5420 23:07:00.782524   == TX Byte 0 ==

 5421 23:07:00.788258  Update DQ  dly =712 (2 ,5, 40)  DQ  OEN =(2 ,2)

 5422 23:07:00.791892  Update DQM dly =712 (2 ,5, 40)  DQM OEN =(2 ,2)

 5423 23:07:00.792004   == TX Byte 1 ==

 5424 23:07:00.798525  Update DQ  dly =709 (2 ,5, 37)  DQ  OEN =(2 ,2)

 5425 23:07:00.801870  Update DQM dly =709 (2 ,5, 37)  DQM OEN =(2 ,2)

 5426 23:07:00.801986  

 5427 23:07:00.802082  [DATLAT]

 5428 23:07:00.805210  Freq=933, CH0 RK1

 5429 23:07:00.805322  

 5430 23:07:00.805415  DATLAT Default: 0xb

 5431 23:07:00.808783  0, 0xFFFF, sum = 0

 5432 23:07:00.808893  1, 0xFFFF, sum = 0

 5433 23:07:00.812519  2, 0xFFFF, sum = 0

 5434 23:07:00.812632  3, 0xFFFF, sum = 0

 5435 23:07:00.815533  4, 0xFFFF, sum = 0

 5436 23:07:00.815660  5, 0xFFFF, sum = 0

 5437 23:07:00.818251  6, 0xFFFF, sum = 0

 5438 23:07:00.818362  7, 0xFFFF, sum = 0

 5439 23:07:00.822021  8, 0xFFFF, sum = 0

 5440 23:07:00.822130  9, 0xFFFF, sum = 0

 5441 23:07:00.824912  10, 0x0, sum = 1

 5442 23:07:00.825025  11, 0x0, sum = 2

 5443 23:07:00.828411  12, 0x0, sum = 3

 5444 23:07:00.828524  13, 0x0, sum = 4

 5445 23:07:00.832031  best_step = 11

 5446 23:07:00.832139  

 5447 23:07:00.832236  ==

 5448 23:07:00.834744  Dram Type= 6, Freq= 0, CH_0, rank 1

 5449 23:07:00.838208  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5450 23:07:00.838322  ==

 5451 23:07:00.842458  RX Vref Scan: 0

 5452 23:07:00.842587  

 5453 23:07:00.842681  RX Vref 0 -> 0, step: 1

 5454 23:07:00.842778  

 5455 23:07:00.845525  RX Delay -61 -> 252, step: 4

 5456 23:07:00.852164  iDelay=199, Bit 0, Center 96 (3 ~ 190) 188

 5457 23:07:00.855581  iDelay=199, Bit 1, Center 96 (3 ~ 190) 188

 5458 23:07:00.858790  iDelay=199, Bit 2, Center 92 (-1 ~ 186) 188

 5459 23:07:00.862378  iDelay=199, Bit 3, Center 94 (-1 ~ 190) 192

 5460 23:07:00.865441  iDelay=199, Bit 4, Center 94 (3 ~ 186) 184

 5461 23:07:00.868741  iDelay=199, Bit 5, Center 84 (-9 ~ 178) 188

 5462 23:07:00.875530  iDelay=199, Bit 6, Center 104 (11 ~ 198) 188

 5463 23:07:00.879158  iDelay=199, Bit 7, Center 102 (11 ~ 194) 184

 5464 23:07:00.882327  iDelay=199, Bit 8, Center 82 (-5 ~ 170) 176

 5465 23:07:00.885687  iDelay=199, Bit 9, Center 78 (-9 ~ 166) 176

 5466 23:07:00.888945  iDelay=199, Bit 10, Center 88 (-1 ~ 178) 180

 5467 23:07:00.892883  iDelay=199, Bit 11, Center 78 (-9 ~ 166) 176

 5468 23:07:00.898952  iDelay=199, Bit 12, Center 92 (3 ~ 182) 180

 5469 23:07:00.902419  iDelay=199, Bit 13, Center 94 (7 ~ 182) 176

 5470 23:07:00.905491  iDelay=199, Bit 14, Center 98 (11 ~ 186) 176

 5471 23:07:00.908965  iDelay=199, Bit 15, Center 96 (7 ~ 186) 180

 5472 23:07:00.909076  ==

 5473 23:07:00.912447  Dram Type= 6, Freq= 0, CH_0, rank 1

 5474 23:07:00.915063  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5475 23:07:00.918780  ==

 5476 23:07:00.918886  DQS Delay:

 5477 23:07:00.918982  DQS0 = 0, DQS1 = 0

 5478 23:07:00.922176  DQM Delay:

 5479 23:07:00.922287  DQM0 = 95, DQM1 = 88

 5480 23:07:00.925650  DQ Delay:

 5481 23:07:00.928358  DQ0 =96, DQ1 =96, DQ2 =92, DQ3 =94

 5482 23:07:00.928468  DQ4 =94, DQ5 =84, DQ6 =104, DQ7 =102

 5483 23:07:00.931647  DQ8 =82, DQ9 =78, DQ10 =88, DQ11 =78

 5484 23:07:00.938560  DQ12 =92, DQ13 =94, DQ14 =98, DQ15 =96

 5485 23:07:00.938678  

 5486 23:07:00.938778  

 5487 23:07:00.945895  [DQSOSCAuto] RK1, (LSB)MR18= 0x1f0c, (MSB)MR19= 0x505, tDQSOscB0 = 418 ps tDQSOscB1 = 412 ps

 5488 23:07:00.948929  CH0 RK1: MR19=505, MR18=1F0C

 5489 23:07:00.955117  CH0_RK1: MR19=0x505, MR18=0x1F0C, DQSOSC=412, MR23=63, INC=63, DEC=42

 5490 23:07:00.958351  [RxdqsGatingPostProcess] freq 933

 5491 23:07:00.961961  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2

 5492 23:07:00.965078  best DQS0 dly(2T, 0.5T) = (0, 11)

 5493 23:07:00.968339  best DQS1 dly(2T, 0.5T) = (0, 11)

 5494 23:07:00.971983  best DQS0 P1 dly(2T, 0.5T) = (0, 15)

 5495 23:07:00.974867  best DQS1 P1 dly(2T, 0.5T) = (0, 15)

 5496 23:07:00.978559  best DQS0 dly(2T, 0.5T) = (0, 10)

 5497 23:07:00.982117  best DQS1 dly(2T, 0.5T) = (0, 11)

 5498 23:07:00.985502  best DQS0 P1 dly(2T, 0.5T) = (0, 14)

 5499 23:07:00.988893  best DQS1 P1 dly(2T, 0.5T) = (0, 15)

 5500 23:07:00.992143  Pre-setting of DQS Precalculation

 5501 23:07:00.994806  [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11

 5502 23:07:00.994914  ==

 5503 23:07:00.998874  Dram Type= 6, Freq= 0, CH_1, rank 0

 5504 23:07:01.001856  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5505 23:07:01.005056  ==

 5506 23:07:01.008609  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 5507 23:07:01.015117  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35

 5508 23:07:01.018354  [CA 0] Center 36 (6~67) winsize 62

 5509 23:07:01.021483  [CA 1] Center 36 (6~67) winsize 62

 5510 23:07:01.024863  [CA 2] Center 34 (4~64) winsize 61

 5511 23:07:01.028783  [CA 3] Center 33 (3~64) winsize 62

 5512 23:07:01.032027  [CA 4] Center 34 (4~65) winsize 62

 5513 23:07:01.035367  [CA 5] Center 33 (3~64) winsize 62

 5514 23:07:01.035484  

 5515 23:07:01.038662  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 5516 23:07:01.038772  

 5517 23:07:01.041995  [CATrainingPosCal] consider 1 rank data

 5518 23:07:01.045580  u2DelayCellTimex100 = 270/100 ps

 5519 23:07:01.048105  CA0 delay=36 (6~67),Diff = 3 PI (18 cell)

 5520 23:07:01.051781  CA1 delay=36 (6~67),Diff = 3 PI (18 cell)

 5521 23:07:01.055015  CA2 delay=34 (4~64),Diff = 1 PI (6 cell)

 5522 23:07:01.058705  CA3 delay=33 (3~64),Diff = 0 PI (0 cell)

 5523 23:07:01.064981  CA4 delay=34 (4~65),Diff = 1 PI (6 cell)

 5524 23:07:01.068316  CA5 delay=33 (3~64),Diff = 0 PI (0 cell)

 5525 23:07:01.068429  

 5526 23:07:01.071879  CA PerBit enable=1, Macro0, CA PI delay=33

 5527 23:07:01.071989  

 5528 23:07:01.074954  [CBTSetCACLKResult] CA Dly = 33

 5529 23:07:01.075061  CS Dly: 4 (0~35)

 5530 23:07:01.075160  ==

 5531 23:07:01.079527  Dram Type= 6, Freq= 0, CH_1, rank 1

 5532 23:07:01.081897  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5533 23:07:01.085005  ==

 5534 23:07:01.088927  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 5535 23:07:01.095055  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35

 5536 23:07:01.098737  [CA 0] Center 36 (6~67) winsize 62

 5537 23:07:01.101801  [CA 1] Center 36 (6~67) winsize 62

 5538 23:07:01.105474  [CA 2] Center 34 (4~64) winsize 61

 5539 23:07:01.108940  [CA 3] Center 33 (3~64) winsize 62

 5540 23:07:01.112369  [CA 4] Center 34 (4~65) winsize 62

 5541 23:07:01.115598  [CA 5] Center 32 (2~63) winsize 62

 5542 23:07:01.115705  

 5543 23:07:01.118559  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 5544 23:07:01.118670  

 5545 23:07:01.121986  [CATrainingPosCal] consider 2 rank data

 5546 23:07:01.125749  u2DelayCellTimex100 = 270/100 ps

 5547 23:07:01.129280  CA0 delay=36 (6~67),Diff = 3 PI (18 cell)

 5548 23:07:01.132238  CA1 delay=36 (6~67),Diff = 3 PI (18 cell)

 5549 23:07:01.136089  CA2 delay=34 (4~64),Diff = 1 PI (6 cell)

 5550 23:07:01.138845  CA3 delay=33 (3~64),Diff = 0 PI (0 cell)

 5551 23:07:01.142025  CA4 delay=34 (4~65),Diff = 1 PI (6 cell)

 5552 23:07:01.145385  CA5 delay=33 (3~63),Diff = 0 PI (0 cell)

 5553 23:07:01.148733  

 5554 23:07:01.152684  CA PerBit enable=1, Macro0, CA PI delay=33

 5555 23:07:01.152791  

 5556 23:07:01.155253  [CBTSetCACLKResult] CA Dly = 33

 5557 23:07:01.155363  CS Dly: 5 (0~37)

 5558 23:07:01.155456  

 5559 23:07:01.159007  ----->DramcWriteLeveling(PI) begin...

 5560 23:07:01.159118  ==

 5561 23:07:01.162299  Dram Type= 6, Freq= 0, CH_1, rank 0

 5562 23:07:01.166237  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5563 23:07:01.169337  ==

 5564 23:07:01.169427  Write leveling (Byte 0): 26 => 26

 5565 23:07:01.172952  Write leveling (Byte 1): 29 => 29

 5566 23:07:01.175670  DramcWriteLeveling(PI) end<-----

 5567 23:07:01.175783  

 5568 23:07:01.175850  ==

 5569 23:07:01.178717  Dram Type= 6, Freq= 0, CH_1, rank 0

 5570 23:07:01.185742  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5571 23:07:01.185854  ==

 5572 23:07:01.185942  [Gating] SW mode calibration

 5573 23:07:01.195777  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

 5574 23:07:01.199390  RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)

 5575 23:07:01.202358   0 14  0 | B1->B0 | 2f2f 3232 | 1 0 | (1 1) (0 0)

 5576 23:07:01.209027   0 14  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5577 23:07:01.213358   0 14  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5578 23:07:01.215514   0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5579 23:07:01.222630   0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5580 23:07:01.225513   0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5581 23:07:01.229018   0 14 24 | B1->B0 | 3333 3434 | 1 1 | (1 0) (1 1)

 5582 23:07:01.235699   0 14 28 | B1->B0 | 2f2f 2f2f | 1 1 | (1 0) (1 0)

 5583 23:07:01.239530   0 15  0 | B1->B0 | 2424 2a2a | 0 1 | (1 0) (1 0)

 5584 23:07:01.242732   0 15  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5585 23:07:01.249264   0 15  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5586 23:07:01.253154   0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5587 23:07:01.256153   0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5588 23:07:01.262663   0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5589 23:07:01.266076   0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5590 23:07:01.269126   0 15 28 | B1->B0 | 3333 3232 | 1 0 | (0 0) (1 1)

 5591 23:07:01.272063   1  0  0 | B1->B0 | 4141 4141 | 0 0 | (0 0) (0 0)

 5592 23:07:01.278994   1  0  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5593 23:07:01.282385   1  0  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5594 23:07:01.285819   1  0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5595 23:07:01.292507   1  0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5596 23:07:01.295656   1  0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5597 23:07:01.299507   1  0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5598 23:07:01.305842   1  0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 5599 23:07:01.309373   1  1  0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 5600 23:07:01.313099   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5601 23:07:01.319450   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5602 23:07:01.323259   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5603 23:07:01.326517   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5604 23:07:01.333053   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5605 23:07:01.335791   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5606 23:07:01.339563   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5607 23:07:01.342627   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5608 23:07:01.349151   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5609 23:07:01.353826   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5610 23:07:01.356062   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5611 23:07:01.362298   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5612 23:07:01.366019   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5613 23:07:01.369736   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5614 23:07:01.375877   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 5615 23:07:01.379557   1  3  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5616 23:07:01.382279  Total UI for P1: 0, mck2ui 16

 5617 23:07:01.386573  best dqsien dly found for B0: ( 1,  2, 28)

 5618 23:07:01.390164  Total UI for P1: 0, mck2ui 16

 5619 23:07:01.392479  best dqsien dly found for B1: ( 1,  2, 28)

 5620 23:07:01.395562  best DQS0 dly(MCK, UI, PI) = (1, 2, 28)

 5621 23:07:01.399175  best DQS1 dly(MCK, UI, PI) = (1, 2, 28)

 5622 23:07:01.399301  

 5623 23:07:01.402606  best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)

 5624 23:07:01.406034  best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)

 5625 23:07:01.409082  [Gating] SW calibration Done

 5626 23:07:01.409185  ==

 5627 23:07:01.412449  Dram Type= 6, Freq= 0, CH_1, rank 0

 5628 23:07:01.415796  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5629 23:07:01.418992  ==

 5630 23:07:01.419095  RX Vref Scan: 0

 5631 23:07:01.419188  

 5632 23:07:01.422677  RX Vref 0 -> 0, step: 1

 5633 23:07:01.422748  

 5634 23:07:01.425660  RX Delay -80 -> 252, step: 8

 5635 23:07:01.428855  iDelay=200, Bit 0, Center 99 (8 ~ 191) 184

 5636 23:07:01.432409  iDelay=200, Bit 1, Center 95 (0 ~ 191) 192

 5637 23:07:01.436464  iDelay=200, Bit 2, Center 87 (-8 ~ 183) 192

 5638 23:07:01.439020  iDelay=200, Bit 3, Center 95 (0 ~ 191) 192

 5639 23:07:01.442837  iDelay=200, Bit 4, Center 95 (0 ~ 191) 192

 5640 23:07:01.448749  iDelay=200, Bit 5, Center 103 (8 ~ 199) 192

 5641 23:07:01.452006  iDelay=200, Bit 6, Center 107 (16 ~ 199) 184

 5642 23:07:01.455728  iDelay=200, Bit 7, Center 95 (0 ~ 191) 192

 5643 23:07:01.458920  iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192

 5644 23:07:01.462346  iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192

 5645 23:07:01.465961  iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192

 5646 23:07:01.472562  iDelay=200, Bit 11, Center 83 (-16 ~ 183) 200

 5647 23:07:01.475534  iDelay=200, Bit 12, Center 95 (0 ~ 191) 192

 5648 23:07:01.478630  iDelay=200, Bit 13, Center 95 (0 ~ 191) 192

 5649 23:07:01.482335  iDelay=200, Bit 14, Center 95 (0 ~ 191) 192

 5650 23:07:01.485260  iDelay=200, Bit 15, Center 95 (0 ~ 191) 192

 5651 23:07:01.485343  ==

 5652 23:07:01.489653  Dram Type= 6, Freq= 0, CH_1, rank 0

 5653 23:07:01.496313  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5654 23:07:01.496397  ==

 5655 23:07:01.496481  DQS Delay:

 5656 23:07:01.498936  DQS0 = 0, DQS1 = 0

 5657 23:07:01.499018  DQM Delay:

 5658 23:07:01.499083  DQM0 = 97, DQM1 = 88

 5659 23:07:01.502010  DQ Delay:

 5660 23:07:01.505818  DQ0 =99, DQ1 =95, DQ2 =87, DQ3 =95

 5661 23:07:01.509729  DQ4 =95, DQ5 =103, DQ6 =107, DQ7 =95

 5662 23:07:01.512132  DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =83

 5663 23:07:01.515781  DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95

 5664 23:07:01.515862  

 5665 23:07:01.515927  

 5666 23:07:01.515986  ==

 5667 23:07:01.519079  Dram Type= 6, Freq= 0, CH_1, rank 0

 5668 23:07:01.522091  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5669 23:07:01.522174  ==

 5670 23:07:01.522238  

 5671 23:07:01.522298  

 5672 23:07:01.525733  	TX Vref Scan disable

 5673 23:07:01.525815   == TX Byte 0 ==

 5674 23:07:01.532438  Update DQ  dly =710 (2 ,5, 38)  DQ  OEN =(2 ,2)

 5675 23:07:01.535634  Update DQM dly =710 (2 ,5, 38)  DQM OEN =(2 ,2)

 5676 23:07:01.535717   == TX Byte 1 ==

 5677 23:07:01.542330  Update DQ  dly =712 (2 ,5, 40)  DQ  OEN =(2 ,2)

 5678 23:07:01.546060  Update DQM dly =712 (2 ,5, 40)  DQM OEN =(2 ,2)

 5679 23:07:01.546146  ==

 5680 23:07:01.549072  Dram Type= 6, Freq= 0, CH_1, rank 0

 5681 23:07:01.552799  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5682 23:07:01.552890  ==

 5683 23:07:01.552956  

 5684 23:07:01.553016  

 5685 23:07:01.555685  	TX Vref Scan disable

 5686 23:07:01.559261   == TX Byte 0 ==

 5687 23:07:01.562863  Update DQ  dly =709 (2 ,5, 37)  DQ  OEN =(2 ,2)

 5688 23:07:01.566630  Update DQM dly =709 (2 ,5, 37)  DQM OEN =(2 ,2)

 5689 23:07:01.569330   == TX Byte 1 ==

 5690 23:07:01.572792  Update DQ  dly =711 (2 ,5, 39)  DQ  OEN =(2 ,2)

 5691 23:07:01.575621  Update DQM dly =711 (2 ,5, 39)  DQM OEN =(2 ,2)

 5692 23:07:01.575731  

 5693 23:07:01.579094  [DATLAT]

 5694 23:07:01.579210  Freq=933, CH1 RK0

 5695 23:07:01.579279  

 5696 23:07:01.582459  DATLAT Default: 0xd

 5697 23:07:01.582555  0, 0xFFFF, sum = 0

 5698 23:07:01.586020  1, 0xFFFF, sum = 0

 5699 23:07:01.586114  2, 0xFFFF, sum = 0

 5700 23:07:01.590113  3, 0xFFFF, sum = 0

 5701 23:07:01.590204  4, 0xFFFF, sum = 0

 5702 23:07:01.592146  5, 0xFFFF, sum = 0

 5703 23:07:01.592238  6, 0xFFFF, sum = 0

 5704 23:07:01.596714  7, 0xFFFF, sum = 0

 5705 23:07:01.596802  8, 0xFFFF, sum = 0

 5706 23:07:01.599227  9, 0xFFFF, sum = 0

 5707 23:07:01.599317  10, 0x0, sum = 1

 5708 23:07:01.602422  11, 0x0, sum = 2

 5709 23:07:01.602532  12, 0x0, sum = 3

 5710 23:07:01.605614  13, 0x0, sum = 4

 5711 23:07:01.605732  best_step = 11

 5712 23:07:01.605798  

 5713 23:07:01.605859  ==

 5714 23:07:01.609364  Dram Type= 6, Freq= 0, CH_1, rank 0

 5715 23:07:01.616010  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5716 23:07:01.616146  ==

 5717 23:07:01.616216  RX Vref Scan: 1

 5718 23:07:01.616278  

 5719 23:07:01.618963  RX Vref 0 -> 0, step: 1

 5720 23:07:01.619045  

 5721 23:07:01.622286  RX Delay -61 -> 252, step: 4

 5722 23:07:01.622371  

 5723 23:07:01.626145  Set Vref, RX VrefLevel [Byte0]: 57

 5724 23:07:01.629562                           [Byte1]: 51

 5725 23:07:01.629645  

 5726 23:07:01.632345  Final RX Vref Byte 0 = 57 to rank0

 5727 23:07:01.636213  Final RX Vref Byte 1 = 51 to rank0

 5728 23:07:01.639209  Final RX Vref Byte 0 = 57 to rank1

 5729 23:07:01.642433  Final RX Vref Byte 1 = 51 to rank1==

 5730 23:07:01.646059  Dram Type= 6, Freq= 0, CH_1, rank 0

 5731 23:07:01.649826  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5732 23:07:01.649932  ==

 5733 23:07:01.652418  DQS Delay:

 5734 23:07:01.652515  DQS0 = 0, DQS1 = 0

 5735 23:07:01.652607  DQM Delay:

 5736 23:07:01.655825  DQM0 = 98, DQM1 = 91

 5737 23:07:01.655900  DQ Delay:

 5738 23:07:01.659408  DQ0 =102, DQ1 =92, DQ2 =88, DQ3 =98

 5739 23:07:01.663263  DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =94

 5740 23:07:01.666261  DQ8 =80, DQ9 =78, DQ10 =92, DQ11 =86

 5741 23:07:01.669460  DQ12 =98, DQ13 =98, DQ14 =100, DQ15 =96

 5742 23:07:01.669563  

 5743 23:07:01.669660  

 5744 23:07:01.679201  [DQSOSCAuto] RK0, (LSB)MR18= 0x16f3, (MSB)MR19= 0x504, tDQSOscB0 = 426 ps tDQSOscB1 = 414 ps

 5745 23:07:01.683215  CH1 RK0: MR19=504, MR18=16F3

 5746 23:07:01.685822  CH1_RK0: MR19=0x504, MR18=0x16F3, DQSOSC=414, MR23=63, INC=63, DEC=42

 5747 23:07:01.685926  

 5748 23:07:01.689255  ----->DramcWriteLeveling(PI) begin...

 5749 23:07:01.692356  ==

 5750 23:07:01.692458  Dram Type= 6, Freq= 0, CH_1, rank 1

 5751 23:07:01.699007  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5752 23:07:01.699094  ==

 5753 23:07:01.702991  Write leveling (Byte 0): 29 => 29

 5754 23:07:01.705916  Write leveling (Byte 1): 30 => 30

 5755 23:07:01.705992  DramcWriteLeveling(PI) end<-----

 5756 23:07:01.709065  

 5757 23:07:01.709167  ==

 5758 23:07:01.713300  Dram Type= 6, Freq= 0, CH_1, rank 1

 5759 23:07:01.715862  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5760 23:07:01.715965  ==

 5761 23:07:01.719734  [Gating] SW mode calibration

 5762 23:07:01.726408  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

 5763 23:07:01.729761  RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)

 5764 23:07:01.736062   0 14  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5765 23:07:01.739352   0 14  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5766 23:07:01.742748   0 14  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5767 23:07:01.749342   0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5768 23:07:01.753386   0 14 16 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)

 5769 23:07:01.756827   0 14 20 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)

 5770 23:07:01.762803   0 14 24 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (1 0)

 5771 23:07:01.766164   0 14 28 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)

 5772 23:07:01.769538   0 15  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5773 23:07:01.776162   0 15  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5774 23:07:01.779595   0 15  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5775 23:07:01.783292   0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5776 23:07:01.789449   0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5777 23:07:01.792811   0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5778 23:07:01.795857   0 15 24 | B1->B0 | 2c2c 3838 | 0 0 | (0 0) (0 0)

 5779 23:07:01.799339   0 15 28 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)

 5780 23:07:01.806133   1  0  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5781 23:07:01.809226   1  0  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5782 23:07:01.813050   1  0  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5783 23:07:01.819239   1  0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5784 23:07:01.822692   1  0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5785 23:07:01.825785   1  0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5786 23:07:01.833257   1  0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 5787 23:07:01.836520   1  0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 5788 23:07:01.839792   1  1  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5789 23:07:01.846094   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5790 23:07:01.849295   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5791 23:07:01.852908   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5792 23:07:01.859208   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5793 23:07:01.862623   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5794 23:07:01.865845   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5795 23:07:01.873103   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5796 23:07:01.876001   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5797 23:07:01.880068   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5798 23:07:01.886443   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5799 23:07:01.889144   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5800 23:07:01.892657   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5801 23:07:01.895908   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 5802 23:07:01.902467   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 5803 23:07:01.905944  Total UI for P1: 0, mck2ui 16

 5804 23:07:01.909193  best dqsien dly found for B0: ( 1,  2, 20)

 5805 23:07:01.912536   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 5806 23:07:01.916194   1  3  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5807 23:07:01.919634  Total UI for P1: 0, mck2ui 16

 5808 23:07:01.923163  best dqsien dly found for B1: ( 1,  2, 26)

 5809 23:07:01.927040  best DQS0 dly(MCK, UI, PI) = (1, 2, 20)

 5810 23:07:01.929270  best DQS1 dly(MCK, UI, PI) = (1, 2, 26)

 5811 23:07:01.932407  

 5812 23:07:01.935998  best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 20)

 5813 23:07:01.939689  best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)

 5814 23:07:01.942917  [Gating] SW calibration Done

 5815 23:07:01.943095  ==

 5816 23:07:01.946126  Dram Type= 6, Freq= 0, CH_1, rank 1

 5817 23:07:01.949417  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5818 23:07:01.949555  ==

 5819 23:07:01.949672  RX Vref Scan: 0

 5820 23:07:01.952289  

 5821 23:07:01.952414  RX Vref 0 -> 0, step: 1

 5822 23:07:01.952523  

 5823 23:07:01.955888  RX Delay -80 -> 252, step: 8

 5824 23:07:01.958887  iDelay=200, Bit 0, Center 95 (0 ~ 191) 192

 5825 23:07:01.963120  iDelay=200, Bit 1, Center 91 (-8 ~ 191) 200

 5826 23:07:01.966020  iDelay=200, Bit 2, Center 87 (-8 ~ 183) 192

 5827 23:07:01.972749  iDelay=200, Bit 3, Center 95 (0 ~ 191) 192

 5828 23:07:01.975850  iDelay=200, Bit 4, Center 95 (0 ~ 191) 192

 5829 23:07:01.979310  iDelay=200, Bit 5, Center 103 (8 ~ 199) 192

 5830 23:07:01.982349  iDelay=200, Bit 6, Center 103 (8 ~ 199) 192

 5831 23:07:01.985973  iDelay=200, Bit 7, Center 91 (0 ~ 183) 184

 5832 23:07:01.989287  iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192

 5833 23:07:01.995475  iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192

 5834 23:07:01.999476  iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192

 5835 23:07:02.002727  iDelay=200, Bit 11, Center 79 (-16 ~ 175) 192

 5836 23:07:02.006338  iDelay=200, Bit 12, Center 95 (0 ~ 191) 192

 5837 23:07:02.009118  iDelay=200, Bit 13, Center 99 (0 ~ 199) 200

 5838 23:07:02.012369  iDelay=200, Bit 14, Center 95 (0 ~ 191) 192

 5839 23:07:02.019474  iDelay=200, Bit 15, Center 95 (0 ~ 191) 192

 5840 23:07:02.019557  ==

 5841 23:07:02.022626  Dram Type= 6, Freq= 0, CH_1, rank 1

 5842 23:07:02.026251  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5843 23:07:02.026322  ==

 5844 23:07:02.026384  DQS Delay:

 5845 23:07:02.029624  DQS0 = 0, DQS1 = 0

 5846 23:07:02.029706  DQM Delay:

 5847 23:07:02.032486  DQM0 = 95, DQM1 = 88

 5848 23:07:02.032595  DQ Delay:

 5849 23:07:02.036155  DQ0 =95, DQ1 =91, DQ2 =87, DQ3 =95

 5850 23:07:02.039141  DQ4 =95, DQ5 =103, DQ6 =103, DQ7 =91

 5851 23:07:02.042472  DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =79

 5852 23:07:02.045624  DQ12 =95, DQ13 =99, DQ14 =95, DQ15 =95

 5853 23:07:02.045712  

 5854 23:07:02.045777  

 5855 23:07:02.045836  ==

 5856 23:07:02.049676  Dram Type= 6, Freq= 0, CH_1, rank 1

 5857 23:07:02.052541  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5858 23:07:02.052641  ==

 5859 23:07:02.056028  

 5860 23:07:02.056124  

 5861 23:07:02.056221  	TX Vref Scan disable

 5862 23:07:02.059315   == TX Byte 0 ==

 5863 23:07:02.063156  Update DQ  dly =712 (2 ,5, 40)  DQ  OEN =(2 ,2)

 5864 23:07:02.066123  Update DQM dly =712 (2 ,5, 40)  DQM OEN =(2 ,2)

 5865 23:07:02.069780   == TX Byte 1 ==

 5866 23:07:02.072302  Update DQ  dly =713 (2 ,5, 41)  DQ  OEN =(2 ,2)

 5867 23:07:02.075853  Update DQM dly =713 (2 ,5, 41)  DQM OEN =(2 ,2)

 5868 23:07:02.075959  ==

 5869 23:07:02.079518  Dram Type= 6, Freq= 0, CH_1, rank 1

 5870 23:07:02.086080  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5871 23:07:02.086161  ==

 5872 23:07:02.086225  

 5873 23:07:02.086284  

 5874 23:07:02.086341  	TX Vref Scan disable

 5875 23:07:02.089813   == TX Byte 0 ==

 5876 23:07:02.093322  Update DQ  dly =711 (2 ,5, 39)  DQ  OEN =(2 ,2)

 5877 23:07:02.096695  Update DQM dly =711 (2 ,5, 39)  DQM OEN =(2 ,2)

 5878 23:07:02.099852   == TX Byte 1 ==

 5879 23:07:02.103527  Update DQ  dly =712 (2 ,5, 40)  DQ  OEN =(2 ,2)

 5880 23:07:02.106600  Update DQM dly =712 (2 ,5, 40)  DQM OEN =(2 ,2)

 5881 23:07:02.110002  

 5882 23:07:02.110117  [DATLAT]

 5883 23:07:02.110210  Freq=933, CH1 RK1

 5884 23:07:02.110299  

 5885 23:07:02.113097  DATLAT Default: 0xb

 5886 23:07:02.113175  0, 0xFFFF, sum = 0

 5887 23:07:02.116965  1, 0xFFFF, sum = 0

 5888 23:07:02.117040  2, 0xFFFF, sum = 0

 5889 23:07:02.119981  3, 0xFFFF, sum = 0

 5890 23:07:02.120089  4, 0xFFFF, sum = 0

 5891 23:07:02.123158  5, 0xFFFF, sum = 0

 5892 23:07:02.126913  6, 0xFFFF, sum = 0

 5893 23:07:02.126994  7, 0xFFFF, sum = 0

 5894 23:07:02.130330  8, 0xFFFF, sum = 0

 5895 23:07:02.130438  9, 0xFFFF, sum = 0

 5896 23:07:02.133731  10, 0x0, sum = 1

 5897 23:07:02.133838  11, 0x0, sum = 2

 5898 23:07:02.133930  12, 0x0, sum = 3

 5899 23:07:02.136344  13, 0x0, sum = 4

 5900 23:07:02.136442  best_step = 11

 5901 23:07:02.136529  

 5902 23:07:02.136623  ==

 5903 23:07:02.139676  Dram Type= 6, Freq= 0, CH_1, rank 1

 5904 23:07:02.147275  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5905 23:07:02.147386  ==

 5906 23:07:02.147477  RX Vref Scan: 0

 5907 23:07:02.147570  

 5908 23:07:02.150347  RX Vref 0 -> 0, step: 1

 5909 23:07:02.150483  

 5910 23:07:02.153218  RX Delay -61 -> 252, step: 4

 5911 23:07:02.156369  iDelay=199, Bit 0, Center 98 (7 ~ 190) 184

 5912 23:07:02.160010  iDelay=199, Bit 1, Center 90 (-1 ~ 182) 184

 5913 23:07:02.166865  iDelay=199, Bit 2, Center 86 (-5 ~ 178) 184

 5914 23:07:02.170105  iDelay=199, Bit 3, Center 94 (3 ~ 186) 184

 5915 23:07:02.173915  iDelay=199, Bit 4, Center 98 (7 ~ 190) 184

 5916 23:07:02.177095  iDelay=199, Bit 5, Center 106 (15 ~ 198) 184

 5917 23:07:02.180064  iDelay=199, Bit 6, Center 102 (11 ~ 194) 184

 5918 23:07:02.183819  iDelay=199, Bit 7, Center 92 (3 ~ 182) 180

 5919 23:07:02.190389  iDelay=199, Bit 8, Center 80 (-13 ~ 174) 188

 5920 23:07:02.193848  iDelay=199, Bit 9, Center 78 (-13 ~ 170) 184

 5921 23:07:02.197182  iDelay=199, Bit 10, Center 88 (-5 ~ 182) 188

 5922 23:07:02.199869  iDelay=199, Bit 11, Center 82 (-9 ~ 174) 184

 5923 23:07:02.203157  iDelay=199, Bit 12, Center 96 (7 ~ 186) 180

 5924 23:07:02.210150  iDelay=199, Bit 13, Center 96 (3 ~ 190) 188

 5925 23:07:02.213049  iDelay=199, Bit 14, Center 98 (7 ~ 190) 184

 5926 23:07:02.216433  iDelay=199, Bit 15, Center 100 (11 ~ 190) 180

 5927 23:07:02.216517  ==

 5928 23:07:02.219732  Dram Type= 6, Freq= 0, CH_1, rank 1

 5929 23:07:02.223084  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5930 23:07:02.223172  ==

 5931 23:07:02.226862  DQS Delay:

 5932 23:07:02.226944  DQS0 = 0, DQS1 = 0

 5933 23:07:02.227009  DQM Delay:

 5934 23:07:02.229951  DQM0 = 95, DQM1 = 89

 5935 23:07:02.230034  DQ Delay:

 5936 23:07:02.233159  DQ0 =98, DQ1 =90, DQ2 =86, DQ3 =94

 5937 23:07:02.236581  DQ4 =98, DQ5 =106, DQ6 =102, DQ7 =92

 5938 23:07:02.240303  DQ8 =80, DQ9 =78, DQ10 =88, DQ11 =82

 5939 23:07:02.243164  DQ12 =96, DQ13 =96, DQ14 =98, DQ15 =100

 5940 23:07:02.243247  

 5941 23:07:02.243312  

 5942 23:07:02.253978  [DQSOSCAuto] RK1, (LSB)MR18= 0xc15, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 418 ps

 5943 23:07:02.256712  CH1 RK1: MR19=505, MR18=C15

 5944 23:07:02.260198  CH1_RK1: MR19=0x505, MR18=0xC15, DQSOSC=415, MR23=63, INC=62, DEC=41

 5945 23:07:02.263207  [RxdqsGatingPostProcess] freq 933

 5946 23:07:02.270375  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2

 5947 23:07:02.272968  best DQS0 dly(2T, 0.5T) = (0, 10)

 5948 23:07:02.276537  best DQS1 dly(2T, 0.5T) = (0, 10)

 5949 23:07:02.280157  best DQS0 P1 dly(2T, 0.5T) = (0, 14)

 5950 23:07:02.283289  best DQS1 P1 dly(2T, 0.5T) = (0, 14)

 5951 23:07:02.286860  best DQS0 dly(2T, 0.5T) = (0, 10)

 5952 23:07:02.286944  best DQS1 dly(2T, 0.5T) = (0, 10)

 5953 23:07:02.289923  best DQS0 P1 dly(2T, 0.5T) = (0, 14)

 5954 23:07:02.294190  best DQS1 P1 dly(2T, 0.5T) = (0, 14)

 5955 23:07:02.296640  Pre-setting of DQS Precalculation

 5956 23:07:02.303512  [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11

 5957 23:07:02.309910  sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3

 5958 23:07:02.316650  calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464

 5959 23:07:02.316737  

 5960 23:07:02.316804  

 5961 23:07:02.320158  [Calibration Summary] 1866 Mbps

 5962 23:07:02.320232  CH 0, Rank 0

 5963 23:07:02.323342  SW Impedance     : PASS

 5964 23:07:02.326958  DUTY Scan        : NO K

 5965 23:07:02.327031  ZQ Calibration   : PASS

 5966 23:07:02.329716  Jitter Meter     : NO K

 5967 23:07:02.333201  CBT Training     : PASS

 5968 23:07:02.333299  Write leveling   : PASS

 5969 23:07:02.337022  RX DQS gating    : PASS

 5970 23:07:02.339833  RX DQ/DQS(RDDQC) : PASS

 5971 23:07:02.339908  TX DQ/DQS        : PASS

 5972 23:07:02.343858  RX DATLAT        : PASS

 5973 23:07:02.346947  RX DQ/DQS(Engine): PASS

 5974 23:07:02.347030  TX OE            : NO K

 5975 23:07:02.349832  All Pass.

 5976 23:07:02.349915  

 5977 23:07:02.349979  CH 0, Rank 1

 5978 23:07:02.353361  SW Impedance     : PASS

 5979 23:07:02.353445  DUTY Scan        : NO K

 5980 23:07:02.357164  ZQ Calibration   : PASS

 5981 23:07:02.360173  Jitter Meter     : NO K

 5982 23:07:02.360255  CBT Training     : PASS

 5983 23:07:02.363556  Write leveling   : PASS

 5984 23:07:02.363639  RX DQS gating    : PASS

 5985 23:07:02.367248  RX DQ/DQS(RDDQC) : PASS

 5986 23:07:02.370900  TX DQ/DQS        : PASS

 5987 23:07:02.370983  RX DATLAT        : PASS

 5988 23:07:02.373211  RX DQ/DQS(Engine): PASS

 5989 23:07:02.377359  TX OE            : NO K

 5990 23:07:02.377448  All Pass.

 5991 23:07:02.377513  

 5992 23:07:02.377574  CH 1, Rank 0

 5993 23:07:02.380281  SW Impedance     : PASS

 5994 23:07:02.383443  DUTY Scan        : NO K

 5995 23:07:02.383526  ZQ Calibration   : PASS

 5996 23:07:02.386668  Jitter Meter     : NO K

 5997 23:07:02.390240  CBT Training     : PASS

 5998 23:07:02.390323  Write leveling   : PASS

 5999 23:07:02.393315  RX DQS gating    : PASS

 6000 23:07:02.397423  RX DQ/DQS(RDDQC) : PASS

 6001 23:07:02.397507  TX DQ/DQS        : PASS

 6002 23:07:02.400312  RX DATLAT        : PASS

 6003 23:07:02.400395  RX DQ/DQS(Engine): PASS

 6004 23:07:02.404425  TX OE            : NO K

 6005 23:07:02.404525  All Pass.

 6006 23:07:02.404604  

 6007 23:07:02.407079  CH 1, Rank 1

 6008 23:07:02.407161  SW Impedance     : PASS

 6009 23:07:02.410061  DUTY Scan        : NO K

 6010 23:07:02.414079  ZQ Calibration   : PASS

 6011 23:07:02.414161  Jitter Meter     : NO K

 6012 23:07:02.416869  CBT Training     : PASS

 6013 23:07:02.420192  Write leveling   : PASS

 6014 23:07:02.420274  RX DQS gating    : PASS

 6015 23:07:02.423767  RX DQ/DQS(RDDQC) : PASS

 6016 23:07:02.427282  TX DQ/DQS        : PASS

 6017 23:07:02.427366  RX DATLAT        : PASS

 6018 23:07:02.430993  RX DQ/DQS(Engine): PASS

 6019 23:07:02.434009  TX OE            : NO K

 6020 23:07:02.434108  All Pass.

 6021 23:07:02.434177  

 6022 23:07:02.434239  DramC Write-DBI off

 6023 23:07:02.437291  	PER_BANK_REFRESH: Hybrid Mode

 6024 23:07:02.440156  TX_TRACKING: ON

 6025 23:07:02.447095  [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0

 6026 23:07:02.450052  [FAST_K] Save calibration result to emmc

 6027 23:07:02.456952  dramc_set_vcore_voltage set vcore to 650000

 6028 23:07:02.457077  Read voltage for 400, 6

 6029 23:07:02.457142  Vio18 = 0

 6030 23:07:02.460422  Vcore = 650000

 6031 23:07:02.460505  Vdram = 0

 6032 23:07:02.460570  Vddq = 0

 6033 23:07:02.463708  Vmddr = 0

 6034 23:07:02.467333  [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0

 6035 23:07:02.473635  [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0

 6036 23:07:02.473747  MEM_TYPE=3, freq_sel=20

 6037 23:07:02.476592  sv_algorithm_assistance_LP4_800 

 6038 23:07:02.483437  ============ PULL DRAM RESETB DOWN ============

 6039 23:07:02.487008  ========== PULL DRAM RESETB DOWN end =========

 6040 23:07:02.490262  [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2

 6041 23:07:02.493681  =================================== 

 6042 23:07:02.497376  LPDDR4 DRAM CONFIGURATION

 6043 23:07:02.500622  =================================== 

 6044 23:07:02.500705  EX_ROW_EN[0]    = 0x0

 6045 23:07:02.504387  EX_ROW_EN[1]    = 0x0

 6046 23:07:02.507232  LP4Y_EN      = 0x0

 6047 23:07:02.507314  WORK_FSP     = 0x0

 6048 23:07:02.510487  WL           = 0x2

 6049 23:07:02.510570  RL           = 0x2

 6050 23:07:02.513845  BL           = 0x2

 6051 23:07:02.513927  RPST         = 0x0

 6052 23:07:02.517195  RD_PRE       = 0x0

 6053 23:07:02.517277  WR_PRE       = 0x1

 6054 23:07:02.520487  WR_PST       = 0x0

 6055 23:07:02.520569  DBI_WR       = 0x0

 6056 23:07:02.523492  DBI_RD       = 0x0

 6057 23:07:02.523573  OTF          = 0x1

 6058 23:07:02.527405  =================================== 

 6059 23:07:02.530769  =================================== 

 6060 23:07:02.533806  ANA top config

 6061 23:07:02.537479  =================================== 

 6062 23:07:02.537563  DLL_ASYNC_EN            =  0

 6063 23:07:02.540480  ALL_SLAVE_EN            =  1

 6064 23:07:02.543693  NEW_RANK_MODE           =  1

 6065 23:07:02.547452  DLL_IDLE_MODE           =  1

 6066 23:07:02.547580  LP45_APHY_COMB_EN       =  1

 6067 23:07:02.550890  TX_ODT_DIS              =  1

 6068 23:07:02.553786  NEW_8X_MODE             =  1

 6069 23:07:02.557285  =================================== 

 6070 23:07:02.560900  =================================== 

 6071 23:07:02.564056  data_rate                  =  800

 6072 23:07:02.567469  CKR                        = 1

 6073 23:07:02.570303  DQ_P2S_RATIO               = 4

 6074 23:07:02.574217  =================================== 

 6075 23:07:02.574300  CA_P2S_RATIO               = 4

 6076 23:07:02.577508  DQ_CA_OPEN                 = 0

 6077 23:07:02.580805  DQ_SEMI_OPEN               = 1

 6078 23:07:02.583853  CA_SEMI_OPEN               = 1

 6079 23:07:02.587158  CA_FULL_RATE               = 0

 6080 23:07:02.587240  DQ_CKDIV4_EN               = 0

 6081 23:07:02.591084  CA_CKDIV4_EN               = 1

 6082 23:07:02.593955  CA_PREDIV_EN               = 0

 6083 23:07:02.597943  PH8_DLY                    = 0

 6084 23:07:02.600899  SEMI_OPEN_CA_PICK_MCK_RATIO= 4

 6085 23:07:02.603970  DQ_AAMCK_DIV               = 0

 6086 23:07:02.604054  CA_AAMCK_DIV               = 0

 6087 23:07:02.607344  CA_ADMCK_DIV               = 4

 6088 23:07:02.610820  DQ_TRACK_CA_EN             = 0

 6089 23:07:02.614483  CA_PICK                    = 800

 6090 23:07:02.617074  CA_MCKIO                   = 400

 6091 23:07:02.621019  MCKIO_SEMI                 = 400

 6092 23:07:02.623834  PLL_FREQ                   = 3016

 6093 23:07:02.623917  DQ_UI_PI_RATIO             = 32

 6094 23:07:02.627366  CA_UI_PI_RATIO             = 32

 6095 23:07:02.630352  =================================== 

 6096 23:07:02.634071  =================================== 

 6097 23:07:02.637310  memory_type:LPDDR4         

 6098 23:07:02.640280  GP_NUM     : 10       

 6099 23:07:02.640364  SRAM_EN    : 1       

 6100 23:07:02.644070  MD32_EN    : 0       

 6101 23:07:02.647052  =================================== 

 6102 23:07:02.650355  [ANA_INIT] >>>>>>>>>>>>>> 

 6103 23:07:02.650476  <<<<<< [CONFIGURE PHASE]: ANA_TX

 6104 23:07:02.654452  >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL

 6105 23:07:02.657751  =================================== 

 6106 23:07:02.661302  data_rate = 800,PCW = 0X7400

 6107 23:07:02.664205  =================================== 

 6108 23:07:02.667416  <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL

 6109 23:07:02.673880  >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 6110 23:07:02.684264  WARN: tr->DQ_AAMCK_DIV=  0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 6111 23:07:02.690559  >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2

 6112 23:07:02.694704  >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL

 6113 23:07:02.697752  <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL

 6114 23:07:02.697837  [ANA_INIT] flow start 

 6115 23:07:02.701238  [ANA_INIT] PLL >>>>>>>> 

 6116 23:07:02.704712  [ANA_INIT] PLL <<<<<<<< 

 6117 23:07:02.704813  [ANA_INIT] MIDPI >>>>>>>> 

 6118 23:07:02.707505  [ANA_INIT] MIDPI <<<<<<<< 

 6119 23:07:02.710739  [ANA_INIT] DLL >>>>>>>> 

 6120 23:07:02.710822  [ANA_INIT] flow end 

 6121 23:07:02.717378  ============ LP4 DIFF to SE enter ============

 6122 23:07:02.721339  ============ LP4 DIFF to SE exit  ============

 6123 23:07:02.724252  [ANA_INIT] <<<<<<<<<<<<< 

 6124 23:07:02.728023  [Flow] Enable top DCM control >>>>> 

 6125 23:07:02.730748  [Flow] Enable top DCM control <<<<< 

 6126 23:07:02.730832  Enable DLL master slave shuffle 

 6127 23:07:02.737405  ============================================================== 

 6128 23:07:02.741086  Gating Mode config

 6129 23:07:02.744217  ============================================================== 

 6130 23:07:02.747666  Config description: 

 6131 23:07:02.757771  RX_GATING_MODE        0: Pulse Mode      1: Burst Mode(8UI)        2: Burst Mode(7UI)  3: Original Burst Mode

 6132 23:07:02.764551  RX_GATING_TRACK_MODE  0: Valid DLY Mode  1: Valid Mode (-like) 2: FIFO mode

 6133 23:07:02.767966  SELPH_MODE            0: By rank         1: By Phase 

 6134 23:07:02.774293  ============================================================== 

 6135 23:07:02.777586  GAT_TRACK_EN                 =  0

 6136 23:07:02.781192  RX_GATING_MODE               =  2

 6137 23:07:02.781277  RX_GATING_TRACK_MODE         =  2

 6138 23:07:02.784211  SELPH_MODE                   =  1

 6139 23:07:02.787904  PICG_EARLY_EN                =  1

 6140 23:07:02.791250  VALID_LAT_VALUE              =  1

 6141 23:07:02.798382  ============================================================== 

 6142 23:07:02.801814  Enter into Gating configuration >>>> 

 6143 23:07:02.804822  Exit from Gating configuration <<<< 

 6144 23:07:02.807997  Enter into  DVFS_PRE_config >>>>> 

 6145 23:07:02.818118  Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. 

 6146 23:07:02.821346  Exit from  DVFS_PRE_config <<<<< 

 6147 23:07:02.825302  Enter into PICG configuration >>>> 

 6148 23:07:02.828615  Exit from PICG configuration <<<< 

 6149 23:07:02.831249  [RX_INPUT] configuration >>>>> 

 6150 23:07:02.831333  [RX_INPUT] configuration <<<<< 

 6151 23:07:02.838968  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>

 6152 23:07:02.844480  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<

 6153 23:07:02.847993  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>

 6154 23:07:02.854732  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<

 6155 23:07:02.861505  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>

 6156 23:07:02.867835  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<

 6157 23:07:02.871449  [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 

 6158 23:07:02.875208  [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 

 6159 23:07:02.881363  [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 

 6160 23:07:02.884834  [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 

 6161 23:07:02.888100  [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 

 6162 23:07:02.891473  [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2

 6163 23:07:02.894989  =================================== 

 6164 23:07:02.898527  LPDDR4 DRAM CONFIGURATION

 6165 23:07:02.901806  =================================== 

 6166 23:07:02.905035  EX_ROW_EN[0]    = 0x0

 6167 23:07:02.905118  EX_ROW_EN[1]    = 0x0

 6168 23:07:02.908984  LP4Y_EN      = 0x0

 6169 23:07:02.909067  WORK_FSP     = 0x0

 6170 23:07:02.911381  WL           = 0x2

 6171 23:07:02.911463  RL           = 0x2

 6172 23:07:02.915424  BL           = 0x2

 6173 23:07:02.915506  RPST         = 0x0

 6174 23:07:02.917950  RD_PRE       = 0x0

 6175 23:07:02.918057  WR_PRE       = 0x1

 6176 23:07:02.921796  WR_PST       = 0x0

 6177 23:07:02.925502  DBI_WR       = 0x0

 6178 23:07:02.925584  DBI_RD       = 0x0

 6179 23:07:02.925648  OTF          = 0x1

 6180 23:07:02.928590  =================================== 

 6181 23:07:02.935183  [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 

 6182 23:07:02.938942  [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 

 6183 23:07:02.941907  [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2

 6184 23:07:02.944979  =================================== 

 6185 23:07:02.948623  LPDDR4 DRAM CONFIGURATION

 6186 23:07:02.951589  =================================== 

 6187 23:07:02.955311  EX_ROW_EN[0]    = 0x10

 6188 23:07:02.955393  EX_ROW_EN[1]    = 0x0

 6189 23:07:02.958749  LP4Y_EN      = 0x0

 6190 23:07:02.958831  WORK_FSP     = 0x0

 6191 23:07:02.961851  WL           = 0x2

 6192 23:07:02.961956  RL           = 0x2

 6193 23:07:02.964938  BL           = 0x2

 6194 23:07:02.965020  RPST         = 0x0

 6195 23:07:02.968477  RD_PRE       = 0x0

 6196 23:07:02.968559  WR_PRE       = 0x1

 6197 23:07:02.971952  WR_PST       = 0x0

 6198 23:07:02.972034  DBI_WR       = 0x0

 6199 23:07:02.975459  DBI_RD       = 0x0

 6200 23:07:02.975542  OTF          = 0x1

 6201 23:07:02.978057  =================================== 

 6202 23:07:02.985224  [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit

 6203 23:07:02.989358  nWR fixed to 30

 6204 23:07:02.993078  [ModeRegInit_LP4] CH0 RK0

 6205 23:07:02.993161  [ModeRegInit_LP4] CH0 RK1

 6206 23:07:02.996384  [ModeRegInit_LP4] CH1 RK0

 6207 23:07:02.999369  [ModeRegInit_LP4] CH1 RK1

 6208 23:07:02.999451  match AC timing 19

 6209 23:07:03.006229  dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1

 6210 23:07:03.009266  SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON

 6211 23:07:03.013601  [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8

 6212 23:07:03.019887  [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17

 6213 23:07:03.023009  [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)

 6214 23:07:03.023093  ==

 6215 23:07:03.026152  Dram Type= 6, Freq= 0, CH_0, rank 0

 6216 23:07:03.029605  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6217 23:07:03.029688  ==

 6218 23:07:03.036859  pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0

 6219 23:07:03.043392  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35

 6220 23:07:03.046335  [CA 0] Center 36 (8~64) winsize 57

 6221 23:07:03.050018  [CA 1] Center 36 (8~64) winsize 57

 6222 23:07:03.050099  [CA 2] Center 36 (8~64) winsize 57

 6223 23:07:03.053137  [CA 3] Center 36 (8~64) winsize 57

 6224 23:07:03.056220  [CA 4] Center 36 (8~64) winsize 57

 6225 23:07:03.059551  [CA 5] Center 36 (8~64) winsize 57

 6226 23:07:03.059635  

 6227 23:07:03.063070  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 6228 23:07:03.066539  

 6229 23:07:03.069374  [CATrainingPosCal] consider 1 rank data

 6230 23:07:03.069456  u2DelayCellTimex100 = 270/100 ps

 6231 23:07:03.076308  CA0 delay=36 (8~64),Diff = 0 PI (0 cell)

 6232 23:07:03.079314  CA1 delay=36 (8~64),Diff = 0 PI (0 cell)

 6233 23:07:03.082907  CA2 delay=36 (8~64),Diff = 0 PI (0 cell)

 6234 23:07:03.086521  CA3 delay=36 (8~64),Diff = 0 PI (0 cell)

 6235 23:07:03.089881  CA4 delay=36 (8~64),Diff = 0 PI (0 cell)

 6236 23:07:03.092674  CA5 delay=36 (8~64),Diff = 0 PI (0 cell)

 6237 23:07:03.092756  

 6238 23:07:03.096077  CA PerBit enable=1, Macro0, CA PI delay=36

 6239 23:07:03.096159  

 6240 23:07:03.099883  [CBTSetCACLKResult] CA Dly = 36

 6241 23:07:03.102643  CS Dly: 1 (0~32)

 6242 23:07:03.102725  ==

 6243 23:07:03.106257  Dram Type= 6, Freq= 0, CH_0, rank 1

 6244 23:07:03.109654  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6245 23:07:03.109738  ==

 6246 23:07:03.112764  pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0

 6247 23:07:03.119430  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35

 6248 23:07:03.122759  [CA 0] Center 36 (8~64) winsize 57

 6249 23:07:03.126163  [CA 1] Center 36 (8~64) winsize 57

 6250 23:07:03.129927  [CA 2] Center 36 (8~64) winsize 57

 6251 23:07:03.132781  [CA 3] Center 36 (8~64) winsize 57

 6252 23:07:03.136417  [CA 4] Center 36 (8~64) winsize 57

 6253 23:07:03.139366  [CA 5] Center 36 (8~64) winsize 57

 6254 23:07:03.139448  

 6255 23:07:03.142876  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 6256 23:07:03.142986  

 6257 23:07:03.146179  [CATrainingPosCal] consider 2 rank data

 6258 23:07:03.149711  u2DelayCellTimex100 = 270/100 ps

 6259 23:07:03.153100  CA0 delay=36 (8~64),Diff = 0 PI (0 cell)

 6260 23:07:03.156425  CA1 delay=36 (8~64),Diff = 0 PI (0 cell)

 6261 23:07:03.159529  CA2 delay=36 (8~64),Diff = 0 PI (0 cell)

 6262 23:07:03.163177  CA3 delay=36 (8~64),Diff = 0 PI (0 cell)

 6263 23:07:03.166245  CA4 delay=36 (8~64),Diff = 0 PI (0 cell)

 6264 23:07:03.169520  CA5 delay=36 (8~64),Diff = 0 PI (0 cell)

 6265 23:07:03.173008  

 6266 23:07:03.176186  CA PerBit enable=1, Macro0, CA PI delay=36

 6267 23:07:03.176268  

 6268 23:07:03.179922  [CBTSetCACLKResult] CA Dly = 36

 6269 23:07:03.180006  CS Dly: 1 (0~32)

 6270 23:07:03.180075  

 6271 23:07:03.183252  ----->DramcWriteLeveling(PI) begin...

 6272 23:07:03.183336  ==

 6273 23:07:03.186286  Dram Type= 6, Freq= 0, CH_0, rank 0

 6274 23:07:03.190043  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6275 23:07:03.190157  ==

 6276 23:07:03.193859  Write leveling (Byte 0): 40 => 8

 6277 23:07:03.196788  Write leveling (Byte 1): 32 => 0

 6278 23:07:03.200201  DramcWriteLeveling(PI) end<-----

 6279 23:07:03.200284  

 6280 23:07:03.200350  ==

 6281 23:07:03.203461  Dram Type= 6, Freq= 0, CH_0, rank 0

 6282 23:07:03.206789  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6283 23:07:03.210624  ==

 6284 23:07:03.210706  [Gating] SW mode calibration

 6285 23:07:03.216311  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1

 6286 23:07:03.223472  RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)

 6287 23:07:03.226984   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6288 23:07:03.232901   0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6289 23:07:03.237081   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6290 23:07:03.239984   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6291 23:07:03.247537   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6292 23:07:03.250249   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6293 23:07:03.253233   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6294 23:07:03.259695   0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6295 23:07:03.263080   0 15  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6296 23:07:03.267089  Total UI for P1: 0, mck2ui 16

 6297 23:07:03.269728  best dqsien dly found for B0: ( 0, 14, 24)

 6298 23:07:03.273622  Total UI for P1: 0, mck2ui 16

 6299 23:07:03.276849  best dqsien dly found for B1: ( 0, 14, 24)

 6300 23:07:03.280032  best DQS0 dly(MCK, UI, PI) = (0, 14, 24)

 6301 23:07:03.283883  best DQS1 dly(MCK, UI, PI) = (0, 14, 24)

 6302 23:07:03.283966  

 6303 23:07:03.286323  best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6304 23:07:03.290287  best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6305 23:07:03.293418  [Gating] SW calibration Done

 6306 23:07:03.293499  ==

 6307 23:07:03.296364  Dram Type= 6, Freq= 0, CH_0, rank 0

 6308 23:07:03.300054  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6309 23:07:03.300137  ==

 6310 23:07:03.303523  RX Vref Scan: 0

 6311 23:07:03.303616  

 6312 23:07:03.306566  RX Vref 0 -> 0, step: 1

 6313 23:07:03.306647  

 6314 23:07:03.306711  RX Delay -410 -> 252, step: 16

 6315 23:07:03.313161  iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480

 6316 23:07:03.316628  iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512

 6317 23:07:03.319944  iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496

 6318 23:07:03.323261  iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496

 6319 23:07:03.330047  iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480

 6320 23:07:03.333401  iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496

 6321 23:07:03.336833  iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496

 6322 23:07:03.340385  iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496

 6323 23:07:03.346547  iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496

 6324 23:07:03.349965  iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496

 6325 23:07:03.353413  iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496

 6326 23:07:03.356681  iDelay=230, Bit 11, Center -43 (-282 ~ 197) 480

 6327 23:07:03.363139  iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496

 6328 23:07:03.366676  iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496

 6329 23:07:03.369962  iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496

 6330 23:07:03.376582  iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496

 6331 23:07:03.376665  ==

 6332 23:07:03.380082  Dram Type= 6, Freq= 0, CH_0, rank 0

 6333 23:07:03.383572  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6334 23:07:03.383655  ==

 6335 23:07:03.383719  DQS Delay:

 6336 23:07:03.386610  DQS0 = 35, DQS1 = 51

 6337 23:07:03.386691  DQM Delay:

 6338 23:07:03.390053  DQM0 = 7, DQM1 = 11

 6339 23:07:03.390133  DQ Delay:

 6340 23:07:03.393500  DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =0

 6341 23:07:03.396626  DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16

 6342 23:07:03.400039  DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8

 6343 23:07:03.403618  DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16

 6344 23:07:03.403700  

 6345 23:07:03.403763  

 6346 23:07:03.403822  ==

 6347 23:07:03.406313  Dram Type= 6, Freq= 0, CH_0, rank 0

 6348 23:07:03.409860  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6349 23:07:03.409942  ==

 6350 23:07:03.410006  

 6351 23:07:03.410065  

 6352 23:07:03.413459  	TX Vref Scan disable

 6353 23:07:03.413541   == TX Byte 0 ==

 6354 23:07:03.420018  Update DQ  dly =580 (4 ,2, 4)  DQ  OEN =(3 ,3)

 6355 23:07:03.423124  Update DQM dly =580 (4 ,2, 4)  DQM OEN =(3 ,3)

 6356 23:07:03.423205   == TX Byte 1 ==

 6357 23:07:03.430072  Update DQ  dly =572 (4 ,1, 28)  DQ  OEN =(3 ,2)

 6358 23:07:03.433189  Update DQM dly =572 (4 ,1, 28)  DQM OEN =(3 ,2)

 6359 23:07:03.433271  ==

 6360 23:07:03.437125  Dram Type= 6, Freq= 0, CH_0, rank 0

 6361 23:07:03.439811  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6362 23:07:03.439893  ==

 6363 23:07:03.439958  

 6364 23:07:03.440049  

 6365 23:07:03.443404  	TX Vref Scan disable

 6366 23:07:03.443511   == TX Byte 0 ==

 6367 23:07:03.450012  Update DQ  dly =580 (4 ,2, 4)  DQ  OEN =(3 ,3)

 6368 23:07:03.453143  Update DQM dly =580 (4 ,2, 4)  DQM OEN =(3 ,3)

 6369 23:07:03.453237   == TX Byte 1 ==

 6370 23:07:03.459748  Update DQ  dly =572 (4 ,1, 28)  DQ  OEN =(3 ,2)

 6371 23:07:03.463493  Update DQM dly =572 (4 ,1, 28)  DQM OEN =(3 ,2)

 6372 23:07:03.463577  

 6373 23:07:03.463642  [DATLAT]

 6374 23:07:03.466803  Freq=400, CH0 RK0

 6375 23:07:03.466885  

 6376 23:07:03.466949  DATLAT Default: 0xf

 6377 23:07:03.470075  0, 0xFFFF, sum = 0

 6378 23:07:03.470157  1, 0xFFFF, sum = 0

 6379 23:07:03.473684  2, 0xFFFF, sum = 0

 6380 23:07:03.473766  3, 0xFFFF, sum = 0

 6381 23:07:03.476559  4, 0xFFFF, sum = 0

 6382 23:07:03.476671  5, 0xFFFF, sum = 0

 6383 23:07:03.480395  6, 0xFFFF, sum = 0

 6384 23:07:03.480478  7, 0xFFFF, sum = 0

 6385 23:07:03.483671  8, 0xFFFF, sum = 0

 6386 23:07:03.483755  9, 0xFFFF, sum = 0

 6387 23:07:03.486995  10, 0xFFFF, sum = 0

 6388 23:07:03.487078  11, 0xFFFF, sum = 0

 6389 23:07:03.490134  12, 0xFFFF, sum = 0

 6390 23:07:03.490216  13, 0x0, sum = 1

 6391 23:07:03.493324  14, 0x0, sum = 2

 6392 23:07:03.493406  15, 0x0, sum = 3

 6393 23:07:03.496549  16, 0x0, sum = 4

 6394 23:07:03.496632  best_step = 14

 6395 23:07:03.496696  

 6396 23:07:03.496755  ==

 6397 23:07:03.500614  Dram Type= 6, Freq= 0, CH_0, rank 0

 6398 23:07:03.507668  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6399 23:07:03.507758  ==

 6400 23:07:03.507824  RX Vref Scan: 1

 6401 23:07:03.507884  

 6402 23:07:03.510358  RX Vref 0 -> 0, step: 1

 6403 23:07:03.510485  

 6404 23:07:03.513623  RX Delay -343 -> 252, step: 8

 6405 23:07:03.513729  

 6406 23:07:03.516753  Set Vref, RX VrefLevel [Byte0]: 53

 6407 23:07:03.520804                           [Byte1]: 52

 6408 23:07:03.520887  

 6409 23:07:03.523706  Final RX Vref Byte 0 = 53 to rank0

 6410 23:07:03.526917  Final RX Vref Byte 1 = 52 to rank0

 6411 23:07:03.530290  Final RX Vref Byte 0 = 53 to rank1

 6412 23:07:03.533522  Final RX Vref Byte 1 = 52 to rank1==

 6413 23:07:03.537235  Dram Type= 6, Freq= 0, CH_0, rank 0

 6414 23:07:03.540510  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6415 23:07:03.540593  ==

 6416 23:07:03.543840  DQS Delay:

 6417 23:07:03.543924  DQS0 = 44, DQS1 = 60

 6418 23:07:03.546820  DQM Delay:

 6419 23:07:03.546915  DQM0 = 11, DQM1 = 15

 6420 23:07:03.550190  DQ Delay:

 6421 23:07:03.550271  DQ0 =12, DQ1 =12, DQ2 =4, DQ3 =12

 6422 23:07:03.553772  DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20

 6423 23:07:03.558195  DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =12

 6424 23:07:03.561067  DQ12 =20, DQ13 =20, DQ14 =28, DQ15 =28

 6425 23:07:03.561149  

 6426 23:07:03.561213  

 6427 23:07:03.570914  [DQSOSCAuto] RK0, (LSB)MR18= 0x8755, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 392 ps

 6428 23:07:03.573816  CH0 RK0: MR19=C0C, MR18=8755

 6429 23:07:03.577300  CH0_RK0: MR19=0xC0C, MR18=0x8755, DQSOSC=392, MR23=63, INC=384, DEC=256

 6430 23:07:03.580624  ==

 6431 23:07:03.580708  Dram Type= 6, Freq= 0, CH_0, rank 1

 6432 23:07:03.587754  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6433 23:07:03.587837  ==

 6434 23:07:03.590748  [Gating] SW mode calibration

 6435 23:07:03.596990  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1

 6436 23:07:03.600627  RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)

 6437 23:07:03.607532   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6438 23:07:03.610178   0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6439 23:07:03.614091   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6440 23:07:03.620403   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6441 23:07:03.624153   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6442 23:07:03.626854   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6443 23:07:03.633538   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6444 23:07:03.636981   0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6445 23:07:03.640322   0 15  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6446 23:07:03.643510  Total UI for P1: 0, mck2ui 16

 6447 23:07:03.647214  best dqsien dly found for B0: ( 0, 14, 24)

 6448 23:07:03.650312  Total UI for P1: 0, mck2ui 16

 6449 23:07:03.654287  best dqsien dly found for B1: ( 0, 14, 24)

 6450 23:07:03.656972  best DQS0 dly(MCK, UI, PI) = (0, 14, 24)

 6451 23:07:03.660521  best DQS1 dly(MCK, UI, PI) = (0, 14, 24)

 6452 23:07:03.660607  

 6453 23:07:03.663909  best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6454 23:07:03.670283  best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6455 23:07:03.670393  [Gating] SW calibration Done

 6456 23:07:03.670504  ==

 6457 23:07:03.673645  Dram Type= 6, Freq= 0, CH_0, rank 1

 6458 23:07:03.680874  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6459 23:07:03.680957  ==

 6460 23:07:03.681023  RX Vref Scan: 0

 6461 23:07:03.681083  

 6462 23:07:03.683679  RX Vref 0 -> 0, step: 1

 6463 23:07:03.683786  

 6464 23:07:03.687418  RX Delay -410 -> 252, step: 16

 6465 23:07:03.690272  iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496

 6466 23:07:03.693408  iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496

 6467 23:07:03.701134  iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496

 6468 23:07:03.703852  iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496

 6469 23:07:03.706819  iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496

 6470 23:07:03.710703  iDelay=230, Bit 5, Center -43 (-282 ~ 197) 480

 6471 23:07:03.717280  iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496

 6472 23:07:03.720517  iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496

 6473 23:07:03.723975  iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496

 6474 23:07:03.726919  iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496

 6475 23:07:03.730310  iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496

 6476 23:07:03.736987  iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496

 6477 23:07:03.741505  iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496

 6478 23:07:03.744017  iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496

 6479 23:07:03.750647  iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496

 6480 23:07:03.753928  iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496

 6481 23:07:03.754009  ==

 6482 23:07:03.757533  Dram Type= 6, Freq= 0, CH_0, rank 1

 6483 23:07:03.760498  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6484 23:07:03.760580  ==

 6485 23:07:03.764058  DQS Delay:

 6486 23:07:03.764143  DQS0 = 43, DQS1 = 51

 6487 23:07:03.764208  DQM Delay:

 6488 23:07:03.767320  DQM0 = 11, DQM1 = 10

 6489 23:07:03.767457  DQ Delay:

 6490 23:07:03.770663  DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8

 6491 23:07:03.774081  DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =24

 6492 23:07:03.777722  DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0

 6493 23:07:03.780329  DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16

 6494 23:07:03.780426  

 6495 23:07:03.780493  

 6496 23:07:03.780557  ==

 6497 23:07:03.784530  Dram Type= 6, Freq= 0, CH_0, rank 1

 6498 23:07:03.787293  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6499 23:07:03.787391  ==

 6500 23:07:03.787459  

 6501 23:07:03.790745  

 6502 23:07:03.790832  	TX Vref Scan disable

 6503 23:07:03.793837   == TX Byte 0 ==

 6504 23:07:03.797461  Update DQ  dly =585 (4 ,2, 9)  DQ  OEN =(3 ,3)

 6505 23:07:03.800457  Update DQM dly =585 (4 ,2, 9)  DQM OEN =(3 ,3)

 6506 23:07:03.800542   == TX Byte 1 ==

 6507 23:07:03.807670  Update DQ  dly =581 (4 ,2, 5)  DQ  OEN =(3 ,3)

 6508 23:07:03.811240  Update DQM dly =581 (4 ,2, 5)  DQM OEN =(3 ,3)

 6509 23:07:03.811346  ==

 6510 23:07:03.815155  Dram Type= 6, Freq= 0, CH_0, rank 1

 6511 23:07:03.817523  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6512 23:07:03.817619  ==

 6513 23:07:03.817685  

 6514 23:07:03.817745  

 6515 23:07:03.820896  	TX Vref Scan disable

 6516 23:07:03.824386   == TX Byte 0 ==

 6517 23:07:03.827499  Update DQ  dly =585 (4 ,2, 9)  DQ  OEN =(3 ,3)

 6518 23:07:03.830785  Update DQM dly =585 (4 ,2, 9)  DQM OEN =(3 ,3)

 6519 23:07:03.830868   == TX Byte 1 ==

 6520 23:07:03.837145  Update DQ  dly =581 (4 ,2, 5)  DQ  OEN =(3 ,3)

 6521 23:07:03.840629  Update DQM dly =581 (4 ,2, 5)  DQM OEN =(3 ,3)

 6522 23:07:03.840712  

 6523 23:07:03.840777  [DATLAT]

 6524 23:07:03.844444  Freq=400, CH0 RK1

 6525 23:07:03.844527  

 6526 23:07:03.844591  DATLAT Default: 0xe

 6527 23:07:03.847257  0, 0xFFFF, sum = 0

 6528 23:07:03.847342  1, 0xFFFF, sum = 0

 6529 23:07:03.850524  2, 0xFFFF, sum = 0

 6530 23:07:03.850607  3, 0xFFFF, sum = 0

 6531 23:07:03.854252  4, 0xFFFF, sum = 0

 6532 23:07:03.854338  5, 0xFFFF, sum = 0

 6533 23:07:03.857527  6, 0xFFFF, sum = 0

 6534 23:07:03.857610  7, 0xFFFF, sum = 0

 6535 23:07:03.860913  8, 0xFFFF, sum = 0

 6536 23:07:03.864174  9, 0xFFFF, sum = 0

 6537 23:07:03.864257  10, 0xFFFF, sum = 0

 6538 23:07:03.867186  11, 0xFFFF, sum = 0

 6539 23:07:03.867270  12, 0xFFFF, sum = 0

 6540 23:07:03.870828  13, 0x0, sum = 1

 6541 23:07:03.870911  14, 0x0, sum = 2

 6542 23:07:03.874304  15, 0x0, sum = 3

 6543 23:07:03.874421  16, 0x0, sum = 4

 6544 23:07:03.874503  best_step = 14

 6545 23:07:03.874564  

 6546 23:07:03.877949  ==

 6547 23:07:03.878031  Dram Type= 6, Freq= 0, CH_0, rank 1

 6548 23:07:03.884133  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6549 23:07:03.884248  ==

 6550 23:07:03.884355  RX Vref Scan: 0

 6551 23:07:03.884463  

 6552 23:07:03.887794  RX Vref 0 -> 0, step: 1

 6553 23:07:03.887876  

 6554 23:07:03.890988  RX Delay -343 -> 252, step: 8

 6555 23:07:03.898543  iDelay=217, Bit 0, Center -32 (-271 ~ 208) 480

 6556 23:07:03.900933  iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480

 6557 23:07:03.904247  iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480

 6558 23:07:03.907831  iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488

 6559 23:07:03.914284  iDelay=217, Bit 4, Center -36 (-271 ~ 200) 472

 6560 23:07:03.918032  iDelay=217, Bit 5, Center -48 (-287 ~ 192) 480

 6561 23:07:03.920904  iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488

 6562 23:07:03.924524  iDelay=217, Bit 7, Center -32 (-271 ~ 208) 480

 6563 23:07:03.931711  iDelay=217, Bit 8, Center -56 (-295 ~ 184) 480

 6564 23:07:03.934566  iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496

 6565 23:07:03.937610  iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488

 6566 23:07:03.941292  iDelay=217, Bit 11, Center -56 (-295 ~ 184) 480

 6567 23:07:03.948055  iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488

 6568 23:07:03.951240  iDelay=217, Bit 13, Center -40 (-279 ~ 200) 480

 6569 23:07:03.954716  iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488

 6570 23:07:03.958156  iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488

 6571 23:07:03.958238  ==

 6572 23:07:03.961259  Dram Type= 6, Freq= 0, CH_0, rank 1

 6573 23:07:03.968435  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6574 23:07:03.968519  ==

 6575 23:07:03.968585  DQS Delay:

 6576 23:07:03.971695  DQS0 = 48, DQS1 = 56

 6577 23:07:03.971778  DQM Delay:

 6578 23:07:03.974900  DQM0 = 12, DQM1 = 10

 6579 23:07:03.974983  DQ Delay:

 6580 23:07:03.978271  DQ0 =16, DQ1 =16, DQ2 =8, DQ3 =12

 6581 23:07:03.981291  DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16

 6582 23:07:03.984444  DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =0

 6583 23:07:03.988262  DQ12 =12, DQ13 =16, DQ14 =20, DQ15 =20

 6584 23:07:03.988345  

 6585 23:07:03.988410  

 6586 23:07:03.994904  [DQSOSCAuto] RK1, (LSB)MR18= 0x9b6e, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 390 ps

 6587 23:07:03.998527  CH0 RK1: MR19=C0C, MR18=9B6E

 6588 23:07:04.005270  CH0_RK1: MR19=0xC0C, MR18=0x9B6E, DQSOSC=390, MR23=63, INC=388, DEC=258

 6589 23:07:04.007900  [RxdqsGatingPostProcess] freq 400

 6590 23:07:04.011552  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3

 6591 23:07:04.014675  best DQS0 dly(2T, 0.5T) = (0, 10)

 6592 23:07:04.018217  best DQS1 dly(2T, 0.5T) = (0, 10)

 6593 23:07:04.021173  best DQS0 P1 dly(2T, 0.5T) = (0, 12)

 6594 23:07:04.025044  best DQS1 P1 dly(2T, 0.5T) = (0, 12)

 6595 23:07:04.028150  best DQS0 dly(2T, 0.5T) = (0, 10)

 6596 23:07:04.031503  best DQS1 dly(2T, 0.5T) = (0, 10)

 6597 23:07:04.034851  best DQS0 P1 dly(2T, 0.5T) = (0, 12)

 6598 23:07:04.038101  best DQS1 P1 dly(2T, 0.5T) = (0, 12)

 6599 23:07:04.041737  Pre-setting of DQS Precalculation

 6600 23:07:04.044469  [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14

 6601 23:07:04.044552  ==

 6602 23:07:04.048164  Dram Type= 6, Freq= 0, CH_1, rank 0

 6603 23:07:04.055312  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6604 23:07:04.055400  ==

 6605 23:07:04.058097  pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0

 6606 23:07:04.064592  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35

 6607 23:07:04.068401  [CA 0] Center 36 (8~64) winsize 57

 6608 23:07:04.071126  [CA 1] Center 36 (8~64) winsize 57

 6609 23:07:04.074563  [CA 2] Center 36 (8~64) winsize 57

 6610 23:07:04.077994  [CA 3] Center 36 (8~64) winsize 57

 6611 23:07:04.081319  [CA 4] Center 36 (8~64) winsize 57

 6612 23:07:04.085372  [CA 5] Center 36 (8~64) winsize 57

 6613 23:07:04.085456  

 6614 23:07:04.088298  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 6615 23:07:04.088380  

 6616 23:07:04.091187  [CATrainingPosCal] consider 1 rank data

 6617 23:07:04.094671  u2DelayCellTimex100 = 270/100 ps

 6618 23:07:04.098121  CA0 delay=36 (8~64),Diff = 0 PI (0 cell)

 6619 23:07:04.101488  CA1 delay=36 (8~64),Diff = 0 PI (0 cell)

 6620 23:07:04.104751  CA2 delay=36 (8~64),Diff = 0 PI (0 cell)

 6621 23:07:04.108559  CA3 delay=36 (8~64),Diff = 0 PI (0 cell)

 6622 23:07:04.111238  CA4 delay=36 (8~64),Diff = 0 PI (0 cell)

 6623 23:07:04.115184  CA5 delay=36 (8~64),Diff = 0 PI (0 cell)

 6624 23:07:04.115266  

 6625 23:07:04.118316  CA PerBit enable=1, Macro0, CA PI delay=36

 6626 23:07:04.121619  

 6627 23:07:04.121700  [CBTSetCACLKResult] CA Dly = 36

 6628 23:07:04.124803  CS Dly: 1 (0~32)

 6629 23:07:04.124886  ==

 6630 23:07:04.128239  Dram Type= 6, Freq= 0, CH_1, rank 1

 6631 23:07:04.131816  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6632 23:07:04.131906  ==

 6633 23:07:04.138364  pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0

 6634 23:07:04.145929  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35

 6635 23:07:04.148076  [CA 0] Center 36 (8~64) winsize 57

 6636 23:07:04.148184  [CA 1] Center 36 (8~64) winsize 57

 6637 23:07:04.151665  [CA 2] Center 36 (8~64) winsize 57

 6638 23:07:04.155531  [CA 3] Center 36 (8~64) winsize 57

 6639 23:07:04.158498  [CA 4] Center 36 (8~64) winsize 57

 6640 23:07:04.161537  [CA 5] Center 36 (8~64) winsize 57

 6641 23:07:04.161622  

 6642 23:07:04.165062  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 6643 23:07:04.165149  

 6644 23:07:04.168379  [CATrainingPosCal] consider 2 rank data

 6645 23:07:04.171723  u2DelayCellTimex100 = 270/100 ps

 6646 23:07:04.175268  CA0 delay=36 (8~64),Diff = 0 PI (0 cell)

 6647 23:07:04.182054  CA1 delay=36 (8~64),Diff = 0 PI (0 cell)

 6648 23:07:04.184987  CA2 delay=36 (8~64),Diff = 0 PI (0 cell)

 6649 23:07:04.188227  CA3 delay=36 (8~64),Diff = 0 PI (0 cell)

 6650 23:07:04.191913  CA4 delay=36 (8~64),Diff = 0 PI (0 cell)

 6651 23:07:04.194910  CA5 delay=36 (8~64),Diff = 0 PI (0 cell)

 6652 23:07:04.194994  

 6653 23:07:04.198492  CA PerBit enable=1, Macro0, CA PI delay=36

 6654 23:07:04.198575  

 6655 23:07:04.201600  [CBTSetCACLKResult] CA Dly = 36

 6656 23:07:04.201682  CS Dly: 1 (0~32)

 6657 23:07:04.201747  

 6658 23:07:04.205451  ----->DramcWriteLeveling(PI) begin...

 6659 23:07:04.208549  ==

 6660 23:07:04.208648  Dram Type= 6, Freq= 0, CH_1, rank 0

 6661 23:07:04.215233  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6662 23:07:04.215316  ==

 6663 23:07:04.218321  Write leveling (Byte 0): 40 => 8

 6664 23:07:04.222253  Write leveling (Byte 1): 40 => 8

 6665 23:07:04.222337  DramcWriteLeveling(PI) end<-----

 6666 23:07:04.222410  

 6667 23:07:04.225813  ==

 6668 23:07:04.228930  Dram Type= 6, Freq= 0, CH_1, rank 0

 6669 23:07:04.231705  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6670 23:07:04.231788  ==

 6671 23:07:04.235063  [Gating] SW mode calibration

 6672 23:07:04.241969  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1

 6673 23:07:04.245653  RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)

 6674 23:07:04.252301   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6675 23:07:04.255440   0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6676 23:07:04.258554   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6677 23:07:04.265293   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6678 23:07:04.268897   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6679 23:07:04.272070   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6680 23:07:04.278854   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6681 23:07:04.282215   0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6682 23:07:04.285440   0 15  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6683 23:07:04.289238  Total UI for P1: 0, mck2ui 16

 6684 23:07:04.292020  best dqsien dly found for B0: ( 0, 14, 24)

 6685 23:07:04.295916  Total UI for P1: 0, mck2ui 16

 6686 23:07:04.298662  best dqsien dly found for B1: ( 0, 14, 24)

 6687 23:07:04.302013  best DQS0 dly(MCK, UI, PI) = (0, 14, 24)

 6688 23:07:04.305680  best DQS1 dly(MCK, UI, PI) = (0, 14, 24)

 6689 23:07:04.305763  

 6690 23:07:04.308513  best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6691 23:07:04.315419  best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6692 23:07:04.315501  [Gating] SW calibration Done

 6693 23:07:04.315566  ==

 6694 23:07:04.319030  Dram Type= 6, Freq= 0, CH_1, rank 0

 6695 23:07:04.325525  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6696 23:07:04.325608  ==

 6697 23:07:04.325672  RX Vref Scan: 0

 6698 23:07:04.325732  

 6699 23:07:04.328971  RX Vref 0 -> 0, step: 1

 6700 23:07:04.329052  

 6701 23:07:04.331986  RX Delay -410 -> 252, step: 16

 6702 23:07:04.335626  iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480

 6703 23:07:04.339253  iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496

 6704 23:07:04.345761  iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496

 6705 23:07:04.348980  iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496

 6706 23:07:04.351899  iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496

 6707 23:07:04.355891  iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496

 6708 23:07:04.358897  iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496

 6709 23:07:04.365628  iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496

 6710 23:07:04.368983  iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512

 6711 23:07:04.372280  iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512

 6712 23:07:04.375447  iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512

 6713 23:07:04.381802  iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512

 6714 23:07:04.385331  iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496

 6715 23:07:04.388693  iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496

 6716 23:07:04.395349  iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496

 6717 23:07:04.399086  iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496

 6718 23:07:04.399169  ==

 6719 23:07:04.402615  Dram Type= 6, Freq= 0, CH_1, rank 0

 6720 23:07:04.405357  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6721 23:07:04.405439  ==

 6722 23:07:04.409024  DQS Delay:

 6723 23:07:04.409106  DQS0 = 51, DQS1 = 59

 6724 23:07:04.409170  DQM Delay:

 6725 23:07:04.412345  DQM0 = 19, DQM1 = 16

 6726 23:07:04.412427  DQ Delay:

 6727 23:07:04.415324  DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16

 6728 23:07:04.419157  DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16

 6729 23:07:04.421688  DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16

 6730 23:07:04.425121  DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24

 6731 23:07:04.425203  

 6732 23:07:04.425267  

 6733 23:07:04.425327  ==

 6734 23:07:04.428382  Dram Type= 6, Freq= 0, CH_1, rank 0

 6735 23:07:04.435455  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6736 23:07:04.435583  ==

 6737 23:07:04.435648  

 6738 23:07:04.435707  

 6739 23:07:04.435764  	TX Vref Scan disable

 6740 23:07:04.438966   == TX Byte 0 ==

 6741 23:07:04.441905  Update DQ  dly =580 (4 ,2, 4)  DQ  OEN =(3 ,3)

 6742 23:07:04.445534  Update DQM dly =580 (4 ,2, 4)  DQM OEN =(3 ,3)

 6743 23:07:04.448638   == TX Byte 1 ==

 6744 23:07:04.452104  Update DQ  dly =580 (4 ,2, 4)  DQ  OEN =(3 ,3)

 6745 23:07:04.455392  Update DQM dly =580 (4 ,2, 4)  DQM OEN =(3 ,3)

 6746 23:07:04.455474  ==

 6747 23:07:04.458785  Dram Type= 6, Freq= 0, CH_1, rank 0

 6748 23:07:04.465157  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6749 23:07:04.465239  ==

 6750 23:07:04.465303  

 6751 23:07:04.465363  

 6752 23:07:04.465419  	TX Vref Scan disable

 6753 23:07:04.468778   == TX Byte 0 ==

 6754 23:07:04.472315  Update DQ  dly =580 (4 ,2, 4)  DQ  OEN =(3 ,3)

 6755 23:07:04.475902  Update DQM dly =580 (4 ,2, 4)  DQM OEN =(3 ,3)

 6756 23:07:04.478619   == TX Byte 1 ==

 6757 23:07:04.482337  Update DQ  dly =580 (4 ,2, 4)  DQ  OEN =(3 ,3)

 6758 23:07:04.485184  Update DQM dly =580 (4 ,2, 4)  DQM OEN =(3 ,3)

 6759 23:07:04.485267  

 6760 23:07:04.488567  [DATLAT]

 6761 23:07:04.488648  Freq=400, CH1 RK0

 6762 23:07:04.488712  

 6763 23:07:04.492556  DATLAT Default: 0xf

 6764 23:07:04.492638  0, 0xFFFF, sum = 0

 6765 23:07:04.495376  1, 0xFFFF, sum = 0

 6766 23:07:04.495459  2, 0xFFFF, sum = 0

 6767 23:07:04.498758  3, 0xFFFF, sum = 0

 6768 23:07:04.498841  4, 0xFFFF, sum = 0

 6769 23:07:04.502221  5, 0xFFFF, sum = 0

 6770 23:07:04.502304  6, 0xFFFF, sum = 0

 6771 23:07:04.505232  7, 0xFFFF, sum = 0

 6772 23:07:04.505315  8, 0xFFFF, sum = 0

 6773 23:07:04.508794  9, 0xFFFF, sum = 0

 6774 23:07:04.508877  10, 0xFFFF, sum = 0

 6775 23:07:04.512614  11, 0xFFFF, sum = 0

 6776 23:07:04.512697  12, 0xFFFF, sum = 0

 6777 23:07:04.515277  13, 0x0, sum = 1

 6778 23:07:04.515361  14, 0x0, sum = 2

 6779 23:07:04.518595  15, 0x0, sum = 3

 6780 23:07:04.518678  16, 0x0, sum = 4

 6781 23:07:04.521984  best_step = 14

 6782 23:07:04.522066  

 6783 23:07:04.522130  ==

 6784 23:07:04.525418  Dram Type= 6, Freq= 0, CH_1, rank 0

 6785 23:07:04.528497  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6786 23:07:04.528579  ==

 6787 23:07:04.531818  RX Vref Scan: 1

 6788 23:07:04.531899  

 6789 23:07:04.531964  RX Vref 0 -> 0, step: 1

 6790 23:07:04.532024  

 6791 23:07:04.535501  RX Delay -359 -> 252, step: 8

 6792 23:07:04.535583  

 6793 23:07:04.538519  Set Vref, RX VrefLevel [Byte0]: 57

 6794 23:07:04.541758                           [Byte1]: 51

 6795 23:07:04.546873  

 6796 23:07:04.546954  Final RX Vref Byte 0 = 57 to rank0

 6797 23:07:04.550138  Final RX Vref Byte 1 = 51 to rank0

 6798 23:07:04.553609  Final RX Vref Byte 0 = 57 to rank1

 6799 23:07:04.556774  Final RX Vref Byte 1 = 51 to rank1==

 6800 23:07:04.559954  Dram Type= 6, Freq= 0, CH_1, rank 0

 6801 23:07:04.566494  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6802 23:07:04.566577  ==

 6803 23:07:04.566643  DQS Delay:

 6804 23:07:04.566702  DQS0 = 48, DQS1 = 64

 6805 23:07:04.570293  DQM Delay:

 6806 23:07:04.570414  DQM0 = 12, DQM1 = 16

 6807 23:07:04.573506  DQ Delay:

 6808 23:07:04.576502  DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12

 6809 23:07:04.576589  DQ4 =8, DQ5 =20, DQ6 =24, DQ7 =8

 6810 23:07:04.579968  DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =12

 6811 23:07:04.583469  DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24

 6812 23:07:04.583549  

 6813 23:07:04.583635  

 6814 23:07:04.593395  [DQSOSCAuto] RK0, (LSB)MR18= 0x8830, (MSB)MR19= 0xc0c, tDQSOscB0 = 403 ps tDQSOscB1 = 392 ps

 6815 23:07:04.596946  CH1 RK0: MR19=C0C, MR18=8830

 6816 23:07:04.603601  CH1_RK0: MR19=0xC0C, MR18=0x8830, DQSOSC=392, MR23=63, INC=384, DEC=256

 6817 23:07:04.603684  ==

 6818 23:07:04.606871  Dram Type= 6, Freq= 0, CH_1, rank 1

 6819 23:07:04.609993  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6820 23:07:04.610079  ==

 6821 23:07:04.613201  [Gating] SW mode calibration

 6822 23:07:04.619982  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1

 6823 23:07:04.623753  RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)

 6824 23:07:04.629861   0 11  0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)

 6825 23:07:04.634658   0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6826 23:07:04.636674   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6827 23:07:04.643349   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6828 23:07:04.646711   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6829 23:07:04.650392   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6830 23:07:04.657114   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6831 23:07:04.660624   0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6832 23:07:04.663739   0 15  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6833 23:07:04.666830  Total UI for P1: 0, mck2ui 16

 6834 23:07:04.670242  best dqsien dly found for B0: ( 0, 14, 24)

 6835 23:07:04.673769  Total UI for P1: 0, mck2ui 16

 6836 23:07:04.677141  best dqsien dly found for B1: ( 0, 14, 24)

 6837 23:07:04.680060  best DQS0 dly(MCK, UI, PI) = (0, 14, 24)

 6838 23:07:04.683963  best DQS1 dly(MCK, UI, PI) = (0, 14, 24)

 6839 23:07:04.684045  

 6840 23:07:04.689834  best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6841 23:07:04.693505  best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6842 23:07:04.693587  [Gating] SW calibration Done

 6843 23:07:04.697016  ==

 6844 23:07:04.700153  Dram Type= 6, Freq= 0, CH_1, rank 1

 6845 23:07:04.703141  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6846 23:07:04.703224  ==

 6847 23:07:04.703289  RX Vref Scan: 0

 6848 23:07:04.703351  

 6849 23:07:04.706809  RX Vref 0 -> 0, step: 1

 6850 23:07:04.706891  

 6851 23:07:04.709859  RX Delay -410 -> 252, step: 16

 6852 23:07:04.713879  iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496

 6853 23:07:04.716936  iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496

 6854 23:07:04.723226  iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512

 6855 23:07:04.727221  iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496

 6856 23:07:04.730017  iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496

 6857 23:07:04.733221  iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496

 6858 23:07:04.740476  iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496

 6859 23:07:04.743406  iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496

 6860 23:07:04.746647  iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496

 6861 23:07:04.749690  iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496

 6862 23:07:04.757245  iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512

 6863 23:07:04.760069  iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496

 6864 23:07:04.763316  iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496

 6865 23:07:04.766529  iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512

 6866 23:07:04.773421  iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496

 6867 23:07:04.776649  iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512

 6868 23:07:04.776732  ==

 6869 23:07:04.780123  Dram Type= 6, Freq= 0, CH_1, rank 1

 6870 23:07:04.783240  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6871 23:07:04.783323  ==

 6872 23:07:04.786579  DQS Delay:

 6873 23:07:04.786661  DQS0 = 43, DQS1 = 51

 6874 23:07:04.789857  DQM Delay:

 6875 23:07:04.789938  DQM0 = 11, DQM1 = 11

 6876 23:07:04.790002  DQ Delay:

 6877 23:07:04.793526  DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8

 6878 23:07:04.796671  DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8

 6879 23:07:04.800291  DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0

 6880 23:07:04.803607  DQ12 =16, DQ13 =24, DQ14 =16, DQ15 =24

 6881 23:07:04.803689  

 6882 23:07:04.803752  

 6883 23:07:04.803811  ==

 6884 23:07:04.806850  Dram Type= 6, Freq= 0, CH_1, rank 1

 6885 23:07:04.809905  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6886 23:07:04.813416  ==

 6887 23:07:04.813498  

 6888 23:07:04.813561  

 6889 23:07:04.813620  	TX Vref Scan disable

 6890 23:07:04.816550   == TX Byte 0 ==

 6891 23:07:04.819955  Update DQ  dly =585 (4 ,2, 9)  DQ  OEN =(3 ,3)

 6892 23:07:04.823252  Update DQM dly =585 (4 ,2, 9)  DQM OEN =(3 ,3)

 6893 23:07:04.827295   == TX Byte 1 ==

 6894 23:07:04.830185  Update DQ  dly =585 (4 ,2, 9)  DQ  OEN =(3 ,3)

 6895 23:07:04.833709  Update DQM dly =585 (4 ,2, 9)  DQM OEN =(3 ,3)

 6896 23:07:04.833791  ==

 6897 23:07:04.836615  Dram Type= 6, Freq= 0, CH_1, rank 1

 6898 23:07:04.840196  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6899 23:07:04.840278  ==

 6900 23:07:04.843692  

 6901 23:07:04.843774  

 6902 23:07:04.843837  	TX Vref Scan disable

 6903 23:07:04.846689   == TX Byte 0 ==

 6904 23:07:04.850309  Update DQ  dly =585 (4 ,2, 9)  DQ  OEN =(3 ,3)

 6905 23:07:04.853622  Update DQM dly =585 (4 ,2, 9)  DQM OEN =(3 ,3)

 6906 23:07:04.856820   == TX Byte 1 ==

 6907 23:07:04.860204  Update DQ  dly =585 (4 ,2, 9)  DQ  OEN =(3 ,3)

 6908 23:07:04.863501  Update DQM dly =585 (4 ,2, 9)  DQM OEN =(3 ,3)

 6909 23:07:04.863584  

 6910 23:07:04.863648  [DATLAT]

 6911 23:07:04.867106  Freq=400, CH1 RK1

 6912 23:07:04.867187  

 6913 23:07:04.867250  DATLAT Default: 0xe

 6914 23:07:04.871102  0, 0xFFFF, sum = 0

 6915 23:07:04.871185  1, 0xFFFF, sum = 0

 6916 23:07:04.873902  2, 0xFFFF, sum = 0

 6917 23:07:04.877166  3, 0xFFFF, sum = 0

 6918 23:07:04.877249  4, 0xFFFF, sum = 0

 6919 23:07:04.880428  5, 0xFFFF, sum = 0

 6920 23:07:04.880511  6, 0xFFFF, sum = 0

 6921 23:07:04.883902  7, 0xFFFF, sum = 0

 6922 23:07:04.883986  8, 0xFFFF, sum = 0

 6923 23:07:04.886971  9, 0xFFFF, sum = 0

 6924 23:07:04.887091  10, 0xFFFF, sum = 0

 6925 23:07:04.890394  11, 0xFFFF, sum = 0

 6926 23:07:04.890515  12, 0xFFFF, sum = 0

 6927 23:07:04.893913  13, 0x0, sum = 1

 6928 23:07:04.893996  14, 0x0, sum = 2

 6929 23:07:04.896959  15, 0x0, sum = 3

 6930 23:07:04.897077  16, 0x0, sum = 4

 6931 23:07:04.900558  best_step = 14

 6932 23:07:04.900635  

 6933 23:07:04.900720  ==

 6934 23:07:04.903504  Dram Type= 6, Freq= 0, CH_1, rank 1

 6935 23:07:04.907049  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6936 23:07:04.907125  ==

 6937 23:07:04.907206  RX Vref Scan: 0

 6938 23:07:04.907285  

 6939 23:07:04.910057  RX Vref 0 -> 0, step: 1

 6940 23:07:04.910128  

 6941 23:07:04.913499  RX Delay -343 -> 252, step: 8

 6942 23:07:04.920924  iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488

 6943 23:07:04.924470  iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488

 6944 23:07:04.927804  iDelay=217, Bit 2, Center -52 (-295 ~ 192) 488

 6945 23:07:04.931301  iDelay=217, Bit 3, Center -44 (-287 ~ 200) 488

 6946 23:07:04.937529  iDelay=217, Bit 4, Center -40 (-287 ~ 208) 496

 6947 23:07:04.941057  iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488

 6948 23:07:04.944484  iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488

 6949 23:07:04.947541  iDelay=217, Bit 7, Center -44 (-287 ~ 200) 488

 6950 23:07:04.954487  iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496

 6951 23:07:04.958046  iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496

 6952 23:07:04.960823  iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496

 6953 23:07:04.964487  iDelay=217, Bit 11, Center -56 (-303 ~ 192) 496

 6954 23:07:04.971140  iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488

 6955 23:07:04.974369  iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496

 6956 23:07:04.977396  iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496

 6957 23:07:04.980782  iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488

 6958 23:07:04.984524  ==

 6959 23:07:04.984617  Dram Type= 6, Freq= 0, CH_1, rank 1

 6960 23:07:04.991064  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6961 23:07:04.991171  ==

 6962 23:07:04.991259  DQS Delay:

 6963 23:07:04.994046  DQS0 = 52, DQS1 = 56

 6964 23:07:04.994152  DQM Delay:

 6965 23:07:04.997560  DQM0 = 12, DQM1 = 9

 6966 23:07:04.997647  DQ Delay:

 6967 23:07:05.000972  DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8

 6968 23:07:05.004452  DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =8

 6969 23:07:05.004540  DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0

 6970 23:07:05.010857  DQ12 =12, DQ13 =16, DQ14 =16, DQ15 =20

 6971 23:07:05.010958  

 6972 23:07:05.011045  

 6973 23:07:05.018075  [DQSOSCAuto] RK1, (LSB)MR18= 0x7c93, (MSB)MR19= 0xc0c, tDQSOscB0 = 391 ps tDQSOscB1 = 394 ps

 6974 23:07:05.020879  CH1 RK1: MR19=C0C, MR18=7C93

 6975 23:07:05.027556  CH1_RK1: MR19=0xC0C, MR18=0x7C93, DQSOSC=391, MR23=63, INC=386, DEC=257

 6976 23:07:05.031375  [RxdqsGatingPostProcess] freq 400

 6977 23:07:05.034229  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3

 6978 23:07:05.037729  best DQS0 dly(2T, 0.5T) = (0, 10)

 6979 23:07:05.041382  best DQS1 dly(2T, 0.5T) = (0, 10)

 6980 23:07:05.044367  best DQS0 P1 dly(2T, 0.5T) = (0, 12)

 6981 23:07:05.047836  best DQS1 P1 dly(2T, 0.5T) = (0, 12)

 6982 23:07:05.050911  best DQS0 dly(2T, 0.5T) = (0, 10)

 6983 23:07:05.054361  best DQS1 dly(2T, 0.5T) = (0, 10)

 6984 23:07:05.057811  best DQS0 P1 dly(2T, 0.5T) = (0, 12)

 6985 23:07:05.061118  best DQS1 P1 dly(2T, 0.5T) = (0, 12)

 6986 23:07:05.064520  Pre-setting of DQS Precalculation

 6987 23:07:05.068088  [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14

 6988 23:07:05.074600  sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6

 6989 23:07:05.084563  calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464

 6990 23:07:05.084672  

 6991 23:07:05.084742  

 6992 23:07:05.084802  [Calibration Summary] 800 Mbps

 6993 23:07:05.087598  CH 0, Rank 0

 6994 23:07:05.087680  SW Impedance     : PASS

 6995 23:07:05.091701  DUTY Scan        : NO K

 6996 23:07:05.094798  ZQ Calibration   : PASS

 6997 23:07:05.094883  Jitter Meter     : NO K

 6998 23:07:05.097835  CBT Training     : PASS

 6999 23:07:05.101630  Write leveling   : PASS

 7000 23:07:05.101716  RX DQS gating    : PASS

 7001 23:07:05.104410  RX DQ/DQS(RDDQC) : PASS

 7002 23:07:05.107916  TX DQ/DQS        : PASS

 7003 23:07:05.107999  RX DATLAT        : PASS

 7004 23:07:05.111339  RX DQ/DQS(Engine): PASS

 7005 23:07:05.114543  TX OE            : NO K

 7006 23:07:05.114627  All Pass.

 7007 23:07:05.114693  

 7008 23:07:05.114754  CH 0, Rank 1

 7009 23:07:05.118245  SW Impedance     : PASS

 7010 23:07:05.121159  DUTY Scan        : NO K

 7011 23:07:05.121243  ZQ Calibration   : PASS

 7012 23:07:05.124982  Jitter Meter     : NO K

 7013 23:07:05.125066  CBT Training     : PASS

 7014 23:07:05.127803  Write leveling   : NO K

 7015 23:07:05.131213  RX DQS gating    : PASS

 7016 23:07:05.131297  RX DQ/DQS(RDDQC) : PASS

 7017 23:07:05.135138  TX DQ/DQS        : PASS

 7018 23:07:05.137836  RX DATLAT        : PASS

 7019 23:07:05.137917  RX DQ/DQS(Engine): PASS

 7020 23:07:05.141655  TX OE            : NO K

 7021 23:07:05.141738  All Pass.

 7022 23:07:05.141802  

 7023 23:07:05.144882  CH 1, Rank 0

 7024 23:07:05.144964  SW Impedance     : PASS

 7025 23:07:05.148052  DUTY Scan        : NO K

 7026 23:07:05.151275  ZQ Calibration   : PASS

 7027 23:07:05.151358  Jitter Meter     : NO K

 7028 23:07:05.154529  CBT Training     : PASS

 7029 23:07:05.158190  Write leveling   : PASS

 7030 23:07:05.158299  RX DQS gating    : PASS

 7031 23:07:05.161288  RX DQ/DQS(RDDQC) : PASS

 7032 23:07:05.161370  TX DQ/DQS        : PASS

 7033 23:07:05.164675  RX DATLAT        : PASS

 7034 23:07:05.167899  RX DQ/DQS(Engine): PASS

 7035 23:07:05.167983  TX OE            : NO K

 7036 23:07:05.171083  All Pass.

 7037 23:07:05.171165  

 7038 23:07:05.171229  CH 1, Rank 1

 7039 23:07:05.174931  SW Impedance     : PASS

 7040 23:07:05.175015  DUTY Scan        : NO K

 7041 23:07:05.178408  ZQ Calibration   : PASS

 7042 23:07:05.181877  Jitter Meter     : NO K

 7043 23:07:05.181959  CBT Training     : PASS

 7044 23:07:05.184645  Write leveling   : NO K

 7045 23:07:05.188238  RX DQS gating    : PASS

 7046 23:07:05.188321  RX DQ/DQS(RDDQC) : PASS

 7047 23:07:05.191597  TX DQ/DQS        : PASS

 7048 23:07:05.194596  RX DATLAT        : PASS

 7049 23:07:05.194682  RX DQ/DQS(Engine): PASS

 7050 23:07:05.198572  TX OE            : NO K

 7051 23:07:05.198650  All Pass.

 7052 23:07:05.198734  

 7053 23:07:05.201482  DramC Write-DBI off

 7054 23:07:05.204427  	PER_BANK_REFRESH: Hybrid Mode

 7055 23:07:05.204504  TX_TRACKING: ON

 7056 23:07:05.215266  [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0

 7057 23:07:05.218246  [FAST_K] Save calibration result to emmc

 7058 23:07:05.221428  dramc_set_vcore_voltage set vcore to 725000

 7059 23:07:05.224511  Read voltage for 1600, 0

 7060 23:07:05.224589  Vio18 = 0

 7061 23:07:05.224652  Vcore = 725000

 7062 23:07:05.227821  Vdram = 0

 7063 23:07:05.227893  Vddq = 0

 7064 23:07:05.227953  Vmddr = 0

 7065 23:07:05.235122  [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0

 7066 23:07:05.237869  [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0

 7067 23:07:05.241346  MEM_TYPE=3, freq_sel=13

 7068 23:07:05.244923  sv_algorithm_assistance_LP4_3733 

 7069 23:07:05.248831  ============ PULL DRAM RESETB DOWN ============

 7070 23:07:05.251835  ========== PULL DRAM RESETB DOWN end =========

 7071 23:07:05.258627  [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5

 7072 23:07:05.261431  =================================== 

 7073 23:07:05.261514  LPDDR4 DRAM CONFIGURATION

 7074 23:07:05.264911  =================================== 

 7075 23:07:05.267955  EX_ROW_EN[0]    = 0x0

 7076 23:07:05.271396  EX_ROW_EN[1]    = 0x0

 7077 23:07:05.271480  LP4Y_EN      = 0x0

 7078 23:07:05.274636  WORK_FSP     = 0x1

 7079 23:07:05.274718  WL           = 0x5

 7080 23:07:05.278040  RL           = 0x5

 7081 23:07:05.278150  BL           = 0x2

 7082 23:07:05.281797  RPST         = 0x0

 7083 23:07:05.281881  RD_PRE       = 0x0

 7084 23:07:05.285178  WR_PRE       = 0x1

 7085 23:07:05.285310  WR_PST       = 0x1

 7086 23:07:05.288230  DBI_WR       = 0x0

 7087 23:07:05.288304  DBI_RD       = 0x0

 7088 23:07:05.291178  OTF          = 0x1

 7089 23:07:05.294599  =================================== 

 7090 23:07:05.298323  =================================== 

 7091 23:07:05.298460  ANA top config

 7092 23:07:05.301952  =================================== 

 7093 23:07:05.304532  DLL_ASYNC_EN            =  0

 7094 23:07:05.308257  ALL_SLAVE_EN            =  0

 7095 23:07:05.308335  NEW_RANK_MODE           =  1

 7096 23:07:05.311224  DLL_IDLE_MODE           =  1

 7097 23:07:05.314822  LP45_APHY_COMB_EN       =  1

 7098 23:07:05.318394  TX_ODT_DIS              =  0

 7099 23:07:05.318552  NEW_8X_MODE             =  1

 7100 23:07:05.322294  =================================== 

 7101 23:07:05.324965  =================================== 

 7102 23:07:05.328544  data_rate                  = 3200

 7103 23:07:05.331533  CKR                        = 1

 7104 23:07:05.335216  DQ_P2S_RATIO               = 8

 7105 23:07:05.338767  =================================== 

 7106 23:07:05.341447  CA_P2S_RATIO               = 8

 7107 23:07:05.345126  DQ_CA_OPEN                 = 0

 7108 23:07:05.345229  DQ_SEMI_OPEN               = 0

 7109 23:07:05.348404  CA_SEMI_OPEN               = 0

 7110 23:07:05.351476  CA_FULL_RATE               = 0

 7111 23:07:05.354721  DQ_CKDIV4_EN               = 0

 7112 23:07:05.358798  CA_CKDIV4_EN               = 0

 7113 23:07:05.361420  CA_PREDIV_EN               = 0

 7114 23:07:05.361521  PH8_DLY                    = 12

 7115 23:07:05.364659  SEMI_OPEN_CA_PICK_MCK_RATIO= 0

 7116 23:07:05.368312  DQ_AAMCK_DIV               = 4

 7117 23:07:05.371757  CA_AAMCK_DIV               = 4

 7118 23:07:05.374607  CA_ADMCK_DIV               = 4

 7119 23:07:05.378166  DQ_TRACK_CA_EN             = 0

 7120 23:07:05.378271  CA_PICK                    = 1600

 7121 23:07:05.381530  CA_MCKIO                   = 1600

 7122 23:07:05.385201  MCKIO_SEMI                 = 0

 7123 23:07:05.388716  PLL_FREQ                   = 3068

 7124 23:07:05.391800  DQ_UI_PI_RATIO             = 32

 7125 23:07:05.395723  CA_UI_PI_RATIO             = 0

 7126 23:07:05.398315  =================================== 

 7127 23:07:05.401960  =================================== 

 7128 23:07:05.402071  memory_type:LPDDR4         

 7129 23:07:05.404928  GP_NUM     : 10       

 7130 23:07:05.408670  SRAM_EN    : 1       

 7131 23:07:05.408770  MD32_EN    : 0       

 7132 23:07:05.411958  =================================== 

 7133 23:07:05.415592  [ANA_INIT] >>>>>>>>>>>>>> 

 7134 23:07:05.418663  <<<<<< [CONFIGURE PHASE]: ANA_TX

 7135 23:07:05.421843  >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL

 7136 23:07:05.426217  =================================== 

 7137 23:07:05.428608  data_rate = 3200,PCW = 0X7600

 7138 23:07:05.432005  =================================== 

 7139 23:07:05.435376  <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL

 7140 23:07:05.439004  >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 7141 23:07:05.445303  <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 7142 23:07:05.448908  >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2

 7143 23:07:05.452395  >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL

 7144 23:07:05.455378  <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL

 7145 23:07:05.458811  [ANA_INIT] flow start 

 7146 23:07:05.462094  [ANA_INIT] PLL >>>>>>>> 

 7147 23:07:05.462172  [ANA_INIT] PLL <<<<<<<< 

 7148 23:07:05.465359  [ANA_INIT] MIDPI >>>>>>>> 

 7149 23:07:05.469853  [ANA_INIT] MIDPI <<<<<<<< 

 7150 23:07:05.469927  [ANA_INIT] DLL >>>>>>>> 

 7151 23:07:05.472390  [ANA_INIT] DLL <<<<<<<< 

 7152 23:07:05.475854  [ANA_INIT] flow end 

 7153 23:07:05.478887  ============ LP4 DIFF to SE enter ============

 7154 23:07:05.481876  ============ LP4 DIFF to SE exit  ============

 7155 23:07:05.485094  [ANA_INIT] <<<<<<<<<<<<< 

 7156 23:07:05.488959  [Flow] Enable top DCM control >>>>> 

 7157 23:07:05.492564  [Flow] Enable top DCM control <<<<< 

 7158 23:07:05.495407  Enable DLL master slave shuffle 

 7159 23:07:05.499064  ============================================================== 

 7160 23:07:05.502148  Gating Mode config

 7161 23:07:05.508647  ============================================================== 

 7162 23:07:05.508731  Config description: 

 7163 23:07:05.518614  RX_GATING_MODE        0: Pulse Mode      1: Burst Mode(8UI)        2: Burst Mode(7UI)  3: Original Burst Mode

 7164 23:07:05.525645  RX_GATING_TRACK_MODE  0: Valid DLY Mode  1: Valid Mode (-like) 2: FIFO mode

 7165 23:07:05.528524  SELPH_MODE            0: By rank         1: By Phase 

 7166 23:07:05.535407  ============================================================== 

 7167 23:07:05.539215  GAT_TRACK_EN                 =  1

 7168 23:07:05.542008  RX_GATING_MODE               =  2

 7169 23:07:05.545804  RX_GATING_TRACK_MODE         =  2

 7170 23:07:05.549233  SELPH_MODE                   =  1

 7171 23:07:05.552369  PICG_EARLY_EN                =  1

 7172 23:07:05.552456  VALID_LAT_VALUE              =  1

 7173 23:07:05.558658  ============================================================== 

 7174 23:07:05.562061  Enter into Gating configuration >>>> 

 7175 23:07:05.565929  Exit from Gating configuration <<<< 

 7176 23:07:05.568999  Enter into  DVFS_PRE_config >>>>> 

 7177 23:07:05.579136  Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. 

 7178 23:07:05.582114  Exit from  DVFS_PRE_config <<<<< 

 7179 23:07:05.585729  Enter into PICG configuration >>>> 

 7180 23:07:05.588716  Exit from PICG configuration <<<< 

 7181 23:07:05.592537  [RX_INPUT] configuration >>>>> 

 7182 23:07:05.595473  [RX_INPUT] configuration <<<<< 

 7183 23:07:05.599193  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>

 7184 23:07:05.605734  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<

 7185 23:07:05.612604  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>

 7186 23:07:05.618940  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<

 7187 23:07:05.626123  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>

 7188 23:07:05.628908  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<

 7189 23:07:05.635996  [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 

 7190 23:07:05.639017  [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 

 7191 23:07:05.642523  [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 

 7192 23:07:05.645811  [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 

 7193 23:07:05.648888  [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 

 7194 23:07:05.655429  [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5

 7195 23:07:05.658936  =================================== 

 7196 23:07:05.662551  LPDDR4 DRAM CONFIGURATION

 7197 23:07:05.665970  =================================== 

 7198 23:07:05.666086  EX_ROW_EN[0]    = 0x0

 7199 23:07:05.669647  EX_ROW_EN[1]    = 0x0

 7200 23:07:05.669772  LP4Y_EN      = 0x0

 7201 23:07:05.672449  WORK_FSP     = 0x1

 7202 23:07:05.672536  WL           = 0x5

 7203 23:07:05.676250  RL           = 0x5

 7204 23:07:05.676375  BL           = 0x2

 7205 23:07:05.679217  RPST         = 0x0

 7206 23:07:05.679304  RD_PRE       = 0x0

 7207 23:07:05.682552  WR_PRE       = 0x1

 7208 23:07:05.682666  WR_PST       = 0x1

 7209 23:07:05.685937  DBI_WR       = 0x0

 7210 23:07:05.686047  DBI_RD       = 0x0

 7211 23:07:05.688897  OTF          = 0x1

 7212 23:07:05.692834  =================================== 

 7213 23:07:05.695712  [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 

 7214 23:07:05.699518  [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 

 7215 23:07:05.705850  [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5

 7216 23:07:05.709579  =================================== 

 7217 23:07:05.709702  LPDDR4 DRAM CONFIGURATION

 7218 23:07:05.712561  =================================== 

 7219 23:07:05.715957  EX_ROW_EN[0]    = 0x10

 7220 23:07:05.719391  EX_ROW_EN[1]    = 0x0

 7221 23:07:05.719473  LP4Y_EN      = 0x0

 7222 23:07:05.723036  WORK_FSP     = 0x1

 7223 23:07:05.723119  WL           = 0x5

 7224 23:07:05.725822  RL           = 0x5

 7225 23:07:05.725904  BL           = 0x2

 7226 23:07:05.729225  RPST         = 0x0

 7227 23:07:05.729307  RD_PRE       = 0x0

 7228 23:07:05.732878  WR_PRE       = 0x1

 7229 23:07:05.732960  WR_PST       = 0x1

 7230 23:07:05.736008  DBI_WR       = 0x0

 7231 23:07:05.736090  DBI_RD       = 0x0

 7232 23:07:05.739876  OTF          = 0x1

 7233 23:07:05.742661  =================================== 

 7234 23:07:05.749042  [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit

 7235 23:07:05.749125  ==

 7236 23:07:05.752466  Dram Type= 6, Freq= 0, CH_0, rank 0

 7237 23:07:05.755943  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7238 23:07:05.756025  ==

 7239 23:07:05.759352  [Duty_Offset_Calibration]

 7240 23:07:05.759433  	B0:2	B1:-1	CA:1

 7241 23:07:05.759498  

 7242 23:07:05.762184  [DutyScan_Calibration_Flow] k_type=0

 7243 23:07:05.771689  

 7244 23:07:05.771770  ==CLK 0==

 7245 23:07:05.775219  Final CLK duty delay cell = -4

 7246 23:07:05.778929  [-4] MAX Duty = 5031%(X100), DQS PI = 6

 7247 23:07:05.782345  [-4] MIN Duty = 4844%(X100), DQS PI = 32

 7248 23:07:05.785761  [-4] AVG Duty = 4937%(X100)

 7249 23:07:05.785842  

 7250 23:07:05.788880  CH0 CLK Duty spec in!! Max-Min= 187%

 7251 23:07:05.792464  [DutyScan_Calibration_Flow] ====Done====

 7252 23:07:05.792545  

 7253 23:07:05.795278  [DutyScan_Calibration_Flow] k_type=1

 7254 23:07:05.811266  

 7255 23:07:05.811349  ==DQS 0 ==

 7256 23:07:05.815030  Final DQS duty delay cell = 0

 7257 23:07:05.818081  [0] MAX Duty = 5125%(X100), DQS PI = 56

 7258 23:07:05.821547  [0] MIN Duty = 5031%(X100), DQS PI = 12

 7259 23:07:05.824645  [0] AVG Duty = 5078%(X100)

 7260 23:07:05.824727  

 7261 23:07:05.824791  ==DQS 1 ==

 7262 23:07:05.828388  Final DQS duty delay cell = -4

 7263 23:07:05.831310  [-4] MAX Duty = 5093%(X100), DQS PI = 0

 7264 23:07:05.835064  [-4] MIN Duty = 5031%(X100), DQS PI = 20

 7265 23:07:05.838601  [-4] AVG Duty = 5062%(X100)

 7266 23:07:05.838683  

 7267 23:07:05.841832  CH0 DQS 0 Duty spec in!! Max-Min= 94%

 7268 23:07:05.841914  

 7269 23:07:05.844716  CH0 DQS 1 Duty spec in!! Max-Min= 62%

 7270 23:07:05.848767  [DutyScan_Calibration_Flow] ====Done====

 7271 23:07:05.848849  

 7272 23:07:05.851628  [DutyScan_Calibration_Flow] k_type=3

 7273 23:07:05.868964  

 7274 23:07:05.869045  ==DQM 0 ==

 7275 23:07:05.872228  Final DQM duty delay cell = 0

 7276 23:07:05.875816  [0] MAX Duty = 5000%(X100), DQS PI = 20

 7277 23:07:05.878932  [0] MIN Duty = 4875%(X100), DQS PI = 6

 7278 23:07:05.879014  [0] AVG Duty = 4937%(X100)

 7279 23:07:05.882581  

 7280 23:07:05.882663  ==DQM 1 ==

 7281 23:07:05.885923  Final DQM duty delay cell = 0

 7282 23:07:05.888906  [0] MAX Duty = 5250%(X100), DQS PI = 58

 7283 23:07:05.892437  [0] MIN Duty = 4969%(X100), DQS PI = 20

 7284 23:07:05.892519  [0] AVG Duty = 5109%(X100)

 7285 23:07:05.892585  

 7286 23:07:05.898892  CH0 DQM 0 Duty spec in!! Max-Min= 125%

 7287 23:07:05.898977  

 7288 23:07:05.902255  CH0 DQM 1 Duty spec in!! Max-Min= 281%

 7289 23:07:05.906089  [DutyScan_Calibration_Flow] ====Done====

 7290 23:07:05.906171  

 7291 23:07:05.908609  [DutyScan_Calibration_Flow] k_type=2

 7292 23:07:05.925287  

 7293 23:07:05.925372  ==DQ 0 ==

 7294 23:07:05.928627  Final DQ duty delay cell = -4

 7295 23:07:05.931982  [-4] MAX Duty = 5031%(X100), DQS PI = 56

 7296 23:07:05.935639  [-4] MIN Duty = 4844%(X100), DQS PI = 28

 7297 23:07:05.938443  [-4] AVG Duty = 4937%(X100)

 7298 23:07:05.938524  

 7299 23:07:05.938587  ==DQ 1 ==

 7300 23:07:05.942174  Final DQ duty delay cell = 0

 7301 23:07:05.945099  [0] MAX Duty = 5031%(X100), DQS PI = 30

 7302 23:07:05.948240  [0] MIN Duty = 4938%(X100), DQS PI = 4

 7303 23:07:05.948322  [0] AVG Duty = 4984%(X100)

 7304 23:07:05.951874  

 7305 23:07:05.955405  CH0 DQ 0 Duty spec in!! Max-Min= 187%

 7306 23:07:05.955487  

 7307 23:07:05.958411  CH0 DQ 1 Duty spec in!! Max-Min= 93%

 7308 23:07:05.961860  [DutyScan_Calibration_Flow] ====Done====

 7309 23:07:05.961947  ==

 7310 23:07:05.964933  Dram Type= 6, Freq= 0, CH_1, rank 0

 7311 23:07:05.968401  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7312 23:07:05.968483  ==

 7313 23:07:05.971934  [Duty_Offset_Calibration]

 7314 23:07:05.972015  	B0:1	B1:1	CA:2

 7315 23:07:05.972079  

 7316 23:07:05.975681  [DutyScan_Calibration_Flow] k_type=0

 7317 23:07:05.985651  

 7318 23:07:05.985731  ==CLK 0==

 7319 23:07:05.989085  Final CLK duty delay cell = 0

 7320 23:07:05.992667  [0] MAX Duty = 5187%(X100), DQS PI = 24

 7321 23:07:05.995204  [0] MIN Duty = 4938%(X100), DQS PI = 58

 7322 23:07:05.995285  [0] AVG Duty = 5062%(X100)

 7323 23:07:05.998721  

 7324 23:07:06.002269  CH1 CLK Duty spec in!! Max-Min= 249%

 7325 23:07:06.005870  [DutyScan_Calibration_Flow] ====Done====

 7326 23:07:06.005951  

 7327 23:07:06.009027  [DutyScan_Calibration_Flow] k_type=1

 7328 23:07:06.025548  

 7329 23:07:06.025630  ==DQS 0 ==

 7330 23:07:06.028432  Final DQS duty delay cell = 0

 7331 23:07:06.031680  [0] MAX Duty = 5062%(X100), DQS PI = 20

 7332 23:07:06.035251  [0] MIN Duty = 4813%(X100), DQS PI = 52

 7333 23:07:06.035332  [0] AVG Duty = 4937%(X100)

 7334 23:07:06.038919  

 7335 23:07:06.038999  ==DQS 1 ==

 7336 23:07:06.041867  Final DQS duty delay cell = 0

 7337 23:07:06.045431  [0] MAX Duty = 5031%(X100), DQS PI = 34

 7338 23:07:06.048527  [0] MIN Duty = 4938%(X100), DQS PI = 12

 7339 23:07:06.051929  [0] AVG Duty = 4984%(X100)

 7340 23:07:06.052010  

 7341 23:07:06.055716  CH1 DQS 0 Duty spec in!! Max-Min= 249%

 7342 23:07:06.055797  

 7343 23:07:06.058431  CH1 DQS 1 Duty spec in!! Max-Min= 93%

 7344 23:07:06.062000  [DutyScan_Calibration_Flow] ====Done====

 7345 23:07:06.062094  

 7346 23:07:06.064999  [DutyScan_Calibration_Flow] k_type=3

 7347 23:07:06.081826  

 7348 23:07:06.081908  ==DQM 0 ==

 7349 23:07:06.085473  Final DQM duty delay cell = 0

 7350 23:07:06.089059  [0] MAX Duty = 5187%(X100), DQS PI = 20

 7351 23:07:06.092259  [0] MIN Duty = 4813%(X100), DQS PI = 50

 7352 23:07:06.092341  [0] AVG Duty = 5000%(X100)

 7353 23:07:06.095757  

 7354 23:07:06.095838  ==DQM 1 ==

 7355 23:07:06.098981  Final DQM duty delay cell = 0

 7356 23:07:06.102199  [0] MAX Duty = 5156%(X100), DQS PI = 10

 7357 23:07:06.105617  [0] MIN Duty = 4875%(X100), DQS PI = 20

 7358 23:07:06.108531  [0] AVG Duty = 5015%(X100)

 7359 23:07:06.108612  

 7360 23:07:06.112197  CH1 DQM 0 Duty spec in!! Max-Min= 374%

 7361 23:07:06.112279  

 7362 23:07:06.115518  CH1 DQM 1 Duty spec in!! Max-Min= 281%

 7363 23:07:06.118973  [DutyScan_Calibration_Flow] ====Done====

 7364 23:07:06.119055  

 7365 23:07:06.121752  [DutyScan_Calibration_Flow] k_type=2

 7366 23:07:06.139597  

 7367 23:07:06.139678  ==DQ 0 ==

 7368 23:07:06.142476  Final DQ duty delay cell = 0

 7369 23:07:06.145981  [0] MAX Duty = 5156%(X100), DQS PI = 20

 7370 23:07:06.149307  [0] MIN Duty = 4907%(X100), DQS PI = 52

 7371 23:07:06.149388  [0] AVG Duty = 5031%(X100)

 7372 23:07:06.149453  

 7373 23:07:06.155496  ==DQ 1 ==

 7374 23:07:06.155955  Final DQ duty delay cell = 0

 7375 23:07:06.159411  [0] MAX Duty = 5093%(X100), DQS PI = 8

 7376 23:07:06.162783  [0] MIN Duty = 5031%(X100), DQS PI = 0

 7377 23:07:06.162865  [0] AVG Duty = 5062%(X100)

 7378 23:07:06.162930  

 7379 23:07:06.165789  CH1 DQ 0 Duty spec in!! Max-Min= 249%

 7380 23:07:06.165871  

 7381 23:07:06.169403  CH1 DQ 1 Duty spec in!! Max-Min= 62%

 7382 23:07:06.175594  [DutyScan_Calibration_Flow] ====Done====

 7383 23:07:06.178986  nWR fixed to 30

 7384 23:07:06.179068  [ModeRegInit_LP4] CH0 RK0

 7385 23:07:06.182326  [ModeRegInit_LP4] CH0 RK1

 7386 23:07:06.185970  [ModeRegInit_LP4] CH1 RK0

 7387 23:07:06.186052  [ModeRegInit_LP4] CH1 RK1

 7388 23:07:06.189136  match AC timing 5

 7389 23:07:06.192331  dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1

 7390 23:07:06.196127  SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON

 7391 23:07:06.202340  [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14

 7392 23:07:06.205672  [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29

 7393 23:07:06.212144  [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)

 7394 23:07:06.212227  [MiockJmeterHQA]

 7395 23:07:06.212291  

 7396 23:07:06.215707  [DramcMiockJmeter] u1RxGatingPI = 0

 7397 23:07:06.218810  0 : 4252, 4027

 7398 23:07:06.218909  4 : 4363, 4137

 7399 23:07:06.218976  8 : 4253, 4027

 7400 23:07:06.222328  12 : 4363, 4138

 7401 23:07:06.222470  16 : 4253, 4026

 7402 23:07:06.225740  20 : 4252, 4027

 7403 23:07:06.225823  24 : 4253, 4026

 7404 23:07:06.229290  28 : 4255, 4030

 7405 23:07:06.229374  32 : 4363, 4137

 7406 23:07:06.229439  36 : 4252, 4027

 7407 23:07:06.232291  40 : 4250, 4027

 7408 23:07:06.232374  44 : 4250, 4027

 7409 23:07:06.235959  48 : 4252, 4030

 7410 23:07:06.236042  52 : 4250, 4027

 7411 23:07:06.239064  56 : 4363, 4137

 7412 23:07:06.239147  60 : 4361, 4138

 7413 23:07:06.239212  64 : 4250, 4026

 7414 23:07:06.242037  68 : 4250, 4027

 7415 23:07:06.242120  72 : 4250, 4027

 7416 23:07:06.245403  76 : 4253, 4027

 7417 23:07:06.245486  80 : 4252, 4030

 7418 23:07:06.249159  84 : 4360, 4137

 7419 23:07:06.249242  88 : 4250, 4027

 7420 23:07:06.252091  92 : 4250, 4027

 7421 23:07:06.252203  96 : 4250, 3371

 7422 23:07:06.252272  100 : 4252, 0

 7423 23:07:06.255739  104 : 4250, 0

 7424 23:07:06.255822  108 : 4250, 0

 7425 23:07:06.258810  112 : 4249, 0

 7426 23:07:06.258893  116 : 4250, 0

 7427 23:07:06.258958  120 : 4250, 0

 7428 23:07:06.262903  124 : 4252, 0

 7429 23:07:06.262986  128 : 4366, 0

 7430 23:07:06.263052  132 : 4361, 0

 7431 23:07:06.265973  136 : 4250, 0

 7432 23:07:06.266056  140 : 4251, 0

 7433 23:07:06.269208  144 : 4253, 0

 7434 23:07:06.269291  148 : 4250, 0

 7435 23:07:06.269356  152 : 4250, 0

 7436 23:07:06.272950  156 : 4250, 0

 7437 23:07:06.273033  160 : 4250, 0

 7438 23:07:06.275933  164 : 4252, 0

 7439 23:07:06.276015  168 : 4361, 0

 7440 23:07:06.276081  172 : 4360, 0

 7441 23:07:06.279366  176 : 4250, 0

 7442 23:07:06.279477  180 : 4360, 0

 7443 23:07:06.282463  184 : 4361, 0

 7444 23:07:06.282546  188 : 4360, 0

 7445 23:07:06.282612  192 : 4252, 0

 7446 23:07:06.285889  196 : 4250, 0

 7447 23:07:06.285971  200 : 4250, 0

 7448 23:07:06.286036  204 : 4249, 0

 7449 23:07:06.289143  208 : 4250, 0

 7450 23:07:06.289227  212 : 4250, 95

 7451 23:07:06.292178  216 : 4250, 3665

 7452 23:07:06.292260  220 : 4361, 4138

 7453 23:07:06.295817  224 : 4250, 4027

 7454 23:07:06.295899  228 : 4250, 4026

 7455 23:07:06.299210  232 : 4250, 4027

 7456 23:07:06.299294  236 : 4253, 4029

 7457 23:07:06.302259  240 : 4250, 4027

 7458 23:07:06.302369  244 : 4252, 4029

 7459 23:07:06.302485  248 : 4361, 4137

 7460 23:07:06.305770  252 : 4250, 4027

 7461 23:07:06.305853  256 : 4250, 4027

 7462 23:07:06.308744  260 : 4360, 4137

 7463 23:07:06.308851  264 : 4250, 4026

 7464 23:07:06.312650  268 : 4250, 4027

 7465 23:07:06.312733  272 : 4361, 4138

 7466 23:07:06.315631  276 : 4250, 4027

 7467 23:07:06.315707  280 : 4250, 4026

 7468 23:07:06.319387  284 : 4250, 4027

 7469 23:07:06.319469  288 : 4250, 4027

 7470 23:07:06.322256  292 : 4250, 4027

 7471 23:07:06.322366  296 : 4250, 4026

 7472 23:07:06.322482  300 : 4361, 4137

 7473 23:07:06.325740  304 : 4250, 4027

 7474 23:07:06.325823  308 : 4250, 4027

 7475 23:07:06.329501  312 : 4360, 4137

 7476 23:07:06.329585  316 : 4250, 4026

 7477 23:07:06.332466  320 : 4250, 4027

 7478 23:07:06.332549  324 : 4363, 4140

 7479 23:07:06.335698  328 : 4250, 4027

 7480 23:07:06.335781  332 : 4252, 2938

 7481 23:07:06.339313  336 : 4250, 115

 7482 23:07:06.339397  

 7483 23:07:06.339462  	MIOCK jitter meter	ch=0

 7484 23:07:06.339522  

 7485 23:07:06.342145  1T = (336-100) = 236 dly cells

 7486 23:07:06.349296  Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps

 7487 23:07:06.349379  ==

 7488 23:07:06.352324  Dram Type= 6, Freq= 0, CH_0, rank 0

 7489 23:07:06.355928  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7490 23:07:06.356011  ==

 7491 23:07:06.362734  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 7492 23:07:06.365839  [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1

 7493 23:07:06.369656  [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1

 7494 23:07:06.375756  u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32

 7495 23:07:06.385698  [CA 0] Center 44 (14~75) winsize 62

 7496 23:07:06.389181  [CA 1] Center 43 (13~74) winsize 62

 7497 23:07:06.392136  [CA 2] Center 39 (10~68) winsize 59

 7498 23:07:06.395800  [CA 3] Center 39 (10~68) winsize 59

 7499 23:07:06.399185  [CA 4] Center 37 (7~67) winsize 61

 7500 23:07:06.402274  [CA 5] Center 37 (7~67) winsize 61

 7501 23:07:06.402381  

 7502 23:07:06.405577  [CmdBusTrainingLP45] Vref(ca) range 0: 32

 7503 23:07:06.405659  

 7504 23:07:06.408631  [CATrainingPosCal] consider 1 rank data

 7505 23:07:06.412222  u2DelayCellTimex100 = 275/100 ps

 7506 23:07:06.416259  CA0 delay=44 (14~75),Diff = 7 PI (24 cell)

 7507 23:07:06.422268  CA1 delay=43 (13~74),Diff = 6 PI (21 cell)

 7508 23:07:06.425651  CA2 delay=39 (10~68),Diff = 2 PI (7 cell)

 7509 23:07:06.429501  CA3 delay=39 (10~68),Diff = 2 PI (7 cell)

 7510 23:07:06.432017  CA4 delay=37 (7~67),Diff = 0 PI (0 cell)

 7511 23:07:06.435521  CA5 delay=37 (7~67),Diff = 0 PI (0 cell)

 7512 23:07:06.435603  

 7513 23:07:06.438922  CA PerBit enable=1, Macro0, CA PI delay=37

 7514 23:07:06.439003  

 7515 23:07:06.442365  [CBTSetCACLKResult] CA Dly = 37

 7516 23:07:06.445780  CS Dly: 10 (0~41)

 7517 23:07:06.448636  [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0

 7518 23:07:06.452337  [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0

 7519 23:07:06.452418  ==

 7520 23:07:06.455352  Dram Type= 6, Freq= 0, CH_0, rank 1

 7521 23:07:06.459052  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7522 23:07:06.462378  ==

 7523 23:07:06.465407  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 7524 23:07:06.468623  [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1

 7525 23:07:06.475174  [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1

 7526 23:07:06.478744  u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32

 7527 23:07:06.489511  [CA 0] Center 44 (14~75) winsize 62

 7528 23:07:06.492655  [CA 1] Center 44 (14~75) winsize 62

 7529 23:07:06.495789  [CA 2] Center 40 (11~69) winsize 59

 7530 23:07:06.499152  [CA 3] Center 39 (10~69) winsize 60

 7531 23:07:06.502873  [CA 4] Center 38 (9~67) winsize 59

 7532 23:07:06.506008  [CA 5] Center 37 (7~67) winsize 61

 7533 23:07:06.506101  

 7534 23:07:06.509190  [CmdBusTrainingLP45] Vref(ca) range 0: 32

 7535 23:07:06.509257  

 7536 23:07:06.512417  [CATrainingPosCal] consider 2 rank data

 7537 23:07:06.515726  u2DelayCellTimex100 = 275/100 ps

 7538 23:07:06.519412  CA0 delay=44 (14~75),Diff = 7 PI (24 cell)

 7539 23:07:06.526033  CA1 delay=44 (14~74),Diff = 7 PI (24 cell)

 7540 23:07:06.529336  CA2 delay=39 (11~68),Diff = 2 PI (7 cell)

 7541 23:07:06.532700  CA3 delay=39 (10~68),Diff = 2 PI (7 cell)

 7542 23:07:06.535751  CA4 delay=38 (9~67),Diff = 1 PI (3 cell)

 7543 23:07:06.539042  CA5 delay=37 (7~67),Diff = 0 PI (0 cell)

 7544 23:07:06.539127  

 7545 23:07:06.542532  CA PerBit enable=1, Macro0, CA PI delay=37

 7546 23:07:06.542625  

 7547 23:07:06.545833  [CBTSetCACLKResult] CA Dly = 37

 7548 23:07:06.549259  CS Dly: 11 (0~44)

 7549 23:07:06.552598  [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0

 7550 23:07:06.555801  [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0

 7551 23:07:06.555882  

 7552 23:07:06.559331  ----->DramcWriteLeveling(PI) begin...

 7553 23:07:06.559407  ==

 7554 23:07:06.562752  Dram Type= 6, Freq= 0, CH_0, rank 0

 7555 23:07:06.565850  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7556 23:07:06.569320  ==

 7557 23:07:06.569420  Write leveling (Byte 0): 32 => 32

 7558 23:07:06.572419  Write leveling (Byte 1): 27 => 27

 7559 23:07:06.575737  DramcWriteLeveling(PI) end<-----

 7560 23:07:06.575836  

 7561 23:07:06.575927  ==

 7562 23:07:06.579736  Dram Type= 6, Freq= 0, CH_0, rank 0

 7563 23:07:06.586010  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7564 23:07:06.586127  ==

 7565 23:07:06.586193  [Gating] SW mode calibration

 7566 23:07:06.596200  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0

 7567 23:07:06.599078  RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)

 7568 23:07:06.606018   1  4  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 7569 23:07:06.609687   1  4  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 7570 23:07:06.613072   1  4  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 7571 23:07:06.615874   1  4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 7572 23:07:06.622602   1  4 16 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)

 7573 23:07:06.625691   1  4 20 | B1->B0 | 2424 3434 | 0 0 | (0 0) (0 0)

 7574 23:07:06.629333   1  4 24 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)

 7575 23:07:06.635664   1  4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 7576 23:07:06.639472   1  5  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 7577 23:07:06.642599   1  5  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 7578 23:07:06.649293   1  5  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 7579 23:07:06.652448   1  5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 7580 23:07:06.656304   1  5 16 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)

 7581 23:07:06.662699   1  5 20 | B1->B0 | 3232 2323 | 1 0 | (1 0) (1 0)

 7582 23:07:06.665639   1  5 24 | B1->B0 | 2c2c 2323 | 1 0 | (1 0) (0 0)

 7583 23:07:06.669681   1  5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 7584 23:07:06.676184   1  6  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 7585 23:07:06.679112   1  6  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 7586 23:07:06.682341   1  6  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 7587 23:07:06.689141   1  6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 7588 23:07:06.692934   1  6 16 | B1->B0 | 2323 3535 | 0 1 | (0 0) (0 0)

 7589 23:07:06.696068   1  6 20 | B1->B0 | 2d2d 4646 | 1 0 | (0 0) (0 0)

 7590 23:07:06.702557   1  6 24 | B1->B0 | 3e3e 4646 | 1 0 | (0 0) (0 0)

 7591 23:07:06.706248   1  6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 7592 23:07:06.709342   1  7  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 7593 23:07:06.713097   1  7  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 7594 23:07:06.719580   1  7  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 7595 23:07:06.722946   1  7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 7596 23:07:06.726605   1  7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 7597 23:07:06.732826   1  7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 7598 23:07:06.735951   1  7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 7599 23:07:06.739263   1  7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7600 23:07:06.745745   1  8  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7601 23:07:06.749209   1  8  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7602 23:07:06.752701   1  8  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7603 23:07:06.759846   1  8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7604 23:07:06.762817   1  8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7605 23:07:06.766275   1  8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7606 23:07:06.772949   1  8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7607 23:07:06.776118   1  8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7608 23:07:06.779662   1  9  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7609 23:07:06.786329   1  9  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7610 23:07:06.790005   1  9  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7611 23:07:06.792888   1  9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 7612 23:07:06.796163   1  9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 7613 23:07:06.803061   1  9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 7614 23:07:06.806730  Total UI for P1: 0, mck2ui 16

 7615 23:07:06.809326  best dqsien dly found for B0: ( 1,  9, 14)

 7616 23:07:06.813139   1  9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 7617 23:07:06.816607   1  9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 7618 23:07:06.819406  Total UI for P1: 0, mck2ui 16

 7619 23:07:06.823164  best dqsien dly found for B1: ( 1,  9, 20)

 7620 23:07:06.826228  best DQS0 dly(MCK, UI, PI) = (1, 9, 14)

 7621 23:07:06.829589  best DQS1 dly(MCK, UI, PI) = (1, 9, 20)

 7622 23:07:06.829671  

 7623 23:07:06.836381  best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)

 7624 23:07:06.839424  best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)

 7625 23:07:06.843040  [Gating] SW calibration Done

 7626 23:07:06.843122  ==

 7627 23:07:06.845812  Dram Type= 6, Freq= 0, CH_0, rank 0

 7628 23:07:06.849829  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7629 23:07:06.849912  ==

 7630 23:07:06.849977  RX Vref Scan: 0

 7631 23:07:06.850036  

 7632 23:07:06.852635  RX Vref 0 -> 0, step: 1

 7633 23:07:06.852716  

 7634 23:07:06.856453  RX Delay 0 -> 252, step: 8

 7635 23:07:06.859420  iDelay=200, Bit 0, Center 131 (80 ~ 183) 104

 7636 23:07:06.863399  iDelay=200, Bit 1, Center 135 (80 ~ 191) 112

 7637 23:07:06.866153  iDelay=200, Bit 2, Center 127 (72 ~ 183) 112

 7638 23:07:06.872720  iDelay=200, Bit 3, Center 127 (72 ~ 183) 112

 7639 23:07:06.876236  iDelay=200, Bit 4, Center 135 (80 ~ 191) 112

 7640 23:07:06.879340  iDelay=200, Bit 5, Center 119 (64 ~ 175) 112

 7641 23:07:06.883354  iDelay=200, Bit 6, Center 143 (88 ~ 199) 112

 7642 23:07:06.886281  iDelay=200, Bit 7, Center 139 (88 ~ 191) 104

 7643 23:07:06.892654  iDelay=200, Bit 8, Center 111 (56 ~ 167) 112

 7644 23:07:06.896639  iDelay=200, Bit 9, Center 115 (64 ~ 167) 104

 7645 23:07:06.899488  iDelay=200, Bit 10, Center 123 (72 ~ 175) 104

 7646 23:07:06.902515  iDelay=200, Bit 11, Center 123 (72 ~ 175) 104

 7647 23:07:06.906607  iDelay=200, Bit 12, Center 131 (72 ~ 191) 120

 7648 23:07:06.912578  iDelay=200, Bit 13, Center 131 (80 ~ 183) 104

 7649 23:07:06.915981  iDelay=200, Bit 14, Center 135 (80 ~ 191) 112

 7650 23:07:06.919953  iDelay=200, Bit 15, Center 135 (80 ~ 191) 112

 7651 23:07:06.920035  ==

 7652 23:07:06.923175  Dram Type= 6, Freq= 0, CH_0, rank 0

 7653 23:07:06.926525  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7654 23:07:06.926608  ==

 7655 23:07:06.929424  DQS Delay:

 7656 23:07:06.929506  DQS0 = 0, DQS1 = 0

 7657 23:07:06.932787  DQM Delay:

 7658 23:07:06.932868  DQM0 = 132, DQM1 = 125

 7659 23:07:06.936097  DQ Delay:

 7660 23:07:06.939561  DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127

 7661 23:07:06.942819  DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =139

 7662 23:07:06.946620  DQ8 =111, DQ9 =115, DQ10 =123, DQ11 =123

 7663 23:07:06.949342  DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135

 7664 23:07:06.949424  

 7665 23:07:06.949488  

 7666 23:07:06.949548  ==

 7667 23:07:06.953028  Dram Type= 6, Freq= 0, CH_0, rank 0

 7668 23:07:06.956830  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7669 23:07:06.956912  ==

 7670 23:07:06.956977  

 7671 23:07:06.957037  

 7672 23:07:06.959485  	TX Vref Scan disable

 7673 23:07:06.963095   == TX Byte 0 ==

 7674 23:07:06.966335  Update DQ  dly =989 (3 ,6, 29)  DQ  OEN =(3 ,3)

 7675 23:07:06.970072  Update DQM dly =989 (3 ,6, 29)  DQM OEN =(3 ,3)

 7676 23:07:06.973330   == TX Byte 1 ==

 7677 23:07:06.976206  Update DQ  dly =983 (3 ,6, 23)  DQ  OEN =(3 ,3)

 7678 23:07:06.979533  Update DQM dly =983 (3 ,6, 23)  DQM OEN =(3 ,3)

 7679 23:07:06.979623  ==

 7680 23:07:06.983124  Dram Type= 6, Freq= 0, CH_0, rank 0

 7681 23:07:06.986248  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7682 23:07:06.986357  ==

 7683 23:07:07.002252  

 7684 23:07:07.005704  TX Vref early break, caculate TX vref

 7685 23:07:07.009191  TX Vref=16, minBit 1, minWin=21, winSum=353

 7686 23:07:07.012041  TX Vref=18, minBit 1, minWin=21, winSum=364

 7687 23:07:07.015684  TX Vref=20, minBit 4, minWin=22, winSum=376

 7688 23:07:07.018622  TX Vref=22, minBit 1, minWin=23, winSum=386

 7689 23:07:07.022409  TX Vref=24, minBit 1, minWin=23, winSum=399

 7690 23:07:07.029321  TX Vref=26, minBit 7, minWin=23, winSum=401

 7691 23:07:07.032300  TX Vref=28, minBit 4, minWin=24, winSum=413

 7692 23:07:07.035962  TX Vref=30, minBit 4, minWin=24, winSum=411

 7693 23:07:07.039031  TX Vref=32, minBit 4, minWin=23, winSum=405

 7694 23:07:07.042794  TX Vref=34, minBit 4, minWin=23, winSum=393

 7695 23:07:07.046166  TX Vref=36, minBit 0, minWin=23, winSum=384

 7696 23:07:07.052558  [TxChooseVref] Worse bit 4, Min win 24, Win sum 413, Final Vref 28

 7697 23:07:07.052641  

 7698 23:07:07.055600  Final TX Range 0 Vref 28

 7699 23:07:07.055682  

 7700 23:07:07.055764  ==

 7701 23:07:07.059568  Dram Type= 6, Freq= 0, CH_0, rank 0

 7702 23:07:07.062379  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7703 23:07:07.062503  ==

 7704 23:07:07.062568  

 7705 23:07:07.062628  

 7706 23:07:07.066092  	TX Vref Scan disable

 7707 23:07:07.072580  [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps

 7708 23:07:07.072662   == TX Byte 0 ==

 7709 23:07:07.075803  u2DelayCellOfst[0]=17 cells (5 PI)

 7710 23:07:07.079201  u2DelayCellOfst[1]=21 cells (6 PI)

 7711 23:07:07.082571  u2DelayCellOfst[2]=14 cells (4 PI)

 7712 23:07:07.085776  u2DelayCellOfst[3]=14 cells (4 PI)

 7713 23:07:07.089112  u2DelayCellOfst[4]=10 cells (3 PI)

 7714 23:07:07.092753  u2DelayCellOfst[5]=0 cells (0 PI)

 7715 23:07:07.096354  u2DelayCellOfst[6]=21 cells (6 PI)

 7716 23:07:07.099221  u2DelayCellOfst[7]=21 cells (6 PI)

 7717 23:07:07.102924  Update DQ  dly =986 (3 ,6, 26)  DQ  OEN =(3 ,3)

 7718 23:07:07.105900  Update DQM dly =989 (3 ,6, 29)  DQM OEN =(3 ,3)

 7719 23:07:07.109098   == TX Byte 1 ==

 7720 23:07:07.109194  u2DelayCellOfst[8]=0 cells (0 PI)

 7721 23:07:07.112316  u2DelayCellOfst[9]=0 cells (0 PI)

 7722 23:07:07.116043  u2DelayCellOfst[10]=7 cells (2 PI)

 7723 23:07:07.119011  u2DelayCellOfst[11]=0 cells (0 PI)

 7724 23:07:07.122658  u2DelayCellOfst[12]=14 cells (4 PI)

 7725 23:07:07.125620  u2DelayCellOfst[13]=10 cells (3 PI)

 7726 23:07:07.128944  u2DelayCellOfst[14]=17 cells (5 PI)

 7727 23:07:07.133004  u2DelayCellOfst[15]=10 cells (3 PI)

 7728 23:07:07.135899  Update DQ  dly =981 (3 ,6, 21)  DQ  OEN =(3 ,3)

 7729 23:07:07.142653  Update DQM dly =983 (3 ,6, 23)  DQM OEN =(3 ,3)

 7730 23:07:07.142761  DramC Write-DBI on

 7731 23:07:07.142851  ==

 7732 23:07:07.145743  Dram Type= 6, Freq= 0, CH_0, rank 0

 7733 23:07:07.149279  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7734 23:07:07.149379  ==

 7735 23:07:07.152729  

 7736 23:07:07.152826  

 7737 23:07:07.152915  	TX Vref Scan disable

 7738 23:07:07.155715   == TX Byte 0 ==

 7739 23:07:07.159126  Update DQM dly =733 (2 ,6, 29)  DQM OEN =(3 ,3)

 7740 23:07:07.162872   == TX Byte 1 ==

 7741 23:07:07.165821  Update DQM dly =725 (2 ,6, 21)  DQM OEN =(3 ,3)

 7742 23:07:07.165961  DramC Write-DBI off

 7743 23:07:07.169404  

 7744 23:07:07.169487  [DATLAT]

 7745 23:07:07.169549  Freq=1600, CH0 RK0

 7746 23:07:07.169607  

 7747 23:07:07.172906  DATLAT Default: 0xf

 7748 23:07:07.173009  0, 0xFFFF, sum = 0

 7749 23:07:07.176267  1, 0xFFFF, sum = 0

 7750 23:07:07.176365  2, 0xFFFF, sum = 0

 7751 23:07:07.179082  3, 0xFFFF, sum = 0

 7752 23:07:07.179178  4, 0xFFFF, sum = 0

 7753 23:07:07.182700  5, 0xFFFF, sum = 0

 7754 23:07:07.182774  6, 0xFFFF, sum = 0

 7755 23:07:07.186247  7, 0xFFFF, sum = 0

 7756 23:07:07.189565  8, 0xFFFF, sum = 0

 7757 23:07:07.189664  9, 0xFFFF, sum = 0

 7758 23:07:07.192837  10, 0xFFFF, sum = 0

 7759 23:07:07.192934  11, 0xFFFF, sum = 0

 7760 23:07:07.196453  12, 0xFFFF, sum = 0

 7761 23:07:07.196550  13, 0xFFFF, sum = 0

 7762 23:07:07.199536  14, 0x0, sum = 1

 7763 23:07:07.199631  15, 0x0, sum = 2

 7764 23:07:07.202718  16, 0x0, sum = 3

 7765 23:07:07.202813  17, 0x0, sum = 4

 7766 23:07:07.202902  best_step = 15

 7767 23:07:07.205908  

 7768 23:07:07.206007  ==

 7769 23:07:07.209050  Dram Type= 6, Freq= 0, CH_0, rank 0

 7770 23:07:07.212773  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7771 23:07:07.212868  ==

 7772 23:07:07.212963  RX Vref Scan: 1

 7773 23:07:07.213051  

 7774 23:07:07.216038  Set Vref Range= 24 -> 127

 7775 23:07:07.216131  

 7776 23:07:07.219351  RX Vref 24 -> 127, step: 1

 7777 23:07:07.219449  

 7778 23:07:07.222841  RX Delay 11 -> 252, step: 4

 7779 23:07:07.222936  

 7780 23:07:07.226146  Set Vref, RX VrefLevel [Byte0]: 24

 7781 23:07:07.229532                           [Byte1]: 24

 7782 23:07:07.229602  

 7783 23:07:07.232865  Set Vref, RX VrefLevel [Byte0]: 25

 7784 23:07:07.236151                           [Byte1]: 25

 7785 23:07:07.236253  

 7786 23:07:07.239481  Set Vref, RX VrefLevel [Byte0]: 26

 7787 23:07:07.242835                           [Byte1]: 26

 7788 23:07:07.246178  

 7789 23:07:07.246280  Set Vref, RX VrefLevel [Byte0]: 27

 7790 23:07:07.249421                           [Byte1]: 27

 7791 23:07:07.254176  

 7792 23:07:07.254278  Set Vref, RX VrefLevel [Byte0]: 28

 7793 23:07:07.256964                           [Byte1]: 28

 7794 23:07:07.261593  

 7795 23:07:07.261664  Set Vref, RX VrefLevel [Byte0]: 29

 7796 23:07:07.264965                           [Byte1]: 29

 7797 23:07:07.269375  

 7798 23:07:07.269479  Set Vref, RX VrefLevel [Byte0]: 30

 7799 23:07:07.272500                           [Byte1]: 30

 7800 23:07:07.276423  

 7801 23:07:07.276504  Set Vref, RX VrefLevel [Byte0]: 31

 7802 23:07:07.279846                           [Byte1]: 31

 7803 23:07:07.284511  

 7804 23:07:07.284606  Set Vref, RX VrefLevel [Byte0]: 32

 7805 23:07:07.287269                           [Byte1]: 32

 7806 23:07:07.291698  

 7807 23:07:07.291771  Set Vref, RX VrefLevel [Byte0]: 33

 7808 23:07:07.295115                           [Byte1]: 33

 7809 23:07:07.299177  

 7810 23:07:07.299258  Set Vref, RX VrefLevel [Byte0]: 34

 7811 23:07:07.302465                           [Byte1]: 34

 7812 23:07:07.306720  

 7813 23:07:07.306789  Set Vref, RX VrefLevel [Byte0]: 35

 7814 23:07:07.310302                           [Byte1]: 35

 7815 23:07:07.315084  

 7816 23:07:07.315153  Set Vref, RX VrefLevel [Byte0]: 36

 7817 23:07:07.318169                           [Byte1]: 36

 7818 23:07:07.322211  

 7819 23:07:07.322305  Set Vref, RX VrefLevel [Byte0]: 37

 7820 23:07:07.325530                           [Byte1]: 37

 7821 23:07:07.329913  

 7822 23:07:07.330021  Set Vref, RX VrefLevel [Byte0]: 38

 7823 23:07:07.333526                           [Byte1]: 38

 7824 23:07:07.337632  

 7825 23:07:07.337702  Set Vref, RX VrefLevel [Byte0]: 39

 7826 23:07:07.340599                           [Byte1]: 39

 7827 23:07:07.345051  

 7828 23:07:07.345119  Set Vref, RX VrefLevel [Byte0]: 40

 7829 23:07:07.348745                           [Byte1]: 40

 7830 23:07:07.352630  

 7831 23:07:07.352699  Set Vref, RX VrefLevel [Byte0]: 41

 7832 23:07:07.355786                           [Byte1]: 41

 7833 23:07:07.360808  

 7834 23:07:07.360907  Set Vref, RX VrefLevel [Byte0]: 42

 7835 23:07:07.363810                           [Byte1]: 42

 7836 23:07:07.368152  

 7837 23:07:07.368226  Set Vref, RX VrefLevel [Byte0]: 43

 7838 23:07:07.371133                           [Byte1]: 43

 7839 23:07:07.375524  

 7840 23:07:07.375592  Set Vref, RX VrefLevel [Byte0]: 44

 7841 23:07:07.379242                           [Byte1]: 44

 7842 23:07:07.382866  

 7843 23:07:07.382933  Set Vref, RX VrefLevel [Byte0]: 45

 7844 23:07:07.386529                           [Byte1]: 45

 7845 23:07:07.390631  

 7846 23:07:07.390714  Set Vref, RX VrefLevel [Byte0]: 46

 7847 23:07:07.394365                           [Byte1]: 46

 7848 23:07:07.398563  

 7849 23:07:07.398634  Set Vref, RX VrefLevel [Byte0]: 47

 7850 23:07:07.401984                           [Byte1]: 47

 7851 23:07:07.406373  

 7852 23:07:07.406502  Set Vref, RX VrefLevel [Byte0]: 48

 7853 23:07:07.409547                           [Byte1]: 48

 7854 23:07:07.413306  

 7855 23:07:07.413377  Set Vref, RX VrefLevel [Byte0]: 49

 7856 23:07:07.416880                           [Byte1]: 49

 7857 23:07:07.421577  

 7858 23:07:07.421674  Set Vref, RX VrefLevel [Byte0]: 50

 7859 23:07:07.424630                           [Byte1]: 50

 7860 23:07:07.428825  

 7861 23:07:07.428921  Set Vref, RX VrefLevel [Byte0]: 51

 7862 23:07:07.432211                           [Byte1]: 51

 7863 23:07:07.436524  

 7864 23:07:07.436620  Set Vref, RX VrefLevel [Byte0]: 52

 7865 23:07:07.440141                           [Byte1]: 52

 7866 23:07:07.443793  

 7867 23:07:07.443887  Set Vref, RX VrefLevel [Byte0]: 53

 7868 23:07:07.447713                           [Byte1]: 53

 7869 23:07:07.451405  

 7870 23:07:07.451501  Set Vref, RX VrefLevel [Byte0]: 54

 7871 23:07:07.455356                           [Byte1]: 54

 7872 23:07:07.459296  

 7873 23:07:07.459393  Set Vref, RX VrefLevel [Byte0]: 55

 7874 23:07:07.462836                           [Byte1]: 55

 7875 23:07:07.467024  

 7876 23:07:07.467121  Set Vref, RX VrefLevel [Byte0]: 56

 7877 23:07:07.470024                           [Byte1]: 56

 7878 23:07:07.474841  

 7879 23:07:07.474944  Set Vref, RX VrefLevel [Byte0]: 57

 7880 23:07:07.477527                           [Byte1]: 57

 7881 23:07:07.482403  

 7882 23:07:07.482489  Set Vref, RX VrefLevel [Byte0]: 58

 7883 23:07:07.485047                           [Byte1]: 58

 7884 23:07:07.489862  

 7885 23:07:07.489967  Set Vref, RX VrefLevel [Byte0]: 59

 7886 23:07:07.493490                           [Byte1]: 59

 7887 23:07:07.497510  

 7888 23:07:07.497602  Set Vref, RX VrefLevel [Byte0]: 60

 7889 23:07:07.500788                           [Byte1]: 60

 7890 23:07:07.504868  

 7891 23:07:07.504959  Set Vref, RX VrefLevel [Byte0]: 61

 7892 23:07:07.508355                           [Byte1]: 61

 7893 23:07:07.512951  

 7894 23:07:07.513047  Set Vref, RX VrefLevel [Byte0]: 62

 7895 23:07:07.515591                           [Byte1]: 62

 7896 23:07:07.520687  

 7897 23:07:07.520780  Set Vref, RX VrefLevel [Byte0]: 63

 7898 23:07:07.523464                           [Byte1]: 63

 7899 23:07:07.528405  

 7900 23:07:07.528477  Set Vref, RX VrefLevel [Byte0]: 64

 7901 23:07:07.530804                           [Byte1]: 64

 7902 23:07:07.535604  

 7903 23:07:07.535668  Set Vref, RX VrefLevel [Byte0]: 65

 7904 23:07:07.538929                           [Byte1]: 65

 7905 23:07:07.542801  

 7906 23:07:07.542868  Set Vref, RX VrefLevel [Byte0]: 66

 7907 23:07:07.546466                           [Byte1]: 66

 7908 23:07:07.550430  

 7909 23:07:07.550523  Set Vref, RX VrefLevel [Byte0]: 67

 7910 23:07:07.553951                           [Byte1]: 67

 7911 23:07:07.558492  

 7912 23:07:07.558560  Set Vref, RX VrefLevel [Byte0]: 68

 7913 23:07:07.561451                           [Byte1]: 68

 7914 23:07:07.565677  

 7915 23:07:07.565770  Set Vref, RX VrefLevel [Byte0]: 69

 7916 23:07:07.569332                           [Byte1]: 69

 7917 23:07:07.573251  

 7918 23:07:07.573342  Set Vref, RX VrefLevel [Byte0]: 70

 7919 23:07:07.576969                           [Byte1]: 70

 7920 23:07:07.581336  

 7921 23:07:07.581439  Set Vref, RX VrefLevel [Byte0]: 71

 7922 23:07:07.584446                           [Byte1]: 71

 7923 23:07:07.588879  

 7924 23:07:07.588994  Set Vref, RX VrefLevel [Byte0]: 72

 7925 23:07:07.591669                           [Byte1]: 72

 7926 23:07:07.596503  

 7927 23:07:07.596599  Set Vref, RX VrefLevel [Byte0]: 73

 7928 23:07:07.599443                           [Byte1]: 73

 7929 23:07:07.604260  

 7930 23:07:07.604356  Set Vref, RX VrefLevel [Byte0]: 74

 7931 23:07:07.607559                           [Byte1]: 74

 7932 23:07:07.611808  

 7933 23:07:07.611904  Set Vref, RX VrefLevel [Byte0]: 75

 7934 23:07:07.614608                           [Byte1]: 75

 7935 23:07:07.619150  

 7936 23:07:07.619240  Set Vref, RX VrefLevel [Byte0]: 76

 7937 23:07:07.622510                           [Byte1]: 76

 7938 23:07:07.626692  

 7939 23:07:07.626770  Final RX Vref Byte 0 = 53 to rank0

 7940 23:07:07.630645  Final RX Vref Byte 1 = 62 to rank0

 7941 23:07:07.633368  Final RX Vref Byte 0 = 53 to rank1

 7942 23:07:07.636747  Final RX Vref Byte 1 = 62 to rank1==

 7943 23:07:07.640289  Dram Type= 6, Freq= 0, CH_0, rank 0

 7944 23:07:07.646526  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7945 23:07:07.646599  ==

 7946 23:07:07.646660  DQS Delay:

 7947 23:07:07.646717  DQS0 = 0, DQS1 = 0

 7948 23:07:07.650177  DQM Delay:

 7949 23:07:07.650270  DQM0 = 129, DQM1 = 122

 7950 23:07:07.653231  DQ Delay:

 7951 23:07:07.656925  DQ0 =130, DQ1 =132, DQ2 =124, DQ3 =126

 7952 23:07:07.660113  DQ4 =132, DQ5 =118, DQ6 =138, DQ7 =138

 7953 23:07:07.663605  DQ8 =112, DQ9 =112, DQ10 =122, DQ11 =118

 7954 23:07:07.666909  DQ12 =128, DQ13 =126, DQ14 =132, DQ15 =132

 7955 23:07:07.666979  

 7956 23:07:07.667039  

 7957 23:07:07.667094  

 7958 23:07:07.670326  [DramC_TX_OE_Calibration] TA2

 7959 23:07:07.673103  Original DQ_B0 (3 6) =30, OEN = 27

 7960 23:07:07.676448  Original DQ_B1 (3 6) =30, OEN = 27

 7961 23:07:07.680185  24, 0x0, End_B0=24 End_B1=24

 7962 23:07:07.680274  25, 0x0, End_B0=25 End_B1=25

 7963 23:07:07.683360  26, 0x0, End_B0=26 End_B1=26

 7964 23:07:07.686960  27, 0x0, End_B0=27 End_B1=27

 7965 23:07:07.690316  28, 0x0, End_B0=28 End_B1=28

 7966 23:07:07.690442  29, 0x0, End_B0=29 End_B1=29

 7967 23:07:07.693935  30, 0x0, End_B0=30 End_B1=30

 7968 23:07:07.697366  31, 0x4141, End_B0=30 End_B1=30

 7969 23:07:07.700161  Byte0 end_step=30  best_step=27

 7970 23:07:07.703986  Byte1 end_step=30  best_step=27

 7971 23:07:07.706895  Byte0 TX OE(2T, 0.5T) = (3, 3)

 7972 23:07:07.706966  Byte1 TX OE(2T, 0.5T) = (3, 3)

 7973 23:07:07.707026  

 7974 23:07:07.707096  

 7975 23:07:07.717135  [DQSOSCAuto] RK0, (LSB)MR18= 0x1307, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 400 ps

 7976 23:07:07.720578  CH0 RK0: MR19=303, MR18=1307

 7977 23:07:07.724380  CH0_RK0: MR19=0x303, MR18=0x1307, DQSOSC=400, MR23=63, INC=23, DEC=15

 7978 23:07:07.727156  

 7979 23:07:07.730664  ----->DramcWriteLeveling(PI) begin...

 7980 23:07:07.730747  ==

 7981 23:07:07.733829  Dram Type= 6, Freq= 0, CH_0, rank 1

 7982 23:07:07.737350  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7983 23:07:07.737447  ==

 7984 23:07:07.740684  Write leveling (Byte 0): 34 => 34

 7985 23:07:07.743492  Write leveling (Byte 1): 28 => 28

 7986 23:07:07.747183  DramcWriteLeveling(PI) end<-----

 7987 23:07:07.747252  

 7988 23:07:07.747315  ==

 7989 23:07:07.750704  Dram Type= 6, Freq= 0, CH_0, rank 1

 7990 23:07:07.753651  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7991 23:07:07.753720  ==

 7992 23:07:07.757468  [Gating] SW mode calibration

 7993 23:07:07.763880  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0

 7994 23:07:07.770400  RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)

 7995 23:07:07.773374   1  4  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 7996 23:07:07.776865   1  4  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 7997 23:07:07.783591   1  4  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 7998 23:07:07.786966   1  4 12 | B1->B0 | 2323 3131 | 0 1 | (0 0) (0 0)

 7999 23:07:07.790425   1  4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)

 8000 23:07:07.794244   1  4 20 | B1->B0 | 2c2c 3434 | 1 1 | (1 1) (1 1)

 8001 23:07:07.800420   1  4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8002 23:07:07.803665   1  4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8003 23:07:07.807403   1  5  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8004 23:07:07.813941   1  5  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8005 23:07:07.817024   1  5  8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)

 8006 23:07:07.820503   1  5 12 | B1->B0 | 3434 2828 | 1 1 | (1 1) (1 0)

 8007 23:07:07.827406   1  5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)

 8008 23:07:07.830699   1  5 20 | B1->B0 | 2d2d 2323 | 0 0 | (1 0) (0 0)

 8009 23:07:07.834162   1  5 24 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)

 8010 23:07:07.840588   1  5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8011 23:07:07.843918   1  6  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8012 23:07:07.847142   1  6  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8013 23:07:07.853831   1  6  8 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)

 8014 23:07:07.856908   1  6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)

 8015 23:07:07.860408   1  6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)

 8016 23:07:07.864036   1  6 20 | B1->B0 | 3b3b 4646 | 0 0 | (1 1) (0 0)

 8017 23:07:07.870912   1  6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8018 23:07:07.874025   1  6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8019 23:07:07.877426   1  7  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8020 23:07:07.883818   1  7  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8021 23:07:07.887282   1  7  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 8022 23:07:07.890842   1  7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 8023 23:07:07.898059   1  7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 8024 23:07:07.900701   1  7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 8025 23:07:07.903784   1  7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8026 23:07:07.910574   1  7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8027 23:07:07.913708   1  8  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8028 23:07:07.917057   1  8  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8029 23:07:07.924128   1  8  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8030 23:07:07.927811   1  8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8031 23:07:07.930369   1  8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8032 23:07:07.937535   1  8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8033 23:07:07.940463   1  8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8034 23:07:07.944381   1  8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8035 23:07:07.950515   1  9  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8036 23:07:07.953786   1  9  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8037 23:07:07.957742   1  9  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 8038 23:07:07.960535   1  9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)

 8039 23:07:07.963744  Total UI for P1: 0, mck2ui 16

 8040 23:07:07.966997  best dqsien dly found for B0: ( 1,  9,  8)

 8041 23:07:07.974230   1  9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)

 8042 23:07:07.977752   1  9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 8043 23:07:07.981458   1  9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 8044 23:07:07.987798   1  9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8045 23:07:07.987904  Total UI for P1: 0, mck2ui 16

 8046 23:07:07.993995  best dqsien dly found for B1: ( 1,  9, 22)

 8047 23:07:07.997407  best DQS0 dly(MCK, UI, PI) = (1, 9, 8)

 8048 23:07:08.001172  best DQS1 dly(MCK, UI, PI) = (1, 9, 22)

 8049 23:07:08.001268  

 8050 23:07:08.004111  best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)

 8051 23:07:08.007891  best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)

 8052 23:07:08.012013  [Gating] SW calibration Done

 8053 23:07:08.012098  ==

 8054 23:07:08.014341  Dram Type= 6, Freq= 0, CH_0, rank 1

 8055 23:07:08.017429  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8056 23:07:08.017526  ==

 8057 23:07:08.021314  RX Vref Scan: 0

 8058 23:07:08.021391  

 8059 23:07:08.021451  RX Vref 0 -> 0, step: 1

 8060 23:07:08.021508  

 8061 23:07:08.023837  RX Delay 0 -> 252, step: 8

 8062 23:07:08.027214  iDelay=200, Bit 0, Center 131 (72 ~ 191) 120

 8063 23:07:08.034330  iDelay=200, Bit 1, Center 135 (80 ~ 191) 112

 8064 23:07:08.037583  iDelay=200, Bit 2, Center 127 (72 ~ 183) 112

 8065 23:07:08.040974  iDelay=200, Bit 3, Center 131 (72 ~ 191) 120

 8066 23:07:08.044399  iDelay=200, Bit 4, Center 131 (72 ~ 191) 120

 8067 23:07:08.047341  iDelay=200, Bit 5, Center 115 (56 ~ 175) 120

 8068 23:07:08.050654  iDelay=200, Bit 6, Center 139 (80 ~ 199) 120

 8069 23:07:08.057488  iDelay=200, Bit 7, Center 139 (80 ~ 199) 120

 8070 23:07:08.061193  iDelay=200, Bit 8, Center 119 (64 ~ 175) 112

 8071 23:07:08.064407  iDelay=200, Bit 9, Center 111 (56 ~ 167) 112

 8072 23:07:08.067567  iDelay=200, Bit 10, Center 123 (64 ~ 183) 120

 8073 23:07:08.070944  iDelay=200, Bit 11, Center 119 (64 ~ 175) 112

 8074 23:07:08.077858  iDelay=200, Bit 12, Center 127 (72 ~ 183) 112

 8075 23:07:08.081225  iDelay=200, Bit 13, Center 131 (72 ~ 191) 120

 8076 23:07:08.084304  iDelay=200, Bit 14, Center 139 (80 ~ 199) 120

 8077 23:07:08.087771  iDelay=200, Bit 15, Center 131 (72 ~ 191) 120

 8078 23:07:08.087878  ==

 8079 23:07:08.091227  Dram Type= 6, Freq= 0, CH_0, rank 1

 8080 23:07:08.097721  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8081 23:07:08.097842  ==

 8082 23:07:08.097989  DQS Delay:

 8083 23:07:08.098085  DQS0 = 0, DQS1 = 0

 8084 23:07:08.101172  DQM Delay:

 8085 23:07:08.101274  DQM0 = 131, DQM1 = 125

 8086 23:07:08.104904  DQ Delay:

 8087 23:07:08.108044  DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =131

 8088 23:07:08.110887  DQ4 =131, DQ5 =115, DQ6 =139, DQ7 =139

 8089 23:07:08.114581  DQ8 =119, DQ9 =111, DQ10 =123, DQ11 =119

 8090 23:07:08.117734  DQ12 =127, DQ13 =131, DQ14 =139, DQ15 =131

 8091 23:07:08.117836  

 8092 23:07:08.117936  

 8093 23:07:08.118031  ==

 8094 23:07:08.121157  Dram Type= 6, Freq= 0, CH_0, rank 1

 8095 23:07:08.124767  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8096 23:07:08.124845  ==

 8097 23:07:08.128019  

 8098 23:07:08.128091  

 8099 23:07:08.128153  	TX Vref Scan disable

 8100 23:07:08.131277   == TX Byte 0 ==

 8101 23:07:08.134474  Update DQ  dly =991 (3 ,6, 31)  DQ  OEN =(3 ,3)

 8102 23:07:08.137945  Update DQM dly =991 (3 ,6, 31)  DQM OEN =(3 ,3)

 8103 23:07:08.141362   == TX Byte 1 ==

 8104 23:07:08.144427  Update DQ  dly =984 (3 ,6, 24)  DQ  OEN =(3 ,3)

 8105 23:07:08.148006  Update DQM dly =984 (3 ,6, 24)  DQM OEN =(3 ,3)

 8106 23:07:08.148117  ==

 8107 23:07:08.151421  Dram Type= 6, Freq= 0, CH_0, rank 1

 8108 23:07:08.157641  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8109 23:07:08.157728  ==

 8110 23:07:08.171474  

 8111 23:07:08.174636  TX Vref early break, caculate TX vref

 8112 23:07:08.178030  TX Vref=16, minBit 0, minWin=22, winSum=370

 8113 23:07:08.181337  TX Vref=18, minBit 0, minWin=23, winSum=385

 8114 23:07:08.184521  TX Vref=20, minBit 2, minWin=23, winSum=394

 8115 23:07:08.188121  TX Vref=22, minBit 0, minWin=24, winSum=401

 8116 23:07:08.191093  TX Vref=24, minBit 4, minWin=24, winSum=408

 8117 23:07:08.198143  TX Vref=26, minBit 1, minWin=25, winSum=421

 8118 23:07:08.201421  TX Vref=28, minBit 2, minWin=25, winSum=423

 8119 23:07:08.204391  TX Vref=30, minBit 4, minWin=25, winSum=422

 8120 23:07:08.208278  TX Vref=32, minBit 0, minWin=25, winSum=413

 8121 23:07:08.211465  TX Vref=34, minBit 0, minWin=24, winSum=409

 8122 23:07:08.214527  TX Vref=36, minBit 0, minWin=23, winSum=395

 8123 23:07:08.221043  [TxChooseVref] Worse bit 2, Min win 25, Win sum 423, Final Vref 28

 8124 23:07:08.221131  

 8125 23:07:08.224907  Final TX Range 0 Vref 28

 8126 23:07:08.224993  

 8127 23:07:08.225078  ==

 8128 23:07:08.227820  Dram Type= 6, Freq= 0, CH_0, rank 1

 8129 23:07:08.231547  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8130 23:07:08.231632  ==

 8131 23:07:08.231717  

 8132 23:07:08.231797  

 8133 23:07:08.234862  	TX Vref Scan disable

 8134 23:07:08.241310  [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps

 8135 23:07:08.241395   == TX Byte 0 ==

 8136 23:07:08.245291  u2DelayCellOfst[0]=14 cells (4 PI)

 8137 23:07:08.247710  u2DelayCellOfst[1]=17 cells (5 PI)

 8138 23:07:08.251196  u2DelayCellOfst[2]=10 cells (3 PI)

 8139 23:07:08.255171  u2DelayCellOfst[3]=10 cells (3 PI)

 8140 23:07:08.258193  u2DelayCellOfst[4]=10 cells (3 PI)

 8141 23:07:08.261476  u2DelayCellOfst[5]=0 cells (0 PI)

 8142 23:07:08.264893  u2DelayCellOfst[6]=17 cells (5 PI)

 8143 23:07:08.267842  u2DelayCellOfst[7]=17 cells (5 PI)

 8144 23:07:08.271505  Update DQ  dly =988 (3 ,6, 28)  DQ  OEN =(3 ,3)

 8145 23:07:08.274762  Update DQM dly =990 (3 ,6, 30)  DQM OEN =(3 ,3)

 8146 23:07:08.278164   == TX Byte 1 ==

 8147 23:07:08.278233  u2DelayCellOfst[8]=0 cells (0 PI)

 8148 23:07:08.281745  u2DelayCellOfst[9]=0 cells (0 PI)

 8149 23:07:08.284375  u2DelayCellOfst[10]=7 cells (2 PI)

 8150 23:07:08.287991  u2DelayCellOfst[11]=0 cells (0 PI)

 8151 23:07:08.291299  u2DelayCellOfst[12]=14 cells (4 PI)

 8152 23:07:08.294900  u2DelayCellOfst[13]=10 cells (3 PI)

 8153 23:07:08.297841  u2DelayCellOfst[14]=14 cells (4 PI)

 8154 23:07:08.301549  u2DelayCellOfst[15]=10 cells (3 PI)

 8155 23:07:08.304467  Update DQ  dly =982 (3 ,6, 22)  DQ  OEN =(3 ,3)

 8156 23:07:08.311637  Update DQM dly =984 (3 ,6, 24)  DQM OEN =(3 ,3)

 8157 23:07:08.311735  DramC Write-DBI on

 8158 23:07:08.311823  ==

 8159 23:07:08.314842  Dram Type= 6, Freq= 0, CH_0, rank 1

 8160 23:07:08.318755  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8161 23:07:08.318851  ==

 8162 23:07:08.318940  

 8163 23:07:08.321636  

 8164 23:07:08.321729  	TX Vref Scan disable

 8165 23:07:08.324889   == TX Byte 0 ==

 8166 23:07:08.328703  Update DQM dly =734 (2 ,6, 30)  DQM OEN =(3 ,3)

 8167 23:07:08.331251   == TX Byte 1 ==

 8168 23:07:08.334945  Update DQM dly =726 (2 ,6, 22)  DQM OEN =(3 ,3)

 8169 23:07:08.335037  DramC Write-DBI off

 8170 23:07:08.335123  

 8171 23:07:08.337955  [DATLAT]

 8172 23:07:08.338044  Freq=1600, CH0 RK1

 8173 23:07:08.338128  

 8174 23:07:08.341986  DATLAT Default: 0xf

 8175 23:07:08.342052  0, 0xFFFF, sum = 0

 8176 23:07:08.344795  1, 0xFFFF, sum = 0

 8177 23:07:08.344889  2, 0xFFFF, sum = 0

 8178 23:07:08.348724  3, 0xFFFF, sum = 0

 8179 23:07:08.348816  4, 0xFFFF, sum = 0

 8180 23:07:08.351731  5, 0xFFFF, sum = 0

 8181 23:07:08.351823  6, 0xFFFF, sum = 0

 8182 23:07:08.354798  7, 0xFFFF, sum = 0

 8183 23:07:08.358019  8, 0xFFFF, sum = 0

 8184 23:07:08.358113  9, 0xFFFF, sum = 0

 8185 23:07:08.361622  10, 0xFFFF, sum = 0

 8186 23:07:08.361715  11, 0xFFFF, sum = 0

 8187 23:07:08.364647  12, 0xFFFF, sum = 0

 8188 23:07:08.364740  13, 0xFFFF, sum = 0

 8189 23:07:08.368116  14, 0x0, sum = 1

 8190 23:07:08.368208  15, 0x0, sum = 2

 8191 23:07:08.371663  16, 0x0, sum = 3

 8192 23:07:08.371756  17, 0x0, sum = 4

 8193 23:07:08.371845  best_step = 15

 8194 23:07:08.375025  

 8195 23:07:08.375091  ==

 8196 23:07:08.377869  Dram Type= 6, Freq= 0, CH_0, rank 1

 8197 23:07:08.381547  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8198 23:07:08.381640  ==

 8199 23:07:08.381726  RX Vref Scan: 0

 8200 23:07:08.381809  

 8201 23:07:08.384892  RX Vref 0 -> 0, step: 1

 8202 23:07:08.384981  

 8203 23:07:08.388044  RX Delay 11 -> 252, step: 4

 8204 23:07:08.392038  iDelay=191, Bit 0, Center 126 (71 ~ 182) 112

 8205 23:07:08.395235  iDelay=191, Bit 1, Center 128 (75 ~ 182) 108

 8206 23:07:08.401358  iDelay=191, Bit 2, Center 122 (67 ~ 178) 112

 8207 23:07:08.404938  iDelay=191, Bit 3, Center 126 (71 ~ 182) 112

 8208 23:07:08.408503  iDelay=191, Bit 4, Center 126 (75 ~ 178) 104

 8209 23:07:08.411724  iDelay=191, Bit 5, Center 116 (59 ~ 174) 116

 8210 23:07:08.415040  iDelay=191, Bit 6, Center 134 (79 ~ 190) 112

 8211 23:07:08.422062  iDelay=191, Bit 7, Center 136 (83 ~ 190) 108

 8212 23:07:08.424722  iDelay=191, Bit 8, Center 112 (59 ~ 166) 108

 8213 23:07:08.428194  iDelay=191, Bit 9, Center 110 (55 ~ 166) 112

 8214 23:07:08.431356  iDelay=191, Bit 10, Center 122 (67 ~ 178) 112

 8215 23:07:08.435334  iDelay=191, Bit 11, Center 116 (63 ~ 170) 108

 8216 23:07:08.441440  iDelay=191, Bit 12, Center 126 (75 ~ 178) 104

 8217 23:07:08.444634  iDelay=191, Bit 13, Center 128 (75 ~ 182) 108

 8218 23:07:08.448116  iDelay=191, Bit 14, Center 134 (79 ~ 190) 112

 8219 23:07:08.451913  iDelay=191, Bit 15, Center 130 (75 ~ 186) 112

 8220 23:07:08.451995  ==

 8221 23:07:08.454762  Dram Type= 6, Freq= 0, CH_0, rank 1

 8222 23:07:08.461623  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8223 23:07:08.461728  ==

 8224 23:07:08.461806  DQS Delay:

 8225 23:07:08.464770  DQS0 = 0, DQS1 = 0

 8226 23:07:08.464853  DQM Delay:

 8227 23:07:08.464917  DQM0 = 126, DQM1 = 122

 8228 23:07:08.467822  DQ Delay:

 8229 23:07:08.471612  DQ0 =126, DQ1 =128, DQ2 =122, DQ3 =126

 8230 23:07:08.474874  DQ4 =126, DQ5 =116, DQ6 =134, DQ7 =136

 8231 23:07:08.478244  DQ8 =112, DQ9 =110, DQ10 =122, DQ11 =116

 8232 23:07:08.481715  DQ12 =126, DQ13 =128, DQ14 =134, DQ15 =130

 8233 23:07:08.481801  

 8234 23:07:08.481886  

 8235 23:07:08.481985  

 8236 23:07:08.484535  [DramC_TX_OE_Calibration] TA2

 8237 23:07:08.488228  Original DQ_B0 (3 6) =30, OEN = 27

 8238 23:07:08.491307  Original DQ_B1 (3 6) =30, OEN = 27

 8239 23:07:08.494907  24, 0x0, End_B0=24 End_B1=24

 8240 23:07:08.495006  25, 0x0, End_B0=25 End_B1=25

 8241 23:07:08.498325  26, 0x0, End_B0=26 End_B1=26

 8242 23:07:08.501613  27, 0x0, End_B0=27 End_B1=27

 8243 23:07:08.504687  28, 0x0, End_B0=28 End_B1=28

 8244 23:07:08.508482  29, 0x0, End_B0=29 End_B1=29

 8245 23:07:08.508567  30, 0x0, End_B0=30 End_B1=30

 8246 23:07:08.511391  31, 0x4141, End_B0=30 End_B1=30

 8247 23:07:08.514910  Byte0 end_step=30  best_step=27

 8248 23:07:08.517874  Byte1 end_step=30  best_step=27

 8249 23:07:08.521559  Byte0 TX OE(2T, 0.5T) = (3, 3)

 8250 23:07:08.524894  Byte1 TX OE(2T, 0.5T) = (3, 3)

 8251 23:07:08.524991  

 8252 23:07:08.525057  

 8253 23:07:08.531605  [DQSOSCAuto] RK1, (LSB)MR18= 0x1b0f, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 396 ps

 8254 23:07:08.534527  CH0 RK1: MR19=303, MR18=1B0F

 8255 23:07:08.541394  CH0_RK1: MR19=0x303, MR18=0x1B0F, DQSOSC=396, MR23=63, INC=23, DEC=15

 8256 23:07:08.544554  [RxdqsGatingPostProcess] freq 1600

 8257 23:07:08.548606  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3

 8258 23:07:08.552012  best DQS0 dly(2T, 0.5T) = (1, 1)

 8259 23:07:08.555412  best DQS1 dly(2T, 0.5T) = (1, 1)

 8260 23:07:08.558014  best DQS0 P1 dly(2T, 0.5T) = (1, 5)

 8261 23:07:08.561513  best DQS1 P1 dly(2T, 0.5T) = (1, 5)

 8262 23:07:08.564852  best DQS0 dly(2T, 0.5T) = (1, 1)

 8263 23:07:08.568629  best DQS1 dly(2T, 0.5T) = (1, 1)

 8264 23:07:08.571825  best DQS0 P1 dly(2T, 0.5T) = (1, 5)

 8265 23:07:08.574675  best DQS1 P1 dly(2T, 0.5T) = (1, 5)

 8266 23:07:08.574757  Pre-setting of DQS Precalculation

 8267 23:07:08.581712  [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15

 8268 23:07:08.581794  ==

 8269 23:07:08.584716  Dram Type= 6, Freq= 0, CH_1, rank 0

 8270 23:07:08.587867  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8271 23:07:08.587950  ==

 8272 23:07:08.594685  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 8273 23:07:08.597802  [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1

 8274 23:07:08.601436  [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1

 8275 23:07:08.608454  u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32

 8276 23:07:08.617822  [CA 0] Center 42 (14~71) winsize 58

 8277 23:07:08.620913  [CA 1] Center 42 (13~71) winsize 59

 8278 23:07:08.624528  [CA 2] Center 37 (9~66) winsize 58

 8279 23:07:08.627710  [CA 3] Center 36 (7~65) winsize 59

 8280 23:07:08.631162  [CA 4] Center 37 (8~67) winsize 60

 8281 23:07:08.634586  [CA 5] Center 36 (7~66) winsize 60

 8282 23:07:08.634670  

 8283 23:07:08.637887  [CmdBusTrainingLP45] Vref(ca) range 0: 32

 8284 23:07:08.637972  

 8285 23:07:08.641820  [CATrainingPosCal] consider 1 rank data

 8286 23:07:08.645350  u2DelayCellTimex100 = 275/100 ps

 8287 23:07:08.648277  CA0 delay=42 (14~71),Diff = 6 PI (21 cell)

 8288 23:07:08.651699  CA1 delay=42 (13~71),Diff = 6 PI (21 cell)

 8289 23:07:08.658081  CA2 delay=37 (9~66),Diff = 1 PI (3 cell)

 8290 23:07:08.661150  CA3 delay=36 (7~65),Diff = 0 PI (0 cell)

 8291 23:07:08.664546  CA4 delay=37 (8~67),Diff = 1 PI (3 cell)

 8292 23:07:08.667630  CA5 delay=36 (7~66),Diff = 0 PI (0 cell)

 8293 23:07:08.667738  

 8294 23:07:08.672169  CA PerBit enable=1, Macro0, CA PI delay=36

 8295 23:07:08.672250  

 8296 23:07:08.674862  [CBTSetCACLKResult] CA Dly = 36

 8297 23:07:08.674943  CS Dly: 9 (0~40)

 8298 23:07:08.681681  [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0

 8299 23:07:08.684670  [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0

 8300 23:07:08.684751  ==

 8301 23:07:08.687913  Dram Type= 6, Freq= 0, CH_1, rank 1

 8302 23:07:08.691301  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8303 23:07:08.691383  ==

 8304 23:07:08.698117  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 8305 23:07:08.701158  [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1

 8306 23:07:08.704615  [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1

 8307 23:07:08.711549  u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32

 8308 23:07:08.720852  [CA 0] Center 42 (13~72) winsize 60

 8309 23:07:08.724088  [CA 1] Center 43 (14~72) winsize 59

 8310 23:07:08.727680  [CA 2] Center 37 (8~67) winsize 60

 8311 23:07:08.731017  [CA 3] Center 37 (8~66) winsize 59

 8312 23:07:08.734289  [CA 4] Center 38 (9~67) winsize 59

 8313 23:07:08.737849  [CA 5] Center 36 (6~66) winsize 61

 8314 23:07:08.737931  

 8315 23:07:08.740802  [CmdBusTrainingLP45] Vref(ca) range 0: 32

 8316 23:07:08.740883  

 8317 23:07:08.744227  [CATrainingPosCal] consider 2 rank data

 8318 23:07:08.747676  u2DelayCellTimex100 = 275/100 ps

 8319 23:07:08.751142  CA0 delay=42 (14~71),Diff = 6 PI (21 cell)

 8320 23:07:08.757777  CA1 delay=42 (14~71),Diff = 6 PI (21 cell)

 8321 23:07:08.761041  CA2 delay=37 (9~66),Diff = 1 PI (3 cell)

 8322 23:07:08.764031  CA3 delay=36 (8~65),Diff = 0 PI (0 cell)

 8323 23:07:08.767570  CA4 delay=38 (9~67),Diff = 2 PI (7 cell)

 8324 23:07:08.771380  CA5 delay=36 (7~66),Diff = 0 PI (0 cell)

 8325 23:07:08.771461  

 8326 23:07:08.774503  CA PerBit enable=1, Macro0, CA PI delay=36

 8327 23:07:08.774584  

 8328 23:07:08.777455  [CBTSetCACLKResult] CA Dly = 36

 8329 23:07:08.777535  CS Dly: 11 (0~44)

 8330 23:07:08.784161  [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0

 8331 23:07:08.787970  [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0

 8332 23:07:08.788052  

 8333 23:07:08.791310  ----->DramcWriteLeveling(PI) begin...

 8334 23:07:08.791392  ==

 8335 23:07:08.794242  Dram Type= 6, Freq= 0, CH_1, rank 0

 8336 23:07:08.797959  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8337 23:07:08.798041  ==

 8338 23:07:08.801515  Write leveling (Byte 0): 25 => 25

 8339 23:07:08.804412  Write leveling (Byte 1): 28 => 28

 8340 23:07:08.807676  DramcWriteLeveling(PI) end<-----

 8341 23:07:08.807757  

 8342 23:07:08.807819  ==

 8343 23:07:08.810971  Dram Type= 6, Freq= 0, CH_1, rank 0

 8344 23:07:08.814289  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8345 23:07:08.818288  ==

 8346 23:07:08.818383  [Gating] SW mode calibration

 8347 23:07:08.824430  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0

 8348 23:07:08.831579  RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)

 8349 23:07:08.834546   1  4  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8350 23:07:08.841432   1  4  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8351 23:07:08.844369   1  4  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8352 23:07:08.847969   1  4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8353 23:07:08.854537   1  4 16 | B1->B0 | 2c2c 2727 | 0 0 | (0 0) (0 0)

 8354 23:07:08.857877   1  4 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)

 8355 23:07:08.861108   1  4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8356 23:07:08.869369   1  4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8357 23:07:08.871672   1  5  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8358 23:07:08.874537   1  5  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8359 23:07:08.877760   1  5  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8360 23:07:08.884166   1  5 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)

 8361 23:07:08.887808   1  5 16 | B1->B0 | 3131 3434 | 0 0 | (1 0) (0 1)

 8362 23:07:08.891025   1  5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8363 23:07:08.898050   1  5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8364 23:07:08.900953   1  5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8365 23:07:08.905049   1  6  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8366 23:07:08.911606   1  6  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8367 23:07:08.914464   1  6  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8368 23:07:08.917955   1  6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8369 23:07:08.924459   1  6 16 | B1->B0 | 4343 3232 | 0 0 | (0 0) (0 0)

 8370 23:07:08.928014   1  6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8371 23:07:08.931436   1  6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8372 23:07:08.937812   1  6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8373 23:07:08.941346   1  7  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8374 23:07:08.944698   1  7  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8375 23:07:08.951302   1  7  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8376 23:07:08.954381   1  7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 8377 23:07:08.957602   1  7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 8378 23:07:08.964752   1  7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8379 23:07:08.968174   1  7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8380 23:07:08.971836   1  7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8381 23:07:08.975027   1  8  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8382 23:07:08.981495   1  8  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8383 23:07:08.984877   1  8  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8384 23:07:08.988247   1  8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8385 23:07:08.995083   1  8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8386 23:07:08.997863   1  8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8387 23:07:09.001235   1  8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8388 23:07:09.007869   1  8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8389 23:07:09.011123   1  9  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8390 23:07:09.014364   1  9  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8391 23:07:09.021096   1  9  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8392 23:07:09.024517   1  9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 8393 23:07:09.028559   1  9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 8394 23:07:09.034660   1  9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8395 23:07:09.034765  Total UI for P1: 0, mck2ui 16

 8396 23:07:09.041091  best dqsien dly found for B0: ( 1,  9, 14)

 8397 23:07:09.041176  Total UI for P1: 0, mck2ui 16

 8398 23:07:09.044574  best dqsien dly found for B1: ( 1,  9, 14)

 8399 23:07:09.051843  best DQS0 dly(MCK, UI, PI) = (1, 9, 14)

 8400 23:07:09.054616  best DQS1 dly(MCK, UI, PI) = (1, 9, 14)

 8401 23:07:09.054698  

 8402 23:07:09.058410  best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)

 8403 23:07:09.061170  best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)

 8404 23:07:09.064676  [Gating] SW calibration Done

 8405 23:07:09.064758  ==

 8406 23:07:09.067772  Dram Type= 6, Freq= 0, CH_1, rank 0

 8407 23:07:09.071062  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8408 23:07:09.071146  ==

 8409 23:07:09.074587  RX Vref Scan: 0

 8410 23:07:09.074690  

 8411 23:07:09.074787  RX Vref 0 -> 0, step: 1

 8412 23:07:09.074876  

 8413 23:07:09.077884  RX Delay 0 -> 252, step: 8

 8414 23:07:09.081277  iDelay=200, Bit 0, Center 139 (88 ~ 191) 104

 8415 23:07:09.084410  iDelay=200, Bit 1, Center 127 (72 ~ 183) 112

 8416 23:07:09.092181  iDelay=200, Bit 2, Center 123 (72 ~ 175) 104

 8417 23:07:09.094830  iDelay=200, Bit 3, Center 135 (80 ~ 191) 112

 8418 23:07:09.098416  iDelay=200, Bit 4, Center 135 (80 ~ 191) 112

 8419 23:07:09.101326  iDelay=200, Bit 5, Center 143 (88 ~ 199) 112

 8420 23:07:09.104921  iDelay=200, Bit 6, Center 143 (96 ~ 191) 96

 8421 23:07:09.111720  iDelay=200, Bit 7, Center 131 (80 ~ 183) 104

 8422 23:07:09.114719  iDelay=200, Bit 8, Center 115 (64 ~ 167) 104

 8423 23:07:09.118264  iDelay=200, Bit 9, Center 115 (64 ~ 167) 104

 8424 23:07:09.121313  iDelay=200, Bit 10, Center 127 (72 ~ 183) 112

 8425 23:07:09.124396  iDelay=200, Bit 11, Center 123 (72 ~ 175) 104

 8426 23:07:09.131522  iDelay=200, Bit 12, Center 135 (80 ~ 191) 112

 8427 23:07:09.135044  iDelay=200, Bit 13, Center 135 (80 ~ 191) 112

 8428 23:07:09.137643  iDelay=200, Bit 14, Center 135 (80 ~ 191) 112

 8429 23:07:09.141576  iDelay=200, Bit 15, Center 131 (80 ~ 183) 104

 8430 23:07:09.141655  ==

 8431 23:07:09.145323  Dram Type= 6, Freq= 0, CH_1, rank 0

 8432 23:07:09.151573  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8433 23:07:09.151665  ==

 8434 23:07:09.151732  DQS Delay:

 8435 23:07:09.154563  DQS0 = 0, DQS1 = 0

 8436 23:07:09.154636  DQM Delay:

 8437 23:07:09.154697  DQM0 = 134, DQM1 = 127

 8438 23:07:09.157935  DQ Delay:

 8439 23:07:09.161213  DQ0 =139, DQ1 =127, DQ2 =123, DQ3 =135

 8440 23:07:09.164998  DQ4 =135, DQ5 =143, DQ6 =143, DQ7 =131

 8441 23:07:09.167995  DQ8 =115, DQ9 =115, DQ10 =127, DQ11 =123

 8442 23:07:09.171082  DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =131

 8443 23:07:09.171161  

 8444 23:07:09.171223  

 8445 23:07:09.171281  ==

 8446 23:07:09.174743  Dram Type= 6, Freq= 0, CH_1, rank 0

 8447 23:07:09.177997  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8448 23:07:09.181279  ==

 8449 23:07:09.181350  

 8450 23:07:09.181411  

 8451 23:07:09.181468  	TX Vref Scan disable

 8452 23:07:09.184542   == TX Byte 0 ==

 8453 23:07:09.187952  Update DQ  dly =983 (3 ,6, 23)  DQ  OEN =(3 ,3)

 8454 23:07:09.191326  Update DQM dly =983 (3 ,6, 23)  DQM OEN =(3 ,3)

 8455 23:07:09.194150   == TX Byte 1 ==

 8456 23:07:09.198085  Update DQ  dly =983 (3 ,6, 23)  DQ  OEN =(3 ,3)

 8457 23:07:09.201492  Update DQM dly =983 (3 ,6, 23)  DQM OEN =(3 ,3)

 8458 23:07:09.201566  ==

 8459 23:07:09.204461  Dram Type= 6, Freq= 0, CH_1, rank 0

 8460 23:07:09.211761  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8461 23:07:09.211844  ==

 8462 23:07:09.224426  

 8463 23:07:09.227413  TX Vref early break, caculate TX vref

 8464 23:07:09.230503  TX Vref=16, minBit 8, minWin=21, winSum=364

 8465 23:07:09.234018  TX Vref=18, minBit 8, minWin=21, winSum=370

 8466 23:07:09.237135  TX Vref=20, minBit 5, minWin=22, winSum=382

 8467 23:07:09.240579  TX Vref=22, minBit 8, minWin=23, winSum=390

 8468 23:07:09.243822  TX Vref=24, minBit 5, minWin=24, winSum=404

 8469 23:07:09.250522  TX Vref=26, minBit 11, minWin=24, winSum=411

 8470 23:07:09.254311  TX Vref=28, minBit 5, minWin=25, winSum=420

 8471 23:07:09.257182  TX Vref=30, minBit 8, minWin=25, winSum=416

 8472 23:07:09.260579  TX Vref=32, minBit 9, minWin=24, winSum=409

 8473 23:07:09.263932  TX Vref=34, minBit 8, minWin=23, winSum=400

 8474 23:07:09.267148  TX Vref=36, minBit 8, minWin=23, winSum=389

 8475 23:07:09.274091  [TxChooseVref] Worse bit 5, Min win 25, Win sum 420, Final Vref 28

 8476 23:07:09.274188  

 8477 23:07:09.277179  Final TX Range 0 Vref 28

 8478 23:07:09.277263  

 8479 23:07:09.277367  ==

 8480 23:07:09.280791  Dram Type= 6, Freq= 0, CH_1, rank 0

 8481 23:07:09.283799  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8482 23:07:09.283878  ==

 8483 23:07:09.283942  

 8484 23:07:09.284001  

 8485 23:07:09.287160  	TX Vref Scan disable

 8486 23:07:09.294199  [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps

 8487 23:07:09.294302   == TX Byte 0 ==

 8488 23:07:09.297106  u2DelayCellOfst[0]=17 cells (5 PI)

 8489 23:07:09.300300  u2DelayCellOfst[1]=10 cells (3 PI)

 8490 23:07:09.303953  u2DelayCellOfst[2]=0 cells (0 PI)

 8491 23:07:09.307187  u2DelayCellOfst[3]=7 cells (2 PI)

 8492 23:07:09.310710  u2DelayCellOfst[4]=10 cells (3 PI)

 8493 23:07:09.313669  u2DelayCellOfst[5]=21 cells (6 PI)

 8494 23:07:09.317338  u2DelayCellOfst[6]=17 cells (5 PI)

 8495 23:07:09.321839  u2DelayCellOfst[7]=7 cells (2 PI)

 8496 23:07:09.323656  Update DQ  dly =980 (3 ,6, 20)  DQ  OEN =(3 ,3)

 8497 23:07:09.327014  Update DQM dly =983 (3 ,6, 23)  DQM OEN =(3 ,3)

 8498 23:07:09.330705   == TX Byte 1 ==

 8499 23:07:09.330781  u2DelayCellOfst[8]=0 cells (0 PI)

 8500 23:07:09.333942  u2DelayCellOfst[9]=7 cells (2 PI)

 8501 23:07:09.337393  u2DelayCellOfst[10]=10 cells (3 PI)

 8502 23:07:09.340846  u2DelayCellOfst[11]=7 cells (2 PI)

 8503 23:07:09.344442  u2DelayCellOfst[12]=14 cells (4 PI)

 8504 23:07:09.348040  u2DelayCellOfst[13]=17 cells (5 PI)

 8505 23:07:09.350868  u2DelayCellOfst[14]=17 cells (5 PI)

 8506 23:07:09.354266  u2DelayCellOfst[15]=17 cells (5 PI)

 8507 23:07:09.357235  Update DQ  dly =981 (3 ,6, 21)  DQ  OEN =(3 ,3)

 8508 23:07:09.364298  Update DQM dly =983 (3 ,6, 23)  DQM OEN =(3 ,3)

 8509 23:07:09.364384  DramC Write-DBI on

 8510 23:07:09.364453  ==

 8511 23:07:09.367394  Dram Type= 6, Freq= 0, CH_1, rank 0

 8512 23:07:09.370692  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8513 23:07:09.370787  ==

 8514 23:07:09.374798  

 8515 23:07:09.374889  

 8516 23:07:09.374992  	TX Vref Scan disable

 8517 23:07:09.377631   == TX Byte 0 ==

 8518 23:07:09.380498  Update DQM dly =723 (2 ,6, 19)  DQM OEN =(3 ,3)

 8519 23:07:09.384322   == TX Byte 1 ==

 8520 23:07:09.387395  Update DQM dly =724 (2 ,6, 20)  DQM OEN =(3 ,3)

 8521 23:07:09.387501  DramC Write-DBI off

 8522 23:07:09.390450  

 8523 23:07:09.390554  [DATLAT]

 8524 23:07:09.390633  Freq=1600, CH1 RK0

 8525 23:07:09.390695  

 8526 23:07:09.393996  DATLAT Default: 0xf

 8527 23:07:09.394095  0, 0xFFFF, sum = 0

 8528 23:07:09.397572  1, 0xFFFF, sum = 0

 8529 23:07:09.397650  2, 0xFFFF, sum = 0

 8530 23:07:09.400652  3, 0xFFFF, sum = 0

 8531 23:07:09.400727  4, 0xFFFF, sum = 0

 8532 23:07:09.404085  5, 0xFFFF, sum = 0

 8533 23:07:09.404186  6, 0xFFFF, sum = 0

 8534 23:07:09.407196  7, 0xFFFF, sum = 0

 8535 23:07:09.410682  8, 0xFFFF, sum = 0

 8536 23:07:09.410758  9, 0xFFFF, sum = 0

 8537 23:07:09.414113  10, 0xFFFF, sum = 0

 8538 23:07:09.414216  11, 0xFFFF, sum = 0

 8539 23:07:09.417468  12, 0xFFFF, sum = 0

 8540 23:07:09.417572  13, 0xFFFF, sum = 0

 8541 23:07:09.420747  14, 0x0, sum = 1

 8542 23:07:09.420855  15, 0x0, sum = 2

 8543 23:07:09.424528  16, 0x0, sum = 3

 8544 23:07:09.424638  17, 0x0, sum = 4

 8545 23:07:09.424730  best_step = 15

 8546 23:07:09.424822  

 8547 23:07:09.427774  ==

 8548 23:07:09.430841  Dram Type= 6, Freq= 0, CH_1, rank 0

 8549 23:07:09.434091  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8550 23:07:09.434191  ==

 8551 23:07:09.434280  RX Vref Scan: 1

 8552 23:07:09.434376  

 8553 23:07:09.437843  Set Vref Range= 24 -> 127

 8554 23:07:09.437940  

 8555 23:07:09.440689  RX Vref 24 -> 127, step: 1

 8556 23:07:09.440787  

 8557 23:07:09.444716  RX Delay 19 -> 252, step: 4

 8558 23:07:09.444789  

 8559 23:07:09.448028  Set Vref, RX VrefLevel [Byte0]: 24

 8560 23:07:09.451032                           [Byte1]: 24

 8561 23:07:09.451117  

 8562 23:07:09.454073  Set Vref, RX VrefLevel [Byte0]: 25

 8563 23:07:09.457800                           [Byte1]: 25

 8564 23:07:09.457902  

 8565 23:07:09.460741  Set Vref, RX VrefLevel [Byte0]: 26

 8566 23:07:09.464432                           [Byte1]: 26

 8567 23:07:09.467779  

 8568 23:07:09.467883  Set Vref, RX VrefLevel [Byte0]: 27

 8569 23:07:09.471189                           [Byte1]: 27

 8570 23:07:09.475272  

 8571 23:07:09.475363  Set Vref, RX VrefLevel [Byte0]: 28

 8572 23:07:09.479030                           [Byte1]: 28

 8573 23:07:09.482678  

 8574 23:07:09.482762  Set Vref, RX VrefLevel [Byte0]: 29

 8575 23:07:09.486645                           [Byte1]: 29

 8576 23:07:09.490311  

 8577 23:07:09.490421  Set Vref, RX VrefLevel [Byte0]: 30

 8578 23:07:09.493449                           [Byte1]: 30

 8579 23:07:09.498460  

 8580 23:07:09.498539  Set Vref, RX VrefLevel [Byte0]: 31

 8581 23:07:09.501412                           [Byte1]: 31

 8582 23:07:09.505490  

 8583 23:07:09.505575  Set Vref, RX VrefLevel [Byte0]: 32

 8584 23:07:09.508815                           [Byte1]: 32

 8585 23:07:09.512875  

 8586 23:07:09.512983  Set Vref, RX VrefLevel [Byte0]: 33

 8587 23:07:09.516454                           [Byte1]: 33

 8588 23:07:09.520696  

 8589 23:07:09.520799  Set Vref, RX VrefLevel [Byte0]: 34

 8590 23:07:09.523834                           [Byte1]: 34

 8591 23:07:09.528270  

 8592 23:07:09.528368  Set Vref, RX VrefLevel [Byte0]: 35

 8593 23:07:09.531203                           [Byte1]: 35

 8594 23:07:09.536001  

 8595 23:07:09.536078  Set Vref, RX VrefLevel [Byte0]: 36

 8596 23:07:09.539221                           [Byte1]: 36

 8597 23:07:09.543209  

 8598 23:07:09.543306  Set Vref, RX VrefLevel [Byte0]: 37

 8599 23:07:09.546606                           [Byte1]: 37

 8600 23:07:09.551197  

 8601 23:07:09.551303  Set Vref, RX VrefLevel [Byte0]: 38

 8602 23:07:09.554093                           [Byte1]: 38

 8603 23:07:09.558477  

 8604 23:07:09.558558  Set Vref, RX VrefLevel [Byte0]: 39

 8605 23:07:09.561626                           [Byte1]: 39

 8606 23:07:09.566208  

 8607 23:07:09.566290  Set Vref, RX VrefLevel [Byte0]: 40

 8608 23:07:09.569531                           [Byte1]: 40

 8609 23:07:09.573610  

 8610 23:07:09.573691  Set Vref, RX VrefLevel [Byte0]: 41

 8611 23:07:09.576855                           [Byte1]: 41

 8612 23:07:09.581315  

 8613 23:07:09.581396  Set Vref, RX VrefLevel [Byte0]: 42

 8614 23:07:09.585035                           [Byte1]: 42

 8615 23:07:09.588923  

 8616 23:07:09.589004  Set Vref, RX VrefLevel [Byte0]: 43

 8617 23:07:09.591846                           [Byte1]: 43

 8618 23:07:09.596134  

 8619 23:07:09.596215  Set Vref, RX VrefLevel [Byte0]: 44

 8620 23:07:09.599455                           [Byte1]: 44

 8621 23:07:09.603822  

 8622 23:07:09.603903  Set Vref, RX VrefLevel [Byte0]: 45

 8623 23:07:09.607063                           [Byte1]: 45

 8624 23:07:09.611421  

 8625 23:07:09.611502  Set Vref, RX VrefLevel [Byte0]: 46

 8626 23:07:09.614907                           [Byte1]: 46

 8627 23:07:09.618812  

 8628 23:07:09.618893  Set Vref, RX VrefLevel [Byte0]: 47

 8629 23:07:09.622355                           [Byte1]: 47

 8630 23:07:09.626737  

 8631 23:07:09.626818  Set Vref, RX VrefLevel [Byte0]: 48

 8632 23:07:09.630051                           [Byte1]: 48

 8633 23:07:09.634084  

 8634 23:07:09.634165  Set Vref, RX VrefLevel [Byte0]: 49

 8635 23:07:09.637803                           [Byte1]: 49

 8636 23:07:09.641801  

 8637 23:07:09.641882  Set Vref, RX VrefLevel [Byte0]: 50

 8638 23:07:09.644887                           [Byte1]: 50

 8639 23:07:09.649168  

 8640 23:07:09.649249  Set Vref, RX VrefLevel [Byte0]: 51

 8641 23:07:09.653017                           [Byte1]: 51

 8642 23:07:09.657196  

 8643 23:07:09.657277  Set Vref, RX VrefLevel [Byte0]: 52

 8644 23:07:09.660298                           [Byte1]: 52

 8645 23:07:09.664790  

 8646 23:07:09.664872  Set Vref, RX VrefLevel [Byte0]: 53

 8647 23:07:09.667965                           [Byte1]: 53

 8648 23:07:09.672009  

 8649 23:07:09.672090  Set Vref, RX VrefLevel [Byte0]: 54

 8650 23:07:09.675522                           [Byte1]: 54

 8651 23:07:09.679563  

 8652 23:07:09.679644  Set Vref, RX VrefLevel [Byte0]: 55

 8653 23:07:09.682755                           [Byte1]: 55

 8654 23:07:09.687542  

 8655 23:07:09.687623  Set Vref, RX VrefLevel [Byte0]: 56

 8656 23:07:09.690810                           [Byte1]: 56

 8657 23:07:09.694492  

 8658 23:07:09.694572  Set Vref, RX VrefLevel [Byte0]: 57

 8659 23:07:09.698353                           [Byte1]: 57

 8660 23:07:09.702256  

 8661 23:07:09.702363  Set Vref, RX VrefLevel [Byte0]: 58

 8662 23:07:09.706119                           [Byte1]: 58

 8663 23:07:09.709670  

 8664 23:07:09.709757  Set Vref, RX VrefLevel [Byte0]: 59

 8665 23:07:09.713327                           [Byte1]: 59

 8666 23:07:09.717737  

 8667 23:07:09.717817  Set Vref, RX VrefLevel [Byte0]: 60

 8668 23:07:09.720932                           [Byte1]: 60

 8669 23:07:09.725083  

 8670 23:07:09.725163  Set Vref, RX VrefLevel [Byte0]: 61

 8671 23:07:09.728052                           [Byte1]: 61

 8672 23:07:09.732890  

 8673 23:07:09.732971  Set Vref, RX VrefLevel [Byte0]: 62

 8674 23:07:09.735697                           [Byte1]: 62

 8675 23:07:09.740485  

 8676 23:07:09.740567  Set Vref, RX VrefLevel [Byte0]: 63

 8677 23:07:09.743491                           [Byte1]: 63

 8678 23:07:09.747561  

 8679 23:07:09.747642  Set Vref, RX VrefLevel [Byte0]: 64

 8680 23:07:09.751380                           [Byte1]: 64

 8681 23:07:09.755103  

 8682 23:07:09.755184  Set Vref, RX VrefLevel [Byte0]: 65

 8683 23:07:09.758567                           [Byte1]: 65

 8684 23:07:09.762812  

 8685 23:07:09.762918  Set Vref, RX VrefLevel [Byte0]: 66

 8686 23:07:09.766087                           [Byte1]: 66

 8687 23:07:09.770429  

 8688 23:07:09.770527  Set Vref, RX VrefLevel [Byte0]: 67

 8689 23:07:09.774001                           [Byte1]: 67

 8690 23:07:09.777890  

 8691 23:07:09.777971  Set Vref, RX VrefLevel [Byte0]: 68

 8692 23:07:09.781575                           [Byte1]: 68

 8693 23:07:09.785613  

 8694 23:07:09.785694  Set Vref, RX VrefLevel [Byte0]: 69

 8695 23:07:09.789274                           [Byte1]: 69

 8696 23:07:09.793360  

 8697 23:07:09.793468  Set Vref, RX VrefLevel [Byte0]: 70

 8698 23:07:09.796575                           [Byte1]: 70

 8699 23:07:09.800875  

 8700 23:07:09.800957  Set Vref, RX VrefLevel [Byte0]: 71

 8701 23:07:09.804076                           [Byte1]: 71

 8702 23:07:09.808508  

 8703 23:07:09.808590  Set Vref, RX VrefLevel [Byte0]: 72

 8704 23:07:09.811722                           [Byte1]: 72

 8705 23:07:09.816043  

 8706 23:07:09.816125  Set Vref, RX VrefLevel [Byte0]: 73

 8707 23:07:09.819173                           [Byte1]: 73

 8708 23:07:09.823235  

 8709 23:07:09.823318  Final RX Vref Byte 0 = 64 to rank0

 8710 23:07:09.826999  Final RX Vref Byte 1 = 56 to rank0

 8711 23:07:09.830045  Final RX Vref Byte 0 = 64 to rank1

 8712 23:07:09.833434  Final RX Vref Byte 1 = 56 to rank1==

 8713 23:07:09.837066  Dram Type= 6, Freq= 0, CH_1, rank 0

 8714 23:07:09.843439  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8715 23:07:09.843523  ==

 8716 23:07:09.843589  DQS Delay:

 8717 23:07:09.843649  DQS0 = 0, DQS1 = 0

 8718 23:07:09.847184  DQM Delay:

 8719 23:07:09.847280  DQM0 = 132, DQM1 = 124

 8720 23:07:09.849928  DQ Delay:

 8721 23:07:09.853787  DQ0 =138, DQ1 =126, DQ2 =120, DQ3 =132

 8722 23:07:09.857023  DQ4 =130, DQ5 =142, DQ6 =142, DQ7 =126

 8723 23:07:09.860185  DQ8 =112, DQ9 =112, DQ10 =128, DQ11 =118

 8724 23:07:09.863543  DQ12 =132, DQ13 =132, DQ14 =130, DQ15 =132

 8725 23:07:09.863619  

 8726 23:07:09.863692  

 8727 23:07:09.863753  

 8728 23:07:09.867145  [DramC_TX_OE_Calibration] TA2

 8729 23:07:09.870237  Original DQ_B0 (3 6) =30, OEN = 27

 8730 23:07:09.873633  Original DQ_B1 (3 6) =30, OEN = 27

 8731 23:07:09.876975  24, 0x0, End_B0=24 End_B1=24

 8732 23:07:09.877051  25, 0x0, End_B0=25 End_B1=25

 8733 23:07:09.880233  26, 0x0, End_B0=26 End_B1=26

 8734 23:07:09.883781  27, 0x0, End_B0=27 End_B1=27

 8735 23:07:09.886611  28, 0x0, End_B0=28 End_B1=28

 8736 23:07:09.886687  29, 0x0, End_B0=29 End_B1=29

 8737 23:07:09.890466  30, 0x0, End_B0=30 End_B1=30

 8738 23:07:09.893544  31, 0x4141, End_B0=30 End_B1=30

 8739 23:07:09.897101  Byte0 end_step=30  best_step=27

 8740 23:07:09.900214  Byte1 end_step=30  best_step=27

 8741 23:07:09.903787  Byte0 TX OE(2T, 0.5T) = (3, 3)

 8742 23:07:09.903870  Byte1 TX OE(2T, 0.5T) = (3, 3)

 8743 23:07:09.903935  

 8744 23:07:09.903994  

 8745 23:07:09.913282  [DQSOSCAuto] RK0, (LSB)MR18= 0x14ff, (MSB)MR19= 0x302, tDQSOscB0 = 410 ps tDQSOscB1 = 399 ps

 8746 23:07:09.916983  CH1 RK0: MR19=302, MR18=14FF

 8747 23:07:09.924001  CH1_RK0: MR19=0x302, MR18=0x14FF, DQSOSC=399, MR23=63, INC=23, DEC=15

 8748 23:07:09.924085  

 8749 23:07:09.927105  ----->DramcWriteLeveling(PI) begin...

 8750 23:07:09.927189  ==

 8751 23:07:09.930906  Dram Type= 6, Freq= 0, CH_1, rank 1

 8752 23:07:09.934086  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8753 23:07:09.934170  ==

 8754 23:07:09.937525  Write leveling (Byte 0): 26 => 26

 8755 23:07:09.940594  Write leveling (Byte 1): 27 => 27

 8756 23:07:09.943886  DramcWriteLeveling(PI) end<-----

 8757 23:07:09.943968  

 8758 23:07:09.944033  ==

 8759 23:07:09.947062  Dram Type= 6, Freq= 0, CH_1, rank 1

 8760 23:07:09.950573  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8761 23:07:09.950656  ==

 8762 23:07:09.953580  [Gating] SW mode calibration

 8763 23:07:09.960753  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0

 8764 23:07:09.967214  RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)

 8765 23:07:09.970298   1  4  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8766 23:07:09.973957   1  4  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8767 23:07:09.980430   1  4  8 | B1->B0 | 2323 2828 | 0 1 | (0 0) (1 1)

 8768 23:07:09.983528   1  4 12 | B1->B0 | 2525 3434 | 0 1 | (0 0) (1 1)

 8769 23:07:09.986726   1  4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8770 23:07:09.990566   1  4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8771 23:07:09.997460   1  4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8772 23:07:10.000210   1  4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8773 23:07:10.003594   1  5  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8774 23:07:10.010300   1  5  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8775 23:07:10.013611   1  5  8 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 0)

 8776 23:07:10.017061   1  5 12 | B1->B0 | 2727 2323 | 0 0 | (0 1) (0 0)

 8777 23:07:10.023947   1  5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8778 23:07:10.026905   1  5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8779 23:07:10.030704   1  5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8780 23:07:10.037079   1  5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8781 23:07:10.040966   1  6  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8782 23:07:10.043509   1  6  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8783 23:07:10.050289   1  6  8 | B1->B0 | 2525 3d3d | 0 0 | (1 1) (1 1)

 8784 23:07:10.053862   1  6 12 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)

 8785 23:07:10.057337   1  6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8786 23:07:10.063537   1  6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8787 23:07:10.067612   1  6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8788 23:07:10.070367   1  6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8789 23:07:10.074143   1  7  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8790 23:07:10.080519   1  7  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 8791 23:07:10.083435   1  7  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 8792 23:07:10.087640   1  7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 8793 23:07:10.093449   1  7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 8794 23:07:10.097556   1  7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8795 23:07:10.100334   1  7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8796 23:07:10.107072   1  7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8797 23:07:10.110700   1  8  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8798 23:07:10.114072   1  8  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8799 23:07:10.120309   1  8  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8800 23:07:10.123941   1  8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8801 23:07:10.127005   1  8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8802 23:07:10.133949   1  8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8803 23:07:10.137063   1  8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8804 23:07:10.140434   1  8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8805 23:07:10.147172   1  9  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8806 23:07:10.150627   1  9  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 8807 23:07:10.154216   1  9  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 8808 23:07:10.157741   1  9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 8809 23:07:10.160347  Total UI for P1: 0, mck2ui 16

 8810 23:07:10.163738  best dqsien dly found for B0: ( 1,  9,  6)

 8811 23:07:10.170572   1  9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8812 23:07:10.173888  Total UI for P1: 0, mck2ui 16

 8813 23:07:10.177374  best dqsien dly found for B1: ( 1,  9, 12)

 8814 23:07:10.180636  best DQS0 dly(MCK, UI, PI) = (1, 9, 6)

 8815 23:07:10.184174  best DQS1 dly(MCK, UI, PI) = (1, 9, 12)

 8816 23:07:10.184265  

 8817 23:07:10.187432  best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)

 8818 23:07:10.190683  best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)

 8819 23:07:10.194143  [Gating] SW calibration Done

 8820 23:07:10.194220  ==

 8821 23:07:10.197798  Dram Type= 6, Freq= 0, CH_1, rank 1

 8822 23:07:10.200892  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8823 23:07:10.200964  ==

 8824 23:07:10.203686  RX Vref Scan: 0

 8825 23:07:10.203754  

 8826 23:07:10.203819  RX Vref 0 -> 0, step: 1

 8827 23:07:10.206998  

 8828 23:07:10.207091  RX Delay 0 -> 252, step: 8

 8829 23:07:10.210376  iDelay=200, Bit 0, Center 135 (80 ~ 191) 112

 8830 23:07:10.217162  iDelay=200, Bit 1, Center 127 (72 ~ 183) 112

 8831 23:07:10.220411  iDelay=200, Bit 2, Center 119 (64 ~ 175) 112

 8832 23:07:10.223978  iDelay=200, Bit 3, Center 131 (80 ~ 183) 104

 8833 23:07:10.227377  iDelay=200, Bit 4, Center 131 (80 ~ 183) 104

 8834 23:07:10.230355  iDelay=200, Bit 5, Center 147 (96 ~ 199) 104

 8835 23:07:10.237062  iDelay=200, Bit 6, Center 143 (88 ~ 199) 112

 8836 23:07:10.240397  iDelay=200, Bit 7, Center 123 (72 ~ 175) 104

 8837 23:07:10.243703  iDelay=200, Bit 8, Center 115 (56 ~ 175) 120

 8838 23:07:10.247137  iDelay=200, Bit 9, Center 115 (56 ~ 175) 120

 8839 23:07:10.250443  iDelay=200, Bit 10, Center 131 (72 ~ 191) 120

 8840 23:07:10.257054  iDelay=200, Bit 11, Center 119 (64 ~ 175) 112

 8841 23:07:10.260491  iDelay=200, Bit 12, Center 135 (80 ~ 191) 112

 8842 23:07:10.263565  iDelay=200, Bit 13, Center 135 (80 ~ 191) 112

 8843 23:07:10.266947  iDelay=200, Bit 14, Center 135 (80 ~ 191) 112

 8844 23:07:10.270630  iDelay=200, Bit 15, Center 135 (80 ~ 191) 112

 8845 23:07:10.273599  ==

 8846 23:07:10.277285  Dram Type= 6, Freq= 0, CH_1, rank 1

 8847 23:07:10.280480  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8848 23:07:10.280556  ==

 8849 23:07:10.280618  DQS Delay:

 8850 23:07:10.284018  DQS0 = 0, DQS1 = 0

 8851 23:07:10.284088  DQM Delay:

 8852 23:07:10.287320  DQM0 = 132, DQM1 = 127

 8853 23:07:10.287421  DQ Delay:

 8854 23:07:10.290743  DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131

 8855 23:07:10.294374  DQ4 =131, DQ5 =147, DQ6 =143, DQ7 =123

 8856 23:07:10.297328  DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119

 8857 23:07:10.300457  DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135

 8858 23:07:10.300598  

 8859 23:07:10.300692  

 8860 23:07:10.300794  ==

 8861 23:07:10.303660  Dram Type= 6, Freq= 0, CH_1, rank 1

 8862 23:07:10.310230  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8863 23:07:10.310341  ==

 8864 23:07:10.310485  

 8865 23:07:10.310584  

 8866 23:07:10.310661  	TX Vref Scan disable

 8867 23:07:10.314354   == TX Byte 0 ==

 8868 23:07:10.317278  Update DQ  dly =983 (3 ,6, 23)  DQ  OEN =(3 ,3)

 8869 23:07:10.320689  Update DQM dly =983 (3 ,6, 23)  DQM OEN =(3 ,3)

 8870 23:07:10.324136   == TX Byte 1 ==

 8871 23:07:10.327552  Update DQ  dly =982 (3 ,6, 22)  DQ  OEN =(3 ,3)

 8872 23:07:10.331046  Update DQM dly =982 (3 ,6, 22)  DQM OEN =(3 ,3)

 8873 23:07:10.334136  ==

 8874 23:07:10.337412  Dram Type= 6, Freq= 0, CH_1, rank 1

 8875 23:07:10.340836  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8876 23:07:10.340915  ==

 8877 23:07:10.353745  

 8878 23:07:10.357309  TX Vref early break, caculate TX vref

 8879 23:07:10.360791  TX Vref=16, minBit 0, minWin=23, winSum=378

 8880 23:07:10.363804  TX Vref=18, minBit 8, minWin=23, winSum=387

 8881 23:07:10.367126  TX Vref=20, minBit 8, minWin=23, winSum=394

 8882 23:07:10.370181  TX Vref=22, minBit 1, minWin=24, winSum=401

 8883 23:07:10.374027  TX Vref=24, minBit 0, minWin=25, winSum=411

 8884 23:07:10.380760  TX Vref=26, minBit 8, minWin=24, winSum=414

 8885 23:07:10.383904  TX Vref=28, minBit 0, minWin=26, winSum=424

 8886 23:07:10.386876  TX Vref=30, minBit 0, minWin=25, winSum=419

 8887 23:07:10.390182  TX Vref=32, minBit 0, minWin=25, winSum=413

 8888 23:07:10.394230  TX Vref=34, minBit 0, minWin=24, winSum=403

 8889 23:07:10.397193  TX Vref=36, minBit 0, minWin=24, winSum=395

 8890 23:07:10.403865  [TxChooseVref] Worse bit 0, Min win 26, Win sum 424, Final Vref 28

 8891 23:07:10.403948  

 8892 23:07:10.407238  Final TX Range 0 Vref 28

 8893 23:07:10.407322  

 8894 23:07:10.407386  ==

 8895 23:07:10.410386  Dram Type= 6, Freq= 0, CH_1, rank 1

 8896 23:07:10.413508  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8897 23:07:10.413616  ==

 8898 23:07:10.413708  

 8899 23:07:10.413796  

 8900 23:07:10.417431  	TX Vref Scan disable

 8901 23:07:10.423916  [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps

 8902 23:07:10.424000   == TX Byte 0 ==

 8903 23:07:10.427481  u2DelayCellOfst[0]=17 cells (5 PI)

 8904 23:07:10.430259  u2DelayCellOfst[1]=10 cells (3 PI)

 8905 23:07:10.434215  u2DelayCellOfst[2]=0 cells (0 PI)

 8906 23:07:10.437125  u2DelayCellOfst[3]=7 cells (2 PI)

 8907 23:07:10.440679  u2DelayCellOfst[4]=10 cells (3 PI)

 8908 23:07:10.444678  u2DelayCellOfst[5]=17 cells (5 PI)

 8909 23:07:10.446873  u2DelayCellOfst[6]=17 cells (5 PI)

 8910 23:07:10.450819  u2DelayCellOfst[7]=3 cells (1 PI)

 8911 23:07:10.453592  Update DQ  dly =980 (3 ,6, 20)  DQ  OEN =(3 ,3)

 8912 23:07:10.456991  Update DQM dly =982 (3 ,6, 22)  DQM OEN =(3 ,3)

 8913 23:07:10.460652   == TX Byte 1 ==

 8914 23:07:10.460737  u2DelayCellOfst[8]=0 cells (0 PI)

 8915 23:07:10.463832  u2DelayCellOfst[9]=3 cells (1 PI)

 8916 23:07:10.467317  u2DelayCellOfst[10]=10 cells (3 PI)

 8917 23:07:10.470349  u2DelayCellOfst[11]=7 cells (2 PI)

 8918 23:07:10.473633  u2DelayCellOfst[12]=14 cells (4 PI)

 8919 23:07:10.477135  u2DelayCellOfst[13]=14 cells (4 PI)

 8920 23:07:10.480101  u2DelayCellOfst[14]=17 cells (5 PI)

 8921 23:07:10.483816  u2DelayCellOfst[15]=14 cells (4 PI)

 8922 23:07:10.487040  Update DQ  dly =980 (3 ,6, 20)  DQ  OEN =(3 ,3)

 8923 23:07:10.493952  Update DQM dly =982 (3 ,6, 22)  DQM OEN =(3 ,3)

 8924 23:07:10.494037  DramC Write-DBI on

 8925 23:07:10.494114  ==

 8926 23:07:10.496947  Dram Type= 6, Freq= 0, CH_1, rank 1

 8927 23:07:10.500649  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8928 23:07:10.500732  ==

 8929 23:07:10.503722  

 8930 23:07:10.503803  

 8931 23:07:10.503868  	TX Vref Scan disable

 8932 23:07:10.507100   == TX Byte 0 ==

 8933 23:07:10.510862  Update DQM dly =724 (2 ,6, 20)  DQM OEN =(3 ,3)

 8934 23:07:10.513974   == TX Byte 1 ==

 8935 23:07:10.516922  Update DQM dly =723 (2 ,6, 19)  DQM OEN =(3 ,3)

 8936 23:07:10.517005  DramC Write-DBI off

 8937 23:07:10.520570  

 8938 23:07:10.520651  [DATLAT]

 8939 23:07:10.520715  Freq=1600, CH1 RK1

 8940 23:07:10.520777  

 8941 23:07:10.523555  DATLAT Default: 0xf

 8942 23:07:10.523637  0, 0xFFFF, sum = 0

 8943 23:07:10.527290  1, 0xFFFF, sum = 0

 8944 23:07:10.527374  2, 0xFFFF, sum = 0

 8945 23:07:10.530693  3, 0xFFFF, sum = 0

 8946 23:07:10.530777  4, 0xFFFF, sum = 0

 8947 23:07:10.534233  5, 0xFFFF, sum = 0

 8948 23:07:10.534343  6, 0xFFFF, sum = 0

 8949 23:07:10.536978  7, 0xFFFF, sum = 0

 8950 23:07:10.537061  8, 0xFFFF, sum = 0

 8951 23:07:10.540760  9, 0xFFFF, sum = 0

 8952 23:07:10.544008  10, 0xFFFF, sum = 0

 8953 23:07:10.544092  11, 0xFFFF, sum = 0

 8954 23:07:10.547376  12, 0xFFFF, sum = 0

 8955 23:07:10.547486  13, 0xFFFF, sum = 0

 8956 23:07:10.551052  14, 0x0, sum = 1

 8957 23:07:10.551136  15, 0x0, sum = 2

 8958 23:07:10.554092  16, 0x0, sum = 3

 8959 23:07:10.554175  17, 0x0, sum = 4

 8960 23:07:10.554241  best_step = 15

 8961 23:07:10.554301  

 8962 23:07:10.557468  ==

 8963 23:07:10.560769  Dram Type= 6, Freq= 0, CH_1, rank 1

 8964 23:07:10.564011  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8965 23:07:10.564094  ==

 8966 23:07:10.564159  RX Vref Scan: 0

 8967 23:07:10.564219  

 8968 23:07:10.567639  RX Vref 0 -> 0, step: 1

 8969 23:07:10.567721  

 8970 23:07:10.570699  RX Delay 11 -> 252, step: 4

 8971 23:07:10.573830  iDelay=191, Bit 0, Center 134 (83 ~ 186) 104

 8972 23:07:10.577324  iDelay=191, Bit 1, Center 126 (75 ~ 178) 104

 8973 23:07:10.584316  iDelay=191, Bit 2, Center 118 (67 ~ 170) 104

 8974 23:07:10.587423  iDelay=191, Bit 3, Center 130 (79 ~ 182) 104

 8975 23:07:10.590802  iDelay=191, Bit 4, Center 130 (79 ~ 182) 104

 8976 23:07:10.593847  iDelay=191, Bit 5, Center 142 (95 ~ 190) 96

 8977 23:07:10.597755  iDelay=191, Bit 6, Center 138 (87 ~ 190) 104

 8978 23:07:10.603766  iDelay=191, Bit 7, Center 124 (75 ~ 174) 100

 8979 23:07:10.607513  iDelay=191, Bit 8, Center 114 (59 ~ 170) 112

 8980 23:07:10.610796  iDelay=191, Bit 9, Center 112 (59 ~ 166) 108

 8981 23:07:10.614380  iDelay=191, Bit 10, Center 128 (75 ~ 182) 108

 8982 23:07:10.617577  iDelay=191, Bit 11, Center 120 (67 ~ 174) 108

 8983 23:07:10.624296  iDelay=191, Bit 12, Center 134 (83 ~ 186) 104

 8984 23:07:10.627566  iDelay=191, Bit 13, Center 134 (83 ~ 186) 104

 8985 23:07:10.630851  iDelay=191, Bit 14, Center 134 (83 ~ 186) 104

 8986 23:07:10.634592  iDelay=191, Bit 15, Center 134 (83 ~ 186) 104

 8987 23:07:10.634668  ==

 8988 23:07:10.637398  Dram Type= 6, Freq= 0, CH_1, rank 1

 8989 23:07:10.641055  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8990 23:07:10.644449  ==

 8991 23:07:10.644524  DQS Delay:

 8992 23:07:10.644586  DQS0 = 0, DQS1 = 0

 8993 23:07:10.647585  DQM Delay:

 8994 23:07:10.647657  DQM0 = 130, DQM1 = 126

 8995 23:07:10.650724  DQ Delay:

 8996 23:07:10.654428  DQ0 =134, DQ1 =126, DQ2 =118, DQ3 =130

 8997 23:07:10.657597  DQ4 =130, DQ5 =142, DQ6 =138, DQ7 =124

 8998 23:07:10.661140  DQ8 =114, DQ9 =112, DQ10 =128, DQ11 =120

 8999 23:07:10.664519  DQ12 =134, DQ13 =134, DQ14 =134, DQ15 =134

 9000 23:07:10.664591  

 9001 23:07:10.664651  

 9002 23:07:10.664708  

 9003 23:07:10.667723  [DramC_TX_OE_Calibration] TA2

 9004 23:07:10.671100  Original DQ_B0 (3 6) =30, OEN = 27

 9005 23:07:10.674539  Original DQ_B1 (3 6) =30, OEN = 27

 9006 23:07:10.674610  24, 0x0, End_B0=24 End_B1=24

 9007 23:07:10.677610  25, 0x0, End_B0=25 End_B1=25

 9008 23:07:10.680910  26, 0x0, End_B0=26 End_B1=26

 9009 23:07:10.684364  27, 0x0, End_B0=27 End_B1=27

 9010 23:07:10.684438  28, 0x0, End_B0=28 End_B1=28

 9011 23:07:10.688003  29, 0x0, End_B0=29 End_B1=29

 9012 23:07:10.691404  30, 0x0, End_B0=30 End_B1=30

 9013 23:07:10.694572  31, 0x4141, End_B0=30 End_B1=30

 9014 23:07:10.698049  Byte0 end_step=30  best_step=27

 9015 23:07:10.701287  Byte1 end_step=30  best_step=27

 9016 23:07:10.701396  Byte0 TX OE(2T, 0.5T) = (3, 3)

 9017 23:07:10.704593  Byte1 TX OE(2T, 0.5T) = (3, 3)

 9018 23:07:10.704675  

 9019 23:07:10.704740  

 9020 23:07:10.714671  [DQSOSCAuto] RK1, (LSB)MR18= 0xd14, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 403 ps

 9021 23:07:10.714755  CH1 RK1: MR19=303, MR18=D14

 9022 23:07:10.721084  CH1_RK1: MR19=0x303, MR18=0xD14, DQSOSC=399, MR23=63, INC=23, DEC=15

 9023 23:07:10.724893  [RxdqsGatingPostProcess] freq 1600

 9024 23:07:10.731350  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3

 9025 23:07:10.734361  best DQS0 dly(2T, 0.5T) = (1, 1)

 9026 23:07:10.737999  best DQS1 dly(2T, 0.5T) = (1, 1)

 9027 23:07:10.741448  best DQS0 P1 dly(2T, 0.5T) = (1, 5)

 9028 23:07:10.745073  best DQS1 P1 dly(2T, 0.5T) = (1, 5)

 9029 23:07:10.745155  best DQS0 dly(2T, 0.5T) = (1, 1)

 9030 23:07:10.748040  best DQS1 dly(2T, 0.5T) = (1, 1)

 9031 23:07:10.751884  best DQS0 P1 dly(2T, 0.5T) = (1, 5)

 9032 23:07:10.754522  best DQS1 P1 dly(2T, 0.5T) = (1, 5)

 9033 23:07:10.758354  Pre-setting of DQS Precalculation

 9034 23:07:10.764739  [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15

 9035 23:07:10.771539  sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0

 9036 23:07:10.778059  calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464

 9037 23:07:10.778142  

 9038 23:07:10.778206  

 9039 23:07:10.781527  [Calibration Summary] 3200 Mbps

 9040 23:07:10.781609  CH 0, Rank 0

 9041 23:07:10.784858  SW Impedance     : PASS

 9042 23:07:10.788452  DUTY Scan        : NO K

 9043 23:07:10.788538  ZQ Calibration   : PASS

 9044 23:07:10.791203  Jitter Meter     : NO K

 9045 23:07:10.791324  CBT Training     : PASS

 9046 23:07:10.794791  Write leveling   : PASS

 9047 23:07:10.798127  RX DQS gating    : PASS

 9048 23:07:10.798234  RX DQ/DQS(RDDQC) : PASS

 9049 23:07:10.801454  TX DQ/DQS        : PASS

 9050 23:07:10.804488  RX DATLAT        : PASS

 9051 23:07:10.804569  RX DQ/DQS(Engine): PASS

 9052 23:07:10.808253  TX OE            : PASS

 9053 23:07:10.808336  All Pass.

 9054 23:07:10.808400  

 9055 23:07:10.811161  CH 0, Rank 1

 9056 23:07:10.811243  SW Impedance     : PASS

 9057 23:07:10.814714  DUTY Scan        : NO K

 9058 23:07:10.818081  ZQ Calibration   : PASS

 9059 23:07:10.818189  Jitter Meter     : NO K

 9060 23:07:10.821032  CBT Training     : PASS

 9061 23:07:10.824584  Write leveling   : PASS

 9062 23:07:10.824666  RX DQS gating    : PASS

 9063 23:07:10.828213  RX DQ/DQS(RDDQC) : PASS

 9064 23:07:10.831434  TX DQ/DQS        : PASS

 9065 23:07:10.831566  RX DATLAT        : PASS

 9066 23:07:10.834554  RX DQ/DQS(Engine): PASS

 9067 23:07:10.837873  TX OE            : PASS

 9068 23:07:10.837983  All Pass.

 9069 23:07:10.838075  

 9070 23:07:10.838164  CH 1, Rank 0

 9071 23:07:10.841105  SW Impedance     : PASS

 9072 23:07:10.841223  DUTY Scan        : NO K

 9073 23:07:10.844739  ZQ Calibration   : PASS

 9074 23:07:10.848108  Jitter Meter     : NO K

 9075 23:07:10.848208  CBT Training     : PASS

 9076 23:07:10.851508  Write leveling   : PASS

 9077 23:07:10.854538  RX DQS gating    : PASS

 9078 23:07:10.854646  RX DQ/DQS(RDDQC) : PASS

 9079 23:07:10.858106  TX DQ/DQS        : PASS

 9080 23:07:10.861720  RX DATLAT        : PASS

 9081 23:07:10.861801  RX DQ/DQS(Engine): PASS

 9082 23:07:10.864618  TX OE            : PASS

 9083 23:07:10.864687  All Pass.

 9084 23:07:10.864748  

 9085 23:07:10.867685  CH 1, Rank 1

 9086 23:07:10.867757  SW Impedance     : PASS

 9087 23:07:10.871161  DUTY Scan        : NO K

 9088 23:07:10.874673  ZQ Calibration   : PASS

 9089 23:07:10.874755  Jitter Meter     : NO K

 9090 23:07:10.877889  CBT Training     : PASS

 9091 23:07:10.877971  Write leveling   : PASS

 9092 23:07:10.881708  RX DQS gating    : PASS

 9093 23:07:10.885218  RX DQ/DQS(RDDQC) : PASS

 9094 23:07:10.885301  TX DQ/DQS        : PASS

 9095 23:07:10.887832  RX DATLAT        : PASS

 9096 23:07:10.891457  RX DQ/DQS(Engine): PASS

 9097 23:07:10.891545  TX OE            : PASS

 9098 23:07:10.895204  All Pass.

 9099 23:07:10.895313  

 9100 23:07:10.895406  DramC Write-DBI on

 9101 23:07:10.898423  	PER_BANK_REFRESH: Hybrid Mode

 9102 23:07:10.898522  TX_TRACKING: ON

 9103 23:07:10.908070  [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0

 9104 23:07:10.918021  sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1

 9105 23:07:10.924741  calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464

 9106 23:07:10.928152  [FAST_K] Save calibration result to emmc

 9107 23:07:10.931365  sync common calibartion params.

 9108 23:07:10.931448  sync cbt_mode0:1, 1:1

 9109 23:07:10.934543  dram_init: ddr_geometry: 2

 9110 23:07:10.938158  dram_init: ddr_geometry: 2

 9111 23:07:10.938240  dram_init: ddr_geometry: 2

 9112 23:07:10.941252  0:dram_rank_size:100000000

 9113 23:07:10.944693  1:dram_rank_size:100000000

 9114 23:07:10.951421  sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000

 9115 23:07:10.951510  DFS_SHUFFLE_HW_MODE: ON

 9116 23:07:10.954740  dramc_set_vcore_voltage set vcore to 725000

 9117 23:07:10.958097  Read voltage for 1600, 0

 9118 23:07:10.958174  Vio18 = 0

 9119 23:07:10.961404  Vcore = 725000

 9120 23:07:10.961486  Vdram = 0

 9121 23:07:10.961567  Vddq = 0

 9122 23:07:10.964398  Vmddr = 0

 9123 23:07:10.964478  switch to 3200 Mbps bootup

 9124 23:07:10.968254  [DramcRunTimeConfig]

 9125 23:07:10.968331  PHYPLL

 9126 23:07:10.971208  DPM_CONTROL_AFTERK: ON

 9127 23:07:10.971286  PER_BANK_REFRESH: ON

 9128 23:07:10.975024  REFRESH_OVERHEAD_REDUCTION: ON

 9129 23:07:10.978415  CMD_PICG_NEW_MODE: OFF

 9130 23:07:10.978535  XRTWTW_NEW_MODE: ON

 9131 23:07:10.981110  XRTRTR_NEW_MODE: ON

 9132 23:07:10.981190  TX_TRACKING: ON

 9133 23:07:10.985044  RDSEL_TRACKING: OFF

 9134 23:07:10.988075  DQS Precalculation for DVFS: ON

 9135 23:07:10.988150  RX_TRACKING: OFF

 9136 23:07:10.991309  HW_GATING DBG: ON

 9137 23:07:10.991384  ZQCS_ENABLE_LP4: ON

 9138 23:07:10.994875  RX_PICG_NEW_MODE: ON

 9139 23:07:10.994951  TX_PICG_NEW_MODE: ON

 9140 23:07:10.997981  ENABLE_RX_DCM_DPHY: ON

 9141 23:07:11.001147  LOWPOWER_GOLDEN_SETTINGS(DCM): ON

 9142 23:07:11.004815  DUMMY_READ_FOR_TRACKING: OFF

 9143 23:07:11.004887  !!! SPM_CONTROL_AFTERK: OFF

 9144 23:07:11.008377  !!! SPM could not control APHY

 9145 23:07:11.011311  IMPEDANCE_TRACKING: ON

 9146 23:07:11.011383  TEMP_SENSOR: ON

 9147 23:07:11.015032  HW_SAVE_FOR_SR: OFF

 9148 23:07:11.018138  CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF

 9149 23:07:11.021611  PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF

 9150 23:07:11.021695  Read ODT Tracking: ON

 9151 23:07:11.025088  Refresh Rate DeBounce: ON

 9152 23:07:11.028488  DFS_NO_QUEUE_FLUSH: ON

 9153 23:07:11.031605  DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF

 9154 23:07:11.031687  ENABLE_DFS_RUNTIME_MRW: OFF

 9155 23:07:11.034899  DDR_RESERVE_NEW_MODE: ON

 9156 23:07:11.037708  MR_CBT_SWITCH_FREQ: ON

 9157 23:07:11.037792  =========================

 9158 23:07:11.057980  [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)

 9159 23:07:11.061178  dram_init: ddr_geometry: 2

 9160 23:07:11.079535  [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)

 9161 23:07:11.083311  dram_init: dram init end (result: 0)

 9162 23:07:11.090048  DRAM-K: Full calibration passed in 24547 msecs

 9163 23:07:11.093380  MRC: failed to locate region type 0.

 9164 23:07:11.093463  DRAM rank0 size:0x100000000,

 9165 23:07:11.096796  DRAM rank1 size=0x100000000

 9166 23:07:11.106377  Mapping address range [0x40000000:0x240000000) as     cacheable | read-write | non-secure | normal

 9167 23:07:11.113117  Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal

 9168 23:07:11.119753  Backing address range [0x40000000:0x80000000) with new page table @0x00112000

 9169 23:07:11.126342  Backing address range [0x40000000:0x40200000) with new page table @0x00113000

 9170 23:07:11.129900  DRAM rank0 size:0x100000000,

 9171 23:07:11.133491  DRAM rank1 size=0x100000000

 9172 23:07:11.133573  CBMEM:

 9173 23:07:11.136628  IMD: root @ 0xfffff000 254 entries.

 9174 23:07:11.139515  IMD: root @ 0xffffec00 62 entries.

 9175 23:07:11.143035  FMAP: area RO_VPD found @ 3f8000 (32768 bytes)

 9176 23:07:11.146579  WARNING: RO_VPD is uninitialized or empty.

 9177 23:07:11.153139  FMAP: area RW_VPD found @ 577000 (16384 bytes)

 9178 23:07:11.160059  CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80

 9179 23:07:11.173110  read SPI 0x42894 0xe01e: 6226 us, 9215 KB/s, 73.720 Mbps

 9180 23:07:11.183519  BS: romstage times (exec / console): total (unknown) / 24057 ms

 9181 23:07:11.183599  

 9182 23:07:11.183663  

 9183 23:07:11.193559  coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...

 9184 23:07:11.197246  ARM64: Exception handlers installed.

 9185 23:07:11.200714  ARM64: Testing exception

 9186 23:07:11.203804  ARM64: Done test exception

 9187 23:07:11.203886  Enumerating buses...

 9188 23:07:11.207065  Show all devs... Before device enumeration.

 9189 23:07:11.210562  Root Device: enabled 1

 9190 23:07:11.213963  CPU_CLUSTER: 0: enabled 1

 9191 23:07:11.214046  CPU: 00: enabled 1

 9192 23:07:11.216920  Compare with tree...

 9193 23:07:11.217008  Root Device: enabled 1

 9194 23:07:11.220565   CPU_CLUSTER: 0: enabled 1

 9195 23:07:11.223603    CPU: 00: enabled 1

 9196 23:07:11.223700  Root Device scanning...

 9197 23:07:11.227801  scan_static_bus for Root Device

 9198 23:07:11.230727  CPU_CLUSTER: 0 enabled

 9199 23:07:11.233992  scan_static_bus for Root Device done

 9200 23:07:11.237856  scan_bus: bus Root Device finished in 8 msecs

 9201 23:07:11.238060  done

 9202 23:07:11.243958  BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms

 9203 23:07:11.247425  FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)

 9204 23:07:11.253740  SF: Detected 00 0000 with sector size 0x1000, total 0x800000

 9205 23:07:11.257340  BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms

 9206 23:07:11.261132  Allocating resources...

 9207 23:07:11.261422  Reading resources...

 9208 23:07:11.267938  Root Device read_resources bus 0 link: 0

 9209 23:07:11.268334  DRAM rank0 size:0x100000000,

 9210 23:07:11.271017  DRAM rank1 size=0x100000000

 9211 23:07:11.274351  CPU_CLUSTER: 0 read_resources bus 0 link: 0

 9212 23:07:11.277403  CPU: 00 missing read_resources

 9213 23:07:11.281165  CPU_CLUSTER: 0 read_resources bus 0 link: 0 done

 9214 23:07:11.287419  Root Device read_resources bus 0 link: 0 done

 9215 23:07:11.287898  Done reading resources.

 9216 23:07:11.294019  Show resources in subtree (Root Device)...After reading.

 9217 23:07:11.297712   Root Device child on link 0 CPU_CLUSTER: 0

 9218 23:07:11.300842    CPU_CLUSTER: 0 child on link 0 CPU: 00

 9219 23:07:11.311457    CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0

 9220 23:07:11.311961     CPU: 00

 9221 23:07:11.314023  Root Device assign_resources, bus 0 link: 0

 9222 23:07:11.317249  CPU_CLUSTER: 0 missing set_resources

 9223 23:07:11.320990  Root Device assign_resources, bus 0 link: 0 done

 9224 23:07:11.324551  Done setting resources.

 9225 23:07:11.330749  Show resources in subtree (Root Device)...After assigning values.

 9226 23:07:11.334498   Root Device child on link 0 CPU_CLUSTER: 0

 9227 23:07:11.337773    CPU_CLUSTER: 0 child on link 0 CPU: 00

 9228 23:07:11.347450    CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0

 9229 23:07:11.347878     CPU: 00

 9230 23:07:11.350978  Done allocating resources.

 9231 23:07:11.354364  BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms

 9232 23:07:11.357427  Enabling resources...

 9233 23:07:11.357850  done.

 9234 23:07:11.361163  BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms

 9235 23:07:11.364297  Initializing devices...

 9236 23:07:11.367925  Root Device init

 9237 23:07:11.368507  init hardware done!

 9238 23:07:11.370935  0x00000018: ctrlr->caps

 9239 23:07:11.371363  52.000 MHz: ctrlr->f_max

 9240 23:07:11.374102  0.400 MHz: ctrlr->f_min

 9241 23:07:11.378055  0x40ff8080: ctrlr->voltages

 9242 23:07:11.378659  sclk: 390625

 9243 23:07:11.380889  Bus Width = 1

 9244 23:07:11.381307  sclk: 390625

 9245 23:07:11.381641  Bus Width = 1

 9246 23:07:11.384654  Early init status = 3

 9247 23:07:11.387259  out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00 

 9248 23:07:11.391817  in-header: 03 fc 00 00 01 00 00 00 

 9249 23:07:11.395286  in-data: 00 

 9250 23:07:11.398238  out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01 

 9251 23:07:11.406591  in-header: 03 fd 00 00 00 00 00 00 

 9252 23:07:11.407304  in-data: 

 9253 23:07:11.409750  out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00 

 9254 23:07:11.414224  in-header: 03 fc 00 00 01 00 00 00 

 9255 23:07:11.417320  in-data: 00 

 9256 23:07:11.420475  out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01 

 9257 23:07:11.426694  in-header: 03 fd 00 00 00 00 00 00 

 9258 23:07:11.429597  in-data: 

 9259 23:07:11.433233  [SSUSB] Setting up USB HOST controller...

 9260 23:07:11.436017  [SSUSB] u3phy_ports_enable u2p:1, u3p:1

 9261 23:07:11.439990  [SSUSB] phy power-on done.

 9262 23:07:11.443062  FMAP: area COREBOOT found @ 21000 (4014080 bytes)

 9263 23:07:11.449345  CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c

 9264 23:07:11.453041  mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)

 9265 23:07:11.460051  CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c

 9266 23:07:11.466184  read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps

 9267 23:07:11.472752  mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)

 9268 23:07:11.479971  CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204

 9269 23:07:11.485961  read SPI 0x705bc 0x1f6a: 923 us, 8712 KB/s, 69.696 Mbps

 9270 23:07:11.486389  SPM: binary array size = 0x9dc

 9271 23:07:11.493214  SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)

 9272 23:07:11.499957  spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18

 9273 23:07:11.506534  mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)

 9274 23:07:11.509305  SPM: spm_init done in 34 msecs, spm pc = 0x3f4

 9275 23:07:11.512731  configure_display: Starting display init

 9276 23:07:11.549977  anx7625_power_on_init: Init interface.

 9277 23:07:11.552650  anx7625_disable_pd_protocol: Disabled PD feature.

 9278 23:07:11.556105  anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.

 9279 23:07:11.583808  anx7625_start_dp_work: Secure OCM version=00

 9280 23:07:11.587140  anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91

 9281 23:07:11.601697  sp_tx_get_edid_block: EDID Block = 1

 9282 23:07:11.704585  Extracted contents:

 9283 23:07:11.708649  header:          00 ff ff ff ff ff ff 00

 9284 23:07:11.711439  serial number:   26 cf 7d 05 00 00 00 00 00 1e

 9285 23:07:11.714638  version:         01 04

 9286 23:07:11.718226  basic params:    95 1f 11 78 0a

 9287 23:07:11.721022  chroma info:     76 90 94 55 54 90 27 21 50 54

 9288 23:07:11.724601  established:     00 00 00

 9289 23:07:11.730787  standard:        01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01

 9290 23:07:11.734258  descriptor 1:    38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19

 9291 23:07:11.741047  descriptor 2:    00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

 9292 23:07:11.747523  descriptor 3:    00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20

 9293 23:07:11.754062  descriptor 4:    00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a

 9294 23:07:11.757311  extensions:      00

 9295 23:07:11.757735  checksum:        fb

 9296 23:07:11.758119  

 9297 23:07:11.761278  Manufacturer: IVO Model 57d Serial Number 0

 9298 23:07:11.764539  Made week 0 of 2020

 9299 23:07:11.765129  EDID version: 1.4

 9300 23:07:11.767773  Digital display

 9301 23:07:11.770898  6 bits per primary color channel

 9302 23:07:11.771320  DisplayPort interface

 9303 23:07:11.774540  Maximum image size: 31 cm x 17 cm

 9304 23:07:11.775068  Gamma: 220%

 9305 23:07:11.778328  Check DPMS levels

 9306 23:07:11.781555  Supported color formats: RGB 4:4:4, YCrCb 4:2:2

 9307 23:07:11.784772  First detailed timing is preferred timing

 9308 23:07:11.787707  Established timings supported:

 9309 23:07:11.790970  Standard timings supported:

 9310 23:07:11.791390  Detailed timings

 9311 23:07:11.797797  Hex of detail: 383680a07038204018303c0035ae10000019

 9312 23:07:11.801540  Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm

 9313 23:07:11.804149                 0780 0798 07c8 0820 hborder 0

 9314 23:07:11.811270                 0438 043b 0447 0458 vborder 0

 9315 23:07:11.811692                 -hsync -vsync

 9316 23:07:11.814507  Did detailed timing

 9317 23:07:11.817774  Hex of detail: 000000000000000000000000000000000000

 9318 23:07:11.821007  Manufacturer-specified data, tag 0

 9319 23:07:11.827719  Hex of detail: 000000fe00496e666f566973696f6e0a2020

 9320 23:07:11.828140  ASCII string: InfoVision

 9321 23:07:11.834208  Hex of detail: 000000fe00523134304e574635205248200a

 9322 23:07:11.834743  ASCII string: R140NWF5 RH 

 9323 23:07:11.838315  Checksum

 9324 23:07:11.838879  Checksum: 0xfb (valid)

 9325 23:07:11.845104  configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz

 9326 23:07:11.845750  DSI data_rate: 832800000 bps

 9327 23:07:11.851973  anx7625_parse_edid: detected IVO panel, use k value 0x3b

 9328 23:07:11.855506  anx7625_parse_edid: pixelclock(138800).

 9329 23:07:11.858995   hactive(1920), hsync(48), hfp(24), hbp(88)

 9330 23:07:11.862043   vactive(1080), vsync(12), vfp(3), vbp(17)

 9331 23:07:11.865515  anx7625_dsi_config: config dsi.

 9332 23:07:11.872183  anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).

 9333 23:07:11.886552  anx7625_dsi_config: success to config DSI

 9334 23:07:11.889852  anx7625_dp_start: MIPI phy setup OK.

 9335 23:07:11.893098  mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4

 9336 23:07:11.896073  mtk_ddp_mode_set invalid vrefresh 60

 9337 23:07:11.899857  main_disp_path_setup

 9338 23:07:11.900276  ovl_layer_smi_id_en

 9339 23:07:11.903139  ovl_layer_smi_id_en

 9340 23:07:11.903560  ccorr_config

 9341 23:07:11.903892  aal_config

 9342 23:07:11.906442  gamma_config

 9343 23:07:11.906864  postmask_config

 9344 23:07:11.909542  dither_config

 9345 23:07:11.913108  framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32

 9346 23:07:11.919890                     x_res x y_res: 1920 x 1080, size: 8294400 at 0x0

 9347 23:07:11.923317  Root Device init finished in 553 msecs

 9348 23:07:11.923886  CPU_CLUSTER: 0 init

 9349 23:07:11.933152  Mapping address range [0x00200000:0x00300000) as     cacheable | read-write |     secure | device

 9350 23:07:11.937023  INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff

 9351 23:07:11.940270  APU_MBOX 0x190000b0 = 0x10001

 9352 23:07:11.943384  APU_MBOX 0x190001b0 = 0x10001

 9353 23:07:11.946591  APU_MBOX 0x190005b0 = 0x10001

 9354 23:07:11.949626  APU_MBOX 0x190006b0 = 0x10001

 9355 23:07:11.953819  CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c

 9356 23:07:11.964991  read SPI 0x539f4 0xe237: 6246 us, 9271 KB/s, 74.168 Mbps

 9357 23:07:11.978342  mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)

 9358 23:07:11.984762  CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0

 9359 23:07:11.996114  read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps

 9360 23:07:12.005598  mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)

 9361 23:07:12.008492  CPU_CLUSTER: 0 init finished in 81 msecs

 9362 23:07:12.012267  Devices initialized

 9363 23:07:12.015795  Show all devs... After init.

 9364 23:07:12.016258  Root Device: enabled 1

 9365 23:07:12.018878  CPU_CLUSTER: 0: enabled 1

 9366 23:07:12.021944  CPU: 00: enabled 1

 9367 23:07:12.025644  BS: BS_DEV_INIT run times (exec / console): 211 / 447 ms

 9368 23:07:12.028889  FMAP: area RW_ELOG found @ 57f000 (4096 bytes)

 9369 23:07:12.032077  ELOG: NV offset 0x57f000 size 0x1000

 9370 23:07:12.038627  read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps

 9371 23:07:12.046297  ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024

 9372 23:07:12.048795  ELOG: Event(17) added with size 13 at 2023-12-27 23:07:51 UTC

 9373 23:07:12.051735  out: cmd=0x121: 03 db 21 01 00 00 00 00 

 9374 23:07:12.056290  in-header: 03 f6 00 00 2c 00 00 00 

 9375 23:07:12.069771  in-data: 69 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 

 9376 23:07:12.076676  ELOG: Event(A1) added with size 10 at 2023-12-27 23:07:51 UTC

 9377 23:07:12.083147  elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b

 9378 23:07:12.090182  ELOG: Event(A0) added with size 9 at 2023-12-27 23:07:51 UTC

 9379 23:07:12.093423  elog_add_boot_reason: Logged dev mode boot

 9380 23:07:12.096548  BS: BS_POST_DEVICE entry times (exec / console): 3 / 64 ms

 9381 23:07:12.099994  Finalize devices...

 9382 23:07:12.100415  Devices finalized

 9383 23:07:12.106668  BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms

 9384 23:07:12.109779  Writing coreboot table at 0xffe64000

 9385 23:07:12.113476   0. 000000000010a000-0000000000113fff: RAMSTAGE

 9386 23:07:12.116264   1. 0000000040000000-00000000400fffff: RAM

 9387 23:07:12.120536   2. 0000000040100000-000000004032afff: RAMSTAGE

 9388 23:07:12.126652   3. 000000004032b000-00000000545fffff: RAM

 9389 23:07:12.130139   4. 0000000054600000-000000005465ffff: BL31

 9390 23:07:12.132962   5. 0000000054660000-00000000ffe63fff: RAM

 9391 23:07:12.136778   6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES

 9392 23:07:12.143452   7. 0000000100000000-000000023fffffff: RAM

 9393 23:07:12.143894  Passing 5 GPIOs to payload:

 9394 23:07:12.150024              NAME |       PORT | POLARITY |     VALUE

 9395 23:07:12.153493          EC in RW | 0x000000aa |      low | undefined

 9396 23:07:12.159765      EC interrupt | 0x00000005 |      low | undefined

 9397 23:07:12.163647     TPM interrupt | 0x000000ab |     high | undefined

 9398 23:07:12.166628    SD card detect | 0x00000011 |     high | undefined

 9399 23:07:12.173460    speaker enable | 0x00000093 |     high | undefined

 9400 23:07:12.176523  out: cmd=0x6: 03 f7 06 00 00 00 00 00 

 9401 23:07:12.179967  in-header: 03 f9 00 00 02 00 00 00 

 9402 23:07:12.180394  in-data: 02 00 

 9403 23:07:12.183756  ADC[4]: Raw value=900221 ID=7

 9404 23:07:12.186504  ADC[3]: Raw value=213336 ID=1

 9405 23:07:12.186930  RAM Code: 0x71

 9406 23:07:12.190502  ADC[6]: Raw value=74557 ID=0

 9407 23:07:12.193109  ADC[5]: Raw value=211860 ID=1

 9408 23:07:12.193532  SKU Code: 0x1

 9409 23:07:12.200420  Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 703a

 9410 23:07:12.203357  coreboot table: 964 bytes.

 9411 23:07:12.207069  IMD ROOT    0. 0xfffff000 0x00001000

 9412 23:07:12.210566  IMD SMALL   1. 0xffffe000 0x00001000

 9413 23:07:12.213725  RO MCACHE   2. 0xffffc000 0x00001104

 9414 23:07:12.216858  CONSOLE     3. 0xfff7c000 0x00080000

 9415 23:07:12.221310  FMAP        4. 0xfff7b000 0x00000452

 9416 23:07:12.221879  TIME STAMP  5. 0xfff7a000 0x00000910

 9417 23:07:12.223484  VBOOT WORK  6. 0xfff66000 0x00014000

 9418 23:07:12.226872  RAMOOPS     7. 0xffe66000 0x00100000

 9419 23:07:12.229825  COREBOOT    8. 0xffe64000 0x00002000

 9420 23:07:12.233377  IMD small region:

 9421 23:07:12.236354    IMD ROOT    0. 0xffffec00 0x00000400

 9422 23:07:12.240519    VPD         1. 0xffffeb80 0x0000006c

 9423 23:07:12.243723    MMC STATUS  2. 0xffffeb60 0x00000004

 9424 23:07:12.250223  BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms

 9425 23:07:12.250736  Probing TPM:  done!

 9426 23:07:12.257003  Connected to device vid:did:rid of 1ae0:0028:00

 9427 23:07:12.263747  Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c

 9428 23:07:12.266811  Initialized TPM device CR50 revision 0

 9429 23:07:12.270839  Checking cr50 for pending updates

 9430 23:07:12.276359  Reading cr50 TPM mode

 9431 23:07:12.284868  BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms

 9432 23:07:12.291526  CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098

 9433 23:07:12.331455  read SPI 0x3990ec 0x4f1b0: 34846 us, 9298 KB/s, 74.384 Mbps

 9434 23:07:12.334954  Checking segment from ROM address 0x40100000

 9435 23:07:12.338197  Checking segment from ROM address 0x4010001c

 9436 23:07:12.344427  Loading segment from ROM address 0x40100000

 9437 23:07:12.344511    code (compression=0)

 9438 23:07:12.350928    New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178

 9439 23:07:12.361341  Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178

 9440 23:07:12.361423  it's not compressed!

 9441 23:07:12.367802  [ 0x80000000, 8004f178, 0x821a7280) <- 40100038

 9442 23:07:12.371381  Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108

 9443 23:07:12.391444  Loading segment from ROM address 0x4010001c

 9444 23:07:12.391527    Entry Point 0x80000000

 9445 23:07:12.394973  Loaded segments

 9446 23:07:12.398026  BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms

 9447 23:07:12.404654  Jumping to boot code at 0x80000000(0xffe64000)

 9448 23:07:12.411511  CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes

 9449 23:07:12.418529  CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290

 9450 23:07:12.426348  read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps

 9451 23:07:12.429261  Checking segment from ROM address 0x40100000

 9452 23:07:12.432599  Checking segment from ROM address 0x4010001c

 9453 23:07:12.436306  Loading segment from ROM address 0x40100000

 9454 23:07:12.439568    code (compression=1)

 9455 23:07:12.445940    New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470

 9456 23:07:12.456015  Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470

 9457 23:07:12.456098  using LZMA

 9458 23:07:12.464174  [ 0x54600000, 54614abc, 0x5462e000) <- 40100038

 9459 23:07:12.471201  Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544

 9460 23:07:12.474407  Loading segment from ROM address 0x4010001c

 9461 23:07:12.474482    Entry Point 0x54601000

 9462 23:07:12.477434  Loaded segments

 9463 23:07:12.481016  NOTICE:  MT8192 bl31_setup

 9464 23:07:12.488298  NOTICE:  BL31: v2.4(debug):v2.4-448-gce3ebc861

 9465 23:07:12.491426  NOTICE:  BL31: Built : Sat Sep 11 09:59:37 UTC 2021

 9466 23:07:12.494437  WARNING: region 0:

 9467 23:07:12.498510  WARNING: 	sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0

 9468 23:07:12.498593  WARNING: region 1:

 9469 23:07:12.504611  WARNING: 	sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d

 9470 23:07:12.504695  WARNING: region 2:

 9471 23:07:12.511573  WARNING: 	sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d

 9472 23:07:12.515054  WARNING: region 3:

 9473 23:07:12.518125  WARNING: 	sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d

 9474 23:07:12.521787  WARNING: region 4:

 9475 23:07:12.525470  WARNING: 	sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d

 9476 23:07:12.528633  WARNING: region 5:

 9477 23:07:12.531704  WARNING: 	sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0

 9478 23:07:12.535330  WARNING: region 6:

 9479 23:07:12.538248  WARNING: 	sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0

 9480 23:07:12.538331  WARNING: region 7:

 9481 23:07:12.545372  WARNING: 	sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0

 9482 23:07:12.548866  INFO:    [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000

 9483 23:07:12.555421  INFO:    [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0

 9484 23:07:12.558762  INFO:    [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff

 9485 23:07:12.561978  INFO:    [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff

 9486 23:07:12.568893  INFO:    [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff

 9487 23:07:12.572244  INFO:    [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00

 9488 23:07:12.576028  INFO:    [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff

 9489 23:07:12.582591  INFO:    [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff

 9490 23:07:12.585554  INFO:    [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff

 9491 23:07:12.592416  INFO:    [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff

 9492 23:07:12.595615  INFO:    [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff

 9493 23:07:12.599481  INFO:    [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff

 9494 23:07:12.605767  INFO:    [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff

 9495 23:07:12.609287  INFO:    [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff

 9496 23:07:12.612904  INFO:    [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff

 9497 23:07:12.619591  INFO:    [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff

 9498 23:07:12.622373  INFO:    [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff

 9499 23:07:12.625766  INFO:    [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff

 9500 23:07:12.632759  INFO:    [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff

 9501 23:07:12.636001  INFO:    [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff

 9502 23:07:12.639159  INFO:    [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff

 9503 23:07:12.645869  INFO:    [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff

 9504 23:07:12.649252  INFO:    [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff

 9505 23:07:12.656198  INFO:    [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff

 9506 23:07:12.659875  INFO:    [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff

 9507 23:07:12.663140  INFO:    [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff

 9508 23:07:12.669816  INFO:    [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff

 9509 23:07:12.673336  INFO:    [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff

 9510 23:07:12.679859  INFO:    [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff

 9511 23:07:12.683250  INFO:    [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff

 9512 23:07:12.686579  INFO:    [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff

 9513 23:07:12.693534  INFO:    [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff

 9514 23:07:12.696694  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0

 9515 23:07:12.700166  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0

 9516 23:07:12.703014  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0

 9517 23:07:12.710312  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0

 9518 23:07:12.713189  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0

 9519 23:07:12.716605  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0

 9520 23:07:12.719710  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0

 9521 23:07:12.726387  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0

 9522 23:07:12.730353  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0

 9523 23:07:12.733681  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0

 9524 23:07:12.736640  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0

 9525 23:07:12.743473  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0

 9526 23:07:12.746887  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0

 9527 23:07:12.749898  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0

 9528 23:07:12.753216  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0

 9529 23:07:12.760130  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0

 9530 23:07:12.763591  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff

 9531 23:07:12.767076  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff

 9532 23:07:12.773573  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff

 9533 23:07:12.777010  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff

 9534 23:07:12.783444  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff

 9535 23:07:12.786872  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff

 9536 23:07:12.790172  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff

 9537 23:07:12.797603  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff

 9538 23:07:12.800420  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff

 9539 23:07:12.807284  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff

 9540 23:07:12.810731  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff

 9541 23:07:12.817507  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff

 9542 23:07:12.820970  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff

 9543 23:07:12.823895  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff

 9544 23:07:12.830884  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff

 9545 23:07:12.834293  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff

 9546 23:07:12.840644  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff

 9547 23:07:12.844174  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff

 9548 23:07:12.850440  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff

 9549 23:07:12.854145  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff

 9550 23:07:12.857670  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff

 9551 23:07:12.864051  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff

 9552 23:07:12.867953  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff

 9553 23:07:12.874342  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff

 9554 23:07:12.877409  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff

 9555 23:07:12.880900  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff

 9556 23:07:12.887523  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff

 9557 23:07:12.891505  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff

 9558 23:07:12.898041  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff

 9559 23:07:12.901145  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff

 9560 23:07:12.907888  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff

 9561 23:07:12.911378  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff

 9562 23:07:12.914854  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff

 9563 23:07:12.921515  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff

 9564 23:07:12.924688  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff

 9565 23:07:12.931813  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff

 9566 23:07:12.934771  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff

 9567 23:07:12.941568  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff

 9568 23:07:12.945039  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff

 9569 23:07:12.948023  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff

 9570 23:07:12.955136  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff

 9571 23:07:12.958101  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff

 9572 23:07:12.964702  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff

 9573 23:07:12.968404  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff

 9574 23:07:12.971482  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff

 9575 23:07:12.978384  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff

 9576 23:07:12.981742  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff

 9577 23:07:12.988486  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff

 9578 23:07:12.991926  INFO:    [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0

 9579 23:07:12.995022  INFO:    [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0

 9580 23:07:13.001665  INFO:    [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0

 9581 23:07:13.005489  INFO:    [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0

 9582 23:07:13.008405  INFO:    [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0

 9583 23:07:13.011701  INFO:    [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff

 9584 23:07:13.018472  INFO:    [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff

 9585 23:07:13.022159  INFO:    [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff

 9586 23:07:13.029194  INFO:    [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff

 9587 23:07:13.032130  INFO:    [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff

 9588 23:07:13.035362  INFO:    [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff

 9589 23:07:13.042061  INFO:    [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff

 9590 23:07:13.045191  INFO:    [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff

 9591 23:07:13.052505  INFO:    [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff

 9592 23:07:13.055364  INFO:    [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff

 9593 23:07:13.058927  INFO:    [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff

 9594 23:07:13.065443  INFO:    [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff

 9595 23:07:13.068899  INFO:    [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff

 9596 23:07:13.075531  INFO:    [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff

 9597 23:07:13.079241  INFO:    [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff

 9598 23:07:13.082462  INFO:    [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18

 9599 23:07:13.085757  INFO:    [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000

 9600 23:07:13.092939  INFO:    [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004

 9601 23:07:13.096027  INFO:    [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0

 9602 23:07:13.099289  INFO:    [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0

 9603 23:07:13.102333  INFO:    [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0

 9604 23:07:13.109217  INFO:    [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0

 9605 23:07:13.112246  INFO:    [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000

 9606 23:07:13.116061  INFO:    [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff

 9607 23:07:13.122791  INFO:    [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff

 9608 23:07:13.126281  INFO:    [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff

 9609 23:07:13.129659  INFO:    [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff

 9610 23:07:13.136024  INFO:    [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff

 9611 23:07:13.139439  INFO:    [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff

 9612 23:07:13.142782  INFO:    [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff

 9613 23:07:13.149652  INFO:    [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc

 9614 23:07:13.153343  INFO:    [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff

 9615 23:07:13.159400  INFO:    [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf

 9616 23:07:13.163393  INFO:    [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff

 9617 23:07:13.166233  INFO:    [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc

 9618 23:07:13.172914  INFO:    [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff

 9619 23:07:13.176135  INFO:    [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff

 9620 23:07:13.180071  INFO:    [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff

 9621 23:07:13.186212  INFO:    [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff

 9622 23:07:13.189566  INFO:    [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff

 9623 23:07:13.196675  INFO:    [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff

 9624 23:07:13.199763  INFO:    [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff

 9625 23:07:13.203380  INFO:    [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff

 9626 23:07:13.210127  INFO:    [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff

 9627 23:07:13.213581  INFO:    [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff

 9628 23:07:13.216949  INFO:    [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff

 9629 23:07:13.223209  INFO:    [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff

 9630 23:07:13.226877  INFO:    [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff

 9631 23:07:13.233413  INFO:    [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff

 9632 23:07:13.236970  INFO:    [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff

 9633 23:07:13.240157  INFO:    [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff

 9634 23:07:13.247245  INFO:    [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff

 9635 23:07:13.250749  INFO:    [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff

 9636 23:07:13.253676  INFO:    [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff

 9637 23:07:13.260736  INFO:    [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff

 9638 23:07:13.263599  INFO:    [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff

 9639 23:07:13.270502  INFO:    [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff

 9640 23:07:13.273836  INFO:    [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff

 9641 23:07:13.277415  INFO:    [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff

 9642 23:07:13.284286  INFO:    [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff

 9643 23:07:13.287112  INFO:    [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff

 9644 23:07:13.290317  INFO:    [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff

 9645 23:07:13.296916  INFO:    [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff

 9646 23:07:13.300525  INFO:    [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff

 9647 23:07:13.307028  INFO:    [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff

 9648 23:07:13.310622  INFO:    [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff

 9649 23:07:13.313652  INFO:    [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff

 9650 23:07:13.320264  INFO:    [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff

 9651 23:07:13.324375  INFO:    [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff

 9652 23:07:13.330732  INFO:    [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff

 9653 23:07:13.333865  INFO:    [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff

 9654 23:07:13.336903  INFO:    [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff

 9655 23:07:13.344110  INFO:    [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff

 9656 23:07:13.347529  INFO:    [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff

 9657 23:07:13.350999  INFO:    [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff

 9658 23:07:13.357657  INFO:    [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff

 9659 23:07:13.360933  INFO:    [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff

 9660 23:07:13.367171  INFO:    [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff

 9661 23:07:13.371141  INFO:    [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff

 9662 23:07:13.374104  INFO:    [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff

 9663 23:07:13.380763  INFO:    [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff

 9664 23:07:13.383707  INFO:    [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff

 9665 23:07:13.390687  INFO:    [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff

 9666 23:07:13.394088  INFO:    [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff

 9667 23:07:13.397075  INFO:    [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff

 9668 23:07:13.403898  INFO:    [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff

 9669 23:07:13.407752  INFO:    [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff

 9670 23:07:13.411042  INFO:    [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff

 9671 23:07:13.417240  INFO:    [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff

 9672 23:07:13.420595  INFO:    [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff

 9673 23:07:13.427539  INFO:    [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff

 9674 23:07:13.430753  INFO:    [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff

 9675 23:07:13.434118  INFO:    [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff

 9676 23:07:13.440605  INFO:    [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff

 9677 23:07:13.443980  INFO:    [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff

 9678 23:07:13.450964  INFO:    [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff

 9679 23:07:13.453696  INFO:    [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff

 9680 23:07:13.460859  INFO:    [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff

 9681 23:07:13.464146  INFO:    [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff

 9682 23:07:13.467553  INFO:    [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff

 9683 23:07:13.474174  INFO:    [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff

 9684 23:07:13.477822  INFO:    [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff

 9685 23:07:13.484085  INFO:    [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff

 9686 23:07:13.487311  INFO:    [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff

 9687 23:07:13.491140  INFO:    [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff

 9688 23:07:13.497422  INFO:    [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff

 9689 23:07:13.500921  INFO:    [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff

 9690 23:07:13.507379  INFO:    [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff

 9691 23:07:13.511290  INFO:    [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff

 9692 23:07:13.514465  INFO:    [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff

 9693 23:07:13.520622  INFO:    [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff

 9694 23:07:13.524572  INFO:    [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff

 9695 23:07:13.531043  INFO:    [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff

 9696 23:07:13.534622  INFO:    [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff

 9697 23:07:13.537638  INFO:    [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff

 9698 23:07:13.544372  INFO:    [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff

 9699 23:07:13.547719  INFO:    [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff

 9700 23:07:13.554298  INFO:    [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff

 9701 23:07:13.557551  INFO:    [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff

 9702 23:07:13.564051  INFO:    [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff

 9703 23:07:13.567271  INFO:    [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff

 9704 23:07:13.571047  INFO:    [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff

 9705 23:07:13.577502  INFO:    [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff

 9706 23:07:13.581447  INFO:    [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff

 9707 23:07:13.587274  INFO:    [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff

 9708 23:07:13.591075  INFO:    [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff

 9709 23:07:13.594310  INFO:    [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff

 9710 23:07:13.600839  INFO:    [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff

 9711 23:07:13.604311  INFO:    [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0

 9712 23:07:13.608243  INFO:    [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0

 9713 23:07:13.610804  INFO:    [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0

 9714 23:07:13.618000  INFO:    [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0

 9715 23:07:13.621005  INFO:    [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0

 9716 23:07:13.624501  INFO:    [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff

 9717 23:07:13.631554  INFO:    [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff

 9718 23:07:13.634682  INFO:    [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff

 9719 23:07:13.638472  INFO:    [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff

 9720 23:07:13.644588  INFO:    [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf

 9721 23:07:13.647544  INFO:    [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff

 9722 23:07:13.651338  INFO:    [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff

 9723 23:07:13.658210  INFO:    [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff

 9724 23:07:13.660981  INFO:    [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff

 9725 23:07:13.664792  INFO:    [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf

 9726 23:07:13.671069  INFO:    [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff

 9727 23:07:13.674106  INFO:    [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff

 9728 23:07:13.681169  INFO:    [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff

 9729 23:07:13.684022  INFO:    [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff

 9730 23:07:13.687744  INFO:    [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf

 9731 23:07:13.694023  INFO:    [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff

 9732 23:07:13.697411  INFO:    [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff

 9733 23:07:13.700788  INFO:    [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff

 9734 23:07:13.707669  INFO:    [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff

 9735 23:07:13.711055  INFO:    [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf

 9736 23:07:13.714082  INFO:    [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff

 9737 23:07:13.720836  INFO:    [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff

 9738 23:07:13.724139  INFO:    [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff

 9739 23:07:13.730809  INFO:    [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff

 9740 23:07:13.734164  INFO:    [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf

 9741 23:07:13.737497  INFO:    [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff

 9742 23:07:13.744436  INFO:    [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff

 9743 23:07:13.748074  INFO:    [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff

 9744 23:07:13.751099  INFO:    [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff

 9745 23:07:13.757552  INFO:    [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf

 9746 23:07:13.761465  INFO:    [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff

 9747 23:07:13.764381  INFO:    [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff

 9748 23:07:13.770736  INFO:    [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff

 9749 23:07:13.774291  INFO:    [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff

 9750 23:07:13.777581  INFO:    [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf

 9751 23:07:13.784316  INFO:    [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0

 9752 23:07:13.787387  INFO:    [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3

 9753 23:07:13.791026  INFO:    [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3

 9754 23:07:13.794603  INFO:    [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3

 9755 23:07:13.797485  INFO:    [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0

 9756 23:07:13.804661  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400

 9757 23:07:13.807789  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0

 9758 23:07:13.811082  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0

 9759 23:07:13.814545  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0

 9760 23:07:13.821385  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0

 9761 23:07:13.824206  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0

 9762 23:07:13.827679  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000

 9763 23:07:13.834355  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0

 9764 23:07:13.837998  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff

 9765 23:07:13.841312  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff

 9766 23:07:13.847998  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff

 9767 23:07:13.851632  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff

 9768 23:07:13.858051  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff

 9769 23:07:13.861038  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff

 9770 23:07:13.864735  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff

 9771 23:07:13.871423  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f

 9772 23:07:13.874555  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3

 9773 23:07:13.881058  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff

 9774 23:07:13.884447  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff

 9775 23:07:13.887642  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff

 9776 23:07:13.894706  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff

 9777 23:07:13.897924  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff

 9778 23:07:13.904403  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff

 9779 23:07:13.907953  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f

 9780 23:07:13.911269  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff

 9781 23:07:13.917555  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff

 9782 23:07:13.921336  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff

 9783 23:07:13.927912  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff

 9784 23:07:13.931391  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff

 9785 23:07:13.934523  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff

 9786 23:07:13.941180  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff

 9787 23:07:13.944294  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f

 9788 23:07:13.951105  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff

 9789 23:07:13.954650  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff

 9790 23:07:13.958266  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff

 9791 23:07:13.964837  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff

 9792 23:07:13.967660  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff

 9793 23:07:13.974957  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff

 9794 23:07:13.977718  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff

 9795 23:07:13.981070  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f

 9796 23:07:13.987841  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff

 9797 23:07:13.991866  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff

 9798 23:07:13.998255  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff

 9799 23:07:14.001227  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff

 9800 23:07:14.004736  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff

 9801 23:07:14.011602  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff

 9802 23:07:14.014531  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff

 9803 23:07:14.021342  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f

 9804 23:07:14.024304  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff

 9805 23:07:14.027492  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff

 9806 23:07:14.034627  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff

 9807 23:07:14.038040  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff

 9808 23:07:14.044792  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff

 9809 23:07:14.048214  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff

 9810 23:07:14.054891  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff

 9811 23:07:14.057633  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f

 9812 23:07:14.061546  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff

 9813 23:07:14.067768  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff

 9814 23:07:14.071102  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff

 9815 23:07:14.075202  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff

 9816 23:07:14.081363  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff

 9817 23:07:14.084951  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff

 9818 23:07:14.091732  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff

 9819 23:07:14.094930  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f

 9820 23:07:14.098599  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff

 9821 23:07:14.104870  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff

 9822 23:07:14.108013  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff

 9823 23:07:14.115096  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff

 9824 23:07:14.117990  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff

 9825 23:07:14.124619  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff

 9826 23:07:14.128573  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff

 9827 23:07:14.131567  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f

 9828 23:07:14.138191  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff

 9829 23:07:14.141053  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff

 9830 23:07:14.144726  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff

 9831 23:07:14.151354  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff

 9832 23:07:14.154841  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff

 9833 23:07:14.161348  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff

 9834 23:07:14.164598  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff

 9835 23:07:14.167874  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f

 9836 23:07:14.174640  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff

 9837 23:07:14.177816  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff

 9838 23:07:14.184713  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff

 9839 23:07:14.188090  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff

 9840 23:07:14.195023  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff

 9841 23:07:14.198135  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff

 9842 23:07:14.204672  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff

 9843 23:07:14.207868  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f

 9844 23:07:14.211283  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff

 9845 23:07:14.218058  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff

 9846 23:07:14.221607  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff

 9847 23:07:14.227823  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff

 9848 23:07:14.231615  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff

 9849 23:07:14.238227  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff

 9850 23:07:14.241257  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff

 9851 23:07:14.244711  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f

 9852 23:07:14.251369  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff

 9853 23:07:14.254608  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff

 9854 23:07:14.261715  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff

 9855 23:07:14.264469  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff

 9856 23:07:14.271149  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff

 9857 23:07:14.275423  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff

 9858 23:07:14.277853  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff

 9859 23:07:14.284837  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f

 9860 23:07:14.288033  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff

 9861 23:07:14.295329  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff

 9862 23:07:14.298116  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff

 9863 23:07:14.301359  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff

 9864 23:07:14.307781  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff

 9865 23:07:14.311543  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff

 9866 23:07:14.318161  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff

 9867 23:07:14.322072  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f

 9868 23:07:14.328125  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff

 9869 23:07:14.331659  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff

 9870 23:07:14.334785  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff

 9871 23:07:14.341523  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff

 9872 23:07:14.344682  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff

 9873 23:07:14.351240  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff

 9874 23:07:14.355367  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff

 9875 23:07:14.358190  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f

 9876 23:07:14.364918  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff

 9877 23:07:14.368556  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff

 9878 23:07:14.375125  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff

 9879 23:07:14.379005  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff

 9880 23:07:14.384846  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff

 9881 23:07:14.388456  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff

 9882 23:07:14.394878  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff

 9883 23:07:14.398558  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f

 9884 23:07:14.401779  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0

 9885 23:07:14.408213  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000

 9886 23:07:14.411759  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff

 9887 23:07:14.418265  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff

 9888 23:07:14.421621  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3

 9889 23:07:14.428086  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff

 9890 23:07:14.431882  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff

 9891 23:07:14.435642  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff

 9892 23:07:14.441998  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff

 9893 23:07:14.445330  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff

 9894 23:07:14.451807  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff

 9895 23:07:14.455449  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff

 9896 23:07:14.461773  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff

 9897 23:07:14.465190  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff

 9898 23:07:14.471442  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff

 9899 23:07:14.475107  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff

 9900 23:07:14.481750  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff

 9901 23:07:14.484884  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff

 9902 23:07:14.491934  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff

 9903 23:07:14.495013  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff

 9904 23:07:14.502053  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff

 9905 23:07:14.505079  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff

 9906 23:07:14.512320  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff

 9907 23:07:14.514891  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff

 9908 23:07:14.522224  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff

 9909 23:07:14.525842  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff

 9910 23:07:14.532273  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff

 9911 23:07:14.535116  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff

 9912 23:07:14.541766  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff

 9913 23:07:14.545179  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff

 9914 23:07:14.551475  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff

 9915 23:07:14.554903  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff

 9916 23:07:14.558322  INFO:    [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0

 9917 23:07:14.561493  INFO:    [APUAPC] vio 0

 9918 23:07:14.564738  INFO:    [APUAPC] set_apusys_ao_apc - SUCCESS!

 9919 23:07:14.571947  INFO:    [APUAPC] set_apusys_noc_dapc - SUCCESS!

 9920 23:07:14.575587  INFO:    [APUAPC] D0_APC_0: 0x400510

 9921 23:07:14.579095  INFO:    [APUAPC] D0_APC_1: 0x0

 9922 23:07:14.581954  INFO:    [APUAPC] D0_APC_2: 0x1540

 9923 23:07:14.582030  INFO:    [APUAPC] D0_APC_3: 0x0

 9924 23:07:14.588298  INFO:    [APUAPC] D1_APC_0: 0xffffffff

 9925 23:07:14.591816  INFO:    [APUAPC] D1_APC_1: 0xffffffff

 9926 23:07:14.596219  INFO:    [APUAPC] D1_APC_2: 0x3fffff

 9927 23:07:14.596295  INFO:    [APUAPC] D1_APC_3: 0x0

 9928 23:07:14.598349  INFO:    [APUAPC] D2_APC_0: 0xffffffff

 9929 23:07:14.601834  INFO:    [APUAPC] D2_APC_1: 0xffffffff

 9930 23:07:14.605061  INFO:    [APUAPC] D2_APC_2: 0x3fffff

 9931 23:07:14.608444  INFO:    [APUAPC] D2_APC_3: 0x0

 9932 23:07:14.612120  INFO:    [APUAPC] D3_APC_0: 0xffffffff

 9933 23:07:14.614953  INFO:    [APUAPC] D3_APC_1: 0xffffffff

 9934 23:07:14.618520  INFO:    [APUAPC] D3_APC_2: 0x3fffff

 9935 23:07:14.621578  INFO:    [APUAPC] D3_APC_3: 0x0

 9936 23:07:14.624891  INFO:    [APUAPC] D4_APC_0: 0xffffffff

 9937 23:07:14.628890  INFO:    [APUAPC] D4_APC_1: 0xffffffff

 9938 23:07:14.631479  INFO:    [APUAPC] D4_APC_2: 0x3fffff

 9939 23:07:14.634824  INFO:    [APUAPC] D4_APC_3: 0x0

 9940 23:07:14.638312  INFO:    [APUAPC] D5_APC_0: 0xffffffff

 9941 23:07:14.642246  INFO:    [APUAPC] D5_APC_1: 0xffffffff

 9942 23:07:14.644944  INFO:    [APUAPC] D5_APC_2: 0x3fffff

 9943 23:07:14.648823  INFO:    [APUAPC] D5_APC_3: 0x0

 9944 23:07:14.651835  INFO:    [APUAPC] D6_APC_0: 0xffffffff

 9945 23:07:14.654747  INFO:    [APUAPC] D6_APC_1: 0xffffffff

 9946 23:07:14.658592  INFO:    [APUAPC] D6_APC_2: 0x3fffff

 9947 23:07:14.661621  INFO:    [APUAPC] D6_APC_3: 0x0

 9948 23:07:14.664958  INFO:    [APUAPC] D7_APC_0: 0xffffffff

 9949 23:07:14.668325  INFO:    [APUAPC] D7_APC_1: 0xffffffff

 9950 23:07:14.671559  INFO:    [APUAPC] D7_APC_2: 0x3fffff

 9951 23:07:14.675095  INFO:    [APUAPC] D7_APC_3: 0x0

 9952 23:07:14.678039  INFO:    [APUAPC] D8_APC_0: 0xffffffff

 9953 23:07:14.681749  INFO:    [APUAPC] D8_APC_1: 0xffffffff

 9954 23:07:14.685101  INFO:    [APUAPC] D8_APC_2: 0x3fffff

 9955 23:07:14.688125  INFO:    [APUAPC] D8_APC_3: 0x0

 9956 23:07:14.691848  INFO:    [APUAPC] D9_APC_0: 0xffffffff

 9957 23:07:14.694703  INFO:    [APUAPC] D9_APC_1: 0xffffffff

 9958 23:07:14.698220  INFO:    [APUAPC] D9_APC_2: 0x3fffff

 9959 23:07:14.701379  INFO:    [APUAPC] D9_APC_3: 0x0

 9960 23:07:14.704668  INFO:    [APUAPC] D10_APC_0: 0xffffffff

 9961 23:07:14.708470  INFO:    [APUAPC] D10_APC_1: 0xffffffff

 9962 23:07:14.711458  INFO:    [APUAPC] D10_APC_2: 0x3fffff

 9963 23:07:14.715534  INFO:    [APUAPC] D10_APC_3: 0x0

 9964 23:07:14.718009  INFO:    [APUAPC] D11_APC_0: 0xffffffff

 9965 23:07:14.721661  INFO:    [APUAPC] D11_APC_1: 0xffffffff

 9966 23:07:14.725609  INFO:    [APUAPC] D11_APC_2: 0x3fffff

 9967 23:07:14.728562  INFO:    [APUAPC] D11_APC_3: 0x0

 9968 23:07:14.731385  INFO:    [APUAPC] D12_APC_0: 0xffffffff

 9969 23:07:14.734824  INFO:    [APUAPC] D12_APC_1: 0xffffffff

 9970 23:07:14.738515  INFO:    [APUAPC] D12_APC_2: 0x3fffff

 9971 23:07:14.741632  INFO:    [APUAPC] D12_APC_3: 0x0

 9972 23:07:14.745035  INFO:    [APUAPC] D13_APC_0: 0xffffffff

 9973 23:07:14.748115  INFO:    [APUAPC] D13_APC_1: 0xffffffff

 9974 23:07:14.751797  INFO:    [APUAPC] D13_APC_2: 0x3fffff

 9975 23:07:14.754973  INFO:    [APUAPC] D13_APC_3: 0x0

 9976 23:07:14.758541  INFO:    [APUAPC] D14_APC_0: 0xffffffff

 9977 23:07:14.762049  INFO:    [APUAPC] D14_APC_1: 0xffffffff

 9978 23:07:14.765490  INFO:    [APUAPC] D14_APC_2: 0x3fffff

 9979 23:07:14.768355  INFO:    [APUAPC] D14_APC_3: 0x0

 9980 23:07:14.771851  INFO:    [APUAPC] D15_APC_0: 0xffffffff

 9981 23:07:14.774862  INFO:    [APUAPC] D15_APC_1: 0xffffffff

 9982 23:07:14.778319  INFO:    [APUAPC] D15_APC_2: 0x3fffff

 9983 23:07:14.781617  INFO:    [APUAPC] D15_APC_3: 0x0

 9984 23:07:14.781691  INFO:    [APUAPC] APC_CON: 0x4

 9985 23:07:14.784978  INFO:    [NOCDAPC] D0_APC_0: 0x0

 9986 23:07:14.788900  INFO:    [NOCDAPC] D0_APC_1: 0x0

 9987 23:07:14.791921  INFO:    [NOCDAPC] D1_APC_0: 0x0

 9988 23:07:14.794704  INFO:    [NOCDAPC] D1_APC_1: 0xfff

 9989 23:07:14.798574  INFO:    [NOCDAPC] D2_APC_0: 0x0

 9990 23:07:14.802010  INFO:    [NOCDAPC] D2_APC_1: 0xfff

 9991 23:07:14.805118  INFO:    [NOCDAPC] D3_APC_0: 0x0

 9992 23:07:14.808909  INFO:    [NOCDAPC] D3_APC_1: 0xfff

 9993 23:07:14.812221  INFO:    [NOCDAPC] D4_APC_0: 0x0

 9994 23:07:14.812297  INFO:    [NOCDAPC] D4_APC_1: 0xfff

 9995 23:07:14.815305  INFO:    [NOCDAPC] D5_APC_0: 0x0

 9996 23:07:14.818225  INFO:    [NOCDAPC] D5_APC_1: 0xfff

 9997 23:07:14.821819  INFO:    [NOCDAPC] D6_APC_0: 0x0

 9998 23:07:14.825465  INFO:    [NOCDAPC] D6_APC_1: 0xfff

 9999 23:07:14.828885  INFO:    [NOCDAPC] D7_APC_0: 0x0

10000 23:07:14.831873  INFO:    [NOCDAPC] D7_APC_1: 0xfff

10001 23:07:14.835585  INFO:    [NOCDAPC] D8_APC_0: 0x0

10002 23:07:14.838937  INFO:    [NOCDAPC] D8_APC_1: 0xfff

10003 23:07:14.842161  INFO:    [NOCDAPC] D9_APC_0: 0x0

10004 23:07:14.845166  INFO:    [NOCDAPC] D9_APC_1: 0xfff

10005 23:07:14.845249  INFO:    [NOCDAPC] D10_APC_0: 0x0

10006 23:07:14.848673  INFO:    [NOCDAPC] D10_APC_1: 0xfff

10007 23:07:14.851487  INFO:    [NOCDAPC] D11_APC_0: 0x0

10008 23:07:14.855156  INFO:    [NOCDAPC] D11_APC_1: 0xfff

10009 23:07:14.858353  INFO:    [NOCDAPC] D12_APC_0: 0x0

10010 23:07:14.862023  INFO:    [NOCDAPC] D12_APC_1: 0xfff

10011 23:07:14.865751  INFO:    [NOCDAPC] D13_APC_0: 0x0

10012 23:07:14.868511  INFO:    [NOCDAPC] D13_APC_1: 0xfff

10013 23:07:14.871566  INFO:    [NOCDAPC] D14_APC_0: 0x0

10014 23:07:14.874993  INFO:    [NOCDAPC] D14_APC_1: 0xfff

10015 23:07:14.878343  INFO:    [NOCDAPC] D15_APC_0: 0x0

10016 23:07:14.882034  INFO:    [NOCDAPC] D15_APC_1: 0xfff

10017 23:07:14.885220  INFO:    [NOCDAPC] APC_CON: 0x4

10018 23:07:14.888366  INFO:    [APUAPC] set_apusys_apc done

10019 23:07:14.888442  INFO:    [DEVAPC] devapc_init done

10020 23:07:14.895320  INFO:    GICv3 without legacy support detected.

10021 23:07:14.898327  INFO:    ARM GICv3 driver initialized in EL3

10022 23:07:14.901514  INFO:    Maximum SPI INTID supported: 639

10023 23:07:14.905321  INFO:    BL31: Initializing runtime services

10024 23:07:14.912016  WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!

10025 23:07:14.915334  INFO:    SPM: enable CPC mode

10026 23:07:14.918529  INFO:    mcdi ready for mcusys-off-idle and system suspend

10027 23:07:14.924694  INFO:    BL31: Preparing for EL3 exit to normal world

10028 23:07:14.928549  INFO:    Entry point address = 0x80000000

10029 23:07:14.928628  INFO:    SPSR = 0x8

10030 23:07:14.935812  

10031 23:07:14.935889  

10032 23:07:14.935960  

10033 23:07:14.936651  end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10034 23:07:14.936759  start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10035 23:07:14.936842  Setting prompt string to ['asurada:']
10036 23:07:14.936918  bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10037 23:07:14.938810  Starting depthcharge on Spherion...

10038 23:07:14.938888  

10039 23:07:14.938951  Wipe memory regions:

10040 23:07:14.939017  

10041 23:07:14.942283  	[0x00000040000000, 0x00000054600000)

10042 23:07:15.064403  

10043 23:07:15.064532  	[0x00000054660000, 0x00000080000000)

10044 23:07:15.325198  

10045 23:07:15.325329  	[0x000000821a7280, 0x000000ffe64000)

10046 23:07:16.069853  

10047 23:07:16.069989  	[0x00000100000000, 0x00000240000000)

10048 23:07:17.960325  

10049 23:07:17.963746  Initializing XHCI USB controller at 0x11200000.

10050 23:07:19.002670  

10051 23:07:19.005591  [firmware-asurada-13885.B-collabora] Dec  7 2021 09:38:38

10052 23:07:19.005680  

10053 23:07:19.005752  

10054 23:07:19.005813  

10055 23:07:19.006092  Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10057 23:07:19.106385  asurada: tftpboot 192.168.201.1 12395354/tftp-deploy-z6ayw89f/kernel/image.itb 12395354/tftp-deploy-z6ayw89f/kernel/cmdline 

10058 23:07:19.106565  Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10059 23:07:19.106679  bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10060 23:07:19.111311  tftpboot 192.168.201.1 12395354/tftp-deploy-z6ayw89f/kernel/image.itp-deploy-z6ayw89f/kernel/cmdline 

10061 23:07:19.111396  

10062 23:07:19.111470  Waiting for link

10063 23:07:19.271487  

10064 23:07:19.271617  R8152: Initializing

10065 23:07:19.271687  

10066 23:07:19.274537  Version 6 (ocp_data = 5c30)

10067 23:07:19.274613  

10068 23:07:19.277929  R8152: Done initializing

10069 23:07:19.277999  

10070 23:07:19.278060  Adding net device

10071 23:07:21.180931  

10072 23:07:21.181065  done.

10073 23:07:21.181138  

10074 23:07:21.181208  MAC: 00:24:32:30:78:52

10075 23:07:21.181268  

10076 23:07:21.184289  Sending DHCP discover... done.

10077 23:07:21.184370  

10078 23:07:21.187447  Waiting for reply... done.

10079 23:07:21.187531  

10080 23:07:21.191200  Sending DHCP request... done.

10081 23:07:21.191279  

10082 23:07:21.196086  Waiting for reply... done.

10083 23:07:21.196168  

10084 23:07:21.196231  My ip is 192.168.201.14

10085 23:07:21.196291  

10086 23:07:21.199262  The DHCP server ip is 192.168.201.1

10087 23:07:21.199335  

10088 23:07:21.205727  TFTP server IP predefined by user: 192.168.201.1

10089 23:07:21.205809  

10090 23:07:21.212838  Bootfile predefined by user: 12395354/tftp-deploy-z6ayw89f/kernel/image.itb

10091 23:07:21.212928  

10092 23:07:21.212996  Sending tftp read request... done.

10093 23:07:21.213058  

10094 23:07:21.219565  Waiting for the transfer... 

10095 23:07:21.219648  

10096 23:07:21.735913  00000000 ################################################################

10097 23:07:21.736049  

10098 23:07:22.273263  00080000 ################################################################

10099 23:07:22.273403  

10100 23:07:22.800994  00100000 ################################################################

10101 23:07:22.801129  

10102 23:07:23.326547  00180000 ################################################################

10103 23:07:23.326690  

10104 23:07:23.846240  00200000 ################################################################

10105 23:07:23.846421  

10106 23:07:24.379985  00280000 ################################################################

10107 23:07:24.380130  

10108 23:07:24.919127  00300000 ################################################################

10109 23:07:24.919277  

10110 23:07:25.449328  00380000 ################################################################

10111 23:07:25.449498  

10112 23:07:25.968927  00400000 ################################################################

10113 23:07:25.969098  

10114 23:07:26.498319  00480000 ################################################################

10115 23:07:26.498490  

10116 23:07:27.038148  00500000 ################################################################

10117 23:07:27.038305  

10118 23:07:27.582099  00580000 ################################################################

10119 23:07:27.582235  

10120 23:07:28.161375  00600000 ################################################################

10121 23:07:28.161516  

10122 23:07:28.743242  00680000 ################################################################

10123 23:07:28.743774  

10124 23:07:29.448242  00700000 ################################################################

10125 23:07:29.448380  

10126 23:07:30.028589  00780000 ################################################################

10127 23:07:30.028728  

10128 23:07:30.647927  00800000 ################################################################

10129 23:07:30.648455  

10130 23:07:31.255849  00880000 ################################################################

10131 23:07:31.256343  

10132 23:07:31.870870  00900000 ################################################################

10133 23:07:31.871389  

10134 23:07:32.576853  00980000 ################################################################

10135 23:07:32.577405  

10136 23:07:33.294315  00a00000 ################################################################

10137 23:07:33.294859  

10138 23:07:33.963420  00a80000 ################################################################

10139 23:07:33.963937  

10140 23:07:34.654683  00b00000 ################################################################

10141 23:07:34.655217  

10142 23:07:35.384618  00b80000 ################################################################

10143 23:07:35.385150  

10144 23:07:36.092848  00c00000 ################################################################

10145 23:07:36.093365  

10146 23:07:36.814081  00c80000 ################################################################

10147 23:07:36.814672  

10148 23:07:37.546861  00d00000 ################################################################

10149 23:07:37.547443  

10150 23:07:38.279854  00d80000 ################################################################

10151 23:07:38.280396  

10152 23:07:39.007173  00e00000 ################################################################

10153 23:07:39.007733  

10154 23:07:39.728472  00e80000 ################################################################

10155 23:07:39.728996  

10156 23:07:40.457708  00f00000 ################################################################

10157 23:07:40.458229  

10158 23:07:41.189463  00f80000 ################################################################

10159 23:07:41.189977  

10160 23:07:41.917374  01000000 ################################################################

10161 23:07:41.917902  

10162 23:07:42.639789  01080000 ################################################################

10163 23:07:42.640337  

10164 23:07:43.353725  01100000 ################################################################

10165 23:07:43.354259  

10166 23:07:44.072156  01180000 ################################################################

10167 23:07:44.072691  

10168 23:07:44.780847  01200000 ################################################################

10169 23:07:44.781406  

10170 23:07:45.474786  01280000 ################################################################

10171 23:07:45.474982  

10172 23:07:46.133479  01300000 ################################################################

10173 23:07:46.134059  

10174 23:07:46.845391  01380000 ################################################################

10175 23:07:46.845917  

10176 23:07:47.548156  01400000 ################################################################

10177 23:07:47.548666  

10178 23:07:48.274377  01480000 ################################################################

10179 23:07:48.274919  

10180 23:07:48.935240  01500000 ################################################################

10181 23:07:48.935771  

10182 23:07:49.611968  01580000 ################################################################

10183 23:07:49.612136  

10184 23:07:50.171132  01600000 ################################################################

10185 23:07:50.171278  

10186 23:07:50.736760  01680000 ################################################################

10187 23:07:50.736939  

10188 23:07:51.339448  01700000 ################################################################

10189 23:07:51.339582  

10190 23:07:51.901946  01780000 ################################################################

10191 23:07:51.902092  

10192 23:07:52.485957  01800000 ################################################################

10193 23:07:52.486091  

10194 23:07:53.035507  01880000 ################################################################

10195 23:07:53.035641  

10196 23:07:53.580435  01900000 ################################################################

10197 23:07:53.580593  

10198 23:07:54.138944  01980000 ################################################################

10199 23:07:54.139135  

10200 23:07:54.725324  01a00000 ################################################################

10201 23:07:54.725822  

10202 23:07:55.304045  01a80000 ################################################################

10203 23:07:55.304182  

10204 23:07:55.885015  01b00000 ################################################################

10205 23:07:55.885147  

10206 23:07:56.459483  01b80000 ################################################################

10207 23:07:56.459631  

10208 23:07:57.042915  01c00000 ################################################################

10209 23:07:57.043062  

10210 23:07:57.677404  01c80000 ################################################################

10211 23:07:57.677572  

10212 23:07:58.293755  01d00000 ################################################################

10213 23:07:58.293926  

10214 23:07:58.941546  01d80000 ################################################################

10215 23:07:58.942068  

10216 23:07:59.592213  01e00000 ################################################################

10217 23:07:59.592404  

10218 23:08:00.202776  01e80000 ################################################################

10219 23:08:00.202914  

10220 23:08:00.896927  01f00000 ################################################################

10221 23:08:00.897454  

10222 23:08:01.490793  01f80000 ################################################################

10223 23:08:01.491324  

10224 23:08:02.076814  02000000 ################################################################

10225 23:08:02.076978  

10226 23:08:02.623727  02080000 ################################################################

10227 23:08:02.623879  

10228 23:08:03.165862  02100000 ################################################################

10229 23:08:03.166012  

10230 23:08:03.727164  02180000 ################################################################

10231 23:08:03.727328  

10232 23:08:04.285297  02200000 ################################################################

10233 23:08:04.285448  

10234 23:08:04.884095  02280000 ################################################################

10235 23:08:04.884617  

10236 23:08:05.453280  02300000 ################################################################

10237 23:08:05.453467  

10238 23:08:06.011996  02380000 ################################################################

10239 23:08:06.012172  

10240 23:08:06.564696  02400000 ################################################################

10241 23:08:06.564882  

10242 23:08:07.102305  02480000 ################################################################

10243 23:08:07.102517  

10244 23:08:07.654726  02500000 ################################################################

10245 23:08:07.654890  

10246 23:08:08.232214  02580000 ################################################################

10247 23:08:08.232731  

10248 23:08:08.903338  02600000 ################################################################

10249 23:08:08.904046  

10250 23:08:09.627459  02680000 ################################################################

10251 23:08:09.628119  

10252 23:08:10.244054  02700000 ################################################################

10253 23:08:10.244203  

10254 23:08:10.868511  02780000 ################################################################

10255 23:08:10.869027  

10256 23:08:11.592548  02800000 ################################################################

10257 23:08:11.593068  

10258 23:08:12.265323  02880000 ################################################################

10259 23:08:12.265669  

10260 23:08:12.987675  02900000 ################################################################

10261 23:08:12.988185  

10262 23:08:13.685874  02980000 ################################################################

10263 23:08:13.686011  

10264 23:08:14.287087  02a00000 ################################################################

10265 23:08:14.287261  

10266 23:08:14.872123  02a80000 ################################################################

10267 23:08:14.872268  

10268 23:08:15.458359  02b00000 ################################################################

10269 23:08:15.458545  

10270 23:08:16.051227  02b80000 ################################################################

10271 23:08:16.051379  

10272 23:08:16.629034  02c00000 ################################################################

10273 23:08:16.629186  

10274 23:08:17.216394  02c80000 ################################################################

10275 23:08:17.216541  

10276 23:08:17.802344  02d00000 ################################################################

10277 23:08:17.802529  

10278 23:08:18.374178  02d80000 ################################################################

10279 23:08:18.374324  

10280 23:08:18.949201  02e00000 ################################################################

10281 23:08:18.949352  

10282 23:08:19.532070  02e80000 ################################################################

10283 23:08:19.532221  

10284 23:08:20.114616  02f00000 ################################################################

10285 23:08:20.114768  

10286 23:08:20.699261  02f80000 ################################################################

10287 23:08:20.699416  

10288 23:08:21.270804  03000000 ################################################################

10289 23:08:21.270948  

10290 23:08:21.818891  03080000 ################################################################

10291 23:08:21.819039  

10292 23:08:22.368237  03100000 ################################################################

10293 23:08:22.368375  

10294 23:08:22.958011  03180000 ################################################################

10295 23:08:22.958163  

10296 23:08:23.540589  03200000 ################################################################

10297 23:08:23.540738  

10298 23:08:24.137905  03280000 ################################################################

10299 23:08:24.138053  

10300 23:08:24.736016  03300000 ################################################################

10301 23:08:24.736166  

10302 23:08:25.334626  03380000 ################################################################

10303 23:08:25.334778  

10304 23:08:25.940769  03400000 ################################################################

10305 23:08:25.940917  

10306 23:08:26.540123  03480000 ################################################################

10307 23:08:26.540557  

10308 23:08:27.202172  03500000 ################################################################

10309 23:08:27.202319  

10310 23:08:27.803886  03580000 ################################################################

10311 23:08:27.804069  

10312 23:08:28.383726  03600000 ################################################################

10313 23:08:28.383911  

10314 23:08:28.943580  03680000 ################################################################

10315 23:08:28.943758  

10316 23:08:29.510921  03700000 ################################################################

10317 23:08:29.511073  

10318 23:08:30.092807  03780000 ################################################################

10319 23:08:30.092988  

10320 23:08:30.482684  03800000 ########################################### done.

10321 23:08:30.482866  

10322 23:08:30.486296  The bootfile was 59066650 bytes long.

10323 23:08:30.486410  

10324 23:08:30.488988  Sending tftp read request... done.

10325 23:08:30.489094  

10326 23:08:30.492281  Waiting for the transfer... 

10327 23:08:30.492392  

10328 23:08:30.495923  00000000 # done.

10329 23:08:30.496036  

10330 23:08:30.502120  Command line loaded dynamically from TFTP file: 12395354/tftp-deploy-z6ayw89f/kernel/cmdline

10331 23:08:30.502239  

10332 23:08:30.516353  The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1

10333 23:08:30.516468  

10334 23:08:30.516562  Loading FIT.

10335 23:08:30.516653  

10336 23:08:30.518944  Image ramdisk-1 has 47536951 bytes.

10337 23:08:30.519054  

10338 23:08:30.521944  Image fdt-1 has 47278 bytes.

10339 23:08:30.522053  

10340 23:08:30.525563  Image kernel-1 has 11480388 bytes.

10341 23:08:30.525671  

10342 23:08:30.535971  Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion

10343 23:08:30.536088  

10344 23:08:30.552533  Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192

10345 23:08:30.552651  

10346 23:08:30.555995  Choosing best match conf-1 for compat google,spherion-rev2.

10347 23:08:30.559488  

10348 23:08:30.563302  Connected to device vid:did:rid of 1ae0:0028:00

10349 23:08:30.573544  

10350 23:08:30.576900  tpm_get_response: command 0x17b, return code 0x0

10351 23:08:30.577010  

10352 23:08:30.579578  ec_init: CrosEC protocol v3 supported (256, 248)

10353 23:08:30.584750  

10354 23:08:30.588145  tpm_cleanup: add release locality here.

10355 23:08:30.588254  

10356 23:08:30.588349  Shutting down all USB controllers.

10357 23:08:30.590830  

10358 23:08:30.590939  Removing current net device

10359 23:08:30.591033  

10360 23:08:30.597416  Exiting depthcharge with code 4 at timestamp: 105031743

10361 23:08:30.597523  

10362 23:08:30.601482  LZMA decompressing kernel-1 to 0x821a6718

10363 23:08:30.601592  

10364 23:08:30.603995  LZMA decompressing kernel-1 to 0x40000000

10365 23:08:32.040468  

10366 23:08:32.040657  jumping to kernel

10367 23:08:32.041441  end: 2.2.4 bootloader-commands (duration 00:01:17) [common]
10368 23:08:32.041583  start: 2.2.5 auto-login-action (timeout 00:03:08) [common]
10369 23:08:32.041690  Setting prompt string to ['Linux version [0-9]']
10370 23:08:32.041789  Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10371 23:08:32.041894  auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10372 23:08:32.121570  

10373 23:08:32.124861  [    0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]

10374 23:08:32.128534  start: 2.2.5.1 login-action (timeout 00:03:08) [common]
10375 23:08:32.128658  The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10376 23:08:32.128761  Setting prompt string to []
10377 23:08:32.128869  Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10378 23:08:32.128973  Using line separator: #'\n'#
10379 23:08:32.129059  No login prompt set.
10380 23:08:32.129158  Parsing kernel messages
10381 23:08:32.129247  ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10382 23:08:32.129408  [login-action] Waiting for messages, (timeout 00:03:08)
10383 23:08:32.148430  [    0.000000] Linux version 6.1.67-cip12-rt7 (KernelCI@build-j59954-arm64-gcc-10-defconfig-arm64-chromebook-nblph) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Wed Dec 27 22:50:56 UTC 2023

10384 23:08:32.151740  [    0.000000] random: crng init done

10385 23:08:32.158259  [    0.000000] Machine model: Google Spherion (rev0 - 3)

10386 23:08:32.161734  [    0.000000] efi: UEFI not found.

10387 23:08:32.168606  [    0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB

10388 23:08:32.175238  [    0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool

10389 23:08:32.185435  [    0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB

10390 23:08:32.195554  [    0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool

10391 23:08:32.201798  [    0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')

10392 23:08:32.208304  [    0.000000] printk: bootconsole [mtk8250] enabled

10393 23:08:32.214641  [    0.000000] NUMA: No NUMA configuration found

10394 23:08:32.221324  [    0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]

10395 23:08:32.224840  [    0.000000] NUMA: NODE_DATA [mem 0x23efcfa00-0x23efd1fff]

10396 23:08:32.228342  [    0.000000] Zone ranges:

10397 23:08:32.235006  [    0.000000]   DMA      [mem 0x0000000040000000-0x00000000ffffffff]

10398 23:08:32.238290  [    0.000000]   DMA32    empty

10399 23:08:32.245202  [    0.000000]   Normal   [mem 0x0000000100000000-0x000000023fffffff]

10400 23:08:32.248273  [    0.000000] Movable zone start for each node

10401 23:08:32.251806  [    0.000000] Early memory node ranges

10402 23:08:32.258326  [    0.000000]   node   0: [mem 0x0000000040000000-0x000000004fffffff]

10403 23:08:32.265644  [    0.000000]   node   0: [mem 0x0000000050000000-0x00000000528fffff]

10404 23:08:32.268816  [    0.000000]   node   0: [mem 0x0000000052900000-0x00000000545fffff]

10405 23:08:32.275553  [    0.000000]   node   0: [mem 0x0000000054700000-0x00000000ffdfffff]

10406 23:08:32.281583  [    0.000000]   node   0: [mem 0x0000000100000000-0x000000023fffffff]

10407 23:08:32.288529  [    0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]

10408 23:08:32.347159  [    0.000000] On node 0, zone DMA: 256 pages in unavailable ranges

10409 23:08:32.353652  [    0.000000] On node 0, zone Normal: 512 pages in unavailable ranges

10410 23:08:32.360357  [    0.000000] cma: Reserved 32 MiB at 0x00000000fde00000

10411 23:08:32.363422  [    0.000000] psci: probing for conduit method from DT.

10412 23:08:32.369826  [    0.000000] psci: PSCIv1.1 detected in firmware.

10413 23:08:32.372819  [    0.000000] psci: Using standard PSCI v0.2 function IDs

10414 23:08:32.379707  [    0.000000] psci: MIGRATE_INFO_TYPE not supported.

10415 23:08:32.383200  [    0.000000] psci: SMC Calling Convention v1.2

10416 23:08:32.390096  [    0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016

10417 23:08:32.394198  [    0.000000] Detected VIPT I-cache on CPU0

10418 23:08:32.400057  [    0.000000] CPU features: detected: GIC system register CPU interface

10419 23:08:32.406424  [    0.000000] CPU features: detected: Virtualization Host Extensions

10420 23:08:32.413009  [    0.000000] CPU features: kernel page table isolation forced ON by KASLR

10421 23:08:32.419642  [    0.000000] CPU features: detected: Kernel page table isolation (KPTI)

10422 23:08:32.426596  [    0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009

10423 23:08:32.434187  [    0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923

10424 23:08:32.440039  [    0.000000] alternatives: applying boot alternatives

10425 23:08:32.442687  [    0.000000] Fallback order for Node 0: 0 

10426 23:08:32.449543  [    0.000000] Built 1 zonelists, mobility grouping on.  Total pages: 2063616

10427 23:08:32.453737  [    0.000000] Policy zone: Normal

10428 23:08:32.470064  [    0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1

10429 23:08:32.479498  <5>[    0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.

10430 23:08:32.490369  <6>[    0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)

10431 23:08:32.499868  <6>[    0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)

10432 23:08:32.506475  <6>[    0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off

10433 23:08:32.509464  <6>[    0.000000] software IO TLB: area num 8.

10434 23:08:32.566275  <6>[    0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)

10435 23:08:32.715716  <6>[    0.000000] Memory: 7922292K/8385536K available (17984K kernel code, 4116K rwdata, 18184K rodata, 8448K init, 615K bss, 430476K reserved, 32768K cma-reserved)

10436 23:08:32.722594  <6>[    0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1

10437 23:08:32.729680  <6>[    0.000000] rcu: Preemptible hierarchical RCU implementation.

10438 23:08:32.732540  <6>[    0.000000] rcu: 	RCU event tracing is enabled.

10439 23:08:32.738809  <6>[    0.000000] rcu: 	RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.

10440 23:08:32.745539  <6>[    0.000000] 	Trampoline variant of Tasks RCU enabled.

10441 23:08:32.748971  <6>[    0.000000] 	Tracing variant of Tasks RCU enabled.

10442 23:08:32.759553  <6>[    0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.

10443 23:08:32.765960  <6>[    0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8

10444 23:08:32.768779  <6>[    0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0

10445 23:08:32.776983  <6>[    0.000000] GICv3: GIC: Using split EOI/Deactivate mode

10446 23:08:32.779883  <6>[    0.000000] GICv3: 608 SPIs implemented

10447 23:08:32.786373  <6>[    0.000000] GICv3: 0 Extended SPIs implemented

10448 23:08:32.790141  <6>[    0.000000] Root IRQ handler: gic_handle_irq

10449 23:08:32.792995  <6>[    0.000000] GICv3: GICv3 features: 16 PPIs

10450 23:08:32.803065  <6>[    0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000

10451 23:08:32.813359  <6>[    0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }

10452 23:08:32.826747  <6>[    0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }

10453 23:08:32.833109  <6>[    0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.

10454 23:08:32.842123  <6>[    0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).

10455 23:08:32.855591  <6>[    0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns

10456 23:08:32.861639  <6>[    0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns

10457 23:08:32.868431  <6>[    0.009183] Console: colour dummy device 80x25

10458 23:08:32.878922  <6>[    0.013935] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)

10459 23:08:32.882077  <6>[    0.024377] pid_max: default: 32768 minimum: 301

10460 23:08:32.888262  <6>[    0.029249] LSM: Security Framework initializing

10461 23:08:32.896031  <6>[    0.034207] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)

10462 23:08:32.904939  <6>[    0.042022] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)

10463 23:08:32.911970  <6>[    0.051431] cblist_init_generic: Setting adjustable number of callback queues.

10464 23:08:32.918762  <6>[    0.058875] cblist_init_generic: Setting shift to 3 and lim to 1.

10465 23:08:32.928422  <6>[    0.065213] cblist_init_generic: Setting adjustable number of callback queues.

10466 23:08:32.931697  <6>[    0.072686] cblist_init_generic: Setting shift to 3 and lim to 1.

10467 23:08:32.938278  <6>[    0.079156] rcu: Hierarchical SRCU implementation.

10468 23:08:32.945079  <6>[    0.079158] rcu: 	Max phase no-delay instances is 1000.

10469 23:08:32.951805  <6>[    0.079182] printk: bootconsole [mtk8250] printing thread started

10470 23:08:32.958099  <6>[    0.097484] EFI services will not be available.

10471 23:08:32.961793  <6>[    0.097685] smp: Bringing up secondary CPUs ...

10472 23:08:32.965849  <6>[    0.097988] Detected VIPT I-cache on CPU1

10473 23:08:32.972448  <6>[    0.098052] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000

10474 23:08:32.978010  <6>[    0.098084] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]

10475 23:08:32.989897  <6>[    0.125915] Detected VIPT I-cache on CPU2

10476 23:08:32.997289  <6>[    0.125961] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000

10477 23:08:33.003165  <6>[    0.125975] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]

10478 23:08:33.009980  <6>[    0.126227] Detected VIPT I-cache on CPU3

10479 23:08:33.016766  <6>[    0.126273] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000

10480 23:08:33.023279  <6>[    0.126287] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]

10481 23:08:33.026374  <6>[    0.126598] CPU features: detected: Spectre-v4

10482 23:08:33.033277  <6>[    0.126604] CPU features: detected: Spectre-BHB

10483 23:08:33.036302  <6>[    0.126609] Detected PIPT I-cache on CPU4

10484 23:08:33.043393  <6>[    0.126667] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000

10485 23:08:33.050637  <6>[    0.126684] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]

10486 23:08:33.056624  <6>[    0.126981] Detected PIPT I-cache on CPU5

10487 23:08:33.063108  <6>[    0.127044] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000

10488 23:08:33.070495  <6>[    0.127061] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]

10489 23:08:33.073166  <6>[    0.127336] Detected PIPT I-cache on CPU6

10490 23:08:33.080252  <6>[    0.127402] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000

10491 23:08:33.086781  <6>[    0.127418] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]

10492 23:08:33.093248  <6>[    0.127712] Detected PIPT I-cache on CPU7

10493 23:08:33.100607  <6>[    0.127776] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000

10494 23:08:33.106691  <6>[    0.127792] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]

10495 23:08:33.110531  <6>[    0.127840] smp: Brought up 1 node, 8 CPUs

10496 23:08:33.116613  <6>[    0.127844] SMP: Total of 8 processors activated.

10497 23:08:33.119682  <6>[    0.127847] CPU features: detected: 32-bit EL0 Support

10498 23:08:33.129745  <6>[    0.127848] CPU features: detected: Data cache clean to the PoU not required for I/D coherence

10499 23:08:33.136527  <6>[    0.127851] CPU features: detected: Common not Private translations

10500 23:08:33.140191  <6>[    0.127852] CPU features: detected: CRC32 instructions

10501 23:08:33.146891  <6>[    0.127855] CPU features: detected: RCpc load-acquire (LDAPR)

10502 23:08:33.153990  <6>[    0.127856] CPU features: detected: LSE atomic instructions

10503 23:08:33.160858  <6>[    0.127858] CPU features: detected: Privileged Access Never

10504 23:08:33.163443  <6>[    0.127859] CPU features: detected: RAS Extension Support

10505 23:08:33.173512  <6>[    0.127862] CPU features: detected: Speculative Store Bypassing Safe (SSBS)

10506 23:08:33.176290  <6>[    0.127926] CPU: All CPU(s) started at EL2

10507 23:08:33.183199  <6>[    0.127928] alternatives: applying system-wide alternatives

10508 23:08:33.186209  <6>[    0.141070] devtmpfs: initialized

10509 23:08:33.196235  <6>[    0.147268] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns

10510 23:08:53.713392  ��������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������������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   4.358804] igb: Intel(R) Gigabit Ethernet Network Driver

10511 23:08:53.716071  <6>[    4.358806] igb: Copyright (c) 2007-2014 Intel Corporation.

10512 23:08:53.722236  <6>[    4.358820] igbvf: Intel(R) Gigabit Virtual Function Network Driver

10513 23:08:53.729441  <6>[    4.358822] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.

10514 23:08:53.733018  <6>[    4.359108] sky2: driver version 1.30

10515 23:08:53.739278  <6>[    4.360166] VFIO - User Level meta-driver version: 0.3

10516 23:08:53.745869  <6>[    4.362963] usbcore: registered new interface driver usb-storage

10517 23:08:53.751885  <6>[    4.363140] usbcore: registered new device driver onboard-usb-hub

10518 23:08:53.755496  <6>[    4.365876] mt6397-rtc mt6359-rtc: registered as rtc0

10519 23:08:53.765478  <6>[    4.366026] mt6397-rtc mt6359-rtc: setting system clock to 2023-12-27T23:09:16 UTC (1703718556)

10520 23:08:53.772264  <6>[    4.366637] i2c_dev: i2c /dev entries driver

10521 23:08:53.781953  <6>[    4.373628] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)

10522 23:08:53.785652  <6>[    4.389626] cpu cpu0: EM: created perf domain

10523 23:08:53.792448  <6>[    4.389954] cpu cpu4: EM: created perf domain

10524 23:08:53.795387  <6>[    4.876637] sdhci: Secure Digital Host Controller Interface driver

10525 23:08:53.801886  <6>[    4.876639] sdhci: Copyright(c) Pierre Ossman

10526 23:08:53.808571  <6>[    4.876990] Synopsys Designware Multimedia Card Interface Driver

10527 23:08:53.815609  <6>[    4.877396] sdhci-pltfm: SDHCI platform and OF driver helper

10528 23:08:53.818292  <6>[    5.277527] ledtrig-cpu: registered to indicate activity on CPUs

10529 23:08:53.821685  

10530 23:08:53.825787  Welcome to [1<6>[    5.278092] mmc0: CQHCI version 5.10

10531 23:08:53.832577  <6>[    5.278462] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000

10532 23:08:53.838724  <6>[    5.278984] usbcore: registered new interface driver usbhid

10533 23:08:53.842283  <6>[    5.278987] usbhid: USB HID core driver

10534 23:08:53.848874  <6>[    5.279153] spi_master spi0: will run message pump with realtime priority

10535 23:08:53.855437  <6>[    5.642056] mmc0: Command Queue Engine enabled

10536 23:08:53.862096  <6>[    5.642066] mmc0: new HS400 Enhanced strobe MMC card at address 0001

10537 23:08:53.865196  <6>[    5.642498] mmcblk0: mmc0:0001 DA4128 116 GiB 

10538 23:08:53.872390  <6>[    5.645677]  mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12

10539 23:08:53.874972  <6>[    5.647806] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB 

10540 23:08:53.881587  <6>[    5.648547] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB 

10541 23:08:53.888150  <6>[    5.649192] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)

10542 23:08:53.902380  <6>[    5.666007] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0

10543 23:08:53.915143  <6>[    5.667999] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1

10544 23:08:53.921905  <6>[    5.670413] cros-ec-spi spi0.0: Chrome EC device registered

10545 23:08:53.928270  <6>[    5.682812] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)

10546 23:08:53.934802  <6>[    5.683815] NET: Registered PF_PACKET protocol family

10547 23:08:53.938296  <6>[    5.683897] 9pnet: Installing 9P2000 support

10548 23:08:53.944716  <5>[    5.683931] Key type dns_resolver registered

10549 23:08:53.948371  <6>[    5.684432] registered taskstats version 1

10550 23:08:53.951886  <5>[    5.684448] Loading compiled-in X.509 certificates

10551 23:08:53.964910  <4>[    5.701496] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator

10552 23:08:53.974586  <4>[    5.701652] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator

10553 23:08:53.981038  <3>[    5.701662] debugfs: File 'uA_load' in directory '/' already present!

10554 23:08:53.987818  <3>[    5.701671] debugfs: File 'min_uV' in directory '/' already present!

10555 23:08:53.994991  <3>[    5.701674] debugfs: File 'max_uV' in directory '/' already present!

10556 23:08:54.001417  <3>[    5.701678] debugfs: File 'constraint_flags' in directory '/' already present!

10557 23:08:54.011771  <3>[    5.703607] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)

10558 23:08:54.014551  <6>[    5.710504] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102

10559 23:08:54.021076  <6>[    5.711048] xhci-mtk 11200000.usb: xHCI Host Controller

10560 23:08:54.027978  <6>[    5.711066] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1

10561 23:08:54.038204  <6>[    5.711276] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010

10562 23:08:54.044575  <6>[    5.711312] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000

10563 23:08:54.051073  <6>[    5.711388] xhci-mtk 11200000.usb: xHCI Host Controller

10564 23:08:54.058023  <6>[    5.711391] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2

10565 23:08:54.064760  <6>[    5.711396] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed

10566 23:08:54.067942  <6>[    5.711736] hub 1-0:1.0: USB hub found

10567 23:08:54.074863  <6>[    5.711746] hub 1-0:1.0: 1 port detected

10568 23:08:54.081201  <6>[    5.711848] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.

10569 23:08:54.084279  <6>[    5.712047] hub 2-0:1.0: USB hub found

10570 23:08:54.090807  <6>[    5.712051] hub 2-0:1.0: 1 port detected

10571 23:08:54.094311  <6>[    5.714781] mtk-msdc 11f70000.mmc: Got CD GPIO

10572 23:08:54.101171  <6>[    5.721881] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()

10573 23:08:54.111433  <6>[    5.721889] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()

10574 23:08:54.117977  <4>[    5.721966] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW

10575 23:08:54.127505  <6>[    5.722459] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()

10576 23:08:54.134638  <6>[    5.722461] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()

10577 23:08:54.144626  <6>[    5.722591] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()

10578 23:08:54.150769  <6>[    5.722597] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()

10579 23:08:54.157242  <6>[    5.722598] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()

10580 23:08:54.167817  <6>[    5.722602] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39

10581 23:08:54.177140  <6>[    5.723788] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)

10582 23:08:54.184154  <6>[    5.723804] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)

10583 23:08:54.193826  <6>[    5.723808] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)

10584 23:08:54.200264  <6>[    5.723811] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)

10585 23:08:54.210825  <6>[    5.723815] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)

10586 23:08:54.217692  <6>[    5.723818] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)

10587 23:08:54.227365  <6>[    5.723821] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)

10588 23:08:54.234079  <6>[    5.723825] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)

10589 23:08:54.243930  <6>[    5.723828] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)

10590 23:08:54.250517  <6>[    5.723832] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)

10591 23:08:54.260740  <6>[    5.723835] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)

10592 23:08:54.267238  <6>[    5.723839] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)

10593 23:08:54.277057  <6>[    5.723842] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)

10594 23:08:54.284480  <6>[    5.723846] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)

10595 23:08:54.293462  <6>[    5.723849] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)

10596 23:08:54.300541  <6>[    5.724148] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0

10597 23:08:54.307380  <6>[    5.724700] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0

10598 23:08:54.313414  <6>[    5.724929] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0

10599 23:08:54.320486  <6>[    5.725161] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0

10600 23:08:54.326829  <6>[    5.725446] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0

10601 23:08:54.333069  <6>[    5.725623] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)

10602 23:08:54.343487  <6>[    5.725634] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)

10603 23:08:54.352989  <6>[    5.725636] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)

10604 23:08:54.362822  <6>[    5.725640] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)

10605 23:08:54.373049  <6>[    5.725643] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)

10606 23:08:54.380135  <6>[    5.725646] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)

10607 23:08:54.389800  <6>[    5.725650] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)

10608 23:08:54.399367  <6>[    5.725652] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)

10609 23:08:54.409388  <6>[    5.725655] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)

10610 23:08:54.419529  <6>[    5.725658] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing

10611 23:08:54.429758  <6>[    5.725661] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing

10612 23:08:54.436253  <6>[    5.726324] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0

10613 23:08:54.443333  <6>[    6.109504] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk

10614 23:08:54.449407  <6>[    6.139252] hub 2-1:1.0: USB hub found

10615 23:08:54.452643  <6>[    6.139535] hub 2-1:1.0: 3 ports detected

10616 23:08:54.456219  <6>[    6.141082] hub 2-1:1.0: USB hub found

10617 23:08:54.459454  <6>[    6.141365] hub 2-1:1.0: 3 ports detected

10618 23:08:54.466557  <6>[    6.261406] usb 1-1: new high-speed USB device number 2 using xhci-mtk

10619 23:08:54.472832  <6>[    6.412919] hub 1-1:1.0: USB hub found

10620 23:08:54.476149  <6>[    6.413186] hub 1-1:1.0: 4 ports detected

10621 23:08:54.479627  <6>[    6.415511] hub 1-1:1.0: USB hub found

10622 23:08:54.483003  <6>[    6.415749] hub 1-1:1.0: 4 ports detected

10623 23:08:54.492501  <6>[    6.497423] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk

10624 23:08:54.499340  <6>[    6.741375] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk

10625 23:08:54.502898  <6>[    6.880145] hub 1-1.4:1.0: USB hub found

10626 23:08:54.505693  <6>[    6.880444] hub 1-1.4:1.0: 2 ports detected

10627 23:08:54.513008  <6>[    6.883366] hub 1-1.4:1.0: USB hub found

10628 23:08:54.515910  <6>[    6.883662] hub 1-1.4:1.0: 2 ports detected

10629 23:08:54.522767  <6>[    7.189368] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk

10630 23:08:54.529154  <6>[    7.389381] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk

10631 23:08:54.532259  <6>[   18.657728] ALSA device list:

10632 23:08:54.535769  <6>[   18.657732]   No soundcards found.

10633 23:08:54.543109  <6>[   20.873702] Freeing unused kernel memory: 8448K

10634 23:08:54.546372  <6>[   20.873779] Run /init as init process

10635 23:08:54.549173  <6>[   20.934535] NET: Registered PF_INET6 protocol family

10636 23:08:54.556041  <6>[   20.935669] Segment Routing with IPv6

10637 23:08:54.558992  <6>[   20.935677] In-situ OAM (IOAM) with IPv6

10638 23:08:54.582719  <30>[   20.968211] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)

10639 23:08:54.585505  <30>[   20.968395] systemd[1]: Detected architecture arm64.

10640 23:08:54.588587  mDebian GNU/Linux 11 (bullseye)!

10641 23:08:54.592809  

10642 23:08:54.610569  <30>[   21.749883] systemd[1]: Set hostname to <debian-bullseye-arm64>.

10643 23:08:54.701439  <30>[   21.837670] systemd[1]: Queued start job for default target Graphical Interface.

10644 23:08:54.739077  [  OK  ] Created slic<30>[   21.878544] systemd[1]: Created slice system-getty.slice.

10645 23:08:54.742101  e system-getty.slice.

10646 23:08:54.765241  [  OK  ] Created slice syste<30>[   21.902269] systemd[1]: Created slice system-modprobe.slice.

10647 23:08:54.765329  m-modprobe.slice.

10648 23:08:54.786947  [  OK  ] Created slic<30>[   21.926593] systemd[1]: Created slice system-serial\x2dgetty.slice.

10649 23:08:54.790281  e system-serial\x2dgetty.slice.

10650 23:08:54.813242  [  OK  ] Created slice User <30>[   21.949834] systemd[1]: Created slice User and Session Slice.

10651 23:08:54.813327  and Session Slice.

10652 23:08:54.837026  [  OK  ] Started Dispatch Pa<30>[   21.973535] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.

10653 23:08:54.840297  ssword …ts to Console Directory Watch.

10654 23:08:54.861124  [  OK  ] Started Forward Pas<30>[   21.997544] systemd[1]: Started Forward Password Requests to Wall Directory Watch.

10655 23:08:54.864323  sword R…uests to Wall Directory Watch.

10656 23:08:54.888753  [  OK  ] Reached target Loca<30>[   22.021583] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.

10657 23:08:54.895318  <30>[   22.021762] systemd[1]: Reached target Local Encrypted Volumes.

10658 23:08:54.898176  l Encrypted Volumes.

10659 23:08:54.918352  [  OK  ] Reached target Path<30>[   22.058097] systemd[1]: Reached target Paths.

10660 23:08:54.918493  s.

10661 23:08:54.941427  [  OK  ] Reached target Remo<30>[   22.077539] systemd[1]: Reached target Remote File Systems.

10662 23:08:54.941513  te File Systems.

10663 23:08:54.961848  [  OK  ] Reached target Slic<30>[   22.101833] systemd[1]: Reached target Slices.

10664 23:08:54.961936  es.

10665 23:08:54.981626  [  OK  ] Reached target Swap<30>[   22.121418] systemd[1]: Reached target Swap.

10666 23:08:54.981712  .

10667 23:08:55.005682  [  OK  ] Listening on initct<30>[   22.142003] systemd[1]: Listening on initctl Compatibility Named Pipe.

10668 23:08:55.008530  l Compatibility Named Pipe.

10669 23:08:55.015378  <30>[   22.157134] systemd[1]: Listening on Journal Audit Socket.

10670 23:08:55.022087  [  OK  ] Listening on Journal Audit Socket.

10671 23:08:55.039625  [  OK  ] Listening on<30>[   22.178759] systemd[1]: Listening on Journal Socket (/dev/log).

10672 23:08:55.042163   Journal Socket (/dev/log).

10673 23:08:55.062761  [  OK  ] Listening on<30>[   22.202803] systemd[1]: Listening on Journal Socket.

10674 23:08:55.066301   Journal Socket.

10675 23:08:55.085713  [  OK  ] Listening on Networ<30>[   22.222083] systemd[1]: Listening on Network Service Netlink Socket.

10676 23:08:55.089091  k Service Netlink Socket.

10677 23:08:55.106979  [  OK  ] Listening on<30>[   22.246739] systemd[1]: Listening on udev Control Socket.

10678 23:08:55.110610   udev Control Socket.

10679 23:08:55.130680  [  OK  ] Listening on<30>[   22.270610] systemd[1]: Listening on udev Kernel Socket.

10680 23:08:55.134291   udev Kernel Socket.

10681 23:08:55.177768           Mounting Huge Pages File Syste<30>[   22.317548] systemd[1]: Mounting Huge Pages File System...

10682 23:08:55.181315  m...

10683 23:08:55.199486           Mounting POSIX<30>[   22.339464] systemd[1]: Mounting POSIX Message Queue File System...

10684 23:08:55.203013   Message Queue File System...

10685 23:08:55.223751           Mountin<30>[   22.363883] systemd[1]: Mounting Kernel Debug File System...

10686 23:08:55.227388  g Kernel Debug File System...

10687 23:08:55.249381  <30>[   22.385890] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.

10688 23:08:55.262813           Starting Create list of st…o<30>[   22.389610] systemd[1]: Starting Create list of static device nodes for the current kernel...

10689 23:08:55.266241  des for the current kernel...

10690 23:08:55.293646           Starting Load Kernel Module co<30>[   22.430189] systemd[1]: Starting Load Kernel Module configfs...

10691 23:08:55.293731  nfigfs...

10692 23:08:55.317830           Starting Load Kernel Module dr<30>[   22.454069] systemd[1]: Starting Load Kernel Module drm...

10693 23:08:55.317914  m...

10694 23:08:55.337484  <30>[   22.474008] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.

10695 23:08:55.351459           Starting Journ<30>[   22.490755] systemd[1]: Starting Journal Service...

10696 23:08:55.351550  al Service...

10697 23:08:55.379989           Starting Load <30>[   22.519534] systemd[1]: Starting Load Kernel Modules...

10698 23:08:55.382997  Kernel Modules...

10699 23:08:55.409509           Starting Remount Root and Kern<30>[   22.546175] systemd[1]: Starting Remount Root and Kernel File Systems...

10700 23:08:55.412883  el File Systems...

10701 23:08:55.439030           Starting Coldp<30>[   22.578872] systemd[1]: Starting Coldplug All udev Devices...

10702 23:08:55.441858  lug All udev Devices...

10703 23:08:55.465898  [  OK  [<30>[   22.608923] systemd[1]: Started Journal Service.

10704 23:08:55.472051  0m] Started Journal Service.

10705 23:08:55.492388  [  OK  ] Mounted Huge Pages File System.

10706 23:08:55.510696  [  OK  ] Mounted POSIX Message Queue File System.

10707 23:08:55.527649  [  OK  ] Mounted Kernel Debug File System.

10708 23:08:55.546100  [  OK  ] Finished Create list of st… nodes for the current kernel.

10709 23:08:55.564358  [  OK  ] Finished Load Kernel Module configfs.

10710 23:08:55.581140  [  OK  ] Finished Load Kernel Module drm.

10711 23:08:55.600230  [  OK  ] Finished Load Kernel Modules.

10712 23:08:55.623964  [FAILED] Failed to start Remount Root and Kernel File Systems.

10713 23:08:55.638053  See 'systemctl status systemd-remount-fs.service' for details.

10714 23:08:55.682655           Mounting Kernel Configuration File System...

10715 23:08:55.702631           Starting Flush Journal to Persistent Storage...

10716 23:08:55.717104  <46>[   22.856149] systemd-journald[190]: Received client request to flush runtime journal.

10717 23:08:55.727322           Starting Load/Save Random Seed...

10718 23:08:55.746347           Starting Apply Kernel Variables...

10719 23:08:55.767384           Starting Create System Users...

10720 23:08:55.790082  [  OK  ] Finished Coldplug All udev Devices.

10721 23:08:55.811623  [  OK  ] Mounted Kernel Configuration File System.

10722 23:08:55.835774  [  OK  ] Finished Flush Journal to Persistent Storage.

10723 23:08:55.852292  [  OK  ] Finished Load/Save Random Seed.

10724 23:08:55.872691  [  OK  ] Finished Apply Kernel Variables.

10725 23:08:55.886582  [  OK  ] Finished Create System Users.

10726 23:08:55.934280           Starting Create Static Device Nodes in /dev...

10727 23:08:55.958197  [  OK  ] Finished Create Static Device Nodes in /dev.

10728 23:08:55.970031  [  OK  ] Reached target Local File Systems (Pre).

10729 23:08:55.989701  [  OK  ] Reached target Local File Systems.

10730 23:08:56.026832           Starting Create Volatile Files and Directories...

10731 23:08:56.054820           Starting Rule-based Manage…for Device Events and Files...

10732 23:08:56.083407  [  OK  ] Started Rule-based Manager for Device Events and Files.

10733 23:08:56.104293  [  OK  ] Finished Create Volatile Files and Directories.

10734 23:08:56.157808           Starting Network Service...

10735 23:08:56.185704           Starting Network Time Synchronization...

10736 23:08:56.217039           Starting Update UTMP about System Boot/Shutdown...

10737 23:08:56.237303  [  OK  ] Started Network Service.

10738 23:08:56.272411  [  OK  ] Started Network Time Synchronization.

10739 23:08:56.285033  <6>[   23.423742] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000

10740 23:08:56.293088  [  OK  ] Found device /dev/ttyS0.

10741 23:08:56.299535  <6>[   23.437745] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:

10742 23:08:56.309664  <6>[   23.437784] mtk-pcie-gen3 11230000.pcie:      MEM 0x0012000000..0x00127fffff -> 0x0012000000

10743 23:08:56.319536  <6>[   23.437793] mtk-pcie-gen3 11230000.pcie:       IO 0x0012800000..0x0012ffffff -> 0x0012800000

10744 23:08:56.323125  <6>[   23.443743] remoteproc remoteproc0: scp is available

10745 23:08:56.329341  <6>[   23.443924] remoteproc remoteproc0: powering up scp

10746 23:08:56.336372  <6>[   23.443931] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164

10747 23:08:56.345906  [  OK  [<6>[   23.443965] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0

10748 23:08:56.352959  <3>[   23.478841] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10749 23:08:56.359643  <3>[   23.478858] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10750 23:08:56.369365  <3>[   23.478862] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10751 23:08:56.376253  <3>[   23.487586] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10752 23:08:56.385949  <3>[   23.487619] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10753 23:08:56.392888  <3>[   23.487624] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10754 23:08:56.403187  <3>[   23.487630] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10755 23:08:56.409547  <3>[   23.487636] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10756 23:08:56.415822  <3>[   23.492182] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10757 23:08:56.426990  <4>[   23.495577] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator

10758 23:08:56.432511  <4>[   23.499162] elants_i2c 4-0010: supply vccio not found, using dummy regulator

10759 23:08:56.439550  <3>[   23.519989] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10760 23:08:56.449764  <3>[   23.520033] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10761 23:08:56.456698  <3>[   23.520046] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10762 23:08:56.466756  0m] Finished [0<3>[   23.526265] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10763 23:08:56.473202  <3>[   23.526294] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10764 23:08:56.484334  <3>[   23.526298] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10765 23:08:56.490612  <3>[   23.526304] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10766 23:08:56.497798  <3>[   23.526307] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10767 23:08:56.507455  ;1;39mUpdate UTM<3>[   23.531132] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10768 23:08:56.510877  <6>[   23.532560] mc: Linux media interface: v0.10

10769 23:08:56.517981  <6>[   23.558935] usbcore: registered new interface driver r8152

10770 23:08:56.528346  P about System B<6>[   23.560922] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered

10771 23:08:56.534791  <6>[   23.564088] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00

10772 23:08:56.538329  <6>[   23.564113] pci_bus 0000:00: root bus resource [bus 00-ff]

10773 23:08:56.548382  oot/Shutdown<6>[   23.564121] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]

10774 23:08:56.558619  <6>[   23.564125] pci_bus 0000:00: root bus resource [io  0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])

10775 23:08:56.565468  <6>[   23.564193] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400

10776 23:08:56.572346  <6>[   23.564221] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]

10777 23:08:56.572435  .

10778 23:08:56.575707  <6>[   23.564328] pci 0000:00:00.0: supports D1 D2

10779 23:08:56.582731  <6>[   23.564333] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold

10780 23:08:56.592692  <6>[   23.565400] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e

10781 23:08:56.599323  <6>[   23.565405] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd

10782 23:08:56.605991  <6>[   23.565410] remoteproc remoteproc0: remote processor scp is now up

10783 23:08:56.613040  <6>[   23.567331] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring

10784 23:08:56.619092  <6>[   23.568236] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000

10785 23:08:56.626141  <6>[   23.568270] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]

10786 23:08:56.635853  <6>[   23.568292] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]

10787 23:08:56.642579  <6>[   23.568307] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]

10788 23:08:56.645676  <6>[   23.568425] pci 0000:01:00.0: supports D1 D2

10789 23:08:56.652840  <6>[   23.568428] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold

10790 23:08:56.666975  [  OK  ] Created slice syste<4>[   23.583709] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.

10791 23:08:56.670116  <4>[   23.583709] Fallback method does not support PEC.

10792 23:08:56.680224  m-systemd\x2dbac<6>[   23.585101] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01

10793 23:08:56.690929  klight.slice<6>[   23.585198] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]

10794 23:08:56.691082  .

10795 23:08:56.697394  <6>[   23.585206] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]

10796 23:08:56.704397  <6>[   23.585236] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]

10797 23:08:56.714701  <6>[   23.585286] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]

10798 23:08:56.722100  <6>[   23.585305] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]

10799 23:08:56.732633  [  OK  ] Reached target Syst<6>[   23.585414] pci 0000:00:00.0: PCI bridge to [bus 01]

10800 23:08:56.742250  em Time Set.<6>[   23.585438] pci 0000:00:00.0:   bridge window [mem 0x12000000-0x121fffff 64bit pref]

10801 23:08:56.742342  

10802 23:08:56.745671  <6>[   23.587494] pcieport 0000:00:00.0: enabling device (0000 -> 0002)

10803 23:08:56.751963  <6>[   23.596285] pcieport 0000:00:00.0: PME: Signaling with IRQ 282

10804 23:08:56.759772  <6>[   23.597844] pcieport 0000:00:00.0: AER: enabled with IRQ 282

10805 23:08:56.769105  [  OK  ] Reached targ<3>[   23.601587] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10806 23:08:56.783304  et Syst<6>[   23.602241] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003

10807 23:08:56.787133  <6>[   23.603977] videodev: Linux video capture interface: v2.00

10808 23:08:56.797419  <6>[   23.609477] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2

10809 23:08:56.806939  em Time Synchron<6>[   23.611432] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3

10810 23:08:56.807063  ized.

10811 23:08:56.816843  <3>[   23.641367] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10812 23:08:56.820223  <6>[   23.661484] Bluetooth: Core ver 2.22

10813 23:08:56.826916  <6>[   23.661604] NET: Registered PF_BLUETOOTH protocol family

10814 23:08:56.837644  [  OK  ] Listening on<6>[   23.661605] Bluetooth: HCI device and connection manager initialized

10815 23:08:56.839855  <6>[   23.661621] Bluetooth: HCI socket layer initialized

10816 23:08:56.846837  <6>[   23.661624] Bluetooth: L2CAP socket layer initialized

10817 23:08:56.853077  <6>[   23.661630] Bluetooth: SCO socket layer initialized

10818 23:08:56.859888  <3>[   23.669187] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10819 23:08:56.866649  <6>[   23.676683] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk

10820 23:08:56.873307  <6>[   23.679136] usbcore: registered new interface driver cdc_ether

10821 23:08:56.879913  <6>[   23.690971] usbcore: registered new interface driver r8153_ecm

10822 23:08:56.889419  <3>[   23.702951] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10823 23:08:56.896434  <4>[   23.707859] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2

10824 23:08:56.906592  <4>[   23.707901] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)

10825 23:08:56.912978  <6>[   23.712830] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)

10826 23:08:56.926036  <6>[   23.728845] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4

10827 23:08:56.933111  <6>[   23.729559] usbcore: registered new interface driver uvcvideo

10828 23:08:56.939669  <3>[   23.732875] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10829 23:08:56.949574  <4>[   23.789877] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2

10830 23:08:56.956052  <3>[   23.789897] Bluetooth: hci0: Failed to load firmware file (-2)

10831 23:08:56.962803  <3>[   23.789899] Bluetooth: hci0: Failed to set up firmware (-2)

10832 23:08:56.973292  <4>[   23.789901] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.

10833 23:08:56.979626  <6>[   23.798686] usbcore: registered new interface driver btusb

10834 23:08:56.985801  <6>[   23.802263] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0

10835 23:08:56.989304  <6>[   23.806286] r8152 2-1.3:1.0 eth0: v1.12.13

10836 23:08:56.999526  <6>[   23.806568] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected

10837 23:08:57.006058  <5>[   23.807291] cfg80211: Loading compiled-in X.509 certificates for regulatory database

10838 23:08:57.012800  <6>[   23.814610] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered

10839 23:08:57.022648  <3>[   23.815912] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10840 23:08:57.032668  <3>[   23.817640] power_supply sbs-5-000b: driver failed to report `voltage_now' property: -6

10841 23:08:57.036682  <6>[   23.821138] r8152 2-1.3:1.0 enx002432307852: renamed from eth0

10842 23:08:57.042349  <5>[   23.823008] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'

10843 23:08:57.052403  <3>[   23.840415] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10844 23:08:57.062142  <3>[   23.841220] power_supply sbs-5-000b: driver failed to report `cycle_count' property: -6

10845 23:08:57.069071  <3>[   23.863799] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10846 23:08:57.078953  <4>[   23.914724] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2

10847 23:08:57.081966  <6>[   23.914764] cfg80211: failed to load regulatory.db

10848 23:08:57.092473  <6>[   23.993922] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000

10849 23:08:57.095284  <6>[   23.994039] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)

10850 23:08:57.102360  <6>[   24.013453] mt7921e 0000:01:00.0: ASIC revision: 79610010

10851 23:08:57.112416  <6>[   24.108938] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a

10852 23:08:57.112527  <6>[   24.108938] 

10853 23:08:57.118951   Load/Save RF …itch Status /dev/rfkill Watch.

10854 23:08:57.165562           Starting Load/Save Screen …of leds:white:kbd_backlight...

10855 23:08:57.186171           Starting Network Name Resolution...

10856 23:08:57.208258  [  OK  ] Finished Load/Save Screen …s of leds:white:kbd_backlight.

10857 23:08:57.229503  <6>[   24.367599] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959

10858 23:08:57.250774  [  OK  ] Reached target Bluetooth.

10859 23:08:57.266204  [  OK  ] Reached target System Initialization.

10860 23:08:57.285789  [  OK  ] Started Discard unused blocks once a week.

10861 23:08:57.301123  [  OK  ] Started Daily Cleanup of Temporary Directories.

10862 23:08:57.314351  [  OK  ] Reached target Timers.

10863 23:08:57.333883  [  OK  ] Listening on D-Bus System Message Bus Socket.

10864 23:08:57.346023  [  OK  ] Reached target Sockets.

10865 23:08:57.363126  [  OK  ] Reached target Basic System.

10866 23:08:57.418699  [  OK  ] Started D-Bus System Message Bus.

10867 23:08:57.495260           Starting User Login Management...

10868 23:08:57.515349           Starting Load/Save RF Kill Switch Status...

10869 23:08:57.531115  [  OK  ] Started Network Name Resolution.

10870 23:08:57.549906  [  OK  ] Started Load/Save RF Kill Switch Status.

10871 23:08:57.570940  [  OK  ] Reached target Network.

10872 23:08:57.589693  [  OK  ] Reached target Host and Network Name Lookups.

10873 23:08:57.643101           Starting Permit User Sessions...

10874 23:08:57.658527  [  OK  ] Started User Login Management.

10875 23:08:57.676124  [  OK  ] Finished Permit User Sessions.

10876 23:08:57.739333  [  OK  ] Started Getty on tty1.

10877 23:08:57.758529  [  OK  ] Started Serial Getty on ttyS0.

10878 23:08:57.775239  [  OK  ] Reached target Login Prompts.

10879 23:08:57.791105  [  OK  ] Reached target Multi-User System.

10880 23:08:57.806306  [  OK  ] Reached target Graphical Interface.

10881 23:08:57.862508           Starting Update UTMP about System Runlevel Changes...

10882 23:08:57.897779  [  OK  ] Finished Update UTMP about System Runlevel Changes.

10883 23:08:57.941632  

10884 23:08:57.941772  

10885 23:08:57.945060  Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0

10886 23:08:57.945169  

10887 23:08:57.948699  debian-bullseye-arm64 login: root (automatic login)

10888 23:08:57.948781  

10889 23:08:57.948844  

10890 23:08:57.964321  Linux debian-bullseye-arm64 6.1.67-cip12-rt7 #1 SMP PREEMPT Wed Dec 27 22:50:56 UTC 2023 aarch64

10891 23:08:57.964412  

10892 23:08:57.971072  The programs included with the Debian GNU/Linux system are free software;

10893 23:08:57.977659  the exact distribution terms for each program are described in the

10894 23:08:57.981062  individual files in /usr/share/doc/*/copyright.

10895 23:08:57.981143  

10896 23:08:57.987705  Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent

10897 23:08:57.990918  permitted by applicable law.

10898 23:08:57.991726  Matched prompt #10: / #
10900 23:08:57.991932  Setting prompt string to ['/ #']
10901 23:08:57.992023  end: 2.2.5.1 login-action (duration 00:00:26) [common]
10903 23:08:57.992215  end: 2.2.5 auto-login-action (duration 00:00:26) [common]
10904 23:08:57.992296  start: 2.2.6 expect-shell-connection (timeout 00:02:42) [common]
10905 23:08:57.992366  Setting prompt string to ['/ #']
10906 23:08:57.992426  Forcing a shell prompt, looking for ['/ #']
10908 23:08:58.042619  / # 

10909 23:08:58.042793  expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10910 23:08:58.042907  Waiting using forced prompt support (timeout 00:02:30)
10911 23:08:58.048110  

10912 23:08:58.048388  end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10913 23:08:58.048484  start: 2.2.7 export-device-env (timeout 00:02:42) [common]
10914 23:08:58.048574  end: 2.2.7 export-device-env (duration 00:00:00) [common]
10915 23:08:58.048656  end: 2.2 depthcharge-retry (duration 00:02:18) [common]
10916 23:08:58.048735  end: 2 depthcharge-action (duration 00:02:18) [common]
10917 23:08:58.048819  start: 3 lava-test-retry (timeout 00:05:00) [common]
10918 23:08:58.048900  start: 3.1 lava-test-shell (timeout 00:05:00) [common]
10919 23:08:58.048974  Using namespace: common
10921 23:08:58.149360  / # #

10922 23:08:58.149537  lava-test-shell: Wait for prompt ['/ #'] (timeout 00:05:00)
10923 23:08:58.149656  <6>[   25.210593] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0

10924 23:08:58.154601  #

10925 23:08:58.154868  Using /lava-12395354
10927 23:08:58.255208  / # export SHELL=/bin/sh

10928 23:08:58.260449  export SHELL=/bin/sh

10930 23:08:58.361017  / # . /lava-12395354/environment

10931 23:08:58.361233  <6>[   25.411083] IPv6: ADDRCONF(NETDEV_CHANGE): enx002432307852: link becomes ready

10932 23:08:58.361312  <6>[   25.413113] r8152 2-1.3:1.0 enx002432307852: carrier on

10933 23:08:58.366404  . /lava-12395354/environment

10935 23:08:58.466984  / # /lava-12395354/bin/lava-test-runner /lava-12395354/0

10936 23:08:58.467220  Test shell timeout: 10s (minimum of the action and connection timeout)
10937 23:08:58.472807  /lava-12395354/bin/lava-test-runner /lava-12395354/0

10938 23:08:58.491995  + export TESTRUN_ID=0_cros-ec

10939 23:08:58.495789  + cd /lava-12395354/0/tests/0_cros-ec

10940 23:08:58.502274  + cat uuid<8>[   25.641668] <LAVA_SIGNAL_STARTRUN 0_cros-ec 12395354_1.5.2.3.1>

10941 23:08:58.502548  Received signal: <STARTRUN> 0_cros-ec 12395354_1.5.2.3.1
10942 23:08:58.502621  Starting test lava.0_cros-ec (12395354_1.5.2.3.1)
10943 23:08:58.502704  Skipping test definition patterns.
10944 23:08:58.505473  

10945 23:08:58.505552  + UUID=12395354_1.5.2.3.1

10946 23:08:58.505617  + set +x

10947 23:08:58.512171  + python3 -m cros.runners.lava_runner -v

10948 23:08:58.887342  test_cros_ec_accel_iio_abi (cros.tests.cros_ec_accel.TestCrosECAccel)

10949 23:08:58.894146  Checks the cros-ec accelerometer IIO ABI. ... skipped 'No cros-ec-accel found'

10950 23:08:58.894261  

10951 23:08:58.900738  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_accel_iio_abi RESULT=skip>

10952 23:08:58.900991  Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_accel_iio_abi RESULT=skip
10954 23:08:58.910637  test_cros_ec_accel_iio_data_is_valid (cros.tests.cros_ec_accel.TestCrosECAccel)

10955 23:08:58.917283  Validates accelerometer data by computing the magnitude. If the ... skipped 'No accelerometer found'

10956 23:08:58.917364  

10957 23:08:58.926944  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_accel_iio_data_is_valid RESULT=skip>

10958 23:08:58.927195  Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_accel_iio_data_is_valid RESULT=skip
10960 23:08:58.936808  test_cros_ec_gyro_iio_abi (cros.tests.cros_e<8>[   26.075027] <LAVA_SIGNAL_ENDRUN 0_cros-ec 12395354_1.5.2.3.1>

10961 23:08:58.936888  c_gyro.TestCrosECGyro)

10962 23:08:58.937120  Received signal: <ENDRUN> 0_cros-ec 12395354_1.5.2.3.1
10963 23:08:58.937195  Ending use of test pattern.
10964 23:08:58.937253  Ending test lava.0_cros-ec (12395354_1.5.2.3.1), duration 0.43
10966 23:08:58.943516  Checks the cros-ec gyroscope IIO ABI. ... skipped 'No cros-ec-gyro found'

10967 23:08:58.943596  

10968 23:08:58.949950  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_gyro_iio_abi RESULT=skip>

10969 23:08:58.950199  Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_gyro_iio_abi RESULT=skip
10971 23:08:58.956703  test_cros_ec_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)

10972 23:08:58.960369  Checks the standard ABI for the main Embedded Controller. ... ok

10973 23:08:58.960449  

10974 23:08:58.966623  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_abi RESULT=pass>

10975 23:08:58.966871  Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_abi RESULT=pass
10977 23:08:58.973279  test_cros_ec_chardev (cros.tests.cros_ec_mcu.TestCrosECMCU)

10978 23:08:58.976868  Checks the main Embedded controller character device. ... ok

10979 23:08:58.976948  

10980 23:08:58.983889  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_chardev RESULT=pass>

10981 23:08:58.984138  Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_chardev RESULT=pass
10983 23:08:58.990114  test_cros_ec_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)

10984 23:08:58.996358  Checks basic comunication with the main Embedded controller. ... ok

10985 23:08:58.996437  

10986 23:08:59.000136  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_hello RESULT=pass>

10987 23:08:59.000440  Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_hello RESULT=pass
10989 23:08:59.006858  test_cros_fp_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)

10990 23:08:59.013138  Checks the standard ABI for the Fingerprint EC. ... skipped 'MCU cros_fp not supported'

10991 23:08:59.013218  

10992 23:08:59.019728  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_abi RESULT=skip>

10993 23:08:59.019977  Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_abi RESULT=skip
10995 23:08:59.026580  test_cros_fp_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)

10996 23:08:59.032897  Checks basic comunication with the fingerprint controller. ... skipped 'MCU cros_fp not found'

10997 23:08:59.032979  

10998 23:08:59.040018  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_hello RESULT=skip>

10999 23:08:59.040296  Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_hello RESULT=skip
11001 23:08:59.046823  test_cros_fp_reboot (cros.tests.cros_ec_mcu.TestCrosECMCU)

11002 23:08:59.053504  Test reboot command on Fingerprint MCU. ... skipped 'MCU cros_fp not found'

11003 23:08:59.053587  

11004 23:08:59.056315  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_reboot RESULT=skip>

11005 23:08:59.056566  Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_reboot RESULT=skip
11007 23:08:59.063508  test_cros_pd_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)

11008 23:08:59.069794  Checks the standard ABI for the Power Delivery EC. ... skipped 'MCU cros_pd not supported'

11009 23:08:59.069876  

11010 23:08:59.076294  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_pd_abi RESULT=skip>

11011 23:08:59.076545  Received signal: <TESTCASE> TEST_CASE_ID=test_cros_pd_abi RESULT=skip
11013 23:08:59.083334  test_cros_pd_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)

11014 23:08:59.089759  Checks basic comunication with the power delivery controller. ... skipped 'MCU cros_pd not found'

11015 23:08:59.089841  

11016 23:08:59.096426  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_pd_hello RESULT=skip>

11017 23:08:59.096677  Received signal: <TESTCASE> TEST_CASE_ID=test_cros_pd_hello RESULT=skip
11019 23:08:59.102814  test_cros_tp_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)

11020 23:08:59.109697  Checks the standard ABI for the Touchpad EC. ... skipped 'MCU cros_tp not supported'

11021 23:08:59.109805  

11022 23:08:59.112766  Received signal: <TESTCASE> TEST_CASE_ID=test_cros_tp_abi RESULT=skip
11024 23:08:59.115963  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_tp_abi RESULT=skip>

11025 23:08:59.119741  test_cros_tp_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)

11026 23:08:59.129103  Checks basic comunication with the touchpad controller. ... skipped 'MCU cros_tp not found'

11027 23:08:59.129199  

11028 23:08:59.132510  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_tp_hello RESULT=skip>

11029 23:08:59.132760  Received signal: <TESTCASE> TEST_CASE_ID=test_cros_tp_hello RESULT=skip
11031 23:08:59.139035  test_cros_ec_pwm_backlight (cros.tests.cros_ec_pwm.TestCrosECPWM)

11032 23:08:59.149163  Check that the backlight is connected to a pwm of the EC and that ... skipped 'No backlight pwm found'

11033 23:08:59.149246  

11034 23:08:59.156034  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_pwm_backlight RESULT=skip>

11035 23:08:59.156285  Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_pwm_backlight RESULT=skip
11037 23:08:59.162370  test_cros_ec_battery_abi (cros.tests.cros_ec_power.TestCrosECPower)

11038 23:08:59.165499  Check the cros battery ABI. ... skipped 'No BAT found'

11039 23:08:59.165580  

11040 23:08:59.172542  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_battery_abi RESULT=skip>

11041 23:08:59.172793  Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_battery_abi RESULT=skip
11043 23:08:59.179234  test_cros_ec_usbpd_charger_abi (cros.tests.cros_ec_power.TestCrosECPower)

11044 23:08:59.185424  Check the cros USBPD charger ABI. ... skipped 'No CROS_USBPD_CHARGER found'

11045 23:08:59.185531  

11046 23:08:59.192443  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_usbpd_charger_abi RESULT=skip>

11047 23:08:59.192695  Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_usbpd_charger_abi RESULT=skip
11049 23:08:59.198810  test_cros_ec_rtc_abi (cros.tests.cros_ec_rtc.TestCrosECRTC)

11050 23:08:59.205950  Check the cros RTC ABI. ... skipped 'EC_FEATURE_RTC not supported, skipping'

11051 23:08:59.206057  

11052 23:08:59.212223  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_rtc_abi RESULT=skip>

11053 23:08:59.212483  Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_rtc_abi RESULT=skip
11055 23:08:59.219765  test_cros_ec_extcon_usbc_abi (cros.tests.cros_ec_extcon.TestCrosECextcon)

11056 23:08:59.225738  Checks the cros-ec extcon ABI. ... skipped 'No extcon device found'

11057 23:08:59.225819  

11058 23:08:59.232478  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_extcon_usbc_abi RESULT=skip>

11059 23:08:59.232559  

11060 23:08:59.232792  Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_extcon_usbc_abi RESULT=skip
11062 23:08:59.238930  ----------------------------------------------------------------------

11063 23:08:59.239013  Ran 18 tests in 0.009s

11064 23:08:59.239076  

11065 23:08:59.241929  OK (skipped=15)

11066 23:08:59.242010  + set +x

11067 23:08:59.245275  <LAVA_TEST_RUNNER EXIT>

11068 23:08:59.245528  ok: lava_test_shell seems to have completed
11069 23:08:59.245699  test_cros_ec_abi: pass
test_cros_ec_accel_iio_abi: skip
test_cros_ec_accel_iio_data_is_valid: skip
test_cros_ec_battery_abi: skip
test_cros_ec_chardev: pass
test_cros_ec_extcon_usbc_abi: skip
test_cros_ec_gyro_iio_abi: skip
test_cros_ec_hello: pass
test_cros_ec_pwm_backlight: skip
test_cros_ec_rtc_abi: skip
test_cros_ec_usbpd_charger_abi: skip
test_cros_fp_abi: skip
test_cros_fp_hello: skip
test_cros_fp_reboot: skip
test_cros_pd_abi: skip
test_cros_pd_hello: skip
test_cros_tp_abi: skip
test_cros_tp_hello: skip

11070 23:08:59.245796  end: 3.1 lava-test-shell (duration 00:00:01) [common]
11071 23:08:59.245879  end: 3 lava-test-retry (duration 00:00:01) [common]
11072 23:08:59.245970  start: 4 finalize (timeout 00:07:14) [common]
11073 23:08:59.246057  start: 4.1 power-off (timeout 00:00:30) [common]
11074 23:08:59.246209  Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=off'
11075 23:08:59.325634  >> Command sent successfully.

11076 23:08:59.328115  Returned 0 in 0 seconds
11077 23:08:59.428526  end: 4.1 power-off (duration 00:00:00) [common]
11079 23:08:59.428904  start: 4.2 read-feedback (timeout 00:07:14) [common]
11080 23:08:59.429260  Listened to connection for namespace 'common' for up to 1s
11081 23:09:00.430159  Finalising connection for namespace 'common'
11082 23:09:00.430381  Disconnecting from shell: Finalise
11083 23:09:00.430501  / # 
11084 23:09:00.530811  end: 4.2 read-feedback (duration 00:00:01) [common]
11085 23:09:00.530987  end: 4 finalize (duration 00:00:01) [common]
11086 23:09:00.531101  Cleaning after the job
11087 23:09:00.531200  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12395354/tftp-deploy-z6ayw89f/ramdisk
11088 23:09:00.538154  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12395354/tftp-deploy-z6ayw89f/kernel
11089 23:09:00.546868  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12395354/tftp-deploy-z6ayw89f/dtb
11090 23:09:00.547098  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12395354/tftp-deploy-z6ayw89f/modules
11091 23:09:00.554492  Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12395354
11092 23:09:00.675609  Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12395354
11093 23:09:00.675770  Job finished correctly