Boot log: mt8192-asurada-spherion-r0
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 12
- Kernel Errors: 26
- Errors: 0
1 23:06:04.026707 lava-dispatcher, installed at version: 2023.10
2 23:06:04.026910 start: 0 validate
3 23:06:04.027045 Start time: 2023-12-27 23:06:04.027037+00:00 (UTC)
4 23:06:04.027160 Using caching service: 'http://localhost/cache/?uri=%s'
5 23:06:04.027291 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-igt%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 23:06:04.287050 Using caching service: 'http://localhost/cache/?uri=%s'
7 23:06:04.287232 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.66-cip11-rt6-10-g38253b8903b4%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 23:06:04.545966 Using caching service: 'http://localhost/cache/?uri=%s'
9 23:06:04.547050 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.66-cip11-rt6-10-g38253b8903b4%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 23:06:30.365705 Using caching service: 'http://localhost/cache/?uri=%s'
11 23:06:30.366458 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.66-cip11-rt6-10-g38253b8903b4%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 23:06:30.892830 validate duration: 26.87
14 23:06:30.893103 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 23:06:30.893198 start: 1.1 download-retry (timeout 00:10:00) [common]
16 23:06:30.893284 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 23:06:30.893404 Not decompressing ramdisk as can be used compressed.
18 23:06:30.893491 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-igt/20230623.0/arm64/rootfs.cpio.gz
19 23:06:30.893556 saving as /var/lib/lava/dispatcher/tmp/12395367/tftp-deploy-jpgcxkez/ramdisk/rootfs.cpio.gz
20 23:06:30.893618 total size: 43284872 (41 MB)
21 23:06:36.394909 progress 0 % (0 MB)
22 23:06:36.409538 progress 5 % (2 MB)
23 23:06:36.420561 progress 10 % (4 MB)
24 23:06:36.431900 progress 15 % (6 MB)
25 23:06:36.442931 progress 20 % (8 MB)
26 23:06:36.453901 progress 25 % (10 MB)
27 23:06:36.464955 progress 30 % (12 MB)
28 23:06:36.476275 progress 35 % (14 MB)
29 23:06:36.487575 progress 40 % (16 MB)
30 23:06:36.498994 progress 45 % (18 MB)
31 23:06:36.510111 progress 50 % (20 MB)
32 23:06:36.521120 progress 55 % (22 MB)
33 23:06:36.532443 progress 60 % (24 MB)
34 23:06:36.543772 progress 65 % (26 MB)
35 23:06:36.555019 progress 70 % (28 MB)
36 23:06:36.566562 progress 75 % (30 MB)
37 23:06:36.577862 progress 80 % (33 MB)
38 23:06:36.589054 progress 85 % (35 MB)
39 23:06:36.600186 progress 90 % (37 MB)
40 23:06:36.611204 progress 95 % (39 MB)
41 23:06:36.622278 progress 100 % (41 MB)
42 23:06:36.622621 41 MB downloaded in 5.73 s (7.21 MB/s)
43 23:06:36.622784 end: 1.1.1 http-download (duration 00:00:06) [common]
45 23:06:36.623032 end: 1.1 download-retry (duration 00:00:06) [common]
46 23:06:36.623120 start: 1.2 download-retry (timeout 00:09:54) [common]
47 23:06:36.623205 start: 1.2.1 http-download (timeout 00:09:54) [common]
48 23:06:36.623348 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.66-cip11-rt6-10-g38253b8903b4/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 23:06:36.623418 saving as /var/lib/lava/dispatcher/tmp/12395367/tftp-deploy-jpgcxkez/kernel/Image
50 23:06:36.623480 total size: 50024960 (47 MB)
51 23:06:36.623542 No compression specified
52 23:06:36.624683 progress 0 % (0 MB)
53 23:06:36.637588 progress 5 % (2 MB)
54 23:06:36.650484 progress 10 % (4 MB)
55 23:06:36.663537 progress 15 % (7 MB)
56 23:06:36.676911 progress 20 % (9 MB)
57 23:06:36.689836 progress 25 % (11 MB)
58 23:06:36.702758 progress 30 % (14 MB)
59 23:06:36.716068 progress 35 % (16 MB)
60 23:06:36.729210 progress 40 % (19 MB)
61 23:06:36.742050 progress 45 % (21 MB)
62 23:06:36.755068 progress 50 % (23 MB)
63 23:06:36.768169 progress 55 % (26 MB)
64 23:06:36.781167 progress 60 % (28 MB)
65 23:06:36.794475 progress 65 % (31 MB)
66 23:06:36.807385 progress 70 % (33 MB)
67 23:06:36.820304 progress 75 % (35 MB)
68 23:06:36.833608 progress 80 % (38 MB)
69 23:06:36.846405 progress 85 % (40 MB)
70 23:06:36.859280 progress 90 % (42 MB)
71 23:06:36.872398 progress 95 % (45 MB)
72 23:06:36.885138 progress 100 % (47 MB)
73 23:06:36.885372 47 MB downloaded in 0.26 s (182.17 MB/s)
74 23:06:36.885526 end: 1.2.1 http-download (duration 00:00:00) [common]
76 23:06:36.885760 end: 1.2 download-retry (duration 00:00:00) [common]
77 23:06:36.885855 start: 1.3 download-retry (timeout 00:09:54) [common]
78 23:06:36.885942 start: 1.3.1 http-download (timeout 00:09:54) [common]
79 23:06:36.886084 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.66-cip11-rt6-10-g38253b8903b4/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 23:06:36.886154 saving as /var/lib/lava/dispatcher/tmp/12395367/tftp-deploy-jpgcxkez/dtb/mt8192-asurada-spherion-r0.dtb
81 23:06:36.886216 total size: 47278 (0 MB)
82 23:06:36.886278 No compression specified
83 23:06:36.887420 progress 69 % (0 MB)
84 23:06:36.887695 progress 100 % (0 MB)
85 23:06:36.887852 0 MB downloaded in 0.00 s (27.60 MB/s)
86 23:06:36.887975 end: 1.3.1 http-download (duration 00:00:00) [common]
88 23:06:36.888195 end: 1.3 download-retry (duration 00:00:00) [common]
89 23:06:36.888279 start: 1.4 download-retry (timeout 00:09:54) [common]
90 23:06:36.888361 start: 1.4.1 http-download (timeout 00:09:54) [common]
91 23:06:36.888480 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.66-cip11-rt6-10-g38253b8903b4/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 23:06:36.888549 saving as /var/lib/lava/dispatcher/tmp/12395367/tftp-deploy-jpgcxkez/modules/modules.tar
93 23:06:36.888613 total size: 8633892 (8 MB)
94 23:06:36.888674 Using unxz to decompress xz
95 23:06:36.892904 progress 0 % (0 MB)
96 23:06:36.913892 progress 5 % (0 MB)
97 23:06:36.937402 progress 10 % (0 MB)
98 23:06:36.960634 progress 15 % (1 MB)
99 23:06:36.985457 progress 20 % (1 MB)
100 23:06:37.010783 progress 25 % (2 MB)
101 23:06:37.039785 progress 30 % (2 MB)
102 23:06:37.065046 progress 35 % (2 MB)
103 23:06:37.088815 progress 40 % (3 MB)
104 23:06:37.113083 progress 45 % (3 MB)
105 23:06:37.138355 progress 50 % (4 MB)
106 23:06:37.162629 progress 55 % (4 MB)
107 23:06:37.189372 progress 60 % (4 MB)
108 23:06:37.214944 progress 65 % (5 MB)
109 23:06:37.239866 progress 70 % (5 MB)
110 23:06:37.263317 progress 75 % (6 MB)
111 23:06:37.291918 progress 80 % (6 MB)
112 23:06:37.318834 progress 85 % (7 MB)
113 23:06:37.346940 progress 90 % (7 MB)
114 23:06:37.378624 progress 95 % (7 MB)
115 23:06:37.406772 progress 100 % (8 MB)
116 23:06:37.412228 8 MB downloaded in 0.52 s (15.73 MB/s)
117 23:06:37.412499 end: 1.4.1 http-download (duration 00:00:01) [common]
119 23:06:37.412848 end: 1.4 download-retry (duration 00:00:01) [common]
120 23:06:37.412957 start: 1.5 prepare-tftp-overlay (timeout 00:09:53) [common]
121 23:06:37.413073 start: 1.5.1 extract-nfsrootfs (timeout 00:09:53) [common]
122 23:06:37.413175 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 23:06:37.413283 start: 1.5.2 lava-overlay (timeout 00:09:53) [common]
124 23:06:37.413536 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12395367/lava-overlay-1a5dhpcj
125 23:06:37.413715 makedir: /var/lib/lava/dispatcher/tmp/12395367/lava-overlay-1a5dhpcj/lava-12395367/bin
126 23:06:37.413862 makedir: /var/lib/lava/dispatcher/tmp/12395367/lava-overlay-1a5dhpcj/lava-12395367/tests
127 23:06:37.414003 makedir: /var/lib/lava/dispatcher/tmp/12395367/lava-overlay-1a5dhpcj/lava-12395367/results
128 23:06:37.414138 Creating /var/lib/lava/dispatcher/tmp/12395367/lava-overlay-1a5dhpcj/lava-12395367/bin/lava-add-keys
129 23:06:37.414307 Creating /var/lib/lava/dispatcher/tmp/12395367/lava-overlay-1a5dhpcj/lava-12395367/bin/lava-add-sources
130 23:06:37.414457 Creating /var/lib/lava/dispatcher/tmp/12395367/lava-overlay-1a5dhpcj/lava-12395367/bin/lava-background-process-start
131 23:06:37.414604 Creating /var/lib/lava/dispatcher/tmp/12395367/lava-overlay-1a5dhpcj/lava-12395367/bin/lava-background-process-stop
132 23:06:37.414752 Creating /var/lib/lava/dispatcher/tmp/12395367/lava-overlay-1a5dhpcj/lava-12395367/bin/lava-common-functions
133 23:06:37.414925 Creating /var/lib/lava/dispatcher/tmp/12395367/lava-overlay-1a5dhpcj/lava-12395367/bin/lava-echo-ipv4
134 23:06:37.415097 Creating /var/lib/lava/dispatcher/tmp/12395367/lava-overlay-1a5dhpcj/lava-12395367/bin/lava-install-packages
135 23:06:37.415268 Creating /var/lib/lava/dispatcher/tmp/12395367/lava-overlay-1a5dhpcj/lava-12395367/bin/lava-installed-packages
136 23:06:37.415439 Creating /var/lib/lava/dispatcher/tmp/12395367/lava-overlay-1a5dhpcj/lava-12395367/bin/lava-os-build
137 23:06:37.415611 Creating /var/lib/lava/dispatcher/tmp/12395367/lava-overlay-1a5dhpcj/lava-12395367/bin/lava-probe-channel
138 23:06:37.415785 Creating /var/lib/lava/dispatcher/tmp/12395367/lava-overlay-1a5dhpcj/lava-12395367/bin/lava-probe-ip
139 23:06:37.415954 Creating /var/lib/lava/dispatcher/tmp/12395367/lava-overlay-1a5dhpcj/lava-12395367/bin/lava-target-ip
140 23:06:37.416098 Creating /var/lib/lava/dispatcher/tmp/12395367/lava-overlay-1a5dhpcj/lava-12395367/bin/lava-target-mac
141 23:06:37.416241 Creating /var/lib/lava/dispatcher/tmp/12395367/lava-overlay-1a5dhpcj/lava-12395367/bin/lava-target-storage
142 23:06:37.416391 Creating /var/lib/lava/dispatcher/tmp/12395367/lava-overlay-1a5dhpcj/lava-12395367/bin/lava-test-case
143 23:06:37.416538 Creating /var/lib/lava/dispatcher/tmp/12395367/lava-overlay-1a5dhpcj/lava-12395367/bin/lava-test-event
144 23:06:37.416717 Creating /var/lib/lava/dispatcher/tmp/12395367/lava-overlay-1a5dhpcj/lava-12395367/bin/lava-test-feedback
145 23:06:37.416864 Creating /var/lib/lava/dispatcher/tmp/12395367/lava-overlay-1a5dhpcj/lava-12395367/bin/lava-test-raise
146 23:06:37.417013 Creating /var/lib/lava/dispatcher/tmp/12395367/lava-overlay-1a5dhpcj/lava-12395367/bin/lava-test-reference
147 23:06:37.417183 Creating /var/lib/lava/dispatcher/tmp/12395367/lava-overlay-1a5dhpcj/lava-12395367/bin/lava-test-runner
148 23:06:37.417328 Creating /var/lib/lava/dispatcher/tmp/12395367/lava-overlay-1a5dhpcj/lava-12395367/bin/lava-test-set
149 23:06:37.417474 Creating /var/lib/lava/dispatcher/tmp/12395367/lava-overlay-1a5dhpcj/lava-12395367/bin/lava-test-shell
150 23:06:37.417624 Updating /var/lib/lava/dispatcher/tmp/12395367/lava-overlay-1a5dhpcj/lava-12395367/bin/lava-install-packages (oe)
151 23:06:37.417800 Updating /var/lib/lava/dispatcher/tmp/12395367/lava-overlay-1a5dhpcj/lava-12395367/bin/lava-installed-packages (oe)
152 23:06:37.417968 Creating /var/lib/lava/dispatcher/tmp/12395367/lava-overlay-1a5dhpcj/lava-12395367/environment
153 23:06:37.418109 LAVA metadata
154 23:06:37.418193 - LAVA_JOB_ID=12395367
155 23:06:37.418273 - LAVA_DISPATCHER_IP=192.168.201.1
156 23:06:37.418423 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:53) [common]
157 23:06:37.418523 skipped lava-vland-overlay
158 23:06:37.418643 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 23:06:37.418767 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:53) [common]
160 23:06:37.418870 skipped lava-multinode-overlay
161 23:06:37.418988 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 23:06:37.419119 start: 1.5.2.3 test-definition (timeout 00:09:53) [common]
163 23:06:37.419233 Loading test definitions
164 23:06:37.419373 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:53) [common]
165 23:06:37.419487 Using /lava-12395367 at stage 0
166 23:06:37.419923 uuid=12395367_1.5.2.3.1 testdef=None
167 23:06:37.420047 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 23:06:37.420175 start: 1.5.2.3.2 test-overlay (timeout 00:09:53) [common]
169 23:06:37.420925 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 23:06:37.421295 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:53) [common]
172 23:06:37.422209 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 23:06:37.422592 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:53) [common]
175 23:06:37.423491 runner path: /var/lib/lava/dispatcher/tmp/12395367/lava-overlay-1a5dhpcj/lava-12395367/0/tests/0_igt-gpu-panfrost test_uuid 12395367_1.5.2.3.1
176 23:06:37.423684 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 23:06:37.423915 Creating lava-test-runner.conf files
179 23:06:37.423998 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12395367/lava-overlay-1a5dhpcj/lava-12395367/0 for stage 0
180 23:06:37.424117 - 0_igt-gpu-panfrost
181 23:06:37.424231 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 23:06:37.424357 start: 1.5.2.4 compress-overlay (timeout 00:09:53) [common]
183 23:06:37.431108 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 23:06:37.431225 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:53) [common]
185 23:06:37.431327 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 23:06:37.431429 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 23:06:37.431538 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:53) [common]
188 23:06:38.840883 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 23:06:38.841295 start: 1.5.4 extract-modules (timeout 00:09:52) [common]
190 23:06:38.841435 extracting modules file /var/lib/lava/dispatcher/tmp/12395367/tftp-deploy-jpgcxkez/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12395367/extract-overlay-ramdisk-fzofc0ly/ramdisk
191 23:06:39.072297 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 23:06:39.072483 start: 1.5.5 apply-overlay-tftp (timeout 00:09:52) [common]
193 23:06:39.072618 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12395367/compress-overlay-a0sl6gsb/overlay-1.5.2.4.tar.gz to ramdisk
194 23:06:39.072754 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12395367/compress-overlay-a0sl6gsb/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12395367/extract-overlay-ramdisk-fzofc0ly/ramdisk
195 23:06:39.079444 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 23:06:39.079576 start: 1.5.6 configure-preseed-file (timeout 00:09:52) [common]
197 23:06:39.079686 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 23:06:39.079800 start: 1.5.7 compress-ramdisk (timeout 00:09:52) [common]
199 23:06:39.079890 Building ramdisk /var/lib/lava/dispatcher/tmp/12395367/extract-overlay-ramdisk-fzofc0ly/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12395367/extract-overlay-ramdisk-fzofc0ly/ramdisk
200 23:06:40.222137 >> 369999 blocks
201 23:06:45.970874 rename /var/lib/lava/dispatcher/tmp/12395367/extract-overlay-ramdisk-fzofc0ly/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12395367/tftp-deploy-jpgcxkez/ramdisk/ramdisk.cpio.gz
202 23:06:45.971360 end: 1.5.7 compress-ramdisk (duration 00:00:07) [common]
203 23:06:45.971497 start: 1.5.8 prepare-kernel (timeout 00:09:45) [common]
204 23:06:45.971619 start: 1.5.8.1 prepare-fit (timeout 00:09:45) [common]
205 23:06:45.971744 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12395367/tftp-deploy-jpgcxkez/kernel/Image'
206 23:06:58.688477 Returned 0 in 12 seconds
207 23:06:58.789348 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12395367/tftp-deploy-jpgcxkez/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12395367/tftp-deploy-jpgcxkez/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12395367/tftp-deploy-jpgcxkez/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12395367/tftp-deploy-jpgcxkez/kernel/image.itb
208 23:06:59.701144 output: FIT description: Kernel Image image with one or more FDT blobs
209 23:06:59.701523 output: Created: Wed Dec 27 23:06:59 2023
210 23:06:59.701625 output: Image 0 (kernel-1)
211 23:06:59.701714 output: Description:
212 23:06:59.701797 output: Created: Wed Dec 27 23:06:59 2023
213 23:06:59.701880 output: Type: Kernel Image
214 23:06:59.701960 output: Compression: lzma compressed
215 23:06:59.702058 output: Data Size: 11480388 Bytes = 11211.32 KiB = 10.95 MiB
216 23:06:59.702154 output: Architecture: AArch64
217 23:06:59.702251 output: OS: Linux
218 23:06:59.702347 output: Load Address: 0x00000000
219 23:06:59.702447 output: Entry Point: 0x00000000
220 23:06:59.702545 output: Hash algo: crc32
221 23:06:59.702641 output: Hash value: a55b2f0b
222 23:06:59.702737 output: Image 1 (fdt-1)
223 23:06:59.702836 output: Description: mt8192-asurada-spherion-r0
224 23:06:59.702929 output: Created: Wed Dec 27 23:06:59 2023
225 23:06:59.703022 output: Type: Flat Device Tree
226 23:06:59.703115 output: Compression: uncompressed
227 23:06:59.703210 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
228 23:06:59.703304 output: Architecture: AArch64
229 23:06:59.703396 output: Hash algo: crc32
230 23:06:59.703487 output: Hash value: cc4352de
231 23:06:59.703578 output: Image 2 (ramdisk-1)
232 23:06:59.703669 output: Description: unavailable
233 23:06:59.703761 output: Created: Wed Dec 27 23:06:59 2023
234 23:06:59.703852 output: Type: RAMDisk Image
235 23:06:59.703942 output: Compression: Unknown Compression
236 23:06:59.704033 output: Data Size: 56431919 Bytes = 55109.30 KiB = 53.82 MiB
237 23:06:59.704124 output: Architecture: AArch64
238 23:06:59.704215 output: OS: Linux
239 23:06:59.704305 output: Load Address: unavailable
240 23:06:59.704395 output: Entry Point: unavailable
241 23:06:59.704485 output: Hash algo: crc32
242 23:06:59.704575 output: Hash value: 58dd4a82
243 23:06:59.704665 output: Default Configuration: 'conf-1'
244 23:06:59.704801 output: Configuration 0 (conf-1)
245 23:06:59.704893 output: Description: mt8192-asurada-spherion-r0
246 23:06:59.704985 output: Kernel: kernel-1
247 23:06:59.705077 output: Init Ramdisk: ramdisk-1
248 23:06:59.705167 output: FDT: fdt-1
249 23:06:59.705258 output: Loadables: kernel-1
250 23:06:59.705349 output:
251 23:06:59.705598 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
252 23:06:59.705741 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
253 23:06:59.705888 end: 1.5 prepare-tftp-overlay (duration 00:00:22) [common]
254 23:06:59.706026 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:31) [common]
255 23:06:59.706138 No LXC device requested
256 23:06:59.706261 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 23:06:59.706391 start: 1.7 deploy-device-env (timeout 00:09:31) [common]
258 23:06:59.706510 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 23:06:59.706620 Checking files for TFTP limit of 4294967296 bytes.
260 23:06:59.707270 end: 1 tftp-deploy (duration 00:00:29) [common]
261 23:06:59.707406 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 23:06:59.707540 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 23:06:59.707718 substitutions:
264 23:06:59.707818 - {DTB}: 12395367/tftp-deploy-jpgcxkez/dtb/mt8192-asurada-spherion-r0.dtb
265 23:06:59.707919 - {INITRD}: 12395367/tftp-deploy-jpgcxkez/ramdisk/ramdisk.cpio.gz
266 23:06:59.708016 - {KERNEL}: 12395367/tftp-deploy-jpgcxkez/kernel/Image
267 23:06:59.708113 - {LAVA_MAC}: None
268 23:06:59.708208 - {PRESEED_CONFIG}: None
269 23:06:59.708302 - {PRESEED_LOCAL}: None
270 23:06:59.708396 - {RAMDISK}: 12395367/tftp-deploy-jpgcxkez/ramdisk/ramdisk.cpio.gz
271 23:06:59.708489 - {ROOT_PART}: None
272 23:06:59.708583 - {ROOT}: None
273 23:06:59.708676 - {SERVER_IP}: 192.168.201.1
274 23:06:59.708811 - {TEE}: None
275 23:06:59.708908 Parsed boot commands:
276 23:06:59.709001 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 23:06:59.709235 Parsed boot commands: tftpboot 192.168.201.1 12395367/tftp-deploy-jpgcxkez/kernel/image.itb 12395367/tftp-deploy-jpgcxkez/kernel/cmdline
278 23:06:59.709362 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 23:06:59.709493 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 23:06:59.709630 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 23:06:59.709758 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 23:06:59.709862 Not connected, no need to disconnect.
283 23:06:59.709979 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 23:06:59.710106 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 23:06:59.710209 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-4'
286 23:06:59.714686 Setting prompt string to ['lava-test: # ']
287 23:06:59.715349 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 23:06:59.715538 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 23:06:59.715727 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 23:06:59.715885 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 23:06:59.716129 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-4' '--port=1' '--command=reboot'
292 23:07:04.861282 >> Command sent successfully.
293 23:07:04.873265 Returned 0 in 5 seconds
294 23:07:04.974489 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 23:07:04.976283 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 23:07:04.976880 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 23:07:04.977372 Setting prompt string to 'Starting depthcharge on Spherion...'
299 23:07:04.977909 Changing prompt to 'Starting depthcharge on Spherion...'
300 23:07:04.978512 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 23:07:04.980124 [Enter `^Ec?' for help]
302 23:07:05.149014
303 23:07:05.149588
304 23:07:05.149991 F0: 102B 0000
305 23:07:05.150350
306 23:07:05.150695 F3: 1001 0000 [0200]
307 23:07:05.151222
308 23:07:05.152418 F3: 1001 0000
309 23:07:05.152926
310 23:07:05.153295 F7: 102D 0000
311 23:07:05.153635
312 23:07:05.153958 F1: 0000 0000
313 23:07:05.156066
314 23:07:05.156528 V0: 0000 0000 [0001]
315 23:07:05.156963
316 23:07:05.157314 00: 0007 8000
317 23:07:05.157666
318 23:07:05.159810 01: 0000 0000
319 23:07:05.160279
320 23:07:05.160644 BP: 0C00 0209 [0000]
321 23:07:05.161045
322 23:07:05.163525 G0: 1182 0000
323 23:07:05.164002
324 23:07:05.164385 EC: 0000 0021 [4000]
325 23:07:05.164777
326 23:07:05.168822 S7: 0000 0000 [0000]
327 23:07:05.169289
328 23:07:05.169653 CC: 0000 0000 [0001]
329 23:07:05.170024
330 23:07:05.170528 T0: 0000 0040 [010F]
331 23:07:05.170909
332 23:07:05.171760 Jump to BL
333 23:07:05.172271
334 23:07:05.195594
335 23:07:05.196158
336 23:07:05.196527
337 23:07:05.202817 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 23:07:05.206392 ARM64: Exception handlers installed.
339 23:07:05.209467 ARM64: Testing exception
340 23:07:05.212795 ARM64: Done test exception
341 23:07:05.219507 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 23:07:05.229430 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 23:07:05.236436 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 23:07:05.246916 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 23:07:05.253256 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 23:07:05.263342 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 23:07:05.274018 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 23:07:05.280622 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 23:07:05.298841 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 23:07:05.302155 WDT: Last reset was cold boot
351 23:07:05.305336 SPI1(PAD0) initialized at 2873684 Hz
352 23:07:05.308823 SPI5(PAD0) initialized at 992727 Hz
353 23:07:05.312141 VBOOT: Loading verstage.
354 23:07:05.318752 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 23:07:05.322249 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 23:07:05.325639 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 23:07:05.328301 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 23:07:05.336637 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 23:07:05.342817 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 23:07:05.353786 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
361 23:07:05.354339
362 23:07:05.354713
363 23:07:05.363591 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 23:07:05.366894 ARM64: Exception handlers installed.
365 23:07:05.370411 ARM64: Testing exception
366 23:07:05.370889 ARM64: Done test exception
367 23:07:05.376924 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 23:07:05.380094 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 23:07:05.394649 Probing TPM: . done!
370 23:07:05.395222 TPM ready after 0 ms
371 23:07:05.401033 Connected to device vid:did:rid of 1ae0:0028:00
372 23:07:05.408318 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
373 23:07:05.452982 Initialized TPM device CR50 revision 0
374 23:07:05.456664 tlcl_send_startup: Startup return code is 0
375 23:07:05.462629 TPM: setup succeeded
376 23:07:05.473591 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 23:07:05.482923 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 23:07:05.492911 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 23:07:05.501677 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 23:07:05.505332 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 23:07:05.508642 in-header: 03 07 00 00 08 00 00 00
382 23:07:05.512146 in-data: aa e4 47 04 13 02 00 00
383 23:07:05.515265 Chrome EC: UHEPI supported
384 23:07:05.522112 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 23:07:05.525437 in-header: 03 9d 00 00 08 00 00 00
386 23:07:05.529079 in-data: 10 20 20 08 00 00 00 00
387 23:07:05.532309 Phase 1
388 23:07:05.535445 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 23:07:05.542118 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 23:07:05.545484 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 23:07:05.549022 Recovery requested (1009000e)
392 23:07:05.552367 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 23:07:05.561811 tlcl_extend: response is 0
394 23:07:05.569788 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 23:07:05.575858 tlcl_extend: response is 0
396 23:07:05.582114 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 23:07:05.602514 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
398 23:07:05.608898 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 23:07:05.609476
400 23:07:05.609854
401 23:07:05.618897 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 23:07:05.622058 ARM64: Exception handlers installed.
403 23:07:05.625632 ARM64: Testing exception
404 23:07:05.626203 ARM64: Done test exception
405 23:07:05.647990 pmic_efuse_setting: Set efuses in 11 msecs
406 23:07:05.651582 pmwrap_interface_init: Select PMIF_VLD_RDY
407 23:07:05.657898 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 23:07:05.661376 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 23:07:05.668829 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 23:07:05.672644 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 23:07:05.676434 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 23:07:05.683633 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 23:07:05.686319 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 23:07:05.689948 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 23:07:05.696627 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 23:07:05.700114 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 23:07:05.706880 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 23:07:05.710025 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 23:07:05.713234 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 23:07:05.719982 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 23:07:05.727348 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 23:07:05.733323 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 23:07:05.736531 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 23:07:05.743423 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 23:07:05.747521 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 23:07:05.754476 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 23:07:05.760764 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 23:07:05.763834 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 23:07:05.770615 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 23:07:05.777501 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 23:07:05.781157 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 23:07:05.787220 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 23:07:05.790878 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 23:07:05.797678 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 23:07:05.800759 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 23:07:05.807749 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 23:07:05.811023 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 23:07:05.817343 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 23:07:05.820948 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 23:07:05.827540 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 23:07:05.830792 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 23:07:05.837502 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 23:07:05.841092 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 23:07:05.847776 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 23:07:05.850943 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 23:07:05.854275 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 23:07:05.860630 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 23:07:05.864119 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 23:07:05.867348 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 23:07:05.874216 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 23:07:05.877605 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 23:07:05.880851 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 23:07:05.887463 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 23:07:05.890525 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 23:07:05.894007 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 23:07:05.897411 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 23:07:05.904044 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 23:07:05.910760 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 23:07:05.920664 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 23:07:05.924574 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 23:07:05.930584 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 23:07:05.940863 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 23:07:05.944018 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 23:07:05.951020 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 23:07:05.953745 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 23:07:05.960773 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x0
467 23:07:05.967596 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 23:07:05.970609 [RTC]rtc_osc_init,62: osc32con val = 0xde70
469 23:07:05.974415 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 23:07:05.985327 [RTC]rtc_get_frequency_meter,154: input=15, output=765
471 23:07:05.994735 [RTC]rtc_get_frequency_meter,154: input=23, output=948
472 23:07:06.004381 [RTC]rtc_get_frequency_meter,154: input=19, output=857
473 23:07:06.013647 [RTC]rtc_get_frequency_meter,154: input=17, output=810
474 23:07:06.023136 [RTC]rtc_get_frequency_meter,154: input=16, output=786
475 23:07:06.033246 [RTC]rtc_get_frequency_meter,154: input=16, output=788
476 23:07:06.042450 [RTC]rtc_get_frequency_meter,154: input=17, output=810
477 23:07:06.045426 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
478 23:07:06.052727 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
479 23:07:06.056264 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 23:07:06.059625 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
481 23:07:06.065852 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 23:07:06.069333 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
483 23:07:06.072212 ADC[4]: Raw value=670800 ID=5
484 23:07:06.072678 ADC[3]: Raw value=212549 ID=1
485 23:07:06.076587 RAM Code: 0x51
486 23:07:06.079239 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 23:07:06.086621 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 23:07:06.092649 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-4GB' @0x75180 size 0x8 in mcache @0x00107f9c
489 23:07:06.099560 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
490 23:07:06.103132 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 23:07:06.105897 in-header: 03 07 00 00 08 00 00 00
492 23:07:06.109189 in-data: aa e4 47 04 13 02 00 00
493 23:07:06.112725 Chrome EC: UHEPI supported
494 23:07:06.119396 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 23:07:06.122748 in-header: 03 d5 00 00 08 00 00 00
496 23:07:06.126216 in-data: 98 20 60 08 00 00 00 00
497 23:07:06.129086 MRC: failed to locate region type 0.
498 23:07:06.132435 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 23:07:06.135632 DRAM-K: Running full calibration
500 23:07:06.142562 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
501 23:07:06.145624 header.status = 0x0
502 23:07:06.149542 header.version = 0x6 (expected: 0x6)
503 23:07:06.152769 header.size = 0xd00 (expected: 0xd00)
504 23:07:06.153350 header.flags = 0x0
505 23:07:06.159626 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 23:07:06.177048 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
507 23:07:06.184021 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 23:07:06.187088 dram_init: ddr_geometry: 0
509 23:07:06.190236 [EMI] MDL number = 0
510 23:07:06.190803 [EMI] Get MDL freq = 0
511 23:07:06.193523 dram_init: ddr_type: 0
512 23:07:06.193995 is_discrete_lpddr4: 1
513 23:07:06.197084 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 23:07:06.197653
515 23:07:06.200853
516 23:07:06.201434 [Bian_co] ETT version 0.0.0.1
517 23:07:06.207557 dram_type 6, R0 cbt_mode 0, R1 cbt_mode 0 VENDOR=6
518 23:07:06.208114
519 23:07:06.210570 dramc_set_vcore_voltage set vcore to 650000
520 23:07:06.211043 Read voltage for 800, 4
521 23:07:06.214134 Vio18 = 0
522 23:07:06.214699 Vcore = 650000
523 23:07:06.215075 Vdram = 0
524 23:07:06.217669 Vddq = 0
525 23:07:06.218231 Vmddr = 0
526 23:07:06.221055 dram_init: config_dvfs: 1
527 23:07:06.224328 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 23:07:06.231314 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 23:07:06.234336 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
530 23:07:06.237401 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
531 23:07:06.241353 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
532 23:07:06.244159 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
533 23:07:06.247878 MEM_TYPE=3, freq_sel=18
534 23:07:06.251058 sv_algorithm_assistance_LP4_1600
535 23:07:06.254351 ============ PULL DRAM RESETB DOWN ============
536 23:07:06.257322 ========== PULL DRAM RESETB DOWN end =========
537 23:07:06.263952 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 23:07:06.267112 ===================================
539 23:07:06.267725 LPDDR4 DRAM CONFIGURATION
540 23:07:06.270734 ===================================
541 23:07:06.273910 EX_ROW_EN[0] = 0x0
542 23:07:06.277214 EX_ROW_EN[1] = 0x0
543 23:07:06.277686 LP4Y_EN = 0x0
544 23:07:06.280771 WORK_FSP = 0x0
545 23:07:06.281392 WL = 0x2
546 23:07:06.284383 RL = 0x2
547 23:07:06.284995 BL = 0x2
548 23:07:06.287478 RPST = 0x0
549 23:07:06.288003 RD_PRE = 0x0
550 23:07:06.290597 WR_PRE = 0x1
551 23:07:06.291026 WR_PST = 0x0
552 23:07:06.294065 DBI_WR = 0x0
553 23:07:06.294574 DBI_RD = 0x0
554 23:07:06.297494 OTF = 0x1
555 23:07:06.300900 ===================================
556 23:07:06.304228 ===================================
557 23:07:06.304770 ANA top config
558 23:07:06.307394 ===================================
559 23:07:06.310532 DLL_ASYNC_EN = 0
560 23:07:06.314108 ALL_SLAVE_EN = 1
561 23:07:06.314618 NEW_RANK_MODE = 1
562 23:07:06.317342 DLL_IDLE_MODE = 1
563 23:07:06.320612 LP45_APHY_COMB_EN = 1
564 23:07:06.324162 TX_ODT_DIS = 1
565 23:07:06.324668 NEW_8X_MODE = 1
566 23:07:06.327624 ===================================
567 23:07:06.330967 ===================================
568 23:07:06.334332 data_rate = 1600
569 23:07:06.337667 CKR = 1
570 23:07:06.340901 DQ_P2S_RATIO = 8
571 23:07:06.344286 ===================================
572 23:07:06.347795 CA_P2S_RATIO = 8
573 23:07:06.351451 DQ_CA_OPEN = 0
574 23:07:06.351987 DQ_SEMI_OPEN = 0
575 23:07:06.354647 CA_SEMI_OPEN = 0
576 23:07:06.357859 CA_FULL_RATE = 0
577 23:07:06.361180 DQ_CKDIV4_EN = 1
578 23:07:06.364066 CA_CKDIV4_EN = 1
579 23:07:06.367508 CA_PREDIV_EN = 0
580 23:07:06.367985 PH8_DLY = 0
581 23:07:06.371029 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 23:07:06.374620 DQ_AAMCK_DIV = 4
583 23:07:06.377799 CA_AAMCK_DIV = 4
584 23:07:06.381426 CA_ADMCK_DIV = 4
585 23:07:06.384174 DQ_TRACK_CA_EN = 0
586 23:07:06.384647 CA_PICK = 800
587 23:07:06.387641 CA_MCKIO = 800
588 23:07:06.391062 MCKIO_SEMI = 0
589 23:07:06.394645 PLL_FREQ = 3068
590 23:07:06.397714 DQ_UI_PI_RATIO = 32
591 23:07:06.400964 CA_UI_PI_RATIO = 0
592 23:07:06.404365 ===================================
593 23:07:06.407725 ===================================
594 23:07:06.408213 memory_type:LPDDR4
595 23:07:06.411177 GP_NUM : 10
596 23:07:06.414361 SRAM_EN : 1
597 23:07:06.414828 MD32_EN : 0
598 23:07:06.418021 ===================================
599 23:07:06.421093 [ANA_INIT] >>>>>>>>>>>>>>
600 23:07:06.424616 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 23:07:06.428191 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 23:07:06.431331 ===================================
603 23:07:06.434762 data_rate = 1600,PCW = 0X7600
604 23:07:06.438243 ===================================
605 23:07:06.441106 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 23:07:06.444977 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 23:07:06.451132 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 23:07:06.454307 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 23:07:06.457653 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 23:07:06.461073 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 23:07:06.464537 [ANA_INIT] flow start
612 23:07:06.467531 [ANA_INIT] PLL >>>>>>>>
613 23:07:06.467999 [ANA_INIT] PLL <<<<<<<<
614 23:07:06.471340 [ANA_INIT] MIDPI >>>>>>>>
615 23:07:06.474951 [ANA_INIT] MIDPI <<<<<<<<
616 23:07:06.477916 [ANA_INIT] DLL >>>>>>>>
617 23:07:06.478479 [ANA_INIT] flow end
618 23:07:06.481301 ============ LP4 DIFF to SE enter ============
619 23:07:06.487725 ============ LP4 DIFF to SE exit ============
620 23:07:06.488297 [ANA_INIT] <<<<<<<<<<<<<
621 23:07:06.490879 [Flow] Enable top DCM control >>>>>
622 23:07:06.494439 [Flow] Enable top DCM control <<<<<
623 23:07:06.498160 Enable DLL master slave shuffle
624 23:07:06.504306 ==============================================================
625 23:07:06.504931 Gating Mode config
626 23:07:06.511370 ==============================================================
627 23:07:06.514197 Config description:
628 23:07:06.520877 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 23:07:06.527732 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 23:07:06.534483 SELPH_MODE 0: By rank 1: By Phase
631 23:07:06.540918 ==============================================================
632 23:07:06.541462 GAT_TRACK_EN = 1
633 23:07:06.544287 RX_GATING_MODE = 2
634 23:07:06.547932 RX_GATING_TRACK_MODE = 2
635 23:07:06.551047 SELPH_MODE = 1
636 23:07:06.554331 PICG_EARLY_EN = 1
637 23:07:06.557952 VALID_LAT_VALUE = 1
638 23:07:06.564272 ==============================================================
639 23:07:06.567485 Enter into Gating configuration >>>>
640 23:07:06.571085 Exit from Gating configuration <<<<
641 23:07:06.574226 Enter into DVFS_PRE_config >>>>>
642 23:07:06.584071 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 23:07:06.587632 Exit from DVFS_PRE_config <<<<<
644 23:07:06.591172 Enter into PICG configuration >>>>
645 23:07:06.594799 Exit from PICG configuration <<<<
646 23:07:06.597719 [RX_INPUT] configuration >>>>>
647 23:07:06.598295 [RX_INPUT] configuration <<<<<
648 23:07:06.604337 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 23:07:06.611238 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 23:07:06.614428 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 23:07:06.620893 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 23:07:06.627498 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 23:07:06.634424 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 23:07:06.637568 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 23:07:06.641561 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 23:07:06.647761 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 23:07:06.650790 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 23:07:06.654351 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 23:07:06.657865 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 23:07:06.661224 ===================================
661 23:07:06.664124 LPDDR4 DRAM CONFIGURATION
662 23:07:06.667566 ===================================
663 23:07:06.670961 EX_ROW_EN[0] = 0x0
664 23:07:06.671430 EX_ROW_EN[1] = 0x0
665 23:07:06.674283 LP4Y_EN = 0x0
666 23:07:06.674751 WORK_FSP = 0x0
667 23:07:06.678095 WL = 0x2
668 23:07:06.678639 RL = 0x2
669 23:07:06.680931 BL = 0x2
670 23:07:06.681398 RPST = 0x0
671 23:07:06.684023 RD_PRE = 0x0
672 23:07:06.684487 WR_PRE = 0x1
673 23:07:06.688037 WR_PST = 0x0
674 23:07:06.688583 DBI_WR = 0x0
675 23:07:06.690935 DBI_RD = 0x0
676 23:07:06.691512 OTF = 0x1
677 23:07:06.694472 ===================================
678 23:07:06.701274 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 23:07:06.703989 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 23:07:06.707802 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 23:07:06.710799 ===================================
682 23:07:06.714494 LPDDR4 DRAM CONFIGURATION
683 23:07:06.717811 ===================================
684 23:07:06.720845 EX_ROW_EN[0] = 0x10
685 23:07:06.721282 EX_ROW_EN[1] = 0x0
686 23:07:06.724082 LP4Y_EN = 0x0
687 23:07:06.724504 WORK_FSP = 0x0
688 23:07:06.727751 WL = 0x2
689 23:07:06.728173 RL = 0x2
690 23:07:06.730917 BL = 0x2
691 23:07:06.731340 RPST = 0x0
692 23:07:06.734070 RD_PRE = 0x0
693 23:07:06.734494 WR_PRE = 0x1
694 23:07:06.737825 WR_PST = 0x0
695 23:07:06.738247 DBI_WR = 0x0
696 23:07:06.741013 DBI_RD = 0x0
697 23:07:06.741434 OTF = 0x1
698 23:07:06.744210 ===================================
699 23:07:06.750895 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 23:07:06.755367 nWR fixed to 40
701 23:07:06.758966 [ModeRegInit_LP4] CH0 RK0
702 23:07:06.759489 [ModeRegInit_LP4] CH0 RK1
703 23:07:06.762000 [ModeRegInit_LP4] CH1 RK0
704 23:07:06.765312 [ModeRegInit_LP4] CH1 RK1
705 23:07:06.766089 match AC timing 12
706 23:07:06.771880 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 0
707 23:07:06.775666 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 23:07:06.778795 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 23:07:06.785296 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 23:07:06.788701 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 23:07:06.789253 [EMI DOE] emi_dcm 0
712 23:07:06.795419 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 23:07:06.795983 ==
714 23:07:06.798390 Dram Type= 6, Freq= 0, CH_0, rank 0
715 23:07:06.801721 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
716 23:07:06.802161 ==
717 23:07:06.808338 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 23:07:06.815255 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 23:07:06.823046 [CA 0] Center 37 (7~68) winsize 62
720 23:07:06.825980 [CA 1] Center 37 (7~68) winsize 62
721 23:07:06.829202 [CA 2] Center 35 (4~66) winsize 63
722 23:07:06.833366 [CA 3] Center 35 (4~66) winsize 63
723 23:07:06.835842 [CA 4] Center 34 (3~65) winsize 63
724 23:07:06.839726 [CA 5] Center 33 (3~64) winsize 62
725 23:07:06.840263
726 23:07:06.842829 [CmdBusTrainingLP45] Vref(ca) range 1: 34
727 23:07:06.843402
728 23:07:06.845805 [CATrainingPosCal] consider 1 rank data
729 23:07:06.849029 u2DelayCellTimex100 = 270/100 ps
730 23:07:06.852663 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
731 23:07:06.855865 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
732 23:07:06.863126 CA2 delay=35 (4~66),Diff = 2 PI (14 cell)
733 23:07:06.865908 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
734 23:07:06.869093 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
735 23:07:06.872672 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
736 23:07:06.873132
737 23:07:06.876266 CA PerBit enable=1, Macro0, CA PI delay=33
738 23:07:06.876688
739 23:07:06.879308 [CBTSetCACLKResult] CA Dly = 33
740 23:07:06.879730 CS Dly: 6 (0~37)
741 23:07:06.882586 ==
742 23:07:06.883011 Dram Type= 6, Freq= 0, CH_0, rank 1
743 23:07:06.889235 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
744 23:07:06.889753 ==
745 23:07:06.892880 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 23:07:06.899147 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 23:07:06.908857 [CA 0] Center 37 (6~68) winsize 63
748 23:07:06.912022 [CA 1] Center 37 (6~68) winsize 63
749 23:07:06.915539 [CA 2] Center 35 (4~66) winsize 63
750 23:07:06.918707 [CA 3] Center 34 (4~65) winsize 62
751 23:07:06.921998 [CA 4] Center 33 (3~64) winsize 62
752 23:07:06.925237 [CA 5] Center 33 (3~64) winsize 62
753 23:07:06.925796
754 23:07:06.928585 [CmdBusTrainingLP45] Vref(ca) range 1: 34
755 23:07:06.929174
756 23:07:06.931817 [CATrainingPosCal] consider 2 rank data
757 23:07:06.935388 u2DelayCellTimex100 = 270/100 ps
758 23:07:06.938709 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
759 23:07:06.942176 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
760 23:07:06.948550 CA2 delay=35 (4~66),Diff = 2 PI (14 cell)
761 23:07:06.951737 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
762 23:07:06.955405 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
763 23:07:06.958372 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
764 23:07:06.958839
765 23:07:06.961697 CA PerBit enable=1, Macro0, CA PI delay=33
766 23:07:06.962181
767 23:07:06.965077 [CBTSetCACLKResult] CA Dly = 33
768 23:07:06.965544 CS Dly: 6 (0~38)
769 23:07:06.965915
770 23:07:06.968821 ----->DramcWriteLeveling(PI) begin...
771 23:07:06.971890 ==
772 23:07:06.975245 Dram Type= 6, Freq= 0, CH_0, rank 0
773 23:07:06.978409 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
774 23:07:06.978879 ==
775 23:07:06.981847 Write leveling (Byte 0): 31 => 31
776 23:07:06.985200 Write leveling (Byte 1): 27 => 27
777 23:07:06.988529 DramcWriteLeveling(PI) end<-----
778 23:07:06.989033
779 23:07:06.989405 ==
780 23:07:06.991889 Dram Type= 6, Freq= 0, CH_0, rank 0
781 23:07:06.995096 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
782 23:07:06.995620 ==
783 23:07:06.998530 [Gating] SW mode calibration
784 23:07:07.005062 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 23:07:07.008675 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 23:07:07.015450 0 6 0 | B1->B0 | 3434 3232 | 0 1 | (0 0) (1 0)
787 23:07:07.018779 0 6 4 | B1->B0 | 2525 2525 | 0 0 | (0 0) (1 0)
788 23:07:07.022177 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 23:07:07.028640 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 23:07:07.031955 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 23:07:07.035141 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 23:07:07.042115 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 23:07:07.045431 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 23:07:07.048622 0 7 0 | B1->B0 | 2424 2b2b | 0 1 | (0 0) (0 0)
795 23:07:07.055687 0 7 4 | B1->B0 | 3838 4242 | 1 0 | (0 0) (0 0)
796 23:07:07.058766 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
797 23:07:07.062082 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
798 23:07:07.068654 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
799 23:07:07.072659 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
800 23:07:07.075508 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
801 23:07:07.078950 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
802 23:07:07.085708 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
803 23:07:07.088694 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
804 23:07:07.091938 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
805 23:07:07.098715 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
806 23:07:07.102065 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
807 23:07:07.105560 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
808 23:07:07.111972 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
809 23:07:07.115239 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
810 23:07:07.118748 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
811 23:07:07.125321 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
812 23:07:07.128985 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
813 23:07:07.132130 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
814 23:07:07.138712 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
815 23:07:07.142014 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
816 23:07:07.145430 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
817 23:07:07.152054 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
818 23:07:07.155476 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
819 23:07:07.158391 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
820 23:07:07.162205 Total UI for P1: 0, mck2ui 16
821 23:07:07.165086 best dqsien dly found for B0: ( 0, 10, 0)
822 23:07:07.168986 Total UI for P1: 0, mck2ui 16
823 23:07:07.172049 best dqsien dly found for B1: ( 0, 10, 0)
824 23:07:07.175303 best DQS0 dly(MCK, UI, PI) = (0, 10, 0)
825 23:07:07.178922 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
826 23:07:07.179391
827 23:07:07.182118 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 0)
828 23:07:07.188497 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
829 23:07:07.189051 [Gating] SW calibration Done
830 23:07:07.189429 ==
831 23:07:07.192061 Dram Type= 6, Freq= 0, CH_0, rank 0
832 23:07:07.199258 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
833 23:07:07.199760 ==
834 23:07:07.200102 RX Vref Scan: 0
835 23:07:07.200473
836 23:07:07.202646 RX Vref 0 -> 0, step: 1
837 23:07:07.203106
838 23:07:07.206172 RX Delay -130 -> 252, step: 16
839 23:07:07.209434 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
840 23:07:07.212938 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
841 23:07:07.216280 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
842 23:07:07.219144 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
843 23:07:07.226099 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
844 23:07:07.229355 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
845 23:07:07.232951 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
846 23:07:07.236045 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
847 23:07:07.239795 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
848 23:07:07.242765 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
849 23:07:07.249476 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
850 23:07:07.252608 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
851 23:07:07.256243 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
852 23:07:07.259619 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
853 23:07:07.265818 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
854 23:07:07.269349 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
855 23:07:07.270053 ==
856 23:07:07.272446 Dram Type= 6, Freq= 0, CH_0, rank 0
857 23:07:07.275816 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
858 23:07:07.276282 ==
859 23:07:07.279761 DQS Delay:
860 23:07:07.280331 DQS0 = 0, DQS1 = 0
861 23:07:07.280701 DQM Delay:
862 23:07:07.282616 DQM0 = 81, DQM1 = 73
863 23:07:07.283180 DQ Delay:
864 23:07:07.286139 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
865 23:07:07.289200 DQ4 =77, DQ5 =69, DQ6 =93, DQ7 =93
866 23:07:07.292376 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =69
867 23:07:07.295844 DQ12 =85, DQ13 =77, DQ14 =85, DQ15 =85
868 23:07:07.296409
869 23:07:07.296841
870 23:07:07.297199 ==
871 23:07:07.298951 Dram Type= 6, Freq= 0, CH_0, rank 0
872 23:07:07.305971 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
873 23:07:07.306548 ==
874 23:07:07.306930
875 23:07:07.307276
876 23:07:07.307639 TX Vref Scan disable
877 23:07:07.309245 == TX Byte 0 ==
878 23:07:07.312618 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
879 23:07:07.315992 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
880 23:07:07.318887 == TX Byte 1 ==
881 23:07:07.322881 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
882 23:07:07.326315 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
883 23:07:07.329181 ==
884 23:07:07.332637 Dram Type= 6, Freq= 0, CH_0, rank 0
885 23:07:07.335867 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
886 23:07:07.336439 ==
887 23:07:07.348910 TX Vref=22, minBit 0, minWin=27, winSum=441
888 23:07:07.352114 TX Vref=24, minBit 4, minWin=27, winSum=448
889 23:07:07.355469 TX Vref=26, minBit 11, minWin=27, winSum=449
890 23:07:07.358802 TX Vref=28, minBit 11, minWin=27, winSum=451
891 23:07:07.361816 TX Vref=30, minBit 0, minWin=28, winSum=454
892 23:07:07.368697 TX Vref=32, minBit 5, minWin=27, winSum=452
893 23:07:07.372268 [TxChooseVref] Worse bit 0, Min win 28, Win sum 454, Final Vref 30
894 23:07:07.372940
895 23:07:07.375315 Final TX Range 1 Vref 30
896 23:07:07.375823
897 23:07:07.376192 ==
898 23:07:07.378826 Dram Type= 6, Freq= 0, CH_0, rank 0
899 23:07:07.382141 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
900 23:07:07.382728 ==
901 23:07:07.383103
902 23:07:07.385181
903 23:07:07.385646 TX Vref Scan disable
904 23:07:07.388570 == TX Byte 0 ==
905 23:07:07.392000 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
906 23:07:07.395655 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
907 23:07:07.398504 == TX Byte 1 ==
908 23:07:07.402104 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
909 23:07:07.408365 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
910 23:07:07.408875
911 23:07:07.409290 [DATLAT]
912 23:07:07.409679 Freq=800, CH0 RK0
913 23:07:07.410025
914 23:07:07.411692 DATLAT Default: 0xa
915 23:07:07.412160 0, 0xFFFF, sum = 0
916 23:07:07.415363 1, 0xFFFF, sum = 0
917 23:07:07.415934 2, 0xFFFF, sum = 0
918 23:07:07.418427 3, 0xFFFF, sum = 0
919 23:07:07.422148 4, 0xFFFF, sum = 0
920 23:07:07.422967 5, 0xFFFF, sum = 0
921 23:07:07.425243 6, 0xFFFF, sum = 0
922 23:07:07.425881 7, 0xFFFF, sum = 0
923 23:07:07.426477 8, 0x0, sum = 1
924 23:07:07.428881 9, 0x0, sum = 2
925 23:07:07.429592 10, 0x0, sum = 3
926 23:07:07.431989 11, 0x0, sum = 4
927 23:07:07.432895 best_step = 9
928 23:07:07.433349
929 23:07:07.433703 ==
930 23:07:07.435094 Dram Type= 6, Freq= 0, CH_0, rank 0
931 23:07:07.442147 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
932 23:07:07.442717 ==
933 23:07:07.443092 RX Vref Scan: 1
934 23:07:07.443438
935 23:07:07.445293 Set Vref Range= 32 -> 127
936 23:07:07.445841
937 23:07:07.448498 RX Vref 32 -> 127, step: 1
938 23:07:07.449157
939 23:07:07.451709 RX Delay -111 -> 252, step: 8
940 23:07:07.452202
941 23:07:07.452817 Set Vref, RX VrefLevel [Byte0]: 32
942 23:07:07.455328 [Byte1]: 32
943 23:07:07.459554
944 23:07:07.460054 Set Vref, RX VrefLevel [Byte0]: 33
945 23:07:07.463176 [Byte1]: 33
946 23:07:07.467327
947 23:07:07.468076 Set Vref, RX VrefLevel [Byte0]: 34
948 23:07:07.470700 [Byte1]: 34
949 23:07:07.475316
950 23:07:07.475938 Set Vref, RX VrefLevel [Byte0]: 35
951 23:07:07.478064 [Byte1]: 35
952 23:07:07.482812
953 23:07:07.483368 Set Vref, RX VrefLevel [Byte0]: 36
954 23:07:07.486004 [Byte1]: 36
955 23:07:07.490311
956 23:07:07.490901 Set Vref, RX VrefLevel [Byte0]: 37
957 23:07:07.493720 [Byte1]: 37
958 23:07:07.497731
959 23:07:07.498261 Set Vref, RX VrefLevel [Byte0]: 38
960 23:07:07.501052 [Byte1]: 38
961 23:07:07.505254
962 23:07:07.505720 Set Vref, RX VrefLevel [Byte0]: 39
963 23:07:07.508753 [Byte1]: 39
964 23:07:07.513126
965 23:07:07.513609 Set Vref, RX VrefLevel [Byte0]: 40
966 23:07:07.516651 [Byte1]: 40
967 23:07:07.520919
968 23:07:07.521589 Set Vref, RX VrefLevel [Byte0]: 41
969 23:07:07.524317 [Byte1]: 41
970 23:07:07.528352
971 23:07:07.528971 Set Vref, RX VrefLevel [Byte0]: 42
972 23:07:07.531606 [Byte1]: 42
973 23:07:07.536459
974 23:07:07.537081 Set Vref, RX VrefLevel [Byte0]: 43
975 23:07:07.539701 [Byte1]: 43
976 23:07:07.544009
977 23:07:07.544581 Set Vref, RX VrefLevel [Byte0]: 44
978 23:07:07.547141 [Byte1]: 44
979 23:07:07.551539
980 23:07:07.552106 Set Vref, RX VrefLevel [Byte0]: 45
981 23:07:07.554514 [Byte1]: 45
982 23:07:07.559300
983 23:07:07.559881 Set Vref, RX VrefLevel [Byte0]: 46
984 23:07:07.562285 [Byte1]: 46
985 23:07:07.566480
986 23:07:07.566937 Set Vref, RX VrefLevel [Byte0]: 47
987 23:07:07.570293 [Byte1]: 47
988 23:07:07.574302
989 23:07:07.574765 Set Vref, RX VrefLevel [Byte0]: 48
990 23:07:07.577408 [Byte1]: 48
991 23:07:07.582022
992 23:07:07.582498 Set Vref, RX VrefLevel [Byte0]: 49
993 23:07:07.585362 [Byte1]: 49
994 23:07:07.589451
995 23:07:07.590014 Set Vref, RX VrefLevel [Byte0]: 50
996 23:07:07.592840 [Byte1]: 50
997 23:07:07.597345
998 23:07:07.597951 Set Vref, RX VrefLevel [Byte0]: 51
999 23:07:07.601043 [Byte1]: 51
1000 23:07:07.604816
1001 23:07:07.605383 Set Vref, RX VrefLevel [Byte0]: 52
1002 23:07:07.608426 [Byte1]: 52
1003 23:07:07.612922
1004 23:07:07.613486 Set Vref, RX VrefLevel [Byte0]: 53
1005 23:07:07.616077 [Byte1]: 53
1006 23:07:07.619934
1007 23:07:07.620434 Set Vref, RX VrefLevel [Byte0]: 54
1008 23:07:07.623621 [Byte1]: 54
1009 23:07:07.627716
1010 23:07:07.628189 Set Vref, RX VrefLevel [Byte0]: 55
1011 23:07:07.630977 [Byte1]: 55
1012 23:07:07.635334
1013 23:07:07.635899 Set Vref, RX VrefLevel [Byte0]: 56
1014 23:07:07.638536 [Byte1]: 56
1015 23:07:07.643308
1016 23:07:07.643878 Set Vref, RX VrefLevel [Byte0]: 57
1017 23:07:07.646243 [Byte1]: 57
1018 23:07:07.650851
1019 23:07:07.651421 Set Vref, RX VrefLevel [Byte0]: 58
1020 23:07:07.654018 [Byte1]: 58
1021 23:07:07.658766
1022 23:07:07.659329 Set Vref, RX VrefLevel [Byte0]: 59
1023 23:07:07.661714 [Byte1]: 59
1024 23:07:07.665918
1025 23:07:07.666501 Set Vref, RX VrefLevel [Byte0]: 60
1026 23:07:07.668988 [Byte1]: 60
1027 23:07:07.673420
1028 23:07:07.673882 Set Vref, RX VrefLevel [Byte0]: 61
1029 23:07:07.676911 [Byte1]: 61
1030 23:07:07.681168
1031 23:07:07.681632 Set Vref, RX VrefLevel [Byte0]: 62
1032 23:07:07.684594 [Byte1]: 62
1033 23:07:07.689183
1034 23:07:07.689741 Set Vref, RX VrefLevel [Byte0]: 63
1035 23:07:07.692257 [Byte1]: 63
1036 23:07:07.696919
1037 23:07:07.697446 Set Vref, RX VrefLevel [Byte0]: 64
1038 23:07:07.700549 [Byte1]: 64
1039 23:07:07.704328
1040 23:07:07.704837 Set Vref, RX VrefLevel [Byte0]: 65
1041 23:07:07.707700 [Byte1]: 65
1042 23:07:07.712058
1043 23:07:07.712669 Set Vref, RX VrefLevel [Byte0]: 66
1044 23:07:07.715334 [Byte1]: 66
1045 23:07:07.719418
1046 23:07:07.719899 Set Vref, RX VrefLevel [Byte0]: 67
1047 23:07:07.722655 [Byte1]: 67
1048 23:07:07.727317
1049 23:07:07.727781 Set Vref, RX VrefLevel [Byte0]: 68
1050 23:07:07.730498 [Byte1]: 68
1051 23:07:07.735656
1052 23:07:07.736205 Set Vref, RX VrefLevel [Byte0]: 69
1053 23:07:07.738572 [Byte1]: 69
1054 23:07:07.742492
1055 23:07:07.743036 Set Vref, RX VrefLevel [Byte0]: 70
1056 23:07:07.745722 [Byte1]: 70
1057 23:07:07.749945
1058 23:07:07.750467 Set Vref, RX VrefLevel [Byte0]: 71
1059 23:07:07.753392 [Byte1]: 71
1060 23:07:07.757829
1061 23:07:07.758400 Set Vref, RX VrefLevel [Byte0]: 72
1062 23:07:07.760841 [Byte1]: 72
1063 23:07:07.765170
1064 23:07:07.765633 Set Vref, RX VrefLevel [Byte0]: 73
1065 23:07:07.768841 [Byte1]: 73
1066 23:07:07.772858
1067 23:07:07.773457 Set Vref, RX VrefLevel [Byte0]: 74
1068 23:07:07.776554 [Byte1]: 74
1069 23:07:07.780655
1070 23:07:07.781261 Final RX Vref Byte 0 = 52 to rank0
1071 23:07:07.784249 Final RX Vref Byte 1 = 56 to rank0
1072 23:07:07.787500 Final RX Vref Byte 0 = 52 to rank1
1073 23:07:07.790974 Final RX Vref Byte 1 = 56 to rank1==
1074 23:07:07.794263 Dram Type= 6, Freq= 0, CH_0, rank 0
1075 23:07:07.800673 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1076 23:07:07.801290 ==
1077 23:07:07.801658 DQS Delay:
1078 23:07:07.801997 DQS0 = 0, DQS1 = 0
1079 23:07:07.804153 DQM Delay:
1080 23:07:07.804607 DQM0 = 84, DQM1 = 73
1081 23:07:07.807233 DQ Delay:
1082 23:07:07.810386 DQ0 =80, DQ1 =84, DQ2 =84, DQ3 =80
1083 23:07:07.813917 DQ4 =88, DQ5 =72, DQ6 =92, DQ7 =92
1084 23:07:07.816861 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =64
1085 23:07:07.820474 DQ12 =80, DQ13 =76, DQ14 =84, DQ15 =84
1086 23:07:07.820969
1087 23:07:07.821331
1088 23:07:07.826903 [DQSOSCAuto] RK0, (LSB)MR18= 0x3e3e, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 394 ps
1089 23:07:07.830207 CH0 RK0: MR19=606, MR18=3E3E
1090 23:07:07.837146 CH0_RK0: MR19=0x606, MR18=0x3E3E, DQSOSC=394, MR23=63, INC=95, DEC=63
1091 23:07:07.837647
1092 23:07:07.840816 ----->DramcWriteLeveling(PI) begin...
1093 23:07:07.841333 ==
1094 23:07:07.843989 Dram Type= 6, Freq= 0, CH_0, rank 1
1095 23:07:07.847080 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1096 23:07:07.847514 ==
1097 23:07:07.850770 Write leveling (Byte 0): 29 => 29
1098 23:07:07.854242 Write leveling (Byte 1): 29 => 29
1099 23:07:07.857310 DramcWriteLeveling(PI) end<-----
1100 23:07:07.857725
1101 23:07:07.858053 ==
1102 23:07:07.860369 Dram Type= 6, Freq= 0, CH_0, rank 1
1103 23:07:07.863962 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1104 23:07:07.864378 ==
1105 23:07:07.867453 [Gating] SW mode calibration
1106 23:07:07.873851 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1107 23:07:07.880609 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1108 23:07:07.883770 0 6 0 | B1->B0 | 2f2f 3030 | 0 0 | (0 0) (0 1)
1109 23:07:07.887154 0 6 4 | B1->B0 | 2626 2424 | 0 0 | (0 0) (0 0)
1110 23:07:07.893889 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1111 23:07:07.897298 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1112 23:07:07.900770 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1113 23:07:07.907400 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1114 23:07:07.910715 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1115 23:07:07.913707 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1116 23:07:07.920638 0 7 0 | B1->B0 | 2525 3030 | 0 0 | (0 0) (1 1)
1117 23:07:07.924064 0 7 4 | B1->B0 | 3a3a 4545 | 0 0 | (0 0) (0 0)
1118 23:07:07.927363 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1119 23:07:07.933949 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1120 23:07:07.937250 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1121 23:07:07.940985 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1122 23:07:07.947240 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1123 23:07:07.950291 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1124 23:07:07.953652 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1125 23:07:07.960914 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1126 23:07:07.963768 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1127 23:07:07.967329 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1128 23:07:07.970098 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1129 23:07:07.977115 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1130 23:07:07.980517 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1131 23:07:07.983859 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1132 23:07:07.990538 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1133 23:07:07.993992 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1134 23:07:07.996924 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1135 23:07:08.003921 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1136 23:07:08.007210 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1137 23:07:08.010265 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1138 23:07:08.017447 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1139 23:07:08.020456 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1140 23:07:08.023994 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1141 23:07:08.030553 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1142 23:07:08.031113 Total UI for P1: 0, mck2ui 16
1143 23:07:08.037414 best dqsien dly found for B0: ( 0, 10, 2)
1144 23:07:08.037970 Total UI for P1: 0, mck2ui 16
1145 23:07:08.043610 best dqsien dly found for B1: ( 0, 10, 0)
1146 23:07:08.047388 best DQS0 dly(MCK, UI, PI) = (0, 10, 2)
1147 23:07:08.050305 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
1148 23:07:08.050861
1149 23:07:08.054122 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 2)
1150 23:07:08.056948 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
1151 23:07:08.060608 [Gating] SW calibration Done
1152 23:07:08.061114 ==
1153 23:07:08.063688 Dram Type= 6, Freq= 0, CH_0, rank 1
1154 23:07:08.067185 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1155 23:07:08.067740 ==
1156 23:07:08.070386 RX Vref Scan: 0
1157 23:07:08.070848
1158 23:07:08.071217 RX Vref 0 -> 0, step: 1
1159 23:07:08.071567
1160 23:07:08.073769 RX Delay -130 -> 252, step: 16
1161 23:07:08.117793 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1162 23:07:08.118801 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1163 23:07:08.119210 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1164 23:07:08.119563 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1165 23:07:08.119900 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1166 23:07:08.120228 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1167 23:07:08.120551 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1168 23:07:08.121057 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1169 23:07:08.121406 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1170 23:07:08.121729 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1171 23:07:08.122046 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1172 23:07:08.126613 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1173 23:07:08.129986 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1174 23:07:08.130539 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1175 23:07:08.133286 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1176 23:07:08.139740 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1177 23:07:08.140289 ==
1178 23:07:08.143203 Dram Type= 6, Freq= 0, CH_0, rank 1
1179 23:07:08.146621 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1180 23:07:08.147196 ==
1181 23:07:08.147564 DQS Delay:
1182 23:07:08.149556 DQS0 = 0, DQS1 = 0
1183 23:07:08.150013 DQM Delay:
1184 23:07:08.153213 DQM0 = 83, DQM1 = 73
1185 23:07:08.153760 DQ Delay:
1186 23:07:08.156520 DQ0 =77, DQ1 =85, DQ2 =85, DQ3 =77
1187 23:07:08.159958 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
1188 23:07:08.163418 DQ8 =53, DQ9 =53, DQ10 =69, DQ11 =69
1189 23:07:08.166557 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1190 23:07:08.167107
1191 23:07:08.167467
1192 23:07:08.167803 ==
1193 23:07:08.169589 Dram Type= 6, Freq= 0, CH_0, rank 1
1194 23:07:08.172682 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1195 23:07:08.173190 ==
1196 23:07:08.173556
1197 23:07:08.173891
1198 23:07:08.176015 TX Vref Scan disable
1199 23:07:08.179668 == TX Byte 0 ==
1200 23:07:08.183292 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1201 23:07:08.186414 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1202 23:07:08.189788 == TX Byte 1 ==
1203 23:07:08.193107 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1204 23:07:08.196621 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1205 23:07:08.197233 ==
1206 23:07:08.200140 Dram Type= 6, Freq= 0, CH_0, rank 1
1207 23:07:08.202850 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1208 23:07:08.206509 ==
1209 23:07:08.217530 TX Vref=22, minBit 0, minWin=27, winSum=444
1210 23:07:08.220928 TX Vref=24, minBit 0, minWin=27, winSum=448
1211 23:07:08.224198 TX Vref=26, minBit 2, minWin=28, winSum=455
1212 23:07:08.227342 TX Vref=28, minBit 2, minWin=28, winSum=457
1213 23:07:08.230965 TX Vref=30, minBit 2, minWin=28, winSum=459
1214 23:07:08.234564 TX Vref=32, minBit 2, minWin=28, winSum=459
1215 23:07:08.240873 [TxChooseVref] Worse bit 2, Min win 28, Win sum 459, Final Vref 30
1216 23:07:08.241425
1217 23:07:08.244140 Final TX Range 1 Vref 30
1218 23:07:08.244690
1219 23:07:08.245125 ==
1220 23:07:08.247441 Dram Type= 6, Freq= 0, CH_0, rank 1
1221 23:07:08.250908 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1222 23:07:08.251610 ==
1223 23:07:08.251991
1224 23:07:08.253984
1225 23:07:08.254540 TX Vref Scan disable
1226 23:07:08.257431 == TX Byte 0 ==
1227 23:07:08.260625 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1228 23:07:08.264126 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1229 23:07:08.267526 == TX Byte 1 ==
1230 23:07:08.270460 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1231 23:07:08.273814 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1232 23:07:08.277289
1233 23:07:08.277838 [DATLAT]
1234 23:07:08.278212 Freq=800, CH0 RK1
1235 23:07:08.278559
1236 23:07:08.280483 DATLAT Default: 0x9
1237 23:07:08.281000 0, 0xFFFF, sum = 0
1238 23:07:08.284058 1, 0xFFFF, sum = 0
1239 23:07:08.284530 2, 0xFFFF, sum = 0
1240 23:07:08.287738 3, 0xFFFF, sum = 0
1241 23:07:08.288297 4, 0xFFFF, sum = 0
1242 23:07:08.290761 5, 0xFFFF, sum = 0
1243 23:07:08.291322 6, 0xFFFF, sum = 0
1244 23:07:08.294014 7, 0xFFFF, sum = 0
1245 23:07:08.294573 8, 0x0, sum = 1
1246 23:07:08.297232 9, 0x0, sum = 2
1247 23:07:08.297718 10, 0x0, sum = 3
1248 23:07:08.300944 11, 0x0, sum = 4
1249 23:07:08.301502 best_step = 9
1250 23:07:08.301872
1251 23:07:08.302214 ==
1252 23:07:08.304123 Dram Type= 6, Freq= 0, CH_0, rank 1
1253 23:07:08.310811 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1254 23:07:08.311373 ==
1255 23:07:08.311746 RX Vref Scan: 0
1256 23:07:08.312090
1257 23:07:08.313872 RX Vref 0 -> 0, step: 1
1258 23:07:08.314413
1259 23:07:08.317322 RX Delay -111 -> 252, step: 8
1260 23:07:08.321138 iDelay=217, Bit 0, Center 80 (-39 ~ 200) 240
1261 23:07:08.324050 iDelay=217, Bit 1, Center 88 (-31 ~ 208) 240
1262 23:07:08.330662 iDelay=217, Bit 2, Center 88 (-31 ~ 208) 240
1263 23:07:08.334234 iDelay=217, Bit 3, Center 84 (-31 ~ 200) 232
1264 23:07:08.337389 iDelay=217, Bit 4, Center 88 (-31 ~ 208) 240
1265 23:07:08.340821 iDelay=217, Bit 5, Center 76 (-39 ~ 192) 232
1266 23:07:08.343799 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1267 23:07:08.347712 iDelay=217, Bit 7, Center 96 (-23 ~ 216) 240
1268 23:07:08.354013 iDelay=217, Bit 8, Center 64 (-47 ~ 176) 224
1269 23:07:08.357393 iDelay=217, Bit 9, Center 60 (-55 ~ 176) 232
1270 23:07:08.360777 iDelay=217, Bit 10, Center 76 (-39 ~ 192) 232
1271 23:07:08.364195 iDelay=217, Bit 11, Center 64 (-47 ~ 176) 224
1272 23:07:08.367685 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
1273 23:07:08.373741 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
1274 23:07:08.377264 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
1275 23:07:08.380485 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1276 23:07:08.380997 ==
1277 23:07:08.384160 Dram Type= 6, Freq= 0, CH_0, rank 1
1278 23:07:08.387439 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1279 23:07:08.390646 ==
1280 23:07:08.391202 DQS Delay:
1281 23:07:08.391566 DQS0 = 0, DQS1 = 0
1282 23:07:08.394206 DQM Delay:
1283 23:07:08.394760 DQM0 = 86, DQM1 = 75
1284 23:07:08.397433 DQ Delay:
1285 23:07:08.397884 DQ0 =80, DQ1 =88, DQ2 =88, DQ3 =84
1286 23:07:08.400372 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =96
1287 23:07:08.404061 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =64
1288 23:07:08.406949 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =84
1289 23:07:08.407363
1290 23:07:08.410951
1291 23:07:08.417539 [DQSOSCAuto] RK1, (LSB)MR18= 0x4242, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
1292 23:07:08.420382 CH0 RK1: MR19=606, MR18=4242
1293 23:07:08.427277 CH0_RK1: MR19=0x606, MR18=0x4242, DQSOSC=393, MR23=63, INC=95, DEC=63
1294 23:07:08.430245 [RxdqsGatingPostProcess] freq 800
1295 23:07:08.433668 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1296 23:07:08.436880 Pre-setting of DQS Precalculation
1297 23:07:08.440351 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1298 23:07:08.443508 ==
1299 23:07:08.446917 Dram Type= 6, Freq= 0, CH_1, rank 0
1300 23:07:08.450404 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1301 23:07:08.450831 ==
1302 23:07:08.453680 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1303 23:07:08.460329 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1304 23:07:08.469974 [CA 0] Center 37 (6~68) winsize 63
1305 23:07:08.473412 [CA 1] Center 37 (6~68) winsize 63
1306 23:07:08.476669 [CA 2] Center 34 (4~65) winsize 62
1307 23:07:08.480277 [CA 3] Center 34 (4~65) winsize 62
1308 23:07:08.483241 [CA 4] Center 33 (3~64) winsize 62
1309 23:07:08.486853 [CA 5] Center 33 (3~64) winsize 62
1310 23:07:08.487414
1311 23:07:08.490257 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1312 23:07:08.490817
1313 23:07:08.493249 [CATrainingPosCal] consider 1 rank data
1314 23:07:08.496806 u2DelayCellTimex100 = 270/100 ps
1315 23:07:08.500037 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
1316 23:07:08.506538 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1317 23:07:08.509990 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1318 23:07:08.513341 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1319 23:07:08.516659 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1320 23:07:08.520067 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1321 23:07:08.520634
1322 23:07:08.523317 CA PerBit enable=1, Macro0, CA PI delay=33
1323 23:07:08.523950
1324 23:07:08.526536 [CBTSetCACLKResult] CA Dly = 33
1325 23:07:08.527095 CS Dly: 5 (0~36)
1326 23:07:08.530059 ==
1327 23:07:08.533453 Dram Type= 6, Freq= 0, CH_1, rank 1
1328 23:07:08.536755 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1329 23:07:08.537320 ==
1330 23:07:08.540014 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1331 23:07:08.546727 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1332 23:07:08.556023 [CA 0] Center 37 (6~68) winsize 63
1333 23:07:08.559232 [CA 1] Center 37 (6~68) winsize 63
1334 23:07:08.562532 [CA 2] Center 34 (4~65) winsize 62
1335 23:07:08.565997 [CA 3] Center 34 (4~65) winsize 62
1336 23:07:08.569402 [CA 4] Center 33 (3~64) winsize 62
1337 23:07:08.572587 [CA 5] Center 33 (3~64) winsize 62
1338 23:07:08.573106
1339 23:07:08.575925 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1340 23:07:08.576489
1341 23:07:08.579846 [CATrainingPosCal] consider 2 rank data
1342 23:07:08.582653 u2DelayCellTimex100 = 270/100 ps
1343 23:07:08.585749 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
1344 23:07:08.589377 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1345 23:07:08.596116 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1346 23:07:08.599339 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1347 23:07:08.602630 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1348 23:07:08.605986 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1349 23:07:08.606547
1350 23:07:08.609165 CA PerBit enable=1, Macro0, CA PI delay=33
1351 23:07:08.609629
1352 23:07:08.612433 [CBTSetCACLKResult] CA Dly = 33
1353 23:07:08.613043 CS Dly: 5 (0~37)
1354 23:07:08.613412
1355 23:07:08.615963 ----->DramcWriteLeveling(PI) begin...
1356 23:07:08.619251 ==
1357 23:07:08.622830 Dram Type= 6, Freq= 0, CH_1, rank 0
1358 23:07:08.625878 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1359 23:07:08.626443 ==
1360 23:07:08.629192 Write leveling (Byte 0): 25 => 25
1361 23:07:08.632487 Write leveling (Byte 1): 23 => 23
1362 23:07:08.636191 DramcWriteLeveling(PI) end<-----
1363 23:07:08.636788
1364 23:07:08.637159 ==
1365 23:07:08.639526 Dram Type= 6, Freq= 0, CH_1, rank 0
1366 23:07:08.642650 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1367 23:07:08.643214 ==
1368 23:07:08.645877 [Gating] SW mode calibration
1369 23:07:08.652658 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1370 23:07:08.655768 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1371 23:07:08.662870 0 6 0 | B1->B0 | 3030 2525 | 0 0 | (0 1) (0 0)
1372 23:07:08.665894 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1373 23:07:08.669308 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1374 23:07:08.675874 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1375 23:07:08.679026 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1376 23:07:08.682473 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1377 23:07:08.688949 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1378 23:07:08.692415 0 6 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (1 1)
1379 23:07:08.695772 0 7 0 | B1->B0 | 2d2d 3f3f | 0 0 | (0 0) (0 0)
1380 23:07:08.702542 0 7 4 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
1381 23:07:08.705676 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1382 23:07:08.708822 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1383 23:07:08.715897 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1384 23:07:08.718924 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1385 23:07:08.722718 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1386 23:07:08.729447 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1387 23:07:08.732384 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1388 23:07:08.735794 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1389 23:07:08.742513 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1390 23:07:08.745516 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1391 23:07:08.748986 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1392 23:07:08.755526 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1393 23:07:08.758976 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1394 23:07:08.761997 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1395 23:07:08.768858 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1396 23:07:08.771903 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1397 23:07:08.775074 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1398 23:07:08.778782 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1399 23:07:08.785238 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1400 23:07:08.788821 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1401 23:07:08.792054 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1402 23:07:08.798568 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1403 23:07:08.802037 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1404 23:07:08.805465 Total UI for P1: 0, mck2ui 16
1405 23:07:08.808762 best dqsien dly found for B0: ( 0, 9, 30)
1406 23:07:08.812177 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1407 23:07:08.815493 Total UI for P1: 0, mck2ui 16
1408 23:07:08.818720 best dqsien dly found for B1: ( 0, 10, 0)
1409 23:07:08.821893 best DQS0 dly(MCK, UI, PI) = (0, 9, 30)
1410 23:07:08.825566 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
1411 23:07:08.826122
1412 23:07:08.832070 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 30)
1413 23:07:08.835250 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
1414 23:07:08.838594 [Gating] SW calibration Done
1415 23:07:08.839142 ==
1416 23:07:08.841940 Dram Type= 6, Freq= 0, CH_1, rank 0
1417 23:07:08.845198 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1418 23:07:08.845665 ==
1419 23:07:08.846033 RX Vref Scan: 0
1420 23:07:08.846376
1421 23:07:08.848593 RX Vref 0 -> 0, step: 1
1422 23:07:08.849114
1423 23:07:08.851848 RX Delay -130 -> 252, step: 16
1424 23:07:08.855431 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1425 23:07:08.858551 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1426 23:07:08.865055 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1427 23:07:08.868373 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1428 23:07:08.871778 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1429 23:07:08.875258 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1430 23:07:08.878397 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1431 23:07:08.885314 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1432 23:07:08.888747 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1433 23:07:08.892095 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1434 23:07:08.895227 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1435 23:07:08.898763 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1436 23:07:08.905374 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1437 23:07:08.908537 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1438 23:07:08.912033 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1439 23:07:08.915166 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1440 23:07:08.915749 ==
1441 23:07:08.918480 Dram Type= 6, Freq= 0, CH_1, rank 0
1442 23:07:08.925319 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1443 23:07:08.925885 ==
1444 23:07:08.926256 DQS Delay:
1445 23:07:08.926597 DQS0 = 0, DQS1 = 0
1446 23:07:08.928205 DQM Delay:
1447 23:07:08.928663 DQM0 = 80, DQM1 = 72
1448 23:07:08.931954 DQ Delay:
1449 23:07:08.934985 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1450 23:07:08.938603 DQ4 =77, DQ5 =93, DQ6 =85, DQ7 =77
1451 23:07:08.939167 DQ8 =53, DQ9 =61, DQ10 =77, DQ11 =69
1452 23:07:08.945635 DQ12 =77, DQ13 =85, DQ14 =77, DQ15 =77
1453 23:07:08.946200
1454 23:07:08.946565
1455 23:07:08.946906 ==
1456 23:07:08.948275 Dram Type= 6, Freq= 0, CH_1, rank 0
1457 23:07:08.951781 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1458 23:07:08.952345 ==
1459 23:07:08.952749
1460 23:07:08.953103
1461 23:07:08.954742 TX Vref Scan disable
1462 23:07:08.955204 == TX Byte 0 ==
1463 23:07:08.961766 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1464 23:07:08.965332 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1465 23:07:08.965901 == TX Byte 1 ==
1466 23:07:08.971563 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
1467 23:07:08.974892 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
1468 23:07:08.975399 ==
1469 23:07:08.978231 Dram Type= 6, Freq= 0, CH_1, rank 0
1470 23:07:08.982030 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1471 23:07:08.982608 ==
1472 23:07:08.995801 TX Vref=22, minBit 0, minWin=27, winSum=446
1473 23:07:08.999083 TX Vref=24, minBit 3, minWin=27, winSum=448
1474 23:07:09.002235 TX Vref=26, minBit 3, minWin=27, winSum=455
1475 23:07:09.005683 TX Vref=28, minBit 3, minWin=27, winSum=456
1476 23:07:09.008590 TX Vref=30, minBit 0, minWin=28, winSum=458
1477 23:07:09.012046 TX Vref=32, minBit 0, minWin=28, winSum=453
1478 23:07:09.018919 [TxChooseVref] Worse bit 0, Min win 28, Win sum 458, Final Vref 30
1479 23:07:09.019494
1480 23:07:09.021780 Final TX Range 1 Vref 30
1481 23:07:09.022247
1482 23:07:09.022613 ==
1483 23:07:09.025523 Dram Type= 6, Freq= 0, CH_1, rank 0
1484 23:07:09.029099 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1485 23:07:09.029682 ==
1486 23:07:09.030053
1487 23:07:09.031842
1488 23:07:09.032445 TX Vref Scan disable
1489 23:07:09.035136 == TX Byte 0 ==
1490 23:07:09.038485 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1491 23:07:09.045604 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1492 23:07:09.046169 == TX Byte 1 ==
1493 23:07:09.049241 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
1494 23:07:09.055366 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
1495 23:07:09.055937
1496 23:07:09.056306 [DATLAT]
1497 23:07:09.056648 Freq=800, CH1 RK0
1498 23:07:09.057048
1499 23:07:09.058120 DATLAT Default: 0xa
1500 23:07:09.058576 0, 0xFFFF, sum = 0
1501 23:07:09.061541 1, 0xFFFF, sum = 0
1502 23:07:09.065065 2, 0xFFFF, sum = 0
1503 23:07:09.065636 3, 0xFFFF, sum = 0
1504 23:07:09.068759 4, 0xFFFF, sum = 0
1505 23:07:09.069354 5, 0xFFFF, sum = 0
1506 23:07:09.071810 6, 0xFFFF, sum = 0
1507 23:07:09.072274 7, 0xFFFF, sum = 0
1508 23:07:09.075083 8, 0x0, sum = 1
1509 23:07:09.075653 9, 0x0, sum = 2
1510 23:07:09.076028 10, 0x0, sum = 3
1511 23:07:09.078413 11, 0x0, sum = 4
1512 23:07:09.078884 best_step = 9
1513 23:07:09.079250
1514 23:07:09.079648 ==
1515 23:07:09.082103 Dram Type= 6, Freq= 0, CH_1, rank 0
1516 23:07:09.088642 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1517 23:07:09.089265 ==
1518 23:07:09.089643 RX Vref Scan: 1
1519 23:07:09.089984
1520 23:07:09.091720 Set Vref Range= 32 -> 127
1521 23:07:09.092181
1522 23:07:09.095195 RX Vref 32 -> 127, step: 1
1523 23:07:09.095752
1524 23:07:09.098410 RX Delay -111 -> 252, step: 8
1525 23:07:09.098874
1526 23:07:09.101556 Set Vref, RX VrefLevel [Byte0]: 32
1527 23:07:09.105021 [Byte1]: 32
1528 23:07:09.105590
1529 23:07:09.108446 Set Vref, RX VrefLevel [Byte0]: 33
1530 23:07:09.111530 [Byte1]: 33
1531 23:07:09.112081
1532 23:07:09.114858 Set Vref, RX VrefLevel [Byte0]: 34
1533 23:07:09.118950 [Byte1]: 34
1534 23:07:09.121480
1535 23:07:09.121986 Set Vref, RX VrefLevel [Byte0]: 35
1536 23:07:09.124804 [Byte1]: 35
1537 23:07:09.129120
1538 23:07:09.129572 Set Vref, RX VrefLevel [Byte0]: 36
1539 23:07:09.132344 [Byte1]: 36
1540 23:07:09.136746
1541 23:07:09.137202 Set Vref, RX VrefLevel [Byte0]: 37
1542 23:07:09.140028 [Byte1]: 37
1543 23:07:09.144686
1544 23:07:09.145281 Set Vref, RX VrefLevel [Byte0]: 38
1545 23:07:09.148031 [Byte1]: 38
1546 23:07:09.152125
1547 23:07:09.152763 Set Vref, RX VrefLevel [Byte0]: 39
1548 23:07:09.155253 [Byte1]: 39
1549 23:07:09.160291
1550 23:07:09.160883 Set Vref, RX VrefLevel [Byte0]: 40
1551 23:07:09.163026 [Byte1]: 40
1552 23:07:09.167252
1553 23:07:09.167703 Set Vref, RX VrefLevel [Byte0]: 41
1554 23:07:09.170507 [Byte1]: 41
1555 23:07:09.175414
1556 23:07:09.175972 Set Vref, RX VrefLevel [Byte0]: 42
1557 23:07:09.178671 [Byte1]: 42
1558 23:07:09.182736
1559 23:07:09.183286 Set Vref, RX VrefLevel [Byte0]: 43
1560 23:07:09.186048 [Byte1]: 43
1561 23:07:09.190255
1562 23:07:09.190912 Set Vref, RX VrefLevel [Byte0]: 44
1563 23:07:09.193308 [Byte1]: 44
1564 23:07:09.197897
1565 23:07:09.198451 Set Vref, RX VrefLevel [Byte0]: 45
1566 23:07:09.201008 [Byte1]: 45
1567 23:07:09.205755
1568 23:07:09.206306 Set Vref, RX VrefLevel [Byte0]: 46
1569 23:07:09.209197 [Byte1]: 46
1570 23:07:09.213414
1571 23:07:09.214021 Set Vref, RX VrefLevel [Byte0]: 47
1572 23:07:09.216365 [Byte1]: 47
1573 23:07:09.221262
1574 23:07:09.221720 Set Vref, RX VrefLevel [Byte0]: 48
1575 23:07:09.224348 [Byte1]: 48
1576 23:07:09.228512
1577 23:07:09.229086 Set Vref, RX VrefLevel [Byte0]: 49
1578 23:07:09.231887 [Byte1]: 49
1579 23:07:09.236246
1580 23:07:09.236851 Set Vref, RX VrefLevel [Byte0]: 50
1581 23:07:09.240145 [Byte1]: 50
1582 23:07:09.243860
1583 23:07:09.244420 Set Vref, RX VrefLevel [Byte0]: 51
1584 23:07:09.247384 [Byte1]: 51
1585 23:07:09.251538
1586 23:07:09.252093 Set Vref, RX VrefLevel [Byte0]: 52
1587 23:07:09.255241 [Byte1]: 52
1588 23:07:09.259289
1589 23:07:09.259853 Set Vref, RX VrefLevel [Byte0]: 53
1590 23:07:09.262727 [Byte1]: 53
1591 23:07:09.266726
1592 23:07:09.267297 Set Vref, RX VrefLevel [Byte0]: 54
1593 23:07:09.270323 [Byte1]: 54
1594 23:07:09.274189
1595 23:07:09.274661 Set Vref, RX VrefLevel [Byte0]: 55
1596 23:07:09.277987 [Byte1]: 55
1597 23:07:09.282175
1598 23:07:09.282640 Set Vref, RX VrefLevel [Byte0]: 56
1599 23:07:09.285137 [Byte1]: 56
1600 23:07:09.289693
1601 23:07:09.290256 Set Vref, RX VrefLevel [Byte0]: 57
1602 23:07:09.293020 [Byte1]: 57
1603 23:07:09.297346
1604 23:07:09.297802 Set Vref, RX VrefLevel [Byte0]: 58
1605 23:07:09.300558 [Byte1]: 58
1606 23:07:09.305054
1607 23:07:09.305514 Set Vref, RX VrefLevel [Byte0]: 59
1608 23:07:09.308703 [Byte1]: 59
1609 23:07:09.312772
1610 23:07:09.313336 Set Vref, RX VrefLevel [Byte0]: 60
1611 23:07:09.316064 [Byte1]: 60
1612 23:07:09.320581
1613 23:07:09.321186 Set Vref, RX VrefLevel [Byte0]: 61
1614 23:07:09.323857 [Byte1]: 61
1615 23:07:09.327654
1616 23:07:09.328115 Set Vref, RX VrefLevel [Byte0]: 62
1617 23:07:09.331436 [Byte1]: 62
1618 23:07:09.335782
1619 23:07:09.336361 Set Vref, RX VrefLevel [Byte0]: 63
1620 23:07:09.339242 [Byte1]: 63
1621 23:07:09.343493
1622 23:07:09.344057 Set Vref, RX VrefLevel [Byte0]: 64
1623 23:07:09.346688 [Byte1]: 64
1624 23:07:09.351042
1625 23:07:09.351605 Set Vref, RX VrefLevel [Byte0]: 65
1626 23:07:09.354650 [Byte1]: 65
1627 23:07:09.358856
1628 23:07:09.359317 Set Vref, RX VrefLevel [Byte0]: 66
1629 23:07:09.361985 [Byte1]: 66
1630 23:07:09.366188
1631 23:07:09.366767 Set Vref, RX VrefLevel [Byte0]: 67
1632 23:07:09.369870 [Byte1]: 67
1633 23:07:09.373874
1634 23:07:09.374363 Set Vref, RX VrefLevel [Byte0]: 68
1635 23:07:09.377306 [Byte1]: 68
1636 23:07:09.381820
1637 23:07:09.382490 Set Vref, RX VrefLevel [Byte0]: 69
1638 23:07:09.384668 [Byte1]: 69
1639 23:07:09.389386
1640 23:07:09.389945 Set Vref, RX VrefLevel [Byte0]: 70
1641 23:07:09.392297 [Byte1]: 70
1642 23:07:09.396833
1643 23:07:09.397393 Set Vref, RX VrefLevel [Byte0]: 71
1644 23:07:09.400125 [Byte1]: 71
1645 23:07:09.404466
1646 23:07:09.405093 Set Vref, RX VrefLevel [Byte0]: 72
1647 23:07:09.408131 [Byte1]: 72
1648 23:07:09.412503
1649 23:07:09.413119 Set Vref, RX VrefLevel [Byte0]: 73
1650 23:07:09.415713 [Byte1]: 73
1651 23:07:09.419652
1652 23:07:09.420214 Set Vref, RX VrefLevel [Byte0]: 74
1653 23:07:09.423025 [Byte1]: 74
1654 23:07:09.427417
1655 23:07:09.427977 Final RX Vref Byte 0 = 58 to rank0
1656 23:07:09.430490 Final RX Vref Byte 1 = 53 to rank0
1657 23:07:09.434207 Final RX Vref Byte 0 = 58 to rank1
1658 23:07:09.437426 Final RX Vref Byte 1 = 53 to rank1==
1659 23:07:09.440975 Dram Type= 6, Freq= 0, CH_1, rank 0
1660 23:07:09.447245 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1661 23:07:09.447816 ==
1662 23:07:09.448185 DQS Delay:
1663 23:07:09.448526 DQS0 = 0, DQS1 = 0
1664 23:07:09.450526 DQM Delay:
1665 23:07:09.450986 DQM0 = 81, DQM1 = 75
1666 23:07:09.453874 DQ Delay:
1667 23:07:09.457433 DQ0 =88, DQ1 =76, DQ2 =72, DQ3 =80
1668 23:07:09.458004 DQ4 =80, DQ5 =92, DQ6 =88, DQ7 =76
1669 23:07:09.460790 DQ8 =60, DQ9 =64, DQ10 =76, DQ11 =68
1670 23:07:09.464162 DQ12 =84, DQ13 =84, DQ14 =80, DQ15 =84
1671 23:07:09.467357
1672 23:07:09.467816
1673 23:07:09.473703 [DQSOSCAuto] RK0, (LSB)MR18= 0x5555, (MSB)MR19= 0x606, tDQSOscB0 = 388 ps tDQSOscB1 = 388 ps
1674 23:07:09.477403 CH1 RK0: MR19=606, MR18=5555
1675 23:07:09.483760 CH1_RK0: MR19=0x606, MR18=0x5555, DQSOSC=388, MR23=63, INC=98, DEC=65
1676 23:07:09.484240
1677 23:07:09.487844 ----->DramcWriteLeveling(PI) begin...
1678 23:07:09.488421 ==
1679 23:07:09.490734 Dram Type= 6, Freq= 0, CH_1, rank 1
1680 23:07:09.494086 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1681 23:07:09.494666 ==
1682 23:07:09.497210 Write leveling (Byte 0): 23 => 23
1683 23:07:09.500942 Write leveling (Byte 1): 23 => 23
1684 23:07:09.504013 DramcWriteLeveling(PI) end<-----
1685 23:07:09.504584
1686 23:07:09.505135 ==
1687 23:07:09.507039 Dram Type= 6, Freq= 0, CH_1, rank 1
1688 23:07:09.510901 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1689 23:07:09.511474 ==
1690 23:07:09.513946 [Gating] SW mode calibration
1691 23:07:09.520481 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1692 23:07:09.527570 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1693 23:07:09.530554 0 6 0 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
1694 23:07:09.534339 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1695 23:07:09.540887 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1696 23:07:09.544200 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1697 23:07:09.547286 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1698 23:07:09.553977 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1699 23:07:09.557425 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1700 23:07:09.560532 0 6 28 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (0 0)
1701 23:07:09.567806 0 7 0 | B1->B0 | 3534 4646 | 1 0 | (0 0) (0 0)
1702 23:07:09.570792 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1703 23:07:09.573829 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1704 23:07:09.577468 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1705 23:07:09.583856 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1706 23:07:09.587776 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1707 23:07:09.590638 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1708 23:07:09.597389 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1709 23:07:09.600767 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1710 23:07:09.604650 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1711 23:07:09.610596 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1712 23:07:09.613904 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1713 23:07:09.617101 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1714 23:07:09.624114 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1715 23:07:09.627642 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1716 23:07:09.630836 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1717 23:07:09.637306 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1718 23:07:09.640768 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1719 23:07:09.644216 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1720 23:07:09.650513 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1721 23:07:09.654165 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1722 23:07:09.657583 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1723 23:07:09.664044 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1724 23:07:09.666601 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1725 23:07:09.670109 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1726 23:07:09.673697 Total UI for P1: 0, mck2ui 16
1727 23:07:09.676659 best dqsien dly found for B0: ( 0, 9, 28)
1728 23:07:09.680229 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1729 23:07:09.683653 Total UI for P1: 0, mck2ui 16
1730 23:07:09.686615 best dqsien dly found for B1: ( 0, 10, 0)
1731 23:07:09.690005 best DQS0 dly(MCK, UI, PI) = (0, 9, 28)
1732 23:07:09.693452 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
1733 23:07:09.696873
1734 23:07:09.700202 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 28)
1735 23:07:09.703356 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
1736 23:07:09.707105 [Gating] SW calibration Done
1737 23:07:09.707186 ==
1738 23:07:09.710008 Dram Type= 6, Freq= 0, CH_1, rank 1
1739 23:07:09.713781 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1740 23:07:09.713863 ==
1741 23:07:09.713927 RX Vref Scan: 0
1742 23:07:09.717180
1743 23:07:09.717260 RX Vref 0 -> 0, step: 1
1744 23:07:09.717323
1745 23:07:09.720733 RX Delay -130 -> 252, step: 16
1746 23:07:09.723651 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1747 23:07:09.727008 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1748 23:07:09.733340 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1749 23:07:09.736942 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1750 23:07:09.740459 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1751 23:07:09.743989 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1752 23:07:09.747144 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1753 23:07:09.753569 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1754 23:07:09.757098 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1755 23:07:09.760246 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1756 23:07:09.763668 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1757 23:07:09.767117 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1758 23:07:09.773650 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1759 23:07:09.777067 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1760 23:07:09.780369 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1761 23:07:09.784017 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1762 23:07:09.784099 ==
1763 23:07:09.787162 Dram Type= 6, Freq= 0, CH_1, rank 1
1764 23:07:09.790698 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1765 23:07:09.794268 ==
1766 23:07:09.794348 DQS Delay:
1767 23:07:09.794412 DQS0 = 0, DQS1 = 0
1768 23:07:09.797069 DQM Delay:
1769 23:07:09.797149 DQM0 = 85, DQM1 = 74
1770 23:07:09.800647 DQ Delay:
1771 23:07:09.803735 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85
1772 23:07:09.803820 DQ4 =85, DQ5 =101, DQ6 =85, DQ7 =85
1773 23:07:09.807089 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
1774 23:07:09.810491 DQ12 =85, DQ13 =85, DQ14 =77, DQ15 =85
1775 23:07:09.813792
1776 23:07:09.813872
1777 23:07:09.813937 ==
1778 23:07:09.817191 Dram Type= 6, Freq= 0, CH_1, rank 1
1779 23:07:09.820328 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1780 23:07:09.820408 ==
1781 23:07:09.820471
1782 23:07:09.820530
1783 23:07:09.823811 TX Vref Scan disable
1784 23:07:09.823891 == TX Byte 0 ==
1785 23:07:09.830653 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1786 23:07:09.833596 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1787 23:07:09.833677 == TX Byte 1 ==
1788 23:07:09.840785 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
1789 23:07:09.843673 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
1790 23:07:09.843753 ==
1791 23:07:09.847155 Dram Type= 6, Freq= 0, CH_1, rank 1
1792 23:07:09.850197 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1793 23:07:09.850278 ==
1794 23:07:09.864018 TX Vref=22, minBit 0, minWin=27, winSum=447
1795 23:07:09.867208 TX Vref=24, minBit 0, minWin=28, winSum=452
1796 23:07:09.870764 TX Vref=26, minBit 5, minWin=28, winSum=458
1797 23:07:09.873707 TX Vref=28, minBit 6, minWin=28, winSum=458
1798 23:07:09.876856 TX Vref=30, minBit 9, minWin=27, winSum=457
1799 23:07:09.883585 TX Vref=32, minBit 9, minWin=27, winSum=453
1800 23:07:09.887077 [TxChooseVref] Worse bit 5, Min win 28, Win sum 458, Final Vref 26
1801 23:07:09.887180
1802 23:07:09.890195 Final TX Range 1 Vref 26
1803 23:07:09.890295
1804 23:07:09.890394 ==
1805 23:07:09.893893 Dram Type= 6, Freq= 0, CH_1, rank 1
1806 23:07:09.897374 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1807 23:07:09.897473 ==
1808 23:07:09.900060
1809 23:07:09.900157
1810 23:07:09.900256 TX Vref Scan disable
1811 23:07:09.903744 == TX Byte 0 ==
1812 23:07:09.907002 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1813 23:07:09.910246 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1814 23:07:09.913622 == TX Byte 1 ==
1815 23:07:09.917142 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
1816 23:07:09.923923 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
1817 23:07:09.924024
1818 23:07:09.924123 [DATLAT]
1819 23:07:09.924220 Freq=800, CH1 RK1
1820 23:07:09.924319
1821 23:07:09.926929 DATLAT Default: 0x9
1822 23:07:09.927029 0, 0xFFFF, sum = 0
1823 23:07:09.930113 1, 0xFFFF, sum = 0
1824 23:07:09.930228 2, 0xFFFF, sum = 0
1825 23:07:09.933791 3, 0xFFFF, sum = 0
1826 23:07:09.933902 4, 0xFFFF, sum = 0
1827 23:07:09.937162 5, 0xFFFF, sum = 0
1828 23:07:09.940258 6, 0xFFFF, sum = 0
1829 23:07:09.940374 7, 0xFFFF, sum = 0
1830 23:07:09.940477 8, 0x0, sum = 1
1831 23:07:09.943729 9, 0x0, sum = 2
1832 23:07:09.943848 10, 0x0, sum = 3
1833 23:07:09.947045 11, 0x0, sum = 4
1834 23:07:09.947174 best_step = 9
1835 23:07:09.947286
1836 23:07:09.947397 ==
1837 23:07:09.950430 Dram Type= 6, Freq= 0, CH_1, rank 1
1838 23:07:09.957131 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1839 23:07:09.957322 ==
1840 23:07:09.957451 RX Vref Scan: 0
1841 23:07:09.957591
1842 23:07:09.960446 RX Vref 0 -> 0, step: 1
1843 23:07:09.960591
1844 23:07:09.963755 RX Delay -111 -> 252, step: 8
1845 23:07:09.967030 iDelay=217, Bit 0, Center 84 (-31 ~ 200) 232
1846 23:07:09.970314 iDelay=217, Bit 1, Center 76 (-39 ~ 192) 232
1847 23:07:09.977014 iDelay=217, Bit 2, Center 72 (-47 ~ 192) 240
1848 23:07:09.980188 iDelay=217, Bit 3, Center 80 (-39 ~ 200) 240
1849 23:07:09.983667 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
1850 23:07:09.987177 iDelay=217, Bit 5, Center 96 (-23 ~ 216) 240
1851 23:07:09.990477 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1852 23:07:09.997244 iDelay=217, Bit 7, Center 80 (-39 ~ 200) 240
1853 23:07:10.000771 iDelay=217, Bit 8, Center 60 (-55 ~ 176) 232
1854 23:07:10.004198 iDelay=217, Bit 9, Center 60 (-55 ~ 176) 232
1855 23:07:10.007668 iDelay=217, Bit 10, Center 72 (-47 ~ 192) 240
1856 23:07:10.010499 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
1857 23:07:10.017466 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
1858 23:07:10.020645 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
1859 23:07:10.024502 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
1860 23:07:10.027368 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1861 23:07:10.027899 ==
1862 23:07:10.030393 Dram Type= 6, Freq= 0, CH_1, rank 1
1863 23:07:10.037641 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1864 23:07:10.038221 ==
1865 23:07:10.038740 DQS Delay:
1866 23:07:10.039336 DQS0 = 0, DQS1 = 0
1867 23:07:10.040502 DQM Delay:
1868 23:07:10.041134 DQM0 = 83, DQM1 = 74
1869 23:07:10.043777 DQ Delay:
1870 23:07:10.047217 DQ0 =84, DQ1 =76, DQ2 =72, DQ3 =80
1871 23:07:10.047837 DQ4 =84, DQ5 =96, DQ6 =92, DQ7 =80
1872 23:07:10.050679 DQ8 =60, DQ9 =60, DQ10 =72, DQ11 =68
1873 23:07:10.053978 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =84
1874 23:07:10.057317
1875 23:07:10.057938
1876 23:07:10.063925 [DQSOSCAuto] RK1, (LSB)MR18= 0x3636, (MSB)MR19= 0x606, tDQSOscB0 = 396 ps tDQSOscB1 = 396 ps
1877 23:07:10.067176 CH1 RK1: MR19=606, MR18=3636
1878 23:07:10.074076 CH1_RK1: MR19=0x606, MR18=0x3636, DQSOSC=396, MR23=63, INC=94, DEC=62
1879 23:07:10.077031 [RxdqsGatingPostProcess] freq 800
1880 23:07:10.080937 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1881 23:07:10.083875 Pre-setting of DQS Precalculation
1882 23:07:10.087258 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1883 23:07:10.097142 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
1884 23:07:10.104024 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
1885 23:07:10.104478
1886 23:07:10.104862
1887 23:07:10.107126 [Calibration Summary] 1600 Mbps
1888 23:07:10.107542 CH 0, Rank 0
1889 23:07:10.110657 SW Impedance : PASS
1890 23:07:10.111071 DUTY Scan : NO K
1891 23:07:10.113960 ZQ Calibration : PASS
1892 23:07:10.117006 Jitter Meter : NO K
1893 23:07:10.117504 CBT Training : PASS
1894 23:07:10.120358 Write leveling : PASS
1895 23:07:10.123692 RX DQS gating : PASS
1896 23:07:10.123988 RX DQ/DQS(RDDQC) : PASS
1897 23:07:10.126816 TX DQ/DQS : PASS
1898 23:07:10.130499 RX DATLAT : PASS
1899 23:07:10.130767 RX DQ/DQS(Engine): PASS
1900 23:07:10.133411 TX OE : NO K
1901 23:07:10.133582 All Pass.
1902 23:07:10.133740
1903 23:07:10.136867 CH 0, Rank 1
1904 23:07:10.137041 SW Impedance : PASS
1905 23:07:10.140130 DUTY Scan : NO K
1906 23:07:10.143492 ZQ Calibration : PASS
1907 23:07:10.143662 Jitter Meter : NO K
1908 23:07:10.146876 CBT Training : PASS
1909 23:07:10.150209 Write leveling : PASS
1910 23:07:10.150337 RX DQS gating : PASS
1911 23:07:10.153351 RX DQ/DQS(RDDQC) : PASS
1912 23:07:10.153472 TX DQ/DQS : PASS
1913 23:07:10.156573 RX DATLAT : PASS
1914 23:07:10.159989 RX DQ/DQS(Engine): PASS
1915 23:07:10.160129 TX OE : NO K
1916 23:07:10.163219 All Pass.
1917 23:07:10.163331
1918 23:07:10.163446 CH 1, Rank 0
1919 23:07:10.166735 SW Impedance : PASS
1920 23:07:10.166875 DUTY Scan : NO K
1921 23:07:10.169792 ZQ Calibration : PASS
1922 23:07:10.173107 Jitter Meter : NO K
1923 23:07:10.173264 CBT Training : PASS
1924 23:07:10.176483 Write leveling : PASS
1925 23:07:10.180089 RX DQS gating : PASS
1926 23:07:10.180241 RX DQ/DQS(RDDQC) : PASS
1927 23:07:10.183340 TX DQ/DQS : PASS
1928 23:07:10.186990 RX DATLAT : PASS
1929 23:07:10.187150 RX DQ/DQS(Engine): PASS
1930 23:07:10.189839 TX OE : NO K
1931 23:07:10.189994 All Pass.
1932 23:07:10.190148
1933 23:07:10.193235 CH 1, Rank 1
1934 23:07:10.193376 SW Impedance : PASS
1935 23:07:10.196861 DUTY Scan : NO K
1936 23:07:10.197017 ZQ Calibration : PASS
1937 23:07:10.200588 Jitter Meter : NO K
1938 23:07:10.203198 CBT Training : PASS
1939 23:07:10.203342 Write leveling : PASS
1940 23:07:10.206805 RX DQS gating : PASS
1941 23:07:10.210244 RX DQ/DQS(RDDQC) : PASS
1942 23:07:10.210353 TX DQ/DQS : PASS
1943 23:07:10.213332 RX DATLAT : PASS
1944 23:07:10.216935 RX DQ/DQS(Engine): PASS
1945 23:07:10.217044 TX OE : NO K
1946 23:07:10.219838 All Pass.
1947 23:07:10.219945
1948 23:07:10.220050 DramC Write-DBI off
1949 23:07:10.223375 PER_BANK_REFRESH: Hybrid Mode
1950 23:07:10.223483 TX_TRACKING: ON
1951 23:07:10.226528 [GetDramInforAfterCalByMRR] Vendor 6.
1952 23:07:10.233504 [GetDramInforAfterCalByMRR] Revision 606.
1953 23:07:10.237098 [GetDramInforAfterCalByMRR] Revision 2 0.
1954 23:07:10.237175 MR0 0x3939
1955 23:07:10.237264 MR8 0x1111
1956 23:07:10.239751 RK0, DieNum 1, Density 16Gb, RKsize 16Gb.
1957 23:07:10.239850
1958 23:07:10.243385 MR0 0x3939
1959 23:07:10.243486 MR8 0x1111
1960 23:07:10.246554 RK1, DieNum 1, Density 16Gb, RKsize 16Gb.
1961 23:07:10.246655
1962 23:07:10.256741 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
1963 23:07:10.259919 [FAST_K] Save calibration result to emmc
1964 23:07:10.263163 [FAST_K] Save calibration result to emmc
1965 23:07:10.266703 dram_init: config_dvfs: 1
1966 23:07:10.270074 dramc_set_vcore_voltage set vcore to 662500
1967 23:07:10.273711 Read voltage for 1200, 2
1968 23:07:10.273814 Vio18 = 0
1969 23:07:10.273916 Vcore = 662500
1970 23:07:10.276613 Vdram = 0
1971 23:07:10.276739 Vddq = 0
1972 23:07:10.276833 Vmddr = 0
1973 23:07:10.283350 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
1974 23:07:10.286659 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
1975 23:07:10.289991 MEM_TYPE=3, freq_sel=15
1976 23:07:10.293133 sv_algorithm_assistance_LP4_1600
1977 23:07:10.296443 ============ PULL DRAM RESETB DOWN ============
1978 23:07:10.300182 ========== PULL DRAM RESETB DOWN end =========
1979 23:07:10.306460 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
1980 23:07:10.309923 ===================================
1981 23:07:10.310050 LPDDR4 DRAM CONFIGURATION
1982 23:07:10.313114 ===================================
1983 23:07:10.316622 EX_ROW_EN[0] = 0x0
1984 23:07:10.320050 EX_ROW_EN[1] = 0x0
1985 23:07:10.320166 LP4Y_EN = 0x0
1986 23:07:10.323396 WORK_FSP = 0x0
1987 23:07:10.323501 WL = 0x4
1988 23:07:10.326595 RL = 0x4
1989 23:07:10.326697 BL = 0x2
1990 23:07:10.329857 RPST = 0x0
1991 23:07:10.329962 RD_PRE = 0x0
1992 23:07:10.333084 WR_PRE = 0x1
1993 23:07:10.333178 WR_PST = 0x0
1994 23:07:10.336550 DBI_WR = 0x0
1995 23:07:10.336636 DBI_RD = 0x0
1996 23:07:10.339973 OTF = 0x1
1997 23:07:10.343299 ===================================
1998 23:07:10.346802 ===================================
1999 23:07:10.346885 ANA top config
2000 23:07:10.349934 ===================================
2001 23:07:10.353584 DLL_ASYNC_EN = 0
2002 23:07:10.356622 ALL_SLAVE_EN = 0
2003 23:07:10.356773 NEW_RANK_MODE = 1
2004 23:07:10.359863 DLL_IDLE_MODE = 1
2005 23:07:10.363378 LP45_APHY_COMB_EN = 1
2006 23:07:10.366636 TX_ODT_DIS = 1
2007 23:07:10.369846 NEW_8X_MODE = 1
2008 23:07:10.373277 ===================================
2009 23:07:10.376397 ===================================
2010 23:07:10.376512 data_rate = 2400
2011 23:07:10.379769 CKR = 1
2012 23:07:10.383511 DQ_P2S_RATIO = 8
2013 23:07:10.386703 ===================================
2014 23:07:10.389711 CA_P2S_RATIO = 8
2015 23:07:10.393212 DQ_CA_OPEN = 0
2016 23:07:10.396516 DQ_SEMI_OPEN = 0
2017 23:07:10.396624 CA_SEMI_OPEN = 0
2018 23:07:10.399807 CA_FULL_RATE = 0
2019 23:07:10.403364 DQ_CKDIV4_EN = 0
2020 23:07:10.406833 CA_CKDIV4_EN = 0
2021 23:07:10.409751 CA_PREDIV_EN = 0
2022 23:07:10.413156 PH8_DLY = 17
2023 23:07:10.413237 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2024 23:07:10.416296 DQ_AAMCK_DIV = 4
2025 23:07:10.419881 CA_AAMCK_DIV = 4
2026 23:07:10.423180 CA_ADMCK_DIV = 4
2027 23:07:10.426553 DQ_TRACK_CA_EN = 0
2028 23:07:10.429802 CA_PICK = 1200
2029 23:07:10.433255 CA_MCKIO = 1200
2030 23:07:10.433326 MCKIO_SEMI = 0
2031 23:07:10.436480 PLL_FREQ = 2366
2032 23:07:10.439551 DQ_UI_PI_RATIO = 32
2033 23:07:10.442869 CA_UI_PI_RATIO = 0
2034 23:07:10.446269 ===================================
2035 23:07:10.450146 ===================================
2036 23:07:10.453208 memory_type:LPDDR4
2037 23:07:10.453290 GP_NUM : 10
2038 23:07:10.456324 SRAM_EN : 1
2039 23:07:10.456405 MD32_EN : 0
2040 23:07:10.459881 ===================================
2041 23:07:10.462950 [ANA_INIT] >>>>>>>>>>>>>>
2042 23:07:10.466495 <<<<<< [CONFIGURE PHASE]: ANA_TX
2043 23:07:10.469554 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2044 23:07:10.472959 ===================================
2045 23:07:10.476590 data_rate = 2400,PCW = 0X5b00
2046 23:07:10.479701 ===================================
2047 23:07:10.482877 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2048 23:07:10.489577 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2049 23:07:10.492865 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2050 23:07:10.499659 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2051 23:07:10.502778 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2052 23:07:10.506125 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2053 23:07:10.506256 [ANA_INIT] flow start
2054 23:07:10.509545 [ANA_INIT] PLL >>>>>>>>
2055 23:07:10.512801 [ANA_INIT] PLL <<<<<<<<
2056 23:07:10.512882 [ANA_INIT] MIDPI >>>>>>>>
2057 23:07:10.516228 [ANA_INIT] MIDPI <<<<<<<<
2058 23:07:10.519454 [ANA_INIT] DLL >>>>>>>>
2059 23:07:10.519534 [ANA_INIT] DLL <<<<<<<<
2060 23:07:10.522742 [ANA_INIT] flow end
2061 23:07:10.526191 ============ LP4 DIFF to SE enter ============
2062 23:07:10.529573 ============ LP4 DIFF to SE exit ============
2063 23:07:10.533162 [ANA_INIT] <<<<<<<<<<<<<
2064 23:07:10.536779 [Flow] Enable top DCM control >>>>>
2065 23:07:10.539681 [Flow] Enable top DCM control <<<<<
2066 23:07:10.543002 Enable DLL master slave shuffle
2067 23:07:10.549739 ==============================================================
2068 23:07:10.549820 Gating Mode config
2069 23:07:10.556230 ==============================================================
2070 23:07:10.556311 Config description:
2071 23:07:10.566339 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2072 23:07:10.572832 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2073 23:07:10.579876 SELPH_MODE 0: By rank 1: By Phase
2074 23:07:10.582952 ==============================================================
2075 23:07:10.586365 GAT_TRACK_EN = 1
2076 23:07:10.589662 RX_GATING_MODE = 2
2077 23:07:10.593353 RX_GATING_TRACK_MODE = 2
2078 23:07:10.596401 SELPH_MODE = 1
2079 23:07:10.599990 PICG_EARLY_EN = 1
2080 23:07:10.603106 VALID_LAT_VALUE = 1
2081 23:07:10.606558 ==============================================================
2082 23:07:10.612989 Enter into Gating configuration >>>>
2083 23:07:10.613070 Exit from Gating configuration <<<<
2084 23:07:10.616299 Enter into DVFS_PRE_config >>>>>
2085 23:07:10.629621 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2086 23:07:10.633145 Exit from DVFS_PRE_config <<<<<
2087 23:07:10.636481 Enter into PICG configuration >>>>
2088 23:07:10.636562 Exit from PICG configuration <<<<
2089 23:07:10.639722 [RX_INPUT] configuration >>>>>
2090 23:07:10.643047 [RX_INPUT] configuration <<<<<
2091 23:07:10.649895 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2092 23:07:10.653248 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2093 23:07:10.659813 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2094 23:07:10.666248 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2095 23:07:10.672897 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2096 23:07:10.679517 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2097 23:07:10.682620 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2098 23:07:10.686310 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2099 23:07:10.692536 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2100 23:07:10.695932 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2101 23:07:10.699324 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2102 23:07:10.702393 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2103 23:07:10.705927 ===================================
2104 23:07:10.709088 LPDDR4 DRAM CONFIGURATION
2105 23:07:10.712590 ===================================
2106 23:07:10.715695 EX_ROW_EN[0] = 0x0
2107 23:07:10.715776 EX_ROW_EN[1] = 0x0
2108 23:07:10.719177 LP4Y_EN = 0x0
2109 23:07:10.719258 WORK_FSP = 0x0
2110 23:07:10.722356 WL = 0x4
2111 23:07:10.722436 RL = 0x4
2112 23:07:10.725664 BL = 0x2
2113 23:07:10.725744 RPST = 0x0
2114 23:07:10.729303 RD_PRE = 0x0
2115 23:07:10.729383 WR_PRE = 0x1
2116 23:07:10.732535 WR_PST = 0x0
2117 23:07:10.732615 DBI_WR = 0x0
2118 23:07:10.735979 DBI_RD = 0x0
2119 23:07:10.736059 OTF = 0x1
2120 23:07:10.739071 ===================================
2121 23:07:10.745886 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2122 23:07:10.749226 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2123 23:07:10.752388 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2124 23:07:10.755778 ===================================
2125 23:07:10.759403 LPDDR4 DRAM CONFIGURATION
2126 23:07:10.762322 ===================================
2127 23:07:10.765709 EX_ROW_EN[0] = 0x10
2128 23:07:10.765788 EX_ROW_EN[1] = 0x0
2129 23:07:10.769142 LP4Y_EN = 0x0
2130 23:07:10.769221 WORK_FSP = 0x0
2131 23:07:10.772554 WL = 0x4
2132 23:07:10.772649 RL = 0x4
2133 23:07:10.775658 BL = 0x2
2134 23:07:10.775736 RPST = 0x0
2135 23:07:10.779241 RD_PRE = 0x0
2136 23:07:10.779319 WR_PRE = 0x1
2137 23:07:10.782517 WR_PST = 0x0
2138 23:07:10.782624 DBI_WR = 0x0
2139 23:07:10.785793 DBI_RD = 0x0
2140 23:07:10.785923 OTF = 0x1
2141 23:07:10.789289 ===================================
2142 23:07:10.795882 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2143 23:07:10.795961 ==
2144 23:07:10.799481 Dram Type= 6, Freq= 0, CH_0, rank 0
2145 23:07:10.805605 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2146 23:07:10.805684 ==
2147 23:07:10.805747 [Duty_Offset_Calibration]
2148 23:07:10.809122 B0:0 B1:2 CA:1
2149 23:07:10.809242
2150 23:07:10.812065 [DutyScan_Calibration_Flow] k_type=0
2151 23:07:10.821062
2152 23:07:10.821140 ==CLK 0==
2153 23:07:10.824292 Final CLK duty delay cell = 0
2154 23:07:10.828017 [0] MAX Duty = 5093%(X100), DQS PI = 12
2155 23:07:10.830923 [0] MIN Duty = 4938%(X100), DQS PI = 52
2156 23:07:10.831003 [0] AVG Duty = 5015%(X100)
2157 23:07:10.834356
2158 23:07:10.837529 CH0 CLK Duty spec in!! Max-Min= 155%
2159 23:07:10.840897 [DutyScan_Calibration_Flow] ====Done====
2160 23:07:10.840976
2161 23:07:10.844092 [DutyScan_Calibration_Flow] k_type=1
2162 23:07:10.860097
2163 23:07:10.860177 ==DQS 0 ==
2164 23:07:10.863724 Final DQS duty delay cell = 0
2165 23:07:10.866768 [0] MAX Duty = 5125%(X100), DQS PI = 30
2166 23:07:10.870145 [0] MIN Duty = 5031%(X100), DQS PI = 4
2167 23:07:10.873559 [0] AVG Duty = 5078%(X100)
2168 23:07:10.873639
2169 23:07:10.873703 ==DQS 1 ==
2170 23:07:10.876655 Final DQS duty delay cell = 0
2171 23:07:10.880324 [0] MAX Duty = 5062%(X100), DQS PI = 56
2172 23:07:10.883688 [0] MIN Duty = 4906%(X100), DQS PI = 16
2173 23:07:10.886753 [0] AVG Duty = 4984%(X100)
2174 23:07:10.886834
2175 23:07:10.890081 CH0 DQS 0 Duty spec in!! Max-Min= 94%
2176 23:07:10.890161
2177 23:07:10.893423 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2178 23:07:10.897190 [DutyScan_Calibration_Flow] ====Done====
2179 23:07:10.897270
2180 23:07:10.899958 [DutyScan_Calibration_Flow] k_type=3
2181 23:07:10.916664
2182 23:07:10.916749 ==DQM 0 ==
2183 23:07:10.919863 Final DQM duty delay cell = 0
2184 23:07:10.923235 [0] MAX Duty = 5156%(X100), DQS PI = 20
2185 23:07:10.926448 [0] MIN Duty = 4969%(X100), DQS PI = 42
2186 23:07:10.930073 [0] AVG Duty = 5062%(X100)
2187 23:07:10.930153
2188 23:07:10.930216 ==DQM 1 ==
2189 23:07:10.933211 Final DQM duty delay cell = 0
2190 23:07:10.936684 [0] MAX Duty = 5000%(X100), DQS PI = 52
2191 23:07:10.940057 [0] MIN Duty = 4844%(X100), DQS PI = 2
2192 23:07:10.940138 [0] AVG Duty = 4922%(X100)
2193 23:07:10.943590
2194 23:07:10.946904 CH0 DQM 0 Duty spec in!! Max-Min= 187%
2195 23:07:10.946984
2196 23:07:10.949822 CH0 DQM 1 Duty spec in!! Max-Min= 156%
2197 23:07:10.953272 [DutyScan_Calibration_Flow] ====Done====
2198 23:07:10.953352
2199 23:07:10.956784 [DutyScan_Calibration_Flow] k_type=2
2200 23:07:10.971642
2201 23:07:10.971723 ==DQ 0 ==
2202 23:07:10.974723 Final DQ duty delay cell = -4
2203 23:07:10.978205 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2204 23:07:10.981638 [-4] MIN Duty = 4813%(X100), DQS PI = 8
2205 23:07:10.984771 [-4] AVG Duty = 4937%(X100)
2206 23:07:10.984852
2207 23:07:10.984916 ==DQ 1 ==
2208 23:07:10.988338 Final DQ duty delay cell = -4
2209 23:07:10.991798 [-4] MAX Duty = 5062%(X100), DQS PI = 6
2210 23:07:10.994869 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2211 23:07:10.998257 [-4] AVG Duty = 4984%(X100)
2212 23:07:10.998338
2213 23:07:11.001523 CH0 DQ 0 Duty spec in!! Max-Min= 249%
2214 23:07:11.001603
2215 23:07:11.004715 CH0 DQ 1 Duty spec in!! Max-Min= 155%
2216 23:07:11.008457 [DutyScan_Calibration_Flow] ====Done====
2217 23:07:11.008563 ==
2218 23:07:11.011601 Dram Type= 6, Freq= 0, CH_1, rank 0
2219 23:07:11.014814 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2220 23:07:11.014896 ==
2221 23:07:11.018153 [Duty_Offset_Calibration]
2222 23:07:11.018234 B0:0 B1:5 CA:-5
2223 23:07:11.018297
2224 23:07:11.021793 [DutyScan_Calibration_Flow] k_type=0
2225 23:07:11.031953
2226 23:07:11.032034 ==CLK 0==
2227 23:07:11.035186 Final CLK duty delay cell = 0
2228 23:07:11.038694 [0] MAX Duty = 5094%(X100), DQS PI = 24
2229 23:07:11.041751 [0] MIN Duty = 4875%(X100), DQS PI = 46
2230 23:07:11.041833 [0] AVG Duty = 4984%(X100)
2231 23:07:11.045643
2232 23:07:11.048934 CH1 CLK Duty spec in!! Max-Min= 219%
2233 23:07:11.051788 [DutyScan_Calibration_Flow] ====Done====
2234 23:07:11.051869
2235 23:07:11.055124 [DutyScan_Calibration_Flow] k_type=1
2236 23:07:11.070621
2237 23:07:11.070701 ==DQS 0 ==
2238 23:07:11.073819 Final DQS duty delay cell = 0
2239 23:07:11.077036 [0] MAX Duty = 5125%(X100), DQS PI = 16
2240 23:07:11.080430 [0] MIN Duty = 4875%(X100), DQS PI = 40
2241 23:07:11.083881 [0] AVG Duty = 5000%(X100)
2242 23:07:11.083961
2243 23:07:11.084025 ==DQS 1 ==
2244 23:07:11.086946 Final DQS duty delay cell = -4
2245 23:07:11.090452 [-4] MAX Duty = 5000%(X100), DQS PI = 18
2246 23:07:11.093646 [-4] MIN Duty = 4907%(X100), DQS PI = 46
2247 23:07:11.096928 [-4] AVG Duty = 4953%(X100)
2248 23:07:11.097009
2249 23:07:11.100166 CH1 DQS 0 Duty spec in!! Max-Min= 250%
2250 23:07:11.100247
2251 23:07:11.103821 CH1 DQS 1 Duty spec in!! Max-Min= 93%
2252 23:07:11.107345 [DutyScan_Calibration_Flow] ====Done====
2253 23:07:11.107426
2254 23:07:11.110087 [DutyScan_Calibration_Flow] k_type=3
2255 23:07:11.125816
2256 23:07:11.125897 ==DQM 0 ==
2257 23:07:11.128914 Final DQM duty delay cell = -4
2258 23:07:11.132786 [-4] MAX Duty = 5094%(X100), DQS PI = 32
2259 23:07:11.135556 [-4] MIN Duty = 4844%(X100), DQS PI = 40
2260 23:07:11.138917 [-4] AVG Duty = 4969%(X100)
2261 23:07:11.138999
2262 23:07:11.139064 ==DQM 1 ==
2263 23:07:11.142310 Final DQM duty delay cell = -4
2264 23:07:11.145775 [-4] MAX Duty = 5094%(X100), DQS PI = 20
2265 23:07:11.148943 [-4] MIN Duty = 4906%(X100), DQS PI = 58
2266 23:07:11.152099 [-4] AVG Duty = 5000%(X100)
2267 23:07:11.152180
2268 23:07:11.155582 CH1 DQM 0 Duty spec in!! Max-Min= 250%
2269 23:07:11.155664
2270 23:07:11.158765 CH1 DQM 1 Duty spec in!! Max-Min= 188%
2271 23:07:11.162354 [DutyScan_Calibration_Flow] ====Done====
2272 23:07:11.162436
2273 23:07:11.165584 [DutyScan_Calibration_Flow] k_type=2
2274 23:07:11.182709
2275 23:07:11.182805 ==DQ 0 ==
2276 23:07:11.186231 Final DQ duty delay cell = 0
2277 23:07:11.189364 [0] MAX Duty = 5093%(X100), DQS PI = 0
2278 23:07:11.192889 [0] MIN Duty = 4969%(X100), DQS PI = 44
2279 23:07:11.192971 [0] AVG Duty = 5031%(X100)
2280 23:07:11.193049
2281 23:07:11.196265 ==DQ 1 ==
2282 23:07:11.199580 Final DQ duty delay cell = 0
2283 23:07:11.202631 [0] MAX Duty = 5031%(X100), DQS PI = 8
2284 23:07:11.205918 [0] MIN Duty = 4907%(X100), DQS PI = 0
2285 23:07:11.206000 [0] AVG Duty = 4969%(X100)
2286 23:07:11.206064
2287 23:07:11.209308 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2288 23:07:11.209389
2289 23:07:11.212576 CH1 DQ 1 Duty spec in!! Max-Min= 124%
2290 23:07:11.219220 [DutyScan_Calibration_Flow] ====Done====
2291 23:07:11.222798 nWR fixed to 30
2292 23:07:11.222879 [ModeRegInit_LP4] CH0 RK0
2293 23:07:11.226142 [ModeRegInit_LP4] CH0 RK1
2294 23:07:11.229372 [ModeRegInit_LP4] CH1 RK0
2295 23:07:11.229452 [ModeRegInit_LP4] CH1 RK1
2296 23:07:11.232749 match AC timing 6
2297 23:07:11.235841 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 0
2298 23:07:11.239448 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2299 23:07:11.246161 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2300 23:07:11.249182 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2301 23:07:11.255937 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2302 23:07:11.256017 ==
2303 23:07:11.259107 Dram Type= 6, Freq= 0, CH_0, rank 0
2304 23:07:11.262712 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2305 23:07:11.262792 ==
2306 23:07:11.269194 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2307 23:07:11.272524 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2308 23:07:11.282403 [CA 0] Center 39 (9~70) winsize 62
2309 23:07:11.286075 [CA 1] Center 39 (8~70) winsize 63
2310 23:07:11.289031 [CA 2] Center 36 (5~67) winsize 63
2311 23:07:11.292926 [CA 3] Center 35 (4~66) winsize 63
2312 23:07:11.295866 [CA 4] Center 34 (3~65) winsize 63
2313 23:07:11.299183 [CA 5] Center 33 (3~64) winsize 62
2314 23:07:11.299296
2315 23:07:11.302263 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2316 23:07:11.302343
2317 23:07:11.305916 [CATrainingPosCal] consider 1 rank data
2318 23:07:11.309150 u2DelayCellTimex100 = 270/100 ps
2319 23:07:11.312259 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2320 23:07:11.319170 CA1 delay=39 (8~70),Diff = 6 PI (28 cell)
2321 23:07:11.322429 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2322 23:07:11.325818 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2323 23:07:11.328759 CA4 delay=34 (3~65),Diff = 1 PI (4 cell)
2324 23:07:11.332628 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2325 23:07:11.332731
2326 23:07:11.335584 CA PerBit enable=1, Macro0, CA PI delay=33
2327 23:07:11.335664
2328 23:07:11.338938 [CBTSetCACLKResult] CA Dly = 33
2329 23:07:11.339018 CS Dly: 7 (0~38)
2330 23:07:11.341946 ==
2331 23:07:11.345413 Dram Type= 6, Freq= 0, CH_0, rank 1
2332 23:07:11.348735 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2333 23:07:11.348829 ==
2334 23:07:11.352091 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2335 23:07:11.358611 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2336 23:07:11.367843 [CA 0] Center 39 (8~70) winsize 63
2337 23:07:11.371585 [CA 1] Center 38 (8~69) winsize 62
2338 23:07:11.374398 [CA 2] Center 36 (5~67) winsize 63
2339 23:07:11.377936 [CA 3] Center 35 (4~66) winsize 63
2340 23:07:11.381347 [CA 4] Center 33 (3~64) winsize 62
2341 23:07:11.384589 [CA 5] Center 34 (3~65) winsize 63
2342 23:07:11.384670
2343 23:07:11.387919 [CmdBusTrainingLP45] Vref(ca) range 1: 39
2344 23:07:11.388000
2345 23:07:11.391601 [CATrainingPosCal] consider 2 rank data
2346 23:07:11.394804 u2DelayCellTimex100 = 270/100 ps
2347 23:07:11.397778 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2348 23:07:11.401622 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2349 23:07:11.407964 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2350 23:07:11.411524 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2351 23:07:11.414575 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2352 23:07:11.418020 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2353 23:07:11.418100
2354 23:07:11.421068 CA PerBit enable=1, Macro0, CA PI delay=33
2355 23:07:11.421149
2356 23:07:11.424817 [CBTSetCACLKResult] CA Dly = 33
2357 23:07:11.424898 CS Dly: 7 (0~39)
2358 23:07:11.424961
2359 23:07:11.428058 ----->DramcWriteLeveling(PI) begin...
2360 23:07:11.431202 ==
2361 23:07:11.431322 Dram Type= 6, Freq= 0, CH_0, rank 0
2362 23:07:11.437993 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2363 23:07:11.438074 ==
2364 23:07:11.441270 Write leveling (Byte 0): 28 => 28
2365 23:07:11.444673 Write leveling (Byte 1): 25 => 25
2366 23:07:11.448015 DramcWriteLeveling(PI) end<-----
2367 23:07:11.448095
2368 23:07:11.448158 ==
2369 23:07:11.451709 Dram Type= 6, Freq= 0, CH_0, rank 0
2370 23:07:11.454620 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2371 23:07:11.454702 ==
2372 23:07:11.457991 [Gating] SW mode calibration
2373 23:07:11.464636 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2374 23:07:11.467844 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2375 23:07:11.474422 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2376 23:07:11.477797 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2377 23:07:11.481523 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2378 23:07:11.487701 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2379 23:07:11.491036 0 11 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2380 23:07:11.494547 0 11 20 | B1->B0 | 3131 2c2c | 0 0 | (1 0) (0 1)
2381 23:07:11.501358 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2382 23:07:11.504353 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2383 23:07:11.507985 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2384 23:07:11.514427 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2385 23:07:11.518047 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2386 23:07:11.521225 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2387 23:07:11.527788 0 12 16 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
2388 23:07:11.531489 0 12 20 | B1->B0 | 3f3f 4444 | 0 0 | (0 0) (0 0)
2389 23:07:11.534701 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2390 23:07:11.541357 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2391 23:07:11.544606 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2392 23:07:11.547961 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2393 23:07:11.554332 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2394 23:07:11.557631 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2395 23:07:11.560986 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2396 23:07:11.567536 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2397 23:07:11.571427 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2398 23:07:11.574580 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2399 23:07:11.577800 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2400 23:07:11.584670 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2401 23:07:11.587740 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2402 23:07:11.590979 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2403 23:07:11.597582 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2404 23:07:11.601310 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2405 23:07:11.604311 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2406 23:07:11.611123 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2407 23:07:11.614255 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2408 23:07:11.617782 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2409 23:07:11.624540 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2410 23:07:11.627587 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2411 23:07:11.631017 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2412 23:07:11.637858 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2413 23:07:11.640985 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2414 23:07:11.644386 Total UI for P1: 0, mck2ui 16
2415 23:07:11.647466 best dqsien dly found for B0: ( 0, 15, 20)
2416 23:07:11.651108 Total UI for P1: 0, mck2ui 16
2417 23:07:11.654144 best dqsien dly found for B1: ( 0, 15, 20)
2418 23:07:11.657721 best DQS0 dly(MCK, UI, PI) = (0, 15, 20)
2419 23:07:11.660987 best DQS1 dly(MCK, UI, PI) = (0, 15, 20)
2420 23:07:11.661067
2421 23:07:11.664143 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 20)
2422 23:07:11.667367 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 20)
2423 23:07:11.670703 [Gating] SW calibration Done
2424 23:07:11.670784 ==
2425 23:07:11.674055 Dram Type= 6, Freq= 0, CH_0, rank 0
2426 23:07:11.677549 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2427 23:07:11.680631 ==
2428 23:07:11.680734 RX Vref Scan: 0
2429 23:07:11.680814
2430 23:07:11.684312 RX Vref 0 -> 0, step: 1
2431 23:07:11.684392
2432 23:07:11.687525 RX Delay -40 -> 252, step: 8
2433 23:07:11.690627 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2434 23:07:11.694054 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2435 23:07:11.697280 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2436 23:07:11.700981 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2437 23:07:11.708022 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2438 23:07:11.711138 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2439 23:07:11.714069 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2440 23:07:11.717270 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2441 23:07:11.720717 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2442 23:07:11.724690 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2443 23:07:11.730819 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2444 23:07:11.734070 iDelay=200, Bit 11, Center 103 (40 ~ 167) 128
2445 23:07:11.737770 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2446 23:07:11.740684 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2447 23:07:11.747392 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
2448 23:07:11.750794 iDelay=200, Bit 15, Center 115 (40 ~ 191) 152
2449 23:07:11.750875 ==
2450 23:07:11.754086 Dram Type= 6, Freq= 0, CH_0, rank 0
2451 23:07:11.757308 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2452 23:07:11.757389 ==
2453 23:07:11.757453 DQS Delay:
2454 23:07:11.760866 DQS0 = 0, DQS1 = 0
2455 23:07:11.760947 DQM Delay:
2456 23:07:11.764232 DQM0 = 115, DQM1 = 106
2457 23:07:11.764312 DQ Delay:
2458 23:07:11.767232 DQ0 =111, DQ1 =115, DQ2 =115, DQ3 =107
2459 23:07:11.770604 DQ4 =123, DQ5 =103, DQ6 =123, DQ7 =123
2460 23:07:11.774015 DQ8 =95, DQ9 =91, DQ10 =103, DQ11 =103
2461 23:07:11.777471 DQ12 =111, DQ13 =115, DQ14 =115, DQ15 =115
2462 23:07:11.777552
2463 23:07:11.781225
2464 23:07:11.781304 ==
2465 23:07:11.784184 Dram Type= 6, Freq= 0, CH_0, rank 0
2466 23:07:11.787701 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2467 23:07:11.787783 ==
2468 23:07:11.787847
2469 23:07:11.787906
2470 23:07:11.790575 TX Vref Scan disable
2471 23:07:11.790655 == TX Byte 0 ==
2472 23:07:11.794202 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2473 23:07:11.800896 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2474 23:07:11.800977 == TX Byte 1 ==
2475 23:07:11.804163 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
2476 23:07:11.810759 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
2477 23:07:11.810840 ==
2478 23:07:11.814476 Dram Type= 6, Freq= 0, CH_0, rank 0
2479 23:07:11.817487 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2480 23:07:11.817568 ==
2481 23:07:11.829819 TX Vref=22, minBit 10, minWin=24, winSum=412
2482 23:07:11.832780 TX Vref=24, minBit 8, minWin=25, winSum=421
2483 23:07:11.836335 TX Vref=26, minBit 10, minWin=25, winSum=430
2484 23:07:11.839452 TX Vref=28, minBit 8, minWin=26, winSum=436
2485 23:07:11.843291 TX Vref=30, minBit 8, minWin=26, winSum=434
2486 23:07:11.849780 TX Vref=32, minBit 11, minWin=26, winSum=436
2487 23:07:11.852830 [TxChooseVref] Worse bit 8, Min win 26, Win sum 436, Final Vref 28
2488 23:07:11.852911
2489 23:07:11.856179 Final TX Range 1 Vref 28
2490 23:07:11.856260
2491 23:07:11.856323 ==
2492 23:07:11.859623 Dram Type= 6, Freq= 0, CH_0, rank 0
2493 23:07:11.862827 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2494 23:07:11.866182 ==
2495 23:07:11.866262
2496 23:07:11.866325
2497 23:07:11.866383 TX Vref Scan disable
2498 23:07:11.869682 == TX Byte 0 ==
2499 23:07:11.872870 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2500 23:07:11.879282 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2501 23:07:11.879364 == TX Byte 1 ==
2502 23:07:11.882629 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
2503 23:07:11.889564 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
2504 23:07:11.889647
2505 23:07:11.889712 [DATLAT]
2506 23:07:11.889772 Freq=1200, CH0 RK0
2507 23:07:11.889830
2508 23:07:11.892922 DATLAT Default: 0xd
2509 23:07:11.893003 0, 0xFFFF, sum = 0
2510 23:07:11.896196 1, 0xFFFF, sum = 0
2511 23:07:11.896279 2, 0xFFFF, sum = 0
2512 23:07:11.899482 3, 0xFFFF, sum = 0
2513 23:07:11.902831 4, 0xFFFF, sum = 0
2514 23:07:11.902913 5, 0xFFFF, sum = 0
2515 23:07:11.906004 6, 0xFFFF, sum = 0
2516 23:07:11.906087 7, 0xFFFF, sum = 0
2517 23:07:11.909464 8, 0xFFFF, sum = 0
2518 23:07:11.909547 9, 0xFFFF, sum = 0
2519 23:07:11.912602 10, 0xFFFF, sum = 0
2520 23:07:11.912735 11, 0x0, sum = 1
2521 23:07:11.916395 12, 0x0, sum = 2
2522 23:07:11.916478 13, 0x0, sum = 3
2523 23:07:11.919381 14, 0x0, sum = 4
2524 23:07:11.919463 best_step = 12
2525 23:07:11.919527
2526 23:07:11.919587 ==
2527 23:07:11.922645 Dram Type= 6, Freq= 0, CH_0, rank 0
2528 23:07:11.926585 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2529 23:07:11.926667 ==
2530 23:07:11.929754 RX Vref Scan: 1
2531 23:07:11.929838
2532 23:07:11.932847 Set Vref Range= 32 -> 127
2533 23:07:11.932928
2534 23:07:11.932991 RX Vref 32 -> 127, step: 1
2535 23:07:11.933051
2536 23:07:11.936172 RX Delay -21 -> 252, step: 4
2537 23:07:11.936253
2538 23:07:11.939548 Set Vref, RX VrefLevel [Byte0]: 32
2539 23:07:11.942665 [Byte1]: 32
2540 23:07:11.946490
2541 23:07:11.946571 Set Vref, RX VrefLevel [Byte0]: 33
2542 23:07:11.949604 [Byte1]: 33
2543 23:07:11.954579
2544 23:07:11.954660 Set Vref, RX VrefLevel [Byte0]: 34
2545 23:07:11.957525 [Byte1]: 34
2546 23:07:11.962386
2547 23:07:11.962467 Set Vref, RX VrefLevel [Byte0]: 35
2548 23:07:11.965254 [Byte1]: 35
2549 23:07:11.969972
2550 23:07:11.970052 Set Vref, RX VrefLevel [Byte0]: 36
2551 23:07:11.973745 [Byte1]: 36
2552 23:07:11.978018
2553 23:07:11.978099 Set Vref, RX VrefLevel [Byte0]: 37
2554 23:07:11.981514 [Byte1]: 37
2555 23:07:11.985760
2556 23:07:11.985841 Set Vref, RX VrefLevel [Byte0]: 38
2557 23:07:11.989185 [Byte1]: 38
2558 23:07:11.993797
2559 23:07:11.993877 Set Vref, RX VrefLevel [Byte0]: 39
2560 23:07:11.997193 [Byte1]: 39
2561 23:07:12.001862
2562 23:07:12.001943 Set Vref, RX VrefLevel [Byte0]: 40
2563 23:07:12.004898 [Byte1]: 40
2564 23:07:12.009520
2565 23:07:12.009600 Set Vref, RX VrefLevel [Byte0]: 41
2566 23:07:12.012960 [Byte1]: 41
2567 23:07:12.017511
2568 23:07:12.017592 Set Vref, RX VrefLevel [Byte0]: 42
2569 23:07:12.020926 [Byte1]: 42
2570 23:07:12.025616
2571 23:07:12.025697 Set Vref, RX VrefLevel [Byte0]: 43
2572 23:07:12.028805 [Byte1]: 43
2573 23:07:12.033568
2574 23:07:12.033649 Set Vref, RX VrefLevel [Byte0]: 44
2575 23:07:12.036662 [Byte1]: 44
2576 23:07:12.041688
2577 23:07:12.041769 Set Vref, RX VrefLevel [Byte0]: 45
2578 23:07:12.044687 [Byte1]: 45
2579 23:07:12.049237
2580 23:07:12.049317 Set Vref, RX VrefLevel [Byte0]: 46
2581 23:07:12.052603 [Byte1]: 46
2582 23:07:12.057141
2583 23:07:12.057221 Set Vref, RX VrefLevel [Byte0]: 47
2584 23:07:12.060453 [Byte1]: 47
2585 23:07:12.065081
2586 23:07:12.065161 Set Vref, RX VrefLevel [Byte0]: 48
2587 23:07:12.068453 [Byte1]: 48
2588 23:07:12.073023
2589 23:07:12.073127 Set Vref, RX VrefLevel [Byte0]: 49
2590 23:07:12.076541 [Byte1]: 49
2591 23:07:12.081162
2592 23:07:12.081243 Set Vref, RX VrefLevel [Byte0]: 50
2593 23:07:12.084415 [Byte1]: 50
2594 23:07:12.088719
2595 23:07:12.088836 Set Vref, RX VrefLevel [Byte0]: 51
2596 23:07:12.092097 [Byte1]: 51
2597 23:07:12.096683
2598 23:07:12.096805 Set Vref, RX VrefLevel [Byte0]: 52
2599 23:07:12.100096 [Byte1]: 52
2600 23:07:12.104676
2601 23:07:12.104807 Set Vref, RX VrefLevel [Byte0]: 53
2602 23:07:12.108239 [Byte1]: 53
2603 23:07:12.112598
2604 23:07:12.112711 Set Vref, RX VrefLevel [Byte0]: 54
2605 23:07:12.116030 [Byte1]: 54
2606 23:07:12.120474
2607 23:07:12.120555 Set Vref, RX VrefLevel [Byte0]: 55
2608 23:07:12.123874 [Byte1]: 55
2609 23:07:12.128725
2610 23:07:12.128807 Set Vref, RX VrefLevel [Byte0]: 56
2611 23:07:12.131888 [Byte1]: 56
2612 23:07:12.136538
2613 23:07:12.136619 Set Vref, RX VrefLevel [Byte0]: 57
2614 23:07:12.139711 [Byte1]: 57
2615 23:07:12.144172
2616 23:07:12.144253 Set Vref, RX VrefLevel [Byte0]: 58
2617 23:07:12.147476 [Byte1]: 58
2618 23:07:12.152283
2619 23:07:12.152363 Set Vref, RX VrefLevel [Byte0]: 59
2620 23:07:12.155493 [Byte1]: 59
2621 23:07:12.160091
2622 23:07:12.160172 Set Vref, RX VrefLevel [Byte0]: 60
2623 23:07:12.163913 [Byte1]: 60
2624 23:07:12.167961
2625 23:07:12.168041 Set Vref, RX VrefLevel [Byte0]: 61
2626 23:07:12.171826 [Byte1]: 61
2627 23:07:12.175894
2628 23:07:12.175975 Set Vref, RX VrefLevel [Byte0]: 62
2629 23:07:12.179541 [Byte1]: 62
2630 23:07:12.183925
2631 23:07:12.184006 Set Vref, RX VrefLevel [Byte0]: 63
2632 23:07:12.187357 [Byte1]: 63
2633 23:07:12.192001
2634 23:07:12.192082 Set Vref, RX VrefLevel [Byte0]: 64
2635 23:07:12.195189 [Byte1]: 64
2636 23:07:12.199856
2637 23:07:12.199960 Set Vref, RX VrefLevel [Byte0]: 65
2638 23:07:12.203328 [Byte1]: 65
2639 23:07:12.207659
2640 23:07:12.207740 Set Vref, RX VrefLevel [Byte0]: 66
2641 23:07:12.211166 [Byte1]: 66
2642 23:07:12.215573
2643 23:07:12.215654 Final RX Vref Byte 0 = 47 to rank0
2644 23:07:12.219185 Final RX Vref Byte 1 = 42 to rank0
2645 23:07:12.222389 Final RX Vref Byte 0 = 47 to rank1
2646 23:07:12.225756 Final RX Vref Byte 1 = 42 to rank1==
2647 23:07:12.229039 Dram Type= 6, Freq= 0, CH_0, rank 0
2648 23:07:12.235803 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2649 23:07:12.235889 ==
2650 23:07:12.235954 DQS Delay:
2651 23:07:12.236015 DQS0 = 0, DQS1 = 0
2652 23:07:12.239447 DQM Delay:
2653 23:07:12.239528 DQM0 = 114, DQM1 = 103
2654 23:07:12.242481 DQ Delay:
2655 23:07:12.245775 DQ0 =112, DQ1 =114, DQ2 =112, DQ3 =108
2656 23:07:12.249078 DQ4 =118, DQ5 =104, DQ6 =124, DQ7 =120
2657 23:07:12.252447 DQ8 =92, DQ9 =84, DQ10 =104, DQ11 =96
2658 23:07:12.255758 DQ12 =110, DQ13 =110, DQ14 =116, DQ15 =114
2659 23:07:12.255838
2660 23:07:12.255902
2661 23:07:12.262504 [DQSOSCAuto] RK0, (LSB)MR18= 0x505, (MSB)MR19= 0x404, tDQSOscB0 = 408 ps tDQSOscB1 = 408 ps
2662 23:07:12.265776 CH0 RK0: MR19=404, MR18=505
2663 23:07:12.272324 CH0_RK0: MR19=0x404, MR18=0x505, DQSOSC=408, MR23=63, INC=39, DEC=26
2664 23:07:12.272406
2665 23:07:12.275622 ----->DramcWriteLeveling(PI) begin...
2666 23:07:12.275705 ==
2667 23:07:12.278835 Dram Type= 6, Freq= 0, CH_0, rank 1
2668 23:07:12.282590 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2669 23:07:12.282672 ==
2670 23:07:12.285936 Write leveling (Byte 0): 26 => 26
2671 23:07:12.288876 Write leveling (Byte 1): 23 => 23
2672 23:07:12.292455 DramcWriteLeveling(PI) end<-----
2673 23:07:12.292536
2674 23:07:12.292600 ==
2675 23:07:12.295975 Dram Type= 6, Freq= 0, CH_0, rank 1
2676 23:07:12.298798 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2677 23:07:12.302521 ==
2678 23:07:12.302602 [Gating] SW mode calibration
2679 23:07:12.312295 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2680 23:07:12.315547 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2681 23:07:12.318969 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2682 23:07:12.325980 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2683 23:07:12.329231 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2684 23:07:12.332326 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2685 23:07:12.339003 0 11 16 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 1)
2686 23:07:12.342435 0 11 20 | B1->B0 | 3131 2727 | 1 0 | (1 0) (1 0)
2687 23:07:12.345427 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2688 23:07:12.352168 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2689 23:07:12.355779 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2690 23:07:12.358894 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2691 23:07:12.366121 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2692 23:07:12.368863 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2693 23:07:12.372273 0 12 16 | B1->B0 | 2323 3534 | 0 1 | (0 0) (0 0)
2694 23:07:12.378744 0 12 20 | B1->B0 | 3e3e 4646 | 1 0 | (0 0) (0 0)
2695 23:07:12.382165 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2696 23:07:12.385434 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2697 23:07:12.389029 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2698 23:07:12.395330 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2699 23:07:12.399087 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2700 23:07:12.401985 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2701 23:07:12.408988 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2702 23:07:12.412010 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2703 23:07:12.415438 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2704 23:07:12.421943 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2705 23:07:12.425450 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2706 23:07:12.428648 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2707 23:07:12.435730 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2708 23:07:12.439024 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2709 23:07:12.442212 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2710 23:07:12.448627 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2711 23:07:12.452146 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2712 23:07:12.455545 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2713 23:07:12.461965 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2714 23:07:12.465544 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2715 23:07:12.468814 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2716 23:07:12.475534 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2717 23:07:12.478595 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2718 23:07:12.481953 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2719 23:07:12.485237 Total UI for P1: 0, mck2ui 16
2720 23:07:12.488605 best dqsien dly found for B0: ( 0, 15, 16)
2721 23:07:12.492586 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2722 23:07:12.495510 Total UI for P1: 0, mck2ui 16
2723 23:07:12.498739 best dqsien dly found for B1: ( 0, 15, 18)
2724 23:07:12.502067 best DQS0 dly(MCK, UI, PI) = (0, 15, 16)
2725 23:07:12.508813 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
2726 23:07:12.508895
2727 23:07:12.512196 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 16)
2728 23:07:12.515608 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
2729 23:07:12.518744 [Gating] SW calibration Done
2730 23:07:12.518825 ==
2731 23:07:12.522079 Dram Type= 6, Freq= 0, CH_0, rank 1
2732 23:07:12.525675 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2733 23:07:12.525757 ==
2734 23:07:12.528634 RX Vref Scan: 0
2735 23:07:12.528752
2736 23:07:12.528818 RX Vref 0 -> 0, step: 1
2737 23:07:12.528879
2738 23:07:12.532357 RX Delay -40 -> 252, step: 8
2739 23:07:12.535236 iDelay=200, Bit 0, Center 107 (32 ~ 183) 152
2740 23:07:12.538770 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2741 23:07:12.545337 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2742 23:07:12.548562 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2743 23:07:12.551736 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2744 23:07:12.555195 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2745 23:07:12.558399 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2746 23:07:12.565059 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2747 23:07:12.568642 iDelay=200, Bit 8, Center 95 (32 ~ 159) 128
2748 23:07:12.571961 iDelay=200, Bit 9, Center 87 (16 ~ 159) 144
2749 23:07:12.575626 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2750 23:07:12.578743 iDelay=200, Bit 11, Center 95 (32 ~ 159) 128
2751 23:07:12.585294 iDelay=200, Bit 12, Center 111 (48 ~ 175) 128
2752 23:07:12.588709 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2753 23:07:12.591643 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
2754 23:07:12.595065 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2755 23:07:12.595147 ==
2756 23:07:12.598617 Dram Type= 6, Freq= 0, CH_0, rank 1
2757 23:07:12.605219 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2758 23:07:12.605301 ==
2759 23:07:12.605365 DQS Delay:
2760 23:07:12.605423 DQS0 = 0, DQS1 = 0
2761 23:07:12.608562 DQM Delay:
2762 23:07:12.608669 DQM0 = 114, DQM1 = 104
2763 23:07:12.611759 DQ Delay:
2764 23:07:12.615146 DQ0 =107, DQ1 =115, DQ2 =115, DQ3 =111
2765 23:07:12.618465 DQ4 =115, DQ5 =107, DQ6 =123, DQ7 =123
2766 23:07:12.621855 DQ8 =95, DQ9 =87, DQ10 =107, DQ11 =95
2767 23:07:12.625056 DQ12 =111, DQ13 =111, DQ14 =111, DQ15 =115
2768 23:07:12.625147
2769 23:07:12.625212
2770 23:07:12.625271 ==
2771 23:07:12.628091 Dram Type= 6, Freq= 0, CH_0, rank 1
2772 23:07:12.631503 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2773 23:07:12.634960 ==
2774 23:07:12.635042
2775 23:07:12.635105
2776 23:07:12.635165 TX Vref Scan disable
2777 23:07:12.638370 == TX Byte 0 ==
2778 23:07:12.641404 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2779 23:07:12.644790 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2780 23:07:12.647979 == TX Byte 1 ==
2781 23:07:12.651196 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
2782 23:07:12.654634 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
2783 23:07:12.658019 ==
2784 23:07:12.658100 Dram Type= 6, Freq= 0, CH_0, rank 1
2785 23:07:12.664489 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2786 23:07:12.664571 ==
2787 23:07:12.675866 TX Vref=22, minBit 8, minWin=25, winSum=413
2788 23:07:12.679199 TX Vref=24, minBit 1, minWin=25, winSum=417
2789 23:07:12.682559 TX Vref=26, minBit 8, minWin=25, winSum=423
2790 23:07:12.685850 TX Vref=28, minBit 8, minWin=25, winSum=428
2791 23:07:12.689133 TX Vref=30, minBit 1, minWin=26, winSum=431
2792 23:07:12.692635 TX Vref=32, minBit 8, minWin=25, winSum=426
2793 23:07:12.698880 [TxChooseVref] Worse bit 1, Min win 26, Win sum 431, Final Vref 30
2794 23:07:12.698962
2795 23:07:12.702568 Final TX Range 1 Vref 30
2796 23:07:12.702649
2797 23:07:12.702713 ==
2798 23:07:12.705578 Dram Type= 6, Freq= 0, CH_0, rank 1
2799 23:07:12.709072 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2800 23:07:12.709154 ==
2801 23:07:12.709219
2802 23:07:12.712336
2803 23:07:12.712416 TX Vref Scan disable
2804 23:07:12.715569 == TX Byte 0 ==
2805 23:07:12.719018 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2806 23:07:12.722076 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2807 23:07:12.725817 == TX Byte 1 ==
2808 23:07:12.729088 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
2809 23:07:12.732372 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
2810 23:07:12.732453
2811 23:07:12.735486 [DATLAT]
2812 23:07:12.735567 Freq=1200, CH0 RK1
2813 23:07:12.735632
2814 23:07:12.739161 DATLAT Default: 0xc
2815 23:07:12.739242 0, 0xFFFF, sum = 0
2816 23:07:12.742310 1, 0xFFFF, sum = 0
2817 23:07:12.742393 2, 0xFFFF, sum = 0
2818 23:07:12.745671 3, 0xFFFF, sum = 0
2819 23:07:12.745752 4, 0xFFFF, sum = 0
2820 23:07:12.748877 5, 0xFFFF, sum = 0
2821 23:07:12.748960 6, 0xFFFF, sum = 0
2822 23:07:12.752125 7, 0xFFFF, sum = 0
2823 23:07:12.752207 8, 0xFFFF, sum = 0
2824 23:07:12.755729 9, 0xFFFF, sum = 0
2825 23:07:12.758886 10, 0xFFFF, sum = 0
2826 23:07:12.758968 11, 0x0, sum = 1
2827 23:07:12.759034 12, 0x0, sum = 2
2828 23:07:12.762354 13, 0x0, sum = 3
2829 23:07:12.762436 14, 0x0, sum = 4
2830 23:07:12.766018 best_step = 12
2831 23:07:12.766098
2832 23:07:12.766162 ==
2833 23:07:12.768924 Dram Type= 6, Freq= 0, CH_0, rank 1
2834 23:07:12.772451 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2835 23:07:12.772533 ==
2836 23:07:12.775738 RX Vref Scan: 0
2837 23:07:12.775819
2838 23:07:12.775884 RX Vref 0 -> 0, step: 1
2839 23:07:12.775944
2840 23:07:12.779122 RX Delay -29 -> 252, step: 4
2841 23:07:12.785760 iDelay=199, Bit 0, Center 110 (39 ~ 182) 144
2842 23:07:12.789342 iDelay=199, Bit 1, Center 116 (43 ~ 190) 148
2843 23:07:12.792538 iDelay=199, Bit 2, Center 112 (43 ~ 182) 140
2844 23:07:12.795880 iDelay=199, Bit 3, Center 108 (39 ~ 178) 140
2845 23:07:12.799142 iDelay=199, Bit 4, Center 118 (47 ~ 190) 144
2846 23:07:12.805831 iDelay=199, Bit 5, Center 108 (39 ~ 178) 140
2847 23:07:12.809333 iDelay=199, Bit 6, Center 124 (55 ~ 194) 140
2848 23:07:12.812492 iDelay=199, Bit 7, Center 124 (51 ~ 198) 148
2849 23:07:12.815704 iDelay=199, Bit 8, Center 90 (27 ~ 154) 128
2850 23:07:12.819137 iDelay=199, Bit 9, Center 86 (23 ~ 150) 128
2851 23:07:12.825896 iDelay=199, Bit 10, Center 106 (39 ~ 174) 136
2852 23:07:12.829459 iDelay=199, Bit 11, Center 94 (35 ~ 154) 120
2853 23:07:12.832672 iDelay=199, Bit 12, Center 110 (47 ~ 174) 128
2854 23:07:12.835990 iDelay=199, Bit 13, Center 110 (47 ~ 174) 128
2855 23:07:12.839196 iDelay=199, Bit 14, Center 116 (55 ~ 178) 124
2856 23:07:12.845975 iDelay=199, Bit 15, Center 114 (51 ~ 178) 128
2857 23:07:12.846056 ==
2858 23:07:12.849296 Dram Type= 6, Freq= 0, CH_0, rank 1
2859 23:07:12.852342 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2860 23:07:12.852424 ==
2861 23:07:12.852489 DQS Delay:
2862 23:07:12.855717 DQS0 = 0, DQS1 = 0
2863 23:07:12.855798 DQM Delay:
2864 23:07:12.859079 DQM0 = 115, DQM1 = 103
2865 23:07:12.859160 DQ Delay:
2866 23:07:12.862433 DQ0 =110, DQ1 =116, DQ2 =112, DQ3 =108
2867 23:07:12.865812 DQ4 =118, DQ5 =108, DQ6 =124, DQ7 =124
2868 23:07:12.869063 DQ8 =90, DQ9 =86, DQ10 =106, DQ11 =94
2869 23:07:12.872661 DQ12 =110, DQ13 =110, DQ14 =116, DQ15 =114
2870 23:07:12.872794
2871 23:07:12.872859
2872 23:07:12.882327 [DQSOSCAuto] RK1, (LSB)MR18= 0x1313, (MSB)MR19= 0x404, tDQSOscB0 = 402 ps tDQSOscB1 = 402 ps
2873 23:07:12.885704 CH0 RK1: MR19=404, MR18=1313
2874 23:07:12.888775 CH0_RK1: MR19=0x404, MR18=0x1313, DQSOSC=402, MR23=63, INC=40, DEC=27
2875 23:07:12.892102 [RxdqsGatingPostProcess] freq 1200
2876 23:07:12.898932 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2877 23:07:12.902172 Pre-setting of DQS Precalculation
2878 23:07:12.905481 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
2879 23:07:12.908676 ==
2880 23:07:12.912301 Dram Type= 6, Freq= 0, CH_1, rank 0
2881 23:07:12.915340 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2882 23:07:12.915422 ==
2883 23:07:12.918739 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2884 23:07:12.925721 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2885 23:07:12.934598 [CA 0] Center 37 (7~68) winsize 62
2886 23:07:12.937719 [CA 1] Center 37 (7~68) winsize 62
2887 23:07:12.941496 [CA 2] Center 34 (4~65) winsize 62
2888 23:07:12.944721 [CA 3] Center 33 (3~64) winsize 62
2889 23:07:12.947946 [CA 4] Center 32 (2~63) winsize 62
2890 23:07:12.951352 [CA 5] Center 32 (1~63) winsize 63
2891 23:07:12.951433
2892 23:07:12.954465 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2893 23:07:12.954546
2894 23:07:12.958065 [CATrainingPosCal] consider 1 rank data
2895 23:07:12.961108 u2DelayCellTimex100 = 270/100 ps
2896 23:07:12.964627 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2897 23:07:12.967778 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2898 23:07:12.974693 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2899 23:07:12.978083 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2900 23:07:12.981098 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
2901 23:07:12.984254 CA5 delay=32 (1~63),Diff = 0 PI (0 cell)
2902 23:07:12.984335
2903 23:07:12.987654 CA PerBit enable=1, Macro0, CA PI delay=32
2904 23:07:12.987735
2905 23:07:12.991265 [CBTSetCACLKResult] CA Dly = 32
2906 23:07:12.991346 CS Dly: 5 (0~36)
2907 23:07:12.994471 ==
2908 23:07:12.994553 Dram Type= 6, Freq= 0, CH_1, rank 1
2909 23:07:13.000999 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2910 23:07:13.001082 ==
2911 23:07:13.004308 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2912 23:07:13.010902 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2913 23:07:13.019738 [CA 0] Center 37 (6~68) winsize 63
2914 23:07:13.023386 [CA 1] Center 37 (6~68) winsize 63
2915 23:07:13.026706 [CA 2] Center 34 (3~65) winsize 63
2916 23:07:13.029791 [CA 3] Center 33 (3~64) winsize 62
2917 23:07:13.033162 [CA 4] Center 32 (2~63) winsize 62
2918 23:07:13.036575 [CA 5] Center 32 (2~63) winsize 62
2919 23:07:13.036657
2920 23:07:13.039752 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2921 23:07:13.039833
2922 23:07:13.043237 [CATrainingPosCal] consider 2 rank data
2923 23:07:13.046287 u2DelayCellTimex100 = 270/100 ps
2924 23:07:13.049948 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2925 23:07:13.053322 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2926 23:07:13.059900 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2927 23:07:13.062869 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2928 23:07:13.066222 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
2929 23:07:13.069701 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
2930 23:07:13.069782
2931 23:07:13.073190 CA PerBit enable=1, Macro0, CA PI delay=32
2932 23:07:13.073271
2933 23:07:13.076364 [CBTSetCACLKResult] CA Dly = 32
2934 23:07:13.076445 CS Dly: 6 (0~38)
2935 23:07:13.076510
2936 23:07:13.079633 ----->DramcWriteLeveling(PI) begin...
2937 23:07:13.083035 ==
2938 23:07:13.086684 Dram Type= 6, Freq= 0, CH_1, rank 0
2939 23:07:13.089810 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2940 23:07:13.089891 ==
2941 23:07:13.092804 Write leveling (Byte 0): 21 => 21
2942 23:07:13.096472 Write leveling (Byte 1): 21 => 21
2943 23:07:13.099572 DramcWriteLeveling(PI) end<-----
2944 23:07:13.099652
2945 23:07:13.099717 ==
2946 23:07:13.103188 Dram Type= 6, Freq= 0, CH_1, rank 0
2947 23:07:13.106181 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2948 23:07:13.106263 ==
2949 23:07:13.109935 [Gating] SW mode calibration
2950 23:07:13.116390 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2951 23:07:13.119612 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2952 23:07:13.126225 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2953 23:07:13.129664 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2954 23:07:13.132911 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2955 23:07:13.139529 0 11 12 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
2956 23:07:13.142831 0 11 16 | B1->B0 | 2f2f 2929 | 0 0 | (0 0) (1 0)
2957 23:07:13.146190 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2958 23:07:13.152587 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2959 23:07:13.156234 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2960 23:07:13.159546 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2961 23:07:13.166426 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2962 23:07:13.169493 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2963 23:07:13.172593 0 12 12 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
2964 23:07:13.179134 0 12 16 | B1->B0 | 3030 4141 | 0 0 | (0 0) (0 0)
2965 23:07:13.182761 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2966 23:07:13.185810 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2967 23:07:13.192455 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2968 23:07:13.196120 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2969 23:07:13.199114 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2970 23:07:13.206071 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2971 23:07:13.209129 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2972 23:07:13.212489 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2973 23:07:13.219481 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2974 23:07:13.222810 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2975 23:07:13.226092 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2976 23:07:13.232476 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2977 23:07:13.235722 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2978 23:07:13.239191 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2979 23:07:13.246004 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2980 23:07:13.249474 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2981 23:07:13.252449 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2982 23:07:13.256018 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2983 23:07:13.262549 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2984 23:07:13.265815 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2985 23:07:13.269078 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2986 23:07:13.276140 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2987 23:07:13.279104 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2988 23:07:13.282556 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2989 23:07:13.289153 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2990 23:07:13.289237 Total UI for P1: 0, mck2ui 16
2991 23:07:13.295863 best dqsien dly found for B0: ( 0, 15, 14)
2992 23:07:13.299134 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2993 23:07:13.302839 Total UI for P1: 0, mck2ui 16
2994 23:07:13.305768 best dqsien dly found for B1: ( 0, 15, 20)
2995 23:07:13.309388 best DQS0 dly(MCK, UI, PI) = (0, 15, 14)
2996 23:07:13.312298 best DQS1 dly(MCK, UI, PI) = (0, 15, 20)
2997 23:07:13.312379
2998 23:07:13.316101 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 14)
2999 23:07:13.319275 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 20)
3000 23:07:13.322655 [Gating] SW calibration Done
3001 23:07:13.322736 ==
3002 23:07:13.325897 Dram Type= 6, Freq= 0, CH_1, rank 0
3003 23:07:13.329473 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3004 23:07:13.332329 ==
3005 23:07:13.332410 RX Vref Scan: 0
3006 23:07:13.332474
3007 23:07:13.335902 RX Vref 0 -> 0, step: 1
3008 23:07:13.335984
3009 23:07:13.339105 RX Delay -40 -> 252, step: 8
3010 23:07:13.342561 iDelay=208, Bit 0, Center 119 (40 ~ 199) 160
3011 23:07:13.345506 iDelay=208, Bit 1, Center 107 (32 ~ 183) 152
3012 23:07:13.349039 iDelay=208, Bit 2, Center 107 (32 ~ 183) 152
3013 23:07:13.352290 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3014 23:07:13.358927 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3015 23:07:13.362394 iDelay=208, Bit 5, Center 127 (48 ~ 207) 160
3016 23:07:13.365673 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3017 23:07:13.368887 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3018 23:07:13.372370 iDelay=208, Bit 8, Center 87 (16 ~ 159) 144
3019 23:07:13.378850 iDelay=208, Bit 9, Center 95 (24 ~ 167) 144
3020 23:07:13.382308 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3021 23:07:13.385751 iDelay=208, Bit 11, Center 99 (32 ~ 167) 136
3022 23:07:13.388915 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3023 23:07:13.392409 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3024 23:07:13.398880 iDelay=208, Bit 14, Center 115 (48 ~ 183) 136
3025 23:07:13.402135 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3026 23:07:13.402217 ==
3027 23:07:13.405456 Dram Type= 6, Freq= 0, CH_1, rank 0
3028 23:07:13.408970 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3029 23:07:13.409051 ==
3030 23:07:13.412227 DQS Delay:
3031 23:07:13.412308 DQS0 = 0, DQS1 = 0
3032 23:07:13.412372 DQM Delay:
3033 23:07:13.415572 DQM0 = 116, DQM1 = 108
3034 23:07:13.415653 DQ Delay:
3035 23:07:13.419143 DQ0 =119, DQ1 =107, DQ2 =107, DQ3 =115
3036 23:07:13.421980 DQ4 =115, DQ5 =127, DQ6 =123, DQ7 =115
3037 23:07:13.425431 DQ8 =87, DQ9 =95, DQ10 =111, DQ11 =99
3038 23:07:13.428744 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3039 23:07:13.432081
3040 23:07:13.432161
3041 23:07:13.432226 ==
3042 23:07:13.435520 Dram Type= 6, Freq= 0, CH_1, rank 0
3043 23:07:13.438875 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3044 23:07:13.438957 ==
3045 23:07:13.439021
3046 23:07:13.439080
3047 23:07:13.442459 TX Vref Scan disable
3048 23:07:13.442540 == TX Byte 0 ==
3049 23:07:13.448809 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3050 23:07:13.452178 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3051 23:07:13.452260 == TX Byte 1 ==
3052 23:07:13.458947 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3053 23:07:13.462016 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3054 23:07:13.462098 ==
3055 23:07:13.465923 Dram Type= 6, Freq= 0, CH_1, rank 0
3056 23:07:13.468617 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3057 23:07:13.468698 ==
3058 23:07:13.480767 TX Vref=22, minBit 1, minWin=25, winSum=415
3059 23:07:13.484233 TX Vref=24, minBit 9, minWin=25, winSum=422
3060 23:07:13.487351 TX Vref=26, minBit 0, minWin=26, winSum=425
3061 23:07:13.490667 TX Vref=28, minBit 3, minWin=26, winSum=429
3062 23:07:13.494092 TX Vref=30, minBit 0, minWin=26, winSum=431
3063 23:07:13.497724 TX Vref=32, minBit 1, minWin=26, winSum=427
3064 23:07:13.504179 [TxChooseVref] Worse bit 0, Min win 26, Win sum 431, Final Vref 30
3065 23:07:13.504261
3066 23:07:13.507757 Final TX Range 1 Vref 30
3067 23:07:13.507839
3068 23:07:13.507903 ==
3069 23:07:13.510764 Dram Type= 6, Freq= 0, CH_1, rank 0
3070 23:07:13.513934 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3071 23:07:13.514016 ==
3072 23:07:13.514080
3073 23:07:13.517529
3074 23:07:13.517609 TX Vref Scan disable
3075 23:07:13.520601 == TX Byte 0 ==
3076 23:07:13.524020 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3077 23:07:13.527366 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3078 23:07:13.530651 == TX Byte 1 ==
3079 23:07:13.534084 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3080 23:07:13.537229 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3081 23:07:13.537311
3082 23:07:13.540641 [DATLAT]
3083 23:07:13.540727 Freq=1200, CH1 RK0
3084 23:07:13.540792
3085 23:07:13.544142 DATLAT Default: 0xd
3086 23:07:13.544223 0, 0xFFFF, sum = 0
3087 23:07:13.547156 1, 0xFFFF, sum = 0
3088 23:07:13.547238 2, 0xFFFF, sum = 0
3089 23:07:13.550410 3, 0xFFFF, sum = 0
3090 23:07:13.550492 4, 0xFFFF, sum = 0
3091 23:07:13.554172 5, 0xFFFF, sum = 0
3092 23:07:13.554254 6, 0xFFFF, sum = 0
3093 23:07:13.557118 7, 0xFFFF, sum = 0
3094 23:07:13.560574 8, 0xFFFF, sum = 0
3095 23:07:13.560656 9, 0xFFFF, sum = 0
3096 23:07:13.564196 10, 0xFFFF, sum = 0
3097 23:07:13.564278 11, 0x0, sum = 1
3098 23:07:13.564343 12, 0x0, sum = 2
3099 23:07:13.567379 13, 0x0, sum = 3
3100 23:07:13.567460 14, 0x0, sum = 4
3101 23:07:13.570411 best_step = 12
3102 23:07:13.570492
3103 23:07:13.570555 ==
3104 23:07:13.573776 Dram Type= 6, Freq= 0, CH_1, rank 0
3105 23:07:13.577244 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3106 23:07:13.577326 ==
3107 23:07:13.580660 RX Vref Scan: 1
3108 23:07:13.580760
3109 23:07:13.580826 Set Vref Range= 32 -> 127
3110 23:07:13.583850
3111 23:07:13.583942 RX Vref 32 -> 127, step: 1
3112 23:07:13.584045
3113 23:07:13.587577 RX Delay -29 -> 252, step: 4
3114 23:07:13.587658
3115 23:07:13.590541 Set Vref, RX VrefLevel [Byte0]: 32
3116 23:07:13.594149 [Byte1]: 32
3117 23:07:13.597449
3118 23:07:13.597530 Set Vref, RX VrefLevel [Byte0]: 33
3119 23:07:13.600416 [Byte1]: 33
3120 23:07:13.605182
3121 23:07:13.605264 Set Vref, RX VrefLevel [Byte0]: 34
3122 23:07:13.608820 [Byte1]: 34
3123 23:07:13.613180
3124 23:07:13.613260 Set Vref, RX VrefLevel [Byte0]: 35
3125 23:07:13.616585 [Byte1]: 35
3126 23:07:13.620995
3127 23:07:13.621075 Set Vref, RX VrefLevel [Byte0]: 36
3128 23:07:13.624367 [Byte1]: 36
3129 23:07:13.628935
3130 23:07:13.629016 Set Vref, RX VrefLevel [Byte0]: 37
3131 23:07:13.632397 [Byte1]: 37
3132 23:07:13.637428
3133 23:07:13.637508 Set Vref, RX VrefLevel [Byte0]: 38
3134 23:07:13.640272 [Byte1]: 38
3135 23:07:13.645235
3136 23:07:13.645315 Set Vref, RX VrefLevel [Byte0]: 39
3137 23:07:13.648499 [Byte1]: 39
3138 23:07:13.652734
3139 23:07:13.652815 Set Vref, RX VrefLevel [Byte0]: 40
3140 23:07:13.656208 [Byte1]: 40
3141 23:07:13.660868
3142 23:07:13.660949 Set Vref, RX VrefLevel [Byte0]: 41
3143 23:07:13.664235 [Byte1]: 41
3144 23:07:13.668950
3145 23:07:13.669030 Set Vref, RX VrefLevel [Byte0]: 42
3146 23:07:13.671885 [Byte1]: 42
3147 23:07:13.676703
3148 23:07:13.676827 Set Vref, RX VrefLevel [Byte0]: 43
3149 23:07:13.680098 [Byte1]: 43
3150 23:07:13.684548
3151 23:07:13.684630 Set Vref, RX VrefLevel [Byte0]: 44
3152 23:07:13.687816 [Byte1]: 44
3153 23:07:13.692698
3154 23:07:13.692822 Set Vref, RX VrefLevel [Byte0]: 45
3155 23:07:13.696346 [Byte1]: 45
3156 23:07:13.700586
3157 23:07:13.700696 Set Vref, RX VrefLevel [Byte0]: 46
3158 23:07:13.703921 [Byte1]: 46
3159 23:07:13.708674
3160 23:07:13.708808 Set Vref, RX VrefLevel [Byte0]: 47
3161 23:07:13.711859 [Byte1]: 47
3162 23:07:13.716525
3163 23:07:13.716605 Set Vref, RX VrefLevel [Byte0]: 48
3164 23:07:13.719953 [Byte1]: 48
3165 23:07:13.724530
3166 23:07:13.724611 Set Vref, RX VrefLevel [Byte0]: 49
3167 23:07:13.727921 [Byte1]: 49
3168 23:07:13.732336
3169 23:07:13.732417 Set Vref, RX VrefLevel [Byte0]: 50
3170 23:07:13.735798 [Byte1]: 50
3171 23:07:13.740585
3172 23:07:13.740666 Set Vref, RX VrefLevel [Byte0]: 51
3173 23:07:13.743558 [Byte1]: 51
3174 23:07:13.748326
3175 23:07:13.748407 Set Vref, RX VrefLevel [Byte0]: 52
3176 23:07:13.751683 [Byte1]: 52
3177 23:07:13.756096
3178 23:07:13.756177 Set Vref, RX VrefLevel [Byte0]: 53
3179 23:07:13.759558 [Byte1]: 53
3180 23:07:13.764194
3181 23:07:13.764275 Set Vref, RX VrefLevel [Byte0]: 54
3182 23:07:13.767384 [Byte1]: 54
3183 23:07:13.772206
3184 23:07:13.772286 Set Vref, RX VrefLevel [Byte0]: 55
3185 23:07:13.775370 [Byte1]: 55
3186 23:07:13.780144
3187 23:07:13.780225 Set Vref, RX VrefLevel [Byte0]: 56
3188 23:07:13.783449 [Byte1]: 56
3189 23:07:13.787957
3190 23:07:13.788037 Set Vref, RX VrefLevel [Byte0]: 57
3191 23:07:13.791676 [Byte1]: 57
3192 23:07:13.796088
3193 23:07:13.796168 Set Vref, RX VrefLevel [Byte0]: 58
3194 23:07:13.799720 [Byte1]: 58
3195 23:07:13.804161
3196 23:07:13.804243 Set Vref, RX VrefLevel [Byte0]: 59
3197 23:07:13.807596 [Byte1]: 59
3198 23:07:13.811996
3199 23:07:13.812076 Set Vref, RX VrefLevel [Byte0]: 60
3200 23:07:13.815201 [Byte1]: 60
3201 23:07:13.820495
3202 23:07:13.820576 Set Vref, RX VrefLevel [Byte0]: 61
3203 23:07:13.823436 [Byte1]: 61
3204 23:07:13.827993
3205 23:07:13.828073 Set Vref, RX VrefLevel [Byte0]: 62
3206 23:07:13.831204 [Byte1]: 62
3207 23:07:13.835869
3208 23:07:13.835950 Set Vref, RX VrefLevel [Byte0]: 63
3209 23:07:13.839242 [Byte1]: 63
3210 23:07:13.844114
3211 23:07:13.844194 Set Vref, RX VrefLevel [Byte0]: 64
3212 23:07:13.847206 [Byte1]: 64
3213 23:07:13.851991
3214 23:07:13.852071 Set Vref, RX VrefLevel [Byte0]: 65
3215 23:07:13.855054 [Byte1]: 65
3216 23:07:13.859749
3217 23:07:13.859830 Set Vref, RX VrefLevel [Byte0]: 66
3218 23:07:13.863366 [Byte1]: 66
3219 23:07:13.867827
3220 23:07:13.867910 Final RX Vref Byte 0 = 51 to rank0
3221 23:07:13.870877 Final RX Vref Byte 1 = 50 to rank0
3222 23:07:13.874488 Final RX Vref Byte 0 = 51 to rank1
3223 23:07:13.877830 Final RX Vref Byte 1 = 50 to rank1==
3224 23:07:13.881235 Dram Type= 6, Freq= 0, CH_1, rank 0
3225 23:07:13.887879 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3226 23:07:13.887961 ==
3227 23:07:13.888026 DQS Delay:
3228 23:07:13.888086 DQS0 = 0, DQS1 = 0
3229 23:07:13.890967 DQM Delay:
3230 23:07:13.891048 DQM0 = 115, DQM1 = 106
3231 23:07:13.894398 DQ Delay:
3232 23:07:13.897851 DQ0 =120, DQ1 =110, DQ2 =106, DQ3 =114
3233 23:07:13.901077 DQ4 =114, DQ5 =126, DQ6 =122, DQ7 =112
3234 23:07:13.904296 DQ8 =86, DQ9 =94, DQ10 =108, DQ11 =98
3235 23:07:13.907597 DQ12 =114, DQ13 =116, DQ14 =116, DQ15 =116
3236 23:07:13.907679
3237 23:07:13.907743
3238 23:07:13.914402 [DQSOSCAuto] RK0, (LSB)MR18= 0x1c1c, (MSB)MR19= 0x404, tDQSOscB0 = 399 ps tDQSOscB1 = 399 ps
3239 23:07:13.917597 CH1 RK0: MR19=404, MR18=1C1C
3240 23:07:13.924307 CH1_RK0: MR19=0x404, MR18=0x1C1C, DQSOSC=399, MR23=63, INC=41, DEC=27
3241 23:07:13.924389
3242 23:07:13.927627 ----->DramcWriteLeveling(PI) begin...
3243 23:07:13.927710 ==
3244 23:07:13.931273 Dram Type= 6, Freq= 0, CH_1, rank 1
3245 23:07:13.934288 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3246 23:07:13.934371 ==
3247 23:07:13.937823 Write leveling (Byte 0): 21 => 21
3248 23:07:13.940873 Write leveling (Byte 1): 21 => 21
3249 23:07:13.944445 DramcWriteLeveling(PI) end<-----
3250 23:07:13.944526
3251 23:07:13.944590 ==
3252 23:07:13.947730 Dram Type= 6, Freq= 0, CH_1, rank 1
3253 23:07:13.954701 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3254 23:07:13.954782 ==
3255 23:07:13.954846 [Gating] SW mode calibration
3256 23:07:13.964399 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3257 23:07:13.967685 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
3258 23:07:13.971198 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3259 23:07:13.977461 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3260 23:07:13.980685 0 11 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
3261 23:07:13.984169 0 11 12 | B1->B0 | 3434 2b2b | 1 1 | (1 1) (1 0)
3262 23:07:13.990918 0 11 16 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (0 0)
3263 23:07:13.994472 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3264 23:07:13.997663 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3265 23:07:14.004195 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3266 23:07:14.007415 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3267 23:07:14.010622 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3268 23:07:14.017380 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3269 23:07:14.020659 0 12 12 | B1->B0 | 2323 3d3d | 0 0 | (0 0) (0 0)
3270 23:07:14.023981 0 12 16 | B1->B0 | 3c3c 4646 | 0 0 | (1 1) (0 0)
3271 23:07:14.030666 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3272 23:07:14.034096 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3273 23:07:14.037522 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3274 23:07:14.044040 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3275 23:07:14.047679 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3276 23:07:14.050857 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3277 23:07:14.057333 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3278 23:07:14.060649 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3279 23:07:14.063997 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3280 23:07:14.070660 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3281 23:07:14.074284 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3282 23:07:14.077059 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3283 23:07:14.084033 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3284 23:07:14.087178 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3285 23:07:14.090716 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3286 23:07:14.093876 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3287 23:07:14.100643 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3288 23:07:14.103796 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3289 23:07:14.107131 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3290 23:07:14.113807 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3291 23:07:14.117020 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3292 23:07:14.120512 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3293 23:07:14.127267 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3294 23:07:14.130742 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3295 23:07:14.133651 Total UI for P1: 0, mck2ui 16
3296 23:07:14.137035 best dqsien dly found for B0: ( 0, 15, 12)
3297 23:07:14.140390 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3298 23:07:14.147409 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3299 23:07:14.147490 Total UI for P1: 0, mck2ui 16
3300 23:07:14.153555 best dqsien dly found for B1: ( 0, 15, 18)
3301 23:07:14.156992 best DQS0 dly(MCK, UI, PI) = (0, 15, 12)
3302 23:07:14.160304 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
3303 23:07:14.160383
3304 23:07:14.163741 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 12)
3305 23:07:14.166939 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
3306 23:07:14.170208 [Gating] SW calibration Done
3307 23:07:14.170287 ==
3308 23:07:14.174106 Dram Type= 6, Freq= 0, CH_1, rank 1
3309 23:07:14.176928 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3310 23:07:14.177034 ==
3311 23:07:14.180399 RX Vref Scan: 0
3312 23:07:14.180478
3313 23:07:14.180541 RX Vref 0 -> 0, step: 1
3314 23:07:14.180599
3315 23:07:14.183442 RX Delay -40 -> 252, step: 8
3316 23:07:14.187128 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3317 23:07:14.193681 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3318 23:07:14.196938 iDelay=200, Bit 2, Center 107 (32 ~ 183) 152
3319 23:07:14.200125 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3320 23:07:14.203972 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3321 23:07:14.206837 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3322 23:07:14.213425 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3323 23:07:14.216920 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3324 23:07:14.220549 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
3325 23:07:14.223587 iDelay=200, Bit 9, Center 91 (16 ~ 167) 152
3326 23:07:14.226738 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
3327 23:07:14.233388 iDelay=200, Bit 11, Center 99 (24 ~ 175) 152
3328 23:07:14.236729 iDelay=200, Bit 12, Center 115 (40 ~ 191) 152
3329 23:07:14.240035 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
3330 23:07:14.243501 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3331 23:07:14.246858 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3332 23:07:14.250345 ==
3333 23:07:14.250425 Dram Type= 6, Freq= 0, CH_1, rank 1
3334 23:07:14.257128 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3335 23:07:14.257210 ==
3336 23:07:14.257274 DQS Delay:
3337 23:07:14.260293 DQS0 = 0, DQS1 = 0
3338 23:07:14.260373 DQM Delay:
3339 23:07:14.263444 DQM0 = 115, DQM1 = 105
3340 23:07:14.263524 DQ Delay:
3341 23:07:14.267139 DQ0 =119, DQ1 =107, DQ2 =107, DQ3 =115
3342 23:07:14.270175 DQ4 =115, DQ5 =123, DQ6 =123, DQ7 =115
3343 23:07:14.273521 DQ8 =91, DQ9 =91, DQ10 =107, DQ11 =99
3344 23:07:14.276839 DQ12 =115, DQ13 =115, DQ14 =115, DQ15 =111
3345 23:07:14.276952
3346 23:07:14.277017
3347 23:07:14.277077 ==
3348 23:07:14.280959 Dram Type= 6, Freq= 0, CH_1, rank 1
3349 23:07:14.283896 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3350 23:07:14.287213 ==
3351 23:07:14.287294
3352 23:07:14.287357
3353 23:07:14.287416 TX Vref Scan disable
3354 23:07:14.290299 == TX Byte 0 ==
3355 23:07:14.293507 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3356 23:07:14.297221 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3357 23:07:14.300278 == TX Byte 1 ==
3358 23:07:14.303589 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3359 23:07:14.306873 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3360 23:07:14.310203 ==
3361 23:07:14.310285 Dram Type= 6, Freq= 0, CH_1, rank 1
3362 23:07:14.316850 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3363 23:07:14.316932 ==
3364 23:07:14.327939 TX Vref=22, minBit 9, minWin=25, winSum=425
3365 23:07:14.330964 TX Vref=24, minBit 0, minWin=26, winSum=424
3366 23:07:14.334220 TX Vref=26, minBit 3, minWin=26, winSum=429
3367 23:07:14.337921 TX Vref=28, minBit 8, minWin=26, winSum=431
3368 23:07:14.341025 TX Vref=30, minBit 9, minWin=26, winSum=436
3369 23:07:14.344243 TX Vref=32, minBit 9, minWin=26, winSum=433
3370 23:07:14.350820 [TxChooseVref] Worse bit 9, Min win 26, Win sum 436, Final Vref 30
3371 23:07:14.350902
3372 23:07:14.354287 Final TX Range 1 Vref 30
3373 23:07:14.354368
3374 23:07:14.354432 ==
3375 23:07:14.357955 Dram Type= 6, Freq= 0, CH_1, rank 1
3376 23:07:14.360933 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3377 23:07:14.361015 ==
3378 23:07:14.361079
3379 23:07:14.364178
3380 23:07:14.364258 TX Vref Scan disable
3381 23:07:14.367951 == TX Byte 0 ==
3382 23:07:14.371001 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3383 23:07:14.374343 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3384 23:07:14.377815 == TX Byte 1 ==
3385 23:07:14.381069 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3386 23:07:14.384638 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3387 23:07:14.384759
3388 23:07:14.387841 [DATLAT]
3389 23:07:14.387921 Freq=1200, CH1 RK1
3390 23:07:14.387984
3391 23:07:14.391337 DATLAT Default: 0xc
3392 23:07:14.391416 0, 0xFFFF, sum = 0
3393 23:07:14.394376 1, 0xFFFF, sum = 0
3394 23:07:14.394459 2, 0xFFFF, sum = 0
3395 23:07:14.397815 3, 0xFFFF, sum = 0
3396 23:07:14.397897 4, 0xFFFF, sum = 0
3397 23:07:14.401104 5, 0xFFFF, sum = 0
3398 23:07:14.401186 6, 0xFFFF, sum = 0
3399 23:07:14.404094 7, 0xFFFF, sum = 0
3400 23:07:14.404176 8, 0xFFFF, sum = 0
3401 23:07:14.407518 9, 0xFFFF, sum = 0
3402 23:07:14.410846 10, 0xFFFF, sum = 0
3403 23:07:14.410927 11, 0x0, sum = 1
3404 23:07:14.410992 12, 0x0, sum = 2
3405 23:07:14.414218 13, 0x0, sum = 3
3406 23:07:14.414299 14, 0x0, sum = 4
3407 23:07:14.417675 best_step = 12
3408 23:07:14.417780
3409 23:07:14.417845 ==
3410 23:07:14.420781 Dram Type= 6, Freq= 0, CH_1, rank 1
3411 23:07:14.424477 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3412 23:07:14.424559 ==
3413 23:07:14.427456 RX Vref Scan: 0
3414 23:07:14.427536
3415 23:07:14.427599 RX Vref 0 -> 0, step: 1
3416 23:07:14.427658
3417 23:07:14.430641 RX Delay -29 -> 252, step: 4
3418 23:07:14.437922 iDelay=199, Bit 0, Center 116 (47 ~ 186) 140
3419 23:07:14.441152 iDelay=199, Bit 1, Center 108 (39 ~ 178) 140
3420 23:07:14.444392 iDelay=199, Bit 2, Center 108 (39 ~ 178) 140
3421 23:07:14.447783 iDelay=199, Bit 3, Center 112 (43 ~ 182) 140
3422 23:07:14.450921 iDelay=199, Bit 4, Center 114 (43 ~ 186) 144
3423 23:07:14.457570 iDelay=199, Bit 5, Center 124 (51 ~ 198) 148
3424 23:07:14.460943 iDelay=199, Bit 6, Center 122 (51 ~ 194) 144
3425 23:07:14.464136 iDelay=199, Bit 7, Center 114 (43 ~ 186) 144
3426 23:07:14.467541 iDelay=199, Bit 8, Center 88 (19 ~ 158) 140
3427 23:07:14.471076 iDelay=199, Bit 9, Center 92 (27 ~ 158) 132
3428 23:07:14.477498 iDelay=199, Bit 10, Center 106 (39 ~ 174) 136
3429 23:07:14.480949 iDelay=199, Bit 11, Center 98 (31 ~ 166) 136
3430 23:07:14.484245 iDelay=199, Bit 12, Center 112 (43 ~ 182) 140
3431 23:07:14.487721 iDelay=199, Bit 13, Center 110 (43 ~ 178) 136
3432 23:07:14.490936 iDelay=199, Bit 14, Center 114 (43 ~ 186) 144
3433 23:07:14.497611 iDelay=199, Bit 15, Center 110 (43 ~ 178) 136
3434 23:07:14.497691 ==
3435 23:07:14.500979 Dram Type= 6, Freq= 0, CH_1, rank 1
3436 23:07:14.504764 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3437 23:07:14.504845 ==
3438 23:07:14.504909 DQS Delay:
3439 23:07:14.507656 DQS0 = 0, DQS1 = 0
3440 23:07:14.507736 DQM Delay:
3441 23:07:14.511026 DQM0 = 114, DQM1 = 103
3442 23:07:14.511105 DQ Delay:
3443 23:07:14.514133 DQ0 =116, DQ1 =108, DQ2 =108, DQ3 =112
3444 23:07:14.517734 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =114
3445 23:07:14.520912 DQ8 =88, DQ9 =92, DQ10 =106, DQ11 =98
3446 23:07:14.524082 DQ12 =112, DQ13 =110, DQ14 =114, DQ15 =110
3447 23:07:14.524163
3448 23:07:14.524225
3449 23:07:14.533944 [DQSOSCAuto] RK1, (LSB)MR18= 0x606, (MSB)MR19= 0x404, tDQSOscB0 = 407 ps tDQSOscB1 = 407 ps
3450 23:07:14.537266 CH1 RK1: MR19=404, MR18=606
3451 23:07:14.541142 CH1_RK1: MR19=0x404, MR18=0x606, DQSOSC=407, MR23=63, INC=39, DEC=26
3452 23:07:14.543944 [RxdqsGatingPostProcess] freq 1200
3453 23:07:14.551074 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
3454 23:07:14.554240 Pre-setting of DQS Precalculation
3455 23:07:14.557299 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
3456 23:07:14.567401 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3457 23:07:14.574198 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3458 23:07:14.574279
3459 23:07:14.574342
3460 23:07:14.577350 [Calibration Summary] 2400 Mbps
3461 23:07:14.577450 CH 0, Rank 0
3462 23:07:14.580517 SW Impedance : PASS
3463 23:07:14.580597 DUTY Scan : NO K
3464 23:07:14.583871 ZQ Calibration : PASS
3465 23:07:14.587618 Jitter Meter : NO K
3466 23:07:14.587736 CBT Training : PASS
3467 23:07:14.590387 Write leveling : PASS
3468 23:07:14.594057 RX DQS gating : PASS
3469 23:07:14.594138 RX DQ/DQS(RDDQC) : PASS
3470 23:07:14.597257 TX DQ/DQS : PASS
3471 23:07:14.600685 RX DATLAT : PASS
3472 23:07:14.600807 RX DQ/DQS(Engine): PASS
3473 23:07:14.603875 TX OE : NO K
3474 23:07:14.603955 All Pass.
3475 23:07:14.604019
3476 23:07:14.607287 CH 0, Rank 1
3477 23:07:14.607367 SW Impedance : PASS
3478 23:07:14.610589 DUTY Scan : NO K
3479 23:07:14.610669 ZQ Calibration : PASS
3480 23:07:14.614117 Jitter Meter : NO K
3481 23:07:14.617135 CBT Training : PASS
3482 23:07:14.617216 Write leveling : PASS
3483 23:07:14.620462 RX DQS gating : PASS
3484 23:07:14.626270 RX DQ/DQS(RDDQC) : PASS
3485 23:07:14.626353 TX DQ/DQS : PASS
3486 23:07:14.627410 RX DATLAT : PASS
3487 23:07:14.630670 RX DQ/DQS(Engine): PASS
3488 23:07:14.630751 TX OE : NO K
3489 23:07:14.633953 All Pass.
3490 23:07:14.634037
3491 23:07:14.634101 CH 1, Rank 0
3492 23:07:14.637292 SW Impedance : PASS
3493 23:07:14.637372 DUTY Scan : NO K
3494 23:07:14.640623 ZQ Calibration : PASS
3495 23:07:14.643894 Jitter Meter : NO K
3496 23:07:14.643975 CBT Training : PASS
3497 23:07:14.647748 Write leveling : PASS
3498 23:07:14.650727 RX DQS gating : PASS
3499 23:07:14.650807 RX DQ/DQS(RDDQC) : PASS
3500 23:07:14.653793 TX DQ/DQS : PASS
3501 23:07:14.653873 RX DATLAT : PASS
3502 23:07:14.657543 RX DQ/DQS(Engine): PASS
3503 23:07:14.660468 TX OE : NO K
3504 23:07:14.660548 All Pass.
3505 23:07:14.660612
3506 23:07:14.660671 CH 1, Rank 1
3507 23:07:14.663801 SW Impedance : PASS
3508 23:07:14.667729 DUTY Scan : NO K
3509 23:07:14.667809 ZQ Calibration : PASS
3510 23:07:14.670721 Jitter Meter : NO K
3511 23:07:14.673840 CBT Training : PASS
3512 23:07:14.673921 Write leveling : PASS
3513 23:07:14.677703 RX DQS gating : PASS
3514 23:07:14.680867 RX DQ/DQS(RDDQC) : PASS
3515 23:07:14.680947 TX DQ/DQS : PASS
3516 23:07:14.684049 RX DATLAT : PASS
3517 23:07:14.687306 RX DQ/DQS(Engine): PASS
3518 23:07:14.687389 TX OE : NO K
3519 23:07:14.690618 All Pass.
3520 23:07:14.690698
3521 23:07:14.690761 DramC Write-DBI off
3522 23:07:14.693838 PER_BANK_REFRESH: Hybrid Mode
3523 23:07:14.693919 TX_TRACKING: ON
3524 23:07:14.703989 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3525 23:07:14.707387 [FAST_K] Save calibration result to emmc
3526 23:07:14.710609 dramc_set_vcore_voltage set vcore to 650000
3527 23:07:14.713980 Read voltage for 600, 5
3528 23:07:14.714060 Vio18 = 0
3529 23:07:14.717153 Vcore = 650000
3530 23:07:14.717265 Vdram = 0
3531 23:07:14.717333 Vddq = 0
3532 23:07:14.717394 Vmddr = 0
3533 23:07:14.723811 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3534 23:07:14.730480 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3535 23:07:14.730562 MEM_TYPE=3, freq_sel=19
3536 23:07:14.734037 sv_algorithm_assistance_LP4_1600
3537 23:07:14.737447 ============ PULL DRAM RESETB DOWN ============
3538 23:07:14.743937 ========== PULL DRAM RESETB DOWN end =========
3539 23:07:14.747229 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3540 23:07:14.750928 ===================================
3541 23:07:14.754022 LPDDR4 DRAM CONFIGURATION
3542 23:07:14.757536 ===================================
3543 23:07:14.757618 EX_ROW_EN[0] = 0x0
3544 23:07:14.760750 EX_ROW_EN[1] = 0x0
3545 23:07:14.760831 LP4Y_EN = 0x0
3546 23:07:14.764184 WORK_FSP = 0x0
3547 23:07:14.764264 WL = 0x2
3548 23:07:14.767522 RL = 0x2
3549 23:07:14.767603 BL = 0x2
3550 23:07:14.770820 RPST = 0x0
3551 23:07:14.770901 RD_PRE = 0x0
3552 23:07:14.774421 WR_PRE = 0x1
3553 23:07:14.774502 WR_PST = 0x0
3554 23:07:14.777466 DBI_WR = 0x0
3555 23:07:14.777552 DBI_RD = 0x0
3556 23:07:14.780731 OTF = 0x1
3557 23:07:14.784185 ===================================
3558 23:07:14.787618 ===================================
3559 23:07:14.787700 ANA top config
3560 23:07:14.790991 ===================================
3561 23:07:14.794051 DLL_ASYNC_EN = 0
3562 23:07:14.797164 ALL_SLAVE_EN = 1
3563 23:07:14.800461 NEW_RANK_MODE = 1
3564 23:07:14.803798 DLL_IDLE_MODE = 1
3565 23:07:14.803977 LP45_APHY_COMB_EN = 1
3566 23:07:14.807194 TX_ODT_DIS = 1
3567 23:07:14.810426 NEW_8X_MODE = 1
3568 23:07:14.813626 ===================================
3569 23:07:14.817027 ===================================
3570 23:07:14.820250 data_rate = 1200
3571 23:07:14.823757 CKR = 1
3572 23:07:14.823838 DQ_P2S_RATIO = 8
3573 23:07:14.826865 ===================================
3574 23:07:14.830272 CA_P2S_RATIO = 8
3575 23:07:14.833636 DQ_CA_OPEN = 0
3576 23:07:14.836990 DQ_SEMI_OPEN = 0
3577 23:07:14.840179 CA_SEMI_OPEN = 0
3578 23:07:14.843767 CA_FULL_RATE = 0
3579 23:07:14.843847 DQ_CKDIV4_EN = 1
3580 23:07:14.847104 CA_CKDIV4_EN = 1
3581 23:07:14.849982 CA_PREDIV_EN = 0
3582 23:07:14.853392 PH8_DLY = 0
3583 23:07:14.856754 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3584 23:07:14.859914 DQ_AAMCK_DIV = 4
3585 23:07:14.859994 CA_AAMCK_DIV = 4
3586 23:07:14.863181 CA_ADMCK_DIV = 4
3587 23:07:14.866740 DQ_TRACK_CA_EN = 0
3588 23:07:14.870003 CA_PICK = 600
3589 23:07:14.873105 CA_MCKIO = 600
3590 23:07:14.876414 MCKIO_SEMI = 0
3591 23:07:14.879663 PLL_FREQ = 2288
3592 23:07:14.883255 DQ_UI_PI_RATIO = 32
3593 23:07:14.883346 CA_UI_PI_RATIO = 0
3594 23:07:14.886789 ===================================
3595 23:07:14.889732 ===================================
3596 23:07:14.892937 memory_type:LPDDR4
3597 23:07:14.896334 GP_NUM : 10
3598 23:07:14.896414 SRAM_EN : 1
3599 23:07:14.899552 MD32_EN : 0
3600 23:07:14.903033 ===================================
3601 23:07:14.906149 [ANA_INIT] >>>>>>>>>>>>>>
3602 23:07:14.909573 <<<<<< [CONFIGURE PHASE]: ANA_TX
3603 23:07:14.912758 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3604 23:07:14.916307 ===================================
3605 23:07:14.916388 data_rate = 1200,PCW = 0X5800
3606 23:07:14.919764 ===================================
3607 23:07:14.922934 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3608 23:07:14.929692 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3609 23:07:14.936360 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3610 23:07:14.939547 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3611 23:07:14.942681 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3612 23:07:14.945939 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3613 23:07:14.949460 [ANA_INIT] flow start
3614 23:07:14.949541 [ANA_INIT] PLL >>>>>>>>
3615 23:07:14.952540 [ANA_INIT] PLL <<<<<<<<
3616 23:07:14.955886 [ANA_INIT] MIDPI >>>>>>>>
3617 23:07:14.959285 [ANA_INIT] MIDPI <<<<<<<<
3618 23:07:14.959366 [ANA_INIT] DLL >>>>>>>>
3619 23:07:14.962558 [ANA_INIT] flow end
3620 23:07:14.965788 ============ LP4 DIFF to SE enter ============
3621 23:07:14.969402 ============ LP4 DIFF to SE exit ============
3622 23:07:14.972290 [ANA_INIT] <<<<<<<<<<<<<
3623 23:07:14.975483 [Flow] Enable top DCM control >>>>>
3624 23:07:14.978991 [Flow] Enable top DCM control <<<<<
3625 23:07:14.982281 Enable DLL master slave shuffle
3626 23:07:14.989211 ==============================================================
3627 23:07:14.989292 Gating Mode config
3628 23:07:14.995610 ==============================================================
3629 23:07:14.995691 Config description:
3630 23:07:15.005638 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3631 23:07:15.012386 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3632 23:07:15.018661 SELPH_MODE 0: By rank 1: By Phase
3633 23:07:15.022004 ==============================================================
3634 23:07:15.025660 GAT_TRACK_EN = 1
3635 23:07:15.029108 RX_GATING_MODE = 2
3636 23:07:15.032107 RX_GATING_TRACK_MODE = 2
3637 23:07:15.035230 SELPH_MODE = 1
3638 23:07:15.038895 PICG_EARLY_EN = 1
3639 23:07:15.042168 VALID_LAT_VALUE = 1
3640 23:07:15.048673 ==============================================================
3641 23:07:15.051805 Enter into Gating configuration >>>>
3642 23:07:15.055192 Exit from Gating configuration <<<<
3643 23:07:15.058447 Enter into DVFS_PRE_config >>>>>
3644 23:07:15.068608 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3645 23:07:15.071733 Exit from DVFS_PRE_config <<<<<
3646 23:07:15.075112 Enter into PICG configuration >>>>
3647 23:07:15.078657 Exit from PICG configuration <<<<
3648 23:07:15.081683 [RX_INPUT] configuration >>>>>
3649 23:07:15.081771 [RX_INPUT] configuration <<<<<
3650 23:07:15.088288 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3651 23:07:15.094978 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3652 23:07:15.098314 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3653 23:07:15.104780 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3654 23:07:15.111253 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3655 23:07:15.117996 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3656 23:07:15.121440 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3657 23:07:15.124568 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3658 23:07:15.131477 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3659 23:07:15.134553 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3660 23:07:15.138004 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3661 23:07:15.144550 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3662 23:07:15.147826 ===================================
3663 23:07:15.147906 LPDDR4 DRAM CONFIGURATION
3664 23:07:15.151207 ===================================
3665 23:07:15.154662 EX_ROW_EN[0] = 0x0
3666 23:07:15.154742 EX_ROW_EN[1] = 0x0
3667 23:07:15.158083 LP4Y_EN = 0x0
3668 23:07:15.158163 WORK_FSP = 0x0
3669 23:07:15.161345 WL = 0x2
3670 23:07:15.164346 RL = 0x2
3671 23:07:15.164426 BL = 0x2
3672 23:07:15.167941 RPST = 0x0
3673 23:07:15.168021 RD_PRE = 0x0
3674 23:07:15.171339 WR_PRE = 0x1
3675 23:07:15.171419 WR_PST = 0x0
3676 23:07:15.174597 DBI_WR = 0x0
3677 23:07:15.174676 DBI_RD = 0x0
3678 23:07:15.177659 OTF = 0x1
3679 23:07:15.181242 ===================================
3680 23:07:15.184759 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3681 23:07:15.187889 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3682 23:07:15.191135 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3683 23:07:15.194488 ===================================
3684 23:07:15.197676 LPDDR4 DRAM CONFIGURATION
3685 23:07:15.200912 ===================================
3686 23:07:15.204353 EX_ROW_EN[0] = 0x10
3687 23:07:15.204434 EX_ROW_EN[1] = 0x0
3688 23:07:15.207621 LP4Y_EN = 0x0
3689 23:07:15.207702 WORK_FSP = 0x0
3690 23:07:15.210792 WL = 0x2
3691 23:07:15.210873 RL = 0x2
3692 23:07:15.214279 BL = 0x2
3693 23:07:15.217442 RPST = 0x0
3694 23:07:15.217523 RD_PRE = 0x0
3695 23:07:15.221164 WR_PRE = 0x1
3696 23:07:15.221245 WR_PST = 0x0
3697 23:07:15.224268 DBI_WR = 0x0
3698 23:07:15.224349 DBI_RD = 0x0
3699 23:07:15.227298 OTF = 0x1
3700 23:07:15.230654 ===================================
3701 23:07:15.234418 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3702 23:07:15.239372 nWR fixed to 30
3703 23:07:15.242709 [ModeRegInit_LP4] CH0 RK0
3704 23:07:15.242790 [ModeRegInit_LP4] CH0 RK1
3705 23:07:15.246265 [ModeRegInit_LP4] CH1 RK0
3706 23:07:15.249517 [ModeRegInit_LP4] CH1 RK1
3707 23:07:15.249597 match AC timing 16
3708 23:07:15.256293 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 0
3709 23:07:15.259303 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3710 23:07:15.263121 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3711 23:07:15.269365 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3712 23:07:15.272868 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3713 23:07:15.272949 ==
3714 23:07:15.275932 Dram Type= 6, Freq= 0, CH_0, rank 0
3715 23:07:15.279520 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3716 23:07:15.279607 ==
3717 23:07:15.285906 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3718 23:07:15.292848 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3719 23:07:15.295756 [CA 0] Center 35 (5~66) winsize 62
3720 23:07:15.299373 [CA 1] Center 35 (5~66) winsize 62
3721 23:07:15.302321 [CA 2] Center 34 (4~65) winsize 62
3722 23:07:15.305639 [CA 3] Center 34 (3~65) winsize 63
3723 23:07:15.308990 [CA 4] Center 33 (3~64) winsize 62
3724 23:07:15.312606 [CA 5] Center 33 (3~64) winsize 62
3725 23:07:15.312720
3726 23:07:15.315930 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3727 23:07:15.316014
3728 23:07:15.318999 [CATrainingPosCal] consider 1 rank data
3729 23:07:15.322353 u2DelayCellTimex100 = 270/100 ps
3730 23:07:15.325594 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
3731 23:07:15.329121 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3732 23:07:15.332458 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3733 23:07:15.335684 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3734 23:07:15.339090 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3735 23:07:15.345634 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3736 23:07:15.345715
3737 23:07:15.349043 CA PerBit enable=1, Macro0, CA PI delay=33
3738 23:07:15.349124
3739 23:07:15.352539 [CBTSetCACLKResult] CA Dly = 33
3740 23:07:15.352620 CS Dly: 5 (0~36)
3741 23:07:15.352685 ==
3742 23:07:15.355657 Dram Type= 6, Freq= 0, CH_0, rank 1
3743 23:07:15.358670 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3744 23:07:15.362364 ==
3745 23:07:15.365408 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3746 23:07:15.372264 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
3747 23:07:15.375382 [CA 0] Center 35 (5~66) winsize 62
3748 23:07:15.378728 [CA 1] Center 35 (5~66) winsize 62
3749 23:07:15.381923 [CA 2] Center 34 (4~65) winsize 62
3750 23:07:15.385601 [CA 3] Center 34 (3~65) winsize 63
3751 23:07:15.388683 [CA 4] Center 33 (3~64) winsize 62
3752 23:07:15.391696 [CA 5] Center 33 (3~64) winsize 62
3753 23:07:15.391777
3754 23:07:15.395181 [CmdBusTrainingLP45] Vref(ca) range 1: 39
3755 23:07:15.395263
3756 23:07:15.398523 [CATrainingPosCal] consider 2 rank data
3757 23:07:15.401622 u2DelayCellTimex100 = 270/100 ps
3758 23:07:15.405115 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
3759 23:07:15.408628 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3760 23:07:15.411793 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3761 23:07:15.418530 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3762 23:07:15.421849 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3763 23:07:15.424866 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3764 23:07:15.424947
3765 23:07:15.428146 CA PerBit enable=1, Macro0, CA PI delay=33
3766 23:07:15.428227
3767 23:07:15.431855 [CBTSetCACLKResult] CA Dly = 33
3768 23:07:15.431937 CS Dly: 5 (0~37)
3769 23:07:15.432001
3770 23:07:15.434961 ----->DramcWriteLeveling(PI) begin...
3771 23:07:15.438177 ==
3772 23:07:15.438258 Dram Type= 6, Freq= 0, CH_0, rank 0
3773 23:07:15.444670 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3774 23:07:15.444800 ==
3775 23:07:15.448200 Write leveling (Byte 0): 31 => 31
3776 23:07:15.451628 Write leveling (Byte 1): 30 => 30
3777 23:07:15.454840 DramcWriteLeveling(PI) end<-----
3778 23:07:15.454922
3779 23:07:15.454986 ==
3780 23:07:15.458271 Dram Type= 6, Freq= 0, CH_0, rank 0
3781 23:07:15.461182 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3782 23:07:15.461282 ==
3783 23:07:15.464677 [Gating] SW mode calibration
3784 23:07:15.471214 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3785 23:07:15.474778 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
3786 23:07:15.481246 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3787 23:07:15.484625 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3788 23:07:15.487904 0 5 8 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (0 0)
3789 23:07:15.494470 0 5 12 | B1->B0 | 2727 2323 | 0 0 | (1 0) (0 0)
3790 23:07:15.497781 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3791 23:07:15.501191 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3792 23:07:15.507633 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3793 23:07:15.510764 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3794 23:07:15.514117 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3795 23:07:15.520952 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3796 23:07:15.524480 0 6 8 | B1->B0 | 3030 3232 | 0 0 | (0 0) (1 1)
3797 23:07:15.527567 0 6 12 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
3798 23:07:15.534123 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3799 23:07:15.537860 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3800 23:07:15.540590 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3801 23:07:15.547157 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3802 23:07:15.550580 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3803 23:07:15.554060 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3804 23:07:15.560574 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3805 23:07:15.563519 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3806 23:07:15.566989 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3807 23:07:15.573843 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3808 23:07:15.577009 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3809 23:07:15.580349 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3810 23:07:15.586988 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3811 23:07:15.590000 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3812 23:07:15.593613 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3813 23:07:15.599829 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3814 23:07:15.603287 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3815 23:07:15.606563 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3816 23:07:15.613207 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3817 23:07:15.616747 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3818 23:07:15.619724 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3819 23:07:15.626284 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3820 23:07:15.629635 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3821 23:07:15.632768 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3822 23:07:15.639511 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3823 23:07:15.643169 Total UI for P1: 0, mck2ui 16
3824 23:07:15.646382 best dqsien dly found for B0: ( 0, 9, 12)
3825 23:07:15.649718 Total UI for P1: 0, mck2ui 16
3826 23:07:15.652864 best dqsien dly found for B1: ( 0, 9, 12)
3827 23:07:15.656174 best DQS0 dly(MCK, UI, PI) = (0, 9, 12)
3828 23:07:15.659568 best DQS1 dly(MCK, UI, PI) = (0, 9, 12)
3829 23:07:15.659648
3830 23:07:15.662512 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 12)
3831 23:07:15.666216 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 12)
3832 23:07:15.669488 [Gating] SW calibration Done
3833 23:07:15.669568 ==
3834 23:07:15.672700 Dram Type= 6, Freq= 0, CH_0, rank 0
3835 23:07:15.675859 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3836 23:07:15.675940 ==
3837 23:07:15.679427 RX Vref Scan: 0
3838 23:07:15.679508
3839 23:07:15.679572 RX Vref 0 -> 0, step: 1
3840 23:07:15.682567
3841 23:07:15.682647 RX Delay -230 -> 252, step: 16
3842 23:07:15.689465 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
3843 23:07:15.692602 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
3844 23:07:15.695916 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
3845 23:07:15.699238 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
3846 23:07:15.705921 iDelay=218, Bit 4, Center 41 (-134 ~ 217) 352
3847 23:07:15.709109 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
3848 23:07:15.712470 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
3849 23:07:15.716232 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
3850 23:07:15.719185 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
3851 23:07:15.725971 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
3852 23:07:15.729158 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
3853 23:07:15.732216 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
3854 23:07:15.735719 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
3855 23:07:15.742551 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
3856 23:07:15.745670 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
3857 23:07:15.748673 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
3858 23:07:15.748763 ==
3859 23:07:15.752024 Dram Type= 6, Freq= 0, CH_0, rank 0
3860 23:07:15.758640 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3861 23:07:15.758721 ==
3862 23:07:15.758785 DQS Delay:
3863 23:07:15.758844 DQS0 = 0, DQS1 = 0
3864 23:07:15.762578 DQM Delay:
3865 23:07:15.762658 DQM0 = 38, DQM1 = 33
3866 23:07:15.765133 DQ Delay:
3867 23:07:15.768523 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
3868 23:07:15.772135 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
3869 23:07:15.775364 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
3870 23:07:15.778444 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
3871 23:07:15.778525
3872 23:07:15.778634
3873 23:07:15.778694 ==
3874 23:07:15.782074 Dram Type= 6, Freq= 0, CH_0, rank 0
3875 23:07:15.785301 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3876 23:07:15.785383 ==
3877 23:07:15.785447
3878 23:07:15.785506
3879 23:07:15.788652 TX Vref Scan disable
3880 23:07:15.788771 == TX Byte 0 ==
3881 23:07:15.795344 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
3882 23:07:15.798505 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
3883 23:07:15.798586 == TX Byte 1 ==
3884 23:07:15.805263 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
3885 23:07:15.808525 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
3886 23:07:15.808606 ==
3887 23:07:15.811699 Dram Type= 6, Freq= 0, CH_0, rank 0
3888 23:07:15.815069 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3889 23:07:15.815150 ==
3890 23:07:15.815213
3891 23:07:15.818246
3892 23:07:15.818325 TX Vref Scan disable
3893 23:07:15.821774 == TX Byte 0 ==
3894 23:07:15.825086 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
3895 23:07:15.831620 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
3896 23:07:15.831700 == TX Byte 1 ==
3897 23:07:15.835224 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
3898 23:07:15.841458 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
3899 23:07:15.841539
3900 23:07:15.841602 [DATLAT]
3901 23:07:15.841662 Freq=600, CH0 RK0
3902 23:07:15.841720
3903 23:07:15.844994 DATLAT Default: 0x9
3904 23:07:15.845074 0, 0xFFFF, sum = 0
3905 23:07:15.848625 1, 0xFFFF, sum = 0
3906 23:07:15.851694 2, 0xFFFF, sum = 0
3907 23:07:15.851775 3, 0xFFFF, sum = 0
3908 23:07:15.854480 4, 0xFFFF, sum = 0
3909 23:07:15.854561 5, 0xFFFF, sum = 0
3910 23:07:15.858013 6, 0xFFFF, sum = 0
3911 23:07:15.858094 7, 0x0, sum = 1
3912 23:07:15.861137 8, 0x0, sum = 2
3913 23:07:15.861218 9, 0x0, sum = 3
3914 23:07:15.861282 10, 0x0, sum = 4
3915 23:07:15.864404 best_step = 8
3916 23:07:15.864484
3917 23:07:15.864547 ==
3918 23:07:15.867630 Dram Type= 6, Freq= 0, CH_0, rank 0
3919 23:07:15.871037 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3920 23:07:15.871150 ==
3921 23:07:15.874599 RX Vref Scan: 1
3922 23:07:15.874679
3923 23:07:15.874742 RX Vref 0 -> 0, step: 1
3924 23:07:15.877746
3925 23:07:15.877826 RX Delay -195 -> 252, step: 8
3926 23:07:15.877890
3927 23:07:15.881208 Set Vref, RX VrefLevel [Byte0]: 47
3928 23:07:15.884388 [Byte1]: 42
3929 23:07:15.888745
3930 23:07:15.888825 Final RX Vref Byte 0 = 47 to rank0
3931 23:07:15.892158 Final RX Vref Byte 1 = 42 to rank0
3932 23:07:15.895498 Final RX Vref Byte 0 = 47 to rank1
3933 23:07:15.898504 Final RX Vref Byte 1 = 42 to rank1==
3934 23:07:15.902015 Dram Type= 6, Freq= 0, CH_0, rank 0
3935 23:07:15.908700 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3936 23:07:15.908844 ==
3937 23:07:15.908937 DQS Delay:
3938 23:07:15.909021 DQS0 = 0, DQS1 = 0
3939 23:07:15.912068 DQM Delay:
3940 23:07:15.912149 DQM0 = 41, DQM1 = 31
3941 23:07:15.915698 DQ Delay:
3942 23:07:15.918747 DQ0 =40, DQ1 =40, DQ2 =36, DQ3 =36
3943 23:07:15.921758 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =52
3944 23:07:15.925150 DQ8 =20, DQ9 =16, DQ10 =28, DQ11 =24
3945 23:07:15.928693 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =44
3946 23:07:15.928781
3947 23:07:15.928845
3948 23:07:15.935280 [DQSOSCAuto] RK0, (LSB)MR18= 0x5252, (MSB)MR19= 0x808, tDQSOscB0 = 394 ps tDQSOscB1 = 394 ps
3949 23:07:15.938698 CH0 RK0: MR19=808, MR18=5252
3950 23:07:15.945277 CH0_RK0: MR19=0x808, MR18=0x5252, DQSOSC=394, MR23=63, INC=168, DEC=112
3951 23:07:15.945359
3952 23:07:15.948513 ----->DramcWriteLeveling(PI) begin...
3953 23:07:15.948594 ==
3954 23:07:15.951996 Dram Type= 6, Freq= 0, CH_0, rank 1
3955 23:07:15.955280 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3956 23:07:15.955361 ==
3957 23:07:15.958570 Write leveling (Byte 0): 29 => 29
3958 23:07:15.961704 Write leveling (Byte 1): 31 => 31
3959 23:07:15.964904 DramcWriteLeveling(PI) end<-----
3960 23:07:15.964985
3961 23:07:15.965048 ==
3962 23:07:15.968293 Dram Type= 6, Freq= 0, CH_0, rank 1
3963 23:07:15.971679 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3964 23:07:15.971760 ==
3965 23:07:15.975153 [Gating] SW mode calibration
3966 23:07:15.981709 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3967 23:07:15.988433 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
3968 23:07:15.991492 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3969 23:07:15.997960 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3970 23:07:16.001297 0 5 8 | B1->B0 | 3232 3131 | 1 1 | (1 0) (1 0)
3971 23:07:16.004619 0 5 12 | B1->B0 | 2828 2525 | 0 0 | (1 1) (0 0)
3972 23:07:16.011519 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3973 23:07:16.014759 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3974 23:07:16.017826 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3975 23:07:16.024552 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3976 23:07:16.027949 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3977 23:07:16.031138 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3978 23:07:16.037803 0 6 8 | B1->B0 | 2e2e 3333 | 0 0 | (0 0) (0 0)
3979 23:07:16.041339 0 6 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
3980 23:07:16.044633 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3981 23:07:16.047748 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3982 23:07:16.054282 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3983 23:07:16.057504 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3984 23:07:16.061113 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3985 23:07:16.067687 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3986 23:07:16.071025 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3987 23:07:16.074563 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3988 23:07:16.080624 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3989 23:07:16.083976 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3990 23:07:16.087467 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3991 23:07:16.094170 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3992 23:07:16.097525 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3993 23:07:16.100860 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3994 23:07:16.107172 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3995 23:07:16.110770 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3996 23:07:16.113910 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3997 23:07:16.120930 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3998 23:07:16.124118 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3999 23:07:16.127053 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4000 23:07:16.133841 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4001 23:07:16.137094 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4002 23:07:16.140210 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4003 23:07:16.147278 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4004 23:07:16.150230 Total UI for P1: 0, mck2ui 16
4005 23:07:16.153495 best dqsien dly found for B0: ( 0, 9, 8)
4006 23:07:16.156831 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4007 23:07:16.160373 Total UI for P1: 0, mck2ui 16
4008 23:07:16.163521 best dqsien dly found for B1: ( 0, 9, 10)
4009 23:07:16.167106 best DQS0 dly(MCK, UI, PI) = (0, 9, 8)
4010 23:07:16.170383 best DQS1 dly(MCK, UI, PI) = (0, 9, 10)
4011 23:07:16.170463
4012 23:07:16.173770 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 8)
4013 23:07:16.176991 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 10)
4014 23:07:16.180102 [Gating] SW calibration Done
4015 23:07:16.180182 ==
4016 23:07:16.183617 Dram Type= 6, Freq= 0, CH_0, rank 1
4017 23:07:16.190065 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4018 23:07:16.190147 ==
4019 23:07:16.190211 RX Vref Scan: 0
4020 23:07:16.190270
4021 23:07:16.193395 RX Vref 0 -> 0, step: 1
4022 23:07:16.193475
4023 23:07:16.196646 RX Delay -230 -> 252, step: 16
4024 23:07:16.200000 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4025 23:07:16.203312 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4026 23:07:16.206465 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4027 23:07:16.213058 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4028 23:07:16.216441 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
4029 23:07:16.220068 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4030 23:07:16.222884 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4031 23:07:16.229814 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4032 23:07:16.233184 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4033 23:07:16.236399 iDelay=218, Bit 9, Center 9 (-150 ~ 169) 320
4034 23:07:16.239774 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4035 23:07:16.242975 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4036 23:07:16.249606 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4037 23:07:16.252677 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4038 23:07:16.256164 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4039 23:07:16.259333 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4040 23:07:16.262708 ==
4041 23:07:16.262788 Dram Type= 6, Freq= 0, CH_0, rank 1
4042 23:07:16.269438 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4043 23:07:16.269522 ==
4044 23:07:16.269586 DQS Delay:
4045 23:07:16.272625 DQS0 = 0, DQS1 = 0
4046 23:07:16.272728 DQM Delay:
4047 23:07:16.276106 DQM0 = 42, DQM1 = 32
4048 23:07:16.276187 DQ Delay:
4049 23:07:16.279636 DQ0 =33, DQ1 =49, DQ2 =33, DQ3 =41
4050 23:07:16.282582 DQ4 =49, DQ5 =33, DQ6 =49, DQ7 =49
4051 23:07:16.286084 DQ8 =25, DQ9 =9, DQ10 =33, DQ11 =25
4052 23:07:16.289517 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4053 23:07:16.289608
4054 23:07:16.289673
4055 23:07:16.289732 ==
4056 23:07:16.292515 Dram Type= 6, Freq= 0, CH_0, rank 1
4057 23:07:16.295937 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4058 23:07:16.296018 ==
4059 23:07:16.296082
4060 23:07:16.296141
4061 23:07:16.299303 TX Vref Scan disable
4062 23:07:16.302771 == TX Byte 0 ==
4063 23:07:16.305766 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4064 23:07:16.309405 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4065 23:07:16.312509 == TX Byte 1 ==
4066 23:07:16.315784 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4067 23:07:16.319121 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4068 23:07:16.319201 ==
4069 23:07:16.322208 Dram Type= 6, Freq= 0, CH_0, rank 1
4070 23:07:16.325769 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4071 23:07:16.329457 ==
4072 23:07:16.329538
4073 23:07:16.329601
4074 23:07:16.329659 TX Vref Scan disable
4075 23:07:16.333150 == TX Byte 0 ==
4076 23:07:16.336666 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4077 23:07:16.343245 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4078 23:07:16.343325 == TX Byte 1 ==
4079 23:07:16.346236 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4080 23:07:16.353392 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4081 23:07:16.353473
4082 23:07:16.353537 [DATLAT]
4083 23:07:16.353596 Freq=600, CH0 RK1
4084 23:07:16.353653
4085 23:07:16.356352 DATLAT Default: 0x8
4086 23:07:16.356433 0, 0xFFFF, sum = 0
4087 23:07:16.359637 1, 0xFFFF, sum = 0
4088 23:07:16.362616 2, 0xFFFF, sum = 0
4089 23:07:16.362697 3, 0xFFFF, sum = 0
4090 23:07:16.366048 4, 0xFFFF, sum = 0
4091 23:07:16.366130 5, 0xFFFF, sum = 0
4092 23:07:16.369289 6, 0xFFFF, sum = 0
4093 23:07:16.369370 7, 0x0, sum = 1
4094 23:07:16.372657 8, 0x0, sum = 2
4095 23:07:16.372778 9, 0x0, sum = 3
4096 23:07:16.372843 10, 0x0, sum = 4
4097 23:07:16.376040 best_step = 8
4098 23:07:16.376120
4099 23:07:16.376183 ==
4100 23:07:16.379214 Dram Type= 6, Freq= 0, CH_0, rank 1
4101 23:07:16.382486 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4102 23:07:16.382568 ==
4103 23:07:16.385955 RX Vref Scan: 0
4104 23:07:16.386045
4105 23:07:16.386110 RX Vref 0 -> 0, step: 1
4106 23:07:16.386170
4107 23:07:16.389156 RX Delay -195 -> 252, step: 8
4108 23:07:16.396720 iDelay=205, Bit 0, Center 36 (-115 ~ 188) 304
4109 23:07:16.400121 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4110 23:07:16.403221 iDelay=205, Bit 2, Center 40 (-115 ~ 196) 312
4111 23:07:16.406500 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4112 23:07:16.413173 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4113 23:07:16.416600 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4114 23:07:16.419900 iDelay=205, Bit 6, Center 44 (-107 ~ 196) 304
4115 23:07:16.423076 iDelay=205, Bit 7, Center 52 (-99 ~ 204) 304
4116 23:07:16.426826 iDelay=205, Bit 8, Center 20 (-123 ~ 164) 288
4117 23:07:16.432973 iDelay=205, Bit 9, Center 16 (-131 ~ 164) 296
4118 23:07:16.436350 iDelay=205, Bit 10, Center 36 (-115 ~ 188) 304
4119 23:07:16.439847 iDelay=205, Bit 11, Center 24 (-123 ~ 172) 296
4120 23:07:16.442998 iDelay=205, Bit 12, Center 40 (-107 ~ 188) 296
4121 23:07:16.449564 iDelay=205, Bit 13, Center 36 (-115 ~ 188) 304
4122 23:07:16.453156 iDelay=205, Bit 14, Center 40 (-107 ~ 188) 296
4123 23:07:16.456189 iDelay=205, Bit 15, Center 40 (-107 ~ 188) 296
4124 23:07:16.456270 ==
4125 23:07:16.459349 Dram Type= 6, Freq= 0, CH_0, rank 1
4126 23:07:16.466422 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4127 23:07:16.466503 ==
4128 23:07:16.466568 DQS Delay:
4129 23:07:16.466628 DQS0 = 0, DQS1 = 0
4130 23:07:16.469832 DQM Delay:
4131 23:07:16.469913 DQM0 = 41, DQM1 = 31
4132 23:07:16.472666 DQ Delay:
4133 23:07:16.476132 DQ0 =36, DQ1 =44, DQ2 =40, DQ3 =36
4134 23:07:16.476212 DQ4 =44, DQ5 =32, DQ6 =44, DQ7 =52
4135 23:07:16.479680 DQ8 =20, DQ9 =16, DQ10 =36, DQ11 =24
4136 23:07:16.485943 DQ12 =40, DQ13 =36, DQ14 =40, DQ15 =40
4137 23:07:16.486025
4138 23:07:16.486089
4139 23:07:16.492734 [DQSOSCAuto] RK1, (LSB)MR18= 0x6060, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps
4140 23:07:16.496271 CH0 RK1: MR19=808, MR18=6060
4141 23:07:16.502767 CH0_RK1: MR19=0x808, MR18=0x6060, DQSOSC=391, MR23=63, INC=171, DEC=114
4142 23:07:16.506022 [RxdqsGatingPostProcess] freq 600
4143 23:07:16.509532 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4144 23:07:16.512527 Pre-setting of DQS Precalculation
4145 23:07:16.519145 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4146 23:07:16.519228 ==
4147 23:07:16.522579 Dram Type= 6, Freq= 0, CH_1, rank 0
4148 23:07:16.525809 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4149 23:07:16.525891 ==
4150 23:07:16.532488 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4151 23:07:16.535809 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4152 23:07:16.540214 [CA 0] Center 35 (5~66) winsize 62
4153 23:07:16.543294 [CA 1] Center 35 (5~66) winsize 62
4154 23:07:16.547039 [CA 2] Center 33 (3~64) winsize 62
4155 23:07:16.550265 [CA 3] Center 33 (3~64) winsize 62
4156 23:07:16.553291 [CA 4] Center 33 (2~64) winsize 63
4157 23:07:16.557122 [CA 5] Center 33 (2~64) winsize 63
4158 23:07:16.557204
4159 23:07:16.560010 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4160 23:07:16.560091
4161 23:07:16.563367 [CATrainingPosCal] consider 1 rank data
4162 23:07:16.566721 u2DelayCellTimex100 = 270/100 ps
4163 23:07:16.569881 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4164 23:07:16.576421 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4165 23:07:16.579795 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4166 23:07:16.582992 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4167 23:07:16.586334 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
4168 23:07:16.589620 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4169 23:07:16.589707
4170 23:07:16.592930 CA PerBit enable=1, Macro0, CA PI delay=33
4171 23:07:16.593012
4172 23:07:16.596847 [CBTSetCACLKResult] CA Dly = 33
4173 23:07:16.596942 CS Dly: 4 (0~35)
4174 23:07:16.599496 ==
4175 23:07:16.603336 Dram Type= 6, Freq= 0, CH_1, rank 1
4176 23:07:16.606191 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4177 23:07:16.606273 ==
4178 23:07:16.613040 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4179 23:07:16.616164 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4180 23:07:16.620310 [CA 0] Center 35 (5~66) winsize 62
4181 23:07:16.623569 [CA 1] Center 34 (4~65) winsize 62
4182 23:07:16.627038 [CA 2] Center 33 (3~64) winsize 62
4183 23:07:16.629914 [CA 3] Center 33 (3~64) winsize 62
4184 23:07:16.633499 [CA 4] Center 32 (2~63) winsize 62
4185 23:07:16.636836 [CA 5] Center 32 (2~63) winsize 62
4186 23:07:16.636917
4187 23:07:16.639954 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4188 23:07:16.640036
4189 23:07:16.643250 [CATrainingPosCal] consider 2 rank data
4190 23:07:16.646815 u2DelayCellTimex100 = 270/100 ps
4191 23:07:16.649769 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
4192 23:07:16.656428 CA1 delay=35 (5~65),Diff = 3 PI (28 cell)
4193 23:07:16.659690 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
4194 23:07:16.663197 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
4195 23:07:16.666342 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
4196 23:07:16.669697 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
4197 23:07:16.669778
4198 23:07:16.672986 CA PerBit enable=1, Macro0, CA PI delay=32
4199 23:07:16.673068
4200 23:07:16.676272 [CBTSetCACLKResult] CA Dly = 32
4201 23:07:16.676353 CS Dly: 4 (0~36)
4202 23:07:16.680131
4203 23:07:16.683024 ----->DramcWriteLeveling(PI) begin...
4204 23:07:16.683107 ==
4205 23:07:16.686433 Dram Type= 6, Freq= 0, CH_1, rank 0
4206 23:07:16.690072 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4207 23:07:16.690156 ==
4208 23:07:16.693066 Write leveling (Byte 0): 26 => 26
4209 23:07:16.696241 Write leveling (Byte 1): 26 => 26
4210 23:07:16.700069 DramcWriteLeveling(PI) end<-----
4211 23:07:16.700149
4212 23:07:16.700213 ==
4213 23:07:16.703067 Dram Type= 6, Freq= 0, CH_1, rank 0
4214 23:07:16.706251 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4215 23:07:16.706333 ==
4216 23:07:16.709427 [Gating] SW mode calibration
4217 23:07:16.716050 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4218 23:07:16.722592 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4219 23:07:16.726263 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4220 23:07:16.729341 0 5 4 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
4221 23:07:16.735900 0 5 8 | B1->B0 | 2f2f 2525 | 1 0 | (1 1) (0 0)
4222 23:07:16.739501 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4223 23:07:16.742847 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4224 23:07:16.749405 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4225 23:07:16.752372 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4226 23:07:16.755950 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4227 23:07:16.762741 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4228 23:07:16.765687 0 6 4 | B1->B0 | 2424 3232 | 0 0 | (0 0) (0 0)
4229 23:07:16.769374 0 6 8 | B1->B0 | 3939 4343 | 0 0 | (0 0) (0 0)
4230 23:07:16.775661 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4231 23:07:16.778901 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4232 23:07:16.782273 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4233 23:07:16.788938 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4234 23:07:16.792241 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4235 23:07:16.795609 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4236 23:07:16.802007 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4237 23:07:16.805415 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4238 23:07:16.808645 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4239 23:07:16.815257 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4240 23:07:16.818773 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4241 23:07:16.822018 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4242 23:07:16.828458 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4243 23:07:16.831765 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4244 23:07:16.834983 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4245 23:07:16.838350 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4246 23:07:16.845440 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4247 23:07:16.848438 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4248 23:07:16.851727 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4249 23:07:16.858205 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4250 23:07:16.861894 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4251 23:07:16.865033 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4252 23:07:16.871709 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4253 23:07:16.875329 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4254 23:07:16.878550 Total UI for P1: 0, mck2ui 16
4255 23:07:16.881543 best dqsien dly found for B0: ( 0, 9, 4)
4256 23:07:16.884836 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4257 23:07:16.888025 Total UI for P1: 0, mck2ui 16
4258 23:07:16.891645 best dqsien dly found for B1: ( 0, 9, 8)
4259 23:07:16.894718 best DQS0 dly(MCK, UI, PI) = (0, 9, 4)
4260 23:07:16.897995 best DQS1 dly(MCK, UI, PI) = (0, 9, 8)
4261 23:07:16.901410
4262 23:07:16.904464 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 4)
4263 23:07:16.907688 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8)
4264 23:07:16.911083 [Gating] SW calibration Done
4265 23:07:16.911168 ==
4266 23:07:16.914459 Dram Type= 6, Freq= 0, CH_1, rank 0
4267 23:07:16.917927 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4268 23:07:16.918009 ==
4269 23:07:16.918073 RX Vref Scan: 0
4270 23:07:16.921032
4271 23:07:16.921111 RX Vref 0 -> 0, step: 1
4272 23:07:16.921175
4273 23:07:16.924260 RX Delay -230 -> 252, step: 16
4274 23:07:16.927760 iDelay=218, Bit 0, Center 41 (-134 ~ 217) 352
4275 23:07:16.934474 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4276 23:07:16.937480 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4277 23:07:16.941196 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4278 23:07:16.944446 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4279 23:07:16.947751 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4280 23:07:16.954122 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4281 23:07:16.957482 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4282 23:07:16.960778 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4283 23:07:16.964314 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4284 23:07:16.970910 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4285 23:07:16.973999 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4286 23:07:16.977490 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4287 23:07:16.980853 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4288 23:07:16.987184 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4289 23:07:16.990465 iDelay=218, Bit 15, Center 41 (-134 ~ 217) 352
4290 23:07:16.990546 ==
4291 23:07:16.993863 Dram Type= 6, Freq= 0, CH_1, rank 0
4292 23:07:16.997323 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4293 23:07:16.997409 ==
4294 23:07:17.000909 DQS Delay:
4295 23:07:17.000988 DQS0 = 0, DQS1 = 0
4296 23:07:17.001051 DQM Delay:
4297 23:07:17.004035 DQM0 = 38, DQM1 = 32
4298 23:07:17.004115 DQ Delay:
4299 23:07:17.007504 DQ0 =41, DQ1 =33, DQ2 =33, DQ3 =33
4300 23:07:17.010671 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4301 23:07:17.013707 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4302 23:07:17.017309 DQ12 =33, DQ13 =49, DQ14 =33, DQ15 =41
4303 23:07:17.017400
4304 23:07:17.017472
4305 23:07:17.017539 ==
4306 23:07:17.020291 Dram Type= 6, Freq= 0, CH_1, rank 0
4307 23:07:17.027042 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4308 23:07:17.027123 ==
4309 23:07:17.027186
4310 23:07:17.027244
4311 23:07:17.027301 TX Vref Scan disable
4312 23:07:17.030688 == TX Byte 0 ==
4313 23:07:17.034104 Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6)
4314 23:07:17.040669 Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6)
4315 23:07:17.040756 == TX Byte 1 ==
4316 23:07:17.043824 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4317 23:07:17.050662 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4318 23:07:17.050742 ==
4319 23:07:17.053570 Dram Type= 6, Freq= 0, CH_1, rank 0
4320 23:07:17.057066 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4321 23:07:17.057146 ==
4322 23:07:17.057209
4323 23:07:17.057267
4324 23:07:17.060446 TX Vref Scan disable
4325 23:07:17.063430 == TX Byte 0 ==
4326 23:07:17.066959 Update DQ dly =570 (2 ,1, 26) DQ OEN =(1 ,6)
4327 23:07:17.070247 Update DQM dly =570 (2 ,1, 26) DQM OEN =(1 ,6)
4328 23:07:17.073733 == TX Byte 1 ==
4329 23:07:17.077000 Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6)
4330 23:07:17.080445 Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6)
4331 23:07:17.080526
4332 23:07:17.080589 [DATLAT]
4333 23:07:17.083449 Freq=600, CH1 RK0
4334 23:07:17.083529
4335 23:07:17.087128 DATLAT Default: 0x9
4336 23:07:17.087210 0, 0xFFFF, sum = 0
4337 23:07:17.090240 1, 0xFFFF, sum = 0
4338 23:07:17.090326 2, 0xFFFF, sum = 0
4339 23:07:17.093459 3, 0xFFFF, sum = 0
4340 23:07:17.093541 4, 0xFFFF, sum = 0
4341 23:07:17.097210 5, 0xFFFF, sum = 0
4342 23:07:17.097293 6, 0xFFFF, sum = 0
4343 23:07:17.100238 7, 0x0, sum = 1
4344 23:07:17.100319 8, 0x0, sum = 2
4345 23:07:17.100384 9, 0x0, sum = 3
4346 23:07:17.103524 10, 0x0, sum = 4
4347 23:07:17.103606 best_step = 8
4348 23:07:17.103670
4349 23:07:17.103730 ==
4350 23:07:17.106758 Dram Type= 6, Freq= 0, CH_1, rank 0
4351 23:07:17.113849 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4352 23:07:17.113930 ==
4353 23:07:17.113993 RX Vref Scan: 1
4354 23:07:17.114053
4355 23:07:17.117010 RX Vref 0 -> 0, step: 1
4356 23:07:17.117091
4357 23:07:17.119907 RX Delay -195 -> 252, step: 8
4358 23:07:17.119987
4359 23:07:17.123309 Set Vref, RX VrefLevel [Byte0]: 51
4360 23:07:17.126554 [Byte1]: 50
4361 23:07:17.126635
4362 23:07:17.129936 Final RX Vref Byte 0 = 51 to rank0
4363 23:07:17.133386 Final RX Vref Byte 1 = 50 to rank0
4364 23:07:17.136597 Final RX Vref Byte 0 = 51 to rank1
4365 23:07:17.140087 Final RX Vref Byte 1 = 50 to rank1==
4366 23:07:17.143193 Dram Type= 6, Freq= 0, CH_1, rank 0
4367 23:07:17.146529 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4368 23:07:17.146635 ==
4369 23:07:17.149672 DQS Delay:
4370 23:07:17.149753 DQS0 = 0, DQS1 = 0
4371 23:07:17.153127 DQM Delay:
4372 23:07:17.153208 DQM0 = 37, DQM1 = 29
4373 23:07:17.153272 DQ Delay:
4374 23:07:17.156515 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =36
4375 23:07:17.159703 DQ4 =36, DQ5 =44, DQ6 =44, DQ7 =36
4376 23:07:17.162879 DQ8 =12, DQ9 =20, DQ10 =32, DQ11 =20
4377 23:07:17.166353 DQ12 =36, DQ13 =40, DQ14 =36, DQ15 =40
4378 23:07:17.166434
4379 23:07:17.166497
4380 23:07:17.176231 [DQSOSCAuto] RK0, (LSB)MR18= 0x7d7d, (MSB)MR19= 0x808, tDQSOscB0 = 386 ps tDQSOscB1 = 386 ps
4381 23:07:17.179381 CH1 RK0: MR19=808, MR18=7D7D
4382 23:07:17.185982 CH1_RK0: MR19=0x808, MR18=0x7D7D, DQSOSC=386, MR23=63, INC=176, DEC=117
4383 23:07:17.186063
4384 23:07:17.189555 ----->DramcWriteLeveling(PI) begin...
4385 23:07:17.189637 ==
4386 23:07:17.192906 Dram Type= 6, Freq= 0, CH_1, rank 1
4387 23:07:17.195901 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4388 23:07:17.195982 ==
4389 23:07:17.199579 Write leveling (Byte 0): 28 => 28
4390 23:07:17.202936 Write leveling (Byte 1): 28 => 28
4391 23:07:17.205993 DramcWriteLeveling(PI) end<-----
4392 23:07:17.206073
4393 23:07:17.206136 ==
4394 23:07:17.209308 Dram Type= 6, Freq= 0, CH_1, rank 1
4395 23:07:17.212850 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4396 23:07:17.212932 ==
4397 23:07:17.215977 [Gating] SW mode calibration
4398 23:07:17.222873 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4399 23:07:17.229280 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4400 23:07:17.232414 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4401 23:07:17.235809 0 5 4 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 0)
4402 23:07:17.242425 0 5 8 | B1->B0 | 3030 2323 | 1 0 | (1 0) (0 0)
4403 23:07:17.245784 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4404 23:07:17.248921 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4405 23:07:17.255806 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4406 23:07:17.258991 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4407 23:07:17.262382 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4408 23:07:17.268665 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4409 23:07:17.272025 0 6 4 | B1->B0 | 2626 2c2c | 0 0 | (1 1) (1 1)
4410 23:07:17.275355 0 6 8 | B1->B0 | 3636 4646 | 0 0 | (0 0) (0 0)
4411 23:07:17.281991 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4412 23:07:17.285422 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4413 23:07:17.288668 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4414 23:07:17.295435 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4415 23:07:17.298697 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4416 23:07:17.302081 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4417 23:07:17.308576 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4418 23:07:17.311868 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4419 23:07:17.315600 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4420 23:07:17.321933 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4421 23:07:17.325306 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4422 23:07:17.328634 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4423 23:07:17.335078 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4424 23:07:17.338341 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4425 23:07:17.341892 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4426 23:07:17.348267 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4427 23:07:17.351622 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4428 23:07:17.355174 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4429 23:07:17.361911 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4430 23:07:17.364771 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4431 23:07:17.368582 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4432 23:07:17.374876 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4433 23:07:17.378240 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4434 23:07:17.381492 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4435 23:07:17.384665 Total UI for P1: 0, mck2ui 16
4436 23:07:17.388222 best dqsien dly found for B0: ( 0, 9, 6)
4437 23:07:17.391560 Total UI for P1: 0, mck2ui 16
4438 23:07:17.395085 best dqsien dly found for B1: ( 0, 9, 6)
4439 23:07:17.398035 best DQS0 dly(MCK, UI, PI) = (0, 9, 6)
4440 23:07:17.401451 best DQS1 dly(MCK, UI, PI) = (0, 9, 6)
4441 23:07:17.401537
4442 23:07:17.404966 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 6)
4443 23:07:17.411298 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 6)
4444 23:07:17.411380 [Gating] SW calibration Done
4445 23:07:17.411446 ==
4446 23:07:17.414611 Dram Type= 6, Freq= 0, CH_1, rank 1
4447 23:07:17.421619 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4448 23:07:17.421703 ==
4449 23:07:17.421768 RX Vref Scan: 0
4450 23:07:17.421829
4451 23:07:17.424737 RX Vref 0 -> 0, step: 1
4452 23:07:17.424819
4453 23:07:17.428026 RX Delay -230 -> 252, step: 16
4454 23:07:17.431308 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4455 23:07:17.434526 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4456 23:07:17.437641 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4457 23:07:17.444547 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4458 23:07:17.447924 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4459 23:07:17.450996 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4460 23:07:17.454541 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4461 23:07:17.461272 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4462 23:07:17.464307 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4463 23:07:17.467658 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4464 23:07:17.471213 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4465 23:07:17.474359 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4466 23:07:17.481324 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4467 23:07:17.484231 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4468 23:07:17.487671 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4469 23:07:17.490994 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4470 23:07:17.494567 ==
4471 23:07:17.497536 Dram Type= 6, Freq= 0, CH_1, rank 1
4472 23:07:17.501038 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4473 23:07:17.501119 ==
4474 23:07:17.501183 DQS Delay:
4475 23:07:17.504188 DQS0 = 0, DQS1 = 0
4476 23:07:17.504268 DQM Delay:
4477 23:07:17.507488 DQM0 = 40, DQM1 = 34
4478 23:07:17.507568 DQ Delay:
4479 23:07:17.511014 DQ0 =41, DQ1 =33, DQ2 =33, DQ3 =33
4480 23:07:17.513961 DQ4 =41, DQ5 =57, DQ6 =49, DQ7 =33
4481 23:07:17.517589 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4482 23:07:17.520565 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =41
4483 23:07:17.520675
4484 23:07:17.520775
4485 23:07:17.520836 ==
4486 23:07:17.524065 Dram Type= 6, Freq= 0, CH_1, rank 1
4487 23:07:17.527787 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4488 23:07:17.527869 ==
4489 23:07:17.527933
4490 23:07:17.527992
4491 23:07:17.530803 TX Vref Scan disable
4492 23:07:17.533936 == TX Byte 0 ==
4493 23:07:17.537512 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4494 23:07:17.540375 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4495 23:07:17.543760 == TX Byte 1 ==
4496 23:07:17.547244 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4497 23:07:17.550705 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4498 23:07:17.550807 ==
4499 23:07:17.553656 Dram Type= 6, Freq= 0, CH_1, rank 1
4500 23:07:17.560237 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4501 23:07:17.560343 ==
4502 23:07:17.560437
4503 23:07:17.560525
4504 23:07:17.560615 TX Vref Scan disable
4505 23:07:17.564801 == TX Byte 0 ==
4506 23:07:17.568125 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4507 23:07:17.571377 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4508 23:07:17.575252 == TX Byte 1 ==
4509 23:07:17.578338 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4510 23:07:17.581422 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4511 23:07:17.584882
4512 23:07:17.584987 [DATLAT]
4513 23:07:17.585079 Freq=600, CH1 RK1
4514 23:07:17.585172
4515 23:07:17.587897 DATLAT Default: 0x8
4516 23:07:17.587996 0, 0xFFFF, sum = 0
4517 23:07:17.591234 1, 0xFFFF, sum = 0
4518 23:07:17.591335 2, 0xFFFF, sum = 0
4519 23:07:17.594537 3, 0xFFFF, sum = 0
4520 23:07:17.597755 4, 0xFFFF, sum = 0
4521 23:07:17.597862 5, 0xFFFF, sum = 0
4522 23:07:17.601187 6, 0xFFFF, sum = 0
4523 23:07:17.601295 7, 0x0, sum = 1
4524 23:07:17.601390 8, 0x0, sum = 2
4525 23:07:17.604891 9, 0x0, sum = 3
4526 23:07:17.604995 10, 0x0, sum = 4
4527 23:07:17.608319 best_step = 8
4528 23:07:17.608415
4529 23:07:17.608506 ==
4530 23:07:17.611408 Dram Type= 6, Freq= 0, CH_1, rank 1
4531 23:07:17.614620 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4532 23:07:17.614717 ==
4533 23:07:17.617738 RX Vref Scan: 0
4534 23:07:17.617824
4535 23:07:17.617892 RX Vref 0 -> 0, step: 1
4536 23:07:17.617951
4537 23:07:17.621245 RX Delay -195 -> 252, step: 8
4538 23:07:17.628088 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4539 23:07:17.631572 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4540 23:07:17.634811 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4541 23:07:17.638449 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4542 23:07:17.645048 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4543 23:07:17.648073 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4544 23:07:17.651640 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4545 23:07:17.654663 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4546 23:07:17.657999 iDelay=205, Bit 8, Center 12 (-147 ~ 172) 320
4547 23:07:17.664800 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4548 23:07:17.668126 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4549 23:07:17.671345 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4550 23:07:17.674956 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4551 23:07:17.681451 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4552 23:07:17.684814 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4553 23:07:17.688015 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4554 23:07:17.688122 ==
4555 23:07:17.691371 Dram Type= 6, Freq= 0, CH_1, rank 1
4556 23:07:17.697966 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4557 23:07:17.698070 ==
4558 23:07:17.698166 DQS Delay:
4559 23:07:17.698257 DQS0 = 0, DQS1 = 0
4560 23:07:17.701140 DQM Delay:
4561 23:07:17.701209 DQM0 = 36, DQM1 = 29
4562 23:07:17.704382 DQ Delay:
4563 23:07:17.707886 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =32
4564 23:07:17.711187 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =32
4565 23:07:17.714403 DQ8 =12, DQ9 =20, DQ10 =28, DQ11 =20
4566 23:07:17.717575 DQ12 =36, DQ13 =40, DQ14 =36, DQ15 =40
4567 23:07:17.717674
4568 23:07:17.717763
4569 23:07:17.724526 [DQSOSCAuto] RK1, (LSB)MR18= 0x5858, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
4570 23:07:17.727711 CH1 RK1: MR19=808, MR18=5858
4571 23:07:17.734272 CH1_RK1: MR19=0x808, MR18=0x5858, DQSOSC=393, MR23=63, INC=169, DEC=113
4572 23:07:17.737462 [RxdqsGatingPostProcess] freq 600
4573 23:07:17.741363 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4574 23:07:17.744577 Pre-setting of DQS Precalculation
4575 23:07:17.750579 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4576 23:07:17.757239 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4577 23:07:17.763685 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4578 23:07:17.763784
4579 23:07:17.763874
4580 23:07:17.767127 [Calibration Summary] 1200 Mbps
4581 23:07:17.767198 CH 0, Rank 0
4582 23:07:17.770558 SW Impedance : PASS
4583 23:07:17.773691 DUTY Scan : NO K
4584 23:07:17.773767 ZQ Calibration : PASS
4585 23:07:17.776983 Jitter Meter : NO K
4586 23:07:17.780587 CBT Training : PASS
4587 23:07:17.780728 Write leveling : PASS
4588 23:07:17.783965 RX DQS gating : PASS
4589 23:07:17.787234 RX DQ/DQS(RDDQC) : PASS
4590 23:07:17.787336 TX DQ/DQS : PASS
4591 23:07:17.790331 RX DATLAT : PASS
4592 23:07:17.793569 RX DQ/DQS(Engine): PASS
4593 23:07:17.793671 TX OE : NO K
4594 23:07:17.796970 All Pass.
4595 23:07:17.797068
4596 23:07:17.797168 CH 0, Rank 1
4597 23:07:17.800270 SW Impedance : PASS
4598 23:07:17.800373 DUTY Scan : NO K
4599 23:07:17.803481 ZQ Calibration : PASS
4600 23:07:17.806965 Jitter Meter : NO K
4601 23:07:17.807066 CBT Training : PASS
4602 23:07:17.810411 Write leveling : PASS
4603 23:07:17.810509 RX DQS gating : PASS
4604 23:07:17.813591 RX DQ/DQS(RDDQC) : PASS
4605 23:07:17.816879 TX DQ/DQS : PASS
4606 23:07:17.816953 RX DATLAT : PASS
4607 23:07:17.820273 RX DQ/DQS(Engine): PASS
4608 23:07:17.823450 TX OE : NO K
4609 23:07:17.823545 All Pass.
4610 23:07:17.823610
4611 23:07:17.823672 CH 1, Rank 0
4612 23:07:17.826753 SW Impedance : PASS
4613 23:07:17.830258 DUTY Scan : NO K
4614 23:07:17.830339 ZQ Calibration : PASS
4615 23:07:17.833342 Jitter Meter : NO K
4616 23:07:17.836507 CBT Training : PASS
4617 23:07:17.836588 Write leveling : PASS
4618 23:07:17.839874 RX DQS gating : PASS
4619 23:07:17.843181 RX DQ/DQS(RDDQC) : PASS
4620 23:07:17.843262 TX DQ/DQS : PASS
4621 23:07:17.846645 RX DATLAT : PASS
4622 23:07:17.849914 RX DQ/DQS(Engine): PASS
4623 23:07:17.849994 TX OE : NO K
4624 23:07:17.853686 All Pass.
4625 23:07:17.853767
4626 23:07:17.853831 CH 1, Rank 1
4627 23:07:17.856726 SW Impedance : PASS
4628 23:07:17.856831 DUTY Scan : NO K
4629 23:07:17.860169 ZQ Calibration : PASS
4630 23:07:17.863035 Jitter Meter : NO K
4631 23:07:17.863109 CBT Training : PASS
4632 23:07:17.866576 Write leveling : PASS
4633 23:07:17.866654 RX DQS gating : PASS
4634 23:07:17.869722 RX DQ/DQS(RDDQC) : PASS
4635 23:07:17.873059 TX DQ/DQS : PASS
4636 23:07:17.873135 RX DATLAT : PASS
4637 23:07:17.876562 RX DQ/DQS(Engine): PASS
4638 23:07:17.879564 TX OE : NO K
4639 23:07:17.879663 All Pass.
4640 23:07:17.879761
4641 23:07:17.882875 DramC Write-DBI off
4642 23:07:17.882974 PER_BANK_REFRESH: Hybrid Mode
4643 23:07:17.886255 TX_TRACKING: ON
4644 23:07:17.896497 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4645 23:07:17.899461 [FAST_K] Save calibration result to emmc
4646 23:07:17.902970 dramc_set_vcore_voltage set vcore to 662500
4647 23:07:17.903073 Read voltage for 933, 3
4648 23:07:17.906501 Vio18 = 0
4649 23:07:17.906603 Vcore = 662500
4650 23:07:17.906701 Vdram = 0
4651 23:07:17.909641 Vddq = 0
4652 23:07:17.909738 Vmddr = 0
4653 23:07:17.912861 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4654 23:07:17.919507 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4655 23:07:17.922843 MEM_TYPE=3, freq_sel=17
4656 23:07:17.926345 sv_algorithm_assistance_LP4_1600
4657 23:07:17.929488 ============ PULL DRAM RESETB DOWN ============
4658 23:07:17.932613 ========== PULL DRAM RESETB DOWN end =========
4659 23:07:17.939599 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4660 23:07:17.942937 ===================================
4661 23:07:17.943039 LPDDR4 DRAM CONFIGURATION
4662 23:07:17.946376 ===================================
4663 23:07:17.949571 EX_ROW_EN[0] = 0x0
4664 23:07:17.949647 EX_ROW_EN[1] = 0x0
4665 23:07:17.952690 LP4Y_EN = 0x0
4666 23:07:17.952806 WORK_FSP = 0x0
4667 23:07:17.956160 WL = 0x3
4668 23:07:17.959249 RL = 0x3
4669 23:07:17.959345 BL = 0x2
4670 23:07:17.962525 RPST = 0x0
4671 23:07:17.962624 RD_PRE = 0x0
4672 23:07:17.966133 WR_PRE = 0x1
4673 23:07:17.966230 WR_PST = 0x0
4674 23:07:17.969291 DBI_WR = 0x0
4675 23:07:17.969391 DBI_RD = 0x0
4676 23:07:17.972860 OTF = 0x1
4677 23:07:17.975967 ===================================
4678 23:07:17.979288 ===================================
4679 23:07:17.979387 ANA top config
4680 23:07:17.982596 ===================================
4681 23:07:17.985988 DLL_ASYNC_EN = 0
4682 23:07:17.989717 ALL_SLAVE_EN = 1
4683 23:07:17.989797 NEW_RANK_MODE = 1
4684 23:07:17.992731 DLL_IDLE_MODE = 1
4685 23:07:17.995918 LP45_APHY_COMB_EN = 1
4686 23:07:17.999162 TX_ODT_DIS = 1
4687 23:07:17.999264 NEW_8X_MODE = 1
4688 23:07:18.002678 ===================================
4689 23:07:18.006291 ===================================
4690 23:07:18.009177 data_rate = 1866
4691 23:07:18.012688 CKR = 1
4692 23:07:18.015746 DQ_P2S_RATIO = 8
4693 23:07:18.019148 ===================================
4694 23:07:18.022359 CA_P2S_RATIO = 8
4695 23:07:18.025739 DQ_CA_OPEN = 0
4696 23:07:18.029093 DQ_SEMI_OPEN = 0
4697 23:07:18.029166 CA_SEMI_OPEN = 0
4698 23:07:18.032217 CA_FULL_RATE = 0
4699 23:07:18.035344 DQ_CKDIV4_EN = 1
4700 23:07:18.038813 CA_CKDIV4_EN = 1
4701 23:07:18.042115 CA_PREDIV_EN = 0
4702 23:07:18.045394 PH8_DLY = 0
4703 23:07:18.045473 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4704 23:07:18.048692 DQ_AAMCK_DIV = 4
4705 23:07:18.052094 CA_AAMCK_DIV = 4
4706 23:07:18.055310 CA_ADMCK_DIV = 4
4707 23:07:18.058739 DQ_TRACK_CA_EN = 0
4708 23:07:18.061942 CA_PICK = 933
4709 23:07:18.065687 CA_MCKIO = 933
4710 23:07:18.065761 MCKIO_SEMI = 0
4711 23:07:18.068825 PLL_FREQ = 3732
4712 23:07:18.072007 DQ_UI_PI_RATIO = 32
4713 23:07:18.075747 CA_UI_PI_RATIO = 0
4714 23:07:18.078698 ===================================
4715 23:07:18.082070 ===================================
4716 23:07:18.085336 memory_type:LPDDR4
4717 23:07:18.085413 GP_NUM : 10
4718 23:07:18.088907 SRAM_EN : 1
4719 23:07:18.088980 MD32_EN : 0
4720 23:07:18.091931 ===================================
4721 23:07:18.095445 [ANA_INIT] >>>>>>>>>>>>>>
4722 23:07:18.098486 <<<<<< [CONFIGURE PHASE]: ANA_TX
4723 23:07:18.101717 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4724 23:07:18.105293 ===================================
4725 23:07:18.108618 data_rate = 1866,PCW = 0X8f00
4726 23:07:18.111714 ===================================
4727 23:07:18.115137 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4728 23:07:18.121590 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4729 23:07:18.125171 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4730 23:07:18.131964 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4731 23:07:18.134868 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4732 23:07:18.138407 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4733 23:07:18.138508 [ANA_INIT] flow start
4734 23:07:18.141445 [ANA_INIT] PLL >>>>>>>>
4735 23:07:18.144857 [ANA_INIT] PLL <<<<<<<<
4736 23:07:18.144939 [ANA_INIT] MIDPI >>>>>>>>
4737 23:07:18.148223 [ANA_INIT] MIDPI <<<<<<<<
4738 23:07:18.151349 [ANA_INIT] DLL >>>>>>>>
4739 23:07:18.151431 [ANA_INIT] flow end
4740 23:07:18.158102 ============ LP4 DIFF to SE enter ============
4741 23:07:18.161557 ============ LP4 DIFF to SE exit ============
4742 23:07:18.164724 [ANA_INIT] <<<<<<<<<<<<<
4743 23:07:18.168209 [Flow] Enable top DCM control >>>>>
4744 23:07:18.171463 [Flow] Enable top DCM control <<<<<
4745 23:07:18.171545 Enable DLL master slave shuffle
4746 23:07:18.178053 ==============================================================
4747 23:07:18.181803 Gating Mode config
4748 23:07:18.184964 ==============================================================
4749 23:07:18.187997 Config description:
4750 23:07:18.198058 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4751 23:07:18.204621 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4752 23:07:18.207825 SELPH_MODE 0: By rank 1: By Phase
4753 23:07:18.214565 ==============================================================
4754 23:07:18.217824 GAT_TRACK_EN = 1
4755 23:07:18.221160 RX_GATING_MODE = 2
4756 23:07:18.224285 RX_GATING_TRACK_MODE = 2
4757 23:07:18.227578 SELPH_MODE = 1
4758 23:07:18.231072 PICG_EARLY_EN = 1
4759 23:07:18.231153 VALID_LAT_VALUE = 1
4760 23:07:18.237591 ==============================================================
4761 23:07:18.241019 Enter into Gating configuration >>>>
4762 23:07:18.244153 Exit from Gating configuration <<<<
4763 23:07:18.247532 Enter into DVFS_PRE_config >>>>>
4764 23:07:18.257751 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4765 23:07:18.260784 Exit from DVFS_PRE_config <<<<<
4766 23:07:18.264254 Enter into PICG configuration >>>>
4767 23:07:18.267476 Exit from PICG configuration <<<<
4768 23:07:18.270769 [RX_INPUT] configuration >>>>>
4769 23:07:18.274163 [RX_INPUT] configuration <<<<<
4770 23:07:18.277316 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4771 23:07:18.284420 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4772 23:07:18.290606 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4773 23:07:18.297312 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4774 23:07:18.303807 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4775 23:07:18.310554 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4776 23:07:18.313804 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4777 23:07:18.317681 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4778 23:07:18.320547 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4779 23:07:18.323888 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4780 23:07:18.330537 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4781 23:07:18.333895 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4782 23:07:18.337487 ===================================
4783 23:07:18.340619 LPDDR4 DRAM CONFIGURATION
4784 23:07:18.344188 ===================================
4785 23:07:18.344287 EX_ROW_EN[0] = 0x0
4786 23:07:18.347067 EX_ROW_EN[1] = 0x0
4787 23:07:18.347174 LP4Y_EN = 0x0
4788 23:07:18.350396 WORK_FSP = 0x0
4789 23:07:18.350495 WL = 0x3
4790 23:07:18.353616 RL = 0x3
4791 23:07:18.357093 BL = 0x2
4792 23:07:18.357172 RPST = 0x0
4793 23:07:18.360478 RD_PRE = 0x0
4794 23:07:18.360557 WR_PRE = 0x1
4795 23:07:18.363830 WR_PST = 0x0
4796 23:07:18.363938 DBI_WR = 0x0
4797 23:07:18.366884 DBI_RD = 0x0
4798 23:07:18.366963 OTF = 0x1
4799 23:07:18.370534 ===================================
4800 23:07:18.373908 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4801 23:07:18.380215 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4802 23:07:18.383582 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4803 23:07:18.387136 ===================================
4804 23:07:18.390345 LPDDR4 DRAM CONFIGURATION
4805 23:07:18.393624 ===================================
4806 23:07:18.393763 EX_ROW_EN[0] = 0x10
4807 23:07:18.397175 EX_ROW_EN[1] = 0x0
4808 23:07:18.397255 LP4Y_EN = 0x0
4809 23:07:18.400357 WORK_FSP = 0x0
4810 23:07:18.400436 WL = 0x3
4811 23:07:18.403597 RL = 0x3
4812 23:07:18.403690 BL = 0x2
4813 23:07:18.407016 RPST = 0x0
4814 23:07:18.407096 RD_PRE = 0x0
4815 23:07:18.410275 WR_PRE = 0x1
4816 23:07:18.413478 WR_PST = 0x0
4817 23:07:18.413570 DBI_WR = 0x0
4818 23:07:18.416966 DBI_RD = 0x0
4819 23:07:18.417089 OTF = 0x1
4820 23:07:18.420098 ===================================
4821 23:07:18.426635 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
4822 23:07:18.430211 nWR fixed to 30
4823 23:07:18.434027 [ModeRegInit_LP4] CH0 RK0
4824 23:07:18.434106 [ModeRegInit_LP4] CH0 RK1
4825 23:07:18.437206 [ModeRegInit_LP4] CH1 RK0
4826 23:07:18.440409 [ModeRegInit_LP4] CH1 RK1
4827 23:07:18.440488 match AC timing 8
4828 23:07:18.446978 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 0
4829 23:07:18.450145 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4830 23:07:18.453555 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
4831 23:07:18.460364 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
4832 23:07:18.463442 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
4833 23:07:18.463523 ==
4834 23:07:18.466740 Dram Type= 6, Freq= 0, CH_0, rank 0
4835 23:07:18.469910 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4836 23:07:18.469992 ==
4837 23:07:18.476537 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4838 23:07:18.483130 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4839 23:07:18.486487 [CA 0] Center 38 (8~69) winsize 62
4840 23:07:18.489724 [CA 1] Center 38 (8~69) winsize 62
4841 23:07:18.493093 [CA 2] Center 36 (6~67) winsize 62
4842 23:07:18.496939 [CA 3] Center 36 (6~66) winsize 61
4843 23:07:18.499914 [CA 4] Center 34 (4~65) winsize 62
4844 23:07:18.503144 [CA 5] Center 34 (4~65) winsize 62
4845 23:07:18.503225
4846 23:07:18.506557 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4847 23:07:18.506638
4848 23:07:18.509500 [CATrainingPosCal] consider 1 rank data
4849 23:07:18.513366 u2DelayCellTimex100 = 270/100 ps
4850 23:07:18.516680 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4851 23:07:18.519881 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4852 23:07:18.522940 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4853 23:07:18.526686 CA3 delay=36 (6~66),Diff = 2 PI (12 cell)
4854 23:07:18.529712 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4855 23:07:18.536163 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4856 23:07:18.536245
4857 23:07:18.539896 CA PerBit enable=1, Macro0, CA PI delay=34
4858 23:07:18.539977
4859 23:07:18.542881 [CBTSetCACLKResult] CA Dly = 34
4860 23:07:18.542963 CS Dly: 7 (0~38)
4861 23:07:18.543027 ==
4862 23:07:18.546305 Dram Type= 6, Freq= 0, CH_0, rank 1
4863 23:07:18.549711 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4864 23:07:18.552850 ==
4865 23:07:18.556610 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4866 23:07:18.562924 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
4867 23:07:18.566227 [CA 0] Center 38 (8~69) winsize 62
4868 23:07:18.569510 [CA 1] Center 38 (7~69) winsize 63
4869 23:07:18.572862 [CA 2] Center 36 (5~67) winsize 63
4870 23:07:18.575899 [CA 3] Center 35 (5~66) winsize 62
4871 23:07:18.579341 [CA 4] Center 34 (4~65) winsize 62
4872 23:07:18.582595 [CA 5] Center 34 (4~65) winsize 62
4873 23:07:18.582676
4874 23:07:18.586015 [CmdBusTrainingLP45] Vref(ca) range 1: 39
4875 23:07:18.586096
4876 23:07:18.589258 [CATrainingPosCal] consider 2 rank data
4877 23:07:18.592654 u2DelayCellTimex100 = 270/100 ps
4878 23:07:18.596142 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4879 23:07:18.599155 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4880 23:07:18.602344 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4881 23:07:18.608929 CA3 delay=36 (6~66),Diff = 2 PI (12 cell)
4882 23:07:18.612187 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4883 23:07:18.615944 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4884 23:07:18.616044
4885 23:07:18.619140 CA PerBit enable=1, Macro0, CA PI delay=34
4886 23:07:18.619222
4887 23:07:18.622131 [CBTSetCACLKResult] CA Dly = 34
4888 23:07:18.622218 CS Dly: 7 (0~39)
4889 23:07:18.622302
4890 23:07:18.625603 ----->DramcWriteLeveling(PI) begin...
4891 23:07:18.628887 ==
4892 23:07:18.628969 Dram Type= 6, Freq= 0, CH_0, rank 0
4893 23:07:18.635666 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4894 23:07:18.635748 ==
4895 23:07:18.638978 Write leveling (Byte 0): 28 => 28
4896 23:07:18.642418 Write leveling (Byte 1): 29 => 29
4897 23:07:18.645670 DramcWriteLeveling(PI) end<-----
4898 23:07:18.645780
4899 23:07:18.645882 ==
4900 23:07:18.648837 Dram Type= 6, Freq= 0, CH_0, rank 0
4901 23:07:18.652047 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4902 23:07:18.652153 ==
4903 23:07:18.655572 [Gating] SW mode calibration
4904 23:07:18.662138 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
4905 23:07:18.668731 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
4906 23:07:18.672061 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4907 23:07:18.675574 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4908 23:07:18.678582 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4909 23:07:18.685060 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4910 23:07:18.688599 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4911 23:07:18.691858 0 10 20 | B1->B0 | 3232 2f2f | 0 0 | (0 0) (0 1)
4912 23:07:18.698371 0 10 24 | B1->B0 | 3030 2323 | 0 0 | (1 1) (0 0)
4913 23:07:18.701572 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4914 23:07:18.705015 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4915 23:07:18.711696 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4916 23:07:18.715163 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4917 23:07:18.718510 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4918 23:07:18.724985 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4919 23:07:18.728063 0 11 20 | B1->B0 | 2a2a 3434 | 0 0 | (0 0) (0 0)
4920 23:07:18.731341 0 11 24 | B1->B0 | 3939 4343 | 0 0 | (0 0) (0 0)
4921 23:07:18.738093 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4922 23:07:18.741246 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4923 23:07:18.744667 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4924 23:07:18.751601 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4925 23:07:18.754786 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4926 23:07:18.758354 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4927 23:07:18.765255 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4928 23:07:18.767875 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4929 23:07:18.771323 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4930 23:07:18.778202 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4931 23:07:18.781147 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4932 23:07:18.784385 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4933 23:07:18.791301 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4934 23:07:18.794523 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4935 23:07:18.797785 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4936 23:07:18.804648 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4937 23:07:18.807534 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4938 23:07:18.810929 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4939 23:07:18.817616 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4940 23:07:18.820859 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4941 23:07:18.824068 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4942 23:07:18.830664 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4943 23:07:18.834187 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4944 23:07:18.837427 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4945 23:07:18.840653 Total UI for P1: 0, mck2ui 16
4946 23:07:18.843981 best dqsien dly found for B0: ( 0, 14, 20)
4947 23:07:18.847175 Total UI for P1: 0, mck2ui 16
4948 23:07:18.850638 best dqsien dly found for B1: ( 0, 14, 20)
4949 23:07:18.853914 best DQS0 dly(MCK, UI, PI) = (0, 14, 20)
4950 23:07:18.857038 best DQS1 dly(MCK, UI, PI) = (0, 14, 20)
4951 23:07:18.860396
4952 23:07:18.863681 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 20)
4953 23:07:18.866902 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20)
4954 23:07:18.870354 [Gating] SW calibration Done
4955 23:07:18.870451 ==
4956 23:07:18.873957 Dram Type= 6, Freq= 0, CH_0, rank 0
4957 23:07:18.877207 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4958 23:07:18.877295 ==
4959 23:07:18.877361 RX Vref Scan: 0
4960 23:07:18.880326
4961 23:07:18.880407 RX Vref 0 -> 0, step: 1
4962 23:07:18.880471
4963 23:07:18.883755 RX Delay -80 -> 252, step: 8
4964 23:07:18.887030 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
4965 23:07:18.890575 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
4966 23:07:18.896594 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
4967 23:07:18.900139 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
4968 23:07:18.903334 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
4969 23:07:18.906767 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
4970 23:07:18.910011 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
4971 23:07:18.913141 iDelay=208, Bit 7, Center 103 (0 ~ 207) 208
4972 23:07:18.920027 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
4973 23:07:18.923295 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
4974 23:07:18.926687 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
4975 23:07:18.929958 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
4976 23:07:18.933068 iDelay=208, Bit 12, Center 91 (0 ~ 183) 184
4977 23:07:18.936397 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
4978 23:07:18.943315 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
4979 23:07:18.946427 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
4980 23:07:18.946530 ==
4981 23:07:18.949764 Dram Type= 6, Freq= 0, CH_0, rank 0
4982 23:07:18.953432 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4983 23:07:18.953526 ==
4984 23:07:18.953613 DQS Delay:
4985 23:07:18.956421 DQS0 = 0, DQS1 = 0
4986 23:07:18.956512 DQM Delay:
4987 23:07:18.959553 DQM0 = 96, DQM1 = 88
4988 23:07:18.959647 DQ Delay:
4989 23:07:18.962921 DQ0 =95, DQ1 =95, DQ2 =95, DQ3 =95
4990 23:07:18.966295 DQ4 =99, DQ5 =87, DQ6 =103, DQ7 =103
4991 23:07:18.969651 DQ8 =79, DQ9 =71, DQ10 =91, DQ11 =87
4992 23:07:18.972800 DQ12 =91, DQ13 =95, DQ14 =95, DQ15 =95
4993 23:07:18.972897
4994 23:07:18.972982
4995 23:07:18.973071 ==
4996 23:07:18.976452 Dram Type= 6, Freq= 0, CH_0, rank 0
4997 23:07:18.982757 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4998 23:07:18.982868 ==
4999 23:07:18.982959
5000 23:07:18.983054
5001 23:07:18.983145 TX Vref Scan disable
5002 23:07:18.986313 == TX Byte 0 ==
5003 23:07:18.989577 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5004 23:07:18.996083 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5005 23:07:18.996190 == TX Byte 1 ==
5006 23:07:18.999646 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5007 23:07:19.006029 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5008 23:07:19.006138 ==
5009 23:07:19.009630 Dram Type= 6, Freq= 0, CH_0, rank 0
5010 23:07:19.012778 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5011 23:07:19.012867 ==
5012 23:07:19.012956
5013 23:07:19.013053
5014 23:07:19.015905 TX Vref Scan disable
5015 23:07:19.016003 == TX Byte 0 ==
5016 23:07:19.022440 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5017 23:07:19.025972 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5018 23:07:19.026078 == TX Byte 1 ==
5019 23:07:19.032306 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5020 23:07:19.035901 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5021 23:07:19.035998
5022 23:07:19.036092 [DATLAT]
5023 23:07:19.038999 Freq=933, CH0 RK0
5024 23:07:19.039106
5025 23:07:19.039198 DATLAT Default: 0xd
5026 23:07:19.042451 0, 0xFFFF, sum = 0
5027 23:07:19.042560 1, 0xFFFF, sum = 0
5028 23:07:19.045907 2, 0xFFFF, sum = 0
5029 23:07:19.046004 3, 0xFFFF, sum = 0
5030 23:07:19.049190 4, 0xFFFF, sum = 0
5031 23:07:19.052380 5, 0xFFFF, sum = 0
5032 23:07:19.052480 6, 0xFFFF, sum = 0
5033 23:07:19.055801 7, 0xFFFF, sum = 0
5034 23:07:19.055898 8, 0xFFFF, sum = 0
5035 23:07:19.059352 9, 0xFFFF, sum = 0
5036 23:07:19.059453 10, 0x0, sum = 1
5037 23:07:19.062150 11, 0x0, sum = 2
5038 23:07:19.062248 12, 0x0, sum = 3
5039 23:07:19.062338 13, 0x0, sum = 4
5040 23:07:19.065652 best_step = 11
5041 23:07:19.065746
5042 23:07:19.065833 ==
5043 23:07:19.068841 Dram Type= 6, Freq= 0, CH_0, rank 0
5044 23:07:19.072018 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5045 23:07:19.072120 ==
5046 23:07:19.075268 RX Vref Scan: 1
5047 23:07:19.075366
5048 23:07:19.078556 RX Vref 0 -> 0, step: 1
5049 23:07:19.078650
5050 23:07:19.078739 RX Delay -69 -> 252, step: 4
5051 23:07:19.078827
5052 23:07:19.082097 Set Vref, RX VrefLevel [Byte0]: 47
5053 23:07:19.085203 [Byte1]: 42
5054 23:07:19.089879
5055 23:07:19.089977 Final RX Vref Byte 0 = 47 to rank0
5056 23:07:19.093275 Final RX Vref Byte 1 = 42 to rank0
5057 23:07:19.096532 Final RX Vref Byte 0 = 47 to rank1
5058 23:07:19.099813 Final RX Vref Byte 1 = 42 to rank1==
5059 23:07:19.103232 Dram Type= 6, Freq= 0, CH_0, rank 0
5060 23:07:19.109839 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5061 23:07:19.109941 ==
5062 23:07:19.110032 DQS Delay:
5063 23:07:19.110118 DQS0 = 0, DQS1 = 0
5064 23:07:19.113254 DQM Delay:
5065 23:07:19.113346 DQM0 = 96, DQM1 = 86
5066 23:07:19.116647 DQ Delay:
5067 23:07:19.119915 DQ0 =92, DQ1 =98, DQ2 =94, DQ3 =94
5068 23:07:19.123634 DQ4 =100, DQ5 =86, DQ6 =104, DQ7 =104
5069 23:07:19.126607 DQ8 =76, DQ9 =70, DQ10 =86, DQ11 =78
5070 23:07:19.129745 DQ12 =92, DQ13 =92, DQ14 =98, DQ15 =96
5071 23:07:19.129843
5072 23:07:19.129923
5073 23:07:19.136439 [DQSOSCAuto] RK0, (LSB)MR18= 0x2121, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 411 ps
5074 23:07:19.139961 CH0 RK0: MR19=505, MR18=2121
5075 23:07:19.146430 CH0_RK0: MR19=0x505, MR18=0x2121, DQSOSC=411, MR23=63, INC=64, DEC=42
5076 23:07:19.146531
5077 23:07:19.149731 ----->DramcWriteLeveling(PI) begin...
5078 23:07:19.149828 ==
5079 23:07:19.153034 Dram Type= 6, Freq= 0, CH_0, rank 1
5080 23:07:19.156265 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5081 23:07:19.156365 ==
5082 23:07:19.159369 Write leveling (Byte 0): 26 => 26
5083 23:07:19.162844 Write leveling (Byte 1): 26 => 26
5084 23:07:19.166134 DramcWriteLeveling(PI) end<-----
5085 23:07:19.166201
5086 23:07:19.166260 ==
5087 23:07:19.169252 Dram Type= 6, Freq= 0, CH_0, rank 1
5088 23:07:19.172844 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5089 23:07:19.172911 ==
5090 23:07:19.176187 [Gating] SW mode calibration
5091 23:07:19.182740 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5092 23:07:19.189427 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5093 23:07:19.192989 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5094 23:07:19.199433 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5095 23:07:19.202811 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5096 23:07:19.205840 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5097 23:07:19.212560 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5098 23:07:19.215793 0 10 20 | B1->B0 | 3333 2f2f | 0 0 | (0 1) (0 1)
5099 23:07:19.219435 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
5100 23:07:19.225610 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5101 23:07:19.229029 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5102 23:07:19.232535 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5103 23:07:19.239001 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5104 23:07:19.242685 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5105 23:07:19.246027 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5106 23:07:19.252200 0 11 20 | B1->B0 | 3131 3a3a | 0 0 | (1 1) (0 0)
5107 23:07:19.255540 0 11 24 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
5108 23:07:19.258739 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5109 23:07:19.265701 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5110 23:07:19.268902 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5111 23:07:19.272278 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5112 23:07:19.278474 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5113 23:07:19.281838 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5114 23:07:19.285151 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5115 23:07:19.291700 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5116 23:07:19.295051 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5117 23:07:19.298202 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5118 23:07:19.305019 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5119 23:07:19.308375 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5120 23:07:19.311464 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5121 23:07:19.318019 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5122 23:07:19.321421 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5123 23:07:19.325164 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5124 23:07:19.331558 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5125 23:07:19.335020 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5126 23:07:19.338038 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5127 23:07:19.341600 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5128 23:07:19.348026 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5129 23:07:19.351915 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5130 23:07:19.354919 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5131 23:07:19.361777 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5132 23:07:19.364979 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5133 23:07:19.368002 Total UI for P1: 0, mck2ui 16
5134 23:07:19.371300 best dqsien dly found for B0: ( 0, 14, 20)
5135 23:07:19.374811 Total UI for P1: 0, mck2ui 16
5136 23:07:19.378260 best dqsien dly found for B1: ( 0, 14, 22)
5137 23:07:19.381448 best DQS0 dly(MCK, UI, PI) = (0, 14, 20)
5138 23:07:19.384523 best DQS1 dly(MCK, UI, PI) = (0, 14, 22)
5139 23:07:19.384604
5140 23:07:19.388166 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 20)
5141 23:07:19.394436 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 22)
5142 23:07:19.394519 [Gating] SW calibration Done
5143 23:07:19.394620 ==
5144 23:07:19.398396 Dram Type= 6, Freq= 0, CH_0, rank 1
5145 23:07:19.404501 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5146 23:07:19.404583 ==
5147 23:07:19.404648 RX Vref Scan: 0
5148 23:07:19.404716
5149 23:07:19.407804 RX Vref 0 -> 0, step: 1
5150 23:07:19.407885
5151 23:07:19.411242 RX Delay -80 -> 252, step: 8
5152 23:07:19.414632 iDelay=200, Bit 0, Center 91 (-8 ~ 191) 200
5153 23:07:19.417693 iDelay=200, Bit 1, Center 99 (0 ~ 199) 200
5154 23:07:19.421032 iDelay=200, Bit 2, Center 91 (-8 ~ 191) 200
5155 23:07:19.424622 iDelay=200, Bit 3, Center 87 (-8 ~ 183) 192
5156 23:07:19.430965 iDelay=200, Bit 4, Center 99 (0 ~ 199) 200
5157 23:07:19.434030 iDelay=200, Bit 5, Center 87 (-16 ~ 191) 208
5158 23:07:19.437585 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5159 23:07:19.440855 iDelay=200, Bit 7, Center 103 (8 ~ 199) 192
5160 23:07:19.444338 iDelay=200, Bit 8, Center 75 (-16 ~ 167) 184
5161 23:07:19.450748 iDelay=200, Bit 9, Center 71 (-24 ~ 167) 192
5162 23:07:19.453955 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5163 23:07:19.457296 iDelay=200, Bit 11, Center 75 (-16 ~ 167) 184
5164 23:07:19.460649 iDelay=200, Bit 12, Center 95 (8 ~ 183) 176
5165 23:07:19.463981 iDelay=200, Bit 13, Center 91 (-8 ~ 191) 200
5166 23:07:19.470771 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5167 23:07:19.473869 iDelay=200, Bit 15, Center 95 (8 ~ 183) 176
5168 23:07:19.473950 ==
5169 23:07:19.477562 Dram Type= 6, Freq= 0, CH_0, rank 1
5170 23:07:19.480487 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5171 23:07:19.480569 ==
5172 23:07:19.480634 DQS Delay:
5173 23:07:19.483690 DQS0 = 0, DQS1 = 0
5174 23:07:19.483771 DQM Delay:
5175 23:07:19.487209 DQM0 = 95, DQM1 = 85
5176 23:07:19.487291 DQ Delay:
5177 23:07:19.490520 DQ0 =91, DQ1 =99, DQ2 =91, DQ3 =87
5178 23:07:19.494259 DQ4 =99, DQ5 =87, DQ6 =103, DQ7 =103
5179 23:07:19.497207 DQ8 =75, DQ9 =71, DQ10 =87, DQ11 =75
5180 23:07:19.500560 DQ12 =95, DQ13 =91, DQ14 =95, DQ15 =95
5181 23:07:19.500642
5182 23:07:19.500714
5183 23:07:19.500805 ==
5184 23:07:19.503653 Dram Type= 6, Freq= 0, CH_0, rank 1
5185 23:07:19.507096 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5186 23:07:19.510373 ==
5187 23:07:19.510453
5188 23:07:19.510517
5189 23:07:19.510576 TX Vref Scan disable
5190 23:07:19.513614 == TX Byte 0 ==
5191 23:07:19.516764 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5192 23:07:19.520162 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5193 23:07:19.523660 == TX Byte 1 ==
5194 23:07:19.526872 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5195 23:07:19.530343 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5196 23:07:19.533690 ==
5197 23:07:19.536906 Dram Type= 6, Freq= 0, CH_0, rank 1
5198 23:07:19.540343 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5199 23:07:19.540424 ==
5200 23:07:19.540488
5201 23:07:19.540548
5202 23:07:19.543405 TX Vref Scan disable
5203 23:07:19.543485 == TX Byte 0 ==
5204 23:07:19.550670 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5205 23:07:19.553205 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5206 23:07:19.553287 == TX Byte 1 ==
5207 23:07:19.560335 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5208 23:07:19.563460 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5209 23:07:19.563541
5210 23:07:19.563605 [DATLAT]
5211 23:07:19.566715 Freq=933, CH0 RK1
5212 23:07:19.566796
5213 23:07:19.566860 DATLAT Default: 0xb
5214 23:07:19.570293 0, 0xFFFF, sum = 0
5215 23:07:19.570376 1, 0xFFFF, sum = 0
5216 23:07:19.573880 2, 0xFFFF, sum = 0
5217 23:07:19.573962 3, 0xFFFF, sum = 0
5218 23:07:19.576938 4, 0xFFFF, sum = 0
5219 23:07:19.577020 5, 0xFFFF, sum = 0
5220 23:07:19.579751 6, 0xFFFF, sum = 0
5221 23:07:19.583209 7, 0xFFFF, sum = 0
5222 23:07:19.583292 8, 0xFFFF, sum = 0
5223 23:07:19.586371 9, 0xFFFF, sum = 0
5224 23:07:19.586452 10, 0x0, sum = 1
5225 23:07:19.586518 11, 0x0, sum = 2
5226 23:07:19.589822 12, 0x0, sum = 3
5227 23:07:19.589904 13, 0x0, sum = 4
5228 23:07:19.593328 best_step = 11
5229 23:07:19.593409
5230 23:07:19.593473 ==
5231 23:07:19.596435 Dram Type= 6, Freq= 0, CH_0, rank 1
5232 23:07:19.599802 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5233 23:07:19.599884 ==
5234 23:07:19.603270 RX Vref Scan: 0
5235 23:07:19.603352
5236 23:07:19.603415 RX Vref 0 -> 0, step: 1
5237 23:07:19.606209
5238 23:07:19.606290 RX Delay -69 -> 252, step: 4
5239 23:07:19.613801 iDelay=199, Bit 0, Center 94 (3 ~ 186) 184
5240 23:07:19.617310 iDelay=199, Bit 1, Center 98 (3 ~ 194) 192
5241 23:07:19.620280 iDelay=199, Bit 2, Center 96 (7 ~ 186) 180
5242 23:07:19.626278 iDelay=199, Bit 3, Center 92 (3 ~ 182) 180
5243 23:07:19.627057 iDelay=199, Bit 4, Center 102 (11 ~ 194) 184
5244 23:07:19.630271 iDelay=199, Bit 5, Center 88 (-5 ~ 182) 188
5245 23:07:19.636727 iDelay=199, Bit 6, Center 104 (15 ~ 194) 180
5246 23:07:19.640338 iDelay=199, Bit 7, Center 106 (15 ~ 198) 184
5247 23:07:19.643485 iDelay=199, Bit 8, Center 76 (-9 ~ 162) 172
5248 23:07:19.646959 iDelay=199, Bit 9, Center 72 (-13 ~ 158) 172
5249 23:07:19.650058 iDelay=199, Bit 10, Center 88 (-5 ~ 182) 188
5250 23:07:19.656755 iDelay=199, Bit 11, Center 78 (-5 ~ 162) 168
5251 23:07:19.660046 iDelay=199, Bit 12, Center 92 (7 ~ 178) 172
5252 23:07:19.663145 iDelay=199, Bit 13, Center 90 (-1 ~ 182) 184
5253 23:07:19.666709 iDelay=199, Bit 14, Center 98 (11 ~ 186) 176
5254 23:07:19.669844 iDelay=199, Bit 15, Center 94 (7 ~ 182) 176
5255 23:07:19.669925 ==
5256 23:07:19.673175 Dram Type= 6, Freq= 0, CH_0, rank 1
5257 23:07:19.680179 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5258 23:07:19.680261 ==
5259 23:07:19.680326 DQS Delay:
5260 23:07:19.683333 DQS0 = 0, DQS1 = 0
5261 23:07:19.683414 DQM Delay:
5262 23:07:19.686662 DQM0 = 97, DQM1 = 86
5263 23:07:19.686743 DQ Delay:
5264 23:07:19.689780 DQ0 =94, DQ1 =98, DQ2 =96, DQ3 =92
5265 23:07:19.693270 DQ4 =102, DQ5 =88, DQ6 =104, DQ7 =106
5266 23:07:19.696236 DQ8 =76, DQ9 =72, DQ10 =88, DQ11 =78
5267 23:07:19.699724 DQ12 =92, DQ13 =90, DQ14 =98, DQ15 =94
5268 23:07:19.699806
5269 23:07:19.699870
5270 23:07:19.706245 [DQSOSCAuto] RK1, (LSB)MR18= 0x2f2f, (MSB)MR19= 0x505, tDQSOscB0 = 407 ps tDQSOscB1 = 407 ps
5271 23:07:19.709627 CH0 RK1: MR19=505, MR18=2F2F
5272 23:07:19.716386 CH0_RK1: MR19=0x505, MR18=0x2F2F, DQSOSC=407, MR23=63, INC=65, DEC=43
5273 23:07:19.719442 [RxdqsGatingPostProcess] freq 933
5274 23:07:19.725943 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5275 23:07:19.726025 Pre-setting of DQS Precalculation
5276 23:07:19.732903 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5277 23:07:19.732985 ==
5278 23:07:19.736568 Dram Type= 6, Freq= 0, CH_1, rank 0
5279 23:07:19.739555 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5280 23:07:19.739637 ==
5281 23:07:19.746149 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5282 23:07:19.752628 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5283 23:07:19.755855 [CA 0] Center 37 (7~68) winsize 62
5284 23:07:19.759505 [CA 1] Center 37 (6~68) winsize 63
5285 23:07:19.762620 [CA 2] Center 34 (4~65) winsize 62
5286 23:07:19.765940 [CA 3] Center 34 (4~65) winsize 62
5287 23:07:19.769447 [CA 4] Center 33 (2~64) winsize 63
5288 23:07:19.772663 [CA 5] Center 33 (2~64) winsize 63
5289 23:07:19.772783
5290 23:07:19.776019 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5291 23:07:19.776101
5292 23:07:19.779321 [CATrainingPosCal] consider 1 rank data
5293 23:07:19.782442 u2DelayCellTimex100 = 270/100 ps
5294 23:07:19.786190 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5295 23:07:19.789245 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5296 23:07:19.792347 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5297 23:07:19.795950 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5298 23:07:19.799178 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
5299 23:07:19.802374 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
5300 23:07:19.802455
5301 23:07:19.809079 CA PerBit enable=1, Macro0, CA PI delay=33
5302 23:07:19.809159
5303 23:07:19.812391 [CBTSetCACLKResult] CA Dly = 33
5304 23:07:19.812472 CS Dly: 5 (0~36)
5305 23:07:19.812535 ==
5306 23:07:19.815817 Dram Type= 6, Freq= 0, CH_1, rank 1
5307 23:07:19.818919 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5308 23:07:19.819000 ==
5309 23:07:19.825855 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5310 23:07:19.832763 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5311 23:07:19.835593 [CA 0] Center 37 (6~68) winsize 63
5312 23:07:19.839222 [CA 1] Center 37 (6~68) winsize 63
5313 23:07:19.842168 [CA 2] Center 34 (4~65) winsize 62
5314 23:07:19.845600 [CA 3] Center 34 (4~64) winsize 61
5315 23:07:19.849046 [CA 4] Center 33 (2~64) winsize 63
5316 23:07:19.852120 [CA 5] Center 33 (2~64) winsize 63
5317 23:07:19.852200
5318 23:07:19.855484 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5319 23:07:19.855564
5320 23:07:19.859184 [CATrainingPosCal] consider 2 rank data
5321 23:07:19.862123 u2DelayCellTimex100 = 270/100 ps
5322 23:07:19.865396 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5323 23:07:19.868710 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5324 23:07:19.872380 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5325 23:07:19.875327 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5326 23:07:19.878625 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
5327 23:07:19.885224 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
5328 23:07:19.885337
5329 23:07:19.888656 CA PerBit enable=1, Macro0, CA PI delay=33
5330 23:07:19.888774
5331 23:07:19.892190 [CBTSetCACLKResult] CA Dly = 33
5332 23:07:19.892272 CS Dly: 5 (0~37)
5333 23:07:19.892337
5334 23:07:19.895200 ----->DramcWriteLeveling(PI) begin...
5335 23:07:19.895284 ==
5336 23:07:19.898797 Dram Type= 6, Freq= 0, CH_1, rank 0
5337 23:07:19.904958 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5338 23:07:19.905048 ==
5339 23:07:19.908284 Write leveling (Byte 0): 23 => 23
5340 23:07:19.908379 Write leveling (Byte 1): 23 => 23
5341 23:07:19.911661 DramcWriteLeveling(PI) end<-----
5342 23:07:19.911758
5343 23:07:19.911843 ==
5344 23:07:19.915280 Dram Type= 6, Freq= 0, CH_1, rank 0
5345 23:07:19.921673 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5346 23:07:19.921786 ==
5347 23:07:19.924996 [Gating] SW mode calibration
5348 23:07:19.931655 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5349 23:07:19.934866 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5350 23:07:19.941555 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5351 23:07:19.945010 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5352 23:07:19.948159 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5353 23:07:19.954968 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5354 23:07:19.957951 0 10 16 | B1->B0 | 3434 3030 | 1 0 | (1 1) (1 1)
5355 23:07:19.961152 0 10 20 | B1->B0 | 3434 2323 | 0 0 | (0 1) (0 0)
5356 23:07:19.968054 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5357 23:07:19.971384 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5358 23:07:19.974619 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5359 23:07:19.981648 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5360 23:07:19.984804 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5361 23:07:19.987854 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5362 23:07:19.994668 0 11 16 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
5363 23:07:19.997952 0 11 20 | B1->B0 | 2525 4343 | 1 0 | (0 0) (0 0)
5364 23:07:20.001379 0 11 24 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
5365 23:07:20.007902 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5366 23:07:20.010978 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5367 23:07:20.014495 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5368 23:07:20.021286 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5369 23:07:20.024462 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5370 23:07:20.027963 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5371 23:07:20.030872 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5372 23:07:20.037576 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5373 23:07:20.041015 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5374 23:07:20.047544 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5375 23:07:20.050909 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5376 23:07:20.054004 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5377 23:07:20.057146 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5378 23:07:20.063776 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5379 23:07:20.067474 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5380 23:07:20.070510 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5381 23:07:20.077148 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5382 23:07:20.080619 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5383 23:07:20.083931 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5384 23:07:20.091052 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5385 23:07:20.093653 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5386 23:07:20.097116 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5387 23:07:20.103559 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5388 23:07:20.107099 Total UI for P1: 0, mck2ui 16
5389 23:07:20.110285 best dqsien dly found for B0: ( 0, 14, 16)
5390 23:07:20.110383 Total UI for P1: 0, mck2ui 16
5391 23:07:20.117148 best dqsien dly found for B1: ( 0, 14, 16)
5392 23:07:20.120404 best DQS0 dly(MCK, UI, PI) = (0, 14, 16)
5393 23:07:20.123601 best DQS1 dly(MCK, UI, PI) = (0, 14, 16)
5394 23:07:20.123696
5395 23:07:20.127018 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 16)
5396 23:07:20.130494 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 16)
5397 23:07:20.133499 [Gating] SW calibration Done
5398 23:07:20.133594 ==
5399 23:07:20.136885 Dram Type= 6, Freq= 0, CH_1, rank 0
5400 23:07:20.140391 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5401 23:07:20.140488 ==
5402 23:07:20.143471 RX Vref Scan: 0
5403 23:07:20.143564
5404 23:07:20.146523 RX Vref 0 -> 0, step: 1
5405 23:07:20.146615
5406 23:07:20.146706 RX Delay -80 -> 252, step: 8
5407 23:07:20.153527 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5408 23:07:20.156864 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5409 23:07:20.159974 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5410 23:07:20.163308 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5411 23:07:20.166642 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5412 23:07:20.169790 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5413 23:07:20.176745 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5414 23:07:20.179873 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5415 23:07:20.182994 iDelay=208, Bit 8, Center 75 (-16 ~ 167) 184
5416 23:07:20.186441 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5417 23:07:20.189800 iDelay=208, Bit 10, Center 87 (-16 ~ 191) 208
5418 23:07:20.196523 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5419 23:07:20.199745 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5420 23:07:20.202758 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5421 23:07:20.206208 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5422 23:07:20.209680 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5423 23:07:20.212691 ==
5424 23:07:20.212817 Dram Type= 6, Freq= 0, CH_1, rank 0
5425 23:07:20.219473 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5426 23:07:20.219573 ==
5427 23:07:20.219663 DQS Delay:
5428 23:07:20.222620 DQS0 = 0, DQS1 = 0
5429 23:07:20.222724 DQM Delay:
5430 23:07:20.226215 DQM0 = 94, DQM1 = 88
5431 23:07:20.226290 DQ Delay:
5432 23:07:20.229828 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5433 23:07:20.232564 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91
5434 23:07:20.236079 DQ8 =75, DQ9 =79, DQ10 =87, DQ11 =79
5435 23:07:20.239680 DQ12 =95, DQ13 =99, DQ14 =91, DQ15 =99
5436 23:07:20.239779
5437 23:07:20.239877
5438 23:07:20.239965 ==
5439 23:07:20.242617 Dram Type= 6, Freq= 0, CH_1, rank 0
5440 23:07:20.246033 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5441 23:07:20.246140 ==
5442 23:07:20.246230
5443 23:07:20.246325
5444 23:07:20.249112 TX Vref Scan disable
5445 23:07:20.252630 == TX Byte 0 ==
5446 23:07:20.255870 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5447 23:07:20.259226 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5448 23:07:20.262500 == TX Byte 1 ==
5449 23:07:20.265612 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5450 23:07:20.269323 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5451 23:07:20.269398 ==
5452 23:07:20.272359 Dram Type= 6, Freq= 0, CH_1, rank 0
5453 23:07:20.278891 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5454 23:07:20.279000 ==
5455 23:07:20.279090
5456 23:07:20.279181
5457 23:07:20.279274 TX Vref Scan disable
5458 23:07:20.282972 == TX Byte 0 ==
5459 23:07:20.286447 Update DQ dly =705 (2 ,5, 33) DQ OEN =(2 ,2)
5460 23:07:20.292567 Update DQM dly =705 (2 ,5, 33) DQM OEN =(2 ,2)
5461 23:07:20.292667 == TX Byte 1 ==
5462 23:07:20.296064 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5463 23:07:20.302731 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5464 23:07:20.302819
5465 23:07:20.302883 [DATLAT]
5466 23:07:20.302944 Freq=933, CH1 RK0
5467 23:07:20.303002
5468 23:07:20.306143 DATLAT Default: 0xd
5469 23:07:20.306224 0, 0xFFFF, sum = 0
5470 23:07:20.309211 1, 0xFFFF, sum = 0
5471 23:07:20.312611 2, 0xFFFF, sum = 0
5472 23:07:20.312745 3, 0xFFFF, sum = 0
5473 23:07:20.315926 4, 0xFFFF, sum = 0
5474 23:07:20.316009 5, 0xFFFF, sum = 0
5475 23:07:20.319251 6, 0xFFFF, sum = 0
5476 23:07:20.319333 7, 0xFFFF, sum = 0
5477 23:07:20.322531 8, 0xFFFF, sum = 0
5478 23:07:20.322613 9, 0xFFFF, sum = 0
5479 23:07:20.325854 10, 0x0, sum = 1
5480 23:07:20.325936 11, 0x0, sum = 2
5481 23:07:20.329113 12, 0x0, sum = 3
5482 23:07:20.329195 13, 0x0, sum = 4
5483 23:07:20.329261 best_step = 11
5484 23:07:20.329320
5485 23:07:20.332546 ==
5486 23:07:20.335874 Dram Type= 6, Freq= 0, CH_1, rank 0
5487 23:07:20.339021 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5488 23:07:20.339126 ==
5489 23:07:20.339222 RX Vref Scan: 1
5490 23:07:20.339310
5491 23:07:20.342569 RX Vref 0 -> 0, step: 1
5492 23:07:20.342670
5493 23:07:20.345702 RX Delay -61 -> 252, step: 4
5494 23:07:20.345798
5495 23:07:20.349107 Set Vref, RX VrefLevel [Byte0]: 51
5496 23:07:20.352439 [Byte1]: 50
5497 23:07:20.352531
5498 23:07:20.355763 Final RX Vref Byte 0 = 51 to rank0
5499 23:07:20.359143 Final RX Vref Byte 1 = 50 to rank0
5500 23:07:20.362220 Final RX Vref Byte 0 = 51 to rank1
5501 23:07:20.365653 Final RX Vref Byte 1 = 50 to rank1==
5502 23:07:20.368806 Dram Type= 6, Freq= 0, CH_1, rank 0
5503 23:07:20.372327 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5504 23:07:20.375566 ==
5505 23:07:20.375666 DQS Delay:
5506 23:07:20.375756 DQS0 = 0, DQS1 = 0
5507 23:07:20.378673 DQM Delay:
5508 23:07:20.378765 DQM0 = 93, DQM1 = 88
5509 23:07:20.381965 DQ Delay:
5510 23:07:20.385591 DQ0 =96, DQ1 =86, DQ2 =86, DQ3 =90
5511 23:07:20.385694 DQ4 =94, DQ5 =104, DQ6 =100, DQ7 =92
5512 23:07:20.388606 DQ8 =72, DQ9 =78, DQ10 =90, DQ11 =80
5513 23:07:20.395429 DQ12 =94, DQ13 =98, DQ14 =96, DQ15 =98
5514 23:07:20.395529
5515 23:07:20.395618
5516 23:07:20.402001 [DQSOSCAuto] RK0, (LSB)MR18= 0x3434, (MSB)MR19= 0x505, tDQSOscB0 = 405 ps tDQSOscB1 = 405 ps
5517 23:07:20.405277 CH1 RK0: MR19=505, MR18=3434
5518 23:07:20.412216 CH1_RK0: MR19=0x505, MR18=0x3434, DQSOSC=405, MR23=63, INC=66, DEC=44
5519 23:07:20.412315
5520 23:07:20.414924 ----->DramcWriteLeveling(PI) begin...
5521 23:07:20.415022 ==
5522 23:07:20.418502 Dram Type= 6, Freq= 0, CH_1, rank 1
5523 23:07:20.422148 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5524 23:07:20.422247 ==
5525 23:07:20.424896 Write leveling (Byte 0): 25 => 25
5526 23:07:20.428595 Write leveling (Byte 1): 24 => 24
5527 23:07:20.431662 DramcWriteLeveling(PI) end<-----
5528 23:07:20.431762
5529 23:07:20.431855 ==
5530 23:07:20.434855 Dram Type= 6, Freq= 0, CH_1, rank 1
5531 23:07:20.438476 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5532 23:07:20.438574 ==
5533 23:07:20.441573 [Gating] SW mode calibration
5534 23:07:20.448416 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5535 23:07:20.454782 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5536 23:07:20.457984 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5537 23:07:20.464597 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5538 23:07:20.467921 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5539 23:07:20.471659 0 10 12 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 1)
5540 23:07:20.478496 0 10 16 | B1->B0 | 3434 2727 | 1 0 | (1 1) (0 0)
5541 23:07:20.481360 0 10 20 | B1->B0 | 2e2e 2323 | 0 0 | (0 0) (0 0)
5542 23:07:20.484520 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5543 23:07:20.491239 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5544 23:07:20.494629 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5545 23:07:20.497772 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5546 23:07:20.504536 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5547 23:07:20.507722 0 11 12 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (1 1)
5548 23:07:20.511063 0 11 16 | B1->B0 | 2525 4242 | 0 0 | (0 0) (0 0)
5549 23:07:20.517831 0 11 20 | B1->B0 | 2f2f 4646 | 0 0 | (0 0) (0 0)
5550 23:07:20.521117 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5551 23:07:20.524540 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5552 23:07:20.527693 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5553 23:07:20.534203 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5554 23:07:20.537365 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5555 23:07:20.541317 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5556 23:07:20.547325 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5557 23:07:20.550650 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5558 23:07:20.554416 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5559 23:07:20.560698 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5560 23:07:20.564425 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5561 23:07:20.567325 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5562 23:07:20.573816 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5563 23:07:20.577347 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5564 23:07:20.580699 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5565 23:07:20.587284 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5566 23:07:20.590441 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5567 23:07:20.593880 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5568 23:07:20.600601 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5569 23:07:20.603540 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5570 23:07:20.606930 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5571 23:07:20.613670 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5572 23:07:20.616826 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5573 23:07:20.619976 Total UI for P1: 0, mck2ui 16
5574 23:07:20.623512 best dqsien dly found for B0: ( 0, 14, 14)
5575 23:07:20.626883 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5576 23:07:20.634022 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5577 23:07:20.634146 Total UI for P1: 0, mck2ui 16
5578 23:07:20.640497 best dqsien dly found for B1: ( 0, 14, 18)
5579 23:07:20.643549 best DQS0 dly(MCK, UI, PI) = (0, 14, 14)
5580 23:07:20.646503 best DQS1 dly(MCK, UI, PI) = (0, 14, 18)
5581 23:07:20.646602
5582 23:07:20.649915 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 14)
5583 23:07:20.653726 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 18)
5584 23:07:20.656514 [Gating] SW calibration Done
5585 23:07:20.656612 ==
5586 23:07:20.659757 Dram Type= 6, Freq= 0, CH_1, rank 1
5587 23:07:20.663186 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5588 23:07:20.663286 ==
5589 23:07:20.666619 RX Vref Scan: 0
5590 23:07:20.666717
5591 23:07:20.669680 RX Vref 0 -> 0, step: 1
5592 23:07:20.669747
5593 23:07:20.669808 RX Delay -80 -> 252, step: 8
5594 23:07:20.676589 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5595 23:07:20.679447 iDelay=208, Bit 1, Center 87 (-8 ~ 183) 192
5596 23:07:20.682957 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5597 23:07:20.686315 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5598 23:07:20.689452 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5599 23:07:20.692753 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5600 23:07:20.699490 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5601 23:07:20.703041 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5602 23:07:20.706193 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5603 23:07:20.709402 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5604 23:07:20.712780 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5605 23:07:20.719820 iDelay=208, Bit 11, Center 79 (-24 ~ 183) 208
5606 23:07:20.722798 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5607 23:07:20.726252 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5608 23:07:20.729638 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5609 23:07:20.732627 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5610 23:07:20.732763 ==
5611 23:07:20.735917 Dram Type= 6, Freq= 0, CH_1, rank 1
5612 23:07:20.742713 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5613 23:07:20.742816 ==
5614 23:07:20.742912 DQS Delay:
5615 23:07:20.743000 DQS0 = 0, DQS1 = 0
5616 23:07:20.746021 DQM Delay:
5617 23:07:20.746118 DQM0 = 94, DQM1 = 88
5618 23:07:20.749376 DQ Delay:
5619 23:07:20.753003 DQ0 =95, DQ1 =87, DQ2 =87, DQ3 =91
5620 23:07:20.756052 DQ4 =95, DQ5 =107, DQ6 =103, DQ7 =91
5621 23:07:20.759433 DQ8 =75, DQ9 =75, DQ10 =87, DQ11 =79
5622 23:07:20.762513 DQ12 =99, DQ13 =99, DQ14 =95, DQ15 =95
5623 23:07:20.762584
5624 23:07:20.762649
5625 23:07:20.762708 ==
5626 23:07:20.765828 Dram Type= 6, Freq= 0, CH_1, rank 1
5627 23:07:20.769199 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5628 23:07:20.769297 ==
5629 23:07:20.769389
5630 23:07:20.769477
5631 23:07:20.772362 TX Vref Scan disable
5632 23:07:20.772454 == TX Byte 0 ==
5633 23:07:20.779340 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5634 23:07:20.783125 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5635 23:07:20.783224 == TX Byte 1 ==
5636 23:07:20.789146 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5637 23:07:20.792337 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5638 23:07:20.792433 ==
5639 23:07:20.795784 Dram Type= 6, Freq= 0, CH_1, rank 1
5640 23:07:20.799188 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5641 23:07:20.799290 ==
5642 23:07:20.799384
5643 23:07:20.799472
5644 23:07:20.802524 TX Vref Scan disable
5645 23:07:20.805759 == TX Byte 0 ==
5646 23:07:20.808824 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5647 23:07:20.812285 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5648 23:07:20.815501 == TX Byte 1 ==
5649 23:07:20.819011 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5650 23:07:20.822347 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5651 23:07:20.822443
5652 23:07:20.825779 [DATLAT]
5653 23:07:20.825846 Freq=933, CH1 RK1
5654 23:07:20.825909
5655 23:07:20.828798 DATLAT Default: 0xb
5656 23:07:20.828863 0, 0xFFFF, sum = 0
5657 23:07:20.832116 1, 0xFFFF, sum = 0
5658 23:07:20.832211 2, 0xFFFF, sum = 0
5659 23:07:20.835550 3, 0xFFFF, sum = 0
5660 23:07:20.835647 4, 0xFFFF, sum = 0
5661 23:07:20.839052 5, 0xFFFF, sum = 0
5662 23:07:20.839148 6, 0xFFFF, sum = 0
5663 23:07:20.842183 7, 0xFFFF, sum = 0
5664 23:07:20.845410 8, 0xFFFF, sum = 0
5665 23:07:20.845485 9, 0xFFFF, sum = 0
5666 23:07:20.848583 10, 0x0, sum = 1
5667 23:07:20.848755 11, 0x0, sum = 2
5668 23:07:20.848818 12, 0x0, sum = 3
5669 23:07:20.852317 13, 0x0, sum = 4
5670 23:07:20.852407 best_step = 11
5671 23:07:20.852472
5672 23:07:20.855149 ==
5673 23:07:20.858921 Dram Type= 6, Freq= 0, CH_1, rank 1
5674 23:07:20.861872 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5675 23:07:20.861954 ==
5676 23:07:20.862018 RX Vref Scan: 0
5677 23:07:20.862078
5678 23:07:20.865344 RX Vref 0 -> 0, step: 1
5679 23:07:20.865425
5680 23:07:20.868480 RX Delay -69 -> 252, step: 4
5681 23:07:20.871882 iDelay=203, Bit 0, Center 96 (7 ~ 186) 180
5682 23:07:20.879142 iDelay=203, Bit 1, Center 90 (-1 ~ 182) 184
5683 23:07:20.881964 iDelay=203, Bit 2, Center 88 (-5 ~ 182) 188
5684 23:07:20.885486 iDelay=203, Bit 3, Center 92 (-1 ~ 186) 188
5685 23:07:20.888500 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5686 23:07:20.891978 iDelay=203, Bit 5, Center 106 (11 ~ 202) 192
5687 23:07:20.895218 iDelay=203, Bit 6, Center 104 (11 ~ 198) 188
5688 23:07:20.901951 iDelay=203, Bit 7, Center 94 (3 ~ 186) 184
5689 23:07:20.905265 iDelay=203, Bit 8, Center 74 (-17 ~ 166) 184
5690 23:07:20.908492 iDelay=203, Bit 9, Center 76 (-17 ~ 170) 188
5691 23:07:20.911747 iDelay=203, Bit 10, Center 88 (-5 ~ 182) 188
5692 23:07:20.914976 iDelay=203, Bit 11, Center 80 (-13 ~ 174) 188
5693 23:07:20.921626 iDelay=203, Bit 12, Center 96 (3 ~ 190) 188
5694 23:07:20.925062 iDelay=203, Bit 13, Center 96 (7 ~ 186) 180
5695 23:07:20.928425 iDelay=203, Bit 14, Center 96 (-1 ~ 194) 196
5696 23:07:20.931726 iDelay=203, Bit 15, Center 96 (7 ~ 186) 180
5697 23:07:20.931807 ==
5698 23:07:20.935116 Dram Type= 6, Freq= 0, CH_1, rank 1
5699 23:07:20.938592 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5700 23:07:20.938674 ==
5701 23:07:20.941785 DQS Delay:
5702 23:07:20.941866 DQS0 = 0, DQS1 = 0
5703 23:07:20.944904 DQM Delay:
5704 23:07:20.944985 DQM0 = 95, DQM1 = 87
5705 23:07:20.945050 DQ Delay:
5706 23:07:20.948248 DQ0 =96, DQ1 =90, DQ2 =88, DQ3 =92
5707 23:07:20.951906 DQ4 =96, DQ5 =106, DQ6 =104, DQ7 =94
5708 23:07:20.955023 DQ8 =74, DQ9 =76, DQ10 =88, DQ11 =80
5709 23:07:20.958281 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
5710 23:07:20.958361
5711 23:07:20.961548
5712 23:07:20.968275 [DQSOSCAuto] RK1, (LSB)MR18= 0x2525, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 410 ps
5713 23:07:20.971695 CH1 RK1: MR19=505, MR18=2525
5714 23:07:20.978339 CH1_RK1: MR19=0x505, MR18=0x2525, DQSOSC=410, MR23=63, INC=64, DEC=42
5715 23:07:20.981374 [RxdqsGatingPostProcess] freq 933
5716 23:07:20.984780 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5717 23:07:20.988175 Pre-setting of DQS Precalculation
5718 23:07:20.994791 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5719 23:07:21.001172 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5720 23:07:21.007929 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5721 23:07:21.008030
5722 23:07:21.008125
5723 23:07:21.011335 [Calibration Summary] 1866 Mbps
5724 23:07:21.011434 CH 0, Rank 0
5725 23:07:21.014377 SW Impedance : PASS
5726 23:07:21.017833 DUTY Scan : NO K
5727 23:07:21.017931 ZQ Calibration : PASS
5728 23:07:21.021156 Jitter Meter : NO K
5729 23:07:21.024308 CBT Training : PASS
5730 23:07:21.024403 Write leveling : PASS
5731 23:07:21.028478 RX DQS gating : PASS
5732 23:07:21.030946 RX DQ/DQS(RDDQC) : PASS
5733 23:07:21.031040 TX DQ/DQS : PASS
5734 23:07:21.034375 RX DATLAT : PASS
5735 23:07:21.034470 RX DQ/DQS(Engine): PASS
5736 23:07:21.037565 TX OE : NO K
5737 23:07:21.037660 All Pass.
5738 23:07:21.037747
5739 23:07:21.041037 CH 0, Rank 1
5740 23:07:21.041134 SW Impedance : PASS
5741 23:07:21.044668 DUTY Scan : NO K
5742 23:07:21.048177 ZQ Calibration : PASS
5743 23:07:21.048272 Jitter Meter : NO K
5744 23:07:21.050843 CBT Training : PASS
5745 23:07:21.054185 Write leveling : PASS
5746 23:07:21.054280 RX DQS gating : PASS
5747 23:07:21.057678 RX DQ/DQS(RDDQC) : PASS
5748 23:07:21.060905 TX DQ/DQS : PASS
5749 23:07:21.060999 RX DATLAT : PASS
5750 23:07:21.064222 RX DQ/DQS(Engine): PASS
5751 23:07:21.067445 TX OE : NO K
5752 23:07:21.067543 All Pass.
5753 23:07:21.067632
5754 23:07:21.067716 CH 1, Rank 0
5755 23:07:21.070700 SW Impedance : PASS
5756 23:07:21.074233 DUTY Scan : NO K
5757 23:07:21.074328 ZQ Calibration : PASS
5758 23:07:21.077583 Jitter Meter : NO K
5759 23:07:21.080946 CBT Training : PASS
5760 23:07:21.081042 Write leveling : PASS
5761 23:07:21.084487 RX DQS gating : PASS
5762 23:07:21.084589 RX DQ/DQS(RDDQC) : PASS
5763 23:07:21.087514 TX DQ/DQS : PASS
5764 23:07:21.090788 RX DATLAT : PASS
5765 23:07:21.090892 RX DQ/DQS(Engine): PASS
5766 23:07:21.094257 TX OE : NO K
5767 23:07:21.094360 All Pass.
5768 23:07:21.094450
5769 23:07:21.097175 CH 1, Rank 1
5770 23:07:21.097277 SW Impedance : PASS
5771 23:07:21.100633 DUTY Scan : NO K
5772 23:07:21.103889 ZQ Calibration : PASS
5773 23:07:21.103993 Jitter Meter : NO K
5774 23:07:21.107479 CBT Training : PASS
5775 23:07:21.110572 Write leveling : PASS
5776 23:07:21.110672 RX DQS gating : PASS
5777 23:07:21.113738 RX DQ/DQS(RDDQC) : PASS
5778 23:07:21.117050 TX DQ/DQS : PASS
5779 23:07:21.117150 RX DATLAT : PASS
5780 23:07:21.120504 RX DQ/DQS(Engine): PASS
5781 23:07:21.124070 TX OE : NO K
5782 23:07:21.124172 All Pass.
5783 23:07:21.124265
5784 23:07:21.126959 DramC Write-DBI off
5785 23:07:21.127059 PER_BANK_REFRESH: Hybrid Mode
5786 23:07:21.130305 TX_TRACKING: ON
5787 23:07:21.137236 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
5788 23:07:21.143747 [FAST_K] Save calibration result to emmc
5789 23:07:21.147162 dramc_set_vcore_voltage set vcore to 650000
5790 23:07:21.147264 Read voltage for 400, 6
5791 23:07:21.150165 Vio18 = 0
5792 23:07:21.150266 Vcore = 650000
5793 23:07:21.150354 Vdram = 0
5794 23:07:21.153563 Vddq = 0
5795 23:07:21.153656 Vmddr = 0
5796 23:07:21.157076 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
5797 23:07:21.163537 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
5798 23:07:21.166658 MEM_TYPE=3, freq_sel=20
5799 23:07:21.170419 sv_algorithm_assistance_LP4_800
5800 23:07:21.173373 ============ PULL DRAM RESETB DOWN ============
5801 23:07:21.176619 ========== PULL DRAM RESETB DOWN end =========
5802 23:07:21.183242 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5803 23:07:21.183346 ===================================
5804 23:07:21.186626 LPDDR4 DRAM CONFIGURATION
5805 23:07:21.190138 ===================================
5806 23:07:21.193406 EX_ROW_EN[0] = 0x0
5807 23:07:21.193502 EX_ROW_EN[1] = 0x0
5808 23:07:21.196457 LP4Y_EN = 0x0
5809 23:07:21.196556 WORK_FSP = 0x0
5810 23:07:21.200070 WL = 0x2
5811 23:07:21.200173 RL = 0x2
5812 23:07:21.203597 BL = 0x2
5813 23:07:21.203698 RPST = 0x0
5814 23:07:21.206625 RD_PRE = 0x0
5815 23:07:21.210247 WR_PRE = 0x1
5816 23:07:21.210346 WR_PST = 0x0
5817 23:07:21.213041 DBI_WR = 0x0
5818 23:07:21.213139 DBI_RD = 0x0
5819 23:07:21.216802 OTF = 0x1
5820 23:07:21.219897 ===================================
5821 23:07:21.223199 ===================================
5822 23:07:21.223296 ANA top config
5823 23:07:21.226361 ===================================
5824 23:07:21.229956 DLL_ASYNC_EN = 0
5825 23:07:21.233033 ALL_SLAVE_EN = 1
5826 23:07:21.233134 NEW_RANK_MODE = 1
5827 23:07:21.236583 DLL_IDLE_MODE = 1
5828 23:07:21.239591 LP45_APHY_COMB_EN = 1
5829 23:07:21.243148 TX_ODT_DIS = 1
5830 23:07:21.243244 NEW_8X_MODE = 1
5831 23:07:21.245999 ===================================
5832 23:07:21.249468 ===================================
5833 23:07:21.252665 data_rate = 800
5834 23:07:21.255990 CKR = 1
5835 23:07:21.259303 DQ_P2S_RATIO = 4
5836 23:07:21.262994 ===================================
5837 23:07:21.265799 CA_P2S_RATIO = 4
5838 23:07:21.269297 DQ_CA_OPEN = 0
5839 23:07:21.272670 DQ_SEMI_OPEN = 1
5840 23:07:21.272788 CA_SEMI_OPEN = 1
5841 23:07:21.276117 CA_FULL_RATE = 0
5842 23:07:21.279215 DQ_CKDIV4_EN = 0
5843 23:07:21.282645 CA_CKDIV4_EN = 1
5844 23:07:21.285781 CA_PREDIV_EN = 0
5845 23:07:21.289122 PH8_DLY = 0
5846 23:07:21.289210 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
5847 23:07:21.292622 DQ_AAMCK_DIV = 0
5848 23:07:21.295922 CA_AAMCK_DIV = 0
5849 23:07:21.299081 CA_ADMCK_DIV = 4
5850 23:07:21.302804 DQ_TRACK_CA_EN = 0
5851 23:07:21.305590 CA_PICK = 800
5852 23:07:21.305672 CA_MCKIO = 400
5853 23:07:21.309433 MCKIO_SEMI = 400
5854 23:07:21.312636 PLL_FREQ = 3016
5855 23:07:21.315772 DQ_UI_PI_RATIO = 32
5856 23:07:21.319105 CA_UI_PI_RATIO = 32
5857 23:07:21.322599 ===================================
5858 23:07:21.325644 ===================================
5859 23:07:21.329083 memory_type:LPDDR4
5860 23:07:21.329164 GP_NUM : 10
5861 23:07:21.332239 SRAM_EN : 1
5862 23:07:21.335653 MD32_EN : 0
5863 23:07:21.338890 ===================================
5864 23:07:21.338971 [ANA_INIT] >>>>>>>>>>>>>>
5865 23:07:21.342366 <<<<<< [CONFIGURE PHASE]: ANA_TX
5866 23:07:21.345676 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5867 23:07:21.349101 ===================================
5868 23:07:21.352110 data_rate = 800,PCW = 0X7400
5869 23:07:21.355657 ===================================
5870 23:07:21.359153 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5871 23:07:21.365605 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5872 23:07:21.375389 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5873 23:07:21.378692 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5874 23:07:21.385272 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5875 23:07:21.388481 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5876 23:07:21.388563 [ANA_INIT] flow start
5877 23:07:21.391842 [ANA_INIT] PLL >>>>>>>>
5878 23:07:21.395151 [ANA_INIT] PLL <<<<<<<<
5879 23:07:21.395232 [ANA_INIT] MIDPI >>>>>>>>
5880 23:07:21.398328 [ANA_INIT] MIDPI <<<<<<<<
5881 23:07:21.401862 [ANA_INIT] DLL >>>>>>>>
5882 23:07:21.401943 [ANA_INIT] flow end
5883 23:07:21.408373 ============ LP4 DIFF to SE enter ============
5884 23:07:21.412158 ============ LP4 DIFF to SE exit ============
5885 23:07:21.412240 [ANA_INIT] <<<<<<<<<<<<<
5886 23:07:21.414783 [Flow] Enable top DCM control >>>>>
5887 23:07:21.418634 [Flow] Enable top DCM control <<<<<
5888 23:07:21.421679 Enable DLL master slave shuffle
5889 23:07:21.428103 ==============================================================
5890 23:07:21.431632 Gating Mode config
5891 23:07:21.435028 ==============================================================
5892 23:07:21.438193 Config description:
5893 23:07:21.447892 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5894 23:07:21.454415 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5895 23:07:21.457820 SELPH_MODE 0: By rank 1: By Phase
5896 23:07:21.465069 ==============================================================
5897 23:07:21.468074 GAT_TRACK_EN = 0
5898 23:07:21.471462 RX_GATING_MODE = 2
5899 23:07:21.474531 RX_GATING_TRACK_MODE = 2
5900 23:07:21.474627 SELPH_MODE = 1
5901 23:07:21.477726 PICG_EARLY_EN = 1
5902 23:07:21.481198 VALID_LAT_VALUE = 1
5903 23:07:21.487728 ==============================================================
5904 23:07:21.491217 Enter into Gating configuration >>>>
5905 23:07:21.494442 Exit from Gating configuration <<<<
5906 23:07:21.497799 Enter into DVFS_PRE_config >>>>>
5907 23:07:21.507565 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5908 23:07:21.510900 Exit from DVFS_PRE_config <<<<<
5909 23:07:21.514249 Enter into PICG configuration >>>>
5910 23:07:21.517897 Exit from PICG configuration <<<<
5911 23:07:21.520863 [RX_INPUT] configuration >>>>>
5912 23:07:21.524127 [RX_INPUT] configuration <<<<<
5913 23:07:21.527519 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5914 23:07:21.533913 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5915 23:07:21.540521 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5916 23:07:21.547359 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5917 23:07:21.554130 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5918 23:07:21.557352 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5919 23:07:21.563918 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5920 23:07:21.567238 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5921 23:07:21.570237 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5922 23:07:21.573594 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5923 23:07:21.580242 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5924 23:07:21.583612 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5925 23:07:21.586960 ===================================
5926 23:07:21.590541 LPDDR4 DRAM CONFIGURATION
5927 23:07:21.593932 ===================================
5928 23:07:21.594031 EX_ROW_EN[0] = 0x0
5929 23:07:21.596943 EX_ROW_EN[1] = 0x0
5930 23:07:21.597042 LP4Y_EN = 0x0
5931 23:07:21.600340 WORK_FSP = 0x0
5932 23:07:21.600440 WL = 0x2
5933 23:07:21.603350 RL = 0x2
5934 23:07:21.606889 BL = 0x2
5935 23:07:21.606994 RPST = 0x0
5936 23:07:21.610208 RD_PRE = 0x0
5937 23:07:21.610310 WR_PRE = 0x1
5938 23:07:21.613567 WR_PST = 0x0
5939 23:07:21.613666 DBI_WR = 0x0
5940 23:07:21.616538 DBI_RD = 0x0
5941 23:07:21.616636 OTF = 0x1
5942 23:07:21.620036 ===================================
5943 23:07:21.623239 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5944 23:07:21.629850 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5945 23:07:21.633350 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5946 23:07:21.636572 ===================================
5947 23:07:21.640015 LPDDR4 DRAM CONFIGURATION
5948 23:07:21.643372 ===================================
5949 23:07:21.643472 EX_ROW_EN[0] = 0x10
5950 23:07:21.646908 EX_ROW_EN[1] = 0x0
5951 23:07:21.647004 LP4Y_EN = 0x0
5952 23:07:21.649811 WORK_FSP = 0x0
5953 23:07:21.649907 WL = 0x2
5954 23:07:21.653193 RL = 0x2
5955 23:07:21.653271 BL = 0x2
5956 23:07:21.656159 RPST = 0x0
5957 23:07:21.659743 RD_PRE = 0x0
5958 23:07:21.659841 WR_PRE = 0x1
5959 23:07:21.662945 WR_PST = 0x0
5960 23:07:21.663044 DBI_WR = 0x0
5961 23:07:21.666140 DBI_RD = 0x0
5962 23:07:21.666236 OTF = 0x1
5963 23:07:21.669450 ===================================
5964 23:07:21.676255 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5965 23:07:21.679979 nWR fixed to 30
5966 23:07:21.683399 [ModeRegInit_LP4] CH0 RK0
5967 23:07:21.683497 [ModeRegInit_LP4] CH0 RK1
5968 23:07:21.686881 [ModeRegInit_LP4] CH1 RK0
5969 23:07:21.689969 [ModeRegInit_LP4] CH1 RK1
5970 23:07:21.690042 match AC timing 18
5971 23:07:21.696471 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 0
5972 23:07:21.699923 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5973 23:07:21.703092 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
5974 23:07:21.710136 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
5975 23:07:21.712911 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
5976 23:07:21.713015 ==
5977 23:07:21.716291 Dram Type= 6, Freq= 0, CH_0, rank 0
5978 23:07:21.719689 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
5979 23:07:21.719791 ==
5980 23:07:21.726506 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
5981 23:07:21.732940 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5982 23:07:21.736537 [CA 0] Center 36 (8~64) winsize 57
5983 23:07:21.739465 [CA 1] Center 36 (8~64) winsize 57
5984 23:07:21.742901 [CA 2] Center 36 (8~64) winsize 57
5985 23:07:21.746086 [CA 3] Center 36 (8~64) winsize 57
5986 23:07:21.746189 [CA 4] Center 36 (8~64) winsize 57
5987 23:07:21.749567 [CA 5] Center 36 (8~64) winsize 57
5988 23:07:21.749666
5989 23:07:21.756239 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5990 23:07:21.756341
5991 23:07:21.759414 [CATrainingPosCal] consider 1 rank data
5992 23:07:21.762639 u2DelayCellTimex100 = 270/100 ps
5993 23:07:21.766109 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
5994 23:07:21.769498 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
5995 23:07:21.772774 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
5996 23:07:21.775822 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
5997 23:07:21.779446 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
5998 23:07:21.782748 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
5999 23:07:21.782851
6000 23:07:21.785891 CA PerBit enable=1, Macro0, CA PI delay=36
6001 23:07:21.785993
6002 23:07:21.789044 [CBTSetCACLKResult] CA Dly = 36
6003 23:07:21.792483 CS Dly: 1 (0~32)
6004 23:07:21.792586 ==
6005 23:07:21.795778 Dram Type= 6, Freq= 0, CH_0, rank 1
6006 23:07:21.799140 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6007 23:07:21.799241 ==
6008 23:07:21.806101 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6009 23:07:21.812384 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
6010 23:07:21.815765 [CA 0] Center 36 (8~64) winsize 57
6011 23:07:21.815847 [CA 1] Center 36 (8~64) winsize 57
6012 23:07:21.819246 [CA 2] Center 36 (8~64) winsize 57
6013 23:07:21.822248 [CA 3] Center 36 (8~64) winsize 57
6014 23:07:21.825667 [CA 4] Center 36 (8~64) winsize 57
6015 23:07:21.829166 [CA 5] Center 36 (8~64) winsize 57
6016 23:07:21.829248
6017 23:07:21.832346 [CmdBusTrainingLP45] Vref(ca) range 1: 39
6018 23:07:21.832428
6019 23:07:21.838853 [CATrainingPosCal] consider 2 rank data
6020 23:07:21.838934 u2DelayCellTimex100 = 270/100 ps
6021 23:07:21.845564 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6022 23:07:21.848653 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6023 23:07:21.852259 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6024 23:07:21.855497 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6025 23:07:21.858784 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6026 23:07:21.862722 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6027 23:07:21.862804
6028 23:07:21.865480 CA PerBit enable=1, Macro0, CA PI delay=36
6029 23:07:21.865562
6030 23:07:21.868690 [CBTSetCACLKResult] CA Dly = 36
6031 23:07:21.872213 CS Dly: 1 (0~32)
6032 23:07:21.872294
6033 23:07:21.875555 ----->DramcWriteLeveling(PI) begin...
6034 23:07:21.875637 ==
6035 23:07:21.878974 Dram Type= 6, Freq= 0, CH_0, rank 0
6036 23:07:21.881928 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6037 23:07:21.882010 ==
6038 23:07:21.885811 Write leveling (Byte 0): 32 => 0
6039 23:07:21.888653 Write leveling (Byte 1): 32 => 0
6040 23:07:21.892092 DramcWriteLeveling(PI) end<-----
6041 23:07:21.892207
6042 23:07:21.892313 ==
6043 23:07:21.895257 Dram Type= 6, Freq= 0, CH_0, rank 0
6044 23:07:21.898297 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6045 23:07:21.898404 ==
6046 23:07:21.902109 [Gating] SW mode calibration
6047 23:07:21.908919 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6048 23:07:21.915136 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6049 23:07:21.918760 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6050 23:07:21.922306 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6051 23:07:21.928655 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6052 23:07:21.931749 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6053 23:07:21.935112 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6054 23:07:21.941805 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6055 23:07:21.945040 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6056 23:07:21.948169 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
6057 23:07:21.954809 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6058 23:07:21.954890 Total UI for P1: 0, mck2ui 16
6059 23:07:21.958137 best dqsien dly found for B0: ( 0, 10, 16)
6060 23:07:21.961674 Total UI for P1: 0, mck2ui 16
6061 23:07:21.964987 best dqsien dly found for B1: ( 0, 10, 24)
6062 23:07:21.971386 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6063 23:07:21.974819 best DQS1 dly(MCK, UI, PI) = (0, 10, 24)
6064 23:07:21.974900
6065 23:07:21.978113 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6066 23:07:21.981467 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 24)
6067 23:07:21.984603 [Gating] SW calibration Done
6068 23:07:21.984685 ==
6069 23:07:21.987987 Dram Type= 6, Freq= 0, CH_0, rank 0
6070 23:07:21.991641 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6071 23:07:21.991723 ==
6072 23:07:21.994523 RX Vref Scan: 0
6073 23:07:21.994603
6074 23:07:21.994666 RX Vref 0 -> 0, step: 1
6075 23:07:21.994726
6076 23:07:21.998303 RX Delay -410 -> 252, step: 16
6077 23:07:22.004616 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6078 23:07:22.007843 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6079 23:07:22.011280 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6080 23:07:22.014596 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6081 23:07:22.021298 iDelay=230, Bit 4, Center -35 (-298 ~ 229) 528
6082 23:07:22.024404 iDelay=230, Bit 5, Center -51 (-298 ~ 197) 496
6083 23:07:22.027959 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6084 23:07:22.031166 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6085 23:07:22.037614 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6086 23:07:22.041110 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6087 23:07:22.044305 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6088 23:07:22.047718 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6089 23:07:22.054158 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6090 23:07:22.057987 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6091 23:07:22.060819 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6092 23:07:22.064471 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6093 23:07:22.067690 ==
6094 23:07:22.067771 Dram Type= 6, Freq= 0, CH_0, rank 0
6095 23:07:22.074256 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6096 23:07:22.074338 ==
6097 23:07:22.074419 DQS Delay:
6098 23:07:22.077811 DQS0 = 51, DQS1 = 59
6099 23:07:22.077892 DQM Delay:
6100 23:07:22.080988 DQM0 = 12, DQM1 = 13
6101 23:07:22.081069 DQ Delay:
6102 23:07:22.084216 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6103 23:07:22.087655 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6104 23:07:22.091104 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6105 23:07:22.094171 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =24
6106 23:07:22.094252
6107 23:07:22.094328
6108 23:07:22.094394 ==
6109 23:07:22.097382 Dram Type= 6, Freq= 0, CH_0, rank 0
6110 23:07:22.101020 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6111 23:07:22.101102 ==
6112 23:07:22.101166
6113 23:07:22.101226
6114 23:07:22.104383 TX Vref Scan disable
6115 23:07:22.104465 == TX Byte 0 ==
6116 23:07:22.110805 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6117 23:07:22.114212 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6118 23:07:22.114312 == TX Byte 1 ==
6119 23:07:22.120631 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6120 23:07:22.124115 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6121 23:07:22.124214 ==
6122 23:07:22.127386 Dram Type= 6, Freq= 0, CH_0, rank 0
6123 23:07:22.130733 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6124 23:07:22.130831 ==
6125 23:07:22.130920
6126 23:07:22.131005
6127 23:07:22.134074 TX Vref Scan disable
6128 23:07:22.134169 == TX Byte 0 ==
6129 23:07:22.140729 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6130 23:07:22.144186 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6131 23:07:22.144282 == TX Byte 1 ==
6132 23:07:22.150520 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6133 23:07:22.154075 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6134 23:07:22.154161
6135 23:07:22.154230 [DATLAT]
6136 23:07:22.157528 Freq=400, CH0 RK0
6137 23:07:22.157622
6138 23:07:22.157689 DATLAT Default: 0xf
6139 23:07:22.160375 0, 0xFFFF, sum = 0
6140 23:07:22.160472 1, 0xFFFF, sum = 0
6141 23:07:22.163764 2, 0xFFFF, sum = 0
6142 23:07:22.167100 3, 0xFFFF, sum = 0
6143 23:07:22.167197 4, 0xFFFF, sum = 0
6144 23:07:22.170709 5, 0xFFFF, sum = 0
6145 23:07:22.170782 6, 0xFFFF, sum = 0
6146 23:07:22.173835 7, 0xFFFF, sum = 0
6147 23:07:22.173933 8, 0xFFFF, sum = 0
6148 23:07:22.177385 9, 0xFFFF, sum = 0
6149 23:07:22.177461 10, 0xFFFF, sum = 0
6150 23:07:22.180465 11, 0xFFFF, sum = 0
6151 23:07:22.180561 12, 0x0, sum = 1
6152 23:07:22.183522 13, 0x0, sum = 2
6153 23:07:22.183619 14, 0x0, sum = 3
6154 23:07:22.187039 15, 0x0, sum = 4
6155 23:07:22.187140 best_step = 13
6156 23:07:22.187231
6157 23:07:22.187319 ==
6158 23:07:22.190093 Dram Type= 6, Freq= 0, CH_0, rank 0
6159 23:07:22.193619 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6160 23:07:22.196839 ==
6161 23:07:22.196938 RX Vref Scan: 1
6162 23:07:22.197028
6163 23:07:22.200161 RX Vref 0 -> 0, step: 1
6164 23:07:22.200260
6165 23:07:22.200351 RX Delay -359 -> 252, step: 8
6166 23:07:22.203853
6167 23:07:22.203954 Set Vref, RX VrefLevel [Byte0]: 47
6168 23:07:22.206810 [Byte1]: 42
6169 23:07:22.212506
6170 23:07:22.212604 Final RX Vref Byte 0 = 47 to rank0
6171 23:07:22.215759 Final RX Vref Byte 1 = 42 to rank0
6172 23:07:22.219480 Final RX Vref Byte 0 = 47 to rank1
6173 23:07:22.222680 Final RX Vref Byte 1 = 42 to rank1==
6174 23:07:22.226157 Dram Type= 6, Freq= 0, CH_0, rank 0
6175 23:07:22.232803 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6176 23:07:22.232879 ==
6177 23:07:22.232952 DQS Delay:
6178 23:07:22.235901 DQS0 = 52, DQS1 = 68
6179 23:07:22.235996 DQM Delay:
6180 23:07:22.236083 DQM0 = 9, DQM1 = 17
6181 23:07:22.239044 DQ Delay:
6182 23:07:22.242391 DQ0 =4, DQ1 =8, DQ2 =8, DQ3 =4
6183 23:07:22.242485 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =20
6184 23:07:22.245564 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6185 23:07:22.249060 DQ12 =24, DQ13 =28, DQ14 =28, DQ15 =28
6186 23:07:22.249156
6187 23:07:22.249247
6188 23:07:22.258846 [DQSOSCAuto] RK0, (LSB)MR18= 0xabab, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 388 ps
6189 23:07:22.262520 CH0 RK0: MR19=C0C, MR18=ABAB
6190 23:07:22.268975 CH0_RK0: MR19=0xC0C, MR18=0xABAB, DQSOSC=388, MR23=63, INC=392, DEC=261
6191 23:07:22.269049 ==
6192 23:07:22.272501 Dram Type= 6, Freq= 0, CH_0, rank 1
6193 23:07:22.275287 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6194 23:07:22.275385 ==
6195 23:07:22.278661 [Gating] SW mode calibration
6196 23:07:22.285352 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6197 23:07:22.292138 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6198 23:07:22.295712 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6199 23:07:22.298545 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6200 23:07:22.305367 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6201 23:07:22.308661 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
6202 23:07:22.311675 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6203 23:07:22.318327 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6204 23:07:22.322052 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6205 23:07:22.324989 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
6206 23:07:22.328327 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6207 23:07:22.331755 Total UI for P1: 0, mck2ui 16
6208 23:07:22.334925 best dqsien dly found for B0: ( 0, 10, 16)
6209 23:07:22.338308 Total UI for P1: 0, mck2ui 16
6210 23:07:22.341678 best dqsien dly found for B1: ( 0, 10, 24)
6211 23:07:22.344985 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6212 23:07:22.351702 best DQS1 dly(MCK, UI, PI) = (0, 10, 24)
6213 23:07:22.351783
6214 23:07:22.354812 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6215 23:07:22.358350 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 24)
6216 23:07:22.361520 [Gating] SW calibration Done
6217 23:07:22.361601 ==
6218 23:07:22.364772 Dram Type= 6, Freq= 0, CH_0, rank 1
6219 23:07:22.368304 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6220 23:07:22.368386 ==
6221 23:07:22.371396 RX Vref Scan: 0
6222 23:07:22.371477
6223 23:07:22.371542 RX Vref 0 -> 0, step: 1
6224 23:07:22.371602
6225 23:07:22.374681 RX Delay -410 -> 252, step: 16
6226 23:07:22.378507 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6227 23:07:22.385017 iDelay=230, Bit 1, Center -35 (-298 ~ 229) 528
6228 23:07:22.387985 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6229 23:07:22.391237 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6230 23:07:22.394850 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6231 23:07:22.401071 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6232 23:07:22.404755 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6233 23:07:22.407673 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6234 23:07:22.411182 iDelay=230, Bit 8, Center -59 (-298 ~ 181) 480
6235 23:07:22.418145 iDelay=230, Bit 9, Center -67 (-314 ~ 181) 496
6236 23:07:22.421267 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6237 23:07:22.424338 iDelay=230, Bit 11, Center -59 (-298 ~ 181) 480
6238 23:07:22.430990 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6239 23:07:22.434176 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6240 23:07:22.437711 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6241 23:07:22.440893 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6242 23:07:22.440975 ==
6243 23:07:22.444488 Dram Type= 6, Freq= 0, CH_0, rank 1
6244 23:07:22.450851 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6245 23:07:22.450933 ==
6246 23:07:22.450997 DQS Delay:
6247 23:07:22.454252 DQS0 = 43, DQS1 = 67
6248 23:07:22.454333 DQM Delay:
6249 23:07:22.458067 DQM0 = 7, DQM1 = 21
6250 23:07:22.458148 DQ Delay:
6251 23:07:22.460932 DQ0 =0, DQ1 =8, DQ2 =0, DQ3 =0
6252 23:07:22.464222 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6253 23:07:22.464303 DQ8 =8, DQ9 =0, DQ10 =24, DQ11 =8
6254 23:07:22.470770 DQ12 =32, DQ13 =32, DQ14 =32, DQ15 =32
6255 23:07:22.470851
6256 23:07:22.470915
6257 23:07:22.470974 ==
6258 23:07:22.474052 Dram Type= 6, Freq= 0, CH_0, rank 1
6259 23:07:22.477562 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6260 23:07:22.477644 ==
6261 23:07:22.477710
6262 23:07:22.477769
6263 23:07:22.480632 TX Vref Scan disable
6264 23:07:22.480739 == TX Byte 0 ==
6265 23:07:22.484192 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6266 23:07:22.490947 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6267 23:07:22.491028 == TX Byte 1 ==
6268 23:07:22.494165 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6269 23:07:22.500376 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6270 23:07:22.500458 ==
6271 23:07:22.503946 Dram Type= 6, Freq= 0, CH_0, rank 1
6272 23:07:22.507073 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6273 23:07:22.507154 ==
6274 23:07:22.507218
6275 23:07:22.507277
6276 23:07:22.510542 TX Vref Scan disable
6277 23:07:22.510623 == TX Byte 0 ==
6278 23:07:22.517071 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6279 23:07:22.520438 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6280 23:07:22.520520 == TX Byte 1 ==
6281 23:07:22.523792 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6282 23:07:22.530225 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6283 23:07:22.530307
6284 23:07:22.530371 [DATLAT]
6285 23:07:22.533570 Freq=400, CH0 RK1
6286 23:07:22.533651
6287 23:07:22.533715 DATLAT Default: 0xd
6288 23:07:22.537271 0, 0xFFFF, sum = 0
6289 23:07:22.537354 1, 0xFFFF, sum = 0
6290 23:07:22.540093 2, 0xFFFF, sum = 0
6291 23:07:22.540175 3, 0xFFFF, sum = 0
6292 23:07:22.543712 4, 0xFFFF, sum = 0
6293 23:07:22.543793 5, 0xFFFF, sum = 0
6294 23:07:22.547212 6, 0xFFFF, sum = 0
6295 23:07:22.547294 7, 0xFFFF, sum = 0
6296 23:07:22.550140 8, 0xFFFF, sum = 0
6297 23:07:22.550222 9, 0xFFFF, sum = 0
6298 23:07:22.553612 10, 0xFFFF, sum = 0
6299 23:07:22.553694 11, 0xFFFF, sum = 0
6300 23:07:22.556998 12, 0x0, sum = 1
6301 23:07:22.557080 13, 0x0, sum = 2
6302 23:07:22.560018 14, 0x0, sum = 3
6303 23:07:22.560099 15, 0x0, sum = 4
6304 23:07:22.563445 best_step = 13
6305 23:07:22.563525
6306 23:07:22.563587 ==
6307 23:07:22.566675 Dram Type= 6, Freq= 0, CH_0, rank 1
6308 23:07:22.570341 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6309 23:07:22.570422 ==
6310 23:07:22.573496 RX Vref Scan: 0
6311 23:07:22.573576
6312 23:07:22.573640 RX Vref 0 -> 0, step: 1
6313 23:07:22.573699
6314 23:07:22.576703 RX Delay -359 -> 252, step: 8
6315 23:07:22.584701 iDelay=217, Bit 0, Center -48 (-295 ~ 200) 496
6316 23:07:22.588023 iDelay=217, Bit 1, Center -36 (-287 ~ 216) 504
6317 23:07:22.591260 iDelay=217, Bit 2, Center -40 (-287 ~ 208) 496
6318 23:07:22.594719 iDelay=217, Bit 3, Center -48 (-295 ~ 200) 496
6319 23:07:22.601652 iDelay=217, Bit 4, Center -40 (-287 ~ 208) 496
6320 23:07:22.605021 iDelay=217, Bit 5, Center -52 (-303 ~ 200) 504
6321 23:07:22.607979 iDelay=217, Bit 6, Center -32 (-279 ~ 216) 496
6322 23:07:22.614313 iDelay=217, Bit 7, Center -32 (-279 ~ 216) 496
6323 23:07:22.618036 iDelay=217, Bit 8, Center -64 (-303 ~ 176) 480
6324 23:07:22.621306 iDelay=217, Bit 9, Center -64 (-303 ~ 176) 480
6325 23:07:22.624473 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6326 23:07:22.630810 iDelay=217, Bit 11, Center -60 (-295 ~ 176) 472
6327 23:07:22.634276 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6328 23:07:22.637608 iDelay=217, Bit 13, Center -44 (-287 ~ 200) 488
6329 23:07:22.640781 iDelay=217, Bit 14, Center -40 (-279 ~ 200) 480
6330 23:07:22.647539 iDelay=217, Bit 15, Center -44 (-287 ~ 200) 488
6331 23:07:22.647620 ==
6332 23:07:22.650951 Dram Type= 6, Freq= 0, CH_0, rank 1
6333 23:07:22.654111 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6334 23:07:22.654192 ==
6335 23:07:22.654256 DQS Delay:
6336 23:07:22.657734 DQS0 = 52, DQS1 = 64
6337 23:07:22.657815 DQM Delay:
6338 23:07:22.660854 DQM0 = 11, DQM1 = 13
6339 23:07:22.660934 DQ Delay:
6340 23:07:22.664107 DQ0 =4, DQ1 =16, DQ2 =12, DQ3 =4
6341 23:07:22.667335 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6342 23:07:22.670856 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6343 23:07:22.674412 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6344 23:07:22.674493
6345 23:07:22.674556
6346 23:07:22.680750 [DQSOSCAuto] RK1, (LSB)MR18= 0xbbbb, (MSB)MR19= 0xc0c, tDQSOscB0 = 386 ps tDQSOscB1 = 386 ps
6347 23:07:22.683774 CH0 RK1: MR19=C0C, MR18=BBBB
6348 23:07:22.690559 CH0_RK1: MR19=0xC0C, MR18=0xBBBB, DQSOSC=386, MR23=63, INC=396, DEC=264
6349 23:07:22.694004 [RxdqsGatingPostProcess] freq 400
6350 23:07:22.700893 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6351 23:07:22.704101 Pre-setting of DQS Precalculation
6352 23:07:22.707114 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6353 23:07:22.707214 ==
6354 23:07:22.710496 Dram Type= 6, Freq= 0, CH_1, rank 0
6355 23:07:22.713741 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6356 23:07:22.713842 ==
6357 23:07:22.720614 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6358 23:07:22.727397 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6359 23:07:22.730795 [CA 0] Center 36 (8~64) winsize 57
6360 23:07:22.733868 [CA 1] Center 36 (8~64) winsize 57
6361 23:07:22.737020 [CA 2] Center 36 (8~64) winsize 57
6362 23:07:22.740388 [CA 3] Center 36 (8~64) winsize 57
6363 23:07:22.743770 [CA 4] Center 36 (8~64) winsize 57
6364 23:07:22.747309 [CA 5] Center 36 (8~64) winsize 57
6365 23:07:22.747406
6366 23:07:22.750356 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6367 23:07:22.750452
6368 23:07:22.753536 [CATrainingPosCal] consider 1 rank data
6369 23:07:22.757338 u2DelayCellTimex100 = 270/100 ps
6370 23:07:22.760303 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6371 23:07:22.763730 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6372 23:07:22.766716 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6373 23:07:22.770197 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6374 23:07:22.773600 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6375 23:07:22.776860 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6376 23:07:22.776958
6377 23:07:22.780137 CA PerBit enable=1, Macro0, CA PI delay=36
6378 23:07:22.783294
6379 23:07:22.783390 [CBTSetCACLKResult] CA Dly = 36
6380 23:07:22.786704 CS Dly: 1 (0~32)
6381 23:07:22.786809 ==
6382 23:07:22.790011 Dram Type= 6, Freq= 0, CH_1, rank 1
6383 23:07:22.793296 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6384 23:07:22.793394 ==
6385 23:07:22.799791 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6386 23:07:22.806366 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6387 23:07:22.809800 [CA 0] Center 36 (8~64) winsize 57
6388 23:07:22.812921 [CA 1] Center 36 (8~64) winsize 57
6389 23:07:22.816583 [CA 2] Center 36 (8~64) winsize 57
6390 23:07:22.816685 [CA 3] Center 36 (8~64) winsize 57
6391 23:07:22.819819 [CA 4] Center 36 (8~64) winsize 57
6392 23:07:22.822796 [CA 5] Center 36 (8~64) winsize 57
6393 23:07:22.822896
6394 23:07:22.829979 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6395 23:07:22.830097
6396 23:07:22.832826 [CATrainingPosCal] consider 2 rank data
6397 23:07:22.836428 u2DelayCellTimex100 = 270/100 ps
6398 23:07:22.839339 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6399 23:07:22.842775 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6400 23:07:22.846169 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6401 23:07:22.849631 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6402 23:07:22.852765 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6403 23:07:22.855934 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6404 23:07:22.856032
6405 23:07:22.859481 CA PerBit enable=1, Macro0, CA PI delay=36
6406 23:07:22.859578
6407 23:07:22.862569 [CBTSetCACLKResult] CA Dly = 36
6408 23:07:22.866169 CS Dly: 1 (0~32)
6409 23:07:22.866268
6410 23:07:22.869508 ----->DramcWriteLeveling(PI) begin...
6411 23:07:22.869606 ==
6412 23:07:22.872596 Dram Type= 6, Freq= 0, CH_1, rank 0
6413 23:07:22.875732 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6414 23:07:22.875829 ==
6415 23:07:22.879217 Write leveling (Byte 0): 32 => 0
6416 23:07:22.882741 Write leveling (Byte 1): 32 => 0
6417 23:07:22.885787 DramcWriteLeveling(PI) end<-----
6418 23:07:22.885887
6419 23:07:22.885975 ==
6420 23:07:22.889011 Dram Type= 6, Freq= 0, CH_1, rank 0
6421 23:07:22.892139 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6422 23:07:22.892251 ==
6423 23:07:22.895719 [Gating] SW mode calibration
6424 23:07:22.902178 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6425 23:07:22.908629 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6426 23:07:22.912185 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6427 23:07:22.915477 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6428 23:07:22.922458 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6429 23:07:22.925285 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6430 23:07:22.928581 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6431 23:07:22.935441 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6432 23:07:22.938521 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6433 23:07:22.941880 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6434 23:07:22.948635 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6435 23:07:22.951895 Total UI for P1: 0, mck2ui 16
6436 23:07:22.955052 best dqsien dly found for B0: ( 0, 10, 16)
6437 23:07:22.958323 Total UI for P1: 0, mck2ui 16
6438 23:07:22.961759 best dqsien dly found for B1: ( 0, 10, 16)
6439 23:07:22.965034 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6440 23:07:22.968177 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6441 23:07:22.968272
6442 23:07:22.971684 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6443 23:07:22.974975 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6444 23:07:22.978284 [Gating] SW calibration Done
6445 23:07:22.978383 ==
6446 23:07:22.981830 Dram Type= 6, Freq= 0, CH_1, rank 0
6447 23:07:22.984925 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6448 23:07:22.985019 ==
6449 23:07:22.987879 RX Vref Scan: 0
6450 23:07:22.987976
6451 23:07:22.991456 RX Vref 0 -> 0, step: 1
6452 23:07:22.991564
6453 23:07:22.994648 RX Delay -410 -> 252, step: 16
6454 23:07:22.997874 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6455 23:07:23.001380 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6456 23:07:23.004551 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6457 23:07:23.011009 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6458 23:07:23.014392 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6459 23:07:23.017681 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6460 23:07:23.020864 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6461 23:07:23.027556 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6462 23:07:23.031274 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6463 23:07:23.034330 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6464 23:07:23.037805 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6465 23:07:23.044480 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6466 23:07:23.047528 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6467 23:07:23.050819 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6468 23:07:23.057447 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6469 23:07:23.060750 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6470 23:07:23.060825 ==
6471 23:07:23.064053 Dram Type= 6, Freq= 0, CH_1, rank 0
6472 23:07:23.067311 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6473 23:07:23.067415 ==
6474 23:07:23.070528 DQS Delay:
6475 23:07:23.070604 DQS0 = 43, DQS1 = 59
6476 23:07:23.070668 DQM Delay:
6477 23:07:23.073962 DQM0 = 6, DQM1 = 15
6478 23:07:23.074052 DQ Delay:
6479 23:07:23.077510 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6480 23:07:23.080480 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6481 23:07:23.083893 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6482 23:07:23.086951 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =32
6483 23:07:23.087057
6484 23:07:23.087148
6485 23:07:23.087236 ==
6486 23:07:23.090333 Dram Type= 6, Freq= 0, CH_1, rank 0
6487 23:07:23.093900 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6488 23:07:23.096923 ==
6489 23:07:23.097029
6490 23:07:23.097120
6491 23:07:23.097216 TX Vref Scan disable
6492 23:07:23.100256 == TX Byte 0 ==
6493 23:07:23.103804 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6494 23:07:23.106927 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6495 23:07:23.110202 == TX Byte 1 ==
6496 23:07:23.113739 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6497 23:07:23.116955 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6498 23:07:23.117052 ==
6499 23:07:23.120353 Dram Type= 6, Freq= 0, CH_1, rank 0
6500 23:07:23.126836 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6501 23:07:23.126935 ==
6502 23:07:23.127036
6503 23:07:23.127123
6504 23:07:23.127216 TX Vref Scan disable
6505 23:07:23.130197 == TX Byte 0 ==
6506 23:07:23.133565 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6507 23:07:23.136597 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6508 23:07:23.139911 == TX Byte 1 ==
6509 23:07:23.143375 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6510 23:07:23.146631 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6511 23:07:23.149798
6512 23:07:23.149894 [DATLAT]
6513 23:07:23.149991 Freq=400, CH1 RK0
6514 23:07:23.150084
6515 23:07:23.153089 DATLAT Default: 0xf
6516 23:07:23.153183 0, 0xFFFF, sum = 0
6517 23:07:23.156500 1, 0xFFFF, sum = 0
6518 23:07:23.156604 2, 0xFFFF, sum = 0
6519 23:07:23.159961 3, 0xFFFF, sum = 0
6520 23:07:23.163251 4, 0xFFFF, sum = 0
6521 23:07:23.163329 5, 0xFFFF, sum = 0
6522 23:07:23.166322 6, 0xFFFF, sum = 0
6523 23:07:23.166404 7, 0xFFFF, sum = 0
6524 23:07:23.169880 8, 0xFFFF, sum = 0
6525 23:07:23.169974 9, 0xFFFF, sum = 0
6526 23:07:23.172986 10, 0xFFFF, sum = 0
6527 23:07:23.173061 11, 0xFFFF, sum = 0
6528 23:07:23.176374 12, 0x0, sum = 1
6529 23:07:23.176472 13, 0x0, sum = 2
6530 23:07:23.179719 14, 0x0, sum = 3
6531 23:07:23.179821 15, 0x0, sum = 4
6532 23:07:23.179917 best_step = 13
6533 23:07:23.183062
6534 23:07:23.183154 ==
6535 23:07:23.186305 Dram Type= 6, Freq= 0, CH_1, rank 0
6536 23:07:23.189736 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6537 23:07:23.189835 ==
6538 23:07:23.189927 RX Vref Scan: 1
6539 23:07:23.190016
6540 23:07:23.193184 RX Vref 0 -> 0, step: 1
6541 23:07:23.193281
6542 23:07:23.196080 RX Delay -359 -> 252, step: 8
6543 23:07:23.196177
6544 23:07:23.199352 Set Vref, RX VrefLevel [Byte0]: 51
6545 23:07:23.202754 [Byte1]: 50
6546 23:07:23.207047
6547 23:07:23.207154 Final RX Vref Byte 0 = 51 to rank0
6548 23:07:23.210254 Final RX Vref Byte 1 = 50 to rank0
6549 23:07:23.213633 Final RX Vref Byte 0 = 51 to rank1
6550 23:07:23.217056 Final RX Vref Byte 1 = 50 to rank1==
6551 23:07:23.220223 Dram Type= 6, Freq= 0, CH_1, rank 0
6552 23:07:23.226862 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6553 23:07:23.226970 ==
6554 23:07:23.227065 DQS Delay:
6555 23:07:23.230360 DQS0 = 48, DQS1 = 64
6556 23:07:23.230460 DQM Delay:
6557 23:07:23.230553 DQM0 = 8, DQM1 = 15
6558 23:07:23.233655 DQ Delay:
6559 23:07:23.236630 DQ0 =12, DQ1 =0, DQ2 =0, DQ3 =8
6560 23:07:23.236770 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6561 23:07:23.239949 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6562 23:07:23.243506 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6563 23:07:23.243603
6564 23:07:23.246360
6565 23:07:23.253029 [DQSOSCAuto] RK0, (LSB)MR18= 0xd1d1, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 384 ps
6566 23:07:23.256789 CH1 RK0: MR19=C0C, MR18=D1D1
6567 23:07:23.263255 CH1_RK0: MR19=0xC0C, MR18=0xD1D1, DQSOSC=384, MR23=63, INC=400, DEC=267
6568 23:07:23.263359 ==
6569 23:07:23.266256 Dram Type= 6, Freq= 0, CH_1, rank 1
6570 23:07:23.269696 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6571 23:07:23.269786 ==
6572 23:07:23.273238 [Gating] SW mode calibration
6573 23:07:23.279378 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6574 23:07:23.286070 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6575 23:07:23.289647 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6576 23:07:23.292641 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6577 23:07:23.299267 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6578 23:07:23.302946 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6579 23:07:23.305892 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6580 23:07:23.312748 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6581 23:07:23.315964 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6582 23:07:23.319163 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6583 23:07:23.326011 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6584 23:07:23.326113 Total UI for P1: 0, mck2ui 16
6585 23:07:23.328976 best dqsien dly found for B0: ( 0, 10, 16)
6586 23:07:23.332459 Total UI for P1: 0, mck2ui 16
6587 23:07:23.335678 best dqsien dly found for B1: ( 0, 10, 16)
6588 23:07:23.342561 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6589 23:07:23.345774 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6590 23:07:23.345875
6591 23:07:23.348912 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6592 23:07:23.352175 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6593 23:07:23.355496 [Gating] SW calibration Done
6594 23:07:23.355597 ==
6595 23:07:23.358667 Dram Type= 6, Freq= 0, CH_1, rank 1
6596 23:07:23.362188 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6597 23:07:23.362287 ==
6598 23:07:23.365338 RX Vref Scan: 0
6599 23:07:23.365409
6600 23:07:23.365469 RX Vref 0 -> 0, step: 1
6601 23:07:23.365533
6602 23:07:23.369283 RX Delay -410 -> 252, step: 16
6603 23:07:23.375332 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6604 23:07:23.378493 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6605 23:07:23.381880 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6606 23:07:23.385171 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6607 23:07:23.392122 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6608 23:07:23.395278 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6609 23:07:23.398486 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6610 23:07:23.401713 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6611 23:07:23.408404 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6612 23:07:23.412048 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6613 23:07:23.415154 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6614 23:07:23.418360 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6615 23:07:23.425006 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6616 23:07:23.428653 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6617 23:07:23.431499 iDelay=230, Bit 14, Center -35 (-298 ~ 229) 528
6618 23:07:23.434825 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6619 23:07:23.438727 ==
6620 23:07:23.442050 Dram Type= 6, Freq= 0, CH_1, rank 1
6621 23:07:23.445085 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6622 23:07:23.445190 ==
6623 23:07:23.445284 DQS Delay:
6624 23:07:23.448231 DQS0 = 43, DQS1 = 59
6625 23:07:23.448326 DQM Delay:
6626 23:07:23.451510 DQM0 = 10, DQM1 = 17
6627 23:07:23.451604 DQ Delay:
6628 23:07:23.454827 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6629 23:07:23.458644 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6630 23:07:23.461328 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6631 23:07:23.465013 DQ12 =32, DQ13 =32, DQ14 =24, DQ15 =24
6632 23:07:23.465094
6633 23:07:23.465158
6634 23:07:23.465218 ==
6635 23:07:23.468202 Dram Type= 6, Freq= 0, CH_1, rank 1
6636 23:07:23.471411 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6637 23:07:23.471493 ==
6638 23:07:23.471558
6639 23:07:23.471617
6640 23:07:23.474710 TX Vref Scan disable
6641 23:07:23.474792 == TX Byte 0 ==
6642 23:07:23.481487 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6643 23:07:23.484633 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6644 23:07:23.484727 == TX Byte 1 ==
6645 23:07:23.491454 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6646 23:07:23.494861 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6647 23:07:23.494965 ==
6648 23:07:23.497890 Dram Type= 6, Freq= 0, CH_1, rank 1
6649 23:07:23.501159 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6650 23:07:23.501258 ==
6651 23:07:23.501348
6652 23:07:23.501438
6653 23:07:23.504524 TX Vref Scan disable
6654 23:07:23.504626 == TX Byte 0 ==
6655 23:07:23.511346 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6656 23:07:23.514527 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6657 23:07:23.514624 == TX Byte 1 ==
6658 23:07:23.521262 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6659 23:07:23.524400 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6660 23:07:23.524495
6661 23:07:23.524587 [DATLAT]
6662 23:07:23.528021 Freq=400, CH1 RK1
6663 23:07:23.528117
6664 23:07:23.528206 DATLAT Default: 0xd
6665 23:07:23.530924 0, 0xFFFF, sum = 0
6666 23:07:23.531023 1, 0xFFFF, sum = 0
6667 23:07:23.534597 2, 0xFFFF, sum = 0
6668 23:07:23.534692 3, 0xFFFF, sum = 0
6669 23:07:23.537557 4, 0xFFFF, sum = 0
6670 23:07:23.537653 5, 0xFFFF, sum = 0
6671 23:07:23.540838 6, 0xFFFF, sum = 0
6672 23:07:23.540936 7, 0xFFFF, sum = 0
6673 23:07:23.544199 8, 0xFFFF, sum = 0
6674 23:07:23.544295 9, 0xFFFF, sum = 0
6675 23:07:23.547444 10, 0xFFFF, sum = 0
6676 23:07:23.551102 11, 0xFFFF, sum = 0
6677 23:07:23.551174 12, 0x0, sum = 1
6678 23:07:23.554290 13, 0x0, sum = 2
6679 23:07:23.554363 14, 0x0, sum = 3
6680 23:07:23.554426 15, 0x0, sum = 4
6681 23:07:23.557507 best_step = 13
6682 23:07:23.557581
6683 23:07:23.557647 ==
6684 23:07:23.560773 Dram Type= 6, Freq= 0, CH_1, rank 1
6685 23:07:23.564050 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6686 23:07:23.564161 ==
6687 23:07:23.567369 RX Vref Scan: 0
6688 23:07:23.567468
6689 23:07:23.567558 RX Vref 0 -> 0, step: 1
6690 23:07:23.570450
6691 23:07:23.570545 RX Delay -359 -> 252, step: 8
6692 23:07:23.579133 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6693 23:07:23.582832 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
6694 23:07:23.586165 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
6695 23:07:23.589110 iDelay=217, Bit 3, Center -44 (-287 ~ 200) 488
6696 23:07:23.595791 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6697 23:07:23.599514 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6698 23:07:23.602751 iDelay=217, Bit 6, Center -32 (-279 ~ 216) 496
6699 23:07:23.605964 iDelay=217, Bit 7, Center -40 (-287 ~ 208) 496
6700 23:07:23.612743 iDelay=217, Bit 8, Center -64 (-311 ~ 184) 496
6701 23:07:23.615606 iDelay=217, Bit 9, Center -60 (-311 ~ 192) 504
6702 23:07:23.619337 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6703 23:07:23.622453 iDelay=217, Bit 11, Center -56 (-303 ~ 192) 496
6704 23:07:23.628992 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6705 23:07:23.632262 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6706 23:07:23.635716 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6707 23:07:23.642513 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6708 23:07:23.642613 ==
6709 23:07:23.645644 Dram Type= 6, Freq= 0, CH_1, rank 1
6710 23:07:23.648837 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6711 23:07:23.648937 ==
6712 23:07:23.649030 DQS Delay:
6713 23:07:23.652051 DQS0 = 48, DQS1 = 64
6714 23:07:23.652146 DQM Delay:
6715 23:07:23.655433 DQM0 = 9, DQM1 = 15
6716 23:07:23.655521 DQ Delay:
6717 23:07:23.659009 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6718 23:07:23.662116 DQ4 =12, DQ5 =20, DQ6 =16, DQ7 =8
6719 23:07:23.665495 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6720 23:07:23.668919 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6721 23:07:23.669000
6722 23:07:23.669064
6723 23:07:23.675649 [DQSOSCAuto] RK1, (LSB)MR18= 0xb6b6, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 387 ps
6724 23:07:23.678664 CH1 RK1: MR19=C0C, MR18=B6B6
6725 23:07:23.685187 CH1_RK1: MR19=0xC0C, MR18=0xB6B6, DQSOSC=387, MR23=63, INC=394, DEC=262
6726 23:07:23.688839 [RxdqsGatingPostProcess] freq 400
6727 23:07:23.695023 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6728 23:07:23.695132 Pre-setting of DQS Precalculation
6729 23:07:23.701785 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6730 23:07:23.708436 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6731 23:07:23.715099 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6732 23:07:23.715181
6733 23:07:23.715245
6734 23:07:23.718350 [Calibration Summary] 800 Mbps
6735 23:07:23.721682 CH 0, Rank 0
6736 23:07:23.721763 SW Impedance : PASS
6737 23:07:23.724973 DUTY Scan : NO K
6738 23:07:23.728392 ZQ Calibration : PASS
6739 23:07:23.728472 Jitter Meter : NO K
6740 23:07:23.731602 CBT Training : PASS
6741 23:07:23.735304 Write leveling : PASS
6742 23:07:23.735385 RX DQS gating : PASS
6743 23:07:23.738473 RX DQ/DQS(RDDQC) : PASS
6744 23:07:23.738555 TX DQ/DQS : PASS
6745 23:07:23.741619 RX DATLAT : PASS
6746 23:07:23.745249 RX DQ/DQS(Engine): PASS
6747 23:07:23.745331 TX OE : NO K
6748 23:07:23.748221 All Pass.
6749 23:07:23.748302
6750 23:07:23.748366 CH 0, Rank 1
6751 23:07:23.751591 SW Impedance : PASS
6752 23:07:23.751672 DUTY Scan : NO K
6753 23:07:23.754999 ZQ Calibration : PASS
6754 23:07:23.758413 Jitter Meter : NO K
6755 23:07:23.758493 CBT Training : PASS
6756 23:07:23.761572 Write leveling : NO K
6757 23:07:23.764815 RX DQS gating : PASS
6758 23:07:23.764897 RX DQ/DQS(RDDQC) : PASS
6759 23:07:23.768095 TX DQ/DQS : PASS
6760 23:07:23.771337 RX DATLAT : PASS
6761 23:07:23.771418 RX DQ/DQS(Engine): PASS
6762 23:07:23.774951 TX OE : NO K
6763 23:07:23.775033 All Pass.
6764 23:07:23.775097
6765 23:07:23.777944 CH 1, Rank 0
6766 23:07:23.778025 SW Impedance : PASS
6767 23:07:23.781383 DUTY Scan : NO K
6768 23:07:23.784501 ZQ Calibration : PASS
6769 23:07:23.784582 Jitter Meter : NO K
6770 23:07:23.788120 CBT Training : PASS
6771 23:07:23.791190 Write leveling : PASS
6772 23:07:23.791271 RX DQS gating : PASS
6773 23:07:23.794539 RX DQ/DQS(RDDQC) : PASS
6774 23:07:23.794621 TX DQ/DQS : PASS
6775 23:07:23.797956 RX DATLAT : PASS
6776 23:07:23.801049 RX DQ/DQS(Engine): PASS
6777 23:07:23.801130 TX OE : NO K
6778 23:07:23.804333 All Pass.
6779 23:07:23.804414
6780 23:07:23.804477 CH 1, Rank 1
6781 23:07:23.807701 SW Impedance : PASS
6782 23:07:23.807782 DUTY Scan : NO K
6783 23:07:23.811614 ZQ Calibration : PASS
6784 23:07:23.814746 Jitter Meter : NO K
6785 23:07:23.814827 CBT Training : PASS
6786 23:07:23.818032 Write leveling : NO K
6787 23:07:23.821063 RX DQS gating : PASS
6788 23:07:23.821145 RX DQ/DQS(RDDQC) : PASS
6789 23:07:23.824334 TX DQ/DQS : PASS
6790 23:07:23.827606 RX DATLAT : PASS
6791 23:07:23.827687 RX DQ/DQS(Engine): PASS
6792 23:07:23.831111 TX OE : NO K
6793 23:07:23.831192 All Pass.
6794 23:07:23.831256
6795 23:07:23.834111 DramC Write-DBI off
6796 23:07:23.837762 PER_BANK_REFRESH: Hybrid Mode
6797 23:07:23.837842 TX_TRACKING: ON
6798 23:07:23.847467 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
6799 23:07:23.850796 [FAST_K] Save calibration result to emmc
6800 23:07:23.854115 dramc_set_vcore_voltage set vcore to 725000
6801 23:07:23.857291 Read voltage for 1600, 0
6802 23:07:23.857372 Vio18 = 0
6803 23:07:23.857436 Vcore = 725000
6804 23:07:23.860740 Vdram = 0
6805 23:07:23.860822 Vddq = 0
6806 23:07:23.860886 Vmddr = 0
6807 23:07:23.867516 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
6808 23:07:23.870751 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6809 23:07:23.874144 MEM_TYPE=3, freq_sel=13
6810 23:07:23.877288 sv_algorithm_assistance_LP4_3733
6811 23:07:23.880461 ============ PULL DRAM RESETB DOWN ============
6812 23:07:23.883819 ========== PULL DRAM RESETB DOWN end =========
6813 23:07:23.890669 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6814 23:07:23.893902 ===================================
6815 23:07:23.897233 LPDDR4 DRAM CONFIGURATION
6816 23:07:23.900429 ===================================
6817 23:07:23.900514 EX_ROW_EN[0] = 0x0
6818 23:07:23.903933 EX_ROW_EN[1] = 0x0
6819 23:07:23.904014 LP4Y_EN = 0x0
6820 23:07:23.907234 WORK_FSP = 0x1
6821 23:07:23.907334 WL = 0x5
6822 23:07:23.910265 RL = 0x5
6823 23:07:23.910345 BL = 0x2
6824 23:07:23.913752 RPST = 0x0
6825 23:07:23.913834 RD_PRE = 0x0
6826 23:07:23.916938 WR_PRE = 0x1
6827 23:07:23.917019 WR_PST = 0x1
6828 23:07:23.920431 DBI_WR = 0x0
6829 23:07:23.920512 DBI_RD = 0x0
6830 23:07:23.923682 OTF = 0x1
6831 23:07:23.926824 ===================================
6832 23:07:23.930714 ===================================
6833 23:07:23.930795 ANA top config
6834 23:07:23.933513 ===================================
6835 23:07:23.937132 DLL_ASYNC_EN = 0
6836 23:07:23.940210 ALL_SLAVE_EN = 0
6837 23:07:23.943579 NEW_RANK_MODE = 1
6838 23:07:23.946628 DLL_IDLE_MODE = 1
6839 23:07:23.946709 LP45_APHY_COMB_EN = 1
6840 23:07:23.950321 TX_ODT_DIS = 0
6841 23:07:23.953436 NEW_8X_MODE = 1
6842 23:07:23.956612 ===================================
6843 23:07:23.960023 ===================================
6844 23:07:23.963251 data_rate = 3200
6845 23:07:23.966823 CKR = 1
6846 23:07:23.966924 DQ_P2S_RATIO = 8
6847 23:07:23.970227 ===================================
6848 23:07:23.973396 CA_P2S_RATIO = 8
6849 23:07:23.976511 DQ_CA_OPEN = 0
6850 23:07:23.979761 DQ_SEMI_OPEN = 0
6851 23:07:23.983064 CA_SEMI_OPEN = 0
6852 23:07:23.986943 CA_FULL_RATE = 0
6853 23:07:23.987044 DQ_CKDIV4_EN = 0
6854 23:07:23.989858 CA_CKDIV4_EN = 0
6855 23:07:23.993066 CA_PREDIV_EN = 0
6856 23:07:23.996318 PH8_DLY = 12
6857 23:07:23.999612 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
6858 23:07:24.002842 DQ_AAMCK_DIV = 4
6859 23:07:24.002942 CA_AAMCK_DIV = 4
6860 23:07:24.006424 CA_ADMCK_DIV = 4
6861 23:07:24.009450 DQ_TRACK_CA_EN = 0
6862 23:07:24.012874 CA_PICK = 1600
6863 23:07:24.016469 CA_MCKIO = 1600
6864 23:07:24.019707 MCKIO_SEMI = 0
6865 23:07:24.022821 PLL_FREQ = 3068
6866 23:07:24.026027 DQ_UI_PI_RATIO = 32
6867 23:07:24.026129 CA_UI_PI_RATIO = 0
6868 23:07:24.029457 ===================================
6869 23:07:24.032686 ===================================
6870 23:07:24.036157 memory_type:LPDDR4
6871 23:07:24.039474 GP_NUM : 10
6872 23:07:24.039572 SRAM_EN : 1
6873 23:07:24.042691 MD32_EN : 0
6874 23:07:24.046334 ===================================
6875 23:07:24.049220 [ANA_INIT] >>>>>>>>>>>>>>
6876 23:07:24.052635 <<<<<< [CONFIGURE PHASE]: ANA_TX
6877 23:07:24.055831 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6878 23:07:24.059295 ===================================
6879 23:07:24.059383 data_rate = 3200,PCW = 0X7600
6880 23:07:24.062703 ===================================
6881 23:07:24.066036 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6882 23:07:24.072729 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6883 23:07:24.079636 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6884 23:07:24.082530 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6885 23:07:24.086042 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6886 23:07:24.089532 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6887 23:07:24.092356 [ANA_INIT] flow start
6888 23:07:24.092436 [ANA_INIT] PLL >>>>>>>>
6889 23:07:24.095723 [ANA_INIT] PLL <<<<<<<<
6890 23:07:24.099076 [ANA_INIT] MIDPI >>>>>>>>
6891 23:07:24.102355 [ANA_INIT] MIDPI <<<<<<<<
6892 23:07:24.102436 [ANA_INIT] DLL >>>>>>>>
6893 23:07:24.105780 [ANA_INIT] DLL <<<<<<<<
6894 23:07:24.109307 [ANA_INIT] flow end
6895 23:07:24.112340 ============ LP4 DIFF to SE enter ============
6896 23:07:24.115654 ============ LP4 DIFF to SE exit ============
6897 23:07:24.119060 [ANA_INIT] <<<<<<<<<<<<<
6898 23:07:24.122324 [Flow] Enable top DCM control >>>>>
6899 23:07:24.125741 [Flow] Enable top DCM control <<<<<
6900 23:07:24.129038 Enable DLL master slave shuffle
6901 23:07:24.132130 ==============================================================
6902 23:07:24.135346 Gating Mode config
6903 23:07:24.141904 ==============================================================
6904 23:07:24.141996 Config description:
6905 23:07:24.151940 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6906 23:07:24.158545 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6907 23:07:24.162046 SELPH_MODE 0: By rank 1: By Phase
6908 23:07:24.168631 ==============================================================
6909 23:07:24.172372 GAT_TRACK_EN = 1
6910 23:07:24.175059 RX_GATING_MODE = 2
6911 23:07:24.178795 RX_GATING_TRACK_MODE = 2
6912 23:07:24.181706 SELPH_MODE = 1
6913 23:07:24.185392 PICG_EARLY_EN = 1
6914 23:07:24.188395 VALID_LAT_VALUE = 1
6915 23:07:24.192256 ==============================================================
6916 23:07:24.194985 Enter into Gating configuration >>>>
6917 23:07:24.198716 Exit from Gating configuration <<<<
6918 23:07:24.201859 Enter into DVFS_PRE_config >>>>>
6919 23:07:24.214752 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6920 23:07:24.214839 Exit from DVFS_PRE_config <<<<<
6921 23:07:24.218380 Enter into PICG configuration >>>>
6922 23:07:24.221834 Exit from PICG configuration <<<<
6923 23:07:24.224904 [RX_INPUT] configuration >>>>>
6924 23:07:24.228061 [RX_INPUT] configuration <<<<<
6925 23:07:24.234716 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6926 23:07:24.237874 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6927 23:07:24.244878 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6928 23:07:24.251051 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6929 23:07:24.257861 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6930 23:07:24.264834 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6931 23:07:24.267957 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6932 23:07:24.271002 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6933 23:07:24.274372 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6934 23:07:24.280756 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6935 23:07:24.284364 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6936 23:07:24.287315 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6937 23:07:24.290979 ===================================
6938 23:07:24.294444 LPDDR4 DRAM CONFIGURATION
6939 23:07:24.297793 ===================================
6940 23:07:24.300654 EX_ROW_EN[0] = 0x0
6941 23:07:24.300756 EX_ROW_EN[1] = 0x0
6942 23:07:24.304182 LP4Y_EN = 0x0
6943 23:07:24.304262 WORK_FSP = 0x1
6944 23:07:24.307355 WL = 0x5
6945 23:07:24.307438 RL = 0x5
6946 23:07:24.310692 BL = 0x2
6947 23:07:24.310773 RPST = 0x0
6948 23:07:24.313834 RD_PRE = 0x0
6949 23:07:24.313914 WR_PRE = 0x1
6950 23:07:24.317232 WR_PST = 0x1
6951 23:07:24.317313 DBI_WR = 0x0
6952 23:07:24.320660 DBI_RD = 0x0
6953 23:07:24.320781 OTF = 0x1
6954 23:07:24.324300 ===================================
6955 23:07:24.330829 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6956 23:07:24.333940 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6957 23:07:24.337464 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6958 23:07:24.340814 ===================================
6959 23:07:24.344030 LPDDR4 DRAM CONFIGURATION
6960 23:07:24.347165 ===================================
6961 23:07:24.350692 EX_ROW_EN[0] = 0x10
6962 23:07:24.350773 EX_ROW_EN[1] = 0x0
6963 23:07:24.353784 LP4Y_EN = 0x0
6964 23:07:24.353865 WORK_FSP = 0x1
6965 23:07:24.357233 WL = 0x5
6966 23:07:24.357314 RL = 0x5
6967 23:07:24.360459 BL = 0x2
6968 23:07:24.360539 RPST = 0x0
6969 23:07:24.363737 RD_PRE = 0x0
6970 23:07:24.363818 WR_PRE = 0x1
6971 23:07:24.366976 WR_PST = 0x1
6972 23:07:24.367057 DBI_WR = 0x0
6973 23:07:24.370185 DBI_RD = 0x0
6974 23:07:24.370266 OTF = 0x1
6975 23:07:24.373656 ===================================
6976 23:07:24.379983 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6977 23:07:24.380064 ==
6978 23:07:24.383649 Dram Type= 6, Freq= 0, CH_0, rank 0
6979 23:07:24.390157 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
6980 23:07:24.390239 ==
6981 23:07:24.390304 [Duty_Offset_Calibration]
6982 23:07:24.393684 B0:0 B1:2 CA:1
6983 23:07:24.393765
6984 23:07:24.396717 [DutyScan_Calibration_Flow] k_type=0
6985 23:07:24.406105
6986 23:07:24.406187 ==CLK 0==
6987 23:07:24.409513 Final CLK duty delay cell = 0
6988 23:07:24.412890 [0] MAX Duty = 5156%(X100), DQS PI = 20
6989 23:07:24.416391 [0] MIN Duty = 4938%(X100), DQS PI = 50
6990 23:07:24.416473 [0] AVG Duty = 5047%(X100)
6991 23:07:24.419368
6992 23:07:24.422533 CH0 CLK Duty spec in!! Max-Min= 218%
6993 23:07:24.425933 [DutyScan_Calibration_Flow] ====Done====
6994 23:07:24.426015
6995 23:07:24.429190 [DutyScan_Calibration_Flow] k_type=1
6996 23:07:24.446125
6997 23:07:24.446206 ==DQS 0 ==
6998 23:07:24.449464 Final DQS duty delay cell = 0
6999 23:07:24.452553 [0] MAX Duty = 5125%(X100), DQS PI = 22
7000 23:07:24.455841 [0] MIN Duty = 5031%(X100), DQS PI = 8
7001 23:07:24.455922 [0] AVG Duty = 5078%(X100)
7002 23:07:24.459651
7003 23:07:24.459732 ==DQS 1 ==
7004 23:07:24.462823 Final DQS duty delay cell = 0
7005 23:07:24.466042 [0] MAX Duty = 5031%(X100), DQS PI = 0
7006 23:07:24.469379 [0] MIN Duty = 4876%(X100), DQS PI = 16
7007 23:07:24.472322 [0] AVG Duty = 4953%(X100)
7008 23:07:24.472403
7009 23:07:24.475907 CH0 DQS 0 Duty spec in!! Max-Min= 94%
7010 23:07:24.475988
7011 23:07:24.479369 CH0 DQS 1 Duty spec in!! Max-Min= 155%
7012 23:07:24.482281 [DutyScan_Calibration_Flow] ====Done====
7013 23:07:24.482382
7014 23:07:24.485927 [DutyScan_Calibration_Flow] k_type=3
7015 23:07:24.502966
7016 23:07:24.503068 ==DQM 0 ==
7017 23:07:24.506759 Final DQM duty delay cell = 0
7018 23:07:24.509518 [0] MAX Duty = 5187%(X100), DQS PI = 22
7019 23:07:24.512931 [0] MIN Duty = 4907%(X100), DQS PI = 42
7020 23:07:24.516233 [0] AVG Duty = 5047%(X100)
7021 23:07:24.516333
7022 23:07:24.516424 ==DQM 1 ==
7023 23:07:24.519743 Final DQM duty delay cell = 0
7024 23:07:24.522833 [0] MAX Duty = 5031%(X100), DQS PI = 52
7025 23:07:24.526386 [0] MIN Duty = 4782%(X100), DQS PI = 14
7026 23:07:24.529508 [0] AVG Duty = 4906%(X100)
7027 23:07:24.529607
7028 23:07:24.532749 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7029 23:07:24.532858
7030 23:07:24.536361 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7031 23:07:24.539338 [DutyScan_Calibration_Flow] ====Done====
7032 23:07:24.539408
7033 23:07:24.542462 [DutyScan_Calibration_Flow] k_type=2
7034 23:07:24.559297
7035 23:07:24.559399 ==DQ 0 ==
7036 23:07:24.562732 Final DQ duty delay cell = 0
7037 23:07:24.566065 [0] MAX Duty = 5218%(X100), DQS PI = 18
7038 23:07:24.569205 [0] MIN Duty = 4938%(X100), DQS PI = 56
7039 23:07:24.569301 [0] AVG Duty = 5078%(X100)
7040 23:07:24.572535
7041 23:07:24.572632 ==DQ 1 ==
7042 23:07:24.575828 Final DQ duty delay cell = -4
7043 23:07:24.579495 [-4] MAX Duty = 5062%(X100), DQS PI = 4
7044 23:07:24.582596 [-4] MIN Duty = 4844%(X100), DQS PI = 36
7045 23:07:24.586013 [-4] AVG Duty = 4953%(X100)
7046 23:07:24.586110
7047 23:07:24.589064 CH0 DQ 0 Duty spec in!! Max-Min= 280%
7048 23:07:24.589163
7049 23:07:24.592686 CH0 DQ 1 Duty spec in!! Max-Min= 218%
7050 23:07:24.595764 [DutyScan_Calibration_Flow] ====Done====
7051 23:07:24.595839 ==
7052 23:07:24.599442 Dram Type= 6, Freq= 0, CH_1, rank 0
7053 23:07:24.602525 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7054 23:07:24.602623 ==
7055 23:07:24.606012 [Duty_Offset_Calibration]
7056 23:07:24.606113 B0:0 B1:4 CA:-5
7057 23:07:24.606202
7058 23:07:24.608943 [DutyScan_Calibration_Flow] k_type=0
7059 23:07:24.619987
7060 23:07:24.620087 ==CLK 0==
7061 23:07:24.626436 Final CLK duty delay cell = 0
7062 23:07:24.626725 [0] MAX Duty = 5156%(X100), DQS PI = 20
7063 23:07:24.629936 [0] MIN Duty = 4906%(X100), DQS PI = 52
7064 23:07:24.633213 [0] AVG Duty = 5031%(X100)
7065 23:07:24.633313
7066 23:07:24.636598 CH1 CLK Duty spec in!! Max-Min= 250%
7067 23:07:24.639676 [DutyScan_Calibration_Flow] ====Done====
7068 23:07:24.639777
7069 23:07:24.643110 [DutyScan_Calibration_Flow] k_type=1
7070 23:07:24.659062
7071 23:07:24.659163 ==DQS 0 ==
7072 23:07:24.662116 Final DQS duty delay cell = 0
7073 23:07:24.665616 [0] MAX Duty = 5187%(X100), DQS PI = 20
7074 23:07:24.668704 [0] MIN Duty = 4876%(X100), DQS PI = 42
7075 23:07:24.672163 [0] AVG Duty = 5031%(X100)
7076 23:07:24.672261
7077 23:07:24.672355 ==DQS 1 ==
7078 23:07:24.675419 Final DQS duty delay cell = -4
7079 23:07:24.678741 [-4] MAX Duty = 5000%(X100), DQS PI = 18
7080 23:07:24.682391 [-4] MIN Duty = 4844%(X100), DQS PI = 56
7081 23:07:24.685618 [-4] AVG Duty = 4922%(X100)
7082 23:07:24.685716
7083 23:07:24.689137 CH1 DQS 0 Duty spec in!! Max-Min= 311%
7084 23:07:24.689234
7085 23:07:24.692104 CH1 DQS 1 Duty spec in!! Max-Min= 156%
7086 23:07:24.695755 [DutyScan_Calibration_Flow] ====Done====
7087 23:07:24.695829
7088 23:07:24.698869 [DutyScan_Calibration_Flow] k_type=3
7089 23:07:24.714540
7090 23:07:24.714644 ==DQM 0 ==
7091 23:07:24.717975 Final DQM duty delay cell = -4
7092 23:07:24.721557 [-4] MAX Duty = 5062%(X100), DQS PI = 34
7093 23:07:24.724514 [-4] MIN Duty = 4813%(X100), DQS PI = 42
7094 23:07:24.727825 [-4] AVG Duty = 4937%(X100)
7095 23:07:24.727923
7096 23:07:24.728013 ==DQM 1 ==
7097 23:07:24.731123 Final DQM duty delay cell = -4
7098 23:07:24.734388 [-4] MAX Duty = 5093%(X100), DQS PI = 16
7099 23:07:24.738035 [-4] MIN Duty = 4907%(X100), DQS PI = 38
7100 23:07:24.741037 [-4] AVG Duty = 5000%(X100)
7101 23:07:24.741132
7102 23:07:24.744342 CH1 DQM 0 Duty spec in!! Max-Min= 249%
7103 23:07:24.744438
7104 23:07:24.747974 CH1 DQM 1 Duty spec in!! Max-Min= 186%
7105 23:07:24.751238 [DutyScan_Calibration_Flow] ====Done====
7106 23:07:24.751332
7107 23:07:24.754410 [DutyScan_Calibration_Flow] k_type=2
7108 23:07:24.772207
7109 23:07:24.772311 ==DQ 0 ==
7110 23:07:24.775684 Final DQ duty delay cell = 0
7111 23:07:24.778852 [0] MAX Duty = 5093%(X100), DQS PI = 18
7112 23:07:24.781943 [0] MIN Duty = 4969%(X100), DQS PI = 46
7113 23:07:24.782014 [0] AVG Duty = 5031%(X100)
7114 23:07:24.785714
7115 23:07:24.785809 ==DQ 1 ==
7116 23:07:24.788724 Final DQ duty delay cell = 0
7117 23:07:24.792717 [0] MAX Duty = 5031%(X100), DQS PI = 4
7118 23:07:24.795666 [0] MIN Duty = 4876%(X100), DQS PI = 28
7119 23:07:24.795765 [0] AVG Duty = 4953%(X100)
7120 23:07:24.795854
7121 23:07:24.798643 CH1 DQ 0 Duty spec in!! Max-Min= 124%
7122 23:07:24.801979
7123 23:07:24.805424 CH1 DQ 1 Duty spec in!! Max-Min= 155%
7124 23:07:24.808688 [DutyScan_Calibration_Flow] ====Done====
7125 23:07:24.812003 nWR fixed to 30
7126 23:07:24.812102 [ModeRegInit_LP4] CH0 RK0
7127 23:07:24.815279 [ModeRegInit_LP4] CH0 RK1
7128 23:07:24.818596 [ModeRegInit_LP4] CH1 RK0
7129 23:07:24.822105 [ModeRegInit_LP4] CH1 RK1
7130 23:07:24.822203 match AC timing 4
7131 23:07:24.825704 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 0
7132 23:07:24.831854 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7133 23:07:24.835209 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7134 23:07:24.841713 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7135 23:07:24.845099 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7136 23:07:24.845169 [MiockJmeterHQA]
7137 23:07:24.845229
7138 23:07:24.848467 [DramcMiockJmeter] u1RxGatingPI = 0
7139 23:07:24.851598 0 : 4253, 4026
7140 23:07:24.851698 4 : 4252, 4027
7141 23:07:24.855063 8 : 4363, 4137
7142 23:07:24.855141 12 : 4252, 4027
7143 23:07:24.855233 16 : 4252, 4027
7144 23:07:24.858391 20 : 4252, 4027
7145 23:07:24.858486 24 : 4363, 4137
7146 23:07:24.861633 28 : 4253, 4026
7147 23:07:24.861716 32 : 4258, 4031
7148 23:07:24.864882 36 : 4250, 4027
7149 23:07:24.864982 40 : 4363, 4138
7150 23:07:24.868255 44 : 4250, 4027
7151 23:07:24.868352 48 : 4361, 4137
7152 23:07:24.868447 52 : 4250, 4027
7153 23:07:24.871542 56 : 4250, 4026
7154 23:07:24.871615 60 : 4250, 4027
7155 23:07:24.875085 64 : 4250, 4027
7156 23:07:24.875191 68 : 4361, 4137
7157 23:07:24.878230 72 : 4250, 4027
7158 23:07:24.878329 76 : 4360, 4138
7159 23:07:24.881446 80 : 4250, 4027
7160 23:07:24.881517 84 : 4250, 4027
7161 23:07:24.881577 88 : 4250, 4026
7162 23:07:24.885012 92 : 4360, 4138
7163 23:07:24.885108 96 : 4250, 4027
7164 23:07:24.888312 100 : 4361, 2987
7165 23:07:24.888410 104 : 4360, 0
7166 23:07:24.891282 108 : 4250, 0
7167 23:07:24.891371 112 : 4250, 0
7168 23:07:24.891437 116 : 4361, 0
7169 23:07:24.894647 120 : 4361, 0
7170 23:07:24.894729 124 : 4360, 0
7171 23:07:24.894796 128 : 4249, 0
7172 23:07:24.898175 132 : 4250, 0
7173 23:07:24.898258 136 : 4250, 0
7174 23:07:24.901370 140 : 4250, 0
7175 23:07:24.901452 144 : 4250, 0
7176 23:07:24.901518 148 : 4250, 0
7177 23:07:24.904816 152 : 4250, 0
7178 23:07:24.904898 156 : 4360, 0
7179 23:07:24.908702 160 : 4361, 0
7180 23:07:24.908822 164 : 4250, 0
7181 23:07:24.908889 168 : 4250, 0
7182 23:07:24.911373 172 : 4361, 0
7183 23:07:24.911455 176 : 4360, 0
7184 23:07:24.914625 180 : 4250, 0
7185 23:07:24.914707 184 : 4250, 0
7186 23:07:24.914773 188 : 4250, 0
7187 23:07:24.917788 192 : 4250, 0
7188 23:07:24.917872 196 : 4250, 0
7189 23:07:24.921139 200 : 4361, 0
7190 23:07:24.921221 204 : 4250, 0
7191 23:07:24.921287 208 : 4360, 0
7192 23:07:24.924434 212 : 4361, 0
7193 23:07:24.924516 216 : 4247, 0
7194 23:07:24.927952 220 : 4250, 310
7195 23:07:24.928035 224 : 4360, 4090
7196 23:07:24.928100 228 : 4250, 4027
7197 23:07:24.931418 232 : 4250, 4026
7198 23:07:24.931501 236 : 4250, 4027
7199 23:07:24.934609 240 : 4250, 4027
7200 23:07:24.934691 244 : 4250, 4026
7201 23:07:24.937719 248 : 4250, 4027
7202 23:07:24.937802 252 : 4252, 4027
7203 23:07:24.941057 256 : 4250, 4027
7204 23:07:24.941139 260 : 4250, 4027
7205 23:07:24.944302 264 : 4250, 4027
7206 23:07:24.944384 268 : 4360, 4138
7207 23:07:24.947503 272 : 4250, 4027
7208 23:07:24.947586 276 : 4360, 4137
7209 23:07:24.951262 280 : 4361, 4137
7210 23:07:24.951345 284 : 4250, 4027
7211 23:07:24.951411 288 : 4250, 4027
7212 23:07:24.954150 292 : 4250, 4027
7213 23:07:24.954233 296 : 4250, 4027
7214 23:07:24.957632 300 : 4250, 4027
7215 23:07:24.957715 304 : 4250, 4027
7216 23:07:24.960968 308 : 4250, 4027
7217 23:07:24.961050 312 : 4250, 4026
7218 23:07:24.964207 316 : 4361, 4137
7219 23:07:24.964289 320 : 4360, 4138
7220 23:07:24.967785 324 : 4247, 4024
7221 23:07:24.967868 328 : 4360, 4137
7222 23:07:24.970777 332 : 4361, 4137
7223 23:07:24.970859 336 : 4250, 3983
7224 23:07:24.974055 340 : 4250, 2099
7225 23:07:24.974138
7226 23:07:24.974202 MIOCK jitter meter ch=0
7227 23:07:24.974261
7228 23:07:24.977641 1T = (340-104) = 236 dly cells
7229 23:07:24.984087 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7230 23:07:24.984169 ==
7231 23:07:24.987561 Dram Type= 6, Freq= 0, CH_0, rank 0
7232 23:07:24.990656 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7233 23:07:24.990739 ==
7234 23:07:24.997299 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7235 23:07:25.000688 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7236 23:07:25.004090 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7237 23:07:25.010870 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7238 23:07:25.019309 [CA 0] Center 42 (12~72) winsize 61
7239 23:07:25.022506 [CA 1] Center 41 (11~72) winsize 62
7240 23:07:25.026031 [CA 2] Center 37 (7~67) winsize 61
7241 23:07:25.029144 [CA 3] Center 37 (7~67) winsize 61
7242 23:07:25.032596 [CA 4] Center 35 (5~66) winsize 62
7243 23:07:25.035902 [CA 5] Center 35 (5~65) winsize 61
7244 23:07:25.035976
7245 23:07:25.039386 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7246 23:07:25.039467
7247 23:07:25.042443 [CATrainingPosCal] consider 1 rank data
7248 23:07:25.045905 u2DelayCellTimex100 = 275/100 ps
7249 23:07:25.049388 CA0 delay=42 (12~72),Diff = 7 PI (24 cell)
7250 23:07:25.055894 CA1 delay=41 (11~72),Diff = 6 PI (21 cell)
7251 23:07:25.059123 CA2 delay=37 (7~67),Diff = 2 PI (7 cell)
7252 23:07:25.063044 CA3 delay=37 (7~67),Diff = 2 PI (7 cell)
7253 23:07:25.065922 CA4 delay=35 (5~66),Diff = 0 PI (0 cell)
7254 23:07:25.068966 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7255 23:07:25.069047
7256 23:07:25.072442 CA PerBit enable=1, Macro0, CA PI delay=35
7257 23:07:25.072523
7258 23:07:25.075753 [CBTSetCACLKResult] CA Dly = 35
7259 23:07:25.079207 CS Dly: 11 (0~42)
7260 23:07:25.082562 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7261 23:07:25.085606 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7262 23:07:25.085688 ==
7263 23:07:25.089367 Dram Type= 6, Freq= 0, CH_0, rank 1
7264 23:07:25.092646 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7265 23:07:25.095838 ==
7266 23:07:25.098840 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7267 23:07:25.102471 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7268 23:07:25.108926 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7269 23:07:25.112470 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7270 23:07:25.122088 [CA 0] Center 42 (12~73) winsize 62
7271 23:07:25.125195 [CA 1] Center 42 (12~73) winsize 62
7272 23:07:25.129140 [CA 2] Center 38 (9~68) winsize 60
7273 23:07:25.132183 [CA 3] Center 37 (8~67) winsize 60
7274 23:07:25.135442 [CA 4] Center 36 (6~66) winsize 61
7275 23:07:25.138539 [CA 5] Center 36 (6~66) winsize 61
7276 23:07:25.138633
7277 23:07:25.142059 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7278 23:07:25.142126
7279 23:07:25.145135 [CATrainingPosCal] consider 2 rank data
7280 23:07:25.148657 u2DelayCellTimex100 = 275/100 ps
7281 23:07:25.151823 CA0 delay=42 (12~72),Diff = 7 PI (24 cell)
7282 23:07:25.158576 CA1 delay=42 (12~72),Diff = 7 PI (24 cell)
7283 23:07:25.161738 CA2 delay=38 (9~67),Diff = 3 PI (10 cell)
7284 23:07:25.165028 CA3 delay=37 (8~67),Diff = 2 PI (7 cell)
7285 23:07:25.168338 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7286 23:07:25.171576 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7287 23:07:25.171674
7288 23:07:25.174851 CA PerBit enable=1, Macro0, CA PI delay=35
7289 23:07:25.174947
7290 23:07:25.178509 [CBTSetCACLKResult] CA Dly = 35
7291 23:07:25.181508 CS Dly: 11 (0~42)
7292 23:07:25.185079 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7293 23:07:25.188218 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7294 23:07:25.188322
7295 23:07:25.191725 ----->DramcWriteLeveling(PI) begin...
7296 23:07:25.191830 ==
7297 23:07:25.194848 Dram Type= 6, Freq= 0, CH_0, rank 0
7298 23:07:25.201494 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7299 23:07:25.201595 ==
7300 23:07:25.204828 Write leveling (Byte 0): 29 => 29
7301 23:07:25.204915 Write leveling (Byte 1): 26 => 26
7302 23:07:25.208372 DramcWriteLeveling(PI) end<-----
7303 23:07:25.208451
7304 23:07:25.211255 ==
7305 23:07:25.211335 Dram Type= 6, Freq= 0, CH_0, rank 0
7306 23:07:25.218432 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7307 23:07:25.218513 ==
7308 23:07:25.221344 [Gating] SW mode calibration
7309 23:07:25.228208 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7310 23:07:25.231278 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7311 23:07:25.238294 0 12 0 | B1->B0 | 2323 2726 | 0 1 | (0 0) (0 0)
7312 23:07:25.241043 0 12 4 | B1->B0 | 2423 3434 | 1 0 | (0 0) (0 0)
7313 23:07:25.244285 0 12 8 | B1->B0 | 3232 3434 | 1 1 | (0 0) (1 1)
7314 23:07:25.251062 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7315 23:07:25.254643 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7316 23:07:25.257734 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7317 23:07:25.264480 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7318 23:07:25.267664 0 12 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7319 23:07:25.271162 0 13 0 | B1->B0 | 3434 2c2c | 1 0 | (1 1) (0 1)
7320 23:07:25.277324 0 13 4 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (1 0)
7321 23:07:25.280841 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7322 23:07:25.284288 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7323 23:07:25.290697 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7324 23:07:25.293851 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7325 23:07:25.297576 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7326 23:07:25.303842 0 13 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7327 23:07:25.307137 0 14 0 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
7328 23:07:25.310662 0 14 4 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
7329 23:07:25.317115 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7330 23:07:25.320692 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7331 23:07:25.323867 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7332 23:07:25.330511 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7333 23:07:25.334070 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7334 23:07:25.337011 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7335 23:07:25.343492 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7336 23:07:25.346865 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7337 23:07:25.350640 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7338 23:07:25.356727 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7339 23:07:25.359997 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7340 23:07:25.363525 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7341 23:07:25.370098 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7342 23:07:25.373838 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7343 23:07:25.376621 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7344 23:07:25.383083 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7345 23:07:25.386667 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7346 23:07:25.389949 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7347 23:07:25.396621 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7348 23:07:25.399892 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7349 23:07:25.403288 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7350 23:07:25.409633 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7351 23:07:25.413097 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7352 23:07:25.416252 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7353 23:07:25.419568 Total UI for P1: 0, mck2ui 16
7354 23:07:25.422949 best dqsien dly found for B0: ( 1, 0, 30)
7355 23:07:25.426301 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7356 23:07:25.429666 Total UI for P1: 0, mck2ui 16
7357 23:07:25.433052 best dqsien dly found for B1: ( 1, 1, 2)
7358 23:07:25.439339 best DQS0 dly(MCK, UI, PI) = (1, 0, 30)
7359 23:07:25.442597 best DQS1 dly(MCK, UI, PI) = (1, 1, 2)
7360 23:07:25.442677
7361 23:07:25.446145 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 30)
7362 23:07:25.449327 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 2)
7363 23:07:25.452628 [Gating] SW calibration Done
7364 23:07:25.452732 ==
7365 23:07:25.455821 Dram Type= 6, Freq= 0, CH_0, rank 0
7366 23:07:25.459222 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7367 23:07:25.459303 ==
7368 23:07:25.462519 RX Vref Scan: 0
7369 23:07:25.462650
7370 23:07:25.462744 RX Vref 0 -> 0, step: 1
7371 23:07:25.462835
7372 23:07:25.466393 RX Delay 0 -> 252, step: 8
7373 23:07:25.469221 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7374 23:07:25.472373 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7375 23:07:25.479238 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7376 23:07:25.482394 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7377 23:07:25.485706 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7378 23:07:25.488913 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7379 23:07:25.492507 iDelay=200, Bit 6, Center 135 (80 ~ 191) 112
7380 23:07:25.499397 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7381 23:07:25.502505 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
7382 23:07:25.505604 iDelay=200, Bit 9, Center 107 (56 ~ 159) 104
7383 23:07:25.509153 iDelay=200, Bit 10, Center 119 (64 ~ 175) 112
7384 23:07:25.512416 iDelay=200, Bit 11, Center 115 (64 ~ 167) 104
7385 23:07:25.519166 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7386 23:07:25.522234 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7387 23:07:25.525448 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
7388 23:07:25.529101 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7389 23:07:25.529200 ==
7390 23:07:25.532265 Dram Type= 6, Freq= 0, CH_0, rank 0
7391 23:07:25.538822 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7392 23:07:25.538926 ==
7393 23:07:25.539019 DQS Delay:
7394 23:07:25.541917 DQS0 = 0, DQS1 = 0
7395 23:07:25.542014 DQM Delay:
7396 23:07:25.545599 DQM0 = 130, DQM1 = 124
7397 23:07:25.545696 DQ Delay:
7398 23:07:25.548818 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =127
7399 23:07:25.552116 DQ4 =135, DQ5 =119, DQ6 =135, DQ7 =139
7400 23:07:25.555483 DQ8 =115, DQ9 =107, DQ10 =119, DQ11 =115
7401 23:07:25.558967 DQ12 =131, DQ13 =131, DQ14 =139, DQ15 =135
7402 23:07:25.559049
7403 23:07:25.559112
7404 23:07:25.559171 ==
7405 23:07:25.561914 Dram Type= 6, Freq= 0, CH_0, rank 0
7406 23:07:25.568754 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7407 23:07:25.568836 ==
7408 23:07:25.568900
7409 23:07:25.568960
7410 23:07:25.569017 TX Vref Scan disable
7411 23:07:25.571927 == TX Byte 0 ==
7412 23:07:25.575480 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7413 23:07:25.578869 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7414 23:07:25.581888 == TX Byte 1 ==
7415 23:07:25.585391 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7416 23:07:25.588500 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
7417 23:07:25.592001 ==
7418 23:07:25.595421 Dram Type= 6, Freq= 0, CH_0, rank 0
7419 23:07:25.598506 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7420 23:07:25.598609 ==
7421 23:07:25.610591
7422 23:07:25.613932 TX Vref early break, caculate TX vref
7423 23:07:25.617196 TX Vref=16, minBit 8, minWin=22, winSum=370
7424 23:07:25.620538 TX Vref=18, minBit 9, minWin=22, winSum=378
7425 23:07:25.624305 TX Vref=20, minBit 9, minWin=22, winSum=386
7426 23:07:25.627343 TX Vref=22, minBit 9, minWin=23, winSum=395
7427 23:07:25.630620 TX Vref=24, minBit 8, minWin=24, winSum=404
7428 23:07:25.637074 TX Vref=26, minBit 8, minWin=25, winSum=414
7429 23:07:25.640637 TX Vref=28, minBit 0, minWin=25, winSum=410
7430 23:07:25.643692 TX Vref=30, minBit 6, minWin=24, winSum=405
7431 23:07:25.647029 TX Vref=32, minBit 3, minWin=24, winSum=397
7432 23:07:25.650445 TX Vref=34, minBit 8, minWin=23, winSum=386
7433 23:07:25.657178 [TxChooseVref] Worse bit 8, Min win 25, Win sum 414, Final Vref 26
7434 23:07:25.657277
7435 23:07:25.660740 Final TX Range 0 Vref 26
7436 23:07:25.660827
7437 23:07:25.660888 ==
7438 23:07:25.663886 Dram Type= 6, Freq= 0, CH_0, rank 0
7439 23:07:25.667136 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7440 23:07:25.667240 ==
7441 23:07:25.667329
7442 23:07:25.667426
7443 23:07:25.670154 TX Vref Scan disable
7444 23:07:25.677027 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7445 23:07:25.677104 == TX Byte 0 ==
7446 23:07:25.680526 u2DelayCellOfst[0]=14 cells (4 PI)
7447 23:07:25.683844 u2DelayCellOfst[1]=21 cells (6 PI)
7448 23:07:25.686878 u2DelayCellOfst[2]=14 cells (4 PI)
7449 23:07:25.690447 u2DelayCellOfst[3]=14 cells (4 PI)
7450 23:07:25.693664 u2DelayCellOfst[4]=10 cells (3 PI)
7451 23:07:25.696731 u2DelayCellOfst[5]=0 cells (0 PI)
7452 23:07:25.700184 u2DelayCellOfst[6]=21 cells (6 PI)
7453 23:07:25.703441 u2DelayCellOfst[7]=21 cells (6 PI)
7454 23:07:25.706847 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7455 23:07:25.710076 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7456 23:07:25.713446 == TX Byte 1 ==
7457 23:07:25.716894 u2DelayCellOfst[8]=3 cells (1 PI)
7458 23:07:25.716966 u2DelayCellOfst[9]=0 cells (0 PI)
7459 23:07:25.720103 u2DelayCellOfst[10]=10 cells (3 PI)
7460 23:07:25.723614 u2DelayCellOfst[11]=3 cells (1 PI)
7461 23:07:25.726777 u2DelayCellOfst[12]=17 cells (5 PI)
7462 23:07:25.730041 u2DelayCellOfst[13]=17 cells (5 PI)
7463 23:07:25.733234 u2DelayCellOfst[14]=17 cells (5 PI)
7464 23:07:25.736402 u2DelayCellOfst[15]=14 cells (4 PI)
7465 23:07:25.739650 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
7466 23:07:25.746582 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
7467 23:07:25.746688 DramC Write-DBI on
7468 23:07:25.746781 ==
7469 23:07:25.749839 Dram Type= 6, Freq= 0, CH_0, rank 0
7470 23:07:25.756355 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7471 23:07:25.756463 ==
7472 23:07:25.756554
7473 23:07:25.756647
7474 23:07:25.756740 TX Vref Scan disable
7475 23:07:25.760672 == TX Byte 0 ==
7476 23:07:25.763731 Update DQM dly =728 (2 ,6, 24) DQM OEN =(3 ,3)
7477 23:07:25.767220 == TX Byte 1 ==
7478 23:07:25.770337 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
7479 23:07:25.773752 DramC Write-DBI off
7480 23:07:25.773857
7481 23:07:25.773946 [DATLAT]
7482 23:07:25.774039 Freq=1600, CH0 RK0
7483 23:07:25.774130
7484 23:07:25.776960 DATLAT Default: 0xf
7485 23:07:25.777042 0, 0xFFFF, sum = 0
7486 23:07:25.780218 1, 0xFFFF, sum = 0
7487 23:07:25.780331 2, 0xFFFF, sum = 0
7488 23:07:25.783567 3, 0xFFFF, sum = 0
7489 23:07:25.786902 4, 0xFFFF, sum = 0
7490 23:07:25.787012 5, 0xFFFF, sum = 0
7491 23:07:25.790547 6, 0xFFFF, sum = 0
7492 23:07:25.790648 7, 0xFFFF, sum = 0
7493 23:07:25.793588 8, 0xFFFF, sum = 0
7494 23:07:25.793672 9, 0xFFFF, sum = 0
7495 23:07:25.797071 10, 0xFFFF, sum = 0
7496 23:07:25.797183 11, 0xFFFF, sum = 0
7497 23:07:25.800358 12, 0xFFF, sum = 0
7498 23:07:25.800461 13, 0x0, sum = 1
7499 23:07:25.803595 14, 0x0, sum = 2
7500 23:07:25.803696 15, 0x0, sum = 3
7501 23:07:25.806778 16, 0x0, sum = 4
7502 23:07:25.806879 best_step = 14
7503 23:07:25.806966
7504 23:07:25.807062 ==
7505 23:07:25.810129 Dram Type= 6, Freq= 0, CH_0, rank 0
7506 23:07:25.813284 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7507 23:07:25.816654 ==
7508 23:07:25.816781 RX Vref Scan: 1
7509 23:07:25.816846
7510 23:07:25.819812 Set Vref Range= 24 -> 127
7511 23:07:25.819906
7512 23:07:25.819971 RX Vref 24 -> 127, step: 1
7513 23:07:25.823331
7514 23:07:25.823429 RX Delay 11 -> 252, step: 4
7515 23:07:25.823521
7516 23:07:25.826494 Set Vref, RX VrefLevel [Byte0]: 24
7517 23:07:25.830030 [Byte1]: 24
7518 23:07:25.833601
7519 23:07:25.833677 Set Vref, RX VrefLevel [Byte0]: 25
7520 23:07:25.836738 [Byte1]: 25
7521 23:07:25.841447
7522 23:07:25.841522 Set Vref, RX VrefLevel [Byte0]: 26
7523 23:07:25.844449 [Byte1]: 26
7524 23:07:25.848942
7525 23:07:25.849040 Set Vref, RX VrefLevel [Byte0]: 27
7526 23:07:25.852191 [Byte1]: 27
7527 23:07:25.856440
7528 23:07:25.856538 Set Vref, RX VrefLevel [Byte0]: 28
7529 23:07:25.859578 [Byte1]: 28
7530 23:07:25.863948
7531 23:07:25.864042 Set Vref, RX VrefLevel [Byte0]: 29
7532 23:07:25.867208 [Byte1]: 29
7533 23:07:25.871653
7534 23:07:25.871745 Set Vref, RX VrefLevel [Byte0]: 30
7535 23:07:25.875569 [Byte1]: 30
7536 23:07:25.879657
7537 23:07:25.879754 Set Vref, RX VrefLevel [Byte0]: 31
7538 23:07:25.882672 [Byte1]: 31
7539 23:07:25.887103
7540 23:07:25.887199 Set Vref, RX VrefLevel [Byte0]: 32
7541 23:07:25.890127 [Byte1]: 32
7542 23:07:25.894408
7543 23:07:25.897600 Set Vref, RX VrefLevel [Byte0]: 33
7544 23:07:25.897687 [Byte1]: 33
7545 23:07:25.902186
7546 23:07:25.902289 Set Vref, RX VrefLevel [Byte0]: 34
7547 23:07:25.905245 [Byte1]: 34
7548 23:07:25.909811
7549 23:07:25.909914 Set Vref, RX VrefLevel [Byte0]: 35
7550 23:07:25.913097 [Byte1]: 35
7551 23:07:25.917390
7552 23:07:25.917485 Set Vref, RX VrefLevel [Byte0]: 36
7553 23:07:25.920585 [Byte1]: 36
7554 23:07:25.925436
7555 23:07:25.925539 Set Vref, RX VrefLevel [Byte0]: 37
7556 23:07:25.928198 [Byte1]: 37
7557 23:07:25.932477
7558 23:07:25.932552 Set Vref, RX VrefLevel [Byte0]: 38
7559 23:07:25.936242 [Byte1]: 38
7560 23:07:25.940225
7561 23:07:25.940321 Set Vref, RX VrefLevel [Byte0]: 39
7562 23:07:25.943902 [Byte1]: 39
7563 23:07:25.947658
7564 23:07:25.947755 Set Vref, RX VrefLevel [Byte0]: 40
7565 23:07:25.951199 [Byte1]: 40
7566 23:07:25.955276
7567 23:07:25.955372 Set Vref, RX VrefLevel [Byte0]: 41
7568 23:07:25.958661 [Byte1]: 41
7569 23:07:25.962960
7570 23:07:25.963028 Set Vref, RX VrefLevel [Byte0]: 42
7571 23:07:25.966366 [Byte1]: 42
7572 23:07:25.970699
7573 23:07:25.970793 Set Vref, RX VrefLevel [Byte0]: 43
7574 23:07:25.974152 [Byte1]: 43
7575 23:07:25.978193
7576 23:07:25.978292 Set Vref, RX VrefLevel [Byte0]: 44
7577 23:07:25.981604 [Byte1]: 44
7578 23:07:25.985794
7579 23:07:25.985889 Set Vref, RX VrefLevel [Byte0]: 45
7580 23:07:25.989071 [Byte1]: 45
7581 23:07:25.993225
7582 23:07:25.996823 Set Vref, RX VrefLevel [Byte0]: 46
7583 23:07:25.996897 [Byte1]: 46
7584 23:07:26.001336
7585 23:07:26.001435 Set Vref, RX VrefLevel [Byte0]: 47
7586 23:07:26.004324 [Byte1]: 47
7587 23:07:26.008647
7588 23:07:26.008782 Set Vref, RX VrefLevel [Byte0]: 48
7589 23:07:26.011865 [Byte1]: 48
7590 23:07:26.016446
7591 23:07:26.016540 Set Vref, RX VrefLevel [Byte0]: 49
7592 23:07:26.019618 [Byte1]: 49
7593 23:07:26.023806
7594 23:07:26.023878 Set Vref, RX VrefLevel [Byte0]: 50
7595 23:07:26.027193 [Byte1]: 50
7596 23:07:26.031593
7597 23:07:26.031692 Set Vref, RX VrefLevel [Byte0]: 51
7598 23:07:26.035240 [Byte1]: 51
7599 23:07:26.039295
7600 23:07:26.039396 Set Vref, RX VrefLevel [Byte0]: 52
7601 23:07:26.042717 [Byte1]: 52
7602 23:07:26.046571
7603 23:07:26.046668 Set Vref, RX VrefLevel [Byte0]: 53
7604 23:07:26.049976 [Byte1]: 53
7605 23:07:26.054503
7606 23:07:26.054600 Set Vref, RX VrefLevel [Byte0]: 54
7607 23:07:26.057692 [Byte1]: 54
7608 23:07:26.062186
7609 23:07:26.062256 Set Vref, RX VrefLevel [Byte0]: 55
7610 23:07:26.065248 [Byte1]: 55
7611 23:07:26.069699
7612 23:07:26.069794 Set Vref, RX VrefLevel [Byte0]: 56
7613 23:07:26.072861 [Byte1]: 56
7614 23:07:26.077547
7615 23:07:26.077622 Set Vref, RX VrefLevel [Byte0]: 57
7616 23:07:26.080634 [Byte1]: 57
7617 23:07:26.084830
7618 23:07:26.084901 Set Vref, RX VrefLevel [Byte0]: 58
7619 23:07:26.088058 [Byte1]: 58
7620 23:07:26.092420
7621 23:07:26.092519 Set Vref, RX VrefLevel [Byte0]: 59
7622 23:07:26.095875 [Byte1]: 59
7623 23:07:26.099932
7624 23:07:26.100029 Set Vref, RX VrefLevel [Byte0]: 60
7625 23:07:26.103130 [Byte1]: 60
7626 23:07:26.107526
7627 23:07:26.107626 Set Vref, RX VrefLevel [Byte0]: 61
7628 23:07:26.110940 [Byte1]: 61
7629 23:07:26.115655
7630 23:07:26.115759 Set Vref, RX VrefLevel [Byte0]: 62
7631 23:07:26.118780 [Byte1]: 62
7632 23:07:26.123058
7633 23:07:26.123162 Set Vref, RX VrefLevel [Byte0]: 63
7634 23:07:26.126569 [Byte1]: 63
7635 23:07:26.130716
7636 23:07:26.130796 Set Vref, RX VrefLevel [Byte0]: 64
7637 23:07:26.133906 [Byte1]: 64
7638 23:07:26.138601
7639 23:07:26.138684 Set Vref, RX VrefLevel [Byte0]: 65
7640 23:07:26.141417 [Byte1]: 65
7641 23:07:26.145742
7642 23:07:26.145823 Set Vref, RX VrefLevel [Byte0]: 66
7643 23:07:26.149194 [Byte1]: 66
7644 23:07:26.153690
7645 23:07:26.153771 Set Vref, RX VrefLevel [Byte0]: 67
7646 23:07:26.156636 [Byte1]: 67
7647 23:07:26.161120
7648 23:07:26.161201 Set Vref, RX VrefLevel [Byte0]: 68
7649 23:07:26.164162 [Byte1]: 68
7650 23:07:26.168486
7651 23:07:26.168568 Set Vref, RX VrefLevel [Byte0]: 69
7652 23:07:26.171721 [Byte1]: 69
7653 23:07:26.176308
7654 23:07:26.176388 Set Vref, RX VrefLevel [Byte0]: 70
7655 23:07:26.179412 [Byte1]: 70
7656 23:07:26.183829
7657 23:07:26.183910 Set Vref, RX VrefLevel [Byte0]: 71
7658 23:07:26.187439 [Byte1]: 71
7659 23:07:26.191180
7660 23:07:26.191260 Set Vref, RX VrefLevel [Byte0]: 72
7661 23:07:26.194655 [Byte1]: 72
7662 23:07:26.199218
7663 23:07:26.199317 Set Vref, RX VrefLevel [Byte0]: 73
7664 23:07:26.202179 [Byte1]: 73
7665 23:07:26.206580
7666 23:07:26.206661 Final RX Vref Byte 0 = 54 to rank0
7667 23:07:26.210347 Final RX Vref Byte 1 = 56 to rank0
7668 23:07:26.213085 Final RX Vref Byte 0 = 54 to rank1
7669 23:07:26.216650 Final RX Vref Byte 1 = 56 to rank1==
7670 23:07:26.219962 Dram Type= 6, Freq= 0, CH_0, rank 0
7671 23:07:26.226609 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7672 23:07:26.226691 ==
7673 23:07:26.226756 DQS Delay:
7674 23:07:26.226816 DQS0 = 0, DQS1 = 0
7675 23:07:26.230328 DQM Delay:
7676 23:07:26.230409 DQM0 = 126, DQM1 = 121
7677 23:07:26.233510 DQ Delay:
7678 23:07:26.236334 DQ0 =122, DQ1 =128, DQ2 =124, DQ3 =122
7679 23:07:26.240031 DQ4 =130, DQ5 =116, DQ6 =136, DQ7 =134
7680 23:07:26.243504 DQ8 =112, DQ9 =104, DQ10 =120, DQ11 =112
7681 23:07:26.246435 DQ12 =126, DQ13 =126, DQ14 =136, DQ15 =134
7682 23:07:26.246517
7683 23:07:26.246581
7684 23:07:26.246640
7685 23:07:26.250055 [DramC_TX_OE_Calibration] TA2
7686 23:07:26.253326 Original DQ_B0 (3 6) =30, OEN = 27
7687 23:07:26.256261 Original DQ_B1 (3 6) =30, OEN = 27
7688 23:07:26.259649 24, 0x0, End_B0=24 End_B1=24
7689 23:07:26.259731 25, 0x0, End_B0=25 End_B1=25
7690 23:07:26.263019 26, 0x0, End_B0=26 End_B1=26
7691 23:07:26.266474 27, 0x0, End_B0=27 End_B1=27
7692 23:07:26.269698 28, 0x0, End_B0=28 End_B1=28
7693 23:07:26.269814 29, 0x0, End_B0=29 End_B1=29
7694 23:07:26.273166 30, 0x0, End_B0=30 End_B1=30
7695 23:07:26.276357 31, 0x4141, End_B0=30 End_B1=30
7696 23:07:26.279500 Byte0 end_step=30 best_step=27
7697 23:07:26.282828 Byte1 end_step=30 best_step=27
7698 23:07:26.286275 Byte0 TX OE(2T, 0.5T) = (3, 3)
7699 23:07:26.289553 Byte1 TX OE(2T, 0.5T) = (3, 3)
7700 23:07:26.289634
7701 23:07:26.289698
7702 23:07:26.296192 [DQSOSCAuto] RK0, (LSB)MR18= 0x1f1f, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 394 ps
7703 23:07:26.299392 CH0 RK0: MR19=303, MR18=1F1F
7704 23:07:26.306251 CH0_RK0: MR19=0x303, MR18=0x1F1F, DQSOSC=394, MR23=63, INC=23, DEC=15
7705 23:07:26.306333
7706 23:07:26.309422 ----->DramcWriteLeveling(PI) begin...
7707 23:07:26.309539 ==
7708 23:07:26.312549 Dram Type= 6, Freq= 0, CH_0, rank 1
7709 23:07:26.315854 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7710 23:07:26.315937 ==
7711 23:07:26.319150 Write leveling (Byte 0): 30 => 30
7712 23:07:26.322774 Write leveling (Byte 1): 27 => 27
7713 23:07:26.325906 DramcWriteLeveling(PI) end<-----
7714 23:07:26.325987
7715 23:07:26.326051 ==
7716 23:07:26.329286 Dram Type= 6, Freq= 0, CH_0, rank 1
7717 23:07:26.332593 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7718 23:07:26.332675 ==
7719 23:07:26.335795 [Gating] SW mode calibration
7720 23:07:26.342502 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7721 23:07:26.349118 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7722 23:07:26.352588 0 12 0 | B1->B0 | 2323 3131 | 0 1 | (0 0) (1 1)
7723 23:07:26.356020 0 12 4 | B1->B0 | 2929 3434 | 0 1 | (0 0) (1 1)
7724 23:07:26.362553 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7725 23:07:26.365808 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7726 23:07:26.368982 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7727 23:07:26.375725 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7728 23:07:26.379124 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7729 23:07:26.382502 0 12 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7730 23:07:26.389234 0 13 0 | B1->B0 | 3434 2b2b | 1 1 | (1 1) (1 0)
7731 23:07:26.392619 0 13 4 | B1->B0 | 2d2d 2323 | 1 0 | (1 0) (0 0)
7732 23:07:26.396018 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7733 23:07:26.402386 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7734 23:07:26.405344 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7735 23:07:26.408714 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7736 23:07:26.415521 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7737 23:07:26.418739 0 13 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7738 23:07:26.421978 0 14 0 | B1->B0 | 2323 4343 | 0 0 | (0 0) (0 0)
7739 23:07:26.428660 0 14 4 | B1->B0 | 3131 4646 | 1 0 | (0 0) (0 0)
7740 23:07:26.432076 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7741 23:07:26.435403 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7742 23:07:26.441924 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7743 23:07:26.445526 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7744 23:07:26.448681 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7745 23:07:26.455338 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7746 23:07:26.458708 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7747 23:07:26.461912 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7748 23:07:26.469035 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7749 23:07:26.471666 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7750 23:07:26.474979 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7751 23:07:26.481622 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7752 23:07:26.485209 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7753 23:07:26.488260 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7754 23:07:26.494701 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7755 23:07:26.498045 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7756 23:07:26.501319 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7757 23:07:26.508086 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7758 23:07:26.511316 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7759 23:07:26.514988 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7760 23:07:26.521330 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7761 23:07:26.524470 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7762 23:07:26.528157 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7763 23:07:26.534518 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7764 23:07:26.534600 Total UI for P1: 0, mck2ui 16
7765 23:07:26.541680 best dqsien dly found for B0: ( 1, 0, 30)
7766 23:07:26.544843 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7767 23:07:26.547857 Total UI for P1: 0, mck2ui 16
7768 23:07:26.551323 best dqsien dly found for B1: ( 1, 1, 2)
7769 23:07:26.554505 best DQS0 dly(MCK, UI, PI) = (1, 0, 30)
7770 23:07:26.557927 best DQS1 dly(MCK, UI, PI) = (1, 1, 2)
7771 23:07:26.558009
7772 23:07:26.560885 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 30)
7773 23:07:26.564393 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 2)
7774 23:07:26.567529 [Gating] SW calibration Done
7775 23:07:26.567618 ==
7776 23:07:26.571010 Dram Type= 6, Freq= 0, CH_0, rank 1
7777 23:07:26.574638 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7778 23:07:26.574721 ==
7779 23:07:26.577531 RX Vref Scan: 0
7780 23:07:26.577616
7781 23:07:26.581015 RX Vref 0 -> 0, step: 1
7782 23:07:26.581096
7783 23:07:26.581190 RX Delay 0 -> 252, step: 8
7784 23:07:26.587350 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7785 23:07:26.590910 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7786 23:07:26.593997 iDelay=200, Bit 2, Center 131 (72 ~ 191) 120
7787 23:07:26.597282 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7788 23:07:26.600816 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
7789 23:07:26.607395 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7790 23:07:26.610624 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7791 23:07:26.614089 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7792 23:07:26.617328 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7793 23:07:26.620249 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7794 23:07:26.627005 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7795 23:07:26.630169 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7796 23:07:26.633552 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7797 23:07:26.636858 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7798 23:07:26.643612 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7799 23:07:26.646903 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7800 23:07:26.646984 ==
7801 23:07:26.650030 Dram Type= 6, Freq= 0, CH_0, rank 1
7802 23:07:26.653254 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7803 23:07:26.653336 ==
7804 23:07:26.656690 DQS Delay:
7805 23:07:26.656811 DQS0 = 0, DQS1 = 0
7806 23:07:26.656876 DQM Delay:
7807 23:07:26.660095 DQM0 = 130, DQM1 = 124
7808 23:07:26.660176 DQ Delay:
7809 23:07:26.663208 DQ0 =127, DQ1 =131, DQ2 =131, DQ3 =127
7810 23:07:26.666570 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =139
7811 23:07:26.673375 DQ8 =111, DQ9 =111, DQ10 =123, DQ11 =119
7812 23:07:26.676669 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =131
7813 23:07:26.676800
7814 23:07:26.676865
7815 23:07:26.676925 ==
7816 23:07:26.679810 Dram Type= 6, Freq= 0, CH_0, rank 1
7817 23:07:26.683226 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7818 23:07:26.683308 ==
7819 23:07:26.683372
7820 23:07:26.683432
7821 23:07:26.686208 TX Vref Scan disable
7822 23:07:26.689626 == TX Byte 0 ==
7823 23:07:26.693315 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7824 23:07:26.696322 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7825 23:07:26.699672 == TX Byte 1 ==
7826 23:07:26.703158 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7827 23:07:26.706258 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7828 23:07:26.706339 ==
7829 23:07:26.709592 Dram Type= 6, Freq= 0, CH_0, rank 1
7830 23:07:26.712821 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7831 23:07:26.712929 ==
7832 23:07:26.727194
7833 23:07:26.730626 TX Vref early break, caculate TX vref
7834 23:07:26.733646 TX Vref=16, minBit 8, minWin=22, winSum=377
7835 23:07:26.736944 TX Vref=18, minBit 1, minWin=23, winSum=384
7836 23:07:26.740455 TX Vref=20, minBit 8, minWin=23, winSum=393
7837 23:07:26.743776 TX Vref=22, minBit 1, minWin=24, winSum=398
7838 23:07:26.746986 TX Vref=24, minBit 0, minWin=25, winSum=409
7839 23:07:26.753631 TX Vref=26, minBit 1, minWin=24, winSum=415
7840 23:07:26.756965 TX Vref=28, minBit 0, minWin=25, winSum=416
7841 23:07:26.760521 TX Vref=30, minBit 8, minWin=24, winSum=410
7842 23:07:26.763475 TX Vref=32, minBit 6, minWin=23, winSum=398
7843 23:07:26.767447 TX Vref=34, minBit 8, minWin=23, winSum=393
7844 23:07:26.773748 [TxChooseVref] Worse bit 0, Min win 25, Win sum 416, Final Vref 28
7845 23:07:26.773836
7846 23:07:26.777080 Final TX Range 0 Vref 28
7847 23:07:26.777162
7848 23:07:26.777226 ==
7849 23:07:26.780536 Dram Type= 6, Freq= 0, CH_0, rank 1
7850 23:07:26.783578 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7851 23:07:26.783661 ==
7852 23:07:26.783725
7853 23:07:26.783784
7854 23:07:26.786556 TX Vref Scan disable
7855 23:07:26.793525 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7856 23:07:26.793607 == TX Byte 0 ==
7857 23:07:26.796879 u2DelayCellOfst[0]=10 cells (3 PI)
7858 23:07:26.799842 u2DelayCellOfst[1]=14 cells (4 PI)
7859 23:07:26.803108 u2DelayCellOfst[2]=7 cells (2 PI)
7860 23:07:26.806808 u2DelayCellOfst[3]=10 cells (3 PI)
7861 23:07:26.809810 u2DelayCellOfst[4]=7 cells (2 PI)
7862 23:07:26.813116 u2DelayCellOfst[5]=0 cells (0 PI)
7863 23:07:26.816478 u2DelayCellOfst[6]=14 cells (4 PI)
7864 23:07:26.819797 u2DelayCellOfst[7]=14 cells (4 PI)
7865 23:07:26.822967 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7866 23:07:26.826504 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7867 23:07:26.829857 == TX Byte 1 ==
7868 23:07:26.832893 u2DelayCellOfst[8]=3 cells (1 PI)
7869 23:07:26.832975 u2DelayCellOfst[9]=0 cells (0 PI)
7870 23:07:26.836203 u2DelayCellOfst[10]=10 cells (3 PI)
7871 23:07:26.839800 u2DelayCellOfst[11]=3 cells (1 PI)
7872 23:07:26.842764 u2DelayCellOfst[12]=14 cells (4 PI)
7873 23:07:26.846069 u2DelayCellOfst[13]=14 cells (4 PI)
7874 23:07:26.849593 u2DelayCellOfst[14]=17 cells (5 PI)
7875 23:07:26.852885 u2DelayCellOfst[15]=14 cells (4 PI)
7876 23:07:26.855966 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
7877 23:07:26.862528 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7878 23:07:26.862610 DramC Write-DBI on
7879 23:07:26.862675 ==
7880 23:07:26.865724 Dram Type= 6, Freq= 0, CH_0, rank 1
7881 23:07:26.872649 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7882 23:07:26.872739 ==
7883 23:07:26.872804
7884 23:07:26.872865
7885 23:07:26.872922 TX Vref Scan disable
7886 23:07:26.876607 == TX Byte 0 ==
7887 23:07:26.879850 Update DQM dly =729 (2 ,6, 25) DQM OEN =(3 ,3)
7888 23:07:26.883200 == TX Byte 1 ==
7889 23:07:26.886707 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
7890 23:07:26.889815 DramC Write-DBI off
7891 23:07:26.889895
7892 23:07:26.889959 [DATLAT]
7893 23:07:26.890019 Freq=1600, CH0 RK1
7894 23:07:26.890094
7895 23:07:26.892995 DATLAT Default: 0xe
7896 23:07:26.893087 0, 0xFFFF, sum = 0
7897 23:07:26.896277 1, 0xFFFF, sum = 0
7898 23:07:26.899927 2, 0xFFFF, sum = 0
7899 23:07:26.900008 3, 0xFFFF, sum = 0
7900 23:07:26.902892 4, 0xFFFF, sum = 0
7901 23:07:26.902975 5, 0xFFFF, sum = 0
7902 23:07:26.906300 6, 0xFFFF, sum = 0
7903 23:07:26.906383 7, 0xFFFF, sum = 0
7904 23:07:26.909663 8, 0xFFFF, sum = 0
7905 23:07:26.909746 9, 0xFFFF, sum = 0
7906 23:07:26.912646 10, 0xFFFF, sum = 0
7907 23:07:26.912783 11, 0xFFFF, sum = 0
7908 23:07:26.916099 12, 0x8FFF, sum = 0
7909 23:07:26.916181 13, 0x0, sum = 1
7910 23:07:26.919680 14, 0x0, sum = 2
7911 23:07:26.919762 15, 0x0, sum = 3
7912 23:07:26.922772 16, 0x0, sum = 4
7913 23:07:26.922854 best_step = 14
7914 23:07:26.922918
7915 23:07:26.922976 ==
7916 23:07:26.926254 Dram Type= 6, Freq= 0, CH_0, rank 1
7917 23:07:26.929573 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7918 23:07:26.932699 ==
7919 23:07:26.932820 RX Vref Scan: 0
7920 23:07:26.932884
7921 23:07:26.936060 RX Vref 0 -> 0, step: 1
7922 23:07:26.936141
7923 23:07:26.939400 RX Delay 11 -> 252, step: 4
7924 23:07:26.943234 iDelay=195, Bit 0, Center 124 (71 ~ 178) 108
7925 23:07:26.945878 iDelay=195, Bit 1, Center 132 (79 ~ 186) 108
7926 23:07:26.949141 iDelay=195, Bit 2, Center 126 (71 ~ 182) 112
7927 23:07:26.955921 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
7928 23:07:26.959134 iDelay=195, Bit 4, Center 132 (79 ~ 186) 108
7929 23:07:26.962404 iDelay=195, Bit 5, Center 120 (67 ~ 174) 108
7930 23:07:26.965528 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
7931 23:07:26.969118 iDelay=195, Bit 7, Center 138 (83 ~ 194) 112
7932 23:07:26.975554 iDelay=195, Bit 8, Center 108 (55 ~ 162) 108
7933 23:07:26.979086 iDelay=195, Bit 9, Center 108 (55 ~ 162) 108
7934 23:07:26.982275 iDelay=195, Bit 10, Center 122 (67 ~ 178) 112
7935 23:07:26.985784 iDelay=195, Bit 11, Center 112 (59 ~ 166) 108
7936 23:07:26.988957 iDelay=195, Bit 12, Center 128 (75 ~ 182) 108
7937 23:07:26.995827 iDelay=195, Bit 13, Center 128 (75 ~ 182) 108
7938 23:07:26.998848 iDelay=195, Bit 14, Center 134 (79 ~ 190) 112
7939 23:07:27.002194 iDelay=195, Bit 15, Center 130 (75 ~ 186) 112
7940 23:07:27.002279 ==
7941 23:07:27.005357 Dram Type= 6, Freq= 0, CH_0, rank 1
7942 23:07:27.009271 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7943 23:07:27.012079 ==
7944 23:07:27.012161 DQS Delay:
7945 23:07:27.012225 DQS0 = 0, DQS1 = 0
7946 23:07:27.015723 DQM Delay:
7947 23:07:27.015804 DQM0 = 129, DQM1 = 121
7948 23:07:27.018745 DQ Delay:
7949 23:07:27.022147 DQ0 =124, DQ1 =132, DQ2 =126, DQ3 =124
7950 23:07:27.025036 DQ4 =132, DQ5 =120, DQ6 =138, DQ7 =138
7951 23:07:27.028417 DQ8 =108, DQ9 =108, DQ10 =122, DQ11 =112
7952 23:07:27.031838 DQ12 =128, DQ13 =128, DQ14 =134, DQ15 =130
7953 23:07:27.031919
7954 23:07:27.031983
7955 23:07:27.032042
7956 23:07:27.034888 [DramC_TX_OE_Calibration] TA2
7957 23:07:27.038651 Original DQ_B0 (3 6) =30, OEN = 27
7958 23:07:27.042104 Original DQ_B1 (3 6) =30, OEN = 27
7959 23:07:27.045506 24, 0x0, End_B0=24 End_B1=24
7960 23:07:27.045588 25, 0x0, End_B0=25 End_B1=25
7961 23:07:27.048373 26, 0x0, End_B0=26 End_B1=26
7962 23:07:27.051554 27, 0x0, End_B0=27 End_B1=27
7963 23:07:27.054769 28, 0x0, End_B0=28 End_B1=28
7964 23:07:27.058163 29, 0x0, End_B0=29 End_B1=29
7965 23:07:27.058246 30, 0x0, End_B0=30 End_B1=30
7966 23:07:27.061936 31, 0x4141, End_B0=30 End_B1=30
7967 23:07:27.064486 Byte0 end_step=30 best_step=27
7968 23:07:27.068002 Byte1 end_step=30 best_step=27
7969 23:07:27.071133 Byte0 TX OE(2T, 0.5T) = (3, 3)
7970 23:07:27.074588 Byte1 TX OE(2T, 0.5T) = (3, 3)
7971 23:07:27.074688
7972 23:07:27.074777
7973 23:07:27.081211 [DQSOSCAuto] RK1, (LSB)MR18= 0x2323, (MSB)MR19= 0x303, tDQSOscB0 = 392 ps tDQSOscB1 = 392 ps
7974 23:07:27.084554 CH0 RK1: MR19=303, MR18=2323
7975 23:07:27.091592 CH0_RK1: MR19=0x303, MR18=0x2323, DQSOSC=392, MR23=63, INC=24, DEC=16
7976 23:07:27.094729 [RxdqsGatingPostProcess] freq 1600
7977 23:07:27.097696 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
7978 23:07:27.101023 Pre-setting of DQS Precalculation
7979 23:07:27.107810 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7980 23:07:27.107890 ==
7981 23:07:27.111028 Dram Type= 6, Freq= 0, CH_1, rank 0
7982 23:07:27.114535 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7983 23:07:27.114615 ==
7984 23:07:27.120822 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7985 23:07:27.124171 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
7986 23:07:27.127622 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
7987 23:07:27.134125 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7988 23:07:27.142349 [CA 0] Center 41 (12~71) winsize 60
7989 23:07:27.146313 [CA 1] Center 40 (10~71) winsize 62
7990 23:07:27.149106 [CA 2] Center 37 (7~67) winsize 61
7991 23:07:27.152313 [CA 3] Center 36 (7~66) winsize 60
7992 23:07:27.155969 [CA 4] Center 34 (4~64) winsize 61
7993 23:07:27.158916 [CA 5] Center 34 (5~64) winsize 60
7994 23:07:27.159019
7995 23:07:27.162076 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7996 23:07:27.162173
7997 23:07:27.165746 [CATrainingPosCal] consider 1 rank data
7998 23:07:27.169061 u2DelayCellTimex100 = 275/100 ps
7999 23:07:27.172164 CA0 delay=41 (12~71),Diff = 7 PI (24 cell)
8000 23:07:27.179074 CA1 delay=40 (10~71),Diff = 6 PI (21 cell)
8001 23:07:27.182185 CA2 delay=37 (7~67),Diff = 3 PI (10 cell)
8002 23:07:27.185621 CA3 delay=36 (7~66),Diff = 2 PI (7 cell)
8003 23:07:27.188884 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
8004 23:07:27.192202 CA5 delay=34 (5~64),Diff = 0 PI (0 cell)
8005 23:07:27.192304
8006 23:07:27.195201 CA PerBit enable=1, Macro0, CA PI delay=34
8007 23:07:27.195276
8008 23:07:27.198584 [CBTSetCACLKResult] CA Dly = 34
8009 23:07:27.201749 CS Dly: 8 (0~39)
8010 23:07:27.205145 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8011 23:07:27.208516 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8012 23:07:27.208618 ==
8013 23:07:27.211764 Dram Type= 6, Freq= 0, CH_1, rank 1
8014 23:07:27.218665 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8015 23:07:27.218743 ==
8016 23:07:27.221861 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8017 23:07:27.228364 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8018 23:07:27.231618 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8019 23:07:27.238225 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8020 23:07:27.244958 [CA 0] Center 40 (10~70) winsize 61
8021 23:07:27.248116 [CA 1] Center 39 (9~70) winsize 62
8022 23:07:27.251753 [CA 2] Center 35 (6~65) winsize 60
8023 23:07:27.254865 [CA 3] Center 35 (6~64) winsize 59
8024 23:07:27.257953 [CA 4] Center 33 (4~62) winsize 59
8025 23:07:27.261661 [CA 5] Center 33 (4~63) winsize 60
8026 23:07:27.261742
8027 23:07:27.264574 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8028 23:07:27.264655
8029 23:07:27.268024 [CATrainingPosCal] consider 2 rank data
8030 23:07:27.271381 u2DelayCellTimex100 = 275/100 ps
8031 23:07:27.274991 CA0 delay=41 (12~70),Diff = 8 PI (28 cell)
8032 23:07:27.281308 CA1 delay=40 (10~70),Diff = 7 PI (24 cell)
8033 23:07:27.284643 CA2 delay=36 (7~65),Diff = 3 PI (10 cell)
8034 23:07:27.288105 CA3 delay=35 (7~64),Diff = 2 PI (7 cell)
8035 23:07:27.291417 CA4 delay=33 (4~62),Diff = 0 PI (0 cell)
8036 23:07:27.294552 CA5 delay=34 (5~63),Diff = 1 PI (3 cell)
8037 23:07:27.294633
8038 23:07:27.297896 CA PerBit enable=1, Macro0, CA PI delay=33
8039 23:07:27.297977
8040 23:07:27.301037 [CBTSetCACLKResult] CA Dly = 33
8041 23:07:27.304490 CS Dly: 9 (0~41)
8042 23:07:27.307823 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8043 23:07:27.311011 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8044 23:07:27.311125
8045 23:07:27.314560 ----->DramcWriteLeveling(PI) begin...
8046 23:07:27.314643 ==
8047 23:07:27.318154 Dram Type= 6, Freq= 0, CH_1, rank 0
8048 23:07:27.324387 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8049 23:07:27.324469 ==
8050 23:07:27.327574 Write leveling (Byte 0): 24 => 24
8051 23:07:27.327656 Write leveling (Byte 1): 22 => 22
8052 23:07:27.330868 DramcWriteLeveling(PI) end<-----
8053 23:07:27.330949
8054 23:07:27.331013 ==
8055 23:07:27.334599 Dram Type= 6, Freq= 0, CH_1, rank 0
8056 23:07:27.341094 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8057 23:07:27.341175 ==
8058 23:07:27.344256 [Gating] SW mode calibration
8059 23:07:27.351109 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8060 23:07:27.354238 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8061 23:07:27.361194 0 12 0 | B1->B0 | 2727 3434 | 0 1 | (0 0) (1 1)
8062 23:07:27.364068 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8063 23:07:27.367479 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8064 23:07:27.374304 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8065 23:07:27.377152 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8066 23:07:27.380674 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8067 23:07:27.387232 0 12 24 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
8068 23:07:27.390729 0 12 28 | B1->B0 | 3434 2929 | 1 0 | (1 0) (1 0)
8069 23:07:27.393769 0 13 0 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (1 0)
8070 23:07:27.400330 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8071 23:07:27.403845 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8072 23:07:27.407232 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8073 23:07:27.413767 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8074 23:07:27.416981 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8075 23:07:27.420281 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8076 23:07:27.427034 0 13 28 | B1->B0 | 2323 3a3a | 0 0 | (0 0) (0 0)
8077 23:07:27.430127 0 14 0 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
8078 23:07:27.433709 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8079 23:07:27.440335 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8080 23:07:27.443391 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8081 23:07:27.446965 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8082 23:07:27.450324 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8083 23:07:27.456709 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8084 23:07:27.459925 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8085 23:07:27.463406 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8086 23:07:27.469938 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8087 23:07:27.473838 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8088 23:07:27.476820 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8089 23:07:27.483220 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8090 23:07:27.486498 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8091 23:07:27.489883 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8092 23:07:27.497020 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8093 23:07:27.499840 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8094 23:07:27.503101 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8095 23:07:27.510185 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8096 23:07:27.513190 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8097 23:07:27.516383 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8098 23:07:27.523126 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8099 23:07:27.526195 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8100 23:07:27.529913 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8101 23:07:27.536284 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8102 23:07:27.539402 Total UI for P1: 0, mck2ui 16
8103 23:07:27.542647 best dqsien dly found for B0: ( 1, 0, 26)
8104 23:07:27.546157 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8105 23:07:27.549717 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8106 23:07:27.552764 Total UI for P1: 0, mck2ui 16
8107 23:07:27.556216 best dqsien dly found for B1: ( 1, 1, 2)
8108 23:07:27.559408 best DQS0 dly(MCK, UI, PI) = (1, 0, 26)
8109 23:07:27.562797 best DQS1 dly(MCK, UI, PI) = (1, 1, 2)
8110 23:07:27.562879
8111 23:07:27.569678 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 26)
8112 23:07:27.572622 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 2)
8113 23:07:27.572702 [Gating] SW calibration Done
8114 23:07:27.576122 ==
8115 23:07:27.579382 Dram Type= 6, Freq= 0, CH_1, rank 0
8116 23:07:27.582441 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8117 23:07:27.582523 ==
8118 23:07:27.582588 RX Vref Scan: 0
8119 23:07:27.582648
8120 23:07:27.585827 RX Vref 0 -> 0, step: 1
8121 23:07:27.585908
8122 23:07:27.589246 RX Delay 0 -> 252, step: 8
8123 23:07:27.592918 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8124 23:07:27.595771 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8125 23:07:27.599474 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8126 23:07:27.605722 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8127 23:07:27.609177 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8128 23:07:27.612222 iDelay=200, Bit 5, Center 139 (80 ~ 199) 120
8129 23:07:27.615900 iDelay=200, Bit 6, Center 135 (80 ~ 191) 112
8130 23:07:27.619274 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8131 23:07:27.625739 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8132 23:07:27.629100 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8133 23:07:27.632506 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8134 23:07:27.635628 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8135 23:07:27.638872 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8136 23:07:27.645611 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8137 23:07:27.649014 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8138 23:07:27.652120 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8139 23:07:27.652200 ==
8140 23:07:27.655574 Dram Type= 6, Freq= 0, CH_1, rank 0
8141 23:07:27.658911 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8142 23:07:27.662277 ==
8143 23:07:27.662358 DQS Delay:
8144 23:07:27.662422 DQS0 = 0, DQS1 = 0
8145 23:07:27.665504 DQM Delay:
8146 23:07:27.665585 DQM0 = 130, DQM1 = 126
8147 23:07:27.668823 DQ Delay:
8148 23:07:27.672197 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =127
8149 23:07:27.675388 DQ4 =131, DQ5 =139, DQ6 =135, DQ7 =127
8150 23:07:27.678728 DQ8 =107, DQ9 =119, DQ10 =127, DQ11 =115
8151 23:07:27.681921 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8152 23:07:27.682002
8153 23:07:27.682066
8154 23:07:27.682125 ==
8155 23:07:27.685139 Dram Type= 6, Freq= 0, CH_1, rank 0
8156 23:07:27.688588 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8157 23:07:27.688669 ==
8158 23:07:27.691806
8159 23:07:27.691912
8160 23:07:27.692004 TX Vref Scan disable
8161 23:07:27.695140 == TX Byte 0 ==
8162 23:07:27.698819 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8163 23:07:27.701780 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
8164 23:07:27.705536 == TX Byte 1 ==
8165 23:07:27.708620 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8166 23:07:27.711763 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8167 23:07:27.711869 ==
8168 23:07:27.715244 Dram Type= 6, Freq= 0, CH_1, rank 0
8169 23:07:27.721911 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8170 23:07:27.722014 ==
8171 23:07:27.733287
8172 23:07:27.736447 TX Vref early break, caculate TX vref
8173 23:07:27.739542 TX Vref=16, minBit 0, minWin=22, winSum=375
8174 23:07:27.742956 TX Vref=18, minBit 0, minWin=22, winSum=377
8175 23:07:27.746232 TX Vref=20, minBit 0, minWin=24, winSum=393
8176 23:07:27.749502 TX Vref=22, minBit 0, minWin=24, winSum=396
8177 23:07:27.752757 TX Vref=24, minBit 3, minWin=23, winSum=402
8178 23:07:27.759712 TX Vref=26, minBit 1, minWin=25, winSum=413
8179 23:07:27.762708 TX Vref=28, minBit 1, minWin=25, winSum=414
8180 23:07:27.765855 TX Vref=30, minBit 0, minWin=24, winSum=407
8181 23:07:27.769729 TX Vref=32, minBit 5, minWin=23, winSum=398
8182 23:07:27.772564 TX Vref=34, minBit 0, minWin=24, winSum=391
8183 23:07:27.779345 [TxChooseVref] Worse bit 1, Min win 25, Win sum 414, Final Vref 28
8184 23:07:27.779444
8185 23:07:27.782858 Final TX Range 0 Vref 28
8186 23:07:27.782954
8187 23:07:27.783042 ==
8188 23:07:27.785730 Dram Type= 6, Freq= 0, CH_1, rank 0
8189 23:07:27.789085 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8190 23:07:27.789181 ==
8191 23:07:27.789272
8192 23:07:27.789362
8193 23:07:27.792351 TX Vref Scan disable
8194 23:07:27.799327 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8195 23:07:27.799429 == TX Byte 0 ==
8196 23:07:27.802495 u2DelayCellOfst[0]=17 cells (5 PI)
8197 23:07:27.805959 u2DelayCellOfst[1]=10 cells (3 PI)
8198 23:07:27.809344 u2DelayCellOfst[2]=0 cells (0 PI)
8199 23:07:27.812371 u2DelayCellOfst[3]=7 cells (2 PI)
8200 23:07:27.815857 u2DelayCellOfst[4]=7 cells (2 PI)
8201 23:07:27.819589 u2DelayCellOfst[5]=14 cells (4 PI)
8202 23:07:27.822502 u2DelayCellOfst[6]=14 cells (4 PI)
8203 23:07:27.825718 u2DelayCellOfst[7]=7 cells (2 PI)
8204 23:07:27.829082 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8205 23:07:27.832168 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
8206 23:07:27.835473 == TX Byte 1 ==
8207 23:07:27.838796 u2DelayCellOfst[8]=0 cells (0 PI)
8208 23:07:27.838897 u2DelayCellOfst[9]=3 cells (1 PI)
8209 23:07:27.841932 u2DelayCellOfst[10]=10 cells (3 PI)
8210 23:07:27.845428 u2DelayCellOfst[11]=3 cells (1 PI)
8211 23:07:27.848874 u2DelayCellOfst[12]=17 cells (5 PI)
8212 23:07:27.851876 u2DelayCellOfst[13]=21 cells (6 PI)
8213 23:07:27.855154 u2DelayCellOfst[14]=21 cells (6 PI)
8214 23:07:27.858736 u2DelayCellOfst[15]=21 cells (6 PI)
8215 23:07:27.861778 Update DQ dly =973 (3 ,6, 13) DQ OEN =(3 ,3)
8216 23:07:27.868262 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8217 23:07:27.868362 DramC Write-DBI on
8218 23:07:27.868452 ==
8219 23:07:27.871608 Dram Type= 6, Freq= 0, CH_1, rank 0
8220 23:07:27.878210 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8221 23:07:27.878309 ==
8222 23:07:27.878399
8223 23:07:27.878485
8224 23:07:27.878573 TX Vref Scan disable
8225 23:07:27.882359 == TX Byte 0 ==
8226 23:07:27.885952 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8227 23:07:27.888699 == TX Byte 1 ==
8228 23:07:27.892172 Update DQM dly =717 (2 ,6, 13) DQM OEN =(3 ,3)
8229 23:07:27.895538 DramC Write-DBI off
8230 23:07:27.895636
8231 23:07:27.895724 [DATLAT]
8232 23:07:27.895811 Freq=1600, CH1 RK0
8233 23:07:27.895899
8234 23:07:27.898907 DATLAT Default: 0xf
8235 23:07:27.899000 0, 0xFFFF, sum = 0
8236 23:07:27.902183 1, 0xFFFF, sum = 0
8237 23:07:27.905456 2, 0xFFFF, sum = 0
8238 23:07:27.905554 3, 0xFFFF, sum = 0
8239 23:07:27.908582 4, 0xFFFF, sum = 0
8240 23:07:27.908684 5, 0xFFFF, sum = 0
8241 23:07:27.912201 6, 0xFFFF, sum = 0
8242 23:07:27.912307 7, 0xFFFF, sum = 0
8243 23:07:27.915606 8, 0xFFFF, sum = 0
8244 23:07:27.915710 9, 0xFFFF, sum = 0
8245 23:07:27.918792 10, 0xFFFF, sum = 0
8246 23:07:27.918897 11, 0xFFFF, sum = 0
8247 23:07:27.922204 12, 0xF7F, sum = 0
8248 23:07:27.922307 13, 0x0, sum = 1
8249 23:07:27.925445 14, 0x0, sum = 2
8250 23:07:27.925545 15, 0x0, sum = 3
8251 23:07:27.928588 16, 0x0, sum = 4
8252 23:07:27.928688 best_step = 14
8253 23:07:27.928799
8254 23:07:27.928866 ==
8255 23:07:27.931880 Dram Type= 6, Freq= 0, CH_1, rank 0
8256 23:07:27.935449 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8257 23:07:27.938575 ==
8258 23:07:27.938675 RX Vref Scan: 1
8259 23:07:27.938764
8260 23:07:27.941987 Set Vref Range= 24 -> 127
8261 23:07:27.942081
8262 23:07:27.945283 RX Vref 24 -> 127, step: 1
8263 23:07:27.945356
8264 23:07:27.945416 RX Delay 3 -> 252, step: 4
8265 23:07:27.945473
8266 23:07:27.948542 Set Vref, RX VrefLevel [Byte0]: 24
8267 23:07:27.951818 [Byte1]: 24
8268 23:07:27.955510
8269 23:07:27.955608 Set Vref, RX VrefLevel [Byte0]: 25
8270 23:07:27.959042 [Byte1]: 25
8271 23:07:27.963143
8272 23:07:27.963210 Set Vref, RX VrefLevel [Byte0]: 26
8273 23:07:27.966278 [Byte1]: 26
8274 23:07:27.970667
8275 23:07:27.970732 Set Vref, RX VrefLevel [Byte0]: 27
8276 23:07:27.974170 [Byte1]: 27
8277 23:07:27.978622
8278 23:07:27.978720 Set Vref, RX VrefLevel [Byte0]: 28
8279 23:07:27.981904 [Byte1]: 28
8280 23:07:27.986129
8281 23:07:27.986227 Set Vref, RX VrefLevel [Byte0]: 29
8282 23:07:27.989401 [Byte1]: 29
8283 23:07:27.994215
8284 23:07:27.994314 Set Vref, RX VrefLevel [Byte0]: 30
8285 23:07:27.997222 [Byte1]: 30
8286 23:07:28.001435
8287 23:07:28.001506 Set Vref, RX VrefLevel [Byte0]: 31
8288 23:07:28.004619 [Byte1]: 31
8289 23:07:28.009028
8290 23:07:28.009127 Set Vref, RX VrefLevel [Byte0]: 32
8291 23:07:28.012402 [Byte1]: 32
8292 23:07:28.016582
8293 23:07:28.016683 Set Vref, RX VrefLevel [Byte0]: 33
8294 23:07:28.020023 [Byte1]: 33
8295 23:07:28.024466
8296 23:07:28.024562 Set Vref, RX VrefLevel [Byte0]: 34
8297 23:07:28.027816 [Byte1]: 34
8298 23:07:28.032651
8299 23:07:28.032778 Set Vref, RX VrefLevel [Byte0]: 35
8300 23:07:28.035191 [Byte1]: 35
8301 23:07:28.039888
8302 23:07:28.039961 Set Vref, RX VrefLevel [Byte0]: 36
8303 23:07:28.043273 [Byte1]: 36
8304 23:07:28.047315
8305 23:07:28.047410 Set Vref, RX VrefLevel [Byte0]: 37
8306 23:07:28.050724 [Byte1]: 37
8307 23:07:28.054880
8308 23:07:28.054952 Set Vref, RX VrefLevel [Byte0]: 38
8309 23:07:28.058140 [Byte1]: 38
8310 23:07:28.062860
8311 23:07:28.062955 Set Vref, RX VrefLevel [Byte0]: 39
8312 23:07:28.066333 [Byte1]: 39
8313 23:07:28.070238
8314 23:07:28.070330 Set Vref, RX VrefLevel [Byte0]: 40
8315 23:07:28.076599 [Byte1]: 40
8316 23:07:28.076692
8317 23:07:28.080027 Set Vref, RX VrefLevel [Byte0]: 41
8318 23:07:28.083395 [Byte1]: 41
8319 23:07:28.083490
8320 23:07:28.086958 Set Vref, RX VrefLevel [Byte0]: 42
8321 23:07:28.089934 [Byte1]: 42
8322 23:07:28.093205
8323 23:07:28.093304 Set Vref, RX VrefLevel [Byte0]: 43
8324 23:07:28.096497 [Byte1]: 43
8325 23:07:28.100887
8326 23:07:28.100958 Set Vref, RX VrefLevel [Byte0]: 44
8327 23:07:28.104103 [Byte1]: 44
8328 23:07:28.108580
8329 23:07:28.108685 Set Vref, RX VrefLevel [Byte0]: 45
8330 23:07:28.111725 [Byte1]: 45
8331 23:07:28.116068
8332 23:07:28.116165 Set Vref, RX VrefLevel [Byte0]: 46
8333 23:07:28.119788 [Byte1]: 46
8334 23:07:28.123707
8335 23:07:28.123780 Set Vref, RX VrefLevel [Byte0]: 47
8336 23:07:28.127930 [Byte1]: 47
8337 23:07:28.131461
8338 23:07:28.131555 Set Vref, RX VrefLevel [Byte0]: 48
8339 23:07:28.134640 [Byte1]: 48
8340 23:07:28.139042
8341 23:07:28.139135 Set Vref, RX VrefLevel [Byte0]: 49
8342 23:07:28.142607 [Byte1]: 49
8343 23:07:28.147204
8344 23:07:28.147299 Set Vref, RX VrefLevel [Byte0]: 50
8345 23:07:28.150140 [Byte1]: 50
8346 23:07:28.154687
8347 23:07:28.154785 Set Vref, RX VrefLevel [Byte0]: 51
8348 23:07:28.157644 [Byte1]: 51
8349 23:07:28.162076
8350 23:07:28.162142 Set Vref, RX VrefLevel [Byte0]: 52
8351 23:07:28.165305 [Byte1]: 52
8352 23:07:28.169928
8353 23:07:28.170023 Set Vref, RX VrefLevel [Byte0]: 53
8354 23:07:28.173148 [Byte1]: 53
8355 23:07:28.177280
8356 23:07:28.177349 Set Vref, RX VrefLevel [Byte0]: 54
8357 23:07:28.180620 [Byte1]: 54
8358 23:07:28.185266
8359 23:07:28.185342 Set Vref, RX VrefLevel [Byte0]: 55
8360 23:07:28.188385 [Byte1]: 55
8361 23:07:28.193067
8362 23:07:28.193166 Set Vref, RX VrefLevel [Byte0]: 56
8363 23:07:28.196169 [Byte1]: 56
8364 23:07:28.200244
8365 23:07:28.200348 Set Vref, RX VrefLevel [Byte0]: 57
8366 23:07:28.203602 [Byte1]: 57
8367 23:07:28.208337
8368 23:07:28.208425 Set Vref, RX VrefLevel [Byte0]: 58
8369 23:07:28.211559 [Byte1]: 58
8370 23:07:28.215878
8371 23:07:28.215959 Set Vref, RX VrefLevel [Byte0]: 59
8372 23:07:28.218955 [Byte1]: 59
8373 23:07:28.223522
8374 23:07:28.223602 Set Vref, RX VrefLevel [Byte0]: 60
8375 23:07:28.226540 [Byte1]: 60
8376 23:07:28.231084
8377 23:07:28.231164 Set Vref, RX VrefLevel [Byte0]: 61
8378 23:07:28.234287 [Byte1]: 61
8379 23:07:28.239047
8380 23:07:28.239164 Set Vref, RX VrefLevel [Byte0]: 62
8381 23:07:28.241887 [Byte1]: 62
8382 23:07:28.246562
8383 23:07:28.246664 Set Vref, RX VrefLevel [Byte0]: 63
8384 23:07:28.249469 [Byte1]: 63
8385 23:07:28.253898
8386 23:07:28.253998 Set Vref, RX VrefLevel [Byte0]: 64
8387 23:07:28.257112 [Byte1]: 64
8388 23:07:28.261530
8389 23:07:28.261603 Set Vref, RX VrefLevel [Byte0]: 65
8390 23:07:28.264679 [Byte1]: 65
8391 23:07:28.269338
8392 23:07:28.269413 Set Vref, RX VrefLevel [Byte0]: 66
8393 23:07:28.272787 [Byte1]: 66
8394 23:07:28.276937
8395 23:07:28.277013 Set Vref, RX VrefLevel [Byte0]: 67
8396 23:07:28.280001 [Byte1]: 67
8397 23:07:28.284428
8398 23:07:28.284528 Set Vref, RX VrefLevel [Byte0]: 68
8399 23:07:28.287790 [Byte1]: 68
8400 23:07:28.292106
8401 23:07:28.292206 Set Vref, RX VrefLevel [Byte0]: 69
8402 23:07:28.295821 [Byte1]: 69
8403 23:07:28.299673
8404 23:07:28.299774 Set Vref, RX VrefLevel [Byte0]: 70
8405 23:07:28.303239 [Byte1]: 70
8406 23:07:28.307644
8407 23:07:28.307753 Set Vref, RX VrefLevel [Byte0]: 71
8408 23:07:28.310815 [Byte1]: 71
8409 23:07:28.315375
8410 23:07:28.315486 Set Vref, RX VrefLevel [Byte0]: 72
8411 23:07:28.318561 [Byte1]: 72
8412 23:07:28.322888
8413 23:07:28.322987 Set Vref, RX VrefLevel [Byte0]: 73
8414 23:07:28.326219 [Byte1]: 73
8415 23:07:28.330343
8416 23:07:28.330441 Final RX Vref Byte 0 = 61 to rank0
8417 23:07:28.333875 Final RX Vref Byte 1 = 56 to rank0
8418 23:07:28.337205 Final RX Vref Byte 0 = 61 to rank1
8419 23:07:28.340466 Final RX Vref Byte 1 = 56 to rank1==
8420 23:07:28.344200 Dram Type= 6, Freq= 0, CH_1, rank 0
8421 23:07:28.350382 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8422 23:07:28.350486 ==
8423 23:07:28.350591 DQS Delay:
8424 23:07:28.350680 DQS0 = 0, DQS1 = 0
8425 23:07:28.353769 DQM Delay:
8426 23:07:28.353870 DQM0 = 129, DQM1 = 124
8427 23:07:28.356991 DQ Delay:
8428 23:07:28.360305 DQ0 =134, DQ1 =122, DQ2 =118, DQ3 =126
8429 23:07:28.363757 DQ4 =130, DQ5 =138, DQ6 =138, DQ7 =126
8430 23:07:28.366915 DQ8 =106, DQ9 =114, DQ10 =128, DQ11 =114
8431 23:07:28.369989 DQ12 =130, DQ13 =134, DQ14 =134, DQ15 =134
8432 23:07:28.370099
8433 23:07:28.370192
8434 23:07:28.370278
8435 23:07:28.373463 [DramC_TX_OE_Calibration] TA2
8436 23:07:28.376641 Original DQ_B0 (3 6) =30, OEN = 27
8437 23:07:28.379969 Original DQ_B1 (3 6) =30, OEN = 27
8438 23:07:28.383554 24, 0x0, End_B0=24 End_B1=24
8439 23:07:28.383631 25, 0x0, End_B0=25 End_B1=25
8440 23:07:28.386687 26, 0x0, End_B0=26 End_B1=26
8441 23:07:28.389991 27, 0x0, End_B0=27 End_B1=27
8442 23:07:28.393354 28, 0x0, End_B0=28 End_B1=28
8443 23:07:28.396379 29, 0x0, End_B0=29 End_B1=29
8444 23:07:28.396489 30, 0x0, End_B0=30 End_B1=30
8445 23:07:28.400083 31, 0x4141, End_B0=30 End_B1=30
8446 23:07:28.403022 Byte0 end_step=30 best_step=27
8447 23:07:28.406598 Byte1 end_step=30 best_step=27
8448 23:07:28.409989 Byte0 TX OE(2T, 0.5T) = (3, 3)
8449 23:07:28.413099 Byte1 TX OE(2T, 0.5T) = (3, 3)
8450 23:07:28.413175
8451 23:07:28.413261
8452 23:07:28.419767 [DQSOSCAuto] RK0, (LSB)MR18= 0x2424, (MSB)MR19= 0x303, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps
8453 23:07:28.422855 CH1 RK0: MR19=303, MR18=2424
8454 23:07:28.429578 CH1_RK0: MR19=0x303, MR18=0x2424, DQSOSC=391, MR23=63, INC=24, DEC=16
8455 23:07:28.429682
8456 23:07:28.432879 ----->DramcWriteLeveling(PI) begin...
8457 23:07:28.432968 ==
8458 23:07:28.436207 Dram Type= 6, Freq= 0, CH_1, rank 1
8459 23:07:28.439734 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8460 23:07:28.439811 ==
8461 23:07:28.442726 Write leveling (Byte 0): 22 => 22
8462 23:07:28.446098 Write leveling (Byte 1): 22 => 22
8463 23:07:28.449481 DramcWriteLeveling(PI) end<-----
8464 23:07:28.449554
8465 23:07:28.449652 ==
8466 23:07:28.452483 Dram Type= 6, Freq= 0, CH_1, rank 1
8467 23:07:28.455910 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8468 23:07:28.459076 ==
8469 23:07:28.459185 [Gating] SW mode calibration
8470 23:07:28.465672 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8471 23:07:28.472639 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8472 23:07:28.475656 0 12 0 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
8473 23:07:28.482584 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8474 23:07:28.485746 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8475 23:07:28.488886 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8476 23:07:28.495433 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8477 23:07:28.498838 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8478 23:07:28.502159 0 12 24 | B1->B0 | 3434 2424 | 1 0 | (1 1) (1 0)
8479 23:07:28.508892 0 12 28 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8480 23:07:28.512267 0 13 0 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
8481 23:07:28.515420 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8482 23:07:28.521839 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8483 23:07:28.525156 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8484 23:07:28.528382 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8485 23:07:28.534878 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8486 23:07:28.538272 0 13 24 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
8487 23:07:28.541522 0 13 28 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
8488 23:07:28.548975 0 14 0 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
8489 23:07:28.551642 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8490 23:07:28.554907 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8491 23:07:28.561627 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8492 23:07:28.565130 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8493 23:07:28.568342 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8494 23:07:28.574811 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8495 23:07:28.578214 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8496 23:07:28.581398 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8497 23:07:28.587902 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8498 23:07:28.591344 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8499 23:07:28.594593 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8500 23:07:28.601265 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8501 23:07:28.604825 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8502 23:07:28.607864 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8503 23:07:28.614268 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8504 23:07:28.617751 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8505 23:07:28.620912 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8506 23:07:28.627546 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8507 23:07:28.630924 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8508 23:07:28.634087 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8509 23:07:28.640908 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8510 23:07:28.643975 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8511 23:07:28.647587 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8512 23:07:28.650976 Total UI for P1: 0, mck2ui 16
8513 23:07:28.654140 best dqsien dly found for B0: ( 1, 0, 24)
8514 23:07:28.660568 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8515 23:07:28.663969 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8516 23:07:28.667062 Total UI for P1: 0, mck2ui 16
8517 23:07:28.670427 best dqsien dly found for B1: ( 1, 0, 30)
8518 23:07:28.673870 best DQS0 dly(MCK, UI, PI) = (1, 0, 24)
8519 23:07:28.677169 best DQS1 dly(MCK, UI, PI) = (1, 0, 30)
8520 23:07:28.677250
8521 23:07:28.680617 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 24)
8522 23:07:28.684132 best DQS1 P1 dly(MCK, UI, PI) = (1, 4, 30)
8523 23:07:28.687121 [Gating] SW calibration Done
8524 23:07:28.687229 ==
8525 23:07:28.690260 Dram Type= 6, Freq= 0, CH_1, rank 1
8526 23:07:28.693560 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8527 23:07:28.696998 ==
8528 23:07:28.697073 RX Vref Scan: 0
8529 23:07:28.697140
8530 23:07:28.700244 RX Vref 0 -> 0, step: 1
8531 23:07:28.700342
8532 23:07:28.700431 RX Delay 0 -> 252, step: 8
8533 23:07:28.706910 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8534 23:07:28.710453 iDelay=200, Bit 1, Center 123 (64 ~ 183) 120
8535 23:07:28.713605 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8536 23:07:28.716903 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8537 23:07:28.720244 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8538 23:07:28.726806 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8539 23:07:28.730003 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8540 23:07:28.733241 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8541 23:07:28.736579 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8542 23:07:28.743209 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8543 23:07:28.746535 iDelay=200, Bit 10, Center 127 (64 ~ 191) 128
8544 23:07:28.749660 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8545 23:07:28.752991 iDelay=200, Bit 12, Center 135 (72 ~ 199) 128
8546 23:07:28.756507 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8547 23:07:28.763256 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8548 23:07:28.766505 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8549 23:07:28.766573 ==
8550 23:07:28.769632 Dram Type= 6, Freq= 0, CH_1, rank 1
8551 23:07:28.772873 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8552 23:07:28.772942 ==
8553 23:07:28.776407 DQS Delay:
8554 23:07:28.776508 DQS0 = 0, DQS1 = 0
8555 23:07:28.776598 DQM Delay:
8556 23:07:28.779545 DQM0 = 131, DQM1 = 125
8557 23:07:28.779638 DQ Delay:
8558 23:07:28.783015 DQ0 =135, DQ1 =123, DQ2 =119, DQ3 =131
8559 23:07:28.786115 DQ4 =131, DQ5 =143, DQ6 =139, DQ7 =131
8560 23:07:28.792664 DQ8 =107, DQ9 =115, DQ10 =127, DQ11 =115
8561 23:07:28.796141 DQ12 =135, DQ13 =139, DQ14 =131, DQ15 =135
8562 23:07:28.796239
8563 23:07:28.796329
8564 23:07:28.796414 ==
8565 23:07:28.799274 Dram Type= 6, Freq= 0, CH_1, rank 1
8566 23:07:28.802793 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8567 23:07:28.802894 ==
8568 23:07:28.802986
8569 23:07:28.803075
8570 23:07:28.806037 TX Vref Scan disable
8571 23:07:28.809204 == TX Byte 0 ==
8572 23:07:28.812514 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8573 23:07:28.815879 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
8574 23:07:28.819101 == TX Byte 1 ==
8575 23:07:28.822422 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8576 23:07:28.826083 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
8577 23:07:28.826183 ==
8578 23:07:28.829113 Dram Type= 6, Freq= 0, CH_1, rank 1
8579 23:07:28.832508 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8580 23:07:28.835495 ==
8581 23:07:28.846255
8582 23:07:28.849349 TX Vref early break, caculate TX vref
8583 23:07:28.852695 TX Vref=16, minBit 0, minWin=22, winSum=370
8584 23:07:28.856120 TX Vref=18, minBit 7, minWin=22, winSum=384
8585 23:07:28.859265 TX Vref=20, minBit 2, minWin=23, winSum=389
8586 23:07:28.862739 TX Vref=22, minBit 0, minWin=24, winSum=401
8587 23:07:28.866173 TX Vref=24, minBit 1, minWin=24, winSum=405
8588 23:07:28.872832 TX Vref=26, minBit 0, minWin=23, winSum=412
8589 23:07:28.876370 TX Vref=28, minBit 0, minWin=25, winSum=420
8590 23:07:28.879282 TX Vref=30, minBit 2, minWin=24, winSum=413
8591 23:07:28.882589 TX Vref=32, minBit 0, minWin=24, winSum=409
8592 23:07:28.886155 TX Vref=34, minBit 0, minWin=22, winSum=396
8593 23:07:28.892599 [TxChooseVref] Worse bit 0, Min win 25, Win sum 420, Final Vref 28
8594 23:07:28.892720
8595 23:07:28.896139 Final TX Range 0 Vref 28
8596 23:07:28.896237
8597 23:07:28.896331 ==
8598 23:07:28.899444 Dram Type= 6, Freq= 0, CH_1, rank 1
8599 23:07:28.902471 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8600 23:07:28.902571 ==
8601 23:07:28.902660
8602 23:07:28.902750
8603 23:07:28.906071 TX Vref Scan disable
8604 23:07:28.912582 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8605 23:07:28.912688 == TX Byte 0 ==
8606 23:07:28.915828 u2DelayCellOfst[0]=17 cells (5 PI)
8607 23:07:28.919043 u2DelayCellOfst[1]=10 cells (3 PI)
8608 23:07:28.922309 u2DelayCellOfst[2]=0 cells (0 PI)
8609 23:07:28.925680 u2DelayCellOfst[3]=7 cells (2 PI)
8610 23:07:28.929048 u2DelayCellOfst[4]=10 cells (3 PI)
8611 23:07:28.932606 u2DelayCellOfst[5]=17 cells (5 PI)
8612 23:07:28.935892 u2DelayCellOfst[6]=17 cells (5 PI)
8613 23:07:28.935991 u2DelayCellOfst[7]=10 cells (3 PI)
8614 23:07:28.942230 Update DQ dly =974 (3 ,6, 14) DQ OEN =(3 ,3)
8615 23:07:28.945696 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8616 23:07:28.945785 == TX Byte 1 ==
8617 23:07:28.948917 u2DelayCellOfst[8]=0 cells (0 PI)
8618 23:07:28.952159 u2DelayCellOfst[9]=7 cells (2 PI)
8619 23:07:28.955699 u2DelayCellOfst[10]=14 cells (4 PI)
8620 23:07:28.959061 u2DelayCellOfst[11]=7 cells (2 PI)
8621 23:07:28.962157 u2DelayCellOfst[12]=17 cells (5 PI)
8622 23:07:28.965654 u2DelayCellOfst[13]=21 cells (6 PI)
8623 23:07:28.968775 u2DelayCellOfst[14]=21 cells (6 PI)
8624 23:07:28.972409 u2DelayCellOfst[15]=17 cells (5 PI)
8625 23:07:28.975249 Update DQ dly =973 (3 ,6, 13) DQ OEN =(3 ,3)
8626 23:07:28.982474 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8627 23:07:28.982566 DramC Write-DBI on
8628 23:07:28.982669 ==
8629 23:07:28.985729 Dram Type= 6, Freq= 0, CH_1, rank 1
8630 23:07:28.988826 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8631 23:07:28.992157 ==
8632 23:07:28.992234
8633 23:07:28.992325
8634 23:07:28.992412 TX Vref Scan disable
8635 23:07:28.995446 == TX Byte 0 ==
8636 23:07:28.998996 Update DQM dly =719 (2 ,6, 15) DQM OEN =(3 ,3)
8637 23:07:29.002101 == TX Byte 1 ==
8638 23:07:29.005363 Update DQM dly =717 (2 ,6, 13) DQM OEN =(3 ,3)
8639 23:07:29.009047 DramC Write-DBI off
8640 23:07:29.009144
8641 23:07:29.009237 [DATLAT]
8642 23:07:29.009324 Freq=1600, CH1 RK1
8643 23:07:29.009412
8644 23:07:29.012046 DATLAT Default: 0xe
8645 23:07:29.015223 0, 0xFFFF, sum = 0
8646 23:07:29.015325 1, 0xFFFF, sum = 0
8647 23:07:29.018508 2, 0xFFFF, sum = 0
8648 23:07:29.018611 3, 0xFFFF, sum = 0
8649 23:07:29.022045 4, 0xFFFF, sum = 0
8650 23:07:29.022149 5, 0xFFFF, sum = 0
8651 23:07:29.025236 6, 0xFFFF, sum = 0
8652 23:07:29.025335 7, 0xFFFF, sum = 0
8653 23:07:29.028621 8, 0xFFFF, sum = 0
8654 23:07:29.028747 9, 0xFFFF, sum = 0
8655 23:07:29.032214 10, 0xFFFF, sum = 0
8656 23:07:29.032312 11, 0xFFFF, sum = 0
8657 23:07:29.035201 12, 0xFFF, sum = 0
8658 23:07:29.035307 13, 0x0, sum = 1
8659 23:07:29.038922 14, 0x0, sum = 2
8660 23:07:29.039002 15, 0x0, sum = 3
8661 23:07:29.041690 16, 0x0, sum = 4
8662 23:07:29.041769 best_step = 14
8663 23:07:29.041858
8664 23:07:29.041942 ==
8665 23:07:29.045316 Dram Type= 6, Freq= 0, CH_1, rank 1
8666 23:07:29.048659 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8667 23:07:29.051825 ==
8668 23:07:29.051925 RX Vref Scan: 0
8669 23:07:29.052013
8670 23:07:29.055207 RX Vref 0 -> 0, step: 1
8671 23:07:29.055277
8672 23:07:29.055342 RX Delay 3 -> 252, step: 4
8673 23:07:29.062387 iDelay=195, Bit 0, Center 128 (75 ~ 182) 108
8674 23:07:29.065595 iDelay=195, Bit 1, Center 122 (67 ~ 178) 112
8675 23:07:29.069020 iDelay=195, Bit 2, Center 116 (63 ~ 170) 108
8676 23:07:29.072457 iDelay=195, Bit 3, Center 122 (67 ~ 178) 112
8677 23:07:29.076089 iDelay=195, Bit 4, Center 126 (71 ~ 182) 112
8678 23:07:29.082296 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112
8679 23:07:29.085534 iDelay=195, Bit 6, Center 136 (83 ~ 190) 108
8680 23:07:29.089063 iDelay=195, Bit 7, Center 126 (71 ~ 182) 112
8681 23:07:29.092110 iDelay=195, Bit 8, Center 104 (47 ~ 162) 116
8682 23:07:29.096041 iDelay=195, Bit 9, Center 110 (55 ~ 166) 112
8683 23:07:29.102349 iDelay=195, Bit 10, Center 124 (67 ~ 182) 116
8684 23:07:29.105711 iDelay=195, Bit 11, Center 114 (59 ~ 170) 112
8685 23:07:29.108790 iDelay=195, Bit 12, Center 132 (75 ~ 190) 116
8686 23:07:29.112275 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8687 23:07:29.118651 iDelay=195, Bit 14, Center 134 (79 ~ 190) 112
8688 23:07:29.122064 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8689 23:07:29.122165 ==
8690 23:07:29.125476 Dram Type= 6, Freq= 0, CH_1, rank 1
8691 23:07:29.128670 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8692 23:07:29.128799 ==
8693 23:07:29.132086 DQS Delay:
8694 23:07:29.132182 DQS0 = 0, DQS1 = 0
8695 23:07:29.132275 DQM Delay:
8696 23:07:29.135764 DQM0 = 126, DQM1 = 122
8697 23:07:29.135856 DQ Delay:
8698 23:07:29.138655 DQ0 =128, DQ1 =122, DQ2 =116, DQ3 =122
8699 23:07:29.142153 DQ4 =126, DQ5 =138, DQ6 =136, DQ7 =126
8700 23:07:29.145556 DQ8 =104, DQ9 =110, DQ10 =124, DQ11 =114
8701 23:07:29.152297 DQ12 =132, DQ13 =132, DQ14 =134, DQ15 =132
8702 23:07:29.152396
8703 23:07:29.152490
8704 23:07:29.152577
8705 23:07:29.155545 [DramC_TX_OE_Calibration] TA2
8706 23:07:29.155642 Original DQ_B0 (3 6) =30, OEN = 27
8707 23:07:29.158652 Original DQ_B1 (3 6) =30, OEN = 27
8708 23:07:29.161897 24, 0x0, End_B0=24 End_B1=24
8709 23:07:29.165296 25, 0x0, End_B0=25 End_B1=25
8710 23:07:29.168879 26, 0x0, End_B0=26 End_B1=26
8711 23:07:29.168954 27, 0x0, End_B0=27 End_B1=27
8712 23:07:29.171925 28, 0x0, End_B0=28 End_B1=28
8713 23:07:29.175364 29, 0x0, End_B0=29 End_B1=29
8714 23:07:29.178312 30, 0x0, End_B0=30 End_B1=30
8715 23:07:29.181736 31, 0x4141, End_B0=30 End_B1=30
8716 23:07:29.185178 Byte0 end_step=30 best_step=27
8717 23:07:29.185250 Byte1 end_step=30 best_step=27
8718 23:07:29.188465 Byte0 TX OE(2T, 0.5T) = (3, 3)
8719 23:07:29.191539 Byte1 TX OE(2T, 0.5T) = (3, 3)
8720 23:07:29.191642
8721 23:07:29.191732
8722 23:07:29.201451 [DQSOSCAuto] RK1, (LSB)MR18= 0x1d1d, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 395 ps
8723 23:07:29.201540 CH1 RK1: MR19=303, MR18=1D1D
8724 23:07:29.208213 CH1_RK1: MR19=0x303, MR18=0x1D1D, DQSOSC=395, MR23=63, INC=23, DEC=15
8725 23:07:29.211582 [RxdqsGatingPostProcess] freq 1600
8726 23:07:29.218367 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
8727 23:07:29.221642 Pre-setting of DQS Precalculation
8728 23:07:29.224872 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
8729 23:07:29.234538 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
8730 23:07:29.241846 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8731 23:07:29.241952
8732 23:07:29.242044
8733 23:07:29.244397 [Calibration Summary] 3200 Mbps
8734 23:07:29.244493 CH 0, Rank 0
8735 23:07:29.248009 SW Impedance : PASS
8736 23:07:29.248118 DUTY Scan : NO K
8737 23:07:29.251595 ZQ Calibration : PASS
8738 23:07:29.254382 Jitter Meter : NO K
8739 23:07:29.254480 CBT Training : PASS
8740 23:07:29.257588 Write leveling : PASS
8741 23:07:29.261191 RX DQS gating : PASS
8742 23:07:29.261265 RX DQ/DQS(RDDQC) : PASS
8743 23:07:29.264661 TX DQ/DQS : PASS
8744 23:07:29.267512 RX DATLAT : PASS
8745 23:07:29.267607 RX DQ/DQS(Engine): PASS
8746 23:07:29.271019 TX OE : PASS
8747 23:07:29.271114 All Pass.
8748 23:07:29.271205
8749 23:07:29.274171 CH 0, Rank 1
8750 23:07:29.274241 SW Impedance : PASS
8751 23:07:29.277435 DUTY Scan : NO K
8752 23:07:29.280929 ZQ Calibration : PASS
8753 23:07:29.281025 Jitter Meter : NO K
8754 23:07:29.284369 CBT Training : PASS
8755 23:07:29.284471 Write leveling : PASS
8756 23:07:29.287664 RX DQS gating : PASS
8757 23:07:29.290879 RX DQ/DQS(RDDQC) : PASS
8758 23:07:29.290977 TX DQ/DQS : PASS
8759 23:07:29.293925 RX DATLAT : PASS
8760 23:07:29.297285 RX DQ/DQS(Engine): PASS
8761 23:07:29.297385 TX OE : PASS
8762 23:07:29.300602 All Pass.
8763 23:07:29.300703
8764 23:07:29.300802 CH 1, Rank 0
8765 23:07:29.304062 SW Impedance : PASS
8766 23:07:29.304165 DUTY Scan : NO K
8767 23:07:29.307343 ZQ Calibration : PASS
8768 23:07:29.310822 Jitter Meter : NO K
8769 23:07:29.310928 CBT Training : PASS
8770 23:07:29.313875 Write leveling : PASS
8771 23:07:29.317391 RX DQS gating : PASS
8772 23:07:29.317492 RX DQ/DQS(RDDQC) : PASS
8773 23:07:29.320631 TX DQ/DQS : PASS
8774 23:07:29.324129 RX DATLAT : PASS
8775 23:07:29.324232 RX DQ/DQS(Engine): PASS
8776 23:07:29.327887 TX OE : PASS
8777 23:07:29.327987 All Pass.
8778 23:07:29.328076
8779 23:07:29.330943 CH 1, Rank 1
8780 23:07:29.331040 SW Impedance : PASS
8781 23:07:29.333885 DUTY Scan : NO K
8782 23:07:29.337350 ZQ Calibration : PASS
8783 23:07:29.337450 Jitter Meter : NO K
8784 23:07:29.340532 CBT Training : PASS
8785 23:07:29.340634 Write leveling : PASS
8786 23:07:29.343851 RX DQS gating : PASS
8787 23:07:29.347368 RX DQ/DQS(RDDQC) : PASS
8788 23:07:29.347469 TX DQ/DQS : PASS
8789 23:07:29.350551 RX DATLAT : PASS
8790 23:07:29.353743 RX DQ/DQS(Engine): PASS
8791 23:07:29.353846 TX OE : PASS
8792 23:07:29.357180 All Pass.
8793 23:07:29.357278
8794 23:07:29.357368 DramC Write-DBI on
8795 23:07:29.360485 PER_BANK_REFRESH: Hybrid Mode
8796 23:07:29.360584 TX_TRACKING: ON
8797 23:07:29.370658 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
8798 23:07:29.380334 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
8799 23:07:29.386969 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8800 23:07:29.390273 [FAST_K] Save calibration result to emmc
8801 23:07:29.393627 sync common calibartion params.
8802 23:07:29.393742 sync cbt_mode0:0, 1:0
8803 23:07:29.396901 dram_init: ddr_geometry: 0
8804 23:07:29.400090 dram_init: ddr_geometry: 0
8805 23:07:29.403581 dram_init: ddr_geometry: 0
8806 23:07:29.403681 0:dram_rank_size:80000000
8807 23:07:29.406885 1:dram_rank_size:80000000
8808 23:07:29.413591 sync rank num:2, rank0_size:0x80000000, rank1_size:0x80000000
8809 23:07:29.413693 DFS_SHUFFLE_HW_MODE: ON
8810 23:07:29.416936 dramc_set_vcore_voltage set vcore to 725000
8811 23:07:29.420113 Read voltage for 1600, 0
8812 23:07:29.420212 Vio18 = 0
8813 23:07:29.423275 Vcore = 725000
8814 23:07:29.423367 Vdram = 0
8815 23:07:29.423458 Vddq = 0
8816 23:07:29.426567 Vmddr = 0
8817 23:07:29.426660 switch to 3200 Mbps bootup
8818 23:07:29.429900 [DramcRunTimeConfig]
8819 23:07:29.429993 PHYPLL
8820 23:07:29.433228 DPM_CONTROL_AFTERK: ON
8821 23:07:29.433295 PER_BANK_REFRESH: ON
8822 23:07:29.436534 REFRESH_OVERHEAD_REDUCTION: ON
8823 23:07:29.439883 CMD_PICG_NEW_MODE: OFF
8824 23:07:29.439952 XRTWTW_NEW_MODE: ON
8825 23:07:29.443372 XRTRTR_NEW_MODE: ON
8826 23:07:29.443466 TX_TRACKING: ON
8827 23:07:29.446401 RDSEL_TRACKING: OFF
8828 23:07:29.450002 DQS Precalculation for DVFS: ON
8829 23:07:29.450096 RX_TRACKING: OFF
8830 23:07:29.452916 HW_GATING DBG: ON
8831 23:07:29.452981 ZQCS_ENABLE_LP4: ON
8832 23:07:29.456481 RX_PICG_NEW_MODE: ON
8833 23:07:29.456575 TX_PICG_NEW_MODE: ON
8834 23:07:29.459594 ENABLE_RX_DCM_DPHY: ON
8835 23:07:29.462931 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
8836 23:07:29.465959 DUMMY_READ_FOR_TRACKING: OFF
8837 23:07:29.469525 !!! SPM_CONTROL_AFTERK: OFF
8838 23:07:29.469606 !!! SPM could not control APHY
8839 23:07:29.472772 IMPEDANCE_TRACKING: ON
8840 23:07:29.472839 TEMP_SENSOR: ON
8841 23:07:29.476177 HW_SAVE_FOR_SR: OFF
8842 23:07:29.479492 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
8843 23:07:29.482976 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
8844 23:07:29.486482 Read ODT Tracking: ON
8845 23:07:29.486553 Refresh Rate DeBounce: ON
8846 23:07:29.489319 DFS_NO_QUEUE_FLUSH: ON
8847 23:07:29.492647 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
8848 23:07:29.495877 ENABLE_DFS_RUNTIME_MRW: OFF
8849 23:07:29.495975 DDR_RESERVE_NEW_MODE: ON
8850 23:07:29.499453 MR_CBT_SWITCH_FREQ: ON
8851 23:07:29.502586 =========================
8852 23:07:29.520006 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
8853 23:07:29.523328 dram_init: ddr_geometry: 0
8854 23:07:29.541369 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
8855 23:07:29.544634 dram_init: dram init end (result: 0)
8856 23:07:29.551787 DRAM-K: Full calibration passed in 23403 msecs
8857 23:07:29.554923 MRC: failed to locate region type 0.
8858 23:07:29.554994 DRAM rank0 size:0x80000000,
8859 23:07:29.557962 DRAM rank1 size=0x80000000
8860 23:07:29.567984 Mapping address range [0x40000000:0x140000000) as cacheable | read-write | non-secure | normal
8861 23:07:29.574698 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
8862 23:07:29.581307 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
8863 23:07:29.587983 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
8864 23:07:29.591058 DRAM rank0 size:0x80000000,
8865 23:07:29.594505 DRAM rank1 size=0x80000000
8866 23:07:29.594617 CBMEM:
8867 23:07:29.598035 IMD: root @ 0xfffff000 254 entries.
8868 23:07:29.601069 IMD: root @ 0xffffec00 62 entries.
8869 23:07:29.604334 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
8870 23:07:29.607994 WARNING: RO_VPD is uninitialized or empty.
8871 23:07:29.614428 FMAP: area RW_VPD found @ 577000 (16384 bytes)
8872 23:07:29.621136 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
8873 23:07:29.633743 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
8874 23:07:29.645365 BS: romstage times (exec / console): total (unknown) / 22946 ms
8875 23:07:29.645469
8876 23:07:29.645562
8877 23:07:29.655139 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
8878 23:07:29.658508 ARM64: Exception handlers installed.
8879 23:07:29.661732 ARM64: Testing exception
8880 23:07:29.665104 ARM64: Done test exception
8881 23:07:29.665173 Enumerating buses...
8882 23:07:29.668214 Show all devs... Before device enumeration.
8883 23:07:29.671507 Root Device: enabled 1
8884 23:07:29.674884 CPU_CLUSTER: 0: enabled 1
8885 23:07:29.674983 CPU: 00: enabled 1
8886 23:07:29.678148 Compare with tree...
8887 23:07:29.678242 Root Device: enabled 1
8888 23:07:29.681496 CPU_CLUSTER: 0: enabled 1
8889 23:07:29.684623 CPU: 00: enabled 1
8890 23:07:29.684745 Root Device scanning...
8891 23:07:29.688018 scan_static_bus for Root Device
8892 23:07:29.691569 CPU_CLUSTER: 0 enabled
8893 23:07:29.695323 scan_static_bus for Root Device done
8894 23:07:29.698046 scan_bus: bus Root Device finished in 8 msecs
8895 23:07:29.698149 done
8896 23:07:29.704732 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
8897 23:07:29.708068 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
8898 23:07:29.714641 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
8899 23:07:29.718136 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
8900 23:07:29.721533 Allocating resources...
8901 23:07:29.724897 Reading resources...
8902 23:07:29.728337 Root Device read_resources bus 0 link: 0
8903 23:07:29.728437 DRAM rank0 size:0x80000000,
8904 23:07:29.731270 DRAM rank1 size=0x80000000
8905 23:07:29.734678 CPU_CLUSTER: 0 read_resources bus 0 link: 0
8906 23:07:29.738104 CPU: 00 missing read_resources
8907 23:07:29.741058 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
8908 23:07:29.747526 Root Device read_resources bus 0 link: 0 done
8909 23:07:29.747626 Done reading resources.
8910 23:07:29.754599 Show resources in subtree (Root Device)...After reading.
8911 23:07:29.757776 Root Device child on link 0 CPU_CLUSTER: 0
8912 23:07:29.761363 CPU_CLUSTER: 0 child on link 0 CPU: 00
8913 23:07:29.770961 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8914 23:07:29.771063 CPU: 00
8915 23:07:29.774317 Root Device assign_resources, bus 0 link: 0
8916 23:07:29.777663 CPU_CLUSTER: 0 missing set_resources
8917 23:07:29.784098 Root Device assign_resources, bus 0 link: 0 done
8918 23:07:29.784200 Done setting resources.
8919 23:07:29.791179 Show resources in subtree (Root Device)...After assigning values.
8920 23:07:29.794413 Root Device child on link 0 CPU_CLUSTER: 0
8921 23:07:29.797804 CPU_CLUSTER: 0 child on link 0 CPU: 00
8922 23:07:29.807309 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8923 23:07:29.807412 CPU: 00
8924 23:07:29.810658 Done allocating resources.
8925 23:07:29.814124 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
8926 23:07:29.817335 Enabling resources...
8927 23:07:29.817436 done.
8928 23:07:29.824207 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
8929 23:07:29.824309 Initializing devices...
8930 23:07:29.827424 Root Device init
8931 23:07:29.827525 init hardware done!
8932 23:07:29.830420 0x00000018: ctrlr->caps
8933 23:07:29.834227 52.000 MHz: ctrlr->f_max
8934 23:07:29.834331 0.400 MHz: ctrlr->f_min
8935 23:07:29.837197 0x40ff8080: ctrlr->voltages
8936 23:07:29.840423 sclk: 390625
8937 23:07:29.840523 Bus Width = 1
8938 23:07:29.840622 sclk: 390625
8939 23:07:29.843742 Bus Width = 1
8940 23:07:29.843845 Early init status = 3
8941 23:07:29.850280 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
8942 23:07:29.853514 in-header: 03 fc 00 00 01 00 00 00
8943 23:07:29.853613 in-data: 00
8944 23:07:29.860080 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
8945 23:07:29.863675 in-header: 03 fd 00 00 00 00 00 00
8946 23:07:29.867179 in-data:
8947 23:07:29.870199 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
8948 23:07:29.873675 in-header: 03 fc 00 00 01 00 00 00
8949 23:07:29.876934 in-data: 00
8950 23:07:29.880354 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
8951 23:07:29.885405 in-header: 03 fd 00 00 00 00 00 00
8952 23:07:29.888286 in-data:
8953 23:07:29.891744 [SSUSB] Setting up USB HOST controller...
8954 23:07:29.895189 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
8955 23:07:29.898279 [SSUSB] phy power-on done.
8956 23:07:29.901530 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
8957 23:07:29.908022 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
8958 23:07:29.911575 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
8959 23:07:29.918046 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
8960 23:07:29.925026 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
8961 23:07:29.931476 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
8962 23:07:29.937934 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
8963 23:07:29.944881 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
8964 23:07:29.948213 SPM: binary array size = 0x9dc
8965 23:07:29.951354 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
8966 23:07:29.957945 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
8967 23:07:29.964513 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
8968 23:07:29.967803 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
8969 23:07:29.974207 configure_display: Starting display init
8970 23:07:30.008107 anx7625_power_on_init: Init interface.
8971 23:07:30.011341 anx7625_disable_pd_protocol: Disabled PD feature.
8972 23:07:30.014692 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
8973 23:07:30.042517 anx7625_start_dp_work: Secure OCM version=00
8974 23:07:30.045779 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
8975 23:07:30.060560 sp_tx_get_edid_block: EDID Block = 1
8976 23:07:30.163132 Extracted contents:
8977 23:07:30.166799 header: 00 ff ff ff ff ff ff 00
8978 23:07:30.169820 serial number: 26 cf 7d 05 00 00 00 00 00 1e
8979 23:07:30.173038 version: 01 04
8980 23:07:30.176177 basic params: 95 1f 11 78 0a
8981 23:07:30.179649 chroma info: 76 90 94 55 54 90 27 21 50 54
8982 23:07:30.182904 established: 00 00 00
8983 23:07:30.189611 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
8984 23:07:30.193485 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
8985 23:07:30.199490 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
8986 23:07:30.206240 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
8987 23:07:30.212681 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
8988 23:07:30.216107 extensions: 00
8989 23:07:30.216211 checksum: fb
8990 23:07:30.216304
8991 23:07:30.219360 Manufacturer: IVO Model 57d Serial Number 0
8992 23:07:30.223012 Made week 0 of 2020
8993 23:07:30.225956 EDID version: 1.4
8994 23:07:30.226066 Digital display
8995 23:07:30.229201 6 bits per primary color channel
8996 23:07:30.229313 DisplayPort interface
8997 23:07:30.232796 Maximum image size: 31 cm x 17 cm
8998 23:07:30.235712 Gamma: 220%
8999 23:07:30.235809 Check DPMS levels
9000 23:07:30.239508 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9001 23:07:30.246040 First detailed timing is preferred timing
9002 23:07:30.246142 Established timings supported:
9003 23:07:30.249106 Standard timings supported:
9004 23:07:30.252379 Detailed timings
9005 23:07:30.255731 Hex of detail: 383680a07038204018303c0035ae10000019
9006 23:07:30.262475 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9007 23:07:30.266034 0780 0798 07c8 0820 hborder 0
9008 23:07:30.268790 0438 043b 0447 0458 vborder 0
9009 23:07:30.272164 -hsync -vsync
9010 23:07:30.272260 Did detailed timing
9011 23:07:30.278914 Hex of detail: 000000000000000000000000000000000000
9012 23:07:30.282231 Manufacturer-specified data, tag 0
9013 23:07:30.285643 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9014 23:07:30.288686 ASCII string: InfoVision
9015 23:07:30.292206 Hex of detail: 000000fe00523134304e574635205248200a
9016 23:07:30.295539 ASCII string: R140NWF5 RH
9017 23:07:30.295644 Checksum
9018 23:07:30.298516 Checksum: 0xfb (valid)
9019 23:07:30.302194 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9020 23:07:30.305229 DSI data_rate: 832800000 bps
9021 23:07:30.311954 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9022 23:07:30.315210 anx7625_parse_edid: pixelclock(138800).
9023 23:07:30.318632 hactive(1920), hsync(48), hfp(24), hbp(88)
9024 23:07:30.322152 vactive(1080), vsync(12), vfp(3), vbp(17)
9025 23:07:30.325353 anx7625_dsi_config: config dsi.
9026 23:07:30.331936 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9027 23:07:30.345425 anx7625_dsi_config: success to config DSI
9028 23:07:30.349045 anx7625_dp_start: MIPI phy setup OK.
9029 23:07:30.352030 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9030 23:07:30.355262 mtk_ddp_mode_set invalid vrefresh 60
9031 23:07:30.358638 main_disp_path_setup
9032 23:07:30.358738 ovl_layer_smi_id_en
9033 23:07:30.361663 ovl_layer_smi_id_en
9034 23:07:30.361764 ccorr_config
9035 23:07:30.361854 aal_config
9036 23:07:30.365004 gamma_config
9037 23:07:30.365106 postmask_config
9038 23:07:30.368489 dither_config
9039 23:07:30.371694 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9040 23:07:30.378524 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9041 23:07:30.381569 Root Device init finished in 551 msecs
9042 23:07:30.385078 CPU_CLUSTER: 0 init
9043 23:07:30.391942 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9044 23:07:30.395070 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9045 23:07:30.398372 APU_MBOX 0x190000b0 = 0x10001
9046 23:07:30.401678 APU_MBOX 0x190001b0 = 0x10001
9047 23:07:30.404990 APU_MBOX 0x190005b0 = 0x10001
9048 23:07:30.408264 APU_MBOX 0x190006b0 = 0x10001
9049 23:07:30.411570 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9050 23:07:30.424279 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9051 23:07:30.436744 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9052 23:07:30.443076 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9053 23:07:30.454937 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9054 23:07:30.464157 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9055 23:07:30.467238 CPU_CLUSTER: 0 init finished in 81 msecs
9056 23:07:30.471127 Devices initialized
9057 23:07:30.473966 Show all devs... After init.
9058 23:07:30.474047 Root Device: enabled 1
9059 23:07:30.477321 CPU_CLUSTER: 0: enabled 1
9060 23:07:30.480727 CPU: 00: enabled 1
9061 23:07:30.483792 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9062 23:07:30.487359 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9063 23:07:30.490261 ELOG: NV offset 0x57f000 size 0x1000
9064 23:07:30.497140 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9065 23:07:30.503792 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9066 23:07:30.507149 ELOG: Event(17) added with size 13 at 2023-12-27 23:07:49 UTC
9067 23:07:30.513481 out: cmd=0x121: 03 db 21 01 00 00 00 00
9068 23:07:30.517635 in-header: 03 11 00 00 2c 00 00 00
9069 23:07:30.526977 in-data: 52 64 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9070 23:07:30.533550 ELOG: Event(A1) added with size 10 at 2023-12-27 23:07:49 UTC
9071 23:07:30.540174 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9072 23:07:30.546735 ELOG: Event(A0) added with size 9 at 2023-12-27 23:07:49 UTC
9073 23:07:30.549964 elog_add_boot_reason: Logged dev mode boot
9074 23:07:30.556517 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9075 23:07:30.556599 Finalize devices...
9076 23:07:30.559837 Devices finalized
9077 23:07:30.563135 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9078 23:07:30.566689 Writing coreboot table at 0xffe64000
9079 23:07:30.569925 0. 000000000010a000-0000000000113fff: RAMSTAGE
9080 23:07:30.573299 1. 0000000040000000-00000000400fffff: RAM
9081 23:07:30.580000 2. 0000000040100000-000000004032afff: RAMSTAGE
9082 23:07:30.583434 3. 000000004032b000-00000000545fffff: RAM
9083 23:07:30.586553 4. 0000000054600000-000000005465ffff: BL31
9084 23:07:30.589858 5. 0000000054660000-00000000ffe63fff: RAM
9085 23:07:30.596478 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9086 23:07:30.600014 7. 0000000100000000-000000013fffffff: RAM
9087 23:07:30.603132 Passing 5 GPIOs to payload:
9088 23:07:30.606489 NAME | PORT | POLARITY | VALUE
9089 23:07:30.609825 EC in RW | 0x000000aa | low | undefined
9090 23:07:30.616414 EC interrupt | 0x00000005 | low | undefined
9091 23:07:30.619740 TPM interrupt | 0x000000ab | high | undefined
9092 23:07:30.626549 SD card detect | 0x00000011 | high | undefined
9093 23:07:30.629782 speaker enable | 0x00000093 | high | undefined
9094 23:07:30.632832 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9095 23:07:30.636176 in-header: 03 f8 00 00 02 00 00 00
9096 23:07:30.639637 in-data: 03 00
9097 23:07:30.639719 ADC[4]: Raw value=669327 ID=5
9098 23:07:30.642716 ADC[3]: Raw value=212549 ID=1
9099 23:07:30.646136 RAM Code: 0x51
9100 23:07:30.649693 ADC[6]: Raw value=74778 ID=0
9101 23:07:30.649775 ADC[5]: Raw value=211444 ID=1
9102 23:07:30.652718 SKU Code: 0x1
9103 23:07:30.656054 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum bca2
9104 23:07:30.659559 coreboot table: 964 bytes.
9105 23:07:30.662662 IMD ROOT 0. 0xfffff000 0x00001000
9106 23:07:30.665857 IMD SMALL 1. 0xffffe000 0x00001000
9107 23:07:30.669605 RO MCACHE 2. 0xffffc000 0x00001104
9108 23:07:30.672620 CONSOLE 3. 0xfff7c000 0x00080000
9109 23:07:30.676161 FMAP 4. 0xfff7b000 0x00000452
9110 23:07:30.679390 TIME STAMP 5. 0xfff7a000 0x00000910
9111 23:07:30.682637 VBOOT WORK 6. 0xfff66000 0x00014000
9112 23:07:30.686388 RAMOOPS 7. 0xffe66000 0x00100000
9113 23:07:30.689161 COREBOOT 8. 0xffe64000 0x00002000
9114 23:07:30.692314 IMD small region:
9115 23:07:30.695708 IMD ROOT 0. 0xffffec00 0x00000400
9116 23:07:30.698913 VPD 1. 0xffffeb80 0x0000006c
9117 23:07:30.702336 MMC STATUS 2. 0xffffeb60 0x00000004
9118 23:07:30.705683 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9119 23:07:30.709035 Probing TPM: done!
9120 23:07:30.712600 Connected to device vid:did:rid of 1ae0:0028:00
9121 23:07:30.723150 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
9122 23:07:30.726601 Initialized TPM device CR50 revision 0
9123 23:07:30.729985 Checking cr50 for pending updates
9124 23:07:30.733687 Reading cr50 TPM mode
9125 23:07:30.742032 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9126 23:07:30.748943 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9127 23:07:30.788965 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9128 23:07:30.791974 Checking segment from ROM address 0x40100000
9129 23:07:30.795583 Checking segment from ROM address 0x4010001c
9130 23:07:30.802202 Loading segment from ROM address 0x40100000
9131 23:07:30.802298 code (compression=0)
9132 23:07:30.812278 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9133 23:07:30.818820 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9134 23:07:30.818925 it's not compressed!
9135 23:07:30.825408 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9136 23:07:30.828796 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9137 23:07:30.849439 Loading segment from ROM address 0x4010001c
9138 23:07:30.849586 Entry Point 0x80000000
9139 23:07:30.852594 Loaded segments
9140 23:07:30.855688 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9141 23:07:30.862477 Jumping to boot code at 0x80000000(0xffe64000)
9142 23:07:30.869095 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9143 23:07:30.875704 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9144 23:07:30.883746 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9145 23:07:30.886974 Checking segment from ROM address 0x40100000
9146 23:07:30.890562 Checking segment from ROM address 0x4010001c
9147 23:07:30.897068 Loading segment from ROM address 0x40100000
9148 23:07:30.897159 code (compression=1)
9149 23:07:30.903685 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9150 23:07:30.913949 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9151 23:07:30.914027 using LZMA
9152 23:07:30.922060 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9153 23:07:30.928975 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9154 23:07:30.931951 Loading segment from ROM address 0x4010001c
9155 23:07:30.932024 Entry Point 0x54601000
9156 23:07:30.935385 Loaded segments
9157 23:07:30.938984 NOTICE: MT8192 bl31_setup
9158 23:07:30.945650 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9159 23:07:30.948996 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9160 23:07:30.952137 WARNING: region 0:
9161 23:07:30.955779 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9162 23:07:30.955877 WARNING: region 1:
9163 23:07:30.962412 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9164 23:07:30.965633 WARNING: region 2:
9165 23:07:30.969255 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9166 23:07:30.972376 WARNING: region 3:
9167 23:07:30.975489 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9168 23:07:30.978676 WARNING: region 4:
9169 23:07:30.985248 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9170 23:07:30.985347 WARNING: region 5:
9171 23:07:30.988800 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9172 23:07:30.992341 WARNING: region 6:
9173 23:07:30.995287 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9174 23:07:30.999085 WARNING: region 7:
9175 23:07:31.001972 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9176 23:07:31.008904 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9177 23:07:31.011995 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9178 23:07:31.015255 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9179 23:07:31.022423 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9180 23:07:31.025605 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9181 23:07:31.028798 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9182 23:07:31.035345 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9183 23:07:31.038906 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9184 23:07:31.045567 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9185 23:07:31.049007 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9186 23:07:31.052271 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9187 23:07:31.058782 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9188 23:07:31.061795 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9189 23:07:31.065167 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9190 23:07:31.072018 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9191 23:07:31.075146 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9192 23:07:31.081960 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9193 23:07:31.085286 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9194 23:07:31.088466 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9195 23:07:31.095369 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9196 23:07:31.098640 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9197 23:07:31.102381 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9198 23:07:31.108659 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9199 23:07:31.112300 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9200 23:07:31.118729 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9201 23:07:31.122074 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9202 23:07:31.125299 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9203 23:07:31.131862 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9204 23:07:31.135647 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9205 23:07:31.142652 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9206 23:07:31.145908 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9207 23:07:31.148987 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9208 23:07:31.155511 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9209 23:07:31.159081 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9210 23:07:31.162029 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9211 23:07:31.165538 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9212 23:07:31.172135 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9213 23:07:31.175229 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9214 23:07:31.178540 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9215 23:07:31.181848 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9216 23:07:31.188535 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9217 23:07:31.192033 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9218 23:07:31.195351 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9219 23:07:31.198954 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9220 23:07:31.205434 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9221 23:07:31.208627 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9222 23:07:31.211983 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9223 23:07:31.215249 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9224 23:07:31.221914 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9225 23:07:31.225373 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9226 23:07:31.232149 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9227 23:07:31.235241 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9228 23:07:31.241583 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9229 23:07:31.244956 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9230 23:07:31.248406 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9231 23:07:31.255182 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9232 23:07:31.258420 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9233 23:07:31.264996 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9234 23:07:31.268458 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9235 23:07:31.275390 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9236 23:07:31.278753 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9237 23:07:31.281748 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9238 23:07:31.288446 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9239 23:07:31.291677 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9240 23:07:31.298514 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9241 23:07:31.301775 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9242 23:07:31.308644 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9243 23:07:31.311826 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9244 23:07:31.315219 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9245 23:07:31.321838 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9246 23:07:31.325032 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9247 23:07:31.331609 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9248 23:07:31.335267 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9249 23:07:31.341791 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9250 23:07:31.344947 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9251 23:07:31.351519 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9252 23:07:31.354787 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9253 23:07:31.358288 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9254 23:07:31.364972 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9255 23:07:31.368287 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9256 23:07:31.375005 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9257 23:07:31.378125 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9258 23:07:31.384989 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9259 23:07:31.388119 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9260 23:07:31.391433 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9261 23:07:31.397956 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9262 23:07:31.401570 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9263 23:07:31.407929 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9264 23:07:31.411519 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9265 23:07:31.417922 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9266 23:07:31.421560 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9267 23:07:31.424850 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9268 23:07:31.431893 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9269 23:07:31.434874 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9270 23:07:31.441085 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9271 23:07:31.444511 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9272 23:07:31.451493 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9273 23:07:31.454598 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9274 23:07:31.457997 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9275 23:07:31.461456 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9276 23:07:31.468078 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9277 23:07:31.471517 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9278 23:07:31.474599 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9279 23:07:31.481404 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9280 23:07:31.484601 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9281 23:07:31.491370 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9282 23:07:31.494536 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9283 23:07:31.497917 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9284 23:07:31.504516 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9285 23:07:31.507913 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9286 23:07:31.511472 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9287 23:07:31.517757 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9288 23:07:31.521591 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9289 23:07:31.528324 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9290 23:07:31.531605 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9291 23:07:31.534505 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9292 23:07:31.541173 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9293 23:07:31.544620 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9294 23:07:31.547982 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9295 23:07:31.554502 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9296 23:07:31.557793 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9297 23:07:31.561217 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9298 23:07:31.564840 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9299 23:07:31.571343 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9300 23:07:31.574706 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9301 23:07:31.578021 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9302 23:07:31.584545 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9303 23:07:31.588091 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9304 23:07:31.594661 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9305 23:07:31.598294 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9306 23:07:31.601206 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9307 23:07:31.608103 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9308 23:07:31.611625 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9309 23:07:31.614521 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9310 23:07:31.621106 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9311 23:07:31.624510 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9312 23:07:31.631200 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9313 23:07:31.634498 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9314 23:07:31.637819 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9315 23:07:31.644498 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9316 23:07:31.647928 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9317 23:07:31.654669 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9318 23:07:31.658193 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9319 23:07:31.661304 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9320 23:07:31.667887 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9321 23:07:31.671221 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9322 23:07:31.674727 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9323 23:07:31.681327 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9324 23:07:31.684548 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9325 23:07:31.691026 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9326 23:07:31.694513 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9327 23:07:31.697730 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9328 23:07:31.704392 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9329 23:07:31.707652 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9330 23:07:31.714341 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9331 23:07:31.717939 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9332 23:07:31.721067 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9333 23:07:31.727795 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9334 23:07:31.731441 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9335 23:07:31.734376 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9336 23:07:31.740983 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9337 23:07:31.744520 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9338 23:07:31.751119 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9339 23:07:31.754409 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9340 23:07:31.757708 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9341 23:07:31.764670 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9342 23:07:31.767594 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9343 23:07:31.774610 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9344 23:07:31.777690 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9345 23:07:31.781287 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9346 23:07:31.787471 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9347 23:07:31.790663 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9348 23:07:31.797478 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9349 23:07:31.800669 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9350 23:07:31.803784 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9351 23:07:31.810509 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9352 23:07:31.813801 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9353 23:07:31.820377 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9354 23:07:31.824009 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9355 23:07:31.827095 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9356 23:07:31.833763 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9357 23:07:31.837006 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9358 23:07:31.843640 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9359 23:07:31.847134 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9360 23:07:31.850149 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9361 23:07:31.856840 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9362 23:07:31.860254 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9363 23:07:31.866871 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9364 23:07:31.869997 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9365 23:07:31.873362 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9366 23:07:31.880496 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9367 23:07:31.883449 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9368 23:07:31.890173 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9369 23:07:31.893363 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9370 23:07:31.896610 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9371 23:07:31.903477 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9372 23:07:31.906559 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9373 23:07:31.913059 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9374 23:07:31.916681 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9375 23:07:31.923062 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9376 23:07:31.926370 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9377 23:07:31.929771 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9378 23:07:31.936228 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9379 23:07:31.939693 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9380 23:07:31.946398 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9381 23:07:31.949714 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9382 23:07:31.956100 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9383 23:07:31.959509 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9384 23:07:31.962773 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9385 23:07:31.969395 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9386 23:07:31.972858 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9387 23:07:31.979679 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9388 23:07:31.982557 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9389 23:07:31.989524 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9390 23:07:31.992626 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9391 23:07:31.995943 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9392 23:07:32.002564 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9393 23:07:32.005927 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9394 23:07:32.012639 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9395 23:07:32.015745 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9396 23:07:32.019197 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9397 23:07:32.026004 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9398 23:07:32.029145 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9399 23:07:32.035725 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9400 23:07:32.039083 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9401 23:07:32.045825 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9402 23:07:32.049319 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9403 23:07:32.052331 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9404 23:07:32.058893 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9405 23:07:32.062227 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9406 23:07:32.065339 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9407 23:07:32.068515 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9408 23:07:32.075309 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9409 23:07:32.078625 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9410 23:07:32.081962 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9411 23:07:32.088559 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9412 23:07:32.092152 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9413 23:07:32.098482 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9414 23:07:32.101913 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9415 23:07:32.105363 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9416 23:07:32.111735 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9417 23:07:32.115127 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9418 23:07:32.118571 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9419 23:07:32.125200 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9420 23:07:32.128535 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9421 23:07:32.131681 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9422 23:07:32.138466 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9423 23:07:32.141651 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9424 23:07:32.145152 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9425 23:07:32.151919 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9426 23:07:32.154856 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9427 23:07:32.161528 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9428 23:07:32.165024 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9429 23:07:32.168116 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9430 23:07:32.175240 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9431 23:07:32.178025 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9432 23:07:32.181291 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9433 23:07:32.187901 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9434 23:07:32.191241 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9435 23:07:32.194606 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9436 23:07:32.201270 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9437 23:07:32.204623 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9438 23:07:32.211446 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9439 23:07:32.214443 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9440 23:07:32.218037 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9441 23:07:32.224174 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9442 23:07:32.227620 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9443 23:07:32.234418 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9444 23:07:32.237989 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9445 23:07:32.240815 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9446 23:07:32.244197 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9447 23:07:32.247991 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9448 23:07:32.253963 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9449 23:07:32.257802 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9450 23:07:32.260518 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9451 23:07:32.264143 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9452 23:07:32.270524 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9453 23:07:32.274158 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9454 23:07:32.277131 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9455 23:07:32.280684 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9456 23:07:32.287000 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9457 23:07:32.290337 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9458 23:07:32.297253 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9459 23:07:32.300550 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9460 23:07:32.303662 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9461 23:07:32.310357 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9462 23:07:32.313800 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9463 23:07:32.320768 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9464 23:07:32.323728 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9465 23:07:32.327212 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9466 23:07:32.333672 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9467 23:07:32.337064 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9468 23:07:32.343486 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9469 23:07:32.347249 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9470 23:07:32.350274 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9471 23:07:32.356944 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9472 23:07:32.360899 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9473 23:07:32.366988 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9474 23:07:32.370155 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9475 23:07:32.373838 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9476 23:07:32.379895 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9477 23:07:32.383459 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9478 23:07:32.390023 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9479 23:07:32.393451 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9480 23:07:32.399693 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9481 23:07:32.403033 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9482 23:07:32.406377 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9483 23:07:32.413230 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9484 23:07:32.416282 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9485 23:07:32.423025 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9486 23:07:32.426240 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9487 23:07:32.432947 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9488 23:07:32.436244 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9489 23:07:32.439551 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9490 23:07:32.445959 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9491 23:07:32.449670 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9492 23:07:32.456270 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9493 23:07:32.459597 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9494 23:07:32.462434 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9495 23:07:32.469063 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9496 23:07:32.472345 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9497 23:07:32.479438 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9498 23:07:32.482273 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9499 23:07:32.485732 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9500 23:07:32.492560 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9501 23:07:32.495854 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9502 23:07:32.502324 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9503 23:07:32.505900 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9504 23:07:32.512322 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9505 23:07:32.515508 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9506 23:07:32.518602 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9507 23:07:32.525607 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9508 23:07:32.528428 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9509 23:07:32.535356 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9510 23:07:32.538619 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9511 23:07:32.545083 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9512 23:07:32.548568 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9513 23:07:32.551869 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9514 23:07:32.558496 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9515 23:07:32.561634 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9516 23:07:32.568464 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9517 23:07:32.571445 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9518 23:07:32.575011 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9519 23:07:32.581688 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9520 23:07:32.584739 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9521 23:07:32.591581 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9522 23:07:32.594567 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9523 23:07:32.598097 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9524 23:07:32.604492 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9525 23:07:32.607822 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9526 23:07:32.614544 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9527 23:07:32.617878 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9528 23:07:32.624634 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9529 23:07:32.627995 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9530 23:07:32.631515 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9531 23:07:32.637698 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9532 23:07:32.640969 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9533 23:07:32.647714 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9534 23:07:32.651081 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9535 23:07:32.657606 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9536 23:07:32.660932 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9537 23:07:32.664398 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9538 23:07:32.670809 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9539 23:07:32.674121 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9540 23:07:32.680580 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9541 23:07:32.683939 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9542 23:07:32.690506 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9543 23:07:32.693916 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9544 23:07:32.700494 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9545 23:07:32.703898 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9546 23:07:32.707256 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9547 23:07:32.713687 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9548 23:07:32.716953 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9549 23:07:32.723574 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9550 23:07:32.726911 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9551 23:07:32.733395 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9552 23:07:32.736914 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9553 23:07:32.740039 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9554 23:07:32.746592 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9555 23:07:32.750015 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9556 23:07:32.756873 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9557 23:07:32.760288 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9558 23:07:32.766559 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9559 23:07:32.769761 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9560 23:07:32.776129 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9561 23:07:32.779572 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9562 23:07:32.782909 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9563 23:07:32.789642 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9564 23:07:32.792995 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9565 23:07:32.799512 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9566 23:07:32.802919 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9567 23:07:32.809615 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9568 23:07:32.812860 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9569 23:07:32.816127 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9570 23:07:32.823400 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9571 23:07:32.826231 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9572 23:07:32.833100 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9573 23:07:32.836026 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9574 23:07:32.842723 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9575 23:07:32.846033 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9576 23:07:32.852425 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9577 23:07:32.855990 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9578 23:07:32.859063 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9579 23:07:32.865593 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9580 23:07:32.869249 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9581 23:07:32.876261 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9582 23:07:32.879295 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9583 23:07:32.885460 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9584 23:07:32.888623 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9585 23:07:32.895575 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9586 23:07:32.898635 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9587 23:07:32.905715 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9588 23:07:32.908714 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9589 23:07:32.915085 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9590 23:07:32.918525 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9591 23:07:32.925237 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9592 23:07:32.928337 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9593 23:07:32.935078 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9594 23:07:32.938520 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9595 23:07:32.944987 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9596 23:07:32.948485 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9597 23:07:32.951929 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9598 23:07:32.958123 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9599 23:07:32.964804 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9600 23:07:32.968181 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9601 23:07:32.974683 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9602 23:07:32.977933 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9603 23:07:32.984872 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9604 23:07:32.988122 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9605 23:07:32.994457 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9606 23:07:32.997798 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9607 23:07:33.004339 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9608 23:07:33.007767 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9609 23:07:33.014236 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9610 23:07:33.018025 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9611 23:07:33.021132 INFO: [APUAPC] vio 0
9612 23:07:33.024406 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9613 23:07:33.031044 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9614 23:07:33.031118 INFO: [APUAPC] D0_APC_0: 0x400510
9615 23:07:33.034106 INFO: [APUAPC] D0_APC_1: 0x0
9616 23:07:33.037503 INFO: [APUAPC] D0_APC_2: 0x1540
9617 23:07:33.040693 INFO: [APUAPC] D0_APC_3: 0x0
9618 23:07:33.044030 INFO: [APUAPC] D1_APC_0: 0xffffffff
9619 23:07:33.047454 INFO: [APUAPC] D1_APC_1: 0xffffffff
9620 23:07:33.050657 INFO: [APUAPC] D1_APC_2: 0x3fffff
9621 23:07:33.054751 INFO: [APUAPC] D1_APC_3: 0x0
9622 23:07:33.057570 INFO: [APUAPC] D2_APC_0: 0xffffffff
9623 23:07:33.060722 INFO: [APUAPC] D2_APC_1: 0xffffffff
9624 23:07:33.063951 INFO: [APUAPC] D2_APC_2: 0x3fffff
9625 23:07:33.067279 INFO: [APUAPC] D2_APC_3: 0x0
9626 23:07:33.070646 INFO: [APUAPC] D3_APC_0: 0xffffffff
9627 23:07:33.073895 INFO: [APUAPC] D3_APC_1: 0xffffffff
9628 23:07:33.077183 INFO: [APUAPC] D3_APC_2: 0x3fffff
9629 23:07:33.080588 INFO: [APUAPC] D3_APC_3: 0x0
9630 23:07:33.083754 INFO: [APUAPC] D4_APC_0: 0xffffffff
9631 23:07:33.087093 INFO: [APUAPC] D4_APC_1: 0xffffffff
9632 23:07:33.090372 INFO: [APUAPC] D4_APC_2: 0x3fffff
9633 23:07:33.093835 INFO: [APUAPC] D4_APC_3: 0x0
9634 23:07:33.097100 INFO: [APUAPC] D5_APC_0: 0xffffffff
9635 23:07:33.100205 INFO: [APUAPC] D5_APC_1: 0xffffffff
9636 23:07:33.103403 INFO: [APUAPC] D5_APC_2: 0x3fffff
9637 23:07:33.106989 INFO: [APUAPC] D5_APC_3: 0x0
9638 23:07:33.110262 INFO: [APUAPC] D6_APC_0: 0xffffffff
9639 23:07:33.113389 INFO: [APUAPC] D6_APC_1: 0xffffffff
9640 23:07:33.116821 INFO: [APUAPC] D6_APC_2: 0x3fffff
9641 23:07:33.120181 INFO: [APUAPC] D6_APC_3: 0x0
9642 23:07:33.123330 INFO: [APUAPC] D7_APC_0: 0xffffffff
9643 23:07:33.126555 INFO: [APUAPC] D7_APC_1: 0xffffffff
9644 23:07:33.129795 INFO: [APUAPC] D7_APC_2: 0x3fffff
9645 23:07:33.132953 INFO: [APUAPC] D7_APC_3: 0x0
9646 23:07:33.136662 INFO: [APUAPC] D8_APC_0: 0xffffffff
9647 23:07:33.140020 INFO: [APUAPC] D8_APC_1: 0xffffffff
9648 23:07:33.142885 INFO: [APUAPC] D8_APC_2: 0x3fffff
9649 23:07:33.146267 INFO: [APUAPC] D8_APC_3: 0x0
9650 23:07:33.149726 INFO: [APUAPC] D9_APC_0: 0xffffffff
9651 23:07:33.152907 INFO: [APUAPC] D9_APC_1: 0xffffffff
9652 23:07:33.156225 INFO: [APUAPC] D9_APC_2: 0x3fffff
9653 23:07:33.159921 INFO: [APUAPC] D9_APC_3: 0x0
9654 23:07:33.162785 INFO: [APUAPC] D10_APC_0: 0xffffffff
9655 23:07:33.166074 INFO: [APUAPC] D10_APC_1: 0xffffffff
9656 23:07:33.169422 INFO: [APUAPC] D10_APC_2: 0x3fffff
9657 23:07:33.172894 INFO: [APUAPC] D10_APC_3: 0x0
9658 23:07:33.176210 INFO: [APUAPC] D11_APC_0: 0xffffffff
9659 23:07:33.179465 INFO: [APUAPC] D11_APC_1: 0xffffffff
9660 23:07:33.182979 INFO: [APUAPC] D11_APC_2: 0x3fffff
9661 23:07:33.186152 INFO: [APUAPC] D11_APC_3: 0x0
9662 23:07:33.189532 INFO: [APUAPC] D12_APC_0: 0xffffffff
9663 23:07:33.192800 INFO: [APUAPC] D12_APC_1: 0xffffffff
9664 23:07:33.195853 INFO: [APUAPC] D12_APC_2: 0x3fffff
9665 23:07:33.199320 INFO: [APUAPC] D12_APC_3: 0x0
9666 23:07:33.202479 INFO: [APUAPC] D13_APC_0: 0xffffffff
9667 23:07:33.205925 INFO: [APUAPC] D13_APC_1: 0xffffffff
9668 23:07:33.209071 INFO: [APUAPC] D13_APC_2: 0x3fffff
9669 23:07:33.212570 INFO: [APUAPC] D13_APC_3: 0x0
9670 23:07:33.216047 INFO: [APUAPC] D14_APC_0: 0xffffffff
9671 23:07:33.218931 INFO: [APUAPC] D14_APC_1: 0xffffffff
9672 23:07:33.222942 INFO: [APUAPC] D14_APC_2: 0x3fffff
9673 23:07:33.225719 INFO: [APUAPC] D14_APC_3: 0x0
9674 23:07:33.228894 INFO: [APUAPC] D15_APC_0: 0xffffffff
9675 23:07:33.232273 INFO: [APUAPC] D15_APC_1: 0xffffffff
9676 23:07:33.235380 INFO: [APUAPC] D15_APC_2: 0x3fffff
9677 23:07:33.238991 INFO: [APUAPC] D15_APC_3: 0x0
9678 23:07:33.242235 INFO: [APUAPC] APC_CON: 0x4
9679 23:07:33.245461 INFO: [NOCDAPC] D0_APC_0: 0x0
9680 23:07:33.245535 INFO: [NOCDAPC] D0_APC_1: 0x0
9681 23:07:33.249094 INFO: [NOCDAPC] D1_APC_0: 0x0
9682 23:07:33.252105 INFO: [NOCDAPC] D1_APC_1: 0xfff
9683 23:07:33.255562 INFO: [NOCDAPC] D2_APC_0: 0x0
9684 23:07:33.258725 INFO: [NOCDAPC] D2_APC_1: 0xfff
9685 23:07:33.262183 INFO: [NOCDAPC] D3_APC_0: 0x0
9686 23:07:33.265427 INFO: [NOCDAPC] D3_APC_1: 0xfff
9687 23:07:33.268850 INFO: [NOCDAPC] D4_APC_0: 0x0
9688 23:07:33.272027 INFO: [NOCDAPC] D4_APC_1: 0xfff
9689 23:07:33.275468 INFO: [NOCDAPC] D5_APC_0: 0x0
9690 23:07:33.278796 INFO: [NOCDAPC] D5_APC_1: 0xfff
9691 23:07:33.278866 INFO: [NOCDAPC] D6_APC_0: 0x0
9692 23:07:33.281824 INFO: [NOCDAPC] D6_APC_1: 0xfff
9693 23:07:33.285066 INFO: [NOCDAPC] D7_APC_0: 0x0
9694 23:07:33.288433 INFO: [NOCDAPC] D7_APC_1: 0xfff
9695 23:07:33.291777 INFO: [NOCDAPC] D8_APC_0: 0x0
9696 23:07:33.295082 INFO: [NOCDAPC] D8_APC_1: 0xfff
9697 23:07:33.298264 INFO: [NOCDAPC] D9_APC_0: 0x0
9698 23:07:33.301872 INFO: [NOCDAPC] D9_APC_1: 0xfff
9699 23:07:33.304980 INFO: [NOCDAPC] D10_APC_0: 0x0
9700 23:07:33.308234 INFO: [NOCDAPC] D10_APC_1: 0xfff
9701 23:07:33.311688 INFO: [NOCDAPC] D11_APC_0: 0x0
9702 23:07:33.314806 INFO: [NOCDAPC] D11_APC_1: 0xfff
9703 23:07:33.318297 INFO: [NOCDAPC] D12_APC_0: 0x0
9704 23:07:33.321581 INFO: [NOCDAPC] D12_APC_1: 0xfff
9705 23:07:33.321660 INFO: [NOCDAPC] D13_APC_0: 0x0
9706 23:07:33.324875 INFO: [NOCDAPC] D13_APC_1: 0xfff
9707 23:07:33.328432 INFO: [NOCDAPC] D14_APC_0: 0x0
9708 23:07:33.331501 INFO: [NOCDAPC] D14_APC_1: 0xfff
9709 23:07:33.335154 INFO: [NOCDAPC] D15_APC_0: 0x0
9710 23:07:33.338130 INFO: [NOCDAPC] D15_APC_1: 0xfff
9711 23:07:33.341505 INFO: [NOCDAPC] APC_CON: 0x4
9712 23:07:33.344792 INFO: [APUAPC] set_apusys_apc done
9713 23:07:33.348205 INFO: [DEVAPC] devapc_init done
9714 23:07:33.351407 INFO: GICv3 without legacy support detected.
9715 23:07:33.354657 INFO: ARM GICv3 driver initialized in EL3
9716 23:07:33.361204 INFO: Maximum SPI INTID supported: 639
9717 23:07:33.364529 INFO: BL31: Initializing runtime services
9718 23:07:33.371507 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9719 23:07:33.371584 INFO: SPM: enable CPC mode
9720 23:07:33.377809 INFO: mcdi ready for mcusys-off-idle and system suspend
9721 23:07:33.381363 INFO: BL31: Preparing for EL3 exit to normal world
9722 23:07:33.384476 INFO: Entry point address = 0x80000000
9723 23:07:33.387438 INFO: SPSR = 0x8
9724 23:07:33.393458
9725 23:07:33.393531
9726 23:07:33.393593
9727 23:07:33.396853 Starting depthcharge on Spherion...
9728 23:07:33.396980
9729 23:07:33.397092 Wipe memory regions:
9730 23:07:33.397209
9731 23:07:33.398191 end: 2.2.3 depthcharge-start (duration 00:00:28) [common]
9732 23:07:33.398298 start: 2.2.4 bootloader-commands (timeout 00:04:26) [common]
9733 23:07:33.398380 Setting prompt string to ['asurada:']
9734 23:07:33.398465 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:26)
9735 23:07:33.399877 [0x00000040000000, 0x00000054600000)
9736 23:07:33.522663
9737 23:07:33.522777 [0x00000054660000, 0x00000080000000)
9738 23:07:33.782646
9739 23:07:33.782770 [0x000000821a7280, 0x000000ffe64000)
9740 23:07:34.527208
9741 23:07:34.527355 [0x00000100000000, 0x00000140000000)
9742 23:07:34.906607
9743 23:07:34.910006 Initializing XHCI USB controller at 0x11200000.
9744 23:07:35.947418
9745 23:07:35.950658 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
9746 23:07:35.950767
9747 23:07:35.950864
9748 23:07:35.950953
9749 23:07:35.951256 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9751 23:07:36.051545 asurada: tftpboot 192.168.201.1 12395367/tftp-deploy-jpgcxkez/kernel/image.itb 12395367/tftp-deploy-jpgcxkez/kernel/cmdline
9752 23:07:36.051668 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9753 23:07:36.051765 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:24)
9754 23:07:36.055943 tftpboot 192.168.201.1 12395367/tftp-deploy-jpgcxkez/kernel/image.itp-deploy-jpgcxkez/kernel/cmdline
9755 23:07:36.056024
9756 23:07:36.056089 Waiting for link
9757 23:07:36.216310
9758 23:07:36.216426 R8152: Initializing
9759 23:07:36.216500
9760 23:07:36.219623 Version 9 (ocp_data = 6010)
9761 23:07:36.219710
9762 23:07:36.222840 R8152: Done initializing
9763 23:07:36.222912
9764 23:07:36.222976 Adding net device
9765 23:07:38.361177
9766 23:07:38.361321 done.
9767 23:07:38.361389
9768 23:07:38.361450 MAC: 00:e0:4c:68:03:bd
9769 23:07:38.361508
9770 23:07:38.364594 Sending DHCP discover... done.
9771 23:07:38.364670
9772 23:07:38.367791 Waiting for reply... done.
9773 23:07:38.367873
9774 23:07:38.371195 Sending DHCP request... done.
9775 23:07:38.371267
9776 23:07:38.376510 Waiting for reply... done.
9777 23:07:38.376589
9778 23:07:38.376653 My ip is 192.168.201.16
9779 23:07:38.376721
9780 23:07:38.379961 The DHCP server ip is 192.168.201.1
9781 23:07:38.380054
9782 23:07:38.386528 TFTP server IP predefined by user: 192.168.201.1
9783 23:07:38.386602
9784 23:07:38.393150 Bootfile predefined by user: 12395367/tftp-deploy-jpgcxkez/kernel/image.itb
9785 23:07:38.393260
9786 23:07:38.396425 Sending tftp read request... done.
9787 23:07:38.396505
9788 23:07:38.399981 Waiting for the transfer...
9789 23:07:38.400068
9790 23:07:38.655806 00000000 ################################################################
9791 23:07:38.655942
9792 23:07:38.916654 00080000 ################################################################
9793 23:07:38.916814
9794 23:07:39.178064 00100000 ################################################################
9795 23:07:39.178196
9796 23:07:39.438035 00180000 ################################################################
9797 23:07:39.438169
9798 23:07:39.694765 00200000 ################################################################
9799 23:07:39.694924
9800 23:07:39.951107 00280000 ################################################################
9801 23:07:39.951242
9802 23:07:40.207501 00300000 ################################################################
9803 23:07:40.207642
9804 23:07:40.462997 00380000 ################################################################
9805 23:07:40.463129
9806 23:07:40.729285 00400000 ################################################################
9807 23:07:40.729423
9808 23:07:40.991611 00480000 ################################################################
9809 23:07:40.991752
9810 23:07:41.254296 00500000 ################################################################
9811 23:07:41.254433
9812 23:07:41.516404 00580000 ################################################################
9813 23:07:41.516538
9814 23:07:41.779159 00600000 ################################################################
9815 23:07:41.779292
9816 23:07:42.041849 00680000 ################################################################
9817 23:07:42.041981
9818 23:07:42.297968 00700000 ################################################################
9819 23:07:42.298100
9820 23:07:42.553192 00780000 ################################################################
9821 23:07:42.553321
9822 23:07:42.807285 00800000 ################################################################
9823 23:07:42.807425
9824 23:07:43.066350 00880000 ################################################################
9825 23:07:43.066490
9826 23:07:43.332726 00900000 ################################################################
9827 23:07:43.332885
9828 23:07:43.605856 00980000 ################################################################
9829 23:07:43.605991
9830 23:07:43.860171 00a00000 ################################################################
9831 23:07:43.860317
9832 23:07:44.114162 00a80000 ################################################################
9833 23:07:44.114295
9834 23:07:44.370621 00b00000 ################################################################
9835 23:07:44.370758
9836 23:07:44.654958 00b80000 ################################################################
9837 23:07:44.655099
9838 23:07:44.938616 00c00000 ################################################################
9839 23:07:44.938748
9840 23:07:45.205978 00c80000 ################################################################
9841 23:07:45.206129
9842 23:07:45.458473 00d00000 ################################################################
9843 23:07:45.458614
9844 23:07:45.709971 00d80000 ################################################################
9845 23:07:45.710140
9846 23:07:45.972539 00e00000 ################################################################
9847 23:07:45.972699
9848 23:07:46.262411 00e80000 ################################################################
9849 23:07:46.262545
9850 23:07:46.552585 00f00000 ################################################################
9851 23:07:46.552766
9852 23:07:46.848938 00f80000 ################################################################
9853 23:07:46.849067
9854 23:07:47.132591 01000000 ################################################################
9855 23:07:47.132762
9856 23:07:47.405939 01080000 ################################################################
9857 23:07:47.406071
9858 23:07:47.667185 01100000 ################################################################
9859 23:07:47.667317
9860 23:07:47.935922 01180000 ################################################################
9861 23:07:47.936049
9862 23:07:48.221025 01200000 ################################################################
9863 23:07:48.221163
9864 23:07:48.490637 01280000 ################################################################
9865 23:07:48.490773
9866 23:07:48.761359 01300000 ################################################################
9867 23:07:48.761499
9868 23:07:49.044010 01380000 ################################################################
9869 23:07:49.044151
9870 23:07:49.309195 01400000 ################################################################
9871 23:07:49.309327
9872 23:07:49.569020 01480000 ################################################################
9873 23:07:49.569148
9874 23:07:49.822398 01500000 ################################################################
9875 23:07:49.822555
9876 23:07:50.095546 01580000 ################################################################
9877 23:07:50.095685
9878 23:07:50.349423 01600000 ################################################################
9879 23:07:50.349553
9880 23:07:50.620587 01680000 ################################################################
9881 23:07:50.620778
9882 23:07:50.882341 01700000 ################################################################
9883 23:07:50.882474
9884 23:07:51.155156 01780000 ################################################################
9885 23:07:51.155291
9886 23:07:51.451301 01800000 ################################################################
9887 23:07:51.451442
9888 23:07:51.747680 01880000 ################################################################
9889 23:07:51.747816
9890 23:07:52.017246 01900000 ################################################################
9891 23:07:52.017391
9892 23:07:52.286375 01980000 ################################################################
9893 23:07:52.286509
9894 23:07:52.548866 01a00000 ################################################################
9895 23:07:52.548999
9896 23:07:52.818131 01a80000 ################################################################
9897 23:07:52.818266
9898 23:07:53.113269 01b00000 ################################################################
9899 23:07:53.113415
9900 23:07:53.401040 01b80000 ################################################################
9901 23:07:53.401188
9902 23:07:53.673502 01c00000 ################################################################
9903 23:07:53.673631
9904 23:07:53.936009 01c80000 ################################################################
9905 23:07:53.936138
9906 23:07:54.218521 01d00000 ################################################################
9907 23:07:54.218664
9908 23:07:54.505876 01d80000 ################################################################
9909 23:07:54.506016
9910 23:07:54.793877 01e00000 ################################################################
9911 23:07:54.794015
9912 23:07:55.087768 01e80000 ################################################################
9913 23:07:55.087903
9914 23:07:55.380642 01f00000 ################################################################
9915 23:07:55.380818
9916 23:07:55.671019 01f80000 ################################################################
9917 23:07:55.671170
9918 23:07:55.955503 02000000 ################################################################
9919 23:07:55.955641
9920 23:07:56.241998 02080000 ################################################################
9921 23:07:56.242136
9922 23:07:56.536543 02100000 ################################################################
9923 23:07:56.536690
9924 23:07:56.804653 02180000 ################################################################
9925 23:07:56.804796
9926 23:07:57.075830 02200000 ################################################################
9927 23:07:57.075965
9928 23:07:57.370792 02280000 ################################################################
9929 23:07:57.370929
9930 23:07:57.683800 02300000 ################################################################
9931 23:07:57.683950
9932 23:07:57.952212 02380000 ################################################################
9933 23:07:57.952345
9934 23:07:58.203496 02400000 ################################################################
9935 23:07:58.203627
9936 23:07:58.477315 02480000 ################################################################
9937 23:07:58.477451
9938 23:07:58.771191 02500000 ################################################################
9939 23:07:58.771331
9940 23:07:59.067086 02580000 ################################################################
9941 23:07:59.067225
9942 23:07:59.345577 02600000 ################################################################
9943 23:07:59.345713
9944 23:07:59.604060 02680000 ################################################################
9945 23:07:59.604220
9946 23:07:59.862572 02700000 ################################################################
9947 23:07:59.862710
9948 23:08:00.123734 02780000 ################################################################
9949 23:08:00.123861
9950 23:08:00.381871 02800000 ################################################################
9951 23:08:00.382001
9952 23:08:00.672640 02880000 ################################################################
9953 23:08:00.672799
9954 23:08:00.936001 02900000 ################################################################
9955 23:08:00.936161
9956 23:08:01.221516 02980000 ################################################################
9957 23:08:01.221674
9958 23:08:01.518621 02a00000 ################################################################
9959 23:08:01.518787
9960 23:08:01.795228 02a80000 ################################################################
9961 23:08:01.795385
9962 23:08:02.080129 02b00000 ################################################################
9963 23:08:02.080289
9964 23:08:02.372695 02b80000 ################################################################
9965 23:08:02.372879
9966 23:08:02.663554 02c00000 ################################################################
9967 23:08:02.663692
9968 23:08:02.935746 02c80000 ################################################################
9969 23:08:02.935882
9970 23:08:03.204358 02d00000 ################################################################
9971 23:08:03.204490
9972 23:08:03.468290 02d80000 ################################################################
9973 23:08:03.468417
9974 23:08:03.765163 02e00000 ################################################################
9975 23:08:03.765293
9976 23:08:04.056035 02e80000 ################################################################
9977 23:08:04.056167
9978 23:08:04.348767 02f00000 ################################################################
9979 23:08:04.348891
9980 23:08:04.631671 02f80000 ################################################################
9981 23:08:04.631798
9982 23:08:04.897219 03000000 ################################################################
9983 23:08:04.897348
9984 23:08:05.172963 03080000 ################################################################
9985 23:08:05.173090
9986 23:08:05.451700 03100000 ################################################################
9987 23:08:05.451828
9988 23:08:05.724266 03180000 ################################################################
9989 23:08:05.724392
9990 23:08:05.997317 03200000 ################################################################
9991 23:08:05.997444
9992 23:08:06.265710 03280000 ################################################################
9993 23:08:06.265842
9994 23:08:06.562450 03300000 ################################################################
9995 23:08:06.562579
9996 23:08:06.848961 03380000 ################################################################
9997 23:08:06.849097
9998 23:08:07.109609 03400000 ################################################################
9999 23:08:07.109739
10000 23:08:07.385738 03480000 ################################################################
10001 23:08:07.385873
10002 23:08:07.636822 03500000 ################################################################
10003 23:08:07.636949
10004 23:08:07.899542 03580000 ################################################################
10005 23:08:07.899673
10006 23:08:08.168641 03600000 ################################################################
10007 23:08:08.168786
10008 23:08:08.442230 03680000 ################################################################
10009 23:08:08.442368
10010 23:08:08.694711 03700000 ################################################################
10011 23:08:08.694846
10012 23:08:08.971053 03780000 ################################################################
10013 23:08:08.971180
10014 23:08:09.239341 03800000 ################################################################
10015 23:08:09.239488
10016 23:08:09.515893 03880000 ################################################################
10017 23:08:09.516023
10018 23:08:09.767679 03900000 ################################################################
10019 23:08:09.767823
10020 23:08:10.024602 03980000 ################################################################
10021 23:08:10.024763
10022 23:08:10.294859 03a00000 ################################################################
10023 23:08:10.295000
10024 23:08:10.565130 03a80000 ################################################################
10025 23:08:10.565263
10026 23:08:10.816674 03b00000 ################################################################
10027 23:08:10.816830
10028 23:08:11.088555 03b80000 ################################################################
10029 23:08:11.088691
10030 23:08:11.356743 03c00000 ################################################################
10031 23:08:11.356899
10032 23:08:11.616936 03c80000 ################################################################
10033 23:08:11.617068
10034 23:08:11.879538 03d00000 ################################################################
10035 23:08:11.879674
10036 23:08:12.150515 03d80000 ################################################################
10037 23:08:12.150649
10038 23:08:12.440732 03e00000 ################################################################
10039 23:08:12.440883
10040 23:08:12.735968 03e80000 ################################################################
10041 23:08:12.736101
10042 23:08:13.030750 03f00000 ################################################################
10043 23:08:13.030891
10044 23:08:13.306128 03f80000 ################################################################
10045 23:08:13.306269
10046 23:08:13.569693 04000000 ################################################################
10047 23:08:13.569825
10048 23:08:13.752183 04080000 ######################################### done.
10049 23:08:13.752668
10050 23:08:13.755178 The bootfile was 67961618 bytes long.
10051 23:08:13.755600
10052 23:08:13.758681 Sending tftp read request... done.
10053 23:08:13.759102
10054 23:08:13.761690 Waiting for the transfer...
10055 23:08:13.762114
10056 23:08:13.762446 00000000 # done.
10057 23:08:13.762764
10058 23:08:13.772269 Command line loaded dynamically from TFTP file: 12395367/tftp-deploy-jpgcxkez/kernel/cmdline
10059 23:08:13.772838
10060 23:08:13.784837 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10061 23:08:13.785281
10062 23:08:13.785616 Loading FIT.
10063 23:08:13.785929
10064 23:08:13.788447 Image ramdisk-1 has 56431919 bytes.
10065 23:08:13.788901
10066 23:08:13.791364 Image fdt-1 has 47278 bytes.
10067 23:08:13.791786
10068 23:08:13.794889 Image kernel-1 has 11480388 bytes.
10069 23:08:13.795377
10070 23:08:13.804794 Compat preference: google,spherion-rev3-sku1 google,spherion-rev3 google,spherion-sku1 google,spherion
10071 23:08:13.805327
10072 23:08:13.821405 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 (match) google,spherion-rev2 google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10073 23:08:13.821989
10074 23:08:13.827624 Choosing best match conf-1 for compat google,spherion-rev3.
10075 23:08:13.828138
10076 23:08:13.831281 Connected to device vid:did:rid of 1ae0:0028:00
10077 23:08:13.843198
10078 23:08:13.846307 tpm_get_response: command 0x17b, return code 0x0
10079 23:08:13.846733
10080 23:08:13.849839 ec_init: CrosEC protocol v3 supported (256, 248)
10081 23:08:13.854415
10082 23:08:13.857280 tpm_cleanup: add release locality here.
10083 23:08:13.857706
10084 23:08:13.858108 Shutting down all USB controllers.
10085 23:08:13.860628
10086 23:08:13.861099 Removing current net device
10087 23:08:13.861440
10088 23:08:13.867226 Exiting depthcharge with code 4 at timestamp: 68668153
10089 23:08:13.867647
10090 23:08:13.870582 LZMA decompressing kernel-1 to 0x821a6718
10091 23:08:13.871052
10092 23:08:13.874177 LZMA decompressing kernel-1 to 0x40000000
10093 23:08:15.309632
10094 23:08:15.310190 jumping to kernel
10095 23:08:15.312319 end: 2.2.4 bootloader-commands (duration 00:00:42) [common]
10096 23:08:15.312890 start: 2.2.5 auto-login-action (timeout 00:03:44) [common]
10097 23:08:15.313305 Setting prompt string to ['Linux version [0-9]']
10098 23:08:15.313686 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10099 23:08:15.314064 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10100 23:08:15.360048
10101 23:08:15.362904 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10102 23:08:15.366334 start: 2.2.5.1 login-action (timeout 00:03:44) [common]
10103 23:08:15.366657 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10104 23:08:15.366952 Setting prompt string to []
10105 23:08:15.367221 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10106 23:08:15.367463 Using line separator: #'\n'#
10107 23:08:15.367666 No login prompt set.
10108 23:08:15.367871 Parsing kernel messages
10109 23:08:15.368059 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10110 23:08:15.368397 [login-action] Waiting for messages, (timeout 00:03:44)
10111 23:08:15.386379 [ 0.000000] Linux version 6.1.67-cip12-rt7 (KernelCI@build-j59954-arm64-gcc-10-defconfig-arm64-chromebook-nblph) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Wed Dec 27 22:50:56 UTC 2023
10112 23:08:15.389434 [ 0.000000] random: crng init done
10113 23:08:15.395872 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10114 23:08:15.399270 [ 0.000000] efi: UEFI not found.
10115 23:08:15.406026 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10116 23:08:15.415919 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10117 23:08:15.425741 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10118 23:08:15.432472 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10119 23:08:15.439144 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10120 23:08:15.445511 [ 0.000000] printk: bootconsole [mtk8250] enabled
10121 23:08:15.452525 [ 0.000000] NUMA: No NUMA configuration found
10122 23:08:15.458870 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000013fffffff]
10123 23:08:15.465455 [ 0.000000] NUMA: NODE_DATA [mem 0x13f7d3a00-0x13f7d5fff]
10124 23:08:15.466044 [ 0.000000] Zone ranges:
10125 23:08:15.471970 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10126 23:08:15.474963 [ 0.000000] DMA32 empty
10127 23:08:15.482164 [ 0.000000] Normal [mem 0x0000000100000000-0x000000013fffffff]
10128 23:08:15.485402 [ 0.000000] Movable zone start for each node
10129 23:08:15.488596 [ 0.000000] Early memory node ranges
10130 23:08:15.495164 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10131 23:08:15.501414 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10132 23:08:15.508600 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10133 23:08:15.514775 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10134 23:08:15.521261 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000013fffffff]
10135 23:08:15.527980 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000013fffffff]
10136 23:08:15.558717 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10137 23:08:15.565376 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10138 23:08:15.571721 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10139 23:08:15.575213 [ 0.000000] psci: probing for conduit method from DT.
10140 23:08:15.581577 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10141 23:08:15.585551 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10142 23:08:15.591524 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10143 23:08:15.595093 [ 0.000000] psci: SMC Calling Convention v1.2
10144 23:08:15.601450 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10145 23:08:15.605048 [ 0.000000] Detected VIPT I-cache on CPU0
10146 23:08:15.611569 [ 0.000000] CPU features: detected: GIC system register CPU interface
10147 23:08:15.618059 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10148 23:08:15.624630 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10149 23:08:15.631423 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10150 23:08:15.637830 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10151 23:08:15.647786 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10152 23:08:15.650931 [ 0.000000] alternatives: applying boot alternatives
10153 23:08:15.657542 [ 0.000000] Fallback order for Node 0: 0
10154 23:08:15.664280 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1031424
10155 23:08:15.667489 [ 0.000000] Policy zone: Normal
10156 23:08:15.681103 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10157 23:08:15.690553 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10158 23:08:15.701322 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10159 23:08:15.711043 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
10160 23:08:15.717747 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10161 23:08:15.720841 <6>[ 0.000000] software IO TLB: area num 8.
10162 23:08:15.776975 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10163 23:08:15.856889 <6>[ 0.000000] Memory: 3799200K/4191232K available (17984K kernel code, 4116K rwdata, 18184K rodata, 8448K init, 615K bss, 359264K reserved, 32768K cma-reserved)
10164 23:08:15.863241 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10165 23:08:15.869662 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10166 23:08:15.873295 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10167 23:08:15.880136 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10168 23:08:15.886627 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10169 23:08:15.889693 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10170 23:08:15.899991 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10171 23:08:15.906263 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10172 23:08:15.913263 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10173 23:08:15.919681 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10174 23:08:15.923323 <6>[ 0.000000] GICv3: 608 SPIs implemented
10175 23:08:15.925930 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10176 23:08:15.932834 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10177 23:08:15.935804 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10178 23:08:15.942805 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10179 23:08:15.955546 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10180 23:08:15.968884 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10181 23:08:15.975352 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10182 23:08:15.983265 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10183 23:08:15.996608 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10184 23:08:16.003306 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10185 23:08:16.010031 <6>[ 0.009235] Console: colour dummy device 80x25
10186 23:08:16.019945 <6>[ 0.013957] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10187 23:08:16.026691 <6>[ 0.024464] pid_max: default: 32768 minimum: 301
10188 23:08:16.030005 <6>[ 0.029336] LSM: Security Framework initializing
10189 23:08:16.036256 <6>[ 0.034250] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10190 23:08:16.046122 <6>[ 0.041857] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10191 23:08:16.052847 <6>[ 0.051067] cblist_init_generic: Setting adjustable number of callback queues.
10192 23:08:16.059479 <6>[ 0.058506] cblist_init_generic: Setting shift to 3 and lim to 1.
10193 23:08:16.069003 <6>[ 0.064884] cblist_init_generic: Setting adjustable number of callback queues.
10194 23:08:16.072803 <6>[ 0.072357] cblist_init_generic: Setting shift to 3 and lim to 1.
10195 23:08:16.079520 <6>[ 0.078836] rcu: Hierarchical SRCU implementation.
10196 23:08:16.086121 <6>[ 0.078838] rcu: Max phase no-delay instances is 1000.
10197 23:08:16.092860 <6>[ 0.078862] printk: bootconsole [mtk8250] printing thread started
10198 23:08:16.099179 <6>[ 0.097192] EFI services will not be available.
10199 23:08:16.102156 <6>[ 0.097390] smp: Bringing up secondary CPUs ...
10200 23:08:16.105744 <6>[ 0.097697] Detected VIPT I-cache on CPU1
10201 23:08:16.115763 <6>[ 0.097764] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10202 23:08:16.121906 <6>[ 0.097794] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10203 23:08:16.131300 <6>[ 0.125645] Detected VIPT I-cache on CPU2
10204 23:08:16.138226 <6>[ 0.125693] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10205 23:08:16.144833 <6>[ 0.125708] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10206 23:08:16.150919 <6>[ 0.125960] Detected VIPT I-cache on CPU3
10207 23:08:16.157563 <6>[ 0.126006] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10208 23:08:16.164026 <6>[ 0.126019] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10209 23:08:16.167254 <6>[ 0.126330] CPU features: detected: Spectre-v4
10210 23:08:16.174017 <6>[ 0.126336] CPU features: detected: Spectre-BHB
10211 23:08:16.177389 <6>[ 0.126341] Detected PIPT I-cache on CPU4
10212 23:08:16.183961 <6>[ 0.126401] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10213 23:08:16.190242 <6>[ 0.126418] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10214 23:08:16.197073 <6>[ 0.126711] Detected PIPT I-cache on CPU5
10215 23:08:16.203814 <6>[ 0.126772] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10216 23:08:16.210562 <6>[ 0.126789] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10217 23:08:16.213407 <6>[ 0.127063] Detected PIPT I-cache on CPU6
10218 23:08:16.224453 <6>[ 0.127125] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10219 23:08:16.230341 <6>[ 0.127141] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10220 23:08:16.233640 <6>[ 0.127436] Detected PIPT I-cache on CPU7
10221 23:08:16.239929 <6>[ 0.127502] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10222 23:08:16.246745 <6>[ 0.127518] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10223 23:08:16.250134 <6>[ 0.127565] smp: Brought up 1 node, 8 CPUs
10224 23:08:16.256402 <6>[ 0.127569] SMP: Total of 8 processors activated.
10225 23:08:16.263309 <6>[ 0.127572] CPU features: detected: 32-bit EL0 Support
10226 23:08:16.269632 <6>[ 0.127574] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10227 23:08:16.276649 <6>[ 0.127576] CPU features: detected: Common not Private translations
10228 23:08:16.283385 <6>[ 0.127578] CPU features: detected: CRC32 instructions
10229 23:08:16.289694 <6>[ 0.127580] CPU features: detected: RCpc load-acquire (LDAPR)
10230 23:08:16.293008 <6>[ 0.127582] CPU features: detected: LSE atomic instructions
10231 23:08:16.299682 <6>[ 0.127583] CPU features: detected: Privileged Access Never
10232 23:08:16.306271 <6>[ 0.127585] CPU features: detected: RAS Extension Support
10233 23:08:16.312883 <6>[ 0.127588] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10234 23:08:16.316162 <6>[ 0.127653] CPU: All CPU(s) started at EL2
10235 23:08:16.323417 <6>[ 0.127655] alternatives: applying system-wide alternatives
10236 23:08:16.326334 <6>[ 0.140002] devtmpfs: initialized
10237 23:08:16.336170 <6>[ 0.145382] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10238 23:08:16.365268 ���ɕ���}%9Q��ɽѽ����2�����5R�<6>[ 0<.363714] printk: console [ttyS0] printing thread started
10239 23:08:16.371289 6>[ <6>[ 0.363748] printk: console [ttyS0] enabled
10240 23:08:16.378147 0.227348] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
10241 23:08:16.385116 <6>[ 0.363752] printk: bootconsole [mtk8250] disabled
10242 23:08:16.391539 <6>[ 0.381653] printk: bootconsole [mtk8250] printing thread stopped
10243 23:08:16.394938 <6>[ 0.382661] SuperH (H)SCI(F) driver initialized
10244 23:08:16.401511 <6>[ 0.383178] msm_serial: driver initialized
10245 23:08:16.408338 <6>[ 0.387917] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10246 23:08:16.418126 <6>[ 0.387947] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10247 23:08:16.424849 <6>[ 0.387976] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10248 23:08:16.443972 <6>[ 0.388005] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10249 23:08:16.452307 <6>[ 0.388027] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10250 23:08:16.457258 <6>[ 0.388055] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10251 23:08:16.469561 <6>[ 0.388083] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10252 23:08:16.470989 <6>[ 0.388194] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10253 23:08:16.481634 <6>[ 0.388223] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10254 23:08:16.485341 <6>[ 0.399560] loop: module loaded
10255 23:08:16.489863 <6>[ 0.402170] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10256 23:08:16.492761 <4>[ 0.418795] mtk-pmic-keys: Failed to locate of_node [id: -1]
10257 23:08:16.496076 <6>[ 0.419636] megasas: 07.719.03.00-rc1
10258 23:08:16.502697 <6>[ 0.431768] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10259 23:08:16.509388 <6>[ 0.431918] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10260 23:08:16.516247 <6>[ 0.443522] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10261 23:08:16.525876 <6>[ 0.495425] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2
10262 23:08:18.645518 <6>[ 2.640613] Freeing initrd memory: 55104K
10263 23:08:18.651538 <6>[ 2.646788] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10264 23:08:18.654382 <6>[ 2.651390] tun: Universal TUN/TAP device driver, 1.6
10265 23:08:18.658168 <6>[ 2.652171] thunder_xcv, ver 1.0
10266 23:08:18.661632 <6>[ 2.652188] thunder_bgx, ver 1.0
10267 23:08:18.664882 <6>[ 2.652201] nicpf, ver 1.0
10268 23:08:18.674270 <6>[ 2.653319] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10269 23:08:18.677713 <6>[ 2.653322] hns3: Copyright (c) 2017 Huawei Corporation.
10270 23:08:18.681217 <6>[ 2.653348] hclge is initializing
10271 23:08:18.687532 <6>[ 2.653366] e1000: Intel(R) PRO/1000 Network Driver
10272 23:08:18.695183 <6>[ 2.653368] e1000: Copyright (c) 1999-2006 Intel Corporation.
10273 23:08:18.698452 <6>[ 2.653385] e1000e: Intel(R) PRO/1000 Network Driver
10274 23:08:18.706038 <6>[ 2.653386] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10275 23:08:18.709177 <6>[ 2.653404] igb: Intel(R) Gigabit Ethernet Network Driver
10276 23:08:18.716080 <6>[ 2.653406] igb: Copyright (c) 2007-2014 Intel Corporation.
10277 23:08:18.723218 <6>[ 2.653420] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10278 23:08:18.729802 <6>[ 2.653422] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10279 23:08:18.733025 <6>[ 2.653715] sky2: driver version 1.30
10280 23:08:18.736410 <6>[ 2.654825] VFIO - User Level meta-driver version: 0.3
10281 23:08:18.743248 <6>[ 2.657719] usbcore: registered new interface driver usb-storage
10282 23:08:18.749685 <6>[ 2.657900] usbcore: registered new device driver onboard-usb-hub
10283 23:08:18.756181 <6>[ 2.660715] mt6397-rtc mt6359-rtc: registered as rtc0
10284 23:08:18.766104 <6>[ 2.660864] mt6397-rtc mt6359-rtc: setting system clock to 2023-12-27T23:08:37 UTC (1703718517)
10285 23:08:18.769668 <6>[ 2.661494] i2c_dev: i2c /dev entries driver
10286 23:08:18.776132 <6>[ 2.668746] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10287 23:08:18.782759 <6>[ 2.683716] cpu cpu0: EM: created perf domain
10288 23:08:18.786204 <6>[ 2.683996] cpu cpu4: EM: created perf domain
10289 23:08:18.792449 <6>[ 2.686876] sdhci: Secure Digital Host Controller Interface driver
10290 23:08:18.799112 <6>[ 2.686877] sdhci: Copyright(c) Pierre Ossman
10291 23:08:18.802387 <6>[ 2.687198] Synopsys Designware Multimedia Card Interface Driver
10292 23:08:18.808887 <6>[ 2.687530] sdhci-pltfm: SDHCI platform and OF driver helper
10293 23:08:18.815787 <6>[ 2.691886] ledtrig-cpu: registered to indicate activity on CPUs
10294 23:08:18.819053 <6>[ 2.692426] mmc0: CQHCI version 5.10
10295 23:08:18.825470 <6>[ 2.692457] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10296 23:08:18.832423 <6>[ 2.692713] usbcore: registered new interface driver usbhid
10297 23:08:18.835683 <6>[ 2.692714] usbhid: USB HID core driver
10298 23:08:18.841875 <6>[ 2.692834] spi_master spi0: will run message pump with realtime priority
10299 23:08:18.855033 <6>[ 2.719352] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10300 23:08:18.868693 <6>[ 2.721428] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10301 23:08:18.875188 <6>[ 2.722862] cros-ec-spi spi0.0: Chrome EC device registered
10302 23:08:18.884787 <6>[ 2.735426] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10303 23:08:18.891504 <6>[ 2.736318] NET: Registered PF_PACKET protocol family
10304 23:08:18.894880 <6>[ 2.736393] 9pnet: Installing 9P2000 support
10305 23:08:18.898741 <5>[ 2.736443] Key type dns_resolver registered
10306 23:08:18.904958 <6>[ 2.736953] registered taskstats version 1
10307 23:08:18.907885 <5>[ 2.736968] Loading compiled-in X.509 certificates
10308 23:08:18.917810 <4>[ 2.755590] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10309 23:08:18.927969 <4>[ 2.755819] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10310 23:08:18.934674 <3>[ 2.755838] debugfs: File 'uA_load' in directory '/' already present!
10311 23:08:18.941423 <3>[ 2.755849] debugfs: File 'min_uV' in directory '/' already present!
10312 23:08:18.947973 <3>[ 2.755855] debugfs: File 'max_uV' in directory '/' already present!
10313 23:08:18.958055 <3>[ 2.755861] debugfs: File 'constraint_flags' in directory '/' already present!
10314 23:08:18.964330 <3>[ 2.759047] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10315 23:08:18.970907 <6>[ 2.768594] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10316 23:08:18.977394 <6>[ 2.769227] xhci-mtk 11200000.usb: xHCI Host Controller
10317 23:08:18.983971 <6>[ 2.769248] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10318 23:08:18.994441 <6>[ 2.769492] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10319 23:08:19.000684 <6>[ 2.769543] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10320 23:08:19.004063 <6>[ 2.769650] xhci-mtk 11200000.usb: xHCI Host Controller
10321 23:08:19.013827 <6>[ 2.769658] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10322 23:08:19.020219 <6>[ 2.769667] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10323 23:08:19.023601 <6>[ 2.770219] hub 1-0:1.0: USB hub found
10324 23:08:19.027322 <6>[ 2.770254] hub 1-0:1.0: 1 port detected
10325 23:08:19.037160 <6>[ 2.770597] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10326 23:08:19.040212 <6>[ 2.771042] hub 2-0:1.0: USB hub found
10327 23:08:19.043329 <6>[ 2.771068] hub 2-0:1.0: 1 port detected
10328 23:08:19.050658 <6>[ 2.774273] mtk-msdc 11f70000.mmc: Got CD GPIO
10329 23:08:19.053567 <6>[ 2.786807] mmc0: Command Queue Engine enabled
10330 23:08:19.060134 <6>[ 2.786819] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10331 23:08:19.066709 <6>[ 2.787393] mmcblk0: mmc0:0001 DA4064 58.2 GiB
10332 23:08:19.073104 <6>[ 2.789325] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10333 23:08:19.082805 <6>[ 2.789331] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10334 23:08:19.089865 <4>[ 2.789480] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10335 23:08:19.099730 <6>[ 2.790114] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10336 23:08:19.106416 <6>[ 2.790118] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10337 23:08:19.116084 <6>[ 2.790240] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10338 23:08:19.122559 <6>[ 2.790251] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10339 23:08:19.129536 <6>[ 2.790254] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10340 23:08:19.139595 <6>[ 2.790260] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10341 23:08:19.145647 <6>[ 2.790575] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10342 23:08:19.149393 <6>[ 2.791864] mmcblk0boot0: mmc0:0001 DA4064 4.00 MiB
10343 23:08:19.159041 <6>[ 2.791940] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10344 23:08:19.165692 <6>[ 2.791968] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10345 23:08:19.175911 <6>[ 2.791974] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10346 23:08:19.182454 <6>[ 2.791981] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10347 23:08:19.192263 <6>[ 2.791988] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10348 23:08:19.201938 <6>[ 2.791995] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10349 23:08:19.208652 <6>[ 2.792002] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10350 23:08:19.218895 <6>[ 2.792008] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10351 23:08:19.225183 <6>[ 2.792016] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10352 23:08:19.235072 <6>[ 2.792024] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10353 23:08:19.241785 <6>[ 2.792031] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10354 23:08:19.251761 <6>[ 2.792038] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10355 23:08:19.258184 <6>[ 2.792044] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10356 23:08:19.268017 <6>[ 2.792051] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10357 23:08:19.275037 <6>[ 2.792058] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10358 23:08:19.281474 <6>[ 2.792736] mmcblk0boot1: mmc0:0001 DA4064 4.00 MiB
10359 23:08:19.287610 <6>[ 2.792923] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10360 23:08:19.294211 <6>[ 2.793678] mmcblk0rpmb: mmc0:0001 DA4064 16.0 MiB, chardev (507:0)
10361 23:08:19.301256 <6>[ 2.794096] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10362 23:08:19.307285 <6>[ 2.794698] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10363 23:08:19.313947 <6>[ 2.795323] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10364 23:08:19.320551 <6>[ 2.795957] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10365 23:08:19.330788 <6>[ 2.796136] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10366 23:08:19.337202 <6>[ 2.796152] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10367 23:08:19.347260 <6>[ 2.796157] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10368 23:08:19.356926 <6>[ 2.796163] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10369 23:08:19.366634 <6>[ 2.796169] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10370 23:08:19.376573 <6>[ 2.796174] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10371 23:08:19.383479 <6>[ 2.796179] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10372 23:08:19.393445 <6>[ 2.796184] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10373 23:08:19.403068 <6>[ 2.796189] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10374 23:08:19.413068 <6>[ 2.796195] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10375 23:08:19.423350 <6>[ 2.796200] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10376 23:08:19.433339 <6>[ 2.797057] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10377 23:08:19.439757 <6>[ 3.152738] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10378 23:08:19.443135 <6>[ 3.179342] hub 2-1:1.0: USB hub found
10379 23:08:19.445877 <6>[ 3.179659] hub 2-1:1.0: 3 ports detected
10380 23:08:19.449382 <6>[ 3.181991] hub 2-1:1.0: USB hub found
10381 23:08:19.455913 <6>[ 3.182297] hub 2-1:1.0: 3 ports detected
10382 23:08:19.462422 <6>[ 3.300534] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10383 23:08:19.465884 <6>[ 3.452616] hub 1-1:1.0: USB hub found
10384 23:08:19.469166 <6>[ 3.453007] hub 1-1:1.0: 4 ports detected
10385 23:08:19.475639 <6>[ 3.456577] hub 1-1:1.0: USB hub found
10386 23:08:19.479028 <6>[ 3.456841] hub 1-1:1.0: 4 ports detected
10387 23:08:19.540112 <6>[ 3.532827] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10388 23:08:19.775964 <6>[ 3.768681] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10389 23:08:19.896760 <6>[ 3.896284] hub 1-1.4:1.0: USB hub found
10390 23:08:19.899876 <6>[ 3.896733] hub 1-1.4:1.0: 2 ports detected
10391 23:08:19.903258 <6>[ 3.899943] hub 1-1.4:1.0: USB hub found
10392 23:08:19.909692 <6>[ 3.900301] hub 1-1.4:1.0: 2 ports detected
10393 23:08:20.195735 <6>[ 4.188674] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10394 23:08:20.379639 <6>[ 4.372676] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10395 23:08:31.104094 <6>[ 15.105687] ALSA device list:
10396 23:08:31.110363 <6>[ 15.105708] No soundcards found.
10397 23:08:31.114315 <6>[ 15.110022] Freeing unused kernel memory: 8448K
10398 23:08:31.117506 <6>[ 15.110214] Run /init as init process
10399 23:08:31.151383 <6>[ 15.151247] NET: Registered PF_INET6 protocol family
10400 23:08:31.154752 <6>[ 15.152733] Segment Routing with IPv6
10401 23:08:31.161141 <6>[ 15.152749] In-situ OAM (IOAM) with IPv6
10402 23:08:31.168818
10403 23:08:31.195441 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0<30>[ 15.172639] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10404 23:08:31.198365 <30>[ 15.173035] systemd[1]: Detected architecture arm64.
10405 23:08:31.201502 m!
10406 23:08:31.201955
10407 23:08:31.223434 <30>[ 15.220716] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10408 23:08:31.350634 <30>[ 15.347863] systemd[1]: Queued start job for default target Graphical Interface.
10409 23:08:31.400001 [[0;32m OK [0m] Created slice [0;1;39msyste<30>[ 15.397487] systemd[1]: Created slice system-getty.slice.
10410 23:08:31.403153 m-getty.slice[0m.
10411 23:08:31.424340 [[0;32m OK [0m] Created slic<30>[ 15.421757] systemd[1]: Created slice system-modprobe.slice.
10412 23:08:31.427552 e [0;1;39msystem-modprobe.slice[0m.
10413 23:08:31.455579 [[0;32m OK [0m] Created slice [0;1;39msyste<30>[ 15.449628] systemd[1]: Created slice system-serial\x2dgetty.slice.
10414 23:08:31.459010 m-serial\x2dgetty.slice[0m.
10415 23:08:31.478962 [[0;32m OK [0m] Created slice [0;1;39mUser <30>[ 15.473340] systemd[1]: Created slice User and Session Slice.
10416 23:08:31.479528 and Session Slice[0m.
10417 23:08:31.503118 [[0;32m OK [0m] Started [0;1;39mDispatch Pa<30>[ 15.497364] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10418 23:08:31.506245 ssword …ts to Console Directory Watch[0m.
10419 23:08:31.531154 [[0;32m OK [0m] Started [0;1;39mForward Pas<30>[ 15.525310] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10420 23:08:31.534287 sword R…uests to Wall Directory Watch[0m.
10421 23:08:31.562589 [[0;32m OK [0m] Reached target [0;1;39mLoca<30>[ 15.553148] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10422 23:08:31.572378 l Encrypted Volu<30>[ 15.553399] systemd[1]: Reached target Local Encrypted Volumes.
10423 23:08:31.573001 mes[0m.
10424 23:08:31.590964 [[0;32m OK [0m] Reached target [0;1;39mPath<30>[ 15.588796] systemd[1]: Reached target Paths.
10425 23:08:31.591548 s[0m.
10426 23:08:31.614124 [[0;32m OK [0m] Reached target [0;1;39mRemo<30>[ 15.608658] systemd[1]: Reached target Remote File Systems.
10427 23:08:31.614750 te File Systems[0m.
10428 23:08:31.631153 [[0;32m OK [0m] Reached target [0;1;39mSlic<30>[ 15.628643] systemd[1]: Reached target Slices.
10429 23:08:31.631727 es[0m.
10430 23:08:31.651067 [[0;32m OK [0m] Reached target [0;1;39mSwap<30>[ 15.648691] systemd[1]: Reached target Swap.
10431 23:08:31.651637 [0m.
10432 23:08:31.674795 [[0;32m OK [0m] Listening on [0;1;39minitct<30>[ 15.669109] systemd[1]: Listening on initctl Compatibility Named Pipe.
10433 23:08:31.678548 l Compatibility Named Pipe[0m.
10434 23:08:31.684764 [[0;32m OK [<30>[ 15.684168] systemd[1]: Listening on Journal Audit Socket.
10435 23:08:31.690955 0m] Listening on [0;1;39mJournal Audit Socket[0m.
10436 23:08:31.708466 [[0;32m OK [0m] Listening on<30>[ 15.705851] systemd[1]: Listening on Journal Socket (/dev/log).
10437 23:08:31.711626 [0;1;39mJournal Socket (/dev/log)[0m.
10438 23:08:31.732047 [[0;32m OK [0m] Listening on<30>[ 15.729863] systemd[1]: Listening on Journal Socket.
10439 23:08:31.735506 [0;1;39mJournal Socket[0m.
10440 23:08:31.751933 [[0;32m OK [0m] Listening on [0;1;39mudev C<30>[ 15.749243] systemd[1]: Listening on udev Control Socket.
10441 23:08:31.754713 ontrol Socket[0m.
10442 23:08:31.776054 [[0;32m OK [0m] Listening on<30>[ 15.773716] systemd[1]: Listening on udev Kernel Socket.
10443 23:08:31.778965 [0;1;39mudev Kernel Socket[0m.
10444 23:08:31.835378 Mounting [0;1;39mHuge Pages File Syste<30>[ 15.832798] systemd[1]: Mounting Huge Pages File System...
10445 23:08:31.838454 m[0m...
10446 23:08:31.862045 Mounting [0;1;39mPOSIX Message Queue F<30>[ 15.856602] systemd[1]: Mounting POSIX Message Queue File System...
10447 23:08:31.862623 ile System[0m...
10448 23:08:31.890087 Mounting [0;1;39mKernel Debug File Sys<30>[ 15.884667] systemd[1]: Mounting Kernel Debug File System...
10449 23:08:31.890751 tem[0m...
10450 23:08:31.912570 Startin<30>[ 15.904815] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10451 23:08:31.922940 g [0;1;39mCreat<30>[ 15.907236] systemd[1]: Starting Create list of static device nodes for the current kernel...
10452 23:08:31.926193 e list of st…odes for the current kernel[0m...
10453 23:08:31.949826 Starting [0;1;39mLoad Kernel Module co<30>[ 15.944499] systemd[1]: Starting Load Kernel Module configfs...
10454 23:08:31.950407 nfigfs[0m...
10455 23:08:31.974125 Starting [0;1;39mLoad Kernel Module dr<30>[ 15.968582] systemd[1]: Starting Load Kernel Module drm...
10456 23:08:31.974709 m[0m...
10457 23:08:31.994489 <30>[ 15.989015] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10458 23:08:32.007568 Starting [0;1;39mJournal Service[0m..<30>[ 16.005442] systemd[1]: Starting Journal Service...
10459 23:08:32.008161 .
10460 23:08:32.029230 Startin<30>[ 16.027092] systemd[1]: Starting Load Kernel Modules...
10461 23:08:32.032447 g [0;1;39mLoad Kernel Modules[0m...
10462 23:08:32.057643 Startin<30>[ 16.055305] systemd[1]: Starting Remount Root and Kernel File Systems...
10463 23:08:32.064328 g [0;1;39mRemount Root and Kernel File Systems[0m...
10464 23:08:32.079533 <30>[ 16.080270] systemd[1]: Starting Coldplug All udev Devices...
10465 23:08:32.085431 Starting [0;1;39mColdplug All udev Devices[0m...
10466 23:08:32.102208 [[0;32m OK [<30>[ 16.103229] systemd[1]: Started Journal Service.
10467 23:08:32.108897 0m] Started [0;1;39mJournal Service[0m.
10468 23:08:32.126954 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10469 23:08:32.144881 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10470 23:08:32.162786 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10471 23:08:32.186367 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10472 23:08:32.200219 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10473 23:08:32.217164 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10474 23:08:32.232655 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10475 23:08:32.253655 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10476 23:08:32.271649 See 'systemctl status systemd-remount-fs.service' for details.
10477 23:08:32.328039 Mounting [0;1;39mKernel Configuration File System[0m...
10478 23:08:32.348827 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10479 23:08:32.375735 Starting [0;1;39mLoad/<46>[ 16.359362] systemd-journald[191]: Received client request to flush runtime journal.
10480 23:08:32.376319 Save Random Seed[0m...
10481 23:08:32.397342 Starting [0;1;39mApply Kernel Variables[0m...
10482 23:08:32.420795 Starting [0;1;39mCreate System Users[0m...
10483 23:08:32.444496 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10484 23:08:32.464883 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10485 23:08:32.488657 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10486 23:08:32.505322 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10487 23:08:32.521189 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10488 23:08:32.541065 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10489 23:08:32.599969 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10490 23:08:32.619846 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10491 23:08:32.635975 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10492 23:08:32.655757 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10493 23:08:32.700212 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10494 23:08:32.724407 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10495 23:08:32.746431 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10496 23:08:32.765963 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10497 23:08:32.822128 Starting [0;1;39mNetwork Time Synchronization[0m...
10498 23:08:32.843974 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10499 23:08:32.892432 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10500 23:08:32.909411 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10501 23:08:32.919217 <6>[ 16.915567] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10502 23:08:32.928997 <6>[ 16.915642] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10503 23:08:32.935590 <6>[ 16.915652] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10504 23:08:32.945580 <6>[ 16.915954] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10505 23:08:32.952003 [[0;32m OK [<6>[ 16.918870] remoteproc remoteproc0: scp is available
10506 23:08:32.958831 0m] Found device<6>[ 16.918945] remoteproc remoteproc0: powering up scp
10507 23:08:32.968261 [0;1;39m/dev/t<6>[ 16.918949] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10508 23:08:32.968865 tyS0[0m.
10509 23:08:32.974976 <6>[ 16.918968] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10510 23:08:32.983122 <6>[ 16.982093] usbcore: registered new interface driver r8152
10511 23:08:32.997893 [[0;32m OK [<3>[ 16.994798] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10512 23:08:33.008043 0m] Created slic<3>[ 16.994843] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10513 23:08:33.018073 e [0;1;39msyste<3>[ 16.994853] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10514 23:08:33.028052 m-systemd\x2dbac<3>[ 16.998166] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10515 23:08:33.037705 klight.slice[0m<3>[ 16.998182] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10516 23:08:33.038253 .
10517 23:08:33.045047 <3>[ 16.998185] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10518 23:08:33.054959 <3>[ 16.998188] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10519 23:08:33.061617 <3>[ 16.998191] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10520 23:08:33.068990 <3>[ 16.999739] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10521 23:08:33.079317 <3>[ 16.999787] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10522 23:08:33.085527 <3>[ 16.999789] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10523 23:08:33.095316 <3>[ 16.999791] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10524 23:08:33.101980 <3>[ 16.999822] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10525 23:08:33.109717 <3>[ 16.999824] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10526 23:08:33.119969 <3>[ 16.999826] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10527 23:08:33.126940 [[0;32m OK [<3>[ 16.999830] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10528 23:08:33.137283 0m] Reached targ<3>[ 16.999832] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10529 23:08:33.147445 et [0;1;39mSyst<3>[ 16.999847] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10530 23:08:33.157479 em Time Set[0m.<6>[ 17.009226] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10531 23:08:33.158065
10532 23:08:33.160930 <6>[ 17.021015] usbcore: registered new interface driver cdc_ether
10533 23:08:33.171254 <4>[ 17.025462] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10534 23:08:33.177773 <4>[ 17.037174] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10535 23:08:33.184584 <4>[ 17.037174] Fallback method does not support PEC.
10536 23:08:33.190853 [[0;32m OK [<4>[ 17.038770] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10537 23:08:33.197965 0m] Reached targ<6>[ 17.041582] mc: Linux media interface: v0.10
10538 23:08:33.208149 et [0;1;39mSyst<6>[ 17.044468] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10539 23:08:33.218062 em Time Synchron<6>[ 17.044512] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10540 23:08:33.218650 ized[0m.
10541 23:08:33.224906 <6>[ 17.044523] remoteproc remoteproc0: remote processor scp is now up
10542 23:08:33.231394 <3>[ 17.051086] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10543 23:08:33.238134 <6>[ 17.067082] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10544 23:08:33.245217 <6>[ 17.067092] pci_bus 0000:00: root bus resource [bus 00-ff]
10545 23:08:33.251954 <6>[ 17.067097] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10546 23:08:33.261391 <6>[ 17.067099] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10547 23:08:33.268395 <6>[ 17.067128] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10548 23:08:33.278450 Startin<6>[ 17.067141] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10549 23:08:33.285540 g [0;1;39mLoad/<6>[ 17.067513] pci 0000:00:00.0: supports D1 D2
10550 23:08:33.293028 Save Screen …o<6>[ 17.067515] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10551 23:08:33.300418 <3>[ 17.071893] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10552 23:08:33.307396 f leds:white:kbd<6>[ 17.093518] videodev: Linux video capture interface: v2.00
10553 23:08:33.317381 _backlight[0m..<6>[ 17.104765] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10554 23:08:33.317947 .
10555 23:08:33.324303 <6>[ 17.106467] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10556 23:08:33.331341 <6>[ 17.106498] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10557 23:08:33.341063 <6>[ 17.106514] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10558 23:08:33.347968 <6>[ 17.106770] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10559 23:08:33.351453 <6>[ 17.106891] pci 0000:01:00.0: supports D1 D2
10560 23:08:33.361381 [[0;32m OK [0m] Finished [0<6>[ 17.106893] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10561 23:08:33.371680 ;1;39mLoad/Save <3>[ 17.114796] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10562 23:08:33.378291 Screen …s of l<6>[ 17.120548] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10563 23:08:33.388220 <6>[ 17.120590] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10564 23:08:33.398347 eds:white:kbd_ba<6>[ 17.120597] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10565 23:08:33.398930 cklight[0m.
10566 23:08:33.405147 <6>[ 17.120611] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10567 23:08:33.415385 <6>[ 17.120627] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10568 23:08:33.421752 <6>[ 17.120643] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10569 23:08:33.429110 <6>[ 17.120659] pci 0000:00:00.0: PCI bridge to [bus 01]
10570 23:08:33.435541 <6>[ 17.120667] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10571 23:08:33.442662 <6>[ 17.120841] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10572 23:08:33.449165 <6>[ 17.122046] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10573 23:08:33.452464 <6>[ 17.122375] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10574 23:08:33.463611 <3>[ 17.136605] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10575 23:08:33.473124 <6>[ 17.137403] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10576 23:08:33.483686 [[0;32m OK [0m] Reached targ<6>[ 17.138045] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10577 23:08:33.493591 et [0;1;39mBlue<6>[ 17.143636] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10578 23:08:33.503940 <6>[ 17.151067] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10579 23:08:33.504562 tooth[0m.
10580 23:08:33.509760 <6>[ 17.166430] usbcore: registered new interface driver r8153_ecm
10581 23:08:33.513143 <6>[ 17.177425] Bluetooth: Core ver 2.22
10582 23:08:33.520156 <6>[ 17.177626] NET: Registered PF_BLUETOOTH protocol family
10583 23:08:33.527001 <6>[ 17.177630] Bluetooth: HCI device and connection manager initialized
10584 23:08:33.530401 <6>[ 17.177668] Bluetooth: HCI socket layer initialized
10585 23:08:33.536624 <6>[ 17.177682] Bluetooth: L2CAP socket layer initialized
10586 23:08:33.539761 <6>[ 17.177711] Bluetooth: SCO socket layer initialized
10587 23:08:33.549408 <3>[ 17.178290] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10588 23:08:33.556213 <6>[ 17.224939] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10589 23:08:33.569379 <6>[ 17.240112] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10590 23:08:33.576141 <6>[ 17.240312] usbcore: registered new interface driver uvcvideo
10591 23:08:33.582805 <3>[ 17.244685] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10592 23:08:33.593102 <5>[ 17.255470] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10593 23:08:33.602172 <4>[ 17.256788] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10594 23:08:33.609020 <3>[ 17.256841] Bluetooth: hci0: Failed to load firmware file (-2)
10595 23:08:33.615743 <3>[ 17.256848] Bluetooth: hci0: Failed to set up firmware (-2)
10596 23:08:33.625654 <4>[ 17.256854] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10597 23:08:33.632205 <6>[ 17.257451] usbcore: registered new interface driver btusb
10598 23:08:33.635775 <6>[ 17.257612] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10599 23:08:33.645520 <6>[ 17.268824] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10600 23:08:33.651901 <5>[ 17.269216] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10601 23:08:33.661751 <4>[ 17.269399] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10602 23:08:33.665107 <6>[ 17.269408] cfg80211: failed to load regulatory.db
10603 23:08:33.675038 <4>[ 17.280648] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10604 23:08:33.681718 <4>[ 17.280668] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10605 23:08:33.691422 <6>[ 17.281970] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10606 23:08:33.701146 <3>[ 17.299789] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10607 23:08:33.707978 <3>[ 17.311795] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10608 23:08:33.714667 <6>[ 17.356560] r8152 2-1.3:1.0 eth0: v1.12.13
10609 23:08:33.721204 <3>[ 17.362120] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10610 23:08:33.731089 <3>[ 17.363614] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10611 23:08:33.737721 <6>[ 17.381523] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10612 23:08:33.744155 <6>[ 17.381676] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10613 23:08:33.750855 <6>[ 17.383704] r8152 2-1.3:1.0 enx00e04c6803bd: renamed from eth0
10614 23:08:33.757626 <6>[ 17.400499] mt7921e 0000:01:00.0: ASIC revision: 79610010
10615 23:08:33.764310 <6>[ 17.495174] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
10616 23:08:33.767258 <6>[ 17.495174]
10617 23:08:33.774087 <6>[ 17.755464] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
10618 23:08:33.780624 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10619 23:08:33.799066 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10620 23:08:33.814374 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10621 23:08:33.827650 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10622 23:08:33.846974 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10623 23:08:33.859443 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10624 23:08:33.875805 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10625 23:08:33.894953 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10626 23:08:33.935952 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10627 23:08:33.966533 Starting [0;1;39mUser Login Management[0m...
10628 23:08:33.982352 Starting [0;1;39mPermit User Sessions[0m...
10629 23:08:33.997558 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10630 23:08:34.076588 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10631 23:08:34.096276 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10632 23:08:34.111685 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10633 23:08:34.131949 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10634 23:08:34.148863 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10635 23:08:34.165627 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10636 23:08:34.185390 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10637 23:08:34.199748 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10638 23:08:34.244043 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10639 23:08:34.276628 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10640 23:08:34.330953
10641 23:08:34.331503
10642 23:08:34.334348 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10643 23:08:34.334907
10644 23:08:34.337438 debian-bullseye-arm64 login: root (automatic login)
10645 23:08:34.337899
10646 23:08:34.338263
10647 23:08:34.353958 Linux debian-bullseye-arm64 6.1.67-cip12-rt7 #1 SMP PREEMPT Wed Dec 27 22:50:56 UTC 2023 aarch64
10648 23:08:34.354512
10649 23:08:34.359877 The programs included with the Debian GNU/Linux system are free software;
10650 23:08:34.367176 the exact distribution terms for each program are described in the
10651 23:08:34.370035 individual files in /usr/share/doc/*/copyright.
10652 23:08:34.370495
10653 23:08:34.377015 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10654 23:08:34.379977 permitted by applicable law.
10655 23:08:34.381486 Matched prompt #10: / #
10657 23:08:34.382605 Setting prompt string to ['/ #']
10658 23:08:34.383081 end: 2.2.5.1 login-action (duration 00:00:19) [common]
10660 23:08:34.384147 end: 2.2.5 auto-login-action (duration 00:00:19) [common]
10661 23:08:34.384636 start: 2.2.6 expect-shell-connection (timeout 00:03:25) [common]
10662 23:08:34.385049 Setting prompt string to ['/ #']
10663 23:08:34.385395 Forcing a shell prompt, looking for ['/ #']
10665 23:08:34.436244 / #
10666 23:08:34.436927 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10667 23:08:34.437379 Waiting using forced prompt support (timeout 00:02:30)
10668 23:08:34.442615
10669 23:08:34.443553 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10670 23:08:34.444066 start: 2.2.7 export-device-env (timeout 00:03:25) [common]
10671 23:08:34.444701 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10672 23:08:34.445354 end: 2.2 depthcharge-retry (duration 00:01:35) [common]
10673 23:08:34.445826 end: 2 depthcharge-action (duration 00:01:35) [common]
10674 23:08:34.446319 start: 3 lava-test-retry (timeout 00:07:56) [common]
10675 23:08:34.446803 start: 3.1 lava-test-shell (timeout 00:07:56) [common]
10676 23:08:34.447213 Using namespace: common
10678 23:08:34.548495 / # #
10679 23:08:34.549184 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
10680 23:08:34.555295 #
10681 23:08:34.556179 Using /lava-12395367
10683 23:08:34.657539 / # export SHELL=/bin/sh
10684 23:08:34.658419 <6>[ 18.596045] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10685 23:08:34.663907 export SHELL=/bin/sh
10687 23:08:34.765728 / # . /lava-12395367/environment
10688 23:08:34.772686 . /lava-12395367/environment
10690 23:08:34.874621 / # /lava-12395367/bin/lava-test-runner /lava-12395367/0
10691 23:08:34.875251 Test shell timeout: 10s (minimum of the action and connection timeout)
10692 23:08:34.881339 /lava-12395367/bin/lava-test-runner /lava-12395367/0
10693 23:08:34.901783 + export TESTRUN_ID=0_igt-gpu-panfrost
10694 23:08:34.908307 + cd /lava-12395367/0/te<8>[ 18.905724] <LAVA_SIGNAL_STARTRUN 0_igt-gpu-panfrost 12395367_1.5.2.3.1>
10695 23:08:34.909211 Received signal: <STARTRUN> 0_igt-gpu-panfrost 12395367_1.5.2.3.1
10696 23:08:34.909626 Starting test lava.0_igt-gpu-panfrost (12395367_1.5.2.3.1)
10697 23:08:34.910078 Skipping test definition patterns.
10698 23:08:34.911586 sts/0_igt-gpu-panfrost
10699 23:08:34.912047 + cat uuid
10700 23:08:34.915031 + UUID=12395367_1.5.2.3.1
10701 23:08:34.915591 + set +x
10702 23:08:34.924760 + IGT_FORCE_DRIVER=panfrost /usr/bin/igt-parser.sh panfrost_gem_new panfrost_get_param panfrost_prime panfrost_submit
10703 23:08:34.931541 <8>[ 18.930507] <LAVA_SIGNAL_TESTSET START panfrost_gem_new>
10704 23:08:34.932390 Received signal: <TESTSET> START panfrost_gem_new
10705 23:08:34.932862 Starting test_set panfrost_gem_new
10706 23:08:34.944008 IGT-Version: 1.27.1-g621c2d3 (aa<14>[ 18.942234] [IGT] panfrost_gem_new: executing
10707 23:08:34.950901 rch64) (Linux: 6<14>[ 18.944202] [IGT] panfrost_gem_new: exiting, ret=77
10708 23:08:34.957661 .1.67-cip12-rt7 <8>[ 18.951103] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-4096 RESULT=skip>
10709 23:08:34.958508 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-4096 RESULT=skip
10711 23:08:34.960453 aarch64)
10712 23:08:34.967246 Test requirement not met in function d<14>[ 18.964872] [IGT] panfrost_gem_new: executing
10713 23:08:34.973816 rm_open_driver, <14>[ 18.966498] [IGT] panfrost_gem_new: exiting, ret=77
10714 23:08:34.980280 file ../lib/drmt<8>[ 18.971776] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-0 RESULT=skip>
10715 23:08:34.981152 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-0 RESULT=skip
10717 23:08:34.983776 est.c:621:
10718 23:08:34.984330 Test requirement: !(fd<0)
10719 23:08:34.990164 No known gpu found for chipset flags 0x32 (panfrost)
10720 23:08:34.993497 Last errno: 2, No such file or directory
10721 23:08:35.000433 [1mSubtest gem-new-4096:<14>[ 18.997949] [IGT] panfrost_gem_new: executing
10722 23:08:35.003515 SKIP (0.000s)[0m
10723 23:08:35.007226 IGT-Version:<14>[ 19.007092] [IGT] panfrost_gem_new: exiting, ret=77
10724 23:08:35.016900 1.27.1-g621c2d3<8>[ 19.014277] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-zeroed RESULT=skip>
10725 23:08:35.017735 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-zeroed RESULT=skip
10727 23:08:35.023306 (aarch64) (Linu<8>[ 19.016096] <LAVA_SIGNAL_TESTSET STOP>
10728 23:08:35.023866 x: 6.1.67-cip12-rt7 aarch64)
10729 23:08:35.024512 Received signal: <TESTSET> STOP
10730 23:08:35.024998 Closing test_set panfrost_gem_new
10731 23:08:35.033310 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:621:
10732 23:08:35.033871 Test requirement: !(fd<0)
10733 23:08:35.039844 No known gpu found for chipset flags 0x32 (panfrost)
10734 23:08:35.043721 Last errno: 2, No such file or directory
10735 23:08:35.050202 [1mS<8>[ 19.044615] <LAVA_SIGNAL_TESTSET START panfrost_get_param>
10736 23:08:35.051044 Received signal: <TESTSET> START panfrost_get_param
10737 23:08:35.051454 Starting test_set panfrost_get_param
10738 23:08:35.053124 ubtest gem-new-0: SKIP (0.000s)[0m
10739 23:08:35.060008 IGT-Version: 1.27.1-g621c2d<14>[ 19.057612] [IGT] panfrost_get_param: executing
10740 23:08:35.066283 3 (aarch64) (Lin<14>[ 19.059527] [IGT] panfrost_get_param: exiting, ret=77
10741 23:08:35.073672 ux: 6.1.67-cip12<8>[ 19.064684] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=base-params RESULT=skip>
10742 23:08:35.074511 Received signal: <TESTCASE> TEST_CASE_ID=base-params RESULT=skip
10744 23:08:35.076093 -rt7 aarch64)
10745 23:08:35.083119 Test requirement not met in funct<14>[ 19.081124] [IGT] panfrost_get_param: executing
10746 23:08:35.089440 ion drm_open_dri<14>[ 19.082764] [IGT] panfrost_get_param: exiting, ret=77
10747 23:08:35.099275 ver, file ../lib<8>[ 19.088083] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=get-bad-param RESULT=skip>
10748 23:08:35.099819 /drmtest.c:621:
10749 23:08:35.100454 Received signal: <TESTCASE> TEST_CASE_ID=get-bad-param RESULT=skip
10751 23:08:35.102804 Test requirement: !(fd<0)
10752 23:08:35.112833 No known gpu found for chipset flags 0x32 (panfrost)<14>[ 19.110559] [IGT] panfrost_get_param: executing
10753 23:08:35.113447
10754 23:08:35.119282 Last errno: 2, No such file or<14>[ 19.118850] [IGT] panfrost_get_param: exiting, ret=77
10755 23:08:35.122385 directory
10756 23:08:35.129099 [1m<8>[ 19.123746] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=get-bad-padding RESULT=skip>
10757 23:08:35.129944 Received signal: <TESTCASE> TEST_CASE_ID=get-bad-padding RESULT=skip
10759 23:08:35.132631 Received signal: <TESTSET> STOP
10760 23:08:35.133121 Closing test_set panfrost_get_param
10761 23:08:35.135901 Subtest gem-new-<8>[ 19.125320] <LAVA_SIGNAL_TESTSET STOP>
10762 23:08:35.136464 zeroed: SKIP (0.000s)[0m
10763 23:08:35.142201 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12-rt7 aarch64)
10764 23:08:35.152576 Test requirement not met in function drm_op<8>[ 19.148423] <LAVA_SIGNAL_TESTSET START panfrost_prime>
10765 23:08:35.153472 Received signal: <TESTSET> START panfrost_prime
10766 23:08:35.153867 Starting test_set panfrost_prime
10767 23:08:35.158948 en_driver, file ../lib/drmtest.c<14>[ 19.159756] [IGT] panfrost_prime: executing
10768 23:08:35.159514 :621:
10769 23:08:35.161906 Test requirement: !(fd<0)
10770 23:08:35.168748 No known gpu f<14>[ 19.166067] [IGT] panfrost_prime: exiting, ret=77
10771 23:08:35.175232 <8>[ 19.172247] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-prime-import RESULT=skip>
10772 23:08:35.176099 Received signal: <TESTCASE> TEST_CASE_ID=gem-prime-import RESULT=skip
10774 23:08:35.178682 <8>[ 19.173646] <LAVA_SIGNAL_TESTSET STOP>
10775 23:08:35.179551 Received signal: <TESTSET> STOP
10776 23:08:35.179950 Closing test_set panfrost_prime
10777 23:08:35.182010 ound for chipset flags 0x32 (panfrost)
10778 23:08:35.188772 Last errno: 2, No such file or directory
10779 23:08:35.191907 [1mSubtest base-params: SKIP (0.000s)[0m
10780 23:08:35.201693 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1<8>[ 19.198858] <LAVA_SIGNAL_TESTSET START panfrost_submit>
10781 23:08:35.202257 .67-cip12-rt7 aarch64)
10782 23:08:35.202907 Received signal: <TESTSET> START panfrost_submit
10783 23:08:35.203279 Starting test_set panfrost_submit
10784 23:08:35.211962 Test requirement not met in function drm<14>[ 19.209757] [IGT] panfrost_submit: executing
10785 23:08:35.218757 _open_driver, fi<14>[ 19.211681] [IGT] panfrost_submit: exiting, ret=77
10786 23:08:35.224890 <8>[ 19.218451] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit RESULT=skip>
10787 23:08:35.225729 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit RESULT=skip
10789 23:08:35.228401 le ../lib/drmtest.c:621:
10790 23:08:35.231452 Test r<14>[ 19.230960] [IGT] panfrost_submit: executing
10791 23:08:35.235081 equirement: !(fd<0)
10792 23:08:35.238102 No known gp<14>[ 19.238445] [IGT] panfrost_submit: exiting, ret=77
10793 23:08:35.248074 <8>[ 19.245285] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-no-jc RESULT=skip>
10794 23:08:35.248916 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-no-jc RESULT=skip
10796 23:08:35.251352 u found for chipset flags 0x32 (panfrost)
10797 23:08:35.254769 Last errno: 2, No such file or directory
10798 23:08:35.257772 [1mSubtest get-bad-param: SKIP (0.000s)[0m
10799 23:08:35.267895 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux<14>[ 19.267367] [IGT] panfrost_submit: executing
10800 23:08:35.271561 : 6.1.67-cip12-rt7 aarch64)
10801 23:08:35.274435 Tes<14>[ 19.274317] [IGT] panfrost_submit: exiting, ret=77
10802 23:08:35.284331 t requirement no<8>[ 19.278895] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-in-syncs RESULT=skip>
10803 23:08:35.285254 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-in-syncs RESULT=skip
10805 23:08:35.291271 t met in function drm_open_driver, file ../lib/drmtest.c:621:
10806 23:08:35.294494 Test requirement: !(fd<0)
10807 23:08:35.297610 No known gpu found for chipset flags 0x32 (panfrost)
10808 23:08:35.300799 Last errno: 2, No such file or directory
10809 23:08:35.307464 [1mSubtest get-bad-pa<14>[ 19.306323] [IGT] panfrost_submit: executing
10810 23:08:35.310413 dding: SKIP (0.000s)[0m
10811 23:08:35.317150 IGT-Ve<14>[ 19.314777] [IGT] panfrost_submit: exiting, ret=77
10812 23:08:35.324054 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-bo-handles RESULT=skip
10814 23:08:35.327083 rsion: 1.27.1-g6<8>[ 19.319819] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-bo-handles RESULT=skip>
10815 23:08:35.330915 21c2d3 (aarch64) (Linux: 6.1.67-cip12-rt7 aarch64)
10816 23:08:35.337250 Test requirement not met in function drm_ope<14>[ 19.339794] [IGT] panfrost_submit: executing
10817 23:08:35.340814 n_driver, file ../lib/drmtest.c:621:
10818 23:08:35.347148 Test requi<14>[ 19.345478] [IGT] panfrost_submit: exiting, ret=77
10819 23:08:35.356778 <8>[ 19.350354] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-requirements RESULT=skip>
10820 23:08:35.357327 rement: !(fd<0)
10821 23:08:35.357966 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-requirements RESULT=skip
10823 23:08:35.363190 No known gpu found for chipset flags 0x32 (panfrost)
10824 23:08:35.367004 Last errno: 2, No such file or directory
10825 23:08:35.370228 [1mSubtest gem-prime-import: SKIP (0.000s)[0m
10826 23:08:35.380097 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux:<14>[ 19.378811] [IGT] panfrost_submit: executing
10827 23:08:35.383681 6.1.67-cip12-rt7 aarch64)
10828 23:08:35.387512 Test<14>[ 19.386393] [IGT] panfrost_submit: exiting, ret=77
10829 23:08:35.396640 requirement not<8>[ 19.390546] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-out-sync RESULT=skip>
10830 23:08:35.397544 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-out-sync RESULT=skip
10832 23:08:35.404048 met in function drm_open_driver, file ../lib/drmtest.c:621:
10833 23:08:35.406402 Test requirement: !(fd<0)
10834 23:08:35.409508 No known gpu found for chipset flags 0x32 (panfrost)
10835 23:08:35.413744 Last errno: 2, No such file or directory
10836 23:08:35.419878 [1mSubtest pan-submit:<14>[ 19.417806] [IGT] panfrost_submit: executing
10837 23:08:35.422744 SKIP (0.000s)[0m
10838 23:08:35.426454 IGT-Version:<14>[ 19.426713] [IGT] panfrost_submit: exiting, ret=77
10839 23:08:35.432797 <8>[ 19.432125] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-reset RESULT=skip>
10840 23:08:35.433657 Received signal: <TESTCASE> TEST_CASE_ID=pan-reset RESULT=skip
10842 23:08:35.439654 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12-rt7 aarch64)
10843 23:08:35.446191 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:621:
10844 23:08:35.452949 <14>[ 19.451812] [IGT] panfrost_submit: executing
10845 23:08:35.453505 Test requirement: !(fd<0)
10846 23:08:35.459361 No kn<14>[ 19.458587] [IGT] panfrost_submit: exiting, ret=77
10847 23:08:35.469326 own gpu found fo<8>[ 19.462781] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-and-close RESULT=skip>
10848 23:08:35.470174 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-and-close RESULT=skip
10850 23:08:35.472306 r chipset flags 0x32 (panfrost)
10851 23:08:35.476032 Last errno: 2, No such file or directory
10852 23:08:35.479335 [1mSubtest pan-submit-error-no-jc: SKIP (0.000s)[0m
10853 23:08:35.485855 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12-rt7 aarch64)
10854 23:08:35.492487 Test<14>[ 19.490379] [IGT] panfrost_submit: executing
10855 23:08:35.498795 requirement not met in function<14>[ 19.498353] [IGT] panfrost_submit: exiting, ret=77
10856 23:08:35.508804 drm_open_driver<8>[ 19.503170] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-unhandled-pagefault RESULT=skip>
10857 23:08:35.509635 Received signal: <TESTCASE> TEST_CASE_ID=pan-unhandled-pagefault RESULT=skip
10859 23:08:35.512249 <8>[ 19.506029] <LAVA_SIGNAL_TESTSET STOP>
10860 23:08:35.513142 Received signal: <TESTSET> STOP
10861 23:08:35.513551 Closing test_set panfrost_submit
10862 23:08:35.515711 , file ../lib/drmtest.c:621:
10863 23:08:35.521990 Te<8>[ 19.519254] <LAVA_SIGNAL_ENDRUN 0_igt-gpu-panfrost 12395367_1.5.2.3.1>
10864 23:08:35.522823 Received signal: <ENDRUN> 0_igt-gpu-panfrost 12395367_1.5.2.3.1
10865 23:08:35.523353 Ending use of test pattern.
10866 23:08:35.523732 Ending test lava.0_igt-gpu-panfrost (12395367_1.5.2.3.1), duration 0.61
10868 23:08:35.525609 st requirement: !(fd<0)
10869 23:08:35.528829 No known gpu found for chipset flags 0x32 (panfrost)
10870 23:08:35.531940 Last errno: 2, No such file or directory
10871 23:08:35.538659 [1mSubtest pan-submit-error-bad-in-syncs: SKIP (0.000s)[0m
10872 23:08:35.545602 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12-rt7 aarch64)
10873 23:08:35.551889 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:621:
10874 23:08:35.555411 Test requirement: !(fd<0)
10875 23:08:35.558699 No known gpu found for chipset flags 0x32 (panfrost)
10876 23:08:35.561643 Last errno: 2, No such file or directory
10877 23:08:35.568478 [1mSubtest pan-submit-error-bad-bo-handles: SKIP (0.000s)[0m
10878 23:08:35.574977 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12-rt7 aarch64)
10879 23:08:35.581620 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:621:
10880 23:08:35.584900 Test requirement: !(fd<0)
10881 23:08:35.588165 No known gpu found for chipset flags 0x32 (panfrost)
10882 23:08:35.591514 Last errno: 2, No such file or directory
10883 23:08:35.598098 [1mSubtest pan-submit-error-bad-requirements: SKIP (0.000s)[0m
10884 23:08:35.604689 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12-rt7 aarch64)
10885 23:08:35.611392 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:621:
10886 23:08:35.614404 Test requirement: !(fd<0)
10887 23:08:35.617685 No known gpu found for chipset flags 0x32 (panfrost)
10888 23:08:35.621237 Last errno: 2, No such file or directory
10889 23:08:35.627824 [1mSubtest pan-submit-error-bad-out-sync: SKIP (0.000s)[0m
10890 23:08:35.634567 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12-rt7 aarch64)
10891 23:08:35.640884 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:621:
10892 23:08:35.644349 Test requirement: !(fd<0)
10893 23:08:35.647239 No known gpu found for chipset flags 0x32 (panfrost)
10894 23:08:35.650766 Last errno: 2, No such file or directory
10895 23:08:35.654165 [1mSubtest pan-reset: SKIP (0.000s)[0m
10896 23:08:35.660802 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12-rt7 aarch64)
10897 23:08:35.667119 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:621:
10898 23:08:35.670729 Test requirement: !(fd<0)
10899 23:08:35.677519 No known gpu found for chipset flags 0x32 (panfrost)
10900 23:08:35.680277 Last errno: 2, No such file or directory
10901 23:08:35.684417 [1mSubtest pan-submit-and-close: SKIP (0.000s)[0m
10902 23:08:35.690461 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.67-cip12-rt7 aarch64)
10903 23:08:35.697210 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:621:
10904 23:08:35.700071 Test requirement: !(fd<0)
10905 23:08:35.703828 No known gpu found for chipset flags 0x32 (panfrost)
10906 23:08:35.706850 Last errno: 2, No such file or directory
10907 23:08:35.713412 [1mSubtest pan-unhandled-pagefault: SKIP (0.000s)[0m
10908 23:08:35.713876 + set +x
10909 23:08:35.716456 <LAVA_TEST_RUNNER EXIT>
10910 23:08:35.717345 ok: lava_test_shell seems to have completed
10911 23:08:35.719212 base-params:
result: skip
set: panfrost_get_param
gem-new-0:
result: skip
set: panfrost_gem_new
gem-new-4096:
result: skip
set: panfrost_gem_new
gem-new-zeroed:
result: skip
set: panfrost_gem_new
gem-prime-import:
result: skip
set: panfrost_prime
get-bad-padding:
result: skip
set: panfrost_get_param
get-bad-param:
result: skip
set: panfrost_get_param
pan-reset:
result: skip
set: panfrost_submit
pan-submit:
result: skip
set: panfrost_submit
pan-submit-and-close:
result: skip
set: panfrost_submit
pan-submit-error-bad-bo-handles:
result: skip
set: panfrost_submit
pan-submit-error-bad-in-syncs:
result: skip
set: panfrost_submit
pan-submit-error-bad-out-sync:
result: skip
set: panfrost_submit
pan-submit-error-bad-requirements:
result: skip
set: panfrost_submit
pan-submit-error-no-jc:
result: skip
set: panfrost_submit
pan-unhandled-pagefault:
result: skip
set: panfrost_submit
10912 23:08:35.719761 end: 3.1 lava-test-shell (duration 00:00:01) [common]
10913 23:08:35.720231 end: 3 lava-test-retry (duration 00:00:01) [common]
10914 23:08:35.720746 start: 4 finalize (timeout 00:07:55) [common]
10915 23:08:35.721283 start: 4.1 power-off (timeout 00:00:30) [common]
10916 23:08:35.722089 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-4' '--port=1' '--command=off'
10917 23:08:35.843967 >> Command sent successfully.
10918 23:08:35.847945 Returned 0 in 0 seconds
10919 23:08:35.948953 end: 4.1 power-off (duration 00:00:00) [common]
10921 23:08:35.950849 start: 4.2 read-feedback (timeout 00:07:55) [common]
10922 23:08:35.952335 Listened to connection for namespace 'common' for up to 1s
10923 23:08:36.952871 Finalising connection for namespace 'common'
10924 23:08:36.953536 Disconnecting from shell: Finalise
10925 23:08:36.953922 / #
10926 23:08:37.054958 end: 4.2 read-feedback (duration 00:00:01) [common]
10927 23:08:37.055673 end: 4 finalize (duration 00:00:01) [common]
10928 23:08:37.056313 Cleaning after the job
10929 23:08:37.056878 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12395367/tftp-deploy-jpgcxkez/ramdisk
10930 23:08:37.091163 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12395367/tftp-deploy-jpgcxkez/kernel
10931 23:08:37.108163 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12395367/tftp-deploy-jpgcxkez/dtb
10932 23:08:37.108416 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12395367/tftp-deploy-jpgcxkez/modules
10933 23:08:37.118204 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12395367
10934 23:08:37.236025 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12395367
10935 23:08:37.236194 Job finished correctly