Boot log: mt8192-asurada-spherion-r0
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 13
- Kernel Errors: 32
- Errors: 0
1 23:10:22.344142 lava-dispatcher, installed at version: 2023.10
2 23:10:22.344355 start: 0 validate
3 23:10:22.344486 Start time: 2023-12-27 23:10:22.344478+00:00 (UTC)
4 23:10:22.344596 Using caching service: 'http://localhost/cache/?uri=%s'
5 23:10:22.344756 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20231214.0%2Farm64%2Finitrd.cpio.gz exists
6 23:10:22.606982 Using caching service: 'http://localhost/cache/?uri=%s'
7 23:10:22.607720 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.66-cip11-rt6-10-g38253b8903b4%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 23:10:22.871156 Using caching service: 'http://localhost/cache/?uri=%s'
9 23:10:22.872122 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.66-cip11-rt6-10-g38253b8903b4%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 23:10:23.135599 Using caching service: 'http://localhost/cache/?uri=%s'
11 23:10:23.136388 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20231214.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 23:10:23.402002 Using caching service: 'http://localhost/cache/?uri=%s'
13 23:10:23.402779 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.66-cip11-rt6-10-g38253b8903b4%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 23:10:23.663862 validate duration: 1.32
16 23:10:23.665111 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 23:10:23.665710 start: 1.1 download-retry (timeout 00:10:00) [common]
18 23:10:23.666306 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 23:10:23.666964 Not decompressing ramdisk as can be used compressed.
20 23:10:23.667453 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20231214.0/arm64/initrd.cpio.gz
21 23:10:23.667855 saving as /var/lib/lava/dispatcher/tmp/12395393/tftp-deploy-jk3l625h/ramdisk/initrd.cpio.gz
22 23:10:23.668231 total size: 5628325 (5 MB)
23 23:10:23.678167 progress 0 % (0 MB)
24 23:10:23.687101 progress 5 % (0 MB)
25 23:10:23.696250 progress 10 % (0 MB)
26 23:10:23.701605 progress 15 % (0 MB)
27 23:10:23.706160 progress 20 % (1 MB)
28 23:10:23.709452 progress 25 % (1 MB)
29 23:10:23.712747 progress 30 % (1 MB)
30 23:10:23.715916 progress 35 % (1 MB)
31 23:10:23.718247 progress 40 % (2 MB)
32 23:10:23.720829 progress 45 % (2 MB)
33 23:10:23.722896 progress 50 % (2 MB)
34 23:10:23.725151 progress 55 % (2 MB)
35 23:10:23.727238 progress 60 % (3 MB)
36 23:10:23.729019 progress 65 % (3 MB)
37 23:10:23.731031 progress 70 % (3 MB)
38 23:10:23.732632 progress 75 % (4 MB)
39 23:10:23.734431 progress 80 % (4 MB)
40 23:10:23.736026 progress 85 % (4 MB)
41 23:10:23.737673 progress 90 % (4 MB)
42 23:10:23.739300 progress 95 % (5 MB)
43 23:10:23.740771 progress 100 % (5 MB)
44 23:10:23.740993 5 MB downloaded in 0.07 s (73.75 MB/s)
45 23:10:23.741148 end: 1.1.1 http-download (duration 00:00:00) [common]
47 23:10:23.741390 end: 1.1 download-retry (duration 00:00:00) [common]
48 23:10:23.741496 start: 1.2 download-retry (timeout 00:10:00) [common]
49 23:10:23.741594 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 23:10:23.741725 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.66-cip11-rt6-10-g38253b8903b4/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 23:10:23.741793 saving as /var/lib/lava/dispatcher/tmp/12395393/tftp-deploy-jk3l625h/kernel/Image
52 23:10:23.741855 total size: 50024960 (47 MB)
53 23:10:23.741917 No compression specified
54 23:10:23.743037 progress 0 % (0 MB)
55 23:10:23.756224 progress 5 % (2 MB)
56 23:10:23.769479 progress 10 % (4 MB)
57 23:10:23.782544 progress 15 % (7 MB)
58 23:10:23.795582 progress 20 % (9 MB)
59 23:10:23.808387 progress 25 % (11 MB)
60 23:10:23.821252 progress 30 % (14 MB)
61 23:10:23.834364 progress 35 % (16 MB)
62 23:10:23.847251 progress 40 % (19 MB)
63 23:10:23.860258 progress 45 % (21 MB)
64 23:10:23.873443 progress 50 % (23 MB)
65 23:10:23.886628 progress 55 % (26 MB)
66 23:10:23.899477 progress 60 % (28 MB)
67 23:10:23.912458 progress 65 % (31 MB)
68 23:10:23.925259 progress 70 % (33 MB)
69 23:10:23.938226 progress 75 % (35 MB)
70 23:10:23.951182 progress 80 % (38 MB)
71 23:10:23.963989 progress 85 % (40 MB)
72 23:10:23.976982 progress 90 % (42 MB)
73 23:10:23.989911 progress 95 % (45 MB)
74 23:10:24.002551 progress 100 % (47 MB)
75 23:10:24.002758 47 MB downloaded in 0.26 s (182.86 MB/s)
76 23:10:24.002907 end: 1.2.1 http-download (duration 00:00:00) [common]
78 23:10:24.003143 end: 1.2 download-retry (duration 00:00:00) [common]
79 23:10:24.003229 start: 1.3 download-retry (timeout 00:10:00) [common]
80 23:10:24.003319 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 23:10:24.003455 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.66-cip11-rt6-10-g38253b8903b4/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 23:10:24.003525 saving as /var/lib/lava/dispatcher/tmp/12395393/tftp-deploy-jk3l625h/dtb/mt8192-asurada-spherion-r0.dtb
83 23:10:24.003587 total size: 47278 (0 MB)
84 23:10:24.003650 No compression specified
85 23:10:24.004791 progress 69 % (0 MB)
86 23:10:24.005067 progress 100 % (0 MB)
87 23:10:24.005223 0 MB downloaded in 0.00 s (27.61 MB/s)
88 23:10:24.005345 end: 1.3.1 http-download (duration 00:00:00) [common]
90 23:10:24.005618 end: 1.3 download-retry (duration 00:00:00) [common]
91 23:10:24.005707 start: 1.4 download-retry (timeout 00:10:00) [common]
92 23:10:24.005824 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 23:10:24.005962 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20231214.0/arm64/full.rootfs.tar.xz
94 23:10:24.006031 saving as /var/lib/lava/dispatcher/tmp/12395393/tftp-deploy-jk3l625h/nfsrootfs/full.rootfs.tar
95 23:10:24.006096 total size: 198084472 (188 MB)
96 23:10:24.006159 Using unxz to decompress xz
97 23:10:24.015295 progress 0 % (0 MB)
98 23:10:24.576403 progress 5 % (9 MB)
99 23:10:25.069385 progress 10 % (18 MB)
100 23:10:25.648262 progress 15 % (28 MB)
101 23:10:25.934500 progress 20 % (37 MB)
102 23:10:26.395656 progress 25 % (47 MB)
103 23:10:26.965783 progress 30 % (56 MB)
104 23:10:27.519708 progress 35 % (66 MB)
105 23:10:28.072544 progress 40 % (75 MB)
106 23:10:28.647786 progress 45 % (85 MB)
107 23:10:29.247287 progress 50 % (94 MB)
108 23:10:29.845617 progress 55 % (103 MB)
109 23:10:30.494559 progress 60 % (113 MB)
110 23:10:30.862377 progress 65 % (122 MB)
111 23:10:30.954141 progress 70 % (132 MB)
112 23:10:31.094555 progress 75 % (141 MB)
113 23:10:31.169786 progress 80 % (151 MB)
114 23:10:31.218534 progress 85 % (160 MB)
115 23:10:31.312788 progress 90 % (170 MB)
116 23:10:31.673577 progress 95 % (179 MB)
117 23:10:32.262067 progress 100 % (188 MB)
118 23:10:32.266729 188 MB downloaded in 8.26 s (22.87 MB/s)
119 23:10:32.266989 end: 1.4.1 http-download (duration 00:00:08) [common]
121 23:10:32.267360 end: 1.4 download-retry (duration 00:00:08) [common]
122 23:10:32.267452 start: 1.5 download-retry (timeout 00:09:51) [common]
123 23:10:32.267540 start: 1.5.1 http-download (timeout 00:09:51) [common]
124 23:10:32.267701 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.66-cip11-rt6-10-g38253b8903b4/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 23:10:32.267773 saving as /var/lib/lava/dispatcher/tmp/12395393/tftp-deploy-jk3l625h/modules/modules.tar
126 23:10:32.267836 total size: 8633892 (8 MB)
127 23:10:32.267915 Using unxz to decompress xz
128 23:10:32.272641 progress 0 % (0 MB)
129 23:10:32.293736 progress 5 % (0 MB)
130 23:10:32.316998 progress 10 % (0 MB)
131 23:10:32.340335 progress 15 % (1 MB)
132 23:10:32.363660 progress 20 % (1 MB)
133 23:10:32.387535 progress 25 % (2 MB)
134 23:10:32.414843 progress 30 % (2 MB)
135 23:10:32.438892 progress 35 % (2 MB)
136 23:10:32.462091 progress 40 % (3 MB)
137 23:10:32.486283 progress 45 % (3 MB)
138 23:10:32.511705 progress 50 % (4 MB)
139 23:10:32.535815 progress 55 % (4 MB)
140 23:10:32.562775 progress 60 % (4 MB)
141 23:10:32.588290 progress 65 % (5 MB)
142 23:10:32.613207 progress 70 % (5 MB)
143 23:10:32.637200 progress 75 % (6 MB)
144 23:10:32.664971 progress 80 % (6 MB)
145 23:10:32.691331 progress 85 % (7 MB)
146 23:10:32.718183 progress 90 % (7 MB)
147 23:10:32.747830 progress 95 % (7 MB)
148 23:10:32.775452 progress 100 % (8 MB)
149 23:10:32.780961 8 MB downloaded in 0.51 s (16.05 MB/s)
150 23:10:32.781213 end: 1.5.1 http-download (duration 00:00:01) [common]
152 23:10:32.781479 end: 1.5 download-retry (duration 00:00:01) [common]
153 23:10:32.781612 start: 1.6 prepare-tftp-overlay (timeout 00:09:51) [common]
154 23:10:32.781707 start: 1.6.1 extract-nfsrootfs (timeout 00:09:51) [common]
155 23:10:36.362457 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/12395393/extract-nfsrootfs-a7c1iqj5
156 23:10:36.362656 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 23:10:36.362756 start: 1.6.2 lava-overlay (timeout 00:09:47) [common]
158 23:10:36.362921 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12395393/lava-overlay-lh2e7u4s
159 23:10:36.363123 makedir: /var/lib/lava/dispatcher/tmp/12395393/lava-overlay-lh2e7u4s/lava-12395393/bin
160 23:10:36.363228 makedir: /var/lib/lava/dispatcher/tmp/12395393/lava-overlay-lh2e7u4s/lava-12395393/tests
161 23:10:36.363328 makedir: /var/lib/lava/dispatcher/tmp/12395393/lava-overlay-lh2e7u4s/lava-12395393/results
162 23:10:36.363431 Creating /var/lib/lava/dispatcher/tmp/12395393/lava-overlay-lh2e7u4s/lava-12395393/bin/lava-add-keys
163 23:10:36.363577 Creating /var/lib/lava/dispatcher/tmp/12395393/lava-overlay-lh2e7u4s/lava-12395393/bin/lava-add-sources
164 23:10:36.363709 Creating /var/lib/lava/dispatcher/tmp/12395393/lava-overlay-lh2e7u4s/lava-12395393/bin/lava-background-process-start
165 23:10:36.363838 Creating /var/lib/lava/dispatcher/tmp/12395393/lava-overlay-lh2e7u4s/lava-12395393/bin/lava-background-process-stop
166 23:10:36.363967 Creating /var/lib/lava/dispatcher/tmp/12395393/lava-overlay-lh2e7u4s/lava-12395393/bin/lava-common-functions
167 23:10:36.364093 Creating /var/lib/lava/dispatcher/tmp/12395393/lava-overlay-lh2e7u4s/lava-12395393/bin/lava-echo-ipv4
168 23:10:36.364218 Creating /var/lib/lava/dispatcher/tmp/12395393/lava-overlay-lh2e7u4s/lava-12395393/bin/lava-install-packages
169 23:10:36.364344 Creating /var/lib/lava/dispatcher/tmp/12395393/lava-overlay-lh2e7u4s/lava-12395393/bin/lava-installed-packages
170 23:10:36.364468 Creating /var/lib/lava/dispatcher/tmp/12395393/lava-overlay-lh2e7u4s/lava-12395393/bin/lava-os-build
171 23:10:36.364593 Creating /var/lib/lava/dispatcher/tmp/12395393/lava-overlay-lh2e7u4s/lava-12395393/bin/lava-probe-channel
172 23:10:36.364718 Creating /var/lib/lava/dispatcher/tmp/12395393/lava-overlay-lh2e7u4s/lava-12395393/bin/lava-probe-ip
173 23:10:36.364843 Creating /var/lib/lava/dispatcher/tmp/12395393/lava-overlay-lh2e7u4s/lava-12395393/bin/lava-target-ip
174 23:10:36.364990 Creating /var/lib/lava/dispatcher/tmp/12395393/lava-overlay-lh2e7u4s/lava-12395393/bin/lava-target-mac
175 23:10:36.365128 Creating /var/lib/lava/dispatcher/tmp/12395393/lava-overlay-lh2e7u4s/lava-12395393/bin/lava-target-storage
176 23:10:36.365256 Creating /var/lib/lava/dispatcher/tmp/12395393/lava-overlay-lh2e7u4s/lava-12395393/bin/lava-test-case
177 23:10:36.365383 Creating /var/lib/lava/dispatcher/tmp/12395393/lava-overlay-lh2e7u4s/lava-12395393/bin/lava-test-event
178 23:10:36.365649 Creating /var/lib/lava/dispatcher/tmp/12395393/lava-overlay-lh2e7u4s/lava-12395393/bin/lava-test-feedback
179 23:10:36.365780 Creating /var/lib/lava/dispatcher/tmp/12395393/lava-overlay-lh2e7u4s/lava-12395393/bin/lava-test-raise
180 23:10:36.365907 Creating /var/lib/lava/dispatcher/tmp/12395393/lava-overlay-lh2e7u4s/lava-12395393/bin/lava-test-reference
181 23:10:36.366033 Creating /var/lib/lava/dispatcher/tmp/12395393/lava-overlay-lh2e7u4s/lava-12395393/bin/lava-test-runner
182 23:10:36.366159 Creating /var/lib/lava/dispatcher/tmp/12395393/lava-overlay-lh2e7u4s/lava-12395393/bin/lava-test-set
183 23:10:36.366284 Creating /var/lib/lava/dispatcher/tmp/12395393/lava-overlay-lh2e7u4s/lava-12395393/bin/lava-test-shell
184 23:10:36.366411 Updating /var/lib/lava/dispatcher/tmp/12395393/lava-overlay-lh2e7u4s/lava-12395393/bin/lava-add-keys (debian)
185 23:10:36.366565 Updating /var/lib/lava/dispatcher/tmp/12395393/lava-overlay-lh2e7u4s/lava-12395393/bin/lava-add-sources (debian)
186 23:10:36.366714 Updating /var/lib/lava/dispatcher/tmp/12395393/lava-overlay-lh2e7u4s/lava-12395393/bin/lava-install-packages (debian)
187 23:10:36.366868 Updating /var/lib/lava/dispatcher/tmp/12395393/lava-overlay-lh2e7u4s/lava-12395393/bin/lava-installed-packages (debian)
188 23:10:36.367071 Updating /var/lib/lava/dispatcher/tmp/12395393/lava-overlay-lh2e7u4s/lava-12395393/bin/lava-os-build (debian)
189 23:10:36.367199 Creating /var/lib/lava/dispatcher/tmp/12395393/lava-overlay-lh2e7u4s/lava-12395393/environment
190 23:10:36.367309 LAVA metadata
191 23:10:36.367383 - LAVA_JOB_ID=12395393
192 23:10:36.367447 - LAVA_DISPATCHER_IP=192.168.201.1
193 23:10:36.367548 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:47) [common]
194 23:10:36.367613 skipped lava-vland-overlay
195 23:10:36.367687 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 23:10:36.367765 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:47) [common]
197 23:10:36.367826 skipped lava-multinode-overlay
198 23:10:36.367899 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 23:10:36.367978 start: 1.6.2.3 test-definition (timeout 00:09:47) [common]
200 23:10:36.368049 Loading test definitions
201 23:10:36.368139 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:47) [common]
202 23:10:36.368209 Using /lava-12395393 at stage 0
203 23:10:36.368487 uuid=12395393_1.6.2.3.1 testdef=None
204 23:10:36.368576 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 23:10:36.368661 start: 1.6.2.3.2 test-overlay (timeout 00:09:47) [common]
206 23:10:36.369140 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 23:10:36.369357 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:47) [common]
209 23:10:36.369975 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 23:10:36.370203 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:47) [common]
212 23:10:36.370749 runner path: /var/lib/lava/dispatcher/tmp/12395393/lava-overlay-lh2e7u4s/lava-12395393/0/tests/0_timesync-off test_uuid 12395393_1.6.2.3.1
213 23:10:36.370904 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 23:10:36.371205 start: 1.6.2.3.5 git-repo-action (timeout 00:09:47) [common]
216 23:10:36.371309 Using /lava-12395393 at stage 0
217 23:10:36.371436 Fetching tests from https://github.com/kernelci/test-definitions.git
218 23:10:36.371513 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/12395393/lava-overlay-lh2e7u4s/lava-12395393/0/tests/1_kselftest-alsa'
219 23:10:40.547016 Running '/usr/bin/git checkout kernelci.org
220 23:10:40.693906 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/12395393/lava-overlay-lh2e7u4s/lava-12395393/0/tests/1_kselftest-alsa/automated/linux/kselftest/kselftest.yaml
221 23:10:40.694713 uuid=12395393_1.6.2.3.5 testdef=None
222 23:10:40.694907 end: 1.6.2.3.5 git-repo-action (duration 00:00:04) [common]
224 23:10:40.695195 start: 1.6.2.3.6 test-overlay (timeout 00:09:43) [common]
225 23:10:40.695939 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 23:10:40.696167 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:43) [common]
228 23:10:40.697122 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 23:10:40.697354 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:43) [common]
231 23:10:40.698343 runner path: /var/lib/lava/dispatcher/tmp/12395393/lava-overlay-lh2e7u4s/lava-12395393/0/tests/1_kselftest-alsa test_uuid 12395393_1.6.2.3.5
232 23:10:40.698436 BOARD='mt8192-asurada-spherion-r0'
233 23:10:40.698502 BRANCH='cip-gitlab'
234 23:10:40.698562 SKIPFILE='/dev/null'
235 23:10:40.698620 SKIP_INSTALL='True'
236 23:10:40.698677 TESTPROG_URL='http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.66-cip11-rt6-10-g38253b8903b4/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 23:10:40.698736 TST_CASENAME=''
238 23:10:40.698791 TST_CMDFILES='alsa'
239 23:10:40.698934 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 23:10:40.699138 Creating lava-test-runner.conf files
242 23:10:40.699202 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12395393/lava-overlay-lh2e7u4s/lava-12395393/0 for stage 0
243 23:10:40.699294 - 0_timesync-off
244 23:10:40.699363 - 1_kselftest-alsa
245 23:10:40.699459 end: 1.6.2.3 test-definition (duration 00:00:04) [common]
246 23:10:40.699544 start: 1.6.2.4 compress-overlay (timeout 00:09:43) [common]
247 23:10:48.120003 end: 1.6.2.4 compress-overlay (duration 00:00:07) [common]
248 23:10:48.120156 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:36) [common]
249 23:10:48.120246 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 23:10:48.120346 end: 1.6.2 lava-overlay (duration 00:00:12) [common]
251 23:10:48.120435 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:36) [common]
252 23:10:48.290245 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 23:10:48.290654 start: 1.6.4 extract-modules (timeout 00:09:35) [common]
254 23:10:48.290865 extracting modules file /var/lib/lava/dispatcher/tmp/12395393/tftp-deploy-jk3l625h/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12395393/extract-nfsrootfs-a7c1iqj5
255 23:10:48.511165 extracting modules file /var/lib/lava/dispatcher/tmp/12395393/tftp-deploy-jk3l625h/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12395393/extract-overlay-ramdisk-3c0zv4lv/ramdisk
256 23:10:48.737918 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 23:10:48.738088 start: 1.6.5 apply-overlay-tftp (timeout 00:09:35) [common]
258 23:10:48.738180 [common] Applying overlay to NFS
259 23:10:48.738250 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12395393/compress-overlay-sjci9ukm/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12395393/extract-nfsrootfs-a7c1iqj5
260 23:10:49.657128 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 23:10:49.657299 start: 1.6.6 configure-preseed-file (timeout 00:09:34) [common]
262 23:10:49.657391 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 23:10:49.657487 start: 1.6.7 compress-ramdisk (timeout 00:09:34) [common]
264 23:10:49.657609 Building ramdisk /var/lib/lava/dispatcher/tmp/12395393/extract-overlay-ramdisk-3c0zv4lv/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12395393/extract-overlay-ramdisk-3c0zv4lv/ramdisk
265 23:10:50.013788 >> 130546 blocks
266 23:10:52.022362 rename /var/lib/lava/dispatcher/tmp/12395393/extract-overlay-ramdisk-3c0zv4lv/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12395393/tftp-deploy-jk3l625h/ramdisk/ramdisk.cpio.gz
267 23:10:52.022825 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 23:10:52.022944 start: 1.6.8 prepare-kernel (timeout 00:09:32) [common]
269 23:10:52.023048 start: 1.6.8.1 prepare-fit (timeout 00:09:32) [common]
270 23:10:52.023154 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12395393/tftp-deploy-jk3l625h/kernel/Image'
271 23:11:04.076074 Returned 0 in 12 seconds
272 23:11:04.177209 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12395393/tftp-deploy-jk3l625h/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12395393/tftp-deploy-jk3l625h/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12395393/tftp-deploy-jk3l625h/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12395393/tftp-deploy-jk3l625h/kernel/image.itb
273 23:11:04.561504 output: FIT description: Kernel Image image with one or more FDT blobs
274 23:11:04.561895 output: Created: Wed Dec 27 23:11:04 2023
275 23:11:04.561969 output: Image 0 (kernel-1)
276 23:11:04.562036 output: Description:
277 23:11:04.562100 output: Created: Wed Dec 27 23:11:04 2023
278 23:11:04.562161 output: Type: Kernel Image
279 23:11:04.562221 output: Compression: lzma compressed
280 23:11:04.562280 output: Data Size: 11480388 Bytes = 11211.32 KiB = 10.95 MiB
281 23:11:04.562340 output: Architecture: AArch64
282 23:11:04.562399 output: OS: Linux
283 23:11:04.562459 output: Load Address: 0x00000000
284 23:11:04.562519 output: Entry Point: 0x00000000
285 23:11:04.562575 output: Hash algo: crc32
286 23:11:04.562634 output: Hash value: a55b2f0b
287 23:11:04.562689 output: Image 1 (fdt-1)
288 23:11:04.562743 output: Description: mt8192-asurada-spherion-r0
289 23:11:04.562796 output: Created: Wed Dec 27 23:11:04 2023
290 23:11:04.562849 output: Type: Flat Device Tree
291 23:11:04.562903 output: Compression: uncompressed
292 23:11:04.562957 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
293 23:11:04.563010 output: Architecture: AArch64
294 23:11:04.563063 output: Hash algo: crc32
295 23:11:04.563117 output: Hash value: cc4352de
296 23:11:04.563170 output: Image 2 (ramdisk-1)
297 23:11:04.563223 output: Description: unavailable
298 23:11:04.563277 output: Created: Wed Dec 27 23:11:04 2023
299 23:11:04.563330 output: Type: RAMDisk Image
300 23:11:04.563383 output: Compression: Unknown Compression
301 23:11:04.563436 output: Data Size: 18766730 Bytes = 18326.88 KiB = 17.90 MiB
302 23:11:04.563489 output: Architecture: AArch64
303 23:11:04.563542 output: OS: Linux
304 23:11:04.563595 output: Load Address: unavailable
305 23:11:04.563648 output: Entry Point: unavailable
306 23:11:04.563702 output: Hash algo: crc32
307 23:11:04.563755 output: Hash value: 6560f69a
308 23:11:04.563808 output: Default Configuration: 'conf-1'
309 23:11:04.563861 output: Configuration 0 (conf-1)
310 23:11:04.563915 output: Description: mt8192-asurada-spherion-r0
311 23:11:04.563968 output: Kernel: kernel-1
312 23:11:04.564020 output: Init Ramdisk: ramdisk-1
313 23:11:04.564073 output: FDT: fdt-1
314 23:11:04.564127 output: Loadables: kernel-1
315 23:11:04.564180 output:
316 23:11:04.564387 end: 1.6.8.1 prepare-fit (duration 00:00:13) [common]
317 23:11:04.564501 end: 1.6.8 prepare-kernel (duration 00:00:13) [common]
318 23:11:04.564646 end: 1.6 prepare-tftp-overlay (duration 00:00:32) [common]
319 23:11:04.564744 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:19) [common]
320 23:11:04.564832 No LXC device requested
321 23:11:04.564915 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 23:11:04.565008 start: 1.8 deploy-device-env (timeout 00:09:19) [common]
323 23:11:04.565089 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 23:11:04.565161 Checking files for TFTP limit of 4294967296 bytes.
325 23:11:04.565711 end: 1 tftp-deploy (duration 00:00:41) [common]
326 23:11:04.565815 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 23:11:04.565907 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 23:11:04.566037 substitutions:
329 23:11:04.566113 - {DTB}: 12395393/tftp-deploy-jk3l625h/dtb/mt8192-asurada-spherion-r0.dtb
330 23:11:04.566179 - {INITRD}: 12395393/tftp-deploy-jk3l625h/ramdisk/ramdisk.cpio.gz
331 23:11:04.566240 - {KERNEL}: 12395393/tftp-deploy-jk3l625h/kernel/Image
332 23:11:04.566300 - {LAVA_MAC}: None
333 23:11:04.566359 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/12395393/extract-nfsrootfs-a7c1iqj5
334 23:11:04.566417 - {NFS_SERVER_IP}: 192.168.201.1
335 23:11:04.566473 - {PRESEED_CONFIG}: None
336 23:11:04.566529 - {PRESEED_LOCAL}: None
337 23:11:04.566584 - {RAMDISK}: 12395393/tftp-deploy-jk3l625h/ramdisk/ramdisk.cpio.gz
338 23:11:04.566639 - {ROOT_PART}: None
339 23:11:04.566694 - {ROOT}: None
340 23:11:04.566748 - {SERVER_IP}: 192.168.201.1
341 23:11:04.566804 - {TEE}: None
342 23:11:04.566859 Parsed boot commands:
343 23:11:04.566913 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 23:11:04.567100 Parsed boot commands: tftpboot 192.168.201.1 12395393/tftp-deploy-jk3l625h/kernel/image.itb 12395393/tftp-deploy-jk3l625h/kernel/cmdline
345 23:11:04.567191 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 23:11:04.567279 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 23:11:04.567372 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 23:11:04.567464 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 23:11:04.567538 Not connected, no need to disconnect.
350 23:11:04.567612 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 23:11:04.567694 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 23:11:04.567762 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-8'
353 23:11:04.571817 Setting prompt string to ['lava-test: # ']
354 23:11:04.572202 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 23:11:04.572311 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 23:11:04.572412 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 23:11:04.572510 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 23:11:04.572723 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=reboot'
359 23:11:09.712502 >> Command sent successfully.
360 23:11:09.723070 Returned 0 in 5 seconds
361 23:11:09.824399 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 23:11:09.825844 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 23:11:09.826373 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 23:11:09.826815 Setting prompt string to 'Starting depthcharge on Spherion...'
366 23:11:09.827289 Changing prompt to 'Starting depthcharge on Spherion...'
367 23:11:09.827695 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 23:11:09.828908 [Enter `^Ec?' for help]
369 23:11:09.988248
370 23:11:09.988805
371 23:11:09.989174 F0: 102B 0000
372 23:11:09.989553
373 23:11:09.989883 F3: 1001 0000 [0200]
374 23:11:09.991608
375 23:11:09.992103 F3: 1001 0000
376 23:11:09.992635
377 23:11:09.992987 F7: 102D 0000
378 23:11:09.993314
379 23:11:09.994963 F1: 0000 0000
380 23:11:09.995399
381 23:11:09.995746 V0: 0000 0000 [0001]
382 23:11:09.996086
383 23:11:09.998028 00: 0007 8000
384 23:11:09.998486
385 23:11:09.998836 01: 0000 0000
386 23:11:09.999174
387 23:11:10.001581 BP: 0C00 0209 [0000]
388 23:11:10.002018
389 23:11:10.002369 G0: 1182 0000
390 23:11:10.002697
391 23:11:10.005393 EC: 0000 0021 [4000]
392 23:11:10.005869
393 23:11:10.006221 S7: 0000 0000 [0000]
394 23:11:10.006552
395 23:11:10.009008 CC: 0000 0000 [0001]
396 23:11:10.009441
397 23:11:10.009839 T0: 0000 0040 [010F]
398 23:11:10.010270
399 23:11:10.010623 Jump to BL
400 23:11:10.010959
401 23:11:10.035355
402 23:11:10.036027
403 23:11:10.036447
404 23:11:10.042421 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 23:11:10.046625 ARM64: Exception handlers installed.
406 23:11:10.049874 ARM64: Testing exception
407 23:11:10.053068 ARM64: Done test exception
408 23:11:10.059896 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 23:11:10.070350 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 23:11:10.076186 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 23:11:10.086399 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 23:11:10.093202 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 23:11:10.103103 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 23:11:10.113405 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 23:11:10.120547 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 23:11:10.138199 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 23:11:10.141539 WDT: Last reset was cold boot
418 23:11:10.145164 SPI1(PAD0) initialized at 2873684 Hz
419 23:11:10.148006 SPI5(PAD0) initialized at 992727 Hz
420 23:11:10.151377 VBOOT: Loading verstage.
421 23:11:10.157986 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 23:11:10.161514 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 23:11:10.164929 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 23:11:10.167965 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 23:11:10.175272 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 23:11:10.181972 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 23:11:10.192977 read SPI 0x96554 0xa1eb: 4594 us, 9022 KB/s, 72.176 Mbps
428 23:11:10.193445
429 23:11:10.193895
430 23:11:10.203248 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 23:11:10.206829 ARM64: Exception handlers installed.
432 23:11:10.209925 ARM64: Testing exception
433 23:11:10.210557 ARM64: Done test exception
434 23:11:10.216729 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 23:11:10.220280 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 23:11:10.234755 Probing TPM: . done!
437 23:11:10.235309 TPM ready after 0 ms
438 23:11:10.240757 Connected to device vid:did:rid of 1ae0:0028:00
439 23:11:10.250348 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
440 23:11:10.290123 Initialized TPM device CR50 revision 0
441 23:11:10.300978 tlcl_send_startup: Startup return code is 0
442 23:11:10.301568 TPM: setup succeeded
443 23:11:10.312239 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 23:11:10.321163 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 23:11:10.332918 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 23:11:10.342175 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 23:11:10.345605 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 23:11:10.349020 in-header: 03 07 00 00 08 00 00 00
449 23:11:10.352395 in-data: aa e4 47 04 13 02 00 00
450 23:11:10.356152 Chrome EC: UHEPI supported
451 23:11:10.363532 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 23:11:10.367139 in-header: 03 9d 00 00 08 00 00 00
453 23:11:10.370485 in-data: 10 20 20 08 00 00 00 00
454 23:11:10.370920 Phase 1
455 23:11:10.374304 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 23:11:10.382086 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 23:11:10.385460 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 23:11:10.389169 Recovery requested (1009000e)
459 23:11:10.396300 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 23:11:10.401562 tlcl_extend: response is 0
461 23:11:10.409571 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 23:11:10.415668 tlcl_extend: response is 0
463 23:11:10.421715 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 23:11:10.442069 read SPI 0x210d4 0x2173b: 15148 us, 9045 KB/s, 72.360 Mbps
465 23:11:10.449578 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 23:11:10.450273
467 23:11:10.450682
468 23:11:10.459977 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 23:11:10.463683 ARM64: Exception handlers installed.
470 23:11:10.464241 ARM64: Testing exception
471 23:11:10.466954 ARM64: Done test exception
472 23:11:10.488722 pmic_efuse_setting: Set efuses in 11 msecs
473 23:11:10.492537 pmwrap_interface_init: Select PMIF_VLD_RDY
474 23:11:10.496300 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 23:11:10.503578 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 23:11:10.507445 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 23:11:10.510755 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 23:11:10.518128 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 23:11:10.522151 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 23:11:10.526312 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 23:11:10.529773 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 23:11:10.536724 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 23:11:10.540052 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 23:11:10.546612 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 23:11:10.550326 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 23:11:10.553166 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 23:11:10.560070 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 23:11:10.566293 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 23:11:10.573429 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 23:11:10.576324 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 23:11:10.583470 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 23:11:10.590433 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 23:11:10.593606 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 23:11:10.601465 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 23:11:10.605260 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 23:11:10.611474 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 23:11:10.615530 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 23:11:10.621965 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 23:11:10.628815 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 23:11:10.632467 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 23:11:10.636329 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 23:11:10.643252 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 23:11:10.646522 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 23:11:10.653899 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 23:11:10.657464 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 23:11:10.661136 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 23:11:10.668493 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 23:11:10.672790 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 23:11:10.676165 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 23:11:10.682560 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 23:11:10.686077 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 23:11:10.693130 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 23:11:10.696438 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 23:11:10.699194 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 23:11:10.702808 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 23:11:10.709747 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 23:11:10.712896 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 23:11:10.716520 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 23:11:10.722815 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 23:11:10.726022 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 23:11:10.729722 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 23:11:10.736460 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 23:11:10.739628 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 23:11:10.742899 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 23:11:10.749664 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 23:11:10.759270 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 23:11:10.762766 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 23:11:10.772678 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 23:11:10.779316 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 23:11:10.785903 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 23:11:10.789467 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 23:11:10.792478 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 23:11:10.800760 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x34
534 23:11:10.807258 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 23:11:10.810558 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
536 23:11:10.814153 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 23:11:10.825032 [RTC]rtc_get_frequency_meter,154: input=15, output=793
538 23:11:10.828606 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
539 23:11:10.834995 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
540 23:11:10.838793 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
541 23:11:10.841779 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
542 23:11:10.844853 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
543 23:11:10.848786 ADC[4]: Raw value=898150 ID=7
544 23:11:10.852416 ADC[3]: Raw value=212700 ID=1
545 23:11:10.855215 RAM Code: 0x71
546 23:11:10.858970 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
547 23:11:10.861710 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
548 23:11:10.872419 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
549 23:11:10.878774 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
550 23:11:10.882384 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
551 23:11:10.885428 in-header: 03 07 00 00 08 00 00 00
552 23:11:10.889183 in-data: aa e4 47 04 13 02 00 00
553 23:11:10.892395 Chrome EC: UHEPI supported
554 23:11:10.895960 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
555 23:11:10.900102 in-header: 03 d5 00 00 08 00 00 00
556 23:11:10.903782 in-data: 98 20 60 08 00 00 00 00
557 23:11:10.907395 MRC: failed to locate region type 0.
558 23:11:10.914618 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
559 23:11:10.918715 DRAM-K: Running full calibration
560 23:11:10.922374 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
561 23:11:10.926211 header.status = 0x0
562 23:11:10.929640 header.version = 0x6 (expected: 0x6)
563 23:11:10.933286 header.size = 0xd00 (expected: 0xd00)
564 23:11:10.933873 header.flags = 0x0
565 23:11:10.939991 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
566 23:11:10.958050 read SPI 0x72590 0x1c583: 12502 us, 9286 KB/s, 74.288 Mbps
567 23:11:10.965616 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
568 23:11:10.969224 dram_init: ddr_geometry: 2
569 23:11:10.969805 [EMI] MDL number = 2
570 23:11:10.972896 [EMI] Get MDL freq = 0
571 23:11:10.973436 dram_init: ddr_type: 0
572 23:11:10.976447 is_discrete_lpddr4: 1
573 23:11:10.980195 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
574 23:11:10.980691
575 23:11:10.981047
576 23:11:10.981369 [Bian_co] ETT version 0.0.0.1
577 23:11:10.987162 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
578 23:11:10.987601
579 23:11:10.991026 dramc_set_vcore_voltage set vcore to 650000
580 23:11:10.991457 Read voltage for 800, 4
581 23:11:10.995273 Vio18 = 0
582 23:11:10.995823 Vcore = 650000
583 23:11:10.996204 Vdram = 0
584 23:11:10.998654 Vddq = 0
585 23:11:10.999101 Vmddr = 0
586 23:11:10.999453 dram_init: config_dvfs: 1
587 23:11:11.005951 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
588 23:11:11.009740 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
589 23:11:11.013301 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=9
590 23:11:11.017452 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=9
591 23:11:11.020679 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
592 23:11:11.024026 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
593 23:11:11.027297 MEM_TYPE=3, freq_sel=18
594 23:11:11.030421 sv_algorithm_assistance_LP4_1600
595 23:11:11.033549 ============ PULL DRAM RESETB DOWN ============
596 23:11:11.040703 ========== PULL DRAM RESETB DOWN end =========
597 23:11:11.043497 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
598 23:11:11.047178 ===================================
599 23:11:11.051006 LPDDR4 DRAM CONFIGURATION
600 23:11:11.053959 ===================================
601 23:11:11.054509 EX_ROW_EN[0] = 0x0
602 23:11:11.057008 EX_ROW_EN[1] = 0x0
603 23:11:11.057594 LP4Y_EN = 0x0
604 23:11:11.060555 WORK_FSP = 0x0
605 23:11:11.061111 WL = 0x2
606 23:11:11.064001 RL = 0x2
607 23:11:11.064548 BL = 0x2
608 23:11:11.067430 RPST = 0x0
609 23:11:11.067977 RD_PRE = 0x0
610 23:11:11.070456 WR_PRE = 0x1
611 23:11:11.070897 WR_PST = 0x0
612 23:11:11.073840 DBI_WR = 0x0
613 23:11:11.077584 DBI_RD = 0x0
614 23:11:11.078138 OTF = 0x1
615 23:11:11.080317 ===================================
616 23:11:11.084021 ===================================
617 23:11:11.084572 ANA top config
618 23:11:11.086903 ===================================
619 23:11:11.090019 DLL_ASYNC_EN = 0
620 23:11:11.093443 ALL_SLAVE_EN = 1
621 23:11:11.096919 NEW_RANK_MODE = 1
622 23:11:11.100473 DLL_IDLE_MODE = 1
623 23:11:11.100911 LP45_APHY_COMB_EN = 1
624 23:11:11.103862 TX_ODT_DIS = 1
625 23:11:11.106848 NEW_8X_MODE = 1
626 23:11:11.110040 ===================================
627 23:11:11.113786 ===================================
628 23:11:11.116892 data_rate = 1600
629 23:11:11.120053 CKR = 1
630 23:11:11.120493 DQ_P2S_RATIO = 8
631 23:11:11.123709 ===================================
632 23:11:11.126640 CA_P2S_RATIO = 8
633 23:11:11.130120 DQ_CA_OPEN = 0
634 23:11:11.133435 DQ_SEMI_OPEN = 0
635 23:11:11.137074 CA_SEMI_OPEN = 0
636 23:11:11.140209 CA_FULL_RATE = 0
637 23:11:11.140645 DQ_CKDIV4_EN = 1
638 23:11:11.143338 CA_CKDIV4_EN = 1
639 23:11:11.147155 CA_PREDIV_EN = 0
640 23:11:11.150250 PH8_DLY = 0
641 23:11:11.153320 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
642 23:11:11.153855 DQ_AAMCK_DIV = 4
643 23:11:11.156951 CA_AAMCK_DIV = 4
644 23:11:11.159938 CA_ADMCK_DIV = 4
645 23:11:11.163589 DQ_TRACK_CA_EN = 0
646 23:11:11.166933 CA_PICK = 800
647 23:11:11.170064 CA_MCKIO = 800
648 23:11:11.173659 MCKIO_SEMI = 0
649 23:11:11.174199 PLL_FREQ = 3068
650 23:11:11.177119 DQ_UI_PI_RATIO = 32
651 23:11:11.180546 CA_UI_PI_RATIO = 0
652 23:11:11.183617 ===================================
653 23:11:11.186713 ===================================
654 23:11:11.190224 memory_type:LPDDR4
655 23:11:11.190662 GP_NUM : 10
656 23:11:11.193273 SRAM_EN : 1
657 23:11:11.196898 MD32_EN : 0
658 23:11:11.200262 ===================================
659 23:11:11.200718 [ANA_INIT] >>>>>>>>>>>>>>
660 23:11:11.203573 <<<<<< [CONFIGURE PHASE]: ANA_TX
661 23:11:11.206874 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
662 23:11:11.210431 ===================================
663 23:11:11.213415 data_rate = 1600,PCW = 0X7600
664 23:11:11.217039 ===================================
665 23:11:11.220192 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
666 23:11:11.226891 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
667 23:11:11.230170 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
668 23:11:11.237052 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
669 23:11:11.240567 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
670 23:11:11.243838 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
671 23:11:11.244389 [ANA_INIT] flow start
672 23:11:11.247090 [ANA_INIT] PLL >>>>>>>>
673 23:11:11.250951 [ANA_INIT] PLL <<<<<<<<
674 23:11:11.251514 [ANA_INIT] MIDPI >>>>>>>>
675 23:11:11.254464 [ANA_INIT] MIDPI <<<<<<<<
676 23:11:11.258096 [ANA_INIT] DLL >>>>>>>>
677 23:11:11.258540 [ANA_INIT] flow end
678 23:11:11.262094 ============ LP4 DIFF to SE enter ============
679 23:11:11.265466 ============ LP4 DIFF to SE exit ============
680 23:11:11.269391 [ANA_INIT] <<<<<<<<<<<<<
681 23:11:11.273120 [Flow] Enable top DCM control >>>>>
682 23:11:11.276389 [Flow] Enable top DCM control <<<<<
683 23:11:11.280414 Enable DLL master slave shuffle
684 23:11:11.283936 ==============================================================
685 23:11:11.287250 Gating Mode config
686 23:11:11.290757 ==============================================================
687 23:11:11.293867 Config description:
688 23:11:11.304748 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
689 23:11:11.308271 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
690 23:11:11.315563 SELPH_MODE 0: By rank 1: By Phase
691 23:11:11.318656 ==============================================================
692 23:11:11.322607 GAT_TRACK_EN = 1
693 23:11:11.326134 RX_GATING_MODE = 2
694 23:11:11.329905 RX_GATING_TRACK_MODE = 2
695 23:11:11.333143 SELPH_MODE = 1
696 23:11:11.336867 PICG_EARLY_EN = 1
697 23:11:11.337404 VALID_LAT_VALUE = 1
698 23:11:11.343917 ==============================================================
699 23:11:11.348073 Enter into Gating configuration >>>>
700 23:11:11.351509 Exit from Gating configuration <<<<
701 23:11:11.352007 Enter into DVFS_PRE_config >>>>>
702 23:11:11.366359 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
703 23:11:11.366963 Exit from DVFS_PRE_config <<<<<
704 23:11:11.369948 Enter into PICG configuration >>>>
705 23:11:11.373441 Exit from PICG configuration <<<<
706 23:11:11.377047 [RX_INPUT] configuration >>>>>
707 23:11:11.380812 [RX_INPUT] configuration <<<<<
708 23:11:11.385564 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
709 23:11:11.388698 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
710 23:11:11.396448 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
711 23:11:11.403703 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
712 23:11:11.407199 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
713 23:11:11.414427 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
714 23:11:11.418528 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
715 23:11:11.421962 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
716 23:11:11.425920 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
717 23:11:11.429645 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
718 23:11:11.433054 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
719 23:11:11.440708 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
720 23:11:11.444178 ===================================
721 23:11:11.444626 LPDDR4 DRAM CONFIGURATION
722 23:11:11.447816 ===================================
723 23:11:11.452415 EX_ROW_EN[0] = 0x0
724 23:11:11.452972 EX_ROW_EN[1] = 0x0
725 23:11:11.456054 LP4Y_EN = 0x0
726 23:11:11.456490 WORK_FSP = 0x0
727 23:11:11.459460 WL = 0x2
728 23:11:11.460009 RL = 0x2
729 23:11:11.460434 BL = 0x2
730 23:11:11.463196 RPST = 0x0
731 23:11:11.463758 RD_PRE = 0x0
732 23:11:11.466732 WR_PRE = 0x1
733 23:11:11.467170 WR_PST = 0x0
734 23:11:11.470662 DBI_WR = 0x0
735 23:11:11.471195 DBI_RD = 0x0
736 23:11:11.474243 OTF = 0x1
737 23:11:11.477804 ===================================
738 23:11:11.481344 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
739 23:11:11.485505 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
740 23:11:11.489245 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
741 23:11:11.493040 ===================================
742 23:11:11.496467 LPDDR4 DRAM CONFIGURATION
743 23:11:11.497009 ===================================
744 23:11:11.500120 EX_ROW_EN[0] = 0x10
745 23:11:11.504034 EX_ROW_EN[1] = 0x0
746 23:11:11.504600 LP4Y_EN = 0x0
747 23:11:11.504957 WORK_FSP = 0x0
748 23:11:11.508046 WL = 0x2
749 23:11:11.508589 RL = 0x2
750 23:11:11.511238 BL = 0x2
751 23:11:11.511798 RPST = 0x0
752 23:11:11.514621 RD_PRE = 0x0
753 23:11:11.515054 WR_PRE = 0x1
754 23:11:11.518788 WR_PST = 0x0
755 23:11:11.519226 DBI_WR = 0x0
756 23:11:11.522437 DBI_RD = 0x0
757 23:11:11.522874 OTF = 0x1
758 23:11:11.525952 ===================================
759 23:11:11.533064 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
760 23:11:11.537357 nWR fixed to 40
761 23:11:11.538066 [ModeRegInit_LP4] CH0 RK0
762 23:11:11.540892 [ModeRegInit_LP4] CH0 RK1
763 23:11:11.544483 [ModeRegInit_LP4] CH1 RK0
764 23:11:11.544921 [ModeRegInit_LP4] CH1 RK1
765 23:11:11.548271 match AC timing 13
766 23:11:11.552370 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
767 23:11:11.556495 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
768 23:11:11.559992 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
769 23:11:11.563376 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
770 23:11:11.570620 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
771 23:11:11.571131 [EMI DOE] emi_dcm 0
772 23:11:11.574328 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
773 23:11:11.574767 ==
774 23:11:11.577858 Dram Type= 6, Freq= 0, CH_0, rank 0
775 23:11:11.581642 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
776 23:11:11.582092 ==
777 23:11:11.589255 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
778 23:11:11.592692 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
779 23:11:11.603270 [CA 0] Center 38 (7~69) winsize 63
780 23:11:11.607032 [CA 1] Center 37 (7~68) winsize 62
781 23:11:11.609979 [CA 2] Center 35 (5~66) winsize 62
782 23:11:11.614072 [CA 3] Center 35 (5~66) winsize 62
783 23:11:11.617000 [CA 4] Center 34 (4~65) winsize 62
784 23:11:11.620625 [CA 5] Center 34 (4~64) winsize 61
785 23:11:11.621159
786 23:11:11.623656 [CmdBusTrainingLP45] Vref(ca) range 1: 32
787 23:11:11.624085
788 23:11:11.626843 [CATrainingPosCal] consider 1 rank data
789 23:11:11.629997 u2DelayCellTimex100 = 270/100 ps
790 23:11:11.633285 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
791 23:11:11.637149 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
792 23:11:11.643717 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
793 23:11:11.646696 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
794 23:11:11.649889 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
795 23:11:11.653552 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
796 23:11:11.654094
797 23:11:11.656939 CA PerBit enable=1, Macro0, CA PI delay=34
798 23:11:11.657521
799 23:11:11.660102 [CBTSetCACLKResult] CA Dly = 34
800 23:11:11.660647 CS Dly: 6 (0~37)
801 23:11:11.661166 ==
802 23:11:11.663137 Dram Type= 6, Freq= 0, CH_0, rank 1
803 23:11:11.670341 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
804 23:11:11.670892 ==
805 23:11:11.673451 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
806 23:11:11.680267 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
807 23:11:11.689997 [CA 0] Center 38 (7~69) winsize 63
808 23:11:11.693557 [CA 1] Center 38 (7~69) winsize 63
809 23:11:11.696785 [CA 2] Center 35 (5~66) winsize 62
810 23:11:11.699557 [CA 3] Center 35 (5~66) winsize 62
811 23:11:11.702999 [CA 4] Center 34 (4~65) winsize 62
812 23:11:11.706290 [CA 5] Center 34 (4~65) winsize 62
813 23:11:11.706717
814 23:11:11.709994 [CmdBusTrainingLP45] Vref(ca) range 1: 32
815 23:11:11.710423
816 23:11:11.712961 [CATrainingPosCal] consider 2 rank data
817 23:11:11.716520 u2DelayCellTimex100 = 270/100 ps
818 23:11:11.720209 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
819 23:11:11.723466 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
820 23:11:11.730237 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
821 23:11:11.733297 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
822 23:11:11.736413 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
823 23:11:11.740199 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
824 23:11:11.740734
825 23:11:11.743432 CA PerBit enable=1, Macro0, CA PI delay=34
826 23:11:11.743972
827 23:11:11.746207 [CBTSetCACLKResult] CA Dly = 34
828 23:11:11.746704 CS Dly: 6 (0~37)
829 23:11:11.747065
830 23:11:11.749586 ----->DramcWriteLeveling(PI) begin...
831 23:11:11.752878 ==
832 23:11:11.753410 Dram Type= 6, Freq= 0, CH_0, rank 0
833 23:11:11.760064 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
834 23:11:11.760586 ==
835 23:11:11.763203 Write leveling (Byte 0): 30 => 30
836 23:11:11.766423 Write leveling (Byte 1): 30 => 30
837 23:11:11.770407 DramcWriteLeveling(PI) end<-----
838 23:11:11.770938
839 23:11:11.771278 ==
840 23:11:11.773134 Dram Type= 6, Freq= 0, CH_0, rank 0
841 23:11:11.776466 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
842 23:11:11.776997 ==
843 23:11:11.779747 [Gating] SW mode calibration
844 23:11:11.786550 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
845 23:11:11.789649 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
846 23:11:11.796302 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
847 23:11:11.799767 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
848 23:11:11.802797 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
849 23:11:11.809688 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
850 23:11:11.812818 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
851 23:11:11.816902 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
852 23:11:11.823113 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
853 23:11:11.826571 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
854 23:11:11.830422 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
855 23:11:11.834166 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 23:11:11.841556 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 23:11:11.844634 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 23:11:11.847967 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 23:11:11.852122 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 23:11:11.859274 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 23:11:11.862097 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 23:11:11.865306 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 23:11:11.868475 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 23:11:11.875286 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
865 23:11:11.878476 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
866 23:11:11.882018 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 23:11:11.888823 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 23:11:11.891968 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 23:11:11.895239 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 23:11:11.902261 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
871 23:11:11.905193 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
872 23:11:11.908962 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 23:11:11.915748 0 9 12 | B1->B0 | 2525 3131 | 1 1 | (1 1) (1 1)
874 23:11:11.918817 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
875 23:11:11.921958 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
876 23:11:11.928573 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
877 23:11:11.931967 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
878 23:11:11.935199 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
879 23:11:11.942046 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
880 23:11:11.945231 0 10 8 | B1->B0 | 3434 3333 | 1 0 | (1 0) (0 0)
881 23:11:11.948412 0 10 12 | B1->B0 | 2f2f 2323 | 0 0 | (0 1) (0 0)
882 23:11:11.952145 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
883 23:11:11.958429 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
884 23:11:11.962049 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
885 23:11:11.965193 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
886 23:11:11.971931 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
887 23:11:11.975047 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
888 23:11:11.978695 0 11 8 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
889 23:11:11.985550 0 11 12 | B1->B0 | 3333 4040 | 0 0 | (0 0) (0 0)
890 23:11:11.988751 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
891 23:11:11.992353 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
892 23:11:11.999182 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
893 23:11:12.002405 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
894 23:11:12.005672 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
895 23:11:12.011833 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
896 23:11:12.015271 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
897 23:11:12.018624 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
898 23:11:12.025468 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
899 23:11:12.028805 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
900 23:11:12.032712 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
901 23:11:12.035757 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
902 23:11:12.042084 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
903 23:11:12.045398 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
904 23:11:12.048832 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 23:11:12.055609 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 23:11:12.059251 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 23:11:12.062162 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 23:11:12.068835 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 23:11:12.072010 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 23:11:12.076054 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 23:11:12.082185 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 23:11:12.085639 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
913 23:11:12.088850 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
914 23:11:12.092332 Total UI for P1: 0, mck2ui 16
915 23:11:12.095164 best dqsien dly found for B0: ( 0, 14, 8)
916 23:11:12.102106 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
917 23:11:12.102538 Total UI for P1: 0, mck2ui 16
918 23:11:12.109137 best dqsien dly found for B1: ( 0, 14, 12)
919 23:11:12.112347 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
920 23:11:12.115343 best DQS1 dly(MCK, UI, PI) = (0, 14, 12)
921 23:11:12.115772
922 23:11:12.118401 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
923 23:11:12.122111 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 12)
924 23:11:12.125277 [Gating] SW calibration Done
925 23:11:12.125762 ==
926 23:11:12.128608 Dram Type= 6, Freq= 0, CH_0, rank 0
927 23:11:12.131670 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
928 23:11:12.132234 ==
929 23:11:12.135009 RX Vref Scan: 0
930 23:11:12.135486
931 23:11:12.135895 RX Vref 0 -> 0, step: 1
932 23:11:12.136235
933 23:11:12.138742 RX Delay -130 -> 252, step: 16
934 23:11:12.142405 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
935 23:11:12.148349 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
936 23:11:12.152013 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
937 23:11:12.155418 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
938 23:11:12.158815 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
939 23:11:12.161926 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
940 23:11:12.168317 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
941 23:11:12.171891 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
942 23:11:12.175300 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
943 23:11:12.178488 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
944 23:11:12.182171 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
945 23:11:12.188847 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
946 23:11:12.191946 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
947 23:11:12.195335 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
948 23:11:12.198664 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
949 23:11:12.201763 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
950 23:11:12.205259 ==
951 23:11:12.205909 Dram Type= 6, Freq= 0, CH_0, rank 0
952 23:11:12.212312 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
953 23:11:12.212839 ==
954 23:11:12.213185 DQS Delay:
955 23:11:12.215284 DQS0 = 0, DQS1 = 0
956 23:11:12.215707 DQM Delay:
957 23:11:12.218442 DQM0 = 80, DQM1 = 70
958 23:11:12.218867 DQ Delay:
959 23:11:12.221671 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
960 23:11:12.225294 DQ4 =77, DQ5 =69, DQ6 =85, DQ7 =93
961 23:11:12.228369 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =61
962 23:11:12.231947 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
963 23:11:12.232475
964 23:11:12.232817
965 23:11:12.233132 ==
966 23:11:12.235612 Dram Type= 6, Freq= 0, CH_0, rank 0
967 23:11:12.238671 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
968 23:11:12.239099 ==
969 23:11:12.239464
970 23:11:12.239786
971 23:11:12.242424 TX Vref Scan disable
972 23:11:12.242850 == TX Byte 0 ==
973 23:11:12.249376 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
974 23:11:12.252549 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
975 23:11:12.253073 == TX Byte 1 ==
976 23:11:12.259533 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
977 23:11:12.262389 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
978 23:11:12.262816 ==
979 23:11:12.265977 Dram Type= 6, Freq= 0, CH_0, rank 0
980 23:11:12.268979 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
981 23:11:12.269578 ==
982 23:11:12.282843 TX Vref=22, minBit 11, minWin=26, winSum=434
983 23:11:12.286079 TX Vref=24, minBit 14, minWin=26, winSum=440
984 23:11:12.289627 TX Vref=26, minBit 7, minWin=27, winSum=443
985 23:11:12.292647 TX Vref=28, minBit 10, minWin=27, winSum=442
986 23:11:12.296028 TX Vref=30, minBit 10, minWin=27, winSum=443
987 23:11:12.302991 TX Vref=32, minBit 2, minWin=27, winSum=440
988 23:11:12.305999 [TxChooseVref] Worse bit 7, Min win 27, Win sum 443, Final Vref 26
989 23:11:12.306432
990 23:11:12.309618 Final TX Range 1 Vref 26
991 23:11:12.310048
992 23:11:12.310388 ==
993 23:11:12.312686 Dram Type= 6, Freq= 0, CH_0, rank 0
994 23:11:12.315834 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
995 23:11:12.316267 ==
996 23:11:12.319635
997 23:11:12.320060
998 23:11:12.320401 TX Vref Scan disable
999 23:11:12.322696 == TX Byte 0 ==
1000 23:11:12.326375 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1001 23:11:12.329567 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1002 23:11:12.332761 == TX Byte 1 ==
1003 23:11:12.335839 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1004 23:11:12.342874 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1005 23:11:12.343302
1006 23:11:12.343637 [DATLAT]
1007 23:11:12.343954 Freq=800, CH0 RK0
1008 23:11:12.344261
1009 23:11:12.346353 DATLAT Default: 0xa
1010 23:11:12.346777 0, 0xFFFF, sum = 0
1011 23:11:12.349274 1, 0xFFFF, sum = 0
1012 23:11:12.349741 2, 0xFFFF, sum = 0
1013 23:11:12.352559 3, 0xFFFF, sum = 0
1014 23:11:12.353042 4, 0xFFFF, sum = 0
1015 23:11:12.356330 5, 0xFFFF, sum = 0
1016 23:11:12.359715 6, 0xFFFF, sum = 0
1017 23:11:12.360146 7, 0xFFFF, sum = 0
1018 23:11:12.362966 8, 0xFFFF, sum = 0
1019 23:11:12.363399 9, 0x0, sum = 1
1020 23:11:12.363746 10, 0x0, sum = 2
1021 23:11:12.365953 11, 0x0, sum = 3
1022 23:11:12.366385 12, 0x0, sum = 4
1023 23:11:12.369655 best_step = 10
1024 23:11:12.370080
1025 23:11:12.370456 ==
1026 23:11:12.372603 Dram Type= 6, Freq= 0, CH_0, rank 0
1027 23:11:12.376059 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1028 23:11:12.376480 ==
1029 23:11:12.379137 RX Vref Scan: 1
1030 23:11:12.379552
1031 23:11:12.379887 Set Vref Range= 32 -> 127
1032 23:11:12.382851
1033 23:11:12.383265 RX Vref 32 -> 127, step: 1
1034 23:11:12.383600
1035 23:11:12.385729 RX Delay -111 -> 252, step: 8
1036 23:11:12.386147
1037 23:11:12.389559 Set Vref, RX VrefLevel [Byte0]: 32
1038 23:11:12.393240 [Byte1]: 32
1039 23:11:12.393806
1040 23:11:12.396150 Set Vref, RX VrefLevel [Byte0]: 33
1041 23:11:12.399546 [Byte1]: 33
1042 23:11:12.403522
1043 23:11:12.403938 Set Vref, RX VrefLevel [Byte0]: 34
1044 23:11:12.406716 [Byte1]: 34
1045 23:11:12.410846
1046 23:11:12.411331 Set Vref, RX VrefLevel [Byte0]: 35
1047 23:11:12.414240 [Byte1]: 35
1048 23:11:12.418891
1049 23:11:12.419351 Set Vref, RX VrefLevel [Byte0]: 36
1050 23:11:12.422086 [Byte1]: 36
1051 23:11:12.426200
1052 23:11:12.426696 Set Vref, RX VrefLevel [Byte0]: 37
1053 23:11:12.429424 [Byte1]: 37
1054 23:11:12.434100
1055 23:11:12.434780 Set Vref, RX VrefLevel [Byte0]: 38
1056 23:11:12.437303 [Byte1]: 38
1057 23:11:12.441326
1058 23:11:12.441850 Set Vref, RX VrefLevel [Byte0]: 39
1059 23:11:12.445219 [Byte1]: 39
1060 23:11:12.449249
1061 23:11:12.449718 Set Vref, RX VrefLevel [Byte0]: 40
1062 23:11:12.453226 [Byte1]: 40
1063 23:11:12.456874
1064 23:11:12.457392 Set Vref, RX VrefLevel [Byte0]: 41
1065 23:11:12.460134 [Byte1]: 41
1066 23:11:12.464679
1067 23:11:12.464908 Set Vref, RX VrefLevel [Byte0]: 42
1068 23:11:12.467617 [Byte1]: 42
1069 23:11:12.471742
1070 23:11:12.471817 Set Vref, RX VrefLevel [Byte0]: 43
1071 23:11:12.475322 [Byte1]: 43
1072 23:11:12.479748
1073 23:11:12.479818 Set Vref, RX VrefLevel [Byte0]: 44
1074 23:11:12.482725 [Byte1]: 44
1075 23:11:12.487103
1076 23:11:12.487184 Set Vref, RX VrefLevel [Byte0]: 45
1077 23:11:12.490775 [Byte1]: 45
1078 23:11:12.495265
1079 23:11:12.495360 Set Vref, RX VrefLevel [Byte0]: 46
1080 23:11:12.498250 [Byte1]: 46
1081 23:11:12.502482
1082 23:11:12.502587 Set Vref, RX VrefLevel [Byte0]: 47
1083 23:11:12.505849 [Byte1]: 47
1084 23:11:12.510561
1085 23:11:12.510682 Set Vref, RX VrefLevel [Byte0]: 48
1086 23:11:12.513949 [Byte1]: 48
1087 23:11:12.518337
1088 23:11:12.518473 Set Vref, RX VrefLevel [Byte0]: 49
1089 23:11:12.521494 [Byte1]: 49
1090 23:11:12.526024
1091 23:11:12.526284 Set Vref, RX VrefLevel [Byte0]: 50
1092 23:11:12.529281 [Byte1]: 50
1093 23:11:12.533168
1094 23:11:12.533457 Set Vref, RX VrefLevel [Byte0]: 51
1095 23:11:12.536605 [Byte1]: 51
1096 23:11:12.541132
1097 23:11:12.541428 Set Vref, RX VrefLevel [Byte0]: 52
1098 23:11:12.544179 [Byte1]: 52
1099 23:11:12.548495
1100 23:11:12.548909 Set Vref, RX VrefLevel [Byte0]: 53
1101 23:11:12.552042 [Byte1]: 53
1102 23:11:12.556542
1103 23:11:12.557117 Set Vref, RX VrefLevel [Byte0]: 54
1104 23:11:12.559643 [Byte1]: 54
1105 23:11:12.563670
1106 23:11:12.564086 Set Vref, RX VrefLevel [Byte0]: 55
1107 23:11:12.567504 [Byte1]: 55
1108 23:11:12.571439
1109 23:11:12.571909 Set Vref, RX VrefLevel [Byte0]: 56
1110 23:11:12.574684 [Byte1]: 56
1111 23:11:12.579463
1112 23:11:12.580001 Set Vref, RX VrefLevel [Byte0]: 57
1113 23:11:12.582590 [Byte1]: 57
1114 23:11:12.586802
1115 23:11:12.587222 Set Vref, RX VrefLevel [Byte0]: 58
1116 23:11:12.590205 [Byte1]: 58
1117 23:11:12.594745
1118 23:11:12.595163 Set Vref, RX VrefLevel [Byte0]: 59
1119 23:11:12.597904 [Byte1]: 59
1120 23:11:12.602226
1121 23:11:12.602813 Set Vref, RX VrefLevel [Byte0]: 60
1122 23:11:12.605262 [Byte1]: 60
1123 23:11:12.609981
1124 23:11:12.610399 Set Vref, RX VrefLevel [Byte0]: 61
1125 23:11:12.612983 [Byte1]: 61
1126 23:11:12.617444
1127 23:11:12.617917 Set Vref, RX VrefLevel [Byte0]: 62
1128 23:11:12.620685 [Byte1]: 62
1129 23:11:12.625048
1130 23:11:12.625572 Set Vref, RX VrefLevel [Byte0]: 63
1131 23:11:12.628389 [Byte1]: 63
1132 23:11:12.632547
1133 23:11:12.632967 Set Vref, RX VrefLevel [Byte0]: 64
1134 23:11:12.636113 [Byte1]: 64
1135 23:11:12.640375
1136 23:11:12.640937 Set Vref, RX VrefLevel [Byte0]: 65
1137 23:11:12.644061 [Byte1]: 65
1138 23:11:12.648210
1139 23:11:12.648793 Set Vref, RX VrefLevel [Byte0]: 66
1140 23:11:12.651463 [Byte1]: 66
1141 23:11:12.656075
1142 23:11:12.656592 Set Vref, RX VrefLevel [Byte0]: 67
1143 23:11:12.658979 [Byte1]: 67
1144 23:11:12.663417
1145 23:11:12.663940 Set Vref, RX VrefLevel [Byte0]: 68
1146 23:11:12.666566 [Byte1]: 68
1147 23:11:12.671224
1148 23:11:12.671748 Set Vref, RX VrefLevel [Byte0]: 69
1149 23:11:12.674259 [Byte1]: 69
1150 23:11:12.678526
1151 23:11:12.679046 Set Vref, RX VrefLevel [Byte0]: 70
1152 23:11:12.681856 [Byte1]: 70
1153 23:11:12.686355
1154 23:11:12.686907 Set Vref, RX VrefLevel [Byte0]: 71
1155 23:11:12.689580 [Byte1]: 71
1156 23:11:12.693760
1157 23:11:12.694273 Set Vref, RX VrefLevel [Byte0]: 72
1158 23:11:12.697089 [Byte1]: 72
1159 23:11:12.701349
1160 23:11:12.701925 Set Vref, RX VrefLevel [Byte0]: 73
1161 23:11:12.704708 [Byte1]: 73
1162 23:11:12.709653
1163 23:11:12.710170 Set Vref, RX VrefLevel [Byte0]: 74
1164 23:11:12.712519 [Byte1]: 74
1165 23:11:12.716990
1166 23:11:12.717558 Set Vref, RX VrefLevel [Byte0]: 75
1167 23:11:12.720193 [Byte1]: 75
1168 23:11:12.724581
1169 23:11:12.725136 Set Vref, RX VrefLevel [Byte0]: 76
1170 23:11:12.727799 [Byte1]: 76
1171 23:11:12.731991
1172 23:11:12.732409 Set Vref, RX VrefLevel [Byte0]: 77
1173 23:11:12.735452 [Byte1]: 77
1174 23:11:12.739834
1175 23:11:12.740373 Set Vref, RX VrefLevel [Byte0]: 78
1176 23:11:12.743086 [Byte1]: 78
1177 23:11:12.747468
1178 23:11:12.747987 Final RX Vref Byte 0 = 63 to rank0
1179 23:11:12.750695 Final RX Vref Byte 1 = 56 to rank0
1180 23:11:12.753948 Final RX Vref Byte 0 = 63 to rank1
1181 23:11:12.757228 Final RX Vref Byte 1 = 56 to rank1==
1182 23:11:12.761306 Dram Type= 6, Freq= 0, CH_0, rank 0
1183 23:11:12.767575 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1184 23:11:12.768121 ==
1185 23:11:12.768461 DQS Delay:
1186 23:11:12.768769 DQS0 = 0, DQS1 = 0
1187 23:11:12.770387 DQM Delay:
1188 23:11:12.770807 DQM0 = 81, DQM1 = 67
1189 23:11:12.773616 DQ Delay:
1190 23:11:12.777618 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1191 23:11:12.781203 DQ4 =80, DQ5 =68, DQ6 =88, DQ7 =92
1192 23:11:12.783891 DQ8 =60, DQ9 =56, DQ10 =68, DQ11 =60
1193 23:11:12.787828 DQ12 =72, DQ13 =72, DQ14 =76, DQ15 =76
1194 23:11:12.788351
1195 23:11:12.788684
1196 23:11:12.793826 [DQSOSCAuto] RK0, (LSB)MR18= 0x2928, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 399 ps
1197 23:11:12.797137 CH0 RK0: MR19=606, MR18=2928
1198 23:11:12.803942 CH0_RK0: MR19=0x606, MR18=0x2928, DQSOSC=399, MR23=63, INC=92, DEC=61
1199 23:11:12.804486
1200 23:11:12.807071 ----->DramcWriteLeveling(PI) begin...
1201 23:11:12.807513 ==
1202 23:11:12.810607 Dram Type= 6, Freq= 0, CH_0, rank 1
1203 23:11:12.813745 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1204 23:11:12.814183 ==
1205 23:11:12.817186 Write leveling (Byte 0): 32 => 32
1206 23:11:12.821002 Write leveling (Byte 1): 30 => 30
1207 23:11:12.824015 DramcWriteLeveling(PI) end<-----
1208 23:11:12.824555
1209 23:11:12.825002 ==
1210 23:11:12.827091 Dram Type= 6, Freq= 0, CH_0, rank 1
1211 23:11:12.830753 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1212 23:11:12.831299 ==
1213 23:11:12.834145 [Gating] SW mode calibration
1214 23:11:12.840202 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1215 23:11:12.847149 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1216 23:11:12.850633 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1217 23:11:12.853967 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1218 23:11:12.860462 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1219 23:11:12.863752 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1220 23:11:12.867133 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 23:11:12.874160 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 23:11:12.877192 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 23:11:12.880731 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 23:11:12.887450 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 23:11:12.890617 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 23:11:12.893850 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 23:11:12.900523 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 23:11:12.903740 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 23:11:12.906862 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 23:11:12.954368 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 23:11:12.954978 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 23:11:12.955432 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 23:11:12.955851 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1234 23:11:12.956623 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1235 23:11:12.956989 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 23:11:12.957412 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 23:11:12.957854 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 23:11:12.958350 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 23:11:12.958840 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1240 23:11:12.997910 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1241 23:11:12.998102 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 23:11:12.998464 0 9 8 | B1->B0 | 2626 2e2e | 1 1 | (1 1) (1 1)
1243 23:11:12.998814 0 9 12 | B1->B0 | 3231 3434 | 1 1 | (0 0) (1 1)
1244 23:11:12.999161 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1245 23:11:12.999309 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1246 23:11:12.999439 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1247 23:11:12.999578 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1248 23:11:12.999747 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1249 23:11:12.999862 0 10 4 | B1->B0 | 3434 3030 | 1 0 | (1 0) (0 1)
1250 23:11:12.999986 0 10 8 | B1->B0 | 3030 2424 | 1 0 | (1 0) (0 0)
1251 23:11:13.009838 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1252 23:11:13.010183 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1253 23:11:13.013511 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1254 23:11:13.016578 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1255 23:11:13.023382 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1256 23:11:13.026937 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1257 23:11:13.029971 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1258 23:11:13.033396 0 11 8 | B1->B0 | 3131 4040 | 0 0 | (0 0) (0 0)
1259 23:11:13.039997 0 11 12 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
1260 23:11:13.043410 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1261 23:11:13.046422 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1262 23:11:13.053725 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1263 23:11:13.057024 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1264 23:11:13.060556 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1265 23:11:13.067478 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1266 23:11:13.070432 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1267 23:11:13.073955 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1268 23:11:13.077764 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1269 23:11:13.084738 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1270 23:11:13.087869 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1271 23:11:13.091164 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1272 23:11:13.095347 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1273 23:11:13.102356 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1274 23:11:13.105315 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 23:11:13.108628 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1276 23:11:13.115137 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1277 23:11:13.118737 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1278 23:11:13.121899 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1279 23:11:13.128960 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1280 23:11:13.131757 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1281 23:11:13.135689 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1282 23:11:13.142190 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1283 23:11:13.145579 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1284 23:11:13.149169 Total UI for P1: 0, mck2ui 16
1285 23:11:13.152321 best dqsien dly found for B0: ( 0, 14, 8)
1286 23:11:13.155912 Total UI for P1: 0, mck2ui 16
1287 23:11:13.159686 best dqsien dly found for B1: ( 0, 14, 10)
1288 23:11:13.162705 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1289 23:11:13.165701 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1290 23:11:13.166120
1291 23:11:13.169597 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1292 23:11:13.172757 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1293 23:11:13.176073 [Gating] SW calibration Done
1294 23:11:13.176644 ==
1295 23:11:13.179214 Dram Type= 6, Freq= 0, CH_0, rank 1
1296 23:11:13.182762 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1297 23:11:13.183184 ==
1298 23:11:13.185685 RX Vref Scan: 0
1299 23:11:13.186158
1300 23:11:13.186494 RX Vref 0 -> 0, step: 1
1301 23:11:13.186804
1302 23:11:13.188904 RX Delay -130 -> 252, step: 16
1303 23:11:13.195714 iDelay=222, Bit 0, Center 69 (-50 ~ 189) 240
1304 23:11:13.199225 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1305 23:11:13.202617 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1306 23:11:13.205790 iDelay=222, Bit 3, Center 69 (-50 ~ 189) 240
1307 23:11:13.209019 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1308 23:11:13.212137 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1309 23:11:13.219075 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1310 23:11:13.222304 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1311 23:11:13.225856 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1312 23:11:13.229258 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1313 23:11:13.232658 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1314 23:11:13.239562 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1315 23:11:13.243126 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1316 23:11:13.245894 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1317 23:11:13.249183 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1318 23:11:13.256130 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1319 23:11:13.256653 ==
1320 23:11:13.259462 Dram Type= 6, Freq= 0, CH_0, rank 1
1321 23:11:13.262445 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1322 23:11:13.262973 ==
1323 23:11:13.263314 DQS Delay:
1324 23:11:13.266169 DQS0 = 0, DQS1 = 0
1325 23:11:13.266694 DQM Delay:
1326 23:11:13.269205 DQM0 = 76, DQM1 = 71
1327 23:11:13.269659 DQ Delay:
1328 23:11:13.273146 DQ0 =69, DQ1 =77, DQ2 =69, DQ3 =69
1329 23:11:13.276272 DQ4 =77, DQ5 =69, DQ6 =85, DQ7 =93
1330 23:11:13.279580 DQ8 =69, DQ9 =53, DQ10 =69, DQ11 =69
1331 23:11:13.282565 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1332 23:11:13.282990
1333 23:11:13.283325
1334 23:11:13.283636 ==
1335 23:11:13.285664 Dram Type= 6, Freq= 0, CH_0, rank 1
1336 23:11:13.289108 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1337 23:11:13.289554 ==
1338 23:11:13.289891
1339 23:11:13.290200
1340 23:11:13.292179 TX Vref Scan disable
1341 23:11:13.296142 == TX Byte 0 ==
1342 23:11:13.298999 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1343 23:11:13.302589 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1344 23:11:13.305947 == TX Byte 1 ==
1345 23:11:13.308972 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1346 23:11:13.312712 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1347 23:11:13.313150 ==
1348 23:11:13.315544 Dram Type= 6, Freq= 0, CH_0, rank 1
1349 23:11:13.319066 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1350 23:11:13.322144 ==
1351 23:11:13.334143 TX Vref=22, minBit 9, minWin=26, winSum=434
1352 23:11:13.337647 TX Vref=24, minBit 1, minWin=27, winSum=439
1353 23:11:13.340439 TX Vref=26, minBit 2, minWin=27, winSum=439
1354 23:11:13.344085 TX Vref=28, minBit 8, minWin=27, winSum=443
1355 23:11:13.347212 TX Vref=30, minBit 1, minWin=27, winSum=443
1356 23:11:13.354095 TX Vref=32, minBit 1, minWin=27, winSum=441
1357 23:11:13.357082 [TxChooseVref] Worse bit 8, Min win 27, Win sum 443, Final Vref 28
1358 23:11:13.357656
1359 23:11:13.360268 Final TX Range 1 Vref 28
1360 23:11:13.360834
1361 23:11:13.361314 ==
1362 23:11:13.363681 Dram Type= 6, Freq= 0, CH_0, rank 1
1363 23:11:13.366917 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1364 23:11:13.367454 ==
1365 23:11:13.370117
1366 23:11:13.370641
1367 23:11:13.371109 TX Vref Scan disable
1368 23:11:13.373345 == TX Byte 0 ==
1369 23:11:13.377072 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1370 23:11:13.383144 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1371 23:11:13.383428 == TX Byte 1 ==
1372 23:11:13.386984 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1373 23:11:13.390172 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1374 23:11:13.393540
1375 23:11:13.393768 [DATLAT]
1376 23:11:13.393898 Freq=800, CH0 RK1
1377 23:11:13.394012
1378 23:11:13.396611 DATLAT Default: 0xa
1379 23:11:13.396878 0, 0xFFFF, sum = 0
1380 23:11:13.400213 1, 0xFFFF, sum = 0
1381 23:11:13.400381 2, 0xFFFF, sum = 0
1382 23:11:13.404039 3, 0xFFFF, sum = 0
1383 23:11:13.404197 4, 0xFFFF, sum = 0
1384 23:11:13.407056 5, 0xFFFF, sum = 0
1385 23:11:13.407209 6, 0xFFFF, sum = 0
1386 23:11:13.410232 7, 0xFFFF, sum = 0
1387 23:11:13.410384 8, 0xFFFF, sum = 0
1388 23:11:13.413464 9, 0x0, sum = 1
1389 23:11:13.413725 10, 0x0, sum = 2
1390 23:11:13.417020 11, 0x0, sum = 3
1391 23:11:13.417251 12, 0x0, sum = 4
1392 23:11:13.420346 best_step = 10
1393 23:11:13.420579
1394 23:11:13.420707 ==
1395 23:11:13.423449 Dram Type= 6, Freq= 0, CH_0, rank 1
1396 23:11:13.426961 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1397 23:11:13.427151 ==
1398 23:11:13.430536 RX Vref Scan: 0
1399 23:11:13.430734
1400 23:11:13.430905 RX Vref 0 -> 0, step: 1
1401 23:11:13.431069
1402 23:11:13.433524 RX Delay -111 -> 252, step: 8
1403 23:11:13.440773 iDelay=209, Bit 0, Center 80 (-31 ~ 192) 224
1404 23:11:13.444219 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
1405 23:11:13.447062 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1406 23:11:13.450514 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
1407 23:11:13.453531 iDelay=209, Bit 4, Center 80 (-31 ~ 192) 224
1408 23:11:13.460459 iDelay=209, Bit 5, Center 64 (-55 ~ 184) 240
1409 23:11:13.463687 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1410 23:11:13.467463 iDelay=209, Bit 7, Center 88 (-31 ~ 208) 240
1411 23:11:13.470870 iDelay=209, Bit 8, Center 60 (-55 ~ 176) 232
1412 23:11:13.473831 iDelay=209, Bit 9, Center 52 (-63 ~ 168) 232
1413 23:11:13.480808 iDelay=209, Bit 10, Center 72 (-47 ~ 192) 240
1414 23:11:13.484075 iDelay=209, Bit 11, Center 60 (-55 ~ 176) 232
1415 23:11:13.487484 iDelay=209, Bit 12, Center 76 (-47 ~ 200) 248
1416 23:11:13.490381 iDelay=209, Bit 13, Center 76 (-39 ~ 192) 232
1417 23:11:13.494035 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
1418 23:11:13.500184 iDelay=209, Bit 15, Center 76 (-39 ~ 192) 232
1419 23:11:13.500604 ==
1420 23:11:13.503660 Dram Type= 6, Freq= 0, CH_0, rank 1
1421 23:11:13.506805 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1422 23:11:13.507223 ==
1423 23:11:13.507555 DQS Delay:
1424 23:11:13.510062 DQS0 = 0, DQS1 = 0
1425 23:11:13.510473 DQM Delay:
1426 23:11:13.513545 DQM0 = 79, DQM1 = 69
1427 23:11:13.513963 DQ Delay:
1428 23:11:13.516644 DQ0 =80, DQ1 =84, DQ2 =76, DQ3 =72
1429 23:11:13.520672 DQ4 =80, DQ5 =64, DQ6 =92, DQ7 =88
1430 23:11:13.523657 DQ8 =60, DQ9 =52, DQ10 =72, DQ11 =60
1431 23:11:13.526913 DQ12 =76, DQ13 =76, DQ14 =80, DQ15 =76
1432 23:11:13.527436
1433 23:11:13.527769
1434 23:11:13.536729 [DQSOSCAuto] RK1, (LSB)MR18= 0x4722, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 392 ps
1435 23:11:13.537253 CH0 RK1: MR19=606, MR18=4722
1436 23:11:13.543946 CH0_RK1: MR19=0x606, MR18=0x4722, DQSOSC=392, MR23=63, INC=96, DEC=64
1437 23:11:13.546853 [RxdqsGatingPostProcess] freq 800
1438 23:11:13.553702 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1439 23:11:13.556966 Pre-setting of DQS Precalculation
1440 23:11:13.560548 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1441 23:11:13.560964 ==
1442 23:11:13.563714 Dram Type= 6, Freq= 0, CH_1, rank 0
1443 23:11:13.566908 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1444 23:11:13.570568 ==
1445 23:11:13.573912 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1446 23:11:13.580425 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1447 23:11:13.588981 [CA 0] Center 37 (7~67) winsize 61
1448 23:11:13.592654 [CA 1] Center 36 (6~67) winsize 62
1449 23:11:13.595707 [CA 2] Center 34 (5~64) winsize 60
1450 23:11:13.599104 [CA 3] Center 34 (4~64) winsize 61
1451 23:11:13.602365 [CA 4] Center 34 (4~65) winsize 62
1452 23:11:13.605615 [CA 5] Center 34 (4~64) winsize 61
1453 23:11:13.606041
1454 23:11:13.609081 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1455 23:11:13.609661
1456 23:11:13.612665 [CATrainingPosCal] consider 1 rank data
1457 23:11:13.615872 u2DelayCellTimex100 = 270/100 ps
1458 23:11:13.618782 CA0 delay=37 (7~67),Diff = 3 PI (21 cell)
1459 23:11:13.622084 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1460 23:11:13.629321 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
1461 23:11:13.632281 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1462 23:11:13.635571 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1463 23:11:13.639136 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1464 23:11:13.639665
1465 23:11:13.641984 CA PerBit enable=1, Macro0, CA PI delay=34
1466 23:11:13.642410
1467 23:11:13.645203 [CBTSetCACLKResult] CA Dly = 34
1468 23:11:13.645761 CS Dly: 5 (0~36)
1469 23:11:13.648368 ==
1470 23:11:13.648789 Dram Type= 6, Freq= 0, CH_1, rank 1
1471 23:11:13.655353 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1472 23:11:13.655780 ==
1473 23:11:13.658936 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1474 23:11:13.665355 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1475 23:11:13.674998 [CA 0] Center 37 (7~67) winsize 61
1476 23:11:13.678150 [CA 1] Center 37 (7~67) winsize 61
1477 23:11:13.681824 [CA 2] Center 35 (5~65) winsize 61
1478 23:11:13.684946 [CA 3] Center 34 (4~64) winsize 61
1479 23:11:13.688359 [CA 4] Center 34 (4~65) winsize 62
1480 23:11:13.691608 [CA 5] Center 33 (3~64) winsize 62
1481 23:11:13.692144
1482 23:11:13.694673 [CmdBusTrainingLP45] Vref(ca) range 1: 30
1483 23:11:13.695095
1484 23:11:13.700809 [CATrainingPosCal] consider 2 rank data
1485 23:11:13.701645 u2DelayCellTimex100 = 270/100 ps
1486 23:11:13.704941 CA0 delay=37 (7~67),Diff = 3 PI (21 cell)
1487 23:11:13.708259 CA1 delay=37 (7~67),Diff = 3 PI (21 cell)
1488 23:11:13.715211 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
1489 23:11:13.718093 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1490 23:11:13.721931 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1491 23:11:13.724822 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1492 23:11:13.725254
1493 23:11:13.728512 CA PerBit enable=1, Macro0, CA PI delay=34
1494 23:11:13.729059
1495 23:11:13.732349 [CBTSetCACLKResult] CA Dly = 34
1496 23:11:13.732905 CS Dly: 5 (0~37)
1497 23:11:13.733264
1498 23:11:13.736132 ----->DramcWriteLeveling(PI) begin...
1499 23:11:13.736690 ==
1500 23:11:13.739591 Dram Type= 6, Freq= 0, CH_1, rank 0
1501 23:11:13.742475 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1502 23:11:13.742927 ==
1503 23:11:13.746575 Write leveling (Byte 0): 28 => 28
1504 23:11:13.750437 Write leveling (Byte 1): 31 => 31
1505 23:11:13.754124 DramcWriteLeveling(PI) end<-----
1506 23:11:13.754660
1507 23:11:13.755004 ==
1508 23:11:13.757528 Dram Type= 6, Freq= 0, CH_1, rank 0
1509 23:11:13.761302 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1510 23:11:13.761842 ==
1511 23:11:13.765641 [Gating] SW mode calibration
1512 23:11:13.772178 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1513 23:11:13.775289 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1514 23:11:13.782478 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1515 23:11:13.785471 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1516 23:11:13.788857 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1517 23:11:13.795253 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1518 23:11:13.798965 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 23:11:13.802133 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 23:11:13.805622 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 23:11:13.812241 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 23:11:13.815716 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 23:11:13.818797 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 23:11:13.825396 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 23:11:13.828738 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 23:11:13.831817 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 23:11:13.839115 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 23:11:13.842155 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 23:11:13.845339 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 23:11:13.851818 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 23:11:13.855337 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1532 23:11:13.859055 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1533 23:11:13.865757 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 23:11:13.868630 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 23:11:13.872475 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 23:11:13.878856 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 23:11:13.882424 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 23:11:13.885564 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 23:11:13.892572 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 23:11:13.895426 0 9 8 | B1->B0 | 2a2a 2929 | 1 1 | (1 1) (1 1)
1541 23:11:13.898873 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1542 23:11:13.905288 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1543 23:11:13.908821 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1544 23:11:13.912680 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1545 23:11:13.915260 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1546 23:11:13.922084 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1547 23:11:13.925425 0 10 4 | B1->B0 | 3333 3434 | 1 1 | (1 0) (0 1)
1548 23:11:13.928860 0 10 8 | B1->B0 | 2f2f 2e2e | 1 1 | (1 0) (1 0)
1549 23:11:13.935409 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1550 23:11:13.938340 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1551 23:11:13.942178 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1552 23:11:13.948247 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1553 23:11:13.951912 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1554 23:11:13.955221 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1555 23:11:13.962003 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1556 23:11:13.965024 0 11 8 | B1->B0 | 3939 3939 | 0 0 | (0 0) (0 0)
1557 23:11:13.968482 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1558 23:11:13.974994 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1559 23:11:13.978694 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1560 23:11:13.981943 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1561 23:11:13.988566 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1562 23:11:13.992164 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1563 23:11:13.995060 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1564 23:11:14.001813 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1565 23:11:14.005081 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1566 23:11:14.008653 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1567 23:11:14.015231 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1568 23:11:14.018302 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1569 23:11:14.021338 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1570 23:11:14.028630 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 23:11:14.031774 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 23:11:14.035238 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 23:11:14.038423 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1574 23:11:14.044991 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1575 23:11:14.048413 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1576 23:11:14.051432 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1577 23:11:14.058706 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1578 23:11:14.061843 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1579 23:11:14.065068 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1580 23:11:14.071658 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1581 23:11:14.074919 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1582 23:11:14.078447 Total UI for P1: 0, mck2ui 16
1583 23:11:14.081721 best dqsien dly found for B0: ( 0, 14, 6)
1584 23:11:14.085130 Total UI for P1: 0, mck2ui 16
1585 23:11:14.088779 best dqsien dly found for B1: ( 0, 14, 8)
1586 23:11:14.091868 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1587 23:11:14.094986 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1588 23:11:14.095512
1589 23:11:14.098172 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1590 23:11:14.101532 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1591 23:11:14.104735 [Gating] SW calibration Done
1592 23:11:14.105160 ==
1593 23:11:14.108642 Dram Type= 6, Freq= 0, CH_1, rank 0
1594 23:11:14.111775 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1595 23:11:14.115135 ==
1596 23:11:14.115561 RX Vref Scan: 0
1597 23:11:14.115899
1598 23:11:14.118230 RX Vref 0 -> 0, step: 1
1599 23:11:14.118746
1600 23:11:14.121465 RX Delay -130 -> 252, step: 16
1601 23:11:14.125027 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1602 23:11:14.128286 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1603 23:11:14.131887 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1604 23:11:14.135110 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1605 23:11:14.138166 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1606 23:11:14.144799 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1607 23:11:14.148174 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1608 23:11:14.151581 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1609 23:11:14.154657 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1610 23:11:14.158137 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1611 23:11:14.164949 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1612 23:11:14.168208 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1613 23:11:14.171555 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1614 23:11:14.174770 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1615 23:11:14.181683 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1616 23:11:14.184835 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1617 23:11:14.185265 ==
1618 23:11:14.187996 Dram Type= 6, Freq= 0, CH_1, rank 0
1619 23:11:14.191611 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1620 23:11:14.192042 ==
1621 23:11:14.192384 DQS Delay:
1622 23:11:14.194916 DQS0 = 0, DQS1 = 0
1623 23:11:14.195398 DQM Delay:
1624 23:11:14.198405 DQM0 = 81, DQM1 = 71
1625 23:11:14.198835 DQ Delay:
1626 23:11:14.201338 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1627 23:11:14.204658 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1628 23:11:14.208492 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
1629 23:11:14.211735 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1630 23:11:14.212264
1631 23:11:14.212604
1632 23:11:14.212920 ==
1633 23:11:14.214592 Dram Type= 6, Freq= 0, CH_1, rank 0
1634 23:11:14.217822 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1635 23:11:14.221405 ==
1636 23:11:14.221891
1637 23:11:14.222232
1638 23:11:14.222548 TX Vref Scan disable
1639 23:11:14.224820 == TX Byte 0 ==
1640 23:11:14.228621 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1641 23:11:14.231790 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1642 23:11:14.234977 == TX Byte 1 ==
1643 23:11:14.238376 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1644 23:11:14.241979 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1645 23:11:14.242514 ==
1646 23:11:14.244697 Dram Type= 6, Freq= 0, CH_1, rank 0
1647 23:11:14.251249 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1648 23:11:14.251767 ==
1649 23:11:14.264376 TX Vref=22, minBit 1, minWin=27, winSum=439
1650 23:11:14.267312 TX Vref=24, minBit 1, minWin=26, winSum=440
1651 23:11:14.270426 TX Vref=26, minBit 1, minWin=27, winSum=442
1652 23:11:14.273858 TX Vref=28, minBit 1, minWin=26, winSum=443
1653 23:11:14.277104 TX Vref=30, minBit 5, minWin=27, winSum=445
1654 23:11:14.280533 TX Vref=32, minBit 6, minWin=27, winSum=446
1655 23:11:14.287333 [TxChooseVref] Worse bit 6, Min win 27, Win sum 446, Final Vref 32
1656 23:11:14.287870
1657 23:11:14.290438 Final TX Range 1 Vref 32
1658 23:11:14.290875
1659 23:11:14.291214 ==
1660 23:11:14.293933 Dram Type= 6, Freq= 0, CH_1, rank 0
1661 23:11:14.297091 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1662 23:11:14.297579 ==
1663 23:11:14.297959
1664 23:11:14.298469
1665 23:11:14.300556 TX Vref Scan disable
1666 23:11:14.303789 == TX Byte 0 ==
1667 23:11:14.307805 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1668 23:11:14.311331 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1669 23:11:14.315046 == TX Byte 1 ==
1670 23:11:14.317983 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1671 23:11:14.321637 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1672 23:11:14.322158
1673 23:11:14.322498 [DATLAT]
1674 23:11:14.324367 Freq=800, CH1 RK0
1675 23:11:14.324823
1676 23:11:14.328031 DATLAT Default: 0xa
1677 23:11:14.328458 0, 0xFFFF, sum = 0
1678 23:11:14.331635 1, 0xFFFF, sum = 0
1679 23:11:14.332163 2, 0xFFFF, sum = 0
1680 23:11:14.334492 3, 0xFFFF, sum = 0
1681 23:11:14.334928 4, 0xFFFF, sum = 0
1682 23:11:14.337668 5, 0xFFFF, sum = 0
1683 23:11:14.338103 6, 0xFFFF, sum = 0
1684 23:11:14.341233 7, 0xFFFF, sum = 0
1685 23:11:14.341715 8, 0xFFFF, sum = 0
1686 23:11:14.344552 9, 0x0, sum = 1
1687 23:11:14.344983 10, 0x0, sum = 2
1688 23:11:14.348014 11, 0x0, sum = 3
1689 23:11:14.348539 12, 0x0, sum = 4
1690 23:11:14.348886 best_step = 10
1691 23:11:14.351721
1692 23:11:14.352239 ==
1693 23:11:14.354563 Dram Type= 6, Freq= 0, CH_1, rank 0
1694 23:11:14.358094 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1695 23:11:14.358624 ==
1696 23:11:14.358968 RX Vref Scan: 1
1697 23:11:14.359286
1698 23:11:14.361135 Set Vref Range= 32 -> 127
1699 23:11:14.361604
1700 23:11:14.365040 RX Vref 32 -> 127, step: 1
1701 23:11:14.365604
1702 23:11:14.367938 RX Delay -111 -> 252, step: 8
1703 23:11:14.368366
1704 23:11:14.371350 Set Vref, RX VrefLevel [Byte0]: 32
1705 23:11:14.374380 [Byte1]: 32
1706 23:11:14.374903
1707 23:11:14.378152 Set Vref, RX VrefLevel [Byte0]: 33
1708 23:11:14.381502 [Byte1]: 33
1709 23:11:14.382031
1710 23:11:14.384365 Set Vref, RX VrefLevel [Byte0]: 34
1711 23:11:14.387830 [Byte1]: 34
1712 23:11:14.392135
1713 23:11:14.392654 Set Vref, RX VrefLevel [Byte0]: 35
1714 23:11:14.394981 [Byte1]: 35
1715 23:11:14.399407
1716 23:11:14.399833 Set Vref, RX VrefLevel [Byte0]: 36
1717 23:11:14.402624 [Byte1]: 36
1718 23:11:14.406832
1719 23:11:14.407254 Set Vref, RX VrefLevel [Byte0]: 37
1720 23:11:14.410136 [Byte1]: 37
1721 23:11:14.414615
1722 23:11:14.415135 Set Vref, RX VrefLevel [Byte0]: 38
1723 23:11:14.417994 [Byte1]: 38
1724 23:11:14.422481
1725 23:11:14.422999 Set Vref, RX VrefLevel [Byte0]: 39
1726 23:11:14.425526 [Byte1]: 39
1727 23:11:14.429896
1728 23:11:14.430338 Set Vref, RX VrefLevel [Byte0]: 40
1729 23:11:14.433028 [Byte1]: 40
1730 23:11:14.437941
1731 23:11:14.438462 Set Vref, RX VrefLevel [Byte0]: 41
1732 23:11:14.441342 [Byte1]: 41
1733 23:11:14.445315
1734 23:11:14.445789 Set Vref, RX VrefLevel [Byte0]: 42
1735 23:11:14.448473 [Byte1]: 42
1736 23:11:14.452842
1737 23:11:14.453361 Set Vref, RX VrefLevel [Byte0]: 43
1738 23:11:14.456608 [Byte1]: 43
1739 23:11:14.460473
1740 23:11:14.460991 Set Vref, RX VrefLevel [Byte0]: 44
1741 23:11:14.464402 [Byte1]: 44
1742 23:11:14.468244
1743 23:11:14.468729 Set Vref, RX VrefLevel [Byte0]: 45
1744 23:11:14.471433 [Byte1]: 45
1745 23:11:14.475710
1746 23:11:14.476129 Set Vref, RX VrefLevel [Byte0]: 46
1747 23:11:14.479091 [Byte1]: 46
1748 23:11:14.484049
1749 23:11:14.484564 Set Vref, RX VrefLevel [Byte0]: 47
1750 23:11:14.486836 [Byte1]: 47
1751 23:11:14.491397
1752 23:11:14.491923 Set Vref, RX VrefLevel [Byte0]: 48
1753 23:11:14.494953 [Byte1]: 48
1754 23:11:14.498645
1755 23:11:14.499113 Set Vref, RX VrefLevel [Byte0]: 49
1756 23:11:14.501881 [Byte1]: 49
1757 23:11:14.506407
1758 23:11:14.506924 Set Vref, RX VrefLevel [Byte0]: 50
1759 23:11:14.509422 [Byte1]: 50
1760 23:11:14.514323
1761 23:11:14.514743 Set Vref, RX VrefLevel [Byte0]: 51
1762 23:11:14.517341 [Byte1]: 51
1763 23:11:14.521553
1764 23:11:14.522006 Set Vref, RX VrefLevel [Byte0]: 52
1765 23:11:14.525598 [Byte1]: 52
1766 23:11:14.529648
1767 23:11:14.530163 Set Vref, RX VrefLevel [Byte0]: 53
1768 23:11:14.533204 [Byte1]: 53
1769 23:11:14.536894
1770 23:11:14.537319 Set Vref, RX VrefLevel [Byte0]: 54
1771 23:11:14.540808 [Byte1]: 54
1772 23:11:14.545092
1773 23:11:14.545685 Set Vref, RX VrefLevel [Byte0]: 55
1774 23:11:14.547802 [Byte1]: 55
1775 23:11:14.552185
1776 23:11:14.552603 Set Vref, RX VrefLevel [Byte0]: 56
1777 23:11:14.556150 [Byte1]: 56
1778 23:11:14.560058
1779 23:11:14.560587 Set Vref, RX VrefLevel [Byte0]: 57
1780 23:11:14.563399 [Byte1]: 57
1781 23:11:14.568029
1782 23:11:14.568546 Set Vref, RX VrefLevel [Byte0]: 58
1783 23:11:14.570859 [Byte1]: 58
1784 23:11:14.575347
1785 23:11:14.575862 Set Vref, RX VrefLevel [Byte0]: 59
1786 23:11:14.578762 [Byte1]: 59
1787 23:11:14.583178
1788 23:11:14.583698 Set Vref, RX VrefLevel [Byte0]: 60
1789 23:11:14.586357 [Byte1]: 60
1790 23:11:14.590762
1791 23:11:14.591274 Set Vref, RX VrefLevel [Byte0]: 61
1792 23:11:14.593716 [Byte1]: 61
1793 23:11:14.598722
1794 23:11:14.599313 Set Vref, RX VrefLevel [Byte0]: 62
1795 23:11:14.601540 [Byte1]: 62
1796 23:11:14.605873
1797 23:11:14.606528 Set Vref, RX VrefLevel [Byte0]: 63
1798 23:11:14.609234 [Byte1]: 63
1799 23:11:14.613382
1800 23:11:14.613946 Set Vref, RX VrefLevel [Byte0]: 64
1801 23:11:14.617221 [Byte1]: 64
1802 23:11:14.621459
1803 23:11:14.622124 Set Vref, RX VrefLevel [Byte0]: 65
1804 23:11:14.624549 [Byte1]: 65
1805 23:11:14.629128
1806 23:11:14.629717 Set Vref, RX VrefLevel [Byte0]: 66
1807 23:11:14.632203 [Byte1]: 66
1808 23:11:14.636687
1809 23:11:14.637114 Set Vref, RX VrefLevel [Byte0]: 67
1810 23:11:14.639974 [Byte1]: 67
1811 23:11:14.644255
1812 23:11:14.644777 Set Vref, RX VrefLevel [Byte0]: 68
1813 23:11:14.647547 [Byte1]: 68
1814 23:11:14.651781
1815 23:11:14.652261 Set Vref, RX VrefLevel [Byte0]: 69
1816 23:11:14.654878 [Byte1]: 69
1817 23:11:14.659811
1818 23:11:14.660327 Set Vref, RX VrefLevel [Byte0]: 70
1819 23:11:14.662721 [Byte1]: 70
1820 23:11:14.667488
1821 23:11:14.668010 Set Vref, RX VrefLevel [Byte0]: 71
1822 23:11:14.670164 [Byte1]: 71
1823 23:11:14.674552
1824 23:11:14.675079 Set Vref, RX VrefLevel [Byte0]: 72
1825 23:11:14.678262 [Byte1]: 72
1826 23:11:14.682427
1827 23:11:14.682944 Set Vref, RX VrefLevel [Byte0]: 73
1828 23:11:14.685840 [Byte1]: 73
1829 23:11:14.690072
1830 23:11:14.690591 Set Vref, RX VrefLevel [Byte0]: 74
1831 23:11:14.693471 [Byte1]: 74
1832 23:11:14.697753
1833 23:11:14.698269 Final RX Vref Byte 0 = 59 to rank0
1834 23:11:14.701126 Final RX Vref Byte 1 = 57 to rank0
1835 23:11:14.704305 Final RX Vref Byte 0 = 59 to rank1
1836 23:11:14.707528 Final RX Vref Byte 1 = 57 to rank1==
1837 23:11:14.710853 Dram Type= 6, Freq= 0, CH_1, rank 0
1838 23:11:14.717770 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1839 23:11:14.718235 ==
1840 23:11:14.718576 DQS Delay:
1841 23:11:14.718894 DQS0 = 0, DQS1 = 0
1842 23:11:14.720919 DQM Delay:
1843 23:11:14.721343 DQM0 = 81, DQM1 = 71
1844 23:11:14.724090 DQ Delay:
1845 23:11:14.727683 DQ0 =84, DQ1 =76, DQ2 =72, DQ3 =76
1846 23:11:14.728108 DQ4 =80, DQ5 =92, DQ6 =92, DQ7 =76
1847 23:11:14.730851 DQ8 =56, DQ9 =64, DQ10 =72, DQ11 =68
1848 23:11:14.737732 DQ12 =80, DQ13 =76, DQ14 =76, DQ15 =76
1849 23:11:14.738258
1850 23:11:14.738602
1851 23:11:14.744648 [DQSOSCAuto] RK0, (LSB)MR18= 0xd17, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 406 ps
1852 23:11:14.747696 CH1 RK0: MR19=606, MR18=D17
1853 23:11:14.754032 CH1_RK0: MR19=0x606, MR18=0xD17, DQSOSC=404, MR23=63, INC=90, DEC=60
1854 23:11:14.754465
1855 23:11:14.757731 ----->DramcWriteLeveling(PI) begin...
1856 23:11:14.758258 ==
1857 23:11:14.760921 Dram Type= 6, Freq= 0, CH_1, rank 1
1858 23:11:14.764581 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1859 23:11:14.765109 ==
1860 23:11:14.767776 Write leveling (Byte 0): 27 => 27
1861 23:11:14.771119 Write leveling (Byte 1): 29 => 29
1862 23:11:14.774630 DramcWriteLeveling(PI) end<-----
1863 23:11:14.775056
1864 23:11:14.775386 ==
1865 23:11:14.777923 Dram Type= 6, Freq= 0, CH_1, rank 1
1866 23:11:14.781305 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1867 23:11:14.781872 ==
1868 23:11:14.784636 [Gating] SW mode calibration
1869 23:11:14.790993 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1870 23:11:14.797953 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1871 23:11:14.801536 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1872 23:11:14.804281 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1873 23:11:14.807772 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 23:11:14.814594 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 23:11:14.817985 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 23:11:14.821088 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 23:11:14.828020 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 23:11:14.831906 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 23:11:14.834572 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 23:11:14.840953 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 23:11:14.844642 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 23:11:14.848111 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 23:11:14.854557 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 23:11:14.857855 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 23:11:14.861158 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 23:11:14.867922 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 23:11:14.871193 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1888 23:11:14.874965 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1889 23:11:14.881638 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 23:11:14.884530 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 23:11:14.888072 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 23:11:14.894184 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 23:11:14.897423 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1894 23:11:14.900618 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 23:11:14.907527 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 23:11:14.910984 0 9 4 | B1->B0 | 2323 2d2c | 0 1 | (0 0) (0 0)
1897 23:11:14.914317 0 9 8 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
1898 23:11:14.921112 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1899 23:11:14.924606 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1900 23:11:14.928113 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1901 23:11:14.931543 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1902 23:11:14.937463 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1903 23:11:14.941356 0 10 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
1904 23:11:14.945028 0 10 4 | B1->B0 | 3434 2a2a | 1 0 | (1 1) (0 0)
1905 23:11:14.951392 0 10 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1906 23:11:14.954274 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1907 23:11:14.957739 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1908 23:11:14.964534 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1909 23:11:14.967781 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1910 23:11:14.971002 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1911 23:11:14.977386 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1912 23:11:14.981302 0 11 4 | B1->B0 | 2c2c 3535 | 1 0 | (0 0) (0 0)
1913 23:11:14.984573 0 11 8 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
1914 23:11:14.991199 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1915 23:11:14.994444 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1916 23:11:14.997189 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1917 23:11:15.003977 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1918 23:11:15.007541 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1919 23:11:15.010845 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1920 23:11:15.017350 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1921 23:11:15.021199 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1922 23:11:15.024320 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1923 23:11:15.030854 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1924 23:11:15.034132 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1925 23:11:15.037098 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1926 23:11:15.044112 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1927 23:11:15.047380 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1928 23:11:15.050518 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1929 23:11:15.056912 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1930 23:11:15.060678 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1931 23:11:15.063798 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1932 23:11:15.070266 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1933 23:11:15.073978 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1934 23:11:15.077274 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1935 23:11:15.080181 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1936 23:11:15.087112 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1937 23:11:15.090334 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1938 23:11:15.094117 Total UI for P1: 0, mck2ui 16
1939 23:11:15.097221 best dqsien dly found for B0: ( 0, 14, 4)
1940 23:11:15.100063 Total UI for P1: 0, mck2ui 16
1941 23:11:15.104009 best dqsien dly found for B1: ( 0, 14, 6)
1942 23:11:15.106958 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1943 23:11:15.110131 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1944 23:11:15.110559
1945 23:11:15.113975 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1946 23:11:15.116954 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1947 23:11:15.120134 [Gating] SW calibration Done
1948 23:11:15.120569 ==
1949 23:11:15.123576 Dram Type= 6, Freq= 0, CH_1, rank 1
1950 23:11:15.127180 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1951 23:11:15.130390 ==
1952 23:11:15.130853 RX Vref Scan: 0
1953 23:11:15.131189
1954 23:11:15.133680 RX Vref 0 -> 0, step: 1
1955 23:11:15.134113
1956 23:11:15.136835 RX Delay -130 -> 252, step: 16
1957 23:11:15.140632 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1958 23:11:15.144243 iDelay=222, Bit 1, Center 69 (-50 ~ 189) 240
1959 23:11:15.147337 iDelay=222, Bit 2, Center 61 (-66 ~ 189) 256
1960 23:11:15.150311 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1961 23:11:15.157356 iDelay=222, Bit 4, Center 69 (-50 ~ 189) 240
1962 23:11:15.160757 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1963 23:11:15.163594 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1964 23:11:15.166741 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1965 23:11:15.170620 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1966 23:11:15.173648 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1967 23:11:15.180825 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1968 23:11:15.183513 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1969 23:11:15.187213 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1970 23:11:15.190549 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1971 23:11:15.197294 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1972 23:11:15.200806 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1973 23:11:15.201234 ==
1974 23:11:15.203841 Dram Type= 6, Freq= 0, CH_1, rank 1
1975 23:11:15.207323 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1976 23:11:15.207868 ==
1977 23:11:15.208211 DQS Delay:
1978 23:11:15.210329 DQS0 = 0, DQS1 = 0
1979 23:11:15.210799 DQM Delay:
1980 23:11:15.214380 DQM0 = 77, DQM1 = 71
1981 23:11:15.214899 DQ Delay:
1982 23:11:15.217345 DQ0 =85, DQ1 =69, DQ2 =61, DQ3 =77
1983 23:11:15.220378 DQ4 =69, DQ5 =85, DQ6 =93, DQ7 =77
1984 23:11:15.224104 DQ8 =61, DQ9 =61, DQ10 =77, DQ11 =61
1985 23:11:15.227479 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1986 23:11:15.228021
1987 23:11:15.228362
1988 23:11:15.228677 ==
1989 23:11:15.230354 Dram Type= 6, Freq= 0, CH_1, rank 1
1990 23:11:15.233936 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1991 23:11:15.234365 ==
1992 23:11:15.237154
1993 23:11:15.237833
1994 23:11:15.238189 TX Vref Scan disable
1995 23:11:15.240762 == TX Byte 0 ==
1996 23:11:15.243766 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1997 23:11:15.247206 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1998 23:11:15.250564 == TX Byte 1 ==
1999 23:11:15.253820 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2000 23:11:15.257282 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2001 23:11:15.257745 ==
2002 23:11:15.260390 Dram Type= 6, Freq= 0, CH_1, rank 1
2003 23:11:15.267543 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2004 23:11:15.268169 ==
2005 23:11:15.279093 TX Vref=22, minBit 6, minWin=27, winSum=450
2006 23:11:15.282979 TX Vref=24, minBit 1, minWin=28, winSum=456
2007 23:11:15.285746 TX Vref=26, minBit 1, minWin=28, winSum=456
2008 23:11:15.289091 TX Vref=28, minBit 1, minWin=28, winSum=459
2009 23:11:15.292340 TX Vref=30, minBit 5, minWin=27, winSum=460
2010 23:11:15.295739 TX Vref=32, minBit 0, minWin=28, winSum=462
2011 23:11:15.302204 [TxChooseVref] Worse bit 0, Min win 28, Win sum 462, Final Vref 32
2012 23:11:15.302767
2013 23:11:15.305863 Final TX Range 1 Vref 32
2014 23:11:15.306329
2015 23:11:15.306900 ==
2016 23:11:15.308994 Dram Type= 6, Freq= 0, CH_1, rank 1
2017 23:11:15.312420 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2018 23:11:15.312843 ==
2019 23:11:15.313172
2020 23:11:15.315662
2021 23:11:15.316241 TX Vref Scan disable
2022 23:11:15.318761 == TX Byte 0 ==
2023 23:11:15.322572 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2024 23:11:15.325855 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2025 23:11:15.329243 == TX Byte 1 ==
2026 23:11:15.332264 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2027 23:11:15.336125 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2028 23:11:15.339013
2029 23:11:15.339531 [DATLAT]
2030 23:11:15.339873 Freq=800, CH1 RK1
2031 23:11:15.340198
2032 23:11:15.342450 DATLAT Default: 0xa
2033 23:11:15.342933 0, 0xFFFF, sum = 0
2034 23:11:15.345763 1, 0xFFFF, sum = 0
2035 23:11:15.346188 2, 0xFFFF, sum = 0
2036 23:11:15.349820 3, 0xFFFF, sum = 0
2037 23:11:15.350363 4, 0xFFFF, sum = 0
2038 23:11:15.352849 5, 0xFFFF, sum = 0
2039 23:11:15.353378 6, 0xFFFF, sum = 0
2040 23:11:15.355791 7, 0xFFFF, sum = 0
2041 23:11:15.359624 8, 0xFFFF, sum = 0
2042 23:11:15.360160 9, 0x0, sum = 1
2043 23:11:15.360513 10, 0x0, sum = 2
2044 23:11:15.362297 11, 0x0, sum = 3
2045 23:11:15.362730 12, 0x0, sum = 4
2046 23:11:15.366253 best_step = 10
2047 23:11:15.366773
2048 23:11:15.367117 ==
2049 23:11:15.369533 Dram Type= 6, Freq= 0, CH_1, rank 1
2050 23:11:15.372247 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2051 23:11:15.372676 ==
2052 23:11:15.375867 RX Vref Scan: 0
2053 23:11:15.376309
2054 23:11:15.376648 RX Vref 0 -> 0, step: 1
2055 23:11:15.376966
2056 23:11:15.378983 RX Delay -111 -> 252, step: 8
2057 23:11:15.386142 iDelay=209, Bit 0, Center 80 (-39 ~ 200) 240
2058 23:11:15.389759 iDelay=209, Bit 1, Center 72 (-47 ~ 192) 240
2059 23:11:15.393015 iDelay=209, Bit 2, Center 68 (-55 ~ 192) 248
2060 23:11:15.395810 iDelay=209, Bit 3, Center 76 (-47 ~ 200) 248
2061 23:11:15.399440 iDelay=209, Bit 4, Center 80 (-39 ~ 200) 240
2062 23:11:15.405743 iDelay=209, Bit 5, Center 88 (-31 ~ 208) 240
2063 23:11:15.409215 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
2064 23:11:15.412618 iDelay=209, Bit 7, Center 76 (-47 ~ 200) 248
2065 23:11:15.415939 iDelay=209, Bit 8, Center 60 (-63 ~ 184) 248
2066 23:11:15.419571 iDelay=209, Bit 9, Center 64 (-55 ~ 184) 240
2067 23:11:15.426002 iDelay=209, Bit 10, Center 80 (-39 ~ 200) 240
2068 23:11:15.429193 iDelay=209, Bit 11, Center 68 (-55 ~ 192) 248
2069 23:11:15.432552 iDelay=209, Bit 12, Center 80 (-39 ~ 200) 240
2070 23:11:15.435852 iDelay=209, Bit 13, Center 80 (-39 ~ 200) 240
2071 23:11:15.439503 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
2072 23:11:15.446066 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
2073 23:11:15.446575 ==
2074 23:11:15.449229 Dram Type= 6, Freq= 0, CH_1, rank 1
2075 23:11:15.452751 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2076 23:11:15.453214 ==
2077 23:11:15.453601 DQS Delay:
2078 23:11:15.455730 DQS0 = 0, DQS1 = 0
2079 23:11:15.456167 DQM Delay:
2080 23:11:15.459428 DQM0 = 78, DQM1 = 74
2081 23:11:15.459957 DQ Delay:
2082 23:11:15.463071 DQ0 =80, DQ1 =72, DQ2 =68, DQ3 =76
2083 23:11:15.466031 DQ4 =80, DQ5 =88, DQ6 =88, DQ7 =76
2084 23:11:15.469296 DQ8 =60, DQ9 =64, DQ10 =80, DQ11 =68
2085 23:11:15.472726 DQ12 =80, DQ13 =80, DQ14 =80, DQ15 =80
2086 23:11:15.473145
2087 23:11:15.473500
2088 23:11:15.479470 [DQSOSCAuto] RK1, (LSB)MR18= 0x2139, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 401 ps
2089 23:11:15.482789 CH1 RK1: MR19=606, MR18=2139
2090 23:11:15.489171 CH1_RK1: MR19=0x606, MR18=0x2139, DQSOSC=395, MR23=63, INC=94, DEC=63
2091 23:11:15.492689 [RxdqsGatingPostProcess] freq 800
2092 23:11:15.499473 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2093 23:11:15.502761 Pre-setting of DQS Precalculation
2094 23:11:15.506460 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2095 23:11:15.512580 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2096 23:11:15.519194 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2097 23:11:15.519703
2098 23:11:15.520040
2099 23:11:15.522867 [Calibration Summary] 1600 Mbps
2100 23:11:15.525693 CH 0, Rank 0
2101 23:11:15.526120 SW Impedance : PASS
2102 23:11:15.529089 DUTY Scan : NO K
2103 23:11:15.532761 ZQ Calibration : PASS
2104 23:11:15.533335 Jitter Meter : NO K
2105 23:11:15.535952 CBT Training : PASS
2106 23:11:15.539368 Write leveling : PASS
2107 23:11:15.539892 RX DQS gating : PASS
2108 23:11:15.542394 RX DQ/DQS(RDDQC) : PASS
2109 23:11:15.546134 TX DQ/DQS : PASS
2110 23:11:15.546675 RX DATLAT : PASS
2111 23:11:15.549553 RX DQ/DQS(Engine): PASS
2112 23:11:15.550076 TX OE : NO K
2113 23:11:15.552265 All Pass.
2114 23:11:15.552698
2115 23:11:15.553030 CH 0, Rank 1
2116 23:11:15.555646 SW Impedance : PASS
2117 23:11:15.556071 DUTY Scan : NO K
2118 23:11:15.559171 ZQ Calibration : PASS
2119 23:11:15.563190 Jitter Meter : NO K
2120 23:11:15.563772 CBT Training : PASS
2121 23:11:15.566250 Write leveling : PASS
2122 23:11:15.569528 RX DQS gating : PASS
2123 23:11:15.570071 RX DQ/DQS(RDDQC) : PASS
2124 23:11:15.572390 TX DQ/DQS : PASS
2125 23:11:15.576316 RX DATLAT : PASS
2126 23:11:15.576840 RX DQ/DQS(Engine): PASS
2127 23:11:15.579301 TX OE : NO K
2128 23:11:15.579720 All Pass.
2129 23:11:15.580051
2130 23:11:15.582322 CH 1, Rank 0
2131 23:11:15.582738 SW Impedance : PASS
2132 23:11:15.586135 DUTY Scan : NO K
2133 23:11:15.589388 ZQ Calibration : PASS
2134 23:11:15.590056 Jitter Meter : NO K
2135 23:11:15.592549 CBT Training : PASS
2136 23:11:15.593067 Write leveling : PASS
2137 23:11:15.596232 RX DQS gating : PASS
2138 23:11:15.599447 RX DQ/DQS(RDDQC) : PASS
2139 23:11:15.599972 TX DQ/DQS : PASS
2140 23:11:15.602159 RX DATLAT : PASS
2141 23:11:15.606063 RX DQ/DQS(Engine): PASS
2142 23:11:15.606480 TX OE : NO K
2143 23:11:15.609225 All Pass.
2144 23:11:15.609887
2145 23:11:15.610257 CH 1, Rank 1
2146 23:11:15.612378 SW Impedance : PASS
2147 23:11:15.612797 DUTY Scan : NO K
2148 23:11:15.615891 ZQ Calibration : PASS
2149 23:11:15.619331 Jitter Meter : NO K
2150 23:11:15.619916 CBT Training : PASS
2151 23:11:15.622529 Write leveling : PASS
2152 23:11:15.625685 RX DQS gating : PASS
2153 23:11:15.626118 RX DQ/DQS(RDDQC) : PASS
2154 23:11:15.629215 TX DQ/DQS : PASS
2155 23:11:15.632633 RX DATLAT : PASS
2156 23:11:15.633151 RX DQ/DQS(Engine): PASS
2157 23:11:15.635861 TX OE : NO K
2158 23:11:15.636413 All Pass.
2159 23:11:15.636760
2160 23:11:15.638939 DramC Write-DBI off
2161 23:11:15.642685 PER_BANK_REFRESH: Hybrid Mode
2162 23:11:15.643210 TX_TRACKING: ON
2163 23:11:15.645553 [GetDramInforAfterCalByMRR] Vendor 6.
2164 23:11:15.649165 [GetDramInforAfterCalByMRR] Revision 606.
2165 23:11:15.652681 [GetDramInforAfterCalByMRR] Revision 2 0.
2166 23:11:15.656168 MR0 0x3b3b
2167 23:11:15.656603 MR8 0x5151
2168 23:11:15.659070 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2169 23:11:15.659508
2170 23:11:15.659953 MR0 0x3b3b
2171 23:11:15.662848 MR8 0x5151
2172 23:11:15.666038 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2173 23:11:15.666480
2174 23:11:15.672601 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2175 23:11:15.675680 [FAST_K] Save calibration result to emmc
2176 23:11:15.682624 [FAST_K] Save calibration result to emmc
2177 23:11:15.683146 dram_init: config_dvfs: 1
2178 23:11:15.685787 dramc_set_vcore_voltage set vcore to 662500
2179 23:11:15.689549 Read voltage for 1200, 2
2180 23:11:15.689986 Vio18 = 0
2181 23:11:15.692800 Vcore = 662500
2182 23:11:15.693339 Vdram = 0
2183 23:11:15.693838 Vddq = 0
2184 23:11:15.696312 Vmddr = 0
2185 23:11:15.699687 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2186 23:11:15.705996 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2187 23:11:15.706433 MEM_TYPE=3, freq_sel=15
2188 23:11:15.709356 sv_algorithm_assistance_LP4_1600
2189 23:11:15.716499 ============ PULL DRAM RESETB DOWN ============
2190 23:11:15.719400 ========== PULL DRAM RESETB DOWN end =========
2191 23:11:15.722785 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2192 23:11:15.725788 ===================================
2193 23:11:15.729310 LPDDR4 DRAM CONFIGURATION
2194 23:11:15.732455 ===================================
2195 23:11:15.732890 EX_ROW_EN[0] = 0x0
2196 23:11:15.736334 EX_ROW_EN[1] = 0x0
2197 23:11:15.739599 LP4Y_EN = 0x0
2198 23:11:15.740034 WORK_FSP = 0x0
2199 23:11:15.742883 WL = 0x4
2200 23:11:15.743423 RL = 0x4
2201 23:11:15.746169 BL = 0x2
2202 23:11:15.746718 RPST = 0x0
2203 23:11:15.749521 RD_PRE = 0x0
2204 23:11:15.749962 WR_PRE = 0x1
2205 23:11:15.753059 WR_PST = 0x0
2206 23:11:15.753530 DBI_WR = 0x0
2207 23:11:15.756036 DBI_RD = 0x0
2208 23:11:15.756472 OTF = 0x1
2209 23:11:15.759778 ===================================
2210 23:11:15.762833 ===================================
2211 23:11:15.765927 ANA top config
2212 23:11:15.769686 ===================================
2213 23:11:15.770128 DLL_ASYNC_EN = 0
2214 23:11:15.772710 ALL_SLAVE_EN = 0
2215 23:11:15.776487 NEW_RANK_MODE = 1
2216 23:11:15.779849 DLL_IDLE_MODE = 1
2217 23:11:15.780367 LP45_APHY_COMB_EN = 1
2218 23:11:15.782842 TX_ODT_DIS = 1
2219 23:11:15.786063 NEW_8X_MODE = 1
2220 23:11:15.789303 ===================================
2221 23:11:15.792736 ===================================
2222 23:11:15.795802 data_rate = 2400
2223 23:11:15.799532 CKR = 1
2224 23:11:15.800101 DQ_P2S_RATIO = 8
2225 23:11:15.803019 ===================================
2226 23:11:15.805919 CA_P2S_RATIO = 8
2227 23:11:15.809155 DQ_CA_OPEN = 0
2228 23:11:15.812886 DQ_SEMI_OPEN = 0
2229 23:11:15.815410 CA_SEMI_OPEN = 0
2230 23:11:15.818987 CA_FULL_RATE = 0
2231 23:11:15.819070 DQ_CKDIV4_EN = 0
2232 23:11:15.822135 CA_CKDIV4_EN = 0
2233 23:11:15.825728 CA_PREDIV_EN = 0
2234 23:11:15.828721 PH8_DLY = 17
2235 23:11:15.832191 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2236 23:11:15.835643 DQ_AAMCK_DIV = 4
2237 23:11:15.835726 CA_AAMCK_DIV = 4
2238 23:11:15.838991 CA_ADMCK_DIV = 4
2239 23:11:15.842019 DQ_TRACK_CA_EN = 0
2240 23:11:15.845285 CA_PICK = 1200
2241 23:11:15.848946 CA_MCKIO = 1200
2242 23:11:15.851984 MCKIO_SEMI = 0
2243 23:11:15.855338 PLL_FREQ = 2366
2244 23:11:15.858625 DQ_UI_PI_RATIO = 32
2245 23:11:15.858708 CA_UI_PI_RATIO = 0
2246 23:11:15.861970 ===================================
2247 23:11:15.865539 ===================================
2248 23:11:15.868568 memory_type:LPDDR4
2249 23:11:15.872292 GP_NUM : 10
2250 23:11:15.872376 SRAM_EN : 1
2251 23:11:15.875436 MD32_EN : 0
2252 23:11:15.878529 ===================================
2253 23:11:15.881900 [ANA_INIT] >>>>>>>>>>>>>>
2254 23:11:15.881983 <<<<<< [CONFIGURE PHASE]: ANA_TX
2255 23:11:15.885316 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2256 23:11:15.888942 ===================================
2257 23:11:15.892285 data_rate = 2400,PCW = 0X5b00
2258 23:11:15.895880 ===================================
2259 23:11:15.898600 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2260 23:11:15.905761 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2261 23:11:15.912201 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2262 23:11:15.915474 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2263 23:11:15.918897 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2264 23:11:15.922203 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2265 23:11:15.925332 [ANA_INIT] flow start
2266 23:11:15.925441 [ANA_INIT] PLL >>>>>>>>
2267 23:11:15.928878 [ANA_INIT] PLL <<<<<<<<
2268 23:11:15.932423 [ANA_INIT] MIDPI >>>>>>>>
2269 23:11:15.932512 [ANA_INIT] MIDPI <<<<<<<<
2270 23:11:15.935935 [ANA_INIT] DLL >>>>>>>>
2271 23:11:15.938856 [ANA_INIT] DLL <<<<<<<<
2272 23:11:15.938951 [ANA_INIT] flow end
2273 23:11:15.945750 ============ LP4 DIFF to SE enter ============
2274 23:11:15.949050 ============ LP4 DIFF to SE exit ============
2275 23:11:15.949240 [ANA_INIT] <<<<<<<<<<<<<
2276 23:11:15.952876 [Flow] Enable top DCM control >>>>>
2277 23:11:15.955866 [Flow] Enable top DCM control <<<<<
2278 23:11:15.959187 Enable DLL master slave shuffle
2279 23:11:15.965818 ==============================================================
2280 23:11:15.969358 Gating Mode config
2281 23:11:15.973088 ==============================================================
2282 23:11:15.976070 Config description:
2283 23:11:15.986276 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2284 23:11:15.993308 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2285 23:11:15.996515 SELPH_MODE 0: By rank 1: By Phase
2286 23:11:16.002988 ==============================================================
2287 23:11:16.006388 GAT_TRACK_EN = 1
2288 23:11:16.009575 RX_GATING_MODE = 2
2289 23:11:16.010105 RX_GATING_TRACK_MODE = 2
2290 23:11:16.013084 SELPH_MODE = 1
2291 23:11:16.016211 PICG_EARLY_EN = 1
2292 23:11:16.019628 VALID_LAT_VALUE = 1
2293 23:11:16.026157 ==============================================================
2294 23:11:16.030134 Enter into Gating configuration >>>>
2295 23:11:16.033089 Exit from Gating configuration <<<<
2296 23:11:16.036525 Enter into DVFS_PRE_config >>>>>
2297 23:11:16.046418 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2298 23:11:16.049327 Exit from DVFS_PRE_config <<<<<
2299 23:11:16.052584 Enter into PICG configuration >>>>
2300 23:11:16.056465 Exit from PICG configuration <<<<
2301 23:11:16.059405 [RX_INPUT] configuration >>>>>
2302 23:11:16.062952 [RX_INPUT] configuration <<<<<
2303 23:11:16.065808 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2304 23:11:16.072396 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2305 23:11:16.079154 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2306 23:11:16.082110 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2307 23:11:16.088955 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2308 23:11:16.095848 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2309 23:11:16.098985 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2310 23:11:16.102664 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2311 23:11:16.108859 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2312 23:11:16.112887 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2313 23:11:16.116090 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2314 23:11:16.122289 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2315 23:11:16.125791 ===================================
2316 23:11:16.126127 LPDDR4 DRAM CONFIGURATION
2317 23:11:16.129235 ===================================
2318 23:11:16.132473 EX_ROW_EN[0] = 0x0
2319 23:11:16.135811 EX_ROW_EN[1] = 0x0
2320 23:11:16.136213 LP4Y_EN = 0x0
2321 23:11:16.139009 WORK_FSP = 0x0
2322 23:11:16.139440 WL = 0x4
2323 23:11:16.142118 RL = 0x4
2324 23:11:16.142548 BL = 0x2
2325 23:11:16.145403 RPST = 0x0
2326 23:11:16.145864 RD_PRE = 0x0
2327 23:11:16.149302 WR_PRE = 0x1
2328 23:11:16.149775 WR_PST = 0x0
2329 23:11:16.152824 DBI_WR = 0x0
2330 23:11:16.153345 DBI_RD = 0x0
2331 23:11:16.155670 OTF = 0x1
2332 23:11:16.158817 ===================================
2333 23:11:16.162147 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2334 23:11:16.165646 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2335 23:11:16.172534 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2336 23:11:16.175425 ===================================
2337 23:11:16.175857 LPDDR4 DRAM CONFIGURATION
2338 23:11:16.179183 ===================================
2339 23:11:16.182423 EX_ROW_EN[0] = 0x10
2340 23:11:16.185851 EX_ROW_EN[1] = 0x0
2341 23:11:16.186377 LP4Y_EN = 0x0
2342 23:11:16.188775 WORK_FSP = 0x0
2343 23:11:16.189203 WL = 0x4
2344 23:11:16.192531 RL = 0x4
2345 23:11:16.193054 BL = 0x2
2346 23:11:16.195472 RPST = 0x0
2347 23:11:16.195999 RD_PRE = 0x0
2348 23:11:16.198878 WR_PRE = 0x1
2349 23:11:16.199452 WR_PST = 0x0
2350 23:11:16.202074 DBI_WR = 0x0
2351 23:11:16.202516 DBI_RD = 0x0
2352 23:11:16.205337 OTF = 0x1
2353 23:11:16.208955 ===================================
2354 23:11:16.215138 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2355 23:11:16.215581 ==
2356 23:11:16.218607 Dram Type= 6, Freq= 0, CH_0, rank 0
2357 23:11:16.221885 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2358 23:11:16.222315 ==
2359 23:11:16.225462 [Duty_Offset_Calibration]
2360 23:11:16.225991 B0:2 B1:0 CA:3
2361 23:11:16.226332
2362 23:11:16.228689 [DutyScan_Calibration_Flow] k_type=0
2363 23:11:16.238309
2364 23:11:16.238726 ==CLK 0==
2365 23:11:16.241792 Final CLK duty delay cell = 0
2366 23:11:16.244938 [0] MAX Duty = 5031%(X100), DQS PI = 12
2367 23:11:16.248896 [0] MIN Duty = 4906%(X100), DQS PI = 54
2368 23:11:16.249415 [0] AVG Duty = 4968%(X100)
2369 23:11:16.252102
2370 23:11:16.252652 CH0 CLK Duty spec in!! Max-Min= 125%
2371 23:11:16.258605 [DutyScan_Calibration_Flow] ====Done====
2372 23:11:16.259109
2373 23:11:16.262026 [DutyScan_Calibration_Flow] k_type=1
2374 23:11:16.277240
2375 23:11:16.277814 ==DQS 0 ==
2376 23:11:16.280424 Final DQS duty delay cell = 0
2377 23:11:16.283837 [0] MAX Duty = 5062%(X100), DQS PI = 28
2378 23:11:16.287217 [0] MIN Duty = 4907%(X100), DQS PI = 4
2379 23:11:16.287643 [0] AVG Duty = 4984%(X100)
2380 23:11:16.290411
2381 23:11:16.290833 ==DQS 1 ==
2382 23:11:16.293852 Final DQS duty delay cell = -4
2383 23:11:16.297140 [-4] MAX Duty = 4969%(X100), DQS PI = 22
2384 23:11:16.300610 [-4] MIN Duty = 4875%(X100), DQS PI = 16
2385 23:11:16.303879 [-4] AVG Duty = 4922%(X100)
2386 23:11:16.304320
2387 23:11:16.306999 CH0 DQS 0 Duty spec in!! Max-Min= 155%
2388 23:11:16.307426
2389 23:11:16.310205 CH0 DQS 1 Duty spec in!! Max-Min= 94%
2390 23:11:16.313855 [DutyScan_Calibration_Flow] ====Done====
2391 23:11:16.314277
2392 23:11:16.316930 [DutyScan_Calibration_Flow] k_type=3
2393 23:11:16.333762
2394 23:11:16.334270 ==DQM 0 ==
2395 23:11:16.337019 Final DQM duty delay cell = 0
2396 23:11:16.340580 [0] MAX Duty = 5093%(X100), DQS PI = 12
2397 23:11:16.343489 [0] MIN Duty = 4876%(X100), DQS PI = 0
2398 23:11:16.347255 [0] AVG Duty = 4984%(X100)
2399 23:11:16.347679
2400 23:11:16.348039 ==DQM 1 ==
2401 23:11:16.350108 Final DQM duty delay cell = 0
2402 23:11:16.353279 [0] MAX Duty = 4969%(X100), DQS PI = 50
2403 23:11:16.356998 [0] MIN Duty = 4876%(X100), DQS PI = 8
2404 23:11:16.357422 [0] AVG Duty = 4922%(X100)
2405 23:11:16.360254
2406 23:11:16.363223 CH0 DQM 0 Duty spec in!! Max-Min= 217%
2407 23:11:16.363648
2408 23:11:16.366760 CH0 DQM 1 Duty spec in!! Max-Min= 93%
2409 23:11:16.370904 [DutyScan_Calibration_Flow] ====Done====
2410 23:11:16.371422
2411 23:11:16.373436 [DutyScan_Calibration_Flow] k_type=2
2412 23:11:16.388338
2413 23:11:16.388846 ==DQ 0 ==
2414 23:11:16.391837 Final DQ duty delay cell = -4
2415 23:11:16.395341 [-4] MAX Duty = 5031%(X100), DQS PI = 20
2416 23:11:16.398574 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2417 23:11:16.401692 [-4] AVG Duty = 4969%(X100)
2418 23:11:16.402129
2419 23:11:16.402460 ==DQ 1 ==
2420 23:11:16.405183 Final DQ duty delay cell = -4
2421 23:11:16.408878 [-4] MAX Duty = 4969%(X100), DQS PI = 0
2422 23:11:16.412213 [-4] MIN Duty = 4876%(X100), DQS PI = 20
2423 23:11:16.415121 [-4] AVG Duty = 4922%(X100)
2424 23:11:16.415544
2425 23:11:16.418703 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2426 23:11:16.419126
2427 23:11:16.421955 CH0 DQ 1 Duty spec in!! Max-Min= 93%
2428 23:11:16.425224 [DutyScan_Calibration_Flow] ====Done====
2429 23:11:16.425800 ==
2430 23:11:16.428790 Dram Type= 6, Freq= 0, CH_1, rank 0
2431 23:11:16.431955 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2432 23:11:16.432497 ==
2433 23:11:16.435062 [Duty_Offset_Calibration]
2434 23:11:16.435497 B0:1 B1:-2 CA:0
2435 23:11:16.436023
2436 23:11:16.438268 [DutyScan_Calibration_Flow] k_type=0
2437 23:11:16.449098
2438 23:11:16.449675 ==CLK 0==
2439 23:11:16.452101 Final CLK duty delay cell = 0
2440 23:11:16.455924 [0] MAX Duty = 5031%(X100), DQS PI = 18
2441 23:11:16.458857 [0] MIN Duty = 4844%(X100), DQS PI = 58
2442 23:11:16.459295 [0] AVG Duty = 4937%(X100)
2443 23:11:16.462386
2444 23:11:16.466095 CH1 CLK Duty spec in!! Max-Min= 187%
2445 23:11:16.469259 [DutyScan_Calibration_Flow] ====Done====
2446 23:11:16.469849
2447 23:11:16.472102 [DutyScan_Calibration_Flow] k_type=1
2448 23:11:16.487644
2449 23:11:16.488183 ==DQS 0 ==
2450 23:11:16.490917 Final DQS duty delay cell = -4
2451 23:11:16.494474 [-4] MAX Duty = 5000%(X100), DQS PI = 16
2452 23:11:16.497879 [-4] MIN Duty = 4876%(X100), DQS PI = 50
2453 23:11:16.500680 [-4] AVG Duty = 4938%(X100)
2454 23:11:16.501224
2455 23:11:16.501726 ==DQS 1 ==
2456 23:11:16.504372 Final DQS duty delay cell = 0
2457 23:11:16.507342 [0] MAX Duty = 5093%(X100), DQS PI = 0
2458 23:11:16.510900 [0] MIN Duty = 4875%(X100), DQS PI = 26
2459 23:11:16.514169 [0] AVG Duty = 4984%(X100)
2460 23:11:16.514628
2461 23:11:16.517641 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2462 23:11:16.518069
2463 23:11:16.520867 CH1 DQS 1 Duty spec in!! Max-Min= 218%
2464 23:11:16.524452 [DutyScan_Calibration_Flow] ====Done====
2465 23:11:16.524974
2466 23:11:16.527273 [DutyScan_Calibration_Flow] k_type=3
2467 23:11:16.544380
2468 23:11:16.544903 ==DQM 0 ==
2469 23:11:16.548020 Final DQM duty delay cell = 0
2470 23:11:16.551254 [0] MAX Duty = 5000%(X100), DQS PI = 22
2471 23:11:16.553984 [0] MIN Duty = 4876%(X100), DQS PI = 2
2472 23:11:16.554415 [0] AVG Duty = 4938%(X100)
2473 23:11:16.557682
2474 23:11:16.558200 ==DQM 1 ==
2475 23:11:16.560966 Final DQM duty delay cell = 0
2476 23:11:16.564642 [0] MAX Duty = 5031%(X100), DQS PI = 36
2477 23:11:16.567437 [0] MIN Duty = 4907%(X100), DQS PI = 0
2478 23:11:16.567874 [0] AVG Duty = 4969%(X100)
2479 23:11:16.571009
2480 23:11:16.574424 CH1 DQM 0 Duty spec in!! Max-Min= 124%
2481 23:11:16.574949
2482 23:11:16.578106 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2483 23:11:16.580892 [DutyScan_Calibration_Flow] ====Done====
2484 23:11:16.581322
2485 23:11:16.584236 [DutyScan_Calibration_Flow] k_type=2
2486 23:11:16.600737
2487 23:11:16.601253 ==DQ 0 ==
2488 23:11:16.603949 Final DQ duty delay cell = 0
2489 23:11:16.607056 [0] MAX Duty = 5062%(X100), DQS PI = 12
2490 23:11:16.610606 [0] MIN Duty = 4938%(X100), DQS PI = 54
2491 23:11:16.611036 [0] AVG Duty = 5000%(X100)
2492 23:11:16.611379
2493 23:11:16.614048 ==DQ 1 ==
2494 23:11:16.617226 Final DQ duty delay cell = 0
2495 23:11:16.620609 [0] MAX Duty = 5125%(X100), DQS PI = 36
2496 23:11:16.624470 [0] MIN Duty = 4969%(X100), DQS PI = 26
2497 23:11:16.624994 [0] AVG Duty = 5047%(X100)
2498 23:11:16.625337
2499 23:11:16.627332 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2500 23:11:16.627761
2501 23:11:16.631080 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2502 23:11:16.637054 [DutyScan_Calibration_Flow] ====Done====
2503 23:11:16.640345 nWR fixed to 30
2504 23:11:16.640775 [ModeRegInit_LP4] CH0 RK0
2505 23:11:16.643805 [ModeRegInit_LP4] CH0 RK1
2506 23:11:16.647305 [ModeRegInit_LP4] CH1 RK0
2507 23:11:16.647732 [ModeRegInit_LP4] CH1 RK1
2508 23:11:16.650399 match AC timing 7
2509 23:11:16.653822 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2510 23:11:16.657199 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2511 23:11:16.663875 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2512 23:11:16.667293 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2513 23:11:16.673462 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2514 23:11:16.673964 ==
2515 23:11:16.677618 Dram Type= 6, Freq= 0, CH_0, rank 0
2516 23:11:16.680620 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2517 23:11:16.681146 ==
2518 23:11:16.687440 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2519 23:11:16.693460 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2520 23:11:16.701077 [CA 0] Center 40 (10~71) winsize 62
2521 23:11:16.703896 [CA 1] Center 39 (9~70) winsize 62
2522 23:11:16.706815 [CA 2] Center 36 (6~66) winsize 61
2523 23:11:16.710776 [CA 3] Center 35 (5~66) winsize 62
2524 23:11:16.713793 [CA 4] Center 34 (4~65) winsize 62
2525 23:11:16.717292 [CA 5] Center 33 (3~64) winsize 62
2526 23:11:16.717879
2527 23:11:16.720431 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2528 23:11:16.720868
2529 23:11:16.723968 [CATrainingPosCal] consider 1 rank data
2530 23:11:16.727333 u2DelayCellTimex100 = 270/100 ps
2531 23:11:16.730838 CA0 delay=40 (10~71),Diff = 7 PI (33 cell)
2532 23:11:16.737590 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2533 23:11:16.740877 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2534 23:11:16.743772 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2535 23:11:16.747654 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2536 23:11:16.750565 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2537 23:11:16.751111
2538 23:11:16.754110 CA PerBit enable=1, Macro0, CA PI delay=33
2539 23:11:16.754647
2540 23:11:16.757237 [CBTSetCACLKResult] CA Dly = 33
2541 23:11:16.757809 CS Dly: 7 (0~38)
2542 23:11:16.760248 ==
2543 23:11:16.764119 Dram Type= 6, Freq= 0, CH_0, rank 1
2544 23:11:16.767305 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2545 23:11:16.767737 ==
2546 23:11:16.770672 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2547 23:11:16.777195 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2548 23:11:16.786914 [CA 0] Center 40 (10~70) winsize 61
2549 23:11:16.790126 [CA 1] Center 40 (10~70) winsize 61
2550 23:11:16.793731 [CA 2] Center 35 (5~66) winsize 62
2551 23:11:16.796929 [CA 3] Center 35 (5~66) winsize 62
2552 23:11:16.799931 [CA 4] Center 34 (3~65) winsize 63
2553 23:11:16.803265 [CA 5] Center 33 (3~64) winsize 62
2554 23:11:16.803694
2555 23:11:16.806307 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2556 23:11:16.806734
2557 23:11:16.809925 [CATrainingPosCal] consider 2 rank data
2558 23:11:16.813464 u2DelayCellTimex100 = 270/100 ps
2559 23:11:16.816925 CA0 delay=40 (10~70),Diff = 7 PI (33 cell)
2560 23:11:16.823479 CA1 delay=40 (10~70),Diff = 7 PI (33 cell)
2561 23:11:16.826460 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2562 23:11:16.829950 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2563 23:11:16.833572 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2564 23:11:16.836917 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2565 23:11:16.837522
2566 23:11:16.840117 CA PerBit enable=1, Macro0, CA PI delay=33
2567 23:11:16.840664
2568 23:11:16.843474 [CBTSetCACLKResult] CA Dly = 33
2569 23:11:16.846327 CS Dly: 8 (0~40)
2570 23:11:16.846776
2571 23:11:16.849628 ----->DramcWriteLeveling(PI) begin...
2572 23:11:16.850177 ==
2573 23:11:16.852921 Dram Type= 6, Freq= 0, CH_0, rank 0
2574 23:11:16.856411 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2575 23:11:16.856936 ==
2576 23:11:16.859730 Write leveling (Byte 0): 32 => 32
2577 23:11:16.863267 Write leveling (Byte 1): 30 => 30
2578 23:11:16.866331 DramcWriteLeveling(PI) end<-----
2579 23:11:16.866867
2580 23:11:16.867219 ==
2581 23:11:16.869768 Dram Type= 6, Freq= 0, CH_0, rank 0
2582 23:11:16.873578 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2583 23:11:16.874100 ==
2584 23:11:16.876765 [Gating] SW mode calibration
2585 23:11:16.883007 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2586 23:11:16.889681 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2587 23:11:16.893177 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2588 23:11:16.896348 0 15 4 | B1->B0 | 2929 3333 | 0 0 | (0 0) (0 0)
2589 23:11:16.902669 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2590 23:11:16.906200 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2591 23:11:16.909459 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2592 23:11:16.916070 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2593 23:11:16.919841 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2594 23:11:16.922801 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2595 23:11:16.929255 1 0 0 | B1->B0 | 3232 2727 | 0 0 | (0 1) (0 0)
2596 23:11:16.932898 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2597 23:11:16.936400 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2598 23:11:16.943206 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2599 23:11:16.945992 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2600 23:11:16.949652 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2601 23:11:16.956235 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2602 23:11:16.959302 1 0 28 | B1->B0 | 2323 2727 | 0 0 | (0 0) (1 1)
2603 23:11:16.962513 1 1 0 | B1->B0 | 2424 2c2c | 0 0 | (0 0) (0 0)
2604 23:11:16.969230 1 1 4 | B1->B0 | 3c3c 4545 | 0 0 | (0 0) (0 0)
2605 23:11:16.972970 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2606 23:11:16.976014 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2607 23:11:16.979260 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2608 23:11:16.986161 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2609 23:11:16.989403 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2610 23:11:16.992685 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2611 23:11:16.999087 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2612 23:11:17.003279 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2613 23:11:17.005671 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2614 23:11:17.012731 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2615 23:11:17.015827 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2616 23:11:17.019453 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2617 23:11:17.025886 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2618 23:11:17.029091 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2619 23:11:17.032754 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2620 23:11:17.039137 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2621 23:11:17.042729 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2622 23:11:17.045678 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2623 23:11:17.052680 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2624 23:11:17.056224 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2625 23:11:17.059128 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2626 23:11:17.066171 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2627 23:11:17.069216 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2628 23:11:17.072263 Total UI for P1: 0, mck2ui 16
2629 23:11:17.075761 best dqsien dly found for B0: ( 1, 3, 28)
2630 23:11:17.079191 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2631 23:11:17.082804 Total UI for P1: 0, mck2ui 16
2632 23:11:17.086106 best dqsien dly found for B1: ( 1, 4, 0)
2633 23:11:17.089162 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2634 23:11:17.092391 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2635 23:11:17.092911
2636 23:11:17.095886 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2637 23:11:17.102455 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2638 23:11:17.102985 [Gating] SW calibration Done
2639 23:11:17.103334 ==
2640 23:11:17.105916 Dram Type= 6, Freq= 0, CH_0, rank 0
2641 23:11:17.112136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2642 23:11:17.112650 ==
2643 23:11:17.112996 RX Vref Scan: 0
2644 23:11:17.113314
2645 23:11:17.115347 RX Vref 0 -> 0, step: 1
2646 23:11:17.115962
2647 23:11:17.118843 RX Delay -40 -> 252, step: 8
2648 23:11:17.122794 iDelay=200, Bit 0, Center 111 (32 ~ 191) 160
2649 23:11:17.125854 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
2650 23:11:17.129107 iDelay=200, Bit 2, Center 111 (32 ~ 191) 160
2651 23:11:17.132380 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2652 23:11:17.139550 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2653 23:11:17.142343 iDelay=200, Bit 5, Center 99 (24 ~ 175) 152
2654 23:11:17.145451 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
2655 23:11:17.149143 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2656 23:11:17.152420 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2657 23:11:17.155382 iDelay=200, Bit 9, Center 87 (8 ~ 167) 160
2658 23:11:17.162543 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2659 23:11:17.165677 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2660 23:11:17.169306 iDelay=200, Bit 12, Center 107 (32 ~ 183) 152
2661 23:11:17.172380 iDelay=200, Bit 13, Center 107 (32 ~ 183) 152
2662 23:11:17.178988 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
2663 23:11:17.182015 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2664 23:11:17.182445 ==
2665 23:11:17.186082 Dram Type= 6, Freq= 0, CH_0, rank 0
2666 23:11:17.189105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2667 23:11:17.189698 ==
2668 23:11:17.192870 DQS Delay:
2669 23:11:17.193389 DQS0 = 0, DQS1 = 0
2670 23:11:17.193786 DQM Delay:
2671 23:11:17.195184 DQM0 = 112, DQM1 = 102
2672 23:11:17.195611 DQ Delay:
2673 23:11:17.199092 DQ0 =111, DQ1 =111, DQ2 =111, DQ3 =107
2674 23:11:17.201849 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123
2675 23:11:17.205303 DQ8 =91, DQ9 =87, DQ10 =103, DQ11 =95
2676 23:11:17.209046 DQ12 =107, DQ13 =107, DQ14 =115, DQ15 =111
2677 23:11:17.209628
2678 23:11:17.211965
2679 23:11:17.212388 ==
2680 23:11:17.215233 Dram Type= 6, Freq= 0, CH_0, rank 0
2681 23:11:17.218916 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2682 23:11:17.219361 ==
2683 23:11:17.219701
2684 23:11:17.220015
2685 23:11:17.221968 TX Vref Scan disable
2686 23:11:17.222391 == TX Byte 0 ==
2687 23:11:17.228899 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2688 23:11:17.231917 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2689 23:11:17.232366 == TX Byte 1 ==
2690 23:11:17.238335 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2691 23:11:17.241864 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2692 23:11:17.242287 ==
2693 23:11:17.245172 Dram Type= 6, Freq= 0, CH_0, rank 0
2694 23:11:17.248425 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2695 23:11:17.248852 ==
2696 23:11:17.261178 TX Vref=22, minBit 0, minWin=26, winSum=417
2697 23:11:17.264940 TX Vref=24, minBit 1, minWin=26, winSum=423
2698 23:11:17.267944 TX Vref=26, minBit 1, minWin=26, winSum=429
2699 23:11:17.271432 TX Vref=28, minBit 10, minWin=26, winSum=435
2700 23:11:17.274317 TX Vref=30, minBit 12, minWin=26, winSum=434
2701 23:11:17.281347 TX Vref=32, minBit 3, minWin=26, winSum=431
2702 23:11:17.284371 [TxChooseVref] Worse bit 10, Min win 26, Win sum 435, Final Vref 28
2703 23:11:17.284920
2704 23:11:17.287599 Final TX Range 1 Vref 28
2705 23:11:17.288156
2706 23:11:17.288606 ==
2707 23:11:17.290935 Dram Type= 6, Freq= 0, CH_0, rank 0
2708 23:11:17.294865 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2709 23:11:17.298142 ==
2710 23:11:17.298681
2711 23:11:17.299131
2712 23:11:17.299549 TX Vref Scan disable
2713 23:11:17.300916 == TX Byte 0 ==
2714 23:11:17.304390 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2715 23:11:17.310926 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2716 23:11:17.311472 == TX Byte 1 ==
2717 23:11:17.314333 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2718 23:11:17.320701 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2719 23:11:17.321153
2720 23:11:17.321687 [DATLAT]
2721 23:11:17.322109 Freq=1200, CH0 RK0
2722 23:11:17.322523
2723 23:11:17.324329 DATLAT Default: 0xd
2724 23:11:17.324763 0, 0xFFFF, sum = 0
2725 23:11:17.327774 1, 0xFFFF, sum = 0
2726 23:11:17.330814 2, 0xFFFF, sum = 0
2727 23:11:17.331259 3, 0xFFFF, sum = 0
2728 23:11:17.334552 4, 0xFFFF, sum = 0
2729 23:11:17.335101 5, 0xFFFF, sum = 0
2730 23:11:17.337561 6, 0xFFFF, sum = 0
2731 23:11:17.338006 7, 0xFFFF, sum = 0
2732 23:11:17.341105 8, 0xFFFF, sum = 0
2733 23:11:17.341579 9, 0xFFFF, sum = 0
2734 23:11:17.344286 10, 0xFFFF, sum = 0
2735 23:11:17.344820 11, 0xFFFF, sum = 0
2736 23:11:17.347680 12, 0x0, sum = 1
2737 23:11:17.348212 13, 0x0, sum = 2
2738 23:11:17.350875 14, 0x0, sum = 3
2739 23:11:17.351380 15, 0x0, sum = 4
2740 23:11:17.354013 best_step = 13
2741 23:11:17.354431
2742 23:11:17.354762 ==
2743 23:11:17.358103 Dram Type= 6, Freq= 0, CH_0, rank 0
2744 23:11:17.361458 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2745 23:11:17.362054 ==
2746 23:11:17.362518 RX Vref Scan: 1
2747 23:11:17.362941
2748 23:11:17.364508 Set Vref Range= 32 -> 127
2749 23:11:17.364943
2750 23:11:17.367314 RX Vref 32 -> 127, step: 1
2751 23:11:17.367749
2752 23:11:17.371289 RX Delay -37 -> 252, step: 4
2753 23:11:17.371835
2754 23:11:17.374384 Set Vref, RX VrefLevel [Byte0]: 32
2755 23:11:17.377573 [Byte1]: 32
2756 23:11:17.378011
2757 23:11:17.380480 Set Vref, RX VrefLevel [Byte0]: 33
2758 23:11:17.384043 [Byte1]: 33
2759 23:11:17.387754
2760 23:11:17.388204 Set Vref, RX VrefLevel [Byte0]: 34
2761 23:11:17.390895 [Byte1]: 34
2762 23:11:17.395545
2763 23:11:17.396063 Set Vref, RX VrefLevel [Byte0]: 35
2764 23:11:17.399001 [Byte1]: 35
2765 23:11:17.403687
2766 23:11:17.404158 Set Vref, RX VrefLevel [Byte0]: 36
2767 23:11:17.406859 [Byte1]: 36
2768 23:11:17.411841
2769 23:11:17.412265 Set Vref, RX VrefLevel [Byte0]: 37
2770 23:11:17.414864 [Byte1]: 37
2771 23:11:17.419403
2772 23:11:17.419828 Set Vref, RX VrefLevel [Byte0]: 38
2773 23:11:17.423052 [Byte1]: 38
2774 23:11:17.427795
2775 23:11:17.428218 Set Vref, RX VrefLevel [Byte0]: 39
2776 23:11:17.430952 [Byte1]: 39
2777 23:11:17.435740
2778 23:11:17.436158 Set Vref, RX VrefLevel [Byte0]: 40
2779 23:11:17.439022 [Byte1]: 40
2780 23:11:17.443621
2781 23:11:17.444128 Set Vref, RX VrefLevel [Byte0]: 41
2782 23:11:17.447042 [Byte1]: 41
2783 23:11:17.451821
2784 23:11:17.452250 Set Vref, RX VrefLevel [Byte0]: 42
2785 23:11:17.454942 [Byte1]: 42
2786 23:11:17.459753
2787 23:11:17.460169 Set Vref, RX VrefLevel [Byte0]: 43
2788 23:11:17.462745 [Byte1]: 43
2789 23:11:17.468029
2790 23:11:17.468559 Set Vref, RX VrefLevel [Byte0]: 44
2791 23:11:17.471309 [Byte1]: 44
2792 23:11:17.475660
2793 23:11:17.476189 Set Vref, RX VrefLevel [Byte0]: 45
2794 23:11:17.479335 [Byte1]: 45
2795 23:11:17.483851
2796 23:11:17.484269 Set Vref, RX VrefLevel [Byte0]: 46
2797 23:11:17.486984 [Byte1]: 46
2798 23:11:17.491418
2799 23:11:17.491837 Set Vref, RX VrefLevel [Byte0]: 47
2800 23:11:17.495210 [Byte1]: 47
2801 23:11:17.499756
2802 23:11:17.500278 Set Vref, RX VrefLevel [Byte0]: 48
2803 23:11:17.503435 [Byte1]: 48
2804 23:11:17.507861
2805 23:11:17.508282 Set Vref, RX VrefLevel [Byte0]: 49
2806 23:11:17.510857 [Byte1]: 49
2807 23:11:17.515580
2808 23:11:17.516004 Set Vref, RX VrefLevel [Byte0]: 50
2809 23:11:17.519488 [Byte1]: 50
2810 23:11:17.523748
2811 23:11:17.524271 Set Vref, RX VrefLevel [Byte0]: 51
2812 23:11:17.527469 [Byte1]: 51
2813 23:11:17.532064
2814 23:11:17.532569 Set Vref, RX VrefLevel [Byte0]: 52
2815 23:11:17.534618 [Byte1]: 52
2816 23:11:17.540062
2817 23:11:17.540579 Set Vref, RX VrefLevel [Byte0]: 53
2818 23:11:17.543217 [Byte1]: 53
2819 23:11:17.547996
2820 23:11:17.548512 Set Vref, RX VrefLevel [Byte0]: 54
2821 23:11:17.551020 [Byte1]: 54
2822 23:11:17.555821
2823 23:11:17.556339 Set Vref, RX VrefLevel [Byte0]: 55
2824 23:11:17.559104 [Byte1]: 55
2825 23:11:17.563918
2826 23:11:17.564436 Set Vref, RX VrefLevel [Byte0]: 56
2827 23:11:17.567016 [Byte1]: 56
2828 23:11:17.571666
2829 23:11:17.572182 Set Vref, RX VrefLevel [Byte0]: 57
2830 23:11:17.575139 [Byte1]: 57
2831 23:11:17.579803
2832 23:11:17.580319 Set Vref, RX VrefLevel [Byte0]: 58
2833 23:11:17.583477 [Byte1]: 58
2834 23:11:17.588042
2835 23:11:17.588558 Set Vref, RX VrefLevel [Byte0]: 59
2836 23:11:17.591209 [Byte1]: 59
2837 23:11:17.595926
2838 23:11:17.596443 Set Vref, RX VrefLevel [Byte0]: 60
2839 23:11:17.599534 [Byte1]: 60
2840 23:11:17.603842
2841 23:11:17.604382 Set Vref, RX VrefLevel [Byte0]: 61
2842 23:11:17.606852 [Byte1]: 61
2843 23:11:17.611567
2844 23:11:17.612085 Set Vref, RX VrefLevel [Byte0]: 62
2845 23:11:17.615073 [Byte1]: 62
2846 23:11:17.619897
2847 23:11:17.620415 Set Vref, RX VrefLevel [Byte0]: 63
2848 23:11:17.622781 [Byte1]: 63
2849 23:11:17.627901
2850 23:11:17.628419 Set Vref, RX VrefLevel [Byte0]: 64
2851 23:11:17.634076 [Byte1]: 64
2852 23:11:17.634502
2853 23:11:17.637332 Set Vref, RX VrefLevel [Byte0]: 65
2854 23:11:17.640924 [Byte1]: 65
2855 23:11:17.641445
2856 23:11:17.644518 Set Vref, RX VrefLevel [Byte0]: 66
2857 23:11:17.647530 [Byte1]: 66
2858 23:11:17.651525
2859 23:11:17.652045 Set Vref, RX VrefLevel [Byte0]: 67
2860 23:11:17.655094 [Byte1]: 67
2861 23:11:17.659931
2862 23:11:17.660463 Set Vref, RX VrefLevel [Byte0]: 68
2863 23:11:17.663124 [Byte1]: 68
2864 23:11:17.667773
2865 23:11:17.668292 Set Vref, RX VrefLevel [Byte0]: 69
2866 23:11:17.670808 [Byte1]: 69
2867 23:11:17.675874
2868 23:11:17.676387 Set Vref, RX VrefLevel [Byte0]: 70
2869 23:11:17.679354 [Byte1]: 70
2870 23:11:17.684044
2871 23:11:17.684556 Set Vref, RX VrefLevel [Byte0]: 71
2872 23:11:17.687252 [Byte1]: 71
2873 23:11:17.692260
2874 23:11:17.692771 Set Vref, RX VrefLevel [Byte0]: 72
2875 23:11:17.695108 [Byte1]: 72
2876 23:11:17.699772
2877 23:11:17.700288 Set Vref, RX VrefLevel [Byte0]: 73
2878 23:11:17.703680 [Byte1]: 73
2879 23:11:17.707777
2880 23:11:17.708196 Set Vref, RX VrefLevel [Byte0]: 74
2881 23:11:17.710950 [Byte1]: 74
2882 23:11:17.715794
2883 23:11:17.716330 Set Vref, RX VrefLevel [Byte0]: 75
2884 23:11:17.718873 [Byte1]: 75
2885 23:11:17.724017
2886 23:11:17.724542 Set Vref, RX VrefLevel [Byte0]: 76
2887 23:11:17.727199 [Byte1]: 76
2888 23:11:17.731905
2889 23:11:17.732423 Final RX Vref Byte 0 = 62 to rank0
2890 23:11:17.735221 Final RX Vref Byte 1 = 47 to rank0
2891 23:11:17.738253 Final RX Vref Byte 0 = 62 to rank1
2892 23:11:17.741619 Final RX Vref Byte 1 = 47 to rank1==
2893 23:11:17.745509 Dram Type= 6, Freq= 0, CH_0, rank 0
2894 23:11:17.751779 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2895 23:11:17.752287 ==
2896 23:11:17.752628 DQS Delay:
2897 23:11:17.752947 DQS0 = 0, DQS1 = 0
2898 23:11:17.754882 DQM Delay:
2899 23:11:17.755308 DQM0 = 112, DQM1 = 98
2900 23:11:17.758197 DQ Delay:
2901 23:11:17.762029 DQ0 =112, DQ1 =112, DQ2 =110, DQ3 =108
2902 23:11:17.765272 DQ4 =112, DQ5 =104, DQ6 =118, DQ7 =120
2903 23:11:17.768985 DQ8 =90, DQ9 =82, DQ10 =100, DQ11 =92
2904 23:11:17.772039 DQ12 =104, DQ13 =104, DQ14 =112, DQ15 =106
2905 23:11:17.772559
2906 23:11:17.772897
2907 23:11:17.778330 [DQSOSCAuto] RK0, (LSB)MR18= 0xf9f9, (MSB)MR19= 0x303, tDQSOscB0 = 412 ps tDQSOscB1 = 412 ps
2908 23:11:17.782063 CH0 RK0: MR19=303, MR18=F9F9
2909 23:11:17.788402 CH0_RK0: MR19=0x303, MR18=0xF9F9, DQSOSC=412, MR23=63, INC=38, DEC=25
2910 23:11:17.788912
2911 23:11:17.792091 ----->DramcWriteLeveling(PI) begin...
2912 23:11:17.792618 ==
2913 23:11:17.795503 Dram Type= 6, Freq= 0, CH_0, rank 1
2914 23:11:17.798772 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2915 23:11:17.799294 ==
2916 23:11:17.802011 Write leveling (Byte 0): 32 => 32
2917 23:11:17.805422 Write leveling (Byte 1): 31 => 31
2918 23:11:17.808551 DramcWriteLeveling(PI) end<-----
2919 23:11:17.809095
2920 23:11:17.809434 ==
2921 23:11:17.812578 Dram Type= 6, Freq= 0, CH_0, rank 1
2922 23:11:17.815680 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2923 23:11:17.818327 ==
2924 23:11:17.818769 [Gating] SW mode calibration
2925 23:11:17.828435 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2926 23:11:17.832095 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2927 23:11:17.834881 0 15 0 | B1->B0 | 2727 3434 | 0 0 | (0 0) (0 0)
2928 23:11:17.841728 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2929 23:11:17.845446 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2930 23:11:17.848638 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2931 23:11:17.855151 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2932 23:11:17.858433 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2933 23:11:17.861548 0 15 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
2934 23:11:17.868367 0 15 28 | B1->B0 | 3434 2424 | 1 0 | (1 1) (1 0)
2935 23:11:17.871695 1 0 0 | B1->B0 | 2828 2323 | 0 0 | (1 0) (0 0)
2936 23:11:17.875290 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2937 23:11:17.881401 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2938 23:11:17.885003 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2939 23:11:17.888818 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2940 23:11:17.895202 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2941 23:11:17.899015 1 0 24 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
2942 23:11:17.901969 1 0 28 | B1->B0 | 2323 4242 | 0 0 | (0 0) (0 0)
2943 23:11:17.908269 1 1 0 | B1->B0 | 4040 4646 | 1 0 | (0 0) (0 0)
2944 23:11:17.911393 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2945 23:11:17.915183 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2946 23:11:17.918363 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2947 23:11:17.925406 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2948 23:11:17.928237 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2949 23:11:17.931529 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2950 23:11:17.938306 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2951 23:11:17.941734 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2952 23:11:17.945006 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2953 23:11:17.951619 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2954 23:11:17.954792 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2955 23:11:17.958382 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2956 23:11:17.965243 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2957 23:11:17.968481 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2958 23:11:17.971993 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2959 23:11:17.978560 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2960 23:11:17.981620 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2961 23:11:17.984838 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2962 23:11:17.991504 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2963 23:11:17.995111 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2964 23:11:17.998170 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2965 23:11:18.004783 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2966 23:11:18.008325 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2967 23:11:18.011929 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2968 23:11:18.015364 Total UI for P1: 0, mck2ui 16
2969 23:11:18.018396 best dqsien dly found for B0: ( 1, 3, 26)
2970 23:11:18.021553 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2971 23:11:18.024620 Total UI for P1: 0, mck2ui 16
2972 23:11:18.028792 best dqsien dly found for B1: ( 1, 4, 0)
2973 23:11:18.031919 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2974 23:11:18.034902 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2975 23:11:18.037931
2976 23:11:18.041827 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2977 23:11:18.045267 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2978 23:11:18.048851 [Gating] SW calibration Done
2979 23:11:18.049373 ==
2980 23:11:18.051618 Dram Type= 6, Freq= 0, CH_0, rank 1
2981 23:11:18.055004 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2982 23:11:18.055426 ==
2983 23:11:18.055754 RX Vref Scan: 0
2984 23:11:18.056064
2985 23:11:18.058651 RX Vref 0 -> 0, step: 1
2986 23:11:18.059170
2987 23:11:18.061384 RX Delay -40 -> 252, step: 8
2988 23:11:18.064787 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2989 23:11:18.068147 iDelay=200, Bit 1, Center 111 (32 ~ 191) 160
2990 23:11:18.074949 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2991 23:11:18.078163 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2992 23:11:18.081446 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2993 23:11:18.085105 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2994 23:11:18.088204 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
2995 23:11:18.092124 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2996 23:11:18.098253 iDelay=200, Bit 8, Center 91 (24 ~ 159) 136
2997 23:11:18.101942 iDelay=200, Bit 9, Center 83 (8 ~ 159) 152
2998 23:11:18.104963 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2999 23:11:18.107957 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
3000 23:11:18.111248 iDelay=200, Bit 12, Center 107 (32 ~ 183) 152
3001 23:11:18.118015 iDelay=200, Bit 13, Center 107 (32 ~ 183) 152
3002 23:11:18.121286 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3003 23:11:18.124923 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3004 23:11:18.125462 ==
3005 23:11:18.128282 Dram Type= 6, Freq= 0, CH_0, rank 1
3006 23:11:18.131177 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3007 23:11:18.131615 ==
3008 23:11:18.135038 DQS Delay:
3009 23:11:18.135588 DQS0 = 0, DQS1 = 0
3010 23:11:18.138081 DQM Delay:
3011 23:11:18.138515 DQM0 = 112, DQM1 = 101
3012 23:11:18.142057 DQ Delay:
3013 23:11:18.144772 DQ0 =111, DQ1 =111, DQ2 =111, DQ3 =107
3014 23:11:18.147932 DQ4 =115, DQ5 =103, DQ6 =119, DQ7 =123
3015 23:11:18.151365 DQ8 =91, DQ9 =83, DQ10 =103, DQ11 =95
3016 23:11:18.155241 DQ12 =107, DQ13 =107, DQ14 =111, DQ15 =111
3017 23:11:18.155788
3018 23:11:18.156246
3019 23:11:18.156672 ==
3020 23:11:18.158283 Dram Type= 6, Freq= 0, CH_0, rank 1
3021 23:11:18.161459 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3022 23:11:18.161950 ==
3023 23:11:18.162401
3024 23:11:18.162825
3025 23:11:18.164632 TX Vref Scan disable
3026 23:11:18.168075 == TX Byte 0 ==
3027 23:11:18.171535 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
3028 23:11:18.175123 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
3029 23:11:18.178076 == TX Byte 1 ==
3030 23:11:18.181631 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3031 23:11:18.184754 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3032 23:11:18.185173 ==
3033 23:11:18.188237 Dram Type= 6, Freq= 0, CH_0, rank 1
3034 23:11:18.191317 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3035 23:11:18.191774 ==
3036 23:11:18.204438 TX Vref=22, minBit 1, minWin=25, winSum=425
3037 23:11:18.207699 TX Vref=24, minBit 1, minWin=26, winSum=431
3038 23:11:18.211126 TX Vref=26, minBit 10, minWin=26, winSum=438
3039 23:11:18.214486 TX Vref=28, minBit 1, minWin=26, winSum=441
3040 23:11:18.218112 TX Vref=30, minBit 1, minWin=27, winSum=442
3041 23:11:18.225122 TX Vref=32, minBit 2, minWin=27, winSum=442
3042 23:11:18.228244 [TxChooseVref] Worse bit 1, Min win 27, Win sum 442, Final Vref 30
3043 23:11:18.228765
3044 23:11:18.231086 Final TX Range 1 Vref 30
3045 23:11:18.231505
3046 23:11:18.231837 ==
3047 23:11:18.235126 Dram Type= 6, Freq= 0, CH_0, rank 1
3048 23:11:18.237986 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3049 23:11:18.238428 ==
3050 23:11:18.238766
3051 23:11:18.241249
3052 23:11:18.241809 TX Vref Scan disable
3053 23:11:18.244959 == TX Byte 0 ==
3054 23:11:18.248127 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
3055 23:11:18.251337 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
3056 23:11:18.255036 == TX Byte 1 ==
3057 23:11:18.258015 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3058 23:11:18.261348 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3059 23:11:18.261904
3060 23:11:18.264884 [DATLAT]
3061 23:11:18.265397 Freq=1200, CH0 RK1
3062 23:11:18.265786
3063 23:11:18.268400 DATLAT Default: 0xd
3064 23:11:18.268914 0, 0xFFFF, sum = 0
3065 23:11:18.271491 1, 0xFFFF, sum = 0
3066 23:11:18.272021 2, 0xFFFF, sum = 0
3067 23:11:18.274341 3, 0xFFFF, sum = 0
3068 23:11:18.274886 4, 0xFFFF, sum = 0
3069 23:11:18.277946 5, 0xFFFF, sum = 0
3070 23:11:18.278479 6, 0xFFFF, sum = 0
3071 23:11:18.281124 7, 0xFFFF, sum = 0
3072 23:11:18.284661 8, 0xFFFF, sum = 0
3073 23:11:18.285184 9, 0xFFFF, sum = 0
3074 23:11:18.287862 10, 0xFFFF, sum = 0
3075 23:11:18.288424 11, 0xFFFF, sum = 0
3076 23:11:18.291131 12, 0x0, sum = 1
3077 23:11:18.291657 13, 0x0, sum = 2
3078 23:11:18.294676 14, 0x0, sum = 3
3079 23:11:18.295207 15, 0x0, sum = 4
3080 23:11:18.295553 best_step = 13
3081 23:11:18.295866
3082 23:11:18.297564 ==
3083 23:11:18.301075 Dram Type= 6, Freq= 0, CH_0, rank 1
3084 23:11:18.304380 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3085 23:11:18.304904 ==
3086 23:11:18.305248 RX Vref Scan: 0
3087 23:11:18.305662
3088 23:11:18.307612 RX Vref 0 -> 0, step: 1
3089 23:11:18.308066
3090 23:11:18.311037 RX Delay -37 -> 252, step: 4
3091 23:11:18.314038 iDelay=195, Bit 0, Center 108 (39 ~ 178) 140
3092 23:11:18.320965 iDelay=195, Bit 1, Center 110 (39 ~ 182) 144
3093 23:11:18.324297 iDelay=195, Bit 2, Center 108 (39 ~ 178) 140
3094 23:11:18.327460 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3095 23:11:18.331017 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3096 23:11:18.334249 iDelay=195, Bit 5, Center 100 (35 ~ 166) 132
3097 23:11:18.341049 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3098 23:11:18.344170 iDelay=195, Bit 7, Center 120 (47 ~ 194) 148
3099 23:11:18.347521 iDelay=195, Bit 8, Center 88 (19 ~ 158) 140
3100 23:11:18.351243 iDelay=195, Bit 9, Center 80 (11 ~ 150) 140
3101 23:11:18.354132 iDelay=195, Bit 10, Center 100 (31 ~ 170) 140
3102 23:11:18.358009 iDelay=195, Bit 11, Center 90 (23 ~ 158) 136
3103 23:11:18.364432 iDelay=195, Bit 12, Center 108 (39 ~ 178) 140
3104 23:11:18.367960 iDelay=195, Bit 13, Center 106 (35 ~ 178) 144
3105 23:11:18.370664 iDelay=195, Bit 14, Center 110 (43 ~ 178) 136
3106 23:11:18.374516 iDelay=195, Bit 15, Center 108 (39 ~ 178) 140
3107 23:11:18.375038 ==
3108 23:11:18.378156 Dram Type= 6, Freq= 0, CH_0, rank 1
3109 23:11:18.384571 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3110 23:11:18.385097 ==
3111 23:11:18.385438 DQS Delay:
3112 23:11:18.387822 DQS0 = 0, DQS1 = 0
3113 23:11:18.388341 DQM Delay:
3114 23:11:18.388702 DQM0 = 110, DQM1 = 98
3115 23:11:18.391080 DQ Delay:
3116 23:11:18.394345 DQ0 =108, DQ1 =110, DQ2 =108, DQ3 =108
3117 23:11:18.397636 DQ4 =112, DQ5 =100, DQ6 =120, DQ7 =120
3118 23:11:18.401087 DQ8 =88, DQ9 =80, DQ10 =100, DQ11 =90
3119 23:11:18.404212 DQ12 =108, DQ13 =106, DQ14 =110, DQ15 =108
3120 23:11:18.404767
3121 23:11:18.405121
3122 23:11:18.411392 [DQSOSCAuto] RK1, (LSB)MR18= 0x12fa, (MSB)MR19= 0x403, tDQSOscB0 = 412 ps tDQSOscB1 = 403 ps
3123 23:11:18.414216 CH0 RK1: MR19=403, MR18=12FA
3124 23:11:18.421112 CH0_RK1: MR19=0x403, MR18=0x12FA, DQSOSC=403, MR23=63, INC=40, DEC=26
3125 23:11:18.423968 [RxdqsGatingPostProcess] freq 1200
3126 23:11:18.431198 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3127 23:11:18.434119 best DQS0 dly(2T, 0.5T) = (0, 11)
3128 23:11:18.437436 best DQS1 dly(2T, 0.5T) = (0, 12)
3129 23:11:18.437903 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3130 23:11:18.440743 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3131 23:11:18.444362 best DQS0 dly(2T, 0.5T) = (0, 11)
3132 23:11:18.447535 best DQS1 dly(2T, 0.5T) = (0, 12)
3133 23:11:18.451297 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3134 23:11:18.454454 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3135 23:11:18.457879 Pre-setting of DQS Precalculation
3136 23:11:18.464841 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3137 23:11:18.465364 ==
3138 23:11:18.467873 Dram Type= 6, Freq= 0, CH_1, rank 0
3139 23:11:18.470837 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3140 23:11:18.471264 ==
3141 23:11:18.477585 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3142 23:11:18.480708 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3143 23:11:18.490898 [CA 0] Center 37 (7~67) winsize 61
3144 23:11:18.494110 [CA 1] Center 37 (7~68) winsize 62
3145 23:11:18.497247 [CA 2] Center 34 (4~64) winsize 61
3146 23:11:18.500769 [CA 3] Center 33 (3~64) winsize 62
3147 23:11:18.503665 [CA 4] Center 34 (4~64) winsize 61
3148 23:11:18.507143 [CA 5] Center 33 (3~63) winsize 61
3149 23:11:18.507595
3150 23:11:18.510264 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3151 23:11:18.510685
3152 23:11:18.513902 [CATrainingPosCal] consider 1 rank data
3153 23:11:18.517004 u2DelayCellTimex100 = 270/100 ps
3154 23:11:18.520779 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3155 23:11:18.523826 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3156 23:11:18.530536 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3157 23:11:18.533773 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3158 23:11:18.536889 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3159 23:11:18.540603 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3160 23:11:18.541121
3161 23:11:18.543619 CA PerBit enable=1, Macro0, CA PI delay=33
3162 23:11:18.544130
3163 23:11:18.547148 [CBTSetCACLKResult] CA Dly = 33
3164 23:11:18.547713 CS Dly: 6 (0~37)
3165 23:11:18.548380 ==
3166 23:11:18.550488 Dram Type= 6, Freq= 0, CH_1, rank 1
3167 23:11:18.557021 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3168 23:11:18.557446 ==
3169 23:11:18.560347 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3170 23:11:18.566865 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
3171 23:11:18.575863 [CA 0] Center 37 (7~67) winsize 61
3172 23:11:18.579423 [CA 1] Center 37 (7~68) winsize 62
3173 23:11:18.582593 [CA 2] Center 34 (4~65) winsize 62
3174 23:11:18.586128 [CA 3] Center 33 (3~64) winsize 62
3175 23:11:18.589226 [CA 4] Center 34 (4~64) winsize 61
3176 23:11:18.592405 [CA 5] Center 32 (2~63) winsize 62
3177 23:11:18.592892
3178 23:11:18.595817 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3179 23:11:18.596232
3180 23:11:18.599309 [CATrainingPosCal] consider 2 rank data
3181 23:11:18.602355 u2DelayCellTimex100 = 270/100 ps
3182 23:11:18.606390 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3183 23:11:18.609200 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3184 23:11:18.616173 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3185 23:11:18.619177 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3186 23:11:18.622434 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3187 23:11:18.626160 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3188 23:11:18.626668
3189 23:11:18.629670 CA PerBit enable=1, Macro0, CA PI delay=33
3190 23:11:18.630191
3191 23:11:18.632649 [CBTSetCACLKResult] CA Dly = 33
3192 23:11:18.633168 CS Dly: 7 (0~39)
3193 23:11:18.633554
3194 23:11:18.636266 ----->DramcWriteLeveling(PI) begin...
3195 23:11:18.639372 ==
3196 23:11:18.639889 Dram Type= 6, Freq= 0, CH_1, rank 0
3197 23:11:18.645864 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3198 23:11:18.646287 ==
3199 23:11:18.649382 Write leveling (Byte 0): 24 => 24
3200 23:11:18.652733 Write leveling (Byte 1): 28 => 28
3201 23:11:18.655828 DramcWriteLeveling(PI) end<-----
3202 23:11:18.656345
3203 23:11:18.656716 ==
3204 23:11:18.659464 Dram Type= 6, Freq= 0, CH_1, rank 0
3205 23:11:18.662441 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3206 23:11:18.662878 ==
3207 23:11:18.665894 [Gating] SW mode calibration
3208 23:11:18.672775 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3209 23:11:18.676316 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3210 23:11:18.682340 0 15 0 | B1->B0 | 3030 2d2d | 0 1 | (0 0) (0 0)
3211 23:11:18.686288 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3212 23:11:18.689822 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3213 23:11:18.696114 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3214 23:11:18.699267 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3215 23:11:18.702396 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3216 23:11:18.709138 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3217 23:11:18.712497 0 15 28 | B1->B0 | 2f2f 2e2e | 0 0 | (0 0) (0 0)
3218 23:11:18.715955 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3219 23:11:18.722607 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3220 23:11:18.726015 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3221 23:11:18.729151 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3222 23:11:18.735817 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3223 23:11:18.739199 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3224 23:11:18.742872 1 0 24 | B1->B0 | 2424 2423 | 0 1 | (0 0) (0 0)
3225 23:11:18.749238 1 0 28 | B1->B0 | 4343 4141 | 0 0 | (0 0) (0 0)
3226 23:11:18.752744 1 1 0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
3227 23:11:18.756048 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3228 23:11:18.762804 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3229 23:11:18.765842 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3230 23:11:18.769248 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3231 23:11:18.775943 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3232 23:11:18.779480 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3233 23:11:18.782543 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3234 23:11:18.785682 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3235 23:11:18.792813 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3236 23:11:18.796390 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3237 23:11:18.799577 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3238 23:11:18.805819 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3239 23:11:18.809247 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3240 23:11:18.812685 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3241 23:11:18.819041 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3242 23:11:18.822922 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3243 23:11:18.825712 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3244 23:11:18.832625 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3245 23:11:18.836109 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3246 23:11:18.839007 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3247 23:11:18.846210 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3248 23:11:18.849274 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3249 23:11:18.852653 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3250 23:11:18.859660 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3251 23:11:18.860180 Total UI for P1: 0, mck2ui 16
3252 23:11:18.865750 best dqsien dly found for B1: ( 1, 3, 28)
3253 23:11:18.869554 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3254 23:11:18.872587 Total UI for P1: 0, mck2ui 16
3255 23:11:18.875868 best dqsien dly found for B0: ( 1, 3, 30)
3256 23:11:18.879484 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
3257 23:11:18.882244 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3258 23:11:18.882665
3259 23:11:18.885725 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
3260 23:11:18.889069 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3261 23:11:18.892346 [Gating] SW calibration Done
3262 23:11:18.892867 ==
3263 23:11:18.895666 Dram Type= 6, Freq= 0, CH_1, rank 0
3264 23:11:18.899066 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3265 23:11:18.899595 ==
3266 23:11:18.902724 RX Vref Scan: 0
3267 23:11:18.903289
3268 23:11:18.905909 RX Vref 0 -> 0, step: 1
3269 23:11:18.906479
3270 23:11:18.906855 RX Delay -40 -> 252, step: 8
3271 23:11:18.912544 iDelay=200, Bit 0, Center 123 (48 ~ 199) 152
3272 23:11:18.915351 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3273 23:11:18.918921 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3274 23:11:18.922161 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3275 23:11:18.925441 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3276 23:11:18.932460 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3277 23:11:18.935795 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3278 23:11:18.939090 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3279 23:11:18.942318 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3280 23:11:18.946062 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3281 23:11:18.949196 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
3282 23:11:18.955516 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
3283 23:11:18.959573 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
3284 23:11:18.962685 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
3285 23:11:18.965937 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3286 23:11:18.972631 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3287 23:11:18.973157 ==
3288 23:11:18.975948 Dram Type= 6, Freq= 0, CH_1, rank 0
3289 23:11:18.979138 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3290 23:11:18.979674 ==
3291 23:11:18.980011 DQS Delay:
3292 23:11:18.982738 DQS0 = 0, DQS1 = 0
3293 23:11:18.983266 DQM Delay:
3294 23:11:18.985700 DQM0 = 115, DQM1 = 105
3295 23:11:18.986284 DQ Delay:
3296 23:11:18.988962 DQ0 =123, DQ1 =111, DQ2 =103, DQ3 =115
3297 23:11:18.992527 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =111
3298 23:11:18.995481 DQ8 =95, DQ9 =99, DQ10 =103, DQ11 =99
3299 23:11:18.999074 DQ12 =111, DQ13 =111, DQ14 =111, DQ15 =111
3300 23:11:18.999499
3301 23:11:18.999832
3302 23:11:19.000140 ==
3303 23:11:19.002263 Dram Type= 6, Freq= 0, CH_1, rank 0
3304 23:11:19.008658 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3305 23:11:19.009103 ==
3306 23:11:19.009592
3307 23:11:19.010013
3308 23:11:19.010425 TX Vref Scan disable
3309 23:11:19.012864 == TX Byte 0 ==
3310 23:11:19.015709 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3311 23:11:19.022650 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3312 23:11:19.023195 == TX Byte 1 ==
3313 23:11:19.025683 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3314 23:11:19.032454 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3315 23:11:19.032984 ==
3316 23:11:19.036240 Dram Type= 6, Freq= 0, CH_1, rank 0
3317 23:11:19.039204 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3318 23:11:19.039650 ==
3319 23:11:19.050557 TX Vref=22, minBit 10, minWin=24, winSum=406
3320 23:11:19.054304 TX Vref=24, minBit 8, minWin=24, winSum=410
3321 23:11:19.057353 TX Vref=26, minBit 8, minWin=25, winSum=418
3322 23:11:19.061076 TX Vref=28, minBit 3, minWin=25, winSum=421
3323 23:11:19.063716 TX Vref=30, minBit 9, minWin=24, winSum=421
3324 23:11:19.067786 TX Vref=32, minBit 9, minWin=25, winSum=417
3325 23:11:19.074197 [TxChooseVref] Worse bit 3, Min win 25, Win sum 421, Final Vref 28
3326 23:11:19.074747
3327 23:11:19.077223 Final TX Range 1 Vref 28
3328 23:11:19.077813
3329 23:11:19.078263 ==
3330 23:11:19.080895 Dram Type= 6, Freq= 0, CH_1, rank 0
3331 23:11:19.083965 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3332 23:11:19.084509 ==
3333 23:11:19.087310
3334 23:11:19.087851
3335 23:11:19.088300 TX Vref Scan disable
3336 23:11:19.090230 == TX Byte 0 ==
3337 23:11:19.093930 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3338 23:11:19.097421 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3339 23:11:19.100604 == TX Byte 1 ==
3340 23:11:19.103596 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3341 23:11:19.107223 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3342 23:11:19.110069
3343 23:11:19.110503 [DATLAT]
3344 23:11:19.110946 Freq=1200, CH1 RK0
3345 23:11:19.111364
3346 23:11:19.113552 DATLAT Default: 0xd
3347 23:11:19.113974 0, 0xFFFF, sum = 0
3348 23:11:19.116451 1, 0xFFFF, sum = 0
3349 23:11:19.119929 2, 0xFFFF, sum = 0
3350 23:11:19.120386 3, 0xFFFF, sum = 0
3351 23:11:19.123488 4, 0xFFFF, sum = 0
3352 23:11:19.123917 5, 0xFFFF, sum = 0
3353 23:11:19.126688 6, 0xFFFF, sum = 0
3354 23:11:19.127116 7, 0xFFFF, sum = 0
3355 23:11:19.130272 8, 0xFFFF, sum = 0
3356 23:11:19.130701 9, 0xFFFF, sum = 0
3357 23:11:19.133355 10, 0xFFFF, sum = 0
3358 23:11:19.133836 11, 0xFFFF, sum = 0
3359 23:11:19.136566 12, 0x0, sum = 1
3360 23:11:19.136989 13, 0x0, sum = 2
3361 23:11:19.140303 14, 0x0, sum = 3
3362 23:11:19.140724 15, 0x0, sum = 4
3363 23:11:19.141060 best_step = 13
3364 23:11:19.143490
3365 23:11:19.143905 ==
3366 23:11:19.147192 Dram Type= 6, Freq= 0, CH_1, rank 0
3367 23:11:19.149859 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3368 23:11:19.150283 ==
3369 23:11:19.150614 RX Vref Scan: 1
3370 23:11:19.150920
3371 23:11:19.153369 Set Vref Range= 32 -> 127
3372 23:11:19.153820
3373 23:11:19.157241 RX Vref 32 -> 127, step: 1
3374 23:11:19.157723
3375 23:11:19.160480 RX Delay -21 -> 252, step: 4
3376 23:11:19.160995
3377 23:11:19.163547 Set Vref, RX VrefLevel [Byte0]: 32
3378 23:11:19.166611 [Byte1]: 32
3379 23:11:19.167028
3380 23:11:19.170209 Set Vref, RX VrefLevel [Byte0]: 33
3381 23:11:19.173520 [Byte1]: 33
3382 23:11:19.176975
3383 23:11:19.177389 Set Vref, RX VrefLevel [Byte0]: 34
3384 23:11:19.180185 [Byte1]: 34
3385 23:11:19.184626
3386 23:11:19.185042 Set Vref, RX VrefLevel [Byte0]: 35
3387 23:11:19.187755 [Byte1]: 35
3388 23:11:19.192470
3389 23:11:19.192985 Set Vref, RX VrefLevel [Byte0]: 36
3390 23:11:19.195758 [Byte1]: 36
3391 23:11:19.200808
3392 23:11:19.201328 Set Vref, RX VrefLevel [Byte0]: 37
3393 23:11:19.204023 [Byte1]: 37
3394 23:11:19.208522
3395 23:11:19.209047 Set Vref, RX VrefLevel [Byte0]: 38
3396 23:11:19.211866 [Byte1]: 38
3397 23:11:19.216211
3398 23:11:19.216631 Set Vref, RX VrefLevel [Byte0]: 39
3399 23:11:19.219888 [Byte1]: 39
3400 23:11:19.224546
3401 23:11:19.225073 Set Vref, RX VrefLevel [Byte0]: 40
3402 23:11:19.227715 [Byte1]: 40
3403 23:11:19.232255
3404 23:11:19.232681 Set Vref, RX VrefLevel [Byte0]: 41
3405 23:11:19.235321 [Byte1]: 41
3406 23:11:19.240258
3407 23:11:19.240783 Set Vref, RX VrefLevel [Byte0]: 42
3408 23:11:19.243515 [Byte1]: 42
3409 23:11:19.247944
3410 23:11:19.248470 Set Vref, RX VrefLevel [Byte0]: 43
3411 23:11:19.251230 [Byte1]: 43
3412 23:11:19.255850
3413 23:11:19.256368 Set Vref, RX VrefLevel [Byte0]: 44
3414 23:11:19.259498 [Byte1]: 44
3415 23:11:19.264319
3416 23:11:19.264841 Set Vref, RX VrefLevel [Byte0]: 45
3417 23:11:19.267306 [Byte1]: 45
3418 23:11:19.272150
3419 23:11:19.272682 Set Vref, RX VrefLevel [Byte0]: 46
3420 23:11:19.274880 [Byte1]: 46
3421 23:11:19.279932
3422 23:11:19.280537 Set Vref, RX VrefLevel [Byte0]: 47
3423 23:11:19.283057 [Byte1]: 47
3424 23:11:19.287851
3425 23:11:19.288372 Set Vref, RX VrefLevel [Byte0]: 48
3426 23:11:19.290898 [Byte1]: 48
3427 23:11:19.295590
3428 23:11:19.296112 Set Vref, RX VrefLevel [Byte0]: 49
3429 23:11:19.298873 [Byte1]: 49
3430 23:11:19.303695
3431 23:11:19.304210 Set Vref, RX VrefLevel [Byte0]: 50
3432 23:11:19.306806 [Byte1]: 50
3433 23:11:19.311414
3434 23:11:19.311835 Set Vref, RX VrefLevel [Byte0]: 51
3435 23:11:19.314556 [Byte1]: 51
3436 23:11:19.319126
3437 23:11:19.319541 Set Vref, RX VrefLevel [Byte0]: 52
3438 23:11:19.322715 [Byte1]: 52
3439 23:11:19.327129
3440 23:11:19.327659 Set Vref, RX VrefLevel [Byte0]: 53
3441 23:11:19.330505 [Byte1]: 53
3442 23:11:19.335358
3443 23:11:19.335883 Set Vref, RX VrefLevel [Byte0]: 54
3444 23:11:19.338869 [Byte1]: 54
3445 23:11:19.343128
3446 23:11:19.343694 Set Vref, RX VrefLevel [Byte0]: 55
3447 23:11:19.346311 [Byte1]: 55
3448 23:11:19.351222
3449 23:11:19.351762 Set Vref, RX VrefLevel [Byte0]: 56
3450 23:11:19.354059 [Byte1]: 56
3451 23:11:19.358830
3452 23:11:19.359354 Set Vref, RX VrefLevel [Byte0]: 57
3453 23:11:19.362416 [Byte1]: 57
3454 23:11:19.366710
3455 23:11:19.367233 Set Vref, RX VrefLevel [Byte0]: 58
3456 23:11:19.370404 [Byte1]: 58
3457 23:11:19.374858
3458 23:11:19.375380 Set Vref, RX VrefLevel [Byte0]: 59
3459 23:11:19.378084 [Byte1]: 59
3460 23:11:19.382659
3461 23:11:19.383177 Set Vref, RX VrefLevel [Byte0]: 60
3462 23:11:19.386231 [Byte1]: 60
3463 23:11:19.390717
3464 23:11:19.391231 Set Vref, RX VrefLevel [Byte0]: 61
3465 23:11:19.393869 [Byte1]: 61
3466 23:11:19.398321
3467 23:11:19.398874 Set Vref, RX VrefLevel [Byte0]: 62
3468 23:11:19.401726 [Byte1]: 62
3469 23:11:19.406348
3470 23:11:19.406871 Set Vref, RX VrefLevel [Byte0]: 63
3471 23:11:19.409687 [Byte1]: 63
3472 23:11:19.414435
3473 23:11:19.414958 Set Vref, RX VrefLevel [Byte0]: 64
3474 23:11:19.418108 [Byte1]: 64
3475 23:11:19.422162
3476 23:11:19.422684 Set Vref, RX VrefLevel [Byte0]: 65
3477 23:11:19.425656 [Byte1]: 65
3478 23:11:19.430198
3479 23:11:19.430741 Set Vref, RX VrefLevel [Byte0]: 66
3480 23:11:19.433735 [Byte1]: 66
3481 23:11:19.438403
3482 23:11:19.438977 Set Vref, RX VrefLevel [Byte0]: 67
3483 23:11:19.441582 [Byte1]: 67
3484 23:11:19.446197
3485 23:11:19.446659 Set Vref, RX VrefLevel [Byte0]: 68
3486 23:11:19.449586 [Byte1]: 68
3487 23:11:19.453927
3488 23:11:19.454341 Set Vref, RX VrefLevel [Byte0]: 69
3489 23:11:19.457143 [Byte1]: 69
3490 23:11:19.461645
3491 23:11:19.462166 Set Vref, RX VrefLevel [Byte0]: 70
3492 23:11:19.465322 [Byte1]: 70
3493 23:11:19.469502
3494 23:11:19.470097 Final RX Vref Byte 0 = 50 to rank0
3495 23:11:19.473422 Final RX Vref Byte 1 = 53 to rank0
3496 23:11:19.476542 Final RX Vref Byte 0 = 50 to rank1
3497 23:11:19.479711 Final RX Vref Byte 1 = 53 to rank1==
3498 23:11:19.482910 Dram Type= 6, Freq= 0, CH_1, rank 0
3499 23:11:19.489866 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3500 23:11:19.490415 ==
3501 23:11:19.490869 DQS Delay:
3502 23:11:19.491292 DQS0 = 0, DQS1 = 0
3503 23:11:19.492842 DQM Delay:
3504 23:11:19.493295 DQM0 = 112, DQM1 = 105
3505 23:11:19.496645 DQ Delay:
3506 23:11:19.500084 DQ0 =118, DQ1 =106, DQ2 =102, DQ3 =110
3507 23:11:19.502809 DQ4 =110, DQ5 =120, DQ6 =126, DQ7 =108
3508 23:11:19.506203 DQ8 =92, DQ9 =100, DQ10 =104, DQ11 =100
3509 23:11:19.509827 DQ12 =112, DQ13 =112, DQ14 =114, DQ15 =112
3510 23:11:19.510388
3511 23:11:19.510837
3512 23:11:19.519698 [DQSOSCAuto] RK0, (LSB)MR18= 0xedf4, (MSB)MR19= 0x303, tDQSOscB0 = 415 ps tDQSOscB1 = 417 ps
3513 23:11:19.520243 CH1 RK0: MR19=303, MR18=EDF4
3514 23:11:19.525907 CH1_RK0: MR19=0x303, MR18=0xEDF4, DQSOSC=415, MR23=63, INC=38, DEC=25
3515 23:11:19.526347
3516 23:11:19.529448 ----->DramcWriteLeveling(PI) begin...
3517 23:11:19.529921 ==
3518 23:11:19.532649 Dram Type= 6, Freq= 0, CH_1, rank 1
3519 23:11:19.539433 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3520 23:11:19.539976 ==
3521 23:11:19.542623 Write leveling (Byte 0): 25 => 25
3522 23:11:19.543059 Write leveling (Byte 1): 28 => 28
3523 23:11:19.545746 DramcWriteLeveling(PI) end<-----
3524 23:11:19.546181
3525 23:11:19.546620 ==
3526 23:11:19.549379 Dram Type= 6, Freq= 0, CH_1, rank 1
3527 23:11:19.556122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3528 23:11:19.556653 ==
3529 23:11:19.559518 [Gating] SW mode calibration
3530 23:11:19.566060 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3531 23:11:19.569357 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3532 23:11:19.576147 0 15 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3533 23:11:19.579952 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3534 23:11:19.582992 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3535 23:11:19.589553 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3536 23:11:19.593029 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3537 23:11:19.596131 0 15 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
3538 23:11:19.599333 0 15 24 | B1->B0 | 3232 2828 | 1 0 | (1 0) (0 0)
3539 23:11:19.605891 0 15 28 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
3540 23:11:19.609785 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3541 23:11:19.612969 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3542 23:11:19.619411 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3543 23:11:19.622375 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3544 23:11:19.625781 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3545 23:11:19.632386 1 0 20 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
3546 23:11:19.635893 1 0 24 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
3547 23:11:19.639786 1 0 28 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
3548 23:11:19.645851 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3549 23:11:19.649256 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3550 23:11:19.652399 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3551 23:11:19.659337 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3552 23:11:19.662373 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3553 23:11:19.665866 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3554 23:11:19.672604 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3555 23:11:19.676203 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3556 23:11:19.679826 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3557 23:11:19.686341 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3558 23:11:19.689390 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3559 23:11:19.692612 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3560 23:11:19.699281 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3561 23:11:19.702879 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3562 23:11:19.705895 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3563 23:11:19.712404 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3564 23:11:19.715504 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3565 23:11:19.718979 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3566 23:11:19.725376 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3567 23:11:19.729110 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3568 23:11:19.732475 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3569 23:11:19.738931 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3570 23:11:19.742168 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3571 23:11:19.745698 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3572 23:11:19.748529 Total UI for P1: 0, mck2ui 16
3573 23:11:19.752485 best dqsien dly found for B0: ( 1, 3, 22)
3574 23:11:19.755317 Total UI for P1: 0, mck2ui 16
3575 23:11:19.759192 best dqsien dly found for B1: ( 1, 3, 24)
3576 23:11:19.762242 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3577 23:11:19.765309 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3578 23:11:19.765781
3579 23:11:19.769079 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3580 23:11:19.775581 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3581 23:11:19.776102 [Gating] SW calibration Done
3582 23:11:19.776448 ==
3583 23:11:19.779443 Dram Type= 6, Freq= 0, CH_1, rank 1
3584 23:11:19.785289 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3585 23:11:19.785773 ==
3586 23:11:19.786113 RX Vref Scan: 0
3587 23:11:19.786428
3588 23:11:19.788668 RX Vref 0 -> 0, step: 1
3589 23:11:19.789187
3590 23:11:19.792090 RX Delay -40 -> 252, step: 8
3591 23:11:19.795083 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3592 23:11:19.798831 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3593 23:11:19.802270 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3594 23:11:19.808828 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
3595 23:11:19.811463 iDelay=200, Bit 4, Center 107 (32 ~ 183) 152
3596 23:11:19.815141 iDelay=200, Bit 5, Center 119 (40 ~ 199) 160
3597 23:11:19.818655 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
3598 23:11:19.821960 iDelay=200, Bit 7, Center 107 (32 ~ 183) 152
3599 23:11:19.825162 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3600 23:11:19.832011 iDelay=200, Bit 9, Center 99 (24 ~ 175) 152
3601 23:11:19.834956 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3602 23:11:19.838352 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3603 23:11:19.841692 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3604 23:11:19.848657 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3605 23:11:19.851527 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3606 23:11:19.855513 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
3607 23:11:19.856046 ==
3608 23:11:19.858061 Dram Type= 6, Freq= 0, CH_1, rank 1
3609 23:11:19.861469 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3610 23:11:19.861939 ==
3611 23:11:19.864485 DQS Delay:
3612 23:11:19.864902 DQS0 = 0, DQS1 = 0
3613 23:11:19.868233 DQM Delay:
3614 23:11:19.868657 DQM0 = 110, DQM1 = 109
3615 23:11:19.868992 DQ Delay:
3616 23:11:19.871509 DQ0 =115, DQ1 =107, DQ2 =99, DQ3 =107
3617 23:11:19.874882 DQ4 =107, DQ5 =119, DQ6 =119, DQ7 =107
3618 23:11:19.881364 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =103
3619 23:11:19.884498 DQ12 =119, DQ13 =119, DQ14 =111, DQ15 =115
3620 23:11:19.885029
3621 23:11:19.885366
3622 23:11:19.885743 ==
3623 23:11:19.888235 Dram Type= 6, Freq= 0, CH_1, rank 1
3624 23:11:19.891392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3625 23:11:19.891825 ==
3626 23:11:19.892158
3627 23:11:19.892465
3628 23:11:19.894665 TX Vref Scan disable
3629 23:11:19.898287 == TX Byte 0 ==
3630 23:11:19.900887 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3631 23:11:19.904847 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3632 23:11:19.908042 == TX Byte 1 ==
3633 23:11:19.910865 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3634 23:11:19.914373 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3635 23:11:19.914900 ==
3636 23:11:19.917635 Dram Type= 6, Freq= 0, CH_1, rank 1
3637 23:11:19.921180 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3638 23:11:19.924501 ==
3639 23:11:19.934198 TX Vref=22, minBit 10, minWin=25, winSum=424
3640 23:11:19.938031 TX Vref=24, minBit 9, minWin=25, winSum=428
3641 23:11:19.941691 TX Vref=26, minBit 8, minWin=26, winSum=434
3642 23:11:19.944267 TX Vref=28, minBit 3, minWin=26, winSum=434
3643 23:11:19.947773 TX Vref=30, minBit 8, minWin=26, winSum=434
3644 23:11:19.954097 TX Vref=32, minBit 8, minWin=25, winSum=432
3645 23:11:19.957794 [TxChooseVref] Worse bit 8, Min win 26, Win sum 434, Final Vref 26
3646 23:11:19.958217
3647 23:11:19.960826 Final TX Range 1 Vref 26
3648 23:11:19.961249
3649 23:11:19.961616 ==
3650 23:11:19.964530 Dram Type= 6, Freq= 0, CH_1, rank 1
3651 23:11:19.967494 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3652 23:11:19.970986 ==
3653 23:11:19.971515
3654 23:11:19.971850
3655 23:11:19.972158 TX Vref Scan disable
3656 23:11:19.974372 == TX Byte 0 ==
3657 23:11:19.977649 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3658 23:11:19.981328 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3659 23:11:19.984215 == TX Byte 1 ==
3660 23:11:19.987959 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3661 23:11:19.990805 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3662 23:11:19.994428
3663 23:11:19.995015 [DATLAT]
3664 23:11:19.995401 Freq=1200, CH1 RK1
3665 23:11:19.995750
3666 23:11:19.997642 DATLAT Default: 0xd
3667 23:11:19.998111 0, 0xFFFF, sum = 0
3668 23:11:20.000767 1, 0xFFFF, sum = 0
3669 23:11:20.001161 2, 0xFFFF, sum = 0
3670 23:11:20.004158 3, 0xFFFF, sum = 0
3671 23:11:20.007699 4, 0xFFFF, sum = 0
3672 23:11:20.008225 5, 0xFFFF, sum = 0
3673 23:11:20.011047 6, 0xFFFF, sum = 0
3674 23:11:20.011503 7, 0xFFFF, sum = 0
3675 23:11:20.014130 8, 0xFFFF, sum = 0
3676 23:11:20.014558 9, 0xFFFF, sum = 0
3677 23:11:20.017302 10, 0xFFFF, sum = 0
3678 23:11:20.017757 11, 0xFFFF, sum = 0
3679 23:11:20.020660 12, 0x0, sum = 1
3680 23:11:20.021194 13, 0x0, sum = 2
3681 23:11:20.024162 14, 0x0, sum = 3
3682 23:11:20.024682 15, 0x0, sum = 4
3683 23:11:20.025025 best_step = 13
3684 23:11:20.027333
3685 23:11:20.027751 ==
3686 23:11:20.030473 Dram Type= 6, Freq= 0, CH_1, rank 1
3687 23:11:20.034215 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3688 23:11:20.034662 ==
3689 23:11:20.035053 RX Vref Scan: 0
3690 23:11:20.035371
3691 23:11:20.037201 RX Vref 0 -> 0, step: 1
3692 23:11:20.037657
3693 23:11:20.040993 RX Delay -21 -> 252, step: 4
3694 23:11:20.043661 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3695 23:11:20.050201 iDelay=195, Bit 1, Center 108 (39 ~ 178) 140
3696 23:11:20.053875 iDelay=195, Bit 2, Center 98 (27 ~ 170) 144
3697 23:11:20.057038 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3698 23:11:20.060592 iDelay=195, Bit 4, Center 106 (35 ~ 178) 144
3699 23:11:20.063794 iDelay=195, Bit 5, Center 120 (51 ~ 190) 140
3700 23:11:20.070266 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3701 23:11:20.073552 iDelay=195, Bit 7, Center 108 (39 ~ 178) 140
3702 23:11:20.077026 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3703 23:11:20.080398 iDelay=195, Bit 9, Center 100 (35 ~ 166) 132
3704 23:11:20.083600 iDelay=195, Bit 10, Center 114 (51 ~ 178) 128
3705 23:11:20.090333 iDelay=195, Bit 11, Center 102 (35 ~ 170) 136
3706 23:11:20.093702 iDelay=195, Bit 12, Center 118 (55 ~ 182) 128
3707 23:11:20.097077 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3708 23:11:20.100316 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3709 23:11:20.107040 iDelay=195, Bit 15, Center 118 (55 ~ 182) 128
3710 23:11:20.107603 ==
3711 23:11:20.109868 Dram Type= 6, Freq= 0, CH_1, rank 1
3712 23:11:20.113207 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3713 23:11:20.113725 ==
3714 23:11:20.114137 DQS Delay:
3715 23:11:20.116591 DQS0 = 0, DQS1 = 0
3716 23:11:20.117057 DQM Delay:
3717 23:11:20.119863 DQM0 = 110, DQM1 = 110
3718 23:11:20.120284 DQ Delay:
3719 23:11:20.123921 DQ0 =114, DQ1 =108, DQ2 =98, DQ3 =108
3720 23:11:20.126333 DQ4 =106, DQ5 =120, DQ6 =122, DQ7 =108
3721 23:11:20.130038 DQ8 =98, DQ9 =100, DQ10 =114, DQ11 =102
3722 23:11:20.133453 DQ12 =118, DQ13 =118, DQ14 =118, DQ15 =118
3723 23:11:20.133907
3724 23:11:20.134242
3725 23:11:20.143012 [DQSOSCAuto] RK1, (LSB)MR18= 0xfb0b, (MSB)MR19= 0x304, tDQSOscB0 = 405 ps tDQSOscB1 = 412 ps
3726 23:11:20.146505 CH1 RK1: MR19=304, MR18=FB0B
3727 23:11:20.149896 CH1_RK1: MR19=0x304, MR18=0xFB0B, DQSOSC=405, MR23=63, INC=39, DEC=26
3728 23:11:20.153071 [RxdqsGatingPostProcess] freq 1200
3729 23:11:20.159722 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3730 23:11:20.163279 best DQS0 dly(2T, 0.5T) = (0, 11)
3731 23:11:20.166714 best DQS1 dly(2T, 0.5T) = (0, 11)
3732 23:11:20.170016 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3733 23:11:20.172849 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3734 23:11:20.176271 best DQS0 dly(2T, 0.5T) = (0, 11)
3735 23:11:20.179673 best DQS1 dly(2T, 0.5T) = (0, 11)
3736 23:11:20.182800 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3737 23:11:20.186368 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3738 23:11:20.189726 Pre-setting of DQS Precalculation
3739 23:11:20.192890 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3740 23:11:20.199726 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3741 23:11:20.206324 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3742 23:11:20.209253
3743 23:11:20.209711
3744 23:11:20.210063 [Calibration Summary] 2400 Mbps
3745 23:11:20.212583 CH 0, Rank 0
3746 23:11:20.213016 SW Impedance : PASS
3747 23:11:20.216140 DUTY Scan : NO K
3748 23:11:20.219648 ZQ Calibration : PASS
3749 23:11:20.220184 Jitter Meter : NO K
3750 23:11:20.222850 CBT Training : PASS
3751 23:11:20.225812 Write leveling : PASS
3752 23:11:20.226250 RX DQS gating : PASS
3753 23:11:20.229975 RX DQ/DQS(RDDQC) : PASS
3754 23:11:20.232752 TX DQ/DQS : PASS
3755 23:11:20.233194 RX DATLAT : PASS
3756 23:11:20.236048 RX DQ/DQS(Engine): PASS
3757 23:11:20.239357 TX OE : NO K
3758 23:11:20.239897 All Pass.
3759 23:11:20.240350
3760 23:11:20.240773 CH 0, Rank 1
3761 23:11:20.242342 SW Impedance : PASS
3762 23:11:20.245954 DUTY Scan : NO K
3763 23:11:20.246389 ZQ Calibration : PASS
3764 23:11:20.249187 Jitter Meter : NO K
3765 23:11:20.252740 CBT Training : PASS
3766 23:11:20.253278 Write leveling : PASS
3767 23:11:20.255843 RX DQS gating : PASS
3768 23:11:20.256277 RX DQ/DQS(RDDQC) : PASS
3769 23:11:20.259384 TX DQ/DQS : PASS
3770 23:11:20.262449 RX DATLAT : PASS
3771 23:11:20.262887 RX DQ/DQS(Engine): PASS
3772 23:11:20.266127 TX OE : NO K
3773 23:11:20.266670 All Pass.
3774 23:11:20.267120
3775 23:11:20.269211 CH 1, Rank 0
3776 23:11:20.269870 SW Impedance : PASS
3777 23:11:20.272650 DUTY Scan : NO K
3778 23:11:20.276056 ZQ Calibration : PASS
3779 23:11:20.276585 Jitter Meter : NO K
3780 23:11:20.279223 CBT Training : PASS
3781 23:11:20.282208 Write leveling : PASS
3782 23:11:20.282632 RX DQS gating : PASS
3783 23:11:20.285619 RX DQ/DQS(RDDQC) : PASS
3784 23:11:20.289366 TX DQ/DQS : PASS
3785 23:11:20.289960 RX DATLAT : PASS
3786 23:11:20.292792 RX DQ/DQS(Engine): PASS
3787 23:11:20.295528 TX OE : NO K
3788 23:11:20.295955 All Pass.
3789 23:11:20.296291
3790 23:11:20.296604 CH 1, Rank 1
3791 23:11:20.298966 SW Impedance : PASS
3792 23:11:20.302426 DUTY Scan : NO K
3793 23:11:20.302948 ZQ Calibration : PASS
3794 23:11:20.305331 Jitter Meter : NO K
3795 23:11:20.309068 CBT Training : PASS
3796 23:11:20.309632 Write leveling : PASS
3797 23:11:20.312115 RX DQS gating : PASS
3798 23:11:20.312537 RX DQ/DQS(RDDQC) : PASS
3799 23:11:20.315351 TX DQ/DQS : PASS
3800 23:11:20.318684 RX DATLAT : PASS
3801 23:11:20.319107 RX DQ/DQS(Engine): PASS
3802 23:11:20.321832 TX OE : NO K
3803 23:11:20.322255 All Pass.
3804 23:11:20.322592
3805 23:11:20.325510 DramC Write-DBI off
3806 23:11:20.328931 PER_BANK_REFRESH: Hybrid Mode
3807 23:11:20.329352 TX_TRACKING: ON
3808 23:11:20.338546 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3809 23:11:20.341623 [FAST_K] Save calibration result to emmc
3810 23:11:20.345462 dramc_set_vcore_voltage set vcore to 650000
3811 23:11:20.348647 Read voltage for 600, 5
3812 23:11:20.349065 Vio18 = 0
3813 23:11:20.351772 Vcore = 650000
3814 23:11:20.352214 Vdram = 0
3815 23:11:20.352561 Vddq = 0
3816 23:11:20.352874 Vmddr = 0
3817 23:11:20.358168 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3818 23:11:20.364947 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3819 23:11:20.365371 MEM_TYPE=3, freq_sel=19
3820 23:11:20.368318 sv_algorithm_assistance_LP4_1600
3821 23:11:20.371874 ============ PULL DRAM RESETB DOWN ============
3822 23:11:20.378308 ========== PULL DRAM RESETB DOWN end =========
3823 23:11:20.381617 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3824 23:11:20.385024 ===================================
3825 23:11:20.388885 LPDDR4 DRAM CONFIGURATION
3826 23:11:20.391556 ===================================
3827 23:11:20.391982 EX_ROW_EN[0] = 0x0
3828 23:11:20.394674 EX_ROW_EN[1] = 0x0
3829 23:11:20.395179 LP4Y_EN = 0x0
3830 23:11:20.398464 WORK_FSP = 0x0
3831 23:11:20.398890 WL = 0x2
3832 23:11:20.401691 RL = 0x2
3833 23:11:20.402209 BL = 0x2
3834 23:11:20.405326 RPST = 0x0
3835 23:11:20.408146 RD_PRE = 0x0
3836 23:11:20.408513 WR_PRE = 0x1
3837 23:11:20.411850 WR_PST = 0x0
3838 23:11:20.412305 DBI_WR = 0x0
3839 23:11:20.414943 DBI_RD = 0x0
3840 23:11:20.415414 OTF = 0x1
3841 23:11:20.417947 ===================================
3842 23:11:20.421598 ===================================
3843 23:11:20.422024 ANA top config
3844 23:11:20.425193 ===================================
3845 23:11:20.428163 DLL_ASYNC_EN = 0
3846 23:11:20.431316 ALL_SLAVE_EN = 1
3847 23:11:20.434995 NEW_RANK_MODE = 1
3848 23:11:20.438357 DLL_IDLE_MODE = 1
3849 23:11:20.438782 LP45_APHY_COMB_EN = 1
3850 23:11:20.441362 TX_ODT_DIS = 1
3851 23:11:20.444902 NEW_8X_MODE = 1
3852 23:11:20.447632 ===================================
3853 23:11:20.451271 ===================================
3854 23:11:20.454686 data_rate = 1200
3855 23:11:20.457602 CKR = 1
3856 23:11:20.463216 DQ_P2S_RATIO = 8
3857 23:11:20.464272 ===================================
3858 23:11:20.464773 CA_P2S_RATIO = 8
3859 23:11:20.467641 DQ_CA_OPEN = 0
3860 23:11:20.471488 DQ_SEMI_OPEN = 0
3861 23:11:20.474605 CA_SEMI_OPEN = 0
3862 23:11:20.477660 CA_FULL_RATE = 0
3863 23:11:20.480784 DQ_CKDIV4_EN = 1
3864 23:11:20.481214 CA_CKDIV4_EN = 1
3865 23:11:20.484303 CA_PREDIV_EN = 0
3866 23:11:20.487329 PH8_DLY = 0
3867 23:11:20.490935 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3868 23:11:20.494339 DQ_AAMCK_DIV = 4
3869 23:11:20.497115 CA_AAMCK_DIV = 4
3870 23:11:20.497759 CA_ADMCK_DIV = 4
3871 23:11:20.500795 DQ_TRACK_CA_EN = 0
3872 23:11:20.503842 CA_PICK = 600
3873 23:11:20.507012 CA_MCKIO = 600
3874 23:11:20.510307 MCKIO_SEMI = 0
3875 23:11:20.513432 PLL_FREQ = 2288
3876 23:11:20.517352 DQ_UI_PI_RATIO = 32
3877 23:11:20.517697 CA_UI_PI_RATIO = 0
3878 23:11:20.520344 ===================================
3879 23:11:20.523402 ===================================
3880 23:11:20.526885 memory_type:LPDDR4
3881 23:11:20.530134 GP_NUM : 10
3882 23:11:20.530491 SRAM_EN : 1
3883 23:11:20.533376 MD32_EN : 0
3884 23:11:20.536978 ===================================
3885 23:11:20.540491 [ANA_INIT] >>>>>>>>>>>>>>
3886 23:11:20.543551 <<<<<< [CONFIGURE PHASE]: ANA_TX
3887 23:11:20.546768 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3888 23:11:20.550381 ===================================
3889 23:11:20.550633 data_rate = 1200,PCW = 0X5800
3890 23:11:20.553618 ===================================
3891 23:11:20.556545 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3892 23:11:20.563300 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3893 23:11:20.570200 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3894 23:11:20.573193 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3895 23:11:20.576834 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3896 23:11:20.580168 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3897 23:11:20.583648 [ANA_INIT] flow start
3898 23:11:20.584056 [ANA_INIT] PLL >>>>>>>>
3899 23:11:20.587214 [ANA_INIT] PLL <<<<<<<<
3900 23:11:20.590075 [ANA_INIT] MIDPI >>>>>>>>
3901 23:11:20.593526 [ANA_INIT] MIDPI <<<<<<<<
3902 23:11:20.593955 [ANA_INIT] DLL >>>>>>>>
3903 23:11:20.596807 [ANA_INIT] flow end
3904 23:11:20.600486 ============ LP4 DIFF to SE enter ============
3905 23:11:20.603648 ============ LP4 DIFF to SE exit ============
3906 23:11:20.607107 [ANA_INIT] <<<<<<<<<<<<<
3907 23:11:20.610140 [Flow] Enable top DCM control >>>>>
3908 23:11:20.613403 [Flow] Enable top DCM control <<<<<
3909 23:11:20.616635 Enable DLL master slave shuffle
3910 23:11:20.623404 ==============================================================
3911 23:11:20.623834 Gating Mode config
3912 23:11:20.630167 ==============================================================
3913 23:11:20.630597 Config description:
3914 23:11:20.639948 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3915 23:11:20.646424 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3916 23:11:20.653249 SELPH_MODE 0: By rank 1: By Phase
3917 23:11:20.656605 ==============================================================
3918 23:11:20.659839 GAT_TRACK_EN = 1
3919 23:11:20.663275 RX_GATING_MODE = 2
3920 23:11:20.666502 RX_GATING_TRACK_MODE = 2
3921 23:11:20.669645 SELPH_MODE = 1
3922 23:11:20.672973 PICG_EARLY_EN = 1
3923 23:11:20.676536 VALID_LAT_VALUE = 1
3924 23:11:20.683115 ==============================================================
3925 23:11:20.686053 Enter into Gating configuration >>>>
3926 23:11:20.689736 Exit from Gating configuration <<<<
3927 23:11:20.693118 Enter into DVFS_PRE_config >>>>>
3928 23:11:20.702842 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3929 23:11:20.706048 Exit from DVFS_PRE_config <<<<<
3930 23:11:20.709371 Enter into PICG configuration >>>>
3931 23:11:20.712677 Exit from PICG configuration <<<<
3932 23:11:20.716096 [RX_INPUT] configuration >>>>>
3933 23:11:20.716689 [RX_INPUT] configuration <<<<<
3934 23:11:20.722536 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3935 23:11:20.729272 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3936 23:11:20.732849 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3937 23:11:20.739495 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3938 23:11:20.746086 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3939 23:11:20.752518 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3940 23:11:20.755971 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3941 23:11:20.759125 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3942 23:11:20.765866 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3943 23:11:20.769185 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3944 23:11:20.772792 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3945 23:11:20.779247 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3946 23:11:20.782447 ===================================
3947 23:11:20.782980 LPDDR4 DRAM CONFIGURATION
3948 23:11:20.785860 ===================================
3949 23:11:20.789090 EX_ROW_EN[0] = 0x0
3950 23:11:20.789665 EX_ROW_EN[1] = 0x0
3951 23:11:20.792775 LP4Y_EN = 0x0
3952 23:11:20.793309 WORK_FSP = 0x0
3953 23:11:20.795726 WL = 0x2
3954 23:11:20.798799 RL = 0x2
3955 23:11:20.799228 BL = 0x2
3956 23:11:20.802487 RPST = 0x0
3957 23:11:20.803029 RD_PRE = 0x0
3958 23:11:20.805638 WR_PRE = 0x1
3959 23:11:20.806166 WR_PST = 0x0
3960 23:11:20.809560 DBI_WR = 0x0
3961 23:11:20.810092 DBI_RD = 0x0
3962 23:11:20.812193 OTF = 0x1
3963 23:11:20.815556 ===================================
3964 23:11:20.819049 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3965 23:11:20.822169 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3966 23:11:20.825692 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3967 23:11:20.828853 ===================================
3968 23:11:20.832252 LPDDR4 DRAM CONFIGURATION
3969 23:11:20.835399 ===================================
3970 23:11:20.838679 EX_ROW_EN[0] = 0x10
3971 23:11:20.839104 EX_ROW_EN[1] = 0x0
3972 23:11:20.842015 LP4Y_EN = 0x0
3973 23:11:20.842440 WORK_FSP = 0x0
3974 23:11:20.845558 WL = 0x2
3975 23:11:20.846090 RL = 0x2
3976 23:11:20.848508 BL = 0x2
3977 23:11:20.848934 RPST = 0x0
3978 23:11:20.851995 RD_PRE = 0x0
3979 23:11:20.855499 WR_PRE = 0x1
3980 23:11:20.856023 WR_PST = 0x0
3981 23:11:20.858430 DBI_WR = 0x0
3982 23:11:20.858850 DBI_RD = 0x0
3983 23:11:20.861662 OTF = 0x1
3984 23:11:20.865157 ===================================
3985 23:11:20.868873 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3986 23:11:20.874034 nWR fixed to 30
3987 23:11:20.877163 [ModeRegInit_LP4] CH0 RK0
3988 23:11:20.877735 [ModeRegInit_LP4] CH0 RK1
3989 23:11:20.880957 [ModeRegInit_LP4] CH1 RK0
3990 23:11:20.884197 [ModeRegInit_LP4] CH1 RK1
3991 23:11:20.884724 match AC timing 17
3992 23:11:20.890399 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3993 23:11:20.894062 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3994 23:11:20.897329 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3995 23:11:20.903882 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3996 23:11:20.907276 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3997 23:11:20.907799 ==
3998 23:11:20.910132 Dram Type= 6, Freq= 0, CH_0, rank 0
3999 23:11:20.913735 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4000 23:11:20.914159 ==
4001 23:11:20.920236 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4002 23:11:20.927124 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4003 23:11:20.930267 [CA 0] Center 37 (7~67) winsize 61
4004 23:11:20.933814 [CA 1] Center 37 (7~67) winsize 61
4005 23:11:20.937244 [CA 2] Center 35 (5~65) winsize 61
4006 23:11:20.940613 [CA 3] Center 35 (5~65) winsize 61
4007 23:11:20.943352 [CA 4] Center 34 (4~65) winsize 62
4008 23:11:20.947014 [CA 5] Center 34 (4~65) winsize 62
4009 23:11:20.947442
4010 23:11:20.950071 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4011 23:11:20.950496
4012 23:11:20.954009 [CATrainingPosCal] consider 1 rank data
4013 23:11:20.957016 u2DelayCellTimex100 = 270/100 ps
4014 23:11:20.960195 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
4015 23:11:20.963405 CA1 delay=37 (7~67),Diff = 3 PI (28 cell)
4016 23:11:20.966427 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
4017 23:11:20.970127 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
4018 23:11:20.973445 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4019 23:11:20.980545 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4020 23:11:20.981067
4021 23:11:20.983437 CA PerBit enable=1, Macro0, CA PI delay=34
4022 23:11:20.983969
4023 23:11:20.986976 [CBTSetCACLKResult] CA Dly = 34
4024 23:11:20.987499 CS Dly: 5 (0~36)
4025 23:11:20.987839 ==
4026 23:11:20.989933 Dram Type= 6, Freq= 0, CH_0, rank 1
4027 23:11:20.993419 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4028 23:11:20.997080 ==
4029 23:11:20.999874 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4030 23:11:21.006176 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4031 23:11:21.009857 [CA 0] Center 37 (7~67) winsize 61
4032 23:11:21.013158 [CA 1] Center 37 (7~67) winsize 61
4033 23:11:21.016798 [CA 2] Center 35 (5~65) winsize 61
4034 23:11:21.019546 [CA 3] Center 34 (4~65) winsize 62
4035 23:11:21.022779 [CA 4] Center 34 (4~65) winsize 62
4036 23:11:21.026104 [CA 5] Center 33 (3~64) winsize 62
4037 23:11:21.026525
4038 23:11:21.029645 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4039 23:11:21.030070
4040 23:11:21.033315 [CATrainingPosCal] consider 2 rank data
4041 23:11:21.036421 u2DelayCellTimex100 = 270/100 ps
4042 23:11:21.039653 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
4043 23:11:21.043679 CA1 delay=37 (7~67),Diff = 3 PI (28 cell)
4044 23:11:21.046400 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
4045 23:11:21.049918 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
4046 23:11:21.056990 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4047 23:11:21.059627 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4048 23:11:21.060053
4049 23:11:21.063019 CA PerBit enable=1, Macro0, CA PI delay=34
4050 23:11:21.063445
4051 23:11:21.066364 [CBTSetCACLKResult] CA Dly = 34
4052 23:11:21.066789 CS Dly: 5 (0~37)
4053 23:11:21.067130
4054 23:11:21.069825 ----->DramcWriteLeveling(PI) begin...
4055 23:11:21.070253 ==
4056 23:11:21.073125 Dram Type= 6, Freq= 0, CH_0, rank 0
4057 23:11:21.079710 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4058 23:11:21.080234 ==
4059 23:11:21.082931 Write leveling (Byte 0): 31 => 31
4060 23:11:21.086458 Write leveling (Byte 1): 31 => 31
4061 23:11:21.086983 DramcWriteLeveling(PI) end<-----
4062 23:11:21.089935
4063 23:11:21.090455 ==
4064 23:11:21.092934 Dram Type= 6, Freq= 0, CH_0, rank 0
4065 23:11:21.096313 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4066 23:11:21.096840 ==
4067 23:11:21.099533 [Gating] SW mode calibration
4068 23:11:21.106024 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4069 23:11:21.109305 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4070 23:11:21.116217 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4071 23:11:21.119190 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4072 23:11:21.122109 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4073 23:11:21.128852 0 9 12 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
4074 23:11:21.132530 0 9 16 | B1->B0 | 3030 2d2d | 0 0 | (0 1) (0 0)
4075 23:11:21.135657 0 9 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4076 23:11:21.142167 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4077 23:11:21.145597 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4078 23:11:21.149359 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4079 23:11:21.155665 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4080 23:11:21.158671 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4081 23:11:21.162396 0 10 12 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
4082 23:11:21.168464 0 10 16 | B1->B0 | 3232 3b3b | 0 0 | (0 0) (0 0)
4083 23:11:21.171907 0 10 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4084 23:11:21.175225 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4085 23:11:21.182061 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4086 23:11:21.185335 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4087 23:11:21.188276 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4088 23:11:21.195042 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4089 23:11:21.198252 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4090 23:11:21.201700 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4091 23:11:21.208565 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4092 23:11:21.211602 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4093 23:11:21.215319 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4094 23:11:21.221661 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4095 23:11:21.225363 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4096 23:11:21.228365 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4097 23:11:21.234811 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4098 23:11:21.237744 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4099 23:11:21.241166 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4100 23:11:21.247798 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4101 23:11:21.251031 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4102 23:11:21.254515 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4103 23:11:21.260805 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4104 23:11:21.264314 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4105 23:11:21.267456 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4106 23:11:21.273737 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4107 23:11:21.277157 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4108 23:11:21.280404 Total UI for P1: 0, mck2ui 16
4109 23:11:21.284031 best dqsien dly found for B0: ( 0, 13, 14)
4110 23:11:21.287510 Total UI for P1: 0, mck2ui 16
4111 23:11:21.290899 best dqsien dly found for B1: ( 0, 13, 18)
4112 23:11:21.294083 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4113 23:11:21.297223 best DQS1 dly(MCK, UI, PI) = (0, 13, 18)
4114 23:11:21.297320
4115 23:11:21.300439 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4116 23:11:21.304438 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)
4117 23:11:21.308027 [Gating] SW calibration Done
4118 23:11:21.308217 ==
4119 23:11:21.310627 Dram Type= 6, Freq= 0, CH_0, rank 0
4120 23:11:21.314051 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4121 23:11:21.317434 ==
4122 23:11:21.317668 RX Vref Scan: 0
4123 23:11:21.317790
4124 23:11:21.320874 RX Vref 0 -> 0, step: 1
4125 23:11:21.321033
4126 23:11:21.324276 RX Delay -230 -> 252, step: 16
4127 23:11:21.327462 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4128 23:11:21.330362 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4129 23:11:21.333832 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4130 23:11:21.340413 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4131 23:11:21.343962 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4132 23:11:21.346919 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4133 23:11:21.350584 iDelay=218, Bit 6, Center 41 (-134 ~ 217) 352
4134 23:11:21.354140 iDelay=218, Bit 7, Center 41 (-134 ~ 217) 352
4135 23:11:21.360705 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4136 23:11:21.363823 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4137 23:11:21.367530 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4138 23:11:21.370339 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4139 23:11:21.377104 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4140 23:11:21.379990 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4141 23:11:21.383541 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4142 23:11:21.386809 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4143 23:11:21.390128 ==
4144 23:11:21.393894 Dram Type= 6, Freq= 0, CH_0, rank 0
4145 23:11:21.396869 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4146 23:11:21.397404 ==
4147 23:11:21.397785 DQS Delay:
4148 23:11:21.399951 DQS0 = 0, DQS1 = 0
4149 23:11:21.400372 DQM Delay:
4150 23:11:21.403404 DQM0 = 34, DQM1 = 31
4151 23:11:21.403927 DQ Delay:
4152 23:11:21.406780 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
4153 23:11:21.410118 DQ4 =33, DQ5 =25, DQ6 =41, DQ7 =41
4154 23:11:21.413220 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =33
4155 23:11:21.416665 DQ12 =33, DQ13 =33, DQ14 =41, DQ15 =33
4156 23:11:21.417089
4157 23:11:21.417425
4158 23:11:21.417800 ==
4159 23:11:21.419790 Dram Type= 6, Freq= 0, CH_0, rank 0
4160 23:11:21.422533 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4161 23:11:21.422620 ==
4162 23:11:21.422689
4163 23:11:21.422751
4164 23:11:21.426192 TX Vref Scan disable
4165 23:11:21.429456 == TX Byte 0 ==
4166 23:11:21.432635 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4167 23:11:21.436337 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4168 23:11:21.439466 == TX Byte 1 ==
4169 23:11:21.442677 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4170 23:11:21.445792 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4171 23:11:21.445874 ==
4172 23:11:21.449594 Dram Type= 6, Freq= 0, CH_0, rank 0
4173 23:11:21.456146 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4174 23:11:21.456321 ==
4175 23:11:21.456406
4176 23:11:21.456482
4177 23:11:21.456553 TX Vref Scan disable
4178 23:11:21.460377 == TX Byte 0 ==
4179 23:11:21.464087 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4180 23:11:21.470020 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4181 23:11:21.470209 == TX Byte 1 ==
4182 23:11:21.473687 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4183 23:11:21.479930 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4184 23:11:21.480168
4185 23:11:21.480326 [DATLAT]
4186 23:11:21.480459 Freq=600, CH0 RK0
4187 23:11:21.480579
4188 23:11:21.483286 DATLAT Default: 0x9
4189 23:11:21.483440 0, 0xFFFF, sum = 0
4190 23:11:21.486596 1, 0xFFFF, sum = 0
4191 23:11:21.489855 2, 0xFFFF, sum = 0
4192 23:11:21.490060 3, 0xFFFF, sum = 0
4193 23:11:21.493425 4, 0xFFFF, sum = 0
4194 23:11:21.493799 5, 0xFFFF, sum = 0
4195 23:11:21.496371 6, 0xFFFF, sum = 0
4196 23:11:21.496627 7, 0xFFFF, sum = 0
4197 23:11:21.500102 8, 0x0, sum = 1
4198 23:11:21.500535 9, 0x0, sum = 2
4199 23:11:21.500943 10, 0x0, sum = 3
4200 23:11:21.503382 11, 0x0, sum = 4
4201 23:11:21.503809 best_step = 9
4202 23:11:21.504201
4203 23:11:21.504517 ==
4204 23:11:21.506962 Dram Type= 6, Freq= 0, CH_0, rank 0
4205 23:11:21.513926 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4206 23:11:21.514386 ==
4207 23:11:21.514723 RX Vref Scan: 1
4208 23:11:21.515038
4209 23:11:21.517137 RX Vref 0 -> 0, step: 1
4210 23:11:21.517706
4211 23:11:21.520142 RX Delay -195 -> 252, step: 8
4212 23:11:21.520565
4213 23:11:21.523424 Set Vref, RX VrefLevel [Byte0]: 62
4214 23:11:21.526894 [Byte1]: 47
4215 23:11:21.527411
4216 23:11:21.529810 Final RX Vref Byte 0 = 62 to rank0
4217 23:11:21.533638 Final RX Vref Byte 1 = 47 to rank0
4218 23:11:21.536874 Final RX Vref Byte 0 = 62 to rank1
4219 23:11:21.539897 Final RX Vref Byte 1 = 47 to rank1==
4220 23:11:21.543249 Dram Type= 6, Freq= 0, CH_0, rank 0
4221 23:11:21.546421 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4222 23:11:21.546936 ==
4223 23:11:21.549588 DQS Delay:
4224 23:11:21.550008 DQS0 = 0, DQS1 = 0
4225 23:11:21.553216 DQM Delay:
4226 23:11:21.553677 DQM0 = 34, DQM1 = 29
4227 23:11:21.554049 DQ Delay:
4228 23:11:21.556235 DQ0 =36, DQ1 =36, DQ2 =32, DQ3 =32
4229 23:11:21.560166 DQ4 =32, DQ5 =20, DQ6 =40, DQ7 =48
4230 23:11:21.563181 DQ8 =20, DQ9 =16, DQ10 =32, DQ11 =24
4231 23:11:21.566339 DQ12 =36, DQ13 =32, DQ14 =40, DQ15 =36
4232 23:11:21.566762
4233 23:11:21.567097
4234 23:11:21.576682 [DQSOSCAuto] RK0, (LSB)MR18= 0x3e3d, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 398 ps
4235 23:11:21.580279 CH0 RK0: MR19=808, MR18=3E3D
4236 23:11:21.586465 CH0_RK0: MR19=0x808, MR18=0x3E3D, DQSOSC=398, MR23=63, INC=165, DEC=110
4237 23:11:21.586987
4238 23:11:21.590295 ----->DramcWriteLeveling(PI) begin...
4239 23:11:21.590796 ==
4240 23:11:21.593528 Dram Type= 6, Freq= 0, CH_0, rank 1
4241 23:11:21.596707 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4242 23:11:21.597231 ==
4243 23:11:21.600066 Write leveling (Byte 0): 31 => 31
4244 23:11:21.603216 Write leveling (Byte 1): 31 => 31
4245 23:11:21.606408 DramcWriteLeveling(PI) end<-----
4246 23:11:21.606933
4247 23:11:21.607268 ==
4248 23:11:21.610144 Dram Type= 6, Freq= 0, CH_0, rank 1
4249 23:11:21.613323 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4250 23:11:21.613938 ==
4251 23:11:21.616247 [Gating] SW mode calibration
4252 23:11:21.622704 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4253 23:11:21.629721 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4254 23:11:21.632727 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4255 23:11:21.636671 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4256 23:11:21.642996 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4257 23:11:21.646316 0 9 12 | B1->B0 | 3434 3030 | 1 1 | (1 1) (0 1)
4258 23:11:21.649737 0 9 16 | B1->B0 | 2e2e 2323 | 1 0 | (0 0) (0 0)
4259 23:11:21.656446 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4260 23:11:21.659714 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4261 23:11:21.663106 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4262 23:11:21.669527 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4263 23:11:21.672838 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4264 23:11:21.676146 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4265 23:11:21.682930 0 10 12 | B1->B0 | 2828 3030 | 1 0 | (0 0) (1 1)
4266 23:11:21.685712 0 10 16 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
4267 23:11:21.689414 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4268 23:11:21.695970 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4269 23:11:21.699042 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4270 23:11:21.702365 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4271 23:11:21.709063 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4272 23:11:21.712334 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4273 23:11:21.715657 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4274 23:11:21.721946 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4275 23:11:21.725166 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4276 23:11:21.728603 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4277 23:11:21.735458 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4278 23:11:21.738409 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4279 23:11:21.742193 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4280 23:11:21.749129 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4281 23:11:21.752202 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4282 23:11:21.755233 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4283 23:11:21.761866 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4284 23:11:21.765266 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4285 23:11:21.769055 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4286 23:11:21.775411 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4287 23:11:21.778490 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4288 23:11:21.781746 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4289 23:11:21.788157 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4290 23:11:21.788593 Total UI for P1: 0, mck2ui 16
4291 23:11:21.791655 best dqsien dly found for B0: ( 0, 13, 10)
4292 23:11:21.798140 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4293 23:11:21.801651 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4294 23:11:21.805006 Total UI for P1: 0, mck2ui 16
4295 23:11:21.808322 best dqsien dly found for B1: ( 0, 13, 16)
4296 23:11:21.812016 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4297 23:11:21.814749 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4298 23:11:21.815219
4299 23:11:21.817970 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4300 23:11:21.824886 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4301 23:11:21.825424 [Gating] SW calibration Done
4302 23:11:21.825810 ==
4303 23:11:21.828551 Dram Type= 6, Freq= 0, CH_0, rank 1
4304 23:11:21.834941 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4305 23:11:21.835503 ==
4306 23:11:21.835850 RX Vref Scan: 0
4307 23:11:21.836166
4308 23:11:21.838229 RX Vref 0 -> 0, step: 1
4309 23:11:21.838656
4310 23:11:21.841768 RX Delay -230 -> 252, step: 16
4311 23:11:21.844780 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4312 23:11:21.848243 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4313 23:11:21.851429 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4314 23:11:21.857789 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4315 23:11:21.861272 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4316 23:11:21.864427 iDelay=218, Bit 5, Center 17 (-150 ~ 185) 336
4317 23:11:21.868319 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4318 23:11:21.874881 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4319 23:11:21.878032 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4320 23:11:21.881695 iDelay=218, Bit 9, Center 9 (-150 ~ 169) 320
4321 23:11:21.884873 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4322 23:11:21.891654 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4323 23:11:21.894559 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4324 23:11:21.898121 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4325 23:11:21.901328 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4326 23:11:21.908103 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4327 23:11:21.908635 ==
4328 23:11:21.911095 Dram Type= 6, Freq= 0, CH_0, rank 1
4329 23:11:21.914601 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4330 23:11:21.915275 ==
4331 23:11:21.915637 DQS Delay:
4332 23:11:21.917655 DQS0 = 0, DQS1 = 0
4333 23:11:21.918084 DQM Delay:
4334 23:11:21.920809 DQM0 = 35, DQM1 = 27
4335 23:11:21.921371 DQ Delay:
4336 23:11:21.924660 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
4337 23:11:21.927654 DQ4 =33, DQ5 =17, DQ6 =49, DQ7 =49
4338 23:11:21.930673 DQ8 =17, DQ9 =9, DQ10 =33, DQ11 =17
4339 23:11:21.934154 DQ12 =33, DQ13 =33, DQ14 =41, DQ15 =33
4340 23:11:21.934602
4341 23:11:21.934940
4342 23:11:21.935254 ==
4343 23:11:21.937597 Dram Type= 6, Freq= 0, CH_0, rank 1
4344 23:11:21.940769 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4345 23:11:21.941199 ==
4346 23:11:21.941570
4347 23:11:21.941889
4348 23:11:21.944070 TX Vref Scan disable
4349 23:11:21.947353 == TX Byte 0 ==
4350 23:11:21.950625 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4351 23:11:21.954032 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4352 23:11:21.957194 == TX Byte 1 ==
4353 23:11:21.961144 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4354 23:11:21.963824 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4355 23:11:21.964368 ==
4356 23:11:21.967314 Dram Type= 6, Freq= 0, CH_0, rank 1
4357 23:11:21.973823 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4358 23:11:21.974344 ==
4359 23:11:21.974691
4360 23:11:21.975005
4361 23:11:21.975304 TX Vref Scan disable
4362 23:11:21.978318 == TX Byte 0 ==
4363 23:11:21.981278 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4364 23:11:21.988008 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4365 23:11:21.988434 == TX Byte 1 ==
4366 23:11:21.991708 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4367 23:11:21.997898 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4368 23:11:21.998320
4369 23:11:21.998663 [DATLAT]
4370 23:11:21.999170 Freq=600, CH0 RK1
4371 23:11:21.999503
4372 23:11:22.001261 DATLAT Default: 0x9
4373 23:11:22.001657 0, 0xFFFF, sum = 0
4374 23:11:22.004874 1, 0xFFFF, sum = 0
4375 23:11:22.008220 2, 0xFFFF, sum = 0
4376 23:11:22.008640 3, 0xFFFF, sum = 0
4377 23:11:22.011495 4, 0xFFFF, sum = 0
4378 23:11:22.011903 5, 0xFFFF, sum = 0
4379 23:11:22.014706 6, 0xFFFF, sum = 0
4380 23:11:22.015184 7, 0xFFFF, sum = 0
4381 23:11:22.018191 8, 0x0, sum = 1
4382 23:11:22.018600 9, 0x0, sum = 2
4383 23:11:22.018845 10, 0x0, sum = 3
4384 23:11:22.021459 11, 0x0, sum = 4
4385 23:11:22.021905 best_step = 9
4386 23:11:22.022167
4387 23:11:22.022393 ==
4388 23:11:22.024772 Dram Type= 6, Freq= 0, CH_0, rank 1
4389 23:11:22.030860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4390 23:11:22.031258 ==
4391 23:11:22.031509 RX Vref Scan: 0
4392 23:11:22.031733
4393 23:11:22.034322 RX Vref 0 -> 0, step: 1
4394 23:11:22.034634
4395 23:11:22.037686 RX Delay -195 -> 252, step: 8
4396 23:11:22.040875 iDelay=205, Bit 0, Center 32 (-123 ~ 188) 312
4397 23:11:22.047765 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4398 23:11:22.051425 iDelay=205, Bit 2, Center 32 (-123 ~ 188) 312
4399 23:11:22.054188 iDelay=205, Bit 3, Center 28 (-131 ~ 188) 320
4400 23:11:22.058178 iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312
4401 23:11:22.064287 iDelay=205, Bit 5, Center 24 (-131 ~ 180) 312
4402 23:11:22.067981 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4403 23:11:22.070982 iDelay=205, Bit 7, Center 44 (-115 ~ 204) 320
4404 23:11:22.074015 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4405 23:11:22.078148 iDelay=205, Bit 9, Center 12 (-139 ~ 164) 304
4406 23:11:22.084324 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4407 23:11:22.087776 iDelay=205, Bit 11, Center 16 (-139 ~ 172) 312
4408 23:11:22.091336 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4409 23:11:22.094436 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4410 23:11:22.101248 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4411 23:11:22.104048 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4412 23:11:22.104572 ==
4413 23:11:22.107732 Dram Type= 6, Freq= 0, CH_0, rank 1
4414 23:11:22.111009 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4415 23:11:22.111539 ==
4416 23:11:22.114182 DQS Delay:
4417 23:11:22.114706 DQS0 = 0, DQS1 = 0
4418 23:11:22.117307 DQM Delay:
4419 23:11:22.117894 DQM0 = 34, DQM1 = 27
4420 23:11:22.118240 DQ Delay:
4421 23:11:22.121048 DQ0 =32, DQ1 =36, DQ2 =32, DQ3 =28
4422 23:11:22.124168 DQ4 =32, DQ5 =24, DQ6 =44, DQ7 =44
4423 23:11:22.127974 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =16
4424 23:11:22.130436 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4425 23:11:22.130862
4426 23:11:22.131196
4427 23:11:22.141174 [DQSOSCAuto] RK1, (LSB)MR18= 0x6d3b, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 389 ps
4428 23:11:22.143911 CH0 RK1: MR19=808, MR18=6D3B
4429 23:11:22.150908 CH0_RK1: MR19=0x808, MR18=0x6D3B, DQSOSC=389, MR23=63, INC=173, DEC=115
4430 23:11:22.151423 [RxdqsGatingPostProcess] freq 600
4431 23:11:22.157295 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4432 23:11:22.160834 Pre-setting of DQS Precalculation
4433 23:11:22.164021 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4434 23:11:22.164558 ==
4435 23:11:22.167369 Dram Type= 6, Freq= 0, CH_1, rank 0
4436 23:11:22.173694 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4437 23:11:22.174290 ==
4438 23:11:22.177592 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4439 23:11:22.183468 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4440 23:11:22.187092 [CA 0] Center 35 (5~66) winsize 62
4441 23:11:22.190614 [CA 1] Center 36 (6~66) winsize 61
4442 23:11:22.193688 [CA 2] Center 34 (4~65) winsize 62
4443 23:11:22.197333 [CA 3] Center 34 (4~65) winsize 62
4444 23:11:22.200616 [CA 4] Center 34 (4~65) winsize 62
4445 23:11:22.203913 [CA 5] Center 33 (3~64) winsize 62
4446 23:11:22.204349
4447 23:11:22.206874 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4448 23:11:22.207318
4449 23:11:22.210080 [CATrainingPosCal] consider 1 rank data
4450 23:11:22.213607 u2DelayCellTimex100 = 270/100 ps
4451 23:11:22.216890 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4452 23:11:22.223781 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4453 23:11:22.226857 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4454 23:11:22.229972 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4455 23:11:22.233583 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4456 23:11:22.236610 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4457 23:11:22.236796
4458 23:11:22.239709 CA PerBit enable=1, Macro0, CA PI delay=33
4459 23:11:22.239895
4460 23:11:22.242952 [CBTSetCACLKResult] CA Dly = 33
4461 23:11:22.246545 CS Dly: 5 (0~36)
4462 23:11:22.246679 ==
4463 23:11:22.249683 Dram Type= 6, Freq= 0, CH_1, rank 1
4464 23:11:22.253169 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4465 23:11:22.253287 ==
4466 23:11:22.256325 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4467 23:11:22.263158 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4468 23:11:22.266699 [CA 0] Center 36 (6~66) winsize 61
4469 23:11:22.270099 [CA 1] Center 36 (5~67) winsize 63
4470 23:11:22.273260 [CA 2] Center 34 (4~65) winsize 62
4471 23:11:22.276733 [CA 3] Center 34 (3~65) winsize 63
4472 23:11:22.280188 [CA 4] Center 34 (4~65) winsize 62
4473 23:11:22.283891 [CA 5] Center 33 (3~64) winsize 62
4474 23:11:22.283985
4475 23:11:22.286735 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4476 23:11:22.286823
4477 23:11:22.290092 [CATrainingPosCal] consider 2 rank data
4478 23:11:22.293758 u2DelayCellTimex100 = 270/100 ps
4479 23:11:22.296832 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4480 23:11:22.300087 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4481 23:11:22.306758 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4482 23:11:22.309896 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4483 23:11:22.313411 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4484 23:11:22.316650 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4485 23:11:22.316735
4486 23:11:22.319998 CA PerBit enable=1, Macro0, CA PI delay=33
4487 23:11:22.320081
4488 23:11:22.323408 [CBTSetCACLKResult] CA Dly = 33
4489 23:11:22.323504 CS Dly: 5 (0~37)
4490 23:11:22.326734
4491 23:11:22.329719 ----->DramcWriteLeveling(PI) begin...
4492 23:11:22.329809 ==
4493 23:11:22.333338 Dram Type= 6, Freq= 0, CH_1, rank 0
4494 23:11:22.336523 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4495 23:11:22.336616 ==
4496 23:11:22.339862 Write leveling (Byte 0): 29 => 29
4497 23:11:22.343410 Write leveling (Byte 1): 31 => 31
4498 23:11:22.346690 DramcWriteLeveling(PI) end<-----
4499 23:11:22.346779
4500 23:11:22.346865 ==
4501 23:11:22.349722 Dram Type= 6, Freq= 0, CH_1, rank 0
4502 23:11:22.352807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4503 23:11:22.352897 ==
4504 23:11:22.355983 [Gating] SW mode calibration
4505 23:11:22.362727 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4506 23:11:22.369525 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4507 23:11:22.373131 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4508 23:11:22.376342 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4509 23:11:22.382623 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4510 23:11:22.385990 0 9 12 | B1->B0 | 3232 3232 | 1 1 | (1 1) (1 1)
4511 23:11:22.389671 0 9 16 | B1->B0 | 2727 2626 | 1 1 | (0 0) (0 0)
4512 23:11:22.396084 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4513 23:11:22.399222 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4514 23:11:22.402682 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4515 23:11:22.409284 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4516 23:11:22.412859 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4517 23:11:22.415688 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4518 23:11:22.422362 0 10 12 | B1->B0 | 3030 2f2f | 0 0 | (0 0) (0 0)
4519 23:11:22.426035 0 10 16 | B1->B0 | 4040 4343 | 0 0 | (0 0) (0 0)
4520 23:11:22.428830 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4521 23:11:22.435760 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4522 23:11:22.439251 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4523 23:11:22.442301 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4524 23:11:22.449004 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4525 23:11:22.452412 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4526 23:11:22.456041 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4527 23:11:22.459489 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4528 23:11:22.466116 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4529 23:11:22.468766 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4530 23:11:22.475613 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4531 23:11:22.479274 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4532 23:11:22.482204 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4533 23:11:22.489161 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4534 23:11:22.492835 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4535 23:11:22.495863 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4536 23:11:22.499174 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4537 23:11:22.505571 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4538 23:11:22.509023 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4539 23:11:22.512751 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4540 23:11:22.519332 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4541 23:11:22.522169 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4542 23:11:22.525684 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4543 23:11:22.532434 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4544 23:11:22.535540 Total UI for P1: 0, mck2ui 16
4545 23:11:22.538727 best dqsien dly found for B0: ( 0, 13, 12)
4546 23:11:22.541957 Total UI for P1: 0, mck2ui 16
4547 23:11:22.545205 best dqsien dly found for B1: ( 0, 13, 12)
4548 23:11:22.548753 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4549 23:11:22.552258 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4550 23:11:22.552979
4551 23:11:22.555102 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4552 23:11:22.558933 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4553 23:11:22.562131 [Gating] SW calibration Done
4554 23:11:22.562661 ==
4555 23:11:22.565300 Dram Type= 6, Freq= 0, CH_1, rank 0
4556 23:11:22.568737 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4557 23:11:22.569175 ==
4558 23:11:22.571930 RX Vref Scan: 0
4559 23:11:22.572461
4560 23:11:22.575367 RX Vref 0 -> 0, step: 1
4561 23:11:22.575896
4562 23:11:22.576455 RX Delay -230 -> 252, step: 16
4563 23:11:22.581753 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4564 23:11:22.585470 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4565 23:11:22.588647 iDelay=218, Bit 2, Center 25 (-150 ~ 201) 352
4566 23:11:22.591944 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4567 23:11:22.598382 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4568 23:11:22.601888 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4569 23:11:22.605011 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4570 23:11:22.608324 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4571 23:11:22.611647 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4572 23:11:22.618167 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4573 23:11:22.621617 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4574 23:11:22.624780 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4575 23:11:22.628732 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4576 23:11:22.634893 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4577 23:11:22.637885 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4578 23:11:22.641258 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4579 23:11:22.641742 ==
4580 23:11:22.644905 Dram Type= 6, Freq= 0, CH_1, rank 0
4581 23:11:22.651497 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4582 23:11:22.651949 ==
4583 23:11:22.652386 DQS Delay:
4584 23:11:22.652918 DQS0 = 0, DQS1 = 0
4585 23:11:22.654455 DQM Delay:
4586 23:11:22.654888 DQM0 = 38, DQM1 = 28
4587 23:11:22.658250 DQ Delay:
4588 23:11:22.661323 DQ0 =49, DQ1 =33, DQ2 =25, DQ3 =33
4589 23:11:22.661794 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4590 23:11:22.664697 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4591 23:11:22.670960 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4592 23:11:22.671393
4593 23:11:22.671829
4594 23:11:22.672241 ==
4595 23:11:22.674694 Dram Type= 6, Freq= 0, CH_1, rank 0
4596 23:11:22.677716 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4597 23:11:22.678141 ==
4598 23:11:22.678478
4599 23:11:22.678788
4600 23:11:22.681223 TX Vref Scan disable
4601 23:11:22.681672 == TX Byte 0 ==
4602 23:11:22.688215 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4603 23:11:22.691359 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4604 23:11:22.691880 == TX Byte 1 ==
4605 23:11:22.697461 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4606 23:11:22.701041 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4607 23:11:22.701608 ==
4608 23:11:22.704175 Dram Type= 6, Freq= 0, CH_1, rank 0
4609 23:11:22.707618 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4610 23:11:22.708047 ==
4611 23:11:22.708382
4612 23:11:22.710795
4613 23:11:22.711216 TX Vref Scan disable
4614 23:11:22.714220 == TX Byte 0 ==
4615 23:11:22.717853 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4616 23:11:22.724467 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4617 23:11:22.724971 == TX Byte 1 ==
4618 23:11:22.727745 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4619 23:11:22.734733 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4620 23:11:22.735256
4621 23:11:22.735592 [DATLAT]
4622 23:11:22.735903 Freq=600, CH1 RK0
4623 23:11:22.736305
4624 23:11:22.737619 DATLAT Default: 0x9
4625 23:11:22.738043 0, 0xFFFF, sum = 0
4626 23:11:22.740553 1, 0xFFFF, sum = 0
4627 23:11:22.740989 2, 0xFFFF, sum = 0
4628 23:11:22.744285 3, 0xFFFF, sum = 0
4629 23:11:22.747336 4, 0xFFFF, sum = 0
4630 23:11:22.747773 5, 0xFFFF, sum = 0
4631 23:11:22.751297 6, 0xFFFF, sum = 0
4632 23:11:22.751841 7, 0xFFFF, sum = 0
4633 23:11:22.752292 8, 0x0, sum = 1
4634 23:11:22.753974 9, 0x0, sum = 2
4635 23:11:22.754413 10, 0x0, sum = 3
4636 23:11:22.757298 11, 0x0, sum = 4
4637 23:11:22.757783 best_step = 9
4638 23:11:22.758218
4639 23:11:22.758629 ==
4640 23:11:22.760776 Dram Type= 6, Freq= 0, CH_1, rank 0
4641 23:11:22.767628 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4642 23:11:22.768065 ==
4643 23:11:22.768510 RX Vref Scan: 1
4644 23:11:22.768929
4645 23:11:22.770726 RX Vref 0 -> 0, step: 1
4646 23:11:22.771158
4647 23:11:22.774007 RX Delay -195 -> 252, step: 8
4648 23:11:22.774441
4649 23:11:22.776963 Set Vref, RX VrefLevel [Byte0]: 50
4650 23:11:22.780451 [Byte1]: 53
4651 23:11:22.781002
4652 23:11:22.783667 Final RX Vref Byte 0 = 50 to rank0
4653 23:11:22.787284 Final RX Vref Byte 1 = 53 to rank0
4654 23:11:22.790432 Final RX Vref Byte 0 = 50 to rank1
4655 23:11:22.793739 Final RX Vref Byte 1 = 53 to rank1==
4656 23:11:22.796541 Dram Type= 6, Freq= 0, CH_1, rank 0
4657 23:11:22.800230 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4658 23:11:22.800314 ==
4659 23:11:22.803309 DQS Delay:
4660 23:11:22.803393 DQS0 = 0, DQS1 = 0
4661 23:11:22.806891 DQM Delay:
4662 23:11:22.806975 DQM0 = 37, DQM1 = 28
4663 23:11:22.807061 DQ Delay:
4664 23:11:22.809966 DQ0 =44, DQ1 =32, DQ2 =24, DQ3 =36
4665 23:11:22.813138 DQ4 =36, DQ5 =48, DQ6 =48, DQ7 =32
4666 23:11:22.816268 DQ8 =12, DQ9 =16, DQ10 =28, DQ11 =20
4667 23:11:22.819731 DQ12 =40, DQ13 =36, DQ14 =36, DQ15 =36
4668 23:11:22.819815
4669 23:11:22.819901
4670 23:11:22.829859 [DQSOSCAuto] RK0, (LSB)MR18= 0x2633, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 402 ps
4671 23:11:22.833260 CH1 RK0: MR19=808, MR18=2633
4672 23:11:22.839459 CH1_RK0: MR19=0x808, MR18=0x2633, DQSOSC=400, MR23=63, INC=163, DEC=109
4673 23:11:22.839545
4674 23:11:22.843152 ----->DramcWriteLeveling(PI) begin...
4675 23:11:22.843238 ==
4676 23:11:22.846220 Dram Type= 6, Freq= 0, CH_1, rank 1
4677 23:11:22.849658 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4678 23:11:22.849743 ==
4679 23:11:22.852905 Write leveling (Byte 0): 32 => 32
4680 23:11:22.856220 Write leveling (Byte 1): 32 => 32
4681 23:11:22.859647 DramcWriteLeveling(PI) end<-----
4682 23:11:22.859731
4683 23:11:22.859815 ==
4684 23:11:22.863225 Dram Type= 6, Freq= 0, CH_1, rank 1
4685 23:11:22.866233 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4686 23:11:22.866327 ==
4687 23:11:22.869291 [Gating] SW mode calibration
4688 23:11:22.876132 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4689 23:11:22.882761 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4690 23:11:22.886084 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4691 23:11:22.889095 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4692 23:11:22.895913 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4693 23:11:22.899007 0 9 12 | B1->B0 | 3131 2f2f | 1 1 | (0 0) (0 0)
4694 23:11:22.902683 0 9 16 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
4695 23:11:22.909319 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4696 23:11:22.912852 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4697 23:11:22.915946 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4698 23:11:22.922658 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4699 23:11:22.925801 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4700 23:11:22.929319 0 10 8 | B1->B0 | 2323 2d2c | 0 1 | (0 0) (0 0)
4701 23:11:22.936224 0 10 12 | B1->B0 | 3131 3b3b | 0 0 | (0 0) (0 0)
4702 23:11:22.939033 0 10 16 | B1->B0 | 4444 4646 | 1 0 | (0 0) (0 0)
4703 23:11:22.942719 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4704 23:11:22.949148 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4705 23:11:22.952726 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4706 23:11:22.955856 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4707 23:11:22.963140 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4708 23:11:22.965847 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4709 23:11:22.969544 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4710 23:11:22.972819 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4711 23:11:22.979576 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4712 23:11:22.983156 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4713 23:11:22.986048 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4714 23:11:22.992733 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4715 23:11:22.995644 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4716 23:11:22.999085 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4717 23:11:23.005938 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4718 23:11:23.009315 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4719 23:11:23.012473 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4720 23:11:23.019317 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4721 23:11:23.022230 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4722 23:11:23.026076 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4723 23:11:23.032972 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4724 23:11:23.036377 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4725 23:11:23.039336 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4726 23:11:23.042968 Total UI for P1: 0, mck2ui 16
4727 23:11:23.046260 best dqsien dly found for B0: ( 0, 13, 10)
4728 23:11:23.052696 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4729 23:11:23.053175 Total UI for P1: 0, mck2ui 16
4730 23:11:23.059403 best dqsien dly found for B1: ( 0, 13, 12)
4731 23:11:23.062842 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4732 23:11:23.065818 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4733 23:11:23.066313
4734 23:11:23.069395 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4735 23:11:23.072356 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4736 23:11:23.076061 [Gating] SW calibration Done
4737 23:11:23.076487 ==
4738 23:11:23.078959 Dram Type= 6, Freq= 0, CH_1, rank 1
4739 23:11:23.082476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4740 23:11:23.082913 ==
4741 23:11:23.085667 RX Vref Scan: 0
4742 23:11:23.086143
4743 23:11:23.086502 RX Vref 0 -> 0, step: 1
4744 23:11:23.086842
4745 23:11:23.089295 RX Delay -230 -> 252, step: 16
4746 23:11:23.095276 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4747 23:11:23.098849 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4748 23:11:23.102000 iDelay=218, Bit 2, Center 17 (-150 ~ 185) 336
4749 23:11:23.105395 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4750 23:11:23.111986 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4751 23:11:23.114918 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4752 23:11:23.118214 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4753 23:11:23.121834 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4754 23:11:23.124894 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4755 23:11:23.131561 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4756 23:11:23.134832 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4757 23:11:23.138457 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4758 23:11:23.141409 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4759 23:11:23.147961 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4760 23:11:23.151767 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4761 23:11:23.154766 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4762 23:11:23.155010 ==
4763 23:11:23.158011 Dram Type= 6, Freq= 0, CH_1, rank 1
4764 23:11:23.161424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4765 23:11:23.164827 ==
4766 23:11:23.165242 DQS Delay:
4767 23:11:23.165612 DQS0 = 0, DQS1 = 0
4768 23:11:23.168377 DQM Delay:
4769 23:11:23.168789 DQM0 = 36, DQM1 = 29
4770 23:11:23.171348 DQ Delay:
4771 23:11:23.171803 DQ0 =41, DQ1 =33, DQ2 =17, DQ3 =33
4772 23:11:23.175022 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4773 23:11:23.178094 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4774 23:11:23.181632 DQ12 =33, DQ13 =41, DQ14 =33, DQ15 =33
4775 23:11:23.184641
4776 23:11:23.185088
4777 23:11:23.185421 ==
4778 23:11:23.188020 Dram Type= 6, Freq= 0, CH_1, rank 1
4779 23:11:23.191345 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4780 23:11:23.191771 ==
4781 23:11:23.192107
4782 23:11:23.192416
4783 23:11:23.194888 TX Vref Scan disable
4784 23:11:23.195319 == TX Byte 0 ==
4785 23:11:23.201301 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4786 23:11:23.204626 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4787 23:11:23.204949 == TX Byte 1 ==
4788 23:11:23.211069 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4789 23:11:23.214089 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4790 23:11:23.214274 ==
4791 23:11:23.217616 Dram Type= 6, Freq= 0, CH_1, rank 1
4792 23:11:23.220854 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4793 23:11:23.221010 ==
4794 23:11:23.221144
4795 23:11:23.221259
4796 23:11:23.223939 TX Vref Scan disable
4797 23:11:23.227644 == TX Byte 0 ==
4798 23:11:23.230794 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4799 23:11:23.234425 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4800 23:11:23.237713 == TX Byte 1 ==
4801 23:11:23.240635 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4802 23:11:23.243691 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4803 23:11:23.247304
4804 23:11:23.247391 [DATLAT]
4805 23:11:23.247459 Freq=600, CH1 RK1
4806 23:11:23.247523
4807 23:11:23.250520 DATLAT Default: 0x9
4808 23:11:23.250603 0, 0xFFFF, sum = 0
4809 23:11:23.253741 1, 0xFFFF, sum = 0
4810 23:11:23.253849 2, 0xFFFF, sum = 0
4811 23:11:23.257201 3, 0xFFFF, sum = 0
4812 23:11:23.257286 4, 0xFFFF, sum = 0
4813 23:11:23.260727 5, 0xFFFF, sum = 0
4814 23:11:23.263750 6, 0xFFFF, sum = 0
4815 23:11:23.263883 7, 0xFFFF, sum = 0
4816 23:11:23.264002 8, 0x0, sum = 1
4817 23:11:23.266868 9, 0x0, sum = 2
4818 23:11:23.267000 10, 0x0, sum = 3
4819 23:11:23.270557 11, 0x0, sum = 4
4820 23:11:23.270664 best_step = 9
4821 23:11:23.270754
4822 23:11:23.270842 ==
4823 23:11:23.273672 Dram Type= 6, Freq= 0, CH_1, rank 1
4824 23:11:23.280353 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4825 23:11:23.280456 ==
4826 23:11:23.280547 RX Vref Scan: 0
4827 23:11:23.280638
4828 23:11:23.283807 RX Vref 0 -> 0, step: 1
4829 23:11:23.283901
4830 23:11:23.287245 RX Delay -195 -> 252, step: 8
4831 23:11:23.290239 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4832 23:11:23.297050 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4833 23:11:23.300151 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4834 23:11:23.303805 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4835 23:11:23.306937 iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312
4836 23:11:23.313705 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4837 23:11:23.317025 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4838 23:11:23.320026 iDelay=205, Bit 7, Center 28 (-131 ~ 188) 320
4839 23:11:23.323647 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4840 23:11:23.327042 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4841 23:11:23.333220 iDelay=205, Bit 10, Center 32 (-131 ~ 196) 328
4842 23:11:23.336867 iDelay=205, Bit 11, Center 24 (-139 ~ 188) 328
4843 23:11:23.340024 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4844 23:11:23.343907 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4845 23:11:23.350003 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4846 23:11:23.353162 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4847 23:11:23.353303 ==
4848 23:11:23.357191 Dram Type= 6, Freq= 0, CH_1, rank 1
4849 23:11:23.360210 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4850 23:11:23.360398 ==
4851 23:11:23.363369 DQS Delay:
4852 23:11:23.363548 DQS0 = 0, DQS1 = 0
4853 23:11:23.363680 DQM Delay:
4854 23:11:23.366495 DQM0 = 35, DQM1 = 30
4855 23:11:23.366672 DQ Delay:
4856 23:11:23.369977 DQ0 =40, DQ1 =32, DQ2 =24, DQ3 =32
4857 23:11:23.373252 DQ4 =32, DQ5 =48, DQ6 =48, DQ7 =28
4858 23:11:23.377011 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =24
4859 23:11:23.379980 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4860 23:11:23.380202
4861 23:11:23.380372
4862 23:11:23.390390 [DQSOSCAuto] RK1, (LSB)MR18= 0x3455, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 400 ps
4863 23:11:23.393421 CH1 RK1: MR19=808, MR18=3455
4864 23:11:23.396862 CH1_RK1: MR19=0x808, MR18=0x3455, DQSOSC=393, MR23=63, INC=169, DEC=113
4865 23:11:23.400566 [RxdqsGatingPostProcess] freq 600
4866 23:11:23.407069 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4867 23:11:23.410058 Pre-setting of DQS Precalculation
4868 23:11:23.413183 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4869 23:11:23.423186 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4870 23:11:23.430113 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4871 23:11:23.430534
4872 23:11:23.430863
4873 23:11:23.433357 [Calibration Summary] 1200 Mbps
4874 23:11:23.433797 CH 0, Rank 0
4875 23:11:23.436725 SW Impedance : PASS
4876 23:11:23.437243 DUTY Scan : NO K
4877 23:11:23.439961 ZQ Calibration : PASS
4878 23:11:23.443768 Jitter Meter : NO K
4879 23:11:23.444299 CBT Training : PASS
4880 23:11:23.446762 Write leveling : PASS
4881 23:11:23.449843 RX DQS gating : PASS
4882 23:11:23.450260 RX DQ/DQS(RDDQC) : PASS
4883 23:11:23.453298 TX DQ/DQS : PASS
4884 23:11:23.456766 RX DATLAT : PASS
4885 23:11:23.457285 RX DQ/DQS(Engine): PASS
4886 23:11:23.459650 TX OE : NO K
4887 23:11:23.460084 All Pass.
4888 23:11:23.460445
4889 23:11:23.463831 CH 0, Rank 1
4890 23:11:23.464357 SW Impedance : PASS
4891 23:11:23.466258 DUTY Scan : NO K
4892 23:11:23.466726 ZQ Calibration : PASS
4893 23:11:23.470032 Jitter Meter : NO K
4894 23:11:23.473032 CBT Training : PASS
4895 23:11:23.473451 Write leveling : PASS
4896 23:11:23.477020 RX DQS gating : PASS
4897 23:11:23.479858 RX DQ/DQS(RDDQC) : PASS
4898 23:11:23.480278 TX DQ/DQS : PASS
4899 23:11:23.483291 RX DATLAT : PASS
4900 23:11:23.486696 RX DQ/DQS(Engine): PASS
4901 23:11:23.487218 TX OE : NO K
4902 23:11:23.489889 All Pass.
4903 23:11:23.490403
4904 23:11:23.490737 CH 1, Rank 0
4905 23:11:23.493605 SW Impedance : PASS
4906 23:11:23.494122 DUTY Scan : NO K
4907 23:11:23.496422 ZQ Calibration : PASS
4908 23:11:23.499707 Jitter Meter : NO K
4909 23:11:23.500227 CBT Training : PASS
4910 23:11:23.502943 Write leveling : PASS
4911 23:11:23.506215 RX DQS gating : PASS
4912 23:11:23.506635 RX DQ/DQS(RDDQC) : PASS
4913 23:11:23.509629 TX DQ/DQS : PASS
4914 23:11:23.510159 RX DATLAT : PASS
4915 23:11:23.513395 RX DQ/DQS(Engine): PASS
4916 23:11:23.516902 TX OE : NO K
4917 23:11:23.517371 All Pass.
4918 23:11:23.517786
4919 23:11:23.518099 CH 1, Rank 1
4920 23:11:23.520095 SW Impedance : PASS
4921 23:11:23.523027 DUTY Scan : NO K
4922 23:11:23.523448 ZQ Calibration : PASS
4923 23:11:23.526675 Jitter Meter : NO K
4924 23:11:23.529699 CBT Training : PASS
4925 23:11:23.530118 Write leveling : PASS
4926 23:11:23.533423 RX DQS gating : PASS
4927 23:11:23.536736 RX DQ/DQS(RDDQC) : PASS
4928 23:11:23.537259 TX DQ/DQS : PASS
4929 23:11:23.540031 RX DATLAT : PASS
4930 23:11:23.542817 RX DQ/DQS(Engine): PASS
4931 23:11:23.543237 TX OE : NO K
4932 23:11:23.543573 All Pass.
4933 23:11:23.546328
4934 23:11:23.546850 DramC Write-DBI off
4935 23:11:23.549979 PER_BANK_REFRESH: Hybrid Mode
4936 23:11:23.550398 TX_TRACKING: ON
4937 23:11:23.560178 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4938 23:11:23.563406 [FAST_K] Save calibration result to emmc
4939 23:11:23.566239 dramc_set_vcore_voltage set vcore to 662500
4940 23:11:23.569819 Read voltage for 933, 3
4941 23:11:23.570343 Vio18 = 0
4942 23:11:23.572873 Vcore = 662500
4943 23:11:23.573397 Vdram = 0
4944 23:11:23.573799 Vddq = 0
4945 23:11:23.574111 Vmddr = 0
4946 23:11:23.579555 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4947 23:11:23.586412 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4948 23:11:23.586940 MEM_TYPE=3, freq_sel=17
4949 23:11:23.589650 sv_algorithm_assistance_LP4_1600
4950 23:11:23.593180 ============ PULL DRAM RESETB DOWN ============
4951 23:11:23.599772 ========== PULL DRAM RESETB DOWN end =========
4952 23:11:23.602981 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4953 23:11:23.606178 ===================================
4954 23:11:23.609549 LPDDR4 DRAM CONFIGURATION
4955 23:11:23.612852 ===================================
4956 23:11:23.613372 EX_ROW_EN[0] = 0x0
4957 23:11:23.616175 EX_ROW_EN[1] = 0x0
4958 23:11:23.616590 LP4Y_EN = 0x0
4959 23:11:23.619298 WORK_FSP = 0x0
4960 23:11:23.622452 WL = 0x3
4961 23:11:23.623032 RL = 0x3
4962 23:11:23.625708 BL = 0x2
4963 23:11:23.626254 RPST = 0x0
4964 23:11:23.628960 RD_PRE = 0x0
4965 23:11:23.629374 WR_PRE = 0x1
4966 23:11:23.632405 WR_PST = 0x0
4967 23:11:23.632821 DBI_WR = 0x0
4968 23:11:23.635834 DBI_RD = 0x0
4969 23:11:23.636252 OTF = 0x1
4970 23:11:23.639172 ===================================
4971 23:11:23.642453 ===================================
4972 23:11:23.645742 ANA top config
4973 23:11:23.648855 ===================================
4974 23:11:23.649274 DLL_ASYNC_EN = 0
4975 23:11:23.652373 ALL_SLAVE_EN = 1
4976 23:11:23.656011 NEW_RANK_MODE = 1
4977 23:11:23.659210 DLL_IDLE_MODE = 1
4978 23:11:23.659737 LP45_APHY_COMB_EN = 1
4979 23:11:23.662133 TX_ODT_DIS = 1
4980 23:11:23.666243 NEW_8X_MODE = 1
4981 23:11:23.669283 ===================================
4982 23:11:23.672490 ===================================
4983 23:11:23.675802 data_rate = 1866
4984 23:11:23.679016 CKR = 1
4985 23:11:23.682349 DQ_P2S_RATIO = 8
4986 23:11:23.685816 ===================================
4987 23:11:23.686340 CA_P2S_RATIO = 8
4988 23:11:23.689130 DQ_CA_OPEN = 0
4989 23:11:23.692218 DQ_SEMI_OPEN = 0
4990 23:11:23.695897 CA_SEMI_OPEN = 0
4991 23:11:23.698891 CA_FULL_RATE = 0
4992 23:11:23.702266 DQ_CKDIV4_EN = 1
4993 23:11:23.702729 CA_CKDIV4_EN = 1
4994 23:11:23.705386 CA_PREDIV_EN = 0
4995 23:11:23.708965 PH8_DLY = 0
4996 23:11:23.712289 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4997 23:11:23.715526 DQ_AAMCK_DIV = 4
4998 23:11:23.718908 CA_AAMCK_DIV = 4
4999 23:11:23.719388 CA_ADMCK_DIV = 4
5000 23:11:23.722301 DQ_TRACK_CA_EN = 0
5001 23:11:23.725352 CA_PICK = 933
5002 23:11:23.728586 CA_MCKIO = 933
5003 23:11:23.731885 MCKIO_SEMI = 0
5004 23:11:23.735353 PLL_FREQ = 3732
5005 23:11:23.738434 DQ_UI_PI_RATIO = 32
5006 23:11:23.738855 CA_UI_PI_RATIO = 0
5007 23:11:23.741612 ===================================
5008 23:11:23.745414 ===================================
5009 23:11:23.748405 memory_type:LPDDR4
5010 23:11:23.751700 GP_NUM : 10
5011 23:11:23.752173 SRAM_EN : 1
5012 23:11:23.754997 MD32_EN : 0
5013 23:11:23.758179 ===================================
5014 23:11:23.761617 [ANA_INIT] >>>>>>>>>>>>>>
5015 23:11:23.764682 <<<<<< [CONFIGURE PHASE]: ANA_TX
5016 23:11:23.768288 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5017 23:11:23.771526 ===================================
5018 23:11:23.771947 data_rate = 1866,PCW = 0X8f00
5019 23:11:23.774711 ===================================
5020 23:11:23.778175 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5021 23:11:23.784621 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5022 23:11:23.791260 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5023 23:11:23.794470 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5024 23:11:23.798057 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5025 23:11:23.801055 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5026 23:11:23.804596 [ANA_INIT] flow start
5027 23:11:23.807667 [ANA_INIT] PLL >>>>>>>>
5028 23:11:23.807819 [ANA_INIT] PLL <<<<<<<<
5029 23:11:23.811398 [ANA_INIT] MIDPI >>>>>>>>
5030 23:11:23.814204 [ANA_INIT] MIDPI <<<<<<<<
5031 23:11:23.814333 [ANA_INIT] DLL >>>>>>>>
5032 23:11:23.817905 [ANA_INIT] flow end
5033 23:11:23.820821 ============ LP4 DIFF to SE enter ============
5034 23:11:23.824406 ============ LP4 DIFF to SE exit ============
5035 23:11:23.827600 [ANA_INIT] <<<<<<<<<<<<<
5036 23:11:23.830843 [Flow] Enable top DCM control >>>>>
5037 23:11:23.833981 [Flow] Enable top DCM control <<<<<
5038 23:11:23.837498 Enable DLL master slave shuffle
5039 23:11:23.844359 ==============================================================
5040 23:11:23.844441 Gating Mode config
5041 23:11:23.850613 ==============================================================
5042 23:11:23.850700 Config description:
5043 23:11:23.860593 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5044 23:11:23.867214 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5045 23:11:23.873759 SELPH_MODE 0: By rank 1: By Phase
5046 23:11:23.876989 ==============================================================
5047 23:11:23.880509 GAT_TRACK_EN = 1
5048 23:11:23.883625 RX_GATING_MODE = 2
5049 23:11:23.887260 RX_GATING_TRACK_MODE = 2
5050 23:11:23.890306 SELPH_MODE = 1
5051 23:11:23.894046 PICG_EARLY_EN = 1
5052 23:11:23.896980 VALID_LAT_VALUE = 1
5053 23:11:23.903801 ==============================================================
5054 23:11:23.906871 Enter into Gating configuration >>>>
5055 23:11:23.910190 Exit from Gating configuration <<<<
5056 23:11:23.913315 Enter into DVFS_PRE_config >>>>>
5057 23:11:23.923110 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5058 23:11:23.926777 Exit from DVFS_PRE_config <<<<<
5059 23:11:23.930221 Enter into PICG configuration >>>>
5060 23:11:23.933322 Exit from PICG configuration <<<<
5061 23:11:23.936465 [RX_INPUT] configuration >>>>>
5062 23:11:23.939665 [RX_INPUT] configuration <<<<<
5063 23:11:23.943300 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5064 23:11:23.949716 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5065 23:11:23.956215 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5066 23:11:23.959439 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5067 23:11:23.966277 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5068 23:11:23.972908 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5069 23:11:23.976062 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5070 23:11:23.982562 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5071 23:11:23.985839 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5072 23:11:23.989919 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5073 23:11:23.992771 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5074 23:11:23.999305 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5075 23:11:24.002667 ===================================
5076 23:11:24.002753 LPDDR4 DRAM CONFIGURATION
5077 23:11:24.006022 ===================================
5078 23:11:24.009144 EX_ROW_EN[0] = 0x0
5079 23:11:24.012563 EX_ROW_EN[1] = 0x0
5080 23:11:24.012648 LP4Y_EN = 0x0
5081 23:11:24.015843 WORK_FSP = 0x0
5082 23:11:24.015927 WL = 0x3
5083 23:11:24.019071 RL = 0x3
5084 23:11:24.019158 BL = 0x2
5085 23:11:24.022225 RPST = 0x0
5086 23:11:24.022309 RD_PRE = 0x0
5087 23:11:24.025955 WR_PRE = 0x1
5088 23:11:24.026050 WR_PST = 0x0
5089 23:11:24.029204 DBI_WR = 0x0
5090 23:11:24.029287 DBI_RD = 0x0
5091 23:11:24.032511 OTF = 0x1
5092 23:11:24.035567 ===================================
5093 23:11:24.038786 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5094 23:11:24.042407 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5095 23:11:24.048683 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5096 23:11:24.051994 ===================================
5097 23:11:24.052081 LPDDR4 DRAM CONFIGURATION
5098 23:11:24.055297 ===================================
5099 23:11:24.058695 EX_ROW_EN[0] = 0x10
5100 23:11:24.062300 EX_ROW_EN[1] = 0x0
5101 23:11:24.062390 LP4Y_EN = 0x0
5102 23:11:24.065281 WORK_FSP = 0x0
5103 23:11:24.065363 WL = 0x3
5104 23:11:24.068723 RL = 0x3
5105 23:11:24.068805 BL = 0x2
5106 23:11:24.072300 RPST = 0x0
5107 23:11:24.072382 RD_PRE = 0x0
5108 23:11:24.075064 WR_PRE = 0x1
5109 23:11:24.075163 WR_PST = 0x0
5110 23:11:24.078726 DBI_WR = 0x0
5111 23:11:24.078834 DBI_RD = 0x0
5112 23:11:24.082057 OTF = 0x1
5113 23:11:24.085221 ===================================
5114 23:11:24.091984 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5115 23:11:24.095035 nWR fixed to 30
5116 23:11:24.098193 [ModeRegInit_LP4] CH0 RK0
5117 23:11:24.098301 [ModeRegInit_LP4] CH0 RK1
5118 23:11:24.101471 [ModeRegInit_LP4] CH1 RK0
5119 23:11:24.105082 [ModeRegInit_LP4] CH1 RK1
5120 23:11:24.105180 match AC timing 9
5121 23:11:24.111449 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5122 23:11:24.115204 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5123 23:11:24.117935 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5124 23:11:24.124560 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5125 23:11:24.128273 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5126 23:11:24.128384 ==
5127 23:11:24.131375 Dram Type= 6, Freq= 0, CH_0, rank 0
5128 23:11:24.134570 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5129 23:11:24.134660 ==
5130 23:11:24.141041 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5131 23:11:24.147967 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5132 23:11:24.151121 [CA 0] Center 38 (7~69) winsize 63
5133 23:11:24.154266 [CA 1] Center 38 (8~69) winsize 62
5134 23:11:24.158065 [CA 2] Center 35 (5~66) winsize 62
5135 23:11:24.161218 [CA 3] Center 35 (5~65) winsize 61
5136 23:11:24.164254 [CA 4] Center 34 (4~65) winsize 62
5137 23:11:24.167970 [CA 5] Center 34 (4~64) winsize 61
5138 23:11:24.168054
5139 23:11:24.171227 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5140 23:11:24.171313
5141 23:11:24.174629 [CATrainingPosCal] consider 1 rank data
5142 23:11:24.177504 u2DelayCellTimex100 = 270/100 ps
5143 23:11:24.181134 CA0 delay=38 (7~69),Diff = 4 PI (24 cell)
5144 23:11:24.184062 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5145 23:11:24.187949 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5146 23:11:24.190801 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5147 23:11:24.194430 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5148 23:11:24.200598 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5149 23:11:24.200682
5150 23:11:24.204240 CA PerBit enable=1, Macro0, CA PI delay=34
5151 23:11:24.204322
5152 23:11:24.207732 [CBTSetCACLKResult] CA Dly = 34
5153 23:11:24.207815 CS Dly: 7 (0~38)
5154 23:11:24.207881 ==
5155 23:11:24.210838 Dram Type= 6, Freq= 0, CH_0, rank 1
5156 23:11:24.213760 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5157 23:11:24.217332 ==
5158 23:11:24.220445 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5159 23:11:24.227307 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5160 23:11:24.230366 [CA 0] Center 38 (8~69) winsize 62
5161 23:11:24.233870 [CA 1] Center 38 (8~69) winsize 62
5162 23:11:24.237178 [CA 2] Center 35 (5~66) winsize 62
5163 23:11:24.240407 [CA 3] Center 35 (5~66) winsize 62
5164 23:11:24.243239 [CA 4] Center 34 (3~65) winsize 63
5165 23:11:24.247081 [CA 5] Center 33 (3~64) winsize 62
5166 23:11:24.247162
5167 23:11:24.249966 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5168 23:11:24.250052
5169 23:11:24.253332 [CATrainingPosCal] consider 2 rank data
5170 23:11:24.256867 u2DelayCellTimex100 = 270/100 ps
5171 23:11:24.260013 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5172 23:11:24.263093 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5173 23:11:24.266857 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5174 23:11:24.273180 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5175 23:11:24.276553 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5176 23:11:24.279698 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5177 23:11:24.279780
5178 23:11:24.282887 CA PerBit enable=1, Macro0, CA PI delay=34
5179 23:11:24.282992
5180 23:11:24.286181 [CBTSetCACLKResult] CA Dly = 34
5181 23:11:24.286264 CS Dly: 7 (0~39)
5182 23:11:24.286329
5183 23:11:24.289541 ----->DramcWriteLeveling(PI) begin...
5184 23:11:24.293295 ==
5185 23:11:24.296574 Dram Type= 6, Freq= 0, CH_0, rank 0
5186 23:11:24.299673 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5187 23:11:24.299759 ==
5188 23:11:24.303266 Write leveling (Byte 0): 33 => 33
5189 23:11:24.306436 Write leveling (Byte 1): 28 => 28
5190 23:11:24.309456 DramcWriteLeveling(PI) end<-----
5191 23:11:24.309577
5192 23:11:24.309643 ==
5193 23:11:24.312933 Dram Type= 6, Freq= 0, CH_0, rank 0
5194 23:11:24.316306 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5195 23:11:24.316391 ==
5196 23:11:24.319442 [Gating] SW mode calibration
5197 23:11:24.325959 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5198 23:11:24.332824 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5199 23:11:24.335794 0 14 0 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (0 0)
5200 23:11:24.339281 0 14 4 | B1->B0 | 3333 3434 | 0 1 | (1 1) (1 1)
5201 23:11:24.346026 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5202 23:11:24.349126 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5203 23:11:24.352635 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5204 23:11:24.359333 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5205 23:11:24.362162 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5206 23:11:24.365487 0 14 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5207 23:11:24.372391 0 15 0 | B1->B0 | 3434 2e2e | 0 1 | (0 0) (1 0)
5208 23:11:24.375591 0 15 4 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (0 0)
5209 23:11:24.378699 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5210 23:11:24.385667 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5211 23:11:24.388743 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5212 23:11:24.391922 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5213 23:11:24.398791 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5214 23:11:24.401725 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5215 23:11:24.405588 1 0 0 | B1->B0 | 2b2b 3636 | 0 1 | (0 0) (0 0)
5216 23:11:24.411949 1 0 4 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
5217 23:11:24.415295 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5218 23:11:24.418314 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5219 23:11:24.425214 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5220 23:11:24.428318 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5221 23:11:24.431871 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5222 23:11:24.438221 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5223 23:11:24.441845 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5224 23:11:24.444841 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5225 23:11:24.451586 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5226 23:11:24.454761 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5227 23:11:24.458210 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5228 23:11:24.464909 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5229 23:11:24.468085 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5230 23:11:24.471563 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5231 23:11:24.477822 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5232 23:11:24.481104 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5233 23:11:24.484513 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5234 23:11:24.490836 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5235 23:11:24.494682 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5236 23:11:24.497872 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5237 23:11:24.501050 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5238 23:11:24.507576 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5239 23:11:24.510780 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5240 23:11:24.514191 Total UI for P1: 0, mck2ui 16
5241 23:11:24.517764 best dqsien dly found for B0: ( 1, 2, 30)
5242 23:11:24.520841 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5243 23:11:24.527246 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5244 23:11:24.530771 Total UI for P1: 0, mck2ui 16
5245 23:11:24.533710 best dqsien dly found for B1: ( 1, 3, 2)
5246 23:11:24.537049 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5247 23:11:24.540846 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5248 23:11:24.540931
5249 23:11:24.543827 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5250 23:11:24.547520 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5251 23:11:24.550437 [Gating] SW calibration Done
5252 23:11:24.550522 ==
5253 23:11:24.553632 Dram Type= 6, Freq= 0, CH_0, rank 0
5254 23:11:24.557239 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5255 23:11:24.557324 ==
5256 23:11:24.560382 RX Vref Scan: 0
5257 23:11:24.560464
5258 23:11:24.563974 RX Vref 0 -> 0, step: 1
5259 23:11:24.564057
5260 23:11:24.564123 RX Delay -80 -> 252, step: 8
5261 23:11:24.570331 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5262 23:11:24.573512 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5263 23:11:24.576818 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5264 23:11:24.579979 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5265 23:11:24.583571 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5266 23:11:24.587130 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5267 23:11:24.593643 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5268 23:11:24.596780 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5269 23:11:24.599832 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5270 23:11:24.603099 iDelay=208, Bit 9, Center 67 (-32 ~ 167) 200
5271 23:11:24.606759 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5272 23:11:24.613191 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5273 23:11:24.616334 iDelay=208, Bit 12, Center 87 (-16 ~ 191) 208
5274 23:11:24.619933 iDelay=208, Bit 13, Center 87 (-16 ~ 191) 208
5275 23:11:24.623211 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5276 23:11:24.629965 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5277 23:11:24.630052 ==
5278 23:11:24.632998 Dram Type= 6, Freq= 0, CH_0, rank 0
5279 23:11:24.636316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5280 23:11:24.636401 ==
5281 23:11:24.636467 DQS Delay:
5282 23:11:24.639770 DQS0 = 0, DQS1 = 0
5283 23:11:24.639853 DQM Delay:
5284 23:11:24.643090 DQM0 = 94, DQM1 = 82
5285 23:11:24.643173 DQ Delay:
5286 23:11:24.646317 DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =91
5287 23:11:24.649621 DQ4 =95, DQ5 =79, DQ6 =103, DQ7 =107
5288 23:11:24.652862 DQ8 =75, DQ9 =67, DQ10 =83, DQ11 =79
5289 23:11:24.656314 DQ12 =87, DQ13 =87, DQ14 =91, DQ15 =91
5290 23:11:24.656399
5291 23:11:24.656465
5292 23:11:24.656525 ==
5293 23:11:24.659239 Dram Type= 6, Freq= 0, CH_0, rank 0
5294 23:11:24.662773 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5295 23:11:24.662857 ==
5296 23:11:24.666253
5297 23:11:24.666336
5298 23:11:24.666401 TX Vref Scan disable
5299 23:11:24.669444 == TX Byte 0 ==
5300 23:11:24.672873 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5301 23:11:24.676062 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5302 23:11:24.679816 == TX Byte 1 ==
5303 23:11:24.682815 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5304 23:11:24.685901 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5305 23:11:24.685985 ==
5306 23:11:24.689543 Dram Type= 6, Freq= 0, CH_0, rank 0
5307 23:11:24.695882 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5308 23:11:24.695968 ==
5309 23:11:24.696034
5310 23:11:24.696095
5311 23:11:24.696154 TX Vref Scan disable
5312 23:11:24.700313 == TX Byte 0 ==
5313 23:11:24.703419 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5314 23:11:24.710280 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5315 23:11:24.710367 == TX Byte 1 ==
5316 23:11:24.713747 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5317 23:11:24.719879 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5318 23:11:24.719966
5319 23:11:24.720033 [DATLAT]
5320 23:11:24.720094 Freq=933, CH0 RK0
5321 23:11:24.720153
5322 23:11:24.723575 DATLAT Default: 0xd
5323 23:11:24.723659 0, 0xFFFF, sum = 0
5324 23:11:24.726779 1, 0xFFFF, sum = 0
5325 23:11:24.729827 2, 0xFFFF, sum = 0
5326 23:11:24.729911 3, 0xFFFF, sum = 0
5327 23:11:24.733764 4, 0xFFFF, sum = 0
5328 23:11:24.733848 5, 0xFFFF, sum = 0
5329 23:11:24.736428 6, 0xFFFF, sum = 0
5330 23:11:24.736513 7, 0xFFFF, sum = 0
5331 23:11:24.740199 8, 0xFFFF, sum = 0
5332 23:11:24.740283 9, 0xFFFF, sum = 0
5333 23:11:24.743365 10, 0x0, sum = 1
5334 23:11:24.743450 11, 0x0, sum = 2
5335 23:11:24.746579 12, 0x0, sum = 3
5336 23:11:24.746664 13, 0x0, sum = 4
5337 23:11:24.746731 best_step = 11
5338 23:11:24.749815
5339 23:11:24.749898 ==
5340 23:11:24.752931 Dram Type= 6, Freq= 0, CH_0, rank 0
5341 23:11:24.756509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5342 23:11:24.756595 ==
5343 23:11:24.756660 RX Vref Scan: 1
5344 23:11:24.756721
5345 23:11:24.759926 RX Vref 0 -> 0, step: 1
5346 23:11:24.760044
5347 23:11:24.763050 RX Delay -77 -> 252, step: 4
5348 23:11:24.763133
5349 23:11:24.766431 Set Vref, RX VrefLevel [Byte0]: 62
5350 23:11:24.769872 [Byte1]: 47
5351 23:11:24.772658
5352 23:11:24.772741 Final RX Vref Byte 0 = 62 to rank0
5353 23:11:24.776205 Final RX Vref Byte 1 = 47 to rank0
5354 23:11:24.779642 Final RX Vref Byte 0 = 62 to rank1
5355 23:11:24.783134 Final RX Vref Byte 1 = 47 to rank1==
5356 23:11:24.786233 Dram Type= 6, Freq= 0, CH_0, rank 0
5357 23:11:24.793050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5358 23:11:24.793138 ==
5359 23:11:24.793204 DQS Delay:
5360 23:11:24.796104 DQS0 = 0, DQS1 = 0
5361 23:11:24.796187 DQM Delay:
5362 23:11:24.796252 DQM0 = 95, DQM1 = 82
5363 23:11:24.799284 DQ Delay:
5364 23:11:24.802401 DQ0 =94, DQ1 =94, DQ2 =92, DQ3 =92
5365 23:11:24.806150 DQ4 =96, DQ5 =84, DQ6 =102, DQ7 =108
5366 23:11:24.809677 DQ8 =76, DQ9 =68, DQ10 =82, DQ11 =78
5367 23:11:24.812384 DQ12 =86, DQ13 =86, DQ14 =96, DQ15 =88
5368 23:11:24.812466
5369 23:11:24.812530
5370 23:11:24.819213 [DQSOSCAuto] RK0, (LSB)MR18= 0x1010, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 416 ps
5371 23:11:24.822344 CH0 RK0: MR19=505, MR18=1010
5372 23:11:24.828805 CH0_RK0: MR19=0x505, MR18=0x1010, DQSOSC=416, MR23=63, INC=62, DEC=41
5373 23:11:24.828894
5374 23:11:24.832175 ----->DramcWriteLeveling(PI) begin...
5375 23:11:24.832259 ==
5376 23:11:24.835792 Dram Type= 6, Freq= 0, CH_0, rank 1
5377 23:11:24.839305 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5378 23:11:24.839388 ==
5379 23:11:24.842399 Write leveling (Byte 0): 31 => 31
5380 23:11:24.845677 Write leveling (Byte 1): 29 => 29
5381 23:11:24.849341 DramcWriteLeveling(PI) end<-----
5382 23:11:24.849449
5383 23:11:24.849562 ==
5384 23:11:24.852550 Dram Type= 6, Freq= 0, CH_0, rank 1
5385 23:11:24.855569 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5386 23:11:24.855655 ==
5387 23:11:24.858781 [Gating] SW mode calibration
5388 23:11:24.865619 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5389 23:11:24.872173 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5390 23:11:24.875576 0 14 0 | B1->B0 | 2525 3434 | 1 1 | (0 0) (1 1)
5391 23:11:24.882344 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5392 23:11:24.885279 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5393 23:11:24.888941 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5394 23:11:24.895235 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5395 23:11:24.898542 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5396 23:11:24.902100 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5397 23:11:24.908465 0 14 28 | B1->B0 | 3232 2e2e | 1 0 | (1 0) (1 0)
5398 23:11:24.912089 0 15 0 | B1->B0 | 3030 2323 | 0 0 | (0 0) (0 0)
5399 23:11:24.915248 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5400 23:11:24.922063 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5401 23:11:24.925107 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5402 23:11:24.928545 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5403 23:11:24.934971 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5404 23:11:24.938571 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5405 23:11:24.941770 0 15 28 | B1->B0 | 2626 3534 | 0 1 | (0 0) (0 0)
5406 23:11:24.948180 1 0 0 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
5407 23:11:24.951632 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5408 23:11:24.954847 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5409 23:11:24.961742 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5410 23:11:24.964827 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5411 23:11:24.968346 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5412 23:11:24.971840 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5413 23:11:24.978236 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5414 23:11:24.981267 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5415 23:11:24.984937 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5416 23:11:24.991210 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5417 23:11:24.994737 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5418 23:11:24.998019 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5419 23:11:25.004583 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5420 23:11:25.007845 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5421 23:11:25.011111 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5422 23:11:25.017978 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5423 23:11:25.021239 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5424 23:11:25.024338 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5425 23:11:25.031234 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5426 23:11:25.034269 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5427 23:11:25.037590 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5428 23:11:25.044653 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5429 23:11:25.047856 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5430 23:11:25.051253 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5431 23:11:25.054554 Total UI for P1: 0, mck2ui 16
5432 23:11:25.058004 best dqsien dly found for B0: ( 1, 2, 28)
5433 23:11:25.064237 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5434 23:11:25.064327 Total UI for P1: 0, mck2ui 16
5435 23:11:25.071087 best dqsien dly found for B1: ( 1, 3, 0)
5436 23:11:25.074272 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5437 23:11:25.077803 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5438 23:11:25.077887
5439 23:11:25.080751 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5440 23:11:25.084082 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5441 23:11:25.087461 [Gating] SW calibration Done
5442 23:11:25.087546 ==
5443 23:11:25.090918 Dram Type= 6, Freq= 0, CH_0, rank 1
5444 23:11:25.094104 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5445 23:11:25.094189 ==
5446 23:11:25.097603 RX Vref Scan: 0
5447 23:11:25.097686
5448 23:11:25.097752 RX Vref 0 -> 0, step: 1
5449 23:11:25.097813
5450 23:11:25.100599 RX Delay -80 -> 252, step: 8
5451 23:11:25.104110 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5452 23:11:25.110944 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5453 23:11:25.114162 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5454 23:11:25.117202 iDelay=208, Bit 3, Center 87 (-16 ~ 191) 208
5455 23:11:25.120620 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5456 23:11:25.123813 iDelay=208, Bit 5, Center 75 (-24 ~ 175) 200
5457 23:11:25.127366 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5458 23:11:25.133926 iDelay=208, Bit 7, Center 103 (0 ~ 207) 208
5459 23:11:25.137317 iDelay=208, Bit 8, Center 71 (-24 ~ 167) 192
5460 23:11:25.140302 iDelay=208, Bit 9, Center 63 (-32 ~ 159) 192
5461 23:11:25.143677 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5462 23:11:25.147253 iDelay=208, Bit 11, Center 71 (-24 ~ 167) 192
5463 23:11:25.153930 iDelay=208, Bit 12, Center 87 (-8 ~ 183) 192
5464 23:11:25.156880 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5465 23:11:25.160455 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5466 23:11:25.163886 iDelay=208, Bit 15, Center 87 (-8 ~ 183) 192
5467 23:11:25.163972 ==
5468 23:11:25.167391 Dram Type= 6, Freq= 0, CH_0, rank 1
5469 23:11:25.173769 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5470 23:11:25.173863 ==
5471 23:11:25.173932 DQS Delay:
5472 23:11:25.173993 DQS0 = 0, DQS1 = 0
5473 23:11:25.177010 DQM Delay:
5474 23:11:25.177093 DQM0 = 91, DQM1 = 81
5475 23:11:25.180202 DQ Delay:
5476 23:11:25.183828 DQ0 =91, DQ1 =95, DQ2 =87, DQ3 =87
5477 23:11:25.187286 DQ4 =91, DQ5 =75, DQ6 =103, DQ7 =103
5478 23:11:25.187371 DQ8 =71, DQ9 =63, DQ10 =87, DQ11 =71
5479 23:11:25.193859 DQ12 =87, DQ13 =91, DQ14 =95, DQ15 =87
5480 23:11:25.193945
5481 23:11:25.194010
5482 23:11:25.194071 ==
5483 23:11:25.197004 Dram Type= 6, Freq= 0, CH_0, rank 1
5484 23:11:25.200123 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5485 23:11:25.200207 ==
5486 23:11:25.200273
5487 23:11:25.200333
5488 23:11:25.203749 TX Vref Scan disable
5489 23:11:25.203832 == TX Byte 0 ==
5490 23:11:25.210182 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5491 23:11:25.213621 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5492 23:11:25.213706 == TX Byte 1 ==
5493 23:11:25.219975 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5494 23:11:25.223505 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5495 23:11:25.223592 ==
5496 23:11:25.226608 Dram Type= 6, Freq= 0, CH_0, rank 1
5497 23:11:25.230054 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5498 23:11:25.230139 ==
5499 23:11:25.230205
5500 23:11:25.233089
5501 23:11:25.233172 TX Vref Scan disable
5502 23:11:25.236585 == TX Byte 0 ==
5503 23:11:25.239969 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5504 23:11:25.243644 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5505 23:11:25.246784 == TX Byte 1 ==
5506 23:11:25.250286 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5507 23:11:25.253337 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5508 23:11:25.253463
5509 23:11:25.256637 [DATLAT]
5510 23:11:25.256720 Freq=933, CH0 RK1
5511 23:11:25.256787
5512 23:11:25.259745 DATLAT Default: 0xb
5513 23:11:25.259828 0, 0xFFFF, sum = 0
5514 23:11:25.263221 1, 0xFFFF, sum = 0
5515 23:11:25.263305 2, 0xFFFF, sum = 0
5516 23:11:25.266643 3, 0xFFFF, sum = 0
5517 23:11:25.266727 4, 0xFFFF, sum = 0
5518 23:11:25.269924 5, 0xFFFF, sum = 0
5519 23:11:25.270008 6, 0xFFFF, sum = 0
5520 23:11:25.273395 7, 0xFFFF, sum = 0
5521 23:11:25.276407 8, 0xFFFF, sum = 0
5522 23:11:25.276491 9, 0xFFFF, sum = 0
5523 23:11:25.276558 10, 0x0, sum = 1
5524 23:11:25.279879 11, 0x0, sum = 2
5525 23:11:25.279964 12, 0x0, sum = 3
5526 23:11:25.283122 13, 0x0, sum = 4
5527 23:11:25.283207 best_step = 11
5528 23:11:25.283273
5529 23:11:25.283333 ==
5530 23:11:25.286770 Dram Type= 6, Freq= 0, CH_0, rank 1
5531 23:11:25.292758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5532 23:11:25.292842 ==
5533 23:11:25.292909 RX Vref Scan: 0
5534 23:11:25.292970
5535 23:11:25.296196 RX Vref 0 -> 0, step: 1
5536 23:11:25.296279
5537 23:11:25.299705 RX Delay -77 -> 252, step: 4
5538 23:11:25.302859 iDelay=199, Bit 0, Center 88 (-5 ~ 182) 188
5539 23:11:25.309790 iDelay=199, Bit 1, Center 96 (7 ~ 186) 180
5540 23:11:25.312888 iDelay=199, Bit 2, Center 90 (-1 ~ 182) 184
5541 23:11:25.316295 iDelay=199, Bit 3, Center 90 (-5 ~ 186) 192
5542 23:11:25.319567 iDelay=199, Bit 4, Center 90 (-5 ~ 186) 192
5543 23:11:25.322819 iDelay=199, Bit 5, Center 82 (-9 ~ 174) 184
5544 23:11:25.326006 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5545 23:11:25.332459 iDelay=199, Bit 7, Center 104 (11 ~ 198) 188
5546 23:11:25.335888 iDelay=199, Bit 8, Center 76 (-13 ~ 166) 180
5547 23:11:25.339331 iDelay=199, Bit 9, Center 66 (-21 ~ 154) 176
5548 23:11:25.342361 iDelay=199, Bit 10, Center 88 (-1 ~ 178) 180
5549 23:11:25.349296 iDelay=199, Bit 11, Center 76 (-13 ~ 166) 180
5550 23:11:25.352305 iDelay=199, Bit 12, Center 88 (-5 ~ 182) 188
5551 23:11:25.355898 iDelay=199, Bit 13, Center 90 (-1 ~ 182) 184
5552 23:11:25.359083 iDelay=199, Bit 14, Center 94 (3 ~ 186) 184
5553 23:11:25.362333 iDelay=199, Bit 15, Center 92 (3 ~ 182) 180
5554 23:11:25.362417 ==
5555 23:11:25.365504 Dram Type= 6, Freq= 0, CH_0, rank 1
5556 23:11:25.372255 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5557 23:11:25.372342 ==
5558 23:11:25.372409 DQS Delay:
5559 23:11:25.375639 DQS0 = 0, DQS1 = 0
5560 23:11:25.375723 DQM Delay:
5561 23:11:25.375790 DQM0 = 93, DQM1 = 83
5562 23:11:25.378787 DQ Delay:
5563 23:11:25.382003 DQ0 =88, DQ1 =96, DQ2 =90, DQ3 =90
5564 23:11:25.385344 DQ4 =90, DQ5 =82, DQ6 =104, DQ7 =104
5565 23:11:25.388603 DQ8 =76, DQ9 =66, DQ10 =88, DQ11 =76
5566 23:11:25.392535 DQ12 =88, DQ13 =90, DQ14 =94, DQ15 =92
5567 23:11:25.392619
5568 23:11:25.392684
5569 23:11:25.398740 [DQSOSCAuto] RK1, (LSB)MR18= 0x2e0e, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 407 ps
5570 23:11:25.401744 CH0 RK1: MR19=505, MR18=2E0E
5571 23:11:25.408891 CH0_RK1: MR19=0x505, MR18=0x2E0E, DQSOSC=407, MR23=63, INC=65, DEC=43
5572 23:11:25.412188 [RxdqsGatingPostProcess] freq 933
5573 23:11:25.418329 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5574 23:11:25.418414 best DQS0 dly(2T, 0.5T) = (0, 10)
5575 23:11:25.421909 best DQS1 dly(2T, 0.5T) = (0, 11)
5576 23:11:25.425397 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5577 23:11:25.428711 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5578 23:11:25.431581 best DQS0 dly(2T, 0.5T) = (0, 10)
5579 23:11:25.435072 best DQS1 dly(2T, 0.5T) = (0, 11)
5580 23:11:25.438120 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5581 23:11:25.441514 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5582 23:11:25.444811 Pre-setting of DQS Precalculation
5583 23:11:25.448197 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5584 23:11:25.451841 ==
5585 23:11:25.454883 Dram Type= 6, Freq= 0, CH_1, rank 0
5586 23:11:25.457939 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5587 23:11:25.458024 ==
5588 23:11:25.461468 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5589 23:11:25.468413 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5590 23:11:25.471627 [CA 0] Center 37 (7~67) winsize 61
5591 23:11:25.475201 [CA 1] Center 37 (7~67) winsize 61
5592 23:11:25.478268 [CA 2] Center 35 (5~65) winsize 61
5593 23:11:25.481500 [CA 3] Center 34 (5~64) winsize 60
5594 23:11:25.485272 [CA 4] Center 34 (5~64) winsize 60
5595 23:11:25.488435 [CA 5] Center 33 (4~63) winsize 60
5596 23:11:25.488520
5597 23:11:25.491673 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5598 23:11:25.491756
5599 23:11:25.494720 [CATrainingPosCal] consider 1 rank data
5600 23:11:25.498120 u2DelayCellTimex100 = 270/100 ps
5601 23:11:25.501897 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5602 23:11:25.508168 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5603 23:11:25.511327 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5604 23:11:25.514872 CA3 delay=34 (5~64),Diff = 1 PI (6 cell)
5605 23:11:25.518358 CA4 delay=34 (5~64),Diff = 1 PI (6 cell)
5606 23:11:25.521862 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
5607 23:11:25.521948
5608 23:11:25.524824 CA PerBit enable=1, Macro0, CA PI delay=33
5609 23:11:25.524908
5610 23:11:25.528029 [CBTSetCACLKResult] CA Dly = 33
5611 23:11:25.528114 CS Dly: 6 (0~37)
5612 23:11:25.531619 ==
5613 23:11:25.534513 Dram Type= 6, Freq= 0, CH_1, rank 1
5614 23:11:25.538059 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5615 23:11:25.538144 ==
5616 23:11:25.541290 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5617 23:11:25.548013 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5618 23:11:25.552136 [CA 0] Center 37 (8~67) winsize 60
5619 23:11:25.555177 [CA 1] Center 38 (7~69) winsize 63
5620 23:11:25.558323 [CA 2] Center 35 (5~65) winsize 61
5621 23:11:25.561829 [CA 3] Center 34 (4~64) winsize 61
5622 23:11:25.565036 [CA 4] Center 35 (5~65) winsize 61
5623 23:11:25.568171 [CA 5] Center 34 (4~64) winsize 61
5624 23:11:25.568254
5625 23:11:25.571696 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5626 23:11:25.571779
5627 23:11:25.574876 [CATrainingPosCal] consider 2 rank data
5628 23:11:25.577996 u2DelayCellTimex100 = 270/100 ps
5629 23:11:25.581758 CA0 delay=37 (8~67),Diff = 4 PI (24 cell)
5630 23:11:25.587989 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5631 23:11:25.591250 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5632 23:11:25.594896 CA3 delay=34 (5~64),Diff = 1 PI (6 cell)
5633 23:11:25.598091 CA4 delay=34 (5~64),Diff = 1 PI (6 cell)
5634 23:11:25.601160 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
5635 23:11:25.601243
5636 23:11:25.604759 CA PerBit enable=1, Macro0, CA PI delay=33
5637 23:11:25.604843
5638 23:11:25.607996 [CBTSetCACLKResult] CA Dly = 33
5639 23:11:25.611194 CS Dly: 7 (0~39)
5640 23:11:25.611277
5641 23:11:25.614627 ----->DramcWriteLeveling(PI) begin...
5642 23:11:25.614713 ==
5643 23:11:25.617981 Dram Type= 6, Freq= 0, CH_1, rank 0
5644 23:11:25.621120 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5645 23:11:25.621204 ==
5646 23:11:25.624227 Write leveling (Byte 0): 27 => 27
5647 23:11:25.627951 Write leveling (Byte 1): 29 => 29
5648 23:11:25.631107 DramcWriteLeveling(PI) end<-----
5649 23:11:25.631190
5650 23:11:25.631255 ==
5651 23:11:25.634545 Dram Type= 6, Freq= 0, CH_1, rank 0
5652 23:11:25.637925 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5653 23:11:25.638010 ==
5654 23:11:25.640866 [Gating] SW mode calibration
5655 23:11:25.647506 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5656 23:11:25.654056 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5657 23:11:25.657612 0 14 0 | B1->B0 | 3030 2f2f | 1 1 | (1 1) (0 0)
5658 23:11:25.660722 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5659 23:11:25.667926 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5660 23:11:25.670967 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5661 23:11:25.674114 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5662 23:11:25.680528 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5663 23:11:25.684190 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5664 23:11:25.687282 0 14 28 | B1->B0 | 3232 2f2f | 0 0 | (0 1) (0 1)
5665 23:11:25.693751 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5666 23:11:25.697370 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5667 23:11:25.700334 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5668 23:11:25.707492 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5669 23:11:25.710336 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5670 23:11:25.713882 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5671 23:11:25.720241 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5672 23:11:25.723509 0 15 28 | B1->B0 | 3130 3131 | 1 0 | (0 0) (0 0)
5673 23:11:25.726893 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5674 23:11:25.733834 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5675 23:11:25.736909 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5676 23:11:25.740039 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5677 23:11:25.746969 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5678 23:11:25.750329 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5679 23:11:25.753375 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5680 23:11:25.760233 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5681 23:11:25.763309 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5682 23:11:25.766939 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5683 23:11:25.773399 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5684 23:11:25.776658 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5685 23:11:25.779890 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5686 23:11:25.786655 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5687 23:11:25.789875 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5688 23:11:25.793061 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5689 23:11:25.799578 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5690 23:11:25.803112 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5691 23:11:25.806262 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5692 23:11:25.812877 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5693 23:11:25.816001 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5694 23:11:25.819676 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5695 23:11:25.826424 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5696 23:11:25.829322 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5697 23:11:25.832779 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5698 23:11:25.836565 Total UI for P1: 0, mck2ui 16
5699 23:11:25.839860 best dqsien dly found for B0: ( 1, 2, 28)
5700 23:11:25.842974 Total UI for P1: 0, mck2ui 16
5701 23:11:25.846000 best dqsien dly found for B1: ( 1, 2, 28)
5702 23:11:25.849317 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5703 23:11:25.852838 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5704 23:11:25.852925
5705 23:11:25.855893 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5706 23:11:25.862568 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5707 23:11:25.862658 [Gating] SW calibration Done
5708 23:11:25.862746 ==
5709 23:11:25.865838 Dram Type= 6, Freq= 0, CH_1, rank 0
5710 23:11:25.872485 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5711 23:11:25.872577 ==
5712 23:11:25.872666 RX Vref Scan: 0
5713 23:11:25.872748
5714 23:11:25.875699 RX Vref 0 -> 0, step: 1
5715 23:11:25.875785
5716 23:11:25.879173 RX Delay -80 -> 252, step: 8
5717 23:11:25.882866 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5718 23:11:25.886015 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5719 23:11:25.889135 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5720 23:11:25.896047 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5721 23:11:25.899223 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5722 23:11:25.902649 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5723 23:11:25.905637 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5724 23:11:25.909326 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5725 23:11:25.912362 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5726 23:11:25.919227 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5727 23:11:25.922512 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5728 23:11:25.925588 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5729 23:11:25.928858 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5730 23:11:25.932376 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5731 23:11:25.938773 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5732 23:11:25.942305 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5733 23:11:25.942395 ==
5734 23:11:25.945498 Dram Type= 6, Freq= 0, CH_1, rank 0
5735 23:11:25.949221 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5736 23:11:25.949309 ==
5737 23:11:25.952017 DQS Delay:
5738 23:11:25.952103 DQS0 = 0, DQS1 = 0
5739 23:11:25.952190 DQM Delay:
5740 23:11:25.955467 DQM0 = 95, DQM1 = 86
5741 23:11:25.955553 DQ Delay:
5742 23:11:25.959098 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5743 23:11:25.962296 DQ4 =91, DQ5 =107, DQ6 =107, DQ7 =91
5744 23:11:25.965345 DQ8 =75, DQ9 =79, DQ10 =87, DQ11 =83
5745 23:11:25.968864 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5746 23:11:25.968950
5747 23:11:25.969037
5748 23:11:25.969119 ==
5749 23:11:25.972277 Dram Type= 6, Freq= 0, CH_1, rank 0
5750 23:11:25.978786 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5751 23:11:25.978875 ==
5752 23:11:25.978963
5753 23:11:25.979045
5754 23:11:25.979125 TX Vref Scan disable
5755 23:11:25.982304 == TX Byte 0 ==
5756 23:11:25.985374 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5757 23:11:25.991927 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5758 23:11:25.992017 == TX Byte 1 ==
5759 23:11:25.995253 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5760 23:11:26.002074 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5761 23:11:26.002163 ==
5762 23:11:26.005161 Dram Type= 6, Freq= 0, CH_1, rank 0
5763 23:11:26.008732 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5764 23:11:26.008818 ==
5765 23:11:26.008906
5766 23:11:26.008989
5767 23:11:26.012097 TX Vref Scan disable
5768 23:11:26.012182 == TX Byte 0 ==
5769 23:11:26.018596 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5770 23:11:26.022129 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5771 23:11:26.022216 == TX Byte 1 ==
5772 23:11:26.028401 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5773 23:11:26.031693 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5774 23:11:26.031780
5775 23:11:26.031867 [DATLAT]
5776 23:11:26.035400 Freq=933, CH1 RK0
5777 23:11:26.035487
5778 23:11:26.035574 DATLAT Default: 0xd
5779 23:11:26.038248 0, 0xFFFF, sum = 0
5780 23:11:26.038335 1, 0xFFFF, sum = 0
5781 23:11:26.042074 2, 0xFFFF, sum = 0
5782 23:11:26.045438 3, 0xFFFF, sum = 0
5783 23:11:26.045590 4, 0xFFFF, sum = 0
5784 23:11:26.048231 5, 0xFFFF, sum = 0
5785 23:11:26.048319 6, 0xFFFF, sum = 0
5786 23:11:26.051928 7, 0xFFFF, sum = 0
5787 23:11:26.052016 8, 0xFFFF, sum = 0
5788 23:11:26.054925 9, 0xFFFF, sum = 0
5789 23:11:26.055012 10, 0x0, sum = 1
5790 23:11:26.058560 11, 0x0, sum = 2
5791 23:11:26.058648 12, 0x0, sum = 3
5792 23:11:26.058737 13, 0x0, sum = 4
5793 23:11:26.061835 best_step = 11
5794 23:11:26.061921
5795 23:11:26.062008 ==
5796 23:11:26.064960 Dram Type= 6, Freq= 0, CH_1, rank 0
5797 23:11:26.068054 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5798 23:11:26.068141 ==
5799 23:11:26.071677 RX Vref Scan: 1
5800 23:11:26.071762
5801 23:11:26.074973 RX Vref 0 -> 0, step: 1
5802 23:11:26.075059
5803 23:11:26.075146 RX Delay -69 -> 252, step: 4
5804 23:11:26.075228
5805 23:11:26.078024 Set Vref, RX VrefLevel [Byte0]: 50
5806 23:11:26.081204 [Byte1]: 53
5807 23:11:26.086067
5808 23:11:26.086155 Final RX Vref Byte 0 = 50 to rank0
5809 23:11:26.089302 Final RX Vref Byte 1 = 53 to rank0
5810 23:11:26.092838 Final RX Vref Byte 0 = 50 to rank1
5811 23:11:26.095799 Final RX Vref Byte 1 = 53 to rank1==
5812 23:11:26.099530 Dram Type= 6, Freq= 0, CH_1, rank 0
5813 23:11:26.106194 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5814 23:11:26.106281 ==
5815 23:11:26.106367 DQS Delay:
5816 23:11:26.109315 DQS0 = 0, DQS1 = 0
5817 23:11:26.109400 DQM Delay:
5818 23:11:26.109512 DQM0 = 96, DQM1 = 88
5819 23:11:26.112728 DQ Delay:
5820 23:11:26.115735 DQ0 =102, DQ1 =90, DQ2 =84, DQ3 =94
5821 23:11:26.119064 DQ4 =94, DQ5 =106, DQ6 =106, DQ7 =92
5822 23:11:26.122167 DQ8 =78, DQ9 =80, DQ10 =86, DQ11 =82
5823 23:11:26.125892 DQ12 =96, DQ13 =94, DQ14 =96, DQ15 =94
5824 23:11:26.125978
5825 23:11:26.126064
5826 23:11:26.132225 [DQSOSCAuto] RK0, (LSB)MR18= 0x40c, (MSB)MR19= 0x505, tDQSOscB0 = 418 ps tDQSOscB1 = 420 ps
5827 23:11:26.135848 CH1 RK0: MR19=505, MR18=40C
5828 23:11:26.142099 CH1_RK0: MR19=0x505, MR18=0x40C, DQSOSC=418, MR23=63, INC=62, DEC=41
5829 23:11:26.142188
5830 23:11:26.145363 ----->DramcWriteLeveling(PI) begin...
5831 23:11:26.145451 ==
5832 23:11:26.148702 Dram Type= 6, Freq= 0, CH_1, rank 1
5833 23:11:26.151985 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5834 23:11:26.152074 ==
5835 23:11:26.155227 Write leveling (Byte 0): 27 => 27
5836 23:11:26.158762 Write leveling (Byte 1): 27 => 27
5837 23:11:26.162411 DramcWriteLeveling(PI) end<-----
5838 23:11:26.162497
5839 23:11:26.162584 ==
5840 23:11:26.165374 Dram Type= 6, Freq= 0, CH_1, rank 1
5841 23:11:26.168914 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5842 23:11:26.169001 ==
5843 23:11:26.172093 [Gating] SW mode calibration
5844 23:11:26.178855 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5845 23:11:26.185292 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5846 23:11:26.188713 0 14 0 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
5847 23:11:26.195392 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5848 23:11:26.198528 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5849 23:11:26.201721 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5850 23:11:26.208419 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5851 23:11:26.211818 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5852 23:11:26.214788 0 14 24 | B1->B0 | 3232 2e2e | 0 1 | (0 0) (1 0)
5853 23:11:26.221685 0 14 28 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
5854 23:11:26.224730 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5855 23:11:26.228112 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5856 23:11:26.235043 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5857 23:11:26.238498 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5858 23:11:26.241732 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5859 23:11:26.248449 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5860 23:11:26.251589 0 15 24 | B1->B0 | 2828 3535 | 0 0 | (0 0) (1 1)
5861 23:11:26.254798 0 15 28 | B1->B0 | 3131 4242 | 1 0 | (0 0) (1 1)
5862 23:11:26.261359 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5863 23:11:26.264783 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5864 23:11:26.267871 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5865 23:11:26.271272 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5866 23:11:26.278075 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5867 23:11:26.281461 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5868 23:11:26.284753 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5869 23:11:26.291557 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5870 23:11:26.294690 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5871 23:11:26.297676 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5872 23:11:26.304413 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5873 23:11:26.307564 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5874 23:11:26.310872 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5875 23:11:26.317440 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5876 23:11:26.321006 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5877 23:11:26.324199 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5878 23:11:26.330861 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5879 23:11:26.334390 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5880 23:11:26.337397 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5881 23:11:26.344267 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5882 23:11:26.347343 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5883 23:11:26.350604 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5884 23:11:26.357280 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5885 23:11:26.360938 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5886 23:11:26.364079 Total UI for P1: 0, mck2ui 16
5887 23:11:26.367318 best dqsien dly found for B0: ( 1, 2, 24)
5888 23:11:26.370584 Total UI for P1: 0, mck2ui 16
5889 23:11:26.374191 best dqsien dly found for B1: ( 1, 2, 26)
5890 23:11:26.377444 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5891 23:11:26.380695 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5892 23:11:26.380803
5893 23:11:26.384071 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5894 23:11:26.386998 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5895 23:11:26.390540 [Gating] SW calibration Done
5896 23:11:26.390620 ==
5897 23:11:26.394196 Dram Type= 6, Freq= 0, CH_1, rank 1
5898 23:11:26.400673 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5899 23:11:26.400755 ==
5900 23:11:26.400819 RX Vref Scan: 0
5901 23:11:26.400879
5902 23:11:26.403598 RX Vref 0 -> 0, step: 1
5903 23:11:26.403679
5904 23:11:26.406854 RX Delay -80 -> 252, step: 8
5905 23:11:26.410618 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5906 23:11:26.413660 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5907 23:11:26.416861 iDelay=208, Bit 2, Center 79 (-16 ~ 175) 192
5908 23:11:26.420433 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5909 23:11:26.426767 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5910 23:11:26.430298 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5911 23:11:26.433792 iDelay=208, Bit 6, Center 99 (0 ~ 199) 200
5912 23:11:26.436743 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5913 23:11:26.440199 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5914 23:11:26.443701 iDelay=208, Bit 9, Center 83 (-16 ~ 183) 200
5915 23:11:26.450644 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5916 23:11:26.453542 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5917 23:11:26.456727 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5918 23:11:26.460099 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5919 23:11:26.463358 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5920 23:11:26.469802 iDelay=208, Bit 15, Center 95 (-8 ~ 199) 208
5921 23:11:26.469888 ==
5922 23:11:26.473449 Dram Type= 6, Freq= 0, CH_1, rank 1
5923 23:11:26.476424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5924 23:11:26.476510 ==
5925 23:11:26.476596 DQS Delay:
5926 23:11:26.480075 DQS0 = 0, DQS1 = 0
5927 23:11:26.480189 DQM Delay:
5928 23:11:26.483215 DQM0 = 93, DQM1 = 90
5929 23:11:26.483296 DQ Delay:
5930 23:11:26.486740 DQ0 =99, DQ1 =91, DQ2 =79, DQ3 =91
5931 23:11:26.490034 DQ4 =91, DQ5 =103, DQ6 =99, DQ7 =91
5932 23:11:26.493414 DQ8 =75, DQ9 =83, DQ10 =91, DQ11 =87
5933 23:11:26.496609 DQ12 =99, DQ13 =99, DQ14 =91, DQ15 =95
5934 23:11:26.496692
5935 23:11:26.496757
5936 23:11:26.496818 ==
5937 23:11:26.499645 Dram Type= 6, Freq= 0, CH_1, rank 1
5938 23:11:26.503272 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5939 23:11:26.503355 ==
5940 23:11:26.503421
5941 23:11:26.506497
5942 23:11:26.506579 TX Vref Scan disable
5943 23:11:26.509954 == TX Byte 0 ==
5944 23:11:26.513112 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5945 23:11:26.516272 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5946 23:11:26.519890 == TX Byte 1 ==
5947 23:11:26.522900 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5948 23:11:26.526069 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5949 23:11:26.526151 ==
5950 23:11:26.529907 Dram Type= 6, Freq= 0, CH_1, rank 1
5951 23:11:26.536023 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5952 23:11:26.536106 ==
5953 23:11:26.536207
5954 23:11:26.536267
5955 23:11:26.536324 TX Vref Scan disable
5956 23:11:26.540578 == TX Byte 0 ==
5957 23:11:26.543788 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5958 23:11:26.547410 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5959 23:11:26.550349 == TX Byte 1 ==
5960 23:11:26.553974 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5961 23:11:26.560203 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5962 23:11:26.560289
5963 23:11:26.560354 [DATLAT]
5964 23:11:26.560416 Freq=933, CH1 RK1
5965 23:11:26.560475
5966 23:11:26.563717 DATLAT Default: 0xb
5967 23:11:26.563799 0, 0xFFFF, sum = 0
5968 23:11:26.566917 1, 0xFFFF, sum = 0
5969 23:11:26.567001 2, 0xFFFF, sum = 0
5970 23:11:26.570077 3, 0xFFFF, sum = 0
5971 23:11:26.573650 4, 0xFFFF, sum = 0
5972 23:11:26.573735 5, 0xFFFF, sum = 0
5973 23:11:26.577054 6, 0xFFFF, sum = 0
5974 23:11:26.577138 7, 0xFFFF, sum = 0
5975 23:11:26.580256 8, 0xFFFF, sum = 0
5976 23:11:26.580339 9, 0xFFFF, sum = 0
5977 23:11:26.583635 10, 0x0, sum = 1
5978 23:11:26.583719 11, 0x0, sum = 2
5979 23:11:26.587087 12, 0x0, sum = 3
5980 23:11:26.587171 13, 0x0, sum = 4
5981 23:11:26.587239 best_step = 11
5982 23:11:26.587300
5983 23:11:26.590120 ==
5984 23:11:26.593524 Dram Type= 6, Freq= 0, CH_1, rank 1
5985 23:11:26.596802 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5986 23:11:26.596886 ==
5987 23:11:26.596954 RX Vref Scan: 0
5988 23:11:26.597015
5989 23:11:26.600357 RX Vref 0 -> 0, step: 1
5990 23:11:26.600439
5991 23:11:26.603235 RX Delay -69 -> 252, step: 4
5992 23:11:26.610121 iDelay=203, Bit 0, Center 96 (-1 ~ 194) 196
5993 23:11:26.613711 iDelay=203, Bit 1, Center 88 (-9 ~ 186) 196
5994 23:11:26.616796 iDelay=203, Bit 2, Center 82 (-13 ~ 178) 192
5995 23:11:26.619817 iDelay=203, Bit 3, Center 88 (-9 ~ 186) 196
5996 23:11:26.623367 iDelay=203, Bit 4, Center 90 (-5 ~ 186) 192
5997 23:11:26.626553 iDelay=203, Bit 5, Center 102 (7 ~ 198) 192
5998 23:11:26.633434 iDelay=203, Bit 6, Center 102 (3 ~ 202) 200
5999 23:11:26.636603 iDelay=203, Bit 7, Center 88 (-9 ~ 186) 196
6000 23:11:26.639634 iDelay=203, Bit 8, Center 82 (-9 ~ 174) 184
6001 23:11:26.643385 iDelay=203, Bit 9, Center 82 (-9 ~ 174) 184
6002 23:11:26.646232 iDelay=203, Bit 10, Center 92 (-1 ~ 186) 188
6003 23:11:26.649701 iDelay=203, Bit 11, Center 84 (-9 ~ 178) 188
6004 23:11:26.656140 iDelay=203, Bit 12, Center 96 (3 ~ 190) 188
6005 23:11:26.659749 iDelay=203, Bit 13, Center 96 (3 ~ 190) 188
6006 23:11:26.662898 iDelay=203, Bit 14, Center 96 (3 ~ 190) 188
6007 23:11:26.666363 iDelay=203, Bit 15, Center 96 (3 ~ 190) 188
6008 23:11:26.666446 ==
6009 23:11:26.669379 Dram Type= 6, Freq= 0, CH_1, rank 1
6010 23:11:26.676384 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
6011 23:11:26.676466 ==
6012 23:11:26.676530 DQS Delay:
6013 23:11:26.676590 DQS0 = 0, DQS1 = 0
6014 23:11:26.679564 DQM Delay:
6015 23:11:26.679637 DQM0 = 92, DQM1 = 90
6016 23:11:26.682595 DQ Delay:
6017 23:11:26.686379 DQ0 =96, DQ1 =88, DQ2 =82, DQ3 =88
6018 23:11:26.689374 DQ4 =90, DQ5 =102, DQ6 =102, DQ7 =88
6019 23:11:26.692904 DQ8 =82, DQ9 =82, DQ10 =92, DQ11 =84
6020 23:11:26.696232 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
6021 23:11:26.696307
6022 23:11:26.696370
6023 23:11:26.702987 [DQSOSCAuto] RK1, (LSB)MR18= 0xd21, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 417 ps
6024 23:11:26.706176 CH1 RK1: MR19=505, MR18=D21
6025 23:11:26.712615 CH1_RK1: MR19=0x505, MR18=0xD21, DQSOSC=411, MR23=63, INC=64, DEC=42
6026 23:11:26.715888 [RxdqsGatingPostProcess] freq 933
6027 23:11:26.719468 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6028 23:11:26.722792 best DQS0 dly(2T, 0.5T) = (0, 10)
6029 23:11:26.726174 best DQS1 dly(2T, 0.5T) = (0, 10)
6030 23:11:26.729381 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6031 23:11:26.732434 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6032 23:11:26.736165 best DQS0 dly(2T, 0.5T) = (0, 10)
6033 23:11:26.738822 best DQS1 dly(2T, 0.5T) = (0, 10)
6034 23:11:26.742197 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6035 23:11:26.745778 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6036 23:11:26.749201 Pre-setting of DQS Precalculation
6037 23:11:26.752316 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6038 23:11:26.758846 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6039 23:11:26.768929 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6040 23:11:26.769050
6041 23:11:26.769156
6042 23:11:26.772566 [Calibration Summary] 1866 Mbps
6043 23:11:26.772648 CH 0, Rank 0
6044 23:11:26.775314 SW Impedance : PASS
6045 23:11:26.775390 DUTY Scan : NO K
6046 23:11:26.779166 ZQ Calibration : PASS
6047 23:11:26.781979 Jitter Meter : NO K
6048 23:11:26.782064 CBT Training : PASS
6049 23:11:26.785479 Write leveling : PASS
6050 23:11:26.785595 RX DQS gating : PASS
6051 23:11:26.788774 RX DQ/DQS(RDDQC) : PASS
6052 23:11:26.791977 TX DQ/DQS : PASS
6053 23:11:26.792067 RX DATLAT : PASS
6054 23:11:26.795504 RX DQ/DQS(Engine): PASS
6055 23:11:26.798672 TX OE : NO K
6056 23:11:26.798755 All Pass.
6057 23:11:26.798820
6058 23:11:26.798879 CH 0, Rank 1
6059 23:11:26.802129 SW Impedance : PASS
6060 23:11:26.805435 DUTY Scan : NO K
6061 23:11:26.805534 ZQ Calibration : PASS
6062 23:11:26.808683 Jitter Meter : NO K
6063 23:11:26.811899 CBT Training : PASS
6064 23:11:26.812012 Write leveling : PASS
6065 23:11:26.815116 RX DQS gating : PASS
6066 23:11:26.818685 RX DQ/DQS(RDDQC) : PASS
6067 23:11:26.818802 TX DQ/DQS : PASS
6068 23:11:26.821808 RX DATLAT : PASS
6069 23:11:26.825297 RX DQ/DQS(Engine): PASS
6070 23:11:26.825371 TX OE : NO K
6071 23:11:26.828553 All Pass.
6072 23:11:26.828653
6073 23:11:26.828745 CH 1, Rank 0
6074 23:11:26.832002 SW Impedance : PASS
6075 23:11:26.832076 DUTY Scan : NO K
6076 23:11:26.835029 ZQ Calibration : PASS
6077 23:11:26.838729 Jitter Meter : NO K
6078 23:11:26.838827 CBT Training : PASS
6079 23:11:26.841775 Write leveling : PASS
6080 23:11:26.844949 RX DQS gating : PASS
6081 23:11:26.845021 RX DQ/DQS(RDDQC) : PASS
6082 23:11:26.848053 TX DQ/DQS : PASS
6083 23:11:26.848127 RX DATLAT : PASS
6084 23:11:26.851784 RX DQ/DQS(Engine): PASS
6085 23:11:26.854908 TX OE : NO K
6086 23:11:26.854990 All Pass.
6087 23:11:26.855053
6088 23:11:26.855112 CH 1, Rank 1
6089 23:11:26.858053 SW Impedance : PASS
6090 23:11:26.861762 DUTY Scan : NO K
6091 23:11:26.861844 ZQ Calibration : PASS
6092 23:11:26.864711 Jitter Meter : NO K
6093 23:11:26.867930 CBT Training : PASS
6094 23:11:26.868011 Write leveling : PASS
6095 23:11:26.871288 RX DQS gating : PASS
6096 23:11:26.874969 RX DQ/DQS(RDDQC) : PASS
6097 23:11:26.875049 TX DQ/DQS : PASS
6098 23:11:26.878215 RX DATLAT : PASS
6099 23:11:26.881306 RX DQ/DQS(Engine): PASS
6100 23:11:26.881386 TX OE : NO K
6101 23:11:26.884928 All Pass.
6102 23:11:26.885009
6103 23:11:26.885074 DramC Write-DBI off
6104 23:11:26.888014 PER_BANK_REFRESH: Hybrid Mode
6105 23:11:26.888095 TX_TRACKING: ON
6106 23:11:26.898006 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6107 23:11:26.901254 [FAST_K] Save calibration result to emmc
6108 23:11:26.904855 dramc_set_vcore_voltage set vcore to 650000
6109 23:11:26.907944 Read voltage for 400, 6
6110 23:11:26.908025 Vio18 = 0
6111 23:11:26.911281 Vcore = 650000
6112 23:11:26.911363 Vdram = 0
6113 23:11:26.911426 Vddq = 0
6114 23:11:26.911486 Vmddr = 0
6115 23:11:26.918318 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6116 23:11:26.924547 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6117 23:11:26.924629 MEM_TYPE=3, freq_sel=20
6118 23:11:26.928144 sv_algorithm_assistance_LP4_800
6119 23:11:26.931194 ============ PULL DRAM RESETB DOWN ============
6120 23:11:26.938044 ========== PULL DRAM RESETB DOWN end =========
6121 23:11:26.941093 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6122 23:11:26.944581 ===================================
6123 23:11:26.948033 LPDDR4 DRAM CONFIGURATION
6124 23:11:26.951207 ===================================
6125 23:11:26.951290 EX_ROW_EN[0] = 0x0
6126 23:11:26.954356 EX_ROW_EN[1] = 0x0
6127 23:11:26.954437 LP4Y_EN = 0x0
6128 23:11:26.957593 WORK_FSP = 0x0
6129 23:11:26.961233 WL = 0x2
6130 23:11:26.961326 RL = 0x2
6131 23:11:26.964265 BL = 0x2
6132 23:11:26.964346 RPST = 0x0
6133 23:11:26.967413 RD_PRE = 0x0
6134 23:11:26.967498 WR_PRE = 0x1
6135 23:11:26.970986 WR_PST = 0x0
6136 23:11:26.971066 DBI_WR = 0x0
6137 23:11:26.974330 DBI_RD = 0x0
6138 23:11:26.974413 OTF = 0x1
6139 23:11:26.977303 ===================================
6140 23:11:26.980792 ===================================
6141 23:11:26.983942 ANA top config
6142 23:11:26.987661 ===================================
6143 23:11:26.987745 DLL_ASYNC_EN = 0
6144 23:11:26.990646 ALL_SLAVE_EN = 1
6145 23:11:26.994172 NEW_RANK_MODE = 1
6146 23:11:26.997487 DLL_IDLE_MODE = 1
6147 23:11:27.000767 LP45_APHY_COMB_EN = 1
6148 23:11:27.000849 TX_ODT_DIS = 1
6149 23:11:27.004191 NEW_8X_MODE = 1
6150 23:11:27.007445 ===================================
6151 23:11:27.010574 ===================================
6152 23:11:27.013693 data_rate = 800
6153 23:11:27.017022 CKR = 1
6154 23:11:27.020666 DQ_P2S_RATIO = 4
6155 23:11:27.023813 ===================================
6156 23:11:27.023889 CA_P2S_RATIO = 4
6157 23:11:27.027243 DQ_CA_OPEN = 0
6158 23:11:27.030453 DQ_SEMI_OPEN = 1
6159 23:11:27.033786 CA_SEMI_OPEN = 1
6160 23:11:27.036990 CA_FULL_RATE = 0
6161 23:11:27.040112 DQ_CKDIV4_EN = 0
6162 23:11:27.040200 CA_CKDIV4_EN = 1
6163 23:11:27.043542 CA_PREDIV_EN = 0
6164 23:11:27.047024 PH8_DLY = 0
6165 23:11:27.050501 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6166 23:11:27.053377 DQ_AAMCK_DIV = 0
6167 23:11:27.056909 CA_AAMCK_DIV = 0
6168 23:11:27.056993 CA_ADMCK_DIV = 4
6169 23:11:27.060227 DQ_TRACK_CA_EN = 0
6170 23:11:27.063462 CA_PICK = 800
6171 23:11:27.067070 CA_MCKIO = 400
6172 23:11:27.070230 MCKIO_SEMI = 400
6173 23:11:27.073848 PLL_FREQ = 3016
6174 23:11:27.076924 DQ_UI_PI_RATIO = 32
6175 23:11:27.080017 CA_UI_PI_RATIO = 32
6176 23:11:27.083445 ===================================
6177 23:11:27.086653 ===================================
6178 23:11:27.086736 memory_type:LPDDR4
6179 23:11:27.090210 GP_NUM : 10
6180 23:11:27.093378 SRAM_EN : 1
6181 23:11:27.093460 MD32_EN : 0
6182 23:11:27.096504 ===================================
6183 23:11:27.100366 [ANA_INIT] >>>>>>>>>>>>>>
6184 23:11:27.103784 <<<<<< [CONFIGURE PHASE]: ANA_TX
6185 23:11:27.107188 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6186 23:11:27.110057 ===================================
6187 23:11:27.112973 data_rate = 800,PCW = 0X7400
6188 23:11:27.116619 ===================================
6189 23:11:27.119857 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6190 23:11:27.122976 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6191 23:11:27.136568 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6192 23:11:27.139500 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6193 23:11:27.143175 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6194 23:11:27.146080 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6195 23:11:27.149511 [ANA_INIT] flow start
6196 23:11:27.149595 [ANA_INIT] PLL >>>>>>>>
6197 23:11:27.153037 [ANA_INIT] PLL <<<<<<<<
6198 23:11:27.156341 [ANA_INIT] MIDPI >>>>>>>>
6199 23:11:27.159739 [ANA_INIT] MIDPI <<<<<<<<
6200 23:11:27.159821 [ANA_INIT] DLL >>>>>>>>
6201 23:11:27.162690 [ANA_INIT] flow end
6202 23:11:27.166274 ============ LP4 DIFF to SE enter ============
6203 23:11:27.169529 ============ LP4 DIFF to SE exit ============
6204 23:11:27.173120 [ANA_INIT] <<<<<<<<<<<<<
6205 23:11:27.176396 [Flow] Enable top DCM control >>>>>
6206 23:11:27.179170 [Flow] Enable top DCM control <<<<<
6207 23:11:27.182815 Enable DLL master slave shuffle
6208 23:11:27.189516 ==============================================================
6209 23:11:27.189599 Gating Mode config
6210 23:11:27.196241 ==============================================================
6211 23:11:27.196323 Config description:
6212 23:11:27.209480 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6213 23:11:27.212702 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6214 23:11:27.219401 SELPH_MODE 0: By rank 1: By Phase
6215 23:11:27.222779 ==============================================================
6216 23:11:27.225938 GAT_TRACK_EN = 0
6217 23:11:27.229114 RX_GATING_MODE = 2
6218 23:11:27.232735 RX_GATING_TRACK_MODE = 2
6219 23:11:27.235957 SELPH_MODE = 1
6220 23:11:27.239103 PICG_EARLY_EN = 1
6221 23:11:27.242703 VALID_LAT_VALUE = 1
6222 23:11:27.249240 ==============================================================
6223 23:11:27.252730 Enter into Gating configuration >>>>
6224 23:11:27.255787 Exit from Gating configuration <<<<
6225 23:11:27.255871 Enter into DVFS_PRE_config >>>>>
6226 23:11:27.269259 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6227 23:11:27.272625 Exit from DVFS_PRE_config <<<<<
6228 23:11:27.275751 Enter into PICG configuration >>>>
6229 23:11:27.279273 Exit from PICG configuration <<<<
6230 23:11:27.279355 [RX_INPUT] configuration >>>>>
6231 23:11:27.282402 [RX_INPUT] configuration <<<<<
6232 23:11:27.289355 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6233 23:11:27.292495 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6234 23:11:27.299293 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6235 23:11:27.305446 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6236 23:11:27.312333 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6237 23:11:27.319058 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6238 23:11:27.322435 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6239 23:11:27.325424 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6240 23:11:27.332541 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6241 23:11:27.335698 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6242 23:11:27.338856 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6243 23:11:27.342619 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6244 23:11:27.345456 ===================================
6245 23:11:27.349088 LPDDR4 DRAM CONFIGURATION
6246 23:11:27.352012 ===================================
6247 23:11:27.355740 EX_ROW_EN[0] = 0x0
6248 23:11:27.355825 EX_ROW_EN[1] = 0x0
6249 23:11:27.358707 LP4Y_EN = 0x0
6250 23:11:27.358814 WORK_FSP = 0x0
6251 23:11:27.362408 WL = 0x2
6252 23:11:27.362522 RL = 0x2
6253 23:11:27.365240 BL = 0x2
6254 23:11:27.365322 RPST = 0x0
6255 23:11:27.368906 RD_PRE = 0x0
6256 23:11:27.368990 WR_PRE = 0x1
6257 23:11:27.372170 WR_PST = 0x0
6258 23:11:27.372254 DBI_WR = 0x0
6259 23:11:27.375275 DBI_RD = 0x0
6260 23:11:27.375358 OTF = 0x1
6261 23:11:27.378557 ===================================
6262 23:11:27.385186 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6263 23:11:27.388811 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6264 23:11:27.391939 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6265 23:11:27.395210 ===================================
6266 23:11:27.398771 LPDDR4 DRAM CONFIGURATION
6267 23:11:27.401853 ===================================
6268 23:11:27.405054 EX_ROW_EN[0] = 0x10
6269 23:11:27.405137 EX_ROW_EN[1] = 0x0
6270 23:11:27.408358 LP4Y_EN = 0x0
6271 23:11:27.408441 WORK_FSP = 0x0
6272 23:11:27.411503 WL = 0x2
6273 23:11:27.411585 RL = 0x2
6274 23:11:27.415245 BL = 0x2
6275 23:11:27.415327 RPST = 0x0
6276 23:11:27.418306 RD_PRE = 0x0
6277 23:11:27.418386 WR_PRE = 0x1
6278 23:11:27.421442 WR_PST = 0x0
6279 23:11:27.421566 DBI_WR = 0x0
6280 23:11:27.425185 DBI_RD = 0x0
6281 23:11:27.428208 OTF = 0x1
6282 23:11:27.428284 ===================================
6283 23:11:27.434713 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6284 23:11:27.439890 nWR fixed to 30
6285 23:11:27.443368 [ModeRegInit_LP4] CH0 RK0
6286 23:11:27.443460 [ModeRegInit_LP4] CH0 RK1
6287 23:11:27.446507 [ModeRegInit_LP4] CH1 RK0
6288 23:11:27.449916 [ModeRegInit_LP4] CH1 RK1
6289 23:11:27.449999 match AC timing 19
6290 23:11:27.456437 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6291 23:11:27.459875 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6292 23:11:27.463110 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6293 23:11:27.469366 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6294 23:11:27.472880 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6295 23:11:27.472958 ==
6296 23:11:27.476152 Dram Type= 6, Freq= 0, CH_0, rank 0
6297 23:11:27.479598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6298 23:11:27.479694 ==
6299 23:11:27.486147 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6300 23:11:27.492734 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6301 23:11:27.496367 [CA 0] Center 36 (8~64) winsize 57
6302 23:11:27.499395 [CA 1] Center 36 (8~64) winsize 57
6303 23:11:27.502556 [CA 2] Center 36 (8~64) winsize 57
6304 23:11:27.506211 [CA 3] Center 36 (8~64) winsize 57
6305 23:11:27.506293 [CA 4] Center 36 (8~64) winsize 57
6306 23:11:27.509356 [CA 5] Center 36 (8~64) winsize 57
6307 23:11:27.509463
6308 23:11:27.515822 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6309 23:11:27.515904
6310 23:11:27.519670 [CATrainingPosCal] consider 1 rank data
6311 23:11:27.522606 u2DelayCellTimex100 = 270/100 ps
6312 23:11:27.526301 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6313 23:11:27.529361 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6314 23:11:27.532582 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6315 23:11:27.535810 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6316 23:11:27.539310 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6317 23:11:27.542564 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6318 23:11:27.542646
6319 23:11:27.545831 CA PerBit enable=1, Macro0, CA PI delay=36
6320 23:11:27.545912
6321 23:11:27.549015 [CBTSetCACLKResult] CA Dly = 36
6322 23:11:27.552238 CS Dly: 1 (0~32)
6323 23:11:27.552344 ==
6324 23:11:27.555449 Dram Type= 6, Freq= 0, CH_0, rank 1
6325 23:11:27.558922 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6326 23:11:27.559007 ==
6327 23:11:27.565739 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6328 23:11:27.572198 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6329 23:11:27.575828 [CA 0] Center 36 (8~64) winsize 57
6330 23:11:27.575912 [CA 1] Center 36 (8~64) winsize 57
6331 23:11:27.578830 [CA 2] Center 36 (8~64) winsize 57
6332 23:11:27.582198 [CA 3] Center 36 (8~64) winsize 57
6333 23:11:27.585170 [CA 4] Center 36 (8~64) winsize 57
6334 23:11:27.588668 [CA 5] Center 36 (8~64) winsize 57
6335 23:11:27.588751
6336 23:11:27.592012 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6337 23:11:27.592095
6338 23:11:27.598838 [CATrainingPosCal] consider 2 rank data
6339 23:11:27.598923 u2DelayCellTimex100 = 270/100 ps
6340 23:11:27.601882 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6341 23:11:27.608867 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6342 23:11:27.612037 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6343 23:11:27.615557 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6344 23:11:27.618393 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6345 23:11:27.621920 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6346 23:11:27.622003
6347 23:11:27.625251 CA PerBit enable=1, Macro0, CA PI delay=36
6348 23:11:27.625332
6349 23:11:27.628553 [CBTSetCACLKResult] CA Dly = 36
6350 23:11:27.631806 CS Dly: 1 (0~32)
6351 23:11:27.631888
6352 23:11:27.634873 ----->DramcWriteLeveling(PI) begin...
6353 23:11:27.634956 ==
6354 23:11:27.638543 Dram Type= 6, Freq= 0, CH_0, rank 0
6355 23:11:27.641766 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6356 23:11:27.641848 ==
6357 23:11:27.645017 Write leveling (Byte 0): 40 => 8
6358 23:11:27.648525 Write leveling (Byte 1): 32 => 0
6359 23:11:27.651522 DramcWriteLeveling(PI) end<-----
6360 23:11:27.651604
6361 23:11:27.651667 ==
6362 23:11:27.655090 Dram Type= 6, Freq= 0, CH_0, rank 0
6363 23:11:27.658515 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6364 23:11:27.658598 ==
6365 23:11:27.661458 [Gating] SW mode calibration
6366 23:11:27.668372 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6367 23:11:27.674832 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6368 23:11:27.677925 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6369 23:11:27.681617 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6370 23:11:27.687968 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6371 23:11:27.691163 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6372 23:11:27.694677 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6373 23:11:27.701239 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6374 23:11:27.704685 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6375 23:11:27.707715 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6376 23:11:27.714516 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6377 23:11:27.714599 Total UI for P1: 0, mck2ui 16
6378 23:11:27.721247 best dqsien dly found for B0: ( 0, 14, 24)
6379 23:11:27.721328 Total UI for P1: 0, mck2ui 16
6380 23:11:27.727736 best dqsien dly found for B1: ( 0, 14, 24)
6381 23:11:27.731227 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6382 23:11:27.734514 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6383 23:11:27.734597
6384 23:11:27.737912 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6385 23:11:27.741092 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6386 23:11:27.744194 [Gating] SW calibration Done
6387 23:11:27.744277 ==
6388 23:11:27.747928 Dram Type= 6, Freq= 0, CH_0, rank 0
6389 23:11:27.750867 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6390 23:11:27.750949 ==
6391 23:11:27.754173 RX Vref Scan: 0
6392 23:11:27.754254
6393 23:11:27.754318 RX Vref 0 -> 0, step: 1
6394 23:11:27.754378
6395 23:11:27.757422 RX Delay -410 -> 252, step: 16
6396 23:11:27.764218 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6397 23:11:27.767171 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6398 23:11:27.770920 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6399 23:11:27.774407 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6400 23:11:27.780789 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6401 23:11:27.783990 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6402 23:11:27.787201 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6403 23:11:27.790696 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6404 23:11:27.797330 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6405 23:11:27.800488 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6406 23:11:27.803685 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6407 23:11:27.806957 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6408 23:11:27.813693 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6409 23:11:27.817244 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6410 23:11:27.820101 iDelay=230, Bit 14, Center -35 (-298 ~ 229) 528
6411 23:11:27.826769 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6412 23:11:27.826852 ==
6413 23:11:27.830332 Dram Type= 6, Freq= 0, CH_0, rank 0
6414 23:11:27.833428 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6415 23:11:27.833553 ==
6416 23:11:27.833617 DQS Delay:
6417 23:11:27.837205 DQS0 = 59, DQS1 = 59
6418 23:11:27.837287 DQM Delay:
6419 23:11:27.840258 DQM0 = 18, DQM1 = 10
6420 23:11:27.840339 DQ Delay:
6421 23:11:27.843478 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6422 23:11:27.846692 DQ4 =16, DQ5 =0, DQ6 =32, DQ7 =32
6423 23:11:27.849948 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6424 23:11:27.853413 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6425 23:11:27.853553
6426 23:11:27.853626
6427 23:11:27.853686 ==
6428 23:11:27.856722 Dram Type= 6, Freq= 0, CH_0, rank 0
6429 23:11:27.859918 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6430 23:11:27.860000 ==
6431 23:11:27.860064
6432 23:11:27.860123
6433 23:11:27.863121 TX Vref Scan disable
6434 23:11:27.866753 == TX Byte 0 ==
6435 23:11:27.869866 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6436 23:11:27.873253 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6437 23:11:27.873335 == TX Byte 1 ==
6438 23:11:27.879883 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6439 23:11:27.883259 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6440 23:11:27.883341 ==
6441 23:11:27.886351 Dram Type= 6, Freq= 0, CH_0, rank 0
6442 23:11:27.890131 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6443 23:11:27.890213 ==
6444 23:11:27.890280
6445 23:11:27.893127
6446 23:11:27.893208 TX Vref Scan disable
6447 23:11:27.896667 == TX Byte 0 ==
6448 23:11:27.899766 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6449 23:11:27.903104 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6450 23:11:27.906732 == TX Byte 1 ==
6451 23:11:27.910003 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6452 23:11:27.912947 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6453 23:11:27.913029
6454 23:11:27.913093 [DATLAT]
6455 23:11:27.916520 Freq=400, CH0 RK0
6456 23:11:27.916601
6457 23:11:27.919811 DATLAT Default: 0xf
6458 23:11:27.919891 0, 0xFFFF, sum = 0
6459 23:11:27.922965 1, 0xFFFF, sum = 0
6460 23:11:27.923048 2, 0xFFFF, sum = 0
6461 23:11:27.926008 3, 0xFFFF, sum = 0
6462 23:11:27.926110 4, 0xFFFF, sum = 0
6463 23:11:27.929401 5, 0xFFFF, sum = 0
6464 23:11:27.929511 6, 0xFFFF, sum = 0
6465 23:11:27.932875 7, 0xFFFF, sum = 0
6466 23:11:27.932957 8, 0xFFFF, sum = 0
6467 23:11:27.936200 9, 0xFFFF, sum = 0
6468 23:11:27.936282 10, 0xFFFF, sum = 0
6469 23:11:27.939913 11, 0xFFFF, sum = 0
6470 23:11:27.939995 12, 0xFFFF, sum = 0
6471 23:11:27.942913 13, 0x0, sum = 1
6472 23:11:27.942995 14, 0x0, sum = 2
6473 23:11:27.946628 15, 0x0, sum = 3
6474 23:11:27.946710 16, 0x0, sum = 4
6475 23:11:27.949391 best_step = 14
6476 23:11:27.949534
6477 23:11:27.949600 ==
6478 23:11:27.952717 Dram Type= 6, Freq= 0, CH_0, rank 0
6479 23:11:27.956410 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6480 23:11:27.956492 ==
6481 23:11:27.959564 RX Vref Scan: 1
6482 23:11:27.959644
6483 23:11:27.959707 RX Vref 0 -> 0, step: 1
6484 23:11:27.959767
6485 23:11:27.962657 RX Delay -359 -> 252, step: 8
6486 23:11:27.962738
6487 23:11:27.966308 Set Vref, RX VrefLevel [Byte0]: 62
6488 23:11:27.969470 [Byte1]: 47
6489 23:11:27.974214
6490 23:11:27.974296 Final RX Vref Byte 0 = 62 to rank0
6491 23:11:27.977409 Final RX Vref Byte 1 = 47 to rank0
6492 23:11:27.980432 Final RX Vref Byte 0 = 62 to rank1
6493 23:11:27.983803 Final RX Vref Byte 1 = 47 to rank1==
6494 23:11:27.987307 Dram Type= 6, Freq= 0, CH_0, rank 0
6495 23:11:27.993808 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6496 23:11:27.993890 ==
6497 23:11:27.993954 DQS Delay:
6498 23:11:27.997420 DQS0 = 60, DQS1 = 68
6499 23:11:27.997556 DQM Delay:
6500 23:11:27.997621 DQM0 = 15, DQM1 = 14
6501 23:11:28.000632 DQ Delay:
6502 23:11:28.004298 DQ0 =16, DQ1 =16, DQ2 =12, DQ3 =12
6503 23:11:28.007238 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6504 23:11:28.007319 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6505 23:11:28.010350 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6506 23:11:28.013945
6507 23:11:28.014026
6508 23:11:28.020476 [DQSOSCAuto] RK0, (LSB)MR18= 0x8180, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
6509 23:11:28.023580 CH0 RK0: MR19=C0C, MR18=8180
6510 23:11:28.030204 CH0_RK0: MR19=0xC0C, MR18=0x8180, DQSOSC=393, MR23=63, INC=382, DEC=254
6511 23:11:28.030306 ==
6512 23:11:28.033747 Dram Type= 6, Freq= 0, CH_0, rank 1
6513 23:11:28.037058 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6514 23:11:28.037141 ==
6515 23:11:28.040176 [Gating] SW mode calibration
6516 23:11:28.047086 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6517 23:11:28.053480 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6518 23:11:28.056989 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6519 23:11:28.060016 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6520 23:11:28.066961 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6521 23:11:28.070180 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6522 23:11:28.073279 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6523 23:11:28.079789 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6524 23:11:28.083445 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6525 23:11:28.086586 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6526 23:11:28.093371 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6527 23:11:28.093453 Total UI for P1: 0, mck2ui 16
6528 23:11:28.100133 best dqsien dly found for B0: ( 0, 14, 24)
6529 23:11:28.100216 Total UI for P1: 0, mck2ui 16
6530 23:11:28.103200 best dqsien dly found for B1: ( 0, 14, 24)
6531 23:11:28.109905 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6532 23:11:28.112879 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6533 23:11:28.112960
6534 23:11:28.116595 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6535 23:11:28.119843 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6536 23:11:28.122876 [Gating] SW calibration Done
6537 23:11:28.122957 ==
6538 23:11:28.126627 Dram Type= 6, Freq= 0, CH_0, rank 1
6539 23:11:28.129765 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6540 23:11:28.129847 ==
6541 23:11:28.133322 RX Vref Scan: 0
6542 23:11:28.133403
6543 23:11:28.133467 RX Vref 0 -> 0, step: 1
6544 23:11:28.133567
6545 23:11:28.136377 RX Delay -410 -> 252, step: 16
6546 23:11:28.143205 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6547 23:11:28.146113 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6548 23:11:28.149728 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6549 23:11:28.152841 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6550 23:11:28.159608 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6551 23:11:28.163182 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6552 23:11:28.166036 iDelay=230, Bit 6, Center -35 (-298 ~ 229) 528
6553 23:11:28.169570 iDelay=230, Bit 7, Center -35 (-298 ~ 229) 528
6554 23:11:28.175977 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6555 23:11:28.179703 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6556 23:11:28.182898 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6557 23:11:28.186257 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6558 23:11:28.192850 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6559 23:11:28.195956 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6560 23:11:28.199224 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6561 23:11:28.202798 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6562 23:11:28.206300 ==
6563 23:11:28.209379 Dram Type= 6, Freq= 0, CH_0, rank 1
6564 23:11:28.212391 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6565 23:11:28.212487 ==
6566 23:11:28.212554 DQS Delay:
6567 23:11:28.216164 DQS0 = 59, DQS1 = 59
6568 23:11:28.216245 DQM Delay:
6569 23:11:28.219229 DQM0 = 16, DQM1 = 10
6570 23:11:28.219310 DQ Delay:
6571 23:11:28.222394 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6572 23:11:28.225631 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6573 23:11:28.229377 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6574 23:11:28.232337 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6575 23:11:28.232418
6576 23:11:28.232481
6577 23:11:28.232540 ==
6578 23:11:28.235722 Dram Type= 6, Freq= 0, CH_0, rank 1
6579 23:11:28.238954 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6580 23:11:28.239037 ==
6581 23:11:28.239101
6582 23:11:28.239161
6583 23:11:28.242224 TX Vref Scan disable
6584 23:11:28.242305 == TX Byte 0 ==
6585 23:11:28.248617 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6586 23:11:28.252222 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6587 23:11:28.252303 == TX Byte 1 ==
6588 23:11:28.258858 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6589 23:11:28.262010 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6590 23:11:28.262094 ==
6591 23:11:28.265594 Dram Type= 6, Freq= 0, CH_0, rank 1
6592 23:11:28.268787 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6593 23:11:28.268869 ==
6594 23:11:28.268934
6595 23:11:28.268993
6596 23:11:28.272224 TX Vref Scan disable
6597 23:11:28.275478 == TX Byte 0 ==
6598 23:11:28.278623 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6599 23:11:28.282115 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6600 23:11:28.282197 == TX Byte 1 ==
6601 23:11:28.288420 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6602 23:11:28.291660 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6603 23:11:28.291743
6604 23:11:28.291806 [DATLAT]
6605 23:11:28.295425 Freq=400, CH0 RK1
6606 23:11:28.295507
6607 23:11:28.295571 DATLAT Default: 0xe
6608 23:11:28.298543 0, 0xFFFF, sum = 0
6609 23:11:28.298626 1, 0xFFFF, sum = 0
6610 23:11:28.301662 2, 0xFFFF, sum = 0
6611 23:11:28.301744 3, 0xFFFF, sum = 0
6612 23:11:28.305415 4, 0xFFFF, sum = 0
6613 23:11:28.305504 5, 0xFFFF, sum = 0
6614 23:11:28.308665 6, 0xFFFF, sum = 0
6615 23:11:28.311800 7, 0xFFFF, sum = 0
6616 23:11:28.311883 8, 0xFFFF, sum = 0
6617 23:11:28.315107 9, 0xFFFF, sum = 0
6618 23:11:28.315189 10, 0xFFFF, sum = 0
6619 23:11:28.318282 11, 0xFFFF, sum = 0
6620 23:11:28.318365 12, 0xFFFF, sum = 0
6621 23:11:28.321901 13, 0x0, sum = 1
6622 23:11:28.321983 14, 0x0, sum = 2
6623 23:11:28.325017 15, 0x0, sum = 3
6624 23:11:28.325099 16, 0x0, sum = 4
6625 23:11:28.325165 best_step = 14
6626 23:11:28.328424
6627 23:11:28.328505 ==
6628 23:11:28.331800 Dram Type= 6, Freq= 0, CH_0, rank 1
6629 23:11:28.335179 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6630 23:11:28.335261 ==
6631 23:11:28.335326 RX Vref Scan: 0
6632 23:11:28.335385
6633 23:11:28.338326 RX Vref 0 -> 0, step: 1
6634 23:11:28.338407
6635 23:11:28.341669 RX Delay -359 -> 252, step: 8
6636 23:11:28.349151 iDelay=217, Bit 0, Center -52 (-303 ~ 200) 504
6637 23:11:28.352251 iDelay=217, Bit 1, Center -44 (-295 ~ 208) 504
6638 23:11:28.355464 iDelay=217, Bit 2, Center -52 (-303 ~ 200) 504
6639 23:11:28.358732 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6640 23:11:28.365649 iDelay=217, Bit 4, Center -52 (-303 ~ 200) 504
6641 23:11:28.368805 iDelay=217, Bit 5, Center -60 (-311 ~ 192) 504
6642 23:11:28.371971 iDelay=217, Bit 6, Center -40 (-295 ~ 216) 512
6643 23:11:28.378786 iDelay=217, Bit 7, Center -36 (-287 ~ 216) 504
6644 23:11:28.382146 iDelay=217, Bit 8, Center -64 (-311 ~ 184) 496
6645 23:11:28.385370 iDelay=217, Bit 9, Center -68 (-311 ~ 176) 488
6646 23:11:28.388615 iDelay=217, Bit 10, Center -52 (-303 ~ 200) 504
6647 23:11:28.395393 iDelay=217, Bit 11, Center -64 (-311 ~ 184) 496
6648 23:11:28.398637 iDelay=217, Bit 12, Center -48 (-295 ~ 200) 496
6649 23:11:28.401724 iDelay=217, Bit 13, Center -48 (-295 ~ 200) 496
6650 23:11:28.405445 iDelay=217, Bit 14, Center -48 (-295 ~ 200) 496
6651 23:11:28.411865 iDelay=217, Bit 15, Center -48 (-295 ~ 200) 496
6652 23:11:28.411949 ==
6653 23:11:28.414978 Dram Type= 6, Freq= 0, CH_0, rank 1
6654 23:11:28.418656 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6655 23:11:28.418739 ==
6656 23:11:28.418806 DQS Delay:
6657 23:11:28.421774 DQS0 = 60, DQS1 = 68
6658 23:11:28.421857 DQM Delay:
6659 23:11:28.425206 DQM0 = 11, DQM1 = 13
6660 23:11:28.425305 DQ Delay:
6661 23:11:28.428470 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6662 23:11:28.431999 DQ4 =8, DQ5 =0, DQ6 =20, DQ7 =24
6663 23:11:28.435336 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =4
6664 23:11:28.438406 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
6665 23:11:28.438488
6666 23:11:28.438553
6667 23:11:28.444839 [DQSOSCAuto] RK1, (LSB)MR18= 0xc87d, (MSB)MR19= 0xc0c, tDQSOscB0 = 394 ps tDQSOscB1 = 385 ps
6668 23:11:28.448540 CH0 RK1: MR19=C0C, MR18=C87D
6669 23:11:28.455217 CH0_RK1: MR19=0xC0C, MR18=0xC87D, DQSOSC=385, MR23=63, INC=398, DEC=265
6670 23:11:28.458597 [RxdqsGatingPostProcess] freq 400
6671 23:11:28.464859 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6672 23:11:28.464946 best DQS0 dly(2T, 0.5T) = (0, 10)
6673 23:11:28.468624 best DQS1 dly(2T, 0.5T) = (0, 10)
6674 23:11:28.471839 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6675 23:11:28.474895 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6676 23:11:28.478592 best DQS0 dly(2T, 0.5T) = (0, 10)
6677 23:11:28.481775 best DQS1 dly(2T, 0.5T) = (0, 10)
6678 23:11:28.484715 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6679 23:11:28.488116 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6680 23:11:28.491579 Pre-setting of DQS Precalculation
6681 23:11:28.498222 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6682 23:11:28.498305 ==
6683 23:11:28.501399 Dram Type= 6, Freq= 0, CH_1, rank 0
6684 23:11:28.505045 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6685 23:11:28.505126 ==
6686 23:11:28.511392 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6687 23:11:28.515160 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6688 23:11:28.518282 [CA 0] Center 36 (8~64) winsize 57
6689 23:11:28.521383 [CA 1] Center 36 (8~64) winsize 57
6690 23:11:28.525053 [CA 2] Center 36 (8~64) winsize 57
6691 23:11:28.528197 [CA 3] Center 36 (8~64) winsize 57
6692 23:11:28.531105 [CA 4] Center 36 (8~64) winsize 57
6693 23:11:28.534852 [CA 5] Center 36 (8~64) winsize 57
6694 23:11:28.534934
6695 23:11:28.537845 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6696 23:11:28.537927
6697 23:11:28.541214 [CATrainingPosCal] consider 1 rank data
6698 23:11:28.544346 u2DelayCellTimex100 = 270/100 ps
6699 23:11:28.547723 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6700 23:11:28.551126 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6701 23:11:28.554713 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6702 23:11:28.561201 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6703 23:11:28.564560 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6704 23:11:28.567663 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6705 23:11:28.567745
6706 23:11:28.571370 CA PerBit enable=1, Macro0, CA PI delay=36
6707 23:11:28.571452
6708 23:11:28.574416 [CBTSetCACLKResult] CA Dly = 36
6709 23:11:28.574497 CS Dly: 1 (0~32)
6710 23:11:28.574562 ==
6711 23:11:28.577610 Dram Type= 6, Freq= 0, CH_1, rank 1
6712 23:11:28.584260 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6713 23:11:28.584343 ==
6714 23:11:28.587606 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6715 23:11:28.594559 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6716 23:11:28.597807 [CA 0] Center 36 (8~64) winsize 57
6717 23:11:28.600901 [CA 1] Center 36 (8~64) winsize 57
6718 23:11:28.604085 [CA 2] Center 36 (8~64) winsize 57
6719 23:11:28.607346 [CA 3] Center 36 (8~64) winsize 57
6720 23:11:28.610896 [CA 4] Center 36 (8~64) winsize 57
6721 23:11:28.614032 [CA 5] Center 36 (8~64) winsize 57
6722 23:11:28.614114
6723 23:11:28.617817 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6724 23:11:28.617898
6725 23:11:28.620916 [CATrainingPosCal] consider 2 rank data
6726 23:11:28.623953 u2DelayCellTimex100 = 270/100 ps
6727 23:11:28.627191 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6728 23:11:28.630398 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6729 23:11:28.633977 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6730 23:11:28.637020 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6731 23:11:28.640771 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6732 23:11:28.647181 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6733 23:11:28.647264
6734 23:11:28.650212 CA PerBit enable=1, Macro0, CA PI delay=36
6735 23:11:28.650294
6736 23:11:28.653691 [CBTSetCACLKResult] CA Dly = 36
6737 23:11:28.653775 CS Dly: 1 (0~32)
6738 23:11:28.653841
6739 23:11:28.657249 ----->DramcWriteLeveling(PI) begin...
6740 23:11:28.657359 ==
6741 23:11:28.660431 Dram Type= 6, Freq= 0, CH_1, rank 0
6742 23:11:28.667267 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6743 23:11:28.667356 ==
6744 23:11:28.670456 Write leveling (Byte 0): 40 => 8
6745 23:11:28.670539 Write leveling (Byte 1): 40 => 8
6746 23:11:28.673455 DramcWriteLeveling(PI) end<-----
6747 23:11:28.673547
6748 23:11:28.673612 ==
6749 23:11:28.676667 Dram Type= 6, Freq= 0, CH_1, rank 0
6750 23:11:28.683564 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6751 23:11:28.683646 ==
6752 23:11:28.687213 [Gating] SW mode calibration
6753 23:11:28.693308 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6754 23:11:28.696558 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6755 23:11:28.703254 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6756 23:11:28.706860 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6757 23:11:28.710098 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6758 23:11:28.716959 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6759 23:11:28.720559 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6760 23:11:28.723709 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6761 23:11:28.726856 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6762 23:11:28.733328 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6763 23:11:28.736500 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6764 23:11:28.740197 Total UI for P1: 0, mck2ui 16
6765 23:11:28.743005 best dqsien dly found for B0: ( 0, 14, 24)
6766 23:11:28.746581 Total UI for P1: 0, mck2ui 16
6767 23:11:28.750547 best dqsien dly found for B1: ( 0, 14, 24)
6768 23:11:28.753406 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6769 23:11:28.756495 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6770 23:11:28.756576
6771 23:11:28.760098 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6772 23:11:28.766695 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6773 23:11:28.766778 [Gating] SW calibration Done
6774 23:11:28.766843 ==
6775 23:11:28.769793 Dram Type= 6, Freq= 0, CH_1, rank 0
6776 23:11:28.776925 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6777 23:11:28.777009 ==
6778 23:11:28.777075 RX Vref Scan: 0
6779 23:11:28.777136
6780 23:11:28.779971 RX Vref 0 -> 0, step: 1
6781 23:11:28.780052
6782 23:11:28.783205 RX Delay -410 -> 252, step: 16
6783 23:11:28.786467 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6784 23:11:28.789482 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6785 23:11:28.796377 iDelay=230, Bit 2, Center -51 (-314 ~ 213) 528
6786 23:11:28.799592 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6787 23:11:28.802859 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6788 23:11:28.806291 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6789 23:11:28.812683 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6790 23:11:28.816067 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6791 23:11:28.819593 iDelay=230, Bit 8, Center -67 (-330 ~ 197) 528
6792 23:11:28.822946 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6793 23:11:28.829694 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6794 23:11:28.832763 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6795 23:11:28.835899 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6796 23:11:28.839678 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6797 23:11:28.846261 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6798 23:11:28.849209 iDelay=230, Bit 15, Center -35 (-298 ~ 229) 528
6799 23:11:28.849290 ==
6800 23:11:28.852871 Dram Type= 6, Freq= 0, CH_1, rank 0
6801 23:11:28.855890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6802 23:11:28.855973 ==
6803 23:11:28.859380 DQS Delay:
6804 23:11:28.859462 DQS0 = 51, DQS1 = 67
6805 23:11:28.862537 DQM Delay:
6806 23:11:28.862619 DQM0 = 13, DQM1 = 18
6807 23:11:28.862684 DQ Delay:
6808 23:11:28.866096 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =8
6809 23:11:28.869147 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6810 23:11:28.872493 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6811 23:11:28.876049 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =32
6812 23:11:28.876132
6813 23:11:28.876196
6814 23:11:28.876255 ==
6815 23:11:28.879235 Dram Type= 6, Freq= 0, CH_1, rank 0
6816 23:11:28.885676 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6817 23:11:28.885759 ==
6818 23:11:28.885825
6819 23:11:28.885884
6820 23:11:28.885941 TX Vref Scan disable
6821 23:11:28.889260 == TX Byte 0 ==
6822 23:11:28.892460 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6823 23:11:28.895950 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6824 23:11:28.899180 == TX Byte 1 ==
6825 23:11:28.902405 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6826 23:11:28.905419 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6827 23:11:28.905537 ==
6828 23:11:28.909222 Dram Type= 6, Freq= 0, CH_1, rank 0
6829 23:11:28.915425 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6830 23:11:28.915509 ==
6831 23:11:28.915573
6832 23:11:28.915632
6833 23:11:28.919059 TX Vref Scan disable
6834 23:11:28.919140 == TX Byte 0 ==
6835 23:11:28.922438 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6836 23:11:28.925591 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6837 23:11:28.928637 == TX Byte 1 ==
6838 23:11:28.931991 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6839 23:11:28.935236 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6840 23:11:28.938896
6841 23:11:28.938978 [DATLAT]
6842 23:11:28.939042 Freq=400, CH1 RK0
6843 23:11:28.939101
6844 23:11:28.942240 DATLAT Default: 0xf
6845 23:11:28.942321 0, 0xFFFF, sum = 0
6846 23:11:28.945607 1, 0xFFFF, sum = 0
6847 23:11:28.945690 2, 0xFFFF, sum = 0
6848 23:11:28.948621 3, 0xFFFF, sum = 0
6849 23:11:28.948703 4, 0xFFFF, sum = 0
6850 23:11:28.951677 5, 0xFFFF, sum = 0
6851 23:11:28.955407 6, 0xFFFF, sum = 0
6852 23:11:28.955490 7, 0xFFFF, sum = 0
6853 23:11:28.958556 8, 0xFFFF, sum = 0
6854 23:11:28.958639 9, 0xFFFF, sum = 0
6855 23:11:28.962247 10, 0xFFFF, sum = 0
6856 23:11:28.962329 11, 0xFFFF, sum = 0
6857 23:11:28.965760 12, 0xFFFF, sum = 0
6858 23:11:28.965843 13, 0x0, sum = 1
6859 23:11:28.968658 14, 0x0, sum = 2
6860 23:11:28.968740 15, 0x0, sum = 3
6861 23:11:28.972046 16, 0x0, sum = 4
6862 23:11:28.972170 best_step = 14
6863 23:11:28.972317
6864 23:11:28.972382 ==
6865 23:11:28.975036 Dram Type= 6, Freq= 0, CH_1, rank 0
6866 23:11:28.978415 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6867 23:11:28.978496 ==
6868 23:11:28.981631 RX Vref Scan: 1
6869 23:11:28.981711
6870 23:11:28.984945 RX Vref 0 -> 0, step: 1
6871 23:11:28.985026
6872 23:11:28.985090 RX Delay -375 -> 252, step: 8
6873 23:11:28.988537
6874 23:11:28.988617 Set Vref, RX VrefLevel [Byte0]: 50
6875 23:11:28.991939 [Byte1]: 53
6876 23:11:28.997500
6877 23:11:28.997581 Final RX Vref Byte 0 = 50 to rank0
6878 23:11:29.000727 Final RX Vref Byte 1 = 53 to rank0
6879 23:11:29.003901 Final RX Vref Byte 0 = 50 to rank1
6880 23:11:29.007422 Final RX Vref Byte 1 = 53 to rank1==
6881 23:11:29.010568 Dram Type= 6, Freq= 0, CH_1, rank 0
6882 23:11:29.017329 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6883 23:11:29.017437 ==
6884 23:11:29.017558 DQS Delay:
6885 23:11:29.020548 DQS0 = 56, DQS1 = 64
6886 23:11:29.020629 DQM Delay:
6887 23:11:29.020694 DQM0 = 12, DQM1 = 10
6888 23:11:29.024031 DQ Delay:
6889 23:11:29.027154 DQ0 =20, DQ1 =4, DQ2 =0, DQ3 =12
6890 23:11:29.027237 DQ4 =12, DQ5 =20, DQ6 =24, DQ7 =8
6891 23:11:29.030907 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6892 23:11:29.034041 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =16
6893 23:11:29.034122
6894 23:11:29.037214
6895 23:11:29.044027 [DQSOSCAuto] RK0, (LSB)MR18= 0x5e71, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 397 ps
6896 23:11:29.047368 CH1 RK0: MR19=C0C, MR18=5E71
6897 23:11:29.053870 CH1_RK0: MR19=0xC0C, MR18=0x5E71, DQSOSC=395, MR23=63, INC=378, DEC=252
6898 23:11:29.053952 ==
6899 23:11:29.057214 Dram Type= 6, Freq= 0, CH_1, rank 1
6900 23:11:29.060408 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6901 23:11:29.060490 ==
6902 23:11:29.064083 [Gating] SW mode calibration
6903 23:11:29.070354 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6904 23:11:29.077346 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6905 23:11:29.080205 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6906 23:11:29.083844 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6907 23:11:29.090557 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6908 23:11:29.093776 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6909 23:11:29.097212 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6910 23:11:29.100671 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6911 23:11:29.107002 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6912 23:11:29.110761 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6913 23:11:29.113849 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6914 23:11:29.117055 Total UI for P1: 0, mck2ui 16
6915 23:11:29.120687 best dqsien dly found for B0: ( 0, 14, 24)
6916 23:11:29.123647 Total UI for P1: 0, mck2ui 16
6917 23:11:29.127059 best dqsien dly found for B1: ( 0, 14, 24)
6918 23:11:29.130173 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6919 23:11:29.133645 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6920 23:11:29.137300
6921 23:11:29.140588 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6922 23:11:29.143586 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6923 23:11:29.146882 [Gating] SW calibration Done
6924 23:11:29.146962 ==
6925 23:11:29.150050 Dram Type= 6, Freq= 0, CH_1, rank 1
6926 23:11:29.153676 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6927 23:11:29.153758 ==
6928 23:11:29.153823 RX Vref Scan: 0
6929 23:11:29.156586
6930 23:11:29.156667 RX Vref 0 -> 0, step: 1
6931 23:11:29.156751
6932 23:11:29.160075 RX Delay -410 -> 252, step: 16
6933 23:11:29.163501 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6934 23:11:29.170256 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6935 23:11:29.173567 iDelay=230, Bit 2, Center -59 (-314 ~ 197) 512
6936 23:11:29.176806 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6937 23:11:29.179913 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6938 23:11:29.186410 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6939 23:11:29.189852 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6940 23:11:29.193460 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6941 23:11:29.196799 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6942 23:11:29.203030 iDelay=230, Bit 9, Center -51 (-314 ~ 213) 528
6943 23:11:29.206329 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6944 23:11:29.210032 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6945 23:11:29.216162 iDelay=230, Bit 12, Center -35 (-298 ~ 229) 528
6946 23:11:29.219938 iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528
6947 23:11:29.223088 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6948 23:11:29.226185 iDelay=230, Bit 15, Center -35 (-298 ~ 229) 528
6949 23:11:29.226266 ==
6950 23:11:29.229323 Dram Type= 6, Freq= 0, CH_1, rank 1
6951 23:11:29.236011 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6952 23:11:29.236093 ==
6953 23:11:29.236158 DQS Delay:
6954 23:11:29.239410 DQS0 = 59, DQS1 = 59
6955 23:11:29.239492 DQM Delay:
6956 23:11:29.243060 DQM0 = 19, DQM1 = 15
6957 23:11:29.243141 DQ Delay:
6958 23:11:29.245820 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6959 23:11:29.249006 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6960 23:11:29.252607 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6961 23:11:29.255577 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =24
6962 23:11:29.255658
6963 23:11:29.255748
6964 23:11:29.255841 ==
6965 23:11:29.258935 Dram Type= 6, Freq= 0, CH_1, rank 1
6966 23:11:29.262683 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6967 23:11:29.262766 ==
6968 23:11:29.262831
6969 23:11:29.262890
6970 23:11:29.265862 TX Vref Scan disable
6971 23:11:29.265943 == TX Byte 0 ==
6972 23:11:29.272164 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6973 23:11:29.275874 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6974 23:11:29.275957 == TX Byte 1 ==
6975 23:11:29.282039 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6976 23:11:29.285859 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6977 23:11:29.285945 ==
6978 23:11:29.289055 Dram Type= 6, Freq= 0, CH_1, rank 1
6979 23:11:29.292362 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6980 23:11:29.292443 ==
6981 23:11:29.292558
6982 23:11:29.292619
6983 23:11:29.295273 TX Vref Scan disable
6984 23:11:29.295354 == TX Byte 0 ==
6985 23:11:29.302093 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6986 23:11:29.305401 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6987 23:11:29.305489 == TX Byte 1 ==
6988 23:11:29.311895 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6989 23:11:29.315154 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6990 23:11:29.315236
6991 23:11:29.315300 [DATLAT]
6992 23:11:29.318397 Freq=400, CH1 RK1
6993 23:11:29.318478
6994 23:11:29.318542 DATLAT Default: 0xe
6995 23:11:29.321926 0, 0xFFFF, sum = 0
6996 23:11:29.322009 1, 0xFFFF, sum = 0
6997 23:11:29.325119 2, 0xFFFF, sum = 0
6998 23:11:29.325201 3, 0xFFFF, sum = 0
6999 23:11:29.328828 4, 0xFFFF, sum = 0
7000 23:11:29.328910 5, 0xFFFF, sum = 0
7001 23:11:29.331824 6, 0xFFFF, sum = 0
7002 23:11:29.335062 7, 0xFFFF, sum = 0
7003 23:11:29.335144 8, 0xFFFF, sum = 0
7004 23:11:29.338742 9, 0xFFFF, sum = 0
7005 23:11:29.338824 10, 0xFFFF, sum = 0
7006 23:11:29.341873 11, 0xFFFF, sum = 0
7007 23:11:29.341956 12, 0xFFFF, sum = 0
7008 23:11:29.344739 13, 0x0, sum = 1
7009 23:11:29.344821 14, 0x0, sum = 2
7010 23:11:29.348212 15, 0x0, sum = 3
7011 23:11:29.348294 16, 0x0, sum = 4
7012 23:11:29.351413 best_step = 14
7013 23:11:29.351494
7014 23:11:29.351558 ==
7015 23:11:29.355135 Dram Type= 6, Freq= 0, CH_1, rank 1
7016 23:11:29.358159 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7017 23:11:29.358242 ==
7018 23:11:29.358307 RX Vref Scan: 0
7019 23:11:29.361280
7020 23:11:29.361361 RX Vref 0 -> 0, step: 1
7021 23:11:29.361425
7022 23:11:29.364837 RX Delay -359 -> 252, step: 8
7023 23:11:29.371882 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
7024 23:11:29.375293 iDelay=217, Bit 1, Center -52 (-303 ~ 200) 504
7025 23:11:29.378779 iDelay=217, Bit 2, Center -60 (-311 ~ 192) 504
7026 23:11:29.385469 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
7027 23:11:29.388489 iDelay=217, Bit 4, Center -44 (-295 ~ 208) 504
7028 23:11:29.392117 iDelay=217, Bit 5, Center -36 (-287 ~ 216) 504
7029 23:11:29.395500 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
7030 23:11:29.401927 iDelay=217, Bit 7, Center -52 (-303 ~ 200) 504
7031 23:11:29.405211 iDelay=217, Bit 8, Center -64 (-319 ~ 192) 512
7032 23:11:29.408532 iDelay=217, Bit 9, Center -64 (-319 ~ 192) 512
7033 23:11:29.412214 iDelay=217, Bit 10, Center -48 (-303 ~ 208) 512
7034 23:11:29.418843 iDelay=217, Bit 11, Center -64 (-319 ~ 192) 512
7035 23:11:29.421982 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
7036 23:11:29.425158 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
7037 23:11:29.428422 iDelay=217, Bit 14, Center -48 (-303 ~ 208) 512
7038 23:11:29.435286 iDelay=217, Bit 15, Center -48 (-303 ~ 208) 512
7039 23:11:29.435369 ==
7040 23:11:29.438468 Dram Type= 6, Freq= 0, CH_1, rank 1
7041 23:11:29.441726 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7042 23:11:29.441809 ==
7043 23:11:29.441874 DQS Delay:
7044 23:11:29.444797 DQS0 = 60, DQS1 = 64
7045 23:11:29.444879 DQM Delay:
7046 23:11:29.448192 DQM0 = 13, DQM1 = 10
7047 23:11:29.448273 DQ Delay:
7048 23:11:29.451587 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
7049 23:11:29.454881 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =8
7050 23:11:29.458046 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
7051 23:11:29.461732 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
7052 23:11:29.461815
7053 23:11:29.461879
7054 23:11:29.468364 [DQSOSCAuto] RK1, (LSB)MR18= 0x73a4, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 395 ps
7055 23:11:29.471215 CH1 RK1: MR19=C0C, MR18=73A4
7056 23:11:29.477774 CH1_RK1: MR19=0xC0C, MR18=0x73A4, DQSOSC=389, MR23=63, INC=390, DEC=260
7057 23:11:29.481303 [RxdqsGatingPostProcess] freq 400
7058 23:11:29.488326 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7059 23:11:29.491717 best DQS0 dly(2T, 0.5T) = (0, 10)
7060 23:11:29.494802 best DQS1 dly(2T, 0.5T) = (0, 10)
7061 23:11:29.498182 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7062 23:11:29.498263 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7063 23:11:29.501212 best DQS0 dly(2T, 0.5T) = (0, 10)
7064 23:11:29.504408 best DQS1 dly(2T, 0.5T) = (0, 10)
7065 23:11:29.507943 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7066 23:11:29.511047 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7067 23:11:29.514666 Pre-setting of DQS Precalculation
7068 23:11:29.520893 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7069 23:11:29.527680 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7070 23:11:29.534234 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7071 23:11:29.534321
7072 23:11:29.534386
7073 23:11:29.537481 [Calibration Summary] 800 Mbps
7074 23:11:29.537564 CH 0, Rank 0
7075 23:11:29.540703 SW Impedance : PASS
7076 23:11:29.544289 DUTY Scan : NO K
7077 23:11:29.544372 ZQ Calibration : PASS
7078 23:11:29.547544 Jitter Meter : NO K
7079 23:11:29.550736 CBT Training : PASS
7080 23:11:29.550819 Write leveling : PASS
7081 23:11:29.554254 RX DQS gating : PASS
7082 23:11:29.557277 RX DQ/DQS(RDDQC) : PASS
7083 23:11:29.557359 TX DQ/DQS : PASS
7084 23:11:29.560563 RX DATLAT : PASS
7085 23:11:29.563854 RX DQ/DQS(Engine): PASS
7086 23:11:29.563937 TX OE : NO K
7087 23:11:29.564004 All Pass.
7088 23:11:29.567509
7089 23:11:29.567591 CH 0, Rank 1
7090 23:11:29.570775 SW Impedance : PASS
7091 23:11:29.570859 DUTY Scan : NO K
7092 23:11:29.573921 ZQ Calibration : PASS
7093 23:11:29.577382 Jitter Meter : NO K
7094 23:11:29.577465 CBT Training : PASS
7095 23:11:29.580651 Write leveling : NO K
7096 23:11:29.580734 RX DQS gating : PASS
7097 23:11:29.584226 RX DQ/DQS(RDDQC) : PASS
7098 23:11:29.587375 TX DQ/DQS : PASS
7099 23:11:29.587459 RX DATLAT : PASS
7100 23:11:29.590518 RX DQ/DQS(Engine): PASS
7101 23:11:29.593995 TX OE : NO K
7102 23:11:29.594078 All Pass.
7103 23:11:29.594144
7104 23:11:29.594204 CH 1, Rank 0
7105 23:11:29.597306 SW Impedance : PASS
7106 23:11:29.600579 DUTY Scan : NO K
7107 23:11:29.600661 ZQ Calibration : PASS
7108 23:11:29.604202 Jitter Meter : NO K
7109 23:11:29.607232 CBT Training : PASS
7110 23:11:29.607315 Write leveling : PASS
7111 23:11:29.610324 RX DQS gating : PASS
7112 23:11:29.613836 RX DQ/DQS(RDDQC) : PASS
7113 23:11:29.613919 TX DQ/DQS : PASS
7114 23:11:29.617064 RX DATLAT : PASS
7115 23:11:29.620217 RX DQ/DQS(Engine): PASS
7116 23:11:29.620299 TX OE : NO K
7117 23:11:29.620365 All Pass.
7118 23:11:29.623498
7119 23:11:29.623580 CH 1, Rank 1
7120 23:11:29.626895 SW Impedance : PASS
7121 23:11:29.626977 DUTY Scan : NO K
7122 23:11:29.630481 ZQ Calibration : PASS
7123 23:11:29.630564 Jitter Meter : NO K
7124 23:11:29.633430 CBT Training : PASS
7125 23:11:29.636836 Write leveling : NO K
7126 23:11:29.636918 RX DQS gating : PASS
7127 23:11:29.640479 RX DQ/DQS(RDDQC) : PASS
7128 23:11:29.643530 TX DQ/DQS : PASS
7129 23:11:29.643613 RX DATLAT : PASS
7130 23:11:29.647212 RX DQ/DQS(Engine): PASS
7131 23:11:29.650120 TX OE : NO K
7132 23:11:29.650204 All Pass.
7133 23:11:29.650270
7134 23:11:29.653448 DramC Write-DBI off
7135 23:11:29.653552 PER_BANK_REFRESH: Hybrid Mode
7136 23:11:29.657018 TX_TRACKING: ON
7137 23:11:29.664002 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7138 23:11:29.670184 [FAST_K] Save calibration result to emmc
7139 23:11:29.673698 dramc_set_vcore_voltage set vcore to 725000
7140 23:11:29.673783 Read voltage for 1600, 0
7141 23:11:29.676919 Vio18 = 0
7142 23:11:29.677001 Vcore = 725000
7143 23:11:29.677067 Vdram = 0
7144 23:11:29.680398 Vddq = 0
7145 23:11:29.680481 Vmddr = 0
7146 23:11:29.683670 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7147 23:11:29.689888 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7148 23:11:29.693495 MEM_TYPE=3, freq_sel=13
7149 23:11:29.696574 sv_algorithm_assistance_LP4_3733
7150 23:11:29.700177 ============ PULL DRAM RESETB DOWN ============
7151 23:11:29.703723 ========== PULL DRAM RESETB DOWN end =========
7152 23:11:29.710118 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7153 23:11:29.713425 ===================================
7154 23:11:29.713564 LPDDR4 DRAM CONFIGURATION
7155 23:11:29.716588 ===================================
7156 23:11:29.719978 EX_ROW_EN[0] = 0x0
7157 23:11:29.720063 EX_ROW_EN[1] = 0x0
7158 23:11:29.723176 LP4Y_EN = 0x0
7159 23:11:29.723261 WORK_FSP = 0x1
7160 23:11:29.726470 WL = 0x5
7161 23:11:29.729800 RL = 0x5
7162 23:11:29.729885 BL = 0x2
7163 23:11:29.733142 RPST = 0x0
7164 23:11:29.733228 RD_PRE = 0x0
7165 23:11:29.736696 WR_PRE = 0x1
7166 23:11:29.736805 WR_PST = 0x1
7167 23:11:29.739845 DBI_WR = 0x0
7168 23:11:29.739931 DBI_RD = 0x0
7169 23:11:29.743017 OTF = 0x1
7170 23:11:29.746205 ===================================
7171 23:11:29.749375 ===================================
7172 23:11:29.749492 ANA top config
7173 23:11:29.752940 ===================================
7174 23:11:29.756030 DLL_ASYNC_EN = 0
7175 23:11:29.759530 ALL_SLAVE_EN = 0
7176 23:11:29.759615 NEW_RANK_MODE = 1
7177 23:11:29.762831 DLL_IDLE_MODE = 1
7178 23:11:29.765944 LP45_APHY_COMB_EN = 1
7179 23:11:29.769161 TX_ODT_DIS = 0
7180 23:11:29.772717 NEW_8X_MODE = 1
7181 23:11:29.776180 ===================================
7182 23:11:29.779389 ===================================
7183 23:11:29.782556 data_rate = 3200
7184 23:11:29.782642 CKR = 1
7185 23:11:29.785793 DQ_P2S_RATIO = 8
7186 23:11:29.789404 ===================================
7187 23:11:29.792611 CA_P2S_RATIO = 8
7188 23:11:29.795764 DQ_CA_OPEN = 0
7189 23:11:29.799321 DQ_SEMI_OPEN = 0
7190 23:11:29.799407 CA_SEMI_OPEN = 0
7191 23:11:29.802629 CA_FULL_RATE = 0
7192 23:11:29.805813 DQ_CKDIV4_EN = 0
7193 23:11:29.809269 CA_CKDIV4_EN = 0
7194 23:11:29.812393 CA_PREDIV_EN = 0
7195 23:11:29.815880 PH8_DLY = 12
7196 23:11:29.819008 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7197 23:11:29.819090 DQ_AAMCK_DIV = 4
7198 23:11:29.822588 CA_AAMCK_DIV = 4
7199 23:11:29.825657 CA_ADMCK_DIV = 4
7200 23:11:29.828827 DQ_TRACK_CA_EN = 0
7201 23:11:29.832697 CA_PICK = 1600
7202 23:11:29.835671 CA_MCKIO = 1600
7203 23:11:29.835754 MCKIO_SEMI = 0
7204 23:11:29.839098 PLL_FREQ = 3068
7205 23:11:29.842430 DQ_UI_PI_RATIO = 32
7206 23:11:29.845665 CA_UI_PI_RATIO = 0
7207 23:11:29.848706 ===================================
7208 23:11:29.852339 ===================================
7209 23:11:29.855689 memory_type:LPDDR4
7210 23:11:29.855772 GP_NUM : 10
7211 23:11:29.858759 SRAM_EN : 1
7212 23:11:29.861861 MD32_EN : 0
7213 23:11:29.865362 ===================================
7214 23:11:29.865445 [ANA_INIT] >>>>>>>>>>>>>>
7215 23:11:29.868605 <<<<<< [CONFIGURE PHASE]: ANA_TX
7216 23:11:29.871903 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7217 23:11:29.875025 ===================================
7218 23:11:29.878407 data_rate = 3200,PCW = 0X7600
7219 23:11:29.881653 ===================================
7220 23:11:29.885037 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7221 23:11:29.891947 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7222 23:11:29.895029 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7223 23:11:29.901673 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7224 23:11:29.904623 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7225 23:11:29.908196 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7226 23:11:29.911500 [ANA_INIT] flow start
7227 23:11:29.911583 [ANA_INIT] PLL >>>>>>>>
7228 23:11:29.914787 [ANA_INIT] PLL <<<<<<<<
7229 23:11:29.917938 [ANA_INIT] MIDPI >>>>>>>>
7230 23:11:29.918020 [ANA_INIT] MIDPI <<<<<<<<
7231 23:11:29.921526 [ANA_INIT] DLL >>>>>>>>
7232 23:11:29.924849 [ANA_INIT] DLL <<<<<<<<
7233 23:11:29.924931 [ANA_INIT] flow end
7234 23:11:29.931598 ============ LP4 DIFF to SE enter ============
7235 23:11:29.934832 ============ LP4 DIFF to SE exit ============
7236 23:11:29.937829 [ANA_INIT] <<<<<<<<<<<<<
7237 23:11:29.941720 [Flow] Enable top DCM control >>>>>
7238 23:11:29.941806 [Flow] Enable top DCM control <<<<<
7239 23:11:29.944667 Enable DLL master slave shuffle
7240 23:11:29.951031 ==============================================================
7241 23:11:29.954723 Gating Mode config
7242 23:11:29.957735 ==============================================================
7243 23:11:29.961411 Config description:
7244 23:11:29.971635 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7245 23:11:29.977902 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7246 23:11:29.980996 SELPH_MODE 0: By rank 1: By Phase
7247 23:11:29.987544 ==============================================================
7248 23:11:29.990819 GAT_TRACK_EN = 1
7249 23:11:29.994199 RX_GATING_MODE = 2
7250 23:11:29.997862 RX_GATING_TRACK_MODE = 2
7251 23:11:29.997945 SELPH_MODE = 1
7252 23:11:30.000809 PICG_EARLY_EN = 1
7253 23:11:30.004368 VALID_LAT_VALUE = 1
7254 23:11:30.010830 ==============================================================
7255 23:11:30.014283 Enter into Gating configuration >>>>
7256 23:11:30.017755 Exit from Gating configuration <<<<
7257 23:11:30.020895 Enter into DVFS_PRE_config >>>>>
7258 23:11:30.030933 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7259 23:11:30.034180 Exit from DVFS_PRE_config <<<<<
7260 23:11:30.037573 Enter into PICG configuration >>>>
7261 23:11:30.040620 Exit from PICG configuration <<<<
7262 23:11:30.044304 [RX_INPUT] configuration >>>>>
7263 23:11:30.047563 [RX_INPUT] configuration <<<<<
7264 23:11:30.050688 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7265 23:11:30.057427 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7266 23:11:30.064087 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7267 23:11:30.070880 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7268 23:11:30.077142 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7269 23:11:30.080330 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7270 23:11:30.087141 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7271 23:11:30.090782 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7272 23:11:30.093755 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7273 23:11:30.097106 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7274 23:11:30.104029 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7275 23:11:30.107294 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7276 23:11:30.110610 ===================================
7277 23:11:30.113737 LPDDR4 DRAM CONFIGURATION
7278 23:11:30.117235 ===================================
7279 23:11:30.117318 EX_ROW_EN[0] = 0x0
7280 23:11:30.120378 EX_ROW_EN[1] = 0x0
7281 23:11:30.120462 LP4Y_EN = 0x0
7282 23:11:30.123752 WORK_FSP = 0x1
7283 23:11:30.123835 WL = 0x5
7284 23:11:30.126928 RL = 0x5
7285 23:11:30.127011 BL = 0x2
7286 23:11:30.130344 RPST = 0x0
7287 23:11:30.130427 RD_PRE = 0x0
7288 23:11:30.133413 WR_PRE = 0x1
7289 23:11:30.136783 WR_PST = 0x1
7290 23:11:30.136866 DBI_WR = 0x0
7291 23:11:30.140250 DBI_RD = 0x0
7292 23:11:30.140332 OTF = 0x1
7293 23:11:30.143628 ===================================
7294 23:11:30.146975 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7295 23:11:30.150177 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7296 23:11:30.156845 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7297 23:11:30.159963 ===================================
7298 23:11:30.163356 LPDDR4 DRAM CONFIGURATION
7299 23:11:30.166500 ===================================
7300 23:11:30.166585 EX_ROW_EN[0] = 0x10
7301 23:11:30.169985 EX_ROW_EN[1] = 0x0
7302 23:11:30.170068 LP4Y_EN = 0x0
7303 23:11:30.173305 WORK_FSP = 0x1
7304 23:11:30.173414 WL = 0x5
7305 23:11:30.176343 RL = 0x5
7306 23:11:30.176425 BL = 0x2
7307 23:11:30.180078 RPST = 0x0
7308 23:11:30.180161 RD_PRE = 0x0
7309 23:11:30.183161 WR_PRE = 0x1
7310 23:11:30.183243 WR_PST = 0x1
7311 23:11:30.186274 DBI_WR = 0x0
7312 23:11:30.190020 DBI_RD = 0x0
7313 23:11:30.190103 OTF = 0x1
7314 23:11:30.193059 ===================================
7315 23:11:30.199772 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7316 23:11:30.199857 ==
7317 23:11:30.202742 Dram Type= 6, Freq= 0, CH_0, rank 0
7318 23:11:30.206006 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7319 23:11:30.206090 ==
7320 23:11:30.209634 [Duty_Offset_Calibration]
7321 23:11:30.212883 B0:2 B1:0 CA:3
7322 23:11:30.212966
7323 23:11:30.215824 [DutyScan_Calibration_Flow] k_type=0
7324 23:11:30.224577
7325 23:11:30.224663 ==CLK 0==
7326 23:11:30.227685 Final CLK duty delay cell = 0
7327 23:11:30.231015 [0] MAX Duty = 5031%(X100), DQS PI = 12
7328 23:11:30.234355 [0] MIN Duty = 4907%(X100), DQS PI = 4
7329 23:11:30.234439 [0] AVG Duty = 4969%(X100)
7330 23:11:30.237841
7331 23:11:30.240769 CH0 CLK Duty spec in!! Max-Min= 124%
7332 23:11:30.243884 [DutyScan_Calibration_Flow] ====Done====
7333 23:11:30.243967
7334 23:11:30.247210 [DutyScan_Calibration_Flow] k_type=1
7335 23:11:30.263836
7336 23:11:30.263947 ==DQS 0 ==
7337 23:11:30.267357 Final DQS duty delay cell = 0
7338 23:11:30.270450 [0] MAX Duty = 5094%(X100), DQS PI = 30
7339 23:11:30.274254 [0] MIN Duty = 4875%(X100), DQS PI = 48
7340 23:11:30.277333 [0] AVG Duty = 4984%(X100)
7341 23:11:30.277417
7342 23:11:30.277508 ==DQS 1 ==
7343 23:11:30.280501 Final DQS duty delay cell = 0
7344 23:11:30.283586 [0] MAX Duty = 5156%(X100), DQS PI = 32
7345 23:11:30.287386 [0] MIN Duty = 5062%(X100), DQS PI = 8
7346 23:11:30.290443 [0] AVG Duty = 5109%(X100)
7347 23:11:30.290527
7348 23:11:30.293628 CH0 DQS 0 Duty spec in!! Max-Min= 219%
7349 23:11:30.293712
7350 23:11:30.296850 CH0 DQS 1 Duty spec in!! Max-Min= 94%
7351 23:11:30.300496 [DutyScan_Calibration_Flow] ====Done====
7352 23:11:30.300580
7353 23:11:30.303763 [DutyScan_Calibration_Flow] k_type=3
7354 23:11:30.320788
7355 23:11:30.320892 ==DQM 0 ==
7356 23:11:30.324053 Final DQM duty delay cell = 0
7357 23:11:30.327497 [0] MAX Duty = 5156%(X100), DQS PI = 30
7358 23:11:30.330516 [0] MIN Duty = 4844%(X100), DQS PI = 50
7359 23:11:30.334225 [0] AVG Duty = 5000%(X100)
7360 23:11:30.334317
7361 23:11:30.334384 ==DQM 1 ==
7362 23:11:30.337318 Final DQM duty delay cell = 0
7363 23:11:30.340849 [0] MAX Duty = 4938%(X100), DQS PI = 60
7364 23:11:30.343951 [0] MIN Duty = 4813%(X100), DQS PI = 14
7365 23:11:30.347353 [0] AVG Duty = 4875%(X100)
7366 23:11:30.347435
7367 23:11:30.350747 CH0 DQM 0 Duty spec in!! Max-Min= 312%
7368 23:11:30.350830
7369 23:11:30.354124 CH0 DQM 1 Duty spec in!! Max-Min= 125%
7370 23:11:30.357272 [DutyScan_Calibration_Flow] ====Done====
7371 23:11:30.357356
7372 23:11:30.360466 [DutyScan_Calibration_Flow] k_type=2
7373 23:11:30.377202
7374 23:11:30.377313 ==DQ 0 ==
7375 23:11:30.380420 Final DQ duty delay cell = -4
7376 23:11:30.383543 [-4] MAX Duty = 5000%(X100), DQS PI = 20
7377 23:11:30.387070 [-4] MIN Duty = 4876%(X100), DQS PI = 0
7378 23:11:30.390213 [-4] AVG Duty = 4938%(X100)
7379 23:11:30.390296
7380 23:11:30.390361 ==DQ 1 ==
7381 23:11:30.393857 Final DQ duty delay cell = 0
7382 23:11:30.397048 [0] MAX Duty = 5156%(X100), DQS PI = 60
7383 23:11:30.400228 [0] MIN Duty = 5000%(X100), DQS PI = 16
7384 23:11:30.403353 [0] AVG Duty = 5078%(X100)
7385 23:11:30.403436
7386 23:11:30.406885 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7387 23:11:30.406972
7388 23:11:30.409964 CH0 DQ 1 Duty spec in!! Max-Min= 156%
7389 23:11:30.413512 [DutyScan_Calibration_Flow] ====Done====
7390 23:11:30.413609 ==
7391 23:11:30.416622 Dram Type= 6, Freq= 0, CH_1, rank 0
7392 23:11:30.420175 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7393 23:11:30.420259 ==
7394 23:11:30.423301 [Duty_Offset_Calibration]
7395 23:11:30.423383 B0:1 B1:-2 CA:0
7396 23:11:30.423448
7397 23:11:30.426809 [DutyScan_Calibration_Flow] k_type=0
7398 23:11:30.437665
7399 23:11:30.437752 ==CLK 0==
7400 23:11:30.440714 Final CLK duty delay cell = 0
7401 23:11:30.444306 [0] MAX Duty = 5062%(X100), DQS PI = 20
7402 23:11:30.447658 [0] MIN Duty = 4844%(X100), DQS PI = 2
7403 23:11:30.447744 [0] AVG Duty = 4953%(X100)
7404 23:11:30.450728
7405 23:11:30.453988 CH1 CLK Duty spec in!! Max-Min= 218%
7406 23:11:30.457770 [DutyScan_Calibration_Flow] ====Done====
7407 23:11:30.457853
7408 23:11:30.460919 [DutyScan_Calibration_Flow] k_type=1
7409 23:11:30.476529
7410 23:11:30.476628 ==DQS 0 ==
7411 23:11:30.479691 Final DQS duty delay cell = -4
7412 23:11:30.482924 [-4] MAX Duty = 4969%(X100), DQS PI = 26
7413 23:11:30.486307 [-4] MIN Duty = 4844%(X100), DQS PI = 0
7414 23:11:30.489471 [-4] AVG Duty = 4906%(X100)
7415 23:11:30.489595
7416 23:11:30.489661 ==DQS 1 ==
7417 23:11:30.492919 Final DQS duty delay cell = 0
7418 23:11:30.496043 [0] MAX Duty = 5093%(X100), DQS PI = 62
7419 23:11:30.499497 [0] MIN Duty = 4844%(X100), DQS PI = 24
7420 23:11:30.502668 [0] AVG Duty = 4968%(X100)
7421 23:11:30.502750
7422 23:11:30.505839 CH1 DQS 0 Duty spec in!! Max-Min= 125%
7423 23:11:30.505923
7424 23:11:30.509383 CH1 DQS 1 Duty spec in!! Max-Min= 249%
7425 23:11:30.512517 [DutyScan_Calibration_Flow] ====Done====
7426 23:11:30.512600
7427 23:11:30.515726 [DutyScan_Calibration_Flow] k_type=3
7428 23:11:30.533273
7429 23:11:30.533365 ==DQM 0 ==
7430 23:11:30.536734 Final DQM duty delay cell = 0
7431 23:11:30.539891 [0] MAX Duty = 5031%(X100), DQS PI = 26
7432 23:11:30.543420 [0] MIN Duty = 4813%(X100), DQS PI = 56
7433 23:11:30.546719 [0] AVG Duty = 4922%(X100)
7434 23:11:30.546803
7435 23:11:30.546869 ==DQM 1 ==
7436 23:11:30.549745 Final DQM duty delay cell = 0
7437 23:11:30.553266 [0] MAX Duty = 5062%(X100), DQS PI = 34
7438 23:11:30.556806 [0] MIN Duty = 4875%(X100), DQS PI = 26
7439 23:11:30.559969 [0] AVG Duty = 4968%(X100)
7440 23:11:30.560053
7441 23:11:30.563158 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7442 23:11:30.563242
7443 23:11:30.566698 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7444 23:11:30.570092 [DutyScan_Calibration_Flow] ====Done====
7445 23:11:30.570176
7446 23:11:30.573321 [DutyScan_Calibration_Flow] k_type=2
7447 23:11:30.590342
7448 23:11:30.590438 ==DQ 0 ==
7449 23:11:30.593744 Final DQ duty delay cell = 0
7450 23:11:30.596895 [0] MAX Duty = 5093%(X100), DQS PI = 20
7451 23:11:30.600042 [0] MIN Duty = 4907%(X100), DQS PI = 58
7452 23:11:30.600127 [0] AVG Duty = 5000%(X100)
7453 23:11:30.603568
7454 23:11:30.603651 ==DQ 1 ==
7455 23:11:30.606732 Final DQ duty delay cell = 0
7456 23:11:30.610491 [0] MAX Duty = 5125%(X100), DQS PI = 34
7457 23:11:30.613327 [0] MIN Duty = 4969%(X100), DQS PI = 24
7458 23:11:30.613412 [0] AVG Duty = 5047%(X100)
7459 23:11:30.616564
7460 23:11:30.620292 CH1 DQ 0 Duty spec in!! Max-Min= 186%
7461 23:11:30.620379
7462 23:11:30.623455 CH1 DQ 1 Duty spec in!! Max-Min= 156%
7463 23:11:30.627175 [DutyScan_Calibration_Flow] ====Done====
7464 23:11:30.630053 nWR fixed to 30
7465 23:11:30.630140 [ModeRegInit_LP4] CH0 RK0
7466 23:11:30.633314 [ModeRegInit_LP4] CH0 RK1
7467 23:11:30.636502 [ModeRegInit_LP4] CH1 RK0
7468 23:11:30.639866 [ModeRegInit_LP4] CH1 RK1
7469 23:11:30.639954 match AC timing 5
7470 23:11:30.646735 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7471 23:11:30.650041 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7472 23:11:30.653030 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7473 23:11:30.659577 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7474 23:11:30.663277 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7475 23:11:30.663366 [MiockJmeterHQA]
7476 23:11:30.663453
7477 23:11:30.666332 [DramcMiockJmeter] u1RxGatingPI = 0
7478 23:11:30.669358 0 : 4257, 4029
7479 23:11:30.669445 4 : 4252, 4027
7480 23:11:30.673161 8 : 4365, 4140
7481 23:11:30.673249 12 : 4254, 4029
7482 23:11:30.673356 16 : 4368, 4140
7483 23:11:30.676224 20 : 4254, 4029
7484 23:11:30.676311 24 : 4257, 4029
7485 23:11:30.679317 28 : 4255, 4029
7486 23:11:30.679404 32 : 4257, 4029
7487 23:11:30.682812 36 : 4370, 4142
7488 23:11:30.682899 40 : 4255, 4029
7489 23:11:30.685933 44 : 4255, 4029
7490 23:11:30.686020 48 : 4252, 4027
7491 23:11:30.686108 52 : 4255, 4029
7492 23:11:30.689159 56 : 4366, 4139
7493 23:11:30.689246 60 : 4255, 4030
7494 23:11:30.692616 64 : 4257, 4032
7495 23:11:30.692736 68 : 4255, 4029
7496 23:11:30.695757 72 : 4365, 4140
7497 23:11:30.695845 76 : 4255, 4029
7498 23:11:30.699284 80 : 4366, 4140
7499 23:11:30.699372 84 : 4363, 4140
7500 23:11:30.699461 88 : 4368, 4142
7501 23:11:30.702709 92 : 4253, 4029
7502 23:11:30.702797 96 : 4257, 4031
7503 23:11:30.705990 100 : 4254, 4029
7504 23:11:30.706078 104 : 4253, 3640
7505 23:11:30.709093 108 : 4257, 2
7506 23:11:30.709179 112 : 4363, 0
7507 23:11:30.709268 116 : 4363, 0
7508 23:11:30.712463 120 : 4252, 0
7509 23:11:30.712553 124 : 4252, 0
7510 23:11:30.715880 128 : 4252, 0
7511 23:11:30.715967 132 : 4258, 0
7512 23:11:30.716056 136 : 4362, 0
7513 23:11:30.719001 140 : 4363, 0
7514 23:11:30.719088 144 : 4367, 0
7515 23:11:30.722347 148 : 4252, 0
7516 23:11:30.722435 152 : 4366, 0
7517 23:11:30.722523 156 : 4253, 0
7518 23:11:30.725687 160 : 4252, 0
7519 23:11:30.725774 164 : 4363, 0
7520 23:11:30.729253 168 : 4253, 0
7521 23:11:30.729339 172 : 4252, 0
7522 23:11:30.729445 176 : 4252, 0
7523 23:11:30.732431 180 : 4363, 0
7524 23:11:30.732518 184 : 4252, 0
7525 23:11:30.732606 188 : 4363, 0
7526 23:11:30.736114 192 : 4252, 0
7527 23:11:30.736201 196 : 4253, 0
7528 23:11:30.739241 200 : 4253, 0
7529 23:11:30.739328 204 : 4366, 0
7530 23:11:30.739416 208 : 4363, 0
7531 23:11:30.742500 212 : 4252, 0
7532 23:11:30.742587 216 : 4363, 0
7533 23:11:30.745729 220 : 4252, 0
7534 23:11:30.745816 224 : 4253, 0
7535 23:11:30.745904 228 : 4253, 0
7536 23:11:30.749160 232 : 4255, 0
7537 23:11:30.749247 236 : 4253, 1080
7538 23:11:30.752475 240 : 4368, 4142
7539 23:11:30.752564 244 : 4365, 4139
7540 23:11:30.755567 248 : 4363, 4140
7541 23:11:30.755655 252 : 4252, 4027
7542 23:11:30.759218 256 : 4366, 4139
7543 23:11:30.759305 260 : 4255, 4029
7544 23:11:30.759394 264 : 4252, 4029
7545 23:11:30.762282 268 : 4253, 4029
7546 23:11:30.762369 272 : 4257, 4032
7547 23:11:30.765621 276 : 4252, 4030
7548 23:11:30.765708 280 : 4365, 4139
7549 23:11:30.768917 284 : 4253, 4029
7550 23:11:30.769005 288 : 4257, 4031
7551 23:11:30.772528 292 : 4253, 4029
7552 23:11:30.772615 296 : 4252, 4030
7553 23:11:30.775523 300 : 4253, 4029
7554 23:11:30.775612 304 : 4252, 4030
7555 23:11:30.778938 308 : 4257, 4031
7556 23:11:30.779041 312 : 4361, 4137
7557 23:11:30.782437 316 : 4252, 4029
7558 23:11:30.782513 320 : 4363, 4140
7559 23:11:30.785462 324 : 4363, 4140
7560 23:11:30.785582 328 : 4252, 4030
7561 23:11:30.785646 332 : 4250, 4026
7562 23:11:30.789252 336 : 4253, 4029
7563 23:11:30.789327 340 : 4257, 4032
7564 23:11:30.792379 344 : 4365, 4139
7565 23:11:30.792452 348 : 4366, 4140
7566 23:11:30.795380 352 : 4252, 4009
7567 23:11:30.795464 356 : 4252, 2739
7568 23:11:30.798867 360 : 4253, 4
7569 23:11:30.798951
7570 23:11:30.799018 MIOCK jitter meter ch=0
7571 23:11:30.799079
7572 23:11:30.802468 1T = (360-108) = 252 dly cells
7573 23:11:30.809143 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7574 23:11:30.809234 ==
7575 23:11:30.812391 Dram Type= 6, Freq= 0, CH_0, rank 0
7576 23:11:30.815387 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7577 23:11:30.815488 ==
7578 23:11:30.822076 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7579 23:11:30.825404 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7580 23:11:30.829432 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7581 23:11:30.835269 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7582 23:11:30.845291 [CA 0] Center 44 (14~75) winsize 62
7583 23:11:30.848886 [CA 1] Center 43 (13~74) winsize 62
7584 23:11:30.852048 [CA 2] Center 40 (11~69) winsize 59
7585 23:11:30.855304 [CA 3] Center 39 (10~69) winsize 60
7586 23:11:30.858777 [CA 4] Center 37 (8~67) winsize 60
7587 23:11:30.862120 [CA 5] Center 37 (7~67) winsize 61
7588 23:11:30.862208
7589 23:11:30.865338 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7590 23:11:30.865425
7591 23:11:30.868773 [CATrainingPosCal] consider 1 rank data
7592 23:11:30.871760 u2DelayCellTimex100 = 258/100 ps
7593 23:11:30.878545 CA0 delay=44 (14~75),Diff = 7 PI (26 cell)
7594 23:11:30.881705 CA1 delay=43 (13~74),Diff = 6 PI (22 cell)
7595 23:11:30.884960 CA2 delay=40 (11~69),Diff = 3 PI (11 cell)
7596 23:11:30.888373 CA3 delay=39 (10~69),Diff = 2 PI (7 cell)
7597 23:11:30.891487 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7598 23:11:30.895382 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7599 23:11:30.895468
7600 23:11:30.898514 CA PerBit enable=1, Macro0, CA PI delay=37
7601 23:11:30.898600
7602 23:11:30.901562 [CBTSetCACLKResult] CA Dly = 37
7603 23:11:30.904998 CS Dly: 11 (0~42)
7604 23:11:30.908172 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7605 23:11:30.911837 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7606 23:11:30.911924 ==
7607 23:11:30.914795 Dram Type= 6, Freq= 0, CH_0, rank 1
7608 23:11:30.921495 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7609 23:11:30.921675 ==
7610 23:11:30.924571 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7611 23:11:30.931411 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7612 23:11:30.934775 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7613 23:11:30.941341 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7614 23:11:30.949344 [CA 0] Center 44 (14~74) winsize 61
7615 23:11:30.952402 [CA 1] Center 43 (13~74) winsize 62
7616 23:11:30.955601 [CA 2] Center 39 (10~68) winsize 59
7617 23:11:30.959285 [CA 3] Center 39 (10~68) winsize 59
7618 23:11:30.962243 [CA 4] Center 36 (7~66) winsize 60
7619 23:11:30.965755 [CA 5] Center 36 (7~66) winsize 60
7620 23:11:30.965869
7621 23:11:30.968865 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7622 23:11:30.968974
7623 23:11:30.975656 [CATrainingPosCal] consider 2 rank data
7624 23:11:30.975774 u2DelayCellTimex100 = 258/100 ps
7625 23:11:30.982251 CA0 delay=44 (14~74),Diff = 8 PI (30 cell)
7626 23:11:30.985907 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7627 23:11:30.989085 CA2 delay=39 (11~68),Diff = 3 PI (11 cell)
7628 23:11:30.992052 CA3 delay=39 (10~68),Diff = 3 PI (11 cell)
7629 23:11:30.995252 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
7630 23:11:30.998902 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7631 23:11:30.999013
7632 23:11:31.002177 CA PerBit enable=1, Macro0, CA PI delay=36
7633 23:11:31.002289
7634 23:11:31.005514 [CBTSetCACLKResult] CA Dly = 36
7635 23:11:31.008618 CS Dly: 11 (0~43)
7636 23:11:31.011763 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7637 23:11:31.015249 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7638 23:11:31.015359
7639 23:11:31.018468 ----->DramcWriteLeveling(PI) begin...
7640 23:11:31.021670 ==
7641 23:11:31.021782 Dram Type= 6, Freq= 0, CH_0, rank 0
7642 23:11:31.028614 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7643 23:11:31.028726 ==
7644 23:11:31.031837 Write leveling (Byte 0): 34 => 34
7645 23:11:31.034966 Write leveling (Byte 1): 27 => 27
7646 23:11:31.038526 DramcWriteLeveling(PI) end<-----
7647 23:11:31.038639
7648 23:11:31.038740 ==
7649 23:11:31.041885 Dram Type= 6, Freq= 0, CH_0, rank 0
7650 23:11:31.044840 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7651 23:11:31.044954 ==
7652 23:11:31.048183 [Gating] SW mode calibration
7653 23:11:31.055165 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7654 23:11:31.061865 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7655 23:11:31.064881 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7656 23:11:31.068574 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7657 23:11:31.071601 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7658 23:11:31.078704 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7659 23:11:31.081890 1 4 16 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (1 1)
7660 23:11:31.084799 1 4 20 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7661 23:11:31.091639 1 4 24 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
7662 23:11:31.094650 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7663 23:11:31.098069 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7664 23:11:31.104555 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7665 23:11:31.108213 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7666 23:11:31.111193 1 5 12 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
7667 23:11:31.117833 1 5 16 | B1->B0 | 3434 2a2a | 1 0 | (1 1) (0 1)
7668 23:11:31.121564 1 5 20 | B1->B0 | 3434 2323 | 0 0 | (0 0) (0 0)
7669 23:11:31.124605 1 5 24 | B1->B0 | 2424 2323 | 0 0 | (0 1) (0 0)
7670 23:11:31.131103 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7671 23:11:31.134757 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7672 23:11:31.137763 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7673 23:11:31.144474 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7674 23:11:31.148079 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7675 23:11:31.150968 1 6 16 | B1->B0 | 2323 3f3f | 0 0 | (0 0) (0 0)
7676 23:11:31.158163 1 6 20 | B1->B0 | 3030 4646 | 0 0 | (0 0) (0 0)
7677 23:11:31.161141 1 6 24 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
7678 23:11:31.164223 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7679 23:11:31.170834 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7680 23:11:31.174394 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7681 23:11:31.177449 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7682 23:11:31.184317 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7683 23:11:31.187646 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7684 23:11:31.190790 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7685 23:11:31.197401 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7686 23:11:31.200870 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7687 23:11:31.204042 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7688 23:11:31.210485 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7689 23:11:31.214304 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7690 23:11:31.217609 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7691 23:11:31.223975 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7692 23:11:31.227170 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7693 23:11:31.230863 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7694 23:11:31.237211 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7695 23:11:31.240810 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7696 23:11:31.243692 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7697 23:11:31.251000 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7698 23:11:31.254077 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7699 23:11:31.257197 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7700 23:11:31.260500 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7701 23:11:31.264102 Total UI for P1: 0, mck2ui 16
7702 23:11:31.267052 best dqsien dly found for B0: ( 1, 9, 14)
7703 23:11:31.273536 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7704 23:11:31.277225 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7705 23:11:31.280673 Total UI for P1: 0, mck2ui 16
7706 23:11:31.283902 best dqsien dly found for B1: ( 1, 9, 24)
7707 23:11:31.287075 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
7708 23:11:31.290245 best DQS1 dly(MCK, UI, PI) = (1, 9, 24)
7709 23:11:31.290329
7710 23:11:31.293880 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
7711 23:11:31.300194 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 24)
7712 23:11:31.300303 [Gating] SW calibration Done
7713 23:11:31.300397 ==
7714 23:11:31.303899 Dram Type= 6, Freq= 0, CH_0, rank 0
7715 23:11:31.310299 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7716 23:11:31.310383 ==
7717 23:11:31.310450 RX Vref Scan: 0
7718 23:11:31.310518
7719 23:11:31.313413 RX Vref 0 -> 0, step: 1
7720 23:11:31.313552
7721 23:11:31.316924 RX Delay 0 -> 252, step: 8
7722 23:11:31.320156 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7723 23:11:31.323099 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
7724 23:11:31.326803 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7725 23:11:31.333421 iDelay=200, Bit 3, Center 123 (72 ~ 175) 104
7726 23:11:31.336658 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
7727 23:11:31.340279 iDelay=200, Bit 5, Center 115 (64 ~ 167) 104
7728 23:11:31.343298 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
7729 23:11:31.346582 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
7730 23:11:31.353422 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
7731 23:11:31.356387 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7732 23:11:31.359686 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7733 23:11:31.363193 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7734 23:11:31.366370 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
7735 23:11:31.373127 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7736 23:11:31.376371 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7737 23:11:31.379713 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7738 23:11:31.379796 ==
7739 23:11:31.383267 Dram Type= 6, Freq= 0, CH_0, rank 0
7740 23:11:31.386229 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7741 23:11:31.386313 ==
7742 23:11:31.390016 DQS Delay:
7743 23:11:31.390100 DQS0 = 0, DQS1 = 0
7744 23:11:31.392935 DQM Delay:
7745 23:11:31.393018 DQM0 = 129, DQM1 = 124
7746 23:11:31.396560 DQ Delay:
7747 23:11:31.399758 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =123
7748 23:11:31.402764 DQ4 =127, DQ5 =115, DQ6 =139, DQ7 =143
7749 23:11:31.406524 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =119
7750 23:11:31.409657 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131
7751 23:11:31.409747
7752 23:11:31.409813
7753 23:11:31.409874 ==
7754 23:11:31.413204 Dram Type= 6, Freq= 0, CH_0, rank 0
7755 23:11:31.416415 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7756 23:11:31.416506 ==
7757 23:11:31.416574
7758 23:11:31.416635
7759 23:11:31.419724 TX Vref Scan disable
7760 23:11:31.422667 == TX Byte 0 ==
7761 23:11:31.426122 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7762 23:11:31.429410 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7763 23:11:31.432611 == TX Byte 1 ==
7764 23:11:31.435910 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7765 23:11:31.439134 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7766 23:11:31.439252 ==
7767 23:11:31.442313 Dram Type= 6, Freq= 0, CH_0, rank 0
7768 23:11:31.448878 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7769 23:11:31.448997 ==
7770 23:11:31.461231
7771 23:11:31.465040 TX Vref early break, caculate TX vref
7772 23:11:31.468176 TX Vref=16, minBit 4, minWin=21, winSum=354
7773 23:11:31.471276 TX Vref=18, minBit 8, minWin=21, winSum=365
7774 23:11:31.474965 TX Vref=20, minBit 8, minWin=21, winSum=373
7775 23:11:31.477837 TX Vref=22, minBit 8, minWin=23, winSum=386
7776 23:11:31.481140 TX Vref=24, minBit 8, minWin=23, winSum=394
7777 23:11:31.487803 TX Vref=26, minBit 4, minWin=24, winSum=398
7778 23:11:31.491208 TX Vref=28, minBit 8, minWin=23, winSum=401
7779 23:11:31.494570 TX Vref=30, minBit 8, minWin=23, winSum=395
7780 23:11:31.498028 TX Vref=32, minBit 8, minWin=23, winSum=385
7781 23:11:31.501236 TX Vref=34, minBit 8, minWin=22, winSum=379
7782 23:11:31.507601 [TxChooseVref] Worse bit 4, Min win 24, Win sum 398, Final Vref 26
7783 23:11:31.507719
7784 23:11:31.510996 Final TX Range 0 Vref 26
7785 23:11:31.511112
7786 23:11:31.511215 ==
7787 23:11:31.514537 Dram Type= 6, Freq= 0, CH_0, rank 0
7788 23:11:31.517726 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7789 23:11:31.517841 ==
7790 23:11:31.517947
7791 23:11:31.518047
7792 23:11:31.521379 TX Vref Scan disable
7793 23:11:31.527711 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7794 23:11:31.527829 == TX Byte 0 ==
7795 23:11:31.531270 u2DelayCellOfst[0]=18 cells (5 PI)
7796 23:11:31.534318 u2DelayCellOfst[1]=22 cells (6 PI)
7797 23:11:31.537626 u2DelayCellOfst[2]=15 cells (4 PI)
7798 23:11:31.540865 u2DelayCellOfst[3]=15 cells (4 PI)
7799 23:11:31.544133 u2DelayCellOfst[4]=7 cells (2 PI)
7800 23:11:31.547525 u2DelayCellOfst[5]=0 cells (0 PI)
7801 23:11:31.550604 u2DelayCellOfst[6]=22 cells (6 PI)
7802 23:11:31.554219 u2DelayCellOfst[7]=22 cells (6 PI)
7803 23:11:31.557387 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7804 23:11:31.561180 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7805 23:11:31.564146 == TX Byte 1 ==
7806 23:11:31.564264 u2DelayCellOfst[8]=0 cells (0 PI)
7807 23:11:31.567676 u2DelayCellOfst[9]=0 cells (0 PI)
7808 23:11:31.570804 u2DelayCellOfst[10]=7 cells (2 PI)
7809 23:11:31.573978 u2DelayCellOfst[11]=3 cells (1 PI)
7810 23:11:31.577189 u2DelayCellOfst[12]=11 cells (3 PI)
7811 23:11:31.580809 u2DelayCellOfst[13]=11 cells (3 PI)
7812 23:11:31.583921 u2DelayCellOfst[14]=15 cells (4 PI)
7813 23:11:31.587300 u2DelayCellOfst[15]=11 cells (3 PI)
7814 23:11:31.590851 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7815 23:11:31.597494 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7816 23:11:31.597610 DramC Write-DBI on
7817 23:11:31.597713 ==
7818 23:11:31.600553 Dram Type= 6, Freq= 0, CH_0, rank 0
7819 23:11:31.604072 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7820 23:11:31.606992 ==
7821 23:11:31.607105
7822 23:11:31.607209
7823 23:11:31.607308 TX Vref Scan disable
7824 23:11:31.610890 == TX Byte 0 ==
7825 23:11:31.614232 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
7826 23:11:31.617413 == TX Byte 1 ==
7827 23:11:31.620848 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
7828 23:11:31.623988 DramC Write-DBI off
7829 23:11:31.624156
7830 23:11:31.624265 [DATLAT]
7831 23:11:31.624364 Freq=1600, CH0 RK0
7832 23:11:31.624464
7833 23:11:31.627774 DATLAT Default: 0xf
7834 23:11:31.627887 0, 0xFFFF, sum = 0
7835 23:11:31.630826 1, 0xFFFF, sum = 0
7836 23:11:31.633911 2, 0xFFFF, sum = 0
7837 23:11:31.634025 3, 0xFFFF, sum = 0
7838 23:11:31.637302 4, 0xFFFF, sum = 0
7839 23:11:31.637415 5, 0xFFFF, sum = 0
7840 23:11:31.640820 6, 0xFFFF, sum = 0
7841 23:11:31.640931 7, 0xFFFF, sum = 0
7842 23:11:31.643835 8, 0xFFFF, sum = 0
7843 23:11:31.643947 9, 0xFFFF, sum = 0
7844 23:11:31.647136 10, 0xFFFF, sum = 0
7845 23:11:31.647250 11, 0xFFFF, sum = 0
7846 23:11:31.650496 12, 0xFFFF, sum = 0
7847 23:11:31.650609 13, 0xFFFF, sum = 0
7848 23:11:31.653720 14, 0x0, sum = 1
7849 23:11:31.653833 15, 0x0, sum = 2
7850 23:11:31.657325 16, 0x0, sum = 3
7851 23:11:31.657439 17, 0x0, sum = 4
7852 23:11:31.660503 best_step = 15
7853 23:11:31.660626
7854 23:11:31.660728 ==
7855 23:11:31.663722 Dram Type= 6, Freq= 0, CH_0, rank 0
7856 23:11:31.666929 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7857 23:11:31.667044 ==
7858 23:11:31.670286 RX Vref Scan: 1
7859 23:11:31.670398
7860 23:11:31.670497 Set Vref Range= 24 -> 127
7861 23:11:31.670594
7862 23:11:31.673923 RX Vref 24 -> 127, step: 1
7863 23:11:31.674037
7864 23:11:31.677190 RX Delay 11 -> 252, step: 4
7865 23:11:31.677303
7866 23:11:31.680328 Set Vref, RX VrefLevel [Byte0]: 24
7867 23:11:31.683411 [Byte1]: 24
7868 23:11:31.683525
7869 23:11:31.686720 Set Vref, RX VrefLevel [Byte0]: 25
7870 23:11:31.690228 [Byte1]: 25
7871 23:11:31.693579
7872 23:11:31.693691 Set Vref, RX VrefLevel [Byte0]: 26
7873 23:11:31.697075 [Byte1]: 26
7874 23:11:31.701157
7875 23:11:31.701270 Set Vref, RX VrefLevel [Byte0]: 27
7876 23:11:31.704611 [Byte1]: 27
7877 23:11:31.708737
7878 23:11:31.708852 Set Vref, RX VrefLevel [Byte0]: 28
7879 23:11:31.712145 [Byte1]: 28
7880 23:11:31.716586
7881 23:11:31.716701 Set Vref, RX VrefLevel [Byte0]: 29
7882 23:11:31.719638 [Byte1]: 29
7883 23:11:31.723991
7884 23:11:31.724103 Set Vref, RX VrefLevel [Byte0]: 30
7885 23:11:31.727248 [Byte1]: 30
7886 23:11:31.731925
7887 23:11:31.732040 Set Vref, RX VrefLevel [Byte0]: 31
7888 23:11:31.735041 [Byte1]: 31
7889 23:11:31.739243
7890 23:11:31.739333 Set Vref, RX VrefLevel [Byte0]: 32
7891 23:11:31.742718 [Byte1]: 32
7892 23:11:31.746870
7893 23:11:31.746953 Set Vref, RX VrefLevel [Byte0]: 33
7894 23:11:31.750351 [Byte1]: 33
7895 23:11:31.754662
7896 23:11:31.754745 Set Vref, RX VrefLevel [Byte0]: 34
7897 23:11:31.757974 [Byte1]: 34
7898 23:11:31.762062
7899 23:11:31.762145 Set Vref, RX VrefLevel [Byte0]: 35
7900 23:11:31.765657 [Byte1]: 35
7901 23:11:31.769920
7902 23:11:31.770010 Set Vref, RX VrefLevel [Byte0]: 36
7903 23:11:31.773175 [Byte1]: 36
7904 23:11:31.777689
7905 23:11:31.777772 Set Vref, RX VrefLevel [Byte0]: 37
7906 23:11:31.780682 [Byte1]: 37
7907 23:11:31.784861
7908 23:11:31.784943 Set Vref, RX VrefLevel [Byte0]: 38
7909 23:11:31.788148 [Byte1]: 38
7910 23:11:31.792813
7911 23:11:31.792896 Set Vref, RX VrefLevel [Byte0]: 39
7912 23:11:31.795781 [Byte1]: 39
7913 23:11:31.800636
7914 23:11:31.800718 Set Vref, RX VrefLevel [Byte0]: 40
7915 23:11:31.803443 [Byte1]: 40
7916 23:11:31.807730
7917 23:11:31.807812 Set Vref, RX VrefLevel [Byte0]: 41
7918 23:11:31.811364 [Byte1]: 41
7919 23:11:31.815355
7920 23:11:31.815438 Set Vref, RX VrefLevel [Byte0]: 42
7921 23:11:31.818838 [Byte1]: 42
7922 23:11:31.823031
7923 23:11:31.823114 Set Vref, RX VrefLevel [Byte0]: 43
7924 23:11:31.826246 [Byte1]: 43
7925 23:11:31.830724
7926 23:11:31.830806 Set Vref, RX VrefLevel [Byte0]: 44
7927 23:11:31.833836 [Byte1]: 44
7928 23:11:31.838224
7929 23:11:31.838310 Set Vref, RX VrefLevel [Byte0]: 45
7930 23:11:31.841667 [Byte1]: 45
7931 23:11:31.845850
7932 23:11:31.845932 Set Vref, RX VrefLevel [Byte0]: 46
7933 23:11:31.849026 [Byte1]: 46
7934 23:11:31.853706
7935 23:11:31.853788 Set Vref, RX VrefLevel [Byte0]: 47
7936 23:11:31.856656 [Byte1]: 47
7937 23:11:31.860970
7938 23:11:31.861053 Set Vref, RX VrefLevel [Byte0]: 48
7939 23:11:31.864403 [Byte1]: 48
7940 23:11:31.868805
7941 23:11:31.868888 Set Vref, RX VrefLevel [Byte0]: 49
7942 23:11:31.871803 [Byte1]: 49
7943 23:11:31.876499
7944 23:11:31.876580 Set Vref, RX VrefLevel [Byte0]: 50
7945 23:11:31.879468 [Byte1]: 50
7946 23:11:31.884213
7947 23:11:31.884295 Set Vref, RX VrefLevel [Byte0]: 51
7948 23:11:31.887430 [Byte1]: 51
7949 23:11:31.891581
7950 23:11:31.891664 Set Vref, RX VrefLevel [Byte0]: 52
7951 23:11:31.894787 [Byte1]: 52
7952 23:11:31.898992
7953 23:11:31.899074 Set Vref, RX VrefLevel [Byte0]: 53
7954 23:11:31.902613 [Byte1]: 53
7955 23:11:31.906746
7956 23:11:31.906829 Set Vref, RX VrefLevel [Byte0]: 54
7957 23:11:31.910148 [Byte1]: 54
7958 23:11:31.914324
7959 23:11:31.914405 Set Vref, RX VrefLevel [Byte0]: 55
7960 23:11:31.917767 [Byte1]: 55
7961 23:11:31.921799
7962 23:11:31.921880 Set Vref, RX VrefLevel [Byte0]: 56
7963 23:11:31.925394 [Byte1]: 56
7964 23:11:31.929742
7965 23:11:31.929824 Set Vref, RX VrefLevel [Byte0]: 57
7966 23:11:31.932868 [Byte1]: 57
7967 23:11:31.937400
7968 23:11:31.937488 Set Vref, RX VrefLevel [Byte0]: 58
7969 23:11:31.940723 [Byte1]: 58
7970 23:11:31.944982
7971 23:11:31.945063 Set Vref, RX VrefLevel [Byte0]: 59
7972 23:11:31.948074 [Byte1]: 59
7973 23:11:31.952369
7974 23:11:31.952450 Set Vref, RX VrefLevel [Byte0]: 60
7975 23:11:31.955800 [Byte1]: 60
7976 23:11:31.959990
7977 23:11:31.960070 Set Vref, RX VrefLevel [Byte0]: 61
7978 23:11:31.963455 [Byte1]: 61
7979 23:11:31.967482
7980 23:11:31.967563 Set Vref, RX VrefLevel [Byte0]: 62
7981 23:11:31.970826 [Byte1]: 62
7982 23:11:31.975286
7983 23:11:31.975367 Set Vref, RX VrefLevel [Byte0]: 63
7984 23:11:31.978969 [Byte1]: 63
7985 23:11:31.983070
7986 23:11:31.983151 Set Vref, RX VrefLevel [Byte0]: 64
7987 23:11:31.986137 [Byte1]: 64
7988 23:11:31.990370
7989 23:11:31.990450 Set Vref, RX VrefLevel [Byte0]: 65
7990 23:11:31.994077 [Byte1]: 65
7991 23:11:31.998252
7992 23:11:31.998336 Set Vref, RX VrefLevel [Byte0]: 66
7993 23:11:32.001458 [Byte1]: 66
7994 23:11:32.005683
7995 23:11:32.005764 Set Vref, RX VrefLevel [Byte0]: 67
7996 23:11:32.009142 [Byte1]: 67
7997 23:11:32.013248
7998 23:11:32.013330 Set Vref, RX VrefLevel [Byte0]: 68
7999 23:11:32.016368 [Byte1]: 68
8000 23:11:32.021007
8001 23:11:32.021089 Set Vref, RX VrefLevel [Byte0]: 69
8002 23:11:32.024132 [Byte1]: 69
8003 23:11:32.028402
8004 23:11:32.028484 Set Vref, RX VrefLevel [Byte0]: 70
8005 23:11:32.032097 [Byte1]: 70
8006 23:11:32.036161
8007 23:11:32.036243 Set Vref, RX VrefLevel [Byte0]: 71
8008 23:11:32.039835 [Byte1]: 71
8009 23:11:32.043624
8010 23:11:32.043706 Set Vref, RX VrefLevel [Byte0]: 72
8011 23:11:32.047124 [Byte1]: 72
8012 23:11:32.051630
8013 23:11:32.051713 Set Vref, RX VrefLevel [Byte0]: 73
8014 23:11:32.054477 [Byte1]: 73
8015 23:11:32.059313
8016 23:11:32.059390 Set Vref, RX VrefLevel [Byte0]: 74
8017 23:11:32.062143 [Byte1]: 74
8018 23:11:32.066750
8019 23:11:32.066818 Set Vref, RX VrefLevel [Byte0]: 75
8020 23:11:32.070042 [Byte1]: 75
8021 23:11:32.074078
8022 23:11:32.074146 Set Vref, RX VrefLevel [Byte0]: 76
8023 23:11:32.077624 [Byte1]: 76
8024 23:11:32.081989
8025 23:11:32.082065 Final RX Vref Byte 0 = 64 to rank0
8026 23:11:32.085145 Final RX Vref Byte 1 = 57 to rank0
8027 23:11:32.088678 Final RX Vref Byte 0 = 64 to rank1
8028 23:11:32.091847 Final RX Vref Byte 1 = 57 to rank1==
8029 23:11:32.095054 Dram Type= 6, Freq= 0, CH_0, rank 0
8030 23:11:32.101873 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8031 23:11:32.101950 ==
8032 23:11:32.102013 DQS Delay:
8033 23:11:32.105045 DQS0 = 0, DQS1 = 0
8034 23:11:32.105115 DQM Delay:
8035 23:11:32.105177 DQM0 = 126, DQM1 = 120
8036 23:11:32.108198 DQ Delay:
8037 23:11:32.111752 DQ0 =126, DQ1 =128, DQ2 =126, DQ3 =122
8038 23:11:32.114944 DQ4 =126, DQ5 =114, DQ6 =134, DQ7 =138
8039 23:11:32.118586 DQ8 =112, DQ9 =108, DQ10 =120, DQ11 =114
8040 23:11:32.121661 DQ12 =126, DQ13 =124, DQ14 =130, DQ15 =128
8041 23:11:32.121729
8042 23:11:32.121793
8043 23:11:32.121854
8044 23:11:32.124872 [DramC_TX_OE_Calibration] TA2
8045 23:11:32.128521 Original DQ_B0 (3 6) =30, OEN = 27
8046 23:11:32.131553 Original DQ_B1 (3 6) =30, OEN = 27
8047 23:11:32.134867 24, 0x0, End_B0=24 End_B1=24
8048 23:11:32.134945 25, 0x0, End_B0=25 End_B1=25
8049 23:11:32.138389 26, 0x0, End_B0=26 End_B1=26
8050 23:11:32.141446 27, 0x0, End_B0=27 End_B1=27
8051 23:11:32.145053 28, 0x0, End_B0=28 End_B1=28
8052 23:11:32.145129 29, 0x0, End_B0=29 End_B1=29
8053 23:11:32.148085 30, 0x0, End_B0=30 End_B1=30
8054 23:11:32.151620 31, 0x4141, End_B0=30 End_B1=30
8055 23:11:32.154738 Byte0 end_step=30 best_step=27
8056 23:11:32.158205 Byte1 end_step=30 best_step=27
8057 23:11:32.161494 Byte0 TX OE(2T, 0.5T) = (3, 3)
8058 23:11:32.164857 Byte1 TX OE(2T, 0.5T) = (3, 3)
8059 23:11:32.164940
8060 23:11:32.165005
8061 23:11:32.171546 [DQSOSCAuto] RK0, (LSB)MR18= 0x1312, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 400 ps
8062 23:11:32.175238 CH0 RK0: MR19=303, MR18=1312
8063 23:11:32.181187 CH0_RK0: MR19=0x303, MR18=0x1312, DQSOSC=400, MR23=63, INC=23, DEC=15
8064 23:11:32.181270
8065 23:11:32.184883 ----->DramcWriteLeveling(PI) begin...
8066 23:11:32.184967 ==
8067 23:11:32.187660 Dram Type= 6, Freq= 0, CH_0, rank 1
8068 23:11:32.191154 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8069 23:11:32.191237 ==
8070 23:11:32.194362 Write leveling (Byte 0): 31 => 31
8071 23:11:32.198021 Write leveling (Byte 1): 29 => 29
8072 23:11:32.201335 DramcWriteLeveling(PI) end<-----
8073 23:11:32.201417
8074 23:11:32.201508 ==
8075 23:11:32.204407 Dram Type= 6, Freq= 0, CH_0, rank 1
8076 23:11:32.207725 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8077 23:11:32.207808 ==
8078 23:11:32.211292 [Gating] SW mode calibration
8079 23:11:32.217871 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8080 23:11:32.224248 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8081 23:11:32.227788 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8082 23:11:32.234101 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8083 23:11:32.237822 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8084 23:11:32.240816 1 4 12 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
8085 23:11:32.247745 1 4 16 | B1->B0 | 2c2c 3434 | 0 1 | (0 0) (1 1)
8086 23:11:32.250533 1 4 20 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8087 23:11:32.253984 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8088 23:11:32.260510 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8089 23:11:32.263926 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8090 23:11:32.267539 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8091 23:11:32.274149 1 5 8 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
8092 23:11:32.277249 1 5 12 | B1->B0 | 3434 2c2c | 1 0 | (1 1) (1 0)
8093 23:11:32.280468 1 5 16 | B1->B0 | 3131 2323 | 0 0 | (0 0) (0 0)
8094 23:11:32.286925 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8095 23:11:32.290352 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8096 23:11:32.293808 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8097 23:11:32.300585 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8098 23:11:32.303614 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8099 23:11:32.307388 1 6 8 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
8100 23:11:32.310437 1 6 12 | B1->B0 | 2323 3b3b | 0 0 | (0 0) (0 0)
8101 23:11:32.316659 1 6 16 | B1->B0 | 3131 4646 | 0 0 | (0 0) (0 0)
8102 23:11:32.320087 1 6 20 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
8103 23:11:32.323705 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8104 23:11:32.329930 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8105 23:11:32.333211 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8106 23:11:32.336737 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8107 23:11:32.343523 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8108 23:11:32.346677 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8109 23:11:32.353051 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8110 23:11:32.356614 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8111 23:11:32.359758 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8112 23:11:32.363131 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8113 23:11:32.369623 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8114 23:11:32.372923 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8115 23:11:32.376290 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8116 23:11:32.382740 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8117 23:11:32.386108 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8118 23:11:32.389333 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8119 23:11:32.395909 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8120 23:11:32.399939 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8121 23:11:32.402519 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8122 23:11:32.409306 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8123 23:11:32.412257 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8124 23:11:32.415855 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8125 23:11:32.418973 Total UI for P1: 0, mck2ui 16
8126 23:11:32.422472 best dqsien dly found for B0: ( 1, 9, 8)
8127 23:11:32.429300 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8128 23:11:32.432608 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8129 23:11:32.435786 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8130 23:11:32.438927 Total UI for P1: 0, mck2ui 16
8131 23:11:32.442492 best dqsien dly found for B1: ( 1, 9, 16)
8132 23:11:32.445767 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8133 23:11:32.452385 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8134 23:11:32.452467
8135 23:11:32.455434 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8136 23:11:32.458644 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8137 23:11:32.462253 [Gating] SW calibration Done
8138 23:11:32.462335 ==
8139 23:11:32.465395 Dram Type= 6, Freq= 0, CH_0, rank 1
8140 23:11:32.468880 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8141 23:11:32.468963 ==
8142 23:11:32.471825 RX Vref Scan: 0
8143 23:11:32.471907
8144 23:11:32.471973 RX Vref 0 -> 0, step: 1
8145 23:11:32.472034
8146 23:11:32.475493 RX Delay 0 -> 252, step: 8
8147 23:11:32.478368 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8148 23:11:32.482013 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8149 23:11:32.488372 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8150 23:11:32.492240 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
8151 23:11:32.495364 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8152 23:11:32.498389 iDelay=200, Bit 5, Center 111 (56 ~ 167) 112
8153 23:11:32.501615 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8154 23:11:32.508203 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8155 23:11:32.511684 iDelay=200, Bit 8, Center 111 (48 ~ 175) 128
8156 23:11:32.515029 iDelay=200, Bit 9, Center 107 (48 ~ 167) 120
8157 23:11:32.518729 iDelay=200, Bit 10, Center 119 (56 ~ 183) 128
8158 23:11:32.521671 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8159 23:11:32.528311 iDelay=200, Bit 12, Center 127 (64 ~ 191) 128
8160 23:11:32.531452 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
8161 23:11:32.535009 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8162 23:11:32.538058 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
8163 23:11:32.538141 ==
8164 23:11:32.541802 Dram Type= 6, Freq= 0, CH_0, rank 1
8165 23:11:32.548079 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8166 23:11:32.548161 ==
8167 23:11:32.548227 DQS Delay:
8168 23:11:32.551231 DQS0 = 0, DQS1 = 0
8169 23:11:32.551313 DQM Delay:
8170 23:11:32.554744 DQM0 = 127, DQM1 = 120
8171 23:11:32.554825 DQ Delay:
8172 23:11:32.557857 DQ0 =127, DQ1 =127, DQ2 =123, DQ3 =123
8173 23:11:32.561033 DQ4 =127, DQ5 =111, DQ6 =139, DQ7 =139
8174 23:11:32.564736 DQ8 =111, DQ9 =107, DQ10 =119, DQ11 =115
8175 23:11:32.568227 DQ12 =127, DQ13 =127, DQ14 =131, DQ15 =127
8176 23:11:32.568309
8177 23:11:32.568373
8178 23:11:32.568436 ==
8179 23:11:32.571269 Dram Type= 6, Freq= 0, CH_0, rank 1
8180 23:11:32.577439 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8181 23:11:32.577561 ==
8182 23:11:32.577628
8183 23:11:32.577688
8184 23:11:32.577746 TX Vref Scan disable
8185 23:11:32.581466 == TX Byte 0 ==
8186 23:11:32.584583 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
8187 23:11:32.590995 Update DQM dly =987 (3 ,6, 27) DQM OEN =(3 ,3)
8188 23:11:32.591078 == TX Byte 1 ==
8189 23:11:32.594449 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8190 23:11:32.600918 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8191 23:11:32.601000 ==
8192 23:11:32.604526 Dram Type= 6, Freq= 0, CH_0, rank 1
8193 23:11:32.607745 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8194 23:11:32.607828 ==
8195 23:11:32.621441
8196 23:11:32.624487 TX Vref early break, caculate TX vref
8197 23:11:32.628024 TX Vref=16, minBit 0, minWin=22, winSum=366
8198 23:11:32.631160 TX Vref=18, minBit 0, minWin=23, winSum=375
8199 23:11:32.634990 TX Vref=20, minBit 0, minWin=23, winSum=387
8200 23:11:32.637793 TX Vref=22, minBit 1, minWin=24, winSum=399
8201 23:11:32.641110 TX Vref=24, minBit 0, minWin=24, winSum=397
8202 23:11:32.647984 TX Vref=26, minBit 1, minWin=25, winSum=412
8203 23:11:32.651348 TX Vref=28, minBit 0, minWin=25, winSum=414
8204 23:11:32.654521 TX Vref=30, minBit 3, minWin=25, winSum=409
8205 23:11:32.657911 TX Vref=32, minBit 8, minWin=23, winSum=400
8206 23:11:32.661326 TX Vref=34, minBit 8, minWin=23, winSum=394
8207 23:11:32.664723 TX Vref=36, minBit 8, minWin=21, winSum=380
8208 23:11:32.671249 [TxChooseVref] Worse bit 0, Min win 25, Win sum 414, Final Vref 28
8209 23:11:32.671339
8210 23:11:32.674331 Final TX Range 0 Vref 28
8211 23:11:32.674416
8212 23:11:32.674482 ==
8213 23:11:32.677648 Dram Type= 6, Freq= 0, CH_0, rank 1
8214 23:11:32.681158 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8215 23:11:32.681243 ==
8216 23:11:32.681310
8217 23:11:32.681372
8218 23:11:32.684215 TX Vref Scan disable
8219 23:11:32.690941 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8220 23:11:32.691026 == TX Byte 0 ==
8221 23:11:32.694231 u2DelayCellOfst[0]=11 cells (3 PI)
8222 23:11:32.697593 u2DelayCellOfst[1]=18 cells (5 PI)
8223 23:11:32.700841 u2DelayCellOfst[2]=11 cells (3 PI)
8224 23:11:32.704269 u2DelayCellOfst[3]=11 cells (3 PI)
8225 23:11:32.707610 u2DelayCellOfst[4]=7 cells (2 PI)
8226 23:11:32.711313 u2DelayCellOfst[5]=0 cells (0 PI)
8227 23:11:32.714467 u2DelayCellOfst[6]=18 cells (5 PI)
8228 23:11:32.717729 u2DelayCellOfst[7]=18 cells (5 PI)
8229 23:11:32.720815 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
8230 23:11:32.724305 Update DQM dly =987 (3 ,6, 27) DQM OEN =(3 ,3)
8231 23:11:32.727373 == TX Byte 1 ==
8232 23:11:32.730840 u2DelayCellOfst[8]=0 cells (0 PI)
8233 23:11:32.730925 u2DelayCellOfst[9]=0 cells (0 PI)
8234 23:11:32.734453 u2DelayCellOfst[10]=3 cells (1 PI)
8235 23:11:32.737601 u2DelayCellOfst[11]=3 cells (1 PI)
8236 23:11:32.740694 u2DelayCellOfst[12]=11 cells (3 PI)
8237 23:11:32.743945 u2DelayCellOfst[13]=11 cells (3 PI)
8238 23:11:32.747143 u2DelayCellOfst[14]=11 cells (3 PI)
8239 23:11:32.750655 u2DelayCellOfst[15]=7 cells (2 PI)
8240 23:11:32.753916 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8241 23:11:32.760897 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8242 23:11:32.760985 DramC Write-DBI on
8243 23:11:32.761054 ==
8244 23:11:32.763928 Dram Type= 6, Freq= 0, CH_0, rank 1
8245 23:11:32.770486 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8246 23:11:32.770576 ==
8247 23:11:32.770644
8248 23:11:32.770705
8249 23:11:32.770763 TX Vref Scan disable
8250 23:11:32.774843 == TX Byte 0 ==
8251 23:11:32.777912 Update DQM dly =731 (2 ,6, 27) DQM OEN =(3 ,3)
8252 23:11:32.780879 == TX Byte 1 ==
8253 23:11:32.784571 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8254 23:11:32.787447 DramC Write-DBI off
8255 23:11:32.787530
8256 23:11:32.787597 [DATLAT]
8257 23:11:32.787658 Freq=1600, CH0 RK1
8258 23:11:32.787718
8259 23:11:32.791015 DATLAT Default: 0xf
8260 23:11:32.794558 0, 0xFFFF, sum = 0
8261 23:11:32.794643 1, 0xFFFF, sum = 0
8262 23:11:32.797406 2, 0xFFFF, sum = 0
8263 23:11:32.797527 3, 0xFFFF, sum = 0
8264 23:11:32.801174 4, 0xFFFF, sum = 0
8265 23:11:32.801258 5, 0xFFFF, sum = 0
8266 23:11:32.804458 6, 0xFFFF, sum = 0
8267 23:11:32.804542 7, 0xFFFF, sum = 0
8268 23:11:32.807395 8, 0xFFFF, sum = 0
8269 23:11:32.807479 9, 0xFFFF, sum = 0
8270 23:11:32.811180 10, 0xFFFF, sum = 0
8271 23:11:32.811265 11, 0xFFFF, sum = 0
8272 23:11:32.814230 12, 0xFFFF, sum = 0
8273 23:11:32.814314 13, 0xCFFF, sum = 0
8274 23:11:32.817439 14, 0x0, sum = 1
8275 23:11:32.817541 15, 0x0, sum = 2
8276 23:11:32.820735 16, 0x0, sum = 3
8277 23:11:32.820820 17, 0x0, sum = 4
8278 23:11:32.824422 best_step = 15
8279 23:11:32.824506
8280 23:11:32.824571 ==
8281 23:11:32.827561 Dram Type= 6, Freq= 0, CH_0, rank 1
8282 23:11:32.830556 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8283 23:11:32.830643 ==
8284 23:11:32.834154 RX Vref Scan: 0
8285 23:11:32.834239
8286 23:11:32.834305 RX Vref 0 -> 0, step: 1
8287 23:11:32.834367
8288 23:11:32.837159 RX Delay 3 -> 252, step: 4
8289 23:11:32.844142 iDelay=191, Bit 0, Center 124 (71 ~ 178) 108
8290 23:11:32.847171 iDelay=191, Bit 1, Center 126 (75 ~ 178) 104
8291 23:11:32.850920 iDelay=191, Bit 2, Center 122 (71 ~ 174) 104
8292 23:11:32.853887 iDelay=191, Bit 3, Center 122 (67 ~ 178) 112
8293 23:11:32.857463 iDelay=191, Bit 4, Center 124 (71 ~ 178) 108
8294 23:11:32.860723 iDelay=191, Bit 5, Center 112 (59 ~ 166) 108
8295 23:11:32.867172 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8296 23:11:32.870784 iDelay=191, Bit 7, Center 134 (79 ~ 190) 112
8297 23:11:32.873938 iDelay=191, Bit 8, Center 112 (55 ~ 170) 116
8298 23:11:32.877395 iDelay=191, Bit 9, Center 104 (47 ~ 162) 116
8299 23:11:32.880760 iDelay=191, Bit 10, Center 118 (59 ~ 178) 120
8300 23:11:32.887486 iDelay=191, Bit 11, Center 112 (55 ~ 170) 116
8301 23:11:32.890673 iDelay=191, Bit 12, Center 124 (67 ~ 182) 116
8302 23:11:32.893866 iDelay=191, Bit 13, Center 124 (67 ~ 182) 116
8303 23:11:32.897222 iDelay=191, Bit 14, Center 128 (71 ~ 186) 116
8304 23:11:32.900456 iDelay=191, Bit 15, Center 124 (67 ~ 182) 116
8305 23:11:32.904031 ==
8306 23:11:32.907214 Dram Type= 6, Freq= 0, CH_0, rank 1
8307 23:11:32.910716 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8308 23:11:32.910805 ==
8309 23:11:32.910873 DQS Delay:
8310 23:11:32.913859 DQS0 = 0, DQS1 = 0
8311 23:11:32.913945 DQM Delay:
8312 23:11:32.916899 DQM0 = 124, DQM1 = 118
8313 23:11:32.916983 DQ Delay:
8314 23:11:32.920657 DQ0 =124, DQ1 =126, DQ2 =122, DQ3 =122
8315 23:11:32.923736 DQ4 =124, DQ5 =112, DQ6 =134, DQ7 =134
8316 23:11:32.927280 DQ8 =112, DQ9 =104, DQ10 =118, DQ11 =112
8317 23:11:32.930448 DQ12 =124, DQ13 =124, DQ14 =128, DQ15 =124
8318 23:11:32.930537
8319 23:11:32.930603
8320 23:11:32.930663
8321 23:11:32.933904 [DramC_TX_OE_Calibration] TA2
8322 23:11:32.937094 Original DQ_B0 (3 6) =30, OEN = 27
8323 23:11:32.940245 Original DQ_B1 (3 6) =30, OEN = 27
8324 23:11:32.944005 24, 0x0, End_B0=24 End_B1=24
8325 23:11:32.947053 25, 0x0, End_B0=25 End_B1=25
8326 23:11:32.947142 26, 0x0, End_B0=26 End_B1=26
8327 23:11:32.950284 27, 0x0, End_B0=27 End_B1=27
8328 23:11:32.953925 28, 0x0, End_B0=28 End_B1=28
8329 23:11:32.956832 29, 0x0, End_B0=29 End_B1=29
8330 23:11:32.960265 30, 0x0, End_B0=30 End_B1=30
8331 23:11:32.960361 31, 0x4141, End_B0=30 End_B1=30
8332 23:11:32.963558 Byte0 end_step=30 best_step=27
8333 23:11:32.966769 Byte1 end_step=30 best_step=27
8334 23:11:32.970500 Byte0 TX OE(2T, 0.5T) = (3, 3)
8335 23:11:32.973676 Byte1 TX OE(2T, 0.5T) = (3, 3)
8336 23:11:32.973765
8337 23:11:32.973832
8338 23:11:32.979898 [DQSOSCAuto] RK1, (LSB)MR18= 0x2210, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 392 ps
8339 23:11:32.983646 CH0 RK1: MR19=303, MR18=2210
8340 23:11:32.990097 CH0_RK1: MR19=0x303, MR18=0x2210, DQSOSC=392, MR23=63, INC=24, DEC=16
8341 23:11:32.993461 [RxdqsGatingPostProcess] freq 1600
8342 23:11:33.000198 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8343 23:11:33.003164 best DQS0 dly(2T, 0.5T) = (1, 1)
8344 23:11:33.003262 best DQS1 dly(2T, 0.5T) = (1, 1)
8345 23:11:33.006297 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8346 23:11:33.009882 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8347 23:11:33.013102 best DQS0 dly(2T, 0.5T) = (1, 1)
8348 23:11:33.016343 best DQS1 dly(2T, 0.5T) = (1, 1)
8349 23:11:33.019898 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8350 23:11:33.023159 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8351 23:11:33.026409 Pre-setting of DQS Precalculation
8352 23:11:33.029698 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8353 23:11:33.032942 ==
8354 23:11:33.036436 Dram Type= 6, Freq= 0, CH_1, rank 0
8355 23:11:33.039252 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8356 23:11:33.039340 ==
8357 23:11:33.042932 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8358 23:11:33.049256 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8359 23:11:33.052851 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8360 23:11:33.059633 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8361 23:11:33.067902 [CA 0] Center 41 (12~70) winsize 59
8362 23:11:33.071159 [CA 1] Center 42 (12~72) winsize 61
8363 23:11:33.074240 [CA 2] Center 37 (8~66) winsize 59
8364 23:11:33.077335 [CA 3] Center 36 (7~66) winsize 60
8365 23:11:33.081044 [CA 4] Center 37 (8~67) winsize 60
8366 23:11:33.084212 [CA 5] Center 36 (7~66) winsize 60
8367 23:11:33.084300
8368 23:11:33.087826 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8369 23:11:33.087912
8370 23:11:33.090834 [CATrainingPosCal] consider 1 rank data
8371 23:11:33.094313 u2DelayCellTimex100 = 258/100 ps
8372 23:11:33.097427 CA0 delay=41 (12~70),Diff = 5 PI (18 cell)
8373 23:11:33.104196 CA1 delay=42 (12~72),Diff = 6 PI (22 cell)
8374 23:11:33.107811 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8375 23:11:33.110850 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8376 23:11:33.114161 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8377 23:11:33.117402 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8378 23:11:33.117530
8379 23:11:33.120961 CA PerBit enable=1, Macro0, CA PI delay=36
8380 23:11:33.121044
8381 23:11:33.124200 [CBTSetCACLKResult] CA Dly = 36
8382 23:11:33.127236 CS Dly: 9 (0~40)
8383 23:11:33.130841 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8384 23:11:33.133827 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8385 23:11:33.133914 ==
8386 23:11:33.137449 Dram Type= 6, Freq= 0, CH_1, rank 1
8387 23:11:33.140500 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8388 23:11:33.140588 ==
8389 23:11:33.147783 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8390 23:11:33.151028 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8391 23:11:33.157084 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8392 23:11:33.160597 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8393 23:11:33.170908 [CA 0] Center 42 (13~72) winsize 60
8394 23:11:33.174362 [CA 1] Center 42 (12~72) winsize 61
8395 23:11:33.177431 [CA 2] Center 38 (9~67) winsize 59
8396 23:11:33.180869 [CA 3] Center 36 (7~66) winsize 60
8397 23:11:33.184035 [CA 4] Center 38 (8~68) winsize 61
8398 23:11:33.187812 [CA 5] Center 36 (6~67) winsize 62
8399 23:11:33.187904
8400 23:11:33.191114 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8401 23:11:33.191200
8402 23:11:33.194278 [CATrainingPosCal] consider 2 rank data
8403 23:11:33.197263 u2DelayCellTimex100 = 258/100 ps
8404 23:11:33.200769 CA0 delay=41 (13~70),Diff = 5 PI (18 cell)
8405 23:11:33.207362 CA1 delay=42 (12~72),Diff = 6 PI (22 cell)
8406 23:11:33.210818 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8407 23:11:33.213960 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8408 23:11:33.217490 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8409 23:11:33.220540 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8410 23:11:33.220629
8411 23:11:33.223737 CA PerBit enable=1, Macro0, CA PI delay=36
8412 23:11:33.223823
8413 23:11:33.226914 [CBTSetCACLKResult] CA Dly = 36
8414 23:11:33.230587 CS Dly: 10 (0~43)
8415 23:11:33.233677 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8416 23:11:33.237261 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8417 23:11:33.237351
8418 23:11:33.240255 ----->DramcWriteLeveling(PI) begin...
8419 23:11:33.240342 ==
8420 23:11:33.243622 Dram Type= 6, Freq= 0, CH_1, rank 0
8421 23:11:33.247262 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8422 23:11:33.250413 ==
8423 23:11:33.253888 Write leveling (Byte 0): 25 => 25
8424 23:11:33.253977 Write leveling (Byte 1): 29 => 29
8425 23:11:33.257080 DramcWriteLeveling(PI) end<-----
8426 23:11:33.257166
8427 23:11:33.257233 ==
8428 23:11:33.260225 Dram Type= 6, Freq= 0, CH_1, rank 0
8429 23:11:33.267030 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8430 23:11:33.267129 ==
8431 23:11:33.270049 [Gating] SW mode calibration
8432 23:11:33.276632 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8433 23:11:33.280313 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8434 23:11:33.286618 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8435 23:11:33.290423 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8436 23:11:33.293329 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8437 23:11:33.299917 1 4 12 | B1->B0 | 2625 2323 | 1 0 | (1 1) (0 0)
8438 23:11:33.303385 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (0 0) (0 0)
8439 23:11:33.306876 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8440 23:11:33.313390 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8441 23:11:33.316325 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8442 23:11:33.319959 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8443 23:11:33.326766 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8444 23:11:33.329897 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8445 23:11:33.333045 1 5 12 | B1->B0 | 3333 3434 | 1 0 | (1 1) (0 1)
8446 23:11:33.339585 1 5 16 | B1->B0 | 2a2a 2d2d | 0 0 | (1 0) (1 0)
8447 23:11:33.342790 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
8448 23:11:33.346292 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8449 23:11:33.352850 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8450 23:11:33.355903 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8451 23:11:33.359677 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8452 23:11:33.365808 1 6 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8453 23:11:33.369395 1 6 12 | B1->B0 | 3232 2827 | 0 1 | (0 0) (0 0)
8454 23:11:33.372635 1 6 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8455 23:11:33.379452 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8456 23:11:33.382468 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8457 23:11:33.385821 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8458 23:11:33.392296 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8459 23:11:33.395981 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8460 23:11:33.398870 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8461 23:11:33.405420 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8462 23:11:33.408893 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8463 23:11:33.412214 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8464 23:11:33.418641 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8465 23:11:33.421871 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8466 23:11:33.425310 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8467 23:11:33.431877 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8468 23:11:33.435390 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8469 23:11:33.438579 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8470 23:11:33.445318 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8471 23:11:33.448501 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8472 23:11:33.452107 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8473 23:11:33.458651 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8474 23:11:33.461814 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8475 23:11:33.465239 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8476 23:11:33.471587 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8477 23:11:33.474786 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8478 23:11:33.478051 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8479 23:11:33.484566 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8480 23:11:33.484649 Total UI for P1: 0, mck2ui 16
8481 23:11:33.488515 best dqsien dly found for B0: ( 1, 9, 14)
8482 23:11:33.491743 Total UI for P1: 0, mck2ui 16
8483 23:11:33.494505 best dqsien dly found for B1: ( 1, 9, 16)
8484 23:11:33.501224 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8485 23:11:33.504660 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8486 23:11:33.504742
8487 23:11:33.507929 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8488 23:11:33.511582 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8489 23:11:33.514760 [Gating] SW calibration Done
8490 23:11:33.514844 ==
8491 23:11:33.517826 Dram Type= 6, Freq= 0, CH_1, rank 0
8492 23:11:33.521293 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8493 23:11:33.521376 ==
8494 23:11:33.524612 RX Vref Scan: 0
8495 23:11:33.524695
8496 23:11:33.524760 RX Vref 0 -> 0, step: 1
8497 23:11:33.524821
8498 23:11:33.527781 RX Delay 0 -> 252, step: 8
8499 23:11:33.531342 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8500 23:11:33.538139 iDelay=200, Bit 1, Center 123 (64 ~ 183) 120
8501 23:11:33.541002 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8502 23:11:33.544768 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8503 23:11:33.547931 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8504 23:11:33.550892 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8505 23:11:33.554259 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8506 23:11:33.561132 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8507 23:11:33.564511 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8508 23:11:33.567956 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8509 23:11:33.570853 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8510 23:11:33.577753 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8511 23:11:33.580801 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8512 23:11:33.584521 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8513 23:11:33.587631 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8514 23:11:33.591051 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8515 23:11:33.591134 ==
8516 23:11:33.594080 Dram Type= 6, Freq= 0, CH_1, rank 0
8517 23:11:33.600707 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8518 23:11:33.600793 ==
8519 23:11:33.600860 DQS Delay:
8520 23:11:33.603927 DQS0 = 0, DQS1 = 0
8521 23:11:33.604009 DQM Delay:
8522 23:11:33.607405 DQM0 = 131, DQM1 = 126
8523 23:11:33.607487 DQ Delay:
8524 23:11:33.610594 DQ0 =135, DQ1 =123, DQ2 =119, DQ3 =131
8525 23:11:33.614263 DQ4 =127, DQ5 =143, DQ6 =143, DQ7 =131
8526 23:11:33.617294 DQ8 =111, DQ9 =115, DQ10 =123, DQ11 =119
8527 23:11:33.620950 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8528 23:11:33.621033
8529 23:11:33.621099
8530 23:11:33.621158 ==
8531 23:11:33.623849 Dram Type= 6, Freq= 0, CH_1, rank 0
8532 23:11:33.630660 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8533 23:11:33.630743 ==
8534 23:11:33.630809
8535 23:11:33.630869
8536 23:11:33.630927 TX Vref Scan disable
8537 23:11:33.634390 == TX Byte 0 ==
8538 23:11:33.637146 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8539 23:11:33.644226 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8540 23:11:33.644309 == TX Byte 1 ==
8541 23:11:33.647384 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8542 23:11:33.653752 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8543 23:11:33.653835 ==
8544 23:11:33.657262 Dram Type= 6, Freq= 0, CH_1, rank 0
8545 23:11:33.660584 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8546 23:11:33.660667 ==
8547 23:11:33.672742
8548 23:11:33.676387 TX Vref early break, caculate TX vref
8549 23:11:33.679637 TX Vref=16, minBit 8, minWin=21, winSum=360
8550 23:11:33.682826 TX Vref=18, minBit 9, minWin=21, winSum=368
8551 23:11:33.686457 TX Vref=20, minBit 11, minWin=22, winSum=377
8552 23:11:33.689438 TX Vref=22, minBit 8, minWin=22, winSum=385
8553 23:11:33.692641 TX Vref=24, minBit 11, minWin=23, winSum=397
8554 23:11:33.699889 TX Vref=26, minBit 11, minWin=24, winSum=406
8555 23:11:33.703007 TX Vref=28, minBit 0, minWin=25, winSum=413
8556 23:11:33.706417 TX Vref=30, minBit 0, minWin=25, winSum=411
8557 23:11:33.709402 TX Vref=32, minBit 0, minWin=24, winSum=397
8558 23:11:33.713014 TX Vref=34, minBit 0, minWin=23, winSum=389
8559 23:11:33.719171 [TxChooseVref] Worse bit 0, Min win 25, Win sum 413, Final Vref 28
8560 23:11:33.719255
8561 23:11:33.722712 Final TX Range 0 Vref 28
8562 23:11:33.722795
8563 23:11:33.722861 ==
8564 23:11:33.725807 Dram Type= 6, Freq= 0, CH_1, rank 0
8565 23:11:33.729274 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8566 23:11:33.729359 ==
8567 23:11:33.729426
8568 23:11:33.729534
8569 23:11:33.732359 TX Vref Scan disable
8570 23:11:33.738904 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8571 23:11:33.738991 == TX Byte 0 ==
8572 23:11:33.742325 u2DelayCellOfst[0]=18 cells (5 PI)
8573 23:11:33.745731 u2DelayCellOfst[1]=11 cells (3 PI)
8574 23:11:33.749029 u2DelayCellOfst[2]=0 cells (0 PI)
8575 23:11:33.752636 u2DelayCellOfst[3]=3 cells (1 PI)
8576 23:11:33.755642 u2DelayCellOfst[4]=7 cells (2 PI)
8577 23:11:33.759275 u2DelayCellOfst[5]=22 cells (6 PI)
8578 23:11:33.762384 u2DelayCellOfst[6]=18 cells (5 PI)
8579 23:11:33.765389 u2DelayCellOfst[7]=7 cells (2 PI)
8580 23:11:33.769096 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8581 23:11:33.772279 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8582 23:11:33.775135 == TX Byte 1 ==
8583 23:11:33.778738 u2DelayCellOfst[8]=0 cells (0 PI)
8584 23:11:33.778824 u2DelayCellOfst[9]=7 cells (2 PI)
8585 23:11:33.782327 u2DelayCellOfst[10]=11 cells (3 PI)
8586 23:11:33.785502 u2DelayCellOfst[11]=7 cells (2 PI)
8587 23:11:33.788900 u2DelayCellOfst[12]=15 cells (4 PI)
8588 23:11:33.792205 u2DelayCellOfst[13]=18 cells (5 PI)
8589 23:11:33.795356 u2DelayCellOfst[14]=18 cells (5 PI)
8590 23:11:33.798773 u2DelayCellOfst[15]=18 cells (5 PI)
8591 23:11:33.805286 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8592 23:11:33.808421 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8593 23:11:33.808505 DramC Write-DBI on
8594 23:11:33.808571 ==
8595 23:11:33.811578 Dram Type= 6, Freq= 0, CH_1, rank 0
8596 23:11:33.818165 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8597 23:11:33.818253 ==
8598 23:11:33.818320
8599 23:11:33.818381
8600 23:11:33.818440 TX Vref Scan disable
8601 23:11:33.822342 == TX Byte 0 ==
8602 23:11:33.825691 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8603 23:11:33.829354 == TX Byte 1 ==
8604 23:11:33.832144 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8605 23:11:33.835715 DramC Write-DBI off
8606 23:11:33.835800
8607 23:11:33.835866 [DATLAT]
8608 23:11:33.835927 Freq=1600, CH1 RK0
8609 23:11:33.835986
8610 23:11:33.838910 DATLAT Default: 0xf
8611 23:11:33.842495 0, 0xFFFF, sum = 0
8612 23:11:33.842583 1, 0xFFFF, sum = 0
8613 23:11:33.845628 2, 0xFFFF, sum = 0
8614 23:11:33.845717 3, 0xFFFF, sum = 0
8615 23:11:33.848624 4, 0xFFFF, sum = 0
8616 23:11:33.848701 5, 0xFFFF, sum = 0
8617 23:11:33.852178 6, 0xFFFF, sum = 0
8618 23:11:33.852263 7, 0xFFFF, sum = 0
8619 23:11:33.855214 8, 0xFFFF, sum = 0
8620 23:11:33.855298 9, 0xFFFF, sum = 0
8621 23:11:33.858795 10, 0xFFFF, sum = 0
8622 23:11:33.858880 11, 0xFFFF, sum = 0
8623 23:11:33.862232 12, 0xFFFF, sum = 0
8624 23:11:33.862316 13, 0x8FFF, sum = 0
8625 23:11:33.865344 14, 0x0, sum = 1
8626 23:11:33.865430 15, 0x0, sum = 2
8627 23:11:33.868800 16, 0x0, sum = 3
8628 23:11:33.868895 17, 0x0, sum = 4
8629 23:11:33.871912 best_step = 15
8630 23:11:33.871999
8631 23:11:33.872066 ==
8632 23:11:33.875078 Dram Type= 6, Freq= 0, CH_1, rank 0
8633 23:11:33.878805 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8634 23:11:33.878894 ==
8635 23:11:33.881989 RX Vref Scan: 1
8636 23:11:33.882077
8637 23:11:33.882143 Set Vref Range= 24 -> 127
8638 23:11:33.882205
8639 23:11:33.885229 RX Vref 24 -> 127, step: 1
8640 23:11:33.885312
8641 23:11:33.888398 RX Delay 11 -> 252, step: 4
8642 23:11:33.888485
8643 23:11:33.892032 Set Vref, RX VrefLevel [Byte0]: 24
8644 23:11:33.895218 [Byte1]: 24
8645 23:11:33.895308
8646 23:11:33.898370 Set Vref, RX VrefLevel [Byte0]: 25
8647 23:11:33.901802 [Byte1]: 25
8648 23:11:33.905286
8649 23:11:33.905409 Set Vref, RX VrefLevel [Byte0]: 26
8650 23:11:33.908659 [Byte1]: 26
8651 23:11:33.913227
8652 23:11:33.913312 Set Vref, RX VrefLevel [Byte0]: 27
8653 23:11:33.916233 [Byte1]: 27
8654 23:11:33.920642
8655 23:11:33.920730 Set Vref, RX VrefLevel [Byte0]: 28
8656 23:11:33.923853 [Byte1]: 28
8657 23:11:33.928308
8658 23:11:33.928398 Set Vref, RX VrefLevel [Byte0]: 29
8659 23:11:33.931235 [Byte1]: 29
8660 23:11:33.935614
8661 23:11:33.935706 Set Vref, RX VrefLevel [Byte0]: 30
8662 23:11:33.938803 [Byte1]: 30
8663 23:11:33.943318
8664 23:11:33.943402 Set Vref, RX VrefLevel [Byte0]: 31
8665 23:11:33.946701 [Byte1]: 31
8666 23:11:33.950765
8667 23:11:33.950850 Set Vref, RX VrefLevel [Byte0]: 32
8668 23:11:33.954390 [Byte1]: 32
8669 23:11:33.958666
8670 23:11:33.958757 Set Vref, RX VrefLevel [Byte0]: 33
8671 23:11:33.961944 [Byte1]: 33
8672 23:11:33.966196
8673 23:11:33.966285 Set Vref, RX VrefLevel [Byte0]: 34
8674 23:11:33.969708 [Byte1]: 34
8675 23:11:33.973730
8676 23:11:33.973816 Set Vref, RX VrefLevel [Byte0]: 35
8677 23:11:33.976855 [Byte1]: 35
8678 23:11:33.981207
8679 23:11:33.981298 Set Vref, RX VrefLevel [Byte0]: 36
8680 23:11:33.984490 [Byte1]: 36
8681 23:11:33.989060
8682 23:11:33.989148 Set Vref, RX VrefLevel [Byte0]: 37
8683 23:11:33.992210 [Byte1]: 37
8684 23:11:33.996396
8685 23:11:33.996484 Set Vref, RX VrefLevel [Byte0]: 38
8686 23:11:33.999634 [Byte1]: 38
8687 23:11:34.004211
8688 23:11:34.004303 Set Vref, RX VrefLevel [Byte0]: 39
8689 23:11:34.007311 [Byte1]: 39
8690 23:11:34.011600
8691 23:11:34.011691 Set Vref, RX VrefLevel [Byte0]: 40
8692 23:11:34.014905 [Byte1]: 40
8693 23:11:34.019304
8694 23:11:34.019401 Set Vref, RX VrefLevel [Byte0]: 41
8695 23:11:34.022960 [Byte1]: 41
8696 23:11:34.027108
8697 23:11:34.027191 Set Vref, RX VrefLevel [Byte0]: 42
8698 23:11:34.030952 [Byte1]: 42
8699 23:11:34.034649
8700 23:11:34.034732 Set Vref, RX VrefLevel [Byte0]: 43
8701 23:11:34.037864 [Byte1]: 43
8702 23:11:34.042242
8703 23:11:34.042326 Set Vref, RX VrefLevel [Byte0]: 44
8704 23:11:34.045683 [Byte1]: 44
8705 23:11:34.049863
8706 23:11:34.049946 Set Vref, RX VrefLevel [Byte0]: 45
8707 23:11:34.053347 [Byte1]: 45
8708 23:11:34.057295
8709 23:11:34.057379 Set Vref, RX VrefLevel [Byte0]: 46
8710 23:11:34.060945 [Byte1]: 46
8711 23:11:34.065115
8712 23:11:34.065201 Set Vref, RX VrefLevel [Byte0]: 47
8713 23:11:34.068307 [Byte1]: 47
8714 23:11:34.072664
8715 23:11:34.072748 Set Vref, RX VrefLevel [Byte0]: 48
8716 23:11:34.076053 [Byte1]: 48
8717 23:11:34.080233
8718 23:11:34.080317 Set Vref, RX VrefLevel [Byte0]: 49
8719 23:11:34.083535 [Byte1]: 49
8720 23:11:34.087858
8721 23:11:34.087943 Set Vref, RX VrefLevel [Byte0]: 50
8722 23:11:34.091518 [Byte1]: 50
8723 23:11:34.095761
8724 23:11:34.095847 Set Vref, RX VrefLevel [Byte0]: 51
8725 23:11:34.098930 [Byte1]: 51
8726 23:11:34.103240
8727 23:11:34.103326 Set Vref, RX VrefLevel [Byte0]: 52
8728 23:11:34.106379 [Byte1]: 52
8729 23:11:34.110681
8730 23:11:34.110767 Set Vref, RX VrefLevel [Byte0]: 53
8731 23:11:34.114112 [Byte1]: 53
8732 23:11:34.118241
8733 23:11:34.118330 Set Vref, RX VrefLevel [Byte0]: 54
8734 23:11:34.121859 [Byte1]: 54
8735 23:11:34.126073
8736 23:11:34.126158 Set Vref, RX VrefLevel [Byte0]: 55
8737 23:11:34.129179 [Byte1]: 55
8738 23:11:34.133371
8739 23:11:34.133457 Set Vref, RX VrefLevel [Byte0]: 56
8740 23:11:34.136700 [Byte1]: 56
8741 23:11:34.141392
8742 23:11:34.141489 Set Vref, RX VrefLevel [Byte0]: 57
8743 23:11:34.144310 [Byte1]: 57
8744 23:11:34.148808
8745 23:11:34.148894 Set Vref, RX VrefLevel [Byte0]: 58
8746 23:11:34.152280 [Byte1]: 58
8747 23:11:34.156197
8748 23:11:34.156285 Set Vref, RX VrefLevel [Byte0]: 59
8749 23:11:34.159733 [Byte1]: 59
8750 23:11:34.163970
8751 23:11:34.164074 Set Vref, RX VrefLevel [Byte0]: 60
8752 23:11:34.167274 [Byte1]: 60
8753 23:11:34.171787
8754 23:11:34.171896 Set Vref, RX VrefLevel [Byte0]: 61
8755 23:11:34.174819 [Byte1]: 61
8756 23:11:34.179307
8757 23:11:34.179406 Set Vref, RX VrefLevel [Byte0]: 62
8758 23:11:34.182367 [Byte1]: 62
8759 23:11:34.186897
8760 23:11:34.186994 Set Vref, RX VrefLevel [Byte0]: 63
8761 23:11:34.190249 [Byte1]: 63
8762 23:11:34.194385
8763 23:11:34.194481 Set Vref, RX VrefLevel [Byte0]: 64
8764 23:11:34.197512 [Byte1]: 64
8765 23:11:34.202224
8766 23:11:34.202318 Set Vref, RX VrefLevel [Byte0]: 65
8767 23:11:34.205331 [Byte1]: 65
8768 23:11:34.209805
8769 23:11:34.209898 Set Vref, RX VrefLevel [Byte0]: 66
8770 23:11:34.212778 [Byte1]: 66
8771 23:11:34.217459
8772 23:11:34.217556 Set Vref, RX VrefLevel [Byte0]: 67
8773 23:11:34.220562 [Byte1]: 67
8774 23:11:34.224764
8775 23:11:34.224847 Set Vref, RX VrefLevel [Byte0]: 68
8776 23:11:34.228426 [Byte1]: 68
8777 23:11:34.232649
8778 23:11:34.232732 Set Vref, RX VrefLevel [Byte0]: 69
8779 23:11:34.235695 [Byte1]: 69
8780 23:11:34.240089
8781 23:11:34.240172 Set Vref, RX VrefLevel [Byte0]: 70
8782 23:11:34.243219 [Byte1]: 70
8783 23:11:34.247674
8784 23:11:34.247756 Set Vref, RX VrefLevel [Byte0]: 71
8785 23:11:34.250850 [Byte1]: 71
8786 23:11:34.255447
8787 23:11:34.255529 Set Vref, RX VrefLevel [Byte0]: 72
8788 23:11:34.258595 [Byte1]: 72
8789 23:11:34.262755
8790 23:11:34.262838 Final RX Vref Byte 0 = 57 to rank0
8791 23:11:34.266315 Final RX Vref Byte 1 = 56 to rank0
8792 23:11:34.269658 Final RX Vref Byte 0 = 57 to rank1
8793 23:11:34.272923 Final RX Vref Byte 1 = 56 to rank1==
8794 23:11:34.276017 Dram Type= 6, Freq= 0, CH_1, rank 0
8795 23:11:34.282545 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8796 23:11:34.282667 ==
8797 23:11:34.282738 DQS Delay:
8798 23:11:34.286238 DQS0 = 0, DQS1 = 0
8799 23:11:34.286327 DQM Delay:
8800 23:11:34.286393 DQM0 = 131, DQM1 = 123
8801 23:11:34.289185 DQ Delay:
8802 23:11:34.292826 DQ0 =138, DQ1 =126, DQ2 =120, DQ3 =126
8803 23:11:34.295959 DQ4 =126, DQ5 =142, DQ6 =142, DQ7 =128
8804 23:11:34.299156 DQ8 =108, DQ9 =112, DQ10 =122, DQ11 =116
8805 23:11:34.302747 DQ12 =132, DQ13 =132, DQ14 =132, DQ15 =132
8806 23:11:34.302844
8807 23:11:34.302911
8808 23:11:34.302972
8809 23:11:34.306195 [DramC_TX_OE_Calibration] TA2
8810 23:11:34.309360 Original DQ_B0 (3 6) =30, OEN = 27
8811 23:11:34.312481 Original DQ_B1 (3 6) =30, OEN = 27
8812 23:11:34.315985 24, 0x0, End_B0=24 End_B1=24
8813 23:11:34.316081 25, 0x0, End_B0=25 End_B1=25
8814 23:11:34.319152 26, 0x0, End_B0=26 End_B1=26
8815 23:11:34.322344 27, 0x0, End_B0=27 End_B1=27
8816 23:11:34.325627 28, 0x0, End_B0=28 End_B1=28
8817 23:11:34.329164 29, 0x0, End_B0=29 End_B1=29
8818 23:11:34.329251 30, 0x0, End_B0=30 End_B1=30
8819 23:11:34.332187 31, 0x4545, End_B0=30 End_B1=30
8820 23:11:34.335684 Byte0 end_step=30 best_step=27
8821 23:11:34.338833 Byte1 end_step=30 best_step=27
8822 23:11:34.342386 Byte0 TX OE(2T, 0.5T) = (3, 3)
8823 23:11:34.345510 Byte1 TX OE(2T, 0.5T) = (3, 3)
8824 23:11:34.345593
8825 23:11:34.345657
8826 23:11:34.352261 [DQSOSCAuto] RK0, (LSB)MR18= 0x70b, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 406 ps
8827 23:11:34.355425 CH1 RK0: MR19=303, MR18=70B
8828 23:11:34.362108 CH1_RK0: MR19=0x303, MR18=0x70B, DQSOSC=404, MR23=63, INC=22, DEC=15
8829 23:11:34.362192
8830 23:11:34.365671 ----->DramcWriteLeveling(PI) begin...
8831 23:11:34.365756 ==
8832 23:11:34.368858 Dram Type= 6, Freq= 0, CH_1, rank 1
8833 23:11:34.371969 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8834 23:11:34.372054 ==
8835 23:11:34.375253 Write leveling (Byte 0): 24 => 24
8836 23:11:34.378866 Write leveling (Byte 1): 28 => 28
8837 23:11:34.381906 DramcWriteLeveling(PI) end<-----
8838 23:11:34.382000
8839 23:11:34.382067 ==
8840 23:11:34.385247 Dram Type= 6, Freq= 0, CH_1, rank 1
8841 23:11:34.388660 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8842 23:11:34.388746 ==
8843 23:11:34.391883 [Gating] SW mode calibration
8844 23:11:34.398401 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8845 23:11:34.405266 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8846 23:11:34.408653 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8847 23:11:34.415249 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8848 23:11:34.418404 1 4 8 | B1->B0 | 2322 3434 | 1 0 | (0 0) (0 0)
8849 23:11:34.422375 1 4 12 | B1->B0 | 2e2e 3434 | 0 1 | (0 0) (1 1)
8850 23:11:34.425777 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8851 23:11:34.431905 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8852 23:11:34.435303 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8853 23:11:34.438554 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8854 23:11:34.445318 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8855 23:11:34.449070 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8856 23:11:34.451929 1 5 8 | B1->B0 | 3434 2626 | 1 0 | (1 0) (1 0)
8857 23:11:34.458921 1 5 12 | B1->B0 | 2c2c 2323 | 0 0 | (1 0) (1 0)
8858 23:11:34.461833 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8859 23:11:34.465268 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8860 23:11:34.471820 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8861 23:11:34.475301 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8862 23:11:34.478463 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8863 23:11:34.485837 1 6 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
8864 23:11:34.488432 1 6 8 | B1->B0 | 2929 4646 | 0 0 | (1 1) (0 0)
8865 23:11:34.492416 1 6 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8866 23:11:34.499042 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8867 23:11:34.501943 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8868 23:11:34.506072 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8869 23:11:34.511828 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8870 23:11:34.514900 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8871 23:11:34.518045 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8872 23:11:34.525128 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8873 23:11:34.528539 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8874 23:11:34.532060 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8875 23:11:34.538125 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8876 23:11:34.541864 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8877 23:11:34.544935 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8878 23:11:34.551843 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8879 23:11:34.555084 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8880 23:11:34.558346 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8881 23:11:34.565095 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8882 23:11:34.568224 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8883 23:11:34.571648 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8884 23:11:34.578405 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8885 23:11:34.581265 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8886 23:11:34.584797 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8887 23:11:34.591358 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8888 23:11:34.594804 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8889 23:11:34.598380 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8890 23:11:34.601514 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8891 23:11:34.604465 Total UI for P1: 0, mck2ui 16
8892 23:11:34.608045 best dqsien dly found for B0: ( 1, 9, 8)
8893 23:11:34.611182 Total UI for P1: 0, mck2ui 16
8894 23:11:34.614193 best dqsien dly found for B1: ( 1, 9, 12)
8895 23:11:34.617635 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8896 23:11:34.620596 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8897 23:11:34.623796
8898 23:11:34.627567 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8899 23:11:34.630722 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8900 23:11:34.633856 [Gating] SW calibration Done
8901 23:11:34.633937 ==
8902 23:11:34.637582 Dram Type= 6, Freq= 0, CH_1, rank 1
8903 23:11:34.640581 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8904 23:11:34.640662 ==
8905 23:11:34.643876 RX Vref Scan: 0
8906 23:11:34.643951
8907 23:11:34.644016 RX Vref 0 -> 0, step: 1
8908 23:11:34.644076
8909 23:11:34.647068 RX Delay 0 -> 252, step: 8
8910 23:11:34.650371 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8911 23:11:34.653837 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8912 23:11:34.660280 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8913 23:11:34.663904 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8914 23:11:34.666829 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8915 23:11:34.670281 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8916 23:11:34.673470 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8917 23:11:34.680557 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8918 23:11:34.683639 iDelay=200, Bit 8, Center 111 (48 ~ 175) 128
8919 23:11:34.686779 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8920 23:11:34.690285 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8921 23:11:34.693575 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8922 23:11:34.700134 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8923 23:11:34.703274 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8924 23:11:34.706505 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8925 23:11:34.710051 iDelay=200, Bit 15, Center 135 (72 ~ 199) 128
8926 23:11:34.710132 ==
8927 23:11:34.713580 Dram Type= 6, Freq= 0, CH_1, rank 1
8928 23:11:34.719829 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8929 23:11:34.719906 ==
8930 23:11:34.719972 DQS Delay:
8931 23:11:34.723489 DQS0 = 0, DQS1 = 0
8932 23:11:34.723563 DQM Delay:
8933 23:11:34.726581 DQM0 = 132, DQM1 = 127
8934 23:11:34.726659 DQ Delay:
8935 23:11:34.730003 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8936 23:11:34.733207 DQ4 =131, DQ5 =143, DQ6 =139, DQ7 =131
8937 23:11:34.736347 DQ8 =111, DQ9 =115, DQ10 =131, DQ11 =123
8938 23:11:34.739676 DQ12 =131, DQ13 =139, DQ14 =131, DQ15 =135
8939 23:11:34.739755
8940 23:11:34.739818
8941 23:11:34.739881 ==
8942 23:11:34.743206 Dram Type= 6, Freq= 0, CH_1, rank 1
8943 23:11:34.749602 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8944 23:11:34.749678 ==
8945 23:11:34.749739
8946 23:11:34.749801
8947 23:11:34.749863 TX Vref Scan disable
8948 23:11:34.753170 == TX Byte 0 ==
8949 23:11:34.756906 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8950 23:11:34.763425 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8951 23:11:34.763596 == TX Byte 1 ==
8952 23:11:34.766903 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8953 23:11:34.773314 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8954 23:11:34.773496 ==
8955 23:11:34.776717 Dram Type= 6, Freq= 0, CH_1, rank 1
8956 23:11:34.779694 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8957 23:11:34.779865 ==
8958 23:11:34.794035
8959 23:11:34.797318 TX Vref early break, caculate TX vref
8960 23:11:34.800461 TX Vref=16, minBit 0, minWin=23, winSum=383
8961 23:11:34.803966 TX Vref=18, minBit 0, minWin=23, winSum=391
8962 23:11:34.807285 TX Vref=20, minBit 0, minWin=24, winSum=405
8963 23:11:34.810073 TX Vref=22, minBit 0, minWin=24, winSum=406
8964 23:11:34.813991 TX Vref=24, minBit 0, minWin=25, winSum=418
8965 23:11:34.820098 TX Vref=26, minBit 1, minWin=25, winSum=421
8966 23:11:34.824232 TX Vref=28, minBit 6, minWin=25, winSum=422
8967 23:11:34.827382 TX Vref=30, minBit 1, minWin=24, winSum=417
8968 23:11:34.830293 TX Vref=32, minBit 0, minWin=24, winSum=406
8969 23:11:34.833616 TX Vref=34, minBit 1, minWin=23, winSum=400
8970 23:11:34.837284 TX Vref=36, minBit 1, minWin=22, winSum=391
8971 23:11:34.843898 [TxChooseVref] Worse bit 6, Min win 25, Win sum 422, Final Vref 28
8972 23:11:34.844394
8973 23:11:34.847052 Final TX Range 0 Vref 28
8974 23:11:34.847537
8975 23:11:34.847845 ==
8976 23:11:34.850232 Dram Type= 6, Freq= 0, CH_1, rank 1
8977 23:11:34.853852 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8978 23:11:34.854379 ==
8979 23:11:34.854722
8980 23:11:34.855036
8981 23:11:34.857244 TX Vref Scan disable
8982 23:11:34.863687 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8983 23:11:34.864206 == TX Byte 0 ==
8984 23:11:34.867150 u2DelayCellOfst[0]=18 cells (5 PI)
8985 23:11:34.870397 u2DelayCellOfst[1]=11 cells (3 PI)
8986 23:11:34.873518 u2DelayCellOfst[2]=0 cells (0 PI)
8987 23:11:34.876716 u2DelayCellOfst[3]=3 cells (1 PI)
8988 23:11:34.880013 u2DelayCellOfst[4]=7 cells (2 PI)
8989 23:11:34.883271 u2DelayCellOfst[5]=22 cells (6 PI)
8990 23:11:34.886637 u2DelayCellOfst[6]=18 cells (5 PI)
8991 23:11:34.890115 u2DelayCellOfst[7]=3 cells (1 PI)
8992 23:11:34.893055 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8993 23:11:34.896215 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8994 23:11:34.900173 == TX Byte 1 ==
8995 23:11:34.902750 u2DelayCellOfst[8]=0 cells (0 PI)
8996 23:11:34.905958 u2DelayCellOfst[9]=7 cells (2 PI)
8997 23:11:34.909411 u2DelayCellOfst[10]=15 cells (4 PI)
8998 23:11:34.909535 u2DelayCellOfst[11]=7 cells (2 PI)
8999 23:11:34.912589 u2DelayCellOfst[12]=18 cells (5 PI)
9000 23:11:34.915884 u2DelayCellOfst[13]=18 cells (5 PI)
9001 23:11:34.919202 u2DelayCellOfst[14]=18 cells (5 PI)
9002 23:11:34.922565 u2DelayCellOfst[15]=18 cells (5 PI)
9003 23:11:34.929558 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
9004 23:11:34.932708 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
9005 23:11:34.933102 DramC Write-DBI on
9006 23:11:34.933411 ==
9007 23:11:34.935996 Dram Type= 6, Freq= 0, CH_1, rank 1
9008 23:11:34.942955 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9009 23:11:34.943381 ==
9010 23:11:34.943691
9011 23:11:34.943977
9012 23:11:34.945843 TX Vref Scan disable
9013 23:11:34.946229 == TX Byte 0 ==
9014 23:11:34.952809 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
9015 23:11:34.953377 == TX Byte 1 ==
9016 23:11:34.955870 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
9017 23:11:34.959035 DramC Write-DBI off
9018 23:11:34.959429
9019 23:11:34.959831 [DATLAT]
9020 23:11:34.962751 Freq=1600, CH1 RK1
9021 23:11:34.963145
9022 23:11:34.963618 DATLAT Default: 0xf
9023 23:11:34.965769 0, 0xFFFF, sum = 0
9024 23:11:34.966181 1, 0xFFFF, sum = 0
9025 23:11:34.968913 2, 0xFFFF, sum = 0
9026 23:11:34.969330 3, 0xFFFF, sum = 0
9027 23:11:34.972087 4, 0xFFFF, sum = 0
9028 23:11:34.972392 5, 0xFFFF, sum = 0
9029 23:11:34.975791 6, 0xFFFF, sum = 0
9030 23:11:34.976094 7, 0xFFFF, sum = 0
9031 23:11:34.978786 8, 0xFFFF, sum = 0
9032 23:11:34.979020 9, 0xFFFF, sum = 0
9033 23:11:34.982326 10, 0xFFFF, sum = 0
9034 23:11:34.985431 11, 0xFFFF, sum = 0
9035 23:11:34.985602 12, 0xFFFF, sum = 0
9036 23:11:34.988694 13, 0x8FFF, sum = 0
9037 23:11:34.988888 14, 0x0, sum = 1
9038 23:11:34.992354 15, 0x0, sum = 2
9039 23:11:34.992516 16, 0x0, sum = 3
9040 23:11:34.995467 17, 0x0, sum = 4
9041 23:11:34.995605 best_step = 15
9042 23:11:34.995728
9043 23:11:34.995845 ==
9044 23:11:34.998680 Dram Type= 6, Freq= 0, CH_1, rank 1
9045 23:11:35.002053 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9046 23:11:35.002143 ==
9047 23:11:35.005006 RX Vref Scan: 0
9048 23:11:35.005134
9049 23:11:35.008606 RX Vref 0 -> 0, step: 1
9050 23:11:35.008721
9051 23:11:35.008824 RX Delay 3 -> 252, step: 4
9052 23:11:35.015498 iDelay=195, Bit 0, Center 134 (83 ~ 186) 104
9053 23:11:35.019150 iDelay=195, Bit 1, Center 128 (79 ~ 178) 100
9054 23:11:35.022129 iDelay=195, Bit 2, Center 118 (67 ~ 170) 104
9055 23:11:35.025649 iDelay=195, Bit 3, Center 126 (75 ~ 178) 104
9056 23:11:35.029013 iDelay=195, Bit 4, Center 124 (67 ~ 182) 116
9057 23:11:35.035686 iDelay=195, Bit 5, Center 140 (87 ~ 194) 108
9058 23:11:35.039065 iDelay=195, Bit 6, Center 142 (91 ~ 194) 104
9059 23:11:35.042101 iDelay=195, Bit 7, Center 124 (71 ~ 178) 108
9060 23:11:35.045818 iDelay=195, Bit 8, Center 110 (55 ~ 166) 112
9061 23:11:35.049319 iDelay=195, Bit 9, Center 114 (63 ~ 166) 104
9062 23:11:35.055600 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
9063 23:11:35.058907 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
9064 23:11:35.062513 iDelay=195, Bit 12, Center 132 (79 ~ 186) 108
9065 23:11:35.065750 iDelay=195, Bit 13, Center 134 (83 ~ 186) 104
9066 23:11:35.072400 iDelay=195, Bit 14, Center 130 (75 ~ 186) 112
9067 23:11:35.075566 iDelay=195, Bit 15, Center 136 (83 ~ 190) 108
9068 23:11:35.075992 ==
9069 23:11:35.078960 Dram Type= 6, Freq= 0, CH_1, rank 1
9070 23:11:35.081969 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9071 23:11:35.082628 ==
9072 23:11:35.083221 DQS Delay:
9073 23:11:35.085429 DQS0 = 0, DQS1 = 0
9074 23:11:35.086099 DQM Delay:
9075 23:11:35.088929 DQM0 = 129, DQM1 = 125
9076 23:11:35.089416 DQ Delay:
9077 23:11:35.092127 DQ0 =134, DQ1 =128, DQ2 =118, DQ3 =126
9078 23:11:35.095438 DQ4 =124, DQ5 =140, DQ6 =142, DQ7 =124
9079 23:11:35.098410 DQ8 =110, DQ9 =114, DQ10 =128, DQ11 =120
9080 23:11:35.105518 DQ12 =132, DQ13 =134, DQ14 =130, DQ15 =136
9081 23:11:35.105787
9082 23:11:35.106000
9083 23:11:35.106218
9084 23:11:35.108418 [DramC_TX_OE_Calibration] TA2
9085 23:11:35.108564 Original DQ_B0 (3 6) =30, OEN = 27
9086 23:11:35.112065 Original DQ_B1 (3 6) =30, OEN = 27
9087 23:11:35.115166 24, 0x0, End_B0=24 End_B1=24
9088 23:11:35.118400 25, 0x0, End_B0=25 End_B1=25
9089 23:11:35.122018 26, 0x0, End_B0=26 End_B1=26
9090 23:11:35.125287 27, 0x0, End_B0=27 End_B1=27
9091 23:11:35.125747 28, 0x0, End_B0=28 End_B1=28
9092 23:11:35.128638 29, 0x0, End_B0=29 End_B1=29
9093 23:11:35.131655 30, 0x0, End_B0=30 End_B1=30
9094 23:11:35.135493 31, 0x4545, End_B0=30 End_B1=30
9095 23:11:35.138269 Byte0 end_step=30 best_step=27
9096 23:11:35.138637 Byte1 end_step=30 best_step=27
9097 23:11:35.141721 Byte0 TX OE(2T, 0.5T) = (3, 3)
9098 23:11:35.145162 Byte1 TX OE(2T, 0.5T) = (3, 3)
9099 23:11:35.145558
9100 23:11:35.145963
9101 23:11:35.154577 [DQSOSCAuto] RK1, (LSB)MR18= 0xd1a, (MSB)MR19= 0x303, tDQSOscB0 = 396 ps tDQSOscB1 = 403 ps
9102 23:11:35.154836 CH1 RK1: MR19=303, MR18=D1A
9103 23:11:35.161710 CH1_RK1: MR19=0x303, MR18=0xD1A, DQSOSC=396, MR23=63, INC=23, DEC=15
9104 23:11:35.164737 [RxdqsGatingPostProcess] freq 1600
9105 23:11:35.171511 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9106 23:11:35.174641 best DQS0 dly(2T, 0.5T) = (1, 1)
9107 23:11:35.177942 best DQS1 dly(2T, 0.5T) = (1, 1)
9108 23:11:35.180996 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9109 23:11:35.184383 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9110 23:11:35.184542 best DQS0 dly(2T, 0.5T) = (1, 1)
9111 23:11:35.187453 best DQS1 dly(2T, 0.5T) = (1, 1)
9112 23:11:35.191307 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9113 23:11:35.194334 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9114 23:11:35.198049 Pre-setting of DQS Precalculation
9115 23:11:35.204629 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9116 23:11:35.211091 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9117 23:11:35.218078 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9118 23:11:35.218505
9119 23:11:35.218840
9120 23:11:35.221126 [Calibration Summary] 3200 Mbps
9121 23:11:35.221582 CH 0, Rank 0
9122 23:11:35.224913 SW Impedance : PASS
9123 23:11:35.227896 DUTY Scan : NO K
9124 23:11:35.228326 ZQ Calibration : PASS
9125 23:11:35.231040 Jitter Meter : NO K
9126 23:11:35.234379 CBT Training : PASS
9127 23:11:35.234801 Write leveling : PASS
9128 23:11:35.237929 RX DQS gating : PASS
9129 23:11:35.241227 RX DQ/DQS(RDDQC) : PASS
9130 23:11:35.242018 TX DQ/DQS : PASS
9131 23:11:35.244257 RX DATLAT : PASS
9132 23:11:35.247626 RX DQ/DQS(Engine): PASS
9133 23:11:35.248289 TX OE : PASS
9134 23:11:35.248878 All Pass.
9135 23:11:35.250693
9136 23:11:35.251237 CH 0, Rank 1
9137 23:11:35.254102 SW Impedance : PASS
9138 23:11:35.254689 DUTY Scan : NO K
9139 23:11:35.257734 ZQ Calibration : PASS
9140 23:11:35.258303 Jitter Meter : NO K
9141 23:11:35.261053 CBT Training : PASS
9142 23:11:35.263963 Write leveling : PASS
9143 23:11:35.264447 RX DQS gating : PASS
9144 23:11:35.267148 RX DQ/DQS(RDDQC) : PASS
9145 23:11:35.270632 TX DQ/DQS : PASS
9146 23:11:35.270938 RX DATLAT : PASS
9147 23:11:35.273580 RX DQ/DQS(Engine): PASS
9148 23:11:35.277050 TX OE : PASS
9149 23:11:35.277231 All Pass.
9150 23:11:35.277375
9151 23:11:35.277544 CH 1, Rank 0
9152 23:11:35.280299 SW Impedance : PASS
9153 23:11:35.283811 DUTY Scan : NO K
9154 23:11:35.283963 ZQ Calibration : PASS
9155 23:11:35.286911 Jitter Meter : NO K
9156 23:11:35.290247 CBT Training : PASS
9157 23:11:35.290378 Write leveling : PASS
9158 23:11:35.293903 RX DQS gating : PASS
9159 23:11:35.297213 RX DQ/DQS(RDDQC) : PASS
9160 23:11:35.297578 TX DQ/DQS : PASS
9161 23:11:35.300300 RX DATLAT : PASS
9162 23:11:35.304000 RX DQ/DQS(Engine): PASS
9163 23:11:35.304241 TX OE : PASS
9164 23:11:35.307001 All Pass.
9165 23:11:35.307239
9166 23:11:35.307429 CH 1, Rank 1
9167 23:11:35.310376 SW Impedance : PASS
9168 23:11:35.310616 DUTY Scan : NO K
9169 23:11:35.313781 ZQ Calibration : PASS
9170 23:11:35.317326 Jitter Meter : NO K
9171 23:11:35.317584 CBT Training : PASS
9172 23:11:35.320276 Write leveling : PASS
9173 23:11:35.320610 RX DQS gating : PASS
9174 23:11:35.323472 RX DQ/DQS(RDDQC) : PASS
9175 23:11:35.327022 TX DQ/DQS : PASS
9176 23:11:35.327264 RX DATLAT : PASS
9177 23:11:35.330215 RX DQ/DQS(Engine): PASS
9178 23:11:35.333728 TX OE : PASS
9179 23:11:35.333970 All Pass.
9180 23:11:35.334200
9181 23:11:35.336956 DramC Write-DBI on
9182 23:11:35.337149 PER_BANK_REFRESH: Hybrid Mode
9183 23:11:35.340079 TX_TRACKING: ON
9184 23:11:35.350406 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9185 23:11:35.356844 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9186 23:11:35.363661 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9187 23:11:35.366946 [FAST_K] Save calibration result to emmc
9188 23:11:35.369954 sync common calibartion params.
9189 23:11:35.373312 sync cbt_mode0:1, 1:1
9190 23:11:35.373573 dram_init: ddr_geometry: 2
9191 23:11:35.376846 dram_init: ddr_geometry: 2
9192 23:11:35.379966 dram_init: ddr_geometry: 2
9193 23:11:35.380159 0:dram_rank_size:100000000
9194 23:11:35.383795 1:dram_rank_size:100000000
9195 23:11:35.390347 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9196 23:11:35.393506 DFS_SHUFFLE_HW_MODE: ON
9197 23:11:35.396466 dramc_set_vcore_voltage set vcore to 725000
9198 23:11:35.396727 Read voltage for 1600, 0
9199 23:11:35.399756 Vio18 = 0
9200 23:11:35.400005 Vcore = 725000
9201 23:11:35.400222 Vdram = 0
9202 23:11:35.403634 Vddq = 0
9203 23:11:35.403823 Vmddr = 0
9204 23:11:35.406724 switch to 3200 Mbps bootup
9205 23:11:35.406915 [DramcRunTimeConfig]
9206 23:11:35.407126 PHYPLL
9207 23:11:35.409714 DPM_CONTROL_AFTERK: ON
9208 23:11:35.413114 PER_BANK_REFRESH: ON
9209 23:11:35.413426 REFRESH_OVERHEAD_REDUCTION: ON
9210 23:11:35.416581 CMD_PICG_NEW_MODE: OFF
9211 23:11:35.420012 XRTWTW_NEW_MODE: ON
9212 23:11:35.420203 XRTRTR_NEW_MODE: ON
9213 23:11:35.423193 TX_TRACKING: ON
9214 23:11:35.423432 RDSEL_TRACKING: OFF
9215 23:11:35.426610 DQS Precalculation for DVFS: ON
9216 23:11:35.429740 RX_TRACKING: OFF
9217 23:11:35.429930 HW_GATING DBG: ON
9218 23:11:35.432958 ZQCS_ENABLE_LP4: ON
9219 23:11:35.433148 RX_PICG_NEW_MODE: ON
9220 23:11:35.436590 TX_PICG_NEW_MODE: ON
9221 23:11:35.436802 ENABLE_RX_DCM_DPHY: ON
9222 23:11:35.439721 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9223 23:11:35.442921 DUMMY_READ_FOR_TRACKING: OFF
9224 23:11:35.446863 !!! SPM_CONTROL_AFTERK: OFF
9225 23:11:35.449813 !!! SPM could not control APHY
9226 23:11:35.450006 IMPEDANCE_TRACKING: ON
9227 23:11:35.452940 TEMP_SENSOR: ON
9228 23:11:35.453198 HW_SAVE_FOR_SR: OFF
9229 23:11:35.456599 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9230 23:11:35.460143 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9231 23:11:35.463443 Read ODT Tracking: ON
9232 23:11:35.466560 Refresh Rate DeBounce: ON
9233 23:11:35.466823 DFS_NO_QUEUE_FLUSH: ON
9234 23:11:35.469499 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9235 23:11:35.473095 ENABLE_DFS_RUNTIME_MRW: OFF
9236 23:11:35.476347 DDR_RESERVE_NEW_MODE: ON
9237 23:11:35.476556 MR_CBT_SWITCH_FREQ: ON
9238 23:11:35.479478 =========================
9239 23:11:35.498344 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9240 23:11:35.501245 dram_init: ddr_geometry: 2
9241 23:11:35.519311 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9242 23:11:35.522854 dram_init: dram init end (result: 0)
9243 23:11:35.529717 DRAM-K: Full calibration passed in 24600 msecs
9244 23:11:35.533091 MRC: failed to locate region type 0.
9245 23:11:35.533298 DRAM rank0 size:0x100000000,
9246 23:11:35.536223 DRAM rank1 size=0x100000000
9247 23:11:35.545909 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9248 23:11:35.552721 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9249 23:11:35.559541 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9250 23:11:35.566049 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9251 23:11:35.568984 DRAM rank0 size:0x100000000,
9252 23:11:35.572626 DRAM rank1 size=0x100000000
9253 23:11:35.572835 CBMEM:
9254 23:11:35.576131 IMD: root @ 0xfffff000 254 entries.
9255 23:11:35.579431 IMD: root @ 0xffffec00 62 entries.
9256 23:11:35.582653 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9257 23:11:35.585631 WARNING: RO_VPD is uninitialized or empty.
9258 23:11:35.592251 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9259 23:11:35.599854 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9260 23:11:35.612080 read SPI 0x42894 0xe01e: 6228 us, 9212 KB/s, 73.696 Mbps
9261 23:11:35.623734 BS: romstage times (exec / console): total (unknown) / 24060 ms
9262 23:11:35.623897
9263 23:11:35.624024
9264 23:11:35.633632 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9265 23:11:35.636744 ARM64: Exception handlers installed.
9266 23:11:35.640122 ARM64: Testing exception
9267 23:11:35.643271 ARM64: Done test exception
9268 23:11:35.643462 Enumerating buses...
9269 23:11:35.646976 Show all devs... Before device enumeration.
9270 23:11:35.649904 Root Device: enabled 1
9271 23:11:35.653492 CPU_CLUSTER: 0: enabled 1
9272 23:11:35.653664 CPU: 00: enabled 1
9273 23:11:35.656646 Compare with tree...
9274 23:11:35.656823 Root Device: enabled 1
9275 23:11:35.659893 CPU_CLUSTER: 0: enabled 1
9276 23:11:35.663136 CPU: 00: enabled 1
9277 23:11:35.663319 Root Device scanning...
9278 23:11:35.666651 scan_static_bus for Root Device
9279 23:11:35.669948 CPU_CLUSTER: 0 enabled
9280 23:11:35.673560 scan_static_bus for Root Device done
9281 23:11:35.676596 scan_bus: bus Root Device finished in 8 msecs
9282 23:11:35.677375 done
9283 23:11:35.683108 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9284 23:11:35.686730 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9285 23:11:35.692944 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9286 23:11:35.696488 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9287 23:11:35.699603 Allocating resources...
9288 23:11:35.703276 Reading resources...
9289 23:11:35.706449 Root Device read_resources bus 0 link: 0
9290 23:11:35.709286 DRAM rank0 size:0x100000000,
9291 23:11:35.709525 DRAM rank1 size=0x100000000
9292 23:11:35.716219 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9293 23:11:35.716402 CPU: 00 missing read_resources
9294 23:11:35.722829 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9295 23:11:35.726278 Root Device read_resources bus 0 link: 0 done
9296 23:11:35.729433 Done reading resources.
9297 23:11:35.733021 Show resources in subtree (Root Device)...After reading.
9298 23:11:35.736052 Root Device child on link 0 CPU_CLUSTER: 0
9299 23:11:35.739328 CPU_CLUSTER: 0 child on link 0 CPU: 00
9300 23:11:35.749274 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9301 23:11:35.749569 CPU: 00
9302 23:11:35.752415 Root Device assign_resources, bus 0 link: 0
9303 23:11:35.756045 CPU_CLUSTER: 0 missing set_resources
9304 23:11:35.762273 Root Device assign_resources, bus 0 link: 0 done
9305 23:11:35.762442 Done setting resources.
9306 23:11:35.769246 Show resources in subtree (Root Device)...After assigning values.
9307 23:11:35.772284 Root Device child on link 0 CPU_CLUSTER: 0
9308 23:11:35.775575 CPU_CLUSTER: 0 child on link 0 CPU: 00
9309 23:11:35.785895 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9310 23:11:35.786063 CPU: 00
9311 23:11:35.789123 Done allocating resources.
9312 23:11:35.795756 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9313 23:11:35.795935 Enabling resources...
9314 23:11:35.796082 done.
9315 23:11:35.802363 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9316 23:11:35.805854 Initializing devices...
9317 23:11:35.805984 Root Device init
9318 23:11:35.809032 init hardware done!
9319 23:11:35.809161 0x00000018: ctrlr->caps
9320 23:11:35.812187 52.000 MHz: ctrlr->f_max
9321 23:11:35.815214 0.400 MHz: ctrlr->f_min
9322 23:11:35.815347 0x40ff8080: ctrlr->voltages
9323 23:11:35.818864 sclk: 390625
9324 23:11:35.818992 Bus Width = 1
9325 23:11:35.819093 sclk: 390625
9326 23:11:35.822067 Bus Width = 1
9327 23:11:35.822195 Early init status = 3
9328 23:11:35.828723 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9329 23:11:35.831798 in-header: 03 fc 00 00 01 00 00 00
9330 23:11:35.834929 in-data: 00
9331 23:11:35.838072 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9332 23:11:35.842235 in-header: 03 fd 00 00 00 00 00 00
9333 23:11:35.845859 in-data:
9334 23:11:35.848878 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9335 23:11:35.852347 in-header: 03 fc 00 00 01 00 00 00
9336 23:11:35.855677 in-data: 00
9337 23:11:35.858956 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9338 23:11:35.863592 in-header: 03 fd 00 00 00 00 00 00
9339 23:11:35.866972 in-data:
9340 23:11:35.870241 [SSUSB] Setting up USB HOST controller...
9341 23:11:35.873383 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9342 23:11:35.876642 [SSUSB] phy power-on done.
9343 23:11:35.880265 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9344 23:11:35.886738 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9345 23:11:35.889809 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9346 23:11:35.896836 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9347 23:11:35.903587 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9348 23:11:35.910065 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9349 23:11:35.916768 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9350 23:11:35.923099 read SPI 0x705bc 0x1f6a: 925 us, 8694 KB/s, 69.552 Mbps
9351 23:11:35.926697 SPM: binary array size = 0x9dc
9352 23:11:35.929768 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9353 23:11:35.936558 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9354 23:11:35.943502 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9355 23:11:35.949616 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9356 23:11:35.953297 configure_display: Starting display init
9357 23:11:35.987113 anx7625_power_on_init: Init interface.
9358 23:11:35.990129 anx7625_disable_pd_protocol: Disabled PD feature.
9359 23:11:35.994189 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9360 23:11:36.021158 anx7625_start_dp_work: Secure OCM version=00
9361 23:11:36.024803 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9362 23:11:36.039559 sp_tx_get_edid_block: EDID Block = 1
9363 23:11:36.141956 Extracted contents:
9364 23:11:36.145264 header: 00 ff ff ff ff ff ff 00
9365 23:11:36.148803 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9366 23:11:36.152019 version: 01 04
9367 23:11:36.155254 basic params: 95 1f 11 78 0a
9368 23:11:36.158791 chroma info: 76 90 94 55 54 90 27 21 50 54
9369 23:11:36.161848 established: 00 00 00
9370 23:11:36.168721 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9371 23:11:36.171793 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9372 23:11:36.178681 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9373 23:11:36.185138 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9374 23:11:36.191634 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9375 23:11:36.194880 extensions: 00
9376 23:11:36.194962 checksum: fb
9377 23:11:36.195026
9378 23:11:36.198776 Manufacturer: IVO Model 57d Serial Number 0
9379 23:11:36.201701 Made week 0 of 2020
9380 23:11:36.201787 EDID version: 1.4
9381 23:11:36.205266 Digital display
9382 23:11:36.208350 6 bits per primary color channel
9383 23:11:36.208454 DisplayPort interface
9384 23:11:36.211816 Maximum image size: 31 cm x 17 cm
9385 23:11:36.214923 Gamma: 220%
9386 23:11:36.215033 Check DPMS levels
9387 23:11:36.218768 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9388 23:11:36.221482 First detailed timing is preferred timing
9389 23:11:36.225442 Established timings supported:
9390 23:11:36.228605 Standard timings supported:
9391 23:11:36.231612 Detailed timings
9392 23:11:36.234988 Hex of detail: 383680a07038204018303c0035ae10000019
9393 23:11:36.238280 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9394 23:11:36.244728 0780 0798 07c8 0820 hborder 0
9395 23:11:36.248032 0438 043b 0447 0458 vborder 0
9396 23:11:36.251391 -hsync -vsync
9397 23:11:36.251525 Did detailed timing
9398 23:11:36.258258 Hex of detail: 000000000000000000000000000000000000
9399 23:11:36.258392 Manufacturer-specified data, tag 0
9400 23:11:36.264846 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9401 23:11:36.268087 ASCII string: InfoVision
9402 23:11:36.271283 Hex of detail: 000000fe00523134304e574635205248200a
9403 23:11:36.274879 ASCII string: R140NWF5 RH
9404 23:11:36.275014 Checksum
9405 23:11:36.278060 Checksum: 0xfb (valid)
9406 23:11:36.281236 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9407 23:11:36.284844 DSI data_rate: 832800000 bps
9408 23:11:36.291680 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9409 23:11:36.294695 anx7625_parse_edid: pixelclock(138800).
9410 23:11:36.298200 hactive(1920), hsync(48), hfp(24), hbp(88)
9411 23:11:36.301515 vactive(1080), vsync(12), vfp(3), vbp(17)
9412 23:11:36.304730 anx7625_dsi_config: config dsi.
9413 23:11:36.311280 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9414 23:11:36.324255 anx7625_dsi_config: success to config DSI
9415 23:11:36.327459 anx7625_dp_start: MIPI phy setup OK.
9416 23:11:36.330922 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9417 23:11:36.334014 mtk_ddp_mode_set invalid vrefresh 60
9418 23:11:36.337502 main_disp_path_setup
9419 23:11:36.337642 ovl_layer_smi_id_en
9420 23:11:36.340943 ovl_layer_smi_id_en
9421 23:11:36.341089 ccorr_config
9422 23:11:36.341196 aal_config
9423 23:11:36.344132 gamma_config
9424 23:11:36.344266 postmask_config
9425 23:11:36.347306 dither_config
9426 23:11:36.350594 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9427 23:11:36.357493 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9428 23:11:36.360439 Root Device init finished in 551 msecs
9429 23:11:36.364259 CPU_CLUSTER: 0 init
9430 23:11:36.370941 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9431 23:11:36.374153 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9432 23:11:36.377051 APU_MBOX 0x190000b0 = 0x10001
9433 23:11:36.380842 APU_MBOX 0x190001b0 = 0x10001
9434 23:11:36.383846 APU_MBOX 0x190005b0 = 0x10001
9435 23:11:36.386984 APU_MBOX 0x190006b0 = 0x10001
9436 23:11:36.390535 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9437 23:11:36.403327 read SPI 0x539f4 0xe237: 6251 us, 9264 KB/s, 74.112 Mbps
9438 23:11:36.415418 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9439 23:11:36.422059 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9440 23:11:36.433810 read SPI 0x61c74 0xe8ef: 6412 us, 9299 KB/s, 74.392 Mbps
9441 23:11:36.442717 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9442 23:11:36.446439 CPU_CLUSTER: 0 init finished in 81 msecs
9443 23:11:36.449403 Devices initialized
9444 23:11:36.453134 Show all devs... After init.
9445 23:11:36.453221 Root Device: enabled 1
9446 23:11:36.456344 CPU_CLUSTER: 0: enabled 1
9447 23:11:36.459244 CPU: 00: enabled 1
9448 23:11:36.462769 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9449 23:11:36.466082 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9450 23:11:36.469181 ELOG: NV offset 0x57f000 size 0x1000
9451 23:11:36.475984 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9452 23:11:36.482844 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9453 23:11:36.486295 ELOG: Event(17) added with size 13 at 2023-12-27 23:11:36 UTC
9454 23:11:36.492376 out: cmd=0x121: 03 db 21 01 00 00 00 00
9455 23:11:36.495820 in-header: 03 42 00 00 2c 00 00 00
9456 23:11:36.505702 in-data: 1c 69 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9457 23:11:36.512506 ELOG: Event(A1) added with size 10 at 2023-12-27 23:11:36 UTC
9458 23:11:36.519182 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9459 23:11:36.525818 ELOG: Event(A0) added with size 9 at 2023-12-27 23:11:36 UTC
9460 23:11:36.528909 elog_add_boot_reason: Logged dev mode boot
9461 23:11:36.535998 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9462 23:11:36.536080 Finalize devices...
9463 23:11:36.539172 Devices finalized
9464 23:11:36.542235 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9465 23:11:36.545426 Writing coreboot table at 0xffe64000
9466 23:11:36.549110 0. 000000000010a000-0000000000113fff: RAMSTAGE
9467 23:11:36.552329 1. 0000000040000000-00000000400fffff: RAM
9468 23:11:36.558721 2. 0000000040100000-000000004032afff: RAMSTAGE
9469 23:11:36.561915 3. 000000004032b000-00000000545fffff: RAM
9470 23:11:36.565441 4. 0000000054600000-000000005465ffff: BL31
9471 23:11:36.568375 5. 0000000054660000-00000000ffe63fff: RAM
9472 23:11:36.575090 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9473 23:11:36.578482 7. 0000000100000000-000000023fffffff: RAM
9474 23:11:36.581506 Passing 5 GPIOs to payload:
9475 23:11:36.585127 NAME | PORT | POLARITY | VALUE
9476 23:11:36.591891 EC in RW | 0x000000aa | low | undefined
9477 23:11:36.594828 EC interrupt | 0x00000005 | low | undefined
9478 23:11:36.597953 TPM interrupt | 0x000000ab | high | undefined
9479 23:11:36.604782 SD card detect | 0x00000011 | high | undefined
9480 23:11:36.608440 speaker enable | 0x00000093 | high | undefined
9481 23:11:36.611763 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9482 23:11:36.614981 in-header: 03 f9 00 00 02 00 00 00
9483 23:11:36.618105 in-data: 02 00
9484 23:11:36.621670 ADC[4]: Raw value=895191 ID=7
9485 23:11:36.621777 ADC[3]: Raw value=213440 ID=1
9486 23:11:36.624653 RAM Code: 0x71
9487 23:11:36.628269 ADC[6]: Raw value=74722 ID=0
9488 23:11:36.628350 ADC[5]: Raw value=212330 ID=1
9489 23:11:36.631408 SKU Code: 0x1
9490 23:11:36.637733 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 5987
9491 23:11:36.637824 coreboot table: 964 bytes.
9492 23:11:36.641656 IMD ROOT 0. 0xfffff000 0x00001000
9493 23:11:36.644723 IMD SMALL 1. 0xffffe000 0x00001000
9494 23:11:36.647749 RO MCACHE 2. 0xffffc000 0x00001104
9495 23:11:36.651520 CONSOLE 3. 0xfff7c000 0x00080000
9496 23:11:36.654580 FMAP 4. 0xfff7b000 0x00000452
9497 23:11:36.658284 TIME STAMP 5. 0xfff7a000 0x00000910
9498 23:11:36.661040 VBOOT WORK 6. 0xfff66000 0x00014000
9499 23:11:36.664197 RAMOOPS 7. 0xffe66000 0x00100000
9500 23:11:36.667729 COREBOOT 8. 0xffe64000 0x00002000
9501 23:11:36.670705 IMD small region:
9502 23:11:36.674178 IMD ROOT 0. 0xffffec00 0x00000400
9503 23:11:36.677464 VPD 1. 0xffffeb80 0x0000006c
9504 23:11:36.680882 MMC STATUS 2. 0xffffeb60 0x00000004
9505 23:11:36.683897 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9506 23:11:36.687442 Probing TPM: done!
9507 23:11:36.690750 Connected to device vid:did:rid of 1ae0:0028:00
9508 23:11:36.701974 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9509 23:11:36.704908 Initialized TPM device CR50 revision 0
9510 23:11:36.708683 Checking cr50 for pending updates
9511 23:11:36.712444 Reading cr50 TPM mode
9512 23:11:36.721233 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9513 23:11:36.727750 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9514 23:11:36.767911 read SPI 0x3990ec 0x4f1b0: 34860 us, 9294 KB/s, 74.352 Mbps
9515 23:11:36.771589 Checking segment from ROM address 0x40100000
9516 23:11:36.774837 Checking segment from ROM address 0x4010001c
9517 23:11:36.781132 Loading segment from ROM address 0x40100000
9518 23:11:36.781214 code (compression=0)
9519 23:11:36.787953 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9520 23:11:36.797834 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9521 23:11:36.797920 it's not compressed!
9522 23:11:36.804469 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9523 23:11:36.807854 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9524 23:11:36.828141 Loading segment from ROM address 0x4010001c
9525 23:11:36.828226 Entry Point 0x80000000
9526 23:11:36.831714 Loaded segments
9527 23:11:36.834776 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9528 23:11:36.841665 Jumping to boot code at 0x80000000(0xffe64000)
9529 23:11:36.848423 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9530 23:11:36.855102 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9531 23:11:36.862700 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9532 23:11:36.866048 Checking segment from ROM address 0x40100000
9533 23:11:36.869257 Checking segment from ROM address 0x4010001c
9534 23:11:36.875676 Loading segment from ROM address 0x40100000
9535 23:11:36.875758 code (compression=1)
9536 23:11:36.882530 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9537 23:11:36.892633 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9538 23:11:36.892716 using LZMA
9539 23:11:36.901072 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9540 23:11:36.907600 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9541 23:11:36.911185 Loading segment from ROM address 0x4010001c
9542 23:11:36.911267 Entry Point 0x54601000
9543 23:11:36.914639 Loaded segments
9544 23:11:36.917798 NOTICE: MT8192 bl31_setup
9545 23:11:36.924775 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9546 23:11:36.928151 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9547 23:11:36.931540 WARNING: region 0:
9548 23:11:36.934758 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9549 23:11:36.934840 WARNING: region 1:
9550 23:11:36.941653 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9551 23:11:36.944907 WARNING: region 2:
9552 23:11:36.948397 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9553 23:11:36.951654 WARNING: region 3:
9554 23:11:36.954796 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9555 23:11:36.957956 WARNING: region 4:
9556 23:11:36.964566 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9557 23:11:36.964648 WARNING: region 5:
9558 23:11:36.968307 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9559 23:11:36.971491 WARNING: region 6:
9560 23:11:36.974814 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9561 23:11:36.974896 WARNING: region 7:
9562 23:11:36.981471 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9563 23:11:36.988387 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9564 23:11:36.991376 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9565 23:11:36.994842 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9566 23:11:37.001779 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9567 23:11:37.004877 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9568 23:11:37.007991 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9569 23:11:37.014804 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9570 23:11:37.018358 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9571 23:11:37.021358 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9572 23:11:37.028282 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9573 23:11:37.031571 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9574 23:11:37.038344 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9575 23:11:37.041534 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9576 23:11:37.044981 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9577 23:11:37.051713 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9578 23:11:37.054740 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9579 23:11:37.058420 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9580 23:11:37.065030 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9581 23:11:37.068084 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9582 23:11:37.074595 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9583 23:11:37.078131 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9584 23:11:37.081360 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9585 23:11:37.088206 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9586 23:11:37.091282 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9587 23:11:37.098401 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9588 23:11:37.101692 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9589 23:11:37.104634 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9590 23:11:37.111342 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9591 23:11:37.115113 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9592 23:11:37.118114 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9593 23:11:37.125013 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9594 23:11:37.128089 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9595 23:11:37.131580 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9596 23:11:37.138272 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9597 23:11:37.141397 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9598 23:11:37.145160 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9599 23:11:37.148291 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9600 23:11:37.155032 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9601 23:11:37.158186 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9602 23:11:37.161866 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9603 23:11:37.164968 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9604 23:11:37.171239 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9605 23:11:37.174879 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9606 23:11:37.178145 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9607 23:11:37.181658 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9608 23:11:37.187973 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9609 23:11:37.191229 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9610 23:11:37.194728 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9611 23:11:37.201508 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9612 23:11:37.204668 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9613 23:11:37.213544 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9614 23:11:37.214856 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9615 23:11:37.218134 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9616 23:11:37.224953 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9617 23:11:37.227980 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9618 23:11:37.234613 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9619 23:11:37.238203 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9620 23:11:37.244905 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9621 23:11:37.248050 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9622 23:11:37.251564 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9623 23:11:37.258043 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9624 23:11:37.261071 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9625 23:11:37.267949 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9626 23:11:37.271553 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9627 23:11:37.278169 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9628 23:11:37.281492 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9629 23:11:37.284626 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9630 23:11:37.291266 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9631 23:11:37.295038 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9632 23:11:37.301420 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9633 23:11:37.304659 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9634 23:11:37.311671 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9635 23:11:37.314879 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9636 23:11:37.318150 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9637 23:11:37.325013 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9638 23:11:37.328546 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9639 23:11:37.334904 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9640 23:11:37.338554 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9641 23:11:37.345029 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9642 23:11:37.348518 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9643 23:11:37.351671 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9644 23:11:37.358285 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9645 23:11:37.361691 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9646 23:11:37.368542 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9647 23:11:37.371514 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9648 23:11:37.378274 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9649 23:11:37.381388 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9650 23:11:37.384823 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9651 23:11:37.391611 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9652 23:11:37.395358 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9653 23:11:37.401674 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9654 23:11:37.405259 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9655 23:11:37.411863 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9656 23:11:37.414981 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9657 23:11:37.418169 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9658 23:11:37.424944 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9659 23:11:37.428259 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9660 23:11:37.431754 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9661 23:11:37.438665 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9662 23:11:37.441776 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9663 23:11:37.444881 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9664 23:11:37.451926 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9665 23:11:37.454842 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9666 23:11:37.458316 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9667 23:11:37.464757 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9668 23:11:37.468397 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9669 23:11:37.474780 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9670 23:11:37.478548 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9671 23:11:37.481495 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9672 23:11:37.488287 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9673 23:11:37.491591 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9674 23:11:37.498402 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9675 23:11:37.501436 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9676 23:11:37.505321 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9677 23:11:37.511565 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9678 23:11:37.515060 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9679 23:11:37.518225 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9680 23:11:37.524756 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9681 23:11:37.528542 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9682 23:11:37.531322 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9683 23:11:37.534907 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9684 23:11:37.541813 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9685 23:11:37.544876 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9686 23:11:37.548208 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9687 23:11:37.554962 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9688 23:11:37.557955 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9689 23:11:37.561618 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9690 23:11:37.568436 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9691 23:11:37.571550 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9692 23:11:37.578230 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9693 23:11:37.581333 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9694 23:11:37.584739 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9695 23:11:37.591511 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9696 23:11:37.594724 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9697 23:11:37.597931 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9698 23:11:37.604889 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9699 23:11:37.608068 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9700 23:11:37.614861 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9701 23:11:37.618134 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9702 23:11:37.621356 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9703 23:11:37.628406 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9704 23:11:37.631656 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9705 23:11:37.638132 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9706 23:11:37.641767 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9707 23:11:37.645208 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9708 23:11:37.651508 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9709 23:11:37.655148 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9710 23:11:37.658128 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9711 23:11:37.664747 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9712 23:11:37.668125 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9713 23:11:37.675034 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9714 23:11:37.678167 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9715 23:11:37.681989 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9716 23:11:37.688304 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9717 23:11:37.691341 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9718 23:11:37.698244 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9719 23:11:37.701586 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9720 23:11:37.704767 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9721 23:11:37.711401 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9722 23:11:37.715064 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9723 23:11:37.721368 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9724 23:11:37.724504 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9725 23:11:37.728258 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9726 23:11:37.734602 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9727 23:11:37.737987 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9728 23:11:37.740947 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9729 23:11:37.747756 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9730 23:11:37.750857 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9731 23:11:37.757443 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9732 23:11:37.760759 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9733 23:11:37.767714 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9734 23:11:37.770773 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9735 23:11:37.774313 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9736 23:11:37.780909 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9737 23:11:37.784161 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9738 23:11:37.787796 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9739 23:11:37.794026 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9740 23:11:37.797549 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9741 23:11:37.804213 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9742 23:11:37.807467 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9743 23:11:37.810843 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9744 23:11:37.817741 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9745 23:11:37.820873 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9746 23:11:37.827585 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9747 23:11:37.830680 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9748 23:11:37.833831 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9749 23:11:37.840617 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9750 23:11:37.844135 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9751 23:11:37.850642 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9752 23:11:37.853723 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9753 23:11:37.857160 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9754 23:11:37.864000 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9755 23:11:37.867349 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9756 23:11:37.873615 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9757 23:11:37.877320 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9758 23:11:37.883458 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9759 23:11:37.886825 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9760 23:11:37.890434 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9761 23:11:37.896564 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9762 23:11:37.900269 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9763 23:11:37.906885 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9764 23:11:37.910048 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9765 23:11:37.913740 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9766 23:11:37.920022 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9767 23:11:37.923607 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9768 23:11:37.929947 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9769 23:11:37.933586 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9770 23:11:37.940081 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9771 23:11:37.943585 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9772 23:11:37.946499 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9773 23:11:37.953294 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9774 23:11:37.956391 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9775 23:11:37.963236 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9776 23:11:37.966627 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9777 23:11:37.969830 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9778 23:11:37.976403 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9779 23:11:37.979759 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9780 23:11:37.986202 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9781 23:11:37.989630 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9782 23:11:37.996021 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9783 23:11:37.999546 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9784 23:11:38.002637 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9785 23:11:38.009874 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9786 23:11:38.012874 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9787 23:11:38.019288 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9788 23:11:38.022964 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9789 23:11:38.029464 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9790 23:11:38.032630 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9791 23:11:38.036425 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9792 23:11:38.042932 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9793 23:11:38.045968 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9794 23:11:38.049207 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9795 23:11:38.052607 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9796 23:11:38.056236 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9797 23:11:38.062510 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9798 23:11:38.065761 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9799 23:11:38.072573 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9800 23:11:38.076143 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9801 23:11:38.079083 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9802 23:11:38.086080 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9803 23:11:38.089036 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9804 23:11:38.095964 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9805 23:11:38.098894 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9806 23:11:38.102120 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9807 23:11:38.108762 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9808 23:11:38.112245 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9809 23:11:38.115450 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9810 23:11:38.121933 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9811 23:11:38.125374 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9812 23:11:38.128751 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9813 23:11:38.135353 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9814 23:11:38.138711 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9815 23:11:38.145702 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9816 23:11:38.148334 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9817 23:11:38.152335 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9818 23:11:38.158663 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9819 23:11:38.161409 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9820 23:11:38.165107 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9821 23:11:38.171882 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9822 23:11:38.175111 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9823 23:11:38.181761 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9824 23:11:38.184932 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9825 23:11:38.188184 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9826 23:11:38.195033 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9827 23:11:38.198106 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9828 23:11:38.201509 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9829 23:11:38.208272 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9830 23:11:38.211463 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9831 23:11:38.214657 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9832 23:11:38.221831 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9833 23:11:38.224909 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9834 23:11:38.228056 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9835 23:11:38.231333 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9836 23:11:38.234785 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9837 23:11:38.241422 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9838 23:11:38.244453 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9839 23:11:38.248091 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9840 23:11:38.251295 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9841 23:11:38.258235 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9842 23:11:38.261188 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9843 23:11:38.264812 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9844 23:11:38.271277 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9845 23:11:38.274552 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9846 23:11:38.277694 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9847 23:11:38.284344 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9848 23:11:38.287856 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9849 23:11:38.294227 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9850 23:11:38.297810 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9851 23:11:38.304207 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9852 23:11:38.307465 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9853 23:11:38.310822 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9854 23:11:38.317709 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9855 23:11:38.321271 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9856 23:11:38.327359 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9857 23:11:38.331197 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9858 23:11:38.334208 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9859 23:11:38.340777 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9860 23:11:38.344369 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9861 23:11:38.350749 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9862 23:11:38.354210 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9863 23:11:38.357278 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9864 23:11:38.364277 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9865 23:11:38.367281 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9866 23:11:38.374030 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9867 23:11:38.377467 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9868 23:11:38.380591 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9869 23:11:38.387375 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9870 23:11:38.390883 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9871 23:11:38.397174 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9872 23:11:38.400608 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9873 23:11:38.407198 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9874 23:11:38.410738 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9875 23:11:38.414196 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9876 23:11:38.420614 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9877 23:11:38.423835 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9878 23:11:38.430502 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9879 23:11:38.434081 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9880 23:11:38.437237 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9881 23:11:38.443945 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9882 23:11:38.447062 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9883 23:11:38.453770 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9884 23:11:38.456947 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9885 23:11:38.460205 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9886 23:11:38.466858 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9887 23:11:38.470061 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9888 23:11:38.476527 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9889 23:11:38.480084 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9890 23:11:38.486361 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9891 23:11:38.489665 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9892 23:11:38.493341 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9893 23:11:38.499632 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9894 23:11:38.503022 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9895 23:11:38.509361 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9896 23:11:38.512839 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9897 23:11:38.519504 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9898 23:11:38.522723 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9899 23:11:38.526162 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9900 23:11:38.532701 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9901 23:11:38.536020 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9902 23:11:38.542742 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9903 23:11:38.546289 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9904 23:11:38.549286 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9905 23:11:38.555735 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9906 23:11:38.559010 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9907 23:11:38.565753 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9908 23:11:38.568940 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9909 23:11:38.572211 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9910 23:11:38.578797 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9911 23:11:38.582293 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9912 23:11:38.588776 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9913 23:11:38.591899 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9914 23:11:38.598568 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9915 23:11:38.601857 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9916 23:11:38.605298 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9917 23:11:38.611962 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9918 23:11:38.615475 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9919 23:11:38.622181 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9920 23:11:38.625333 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9921 23:11:38.631790 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9922 23:11:38.635383 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9923 23:11:38.641797 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9924 23:11:38.644891 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9925 23:11:38.648492 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9926 23:11:38.654912 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9927 23:11:38.658543 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9928 23:11:38.664875 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9929 23:11:38.667963 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9930 23:11:38.674753 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9931 23:11:38.678202 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9932 23:11:38.681429 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9933 23:11:38.687892 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9934 23:11:38.691328 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9935 23:11:38.697787 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9936 23:11:38.701046 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9937 23:11:38.707547 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9938 23:11:38.710937 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9939 23:11:38.717804 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9940 23:11:38.720935 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9941 23:11:38.724557 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9942 23:11:38.730908 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9943 23:11:38.734247 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9944 23:11:38.740746 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9945 23:11:38.743958 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9946 23:11:38.750744 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9947 23:11:38.753834 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9948 23:11:38.757215 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9949 23:11:38.764298 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9950 23:11:38.767127 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9951 23:11:38.773949 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9952 23:11:38.777049 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9953 23:11:38.783843 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9954 23:11:38.786882 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9955 23:11:38.793736 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9956 23:11:38.797097 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9957 23:11:38.800210 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9958 23:11:38.806820 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9959 23:11:38.810033 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9960 23:11:38.816702 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9961 23:11:38.820425 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9962 23:11:38.826824 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9963 23:11:38.830341 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9964 23:11:38.833337 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9965 23:11:38.839920 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9966 23:11:38.843381 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9967 23:11:38.849832 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9968 23:11:38.853384 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9969 23:11:38.859717 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9970 23:11:38.863326 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9971 23:11:38.869759 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9972 23:11:38.873297 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9973 23:11:38.879759 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9974 23:11:38.883339 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9975 23:11:38.889678 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9976 23:11:38.892997 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9977 23:11:38.900176 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9978 23:11:38.903254 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9979 23:11:38.909404 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9980 23:11:38.912604 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9981 23:11:38.919559 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9982 23:11:38.922819 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9983 23:11:38.929486 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9984 23:11:38.932775 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9985 23:11:38.939320 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9986 23:11:38.942424 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9987 23:11:38.948787 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9988 23:11:38.952169 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9989 23:11:38.958807 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9990 23:11:38.962467 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9991 23:11:38.968704 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9992 23:11:38.972397 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9993 23:11:38.978730 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9994 23:11:38.982017 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9995 23:11:38.988588 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9996 23:11:38.992156 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9997 23:11:38.995277 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9998 23:11:38.998665 INFO: [APUAPC] vio 0
9999 23:11:39.005234 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
10000 23:11:39.008525 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
10001 23:11:39.011569 INFO: [APUAPC] D0_APC_0: 0x400510
10002 23:11:39.015278 INFO: [APUAPC] D0_APC_1: 0x0
10003 23:11:39.018254 INFO: [APUAPC] D0_APC_2: 0x1540
10004 23:11:39.021617 INFO: [APUAPC] D0_APC_3: 0x0
10005 23:11:39.025194 INFO: [APUAPC] D1_APC_0: 0xffffffff
10006 23:11:39.028314 INFO: [APUAPC] D1_APC_1: 0xffffffff
10007 23:11:39.031438 INFO: [APUAPC] D1_APC_2: 0x3fffff
10008 23:11:39.035006 INFO: [APUAPC] D1_APC_3: 0x0
10009 23:11:39.038141 INFO: [APUAPC] D2_APC_0: 0xffffffff
10010 23:11:39.041316 INFO: [APUAPC] D2_APC_1: 0xffffffff
10011 23:11:39.044827 INFO: [APUAPC] D2_APC_2: 0x3fffff
10012 23:11:39.047708 INFO: [APUAPC] D2_APC_3: 0x0
10013 23:11:39.051289 INFO: [APUAPC] D3_APC_0: 0xffffffff
10014 23:11:39.054604 INFO: [APUAPC] D3_APC_1: 0xffffffff
10015 23:11:39.057648 INFO: [APUAPC] D3_APC_2: 0x3fffff
10016 23:11:39.061226 INFO: [APUAPC] D3_APC_3: 0x0
10017 23:11:39.064320 INFO: [APUAPC] D4_APC_0: 0xffffffff
10018 23:11:39.067863 INFO: [APUAPC] D4_APC_1: 0xffffffff
10019 23:11:39.071131 INFO: [APUAPC] D4_APC_2: 0x3fffff
10020 23:11:39.071243 INFO: [APUAPC] D4_APC_3: 0x0
10021 23:11:39.074831 INFO: [APUAPC] D5_APC_0: 0xffffffff
10022 23:11:39.081068 INFO: [APUAPC] D5_APC_1: 0xffffffff
10023 23:11:39.084496 INFO: [APUAPC] D5_APC_2: 0x3fffff
10024 23:11:39.084578 INFO: [APUAPC] D5_APC_3: 0x0
10025 23:11:39.087544 INFO: [APUAPC] D6_APC_0: 0xffffffff
10026 23:11:39.090866 INFO: [APUAPC] D6_APC_1: 0xffffffff
10027 23:11:39.094176 INFO: [APUAPC] D6_APC_2: 0x3fffff
10028 23:11:39.097783 INFO: [APUAPC] D6_APC_3: 0x0
10029 23:11:39.100909 INFO: [APUAPC] D7_APC_0: 0xffffffff
10030 23:11:39.104167 INFO: [APUAPC] D7_APC_1: 0xffffffff
10031 23:11:39.107678 INFO: [APUAPC] D7_APC_2: 0x3fffff
10032 23:11:39.110979 INFO: [APUAPC] D7_APC_3: 0x0
10033 23:11:39.114423 INFO: [APUAPC] D8_APC_0: 0xffffffff
10034 23:11:39.117645 INFO: [APUAPC] D8_APC_1: 0xffffffff
10035 23:11:39.120900 INFO: [APUAPC] D8_APC_2: 0x3fffff
10036 23:11:39.124407 INFO: [APUAPC] D8_APC_3: 0x0
10037 23:11:39.127701 INFO: [APUAPC] D9_APC_0: 0xffffffff
10038 23:11:39.130930 INFO: [APUAPC] D9_APC_1: 0xffffffff
10039 23:11:39.134398 INFO: [APUAPC] D9_APC_2: 0x3fffff
10040 23:11:39.137398 INFO: [APUAPC] D9_APC_3: 0x0
10041 23:11:39.140520 INFO: [APUAPC] D10_APC_0: 0xffffffff
10042 23:11:39.144153 INFO: [APUAPC] D10_APC_1: 0xffffffff
10043 23:11:39.147307 INFO: [APUAPC] D10_APC_2: 0x3fffff
10044 23:11:39.150834 INFO: [APUAPC] D10_APC_3: 0x0
10045 23:11:39.153796 INFO: [APUAPC] D11_APC_0: 0xffffffff
10046 23:11:39.157398 INFO: [APUAPC] D11_APC_1: 0xffffffff
10047 23:11:39.160810 INFO: [APUAPC] D11_APC_2: 0x3fffff
10048 23:11:39.163843 INFO: [APUAPC] D11_APC_3: 0x0
10049 23:11:39.167513 INFO: [APUAPC] D12_APC_0: 0xffffffff
10050 23:11:39.170542 INFO: [APUAPC] D12_APC_1: 0xffffffff
10051 23:11:39.173740 INFO: [APUAPC] D12_APC_2: 0x3fffff
10052 23:11:39.177340 INFO: [APUAPC] D12_APC_3: 0x0
10053 23:11:39.180459 INFO: [APUAPC] D13_APC_0: 0xffffffff
10054 23:11:39.183745 INFO: [APUAPC] D13_APC_1: 0xffffffff
10055 23:11:39.187220 INFO: [APUAPC] D13_APC_2: 0x3fffff
10056 23:11:39.190296 INFO: [APUAPC] D13_APC_3: 0x0
10057 23:11:39.193910 INFO: [APUAPC] D14_APC_0: 0xffffffff
10058 23:11:39.196979 INFO: [APUAPC] D14_APC_1: 0xffffffff
10059 23:11:39.200177 INFO: [APUAPC] D14_APC_2: 0x3fffff
10060 23:11:39.203902 INFO: [APUAPC] D14_APC_3: 0x0
10061 23:11:39.207009 INFO: [APUAPC] D15_APC_0: 0xffffffff
10062 23:11:39.210151 INFO: [APUAPC] D15_APC_1: 0xffffffff
10063 23:11:39.213582 INFO: [APUAPC] D15_APC_2: 0x3fffff
10064 23:11:39.217013 INFO: [APUAPC] D15_APC_3: 0x0
10065 23:11:39.220232 INFO: [APUAPC] APC_CON: 0x4
10066 23:11:39.223751 INFO: [NOCDAPC] D0_APC_0: 0x0
10067 23:11:39.226901 INFO: [NOCDAPC] D0_APC_1: 0x0
10068 23:11:39.230276 INFO: [NOCDAPC] D1_APC_0: 0x0
10069 23:11:39.233411 INFO: [NOCDAPC] D1_APC_1: 0xfff
10070 23:11:39.236783 INFO: [NOCDAPC] D2_APC_0: 0x0
10071 23:11:39.240382 INFO: [NOCDAPC] D2_APC_1: 0xfff
10072 23:11:39.240465 INFO: [NOCDAPC] D3_APC_0: 0x0
10073 23:11:39.243466 INFO: [NOCDAPC] D3_APC_1: 0xfff
10074 23:11:39.246641 INFO: [NOCDAPC] D4_APC_0: 0x0
10075 23:11:39.249804 INFO: [NOCDAPC] D4_APC_1: 0xfff
10076 23:11:39.253329 INFO: [NOCDAPC] D5_APC_0: 0x0
10077 23:11:39.256857 INFO: [NOCDAPC] D5_APC_1: 0xfff
10078 23:11:39.259910 INFO: [NOCDAPC] D6_APC_0: 0x0
10079 23:11:39.263057 INFO: [NOCDAPC] D6_APC_1: 0xfff
10080 23:11:39.266917 INFO: [NOCDAPC] D7_APC_0: 0x0
10081 23:11:39.269772 INFO: [NOCDAPC] D7_APC_1: 0xfff
10082 23:11:39.269855 INFO: [NOCDAPC] D8_APC_0: 0x0
10083 23:11:39.273199 INFO: [NOCDAPC] D8_APC_1: 0xfff
10084 23:11:39.276417 INFO: [NOCDAPC] D9_APC_0: 0x0
10085 23:11:39.280176 INFO: [NOCDAPC] D9_APC_1: 0xfff
10086 23:11:39.283331 INFO: [NOCDAPC] D10_APC_0: 0x0
10087 23:11:39.286529 INFO: [NOCDAPC] D10_APC_1: 0xfff
10088 23:11:39.289733 INFO: [NOCDAPC] D11_APC_0: 0x0
10089 23:11:39.293250 INFO: [NOCDAPC] D11_APC_1: 0xfff
10090 23:11:39.296352 INFO: [NOCDAPC] D12_APC_0: 0x0
10091 23:11:39.299902 INFO: [NOCDAPC] D12_APC_1: 0xfff
10092 23:11:39.303366 INFO: [NOCDAPC] D13_APC_0: 0x0
10093 23:11:39.306429 INFO: [NOCDAPC] D13_APC_1: 0xfff
10094 23:11:39.309739 INFO: [NOCDAPC] D14_APC_0: 0x0
10095 23:11:39.313267 INFO: [NOCDAPC] D14_APC_1: 0xfff
10096 23:11:39.313350 INFO: [NOCDAPC] D15_APC_0: 0x0
10097 23:11:39.316496 INFO: [NOCDAPC] D15_APC_1: 0xfff
10098 23:11:39.319584 INFO: [NOCDAPC] APC_CON: 0x4
10099 23:11:39.323186 INFO: [APUAPC] set_apusys_apc done
10100 23:11:39.326171 INFO: [DEVAPC] devapc_init done
10101 23:11:39.333086 INFO: GICv3 without legacy support detected.
10102 23:11:39.336359 INFO: ARM GICv3 driver initialized in EL3
10103 23:11:39.339705 INFO: Maximum SPI INTID supported: 639
10104 23:11:39.343161 INFO: BL31: Initializing runtime services
10105 23:11:39.349471 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10106 23:11:39.353166 INFO: SPM: enable CPC mode
10107 23:11:39.356138 INFO: mcdi ready for mcusys-off-idle and system suspend
10108 23:11:39.362723 INFO: BL31: Preparing for EL3 exit to normal world
10109 23:11:39.366131 INFO: Entry point address = 0x80000000
10110 23:11:39.366214 INFO: SPSR = 0x8
10111 23:11:39.372792
10112 23:11:39.372925
10113 23:11:39.373046
10114 23:11:39.376114 Starting depthcharge on Spherion...
10115 23:11:39.376197
10116 23:11:39.376263 Wipe memory regions:
10117 23:11:39.376324
10118 23:11:39.377287 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10119 23:11:39.377430 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10120 23:11:39.377579 Setting prompt string to ['asurada:']
10121 23:11:39.377665 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10122 23:11:39.379432 [0x00000040000000, 0x00000054600000)
10123 23:11:39.501917
10124 23:11:39.502042 [0x00000054660000, 0x00000080000000)
10125 23:11:39.762318
10126 23:11:39.762479 [0x000000821a7280, 0x000000ffe64000)
10127 23:11:40.507121
10128 23:11:40.507513 [0x00000100000000, 0x00000240000000)
10129 23:11:42.398032
10130 23:11:42.401144 Initializing XHCI USB controller at 0x11200000.
10131 23:11:43.438594
10132 23:11:43.441980 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10133 23:11:43.442073
10134 23:11:43.442137
10135 23:11:43.442198
10136 23:11:43.442478 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10138 23:11:43.542825 asurada: tftpboot 192.168.201.1 12395393/tftp-deploy-jk3l625h/kernel/image.itb 12395393/tftp-deploy-jk3l625h/kernel/cmdline
10139 23:11:43.542981 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10140 23:11:43.543111 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10141 23:11:43.547498 tftpboot 192.168.201.1 12395393/tftp-deploy-jk3l625h/kernel/image.itp-deploy-jk3l625h/kernel/cmdline
10142 23:11:43.547583
10143 23:11:43.547648 Waiting for link
10144 23:11:43.707617
10145 23:11:43.707829 R8152: Initializing
10146 23:11:43.707914
10147 23:11:43.711048 Version 6 (ocp_data = 5c30)
10148 23:11:43.711147
10149 23:11:43.714053 R8152: Done initializing
10150 23:11:43.714171
10151 23:11:43.714295 Adding net device
10152 23:11:45.743776
10153 23:11:45.743916 done.
10154 23:11:45.743987
10155 23:11:45.744050 MAC: 00:24:32:30:78:ff
10156 23:11:45.744109
10157 23:11:45.746930 Sending DHCP discover... done.
10158 23:11:45.747015
10159 23:11:45.750935 Waiting for reply... done.
10160 23:11:45.751026
10161 23:11:45.753615 Sending DHCP request... done.
10162 23:11:45.753697
10163 23:11:45.758289 Waiting for reply... done.
10164 23:11:45.758370
10165 23:11:45.758435 My ip is 192.168.201.21
10166 23:11:45.758494
10167 23:11:45.761345 The DHCP server ip is 192.168.201.1
10168 23:11:45.761456
10169 23:11:45.768390 TFTP server IP predefined by user: 192.168.201.1
10170 23:11:45.768472
10171 23:11:45.774707 Bootfile predefined by user: 12395393/tftp-deploy-jk3l625h/kernel/image.itb
10172 23:11:45.774790
10173 23:11:45.778019 Sending tftp read request... done.
10174 23:11:45.778101
10175 23:11:45.782049 Waiting for the transfer...
10176 23:11:45.782130
10177 23:11:46.361100 00000000 ################################################################
10178 23:11:46.361248
10179 23:11:46.952619 00080000 ################################################################
10180 23:11:46.952768
10181 23:11:47.525332 00100000 ################################################################
10182 23:11:47.525492
10183 23:11:48.080904 00180000 ################################################################
10184 23:11:48.081056
10185 23:11:48.639011 00200000 ################################################################
10186 23:11:48.639159
10187 23:11:49.201724 00280000 ################################################################
10188 23:11:49.201884
10189 23:11:49.773103 00300000 ################################################################
10190 23:11:49.773293
10191 23:11:50.327859 00380000 ################################################################
10192 23:11:50.328015
10193 23:11:50.896532 00400000 ################################################################
10194 23:11:50.896688
10195 23:11:51.465219 00480000 ################################################################
10196 23:11:51.465376
10197 23:11:52.029042 00500000 ################################################################
10198 23:11:52.029201
10199 23:11:52.612472 00580000 ################################################################
10200 23:11:52.612633
10201 23:11:53.226250 00600000 ################################################################
10202 23:11:53.226412
10203 23:11:53.793424 00680000 ################################################################
10204 23:11:53.793592
10205 23:11:54.364171 00700000 ################################################################
10206 23:11:54.364336
10207 23:11:54.903797 00780000 ################################################################
10208 23:11:54.903960
10209 23:11:55.463725 00800000 ################################################################
10210 23:11:55.463889
10211 23:11:56.043109 00880000 ################################################################
10212 23:11:56.043257
10213 23:11:56.604727 00900000 ################################################################
10214 23:11:56.604885
10215 23:11:57.163674 00980000 ################################################################
10216 23:11:57.163838
10217 23:11:57.741361 00a00000 ################################################################
10218 23:11:57.741583
10219 23:11:58.306311 00a80000 ################################################################
10220 23:11:58.306470
10221 23:11:58.864694 00b00000 ################################################################
10222 23:11:58.864852
10223 23:11:59.427109 00b80000 ################################################################
10224 23:11:59.427286
10225 23:12:00.009682 00c00000 ################################################################
10226 23:12:00.009838
10227 23:12:00.583781 00c80000 ################################################################
10228 23:12:00.583934
10229 23:12:01.168475 00d00000 ################################################################
10230 23:12:01.168627
10231 23:12:01.780076 00d80000 ################################################################
10232 23:12:01.780578
10233 23:12:02.516234 00e00000 ################################################################
10234 23:12:02.516827
10235 23:12:03.230069 00e80000 ################################################################
10236 23:12:03.230594
10237 23:12:03.929568 00f00000 ################################################################
10238 23:12:03.930161
10239 23:12:04.671783 00f80000 ################################################################
10240 23:12:04.672323
10241 23:12:05.273351 01000000 ################################################################
10242 23:12:05.273550
10243 23:12:05.908230 01080000 ################################################################
10244 23:12:05.908786
10245 23:12:06.608260 01100000 ################################################################
10246 23:12:06.608807
10247 23:12:07.280378 01180000 ################################################################
10248 23:12:07.281100
10249 23:12:07.945877 01200000 ################################################################
10250 23:12:07.946049
10251 23:12:08.563125 01280000 ################################################################
10252 23:12:08.563268
10253 23:12:09.187478 01300000 ################################################################
10254 23:12:09.188051
10255 23:12:09.918166 01380000 ################################################################
10256 23:12:09.918314
10257 23:12:10.605704 01400000 ################################################################
10258 23:12:10.605903
10259 23:12:11.195497 01480000 ################################################################
10260 23:12:11.195645
10261 23:12:11.755466 01500000 ################################################################
10262 23:12:11.755611
10263 23:12:12.285878 01580000 ################################################################
10264 23:12:12.286022
10265 23:12:12.804219 01600000 ################################################################
10266 23:12:12.804372
10267 23:12:13.345121 01680000 ################################################################
10268 23:12:13.345258
10269 23:12:13.871974 01700000 ################################################################
10270 23:12:13.872115
10271 23:12:14.389718 01780000 ################################################################
10272 23:12:14.389859
10273 23:12:14.941913 01800000 ################################################################
10274 23:12:14.942055
10275 23:12:15.506436 01880000 ################################################################
10276 23:12:15.506583
10277 23:12:16.035697 01900000 ################################################################
10278 23:12:16.035846
10279 23:12:16.596254 01980000 ################################################################
10280 23:12:16.596415
10281 23:12:17.150734 01a00000 ################################################################
10282 23:12:17.150868
10283 23:12:17.705649 01a80000 ################################################################
10284 23:12:17.705800
10285 23:12:18.244963 01b00000 ################################################################
10286 23:12:18.245102
10287 23:12:18.782540 01b80000 ################################################################
10288 23:12:18.782688
10289 23:12:19.297298 01c00000 ################################################################
10290 23:12:19.297463
10291 23:12:19.707308 01c80000 ################################################### done.
10292 23:12:19.707475
10293 23:12:19.710212 The bootfile was 30296430 bytes long.
10294 23:12:19.710316
10295 23:12:19.713638 Sending tftp read request... done.
10296 23:12:19.713744
10297 23:12:19.716718 Waiting for the transfer...
10298 23:12:19.716866
10299 23:12:19.716961 00000000 # done.
10300 23:12:19.720356
10301 23:12:19.726967 Command line loaded dynamically from TFTP file: 12395393/tftp-deploy-jk3l625h/kernel/cmdline
10302 23:12:19.727075
10303 23:12:19.750217 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12395393/extract-nfsrootfs-a7c1iqj5,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10304 23:12:19.750300
10305 23:12:19.750368 Loading FIT.
10306 23:12:19.750430
10307 23:12:19.753711 Image ramdisk-1 has 18766730 bytes.
10308 23:12:19.753786
10309 23:12:19.756491 Image fdt-1 has 47278 bytes.
10310 23:12:19.756567
10311 23:12:19.760125 Image kernel-1 has 11480388 bytes.
10312 23:12:19.760242
10313 23:12:19.766628 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10314 23:12:19.766734
10315 23:12:19.786304 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10316 23:12:19.786402
10317 23:12:19.789962 Choosing best match conf-1 for compat google,spherion-rev2.
10318 23:12:19.794816
10319 23:12:19.799103 Connected to device vid:did:rid of 1ae0:0028:00
10320 23:12:19.806024
10321 23:12:19.809329 tpm_get_response: command 0x17b, return code 0x0
10322 23:12:19.809429
10323 23:12:19.813011 ec_init: CrosEC protocol v3 supported (256, 248)
10324 23:12:19.817051
10325 23:12:19.820438 tpm_cleanup: add release locality here.
10326 23:12:19.820515
10327 23:12:19.820579 Shutting down all USB controllers.
10328 23:12:19.823574
10329 23:12:19.823673 Removing current net device
10330 23:12:19.823762
10331 23:12:19.830506 Exiting depthcharge with code 4 at timestamp: 69791748
10332 23:12:19.830582
10333 23:12:19.833325 LZMA decompressing kernel-1 to 0x821a6718
10334 23:12:19.833429
10335 23:12:19.837082 LZMA decompressing kernel-1 to 0x40000000
10336 23:12:21.272204
10337 23:12:21.272372 jumping to kernel
10338 23:12:21.273214 end: 2.2.4 bootloader-commands (duration 00:00:42) [common]
10339 23:12:21.273346 start: 2.2.5 auto-login-action (timeout 00:03:43) [common]
10340 23:12:21.273452 Setting prompt string to ['Linux version [0-9]']
10341 23:12:21.273593 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10342 23:12:21.273686 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10343 23:12:21.353861
10344 23:12:21.357177 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10345 23:12:21.360602 start: 2.2.5.1 login-action (timeout 00:03:43) [common]
10346 23:12:21.360709 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10347 23:12:21.360806 Setting prompt string to []
10348 23:12:21.360915 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10349 23:12:21.361015 Using line separator: #'\n'#
10350 23:12:21.361105 No login prompt set.
10351 23:12:21.361197 Parsing kernel messages
10352 23:12:21.361293 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10353 23:12:21.361465 [login-action] Waiting for messages, (timeout 00:03:43)
10354 23:12:21.380593 [ 0.000000] Linux version 6.1.67-cip12-rt7 (KernelCI@build-j59954-arm64-gcc-10-defconfig-arm64-chromebook-nblph) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Wed Dec 27 22:50:56 UTC 2023
10355 23:12:21.383724 [ 0.000000] random: crng init done
10356 23:12:21.390672 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10357 23:12:21.393694 [ 0.000000] efi: UEFI not found.
10358 23:12:21.400035 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10359 23:12:21.410325 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10360 23:12:21.416670 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10361 23:12:21.426755 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10362 23:12:21.433253 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10363 23:12:21.440348 [ 0.000000] printk: bootconsole [mtk8250] enabled
10364 23:12:21.446618 [ 0.000000] NUMA: No NUMA configuration found
10365 23:12:21.453567 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10366 23:12:21.456384 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcfa00-0x23efd1fff]
10367 23:12:21.459814 [ 0.000000] Zone ranges:
10368 23:12:21.466482 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10369 23:12:21.469862 [ 0.000000] DMA32 empty
10370 23:12:21.476143 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10371 23:12:21.479876 [ 0.000000] Movable zone start for each node
10372 23:12:21.483060 [ 0.000000] Early memory node ranges
10373 23:12:21.489636 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10374 23:12:21.495932 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10375 23:12:21.502900 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10376 23:12:21.509309 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10377 23:12:21.515750 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10378 23:12:21.522392 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10379 23:12:21.578573 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10380 23:12:21.585620 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10381 23:12:21.591925 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10382 23:12:21.595112 [ 0.000000] psci: probing for conduit method from DT.
10383 23:12:21.601966 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10384 23:12:21.604982 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10385 23:12:21.611714 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10386 23:12:21.615025 [ 0.000000] psci: SMC Calling Convention v1.2
10387 23:12:21.621428 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10388 23:12:21.625023 [ 0.000000] Detected VIPT I-cache on CPU0
10389 23:12:21.631778 [ 0.000000] CPU features: detected: GIC system register CPU interface
10390 23:12:21.638417 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10391 23:12:21.644879 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10392 23:12:21.651418 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10393 23:12:21.661308 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10394 23:12:21.668035 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10395 23:12:21.671249 [ 0.000000] alternatives: applying boot alternatives
10396 23:12:21.678015 [ 0.000000] Fallback order for Node 0: 0
10397 23:12:21.684497 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10398 23:12:21.687605 [ 0.000000] Policy zone: Normal
10399 23:12:21.711009 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12395393/extract-nfsrootfs-a7c1iqj5,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10400 23:12:21.720499 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10401 23:12:21.731586 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10402 23:12:21.741885 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10403 23:12:21.748170 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10404 23:12:21.751412 <6>[ 0.000000] software IO TLB: area num 8.
10405 23:12:21.808074 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10406 23:12:21.956995 <6>[ 0.000000] Memory: 7950392K/8385536K available (17984K kernel code, 4116K rwdata, 18184K rodata, 8448K init, 615K bss, 402376K reserved, 32768K cma-reserved)
10407 23:12:21.964174 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10408 23:12:21.970503 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10409 23:12:21.973722 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10410 23:12:21.980294 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10411 23:12:21.987104 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10412 23:12:21.990339 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10413 23:12:22.000540 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10414 23:12:22.006770 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10415 23:12:22.013357 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10416 23:12:22.020149 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10417 23:12:22.023446 <6>[ 0.000000] GICv3: 608 SPIs implemented
10418 23:12:22.026581 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10419 23:12:22.032992 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10420 23:12:22.036378 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10421 23:12:22.042928 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10422 23:12:22.056451 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10423 23:12:22.066125 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10424 23:12:22.076082 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10425 23:12:22.083394 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10426 23:12:22.097238 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10427 23:12:22.103352 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10428 23:12:22.110301 <6>[ 0.009185] Console: colour dummy device 80x25
10429 23:12:22.119928 <6>[ 0.013938] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10430 23:12:22.126354 <6>[ 0.024380] pid_max: default: 32768 minimum: 301
10431 23:12:22.130026 <6>[ 0.029253] LSM: Security Framework initializing
10432 23:12:22.136161 <6>[ 0.034193] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10433 23:12:22.146407 <6>[ 0.042055] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10434 23:12:22.156283 <6>[ 0.051465] cblist_init_generic: Setting adjustable number of callback queues.
10435 23:12:22.159523 <6>[ 0.058909] cblist_init_generic: Setting shift to 3 and lim to 1.
10436 23:12:22.169408 <6>[ 0.065247] cblist_init_generic: Setting adjustable number of callback queues.
10437 23:12:22.176083 <6>[ 0.072675] cblist_init_generic: Setting shift to 3 and lim to 1.
10438 23:12:22.179023 <6>[ 0.079155] rcu: Hierarchical SRCU implementation.
10439 23:12:22.185877 <6>[ 0.079157] rcu: Max phase no-delay instances is 1000.
10440 23:12:22.192254 <6>[ 0.079181] printk: bootconsole [mtk8250] printing thread started
10441 23:12:22.199096 <6>[ 0.097520] EFI services will not be available.
10442 23:12:22.202189 <6>[ 0.097721] smp: Bringing up secondary CPUs ...
10443 23:12:22.209109 <6>[ 0.098032] Detected VIPT I-cache on CPU1
10444 23:12:22.215434 <6>[ 0.098101] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10445 23:12:22.221923 <6>[ 0.098131] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10446 23:12:22.231612 <6>[ 0.125981] Detected VIPT I-cache on CPU2
10447 23:12:22.241381 <6>[ 0.126031] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10448 23:12:22.248207 <6>[ 0.126048] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10449 23:12:22.251873 <6>[ 0.126303] Detected VIPT I-cache on CPU3
10450 23:12:22.258424 <6>[ 0.126348] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10451 23:12:22.264724 <6>[ 0.126363] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10452 23:12:22.268039 <6>[ 0.126672] CPU features: detected: Spectre-v4
10453 23:12:22.275001 <6>[ 0.126677] CPU features: detected: Spectre-BHB
10454 23:12:22.277890 <6>[ 0.126682] Detected PIPT I-cache on CPU4
10455 23:12:22.284887 <6>[ 0.126741] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10456 23:12:22.291047 <6>[ 0.126757] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10457 23:12:22.297832 <6>[ 0.127053] Detected PIPT I-cache on CPU5
10458 23:12:22.304189 <6>[ 0.127113] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10459 23:12:22.310800 <6>[ 0.127130] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10460 23:12:22.314207 <6>[ 0.127409] Detected PIPT I-cache on CPU6
10461 23:12:22.324386 <6>[ 0.127472] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10462 23:12:22.330588 <6>[ 0.127488] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10463 23:12:22.334358 <6>[ 0.127780] Detected PIPT I-cache on CPU7
10464 23:12:22.340730 <6>[ 0.127843] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10465 23:12:22.347355 <6>[ 0.127859] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10466 23:12:22.350594 <6>[ 0.127906] smp: Brought up 1 node, 8 CPUs
10467 23:12:22.357350 <6>[ 0.127911] SMP: Total of 8 processors activated.
10468 23:12:22.363514 <6>[ 0.127913] CPU features: detected: 32-bit EL0 Support
10469 23:12:22.370157 <6>[ 0.127915] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10470 23:12:22.376615 <6>[ 0.127918] CPU features: detected: Common not Private translations
10471 23:12:22.383161 <6>[ 0.127920] CPU features: detected: CRC32 instructions
10472 23:12:22.390088 <6>[ 0.127922] CPU features: detected: RCpc load-acquire (LDAPR)
10473 23:12:22.393409 <6>[ 0.127924] CPU features: detected: LSE atomic instructions
10474 23:12:22.399682 <6>[ 0.127926] CPU features: detected: Privileged Access Never
10475 23:12:22.406477 <6>[ 0.127927] CPU features: detected: RAS Extension Support
10476 23:12:22.412987 <6>[ 0.127930] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10477 23:12:22.416558 <6>[ 0.128001] CPU: All CPU(s) started at EL2
10478 23:12:22.422889 <6>[ 0.128003] alternatives: applying system-wide alternatives
10479 23:12:22.426285 <6>[ 0.141066] devtmpfs: initialized
10480 23:12:22.458878 �սѵ������B�͡����������ɥ��郪��Bzɑ�Ɂ�b��ʲ�ѕͥkR�<6>[ 0.35<6492] printk: console [ttyS0] printing thread started
10481 23:12:22.462116 6>[ 0.225661] pnp: PnP ACPI: disabled
10482 23:12:22.470082 <6>[ 0.356503] printk: console [ttyS0] enabled
10483 23:12:22.473506 <6>[ 0.356507] printk: bootconsole [mtk8250] disabled
10484 23:12:22.480394 <6>[ 0.366083] printk: bootconsole [mtk8250] printing thread stopped
10485 23:12:22.486915 <6>[ 0.367258] SuperH (H)SCI(F) driver initialized
10486 23:12:22.490257 <6>[ 0.367772] msm_serial: driver initialized
10487 23:12:22.500293 <6>[ 0.372461] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10488 23:12:22.506642 <6>[ 0.372493] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10489 23:12:22.519997 <6>[ 0.372522] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10490 23:12:22.524986 <6>[ 0.372551] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10491 23:12:22.538400 <6>[ 0.372572] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10492 23:12:22.543642 <6>[ 0.372599] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10493 23:12:22.558184 <6>[ 0.372627] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10494 23:12:22.558519 <6>[ 0.372737] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10495 23:12:22.568100 <6>[ 0.372767] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10496 23:12:22.575266 <6>[ 0.382538] loop: module loaded
10497 23:12:22.578448 <6>[ 0.385132] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10498 23:12:22.581758 <4>[ 0.402048] mtk-pmic-keys: Failed to locate of_node [id: -1]
10499 23:12:22.588752 <6>[ 0.402860] megasas: 07.719.03.00-rc1
10500 23:12:22.591485 <6>[ 0.412804] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10501 23:12:22.598490 <6>[ 0.416849] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10502 23:12:22.604837 <6>[ 0.429111] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10503 23:12:22.614566 <6>[ 0.480897] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10504 23:12:23.122060 <6>[ 1.020312] Freeing initrd memory: 18324K
10505 23:12:23.130048 <6>[ 1.027698] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10506 23:12:23.137030 <6>[ 1.032363] tun: Universal TUN/TAP device driver, 1.6
10507 23:12:23.140045 <6>[ 1.033108] thunder_xcv, ver 1.0
10508 23:12:23.143390 <6>[ 1.033125] thunder_bgx, ver 1.0
10509 23:12:23.146527 <6>[ 1.033138] nicpf, ver 1.0
10510 23:12:23.153418 <6>[ 1.034198] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10511 23:12:23.160156 <6>[ 1.034201] hns3: Copyright (c) 2017 Huawei Corporation.
10512 23:12:23.163359 <6>[ 1.034226] hclge is initializing
10513 23:12:23.166607 <6>[ 1.034239] e1000: Intel(R) PRO/1000 Network Driver
10514 23:12:23.173288 <6>[ 1.034241] e1000: Copyright (c) 1999-2006 Intel Corporation.
10515 23:12:23.180106 <6>[ 1.034258] e1000e: Intel(R) PRO/1000 Network Driver
10516 23:12:23.187337 <6>[ 1.034259] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10517 23:12:23.191056 <6>[ 1.034277] igb: Intel(R) Gigabit Ethernet Network Driver
10518 23:12:23.198233 <6>[ 1.034279] igb: Copyright (c) 2007-2014 Intel Corporation.
10519 23:12:23.204786 <6>[ 1.034292] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10520 23:12:23.208110 <6>[ 1.034294] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10521 23:12:23.215201 <6>[ 1.034580] sky2: driver version 1.30
10522 23:12:23.218765 <6>[ 1.035652] VFIO - User Level meta-driver version: 0.3
10523 23:12:23.225597 <6>[ 1.038502] usbcore: registered new interface driver usb-storage
10524 23:12:23.232152 <6>[ 1.038681] usbcore: registered new device driver onboard-usb-hub
10525 23:12:23.235190 <6>[ 1.041392] mt6397-rtc mt6359-rtc: registered as rtc0
10526 23:12:23.245511 <6>[ 1.041545] mt6397-rtc mt6359-rtc: setting system clock to 2023-12-27T23:12:23 UTC (1703718743)
10527 23:12:23.251808 <6>[ 1.042151] i2c_dev: i2c /dev entries driver
10528 23:12:23.258790 <6>[ 1.049247] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10529 23:12:23.261770 <6>[ 1.064244] cpu cpu0: EM: created perf domain
10530 23:12:23.268341 <6>[ 1.064550] cpu cpu4: EM: created perf domain
10531 23:12:23.274896 <6>[ 1.067696] sdhci: Secure Digital Host Controller Interface driver
10532 23:12:23.278181 <6>[ 1.067698] sdhci: Copyright(c) Pierre Ossman
10533 23:12:23.285172 <6>[ 1.068059] Synopsys Designware Multimedia Card Interface Driver
10534 23:12:23.291718 <6>[ 1.068424] sdhci-pltfm: SDHCI platform and OF driver helper
10535 23:12:23.294853 <6>[ 1.073021] mmc0: CQHCI version 5.10
10536 23:12:23.301554 <6>[ 1.078933] ledtrig-cpu: registered to indicate activity on CPUs
10537 23:12:23.308238 <6>[ 1.079717] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10538 23:12:23.315076 <6>[ 1.080005] usbcore: registered new interface driver usbhid
10539 23:12:23.318357 <6>[ 1.080007] usbhid: USB HID core driver
10540 23:12:23.324897 <6>[ 1.080129] spi_master spi0: will run message pump with realtime priority
10541 23:12:23.337930 <6>[ 1.113329] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10542 23:12:23.351213 <6>[ 1.115697] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10543 23:12:23.358100 <6>[ 1.116731] cros-ec-spi spi0.0: Chrome EC device registered
10544 23:12:23.364662 <6>[ 1.135709] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10545 23:12:23.371018 <6>[ 1.138113] NET: Registered PF_PACKET protocol family
10546 23:12:23.374347 <6>[ 1.138212] 9pnet: Installing 9P2000 support
10547 23:12:23.380816 <5>[ 1.138261] Key type dns_resolver registered
10548 23:12:23.384094 <6>[ 1.138695] registered taskstats version 1
10549 23:12:23.391173 <5>[ 1.138712] Loading compiled-in X.509 certificates
10550 23:12:23.401096 <4>[ 1.154683] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10551 23:12:23.410763 <4>[ 1.154846] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10552 23:12:23.417868 <3>[ 1.154856] debugfs: File 'uA_load' in directory '/' already present!
10553 23:12:23.424145 <3>[ 1.154864] debugfs: File 'min_uV' in directory '/' already present!
10554 23:12:23.430923 <3>[ 1.154867] debugfs: File 'max_uV' in directory '/' already present!
10555 23:12:23.437811 <3>[ 1.154871] debugfs: File 'constraint_flags' in directory '/' already present!
10556 23:12:23.447588 <3>[ 1.156942] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10557 23:12:23.453953 <6>[ 1.163642] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10558 23:12:23.457248 <6>[ 1.164311] xhci-mtk 11200000.usb: xHCI Host Controller
10559 23:12:23.464315 <6>[ 1.164330] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10560 23:12:23.474004 <6>[ 1.164533] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10561 23:12:23.480746 <6>[ 1.164579] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10562 23:12:23.487421 <6>[ 1.164680] xhci-mtk 11200000.usb: xHCI Host Controller
10563 23:12:23.494056 <6>[ 1.164693] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10564 23:12:23.500929 <6>[ 1.164707] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10565 23:12:23.504045 <6>[ 1.165534] hub 1-0:1.0: USB hub found
10566 23:12:23.510967 <6>[ 1.165596] hub 1-0:1.0: 1 port detected
10567 23:12:23.517491 <6>[ 1.166035] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10568 23:12:23.520687 <6>[ 1.166558] hub 2-0:1.0: USB hub found
10569 23:12:23.527234 <6>[ 1.166618] hub 2-0:1.0: 1 port detected
10570 23:12:23.530548 <6>[ 1.167522] mmc0: Command Queue Engine enabled
10571 23:12:23.537382 <6>[ 1.167538] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10572 23:12:23.540461 <6>[ 1.168264] mmcblk0: mmc0:0001 DA4128 116 GiB
10573 23:12:23.547199 <6>[ 1.172811] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10574 23:12:23.553960 <6>[ 1.172855] mtk-msdc 11f70000.mmc: Got CD GPIO
10575 23:12:23.557251 <6>[ 1.175305] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10576 23:12:23.563531 <6>[ 1.175988] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10577 23:12:23.570410 <6>[ 1.176670] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10578 23:12:23.577134 <6>[ 1.188189] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10579 23:12:23.586990 <6>[ 1.188197] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10580 23:12:23.593367 <4>[ 1.188342] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10581 23:12:23.603642 <6>[ 1.188974] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10582 23:12:23.610167 <6>[ 1.188978] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10583 23:12:23.619835 <6>[ 1.189101] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10584 23:12:23.626346 <6>[ 1.189115] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10585 23:12:23.633221 <6>[ 1.189119] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10586 23:12:23.642990 <6>[ 1.189124] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10587 23:12:23.652843 <6>[ 1.190617] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10588 23:12:23.659409 <6>[ 1.190637] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10589 23:12:23.669206 <6>[ 1.190643] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10590 23:12:23.676099 <6>[ 1.190650] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10591 23:12:23.686150 <6>[ 1.190656] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10592 23:12:23.692410 <6>[ 1.190662] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10593 23:12:23.702276 <6>[ 1.190669] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10594 23:12:23.709181 <6>[ 1.190675] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10595 23:12:23.718938 <6>[ 1.190681] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10596 23:12:23.725741 <6>[ 1.190688] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10597 23:12:23.735494 <6>[ 1.190694] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10598 23:12:23.741892 <6>[ 1.190700] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10599 23:12:23.752128 <6>[ 1.190706] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10600 23:12:23.758600 <6>[ 1.190712] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10601 23:12:23.768295 <6>[ 1.190719] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10602 23:12:23.774936 <6>[ 1.191222] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10603 23:12:23.781881 <6>[ 1.192061] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10604 23:12:23.788395 <6>[ 1.192598] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10605 23:12:23.794821 <6>[ 1.193221] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10606 23:12:23.801820 <6>[ 1.193893] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10607 23:12:23.811577 <6>[ 1.194091] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10608 23:12:23.818165 <6>[ 1.194105] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10609 23:12:23.827768 <6>[ 1.194110] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10610 23:12:23.838071 <6>[ 1.194115] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10611 23:12:23.848022 <6>[ 1.194121] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10612 23:12:23.857623 <6>[ 1.194126] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10613 23:12:23.867441 <6>[ 1.194131] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10614 23:12:23.874279 <6>[ 1.194136] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10615 23:12:23.884344 <6>[ 1.194141] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10616 23:12:23.894278 <6>[ 1.194148] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10617 23:12:23.904182 <6>[ 1.194152] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10618 23:12:23.913955 <6>[ 1.195283] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10619 23:12:23.920575 <6>[ 1.210081] Trying to probe devices needed for running init ...
10620 23:12:23.927452 <6>[ 1.577552] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10621 23:12:23.930521 <6>[ 1.730294] hub 1-1:1.0: USB hub found
10622 23:12:23.933932 <6>[ 1.730703] hub 1-1:1.0: 4 ports detected
10623 23:12:23.937143 <6>[ 1.734778] hub 1-1:1.0: USB hub found
10624 23:12:23.943626 <6>[ 1.735142] hub 1-1:1.0: 4 ports detected
10625 23:12:23.965124 <6>[ 1.857786] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10626 23:12:23.986117 <6>[ 1.883479] hub 2-1:1.0: USB hub found
10627 23:12:23.989556 <6>[ 1.883946] hub 2-1:1.0: 3 ports detected
10628 23:12:23.992816 <6>[ 1.887565] hub 2-1:1.0: USB hub found
10629 23:12:23.996019 <6>[ 1.888011] hub 2-1:1.0: 3 ports detected
10630 23:12:24.153442 <6>[ 2.045729] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10631 23:12:24.278174 <6>[ 2.173436] hub 1-1.4:1.0: USB hub found
10632 23:12:24.281233 <6>[ 2.173843] hub 1-1.4:1.0: 2 ports detected
10633 23:12:24.284518 <6>[ 2.176782] hub 1-1.4:1.0: USB hub found
10634 23:12:24.291079 <6>[ 2.177105] hub 1-1.4:1.0: 2 ports detected
10635 23:12:24.357265 <6>[ 2.249870] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10636 23:12:24.573268 <6>[ 2.465684] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10637 23:12:24.757191 <6>[ 2.649721] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10638 23:12:35.606196 <6>[ 13.506788] ALSA device list:
10639 23:12:35.612878 <6>[ 13.506811] No soundcards found.
10640 23:12:35.616399 <6>[ 13.511383] Freeing unused kernel memory: 8448K
10641 23:12:35.619448 <6>[ 13.511648] Run /init as init process
10642 23:12:35.622645 Loading, please wait...
10643 23:12:35.653560 Starting systemd-udevd version 252.19-1~deb12u1
10644 23:12:35.924759 <6>[ 13.817986] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10645 23:12:35.931019 <6>[ 13.818132] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10646 23:12:35.945920 <6>[ 13.818147] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10647 23:12:35.960959 <6>[ 13.843622] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10648 23:12:35.963774 <6>[ 13.855375] remoteproc remoteproc0: scp is available
10649 23:12:35.970360 <6>[ 13.855797] remoteproc remoteproc0: powering up scp
10650 23:12:35.977267 <6>[ 13.855815] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10651 23:12:35.984139 <6>[ 13.855925] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10652 23:12:36.000770 <4>[ 13.895791] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10653 23:12:36.016889 <4>[ 13.910538] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10654 23:12:36.019867 <6>[ 13.918556] usbcore: registered new interface driver r8152
10655 23:12:36.030025 <3>[ 13.921585] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10656 23:12:36.036440 <3>[ 13.921604] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10657 23:12:36.046302 <3>[ 13.921612] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10658 23:12:36.053263 <3>[ 13.934957] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10659 23:12:36.063290 <3>[ 13.935004] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10660 23:12:36.069717 <3>[ 13.935009] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10661 23:12:36.079331 <3>[ 13.935014] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10662 23:12:36.086133 <3>[ 13.935017] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10663 23:12:36.092865 <3>[ 13.937534] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10664 23:12:36.100086 <6>[ 13.939333] mc: Linux media interface: v0.10
10665 23:12:36.106027 <3>[ 13.939489] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10666 23:12:36.116659 <3>[ 13.939519] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10667 23:12:36.123724 <3>[ 13.939522] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10668 23:12:36.130147 <3>[ 13.940249] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10669 23:12:36.140060 <3>[ 13.940261] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10670 23:12:36.146736 <3>[ 13.940264] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10671 23:12:36.156901 <3>[ 13.940268] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10672 23:12:36.163192 <3>[ 13.940279] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10673 23:12:36.169542 <3>[ 13.941789] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10674 23:12:36.179694 <6>[ 13.943072] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10675 23:12:36.183016 <6>[ 13.943087] pci_bus 0000:00: root bus resource [bus 00-ff]
10676 23:12:36.189949 <6>[ 13.943098] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10677 23:12:36.199851 <6>[ 13.943104] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10678 23:12:36.206366 <6>[ 13.943180] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10679 23:12:36.216145 <6>[ 13.943210] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10680 23:12:36.219192 <6>[ 13.943294] pci 0000:00:00.0: supports D1 D2
10681 23:12:36.226240 <6>[ 13.943297] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10682 23:12:36.232415 <6>[ 13.950568] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10683 23:12:36.242514 <6>[ 13.954134] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10684 23:12:36.249004 <6>[ 13.961496] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10685 23:12:36.255563 <6>[ 13.961552] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10686 23:12:36.262232 <6>[ 13.961583] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10687 23:12:36.268602 <6>[ 13.961602] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10688 23:12:36.275463 <6>[ 13.961764] pci 0000:01:00.0: supports D1 D2
10689 23:12:36.282023 <6>[ 13.961772] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10690 23:12:36.292187 <4>[ 13.978421] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10691 23:12:36.295162 <4>[ 13.978421] Fallback method does not support PEC.
10692 23:12:36.305234 <6>[ 13.981468] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10693 23:12:36.312248 <6>[ 13.981468] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10694 23:12:36.318721 <6>[ 13.981490] remoteproc remoteproc0: remote processor scp is now up
10695 23:12:36.321674 <6>[ 13.990187] videodev: Linux video capture interface: v2.00
10696 23:12:36.331807 <6>[ 13.990294] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10697 23:12:36.338624 <6>[ 13.990440] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10698 23:12:36.344737 <6>[ 13.990451] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10699 23:12:36.354985 <6>[ 13.990483] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10700 23:12:36.361383 <6>[ 13.990506] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10701 23:12:36.371609 <6>[ 13.990522] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10702 23:12:36.374801 <6>[ 13.990542] pci 0000:00:00.0: PCI bridge to [bus 01]
10703 23:12:36.385138 <6>[ 13.990553] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10704 23:12:36.391295 <6>[ 13.993747] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10705 23:12:36.394597 <6>[ 13.994276] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10706 23:12:36.401286 <6>[ 13.994466] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10707 23:12:36.410772 <3>[ 14.006192] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10708 23:12:36.420810 <6>[ 14.015784] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10709 23:12:36.427491 <6>[ 14.017945] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10710 23:12:36.434438 <3>[ 14.027114] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10711 23:12:36.443943 <6>[ 14.037307] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10712 23:12:36.450369 <6>[ 14.038847] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10713 23:12:36.460450 <4>[ 14.041676] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10714 23:12:36.470260 <4>[ 14.041686] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10715 23:12:36.480596 <6>[ 14.046254] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10716 23:12:36.486801 <6>[ 14.046596] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10717 23:12:36.493803 <6>[ 14.077378] usbcore: registered new interface driver cdc_ether
10718 23:12:36.497177 <6>[ 14.084127] Bluetooth: Core ver 2.22
10719 23:12:36.503642 <6>[ 14.084213] NET: Registered PF_BLUETOOTH protocol family
10720 23:12:36.509971 <6>[ 14.084218] Bluetooth: HCI device and connection manager initialized
10721 23:12:36.516480 <6>[ 14.084236] Bluetooth: HCI socket layer initialized
10722 23:12:36.520204 <6>[ 14.084240] Bluetooth: L2CAP socket layer initialized
10723 23:12:36.526573 <6>[ 14.084247] Bluetooth: SCO socket layer initialized
10724 23:12:36.533272 <6>[ 14.089491] usbcore: registered new interface driver r8153_ecm
10725 23:12:36.536830 <6>[ 14.089678] r8152 2-1.3:1.0 eth0: v1.12.13
10726 23:12:36.542771 <6>[ 14.100699] r8152 2-1.3:1.0 enx0024323078ff: renamed from eth0
10727 23:12:36.549973 <6>[ 14.121047] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10728 23:12:36.563016 <6>[ 14.122161] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10729 23:12:36.569586 <6>[ 14.122296] usbcore: registered new interface driver uvcvideo
10730 23:12:36.573132 <6>[ 14.139841] usbcore: registered new interface driver btusb
10731 23:12:36.583012 <4>[ 14.141094] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10732 23:12:36.589499 <3>[ 14.141100] Bluetooth: hci0: Failed to load firmware file (-2)
10733 23:12:36.596143 <3>[ 14.141102] Bluetooth: hci0: Failed to set up firmware (-2)
10734 23:12:36.605656 <4>[ 14.141103] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10735 23:12:36.612970 <6>[ 14.154105] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10736 23:12:36.622404 <5>[ 14.412066] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10737 23:12:36.628604 <5>[ 14.428754] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10738 23:12:36.636009 <4>[ 14.428851] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10739 23:12:36.641959 <6>[ 14.428860] cfg80211: failed to load regulatory.db
10740 23:12:36.648798 <6>[ 14.545014] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10741 23:12:36.655548 <6>[ 14.545112] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10742 23:12:36.669392 <6>[ 14.565535] mt7921e 0000:01:00.0: ASIC revision: 79610010
10743 23:12:36.768860 <6>[ 14.661641] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
10744 23:12:36.772068 <6>[ 14.661641]
10745 23:12:36.786398 Begin: Loading essential drivers ... done.
10746 23:12:36.789730 Begin: Running /scripts/init-premount ... done.
10747 23:12:36.796247 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10748 23:12:36.805918 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10749 23:12:36.809134 Device /sys/class/net/enx0024323078ff found
10750 23:12:36.809687 done.
10751 23:12:36.833671 Begin: Waiting up to 180 secs for any network device to become available ... done.
10752 23:12:36.900588 IP-Config: enx0024323078ff hardware address 00:24:32:30:78:ff mtu 1500 DHCP
10753 23:12:37.024164 <6>[ 14.919702] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
10754 23:12:37.860898 <6>[ 15.759963] r8152 2-1.3:1.0 enx0024323078ff: carrier on
10755 23:12:37.892280 <6>[ 15.789606] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10756 23:12:38.640605 IP-Config: no response after 2 secs - giving up
10757 23:12:38.681279 IP-Config: enx0024323078ff hardware address 00:24:32:30:78:ff mtu 1500 DHCP
10758 23:12:38.704916 IP-Config: wlp1s0 hardware address d8:f3:bc:78:28:07 mtu 1500 DHCP
10759 23:12:39.417565 IP-Config: enx0024323078ff complete (dhcp from 192.168.201.1):
10760 23:12:39.424309 address: 192.168.201.21 broadcast: 192.168.201.255 netmask: 255.255.255.0
10761 23:12:39.430797 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10762 23:12:39.437186 host : mt8192-asurada-spherion-r0-cbg-8
10763 23:12:39.443728 domain : lava-rack
10764 23:12:39.449837 rootserver: 192.168.201.1 rootpath:
10765 23:12:39.450320 filename :
10766 23:12:39.613329 done.
10767 23:12:39.623438 Begin: Running /scripts/nfs-bottom ... done.
10768 23:12:39.637792 Begin: Running /scripts/init-bottom ... done.
10769 23:12:41.033678 <6>[ 18.930612] NET: Registered PF_INET6 protocol family
10770 23:12:41.037009 <6>[ 18.932866] Segment Routing with IPv6
10771 23:12:41.043444 <6>[ 18.932893] In-situ OAM (IOAM) with IPv6
10772 23:12:41.254924 <30>[ 19.125936] systemd[1]: systemd 252.19-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10773 23:12:41.261670 <30>[ 19.125977] systemd[1]: Detected architecture arm64.
10774 23:12:41.271037
10775 23:12:41.275052 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10776 23:12:41.275578
10777 23:12:41.300580 <30>[ 19.200159] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10778 23:12:42.600105 <30>[ 20.493923] systemd[1]: Queued start job for default target graphical.target.
10779 23:12:42.633638 [[0;32m OK [0m] Created slic<30>[ 20.527493] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10780 23:12:42.637179 e [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10781 23:12:42.662023 [[0;32m OK [0m] Created slic<30>[ 20.555768] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10782 23:12:42.665416 e [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10783 23:12:42.689632 [[0;32m OK [0m] Created slic<30>[ 20.583665] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10784 23:12:42.696367 e [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10785 23:12:42.717135 [[0;32m OK [0m] Created slic<30>[ 20.611249] systemd[1]: Created slice user.slice - User and Session Slice.
10786 23:12:42.720697 e [0;1;39muser.slice[0m - User and Session Slice.
10787 23:12:42.748097 [[0;32m OK [0m] Started [0;<30>[ 20.638633] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10788 23:12:42.750965 1;39msystemd-ask-passwo…quests to Console Directory Watch.
10789 23:12:42.780242 [[0;32m OK [0m] Started [0;<30>[ 20.670624] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10790 23:12:42.783226 1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10791 23:12:42.817672 [[0;32m OK [0m] Reached target [0;1;39mcryp<30>[ 20.697937] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10792 23:12:42.823928 <30>[ 20.698208] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10793 23:12:42.827076 tsetup.…get[0m - Local Encrypted Volumes.
10794 23:12:42.850836 [[0;32m OK [0m] Reached target [0;1;39minte<30>[ 20.741779] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10795 23:12:42.854198 grityse…Local Integrity Protected Volumes.
10796 23:12:42.876318 [[0;32m OK [0m] Reached target [0;1;39mpath<30>[ 20.770315] systemd[1]: Reached target paths.target - Path Units.
10797 23:12:42.876826 s.target[0m - Path Units.
10798 23:12:42.900712 [[0;32m OK [0m] Reached target [0;1;39mremo<30>[ 20.794224] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10799 23:12:42.903778 te-fs.target[0m - Remote File Systems.
10800 23:12:42.923501 [[0;32m OK [0m] Reached target [0;1;39mslic<30>[ 20.817728] systemd[1]: Reached target slices.target - Slice Units.
10801 23:12:42.926815 es.target[0m - Slice Units.
10802 23:12:42.948219 [[0;32m OK [0m] Reached target [0;1;39mswap<30>[ 20.842250] systemd[1]: Reached target swap.target - Swaps.
10803 23:12:42.948735 .target[0m - Swaps.
10804 23:12:42.971942 [[0;32m OK [0m] Reached target [0;1;39mveri<30>[ 20.866276] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10805 23:12:42.978700 tysetup… - Local Verity Protected Volumes.
10806 23:12:43.000650 [[0;32m OK [0m] Listening on<30>[ 20.894747] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10807 23:12:43.006906 [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10808 23:12:43.032475 [[0;32m OK [0m] Listening on [0;1;39msystem<30>[ 20.926366] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10809 23:12:43.038755 d-journ…socket[0m - Journal Audit Socket.
10810 23:12:43.061644 [[0;32m OK [0m] Listening on<30>[ 20.955667] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10811 23:12:43.068250 [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10812 23:12:43.088274 [[0;32m OK [0m] Listening on [0;1;39msystem<30>[ 20.982448] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10813 23:12:43.091165 d-journald.socket[0m - Journal Socket.
10814 23:12:43.113326 [[0;32m OK [0m] Listening on<30>[ 21.007588] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10815 23:12:43.120136 [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10816 23:12:43.144776 [[0;32m OK [0m] Listening on<30>[ 21.038924] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10817 23:12:43.151209 [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10818 23:12:43.172034 [[0;32m OK [0m] Listening on [0;1;39msystem<30>[ 21.066320] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10819 23:12:43.175476 d-udevd…l.socket[0m - udev Kernel Socket.
10820 23:12:43.232099 Mounting [0;1;39mdev-hugepages.mount[<30>[ 21.126206] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10821 23:12:43.235193 0m - Huge Pages File System...
10822 23:12:43.254830 Mountin<30>[ 21.152439] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10823 23:12:43.261253 g [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10824 23:12:43.287282 Mounting [0;1;39msys-kernel-debug.…<30>[ 21.181604] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10825 23:12:43.290722 [0m - Kernel Debug File System...
10826 23:12:43.318028 <30>[ 21.206026] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10827 23:12:43.368546 Starting [0;1;39mkmod-<30>[ 21.262739] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10828 23:12:43.372089 static-nodes…ate List of Static Device Nodes...
10829 23:12:43.403040 Startin<30>[ 21.297133] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10830 23:12:43.406382 g [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10831 23:12:43.468553 Starting [0;1;39mmodpr<30>[ 21.362579] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10832 23:12:43.471472 obe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10833 23:12:43.503061 Starting [0;1;39mmodprobe@drm.service<30>[ 21.397515] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10834 23:12:43.506442 [0m - Load Kernel Module drm...
10835 23:12:43.523605 <6>[ 21.418158] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10836 23:12:43.542669 Startin<30>[ 21.436915] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10837 23:12:43.545622 g [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10838 23:12:43.570873 Startin<30>[ 21.468426] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10839 23:12:43.577375 g [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10840 23:12:43.606664 Startin<30>[ 21.504297] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10841 23:12:43.613188 g [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10842 23:12:43.623849 <6>[ 21.523051] fuse: init (API version 7.37)
10843 23:12:43.680195 Starting [0;1;39msyste<30>[ 21.574640] systemd[1]: Starting systemd-journald.service - Journal Service...
10844 23:12:43.683460 md-journald.service[0m - Journal Service...
10845 23:12:43.719395 Startin<30>[ 21.617114] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10846 23:12:43.725918 g [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10847 23:12:43.755950 Starting [0;1;39msyste<30>[ 21.647101] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10848 23:12:43.759209 md-network-g… units from Kernel command line...
10849 23:12:43.824316 Starting [0;1;39msyste<30>[ 21.718711] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10850 23:12:43.830631 md-remount-f…nt Root and Kernel File Systems...
10851 23:12:43.859750 Starting [0;1;39msystemd-udev-trig…[<30>[ 21.753633] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10852 23:12:43.869702 0m - Coldplug Al<3>[ 21.760252] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10853 23:12:43.872917 l udev Devices...
10854 23:12:43.895657 <3>[ 21.792096] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10855 23:12:43.908647 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepag<30>[ 21.801563] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10856 23:12:43.911814 es.mount[0m - Huge Pages File System.
10857 23:12:43.932608 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.<30>[ 21.826397] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
10858 23:12:43.942603 mount[…- POSI<3>[ 21.830345] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10859 23:12:43.945470 X Message Queue File System.
10860 23:12:43.959584 <3>[ 21.856930] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10861 23:12:43.973588 [[0;32m OK [0m] Mounted [0;<30>[ 21.867729] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
10862 23:12:43.977072 1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10863 23:12:43.987445 <3>[ 21.883744] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10864 23:12:44.001974 [[0;32m OK [0m] Finished [0<30>[ 21.895625] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
10865 23:12:44.011844 ;1;39mkmod-stati<3>[ 21.903868] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10866 23:12:44.015743 c-nodes…reate List of Static Device Nodes.
10867 23:12:44.037863 [[0;32m OK [0m] Finished [0<30>[ 21.930878] systemd[1]: modprobe@configfs.service: Deactivated successfully.
10868 23:12:44.044543 <30>[ 21.931560] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
10869 23:12:44.051177 ;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10870 23:12:44.063817 <3>[ 21.959058] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10871 23:12:44.074819 [[0;32m OK [0m] Finished [0<30>[ 21.971367] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
10872 23:12:44.085002 ;1;39mmodprobe@d<30>[ 21.971863] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
10873 23:12:44.088063 m_mod.s…e[0m - Load Kernel Module dm_mod.
10874 23:12:44.100075 <3>[ 21.994189] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10875 23:12:44.110745 [[0;32m OK [0m] Finished [0<30>[ 22.007406] systemd[1]: modprobe@drm.service: Deactivated successfully.
10876 23:12:44.120944 ;1;39mmodprobe@d<30>[ 22.007858] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
10877 23:12:44.131550 rm.service[0m -<3>[ 22.014916] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10878 23:12:44.141282 Load Kernel Mod<3>[ 22.036646] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10879 23:12:44.141961 ule drm.
10880 23:12:44.164203 [[0;32m OK [0m] Finished [0<30>[ 22.058681] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
10881 23:12:44.175196 ;1;39mmodprobe@e<30>[ 22.058934] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
10882 23:12:44.178600 fi_psto…m - Load Kernel Module efi_pstore.
10883 23:12:44.199946 [[0;32m OK [0m] Started [0;1;39msystemd-jou<30>[ 22.094406] systemd[1]: Started systemd-journald.service - Journal Service.
10884 23:12:44.204083 rnald.service[0m - Journal Service.
10885 23:12:44.225623 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
10886 23:12:44.247307 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10887 23:12:44.265871 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10888 23:12:44.285965 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10889 23:12:44.316008 [[0;32m OK [0m] Finished [0<4>[ 22.204957] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10890 23:12:44.326033 ;1;39msystemd-re<3>[ 22.204967] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10891 23:12:44.329275 mount-f…ount Root and Kernel File Systems.
10892 23:12:44.349611 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10893 23:12:44.370711 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10894 23:12:44.424143 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
10895 23:12:44.444619 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10896 23:12:44.467803 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10897 23:12:44.490920 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10898 23:12:44.520643 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10899 23:12:44.538900 <46>[ 22.434936] systemd-journald[315]: Received client request to flush runtime journal.
10900 23:12:44.555870 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10901 23:12:44.586123 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
10902 23:12:44.605213 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10903 23:12:44.625675 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10904 23:12:44.645747 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10905 23:12:45.671360 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10906 23:12:45.712044 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10907 23:12:45.958210 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10908 23:12:46.091700 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10909 23:12:46.108194 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10910 23:12:46.127430 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10911 23:12:46.188826 Starting [0;1;39msystemd-binfmt.se…et Up Additional Binary Formats...
10912 23:12:46.210618 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10913 23:12:46.235621 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10914 23:12:46.266700 [[0;1;31mFAILED[0m] Failed to start [0;1;39msystemd-bi… Set Up Additional Binary Formats.
10915 23:12:46.279787 See 'systemctl status systemd-binfmt.service' for details.
10916 23:12:46.539171 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10917 23:12:46.593101 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
10918 23:12:46.655835 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10919 23:12:46.764995 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10920 23:12:46.949484 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10921 23:12:46.983558 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10922 23:12:47.044413 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
10923 23:12:47.064789 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
10924 23:12:47.144962 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
10925 23:12:47.201060 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
10926 23:12:47.220680 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10927 23:12:47.245446 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
10928 23:12:47.295948 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
10929 23:12:47.322093 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
10930 23:12:47.337187 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10931 23:12:47.349906 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
10932 23:12:47.372416 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10933 23:12:47.392481 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10934 23:12:47.415501 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10935 23:12:47.441088 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
10936 23:12:47.463287 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
10937 23:12:47.485012 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
10938 23:12:47.536508 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
10939 23:12:47.564572 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
10940 23:12:47.583963 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
10941 23:12:47.605302 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
10942 23:12:47.623963 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
10943 23:12:47.641640 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
10944 23:12:47.687287 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
10945 23:12:47.725505 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
10946 23:12:47.851964 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
10947 23:12:47.876634 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
10948 23:12:47.899499 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
10949 23:12:48.024461 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
10950 23:12:48.084037 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
10951 23:12:48.105795 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
10952 23:12:48.125924 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
10953 23:12:48.143713 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
10954 23:12:48.184120 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
10955 23:12:48.208651 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
10956 23:12:48.241969 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
10957 23:12:48.261861 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
10958 23:12:48.334475 Starting [0;1;39msystemd-hostnamed.service[0m - Hostname Service...
10959 23:12:48.360300 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
10960 23:12:48.418526 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
10961 23:12:48.458026 [[0;32m OK [0m] Started [0;1;39msystemd-hostnamed.service[0m - Hostname Service.
10962 23:12:48.545914
10963 23:12:48.546068
10964 23:12:48.548975 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
10965 23:12:48.549058
10966 23:12:48.552424 debian-bookworm-arm64 login: root (automatic login)
10967 23:12:48.552537
10968 23:12:48.552606
10969 23:12:48.888770 Linux debian-bookworm-arm64 6.1.67-cip12-rt7 #1 SMP PREEMPT Wed Dec 27 22:50:56 UTC 2023 aarch64
10970 23:12:48.889390
10971 23:12:48.895363 The programs included with the Debian GNU/Linux system are free software;
10972 23:12:48.901535 the exact distribution terms for each program are described in the
10973 23:12:48.905170 individual files in /usr/share/doc/*/copyright.
10974 23:12:48.905766
10975 23:12:48.911899 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10976 23:12:48.915134 permitted by applicable law.
10977 23:12:50.085412 Matched prompt #10: / #
10979 23:12:50.085794 Setting prompt string to ['/ #']
10980 23:12:50.085929 end: 2.2.5.1 login-action (duration 00:00:29) [common]
10982 23:12:50.086217 end: 2.2.5 auto-login-action (duration 00:00:29) [common]
10983 23:12:50.086343 start: 2.2.6 expect-shell-connection (timeout 00:03:14) [common]
10984 23:12:50.086450 Setting prompt string to ['/ #']
10985 23:12:50.086541 Forcing a shell prompt, looking for ['/ #']
10987 23:12:50.136841 / #
10988 23:12:50.137340 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10989 23:12:50.137887 Waiting using forced prompt support (timeout 00:02:30)
10990 23:12:50.142655
10991 23:12:50.143415 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10992 23:12:50.143886 start: 2.2.7 export-device-env (timeout 00:03:14) [common]
10994 23:12:50.244933 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12395393/extract-nfsrootfs-a7c1iqj5'
10995 23:12:50.249931 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12395393/extract-nfsrootfs-a7c1iqj5'
10997 23:12:50.350460 / # export NFS_SERVER_IP='192.168.201.1'
10998 23:12:50.355676 export NFS_SERVER_IP='192.168.201.1'
10999 23:12:50.355965 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11000 23:12:50.356066 end: 2.2 depthcharge-retry (duration 00:01:46) [common]
11001 23:12:50.356161 end: 2 depthcharge-action (duration 00:01:46) [common]
11002 23:12:50.356253 start: 3 lava-test-retry (timeout 00:07:33) [common]
11003 23:12:50.356342 start: 3.1 lava-test-shell (timeout 00:07:33) [common]
11004 23:12:50.356418 Using namespace: common
11006 23:12:50.456790 / # #
11007 23:12:50.456945 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11008 23:12:50.461746 #
11009 23:12:50.462012 Using /lava-12395393
11011 23:12:50.562321 / # export SHELL=/bin/bash
11012 23:12:50.567214 export SHELL=/bin/bash
11014 23:12:50.667710 / # . /lava-12395393/environment
11015 23:12:50.672693 . /lava-12395393/environment
11017 23:12:50.779647 / # /lava-12395393/bin/lava-test-runner /lava-12395393/0
11018 23:12:50.779837 Test shell timeout: 10s (minimum of the action and connection timeout)
11019 23:12:50.784272 /lava-12395393/bin/lava-test-runner /lava-12395393/0
11020 23:12:51.052274 + export TESTRUN_ID=0_timesync-off
11021 23:12:51.055931 + TESTRUN_ID=0_timesync-off
11022 23:12:51.059312 + cd /lava-12395393/0/tests/0_timesync-off
11023 23:12:51.062376 ++ cat uuid
11024 23:12:51.066564 + UUID=12395393_1.6.2.3.1
11025 23:12:51.066651 + set +x
11026 23:12:51.073404 <LAVA_SIGNAL_STARTRUN 0_timesync-off 12395393_1.6.2.3.1>
11027 23:12:51.073719 Received signal: <STARTRUN> 0_timesync-off 12395393_1.6.2.3.1
11028 23:12:51.073796 Starting test lava.0_timesync-off (12395393_1.6.2.3.1)
11029 23:12:51.073882 Skipping test definition patterns.
11030 23:12:51.076598 + systemctl stop systemd-timesyncd
11031 23:12:51.130368 + set +x
11032 23:12:51.133908 <LAVA_SIGNAL_ENDRUN 0_timesync-off 12395393_1.6.2.3.1>
11033 23:12:51.134172 Received signal: <ENDRUN> 0_timesync-off 12395393_1.6.2.3.1
11034 23:12:51.134257 Ending use of test pattern.
11035 23:12:51.134318 Ending test lava.0_timesync-off (12395393_1.6.2.3.1), duration 0.06
11037 23:12:51.210545 + export TESTRUN_ID=1_kselftest-alsa
11038 23:12:51.214068 + TESTRUN_ID=1_kselftest-alsa
11039 23:12:51.220549 + cd /lava-12395393/0/tests/1_kselftest-alsa
11040 23:12:51.220655 ++ cat uuid
11041 23:12:51.224707 + UUID=12395393_1.6.2.3.5
11042 23:12:51.224782 + set +x
11043 23:12:51.231242 <LAVA_SIGNAL_STARTRUN 1_kselftest-alsa 12395393_1.6.2.3.5>
11044 23:12:51.231534 Received signal: <STARTRUN> 1_kselftest-alsa 12395393_1.6.2.3.5
11045 23:12:51.231634 Starting test lava.1_kselftest-alsa (12395393_1.6.2.3.5)
11046 23:12:51.231748 Skipping test definition patterns.
11047 23:12:51.234403 + cd ./automated/linux/kselftest/
11048 23:12:51.264049 + ./kselftest.sh -c alsa -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.66-cip11-rt6-10-g38253b8903b4/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip-gitlab -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11049 23:12:51.304299 INFO: install_deps skipped
11050 23:12:51.828652 --2023-12-27 23:12:52-- http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.66-cip11-rt6-10-g38253b8903b4/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11051 23:12:51.835502 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11052 23:12:51.963581 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11053 23:12:52.097571 HTTP request sent, awaiting response... 200 OK
11054 23:12:52.100669 Length: 2966456 (2.8M) [application/octet-stream]
11055 23:12:52.104030 Saving to: 'kselftest.tar.xz'
11056 23:12:52.104631
11057 23:12:52.104978
11058 23:12:52.364149 kselftest.tar.xz 0%[ ] 0 --.-KB/s
11059 23:12:52.631256 kselftest.tar.xz 1%[ ] 47.81K 185KB/s
11060 23:12:53.085957 kselftest.tar.xz 7%[> ] 217.50K 420KB/s
11061 23:12:53.299316 kselftest.tar.xz 28%[====> ] 827.89K 861KB/s
11062 23:12:53.336190 kselftest.tar.xz 90%[=================> ] 2.55M 2.18MB/s
11063 23:12:53.342670 kselftest.tar.xz 100%[===================>] 2.83M 2.35MB/s in 1.2s
11064 23:12:53.343269
11065 23:12:53.602483 2023-12-27 23:12:53 (2.35 MB/s) - 'kselftest.tar.xz' saved [2966456/2966456]
11066 23:12:53.602922
11067 23:13:00.460242 skiplist:
11068 23:13:00.463127 ========================================
11069 23:13:00.466612 ========================================
11070 23:13:00.526348 alsa:mixer-test
11071 23:13:00.552739 ============== Tests to run ===============
11072 23:13:00.556240 alsa:mixer-test
11073 23:13:00.559350 ===========End Tests to run ===============
11074 23:13:00.565114 shardfile-alsa pass
11075 23:13:00.687541 <12>[ 38.589742] kselftest: Running tests in alsa
11076 23:13:00.697656 TAP version 13
11077 23:13:00.716274 1..1
11078 23:13:00.738970 # selftests: alsa: mixer-test
11079 23:13:01.280178 # TAP version 13
11080 23:13:01.280350 # 1..0
11081 23:13:01.286622 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:0 error:0
11082 23:13:01.290414 ok 1 selftests: alsa: mixer-test
11083 23:13:02.059304 alsa_mixer-test pass
11084 23:13:02.106689 + ../../utils/send-to-lava.sh ./output/result.txt
11085 23:13:02.201597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-alsa RESULT=pass>
11086 23:13:02.202519 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-alsa RESULT=pass
11088 23:13:02.266286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test RESULT=pass>
11089 23:13:02.266728 + set +x
11090 23:13:02.267334 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test RESULT=pass
11092 23:13:02.273101 <LAVA_SIGNAL_ENDRUN 1_kselftest-alsa 12395393_1.6.2.3.5>
11093 23:13:02.273829 Received signal: <ENDRUN> 1_kselftest-alsa 12395393_1.6.2.3.5
11094 23:13:02.274222 Ending use of test pattern.
11095 23:13:02.274547 Ending test lava.1_kselftest-alsa (12395393_1.6.2.3.5), duration 11.04
11097 23:13:02.276060 <LAVA_TEST_RUNNER EXIT>
11098 23:13:02.276761 ok: lava_test_shell seems to have completed
11099 23:13:02.277290 alsa_mixer-test: pass
shardfile-alsa: pass
11100 23:13:02.277766 end: 3.1 lava-test-shell (duration 00:00:12) [common]
11101 23:13:02.278194 end: 3 lava-test-retry (duration 00:00:12) [common]
11102 23:13:02.278619 start: 4 finalize (timeout 00:07:21) [common]
11103 23:13:02.279073 start: 4.1 power-off (timeout 00:00:30) [common]
11104 23:13:02.279817 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=off'
11105 23:13:02.401593 >> Command sent successfully.
11106 23:13:02.405275 Returned 0 in 0 seconds
11107 23:13:02.506152 end: 4.1 power-off (duration 00:00:00) [common]
11109 23:13:02.507684 start: 4.2 read-feedback (timeout 00:07:21) [common]
11110 23:13:02.508893 Listened to connection for namespace 'common' for up to 1s
11111 23:13:03.509687 Finalising connection for namespace 'common'
11112 23:13:03.510307 Disconnecting from shell: Finalise
11113 23:13:03.510702 / #
11114 23:13:03.611642 end: 4.2 read-feedback (duration 00:00:01) [common]
11115 23:13:03.612371 end: 4 finalize (duration 00:00:01) [common]
11116 23:13:03.612989 Cleaning after the job
11117 23:13:03.613593 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12395393/tftp-deploy-jk3l625h/ramdisk
11118 23:13:03.627189 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12395393/tftp-deploy-jk3l625h/kernel
11119 23:13:03.660661 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12395393/tftp-deploy-jk3l625h/dtb
11120 23:13:03.660962 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12395393/tftp-deploy-jk3l625h/nfsrootfs
11121 23:13:03.764254 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12395393/tftp-deploy-jk3l625h/modules
11122 23:13:03.771505 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12395393
11123 23:13:04.434265 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12395393
11124 23:13:04.434454 Job finished correctly