Boot log: mt8192-asurada-spherion-r0
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 14
- Kernel Errors: 36
- Errors: 0
1 23:11:49.768313 lava-dispatcher, installed at version: 2023.10
2 23:11:49.768534 start: 0 validate
3 23:11:49.768666 Start time: 2023-12-27 23:11:49.768657+00:00 (UTC)
4 23:11:49.768783 Using caching service: 'http://localhost/cache/?uri=%s'
5 23:11:49.768915 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230623.0%2Farm64%2Finitrd.cpio.gz exists
6 23:11:50.030789 Using caching service: 'http://localhost/cache/?uri=%s'
7 23:11:50.031524 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.66-cip11-rt6-10-g38253b8903b4%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 23:11:50.295040 Using caching service: 'http://localhost/cache/?uri=%s'
9 23:11:50.295861 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.66-cip11-rt6-10-g38253b8903b4%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 23:11:50.559208 Using caching service: 'http://localhost/cache/?uri=%s'
11 23:11:50.560026 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230623.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 23:11:50.823148 Using caching service: 'http://localhost/cache/?uri=%s'
13 23:11:50.823981 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.66-cip11-rt6-10-g38253b8903b4%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 23:11:51.085530 validate duration: 1.32
16 23:11:51.086773 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 23:11:51.087326 start: 1.1 download-retry (timeout 00:10:00) [common]
18 23:11:51.087881 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 23:11:51.088497 Not decompressing ramdisk as can be used compressed.
20 23:11:51.088964 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230623.0/arm64/initrd.cpio.gz
21 23:11:51.089346 saving as /var/lib/lava/dispatcher/tmp/12395410/tftp-deploy-_gi8__3c/ramdisk/initrd.cpio.gz
22 23:11:51.089751 total size: 4665395 (4 MB)
23 23:11:51.095320 progress 0 % (0 MB)
24 23:11:51.103791 progress 5 % (0 MB)
25 23:11:51.109906 progress 10 % (0 MB)
26 23:11:51.114221 progress 15 % (0 MB)
27 23:11:51.117775 progress 20 % (0 MB)
28 23:11:51.120765 progress 25 % (1 MB)
29 23:11:51.123459 progress 30 % (1 MB)
30 23:11:51.125868 progress 35 % (1 MB)
31 23:11:51.128143 progress 40 % (1 MB)
32 23:11:51.130516 progress 45 % (2 MB)
33 23:11:51.132545 progress 50 % (2 MB)
34 23:11:51.134326 progress 55 % (2 MB)
35 23:11:51.136098 progress 60 % (2 MB)
36 23:11:51.137825 progress 65 % (2 MB)
37 23:11:51.139381 progress 70 % (3 MB)
38 23:11:51.140955 progress 75 % (3 MB)
39 23:11:51.142517 progress 80 % (3 MB)
40 23:11:51.144128 progress 85 % (3 MB)
41 23:11:51.145534 progress 90 % (4 MB)
42 23:11:51.146938 progress 95 % (4 MB)
43 23:11:51.148294 progress 100 % (4 MB)
44 23:11:51.148453 4 MB downloaded in 0.06 s (75.76 MB/s)
45 23:11:51.148605 end: 1.1.1 http-download (duration 00:00:00) [common]
47 23:11:51.148851 end: 1.1 download-retry (duration 00:00:00) [common]
48 23:11:51.148940 start: 1.2 download-retry (timeout 00:10:00) [common]
49 23:11:51.149026 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 23:11:51.149162 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.66-cip11-rt6-10-g38253b8903b4/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 23:11:51.149232 saving as /var/lib/lava/dispatcher/tmp/12395410/tftp-deploy-_gi8__3c/kernel/Image
52 23:11:51.149294 total size: 50024960 (47 MB)
53 23:11:51.149357 No compression specified
54 23:11:51.150473 progress 0 % (0 MB)
55 23:11:51.163427 progress 5 % (2 MB)
56 23:11:51.176402 progress 10 % (4 MB)
57 23:11:51.189213 progress 15 % (7 MB)
58 23:11:51.202325 progress 20 % (9 MB)
59 23:11:51.215282 progress 25 % (11 MB)
60 23:11:51.228264 progress 30 % (14 MB)
61 23:11:51.241539 progress 35 % (16 MB)
62 23:11:51.254469 progress 40 % (19 MB)
63 23:11:51.267280 progress 45 % (21 MB)
64 23:11:51.280437 progress 50 % (23 MB)
65 23:11:51.293259 progress 55 % (26 MB)
66 23:11:51.306206 progress 60 % (28 MB)
67 23:11:51.319367 progress 65 % (31 MB)
68 23:11:51.332297 progress 70 % (33 MB)
69 23:11:51.345181 progress 75 % (35 MB)
70 23:11:51.358370 progress 80 % (38 MB)
71 23:11:51.371436 progress 85 % (40 MB)
72 23:11:51.384279 progress 90 % (42 MB)
73 23:11:51.397107 progress 95 % (45 MB)
74 23:11:51.410369 progress 100 % (47 MB)
75 23:11:51.410578 47 MB downloaded in 0.26 s (182.59 MB/s)
76 23:11:51.410728 end: 1.2.1 http-download (duration 00:00:00) [common]
78 23:11:51.410962 end: 1.2 download-retry (duration 00:00:00) [common]
79 23:11:51.411048 start: 1.3 download-retry (timeout 00:10:00) [common]
80 23:11:51.411136 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 23:11:51.411282 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.66-cip11-rt6-10-g38253b8903b4/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 23:11:51.411378 saving as /var/lib/lava/dispatcher/tmp/12395410/tftp-deploy-_gi8__3c/dtb/mt8192-asurada-spherion-r0.dtb
83 23:11:51.411467 total size: 47278 (0 MB)
84 23:11:51.411557 No compression specified
85 23:11:51.413390 progress 69 % (0 MB)
86 23:11:51.413694 progress 100 % (0 MB)
87 23:11:51.413872 0 MB downloaded in 0.00 s (18.77 MB/s)
88 23:11:51.413995 end: 1.3.1 http-download (duration 00:00:00) [common]
90 23:11:51.414218 end: 1.3 download-retry (duration 00:00:00) [common]
91 23:11:51.414305 start: 1.4 download-retry (timeout 00:10:00) [common]
92 23:11:51.414387 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 23:11:51.414498 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230623.0/arm64/full.rootfs.tar.xz
94 23:11:51.414564 saving as /var/lib/lava/dispatcher/tmp/12395410/tftp-deploy-_gi8__3c/nfsrootfs/full.rootfs.tar
95 23:11:51.414623 total size: 200813988 (191 MB)
96 23:11:51.414683 Using unxz to decompress xz
97 23:11:51.418770 progress 0 % (0 MB)
98 23:11:51.943530 progress 5 % (9 MB)
99 23:11:52.453480 progress 10 % (19 MB)
100 23:11:53.033775 progress 15 % (28 MB)
101 23:11:53.404733 progress 20 % (38 MB)
102 23:11:53.726307 progress 25 % (47 MB)
103 23:11:54.310617 progress 30 % (57 MB)
104 23:11:54.858091 progress 35 % (67 MB)
105 23:11:55.444806 progress 40 % (76 MB)
106 23:11:55.998882 progress 45 % (86 MB)
107 23:11:56.574380 progress 50 % (95 MB)
108 23:11:57.198136 progress 55 % (105 MB)
109 23:11:57.852448 progress 60 % (114 MB)
110 23:11:57.971173 progress 65 % (124 MB)
111 23:11:58.109700 progress 70 % (134 MB)
112 23:11:58.205523 progress 75 % (143 MB)
113 23:11:58.275944 progress 80 % (153 MB)
114 23:11:58.344188 progress 85 % (162 MB)
115 23:11:58.444661 progress 90 % (172 MB)
116 23:11:58.718859 progress 95 % (181 MB)
117 23:11:59.287272 progress 100 % (191 MB)
118 23:11:59.292533 191 MB downloaded in 7.88 s (24.31 MB/s)
119 23:11:59.292778 end: 1.4.1 http-download (duration 00:00:08) [common]
121 23:11:59.293040 end: 1.4 download-retry (duration 00:00:08) [common]
122 23:11:59.293132 start: 1.5 download-retry (timeout 00:09:52) [common]
123 23:11:59.293220 start: 1.5.1 http-download (timeout 00:09:52) [common]
124 23:11:59.293379 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.66-cip11-rt6-10-g38253b8903b4/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 23:11:59.293449 saving as /var/lib/lava/dispatcher/tmp/12395410/tftp-deploy-_gi8__3c/modules/modules.tar
126 23:11:59.293511 total size: 8633892 (8 MB)
127 23:11:59.293575 Using unxz to decompress xz
128 23:11:59.297849 progress 0 % (0 MB)
129 23:11:59.318811 progress 5 % (0 MB)
130 23:11:59.342177 progress 10 % (0 MB)
131 23:11:59.365394 progress 15 % (1 MB)
132 23:11:59.388577 progress 20 % (1 MB)
133 23:11:59.412125 progress 25 % (2 MB)
134 23:11:59.439417 progress 30 % (2 MB)
135 23:11:59.463183 progress 35 % (2 MB)
136 23:11:59.486320 progress 40 % (3 MB)
137 23:11:59.509940 progress 45 % (3 MB)
138 23:11:59.534751 progress 50 % (4 MB)
139 23:11:59.558646 progress 55 % (4 MB)
140 23:11:59.586585 progress 60 % (4 MB)
141 23:11:59.612035 progress 65 % (5 MB)
142 23:11:59.636498 progress 70 % (5 MB)
143 23:11:59.659976 progress 75 % (6 MB)
144 23:11:59.688180 progress 80 % (6 MB)
145 23:11:59.714705 progress 85 % (7 MB)
146 23:11:59.742228 progress 90 % (7 MB)
147 23:11:59.772995 progress 95 % (7 MB)
148 23:11:59.802023 progress 100 % (8 MB)
149 23:11:59.807579 8 MB downloaded in 0.51 s (16.02 MB/s)
150 23:11:59.807890 end: 1.5.1 http-download (duration 00:00:01) [common]
152 23:11:59.808168 end: 1.5 download-retry (duration 00:00:01) [common]
153 23:11:59.808265 start: 1.6 prepare-tftp-overlay (timeout 00:09:51) [common]
154 23:11:59.808362 start: 1.6.1 extract-nfsrootfs (timeout 00:09:51) [common]
155 23:12:03.381472 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/12395410/extract-nfsrootfs-71p0c99j
156 23:12:03.381674 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 23:12:03.381771 start: 1.6.2 lava-overlay (timeout 00:09:48) [common]
158 23:12:03.381971 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12395410/lava-overlay-ul5xpho2
159 23:12:03.382117 makedir: /var/lib/lava/dispatcher/tmp/12395410/lava-overlay-ul5xpho2/lava-12395410/bin
160 23:12:03.382223 makedir: /var/lib/lava/dispatcher/tmp/12395410/lava-overlay-ul5xpho2/lava-12395410/tests
161 23:12:03.382325 makedir: /var/lib/lava/dispatcher/tmp/12395410/lava-overlay-ul5xpho2/lava-12395410/results
162 23:12:03.382427 Creating /var/lib/lava/dispatcher/tmp/12395410/lava-overlay-ul5xpho2/lava-12395410/bin/lava-add-keys
163 23:12:03.382577 Creating /var/lib/lava/dispatcher/tmp/12395410/lava-overlay-ul5xpho2/lava-12395410/bin/lava-add-sources
164 23:12:03.382717 Creating /var/lib/lava/dispatcher/tmp/12395410/lava-overlay-ul5xpho2/lava-12395410/bin/lava-background-process-start
165 23:12:03.382861 Creating /var/lib/lava/dispatcher/tmp/12395410/lava-overlay-ul5xpho2/lava-12395410/bin/lava-background-process-stop
166 23:12:03.382993 Creating /var/lib/lava/dispatcher/tmp/12395410/lava-overlay-ul5xpho2/lava-12395410/bin/lava-common-functions
167 23:12:03.383121 Creating /var/lib/lava/dispatcher/tmp/12395410/lava-overlay-ul5xpho2/lava-12395410/bin/lava-echo-ipv4
168 23:12:03.383250 Creating /var/lib/lava/dispatcher/tmp/12395410/lava-overlay-ul5xpho2/lava-12395410/bin/lava-install-packages
169 23:12:03.383376 Creating /var/lib/lava/dispatcher/tmp/12395410/lava-overlay-ul5xpho2/lava-12395410/bin/lava-installed-packages
170 23:12:03.383501 Creating /var/lib/lava/dispatcher/tmp/12395410/lava-overlay-ul5xpho2/lava-12395410/bin/lava-os-build
171 23:12:03.383626 Creating /var/lib/lava/dispatcher/tmp/12395410/lava-overlay-ul5xpho2/lava-12395410/bin/lava-probe-channel
172 23:12:03.383768 Creating /var/lib/lava/dispatcher/tmp/12395410/lava-overlay-ul5xpho2/lava-12395410/bin/lava-probe-ip
173 23:12:03.383894 Creating /var/lib/lava/dispatcher/tmp/12395410/lava-overlay-ul5xpho2/lava-12395410/bin/lava-target-ip
174 23:12:03.384020 Creating /var/lib/lava/dispatcher/tmp/12395410/lava-overlay-ul5xpho2/lava-12395410/bin/lava-target-mac
175 23:12:03.384145 Creating /var/lib/lava/dispatcher/tmp/12395410/lava-overlay-ul5xpho2/lava-12395410/bin/lava-target-storage
176 23:12:03.384274 Creating /var/lib/lava/dispatcher/tmp/12395410/lava-overlay-ul5xpho2/lava-12395410/bin/lava-test-case
177 23:12:03.384400 Creating /var/lib/lava/dispatcher/tmp/12395410/lava-overlay-ul5xpho2/lava-12395410/bin/lava-test-event
178 23:12:03.384523 Creating /var/lib/lava/dispatcher/tmp/12395410/lava-overlay-ul5xpho2/lava-12395410/bin/lava-test-feedback
179 23:12:03.384648 Creating /var/lib/lava/dispatcher/tmp/12395410/lava-overlay-ul5xpho2/lava-12395410/bin/lava-test-raise
180 23:12:03.384773 Creating /var/lib/lava/dispatcher/tmp/12395410/lava-overlay-ul5xpho2/lava-12395410/bin/lava-test-reference
181 23:12:03.384900 Creating /var/lib/lava/dispatcher/tmp/12395410/lava-overlay-ul5xpho2/lava-12395410/bin/lava-test-runner
182 23:12:03.385026 Creating /var/lib/lava/dispatcher/tmp/12395410/lava-overlay-ul5xpho2/lava-12395410/bin/lava-test-set
183 23:12:03.385152 Creating /var/lib/lava/dispatcher/tmp/12395410/lava-overlay-ul5xpho2/lava-12395410/bin/lava-test-shell
184 23:12:03.385280 Updating /var/lib/lava/dispatcher/tmp/12395410/lava-overlay-ul5xpho2/lava-12395410/bin/lava-add-keys (debian)
185 23:12:03.385434 Updating /var/lib/lava/dispatcher/tmp/12395410/lava-overlay-ul5xpho2/lava-12395410/bin/lava-add-sources (debian)
186 23:12:03.385577 Updating /var/lib/lava/dispatcher/tmp/12395410/lava-overlay-ul5xpho2/lava-12395410/bin/lava-install-packages (debian)
187 23:12:03.385719 Updating /var/lib/lava/dispatcher/tmp/12395410/lava-overlay-ul5xpho2/lava-12395410/bin/lava-installed-packages (debian)
188 23:12:03.385860 Updating /var/lib/lava/dispatcher/tmp/12395410/lava-overlay-ul5xpho2/lava-12395410/bin/lava-os-build (debian)
189 23:12:03.385983 Creating /var/lib/lava/dispatcher/tmp/12395410/lava-overlay-ul5xpho2/lava-12395410/environment
190 23:12:03.386081 LAVA metadata
191 23:12:03.386150 - LAVA_JOB_ID=12395410
192 23:12:03.386212 - LAVA_DISPATCHER_IP=192.168.201.1
193 23:12:03.386313 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:48) [common]
194 23:12:03.386380 skipped lava-vland-overlay
195 23:12:03.386454 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 23:12:03.386533 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:48) [common]
197 23:12:03.386594 skipped lava-multinode-overlay
198 23:12:03.386679 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 23:12:03.386758 start: 1.6.2.3 test-definition (timeout 00:09:48) [common]
200 23:12:03.386832 Loading test definitions
201 23:12:03.386919 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:48) [common]
202 23:12:03.386990 Using /lava-12395410 at stage 0
203 23:12:03.387286 uuid=12395410_1.6.2.3.1 testdef=None
204 23:12:03.387373 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 23:12:03.387457 start: 1.6.2.3.2 test-overlay (timeout 00:09:48) [common]
206 23:12:03.388030 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 23:12:03.388248 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:48) [common]
209 23:12:03.388808 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 23:12:03.389036 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:48) [common]
212 23:12:03.389576 runner path: /var/lib/lava/dispatcher/tmp/12395410/lava-overlay-ul5xpho2/lava-12395410/0/tests/0_timesync-off test_uuid 12395410_1.6.2.3.1
213 23:12:03.389731 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 23:12:03.389953 start: 1.6.2.3.5 git-repo-action (timeout 00:09:48) [common]
216 23:12:03.390025 Using /lava-12395410 at stage 0
217 23:12:03.390120 Fetching tests from https://github.com/kernelci/test-definitions.git
218 23:12:03.390197 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/12395410/lava-overlay-ul5xpho2/lava-12395410/0/tests/1_kselftest-arm64'
219 23:12:07.254654 Running '/usr/bin/git checkout kernelci.org
220 23:12:07.400968 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/12395410/lava-overlay-ul5xpho2/lava-12395410/0/tests/1_kselftest-arm64/automated/linux/kselftest/kselftest.yaml
221 23:12:07.401724 uuid=12395410_1.6.2.3.5 testdef=None
222 23:12:07.401877 end: 1.6.2.3.5 git-repo-action (duration 00:00:04) [common]
224 23:12:07.402124 start: 1.6.2.3.6 test-overlay (timeout 00:09:44) [common]
225 23:12:07.402850 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 23:12:07.403076 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:44) [common]
228 23:12:07.404084 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 23:12:07.404312 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:44) [common]
231 23:12:07.405222 runner path: /var/lib/lava/dispatcher/tmp/12395410/lava-overlay-ul5xpho2/lava-12395410/0/tests/1_kselftest-arm64 test_uuid 12395410_1.6.2.3.5
232 23:12:07.405315 BOARD='mt8192-asurada-spherion-r0'
233 23:12:07.405379 BRANCH='cip-gitlab'
234 23:12:07.405438 SKIPFILE='/dev/null'
235 23:12:07.405495 SKIP_INSTALL='True'
236 23:12:07.405549 TESTPROG_URL='http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.66-cip11-rt6-10-g38253b8903b4/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 23:12:07.405605 TST_CASENAME=''
238 23:12:07.405658 TST_CMDFILES='arm64'
239 23:12:07.405799 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 23:12:07.405996 Creating lava-test-runner.conf files
242 23:12:07.406059 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12395410/lava-overlay-ul5xpho2/lava-12395410/0 for stage 0
243 23:12:07.406152 - 0_timesync-off
244 23:12:07.406224 - 1_kselftest-arm64
245 23:12:07.406319 end: 1.6.2.3 test-definition (duration 00:00:04) [common]
246 23:12:07.406408 start: 1.6.2.4 compress-overlay (timeout 00:09:44) [common]
247 23:12:14.839922 end: 1.6.2.4 compress-overlay (duration 00:00:07) [common]
248 23:12:14.840079 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:36) [common]
249 23:12:14.840173 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 23:12:14.840271 end: 1.6.2 lava-overlay (duration 00:00:11) [common]
251 23:12:14.840359 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:36) [common]
252 23:12:14.959864 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 23:12:14.960257 start: 1.6.4 extract-modules (timeout 00:09:36) [common]
254 23:12:14.960383 extracting modules file /var/lib/lava/dispatcher/tmp/12395410/tftp-deploy-_gi8__3c/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12395410/extract-nfsrootfs-71p0c99j
255 23:12:15.179492 extracting modules file /var/lib/lava/dispatcher/tmp/12395410/tftp-deploy-_gi8__3c/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12395410/extract-overlay-ramdisk-1oyofa7c/ramdisk
256 23:12:15.405412 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 23:12:15.405585 start: 1.6.5 apply-overlay-tftp (timeout 00:09:36) [common]
258 23:12:15.405677 [common] Applying overlay to NFS
259 23:12:15.405749 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12395410/compress-overlay-o8yp_d81/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12395410/extract-nfsrootfs-71p0c99j
260 23:12:16.322959 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 23:12:16.323127 start: 1.6.6 configure-preseed-file (timeout 00:09:35) [common]
262 23:12:16.323220 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 23:12:16.323310 start: 1.6.7 compress-ramdisk (timeout 00:09:35) [common]
264 23:12:16.323390 Building ramdisk /var/lib/lava/dispatcher/tmp/12395410/extract-overlay-ramdisk-1oyofa7c/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12395410/extract-overlay-ramdisk-1oyofa7c/ramdisk
265 23:12:16.655909 >> 119421 blocks
266 23:12:18.564887 rename /var/lib/lava/dispatcher/tmp/12395410/extract-overlay-ramdisk-1oyofa7c/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12395410/tftp-deploy-_gi8__3c/ramdisk/ramdisk.cpio.gz
267 23:12:18.565338 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 23:12:18.565455 start: 1.6.8 prepare-kernel (timeout 00:09:33) [common]
269 23:12:18.565555 start: 1.6.8.1 prepare-fit (timeout 00:09:33) [common]
270 23:12:18.565662 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12395410/tftp-deploy-_gi8__3c/kernel/Image'
271 23:12:30.576100 Returned 0 in 12 seconds
272 23:12:30.677077 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12395410/tftp-deploy-_gi8__3c/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12395410/tftp-deploy-_gi8__3c/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12395410/tftp-deploy-_gi8__3c/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12395410/tftp-deploy-_gi8__3c/kernel/image.itb
273 23:12:31.045957 output: FIT description: Kernel Image image with one or more FDT blobs
274 23:12:31.046354 output: Created: Wed Dec 27 23:12:30 2023
275 23:12:31.046430 output: Image 0 (kernel-1)
276 23:12:31.046495 output: Description:
277 23:12:31.046557 output: Created: Wed Dec 27 23:12:30 2023
278 23:12:31.046617 output: Type: Kernel Image
279 23:12:31.046678 output: Compression: lzma compressed
280 23:12:31.046736 output: Data Size: 11480388 Bytes = 11211.32 KiB = 10.95 MiB
281 23:12:31.046797 output: Architecture: AArch64
282 23:12:31.046855 output: OS: Linux
283 23:12:31.046911 output: Load Address: 0x00000000
284 23:12:31.046969 output: Entry Point: 0x00000000
285 23:12:31.047026 output: Hash algo: crc32
286 23:12:31.047083 output: Hash value: a55b2f0b
287 23:12:31.047144 output: Image 1 (fdt-1)
288 23:12:31.047197 output: Description: mt8192-asurada-spherion-r0
289 23:12:31.047251 output: Created: Wed Dec 27 23:12:30 2023
290 23:12:31.047305 output: Type: Flat Device Tree
291 23:12:31.047358 output: Compression: uncompressed
292 23:12:31.047412 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
293 23:12:31.047465 output: Architecture: AArch64
294 23:12:31.047517 output: Hash algo: crc32
295 23:12:31.047570 output: Hash value: cc4352de
296 23:12:31.047623 output: Image 2 (ramdisk-1)
297 23:12:31.047685 output: Description: unavailable
298 23:12:31.047778 output: Created: Wed Dec 27 23:12:30 2023
299 23:12:31.047832 output: Type: RAMDisk Image
300 23:12:31.047885 output: Compression: Unknown Compression
301 23:12:31.047938 output: Data Size: 17802118 Bytes = 17384.88 KiB = 16.98 MiB
302 23:12:31.047992 output: Architecture: AArch64
303 23:12:31.048045 output: OS: Linux
304 23:12:31.048098 output: Load Address: unavailable
305 23:12:31.048151 output: Entry Point: unavailable
306 23:12:31.048246 output: Hash algo: crc32
307 23:12:31.048299 output: Hash value: 706d8ef6
308 23:12:31.048352 output: Default Configuration: 'conf-1'
309 23:12:31.048405 output: Configuration 0 (conf-1)
310 23:12:31.048457 output: Description: mt8192-asurada-spherion-r0
311 23:12:31.048511 output: Kernel: kernel-1
312 23:12:31.048563 output: Init Ramdisk: ramdisk-1
313 23:12:31.048616 output: FDT: fdt-1
314 23:12:31.048669 output: Loadables: kernel-1
315 23:12:31.048722 output:
316 23:12:31.048926 end: 1.6.8.1 prepare-fit (duration 00:00:12) [common]
317 23:12:31.049027 end: 1.6.8 prepare-kernel (duration 00:00:12) [common]
318 23:12:31.049131 end: 1.6 prepare-tftp-overlay (duration 00:00:31) [common]
319 23:12:31.049227 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:20) [common]
320 23:12:31.049311 No LXC device requested
321 23:12:31.049390 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 23:12:31.049476 start: 1.8 deploy-device-env (timeout 00:09:20) [common]
323 23:12:31.049552 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 23:12:31.049620 Checking files for TFTP limit of 4294967296 bytes.
325 23:12:31.050129 end: 1 tftp-deploy (duration 00:00:40) [common]
326 23:12:31.050238 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 23:12:31.050329 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 23:12:31.050454 substitutions:
329 23:12:31.050525 - {DTB}: 12395410/tftp-deploy-_gi8__3c/dtb/mt8192-asurada-spherion-r0.dtb
330 23:12:31.050592 - {INITRD}: 12395410/tftp-deploy-_gi8__3c/ramdisk/ramdisk.cpio.gz
331 23:12:31.050652 - {KERNEL}: 12395410/tftp-deploy-_gi8__3c/kernel/Image
332 23:12:31.050710 - {LAVA_MAC}: None
333 23:12:31.050767 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/12395410/extract-nfsrootfs-71p0c99j
334 23:12:31.050824 - {NFS_SERVER_IP}: 192.168.201.1
335 23:12:31.050880 - {PRESEED_CONFIG}: None
336 23:12:31.050935 - {PRESEED_LOCAL}: None
337 23:12:31.050990 - {RAMDISK}: 12395410/tftp-deploy-_gi8__3c/ramdisk/ramdisk.cpio.gz
338 23:12:31.051045 - {ROOT_PART}: None
339 23:12:31.051099 - {ROOT}: None
340 23:12:31.051153 - {SERVER_IP}: 192.168.201.1
341 23:12:31.051208 - {TEE}: None
342 23:12:31.051262 Parsed boot commands:
343 23:12:31.051315 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 23:12:31.051502 Parsed boot commands: tftpboot 192.168.201.1 12395410/tftp-deploy-_gi8__3c/kernel/image.itb 12395410/tftp-deploy-_gi8__3c/kernel/cmdline
345 23:12:31.051593 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 23:12:31.051686 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 23:12:31.051816 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 23:12:31.051907 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 23:12:31.051979 Not connected, no need to disconnect.
350 23:12:31.052053 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 23:12:31.052132 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 23:12:31.052202 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-9'
353 23:12:31.056430 Setting prompt string to ['lava-test: # ']
354 23:12:31.056923 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 23:12:31.057075 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 23:12:31.057220 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 23:12:31.057363 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 23:12:31.057675 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=reboot'
359 23:12:36.188408 >> Command sent successfully.
360 23:12:36.190754 Returned 0 in 5 seconds
361 23:12:36.291153 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 23:12:36.291488 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 23:12:36.291590 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 23:12:36.291712 Setting prompt string to 'Starting depthcharge on Spherion...'
366 23:12:36.291795 Changing prompt to 'Starting depthcharge on Spherion...'
367 23:12:36.291865 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 23:12:36.292130 [Enter `^Ec?' for help]
369 23:12:36.465327
370 23:12:36.465485
371 23:12:36.465555 F0: 102B 0000
372 23:12:36.465620
373 23:12:36.465679 F3: 1001 0000 [0200]
374 23:12:36.465738
375 23:12:36.468577 F3: 1001 0000
376 23:12:36.468662
377 23:12:36.468728 F7: 102D 0000
378 23:12:36.468789
379 23:12:36.468848 F1: 0000 0000
380 23:12:36.472698
381 23:12:36.472801 V0: 0000 0000 [0001]
382 23:12:36.472868
383 23:12:36.472930 00: 0007 8000
384 23:12:36.472995
385 23:12:36.475627 01: 0000 0000
386 23:12:36.475763
387 23:12:36.475830 BP: 0C00 0209 [0000]
388 23:12:36.475892
389 23:12:36.479555 G0: 1182 0000
390 23:12:36.479665
391 23:12:36.479774 EC: 0000 0021 [4000]
392 23:12:36.479836
393 23:12:36.482901 S7: 0000 0000 [0000]
394 23:12:36.482985
395 23:12:36.483051 CC: 0000 0000 [0001]
396 23:12:36.483112
397 23:12:36.486531 T0: 0000 0040 [010F]
398 23:12:36.486617
399 23:12:36.486684 Jump to BL
400 23:12:36.486746
401 23:12:36.511309
402 23:12:36.511404
403 23:12:36.511469
404 23:12:36.518492 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 23:12:36.522143 ARM64: Exception handlers installed.
406 23:12:36.526026 ARM64: Testing exception
407 23:12:36.529229 ARM64: Done test exception
408 23:12:36.536346 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 23:12:36.547490 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 23:12:36.554527 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 23:12:36.562086 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 23:12:36.569320 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 23:12:36.579862 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 23:12:36.589592 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 23:12:36.595588 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 23:12:36.614482 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 23:12:36.618252 WDT: Last reset was cold boot
418 23:12:36.620996 SPI1(PAD0) initialized at 2873684 Hz
419 23:12:36.624478 SPI5(PAD0) initialized at 992727 Hz
420 23:12:36.627962 VBOOT: Loading verstage.
421 23:12:36.634410 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 23:12:36.637711 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 23:12:36.640883 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 23:12:36.644274 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 23:12:36.652539 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 23:12:36.658306 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 23:12:36.669425 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
428 23:12:36.669514
429 23:12:36.669580
430 23:12:36.679428 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 23:12:36.682810 ARM64: Exception handlers installed.
432 23:12:36.686125 ARM64: Testing exception
433 23:12:36.686210 ARM64: Done test exception
434 23:12:36.692558 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 23:12:36.696181 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 23:12:36.710813 Probing TPM: . done!
437 23:12:36.710899 TPM ready after 0 ms
438 23:12:36.717324 Connected to device vid:did:rid of 1ae0:0028:00
439 23:12:36.728093 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
440 23:12:36.765618 Initialized TPM device CR50 revision 0
441 23:12:36.777821 tlcl_send_startup: Startup return code is 0
442 23:12:36.777914 TPM: setup succeeded
443 23:12:36.788825 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 23:12:36.797935 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 23:12:36.804430 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 23:12:36.816167 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 23:12:36.819958 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 23:12:36.822949 in-header: 03 07 00 00 08 00 00 00
449 23:12:36.827057 in-data: aa e4 47 04 13 02 00 00
450 23:12:36.829923 Chrome EC: UHEPI supported
451 23:12:36.836778 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 23:12:36.839925 in-header: 03 ad 00 00 08 00 00 00
453 23:12:36.842834 in-data: 00 20 20 08 00 00 00 00
454 23:12:36.842919 Phase 1
455 23:12:36.846409 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 23:12:36.853730 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 23:12:36.860010 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 23:12:36.863105 Recovery requested (1009000e)
459 23:12:36.866605 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 23:12:36.875540 tlcl_extend: response is 0
461 23:12:36.883912 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 23:12:36.889112 tlcl_extend: response is 0
463 23:12:36.895442 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 23:12:36.915966 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
465 23:12:36.922906 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 23:12:36.922992
467 23:12:36.923059
468 23:12:36.933653 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 23:12:36.936642 ARM64: Exception handlers installed.
470 23:12:36.936733 ARM64: Testing exception
471 23:12:36.940746 ARM64: Done test exception
472 23:12:36.962076 pmic_efuse_setting: Set efuses in 11 msecs
473 23:12:36.965775 pmwrap_interface_init: Select PMIF_VLD_RDY
474 23:12:36.972112 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 23:12:36.975314 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 23:12:36.982053 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 23:12:36.985162 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 23:12:36.988448 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 23:12:36.995389 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 23:12:36.998690 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 23:12:37.005281 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 23:12:37.008878 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 23:12:37.015184 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 23:12:37.018486 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 23:12:37.022205 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 23:12:37.028496 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 23:12:37.034970 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 23:12:37.038756 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 23:12:37.045248 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 23:12:37.052069 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 23:12:37.055564 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 23:12:37.062080 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 23:12:37.068323 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 23:12:37.072174 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 23:12:37.078880 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 23:12:37.085781 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 23:12:37.088485 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 23:12:37.095642 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 23:12:37.102271 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 23:12:37.106117 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 23:12:37.109506 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 23:12:37.116091 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 23:12:37.119942 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 23:12:37.126756 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 23:12:37.129980 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 23:12:37.136847 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 23:12:37.140120 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 23:12:37.146729 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 23:12:37.150612 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 23:12:37.156783 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 23:12:37.160159 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 23:12:37.164115 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 23:12:37.167874 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 23:12:37.175142 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 23:12:37.179272 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 23:12:37.181748 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 23:12:37.185466 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 23:12:37.192061 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 23:12:37.195149 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 23:12:37.198582 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 23:12:37.205004 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 23:12:37.208980 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 23:12:37.211803 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 23:12:37.215518 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 23:12:37.225311 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 23:12:37.231489 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 23:12:37.238715 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 23:12:37.245518 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 23:12:37.255048 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 23:12:37.258524 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 23:12:37.262053 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 23:12:37.268076 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 23:12:37.274855 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6c, sec=0x0
534 23:12:37.282062 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 23:12:37.284404 [RTC]rtc_osc_init,62: osc32con val = 0xde6c
536 23:12:37.288213 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 23:12:37.298963 [RTC]rtc_get_frequency_meter,154: input=15, output=834
538 23:12:37.308281 [RTC]rtc_get_frequency_meter,154: input=7, output=709
539 23:12:37.317809 [RTC]rtc_get_frequency_meter,154: input=11, output=772
540 23:12:37.327657 [RTC]rtc_get_frequency_meter,154: input=13, output=803
541 23:12:37.336598 [RTC]rtc_get_frequency_meter,154: input=12, output=788
542 23:12:37.345817 [RTC]rtc_get_frequency_meter,154: input=12, output=787
543 23:12:37.355650 [RTC]rtc_get_frequency_meter,154: input=13, output=803
544 23:12:37.358934 [RTC]rtc_eosc_cali,47: left: 12, middle: 12, right: 13
545 23:12:37.366154 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6c
546 23:12:37.369210 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
547 23:12:37.372844 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
548 23:12:37.379905 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
549 23:12:37.382609 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
550 23:12:37.386017 ADC[4]: Raw value=902661 ID=7
551 23:12:37.386100 ADC[3]: Raw value=214021 ID=1
552 23:12:37.389353 RAM Code: 0x71
553 23:12:37.392522 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
554 23:12:37.400061 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
555 23:12:37.405890 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
556 23:12:37.412887 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
557 23:12:37.415612 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
558 23:12:37.418978 in-header: 03 07 00 00 08 00 00 00
559 23:12:37.422590 in-data: aa e4 47 04 13 02 00 00
560 23:12:37.426179 Chrome EC: UHEPI supported
561 23:12:37.432701 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
562 23:12:37.435876 in-header: 03 dd 00 00 08 00 00 00
563 23:12:37.439050 in-data: 90 20 60 08 00 00 00 00
564 23:12:37.442565 MRC: failed to locate region type 0.
565 23:12:37.449158 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
566 23:12:37.452539 DRAM-K: Running full calibration
567 23:12:37.459124 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
568 23:12:37.459212 header.status = 0x0
569 23:12:37.462344 header.version = 0x6 (expected: 0x6)
570 23:12:37.465625 header.size = 0xd00 (expected: 0xd00)
571 23:12:37.468952 header.flags = 0x0
572 23:12:37.475883 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
573 23:12:37.492438 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
574 23:12:37.498958 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
575 23:12:37.502397 dram_init: ddr_geometry: 2
576 23:12:37.505810 [EMI] MDL number = 2
577 23:12:37.505896 [EMI] Get MDL freq = 0
578 23:12:37.509215 dram_init: ddr_type: 0
579 23:12:37.509322 is_discrete_lpddr4: 1
580 23:12:37.512373 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
581 23:12:37.512458
582 23:12:37.512548
583 23:12:37.516116 [Bian_co] ETT version 0.0.0.1
584 23:12:37.522291 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
585 23:12:37.522377
586 23:12:37.525584 dramc_set_vcore_voltage set vcore to 650000
587 23:12:37.528804 Read voltage for 800, 4
588 23:12:37.528889 Vio18 = 0
589 23:12:37.528956 Vcore = 650000
590 23:12:37.532434 Vdram = 0
591 23:12:37.532518 Vddq = 0
592 23:12:37.532582 Vmddr = 0
593 23:12:37.535425 dram_init: config_dvfs: 1
594 23:12:37.539464 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
595 23:12:37.545378 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
596 23:12:37.548915 [SwImpedanceCal] DRVP=8, DRVN=16, ODTN=9
597 23:12:37.551827 freq_region=0, Reg: DRVP=8, DRVN=16, ODTN=9
598 23:12:37.555586 [SwImpedanceCal] DRVP=14, DRVN=24, ODTN=9
599 23:12:37.561873 freq_region=1, Reg: DRVP=14, DRVN=24, ODTN=9
600 23:12:37.561960 MEM_TYPE=3, freq_sel=18
601 23:12:37.565472 sv_algorithm_assistance_LP4_1600
602 23:12:37.568709 ============ PULL DRAM RESETB DOWN ============
603 23:12:37.575393 ========== PULL DRAM RESETB DOWN end =========
604 23:12:37.579099 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
605 23:12:37.581864 ===================================
606 23:12:37.585643 LPDDR4 DRAM CONFIGURATION
607 23:12:37.588301 ===================================
608 23:12:37.588386 EX_ROW_EN[0] = 0x0
609 23:12:37.591590 EX_ROW_EN[1] = 0x0
610 23:12:37.591697 LP4Y_EN = 0x0
611 23:12:37.595236 WORK_FSP = 0x0
612 23:12:37.595320 WL = 0x2
613 23:12:37.598115 RL = 0x2
614 23:12:37.602304 BL = 0x2
615 23:12:37.602388 RPST = 0x0
616 23:12:37.605370 RD_PRE = 0x0
617 23:12:37.605454 WR_PRE = 0x1
618 23:12:37.608952 WR_PST = 0x0
619 23:12:37.609037 DBI_WR = 0x0
620 23:12:37.611529 DBI_RD = 0x0
621 23:12:37.611612 OTF = 0x1
622 23:12:37.615165 ===================================
623 23:12:37.618127 ===================================
624 23:12:37.621493 ANA top config
625 23:12:37.625064 ===================================
626 23:12:37.625148 DLL_ASYNC_EN = 0
627 23:12:37.627927 ALL_SLAVE_EN = 1
628 23:12:37.631558 NEW_RANK_MODE = 1
629 23:12:37.635298 DLL_IDLE_MODE = 1
630 23:12:37.635384 LP45_APHY_COMB_EN = 1
631 23:12:37.638439 TX_ODT_DIS = 1
632 23:12:37.641578 NEW_8X_MODE = 1
633 23:12:37.645139 ===================================
634 23:12:37.648212 ===================================
635 23:12:37.651851 data_rate = 1600
636 23:12:37.655342 CKR = 1
637 23:12:37.658630 DQ_P2S_RATIO = 8
638 23:12:37.661160 ===================================
639 23:12:37.661248 CA_P2S_RATIO = 8
640 23:12:37.664669 DQ_CA_OPEN = 0
641 23:12:37.668358 DQ_SEMI_OPEN = 0
642 23:12:37.671034 CA_SEMI_OPEN = 0
643 23:12:37.674737 CA_FULL_RATE = 0
644 23:12:37.678183 DQ_CKDIV4_EN = 1
645 23:12:37.678268 CA_CKDIV4_EN = 1
646 23:12:37.680945 CA_PREDIV_EN = 0
647 23:12:37.685147 PH8_DLY = 0
648 23:12:37.687427 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
649 23:12:37.690914 DQ_AAMCK_DIV = 4
650 23:12:37.694145 CA_AAMCK_DIV = 4
651 23:12:37.694229 CA_ADMCK_DIV = 4
652 23:12:37.697779 DQ_TRACK_CA_EN = 0
653 23:12:37.701653 CA_PICK = 800
654 23:12:37.704240 CA_MCKIO = 800
655 23:12:37.707268 MCKIO_SEMI = 0
656 23:12:37.710621 PLL_FREQ = 3068
657 23:12:37.714058 DQ_UI_PI_RATIO = 32
658 23:12:37.714141 CA_UI_PI_RATIO = 0
659 23:12:37.717380 ===================================
660 23:12:37.721325 ===================================
661 23:12:37.724375 memory_type:LPDDR4
662 23:12:37.729046 GP_NUM : 10
663 23:12:37.729130 SRAM_EN : 1
664 23:12:37.730857 MD32_EN : 0
665 23:12:37.733863 ===================================
666 23:12:37.737321 [ANA_INIT] >>>>>>>>>>>>>>
667 23:12:37.740817 <<<<<< [CONFIGURE PHASE]: ANA_TX
668 23:12:37.744402 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
669 23:12:37.747610 ===================================
670 23:12:37.747734 data_rate = 1600,PCW = 0X7600
671 23:12:37.751517 ===================================
672 23:12:37.754199 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
673 23:12:37.761314 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 23:12:37.767229 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
675 23:12:37.770225 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
676 23:12:37.773697 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
677 23:12:37.776783 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
678 23:12:37.780497 [ANA_INIT] flow start
679 23:12:37.783576 [ANA_INIT] PLL >>>>>>>>
680 23:12:37.783660 [ANA_INIT] PLL <<<<<<<<
681 23:12:37.786602 [ANA_INIT] MIDPI >>>>>>>>
682 23:12:37.790514 [ANA_INIT] MIDPI <<<<<<<<
683 23:12:37.790598 [ANA_INIT] DLL >>>>>>>>
684 23:12:37.793555 [ANA_INIT] flow end
685 23:12:37.796508 ============ LP4 DIFF to SE enter ============
686 23:12:37.803471 ============ LP4 DIFF to SE exit ============
687 23:12:37.803557 [ANA_INIT] <<<<<<<<<<<<<
688 23:12:37.806901 [Flow] Enable top DCM control >>>>>
689 23:12:37.810132 [Flow] Enable top DCM control <<<<<
690 23:12:37.813455 Enable DLL master slave shuffle
691 23:12:37.819818 ==============================================================
692 23:12:37.819903 Gating Mode config
693 23:12:37.826535 ==============================================================
694 23:12:37.830058 Config description:
695 23:12:37.836634 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
696 23:12:37.843246 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
697 23:12:37.849814 SELPH_MODE 0: By rank 1: By Phase
698 23:12:37.856444 ==============================================================
699 23:12:37.856531 GAT_TRACK_EN = 1
700 23:12:37.859976 RX_GATING_MODE = 2
701 23:12:37.863415 RX_GATING_TRACK_MODE = 2
702 23:12:37.866781 SELPH_MODE = 1
703 23:12:37.870012 PICG_EARLY_EN = 1
704 23:12:37.872992 VALID_LAT_VALUE = 1
705 23:12:37.879687 ==============================================================
706 23:12:37.882910 Enter into Gating configuration >>>>
707 23:12:37.886766 Exit from Gating configuration <<<<
708 23:12:37.889562 Enter into DVFS_PRE_config >>>>>
709 23:12:37.899378 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
710 23:12:37.902585 Exit from DVFS_PRE_config <<<<<
711 23:12:37.906477 Enter into PICG configuration >>>>
712 23:12:37.909791 Exit from PICG configuration <<<<
713 23:12:37.913211 [RX_INPUT] configuration >>>>>
714 23:12:37.913296 [RX_INPUT] configuration <<<<<
715 23:12:37.919389 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
716 23:12:37.926290 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
717 23:12:37.929775 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
718 23:12:37.937137 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
719 23:12:37.944052 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
720 23:12:37.951069 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
721 23:12:37.954952 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
722 23:12:37.958546 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
723 23:12:37.961787 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
724 23:12:37.965937 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
725 23:12:37.969665 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
726 23:12:37.976448 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
727 23:12:37.976536 ===================================
728 23:12:37.980522 LPDDR4 DRAM CONFIGURATION
729 23:12:37.983937 ===================================
730 23:12:37.984022 EX_ROW_EN[0] = 0x0
731 23:12:37.986999 EX_ROW_EN[1] = 0x0
732 23:12:37.990727 LP4Y_EN = 0x0
733 23:12:37.990811 WORK_FSP = 0x0
734 23:12:37.994689 WL = 0x2
735 23:12:37.994773 RL = 0x2
736 23:12:37.994840 BL = 0x2
737 23:12:37.998213 RPST = 0x0
738 23:12:37.998297 RD_PRE = 0x0
739 23:12:38.001964 WR_PRE = 0x1
740 23:12:38.002048 WR_PST = 0x0
741 23:12:38.005944 DBI_WR = 0x0
742 23:12:38.006031 DBI_RD = 0x0
743 23:12:38.008908 OTF = 0x1
744 23:12:38.012792 ===================================
745 23:12:38.016994 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
746 23:12:38.020473 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
747 23:12:38.024266 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
748 23:12:38.027589 ===================================
749 23:12:38.030522 LPDDR4 DRAM CONFIGURATION
750 23:12:38.034179 ===================================
751 23:12:38.034264 EX_ROW_EN[0] = 0x10
752 23:12:38.038061 EX_ROW_EN[1] = 0x0
753 23:12:38.038146 LP4Y_EN = 0x0
754 23:12:38.042340 WORK_FSP = 0x0
755 23:12:38.042424 WL = 0x2
756 23:12:38.045793 RL = 0x2
757 23:12:38.045877 BL = 0x2
758 23:12:38.049457 RPST = 0x0
759 23:12:38.049558 RD_PRE = 0x0
760 23:12:38.049625 WR_PRE = 0x1
761 23:12:38.052836 WR_PST = 0x0
762 23:12:38.052921 DBI_WR = 0x0
763 23:12:38.056690 DBI_RD = 0x0
764 23:12:38.056774 OTF = 0x1
765 23:12:38.060100 ===================================
766 23:12:38.067233 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
767 23:12:38.071437 nWR fixed to 40
768 23:12:38.071524 [ModeRegInit_LP4] CH0 RK0
769 23:12:38.074967 [ModeRegInit_LP4] CH0 RK1
770 23:12:38.078841 [ModeRegInit_LP4] CH1 RK0
771 23:12:38.078931 [ModeRegInit_LP4] CH1 RK1
772 23:12:38.082466 match AC timing 13
773 23:12:38.086270 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
774 23:12:38.089707 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
775 23:12:38.096454 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
776 23:12:38.099730 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
777 23:12:38.103166 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
778 23:12:38.106530 [EMI DOE] emi_dcm 0
779 23:12:38.110539 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
780 23:12:38.110623 ==
781 23:12:38.113756 Dram Type= 6, Freq= 0, CH_0, rank 0
782 23:12:38.116587 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
783 23:12:38.116672 ==
784 23:12:38.123604 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
785 23:12:38.130062 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
786 23:12:38.138423 [CA 0] Center 37 (6~68) winsize 63
787 23:12:38.141832 [CA 1] Center 37 (7~67) winsize 61
788 23:12:38.144903 [CA 2] Center 34 (4~65) winsize 62
789 23:12:38.149050 [CA 3] Center 34 (4~65) winsize 62
790 23:12:38.152361 [CA 4] Center 33 (3~64) winsize 62
791 23:12:38.155506 [CA 5] Center 33 (3~64) winsize 62
792 23:12:38.155603
793 23:12:38.159081 [CmdBusTrainingLP45] Vref(ca) range 1: 30
794 23:12:38.159166
795 23:12:38.162316 [CATrainingPosCal] consider 1 rank data
796 23:12:38.165630 u2DelayCellTimex100 = 270/100 ps
797 23:12:38.169078 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
798 23:12:38.172011 CA1 delay=37 (7~67),Diff = 4 PI (28 cell)
799 23:12:38.175497 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
800 23:12:38.178826 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
801 23:12:38.185786 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
802 23:12:38.188911 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
803 23:12:38.188995
804 23:12:38.191957 CA PerBit enable=1, Macro0, CA PI delay=33
805 23:12:38.192043
806 23:12:38.195583 [CBTSetCACLKResult] CA Dly = 33
807 23:12:38.195668 CS Dly: 6 (0~37)
808 23:12:38.195806 ==
809 23:12:38.198624 Dram Type= 6, Freq= 0, CH_0, rank 1
810 23:12:38.205782 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
811 23:12:38.205868 ==
812 23:12:38.209550 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
813 23:12:38.215147 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
814 23:12:38.224695 [CA 0] Center 36 (6~67) winsize 62
815 23:12:38.228159 [CA 1] Center 37 (7~68) winsize 62
816 23:12:38.230899 [CA 2] Center 34 (4~65) winsize 62
817 23:12:38.234482 [CA 3] Center 34 (4~65) winsize 62
818 23:12:38.238297 [CA 4] Center 33 (3~64) winsize 62
819 23:12:38.242249 [CA 5] Center 33 (3~64) winsize 62
820 23:12:38.242333
821 23:12:38.244900 [CmdBusTrainingLP45] Vref(ca) range 1: 34
822 23:12:38.244984
823 23:12:38.247736 [CATrainingPosCal] consider 2 rank data
824 23:12:38.250956 u2DelayCellTimex100 = 270/100 ps
825 23:12:38.255158 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
826 23:12:38.258545 CA1 delay=37 (7~67),Diff = 4 PI (28 cell)
827 23:12:38.264608 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
828 23:12:38.268463 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
829 23:12:38.271512 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
830 23:12:38.275251 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
831 23:12:38.275335
832 23:12:38.278821 CA PerBit enable=1, Macro0, CA PI delay=33
833 23:12:38.278905
834 23:12:38.282759 [CBTSetCACLKResult] CA Dly = 33
835 23:12:38.282843 CS Dly: 7 (0~39)
836 23:12:38.282910
837 23:12:38.286096 ----->DramcWriteLeveling(PI) begin...
838 23:12:38.286187 ==
839 23:12:38.289596 Dram Type= 6, Freq= 0, CH_0, rank 0
840 23:12:38.294355 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
841 23:12:38.294441 ==
842 23:12:38.296429 Write leveling (Byte 0): 32 => 32
843 23:12:38.299598 Write leveling (Byte 1): 31 => 31
844 23:12:38.302989 DramcWriteLeveling(PI) end<-----
845 23:12:38.303073
846 23:12:38.303139 ==
847 23:12:38.306170 Dram Type= 6, Freq= 0, CH_0, rank 0
848 23:12:38.309786 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
849 23:12:38.309871 ==
850 23:12:38.313256 [Gating] SW mode calibration
851 23:12:38.319732 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
852 23:12:38.327118 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
853 23:12:38.329875 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
854 23:12:38.333425 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
855 23:12:38.339607 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
856 23:12:38.342885 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 23:12:38.346400 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 23:12:38.353190 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 23:12:38.356555 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 23:12:38.360119 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 23:12:38.367025 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 23:12:38.369280 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 23:12:38.372796 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 23:12:38.379347 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 23:12:38.383064 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 23:12:38.385958 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 23:12:38.392389 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 23:12:38.395639 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 23:12:38.399617 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 23:12:38.406643 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
871 23:12:38.409707 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
872 23:12:38.412145 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 23:12:38.419901 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 23:12:38.422340 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 23:12:38.425620 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 23:12:38.432159 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 23:12:38.435711 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 23:12:38.439403 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
879 23:12:38.445761 0 9 8 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
880 23:12:38.449012 0 9 12 | B1->B0 | 2d2d 3434 | 0 1 | (0 0) (1 1)
881 23:12:38.452064 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 23:12:38.458795 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 23:12:38.462008 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
884 23:12:38.465355 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
885 23:12:38.471832 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
886 23:12:38.475392 0 10 4 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
887 23:12:38.478801 0 10 8 | B1->B0 | 3333 2e2e | 1 0 | (1 1) (1 1)
888 23:12:38.484998 0 10 12 | B1->B0 | 2c2c 2323 | 0 0 | (1 1) (0 0)
889 23:12:38.489769 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 23:12:38.491988 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 23:12:38.499093 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
892 23:12:38.501867 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
893 23:12:38.504960 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
894 23:12:38.511958 0 11 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
895 23:12:38.515096 0 11 8 | B1->B0 | 2626 3737 | 0 0 | (0 0) (0 0)
896 23:12:38.518201 0 11 12 | B1->B0 | 3c3c 4646 | 1 0 | (0 0) (0 0)
897 23:12:38.524712 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 23:12:38.528430 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 23:12:38.531357 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
900 23:12:38.538053 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
901 23:12:38.541401 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
902 23:12:38.544832 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
903 23:12:38.551185 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
904 23:12:38.554851 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 23:12:38.558498 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 23:12:38.564331 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 23:12:38.567967 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 23:12:38.570863 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 23:12:38.578331 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 23:12:38.581029 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 23:12:38.584009 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 23:12:38.591228 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 23:12:38.594283 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 23:12:38.597460 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 23:12:38.603940 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
916 23:12:38.607528 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
917 23:12:38.610816 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
918 23:12:38.617918 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
919 23:12:38.620472 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
920 23:12:38.624121 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
921 23:12:38.628329 Total UI for P1: 0, mck2ui 16
922 23:12:38.630600 best dqsien dly found for B0: ( 0, 14, 8)
923 23:12:38.633776 Total UI for P1: 0, mck2ui 16
924 23:12:38.637327 best dqsien dly found for B1: ( 0, 14, 10)
925 23:12:38.641056 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
926 23:12:38.644408 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
927 23:12:38.644493
928 23:12:38.647104 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
929 23:12:38.653679 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
930 23:12:38.653764 [Gating] SW calibration Done
931 23:12:38.653830 ==
932 23:12:38.657433 Dram Type= 6, Freq= 0, CH_0, rank 0
933 23:12:38.661025 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 23:12:38.664735 ==
935 23:12:38.664820 RX Vref Scan: 0
936 23:12:38.664886
937 23:12:38.668185 RX Vref 0 -> 0, step: 1
938 23:12:38.668269
939 23:12:38.671189 RX Delay -130 -> 252, step: 16
940 23:12:38.674353 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
941 23:12:38.677627 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
942 23:12:38.681466 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
943 23:12:38.684569 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
944 23:12:38.688690 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
945 23:12:38.691908 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
946 23:12:38.699802 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
947 23:12:38.703592 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
948 23:12:38.706927 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
949 23:12:38.710539 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
950 23:12:38.714484 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
951 23:12:38.717932 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
952 23:12:38.721636 iDelay=222, Bit 12, Center 69 (-50 ~ 189) 240
953 23:12:38.725307 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
954 23:12:38.728904 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
955 23:12:38.735465 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
956 23:12:38.735549 ==
957 23:12:38.739313 Dram Type= 6, Freq= 0, CH_0, rank 0
958 23:12:38.742018 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
959 23:12:38.742101 ==
960 23:12:38.742167 DQS Delay:
961 23:12:38.745510 DQS0 = 0, DQS1 = 0
962 23:12:38.745592 DQM Delay:
963 23:12:38.748655 DQM0 = 86, DQM1 = 71
964 23:12:38.748737 DQ Delay:
965 23:12:38.752661 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
966 23:12:38.755554 DQ4 =85, DQ5 =69, DQ6 =101, DQ7 =93
967 23:12:38.758653 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
968 23:12:38.761868 DQ12 =69, DQ13 =77, DQ14 =85, DQ15 =77
969 23:12:38.761951
970 23:12:38.762020
971 23:12:38.762082 ==
972 23:12:38.765301 Dram Type= 6, Freq= 0, CH_0, rank 0
973 23:12:38.768756 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
974 23:12:38.768842 ==
975 23:12:38.768907
976 23:12:38.772944
977 23:12:38.773026 TX Vref Scan disable
978 23:12:38.774976 == TX Byte 0 ==
979 23:12:38.778745 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
980 23:12:38.782254 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
981 23:12:38.785156 == TX Byte 1 ==
982 23:12:38.789161 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
983 23:12:38.792417 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
984 23:12:38.792500 ==
985 23:12:38.795950 Dram Type= 6, Freq= 0, CH_0, rank 0
986 23:12:38.800439 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
987 23:12:38.800522 ==
988 23:12:38.814167 TX Vref=22, minBit 4, minWin=27, winSum=442
989 23:12:38.816898 TX Vref=24, minBit 5, minWin=27, winSum=442
990 23:12:38.820315 TX Vref=26, minBit 4, minWin=27, winSum=445
991 23:12:38.823618 TX Vref=28, minBit 0, minWin=28, winSum=450
992 23:12:38.827022 TX Vref=30, minBit 10, minWin=27, winSum=449
993 23:12:38.829954 TX Vref=32, minBit 4, minWin=27, winSum=446
994 23:12:38.836638 [TxChooseVref] Worse bit 0, Min win 28, Win sum 450, Final Vref 28
995 23:12:38.836722
996 23:12:38.840376 Final TX Range 1 Vref 28
997 23:12:38.840459
998 23:12:38.840523 ==
999 23:12:38.843446 Dram Type= 6, Freq= 0, CH_0, rank 0
1000 23:12:38.846899 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1001 23:12:38.846982 ==
1002 23:12:38.847048
1003 23:12:38.847106
1004 23:12:38.849902 TX Vref Scan disable
1005 23:12:38.853402 == TX Byte 0 ==
1006 23:12:38.857658 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1007 23:12:38.859867 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1008 23:12:38.863314 == TX Byte 1 ==
1009 23:12:38.866841 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1010 23:12:38.869749 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1011 23:12:38.873280
1012 23:12:38.873363 [DATLAT]
1013 23:12:38.873428 Freq=800, CH0 RK0
1014 23:12:38.873488
1015 23:12:38.876624 DATLAT Default: 0xa
1016 23:12:38.876706 0, 0xFFFF, sum = 0
1017 23:12:38.879938 1, 0xFFFF, sum = 0
1018 23:12:38.880025 2, 0xFFFF, sum = 0
1019 23:12:38.883381 3, 0xFFFF, sum = 0
1020 23:12:38.883464 4, 0xFFFF, sum = 0
1021 23:12:38.887227 5, 0xFFFF, sum = 0
1022 23:12:38.889716 6, 0xFFFF, sum = 0
1023 23:12:38.889799 7, 0xFFFF, sum = 0
1024 23:12:38.889865 8, 0x0, sum = 1
1025 23:12:38.893058 9, 0x0, sum = 2
1026 23:12:38.893140 10, 0x0, sum = 3
1027 23:12:38.896434 11, 0x0, sum = 4
1028 23:12:38.896516 best_step = 9
1029 23:12:38.896580
1030 23:12:38.896638 ==
1031 23:12:38.899628 Dram Type= 6, Freq= 0, CH_0, rank 0
1032 23:12:38.906952 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1033 23:12:38.907036 ==
1034 23:12:38.907100 RX Vref Scan: 1
1035 23:12:38.907158
1036 23:12:38.910055 Set Vref Range= 32 -> 127
1037 23:12:38.910135
1038 23:12:38.913996 RX Vref 32 -> 127, step: 1
1039 23:12:38.914077
1040 23:12:38.917127 RX Delay -111 -> 252, step: 8
1041 23:12:38.917208
1042 23:12:38.919457 Set Vref, RX VrefLevel [Byte0]: 32
1043 23:12:38.923189 [Byte1]: 32
1044 23:12:38.923270
1045 23:12:38.926283 Set Vref, RX VrefLevel [Byte0]: 33
1046 23:12:38.929995 [Byte1]: 33
1047 23:12:38.930075
1048 23:12:38.933358 Set Vref, RX VrefLevel [Byte0]: 34
1049 23:12:38.936472 [Byte1]: 34
1050 23:12:38.939531
1051 23:12:38.939611 Set Vref, RX VrefLevel [Byte0]: 35
1052 23:12:38.942711 [Byte1]: 35
1053 23:12:38.947401
1054 23:12:38.947482 Set Vref, RX VrefLevel [Byte0]: 36
1055 23:12:38.950838 [Byte1]: 36
1056 23:12:38.955117
1057 23:12:38.955197 Set Vref, RX VrefLevel [Byte0]: 37
1058 23:12:38.959027 [Byte1]: 37
1059 23:12:38.963041
1060 23:12:38.966751 Set Vref, RX VrefLevel [Byte0]: 38
1061 23:12:38.969268 [Byte1]: 38
1062 23:12:38.969349
1063 23:12:38.972142 Set Vref, RX VrefLevel [Byte0]: 39
1064 23:12:38.975445 [Byte1]: 39
1065 23:12:38.975526
1066 23:12:38.978910 Set Vref, RX VrefLevel [Byte0]: 40
1067 23:12:38.982122 [Byte1]: 40
1068 23:12:38.985705
1069 23:12:38.985786 Set Vref, RX VrefLevel [Byte0]: 41
1070 23:12:38.988962 [Byte1]: 41
1071 23:12:38.993218
1072 23:12:38.993298 Set Vref, RX VrefLevel [Byte0]: 42
1073 23:12:38.996152 [Byte1]: 42
1074 23:12:39.000773
1075 23:12:39.000853 Set Vref, RX VrefLevel [Byte0]: 43
1076 23:12:39.004058 [Byte1]: 43
1077 23:12:39.008200
1078 23:12:39.008327 Set Vref, RX VrefLevel [Byte0]: 44
1079 23:12:39.011581 [Byte1]: 44
1080 23:12:39.016490
1081 23:12:39.016571 Set Vref, RX VrefLevel [Byte0]: 45
1082 23:12:39.019518 [Byte1]: 45
1083 23:12:39.023906
1084 23:12:39.023988 Set Vref, RX VrefLevel [Byte0]: 46
1085 23:12:39.027279 [Byte1]: 46
1086 23:12:39.031316
1087 23:12:39.031396 Set Vref, RX VrefLevel [Byte0]: 47
1088 23:12:39.034655 [Byte1]: 47
1089 23:12:39.038831
1090 23:12:39.038912 Set Vref, RX VrefLevel [Byte0]: 48
1091 23:12:39.042049 [Byte1]: 48
1092 23:12:39.047072
1093 23:12:39.047152 Set Vref, RX VrefLevel [Byte0]: 49
1094 23:12:39.050172 [Byte1]: 49
1095 23:12:39.054335
1096 23:12:39.054416 Set Vref, RX VrefLevel [Byte0]: 50
1097 23:12:39.057458 [Byte1]: 50
1098 23:12:39.061840
1099 23:12:39.061922 Set Vref, RX VrefLevel [Byte0]: 51
1100 23:12:39.065213 [Byte1]: 51
1101 23:12:39.069408
1102 23:12:39.069489 Set Vref, RX VrefLevel [Byte0]: 52
1103 23:12:39.073080 [Byte1]: 52
1104 23:12:39.077405
1105 23:12:39.077486 Set Vref, RX VrefLevel [Byte0]: 53
1106 23:12:39.080403 [Byte1]: 53
1107 23:12:39.085121
1108 23:12:39.085205 Set Vref, RX VrefLevel [Byte0]: 54
1109 23:12:39.087979 [Byte1]: 54
1110 23:12:39.092528
1111 23:12:39.092609 Set Vref, RX VrefLevel [Byte0]: 55
1112 23:12:39.095657 [Byte1]: 55
1113 23:12:39.100926
1114 23:12:39.101007 Set Vref, RX VrefLevel [Byte0]: 56
1115 23:12:39.103081 [Byte1]: 56
1116 23:12:39.107930
1117 23:12:39.108011 Set Vref, RX VrefLevel [Byte0]: 57
1118 23:12:39.111279 [Byte1]: 57
1119 23:12:39.115230
1120 23:12:39.115310 Set Vref, RX VrefLevel [Byte0]: 58
1121 23:12:39.119422 [Byte1]: 58
1122 23:12:39.123581
1123 23:12:39.123660 Set Vref, RX VrefLevel [Byte0]: 59
1124 23:12:39.126292 [Byte1]: 59
1125 23:12:39.130723
1126 23:12:39.130804 Set Vref, RX VrefLevel [Byte0]: 60
1127 23:12:39.134116 [Byte1]: 60
1128 23:12:39.138061
1129 23:12:39.138142 Set Vref, RX VrefLevel [Byte0]: 61
1130 23:12:39.141688 [Byte1]: 61
1131 23:12:39.145853
1132 23:12:39.145934 Set Vref, RX VrefLevel [Byte0]: 62
1133 23:12:39.149103 [Byte1]: 62
1134 23:12:39.153863
1135 23:12:39.153944 Set Vref, RX VrefLevel [Byte0]: 63
1136 23:12:39.157996 [Byte1]: 63
1137 23:12:39.161715
1138 23:12:39.161797 Set Vref, RX VrefLevel [Byte0]: 64
1139 23:12:39.164827 [Byte1]: 64
1140 23:12:39.169430
1141 23:12:39.169511 Set Vref, RX VrefLevel [Byte0]: 65
1142 23:12:39.172545 [Byte1]: 65
1143 23:12:39.176573
1144 23:12:39.176654 Set Vref, RX VrefLevel [Byte0]: 66
1145 23:12:39.179919 [Byte1]: 66
1146 23:12:39.184320
1147 23:12:39.184399 Set Vref, RX VrefLevel [Byte0]: 67
1148 23:12:39.187351 [Byte1]: 67
1149 23:12:39.192340
1150 23:12:39.192420 Set Vref, RX VrefLevel [Byte0]: 68
1151 23:12:39.195297 [Byte1]: 68
1152 23:12:39.200071
1153 23:12:39.200151 Set Vref, RX VrefLevel [Byte0]: 69
1154 23:12:39.202785 [Byte1]: 69
1155 23:12:39.207508
1156 23:12:39.207589 Set Vref, RX VrefLevel [Byte0]: 70
1157 23:12:39.211260 [Byte1]: 70
1158 23:12:39.214792
1159 23:12:39.214874 Set Vref, RX VrefLevel [Byte0]: 71
1160 23:12:39.218410 [Byte1]: 71
1161 23:12:39.222436
1162 23:12:39.222516 Set Vref, RX VrefLevel [Byte0]: 72
1163 23:12:39.226058 [Byte1]: 72
1164 23:12:39.230461
1165 23:12:39.230541 Set Vref, RX VrefLevel [Byte0]: 73
1166 23:12:39.234127 [Byte1]: 73
1167 23:12:39.238088
1168 23:12:39.238169 Set Vref, RX VrefLevel [Byte0]: 74
1169 23:12:39.242893 [Byte1]: 74
1170 23:12:39.245225
1171 23:12:39.245309 Set Vref, RX VrefLevel [Byte0]: 75
1172 23:12:39.248693 [Byte1]: 75
1173 23:12:39.253021
1174 23:12:39.253103 Set Vref, RX VrefLevel [Byte0]: 76
1175 23:12:39.256941 [Byte1]: 76
1176 23:12:39.260567
1177 23:12:39.264057 Set Vref, RX VrefLevel [Byte0]: 77
1178 23:12:39.264139 [Byte1]: 77
1179 23:12:39.268989
1180 23:12:39.269071 Set Vref, RX VrefLevel [Byte0]: 78
1181 23:12:39.271855 [Byte1]: 78
1182 23:12:39.275972
1183 23:12:39.276053 Set Vref, RX VrefLevel [Byte0]: 79
1184 23:12:39.279483 [Byte1]: 79
1185 23:12:39.284170
1186 23:12:39.284251 Set Vref, RX VrefLevel [Byte0]: 80
1187 23:12:39.287926 [Byte1]: 80
1188 23:12:39.291659
1189 23:12:39.291777 Set Vref, RX VrefLevel [Byte0]: 81
1190 23:12:39.294810 [Byte1]: 81
1191 23:12:39.299115
1192 23:12:39.299196 Final RX Vref Byte 0 = 62 to rank0
1193 23:12:39.303443 Final RX Vref Byte 1 = 63 to rank0
1194 23:12:39.306568 Final RX Vref Byte 0 = 62 to rank1
1195 23:12:39.310174 Final RX Vref Byte 1 = 63 to rank1==
1196 23:12:39.313623 Dram Type= 6, Freq= 0, CH_0, rank 0
1197 23:12:39.317143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1198 23:12:39.317225 ==
1199 23:12:39.317291 DQS Delay:
1200 23:12:39.320774 DQS0 = 0, DQS1 = 0
1201 23:12:39.320856 DQM Delay:
1202 23:12:39.324570 DQM0 = 86, DQM1 = 76
1203 23:12:39.324650 DQ Delay:
1204 23:12:39.327996 DQ0 =84, DQ1 =88, DQ2 =84, DQ3 =84
1205 23:12:39.331765 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =96
1206 23:12:39.335317 DQ8 =68, DQ9 =64, DQ10 =76, DQ11 =72
1207 23:12:39.338784 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =80
1208 23:12:39.338864
1209 23:12:39.338928
1210 23:12:39.346238 [DQSOSCAuto] RK0, (LSB)MR18= 0x4627, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 392 ps
1211 23:12:39.349905 CH0 RK0: MR19=606, MR18=4627
1212 23:12:39.353349 CH0_RK0: MR19=0x606, MR18=0x4627, DQSOSC=392, MR23=63, INC=96, DEC=64
1213 23:12:39.353431
1214 23:12:39.357372 ----->DramcWriteLeveling(PI) begin...
1215 23:12:39.357455 ==
1216 23:12:39.361673 Dram Type= 6, Freq= 0, CH_0, rank 1
1217 23:12:39.364871 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1218 23:12:39.364953 ==
1219 23:12:39.368732 Write leveling (Byte 0): 31 => 31
1220 23:12:39.372555 Write leveling (Byte 1): 32 => 32
1221 23:12:39.375552 DramcWriteLeveling(PI) end<-----
1222 23:12:39.375634
1223 23:12:39.375738 ==
1224 23:12:39.379777 Dram Type= 6, Freq= 0, CH_0, rank 1
1225 23:12:39.384141 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1226 23:12:39.384258 ==
1227 23:12:39.427078 [Gating] SW mode calibration
1228 23:12:39.427506 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1229 23:12:39.428169 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1230 23:12:39.428581 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1231 23:12:39.428663 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1232 23:12:39.428913 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1233 23:12:39.429551 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 23:12:39.429818 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 23:12:39.430239 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 23:12:39.430320 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 23:12:39.471122 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 23:12:39.471515 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 23:12:39.471795 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1240 23:12:39.472167 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1241 23:12:39.472249 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 23:12:39.472499 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1243 23:12:39.473162 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 23:12:39.473531 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1245 23:12:39.473798 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1246 23:12:39.473869 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1247 23:12:39.515158 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1248 23:12:39.515920 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1249 23:12:39.516188 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1250 23:12:39.516267 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1251 23:12:39.516331 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1252 23:12:39.516711 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1253 23:12:39.517432 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1254 23:12:39.517988 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1255 23:12:39.518437 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1256 23:12:39.518520 0 9 8 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
1257 23:12:39.559189 0 9 12 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
1258 23:12:39.559475 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1259 23:12:39.559734 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1260 23:12:39.559986 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1261 23:12:39.560052 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1262 23:12:39.560500 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1263 23:12:39.560766 0 10 4 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 1)
1264 23:12:39.560845 0 10 8 | B1->B0 | 2f2f 2828 | 0 0 | (0 0) (0 0)
1265 23:12:39.561965 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1266 23:12:39.562047 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1267 23:12:39.569736 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1268 23:12:39.573388 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1269 23:12:39.576452 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1270 23:12:39.580022 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1271 23:12:39.584099 0 11 4 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
1272 23:12:39.587620 0 11 8 | B1->B0 | 2e2e 3737 | 0 1 | (0 0) (0 0)
1273 23:12:39.591015 0 11 12 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
1274 23:12:39.594916 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1275 23:12:39.598825 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1276 23:12:39.605736 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1277 23:12:39.609443 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1278 23:12:39.613722 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1279 23:12:39.616684 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1280 23:12:39.620249 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1281 23:12:39.628015 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1282 23:12:39.631313 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1283 23:12:39.635380 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1284 23:12:39.638853 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1285 23:12:39.642534 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1286 23:12:39.649321 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1287 23:12:39.652956 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1288 23:12:39.656687 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1289 23:12:39.663032 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1290 23:12:39.665946 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1291 23:12:39.669538 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1292 23:12:39.675890 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1293 23:12:39.679710 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1294 23:12:39.683218 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1295 23:12:39.689419 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1296 23:12:39.693037 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1297 23:12:39.695702 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1298 23:12:39.699751 Total UI for P1: 0, mck2ui 16
1299 23:12:39.702249 best dqsien dly found for B0: ( 0, 14, 8)
1300 23:12:39.706982 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1301 23:12:39.709243 Total UI for P1: 0, mck2ui 16
1302 23:12:39.712455 best dqsien dly found for B1: ( 0, 14, 12)
1303 23:12:39.716048 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1304 23:12:39.722398 best DQS1 dly(MCK, UI, PI) = (0, 14, 12)
1305 23:12:39.722480
1306 23:12:39.726071 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1307 23:12:39.729357 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 12)
1308 23:12:39.732483 [Gating] SW calibration Done
1309 23:12:39.732565 ==
1310 23:12:39.735613 Dram Type= 6, Freq= 0, CH_0, rank 1
1311 23:12:39.739158 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1312 23:12:39.739241 ==
1313 23:12:39.742819 RX Vref Scan: 0
1314 23:12:39.742902
1315 23:12:39.742965 RX Vref 0 -> 0, step: 1
1316 23:12:39.743024
1317 23:12:39.745636 RX Delay -130 -> 252, step: 16
1318 23:12:39.748632 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1319 23:12:39.755619 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1320 23:12:39.758610 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
1321 23:12:39.762550 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1322 23:12:39.765238 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1323 23:12:39.768676 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1324 23:12:39.775620 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1325 23:12:39.779291 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1326 23:12:39.781819 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1327 23:12:39.785671 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
1328 23:12:39.788449 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1329 23:12:39.795341 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1330 23:12:39.798476 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1331 23:12:39.802071 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1332 23:12:39.805191 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1333 23:12:39.808783 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1334 23:12:39.812300 ==
1335 23:12:39.815337 Dram Type= 6, Freq= 0, CH_0, rank 1
1336 23:12:39.818695 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1337 23:12:39.818777 ==
1338 23:12:39.818842 DQS Delay:
1339 23:12:39.821940 DQS0 = 0, DQS1 = 0
1340 23:12:39.822021 DQM Delay:
1341 23:12:39.825424 DQM0 = 83, DQM1 = 76
1342 23:12:39.825506 DQ Delay:
1343 23:12:39.828724 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =77
1344 23:12:39.831802 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
1345 23:12:39.835024 DQ8 =69, DQ9 =61, DQ10 =77, DQ11 =69
1346 23:12:39.838173 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
1347 23:12:39.838256
1348 23:12:39.838320
1349 23:12:39.838379 ==
1350 23:12:39.842356 Dram Type= 6, Freq= 0, CH_0, rank 1
1351 23:12:39.844815 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1352 23:12:39.844898 ==
1353 23:12:39.844962
1354 23:12:39.845021
1355 23:12:39.848075 TX Vref Scan disable
1356 23:12:39.851957 == TX Byte 0 ==
1357 23:12:39.854676 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1358 23:12:39.859005 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1359 23:12:39.861980 == TX Byte 1 ==
1360 23:12:39.864992 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1361 23:12:39.868346 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1362 23:12:39.868429 ==
1363 23:12:39.871838 Dram Type= 6, Freq= 0, CH_0, rank 1
1364 23:12:39.875097 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1365 23:12:39.878619 ==
1366 23:12:39.889681 TX Vref=22, minBit 4, minWin=27, winSum=446
1367 23:12:39.893161 TX Vref=24, minBit 2, minWin=28, winSum=451
1368 23:12:39.896273 TX Vref=26, minBit 8, minWin=27, winSum=444
1369 23:12:39.899367 TX Vref=28, minBit 9, minWin=27, winSum=446
1370 23:12:39.903046 TX Vref=30, minBit 9, minWin=27, winSum=448
1371 23:12:39.909491 TX Vref=32, minBit 9, minWin=27, winSum=443
1372 23:12:39.912899 [TxChooseVref] Worse bit 2, Min win 28, Win sum 451, Final Vref 24
1373 23:12:39.912974
1374 23:12:39.915873 Final TX Range 1 Vref 24
1375 23:12:39.915955
1376 23:12:39.916018 ==
1377 23:12:39.919163 Dram Type= 6, Freq= 0, CH_0, rank 1
1378 23:12:39.922441 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1379 23:12:39.926197 ==
1380 23:12:39.926278
1381 23:12:39.926342
1382 23:12:39.926401 TX Vref Scan disable
1383 23:12:39.929475 == TX Byte 0 ==
1384 23:12:39.932523 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1385 23:12:39.936100 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1386 23:12:39.939141 == TX Byte 1 ==
1387 23:12:39.942963 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1388 23:12:39.949627 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1389 23:12:39.949710
1390 23:12:39.949774 [DATLAT]
1391 23:12:39.949834 Freq=800, CH0 RK1
1392 23:12:39.949892
1393 23:12:39.952733 DATLAT Default: 0x9
1394 23:12:39.952814 0, 0xFFFF, sum = 0
1395 23:12:39.955963 1, 0xFFFF, sum = 0
1396 23:12:39.956046 2, 0xFFFF, sum = 0
1397 23:12:39.959305 3, 0xFFFF, sum = 0
1398 23:12:39.962824 4, 0xFFFF, sum = 0
1399 23:12:39.962907 5, 0xFFFF, sum = 0
1400 23:12:39.965693 6, 0xFFFF, sum = 0
1401 23:12:39.965775 7, 0xFFFF, sum = 0
1402 23:12:39.969330 8, 0xFFFF, sum = 0
1403 23:12:39.969441 9, 0x0, sum = 1
1404 23:12:39.969535 10, 0x0, sum = 2
1405 23:12:39.972954 11, 0x0, sum = 3
1406 23:12:39.973036 12, 0x0, sum = 4
1407 23:12:39.976117 best_step = 10
1408 23:12:39.976198
1409 23:12:39.976262 ==
1410 23:12:39.978852 Dram Type= 6, Freq= 0, CH_0, rank 1
1411 23:12:39.982084 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1412 23:12:39.982166 ==
1413 23:12:39.985637 RX Vref Scan: 0
1414 23:12:39.985719
1415 23:12:39.988922 RX Vref 0 -> 0, step: 1
1416 23:12:39.989003
1417 23:12:39.989066 RX Delay -95 -> 252, step: 8
1418 23:12:39.996403 iDelay=209, Bit 0, Center 80 (-31 ~ 192) 224
1419 23:12:40.000105 iDelay=209, Bit 1, Center 88 (-31 ~ 208) 240
1420 23:12:40.002393 iDelay=209, Bit 2, Center 80 (-31 ~ 192) 224
1421 23:12:40.006071 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1422 23:12:40.009246 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
1423 23:12:40.015662 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1424 23:12:40.019104 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1425 23:12:40.022337 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1426 23:12:40.025396 iDelay=209, Bit 8, Center 68 (-47 ~ 184) 232
1427 23:12:40.028781 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
1428 23:12:40.035316 iDelay=209, Bit 10, Center 76 (-39 ~ 192) 232
1429 23:12:40.039835 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
1430 23:12:40.042058 iDelay=209, Bit 12, Center 84 (-31 ~ 200) 232
1431 23:12:40.045549 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1432 23:12:40.052614 iDelay=209, Bit 14, Center 84 (-31 ~ 200) 232
1433 23:12:40.055268 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1434 23:12:40.055352 ==
1435 23:12:40.058901 Dram Type= 6, Freq= 0, CH_0, rank 1
1436 23:12:40.061837 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1437 23:12:40.061919 ==
1438 23:12:40.065646 DQS Delay:
1439 23:12:40.065729 DQS0 = 0, DQS1 = 0
1440 23:12:40.065792 DQM Delay:
1441 23:12:40.069190 DQM0 = 85, DQM1 = 76
1442 23:12:40.069271 DQ Delay:
1443 23:12:40.072584 DQ0 =80, DQ1 =88, DQ2 =80, DQ3 =84
1444 23:12:40.075134 DQ4 =84, DQ5 =76, DQ6 =92, DQ7 =96
1445 23:12:40.078812 DQ8 =68, DQ9 =64, DQ10 =76, DQ11 =68
1446 23:12:40.081826 DQ12 =84, DQ13 =80, DQ14 =84, DQ15 =84
1447 23:12:40.081908
1448 23:12:40.081971
1449 23:12:40.091863 [DQSOSCAuto] RK1, (LSB)MR18= 0x3f05, (MSB)MR19= 0x606, tDQSOscB0 = 408 ps tDQSOscB1 = 393 ps
1450 23:12:40.091986 CH0 RK1: MR19=606, MR18=3F05
1451 23:12:40.098302 CH0_RK1: MR19=0x606, MR18=0x3F05, DQSOSC=393, MR23=63, INC=95, DEC=63
1452 23:12:40.101562 [RxdqsGatingPostProcess] freq 800
1453 23:12:40.108680 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1454 23:12:40.111986 Pre-setting of DQS Precalculation
1455 23:12:40.115131 [DualRankRxdatlatCal] RK0: 9, RK1: 10, Final_Datlat 10
1456 23:12:40.115215 ==
1457 23:12:40.118358 Dram Type= 6, Freq= 0, CH_1, rank 0
1458 23:12:40.121983 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1459 23:12:40.125223 ==
1460 23:12:40.128484 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1461 23:12:40.135508 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1462 23:12:40.144074 [CA 0] Center 36 (6~67) winsize 62
1463 23:12:40.147354 [CA 1] Center 36 (6~67) winsize 62
1464 23:12:40.150710 [CA 2] Center 34 (4~65) winsize 62
1465 23:12:40.153938 [CA 3] Center 34 (3~65) winsize 63
1466 23:12:40.157175 [CA 4] Center 34 (4~65) winsize 62
1467 23:12:40.161121 [CA 5] Center 34 (3~65) winsize 63
1468 23:12:40.161212
1469 23:12:40.164479 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1470 23:12:40.164563
1471 23:12:40.167923 [CATrainingPosCal] consider 1 rank data
1472 23:12:40.170485 u2DelayCellTimex100 = 270/100 ps
1473 23:12:40.174002 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1474 23:12:40.177694 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1475 23:12:40.184072 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1476 23:12:40.187225 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1477 23:12:40.190886 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1478 23:12:40.193755 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1479 23:12:40.193841
1480 23:12:40.197914 CA PerBit enable=1, Macro0, CA PI delay=34
1481 23:12:40.198018
1482 23:12:40.200730 [CBTSetCACLKResult] CA Dly = 34
1483 23:12:40.200828 CS Dly: 4 (0~35)
1484 23:12:40.203623 ==
1485 23:12:40.203746 Dram Type= 6, Freq= 0, CH_1, rank 1
1486 23:12:40.211119 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1487 23:12:40.211247 ==
1488 23:12:40.213657 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1489 23:12:40.219976 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1490 23:12:40.230324 [CA 0] Center 36 (6~67) winsize 62
1491 23:12:40.233589 [CA 1] Center 36 (6~67) winsize 62
1492 23:12:40.237531 [CA 2] Center 34 (4~65) winsize 62
1493 23:12:40.240367 [CA 3] Center 34 (3~65) winsize 63
1494 23:12:40.243369 [CA 4] Center 34 (4~65) winsize 62
1495 23:12:40.246650 [CA 5] Center 34 (3~65) winsize 63
1496 23:12:40.246741
1497 23:12:40.249878 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1498 23:12:40.249965
1499 23:12:40.253422 [CATrainingPosCal] consider 2 rank data
1500 23:12:40.256843 u2DelayCellTimex100 = 270/100 ps
1501 23:12:40.259722 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1502 23:12:40.266748 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1503 23:12:40.270280 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1504 23:12:40.273023 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1505 23:12:40.276304 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1506 23:12:40.280030 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1507 23:12:40.280122
1508 23:12:40.283404 CA PerBit enable=1, Macro0, CA PI delay=34
1509 23:12:40.283489
1510 23:12:40.287151 [CBTSetCACLKResult] CA Dly = 34
1511 23:12:40.287236 CS Dly: 5 (0~38)
1512 23:12:40.290352
1513 23:12:40.293516 ----->DramcWriteLeveling(PI) begin...
1514 23:12:40.293603 ==
1515 23:12:40.296372 Dram Type= 6, Freq= 0, CH_1, rank 0
1516 23:12:40.300014 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1517 23:12:40.300100 ==
1518 23:12:40.303173 Write leveling (Byte 0): 29 => 29
1519 23:12:40.306158 Write leveling (Byte 1): 29 => 29
1520 23:12:40.310083 DramcWriteLeveling(PI) end<-----
1521 23:12:40.310170
1522 23:12:40.310234 ==
1523 23:12:40.312863 Dram Type= 6, Freq= 0, CH_1, rank 0
1524 23:12:40.316175 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1525 23:12:40.316260 ==
1526 23:12:40.319806 [Gating] SW mode calibration
1527 23:12:40.326219 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1528 23:12:40.333002 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1529 23:12:40.336454 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1530 23:12:40.339416 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1531 23:12:40.346375 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 23:12:40.350485 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 23:12:40.352829 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 23:12:40.360144 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 23:12:40.362844 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 23:12:40.366118 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 23:12:40.372451 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 23:12:40.375664 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 23:12:40.379112 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 23:12:40.385635 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 23:12:40.389059 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1542 23:12:40.392194 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1543 23:12:40.399239 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1544 23:12:40.402557 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1545 23:12:40.405933 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1546 23:12:40.412279 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1547 23:12:40.415805 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1548 23:12:40.418694 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1549 23:12:40.425893 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1550 23:12:40.428871 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1551 23:12:40.432122 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1552 23:12:40.435812 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1553 23:12:40.442298 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1554 23:12:40.445517 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1555 23:12:40.448602 0 9 8 | B1->B0 | 2c2c 3434 | 1 1 | (1 1) (1 1)
1556 23:12:40.455579 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1557 23:12:40.458618 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1558 23:12:40.462065 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1559 23:12:40.468618 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1560 23:12:40.471989 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1561 23:12:40.476019 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1562 23:12:40.481838 0 10 4 | B1->B0 | 3434 3434 | 0 1 | (0 1) (1 0)
1563 23:12:40.485049 0 10 8 | B1->B0 | 2e2e 2525 | 0 0 | (1 1) (0 0)
1564 23:12:40.488353 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1565 23:12:40.495378 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1566 23:12:40.498771 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1567 23:12:40.501722 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1568 23:12:40.508115 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1569 23:12:40.511817 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1570 23:12:40.516025 0 11 4 | B1->B0 | 2424 2424 | 0 1 | (0 0) (0 0)
1571 23:12:40.522000 0 11 8 | B1->B0 | 3939 4444 | 1 0 | (0 0) (0 0)
1572 23:12:40.525092 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1573 23:12:40.528287 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1574 23:12:40.535422 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1575 23:12:40.538354 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1576 23:12:40.541552 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1577 23:12:40.548416 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1578 23:12:40.551604 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1579 23:12:40.554773 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1580 23:12:40.561765 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1581 23:12:40.564923 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1582 23:12:40.568063 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1583 23:12:40.575135 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1584 23:12:40.578517 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1585 23:12:40.581702 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1586 23:12:40.588062 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1587 23:12:40.591590 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1588 23:12:40.594763 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1589 23:12:40.598051 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1590 23:12:40.605057 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1591 23:12:40.608530 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1592 23:12:40.611098 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1593 23:12:40.617799 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1594 23:12:40.621351 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1595 23:12:40.624537 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1596 23:12:40.628073 Total UI for P1: 0, mck2ui 16
1597 23:12:40.630948 best dqsien dly found for B0: ( 0, 14, 2)
1598 23:12:40.637898 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1599 23:12:40.641694 Total UI for P1: 0, mck2ui 16
1600 23:12:40.644802 best dqsien dly found for B1: ( 0, 14, 6)
1601 23:12:40.647458 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1602 23:12:40.650995 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1603 23:12:40.651076
1604 23:12:40.654088 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1605 23:12:40.657410 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1606 23:12:40.661533 [Gating] SW calibration Done
1607 23:12:40.661616 ==
1608 23:12:40.664489 Dram Type= 6, Freq= 0, CH_1, rank 0
1609 23:12:40.668111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1610 23:12:40.668194 ==
1611 23:12:40.671192 RX Vref Scan: 0
1612 23:12:40.671274
1613 23:12:40.671338 RX Vref 0 -> 0, step: 1
1614 23:12:40.674037
1615 23:12:40.674118 RX Delay -130 -> 252, step: 16
1616 23:12:40.681334 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1617 23:12:40.684056 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1618 23:12:40.687807 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1619 23:12:40.690622 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1620 23:12:40.693759 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1621 23:12:40.700824 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1622 23:12:40.703787 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1623 23:12:40.707212 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1624 23:12:40.710452 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1625 23:12:40.713840 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1626 23:12:40.720882 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1627 23:12:40.723679 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1628 23:12:40.727269 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1629 23:12:40.730360 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1630 23:12:40.737078 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1631 23:12:40.741055 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1632 23:12:40.741155 ==
1633 23:12:40.743391 Dram Type= 6, Freq= 0, CH_1, rank 0
1634 23:12:40.747031 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1635 23:12:40.747143 ==
1636 23:12:40.747234 DQS Delay:
1637 23:12:40.750224 DQS0 = 0, DQS1 = 0
1638 23:12:40.750331 DQM Delay:
1639 23:12:40.753735 DQM0 = 89, DQM1 = 79
1640 23:12:40.753816 DQ Delay:
1641 23:12:40.757020 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =85
1642 23:12:40.759830 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1643 23:12:40.763192 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1644 23:12:40.766604 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =93
1645 23:12:40.766685
1646 23:12:40.766749
1647 23:12:40.766807 ==
1648 23:12:40.769865 Dram Type= 6, Freq= 0, CH_1, rank 0
1649 23:12:40.776363 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1650 23:12:40.776470 ==
1651 23:12:40.776562
1652 23:12:40.776649
1653 23:12:40.776734 TX Vref Scan disable
1654 23:12:40.779987 == TX Byte 0 ==
1655 23:12:40.783814 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1656 23:12:40.789852 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1657 23:12:40.789961 == TX Byte 1 ==
1658 23:12:40.793834 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1659 23:12:40.800429 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1660 23:12:40.800511 ==
1661 23:12:40.803551 Dram Type= 6, Freq= 0, CH_1, rank 0
1662 23:12:40.806504 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1663 23:12:40.806585 ==
1664 23:12:40.819515 TX Vref=22, minBit 8, minWin=27, winSum=441
1665 23:12:40.822387 TX Vref=24, minBit 10, minWin=26, winSum=447
1666 23:12:40.825757 TX Vref=26, minBit 9, minWin=27, winSum=446
1667 23:12:40.829128 TX Vref=28, minBit 9, minWin=27, winSum=446
1668 23:12:40.832289 TX Vref=30, minBit 8, minWin=27, winSum=448
1669 23:12:40.839302 TX Vref=32, minBit 8, minWin=27, winSum=446
1670 23:12:40.842996 [TxChooseVref] Worse bit 8, Min win 27, Win sum 448, Final Vref 30
1671 23:12:40.843079
1672 23:12:40.846263 Final TX Range 1 Vref 30
1673 23:12:40.846345
1674 23:12:40.846408 ==
1675 23:12:40.848840 Dram Type= 6, Freq= 0, CH_1, rank 0
1676 23:12:40.852306 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1677 23:12:40.852388 ==
1678 23:12:40.855603
1679 23:12:40.855704
1680 23:12:40.855768 TX Vref Scan disable
1681 23:12:40.858952 == TX Byte 0 ==
1682 23:12:40.862717 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1683 23:12:40.869140 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1684 23:12:40.869221 == TX Byte 1 ==
1685 23:12:40.872431 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1686 23:12:40.879168 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1687 23:12:40.879249
1688 23:12:40.879313 [DATLAT]
1689 23:12:40.879372 Freq=800, CH1 RK0
1690 23:12:40.879430
1691 23:12:40.882630 DATLAT Default: 0xa
1692 23:12:40.882711 0, 0xFFFF, sum = 0
1693 23:12:40.885491 1, 0xFFFF, sum = 0
1694 23:12:40.888860 2, 0xFFFF, sum = 0
1695 23:12:40.888943 3, 0xFFFF, sum = 0
1696 23:12:40.892221 4, 0xFFFF, sum = 0
1697 23:12:40.892303 5, 0xFFFF, sum = 0
1698 23:12:40.895575 6, 0xFFFF, sum = 0
1699 23:12:40.895692 7, 0xFFFF, sum = 0
1700 23:12:40.898787 8, 0xFFFF, sum = 0
1701 23:12:40.898869 9, 0x0, sum = 1
1702 23:12:40.901993 10, 0x0, sum = 2
1703 23:12:40.902075 11, 0x0, sum = 3
1704 23:12:40.906835 12, 0x0, sum = 4
1705 23:12:40.906918 best_step = 10
1706 23:12:40.906981
1707 23:12:40.907039 ==
1708 23:12:40.909104 Dram Type= 6, Freq= 0, CH_1, rank 0
1709 23:12:40.911979 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1710 23:12:40.912060 ==
1711 23:12:40.915256 RX Vref Scan: 1
1712 23:12:40.915337
1713 23:12:40.918631 Set Vref Range= 32 -> 127
1714 23:12:40.918715
1715 23:12:40.918778 RX Vref 32 -> 127, step: 1
1716 23:12:40.918837
1717 23:12:40.922200 RX Delay -95 -> 252, step: 8
1718 23:12:40.922281
1719 23:12:40.925659 Set Vref, RX VrefLevel [Byte0]: 32
1720 23:12:40.928363 [Byte1]: 32
1721 23:12:40.931647
1722 23:12:40.931763 Set Vref, RX VrefLevel [Byte0]: 33
1723 23:12:40.935409 [Byte1]: 33
1724 23:12:40.939249
1725 23:12:40.939332 Set Vref, RX VrefLevel [Byte0]: 34
1726 23:12:40.942875 [Byte1]: 34
1727 23:12:40.946967
1728 23:12:40.947051 Set Vref, RX VrefLevel [Byte0]: 35
1729 23:12:40.950316 [Byte1]: 35
1730 23:12:40.954919
1731 23:12:40.955006 Set Vref, RX VrefLevel [Byte0]: 36
1732 23:12:40.958112 [Byte1]: 36
1733 23:12:40.962057
1734 23:12:40.962142 Set Vref, RX VrefLevel [Byte0]: 37
1735 23:12:40.965353 [Byte1]: 37
1736 23:12:40.969723
1737 23:12:40.969808 Set Vref, RX VrefLevel [Byte0]: 38
1738 23:12:40.973066 [Byte1]: 38
1739 23:12:40.978227
1740 23:12:40.978312 Set Vref, RX VrefLevel [Byte0]: 39
1741 23:12:40.980707 [Byte1]: 39
1742 23:12:40.985019
1743 23:12:40.985104 Set Vref, RX VrefLevel [Byte0]: 40
1744 23:12:40.988597 [Byte1]: 40
1745 23:12:40.992593
1746 23:12:40.992677 Set Vref, RX VrefLevel [Byte0]: 41
1747 23:12:40.995888 [Byte1]: 41
1748 23:12:41.000340
1749 23:12:41.000425 Set Vref, RX VrefLevel [Byte0]: 42
1750 23:12:41.004237 [Byte1]: 42
1751 23:12:41.007605
1752 23:12:41.007756 Set Vref, RX VrefLevel [Byte0]: 43
1753 23:12:41.011373 [Byte1]: 43
1754 23:12:41.015808
1755 23:12:41.015891 Set Vref, RX VrefLevel [Byte0]: 44
1756 23:12:41.018499 [Byte1]: 44
1757 23:12:41.023013
1758 23:12:41.023094 Set Vref, RX VrefLevel [Byte0]: 45
1759 23:12:41.026519 [Byte1]: 45
1760 23:12:41.030551
1761 23:12:41.030632 Set Vref, RX VrefLevel [Byte0]: 46
1762 23:12:41.034721 [Byte1]: 46
1763 23:12:41.038067
1764 23:12:41.038148 Set Vref, RX VrefLevel [Byte0]: 47
1765 23:12:41.041752 [Byte1]: 47
1766 23:12:41.045887
1767 23:12:41.045969 Set Vref, RX VrefLevel [Byte0]: 48
1768 23:12:41.049687 [Byte1]: 48
1769 23:12:41.053806
1770 23:12:41.053888 Set Vref, RX VrefLevel [Byte0]: 49
1771 23:12:41.056760 [Byte1]: 49
1772 23:12:41.060832
1773 23:12:41.060915 Set Vref, RX VrefLevel [Byte0]: 50
1774 23:12:41.064474 [Byte1]: 50
1775 23:12:41.068346
1776 23:12:41.068428 Set Vref, RX VrefLevel [Byte0]: 51
1777 23:12:41.072053 [Byte1]: 51
1778 23:12:41.076088
1779 23:12:41.076169 Set Vref, RX VrefLevel [Byte0]: 52
1780 23:12:41.079558 [Byte1]: 52
1781 23:12:41.083903
1782 23:12:41.083993 Set Vref, RX VrefLevel [Byte0]: 53
1783 23:12:41.087110 [Byte1]: 53
1784 23:12:41.091162
1785 23:12:41.091252 Set Vref, RX VrefLevel [Byte0]: 54
1786 23:12:41.094595 [Byte1]: 54
1787 23:12:41.098960
1788 23:12:41.099044 Set Vref, RX VrefLevel [Byte0]: 55
1789 23:12:41.102370 [Byte1]: 55
1790 23:12:41.106430
1791 23:12:41.106516 Set Vref, RX VrefLevel [Byte0]: 56
1792 23:12:41.109665 [Byte1]: 56
1793 23:12:41.114179
1794 23:12:41.114263 Set Vref, RX VrefLevel [Byte0]: 57
1795 23:12:41.117766 [Byte1]: 57
1796 23:12:41.121944
1797 23:12:41.122025 Set Vref, RX VrefLevel [Byte0]: 58
1798 23:12:41.125384 [Byte1]: 58
1799 23:12:41.129535
1800 23:12:41.129616 Set Vref, RX VrefLevel [Byte0]: 59
1801 23:12:41.132408 [Byte1]: 59
1802 23:12:41.137150
1803 23:12:41.137240 Set Vref, RX VrefLevel [Byte0]: 60
1804 23:12:41.140282 [Byte1]: 60
1805 23:12:41.144373
1806 23:12:41.144461 Set Vref, RX VrefLevel [Byte0]: 61
1807 23:12:41.147564 [Byte1]: 61
1808 23:12:41.152351
1809 23:12:41.152439 Set Vref, RX VrefLevel [Byte0]: 62
1810 23:12:41.155619 [Byte1]: 62
1811 23:12:41.159536
1812 23:12:41.159619 Set Vref, RX VrefLevel [Byte0]: 63
1813 23:12:41.163162 [Byte1]: 63
1814 23:12:41.167166
1815 23:12:41.167249 Set Vref, RX VrefLevel [Byte0]: 64
1816 23:12:41.170770 [Byte1]: 64
1817 23:12:41.175093
1818 23:12:41.175181 Set Vref, RX VrefLevel [Byte0]: 65
1819 23:12:41.178460 [Byte1]: 65
1820 23:12:41.182463
1821 23:12:41.182547 Set Vref, RX VrefLevel [Byte0]: 66
1822 23:12:41.186141 [Byte1]: 66
1823 23:12:41.190276
1824 23:12:41.190361 Set Vref, RX VrefLevel [Byte0]: 67
1825 23:12:41.193167 [Byte1]: 67
1826 23:12:41.197672
1827 23:12:41.197758 Set Vref, RX VrefLevel [Byte0]: 68
1828 23:12:41.201238 [Byte1]: 68
1829 23:12:41.205288
1830 23:12:41.205375 Set Vref, RX VrefLevel [Byte0]: 69
1831 23:12:41.208907 [Byte1]: 69
1832 23:12:41.212810
1833 23:12:41.212897 Set Vref, RX VrefLevel [Byte0]: 70
1834 23:12:41.216186 [Byte1]: 70
1835 23:12:41.220897
1836 23:12:41.220985 Set Vref, RX VrefLevel [Byte0]: 71
1837 23:12:41.224154 [Byte1]: 71
1838 23:12:41.228087
1839 23:12:41.228177 Set Vref, RX VrefLevel [Byte0]: 72
1840 23:12:41.231177 [Byte1]: 72
1841 23:12:41.235874
1842 23:12:41.235955 Set Vref, RX VrefLevel [Byte0]: 73
1843 23:12:41.239391 [Byte1]: 73
1844 23:12:41.243652
1845 23:12:41.243784 Set Vref, RX VrefLevel [Byte0]: 74
1846 23:12:41.246365 [Byte1]: 74
1847 23:12:41.250930
1848 23:12:41.251009 Set Vref, RX VrefLevel [Byte0]: 75
1849 23:12:41.253967 [Byte1]: 75
1850 23:12:41.258581
1851 23:12:41.258661 Set Vref, RX VrefLevel [Byte0]: 76
1852 23:12:41.261584 [Byte1]: 76
1853 23:12:41.266631
1854 23:12:41.266711 Final RX Vref Byte 0 = 57 to rank0
1855 23:12:41.269380 Final RX Vref Byte 1 = 62 to rank0
1856 23:12:41.272606 Final RX Vref Byte 0 = 57 to rank1
1857 23:12:41.276610 Final RX Vref Byte 1 = 62 to rank1==
1858 23:12:41.279306 Dram Type= 6, Freq= 0, CH_1, rank 0
1859 23:12:41.286099 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1860 23:12:41.286184 ==
1861 23:12:41.286272 DQS Delay:
1862 23:12:41.289075 DQS0 = 0, DQS1 = 0
1863 23:12:41.289155 DQM Delay:
1864 23:12:41.289217 DQM0 = 86, DQM1 = 78
1865 23:12:41.292277 DQ Delay:
1866 23:12:41.296157 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
1867 23:12:41.299359 DQ4 =80, DQ5 =100, DQ6 =100, DQ7 =80
1868 23:12:41.302790 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1869 23:12:41.305439 DQ12 =88, DQ13 =84, DQ14 =88, DQ15 =84
1870 23:12:41.305519
1871 23:12:41.305582
1872 23:12:41.312371 [DQSOSCAuto] RK0, (LSB)MR18= 0x331f, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 396 ps
1873 23:12:41.316529 CH1 RK0: MR19=606, MR18=331F
1874 23:12:41.323126 CH1_RK0: MR19=0x606, MR18=0x331F, DQSOSC=396, MR23=63, INC=94, DEC=62
1875 23:12:41.323218
1876 23:12:41.325834 ----->DramcWriteLeveling(PI) begin...
1877 23:12:41.325918 ==
1878 23:12:41.329502 Dram Type= 6, Freq= 0, CH_1, rank 1
1879 23:12:41.332289 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1880 23:12:41.332372 ==
1881 23:12:41.335798 Write leveling (Byte 0): 27 => 27
1882 23:12:41.339473 Write leveling (Byte 1): 27 => 27
1883 23:12:41.342082 DramcWriteLeveling(PI) end<-----
1884 23:12:41.342168
1885 23:12:41.342232 ==
1886 23:12:41.345794 Dram Type= 6, Freq= 0, CH_1, rank 1
1887 23:12:41.348883 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1888 23:12:41.348966 ==
1889 23:12:41.352047 [Gating] SW mode calibration
1890 23:12:41.359119 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1891 23:12:41.365409 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1892 23:12:41.368938 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1893 23:12:41.375589 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1894 23:12:41.378855 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1895 23:12:41.382782 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 23:12:41.388667 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1897 23:12:41.392645 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1898 23:12:41.395320 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1899 23:12:41.401974 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1900 23:12:41.404954 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1901 23:12:41.408669 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1902 23:12:41.415192 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1903 23:12:41.418166 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1904 23:12:41.421786 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1905 23:12:41.428167 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1906 23:12:41.431790 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1907 23:12:41.435004 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1908 23:12:41.441516 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1909 23:12:41.444509 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1910 23:12:41.448080 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 1)
1911 23:12:41.454874 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1912 23:12:41.457995 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1913 23:12:41.461572 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1914 23:12:41.464760 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1915 23:12:41.471434 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1916 23:12:41.474536 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1917 23:12:41.477963 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1918 23:12:41.485206 0 9 8 | B1->B0 | 3131 2626 | 0 0 | (0 0) (0 0)
1919 23:12:41.487614 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1920 23:12:41.491261 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1921 23:12:41.497566 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1922 23:12:41.501270 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1923 23:12:41.504357 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1924 23:12:41.511199 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1925 23:12:41.514812 0 10 4 | B1->B0 | 2f2f 3434 | 0 1 | (1 0) (1 0)
1926 23:12:41.518154 0 10 8 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (1 1)
1927 23:12:41.524123 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1928 23:12:41.527656 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1929 23:12:41.531480 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1930 23:12:41.537625 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1931 23:12:41.540783 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1932 23:12:41.544759 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1933 23:12:41.550620 0 11 4 | B1->B0 | 302f 2323 | 1 0 | (0 0) (0 0)
1934 23:12:41.554333 0 11 8 | B1->B0 | 4545 3535 | 0 0 | (0 0) (0 0)
1935 23:12:41.557466 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1936 23:12:41.564081 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1937 23:12:41.567582 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1938 23:12:41.570755 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1939 23:12:41.577278 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1940 23:12:41.581168 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1941 23:12:41.584119 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1942 23:12:41.590419 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1943 23:12:41.594573 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1944 23:12:41.597758 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1945 23:12:41.604071 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1946 23:12:41.606920 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1947 23:12:41.610735 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1948 23:12:41.617179 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1949 23:12:41.620599 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1950 23:12:41.624025 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1951 23:12:41.630204 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1952 23:12:41.634378 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1953 23:12:41.637244 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1954 23:12:41.643390 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1955 23:12:41.646992 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1956 23:12:41.650403 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1957 23:12:41.657364 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1958 23:12:41.657529 Total UI for P1: 0, mck2ui 16
1959 23:12:41.659931 best dqsien dly found for B1: ( 0, 14, 2)
1960 23:12:41.666907 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1961 23:12:41.670920 Total UI for P1: 0, mck2ui 16
1962 23:12:41.673980 best dqsien dly found for B0: ( 0, 14, 4)
1963 23:12:41.677319 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1964 23:12:41.680436 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1965 23:12:41.680557
1966 23:12:41.683590 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1967 23:12:41.687037 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1968 23:12:41.690450 [Gating] SW calibration Done
1969 23:12:41.690631 ==
1970 23:12:41.693398 Dram Type= 6, Freq= 0, CH_1, rank 1
1971 23:12:41.698678 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1972 23:12:41.698958 ==
1973 23:12:41.700909 RX Vref Scan: 0
1974 23:12:41.701115
1975 23:12:41.701273 RX Vref 0 -> 0, step: 1
1976 23:12:41.703777
1977 23:12:41.704105 RX Delay -130 -> 252, step: 16
1978 23:12:41.710593 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1979 23:12:41.713758 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1980 23:12:41.717215 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1981 23:12:41.720688 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1982 23:12:41.723998 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1983 23:12:41.731120 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1984 23:12:41.734858 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1985 23:12:41.736947 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1986 23:12:41.740325 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1987 23:12:41.744070 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1988 23:12:41.750276 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1989 23:12:41.754016 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1990 23:12:41.757072 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1991 23:12:41.761096 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1992 23:12:41.763718 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1993 23:12:41.770391 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1994 23:12:41.770848 ==
1995 23:12:41.773091 Dram Type= 6, Freq= 0, CH_1, rank 1
1996 23:12:41.777057 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1997 23:12:41.777521 ==
1998 23:12:41.777812 DQS Delay:
1999 23:12:41.779935 DQS0 = 0, DQS1 = 0
2000 23:12:41.780319 DQM Delay:
2001 23:12:41.783665 DQM0 = 88, DQM1 = 78
2002 23:12:41.784053 DQ Delay:
2003 23:12:41.787319 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =85
2004 23:12:41.790140 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
2005 23:12:41.794020 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
2006 23:12:41.796387 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
2007 23:12:41.796744
2008 23:12:41.797021
2009 23:12:41.797275 ==
2010 23:12:41.800693 Dram Type= 6, Freq= 0, CH_1, rank 1
2011 23:12:41.803577 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2012 23:12:41.807372 ==
2013 23:12:41.807892
2014 23:12:41.808202
2015 23:12:41.808481 TX Vref Scan disable
2016 23:12:41.810533 == TX Byte 0 ==
2017 23:12:41.813890 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2018 23:12:41.816993 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2019 23:12:41.820104 == TX Byte 1 ==
2020 23:12:41.823357 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
2021 23:12:41.826943 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
2022 23:12:41.829991 ==
2023 23:12:41.833130 Dram Type= 6, Freq= 0, CH_1, rank 1
2024 23:12:41.836108 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2025 23:12:41.836518 ==
2026 23:12:41.848686 TX Vref=22, minBit 1, minWin=27, winSum=443
2027 23:12:41.851981 TX Vref=24, minBit 8, minWin=27, winSum=445
2028 23:12:41.856014 TX Vref=26, minBit 13, minWin=27, winSum=451
2029 23:12:41.859497 TX Vref=28, minBit 13, minWin=27, winSum=450
2030 23:12:41.862774 TX Vref=30, minBit 8, minWin=27, winSum=448
2031 23:12:41.869482 TX Vref=32, minBit 6, minWin=27, winSum=450
2032 23:12:41.871971 [TxChooseVref] Worse bit 13, Min win 27, Win sum 451, Final Vref 26
2033 23:12:41.872449
2034 23:12:41.875574 Final TX Range 1 Vref 26
2035 23:12:41.876000
2036 23:12:41.876353 ==
2037 23:12:41.878641 Dram Type= 6, Freq= 0, CH_1, rank 1
2038 23:12:41.882128 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2039 23:12:41.885710 ==
2040 23:12:41.886220
2041 23:12:41.886663
2042 23:12:41.887075 TX Vref Scan disable
2043 23:12:41.889252 == TX Byte 0 ==
2044 23:12:41.892846 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2045 23:12:41.898624 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2046 23:12:41.899043 == TX Byte 1 ==
2047 23:12:41.902006 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
2048 23:12:41.908644 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
2049 23:12:41.908996
2050 23:12:41.909270 [DATLAT]
2051 23:12:41.909795 Freq=800, CH1 RK1
2052 23:12:41.910255
2053 23:12:41.912164 DATLAT Default: 0xa
2054 23:12:41.912518 0, 0xFFFF, sum = 0
2055 23:12:41.915484 1, 0xFFFF, sum = 0
2056 23:12:41.918841 2, 0xFFFF, sum = 0
2057 23:12:41.919196 3, 0xFFFF, sum = 0
2058 23:12:41.922245 4, 0xFFFF, sum = 0
2059 23:12:41.922703 5, 0xFFFF, sum = 0
2060 23:12:41.925789 6, 0xFFFF, sum = 0
2061 23:12:41.926147 7, 0xFFFF, sum = 0
2062 23:12:41.928633 8, 0xFFFF, sum = 0
2063 23:12:41.928990 9, 0x0, sum = 1
2064 23:12:41.932039 10, 0x0, sum = 2
2065 23:12:41.932498 11, 0x0, sum = 3
2066 23:12:41.932783 12, 0x0, sum = 4
2067 23:12:41.935733 best_step = 10
2068 23:12:41.936183
2069 23:12:41.936466 ==
2070 23:12:41.939291 Dram Type= 6, Freq= 0, CH_1, rank 1
2071 23:12:41.942275 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2072 23:12:41.942745 ==
2073 23:12:41.945433 RX Vref Scan: 0
2074 23:12:41.945784
2075 23:12:41.946062 RX Vref 0 -> 0, step: 1
2076 23:12:41.948608
2077 23:12:41.948958 RX Delay -95 -> 252, step: 8
2078 23:12:41.956514 iDelay=217, Bit 0, Center 92 (-23 ~ 208) 232
2079 23:12:41.959418 iDelay=217, Bit 1, Center 80 (-31 ~ 192) 224
2080 23:12:41.962255 iDelay=217, Bit 2, Center 76 (-39 ~ 192) 232
2081 23:12:41.965498 iDelay=217, Bit 3, Center 88 (-23 ~ 200) 224
2082 23:12:41.970095 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
2083 23:12:41.975847 iDelay=217, Bit 5, Center 96 (-15 ~ 208) 224
2084 23:12:41.978960 iDelay=217, Bit 6, Center 100 (-15 ~ 216) 232
2085 23:12:41.982516 iDelay=217, Bit 7, Center 84 (-31 ~ 200) 232
2086 23:12:41.986021 iDelay=217, Bit 8, Center 68 (-47 ~ 184) 232
2087 23:12:41.989277 iDelay=217, Bit 9, Center 68 (-47 ~ 184) 232
2088 23:12:41.996096 iDelay=217, Bit 10, Center 80 (-39 ~ 200) 240
2089 23:12:41.999252 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
2090 23:12:42.002447 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
2091 23:12:42.005507 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
2092 23:12:42.011780 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
2093 23:12:42.015245 iDelay=217, Bit 15, Center 88 (-31 ~ 208) 240
2094 23:12:42.015893 ==
2095 23:12:42.018772 Dram Type= 6, Freq= 0, CH_1, rank 1
2096 23:12:42.022050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2097 23:12:42.022537 ==
2098 23:12:42.025317 DQS Delay:
2099 23:12:42.025697 DQS0 = 0, DQS1 = 0
2100 23:12:42.025996 DQM Delay:
2101 23:12:42.028352 DQM0 = 87, DQM1 = 78
2102 23:12:42.028734 DQ Delay:
2103 23:12:42.031835 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =88
2104 23:12:42.035813 DQ4 =84, DQ5 =96, DQ6 =100, DQ7 =84
2105 23:12:42.038552 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
2106 23:12:42.041605 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =88
2107 23:12:42.041986
2108 23:12:42.042284
2109 23:12:42.051627 [DQSOSCAuto] RK1, (LSB)MR18= 0x170f, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 404 ps
2110 23:12:42.055332 CH1 RK1: MR19=606, MR18=170F
2111 23:12:42.058721 CH1_RK1: MR19=0x606, MR18=0x170F, DQSOSC=404, MR23=63, INC=90, DEC=60
2112 23:12:42.061761 [RxdqsGatingPostProcess] freq 800
2113 23:12:42.068846 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2114 23:12:42.072110 Pre-setting of DQS Precalculation
2115 23:12:42.075022 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2116 23:12:42.085087 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2117 23:12:42.091737 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2118 23:12:42.092266
2119 23:12:42.092596
2120 23:12:42.095332 [Calibration Summary] 1600 Mbps
2121 23:12:42.095890 CH 0, Rank 0
2122 23:12:42.098767 SW Impedance : PASS
2123 23:12:42.099281 DUTY Scan : NO K
2124 23:12:42.101843 ZQ Calibration : PASS
2125 23:12:42.105315 Jitter Meter : NO K
2126 23:12:42.105830 CBT Training : PASS
2127 23:12:42.109012 Write leveling : PASS
2128 23:12:42.111891 RX DQS gating : PASS
2129 23:12:42.112401 RX DQ/DQS(RDDQC) : PASS
2130 23:12:42.114872 TX DQ/DQS : PASS
2131 23:12:42.115390 RX DATLAT : PASS
2132 23:12:42.118304 RX DQ/DQS(Engine): PASS
2133 23:12:42.121879 TX OE : NO K
2134 23:12:42.122393 All Pass.
2135 23:12:42.122717
2136 23:12:42.123020 CH 0, Rank 1
2137 23:12:42.124855 SW Impedance : PASS
2138 23:12:42.128423 DUTY Scan : NO K
2139 23:12:42.128937 ZQ Calibration : PASS
2140 23:12:42.131201 Jitter Meter : NO K
2141 23:12:42.134477 CBT Training : PASS
2142 23:12:42.134896 Write leveling : PASS
2143 23:12:42.137743 RX DQS gating : PASS
2144 23:12:42.141191 RX DQ/DQS(RDDQC) : PASS
2145 23:12:42.141609 TX DQ/DQS : PASS
2146 23:12:42.145385 RX DATLAT : PASS
2147 23:12:42.148448 RX DQ/DQS(Engine): PASS
2148 23:12:42.148804 TX OE : NO K
2149 23:12:42.151426 All Pass.
2150 23:12:42.151841
2151 23:12:42.152146 CH 1, Rank 0
2152 23:12:42.155408 SW Impedance : PASS
2153 23:12:42.155928 DUTY Scan : NO K
2154 23:12:42.157622 ZQ Calibration : PASS
2155 23:12:42.161006 Jitter Meter : NO K
2156 23:12:42.161386 CBT Training : PASS
2157 23:12:42.164517 Write leveling : PASS
2158 23:12:42.167885 RX DQS gating : PASS
2159 23:12:42.168362 RX DQ/DQS(RDDQC) : PASS
2160 23:12:42.171143 TX DQ/DQS : PASS
2161 23:12:42.174845 RX DATLAT : PASS
2162 23:12:42.175329 RX DQ/DQS(Engine): PASS
2163 23:12:42.177908 TX OE : NO K
2164 23:12:42.178387 All Pass.
2165 23:12:42.178692
2166 23:12:42.180907 CH 1, Rank 1
2167 23:12:42.181287 SW Impedance : PASS
2168 23:12:42.184250 DUTY Scan : NO K
2169 23:12:42.184628 ZQ Calibration : PASS
2170 23:12:42.187992 Jitter Meter : NO K
2171 23:12:42.190954 CBT Training : PASS
2172 23:12:42.191331 Write leveling : PASS
2173 23:12:42.194849 RX DQS gating : PASS
2174 23:12:42.197848 RX DQ/DQS(RDDQC) : PASS
2175 23:12:42.198328 TX DQ/DQS : PASS
2176 23:12:42.201691 RX DATLAT : PASS
2177 23:12:42.205006 RX DQ/DQS(Engine): PASS
2178 23:12:42.205485 TX OE : NO K
2179 23:12:42.207624 All Pass.
2180 23:12:42.208141
2181 23:12:42.208445 DramC Write-DBI off
2182 23:12:42.210910 PER_BANK_REFRESH: Hybrid Mode
2183 23:12:42.211386 TX_TRACKING: ON
2184 23:12:42.214658 [GetDramInforAfterCalByMRR] Vendor 6.
2185 23:12:42.221049 [GetDramInforAfterCalByMRR] Revision 606.
2186 23:12:42.224462 [GetDramInforAfterCalByMRR] Revision 2 0.
2187 23:12:42.225068 MR0 0x3b3b
2188 23:12:42.225383 MR8 0x5151
2189 23:12:42.227307 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2190 23:12:42.230587
2191 23:12:42.231068 MR0 0x3b3b
2192 23:12:42.231488 MR8 0x5151
2193 23:12:42.233956 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2194 23:12:42.234334
2195 23:12:42.243818 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2196 23:12:42.247393 [FAST_K] Save calibration result to emmc
2197 23:12:42.250775 [FAST_K] Save calibration result to emmc
2198 23:12:42.253920 dram_init: config_dvfs: 1
2199 23:12:42.257585 dramc_set_vcore_voltage set vcore to 662500
2200 23:12:42.261175 Read voltage for 1200, 2
2201 23:12:42.261559 Vio18 = 0
2202 23:12:42.261890 Vcore = 662500
2203 23:12:42.264370 Vdram = 0
2204 23:12:42.264747 Vddq = 0
2205 23:12:42.265047 Vmddr = 0
2206 23:12:42.270653 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2207 23:12:42.274104 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2208 23:12:42.277756 MEM_TYPE=3, freq_sel=15
2209 23:12:42.280708 sv_algorithm_assistance_LP4_1600
2210 23:12:42.283616 ============ PULL DRAM RESETB DOWN ============
2211 23:12:42.286878 ========== PULL DRAM RESETB DOWN end =========
2212 23:12:42.293562 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2213 23:12:42.296713 ===================================
2214 23:12:42.301100 LPDDR4 DRAM CONFIGURATION
2215 23:12:42.304069 ===================================
2216 23:12:42.304583 EX_ROW_EN[0] = 0x0
2217 23:12:42.307305 EX_ROW_EN[1] = 0x0
2218 23:12:42.307861 LP4Y_EN = 0x0
2219 23:12:42.310485 WORK_FSP = 0x0
2220 23:12:42.310998 WL = 0x4
2221 23:12:42.313532 RL = 0x4
2222 23:12:42.314047 BL = 0x2
2223 23:12:42.317135 RPST = 0x0
2224 23:12:42.317647 RD_PRE = 0x0
2225 23:12:42.320757 WR_PRE = 0x1
2226 23:12:42.321289 WR_PST = 0x0
2227 23:12:42.324592 DBI_WR = 0x0
2228 23:12:42.325292 DBI_RD = 0x0
2229 23:12:42.326483 OTF = 0x1
2230 23:12:42.329622 ===================================
2231 23:12:42.333685 ===================================
2232 23:12:42.334101 ANA top config
2233 23:12:42.336826 ===================================
2234 23:12:42.339980 DLL_ASYNC_EN = 0
2235 23:12:42.342892 ALL_SLAVE_EN = 0
2236 23:12:42.346351 NEW_RANK_MODE = 1
2237 23:12:42.346768 DLL_IDLE_MODE = 1
2238 23:12:42.350388 LP45_APHY_COMB_EN = 1
2239 23:12:42.353091 TX_ODT_DIS = 1
2240 23:12:42.357323 NEW_8X_MODE = 1
2241 23:12:42.359732 ===================================
2242 23:12:42.363567 ===================================
2243 23:12:42.366413 data_rate = 2400
2244 23:12:42.369510 CKR = 1
2245 23:12:42.369924 DQ_P2S_RATIO = 8
2246 23:12:42.372900 ===================================
2247 23:12:42.376971 CA_P2S_RATIO = 8
2248 23:12:42.379722 DQ_CA_OPEN = 0
2249 23:12:42.382699 DQ_SEMI_OPEN = 0
2250 23:12:42.386197 CA_SEMI_OPEN = 0
2251 23:12:42.389406 CA_FULL_RATE = 0
2252 23:12:42.389833 DQ_CKDIV4_EN = 0
2253 23:12:42.393061 CA_CKDIV4_EN = 0
2254 23:12:42.396648 CA_PREDIV_EN = 0
2255 23:12:42.400146 PH8_DLY = 17
2256 23:12:42.403693 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2257 23:12:42.406429 DQ_AAMCK_DIV = 4
2258 23:12:42.406931 CA_AAMCK_DIV = 4
2259 23:12:42.409844 CA_ADMCK_DIV = 4
2260 23:12:42.413925 DQ_TRACK_CA_EN = 0
2261 23:12:42.416209 CA_PICK = 1200
2262 23:12:42.419936 CA_MCKIO = 1200
2263 23:12:42.422845 MCKIO_SEMI = 0
2264 23:12:42.426129 PLL_FREQ = 2366
2265 23:12:42.426542 DQ_UI_PI_RATIO = 32
2266 23:12:42.429886 CA_UI_PI_RATIO = 0
2267 23:12:42.432714 ===================================
2268 23:12:42.436116 ===================================
2269 23:12:42.439334 memory_type:LPDDR4
2270 23:12:42.442433 GP_NUM : 10
2271 23:12:42.442514 SRAM_EN : 1
2272 23:12:42.445651 MD32_EN : 0
2273 23:12:42.450090 ===================================
2274 23:12:42.452506 [ANA_INIT] >>>>>>>>>>>>>>
2275 23:12:42.452919 <<<<<< [CONFIGURE PHASE]: ANA_TX
2276 23:12:42.456107 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2277 23:12:42.459365 ===================================
2278 23:12:42.462396 data_rate = 2400,PCW = 0X5b00
2279 23:12:42.466267 ===================================
2280 23:12:42.468864 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2281 23:12:42.475753 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2282 23:12:42.482179 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2283 23:12:42.486525 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2284 23:12:42.489548 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2285 23:12:42.491920 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2286 23:12:42.495956 [ANA_INIT] flow start
2287 23:12:42.496182 [ANA_INIT] PLL >>>>>>>>
2288 23:12:42.499426 [ANA_INIT] PLL <<<<<<<<
2289 23:12:42.502077 [ANA_INIT] MIDPI >>>>>>>>
2290 23:12:42.502281 [ANA_INIT] MIDPI <<<<<<<<
2291 23:12:42.505604 [ANA_INIT] DLL >>>>>>>>
2292 23:12:42.508821 [ANA_INIT] DLL <<<<<<<<
2293 23:12:42.509039 [ANA_INIT] flow end
2294 23:12:42.515383 ============ LP4 DIFF to SE enter ============
2295 23:12:42.519280 ============ LP4 DIFF to SE exit ============
2296 23:12:42.522147 [ANA_INIT] <<<<<<<<<<<<<
2297 23:12:42.525535 [Flow] Enable top DCM control >>>>>
2298 23:12:42.529333 [Flow] Enable top DCM control <<<<<
2299 23:12:42.529413 Enable DLL master slave shuffle
2300 23:12:42.535542 ==============================================================
2301 23:12:42.538594 Gating Mode config
2302 23:12:42.541533 ==============================================================
2303 23:12:42.545275 Config description:
2304 23:12:42.555041 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2305 23:12:42.561951 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2306 23:12:42.565755 SELPH_MODE 0: By rank 1: By Phase
2307 23:12:42.572164 ==============================================================
2308 23:12:42.575419 GAT_TRACK_EN = 1
2309 23:12:42.578872 RX_GATING_MODE = 2
2310 23:12:42.581880 RX_GATING_TRACK_MODE = 2
2311 23:12:42.585098 SELPH_MODE = 1
2312 23:12:42.588972 PICG_EARLY_EN = 1
2313 23:12:42.589141 VALID_LAT_VALUE = 1
2314 23:12:42.595140 ==============================================================
2315 23:12:42.599070 Enter into Gating configuration >>>>
2316 23:12:42.601709 Exit from Gating configuration <<<<
2317 23:12:42.604808 Enter into DVFS_PRE_config >>>>>
2318 23:12:42.615216 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2319 23:12:42.617873 Exit from DVFS_PRE_config <<<<<
2320 23:12:42.621357 Enter into PICG configuration >>>>
2321 23:12:42.625201 Exit from PICG configuration <<<<
2322 23:12:42.628132 [RX_INPUT] configuration >>>>>
2323 23:12:42.632363 [RX_INPUT] configuration <<<<<
2324 23:12:42.634627 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2325 23:12:42.641674 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2326 23:12:42.647841 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2327 23:12:42.654881 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2328 23:12:42.661465 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2329 23:12:42.668054 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2330 23:12:42.671220 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2331 23:12:42.674968 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2332 23:12:42.678422 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2333 23:12:42.681260 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2334 23:12:42.688487 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2335 23:12:42.692270 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2336 23:12:42.695206 ===================================
2337 23:12:42.698532 LPDDR4 DRAM CONFIGURATION
2338 23:12:42.701782 ===================================
2339 23:12:42.702314 EX_ROW_EN[0] = 0x0
2340 23:12:42.705010 EX_ROW_EN[1] = 0x0
2341 23:12:42.705443 LP4Y_EN = 0x0
2342 23:12:42.708499 WORK_FSP = 0x0
2343 23:12:42.708928 WL = 0x4
2344 23:12:42.712357 RL = 0x4
2345 23:12:42.714943 BL = 0x2
2346 23:12:42.715578 RPST = 0x0
2347 23:12:42.717571 RD_PRE = 0x0
2348 23:12:42.717924 WR_PRE = 0x1
2349 23:12:42.721547 WR_PST = 0x0
2350 23:12:42.722055 DBI_WR = 0x0
2351 23:12:42.724387 DBI_RD = 0x0
2352 23:12:42.724813 OTF = 0x1
2353 23:12:42.727824 ===================================
2354 23:12:42.731272 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2355 23:12:42.738202 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2356 23:12:42.741690 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2357 23:12:42.744173 ===================================
2358 23:12:42.747410 LPDDR4 DRAM CONFIGURATION
2359 23:12:42.750846 ===================================
2360 23:12:42.751431 EX_ROW_EN[0] = 0x10
2361 23:12:42.753974 EX_ROW_EN[1] = 0x0
2362 23:12:42.754477 LP4Y_EN = 0x0
2363 23:12:42.757681 WORK_FSP = 0x0
2364 23:12:42.758176 WL = 0x4
2365 23:12:42.761383 RL = 0x4
2366 23:12:42.761964 BL = 0x2
2367 23:12:42.764157 RPST = 0x0
2368 23:12:42.764707 RD_PRE = 0x0
2369 23:12:42.767612 WR_PRE = 0x1
2370 23:12:42.770882 WR_PST = 0x0
2371 23:12:42.771256 DBI_WR = 0x0
2372 23:12:42.774009 DBI_RD = 0x0
2373 23:12:42.774294 OTF = 0x1
2374 23:12:42.777691 ===================================
2375 23:12:42.783881 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2376 23:12:42.784031 ==
2377 23:12:42.787176 Dram Type= 6, Freq= 0, CH_0, rank 0
2378 23:12:42.790163 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2379 23:12:42.790292 ==
2380 23:12:42.793696 [Duty_Offset_Calibration]
2381 23:12:42.797351 B0:1 B1:-1 CA:0
2382 23:12:42.797531
2383 23:12:42.800287 [DutyScan_Calibration_Flow] k_type=0
2384 23:12:42.808388
2385 23:12:42.808576 ==CLK 0==
2386 23:12:42.812348 Final CLK duty delay cell = 0
2387 23:12:42.814608 [0] MAX Duty = 5125%(X100), DQS PI = 24
2388 23:12:42.817990 [0] MIN Duty = 4907%(X100), DQS PI = 6
2389 23:12:42.818070 [0] AVG Duty = 5016%(X100)
2390 23:12:42.821170
2391 23:12:42.825532 CH0 CLK Duty spec in!! Max-Min= 218%
2392 23:12:42.828471 [DutyScan_Calibration_Flow] ====Done====
2393 23:12:42.828913
2394 23:12:42.832775 [DutyScan_Calibration_Flow] k_type=1
2395 23:12:42.847039
2396 23:12:42.847536 ==DQS 0 ==
2397 23:12:42.850534 Final DQS duty delay cell = -4
2398 23:12:42.853893 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2399 23:12:42.856976 [-4] MIN Duty = 4875%(X100), DQS PI = 56
2400 23:12:42.860173 [-4] AVG Duty = 4968%(X100)
2401 23:12:42.860620
2402 23:12:42.860964 ==DQS 1 ==
2403 23:12:42.863604 Final DQS duty delay cell = 0
2404 23:12:42.868601 [0] MAX Duty = 5124%(X100), DQS PI = 4
2405 23:12:42.869847 [0] MIN Duty = 5000%(X100), DQS PI = 24
2406 23:12:42.873010 [0] AVG Duty = 5062%(X100)
2407 23:12:42.873344
2408 23:12:42.876210 CH0 DQS 0 Duty spec in!! Max-Min= 187%
2409 23:12:42.876521
2410 23:12:42.879775 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2411 23:12:42.883235 [DutyScan_Calibration_Flow] ====Done====
2412 23:12:42.883411
2413 23:12:42.886614 [DutyScan_Calibration_Flow] k_type=3
2414 23:12:42.904573
2415 23:12:42.904657 ==DQM 0 ==
2416 23:12:42.907857 Final DQM duty delay cell = 0
2417 23:12:42.911777 [0] MAX Duty = 5062%(X100), DQS PI = 18
2418 23:12:42.914648 [0] MIN Duty = 4875%(X100), DQS PI = 6
2419 23:12:42.914728 [0] AVG Duty = 4968%(X100)
2420 23:12:42.917794
2421 23:12:42.917879 ==DQM 1 ==
2422 23:12:42.921653 Final DQM duty delay cell = 4
2423 23:12:42.924853 [4] MAX Duty = 5187%(X100), DQS PI = 14
2424 23:12:42.927944 [4] MIN Duty = 5000%(X100), DQS PI = 24
2425 23:12:42.928320 [4] AVG Duty = 5093%(X100)
2426 23:12:42.931155
2427 23:12:42.935801 CH0 DQM 0 Duty spec in!! Max-Min= 187%
2428 23:12:42.936178
2429 23:12:42.937876 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2430 23:12:42.941205 [DutyScan_Calibration_Flow] ====Done====
2431 23:12:42.941583
2432 23:12:42.945630 [DutyScan_Calibration_Flow] k_type=2
2433 23:12:42.959203
2434 23:12:42.959517 ==DQ 0 ==
2435 23:12:42.962475 Final DQ duty delay cell = -4
2436 23:12:42.966334 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2437 23:12:42.969164 [-4] MIN Duty = 4907%(X100), DQS PI = 46
2438 23:12:42.972915 [-4] AVG Duty = 4969%(X100)
2439 23:12:42.973058
2440 23:12:42.973170 ==DQ 1 ==
2441 23:12:42.976683 Final DQ duty delay cell = -4
2442 23:12:42.979150 [-4] MAX Duty = 5000%(X100), DQS PI = 54
2443 23:12:42.982328 [-4] MIN Duty = 4876%(X100), DQS PI = 16
2444 23:12:42.985625 [-4] AVG Duty = 4938%(X100)
2445 23:12:42.985768
2446 23:12:42.989411 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2447 23:12:42.989569
2448 23:12:42.992178 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2449 23:12:42.995697 [DutyScan_Calibration_Flow] ====Done====
2450 23:12:42.995826 ==
2451 23:12:42.999695 Dram Type= 6, Freq= 0, CH_1, rank 0
2452 23:12:43.002345 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2453 23:12:43.002487 ==
2454 23:12:43.006224 [Duty_Offset_Calibration]
2455 23:12:43.009046 B0:-1 B1:1 CA:2
2456 23:12:43.009191
2457 23:12:43.011800 [DutyScan_Calibration_Flow] k_type=0
2458 23:12:43.019968
2459 23:12:43.020254 ==CLK 0==
2460 23:12:43.023567 Final CLK duty delay cell = 0
2461 23:12:43.027275 [0] MAX Duty = 5156%(X100), DQS PI = 22
2462 23:12:43.030552 [0] MIN Duty = 4969%(X100), DQS PI = 62
2463 23:12:43.030771 [0] AVG Duty = 5062%(X100)
2464 23:12:43.033738
2465 23:12:43.036614 CH1 CLK Duty spec in!! Max-Min= 187%
2466 23:12:43.041100 [DutyScan_Calibration_Flow] ====Done====
2467 23:12:43.041468
2468 23:12:43.043690 [DutyScan_Calibration_Flow] k_type=1
2469 23:12:43.059592
2470 23:12:43.059981 ==DQS 0 ==
2471 23:12:43.062611 Final DQS duty delay cell = 0
2472 23:12:43.066460 [0] MAX Duty = 5156%(X100), DQS PI = 48
2473 23:12:43.069110 [0] MIN Duty = 4907%(X100), DQS PI = 6
2474 23:12:43.069401 [0] AVG Duty = 5031%(X100)
2475 23:12:43.072785
2476 23:12:43.073054 ==DQS 1 ==
2477 23:12:43.075892 Final DQS duty delay cell = 0
2478 23:12:43.079493 [0] MAX Duty = 5094%(X100), DQS PI = 10
2479 23:12:43.082576 [0] MIN Duty = 4969%(X100), DQS PI = 58
2480 23:12:43.086128 [0] AVG Duty = 5031%(X100)
2481 23:12:43.086401
2482 23:12:43.089078 CH1 DQS 0 Duty spec in!! Max-Min= 249%
2483 23:12:43.089351
2484 23:12:43.092335 CH1 DQS 1 Duty spec in!! Max-Min= 125%
2485 23:12:43.095828 [DutyScan_Calibration_Flow] ====Done====
2486 23:12:43.096102
2487 23:12:43.099129 [DutyScan_Calibration_Flow] k_type=3
2488 23:12:43.115317
2489 23:12:43.115398 ==DQM 0 ==
2490 23:12:43.118568 Final DQM duty delay cell = -4
2491 23:12:43.121626 [-4] MAX Duty = 5062%(X100), DQS PI = 36
2492 23:12:43.124975 [-4] MIN Duty = 4876%(X100), DQS PI = 6
2493 23:12:43.128540 [-4] AVG Duty = 4969%(X100)
2494 23:12:43.128919
2495 23:12:43.129221 ==DQM 1 ==
2496 23:12:43.132264 Final DQM duty delay cell = 0
2497 23:12:43.135489 [0] MAX Duty = 5187%(X100), DQS PI = 6
2498 23:12:43.138120 [0] MIN Duty = 5000%(X100), DQS PI = 28
2499 23:12:43.141412 [0] AVG Duty = 5093%(X100)
2500 23:12:43.141793
2501 23:12:43.145242 CH1 DQM 0 Duty spec in!! Max-Min= 186%
2502 23:12:43.145624
2503 23:12:43.148446 CH1 DQM 1 Duty spec in!! Max-Min= 187%
2504 23:12:43.151534 [DutyScan_Calibration_Flow] ====Done====
2505 23:12:43.152003
2506 23:12:43.154861 [DutyScan_Calibration_Flow] k_type=2
2507 23:12:43.171535
2508 23:12:43.171763 ==DQ 0 ==
2509 23:12:43.175352 Final DQ duty delay cell = 0
2510 23:12:43.178475 [0] MAX Duty = 5187%(X100), DQS PI = 32
2511 23:12:43.182023 [0] MIN Duty = 4907%(X100), DQS PI = 6
2512 23:12:43.182189 [0] AVG Duty = 5047%(X100)
2513 23:12:43.184892
2514 23:12:43.185050 ==DQ 1 ==
2515 23:12:43.188224 Final DQ duty delay cell = 0
2516 23:12:43.191611 [0] MAX Duty = 5124%(X100), DQS PI = 10
2517 23:12:43.194640 [0] MIN Duty = 4969%(X100), DQS PI = 58
2518 23:12:43.194785 [0] AVG Duty = 5046%(X100)
2519 23:12:43.194898
2520 23:12:43.198167 CH1 DQ 0 Duty spec in!! Max-Min= 280%
2521 23:12:43.202463
2522 23:12:43.204734 CH1 DQ 1 Duty spec in!! Max-Min= 155%
2523 23:12:43.208005 [DutyScan_Calibration_Flow] ====Done====
2524 23:12:43.211645 nWR fixed to 30
2525 23:12:43.211816 [ModeRegInit_LP4] CH0 RK0
2526 23:12:43.214827 [ModeRegInit_LP4] CH0 RK1
2527 23:12:43.217880 [ModeRegInit_LP4] CH1 RK0
2528 23:12:43.221168 [ModeRegInit_LP4] CH1 RK1
2529 23:12:43.221248 match AC timing 7
2530 23:12:43.224699 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2531 23:12:43.231358 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2532 23:12:43.234677 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2533 23:12:43.241523 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2534 23:12:43.244489 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2535 23:12:43.244577 ==
2536 23:12:43.248370 Dram Type= 6, Freq= 0, CH_0, rank 0
2537 23:12:43.251509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2538 23:12:43.251993 ==
2539 23:12:43.258465 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2540 23:12:43.265157 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
2541 23:12:43.272068 [CA 0] Center 39 (9~70) winsize 62
2542 23:12:43.275150 [CA 1] Center 39 (9~69) winsize 61
2543 23:12:43.278491 [CA 2] Center 35 (5~66) winsize 62
2544 23:12:43.281542 [CA 3] Center 35 (5~66) winsize 62
2545 23:12:43.284830 [CA 4] Center 33 (4~63) winsize 60
2546 23:12:43.288598 [CA 5] Center 33 (3~63) winsize 61
2547 23:12:43.288794
2548 23:12:43.291687 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2549 23:12:43.291859
2550 23:12:43.294744 [CATrainingPosCal] consider 1 rank data
2551 23:12:43.298692 u2DelayCellTimex100 = 270/100 ps
2552 23:12:43.301626 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2553 23:12:43.304466 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2554 23:12:43.311556 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2555 23:12:43.314426 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2556 23:12:43.318257 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
2557 23:12:43.321614 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2558 23:12:43.321689
2559 23:12:43.324439 CA PerBit enable=1, Macro0, CA PI delay=33
2560 23:12:43.324517
2561 23:12:43.328078 [CBTSetCACLKResult] CA Dly = 33
2562 23:12:43.328181 CS Dly: 8 (0~39)
2563 23:12:43.331666 ==
2564 23:12:43.334367 Dram Type= 6, Freq= 0, CH_0, rank 1
2565 23:12:43.338024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2566 23:12:43.338106 ==
2567 23:12:43.341496 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2568 23:12:43.347562 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2569 23:12:43.357263 [CA 0] Center 39 (9~70) winsize 62
2570 23:12:43.360538 [CA 1] Center 39 (9~70) winsize 62
2571 23:12:43.364285 [CA 2] Center 35 (5~66) winsize 62
2572 23:12:43.367262 [CA 3] Center 34 (4~65) winsize 62
2573 23:12:43.371593 [CA 4] Center 33 (3~64) winsize 62
2574 23:12:43.373903 [CA 5] Center 33 (3~63) winsize 61
2575 23:12:43.373990
2576 23:12:43.377557 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2577 23:12:43.377651
2578 23:12:43.380543 [CATrainingPosCal] consider 2 rank data
2579 23:12:43.384424 u2DelayCellTimex100 = 270/100 ps
2580 23:12:43.388396 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2581 23:12:43.394138 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2582 23:12:43.397201 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2583 23:12:43.401047 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
2584 23:12:43.403696 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
2585 23:12:43.407526 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2586 23:12:43.407606
2587 23:12:43.410421 CA PerBit enable=1, Macro0, CA PI delay=33
2588 23:12:43.410502
2589 23:12:43.413988 [CBTSetCACLKResult] CA Dly = 33
2590 23:12:43.414068 CS Dly: 9 (0~41)
2591 23:12:43.416798
2592 23:12:43.420043 ----->DramcWriteLeveling(PI) begin...
2593 23:12:43.420124 ==
2594 23:12:43.423527 Dram Type= 6, Freq= 0, CH_0, rank 0
2595 23:12:43.427791 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2596 23:12:43.427878 ==
2597 23:12:43.430198 Write leveling (Byte 0): 32 => 32
2598 23:12:43.434506 Write leveling (Byte 1): 29 => 29
2599 23:12:43.437023 DramcWriteLeveling(PI) end<-----
2600 23:12:43.437631
2601 23:12:43.438225 ==
2602 23:12:43.440752 Dram Type= 6, Freq= 0, CH_0, rank 0
2603 23:12:43.444079 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2604 23:12:43.444494 ==
2605 23:12:43.447038 [Gating] SW mode calibration
2606 23:12:43.453419 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2607 23:12:43.460523 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2608 23:12:43.463873 0 15 0 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (0 0)
2609 23:12:43.466790 0 15 4 | B1->B0 | 2626 3434 | 0 1 | (0 0) (1 1)
2610 23:12:43.474174 0 15 8 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
2611 23:12:43.476942 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2612 23:12:43.480002 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2613 23:12:43.486794 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2614 23:12:43.490193 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2615 23:12:43.494529 0 15 28 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (1 0)
2616 23:12:43.496630 1 0 0 | B1->B0 | 2e2e 2323 | 0 0 | (1 0) (0 0)
2617 23:12:43.503303 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2618 23:12:43.506444 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2619 23:12:43.512742 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2620 23:12:43.516692 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2621 23:12:43.519527 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2622 23:12:43.526076 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2623 23:12:43.529349 1 0 28 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
2624 23:12:43.532535 1 1 0 | B1->B0 | 2a2a 4646 | 0 0 | (0 0) (0 0)
2625 23:12:43.540425 1 1 4 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
2626 23:12:43.543030 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2627 23:12:43.546732 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2628 23:12:43.549374 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2629 23:12:43.555827 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2630 23:12:43.559677 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2631 23:12:43.562520 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2632 23:12:43.569463 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2633 23:12:43.572967 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2634 23:12:43.576031 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2635 23:12:43.582103 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2636 23:12:43.586110 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2637 23:12:43.589315 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2638 23:12:43.596366 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2639 23:12:43.599211 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2640 23:12:43.603127 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2641 23:12:43.609791 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2642 23:12:43.612865 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2643 23:12:43.616072 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2644 23:12:43.622043 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2645 23:12:43.625482 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2646 23:12:43.628748 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2647 23:12:43.635248 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2648 23:12:43.638806 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2649 23:12:43.642492 Total UI for P1: 0, mck2ui 16
2650 23:12:43.646247 best dqsien dly found for B0: ( 1, 3, 28)
2651 23:12:43.649290 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2652 23:12:43.655464 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2653 23:12:43.655572 Total UI for P1: 0, mck2ui 16
2654 23:12:43.661544 best dqsien dly found for B1: ( 1, 4, 2)
2655 23:12:43.664770 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2656 23:12:43.668575 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2657 23:12:43.668966
2658 23:12:43.672351 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2659 23:12:43.675173 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2660 23:12:43.679020 [Gating] SW calibration Done
2661 23:12:43.679398 ==
2662 23:12:43.681768 Dram Type= 6, Freq= 0, CH_0, rank 0
2663 23:12:43.685399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2664 23:12:43.685607 ==
2665 23:12:43.688165 RX Vref Scan: 0
2666 23:12:43.688440
2667 23:12:43.688671 RX Vref 0 -> 0, step: 1
2668 23:12:43.688911
2669 23:12:43.691708 RX Delay -40 -> 252, step: 8
2670 23:12:43.694882 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2671 23:12:43.701741 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2672 23:12:43.704684 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2673 23:12:43.708220 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2674 23:12:43.711696 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2675 23:12:43.714618 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2676 23:12:43.721534 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2677 23:12:43.724613 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2678 23:12:43.727943 iDelay=200, Bit 8, Center 99 (24 ~ 175) 152
2679 23:12:43.731440 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2680 23:12:43.735119 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
2681 23:12:43.742014 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2682 23:12:43.744467 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2683 23:12:43.748089 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2684 23:12:43.752019 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2685 23:12:43.754647 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2686 23:12:43.758718 ==
2687 23:12:43.761745 Dram Type= 6, Freq= 0, CH_0, rank 0
2688 23:12:43.764342 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2689 23:12:43.764420 ==
2690 23:12:43.764483 DQS Delay:
2691 23:12:43.768002 DQS0 = 0, DQS1 = 0
2692 23:12:43.768079 DQM Delay:
2693 23:12:43.771054 DQM0 = 119, DQM1 = 107
2694 23:12:43.771171 DQ Delay:
2695 23:12:43.774278 DQ0 =119, DQ1 =119, DQ2 =115, DQ3 =115
2696 23:12:43.777554 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =127
2697 23:12:43.781369 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =103
2698 23:12:43.784383 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2699 23:12:43.784459
2700 23:12:43.784542
2701 23:12:43.784600 ==
2702 23:12:43.787563 Dram Type= 6, Freq= 0, CH_0, rank 0
2703 23:12:43.794301 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2704 23:12:43.794403 ==
2705 23:12:43.794506
2706 23:12:43.794602
2707 23:12:43.797747 TX Vref Scan disable
2708 23:12:43.797861 == TX Byte 0 ==
2709 23:12:43.800764 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2710 23:12:43.807332 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2711 23:12:43.807441 == TX Byte 1 ==
2712 23:12:43.810405 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2713 23:12:43.817622 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2714 23:12:43.817719 ==
2715 23:12:43.820788 Dram Type= 6, Freq= 0, CH_0, rank 0
2716 23:12:43.824910 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2717 23:12:43.824996 ==
2718 23:12:43.835966 TX Vref=22, minBit 7, minWin=25, winSum=417
2719 23:12:43.839426 TX Vref=24, minBit 13, minWin=25, winSum=424
2720 23:12:43.842922 TX Vref=26, minBit 10, minWin=26, winSum=430
2721 23:12:43.846222 TX Vref=28, minBit 13, minWin=25, winSum=431
2722 23:12:43.849482 TX Vref=30, minBit 10, minWin=25, winSum=433
2723 23:12:43.856440 TX Vref=32, minBit 10, minWin=25, winSum=428
2724 23:12:43.859781 [TxChooseVref] Worse bit 10, Min win 26, Win sum 430, Final Vref 26
2725 23:12:43.860187
2726 23:12:43.863766 Final TX Range 1 Vref 26
2727 23:12:43.864119
2728 23:12:43.864439 ==
2729 23:12:43.866520 Dram Type= 6, Freq= 0, CH_0, rank 0
2730 23:12:43.873825 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2731 23:12:43.874006 ==
2732 23:12:43.874149
2733 23:12:43.874280
2734 23:12:43.874406 TX Vref Scan disable
2735 23:12:43.876020 == TX Byte 0 ==
2736 23:12:43.879431 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2737 23:12:43.883450 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2738 23:12:43.886869 == TX Byte 1 ==
2739 23:12:43.889698 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2740 23:12:43.896800 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2741 23:12:43.896966
2742 23:12:43.897121 [DATLAT]
2743 23:12:43.897261 Freq=1200, CH0 RK0
2744 23:12:43.897369
2745 23:12:43.899389 DATLAT Default: 0xd
2746 23:12:43.899528 0, 0xFFFF, sum = 0
2747 23:12:43.903088 1, 0xFFFF, sum = 0
2748 23:12:43.903199 2, 0xFFFF, sum = 0
2749 23:12:43.905867 3, 0xFFFF, sum = 0
2750 23:12:43.909280 4, 0xFFFF, sum = 0
2751 23:12:43.909377 5, 0xFFFF, sum = 0
2752 23:12:43.912634 6, 0xFFFF, sum = 0
2753 23:12:43.912732 7, 0xFFFF, sum = 0
2754 23:12:43.915848 8, 0xFFFF, sum = 0
2755 23:12:43.915943 9, 0xFFFF, sum = 0
2756 23:12:43.920613 10, 0xFFFF, sum = 0
2757 23:12:43.920713 11, 0xFFFF, sum = 0
2758 23:12:43.922782 12, 0x0, sum = 1
2759 23:12:43.922880 13, 0x0, sum = 2
2760 23:12:43.926620 14, 0x0, sum = 3
2761 23:12:43.926716 15, 0x0, sum = 4
2762 23:12:43.929511 best_step = 13
2763 23:12:43.929607
2764 23:12:43.929688 ==
2765 23:12:43.933417 Dram Type= 6, Freq= 0, CH_0, rank 0
2766 23:12:43.935641 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2767 23:12:43.935762 ==
2768 23:12:43.935848 RX Vref Scan: 1
2769 23:12:43.939330
2770 23:12:43.939425 Set Vref Range= 32 -> 127
2771 23:12:43.939517
2772 23:12:43.943082 RX Vref 32 -> 127, step: 1
2773 23:12:43.943182
2774 23:12:43.946692 RX Delay -21 -> 252, step: 4
2775 23:12:43.946796
2776 23:12:43.949103 Set Vref, RX VrefLevel [Byte0]: 32
2777 23:12:43.953532 [Byte1]: 32
2778 23:12:43.953667
2779 23:12:43.956189 Set Vref, RX VrefLevel [Byte0]: 33
2780 23:12:43.959104 [Byte1]: 33
2781 23:12:43.962769
2782 23:12:43.962895 Set Vref, RX VrefLevel [Byte0]: 34
2783 23:12:43.965997 [Byte1]: 34
2784 23:12:43.970850
2785 23:12:43.970961 Set Vref, RX VrefLevel [Byte0]: 35
2786 23:12:43.974149 [Byte1]: 35
2787 23:12:43.979340
2788 23:12:43.979439 Set Vref, RX VrefLevel [Byte0]: 36
2789 23:12:43.981656 [Byte1]: 36
2790 23:12:43.986989
2791 23:12:43.987064 Set Vref, RX VrefLevel [Byte0]: 37
2792 23:12:43.989824 [Byte1]: 37
2793 23:12:43.994412
2794 23:12:43.994482 Set Vref, RX VrefLevel [Byte0]: 38
2795 23:12:43.997976 [Byte1]: 38
2796 23:12:44.003120
2797 23:12:44.003195 Set Vref, RX VrefLevel [Byte0]: 39
2798 23:12:44.005450 [Byte1]: 39
2799 23:12:44.010518
2800 23:12:44.010632 Set Vref, RX VrefLevel [Byte0]: 40
2801 23:12:44.013855 [Byte1]: 40
2802 23:12:44.018601
2803 23:12:44.018704 Set Vref, RX VrefLevel [Byte0]: 41
2804 23:12:44.021837 [Byte1]: 41
2805 23:12:44.026282
2806 23:12:44.026385 Set Vref, RX VrefLevel [Byte0]: 42
2807 23:12:44.029351 [Byte1]: 42
2808 23:12:44.034382
2809 23:12:44.034498 Set Vref, RX VrefLevel [Byte0]: 43
2810 23:12:44.038123 [Byte1]: 43
2811 23:12:44.042117
2812 23:12:44.042230 Set Vref, RX VrefLevel [Byte0]: 44
2813 23:12:44.045298 [Byte1]: 44
2814 23:12:44.050237
2815 23:12:44.050382 Set Vref, RX VrefLevel [Byte0]: 45
2816 23:12:44.053005 [Byte1]: 45
2817 23:12:44.057980
2818 23:12:44.058213 Set Vref, RX VrefLevel [Byte0]: 46
2819 23:12:44.061410 [Byte1]: 46
2820 23:12:44.065880
2821 23:12:44.066082 Set Vref, RX VrefLevel [Byte0]: 47
2822 23:12:44.068840 [Byte1]: 47
2823 23:12:44.073668
2824 23:12:44.073964 Set Vref, RX VrefLevel [Byte0]: 48
2825 23:12:44.077445 [Byte1]: 48
2826 23:12:44.081711
2827 23:12:44.082107 Set Vref, RX VrefLevel [Byte0]: 49
2828 23:12:44.085035 [Byte1]: 49
2829 23:12:44.089777
2830 23:12:44.090097 Set Vref, RX VrefLevel [Byte0]: 50
2831 23:12:44.092898 [Byte1]: 50
2832 23:12:44.097500
2833 23:12:44.097818 Set Vref, RX VrefLevel [Byte0]: 51
2834 23:12:44.100895 [Byte1]: 51
2835 23:12:44.105515
2836 23:12:44.105830 Set Vref, RX VrefLevel [Byte0]: 52
2837 23:12:44.108944 [Byte1]: 52
2838 23:12:44.113734
2839 23:12:44.113990 Set Vref, RX VrefLevel [Byte0]: 53
2840 23:12:44.117221 [Byte1]: 53
2841 23:12:44.121552
2842 23:12:44.121708 Set Vref, RX VrefLevel [Byte0]: 54
2843 23:12:44.124454 [Byte1]: 54
2844 23:12:44.129443
2845 23:12:44.129560 Set Vref, RX VrefLevel [Byte0]: 55
2846 23:12:44.132451 [Byte1]: 55
2847 23:12:44.137764
2848 23:12:44.137862 Set Vref, RX VrefLevel [Byte0]: 56
2849 23:12:44.141004 [Byte1]: 56
2850 23:12:44.144792
2851 23:12:44.144884 Set Vref, RX VrefLevel [Byte0]: 57
2852 23:12:44.148461 [Byte1]: 57
2853 23:12:44.153084
2854 23:12:44.153211 Set Vref, RX VrefLevel [Byte0]: 58
2855 23:12:44.156009 [Byte1]: 58
2856 23:12:44.160518
2857 23:12:44.163902 Set Vref, RX VrefLevel [Byte0]: 59
2858 23:12:44.167082 [Byte1]: 59
2859 23:12:44.167155
2860 23:12:44.170340 Set Vref, RX VrefLevel [Byte0]: 60
2861 23:12:44.173974 [Byte1]: 60
2862 23:12:44.174072
2863 23:12:44.177145 Set Vref, RX VrefLevel [Byte0]: 61
2864 23:12:44.180645 [Byte1]: 61
2865 23:12:44.185064
2866 23:12:44.185163 Set Vref, RX VrefLevel [Byte0]: 62
2867 23:12:44.187565 [Byte1]: 62
2868 23:12:44.192356
2869 23:12:44.192432 Set Vref, RX VrefLevel [Byte0]: 63
2870 23:12:44.196015 [Byte1]: 63
2871 23:12:44.201130
2872 23:12:44.201200 Set Vref, RX VrefLevel [Byte0]: 64
2873 23:12:44.203610 [Byte1]: 64
2874 23:12:44.208207
2875 23:12:44.208283 Set Vref, RX VrefLevel [Byte0]: 65
2876 23:12:44.212586 [Byte1]: 65
2877 23:12:44.216302
2878 23:12:44.216380 Set Vref, RX VrefLevel [Byte0]: 66
2879 23:12:44.219914 [Byte1]: 66
2880 23:12:44.224149
2881 23:12:44.224222 Set Vref, RX VrefLevel [Byte0]: 67
2882 23:12:44.227541 [Byte1]: 67
2883 23:12:44.232074
2884 23:12:44.232173 Set Vref, RX VrefLevel [Byte0]: 68
2885 23:12:44.235966 [Byte1]: 68
2886 23:12:44.239851
2887 23:12:44.239947 Set Vref, RX VrefLevel [Byte0]: 69
2888 23:12:44.243570 [Byte1]: 69
2889 23:12:44.248045
2890 23:12:44.248126 Set Vref, RX VrefLevel [Byte0]: 70
2891 23:12:44.251803 [Byte1]: 70
2892 23:12:44.256202
2893 23:12:44.256275 Set Vref, RX VrefLevel [Byte0]: 71
2894 23:12:44.259537 [Byte1]: 71
2895 23:12:44.264042
2896 23:12:44.264142 Set Vref, RX VrefLevel [Byte0]: 72
2897 23:12:44.267334 [Byte1]: 72
2898 23:12:44.271763
2899 23:12:44.271861 Set Vref, RX VrefLevel [Byte0]: 73
2900 23:12:44.275793 [Byte1]: 73
2901 23:12:44.279558
2902 23:12:44.279628 Set Vref, RX VrefLevel [Byte0]: 74
2903 23:12:44.282947 [Byte1]: 74
2904 23:12:44.287919
2905 23:12:44.288000 Set Vref, RX VrefLevel [Byte0]: 75
2906 23:12:44.290882 [Byte1]: 75
2907 23:12:44.295615
2908 23:12:44.295715 Set Vref, RX VrefLevel [Byte0]: 76
2909 23:12:44.299192 [Byte1]: 76
2910 23:12:44.304240
2911 23:12:44.304355 Set Vref, RX VrefLevel [Byte0]: 77
2912 23:12:44.307551 [Byte1]: 77
2913 23:12:44.311476
2914 23:12:44.311651 Final RX Vref Byte 0 = 61 to rank0
2915 23:12:44.314657 Final RX Vref Byte 1 = 49 to rank0
2916 23:12:44.318059 Final RX Vref Byte 0 = 61 to rank1
2917 23:12:44.321523 Final RX Vref Byte 1 = 49 to rank1==
2918 23:12:44.324946 Dram Type= 6, Freq= 0, CH_0, rank 0
2919 23:12:44.331521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2920 23:12:44.331713 ==
2921 23:12:44.331854 DQS Delay:
2922 23:12:44.334453 DQS0 = 0, DQS1 = 0
2923 23:12:44.334634 DQM Delay:
2924 23:12:44.334748 DQM0 = 119, DQM1 = 106
2925 23:12:44.337754 DQ Delay:
2926 23:12:44.341142 DQ0 =116, DQ1 =120, DQ2 =116, DQ3 =116
2927 23:12:44.344586 DQ4 =120, DQ5 =114, DQ6 =124, DQ7 =126
2928 23:12:44.347945 DQ8 =96, DQ9 =92, DQ10 =110, DQ11 =100
2929 23:12:44.351134 DQ12 =112, DQ13 =110, DQ14 =118, DQ15 =116
2930 23:12:44.351275
2931 23:12:44.351441
2932 23:12:44.361191 [DQSOSCAuto] RK0, (LSB)MR18= 0xdf8, (MSB)MR19= 0x403, tDQSOscB0 = 413 ps tDQSOscB1 = 405 ps
2933 23:12:44.361331 CH0 RK0: MR19=403, MR18=DF8
2934 23:12:44.368650 CH0_RK0: MR19=0x403, MR18=0xDF8, DQSOSC=405, MR23=63, INC=39, DEC=26
2935 23:12:44.368846
2936 23:12:44.371228 ----->DramcWriteLeveling(PI) begin...
2937 23:12:44.371438 ==
2938 23:12:44.374051 Dram Type= 6, Freq= 0, CH_0, rank 1
2939 23:12:44.381639 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2940 23:12:44.381884 ==
2941 23:12:44.384567 Write leveling (Byte 0): 32 => 32
2942 23:12:44.384746 Write leveling (Byte 1): 29 => 29
2943 23:12:44.387616 DramcWriteLeveling(PI) end<-----
2944 23:12:44.387813
2945 23:12:44.387970 ==
2946 23:12:44.390611 Dram Type= 6, Freq= 0, CH_0, rank 1
2947 23:12:44.397579 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2948 23:12:44.397761 ==
2949 23:12:44.400854 [Gating] SW mode calibration
2950 23:12:44.408279 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2951 23:12:44.410947 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2952 23:12:44.417191 0 15 0 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
2953 23:12:44.420879 0 15 4 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
2954 23:12:44.424381 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2955 23:12:44.430424 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2956 23:12:44.433895 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2957 23:12:44.437930 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2958 23:12:44.443566 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2959 23:12:44.446907 0 15 28 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
2960 23:12:44.450398 1 0 0 | B1->B0 | 2e2e 2323 | 0 0 | (0 1) (1 0)
2961 23:12:44.456938 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2962 23:12:44.461198 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2963 23:12:44.464465 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2964 23:12:44.470551 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2965 23:12:44.474024 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2966 23:12:44.477138 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2967 23:12:44.484066 1 0 28 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
2968 23:12:44.486674 1 1 0 | B1->B0 | 3635 4646 | 1 0 | (0 0) (0 0)
2969 23:12:44.490113 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2970 23:12:44.496610 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2971 23:12:44.499999 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2972 23:12:44.503446 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2973 23:12:44.509602 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2974 23:12:44.513083 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2975 23:12:44.517016 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2976 23:12:44.519888 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2977 23:12:44.526224 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2978 23:12:44.529931 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2979 23:12:44.533151 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2980 23:12:44.539550 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2981 23:12:44.542959 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2982 23:12:44.546686 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2983 23:12:44.552895 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2984 23:12:44.559611 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2985 23:12:44.559935 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2986 23:12:44.566615 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2987 23:12:44.570047 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2988 23:12:44.572822 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2989 23:12:44.579506 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2990 23:12:44.582713 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2991 23:12:44.586275 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2992 23:12:44.592857 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2993 23:12:44.592974 Total UI for P1: 0, mck2ui 16
2994 23:12:44.600149 best dqsien dly found for B0: ( 1, 3, 28)
2995 23:12:44.603179 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2996 23:12:44.606150 Total UI for P1: 0, mck2ui 16
2997 23:12:44.609459 best dqsien dly found for B1: ( 1, 4, 0)
2998 23:12:44.612544 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2999 23:12:44.616462 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
3000 23:12:44.616538
3001 23:12:44.619223 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3002 23:12:44.622455 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
3003 23:12:44.626663 [Gating] SW calibration Done
3004 23:12:44.626739 ==
3005 23:12:44.629357 Dram Type= 6, Freq= 0, CH_0, rank 1
3006 23:12:44.633024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3007 23:12:44.636102 ==
3008 23:12:44.636173 RX Vref Scan: 0
3009 23:12:44.636234
3010 23:12:44.639299 RX Vref 0 -> 0, step: 1
3011 23:12:44.639396
3012 23:12:44.639486 RX Delay -40 -> 252, step: 8
3013 23:12:44.646059 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
3014 23:12:44.649082 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
3015 23:12:44.652850 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
3016 23:12:44.656072 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3017 23:12:44.663022 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3018 23:12:44.665368 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
3019 23:12:44.669917 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3020 23:12:44.672527 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
3021 23:12:44.675888 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3022 23:12:44.679221 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3023 23:12:44.685753 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3024 23:12:44.688906 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3025 23:12:44.692044 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
3026 23:12:44.695611 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3027 23:12:44.702796 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3028 23:12:44.705225 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3029 23:12:44.705293 ==
3030 23:12:44.708703 Dram Type= 6, Freq= 0, CH_0, rank 1
3031 23:12:44.712638 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3032 23:12:44.712710 ==
3033 23:12:44.715253 DQS Delay:
3034 23:12:44.715364 DQS0 = 0, DQS1 = 0
3035 23:12:44.715431 DQM Delay:
3036 23:12:44.718771 DQM0 = 116, DQM1 = 108
3037 23:12:44.718848 DQ Delay:
3038 23:12:44.721763 DQ0 =111, DQ1 =123, DQ2 =111, DQ3 =115
3039 23:12:44.725426 DQ4 =115, DQ5 =111, DQ6 =123, DQ7 =123
3040 23:12:44.728594 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =103
3041 23:12:44.735408 DQ12 =111, DQ13 =119, DQ14 =119, DQ15 =111
3042 23:12:44.735490
3043 23:12:44.735554
3044 23:12:44.735614 ==
3045 23:12:44.738581 Dram Type= 6, Freq= 0, CH_0, rank 1
3046 23:12:44.741855 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3047 23:12:44.741938 ==
3048 23:12:44.742002
3049 23:12:44.742061
3050 23:12:44.745752 TX Vref Scan disable
3051 23:12:44.745834 == TX Byte 0 ==
3052 23:12:44.752265 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
3053 23:12:44.754848 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
3054 23:12:44.754962 == TX Byte 1 ==
3055 23:12:44.761643 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3056 23:12:44.764797 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3057 23:12:44.764911 ==
3058 23:12:44.768779 Dram Type= 6, Freq= 0, CH_0, rank 1
3059 23:12:44.772245 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3060 23:12:44.772361 ==
3061 23:12:44.784710 TX Vref=22, minBit 5, minWin=25, winSum=422
3062 23:12:44.788383 TX Vref=24, minBit 5, minWin=25, winSum=426
3063 23:12:44.791786 TX Vref=26, minBit 1, minWin=26, winSum=430
3064 23:12:44.794672 TX Vref=28, minBit 1, minWin=26, winSum=433
3065 23:12:44.797688 TX Vref=30, minBit 13, minWin=26, winSum=436
3066 23:12:44.804819 TX Vref=32, minBit 10, minWin=26, winSum=432
3067 23:12:44.808051 [TxChooseVref] Worse bit 13, Min win 26, Win sum 436, Final Vref 30
3068 23:12:44.808133
3069 23:12:44.810943 Final TX Range 1 Vref 30
3070 23:12:44.811025
3071 23:12:44.811089 ==
3072 23:12:44.814639 Dram Type= 6, Freq= 0, CH_0, rank 1
3073 23:12:44.818780 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3074 23:12:44.820862 ==
3075 23:12:44.820943
3076 23:12:44.821008
3077 23:12:44.821067 TX Vref Scan disable
3078 23:12:44.825529 == TX Byte 0 ==
3079 23:12:44.828218 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
3080 23:12:44.834976 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
3081 23:12:44.835074 == TX Byte 1 ==
3082 23:12:44.838204 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3083 23:12:44.845375 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3084 23:12:44.845445
3085 23:12:44.845506 [DATLAT]
3086 23:12:44.845562 Freq=1200, CH0 RK1
3087 23:12:44.845618
3088 23:12:44.848926 DATLAT Default: 0xd
3089 23:12:44.848990 0, 0xFFFF, sum = 0
3090 23:12:44.851272 1, 0xFFFF, sum = 0
3091 23:12:44.851365 2, 0xFFFF, sum = 0
3092 23:12:44.854378 3, 0xFFFF, sum = 0
3093 23:12:44.857748 4, 0xFFFF, sum = 0
3094 23:12:44.857817 5, 0xFFFF, sum = 0
3095 23:12:44.861217 6, 0xFFFF, sum = 0
3096 23:12:44.861287 7, 0xFFFF, sum = 0
3097 23:12:44.864352 8, 0xFFFF, sum = 0
3098 23:12:44.864449 9, 0xFFFF, sum = 0
3099 23:12:44.867996 10, 0xFFFF, sum = 0
3100 23:12:44.868073 11, 0xFFFF, sum = 0
3101 23:12:44.870865 12, 0x0, sum = 1
3102 23:12:44.870932 13, 0x0, sum = 2
3103 23:12:44.874545 14, 0x0, sum = 3
3104 23:12:44.874615 15, 0x0, sum = 4
3105 23:12:44.877792 best_step = 13
3106 23:12:44.877860
3107 23:12:44.877918 ==
3108 23:12:44.881261 Dram Type= 6, Freq= 0, CH_0, rank 1
3109 23:12:44.883858 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3110 23:12:44.883930 ==
3111 23:12:44.883991 RX Vref Scan: 0
3112 23:12:44.887370
3113 23:12:44.887437 RX Vref 0 -> 0, step: 1
3114 23:12:44.887495
3115 23:12:44.891787 RX Delay -21 -> 252, step: 4
3116 23:12:44.897183 iDelay=195, Bit 0, Center 114 (47 ~ 182) 136
3117 23:12:44.900776 iDelay=195, Bit 1, Center 118 (47 ~ 190) 144
3118 23:12:44.903881 iDelay=195, Bit 2, Center 110 (43 ~ 178) 136
3119 23:12:44.907336 iDelay=195, Bit 3, Center 112 (43 ~ 182) 140
3120 23:12:44.910749 iDelay=195, Bit 4, Center 116 (47 ~ 186) 140
3121 23:12:44.917516 iDelay=195, Bit 5, Center 110 (43 ~ 178) 136
3122 23:12:44.920517 iDelay=195, Bit 6, Center 124 (55 ~ 194) 140
3123 23:12:44.923457 iDelay=195, Bit 7, Center 124 (55 ~ 194) 140
3124 23:12:44.927199 iDelay=195, Bit 8, Center 96 (27 ~ 166) 140
3125 23:12:44.931478 iDelay=195, Bit 9, Center 94 (27 ~ 162) 136
3126 23:12:44.938371 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3127 23:12:44.940317 iDelay=195, Bit 11, Center 100 (35 ~ 166) 132
3128 23:12:44.943694 iDelay=195, Bit 12, Center 114 (47 ~ 182) 136
3129 23:12:44.946714 iDelay=195, Bit 13, Center 114 (47 ~ 182) 136
3130 23:12:44.950681 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3131 23:12:44.956901 iDelay=195, Bit 15, Center 116 (51 ~ 182) 132
3132 23:12:44.957004 ==
3133 23:12:44.960008 Dram Type= 6, Freq= 0, CH_0, rank 1
3134 23:12:44.963755 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3135 23:12:44.963824 ==
3136 23:12:44.963885 DQS Delay:
3137 23:12:44.967109 DQS0 = 0, DQS1 = 0
3138 23:12:44.967204 DQM Delay:
3139 23:12:44.970173 DQM0 = 116, DQM1 = 107
3140 23:12:44.970268 DQ Delay:
3141 23:12:44.973904 DQ0 =114, DQ1 =118, DQ2 =110, DQ3 =112
3142 23:12:44.977248 DQ4 =116, DQ5 =110, DQ6 =124, DQ7 =124
3143 23:12:44.980063 DQ8 =96, DQ9 =94, DQ10 =110, DQ11 =100
3144 23:12:44.983951 DQ12 =114, DQ13 =114, DQ14 =118, DQ15 =116
3145 23:12:44.984022
3146 23:12:44.984082
3147 23:12:44.993165 [DQSOSCAuto] RK1, (LSB)MR18= 0xae5, (MSB)MR19= 0x403, tDQSOscB0 = 421 ps tDQSOscB1 = 406 ps
3148 23:12:44.997240 CH0 RK1: MR19=403, MR18=AE5
3149 23:12:44.999838 CH0_RK1: MR19=0x403, MR18=0xAE5, DQSOSC=406, MR23=63, INC=39, DEC=26
3150 23:12:45.003305 [RxdqsGatingPostProcess] freq 1200
3151 23:12:45.009998 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3152 23:12:45.013207 best DQS0 dly(2T, 0.5T) = (0, 11)
3153 23:12:45.016708 best DQS1 dly(2T, 0.5T) = (0, 12)
3154 23:12:45.020168 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3155 23:12:45.023068 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3156 23:12:45.026638 best DQS0 dly(2T, 0.5T) = (0, 11)
3157 23:12:45.029446 best DQS1 dly(2T, 0.5T) = (0, 12)
3158 23:12:45.033524 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3159 23:12:45.036199 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3160 23:12:45.039849 Pre-setting of DQS Precalculation
3161 23:12:45.042798 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3162 23:12:45.042863 ==
3163 23:12:45.046339 Dram Type= 6, Freq= 0, CH_1, rank 0
3164 23:12:45.049934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3165 23:12:45.052526 ==
3166 23:12:45.055920 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3167 23:12:45.063392 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3168 23:12:45.071447 [CA 0] Center 37 (7~67) winsize 61
3169 23:12:45.074287 [CA 1] Center 37 (7~68) winsize 62
3170 23:12:45.077339 [CA 2] Center 34 (4~64) winsize 61
3171 23:12:45.080866 [CA 3] Center 33 (3~64) winsize 62
3172 23:12:45.084259 [CA 4] Center 34 (4~64) winsize 61
3173 23:12:45.087945 [CA 5] Center 33 (3~64) winsize 62
3174 23:12:45.088028
3175 23:12:45.090830 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3176 23:12:45.090903
3177 23:12:45.094182 [CATrainingPosCal] consider 1 rank data
3178 23:12:45.097124 u2DelayCellTimex100 = 270/100 ps
3179 23:12:45.100542 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3180 23:12:45.107315 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3181 23:12:45.110397 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3182 23:12:45.114124 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3183 23:12:45.117153 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3184 23:12:45.120500 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3185 23:12:45.120582
3186 23:12:45.124521 CA PerBit enable=1, Macro0, CA PI delay=33
3187 23:12:45.124659
3188 23:12:45.127606 [CBTSetCACLKResult] CA Dly = 33
3189 23:12:45.127736 CS Dly: 5 (0~36)
3190 23:12:45.131360 ==
3191 23:12:45.133759 Dram Type= 6, Freq= 0, CH_1, rank 1
3192 23:12:45.136905 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3193 23:12:45.137034 ==
3194 23:12:45.140943 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3195 23:12:45.147150 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3196 23:12:45.157041 [CA 0] Center 37 (7~68) winsize 62
3197 23:12:45.160252 [CA 1] Center 38 (8~68) winsize 61
3198 23:12:45.163292 [CA 2] Center 34 (4~65) winsize 62
3199 23:12:45.165980 [CA 3] Center 33 (3~64) winsize 62
3200 23:12:45.169315 [CA 4] Center 34 (3~65) winsize 63
3201 23:12:45.172745 [CA 5] Center 33 (3~64) winsize 62
3202 23:12:45.172880
3203 23:12:45.176005 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3204 23:12:45.176130
3205 23:12:45.179204 [CATrainingPosCal] consider 2 rank data
3206 23:12:45.182699 u2DelayCellTimex100 = 270/100 ps
3207 23:12:45.185872 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3208 23:12:45.192545 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3209 23:12:45.196336 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3210 23:12:45.199500 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3211 23:12:45.202482 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3212 23:12:45.206449 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3213 23:12:45.206542
3214 23:12:45.209314 CA PerBit enable=1, Macro0, CA PI delay=33
3215 23:12:45.209396
3216 23:12:45.212736 [CBTSetCACLKResult] CA Dly = 33
3217 23:12:45.212818 CS Dly: 7 (0~40)
3218 23:12:45.215642
3219 23:12:45.219718 ----->DramcWriteLeveling(PI) begin...
3220 23:12:45.219807 ==
3221 23:12:45.222465 Dram Type= 6, Freq= 0, CH_1, rank 0
3222 23:12:45.226471 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3223 23:12:45.226556 ==
3224 23:12:45.229667 Write leveling (Byte 0): 23 => 23
3225 23:12:45.232754 Write leveling (Byte 1): 28 => 28
3226 23:12:45.236217 DramcWriteLeveling(PI) end<-----
3227 23:12:45.236299
3228 23:12:45.236363 ==
3229 23:12:45.239968 Dram Type= 6, Freq= 0, CH_1, rank 0
3230 23:12:45.242377 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3231 23:12:45.242459 ==
3232 23:12:45.246045 [Gating] SW mode calibration
3233 23:12:45.253375 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3234 23:12:45.258981 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3235 23:12:45.263073 0 15 0 | B1->B0 | 3333 3434 | 1 1 | (0 0) (1 1)
3236 23:12:45.265864 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3237 23:12:45.272257 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3238 23:12:45.275965 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3239 23:12:45.279021 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3240 23:12:45.285841 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3241 23:12:45.288699 0 15 24 | B1->B0 | 3434 2d2d | 1 0 | (1 0) (0 1)
3242 23:12:45.292335 0 15 28 | B1->B0 | 2626 2323 | 0 0 | (0 1) (1 0)
3243 23:12:45.298765 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3244 23:12:45.302388 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3245 23:12:45.305406 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3246 23:12:45.312069 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3247 23:12:45.316179 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3248 23:12:45.318733 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3249 23:12:45.325315 1 0 24 | B1->B0 | 2626 3636 | 0 1 | (0 0) (0 0)
3250 23:12:45.328630 1 0 28 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
3251 23:12:45.331956 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3252 23:12:45.335609 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3253 23:12:45.341975 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3254 23:12:45.345604 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3255 23:12:45.348569 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3256 23:12:45.355150 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3257 23:12:45.358989 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3258 23:12:45.362273 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3259 23:12:45.368752 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3260 23:12:45.371939 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3261 23:12:45.375626 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3262 23:12:45.381819 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3263 23:12:45.385228 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3264 23:12:45.388092 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3265 23:12:45.395293 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3266 23:12:45.398672 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3267 23:12:45.401669 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3268 23:12:45.408222 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3269 23:12:45.411517 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3270 23:12:45.415401 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3271 23:12:45.421330 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3272 23:12:45.424856 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3273 23:12:45.428405 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3274 23:12:45.434776 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3275 23:12:45.434893 Total UI for P1: 0, mck2ui 16
3276 23:12:45.441418 best dqsien dly found for B0: ( 1, 3, 24)
3277 23:12:45.445209 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3278 23:12:45.448190 Total UI for P1: 0, mck2ui 16
3279 23:12:45.452222 best dqsien dly found for B1: ( 1, 3, 26)
3280 23:12:45.454740 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3281 23:12:45.457863 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3282 23:12:45.457944
3283 23:12:45.461602 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3284 23:12:45.464481 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3285 23:12:45.468066 [Gating] SW calibration Done
3286 23:12:45.468153 ==
3287 23:12:45.471373 Dram Type= 6, Freq= 0, CH_1, rank 0
3288 23:12:45.474530 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3289 23:12:45.478429 ==
3290 23:12:45.478511 RX Vref Scan: 0
3291 23:12:45.478575
3292 23:12:45.481521 RX Vref 0 -> 0, step: 1
3293 23:12:45.481603
3294 23:12:45.481666 RX Delay -40 -> 252, step: 8
3295 23:12:45.488276 iDelay=208, Bit 0, Center 123 (48 ~ 199) 152
3296 23:12:45.491287 iDelay=208, Bit 1, Center 111 (40 ~ 183) 144
3297 23:12:45.494557 iDelay=208, Bit 2, Center 111 (40 ~ 183) 144
3298 23:12:45.497891 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3299 23:12:45.501462 iDelay=208, Bit 4, Center 111 (40 ~ 183) 144
3300 23:12:45.508497 iDelay=208, Bit 5, Center 131 (56 ~ 207) 152
3301 23:12:45.511461 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3302 23:12:45.514815 iDelay=208, Bit 7, Center 115 (48 ~ 183) 136
3303 23:12:45.517720 iDelay=208, Bit 8, Center 95 (24 ~ 167) 144
3304 23:12:45.521185 iDelay=208, Bit 9, Center 99 (24 ~ 175) 152
3305 23:12:45.527971 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3306 23:12:45.531176 iDelay=208, Bit 11, Center 95 (24 ~ 167) 144
3307 23:12:45.534424 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3308 23:12:45.537632 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3309 23:12:45.541205 iDelay=208, Bit 14, Center 115 (40 ~ 191) 152
3310 23:12:45.547497 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3311 23:12:45.547577 ==
3312 23:12:45.550930 Dram Type= 6, Freq= 0, CH_1, rank 0
3313 23:12:45.554124 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3314 23:12:45.554206 ==
3315 23:12:45.554270 DQS Delay:
3316 23:12:45.557727 DQS0 = 0, DQS1 = 0
3317 23:12:45.557808 DQM Delay:
3318 23:12:45.561099 DQM0 = 117, DQM1 = 109
3319 23:12:45.561180 DQ Delay:
3320 23:12:45.564579 DQ0 =123, DQ1 =111, DQ2 =111, DQ3 =115
3321 23:12:45.567324 DQ4 =111, DQ5 =131, DQ6 =123, DQ7 =115
3322 23:12:45.570727 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =95
3323 23:12:45.574441 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3324 23:12:45.577541
3325 23:12:45.577621
3326 23:12:45.577684 ==
3327 23:12:45.580674 Dram Type= 6, Freq= 0, CH_1, rank 0
3328 23:12:45.583944 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3329 23:12:45.584025 ==
3330 23:12:45.584090
3331 23:12:45.584147
3332 23:12:45.587570 TX Vref Scan disable
3333 23:12:45.587650 == TX Byte 0 ==
3334 23:12:45.594156 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
3335 23:12:45.597843 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
3336 23:12:45.597924 == TX Byte 1 ==
3337 23:12:45.604435 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3338 23:12:45.607239 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3339 23:12:45.607321 ==
3340 23:12:45.610341 Dram Type= 6, Freq= 0, CH_1, rank 0
3341 23:12:45.613757 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3342 23:12:45.613843 ==
3343 23:12:45.626222 TX Vref=22, minBit 10, minWin=24, winSum=412
3344 23:12:45.630156 TX Vref=24, minBit 8, minWin=25, winSum=421
3345 23:12:45.633362 TX Vref=26, minBit 8, minWin=25, winSum=426
3346 23:12:45.636448 TX Vref=28, minBit 8, minWin=25, winSum=431
3347 23:12:45.640103 TX Vref=30, minBit 8, minWin=25, winSum=428
3348 23:12:45.646453 TX Vref=32, minBit 8, minWin=25, winSum=425
3349 23:12:45.649553 [TxChooseVref] Worse bit 8, Min win 25, Win sum 431, Final Vref 28
3350 23:12:45.649636
3351 23:12:45.652857 Final TX Range 1 Vref 28
3352 23:12:45.652965
3353 23:12:45.653059 ==
3354 23:12:45.656487 Dram Type= 6, Freq= 0, CH_1, rank 0
3355 23:12:45.659497 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3356 23:12:45.662723 ==
3357 23:12:45.662805
3358 23:12:45.662868
3359 23:12:45.662927 TX Vref Scan disable
3360 23:12:45.666032 == TX Byte 0 ==
3361 23:12:45.670021 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
3362 23:12:45.676393 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
3363 23:12:45.676475 == TX Byte 1 ==
3364 23:12:45.679646 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3365 23:12:45.686550 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3366 23:12:45.686632
3367 23:12:45.686696 [DATLAT]
3368 23:12:45.686755 Freq=1200, CH1 RK0
3369 23:12:45.686813
3370 23:12:45.689832 DATLAT Default: 0xd
3371 23:12:45.692671 0, 0xFFFF, sum = 0
3372 23:12:45.692754 1, 0xFFFF, sum = 0
3373 23:12:45.695831 2, 0xFFFF, sum = 0
3374 23:12:45.695912 3, 0xFFFF, sum = 0
3375 23:12:45.699959 4, 0xFFFF, sum = 0
3376 23:12:45.700041 5, 0xFFFF, sum = 0
3377 23:12:45.702483 6, 0xFFFF, sum = 0
3378 23:12:45.702565 7, 0xFFFF, sum = 0
3379 23:12:45.706384 8, 0xFFFF, sum = 0
3380 23:12:45.706466 9, 0xFFFF, sum = 0
3381 23:12:45.709213 10, 0xFFFF, sum = 0
3382 23:12:45.709296 11, 0xFFFF, sum = 0
3383 23:12:45.712495 12, 0x0, sum = 1
3384 23:12:45.712577 13, 0x0, sum = 2
3385 23:12:45.715664 14, 0x0, sum = 3
3386 23:12:45.715781 15, 0x0, sum = 4
3387 23:12:45.719642 best_step = 13
3388 23:12:45.719733
3389 23:12:45.719797 ==
3390 23:12:45.722411 Dram Type= 6, Freq= 0, CH_1, rank 0
3391 23:12:45.725785 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3392 23:12:45.725867 ==
3393 23:12:45.729647 RX Vref Scan: 1
3394 23:12:45.729728
3395 23:12:45.729790 Set Vref Range= 32 -> 127
3396 23:12:45.729850
3397 23:12:45.732562 RX Vref 32 -> 127, step: 1
3398 23:12:45.732642
3399 23:12:45.735531 RX Delay -21 -> 252, step: 4
3400 23:12:45.735612
3401 23:12:45.739239 Set Vref, RX VrefLevel [Byte0]: 32
3402 23:12:45.742161 [Byte1]: 32
3403 23:12:45.742242
3404 23:12:45.745475 Set Vref, RX VrefLevel [Byte0]: 33
3405 23:12:45.748560 [Byte1]: 33
3406 23:12:45.752675
3407 23:12:45.752756 Set Vref, RX VrefLevel [Byte0]: 34
3408 23:12:45.755953 [Byte1]: 34
3409 23:12:45.760660
3410 23:12:45.760740 Set Vref, RX VrefLevel [Byte0]: 35
3411 23:12:45.764783 [Byte1]: 35
3412 23:12:45.768844
3413 23:12:45.768924 Set Vref, RX VrefLevel [Byte0]: 36
3414 23:12:45.771928 [Byte1]: 36
3415 23:12:45.776826
3416 23:12:45.776905 Set Vref, RX VrefLevel [Byte0]: 37
3417 23:12:45.779626 [Byte1]: 37
3418 23:12:45.785493
3419 23:12:45.785573 Set Vref, RX VrefLevel [Byte0]: 38
3420 23:12:45.788020 [Byte1]: 38
3421 23:12:45.792093
3422 23:12:45.792172 Set Vref, RX VrefLevel [Byte0]: 39
3423 23:12:45.795932 [Byte1]: 39
3424 23:12:45.800497
3425 23:12:45.800577 Set Vref, RX VrefLevel [Byte0]: 40
3426 23:12:45.803532 [Byte1]: 40
3427 23:12:45.808312
3428 23:12:45.808392 Set Vref, RX VrefLevel [Byte0]: 41
3429 23:12:45.811947 [Byte1]: 41
3430 23:12:45.816728
3431 23:12:45.816811 Set Vref, RX VrefLevel [Byte0]: 42
3432 23:12:45.819970 [Byte1]: 42
3433 23:12:45.824170
3434 23:12:45.824250 Set Vref, RX VrefLevel [Byte0]: 43
3435 23:12:45.827718 [Byte1]: 43
3436 23:12:45.832156
3437 23:12:45.832237 Set Vref, RX VrefLevel [Byte0]: 44
3438 23:12:45.835326 [Byte1]: 44
3439 23:12:45.839914
3440 23:12:45.839995 Set Vref, RX VrefLevel [Byte0]: 45
3441 23:12:45.843272 [Byte1]: 45
3442 23:12:45.847990
3443 23:12:45.848070 Set Vref, RX VrefLevel [Byte0]: 46
3444 23:12:45.850906 [Byte1]: 46
3445 23:12:45.855892
3446 23:12:45.855973 Set Vref, RX VrefLevel [Byte0]: 47
3447 23:12:45.859054 [Byte1]: 47
3448 23:12:45.863434
3449 23:12:45.863515 Set Vref, RX VrefLevel [Byte0]: 48
3450 23:12:45.867030 [Byte1]: 48
3451 23:12:45.871938
3452 23:12:45.872020 Set Vref, RX VrefLevel [Byte0]: 49
3453 23:12:45.874754 [Byte1]: 49
3454 23:12:45.879600
3455 23:12:45.879707 Set Vref, RX VrefLevel [Byte0]: 50
3456 23:12:45.882619 [Byte1]: 50
3457 23:12:45.888771
3458 23:12:45.888853 Set Vref, RX VrefLevel [Byte0]: 51
3459 23:12:45.890660 [Byte1]: 51
3460 23:12:45.895117
3461 23:12:45.895206 Set Vref, RX VrefLevel [Byte0]: 52
3462 23:12:45.898845 [Byte1]: 52
3463 23:12:45.903389
3464 23:12:45.903470 Set Vref, RX VrefLevel [Byte0]: 53
3465 23:12:45.906611 [Byte1]: 53
3466 23:12:45.911447
3467 23:12:45.911528 Set Vref, RX VrefLevel [Byte0]: 54
3468 23:12:45.914382 [Byte1]: 54
3469 23:12:45.919442
3470 23:12:45.919523 Set Vref, RX VrefLevel [Byte0]: 55
3471 23:12:45.922218 [Byte1]: 55
3472 23:12:45.927351
3473 23:12:45.927433 Set Vref, RX VrefLevel [Byte0]: 56
3474 23:12:45.930535 [Byte1]: 56
3475 23:12:45.935199
3476 23:12:45.935280 Set Vref, RX VrefLevel [Byte0]: 57
3477 23:12:45.938037 [Byte1]: 57
3478 23:12:45.942950
3479 23:12:45.943031 Set Vref, RX VrefLevel [Byte0]: 58
3480 23:12:45.946226 [Byte1]: 58
3481 23:12:45.950871
3482 23:12:45.950952 Set Vref, RX VrefLevel [Byte0]: 59
3483 23:12:45.953891 [Byte1]: 59
3484 23:12:45.958559
3485 23:12:45.958641 Set Vref, RX VrefLevel [Byte0]: 60
3486 23:12:45.961692 [Byte1]: 60
3487 23:12:45.966454
3488 23:12:45.966535 Set Vref, RX VrefLevel [Byte0]: 61
3489 23:12:45.969682 [Byte1]: 61
3490 23:12:45.974424
3491 23:12:45.974505 Set Vref, RX VrefLevel [Byte0]: 62
3492 23:12:45.977960 [Byte1]: 62
3493 23:12:45.982113
3494 23:12:45.982198 Set Vref, RX VrefLevel [Byte0]: 63
3495 23:12:45.985900 [Byte1]: 63
3496 23:12:45.990048
3497 23:12:45.990129 Set Vref, RX VrefLevel [Byte0]: 64
3498 23:12:45.993776 [Byte1]: 64
3499 23:12:45.998177
3500 23:12:45.998259 Set Vref, RX VrefLevel [Byte0]: 65
3501 23:12:46.002018 [Byte1]: 65
3502 23:12:46.006371
3503 23:12:46.006452 Set Vref, RX VrefLevel [Byte0]: 66
3504 23:12:46.009374 [Byte1]: 66
3505 23:12:46.014975
3506 23:12:46.015055 Set Vref, RX VrefLevel [Byte0]: 67
3507 23:12:46.017584 [Byte1]: 67
3508 23:12:46.021822
3509 23:12:46.021902 Final RX Vref Byte 0 = 50 to rank0
3510 23:12:46.026043 Final RX Vref Byte 1 = 51 to rank0
3511 23:12:46.028891 Final RX Vref Byte 0 = 50 to rank1
3512 23:12:46.031959 Final RX Vref Byte 1 = 51 to rank1==
3513 23:12:46.035493 Dram Type= 6, Freq= 0, CH_1, rank 0
3514 23:12:46.042076 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3515 23:12:46.042157 ==
3516 23:12:46.042221 DQS Delay:
3517 23:12:46.042280 DQS0 = 0, DQS1 = 0
3518 23:12:46.045745 DQM Delay:
3519 23:12:46.045825 DQM0 = 115, DQM1 = 109
3520 23:12:46.048541 DQ Delay:
3521 23:12:46.051990 DQ0 =120, DQ1 =110, DQ2 =106, DQ3 =112
3522 23:12:46.055484 DQ4 =114, DQ5 =126, DQ6 =124, DQ7 =112
3523 23:12:46.058590 DQ8 =98, DQ9 =102, DQ10 =112, DQ11 =98
3524 23:12:46.061905 DQ12 =116, DQ13 =114, DQ14 =118, DQ15 =118
3525 23:12:46.061985
3526 23:12:46.062048
3527 23:12:46.068187 [DQSOSCAuto] RK0, (LSB)MR18= 0xf3, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 410 ps
3528 23:12:46.071453 CH1 RK0: MR19=403, MR18=F3
3529 23:12:46.078725 CH1_RK0: MR19=0x403, MR18=0xF3, DQSOSC=410, MR23=63, INC=39, DEC=26
3530 23:12:46.078806
3531 23:12:46.081514 ----->DramcWriteLeveling(PI) begin...
3532 23:12:46.081596 ==
3533 23:12:46.084836 Dram Type= 6, Freq= 0, CH_1, rank 1
3534 23:12:46.088391 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3535 23:12:46.091517 ==
3536 23:12:46.091596 Write leveling (Byte 0): 24 => 24
3537 23:12:46.094737 Write leveling (Byte 1): 28 => 28
3538 23:12:46.097917 DramcWriteLeveling(PI) end<-----
3539 23:12:46.097997
3540 23:12:46.098061 ==
3541 23:12:46.101509 Dram Type= 6, Freq= 0, CH_1, rank 1
3542 23:12:46.108215 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3543 23:12:46.108296 ==
3544 23:12:46.110976 [Gating] SW mode calibration
3545 23:12:46.117313 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3546 23:12:46.120821 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3547 23:12:46.127576 0 15 0 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
3548 23:12:46.130629 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3549 23:12:46.134337 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3550 23:12:46.140684 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3551 23:12:46.144000 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3552 23:12:46.147572 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3553 23:12:46.153808 0 15 24 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 0)
3554 23:12:46.158463 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
3555 23:12:46.160599 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3556 23:12:46.167296 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3557 23:12:46.170845 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3558 23:12:46.174208 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3559 23:12:46.180369 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3560 23:12:46.183468 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3561 23:12:46.187529 1 0 24 | B1->B0 | 3f3f 2626 | 0 0 | (0 0) (0 0)
3562 23:12:46.193731 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3563 23:12:46.196892 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3564 23:12:46.200223 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3565 23:12:46.206986 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3566 23:12:46.210344 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3567 23:12:46.213651 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3568 23:12:46.219988 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3569 23:12:46.223829 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3570 23:12:46.226974 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3571 23:12:46.233448 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3572 23:12:46.236394 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3573 23:12:46.239575 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3574 23:12:46.247055 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3575 23:12:46.250096 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3576 23:12:46.253274 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3577 23:12:46.256935 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3578 23:12:46.262818 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3579 23:12:46.266537 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3580 23:12:46.269986 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3581 23:12:46.276829 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3582 23:12:46.279490 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3583 23:12:46.286372 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3584 23:12:46.290092 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3585 23:12:46.292508 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3586 23:12:46.299405 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3587 23:12:46.302358 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3588 23:12:46.306080 Total UI for P1: 0, mck2ui 16
3589 23:12:46.309151 best dqsien dly found for B0: ( 1, 3, 28)
3590 23:12:46.312388 Total UI for P1: 0, mck2ui 16
3591 23:12:46.315587 best dqsien dly found for B1: ( 1, 3, 26)
3592 23:12:46.319056 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3593 23:12:46.322702 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3594 23:12:46.322783
3595 23:12:46.325432 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3596 23:12:46.329141 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3597 23:12:46.332304 [Gating] SW calibration Done
3598 23:12:46.332385 ==
3599 23:12:46.335806 Dram Type= 6, Freq= 0, CH_1, rank 1
3600 23:12:46.338887 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3601 23:12:46.338969 ==
3602 23:12:46.342361 RX Vref Scan: 0
3603 23:12:46.342441
3604 23:12:46.345701 RX Vref 0 -> 0, step: 1
3605 23:12:46.345792
3606 23:12:46.345856 RX Delay -40 -> 252, step: 8
3607 23:12:46.352193 iDelay=208, Bit 0, Center 123 (56 ~ 191) 136
3608 23:12:46.355291 iDelay=208, Bit 1, Center 107 (32 ~ 183) 152
3609 23:12:46.358925 iDelay=208, Bit 2, Center 103 (32 ~ 175) 144
3610 23:12:46.362198 iDelay=208, Bit 3, Center 111 (40 ~ 183) 144
3611 23:12:46.365212 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3612 23:12:46.371609 iDelay=208, Bit 5, Center 127 (56 ~ 199) 144
3613 23:12:46.375346 iDelay=208, Bit 6, Center 131 (56 ~ 207) 152
3614 23:12:46.378443 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3615 23:12:46.382247 iDelay=208, Bit 8, Center 95 (24 ~ 167) 144
3616 23:12:46.385275 iDelay=208, Bit 9, Center 95 (24 ~ 167) 144
3617 23:12:46.391741 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3618 23:12:46.395138 iDelay=208, Bit 11, Center 99 (32 ~ 167) 136
3619 23:12:46.398393 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3620 23:12:46.402148 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3621 23:12:46.408247 iDelay=208, Bit 14, Center 115 (40 ~ 191) 152
3622 23:12:46.411414 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3623 23:12:46.411495 ==
3624 23:12:46.415310 Dram Type= 6, Freq= 0, CH_1, rank 1
3625 23:12:46.418045 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3626 23:12:46.418126 ==
3627 23:12:46.421431 DQS Delay:
3628 23:12:46.421513 DQS0 = 0, DQS1 = 0
3629 23:12:46.421578 DQM Delay:
3630 23:12:46.424749 DQM0 = 116, DQM1 = 109
3631 23:12:46.424856 DQ Delay:
3632 23:12:46.428485 DQ0 =123, DQ1 =107, DQ2 =103, DQ3 =111
3633 23:12:46.431594 DQ4 =115, DQ5 =127, DQ6 =131, DQ7 =115
3634 23:12:46.434497 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =99
3635 23:12:46.441215 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3636 23:12:46.441297
3637 23:12:46.441360
3638 23:12:46.441418 ==
3639 23:12:46.444250 Dram Type= 6, Freq= 0, CH_1, rank 1
3640 23:12:46.448048 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3641 23:12:46.448130 ==
3642 23:12:46.448193
3643 23:12:46.448251
3644 23:12:46.450978 TX Vref Scan disable
3645 23:12:46.451058 == TX Byte 0 ==
3646 23:12:46.457745 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3647 23:12:46.461271 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3648 23:12:46.461351 == TX Byte 1 ==
3649 23:12:46.467941 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3650 23:12:46.470625 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3651 23:12:46.470706 ==
3652 23:12:46.474228 Dram Type= 6, Freq= 0, CH_1, rank 1
3653 23:12:46.477400 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3654 23:12:46.477481 ==
3655 23:12:46.490627 TX Vref=22, minBit 2, minWin=26, winSum=428
3656 23:12:46.493502 TX Vref=24, minBit 8, minWin=26, winSum=432
3657 23:12:46.497293 TX Vref=26, minBit 8, minWin=26, winSum=433
3658 23:12:46.500362 TX Vref=28, minBit 8, minWin=26, winSum=434
3659 23:12:46.503597 TX Vref=30, minBit 8, minWin=26, winSum=435
3660 23:12:46.511196 TX Vref=32, minBit 8, minWin=26, winSum=433
3661 23:12:46.513375 [TxChooseVref] Worse bit 8, Min win 26, Win sum 435, Final Vref 30
3662 23:12:46.513472
3663 23:12:46.517178 Final TX Range 1 Vref 30
3664 23:12:46.517259
3665 23:12:46.517323 ==
3666 23:12:46.520394 Dram Type= 6, Freq= 0, CH_1, rank 1
3667 23:12:46.523537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3668 23:12:46.527459 ==
3669 23:12:46.527540
3670 23:12:46.527603
3671 23:12:46.527661 TX Vref Scan disable
3672 23:12:46.530192 == TX Byte 0 ==
3673 23:12:46.533292 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3674 23:12:46.540274 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3675 23:12:46.540355 == TX Byte 1 ==
3676 23:12:46.543811 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3677 23:12:46.550478 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3678 23:12:46.550563
3679 23:12:46.550627 [DATLAT]
3680 23:12:46.550686 Freq=1200, CH1 RK1
3681 23:12:46.550743
3682 23:12:46.553432 DATLAT Default: 0xd
3683 23:12:46.556458 0, 0xFFFF, sum = 0
3684 23:12:46.556541 1, 0xFFFF, sum = 0
3685 23:12:46.560018 2, 0xFFFF, sum = 0
3686 23:12:46.560099 3, 0xFFFF, sum = 0
3687 23:12:46.563235 4, 0xFFFF, sum = 0
3688 23:12:46.563317 5, 0xFFFF, sum = 0
3689 23:12:46.566591 6, 0xFFFF, sum = 0
3690 23:12:46.566673 7, 0xFFFF, sum = 0
3691 23:12:46.570030 8, 0xFFFF, sum = 0
3692 23:12:46.570112 9, 0xFFFF, sum = 0
3693 23:12:46.572998 10, 0xFFFF, sum = 0
3694 23:12:46.573080 11, 0xFFFF, sum = 0
3695 23:12:46.575993 12, 0x0, sum = 1
3696 23:12:46.576074 13, 0x0, sum = 2
3697 23:12:46.580788 14, 0x0, sum = 3
3698 23:12:46.580870 15, 0x0, sum = 4
3699 23:12:46.583144 best_step = 13
3700 23:12:46.583224
3701 23:12:46.583287 ==
3702 23:12:46.586290 Dram Type= 6, Freq= 0, CH_1, rank 1
3703 23:12:46.589294 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3704 23:12:46.589377 ==
3705 23:12:46.592918 RX Vref Scan: 0
3706 23:12:46.593000
3707 23:12:46.593063 RX Vref 0 -> 0, step: 1
3708 23:12:46.593122
3709 23:12:46.596249 RX Delay -21 -> 252, step: 4
3710 23:12:46.603102 iDelay=199, Bit 0, Center 118 (51 ~ 186) 136
3711 23:12:46.606280 iDelay=199, Bit 1, Center 110 (43 ~ 178) 136
3712 23:12:46.609022 iDelay=199, Bit 2, Center 106 (43 ~ 170) 128
3713 23:12:46.612300 iDelay=199, Bit 3, Center 112 (47 ~ 178) 132
3714 23:12:46.615888 iDelay=199, Bit 4, Center 114 (47 ~ 182) 136
3715 23:12:46.622486 iDelay=199, Bit 5, Center 128 (63 ~ 194) 132
3716 23:12:46.626456 iDelay=199, Bit 6, Center 130 (63 ~ 198) 136
3717 23:12:46.628682 iDelay=199, Bit 7, Center 116 (51 ~ 182) 132
3718 23:12:46.632196 iDelay=199, Bit 8, Center 96 (31 ~ 162) 132
3719 23:12:46.635439 iDelay=199, Bit 9, Center 100 (35 ~ 166) 132
3720 23:12:46.641872 iDelay=199, Bit 10, Center 110 (43 ~ 178) 136
3721 23:12:46.646020 iDelay=199, Bit 11, Center 100 (35 ~ 166) 132
3722 23:12:46.648675 iDelay=199, Bit 12, Center 118 (51 ~ 186) 136
3723 23:12:46.651861 iDelay=199, Bit 13, Center 118 (51 ~ 186) 136
3724 23:12:46.658936 iDelay=199, Bit 14, Center 116 (51 ~ 182) 132
3725 23:12:46.661922 iDelay=199, Bit 15, Center 118 (51 ~ 186) 136
3726 23:12:46.662004 ==
3727 23:12:46.665211 Dram Type= 6, Freq= 0, CH_1, rank 1
3728 23:12:46.668571 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3729 23:12:46.668680 ==
3730 23:12:46.671925 DQS Delay:
3731 23:12:46.672006 DQS0 = 0, DQS1 = 0
3732 23:12:46.672070 DQM Delay:
3733 23:12:46.675011 DQM0 = 116, DQM1 = 109
3734 23:12:46.675092 DQ Delay:
3735 23:12:46.678707 DQ0 =118, DQ1 =110, DQ2 =106, DQ3 =112
3736 23:12:46.682244 DQ4 =114, DQ5 =128, DQ6 =130, DQ7 =116
3737 23:12:46.685558 DQ8 =96, DQ9 =100, DQ10 =110, DQ11 =100
3738 23:12:46.691534 DQ12 =118, DQ13 =118, DQ14 =116, DQ15 =118
3739 23:12:46.691640
3740 23:12:46.691759
3741 23:12:46.698326 [DQSOSCAuto] RK1, (LSB)MR18= 0xf4ef, (MSB)MR19= 0x303, tDQSOscB0 = 417 ps tDQSOscB1 = 415 ps
3742 23:12:46.702017 CH1 RK1: MR19=303, MR18=F4EF
3743 23:12:46.707990 CH1_RK1: MR19=0x303, MR18=0xF4EF, DQSOSC=415, MR23=63, INC=38, DEC=25
3744 23:12:46.711081 [RxdqsGatingPostProcess] freq 1200
3745 23:12:46.714762 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3746 23:12:46.718123 best DQS0 dly(2T, 0.5T) = (0, 11)
3747 23:12:46.721455 best DQS1 dly(2T, 0.5T) = (0, 11)
3748 23:12:46.724694 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3749 23:12:46.728045 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3750 23:12:46.731082 best DQS0 dly(2T, 0.5T) = (0, 11)
3751 23:12:46.734886 best DQS1 dly(2T, 0.5T) = (0, 11)
3752 23:12:46.738065 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3753 23:12:46.742554 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3754 23:12:46.744763 Pre-setting of DQS Precalculation
3755 23:12:46.747503 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3756 23:12:46.758074 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3757 23:12:46.764807 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3758 23:12:46.764889
3759 23:12:46.764952
3760 23:12:46.767461 [Calibration Summary] 2400 Mbps
3761 23:12:46.767568 CH 0, Rank 0
3762 23:12:46.770820 SW Impedance : PASS
3763 23:12:46.770901 DUTY Scan : NO K
3764 23:12:46.773940 ZQ Calibration : PASS
3765 23:12:46.777635 Jitter Meter : NO K
3766 23:12:46.777716 CBT Training : PASS
3767 23:12:46.780837 Write leveling : PASS
3768 23:12:46.783971 RX DQS gating : PASS
3769 23:12:46.784051 RX DQ/DQS(RDDQC) : PASS
3770 23:12:46.787496 TX DQ/DQS : PASS
3771 23:12:46.790510 RX DATLAT : PASS
3772 23:12:46.790590 RX DQ/DQS(Engine): PASS
3773 23:12:46.794156 TX OE : NO K
3774 23:12:46.794237 All Pass.
3775 23:12:46.794300
3776 23:12:46.797455 CH 0, Rank 1
3777 23:12:46.797562 SW Impedance : PASS
3778 23:12:46.800646 DUTY Scan : NO K
3779 23:12:46.803812 ZQ Calibration : PASS
3780 23:12:46.803893 Jitter Meter : NO K
3781 23:12:46.807997 CBT Training : PASS
3782 23:12:46.810846 Write leveling : PASS
3783 23:12:46.810927 RX DQS gating : PASS
3784 23:12:46.813692 RX DQ/DQS(RDDQC) : PASS
3785 23:12:46.817482 TX DQ/DQS : PASS
3786 23:12:46.817563 RX DATLAT : PASS
3787 23:12:46.820667 RX DQ/DQS(Engine): PASS
3788 23:12:46.823837 TX OE : NO K
3789 23:12:46.823917 All Pass.
3790 23:12:46.823980
3791 23:12:46.824039 CH 1, Rank 0
3792 23:12:46.827254 SW Impedance : PASS
3793 23:12:46.830740 DUTY Scan : NO K
3794 23:12:46.830820 ZQ Calibration : PASS
3795 23:12:46.833581 Jitter Meter : NO K
3796 23:12:46.833661 CBT Training : PASS
3797 23:12:46.836734 Write leveling : PASS
3798 23:12:46.840377 RX DQS gating : PASS
3799 23:12:46.840457 RX DQ/DQS(RDDQC) : PASS
3800 23:12:46.843692 TX DQ/DQS : PASS
3801 23:12:46.847559 RX DATLAT : PASS
3802 23:12:46.847639 RX DQ/DQS(Engine): PASS
3803 23:12:46.850197 TX OE : NO K
3804 23:12:46.850277 All Pass.
3805 23:12:46.850340
3806 23:12:46.853659 CH 1, Rank 1
3807 23:12:46.853739 SW Impedance : PASS
3808 23:12:46.856683 DUTY Scan : NO K
3809 23:12:46.860141 ZQ Calibration : PASS
3810 23:12:46.860221 Jitter Meter : NO K
3811 23:12:46.863532 CBT Training : PASS
3812 23:12:46.866889 Write leveling : PASS
3813 23:12:46.866969 RX DQS gating : PASS
3814 23:12:46.869768 RX DQ/DQS(RDDQC) : PASS
3815 23:12:46.873295 TX DQ/DQS : PASS
3816 23:12:46.873376 RX DATLAT : PASS
3817 23:12:46.876440 RX DQ/DQS(Engine): PASS
3818 23:12:46.880665 TX OE : NO K
3819 23:12:46.880745 All Pass.
3820 23:12:46.880808
3821 23:12:46.883152 DramC Write-DBI off
3822 23:12:46.883232 PER_BANK_REFRESH: Hybrid Mode
3823 23:12:46.886339 TX_TRACKING: ON
3824 23:12:46.892946 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3825 23:12:46.900152 [FAST_K] Save calibration result to emmc
3826 23:12:46.902825 dramc_set_vcore_voltage set vcore to 650000
3827 23:12:46.902906 Read voltage for 600, 5
3828 23:12:46.906306 Vio18 = 0
3829 23:12:46.906385 Vcore = 650000
3830 23:12:46.906448 Vdram = 0
3831 23:12:46.909620 Vddq = 0
3832 23:12:46.909701 Vmddr = 0
3833 23:12:46.912674 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3834 23:12:46.919658 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3835 23:12:46.923487 MEM_TYPE=3, freq_sel=19
3836 23:12:46.926100 sv_algorithm_assistance_LP4_1600
3837 23:12:46.929016 ============ PULL DRAM RESETB DOWN ============
3838 23:12:46.932648 ========== PULL DRAM RESETB DOWN end =========
3839 23:12:46.939394 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3840 23:12:46.942772 ===================================
3841 23:12:46.942853 LPDDR4 DRAM CONFIGURATION
3842 23:12:46.945831 ===================================
3843 23:12:46.949158 EX_ROW_EN[0] = 0x0
3844 23:12:46.949239 EX_ROW_EN[1] = 0x0
3845 23:12:46.952557 LP4Y_EN = 0x0
3846 23:12:46.955942 WORK_FSP = 0x0
3847 23:12:46.956023 WL = 0x2
3848 23:12:46.959043 RL = 0x2
3849 23:12:46.959123 BL = 0x2
3850 23:12:46.962382 RPST = 0x0
3851 23:12:46.962462 RD_PRE = 0x0
3852 23:12:46.965908 WR_PRE = 0x1
3853 23:12:46.965988 WR_PST = 0x0
3854 23:12:46.968946 DBI_WR = 0x0
3855 23:12:46.969029 DBI_RD = 0x0
3856 23:12:46.972521 OTF = 0x1
3857 23:12:46.975429 ===================================
3858 23:12:46.978781 ===================================
3859 23:12:46.978862 ANA top config
3860 23:12:46.981977 ===================================
3861 23:12:46.985968 DLL_ASYNC_EN = 0
3862 23:12:46.988975 ALL_SLAVE_EN = 1
3863 23:12:46.991949 NEW_RANK_MODE = 1
3864 23:12:46.992032 DLL_IDLE_MODE = 1
3865 23:12:46.995021 LP45_APHY_COMB_EN = 1
3866 23:12:46.998401 TX_ODT_DIS = 1
3867 23:12:47.002023 NEW_8X_MODE = 1
3868 23:12:47.005121 ===================================
3869 23:12:47.008523 ===================================
3870 23:12:47.011614 data_rate = 1200
3871 23:12:47.011734 CKR = 1
3872 23:12:47.014889 DQ_P2S_RATIO = 8
3873 23:12:47.018601 ===================================
3874 23:12:47.021983 CA_P2S_RATIO = 8
3875 23:12:47.024778 DQ_CA_OPEN = 0
3876 23:12:47.028188 DQ_SEMI_OPEN = 0
3877 23:12:47.031477 CA_SEMI_OPEN = 0
3878 23:12:47.031559 CA_FULL_RATE = 0
3879 23:12:47.035140 DQ_CKDIV4_EN = 1
3880 23:12:47.038390 CA_CKDIV4_EN = 1
3881 23:12:47.041575 CA_PREDIV_EN = 0
3882 23:12:47.044922 PH8_DLY = 0
3883 23:12:47.048269 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3884 23:12:47.048350 DQ_AAMCK_DIV = 4
3885 23:12:47.050934 CA_AAMCK_DIV = 4
3886 23:12:47.054566 CA_ADMCK_DIV = 4
3887 23:12:47.057601 DQ_TRACK_CA_EN = 0
3888 23:12:47.061331 CA_PICK = 600
3889 23:12:47.064388 CA_MCKIO = 600
3890 23:12:47.067705 MCKIO_SEMI = 0
3891 23:12:47.070780 PLL_FREQ = 2288
3892 23:12:47.070860 DQ_UI_PI_RATIO = 32
3893 23:12:47.073999 CA_UI_PI_RATIO = 0
3894 23:12:47.077236 ===================================
3895 23:12:47.081197 ===================================
3896 23:12:47.083704 memory_type:LPDDR4
3897 23:12:47.087022 GP_NUM : 10
3898 23:12:47.087103 SRAM_EN : 1
3899 23:12:47.091042 MD32_EN : 0
3900 23:12:47.094182 ===================================
3901 23:12:47.097152 [ANA_INIT] >>>>>>>>>>>>>>
3902 23:12:47.097233 <<<<<< [CONFIGURE PHASE]: ANA_TX
3903 23:12:47.100918 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3904 23:12:47.104094 ===================================
3905 23:12:47.107163 data_rate = 1200,PCW = 0X5800
3906 23:12:47.110298 ===================================
3907 23:12:47.113726 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3908 23:12:47.120230 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3909 23:12:47.127019 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3910 23:12:47.131321 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3911 23:12:47.133599 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3912 23:12:47.137485 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3913 23:12:47.140145 [ANA_INIT] flow start
3914 23:12:47.140226 [ANA_INIT] PLL >>>>>>>>
3915 23:12:47.143506 [ANA_INIT] PLL <<<<<<<<
3916 23:12:47.146744 [ANA_INIT] MIDPI >>>>>>>>
3917 23:12:47.149945 [ANA_INIT] MIDPI <<<<<<<<
3918 23:12:47.150025 [ANA_INIT] DLL >>>>>>>>
3919 23:12:47.153029 [ANA_INIT] flow end
3920 23:12:47.156801 ============ LP4 DIFF to SE enter ============
3921 23:12:47.159953 ============ LP4 DIFF to SE exit ============
3922 23:12:47.162879 [ANA_INIT] <<<<<<<<<<<<<
3923 23:12:47.167451 [Flow] Enable top DCM control >>>>>
3924 23:12:47.169503 [Flow] Enable top DCM control <<<<<
3925 23:12:47.173404 Enable DLL master slave shuffle
3926 23:12:47.179478 ==============================================================
3927 23:12:47.179559 Gating Mode config
3928 23:12:47.186188 ==============================================================
3929 23:12:47.186269 Config description:
3930 23:12:47.195872 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3931 23:12:47.202818 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3932 23:12:47.209267 SELPH_MODE 0: By rank 1: By Phase
3933 23:12:47.212553 ==============================================================
3934 23:12:47.216247 GAT_TRACK_EN = 1
3935 23:12:47.219388 RX_GATING_MODE = 2
3936 23:12:47.222346 RX_GATING_TRACK_MODE = 2
3937 23:12:47.225913 SELPH_MODE = 1
3938 23:12:47.229071 PICG_EARLY_EN = 1
3939 23:12:47.232338 VALID_LAT_VALUE = 1
3940 23:12:47.239321 ==============================================================
3941 23:12:47.242435 Enter into Gating configuration >>>>
3942 23:12:47.245734 Exit from Gating configuration <<<<
3943 23:12:47.249128 Enter into DVFS_PRE_config >>>>>
3944 23:12:47.258893 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3945 23:12:47.262565 Exit from DVFS_PRE_config <<<<<
3946 23:12:47.265294 Enter into PICG configuration >>>>
3947 23:12:47.268576 Exit from PICG configuration <<<<
3948 23:12:47.272131 [RX_INPUT] configuration >>>>>
3949 23:12:47.272212 [RX_INPUT] configuration <<<<<
3950 23:12:47.278391 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3951 23:12:47.285252 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3952 23:12:47.292644 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3953 23:12:47.295153 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3954 23:12:47.302100 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3955 23:12:47.308655 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3956 23:12:47.312191 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3957 23:12:47.318544 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3958 23:12:47.321371 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3959 23:12:47.324803 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3960 23:12:47.329091 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3961 23:12:47.335081 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3962 23:12:47.338709 ===================================
3963 23:12:47.338791 LPDDR4 DRAM CONFIGURATION
3964 23:12:47.340977 ===================================
3965 23:12:47.344235 EX_ROW_EN[0] = 0x0
3966 23:12:47.347638 EX_ROW_EN[1] = 0x0
3967 23:12:47.347729 LP4Y_EN = 0x0
3968 23:12:47.351426 WORK_FSP = 0x0
3969 23:12:47.351507 WL = 0x2
3970 23:12:47.354512 RL = 0x2
3971 23:12:47.354593 BL = 0x2
3972 23:12:47.357575 RPST = 0x0
3973 23:12:47.357656 RD_PRE = 0x0
3974 23:12:47.360882 WR_PRE = 0x1
3975 23:12:47.360963 WR_PST = 0x0
3976 23:12:47.364064 DBI_WR = 0x0
3977 23:12:47.364144 DBI_RD = 0x0
3978 23:12:47.367600 OTF = 0x1
3979 23:12:47.371003 ===================================
3980 23:12:47.374157 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3981 23:12:47.377492 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3982 23:12:47.384014 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3983 23:12:47.387416 ===================================
3984 23:12:47.390144 LPDDR4 DRAM CONFIGURATION
3985 23:12:47.390232 ===================================
3986 23:12:47.393559 EX_ROW_EN[0] = 0x10
3987 23:12:47.397234 EX_ROW_EN[1] = 0x0
3988 23:12:47.397315 LP4Y_EN = 0x0
3989 23:12:47.400548 WORK_FSP = 0x0
3990 23:12:47.400628 WL = 0x2
3991 23:12:47.403875 RL = 0x2
3992 23:12:47.403955 BL = 0x2
3993 23:12:47.406758 RPST = 0x0
3994 23:12:47.406838 RD_PRE = 0x0
3995 23:12:47.409978 WR_PRE = 0x1
3996 23:12:47.410058 WR_PST = 0x0
3997 23:12:47.413524 DBI_WR = 0x0
3998 23:12:47.413604 DBI_RD = 0x0
3999 23:12:47.416833 OTF = 0x1
4000 23:12:47.419974 ===================================
4001 23:12:47.426596 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
4002 23:12:47.430521 nWR fixed to 30
4003 23:12:47.433140 [ModeRegInit_LP4] CH0 RK0
4004 23:12:47.433220 [ModeRegInit_LP4] CH0 RK1
4005 23:12:47.436872 [ModeRegInit_LP4] CH1 RK0
4006 23:12:47.439945 [ModeRegInit_LP4] CH1 RK1
4007 23:12:47.440026 match AC timing 17
4008 23:12:47.446354 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
4009 23:12:47.449784 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4010 23:12:47.453041 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
4011 23:12:47.459966 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
4012 23:12:47.463000 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
4013 23:12:47.463080 ==
4014 23:12:47.466839 Dram Type= 6, Freq= 0, CH_0, rank 0
4015 23:12:47.469777 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4016 23:12:47.469858 ==
4017 23:12:47.477144 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4018 23:12:47.482849 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4019 23:12:47.486078 [CA 0] Center 36 (6~66) winsize 61
4020 23:12:47.489648 [CA 1] Center 36 (6~66) winsize 61
4021 23:12:47.493425 [CA 2] Center 34 (3~65) winsize 63
4022 23:12:47.496518 [CA 3] Center 34 (3~65) winsize 63
4023 23:12:47.499788 [CA 4] Center 33 (3~64) winsize 62
4024 23:12:47.503143 [CA 5] Center 33 (3~64) winsize 62
4025 23:12:47.503224
4026 23:12:47.505856 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4027 23:12:47.505937
4028 23:12:47.509218 [CATrainingPosCal] consider 1 rank data
4029 23:12:47.513171 u2DelayCellTimex100 = 270/100 ps
4030 23:12:47.515971 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4031 23:12:47.519268 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4032 23:12:47.522552 CA2 delay=34 (3~65),Diff = 1 PI (9 cell)
4033 23:12:47.529272 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4034 23:12:47.532065 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4035 23:12:47.535617 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4036 23:12:47.535735
4037 23:12:47.538800 CA PerBit enable=1, Macro0, CA PI delay=33
4038 23:12:47.538881
4039 23:12:47.542119 [CBTSetCACLKResult] CA Dly = 33
4040 23:12:47.542200 CS Dly: 5 (0~36)
4041 23:12:47.542263 ==
4042 23:12:47.546511 Dram Type= 6, Freq= 0, CH_0, rank 1
4043 23:12:47.552293 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4044 23:12:47.552375 ==
4045 23:12:47.555181 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4046 23:12:47.561955 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4047 23:12:47.565339 [CA 0] Center 36 (6~66) winsize 61
4048 23:12:47.568754 [CA 1] Center 36 (6~66) winsize 61
4049 23:12:47.572382 [CA 2] Center 33 (3~64) winsize 62
4050 23:12:47.575239 [CA 3] Center 33 (3~64) winsize 62
4051 23:12:47.579473 [CA 4] Center 33 (3~64) winsize 62
4052 23:12:47.582501 [CA 5] Center 33 (2~64) winsize 63
4053 23:12:47.582581
4054 23:12:47.586370 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4055 23:12:47.586451
4056 23:12:47.588978 [CATrainingPosCal] consider 2 rank data
4057 23:12:47.592804 u2DelayCellTimex100 = 270/100 ps
4058 23:12:47.595884 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4059 23:12:47.598563 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4060 23:12:47.605059 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4061 23:12:47.608875 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4062 23:12:47.612122 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4063 23:12:47.615773 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4064 23:12:47.615853
4065 23:12:47.618328 CA PerBit enable=1, Macro0, CA PI delay=33
4066 23:12:47.618408
4067 23:12:47.622156 [CBTSetCACLKResult] CA Dly = 33
4068 23:12:47.622237 CS Dly: 5 (0~36)
4069 23:12:47.625263
4070 23:12:47.628800 ----->DramcWriteLeveling(PI) begin...
4071 23:12:47.628881 ==
4072 23:12:47.631976 Dram Type= 6, Freq= 0, CH_0, rank 0
4073 23:12:47.635001 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4074 23:12:47.635081 ==
4075 23:12:47.638333 Write leveling (Byte 0): 32 => 32
4076 23:12:47.641704 Write leveling (Byte 1): 28 => 28
4077 23:12:47.644969 DramcWriteLeveling(PI) end<-----
4078 23:12:47.645050
4079 23:12:47.645114 ==
4080 23:12:47.647998 Dram Type= 6, Freq= 0, CH_0, rank 0
4081 23:12:47.651395 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4082 23:12:47.651476 ==
4083 23:12:47.655531 [Gating] SW mode calibration
4084 23:12:47.661162 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4085 23:12:47.668904 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4086 23:12:47.671444 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4087 23:12:47.674763 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4088 23:12:47.681231 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4089 23:12:47.684553 0 9 12 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
4090 23:12:47.687552 0 9 16 | B1->B0 | 3030 2626 | 0 0 | (0 0) (0 0)
4091 23:12:47.694085 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4092 23:12:47.697547 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4093 23:12:47.701396 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4094 23:12:47.707626 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4095 23:12:47.710951 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4096 23:12:47.714624 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4097 23:12:47.720945 0 10 12 | B1->B0 | 2424 3030 | 0 0 | (0 0) (0 0)
4098 23:12:47.723945 0 10 16 | B1->B0 | 3535 3d3d | 0 0 | (1 1) (0 0)
4099 23:12:47.727187 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4100 23:12:47.734206 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4101 23:12:47.737045 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4102 23:12:47.740414 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4103 23:12:47.747209 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4104 23:12:47.750701 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4105 23:12:47.753776 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4106 23:12:47.760335 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4107 23:12:47.763853 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4108 23:12:47.766706 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4109 23:12:47.773412 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4110 23:12:47.776720 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4111 23:12:47.780597 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4112 23:12:47.786684 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4113 23:12:47.790457 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4114 23:12:47.793498 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4115 23:12:47.800392 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4116 23:12:47.803078 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4117 23:12:47.806381 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4118 23:12:47.813121 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4119 23:12:47.816482 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4120 23:12:47.820099 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4121 23:12:47.827165 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4122 23:12:47.829797 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4123 23:12:47.832799 Total UI for P1: 0, mck2ui 16
4124 23:12:47.836134 best dqsien dly found for B1: ( 0, 13, 14)
4125 23:12:47.839438 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4126 23:12:47.843098 Total UI for P1: 0, mck2ui 16
4127 23:12:47.846727 best dqsien dly found for B0: ( 0, 13, 16)
4128 23:12:47.850600 best DQS0 dly(MCK, UI, PI) = (0, 13, 16)
4129 23:12:47.853540 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4130 23:12:47.853620
4131 23:12:47.859150 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 16)
4132 23:12:47.862493 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4133 23:12:47.865568 [Gating] SW calibration Done
4134 23:12:47.865648 ==
4135 23:12:47.868913 Dram Type= 6, Freq= 0, CH_0, rank 0
4136 23:12:47.873071 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4137 23:12:47.873152 ==
4138 23:12:47.873215 RX Vref Scan: 0
4139 23:12:47.873274
4140 23:12:47.876542 RX Vref 0 -> 0, step: 1
4141 23:12:47.876622
4142 23:12:47.879336 RX Delay -230 -> 252, step: 16
4143 23:12:47.882210 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4144 23:12:47.888764 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4145 23:12:47.892218 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4146 23:12:47.895175 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4147 23:12:47.899022 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
4148 23:12:47.901869 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4149 23:12:47.908760 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4150 23:12:47.911915 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4151 23:12:47.915040 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4152 23:12:47.918867 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4153 23:12:47.925526 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4154 23:12:47.928994 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4155 23:12:47.932358 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4156 23:12:47.934888 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4157 23:12:47.941528 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4158 23:12:47.944899 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4159 23:12:47.944979 ==
4160 23:12:47.948705 Dram Type= 6, Freq= 0, CH_0, rank 0
4161 23:12:47.951804 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4162 23:12:47.951888 ==
4163 23:12:47.954864 DQS Delay:
4164 23:12:47.954944 DQS0 = 0, DQS1 = 0
4165 23:12:47.955026 DQM Delay:
4166 23:12:47.958805 DQM0 = 47, DQM1 = 33
4167 23:12:47.958886 DQ Delay:
4168 23:12:47.961781 DQ0 =41, DQ1 =49, DQ2 =41, DQ3 =41
4169 23:12:47.964765 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4170 23:12:47.968136 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4171 23:12:47.971245 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =41
4172 23:12:47.971325
4173 23:12:47.971388
4174 23:12:47.971445 ==
4175 23:12:47.974406 Dram Type= 6, Freq= 0, CH_0, rank 0
4176 23:12:47.980854 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4177 23:12:47.980935 ==
4178 23:12:47.980999
4179 23:12:47.981057
4180 23:12:47.984411 TX Vref Scan disable
4181 23:12:47.984491 == TX Byte 0 ==
4182 23:12:47.987944 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4183 23:12:47.994188 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4184 23:12:47.994268 == TX Byte 1 ==
4185 23:12:47.998325 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4186 23:12:48.004871 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4187 23:12:48.004952 ==
4188 23:12:48.007207 Dram Type= 6, Freq= 0, CH_0, rank 0
4189 23:12:48.010490 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4190 23:12:48.010572 ==
4191 23:12:48.010635
4192 23:12:48.010694
4193 23:12:48.014072 TX Vref Scan disable
4194 23:12:48.017759 == TX Byte 0 ==
4195 23:12:48.020443 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4196 23:12:48.025113 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4197 23:12:48.027921 == TX Byte 1 ==
4198 23:12:48.031195 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4199 23:12:48.033984 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4200 23:12:48.034064
4201 23:12:48.037188 [DATLAT]
4202 23:12:48.037268 Freq=600, CH0 RK0
4203 23:12:48.037332
4204 23:12:48.040851 DATLAT Default: 0x9
4205 23:12:48.040932 0, 0xFFFF, sum = 0
4206 23:12:48.044138 1, 0xFFFF, sum = 0
4207 23:12:48.044220 2, 0xFFFF, sum = 0
4208 23:12:48.046805 3, 0xFFFF, sum = 0
4209 23:12:48.046886 4, 0xFFFF, sum = 0
4210 23:12:48.050365 5, 0xFFFF, sum = 0
4211 23:12:48.050447 6, 0xFFFF, sum = 0
4212 23:12:48.053574 7, 0xFFFF, sum = 0
4213 23:12:48.053656 8, 0x0, sum = 1
4214 23:12:48.056671 9, 0x0, sum = 2
4215 23:12:48.056753 10, 0x0, sum = 3
4216 23:12:48.060130 11, 0x0, sum = 4
4217 23:12:48.060211 best_step = 9
4218 23:12:48.060275
4219 23:12:48.060333 ==
4220 23:12:48.063436 Dram Type= 6, Freq= 0, CH_0, rank 0
4221 23:12:48.070095 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4222 23:12:48.070176 ==
4223 23:12:48.070239 RX Vref Scan: 1
4224 23:12:48.070297
4225 23:12:48.073666 RX Vref 0 -> 0, step: 1
4226 23:12:48.073746
4227 23:12:48.076424 RX Delay -195 -> 252, step: 8
4228 23:12:48.076505
4229 23:12:48.079757 Set Vref, RX VrefLevel [Byte0]: 61
4230 23:12:48.083040 [Byte1]: 49
4231 23:12:48.083120
4232 23:12:48.086712 Final RX Vref Byte 0 = 61 to rank0
4233 23:12:48.090368 Final RX Vref Byte 1 = 49 to rank0
4234 23:12:48.093515 Final RX Vref Byte 0 = 61 to rank1
4235 23:12:48.096725 Final RX Vref Byte 1 = 49 to rank1==
4236 23:12:48.100260 Dram Type= 6, Freq= 0, CH_0, rank 0
4237 23:12:48.102874 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4238 23:12:48.102954 ==
4239 23:12:48.106736 DQS Delay:
4240 23:12:48.106817 DQS0 = 0, DQS1 = 0
4241 23:12:48.109959 DQM Delay:
4242 23:12:48.110039 DQM0 = 43, DQM1 = 32
4243 23:12:48.110102 DQ Delay:
4244 23:12:48.112896 DQ0 =44, DQ1 =44, DQ2 =40, DQ3 =40
4245 23:12:48.116419 DQ4 =48, DQ5 =32, DQ6 =52, DQ7 =48
4246 23:12:48.120164 DQ8 =24, DQ9 =20, DQ10 =32, DQ11 =24
4247 23:12:48.123077 DQ12 =36, DQ13 =36, DQ14 =44, DQ15 =40
4248 23:12:48.123157
4249 23:12:48.123220
4250 23:12:48.132646 [DQSOSCAuto] RK0, (LSB)MR18= 0x623a, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 391 ps
4251 23:12:48.135911 CH0 RK0: MR19=808, MR18=623A
4252 23:12:48.142505 CH0_RK0: MR19=0x808, MR18=0x623A, DQSOSC=391, MR23=63, INC=171, DEC=114
4253 23:12:48.142587
4254 23:12:48.146035 ----->DramcWriteLeveling(PI) begin...
4255 23:12:48.146117 ==
4256 23:12:48.149134 Dram Type= 6, Freq= 0, CH_0, rank 1
4257 23:12:48.153498 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4258 23:12:48.153578 ==
4259 23:12:48.155867 Write leveling (Byte 0): 33 => 33
4260 23:12:48.159288 Write leveling (Byte 1): 33 => 33
4261 23:12:48.162216 DramcWriteLeveling(PI) end<-----
4262 23:12:48.162297
4263 23:12:48.162359 ==
4264 23:12:48.166039 Dram Type= 6, Freq= 0, CH_0, rank 1
4265 23:12:48.168757 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4266 23:12:48.168838 ==
4267 23:12:48.172326 [Gating] SW mode calibration
4268 23:12:48.178587 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4269 23:12:48.185605 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4270 23:12:48.188692 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4271 23:12:48.192241 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4272 23:12:48.199148 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4273 23:12:48.201973 0 9 12 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 0)
4274 23:12:48.205604 0 9 16 | B1->B0 | 2b2b 2b2b | 1 1 | (1 1) (0 0)
4275 23:12:48.211488 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4276 23:12:48.214912 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4277 23:12:48.218980 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4278 23:12:48.225685 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4279 23:12:48.228522 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4280 23:12:48.231448 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4281 23:12:48.239225 0 10 12 | B1->B0 | 2525 2525 | 0 0 | (0 0) (0 0)
4282 23:12:48.241916 0 10 16 | B1->B0 | 3c3c 4545 | 0 0 | (0 0) (0 0)
4283 23:12:48.244980 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4284 23:12:48.251503 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4285 23:12:48.254488 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4286 23:12:48.257813 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4287 23:12:48.265173 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4288 23:12:48.267855 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4289 23:12:48.271885 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4290 23:12:48.277532 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4291 23:12:48.280849 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4292 23:12:48.284589 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4293 23:12:48.291155 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4294 23:12:48.294261 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4295 23:12:48.297368 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4296 23:12:48.304244 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4297 23:12:48.307620 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4298 23:12:48.311049 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4299 23:12:48.317565 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4300 23:12:48.320767 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4301 23:12:48.324298 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4302 23:12:48.330472 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4303 23:12:48.333681 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4304 23:12:48.337416 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4305 23:12:48.344413 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4306 23:12:48.348044 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4307 23:12:48.350287 Total UI for P1: 0, mck2ui 16
4308 23:12:48.353703 best dqsien dly found for B0: ( 0, 13, 12)
4309 23:12:48.356888 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4310 23:12:48.360443 Total UI for P1: 0, mck2ui 16
4311 23:12:48.363362 best dqsien dly found for B1: ( 0, 13, 14)
4312 23:12:48.366723 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4313 23:12:48.373275 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4314 23:12:48.373355
4315 23:12:48.377205 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4316 23:12:48.380373 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4317 23:12:48.384425 [Gating] SW calibration Done
4318 23:12:48.384505 ==
4319 23:12:48.388541 Dram Type= 6, Freq= 0, CH_0, rank 1
4320 23:12:48.389589 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4321 23:12:48.389669 ==
4322 23:12:48.393137 RX Vref Scan: 0
4323 23:12:48.393230
4324 23:12:48.393353 RX Vref 0 -> 0, step: 1
4325 23:12:48.393439
4326 23:12:48.396558 RX Delay -230 -> 252, step: 16
4327 23:12:48.399661 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4328 23:12:48.406793 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4329 23:12:48.409428 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4330 23:12:48.413169 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4331 23:12:48.415977 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4332 23:12:48.423019 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4333 23:12:48.426753 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4334 23:12:48.429693 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4335 23:12:48.433177 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4336 23:12:48.436799 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4337 23:12:48.442608 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4338 23:12:48.445958 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4339 23:12:48.449466 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4340 23:12:48.452541 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4341 23:12:48.458990 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4342 23:12:48.462525 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4343 23:12:48.462605 ==
4344 23:12:48.465848 Dram Type= 6, Freq= 0, CH_0, rank 1
4345 23:12:48.469434 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4346 23:12:48.469515 ==
4347 23:12:48.472519 DQS Delay:
4348 23:12:48.472614 DQS0 = 0, DQS1 = 0
4349 23:12:48.475597 DQM Delay:
4350 23:12:48.475736 DQM0 = 44, DQM1 = 34
4351 23:12:48.475802 DQ Delay:
4352 23:12:48.478781 DQ0 =41, DQ1 =49, DQ2 =41, DQ3 =41
4353 23:12:48.482011 DQ4 =41, DQ5 =41, DQ6 =49, DQ7 =49
4354 23:12:48.485121 DQ8 =17, DQ9 =17, DQ10 =41, DQ11 =25
4355 23:12:48.489270 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =41
4356 23:12:48.489350
4357 23:12:48.491901
4358 23:12:48.491981 ==
4359 23:12:48.495592 Dram Type= 6, Freq= 0, CH_0, rank 1
4360 23:12:48.499441 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4361 23:12:48.499547 ==
4362 23:12:48.499637
4363 23:12:48.499747
4364 23:12:48.501815 TX Vref Scan disable
4365 23:12:48.501894 == TX Byte 0 ==
4366 23:12:48.508452 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4367 23:12:48.511600 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4368 23:12:48.511735 == TX Byte 1 ==
4369 23:12:48.518853 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4370 23:12:48.521792 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4371 23:12:48.521872 ==
4372 23:12:48.525195 Dram Type= 6, Freq= 0, CH_0, rank 1
4373 23:12:48.528775 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4374 23:12:48.528855 ==
4375 23:12:48.528917
4376 23:12:48.528982
4377 23:12:48.531488 TX Vref Scan disable
4378 23:12:48.534637 == TX Byte 0 ==
4379 23:12:48.538253 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4380 23:12:48.541614 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4381 23:12:48.544777 == TX Byte 1 ==
4382 23:12:48.548175 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4383 23:12:48.554642 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4384 23:12:48.554721
4385 23:12:48.554784 [DATLAT]
4386 23:12:48.554842 Freq=600, CH0 RK1
4387 23:12:48.554898
4388 23:12:48.557930 DATLAT Default: 0x9
4389 23:12:48.558010 0, 0xFFFF, sum = 0
4390 23:12:48.560980 1, 0xFFFF, sum = 0
4391 23:12:48.564319 2, 0xFFFF, sum = 0
4392 23:12:48.564400 3, 0xFFFF, sum = 0
4393 23:12:48.567715 4, 0xFFFF, sum = 0
4394 23:12:48.567796 5, 0xFFFF, sum = 0
4395 23:12:48.570991 6, 0xFFFF, sum = 0
4396 23:12:48.571071 7, 0xFFFF, sum = 0
4397 23:12:48.574367 8, 0x0, sum = 1
4398 23:12:48.574448 9, 0x0, sum = 2
4399 23:12:48.574511 10, 0x0, sum = 3
4400 23:12:48.578060 11, 0x0, sum = 4
4401 23:12:48.578140 best_step = 9
4402 23:12:48.578203
4403 23:12:48.580923 ==
4404 23:12:48.581005 Dram Type= 6, Freq= 0, CH_0, rank 1
4405 23:12:48.587624 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4406 23:12:48.587728 ==
4407 23:12:48.587791 RX Vref Scan: 0
4408 23:12:48.587849
4409 23:12:48.590718 RX Vref 0 -> 0, step: 1
4410 23:12:48.590797
4411 23:12:48.594121 RX Delay -195 -> 252, step: 8
4412 23:12:48.600461 iDelay=205, Bit 0, Center 36 (-115 ~ 188) 304
4413 23:12:48.603719 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4414 23:12:48.607437 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4415 23:12:48.610306 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4416 23:12:48.614207 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4417 23:12:48.620264 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4418 23:12:48.624413 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4419 23:12:48.627266 iDelay=205, Bit 7, Center 52 (-99 ~ 204) 304
4420 23:12:48.630437 iDelay=205, Bit 8, Center 28 (-123 ~ 180) 304
4421 23:12:48.637013 iDelay=205, Bit 9, Center 20 (-131 ~ 172) 304
4422 23:12:48.639853 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4423 23:12:48.643215 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4424 23:12:48.646514 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4425 23:12:48.653316 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4426 23:12:48.657264 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4427 23:12:48.659886 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4428 23:12:48.659966 ==
4429 23:12:48.662799 Dram Type= 6, Freq= 0, CH_0, rank 1
4430 23:12:48.666190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4431 23:12:48.670213 ==
4432 23:12:48.670293 DQS Delay:
4433 23:12:48.670356 DQS0 = 0, DQS1 = 0
4434 23:12:48.672679 DQM Delay:
4435 23:12:48.672758 DQM0 = 41, DQM1 = 37
4436 23:12:48.675931 DQ Delay:
4437 23:12:48.679639 DQ0 =36, DQ1 =44, DQ2 =36, DQ3 =40
4438 23:12:48.679757 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =52
4439 23:12:48.682927 DQ8 =28, DQ9 =20, DQ10 =40, DQ11 =28
4440 23:12:48.689389 DQ12 =44, DQ13 =44, DQ14 =48, DQ15 =44
4441 23:12:48.689469
4442 23:12:48.689531
4443 23:12:48.696059 [DQSOSCAuto] RK1, (LSB)MR18= 0x5d10, (MSB)MR19= 0x808, tDQSOscB0 = 406 ps tDQSOscB1 = 392 ps
4444 23:12:48.699974 CH0 RK1: MR19=808, MR18=5D10
4445 23:12:48.705786 CH0_RK1: MR19=0x808, MR18=0x5D10, DQSOSC=392, MR23=63, INC=170, DEC=113
4446 23:12:48.709107 [RxdqsGatingPostProcess] freq 600
4447 23:12:48.712459 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4448 23:12:48.715869 Pre-setting of DQS Precalculation
4449 23:12:48.722937 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4450 23:12:48.723018 ==
4451 23:12:48.726508 Dram Type= 6, Freq= 0, CH_1, rank 0
4452 23:12:48.729225 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4453 23:12:48.729306 ==
4454 23:12:48.736350 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4455 23:12:48.742464 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4456 23:12:48.745410 [CA 0] Center 35 (5~66) winsize 62
4457 23:12:48.748667 [CA 1] Center 35 (5~66) winsize 62
4458 23:12:48.752113 [CA 2] Center 34 (4~65) winsize 62
4459 23:12:48.755353 [CA 3] Center 33 (3~64) winsize 62
4460 23:12:48.758837 [CA 4] Center 34 (4~64) winsize 61
4461 23:12:48.761784 [CA 5] Center 33 (3~64) winsize 62
4462 23:12:48.761865
4463 23:12:48.765286 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4464 23:12:48.765366
4465 23:12:48.768646 [CATrainingPosCal] consider 1 rank data
4466 23:12:48.772289 u2DelayCellTimex100 = 270/100 ps
4467 23:12:48.775190 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4468 23:12:48.778858 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4469 23:12:48.782055 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4470 23:12:48.785348 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4471 23:12:48.789039 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4472 23:12:48.792323 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4473 23:12:48.792404
4474 23:12:48.795817 CA PerBit enable=1, Macro0, CA PI delay=33
4475 23:12:48.798743
4476 23:12:48.798823 [CBTSetCACLKResult] CA Dly = 33
4477 23:12:48.801817 CS Dly: 5 (0~36)
4478 23:12:48.801897 ==
4479 23:12:48.805301 Dram Type= 6, Freq= 0, CH_1, rank 1
4480 23:12:48.808327 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4481 23:12:48.808408 ==
4482 23:12:48.815072 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4483 23:12:48.821662 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4484 23:12:48.824806 [CA 0] Center 35 (5~66) winsize 62
4485 23:12:48.827963 [CA 1] Center 36 (6~66) winsize 61
4486 23:12:48.831234 [CA 2] Center 34 (4~65) winsize 62
4487 23:12:48.834763 [CA 3] Center 33 (3~64) winsize 62
4488 23:12:48.838031 [CA 4] Center 34 (4~65) winsize 62
4489 23:12:48.841648 [CA 5] Center 34 (3~65) winsize 63
4490 23:12:48.841728
4491 23:12:48.844841 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4492 23:12:48.844921
4493 23:12:48.848343 [CATrainingPosCal] consider 2 rank data
4494 23:12:48.851369 u2DelayCellTimex100 = 270/100 ps
4495 23:12:48.854709 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4496 23:12:48.858098 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4497 23:12:48.861443 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4498 23:12:48.864439 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4499 23:12:48.867545 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4500 23:12:48.874386 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4501 23:12:48.874466
4502 23:12:48.878313 CA PerBit enable=1, Macro0, CA PI delay=33
4503 23:12:48.878394
4504 23:12:48.881089 [CBTSetCACLKResult] CA Dly = 33
4505 23:12:48.881169 CS Dly: 5 (0~37)
4506 23:12:48.881232
4507 23:12:48.883952 ----->DramcWriteLeveling(PI) begin...
4508 23:12:48.884035 ==
4509 23:12:48.887704 Dram Type= 6, Freq= 0, CH_1, rank 0
4510 23:12:48.894069 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4511 23:12:48.894150 ==
4512 23:12:48.897502 Write leveling (Byte 0): 29 => 29
4513 23:12:48.897582 Write leveling (Byte 1): 29 => 29
4514 23:12:48.901313 DramcWriteLeveling(PI) end<-----
4515 23:12:48.901393
4516 23:12:48.904599 ==
4517 23:12:48.904679 Dram Type= 6, Freq= 0, CH_1, rank 0
4518 23:12:48.910702 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4519 23:12:48.910784 ==
4520 23:12:48.914102 [Gating] SW mode calibration
4521 23:12:48.921091 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4522 23:12:48.923644 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4523 23:12:48.930740 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4524 23:12:48.933838 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4525 23:12:48.937150 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4526 23:12:48.943626 0 9 12 | B1->B0 | 2f2f 2d2d | 0 1 | (1 1) (1 0)
4527 23:12:48.946987 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4528 23:12:48.950246 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4529 23:12:48.957343 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4530 23:12:48.960176 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4531 23:12:48.964239 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4532 23:12:48.970574 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4533 23:12:48.973410 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4534 23:12:48.977084 0 10 12 | B1->B0 | 3232 3636 | 0 0 | (0 0) (0 0)
4535 23:12:48.983656 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4536 23:12:48.986461 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4537 23:12:48.990170 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4538 23:12:48.996250 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4539 23:12:48.999787 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4540 23:12:49.002853 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4541 23:12:49.010044 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4542 23:12:49.013411 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4543 23:12:49.016471 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4544 23:12:49.023168 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4545 23:12:49.026199 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4546 23:12:49.029390 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4547 23:12:49.035818 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4548 23:12:49.039579 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4549 23:12:49.042603 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4550 23:12:49.049622 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4551 23:12:49.052484 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4552 23:12:49.055857 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4553 23:12:49.062741 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4554 23:12:49.065755 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4555 23:12:49.069367 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4556 23:12:49.076832 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4557 23:12:49.078813 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4558 23:12:49.082402 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4559 23:12:49.088571 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4560 23:12:49.091928 Total UI for P1: 0, mck2ui 16
4561 23:12:49.095256 best dqsien dly found for B0: ( 0, 13, 12)
4562 23:12:49.095336 Total UI for P1: 0, mck2ui 16
4563 23:12:49.101961 best dqsien dly found for B1: ( 0, 13, 14)
4564 23:12:49.105387 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4565 23:12:49.108271 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4566 23:12:49.108351
4567 23:12:49.111953 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4568 23:12:49.115041 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4569 23:12:49.118129 [Gating] SW calibration Done
4570 23:12:49.118210 ==
4571 23:12:49.122002 Dram Type= 6, Freq= 0, CH_1, rank 0
4572 23:12:49.125303 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4573 23:12:49.125384 ==
4574 23:12:49.128080 RX Vref Scan: 0
4575 23:12:49.128161
4576 23:12:49.131383 RX Vref 0 -> 0, step: 1
4577 23:12:49.131463
4578 23:12:49.131526 RX Delay -230 -> 252, step: 16
4579 23:12:49.138894 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4580 23:12:49.141471 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4581 23:12:49.144328 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4582 23:12:49.147644 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4583 23:12:49.154698 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4584 23:12:49.158025 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4585 23:12:49.161920 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4586 23:12:49.164727 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4587 23:12:49.168099 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4588 23:12:49.174213 iDelay=218, Bit 9, Center 33 (-134 ~ 201) 336
4589 23:12:49.177564 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4590 23:12:49.180872 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4591 23:12:49.184977 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4592 23:12:49.191035 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4593 23:12:49.194164 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4594 23:12:49.198264 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4595 23:12:49.198370 ==
4596 23:12:49.201192 Dram Type= 6, Freq= 0, CH_1, rank 0
4597 23:12:49.207523 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4598 23:12:49.207604 ==
4599 23:12:49.207668 DQS Delay:
4600 23:12:49.211133 DQS0 = 0, DQS1 = 0
4601 23:12:49.211213 DQM Delay:
4602 23:12:49.211276 DQM0 = 52, DQM1 = 42
4603 23:12:49.213913 DQ Delay:
4604 23:12:49.217811 DQ0 =57, DQ1 =49, DQ2 =49, DQ3 =49
4605 23:12:49.220523 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4606 23:12:49.223948 DQ8 =17, DQ9 =33, DQ10 =33, DQ11 =25
4607 23:12:49.227159 DQ12 =57, DQ13 =57, DQ14 =57, DQ15 =57
4608 23:12:49.227239
4609 23:12:49.227302
4610 23:12:49.227361 ==
4611 23:12:49.231217 Dram Type= 6, Freq= 0, CH_1, rank 0
4612 23:12:49.233675 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4613 23:12:49.233756 ==
4614 23:12:49.233819
4615 23:12:49.233877
4616 23:12:49.237384 TX Vref Scan disable
4617 23:12:49.237465 == TX Byte 0 ==
4618 23:12:49.244057 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4619 23:12:49.246880 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4620 23:12:49.246961 == TX Byte 1 ==
4621 23:12:49.253678 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4622 23:12:49.257353 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4623 23:12:49.257434 ==
4624 23:12:49.260407 Dram Type= 6, Freq= 0, CH_1, rank 0
4625 23:12:49.263300 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4626 23:12:49.263380 ==
4627 23:12:49.267141
4628 23:12:49.267220
4629 23:12:49.267284 TX Vref Scan disable
4630 23:12:49.272271 == TX Byte 0 ==
4631 23:12:49.273826 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4632 23:12:49.280302 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4633 23:12:49.280382 == TX Byte 1 ==
4634 23:12:49.283323 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4635 23:12:49.290504 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4636 23:12:49.290585
4637 23:12:49.290648 [DATLAT]
4638 23:12:49.290706 Freq=600, CH1 RK0
4639 23:12:49.290762
4640 23:12:49.294076 DATLAT Default: 0x9
4641 23:12:49.296776 0, 0xFFFF, sum = 0
4642 23:12:49.296858 1, 0xFFFF, sum = 0
4643 23:12:49.300164 2, 0xFFFF, sum = 0
4644 23:12:49.300245 3, 0xFFFF, sum = 0
4645 23:12:49.304420 4, 0xFFFF, sum = 0
4646 23:12:49.304503 5, 0xFFFF, sum = 0
4647 23:12:49.306672 6, 0xFFFF, sum = 0
4648 23:12:49.306752 7, 0xFFFF, sum = 0
4649 23:12:49.310511 8, 0x0, sum = 1
4650 23:12:49.310592 9, 0x0, sum = 2
4651 23:12:49.313146 10, 0x0, sum = 3
4652 23:12:49.313227 11, 0x0, sum = 4
4653 23:12:49.313290 best_step = 9
4654 23:12:49.313349
4655 23:12:49.316718 ==
4656 23:12:49.319859 Dram Type= 6, Freq= 0, CH_1, rank 0
4657 23:12:49.323291 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4658 23:12:49.323371 ==
4659 23:12:49.323434 RX Vref Scan: 1
4660 23:12:49.323491
4661 23:12:49.326702 RX Vref 0 -> 0, step: 1
4662 23:12:49.326781
4663 23:12:49.329366 RX Delay -195 -> 252, step: 8
4664 23:12:49.329445
4665 23:12:49.332761 Set Vref, RX VrefLevel [Byte0]: 50
4666 23:12:49.336320 [Byte1]: 51
4667 23:12:49.336438
4668 23:12:49.340146 Final RX Vref Byte 0 = 50 to rank0
4669 23:12:49.342716 Final RX Vref Byte 1 = 51 to rank0
4670 23:12:49.346109 Final RX Vref Byte 0 = 50 to rank1
4671 23:12:49.349801 Final RX Vref Byte 1 = 51 to rank1==
4672 23:12:49.352600 Dram Type= 6, Freq= 0, CH_1, rank 0
4673 23:12:49.359576 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4674 23:12:49.359656 ==
4675 23:12:49.359759 DQS Delay:
4676 23:12:49.359818 DQS0 = 0, DQS1 = 0
4677 23:12:49.362792 DQM Delay:
4678 23:12:49.362871 DQM0 = 47, DQM1 = 36
4679 23:12:49.365983 DQ Delay:
4680 23:12:49.369471 DQ0 =56, DQ1 =44, DQ2 =36, DQ3 =44
4681 23:12:49.372312 DQ4 =44, DQ5 =56, DQ6 =56, DQ7 =44
4682 23:12:49.375795 DQ8 =24, DQ9 =24, DQ10 =40, DQ11 =28
4683 23:12:49.379271 DQ12 =44, DQ13 =40, DQ14 =48, DQ15 =44
4684 23:12:49.379351
4685 23:12:49.379414
4686 23:12:49.385639 [DQSOSCAuto] RK0, (LSB)MR18= 0x472c, (MSB)MR19= 0x808, tDQSOscB0 = 401 ps tDQSOscB1 = 396 ps
4687 23:12:49.388830 CH1 RK0: MR19=808, MR18=472C
4688 23:12:49.395462 CH1_RK0: MR19=0x808, MR18=0x472C, DQSOSC=396, MR23=63, INC=167, DEC=111
4689 23:12:49.395543
4690 23:12:49.398836 ----->DramcWriteLeveling(PI) begin...
4691 23:12:49.398917 ==
4692 23:12:49.402131 Dram Type= 6, Freq= 0, CH_1, rank 1
4693 23:12:49.405780 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4694 23:12:49.405860 ==
4695 23:12:49.408891 Write leveling (Byte 0): 31 => 31
4696 23:12:49.412354 Write leveling (Byte 1): 31 => 31
4697 23:12:49.415495 DramcWriteLeveling(PI) end<-----
4698 23:12:49.415574
4699 23:12:49.415636 ==
4700 23:12:49.418492 Dram Type= 6, Freq= 0, CH_1, rank 1
4701 23:12:49.422564 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4702 23:12:49.425855 ==
4703 23:12:49.425934 [Gating] SW mode calibration
4704 23:12:49.435041 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4705 23:12:49.438243 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4706 23:12:49.441522 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4707 23:12:49.447799 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4708 23:12:49.451135 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4709 23:12:49.454610 0 9 12 | B1->B0 | 2f2f 3333 | 0 1 | (0 1) (1 0)
4710 23:12:49.461487 0 9 16 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
4711 23:12:49.464703 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4712 23:12:49.468097 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4713 23:12:49.474346 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4714 23:12:49.477398 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4715 23:12:49.481165 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4716 23:12:49.487622 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4717 23:12:49.490981 0 10 12 | B1->B0 | 3434 2a2a | 1 0 | (0 0) (0 0)
4718 23:12:49.494551 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4719 23:12:49.500668 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4720 23:12:49.503930 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4721 23:12:49.507399 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4722 23:12:49.513916 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4723 23:12:49.517284 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4724 23:12:49.520349 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4725 23:12:49.526913 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4726 23:12:49.530728 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4727 23:12:49.534365 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4728 23:12:49.539960 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4729 23:12:49.543643 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4730 23:12:49.547419 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4731 23:12:49.553268 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4732 23:12:49.556646 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4733 23:12:49.559862 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4734 23:12:49.566852 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4735 23:12:49.569769 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4736 23:12:49.573150 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4737 23:12:49.580029 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4738 23:12:49.583933 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4739 23:12:49.586520 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4740 23:12:49.593410 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4741 23:12:49.596162 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4742 23:12:49.600190 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4743 23:12:49.603397 Total UI for P1: 0, mck2ui 16
4744 23:12:49.606004 best dqsien dly found for B0: ( 0, 13, 12)
4745 23:12:49.609776 Total UI for P1: 0, mck2ui 16
4746 23:12:49.612850 best dqsien dly found for B1: ( 0, 13, 12)
4747 23:12:49.615889 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4748 23:12:49.622500 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4749 23:12:49.622580
4750 23:12:49.625514 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4751 23:12:49.629203 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4752 23:12:49.632914 [Gating] SW calibration Done
4753 23:12:49.632995 ==
4754 23:12:49.635760 Dram Type= 6, Freq= 0, CH_1, rank 1
4755 23:12:49.639065 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4756 23:12:49.639145 ==
4757 23:12:49.642316 RX Vref Scan: 0
4758 23:12:49.642408
4759 23:12:49.642471 RX Vref 0 -> 0, step: 1
4760 23:12:49.642529
4761 23:12:49.646222 RX Delay -230 -> 252, step: 16
4762 23:12:49.649390 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4763 23:12:49.655377 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4764 23:12:49.659027 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4765 23:12:49.661795 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4766 23:12:49.665290 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4767 23:12:49.671977 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4768 23:12:49.675616 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4769 23:12:49.678610 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4770 23:12:49.681907 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4771 23:12:49.685131 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4772 23:12:49.691873 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4773 23:12:49.695194 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4774 23:12:49.698338 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4775 23:12:49.705148 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4776 23:12:49.708116 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4777 23:12:49.711543 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4778 23:12:49.711648 ==
4779 23:12:49.715132 Dram Type= 6, Freq= 0, CH_1, rank 1
4780 23:12:49.718681 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4781 23:12:49.718761 ==
4782 23:12:49.721194 DQS Delay:
4783 23:12:49.721273 DQS0 = 0, DQS1 = 0
4784 23:12:49.724689 DQM Delay:
4785 23:12:49.724768 DQM0 = 42, DQM1 = 37
4786 23:12:49.724831 DQ Delay:
4787 23:12:49.728361 DQ0 =49, DQ1 =41, DQ2 =25, DQ3 =41
4788 23:12:49.731444 DQ4 =41, DQ5 =57, DQ6 =49, DQ7 =33
4789 23:12:49.734660 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =25
4790 23:12:49.738120 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =49
4791 23:12:49.738199
4792 23:12:49.741094
4793 23:12:49.741173 ==
4794 23:12:49.744488 Dram Type= 6, Freq= 0, CH_1, rank 1
4795 23:12:49.747861 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4796 23:12:49.747940 ==
4797 23:12:49.748003
4798 23:12:49.748061
4799 23:12:49.751017 TX Vref Scan disable
4800 23:12:49.751096 == TX Byte 0 ==
4801 23:12:49.757909 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4802 23:12:49.761165 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4803 23:12:49.761245 == TX Byte 1 ==
4804 23:12:49.769734 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4805 23:12:49.771152 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4806 23:12:49.771232 ==
4807 23:12:49.774200 Dram Type= 6, Freq= 0, CH_1, rank 1
4808 23:12:49.777615 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4809 23:12:49.777696 ==
4810 23:12:49.777759
4811 23:12:49.777816
4812 23:12:49.781472 TX Vref Scan disable
4813 23:12:49.784518 == TX Byte 0 ==
4814 23:12:49.787635 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4815 23:12:49.790439 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4816 23:12:49.794129 == TX Byte 1 ==
4817 23:12:49.797294 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4818 23:12:49.800705 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4819 23:12:49.803878
4820 23:12:49.803958 [DATLAT]
4821 23:12:49.804021 Freq=600, CH1 RK1
4822 23:12:49.804080
4823 23:12:49.807022 DATLAT Default: 0x9
4824 23:12:49.807102 0, 0xFFFF, sum = 0
4825 23:12:49.810497 1, 0xFFFF, sum = 0
4826 23:12:49.810578 2, 0xFFFF, sum = 0
4827 23:12:49.814281 3, 0xFFFF, sum = 0
4828 23:12:49.814363 4, 0xFFFF, sum = 0
4829 23:12:49.817501 5, 0xFFFF, sum = 0
4830 23:12:49.820384 6, 0xFFFF, sum = 0
4831 23:12:49.820466 7, 0xFFFF, sum = 0
4832 23:12:49.820531 8, 0x0, sum = 1
4833 23:12:49.823795 9, 0x0, sum = 2
4834 23:12:49.823876 10, 0x0, sum = 3
4835 23:12:49.826989 11, 0x0, sum = 4
4836 23:12:49.827070 best_step = 9
4837 23:12:49.827132
4838 23:12:49.827190 ==
4839 23:12:49.830136 Dram Type= 6, Freq= 0, CH_1, rank 1
4840 23:12:49.837171 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4841 23:12:49.837252 ==
4842 23:12:49.837315 RX Vref Scan: 0
4843 23:12:49.837372
4844 23:12:49.840529 RX Vref 0 -> 0, step: 1
4845 23:12:49.840609
4846 23:12:49.843859 RX Delay -179 -> 252, step: 8
4847 23:12:49.846797 iDelay=213, Bit 0, Center 48 (-99 ~ 196) 296
4848 23:12:49.853830 iDelay=213, Bit 1, Center 40 (-107 ~ 188) 296
4849 23:12:49.856503 iDelay=213, Bit 2, Center 32 (-115 ~ 180) 296
4850 23:12:49.860144 iDelay=213, Bit 3, Center 40 (-107 ~ 188) 296
4851 23:12:49.863776 iDelay=213, Bit 4, Center 44 (-107 ~ 196) 304
4852 23:12:49.870454 iDelay=213, Bit 5, Center 56 (-91 ~ 204) 296
4853 23:12:49.872944 iDelay=213, Bit 6, Center 60 (-91 ~ 212) 304
4854 23:12:49.877317 iDelay=213, Bit 7, Center 44 (-107 ~ 196) 304
4855 23:12:49.880169 iDelay=213, Bit 8, Center 24 (-131 ~ 180) 312
4856 23:12:49.883027 iDelay=213, Bit 9, Center 24 (-131 ~ 180) 312
4857 23:12:49.890067 iDelay=213, Bit 10, Center 32 (-123 ~ 188) 312
4858 23:12:49.892866 iDelay=213, Bit 11, Center 28 (-123 ~ 180) 304
4859 23:12:49.896084 iDelay=213, Bit 12, Center 48 (-107 ~ 204) 312
4860 23:12:49.899609 iDelay=213, Bit 13, Center 44 (-107 ~ 196) 304
4861 23:12:49.906242 iDelay=213, Bit 14, Center 44 (-107 ~ 196) 304
4862 23:12:49.909522 iDelay=213, Bit 15, Center 48 (-107 ~ 204) 312
4863 23:12:49.909603 ==
4864 23:12:49.912836 Dram Type= 6, Freq= 0, CH_1, rank 1
4865 23:12:49.916540 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4866 23:12:49.916621 ==
4867 23:12:49.919427 DQS Delay:
4868 23:12:49.919507 DQS0 = 0, DQS1 = 0
4869 23:12:49.923006 DQM Delay:
4870 23:12:49.923085 DQM0 = 45, DQM1 = 36
4871 23:12:49.923148 DQ Delay:
4872 23:12:49.926539 DQ0 =48, DQ1 =40, DQ2 =32, DQ3 =40
4873 23:12:49.929372 DQ4 =44, DQ5 =56, DQ6 =60, DQ7 =44
4874 23:12:49.932409 DQ8 =24, DQ9 =24, DQ10 =32, DQ11 =28
4875 23:12:49.936058 DQ12 =48, DQ13 =44, DQ14 =44, DQ15 =48
4876 23:12:49.936138
4877 23:12:49.936200
4878 23:12:49.945412 [DQSOSCAuto] RK1, (LSB)MR18= 0x291e, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 402 ps
4879 23:12:49.949214 CH1 RK1: MR19=808, MR18=291E
4880 23:12:49.955930 CH1_RK1: MR19=0x808, MR18=0x291E, DQSOSC=402, MR23=63, INC=162, DEC=108
4881 23:12:49.959315 [RxdqsGatingPostProcess] freq 600
4882 23:12:49.963199 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4883 23:12:49.965715 Pre-setting of DQS Precalculation
4884 23:12:49.973026 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4885 23:12:49.978322 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4886 23:12:49.985913 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4887 23:12:49.985993
4888 23:12:49.986055
4889 23:12:49.988930 [Calibration Summary] 1200 Mbps
4890 23:12:49.989009 CH 0, Rank 0
4891 23:12:49.992078 SW Impedance : PASS
4892 23:12:49.995084 DUTY Scan : NO K
4893 23:12:49.995164 ZQ Calibration : PASS
4894 23:12:49.998431 Jitter Meter : NO K
4895 23:12:50.001894 CBT Training : PASS
4896 23:12:50.001975 Write leveling : PASS
4897 23:12:50.004899 RX DQS gating : PASS
4898 23:12:50.004979 RX DQ/DQS(RDDQC) : PASS
4899 23:12:50.009075 TX DQ/DQS : PASS
4900 23:12:50.011420 RX DATLAT : PASS
4901 23:12:50.011500 RX DQ/DQS(Engine): PASS
4902 23:12:50.014698 TX OE : NO K
4903 23:12:50.014778 All Pass.
4904 23:12:50.014840
4905 23:12:50.018067 CH 0, Rank 1
4906 23:12:50.018146 SW Impedance : PASS
4907 23:12:50.021805 DUTY Scan : NO K
4908 23:12:50.024814 ZQ Calibration : PASS
4909 23:12:50.024893 Jitter Meter : NO K
4910 23:12:50.028093 CBT Training : PASS
4911 23:12:50.031462 Write leveling : PASS
4912 23:12:50.031541 RX DQS gating : PASS
4913 23:12:50.035456 RX DQ/DQS(RDDQC) : PASS
4914 23:12:50.037807 TX DQ/DQS : PASS
4915 23:12:50.037887 RX DATLAT : PASS
4916 23:12:50.041333 RX DQ/DQS(Engine): PASS
4917 23:12:50.044518 TX OE : NO K
4918 23:12:50.044598 All Pass.
4919 23:12:50.044660
4920 23:12:50.044717 CH 1, Rank 0
4921 23:12:50.047808 SW Impedance : PASS
4922 23:12:50.051467 DUTY Scan : NO K
4923 23:12:50.051546 ZQ Calibration : PASS
4924 23:12:50.055109 Jitter Meter : NO K
4925 23:12:50.057855 CBT Training : PASS
4926 23:12:50.057934 Write leveling : PASS
4927 23:12:50.061372 RX DQS gating : PASS
4928 23:12:50.061451 RX DQ/DQS(RDDQC) : PASS
4929 23:12:50.064634 TX DQ/DQS : PASS
4930 23:12:50.068345 RX DATLAT : PASS
4931 23:12:50.068424 RX DQ/DQS(Engine): PASS
4932 23:12:50.071154 TX OE : NO K
4933 23:12:50.071244 All Pass.
4934 23:12:50.071307
4935 23:12:50.074349 CH 1, Rank 1
4936 23:12:50.074429 SW Impedance : PASS
4937 23:12:50.077653 DUTY Scan : NO K
4938 23:12:50.080985 ZQ Calibration : PASS
4939 23:12:50.081065 Jitter Meter : NO K
4940 23:12:50.084285 CBT Training : PASS
4941 23:12:50.088578 Write leveling : PASS
4942 23:12:50.088658 RX DQS gating : PASS
4943 23:12:50.091106 RX DQ/DQS(RDDQC) : PASS
4944 23:12:50.094233 TX DQ/DQS : PASS
4945 23:12:50.094313 RX DATLAT : PASS
4946 23:12:50.098396 RX DQ/DQS(Engine): PASS
4947 23:12:50.100661 TX OE : NO K
4948 23:12:50.100741 All Pass.
4949 23:12:50.100803
4950 23:12:50.104606 DramC Write-DBI off
4951 23:12:50.104686 PER_BANK_REFRESH: Hybrid Mode
4952 23:12:50.107649 TX_TRACKING: ON
4953 23:12:50.113932 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4954 23:12:50.120491 [FAST_K] Save calibration result to emmc
4955 23:12:50.123821 dramc_set_vcore_voltage set vcore to 662500
4956 23:12:50.123901 Read voltage for 933, 3
4957 23:12:50.127409 Vio18 = 0
4958 23:12:50.127488 Vcore = 662500
4959 23:12:50.127550 Vdram = 0
4960 23:12:50.130394 Vddq = 0
4961 23:12:50.130473 Vmddr = 0
4962 23:12:50.133940 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4963 23:12:50.139998 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4964 23:12:50.143420 MEM_TYPE=3, freq_sel=17
4965 23:12:50.147098 sv_algorithm_assistance_LP4_1600
4966 23:12:50.150071 ============ PULL DRAM RESETB DOWN ============
4967 23:12:50.153402 ========== PULL DRAM RESETB DOWN end =========
4968 23:12:50.160051 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4969 23:12:50.163214 ===================================
4970 23:12:50.163294 LPDDR4 DRAM CONFIGURATION
4971 23:12:50.166319 ===================================
4972 23:12:50.169536 EX_ROW_EN[0] = 0x0
4973 23:12:50.172925 EX_ROW_EN[1] = 0x0
4974 23:12:50.173004 LP4Y_EN = 0x0
4975 23:12:50.177098 WORK_FSP = 0x0
4976 23:12:50.177180 WL = 0x3
4977 23:12:50.179762 RL = 0x3
4978 23:12:50.179842 BL = 0x2
4979 23:12:50.182912 RPST = 0x0
4980 23:12:50.182991 RD_PRE = 0x0
4981 23:12:50.185972 WR_PRE = 0x1
4982 23:12:50.186051 WR_PST = 0x0
4983 23:12:50.189593 DBI_WR = 0x0
4984 23:12:50.189672 DBI_RD = 0x0
4985 23:12:50.192887 OTF = 0x1
4986 23:12:50.195978 ===================================
4987 23:12:50.200092 ===================================
4988 23:12:50.200172 ANA top config
4989 23:12:50.203074 ===================================
4990 23:12:50.206340 DLL_ASYNC_EN = 0
4991 23:12:50.210792 ALL_SLAVE_EN = 1
4992 23:12:50.212804 NEW_RANK_MODE = 1
4993 23:12:50.212885 DLL_IDLE_MODE = 1
4994 23:12:50.216711 LP45_APHY_COMB_EN = 1
4995 23:12:50.219360 TX_ODT_DIS = 1
4996 23:12:50.222356 NEW_8X_MODE = 1
4997 23:12:50.225679 ===================================
4998 23:12:50.229417 ===================================
4999 23:12:50.232892 data_rate = 1866
5000 23:12:50.232972 CKR = 1
5001 23:12:50.235572 DQ_P2S_RATIO = 8
5002 23:12:50.238839 ===================================
5003 23:12:50.242153 CA_P2S_RATIO = 8
5004 23:12:50.245645 DQ_CA_OPEN = 0
5005 23:12:50.249664 DQ_SEMI_OPEN = 0
5006 23:12:50.253074 CA_SEMI_OPEN = 0
5007 23:12:50.253154 CA_FULL_RATE = 0
5008 23:12:50.255427 DQ_CKDIV4_EN = 1
5009 23:12:50.258978 CA_CKDIV4_EN = 1
5010 23:12:50.262305 CA_PREDIV_EN = 0
5011 23:12:50.265477 PH8_DLY = 0
5012 23:12:50.268410 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
5013 23:12:50.272373 DQ_AAMCK_DIV = 4
5014 23:12:50.272453 CA_AAMCK_DIV = 4
5015 23:12:50.275177 CA_ADMCK_DIV = 4
5016 23:12:50.278664 DQ_TRACK_CA_EN = 0
5017 23:12:50.281914 CA_PICK = 933
5018 23:12:50.284999 CA_MCKIO = 933
5019 23:12:50.288593 MCKIO_SEMI = 0
5020 23:12:50.291838 PLL_FREQ = 3732
5021 23:12:50.291919 DQ_UI_PI_RATIO = 32
5022 23:12:50.295172 CA_UI_PI_RATIO = 0
5023 23:12:50.298422 ===================================
5024 23:12:50.302257 ===================================
5025 23:12:50.304864 memory_type:LPDDR4
5026 23:12:50.308851 GP_NUM : 10
5027 23:12:50.308931 SRAM_EN : 1
5028 23:12:50.312516 MD32_EN : 0
5029 23:12:50.315414 ===================================
5030 23:12:50.318040 [ANA_INIT] >>>>>>>>>>>>>>
5031 23:12:50.318120 <<<<<< [CONFIGURE PHASE]: ANA_TX
5032 23:12:50.321340 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5033 23:12:50.324529 ===================================
5034 23:12:50.328029 data_rate = 1866,PCW = 0X8f00
5035 23:12:50.331572 ===================================
5036 23:12:50.334830 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5037 23:12:50.341652 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5038 23:12:50.347716 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5039 23:12:50.351617 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5040 23:12:50.354518 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5041 23:12:50.357636 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5042 23:12:50.360960 [ANA_INIT] flow start
5043 23:12:50.361040 [ANA_INIT] PLL >>>>>>>>
5044 23:12:50.364169 [ANA_INIT] PLL <<<<<<<<
5045 23:12:50.367536 [ANA_INIT] MIDPI >>>>>>>>
5046 23:12:50.370795 [ANA_INIT] MIDPI <<<<<<<<
5047 23:12:50.370876 [ANA_INIT] DLL >>>>>>>>
5048 23:12:50.373952 [ANA_INIT] flow end
5049 23:12:50.377339 ============ LP4 DIFF to SE enter ============
5050 23:12:50.380895 ============ LP4 DIFF to SE exit ============
5051 23:12:50.384233 [ANA_INIT] <<<<<<<<<<<<<
5052 23:12:50.387024 [Flow] Enable top DCM control >>>>>
5053 23:12:50.390330 [Flow] Enable top DCM control <<<<<
5054 23:12:50.394039 Enable DLL master slave shuffle
5055 23:12:50.400267 ==============================================================
5056 23:12:50.400348 Gating Mode config
5057 23:12:50.406817 ==============================================================
5058 23:12:50.406897 Config description:
5059 23:12:50.416877 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5060 23:12:50.423341 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5061 23:12:50.430112 SELPH_MODE 0: By rank 1: By Phase
5062 23:12:50.436544 ==============================================================
5063 23:12:50.436625 GAT_TRACK_EN = 1
5064 23:12:50.439845 RX_GATING_MODE = 2
5065 23:12:50.443503 RX_GATING_TRACK_MODE = 2
5066 23:12:50.446577 SELPH_MODE = 1
5067 23:12:50.449890 PICG_EARLY_EN = 1
5068 23:12:50.452953 VALID_LAT_VALUE = 1
5069 23:12:50.459505 ==============================================================
5070 23:12:50.462919 Enter into Gating configuration >>>>
5071 23:12:50.466054 Exit from Gating configuration <<<<
5072 23:12:50.469497 Enter into DVFS_PRE_config >>>>>
5073 23:12:50.479309 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5074 23:12:50.483371 Exit from DVFS_PRE_config <<<<<
5075 23:12:50.486039 Enter into PICG configuration >>>>
5076 23:12:50.489088 Exit from PICG configuration <<<<
5077 23:12:50.492826 [RX_INPUT] configuration >>>>>
5078 23:12:50.495852 [RX_INPUT] configuration <<<<<
5079 23:12:50.498952 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5080 23:12:50.505719 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5081 23:12:50.512531 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5082 23:12:50.519026 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5083 23:12:50.522471 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5084 23:12:50.528909 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5085 23:12:50.532177 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5086 23:12:50.539752 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5087 23:12:50.541792 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5088 23:12:50.545607 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5089 23:12:50.548688 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5090 23:12:50.555110 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5091 23:12:50.558220 ===================================
5092 23:12:50.561551 LPDDR4 DRAM CONFIGURATION
5093 23:12:50.565076 ===================================
5094 23:12:50.565156 EX_ROW_EN[0] = 0x0
5095 23:12:50.568667 EX_ROW_EN[1] = 0x0
5096 23:12:50.568747 LP4Y_EN = 0x0
5097 23:12:50.572117 WORK_FSP = 0x0
5098 23:12:50.572197 WL = 0x3
5099 23:12:50.574790 RL = 0x3
5100 23:12:50.574870 BL = 0x2
5101 23:12:50.578302 RPST = 0x0
5102 23:12:50.578383 RD_PRE = 0x0
5103 23:12:50.581703 WR_PRE = 0x1
5104 23:12:50.581883 WR_PST = 0x0
5105 23:12:50.584996 DBI_WR = 0x0
5106 23:12:50.587983 DBI_RD = 0x0
5107 23:12:50.588063 OTF = 0x1
5108 23:12:50.591962 ===================================
5109 23:12:50.594933 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5110 23:12:50.597879 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5111 23:12:50.604610 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5112 23:12:50.608353 ===================================
5113 23:12:50.611256 LPDDR4 DRAM CONFIGURATION
5114 23:12:50.615027 ===================================
5115 23:12:50.615107 EX_ROW_EN[0] = 0x10
5116 23:12:50.617589 EX_ROW_EN[1] = 0x0
5117 23:12:50.617669 LP4Y_EN = 0x0
5118 23:12:50.620885 WORK_FSP = 0x0
5119 23:12:50.620970 WL = 0x3
5120 23:12:50.624386 RL = 0x3
5121 23:12:50.624466 BL = 0x2
5122 23:12:50.627622 RPST = 0x0
5123 23:12:50.627743 RD_PRE = 0x0
5124 23:12:50.631053 WR_PRE = 0x1
5125 23:12:50.631133 WR_PST = 0x0
5126 23:12:50.634339 DBI_WR = 0x0
5127 23:12:50.637547 DBI_RD = 0x0
5128 23:12:50.637627 OTF = 0x1
5129 23:12:50.641254 ===================================
5130 23:12:50.647668 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5131 23:12:50.651131 nWR fixed to 30
5132 23:12:50.654721 [ModeRegInit_LP4] CH0 RK0
5133 23:12:50.654802 [ModeRegInit_LP4] CH0 RK1
5134 23:12:50.658008 [ModeRegInit_LP4] CH1 RK0
5135 23:12:50.661049 [ModeRegInit_LP4] CH1 RK1
5136 23:12:50.661129 match AC timing 9
5137 23:12:50.667596 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5138 23:12:50.671056 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5139 23:12:50.675050 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5140 23:12:50.680507 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5141 23:12:50.684087 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5142 23:12:50.684167 ==
5143 23:12:50.687221 Dram Type= 6, Freq= 0, CH_0, rank 0
5144 23:12:50.691354 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5145 23:12:50.691434 ==
5146 23:12:50.697090 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5147 23:12:50.703553 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5148 23:12:50.706971 [CA 0] Center 37 (7~68) winsize 62
5149 23:12:50.710824 [CA 1] Center 37 (7~68) winsize 62
5150 23:12:50.713687 [CA 2] Center 34 (4~65) winsize 62
5151 23:12:50.717221 [CA 3] Center 35 (5~65) winsize 61
5152 23:12:50.720771 [CA 4] Center 33 (3~64) winsize 62
5153 23:12:50.723317 [CA 5] Center 33 (3~64) winsize 62
5154 23:12:50.723397
5155 23:12:50.726890 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5156 23:12:50.726970
5157 23:12:50.730567 [CATrainingPosCal] consider 1 rank data
5158 23:12:50.733531 u2DelayCellTimex100 = 270/100 ps
5159 23:12:50.737025 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5160 23:12:50.740118 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5161 23:12:50.743351 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5162 23:12:50.749611 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5163 23:12:50.752795 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5164 23:12:50.756372 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5165 23:12:50.756452
5166 23:12:50.760467 CA PerBit enable=1, Macro0, CA PI delay=33
5167 23:12:50.760548
5168 23:12:50.763038 [CBTSetCACLKResult] CA Dly = 33
5169 23:12:50.763118 CS Dly: 7 (0~38)
5170 23:12:50.763182 ==
5171 23:12:50.766332 Dram Type= 6, Freq= 0, CH_0, rank 1
5172 23:12:50.773100 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5173 23:12:50.773184 ==
5174 23:12:50.777299 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5175 23:12:50.782533 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5176 23:12:50.786552 [CA 0] Center 37 (7~68) winsize 62
5177 23:12:50.789420 [CA 1] Center 37 (7~68) winsize 62
5178 23:12:50.792827 [CA 2] Center 34 (4~65) winsize 62
5179 23:12:50.797122 [CA 3] Center 34 (4~65) winsize 62
5180 23:12:50.799269 [CA 4] Center 33 (3~64) winsize 62
5181 23:12:50.802773 [CA 5] Center 32 (2~63) winsize 62
5182 23:12:50.802853
5183 23:12:50.805907 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5184 23:12:50.805988
5185 23:12:50.809120 [CATrainingPosCal] consider 2 rank data
5186 23:12:50.813024 u2DelayCellTimex100 = 270/100 ps
5187 23:12:50.815788 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5188 23:12:50.822724 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5189 23:12:50.825783 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5190 23:12:50.828905 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5191 23:12:50.832227 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5192 23:12:50.835944 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5193 23:12:50.836025
5194 23:12:50.839135 CA PerBit enable=1, Macro0, CA PI delay=33
5195 23:12:50.839215
5196 23:12:50.842749 [CBTSetCACLKResult] CA Dly = 33
5197 23:12:50.845810 CS Dly: 7 (0~39)
5198 23:12:50.845889
5199 23:12:50.849428 ----->DramcWriteLeveling(PI) begin...
5200 23:12:50.849509 ==
5201 23:12:50.852285 Dram Type= 6, Freq= 0, CH_0, rank 0
5202 23:12:50.856283 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5203 23:12:50.856363 ==
5204 23:12:50.858596 Write leveling (Byte 0): 32 => 32
5205 23:12:50.861787 Write leveling (Byte 1): 27 => 27
5206 23:12:50.865500 DramcWriteLeveling(PI) end<-----
5207 23:12:50.865580
5208 23:12:50.865642 ==
5209 23:12:50.868506 Dram Type= 6, Freq= 0, CH_0, rank 0
5210 23:12:50.871930 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5211 23:12:50.872010 ==
5212 23:12:50.875467 [Gating] SW mode calibration
5213 23:12:50.882339 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5214 23:12:50.889170 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5215 23:12:50.891837 0 14 0 | B1->B0 | 2323 3232 | 0 1 | (1 1) (1 1)
5216 23:12:50.895166 0 14 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5217 23:12:50.901951 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5218 23:12:50.905469 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5219 23:12:50.908707 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5220 23:12:50.914501 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5221 23:12:50.918161 0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5222 23:12:50.921273 0 14 28 | B1->B0 | 3434 2f2f | 0 0 | (0 0) (0 0)
5223 23:12:50.927728 0 15 0 | B1->B0 | 3232 2323 | 0 0 | (1 0) (1 0)
5224 23:12:50.930871 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5225 23:12:50.937628 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5226 23:12:50.941499 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5227 23:12:50.944414 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5228 23:12:50.950628 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5229 23:12:50.954357 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5230 23:12:50.957510 0 15 28 | B1->B0 | 2323 3535 | 0 0 | (0 0) (0 0)
5231 23:12:50.963947 1 0 0 | B1->B0 | 3434 4343 | 0 0 | (0 0) (0 0)
5232 23:12:50.967741 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5233 23:12:50.970516 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5234 23:12:50.977622 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5235 23:12:50.980349 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5236 23:12:50.983717 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5237 23:12:50.990499 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5238 23:12:50.993696 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5239 23:12:50.996685 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5240 23:12:51.003513 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5241 23:12:51.006410 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5242 23:12:51.010092 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5243 23:12:51.016567 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5244 23:12:51.020039 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5245 23:12:51.023025 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5246 23:12:51.029700 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5247 23:12:51.033064 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5248 23:12:51.036425 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5249 23:12:51.042819 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5250 23:12:51.046057 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5251 23:12:51.049668 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5252 23:12:51.056101 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5253 23:12:51.059560 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5254 23:12:51.062468 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5255 23:12:51.070408 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5256 23:12:51.073135 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5257 23:12:51.076280 Total UI for P1: 0, mck2ui 16
5258 23:12:51.079435 best dqsien dly found for B0: ( 1, 2, 28)
5259 23:12:51.082458 Total UI for P1: 0, mck2ui 16
5260 23:12:51.086400 best dqsien dly found for B1: ( 1, 3, 0)
5261 23:12:51.088791 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5262 23:12:51.092915 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5263 23:12:51.092995
5264 23:12:51.095990 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5265 23:12:51.099059 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5266 23:12:51.102062 [Gating] SW calibration Done
5267 23:12:51.102141 ==
5268 23:12:51.105886 Dram Type= 6, Freq= 0, CH_0, rank 0
5269 23:12:51.109354 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5270 23:12:51.112596 ==
5271 23:12:51.112675 RX Vref Scan: 0
5272 23:12:51.112738
5273 23:12:51.115491 RX Vref 0 -> 0, step: 1
5274 23:12:51.115570
5275 23:12:51.119126 RX Delay -80 -> 252, step: 8
5276 23:12:51.121979 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5277 23:12:51.124831 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5278 23:12:51.128292 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5279 23:12:51.132090 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5280 23:12:51.135595 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5281 23:12:51.141569 iDelay=208, Bit 5, Center 83 (-16 ~ 183) 200
5282 23:12:51.144903 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5283 23:12:51.148122 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5284 23:12:51.151976 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5285 23:12:51.155473 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5286 23:12:51.161247 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5287 23:12:51.164594 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5288 23:12:51.168218 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5289 23:12:51.171521 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5290 23:12:51.174594 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5291 23:12:51.181228 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5292 23:12:51.181307 ==
5293 23:12:51.184774 Dram Type= 6, Freq= 0, CH_0, rank 0
5294 23:12:51.187900 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5295 23:12:51.188006 ==
5296 23:12:51.188096 DQS Delay:
5297 23:12:51.191026 DQS0 = 0, DQS1 = 0
5298 23:12:51.191131 DQM Delay:
5299 23:12:51.194367 DQM0 = 97, DQM1 = 85
5300 23:12:51.194446 DQ Delay:
5301 23:12:51.197831 DQ0 =99, DQ1 =99, DQ2 =91, DQ3 =91
5302 23:12:51.201436 DQ4 =99, DQ5 =83, DQ6 =107, DQ7 =107
5303 23:12:51.204394 DQ8 =79, DQ9 =75, DQ10 =83, DQ11 =79
5304 23:12:51.208887 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5305 23:12:51.208968
5306 23:12:51.209030
5307 23:12:51.209088 ==
5308 23:12:51.211051 Dram Type= 6, Freq= 0, CH_0, rank 0
5309 23:12:51.213994 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5310 23:12:51.218401 ==
5311 23:12:51.218480
5312 23:12:51.218541
5313 23:12:51.218598 TX Vref Scan disable
5314 23:12:51.221022 == TX Byte 0 ==
5315 23:12:51.223835 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5316 23:12:51.228044 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5317 23:12:51.230983 == TX Byte 1 ==
5318 23:12:51.234012 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5319 23:12:51.240866 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5320 23:12:51.240945 ==
5321 23:12:51.244054 Dram Type= 6, Freq= 0, CH_0, rank 0
5322 23:12:51.247161 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5323 23:12:51.247240 ==
5324 23:12:51.247301
5325 23:12:51.247358
5326 23:12:51.250411 TX Vref Scan disable
5327 23:12:51.250490 == TX Byte 0 ==
5328 23:12:51.257295 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5329 23:12:51.260640 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5330 23:12:51.260720 == TX Byte 1 ==
5331 23:12:51.267282 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5332 23:12:51.270458 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5333 23:12:51.270538
5334 23:12:51.270600 [DATLAT]
5335 23:12:51.273992 Freq=933, CH0 RK0
5336 23:12:51.274071
5337 23:12:51.274132 DATLAT Default: 0xd
5338 23:12:51.277242 0, 0xFFFF, sum = 0
5339 23:12:51.277323 1, 0xFFFF, sum = 0
5340 23:12:51.280237 2, 0xFFFF, sum = 0
5341 23:12:51.280318 3, 0xFFFF, sum = 0
5342 23:12:51.283506 4, 0xFFFF, sum = 0
5343 23:12:51.287042 5, 0xFFFF, sum = 0
5344 23:12:51.287128 6, 0xFFFF, sum = 0
5345 23:12:51.290623 7, 0xFFFF, sum = 0
5346 23:12:51.290703 8, 0xFFFF, sum = 0
5347 23:12:51.293448 9, 0xFFFF, sum = 0
5348 23:12:51.293544 10, 0x0, sum = 1
5349 23:12:51.297291 11, 0x0, sum = 2
5350 23:12:51.297371 12, 0x0, sum = 3
5351 23:12:51.300162 13, 0x0, sum = 4
5352 23:12:51.300257 best_step = 11
5353 23:12:51.300349
5354 23:12:51.300420 ==
5355 23:12:51.303370 Dram Type= 6, Freq= 0, CH_0, rank 0
5356 23:12:51.306530 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5357 23:12:51.306610 ==
5358 23:12:51.309941 RX Vref Scan: 1
5359 23:12:51.310020
5360 23:12:51.313510 RX Vref 0 -> 0, step: 1
5361 23:12:51.313589
5362 23:12:51.313651 RX Delay -69 -> 252, step: 4
5363 23:12:51.313709
5364 23:12:51.318841 Set Vref, RX VrefLevel [Byte0]: 61
5365 23:12:51.320594 [Byte1]: 49
5366 23:12:51.324843
5367 23:12:51.324923 Final RX Vref Byte 0 = 61 to rank0
5368 23:12:51.328554 Final RX Vref Byte 1 = 49 to rank0
5369 23:12:51.331199 Final RX Vref Byte 0 = 61 to rank1
5370 23:12:51.334497 Final RX Vref Byte 1 = 49 to rank1==
5371 23:12:51.337961 Dram Type= 6, Freq= 0, CH_0, rank 0
5372 23:12:51.344301 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5373 23:12:51.344381 ==
5374 23:12:51.344444 DQS Delay:
5375 23:12:51.347708 DQS0 = 0, DQS1 = 0
5376 23:12:51.347801 DQM Delay:
5377 23:12:51.347862 DQM0 = 97, DQM1 = 85
5378 23:12:51.351078 DQ Delay:
5379 23:12:51.354572 DQ0 =96, DQ1 =98, DQ2 =94, DQ3 =94
5380 23:12:51.357803 DQ4 =96, DQ5 =88, DQ6 =106, DQ7 =106
5381 23:12:51.361133 DQ8 =78, DQ9 =76, DQ10 =84, DQ11 =78
5382 23:12:51.364469 DQ12 =92, DQ13 =88, DQ14 =96, DQ15 =94
5383 23:12:51.364548
5384 23:12:51.364610
5385 23:12:51.371050 [DQSOSCAuto] RK0, (LSB)MR18= 0x2d14, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 407 ps
5386 23:12:51.374733 CH0 RK0: MR19=505, MR18=2D14
5387 23:12:51.380664 CH0_RK0: MR19=0x505, MR18=0x2D14, DQSOSC=407, MR23=63, INC=65, DEC=43
5388 23:12:51.380743
5389 23:12:51.383938 ----->DramcWriteLeveling(PI) begin...
5390 23:12:51.384019 ==
5391 23:12:51.387145 Dram Type= 6, Freq= 0, CH_0, rank 1
5392 23:12:51.390635 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5393 23:12:51.390715 ==
5394 23:12:51.394007 Write leveling (Byte 0): 32 => 32
5395 23:12:51.397280 Write leveling (Byte 1): 30 => 30
5396 23:12:51.400924 DramcWriteLeveling(PI) end<-----
5397 23:12:51.401003
5398 23:12:51.401065 ==
5399 23:12:51.403905 Dram Type= 6, Freq= 0, CH_0, rank 1
5400 23:12:51.407163 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5401 23:12:51.410578 ==
5402 23:12:51.410658 [Gating] SW mode calibration
5403 23:12:51.420325 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5404 23:12:51.423534 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5405 23:12:51.426698 0 14 0 | B1->B0 | 2c2c 3231 | 1 1 | (1 1) (1 1)
5406 23:12:51.433389 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5407 23:12:51.436927 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5408 23:12:51.440600 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5409 23:12:51.447257 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5410 23:12:51.450373 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5411 23:12:51.453403 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5412 23:12:51.459918 0 14 28 | B1->B0 | 3232 2e2e | 1 0 | (1 1) (0 0)
5413 23:12:51.463525 0 15 0 | B1->B0 | 3030 2626 | 0 0 | (0 1) (1 0)
5414 23:12:51.466630 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5415 23:12:51.472973 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5416 23:12:51.476113 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5417 23:12:51.479506 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5418 23:12:51.486057 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5419 23:12:51.489459 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5420 23:12:51.493279 0 15 28 | B1->B0 | 2323 3535 | 0 0 | (0 0) (1 1)
5421 23:12:51.499444 1 0 0 | B1->B0 | 3939 4242 | 0 0 | (1 1) (0 0)
5422 23:12:51.502957 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5423 23:12:51.506482 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5424 23:12:51.512670 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5425 23:12:51.515835 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5426 23:12:51.519300 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5427 23:12:51.526173 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5428 23:12:51.528823 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5429 23:12:51.533096 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5430 23:12:51.538943 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5431 23:12:51.542389 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5432 23:12:51.545625 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5433 23:12:51.552392 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5434 23:12:51.555312 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5435 23:12:51.558631 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5436 23:12:51.565567 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5437 23:12:51.569055 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5438 23:12:51.572359 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5439 23:12:51.578659 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5440 23:12:51.581910 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5441 23:12:51.584906 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5442 23:12:51.591481 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5443 23:12:51.594911 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5444 23:12:51.598569 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5445 23:12:51.604794 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5446 23:12:51.608039 Total UI for P1: 0, mck2ui 16
5447 23:12:51.611942 best dqsien dly found for B0: ( 1, 2, 28)
5448 23:12:51.614802 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5449 23:12:51.618388 Total UI for P1: 0, mck2ui 16
5450 23:12:51.621495 best dqsien dly found for B1: ( 1, 3, 0)
5451 23:12:51.624857 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5452 23:12:51.627768 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5453 23:12:51.627848
5454 23:12:51.630849 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5455 23:12:51.634466 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5456 23:12:51.638336 [Gating] SW calibration Done
5457 23:12:51.638416 ==
5458 23:12:51.640766 Dram Type= 6, Freq= 0, CH_0, rank 1
5459 23:12:51.647486 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5460 23:12:51.647568 ==
5461 23:12:51.647631 RX Vref Scan: 0
5462 23:12:51.647697
5463 23:12:51.651020 RX Vref 0 -> 0, step: 1
5464 23:12:51.651100
5465 23:12:51.654153 RX Delay -80 -> 252, step: 8
5466 23:12:51.657935 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5467 23:12:51.660626 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5468 23:12:51.664252 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5469 23:12:51.667402 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5470 23:12:51.674045 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5471 23:12:51.677024 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5472 23:12:51.680797 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5473 23:12:51.683769 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5474 23:12:51.686934 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5475 23:12:51.693634 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5476 23:12:51.697264 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5477 23:12:51.700192 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5478 23:12:51.703436 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5479 23:12:51.706950 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5480 23:12:51.714294 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5481 23:12:51.716909 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5482 23:12:51.717003 ==
5483 23:12:51.720794 Dram Type= 6, Freq= 0, CH_0, rank 1
5484 23:12:51.723411 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5485 23:12:51.723492 ==
5486 23:12:51.723555 DQS Delay:
5487 23:12:51.726558 DQS0 = 0, DQS1 = 0
5488 23:12:51.726638 DQM Delay:
5489 23:12:51.730027 DQM0 = 97, DQM1 = 87
5490 23:12:51.730108 DQ Delay:
5491 23:12:51.733095 DQ0 =91, DQ1 =99, DQ2 =91, DQ3 =91
5492 23:12:51.736628 DQ4 =103, DQ5 =87, DQ6 =107, DQ7 =107
5493 23:12:51.739922 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =79
5494 23:12:51.743659 DQ12 =91, DQ13 =91, DQ14 =95, DQ15 =91
5495 23:12:51.743776
5496 23:12:51.743840
5497 23:12:51.743897 ==
5498 23:12:51.746195 Dram Type= 6, Freq= 0, CH_0, rank 1
5499 23:12:51.752837 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5500 23:12:51.752918 ==
5501 23:12:51.752981
5502 23:12:51.753039
5503 23:12:51.753094 TX Vref Scan disable
5504 23:12:51.757024 == TX Byte 0 ==
5505 23:12:51.760380 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5506 23:12:51.766281 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5507 23:12:51.766362 == TX Byte 1 ==
5508 23:12:51.770254 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5509 23:12:51.777088 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5510 23:12:51.777169 ==
5511 23:12:51.779771 Dram Type= 6, Freq= 0, CH_0, rank 1
5512 23:12:51.782752 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5513 23:12:51.782834 ==
5514 23:12:51.782896
5515 23:12:51.782954
5516 23:12:51.786519 TX Vref Scan disable
5517 23:12:51.789366 == TX Byte 0 ==
5518 23:12:51.793235 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5519 23:12:51.796228 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5520 23:12:51.799131 == TX Byte 1 ==
5521 23:12:51.802641 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5522 23:12:51.805983 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5523 23:12:51.806063
5524 23:12:51.806125 [DATLAT]
5525 23:12:51.808957 Freq=933, CH0 RK1
5526 23:12:51.809037
5527 23:12:51.812377 DATLAT Default: 0xb
5528 23:12:51.812456 0, 0xFFFF, sum = 0
5529 23:12:51.815501 1, 0xFFFF, sum = 0
5530 23:12:51.815582 2, 0xFFFF, sum = 0
5531 23:12:51.819131 3, 0xFFFF, sum = 0
5532 23:12:51.819213 4, 0xFFFF, sum = 0
5533 23:12:51.822403 5, 0xFFFF, sum = 0
5534 23:12:51.822483 6, 0xFFFF, sum = 0
5535 23:12:51.825610 7, 0xFFFF, sum = 0
5536 23:12:51.825693 8, 0xFFFF, sum = 0
5537 23:12:51.829073 9, 0xFFFF, sum = 0
5538 23:12:51.829165 10, 0x0, sum = 1
5539 23:12:51.832427 11, 0x0, sum = 2
5540 23:12:51.832507 12, 0x0, sum = 3
5541 23:12:51.835758 13, 0x0, sum = 4
5542 23:12:51.835838 best_step = 11
5543 23:12:51.835900
5544 23:12:51.835958 ==
5545 23:12:51.838916 Dram Type= 6, Freq= 0, CH_0, rank 1
5546 23:12:51.842042 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5547 23:12:51.845253 ==
5548 23:12:51.845332 RX Vref Scan: 0
5549 23:12:51.845395
5550 23:12:51.848360 RX Vref 0 -> 0, step: 1
5551 23:12:51.848440
5552 23:12:51.851832 RX Delay -61 -> 252, step: 4
5553 23:12:51.855056 iDelay=203, Bit 0, Center 92 (-1 ~ 186) 188
5554 23:12:51.858479 iDelay=203, Bit 1, Center 96 (-1 ~ 194) 196
5555 23:12:51.865272 iDelay=203, Bit 2, Center 88 (-5 ~ 182) 188
5556 23:12:51.868455 iDelay=203, Bit 3, Center 92 (-5 ~ 190) 196
5557 23:12:51.871929 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5558 23:12:51.875188 iDelay=203, Bit 5, Center 86 (-9 ~ 182) 192
5559 23:12:51.878686 iDelay=203, Bit 6, Center 104 (7 ~ 202) 196
5560 23:12:51.882093 iDelay=203, Bit 7, Center 104 (11 ~ 198) 188
5561 23:12:51.888866 iDelay=203, Bit 8, Center 78 (-13 ~ 170) 184
5562 23:12:51.891561 iDelay=203, Bit 9, Center 74 (-17 ~ 166) 184
5563 23:12:51.894934 iDelay=203, Bit 10, Center 86 (-9 ~ 182) 192
5564 23:12:51.898072 iDelay=203, Bit 11, Center 78 (-13 ~ 170) 184
5565 23:12:51.901474 iDelay=203, Bit 12, Center 94 (3 ~ 186) 184
5566 23:12:51.908283 iDelay=203, Bit 13, Center 90 (-5 ~ 186) 192
5567 23:12:51.911695 iDelay=203, Bit 14, Center 94 (3 ~ 186) 184
5568 23:12:51.914953 iDelay=203, Bit 15, Center 92 (-1 ~ 186) 188
5569 23:12:51.915033 ==
5570 23:12:51.917915 Dram Type= 6, Freq= 0, CH_0, rank 1
5571 23:12:51.922100 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5572 23:12:51.922181 ==
5573 23:12:51.924531 DQS Delay:
5574 23:12:51.924612 DQS0 = 0, DQS1 = 0
5575 23:12:51.927799 DQM Delay:
5576 23:12:51.927879 DQM0 = 94, DQM1 = 85
5577 23:12:51.927942 DQ Delay:
5578 23:12:51.931175 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =92
5579 23:12:51.934507 DQ4 =96, DQ5 =86, DQ6 =104, DQ7 =104
5580 23:12:51.938026 DQ8 =78, DQ9 =74, DQ10 =86, DQ11 =78
5581 23:12:51.941226 DQ12 =94, DQ13 =90, DQ14 =94, DQ15 =92
5582 23:12:51.941306
5583 23:12:51.941369
5584 23:12:51.952182 [DQSOSCAuto] RK1, (LSB)MR18= 0x27f7, (MSB)MR19= 0x504, tDQSOscB0 = 425 ps tDQSOscB1 = 409 ps
5585 23:12:51.954719 CH0 RK1: MR19=504, MR18=27F7
5586 23:12:51.960557 CH0_RK1: MR19=0x504, MR18=0x27F7, DQSOSC=409, MR23=63, INC=64, DEC=43
5587 23:12:51.964112 [RxdqsGatingPostProcess] freq 933
5588 23:12:51.967462 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5589 23:12:51.971097 best DQS0 dly(2T, 0.5T) = (0, 10)
5590 23:12:51.974009 best DQS1 dly(2T, 0.5T) = (0, 11)
5591 23:12:51.977456 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5592 23:12:51.980514 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5593 23:12:51.984355 best DQS0 dly(2T, 0.5T) = (0, 10)
5594 23:12:51.987450 best DQS1 dly(2T, 0.5T) = (0, 11)
5595 23:12:51.990840 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5596 23:12:51.994139 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5597 23:12:51.997163 Pre-setting of DQS Precalculation
5598 23:12:52.000682 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5599 23:12:52.000763 ==
5600 23:12:52.003905 Dram Type= 6, Freq= 0, CH_1, rank 0
5601 23:12:52.010487 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5602 23:12:52.010569 ==
5603 23:12:52.014378 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5604 23:12:52.020413 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5605 23:12:52.023566 [CA 0] Center 36 (6~67) winsize 62
5606 23:12:52.027320 [CA 1] Center 37 (6~68) winsize 63
5607 23:12:52.030153 [CA 2] Center 34 (4~65) winsize 62
5608 23:12:52.033393 [CA 3] Center 33 (3~64) winsize 62
5609 23:12:52.036672 [CA 4] Center 34 (4~65) winsize 62
5610 23:12:52.040314 [CA 5] Center 33 (3~64) winsize 62
5611 23:12:52.040395
5612 23:12:52.043282 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5613 23:12:52.043363
5614 23:12:52.046696 [CATrainingPosCal] consider 1 rank data
5615 23:12:52.049972 u2DelayCellTimex100 = 270/100 ps
5616 23:12:52.053390 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5617 23:12:52.057223 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5618 23:12:52.064166 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5619 23:12:52.066502 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5620 23:12:52.069635 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5621 23:12:52.073529 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5622 23:12:52.073610
5623 23:12:52.076344 CA PerBit enable=1, Macro0, CA PI delay=33
5624 23:12:52.076424
5625 23:12:52.079840 [CBTSetCACLKResult] CA Dly = 33
5626 23:12:52.079921 CS Dly: 6 (0~37)
5627 23:12:52.082967 ==
5628 23:12:52.086315 Dram Type= 6, Freq= 0, CH_1, rank 1
5629 23:12:52.090188 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5630 23:12:52.090269 ==
5631 23:12:52.092947 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5632 23:12:52.099391 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5633 23:12:52.103631 [CA 0] Center 36 (6~67) winsize 62
5634 23:12:52.106357 [CA 1] Center 37 (7~68) winsize 62
5635 23:12:52.110319 [CA 2] Center 34 (4~65) winsize 62
5636 23:12:52.113804 [CA 3] Center 34 (3~65) winsize 63
5637 23:12:52.116954 [CA 4] Center 34 (4~65) winsize 62
5638 23:12:52.119593 [CA 5] Center 33 (3~64) winsize 62
5639 23:12:52.119726
5640 23:12:52.123539 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5641 23:12:52.123619
5642 23:12:52.126483 [CATrainingPosCal] consider 2 rank data
5643 23:12:52.129788 u2DelayCellTimex100 = 270/100 ps
5644 23:12:52.132840 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5645 23:12:52.139567 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5646 23:12:52.142881 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5647 23:12:52.146477 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5648 23:12:52.149596 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5649 23:12:52.152553 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5650 23:12:52.152634
5651 23:12:52.155861 CA PerBit enable=1, Macro0, CA PI delay=33
5652 23:12:52.155941
5653 23:12:52.159330 [CBTSetCACLKResult] CA Dly = 33
5654 23:12:52.162576 CS Dly: 7 (0~39)
5655 23:12:52.162656
5656 23:12:52.165627 ----->DramcWriteLeveling(PI) begin...
5657 23:12:52.165708 ==
5658 23:12:52.169338 Dram Type= 6, Freq= 0, CH_1, rank 0
5659 23:12:52.172256 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5660 23:12:52.172336 ==
5661 23:12:52.175417 Write leveling (Byte 0): 28 => 28
5662 23:12:52.178725 Write leveling (Byte 1): 30 => 30
5663 23:12:52.182631 DramcWriteLeveling(PI) end<-----
5664 23:12:52.182711
5665 23:12:52.182775 ==
5666 23:12:52.186169 Dram Type= 6, Freq= 0, CH_1, rank 0
5667 23:12:52.188486 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5668 23:12:52.188566 ==
5669 23:12:52.192446 [Gating] SW mode calibration
5670 23:12:52.199216 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5671 23:12:52.204975 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5672 23:12:52.208290 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5673 23:12:52.215269 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5674 23:12:52.218446 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5675 23:12:52.221572 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5676 23:12:52.225483 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5677 23:12:52.231864 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5678 23:12:52.235052 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
5679 23:12:52.238710 0 14 28 | B1->B0 | 2f2f 2f2f | 0 0 | (0 0) (0 0)
5680 23:12:52.245502 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5681 23:12:52.248072 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5682 23:12:52.252343 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5683 23:12:52.258110 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5684 23:12:52.261667 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5685 23:12:52.264731 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5686 23:12:52.271049 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5687 23:12:52.274455 0 15 28 | B1->B0 | 3a3a 3939 | 0 0 | (0 0) (0 0)
5688 23:12:52.277843 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5689 23:12:52.284534 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5690 23:12:52.288249 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5691 23:12:52.291547 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5692 23:12:52.297618 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5693 23:12:52.300842 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5694 23:12:52.304216 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5695 23:12:52.311539 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5696 23:12:52.314086 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5697 23:12:52.318357 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5698 23:12:52.323852 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5699 23:12:52.327309 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5700 23:12:52.330969 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5701 23:12:52.337323 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5702 23:12:52.340933 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5703 23:12:52.343575 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5704 23:12:52.350629 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5705 23:12:52.353588 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5706 23:12:52.357468 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5707 23:12:52.363754 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5708 23:12:52.367080 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5709 23:12:52.370173 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5710 23:12:52.377057 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5711 23:12:52.379902 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5712 23:12:52.383320 Total UI for P1: 0, mck2ui 16
5713 23:12:52.386981 best dqsien dly found for B0: ( 1, 2, 24)
5714 23:12:52.389913 Total UI for P1: 0, mck2ui 16
5715 23:12:52.393305 best dqsien dly found for B1: ( 1, 2, 24)
5716 23:12:52.397109 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5717 23:12:52.400241 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5718 23:12:52.400319
5719 23:12:52.403958 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5720 23:12:52.409805 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5721 23:12:52.409885 [Gating] SW calibration Done
5722 23:12:52.409947 ==
5723 23:12:52.413577 Dram Type= 6, Freq= 0, CH_1, rank 0
5724 23:12:52.419946 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5725 23:12:52.420028 ==
5726 23:12:52.420091 RX Vref Scan: 0
5727 23:12:52.420151
5728 23:12:52.422809 RX Vref 0 -> 0, step: 1
5729 23:12:52.422889
5730 23:12:52.426292 RX Delay -80 -> 252, step: 8
5731 23:12:52.429548 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5732 23:12:52.432617 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5733 23:12:52.435988 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5734 23:12:52.443290 iDelay=208, Bit 3, Center 103 (8 ~ 199) 192
5735 23:12:52.446563 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5736 23:12:52.449504 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5737 23:12:52.452760 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5738 23:12:52.455884 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5739 23:12:52.459400 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5740 23:12:52.465965 iDelay=208, Bit 9, Center 83 (-16 ~ 183) 200
5741 23:12:52.469264 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5742 23:12:52.472290 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5743 23:12:52.475762 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5744 23:12:52.479050 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5745 23:12:52.485840 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5746 23:12:52.489094 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5747 23:12:52.489177 ==
5748 23:12:52.492446 Dram Type= 6, Freq= 0, CH_1, rank 0
5749 23:12:52.495564 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5750 23:12:52.495677 ==
5751 23:12:52.498733 DQS Delay:
5752 23:12:52.498812 DQS0 = 0, DQS1 = 0
5753 23:12:52.498875 DQM Delay:
5754 23:12:52.502594 DQM0 = 103, DQM1 = 92
5755 23:12:52.502673 DQ Delay:
5756 23:12:52.505189 DQ0 =107, DQ1 =99, DQ2 =95, DQ3 =103
5757 23:12:52.509367 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =99
5758 23:12:52.512958 DQ8 =79, DQ9 =83, DQ10 =91, DQ11 =79
5759 23:12:52.515436 DQ12 =103, DQ13 =103, DQ14 =99, DQ15 =103
5760 23:12:52.515515
5761 23:12:52.515577
5762 23:12:52.518992 ==
5763 23:12:52.521874 Dram Type= 6, Freq= 0, CH_1, rank 0
5764 23:12:52.525320 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5765 23:12:52.525400 ==
5766 23:12:52.525463
5767 23:12:52.525521
5768 23:12:52.528691 TX Vref Scan disable
5769 23:12:52.528771 == TX Byte 0 ==
5770 23:12:52.535003 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5771 23:12:52.538511 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5772 23:12:52.538591 == TX Byte 1 ==
5773 23:12:52.545114 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5774 23:12:52.548114 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5775 23:12:52.548194 ==
5776 23:12:52.551559 Dram Type= 6, Freq= 0, CH_1, rank 0
5777 23:12:52.554879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5778 23:12:52.554960 ==
5779 23:12:52.555022
5780 23:12:52.555080
5781 23:12:52.558805 TX Vref Scan disable
5782 23:12:52.562028 == TX Byte 0 ==
5783 23:12:52.564974 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5784 23:12:52.569638 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5785 23:12:52.571700 == TX Byte 1 ==
5786 23:12:52.574934 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5787 23:12:52.578445 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5788 23:12:52.578525
5789 23:12:52.582042 [DATLAT]
5790 23:12:52.582121 Freq=933, CH1 RK0
5791 23:12:52.582184
5792 23:12:52.585106 DATLAT Default: 0xd
5793 23:12:52.585186 0, 0xFFFF, sum = 0
5794 23:12:52.588383 1, 0xFFFF, sum = 0
5795 23:12:52.588464 2, 0xFFFF, sum = 0
5796 23:12:52.591517 3, 0xFFFF, sum = 0
5797 23:12:52.591598 4, 0xFFFF, sum = 0
5798 23:12:52.595187 5, 0xFFFF, sum = 0
5799 23:12:52.595268 6, 0xFFFF, sum = 0
5800 23:12:52.598135 7, 0xFFFF, sum = 0
5801 23:12:52.598216 8, 0xFFFF, sum = 0
5802 23:12:52.601758 9, 0xFFFF, sum = 0
5803 23:12:52.601838 10, 0x0, sum = 1
5804 23:12:52.605204 11, 0x0, sum = 2
5805 23:12:52.605284 12, 0x0, sum = 3
5806 23:12:52.608652 13, 0x0, sum = 4
5807 23:12:52.608732 best_step = 11
5808 23:12:52.608795
5809 23:12:52.608853 ==
5810 23:12:52.611124 Dram Type= 6, Freq= 0, CH_1, rank 0
5811 23:12:52.617758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5812 23:12:52.617838 ==
5813 23:12:52.617901 RX Vref Scan: 1
5814 23:12:52.617960
5815 23:12:52.621080 RX Vref 0 -> 0, step: 1
5816 23:12:52.621159
5817 23:12:52.624597 RX Delay -61 -> 252, step: 4
5818 23:12:52.624676
5819 23:12:52.628125 Set Vref, RX VrefLevel [Byte0]: 50
5820 23:12:52.631335 [Byte1]: 51
5821 23:12:52.631415
5822 23:12:52.634440 Final RX Vref Byte 0 = 50 to rank0
5823 23:12:52.637783 Final RX Vref Byte 1 = 51 to rank0
5824 23:12:52.640956 Final RX Vref Byte 0 = 50 to rank1
5825 23:12:52.644036 Final RX Vref Byte 1 = 51 to rank1==
5826 23:12:52.647513 Dram Type= 6, Freq= 0, CH_1, rank 0
5827 23:12:52.650850 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5828 23:12:52.650930 ==
5829 23:12:52.653974 DQS Delay:
5830 23:12:52.654054 DQS0 = 0, DQS1 = 0
5831 23:12:52.657380 DQM Delay:
5832 23:12:52.657459 DQM0 = 101, DQM1 = 93
5833 23:12:52.657523 DQ Delay:
5834 23:12:52.660870 DQ0 =106, DQ1 =98, DQ2 =92, DQ3 =98
5835 23:12:52.664019 DQ4 =98, DQ5 =112, DQ6 =110, DQ7 =98
5836 23:12:52.667420 DQ8 =80, DQ9 =84, DQ10 =94, DQ11 =84
5837 23:12:52.673937 DQ12 =102, DQ13 =98, DQ14 =104, DQ15 =104
5838 23:12:52.674017
5839 23:12:52.674079
5840 23:12:52.680291 [DQSOSCAuto] RK0, (LSB)MR18= 0x1f0f, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 412 ps
5841 23:12:52.684049 CH1 RK0: MR19=505, MR18=1F0F
5842 23:12:52.690622 CH1_RK0: MR19=0x505, MR18=0x1F0F, DQSOSC=412, MR23=63, INC=63, DEC=42
5843 23:12:52.690702
5844 23:12:52.694415 ----->DramcWriteLeveling(PI) begin...
5845 23:12:52.694496 ==
5846 23:12:52.696610 Dram Type= 6, Freq= 0, CH_1, rank 1
5847 23:12:52.699987 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5848 23:12:52.700067 ==
5849 23:12:52.703168 Write leveling (Byte 0): 27 => 27
5850 23:12:52.707161 Write leveling (Byte 1): 27 => 27
5851 23:12:52.710581 DramcWriteLeveling(PI) end<-----
5852 23:12:52.710661
5853 23:12:52.710724 ==
5854 23:12:52.713384 Dram Type= 6, Freq= 0, CH_1, rank 1
5855 23:12:52.716562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5856 23:12:52.716642 ==
5857 23:12:52.720469 [Gating] SW mode calibration
5858 23:12:52.726761 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5859 23:12:52.733418 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5860 23:12:52.736425 0 14 0 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
5861 23:12:52.742721 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5862 23:12:52.745764 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5863 23:12:52.749421 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5864 23:12:52.755935 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5865 23:12:52.759096 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5866 23:12:52.762473 0 14 24 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
5867 23:12:52.769514 0 14 28 | B1->B0 | 2626 3131 | 0 1 | (0 0) (1 0)
5868 23:12:52.772215 0 15 0 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
5869 23:12:52.775391 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5870 23:12:52.782270 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5871 23:12:52.785341 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5872 23:12:52.789047 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5873 23:12:52.795314 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5874 23:12:52.798714 0 15 24 | B1->B0 | 2727 2323 | 1 0 | (0 0) (0 0)
5875 23:12:52.801773 0 15 28 | B1->B0 | 3f3f 3131 | 1 0 | (0 0) (0 0)
5876 23:12:52.808533 1 0 0 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
5877 23:12:52.811842 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5878 23:12:52.815061 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5879 23:12:52.821582 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5880 23:12:52.825231 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5881 23:12:52.828234 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5882 23:12:52.834671 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5883 23:12:52.838520 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5884 23:12:52.841252 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5885 23:12:52.847868 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5886 23:12:52.851922 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5887 23:12:52.855114 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5888 23:12:52.861165 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5889 23:12:52.864259 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5890 23:12:52.867630 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5891 23:12:52.874057 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5892 23:12:52.877721 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5893 23:12:52.880831 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5894 23:12:52.887652 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5895 23:12:52.891295 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5896 23:12:52.893987 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5897 23:12:52.900751 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5898 23:12:52.904060 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5899 23:12:52.907325 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5900 23:12:52.910558 Total UI for P1: 0, mck2ui 16
5901 23:12:52.913792 best dqsien dly found for B1: ( 1, 2, 26)
5902 23:12:52.920777 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5903 23:12:52.923591 Total UI for P1: 0, mck2ui 16
5904 23:12:52.926786 best dqsien dly found for B0: ( 1, 2, 28)
5905 23:12:52.930143 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5906 23:12:52.933591 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5907 23:12:52.933670
5908 23:12:52.937008 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5909 23:12:52.939836 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5910 23:12:52.943566 [Gating] SW calibration Done
5911 23:12:52.943646 ==
5912 23:12:52.946703 Dram Type= 6, Freq= 0, CH_1, rank 1
5913 23:12:52.949946 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5914 23:12:52.950026 ==
5915 23:12:52.953608 RX Vref Scan: 0
5916 23:12:52.953687
5917 23:12:52.956365 RX Vref 0 -> 0, step: 1
5918 23:12:52.956445
5919 23:12:52.956507 RX Delay -80 -> 252, step: 8
5920 23:12:52.963020 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5921 23:12:52.966604 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5922 23:12:52.969950 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5923 23:12:52.973378 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5924 23:12:52.976269 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5925 23:12:52.983617 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5926 23:12:52.986059 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5927 23:12:52.989919 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5928 23:12:52.992742 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5929 23:12:52.996000 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5930 23:12:52.999344 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5931 23:12:53.005871 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5932 23:12:53.009412 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5933 23:12:53.012279 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5934 23:12:53.015573 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5935 23:12:53.019028 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5936 23:12:53.022469 ==
5937 23:12:53.025829 Dram Type= 6, Freq= 0, CH_1, rank 1
5938 23:12:53.029365 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5939 23:12:53.029446 ==
5940 23:12:53.029510 DQS Delay:
5941 23:12:53.033211 DQS0 = 0, DQS1 = 0
5942 23:12:53.033291 DQM Delay:
5943 23:12:53.036008 DQM0 = 100, DQM1 = 92
5944 23:12:53.036088 DQ Delay:
5945 23:12:53.038731 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
5946 23:12:53.042492 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =95
5947 23:12:53.045689 DQ8 =79, DQ9 =79, DQ10 =95, DQ11 =83
5948 23:12:53.049218 DQ12 =103, DQ13 =103, DQ14 =95, DQ15 =99
5949 23:12:53.049298
5950 23:12:53.049360
5951 23:12:53.049418 ==
5952 23:12:53.052227 Dram Type= 6, Freq= 0, CH_1, rank 1
5953 23:12:53.055904 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5954 23:12:53.055984 ==
5955 23:12:53.058673
5956 23:12:53.058752
5957 23:12:53.058815 TX Vref Scan disable
5958 23:12:53.062195 == TX Byte 0 ==
5959 23:12:53.065447 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5960 23:12:53.068841 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5961 23:12:53.072033 == TX Byte 1 ==
5962 23:12:53.075170 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5963 23:12:53.078466 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5964 23:12:53.081749 ==
5965 23:12:53.081842 Dram Type= 6, Freq= 0, CH_1, rank 1
5966 23:12:53.088758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5967 23:12:53.088838 ==
5968 23:12:53.088901
5969 23:12:53.088959
5970 23:12:53.091859 TX Vref Scan disable
5971 23:12:53.091939 == TX Byte 0 ==
5972 23:12:53.098254 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5973 23:12:53.101411 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5974 23:12:53.101493 == TX Byte 1 ==
5975 23:12:53.108819 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5976 23:12:53.111393 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5977 23:12:53.111474
5978 23:12:53.111537 [DATLAT]
5979 23:12:53.115511 Freq=933, CH1 RK1
5980 23:12:53.115615
5981 23:12:53.115739 DATLAT Default: 0xb
5982 23:12:53.118476 0, 0xFFFF, sum = 0
5983 23:12:53.118556 1, 0xFFFF, sum = 0
5984 23:12:53.121192 2, 0xFFFF, sum = 0
5985 23:12:53.121271 3, 0xFFFF, sum = 0
5986 23:12:53.124669 4, 0xFFFF, sum = 0
5987 23:12:53.124793 5, 0xFFFF, sum = 0
5988 23:12:53.127772 6, 0xFFFF, sum = 0
5989 23:12:53.131758 7, 0xFFFF, sum = 0
5990 23:12:53.131837 8, 0xFFFF, sum = 0
5991 23:12:53.135690 9, 0xFFFF, sum = 0
5992 23:12:53.135784 10, 0x0, sum = 1
5993 23:12:53.135847 11, 0x0, sum = 2
5994 23:12:53.137698 12, 0x0, sum = 3
5995 23:12:53.137777 13, 0x0, sum = 4
5996 23:12:53.141104 best_step = 11
5997 23:12:53.141182
5998 23:12:53.141242 ==
5999 23:12:53.144969 Dram Type= 6, Freq= 0, CH_1, rank 1
6000 23:12:53.147552 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
6001 23:12:53.147675 ==
6002 23:12:53.150932 RX Vref Scan: 0
6003 23:12:53.151010
6004 23:12:53.151072 RX Vref 0 -> 0, step: 1
6005 23:12:53.154348
6006 23:12:53.154426 RX Delay -61 -> 252, step: 4
6007 23:12:53.161685 iDelay=207, Bit 0, Center 106 (19 ~ 194) 176
6008 23:12:53.165307 iDelay=207, Bit 1, Center 94 (7 ~ 182) 176
6009 23:12:53.168772 iDelay=207, Bit 2, Center 90 (3 ~ 178) 176
6010 23:12:53.171791 iDelay=207, Bit 3, Center 98 (15 ~ 182) 168
6011 23:12:53.175350 iDelay=207, Bit 4, Center 100 (11 ~ 190) 180
6012 23:12:53.181769 iDelay=207, Bit 5, Center 110 (23 ~ 198) 176
6013 23:12:53.184951 iDelay=207, Bit 6, Center 114 (23 ~ 206) 184
6014 23:12:53.188532 iDelay=207, Bit 7, Center 98 (7 ~ 190) 184
6015 23:12:53.191438 iDelay=207, Bit 8, Center 82 (-5 ~ 170) 176
6016 23:12:53.195484 iDelay=207, Bit 9, Center 84 (-5 ~ 174) 180
6017 23:12:53.198180 iDelay=207, Bit 10, Center 90 (-1 ~ 182) 184
6018 23:12:53.204785 iDelay=207, Bit 11, Center 84 (-5 ~ 174) 180
6019 23:12:53.208857 iDelay=207, Bit 12, Center 102 (11 ~ 194) 184
6020 23:12:53.211298 iDelay=207, Bit 13, Center 100 (11 ~ 190) 180
6021 23:12:53.214996 iDelay=207, Bit 14, Center 100 (11 ~ 190) 180
6022 23:12:53.221858 iDelay=207, Bit 15, Center 100 (11 ~ 190) 180
6023 23:12:53.221939 ==
6024 23:12:53.225053 Dram Type= 6, Freq= 0, CH_1, rank 1
6025 23:12:53.228014 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
6026 23:12:53.228095 ==
6027 23:12:53.228158 DQS Delay:
6028 23:12:53.231058 DQS0 = 0, DQS1 = 0
6029 23:12:53.231137 DQM Delay:
6030 23:12:53.234765 DQM0 = 101, DQM1 = 92
6031 23:12:53.234862 DQ Delay:
6032 23:12:53.237696 DQ0 =106, DQ1 =94, DQ2 =90, DQ3 =98
6033 23:12:53.241082 DQ4 =100, DQ5 =110, DQ6 =114, DQ7 =98
6034 23:12:53.244366 DQ8 =82, DQ9 =84, DQ10 =90, DQ11 =84
6035 23:12:53.247912 DQ12 =102, DQ13 =100, DQ14 =100, DQ15 =100
6036 23:12:53.247992
6037 23:12:53.248055
6038 23:12:53.257101 [DQSOSCAuto] RK1, (LSB)MR18= 0xa04, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 418 ps
6039 23:12:53.261074 CH1 RK1: MR19=505, MR18=A04
6040 23:12:53.264017 CH1_RK1: MR19=0x505, MR18=0xA04, DQSOSC=418, MR23=63, INC=62, DEC=41
6041 23:12:53.267237 [RxdqsGatingPostProcess] freq 933
6042 23:12:53.274033 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6043 23:12:53.277116 best DQS0 dly(2T, 0.5T) = (0, 10)
6044 23:12:53.280364 best DQS1 dly(2T, 0.5T) = (0, 10)
6045 23:12:53.283817 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6046 23:12:53.286919 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6047 23:12:53.290168 best DQS0 dly(2T, 0.5T) = (0, 10)
6048 23:12:53.293505 best DQS1 dly(2T, 0.5T) = (0, 10)
6049 23:12:53.296850 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6050 23:12:53.300499 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6051 23:12:53.303480 Pre-setting of DQS Precalculation
6052 23:12:53.306868 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6053 23:12:53.314012 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6054 23:12:53.320229 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6055 23:12:53.320310
6056 23:12:53.320373
6057 23:12:53.323358 [Calibration Summary] 1866 Mbps
6058 23:12:53.326918 CH 0, Rank 0
6059 23:12:53.326998 SW Impedance : PASS
6060 23:12:53.330037 DUTY Scan : NO K
6061 23:12:53.333039 ZQ Calibration : PASS
6062 23:12:53.333123 Jitter Meter : NO K
6063 23:12:53.336584 CBT Training : PASS
6064 23:12:53.340159 Write leveling : PASS
6065 23:12:53.340243 RX DQS gating : PASS
6066 23:12:53.343607 RX DQ/DQS(RDDQC) : PASS
6067 23:12:53.347476 TX DQ/DQS : PASS
6068 23:12:53.347558 RX DATLAT : PASS
6069 23:12:53.350018 RX DQ/DQS(Engine): PASS
6070 23:12:53.353044 TX OE : NO K
6071 23:12:53.353125 All Pass.
6072 23:12:53.353188
6073 23:12:53.353245 CH 0, Rank 1
6074 23:12:53.356517 SW Impedance : PASS
6075 23:12:53.359622 DUTY Scan : NO K
6076 23:12:53.359756 ZQ Calibration : PASS
6077 23:12:53.363562 Jitter Meter : NO K
6078 23:12:53.366387 CBT Training : PASS
6079 23:12:53.366470 Write leveling : PASS
6080 23:12:53.369429 RX DQS gating : PASS
6081 23:12:53.369510 RX DQ/DQS(RDDQC) : PASS
6082 23:12:53.372647 TX DQ/DQS : PASS
6083 23:12:53.376361 RX DATLAT : PASS
6084 23:12:53.376443 RX DQ/DQS(Engine): PASS
6085 23:12:53.379864 TX OE : NO K
6086 23:12:53.379945 All Pass.
6087 23:12:53.380009
6088 23:12:53.382608 CH 1, Rank 0
6089 23:12:53.382687 SW Impedance : PASS
6090 23:12:53.385757 DUTY Scan : NO K
6091 23:12:53.389660 ZQ Calibration : PASS
6092 23:12:53.389741 Jitter Meter : NO K
6093 23:12:53.392670 CBT Training : PASS
6094 23:12:53.396260 Write leveling : PASS
6095 23:12:53.396341 RX DQS gating : PASS
6096 23:12:53.399127 RX DQ/DQS(RDDQC) : PASS
6097 23:12:53.402836 TX DQ/DQS : PASS
6098 23:12:53.402919 RX DATLAT : PASS
6099 23:12:53.405531 RX DQ/DQS(Engine): PASS
6100 23:12:53.409051 TX OE : NO K
6101 23:12:53.409134 All Pass.
6102 23:12:53.409198
6103 23:12:53.409257 CH 1, Rank 1
6104 23:12:53.412148 SW Impedance : PASS
6105 23:12:53.415951 DUTY Scan : NO K
6106 23:12:53.416033 ZQ Calibration : PASS
6107 23:12:53.419016 Jitter Meter : NO K
6108 23:12:53.421942 CBT Training : PASS
6109 23:12:53.422025 Write leveling : PASS
6110 23:12:53.425257 RX DQS gating : PASS
6111 23:12:53.428822 RX DQ/DQS(RDDQC) : PASS
6112 23:12:53.428904 TX DQ/DQS : PASS
6113 23:12:53.432260 RX DATLAT : PASS
6114 23:12:53.435424 RX DQ/DQS(Engine): PASS
6115 23:12:53.435507 TX OE : NO K
6116 23:12:53.438613 All Pass.
6117 23:12:53.438694
6118 23:12:53.438758 DramC Write-DBI off
6119 23:12:53.441516 PER_BANK_REFRESH: Hybrid Mode
6120 23:12:53.441597 TX_TRACKING: ON
6121 23:12:53.451782 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6122 23:12:53.455693 [FAST_K] Save calibration result to emmc
6123 23:12:53.458349 dramc_set_vcore_voltage set vcore to 650000
6124 23:12:53.461904 Read voltage for 400, 6
6125 23:12:53.461985 Vio18 = 0
6126 23:12:53.465475 Vcore = 650000
6127 23:12:53.465556 Vdram = 0
6128 23:12:53.465620 Vddq = 0
6129 23:12:53.468392 Vmddr = 0
6130 23:12:53.471580 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6131 23:12:53.478292 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6132 23:12:53.478374 MEM_TYPE=3, freq_sel=20
6133 23:12:53.481905 sv_algorithm_assistance_LP4_800
6134 23:12:53.488410 ============ PULL DRAM RESETB DOWN ============
6135 23:12:53.491496 ========== PULL DRAM RESETB DOWN end =========
6136 23:12:53.494558 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6137 23:12:53.498453 ===================================
6138 23:12:53.501248 LPDDR4 DRAM CONFIGURATION
6139 23:12:53.504811 ===================================
6140 23:12:53.504918 EX_ROW_EN[0] = 0x0
6141 23:12:53.508175 EX_ROW_EN[1] = 0x0
6142 23:12:53.511147 LP4Y_EN = 0x0
6143 23:12:53.511241 WORK_FSP = 0x0
6144 23:12:53.514560 WL = 0x2
6145 23:12:53.514640 RL = 0x2
6146 23:12:53.517877 BL = 0x2
6147 23:12:53.517957 RPST = 0x0
6148 23:12:53.521394 RD_PRE = 0x0
6149 23:12:53.521489 WR_PRE = 0x1
6150 23:12:53.524503 WR_PST = 0x0
6151 23:12:53.524582 DBI_WR = 0x0
6152 23:12:53.528296 DBI_RD = 0x0
6153 23:12:53.528376 OTF = 0x1
6154 23:12:53.531225 ===================================
6155 23:12:53.535343 ===================================
6156 23:12:53.537983 ANA top config
6157 23:12:53.541786 ===================================
6158 23:12:53.541866 DLL_ASYNC_EN = 0
6159 23:12:53.544075 ALL_SLAVE_EN = 1
6160 23:12:53.547709 NEW_RANK_MODE = 1
6161 23:12:53.550694 DLL_IDLE_MODE = 1
6162 23:12:53.554242 LP45_APHY_COMB_EN = 1
6163 23:12:53.554322 TX_ODT_DIS = 1
6164 23:12:53.557325 NEW_8X_MODE = 1
6165 23:12:53.561195 ===================================
6166 23:12:53.563817 ===================================
6167 23:12:53.567355 data_rate = 800
6168 23:12:53.570593 CKR = 1
6169 23:12:53.573786 DQ_P2S_RATIO = 4
6170 23:12:53.577050 ===================================
6171 23:12:53.580170 CA_P2S_RATIO = 4
6172 23:12:53.580253 DQ_CA_OPEN = 0
6173 23:12:53.584174 DQ_SEMI_OPEN = 1
6174 23:12:53.586958 CA_SEMI_OPEN = 1
6175 23:12:53.590300 CA_FULL_RATE = 0
6176 23:12:53.594040 DQ_CKDIV4_EN = 0
6177 23:12:53.597190 CA_CKDIV4_EN = 1
6178 23:12:53.597275 CA_PREDIV_EN = 0
6179 23:12:53.600013 PH8_DLY = 0
6180 23:12:53.603577 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6181 23:12:53.606949 DQ_AAMCK_DIV = 0
6182 23:12:53.610556 CA_AAMCK_DIV = 0
6183 23:12:53.613320 CA_ADMCK_DIV = 4
6184 23:12:53.616371 DQ_TRACK_CA_EN = 0
6185 23:12:53.616453 CA_PICK = 800
6186 23:12:53.620270 CA_MCKIO = 400
6187 23:12:53.623775 MCKIO_SEMI = 400
6188 23:12:53.626914 PLL_FREQ = 3016
6189 23:12:53.629719 DQ_UI_PI_RATIO = 32
6190 23:12:53.633234 CA_UI_PI_RATIO = 32
6191 23:12:53.636163 ===================================
6192 23:12:53.639512 ===================================
6193 23:12:53.642718 memory_type:LPDDR4
6194 23:12:53.642800 GP_NUM : 10
6195 23:12:53.646416 SRAM_EN : 1
6196 23:12:53.646499 MD32_EN : 0
6197 23:12:53.649759 ===================================
6198 23:12:53.653248 [ANA_INIT] >>>>>>>>>>>>>>
6199 23:12:53.656293 <<<<<< [CONFIGURE PHASE]: ANA_TX
6200 23:12:53.659806 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6201 23:12:53.664670 ===================================
6202 23:12:53.666025 data_rate = 800,PCW = 0X7400
6203 23:12:53.669492 ===================================
6204 23:12:53.673112 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6205 23:12:53.679068 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6206 23:12:53.689684 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6207 23:12:53.692600 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6208 23:12:53.695390 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6209 23:12:53.702157 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6210 23:12:53.702239 [ANA_INIT] flow start
6211 23:12:53.705582 [ANA_INIT] PLL >>>>>>>>
6212 23:12:53.709489 [ANA_INIT] PLL <<<<<<<<
6213 23:12:53.709571 [ANA_INIT] MIDPI >>>>>>>>
6214 23:12:53.712453 [ANA_INIT] MIDPI <<<<<<<<
6215 23:12:53.715131 [ANA_INIT] DLL >>>>>>>>
6216 23:12:53.715215 [ANA_INIT] flow end
6217 23:12:53.718922 ============ LP4 DIFF to SE enter ============
6218 23:12:53.725159 ============ LP4 DIFF to SE exit ============
6219 23:12:53.725241 [ANA_INIT] <<<<<<<<<<<<<
6220 23:12:53.728859 [Flow] Enable top DCM control >>>>>
6221 23:12:53.732077 [Flow] Enable top DCM control <<<<<
6222 23:12:53.735536 Enable DLL master slave shuffle
6223 23:12:53.741708 ==============================================================
6224 23:12:53.745025 Gating Mode config
6225 23:12:53.748468 ==============================================================
6226 23:12:53.751433 Config description:
6227 23:12:53.762021 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6228 23:12:53.768081 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6229 23:12:53.771466 SELPH_MODE 0: By rank 1: By Phase
6230 23:12:53.778066 ==============================================================
6231 23:12:53.781412 GAT_TRACK_EN = 0
6232 23:12:53.784764 RX_GATING_MODE = 2
6233 23:12:53.788068 RX_GATING_TRACK_MODE = 2
6234 23:12:53.791497 SELPH_MODE = 1
6235 23:12:53.791578 PICG_EARLY_EN = 1
6236 23:12:53.794120 VALID_LAT_VALUE = 1
6237 23:12:53.801270 ==============================================================
6238 23:12:53.804721 Enter into Gating configuration >>>>
6239 23:12:53.807925 Exit from Gating configuration <<<<
6240 23:12:53.811174 Enter into DVFS_PRE_config >>>>>
6241 23:12:53.820620 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6242 23:12:53.823933 Exit from DVFS_PRE_config <<<<<
6243 23:12:53.827220 Enter into PICG configuration >>>>
6244 23:12:53.830554 Exit from PICG configuration <<<<
6245 23:12:53.833886 [RX_INPUT] configuration >>>>>
6246 23:12:53.837571 [RX_INPUT] configuration <<<<<
6247 23:12:53.843525 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6248 23:12:53.846727 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6249 23:12:53.853742 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6250 23:12:53.859869 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6251 23:12:53.866730 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6252 23:12:53.873593 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6253 23:12:53.876363 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6254 23:12:53.879642 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6255 23:12:53.883588 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6256 23:12:53.890167 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6257 23:12:53.893171 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6258 23:12:53.896733 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6259 23:12:53.899535 ===================================
6260 23:12:53.903260 LPDDR4 DRAM CONFIGURATION
6261 23:12:53.906521 ===================================
6262 23:12:53.909410 EX_ROW_EN[0] = 0x0
6263 23:12:53.909491 EX_ROW_EN[1] = 0x0
6264 23:12:53.912981 LP4Y_EN = 0x0
6265 23:12:53.913061 WORK_FSP = 0x0
6266 23:12:53.916546 WL = 0x2
6267 23:12:53.916626 RL = 0x2
6268 23:12:53.919965 BL = 0x2
6269 23:12:53.920044 RPST = 0x0
6270 23:12:53.923496 RD_PRE = 0x0
6271 23:12:53.923575 WR_PRE = 0x1
6272 23:12:53.926088 WR_PST = 0x0
6273 23:12:53.926167 DBI_WR = 0x0
6274 23:12:53.929372 DBI_RD = 0x0
6275 23:12:53.929451 OTF = 0x1
6276 23:12:53.932867 ===================================
6277 23:12:53.939618 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6278 23:12:53.943434 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6279 23:12:53.946140 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6280 23:12:53.949588 ===================================
6281 23:12:53.952965 LPDDR4 DRAM CONFIGURATION
6282 23:12:53.956669 ===================================
6283 23:12:53.959509 EX_ROW_EN[0] = 0x10
6284 23:12:53.959589 EX_ROW_EN[1] = 0x0
6285 23:12:53.962899 LP4Y_EN = 0x0
6286 23:12:53.962978 WORK_FSP = 0x0
6287 23:12:53.965634 WL = 0x2
6288 23:12:53.965713 RL = 0x2
6289 23:12:53.969336 BL = 0x2
6290 23:12:53.969415 RPST = 0x0
6291 23:12:53.972565 RD_PRE = 0x0
6292 23:12:53.972644 WR_PRE = 0x1
6293 23:12:53.975993 WR_PST = 0x0
6294 23:12:53.976073 DBI_WR = 0x0
6295 23:12:53.978941 DBI_RD = 0x0
6296 23:12:53.979021 OTF = 0x1
6297 23:12:53.983028 ===================================
6298 23:12:53.988866 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6299 23:12:53.993556 nWR fixed to 30
6300 23:12:53.996751 [ModeRegInit_LP4] CH0 RK0
6301 23:12:53.996831 [ModeRegInit_LP4] CH0 RK1
6302 23:12:54.000444 [ModeRegInit_LP4] CH1 RK0
6303 23:12:54.004522 [ModeRegInit_LP4] CH1 RK1
6304 23:12:54.004602 match AC timing 19
6305 23:12:54.010479 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6306 23:12:54.013709 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6307 23:12:54.016607 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6308 23:12:54.023553 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6309 23:12:54.026867 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6310 23:12:54.026947 ==
6311 23:12:54.029592 Dram Type= 6, Freq= 0, CH_0, rank 0
6312 23:12:54.032775 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6313 23:12:54.032855 ==
6314 23:12:54.039545 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6315 23:12:54.046243 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6316 23:12:54.049601 [CA 0] Center 36 (8~64) winsize 57
6317 23:12:54.052571 [CA 1] Center 36 (8~64) winsize 57
6318 23:12:54.056449 [CA 2] Center 36 (8~64) winsize 57
6319 23:12:54.059800 [CA 3] Center 36 (8~64) winsize 57
6320 23:12:54.062960 [CA 4] Center 36 (8~64) winsize 57
6321 23:12:54.065867 [CA 5] Center 36 (8~64) winsize 57
6322 23:12:54.065948
6323 23:12:54.069672 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6324 23:12:54.069752
6325 23:12:54.072494 [CATrainingPosCal] consider 1 rank data
6326 23:12:54.075954 u2DelayCellTimex100 = 270/100 ps
6327 23:12:54.079310 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6328 23:12:54.082765 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6329 23:12:54.085806 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6330 23:12:54.089918 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6331 23:12:54.092379 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6332 23:12:54.095761 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6333 23:12:54.095842
6334 23:12:54.102308 CA PerBit enable=1, Macro0, CA PI delay=36
6335 23:12:54.102407
6336 23:12:54.102473 [CBTSetCACLKResult] CA Dly = 36
6337 23:12:54.105756 CS Dly: 1 (0~32)
6338 23:12:54.105861 ==
6339 23:12:54.109117 Dram Type= 6, Freq= 0, CH_0, rank 1
6340 23:12:54.112237 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6341 23:12:54.112318 ==
6342 23:12:54.119790 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6343 23:12:54.125126 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6344 23:12:54.128263 [CA 0] Center 36 (8~64) winsize 57
6345 23:12:54.131894 [CA 1] Center 36 (8~64) winsize 57
6346 23:12:54.135015 [CA 2] Center 36 (8~64) winsize 57
6347 23:12:54.138100 [CA 3] Center 36 (8~64) winsize 57
6348 23:12:54.141452 [CA 4] Center 36 (8~64) winsize 57
6349 23:12:54.145036 [CA 5] Center 36 (8~64) winsize 57
6350 23:12:54.145117
6351 23:12:54.148134 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6352 23:12:54.148214
6353 23:12:54.151837 [CATrainingPosCal] consider 2 rank data
6354 23:12:54.154860 u2DelayCellTimex100 = 270/100 ps
6355 23:12:54.158033 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6356 23:12:54.161175 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6357 23:12:54.164603 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6358 23:12:54.167937 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6359 23:12:54.171145 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6360 23:12:54.174540 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6361 23:12:54.174623
6362 23:12:54.178142 CA PerBit enable=1, Macro0, CA PI delay=36
6363 23:12:54.181207
6364 23:12:54.181286 [CBTSetCACLKResult] CA Dly = 36
6365 23:12:54.185000 CS Dly: 1 (0~32)
6366 23:12:54.185080
6367 23:12:54.187775 ----->DramcWriteLeveling(PI) begin...
6368 23:12:54.187857 ==
6369 23:12:54.191414 Dram Type= 6, Freq= 0, CH_0, rank 0
6370 23:12:54.194607 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6371 23:12:54.194688 ==
6372 23:12:54.197711 Write leveling (Byte 0): 40 => 8
6373 23:12:54.201236 Write leveling (Byte 1): 32 => 0
6374 23:12:54.204092 DramcWriteLeveling(PI) end<-----
6375 23:12:54.204172
6376 23:12:54.204234 ==
6377 23:12:54.207551 Dram Type= 6, Freq= 0, CH_0, rank 0
6378 23:12:54.211313 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6379 23:12:54.213907 ==
6380 23:12:54.213987 [Gating] SW mode calibration
6381 23:12:54.224032 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6382 23:12:54.226980 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6383 23:12:54.230755 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6384 23:12:54.237136 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6385 23:12:54.240202 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6386 23:12:54.243736 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6387 23:12:54.250172 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6388 23:12:54.253899 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6389 23:12:54.256613 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6390 23:12:54.263578 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6391 23:12:54.266998 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6392 23:12:54.270455 Total UI for P1: 0, mck2ui 16
6393 23:12:54.273224 best dqsien dly found for B0: ( 0, 14, 24)
6394 23:12:54.276992 Total UI for P1: 0, mck2ui 16
6395 23:12:54.280607 best dqsien dly found for B1: ( 0, 14, 24)
6396 23:12:54.283202 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6397 23:12:54.286659 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6398 23:12:54.286739
6399 23:12:54.289895 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6400 23:12:54.296427 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6401 23:12:54.296507 [Gating] SW calibration Done
6402 23:12:54.296569 ==
6403 23:12:54.300014 Dram Type= 6, Freq= 0, CH_0, rank 0
6404 23:12:54.306694 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6405 23:12:54.306776 ==
6406 23:12:54.306839 RX Vref Scan: 0
6407 23:12:54.306897
6408 23:12:54.310079 RX Vref 0 -> 0, step: 1
6409 23:12:54.310159
6410 23:12:54.313305 RX Delay -410 -> 252, step: 16
6411 23:12:54.316422 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6412 23:12:54.320301 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6413 23:12:54.326526 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6414 23:12:54.329749 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6415 23:12:54.332744 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6416 23:12:54.336187 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6417 23:12:54.342704 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6418 23:12:54.345935 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6419 23:12:54.349157 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6420 23:12:54.352439 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6421 23:12:54.359256 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6422 23:12:54.362572 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6423 23:12:54.366358 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6424 23:12:54.372237 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6425 23:12:54.375580 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6426 23:12:54.379252 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6427 23:12:54.379331 ==
6428 23:12:54.382210 Dram Type= 6, Freq= 0, CH_0, rank 0
6429 23:12:54.385346 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6430 23:12:54.385440 ==
6431 23:12:54.389682 DQS Delay:
6432 23:12:54.389760 DQS0 = 43, DQS1 = 59
6433 23:12:54.392577 DQM Delay:
6434 23:12:54.392655 DQM0 = 10, DQM1 = 15
6435 23:12:54.395636 DQ Delay:
6436 23:12:54.395782 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6437 23:12:54.398888 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6438 23:12:54.402613 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6439 23:12:54.405810 DQ12 =24, DQ13 =16, DQ14 =24, DQ15 =24
6440 23:12:54.405890
6441 23:12:54.405952
6442 23:12:54.406009 ==
6443 23:12:54.409062 Dram Type= 6, Freq= 0, CH_0, rank 0
6444 23:12:54.415455 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6445 23:12:54.415562 ==
6446 23:12:54.415654
6447 23:12:54.415763
6448 23:12:54.415820 TX Vref Scan disable
6449 23:12:54.419014 == TX Byte 0 ==
6450 23:12:54.422166 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6451 23:12:54.425655 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6452 23:12:54.428987 == TX Byte 1 ==
6453 23:12:54.432605 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6454 23:12:54.435291 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6455 23:12:54.438517 ==
6456 23:12:54.442062 Dram Type= 6, Freq= 0, CH_0, rank 0
6457 23:12:54.445542 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6458 23:12:54.445624 ==
6459 23:12:54.445688
6460 23:12:54.445746
6461 23:12:54.448204 TX Vref Scan disable
6462 23:12:54.448284 == TX Byte 0 ==
6463 23:12:54.451693 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6464 23:12:54.458808 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6465 23:12:54.458889 == TX Byte 1 ==
6466 23:12:54.461385 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6467 23:12:54.468544 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6468 23:12:54.468626
6469 23:12:54.468691 [DATLAT]
6470 23:12:54.468751 Freq=400, CH0 RK0
6471 23:12:54.471492
6472 23:12:54.471597 DATLAT Default: 0xf
6473 23:12:54.475183 0, 0xFFFF, sum = 0
6474 23:12:54.475264 1, 0xFFFF, sum = 0
6475 23:12:54.477886 2, 0xFFFF, sum = 0
6476 23:12:54.477968 3, 0xFFFF, sum = 0
6477 23:12:54.481741 4, 0xFFFF, sum = 0
6478 23:12:54.481822 5, 0xFFFF, sum = 0
6479 23:12:54.485302 6, 0xFFFF, sum = 0
6480 23:12:54.485385 7, 0xFFFF, sum = 0
6481 23:12:54.488470 8, 0xFFFF, sum = 0
6482 23:12:54.488552 9, 0xFFFF, sum = 0
6483 23:12:54.490944 10, 0xFFFF, sum = 0
6484 23:12:54.491025 11, 0xFFFF, sum = 0
6485 23:12:54.494561 12, 0xFFFF, sum = 0
6486 23:12:54.494670 13, 0x0, sum = 1
6487 23:12:54.498799 14, 0x0, sum = 2
6488 23:12:54.498881 15, 0x0, sum = 3
6489 23:12:54.501167 16, 0x0, sum = 4
6490 23:12:54.501249 best_step = 14
6491 23:12:54.501312
6492 23:12:54.501370 ==
6493 23:12:54.504332 Dram Type= 6, Freq= 0, CH_0, rank 0
6494 23:12:54.510930 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6495 23:12:54.511012 ==
6496 23:12:54.511076 RX Vref Scan: 1
6497 23:12:54.511134
6498 23:12:54.514328 RX Vref 0 -> 0, step: 1
6499 23:12:54.514409
6500 23:12:54.517806 RX Delay -359 -> 252, step: 8
6501 23:12:54.517887
6502 23:12:54.520840 Set Vref, RX VrefLevel [Byte0]: 61
6503 23:12:54.524215 [Byte1]: 49
6504 23:12:54.527423
6505 23:12:54.527503 Final RX Vref Byte 0 = 61 to rank0
6506 23:12:54.532161 Final RX Vref Byte 1 = 49 to rank0
6507 23:12:54.534771 Final RX Vref Byte 0 = 61 to rank1
6508 23:12:54.537615 Final RX Vref Byte 1 = 49 to rank1==
6509 23:12:54.541110 Dram Type= 6, Freq= 0, CH_0, rank 0
6510 23:12:54.547328 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6511 23:12:54.547414 ==
6512 23:12:54.547478 DQS Delay:
6513 23:12:54.550582 DQS0 = 48, DQS1 = 60
6514 23:12:54.550663 DQM Delay:
6515 23:12:54.550726 DQM0 = 12, DQM1 = 12
6516 23:12:54.553770 DQ Delay:
6517 23:12:54.557461 DQ0 =12, DQ1 =16, DQ2 =8, DQ3 =8
6518 23:12:54.560461 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6519 23:12:54.563638 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =4
6520 23:12:54.566949 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6521 23:12:54.567029
6522 23:12:54.567092
6523 23:12:54.573676 [DQSOSCAuto] RK0, (LSB)MR18= 0xbe80, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 386 ps
6524 23:12:54.576818 CH0 RK0: MR19=C0C, MR18=BE80
6525 23:12:54.583417 CH0_RK0: MR19=0xC0C, MR18=0xBE80, DQSOSC=386, MR23=63, INC=396, DEC=264
6526 23:12:54.583499 ==
6527 23:12:54.586442 Dram Type= 6, Freq= 0, CH_0, rank 1
6528 23:12:54.590105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6529 23:12:54.590187 ==
6530 23:12:54.593309 [Gating] SW mode calibration
6531 23:12:54.601215 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6532 23:12:54.606601 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6533 23:12:54.609718 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6534 23:12:54.613048 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6535 23:12:54.620241 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6536 23:12:54.622890 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6537 23:12:54.626502 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6538 23:12:54.632749 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6539 23:12:54.636618 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6540 23:12:54.639686 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6541 23:12:54.646037 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6542 23:12:54.649374 Total UI for P1: 0, mck2ui 16
6543 23:12:54.652624 best dqsien dly found for B0: ( 0, 14, 24)
6544 23:12:54.655906 Total UI for P1: 0, mck2ui 16
6545 23:12:54.659083 best dqsien dly found for B1: ( 0, 14, 24)
6546 23:12:54.662129 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6547 23:12:54.665393 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6548 23:12:54.665496
6549 23:12:54.668691 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6550 23:12:54.671989 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6551 23:12:54.675270 [Gating] SW calibration Done
6552 23:12:54.675351 ==
6553 23:12:54.678876 Dram Type= 6, Freq= 0, CH_0, rank 1
6554 23:12:54.681878 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6555 23:12:54.685371 ==
6556 23:12:54.685451 RX Vref Scan: 0
6557 23:12:54.685515
6558 23:12:54.688933 RX Vref 0 -> 0, step: 1
6559 23:12:54.689014
6560 23:12:54.691848 RX Delay -410 -> 252, step: 16
6561 23:12:54.695213 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6562 23:12:54.698609 iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512
6563 23:12:54.701769 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6564 23:12:54.708305 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6565 23:12:54.711746 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6566 23:12:54.715191 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6567 23:12:54.718165 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6568 23:12:54.725128 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6569 23:12:54.727908 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6570 23:12:54.732084 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6571 23:12:54.737755 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6572 23:12:54.741691 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6573 23:12:54.744609 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6574 23:12:54.747835 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6575 23:12:54.754360 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6576 23:12:54.757788 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6577 23:12:54.757869 ==
6578 23:12:54.761440 Dram Type= 6, Freq= 0, CH_0, rank 1
6579 23:12:54.764729 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6580 23:12:54.764811 ==
6581 23:12:54.767621 DQS Delay:
6582 23:12:54.767757 DQS0 = 43, DQS1 = 59
6583 23:12:54.770804 DQM Delay:
6584 23:12:54.770884 DQM0 = 10, DQM1 = 16
6585 23:12:54.770947 DQ Delay:
6586 23:12:54.774365 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6587 23:12:54.778172 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6588 23:12:54.781136 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6589 23:12:54.784290 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6590 23:12:54.784371
6591 23:12:54.784434
6592 23:12:54.784493 ==
6593 23:12:54.787878 Dram Type= 6, Freq= 0, CH_0, rank 1
6594 23:12:54.793987 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6595 23:12:54.794068 ==
6596 23:12:54.794131
6597 23:12:54.794189
6598 23:12:54.794243 TX Vref Scan disable
6599 23:12:54.799869 == TX Byte 0 ==
6600 23:12:54.801262 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6601 23:12:54.803865 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6602 23:12:54.807463 == TX Byte 1 ==
6603 23:12:54.810471 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6604 23:12:54.814210 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6605 23:12:54.814291 ==
6606 23:12:54.817634 Dram Type= 6, Freq= 0, CH_0, rank 1
6607 23:12:54.824096 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6608 23:12:54.824182 ==
6609 23:12:54.824246
6610 23:12:54.824304
6611 23:12:54.824359 TX Vref Scan disable
6612 23:12:54.827168 == TX Byte 0 ==
6613 23:12:54.830421 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6614 23:12:54.834261 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6615 23:12:54.836864 == TX Byte 1 ==
6616 23:12:54.840511 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6617 23:12:54.843870 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6618 23:12:54.843949
6619 23:12:54.847052 [DATLAT]
6620 23:12:54.847131 Freq=400, CH0 RK1
6621 23:12:54.847195
6622 23:12:54.850258 DATLAT Default: 0xe
6623 23:12:54.850338 0, 0xFFFF, sum = 0
6624 23:12:54.853770 1, 0xFFFF, sum = 0
6625 23:12:54.853851 2, 0xFFFF, sum = 0
6626 23:12:54.857459 3, 0xFFFF, sum = 0
6627 23:12:54.857540 4, 0xFFFF, sum = 0
6628 23:12:54.860112 5, 0xFFFF, sum = 0
6629 23:12:54.860193 6, 0xFFFF, sum = 0
6630 23:12:54.864239 7, 0xFFFF, sum = 0
6631 23:12:54.867078 8, 0xFFFF, sum = 0
6632 23:12:54.867159 9, 0xFFFF, sum = 0
6633 23:12:54.870654 10, 0xFFFF, sum = 0
6634 23:12:54.870735 11, 0xFFFF, sum = 0
6635 23:12:54.873464 12, 0xFFFF, sum = 0
6636 23:12:54.873545 13, 0x0, sum = 1
6637 23:12:54.876698 14, 0x0, sum = 2
6638 23:12:54.876780 15, 0x0, sum = 3
6639 23:12:54.880196 16, 0x0, sum = 4
6640 23:12:54.880277 best_step = 14
6641 23:12:54.880340
6642 23:12:54.880399 ==
6643 23:12:54.883334 Dram Type= 6, Freq= 0, CH_0, rank 1
6644 23:12:54.887093 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6645 23:12:54.887174 ==
6646 23:12:54.889809 RX Vref Scan: 0
6647 23:12:54.889889
6648 23:12:54.893996 RX Vref 0 -> 0, step: 1
6649 23:12:54.894076
6650 23:12:54.894138 RX Delay -359 -> 252, step: 8
6651 23:12:54.901978 iDelay=217, Bit 0, Center -40 (-279 ~ 200) 480
6652 23:12:54.905197 iDelay=217, Bit 1, Center -36 (-279 ~ 208) 488
6653 23:12:54.908718 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6654 23:12:54.915579 iDelay=217, Bit 3, Center -40 (-287 ~ 208) 496
6655 23:12:54.918562 iDelay=217, Bit 4, Center -32 (-271 ~ 208) 480
6656 23:12:54.922058 iDelay=217, Bit 5, Center -44 (-287 ~ 200) 488
6657 23:12:54.925048 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6658 23:12:54.932039 iDelay=217, Bit 7, Center -28 (-271 ~ 216) 488
6659 23:12:54.935272 iDelay=217, Bit 8, Center -52 (-295 ~ 192) 488
6660 23:12:54.938395 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6661 23:12:54.941884 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6662 23:12:54.948396 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6663 23:12:54.951634 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6664 23:12:54.954876 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6665 23:12:54.958412 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6666 23:12:54.965524 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6667 23:12:54.965608 ==
6668 23:12:54.968393 Dram Type= 6, Freq= 0, CH_0, rank 1
6669 23:12:54.971428 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6670 23:12:54.971510 ==
6671 23:12:54.971576 DQS Delay:
6672 23:12:54.974877 DQS0 = 44, DQS1 = 60
6673 23:12:54.974957 DQM Delay:
6674 23:12:54.978109 DQM0 = 8, DQM1 = 15
6675 23:12:54.978190 DQ Delay:
6676 23:12:54.981292 DQ0 =4, DQ1 =8, DQ2 =4, DQ3 =4
6677 23:12:54.985166 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =16
6678 23:12:54.987954 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6679 23:12:54.991453 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =24
6680 23:12:54.991559
6681 23:12:54.991650
6682 23:12:54.997880 [DQSOSCAuto] RK1, (LSB)MR18= 0xb643, (MSB)MR19= 0xc0c, tDQSOscB0 = 401 ps tDQSOscB1 = 387 ps
6683 23:12:55.001329 CH0 RK1: MR19=C0C, MR18=B643
6684 23:12:55.007657 CH0_RK1: MR19=0xC0C, MR18=0xB643, DQSOSC=387, MR23=63, INC=394, DEC=262
6685 23:12:55.011725 [RxdqsGatingPostProcess] freq 400
6686 23:12:55.017951 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6687 23:12:55.020994 best DQS0 dly(2T, 0.5T) = (0, 10)
6688 23:12:55.024177 best DQS1 dly(2T, 0.5T) = (0, 10)
6689 23:12:55.024258 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6690 23:12:55.027972 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6691 23:12:55.030612 best DQS0 dly(2T, 0.5T) = (0, 10)
6692 23:12:55.034390 best DQS1 dly(2T, 0.5T) = (0, 10)
6693 23:12:55.037277 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6694 23:12:55.041150 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6695 23:12:55.043968 Pre-setting of DQS Precalculation
6696 23:12:55.050529 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6697 23:12:55.050610 ==
6698 23:12:55.053915 Dram Type= 6, Freq= 0, CH_1, rank 0
6699 23:12:55.057215 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6700 23:12:55.057297 ==
6701 23:12:55.063705 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6702 23:12:55.070204 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6703 23:12:55.073337 [CA 0] Center 36 (8~64) winsize 57
6704 23:12:55.073417 [CA 1] Center 36 (8~64) winsize 57
6705 23:12:55.077364 [CA 2] Center 36 (8~64) winsize 57
6706 23:12:55.080357 [CA 3] Center 36 (8~64) winsize 57
6707 23:12:55.083238 [CA 4] Center 36 (8~64) winsize 57
6708 23:12:55.087076 [CA 5] Center 36 (8~64) winsize 57
6709 23:12:55.087157
6710 23:12:55.090034 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6711 23:12:55.093861
6712 23:12:55.096536 [CATrainingPosCal] consider 1 rank data
6713 23:12:55.096617 u2DelayCellTimex100 = 270/100 ps
6714 23:12:55.103240 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6715 23:12:55.106361 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6716 23:12:55.110009 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6717 23:12:55.113528 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6718 23:12:55.116658 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6719 23:12:55.119445 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6720 23:12:55.119558
6721 23:12:55.122989 CA PerBit enable=1, Macro0, CA PI delay=36
6722 23:12:55.123069
6723 23:12:55.126251 [CBTSetCACLKResult] CA Dly = 36
6724 23:12:55.129702 CS Dly: 1 (0~32)
6725 23:12:55.129782 ==
6726 23:12:55.133362 Dram Type= 6, Freq= 0, CH_1, rank 1
6727 23:12:55.136676 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6728 23:12:55.136757 ==
6729 23:12:55.142805 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6730 23:12:55.146441 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6731 23:12:55.149427 [CA 0] Center 36 (8~64) winsize 57
6732 23:12:55.152448 [CA 1] Center 36 (8~64) winsize 57
6733 23:12:55.156131 [CA 2] Center 36 (8~64) winsize 57
6734 23:12:55.159395 [CA 3] Center 36 (8~64) winsize 57
6735 23:12:55.162993 [CA 4] Center 36 (8~64) winsize 57
6736 23:12:55.166114 [CA 5] Center 36 (8~64) winsize 57
6737 23:12:55.166195
6738 23:12:55.169655 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6739 23:12:55.169735
6740 23:12:55.172707 [CATrainingPosCal] consider 2 rank data
6741 23:12:55.175689 u2DelayCellTimex100 = 270/100 ps
6742 23:12:55.179181 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6743 23:12:55.186016 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6744 23:12:55.188897 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6745 23:12:55.193116 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6746 23:12:55.196030 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6747 23:12:55.199118 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6748 23:12:55.199199
6749 23:12:55.202272 CA PerBit enable=1, Macro0, CA PI delay=36
6750 23:12:55.202353
6751 23:12:55.205596 [CBTSetCACLKResult] CA Dly = 36
6752 23:12:55.205675 CS Dly: 1 (0~32)
6753 23:12:55.208595
6754 23:12:55.211829 ----->DramcWriteLeveling(PI) begin...
6755 23:12:55.211911 ==
6756 23:12:55.215867 Dram Type= 6, Freq= 0, CH_1, rank 0
6757 23:12:55.218869 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6758 23:12:55.218949 ==
6759 23:12:55.222227 Write leveling (Byte 0): 40 => 8
6760 23:12:55.225367 Write leveling (Byte 1): 32 => 0
6761 23:12:55.228615 DramcWriteLeveling(PI) end<-----
6762 23:12:55.228694
6763 23:12:55.228757 ==
6764 23:12:55.232080 Dram Type= 6, Freq= 0, CH_1, rank 0
6765 23:12:55.235191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6766 23:12:55.235268 ==
6767 23:12:55.238487 [Gating] SW mode calibration
6768 23:12:55.244915 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6769 23:12:55.252315 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6770 23:12:55.255085 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6771 23:12:55.258340 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6772 23:12:55.264624 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6773 23:12:55.268004 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6774 23:12:55.271513 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6775 23:12:55.277810 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6776 23:12:55.281461 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6777 23:12:55.284455 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6778 23:12:55.290878 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6779 23:12:55.294746 Total UI for P1: 0, mck2ui 16
6780 23:12:55.297473 best dqsien dly found for B0: ( 0, 14, 24)
6781 23:12:55.297557 Total UI for P1: 0, mck2ui 16
6782 23:12:55.304271 best dqsien dly found for B1: ( 0, 14, 24)
6783 23:12:55.307308 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6784 23:12:55.310731 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6785 23:12:55.310812
6786 23:12:55.314370 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6787 23:12:55.317717 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6788 23:12:55.321199 [Gating] SW calibration Done
6789 23:12:55.321279 ==
6790 23:12:55.324340 Dram Type= 6, Freq= 0, CH_1, rank 0
6791 23:12:55.327589 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6792 23:12:55.327678 ==
6793 23:12:55.330528 RX Vref Scan: 0
6794 23:12:55.330608
6795 23:12:55.333943 RX Vref 0 -> 0, step: 1
6796 23:12:55.334024
6797 23:12:55.334087 RX Delay -410 -> 252, step: 16
6798 23:12:55.340302 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6799 23:12:55.344240 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6800 23:12:55.347124 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6801 23:12:55.353619 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6802 23:12:55.356798 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6803 23:12:55.360684 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6804 23:12:55.363836 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6805 23:12:55.370031 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6806 23:12:55.373847 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6807 23:12:55.377285 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6808 23:12:55.380355 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6809 23:12:55.386406 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6810 23:12:55.390376 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6811 23:12:55.393512 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6812 23:12:55.396452 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6813 23:12:55.402878 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6814 23:12:55.402958 ==
6815 23:12:55.406893 Dram Type= 6, Freq= 0, CH_1, rank 0
6816 23:12:55.409831 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6817 23:12:55.409913 ==
6818 23:12:55.412973 DQS Delay:
6819 23:12:55.413054 DQS0 = 43, DQS1 = 51
6820 23:12:55.413116 DQM Delay:
6821 23:12:55.416166 DQM0 = 12, DQM1 = 14
6822 23:12:55.416247 DQ Delay:
6823 23:12:55.420333 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6824 23:12:55.423013 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6825 23:12:55.425966 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6826 23:12:55.430070 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6827 23:12:55.430151
6828 23:12:55.430213
6829 23:12:55.430271 ==
6830 23:12:55.432658 Dram Type= 6, Freq= 0, CH_1, rank 0
6831 23:12:55.436706 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6832 23:12:55.439471 ==
6833 23:12:55.439552
6834 23:12:55.439614
6835 23:12:55.439681 TX Vref Scan disable
6836 23:12:55.442501 == TX Byte 0 ==
6837 23:12:55.445883 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6838 23:12:55.449637 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6839 23:12:55.452916 == TX Byte 1 ==
6840 23:12:55.455695 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6841 23:12:55.459742 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6842 23:12:55.459823 ==
6843 23:12:55.462355 Dram Type= 6, Freq= 0, CH_1, rank 0
6844 23:12:55.468943 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6845 23:12:55.469024 ==
6846 23:12:55.469087
6847 23:12:55.469145
6848 23:12:55.469201 TX Vref Scan disable
6849 23:12:55.472337 == TX Byte 0 ==
6850 23:12:55.476023 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6851 23:12:55.478775 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6852 23:12:55.482114 == TX Byte 1 ==
6853 23:12:55.485209 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6854 23:12:55.488576 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6855 23:12:55.488657
6856 23:12:55.492132 [DATLAT]
6857 23:12:55.492212 Freq=400, CH1 RK0
6858 23:12:55.492276
6859 23:12:55.495159 DATLAT Default: 0xf
6860 23:12:55.495239 0, 0xFFFF, sum = 0
6861 23:12:55.498332 1, 0xFFFF, sum = 0
6862 23:12:55.498414 2, 0xFFFF, sum = 0
6863 23:12:55.501684 3, 0xFFFF, sum = 0
6864 23:12:55.501766 4, 0xFFFF, sum = 0
6865 23:12:55.505282 5, 0xFFFF, sum = 0
6866 23:12:55.508610 6, 0xFFFF, sum = 0
6867 23:12:55.508691 7, 0xFFFF, sum = 0
6868 23:12:55.511652 8, 0xFFFF, sum = 0
6869 23:12:55.511771 9, 0xFFFF, sum = 0
6870 23:12:55.515293 10, 0xFFFF, sum = 0
6871 23:12:55.515373 11, 0xFFFF, sum = 0
6872 23:12:55.518530 12, 0xFFFF, sum = 0
6873 23:12:55.518610 13, 0x0, sum = 1
6874 23:12:55.521993 14, 0x0, sum = 2
6875 23:12:55.522074 15, 0x0, sum = 3
6876 23:12:55.524827 16, 0x0, sum = 4
6877 23:12:55.524908 best_step = 14
6878 23:12:55.524969
6879 23:12:55.525026 ==
6880 23:12:55.528386 Dram Type= 6, Freq= 0, CH_1, rank 0
6881 23:12:55.531653 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6882 23:12:55.531767 ==
6883 23:12:55.534862 RX Vref Scan: 1
6884 23:12:55.534941
6885 23:12:55.538257 RX Vref 0 -> 0, step: 1
6886 23:12:55.538337
6887 23:12:55.538399 RX Delay -343 -> 252, step: 8
6888 23:12:55.541298
6889 23:12:55.541377 Set Vref, RX VrefLevel [Byte0]: 50
6890 23:12:55.544977 [Byte1]: 51
6891 23:12:55.550500
6892 23:12:55.550580 Final RX Vref Byte 0 = 50 to rank0
6893 23:12:55.554364 Final RX Vref Byte 1 = 51 to rank0
6894 23:12:55.557936 Final RX Vref Byte 0 = 50 to rank1
6895 23:12:55.560515 Final RX Vref Byte 1 = 51 to rank1==
6896 23:12:55.564295 Dram Type= 6, Freq= 0, CH_1, rank 0
6897 23:12:55.570459 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6898 23:12:55.570540 ==
6899 23:12:55.570603 DQS Delay:
6900 23:12:55.573309 DQS0 = 44, DQS1 = 52
6901 23:12:55.573388 DQM Delay:
6902 23:12:55.573451 DQM0 = 9, DQM1 = 9
6903 23:12:55.577703 DQ Delay:
6904 23:12:55.580496 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =4
6905 23:12:55.580575 DQ4 =8, DQ5 =20, DQ6 =16, DQ7 =4
6906 23:12:55.583259 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =0
6907 23:12:55.586951 DQ12 =16, DQ13 =12, DQ14 =16, DQ15 =16
6908 23:12:55.587030
6909 23:12:55.590350
6910 23:12:55.596734 [DQSOSCAuto] RK0, (LSB)MR18= 0x9b71, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 390 ps
6911 23:12:55.599641 CH1 RK0: MR19=C0C, MR18=9B71
6912 23:12:55.606308 CH1_RK0: MR19=0xC0C, MR18=0x9B71, DQSOSC=390, MR23=63, INC=388, DEC=258
6913 23:12:55.606389 ==
6914 23:12:55.609650 Dram Type= 6, Freq= 0, CH_1, rank 1
6915 23:12:55.613229 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6916 23:12:55.613309 ==
6917 23:12:55.616202 [Gating] SW mode calibration
6918 23:12:55.622789 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6919 23:12:55.629388 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6920 23:12:55.633103 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6921 23:12:55.635647 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6922 23:12:55.642489 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6923 23:12:55.645735 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6924 23:12:55.648990 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6925 23:12:55.655437 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6926 23:12:55.659254 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6927 23:12:55.662132 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6928 23:12:55.668631 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6929 23:12:55.672040 Total UI for P1: 0, mck2ui 16
6930 23:12:55.675365 best dqsien dly found for B0: ( 0, 14, 24)
6931 23:12:55.678531 Total UI for P1: 0, mck2ui 16
6932 23:12:55.681685 best dqsien dly found for B1: ( 0, 14, 24)
6933 23:12:55.685387 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6934 23:12:55.688512 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6935 23:12:55.688591
6936 23:12:55.691977 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6937 23:12:55.695579 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6938 23:12:55.698304 [Gating] SW calibration Done
6939 23:12:55.698383 ==
6940 23:12:55.701529 Dram Type= 6, Freq= 0, CH_1, rank 1
6941 23:12:55.704552 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6942 23:12:55.704632 ==
6943 23:12:55.707923 RX Vref Scan: 0
6944 23:12:55.708018
6945 23:12:55.711272 RX Vref 0 -> 0, step: 1
6946 23:12:55.711351
6947 23:12:55.714808 RX Delay -410 -> 252, step: 16
6948 23:12:55.717954 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6949 23:12:55.720991 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6950 23:12:55.724546 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6951 23:12:55.730855 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6952 23:12:55.734285 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6953 23:12:55.737682 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6954 23:12:55.740644 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6955 23:12:55.747717 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6956 23:12:55.751244 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6957 23:12:55.754400 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6958 23:12:55.757148 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6959 23:12:55.763876 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6960 23:12:55.767879 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6961 23:12:55.770527 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6962 23:12:55.777198 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6963 23:12:55.780653 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6964 23:12:55.780733 ==
6965 23:12:55.783793 Dram Type= 6, Freq= 0, CH_1, rank 1
6966 23:12:55.787306 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6967 23:12:55.787387 ==
6968 23:12:55.790512 DQS Delay:
6969 23:12:55.790592 DQS0 = 51, DQS1 = 51
6970 23:12:55.793530 DQM Delay:
6971 23:12:55.793610 DQM0 = 19, DQM1 = 14
6972 23:12:55.793673 DQ Delay:
6973 23:12:55.797620 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6974 23:12:55.800519 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6975 23:12:55.803549 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6976 23:12:55.806657 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6977 23:12:55.806737
6978 23:12:55.806799
6979 23:12:55.806857 ==
6980 23:12:55.810158 Dram Type= 6, Freq= 0, CH_1, rank 1
6981 23:12:55.816736 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6982 23:12:55.816817 ==
6983 23:12:55.816880
6984 23:12:55.816939
6985 23:12:55.816995 TX Vref Scan disable
6986 23:12:55.820490 == TX Byte 0 ==
6987 23:12:55.823046 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6988 23:12:55.826303 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6989 23:12:55.829712 == TX Byte 1 ==
6990 23:12:55.833210 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6991 23:12:55.836431 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6992 23:12:55.840219 ==
6993 23:12:55.840300 Dram Type= 6, Freq= 0, CH_1, rank 1
6994 23:12:55.846457 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6995 23:12:55.846562 ==
6996 23:12:55.846647
6997 23:12:55.846707
6998 23:12:55.849664 TX Vref Scan disable
6999 23:12:55.849744 == TX Byte 0 ==
7000 23:12:55.853112 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
7001 23:12:55.859981 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
7002 23:12:55.860062 == TX Byte 1 ==
7003 23:12:55.864044 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
7004 23:12:55.866043 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
7005 23:12:55.869357
7006 23:12:55.869437 [DATLAT]
7007 23:12:55.869500 Freq=400, CH1 RK1
7008 23:12:55.869560
7009 23:12:55.872684 DATLAT Default: 0xe
7010 23:12:55.872764 0, 0xFFFF, sum = 0
7011 23:12:55.876081 1, 0xFFFF, sum = 0
7012 23:12:55.876162 2, 0xFFFF, sum = 0
7013 23:12:55.879853 3, 0xFFFF, sum = 0
7014 23:12:55.882403 4, 0xFFFF, sum = 0
7015 23:12:55.882484 5, 0xFFFF, sum = 0
7016 23:12:55.885816 6, 0xFFFF, sum = 0
7017 23:12:55.885897 7, 0xFFFF, sum = 0
7018 23:12:55.889264 8, 0xFFFF, sum = 0
7019 23:12:55.889345 9, 0xFFFF, sum = 0
7020 23:12:55.892767 10, 0xFFFF, sum = 0
7021 23:12:55.892848 11, 0xFFFF, sum = 0
7022 23:12:55.895825 12, 0xFFFF, sum = 0
7023 23:12:55.895906 13, 0x0, sum = 1
7024 23:12:55.899184 14, 0x0, sum = 2
7025 23:12:55.899265 15, 0x0, sum = 3
7026 23:12:55.902814 16, 0x0, sum = 4
7027 23:12:55.902896 best_step = 14
7028 23:12:55.902959
7029 23:12:55.903017 ==
7030 23:12:55.905863 Dram Type= 6, Freq= 0, CH_1, rank 1
7031 23:12:55.908886 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7032 23:12:55.912313 ==
7033 23:12:55.912393 RX Vref Scan: 0
7034 23:12:55.912457
7035 23:12:55.915860 RX Vref 0 -> 0, step: 1
7036 23:12:55.915940
7037 23:12:55.918741 RX Delay -343 -> 252, step: 8
7038 23:12:55.925371 iDelay=225, Bit 0, Center -28 (-271 ~ 216) 488
7039 23:12:55.928772 iDelay=225, Bit 1, Center -40 (-279 ~ 200) 480
7040 23:12:55.932363 iDelay=225, Bit 2, Center -44 (-287 ~ 200) 488
7041 23:12:55.935244 iDelay=225, Bit 3, Center -36 (-271 ~ 200) 472
7042 23:12:55.941900 iDelay=225, Bit 4, Center -36 (-279 ~ 208) 488
7043 23:12:55.944894 iDelay=225, Bit 5, Center -24 (-263 ~ 216) 480
7044 23:12:55.948631 iDelay=225, Bit 6, Center -24 (-271 ~ 224) 496
7045 23:12:55.951379 iDelay=225, Bit 7, Center -36 (-279 ~ 208) 488
7046 23:12:55.958307 iDelay=225, Bit 8, Center -56 (-303 ~ 192) 496
7047 23:12:55.961730 iDelay=225, Bit 9, Center -56 (-303 ~ 192) 496
7048 23:12:55.965238 iDelay=225, Bit 10, Center -44 (-287 ~ 200) 488
7049 23:12:55.968360 iDelay=225, Bit 11, Center -52 (-295 ~ 192) 488
7050 23:12:55.975336 iDelay=225, Bit 12, Center -36 (-287 ~ 216) 504
7051 23:12:55.978275 iDelay=225, Bit 13, Center -36 (-279 ~ 208) 488
7052 23:12:55.981149 iDelay=225, Bit 14, Center -40 (-287 ~ 208) 496
7053 23:12:55.987783 iDelay=225, Bit 15, Center -32 (-279 ~ 216) 496
7054 23:12:55.987864 ==
7055 23:12:55.991635 Dram Type= 6, Freq= 0, CH_1, rank 1
7056 23:12:55.994472 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7057 23:12:55.994553 ==
7058 23:12:55.994634 DQS Delay:
7059 23:12:55.997942 DQS0 = 44, DQS1 = 56
7060 23:12:55.998023 DQM Delay:
7061 23:12:56.001427 DQM0 = 10, DQM1 = 12
7062 23:12:56.001507 DQ Delay:
7063 23:12:56.004707 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =8
7064 23:12:56.008133 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =8
7065 23:12:56.010671 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
7066 23:12:56.013917 DQ12 =20, DQ13 =20, DQ14 =16, DQ15 =24
7067 23:12:56.013997
7068 23:12:56.014060
7069 23:12:56.020465 [DQSOSCAuto] RK1, (LSB)MR18= 0x6c5c, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 396 ps
7070 23:12:56.024721 CH1 RK1: MR19=C0C, MR18=6C5C
7071 23:12:56.030779 CH1_RK1: MR19=0xC0C, MR18=0x6C5C, DQSOSC=396, MR23=63, INC=376, DEC=251
7072 23:12:56.033612 [RxdqsGatingPostProcess] freq 400
7073 23:12:56.040574 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7074 23:12:56.043962 best DQS0 dly(2T, 0.5T) = (0, 10)
7075 23:12:56.047116 best DQS1 dly(2T, 0.5T) = (0, 10)
7076 23:12:56.050645 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7077 23:12:56.053419 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7078 23:12:56.053499 best DQS0 dly(2T, 0.5T) = (0, 10)
7079 23:12:56.057006 best DQS1 dly(2T, 0.5T) = (0, 10)
7080 23:12:56.060249 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7081 23:12:56.063598 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7082 23:12:56.066850 Pre-setting of DQS Precalculation
7083 23:12:56.073768 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7084 23:12:56.079951 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7085 23:12:56.086612 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7086 23:12:56.086695
7087 23:12:56.086759
7088 23:12:56.089869 [Calibration Summary] 800 Mbps
7089 23:12:56.089949 CH 0, Rank 0
7090 23:12:56.093118 SW Impedance : PASS
7091 23:12:56.096781 DUTY Scan : NO K
7092 23:12:56.096861 ZQ Calibration : PASS
7093 23:12:56.099540 Jitter Meter : NO K
7094 23:12:56.103354 CBT Training : PASS
7095 23:12:56.103434 Write leveling : PASS
7096 23:12:56.106732 RX DQS gating : PASS
7097 23:12:56.109867 RX DQ/DQS(RDDQC) : PASS
7098 23:12:56.109947 TX DQ/DQS : PASS
7099 23:12:56.112797 RX DATLAT : PASS
7100 23:12:56.116622 RX DQ/DQS(Engine): PASS
7101 23:12:56.116702 TX OE : NO K
7102 23:12:56.119458 All Pass.
7103 23:12:56.119538
7104 23:12:56.119601 CH 0, Rank 1
7105 23:12:56.122855 SW Impedance : PASS
7106 23:12:56.122936 DUTY Scan : NO K
7107 23:12:56.126052 ZQ Calibration : PASS
7108 23:12:56.130034 Jitter Meter : NO K
7109 23:12:56.130114 CBT Training : PASS
7110 23:12:56.132750 Write leveling : NO K
7111 23:12:56.136707 RX DQS gating : PASS
7112 23:12:56.136788 RX DQ/DQS(RDDQC) : PASS
7113 23:12:56.139530 TX DQ/DQS : PASS
7114 23:12:56.139610 RX DATLAT : PASS
7115 23:12:56.142921 RX DQ/DQS(Engine): PASS
7116 23:12:56.145877 TX OE : NO K
7117 23:12:56.145957 All Pass.
7118 23:12:56.146020
7119 23:12:56.146077 CH 1, Rank 0
7120 23:12:56.149330 SW Impedance : PASS
7121 23:12:56.152572 DUTY Scan : NO K
7122 23:12:56.152653 ZQ Calibration : PASS
7123 23:12:56.155958 Jitter Meter : NO K
7124 23:12:56.158963 CBT Training : PASS
7125 23:12:56.159044 Write leveling : PASS
7126 23:12:56.162839 RX DQS gating : PASS
7127 23:12:56.165701 RX DQ/DQS(RDDQC) : PASS
7128 23:12:56.165781 TX DQ/DQS : PASS
7129 23:12:56.168829 RX DATLAT : PASS
7130 23:12:56.172340 RX DQ/DQS(Engine): PASS
7131 23:12:56.172419 TX OE : NO K
7132 23:12:56.175584 All Pass.
7133 23:12:56.175713
7134 23:12:56.175792 CH 1, Rank 1
7135 23:12:56.178704 SW Impedance : PASS
7136 23:12:56.178783 DUTY Scan : NO K
7137 23:12:56.182226 ZQ Calibration : PASS
7138 23:12:56.185732 Jitter Meter : NO K
7139 23:12:56.185812 CBT Training : PASS
7140 23:12:56.188699 Write leveling : NO K
7141 23:12:56.192007 RX DQS gating : PASS
7142 23:12:56.192086 RX DQ/DQS(RDDQC) : PASS
7143 23:12:56.195297 TX DQ/DQS : PASS
7144 23:12:56.198600 RX DATLAT : PASS
7145 23:12:56.198680 RX DQ/DQS(Engine): PASS
7146 23:12:56.202120 TX OE : NO K
7147 23:12:56.202201 All Pass.
7148 23:12:56.202263
7149 23:12:56.205431 DramC Write-DBI off
7150 23:12:56.208423 PER_BANK_REFRESH: Hybrid Mode
7151 23:12:56.208504 TX_TRACKING: ON
7152 23:12:56.219165 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7153 23:12:56.222110 [FAST_K] Save calibration result to emmc
7154 23:12:56.225650 dramc_set_vcore_voltage set vcore to 725000
7155 23:12:56.228558 Read voltage for 1600, 0
7156 23:12:56.228638 Vio18 = 0
7157 23:12:56.228702 Vcore = 725000
7158 23:12:56.231555 Vdram = 0
7159 23:12:56.231660 Vddq = 0
7160 23:12:56.231778 Vmddr = 0
7161 23:12:56.237889 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7162 23:12:56.241575 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7163 23:12:56.245046 MEM_TYPE=3, freq_sel=13
7164 23:12:56.247846 sv_algorithm_assistance_LP4_3733
7165 23:12:56.251123 ============ PULL DRAM RESETB DOWN ============
7166 23:12:56.258350 ========== PULL DRAM RESETB DOWN end =========
7167 23:12:56.261023 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7168 23:12:56.264551 ===================================
7169 23:12:56.267799 LPDDR4 DRAM CONFIGURATION
7170 23:12:56.271801 ===================================
7171 23:12:56.271881 EX_ROW_EN[0] = 0x0
7172 23:12:56.274718 EX_ROW_EN[1] = 0x0
7173 23:12:56.274797 LP4Y_EN = 0x0
7174 23:12:56.277911 WORK_FSP = 0x1
7175 23:12:56.277991 WL = 0x5
7176 23:12:56.281211 RL = 0x5
7177 23:12:56.284819 BL = 0x2
7178 23:12:56.284898 RPST = 0x0
7179 23:12:56.288496 RD_PRE = 0x0
7180 23:12:56.288577 WR_PRE = 0x1
7181 23:12:56.290639 WR_PST = 0x1
7182 23:12:56.290718 DBI_WR = 0x0
7183 23:12:56.294894 DBI_RD = 0x0
7184 23:12:56.294974 OTF = 0x1
7185 23:12:56.297153 ===================================
7186 23:12:56.300642 ===================================
7187 23:12:56.304292 ANA top config
7188 23:12:56.308593 ===================================
7189 23:12:56.308699 DLL_ASYNC_EN = 0
7190 23:12:56.311035 ALL_SLAVE_EN = 0
7191 23:12:56.314041 NEW_RANK_MODE = 1
7192 23:12:56.317992 DLL_IDLE_MODE = 1
7193 23:12:56.318076 LP45_APHY_COMB_EN = 1
7194 23:12:56.320578 TX_ODT_DIS = 0
7195 23:12:56.323658 NEW_8X_MODE = 1
7196 23:12:56.326987 ===================================
7197 23:12:56.330328 ===================================
7198 23:12:56.333764 data_rate = 3200
7199 23:12:56.337501 CKR = 1
7200 23:12:56.340454 DQ_P2S_RATIO = 8
7201 23:12:56.343615 ===================================
7202 23:12:56.343735 CA_P2S_RATIO = 8
7203 23:12:56.346619 DQ_CA_OPEN = 0
7204 23:12:56.350099 DQ_SEMI_OPEN = 0
7205 23:12:56.353349 CA_SEMI_OPEN = 0
7206 23:12:56.357121 CA_FULL_RATE = 0
7207 23:12:56.360012 DQ_CKDIV4_EN = 0
7208 23:12:56.360092 CA_CKDIV4_EN = 0
7209 23:12:56.363473 CA_PREDIV_EN = 0
7210 23:12:56.366827 PH8_DLY = 12
7211 23:12:56.370027 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7212 23:12:56.373185 DQ_AAMCK_DIV = 4
7213 23:12:56.376420 CA_AAMCK_DIV = 4
7214 23:12:56.376500 CA_ADMCK_DIV = 4
7215 23:12:56.379421 DQ_TRACK_CA_EN = 0
7216 23:12:56.383043 CA_PICK = 1600
7217 23:12:56.386464 CA_MCKIO = 1600
7218 23:12:56.389530 MCKIO_SEMI = 0
7219 23:12:56.393177 PLL_FREQ = 3068
7220 23:12:56.396507 DQ_UI_PI_RATIO = 32
7221 23:12:56.399652 CA_UI_PI_RATIO = 0
7222 23:12:56.402822 ===================================
7223 23:12:56.406174 ===================================
7224 23:12:56.406255 memory_type:LPDDR4
7225 23:12:56.409199 GP_NUM : 10
7226 23:12:56.412884 SRAM_EN : 1
7227 23:12:56.412964 MD32_EN : 0
7228 23:12:56.416100 ===================================
7229 23:12:56.419864 [ANA_INIT] >>>>>>>>>>>>>>
7230 23:12:56.422303 <<<<<< [CONFIGURE PHASE]: ANA_TX
7231 23:12:56.426271 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7232 23:12:56.429354 ===================================
7233 23:12:56.432292 data_rate = 3200,PCW = 0X7600
7234 23:12:56.435902 ===================================
7235 23:12:56.438857 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7236 23:12:56.442256 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7237 23:12:56.449138 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7238 23:12:56.452573 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7239 23:12:56.455778 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7240 23:12:56.462513 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7241 23:12:56.462592 [ANA_INIT] flow start
7242 23:12:56.465922 [ANA_INIT] PLL >>>>>>>>
7243 23:12:56.469063 [ANA_INIT] PLL <<<<<<<<
7244 23:12:56.469144 [ANA_INIT] MIDPI >>>>>>>>
7245 23:12:56.472178 [ANA_INIT] MIDPI <<<<<<<<
7246 23:12:56.475067 [ANA_INIT] DLL >>>>>>>>
7247 23:12:56.475147 [ANA_INIT] DLL <<<<<<<<
7248 23:12:56.478626 [ANA_INIT] flow end
7249 23:12:56.482080 ============ LP4 DIFF to SE enter ============
7250 23:12:56.485044 ============ LP4 DIFF to SE exit ============
7251 23:12:56.488577 [ANA_INIT] <<<<<<<<<<<<<
7252 23:12:56.491504 [Flow] Enable top DCM control >>>>>
7253 23:12:56.495103 [Flow] Enable top DCM control <<<<<
7254 23:12:56.498999 Enable DLL master slave shuffle
7255 23:12:56.505106 ==============================================================
7256 23:12:56.505187 Gating Mode config
7257 23:12:56.511675 ==============================================================
7258 23:12:56.511755 Config description:
7259 23:12:56.522114 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7260 23:12:56.528716 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7261 23:12:56.534494 SELPH_MODE 0: By rank 1: By Phase
7262 23:12:56.537875 ==============================================================
7263 23:12:56.541791 GAT_TRACK_EN = 1
7264 23:12:56.544769 RX_GATING_MODE = 2
7265 23:12:56.547961 RX_GATING_TRACK_MODE = 2
7266 23:12:56.551444 SELPH_MODE = 1
7267 23:12:56.554352 PICG_EARLY_EN = 1
7268 23:12:56.558114 VALID_LAT_VALUE = 1
7269 23:12:56.564824 ==============================================================
7270 23:12:56.567827 Enter into Gating configuration >>>>
7271 23:12:56.571048 Exit from Gating configuration <<<<
7272 23:12:56.574751 Enter into DVFS_PRE_config >>>>>
7273 23:12:56.584460 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7274 23:12:56.587430 Exit from DVFS_PRE_config <<<<<
7275 23:12:56.591255 Enter into PICG configuration >>>>
7276 23:12:56.594427 Exit from PICG configuration <<<<
7277 23:12:56.597247 [RX_INPUT] configuration >>>>>
7278 23:12:56.601583 [RX_INPUT] configuration <<<<<
7279 23:12:56.603837 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7280 23:12:56.611164 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7281 23:12:56.617577 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7282 23:12:56.620961 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7283 23:12:56.627447 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7284 23:12:56.633472 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7285 23:12:56.637508 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7286 23:12:56.643530 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7287 23:12:56.647941 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7288 23:12:56.650037 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7289 23:12:56.653263 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7290 23:12:56.660027 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7291 23:12:56.663230 ===================================
7292 23:12:56.666800 LPDDR4 DRAM CONFIGURATION
7293 23:12:56.666881 ===================================
7294 23:12:56.670499 EX_ROW_EN[0] = 0x0
7295 23:12:56.673178 EX_ROW_EN[1] = 0x0
7296 23:12:56.673258 LP4Y_EN = 0x0
7297 23:12:56.676928 WORK_FSP = 0x1
7298 23:12:56.677008 WL = 0x5
7299 23:12:56.679845 RL = 0x5
7300 23:12:56.679924 BL = 0x2
7301 23:12:56.683284 RPST = 0x0
7302 23:12:56.683364 RD_PRE = 0x0
7303 23:12:56.686948 WR_PRE = 0x1
7304 23:12:56.687029 WR_PST = 0x1
7305 23:12:56.690048 DBI_WR = 0x0
7306 23:12:56.690127 DBI_RD = 0x0
7307 23:12:56.692976 OTF = 0x1
7308 23:12:56.696874 ===================================
7309 23:12:56.699540 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7310 23:12:56.703550 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7311 23:12:56.709876 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7312 23:12:56.713285 ===================================
7313 23:12:56.713366 LPDDR4 DRAM CONFIGURATION
7314 23:12:56.716377 ===================================
7315 23:12:56.719723 EX_ROW_EN[0] = 0x10
7316 23:12:56.723098 EX_ROW_EN[1] = 0x0
7317 23:12:56.723177 LP4Y_EN = 0x0
7318 23:12:56.726227 WORK_FSP = 0x1
7319 23:12:56.726307 WL = 0x5
7320 23:12:56.729318 RL = 0x5
7321 23:12:56.729397 BL = 0x2
7322 23:12:56.733301 RPST = 0x0
7323 23:12:56.733381 RD_PRE = 0x0
7324 23:12:56.736380 WR_PRE = 0x1
7325 23:12:56.736460 WR_PST = 0x1
7326 23:12:56.739930 DBI_WR = 0x0
7327 23:12:56.740010 DBI_RD = 0x0
7328 23:12:56.742712 OTF = 0x1
7329 23:12:56.745998 ===================================
7330 23:12:56.752443 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7331 23:12:56.752524 ==
7332 23:12:56.756161 Dram Type= 6, Freq= 0, CH_0, rank 0
7333 23:12:56.759244 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7334 23:12:56.759325 ==
7335 23:12:56.762481 [Duty_Offset_Calibration]
7336 23:12:56.762560 B0:1 B1:-1 CA:0
7337 23:12:56.762624
7338 23:12:56.767539 [DutyScan_Calibration_Flow] k_type=0
7339 23:12:56.777284
7340 23:12:56.777364 ==CLK 0==
7341 23:12:56.780116 Final CLK duty delay cell = 0
7342 23:12:56.783666 [0] MAX Duty = 5125%(X100), DQS PI = 20
7343 23:12:56.786966 [0] MIN Duty = 4907%(X100), DQS PI = 6
7344 23:12:56.789962 [0] AVG Duty = 5016%(X100)
7345 23:12:56.790042
7346 23:12:56.793182 CH0 CLK Duty spec in!! Max-Min= 218%
7347 23:12:56.796522 [DutyScan_Calibration_Flow] ====Done====
7348 23:12:56.796602
7349 23:12:56.799456 [DutyScan_Calibration_Flow] k_type=1
7350 23:12:56.815812
7351 23:12:56.815892 ==DQS 0 ==
7352 23:12:56.819641 Final DQS duty delay cell = -4
7353 23:12:56.823238 [-4] MAX Duty = 5000%(X100), DQS PI = 18
7354 23:12:56.826009 [-4] MIN Duty = 4844%(X100), DQS PI = 58
7355 23:12:56.829640 [-4] AVG Duty = 4922%(X100)
7356 23:12:56.829720
7357 23:12:56.829784 ==DQS 1 ==
7358 23:12:56.832924 Final DQS duty delay cell = 0
7359 23:12:56.835549 [0] MAX Duty = 5187%(X100), DQS PI = 4
7360 23:12:56.839517 [0] MIN Duty = 5031%(X100), DQS PI = 18
7361 23:12:56.842784 [0] AVG Duty = 5109%(X100)
7362 23:12:56.842864
7363 23:12:56.846207 CH0 DQS 0 Duty spec in!! Max-Min= 156%
7364 23:12:56.846286
7365 23:12:56.849005 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7366 23:12:56.852062 [DutyScan_Calibration_Flow] ====Done====
7367 23:12:56.852142
7368 23:12:56.855504 [DutyScan_Calibration_Flow] k_type=3
7369 23:12:56.873618
7370 23:12:56.873701 ==DQM 0 ==
7371 23:12:56.876935 Final DQM duty delay cell = 0
7372 23:12:56.880902 [0] MAX Duty = 5093%(X100), DQS PI = 20
7373 23:12:56.883297 [0] MIN Duty = 4907%(X100), DQS PI = 10
7374 23:12:56.887094 [0] AVG Duty = 5000%(X100)
7375 23:12:56.887212
7376 23:12:56.887276 ==DQM 1 ==
7377 23:12:56.889806 Final DQM duty delay cell = 0
7378 23:12:56.893046 [0] MAX Duty = 5031%(X100), DQS PI = 6
7379 23:12:56.896341 [0] MIN Duty = 4813%(X100), DQS PI = 20
7380 23:12:56.899887 [0] AVG Duty = 4922%(X100)
7381 23:12:56.899979
7382 23:12:56.903668 CH0 DQM 0 Duty spec in!! Max-Min= 186%
7383 23:12:56.903789
7384 23:12:56.906549 CH0 DQM 1 Duty spec in!! Max-Min= 218%
7385 23:12:56.910152 [DutyScan_Calibration_Flow] ====Done====
7386 23:12:56.910232
7387 23:12:56.912925 [DutyScan_Calibration_Flow] k_type=2
7388 23:12:56.929862
7389 23:12:56.929959 ==DQ 0 ==
7390 23:12:56.933511 Final DQ duty delay cell = -4
7391 23:12:56.936439 [-4] MAX Duty = 5031%(X100), DQS PI = 24
7392 23:12:56.939902 [-4] MIN Duty = 4876%(X100), DQS PI = 54
7393 23:12:56.942940 [-4] AVG Duty = 4953%(X100)
7394 23:12:56.943019
7395 23:12:56.943081 ==DQ 1 ==
7396 23:12:56.946413 Final DQ duty delay cell = 0
7397 23:12:56.949779 [0] MAX Duty = 5125%(X100), DQS PI = 46
7398 23:12:56.953151 [0] MIN Duty = 5000%(X100), DQS PI = 36
7399 23:12:56.956074 [0] AVG Duty = 5062%(X100)
7400 23:12:56.956154
7401 23:12:56.959314 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7402 23:12:56.959395
7403 23:12:56.962777 CH0 DQ 1 Duty spec in!! Max-Min= 125%
7404 23:12:56.966652 [DutyScan_Calibration_Flow] ====Done====
7405 23:12:56.966731 ==
7406 23:12:56.969528 Dram Type= 6, Freq= 0, CH_1, rank 0
7407 23:12:56.973581 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7408 23:12:56.973663 ==
7409 23:12:56.976450 [Duty_Offset_Calibration]
7410 23:12:56.976530 B0:-1 B1:1 CA:2
7411 23:12:56.976592
7412 23:12:56.979325 [DutyScan_Calibration_Flow] k_type=0
7413 23:12:56.990949
7414 23:12:56.991043 ==CLK 0==
7415 23:12:56.993747 Final CLK duty delay cell = 0
7416 23:12:56.996810 [0] MAX Duty = 5187%(X100), DQS PI = 22
7417 23:12:57.000778 [0] MIN Duty = 4969%(X100), DQS PI = 0
7418 23:12:57.004086 [0] AVG Duty = 5078%(X100)
7419 23:12:57.004174
7420 23:12:57.006799 CH1 CLK Duty spec in!! Max-Min= 218%
7421 23:12:57.010501 [DutyScan_Calibration_Flow] ====Done====
7422 23:12:57.010583
7423 23:12:57.013681 [DutyScan_Calibration_Flow] k_type=1
7424 23:12:57.030698
7425 23:12:57.030813 ==DQS 0 ==
7426 23:12:57.033197 Final DQS duty delay cell = 0
7427 23:12:57.036618 [0] MAX Duty = 5124%(X100), DQS PI = 18
7428 23:12:57.040491 [0] MIN Duty = 4938%(X100), DQS PI = 8
7429 23:12:57.043097 [0] AVG Duty = 5031%(X100)
7430 23:12:57.043179
7431 23:12:57.043243 ==DQS 1 ==
7432 23:12:57.046497 Final DQS duty delay cell = 0
7433 23:12:57.050334 [0] MAX Duty = 5093%(X100), DQS PI = 24
7434 23:12:57.053106 [0] MIN Duty = 4969%(X100), DQS PI = 56
7435 23:12:57.056350 [0] AVG Duty = 5031%(X100)
7436 23:12:57.056433
7437 23:12:57.059661 CH1 DQS 0 Duty spec in!! Max-Min= 186%
7438 23:12:57.059781
7439 23:12:57.062867 CH1 DQS 1 Duty spec in!! Max-Min= 124%
7440 23:12:57.066666 [DutyScan_Calibration_Flow] ====Done====
7441 23:12:57.066749
7442 23:12:57.069982 [DutyScan_Calibration_Flow] k_type=3
7443 23:12:57.086929
7444 23:12:57.087052 ==DQM 0 ==
7445 23:12:57.090352 Final DQM duty delay cell = 0
7446 23:12:57.093795 [0] MAX Duty = 5218%(X100), DQS PI = 18
7447 23:12:57.097654 [0] MIN Duty = 5031%(X100), DQS PI = 8
7448 23:12:57.100179 [0] AVG Duty = 5124%(X100)
7449 23:12:57.100262
7450 23:12:57.100326 ==DQM 1 ==
7451 23:12:57.103216 Final DQM duty delay cell = 0
7452 23:12:57.107075 [0] MAX Duty = 5156%(X100), DQS PI = 2
7453 23:12:57.109916 [0] MIN Duty = 4969%(X100), DQS PI = 28
7454 23:12:57.113583 [0] AVG Duty = 5062%(X100)
7455 23:12:57.113669
7456 23:12:57.116826 CH1 DQM 0 Duty spec in!! Max-Min= 187%
7457 23:12:57.116908
7458 23:12:57.120920 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7459 23:12:57.123315 [DutyScan_Calibration_Flow] ====Done====
7460 23:12:57.123397
7461 23:12:57.126327 [DutyScan_Calibration_Flow] k_type=2
7462 23:12:57.143984
7463 23:12:57.144112 ==DQ 0 ==
7464 23:12:57.147651 Final DQ duty delay cell = 0
7465 23:12:57.150956 [0] MAX Duty = 5156%(X100), DQS PI = 28
7466 23:12:57.153700 [0] MIN Duty = 4906%(X100), DQS PI = 8
7467 23:12:57.153784 [0] AVG Duty = 5031%(X100)
7468 23:12:57.156816
7469 23:12:57.156898 ==DQ 1 ==
7470 23:12:57.160494 Final DQ duty delay cell = 0
7471 23:12:57.163537 [0] MAX Duty = 5156%(X100), DQS PI = 8
7472 23:12:57.166710 [0] MIN Duty = 4969%(X100), DQS PI = 56
7473 23:12:57.166794 [0] AVG Duty = 5062%(X100)
7474 23:12:57.170279
7475 23:12:57.173547 CH1 DQ 0 Duty spec in!! Max-Min= 250%
7476 23:12:57.173632
7477 23:12:57.177724 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7478 23:12:57.180351 [DutyScan_Calibration_Flow] ====Done====
7479 23:12:57.184283 nWR fixed to 30
7480 23:12:57.184369 [ModeRegInit_LP4] CH0 RK0
7481 23:12:57.187319 [ModeRegInit_LP4] CH0 RK1
7482 23:12:57.190194 [ModeRegInit_LP4] CH1 RK0
7483 23:12:57.193532 [ModeRegInit_LP4] CH1 RK1
7484 23:12:57.193614 match AC timing 5
7485 23:12:57.200025 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7486 23:12:57.203419 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7487 23:12:57.206283 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7488 23:12:57.213157 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7489 23:12:57.216121 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7490 23:12:57.216208 [MiockJmeterHQA]
7491 23:12:57.216271
7492 23:12:57.219650 [DramcMiockJmeter] u1RxGatingPI = 0
7493 23:12:57.223086 0 : 4254, 4027
7494 23:12:57.223170 4 : 4363, 4137
7495 23:12:57.225856 8 : 4253, 4026
7496 23:12:57.225939 12 : 4363, 4137
7497 23:12:57.229933 16 : 4252, 4027
7498 23:12:57.230016 20 : 4253, 4027
7499 23:12:57.230081 24 : 4252, 4027
7500 23:12:57.232928 28 : 4255, 4029
7501 23:12:57.233010 32 : 4363, 4137
7502 23:12:57.236527 36 : 4252, 4027
7503 23:12:57.236610 40 : 4252, 4027
7504 23:12:57.239295 44 : 4252, 4027
7505 23:12:57.239377 48 : 4255, 4029
7506 23:12:57.242424 52 : 4250, 4027
7507 23:12:57.242508 56 : 4360, 4138
7508 23:12:57.242573 60 : 4360, 4138
7509 23:12:57.245700 64 : 4250, 4027
7510 23:12:57.245783 68 : 4249, 4027
7511 23:12:57.249218 72 : 4250, 4027
7512 23:12:57.249302 76 : 4250, 4027
7513 23:12:57.252269 80 : 4252, 4029
7514 23:12:57.252352 84 : 4361, 4137
7515 23:12:57.256043 88 : 4250, 4027
7516 23:12:57.256126 92 : 4250, 554
7517 23:12:57.256191 96 : 4360, 0
7518 23:12:57.259369 100 : 4250, 0
7519 23:12:57.259451 104 : 4250, 0
7520 23:12:57.262423 108 : 4250, 0
7521 23:12:57.262507 112 : 4249, 0
7522 23:12:57.262572 116 : 4250, 0
7523 23:12:57.265689 120 : 4253, 0
7524 23:12:57.265772 124 : 4249, 0
7525 23:12:57.265836 128 : 4250, 0
7526 23:12:57.269046 132 : 4363, 0
7527 23:12:57.269130 136 : 4249, 0
7528 23:12:57.272214 140 : 4250, 0
7529 23:12:57.272299 144 : 4363, 0
7530 23:12:57.272365 148 : 4250, 0
7531 23:12:57.275534 152 : 4250, 0
7532 23:12:57.275617 156 : 4250, 0
7533 23:12:57.278731 160 : 4250, 0
7534 23:12:57.278814 164 : 4249, 0
7535 23:12:57.278878 168 : 4250, 0
7536 23:12:57.282035 172 : 4252, 0
7537 23:12:57.282118 176 : 4361, 0
7538 23:12:57.285690 180 : 4361, 0
7539 23:12:57.285774 184 : 4250, 0
7540 23:12:57.285839 188 : 4249, 0
7541 23:12:57.288374 192 : 4250, 0
7542 23:12:57.288457 196 : 4250, 0
7543 23:12:57.292273 200 : 4250, 0
7544 23:12:57.292357 204 : 4252, 0
7545 23:12:57.292422 208 : 4250, 0
7546 23:12:57.294852 212 : 4252, 0
7547 23:12:57.294934 216 : 4250, 0
7548 23:12:57.298678 220 : 4250, 0
7549 23:12:57.298761 224 : 4252, 128
7550 23:12:57.298827 228 : 4361, 3470
7551 23:12:57.301528 232 : 4250, 4027
7552 23:12:57.301611 236 : 4249, 4027
7553 23:12:57.304791 240 : 4363, 4140
7554 23:12:57.304873 244 : 4250, 4027
7555 23:12:57.308296 248 : 4250, 4027
7556 23:12:57.308379 252 : 4249, 4027
7557 23:12:57.311254 256 : 4252, 4029
7558 23:12:57.311337 260 : 4250, 4027
7559 23:12:57.314509 264 : 4252, 4027
7560 23:12:57.314592 268 : 4361, 4138
7561 23:12:57.318017 272 : 4250, 4027
7562 23:12:57.318100 276 : 4250, 4027
7563 23:12:57.321743 280 : 4361, 4137
7564 23:12:57.321826 284 : 4250, 4027
7565 23:12:57.324812 288 : 4250, 4027
7566 23:12:57.324895 292 : 4363, 4140
7567 23:12:57.328083 296 : 4250, 4027
7568 23:12:57.328167 300 : 4250, 4027
7569 23:12:57.328232 304 : 4249, 4027
7570 23:12:57.331457 308 : 4252, 4029
7571 23:12:57.331540 312 : 4250, 4027
7572 23:12:57.334643 316 : 4250, 4027
7573 23:12:57.334730 320 : 4360, 4138
7574 23:12:57.338095 324 : 4250, 4027
7575 23:12:57.338179 328 : 4250, 4026
7576 23:12:57.341165 332 : 4361, 4137
7577 23:12:57.341249 336 : 4253, 3673
7578 23:12:57.344632 340 : 4250, 1971
7579 23:12:57.344716
7580 23:12:57.344780 MIOCK jitter meter ch=0
7581 23:12:57.344839
7582 23:12:57.347932 1T = (340-92) = 248 dly cells
7583 23:12:57.354979 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 262/100 ps
7584 23:12:57.355070 ==
7585 23:12:57.357536 Dram Type= 6, Freq= 0, CH_0, rank 0
7586 23:12:57.360605 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7587 23:12:57.360689 ==
7588 23:12:57.367021 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7589 23:12:57.370511 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7590 23:12:57.377171 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7591 23:12:57.380341 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7592 23:12:57.391642 [CA 0] Center 43 (12~74) winsize 63
7593 23:12:57.394533 [CA 1] Center 42 (12~73) winsize 62
7594 23:12:57.397590 [CA 2] Center 38 (9~68) winsize 60
7595 23:12:57.400975 [CA 3] Center 38 (8~68) winsize 61
7596 23:12:57.403965 [CA 4] Center 36 (7~66) winsize 60
7597 23:12:57.407618 [CA 5] Center 35 (6~65) winsize 60
7598 23:12:57.407742
7599 23:12:57.410561 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7600 23:12:57.410645
7601 23:12:57.416846 [CATrainingPosCal] consider 1 rank data
7602 23:12:57.416939 u2DelayCellTimex100 = 262/100 ps
7603 23:12:57.423458 CA0 delay=43 (12~74),Diff = 8 PI (29 cell)
7604 23:12:57.427266 CA1 delay=42 (12~73),Diff = 7 PI (26 cell)
7605 23:12:57.430626 CA2 delay=38 (9~68),Diff = 3 PI (11 cell)
7606 23:12:57.433722 CA3 delay=38 (8~68),Diff = 3 PI (11 cell)
7607 23:12:57.436860 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7608 23:12:57.440323 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7609 23:12:57.440407
7610 23:12:57.445181 CA PerBit enable=1, Macro0, CA PI delay=35
7611 23:12:57.445265
7612 23:12:57.446820 [CBTSetCACLKResult] CA Dly = 35
7613 23:12:57.450057 CS Dly: 12 (0~43)
7614 23:12:57.454058 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7615 23:12:57.457143 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7616 23:12:57.457244 ==
7617 23:12:57.459994 Dram Type= 6, Freq= 0, CH_0, rank 1
7618 23:12:57.466670 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7619 23:12:57.466767 ==
7620 23:12:57.469825 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7621 23:12:57.476296 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7622 23:12:57.479945 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7623 23:12:57.486609 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7624 23:12:57.494417 [CA 0] Center 42 (12~73) winsize 62
7625 23:12:57.497762 [CA 1] Center 43 (13~73) winsize 61
7626 23:12:57.500768 [CA 2] Center 37 (8~67) winsize 60
7627 23:12:57.504187 [CA 3] Center 37 (7~67) winsize 61
7628 23:12:57.507577 [CA 4] Center 35 (6~65) winsize 60
7629 23:12:57.510717 [CA 5] Center 35 (5~65) winsize 61
7630 23:12:57.510829
7631 23:12:57.515088 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7632 23:12:57.515194
7633 23:12:57.517327 [CATrainingPosCal] consider 2 rank data
7634 23:12:57.521262 u2DelayCellTimex100 = 262/100 ps
7635 23:12:57.527287 CA0 delay=42 (12~73),Diff = 7 PI (26 cell)
7636 23:12:57.531087 CA1 delay=43 (13~73),Diff = 8 PI (29 cell)
7637 23:12:57.533925 CA2 delay=38 (9~67),Diff = 3 PI (11 cell)
7638 23:12:57.537675 CA3 delay=37 (8~67),Diff = 2 PI (7 cell)
7639 23:12:57.540340 CA4 delay=36 (7~65),Diff = 1 PI (3 cell)
7640 23:12:57.543720 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7641 23:12:57.543813
7642 23:12:57.547621 CA PerBit enable=1, Macro0, CA PI delay=35
7643 23:12:57.547714
7644 23:12:57.551116 [CBTSetCACLKResult] CA Dly = 35
7645 23:12:57.554124 CS Dly: 12 (0~44)
7646 23:12:57.557026 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7647 23:12:57.560246 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7648 23:12:57.560331
7649 23:12:57.563461 ----->DramcWriteLeveling(PI) begin...
7650 23:12:57.563547 ==
7651 23:12:57.566854 Dram Type= 6, Freq= 0, CH_0, rank 0
7652 23:12:57.573389 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7653 23:12:57.573503 ==
7654 23:12:57.577381 Write leveling (Byte 0): 34 => 34
7655 23:12:57.580413 Write leveling (Byte 1): 27 => 27
7656 23:12:57.580498 DramcWriteLeveling(PI) end<-----
7657 23:12:57.584383
7658 23:12:57.584468 ==
7659 23:12:57.586826 Dram Type= 6, Freq= 0, CH_0, rank 0
7660 23:12:57.590408 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7661 23:12:57.590494 ==
7662 23:12:57.593179 [Gating] SW mode calibration
7663 23:12:57.600267 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7664 23:12:57.603388 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7665 23:12:57.609974 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7666 23:12:57.613399 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7667 23:12:57.616295 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7668 23:12:57.623209 1 4 12 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
7669 23:12:57.626367 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7670 23:12:57.629575 1 4 20 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7671 23:12:57.636958 1 4 24 | B1->B0 | 2d2d 3434 | 0 1 | (1 1) (1 1)
7672 23:12:57.639804 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7673 23:12:57.642967 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7674 23:12:57.649767 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7675 23:12:57.652974 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7676 23:12:57.656931 1 5 12 | B1->B0 | 3434 2e2e | 1 0 | (1 1) (0 1)
7677 23:12:57.662531 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7678 23:12:57.665765 1 5 20 | B1->B0 | 3333 2323 | 0 0 | (0 1) (0 0)
7679 23:12:57.669643 1 5 24 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
7680 23:12:57.675994 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7681 23:12:57.680003 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7682 23:12:57.681949 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7683 23:12:57.689474 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7684 23:12:57.692670 1 6 12 | B1->B0 | 2323 3535 | 0 1 | (0 0) (0 0)
7685 23:12:57.695847 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7686 23:12:57.702168 1 6 20 | B1->B0 | 2f2f 4646 | 0 0 | (0 0) (0 0)
7687 23:12:57.705516 1 6 24 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
7688 23:12:57.708671 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7689 23:12:57.715321 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7690 23:12:57.718825 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7691 23:12:57.722060 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7692 23:12:57.729149 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7693 23:12:57.732236 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7694 23:12:57.735017 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7695 23:12:57.741787 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7696 23:12:57.745309 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7697 23:12:57.748303 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7698 23:12:57.755159 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7699 23:12:57.758481 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7700 23:12:57.761653 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7701 23:12:57.768335 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7702 23:12:57.772222 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7703 23:12:57.775051 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7704 23:12:57.782073 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7705 23:12:57.784820 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7706 23:12:57.787847 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7707 23:12:57.795114 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7708 23:12:57.798135 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7709 23:12:57.801306 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7710 23:12:57.804707 Total UI for P1: 0, mck2ui 16
7711 23:12:57.808841 best dqsien dly found for B0: ( 1, 9, 12)
7712 23:12:57.815026 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7713 23:12:57.818014 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7714 23:12:57.821063 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7715 23:12:57.824221 Total UI for P1: 0, mck2ui 16
7716 23:12:57.827982 best dqsien dly found for B1: ( 1, 9, 22)
7717 23:12:57.830965 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
7718 23:12:57.834615 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7719 23:12:57.837331
7720 23:12:57.840991 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
7721 23:12:57.844170 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7722 23:12:57.847623 [Gating] SW calibration Done
7723 23:12:57.847730 ==
7724 23:12:57.850830 Dram Type= 6, Freq= 0, CH_0, rank 0
7725 23:12:57.854254 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7726 23:12:57.854341 ==
7727 23:12:57.857320 RX Vref Scan: 0
7728 23:12:57.857404
7729 23:12:57.857469 RX Vref 0 -> 0, step: 1
7730 23:12:57.857530
7731 23:12:57.860874 RX Delay 0 -> 252, step: 8
7732 23:12:57.864087 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
7733 23:12:57.867195 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7734 23:12:57.874414 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7735 23:12:57.877576 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7736 23:12:57.880895 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7737 23:12:57.883879 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7738 23:12:57.886801 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
7739 23:12:57.893296 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7740 23:12:57.896979 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
7741 23:12:57.900172 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7742 23:12:57.903508 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
7743 23:12:57.909971 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7744 23:12:57.913252 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7745 23:12:57.916746 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7746 23:12:57.919735 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7747 23:12:57.923443 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7748 23:12:57.926956 ==
7749 23:12:57.927045 Dram Type= 6, Freq= 0, CH_0, rank 0
7750 23:12:57.933310 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7751 23:12:57.933405 ==
7752 23:12:57.933472 DQS Delay:
7753 23:12:57.936298 DQS0 = 0, DQS1 = 0
7754 23:12:57.936382 DQM Delay:
7755 23:12:57.939490 DQM0 = 134, DQM1 = 126
7756 23:12:57.939574 DQ Delay:
7757 23:12:57.943462 DQ0 =131, DQ1 =139, DQ2 =131, DQ3 =131
7758 23:12:57.946982 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =147
7759 23:12:57.949852 DQ8 =115, DQ9 =115, DQ10 =127, DQ11 =119
7760 23:12:57.952832 DQ12 =131, DQ13 =135, DQ14 =139, DQ15 =131
7761 23:12:57.952916
7762 23:12:57.952981
7763 23:12:57.953041 ==
7764 23:12:57.956538 Dram Type= 6, Freq= 0, CH_0, rank 0
7765 23:12:57.962921 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7766 23:12:57.963017 ==
7767 23:12:57.963084
7768 23:12:57.963143
7769 23:12:57.965827 TX Vref Scan disable
7770 23:12:57.965910 == TX Byte 0 ==
7771 23:12:57.970243 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7772 23:12:57.975859 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
7773 23:12:57.975963 == TX Byte 1 ==
7774 23:12:57.979075 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7775 23:12:57.985956 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7776 23:12:57.986066 ==
7777 23:12:57.989403 Dram Type= 6, Freq= 0, CH_0, rank 0
7778 23:12:57.992184 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7779 23:12:57.992293 ==
7780 23:12:58.006233
7781 23:12:58.009353 TX Vref early break, caculate TX vref
7782 23:12:58.012909 TX Vref=16, minBit 1, minWin=22, winSum=367
7783 23:12:58.015681 TX Vref=18, minBit 1, minWin=23, winSum=380
7784 23:12:58.019621 TX Vref=20, minBit 3, minWin=24, winSum=392
7785 23:12:58.022721 TX Vref=22, minBit 4, minWin=24, winSum=400
7786 23:12:58.025878 TX Vref=24, minBit 6, minWin=24, winSum=409
7787 23:12:58.032799 TX Vref=26, minBit 5, minWin=24, winSum=414
7788 23:12:58.035981 TX Vref=28, minBit 4, minWin=25, winSum=419
7789 23:12:58.039604 TX Vref=30, minBit 4, minWin=24, winSum=411
7790 23:12:58.042636 TX Vref=32, minBit 4, minWin=24, winSum=398
7791 23:12:58.046379 TX Vref=34, minBit 4, minWin=23, winSum=393
7792 23:12:58.052428 [TxChooseVref] Worse bit 4, Min win 25, Win sum 419, Final Vref 28
7793 23:12:58.052528
7794 23:12:58.055809 Final TX Range 0 Vref 28
7795 23:12:58.055897
7796 23:12:58.055962 ==
7797 23:12:58.059321 Dram Type= 6, Freq= 0, CH_0, rank 0
7798 23:12:58.062530 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7799 23:12:58.062615 ==
7800 23:12:58.062680
7801 23:12:58.062740
7802 23:12:58.066612 TX Vref Scan disable
7803 23:12:58.072445 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
7804 23:12:58.072547 == TX Byte 0 ==
7805 23:12:58.075791 u2DelayCellOfst[0]=18 cells (5 PI)
7806 23:12:58.078902 u2DelayCellOfst[1]=18 cells (5 PI)
7807 23:12:58.081858 u2DelayCellOfst[2]=14 cells (4 PI)
7808 23:12:58.085670 u2DelayCellOfst[3]=14 cells (4 PI)
7809 23:12:58.088446 u2DelayCellOfst[4]=11 cells (3 PI)
7810 23:12:58.091947 u2DelayCellOfst[5]=0 cells (0 PI)
7811 23:12:58.095525 u2DelayCellOfst[6]=18 cells (5 PI)
7812 23:12:58.099160 u2DelayCellOfst[7]=22 cells (6 PI)
7813 23:12:58.102057 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7814 23:12:58.104912 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
7815 23:12:58.108333 == TX Byte 1 ==
7816 23:12:58.111469 u2DelayCellOfst[8]=0 cells (0 PI)
7817 23:12:58.115454 u2DelayCellOfst[9]=0 cells (0 PI)
7818 23:12:58.115546 u2DelayCellOfst[10]=3 cells (1 PI)
7819 23:12:58.118485 u2DelayCellOfst[11]=0 cells (0 PI)
7820 23:12:58.121730 u2DelayCellOfst[12]=11 cells (3 PI)
7821 23:12:58.125014 u2DelayCellOfst[13]=11 cells (3 PI)
7822 23:12:58.127884 u2DelayCellOfst[14]=14 cells (4 PI)
7823 23:12:58.131639 u2DelayCellOfst[15]=11 cells (3 PI)
7824 23:12:58.137853 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7825 23:12:58.141527 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7826 23:12:58.141621 DramC Write-DBI on
7827 23:12:58.141686 ==
7828 23:12:58.144810 Dram Type= 6, Freq= 0, CH_0, rank 0
7829 23:12:58.150874 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7830 23:12:58.150970 ==
7831 23:12:58.151037
7832 23:12:58.151097
7833 23:12:58.155010 TX Vref Scan disable
7834 23:12:58.155095 == TX Byte 0 ==
7835 23:12:58.160976 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
7836 23:12:58.161067 == TX Byte 1 ==
7837 23:12:58.164352 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
7838 23:12:58.168541 DramC Write-DBI off
7839 23:12:58.168630
7840 23:12:58.168695 [DATLAT]
7841 23:12:58.170815 Freq=1600, CH0 RK0
7842 23:12:58.170899
7843 23:12:58.170964 DATLAT Default: 0xf
7844 23:12:58.174465 0, 0xFFFF, sum = 0
7845 23:12:58.174553 1, 0xFFFF, sum = 0
7846 23:12:58.177644 2, 0xFFFF, sum = 0
7847 23:12:58.177737 3, 0xFFFF, sum = 0
7848 23:12:58.180526 4, 0xFFFF, sum = 0
7849 23:12:58.180613 5, 0xFFFF, sum = 0
7850 23:12:58.184320 6, 0xFFFF, sum = 0
7851 23:12:58.187384 7, 0xFFFF, sum = 0
7852 23:12:58.187475 8, 0xFFFF, sum = 0
7853 23:12:58.191048 9, 0xFFFF, sum = 0
7854 23:12:58.191137 10, 0xFFFF, sum = 0
7855 23:12:58.193743 11, 0xFFFF, sum = 0
7856 23:12:58.193830 12, 0xFFFF, sum = 0
7857 23:12:58.196844 13, 0xFFFF, sum = 0
7858 23:12:58.196929 14, 0x0, sum = 1
7859 23:12:58.200329 15, 0x0, sum = 2
7860 23:12:58.200416 16, 0x0, sum = 3
7861 23:12:58.203509 17, 0x0, sum = 4
7862 23:12:58.203597 best_step = 15
7863 23:12:58.203741
7864 23:12:58.203822 ==
7865 23:12:58.206648 Dram Type= 6, Freq= 0, CH_0, rank 0
7866 23:12:58.210255 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7867 23:12:58.214381 ==
7868 23:12:58.214473 RX Vref Scan: 1
7869 23:12:58.214558
7870 23:12:58.216680 Set Vref Range= 24 -> 127
7871 23:12:58.216764
7872 23:12:58.220044 RX Vref 24 -> 127, step: 1
7873 23:12:58.220129
7874 23:12:58.220213 RX Delay 11 -> 252, step: 4
7875 23:12:58.220293
7876 23:12:58.223511 Set Vref, RX VrefLevel [Byte0]: 24
7877 23:12:58.226555 [Byte1]: 24
7878 23:12:58.230710
7879 23:12:58.230799 Set Vref, RX VrefLevel [Byte0]: 25
7880 23:12:58.234206 [Byte1]: 25
7881 23:12:58.238463
7882 23:12:58.238555 Set Vref, RX VrefLevel [Byte0]: 26
7883 23:12:58.242282 [Byte1]: 26
7884 23:12:58.246727
7885 23:12:58.246832 Set Vref, RX VrefLevel [Byte0]: 27
7886 23:12:58.249294 [Byte1]: 27
7887 23:12:58.253547
7888 23:12:58.253638 Set Vref, RX VrefLevel [Byte0]: 28
7889 23:12:58.257447 [Byte1]: 28
7890 23:12:58.260971
7891 23:12:58.261057 Set Vref, RX VrefLevel [Byte0]: 29
7892 23:12:58.264259 [Byte1]: 29
7893 23:12:58.268443
7894 23:12:58.268531 Set Vref, RX VrefLevel [Byte0]: 30
7895 23:12:58.272293 [Byte1]: 30
7896 23:12:58.276225
7897 23:12:58.276326 Set Vref, RX VrefLevel [Byte0]: 31
7898 23:12:58.279845 [Byte1]: 31
7899 23:12:58.283866
7900 23:12:58.283955 Set Vref, RX VrefLevel [Byte0]: 32
7901 23:12:58.287138 [Byte1]: 32
7902 23:12:58.292434
7903 23:12:58.292532 Set Vref, RX VrefLevel [Byte0]: 33
7904 23:12:58.294857 [Byte1]: 33
7905 23:12:58.299150
7906 23:12:58.299239 Set Vref, RX VrefLevel [Byte0]: 34
7907 23:12:58.302515 [Byte1]: 34
7908 23:12:58.307004
7909 23:12:58.307095 Set Vref, RX VrefLevel [Byte0]: 35
7910 23:12:58.310320 [Byte1]: 35
7911 23:12:58.314611
7912 23:12:58.317503 Set Vref, RX VrefLevel [Byte0]: 36
7913 23:12:58.321061 [Byte1]: 36
7914 23:12:58.321153
7915 23:12:58.324546 Set Vref, RX VrefLevel [Byte0]: 37
7916 23:12:58.327458 [Byte1]: 37
7917 23:12:58.327544
7918 23:12:58.330611 Set Vref, RX VrefLevel [Byte0]: 38
7919 23:12:58.333856 [Byte1]: 38
7920 23:12:58.337335
7921 23:12:58.337425 Set Vref, RX VrefLevel [Byte0]: 39
7922 23:12:58.340626 [Byte1]: 39
7923 23:12:58.344588
7924 23:12:58.344679 Set Vref, RX VrefLevel [Byte0]: 40
7925 23:12:58.348697 [Byte1]: 40
7926 23:12:58.352835
7927 23:12:58.352926 Set Vref, RX VrefLevel [Byte0]: 41
7928 23:12:58.356317 [Byte1]: 41
7929 23:12:58.360924
7930 23:12:58.361014 Set Vref, RX VrefLevel [Byte0]: 42
7931 23:12:58.363178 [Byte1]: 42
7932 23:12:58.368399
7933 23:12:58.368487 Set Vref, RX VrefLevel [Byte0]: 43
7934 23:12:58.370924 [Byte1]: 43
7935 23:12:58.375242
7936 23:12:58.375342 Set Vref, RX VrefLevel [Byte0]: 44
7937 23:12:58.378561 [Byte1]: 44
7938 23:12:58.382759
7939 23:12:58.382850 Set Vref, RX VrefLevel [Byte0]: 45
7940 23:12:58.386371 [Byte1]: 45
7941 23:12:58.390376
7942 23:12:58.390468 Set Vref, RX VrefLevel [Byte0]: 46
7943 23:12:58.394293 [Byte1]: 46
7944 23:12:58.398644
7945 23:12:58.398737 Set Vref, RX VrefLevel [Byte0]: 47
7946 23:12:58.401712 [Byte1]: 47
7947 23:12:58.405454
7948 23:12:58.405544 Set Vref, RX VrefLevel [Byte0]: 48
7949 23:12:58.409194 [Byte1]: 48
7950 23:12:58.413348
7951 23:12:58.413439 Set Vref, RX VrefLevel [Byte0]: 49
7952 23:12:58.416603 [Byte1]: 49
7953 23:12:58.421199
7954 23:12:58.421294 Set Vref, RX VrefLevel [Byte0]: 50
7955 23:12:58.424168 [Byte1]: 50
7956 23:12:58.428511
7957 23:12:58.428603 Set Vref, RX VrefLevel [Byte0]: 51
7958 23:12:58.432800 [Byte1]: 51
7959 23:12:58.436281
7960 23:12:58.436388 Set Vref, RX VrefLevel [Byte0]: 52
7961 23:12:58.439701 [Byte1]: 52
7962 23:12:58.443920
7963 23:12:58.444008 Set Vref, RX VrefLevel [Byte0]: 53
7964 23:12:58.447237 [Byte1]: 53
7965 23:12:58.451488
7966 23:12:58.451577 Set Vref, RX VrefLevel [Byte0]: 54
7967 23:12:58.455034 [Byte1]: 54
7968 23:12:58.459155
7969 23:12:58.459245 Set Vref, RX VrefLevel [Byte0]: 55
7970 23:12:58.462634 [Byte1]: 55
7971 23:12:58.466850
7972 23:12:58.466943 Set Vref, RX VrefLevel [Byte0]: 56
7973 23:12:58.469741 [Byte1]: 56
7974 23:12:58.474398
7975 23:12:58.474495 Set Vref, RX VrefLevel [Byte0]: 57
7976 23:12:58.477702 [Byte1]: 57
7977 23:12:58.481922
7978 23:12:58.482014 Set Vref, RX VrefLevel [Byte0]: 58
7979 23:12:58.485495 [Byte1]: 58
7980 23:12:58.489334
7981 23:12:58.489424 Set Vref, RX VrefLevel [Byte0]: 59
7982 23:12:58.493007 [Byte1]: 59
7983 23:12:58.497496
7984 23:12:58.497587 Set Vref, RX VrefLevel [Byte0]: 60
7985 23:12:58.500569 [Byte1]: 60
7986 23:12:58.504638
7987 23:12:58.504733 Set Vref, RX VrefLevel [Byte0]: 61
7988 23:12:58.508435 [Byte1]: 61
7989 23:12:58.512273
7990 23:12:58.512361 Set Vref, RX VrefLevel [Byte0]: 62
7991 23:12:58.515395 [Byte1]: 62
7992 23:12:58.519699
7993 23:12:58.519803 Set Vref, RX VrefLevel [Byte0]: 63
7994 23:12:58.523000 [Byte1]: 63
7995 23:12:58.527613
7996 23:12:58.527762 Set Vref, RX VrefLevel [Byte0]: 64
7997 23:12:58.531858 [Byte1]: 64
7998 23:12:58.535544
7999 23:12:58.535634 Set Vref, RX VrefLevel [Byte0]: 65
8000 23:12:58.538729 [Byte1]: 65
8001 23:12:58.542840
8002 23:12:58.542933 Set Vref, RX VrefLevel [Byte0]: 66
8003 23:12:58.545988 [Byte1]: 66
8004 23:12:58.550743
8005 23:12:58.550835 Set Vref, RX VrefLevel [Byte0]: 67
8006 23:12:58.553373 [Byte1]: 67
8007 23:12:58.557858
8008 23:12:58.557966 Set Vref, RX VrefLevel [Byte0]: 68
8009 23:12:58.561113 [Byte1]: 68
8010 23:12:58.565755
8011 23:12:58.565847 Set Vref, RX VrefLevel [Byte0]: 69
8012 23:12:58.569114 [Byte1]: 69
8013 23:12:58.573478
8014 23:12:58.573574 Set Vref, RX VrefLevel [Byte0]: 70
8015 23:12:58.576557 [Byte1]: 70
8016 23:12:58.581112
8017 23:12:58.581205 Set Vref, RX VrefLevel [Byte0]: 71
8018 23:12:58.584108 [Byte1]: 71
8019 23:12:58.588415
8020 23:12:58.588507 Set Vref, RX VrefLevel [Byte0]: 72
8021 23:12:58.591694 [Byte1]: 72
8022 23:12:58.596252
8023 23:12:58.596383 Set Vref, RX VrefLevel [Byte0]: 73
8024 23:12:58.599587 [Byte1]: 73
8025 23:12:58.603887
8026 23:12:58.604005 Set Vref, RX VrefLevel [Byte0]: 74
8027 23:12:58.606772 [Byte1]: 74
8028 23:12:58.611217
8029 23:12:58.611309 Set Vref, RX VrefLevel [Byte0]: 75
8030 23:12:58.614569 [Byte1]: 75
8031 23:12:58.619230
8032 23:12:58.619410 Set Vref, RX VrefLevel [Byte0]: 76
8033 23:12:58.622671 [Byte1]: 76
8034 23:12:58.626792
8035 23:12:58.626880 Set Vref, RX VrefLevel [Byte0]: 77
8036 23:12:58.630043 [Byte1]: 77
8037 23:12:58.634715
8038 23:12:58.634812 Set Vref, RX VrefLevel [Byte0]: 78
8039 23:12:58.637622 [Byte1]: 78
8040 23:12:58.641984
8041 23:12:58.642104 Set Vref, RX VrefLevel [Byte0]: 79
8042 23:12:58.645733 [Byte1]: 79
8043 23:12:58.649668
8044 23:12:58.649764 Set Vref, RX VrefLevel [Byte0]: 80
8045 23:12:58.652724 [Byte1]: 80
8046 23:12:58.657594
8047 23:12:58.657692 Final RX Vref Byte 0 = 67 to rank0
8048 23:12:58.660553 Final RX Vref Byte 1 = 56 to rank0
8049 23:12:58.663791 Final RX Vref Byte 0 = 67 to rank1
8050 23:12:58.666744 Final RX Vref Byte 1 = 56 to rank1==
8051 23:12:58.669941 Dram Type= 6, Freq= 0, CH_0, rank 0
8052 23:12:58.676698 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8053 23:12:58.676808 ==
8054 23:12:58.676874 DQS Delay:
8055 23:12:58.676935 DQS0 = 0, DQS1 = 0
8056 23:12:58.680296 DQM Delay:
8057 23:12:58.680381 DQM0 = 133, DQM1 = 124
8058 23:12:58.683892 DQ Delay:
8059 23:12:58.687124 DQ0 =132, DQ1 =136, DQ2 =130, DQ3 =132
8060 23:12:58.690089 DQ4 =134, DQ5 =122, DQ6 =140, DQ7 =140
8061 23:12:58.693579 DQ8 =114, DQ9 =110, DQ10 =126, DQ11 =118
8062 23:12:58.696643 DQ12 =130, DQ13 =128, DQ14 =136, DQ15 =130
8063 23:12:58.696730
8064 23:12:58.696795
8065 23:12:58.696855
8066 23:12:58.700266 [DramC_TX_OE_Calibration] TA2
8067 23:12:58.703546 Original DQ_B0 (3 6) =30, OEN = 27
8068 23:12:58.706550 Original DQ_B1 (3 6) =30, OEN = 27
8069 23:12:58.710208 24, 0x0, End_B0=24 End_B1=24
8070 23:12:58.710296 25, 0x0, End_B0=25 End_B1=25
8071 23:12:58.713828 26, 0x0, End_B0=26 End_B1=26
8072 23:12:58.716566 27, 0x0, End_B0=27 End_B1=27
8073 23:12:58.720078 28, 0x0, End_B0=28 End_B1=28
8074 23:12:58.723118 29, 0x0, End_B0=29 End_B1=29
8075 23:12:58.723208 30, 0x0, End_B0=30 End_B1=30
8076 23:12:58.727004 31, 0x4141, End_B0=30 End_B1=30
8077 23:12:58.730520 Byte0 end_step=30 best_step=27
8078 23:12:58.733101 Byte1 end_step=30 best_step=27
8079 23:12:58.736480 Byte0 TX OE(2T, 0.5T) = (3, 3)
8080 23:12:58.739517 Byte1 TX OE(2T, 0.5T) = (3, 3)
8081 23:12:58.739604
8082 23:12:58.739677
8083 23:12:58.746227 [DQSOSCAuto] RK0, (LSB)MR18= 0x2112, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 393 ps
8084 23:12:58.749580 CH0 RK0: MR19=303, MR18=2112
8085 23:12:58.756297 CH0_RK0: MR19=0x303, MR18=0x2112, DQSOSC=393, MR23=63, INC=23, DEC=15
8086 23:12:58.756404
8087 23:12:58.759420 ----->DramcWriteLeveling(PI) begin...
8088 23:12:58.759506 ==
8089 23:12:58.763260 Dram Type= 6, Freq= 0, CH_0, rank 1
8090 23:12:58.765793 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8091 23:12:58.765879 ==
8092 23:12:58.769539 Write leveling (Byte 0): 34 => 34
8093 23:12:58.772938 Write leveling (Byte 1): 28 => 28
8094 23:12:58.776105 DramcWriteLeveling(PI) end<-----
8095 23:12:58.776194
8096 23:12:58.776259 ==
8097 23:12:58.779076 Dram Type= 6, Freq= 0, CH_0, rank 1
8098 23:12:58.782436 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8099 23:12:58.782524 ==
8100 23:12:58.785678 [Gating] SW mode calibration
8101 23:12:58.792385 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8102 23:12:58.799267 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8103 23:12:58.802393 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8104 23:12:58.809042 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8105 23:12:58.812490 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8106 23:12:58.815372 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8107 23:12:58.822417 1 4 16 | B1->B0 | 2323 3333 | 0 0 | (0 0) (1 1)
8108 23:12:58.825346 1 4 20 | B1->B0 | 2928 3434 | 1 1 | (0 0) (1 1)
8109 23:12:58.829080 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8110 23:12:58.836691 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8111 23:12:58.838831 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8112 23:12:58.842059 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8113 23:12:58.848512 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8114 23:12:58.852490 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8115 23:12:58.855077 1 5 16 | B1->B0 | 3434 2a2a | 1 0 | (1 0) (1 1)
8116 23:12:58.862374 1 5 20 | B1->B0 | 3030 2323 | 1 0 | (1 0) (0 0)
8117 23:12:58.864989 1 5 24 | B1->B0 | 2626 2323 | 0 0 | (0 1) (0 0)
8118 23:12:58.868491 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8119 23:12:58.874829 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8120 23:12:58.878082 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8121 23:12:58.881674 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8122 23:12:58.888008 1 6 12 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
8123 23:12:58.891496 1 6 16 | B1->B0 | 2424 4444 | 1 0 | (0 0) (0 0)
8124 23:12:58.894778 1 6 20 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
8125 23:12:58.902178 1 6 24 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8126 23:12:58.904638 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8127 23:12:58.907998 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8128 23:12:58.914421 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8129 23:12:58.917952 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8130 23:12:58.921094 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8131 23:12:58.927623 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8132 23:12:58.931427 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8133 23:12:58.934313 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8134 23:12:58.941035 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8135 23:12:58.944186 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8136 23:12:58.947514 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8137 23:12:58.954704 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8138 23:12:58.957641 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8139 23:12:58.961140 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8140 23:12:58.967402 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8141 23:12:58.970947 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8142 23:12:58.974042 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8143 23:12:58.980308 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8144 23:12:58.984052 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8145 23:12:58.987096 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8146 23:12:58.993823 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8147 23:12:58.993936 Total UI for P1: 0, mck2ui 16
8148 23:12:59.000373 best dqsien dly found for B0: ( 1, 9, 10)
8149 23:12:59.003351 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8150 23:12:59.007028 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8151 23:12:59.013324 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8152 23:12:59.013433 Total UI for P1: 0, mck2ui 16
8153 23:12:59.020110 best dqsien dly found for B1: ( 1, 9, 16)
8154 23:12:59.023386 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8155 23:12:59.027222 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8156 23:12:59.027314
8157 23:12:59.030106 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8158 23:12:59.034007 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8159 23:12:59.036831 [Gating] SW calibration Done
8160 23:12:59.036921 ==
8161 23:12:59.040754 Dram Type= 6, Freq= 0, CH_0, rank 1
8162 23:12:59.043109 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8163 23:12:59.043203 ==
8164 23:12:59.046601 RX Vref Scan: 0
8165 23:12:59.046687
8166 23:12:59.046752 RX Vref 0 -> 0, step: 1
8167 23:12:59.046830
8168 23:12:59.049787 RX Delay 0 -> 252, step: 8
8169 23:12:59.053242 iDelay=208, Bit 0, Center 135 (80 ~ 191) 112
8170 23:12:59.060035 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8171 23:12:59.063236 iDelay=208, Bit 2, Center 127 (72 ~ 183) 112
8172 23:12:59.066137 iDelay=208, Bit 3, Center 127 (72 ~ 183) 112
8173 23:12:59.069679 iDelay=208, Bit 4, Center 135 (80 ~ 191) 112
8174 23:12:59.073340 iDelay=208, Bit 5, Center 123 (64 ~ 183) 120
8175 23:12:59.079598 iDelay=208, Bit 6, Center 139 (80 ~ 199) 120
8176 23:12:59.082697 iDelay=208, Bit 7, Center 147 (88 ~ 207) 120
8177 23:12:59.086495 iDelay=208, Bit 8, Center 115 (56 ~ 175) 120
8178 23:12:59.089392 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8179 23:12:59.096000 iDelay=208, Bit 10, Center 131 (72 ~ 191) 120
8180 23:12:59.099827 iDelay=208, Bit 11, Center 123 (64 ~ 183) 120
8181 23:12:59.102669 iDelay=208, Bit 12, Center 131 (72 ~ 191) 120
8182 23:12:59.105768 iDelay=208, Bit 13, Center 135 (80 ~ 191) 112
8183 23:12:59.109354 iDelay=208, Bit 14, Center 139 (80 ~ 199) 120
8184 23:12:59.115432 iDelay=208, Bit 15, Center 135 (80 ~ 191) 112
8185 23:12:59.115539 ==
8186 23:12:59.118651 Dram Type= 6, Freq= 0, CH_0, rank 1
8187 23:12:59.122232 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8188 23:12:59.122322 ==
8189 23:12:59.122388 DQS Delay:
8190 23:12:59.125362 DQS0 = 0, DQS1 = 0
8191 23:12:59.125448 DQM Delay:
8192 23:12:59.128976 DQM0 = 133, DQM1 = 128
8193 23:12:59.129063 DQ Delay:
8194 23:12:59.132291 DQ0 =135, DQ1 =135, DQ2 =127, DQ3 =127
8195 23:12:59.135120 DQ4 =135, DQ5 =123, DQ6 =139, DQ7 =147
8196 23:12:59.138673 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =123
8197 23:12:59.144949 DQ12 =131, DQ13 =135, DQ14 =139, DQ15 =135
8198 23:12:59.145054
8199 23:12:59.145120
8200 23:12:59.145180 ==
8201 23:12:59.148288 Dram Type= 6, Freq= 0, CH_0, rank 1
8202 23:12:59.151854 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8203 23:12:59.151939 ==
8204 23:12:59.152006
8205 23:12:59.152067
8206 23:12:59.155332 TX Vref Scan disable
8207 23:12:59.155415 == TX Byte 0 ==
8208 23:12:59.161848 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8209 23:12:59.165452 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8210 23:12:59.165538 == TX Byte 1 ==
8211 23:12:59.171171 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8212 23:12:59.175295 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8213 23:12:59.175388 ==
8214 23:12:59.178242 Dram Type= 6, Freq= 0, CH_0, rank 1
8215 23:12:59.181128 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8216 23:12:59.181215 ==
8217 23:12:59.195882
8218 23:12:59.199235 TX Vref early break, caculate TX vref
8219 23:12:59.203230 TX Vref=16, minBit 1, minWin=22, winSum=377
8220 23:12:59.206000 TX Vref=18, minBit 1, minWin=22, winSum=385
8221 23:12:59.208812 TX Vref=20, minBit 1, minWin=23, winSum=396
8222 23:12:59.212973 TX Vref=22, minBit 1, minWin=24, winSum=405
8223 23:12:59.215979 TX Vref=24, minBit 0, minWin=25, winSum=416
8224 23:12:59.222490 TX Vref=26, minBit 1, minWin=24, winSum=413
8225 23:12:59.226069 TX Vref=28, minBit 0, minWin=24, winSum=406
8226 23:12:59.228738 TX Vref=30, minBit 1, minWin=23, winSum=403
8227 23:12:59.232988 TX Vref=32, minBit 7, minWin=23, winSum=395
8228 23:12:59.235545 TX Vref=34, minBit 1, minWin=23, winSum=392
8229 23:12:59.242535 [TxChooseVref] Worse bit 0, Min win 25, Win sum 416, Final Vref 24
8230 23:12:59.242646
8231 23:12:59.246188 Final TX Range 0 Vref 24
8232 23:12:59.246274
8233 23:12:59.246339 ==
8234 23:12:59.248984 Dram Type= 6, Freq= 0, CH_0, rank 1
8235 23:12:59.252439 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8236 23:12:59.252525 ==
8237 23:12:59.252590
8238 23:12:59.252650
8239 23:12:59.255525 TX Vref Scan disable
8240 23:12:59.261933 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8241 23:12:59.262031 == TX Byte 0 ==
8242 23:12:59.264876 u2DelayCellOfst[0]=11 cells (3 PI)
8243 23:12:59.268873 u2DelayCellOfst[1]=14 cells (4 PI)
8244 23:12:59.271877 u2DelayCellOfst[2]=11 cells (3 PI)
8245 23:12:59.274863 u2DelayCellOfst[3]=11 cells (3 PI)
8246 23:12:59.278679 u2DelayCellOfst[4]=7 cells (2 PI)
8247 23:12:59.281857 u2DelayCellOfst[5]=0 cells (0 PI)
8248 23:12:59.284854 u2DelayCellOfst[6]=14 cells (4 PI)
8249 23:12:59.288486 u2DelayCellOfst[7]=18 cells (5 PI)
8250 23:12:59.291444 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
8251 23:12:59.295626 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8252 23:12:59.298060 == TX Byte 1 ==
8253 23:12:59.301519 u2DelayCellOfst[8]=0 cells (0 PI)
8254 23:12:59.304797 u2DelayCellOfst[9]=0 cells (0 PI)
8255 23:12:59.304885 u2DelayCellOfst[10]=7 cells (2 PI)
8256 23:12:59.308136 u2DelayCellOfst[11]=3 cells (1 PI)
8257 23:12:59.311464 u2DelayCellOfst[12]=11 cells (3 PI)
8258 23:12:59.314840 u2DelayCellOfst[13]=11 cells (3 PI)
8259 23:12:59.318500 u2DelayCellOfst[14]=18 cells (5 PI)
8260 23:12:59.321496 u2DelayCellOfst[15]=11 cells (3 PI)
8261 23:12:59.327987 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8262 23:12:59.331297 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8263 23:12:59.331388 DramC Write-DBI on
8264 23:12:59.331454 ==
8265 23:12:59.335536 Dram Type= 6, Freq= 0, CH_0, rank 1
8266 23:12:59.341719 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8267 23:12:59.341825 ==
8268 23:12:59.341894
8269 23:12:59.341953
8270 23:12:59.344299 TX Vref Scan disable
8271 23:12:59.344387 == TX Byte 0 ==
8272 23:12:59.351104 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
8273 23:12:59.351198 == TX Byte 1 ==
8274 23:12:59.354418 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8275 23:12:59.357556 DramC Write-DBI off
8276 23:12:59.357642
8277 23:12:59.357706 [DATLAT]
8278 23:12:59.360774 Freq=1600, CH0 RK1
8279 23:12:59.360858
8280 23:12:59.360922 DATLAT Default: 0xf
8281 23:12:59.364328 0, 0xFFFF, sum = 0
8282 23:12:59.364414 1, 0xFFFF, sum = 0
8283 23:12:59.367254 2, 0xFFFF, sum = 0
8284 23:12:59.367355 3, 0xFFFF, sum = 0
8285 23:12:59.370795 4, 0xFFFF, sum = 0
8286 23:12:59.370881 5, 0xFFFF, sum = 0
8287 23:12:59.374313 6, 0xFFFF, sum = 0
8288 23:12:59.374402 7, 0xFFFF, sum = 0
8289 23:12:59.377584 8, 0xFFFF, sum = 0
8290 23:12:59.380455 9, 0xFFFF, sum = 0
8291 23:12:59.380543 10, 0xFFFF, sum = 0
8292 23:12:59.384135 11, 0xFFFF, sum = 0
8293 23:12:59.384223 12, 0xFFFF, sum = 0
8294 23:12:59.386938 13, 0xFFFF, sum = 0
8295 23:12:59.387023 14, 0x0, sum = 1
8296 23:12:59.390704 15, 0x0, sum = 2
8297 23:12:59.390793 16, 0x0, sum = 3
8298 23:12:59.394096 17, 0x0, sum = 4
8299 23:12:59.394182 best_step = 15
8300 23:12:59.394247
8301 23:12:59.394307 ==
8302 23:12:59.397800 Dram Type= 6, Freq= 0, CH_0, rank 1
8303 23:12:59.400876 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8304 23:12:59.400961 ==
8305 23:12:59.403564 RX Vref Scan: 0
8306 23:12:59.403657
8307 23:12:59.407364 RX Vref 0 -> 0, step: 1
8308 23:12:59.407448
8309 23:12:59.407548 RX Delay 11 -> 252, step: 4
8310 23:12:59.414067 iDelay=195, Bit 0, Center 126 (75 ~ 178) 104
8311 23:12:59.417415 iDelay=195, Bit 1, Center 134 (79 ~ 190) 112
8312 23:12:59.420951 iDelay=195, Bit 2, Center 124 (71 ~ 178) 108
8313 23:12:59.424134 iDelay=195, Bit 3, Center 126 (75 ~ 178) 104
8314 23:12:59.427614 iDelay=195, Bit 4, Center 132 (79 ~ 186) 108
8315 23:12:59.434546 iDelay=195, Bit 5, Center 120 (67 ~ 174) 108
8316 23:12:59.437667 iDelay=195, Bit 6, Center 136 (83 ~ 190) 108
8317 23:12:59.441306 iDelay=195, Bit 7, Center 140 (87 ~ 194) 108
8318 23:12:59.444124 iDelay=195, Bit 8, Center 114 (59 ~ 170) 112
8319 23:12:59.448093 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8320 23:12:59.454757 iDelay=195, Bit 10, Center 126 (71 ~ 182) 112
8321 23:12:59.457574 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8322 23:12:59.461499 iDelay=195, Bit 12, Center 132 (79 ~ 186) 108
8323 23:12:59.463899 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8324 23:12:59.470465 iDelay=195, Bit 14, Center 136 (83 ~ 190) 108
8325 23:12:59.473668 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8326 23:12:59.473762 ==
8327 23:12:59.476810 Dram Type= 6, Freq= 0, CH_0, rank 1
8328 23:12:59.480467 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8329 23:12:59.480557 ==
8330 23:12:59.484367 DQS Delay:
8331 23:12:59.484456 DQS0 = 0, DQS1 = 0
8332 23:12:59.484521 DQM Delay:
8333 23:12:59.486989 DQM0 = 129, DQM1 = 125
8334 23:12:59.487072 DQ Delay:
8335 23:12:59.490536 DQ0 =126, DQ1 =134, DQ2 =124, DQ3 =126
8336 23:12:59.493547 DQ4 =132, DQ5 =120, DQ6 =136, DQ7 =140
8337 23:12:59.497362 DQ8 =114, DQ9 =112, DQ10 =126, DQ11 =120
8338 23:12:59.503545 DQ12 =132, DQ13 =132, DQ14 =136, DQ15 =132
8339 23:12:59.503653
8340 23:12:59.503766
8341 23:12:59.503829
8342 23:12:59.506959 [DramC_TX_OE_Calibration] TA2
8343 23:12:59.510377 Original DQ_B0 (3 6) =30, OEN = 27
8344 23:12:59.510463 Original DQ_B1 (3 6) =30, OEN = 27
8345 23:12:59.513670 24, 0x0, End_B0=24 End_B1=24
8346 23:12:59.517349 25, 0x0, End_B0=25 End_B1=25
8347 23:12:59.520593 26, 0x0, End_B0=26 End_B1=26
8348 23:12:59.523659 27, 0x0, End_B0=27 End_B1=27
8349 23:12:59.523787 28, 0x0, End_B0=28 End_B1=28
8350 23:12:59.526734 29, 0x0, End_B0=29 End_B1=29
8351 23:12:59.529926 30, 0x0, End_B0=30 End_B1=30
8352 23:12:59.533376 31, 0x4141, End_B0=30 End_B1=30
8353 23:12:59.537275 Byte0 end_step=30 best_step=27
8354 23:12:59.539740 Byte1 end_step=30 best_step=27
8355 23:12:59.539846 Byte0 TX OE(2T, 0.5T) = (3, 3)
8356 23:12:59.543766 Byte1 TX OE(2T, 0.5T) = (3, 3)
8357 23:12:59.543851
8358 23:12:59.543914
8359 23:12:59.553213 [DQSOSCAuto] RK1, (LSB)MR18= 0x2104, (MSB)MR19= 0x303, tDQSOscB0 = 408 ps tDQSOscB1 = 393 ps
8360 23:12:59.556677 CH0 RK1: MR19=303, MR18=2104
8361 23:12:59.559693 CH0_RK1: MR19=0x303, MR18=0x2104, DQSOSC=393, MR23=63, INC=23, DEC=15
8362 23:12:59.563328 [RxdqsGatingPostProcess] freq 1600
8363 23:12:59.569763 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8364 23:12:59.573227 best DQS0 dly(2T, 0.5T) = (1, 1)
8365 23:12:59.576967 best DQS1 dly(2T, 0.5T) = (1, 1)
8366 23:12:59.579645 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8367 23:12:59.583196 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8368 23:12:59.586372 best DQS0 dly(2T, 0.5T) = (1, 1)
8369 23:12:59.586458 best DQS1 dly(2T, 0.5T) = (1, 1)
8370 23:12:59.589624 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8371 23:12:59.592905 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8372 23:12:59.596399 Pre-setting of DQS Precalculation
8373 23:12:59.602638 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8374 23:12:59.602738 ==
8375 23:12:59.605898 Dram Type= 6, Freq= 0, CH_1, rank 0
8376 23:12:59.609448 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8377 23:12:59.609537 ==
8378 23:12:59.616308 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8379 23:12:59.619379 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8380 23:12:59.623283 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8381 23:12:59.629442 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8382 23:12:59.639212 [CA 0] Center 41 (12~71) winsize 60
8383 23:12:59.641918 [CA 1] Center 41 (12~71) winsize 60
8384 23:12:59.645158 [CA 2] Center 37 (8~66) winsize 59
8385 23:12:59.648129 [CA 3] Center 36 (7~65) winsize 59
8386 23:12:59.651890 [CA 4] Center 37 (7~67) winsize 61
8387 23:12:59.655118 [CA 5] Center 36 (7~66) winsize 60
8388 23:12:59.655205
8389 23:12:59.658578 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8390 23:12:59.658664
8391 23:12:59.664778 [CATrainingPosCal] consider 1 rank data
8392 23:12:59.664870 u2DelayCellTimex100 = 262/100 ps
8393 23:12:59.671991 CA0 delay=41 (12~71),Diff = 5 PI (18 cell)
8394 23:12:59.674486 CA1 delay=41 (12~71),Diff = 5 PI (18 cell)
8395 23:12:59.678578 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8396 23:12:59.681001 CA3 delay=36 (7~65),Diff = 0 PI (0 cell)
8397 23:12:59.685078 CA4 delay=37 (7~67),Diff = 1 PI (3 cell)
8398 23:12:59.688245 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8399 23:12:59.688331
8400 23:12:59.691101 CA PerBit enable=1, Macro0, CA PI delay=36
8401 23:12:59.691221
8402 23:12:59.694301 [CBTSetCACLKResult] CA Dly = 36
8403 23:12:59.698426 CS Dly: 8 (0~39)
8404 23:12:59.701237 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8405 23:12:59.704266 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8406 23:12:59.704353 ==
8407 23:12:59.707442 Dram Type= 6, Freq= 0, CH_1, rank 1
8408 23:12:59.714101 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8409 23:12:59.714209 ==
8410 23:12:59.717549 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8411 23:12:59.724560 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8412 23:12:59.727514 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8413 23:12:59.734181 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8414 23:12:59.741545 [CA 0] Center 42 (13~72) winsize 60
8415 23:12:59.745673 [CA 1] Center 43 (14~72) winsize 59
8416 23:12:59.747965 [CA 2] Center 37 (8~67) winsize 60
8417 23:12:59.751783 [CA 3] Center 37 (7~67) winsize 61
8418 23:12:59.754865 [CA 4] Center 38 (9~67) winsize 59
8419 23:12:59.758438 [CA 5] Center 37 (8~67) winsize 60
8420 23:12:59.758533
8421 23:12:59.761287 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8422 23:12:59.761375
8423 23:12:59.767951 [CATrainingPosCal] consider 2 rank data
8424 23:12:59.768051 u2DelayCellTimex100 = 262/100 ps
8425 23:12:59.774708 CA0 delay=42 (13~71),Diff = 6 PI (22 cell)
8426 23:12:59.778039 CA1 delay=42 (14~71),Diff = 6 PI (22 cell)
8427 23:12:59.781345 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8428 23:12:59.785059 CA3 delay=36 (7~65),Diff = 0 PI (0 cell)
8429 23:12:59.788129 CA4 delay=38 (9~67),Diff = 2 PI (7 cell)
8430 23:12:59.791432 CA5 delay=37 (8~66),Diff = 1 PI (3 cell)
8431 23:12:59.791518
8432 23:12:59.794318 CA PerBit enable=1, Macro0, CA PI delay=36
8433 23:12:59.794402
8434 23:12:59.797975 [CBTSetCACLKResult] CA Dly = 36
8435 23:12:59.801422 CS Dly: 11 (0~45)
8436 23:12:59.804469 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8437 23:12:59.807530 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8438 23:12:59.807617
8439 23:12:59.811231 ----->DramcWriteLeveling(PI) begin...
8440 23:12:59.811318 ==
8441 23:12:59.814689 Dram Type= 6, Freq= 0, CH_1, rank 0
8442 23:12:59.820700 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8443 23:12:59.820814 ==
8444 23:12:59.823887 Write leveling (Byte 0): 23 => 23
8445 23:12:59.827311 Write leveling (Byte 1): 26 => 26
8446 23:12:59.827397 DramcWriteLeveling(PI) end<-----
8447 23:12:59.830508
8448 23:12:59.830592 ==
8449 23:12:59.833845 Dram Type= 6, Freq= 0, CH_1, rank 0
8450 23:12:59.837604 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8451 23:12:59.837699 ==
8452 23:12:59.840673 [Gating] SW mode calibration
8453 23:12:59.847008 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8454 23:12:59.850277 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8455 23:12:59.857261 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8456 23:12:59.860268 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8457 23:12:59.863400 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8458 23:12:59.870299 1 4 12 | B1->B0 | 3232 3434 | 0 0 | (0 0) (0 0)
8459 23:12:59.873476 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8460 23:12:59.876533 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8461 23:12:59.883546 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8462 23:12:59.886365 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8463 23:12:59.893194 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8464 23:12:59.896556 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8465 23:12:59.900439 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8466 23:12:59.903377 1 5 12 | B1->B0 | 2d2d 2323 | 0 0 | (0 1) (0 0)
8467 23:12:59.909489 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8468 23:12:59.912938 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8469 23:12:59.919520 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8470 23:12:59.922779 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8471 23:12:59.926070 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8472 23:12:59.929262 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8473 23:12:59.936057 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8474 23:12:59.939258 1 6 12 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
8475 23:12:59.943160 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8476 23:12:59.949475 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8477 23:12:59.952510 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8478 23:12:59.958960 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8479 23:12:59.962293 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8480 23:12:59.965513 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8481 23:12:59.972515 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8482 23:12:59.975808 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8483 23:12:59.978773 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8484 23:12:59.985595 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8485 23:12:59.989112 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8486 23:12:59.991711 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8487 23:12:59.998448 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8488 23:13:00.002236 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8489 23:13:00.005716 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8490 23:13:00.012021 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8491 23:13:00.015378 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8492 23:13:00.018243 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8493 23:13:00.021930 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8494 23:13:00.028156 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8495 23:13:00.031513 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8496 23:13:00.035815 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8497 23:13:00.041512 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8498 23:13:00.045681 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8499 23:13:00.048080 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8500 23:13:00.051356 Total UI for P1: 0, mck2ui 16
8501 23:13:00.055811 best dqsien dly found for B0: ( 1, 9, 10)
8502 23:13:00.061562 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8503 23:13:00.065119 Total UI for P1: 0, mck2ui 16
8504 23:13:00.067910 best dqsien dly found for B1: ( 1, 9, 14)
8505 23:13:00.072333 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8506 23:13:00.074763 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8507 23:13:00.074853
8508 23:13:00.077936 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8509 23:13:00.081217 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8510 23:13:00.084311 [Gating] SW calibration Done
8511 23:13:00.084398 ==
8512 23:13:00.087906 Dram Type= 6, Freq= 0, CH_1, rank 0
8513 23:13:00.091091 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8514 23:13:00.091179 ==
8515 23:13:00.094911 RX Vref Scan: 0
8516 23:13:00.094998
8517 23:13:00.098098 RX Vref 0 -> 0, step: 1
8518 23:13:00.098183
8519 23:13:00.098248 RX Delay 0 -> 252, step: 8
8520 23:13:00.104291 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8521 23:13:00.107627 iDelay=208, Bit 1, Center 131 (80 ~ 183) 104
8522 23:13:00.111257 iDelay=208, Bit 2, Center 127 (72 ~ 183) 112
8523 23:13:00.114326 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8524 23:13:00.118128 iDelay=208, Bit 4, Center 135 (80 ~ 191) 112
8525 23:13:00.124128 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8526 23:13:00.127819 iDelay=208, Bit 6, Center 147 (96 ~ 199) 104
8527 23:13:00.130950 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8528 23:13:00.134026 iDelay=208, Bit 8, Center 115 (56 ~ 175) 120
8529 23:13:00.138106 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8530 23:13:00.144155 iDelay=208, Bit 10, Center 127 (72 ~ 183) 112
8531 23:13:00.147375 iDelay=208, Bit 11, Center 123 (72 ~ 175) 104
8532 23:13:00.150481 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8533 23:13:00.153766 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8534 23:13:00.160745 iDelay=208, Bit 14, Center 135 (80 ~ 191) 112
8535 23:13:00.164112 iDelay=208, Bit 15, Center 135 (80 ~ 191) 112
8536 23:13:00.164206 ==
8537 23:13:00.167355 Dram Type= 6, Freq= 0, CH_1, rank 0
8538 23:13:00.170227 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8539 23:13:00.170314 ==
8540 23:13:00.170380 DQS Delay:
8541 23:13:00.174178 DQS0 = 0, DQS1 = 0
8542 23:13:00.174265 DQM Delay:
8543 23:13:00.176840 DQM0 = 137, DQM1 = 128
8544 23:13:00.176931 DQ Delay:
8545 23:13:00.180627 DQ0 =139, DQ1 =131, DQ2 =127, DQ3 =131
8546 23:13:00.183788 DQ4 =135, DQ5 =151, DQ6 =147, DQ7 =135
8547 23:13:00.187297 DQ8 =115, DQ9 =115, DQ10 =127, DQ11 =123
8548 23:13:00.193780 DQ12 =135, DQ13 =139, DQ14 =135, DQ15 =135
8549 23:13:00.193883
8550 23:13:00.193957
8551 23:13:00.194019 ==
8552 23:13:00.196908 Dram Type= 6, Freq= 0, CH_1, rank 0
8553 23:13:00.200793 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8554 23:13:00.200870 ==
8555 23:13:00.200940
8556 23:13:00.200999
8557 23:13:00.203822 TX Vref Scan disable
8558 23:13:00.203889 == TX Byte 0 ==
8559 23:13:00.209920 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8560 23:13:00.213766 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8561 23:13:00.213854 == TX Byte 1 ==
8562 23:13:00.220659 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8563 23:13:00.223459 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8564 23:13:00.223535 ==
8565 23:13:00.227294 Dram Type= 6, Freq= 0, CH_1, rank 0
8566 23:13:00.229489 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8567 23:13:00.229563 ==
8568 23:13:00.244066
8569 23:13:00.247166 TX Vref early break, caculate TX vref
8570 23:13:00.250501 TX Vref=16, minBit 0, minWin=21, winSum=371
8571 23:13:00.253560 TX Vref=18, minBit 0, minWin=22, winSum=383
8572 23:13:00.257425 TX Vref=20, minBit 0, minWin=23, winSum=391
8573 23:13:00.260379 TX Vref=22, minBit 0, minWin=22, winSum=401
8574 23:13:00.263519 TX Vref=24, minBit 0, minWin=24, winSum=412
8575 23:13:00.269906 TX Vref=26, minBit 0, minWin=24, winSum=418
8576 23:13:00.273320 TX Vref=28, minBit 0, minWin=24, winSum=413
8577 23:13:00.276348 TX Vref=30, minBit 5, minWin=23, winSum=409
8578 23:13:00.279944 TX Vref=32, minBit 0, minWin=23, winSum=398
8579 23:13:00.283250 TX Vref=34, minBit 5, minWin=22, winSum=389
8580 23:13:00.289905 [TxChooseVref] Worse bit 0, Min win 24, Win sum 418, Final Vref 26
8581 23:13:00.290020
8582 23:13:00.293284 Final TX Range 0 Vref 26
8583 23:13:00.293369
8584 23:13:00.293433 ==
8585 23:13:00.297005 Dram Type= 6, Freq= 0, CH_1, rank 0
8586 23:13:00.299778 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8587 23:13:00.299855 ==
8588 23:13:00.299917
8589 23:13:00.299975
8590 23:13:00.302994 TX Vref Scan disable
8591 23:13:00.309442 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8592 23:13:00.309542 == TX Byte 0 ==
8593 23:13:00.313218 u2DelayCellOfst[0]=18 cells (5 PI)
8594 23:13:00.316375 u2DelayCellOfst[1]=14 cells (4 PI)
8595 23:13:00.319439 u2DelayCellOfst[2]=0 cells (0 PI)
8596 23:13:00.323093 u2DelayCellOfst[3]=7 cells (2 PI)
8597 23:13:00.326374 u2DelayCellOfst[4]=11 cells (3 PI)
8598 23:13:00.329806 u2DelayCellOfst[5]=22 cells (6 PI)
8599 23:13:00.332896 u2DelayCellOfst[6]=22 cells (6 PI)
8600 23:13:00.336609 u2DelayCellOfst[7]=7 cells (2 PI)
8601 23:13:00.339871 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8602 23:13:00.342930 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8603 23:13:00.345841 == TX Byte 1 ==
8604 23:13:00.349331 u2DelayCellOfst[8]=0 cells (0 PI)
8605 23:13:00.352959 u2DelayCellOfst[9]=3 cells (1 PI)
8606 23:13:00.355893 u2DelayCellOfst[10]=11 cells (3 PI)
8607 23:13:00.355981 u2DelayCellOfst[11]=7 cells (2 PI)
8608 23:13:00.359086 u2DelayCellOfst[12]=14 cells (4 PI)
8609 23:13:00.362663 u2DelayCellOfst[13]=18 cells (5 PI)
8610 23:13:00.365669 u2DelayCellOfst[14]=18 cells (5 PI)
8611 23:13:00.368856 u2DelayCellOfst[15]=18 cells (5 PI)
8612 23:13:00.376194 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8613 23:13:00.378829 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8614 23:13:00.378924 DramC Write-DBI on
8615 23:13:00.378990 ==
8616 23:13:00.382285 Dram Type= 6, Freq= 0, CH_1, rank 0
8617 23:13:00.389194 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8618 23:13:00.389303 ==
8619 23:13:00.389369
8620 23:13:00.389428
8621 23:13:00.392125 TX Vref Scan disable
8622 23:13:00.392212 == TX Byte 0 ==
8623 23:13:00.399003 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8624 23:13:00.399107 == TX Byte 1 ==
8625 23:13:00.401872 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8626 23:13:00.405710 DramC Write-DBI off
8627 23:13:00.405802
8628 23:13:00.405867 [DATLAT]
8629 23:13:00.408816 Freq=1600, CH1 RK0
8630 23:13:00.408901
8631 23:13:00.408966 DATLAT Default: 0xf
8632 23:13:00.412014 0, 0xFFFF, sum = 0
8633 23:13:00.412100 1, 0xFFFF, sum = 0
8634 23:13:00.414871 2, 0xFFFF, sum = 0
8635 23:13:00.414957 3, 0xFFFF, sum = 0
8636 23:13:00.418419 4, 0xFFFF, sum = 0
8637 23:13:00.418507 5, 0xFFFF, sum = 0
8638 23:13:00.421570 6, 0xFFFF, sum = 0
8639 23:13:00.425188 7, 0xFFFF, sum = 0
8640 23:13:00.425278 8, 0xFFFF, sum = 0
8641 23:13:00.428738 9, 0xFFFF, sum = 0
8642 23:13:00.428830 10, 0xFFFF, sum = 0
8643 23:13:00.431506 11, 0xFFFF, sum = 0
8644 23:13:00.431592 12, 0xFFFF, sum = 0
8645 23:13:00.434930 13, 0xFFFF, sum = 0
8646 23:13:00.435017 14, 0x0, sum = 1
8647 23:13:00.438074 15, 0x0, sum = 2
8648 23:13:00.438161 16, 0x0, sum = 3
8649 23:13:00.441915 17, 0x0, sum = 4
8650 23:13:00.442002 best_step = 15
8651 23:13:00.442067
8652 23:13:00.442127 ==
8653 23:13:00.444561 Dram Type= 6, Freq= 0, CH_1, rank 0
8654 23:13:00.448014 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8655 23:13:00.451813 ==
8656 23:13:00.451901 RX Vref Scan: 1
8657 23:13:00.451968
8658 23:13:00.455056 Set Vref Range= 24 -> 127
8659 23:13:00.455141
8660 23:13:00.455206 RX Vref 24 -> 127, step: 1
8661 23:13:00.458148
8662 23:13:00.458231 RX Delay 11 -> 252, step: 4
8663 23:13:00.458297
8664 23:13:00.461296 Set Vref, RX VrefLevel [Byte0]: 24
8665 23:13:00.464643 [Byte1]: 24
8666 23:13:00.468523
8667 23:13:00.468614 Set Vref, RX VrefLevel [Byte0]: 25
8668 23:13:00.471648 [Byte1]: 25
8669 23:13:00.475797
8670 23:13:00.475893 Set Vref, RX VrefLevel [Byte0]: 26
8671 23:13:00.479389 [Byte1]: 26
8672 23:13:00.483460
8673 23:13:00.483551 Set Vref, RX VrefLevel [Byte0]: 27
8674 23:13:00.487355 [Byte1]: 27
8675 23:13:00.490921
8676 23:13:00.491012 Set Vref, RX VrefLevel [Byte0]: 28
8677 23:13:00.494363 [Byte1]: 28
8678 23:13:00.498996
8679 23:13:00.499105 Set Vref, RX VrefLevel [Byte0]: 29
8680 23:13:00.502294 [Byte1]: 29
8681 23:13:00.506638
8682 23:13:00.506731 Set Vref, RX VrefLevel [Byte0]: 30
8683 23:13:00.510089 [Byte1]: 30
8684 23:13:00.513933
8685 23:13:00.514023 Set Vref, RX VrefLevel [Byte0]: 31
8686 23:13:00.517353 [Byte1]: 31
8687 23:13:00.521822
8688 23:13:00.521916 Set Vref, RX VrefLevel [Byte0]: 32
8689 23:13:00.527621 [Byte1]: 32
8690 23:13:00.527743
8691 23:13:00.531008 Set Vref, RX VrefLevel [Byte0]: 33
8692 23:13:00.534553 [Byte1]: 33
8693 23:13:00.534643
8694 23:13:00.537743 Set Vref, RX VrefLevel [Byte0]: 34
8695 23:13:00.541699 [Byte1]: 34
8696 23:13:00.544278
8697 23:13:00.544363 Set Vref, RX VrefLevel [Byte0]: 35
8698 23:13:00.547496 [Byte1]: 35
8699 23:13:00.552872
8700 23:13:00.552966 Set Vref, RX VrefLevel [Byte0]: 36
8701 23:13:00.555456 [Byte1]: 36
8702 23:13:00.559811
8703 23:13:00.559903 Set Vref, RX VrefLevel [Byte0]: 37
8704 23:13:00.563194 [Byte1]: 37
8705 23:13:00.567117
8706 23:13:00.567229 Set Vref, RX VrefLevel [Byte0]: 38
8707 23:13:00.570689 [Byte1]: 38
8708 23:13:00.574986
8709 23:13:00.575079 Set Vref, RX VrefLevel [Byte0]: 39
8710 23:13:00.578017 [Byte1]: 39
8711 23:13:00.582620
8712 23:13:00.582713 Set Vref, RX VrefLevel [Byte0]: 40
8713 23:13:00.585565 [Byte1]: 40
8714 23:13:00.590744
8715 23:13:00.590839 Set Vref, RX VrefLevel [Byte0]: 41
8716 23:13:00.593483 [Byte1]: 41
8717 23:13:00.597776
8718 23:13:00.597866 Set Vref, RX VrefLevel [Byte0]: 42
8719 23:13:00.601121 [Byte1]: 42
8720 23:13:00.605118
8721 23:13:00.605228 Set Vref, RX VrefLevel [Byte0]: 43
8722 23:13:00.608425 [Byte1]: 43
8723 23:13:00.613055
8724 23:13:00.613150 Set Vref, RX VrefLevel [Byte0]: 44
8725 23:13:00.616006 [Byte1]: 44
8726 23:13:00.620402
8727 23:13:00.620496 Set Vref, RX VrefLevel [Byte0]: 45
8728 23:13:00.623867 [Byte1]: 45
8729 23:13:00.628426
8730 23:13:00.628526 Set Vref, RX VrefLevel [Byte0]: 46
8731 23:13:00.631538 [Byte1]: 46
8732 23:13:00.635536
8733 23:13:00.635633 Set Vref, RX VrefLevel [Byte0]: 47
8734 23:13:00.639388 [Byte1]: 47
8735 23:13:00.643516
8736 23:13:00.643610 Set Vref, RX VrefLevel [Byte0]: 48
8737 23:13:00.646845 [Byte1]: 48
8738 23:13:00.650792
8739 23:13:00.650881 Set Vref, RX VrefLevel [Byte0]: 49
8740 23:13:00.654160 [Byte1]: 49
8741 23:13:00.658386
8742 23:13:00.658478 Set Vref, RX VrefLevel [Byte0]: 50
8743 23:13:00.661847 [Byte1]: 50
8744 23:13:00.666290
8745 23:13:00.666382 Set Vref, RX VrefLevel [Byte0]: 51
8746 23:13:00.669728 [Byte1]: 51
8747 23:13:00.673500
8748 23:13:00.673582 Set Vref, RX VrefLevel [Byte0]: 52
8749 23:13:00.676918 [Byte1]: 52
8750 23:13:00.681306
8751 23:13:00.681401 Set Vref, RX VrefLevel [Byte0]: 53
8752 23:13:00.684700 [Byte1]: 53
8753 23:13:00.688824
8754 23:13:00.688914 Set Vref, RX VrefLevel [Byte0]: 54
8755 23:13:00.692555 [Byte1]: 54
8756 23:13:00.697484
8757 23:13:00.697587 Set Vref, RX VrefLevel [Byte0]: 55
8758 23:13:00.699876 [Byte1]: 55
8759 23:13:00.704064
8760 23:13:00.704159 Set Vref, RX VrefLevel [Byte0]: 56
8761 23:13:00.708021 [Byte1]: 56
8762 23:13:00.711573
8763 23:13:00.711665 Set Vref, RX VrefLevel [Byte0]: 57
8764 23:13:00.715095 [Byte1]: 57
8765 23:13:00.720030
8766 23:13:00.720128 Set Vref, RX VrefLevel [Byte0]: 58
8767 23:13:00.722822 [Byte1]: 58
8768 23:13:00.727061
8769 23:13:00.727156 Set Vref, RX VrefLevel [Byte0]: 59
8770 23:13:00.730181 [Byte1]: 59
8771 23:13:00.734405
8772 23:13:00.734498 Set Vref, RX VrefLevel [Byte0]: 60
8773 23:13:00.737726 [Byte1]: 60
8774 23:13:00.742385
8775 23:13:00.742484 Set Vref, RX VrefLevel [Byte0]: 61
8776 23:13:00.745935 [Byte1]: 61
8777 23:13:00.749636
8778 23:13:00.749739 Set Vref, RX VrefLevel [Byte0]: 62
8779 23:13:00.753056 [Byte1]: 62
8780 23:13:00.757611
8781 23:13:00.757700 Set Vref, RX VrefLevel [Byte0]: 63
8782 23:13:00.761910 [Byte1]: 63
8783 23:13:00.765028
8784 23:13:00.765117 Set Vref, RX VrefLevel [Byte0]: 64
8785 23:13:00.768871 [Byte1]: 64
8786 23:13:00.772779
8787 23:13:00.772867 Set Vref, RX VrefLevel [Byte0]: 65
8788 23:13:00.776208 [Byte1]: 65
8789 23:13:00.780023
8790 23:13:00.780114 Set Vref, RX VrefLevel [Byte0]: 66
8791 23:13:00.783401 [Byte1]: 66
8792 23:13:00.788335
8793 23:13:00.788434 Set Vref, RX VrefLevel [Byte0]: 67
8794 23:13:00.791337 [Byte1]: 67
8795 23:13:00.795653
8796 23:13:00.795769 Set Vref, RX VrefLevel [Byte0]: 68
8797 23:13:00.798885 [Byte1]: 68
8798 23:13:00.802895
8799 23:13:00.802979 Set Vref, RX VrefLevel [Byte0]: 69
8800 23:13:00.806556 [Byte1]: 69
8801 23:13:00.810613
8802 23:13:00.810700 Set Vref, RX VrefLevel [Byte0]: 70
8803 23:13:00.814972 [Byte1]: 70
8804 23:13:00.818551
8805 23:13:00.818643 Set Vref, RX VrefLevel [Byte0]: 71
8806 23:13:00.821566 [Byte1]: 71
8807 23:13:00.825826
8808 23:13:00.825915 Set Vref, RX VrefLevel [Byte0]: 72
8809 23:13:00.829288 [Byte1]: 72
8810 23:13:00.834064
8811 23:13:00.834159 Set Vref, RX VrefLevel [Byte0]: 73
8812 23:13:00.837039 [Byte1]: 73
8813 23:13:00.841233
8814 23:13:00.841333 Set Vref, RX VrefLevel [Byte0]: 74
8815 23:13:00.844763 [Byte1]: 74
8816 23:13:00.848910
8817 23:13:00.849000 Set Vref, RX VrefLevel [Byte0]: 75
8818 23:13:00.851945 [Byte1]: 75
8819 23:13:00.856540
8820 23:13:00.856631 Final RX Vref Byte 0 = 54 to rank0
8821 23:13:00.859646 Final RX Vref Byte 1 = 57 to rank0
8822 23:13:00.862864 Final RX Vref Byte 0 = 54 to rank1
8823 23:13:00.866917 Final RX Vref Byte 1 = 57 to rank1==
8824 23:13:00.870225 Dram Type= 6, Freq= 0, CH_1, rank 0
8825 23:13:00.876747 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8826 23:13:00.876846 ==
8827 23:13:00.876908 DQS Delay:
8828 23:13:00.876965 DQS0 = 0, DQS1 = 0
8829 23:13:00.879854 DQM Delay:
8830 23:13:00.879924 DQM0 = 133, DQM1 = 127
8831 23:13:00.882935 DQ Delay:
8832 23:13:00.885994 DQ0 =140, DQ1 =128, DQ2 =124, DQ3 =130
8833 23:13:00.889367 DQ4 =130, DQ5 =146, DQ6 =142, DQ7 =128
8834 23:13:00.893005 DQ8 =116, DQ9 =114, DQ10 =130, DQ11 =116
8835 23:13:00.896362 DQ12 =134, DQ13 =136, DQ14 =136, DQ15 =138
8836 23:13:00.896442
8837 23:13:00.896502
8838 23:13:00.896558
8839 23:13:00.899599 [DramC_TX_OE_Calibration] TA2
8840 23:13:00.902614 Original DQ_B0 (3 6) =30, OEN = 27
8841 23:13:00.906201 Original DQ_B1 (3 6) =30, OEN = 27
8842 23:13:00.909466 24, 0x0, End_B0=24 End_B1=24
8843 23:13:00.909580 25, 0x0, End_B0=25 End_B1=25
8844 23:13:00.912599 26, 0x0, End_B0=26 End_B1=26
8845 23:13:00.915704 27, 0x0, End_B0=27 End_B1=27
8846 23:13:00.919039 28, 0x0, End_B0=28 End_B1=28
8847 23:13:00.922790 29, 0x0, End_B0=29 End_B1=29
8848 23:13:00.922886 30, 0x0, End_B0=30 End_B1=30
8849 23:13:00.925978 31, 0x4141, End_B0=30 End_B1=30
8850 23:13:00.929370 Byte0 end_step=30 best_step=27
8851 23:13:00.933006 Byte1 end_step=30 best_step=27
8852 23:13:00.936102 Byte0 TX OE(2T, 0.5T) = (3, 3)
8853 23:13:00.939318 Byte1 TX OE(2T, 0.5T) = (3, 3)
8854 23:13:00.939408
8855 23:13:00.939473
8856 23:13:00.945597 [DQSOSCAuto] RK0, (LSB)MR18= 0x170d, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 398 ps
8857 23:13:00.949172 CH1 RK0: MR19=303, MR18=170D
8858 23:13:00.956137 CH1_RK0: MR19=0x303, MR18=0x170D, DQSOSC=398, MR23=63, INC=23, DEC=15
8859 23:13:00.956247
8860 23:13:00.960040 ----->DramcWriteLeveling(PI) begin...
8861 23:13:00.960131 ==
8862 23:13:00.962309 Dram Type= 6, Freq= 0, CH_1, rank 1
8863 23:13:00.965188 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8864 23:13:00.965272 ==
8865 23:13:00.968694 Write leveling (Byte 0): 23 => 23
8866 23:13:00.972141 Write leveling (Byte 1): 27 => 27
8867 23:13:00.975435 DramcWriteLeveling(PI) end<-----
8868 23:13:00.975528
8869 23:13:00.975646 ==
8870 23:13:00.979603 Dram Type= 6, Freq= 0, CH_1, rank 1
8871 23:13:00.982117 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8872 23:13:00.985039 ==
8873 23:13:00.985119 [Gating] SW mode calibration
8874 23:13:00.994914 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8875 23:13:00.998318 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8876 23:13:01.002740 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8877 23:13:01.008187 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8878 23:13:01.011581 1 4 8 | B1->B0 | 2625 2323 | 1 0 | (0 0) (0 0)
8879 23:13:01.014730 1 4 12 | B1->B0 | 3434 2424 | 1 1 | (1 1) (0 0)
8880 23:13:01.021348 1 4 16 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
8881 23:13:01.024772 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8882 23:13:01.028390 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8883 23:13:01.034759 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8884 23:13:01.037762 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8885 23:13:01.041314 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8886 23:13:01.047598 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8887 23:13:01.051081 1 5 12 | B1->B0 | 2626 3434 | 0 1 | (1 0) (1 0)
8888 23:13:01.054177 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8889 23:13:01.060620 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8890 23:13:01.064404 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8891 23:13:01.067937 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8892 23:13:01.074297 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8893 23:13:01.077390 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8894 23:13:01.080448 1 6 8 | B1->B0 | 2f2f 2323 | 0 0 | (1 1) (0 0)
8895 23:13:01.087009 1 6 12 | B1->B0 | 4545 2828 | 0 1 | (0 0) (0 0)
8896 23:13:01.090692 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8897 23:13:01.093601 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8898 23:13:01.100239 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8899 23:13:01.103871 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8900 23:13:01.106832 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8901 23:13:01.113249 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8902 23:13:01.117491 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8903 23:13:01.123079 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8904 23:13:01.126438 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8905 23:13:01.130332 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8906 23:13:01.136471 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8907 23:13:01.140022 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8908 23:13:01.143902 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8909 23:13:01.149860 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8910 23:13:01.152805 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8911 23:13:01.156091 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8912 23:13:01.162678 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8913 23:13:01.166465 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8914 23:13:01.169549 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8915 23:13:01.175700 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8916 23:13:01.179244 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8917 23:13:01.182755 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8918 23:13:01.189342 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8919 23:13:01.192885 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8920 23:13:01.195492 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8921 23:13:01.198743 Total UI for P1: 0, mck2ui 16
8922 23:13:01.202302 best dqsien dly found for B0: ( 1, 9, 10)
8923 23:13:01.205515 Total UI for P1: 0, mck2ui 16
8924 23:13:01.208881 best dqsien dly found for B1: ( 1, 9, 10)
8925 23:13:01.212886 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8926 23:13:01.215697 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8927 23:13:01.215795
8928 23:13:01.218926 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8929 23:13:01.225631 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8930 23:13:01.225729 [Gating] SW calibration Done
8931 23:13:01.228581 ==
8932 23:13:01.232602 Dram Type= 6, Freq= 0, CH_1, rank 1
8933 23:13:01.235352 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8934 23:13:01.235437 ==
8935 23:13:01.235500 RX Vref Scan: 0
8936 23:13:01.235559
8937 23:13:01.238332 RX Vref 0 -> 0, step: 1
8938 23:13:01.238404
8939 23:13:01.241762 RX Delay 0 -> 252, step: 8
8940 23:13:01.244816 iDelay=208, Bit 0, Center 143 (88 ~ 199) 112
8941 23:13:01.248825 iDelay=208, Bit 1, Center 131 (72 ~ 191) 120
8942 23:13:01.251500 iDelay=208, Bit 2, Center 123 (64 ~ 183) 120
8943 23:13:01.258687 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8944 23:13:01.262338 iDelay=208, Bit 4, Center 131 (72 ~ 191) 120
8945 23:13:01.264941 iDelay=208, Bit 5, Center 147 (88 ~ 207) 120
8946 23:13:01.268136 iDelay=208, Bit 6, Center 147 (88 ~ 207) 120
8947 23:13:01.271564 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8948 23:13:01.278127 iDelay=208, Bit 8, Center 115 (56 ~ 175) 120
8949 23:13:01.281647 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8950 23:13:01.284475 iDelay=208, Bit 10, Center 131 (72 ~ 191) 120
8951 23:13:01.287660 iDelay=208, Bit 11, Center 119 (64 ~ 175) 112
8952 23:13:01.294638 iDelay=208, Bit 12, Center 139 (80 ~ 199) 120
8953 23:13:01.297825 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8954 23:13:01.301252 iDelay=208, Bit 14, Center 135 (72 ~ 199) 128
8955 23:13:01.304498 iDelay=208, Bit 15, Center 139 (80 ~ 199) 120
8956 23:13:01.304590 ==
8957 23:13:01.308180 Dram Type= 6, Freq= 0, CH_1, rank 1
8958 23:13:01.314676 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8959 23:13:01.314783 ==
8960 23:13:01.314850 DQS Delay:
8961 23:13:01.317944 DQS0 = 0, DQS1 = 0
8962 23:13:01.318031 DQM Delay:
8963 23:13:01.318096 DQM0 = 136, DQM1 = 129
8964 23:13:01.321557 DQ Delay:
8965 23:13:01.324132 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8966 23:13:01.328285 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8967 23:13:01.330843 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119
8968 23:13:01.334123 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =139
8969 23:13:01.334211
8970 23:13:01.334277
8971 23:13:01.334336 ==
8972 23:13:01.337371 Dram Type= 6, Freq= 0, CH_1, rank 1
8973 23:13:01.344329 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8974 23:13:01.344438 ==
8975 23:13:01.344505
8976 23:13:01.344565
8977 23:13:01.344621 TX Vref Scan disable
8978 23:13:01.347150 == TX Byte 0 ==
8979 23:13:01.350569 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8980 23:13:01.357907 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8981 23:13:01.358014 == TX Byte 1 ==
8982 23:13:01.361410 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8983 23:13:01.367461 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8984 23:13:01.367559 ==
8985 23:13:01.370603 Dram Type= 6, Freq= 0, CH_1, rank 1
8986 23:13:01.373375 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8987 23:13:01.373462 ==
8988 23:13:01.386467
8989 23:13:01.390506 TX Vref early break, caculate TX vref
8990 23:13:01.393382 TX Vref=16, minBit 0, minWin=22, winSum=373
8991 23:13:01.396584 TX Vref=18, minBit 0, minWin=22, winSum=389
8992 23:13:01.399319 TX Vref=20, minBit 0, minWin=23, winSum=399
8993 23:13:01.402607 TX Vref=22, minBit 1, minWin=24, winSum=407
8994 23:13:01.406690 TX Vref=24, minBit 5, minWin=24, winSum=411
8995 23:13:01.413321 TX Vref=26, minBit 0, minWin=24, winSum=418
8996 23:13:01.415485 TX Vref=28, minBit 1, minWin=24, winSum=417
8997 23:13:01.419515 TX Vref=30, minBit 0, minWin=24, winSum=412
8998 23:13:01.422196 TX Vref=32, minBit 0, minWin=23, winSum=403
8999 23:13:01.426182 TX Vref=34, minBit 0, minWin=23, winSum=396
9000 23:13:01.432376 [TxChooseVref] Worse bit 0, Min win 24, Win sum 418, Final Vref 26
9001 23:13:01.432479
9002 23:13:01.435700 Final TX Range 0 Vref 26
9003 23:13:01.435788
9004 23:13:01.435853 ==
9005 23:13:01.438598 Dram Type= 6, Freq= 0, CH_1, rank 1
9006 23:13:01.442161 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9007 23:13:01.442256 ==
9008 23:13:01.442322
9009 23:13:01.442383
9010 23:13:01.445439 TX Vref Scan disable
9011 23:13:01.452008 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
9012 23:13:01.452109 == TX Byte 0 ==
9013 23:13:01.455023 u2DelayCellOfst[0]=18 cells (5 PI)
9014 23:13:01.458585 u2DelayCellOfst[1]=11 cells (3 PI)
9015 23:13:01.461887 u2DelayCellOfst[2]=0 cells (0 PI)
9016 23:13:01.465143 u2DelayCellOfst[3]=7 cells (2 PI)
9017 23:13:01.468214 u2DelayCellOfst[4]=7 cells (2 PI)
9018 23:13:01.471570 u2DelayCellOfst[5]=18 cells (5 PI)
9019 23:13:01.474943 u2DelayCellOfst[6]=18 cells (5 PI)
9020 23:13:01.478070 u2DelayCellOfst[7]=3 cells (1 PI)
9021 23:13:01.481673 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
9022 23:13:01.484907 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
9023 23:13:01.488880 == TX Byte 1 ==
9024 23:13:01.491389 u2DelayCellOfst[8]=0 cells (0 PI)
9025 23:13:01.495247 u2DelayCellOfst[9]=7 cells (2 PI)
9026 23:13:01.498334 u2DelayCellOfst[10]=11 cells (3 PI)
9027 23:13:01.500930 u2DelayCellOfst[11]=7 cells (2 PI)
9028 23:13:01.504808 u2DelayCellOfst[12]=14 cells (4 PI)
9029 23:13:01.504925 u2DelayCellOfst[13]=18 cells (5 PI)
9030 23:13:01.507723 u2DelayCellOfst[14]=18 cells (5 PI)
9031 23:13:01.512278 u2DelayCellOfst[15]=18 cells (5 PI)
9032 23:13:01.517510 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
9033 23:13:01.521182 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
9034 23:13:01.521314 DramC Write-DBI on
9035 23:13:01.524692 ==
9036 23:13:01.527727 Dram Type= 6, Freq= 0, CH_1, rank 1
9037 23:13:01.531574 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9038 23:13:01.531665 ==
9039 23:13:01.531778
9040 23:13:01.531839
9041 23:13:01.534350 TX Vref Scan disable
9042 23:13:01.534433 == TX Byte 0 ==
9043 23:13:01.541150 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
9044 23:13:01.541257 == TX Byte 1 ==
9045 23:13:01.543703 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
9046 23:13:01.547322 DramC Write-DBI off
9047 23:13:01.547412
9048 23:13:01.547489 [DATLAT]
9049 23:13:01.550928 Freq=1600, CH1 RK1
9050 23:13:01.551014
9051 23:13:01.551079 DATLAT Default: 0xf
9052 23:13:01.553768 0, 0xFFFF, sum = 0
9053 23:13:01.553856 1, 0xFFFF, sum = 0
9054 23:13:01.557570 2, 0xFFFF, sum = 0
9055 23:13:01.557657 3, 0xFFFF, sum = 0
9056 23:13:01.560520 4, 0xFFFF, sum = 0
9057 23:13:01.560605 5, 0xFFFF, sum = 0
9058 23:13:01.564855 6, 0xFFFF, sum = 0
9059 23:13:01.567662 7, 0xFFFF, sum = 0
9060 23:13:01.567791 8, 0xFFFF, sum = 0
9061 23:13:01.570594 9, 0xFFFF, sum = 0
9062 23:13:01.570679 10, 0xFFFF, sum = 0
9063 23:13:01.573851 11, 0xFFFF, sum = 0
9064 23:13:01.573963 12, 0xFFFF, sum = 0
9065 23:13:01.577857 13, 0xFFFF, sum = 0
9066 23:13:01.577977 14, 0x0, sum = 1
9067 23:13:01.580176 15, 0x0, sum = 2
9068 23:13:01.580261 16, 0x0, sum = 3
9069 23:13:01.583882 17, 0x0, sum = 4
9070 23:13:01.583967 best_step = 15
9071 23:13:01.584031
9072 23:13:01.584090 ==
9073 23:13:01.587858 Dram Type= 6, Freq= 0, CH_1, rank 1
9074 23:13:01.593852 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9075 23:13:01.593952 ==
9076 23:13:01.594017 RX Vref Scan: 0
9077 23:13:01.594077
9078 23:13:01.597361 RX Vref 0 -> 0, step: 1
9079 23:13:01.597446
9080 23:13:01.600022 RX Delay 11 -> 252, step: 4
9081 23:13:01.603412 iDelay=203, Bit 0, Center 140 (87 ~ 194) 108
9082 23:13:01.607052 iDelay=203, Bit 1, Center 128 (75 ~ 182) 108
9083 23:13:01.610411 iDelay=203, Bit 2, Center 122 (67 ~ 178) 112
9084 23:13:01.616198 iDelay=203, Bit 3, Center 130 (79 ~ 182) 104
9085 23:13:01.619451 iDelay=203, Bit 4, Center 132 (75 ~ 190) 116
9086 23:13:01.623179 iDelay=203, Bit 5, Center 144 (91 ~ 198) 108
9087 23:13:01.626398 iDelay=203, Bit 6, Center 146 (91 ~ 202) 112
9088 23:13:01.629585 iDelay=203, Bit 7, Center 130 (79 ~ 182) 104
9089 23:13:01.636766 iDelay=203, Bit 8, Center 112 (55 ~ 170) 116
9090 23:13:01.639694 iDelay=203, Bit 9, Center 116 (63 ~ 170) 108
9091 23:13:01.643083 iDelay=203, Bit 10, Center 126 (71 ~ 182) 112
9092 23:13:01.646052 iDelay=203, Bit 11, Center 116 (63 ~ 170) 108
9093 23:13:01.652987 iDelay=203, Bit 12, Center 136 (83 ~ 190) 108
9094 23:13:01.656572 iDelay=203, Bit 13, Center 134 (79 ~ 190) 112
9095 23:13:01.658873 iDelay=203, Bit 14, Center 134 (79 ~ 190) 112
9096 23:13:01.662412 iDelay=203, Bit 15, Center 138 (83 ~ 194) 112
9097 23:13:01.662502 ==
9098 23:13:01.665535 Dram Type= 6, Freq= 0, CH_1, rank 1
9099 23:13:01.672809 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9100 23:13:01.672913 ==
9101 23:13:01.672982 DQS Delay:
9102 23:13:01.675358 DQS0 = 0, DQS1 = 0
9103 23:13:01.675442 DQM Delay:
9104 23:13:01.675506 DQM0 = 134, DQM1 = 126
9105 23:13:01.678648 DQ Delay:
9106 23:13:01.682395 DQ0 =140, DQ1 =128, DQ2 =122, DQ3 =130
9107 23:13:01.685987 DQ4 =132, DQ5 =144, DQ6 =146, DQ7 =130
9108 23:13:01.689028 DQ8 =112, DQ9 =116, DQ10 =126, DQ11 =116
9109 23:13:01.691883 DQ12 =136, DQ13 =134, DQ14 =134, DQ15 =138
9110 23:13:01.691972
9111 23:13:01.692037
9112 23:13:01.692096
9113 23:13:01.695303 [DramC_TX_OE_Calibration] TA2
9114 23:13:01.699166 Original DQ_B0 (3 6) =30, OEN = 27
9115 23:13:01.702124 Original DQ_B1 (3 6) =30, OEN = 27
9116 23:13:01.705310 24, 0x0, End_B0=24 End_B1=24
9117 23:13:01.708511 25, 0x0, End_B0=25 End_B1=25
9118 23:13:01.708600 26, 0x0, End_B0=26 End_B1=26
9119 23:13:01.711645 27, 0x0, End_B0=27 End_B1=27
9120 23:13:01.715074 28, 0x0, End_B0=28 End_B1=28
9121 23:13:01.718021 29, 0x0, End_B0=29 End_B1=29
9122 23:13:01.721182 30, 0x0, End_B0=30 End_B1=30
9123 23:13:01.721271 31, 0x4545, End_B0=30 End_B1=30
9124 23:13:01.725617 Byte0 end_step=30 best_step=27
9125 23:13:01.728376 Byte1 end_step=30 best_step=27
9126 23:13:01.731698 Byte0 TX OE(2T, 0.5T) = (3, 3)
9127 23:13:01.734572 Byte1 TX OE(2T, 0.5T) = (3, 3)
9128 23:13:01.734658
9129 23:13:01.734722
9130 23:13:01.741399 [DQSOSCAuto] RK1, (LSB)MR18= 0xa07, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 404 ps
9131 23:13:01.744906 CH1 RK1: MR19=303, MR18=A07
9132 23:13:01.751280 CH1_RK1: MR19=0x303, MR18=0xA07, DQSOSC=404, MR23=63, INC=22, DEC=15
9133 23:13:01.754505 [RxdqsGatingPostProcess] freq 1600
9134 23:13:01.761098 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9135 23:13:01.761207 best DQS0 dly(2T, 0.5T) = (1, 1)
9136 23:13:01.764309 best DQS1 dly(2T, 0.5T) = (1, 1)
9137 23:13:01.767322 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9138 23:13:01.771352 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9139 23:13:01.774505 best DQS0 dly(2T, 0.5T) = (1, 1)
9140 23:13:01.777478 best DQS1 dly(2T, 0.5T) = (1, 1)
9141 23:13:01.780734 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9142 23:13:01.784305 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9143 23:13:01.788745 Pre-setting of DQS Precalculation
9144 23:13:01.791479 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9145 23:13:01.801476 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9146 23:13:01.807464 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9147 23:13:01.807571
9148 23:13:01.807636
9149 23:13:01.811345 [Calibration Summary] 3200 Mbps
9150 23:13:01.811431 CH 0, Rank 0
9151 23:13:01.814012 SW Impedance : PASS
9152 23:13:01.814096 DUTY Scan : NO K
9153 23:13:01.817624 ZQ Calibration : PASS
9154 23:13:01.820643 Jitter Meter : NO K
9155 23:13:01.820732 CBT Training : PASS
9156 23:13:01.823707 Write leveling : PASS
9157 23:13:01.827022 RX DQS gating : PASS
9158 23:13:01.827108 RX DQ/DQS(RDDQC) : PASS
9159 23:13:01.830568 TX DQ/DQS : PASS
9160 23:13:01.834126 RX DATLAT : PASS
9161 23:13:01.834213 RX DQ/DQS(Engine): PASS
9162 23:13:01.836822 TX OE : PASS
9163 23:13:01.836906 All Pass.
9164 23:13:01.836971
9165 23:13:01.840277 CH 0, Rank 1
9166 23:13:01.840361 SW Impedance : PASS
9167 23:13:01.843693 DUTY Scan : NO K
9168 23:13:01.846764 ZQ Calibration : PASS
9169 23:13:01.846850 Jitter Meter : NO K
9170 23:13:01.850602 CBT Training : PASS
9171 23:13:01.853642 Write leveling : PASS
9172 23:13:01.853737 RX DQS gating : PASS
9173 23:13:01.857259 RX DQ/DQS(RDDQC) : PASS
9174 23:13:01.860058 TX DQ/DQS : PASS
9175 23:13:01.860144 RX DATLAT : PASS
9176 23:13:01.863026 RX DQ/DQS(Engine): PASS
9177 23:13:01.863110 TX OE : PASS
9178 23:13:01.867132 All Pass.
9179 23:13:01.867218
9180 23:13:01.867296 CH 1, Rank 0
9181 23:13:01.869723 SW Impedance : PASS
9182 23:13:01.869806 DUTY Scan : NO K
9183 23:13:01.873498 ZQ Calibration : PASS
9184 23:13:01.876704 Jitter Meter : NO K
9185 23:13:01.876794 CBT Training : PASS
9186 23:13:01.880107 Write leveling : PASS
9187 23:13:01.883336 RX DQS gating : PASS
9188 23:13:01.883420 RX DQ/DQS(RDDQC) : PASS
9189 23:13:01.886498 TX DQ/DQS : PASS
9190 23:13:01.889683 RX DATLAT : PASS
9191 23:13:01.889776 RX DQ/DQS(Engine): PASS
9192 23:13:01.893279 TX OE : PASS
9193 23:13:01.893367 All Pass.
9194 23:13:01.893439
9195 23:13:01.896299 CH 1, Rank 1
9196 23:13:01.896383 SW Impedance : PASS
9197 23:13:01.899433 DUTY Scan : NO K
9198 23:13:01.902543 ZQ Calibration : PASS
9199 23:13:01.902633 Jitter Meter : NO K
9200 23:13:01.906539 CBT Training : PASS
9201 23:13:01.909944 Write leveling : PASS
9202 23:13:01.910028 RX DQS gating : PASS
9203 23:13:01.912938 RX DQ/DQS(RDDQC) : PASS
9204 23:13:01.916318 TX DQ/DQS : PASS
9205 23:13:01.916398 RX DATLAT : PASS
9206 23:13:01.919632 RX DQ/DQS(Engine): PASS
9207 23:13:01.922755 TX OE : PASS
9208 23:13:01.922862 All Pass.
9209 23:13:01.922991
9210 23:13:01.923080 DramC Write-DBI on
9211 23:13:01.925765 PER_BANK_REFRESH: Hybrid Mode
9212 23:13:01.929499 TX_TRACKING: ON
9213 23:13:01.935852 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9214 23:13:01.946249 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9215 23:13:01.953518 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9216 23:13:01.955566 [FAST_K] Save calibration result to emmc
9217 23:13:01.959657 sync common calibartion params.
9218 23:13:01.963617 sync cbt_mode0:1, 1:1
9219 23:13:01.963757 dram_init: ddr_geometry: 2
9220 23:13:01.965453 dram_init: ddr_geometry: 2
9221 23:13:01.969264 dram_init: ddr_geometry: 2
9222 23:13:01.969355 0:dram_rank_size:100000000
9223 23:13:01.972984 1:dram_rank_size:100000000
9224 23:13:01.978726 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9225 23:13:01.982007 DFS_SHUFFLE_HW_MODE: ON
9226 23:13:01.985432 dramc_set_vcore_voltage set vcore to 725000
9227 23:13:01.985525 Read voltage for 1600, 0
9228 23:13:01.989012 Vio18 = 0
9229 23:13:01.989097 Vcore = 725000
9230 23:13:01.989164 Vdram = 0
9231 23:13:01.992489 Vddq = 0
9232 23:13:01.992573 Vmddr = 0
9233 23:13:01.995208 switch to 3200 Mbps bootup
9234 23:13:01.995293 [DramcRunTimeConfig]
9235 23:13:01.995358 PHYPLL
9236 23:13:01.998927 DPM_CONTROL_AFTERK: ON
9237 23:13:02.002160 PER_BANK_REFRESH: ON
9238 23:13:02.005279 REFRESH_OVERHEAD_REDUCTION: ON
9239 23:13:02.005366 CMD_PICG_NEW_MODE: OFF
9240 23:13:02.008524 XRTWTW_NEW_MODE: ON
9241 23:13:02.008609 XRTRTR_NEW_MODE: ON
9242 23:13:02.011951 TX_TRACKING: ON
9243 23:13:02.012035 RDSEL_TRACKING: OFF
9244 23:13:02.015599 DQS Precalculation for DVFS: ON
9245 23:13:02.018698 RX_TRACKING: OFF
9246 23:13:02.018783 HW_GATING DBG: ON
9247 23:13:02.022147 ZQCS_ENABLE_LP4: ON
9248 23:13:02.022232 RX_PICG_NEW_MODE: ON
9249 23:13:02.024796 TX_PICG_NEW_MODE: ON
9250 23:13:02.024880 ENABLE_RX_DCM_DPHY: ON
9251 23:13:02.028268 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9252 23:13:02.031586 DUMMY_READ_FOR_TRACKING: OFF
9253 23:13:02.034971 !!! SPM_CONTROL_AFTERK: OFF
9254 23:13:02.038022 !!! SPM could not control APHY
9255 23:13:02.038112 IMPEDANCE_TRACKING: ON
9256 23:13:02.042039 TEMP_SENSOR: ON
9257 23:13:02.042129 HW_SAVE_FOR_SR: OFF
9258 23:13:02.044867 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9259 23:13:02.048060 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9260 23:13:02.052234 Read ODT Tracking: ON
9261 23:13:02.054830 Refresh Rate DeBounce: ON
9262 23:13:02.054917 DFS_NO_QUEUE_FLUSH: ON
9263 23:13:02.058290 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9264 23:13:02.061662 ENABLE_DFS_RUNTIME_MRW: OFF
9265 23:13:02.064945 DDR_RESERVE_NEW_MODE: ON
9266 23:13:02.065032 MR_CBT_SWITCH_FREQ: ON
9267 23:13:02.067897 =========================
9268 23:13:02.086568 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9269 23:13:02.089857 dram_init: ddr_geometry: 2
9270 23:13:02.108338 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9271 23:13:02.111541 dram_init: dram init end (result: 0)
9272 23:13:02.118181 DRAM-K: Full calibration passed in 24654 msecs
9273 23:13:02.122044 MRC: failed to locate region type 0.
9274 23:13:02.122142 DRAM rank0 size:0x100000000,
9275 23:13:02.124656 DRAM rank1 size=0x100000000
9276 23:13:02.134607 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9277 23:13:02.141905 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9278 23:13:02.148245 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9279 23:13:02.154707 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9280 23:13:02.157741 DRAM rank0 size:0x100000000,
9281 23:13:02.161534 DRAM rank1 size=0x100000000
9282 23:13:02.161626 CBMEM:
9283 23:13:02.164348 IMD: root @ 0xfffff000 254 entries.
9284 23:13:02.168758 IMD: root @ 0xffffec00 62 entries.
9285 23:13:02.171567 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9286 23:13:02.178125 WARNING: RO_VPD is uninitialized or empty.
9287 23:13:02.180834 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9288 23:13:02.189391 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9289 23:13:02.201216 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9290 23:13:02.212654 BS: romstage times (exec / console): total (unknown) / 24142 ms
9291 23:13:02.212799
9292 23:13:02.212866
9293 23:13:02.223160 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9294 23:13:02.227009 ARM64: Exception handlers installed.
9295 23:13:02.229082 ARM64: Testing exception
9296 23:13:02.232123 ARM64: Done test exception
9297 23:13:02.232209 Enumerating buses...
9298 23:13:02.236333 Show all devs... Before device enumeration.
9299 23:13:02.239196 Root Device: enabled 1
9300 23:13:02.242696 CPU_CLUSTER: 0: enabled 1
9301 23:13:02.242788 CPU: 00: enabled 1
9302 23:13:02.245336 Compare with tree...
9303 23:13:02.245420 Root Device: enabled 1
9304 23:13:02.248805 CPU_CLUSTER: 0: enabled 1
9305 23:13:02.252475 CPU: 00: enabled 1
9306 23:13:02.252558 Root Device scanning...
9307 23:13:02.255879 scan_static_bus for Root Device
9308 23:13:02.258569 CPU_CLUSTER: 0 enabled
9309 23:13:02.262019 scan_static_bus for Root Device done
9310 23:13:02.265419 scan_bus: bus Root Device finished in 8 msecs
9311 23:13:02.265508 done
9312 23:13:02.271775 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9313 23:13:02.275597 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9314 23:13:02.282185 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9315 23:13:02.288544 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9316 23:13:02.288657 Allocating resources...
9317 23:13:02.292138 Reading resources...
9318 23:13:02.294572 Root Device read_resources bus 0 link: 0
9319 23:13:02.298183 DRAM rank0 size:0x100000000,
9320 23:13:02.298273 DRAM rank1 size=0x100000000
9321 23:13:02.304649 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9322 23:13:02.304750 CPU: 00 missing read_resources
9323 23:13:02.311172 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9324 23:13:02.314318 Root Device read_resources bus 0 link: 0 done
9325 23:13:02.317464 Done reading resources.
9326 23:13:02.320881 Show resources in subtree (Root Device)...After reading.
9327 23:13:02.324394 Root Device child on link 0 CPU_CLUSTER: 0
9328 23:13:02.327479 CPU_CLUSTER: 0 child on link 0 CPU: 00
9329 23:13:02.337327 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9330 23:13:02.337458 CPU: 00
9331 23:13:02.344386 Root Device assign_resources, bus 0 link: 0
9332 23:13:02.347231 CPU_CLUSTER: 0 missing set_resources
9333 23:13:02.350950 Root Device assign_resources, bus 0 link: 0 done
9334 23:13:02.353799 Done setting resources.
9335 23:13:02.357681 Show resources in subtree (Root Device)...After assigning values.
9336 23:13:02.363720 Root Device child on link 0 CPU_CLUSTER: 0
9337 23:13:02.367112 CPU_CLUSTER: 0 child on link 0 CPU: 00
9338 23:13:02.373443 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9339 23:13:02.376814 CPU: 00
9340 23:13:02.376902 Done allocating resources.
9341 23:13:02.383552 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9342 23:13:02.386711 Enabling resources...
9343 23:13:02.386805 done.
9344 23:13:02.390370 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9345 23:13:02.393397 Initializing devices...
9346 23:13:02.393487 Root Device init
9347 23:13:02.396493 init hardware done!
9348 23:13:02.400002 0x00000018: ctrlr->caps
9349 23:13:02.400092 52.000 MHz: ctrlr->f_max
9350 23:13:02.403169 0.400 MHz: ctrlr->f_min
9351 23:13:02.406780 0x40ff8080: ctrlr->voltages
9352 23:13:02.406871 sclk: 390625
9353 23:13:02.406946 Bus Width = 1
9354 23:13:02.410188 sclk: 390625
9355 23:13:02.410273 Bus Width = 1
9356 23:13:02.413122 Early init status = 3
9357 23:13:02.416448 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9358 23:13:02.420767 in-header: 03 fc 00 00 01 00 00 00
9359 23:13:02.425539 in-data: 00
9360 23:13:02.427370 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9361 23:13:02.432963 in-header: 03 fd 00 00 00 00 00 00
9362 23:13:02.436285 in-data:
9363 23:13:02.439198 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9364 23:13:02.443064 in-header: 03 fc 00 00 01 00 00 00
9365 23:13:02.446441 in-data: 00
9366 23:13:02.449201 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9367 23:13:02.454374 in-header: 03 fd 00 00 00 00 00 00
9368 23:13:02.457124 in-data:
9369 23:13:02.460628 [SSUSB] Setting up USB HOST controller...
9370 23:13:02.463877 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9371 23:13:02.466924 [SSUSB] phy power-on done.
9372 23:13:02.470930 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9373 23:13:02.477212 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9374 23:13:02.480690 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9375 23:13:02.487540 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9376 23:13:02.493530 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
9377 23:13:02.500024 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9378 23:13:02.506714 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9379 23:13:02.513514 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9380 23:13:02.516315 SPM: binary array size = 0x9dc
9381 23:13:02.520430 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9382 23:13:02.526855 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9383 23:13:02.533730 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9384 23:13:02.539391 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9385 23:13:02.543483 configure_display: Starting display init
9386 23:13:02.577396 anx7625_power_on_init: Init interface.
9387 23:13:02.580517 anx7625_disable_pd_protocol: Disabled PD feature.
9388 23:13:02.584301 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9389 23:13:02.611707 anx7625_start_dp_work: Secure OCM version=00
9390 23:13:02.615419 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9391 23:13:02.630829 sp_tx_get_edid_block: EDID Block = 1
9392 23:13:02.732698 Extracted contents:
9393 23:13:02.735751 header: 00 ff ff ff ff ff ff 00
9394 23:13:02.738700 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9395 23:13:02.742540 version: 01 04
9396 23:13:02.745597 basic params: 95 1f 11 78 0a
9397 23:13:02.749294 chroma info: 76 90 94 55 54 90 27 21 50 54
9398 23:13:02.752380 established: 00 00 00
9399 23:13:02.758817 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9400 23:13:02.762047 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9401 23:13:02.768562 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9402 23:13:02.775907 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9403 23:13:02.782253 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9404 23:13:02.785542 extensions: 00
9405 23:13:02.785660 checksum: fb
9406 23:13:02.785738
9407 23:13:02.788154 Manufacturer: IVO Model 57d Serial Number 0
9408 23:13:02.791614 Made week 0 of 2020
9409 23:13:02.795576 EDID version: 1.4
9410 23:13:02.795701 Digital display
9411 23:13:02.798072 6 bits per primary color channel
9412 23:13:02.798161 DisplayPort interface
9413 23:13:02.801640 Maximum image size: 31 cm x 17 cm
9414 23:13:02.805199 Gamma: 220%
9415 23:13:02.805311 Check DPMS levels
9416 23:13:02.808127 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9417 23:13:02.814893 First detailed timing is preferred timing
9418 23:13:02.815044 Established timings supported:
9419 23:13:02.817987 Standard timings supported:
9420 23:13:02.821475 Detailed timings
9421 23:13:02.825330 Hex of detail: 383680a07038204018303c0035ae10000019
9422 23:13:02.832441 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9423 23:13:02.834705 0780 0798 07c8 0820 hborder 0
9424 23:13:02.838127 0438 043b 0447 0458 vborder 0
9425 23:13:02.841295 -hsync -vsync
9426 23:13:02.841396 Did detailed timing
9427 23:13:02.848528 Hex of detail: 000000000000000000000000000000000000
9428 23:13:02.850917 Manufacturer-specified data, tag 0
9429 23:13:02.854218 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9430 23:13:02.857560 ASCII string: InfoVision
9431 23:13:02.860954 Hex of detail: 000000fe00523134304e574635205248200a
9432 23:13:02.864237 ASCII string: R140NWF5 RH
9433 23:13:02.864334 Checksum
9434 23:13:02.867507 Checksum: 0xfb (valid)
9435 23:13:02.871260 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9436 23:13:02.875140 DSI data_rate: 832800000 bps
9437 23:13:02.880985 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9438 23:13:02.883908 anx7625_parse_edid: pixelclock(138800).
9439 23:13:02.887621 hactive(1920), hsync(48), hfp(24), hbp(88)
9440 23:13:02.891502 vactive(1080), vsync(12), vfp(3), vbp(17)
9441 23:13:02.894339 anx7625_dsi_config: config dsi.
9442 23:13:02.900968 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9443 23:13:02.914563 anx7625_dsi_config: success to config DSI
9444 23:13:02.917517 anx7625_dp_start: MIPI phy setup OK.
9445 23:13:02.921600 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9446 23:13:02.924302 mtk_ddp_mode_set invalid vrefresh 60
9447 23:13:02.927703 main_disp_path_setup
9448 23:13:02.927818 ovl_layer_smi_id_en
9449 23:13:02.930640 ovl_layer_smi_id_en
9450 23:13:02.930727 ccorr_config
9451 23:13:02.930792 aal_config
9452 23:13:02.934472 gamma_config
9453 23:13:02.934560 postmask_config
9454 23:13:02.937141 dither_config
9455 23:13:02.940788 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9456 23:13:02.947252 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9457 23:13:02.950570 Root Device init finished in 553 msecs
9458 23:13:02.953890 CPU_CLUSTER: 0 init
9459 23:13:02.960147 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9460 23:13:02.967719 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9461 23:13:02.967878 APU_MBOX 0x190000b0 = 0x10001
9462 23:13:02.970506 APU_MBOX 0x190001b0 = 0x10001
9463 23:13:02.973641 APU_MBOX 0x190005b0 = 0x10001
9464 23:13:02.977119 APU_MBOX 0x190006b0 = 0x10001
9465 23:13:02.983957 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9466 23:13:02.993546 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9467 23:13:03.006062 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9468 23:13:03.012126 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9469 23:13:03.023652 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9470 23:13:03.033608 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9471 23:13:03.036525 CPU_CLUSTER: 0 init finished in 81 msecs
9472 23:13:03.040521 Devices initialized
9473 23:13:03.043653 Show all devs... After init.
9474 23:13:03.043772 Root Device: enabled 1
9475 23:13:03.046289 CPU_CLUSTER: 0: enabled 1
9476 23:13:03.049332 CPU: 00: enabled 1
9477 23:13:03.052604 BS: BS_DEV_INIT run times (exec / console): 211 / 447 ms
9478 23:13:03.056692 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9479 23:13:03.059682 ELOG: NV offset 0x57f000 size 0x1000
9480 23:13:03.066075 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9481 23:13:03.072628 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9482 23:13:03.076030 ELOG: Event(17) added with size 13 at 2023-12-27 23:13:03 UTC
9483 23:13:03.083483 out: cmd=0x121: 03 db 21 01 00 00 00 00
9484 23:13:03.087076 in-header: 03 a7 00 00 2c 00 00 00
9485 23:13:03.096888 in-data: b8 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9486 23:13:03.102478 ELOG: Event(A1) added with size 10 at 2023-12-27 23:13:03 UTC
9487 23:13:03.110167 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9488 23:13:03.115588 ELOG: Event(A0) added with size 9 at 2023-12-27 23:13:03 UTC
9489 23:13:03.118987 elog_add_boot_reason: Logged dev mode boot
9490 23:13:03.125861 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9491 23:13:03.125986 Finalize devices...
9492 23:13:03.129109 Devices finalized
9493 23:13:03.132323 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9494 23:13:03.136279 Writing coreboot table at 0xffe64000
9495 23:13:03.138861 0. 000000000010a000-0000000000113fff: RAMSTAGE
9496 23:13:03.142362 1. 0000000040000000-00000000400fffff: RAM
9497 23:13:03.148729 2. 0000000040100000-000000004032afff: RAMSTAGE
9498 23:13:03.152139 3. 000000004032b000-00000000545fffff: RAM
9499 23:13:03.155829 4. 0000000054600000-000000005465ffff: BL31
9500 23:13:03.158746 5. 0000000054660000-00000000ffe63fff: RAM
9501 23:13:03.165623 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9502 23:13:03.169278 7. 0000000100000000-000000023fffffff: RAM
9503 23:13:03.172245 Passing 5 GPIOs to payload:
9504 23:13:03.175645 NAME | PORT | POLARITY | VALUE
9505 23:13:03.181795 EC in RW | 0x000000aa | low | undefined
9506 23:13:03.185371 EC interrupt | 0x00000005 | low | undefined
9507 23:13:03.188186 TPM interrupt | 0x000000ab | high | undefined
9508 23:13:03.195133 SD card detect | 0x00000011 | high | undefined
9509 23:13:03.198354 speaker enable | 0x00000093 | high | undefined
9510 23:13:03.202154 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9511 23:13:03.205216 in-header: 03 f9 00 00 02 00 00 00
9512 23:13:03.207915 in-data: 02 00
9513 23:13:03.211956 ADC[4]: Raw value=901552 ID=7
9514 23:13:03.212060 ADC[3]: Raw value=213282 ID=1
9515 23:13:03.214888 RAM Code: 0x71
9516 23:13:03.218257 ADC[6]: Raw value=75036 ID=0
9517 23:13:03.218350 ADC[5]: Raw value=212912 ID=1
9518 23:13:03.221385 SKU Code: 0x1
9519 23:13:03.228171 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum a1a9
9520 23:13:03.228289 coreboot table: 964 bytes.
9521 23:13:03.231608 IMD ROOT 0. 0xfffff000 0x00001000
9522 23:13:03.235506 IMD SMALL 1. 0xffffe000 0x00001000
9523 23:13:03.237932 RO MCACHE 2. 0xffffc000 0x00001104
9524 23:13:03.241210 CONSOLE 3. 0xfff7c000 0x00080000
9525 23:13:03.244441 FMAP 4. 0xfff7b000 0x00000452
9526 23:13:03.248235 TIME STAMP 5. 0xfff7a000 0x00000910
9527 23:13:03.251074 VBOOT WORK 6. 0xfff66000 0x00014000
9528 23:13:03.254346 RAMOOPS 7. 0xffe66000 0x00100000
9529 23:13:03.257642 COREBOOT 8. 0xffe64000 0x00002000
9530 23:13:03.261245 IMD small region:
9531 23:13:03.264660 IMD ROOT 0. 0xffffec00 0x00000400
9532 23:13:03.267418 VPD 1. 0xffffeb80 0x0000006c
9533 23:13:03.271293 MMC STATUS 2. 0xffffeb60 0x00000004
9534 23:13:03.274625 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9535 23:13:03.277877 Probing TPM: done!
9536 23:13:03.281668 Connected to device vid:did:rid of 1ae0:0028:00
9537 23:13:03.291957 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9538 23:13:03.295421 Initialized TPM device CR50 revision 0
9539 23:13:03.298497 Checking cr50 for pending updates
9540 23:13:03.302638 Reading cr50 TPM mode
9541 23:13:03.311432 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9542 23:13:03.318658 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9543 23:13:03.357821 read SPI 0x3990ec 0x4f1b0: 34847 us, 9298 KB/s, 74.384 Mbps
9544 23:13:03.361139 Checking segment from ROM address 0x40100000
9545 23:13:03.365324 Checking segment from ROM address 0x4010001c
9546 23:13:03.371318 Loading segment from ROM address 0x40100000
9547 23:13:03.371462 code (compression=0)
9548 23:13:03.381328 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9549 23:13:03.388104 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9550 23:13:03.388233 it's not compressed!
9551 23:13:03.394549 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9552 23:13:03.401110 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9553 23:13:03.418552 Loading segment from ROM address 0x4010001c
9554 23:13:03.418700 Entry Point 0x80000000
9555 23:13:03.422132 Loaded segments
9556 23:13:03.425061 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9557 23:13:03.432392 Jumping to boot code at 0x80000000(0xffe64000)
9558 23:13:03.438416 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9559 23:13:03.444909 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9560 23:13:03.452900 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9561 23:13:03.456867 Checking segment from ROM address 0x40100000
9562 23:13:03.459359 Checking segment from ROM address 0x4010001c
9563 23:13:03.466108 Loading segment from ROM address 0x40100000
9564 23:13:03.466234 code (compression=1)
9565 23:13:03.473397 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9566 23:13:03.483124 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9567 23:13:03.483273 using LZMA
9568 23:13:03.491560 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9569 23:13:03.497978 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9570 23:13:03.501032 Loading segment from ROM address 0x4010001c
9571 23:13:03.501129 Entry Point 0x54601000
9572 23:13:03.504552 Loaded segments
9573 23:13:03.507928 NOTICE: MT8192 bl31_setup
9574 23:13:03.514830 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9575 23:13:03.519128 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9576 23:13:03.521656 WARNING: region 0:
9577 23:13:03.524995 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9578 23:13:03.525095 WARNING: region 1:
9579 23:13:03.532003 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9580 23:13:03.535024 WARNING: region 2:
9581 23:13:03.538761 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9582 23:13:03.541912 WARNING: region 3:
9583 23:13:03.545473 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9584 23:13:03.548985 WARNING: region 4:
9585 23:13:03.555279 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9586 23:13:03.555382 WARNING: region 5:
9587 23:13:03.558313 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9588 23:13:03.561908 WARNING: region 6:
9589 23:13:03.565004 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9590 23:13:03.567878 WARNING: region 7:
9591 23:13:03.571421 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9592 23:13:03.578494 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9593 23:13:03.581150 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9594 23:13:03.584349 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9595 23:13:03.591221 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9596 23:13:03.594877 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9597 23:13:03.598132 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9598 23:13:03.604525 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9599 23:13:03.607874 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9600 23:13:03.614530 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9601 23:13:03.617518 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9602 23:13:03.621309 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9603 23:13:03.627551 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9604 23:13:03.630754 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9605 23:13:03.637899 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9606 23:13:03.641190 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9607 23:13:03.644504 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9608 23:13:03.651528 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9609 23:13:03.654277 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9610 23:13:03.657599 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9611 23:13:03.663991 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9612 23:13:03.667366 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9613 23:13:03.674116 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9614 23:13:03.677072 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9615 23:13:03.680568 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9616 23:13:03.687957 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9617 23:13:03.690657 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9618 23:13:03.697566 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9619 23:13:03.700316 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9620 23:13:03.704148 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9621 23:13:03.710223 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9622 23:13:03.714169 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9623 23:13:03.721317 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9624 23:13:03.724027 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9625 23:13:03.727318 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9626 23:13:03.730375 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9627 23:13:03.737033 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9628 23:13:03.740641 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9629 23:13:03.743349 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9630 23:13:03.746849 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9631 23:13:03.753543 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9632 23:13:03.756955 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9633 23:13:03.760288 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9634 23:13:03.764182 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9635 23:13:03.770289 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9636 23:13:03.773433 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9637 23:13:03.776661 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9638 23:13:03.780054 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9639 23:13:03.787606 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9640 23:13:03.790117 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9641 23:13:03.797383 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9642 23:13:03.800165 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9643 23:13:03.803313 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9644 23:13:03.809821 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9645 23:13:03.813132 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9646 23:13:03.819876 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9647 23:13:03.823151 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9648 23:13:03.829852 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9649 23:13:03.832973 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9650 23:13:03.839527 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9651 23:13:03.842818 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9652 23:13:03.846197 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9653 23:13:03.853206 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9654 23:13:03.856358 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9655 23:13:03.862823 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9656 23:13:03.866451 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9657 23:13:03.873211 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9658 23:13:03.875753 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9659 23:13:03.882494 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9660 23:13:03.886251 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9661 23:13:03.889922 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9662 23:13:03.896098 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9663 23:13:03.899262 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9664 23:13:03.906270 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9665 23:13:03.908750 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9666 23:13:03.915968 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9667 23:13:03.919260 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9668 23:13:03.925620 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9669 23:13:03.929015 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9670 23:13:03.932127 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9671 23:13:03.939532 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9672 23:13:03.942202 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9673 23:13:03.948598 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9674 23:13:03.951878 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9675 23:13:03.958699 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9676 23:13:03.961698 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9677 23:13:03.968540 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9678 23:13:03.972239 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9679 23:13:03.975121 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9680 23:13:03.981635 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9681 23:13:03.985070 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9682 23:13:03.991582 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9683 23:13:03.994792 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9684 23:13:04.001643 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9685 23:13:04.004622 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9686 23:13:04.011630 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9687 23:13:04.014864 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9688 23:13:04.018422 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9689 23:13:04.024509 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9690 23:13:04.029228 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9691 23:13:04.032388 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9692 23:13:04.034975 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9693 23:13:04.040895 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9694 23:13:04.044394 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9695 23:13:04.051248 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9696 23:13:04.054447 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9697 23:13:04.057811 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9698 23:13:04.064513 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9699 23:13:04.067766 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9700 23:13:04.074010 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9701 23:13:04.077315 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9702 23:13:04.081855 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9703 23:13:04.088052 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9704 23:13:04.090879 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9705 23:13:04.097651 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9706 23:13:04.100565 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9707 23:13:04.104209 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9708 23:13:04.110893 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9709 23:13:04.113884 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9710 23:13:04.117573 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9711 23:13:04.124114 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9712 23:13:04.127247 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9713 23:13:04.130704 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9714 23:13:04.133762 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9715 23:13:04.140598 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9716 23:13:04.144459 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9717 23:13:04.146849 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9718 23:13:04.153670 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9719 23:13:04.157378 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9720 23:13:04.163565 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9721 23:13:04.166932 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9722 23:13:04.170092 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9723 23:13:04.177565 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9724 23:13:04.180362 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9725 23:13:04.186817 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9726 23:13:04.191331 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9727 23:13:04.193620 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9728 23:13:04.200495 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9729 23:13:04.204054 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9730 23:13:04.207791 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9731 23:13:04.213328 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9732 23:13:04.216564 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9733 23:13:04.223622 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9734 23:13:04.226683 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9735 23:13:04.229735 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9736 23:13:04.236961 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9737 23:13:04.240313 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9738 23:13:04.246763 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9739 23:13:04.250306 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9740 23:13:04.252796 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9741 23:13:04.259475 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9742 23:13:04.262954 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9743 23:13:04.269933 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9744 23:13:04.273110 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9745 23:13:04.276594 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9746 23:13:04.283287 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9747 23:13:04.286501 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9748 23:13:04.292465 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9749 23:13:04.296202 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9750 23:13:04.299637 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9751 23:13:04.306038 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9752 23:13:04.309364 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9753 23:13:04.315794 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9754 23:13:04.319238 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9755 23:13:04.323068 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9756 23:13:04.330046 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9757 23:13:04.332469 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9758 23:13:04.339886 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9759 23:13:04.342376 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9760 23:13:04.345735 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9761 23:13:04.353196 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9762 23:13:04.355629 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9763 23:13:04.361994 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9764 23:13:04.365456 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9765 23:13:04.369044 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9766 23:13:04.375172 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9767 23:13:04.379015 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9768 23:13:04.385127 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9769 23:13:04.388642 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9770 23:13:04.391779 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9771 23:13:04.398567 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9772 23:13:04.402140 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9773 23:13:04.405531 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9774 23:13:04.411894 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9775 23:13:04.415520 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9776 23:13:04.421451 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9777 23:13:04.424659 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9778 23:13:04.432243 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9779 23:13:04.434628 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9780 23:13:04.438203 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9781 23:13:04.445225 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9782 23:13:04.447952 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9783 23:13:04.454661 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9784 23:13:04.458517 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9785 23:13:04.461942 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9786 23:13:04.467586 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9787 23:13:04.471364 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9788 23:13:04.477521 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9789 23:13:04.481121 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9790 23:13:04.487203 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9791 23:13:04.490563 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9792 23:13:04.494034 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9793 23:13:04.500342 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9794 23:13:04.503596 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9795 23:13:04.510377 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9796 23:13:04.514041 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9797 23:13:04.520330 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9798 23:13:04.523862 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9799 23:13:04.526936 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9800 23:13:04.533517 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9801 23:13:04.536647 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9802 23:13:04.543341 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9803 23:13:04.547066 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9804 23:13:04.553374 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9805 23:13:04.556856 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9806 23:13:04.560314 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9807 23:13:04.566475 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9808 23:13:04.569928 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9809 23:13:04.576442 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9810 23:13:04.579733 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9811 23:13:04.586737 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9812 23:13:04.590076 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9813 23:13:04.593456 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9814 23:13:04.600473 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9815 23:13:04.603081 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9816 23:13:04.609392 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9817 23:13:04.612877 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9818 23:13:04.619104 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9819 23:13:04.622892 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9820 23:13:04.626063 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9821 23:13:04.632382 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9822 23:13:04.635418 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9823 23:13:04.639435 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9824 23:13:04.642708 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9825 23:13:04.648898 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9826 23:13:04.652477 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9827 23:13:04.655761 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9828 23:13:04.661953 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9829 23:13:04.665225 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9830 23:13:04.669091 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9831 23:13:04.675439 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9832 23:13:04.678177 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9833 23:13:04.684979 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9834 23:13:04.689642 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9835 23:13:04.691779 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9836 23:13:04.698467 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9837 23:13:04.702070 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9838 23:13:04.708215 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9839 23:13:04.711973 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9840 23:13:04.714853 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9841 23:13:04.721014 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9842 23:13:04.724261 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9843 23:13:04.731803 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9844 23:13:04.734677 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9845 23:13:04.737829 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9846 23:13:04.744282 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9847 23:13:04.747581 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9848 23:13:04.751340 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9849 23:13:04.757483 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9850 23:13:04.760422 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9851 23:13:04.763974 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9852 23:13:04.770555 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9853 23:13:04.773600 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9854 23:13:04.780478 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9855 23:13:04.783808 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9856 23:13:04.787833 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9857 23:13:04.793967 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9858 23:13:04.797247 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9859 23:13:04.803229 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9860 23:13:04.806831 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9861 23:13:04.809959 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9862 23:13:04.813483 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9863 23:13:04.819752 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9864 23:13:04.823030 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9865 23:13:04.826611 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9866 23:13:04.829881 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9867 23:13:04.836609 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9868 23:13:04.839548 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9869 23:13:04.843776 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9870 23:13:04.846722 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9871 23:13:04.853044 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9872 23:13:04.856609 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9873 23:13:04.859515 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9874 23:13:04.865880 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9875 23:13:04.869446 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9876 23:13:04.872958 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9877 23:13:04.879125 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9878 23:13:04.882884 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9879 23:13:04.889015 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9880 23:13:04.892368 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9881 23:13:04.895886 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9882 23:13:04.902431 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9883 23:13:04.905729 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9884 23:13:04.913238 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9885 23:13:04.915746 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9886 23:13:04.923308 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9887 23:13:04.926064 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9888 23:13:04.928939 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9889 23:13:04.936112 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9890 23:13:04.939457 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9891 23:13:04.946821 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9892 23:13:04.949778 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9893 23:13:04.952417 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9894 23:13:04.959210 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9895 23:13:04.963449 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9896 23:13:04.969298 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9897 23:13:04.972887 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9898 23:13:04.975381 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9899 23:13:04.982157 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9900 23:13:04.985418 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9901 23:13:04.991842 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9902 23:13:04.995005 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9903 23:13:05.001847 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9904 23:13:05.005482 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9905 23:13:05.008961 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9906 23:13:05.015616 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9907 23:13:05.018330 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9908 23:13:05.024641 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9909 23:13:05.028633 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9910 23:13:05.035347 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9911 23:13:05.038017 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9912 23:13:05.041297 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9913 23:13:05.048207 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9914 23:13:05.051429 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9915 23:13:05.057665 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9916 23:13:05.061522 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9917 23:13:05.064835 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9918 23:13:05.071155 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9919 23:13:05.074783 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9920 23:13:05.080946 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9921 23:13:05.084342 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9922 23:13:05.087786 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9923 23:13:05.095209 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9924 23:13:05.097838 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9925 23:13:05.104197 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9926 23:13:05.107884 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9927 23:13:05.114221 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9928 23:13:05.117456 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9929 23:13:05.120405 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9930 23:13:05.127200 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9931 23:13:05.130142 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9932 23:13:05.136980 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9933 23:13:05.140643 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9934 23:13:05.147054 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9935 23:13:05.150451 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9936 23:13:05.153573 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9937 23:13:05.160939 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9938 23:13:05.164187 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9939 23:13:05.169917 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9940 23:13:05.173118 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9941 23:13:05.176631 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9942 23:13:05.182985 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9943 23:13:05.186797 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9944 23:13:05.193176 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9945 23:13:05.196542 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9946 23:13:05.203856 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9947 23:13:05.206442 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9948 23:13:05.209796 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9949 23:13:05.216776 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9950 23:13:05.219597 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9951 23:13:05.228352 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9952 23:13:05.229157 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9953 23:13:05.235726 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9954 23:13:05.239041 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9955 23:13:05.245483 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9956 23:13:05.248951 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9957 23:13:05.252141 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9958 23:13:05.258823 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9959 23:13:05.261963 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9960 23:13:05.268821 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9961 23:13:05.272000 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9962 23:13:05.279453 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9963 23:13:05.282888 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9964 23:13:05.288378 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9965 23:13:05.292310 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9966 23:13:05.298647 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9967 23:13:05.301800 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9968 23:13:05.304778 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9969 23:13:05.312051 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9970 23:13:05.314650 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9971 23:13:05.321466 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9972 23:13:05.324939 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9973 23:13:05.332383 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9974 23:13:05.334739 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9975 23:13:05.341186 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9976 23:13:05.344479 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9977 23:13:05.347522 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9978 23:13:05.354255 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9979 23:13:05.357734 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9980 23:13:05.364496 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9981 23:13:05.367553 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9982 23:13:05.374210 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9983 23:13:05.377245 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9984 23:13:05.383990 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9985 23:13:05.387195 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9986 23:13:05.391677 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9987 23:13:05.397443 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9988 23:13:05.401255 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9989 23:13:05.407383 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9990 23:13:05.410680 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9991 23:13:05.417287 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9992 23:13:05.420703 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9993 23:13:05.424289 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9994 23:13:05.430697 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9995 23:13:05.433832 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9996 23:13:05.440265 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9997 23:13:05.443985 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9998 23:13:05.450553 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9999 23:13:05.453754 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
10000 23:13:05.460489 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
10001 23:13:05.463537 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
10002 23:13:05.470035 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
10003 23:13:05.473875 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
10004 23:13:05.480131 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
10005 23:13:05.483602 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
10006 23:13:05.486688 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
10007 23:13:05.493244 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
10008 23:13:05.496775 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
10009 23:13:05.503450 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
10010 23:13:05.506618 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
10011 23:13:05.513009 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
10012 23:13:05.516566 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
10013 23:13:05.522772 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
10014 23:13:05.526409 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
10015 23:13:05.533096 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
10016 23:13:05.536193 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
10017 23:13:05.543031 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
10018 23:13:05.546217 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
10019 23:13:05.553102 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
10020 23:13:05.557229 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
10021 23:13:05.562698 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
10022 23:13:05.566205 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
10023 23:13:05.572527 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
10024 23:13:05.579234 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
10025 23:13:05.583300 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
10026 23:13:05.585689 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
10027 23:13:05.589291 INFO: [APUAPC] vio 0
10028 23:13:05.592461 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
10029 23:13:05.599239 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
10030 23:13:05.602405 INFO: [APUAPC] D0_APC_0: 0x400510
10031 23:13:05.605819 INFO: [APUAPC] D0_APC_1: 0x0
10032 23:13:05.609353 INFO: [APUAPC] D0_APC_2: 0x1540
10033 23:13:05.609435 INFO: [APUAPC] D0_APC_3: 0x0
10034 23:13:05.615967 INFO: [APUAPC] D1_APC_0: 0xffffffff
10035 23:13:05.619497 INFO: [APUAPC] D1_APC_1: 0xffffffff
10036 23:13:05.621884 INFO: [APUAPC] D1_APC_2: 0x3fffff
10037 23:13:05.621966 INFO: [APUAPC] D1_APC_3: 0x0
10038 23:13:05.625261 INFO: [APUAPC] D2_APC_0: 0xffffffff
10039 23:13:05.629764 INFO: [APUAPC] D2_APC_1: 0xffffffff
10040 23:13:05.632421 INFO: [APUAPC] D2_APC_2: 0x3fffff
10041 23:13:05.635130 INFO: [APUAPC] D2_APC_3: 0x0
10042 23:13:05.638909 INFO: [APUAPC] D3_APC_0: 0xffffffff
10043 23:13:05.642303 INFO: [APUAPC] D3_APC_1: 0xffffffff
10044 23:13:05.645054 INFO: [APUAPC] D3_APC_2: 0x3fffff
10045 23:13:05.648274 INFO: [APUAPC] D3_APC_3: 0x0
10046 23:13:05.652159 INFO: [APUAPC] D4_APC_0: 0xffffffff
10047 23:13:05.655156 INFO: [APUAPC] D4_APC_1: 0xffffffff
10048 23:13:05.659116 INFO: [APUAPC] D4_APC_2: 0x3fffff
10049 23:13:05.662150 INFO: [APUAPC] D4_APC_3: 0x0
10050 23:13:05.665283 INFO: [APUAPC] D5_APC_0: 0xffffffff
10051 23:13:05.668606 INFO: [APUAPC] D5_APC_1: 0xffffffff
10052 23:13:05.671865 INFO: [APUAPC] D5_APC_2: 0x3fffff
10053 23:13:05.675119 INFO: [APUAPC] D5_APC_3: 0x0
10054 23:13:05.678068 INFO: [APUAPC] D6_APC_0: 0xffffffff
10055 23:13:05.681680 INFO: [APUAPC] D6_APC_1: 0xffffffff
10056 23:13:05.684643 INFO: [APUAPC] D6_APC_2: 0x3fffff
10057 23:13:05.687828 INFO: [APUAPC] D6_APC_3: 0x0
10058 23:13:05.691290 INFO: [APUAPC] D7_APC_0: 0xffffffff
10059 23:13:05.694581 INFO: [APUAPC] D7_APC_1: 0xffffffff
10060 23:13:05.697868 INFO: [APUAPC] D7_APC_2: 0x3fffff
10061 23:13:05.701748 INFO: [APUAPC] D7_APC_3: 0x0
10062 23:13:05.704374 INFO: [APUAPC] D8_APC_0: 0xffffffff
10063 23:13:05.708016 INFO: [APUAPC] D8_APC_1: 0xffffffff
10064 23:13:05.711062 INFO: [APUAPC] D8_APC_2: 0x3fffff
10065 23:13:05.714865 INFO: [APUAPC] D8_APC_3: 0x0
10066 23:13:05.717906 INFO: [APUAPC] D9_APC_0: 0xffffffff
10067 23:13:05.721012 INFO: [APUAPC] D9_APC_1: 0xffffffff
10068 23:13:05.724548 INFO: [APUAPC] D9_APC_2: 0x3fffff
10069 23:13:05.728274 INFO: [APUAPC] D9_APC_3: 0x0
10070 23:13:05.730972 INFO: [APUAPC] D10_APC_0: 0xffffffff
10071 23:13:05.734038 INFO: [APUAPC] D10_APC_1: 0xffffffff
10072 23:13:05.737282 INFO: [APUAPC] D10_APC_2: 0x3fffff
10073 23:13:05.740759 INFO: [APUAPC] D10_APC_3: 0x0
10074 23:13:05.744145 INFO: [APUAPC] D11_APC_0: 0xffffffff
10075 23:13:05.747532 INFO: [APUAPC] D11_APC_1: 0xffffffff
10076 23:13:05.750692 INFO: [APUAPC] D11_APC_2: 0x3fffff
10077 23:13:05.753948 INFO: [APUAPC] D11_APC_3: 0x0
10078 23:13:05.758188 INFO: [APUAPC] D12_APC_0: 0xffffffff
10079 23:13:05.761167 INFO: [APUAPC] D12_APC_1: 0xffffffff
10080 23:13:05.764436 INFO: [APUAPC] D12_APC_2: 0x3fffff
10081 23:13:05.768354 INFO: [APUAPC] D12_APC_3: 0x0
10082 23:13:05.771180 INFO: [APUAPC] D13_APC_0: 0xffffffff
10083 23:13:05.774416 INFO: [APUAPC] D13_APC_1: 0xffffffff
10084 23:13:05.777224 INFO: [APUAPC] D13_APC_2: 0x3fffff
10085 23:13:05.780494 INFO: [APUAPC] D13_APC_3: 0x0
10086 23:13:05.783907 INFO: [APUAPC] D14_APC_0: 0xffffffff
10087 23:13:05.787231 INFO: [APUAPC] D14_APC_1: 0xffffffff
10088 23:13:05.790452 INFO: [APUAPC] D14_APC_2: 0x3fffff
10089 23:13:05.793529 INFO: [APUAPC] D14_APC_3: 0x0
10090 23:13:05.796967 INFO: [APUAPC] D15_APC_0: 0xffffffff
10091 23:13:05.800497 INFO: [APUAPC] D15_APC_1: 0xffffffff
10092 23:13:05.803706 INFO: [APUAPC] D15_APC_2: 0x3fffff
10093 23:13:05.807569 INFO: [APUAPC] D15_APC_3: 0x0
10094 23:13:05.810289 INFO: [APUAPC] APC_CON: 0x4
10095 23:13:05.814111 INFO: [NOCDAPC] D0_APC_0: 0x0
10096 23:13:05.816864 INFO: [NOCDAPC] D0_APC_1: 0x0
10097 23:13:05.819950 INFO: [NOCDAPC] D1_APC_0: 0x0
10098 23:13:05.823602 INFO: [NOCDAPC] D1_APC_1: 0xfff
10099 23:13:05.826447 INFO: [NOCDAPC] D2_APC_0: 0x0
10100 23:13:05.829768 INFO: [NOCDAPC] D2_APC_1: 0xfff
10101 23:13:05.829852 INFO: [NOCDAPC] D3_APC_0: 0x0
10102 23:13:05.833285 INFO: [NOCDAPC] D3_APC_1: 0xfff
10103 23:13:05.836838 INFO: [NOCDAPC] D4_APC_0: 0x0
10104 23:13:05.840822 INFO: [NOCDAPC] D4_APC_1: 0xfff
10105 23:13:05.843961 INFO: [NOCDAPC] D5_APC_0: 0x0
10106 23:13:05.847055 INFO: [NOCDAPC] D5_APC_1: 0xfff
10107 23:13:05.850034 INFO: [NOCDAPC] D6_APC_0: 0x0
10108 23:13:05.853479 INFO: [NOCDAPC] D6_APC_1: 0xfff
10109 23:13:05.856527 INFO: [NOCDAPC] D7_APC_0: 0x0
10110 23:13:05.860029 INFO: [NOCDAPC] D7_APC_1: 0xfff
10111 23:13:05.863031 INFO: [NOCDAPC] D8_APC_0: 0x0
10112 23:13:05.866953 INFO: [NOCDAPC] D8_APC_1: 0xfff
10113 23:13:05.867036 INFO: [NOCDAPC] D9_APC_0: 0x0
10114 23:13:05.869676 INFO: [NOCDAPC] D9_APC_1: 0xfff
10115 23:13:05.874366 INFO: [NOCDAPC] D10_APC_0: 0x0
10116 23:13:05.875983 INFO: [NOCDAPC] D10_APC_1: 0xfff
10117 23:13:05.879202 INFO: [NOCDAPC] D11_APC_0: 0x0
10118 23:13:05.882702 INFO: [NOCDAPC] D11_APC_1: 0xfff
10119 23:13:05.885947 INFO: [NOCDAPC] D12_APC_0: 0x0
10120 23:13:05.889330 INFO: [NOCDAPC] D12_APC_1: 0xfff
10121 23:13:05.893042 INFO: [NOCDAPC] D13_APC_0: 0x0
10122 23:13:05.895997 INFO: [NOCDAPC] D13_APC_1: 0xfff
10123 23:13:05.898876 INFO: [NOCDAPC] D14_APC_0: 0x0
10124 23:13:05.902451 INFO: [NOCDAPC] D14_APC_1: 0xfff
10125 23:13:05.906236 INFO: [NOCDAPC] D15_APC_0: 0x0
10126 23:13:05.908968 INFO: [NOCDAPC] D15_APC_1: 0xfff
10127 23:13:05.912154 INFO: [NOCDAPC] APC_CON: 0x4
10128 23:13:05.916208 INFO: [APUAPC] set_apusys_apc done
10129 23:13:05.916292 INFO: [DEVAPC] devapc_init done
10130 23:13:05.922039 INFO: GICv3 without legacy support detected.
10131 23:13:05.925395 INFO: ARM GICv3 driver initialized in EL3
10132 23:13:05.929456 INFO: Maximum SPI INTID supported: 639
10133 23:13:05.931913 INFO: BL31: Initializing runtime services
10134 23:13:05.938848 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10135 23:13:05.942271 INFO: SPM: enable CPC mode
10136 23:13:05.945834 INFO: mcdi ready for mcusys-off-idle and system suspend
10137 23:13:05.952035 INFO: BL31: Preparing for EL3 exit to normal world
10138 23:13:05.955951 INFO: Entry point address = 0x80000000
10139 23:13:05.958458 INFO: SPSR = 0x8
10140 23:13:05.962703
10141 23:13:05.962785
10142 23:13:05.962849
10143 23:13:05.966332 Starting depthcharge on Spherion...
10144 23:13:05.966414
10145 23:13:05.966478 Wipe memory regions:
10146 23:13:05.966538
10147 23:13:05.967226 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10148 23:13:05.967326 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10149 23:13:05.967411 Setting prompt string to ['asurada:']
10150 23:13:05.967490 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10151 23:13:05.969251 [0x00000040000000, 0x00000054600000)
10152 23:13:06.091643
10153 23:13:06.091839 [0x00000054660000, 0x00000080000000)
10154 23:13:06.352260
10155 23:13:06.352418 [0x000000821a7280, 0x000000ffe64000)
10156 23:13:07.097266
10157 23:13:07.097421 [0x00000100000000, 0x00000240000000)
10158 23:13:08.987962
10159 23:13:08.990994 Initializing XHCI USB controller at 0x11200000.
10160 23:13:09.972941
10161 23:13:09.973464 R8152: Initializing
10162 23:13:09.973801
10163 23:13:09.975663 Version 9 (ocp_data = 6010)
10164 23:13:09.976119
10165 23:13:09.979170 R8152: Done initializing
10166 23:13:09.979743
10167 23:13:09.980086 Adding net device
10168 23:13:10.376515
10169 23:13:10.380093 [firmware-asurada-13885.B-collabora] Dec 14 2021 15:21:43
10170 23:13:10.380615
10171 23:13:10.380948
10172 23:13:10.381254
10173 23:13:10.382014 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10175 23:13:10.483219 asurada: tftpboot 192.168.201.1 12395410/tftp-deploy-_gi8__3c/kernel/image.itb 12395410/tftp-deploy-_gi8__3c/kernel/cmdline
10176 23:13:10.484046 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10177 23:13:10.484483 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10178 23:13:10.489393 tftpboot 192.168.201.1 12395410/tftp-deploy-_gi8__3c/kernel/image.itp-deploy-_gi8__3c/kernel/cmdline
10179 23:13:10.489942
10180 23:13:10.490275 Waiting for link
10181 23:13:10.690867
10182 23:13:10.691380 done.
10183 23:13:10.691746
10184 23:13:10.692061 MAC: f4:f5:e8:50:de:0a
10185 23:13:10.692360
10186 23:13:10.693832 Sending DHCP discover... done.
10187 23:13:10.694250
10188 23:13:10.697009 Waiting for reply... done.
10189 23:13:10.697457
10190 23:13:10.700526 Sending DHCP request... done.
10191 23:13:10.700947
10192 23:13:10.706053 Waiting for reply... done.
10193 23:13:10.706472
10194 23:13:10.706802 My ip is 192.168.201.14
10195 23:13:10.707107
10196 23:13:10.710037 The DHCP server ip is 192.168.201.1
10197 23:13:10.710460
10198 23:13:10.716080 TFTP server IP predefined by user: 192.168.201.1
10199 23:13:10.716517
10200 23:13:10.723172 Bootfile predefined by user: 12395410/tftp-deploy-_gi8__3c/kernel/image.itb
10201 23:13:10.723763
10202 23:13:10.726589 Sending tftp read request... done.
10203 23:13:10.727178
10204 23:13:10.732310 Waiting for the transfer...
10205 23:13:10.732831
10206 23:13:11.019938 00000000 ################################################################
10207 23:13:11.020085
10208 23:13:11.279895 00080000 ################################################################
10209 23:13:11.280034
10210 23:13:11.525379 00100000 ################################################################
10211 23:13:11.525531
10212 23:13:11.745783 00180000 ################################################################
10213 23:13:11.745963
10214 23:13:11.977627 00200000 ################################################################
10215 23:13:11.977801
10216 23:13:12.225403 00280000 ################################################################
10217 23:13:12.225584
10218 23:13:12.462150 00300000 ################################################################
10219 23:13:12.462309
10220 23:13:12.712225 00380000 ################################################################
10221 23:13:12.712383
10222 23:13:12.974243 00400000 ################################################################
10223 23:13:12.974383
10224 23:13:13.216358 00480000 ################################################################
10225 23:13:13.216520
10226 23:13:13.470686 00500000 ################################################################
10227 23:13:13.470835
10228 23:13:13.725181 00580000 ################################################################
10229 23:13:13.725338
10230 23:13:13.984720 00600000 ################################################################
10231 23:13:13.984890
10232 23:13:14.246629 00680000 ################################################################
10233 23:13:14.246816
10234 23:13:14.492613 00700000 ################################################################
10235 23:13:14.492779
10236 23:13:14.759100 00780000 ################################################################
10237 23:13:14.759260
10238 23:13:15.022070 00800000 ################################################################
10239 23:13:15.022210
10240 23:13:15.297626 00880000 ################################################################
10241 23:13:15.297764
10242 23:13:15.558877 00900000 ################################################################
10243 23:13:15.559023
10244 23:13:15.798566 00980000 ################################################################
10245 23:13:15.798709
10246 23:13:16.040680 00a00000 ################################################################
10247 23:13:16.040823
10248 23:13:16.278882 00a80000 ################################################################
10249 23:13:16.279020
10250 23:13:16.514060 00b00000 ################################################################
10251 23:13:16.514192
10252 23:13:16.752999 00b80000 ################################################################
10253 23:13:16.753133
10254 23:13:16.992039 00c00000 ################################################################
10255 23:13:16.992165
10256 23:13:17.232194 00c80000 ################################################################
10257 23:13:17.232327
10258 23:13:17.476232 00d00000 ################################################################
10259 23:13:17.476368
10260 23:13:17.713202 00d80000 ################################################################
10261 23:13:17.713330
10262 23:13:17.954834 00e00000 ################################################################
10263 23:13:17.954989
10264 23:13:18.189137 00e80000 ################################################################
10265 23:13:18.189275
10266 23:13:18.416046 00f00000 ################################################################
10267 23:13:18.416182
10268 23:13:18.647208 00f80000 ################################################################
10269 23:13:18.647332
10270 23:13:18.891087 01000000 ################################################################
10271 23:13:18.891228
10272 23:13:19.147694 01080000 ################################################################
10273 23:13:19.147833
10274 23:13:19.400662 01100000 ################################################################
10275 23:13:19.400796
10276 23:13:19.672477 01180000 ################################################################
10277 23:13:19.672619
10278 23:13:19.940559 01200000 ################################################################
10279 23:13:19.940709
10280 23:13:20.210192 01280000 ################################################################
10281 23:13:20.210334
10282 23:13:20.480939 01300000 ################################################################
10283 23:13:20.481076
10284 23:13:20.710301 01380000 ################################################################
10285 23:13:20.710434
10286 23:13:20.958791 01400000 ################################################################
10287 23:13:20.958962
10288 23:13:21.225483 01480000 ################################################################
10289 23:13:21.225621
10290 23:13:21.495353 01500000 ################################################################
10291 23:13:21.495484
10292 23:13:21.765312 01580000 ################################################################
10293 23:13:21.765450
10294 23:13:22.033257 01600000 ################################################################
10295 23:13:22.033399
10296 23:13:22.300721 01680000 ################################################################
10297 23:13:22.300866
10298 23:13:22.570425 01700000 ################################################################
10299 23:13:22.570563
10300 23:13:22.819251 01780000 ################################################################
10301 23:13:22.819385
10302 23:13:23.078883 01800000 ################################################################
10303 23:13:23.079020
10304 23:13:23.339698 01880000 ################################################################
10305 23:13:23.339849
10306 23:13:23.596511 01900000 ################################################################
10307 23:13:23.596642
10308 23:13:23.863252 01980000 ################################################################
10309 23:13:23.863386
10310 23:13:24.133612 01a00000 ################################################################
10311 23:13:24.133742
10312 23:13:24.403816 01a80000 ################################################################
10313 23:13:24.403958
10314 23:13:24.662305 01b00000 ################################################################
10315 23:13:24.662454
10316 23:13:24.900360 01b80000 ############################################################# done.
10317 23:13:24.900491
10318 23:13:24.903374 The bootfile was 29331818 bytes long.
10319 23:13:24.903448
10320 23:13:24.906596 Sending tftp read request... done.
10321 23:13:24.906675
10322 23:13:24.910071 Waiting for the transfer...
10323 23:13:24.910142
10324 23:13:24.910205 00000000 # done.
10325 23:13:24.910264
10326 23:13:24.919716 Command line loaded dynamically from TFTP file: 12395410/tftp-deploy-_gi8__3c/kernel/cmdline
10327 23:13:24.919809
10328 23:13:24.942480 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12395410/extract-nfsrootfs-71p0c99j,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10329 23:13:24.942565
10330 23:13:24.942628 Loading FIT.
10331 23:13:24.942687
10332 23:13:24.946196 Image ramdisk-1 has 17802118 bytes.
10333 23:13:24.946269
10334 23:13:24.949446 Image fdt-1 has 47278 bytes.
10335 23:13:24.949523
10336 23:13:24.952441 Image kernel-1 has 11480388 bytes.
10337 23:13:24.952510
10338 23:13:24.958965 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10339 23:13:24.959044
10340 23:13:24.978943 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10341 23:13:24.979026
10342 23:13:24.982607 Choosing best match conf-1 for compat google,spherion-rev2.
10343 23:13:24.987425
10344 23:13:24.991664 Connected to device vid:did:rid of 1ae0:0028:00
10345 23:13:24.998942
10346 23:13:25.001975 tpm_get_response: command 0x17b, return code 0x0
10347 23:13:25.002047
10348 23:13:25.005539 ec_init: CrosEC protocol v3 supported (256, 248)
10349 23:13:25.009779
10350 23:13:25.013567 tpm_cleanup: add release locality here.
10351 23:13:25.013640
10352 23:13:25.013700 Shutting down all USB controllers.
10353 23:13:25.016476
10354 23:13:25.016549 Removing current net device
10355 23:13:25.016613
10356 23:13:25.022968 Exiting depthcharge with code 4 at timestamp: 48507855
10357 23:13:25.023044
10358 23:13:25.026392 LZMA decompressing kernel-1 to 0x821a6718
10359 23:13:25.026466
10360 23:13:25.029395 LZMA decompressing kernel-1 to 0x40000000
10361 23:13:26.465998
10362 23:13:26.466140 jumping to kernel
10363 23:13:26.466585 end: 2.2.4 bootloader-commands (duration 00:00:20) [common]
10364 23:13:26.466683 start: 2.2.5 auto-login-action (timeout 00:04:05) [common]
10365 23:13:26.466759 Setting prompt string to ['Linux version [0-9]']
10366 23:13:26.466833 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10367 23:13:26.466899 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10368 23:13:26.548495
10369 23:13:26.551199 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10370 23:13:26.554532 start: 2.2.5.1 login-action (timeout 00:04:04) [common]
10371 23:13:26.554618 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10372 23:13:26.554691 Setting prompt string to []
10373 23:13:26.554765 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10374 23:13:26.554836 Using line separator: #'\n'#
10375 23:13:26.554894 No login prompt set.
10376 23:13:26.554958 Parsing kernel messages
10377 23:13:26.555013 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10378 23:13:26.555110 [login-action] Waiting for messages, (timeout 00:04:04)
10379 23:13:26.574059 [ 0.000000] Linux version 6.1.67-cip12-rt7 (KernelCI@build-j59954-arm64-gcc-10-defconfig-arm64-chromebook-nblph) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Wed Dec 27 22:50:56 UTC 2023
10380 23:13:26.577889 [ 0.000000] random: crng init done
10381 23:13:26.584121 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10382 23:13:26.587532 [ 0.000000] efi: UEFI not found.
10383 23:13:26.594002 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10384 23:13:26.604230 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10385 23:13:26.614207 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10386 23:13:26.620476 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10387 23:13:26.627460 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10388 23:13:26.633425 [ 0.000000] printk: bootconsole [mtk8250] enabled
10389 23:13:26.640127 [ 0.000000] NUMA: No NUMA configuration found
10390 23:13:26.646884 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10391 23:13:26.653158 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcfa00-0x23efd1fff]
10392 23:13:26.653241 [ 0.000000] Zone ranges:
10393 23:13:26.659587 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10394 23:13:26.663183 [ 0.000000] DMA32 empty
10395 23:13:26.669812 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10396 23:13:26.672636 [ 0.000000] Movable zone start for each node
10397 23:13:26.676171 [ 0.000000] Early memory node ranges
10398 23:13:26.682676 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10399 23:13:26.689394 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10400 23:13:26.695898 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10401 23:13:26.702624 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10402 23:13:26.709097 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10403 23:13:26.715609 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10404 23:13:26.772497 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10405 23:13:26.779045 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10406 23:13:26.785802 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10407 23:13:26.788868 [ 0.000000] psci: probing for conduit method from DT.
10408 23:13:26.795468 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10409 23:13:26.799305 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10410 23:13:26.805702 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10411 23:13:26.809064 [ 0.000000] psci: SMC Calling Convention v1.2
10412 23:13:26.815460 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10413 23:13:26.818851 [ 0.000000] Detected VIPT I-cache on CPU0
10414 23:13:26.825343 [ 0.000000] CPU features: detected: GIC system register CPU interface
10415 23:13:26.831944 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10416 23:13:26.838325 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10417 23:13:26.845076 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10418 23:13:26.854723 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10419 23:13:26.861790 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10420 23:13:26.864952 [ 0.000000] alternatives: applying boot alternatives
10421 23:13:26.871220 [ 0.000000] Fallback order for Node 0: 0
10422 23:13:26.877691 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10423 23:13:26.881556 [ 0.000000] Policy zone: Normal
10424 23:13:26.904301 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12395410/extract-nfsrootfs-71p0c99j,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10425 23:13:26.914468 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10426 23:13:26.925517 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10427 23:13:26.936160 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10428 23:13:26.941595 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10429 23:13:26.945622 <6>[ 0.000000] software IO TLB: area num 8.
10430 23:13:27.002097 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10431 23:13:27.151387 <6>[ 0.000000] Memory: 7951332K/8385536K available (17984K kernel code, 4116K rwdata, 18184K rodata, 8448K init, 615K bss, 401436K reserved, 32768K cma-reserved)
10432 23:13:27.157727 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10433 23:13:27.164103 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10434 23:13:27.168036 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10435 23:13:27.174923 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10436 23:13:27.180675 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10437 23:13:27.184452 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10438 23:13:27.194277 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10439 23:13:27.200527 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10440 23:13:27.207317 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10441 23:13:27.213747 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10442 23:13:27.217436 <6>[ 0.000000] GICv3: 608 SPIs implemented
10443 23:13:27.220976 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10444 23:13:27.227001 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10445 23:13:27.230268 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10446 23:13:27.237538 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10447 23:13:27.250282 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10448 23:13:27.263257 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10449 23:13:27.269862 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10450 23:13:27.278018 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10451 23:13:27.291519 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10452 23:13:27.297247 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10453 23:13:27.304543 <6>[ 0.009236] Console: colour dummy device 80x25
10454 23:13:27.313960 <6>[ 0.013989] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10455 23:13:27.321258 <6>[ 0.024431] pid_max: default: 32768 minimum: 301
10456 23:13:27.323865 <6>[ 0.029303] LSM: Security Framework initializing
10457 23:13:27.330324 <6>[ 0.034242] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10458 23:13:27.340309 <6>[ 0.042055] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10459 23:13:27.346639 <6>[ 0.051347] cblist_init_generic: Setting adjustable number of callback queues.
10460 23:13:27.353997 <6>[ 0.058790] cblist_init_generic: Setting shift to 3 and lim to 1.
10461 23:13:27.363803 <6>[ 0.065127] cblist_init_generic: Setting adjustable number of callback queues.
10462 23:13:27.369650 <6>[ 0.072555] cblist_init_generic: Setting shift to 3 and lim to 1.
10463 23:13:27.374505 <6>[ 0.078993] rcu: Hierarchical SRCU implementation.
10464 23:13:27.379898 <6>[ 0.078995] rcu: Max phase no-delay instances is 1000.
10465 23:13:27.386257 <6>[ 0.079019] printk: bootconsole [mtk8250] printing thread started
10466 23:13:27.392682 <6>[ 0.097348] EFI services will not be available.
10467 23:13:27.396360 <6>[ 0.097549] smp: Bringing up secondary CPUs ...
10468 23:13:27.400231 <6>[ 0.097857] Detected VIPT I-cache on CPU1
10469 23:13:27.409225 <6>[ 0.097926] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10470 23:13:27.416392 <6>[ 0.097958] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10471 23:13:27.425198 <6>[ 0.125822] Detected VIPT I-cache on CPU2
10472 23:13:27.435516 <6>[ 0.125869] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10473 23:13:27.441769 <6>[ 0.125885] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10474 23:13:27.445112 <6>[ 0.126144] Detected VIPT I-cache on CPU3
10475 23:13:27.451648 <6>[ 0.126190] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10476 23:13:27.458538 <6>[ 0.126203] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10477 23:13:27.465086 <6>[ 0.126513] CPU features: detected: Spectre-v4
10478 23:13:27.468340 <6>[ 0.126519] CPU features: detected: Spectre-BHB
10479 23:13:27.471281 <6>[ 0.126523] Detected PIPT I-cache on CPU4
10480 23:13:27.478107 <6>[ 0.126582] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10481 23:13:27.485153 <6>[ 0.126598] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10482 23:13:27.491264 <6>[ 0.126888] Detected PIPT I-cache on CPU5
10483 23:13:27.498233 <6>[ 0.126947] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10484 23:13:27.504561 <6>[ 0.126964] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10485 23:13:27.507817 <6>[ 0.127239] Detected PIPT I-cache on CPU6
10486 23:13:27.518007 <6>[ 0.127303] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10487 23:13:27.524720 <6>[ 0.127319] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10488 23:13:27.528132 <6>[ 0.127611] Detected PIPT I-cache on CPU7
10489 23:13:27.534548 <6>[ 0.127675] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10490 23:13:27.540624 <6>[ 0.127691] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10491 23:13:27.544037 <6>[ 0.127738] smp: Brought up 1 node, 8 CPUs
10492 23:13:27.550623 <6>[ 0.127743] SMP: Total of 8 processors activated.
10493 23:13:27.557252 <6>[ 0.127746] CPU features: detected: 32-bit EL0 Support
10494 23:13:27.563606 <6>[ 0.127748] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10495 23:13:27.570610 <6>[ 0.127751] CPU features: detected: Common not Private translations
10496 23:13:27.577189 <6>[ 0.127752] CPU features: detected: CRC32 instructions
10497 23:13:27.583552 <6>[ 0.127755] CPU features: detected: RCpc load-acquire (LDAPR)
10498 23:13:27.586627 <6>[ 0.127756] CPU features: detected: LSE atomic instructions
10499 23:13:27.593591 <6>[ 0.127758] CPU features: detected: Privileged Access Never
10500 23:13:27.600019 <6>[ 0.127759] CPU features: detected: RAS Extension Support
10501 23:13:27.606417 <6>[ 0.127763] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10502 23:13:27.610098 <6>[ 0.127827] CPU: All CPU(s) started at EL2
10503 23:13:27.616141 <6>[ 0.127829] alternatives: applying system-wide alternatives
10504 23:13:27.620144 <6>[ 0.140899] devtmpfs: initialized
10505 23:13:27.649013 � ����B�͡����������ɥ��郪��Bzɑ�Ɂ�b��ʲ�ѕͥkRƲ���r��������s����A�
10506 23:13:27.655378 A%�"�ͅ����5R�<6>[ 0.359497] prin<tk: console [ttyS0] printing thread started
10507 23:13:27.659211 6>[ 0.228153] NET: Registered PF_INET protocol family
10508 23:13:27.667653 <6>[ 0.359508] printk: console [ttyS0] enabled
10509 23:13:27.671315 <6>[ 0.359512] printk: bootconsole [mtk8250] disabled
10510 23:13:27.678537 <6>[ 0.370481] printk: bootconsole [mtk8250] printing thread stopped
10511 23:13:27.684977 <6>[ 0.371649] SuperH (H)SCI(F) driver initialized
10512 23:13:27.687894 <6>[ 0.372126] msm_serial: driver initialized
10513 23:13:27.697679 <6>[ 0.376754] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10514 23:13:27.704151 <6>[ 0.376783] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10515 23:13:27.717336 <6>[ 0.376813] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10516 23:13:27.721568 <6>[ 0.376843] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10517 23:13:27.732034 <6>[ 0.376864] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10518 23:13:27.739476 <6>[ 0.376891] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10519 23:13:27.759422 <6>[ 0.376919] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10520 23:13:27.759776 <6>[ 0.377032] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10521 23:13:27.771368 <6>[ 0.377061] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10522 23:13:27.771447 <6>[ 0.386450] loop: module loaded
10523 23:13:27.779808 <6>[ 0.389033] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10524 23:13:27.782642 <4>[ 0.406189] mtk-pmic-keys: Failed to locate of_node [id: -1]
10525 23:13:27.786106 <6>[ 0.407176] megasas: 07.719.03.00-rc1
10526 23:13:27.789552 <6>[ 0.416702] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10527 23:13:27.795974 <6>[ 0.420727] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10528 23:13:27.803003 <6>[ 0.432743] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10529 23:13:27.812473 <6>[ 0.491410] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10530 23:13:28.308300 <6>[ 1.010134] Freeing initrd memory: 17380K
10531 23:13:28.314556 <6>[ 1.016445] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10532 23:13:28.317786 <6>[ 1.021122] tun: Universal TUN/TAP device driver, 1.6
10533 23:13:28.321408 <6>[ 1.021889] thunder_xcv, ver 1.0
10534 23:13:28.324843 <6>[ 1.021907] thunder_bgx, ver 1.0
10535 23:13:28.327562 <6>[ 1.021923] nicpf, ver 1.0
10536 23:13:28.337535 <6>[ 1.022964] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10537 23:13:28.340676 <6>[ 1.022966] hns3: Copyright (c) 2017 Huawei Corporation.
10538 23:13:28.344041 <6>[ 1.022991] hclge is initializing
10539 23:13:28.350497 <6>[ 1.023007] e1000: Intel(R) PRO/1000 Network Driver
10540 23:13:28.358181 <6>[ 1.023009] e1000: Copyright (c) 1999-2006 Intel Corporation.
10541 23:13:28.361262 <6>[ 1.023028] e1000e: Intel(R) PRO/1000 Network Driver
10542 23:13:28.368032 <6>[ 1.023030] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10543 23:13:28.372480 <6>[ 1.023046] igb: Intel(R) Gigabit Ethernet Network Driver
10544 23:13:28.378303 <6>[ 1.023048] igb: Copyright (c) 2007-2014 Intel Corporation.
10545 23:13:28.385280 <6>[ 1.023062] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10546 23:13:28.392425 <6>[ 1.023064] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10547 23:13:28.395553 <6>[ 1.023362] sky2: driver version 1.30
10548 23:13:28.401687 <6>[ 1.024437] VFIO - User Level meta-driver version: 0.3
10549 23:13:28.408365 <6>[ 1.027278] usbcore: registered new interface driver usb-storage
10550 23:13:28.415025 <6>[ 1.027458] usbcore: registered new device driver onboard-usb-hub
10551 23:13:28.418346 <6>[ 1.030253] mt6397-rtc mt6359-rtc: registered as rtc0
10552 23:13:28.428237 <6>[ 1.030408] mt6397-rtc mt6359-rtc: setting system clock to 2023-12-27T23:13:28 UTC (1703718808)
10553 23:13:28.431583 <6>[ 1.031026] i2c_dev: i2c /dev entries driver
10554 23:13:28.441440 <6>[ 1.038346] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10555 23:13:28.444404 <6>[ 1.054340] cpu cpu0: EM: created perf domain
10556 23:13:28.451339 <6>[ 1.054658] cpu cpu4: EM: created perf domain
10557 23:13:28.454845 <6>[ 1.055787] sdhci: Secure Digital Host Controller Interface driver
10558 23:13:28.461858 <6>[ 1.055788] sdhci: Copyright(c) Pierre Ossman
10559 23:13:28.468526 <6>[ 1.056118] Synopsys Designware Multimedia Card Interface Driver
10560 23:13:28.474533 <6>[ 1.056520] sdhci-pltfm: SDHCI platform and OF driver helper
10561 23:13:28.477860 <6>[ 1.060827] ledtrig-cpu: registered to indicate activity on CPUs
10562 23:13:28.484551 <6>[ 1.061208] mmc0: CQHCI version 5.10
10563 23:13:28.490930 <6>[ 1.063287] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10564 23:13:28.494434 <6>[ 1.064849] usbcore: registered new interface driver usbhid
10565 23:13:28.500912 <6>[ 1.064855] usbhid: USB HID core driver
10566 23:13:28.507762 <6>[ 1.065146] spi_master spi0: will run message pump with realtime priority
10567 23:13:28.520846 <6>[ 1.096480] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10568 23:13:28.533816 <6>[ 1.098870] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10569 23:13:28.537024 <6>[ 1.099950] cros-ec-spi spi0.0: Chrome EC device registered
10570 23:13:28.547015 <6>[ 1.117964] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10571 23:13:28.554260 <6>[ 1.121179] NET: Registered PF_PACKET protocol family
10572 23:13:28.556734 <6>[ 1.121319] 9pnet: Installing 9P2000 support
10573 23:13:28.563625 <5>[ 1.121388] Key type dns_resolver registered
10574 23:13:28.566797 <6>[ 1.121839] registered taskstats version 1
10575 23:13:28.570397 <5>[ 1.121860] Loading compiled-in X.509 certificates
10576 23:13:28.583909 <4>[ 1.137360] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10577 23:13:28.593269 <4>[ 1.137505] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10578 23:13:28.600268 <3>[ 1.137509] debugfs: File 'uA_load' in directory '/' already present!
10579 23:13:28.606949 <3>[ 1.137514] debugfs: File 'min_uV' in directory '/' already present!
10580 23:13:28.613287 <3>[ 1.137515] debugfs: File 'max_uV' in directory '/' already present!
10581 23:13:28.619910 <3>[ 1.137517] debugfs: File 'constraint_flags' in directory '/' already present!
10582 23:13:28.629361 <3>[ 1.138749] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10583 23:13:28.636414 <6>[ 1.141752] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10584 23:13:28.639749 <6>[ 1.142338] xhci-mtk 11200000.usb: xHCI Host Controller
10585 23:13:28.650007 <6>[ 1.142354] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10586 23:13:28.656341 <6>[ 1.142558] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10587 23:13:28.662457 <6>[ 1.142594] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10588 23:13:28.669466 <6>[ 1.142674] xhci-mtk 11200000.usb: xHCI Host Controller
10589 23:13:28.676178 <6>[ 1.142676] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10590 23:13:28.682307 <6>[ 1.142681] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10591 23:13:28.689376 <6>[ 1.143180] hub 1-0:1.0: USB hub found
10592 23:13:28.692612 <6>[ 1.143191] hub 1-0:1.0: 1 port detected
10593 23:13:28.698951 <6>[ 1.143296] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10594 23:13:28.705403 <6>[ 1.143658] hub 2-0:1.0: USB hub found
10595 23:13:28.709053 <6>[ 1.143668] hub 2-0:1.0: 1 port detected
10596 23:13:28.712003 <6>[ 1.147834] mtk-msdc 11f70000.mmc: Got CD GPIO
10597 23:13:28.721839 <6>[ 1.154996] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10598 23:13:28.728834 <6>[ 1.155004] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10599 23:13:28.738982 <4>[ 1.155085] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10600 23:13:28.745643 <6>[ 1.155576] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10601 23:13:28.755190 <6>[ 1.155577] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10602 23:13:28.761641 <6>[ 1.155716] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10603 23:13:28.768346 <6>[ 1.155723] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10604 23:13:28.778066 <6>[ 1.155724] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10605 23:13:28.784595 <6>[ 1.155728] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10606 23:13:28.795097 <6>[ 1.156560] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10607 23:13:28.804810 <6>[ 1.156569] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10608 23:13:28.811510 <6>[ 1.156573] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10609 23:13:28.820978 <6>[ 1.156576] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10610 23:13:28.827692 <6>[ 1.156580] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10611 23:13:28.837752 <6>[ 1.156583] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10612 23:13:28.843895 <6>[ 1.156587] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10613 23:13:28.853782 <6>[ 1.156590] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10614 23:13:28.860544 <6>[ 1.156594] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10615 23:13:28.870178 <6>[ 1.156597] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10616 23:13:28.877719 <6>[ 1.156600] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10617 23:13:28.886690 <6>[ 1.156604] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10618 23:13:28.893567 <6>[ 1.156607] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10619 23:13:28.903240 <6>[ 1.156610] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10620 23:13:28.910128 <6>[ 1.156614] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10621 23:13:28.917208 <6>[ 1.156904] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10622 23:13:28.923460 <6>[ 1.157570] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10623 23:13:28.929721 <6>[ 1.157807] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10624 23:13:28.936500 <6>[ 1.158054] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10625 23:13:28.942673 <6>[ 1.158314] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10626 23:13:28.953217 <6>[ 1.158469] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10627 23:13:28.962806 <6>[ 1.158478] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10628 23:13:28.972420 <6>[ 1.158480] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10629 23:13:28.982352 <6>[ 1.158483] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10630 23:13:28.989158 <6>[ 1.158486] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10631 23:13:28.998829 <6>[ 1.158489] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10632 23:13:29.009396 <6>[ 1.158492] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10633 23:13:29.019180 <6>[ 1.158495] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10634 23:13:29.028617 <6>[ 1.158497] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10635 23:13:29.039304 <6>[ 1.158501] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10636 23:13:29.048476 <6>[ 1.158503] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10637 23:13:29.055227 <6>[ 1.159321] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10638 23:13:29.061891 <6>[ 1.160498] mmc0: Command Queue Engine enabled
10639 23:13:29.068881 <6>[ 1.160506] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10640 23:13:29.071848 <6>[ 1.160983] mmcblk0: mmc0:0001 DA4128 116 GiB
10641 23:13:29.078449 <6>[ 1.164251] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10642 23:13:29.085557 <6>[ 1.165021] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10643 23:13:29.088698 <6>[ 1.165762] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10644 23:13:29.095263 <6>[ 1.166259] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10645 23:13:29.101448 <6>[ 1.186057] Trying to probe devices needed for running init ...
10646 23:13:29.108181 <6>[ 1.557399] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10647 23:13:29.111517 <6>[ 1.710127] hub 1-1:1.0: USB hub found
10648 23:13:29.117845 <6>[ 1.710545] hub 1-1:1.0: 4 ports detected
10649 23:13:29.120988 <6>[ 1.714402] hub 1-1:1.0: USB hub found
10650 23:13:29.124276 <6>[ 1.714691] hub 1-1:1.0: 4 ports detected
10651 23:13:29.138973 <6>[ 1.837635] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10652 23:13:29.160327 <6>[ 1.861935] hub 2-1:1.0: USB hub found
10653 23:13:29.163133 <6>[ 1.862303] hub 2-1:1.0: 3 ports detected
10654 23:13:29.166364 <6>[ 1.864420] hub 2-1:1.0: USB hub found
10655 23:13:29.173071 <6>[ 1.864726] hub 2-1:1.0: 3 ports detected
10656 23:13:29.327519 <6>[ 2.025622] usb 1-1.1: new high-speed USB device number 3 using xhci-mtk
10657 23:13:29.447896 <6>[ 2.151461] hub 1-1.1:1.0: USB hub found
10658 23:13:29.451016 <6>[ 2.151572] hub 1-1.1:1.0: 4 ports detected
10659 23:13:29.559400 <6>[ 2.257414] usb 1-1.4: new high-speed USB device number 4 using xhci-mtk
10660 23:13:29.680264 <6>[ 2.384939] hub 1-1.4:1.0: USB hub found
10661 23:13:29.683090 <6>[ 2.385328] hub 1-1.4:1.0: 2 ports detected
10662 23:13:29.686793 <6>[ 2.388833] hub 1-1.4:1.0: USB hub found
10663 23:13:29.693832 <6>[ 2.389171] hub 1-1.4:1.0: 2 ports detected
10664 23:13:29.762890 <6>[ 2.461589] usb 1-1.1.1: new high-speed USB device number 5 using xhci-mtk
10665 23:13:29.979005 <6>[ 2.677605] usb 1-1.4.1: new high-speed USB device number 6 using xhci-mtk
10666 23:13:30.162950 <6>[ 2.861622] usb 1-1.4.2: new high-speed USB device number 7 using xhci-mtk
10667 23:13:40.768216 <6>[ 13.474614] ALSA device list:
10668 23:13:40.774043 <6>[ 13.474634] No soundcards found.
10669 23:13:40.777660 <6>[ 13.478312] Freeing unused kernel memory: 8448K
10670 23:13:40.780912 <6>[ 13.478532] Run /init as init process
10671 23:13:40.783930 Loading, please wait...
10672 23:13:40.802756 Starting version 247.3-7+deb11u2
10673 23:13:40.942586 <6>[ 13.644418] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10674 23:13:40.962898 <6>[ 13.654607] remoteproc remoteproc0: scp is available
10675 23:13:40.969799 <6>[ 13.654639] remoteproc remoteproc0: powering up scp
10676 23:13:40.976246 <6>[ 13.654641] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10677 23:13:40.982590 <6>[ 13.654650] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10678 23:13:40.989884 <6>[ 13.674862] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10679 23:13:40.999542 <6>[ 13.674882] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10680 23:13:41.009658 <6>[ 13.674887] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10681 23:13:41.016448 <3>[ 13.679046] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10682 23:13:41.025829 <3>[ 13.679063] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10683 23:13:41.032455 <3>[ 13.679071] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10684 23:13:41.042786 <3>[ 13.705870] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10685 23:13:41.048712 <3>[ 13.705889] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10686 23:13:41.054894 <3>[ 13.705896] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10687 23:13:41.064788 <3>[ 13.705906] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10688 23:13:41.072862 <3>[ 13.705913] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10689 23:13:41.082467 <3>[ 13.716838] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10690 23:13:41.088659 <3>[ 13.716916] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10691 23:13:41.095950 <3>[ 13.716925] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10692 23:13:41.105973 <3>[ 13.716932] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10693 23:13:41.112990 <3>[ 13.717002] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10694 23:13:41.122038 <3>[ 13.717010] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10695 23:13:41.128821 <3>[ 13.717017] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10696 23:13:41.138778 <3>[ 13.717025] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10697 23:13:41.145525 <3>[ 13.717031] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10698 23:13:41.152759 <3>[ 13.721767] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10699 23:13:41.161800 <4>[ 13.728292] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10700 23:13:41.168463 <4>[ 13.728352] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10701 23:13:41.172197 <6>[ 13.736281] mc: Linux media interface: v0.10
10702 23:13:41.182430 <6>[ 13.745318] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10703 23:13:41.185222 <6>[ 13.750852] usbcore: registered new interface driver r8152
10704 23:13:41.195065 <4>[ 13.770265] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10705 23:13:41.198306 <4>[ 13.770265] Fallback method does not support PEC.
10706 23:13:41.208713 <3>[ 13.786289] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10707 23:13:41.214863 <6>[ 13.797732] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10708 23:13:41.221381 <6>[ 13.797736] pci_bus 0000:00: root bus resource [bus 00-ff]
10709 23:13:41.227990 <6>[ 13.797739] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10710 23:13:41.237769 <6>[ 13.797741] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10711 23:13:41.244306 <6>[ 13.797758] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10712 23:13:41.251265 <6>[ 13.797770] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10713 23:13:41.257678 <6>[ 13.797824] pci 0000:00:00.0: supports D1 D2
10714 23:13:41.264534 <6>[ 13.797826] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10715 23:13:41.271539 <6>[ 13.798495] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10716 23:13:41.277813 <6>[ 13.798563] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10717 23:13:41.283927 <6>[ 13.798587] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10718 23:13:41.291055 <6>[ 13.798602] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10719 23:13:41.300935 <6>[ 13.798616] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10720 23:13:41.303965 <6>[ 13.798717] pci 0000:01:00.0: supports D1 D2
10721 23:13:41.311440 <6>[ 13.798718] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10722 23:13:41.317232 <6>[ 13.798750] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10723 23:13:41.327095 <6>[ 13.798794] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10724 23:13:41.334267 <6>[ 13.798798] remoteproc remoteproc0: remote processor scp is now up
10725 23:13:41.340666 <6>[ 13.809363] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10726 23:13:41.347033 <6>[ 13.809375] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10727 23:13:41.356730 <6>[ 13.809378] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10728 23:13:41.363544 <6>[ 13.809386] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10729 23:13:41.373194 <6>[ 13.809398] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10730 23:13:41.380127 <6>[ 13.809411] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10731 23:13:41.386929 <6>[ 13.809422] pci 0000:00:00.0: PCI bridge to [bus 01]
10732 23:13:41.393391 <6>[ 13.809427] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10733 23:13:41.400194 <6>[ 13.809493] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10734 23:13:41.406376 <6>[ 13.809800] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10735 23:13:41.413841 <6>[ 13.809876] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10736 23:13:41.419454 <6>[ 13.810099] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10737 23:13:41.429450 <3>[ 13.811476] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10738 23:13:41.436169 <6>[ 13.811506] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10739 23:13:41.442756 <6>[ 13.833613] usb 1-1.1.1: reset high-speed USB device number 5 using xhci-mtk
10740 23:13:41.452637 <6>[ 13.837727] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10741 23:13:41.463056 <6>[ 13.854391] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10742 23:13:41.472451 <6>[ 13.854674] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10743 23:13:41.479022 <6>[ 13.866275] videodev: Linux video capture interface: v2.00
10744 23:13:41.486187 <5>[ 13.873701] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10745 23:13:41.492413 <6>[ 13.880237] usbcore: registered new interface driver cdc_ether
10746 23:13:41.499007 <5>[ 13.884690] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10747 23:13:41.508844 <4>[ 13.884784] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10748 23:13:41.512150 <6>[ 13.884791] cfg80211: failed to load regulatory.db
10749 23:13:41.518885 <6>[ 13.892348] usbcore: registered new interface driver r8153_ecm
10750 23:13:41.521723 <6>[ 13.899735] Bluetooth: Core ver 2.22
10751 23:13:41.528759 <6>[ 13.899768] NET: Registered PF_BLUETOOTH protocol family
10752 23:13:41.535045 <6>[ 13.899770] Bluetooth: HCI device and connection manager initialized
10753 23:13:41.541423 <6>[ 13.899777] Bluetooth: HCI socket layer initialized
10754 23:13:41.545031 <6>[ 13.899779] Bluetooth: L2CAP socket layer initialized
10755 23:13:41.551663 <6>[ 13.899783] Bluetooth: SCO socket layer initialized
10756 23:13:41.557933 <6>[ 13.927906] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10757 23:13:41.571256 <6>[ 13.928844] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10758 23:13:41.574765 <6>[ 13.928919] usbcore: registered new interface driver uvcvideo
10759 23:13:41.584748 <4>[ 13.940430] r8152 1-1.1.1:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10760 23:13:41.594910 <4>[ 13.940441] r8152 1-1.1.1:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10761 23:13:41.597831 <6>[ 13.968463] usbcore: registered new interface driver btusb
10762 23:13:41.604284 <6>[ 13.968507] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10763 23:13:41.617997 <4>[ 13.969094] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10764 23:13:41.621163 <3>[ 13.969102] Bluetooth: hci0: Failed to load firmware file (-2)
10765 23:13:41.627459 <3>[ 13.969105] Bluetooth: hci0: Failed to set up firmware (-2)
10766 23:13:41.637350 <4>[ 13.969107] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10767 23:13:41.647156 <6>[ 13.976247] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10768 23:13:41.653730 <6>[ 13.976315] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10769 23:13:41.657006 <6>[ 13.993517] mt7921e 0000:01:00.0: ASIC revision: 79610010
10770 23:13:41.663844 <6>[ 13.993697] r8152 1-1.1.1:1.0 eth0: v1.12.13
10771 23:13:41.667300 <6>[ 14.000419] r8152 1-1.1.1:1.0 enxf4f5e850de0a: renamed from eth0
10772 23:13:41.676853 <6>[ 14.079075] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
10773 23:13:41.680148 <6>[ 14.079075]
10774 23:13:41.686804 <6>[ 14.335532] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
10775 23:13:41.690917 Begin: Loading essential drivers ... done.
10776 23:13:41.696827 Begin: Running /scripts/init-premount ... done.
10777 23:13:41.703128 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10778 23:13:41.710089 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10779 23:13:41.716901 Device /sys/class/net/enxf4f5e850de0a found
10780 23:13:41.716998 done.
10781 23:13:41.750031 IP-Config: enxf4f5e850de0a hardware address f4:f5:e8:50:de:0a mtu 1500 DHCP
10782 23:13:42.470910 <6>[ 15.177068] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10783 23:13:42.824003 IP-Config: no response after 2 secs - giving up
10784 23:13:42.883344 IP-Config: wlp1s0 hardware address d8:f3:bc:78:0c:47 mtu 1500 DHCP
10785 23:13:42.938456 <6>[ 15.644467] r8152 1-1.1.1:1.0 enxf4f5e850de0a: carrier on
10786 23:13:43.602493 IP-Config: enxf4f5e850de0a hardware address f4:f5:e8:50:de:0a mtu 1500 DHCP
10787 23:13:43.605762 IP-Config: enxf4f5e850de0a complete (dhcp from 192.168.201.1):
10788 23:13:43.615452 address: 192.168.201.14 broadcast: 192.168.201.255 netmask: 255.255.255.0
10789 23:13:43.622158 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10790 23:13:43.628524 host : mt8192-asurada-spherion-r0-cbg-9
10791 23:13:43.635258 domain : lava-rack
10792 23:13:43.638362 rootserver: 192.168.201.1 rootpath:
10793 23:13:43.638823 filename :
10794 23:13:43.758973 done.
10795 23:13:43.766018 Begin: Running /scripts/nfs-bottom ... done.
10796 23:13:43.774232 Begin: Running /scripts/init-bottom ... done.
10797 23:13:44.939480 <6>[ 17.643068] NET: Registered PF_INET6 protocol family
10798 23:13:44.942895 <6>[ 17.645044] Segment Routing with IPv6
10799 23:13:44.949264 <6>[ 17.645072] In-situ OAM (IOAM) with IPv6
10800 23:13:45.046343 <30>[ 17.732149] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10801 23:13:45.046482
10802 23:13:45.052468 Welcome to [1<30>[ 17.732945] systemd[1]: Detected architecture arm64.
10803 23:13:45.055893 mDebian GNU/Linux 11 (bullseye)[0m!
10804 23:13:45.056004
10805 23:13:45.078019 <30>[ 17.783545] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10806 23:13:45.837798 <30>[ 18.539602] systemd[1]: Queued start job for default target Graphical Interface.
10807 23:13:45.876756 [[0;32m OK [<30>[ 18.579976] systemd[1]: Created slice system-getty.slice.
10808 23:13:45.880118 0m] Created slice [0;1;39msystem-getty.slice[0m.
10809 23:13:45.899567 [[0;32m OK [0m] Created slic<30>[ 18.603016] systemd[1]: Created slice system-modprobe.slice.
10810 23:13:45.902771 e [0;1;39msystem-modprobe.slice[0m.
10811 23:13:45.922799 [[0;32m OK [0m] Created slic<30>[ 18.626902] systemd[1]: Created slice system-serial\x2dgetty.slice.
10812 23:13:45.929495 e [0;1;39msystem-serial\x2dgetty.slice[0m.
10813 23:13:45.947244 [[0;32m OK [0m] Created slic<30>[ 18.651180] systemd[1]: Created slice User and Session Slice.
10814 23:13:45.950492 e [0;1;39mUser and Session Slice[0m.
10815 23:13:45.973684 [[0;32m OK [0m] Started [0;1;39mDispatch Pa<30>[ 18.674330] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10816 23:13:45.977773 ssword …ts to Console Directory Watch[0m.
10817 23:13:46.001364 [[0;32m OK [0m] Started [0;1;39mForward Pas<30>[ 18.701812] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10818 23:13:46.004595 sword R…uests to Wall Directory Watch[0m.
10819 23:13:46.028740 [[0;32m OK [0m] Reached target [0;1;39mLoca<30>[ 18.725883] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10820 23:13:46.035639 <30>[ 18.726093] systemd[1]: Reached target Local Encrypted Volumes.
10821 23:13:46.038734 l Encrypted Volumes[0m.
10822 23:13:46.058442 [[0;32m OK [0m] Reached target [0;1;39mPath<30>[ 18.762030] systemd[1]: Reached target Paths.
10823 23:13:46.058763 s[0m.
10824 23:13:46.081701 [[0;32m OK [0m] Reached target [0;1;39mRemo<30>[ 18.781600] systemd[1]: Reached target Remote File Systems.
10825 23:13:46.082253 te File Systems[0m.
10826 23:13:46.102084 [[0;32m OK [0m] Reached target [0;1;39mSlic<30>[ 18.805917] systemd[1]: Reached target Slices.
10827 23:13:46.102512 es[0m.
10828 23:13:46.122124 [[0;32m OK [0m] Reached target [0;1;39mSwap<30>[ 18.825604] systemd[1]: Reached target Swap.
10829 23:13:46.122692 [0m.
10830 23:13:46.146117 [[0;32m OK [0m] Listening on [0;1;39minitct<30>[ 18.846073] systemd[1]: Listening on initctl Compatibility Named Pipe.
10831 23:13:46.148913 l Compatibility Named Pipe[0m.
10832 23:13:46.168700 [[0;32m OK [0m] Listening on<30>[ 18.871484] systemd[1]: Listening on Journal Audit Socket.
10833 23:13:46.170979 [0;1;39mJournal Audit Socket[0m.
10834 23:13:46.191571 [[0;32m OK [0m] Listening on<30>[ 18.895089] systemd[1]: Listening on Journal Socket (/dev/log).
10835 23:13:46.194849 [0;1;39mJournal Socket (/dev/log)[0m.
10836 23:13:46.215550 [[0;32m OK [0m] Listening on<30>[ 18.918757] systemd[1]: Listening on Journal Socket.
10837 23:13:46.218617 [0;1;39mJournal Socket[0m.
10838 23:13:46.236689 [[0;32m OK [0m] Listening on<30>[ 18.939441] systemd[1]: Listening on Network Service Netlink Socket.
10839 23:13:46.242562 [0;1;39mNetwork Service Netlink Socket[0m.
10840 23:13:46.261851 [[0;32m OK [<30>[ 18.964677] systemd[1]: Listening on udev Control Socket.
10841 23:13:46.264135 0m] Listening on [0;1;39mudev Control Socket[0m.
10842 23:13:46.283040 [[0;32m OK [0m] Listening on [0;1;39mudev K<30>[ 18.986044] systemd[1]: Listening on udev Kernel Socket.
10843 23:13:46.286153 ernel Socket[0m.
10844 23:13:46.345640 Mounting [0;1;39mHuge Pages File Syste<30>[ 19.045664] systemd[1]: Mounting Huge Pages File System...
10845 23:13:46.345953 m[0m...
10846 23:13:46.369180 Mounting [0;1;39mPOSIX Message Queue F<30>[ 19.069639] systemd[1]: Mounting POSIX Message Queue File System...
10847 23:13:46.369557 ile System[0m...
10848 23:13:46.397790 Mounting [0;1;39mKernel Debug File Sys<30>[ 19.097971] systemd[1]: Mounting Kernel Debug File System...
10849 23:13:46.398241 tem[0m...
10850 23:13:46.421952 <30>[ 19.121727] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10851 23:13:46.435828 Startin<30>[ 19.136394] systemd[1]: Starting Create list of static device nodes for the current kernel...
10852 23:13:46.439451 g [0;1;39mCreate list of st…odes for the current kernel[0m...
10853 23:13:46.461114 Startin<30>[ 19.164679] systemd[1]: Starting Load Kernel Module configfs...
10854 23:13:46.464323 g [0;1;39mLoad Kernel Module configfs[0m...
10855 23:13:46.493505 Starting [0;1;39mLoad Kernel Module dr<30>[ 19.194194] systemd[1]: Starting Load Kernel Module drm...
10856 23:13:46.493837 m[0m...
10857 23:13:46.516878 Startin<30>[ 19.220516] systemd[1]: Starting Load Kernel Module fuse...
10858 23:13:46.519988 g [0;1;39mLoad Kernel Module fuse[0m...
10859 23:13:46.545752 <6>[ 19.252404] fuse: init (API version 7.37)
10860 23:13:46.555858 <30>[ 19.253366] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10861 23:13:46.593776 Starting [0;1;39mJournal Service[0m..<30>[ 19.297896] systemd[1]: Starting Journal Service...
10862 23:13:46.593901 .
10863 23:13:46.619797 Startin<30>[ 19.323866] systemd[1]: Starting Load Kernel Modules...
10864 23:13:46.622813 g [0;1;39mLoad Kernel Modules[0m...
10865 23:13:46.644054 Startin<30>[ 19.347997] systemd[1]: Starting Remount Root and Kernel File Systems...
10866 23:13:46.650423 g [0;1;39mRemount Root and Kernel File Systems[0m...
10867 23:13:46.693002 Starting [0;1;39mColdplug All udev Dev<30>[ 19.394031] systemd[1]: Starting Coldplug All udev Devices...
10868 23:13:46.693102 ices[0m...
10869 23:13:46.723793 [[0;32m OK [0m] Mounted [0;<30>[ 19.427386] systemd[1]: Mounted Huge Pages File System.
10870 23:13:46.726535 1;39mHuge Pages File System[0m.
10871 23:13:46.749172 <3>[ 19.449312] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10872 23:13:46.758693 [[0;32m OK [0m] Mounted [0;<30>[ 19.462777] systemd[1]: Mounted POSIX Message Queue File System.
10873 23:13:46.762171 1;39mPOSIX Message Queue File System[0m.
10874 23:13:46.781212 <3>[ 19.482007] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10875 23:13:46.787301 <30>[ 19.485886] systemd[1]: Mounted Kernel Debug File System.
10876 23:13:46.794370 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10877 23:13:46.813393 <3>[ 19.516007] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10878 23:13:46.826738 [[0;32m OK [0m] Finished [0<30>[ 19.527806] systemd[1]: Finished Create list of static device nodes for the current kernel.
10879 23:13:46.831020 ;1;39mCreate list of st… nodes for the current kernel[0m.
10880 23:13:46.845033 <3>[ 19.548120] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10881 23:13:46.856437 [[0;32m OK [<30>[ 19.559207] systemd[1]: modprobe@configfs.service: Succeeded.
10882 23:13:46.862314 0m] Finished [0<30>[ 19.559917] systemd[1]: Finished Load Kernel Module configfs.
10883 23:13:46.865435 ;1;39mLoad Kernel Module configfs[0m.
10884 23:13:46.887479 [[0;32m OK [0m] Finished [0<30>[ 19.590316] systemd[1]: modprobe@drm.service: Succeeded.
10885 23:13:46.894402 ;1;39mLoad Kerne<30>[ 19.590996] systemd[1]: Finished Load Kernel Module drm.
10886 23:13:46.903631 l Module drm[0m<3>[ 19.593464] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10887 23:13:46.903829 .
10888 23:13:46.921546 <3>[ 19.624298] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10889 23:13:46.932496 [[0;32m OK [<30>[ 19.635100] systemd[1]: modprobe@fuse.service: Succeeded.
10890 23:13:46.939124 0m] Finished [0<30>[ 19.635917] systemd[1]: Finished Load Kernel Module fuse.
10891 23:13:46.941656 ;1;39mLoad Kernel Module fuse[0m.
10892 23:13:46.957447 <3>[ 19.659272] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10893 23:13:46.963815 <30>[ 19.662466] systemd[1]: Finished Load Kernel Modules.
10894 23:13:46.968181 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10895 23:13:46.977387 <3>[ 19.680557] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10896 23:13:46.987986 [[0;32m OK [0m] Finished [0<30>[ 19.691498] systemd[1]: Finished Remount Root and Kernel File Systems.
10897 23:13:46.994746 ;1;39mRemount Root and Kernel File Systems[0m.
10898 23:13:47.009598 <3>[ 19.710387] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10899 23:13:47.040435 Mountin<3>[ 19.739501] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10900 23:13:47.047218 g [0;1;39mFUSE <30>[ 19.740749] systemd[1]: Mounting FUSE Control File System...
10901 23:13:47.049931 Control File System[0m...
10902 23:13:47.068281 Mounting [0;1;39mKerne<30>[ 19.771642] systemd[1]: Mounting Kernel Configuration File System...
10903 23:13:47.071142 l Configuration File System[0m...
10904 23:13:47.097532 <30>[ 19.797712] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10905 23:13:47.107977 <30>[ 19.797917] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10906 23:13:47.126650 Starting [0;1;39mLoad/Save Random Seed<30>[ 19.829867] systemd[1]: Starting Load/Save Random Seed...
10907 23:13:47.129473 [0m...
10908 23:13:47.148233 Startin<30>[ 19.852055] systemd[1]: Starting Apply Kernel Variables...
10909 23:13:47.151790 g [0;1;39mApply Kernel Variables[0m...
10910 23:13:47.173953 Starting [0;1;39mCreate System Users[<30>[ 19.877469] systemd[1]: Starting Create System Users...
10911 23:13:47.176967 0m...
10912 23:13:47.195993 <4>[ 19.890182] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10913 23:13:47.206794 <3>[ 19.890196] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10914 23:13:47.209573 <30>[ 19.911797] systemd[1]: Started Journal Service.
10915 23:13:47.213076 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10916 23:13:47.242752 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10917 23:13:47.258292 See 'systemctl status systemd-udev-trigger.service' for details.
10918 23:13:47.274940 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10919 23:13:47.291097 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10920 23:13:47.308136 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10921 23:13:47.328332 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10922 23:13:47.344717 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10923 23:13:47.383985 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10924 23:13:47.399201 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10925 23:13:47.429132 <46>[ 20.129801] systemd-journald[308]: Received client request to flush runtime journal.
10926 23:13:48.198504 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10927 23:13:48.210736 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10928 23:13:48.226340 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10929 23:13:48.278172 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10930 23:13:48.856291 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10931 23:13:48.910497 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10932 23:13:48.948510 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10933 23:13:48.982149 Starting [0;1;39mNetwork Service[0m...
10934 23:13:49.113438 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10935 23:13:49.169168 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10936 23:13:49.186339 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10937 23:13:49.563011 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10938 23:13:49.581372 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10939 23:13:49.622055 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10940 23:13:49.643597 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10941 23:13:49.658725 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10942 23:13:49.693005 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10943 23:13:49.747900 Starting [0;1;39mNetwork Name Resolution[0m...
10944 23:13:49.769052 Starting [0;1;39mNetwork Time Synchronization[0m...
10945 23:13:49.784442 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10946 23:13:49.802995 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10947 23:13:49.849033 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10948 23:13:49.942904 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10949 23:13:49.959447 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10950 23:13:49.977455 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10951 23:13:49.990663 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10952 23:13:50.006409 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10953 23:13:50.032443 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10954 23:13:50.100713 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10955 23:13:50.159221 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10956 23:13:50.217537 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10957 23:13:50.230381 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10958 23:13:50.257266 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10959 23:13:50.270562 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10960 23:13:50.285572 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10961 23:13:50.318800 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10962 23:13:50.422395 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
10963 23:13:50.503353 Starting [0;1;39mUser Login Management[0m...
10964 23:13:50.524393 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10965 23:13:50.543167 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10966 23:13:50.562023 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10967 23:13:50.610716 Starting [0;1;39mPermit User Sessions[0m...
10968 23:13:50.716051 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
10969 23:13:50.735940 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10970 23:13:50.780086 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10971 23:13:50.839658 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10972 23:13:50.846201 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10973 23:13:50.865699 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10974 23:13:50.889516 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10975 23:13:50.908737 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10976 23:13:50.969921 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10977 23:13:51.007181 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10978 23:13:51.063993
10979 23:13:51.064456
10980 23:13:51.067555 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10981 23:13:51.068083
10982 23:13:51.070744 debian-bullseye-arm64 login: root (automatic login)
10983 23:13:51.071168
10984 23:13:51.071497
10985 23:13:51.403460 Linux debian-bullseye-arm64 6.1.67-cip12-rt7 #1 SMP PREEMPT Wed Dec 27 22:50:56 UTC 2023 aarch64
10986 23:13:51.403602
10987 23:13:51.409386 The programs included with the Debian GNU/Linux system are free software;
10988 23:13:51.416818 the exact distribution terms for each program are described in the
10989 23:13:51.419238 individual files in /usr/share/doc/*/copyright.
10990 23:13:51.419322
10991 23:13:51.425860 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10992 23:13:51.429321 permitted by applicable law.
10993 23:13:52.206279 Matched prompt #10: / #
10995 23:13:52.206564 Setting prompt string to ['/ #']
10996 23:13:52.206659 end: 2.2.5.1 login-action (duration 00:00:26) [common]
10998 23:13:52.206849 end: 2.2.5 auto-login-action (duration 00:00:26) [common]
10999 23:13:52.206952 start: 2.2.6 expect-shell-connection (timeout 00:03:39) [common]
11000 23:13:52.207025 Setting prompt string to ['/ #']
11001 23:13:52.207088 Forcing a shell prompt, looking for ['/ #']
11003 23:13:52.257337 / #
11004 23:13:52.257753 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11005 23:13:52.258036 Waiting using forced prompt support (timeout 00:02:30)
11006 23:13:52.263759
11007 23:13:52.264575 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11008 23:13:52.265004 start: 2.2.7 export-device-env (timeout 00:03:39) [common]
11010 23:13:52.366234 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12395410/extract-nfsrootfs-71p0c99j'
11011 23:13:52.373031 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12395410/extract-nfsrootfs-71p0c99j'
11013 23:13:52.474639 / # export NFS_SERVER_IP='192.168.201.1'
11014 23:13:52.480739 export NFS_SERVER_IP='192.168.201.1'
11015 23:13:52.481580 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11016 23:13:52.482120 end: 2.2 depthcharge-retry (duration 00:01:21) [common]
11017 23:13:52.482622 end: 2 depthcharge-action (duration 00:01:21) [common]
11018 23:13:52.483153 start: 3 lava-test-retry (timeout 00:07:59) [common]
11019 23:13:52.483708 start: 3.1 lava-test-shell (timeout 00:07:59) [common]
11020 23:13:52.484174 Using namespace: common
11022 23:13:52.585452 / # #
11023 23:13:52.586192 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11024 23:13:52.591840 #
11025 23:13:52.592708 Using /lava-12395410
11027 23:13:52.693938 / # export SHELL=/bin/bash
11028 23:13:52.701040 export SHELL=/bin/bash
11030 23:13:52.802698 / # . /lava-12395410/environment
11031 23:13:52.809825 . /lava-12395410/environment
11033 23:13:52.916683 / # /lava-12395410/bin/lava-test-runner /lava-12395410/0
11034 23:13:52.917329 Test shell timeout: 10s (minimum of the action and connection timeout)
11035 23:13:52.923057 /lava-12395410/bin/lava-test-runner /lava-12395410/0
11036 23:13:53.181059 + export TESTRUN_ID=0_timesync-off
11037 23:13:53.184400 + TESTRUN_ID=0_timesync-off
11038 23:13:53.188152 + cd /lava-12395410/0/tests/0_timesync-off
11039 23:13:53.191077 ++ cat uuid
11040 23:13:53.194928 + UUID=12395410_1.6.2.3.1
11041 23:13:53.195346 + set +x
11042 23:13:53.201302 <LAVA_SIGNAL_STARTRUN 0_timesync-off 12395410_1.6.2.3.1>
11043 23:13:53.201994 Received signal: <STARTRUN> 0_timesync-off 12395410_1.6.2.3.1
11044 23:13:53.202365 Starting test lava.0_timesync-off (12395410_1.6.2.3.1)
11045 23:13:53.202780 Skipping test definition patterns.
11046 23:13:53.204188 + systemctl stop systemd-timesyncd
11047 23:13:53.259830 + set +x
11048 23:13:53.262853 <LAVA_SIGNAL_ENDRUN 0_timesync-off 12395410_1.6.2.3.1>
11049 23:13:53.263160 Received signal: <ENDRUN> 0_timesync-off 12395410_1.6.2.3.1
11050 23:13:53.263278 Ending use of test pattern.
11051 23:13:53.263372 Ending test lava.0_timesync-off (12395410_1.6.2.3.1), duration 0.06
11053 23:13:53.324216 + export TESTRUN_ID=1_kselftest-arm64
11054 23:13:53.324307 + TESTRUN_ID=1_kselftest-arm64
11055 23:13:53.331278 + cd /lava-12395410/0/tests/1_kselftest-arm64
11056 23:13:53.331360 ++ cat uuid
11057 23:13:53.334402 + UUID=12395410_1.6.2.3.5
11058 23:13:53.334483 + set +x
11059 23:13:53.338092 <LAVA_SIGNAL_STARTRUN 1_kselftest-arm64 12395410_1.6.2.3.5>
11060 23:13:53.338346 Received signal: <STARTRUN> 1_kselftest-arm64 12395410_1.6.2.3.5
11061 23:13:53.338416 Starting test lava.1_kselftest-arm64 (12395410_1.6.2.3.5)
11062 23:13:53.338492 Skipping test definition patterns.
11063 23:13:53.341792 + cd ./automated/linux/kselftest/
11064 23:13:53.370972 + ./kselftest.sh -c arm64 -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.66-cip11-rt6-10-g38253b8903b4/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip-gitlab -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11065 23:13:53.388043 INFO: install_deps skipped
11066 23:13:53.490524 --2023-12-27 23:13:53-- http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.66-cip11-rt6-10-g38253b8903b4/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11067 23:13:53.509042 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11068 23:13:53.638184 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11069 23:13:53.767299 HTTP request sent, awaiting response... 200 OK
11070 23:13:53.770835 Length: 2966456 (2.8M) [application/octet-stream]
11071 23:13:53.774852 Saving to: 'kselftest.tar.xz'
11072 23:13:53.775409
11073 23:13:53.775830
11074 23:13:54.026958 kselftest.tar.xz 0%[ ] 0 --.-KB/s
11075 23:13:54.285723 kselftest.tar.xz 1%[ ] 44.98K 177KB/s
11076 23:13:54.723604 kselftest.tar.xz 7%[> ] 217.50K 428KB/s
11077 23:13:54.988890 kselftest.tar.xz 27%[====> ] 808.57K 861KB/s
11078 23:13:55.070831 kselftest.tar.xz 81%[===============> ] 2.29M 1.91MB/s
11079 23:13:55.077257 kselftest.tar.xz 100%[===================>] 2.83M 2.21MB/s in 1.3s
11080 23:13:55.077352
11081 23:13:55.342427 2023-12-27 23:13:55 (2.21 MB/s) - 'kselftest.tar.xz' saved [2966456/2966456]
11082 23:13:55.342573
11083 23:14:00.804054 skiplist:
11084 23:14:00.807025 ========================================
11085 23:14:00.810393 ========================================
11086 23:14:00.849316 arm64:tags_test
11087 23:14:00.853300 arm64:run_tags_test.sh
11088 23:14:00.853383 arm64:fake_sigreturn_bad_magic
11089 23:14:00.855629 arm64:fake_sigreturn_bad_size
11090 23:14:00.859551 arm64:fake_sigreturn_bad_size_for_magic0
11091 23:14:00.862253 arm64:fake_sigreturn_duplicated_fpsimd
11092 23:14:00.865772 arm64:fake_sigreturn_misaligned_sp
11093 23:14:00.868874 arm64:fake_sigreturn_missing_fpsimd
11094 23:14:00.871877 arm64:fake_sigreturn_sme_change_vl
11095 23:14:00.875860 arm64:fake_sigreturn_sve_change_vl
11096 23:14:00.878571 arm64:mangle_pstate_invalid_compat_toggle
11097 23:14:00.883382 arm64:mangle_pstate_invalid_daif_bits
11098 23:14:00.885257 arm64:mangle_pstate_invalid_mode_el1h
11099 23:14:00.888678 arm64:mangle_pstate_invalid_mode_el1t
11100 23:14:00.892238 arm64:mangle_pstate_invalid_mode_el2h
11101 23:14:00.898403 arm64:mangle_pstate_invalid_mode_el2t
11102 23:14:00.902261 arm64:mangle_pstate_invalid_mode_el3h
11103 23:14:00.905033 arm64:mangle_pstate_invalid_mode_el3t
11104 23:14:00.905120 arm64:sme_trap_no_sm
11105 23:14:00.908354 arm64:sme_trap_non_streaming
11106 23:14:00.908441 arm64:sme_trap_za
11107 23:14:00.911686 arm64:sme_vl
11108 23:14:00.911782 arm64:ssve_regs
11109 23:14:00.915373 arm64:sve_regs
11110 23:14:00.915473 arm64:sve_vl
11111 23:14:00.919688 arm64:za_no_regs
11112 23:14:00.919790 arm64:za_regs
11113 23:14:00.919871 arm64:pac
11114 23:14:00.921715 arm64:fp-stress
11115 23:14:00.921826 arm64:sve-ptrace
11116 23:14:00.925196 arm64:sve-probe-vls
11117 23:14:00.925317 arm64:vec-syscfg
11118 23:14:00.928153 arm64:za-fork
11119 23:14:00.928272 arm64:za-ptrace
11120 23:14:00.931490 arm64:check_buffer_fill
11121 23:14:00.931624 arm64:check_child_memory
11122 23:14:00.934849 arm64:check_gcr_el1_cswitch
11123 23:14:00.938525 arm64:check_ksm_options
11124 23:14:00.938675 arm64:check_mmap_options
11125 23:14:00.941757 arm64:check_prctl
11126 23:14:00.944611 arm64:check_tags_inclusion
11127 23:14:00.944783 arm64:check_user_mem
11128 23:14:00.948437 arm64:btitest
11129 23:14:00.948636 arm64:nobtitest
11130 23:14:00.948794 arm64:hwcap
11131 23:14:00.951464 arm64:ptrace
11132 23:14:00.951778 arm64:syscall-abi
11133 23:14:00.954566 arm64:tpidr2
11134 23:14:00.958421 ============== Tests to run ===============
11135 23:14:00.958723 arm64:tags_test
11136 23:14:00.961597 arm64:run_tags_test.sh
11137 23:14:00.965280 arm64:fake_sigreturn_bad_magic
11138 23:14:00.968215 arm64:fake_sigreturn_bad_size
11139 23:14:00.971654 arm64:fake_sigreturn_bad_size_for_magic0
11140 23:14:00.974996 arm64:fake_sigreturn_duplicated_fpsimd
11141 23:14:00.977899 arm64:fake_sigreturn_misaligned_sp
11142 23:14:00.981150 arm64:fake_sigreturn_missing_fpsimd
11143 23:14:00.985093 arm64:fake_sigreturn_sme_change_vl
11144 23:14:00.988010 arm64:fake_sigreturn_sve_change_vl
11145 23:14:00.990905 arm64:mangle_pstate_invalid_compat_toggle
11146 23:14:00.994702 arm64:mangle_pstate_invalid_daif_bits
11147 23:14:00.998312 arm64:mangle_pstate_invalid_mode_el1h
11148 23:14:01.001349 arm64:mangle_pstate_invalid_mode_el1t
11149 23:14:01.004489 arm64:mangle_pstate_invalid_mode_el2h
11150 23:14:01.007930 arm64:mangle_pstate_invalid_mode_el2t
11151 23:14:01.011456 arm64:mangle_pstate_invalid_mode_el3h
11152 23:14:01.014130 arm64:mangle_pstate_invalid_mode_el3t
11153 23:14:01.014547 arm64:sme_trap_no_sm
11154 23:14:01.017973 arm64:sme_trap_non_streaming
11155 23:14:01.020875 arm64:sme_trap_za
11156 23:14:01.021293 arm64:sme_vl
11157 23:14:01.024003 arm64:ssve_regs
11158 23:14:01.024422 arm64:sve_regs
11159 23:14:01.024751 arm64:sve_vl
11160 23:14:01.027704 arm64:za_no_regs
11161 23:14:01.028130 arm64:za_regs
11162 23:14:01.031226 arm64:pac
11163 23:14:01.031856 arm64:fp-stress
11164 23:14:01.032389 arm64:sve-ptrace
11165 23:14:01.034336 arm64:sve-probe-vls
11166 23:14:01.034753 arm64:vec-syscfg
11167 23:14:01.037183 arm64:za-fork
11168 23:14:01.037600 arm64:za-ptrace
11169 23:14:01.040342 arm64:check_buffer_fill
11170 23:14:01.043647 arm64:check_child_memory
11171 23:14:01.044107 arm64:check_gcr_el1_cswitch
11172 23:14:01.047372 arm64:check_ksm_options
11173 23:14:01.050241 arm64:check_mmap_options
11174 23:14:01.050659 arm64:check_prctl
11175 23:14:01.053899 arm64:check_tags_inclusion
11176 23:14:01.057235 arm64:check_user_mem
11177 23:14:01.057808 arm64:btitest
11178 23:14:01.058159 arm64:nobtitest
11179 23:14:01.060973 arm64:hwcap
11180 23:14:01.061387 arm64:ptrace
11181 23:14:01.064125 arm64:syscall-abi
11182 23:14:01.064541 arm64:tpidr2
11183 23:14:01.067804 ===========End Tests to run ===============
11184 23:14:01.070590 shardfile-arm64 pass
11185 23:14:01.264806 <12>[ 33.970537] kselftest: Running tests in arm64
11186 23:14:01.272668 TAP version 13
11187 23:14:01.284835 1..48
11188 23:14:01.301212 # selftests: arm64: tags_test
11189 23:14:01.726386 ok 1 selftests: arm64: tags_test
11190 23:14:01.737775 # selftests: arm64: run_tags_test.sh
11191 23:14:01.796313 # --------------------
11192 23:14:01.798935 # running tags test
11193 23:14:01.799401 # --------------------
11194 23:14:01.802366 # [PASS]
11195 23:14:01.806274 ok 2 selftests: arm64: run_tags_test.sh
11196 23:14:01.818439 # selftests: arm64: fake_sigreturn_bad_magic
11197 23:14:01.891189 # Registered handlers for all signals.
11198 23:14:01.891618 # Detected MINSTKSIGSZ:4720
11199 23:14:01.893621 # Testcase initialized.
11200 23:14:01.897030 # uc context validated.
11201 23:14:01.900549 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11202 23:14:01.904030 # Handled SIG_COPYCTX
11203 23:14:01.904483 # Available space:3568
11204 23:14:01.910436 # Using badly built context - ERR: BAD MAGIC !
11205 23:14:01.916526 # SIG_OK -- SP:0xFFFFC93D5BA0 si_addr@:0xffffc93d5ba0 si_code:2 token@:0xffffc93d4940 offset:-4704
11206 23:14:01.920058 # ==>> completed. PASS(1)
11207 23:14:01.926872 # # FAKE_SIGRETURN_BAD_MAGIC :: Trigger a sigreturn with a sigframe with a bad magic
11208 23:14:01.933412 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFC93D4940
11209 23:14:01.939808 ok 3 selftests: arm64: fake_sigreturn_bad_magic
11210 23:14:01.943289 # selftests: arm64: fake_sigreturn_bad_size
11211 23:14:01.975143 # Registered handlers for all signals.
11212 23:14:01.975764 # Detected MINSTKSIGSZ:4720
11213 23:14:01.978555 # Testcase initialized.
11214 23:14:01.981651 # uc context validated.
11215 23:14:01.985407 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11216 23:14:01.988704 # Handled SIG_COPYCTX
11217 23:14:01.989161 # Available space:3568
11218 23:14:01.991574 # uc context validated.
11219 23:14:01.998030 # Using badly built context - ERR: Bad size for esr_context
11220 23:14:02.004333 # SIG_OK -- SP:0xFFFFE26ED110 si_addr@:0xffffe26ed110 si_code:2 token@:0xffffe26ebeb0 offset:-4704
11221 23:14:02.007298 # ==>> completed. PASS(1)
11222 23:14:02.014572 # # FAKE_SIGRETURN_BAD_SIZE :: Triggers a sigreturn with a overrun __reserved area
11223 23:14:02.021646 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFE26EBEB0
11224 23:14:02.027930 ok 4 selftests: arm64: fake_sigreturn_bad_size
11225 23:14:02.031236 # selftests: arm64: fake_sigreturn_bad_size_for_magic0
11226 23:14:02.051305 # Registered handlers for all signals.
11227 23:14:02.051919 # Detected MINSTKSIGSZ:4720
11228 23:14:02.054077 # Testcase initialized.
11229 23:14:02.057208 # uc context validated.
11230 23:14:02.060550 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11231 23:14:02.064183 # Handled SIG_COPYCTX
11232 23:14:02.064675 # Available space:3568
11233 23:14:02.070273 # Using badly built context - ERR: Bad size for terminator
11234 23:14:02.080388 # SIG_OK -- SP:0xFFFFC5993B30 si_addr@:0xffffc5993b30 si_code:2 token@:0xffffc59928d0 offset:-4704
11235 23:14:02.080813 # ==>> completed. PASS(1)
11236 23:14:02.090301 # # FAKE_SIGRETURN_BAD_SIZE_FOR_TERMINATOR :: Trigger a sigreturn using non-zero size terminator
11237 23:14:02.096643 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFC59928D0
11238 23:14:02.100292 ok 5 selftests: arm64: fake_sigreturn_bad_size_for_magic0
11239 23:14:02.106617 # selftests: arm64: fake_sigreturn_duplicated_fpsimd
11240 23:14:02.120962 # Registered handlers for all signals.
11241 23:14:02.121511 # Detected MINSTKSIGSZ:4720
11242 23:14:02.124136 # Testcase initialized.
11243 23:14:02.127468 # uc context validated.
11244 23:14:02.130610 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11245 23:14:02.133760 # Handled SIG_COPYCTX
11246 23:14:02.134361 # Available space:3568
11247 23:14:02.140333 # Using badly built context - ERR: Multiple FPSIMD_MAGIC
11248 23:14:02.150300 # SIG_OK -- SP:0xFFFFD6C6BBA0 si_addr@:0xffffd6c6bba0 si_code:2 token@:0xffffd6c6a940 offset:-4704
11249 23:14:02.150724 # ==>> completed. PASS(1)
11250 23:14:02.160592 # # FAKE_SIGRETURN_DUPLICATED_FPSIMD :: Triggers a sigreturn including two fpsimd_context
11251 23:14:02.167156 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFD6C6A940
11252 23:14:02.171248 ok 6 selftests: arm64: fake_sigreturn_duplicated_fpsimd
11253 23:14:02.173534 # selftests: arm64: fake_sigreturn_misaligned_sp
11254 23:14:02.207364 # Registered handlers for all signals.
11255 23:14:02.207953 # Detected MINSTKSIGSZ:4720
11256 23:14:02.210490 # Testcase initialized.
11257 23:14:02.214364 # uc context validated.
11258 23:14:02.217376 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11259 23:14:02.220703 # Handled SIG_COPYCTX
11260 23:14:02.227369 # SIG_OK -- SP:0xFFFFEA524CA3 si_addr@:0xffffea524ca3 si_code:2 token@:0xffffea524ca3 offset:0
11261 23:14:02.230388 # ==>> completed. PASS(1)
11262 23:14:02.237246 # # FAKE_SIGRETURN_MISALIGNED_SP :: Triggers a sigreturn with a misaligned sigframe
11263 23:14:02.243334 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFEA524CA3
11264 23:14:02.250080 ok 7 selftests: arm64: fake_sigreturn_misaligned_sp
11265 23:14:02.254384 # selftests: arm64: fake_sigreturn_missing_fpsimd
11266 23:14:02.290683 # Registered handlers for all signals.
11267 23:14:02.291272 # Detected MINSTKSIGSZ:4720
11268 23:14:02.293870 # Testcase initialized.
11269 23:14:02.297836 # uc context validated.
11270 23:14:02.300567 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11271 23:14:02.304309 # Handled SIG_COPYCTX
11272 23:14:02.307515 # Mangling template header. Spare space:4096
11273 23:14:02.311035 # Using badly built context - ERR: Missing FPSIMD
11274 23:14:02.320457 # SIG_OK -- SP:0xFFFFCD817C50 si_addr@:0xffffcd817c50 si_code:2 token@:0xffffcd8169f0 offset:-4704
11275 23:14:02.324236 # ==>> completed. PASS(1)
11276 23:14:02.330530 # # FAKE_SIGRETURN_MISSING_FPSIMD :: Triggers a sigreturn with a missing fpsimd_context
11277 23:14:02.336947 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFCD8169F0
11278 23:14:02.340225 ok 8 selftests: arm64: fake_sigreturn_missing_fpsimd
11279 23:14:02.347112 # selftests: arm64: fake_sigreturn_sme_change_vl
11280 23:14:02.364043 # Registered handlers for all signals.
11281 23:14:02.364599 # Detected MINSTKSIGSZ:4720
11282 23:14:02.367132 # ==>> completed. SKIP.
11283 23:14:02.374661 # # FAKE_SIGRETURN_SSVE_CHANGE :: Attempt to change Streaming SVE VL
11284 23:14:02.377168 ok 9 selftests: arm64: fake_sigreturn_sme_change_vl # SKIP
11285 23:14:02.383775 # selftests: arm64: fake_sigreturn_sve_change_vl
11286 23:14:02.446424 # Registered handlers for all signals.
11287 23:14:02.446971 # Detected MINSTKSIGSZ:4720
11288 23:14:02.449603 # ==>> completed. SKIP.
11289 23:14:02.452808 # # FAKE_SIGRETURN_SVE_CHANGE :: Attempt to change SVE VL
11290 23:14:02.459420 ok 10 selftests: arm64: fake_sigreturn_sve_change_vl # SKIP
11291 23:14:02.466696 # selftests: arm64: mangle_pstate_invalid_compat_toggle
11292 23:14:02.524073 # Registered handlers for all signals.
11293 23:14:02.524636 # Detected MINSTKSIGSZ:4720
11294 23:14:02.526416 # Testcase initialized.
11295 23:14:02.529931 # uc context validated.
11296 23:14:02.530456 # Handled SIG_TRIG
11297 23:14:02.539751 # SIG_OK -- SP:0xFFFFCF0AF250 si_addr@:0xffffcf0af250 si_code:2 token@:(nil) offset:-281474155344464
11298 23:14:02.542797 # ==>> completed. PASS(1)
11299 23:14:02.549886 # # MANGLE_PSTATE_INVALID_STATE_TOGGLE :: Mangling uc_mcontext with INVALID STATE_TOGGLE
11300 23:14:02.556499 ok 11 selftests: arm64: mangle_pstate_invalid_compat_toggle
11301 23:14:02.559611 # selftests: arm64: mangle_pstate_invalid_daif_bits
11302 23:14:02.577567 # Registered handlers for all signals.
11303 23:14:02.578109 # Detected MINSTKSIGSZ:4720
11304 23:14:02.581130 # Testcase initialized.
11305 23:14:02.583732 # uc context validated.
11306 23:14:02.584211 # Handled SIG_TRIG
11307 23:14:02.594617 # SIG_OK -- SP:0xFFFFD50B62E0 si_addr@:0xffffd50b62e0 si_code:2 token@:(nil) offset:-281474256036576
11308 23:14:02.597822 # ==>> completed. PASS(1)
11309 23:14:02.604207 # # MANGLE_PSTATE_INVALID_DAIF_BITS :: Mangling uc_mcontext with INVALID DAIF_BITS
11310 23:14:02.607406 ok 12 selftests: arm64: mangle_pstate_invalid_daif_bits
11311 23:14:02.613836 # selftests: arm64: mangle_pstate_invalid_mode_el1h
11312 23:14:02.646569 # Registered handlers for all signals.
11313 23:14:02.647112 # Detected MINSTKSIGSZ:4720
11314 23:14:02.650187 # Testcase initialized.
11315 23:14:02.653628 # uc context validated.
11316 23:14:02.654219 # Handled SIG_TRIG
11317 23:14:02.663990 # SIG_OK -- SP:0xFFFFFEAD53A0 si_addr@:0xfffffead53a0 si_code:2 token@:(nil) offset:-281474954515360
11318 23:14:02.667166 # ==>> completed. PASS(1)
11319 23:14:02.673497 # # MANGLE_PSTATE_INVALID_MODE_EL1h :: Mangling uc_mcontext INVALID MODE EL1h
11320 23:14:02.676878 ok 13 selftests: arm64: mangle_pstate_invalid_mode_el1h
11321 23:14:02.683579 # selftests: arm64: mangle_pstate_invalid_mode_el1t
11322 23:14:02.719090 # Registered handlers for all signals.
11323 23:14:02.719634 # Detected MINSTKSIGSZ:4720
11324 23:14:02.722197 # Testcase initialized.
11325 23:14:02.725388 # uc context validated.
11326 23:14:02.725851 # Handled SIG_TRIG
11327 23:14:02.735169 # SIG_OK -- SP:0xFFFFFE271160 si_addr@:0xfffffe271160 si_code:2 token@:(nil) offset:-281474945716576
11328 23:14:02.738728 # ==>> completed. PASS(1)
11329 23:14:02.745057 # # MANGLE_PSTATE_INVALID_MODE_EL1t :: Mangling uc_mcontext INVALID MODE EL1t
11330 23:14:02.748652 ok 14 selftests: arm64: mangle_pstate_invalid_mode_el1t
11331 23:14:02.754670 # selftests: arm64: mangle_pstate_invalid_mode_el2h
11332 23:14:02.801008 # Registered handlers for all signals.
11333 23:14:02.801553 # Detected MINSTKSIGSZ:4720
11334 23:14:02.804143 # Testcase initialized.
11335 23:14:02.807178 # uc context validated.
11336 23:14:02.807864 # Handled SIG_TRIG
11337 23:14:02.816926 # SIG_OK -- SP:0xFFFFEFFA77E0 si_addr@:0xffffeffa77e0 si_code:2 token@:(nil) offset:-281474707912672
11338 23:14:02.820485 # ==>> completed. PASS(1)
11339 23:14:02.827783 # # MANGLE_PSTATE_INVALID_MODE_EL2h :: Mangling uc_mcontext INVALID MODE EL2h
11340 23:14:02.830416 ok 15 selftests: arm64: mangle_pstate_invalid_mode_el2h
11341 23:14:02.837053 # selftests: arm64: mangle_pstate_invalid_mode_el2t
11342 23:14:02.868674 # Registered handlers for all signals.
11343 23:14:02.869214 # Detected MINSTKSIGSZ:4720
11344 23:14:02.871534 # Testcase initialized.
11345 23:14:02.875035 # uc context validated.
11346 23:14:02.875604 # Handled SIG_TRIG
11347 23:14:02.884795 # SIG_OK -- SP:0xFFFFC0BE47F0 si_addr@:0xffffc0be47f0 si_code:2 token@:(nil) offset:-281473915439088
11348 23:14:02.888258 # ==>> completed. PASS(1)
11349 23:14:02.894735 # # MANGLE_PSTATE_INVALID_MODE_EL2t :: Mangling uc_mcontext INVALID MODE EL2t
11350 23:14:02.898742 ok 16 selftests: arm64: mangle_pstate_invalid_mode_el2t
11351 23:14:02.904809 # selftests: arm64: mangle_pstate_invalid_mode_el3h
11352 23:14:02.935355 # Registered handlers for all signals.
11353 23:14:02.935943 # Detected MINSTKSIGSZ:4720
11354 23:14:02.938583 # Testcase initialized.
11355 23:14:02.941862 # uc context validated.
11356 23:14:02.942342 # Handled SIG_TRIG
11357 23:14:02.952380 # SIG_OK -- SP:0xFFFFFE851230 si_addr@:0xfffffe851230 si_code:2 token@:(nil) offset:-281474951877168
11358 23:14:02.955084 # ==>> completed. PASS(1)
11359 23:14:02.961904 # # MANGLE_PSTATE_INVALID_MODE_EL3h :: Mangling uc_mcontext INVALID MODE EL3h
11360 23:14:02.964869 ok 17 selftests: arm64: mangle_pstate_invalid_mode_el3h
11361 23:14:02.972356 # selftests: arm64: mangle_pstate_invalid_mode_el3t
11362 23:14:03.007935 # Registered handlers for all signals.
11363 23:14:03.008405 # Detected MINSTKSIGSZ:4720
11364 23:14:03.011194 # Testcase initialized.
11365 23:14:03.014772 # uc context validated.
11366 23:14:03.015188 # Handled SIG_TRIG
11367 23:14:03.024530 # SIG_OK -- SP:0xFFFFD8DDB5A0 si_addr@:0xffffd8ddb5a0 si_code:2 token@:(nil) offset:-281474320151968
11368 23:14:03.027729 # ==>> completed. PASS(1)
11369 23:14:03.034169 # # MANGLE_PSTATE_INVALID_MODE_EL3t :: Mangling uc_mcontext INVALID MODE EL3t
11370 23:14:03.037651 ok 18 selftests: arm64: mangle_pstate_invalid_mode_el3t
11371 23:14:03.040771 # selftests: arm64: sme_trap_no_sm
11372 23:14:03.074852 # Registered handlers for all signals.
11373 23:14:03.075410 # Detected MINSTKSIGSZ:4720
11374 23:14:03.077739 # ==>> completed. SKIP.
11375 23:14:03.088221 # # SME trap without SM :: Check that we get a SIGILL if we use streaming mode without enabling it
11376 23:14:03.090880 ok 19 selftests: arm64: sme_trap_no_sm # SKIP
11377 23:14:03.094382 # selftests: arm64: sme_trap_non_streaming
11378 23:14:03.143973 # Registered handlers for all signals.
11379 23:14:03.144398 # Detected MINSTKSIGSZ:4720
11380 23:14:03.146722 # ==>> completed. SKIP.
11381 23:14:03.156950 # # SME SM trap unsupported instruction :: Check that we get a SIGILL if we use an unsupported instruction in streaming mode
11382 23:14:03.163394 ok 20 selftests: arm64: sme_trap_non_streaming # SKIP
11383 23:14:03.166343 # selftests: arm64: sme_trap_za
11384 23:14:03.216885 # Registered handlers for all signals.
11385 23:14:03.217451 # Detected MINSTKSIGSZ:4720
11386 23:14:03.219859 # Testcase initialized.
11387 23:14:03.229903 # SIG_OK -- SP:0xFFFFE5E8BD40 si_addr@:0xaaaae3d92510 si_code:1 token@:(nil) offset:-187650943821072
11388 23:14:03.230492 # ==>> completed. PASS(1)
11389 23:14:03.239158 # # SME ZA trap :: Check that we get a SIGILL if we access ZA without enabling
11390 23:14:03.242190 ok 21 selftests: arm64: sme_trap_za
11391 23:14:03.242761 # selftests: arm64: sme_vl
11392 23:14:03.280656 # Registered handlers for all signals.
11393 23:14:03.280805 # Detected MINSTKSIGSZ:4720
11394 23:14:03.283642 # ==>> completed. SKIP.
11395 23:14:03.289920 # # SME VL :: Check that we get the right SME VL reported
11396 23:14:03.293443 ok 22 selftests: arm64: sme_vl # SKIP
11397 23:14:03.293545 # selftests: arm64: ssve_regs
11398 23:14:03.357233 # Registered handlers for all signals.
11399 23:14:03.357365 # Detected MINSTKSIGSZ:4720
11400 23:14:03.360686 # ==>> completed. SKIP.
11401 23:14:03.366800 # # Streaming SVE registers :: Check that we get the right Streaming SVE registers reported
11402 23:14:03.373551 ok 23 selftests: arm64: ssve_regs # SKIP
11403 23:14:03.373646 # selftests: arm64: sve_regs
11404 23:14:03.431382 # Registered handlers for all signals.
11405 23:14:03.432122 # Detected MINSTKSIGSZ:4720
11406 23:14:03.435182 # ==>> completed. SKIP.
11407 23:14:03.440611 # # SVE registers :: Check that we get the right SVE registers reported
11408 23:14:03.444230 ok 24 selftests: arm64: sve_regs # SKIP
11409 23:14:03.450077 # selftests: arm64: sve_vl
11410 23:14:03.504441 # Registered handlers for all signals.
11411 23:14:03.505022 # Detected MINSTKSIGSZ:4720
11412 23:14:03.507777 # ==>> completed. SKIP.
11413 23:14:03.514769 # # SVE VL :: Check that we get the right SVE VL reported
11414 23:14:03.517530 ok 25 selftests: arm64: sve_vl # SKIP
11415 23:14:03.520923 # selftests: arm64: za_no_regs
11416 23:14:03.576468 # Registered handlers for all signals.
11417 23:14:03.577020 # Detected MINSTKSIGSZ:4720
11418 23:14:03.580018 # ==>> completed. SKIP.
11419 23:14:03.586136 # # ZA registers - ZA disabled :: Check ZA context with ZA disabled
11420 23:14:03.589948 ok 26 selftests: arm64: za_no_regs # SKIP
11421 23:14:03.592874 # selftests: arm64: za_regs
11422 23:14:03.632089 # Registered handlers for all signals.
11423 23:14:03.632516 # Detected MINSTKSIGSZ:4720
11424 23:14:03.635087 # ==>> completed. SKIP.
11425 23:14:03.641714 # # ZA register :: Check that we get the right ZA registers reported
11426 23:14:03.645706 ok 27 selftests: arm64: za_regs # SKIP
11427 23:14:03.649878 # selftests: arm64: pac
11428 23:14:03.716100 # TAP version 13
11429 23:14:03.716624 # 1..7
11430 23:14:03.718922 # # Starting 7 tests from 1 test cases.
11431 23:14:03.722690 # # RUN global.corrupt_pac ...
11432 23:14:03.725758 # # SKIP PAUTH not enabled
11433 23:14:03.729268 # # OK global.corrupt_pac
11434 23:14:03.732840 # ok 1 # SKIP PAUTH not enabled
11435 23:14:03.738614 # # RUN global.pac_instructions_not_nop ...
11436 23:14:03.741799 # # SKIP PAUTH not enabled
11437 23:14:03.745564 # # OK global.pac_instructions_not_nop
11438 23:14:03.748947 # ok 2 # SKIP PAUTH not enabled
11439 23:14:03.756054 # # RUN global.pac_instructions_not_nop_generic ...
11440 23:14:03.758404 # # SKIP Generic PAUTH not enabled
11441 23:14:03.762176 # # OK global.pac_instructions_not_nop_generic
11442 23:14:03.769225 # ok 3 # SKIP Generic PAUTH not enabled
11443 23:14:03.771844 # # RUN global.single_thread_different_keys ...
11444 23:14:03.775258 # # SKIP PAUTH not enabled
11445 23:14:03.781800 # # OK global.single_thread_different_keys
11446 23:14:03.782227 # ok 4 # SKIP PAUTH not enabled
11447 23:14:03.788606 # # RUN global.exec_changed_keys ...
11448 23:14:03.791410 # # SKIP PAUTH not enabled
11449 23:14:03.794973 # # OK global.exec_changed_keys
11450 23:14:03.798744 # ok 5 # SKIP PAUTH not enabled
11451 23:14:03.801924 # # RUN global.context_switch_keep_keys ...
11452 23:14:03.804923 # # SKIP PAUTH not enabled
11453 23:14:03.811658 # # OK global.context_switch_keep_keys
11454 23:14:03.812146 # ok 6 # SKIP PAUTH not enabled
11455 23:14:03.818037 # # RUN global.context_switch_keep_keys_generic ...
11456 23:14:03.821465 # # SKIP Generic PAUTH not enabled
11457 23:14:03.828386 # # OK global.context_switch_keep_keys_generic
11458 23:14:03.831285 # ok 7 # SKIP Generic PAUTH not enabled
11459 23:14:03.834462 # # PASSED: 7 / 7 tests passed.
11460 23:14:03.838016 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:7 error:0
11461 23:14:03.841231 ok 28 selftests: arm64: pac
11462 23:14:03.845027 # selftests: arm64: fp-stress
11463 23:14:11.499106 <6>[ 44.208181] vpu: disabling
11464 23:14:11.502740 <6>[ 44.208262] vproc2: disabling
11465 23:14:11.505461 <6>[ 44.208299] vproc1: disabling
11466 23:14:11.509218 <6>[ 44.208337] vaud18: disabling
11467 23:14:11.512439 <6>[ 44.208517] vsram_others: disabling
11468 23:14:11.515870 <6>[ 44.208644] va09: disabling
11469 23:14:11.518737 <6>[ 44.208699] vsram_md: disabling
11470 23:14:11.522752 <6>[ 44.208793] Vgpu: disabling
11471 23:14:13.805135 # TAP version 13
11472 23:14:13.805271 # 1..16
11473 23:14:13.808389 # # 8 CPUs, 0 SVE VLs, 0 SME VLs
11474 23:14:13.812293 # # Will run for 10s
11475 23:14:13.812381 # # Started FPSIMD-0-0
11476 23:14:13.815087 # # Started FPSIMD-0-1
11477 23:14:13.818206 # # Started FPSIMD-1-0
11478 23:14:13.818293 # # Started FPSIMD-1-1
11479 23:14:13.821581 # # Started FPSIMD-2-0
11480 23:14:13.821669 # # Started FPSIMD-2-1
11481 23:14:13.824751 # # Started FPSIMD-3-0
11482 23:14:13.828264 # # Started FPSIMD-3-1
11483 23:14:13.828379 # # Started FPSIMD-4-0
11484 23:14:13.831198 # # Started FPSIMD-4-1
11485 23:14:13.835093 # # Started FPSIMD-5-0
11486 23:14:13.835205 # # Started FPSIMD-5-1
11487 23:14:13.837706 # # Started FPSIMD-6-0
11488 23:14:13.841274 # # Started FPSIMD-6-1
11489 23:14:13.841382 # # Started FPSIMD-7-0
11490 23:14:13.844568 # # Started FPSIMD-7-1
11491 23:14:13.848160 # # FPSIMD-0-0: Vector length: 128 bits
11492 23:14:13.851606 # # FPSIMD-0-0: PID: 1168
11493 23:14:13.854812 # # FPSIMD-1-0: Vector length: 128 bits
11494 23:14:13.855018 # # FPSIMD-1-0: PID: 1170
11495 23:14:13.858063 # # FPSIMD-1-1: Vector length: 128 bits
11496 23:14:13.862068 # # FPSIMD-1-1: PID: 1171
11497 23:14:13.864421 # # FPSIMD-2-0: Vector length: 128 bits
11498 23:14:13.867529 # # FPSIMD-2-0: PID: 1172
11499 23:14:13.870893 # # FPSIMD-0-1: Vector length: 128 bits
11500 23:14:13.874206 # # FPSIMD-0-1: PID: 1169
11501 23:14:13.877578 # # FPSIMD-4-1: Vector length: 128 bits
11502 23:14:13.880751 # # FPSIMD-4-1: PID: 1177
11503 23:14:13.884272 # # FPSIMD-5-1: Vector length: 128 bits
11504 23:14:13.884348 # # FPSIMD-5-1: PID: 1179
11505 23:14:13.887432 # # FPSIMD-3-0: Vector length: 128 bits
11506 23:14:13.890947 # # FPSIMD-3-0: PID: 1174
11507 23:14:13.893927 # # FPSIMD-4-0: Vector length: 128 bits
11508 23:14:13.897502 # # FPSIMD-4-0: PID: 1176
11509 23:14:13.900491 # # FPSIMD-6-0: Vector length: 128 bits
11510 23:14:13.904362 # # FPSIMD-6-0: PID: 1180
11511 23:14:13.906930 # # FPSIMD-5-0: Vector length: 128 bits
11512 23:14:13.907003 # # FPSIMD-5-0: PID: 1178
11513 23:14:13.913921 # # FPSIMD-3-1: Vector length: 128 bits
11514 23:14:13.914003 # # FPSIMD-3-1: PID: 1175
11515 23:14:13.917899 # # FPSIMD-6-1: Vector length: 128 bits
11516 23:14:13.920687 # # FPSIMD-6-1: PID: 1181
11517 23:14:13.923948 # # FPSIMD-2-1: Vector length: 128 bits
11518 23:14:13.926975 # # FPSIMD-2-1: PID: 1173
11519 23:14:13.930490 # # FPSIMD-7-0: Vector length: 128 bits
11520 23:14:13.933707 # # FPSIMD-7-0: PID: 1182
11521 23:14:13.936770 # # FPSIMD-7-1: Vector length: 128 bits
11522 23:14:13.936851 # # FPSIMD-7-1: PID: 1183
11523 23:14:13.939953 # # Finishing up...
11524 23:14:13.947073 # # FPSIMD-0-1: Terminated by signal 15, no error, iterations=974368, signals=10
11525 23:14:13.953328 # # FPSIMD-3-1: Terminated by signal 15, no error, iterations=1055679, signals=10
11526 23:14:13.960224 # # FPSIMD-1-1: Terminated by signal 15, no error, iterations=1833036, signals=10
11527 23:14:13.969931 # # FPSIMD-0-0: Terminated by signal 15, no error, iterations=2168872, signals=10
11528 23:14:13.976571 # # FPSIMD-2-0: Terminated by signal 15, no error, iterations=1046194, signals=10
11529 23:14:13.983097 # # FPSIMD-5-0: Terminated by signal 15, no error, iterations=1077750, signals=10
11530 23:14:13.989789 # # FPSIMD-5-1: Terminated by signal 15, no error, iterations=1305774, signals=10
11531 23:14:13.993265 # ok 1 FPSIMD-0-0
11532 23:14:13.993387 # ok 2 FPSIMD-0-1
11533 23:14:13.996693 # ok 3 FPSIMD-1-0
11534 23:14:13.996815 # ok 4 FPSIMD-1-1
11535 23:14:14.000071 # ok 5 FPSIMD-2-0
11536 23:14:14.000207 # ok 6 FPSIMD-2-1
11537 23:14:14.003912 # ok 7 FPSIMD-3-0
11538 23:14:14.004064 # ok 8 FPSIMD-3-1
11539 23:14:14.006919 # ok 9 FPSIMD-4-0
11540 23:14:14.007102 # ok 10 FPSIMD-4-1
11541 23:14:14.009931 # ok 11 FPSIMD-5-0
11542 23:14:14.010104 # ok 12 FPSIMD-5-1
11543 23:14:14.013150 # ok 13 FPSIMD-6-0
11544 23:14:14.013353 # ok 14 FPSIMD-6-1
11545 23:14:14.016039 # ok 15 FPSIMD-7-0
11546 23:14:14.016241 # ok 16 FPSIMD-7-1
11547 23:14:14.026489 # # FPSIMD-6-0: Terminated by signal 15, no error, iterations=1366047, signals=9
11548 23:14:14.033107 # # FPSIMD-4-0: Terminated by signal 15, no error, iterations=1241820, signals=10
11549 23:14:14.040154 # # FPSIMD-7-0: Terminated by signal 15, no error, iterations=1088717, signals=10
11550 23:14:14.045876 # # FPSIMD-6-1: Terminated by signal 15, no error, iterations=1413816, signals=10
11551 23:14:14.053206 # # FPSIMD-3-0: Terminated by signal 15, no error, iterations=967573, signals=9
11552 23:14:14.059640 # # FPSIMD-4-1: Terminated by signal 15, no error, iterations=922663, signals=10
11553 23:14:14.069068 # # FPSIMD-2-1: Terminated by signal 15, no error, iterations=1947344, signals=10
11554 23:14:14.076401 # # FPSIMD-7-1: Terminated by signal 15, no error, iterations=1097514, signals=10
11555 23:14:14.082240 # # FPSIMD-1-0: Terminated by signal 15, no error, iterations=1007591, signals=9
11556 23:14:14.085885 # # Totals: pass:16 fail:0 xfail:0 xpass:0 skip:0 error:0
11557 23:14:14.089073 ok 29 selftests: arm64: fp-stress
11558 23:14:14.092206 # selftests: arm64: sve-ptrace
11559 23:14:14.095529 # TAP version 13
11560 23:14:14.096066 # 1..4104
11561 23:14:14.099942 # ok 2 # SKIP SVE not available
11562 23:14:14.102282 # # Planned tests != run tests (4104 != 1)
11563 23:14:14.108997 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11564 23:14:14.112064 ok 30 selftests: arm64: sve-ptrace # SKIP
11565 23:14:14.115223 # selftests: arm64: sve-probe-vls
11566 23:14:14.115863 # TAP version 13
11567 23:14:14.116265 # 1..2
11568 23:14:14.118557 # ok 2 # SKIP SVE not available
11569 23:14:14.122635 # # Planned tests != run tests (2 != 1)
11570 23:14:14.129589 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11571 23:14:14.131982 ok 31 selftests: arm64: sve-probe-vls # SKIP
11572 23:14:14.135277 # selftests: arm64: vec-syscfg
11573 23:14:14.135847 # TAP version 13
11574 23:14:14.139415 # 1..20
11575 23:14:14.139870 # ok 1 # SKIP SVE not supported
11576 23:14:14.141930 # ok 2 # SKIP SVE not supported
11577 23:14:14.145034 # ok 3 # SKIP SVE not supported
11578 23:14:14.148708 # ok 4 # SKIP SVE not supported
11579 23:14:14.151593 # ok 5 # SKIP SVE not supported
11580 23:14:14.155424 # ok 6 # SKIP SVE not supported
11581 23:14:14.158130 # ok 7 # SKIP SVE not supported
11582 23:14:14.158550 # ok 8 # SKIP SVE not supported
11583 23:14:14.161630 # ok 9 # SKIP SVE not supported
11584 23:14:14.165619 # ok 10 # SKIP SVE not supported
11585 23:14:14.168784 # ok 11 # SKIP SME not supported
11586 23:14:14.172321 # ok 12 # SKIP SME not supported
11587 23:14:14.174782 # ok 13 # SKIP SME not supported
11588 23:14:14.177852 # ok 14 # SKIP SME not supported
11589 23:14:14.181520 # ok 15 # SKIP SME not supported
11590 23:14:14.184697 # ok 16 # SKIP SME not supported
11591 23:14:14.185219 # ok 17 # SKIP SME not supported
11592 23:14:14.187644 # ok 18 # SKIP SME not supported
11593 23:14:14.191381 # ok 19 # SKIP SME not supported
11594 23:14:14.194950 # ok 20 # SKIP SME not supported
11595 23:14:14.201139 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:20 error:0
11596 23:14:14.204251 ok 32 selftests: arm64: vec-syscfg
11597 23:14:14.204672 # selftests: arm64: za-fork
11598 23:14:14.207756 # TAP version 13
11599 23:14:14.208178 # 1..1
11600 23:14:14.210989 # # PID: 1258
11601 23:14:14.211408 # # SME support not present
11602 23:14:14.215446 # ok 0 skipped
11603 23:14:14.217938 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11604 23:14:14.221427 ok 33 selftests: arm64: za-fork
11605 23:14:14.224483 # selftests: arm64: za-ptrace
11606 23:14:14.224902 # TAP version 13
11607 23:14:14.227613 # 1..1
11608 23:14:14.228094 # ok 2 # SKIP SME not available
11609 23:14:14.234069 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11610 23:14:14.237417 ok 34 selftests: arm64: za-ptrace # SKIP
11611 23:14:14.240968 # selftests: arm64: check_buffer_fill
11612 23:14:14.244444 # # SKIP: MTE features unavailable
11613 23:14:14.247809 ok 35 selftests: arm64: check_buffer_fill # SKIP
11614 23:14:14.250353 # selftests: arm64: check_child_memory
11615 23:14:14.291284 # # SKIP: MTE features unavailable
11616 23:14:14.299156 ok 36 selftests: arm64: check_child_memory # SKIP
11617 23:14:14.313789 # selftests: arm64: check_gcr_el1_cswitch
11618 23:14:14.376661 # # SKIP: MTE features unavailable
11619 23:14:14.384576 ok 37 selftests: arm64: check_gcr_el1_cswitch # SKIP
11620 23:14:14.399047 # selftests: arm64: check_ksm_options
11621 23:14:14.453808 # # SKIP: MTE features unavailable
11622 23:14:14.461048 ok 38 selftests: arm64: check_ksm_options # SKIP
11623 23:14:14.472330 # selftests: arm64: check_mmap_options
11624 23:14:14.515156 # # SKIP: MTE features unavailable
11625 23:14:14.521798 ok 39 selftests: arm64: check_mmap_options # SKIP
11626 23:14:14.528663 # selftests: arm64: check_prctl
11627 23:14:14.563241 # TAP version 13
11628 23:14:14.563777 # 1..5
11629 23:14:14.566704 # ok 1 check_basic_read
11630 23:14:14.567126 # ok 2 NONE
11631 23:14:14.569889 # ok 3 # SKIP SYNC
11632 23:14:14.570315 # ok 4 # SKIP ASYNC
11633 23:14:14.573242 # ok 5 # SKIP SYNC+ASYNC
11634 23:14:14.576559 # # Totals: pass:2 fail:0 xfail:0 xpass:0 skip:3 error:0
11635 23:14:14.580246 ok 40 selftests: arm64: check_prctl
11636 23:14:14.586064 # selftests: arm64: check_tags_inclusion
11637 23:14:14.633249 # # SKIP: MTE features unavailable
11638 23:14:14.640043 ok 41 selftests: arm64: check_tags_inclusion # SKIP
11639 23:14:14.650655 # selftests: arm64: check_user_mem
11640 23:14:14.724521 # # SKIP: MTE features unavailable
11641 23:14:14.731265 ok 42 selftests: arm64: check_user_mem # SKIP
11642 23:14:14.744163 # selftests: arm64: btitest
11643 23:14:14.804982 # TAP version 13
11644 23:14:14.805534 # 1..18
11645 23:14:14.807800 # # HWCAP_PACA not present
11646 23:14:14.811438 # # HWCAP2_BTI not present
11647 23:14:14.814236 # # Test binary built for BTI
11648 23:14:14.817569 # ok 1 nohint_func/call_using_br_x0 # SKIP
11649 23:14:14.821539 # ok 1 nohint_func/call_using_br_x16 # SKIP
11650 23:14:14.824221 # ok 1 nohint_func/call_using_blr # SKIP
11651 23:14:14.827805 # ok 1 bti_none_func/call_using_br_x0 # SKIP
11652 23:14:14.830718 # ok 1 bti_none_func/call_using_br_x16 # SKIP
11653 23:14:14.837399 # ok 1 bti_none_func/call_using_blr # SKIP
11654 23:14:14.840633 # ok 1 bti_c_func/call_using_br_x0 # SKIP
11655 23:14:14.844077 # ok 1 bti_c_func/call_using_br_x16 # SKIP
11656 23:14:14.847163 # ok 1 bti_c_func/call_using_blr # SKIP
11657 23:14:14.851029 # ok 1 bti_j_func/call_using_br_x0 # SKIP
11658 23:14:14.853882 # ok 1 bti_j_func/call_using_br_x16 # SKIP
11659 23:14:14.857291 # ok 1 bti_j_func/call_using_blr # SKIP
11660 23:14:14.860957 # ok 1 bti_jc_func/call_using_br_x0 # SKIP
11661 23:14:14.867332 # ok 1 bti_jc_func/call_using_br_x16 # SKIP
11662 23:14:14.870510 # ok 1 bti_jc_func/call_using_blr # SKIP
11663 23:14:14.873862 # ok 1 paciasp_func/call_using_br_x0 # SKIP
11664 23:14:14.877423 # ok 1 paciasp_func/call_using_br_x16 # SKIP
11665 23:14:14.880520 # ok 1 paciasp_func/call_using_blr # SKIP
11666 23:14:14.887507 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:18 error:0
11667 23:14:14.890283 # # WARNING - EXPECTED TEST COUNT WRONG
11668 23:14:14.893744 ok 43 selftests: arm64: btitest
11669 23:14:14.896886 # selftests: arm64: nobtitest
11670 23:14:14.897352 # TAP version 13
11671 23:14:14.897721 # 1..18
11672 23:14:14.900722 # # HWCAP_PACA not present
11673 23:14:14.903491 # # HWCAP2_BTI not present
11674 23:14:14.907144 # # Test binary not built for BTI
11675 23:14:14.910362 # ok 1 nohint_func/call_using_br_x0 # SKIP
11676 23:14:14.913370 # ok 1 nohint_func/call_using_br_x16 # SKIP
11677 23:14:14.917398 # ok 1 nohint_func/call_using_blr # SKIP
11678 23:14:14.920219 # ok 1 bti_none_func/call_using_br_x0 # SKIP
11679 23:14:14.926605 # ok 1 bti_none_func/call_using_br_x16 # SKIP
11680 23:14:14.929899 # ok 1 bti_none_func/call_using_blr # SKIP
11681 23:14:14.933186 # ok 1 bti_c_func/call_using_br_x0 # SKIP
11682 23:14:14.936178 # ok 1 bti_c_func/call_using_br_x16 # SKIP
11683 23:14:14.939886 # ok 1 bti_c_func/call_using_blr # SKIP
11684 23:14:14.942924 # ok 1 bti_j_func/call_using_br_x0 # SKIP
11685 23:14:14.946831 # ok 1 bti_j_func/call_using_br_x16 # SKIP
11686 23:14:14.953078 # ok 1 bti_j_func/call_using_blr # SKIP
11687 23:14:14.956875 # ok 1 bti_jc_func/call_using_br_x0 # SKIP
11688 23:14:14.959790 # ok 1 bti_jc_func/call_using_br_x16 # SKIP
11689 23:14:14.963108 # ok 1 bti_jc_func/call_using_blr # SKIP
11690 23:14:14.966336 # ok 1 paciasp_func/call_using_br_x0 # SKIP
11691 23:14:14.969375 # ok 1 paciasp_func/call_using_br_x16 # SKIP
11692 23:14:14.975947 # ok 1 paciasp_func/call_using_blr # SKIP
11693 23:14:14.979283 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:18 error:0
11694 23:14:14.982881 # # WARNING - EXPECTED TEST COUNT WRONG
11695 23:14:14.986821 ok 44 selftests: arm64: nobtitest
11696 23:14:14.989471 # selftests: arm64: hwcap
11697 23:14:14.989896 # TAP version 13
11698 23:14:14.990229 # 1..28
11699 23:14:14.992671 # ok 1 cpuinfo_match_RNG
11700 23:14:14.995831 # # SIGILL reported for RNG
11701 23:14:14.998936 # ok 2 # SKIP sigill_RNG
11702 23:14:14.999358 # ok 3 cpuinfo_match_SME
11703 23:14:15.002156 # ok 4 sigill_SME
11704 23:14:15.002581 # ok 5 cpuinfo_match_SVE
11705 23:14:15.006121 # ok 6 sigill_SVE
11706 23:14:15.009132 # ok 7 cpuinfo_match_SVE 2
11707 23:14:15.012072 # # SIGILL reported for SVE 2
11708 23:14:15.012494 # ok 8 # SKIP sigill_SVE 2
11709 23:14:15.015477 # ok 9 cpuinfo_match_SVE AES
11710 23:14:15.018978 # # SIGILL reported for SVE AES
11711 23:14:15.022258 # ok 10 # SKIP sigill_SVE AES
11712 23:14:15.025236 # ok 11 cpuinfo_match_SVE2 PMULL
11713 23:14:15.028603 # # SIGILL reported for SVE2 PMULL
11714 23:14:15.029026 # ok 12 # SKIP sigill_SVE2 PMULL
11715 23:14:15.032483 # ok 13 cpuinfo_match_SVE2 BITPERM
11716 23:14:15.035221 # # SIGILL reported for SVE2 BITPERM
11717 23:14:15.038276 # ok 14 # SKIP sigill_SVE2 BITPERM
11718 23:14:15.041851 # ok 15 cpuinfo_match_SVE2 SHA3
11719 23:14:15.045157 # # SIGILL reported for SVE2 SHA3
11720 23:14:15.048978 # ok 16 # SKIP sigill_SVE2 SHA3
11721 23:14:15.051661 # ok 17 cpuinfo_match_SVE2 SM4
11722 23:14:15.055034 # # SIGILL reported for SVE2 SM4
11723 23:14:15.058673 # ok 18 # SKIP sigill_SVE2 SM4
11724 23:14:15.061808 # ok 19 cpuinfo_match_SVE2 I8MM
11725 23:14:15.062246 # # SIGILL reported for SVE2 I8MM
11726 23:14:15.064897 # ok 20 # SKIP sigill_SVE2 I8MM
11727 23:14:15.068325 # ok 21 cpuinfo_match_SVE2 F32MM
11728 23:14:15.071719 # # SIGILL reported for SVE2 F32MM
11729 23:14:15.074659 # ok 22 # SKIP sigill_SVE2 F32MM
11730 23:14:15.077912 # ok 23 cpuinfo_match_SVE2 F64MM
11731 23:14:15.081175 # # SIGILL reported for SVE2 F64MM
11732 23:14:15.084605 # ok 24 # SKIP sigill_SVE2 F64MM
11733 23:14:15.087815 # ok 25 cpuinfo_match_SVE2 BF16
11734 23:14:15.091594 # # SIGILL reported for SVE2 BF16
11735 23:14:15.092126 # ok 26 # SKIP sigill_SVE2 BF16
11736 23:14:15.094332 # ok 27 cpuinfo_match_SVE2 EBF16
11737 23:14:15.097737 # ok 28 # SKIP sigill_SVE2 EBF16
11738 23:14:15.104340 # # Totals: pass:16 fail:0 xfail:0 xpass:0 skip:12 error:0
11739 23:14:15.108207 ok 45 selftests: arm64: hwcap
11740 23:14:15.108631 # selftests: arm64: ptrace
11741 23:14:15.111787 # TAP version 13
11742 23:14:15.112208 # 1..7
11743 23:14:15.114132 # # Parent is 1500, child is 1501
11744 23:14:15.117621 # ok 1 read_tpidr_one
11745 23:14:15.118040 # ok 2 write_tpidr_one
11746 23:14:15.120634 # ok 3 verify_tpidr_one
11747 23:14:15.121052 # ok 4 count_tpidrs
11748 23:14:15.124230 # ok 5 tpidr2_write
11749 23:14:15.127795 # ok 6 tpidr2_read
11750 23:14:15.128315 # ok 7 write_tpidr_only
11751 23:14:15.133999 # # Totals: pass:7 fail:0 xfail:0 xpass:0 skip:0 error:0
11752 23:14:15.138045 ok 46 selftests: arm64: ptrace
11753 23:14:15.138582 # selftests: arm64: syscall-abi
11754 23:14:15.183162 # TAP version 13
11755 23:14:15.183772 # 1..2
11756 23:14:15.186619 # ok 1 getpid() FPSIMD
11757 23:14:15.189834 # ok 2 sched_yield() FPSIMD
11758 23:14:15.192718 # # Totals: pass:2 fail:0 xfail:0 xpass:0 skip:0 error:0
11759 23:14:15.195930 ok 47 selftests: arm64: syscall-abi
11760 23:14:15.201667 # selftests: arm64: tpidr2
11761 23:14:15.264341 # TAP version 13
11762 23:14:15.264933 # 1..5
11763 23:14:15.267538 # # PID: 1537
11764 23:14:15.268057 # # SME support not present
11765 23:14:15.270666 # ok 0 skipped, TPIDR2 not supported
11766 23:14:15.273913 # ok 1 skipped, TPIDR2 not supported
11767 23:14:15.277068 # ok 2 skipped, TPIDR2 not supported
11768 23:14:15.280356 # ok 3 skipped, TPIDR2 not supported
11769 23:14:15.283225 # ok 4 skipped, TPIDR2 not supported
11770 23:14:15.290619 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:5 error:0
11771 23:14:15.293915 ok 48 selftests: arm64: tpidr2
11772 23:14:15.912634 arm64_tags_test pass
11773 23:14:15.915659 arm64_run_tags_test_sh pass
11774 23:14:15.918624 arm64_fake_sigreturn_bad_magic pass
11775 23:14:15.921940 arm64_fake_sigreturn_bad_size pass
11776 23:14:15.925384 arm64_fake_sigreturn_bad_size_for_magic0 pass
11777 23:14:15.928197 arm64_fake_sigreturn_duplicated_fpsimd pass
11778 23:14:15.931896 arm64_fake_sigreturn_misaligned_sp pass
11779 23:14:15.935423 arm64_fake_sigreturn_missing_fpsimd pass
11780 23:14:15.938707 arm64_fake_sigreturn_sme_change_vl skip
11781 23:14:15.944817 arm64_fake_sigreturn_sve_change_vl skip
11782 23:14:15.948097 arm64_mangle_pstate_invalid_compat_toggle pass
11783 23:14:15.951967 arm64_mangle_pstate_invalid_daif_bits pass
11784 23:14:15.954503 arm64_mangle_pstate_invalid_mode_el1h pass
11785 23:14:15.958420 arm64_mangle_pstate_invalid_mode_el1t pass
11786 23:14:15.961788 arm64_mangle_pstate_invalid_mode_el2h pass
11787 23:14:15.968261 arm64_mangle_pstate_invalid_mode_el2t pass
11788 23:14:15.972080 arm64_mangle_pstate_invalid_mode_el3h pass
11789 23:14:15.974395 arm64_mangle_pstate_invalid_mode_el3t pass
11790 23:14:15.978019 arm64_sme_trap_no_sm skip
11791 23:14:15.981147 arm64_sme_trap_non_streaming skip
11792 23:14:15.981716 arm64_sme_trap_za pass
11793 23:14:15.984300 arm64_sme_vl skip
11794 23:14:15.984956 arm64_ssve_regs skip
11795 23:14:15.988507 arm64_sve_regs skip
11796 23:14:15.988964 arm64_sve_vl skip
11797 23:14:15.991354 arm64_za_no_regs skip
11798 23:14:15.991969 arm64_za_regs skip
11799 23:14:15.994187 arm64_pac_pauth_not_enabled skip
11800 23:14:15.998289 arm64_pac_pauth_not_enabled skip
11801 23:14:16.001371 arm64_pac_generic_pauth_not_enabled skip
11802 23:14:16.004466 arm64_pac_pauth_not_enabled skip
11803 23:14:16.007312 arm64_pac_pauth_not_enabled skip
11804 23:14:16.011043 arm64_pac_pauth_not_enabled skip
11805 23:14:16.014063 arm64_pac_generic_pauth_not_enabled skip
11806 23:14:16.014521 arm64_pac pass
11807 23:14:16.018332 arm64_fp-stress_FPSIMD-0-0 pass
11808 23:14:16.020556 arm64_fp-stress_FPSIMD-0-1 pass
11809 23:14:16.024484 arm64_fp-stress_FPSIMD-1-0 pass
11810 23:14:16.028165 arm64_fp-stress_FPSIMD-1-1 pass
11811 23:14:16.030874 arm64_fp-stress_FPSIMD-2-0 pass
11812 23:14:16.034473 arm64_fp-stress_FPSIMD-2-1 pass
11813 23:14:16.037300 arm64_fp-stress_FPSIMD-3-0 pass
11814 23:14:16.037763 arm64_fp-stress_FPSIMD-3-1 pass
11815 23:14:16.040662 arm64_fp-stress_FPSIMD-4-0 pass
11816 23:14:16.044260 arm64_fp-stress_FPSIMD-4-1 pass
11817 23:14:16.047790 arm64_fp-stress_FPSIMD-5-0 pass
11818 23:14:16.050524 arm64_fp-stress_FPSIMD-5-1 pass
11819 23:14:16.053818 arm64_fp-stress_FPSIMD-6-0 pass
11820 23:14:16.057107 arm64_fp-stress_FPSIMD-6-1 pass
11821 23:14:16.060274 arm64_fp-stress_FPSIMD-7-0 pass
11822 23:14:16.060732 arm64_fp-stress_FPSIMD-7-1 pass
11823 23:14:16.063739 arm64_fp-stress pass
11824 23:14:16.067013 arm64_sve-ptrace_sve_not_available skip
11825 23:14:16.070189 arm64_sve-ptrace skip
11826 23:14:16.073309 arm64_sve-probe-vls_sve_not_available skip
11827 23:14:16.073821 arm64_sve-probe-vls skip
11828 23:14:16.080429 arm64_vec-syscfg_sve_not_supported skip
11829 23:14:16.084042 arm64_vec-syscfg_sve_not_supported skip
11830 23:14:16.087599 arm64_vec-syscfg_sve_not_supported skip
11831 23:14:16.089943 arm64_vec-syscfg_sve_not_supported skip
11832 23:14:16.093537 arm64_vec-syscfg_sve_not_supported skip
11833 23:14:16.098007 arm64_vec-syscfg_sve_not_supported skip
11834 23:14:16.100323 arm64_vec-syscfg_sve_not_supported skip
11835 23:14:16.103854 arm64_vec-syscfg_sve_not_supported skip
11836 23:14:16.106723 arm64_vec-syscfg_sve_not_supported skip
11837 23:14:16.109937 arm64_vec-syscfg_sve_not_supported skip
11838 23:14:16.113148 arm64_vec-syscfg_sme_not_supported skip
11839 23:14:16.116844 arm64_vec-syscfg_sme_not_supported skip
11840 23:14:16.120056 arm64_vec-syscfg_sme_not_supported skip
11841 23:14:16.126527 arm64_vec-syscfg_sme_not_supported skip
11842 23:14:16.130470 arm64_vec-syscfg_sme_not_supported skip
11843 23:14:16.133101 arm64_vec-syscfg_sme_not_supported skip
11844 23:14:16.136481 arm64_vec-syscfg_sme_not_supported skip
11845 23:14:16.139754 arm64_vec-syscfg_sme_not_supported skip
11846 23:14:16.142985 arm64_vec-syscfg_sme_not_supported skip
11847 23:14:16.146550 arm64_vec-syscfg_sme_not_supported skip
11848 23:14:16.149718 arm64_vec-syscfg pass
11849 23:14:16.150275 arm64_za-fork_skipped pass
11850 23:14:16.153056 arm64_za-fork pass
11851 23:14:16.156288 arm64_za-ptrace_sme_not_available skip
11852 23:14:16.159774 arm64_za-ptrace skip
11853 23:14:16.160407 arm64_check_buffer_fill skip
11854 23:14:16.162988 arm64_check_child_memory skip
11855 23:14:16.165994 arm64_check_gcr_el1_cswitch skip
11856 23:14:16.169595 arm64_check_ksm_options skip
11857 23:14:16.173204 arm64_check_mmap_options skip
11858 23:14:16.176565 arm64_check_prctl_check_basic_read pass
11859 23:14:16.177034 arm64_check_prctl_NONE pass
11860 23:14:16.179415 arm64_check_prctl_sync skip
11861 23:14:16.182202 arm64_check_prctl_async skip
11862 23:14:16.186022 arm64_check_prctl_sync_async skip
11863 23:14:16.189338 arm64_check_prctl pass
11864 23:14:16.189906 arm64_check_tags_inclusion skip
11865 23:14:16.192522 arm64_check_user_mem skip
11866 23:14:16.195473 arm64_btitest_nohint_func_call_using_br_x0 skip
11867 23:14:16.202835 arm64_btitest_nohint_func_call_using_br_x16 skip
11868 23:14:16.206082 arm64_btitest_nohint_func_call_using_blr skip
11869 23:14:16.208960 arm64_btitest_bti_none_func_call_using_br_x0 skip
11870 23:14:16.215953 arm64_btitest_bti_none_func_call_using_br_x16 skip
11871 23:14:16.218880 arm64_btitest_bti_none_func_call_using_blr skip
11872 23:14:16.222489 arm64_btitest_bti_c_func_call_using_br_x0 skip
11873 23:14:16.229360 arm64_btitest_bti_c_func_call_using_br_x16 skip
11874 23:14:16.232220 arm64_btitest_bti_c_func_call_using_blr skip
11875 23:14:16.236119 arm64_btitest_bti_j_func_call_using_br_x0 skip
11876 23:14:16.238701 arm64_btitest_bti_j_func_call_using_br_x16 skip
11877 23:14:16.245553 arm64_btitest_bti_j_func_call_using_blr skip
11878 23:14:16.248396 arm64_btitest_bti_jc_func_call_using_br_x0 skip
11879 23:14:16.251651 arm64_btitest_bti_jc_func_call_using_br_x16 skip
11880 23:14:16.255495 arm64_btitest_bti_jc_func_call_using_blr skip
11881 23:14:16.261595 arm64_btitest_paciasp_func_call_using_br_x0 skip
11882 23:14:16.265768 arm64_btitest_paciasp_func_call_using_br_x16 skip
11883 23:14:16.268387 arm64_btitest_paciasp_func_call_using_blr skip
11884 23:14:16.271607 arm64_btitest pass
11885 23:14:16.275107 arm64_nobtitest_nohint_func_call_using_br_x0 skip
11886 23:14:16.281963 arm64_nobtitest_nohint_func_call_using_br_x16 skip
11887 23:14:16.284527 arm64_nobtitest_nohint_func_call_using_blr skip
11888 23:14:16.288367 arm64_nobtitest_bti_none_func_call_using_br_x0 skip
11889 23:14:16.294553 arm64_nobtitest_bti_none_func_call_using_br_x16 skip
11890 23:14:16.298180 arm64_nobtitest_bti_none_func_call_using_blr skip
11891 23:14:16.301304 arm64_nobtitest_bti_c_func_call_using_br_x0 skip
11892 23:14:16.307729 arm64_nobtitest_bti_c_func_call_using_br_x16 skip
11893 23:14:16.311137 arm64_nobtitest_bti_c_func_call_using_blr skip
11894 23:14:16.314922 arm64_nobtitest_bti_j_func_call_using_br_x0 skip
11895 23:14:16.320756 arm64_nobtitest_bti_j_func_call_using_br_x16 skip
11896 23:14:16.324182 arm64_nobtitest_bti_j_func_call_using_blr skip
11897 23:14:16.327719 arm64_nobtitest_bti_jc_func_call_using_br_x0 skip
11898 23:14:16.334713 arm64_nobtitest_bti_jc_func_call_using_br_x16 skip
11899 23:14:16.337943 arm64_nobtitest_bti_jc_func_call_using_blr skip
11900 23:14:16.340785 arm64_nobtitest_paciasp_func_call_using_br_x0 skip
11901 23:14:16.347582 arm64_nobtitest_paciasp_func_call_using_br_x16 skip
11902 23:14:16.350863 arm64_nobtitest_paciasp_func_call_using_blr skip
11903 23:14:16.351283 arm64_nobtitest pass
11904 23:14:16.354105 arm64_hwcap_cpuinfo_match_RNG pass
11905 23:14:16.357306 arm64_hwcap_sigill_rng skip
11906 23:14:16.360894 arm64_hwcap_cpuinfo_match_SME pass
11907 23:14:16.364216 arm64_hwcap_sigill_SME pass
11908 23:14:16.367635 arm64_hwcap_cpuinfo_match_SVE pass
11909 23:14:16.370450 arm64_hwcap_sigill_SVE pass
11910 23:14:16.373920 arm64_hwcap_cpuinfo_match_SVE_2 pass
11911 23:14:16.374300 arm64_hwcap_sigill_sve_2 skip
11912 23:14:16.377356 arm64_hwcap_cpuinfo_match_SVE_AES pass
11913 23:14:16.380760 arm64_hwcap_sigill_sve_aes skip
11914 23:14:16.384273 arm64_hwcap_cpuinfo_match_SVE2_PMULL pass
11915 23:14:16.387058 arm64_hwcap_sigill_sve2_pmull skip
11916 23:14:16.393661 arm64_hwcap_cpuinfo_match_SVE2_BITPERM pass
11917 23:14:16.396860 arm64_hwcap_sigill_sve2_bitperm skip
11918 23:14:16.400044 arm64_hwcap_cpuinfo_match_SVE2_SHA3 pass
11919 23:14:16.403566 arm64_hwcap_sigill_sve2_sha3 skip
11920 23:14:16.407410 arm64_hwcap_cpuinfo_match_SVE2_SM4 pass
11921 23:14:16.409919 arm64_hwcap_sigill_sve2_sm4 skip
11922 23:14:16.413782 arm64_hwcap_cpuinfo_match_SVE2_I8MM pass
11923 23:14:16.417027 arm64_hwcap_sigill_sve2_i8mm skip
11924 23:14:16.420184 arm64_hwcap_cpuinfo_match_SVE2_F32MM pass
11925 23:14:16.424028 arm64_hwcap_sigill_sve2_f32mm skip
11926 23:14:16.426710 arm64_hwcap_cpuinfo_match_SVE2_F64MM pass
11927 23:14:16.429642 arm64_hwcap_sigill_sve2_f64mm skip
11928 23:14:16.432986 arm64_hwcap_cpuinfo_match_SVE2_BF16 pass
11929 23:14:16.437227 arm64_hwcap_sigill_sve2_bf16 skip
11930 23:14:16.439645 arm64_hwcap_cpuinfo_match_SVE2_EBF16 pass
11931 23:14:16.443328 arm64_hwcap_sigill_sve2_ebf16 skip
11932 23:14:16.443873 arm64_hwcap pass
11933 23:14:16.446522 arm64_ptrace_read_tpidr_one pass
11934 23:14:16.450070 arm64_ptrace_write_tpidr_one pass
11935 23:14:16.453172 arm64_ptrace_verify_tpidr_one pass
11936 23:14:16.456262 arm64_ptrace_count_tpidrs pass
11937 23:14:16.460036 arm64_ptrace_tpidr2_write pass
11938 23:14:16.462941 arm64_ptrace_tpidr2_read pass
11939 23:14:16.466467 arm64_ptrace_write_tpidr_only pass
11940 23:14:16.466941 arm64_ptrace pass
11941 23:14:16.469315 arm64_syscall-abi_getpid_FPSIMD pass
11942 23:14:16.473148 arm64_syscall-abi_sched_yield_FPSIMD pass
11943 23:14:16.476016 arm64_syscall-abi pass
11944 23:14:16.479817 arm64_tpidr2_skipped_TPIDR2_not_supported pass
11945 23:14:16.483271 arm64_tpidr2_skipped_TPIDR2_not_supported pass
11946 23:14:16.489263 arm64_tpidr2_skipped_TPIDR2_not_supported pass
11947 23:14:16.492939 arm64_tpidr2_skipped_TPIDR2_not_supported pass
11948 23:14:16.496132 arm64_tpidr2_skipped_TPIDR2_not_supported pass
11949 23:14:16.499156 arm64_tpidr2 pass
11950 23:14:16.502635 + ../../utils/send-to-lava.sh ./output/result.txt
11951 23:14:16.509173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-arm64 RESULT=pass>
11952 23:14:16.509996 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-arm64 RESULT=pass
11954 23:14:16.512772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tags_test RESULT=pass>
11955 23:14:16.513513 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tags_test RESULT=pass
11957 23:14:16.519372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_run_tags_test_sh RESULT=pass>
11958 23:14:16.520178 Received signal: <TESTCASE> TEST_CASE_ID=arm64_run_tags_test_sh RESULT=pass
11960 23:14:16.525362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_magic RESULT=pass>
11961 23:14:16.526062 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_magic RESULT=pass
11963 23:14:16.532417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_size RESULT=pass>
11964 23:14:16.533093 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_size RESULT=pass
11966 23:14:16.570244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_size_for_magic0 RESULT=pass>
11967 23:14:16.570984 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_size_for_magic0 RESULT=pass
11969 23:14:16.617919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_duplicated_fpsimd RESULT=pass>
11970 23:14:16.618666 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_duplicated_fpsimd RESULT=pass
11972 23:14:16.666442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_misaligned_sp RESULT=pass>
11973 23:14:16.667253 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_misaligned_sp RESULT=pass
11975 23:14:16.720638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_missing_fpsimd RESULT=pass>
11976 23:14:16.721345 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_missing_fpsimd RESULT=pass
11978 23:14:16.774767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_sme_change_vl RESULT=skip>
11979 23:14:16.775027 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_sme_change_vl RESULT=skip
11981 23:14:16.824775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_sve_change_vl RESULT=skip>
11982 23:14:16.825043 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_sve_change_vl RESULT=skip
11984 23:14:16.874643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_compat_toggle RESULT=pass>
11985 23:14:16.875187 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_compat_toggle RESULT=pass
11987 23:14:16.925227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_daif_bits RESULT=pass>
11988 23:14:16.925999 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_daif_bits RESULT=pass
11990 23:14:16.969473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1h RESULT=pass>
11991 23:14:16.969728 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1h RESULT=pass
11993 23:14:17.016353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1t RESULT=pass>
11994 23:14:17.016610 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1t RESULT=pass
11996 23:14:17.051443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2h RESULT=pass>
11997 23:14:17.051708 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2h RESULT=pass
11999 23:14:17.095297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2t RESULT=pass>
12000 23:14:17.095550 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2t RESULT=pass
12002 23:14:17.143182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3h RESULT=pass>
12003 23:14:17.143444 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3h RESULT=pass
12005 23:14:17.192692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3t RESULT=pass>
12006 23:14:17.192962 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3t RESULT=pass
12008 23:14:17.236213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_no_sm RESULT=skip>
12009 23:14:17.236483 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_no_sm RESULT=skip
12011 23:14:17.286888 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_non_streaming RESULT=skip
12013 23:14:17.289771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_non_streaming RESULT=skip>
12014 23:14:17.335728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_za RESULT=pass>
12015 23:14:17.335994 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_za RESULT=pass
12017 23:14:17.374903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_vl RESULT=skip>
12018 23:14:17.375153 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_vl RESULT=skip
12020 23:14:17.424376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ssve_regs RESULT=skip>
12021 23:14:17.424645 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ssve_regs RESULT=skip
12023 23:14:17.473162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve_regs RESULT=skip>
12024 23:14:17.473903 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve_regs RESULT=skip
12026 23:14:17.522449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve_vl RESULT=skip>
12027 23:14:17.523186 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve_vl RESULT=skip
12029 23:14:17.571388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za_no_regs RESULT=skip>
12030 23:14:17.571657 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za_no_regs RESULT=skip
12032 23:14:17.614767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za_regs RESULT=skip>
12033 23:14:17.615244 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za_regs RESULT=skip
12035 23:14:17.665535 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip
12037 23:14:17.668477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip>
12038 23:14:17.713160 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip
12040 23:14:17.715988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip>
12041 23:14:17.758114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_generic_pauth_not_enabled RESULT=skip>
12042 23:14:17.758790 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_generic_pauth_not_enabled RESULT=skip
12044 23:14:17.807158 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip
12046 23:14:17.809514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip>
12047 23:14:17.856311 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip
12049 23:14:17.859203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip>
12050 23:14:17.905944 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip
12052 23:14:17.908260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip>
12053 23:14:17.959978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_generic_pauth_not_enabled RESULT=skip>
12054 23:14:17.960741 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_generic_pauth_not_enabled RESULT=skip
12056 23:14:18.002770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac RESULT=pass>
12057 23:14:18.003455 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac RESULT=pass
12059 23:14:18.052290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-0 RESULT=pass>
12060 23:14:18.052972 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-0 RESULT=pass
12062 23:14:18.098432 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-1 RESULT=pass
12064 23:14:18.100794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-1 RESULT=pass>
12065 23:14:18.146603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-0 RESULT=pass>
12066 23:14:18.147279 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-0 RESULT=pass
12068 23:14:18.198113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-1 RESULT=pass>
12069 23:14:18.198854 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-1 RESULT=pass
12071 23:14:18.247147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-0 RESULT=pass>
12072 23:14:18.247874 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-0 RESULT=pass
12074 23:14:18.301717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-1 RESULT=pass>
12075 23:14:18.302408 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-1 RESULT=pass
12077 23:14:18.348715 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-0 RESULT=pass
12079 23:14:18.351848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-0 RESULT=pass>
12080 23:14:18.395775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-1 RESULT=pass>
12081 23:14:18.396029 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-1 RESULT=pass
12083 23:14:18.435385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-0 RESULT=pass>
12084 23:14:18.435637 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-0 RESULT=pass
12086 23:14:18.476005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-1 RESULT=pass>
12087 23:14:18.476266 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-1 RESULT=pass
12089 23:14:18.519343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-0 RESULT=pass>
12090 23:14:18.520059 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-0 RESULT=pass
12092 23:14:18.569520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-1 RESULT=pass>
12093 23:14:18.570197 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-1 RESULT=pass
12095 23:14:18.619367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-0 RESULT=pass>
12096 23:14:18.620089 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-0 RESULT=pass
12098 23:14:18.667832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-1 RESULT=pass>
12099 23:14:18.668510 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-1 RESULT=pass
12101 23:14:18.716573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-0 RESULT=pass>
12102 23:14:18.717311 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-0 RESULT=pass
12104 23:14:18.767317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-1 RESULT=pass>
12105 23:14:18.768062 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-1 RESULT=pass
12107 23:14:18.810231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress RESULT=pass>
12108 23:14:18.810935 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress RESULT=pass
12110 23:14:18.860469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_sve_not_available RESULT=skip>
12111 23:14:18.861149 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_sve_not_available RESULT=skip
12113 23:14:18.909316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace RESULT=skip>
12114 23:14:18.910047 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace RESULT=skip
12116 23:14:18.965300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls_sve_not_available RESULT=skip>
12117 23:14:18.965559 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls_sve_not_available RESULT=skip
12119 23:14:19.004059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls RESULT=skip>
12120 23:14:19.004313 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls RESULT=skip
12122 23:14:19.047785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12123 23:14:19.048057 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12125 23:14:19.081466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12126 23:14:19.081830 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12128 23:14:19.125202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12129 23:14:19.125875 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12131 23:14:19.168927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12132 23:14:19.169185 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12134 23:14:19.209963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12135 23:14:19.210218 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12137 23:14:19.244952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12138 23:14:19.245206 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12140 23:14:19.280212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12141 23:14:19.280463 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12143 23:14:19.322636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12144 23:14:19.322907 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12146 23:14:19.366002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12147 23:14:19.366768 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12149 23:14:19.418022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12150 23:14:19.418693 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12152 23:14:19.469257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12153 23:14:19.469995 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12155 23:14:19.524216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12156 23:14:19.524962 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12158 23:14:19.577746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12159 23:14:19.578022 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12161 23:14:19.617116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12162 23:14:19.617848 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12164 23:14:19.666465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12165 23:14:19.667201 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12167 23:14:19.708219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12168 23:14:19.708997 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12170 23:14:19.756566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12171 23:14:19.756822 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12173 23:14:19.802466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12174 23:14:19.802741 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12176 23:14:19.844616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12177 23:14:19.845313 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12179 23:14:19.882655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12180 23:14:19.883335 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12182 23:14:19.933312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg RESULT=pass>
12183 23:14:19.934140 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg RESULT=pass
12185 23:14:19.987421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-fork_skipped RESULT=pass>
12186 23:14:19.988142 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-fork_skipped RESULT=pass
12188 23:14:20.037208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-fork RESULT=pass>
12189 23:14:20.037944 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-fork RESULT=pass
12191 23:14:20.092396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_sme_not_available RESULT=skip>
12192 23:14:20.093127 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_sme_not_available RESULT=skip
12194 23:14:20.137500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace RESULT=skip>
12195 23:14:20.138230 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace RESULT=skip
12197 23:14:20.183720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill RESULT=skip>
12198 23:14:20.184090 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill RESULT=skip
12200 23:14:20.228746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory RESULT=skip>
12201 23:14:20.229028 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory RESULT=skip
12203 23:14:20.268847 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_gcr_el1_cswitch RESULT=skip
12205 23:14:20.271721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_gcr_el1_cswitch RESULT=skip>
12206 23:14:20.308494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_ksm_options RESULT=skip>
12207 23:14:20.308750 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_ksm_options RESULT=skip
12209 23:14:20.344276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options RESULT=skip>
12210 23:14:20.344526 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options RESULT=skip
12212 23:14:20.397965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_check_basic_read RESULT=pass>
12213 23:14:20.398228 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_check_basic_read RESULT=pass
12215 23:14:20.428669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_NONE RESULT=pass>
12216 23:14:20.428924 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_NONE RESULT=pass
12218 23:14:20.468840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_sync RESULT=skip>
12219 23:14:20.469094 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_sync RESULT=skip
12221 23:14:20.505255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_async RESULT=skip>
12222 23:14:20.505509 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_async RESULT=skip
12224 23:14:20.541317 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_sync_async RESULT=skip
12226 23:14:20.544471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_sync_async RESULT=skip>
12227 23:14:20.580074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl RESULT=pass>
12228 23:14:20.580328 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl RESULT=pass
12230 23:14:20.622427 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_tags_inclusion RESULT=skip
12232 23:14:20.625778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_tags_inclusion RESULT=skip>
12233 23:14:20.660980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem RESULT=skip>
12234 23:14:20.661241 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem RESULT=skip
12236 23:14:20.713549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x0 RESULT=skip>
12237 23:14:20.714285 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x0 RESULT=skip
12239 23:14:20.765320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x16 RESULT=skip>
12240 23:14:20.766053 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x16 RESULT=skip
12242 23:14:20.817422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_blr RESULT=skip>
12243 23:14:20.818181 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_blr RESULT=skip
12245 23:14:20.867889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x0 RESULT=skip>
12246 23:14:20.868631 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x0 RESULT=skip
12248 23:14:20.907888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x16 RESULT=skip>
12249 23:14:20.908162 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x16 RESULT=skip
12251 23:14:20.953329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_blr RESULT=skip>
12252 23:14:20.953901 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_blr RESULT=skip
12254 23:14:20.997786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x0 RESULT=skip>
12255 23:14:20.998040 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x0 RESULT=skip
12257 23:14:21.041235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x16 RESULT=skip>
12258 23:14:21.041498 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x16 RESULT=skip
12260 23:14:21.088799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_blr RESULT=skip>
12261 23:14:21.089082 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_blr RESULT=skip
12263 23:14:21.133931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x0 RESULT=skip>
12264 23:14:21.134199 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x0 RESULT=skip
12266 23:14:21.178212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x16 RESULT=skip>
12267 23:14:21.178488 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x16 RESULT=skip
12269 23:14:21.219465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_blr RESULT=skip>
12270 23:14:21.219698 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_blr RESULT=skip
12272 23:14:21.264008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x0 RESULT=skip>
12273 23:14:21.264280 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x0 RESULT=skip
12275 23:14:21.311277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x16 RESULT=skip>
12276 23:14:21.312072 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x16 RESULT=skip
12278 23:14:21.364792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_blr RESULT=skip>
12279 23:14:21.365692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_blr RESULT=skip
12281 23:14:21.412785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x0 RESULT=skip>
12282 23:14:21.413043 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x0 RESULT=skip
12284 23:14:21.457408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x16 RESULT=skip>
12285 23:14:21.457671 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x16 RESULT=skip
12287 23:14:21.504479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_blr RESULT=skip>
12288 23:14:21.504746 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_blr RESULT=skip
12290 23:14:21.539854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest RESULT=pass>
12291 23:14:21.540105 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest RESULT=pass
12293 23:14:21.588323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x0 RESULT=skip>
12294 23:14:21.588593 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x0 RESULT=skip
12296 23:14:21.631347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x16 RESULT=skip>
12297 23:14:21.632175 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x16 RESULT=skip
12299 23:14:21.677375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_blr RESULT=skip>
12300 23:14:21.678266 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_blr RESULT=skip
12302 23:14:21.728552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x0 RESULT=skip>
12303 23:14:21.729276 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x0 RESULT=skip
12305 23:14:21.784010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x16 RESULT=skip>
12306 23:14:21.784293 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x16 RESULT=skip
12308 23:14:21.824149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_blr RESULT=skip>
12309 23:14:21.825080 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_blr RESULT=skip
12311 23:14:21.868746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x0 RESULT=skip>
12312 23:14:21.869004 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x0 RESULT=skip
12314 23:14:21.913316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x16 RESULT=skip>
12315 23:14:21.913570 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x16 RESULT=skip
12317 23:14:21.944597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_blr RESULT=skip>
12318 23:14:21.944851 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_blr RESULT=skip
12320 23:14:21.979384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x0 RESULT=skip>
12321 23:14:21.979636 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x0 RESULT=skip
12323 23:14:22.019779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x16 RESULT=skip>
12324 23:14:22.020042 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x16 RESULT=skip
12326 23:14:22.054216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_blr RESULT=skip>
12327 23:14:22.054473 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_blr RESULT=skip
12329 23:14:22.092781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x0 RESULT=skip>
12330 23:14:22.093037 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x0 RESULT=skip
12332 23:14:22.136212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x16 RESULT=skip>
12333 23:14:22.136476 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x16 RESULT=skip
12335 23:14:22.176651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_blr RESULT=skip>
12336 23:14:22.177326 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_blr RESULT=skip
12338 23:14:22.224466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x0 RESULT=skip>
12339 23:14:22.225160 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x0 RESULT=skip
12341 23:14:22.273830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x16 RESULT=skip>
12342 23:14:22.274513 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x16 RESULT=skip
12344 23:14:22.326363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_blr RESULT=skip>
12345 23:14:22.327051 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_blr RESULT=skip
12347 23:14:22.374207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest RESULT=pass>
12348 23:14:22.374463 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest RESULT=pass
12350 23:14:22.420419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_RNG RESULT=pass>
12351 23:14:22.420677 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_RNG RESULT=pass
12353 23:14:22.458797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_rng RESULT=skip>
12354 23:14:22.459052 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_rng RESULT=skip
12356 23:14:22.496693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SME RESULT=pass>
12357 23:14:22.496946 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SME RESULT=pass
12359 23:14:22.528603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SME RESULT=pass>
12360 23:14:22.528857 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SME RESULT=pass
12362 23:14:22.566704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE RESULT=pass>
12363 23:14:22.566960 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE RESULT=pass
12365 23:14:22.593503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE RESULT=pass>
12366 23:14:22.593760 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE RESULT=pass
12368 23:14:22.633184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_2 RESULT=pass>
12369 23:14:22.633449 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_2 RESULT=pass
12371 23:14:22.666822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve_2 RESULT=skip>
12372 23:14:22.667075 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve_2 RESULT=skip
12374 23:14:22.707824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_AES RESULT=pass>
12375 23:14:22.708078 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_AES RESULT=pass
12377 23:14:22.747158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve_aes RESULT=skip>
12378 23:14:22.747419 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve_aes RESULT=skip
12380 23:14:22.797622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_PMULL RESULT=pass>
12381 23:14:22.797895 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_PMULL RESULT=pass
12383 23:14:22.845735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_pmull RESULT=skip>
12384 23:14:22.846442 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_pmull RESULT=skip
12386 23:14:22.893597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BITPERM RESULT=pass>
12387 23:14:22.894296 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BITPERM RESULT=pass
12389 23:14:22.944602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_bitperm RESULT=skip>
12390 23:14:22.945275 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_bitperm RESULT=skip
12392 23:14:22.992093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SHA3 RESULT=pass>
12393 23:14:22.992769 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SHA3 RESULT=pass
12395 23:14:23.032982 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_sha3 RESULT=skip
12397 23:14:23.035541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_sha3 RESULT=skip>
12398 23:14:23.080634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SM4 RESULT=pass>
12399 23:14:23.081308 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SM4 RESULT=pass
12401 23:14:23.126882 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_sm4 RESULT=skip
12403 23:14:23.129848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_sm4 RESULT=skip>
12404 23:14:23.177033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_I8MM RESULT=pass>
12405 23:14:23.177705 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_I8MM RESULT=pass
12407 23:14:23.224658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_i8mm RESULT=skip>
12408 23:14:23.225331 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_i8mm RESULT=skip
12410 23:14:23.272688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F32MM RESULT=pass>
12411 23:14:23.273540 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F32MM RESULT=pass
12413 23:14:23.317227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_f32mm RESULT=skip>
12414 23:14:23.317561 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_f32mm RESULT=skip
12416 23:14:23.357971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F64MM RESULT=pass>
12417 23:14:23.358297 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F64MM RESULT=pass
12419 23:14:23.394569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_f64mm RESULT=skip>
12420 23:14:23.394835 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_f64mm RESULT=skip
12422 23:14:23.431264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BF16 RESULT=pass>
12423 23:14:23.431520 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BF16 RESULT=pass
12425 23:14:23.465589 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_bf16 RESULT=skip
12427 23:14:23.468271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_bf16 RESULT=skip>
12428 23:14:23.505745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_EBF16 RESULT=pass>
12429 23:14:23.505998 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_EBF16 RESULT=pass
12431 23:14:23.548524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_ebf16 RESULT=skip>
12432 23:14:23.548778 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_ebf16 RESULT=skip
12434 23:14:23.587411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap RESULT=pass>
12435 23:14:23.587679 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap RESULT=pass
12437 23:14:23.633170 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_read_tpidr_one RESULT=pass
12439 23:14:23.636153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_read_tpidr_one RESULT=pass>
12440 23:14:23.675877 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_write_tpidr_one RESULT=pass
12442 23:14:23.679002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_write_tpidr_one RESULT=pass>
12443 23:14:23.715254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_verify_tpidr_one RESULT=pass>
12444 23:14:23.715511 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_verify_tpidr_one RESULT=pass
12446 23:14:23.747339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_count_tpidrs RESULT=pass>
12447 23:14:23.747595 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_count_tpidrs RESULT=pass
12449 23:14:23.784686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_tpidr2_write RESULT=pass>
12450 23:14:23.784939 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_tpidr2_write RESULT=pass
12452 23:14:23.822500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_tpidr2_read RESULT=pass>
12453 23:14:23.822756 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_tpidr2_read RESULT=pass
12455 23:14:23.867493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_write_tpidr_only RESULT=pass>
12456 23:14:23.868294 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_write_tpidr_only RESULT=pass
12458 23:14:23.898390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace RESULT=pass>
12459 23:14:23.898737 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace RESULT=pass
12461 23:14:23.944774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_FPSIMD RESULT=pass>
12462 23:14:23.945041 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_FPSIMD RESULT=pass
12464 23:14:23.978919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_FPSIMD RESULT=pass>
12465 23:14:23.979272 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_FPSIMD RESULT=pass
12467 23:14:24.017902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi RESULT=pass>
12468 23:14:24.018169 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi RESULT=pass
12470 23:14:24.065401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12471 23:14:24.065664 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12473 23:14:24.103632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12474 23:14:24.103932 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12476 23:14:24.142397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12477 23:14:24.142650 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12479 23:14:24.186698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12480 23:14:24.186953 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12482 23:14:24.229196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12483 23:14:24.229451 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12485 23:14:24.263458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2 RESULT=pass>
12486 23:14:24.263540 + set +x
12487 23:14:24.263775 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2 RESULT=pass
12489 23:14:24.270774 <LAVA_SIGNAL_ENDRUN 1_kselftest-arm64 12395410_1.6.2.3.5>
12490 23:14:24.271122 Received signal: <ENDRUN> 1_kselftest-arm64 12395410_1.6.2.3.5
12491 23:14:24.271209 Ending use of test pattern.
12492 23:14:24.271276 Ending test lava.1_kselftest-arm64 (12395410_1.6.2.3.5), duration 30.93
12494 23:14:24.273192 <LAVA_TEST_RUNNER EXIT>
12495 23:14:24.273461 ok: lava_test_shell seems to have completed
12496 23:14:24.274564 arm64_btitest: pass
arm64_btitest_bti_c_func_call_using_blr: skip
arm64_btitest_bti_c_func_call_using_br_x0: skip
arm64_btitest_bti_c_func_call_using_br_x16: skip
arm64_btitest_bti_j_func_call_using_blr: skip
arm64_btitest_bti_j_func_call_using_br_x0: skip
arm64_btitest_bti_j_func_call_using_br_x16: skip
arm64_btitest_bti_jc_func_call_using_blr: skip
arm64_btitest_bti_jc_func_call_using_br_x0: skip
arm64_btitest_bti_jc_func_call_using_br_x16: skip
arm64_btitest_bti_none_func_call_using_blr: skip
arm64_btitest_bti_none_func_call_using_br_x0: skip
arm64_btitest_bti_none_func_call_using_br_x16: skip
arm64_btitest_nohint_func_call_using_blr: skip
arm64_btitest_nohint_func_call_using_br_x0: skip
arm64_btitest_nohint_func_call_using_br_x16: skip
arm64_btitest_paciasp_func_call_using_blr: skip
arm64_btitest_paciasp_func_call_using_br_x0: skip
arm64_btitest_paciasp_func_call_using_br_x16: skip
arm64_check_buffer_fill: skip
arm64_check_child_memory: skip
arm64_check_gcr_el1_cswitch: skip
arm64_check_ksm_options: skip
arm64_check_mmap_options: skip
arm64_check_prctl: pass
arm64_check_prctl_NONE: pass
arm64_check_prctl_async: skip
arm64_check_prctl_check_basic_read: pass
arm64_check_prctl_sync: skip
arm64_check_prctl_sync_async: skip
arm64_check_tags_inclusion: skip
arm64_check_user_mem: skip
arm64_fake_sigreturn_bad_magic: pass
arm64_fake_sigreturn_bad_size: pass
arm64_fake_sigreturn_bad_size_for_magic0: pass
arm64_fake_sigreturn_duplicated_fpsimd: pass
arm64_fake_sigreturn_misaligned_sp: pass
arm64_fake_sigreturn_missing_fpsimd: pass
arm64_fake_sigreturn_sme_change_vl: skip
arm64_fake_sigreturn_sve_change_vl: skip
arm64_fp-stress: pass
arm64_fp-stress_FPSIMD-0-0: pass
arm64_fp-stress_FPSIMD-0-1: pass
arm64_fp-stress_FPSIMD-1-0: pass
arm64_fp-stress_FPSIMD-1-1: pass
arm64_fp-stress_FPSIMD-2-0: pass
arm64_fp-stress_FPSIMD-2-1: pass
arm64_fp-stress_FPSIMD-3-0: pass
arm64_fp-stress_FPSIMD-3-1: pass
arm64_fp-stress_FPSIMD-4-0: pass
arm64_fp-stress_FPSIMD-4-1: pass
arm64_fp-stress_FPSIMD-5-0: pass
arm64_fp-stress_FPSIMD-5-1: pass
arm64_fp-stress_FPSIMD-6-0: pass
arm64_fp-stress_FPSIMD-6-1: pass
arm64_fp-stress_FPSIMD-7-0: pass
arm64_fp-stress_FPSIMD-7-1: pass
arm64_hwcap: pass
arm64_hwcap_cpuinfo_match_RNG: pass
arm64_hwcap_cpuinfo_match_SME: pass
arm64_hwcap_cpuinfo_match_SVE: pass
arm64_hwcap_cpuinfo_match_SVE2_BF16: pass
arm64_hwcap_cpuinfo_match_SVE2_BITPERM: pass
arm64_hwcap_cpuinfo_match_SVE2_EBF16: pass
arm64_hwcap_cpuinfo_match_SVE2_F32MM: pass
arm64_hwcap_cpuinfo_match_SVE2_F64MM: pass
arm64_hwcap_cpuinfo_match_SVE2_I8MM: pass
arm64_hwcap_cpuinfo_match_SVE2_PMULL: pass
arm64_hwcap_cpuinfo_match_SVE2_SHA3: pass
arm64_hwcap_cpuinfo_match_SVE2_SM4: pass
arm64_hwcap_cpuinfo_match_SVE_2: pass
arm64_hwcap_cpuinfo_match_SVE_AES: pass
arm64_hwcap_sigill_SME: pass
arm64_hwcap_sigill_SVE: pass
arm64_hwcap_sigill_rng: skip
arm64_hwcap_sigill_sve2_bf16: skip
arm64_hwcap_sigill_sve2_bitperm: skip
arm64_hwcap_sigill_sve2_ebf16: skip
arm64_hwcap_sigill_sve2_f32mm: skip
arm64_hwcap_sigill_sve2_f64mm: skip
arm64_hwcap_sigill_sve2_i8mm: skip
arm64_hwcap_sigill_sve2_pmull: skip
arm64_hwcap_sigill_sve2_sha3: skip
arm64_hwcap_sigill_sve2_sm4: skip
arm64_hwcap_sigill_sve_2: skip
arm64_hwcap_sigill_sve_aes: skip
arm64_mangle_pstate_invalid_compat_toggle: pass
arm64_mangle_pstate_invalid_daif_bits: pass
arm64_mangle_pstate_invalid_mode_el1h: pass
arm64_mangle_pstate_invalid_mode_el1t: pass
arm64_mangle_pstate_invalid_mode_el2h: pass
arm64_mangle_pstate_invalid_mode_el2t: pass
arm64_mangle_pstate_invalid_mode_el3h: pass
arm64_mangle_pstate_invalid_mode_el3t: pass
arm64_nobtitest: pass
arm64_nobtitest_bti_c_func_call_using_blr: skip
arm64_nobtitest_bti_c_func_call_using_br_x0: skip
arm64_nobtitest_bti_c_func_call_using_br_x16: skip
arm64_nobtitest_bti_j_func_call_using_blr: skip
arm64_nobtitest_bti_j_func_call_using_br_x0: skip
arm64_nobtitest_bti_j_func_call_using_br_x16: skip
arm64_nobtitest_bti_jc_func_call_using_blr: skip
arm64_nobtitest_bti_jc_func_call_using_br_x0: skip
arm64_nobtitest_bti_jc_func_call_using_br_x16: skip
arm64_nobtitest_bti_none_func_call_using_blr: skip
arm64_nobtitest_bti_none_func_call_using_br_x0: skip
arm64_nobtitest_bti_none_func_call_using_br_x16: skip
arm64_nobtitest_nohint_func_call_using_blr: skip
arm64_nobtitest_nohint_func_call_using_br_x0: skip
arm64_nobtitest_nohint_func_call_using_br_x16: skip
arm64_nobtitest_paciasp_func_call_using_blr: skip
arm64_nobtitest_paciasp_func_call_using_br_x0: skip
arm64_nobtitest_paciasp_func_call_using_br_x16: skip
arm64_pac: pass
arm64_pac_generic_pauth_not_enabled: skip
arm64_pac_pauth_not_enabled: skip
arm64_ptrace: pass
arm64_ptrace_count_tpidrs: pass
arm64_ptrace_read_tpidr_one: pass
arm64_ptrace_tpidr2_read: pass
arm64_ptrace_tpidr2_write: pass
arm64_ptrace_verify_tpidr_one: pass
arm64_ptrace_write_tpidr_one: pass
arm64_ptrace_write_tpidr_only: pass
arm64_run_tags_test_sh: pass
arm64_sme_trap_no_sm: skip
arm64_sme_trap_non_streaming: skip
arm64_sme_trap_za: pass
arm64_sme_vl: skip
arm64_ssve_regs: skip
arm64_sve-probe-vls: skip
arm64_sve-probe-vls_sve_not_available: skip
arm64_sve-ptrace: skip
arm64_sve-ptrace_sve_not_available: skip
arm64_sve_regs: skip
arm64_sve_vl: skip
arm64_syscall-abi: pass
arm64_syscall-abi_getpid_FPSIMD: pass
arm64_syscall-abi_sched_yield_FPSIMD: pass
arm64_tags_test: pass
arm64_tpidr2: pass
arm64_tpidr2_skipped_TPIDR2_not_supported: pass
arm64_vec-syscfg: pass
arm64_vec-syscfg_sme_not_supported: skip
arm64_vec-syscfg_sve_not_supported: skip
arm64_za-fork: pass
arm64_za-fork_skipped: pass
arm64_za-ptrace: skip
arm64_za-ptrace_sme_not_available: skip
arm64_za_no_regs: skip
arm64_za_regs: skip
shardfile-arm64: pass
12497 23:14:24.274728 end: 3.1 lava-test-shell (duration 00:00:32) [common]
12498 23:14:24.274829 end: 3 lava-test-retry (duration 00:00:32) [common]
12499 23:14:24.274926 start: 4 finalize (timeout 00:07:27) [common]
12500 23:14:24.275026 start: 4.1 power-off (timeout 00:00:30) [common]
12501 23:14:24.275194 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=off'
12502 23:14:24.354201 >> Command sent successfully.
12503 23:14:24.359011 Returned 0 in 0 seconds
12504 23:14:24.460059 end: 4.1 power-off (duration 00:00:00) [common]
12506 23:14:24.461582 start: 4.2 read-feedback (timeout 00:07:27) [common]
12507 23:14:24.463197 Listened to connection for namespace 'common' for up to 1s
12508 23:14:25.463805 Finalising connection for namespace 'common'
12509 23:14:25.464471 Disconnecting from shell: Finalise
12510 23:14:25.464874 / #
12511 23:14:25.566050 end: 4.2 read-feedback (duration 00:00:01) [common]
12512 23:14:25.566770 end: 4 finalize (duration 00:00:01) [common]
12513 23:14:25.567378 Cleaning after the job
12514 23:14:25.567967 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12395410/tftp-deploy-_gi8__3c/ramdisk
12515 23:14:25.581234 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12395410/tftp-deploy-_gi8__3c/kernel
12516 23:14:25.617140 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12395410/tftp-deploy-_gi8__3c/dtb
12517 23:14:25.617443 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12395410/tftp-deploy-_gi8__3c/nfsrootfs
12518 23:14:25.710368 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12395410/tftp-deploy-_gi8__3c/modules
12519 23:14:25.717593 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12395410
12520 23:14:26.354051 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12395410
12521 23:14:26.354237 Job finished correctly