Boot log: mt8192-asurada-spherion-r0
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 14
- Kernel Errors: 34
- Errors: 0
1 23:09:51.372897 lava-dispatcher, installed at version: 2023.10
2 23:09:51.373103 start: 0 validate
3 23:09:51.373235 Start time: 2023-12-27 23:09:51.373227+00:00 (UTC)
4 23:09:51.373347 Using caching service: 'http://localhost/cache/?uri=%s'
5 23:09:51.373475 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230623.0%2Farm64%2Finitrd.cpio.gz exists
6 23:09:51.643956 Using caching service: 'http://localhost/cache/?uri=%s'
7 23:09:51.644624 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.66-cip11-rt6-10-g38253b8903b4%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 23:09:51.896842 Using caching service: 'http://localhost/cache/?uri=%s'
9 23:09:51.897005 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.66-cip11-rt6-10-g38253b8903b4%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 23:09:52.153887 Using caching service: 'http://localhost/cache/?uri=%s'
11 23:09:52.154070 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230623.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 23:09:52.405431 Using caching service: 'http://localhost/cache/?uri=%s'
13 23:09:52.406129 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.66-cip11-rt6-10-g38253b8903b4%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 23:09:52.672931 validate duration: 1.30
16 23:09:52.674134 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 23:09:52.674641 start: 1.1 download-retry (timeout 00:10:00) [common]
18 23:09:52.675103 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 23:09:52.675751 Not decompressing ramdisk as can be used compressed.
20 23:09:52.676215 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230623.0/arm64/initrd.cpio.gz
21 23:09:52.676574 saving as /var/lib/lava/dispatcher/tmp/12395392/tftp-deploy-l3kfndy0/ramdisk/initrd.cpio.gz
22 23:09:52.676908 total size: 4665395 (4 MB)
23 23:09:52.681735 progress 0 % (0 MB)
24 23:09:52.689401 progress 5 % (0 MB)
25 23:09:52.696099 progress 10 % (0 MB)
26 23:09:52.701753 progress 15 % (0 MB)
27 23:09:52.705735 progress 20 % (0 MB)
28 23:09:52.709265 progress 25 % (1 MB)
29 23:09:52.712096 progress 30 % (1 MB)
30 23:09:52.714678 progress 35 % (1 MB)
31 23:09:52.716959 progress 40 % (1 MB)
32 23:09:52.719504 progress 45 % (2 MB)
33 23:09:52.721453 progress 50 % (2 MB)
34 23:09:52.723459 progress 55 % (2 MB)
35 23:09:52.725271 progress 60 % (2 MB)
36 23:09:52.727013 progress 65 % (2 MB)
37 23:09:52.728734 progress 70 % (3 MB)
38 23:09:52.730308 progress 75 % (3 MB)
39 23:09:52.731912 progress 80 % (3 MB)
40 23:09:52.733662 progress 85 % (3 MB)
41 23:09:52.735076 progress 90 % (4 MB)
42 23:09:52.736494 progress 95 % (4 MB)
43 23:09:52.737931 progress 100 % (4 MB)
44 23:09:52.738111 4 MB downloaded in 0.06 s (72.67 MB/s)
45 23:09:52.738279 end: 1.1.1 http-download (duration 00:00:00) [common]
47 23:09:52.738550 end: 1.1 download-retry (duration 00:00:00) [common]
48 23:09:52.738645 start: 1.2 download-retry (timeout 00:10:00) [common]
49 23:09:52.738738 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 23:09:52.738883 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.66-cip11-rt6-10-g38253b8903b4/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 23:09:52.738958 saving as /var/lib/lava/dispatcher/tmp/12395392/tftp-deploy-l3kfndy0/kernel/Image
52 23:09:52.739026 total size: 50024960 (47 MB)
53 23:09:52.739102 No compression specified
54 23:09:52.740223 progress 0 % (0 MB)
55 23:09:52.753292 progress 5 % (2 MB)
56 23:09:52.766211 progress 10 % (4 MB)
57 23:09:52.779184 progress 15 % (7 MB)
58 23:09:52.792344 progress 20 % (9 MB)
59 23:09:52.805332 progress 25 % (11 MB)
60 23:09:52.818296 progress 30 % (14 MB)
61 23:09:52.831456 progress 35 % (16 MB)
62 23:09:52.844547 progress 40 % (19 MB)
63 23:09:52.857495 progress 45 % (21 MB)
64 23:09:52.870649 progress 50 % (23 MB)
65 23:09:52.883611 progress 55 % (26 MB)
66 23:09:52.896625 progress 60 % (28 MB)
67 23:09:52.909744 progress 65 % (31 MB)
68 23:09:52.922885 progress 70 % (33 MB)
69 23:09:52.935871 progress 75 % (35 MB)
70 23:09:52.949381 progress 80 % (38 MB)
71 23:09:52.962477 progress 85 % (40 MB)
72 23:09:52.975546 progress 90 % (42 MB)
73 23:09:52.988671 progress 95 % (45 MB)
74 23:09:53.001430 progress 100 % (47 MB)
75 23:09:53.001642 47 MB downloaded in 0.26 s (181.67 MB/s)
76 23:09:53.001793 end: 1.2.1 http-download (duration 00:00:00) [common]
78 23:09:53.002029 end: 1.2 download-retry (duration 00:00:00) [common]
79 23:09:53.002117 start: 1.3 download-retry (timeout 00:10:00) [common]
80 23:09:53.002205 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 23:09:53.002338 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.66-cip11-rt6-10-g38253b8903b4/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 23:09:53.002407 saving as /var/lib/lava/dispatcher/tmp/12395392/tftp-deploy-l3kfndy0/dtb/mt8192-asurada-spherion-r0.dtb
83 23:09:53.002467 total size: 47278 (0 MB)
84 23:09:53.002527 No compression specified
85 23:09:53.003695 progress 69 % (0 MB)
86 23:09:53.003969 progress 100 % (0 MB)
87 23:09:53.004124 0 MB downloaded in 0.00 s (27.25 MB/s)
88 23:09:53.004247 end: 1.3.1 http-download (duration 00:00:00) [common]
90 23:09:53.004473 end: 1.3 download-retry (duration 00:00:00) [common]
91 23:09:53.004561 start: 1.4 download-retry (timeout 00:10:00) [common]
92 23:09:53.004643 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 23:09:53.004754 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230623.0/arm64/full.rootfs.tar.xz
94 23:09:53.004821 saving as /var/lib/lava/dispatcher/tmp/12395392/tftp-deploy-l3kfndy0/nfsrootfs/full.rootfs.tar
95 23:09:53.004880 total size: 200813988 (191 MB)
96 23:09:53.004940 Using unxz to decompress xz
97 23:09:53.009077 progress 0 % (0 MB)
98 23:09:53.543477 progress 5 % (9 MB)
99 23:09:54.058341 progress 10 % (19 MB)
100 23:09:54.648409 progress 15 % (28 MB)
101 23:09:55.022142 progress 20 % (38 MB)
102 23:09:55.347409 progress 25 % (47 MB)
103 23:09:55.938527 progress 30 % (57 MB)
104 23:09:56.486592 progress 35 % (67 MB)
105 23:09:57.074991 progress 40 % (76 MB)
106 23:09:57.632976 progress 45 % (86 MB)
107 23:09:58.215194 progress 50 % (95 MB)
108 23:09:58.846481 progress 55 % (105 MB)
109 23:09:59.536333 progress 60 % (114 MB)
110 23:09:59.657909 progress 65 % (124 MB)
111 23:09:59.800209 progress 70 % (134 MB)
112 23:09:59.897794 progress 75 % (143 MB)
113 23:09:59.969856 progress 80 % (153 MB)
114 23:10:00.038078 progress 85 % (162 MB)
115 23:10:00.140034 progress 90 % (172 MB)
116 23:10:00.417676 progress 95 % (181 MB)
117 23:10:00.993898 progress 100 % (191 MB)
118 23:10:00.999092 191 MB downloaded in 7.99 s (23.96 MB/s)
119 23:10:00.999424 end: 1.4.1 http-download (duration 00:00:08) [common]
121 23:10:00.999694 end: 1.4 download-retry (duration 00:00:08) [common]
122 23:10:00.999782 start: 1.5 download-retry (timeout 00:09:52) [common]
123 23:10:00.999872 start: 1.5.1 http-download (timeout 00:09:52) [common]
124 23:10:01.000025 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.66-cip11-rt6-10-g38253b8903b4/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 23:10:01.000096 saving as /var/lib/lava/dispatcher/tmp/12395392/tftp-deploy-l3kfndy0/modules/modules.tar
126 23:10:01.000161 total size: 8633892 (8 MB)
127 23:10:01.000225 Using unxz to decompress xz
128 23:10:01.004591 progress 0 % (0 MB)
129 23:10:01.025719 progress 5 % (0 MB)
130 23:10:01.049116 progress 10 % (0 MB)
131 23:10:01.072585 progress 15 % (1 MB)
132 23:10:01.095763 progress 20 % (1 MB)
133 23:10:01.119590 progress 25 % (2 MB)
134 23:10:01.147017 progress 30 % (2 MB)
135 23:10:01.171344 progress 35 % (2 MB)
136 23:10:01.194618 progress 40 % (3 MB)
137 23:10:01.218698 progress 45 % (3 MB)
138 23:10:01.244028 progress 50 % (4 MB)
139 23:10:01.268140 progress 55 % (4 MB)
140 23:10:01.294920 progress 60 % (4 MB)
141 23:10:01.320379 progress 65 % (5 MB)
142 23:10:01.345072 progress 70 % (5 MB)
143 23:10:01.368456 progress 75 % (6 MB)
144 23:10:01.395326 progress 80 % (6 MB)
145 23:10:01.420890 progress 85 % (7 MB)
146 23:10:01.447452 progress 90 % (7 MB)
147 23:10:01.477274 progress 95 % (7 MB)
148 23:10:01.504988 progress 100 % (8 MB)
149 23:10:01.510476 8 MB downloaded in 0.51 s (16.14 MB/s)
150 23:10:01.510728 end: 1.5.1 http-download (duration 00:00:01) [common]
152 23:10:01.511011 end: 1.5 download-retry (duration 00:00:01) [common]
153 23:10:01.511102 start: 1.6 prepare-tftp-overlay (timeout 00:09:51) [common]
154 23:10:01.511193 start: 1.6.1 extract-nfsrootfs (timeout 00:09:51) [common]
155 23:10:05.121184 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/12395392/extract-nfsrootfs-_9e2sa3_
156 23:10:05.121373 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 23:10:05.121480 start: 1.6.2 lava-overlay (timeout 00:09:48) [common]
158 23:10:05.121658 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12395392/lava-overlay-zlav7ku0
159 23:10:05.121794 makedir: /var/lib/lava/dispatcher/tmp/12395392/lava-overlay-zlav7ku0/lava-12395392/bin
160 23:10:05.121900 makedir: /var/lib/lava/dispatcher/tmp/12395392/lava-overlay-zlav7ku0/lava-12395392/tests
161 23:10:05.122002 makedir: /var/lib/lava/dispatcher/tmp/12395392/lava-overlay-zlav7ku0/lava-12395392/results
162 23:10:05.122107 Creating /var/lib/lava/dispatcher/tmp/12395392/lava-overlay-zlav7ku0/lava-12395392/bin/lava-add-keys
163 23:10:05.122256 Creating /var/lib/lava/dispatcher/tmp/12395392/lava-overlay-zlav7ku0/lava-12395392/bin/lava-add-sources
164 23:10:05.122393 Creating /var/lib/lava/dispatcher/tmp/12395392/lava-overlay-zlav7ku0/lava-12395392/bin/lava-background-process-start
165 23:10:05.122527 Creating /var/lib/lava/dispatcher/tmp/12395392/lava-overlay-zlav7ku0/lava-12395392/bin/lava-background-process-stop
166 23:10:05.122659 Creating /var/lib/lava/dispatcher/tmp/12395392/lava-overlay-zlav7ku0/lava-12395392/bin/lava-common-functions
167 23:10:05.122794 Creating /var/lib/lava/dispatcher/tmp/12395392/lava-overlay-zlav7ku0/lava-12395392/bin/lava-echo-ipv4
168 23:10:05.122925 Creating /var/lib/lava/dispatcher/tmp/12395392/lava-overlay-zlav7ku0/lava-12395392/bin/lava-install-packages
169 23:10:05.123055 Creating /var/lib/lava/dispatcher/tmp/12395392/lava-overlay-zlav7ku0/lava-12395392/bin/lava-installed-packages
170 23:10:05.123185 Creating /var/lib/lava/dispatcher/tmp/12395392/lava-overlay-zlav7ku0/lava-12395392/bin/lava-os-build
171 23:10:05.123317 Creating /var/lib/lava/dispatcher/tmp/12395392/lava-overlay-zlav7ku0/lava-12395392/bin/lava-probe-channel
172 23:10:05.123500 Creating /var/lib/lava/dispatcher/tmp/12395392/lava-overlay-zlav7ku0/lava-12395392/bin/lava-probe-ip
173 23:10:05.123634 Creating /var/lib/lava/dispatcher/tmp/12395392/lava-overlay-zlav7ku0/lava-12395392/bin/lava-target-ip
174 23:10:05.123764 Creating /var/lib/lava/dispatcher/tmp/12395392/lava-overlay-zlav7ku0/lava-12395392/bin/lava-target-mac
175 23:10:05.123895 Creating /var/lib/lava/dispatcher/tmp/12395392/lava-overlay-zlav7ku0/lava-12395392/bin/lava-target-storage
176 23:10:05.124027 Creating /var/lib/lava/dispatcher/tmp/12395392/lava-overlay-zlav7ku0/lava-12395392/bin/lava-test-case
177 23:10:05.124159 Creating /var/lib/lava/dispatcher/tmp/12395392/lava-overlay-zlav7ku0/lava-12395392/bin/lava-test-event
178 23:10:05.124286 Creating /var/lib/lava/dispatcher/tmp/12395392/lava-overlay-zlav7ku0/lava-12395392/bin/lava-test-feedback
179 23:10:05.124415 Creating /var/lib/lava/dispatcher/tmp/12395392/lava-overlay-zlav7ku0/lava-12395392/bin/lava-test-raise
180 23:10:05.124545 Creating /var/lib/lava/dispatcher/tmp/12395392/lava-overlay-zlav7ku0/lava-12395392/bin/lava-test-reference
181 23:10:05.124674 Creating /var/lib/lava/dispatcher/tmp/12395392/lava-overlay-zlav7ku0/lava-12395392/bin/lava-test-runner
182 23:10:05.124803 Creating /var/lib/lava/dispatcher/tmp/12395392/lava-overlay-zlav7ku0/lava-12395392/bin/lava-test-set
183 23:10:05.124932 Creating /var/lib/lava/dispatcher/tmp/12395392/lava-overlay-zlav7ku0/lava-12395392/bin/lava-test-shell
184 23:10:05.125062 Updating /var/lib/lava/dispatcher/tmp/12395392/lava-overlay-zlav7ku0/lava-12395392/bin/lava-add-keys (debian)
185 23:10:05.125219 Updating /var/lib/lava/dispatcher/tmp/12395392/lava-overlay-zlav7ku0/lava-12395392/bin/lava-add-sources (debian)
186 23:10:05.125363 Updating /var/lib/lava/dispatcher/tmp/12395392/lava-overlay-zlav7ku0/lava-12395392/bin/lava-install-packages (debian)
187 23:10:05.125507 Updating /var/lib/lava/dispatcher/tmp/12395392/lava-overlay-zlav7ku0/lava-12395392/bin/lava-installed-packages (debian)
188 23:10:05.125649 Updating /var/lib/lava/dispatcher/tmp/12395392/lava-overlay-zlav7ku0/lava-12395392/bin/lava-os-build (debian)
189 23:10:05.125774 Creating /var/lib/lava/dispatcher/tmp/12395392/lava-overlay-zlav7ku0/lava-12395392/environment
190 23:10:05.125873 LAVA metadata
191 23:10:05.125947 - LAVA_JOB_ID=12395392
192 23:10:05.126012 - LAVA_DISPATCHER_IP=192.168.201.1
193 23:10:05.126115 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:48) [common]
194 23:10:05.126183 skipped lava-vland-overlay
195 23:10:05.126260 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 23:10:05.126341 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:48) [common]
197 23:10:05.126404 skipped lava-multinode-overlay
198 23:10:05.126479 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 23:10:05.126571 start: 1.6.2.3 test-definition (timeout 00:09:48) [common]
200 23:10:05.126644 Loading test definitions
201 23:10:05.126736 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:48) [common]
202 23:10:05.126809 Using /lava-12395392 at stage 0
203 23:10:05.127100 uuid=12395392_1.6.2.3.1 testdef=None
204 23:10:05.127190 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 23:10:05.127277 start: 1.6.2.3.2 test-overlay (timeout 00:09:48) [common]
206 23:10:05.127855 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 23:10:05.128080 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:48) [common]
209 23:10:05.128650 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 23:10:05.128887 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:48) [common]
212 23:10:05.129439 runner path: /var/lib/lava/dispatcher/tmp/12395392/lava-overlay-zlav7ku0/lava-12395392/0/tests/0_timesync-off test_uuid 12395392_1.6.2.3.1
213 23:10:05.129604 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 23:10:05.129834 start: 1.6.2.3.5 git-repo-action (timeout 00:09:48) [common]
216 23:10:05.129909 Using /lava-12395392 at stage 0
217 23:10:05.130008 Fetching tests from https://github.com/kernelci/test-definitions.git
218 23:10:05.130089 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/12395392/lava-overlay-zlav7ku0/lava-12395392/0/tests/1_kselftest-dt'
219 23:10:10.780003 Running '/usr/bin/git checkout kernelci.org
220 23:10:10.927148 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/12395392/lava-overlay-zlav7ku0/lava-12395392/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
221 23:10:10.927891 uuid=12395392_1.6.2.3.5 testdef=None
222 23:10:10.928058 end: 1.6.2.3.5 git-repo-action (duration 00:00:06) [common]
224 23:10:10.928310 start: 1.6.2.3.6 test-overlay (timeout 00:09:42) [common]
225 23:10:10.929064 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 23:10:10.929298 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:42) [common]
228 23:10:10.930281 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 23:10:10.930516 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:42) [common]
231 23:10:10.931462 runner path: /var/lib/lava/dispatcher/tmp/12395392/lava-overlay-zlav7ku0/lava-12395392/0/tests/1_kselftest-dt test_uuid 12395392_1.6.2.3.5
232 23:10:10.931556 BOARD='mt8192-asurada-spherion-r0'
233 23:10:10.931647 BRANCH='cip-gitlab'
234 23:10:10.931729 SKIPFILE='/dev/null'
235 23:10:10.931788 SKIP_INSTALL='True'
236 23:10:10.931845 TESTPROG_URL='http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.66-cip11-rt6-10-g38253b8903b4/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 23:10:10.931906 TST_CASENAME=''
238 23:10:10.931961 TST_CMDFILES='dt'
239 23:10:10.932104 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 23:10:10.932312 Creating lava-test-runner.conf files
242 23:10:10.932377 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12395392/lava-overlay-zlav7ku0/lava-12395392/0 for stage 0
243 23:10:10.932470 - 0_timesync-off
244 23:10:10.932542 - 1_kselftest-dt
245 23:10:10.932638 end: 1.6.2.3 test-definition (duration 00:00:06) [common]
246 23:10:10.932725 start: 1.6.2.4 compress-overlay (timeout 00:09:42) [common]
247 23:10:18.425953 end: 1.6.2.4 compress-overlay (duration 00:00:07) [common]
248 23:10:18.426116 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:34) [common]
249 23:10:18.426212 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 23:10:18.426312 end: 1.6.2 lava-overlay (duration 00:00:13) [common]
251 23:10:18.426405 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:34) [common]
252 23:10:18.546764 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 23:10:18.547165 start: 1.6.4 extract-modules (timeout 00:09:34) [common]
254 23:10:18.547289 extracting modules file /var/lib/lava/dispatcher/tmp/12395392/tftp-deploy-l3kfndy0/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12395392/extract-nfsrootfs-_9e2sa3_
255 23:10:18.769575 extracting modules file /var/lib/lava/dispatcher/tmp/12395392/tftp-deploy-l3kfndy0/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12395392/extract-overlay-ramdisk-b7b53xg2/ramdisk
256 23:10:18.998298 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 23:10:18.998471 start: 1.6.5 apply-overlay-tftp (timeout 00:09:34) [common]
258 23:10:18.998567 [common] Applying overlay to NFS
259 23:10:18.998639 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12395392/compress-overlay-t8l90nme/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12395392/extract-nfsrootfs-_9e2sa3_
260 23:10:19.927085 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 23:10:19.927240 start: 1.6.6 configure-preseed-file (timeout 00:09:33) [common]
262 23:10:19.927336 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 23:10:19.927518 start: 1.6.7 compress-ramdisk (timeout 00:09:33) [common]
264 23:10:19.927597 Building ramdisk /var/lib/lava/dispatcher/tmp/12395392/extract-overlay-ramdisk-b7b53xg2/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12395392/extract-overlay-ramdisk-b7b53xg2/ramdisk
265 23:10:20.286365 >> 119421 blocks
266 23:10:22.220022 rename /var/lib/lava/dispatcher/tmp/12395392/extract-overlay-ramdisk-b7b53xg2/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12395392/tftp-deploy-l3kfndy0/ramdisk/ramdisk.cpio.gz
267 23:10:22.220499 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 23:10:22.220672 start: 1.6.8 prepare-kernel (timeout 00:09:30) [common]
269 23:10:22.220817 start: 1.6.8.1 prepare-fit (timeout 00:09:30) [common]
270 23:10:22.220969 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12395392/tftp-deploy-l3kfndy0/kernel/Image'
271 23:10:34.714345 Returned 0 in 12 seconds
272 23:10:34.815288 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12395392/tftp-deploy-l3kfndy0/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12395392/tftp-deploy-l3kfndy0/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12395392/tftp-deploy-l3kfndy0/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12395392/tftp-deploy-l3kfndy0/kernel/image.itb
273 23:10:35.196335 output: FIT description: Kernel Image image with one or more FDT blobs
274 23:10:35.196734 output: Created: Wed Dec 27 23:10:35 2023
275 23:10:35.196846 output: Image 0 (kernel-1)
276 23:10:35.196952 output: Description:
277 23:10:35.197055 output: Created: Wed Dec 27 23:10:35 2023
278 23:10:35.197157 output: Type: Kernel Image
279 23:10:35.197252 output: Compression: lzma compressed
280 23:10:35.197355 output: Data Size: 11480388 Bytes = 11211.32 KiB = 10.95 MiB
281 23:10:35.197455 output: Architecture: AArch64
282 23:10:35.197584 output: OS: Linux
283 23:10:35.197683 output: Load Address: 0x00000000
284 23:10:35.197783 output: Entry Point: 0x00000000
285 23:10:35.197880 output: Hash algo: crc32
286 23:10:35.197981 output: Hash value: a55b2f0b
287 23:10:35.198079 output: Image 1 (fdt-1)
288 23:10:35.198173 output: Description: mt8192-asurada-spherion-r0
289 23:10:35.198266 output: Created: Wed Dec 27 23:10:35 2023
290 23:10:35.198362 output: Type: Flat Device Tree
291 23:10:35.198455 output: Compression: uncompressed
292 23:10:35.198546 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
293 23:10:35.198638 output: Architecture: AArch64
294 23:10:35.198728 output: Hash algo: crc32
295 23:10:35.198819 output: Hash value: cc4352de
296 23:10:35.198909 output: Image 2 (ramdisk-1)
297 23:10:35.198998 output: Description: unavailable
298 23:10:35.199088 output: Created: Wed Dec 27 23:10:35 2023
299 23:10:35.199178 output: Type: RAMDisk Image
300 23:10:35.199268 output: Compression: Unknown Compression
301 23:10:35.199358 output: Data Size: 17793011 Bytes = 17375.99 KiB = 16.97 MiB
302 23:10:35.199488 output: Architecture: AArch64
303 23:10:35.199588 output: OS: Linux
304 23:10:35.199681 output: Load Address: unavailable
305 23:10:35.199772 output: Entry Point: unavailable
306 23:10:35.199863 output: Hash algo: crc32
307 23:10:35.199953 output: Hash value: 1bbec55a
308 23:10:35.200043 output: Default Configuration: 'conf-1'
309 23:10:35.200133 output: Configuration 0 (conf-1)
310 23:10:35.200223 output: Description: mt8192-asurada-spherion-r0
311 23:10:35.200313 output: Kernel: kernel-1
312 23:10:35.200403 output: Init Ramdisk: ramdisk-1
313 23:10:35.200495 output: FDT: fdt-1
314 23:10:35.200587 output: Loadables: kernel-1
315 23:10:35.200676 output:
316 23:10:35.200938 end: 1.6.8.1 prepare-fit (duration 00:00:13) [common]
317 23:10:35.201081 end: 1.6.8 prepare-kernel (duration 00:00:13) [common]
318 23:10:35.201234 end: 1.6 prepare-tftp-overlay (duration 00:00:34) [common]
319 23:10:35.201369 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:17) [common]
320 23:10:35.201494 No LXC device requested
321 23:10:35.201617 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 23:10:35.201747 start: 1.8 deploy-device-env (timeout 00:09:17) [common]
323 23:10:35.201865 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 23:10:35.201971 Checking files for TFTP limit of 4294967296 bytes.
325 23:10:35.202650 end: 1 tftp-deploy (duration 00:00:43) [common]
326 23:10:35.202785 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 23:10:35.202919 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 23:10:35.203101 substitutions:
329 23:10:35.203201 - {DTB}: 12395392/tftp-deploy-l3kfndy0/dtb/mt8192-asurada-spherion-r0.dtb
330 23:10:35.203303 - {INITRD}: 12395392/tftp-deploy-l3kfndy0/ramdisk/ramdisk.cpio.gz
331 23:10:35.203437 - {KERNEL}: 12395392/tftp-deploy-l3kfndy0/kernel/Image
332 23:10:35.203515 - {LAVA_MAC}: None
333 23:10:35.203592 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/12395392/extract-nfsrootfs-_9e2sa3_
334 23:10:35.203687 - {NFS_SERVER_IP}: 192.168.201.1
335 23:10:35.203785 - {PRESEED_CONFIG}: None
336 23:10:35.203881 - {PRESEED_LOCAL}: None
337 23:10:35.203975 - {RAMDISK}: 12395392/tftp-deploy-l3kfndy0/ramdisk/ramdisk.cpio.gz
338 23:10:35.204072 - {ROOT_PART}: None
339 23:10:35.204166 - {ROOT}: None
340 23:10:35.204260 - {SERVER_IP}: 192.168.201.1
341 23:10:35.204354 - {TEE}: None
342 23:10:35.204447 Parsed boot commands:
343 23:10:35.204539 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 23:10:35.204782 Parsed boot commands: tftpboot 192.168.201.1 12395392/tftp-deploy-l3kfndy0/kernel/image.itb 12395392/tftp-deploy-l3kfndy0/kernel/cmdline
345 23:10:35.204911 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 23:10:35.205038 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 23:10:35.205173 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 23:10:35.205307 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 23:10:35.205416 Not connected, no need to disconnect.
350 23:10:35.205533 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 23:10:35.205659 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 23:10:35.205766 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-2'
353 23:10:35.210355 Setting prompt string to ['lava-test: # ']
354 23:10:35.210835 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 23:10:35.211024 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 23:10:35.211199 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 23:10:35.211348 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 23:10:35.211718 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-2' '--port=1' '--command=reboot'
359 23:10:40.369085 >> Command sent successfully.
360 23:10:40.379667 Returned 0 in 5 seconds
361 23:10:40.481040 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 23:10:40.483150 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 23:10:40.483893 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 23:10:40.484580 Setting prompt string to 'Starting depthcharge on Spherion...'
366 23:10:40.485192 Changing prompt to 'Starting depthcharge on Spherion...'
367 23:10:40.485810 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 23:10:40.487661 [Enter `^Ec?' for help]
369 23:10:40.643925
370 23:10:40.644432
371 23:10:40.644899 F0: 102B 0000
372 23:10:40.645429
373 23:10:40.645997 F3: 1001 0000 [0200]
374 23:10:40.646546
375 23:10:40.647516 F3: 1001 0000
376 23:10:40.647957
377 23:10:40.648303 F7: 102D 0000
378 23:10:40.648628
379 23:10:40.648937 F1: 0000 0000
380 23:10:40.651212
381 23:10:40.651688 V0: 0000 0000 [0001]
382 23:10:40.652048
383 23:10:40.652369 00: 0007 8000
384 23:10:40.652698
385 23:10:40.655139 01: 0000 0000
386 23:10:40.655639
387 23:10:40.655990 BP: 0C00 0209 [0000]
388 23:10:40.656394
389 23:10:40.658841 G0: 1182 0000
390 23:10:40.659280
391 23:10:40.659681 EC: 0000 0021 [4000]
392 23:10:40.660007
393 23:10:40.662493 S7: 0000 0000 [0000]
394 23:10:40.662919
395 23:10:40.663256 CC: 0000 0000 [0001]
396 23:10:40.663651
397 23:10:40.666254 T0: 0000 0040 [010F]
398 23:10:40.666685
399 23:10:40.667026 Jump to BL
400 23:10:40.667346
401 23:10:40.691118
402 23:10:40.691664
403 23:10:40.692142
404 23:10:40.698079 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 23:10:40.701715 ARM64: Exception handlers installed.
406 23:10:40.705375 ARM64: Testing exception
407 23:10:40.708671 ARM64: Done test exception
408 23:10:40.716125 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 23:10:40.727261 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 23:10:40.733569 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 23:10:40.744515 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 23:10:40.749873 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 23:10:40.756511 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 23:10:40.767202 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 23:10:40.774415 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 23:10:40.793798 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 23:10:40.797398 WDT: Last reset was cold boot
418 23:10:40.800141 SPI1(PAD0) initialized at 2873684 Hz
419 23:10:40.804075 SPI5(PAD0) initialized at 992727 Hz
420 23:10:40.807461 VBOOT: Loading verstage.
421 23:10:40.813709 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 23:10:40.817184 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 23:10:40.820380 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 23:10:40.823923 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 23:10:40.831278 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 23:10:40.838419 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 23:10:40.848629 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
428 23:10:40.849067
429 23:10:40.849427
430 23:10:40.858868 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 23:10:40.862321 ARM64: Exception handlers installed.
432 23:10:40.865075 ARM64: Testing exception
433 23:10:40.865502 ARM64: Done test exception
434 23:10:40.872673 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 23:10:40.875814 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 23:10:40.889461 Probing TPM: . done!
437 23:10:40.890077 TPM ready after 0 ms
438 23:10:40.896590 Connected to device vid:did:rid of 1ae0:0028:00
439 23:10:40.903653 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
440 23:10:40.961933 Initialized TPM device CR50 revision 0
441 23:10:40.973407 tlcl_send_startup: Startup return code is 0
442 23:10:40.973847 TPM: setup succeeded
443 23:10:40.985253 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 23:10:40.993989 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 23:10:41.006077 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 23:10:41.016167 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 23:10:41.019156 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 23:10:41.024653 in-header: 03 07 00 00 08 00 00 00
449 23:10:41.027930 in-data: aa e4 47 04 13 02 00 00
450 23:10:41.031420 Chrome EC: UHEPI supported
451 23:10:41.038784 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 23:10:41.042936 in-header: 03 95 00 00 08 00 00 00
453 23:10:41.046489 in-data: 18 20 20 08 00 00 00 00
454 23:10:41.046919 Phase 1
455 23:10:41.049605 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 23:10:41.057117 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 23:10:41.061062 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 23:10:41.064326 Recovery requested (1009000e)
459 23:10:41.073574 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 23:10:41.078838 tlcl_extend: response is 0
461 23:10:41.087945 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 23:10:41.094786 tlcl_extend: response is 0
463 23:10:41.100882 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 23:10:41.120492 read SPI 0x210d4 0x2173b: 15140 us, 9050 KB/s, 72.400 Mbps
465 23:10:41.127602 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 23:10:41.128031
467 23:10:41.128423
468 23:10:41.136811 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 23:10:41.140327 ARM64: Exception handlers installed.
470 23:10:41.144062 ARM64: Testing exception
471 23:10:41.144491 ARM64: Done test exception
472 23:10:41.166049 pmic_efuse_setting: Set efuses in 11 msecs
473 23:10:41.169330 pmwrap_interface_init: Select PMIF_VLD_RDY
474 23:10:41.176156 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 23:10:41.179358 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 23:10:41.186321 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 23:10:41.189809 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 23:10:41.193140 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 23:10:41.200278 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 23:10:41.203534 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 23:10:41.211001 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 23:10:41.214206 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 23:10:41.217996 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 23:10:41.221460 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 23:10:41.229084 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 23:10:41.232780 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 23:10:41.240260 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 23:10:41.243228 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 23:10:41.250513 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 23:10:41.254208 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 23:10:41.261558 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 23:10:41.265286 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 23:10:41.272799 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 23:10:41.276238 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 23:10:41.283416 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 23:10:41.287781 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 23:10:41.294730 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 23:10:41.298466 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 23:10:41.305403 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 23:10:41.309182 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 23:10:41.316287 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 23:10:41.319478 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 23:10:41.323295 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 23:10:41.330372 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 23:10:41.333919 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 23:10:41.340942 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 23:10:41.344648 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 23:10:41.348178 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 23:10:41.356483 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 23:10:41.359704 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 23:10:41.363778 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 23:10:41.370546 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 23:10:41.374175 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 23:10:41.377855 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 23:10:41.381551 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 23:10:41.389342 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 23:10:41.392646 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 23:10:41.396020 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 23:10:41.400077 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 23:10:41.403398 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 23:10:41.407161 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 23:10:41.415080 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 23:10:41.418698 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 23:10:41.421606 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 23:10:41.429083 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 23:10:41.436336 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 23:10:41.443428 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 23:10:41.451575 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 23:10:41.458141 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 23:10:41.461920 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 23:10:41.469843 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 23:10:41.472718 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 23:10:41.480355 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6b, sec=0x26
534 23:10:41.483648 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 23:10:41.490756 [RTC]rtc_osc_init,62: osc32con val = 0xde6b
536 23:10:41.493903 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 23:10:41.503821 [RTC]rtc_get_frequency_meter,154: input=15, output=852
538 23:10:41.512946 [RTC]rtc_get_frequency_meter,154: input=7, output=724
539 23:10:41.522173 [RTC]rtc_get_frequency_meter,154: input=11, output=788
540 23:10:41.532262 [RTC]rtc_get_frequency_meter,154: input=13, output=820
541 23:10:41.541105 [RTC]rtc_get_frequency_meter,154: input=12, output=805
542 23:10:41.550696 [RTC]rtc_get_frequency_meter,154: input=11, output=789
543 23:10:41.560929 [RTC]rtc_get_frequency_meter,154: input=12, output=805
544 23:10:41.564334 [RTC]rtc_eosc_cali,47: left: 11, middle: 11, right: 12
545 23:10:41.568752 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6b
546 23:10:41.571945 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
547 23:10:41.579481 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
548 23:10:41.583104 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
549 23:10:41.587348 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
550 23:10:41.590587 ADC[4]: Raw value=903325 ID=7
551 23:10:41.590692 ADC[3]: Raw value=213916 ID=1
552 23:10:41.594093 RAM Code: 0x71
553 23:10:41.598215 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
554 23:10:41.602300 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
555 23:10:41.612577 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
556 23:10:41.616309 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
557 23:10:41.619287 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
558 23:10:41.623880 in-header: 03 07 00 00 08 00 00 00
559 23:10:41.627934 in-data: aa e4 47 04 13 02 00 00
560 23:10:41.631615 Chrome EC: UHEPI supported
561 23:10:41.638204 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
562 23:10:41.642020 in-header: 03 95 00 00 08 00 00 00
563 23:10:41.645599 in-data: 18 20 20 08 00 00 00 00
564 23:10:41.649814 MRC: failed to locate region type 0.
565 23:10:41.653165 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
566 23:10:41.657042 DRAM-K: Running full calibration
567 23:10:41.664507 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
568 23:10:41.664942 header.status = 0x0
569 23:10:41.668516 header.version = 0x6 (expected: 0x6)
570 23:10:41.672310 header.size = 0xd00 (expected: 0xd00)
571 23:10:41.675709 header.flags = 0x0
572 23:10:41.678974 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
573 23:10:41.698359 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
574 23:10:41.705398 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
575 23:10:41.709369 dram_init: ddr_geometry: 2
576 23:10:41.709801 [EMI] MDL number = 2
577 23:10:41.713259 [EMI] Get MDL freq = 0
578 23:10:41.713690 dram_init: ddr_type: 0
579 23:10:41.716413 is_discrete_lpddr4: 1
580 23:10:41.719672 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
581 23:10:41.719755
582 23:10:41.719821
583 23:10:41.722691 [Bian_co] ETT version 0.0.0.1
584 23:10:41.725668 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
585 23:10:41.725757
586 23:10:41.729413 dramc_set_vcore_voltage set vcore to 650000
587 23:10:41.733003 Read voltage for 800, 4
588 23:10:41.733099 Vio18 = 0
589 23:10:41.733174 Vcore = 650000
590 23:10:41.736872 Vdram = 0
591 23:10:41.736978 Vddq = 0
592 23:10:41.737059 Vmddr = 0
593 23:10:41.740646 dram_init: config_dvfs: 1
594 23:10:41.743922 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
595 23:10:41.751162 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
596 23:10:41.754868 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
597 23:10:41.757763 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
598 23:10:41.761446 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
599 23:10:41.765501 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
600 23:10:41.768882 MEM_TYPE=3, freq_sel=18
601 23:10:41.772428 sv_algorithm_assistance_LP4_1600
602 23:10:41.775704 ============ PULL DRAM RESETB DOWN ============
603 23:10:41.779425 ========== PULL DRAM RESETB DOWN end =========
604 23:10:41.782324 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
605 23:10:41.786178 ===================================
606 23:10:41.789164 LPDDR4 DRAM CONFIGURATION
607 23:10:41.792549 ===================================
608 23:10:41.795751 EX_ROW_EN[0] = 0x0
609 23:10:41.796178 EX_ROW_EN[1] = 0x0
610 23:10:41.799251 LP4Y_EN = 0x0
611 23:10:41.799762 WORK_FSP = 0x0
612 23:10:41.802939 WL = 0x2
613 23:10:41.803444 RL = 0x2
614 23:10:41.805733 BL = 0x2
615 23:10:41.806153 RPST = 0x0
616 23:10:41.809048 RD_PRE = 0x0
617 23:10:41.809521 WR_PRE = 0x1
618 23:10:41.812297 WR_PST = 0x0
619 23:10:41.812753 DBI_WR = 0x0
620 23:10:41.815893 DBI_RD = 0x0
621 23:10:41.815975 OTF = 0x1
622 23:10:41.819125 ===================================
623 23:10:41.821883 ===================================
624 23:10:41.825417 ANA top config
625 23:10:41.829043 ===================================
626 23:10:41.831973 DLL_ASYNC_EN = 0
627 23:10:41.832104 ALL_SLAVE_EN = 1
628 23:10:41.835106 NEW_RANK_MODE = 1
629 23:10:41.838786 DLL_IDLE_MODE = 1
630 23:10:41.841913 LP45_APHY_COMB_EN = 1
631 23:10:41.842009 TX_ODT_DIS = 1
632 23:10:41.845292 NEW_8X_MODE = 1
633 23:10:41.848533 ===================================
634 23:10:41.852070 ===================================
635 23:10:41.855357 data_rate = 1600
636 23:10:41.858491 CKR = 1
637 23:10:41.861752 DQ_P2S_RATIO = 8
638 23:10:41.865190 ===================================
639 23:10:41.869449 CA_P2S_RATIO = 8
640 23:10:41.869603 DQ_CA_OPEN = 0
641 23:10:41.872488 DQ_SEMI_OPEN = 0
642 23:10:41.875923 CA_SEMI_OPEN = 0
643 23:10:41.878891 CA_FULL_RATE = 0
644 23:10:41.882328 DQ_CKDIV4_EN = 1
645 23:10:41.882572 CA_CKDIV4_EN = 1
646 23:10:41.886118 CA_PREDIV_EN = 0
647 23:10:41.889288 PH8_DLY = 0
648 23:10:41.892422 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
649 23:10:41.896226 DQ_AAMCK_DIV = 4
650 23:10:41.899359 CA_AAMCK_DIV = 4
651 23:10:41.899826 CA_ADMCK_DIV = 4
652 23:10:41.902690 DQ_TRACK_CA_EN = 0
653 23:10:41.905642 CA_PICK = 800
654 23:10:41.908993 CA_MCKIO = 800
655 23:10:41.912937 MCKIO_SEMI = 0
656 23:10:41.916642 PLL_FREQ = 3068
657 23:10:41.916725 DQ_UI_PI_RATIO = 32
658 23:10:41.920210 CA_UI_PI_RATIO = 0
659 23:10:41.923654 ===================================
660 23:10:41.927321 ===================================
661 23:10:41.931090 memory_type:LPDDR4
662 23:10:41.931173 GP_NUM : 10
663 23:10:41.934921 SRAM_EN : 1
664 23:10:41.935003 MD32_EN : 0
665 23:10:41.938538 ===================================
666 23:10:41.942894 [ANA_INIT] >>>>>>>>>>>>>>
667 23:10:41.942979 <<<<<< [CONFIGURE PHASE]: ANA_TX
668 23:10:41.945811 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
669 23:10:41.949621 ===================================
670 23:10:41.953407 data_rate = 1600,PCW = 0X7600
671 23:10:41.956185 ===================================
672 23:10:41.959729 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
673 23:10:41.966104 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 23:10:41.973272 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
675 23:10:41.975909 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
676 23:10:41.979333 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
677 23:10:41.983047 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
678 23:10:41.985946 [ANA_INIT] flow start
679 23:10:41.986029 [ANA_INIT] PLL >>>>>>>>
680 23:10:41.989543 [ANA_INIT] PLL <<<<<<<<
681 23:10:41.992451 [ANA_INIT] MIDPI >>>>>>>>
682 23:10:41.992535 [ANA_INIT] MIDPI <<<<<<<<
683 23:10:41.995962 [ANA_INIT] DLL >>>>>>>>
684 23:10:41.999220 [ANA_INIT] flow end
685 23:10:42.002238 ============ LP4 DIFF to SE enter ============
686 23:10:42.005848 ============ LP4 DIFF to SE exit ============
687 23:10:42.009627 [ANA_INIT] <<<<<<<<<<<<<
688 23:10:42.012271 [Flow] Enable top DCM control >>>>>
689 23:10:42.015949 [Flow] Enable top DCM control <<<<<
690 23:10:42.019009 Enable DLL master slave shuffle
691 23:10:42.022300 ==============================================================
692 23:10:42.025984 Gating Mode config
693 23:10:42.031993 ==============================================================
694 23:10:42.032118 Config description:
695 23:10:42.041849 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
696 23:10:42.048634 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
697 23:10:42.055242 SELPH_MODE 0: By rank 1: By Phase
698 23:10:42.058855 ==============================================================
699 23:10:42.061970 GAT_TRACK_EN = 1
700 23:10:42.064990 RX_GATING_MODE = 2
701 23:10:42.068775 RX_GATING_TRACK_MODE = 2
702 23:10:42.072429 SELPH_MODE = 1
703 23:10:42.074834 PICG_EARLY_EN = 1
704 23:10:42.078826 VALID_LAT_VALUE = 1
705 23:10:42.082122 ==============================================================
706 23:10:42.084919 Enter into Gating configuration >>>>
707 23:10:42.088300 Exit from Gating configuration <<<<
708 23:10:42.092383 Enter into DVFS_PRE_config >>>>>
709 23:10:42.105312 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
710 23:10:42.108780 Exit from DVFS_PRE_config <<<<<
711 23:10:42.111962 Enter into PICG configuration >>>>
712 23:10:42.112401 Exit from PICG configuration <<<<
713 23:10:42.115615 [RX_INPUT] configuration >>>>>
714 23:10:42.118702 [RX_INPUT] configuration <<<<<
715 23:10:42.125501 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
716 23:10:42.128733 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
717 23:10:42.134983 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
718 23:10:42.141665 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
719 23:10:42.148303 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
720 23:10:42.155177 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
721 23:10:42.158326 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
722 23:10:42.161668 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
723 23:10:42.165178 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
724 23:10:42.171644 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
725 23:10:42.175036 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
726 23:10:42.178526 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
727 23:10:42.182090 ===================================
728 23:10:42.185882 LPDDR4 DRAM CONFIGURATION
729 23:10:42.188369 ===================================
730 23:10:42.191761 EX_ROW_EN[0] = 0x0
731 23:10:42.192192 EX_ROW_EN[1] = 0x0
732 23:10:42.195446 LP4Y_EN = 0x0
733 23:10:42.195844 WORK_FSP = 0x0
734 23:10:42.199116 WL = 0x2
735 23:10:42.199563 RL = 0x2
736 23:10:42.201903 BL = 0x2
737 23:10:42.202319 RPST = 0x0
738 23:10:42.205338 RD_PRE = 0x0
739 23:10:42.205644 WR_PRE = 0x1
740 23:10:42.208307 WR_PST = 0x0
741 23:10:42.208634 DBI_WR = 0x0
742 23:10:42.211711 DBI_RD = 0x0
743 23:10:42.212020 OTF = 0x1
744 23:10:42.215167 ===================================
745 23:10:42.221531 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
746 23:10:42.224895 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
747 23:10:42.228034 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
748 23:10:42.231594 ===================================
749 23:10:42.234749 LPDDR4 DRAM CONFIGURATION
750 23:10:42.238378 ===================================
751 23:10:42.238705 EX_ROW_EN[0] = 0x10
752 23:10:42.241352 EX_ROW_EN[1] = 0x0
753 23:10:42.244606 LP4Y_EN = 0x0
754 23:10:42.244930 WORK_FSP = 0x0
755 23:10:42.248873 WL = 0x2
756 23:10:42.249194 RL = 0x2
757 23:10:42.251398 BL = 0x2
758 23:10:42.251706 RPST = 0x0
759 23:10:42.254543 RD_PRE = 0x0
760 23:10:42.254848 WR_PRE = 0x1
761 23:10:42.258022 WR_PST = 0x0
762 23:10:42.258119 DBI_WR = 0x0
763 23:10:42.261357 DBI_RD = 0x0
764 23:10:42.261441 OTF = 0x1
765 23:10:42.264633 ===================================
766 23:10:42.271190 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
767 23:10:42.275712 nWR fixed to 40
768 23:10:42.278946 [ModeRegInit_LP4] CH0 RK0
769 23:10:42.279036 [ModeRegInit_LP4] CH0 RK1
770 23:10:42.282341 [ModeRegInit_LP4] CH1 RK0
771 23:10:42.285465 [ModeRegInit_LP4] CH1 RK1
772 23:10:42.285574 match AC timing 13
773 23:10:42.291988 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
774 23:10:42.295256 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
775 23:10:42.299282 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
776 23:10:42.305818 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
777 23:10:42.309075 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
778 23:10:42.309164 [EMI DOE] emi_dcm 0
779 23:10:42.315310 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
780 23:10:42.315418 ==
781 23:10:42.318488 Dram Type= 6, Freq= 0, CH_0, rank 0
782 23:10:42.322010 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
783 23:10:42.322115 ==
784 23:10:42.328665 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
785 23:10:42.335420 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
786 23:10:42.343268 [CA 0] Center 37 (7~68) winsize 62
787 23:10:42.346554 [CA 1] Center 37 (7~68) winsize 62
788 23:10:42.350774 [CA 2] Center 34 (4~65) winsize 62
789 23:10:42.353471 [CA 3] Center 35 (4~66) winsize 63
790 23:10:42.356883 [CA 4] Center 33 (3~64) winsize 62
791 23:10:42.359813 [CA 5] Center 33 (3~64) winsize 62
792 23:10:42.360270
793 23:10:42.363572 [CmdBusTrainingLP45] Vref(ca) range 1: 32
794 23:10:42.364003
795 23:10:42.366794 [CATrainingPosCal] consider 1 rank data
796 23:10:42.369779 u2DelayCellTimex100 = 270/100 ps
797 23:10:42.373045 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
798 23:10:42.380003 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
799 23:10:42.383132 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
800 23:10:42.386261 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
801 23:10:42.389786 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
802 23:10:42.393244 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
803 23:10:42.393964
804 23:10:42.396490 CA PerBit enable=1, Macro0, CA PI delay=33
805 23:10:42.396920
806 23:10:42.399658 [CBTSetCACLKResult] CA Dly = 33
807 23:10:42.400083 CS Dly: 5 (0~36)
808 23:10:42.403297 ==
809 23:10:42.406721 Dram Type= 6, Freq= 0, CH_0, rank 1
810 23:10:42.409622 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
811 23:10:42.410049 ==
812 23:10:42.413023 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
813 23:10:42.419670 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
814 23:10:42.429987 [CA 0] Center 38 (7~69) winsize 63
815 23:10:42.433513 [CA 1] Center 37 (7~68) winsize 62
816 23:10:42.436179 [CA 2] Center 35 (4~66) winsize 63
817 23:10:42.440113 [CA 3] Center 35 (4~66) winsize 63
818 23:10:42.443575 [CA 4] Center 34 (3~65) winsize 63
819 23:10:42.446593 [CA 5] Center 33 (3~64) winsize 62
820 23:10:42.447037
821 23:10:42.450031 [CmdBusTrainingLP45] Vref(ca) range 1: 34
822 23:10:42.450481
823 23:10:42.452958 [CATrainingPosCal] consider 2 rank data
824 23:10:42.456644 u2DelayCellTimex100 = 270/100 ps
825 23:10:42.459801 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
826 23:10:42.463241 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
827 23:10:42.469908 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
828 23:10:42.472945 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
829 23:10:42.476265 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
830 23:10:42.479498 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
831 23:10:42.479969
832 23:10:42.483101 CA PerBit enable=1, Macro0, CA PI delay=33
833 23:10:42.483569
834 23:10:42.486165 [CBTSetCACLKResult] CA Dly = 33
835 23:10:42.486624 CS Dly: 6 (0~38)
836 23:10:42.489742
837 23:10:42.492881 ----->DramcWriteLeveling(PI) begin...
838 23:10:42.493323 ==
839 23:10:42.496592 Dram Type= 6, Freq= 0, CH_0, rank 0
840 23:10:42.500230 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
841 23:10:42.500656 ==
842 23:10:42.503237 Write leveling (Byte 0): 32 => 32
843 23:10:42.506748 Write leveling (Byte 1): 28 => 28
844 23:10:42.507170 DramcWriteLeveling(PI) end<-----
845 23:10:42.507575
846 23:10:42.511466 ==
847 23:10:42.511895 Dram Type= 6, Freq= 0, CH_0, rank 0
848 23:10:42.517409 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
849 23:10:42.517869 ==
850 23:10:42.520605 [Gating] SW mode calibration
851 23:10:42.528262 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
852 23:10:42.531489 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
853 23:10:42.534395 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
854 23:10:42.540918 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
855 23:10:42.544150 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
856 23:10:42.547858 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 23:10:42.554597 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 23:10:42.557740 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 23:10:42.560959 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 23:10:42.567529 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 23:10:42.570952 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 23:10:42.574674 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 23:10:42.581415 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 23:10:42.584358 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 23:10:42.587498 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 23:10:42.594227 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 23:10:42.598106 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 23:10:42.601151 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 23:10:42.607645 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 23:10:42.611086 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
871 23:10:42.614520 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
872 23:10:42.617570 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 23:10:42.624209 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 23:10:42.627991 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 23:10:42.630619 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 23:10:42.637264 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 23:10:42.641013 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 23:10:42.644332 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
879 23:10:42.650986 0 9 8 | B1->B0 | 2322 2e2e | 1 0 | (0 0) (0 0)
880 23:10:42.654085 0 9 12 | B1->B0 | 2a2a 3434 | 0 1 | (0 0) (1 1)
881 23:10:42.657842 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 23:10:42.664178 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 23:10:42.667398 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
884 23:10:42.670686 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
885 23:10:42.677435 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
886 23:10:42.680572 0 10 4 | B1->B0 | 3434 3333 | 1 1 | (1 1) (0 1)
887 23:10:42.683853 0 10 8 | B1->B0 | 3232 2727 | 1 1 | (1 0) (1 0)
888 23:10:42.690565 0 10 12 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (0 0)
889 23:10:42.694147 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 23:10:42.697521 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 23:10:42.703775 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
892 23:10:42.707196 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
893 23:10:42.710394 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
894 23:10:42.717109 0 11 4 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
895 23:10:42.720644 0 11 8 | B1->B0 | 2323 3e3e | 0 0 | (0 0) (0 0)
896 23:10:42.723946 0 11 12 | B1->B0 | 3a3a 4646 | 1 0 | (0 0) (0 0)
897 23:10:42.729850 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 23:10:42.733440 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 23:10:42.736877 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
900 23:10:42.743266 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
901 23:10:42.747072 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
902 23:10:42.750128 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
903 23:10:42.756547 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
904 23:10:42.760357 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 23:10:42.763315 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 23:10:42.767267 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 23:10:42.773487 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 23:10:42.776934 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 23:10:42.780397 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 23:10:42.786544 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 23:10:42.790495 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 23:10:42.793490 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 23:10:42.799872 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 23:10:42.803024 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 23:10:42.806569 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
916 23:10:42.813274 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
917 23:10:42.816833 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
918 23:10:42.820127 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
919 23:10:42.826790 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
920 23:10:42.827214 Total UI for P1: 0, mck2ui 16
921 23:10:42.834261 best dqsien dly found for B0: ( 0, 14, 4)
922 23:10:42.837043 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
923 23:10:42.840112 Total UI for P1: 0, mck2ui 16
924 23:10:42.843497 best dqsien dly found for B1: ( 0, 14, 8)
925 23:10:42.847015 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
926 23:10:42.850033 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
927 23:10:42.850478
928 23:10:42.853212 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
929 23:10:42.857108 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
930 23:10:42.860234 [Gating] SW calibration Done
931 23:10:42.860681 ==
932 23:10:42.863433 Dram Type= 6, Freq= 0, CH_0, rank 0
933 23:10:42.867130 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 23:10:42.867704 ==
935 23:10:42.871043 RX Vref Scan: 0
936 23:10:42.871602
937 23:10:42.871962 RX Vref 0 -> 0, step: 1
938 23:10:42.872307
939 23:10:42.874222 RX Delay -130 -> 252, step: 16
940 23:10:42.877835 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
941 23:10:42.884390 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
942 23:10:42.887693 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
943 23:10:42.890799 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
944 23:10:42.894695 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
945 23:10:42.897806 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
946 23:10:42.904359 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
947 23:10:42.907426 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
948 23:10:42.910857 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
949 23:10:42.913809 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
950 23:10:42.917142 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
951 23:10:42.924204 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
952 23:10:42.927466 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
953 23:10:42.930771 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
954 23:10:42.933794 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
955 23:10:42.940611 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
956 23:10:42.941036 ==
957 23:10:42.943847 Dram Type= 6, Freq= 0, CH_0, rank 0
958 23:10:42.947091 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
959 23:10:42.947739 ==
960 23:10:42.948269 DQS Delay:
961 23:10:42.950437 DQS0 = 0, DQS1 = 0
962 23:10:42.951002 DQM Delay:
963 23:10:42.953613 DQM0 = 88, DQM1 = 75
964 23:10:42.954111 DQ Delay:
965 23:10:42.957271 DQ0 =93, DQ1 =85, DQ2 =85, DQ3 =85
966 23:10:42.960504 DQ4 =93, DQ5 =69, DQ6 =101, DQ7 =93
967 23:10:42.964002 DQ8 =69, DQ9 =61, DQ10 =69, DQ11 =69
968 23:10:42.967065 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
969 23:10:42.967618
970 23:10:42.967960
971 23:10:42.968273 ==
972 23:10:42.970192 Dram Type= 6, Freq= 0, CH_0, rank 0
973 23:10:42.973640 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
974 23:10:42.974065 ==
975 23:10:42.974397
976 23:10:42.974705
977 23:10:42.977180 TX Vref Scan disable
978 23:10:42.980428 == TX Byte 0 ==
979 23:10:42.983664 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
980 23:10:42.987243 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
981 23:10:42.990338 == TX Byte 1 ==
982 23:10:42.994142 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
983 23:10:42.997090 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
984 23:10:42.997512 ==
985 23:10:43.000243 Dram Type= 6, Freq= 0, CH_0, rank 0
986 23:10:43.007326 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
987 23:10:43.007793 ==
988 23:10:43.018710 TX Vref=22, minBit 4, minWin=26, winSum=436
989 23:10:43.022273 TX Vref=24, minBit 4, minWin=26, winSum=442
990 23:10:43.026099 TX Vref=26, minBit 1, minWin=27, winSum=446
991 23:10:43.028883 TX Vref=28, minBit 1, minWin=27, winSum=450
992 23:10:43.032048 TX Vref=30, minBit 1, minWin=27, winSum=452
993 23:10:43.038686 TX Vref=32, minBit 2, minWin=27, winSum=453
994 23:10:43.042205 [TxChooseVref] Worse bit 2, Min win 27, Win sum 453, Final Vref 32
995 23:10:43.042644
996 23:10:43.045352 Final TX Range 1 Vref 32
997 23:10:43.045781
998 23:10:43.046298 ==
999 23:10:43.049601 Dram Type= 6, Freq= 0, CH_0, rank 0
1000 23:10:43.052020 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1001 23:10:43.052445 ==
1002 23:10:43.055140
1003 23:10:43.055247
1004 23:10:43.055339 TX Vref Scan disable
1005 23:10:43.058361 == TX Byte 0 ==
1006 23:10:43.061646 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1007 23:10:43.068223 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1008 23:10:43.068311 == TX Byte 1 ==
1009 23:10:43.071680 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1010 23:10:43.078604 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1011 23:10:43.078708
1012 23:10:43.078789 [DATLAT]
1013 23:10:43.078863 Freq=800, CH0 RK0
1014 23:10:43.078935
1015 23:10:43.081964 DATLAT Default: 0xa
1016 23:10:43.082075 0, 0xFFFF, sum = 0
1017 23:10:43.084932 1, 0xFFFF, sum = 0
1018 23:10:43.088070 2, 0xFFFF, sum = 0
1019 23:10:43.088194 3, 0xFFFF, sum = 0
1020 23:10:43.091848 4, 0xFFFF, sum = 0
1021 23:10:43.091985 5, 0xFFFF, sum = 0
1022 23:10:43.094733 6, 0xFFFF, sum = 0
1023 23:10:43.094935 7, 0xFFFF, sum = 0
1024 23:10:43.098019 8, 0xFFFF, sum = 0
1025 23:10:43.098215 9, 0x0, sum = 1
1026 23:10:43.102027 10, 0x0, sum = 2
1027 23:10:43.102205 11, 0x0, sum = 3
1028 23:10:43.104885 12, 0x0, sum = 4
1029 23:10:43.105086 best_step = 10
1030 23:10:43.105245
1031 23:10:43.105391 ==
1032 23:10:43.108084 Dram Type= 6, Freq= 0, CH_0, rank 0
1033 23:10:43.111711 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1034 23:10:43.112129 ==
1035 23:10:43.114872 RX Vref Scan: 1
1036 23:10:43.115285
1037 23:10:43.118848 Set Vref Range= 32 -> 127
1038 23:10:43.119264
1039 23:10:43.119648 RX Vref 32 -> 127, step: 1
1040 23:10:43.119961
1041 23:10:43.122068 RX Delay -95 -> 252, step: 8
1042 23:10:43.122483
1043 23:10:43.125033 Set Vref, RX VrefLevel [Byte0]: 32
1044 23:10:43.128381 [Byte1]: 32
1045 23:10:43.131929
1046 23:10:43.132345 Set Vref, RX VrefLevel [Byte0]: 33
1047 23:10:43.134940 [Byte1]: 33
1048 23:10:43.140151
1049 23:10:43.140572 Set Vref, RX VrefLevel [Byte0]: 34
1050 23:10:43.143308 [Byte1]: 34
1051 23:10:43.146844
1052 23:10:43.147255 Set Vref, RX VrefLevel [Byte0]: 35
1053 23:10:43.150076 [Byte1]: 35
1054 23:10:43.154687
1055 23:10:43.155158 Set Vref, RX VrefLevel [Byte0]: 36
1056 23:10:43.157750 [Byte1]: 36
1057 23:10:43.161862
1058 23:10:43.162273 Set Vref, RX VrefLevel [Byte0]: 37
1059 23:10:43.165651 [Byte1]: 37
1060 23:10:43.170009
1061 23:10:43.170485 Set Vref, RX VrefLevel [Byte0]: 38
1062 23:10:43.173342 [Byte1]: 38
1063 23:10:43.178027
1064 23:10:43.178442 Set Vref, RX VrefLevel [Byte0]: 39
1065 23:10:43.181237 [Byte1]: 39
1066 23:10:43.185248
1067 23:10:43.185661 Set Vref, RX VrefLevel [Byte0]: 40
1068 23:10:43.188968 [Byte1]: 40
1069 23:10:43.192573
1070 23:10:43.192989 Set Vref, RX VrefLevel [Byte0]: 41
1071 23:10:43.196271 [Byte1]: 41
1072 23:10:43.200167
1073 23:10:43.200581 Set Vref, RX VrefLevel [Byte0]: 42
1074 23:10:43.203307 [Byte1]: 42
1075 23:10:43.207497
1076 23:10:43.207992 Set Vref, RX VrefLevel [Byte0]: 43
1077 23:10:43.210590 [Byte1]: 43
1078 23:10:43.215181
1079 23:10:43.215713 Set Vref, RX VrefLevel [Byte0]: 44
1080 23:10:43.218598 [Byte1]: 44
1081 23:10:43.222740
1082 23:10:43.223205 Set Vref, RX VrefLevel [Byte0]: 45
1083 23:10:43.226443 [Byte1]: 45
1084 23:10:43.230549
1085 23:10:43.231009 Set Vref, RX VrefLevel [Byte0]: 46
1086 23:10:43.233760 [Byte1]: 46
1087 23:10:43.237928
1088 23:10:43.238412 Set Vref, RX VrefLevel [Byte0]: 47
1089 23:10:43.241205 [Byte1]: 47
1090 23:10:43.245620
1091 23:10:43.246057 Set Vref, RX VrefLevel [Byte0]: 48
1092 23:10:43.249910 [Byte1]: 48
1093 23:10:43.253301
1094 23:10:43.253711 Set Vref, RX VrefLevel [Byte0]: 49
1095 23:10:43.256593 [Byte1]: 49
1096 23:10:43.261272
1097 23:10:43.261687 Set Vref, RX VrefLevel [Byte0]: 50
1098 23:10:43.263966 [Byte1]: 50
1099 23:10:43.268144
1100 23:10:43.268626 Set Vref, RX VrefLevel [Byte0]: 51
1101 23:10:43.271390 [Byte1]: 51
1102 23:10:43.275663
1103 23:10:43.275746 Set Vref, RX VrefLevel [Byte0]: 52
1104 23:10:43.278746 [Byte1]: 52
1105 23:10:43.282936
1106 23:10:43.283042 Set Vref, RX VrefLevel [Byte0]: 53
1107 23:10:43.286657 [Byte1]: 53
1108 23:10:43.291336
1109 23:10:43.291435 Set Vref, RX VrefLevel [Byte0]: 54
1110 23:10:43.294008 [Byte1]: 54
1111 23:10:43.298365
1112 23:10:43.298490 Set Vref, RX VrefLevel [Byte0]: 55
1113 23:10:43.301856 [Byte1]: 55
1114 23:10:43.305963
1115 23:10:43.306071 Set Vref, RX VrefLevel [Byte0]: 56
1116 23:10:43.309124 [Byte1]: 56
1117 23:10:43.314012
1118 23:10:43.314136 Set Vref, RX VrefLevel [Byte0]: 57
1119 23:10:43.316693 [Byte1]: 57
1120 23:10:43.321393
1121 23:10:43.321541 Set Vref, RX VrefLevel [Byte0]: 58
1122 23:10:43.324604 [Byte1]: 58
1123 23:10:43.329081
1124 23:10:43.329250 Set Vref, RX VrefLevel [Byte0]: 59
1125 23:10:43.332023 [Byte1]: 59
1126 23:10:43.336304
1127 23:10:43.336568 Set Vref, RX VrefLevel [Byte0]: 60
1128 23:10:43.339706 [Byte1]: 60
1129 23:10:43.344036
1130 23:10:43.344423 Set Vref, RX VrefLevel [Byte0]: 61
1131 23:10:43.347394 [Byte1]: 61
1132 23:10:43.351842
1133 23:10:43.352311 Set Vref, RX VrefLevel [Byte0]: 62
1134 23:10:43.355142 [Byte1]: 62
1135 23:10:43.359867
1136 23:10:43.360282 Set Vref, RX VrefLevel [Byte0]: 63
1137 23:10:43.363453 [Byte1]: 63
1138 23:10:43.366824
1139 23:10:43.367297 Set Vref, RX VrefLevel [Byte0]: 64
1140 23:10:43.370432 [Byte1]: 64
1141 23:10:43.374732
1142 23:10:43.375192 Set Vref, RX VrefLevel [Byte0]: 65
1143 23:10:43.377922 [Byte1]: 65
1144 23:10:43.382388
1145 23:10:43.382849 Set Vref, RX VrefLevel [Byte0]: 66
1146 23:10:43.385698 [Byte1]: 66
1147 23:10:43.389694
1148 23:10:43.390109 Set Vref, RX VrefLevel [Byte0]: 67
1149 23:10:43.392977 [Byte1]: 67
1150 23:10:43.397453
1151 23:10:43.397949 Set Vref, RX VrefLevel [Byte0]: 68
1152 23:10:43.415018 [Byte1]: 68
1153 23:10:43.415511
1154 23:10:43.415851 Set Vref, RX VrefLevel [Byte0]: 69
1155 23:10:43.416164 [Byte1]: 69
1156 23:10:43.416461
1157 23:10:43.416751 Set Vref, RX VrefLevel [Byte0]: 70
1158 23:10:43.417372 [Byte1]: 70
1159 23:10:43.420500
1160 23:10:43.420912 Set Vref, RX VrefLevel [Byte0]: 71
1161 23:10:43.423956 [Byte1]: 71
1162 23:10:43.428115
1163 23:10:43.428529 Set Vref, RX VrefLevel [Byte0]: 72
1164 23:10:43.431141 [Byte1]: 72
1165 23:10:43.435849
1166 23:10:43.436279 Set Vref, RX VrefLevel [Byte0]: 73
1167 23:10:43.439226 [Byte1]: 73
1168 23:10:43.443125
1169 23:10:43.443660 Set Vref, RX VrefLevel [Byte0]: 74
1170 23:10:43.446192 [Byte1]: 74
1171 23:10:43.450919
1172 23:10:43.451523 Final RX Vref Byte 0 = 56 to rank0
1173 23:10:43.453617 Final RX Vref Byte 1 = 57 to rank0
1174 23:10:43.457516 Final RX Vref Byte 0 = 56 to rank1
1175 23:10:43.460723 Final RX Vref Byte 1 = 57 to rank1==
1176 23:10:43.464374 Dram Type= 6, Freq= 0, CH_0, rank 0
1177 23:10:43.470288 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1178 23:10:43.470799 ==
1179 23:10:43.471139 DQS Delay:
1180 23:10:43.471483 DQS0 = 0, DQS1 = 0
1181 23:10:43.474658 DQM Delay:
1182 23:10:43.475206 DQM0 = 87, DQM1 = 75
1183 23:10:43.477112 DQ Delay:
1184 23:10:43.480878 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1185 23:10:43.483549 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1186 23:10:43.487445 DQ8 =68, DQ9 =60, DQ10 =76, DQ11 =68
1187 23:10:43.490566 DQ12 =84, DQ13 =80, DQ14 =84, DQ15 =84
1188 23:10:43.491010
1189 23:10:43.491524
1190 23:10:43.496924 [DQSOSCAuto] RK0, (LSB)MR18= 0x2a24, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 399 ps
1191 23:10:43.500063 CH0 RK0: MR19=606, MR18=2A24
1192 23:10:43.507188 CH0_RK0: MR19=0x606, MR18=0x2A24, DQSOSC=399, MR23=63, INC=92, DEC=61
1193 23:10:43.507883
1194 23:10:43.510500 ----->DramcWriteLeveling(PI) begin...
1195 23:10:43.510922 ==
1196 23:10:43.514123 Dram Type= 6, Freq= 0, CH_0, rank 1
1197 23:10:43.516942 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1198 23:10:43.517363 ==
1199 23:10:43.520134 Write leveling (Byte 0): 33 => 33
1200 23:10:43.523503 Write leveling (Byte 1): 28 => 28
1201 23:10:43.527265 DramcWriteLeveling(PI) end<-----
1202 23:10:43.527596
1203 23:10:43.527837 ==
1204 23:10:43.530011 Dram Type= 6, Freq= 0, CH_0, rank 1
1205 23:10:43.533210 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1206 23:10:43.533437 ==
1207 23:10:43.536688 [Gating] SW mode calibration
1208 23:10:43.543001 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1209 23:10:43.549899 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1210 23:10:43.553465 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1211 23:10:43.556378 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1212 23:10:43.600682 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1213 23:10:43.601202 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1214 23:10:43.601488 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1215 23:10:43.601561 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1216 23:10:43.601624 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1217 23:10:43.601682 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1218 23:10:43.602189 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1219 23:10:43.602475 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1220 23:10:43.602544 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 23:10:43.602606 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 23:10:43.630758 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 23:10:43.631286 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 23:10:43.631607 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 23:10:43.631693 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 23:10:43.631767 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 23:10:43.632297 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 23:10:43.634947 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1229 23:10:43.638947 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 23:10:43.641890 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 23:10:43.645069 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 23:10:43.651547 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 23:10:43.655588 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 23:10:43.658498 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 23:10:43.664896 0 9 4 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
1236 23:10:43.668170 0 9 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
1237 23:10:43.671855 0 9 12 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
1238 23:10:43.677952 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1239 23:10:43.681704 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1240 23:10:43.685204 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1241 23:10:43.691708 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1242 23:10:43.694643 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1243 23:10:43.697945 0 10 4 | B1->B0 | 3434 3030 | 1 1 | (1 1) (0 1)
1244 23:10:43.701502 0 10 8 | B1->B0 | 3232 2323 | 0 0 | (1 1) (0 0)
1245 23:10:43.708126 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1246 23:10:43.711738 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1247 23:10:43.714769 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1248 23:10:43.721274 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1249 23:10:43.724589 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1250 23:10:43.728028 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1251 23:10:43.734598 0 11 4 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
1252 23:10:43.738213 0 11 8 | B1->B0 | 3535 4646 | 0 0 | (1 1) (0 0)
1253 23:10:43.742114 0 11 12 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
1254 23:10:43.745288 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1255 23:10:43.752847 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1256 23:10:43.756776 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1257 23:10:43.759930 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1258 23:10:43.763062 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1259 23:10:43.770143 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1260 23:10:43.773619 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1261 23:10:43.776922 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1262 23:10:43.783201 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1263 23:10:43.786720 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1264 23:10:43.790065 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1265 23:10:43.796858 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1266 23:10:43.799916 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1267 23:10:43.803685 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1268 23:10:43.810086 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1269 23:10:43.813148 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1270 23:10:43.816841 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1271 23:10:43.823581 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1272 23:10:43.826860 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1273 23:10:43.830157 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1274 23:10:43.832884 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 23:10:43.840221 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1276 23:10:43.843851 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1277 23:10:43.847095 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1278 23:10:43.849921 Total UI for P1: 0, mck2ui 16
1279 23:10:43.853167 best dqsien dly found for B0: ( 0, 14, 6)
1280 23:10:43.856235 Total UI for P1: 0, mck2ui 16
1281 23:10:43.859772 best dqsien dly found for B1: ( 0, 14, 8)
1282 23:10:43.863072 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1283 23:10:43.866379 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1284 23:10:43.869648
1285 23:10:43.873002 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1286 23:10:43.876387 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1287 23:10:43.880445 [Gating] SW calibration Done
1288 23:10:43.880529 ==
1289 23:10:43.882963 Dram Type= 6, Freq= 0, CH_0, rank 1
1290 23:10:43.886734 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1291 23:10:43.886816 ==
1292 23:10:43.886880 RX Vref Scan: 0
1293 23:10:43.886941
1294 23:10:43.889701 RX Vref 0 -> 0, step: 1
1295 23:10:43.889782
1296 23:10:43.893125 RX Delay -130 -> 252, step: 16
1297 23:10:43.896524 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1298 23:10:43.899616 iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224
1299 23:10:43.906719 iDelay=206, Bit 2, Center 85 (-18 ~ 189) 208
1300 23:10:43.910326 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1301 23:10:43.913005 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1302 23:10:43.916250 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
1303 23:10:43.919547 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1304 23:10:43.926168 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1305 23:10:43.929405 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1306 23:10:43.933220 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1307 23:10:43.936197 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
1308 23:10:43.939539 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1309 23:10:43.946817 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1310 23:10:43.950196 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1311 23:10:43.952884 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
1312 23:10:43.956399 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1313 23:10:43.956481 ==
1314 23:10:43.959231 Dram Type= 6, Freq= 0, CH_0, rank 1
1315 23:10:43.965999 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1316 23:10:43.966084 ==
1317 23:10:43.966149 DQS Delay:
1318 23:10:43.966209 DQS0 = 0, DQS1 = 0
1319 23:10:43.969797 DQM Delay:
1320 23:10:43.969879 DQM0 = 88, DQM1 = 78
1321 23:10:43.972502 DQ Delay:
1322 23:10:43.975980 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
1323 23:10:43.979535 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93
1324 23:10:43.982260 DQ8 =69, DQ9 =61, DQ10 =77, DQ11 =69
1325 23:10:43.985706 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85
1326 23:10:43.985789
1327 23:10:43.985853
1328 23:10:43.985912 ==
1329 23:10:43.989123 Dram Type= 6, Freq= 0, CH_0, rank 1
1330 23:10:43.992493 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1331 23:10:43.992586 ==
1332 23:10:43.992651
1333 23:10:43.992711
1334 23:10:43.995800 TX Vref Scan disable
1335 23:10:43.995882 == TX Byte 0 ==
1336 23:10:44.002508 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1337 23:10:44.005849 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1338 23:10:44.005946 == TX Byte 1 ==
1339 23:10:44.012572 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1340 23:10:44.015875 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1341 23:10:44.015993 ==
1342 23:10:44.019166 Dram Type= 6, Freq= 0, CH_0, rank 1
1343 23:10:44.022492 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1344 23:10:44.022575 ==
1345 23:10:44.037105 TX Vref=22, minBit 1, minWin=27, winSum=441
1346 23:10:44.040395 TX Vref=24, minBit 1, minWin=27, winSum=443
1347 23:10:44.043915 TX Vref=26, minBit 2, minWin=27, winSum=448
1348 23:10:44.047186 TX Vref=28, minBit 1, minWin=27, winSum=449
1349 23:10:44.050831 TX Vref=30, minBit 2, minWin=27, winSum=449
1350 23:10:44.053424 TX Vref=32, minBit 1, minWin=27, winSum=446
1351 23:10:44.060495 [TxChooseVref] Worse bit 1, Min win 27, Win sum 449, Final Vref 28
1352 23:10:44.060580
1353 23:10:44.064033 Final TX Range 1 Vref 28
1354 23:10:44.064130
1355 23:10:44.064197 ==
1356 23:10:44.066913 Dram Type= 6, Freq= 0, CH_0, rank 1
1357 23:10:44.070022 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1358 23:10:44.070118 ==
1359 23:10:44.070183
1360 23:10:44.073338
1361 23:10:44.073419 TX Vref Scan disable
1362 23:10:44.076819 == TX Byte 0 ==
1363 23:10:44.080650 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1364 23:10:44.087205 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1365 23:10:44.087289 == TX Byte 1 ==
1366 23:10:44.090422 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1367 23:10:44.096747 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1368 23:10:44.096830
1369 23:10:44.096894 [DATLAT]
1370 23:10:44.096952 Freq=800, CH0 RK1
1371 23:10:44.097009
1372 23:10:44.100384 DATLAT Default: 0xa
1373 23:10:44.100466 0, 0xFFFF, sum = 0
1374 23:10:44.103553 1, 0xFFFF, sum = 0
1375 23:10:44.103635 2, 0xFFFF, sum = 0
1376 23:10:44.106717 3, 0xFFFF, sum = 0
1377 23:10:44.110690 4, 0xFFFF, sum = 0
1378 23:10:44.110773 5, 0xFFFF, sum = 0
1379 23:10:44.113442 6, 0xFFFF, sum = 0
1380 23:10:44.113524 7, 0xFFFF, sum = 0
1381 23:10:44.116857 8, 0xFFFF, sum = 0
1382 23:10:44.116939 9, 0x0, sum = 1
1383 23:10:44.117004 10, 0x0, sum = 2
1384 23:10:44.120060 11, 0x0, sum = 3
1385 23:10:44.120141 12, 0x0, sum = 4
1386 23:10:44.123302 best_step = 10
1387 23:10:44.123422
1388 23:10:44.123486 ==
1389 23:10:44.126661 Dram Type= 6, Freq= 0, CH_0, rank 1
1390 23:10:44.129883 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1391 23:10:44.129967 ==
1392 23:10:44.133386 RX Vref Scan: 0
1393 23:10:44.133467
1394 23:10:44.133530 RX Vref 0 -> 0, step: 1
1395 23:10:44.133591
1396 23:10:44.137004 RX Delay -95 -> 252, step: 8
1397 23:10:44.143314 iDelay=209, Bit 0, Center 84 (-23 ~ 192) 216
1398 23:10:44.146854 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1399 23:10:44.150124 iDelay=209, Bit 2, Center 80 (-31 ~ 192) 224
1400 23:10:44.153404 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
1401 23:10:44.156751 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1402 23:10:44.163406 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1403 23:10:44.166589 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1404 23:10:44.170075 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1405 23:10:44.173393 iDelay=209, Bit 8, Center 68 (-47 ~ 184) 232
1406 23:10:44.176635 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
1407 23:10:44.183809 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1408 23:10:44.187013 iDelay=209, Bit 11, Center 72 (-39 ~ 184) 224
1409 23:10:44.190335 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
1410 23:10:44.193120 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1411 23:10:44.200298 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1412 23:10:44.203319 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1413 23:10:44.203442 ==
1414 23:10:44.207074 Dram Type= 6, Freq= 0, CH_0, rank 1
1415 23:10:44.210341 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1416 23:10:44.210423 ==
1417 23:10:44.213484 DQS Delay:
1418 23:10:44.213563 DQS0 = 0, DQS1 = 0
1419 23:10:44.213626 DQM Delay:
1420 23:10:44.216924 DQM0 = 86, DQM1 = 77
1421 23:10:44.217005 DQ Delay:
1422 23:10:44.219527 DQ0 =84, DQ1 =88, DQ2 =80, DQ3 =80
1423 23:10:44.223080 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1424 23:10:44.227264 DQ8 =68, DQ9 =64, DQ10 =80, DQ11 =72
1425 23:10:44.230024 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =84
1426 23:10:44.230105
1427 23:10:44.230168
1428 23:10:44.239505 [DQSOSCAuto] RK1, (LSB)MR18= 0x2521, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 400 ps
1429 23:10:44.239664 CH0 RK1: MR19=606, MR18=2521
1430 23:10:44.247027 CH0_RK1: MR19=0x606, MR18=0x2521, DQSOSC=400, MR23=63, INC=92, DEC=61
1431 23:10:44.249584 [RxdqsGatingPostProcess] freq 800
1432 23:10:44.256360 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1433 23:10:44.260378 Pre-setting of DQS Precalculation
1434 23:10:44.263080 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1435 23:10:44.263239 ==
1436 23:10:44.266344 Dram Type= 6, Freq= 0, CH_1, rank 0
1437 23:10:44.273165 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1438 23:10:44.273325 ==
1439 23:10:44.276346 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1440 23:10:44.283082 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1441 23:10:44.292432 [CA 0] Center 37 (6~68) winsize 63
1442 23:10:44.295398 [CA 1] Center 37 (6~68) winsize 63
1443 23:10:44.299104 [CA 2] Center 35 (5~66) winsize 62
1444 23:10:44.302247 [CA 3] Center 34 (4~65) winsize 62
1445 23:10:44.305690 [CA 4] Center 35 (4~66) winsize 63
1446 23:10:44.309216 [CA 5] Center 34 (4~65) winsize 62
1447 23:10:44.309469
1448 23:10:44.312074 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1449 23:10:44.312278
1450 23:10:44.316351 [CATrainingPosCal] consider 1 rank data
1451 23:10:44.318820 u2DelayCellTimex100 = 270/100 ps
1452 23:10:44.322585 CA0 delay=37 (6~68),Diff = 3 PI (21 cell)
1453 23:10:44.325734 CA1 delay=37 (6~68),Diff = 3 PI (21 cell)
1454 23:10:44.331981 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
1455 23:10:44.334952 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1456 23:10:44.338390 CA4 delay=35 (4~66),Diff = 1 PI (7 cell)
1457 23:10:44.342069 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1458 23:10:44.342219
1459 23:10:44.345408 CA PerBit enable=1, Macro0, CA PI delay=34
1460 23:10:44.345553
1461 23:10:44.348461 [CBTSetCACLKResult] CA Dly = 34
1462 23:10:44.348576 CS Dly: 4 (0~35)
1463 23:10:44.352066 ==
1464 23:10:44.352187 Dram Type= 6, Freq= 0, CH_1, rank 1
1465 23:10:44.358531 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1466 23:10:44.358675 ==
1467 23:10:44.361487 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1468 23:10:44.368277 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1469 23:10:44.378227 [CA 0] Center 36 (6~67) winsize 62
1470 23:10:44.381786 [CA 1] Center 37 (6~68) winsize 63
1471 23:10:44.384537 [CA 2] Center 35 (5~66) winsize 62
1472 23:10:44.388235 [CA 3] Center 34 (4~65) winsize 62
1473 23:10:44.392138 [CA 4] Center 34 (4~65) winsize 62
1474 23:10:44.394633 [CA 5] Center 34 (4~65) winsize 62
1475 23:10:44.394829
1476 23:10:44.398071 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1477 23:10:44.398261
1478 23:10:44.401101 [CATrainingPosCal] consider 2 rank data
1479 23:10:44.404580 u2DelayCellTimex100 = 270/100 ps
1480 23:10:44.409031 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1481 23:10:44.412203 CA1 delay=37 (6~68),Diff = 3 PI (21 cell)
1482 23:10:44.415565 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
1483 23:10:44.419774 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1484 23:10:44.423597 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1485 23:10:44.426520 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1486 23:10:44.426791
1487 23:10:44.429999 CA PerBit enable=1, Macro0, CA PI delay=34
1488 23:10:44.430301
1489 23:10:44.434468 [CBTSetCACLKResult] CA Dly = 34
1490 23:10:44.438193 CS Dly: 5 (0~37)
1491 23:10:44.438665
1492 23:10:44.441285 ----->DramcWriteLeveling(PI) begin...
1493 23:10:44.441708 ==
1494 23:10:44.445035 Dram Type= 6, Freq= 0, CH_1, rank 0
1495 23:10:44.448016 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1496 23:10:44.448506 ==
1497 23:10:44.451223 Write leveling (Byte 0): 23 => 23
1498 23:10:44.454666 Write leveling (Byte 1): 26 => 26
1499 23:10:44.458414 DramcWriteLeveling(PI) end<-----
1500 23:10:44.458977
1501 23:10:44.459322 ==
1502 23:10:44.461652 Dram Type= 6, Freq= 0, CH_1, rank 0
1503 23:10:44.465044 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1504 23:10:44.465563 ==
1505 23:10:44.467962 [Gating] SW mode calibration
1506 23:10:44.474651 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1507 23:10:44.480892 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1508 23:10:44.484171 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1509 23:10:44.488106 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1510 23:10:44.494833 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1511 23:10:44.498225 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1512 23:10:44.501461 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1513 23:10:44.507498 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1514 23:10:44.511881 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1515 23:10:44.515284 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1516 23:10:44.521009 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1517 23:10:44.524833 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1518 23:10:44.527631 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 23:10:44.534709 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 23:10:44.537520 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 23:10:44.540852 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 23:10:44.544277 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 23:10:44.551741 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 23:10:44.554340 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 23:10:44.557231 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1526 23:10:44.563818 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 23:10:44.567275 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 23:10:44.571468 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 23:10:44.577686 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 23:10:44.580972 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 23:10:44.583949 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 23:10:44.590382 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 23:10:44.593775 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 23:10:44.597255 0 9 8 | B1->B0 | 2d2d 3434 | 1 0 | (1 1) (0 0)
1535 23:10:44.603951 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1536 23:10:44.607649 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1537 23:10:44.611070 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1538 23:10:44.618180 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1539 23:10:44.620226 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1540 23:10:44.623929 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1541 23:10:44.631031 0 10 4 | B1->B0 | 3333 3232 | 1 1 | (1 0) (1 1)
1542 23:10:44.634075 0 10 8 | B1->B0 | 2929 2525 | 0 0 | (1 0) (0 0)
1543 23:10:44.637199 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1544 23:10:44.644026 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1545 23:10:44.647057 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1546 23:10:44.650371 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1547 23:10:44.657286 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1548 23:10:44.660554 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1549 23:10:44.664000 0 11 4 | B1->B0 | 2626 2b2b | 0 0 | (0 0) (0 0)
1550 23:10:44.670923 0 11 8 | B1->B0 | 3939 3f3f | 1 0 | (0 0) (1 1)
1551 23:10:44.674078 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1552 23:10:44.676792 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1553 23:10:44.683956 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1554 23:10:44.687084 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1555 23:10:44.690956 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1556 23:10:44.693846 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1557 23:10:44.700876 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1558 23:10:44.703211 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1559 23:10:44.707090 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1560 23:10:44.713887 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1561 23:10:44.717520 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1562 23:10:44.719875 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1563 23:10:44.726768 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1564 23:10:44.730383 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1565 23:10:44.733441 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1566 23:10:44.740090 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1567 23:10:44.743959 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1568 23:10:44.746291 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1569 23:10:44.753080 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1570 23:10:44.756374 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 23:10:44.759774 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 23:10:44.766246 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 23:10:44.770103 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1574 23:10:44.773478 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1575 23:10:44.776231 Total UI for P1: 0, mck2ui 16
1576 23:10:44.779657 best dqsien dly found for B0: ( 0, 14, 4)
1577 23:10:44.782937 Total UI for P1: 0, mck2ui 16
1578 23:10:44.786039 best dqsien dly found for B1: ( 0, 14, 4)
1579 23:10:44.790177 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1580 23:10:44.792993 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1581 23:10:44.793405
1582 23:10:44.799904 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1583 23:10:44.802556 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1584 23:10:44.806042 [Gating] SW calibration Done
1585 23:10:44.806453 ==
1586 23:10:44.809787 Dram Type= 6, Freq= 0, CH_1, rank 0
1587 23:10:44.812734 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1588 23:10:44.813258 ==
1589 23:10:44.813595 RX Vref Scan: 0
1590 23:10:44.813902
1591 23:10:44.815893 RX Vref 0 -> 0, step: 1
1592 23:10:44.816304
1593 23:10:44.818994 RX Delay -130 -> 252, step: 16
1594 23:10:44.822563 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1595 23:10:44.826097 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1596 23:10:44.833048 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1597 23:10:44.835916 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1598 23:10:44.839161 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1599 23:10:44.842899 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1600 23:10:44.846148 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1601 23:10:44.852229 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1602 23:10:44.856215 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1603 23:10:44.859687 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1604 23:10:44.863056 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1605 23:10:44.865908 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1606 23:10:44.872327 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1607 23:10:44.875613 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1608 23:10:44.878867 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1609 23:10:44.882690 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1610 23:10:44.883294 ==
1611 23:10:44.885420 Dram Type= 6, Freq= 0, CH_1, rank 0
1612 23:10:44.892526 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1613 23:10:44.893083 ==
1614 23:10:44.893417 DQS Delay:
1615 23:10:44.895617 DQS0 = 0, DQS1 = 0
1616 23:10:44.896028 DQM Delay:
1617 23:10:44.896351 DQM0 = 87, DQM1 = 78
1618 23:10:44.899172 DQ Delay:
1619 23:10:44.902174 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85
1620 23:10:44.905734 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1621 23:10:44.908839 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1622 23:10:44.912224 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1623 23:10:44.912931
1624 23:10:44.913282
1625 23:10:44.913587 ==
1626 23:10:44.916007 Dram Type= 6, Freq= 0, CH_1, rank 0
1627 23:10:44.918958 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1628 23:10:44.919519 ==
1629 23:10:44.919860
1630 23:10:44.920164
1631 23:10:44.922304 TX Vref Scan disable
1632 23:10:44.922710 == TX Byte 0 ==
1633 23:10:44.929486 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
1634 23:10:44.932401 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
1635 23:10:44.935914 == TX Byte 1 ==
1636 23:10:44.939073 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1637 23:10:44.942785 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1638 23:10:44.943334 ==
1639 23:10:44.945634 Dram Type= 6, Freq= 0, CH_1, rank 0
1640 23:10:44.949240 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1641 23:10:44.949676 ==
1642 23:10:44.963635 TX Vref=22, minBit 3, minWin=26, winSum=437
1643 23:10:44.966771 TX Vref=24, minBit 0, minWin=26, winSum=440
1644 23:10:44.970228 TX Vref=26, minBit 0, minWin=27, winSum=445
1645 23:10:44.973909 TX Vref=28, minBit 5, minWin=26, winSum=447
1646 23:10:44.976717 TX Vref=30, minBit 1, minWin=27, winSum=453
1647 23:10:44.980356 TX Vref=32, minBit 1, minWin=27, winSum=454
1648 23:10:44.987165 [TxChooseVref] Worse bit 1, Min win 27, Win sum 454, Final Vref 32
1649 23:10:44.987922
1650 23:10:44.990796 Final TX Range 1 Vref 32
1651 23:10:44.991327
1652 23:10:44.991716 ==
1653 23:10:44.994467 Dram Type= 6, Freq= 0, CH_1, rank 0
1654 23:10:44.997453 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1655 23:10:44.997863 ==
1656 23:10:44.998182
1657 23:10:44.998478
1658 23:10:45.001274 TX Vref Scan disable
1659 23:10:45.004561 == TX Byte 0 ==
1660 23:10:45.007273 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
1661 23:10:45.010776 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
1662 23:10:45.014388 == TX Byte 1 ==
1663 23:10:45.018253 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1664 23:10:45.021212 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1665 23:10:45.021756
1666 23:10:45.024390 [DATLAT]
1667 23:10:45.024891 Freq=800, CH1 RK0
1668 23:10:45.025220
1669 23:10:45.027735 DATLAT Default: 0xa
1670 23:10:45.028277 0, 0xFFFF, sum = 0
1671 23:10:45.030976 1, 0xFFFF, sum = 0
1672 23:10:45.031542 2, 0xFFFF, sum = 0
1673 23:10:45.034340 3, 0xFFFF, sum = 0
1674 23:10:45.034757 4, 0xFFFF, sum = 0
1675 23:10:45.037402 5, 0xFFFF, sum = 0
1676 23:10:45.037815 6, 0xFFFF, sum = 0
1677 23:10:45.040740 7, 0xFFFF, sum = 0
1678 23:10:45.041253 8, 0xFFFF, sum = 0
1679 23:10:45.043818 9, 0x0, sum = 1
1680 23:10:45.044233 10, 0x0, sum = 2
1681 23:10:45.047201 11, 0x0, sum = 3
1682 23:10:45.047682 12, 0x0, sum = 4
1683 23:10:45.050318 best_step = 10
1684 23:10:45.050729
1685 23:10:45.051053 ==
1686 23:10:45.053887 Dram Type= 6, Freq= 0, CH_1, rank 0
1687 23:10:45.057524 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1688 23:10:45.058108 ==
1689 23:10:45.058456 RX Vref Scan: 1
1690 23:10:45.060776
1691 23:10:45.061182 Set Vref Range= 32 -> 127
1692 23:10:45.061506
1693 23:10:45.064031 RX Vref 32 -> 127, step: 1
1694 23:10:45.064441
1695 23:10:45.067496 RX Delay -95 -> 252, step: 8
1696 23:10:45.067905
1697 23:10:45.070601 Set Vref, RX VrefLevel [Byte0]: 32
1698 23:10:45.074555 [Byte1]: 32
1699 23:10:45.075057
1700 23:10:45.077385 Set Vref, RX VrefLevel [Byte0]: 33
1701 23:10:45.080305 [Byte1]: 33
1702 23:10:45.080718
1703 23:10:45.084001 Set Vref, RX VrefLevel [Byte0]: 34
1704 23:10:45.087201 [Byte1]: 34
1705 23:10:45.091408
1706 23:10:45.091924 Set Vref, RX VrefLevel [Byte0]: 35
1707 23:10:45.094700 [Byte1]: 35
1708 23:10:45.099077
1709 23:10:45.099696 Set Vref, RX VrefLevel [Byte0]: 36
1710 23:10:45.101909 [Byte1]: 36
1711 23:10:45.107187
1712 23:10:45.107766 Set Vref, RX VrefLevel [Byte0]: 37
1713 23:10:45.109993 [Byte1]: 37
1714 23:10:45.113879
1715 23:10:45.114292 Set Vref, RX VrefLevel [Byte0]: 38
1716 23:10:45.117466 [Byte1]: 38
1717 23:10:45.122231
1718 23:10:45.122738 Set Vref, RX VrefLevel [Byte0]: 39
1719 23:10:45.125647 [Byte1]: 39
1720 23:10:45.129251
1721 23:10:45.129804 Set Vref, RX VrefLevel [Byte0]: 40
1722 23:10:45.132420 [Byte1]: 40
1723 23:10:45.136798
1724 23:10:45.137207 Set Vref, RX VrefLevel [Byte0]: 41
1725 23:10:45.140139 [Byte1]: 41
1726 23:10:45.145019
1727 23:10:45.145518 Set Vref, RX VrefLevel [Byte0]: 42
1728 23:10:45.148037 [Byte1]: 42
1729 23:10:45.151925
1730 23:10:45.152334 Set Vref, RX VrefLevel [Byte0]: 43
1731 23:10:45.155311 [Byte1]: 43
1732 23:10:45.159393
1733 23:10:45.159813 Set Vref, RX VrefLevel [Byte0]: 44
1734 23:10:45.162911 [Byte1]: 44
1735 23:10:45.167127
1736 23:10:45.167660 Set Vref, RX VrefLevel [Byte0]: 45
1737 23:10:45.170832 [Byte1]: 45
1738 23:10:45.174536
1739 23:10:45.174945 Set Vref, RX VrefLevel [Byte0]: 46
1740 23:10:45.178705 [Byte1]: 46
1741 23:10:45.182848
1742 23:10:45.183407 Set Vref, RX VrefLevel [Byte0]: 47
1743 23:10:45.186100 [Byte1]: 47
1744 23:10:45.190690
1745 23:10:45.191190 Set Vref, RX VrefLevel [Byte0]: 48
1746 23:10:45.193633 [Byte1]: 48
1747 23:10:45.197383
1748 23:10:45.197893 Set Vref, RX VrefLevel [Byte0]: 49
1749 23:10:45.200679 [Byte1]: 49
1750 23:10:45.205264
1751 23:10:45.205781 Set Vref, RX VrefLevel [Byte0]: 50
1752 23:10:45.208708 [Byte1]: 50
1753 23:10:45.212901
1754 23:10:45.213414 Set Vref, RX VrefLevel [Byte0]: 51
1755 23:10:45.216261 [Byte1]: 51
1756 23:10:45.220474
1757 23:10:45.220987 Set Vref, RX VrefLevel [Byte0]: 52
1758 23:10:45.223653 [Byte1]: 52
1759 23:10:45.228066
1760 23:10:45.228601 Set Vref, RX VrefLevel [Byte0]: 53
1761 23:10:45.231440 [Byte1]: 53
1762 23:10:45.235733
1763 23:10:45.236251 Set Vref, RX VrefLevel [Byte0]: 54
1764 23:10:45.238534 [Byte1]: 54
1765 23:10:45.244048
1766 23:10:45.244562 Set Vref, RX VrefLevel [Byte0]: 55
1767 23:10:45.246442 [Byte1]: 55
1768 23:10:45.251079
1769 23:10:45.251542 Set Vref, RX VrefLevel [Byte0]: 56
1770 23:10:45.254339 [Byte1]: 56
1771 23:10:45.258268
1772 23:10:45.258683 Set Vref, RX VrefLevel [Byte0]: 57
1773 23:10:45.261346 [Byte1]: 57
1774 23:10:45.266470
1775 23:10:45.267019 Set Vref, RX VrefLevel [Byte0]: 58
1776 23:10:45.269095 [Byte1]: 58
1777 23:10:45.273352
1778 23:10:45.273770 Set Vref, RX VrefLevel [Byte0]: 59
1779 23:10:45.276743 [Byte1]: 59
1780 23:10:45.280917
1781 23:10:45.281332 Set Vref, RX VrefLevel [Byte0]: 60
1782 23:10:45.284262 [Byte1]: 60
1783 23:10:45.289297
1784 23:10:45.289714 Set Vref, RX VrefLevel [Byte0]: 61
1785 23:10:45.292252 [Byte1]: 61
1786 23:10:45.296270
1787 23:10:45.296567 Set Vref, RX VrefLevel [Byte0]: 62
1788 23:10:45.299740 [Byte1]: 62
1789 23:10:45.303657
1790 23:10:45.303998 Set Vref, RX VrefLevel [Byte0]: 63
1791 23:10:45.306661 [Byte1]: 63
1792 23:10:45.310987
1793 23:10:45.311218 Set Vref, RX VrefLevel [Byte0]: 64
1794 23:10:45.314325 [Byte1]: 64
1795 23:10:45.319348
1796 23:10:45.319562 Set Vref, RX VrefLevel [Byte0]: 65
1797 23:10:45.322383 [Byte1]: 65
1798 23:10:45.326055
1799 23:10:45.326209 Set Vref, RX VrefLevel [Byte0]: 66
1800 23:10:45.329656 [Byte1]: 66
1801 23:10:45.333980
1802 23:10:45.334122 Set Vref, RX VrefLevel [Byte0]: 67
1803 23:10:45.336993 [Byte1]: 67
1804 23:10:45.341288
1805 23:10:45.341413 Set Vref, RX VrefLevel [Byte0]: 68
1806 23:10:45.344455 [Byte1]: 68
1807 23:10:45.349189
1808 23:10:45.349278 Set Vref, RX VrefLevel [Byte0]: 69
1809 23:10:45.352403 [Byte1]: 69
1810 23:10:45.356554
1811 23:10:45.356637 Set Vref, RX VrefLevel [Byte0]: 70
1812 23:10:45.359773 [Byte1]: 70
1813 23:10:45.363939
1814 23:10:45.364021 Set Vref, RX VrefLevel [Byte0]: 71
1815 23:10:45.367261 [Byte1]: 71
1816 23:10:45.371713
1817 23:10:45.371796 Set Vref, RX VrefLevel [Byte0]: 72
1818 23:10:45.375209 [Byte1]: 72
1819 23:10:45.379711
1820 23:10:45.379793 Final RX Vref Byte 0 = 60 to rank0
1821 23:10:45.382586 Final RX Vref Byte 1 = 58 to rank0
1822 23:10:45.386019 Final RX Vref Byte 0 = 60 to rank1
1823 23:10:45.389576 Final RX Vref Byte 1 = 58 to rank1==
1824 23:10:45.392901 Dram Type= 6, Freq= 0, CH_1, rank 0
1825 23:10:45.399556 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1826 23:10:45.399640 ==
1827 23:10:45.399706 DQS Delay:
1828 23:10:45.399766 DQS0 = 0, DQS1 = 0
1829 23:10:45.403337 DQM Delay:
1830 23:10:45.403462 DQM0 = 87, DQM1 = 81
1831 23:10:45.405741 DQ Delay:
1832 23:10:45.409585 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
1833 23:10:45.412543 DQ4 =84, DQ5 =96, DQ6 =100, DQ7 =84
1834 23:10:45.415845 DQ8 =72, DQ9 =72, DQ10 =80, DQ11 =72
1835 23:10:45.419588 DQ12 =88, DQ13 =92, DQ14 =88, DQ15 =88
1836 23:10:45.419670
1837 23:10:45.419734
1838 23:10:45.425683 [DQSOSCAuto] RK0, (LSB)MR18= 0x1427, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 404 ps
1839 23:10:45.428953 CH1 RK0: MR19=606, MR18=1427
1840 23:10:45.435489 CH1_RK0: MR19=0x606, MR18=0x1427, DQSOSC=400, MR23=63, INC=92, DEC=61
1841 23:10:45.435572
1842 23:10:45.439176 ----->DramcWriteLeveling(PI) begin...
1843 23:10:45.439260 ==
1844 23:10:45.442439 Dram Type= 6, Freq= 0, CH_1, rank 1
1845 23:10:45.445423 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1846 23:10:45.445504 ==
1847 23:10:45.448972 Write leveling (Byte 0): 26 => 26
1848 23:10:45.452164 Write leveling (Byte 1): 26 => 26
1849 23:10:45.455772 DramcWriteLeveling(PI) end<-----
1850 23:10:45.455904
1851 23:10:45.456025 ==
1852 23:10:45.458712 Dram Type= 6, Freq= 0, CH_1, rank 1
1853 23:10:45.462422 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1854 23:10:45.462549 ==
1855 23:10:45.466311 [Gating] SW mode calibration
1856 23:10:45.472738 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1857 23:10:45.479128 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1858 23:10:45.481940 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1859 23:10:45.488622 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1860 23:10:45.492096 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1861 23:10:45.495243 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1862 23:10:45.501846 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1863 23:10:45.505380 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1864 23:10:45.508835 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1865 23:10:45.512931 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1866 23:10:45.519462 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1867 23:10:45.522243 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1868 23:10:45.525954 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1869 23:10:45.532208 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1870 23:10:45.535491 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1871 23:10:45.538573 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1872 23:10:45.545629 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1873 23:10:45.548985 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 23:10:45.552205 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1875 23:10:45.558591 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1876 23:10:45.562232 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 23:10:45.565376 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 23:10:45.571937 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 23:10:45.575090 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 23:10:45.578536 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 23:10:45.585297 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 23:10:45.588713 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 23:10:45.591714 0 9 4 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (1 1)
1884 23:10:45.598376 0 9 8 | B1->B0 | 2b2b 3434 | 0 1 | (0 0) (1 1)
1885 23:10:45.601485 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1886 23:10:45.605060 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1887 23:10:45.611474 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1888 23:10:45.615104 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1889 23:10:45.618247 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1890 23:10:45.624887 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1891 23:10:45.628007 0 10 4 | B1->B0 | 3333 2525 | 1 0 | (1 1) (0 0)
1892 23:10:45.631587 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 23:10:45.638384 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1894 23:10:45.641397 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 23:10:45.644709 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 23:10:45.651421 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1897 23:10:45.654863 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1898 23:10:45.657708 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1899 23:10:45.661878 0 11 4 | B1->B0 | 2323 3d3d | 0 0 | (0 0) (0 0)
1900 23:10:45.668465 0 11 8 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
1901 23:10:45.671699 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1902 23:10:45.674516 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1903 23:10:45.681369 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1904 23:10:45.684546 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1905 23:10:45.688225 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1906 23:10:45.694724 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1907 23:10:45.697902 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1908 23:10:45.702376 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1909 23:10:45.707993 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1910 23:10:45.711272 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1911 23:10:45.714456 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1912 23:10:45.720933 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1913 23:10:45.724763 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1914 23:10:45.727865 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1915 23:10:45.734211 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1916 23:10:45.737396 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1917 23:10:45.740765 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1918 23:10:45.747763 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1919 23:10:45.750519 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1920 23:10:45.753976 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1921 23:10:45.760575 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1922 23:10:45.763964 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1923 23:10:45.767250 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1924 23:10:45.773930 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1925 23:10:45.774013 Total UI for P1: 0, mck2ui 16
1926 23:10:45.781248 best dqsien dly found for B0: ( 0, 14, 4)
1927 23:10:45.781330 Total UI for P1: 0, mck2ui 16
1928 23:10:45.787314 best dqsien dly found for B1: ( 0, 14, 6)
1929 23:10:45.790857 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1930 23:10:45.793876 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1931 23:10:45.793957
1932 23:10:45.797236 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1933 23:10:45.800865 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1934 23:10:45.804072 [Gating] SW calibration Done
1935 23:10:45.804154 ==
1936 23:10:45.807017 Dram Type= 6, Freq= 0, CH_1, rank 1
1937 23:10:45.810644 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1938 23:10:45.810727 ==
1939 23:10:45.814196 RX Vref Scan: 0
1940 23:10:45.814277
1941 23:10:45.814341 RX Vref 0 -> 0, step: 1
1942 23:10:45.814401
1943 23:10:45.816866 RX Delay -130 -> 252, step: 16
1944 23:10:45.820464 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1945 23:10:45.827255 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1946 23:10:45.830047 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1947 23:10:45.833343 iDelay=206, Bit 3, Center 77 (-34 ~ 189) 224
1948 23:10:45.836934 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1949 23:10:45.840233 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1950 23:10:45.846562 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1951 23:10:45.850206 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
1952 23:10:45.853511 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1953 23:10:45.856694 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1954 23:10:45.859812 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1955 23:10:45.866579 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1956 23:10:45.869925 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1957 23:10:45.873472 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1958 23:10:45.877077 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1959 23:10:45.883294 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1960 23:10:45.883443 ==
1961 23:10:45.886552 Dram Type= 6, Freq= 0, CH_1, rank 1
1962 23:10:45.889601 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1963 23:10:45.889687 ==
1964 23:10:45.889782 DQS Delay:
1965 23:10:45.893556 DQS0 = 0, DQS1 = 0
1966 23:10:45.893637 DQM Delay:
1967 23:10:45.896548 DQM0 = 84, DQM1 = 80
1968 23:10:45.896629 DQ Delay:
1969 23:10:45.899764 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =77
1970 23:10:45.902847 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =85
1971 23:10:45.906623 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1972 23:10:45.909632 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1973 23:10:45.909741
1974 23:10:45.909807
1975 23:10:45.909867 ==
1976 23:10:45.913528 Dram Type= 6, Freq= 0, CH_1, rank 1
1977 23:10:45.916384 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1978 23:10:45.916466 ==
1979 23:10:45.916532
1980 23:10:45.916591
1981 23:10:45.920551 TX Vref Scan disable
1982 23:10:45.923324 == TX Byte 0 ==
1983 23:10:45.926400 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1984 23:10:45.929743 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1985 23:10:45.933133 == TX Byte 1 ==
1986 23:10:45.936271 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1987 23:10:45.939881 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1988 23:10:45.939963 ==
1989 23:10:45.943035 Dram Type= 6, Freq= 0, CH_1, rank 1
1990 23:10:45.949547 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1991 23:10:45.949630 ==
1992 23:10:45.960939 TX Vref=22, minBit 1, minWin=26, winSum=447
1993 23:10:45.964293 TX Vref=24, minBit 6, minWin=26, winSum=446
1994 23:10:45.967649 TX Vref=26, minBit 2, minWin=27, winSum=453
1995 23:10:45.971554 TX Vref=28, minBit 2, minWin=27, winSum=455
1996 23:10:45.974221 TX Vref=30, minBit 2, minWin=27, winSum=454
1997 23:10:45.981543 TX Vref=32, minBit 2, minWin=27, winSum=455
1998 23:10:45.984396 [TxChooseVref] Worse bit 2, Min win 27, Win sum 455, Final Vref 28
1999 23:10:45.984480
2000 23:10:45.987509 Final TX Range 1 Vref 28
2001 23:10:45.987592
2002 23:10:45.987656 ==
2003 23:10:45.991216 Dram Type= 6, Freq= 0, CH_1, rank 1
2004 23:10:45.994433 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2005 23:10:45.994516 ==
2006 23:10:45.997490
2007 23:10:45.997571
2008 23:10:45.997635 TX Vref Scan disable
2009 23:10:46.000791 == TX Byte 0 ==
2010 23:10:46.004143 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
2011 23:10:46.010962 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
2012 23:10:46.011046 == TX Byte 1 ==
2013 23:10:46.014264 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
2014 23:10:46.020888 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
2015 23:10:46.020975
2016 23:10:46.021040 [DATLAT]
2017 23:10:46.021101 Freq=800, CH1 RK1
2018 23:10:46.021161
2019 23:10:46.024085 DATLAT Default: 0xa
2020 23:10:46.024167 0, 0xFFFF, sum = 0
2021 23:10:46.027319 1, 0xFFFF, sum = 0
2022 23:10:46.027420 2, 0xFFFF, sum = 0
2023 23:10:46.030680 3, 0xFFFF, sum = 0
2024 23:10:46.034048 4, 0xFFFF, sum = 0
2025 23:10:46.034131 5, 0xFFFF, sum = 0
2026 23:10:46.037665 6, 0xFFFF, sum = 0
2027 23:10:46.037748 7, 0xFFFF, sum = 0
2028 23:10:46.040616 8, 0xFFFF, sum = 0
2029 23:10:46.040699 9, 0x0, sum = 1
2030 23:10:46.043966 10, 0x0, sum = 2
2031 23:10:46.044048 11, 0x0, sum = 3
2032 23:10:46.044113 12, 0x0, sum = 4
2033 23:10:46.047349 best_step = 10
2034 23:10:46.047472
2035 23:10:46.047536 ==
2036 23:10:46.051040 Dram Type= 6, Freq= 0, CH_1, rank 1
2037 23:10:46.053923 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2038 23:10:46.054005 ==
2039 23:10:46.057508 RX Vref Scan: 0
2040 23:10:46.057589
2041 23:10:46.057653 RX Vref 0 -> 0, step: 1
2042 23:10:46.060535
2043 23:10:46.060615 RX Delay -95 -> 252, step: 8
2044 23:10:46.067341 iDelay=209, Bit 0, Center 92 (-23 ~ 208) 232
2045 23:10:46.070997 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
2046 23:10:46.074633 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
2047 23:10:46.077545 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
2048 23:10:46.080864 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
2049 23:10:46.088297 iDelay=209, Bit 5, Center 96 (-15 ~ 208) 224
2050 23:10:46.090794 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
2051 23:10:46.094454 iDelay=209, Bit 7, Center 84 (-31 ~ 200) 232
2052 23:10:46.097793 iDelay=209, Bit 8, Center 76 (-31 ~ 184) 216
2053 23:10:46.101287 iDelay=209, Bit 9, Center 76 (-31 ~ 184) 216
2054 23:10:46.107332 iDelay=209, Bit 10, Center 88 (-23 ~ 200) 224
2055 23:10:46.111277 iDelay=209, Bit 11, Center 80 (-31 ~ 192) 224
2056 23:10:46.114471 iDelay=209, Bit 12, Center 88 (-23 ~ 200) 224
2057 23:10:46.117174 iDelay=209, Bit 13, Center 92 (-15 ~ 200) 216
2058 23:10:46.124664 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2059 23:10:46.127738 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
2060 23:10:46.127935 ==
2061 23:10:46.130475 Dram Type= 6, Freq= 0, CH_1, rank 1
2062 23:10:46.134072 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2063 23:10:46.134248 ==
2064 23:10:46.137059 DQS Delay:
2065 23:10:46.137287 DQS0 = 0, DQS1 = 0
2066 23:10:46.137414 DQM Delay:
2067 23:10:46.141224 DQM0 = 86, DQM1 = 84
2068 23:10:46.141478 DQ Delay:
2069 23:10:46.143915 DQ0 =92, DQ1 =84, DQ2 =76, DQ3 =80
2070 23:10:46.147409 DQ4 =84, DQ5 =96, DQ6 =96, DQ7 =84
2071 23:10:46.150496 DQ8 =76, DQ9 =76, DQ10 =88, DQ11 =80
2072 23:10:46.153679 DQ12 =88, DQ13 =92, DQ14 =88, DQ15 =88
2073 23:10:46.153990
2074 23:10:46.154191
2075 23:10:46.164078 [DQSOSCAuto] RK1, (LSB)MR18= 0x203b, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 401 ps
2076 23:10:46.164474 CH1 RK1: MR19=606, MR18=203B
2077 23:10:46.170629 CH1_RK1: MR19=0x606, MR18=0x203B, DQSOSC=394, MR23=63, INC=95, DEC=63
2078 23:10:46.174619 [RxdqsGatingPostProcess] freq 800
2079 23:10:46.181480 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2080 23:10:46.184369 Pre-setting of DQS Precalculation
2081 23:10:46.187265 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2082 23:10:46.193788 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2083 23:10:46.203855 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2084 23:10:46.204350
2085 23:10:46.204676
2086 23:10:46.207586 [Calibration Summary] 1600 Mbps
2087 23:10:46.207998 CH 0, Rank 0
2088 23:10:46.211114 SW Impedance : PASS
2089 23:10:46.211669 DUTY Scan : NO K
2090 23:10:46.213857 ZQ Calibration : PASS
2091 23:10:46.217059 Jitter Meter : NO K
2092 23:10:46.217569 CBT Training : PASS
2093 23:10:46.220671 Write leveling : PASS
2094 23:10:46.223796 RX DQS gating : PASS
2095 23:10:46.224301 RX DQ/DQS(RDDQC) : PASS
2096 23:10:46.228015 TX DQ/DQS : PASS
2097 23:10:46.228523 RX DATLAT : PASS
2098 23:10:46.230075 RX DQ/DQS(Engine): PASS
2099 23:10:46.233630 TX OE : NO K
2100 23:10:46.234136 All Pass.
2101 23:10:46.234466
2102 23:10:46.237081 CH 0, Rank 1
2103 23:10:46.237586 SW Impedance : PASS
2104 23:10:46.240519 DUTY Scan : NO K
2105 23:10:46.241026 ZQ Calibration : PASS
2106 23:10:46.243812 Jitter Meter : NO K
2107 23:10:46.247081 CBT Training : PASS
2108 23:10:46.247649 Write leveling : PASS
2109 23:10:46.250607 RX DQS gating : PASS
2110 23:10:46.253643 RX DQ/DQS(RDDQC) : PASS
2111 23:10:46.254065 TX DQ/DQS : PASS
2112 23:10:46.256451 RX DATLAT : PASS
2113 23:10:46.259705 RX DQ/DQS(Engine): PASS
2114 23:10:46.260144 TX OE : NO K
2115 23:10:46.263679 All Pass.
2116 23:10:46.264096
2117 23:10:46.264423 CH 1, Rank 0
2118 23:10:46.266982 SW Impedance : PASS
2119 23:10:46.267537 DUTY Scan : NO K
2120 23:10:46.269937 ZQ Calibration : PASS
2121 23:10:46.273266 Jitter Meter : NO K
2122 23:10:46.273774 CBT Training : PASS
2123 23:10:46.276154 Write leveling : PASS
2124 23:10:46.280779 RX DQS gating : PASS
2125 23:10:46.281284 RX DQ/DQS(RDDQC) : PASS
2126 23:10:46.283086 TX DQ/DQS : PASS
2127 23:10:46.286567 RX DATLAT : PASS
2128 23:10:46.286986 RX DQ/DQS(Engine): PASS
2129 23:10:46.289467 TX OE : NO K
2130 23:10:46.289885 All Pass.
2131 23:10:46.290314
2132 23:10:46.293103 CH 1, Rank 1
2133 23:10:46.293524 SW Impedance : PASS
2134 23:10:46.296562 DUTY Scan : NO K
2135 23:10:46.296984 ZQ Calibration : PASS
2136 23:10:46.299473 Jitter Meter : NO K
2137 23:10:46.302924 CBT Training : PASS
2138 23:10:46.303339 Write leveling : PASS
2139 23:10:46.305947 RX DQS gating : PASS
2140 23:10:46.309816 RX DQ/DQS(RDDQC) : PASS
2141 23:10:46.310239 TX DQ/DQS : PASS
2142 23:10:46.312682 RX DATLAT : PASS
2143 23:10:46.316057 RX DQ/DQS(Engine): PASS
2144 23:10:46.316486 TX OE : NO K
2145 23:10:46.320296 All Pass.
2146 23:10:46.320722
2147 23:10:46.321052 DramC Write-DBI off
2148 23:10:46.322904 PER_BANK_REFRESH: Hybrid Mode
2149 23:10:46.323323 TX_TRACKING: ON
2150 23:10:46.325913 [GetDramInforAfterCalByMRR] Vendor 6.
2151 23:10:46.332536 [GetDramInforAfterCalByMRR] Revision 606.
2152 23:10:46.336513 [GetDramInforAfterCalByMRR] Revision 2 0.
2153 23:10:46.336773 MR0 0x3b3b
2154 23:10:46.336921 MR8 0x5151
2155 23:10:46.339128 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2156 23:10:46.339310
2157 23:10:46.343061 MR0 0x3b3b
2158 23:10:46.343220 MR8 0x5151
2159 23:10:46.346139 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2160 23:10:46.346297
2161 23:10:46.356317 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2162 23:10:46.359595 [FAST_K] Save calibration result to emmc
2163 23:10:46.362700 [FAST_K] Save calibration result to emmc
2164 23:10:46.366120 dram_init: config_dvfs: 1
2165 23:10:46.369215 dramc_set_vcore_voltage set vcore to 662500
2166 23:10:46.372795 Read voltage for 1200, 2
2167 23:10:46.372948 Vio18 = 0
2168 23:10:46.373023 Vcore = 662500
2169 23:10:46.376038 Vdram = 0
2170 23:10:46.376190 Vddq = 0
2171 23:10:46.376264 Vmddr = 0
2172 23:10:46.382364 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2173 23:10:46.385898 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2174 23:10:46.389833 MEM_TYPE=3, freq_sel=15
2175 23:10:46.392887 sv_algorithm_assistance_LP4_1600
2176 23:10:46.395650 ============ PULL DRAM RESETB DOWN ============
2177 23:10:46.398982 ========== PULL DRAM RESETB DOWN end =========
2178 23:10:46.406121 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2179 23:10:46.409025 ===================================
2180 23:10:46.412030 LPDDR4 DRAM CONFIGURATION
2181 23:10:46.415304 ===================================
2182 23:10:46.415452 EX_ROW_EN[0] = 0x0
2183 23:10:46.418740 EX_ROW_EN[1] = 0x0
2184 23:10:46.418935 LP4Y_EN = 0x0
2185 23:10:46.422351 WORK_FSP = 0x0
2186 23:10:46.422546 WL = 0x4
2187 23:10:46.425627 RL = 0x4
2188 23:10:46.425839 BL = 0x2
2189 23:10:46.429219 RPST = 0x0
2190 23:10:46.429448 RD_PRE = 0x0
2191 23:10:46.433128 WR_PRE = 0x1
2192 23:10:46.433384 WR_PST = 0x0
2193 23:10:46.435852 DBI_WR = 0x0
2194 23:10:46.436102 DBI_RD = 0x0
2195 23:10:46.439409 OTF = 0x1
2196 23:10:46.442647 ===================================
2197 23:10:46.445548 ===================================
2198 23:10:46.445887 ANA top config
2199 23:10:46.449191 ===================================
2200 23:10:46.451969 DLL_ASYNC_EN = 0
2201 23:10:46.455639 ALL_SLAVE_EN = 0
2202 23:10:46.459518 NEW_RANK_MODE = 1
2203 23:10:46.460044 DLL_IDLE_MODE = 1
2204 23:10:46.462200 LP45_APHY_COMB_EN = 1
2205 23:10:46.466208 TX_ODT_DIS = 1
2206 23:10:46.469292 NEW_8X_MODE = 1
2207 23:10:46.472890 ===================================
2208 23:10:46.475932 ===================================
2209 23:10:46.478995 data_rate = 2400
2210 23:10:46.479553 CKR = 1
2211 23:10:46.482688 DQ_P2S_RATIO = 8
2212 23:10:46.485516 ===================================
2213 23:10:46.488922 CA_P2S_RATIO = 8
2214 23:10:46.492304 DQ_CA_OPEN = 0
2215 23:10:46.495450 DQ_SEMI_OPEN = 0
2216 23:10:46.499051 CA_SEMI_OPEN = 0
2217 23:10:46.499596 CA_FULL_RATE = 0
2218 23:10:46.502173 DQ_CKDIV4_EN = 0
2219 23:10:46.505812 CA_CKDIV4_EN = 0
2220 23:10:46.508666 CA_PREDIV_EN = 0
2221 23:10:46.512303 PH8_DLY = 17
2222 23:10:46.515971 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2223 23:10:46.516477 DQ_AAMCK_DIV = 4
2224 23:10:46.518859 CA_AAMCK_DIV = 4
2225 23:10:46.522417 CA_ADMCK_DIV = 4
2226 23:10:46.525536 DQ_TRACK_CA_EN = 0
2227 23:10:46.528464 CA_PICK = 1200
2228 23:10:46.531699 CA_MCKIO = 1200
2229 23:10:46.535798 MCKIO_SEMI = 0
2230 23:10:46.539028 PLL_FREQ = 2366
2231 23:10:46.539580 DQ_UI_PI_RATIO = 32
2232 23:10:46.542002 CA_UI_PI_RATIO = 0
2233 23:10:46.545647 ===================================
2234 23:10:46.548627 ===================================
2235 23:10:46.552764 memory_type:LPDDR4
2236 23:10:46.555597 GP_NUM : 10
2237 23:10:46.556015 SRAM_EN : 1
2238 23:10:46.559174 MD32_EN : 0
2239 23:10:46.562716 ===================================
2240 23:10:46.563140 [ANA_INIT] >>>>>>>>>>>>>>
2241 23:10:46.565024 <<<<<< [CONFIGURE PHASE]: ANA_TX
2242 23:10:46.568390 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2243 23:10:46.571760 ===================================
2244 23:10:46.574770 data_rate = 2400,PCW = 0X5b00
2245 23:10:46.578251 ===================================
2246 23:10:46.582650 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2247 23:10:46.588696 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2248 23:10:46.594986 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2249 23:10:46.598882 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2250 23:10:46.601957 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2251 23:10:46.605005 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2252 23:10:46.608711 [ANA_INIT] flow start
2253 23:10:46.609235 [ANA_INIT] PLL >>>>>>>>
2254 23:10:46.611399 [ANA_INIT] PLL <<<<<<<<
2255 23:10:46.614837 [ANA_INIT] MIDPI >>>>>>>>
2256 23:10:46.615247 [ANA_INIT] MIDPI <<<<<<<<
2257 23:10:46.618432 [ANA_INIT] DLL >>>>>>>>
2258 23:10:46.621786 [ANA_INIT] DLL <<<<<<<<
2259 23:10:46.622289 [ANA_INIT] flow end
2260 23:10:46.628143 ============ LP4 DIFF to SE enter ============
2261 23:10:46.631302 ============ LP4 DIFF to SE exit ============
2262 23:10:46.634790 [ANA_INIT] <<<<<<<<<<<<<
2263 23:10:46.637648 [Flow] Enable top DCM control >>>>>
2264 23:10:46.641179 [Flow] Enable top DCM control <<<<<
2265 23:10:46.641692 Enable DLL master slave shuffle
2266 23:10:46.647918 ==============================================================
2267 23:10:46.651473 Gating Mode config
2268 23:10:46.654398 ==============================================================
2269 23:10:46.657879 Config description:
2270 23:10:46.668322 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2271 23:10:46.674253 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2272 23:10:46.678067 SELPH_MODE 0: By rank 1: By Phase
2273 23:10:46.684381 ==============================================================
2274 23:10:46.687897 GAT_TRACK_EN = 1
2275 23:10:46.690878 RX_GATING_MODE = 2
2276 23:10:46.694191 RX_GATING_TRACK_MODE = 2
2277 23:10:46.697394 SELPH_MODE = 1
2278 23:10:46.701452 PICG_EARLY_EN = 1
2279 23:10:46.701961 VALID_LAT_VALUE = 1
2280 23:10:46.707598 ==============================================================
2281 23:10:46.710757 Enter into Gating configuration >>>>
2282 23:10:46.713836 Exit from Gating configuration <<<<
2283 23:10:46.717218 Enter into DVFS_PRE_config >>>>>
2284 23:10:46.729062 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2285 23:10:46.731055 Exit from DVFS_PRE_config <<<<<
2286 23:10:46.734882 Enter into PICG configuration >>>>
2287 23:10:46.737002 Exit from PICG configuration <<<<
2288 23:10:46.740680 [RX_INPUT] configuration >>>>>
2289 23:10:46.743962 [RX_INPUT] configuration <<<<<
2290 23:10:46.747384 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2291 23:10:46.753836 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2292 23:10:46.760299 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2293 23:10:46.766671 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2294 23:10:46.773434 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2295 23:10:46.780526 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2296 23:10:46.783525 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2297 23:10:46.787033 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2298 23:10:46.790136 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2299 23:10:46.794114 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2300 23:10:46.800733 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2301 23:10:46.803330 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2302 23:10:46.806699 ===================================
2303 23:10:46.809761 LPDDR4 DRAM CONFIGURATION
2304 23:10:46.813212 ===================================
2305 23:10:46.813675 EX_ROW_EN[0] = 0x0
2306 23:10:46.816883 EX_ROW_EN[1] = 0x0
2307 23:10:46.817330 LP4Y_EN = 0x0
2308 23:10:46.819992 WORK_FSP = 0x0
2309 23:10:46.820405 WL = 0x4
2310 23:10:46.823603 RL = 0x4
2311 23:10:46.826516 BL = 0x2
2312 23:10:46.826926 RPST = 0x0
2313 23:10:46.830451 RD_PRE = 0x0
2314 23:10:46.830960 WR_PRE = 0x1
2315 23:10:46.833780 WR_PST = 0x0
2316 23:10:46.834290 DBI_WR = 0x0
2317 23:10:46.836815 DBI_RD = 0x0
2318 23:10:46.837329 OTF = 0x1
2319 23:10:46.839913 ===================================
2320 23:10:46.843435 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2321 23:10:46.850124 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2322 23:10:46.853735 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2323 23:10:46.856382 ===================================
2324 23:10:46.860204 LPDDR4 DRAM CONFIGURATION
2325 23:10:46.863344 ===================================
2326 23:10:46.863812 EX_ROW_EN[0] = 0x10
2327 23:10:46.867051 EX_ROW_EN[1] = 0x0
2328 23:10:46.867617 LP4Y_EN = 0x0
2329 23:10:46.870186 WORK_FSP = 0x0
2330 23:10:46.870598 WL = 0x4
2331 23:10:46.874066 RL = 0x4
2332 23:10:46.874572 BL = 0x2
2333 23:10:46.876754 RPST = 0x0
2334 23:10:46.877127 RD_PRE = 0x0
2335 23:10:46.879758 WR_PRE = 0x1
2336 23:10:46.883224 WR_PST = 0x0
2337 23:10:46.883790 DBI_WR = 0x0
2338 23:10:46.886454 DBI_RD = 0x0
2339 23:10:46.886969 OTF = 0x1
2340 23:10:46.889818 ===================================
2341 23:10:46.896698 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2342 23:10:46.897207 ==
2343 23:10:46.899739 Dram Type= 6, Freq= 0, CH_0, rank 0
2344 23:10:46.902971 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2345 23:10:46.903437 ==
2346 23:10:46.906803 [Duty_Offset_Calibration]
2347 23:10:46.907352 B0:2 B1:0 CA:4
2348 23:10:46.909647
2349 23:10:46.912997 [DutyScan_Calibration_Flow] k_type=0
2350 23:10:46.920504
2351 23:10:46.921006 ==CLK 0==
2352 23:10:46.924226 Final CLK duty delay cell = -4
2353 23:10:46.926940 [-4] MAX Duty = 5031%(X100), DQS PI = 14
2354 23:10:46.929752 [-4] MIN Duty = 4844%(X100), DQS PI = 8
2355 23:10:46.932953 [-4] AVG Duty = 4937%(X100)
2356 23:10:46.933366
2357 23:10:46.936427 CH0 CLK Duty spec in!! Max-Min= 187%
2358 23:10:46.939854 [DutyScan_Calibration_Flow] ====Done====
2359 23:10:46.940269
2360 23:10:46.943026 [DutyScan_Calibration_Flow] k_type=1
2361 23:10:46.958799
2362 23:10:46.959213 ==DQS 0 ==
2363 23:10:46.962005 Final DQS duty delay cell = -4
2364 23:10:46.965592 [-4] MAX Duty = 4969%(X100), DQS PI = 16
2365 23:10:46.968857 [-4] MIN Duty = 4875%(X100), DQS PI = 2
2366 23:10:46.971696 [-4] AVG Duty = 4922%(X100)
2367 23:10:46.972107
2368 23:10:46.972430 ==DQS 1 ==
2369 23:10:46.975311 Final DQS duty delay cell = 0
2370 23:10:46.978716 [0] MAX Duty = 5125%(X100), DQS PI = 50
2371 23:10:46.982444 [0] MIN Duty = 4969%(X100), DQS PI = 62
2372 23:10:46.985125 [0] AVG Duty = 5047%(X100)
2373 23:10:46.985540
2374 23:10:46.988569 CH0 DQS 0 Duty spec in!! Max-Min= 94%
2375 23:10:46.988977
2376 23:10:46.991802 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2377 23:10:46.995200 [DutyScan_Calibration_Flow] ====Done====
2378 23:10:46.995657
2379 23:10:46.999547 [DutyScan_Calibration_Flow] k_type=3
2380 23:10:47.015476
2381 23:10:47.015972 ==DQM 0 ==
2382 23:10:47.018854 Final DQM duty delay cell = 0
2383 23:10:47.022239 [0] MAX Duty = 5093%(X100), DQS PI = 20
2384 23:10:47.025575 [0] MIN Duty = 4844%(X100), DQS PI = 52
2385 23:10:47.028864 [0] AVG Duty = 4968%(X100)
2386 23:10:47.029369
2387 23:10:47.029695 ==DQM 1 ==
2388 23:10:47.032376 Final DQM duty delay cell = 0
2389 23:10:47.035508 [0] MAX Duty = 5000%(X100), DQS PI = 4
2390 23:10:47.039168 [0] MIN Duty = 4875%(X100), DQS PI = 20
2391 23:10:47.042272 [0] AVG Duty = 4937%(X100)
2392 23:10:47.042774
2393 23:10:47.045390 CH0 DQM 0 Duty spec in!! Max-Min= 249%
2394 23:10:47.045894
2395 23:10:47.048560 CH0 DQM 1 Duty spec in!! Max-Min= 125%
2396 23:10:47.051858 [DutyScan_Calibration_Flow] ====Done====
2397 23:10:47.052274
2398 23:10:47.055723 [DutyScan_Calibration_Flow] k_type=2
2399 23:10:47.072328
2400 23:10:47.072833 ==DQ 0 ==
2401 23:10:47.075418 Final DQ duty delay cell = 0
2402 23:10:47.079637 [0] MAX Duty = 5125%(X100), DQS PI = 18
2403 23:10:47.082638 [0] MIN Duty = 4969%(X100), DQS PI = 52
2404 23:10:47.083144 [0] AVG Duty = 5047%(X100)
2405 23:10:47.085578
2406 23:10:47.085983 ==DQ 1 ==
2407 23:10:47.088911 Final DQ duty delay cell = 0
2408 23:10:47.092703 [0] MAX Duty = 5156%(X100), DQS PI = 6
2409 23:10:47.095625 [0] MIN Duty = 4938%(X100), DQS PI = 16
2410 23:10:47.096130 [0] AVG Duty = 5047%(X100)
2411 23:10:47.096460
2412 23:10:47.098563 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2413 23:10:47.101981
2414 23:10:47.105277 CH0 DQ 1 Duty spec in!! Max-Min= 218%
2415 23:10:47.108354 [DutyScan_Calibration_Flow] ====Done====
2416 23:10:47.108762 ==
2417 23:10:47.112061 Dram Type= 6, Freq= 0, CH_1, rank 0
2418 23:10:47.115012 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2419 23:10:47.115472 ==
2420 23:10:47.118189 [Duty_Offset_Calibration]
2421 23:10:47.118599 B0:0 B1:-1 CA:3
2422 23:10:47.118923
2423 23:10:47.121684 [DutyScan_Calibration_Flow] k_type=0
2424 23:10:47.131771
2425 23:10:47.132307 ==CLK 0==
2426 23:10:47.134738 Final CLK duty delay cell = -4
2427 23:10:47.138197 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2428 23:10:47.141434 [-4] MIN Duty = 4876%(X100), DQS PI = 36
2429 23:10:47.144326 [-4] AVG Duty = 4938%(X100)
2430 23:10:47.144740
2431 23:10:47.147899 CH1 CLK Duty spec in!! Max-Min= 124%
2432 23:10:47.151458 [DutyScan_Calibration_Flow] ====Done====
2433 23:10:47.151962
2434 23:10:47.154430 [DutyScan_Calibration_Flow] k_type=1
2435 23:10:47.170793
2436 23:10:47.171299 ==DQS 0 ==
2437 23:10:47.174927 Final DQS duty delay cell = 0
2438 23:10:47.177148 [0] MAX Duty = 5187%(X100), DQS PI = 18
2439 23:10:47.180567 [0] MIN Duty = 4907%(X100), DQS PI = 38
2440 23:10:47.183886 [0] AVG Duty = 5047%(X100)
2441 23:10:47.184298
2442 23:10:47.184626 ==DQS 1 ==
2443 23:10:47.187730 Final DQS duty delay cell = 0
2444 23:10:47.190744 [0] MAX Duty = 5156%(X100), DQS PI = 8
2445 23:10:47.194026 [0] MIN Duty = 5000%(X100), DQS PI = 26
2446 23:10:47.197616 [0] AVG Duty = 5078%(X100)
2447 23:10:47.198126
2448 23:10:47.200540 CH1 DQS 0 Duty spec in!! Max-Min= 280%
2449 23:10:47.200968
2450 23:10:47.204298 CH1 DQS 1 Duty spec in!! Max-Min= 156%
2451 23:10:47.207306 [DutyScan_Calibration_Flow] ====Done====
2452 23:10:47.207876
2453 23:10:47.211273 [DutyScan_Calibration_Flow] k_type=3
2454 23:10:47.227457
2455 23:10:47.227964 ==DQM 0 ==
2456 23:10:47.230964 Final DQM duty delay cell = 0
2457 23:10:47.234247 [0] MAX Duty = 5031%(X100), DQS PI = 28
2458 23:10:47.237517 [0] MIN Duty = 4782%(X100), DQS PI = 38
2459 23:10:47.240637 [0] AVG Duty = 4906%(X100)
2460 23:10:47.241141
2461 23:10:47.241466 ==DQM 1 ==
2462 23:10:47.244098 Final DQM duty delay cell = 0
2463 23:10:47.247268 [0] MAX Duty = 5000%(X100), DQS PI = 34
2464 23:10:47.250843 [0] MIN Duty = 4844%(X100), DQS PI = 0
2465 23:10:47.254090 [0] AVG Duty = 4922%(X100)
2466 23:10:47.254601
2467 23:10:47.257361 CH1 DQM 0 Duty spec in!! Max-Min= 249%
2468 23:10:47.257775
2469 23:10:47.260327 CH1 DQM 1 Duty spec in!! Max-Min= 156%
2470 23:10:47.264265 [DutyScan_Calibration_Flow] ====Done====
2471 23:10:47.264813
2472 23:10:47.267267 [DutyScan_Calibration_Flow] k_type=2
2473 23:10:47.282966
2474 23:10:47.283520 ==DQ 0 ==
2475 23:10:47.286525 Final DQ duty delay cell = -4
2476 23:10:47.289619 [-4] MAX Duty = 5031%(X100), DQS PI = 30
2477 23:10:47.293181 [-4] MIN Duty = 4876%(X100), DQS PI = 18
2478 23:10:47.296938 [-4] AVG Duty = 4953%(X100)
2479 23:10:47.297450
2480 23:10:47.297776 ==DQ 1 ==
2481 23:10:47.299463 Final DQ duty delay cell = 0
2482 23:10:47.303225 [0] MAX Duty = 5031%(X100), DQS PI = 32
2483 23:10:47.306888 [0] MIN Duty = 4844%(X100), DQS PI = 0
2484 23:10:47.309859 [0] AVG Duty = 4937%(X100)
2485 23:10:47.310268
2486 23:10:47.312915 CH1 DQ 0 Duty spec in!! Max-Min= 155%
2487 23:10:47.313417
2488 23:10:47.317286 CH1 DQ 1 Duty spec in!! Max-Min= 187%
2489 23:10:47.319563 [DutyScan_Calibration_Flow] ====Done====
2490 23:10:47.323216 nWR fixed to 30
2491 23:10:47.326305 [ModeRegInit_LP4] CH0 RK0
2492 23:10:47.326807 [ModeRegInit_LP4] CH0 RK1
2493 23:10:47.329761 [ModeRegInit_LP4] CH1 RK0
2494 23:10:47.333061 [ModeRegInit_LP4] CH1 RK1
2495 23:10:47.333571 match AC timing 7
2496 23:10:47.339594 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2497 23:10:47.342651 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2498 23:10:47.346195 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2499 23:10:47.352656 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2500 23:10:47.356120 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2501 23:10:47.356543 ==
2502 23:10:47.358950 Dram Type= 6, Freq= 0, CH_0, rank 0
2503 23:10:47.362323 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2504 23:10:47.362740 ==
2505 23:10:47.369195 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2506 23:10:47.376318 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2507 23:10:47.383984 [CA 0] Center 39 (9~70) winsize 62
2508 23:10:47.386512 [CA 1] Center 39 (9~69) winsize 61
2509 23:10:47.389977 [CA 2] Center 35 (5~66) winsize 62
2510 23:10:47.393196 [CA 3] Center 35 (5~66) winsize 62
2511 23:10:47.396329 [CA 4] Center 33 (3~64) winsize 62
2512 23:10:47.399968 [CA 5] Center 33 (3~64) winsize 62
2513 23:10:47.400479
2514 23:10:47.402811 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2515 23:10:47.403314
2516 23:10:47.406094 [CATrainingPosCal] consider 1 rank data
2517 23:10:47.409399 u2DelayCellTimex100 = 270/100 ps
2518 23:10:47.413409 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2519 23:10:47.419356 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2520 23:10:47.423056 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2521 23:10:47.426192 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2522 23:10:47.429259 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2523 23:10:47.432703 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2524 23:10:47.433118
2525 23:10:47.436049 CA PerBit enable=1, Macro0, CA PI delay=33
2526 23:10:47.436462
2527 23:10:47.439437 [CBTSetCACLKResult] CA Dly = 33
2528 23:10:47.443328 CS Dly: 7 (0~38)
2529 23:10:47.443788 ==
2530 23:10:47.445978 Dram Type= 6, Freq= 0, CH_0, rank 1
2531 23:10:47.449293 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2532 23:10:47.449809 ==
2533 23:10:47.455721 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2534 23:10:47.458931 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2535 23:10:47.469226 [CA 0] Center 39 (9~70) winsize 62
2536 23:10:47.472169 [CA 1] Center 39 (9~70) winsize 62
2537 23:10:47.475558 [CA 2] Center 35 (5~66) winsize 62
2538 23:10:47.478828 [CA 3] Center 35 (5~66) winsize 62
2539 23:10:47.482488 [CA 4] Center 34 (4~65) winsize 62
2540 23:10:47.485600 [CA 5] Center 33 (3~63) winsize 61
2541 23:10:47.486017
2542 23:10:47.488832 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2543 23:10:47.489339
2544 23:10:47.492535 [CATrainingPosCal] consider 2 rank data
2545 23:10:47.495911 u2DelayCellTimex100 = 270/100 ps
2546 23:10:47.499176 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2547 23:10:47.505372 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2548 23:10:47.508838 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2549 23:10:47.512268 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2550 23:10:47.515267 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
2551 23:10:47.519908 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2552 23:10:47.520423
2553 23:10:47.522269 CA PerBit enable=1, Macro0, CA PI delay=33
2554 23:10:47.522782
2555 23:10:47.526172 [CBTSetCACLKResult] CA Dly = 33
2556 23:10:47.526690 CS Dly: 8 (0~41)
2557 23:10:47.527019
2558 23:10:47.528831 ----->DramcWriteLeveling(PI) begin...
2559 23:10:47.532512 ==
2560 23:10:47.535807 Dram Type= 6, Freq= 0, CH_0, rank 0
2561 23:10:47.539407 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2562 23:10:47.539927 ==
2563 23:10:47.542206 Write leveling (Byte 0): 33 => 33
2564 23:10:47.545550 Write leveling (Byte 1): 27 => 27
2565 23:10:47.548904 DramcWriteLeveling(PI) end<-----
2566 23:10:47.549415
2567 23:10:47.549740 ==
2568 23:10:47.551580 Dram Type= 6, Freq= 0, CH_0, rank 0
2569 23:10:47.556209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2570 23:10:47.556715 ==
2571 23:10:47.558807 [Gating] SW mode calibration
2572 23:10:47.565572 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2573 23:10:47.571993 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2574 23:10:47.575258 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2575 23:10:47.578661 0 15 4 | B1->B0 | 2c2c 3434 | 1 1 | (0 0) (1 1)
2576 23:10:47.585244 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2577 23:10:47.588152 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2578 23:10:47.591717 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2579 23:10:47.598983 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2580 23:10:47.601943 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
2581 23:10:47.604781 0 15 28 | B1->B0 | 3434 2828 | 1 1 | (1 1) (1 0)
2582 23:10:47.611612 1 0 0 | B1->B0 | 3232 2323 | 0 0 | (0 0) (0 0)
2583 23:10:47.614752 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2584 23:10:47.618228 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2585 23:10:47.624638 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2586 23:10:47.628055 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2587 23:10:47.631697 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2588 23:10:47.638206 1 0 24 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
2589 23:10:47.642396 1 0 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
2590 23:10:47.644831 1 1 0 | B1->B0 | 2c2c 4646 | 1 0 | (0 0) (0 0)
2591 23:10:47.651045 1 1 4 | B1->B0 | 4343 4646 | 0 0 | (1 1) (0 0)
2592 23:10:47.655240 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2593 23:10:47.657579 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2594 23:10:47.664719 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2595 23:10:47.667344 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2596 23:10:47.671469 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2597 23:10:47.677824 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2598 23:10:47.680817 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2599 23:10:47.684605 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2600 23:10:47.690671 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2601 23:10:47.694357 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2602 23:10:47.697590 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2603 23:10:47.700653 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2604 23:10:47.707859 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2605 23:10:47.710229 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2606 23:10:47.717141 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2607 23:10:47.721285 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2608 23:10:47.724055 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2609 23:10:47.727636 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2610 23:10:47.733447 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2611 23:10:47.737463 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2612 23:10:47.740306 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2613 23:10:47.746888 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
2614 23:10:47.750344 Total UI for P1: 0, mck2ui 16
2615 23:10:47.753602 best dqsien dly found for B0: ( 1, 3, 24)
2616 23:10:47.756949 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
2617 23:10:47.760206 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2618 23:10:47.767023 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2619 23:10:47.770439 Total UI for P1: 0, mck2ui 16
2620 23:10:47.773439 best dqsien dly found for B1: ( 1, 4, 4)
2621 23:10:47.777105 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
2622 23:10:47.780367 best DQS1 dly(MCK, UI, PI) = (1, 4, 4)
2623 23:10:47.780879
2624 23:10:47.783712 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
2625 23:10:47.786901 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 4)
2626 23:10:47.790601 [Gating] SW calibration Done
2627 23:10:47.791136 ==
2628 23:10:47.793432 Dram Type= 6, Freq= 0, CH_0, rank 0
2629 23:10:47.796933 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2630 23:10:47.797352 ==
2631 23:10:47.800113 RX Vref Scan: 0
2632 23:10:47.800627
2633 23:10:47.800957 RX Vref 0 -> 0, step: 1
2634 23:10:47.801260
2635 23:10:47.803189 RX Delay -40 -> 252, step: 8
2636 23:10:47.810084 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2637 23:10:47.812841 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2638 23:10:47.817115 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2639 23:10:47.820179 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2640 23:10:47.823349 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
2641 23:10:47.826599 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2642 23:10:47.833332 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2643 23:10:47.836308 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2644 23:10:47.840378 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2645 23:10:47.843257 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2646 23:10:47.846120 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2647 23:10:47.853107 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2648 23:10:47.856275 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2649 23:10:47.859415 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2650 23:10:47.862568 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2651 23:10:47.869520 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2652 23:10:47.869957 ==
2653 23:10:47.873341 Dram Type= 6, Freq= 0, CH_0, rank 0
2654 23:10:47.876070 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2655 23:10:47.876489 ==
2656 23:10:47.876822 DQS Delay:
2657 23:10:47.879939 DQS0 = 0, DQS1 = 0
2658 23:10:47.880353 DQM Delay:
2659 23:10:47.882653 DQM0 = 117, DQM1 = 108
2660 23:10:47.883062 DQ Delay:
2661 23:10:47.886521 DQ0 =115, DQ1 =115, DQ2 =115, DQ3 =111
2662 23:10:47.889440 DQ4 =123, DQ5 =111, DQ6 =123, DQ7 =127
2663 23:10:47.892774 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2664 23:10:47.895672 DQ12 =119, DQ13 =115, DQ14 =119, DQ15 =115
2665 23:10:47.896086
2666 23:10:47.896412
2667 23:10:47.899426 ==
2668 23:10:47.899846 Dram Type= 6, Freq= 0, CH_0, rank 0
2669 23:10:47.906095 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2670 23:10:47.906679 ==
2671 23:10:47.907020
2672 23:10:47.907327
2673 23:10:47.909783 TX Vref Scan disable
2674 23:10:47.910199 == TX Byte 0 ==
2675 23:10:47.913385 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2676 23:10:47.919422 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2677 23:10:47.919966 == TX Byte 1 ==
2678 23:10:47.922475 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2679 23:10:47.929567 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2680 23:10:47.930086 ==
2681 23:10:47.932688 Dram Type= 6, Freq= 0, CH_0, rank 0
2682 23:10:47.935580 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2683 23:10:47.936005 ==
2684 23:10:47.948323 TX Vref=22, minBit 1, minWin=25, winSum=411
2685 23:10:47.951942 TX Vref=24, minBit 3, minWin=25, winSum=413
2686 23:10:47.954828 TX Vref=26, minBit 1, minWin=25, winSum=422
2687 23:10:47.958944 TX Vref=28, minBit 8, minWin=26, winSum=428
2688 23:10:47.961199 TX Vref=30, minBit 4, minWin=26, winSum=428
2689 23:10:47.965466 TX Vref=32, minBit 2, minWin=25, winSum=423
2690 23:10:47.971129 [TxChooseVref] Worse bit 8, Min win 26, Win sum 428, Final Vref 28
2691 23:10:47.971678
2692 23:10:47.974583 Final TX Range 1 Vref 28
2693 23:10:47.975000
2694 23:10:47.975325 ==
2695 23:10:47.978148 Dram Type= 6, Freq= 0, CH_0, rank 0
2696 23:10:47.981048 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2697 23:10:47.981464 ==
2698 23:10:47.984823
2699 23:10:47.985237
2700 23:10:47.985564 TX Vref Scan disable
2701 23:10:47.987621 == TX Byte 0 ==
2702 23:10:47.991449 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2703 23:10:47.998597 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2704 23:10:47.999128 == TX Byte 1 ==
2705 23:10:48.001720 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2706 23:10:48.007717 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2707 23:10:48.008132
2708 23:10:48.008457 [DATLAT]
2709 23:10:48.008763 Freq=1200, CH0 RK0
2710 23:10:48.009057
2711 23:10:48.010836 DATLAT Default: 0xd
2712 23:10:48.011286 0, 0xFFFF, sum = 0
2713 23:10:48.014636 1, 0xFFFF, sum = 0
2714 23:10:48.017589 2, 0xFFFF, sum = 0
2715 23:10:48.018010 3, 0xFFFF, sum = 0
2716 23:10:48.021305 4, 0xFFFF, sum = 0
2717 23:10:48.021832 5, 0xFFFF, sum = 0
2718 23:10:48.026268 6, 0xFFFF, sum = 0
2719 23:10:48.026788 7, 0xFFFF, sum = 0
2720 23:10:48.027653 8, 0xFFFF, sum = 0
2721 23:10:48.028072 9, 0xFFFF, sum = 0
2722 23:10:48.031276 10, 0xFFFF, sum = 0
2723 23:10:48.031841 11, 0xFFFF, sum = 0
2724 23:10:48.035022 12, 0x0, sum = 1
2725 23:10:48.035593 13, 0x0, sum = 2
2726 23:10:48.037356 14, 0x0, sum = 3
2727 23:10:48.037779 15, 0x0, sum = 4
2728 23:10:48.040972 best_step = 13
2729 23:10:48.041497
2730 23:10:48.041828 ==
2731 23:10:48.045215 Dram Type= 6, Freq= 0, CH_0, rank 0
2732 23:10:48.047657 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2733 23:10:48.048080 ==
2734 23:10:48.048412 RX Vref Scan: 1
2735 23:10:48.050957
2736 23:10:48.051517 Set Vref Range= 32 -> 127
2737 23:10:48.051859
2738 23:10:48.054704 RX Vref 32 -> 127, step: 1
2739 23:10:48.055407
2740 23:10:48.057598 RX Delay -21 -> 252, step: 4
2741 23:10:48.058077
2742 23:10:48.061010 Set Vref, RX VrefLevel [Byte0]: 32
2743 23:10:48.063983 [Byte1]: 32
2744 23:10:48.064400
2745 23:10:48.067354 Set Vref, RX VrefLevel [Byte0]: 33
2746 23:10:48.070308 [Byte1]: 33
2747 23:10:48.074277
2748 23:10:48.074692 Set Vref, RX VrefLevel [Byte0]: 34
2749 23:10:48.078096 [Byte1]: 34
2750 23:10:48.082552
2751 23:10:48.083069 Set Vref, RX VrefLevel [Byte0]: 35
2752 23:10:48.085652 [Byte1]: 35
2753 23:10:48.090265
2754 23:10:48.090785 Set Vref, RX VrefLevel [Byte0]: 36
2755 23:10:48.093857 [Byte1]: 36
2756 23:10:48.098262
2757 23:10:48.098788 Set Vref, RX VrefLevel [Byte0]: 37
2758 23:10:48.101779 [Byte1]: 37
2759 23:10:48.106166
2760 23:10:48.106707 Set Vref, RX VrefLevel [Byte0]: 38
2761 23:10:48.109426 [Byte1]: 38
2762 23:10:48.114255
2763 23:10:48.114761 Set Vref, RX VrefLevel [Byte0]: 39
2764 23:10:48.117582 [Byte1]: 39
2765 23:10:48.121914
2766 23:10:48.122426 Set Vref, RX VrefLevel [Byte0]: 40
2767 23:10:48.126971 [Byte1]: 40
2768 23:10:48.130278
2769 23:10:48.130787 Set Vref, RX VrefLevel [Byte0]: 41
2770 23:10:48.133203 [Byte1]: 41
2771 23:10:48.137710
2772 23:10:48.138231 Set Vref, RX VrefLevel [Byte0]: 42
2773 23:10:48.141241 [Byte1]: 42
2774 23:10:48.145994
2775 23:10:48.146509 Set Vref, RX VrefLevel [Byte0]: 43
2776 23:10:48.149616 [Byte1]: 43
2777 23:10:48.153952
2778 23:10:48.154469 Set Vref, RX VrefLevel [Byte0]: 44
2779 23:10:48.156769 [Byte1]: 44
2780 23:10:48.161452
2781 23:10:48.162167 Set Vref, RX VrefLevel [Byte0]: 45
2782 23:10:48.164688 [Byte1]: 45
2783 23:10:48.169734
2784 23:10:48.170251 Set Vref, RX VrefLevel [Byte0]: 46
2785 23:10:48.172586 [Byte1]: 46
2786 23:10:48.178010
2787 23:10:48.178532 Set Vref, RX VrefLevel [Byte0]: 47
2788 23:10:48.180513 [Byte1]: 47
2789 23:10:48.185538
2790 23:10:48.186052 Set Vref, RX VrefLevel [Byte0]: 48
2791 23:10:48.188682 [Byte1]: 48
2792 23:10:48.193652
2793 23:10:48.194168 Set Vref, RX VrefLevel [Byte0]: 49
2794 23:10:48.197063 [Byte1]: 49
2795 23:10:48.201027
2796 23:10:48.201533 Set Vref, RX VrefLevel [Byte0]: 50
2797 23:10:48.204481 [Byte1]: 50
2798 23:10:48.209171
2799 23:10:48.209693 Set Vref, RX VrefLevel [Byte0]: 51
2800 23:10:48.212536 [Byte1]: 51
2801 23:10:48.217546
2802 23:10:48.218066 Set Vref, RX VrefLevel [Byte0]: 52
2803 23:10:48.220354 [Byte1]: 52
2804 23:10:48.225141
2805 23:10:48.225552 Set Vref, RX VrefLevel [Byte0]: 53
2806 23:10:48.228310 [Byte1]: 53
2807 23:10:48.233227
2808 23:10:48.233743 Set Vref, RX VrefLevel [Byte0]: 54
2809 23:10:48.236303 [Byte1]: 54
2810 23:10:48.240906
2811 23:10:48.241427 Set Vref, RX VrefLevel [Byte0]: 55
2812 23:10:48.245036 [Byte1]: 55
2813 23:10:48.248875
2814 23:10:48.249287 Set Vref, RX VrefLevel [Byte0]: 56
2815 23:10:48.252312 [Byte1]: 56
2816 23:10:48.256643
2817 23:10:48.257156 Set Vref, RX VrefLevel [Byte0]: 57
2818 23:10:48.259880 [Byte1]: 57
2819 23:10:48.264630
2820 23:10:48.265150 Set Vref, RX VrefLevel [Byte0]: 58
2821 23:10:48.267747 [Byte1]: 58
2822 23:10:48.272223
2823 23:10:48.272636 Set Vref, RX VrefLevel [Byte0]: 59
2824 23:10:48.276038 [Byte1]: 59
2825 23:10:48.280806
2826 23:10:48.281319 Set Vref, RX VrefLevel [Byte0]: 60
2827 23:10:48.283498 [Byte1]: 60
2828 23:10:48.288528
2829 23:10:48.289043 Set Vref, RX VrefLevel [Byte0]: 61
2830 23:10:48.291467 [Byte1]: 61
2831 23:10:48.296427
2832 23:10:48.297080 Set Vref, RX VrefLevel [Byte0]: 62
2833 23:10:48.299986 [Byte1]: 62
2834 23:10:48.304185
2835 23:10:48.304614 Set Vref, RX VrefLevel [Byte0]: 63
2836 23:10:48.307312 [Byte1]: 63
2837 23:10:48.312089
2838 23:10:48.312597 Set Vref, RX VrefLevel [Byte0]: 64
2839 23:10:48.315541 [Byte1]: 64
2840 23:10:48.320709
2841 23:10:48.321224 Set Vref, RX VrefLevel [Byte0]: 65
2842 23:10:48.323478 [Byte1]: 65
2843 23:10:48.328045
2844 23:10:48.328455 Set Vref, RX VrefLevel [Byte0]: 66
2845 23:10:48.331256 [Byte1]: 66
2846 23:10:48.336067
2847 23:10:48.336641 Set Vref, RX VrefLevel [Byte0]: 67
2848 23:10:48.339987 [Byte1]: 67
2849 23:10:48.344321
2850 23:10:48.344835 Final RX Vref Byte 0 = 51 to rank0
2851 23:10:48.346964 Final RX Vref Byte 1 = 48 to rank0
2852 23:10:48.350666 Final RX Vref Byte 0 = 51 to rank1
2853 23:10:48.353918 Final RX Vref Byte 1 = 48 to rank1==
2854 23:10:48.357006 Dram Type= 6, Freq= 0, CH_0, rank 0
2855 23:10:48.363885 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2856 23:10:48.364394 ==
2857 23:10:48.364731 DQS Delay:
2858 23:10:48.365039 DQS0 = 0, DQS1 = 0
2859 23:10:48.366792 DQM Delay:
2860 23:10:48.367208 DQM0 = 117, DQM1 = 104
2861 23:10:48.370974 DQ Delay:
2862 23:10:48.374454 DQ0 =118, DQ1 =118, DQ2 =114, DQ3 =114
2863 23:10:48.378043 DQ4 =118, DQ5 =110, DQ6 =124, DQ7 =122
2864 23:10:48.380000 DQ8 =92, DQ9 =90, DQ10 =104, DQ11 =100
2865 23:10:48.383815 DQ12 =112, DQ13 =108, DQ14 =116, DQ15 =110
2866 23:10:48.384335
2867 23:10:48.384664
2868 23:10:48.394118 [DQSOSCAuto] RK0, (LSB)MR18= 0xfefa, (MSB)MR19= 0x303, tDQSOscB0 = 412 ps tDQSOscB1 = 410 ps
2869 23:10:48.394660 CH0 RK0: MR19=303, MR18=FEFA
2870 23:10:48.400171 CH0_RK0: MR19=0x303, MR18=0xFEFA, DQSOSC=410, MR23=63, INC=39, DEC=26
2871 23:10:48.400691
2872 23:10:48.404182 ----->DramcWriteLeveling(PI) begin...
2873 23:10:48.404710 ==
2874 23:10:48.406799 Dram Type= 6, Freq= 0, CH_0, rank 1
2875 23:10:48.419047 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2876 23:10:48.419502 ==
2877 23:10:48.419922 Write leveling (Byte 0): 33 => 33
2878 23:10:48.420247 Write leveling (Byte 1): 28 => 28
2879 23:10:48.420880 DramcWriteLeveling(PI) end<-----
2880 23:10:48.421216
2881 23:10:48.423037 ==
2882 23:10:48.423488 Dram Type= 6, Freq= 0, CH_0, rank 1
2883 23:10:48.429845 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2884 23:10:48.430264 ==
2885 23:10:48.433285 [Gating] SW mode calibration
2886 23:10:48.442003 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2887 23:10:48.442976 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2888 23:10:48.449969 0 15 0 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
2889 23:10:48.452695 0 15 4 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
2890 23:10:48.456331 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2891 23:10:48.462779 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2892 23:10:48.466350 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2893 23:10:48.469542 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2894 23:10:48.476100 0 15 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
2895 23:10:48.479558 0 15 28 | B1->B0 | 3434 2424 | 1 0 | (1 1) (0 0)
2896 23:10:48.482732 1 0 0 | B1->B0 | 2d2d 2323 | 0 0 | (1 0) (0 0)
2897 23:10:48.490290 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2898 23:10:48.492643 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2899 23:10:48.496342 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2900 23:10:48.502755 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2901 23:10:48.506164 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2902 23:10:48.510083 1 0 24 | B1->B0 | 2323 3333 | 0 1 | (0 0) (0 0)
2903 23:10:48.516358 1 0 28 | B1->B0 | 2c2c 4646 | 0 0 | (0 0) (0 0)
2904 23:10:48.519196 1 1 0 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
2905 23:10:48.522557 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2906 23:10:48.530114 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2907 23:10:48.532829 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2908 23:10:48.535993 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2909 23:10:48.542563 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2910 23:10:48.546343 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2911 23:10:48.549348 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2912 23:10:48.552993 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2913 23:10:48.559709 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2914 23:10:48.562416 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2915 23:10:48.569216 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2916 23:10:48.572334 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2917 23:10:48.575760 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2918 23:10:48.578779 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2919 23:10:48.585463 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2920 23:10:48.588639 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2921 23:10:48.592113 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2922 23:10:48.599067 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2923 23:10:48.602073 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2924 23:10:48.605567 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2925 23:10:48.611978 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2926 23:10:48.615280 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2927 23:10:48.618243 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2928 23:10:48.622185 Total UI for P1: 0, mck2ui 16
2929 23:10:48.625752 best dqsien dly found for B0: ( 1, 3, 24)
2930 23:10:48.632272 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2931 23:10:48.635028 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2932 23:10:48.638656 Total UI for P1: 0, mck2ui 16
2933 23:10:48.641774 best dqsien dly found for B1: ( 1, 3, 30)
2934 23:10:48.644923 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
2935 23:10:48.648431 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2936 23:10:48.648852
2937 23:10:48.651618 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
2938 23:10:48.659009 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2939 23:10:48.659577 [Gating] SW calibration Done
2940 23:10:48.659925 ==
2941 23:10:48.661982 Dram Type= 6, Freq= 0, CH_0, rank 1
2942 23:10:48.668366 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2943 23:10:48.668787 ==
2944 23:10:48.669121 RX Vref Scan: 0
2945 23:10:48.669429
2946 23:10:48.671414 RX Vref 0 -> 0, step: 1
2947 23:10:48.671833
2948 23:10:48.674710 RX Delay -40 -> 252, step: 8
2949 23:10:48.677935 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2950 23:10:48.681649 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2951 23:10:48.684203 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2952 23:10:48.691152 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2953 23:10:48.694727 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2954 23:10:48.697967 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2955 23:10:48.700906 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2956 23:10:48.704128 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
2957 23:10:48.710859 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2958 23:10:48.714437 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2959 23:10:48.717389 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2960 23:10:48.721419 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2961 23:10:48.724273 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2962 23:10:48.730981 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2963 23:10:48.733979 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2964 23:10:48.737679 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2965 23:10:48.738199 ==
2966 23:10:48.741170 Dram Type= 6, Freq= 0, CH_0, rank 1
2967 23:10:48.743968 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2968 23:10:48.744392 ==
2969 23:10:48.747716 DQS Delay:
2970 23:10:48.748230 DQS0 = 0, DQS1 = 0
2971 23:10:48.750872 DQM Delay:
2972 23:10:48.751471 DQM0 = 115, DQM1 = 106
2973 23:10:48.753875 DQ Delay:
2974 23:10:48.757391 DQ0 =111, DQ1 =119, DQ2 =111, DQ3 =115
2975 23:10:48.760472 DQ4 =119, DQ5 =103, DQ6 =127, DQ7 =119
2976 23:10:48.764002 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =99
2977 23:10:48.767274 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =115
2978 23:10:48.767741
2979 23:10:48.768076
2980 23:10:48.768386 ==
2981 23:10:48.770497 Dram Type= 6, Freq= 0, CH_0, rank 1
2982 23:10:48.774322 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2983 23:10:48.774847 ==
2984 23:10:48.775176
2985 23:10:48.775573
2986 23:10:48.777095 TX Vref Scan disable
2987 23:10:48.780836 == TX Byte 0 ==
2988 23:10:48.783767 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2989 23:10:48.787127 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2990 23:10:48.790496 == TX Byte 1 ==
2991 23:10:48.794904 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2992 23:10:48.796996 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2993 23:10:48.797417 ==
2994 23:10:48.801717 Dram Type= 6, Freq= 0, CH_0, rank 1
2995 23:10:48.803724 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2996 23:10:48.807065 ==
2997 23:10:48.817548 TX Vref=22, minBit 1, minWin=26, winSum=422
2998 23:10:48.821123 TX Vref=24, minBit 1, minWin=26, winSum=424
2999 23:10:48.824455 TX Vref=26, minBit 12, minWin=26, winSum=428
3000 23:10:48.828036 TX Vref=28, minBit 12, minWin=26, winSum=431
3001 23:10:48.830991 TX Vref=30, minBit 13, minWin=26, winSum=432
3002 23:10:48.837362 TX Vref=32, minBit 13, minWin=25, winSum=432
3003 23:10:48.841012 [TxChooseVref] Worse bit 13, Min win 26, Win sum 432, Final Vref 30
3004 23:10:48.841534
3005 23:10:48.845152 Final TX Range 1 Vref 30
3006 23:10:48.845672
3007 23:10:48.846005 ==
3008 23:10:48.848422 Dram Type= 6, Freq= 0, CH_0, rank 1
3009 23:10:48.851047 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3010 23:10:48.853882 ==
3011 23:10:48.854298
3012 23:10:48.854625
3013 23:10:48.854930 TX Vref Scan disable
3014 23:10:48.858152 == TX Byte 0 ==
3015 23:10:48.861274 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
3016 23:10:48.867436 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
3017 23:10:48.867862 == TX Byte 1 ==
3018 23:10:48.870988 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3019 23:10:48.877867 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3020 23:10:48.878379
3021 23:10:48.878716 [DATLAT]
3022 23:10:48.879023 Freq=1200, CH0 RK1
3023 23:10:48.879317
3024 23:10:48.881436 DATLAT Default: 0xd
3025 23:10:48.881950 0, 0xFFFF, sum = 0
3026 23:10:48.883914 1, 0xFFFF, sum = 0
3027 23:10:48.887335 2, 0xFFFF, sum = 0
3028 23:10:48.887803 3, 0xFFFF, sum = 0
3029 23:10:48.890589 4, 0xFFFF, sum = 0
3030 23:10:48.891008 5, 0xFFFF, sum = 0
3031 23:10:48.894570 6, 0xFFFF, sum = 0
3032 23:10:48.895092 7, 0xFFFF, sum = 0
3033 23:10:48.897583 8, 0xFFFF, sum = 0
3034 23:10:48.898006 9, 0xFFFF, sum = 0
3035 23:10:48.901112 10, 0xFFFF, sum = 0
3036 23:10:48.901631 11, 0xFFFF, sum = 0
3037 23:10:48.904355 12, 0x0, sum = 1
3038 23:10:48.904880 13, 0x0, sum = 2
3039 23:10:48.907790 14, 0x0, sum = 3
3040 23:10:48.908349 15, 0x0, sum = 4
3041 23:10:48.908701 best_step = 13
3042 23:10:48.911005
3043 23:10:48.911477 ==
3044 23:10:48.914114 Dram Type= 6, Freq= 0, CH_0, rank 1
3045 23:10:48.917663 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3046 23:10:48.918082 ==
3047 23:10:48.918411 RX Vref Scan: 0
3048 23:10:48.918721
3049 23:10:48.921435 RX Vref 0 -> 0, step: 1
3050 23:10:48.921948
3051 23:10:48.924179 RX Delay -21 -> 252, step: 4
3052 23:10:48.927465 iDelay=195, Bit 0, Center 114 (51 ~ 178) 128
3053 23:10:48.934039 iDelay=195, Bit 1, Center 116 (47 ~ 186) 140
3054 23:10:48.937086 iDelay=195, Bit 2, Center 110 (43 ~ 178) 136
3055 23:10:48.940548 iDelay=195, Bit 3, Center 112 (47 ~ 178) 132
3056 23:10:48.944860 iDelay=195, Bit 4, Center 118 (51 ~ 186) 136
3057 23:10:48.947246 iDelay=195, Bit 5, Center 108 (43 ~ 174) 132
3058 23:10:48.953547 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3059 23:10:48.957661 iDelay=195, Bit 7, Center 122 (55 ~ 190) 136
3060 23:10:48.960759 iDelay=195, Bit 8, Center 96 (27 ~ 166) 140
3061 23:10:48.963400 iDelay=195, Bit 9, Center 92 (23 ~ 162) 140
3062 23:10:48.967038 iDelay=195, Bit 10, Center 106 (39 ~ 174) 136
3063 23:10:48.973743 iDelay=195, Bit 11, Center 98 (31 ~ 166) 136
3064 23:10:48.976934 iDelay=195, Bit 12, Center 110 (43 ~ 178) 136
3065 23:10:48.980236 iDelay=195, Bit 13, Center 110 (43 ~ 178) 136
3066 23:10:48.983563 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3067 23:10:48.990457 iDelay=195, Bit 15, Center 112 (47 ~ 178) 132
3068 23:10:48.990890 ==
3069 23:10:48.993017 Dram Type= 6, Freq= 0, CH_0, rank 1
3070 23:10:48.996896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3071 23:10:48.997331 ==
3072 23:10:48.997771 DQS Delay:
3073 23:10:49.001035 DQS0 = 0, DQS1 = 0
3074 23:10:49.001557 DQM Delay:
3075 23:10:49.003495 DQM0 = 115, DQM1 = 105
3076 23:10:49.003928 DQ Delay:
3077 23:10:49.007967 DQ0 =114, DQ1 =116, DQ2 =110, DQ3 =112
3078 23:10:49.009989 DQ4 =118, DQ5 =108, DQ6 =126, DQ7 =122
3079 23:10:49.013128 DQ8 =96, DQ9 =92, DQ10 =106, DQ11 =98
3080 23:10:49.016992 DQ12 =110, DQ13 =110, DQ14 =116, DQ15 =112
3081 23:10:49.017533
3082 23:10:49.017977
3083 23:10:49.027771 [DQSOSCAuto] RK1, (LSB)MR18= 0x1fe, (MSB)MR19= 0x403, tDQSOscB0 = 410 ps tDQSOscB1 = 409 ps
3084 23:10:49.030638 CH0 RK1: MR19=403, MR18=1FE
3085 23:10:49.033851 CH0_RK1: MR19=0x403, MR18=0x1FE, DQSOSC=409, MR23=63, INC=39, DEC=26
3086 23:10:49.037124 [RxdqsGatingPostProcess] freq 1200
3087 23:10:49.043518 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3088 23:10:49.046779 best DQS0 dly(2T, 0.5T) = (0, 11)
3089 23:10:49.049933 best DQS1 dly(2T, 0.5T) = (0, 12)
3090 23:10:49.053030 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3091 23:10:49.056636 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3092 23:10:49.060938 best DQS0 dly(2T, 0.5T) = (0, 11)
3093 23:10:49.062953 best DQS1 dly(2T, 0.5T) = (0, 11)
3094 23:10:49.066764 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3095 23:10:49.069737 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3096 23:10:49.070171 Pre-setting of DQS Precalculation
3097 23:10:49.076504 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3098 23:10:49.077002 ==
3099 23:10:49.079472 Dram Type= 6, Freq= 0, CH_1, rank 0
3100 23:10:49.083162 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3101 23:10:49.083857 ==
3102 23:10:49.089622 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3103 23:10:49.096061 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3104 23:10:49.103824 [CA 0] Center 38 (8~68) winsize 61
3105 23:10:49.107668 [CA 1] Center 37 (7~68) winsize 62
3106 23:10:49.110420 [CA 2] Center 35 (6~65) winsize 60
3107 23:10:49.113821 [CA 3] Center 34 (4~64) winsize 61
3108 23:10:49.117257 [CA 4] Center 34 (4~64) winsize 61
3109 23:10:49.120459 [CA 5] Center 33 (3~63) winsize 61
3110 23:10:49.120985
3111 23:10:49.123756 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3112 23:10:49.124305
3113 23:10:49.127636 [CATrainingPosCal] consider 1 rank data
3114 23:10:49.130179 u2DelayCellTimex100 = 270/100 ps
3115 23:10:49.134171 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3116 23:10:49.140666 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3117 23:10:49.143759 CA2 delay=35 (6~65),Diff = 2 PI (9 cell)
3118 23:10:49.147458 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3119 23:10:49.149859 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3120 23:10:49.153479 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3121 23:10:49.154009
3122 23:10:49.156453 CA PerBit enable=1, Macro0, CA PI delay=33
3123 23:10:49.156883
3124 23:10:49.160655 [CBTSetCACLKResult] CA Dly = 33
3125 23:10:49.161176 CS Dly: 5 (0~36)
3126 23:10:49.163691 ==
3127 23:10:49.166769 Dram Type= 6, Freq= 0, CH_1, rank 1
3128 23:10:49.170073 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3129 23:10:49.170508 ==
3130 23:10:49.173353 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3131 23:10:49.179760 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3132 23:10:49.189456 [CA 0] Center 37 (7~68) winsize 62
3133 23:10:49.192530 [CA 1] Center 38 (8~68) winsize 61
3134 23:10:49.195717 [CA 2] Center 35 (5~65) winsize 61
3135 23:10:49.199287 [CA 3] Center 33 (3~63) winsize 61
3136 23:10:49.202544 [CA 4] Center 34 (4~64) winsize 61
3137 23:10:49.205804 [CA 5] Center 33 (3~63) winsize 61
3138 23:10:49.206329
3139 23:10:49.208954 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3140 23:10:49.209384
3141 23:10:49.213160 [CATrainingPosCal] consider 2 rank data
3142 23:10:49.215610 u2DelayCellTimex100 = 270/100 ps
3143 23:10:49.219228 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3144 23:10:49.226294 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3145 23:10:49.229143 CA2 delay=35 (6~65),Diff = 2 PI (9 cell)
3146 23:10:49.233009 CA3 delay=33 (4~63),Diff = 0 PI (0 cell)
3147 23:10:49.235501 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3148 23:10:49.239244 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3149 23:10:49.239858
3150 23:10:49.242633 CA PerBit enable=1, Macro0, CA PI delay=33
3151 23:10:49.243154
3152 23:10:49.246237 [CBTSetCACLKResult] CA Dly = 33
3153 23:10:49.246763 CS Dly: 6 (0~38)
3154 23:10:49.248983
3155 23:10:49.252775 ----->DramcWriteLeveling(PI) begin...
3156 23:10:49.253300 ==
3157 23:10:49.255981 Dram Type= 6, Freq= 0, CH_1, rank 0
3158 23:10:49.259205 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3159 23:10:49.259783 ==
3160 23:10:49.263057 Write leveling (Byte 0): 25 => 25
3161 23:10:49.265547 Write leveling (Byte 1): 26 => 26
3162 23:10:49.268950 DramcWriteLeveling(PI) end<-----
3163 23:10:49.269383
3164 23:10:49.269819 ==
3165 23:10:49.272521 Dram Type= 6, Freq= 0, CH_1, rank 0
3166 23:10:49.275858 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3167 23:10:49.276290 ==
3168 23:10:49.279258 [Gating] SW mode calibration
3169 23:10:49.285774 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3170 23:10:49.292451 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3171 23:10:49.295663 0 15 0 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
3172 23:10:49.299317 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3173 23:10:49.305542 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3174 23:10:49.309473 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3175 23:10:49.312701 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3176 23:10:49.315468 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3177 23:10:49.322650 0 15 24 | B1->B0 | 3434 3333 | 1 0 | (1 0) (0 0)
3178 23:10:49.325425 0 15 28 | B1->B0 | 2c2c 2525 | 0 0 | (0 1) (0 0)
3179 23:10:49.332299 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3180 23:10:49.335947 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3181 23:10:49.339218 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3182 23:10:49.345561 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3183 23:10:49.348191 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3184 23:10:49.352230 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3185 23:10:49.358919 1 0 24 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
3186 23:10:49.361600 1 0 28 | B1->B0 | 3e3e 4646 | 0 0 | (1 1) (0 0)
3187 23:10:49.365147 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3188 23:10:49.368408 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3189 23:10:49.374839 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3190 23:10:49.378191 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3191 23:10:49.381560 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3192 23:10:49.388091 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3193 23:10:49.392385 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3194 23:10:49.394689 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3195 23:10:49.402076 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3196 23:10:49.405100 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3197 23:10:49.408361 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3198 23:10:49.414334 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3199 23:10:49.418267 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3200 23:10:49.421223 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3201 23:10:49.428217 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3202 23:10:49.431774 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3203 23:10:49.435020 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3204 23:10:49.441638 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3205 23:10:49.444855 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3206 23:10:49.447895 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3207 23:10:49.454663 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3208 23:10:49.457920 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3209 23:10:49.461186 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3210 23:10:49.467794 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3211 23:10:49.471516 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3212 23:10:49.475401 Total UI for P1: 0, mck2ui 16
3213 23:10:49.477704 best dqsien dly found for B0: ( 1, 3, 26)
3214 23:10:49.481231 Total UI for P1: 0, mck2ui 16
3215 23:10:49.484129 best dqsien dly found for B1: ( 1, 3, 28)
3216 23:10:49.488339 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3217 23:10:49.491134 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3218 23:10:49.491604
3219 23:10:49.494807 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3220 23:10:49.498492 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3221 23:10:49.500772 [Gating] SW calibration Done
3222 23:10:49.501191 ==
3223 23:10:49.504294 Dram Type= 6, Freq= 0, CH_1, rank 0
3224 23:10:49.507648 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3225 23:10:49.510543 ==
3226 23:10:49.510957 RX Vref Scan: 0
3227 23:10:49.511285
3228 23:10:49.514297 RX Vref 0 -> 0, step: 1
3229 23:10:49.514711
3230 23:10:49.518078 RX Delay -40 -> 252, step: 8
3231 23:10:49.521791 iDelay=200, Bit 0, Center 123 (48 ~ 199) 152
3232 23:10:49.523980 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3233 23:10:49.527522 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3234 23:10:49.531020 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3235 23:10:49.538256 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3236 23:10:49.540963 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3237 23:10:49.544055 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3238 23:10:49.547470 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3239 23:10:49.550382 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3240 23:10:49.557642 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3241 23:10:49.560773 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3242 23:10:49.564473 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3243 23:10:49.567221 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3244 23:10:49.570483 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3245 23:10:49.577410 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3246 23:10:49.580518 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3247 23:10:49.581028 ==
3248 23:10:49.583945 Dram Type= 6, Freq= 0, CH_1, rank 0
3249 23:10:49.587347 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3250 23:10:49.587911 ==
3251 23:10:49.590340 DQS Delay:
3252 23:10:49.590753 DQS0 = 0, DQS1 = 0
3253 23:10:49.591079 DQM Delay:
3254 23:10:49.593847 DQM0 = 115, DQM1 = 112
3255 23:10:49.594354 DQ Delay:
3256 23:10:49.597003 DQ0 =123, DQ1 =111, DQ2 =107, DQ3 =115
3257 23:10:49.600121 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =111
3258 23:10:49.604280 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
3259 23:10:49.610635 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =119
3260 23:10:49.611128
3261 23:10:49.611504
3262 23:10:49.611820 ==
3263 23:10:49.613247 Dram Type= 6, Freq= 0, CH_1, rank 0
3264 23:10:49.616757 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3265 23:10:49.617172 ==
3266 23:10:49.617498
3267 23:10:49.617799
3268 23:10:49.619903 TX Vref Scan disable
3269 23:10:49.620261 == TX Byte 0 ==
3270 23:10:49.626768 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3271 23:10:49.630091 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3272 23:10:49.630681 == TX Byte 1 ==
3273 23:10:49.637048 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3274 23:10:49.639956 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3275 23:10:49.640465 ==
3276 23:10:49.643120 Dram Type= 6, Freq= 0, CH_1, rank 0
3277 23:10:49.646694 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3278 23:10:49.647226 ==
3279 23:10:49.659867 TX Vref=22, minBit 9, minWin=23, winSum=409
3280 23:10:49.662885 TX Vref=24, minBit 9, minWin=24, winSum=413
3281 23:10:49.665938 TX Vref=26, minBit 8, minWin=25, winSum=420
3282 23:10:49.669067 TX Vref=28, minBit 9, minWin=24, winSum=420
3283 23:10:49.672306 TX Vref=30, minBit 9, minWin=25, winSum=424
3284 23:10:49.679176 TX Vref=32, minBit 9, minWin=25, winSum=426
3285 23:10:49.682949 [TxChooseVref] Worse bit 9, Min win 25, Win sum 426, Final Vref 32
3286 23:10:49.683510
3287 23:10:49.685726 Final TX Range 1 Vref 32
3288 23:10:49.686137
3289 23:10:49.686463 ==
3290 23:10:49.689012 Dram Type= 6, Freq= 0, CH_1, rank 0
3291 23:10:49.692564 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3292 23:10:49.693087 ==
3293 23:10:49.695902
3294 23:10:49.696446
3295 23:10:49.696781 TX Vref Scan disable
3296 23:10:49.698897 == TX Byte 0 ==
3297 23:10:49.702186 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3298 23:10:49.706627 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3299 23:10:49.709090 == TX Byte 1 ==
3300 23:10:49.712239 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3301 23:10:49.719235 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3302 23:10:49.719793
3303 23:10:49.720131 [DATLAT]
3304 23:10:49.720434 Freq=1200, CH1 RK0
3305 23:10:49.720725
3306 23:10:49.722097 DATLAT Default: 0xd
3307 23:10:49.722506 0, 0xFFFF, sum = 0
3308 23:10:49.725402 1, 0xFFFF, sum = 0
3309 23:10:49.728883 2, 0xFFFF, sum = 0
3310 23:10:49.729395 3, 0xFFFF, sum = 0
3311 23:10:49.733252 4, 0xFFFF, sum = 0
3312 23:10:49.733767 5, 0xFFFF, sum = 0
3313 23:10:49.736049 6, 0xFFFF, sum = 0
3314 23:10:49.736562 7, 0xFFFF, sum = 0
3315 23:10:49.738826 8, 0xFFFF, sum = 0
3316 23:10:49.739440 9, 0xFFFF, sum = 0
3317 23:10:49.742446 10, 0xFFFF, sum = 0
3318 23:10:49.742955 11, 0xFFFF, sum = 0
3319 23:10:49.745208 12, 0x0, sum = 1
3320 23:10:49.745626 13, 0x0, sum = 2
3321 23:10:49.748729 14, 0x0, sum = 3
3322 23:10:49.749147 15, 0x0, sum = 4
3323 23:10:49.752187 best_step = 13
3324 23:10:49.752695
3325 23:10:49.753024 ==
3326 23:10:49.755553 Dram Type= 6, Freq= 0, CH_1, rank 0
3327 23:10:49.758756 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3328 23:10:49.759265 ==
3329 23:10:49.759637 RX Vref Scan: 1
3330 23:10:49.759946
3331 23:10:49.761694 Set Vref Range= 32 -> 127
3332 23:10:49.762107
3333 23:10:49.765326 RX Vref 32 -> 127, step: 1
3334 23:10:49.765739
3335 23:10:49.768671 RX Delay -13 -> 252, step: 4
3336 23:10:49.769359
3337 23:10:49.771750 Set Vref, RX VrefLevel [Byte0]: 32
3338 23:10:49.775243 [Byte1]: 32
3339 23:10:49.775802
3340 23:10:49.778471 Set Vref, RX VrefLevel [Byte0]: 33
3341 23:10:49.781953 [Byte1]: 33
3342 23:10:49.785846
3343 23:10:49.786352 Set Vref, RX VrefLevel [Byte0]: 34
3344 23:10:49.788825 [Byte1]: 34
3345 23:10:49.793486
3346 23:10:49.793992 Set Vref, RX VrefLevel [Byte0]: 35
3347 23:10:49.796523 [Byte1]: 35
3348 23:10:49.801637
3349 23:10:49.802141 Set Vref, RX VrefLevel [Byte0]: 36
3350 23:10:49.804640 [Byte1]: 36
3351 23:10:49.809041
3352 23:10:49.809553 Set Vref, RX VrefLevel [Byte0]: 37
3353 23:10:49.812304 [Byte1]: 37
3354 23:10:49.817093
3355 23:10:49.817505 Set Vref, RX VrefLevel [Byte0]: 38
3356 23:10:49.819997 [Byte1]: 38
3357 23:10:49.824614
3358 23:10:49.825021 Set Vref, RX VrefLevel [Byte0]: 39
3359 23:10:49.828089 [Byte1]: 39
3360 23:10:49.832691
3361 23:10:49.833102 Set Vref, RX VrefLevel [Byte0]: 40
3362 23:10:49.836082 [Byte1]: 40
3363 23:10:49.840340
3364 23:10:49.840746 Set Vref, RX VrefLevel [Byte0]: 41
3365 23:10:49.843825 [Byte1]: 41
3366 23:10:49.848321
3367 23:10:49.848727 Set Vref, RX VrefLevel [Byte0]: 42
3368 23:10:49.851875 [Byte1]: 42
3369 23:10:49.856252
3370 23:10:49.856759 Set Vref, RX VrefLevel [Byte0]: 43
3371 23:10:49.860428 [Byte1]: 43
3372 23:10:49.864349
3373 23:10:49.864854 Set Vref, RX VrefLevel [Byte0]: 44
3374 23:10:49.867806 [Byte1]: 44
3375 23:10:49.871958
3376 23:10:49.872372 Set Vref, RX VrefLevel [Byte0]: 45
3377 23:10:49.876194 [Byte1]: 45
3378 23:10:49.879972
3379 23:10:49.880379 Set Vref, RX VrefLevel [Byte0]: 46
3380 23:10:49.883137 [Byte1]: 46
3381 23:10:49.888099
3382 23:10:49.888509 Set Vref, RX VrefLevel [Byte0]: 47
3383 23:10:49.891066 [Byte1]: 47
3384 23:10:49.896017
3385 23:10:49.896426 Set Vref, RX VrefLevel [Byte0]: 48
3386 23:10:49.899147 [Byte1]: 48
3387 23:10:49.903788
3388 23:10:49.904195 Set Vref, RX VrefLevel [Byte0]: 49
3389 23:10:49.906947 [Byte1]: 49
3390 23:10:49.911561
3391 23:10:49.911967 Set Vref, RX VrefLevel [Byte0]: 50
3392 23:10:49.914836 [Byte1]: 50
3393 23:10:49.919759
3394 23:10:49.920260 Set Vref, RX VrefLevel [Byte0]: 51
3395 23:10:49.922767 [Byte1]: 51
3396 23:10:49.927698
3397 23:10:49.928107 Set Vref, RX VrefLevel [Byte0]: 52
3398 23:10:49.930865 [Byte1]: 52
3399 23:10:49.935351
3400 23:10:49.935894 Set Vref, RX VrefLevel [Byte0]: 53
3401 23:10:49.938624 [Byte1]: 53
3402 23:10:49.942953
3403 23:10:49.943360 Set Vref, RX VrefLevel [Byte0]: 54
3404 23:10:49.946270 [Byte1]: 54
3405 23:10:49.951423
3406 23:10:49.951932 Set Vref, RX VrefLevel [Byte0]: 55
3407 23:10:49.954561 [Byte1]: 55
3408 23:10:49.958980
3409 23:10:49.959520 Set Vref, RX VrefLevel [Byte0]: 56
3410 23:10:49.962593 [Byte1]: 56
3411 23:10:49.967019
3412 23:10:49.967559 Set Vref, RX VrefLevel [Byte0]: 57
3413 23:10:49.969997 [Byte1]: 57
3414 23:10:49.974733
3415 23:10:49.975256 Set Vref, RX VrefLevel [Byte0]: 58
3416 23:10:49.977735 [Byte1]: 58
3417 23:10:49.982635
3418 23:10:49.983150 Set Vref, RX VrefLevel [Byte0]: 59
3419 23:10:49.986388 [Byte1]: 59
3420 23:10:49.990741
3421 23:10:49.991245 Set Vref, RX VrefLevel [Byte0]: 60
3422 23:10:49.994301 [Byte1]: 60
3423 23:10:49.998310
3424 23:10:49.998815 Set Vref, RX VrefLevel [Byte0]: 61
3425 23:10:50.001963 [Byte1]: 61
3426 23:10:50.006111
3427 23:10:50.006610 Set Vref, RX VrefLevel [Byte0]: 62
3428 23:10:50.009336 [Byte1]: 62
3429 23:10:50.014008
3430 23:10:50.014505 Set Vref, RX VrefLevel [Byte0]: 63
3431 23:10:50.017233 [Byte1]: 63
3432 23:10:50.021822
3433 23:10:50.022275 Set Vref, RX VrefLevel [Byte0]: 64
3434 23:10:50.024666 [Byte1]: 64
3435 23:10:50.028989
3436 23:10:50.029069 Set Vref, RX VrefLevel [Byte0]: 65
3437 23:10:50.032639 [Byte1]: 65
3438 23:10:50.037342
3439 23:10:50.037428 Final RX Vref Byte 0 = 51 to rank0
3440 23:10:50.040341 Final RX Vref Byte 1 = 48 to rank0
3441 23:10:50.043786 Final RX Vref Byte 0 = 51 to rank1
3442 23:10:50.047203 Final RX Vref Byte 1 = 48 to rank1==
3443 23:10:50.050105 Dram Type= 6, Freq= 0, CH_1, rank 0
3444 23:10:50.057336 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3445 23:10:50.057820 ==
3446 23:10:50.058141 DQS Delay:
3447 23:10:50.060622 DQS0 = 0, DQS1 = 0
3448 23:10:50.061061 DQM Delay:
3449 23:10:50.061397 DQM0 = 114, DQM1 = 111
3450 23:10:50.063827 DQ Delay:
3451 23:10:50.067192 DQ0 =120, DQ1 =110, DQ2 =106, DQ3 =114
3452 23:10:50.070495 DQ4 =110, DQ5 =122, DQ6 =124, DQ7 =110
3453 23:10:50.074140 DQ8 =96, DQ9 =102, DQ10 =114, DQ11 =106
3454 23:10:50.077641 DQ12 =120, DQ13 =118, DQ14 =116, DQ15 =120
3455 23:10:50.078055
3456 23:10:50.078381
3457 23:10:50.087450 [DQSOSCAuto] RK0, (LSB)MR18= 0xf3ff, (MSB)MR19= 0x303, tDQSOscB0 = 410 ps tDQSOscB1 = 415 ps
3458 23:10:50.087957 CH1 RK0: MR19=303, MR18=F3FF
3459 23:10:50.093667 CH1_RK0: MR19=0x303, MR18=0xF3FF, DQSOSC=410, MR23=63, INC=39, DEC=26
3460 23:10:50.094174
3461 23:10:50.096651 ----->DramcWriteLeveling(PI) begin...
3462 23:10:50.097073 ==
3463 23:10:50.100074 Dram Type= 6, Freq= 0, CH_1, rank 1
3464 23:10:50.107033 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3465 23:10:50.107590 ==
3466 23:10:50.110469 Write leveling (Byte 0): 26 => 26
3467 23:10:50.113836 Write leveling (Byte 1): 27 => 27
3468 23:10:50.114283 DramcWriteLeveling(PI) end<-----
3469 23:10:50.114616
3470 23:10:50.116663 ==
3471 23:10:50.120631 Dram Type= 6, Freq= 0, CH_1, rank 1
3472 23:10:50.123557 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3473 23:10:50.123979 ==
3474 23:10:50.127082 [Gating] SW mode calibration
3475 23:10:50.133617 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3476 23:10:50.136744 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3477 23:10:50.143462 0 15 0 | B1->B0 | 3333 3434 | 1 1 | (0 0) (1 1)
3478 23:10:50.146596 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3479 23:10:50.150169 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3480 23:10:50.156588 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3481 23:10:50.160350 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3482 23:10:50.163128 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3483 23:10:50.169925 0 15 24 | B1->B0 | 3434 2727 | 1 0 | (1 0) (1 0)
3484 23:10:50.173329 0 15 28 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (0 0)
3485 23:10:50.176418 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3486 23:10:50.183299 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3487 23:10:50.186355 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3488 23:10:50.189996 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3489 23:10:50.196699 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3490 23:10:50.199750 1 0 20 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
3491 23:10:50.203302 1 0 24 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
3492 23:10:50.209491 1 0 28 | B1->B0 | 3434 4646 | 1 0 | (0 0) (0 0)
3493 23:10:50.212828 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3494 23:10:50.216000 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3495 23:10:50.223290 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3496 23:10:50.226224 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3497 23:10:50.229444 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3498 23:10:50.237210 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3499 23:10:50.239263 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3500 23:10:50.242527 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3501 23:10:50.249660 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3502 23:10:50.253143 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3503 23:10:50.256612 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3504 23:10:50.263287 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3505 23:10:50.266329 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3506 23:10:50.269403 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3507 23:10:50.276485 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3508 23:10:50.279044 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3509 23:10:50.282350 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3510 23:10:50.289276 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3511 23:10:50.292262 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3512 23:10:50.295749 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3513 23:10:50.302146 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3514 23:10:50.305646 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3515 23:10:50.308724 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3516 23:10:50.315195 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3517 23:10:50.315663 Total UI for P1: 0, mck2ui 16
3518 23:10:50.322600 best dqsien dly found for B0: ( 1, 3, 22)
3519 23:10:50.325847 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3520 23:10:50.328572 Total UI for P1: 0, mck2ui 16
3521 23:10:50.331854 best dqsien dly found for B1: ( 1, 3, 28)
3522 23:10:50.335258 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3523 23:10:50.338508 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3524 23:10:50.339056
3525 23:10:50.341589 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3526 23:10:50.344834 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3527 23:10:50.348134 [Gating] SW calibration Done
3528 23:10:50.348516 ==
3529 23:10:50.351438 Dram Type= 6, Freq= 0, CH_1, rank 1
3530 23:10:50.354530 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3531 23:10:50.358505 ==
3532 23:10:50.359024 RX Vref Scan: 0
3533 23:10:50.359356
3534 23:10:50.360899 RX Vref 0 -> 0, step: 1
3535 23:10:50.361312
3536 23:10:50.364525 RX Delay -40 -> 252, step: 8
3537 23:10:50.368209 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3538 23:10:50.371400 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3539 23:10:50.374333 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3540 23:10:50.377659 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3541 23:10:50.384435 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3542 23:10:50.387732 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3543 23:10:50.390907 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
3544 23:10:50.394090 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3545 23:10:50.398065 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3546 23:10:50.403953 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3547 23:10:50.407493 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3548 23:10:50.410459 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3549 23:10:50.414516 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3550 23:10:50.420698 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3551 23:10:50.423936 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3552 23:10:50.427861 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3553 23:10:50.428276 ==
3554 23:10:50.430400 Dram Type= 6, Freq= 0, CH_1, rank 1
3555 23:10:50.433763 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3556 23:10:50.434281 ==
3557 23:10:50.437202 DQS Delay:
3558 23:10:50.437717 DQS0 = 0, DQS1 = 0
3559 23:10:50.440315 DQM Delay:
3560 23:10:50.440725 DQM0 = 114, DQM1 = 111
3561 23:10:50.443440 DQ Delay:
3562 23:10:50.447484 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =111
3563 23:10:50.450054 DQ4 =115, DQ5 =123, DQ6 =119, DQ7 =111
3564 23:10:50.453696 DQ8 =99, DQ9 =99, DQ10 =111, DQ11 =107
3565 23:10:50.456645 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3566 23:10:50.457099
3567 23:10:50.457429
3568 23:10:50.457735 ==
3569 23:10:50.459977 Dram Type= 6, Freq= 0, CH_1, rank 1
3570 23:10:50.463437 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3571 23:10:50.463980 ==
3572 23:10:50.464317
3573 23:10:50.464627
3574 23:10:50.466266 TX Vref Scan disable
3575 23:10:50.470421 == TX Byte 0 ==
3576 23:10:50.472685 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3577 23:10:50.475901 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3578 23:10:50.479357 == TX Byte 1 ==
3579 23:10:50.482674 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3580 23:10:50.486302 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3581 23:10:50.486823 ==
3582 23:10:50.489185 Dram Type= 6, Freq= 0, CH_1, rank 1
3583 23:10:50.495818 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3584 23:10:50.496339 ==
3585 23:10:50.506815 TX Vref=22, minBit 9, minWin=25, winSum=421
3586 23:10:50.510311 TX Vref=24, minBit 9, minWin=25, winSum=422
3587 23:10:50.513072 TX Vref=26, minBit 9, minWin=25, winSum=423
3588 23:10:50.516346 TX Vref=28, minBit 9, minWin=24, winSum=424
3589 23:10:50.519895 TX Vref=30, minBit 1, minWin=26, winSum=430
3590 23:10:50.526032 TX Vref=32, minBit 1, minWin=26, winSum=428
3591 23:10:50.529501 [TxChooseVref] Worse bit 1, Min win 26, Win sum 430, Final Vref 30
3592 23:10:50.530033
3593 23:10:50.533101 Final TX Range 1 Vref 30
3594 23:10:50.533621
3595 23:10:50.533999 ==
3596 23:10:50.536078 Dram Type= 6, Freq= 0, CH_1, rank 1
3597 23:10:50.539625 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3598 23:10:50.542397 ==
3599 23:10:50.542819
3600 23:10:50.543146
3601 23:10:50.543481 TX Vref Scan disable
3602 23:10:50.546006 == TX Byte 0 ==
3603 23:10:50.549693 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3604 23:10:50.556430 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3605 23:10:50.556950 == TX Byte 1 ==
3606 23:10:50.559275 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3607 23:10:50.565863 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3608 23:10:50.566368
3609 23:10:50.566699 [DATLAT]
3610 23:10:50.567006 Freq=1200, CH1 RK1
3611 23:10:50.567302
3612 23:10:50.569240 DATLAT Default: 0xd
3613 23:10:50.572639 0, 0xFFFF, sum = 0
3614 23:10:50.573063 1, 0xFFFF, sum = 0
3615 23:10:50.575625 2, 0xFFFF, sum = 0
3616 23:10:50.576074 3, 0xFFFF, sum = 0
3617 23:10:50.579711 4, 0xFFFF, sum = 0
3618 23:10:50.580127 5, 0xFFFF, sum = 0
3619 23:10:50.582370 6, 0xFFFF, sum = 0
3620 23:10:50.582890 7, 0xFFFF, sum = 0
3621 23:10:50.585696 8, 0xFFFF, sum = 0
3622 23:10:50.586214 9, 0xFFFF, sum = 0
3623 23:10:50.588940 10, 0xFFFF, sum = 0
3624 23:10:50.589471 11, 0xFFFF, sum = 0
3625 23:10:50.592283 12, 0x0, sum = 1
3626 23:10:50.592698 13, 0x0, sum = 2
3627 23:10:50.596208 14, 0x0, sum = 3
3628 23:10:50.596626 15, 0x0, sum = 4
3629 23:10:50.598845 best_step = 13
3630 23:10:50.599255
3631 23:10:50.599623 ==
3632 23:10:50.602266 Dram Type= 6, Freq= 0, CH_1, rank 1
3633 23:10:50.605460 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3634 23:10:50.605976 ==
3635 23:10:50.608671 RX Vref Scan: 0
3636 23:10:50.609081
3637 23:10:50.609402 RX Vref 0 -> 0, step: 1
3638 23:10:50.609704
3639 23:10:50.611727 RX Delay -13 -> 252, step: 4
3640 23:10:50.618144 iDelay=195, Bit 0, Center 116 (47 ~ 186) 140
3641 23:10:50.622496 iDelay=195, Bit 1, Center 112 (43 ~ 182) 140
3642 23:10:50.625441 iDelay=195, Bit 2, Center 108 (43 ~ 174) 132
3643 23:10:50.628868 iDelay=195, Bit 3, Center 114 (47 ~ 182) 136
3644 23:10:50.632103 iDelay=195, Bit 4, Center 114 (47 ~ 182) 136
3645 23:10:50.638506 iDelay=195, Bit 5, Center 124 (55 ~ 194) 140
3646 23:10:50.641868 iDelay=195, Bit 6, Center 122 (55 ~ 190) 136
3647 23:10:50.645244 iDelay=195, Bit 7, Center 112 (43 ~ 182) 140
3648 23:10:50.648311 iDelay=195, Bit 8, Center 100 (39 ~ 162) 124
3649 23:10:50.651817 iDelay=195, Bit 9, Center 102 (43 ~ 162) 120
3650 23:10:50.658035 iDelay=195, Bit 10, Center 114 (51 ~ 178) 128
3651 23:10:50.661344 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3652 23:10:50.664783 iDelay=195, Bit 12, Center 120 (59 ~ 182) 124
3653 23:10:50.668688 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3654 23:10:50.674230 iDelay=195, Bit 14, Center 116 (55 ~ 178) 124
3655 23:10:50.677984 iDelay=195, Bit 15, Center 120 (55 ~ 186) 132
3656 23:10:50.678401 ==
3657 23:10:50.681047 Dram Type= 6, Freq= 0, CH_1, rank 1
3658 23:10:50.684460 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3659 23:10:50.684881 ==
3660 23:10:50.687469 DQS Delay:
3661 23:10:50.687888 DQS0 = 0, DQS1 = 0
3662 23:10:50.688223 DQM Delay:
3663 23:10:50.690735 DQM0 = 115, DQM1 = 112
3664 23:10:50.691145 DQ Delay:
3665 23:10:50.694233 DQ0 =116, DQ1 =112, DQ2 =108, DQ3 =114
3666 23:10:50.698280 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =112
3667 23:10:50.701126 DQ8 =100, DQ9 =102, DQ10 =114, DQ11 =106
3668 23:10:50.707896 DQ12 =120, DQ13 =118, DQ14 =116, DQ15 =120
3669 23:10:50.708412
3670 23:10:50.708738
3671 23:10:50.714455 [DQSOSCAuto] RK1, (LSB)MR18= 0xfa0c, (MSB)MR19= 0x304, tDQSOscB0 = 405 ps tDQSOscB1 = 412 ps
3672 23:10:50.718121 CH1 RK1: MR19=304, MR18=FA0C
3673 23:10:50.724173 CH1_RK1: MR19=0x304, MR18=0xFA0C, DQSOSC=405, MR23=63, INC=39, DEC=26
3674 23:10:50.727879 [RxdqsGatingPostProcess] freq 1200
3675 23:10:50.734057 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3676 23:10:50.734573 best DQS0 dly(2T, 0.5T) = (0, 11)
3677 23:10:50.737424 best DQS1 dly(2T, 0.5T) = (0, 11)
3678 23:10:50.740478 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3679 23:10:50.744347 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3680 23:10:50.747073 best DQS0 dly(2T, 0.5T) = (0, 11)
3681 23:10:50.750580 best DQS1 dly(2T, 0.5T) = (0, 11)
3682 23:10:50.753906 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3683 23:10:50.756827 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3684 23:10:50.760246 Pre-setting of DQS Precalculation
3685 23:10:50.766811 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3686 23:10:50.773418 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3687 23:10:50.780078 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3688 23:10:50.780497
3689 23:10:50.780928
3690 23:10:50.783106 [Calibration Summary] 2400 Mbps
3691 23:10:50.783556 CH 0, Rank 0
3692 23:10:50.787008 SW Impedance : PASS
3693 23:10:50.790211 DUTY Scan : NO K
3694 23:10:50.790720 ZQ Calibration : PASS
3695 23:10:50.793182 Jitter Meter : NO K
3696 23:10:50.796694 CBT Training : PASS
3697 23:10:50.797128 Write leveling : PASS
3698 23:10:50.799983 RX DQS gating : PASS
3699 23:10:50.803156 RX DQ/DQS(RDDQC) : PASS
3700 23:10:50.803840 TX DQ/DQS : PASS
3701 23:10:50.806686 RX DATLAT : PASS
3702 23:10:50.807104 RX DQ/DQS(Engine): PASS
3703 23:10:50.809774 TX OE : NO K
3704 23:10:50.810293 All Pass.
3705 23:10:50.810626
3706 23:10:50.812797 CH 0, Rank 1
3707 23:10:50.815990 SW Impedance : PASS
3708 23:10:50.816405 DUTY Scan : NO K
3709 23:10:50.819177 ZQ Calibration : PASS
3710 23:10:50.819660 Jitter Meter : NO K
3711 23:10:50.822834 CBT Training : PASS
3712 23:10:50.826397 Write leveling : PASS
3713 23:10:50.826918 RX DQS gating : PASS
3714 23:10:50.830561 RX DQ/DQS(RDDQC) : PASS
3715 23:10:50.834228 TX DQ/DQS : PASS
3716 23:10:50.834748 RX DATLAT : PASS
3717 23:10:50.836161 RX DQ/DQS(Engine): PASS
3718 23:10:50.839244 TX OE : NO K
3719 23:10:50.839853 All Pass.
3720 23:10:50.840201
3721 23:10:50.840523 CH 1, Rank 0
3722 23:10:50.842836 SW Impedance : PASS
3723 23:10:50.846251 DUTY Scan : NO K
3724 23:10:50.846772 ZQ Calibration : PASS
3725 23:10:50.849392 Jitter Meter : NO K
3726 23:10:50.852381 CBT Training : PASS
3727 23:10:50.852889 Write leveling : PASS
3728 23:10:50.855858 RX DQS gating : PASS
3729 23:10:50.858647 RX DQ/DQS(RDDQC) : PASS
3730 23:10:50.859061 TX DQ/DQS : PASS
3731 23:10:50.862430 RX DATLAT : PASS
3732 23:10:50.865531 RX DQ/DQS(Engine): PASS
3733 23:10:50.866047 TX OE : NO K
3734 23:10:50.868654 All Pass.
3735 23:10:50.869084
3736 23:10:50.869408 CH 1, Rank 1
3737 23:10:50.872129 SW Impedance : PASS
3738 23:10:50.872546 DUTY Scan : NO K
3739 23:10:50.875318 ZQ Calibration : PASS
3740 23:10:50.878664 Jitter Meter : NO K
3741 23:10:50.879075 CBT Training : PASS
3742 23:10:50.881787 Write leveling : PASS
3743 23:10:50.885437 RX DQS gating : PASS
3744 23:10:50.885953 RX DQ/DQS(RDDQC) : PASS
3745 23:10:50.888788 TX DQ/DQS : PASS
3746 23:10:50.891846 RX DATLAT : PASS
3747 23:10:50.892259 RX DQ/DQS(Engine): PASS
3748 23:10:50.895179 TX OE : NO K
3749 23:10:50.895723 All Pass.
3750 23:10:50.896052
3751 23:10:50.898687 DramC Write-DBI off
3752 23:10:50.902138 PER_BANK_REFRESH: Hybrid Mode
3753 23:10:50.902657 TX_TRACKING: ON
3754 23:10:50.912082 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3755 23:10:50.915449 [FAST_K] Save calibration result to emmc
3756 23:10:50.918402 dramc_set_vcore_voltage set vcore to 650000
3757 23:10:50.921460 Read voltage for 600, 5
3758 23:10:50.921880 Vio18 = 0
3759 23:10:50.922209 Vcore = 650000
3760 23:10:50.925834 Vdram = 0
3761 23:10:50.926344 Vddq = 0
3762 23:10:50.926675 Vmddr = 0
3763 23:10:50.931513 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3764 23:10:50.934807 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3765 23:10:50.938552 MEM_TYPE=3, freq_sel=19
3766 23:10:50.942020 sv_algorithm_assistance_LP4_1600
3767 23:10:50.944758 ============ PULL DRAM RESETB DOWN ============
3768 23:10:50.948110 ========== PULL DRAM RESETB DOWN end =========
3769 23:10:50.954724 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3770 23:10:50.958074 ===================================
3771 23:10:50.961164 LPDDR4 DRAM CONFIGURATION
3772 23:10:50.964592 ===================================
3773 23:10:50.965101 EX_ROW_EN[0] = 0x0
3774 23:10:50.968031 EX_ROW_EN[1] = 0x0
3775 23:10:50.968534 LP4Y_EN = 0x0
3776 23:10:50.971590 WORK_FSP = 0x0
3777 23:10:50.972006 WL = 0x2
3778 23:10:50.974449 RL = 0x2
3779 23:10:50.975113 BL = 0x2
3780 23:10:50.977890 RPST = 0x0
3781 23:10:50.978324 RD_PRE = 0x0
3782 23:10:50.980884 WR_PRE = 0x1
3783 23:10:50.981370 WR_PST = 0x0
3784 23:10:50.984336 DBI_WR = 0x0
3785 23:10:50.985073 DBI_RD = 0x0
3786 23:10:50.987325 OTF = 0x1
3787 23:10:50.991281 ===================================
3788 23:10:50.994273 ===================================
3789 23:10:50.994697 ANA top config
3790 23:10:50.996948 ===================================
3791 23:10:51.000335 DLL_ASYNC_EN = 0
3792 23:10:51.003978 ALL_SLAVE_EN = 1
3793 23:10:51.007283 NEW_RANK_MODE = 1
3794 23:10:51.010760 DLL_IDLE_MODE = 1
3795 23:10:51.011270 LP45_APHY_COMB_EN = 1
3796 23:10:51.014136 TX_ODT_DIS = 1
3797 23:10:51.016648 NEW_8X_MODE = 1
3798 23:10:51.020015 ===================================
3799 23:10:51.023613 ===================================
3800 23:10:51.027497 data_rate = 1200
3801 23:10:51.030228 CKR = 1
3802 23:10:51.033553 DQ_P2S_RATIO = 8
3803 23:10:51.036989 ===================================
3804 23:10:51.037519 CA_P2S_RATIO = 8
3805 23:10:51.040051 DQ_CA_OPEN = 0
3806 23:10:51.043255 DQ_SEMI_OPEN = 0
3807 23:10:51.047569 CA_SEMI_OPEN = 0
3808 23:10:51.049993 CA_FULL_RATE = 0
3809 23:10:51.053802 DQ_CKDIV4_EN = 1
3810 23:10:51.054223 CA_CKDIV4_EN = 1
3811 23:10:51.056040 CA_PREDIV_EN = 0
3812 23:10:51.059737 PH8_DLY = 0
3813 23:10:51.062680 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3814 23:10:51.066006 DQ_AAMCK_DIV = 4
3815 23:10:51.069194 CA_AAMCK_DIV = 4
3816 23:10:51.069286 CA_ADMCK_DIV = 4
3817 23:10:51.072398 DQ_TRACK_CA_EN = 0
3818 23:10:51.075717 CA_PICK = 600
3819 23:10:51.079318 CA_MCKIO = 600
3820 23:10:51.082857 MCKIO_SEMI = 0
3821 23:10:51.085743 PLL_FREQ = 2288
3822 23:10:51.089425 DQ_UI_PI_RATIO = 32
3823 23:10:51.092377 CA_UI_PI_RATIO = 0
3824 23:10:51.095451 ===================================
3825 23:10:51.095700 ===================================
3826 23:10:51.098868 memory_type:LPDDR4
3827 23:10:51.102108 GP_NUM : 10
3828 23:10:51.102385 SRAM_EN : 1
3829 23:10:51.105714 MD32_EN : 0
3830 23:10:51.108632 ===================================
3831 23:10:51.112557 [ANA_INIT] >>>>>>>>>>>>>>
3832 23:10:51.115687 <<<<<< [CONFIGURE PHASE]: ANA_TX
3833 23:10:51.119058 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3834 23:10:51.122159 ===================================
3835 23:10:51.126397 data_rate = 1200,PCW = 0X5800
3836 23:10:51.129500 ===================================
3837 23:10:51.132038 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3838 23:10:51.135402 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3839 23:10:51.141859 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3840 23:10:51.145662 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3841 23:10:51.148217 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3842 23:10:51.152507 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3843 23:10:51.155099 [ANA_INIT] flow start
3844 23:10:51.158130 [ANA_INIT] PLL >>>>>>>>
3845 23:10:51.158566 [ANA_INIT] PLL <<<<<<<<
3846 23:10:51.161691 [ANA_INIT] MIDPI >>>>>>>>
3847 23:10:51.165179 [ANA_INIT] MIDPI <<<<<<<<
3848 23:10:51.168817 [ANA_INIT] DLL >>>>>>>>
3849 23:10:51.169331 [ANA_INIT] flow end
3850 23:10:51.171821 ============ LP4 DIFF to SE enter ============
3851 23:10:51.178447 ============ LP4 DIFF to SE exit ============
3852 23:10:51.178896 [ANA_INIT] <<<<<<<<<<<<<
3853 23:10:51.181422 [Flow] Enable top DCM control >>>>>
3854 23:10:51.184731 [Flow] Enable top DCM control <<<<<
3855 23:10:51.187656 Enable DLL master slave shuffle
3856 23:10:51.194621 ==============================================================
3857 23:10:51.195077 Gating Mode config
3858 23:10:51.201431 ==============================================================
3859 23:10:51.204456 Config description:
3860 23:10:51.214494 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3861 23:10:51.221041 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3862 23:10:51.224283 SELPH_MODE 0: By rank 1: By Phase
3863 23:10:51.231035 ==============================================================
3864 23:10:51.234842 GAT_TRACK_EN = 1
3865 23:10:51.237166 RX_GATING_MODE = 2
3866 23:10:51.240773 RX_GATING_TRACK_MODE = 2
3867 23:10:51.241191 SELPH_MODE = 1
3868 23:10:51.244127 PICG_EARLY_EN = 1
3869 23:10:51.247439 VALID_LAT_VALUE = 1
3870 23:10:51.254525 ==============================================================
3871 23:10:51.257428 Enter into Gating configuration >>>>
3872 23:10:51.260533 Exit from Gating configuration <<<<
3873 23:10:51.263612 Enter into DVFS_PRE_config >>>>>
3874 23:10:51.273761 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3875 23:10:51.277072 Exit from DVFS_PRE_config <<<<<
3876 23:10:51.280143 Enter into PICG configuration >>>>
3877 23:10:51.283232 Exit from PICG configuration <<<<
3878 23:10:51.286706 [RX_INPUT] configuration >>>>>
3879 23:10:51.290560 [RX_INPUT] configuration <<<<<
3880 23:10:51.293792 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3881 23:10:51.300114 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3882 23:10:51.306649 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3883 23:10:51.313094 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3884 23:10:51.319810 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3885 23:10:51.326204 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3886 23:10:51.330150 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3887 23:10:51.332774 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3888 23:10:51.336150 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3889 23:10:51.342851 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3890 23:10:51.347083 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3891 23:10:51.349281 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3892 23:10:51.352536 ===================================
3893 23:10:51.355840 LPDDR4 DRAM CONFIGURATION
3894 23:10:51.359149 ===================================
3895 23:10:51.359612 EX_ROW_EN[0] = 0x0
3896 23:10:51.362932 EX_ROW_EN[1] = 0x0
3897 23:10:51.366404 LP4Y_EN = 0x0
3898 23:10:51.366910 WORK_FSP = 0x0
3899 23:10:51.370043 WL = 0x2
3900 23:10:51.370545 RL = 0x2
3901 23:10:51.372881 BL = 0x2
3902 23:10:51.373457 RPST = 0x0
3903 23:10:51.375955 RD_PRE = 0x0
3904 23:10:51.376381 WR_PRE = 0x1
3905 23:10:51.379216 WR_PST = 0x0
3906 23:10:51.379704 DBI_WR = 0x0
3907 23:10:51.381990 DBI_RD = 0x0
3908 23:10:51.382402 OTF = 0x1
3909 23:10:51.385736 ===================================
3910 23:10:51.388882 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3911 23:10:51.395760 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3912 23:10:51.398980 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3913 23:10:51.402219 ===================================
3914 23:10:51.405911 LPDDR4 DRAM CONFIGURATION
3915 23:10:51.408680 ===================================
3916 23:10:51.409242 EX_ROW_EN[0] = 0x10
3917 23:10:51.411742 EX_ROW_EN[1] = 0x0
3918 23:10:51.415357 LP4Y_EN = 0x0
3919 23:10:51.415914 WORK_FSP = 0x0
3920 23:10:51.418741 WL = 0x2
3921 23:10:51.419153 RL = 0x2
3922 23:10:51.422290 BL = 0x2
3923 23:10:51.422797 RPST = 0x0
3924 23:10:51.425191 RD_PRE = 0x0
3925 23:10:51.425608 WR_PRE = 0x1
3926 23:10:51.428661 WR_PST = 0x0
3927 23:10:51.429078 DBI_WR = 0x0
3928 23:10:51.431744 DBI_RD = 0x0
3929 23:10:51.432162 OTF = 0x1
3930 23:10:51.435215 ===================================
3931 23:10:51.441403 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3932 23:10:51.445851 nWR fixed to 30
3933 23:10:51.449220 [ModeRegInit_LP4] CH0 RK0
3934 23:10:51.449636 [ModeRegInit_LP4] CH0 RK1
3935 23:10:51.453050 [ModeRegInit_LP4] CH1 RK0
3936 23:10:51.456261 [ModeRegInit_LP4] CH1 RK1
3937 23:10:51.456677 match AC timing 17
3938 23:10:51.462752 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3939 23:10:51.466581 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3940 23:10:51.469776 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3941 23:10:51.476158 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3942 23:10:51.479452 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3943 23:10:51.479874 ==
3944 23:10:51.482369 Dram Type= 6, Freq= 0, CH_0, rank 0
3945 23:10:51.486092 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3946 23:10:51.486597 ==
3947 23:10:51.492413 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3948 23:10:51.498988 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3949 23:10:51.502424 [CA 0] Center 36 (6~67) winsize 62
3950 23:10:51.505742 [CA 1] Center 36 (6~67) winsize 62
3951 23:10:51.508636 [CA 2] Center 34 (4~65) winsize 62
3952 23:10:51.512128 [CA 3] Center 34 (4~65) winsize 62
3953 23:10:51.515975 [CA 4] Center 33 (3~64) winsize 62
3954 23:10:51.518854 [CA 5] Center 33 (3~64) winsize 62
3955 23:10:51.519271
3956 23:10:51.522733 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3957 23:10:51.523230
3958 23:10:51.525309 [CATrainingPosCal] consider 1 rank data
3959 23:10:51.528706 u2DelayCellTimex100 = 270/100 ps
3960 23:10:51.532139 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3961 23:10:51.535189 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3962 23:10:51.539047 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3963 23:10:51.545034 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3964 23:10:51.548447 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3965 23:10:51.551540 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3966 23:10:51.552043
3967 23:10:51.554920 CA PerBit enable=1, Macro0, CA PI delay=33
3968 23:10:51.555335
3969 23:10:51.558183 [CBTSetCACLKResult] CA Dly = 33
3970 23:10:51.558687 CS Dly: 4 (0~35)
3971 23:10:51.559032 ==
3972 23:10:51.561950 Dram Type= 6, Freq= 0, CH_0, rank 1
3973 23:10:51.568189 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3974 23:10:51.568703 ==
3975 23:10:51.571554 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3976 23:10:51.578447 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3977 23:10:51.581933 [CA 0] Center 36 (6~67) winsize 62
3978 23:10:51.585547 [CA 1] Center 36 (6~67) winsize 62
3979 23:10:51.587874 [CA 2] Center 35 (4~66) winsize 63
3980 23:10:51.591499 [CA 3] Center 35 (4~66) winsize 63
3981 23:10:51.594568 [CA 4] Center 34 (4~65) winsize 62
3982 23:10:51.598459 [CA 5] Center 34 (3~65) winsize 63
3983 23:10:51.598984
3984 23:10:51.601339 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3985 23:10:51.601844
3986 23:10:51.604762 [CATrainingPosCal] consider 2 rank data
3987 23:10:51.607768 u2DelayCellTimex100 = 270/100 ps
3988 23:10:51.611068 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3989 23:10:51.617527 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3990 23:10:51.621213 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3991 23:10:51.624393 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3992 23:10:51.627893 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
3993 23:10:51.631132 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3994 23:10:51.631669
3995 23:10:51.634127 CA PerBit enable=1, Macro0, CA PI delay=33
3996 23:10:51.634542
3997 23:10:51.637377 [CBTSetCACLKResult] CA Dly = 33
3998 23:10:51.641665 CS Dly: 4 (0~36)
3999 23:10:51.642078
4000 23:10:51.643847 ----->DramcWriteLeveling(PI) begin...
4001 23:10:51.644263 ==
4002 23:10:51.647479 Dram Type= 6, Freq= 0, CH_0, rank 0
4003 23:10:51.651136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4004 23:10:51.651684 ==
4005 23:10:51.654373 Write leveling (Byte 0): 32 => 32
4006 23:10:51.656842 Write leveling (Byte 1): 31 => 31
4007 23:10:51.660231 DramcWriteLeveling(PI) end<-----
4008 23:10:51.660642
4009 23:10:51.660966 ==
4010 23:10:51.663894 Dram Type= 6, Freq= 0, CH_0, rank 0
4011 23:10:51.666991 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4012 23:10:51.667683 ==
4013 23:10:51.670198 [Gating] SW mode calibration
4014 23:10:51.677207 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4015 23:10:51.683192 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4016 23:10:51.686803 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4017 23:10:51.693381 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4018 23:10:51.696245 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4019 23:10:51.699986 0 9 12 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
4020 23:10:51.706550 0 9 16 | B1->B0 | 2f2f 2727 | 0 0 | (1 1) (0 0)
4021 23:10:51.710258 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4022 23:10:51.713038 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4023 23:10:51.719225 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4024 23:10:51.722684 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4025 23:10:51.726132 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4026 23:10:51.732656 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4027 23:10:51.736026 0 10 12 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
4028 23:10:51.739830 0 10 16 | B1->B0 | 3939 4242 | 1 0 | (0 0) (0 0)
4029 23:10:51.746030 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4030 23:10:51.749062 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4031 23:10:51.752439 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4032 23:10:51.759024 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4033 23:10:51.762546 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4034 23:10:51.765473 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4035 23:10:51.771959 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4036 23:10:51.775054 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4037 23:10:51.778561 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4038 23:10:51.784836 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4039 23:10:51.788241 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4040 23:10:51.791465 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4041 23:10:51.798268 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4042 23:10:51.801685 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4043 23:10:51.804809 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4044 23:10:51.811315 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4045 23:10:51.814611 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4046 23:10:51.818217 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4047 23:10:51.824692 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4048 23:10:51.828114 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4049 23:10:51.831261 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4050 23:10:51.837712 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4051 23:10:51.840944 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4052 23:10:51.844147 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4053 23:10:51.847956 Total UI for P1: 0, mck2ui 16
4054 23:10:51.851752 best dqsien dly found for B0: ( 0, 13, 12)
4055 23:10:51.857832 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4056 23:10:51.858340 Total UI for P1: 0, mck2ui 16
4057 23:10:51.864046 best dqsien dly found for B1: ( 0, 13, 18)
4058 23:10:51.867435 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4059 23:10:51.871408 best DQS1 dly(MCK, UI, PI) = (0, 13, 18)
4060 23:10:51.871967
4061 23:10:51.873630 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4062 23:10:51.877349 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)
4063 23:10:51.880226 [Gating] SW calibration Done
4064 23:10:51.880683 ==
4065 23:10:51.883659 Dram Type= 6, Freq= 0, CH_0, rank 0
4066 23:10:51.887246 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4067 23:10:51.887811 ==
4068 23:10:51.890245 RX Vref Scan: 0
4069 23:10:51.890754
4070 23:10:51.893320 RX Vref 0 -> 0, step: 1
4071 23:10:51.893734
4072 23:10:51.894059 RX Delay -230 -> 252, step: 16
4073 23:10:51.900565 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4074 23:10:51.903677 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4075 23:10:51.906589 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4076 23:10:51.910220 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4077 23:10:51.916465 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4078 23:10:51.919970 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4079 23:10:51.923232 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4080 23:10:51.926502 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4081 23:10:51.933233 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4082 23:10:51.936345 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4083 23:10:51.939806 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4084 23:10:51.942911 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4085 23:10:51.949688 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4086 23:10:51.952993 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4087 23:10:51.956087 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4088 23:10:51.960079 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4089 23:10:51.960590 ==
4090 23:10:51.962480 Dram Type= 6, Freq= 0, CH_0, rank 0
4091 23:10:51.970591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4092 23:10:51.971140 ==
4093 23:10:51.971534 DQS Delay:
4094 23:10:51.972253 DQS0 = 0, DQS1 = 0
4095 23:10:51.972599 DQM Delay:
4096 23:10:51.972894 DQM0 = 42, DQM1 = 35
4097 23:10:51.975752 DQ Delay:
4098 23:10:51.978980 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4099 23:10:51.982222 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4100 23:10:51.985928 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4101 23:10:51.988977 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4102 23:10:51.989392
4103 23:10:51.989721
4104 23:10:51.990024 ==
4105 23:10:51.992249 Dram Type= 6, Freq= 0, CH_0, rank 0
4106 23:10:51.995729 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4107 23:10:51.996383 ==
4108 23:10:51.996999
4109 23:10:51.997470
4110 23:10:51.999348 TX Vref Scan disable
4111 23:10:52.002009 == TX Byte 0 ==
4112 23:10:52.005258 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4113 23:10:52.008899 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4114 23:10:52.011710 == TX Byte 1 ==
4115 23:10:52.015546 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4116 23:10:52.018081 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4117 23:10:52.018318 ==
4118 23:10:52.021874 Dram Type= 6, Freq= 0, CH_0, rank 0
4119 23:10:52.028313 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4120 23:10:52.028443 ==
4121 23:10:52.028545
4122 23:10:52.028640
4123 23:10:52.028730 TX Vref Scan disable
4124 23:10:52.032630 == TX Byte 0 ==
4125 23:10:52.035498 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4126 23:10:52.042475 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4127 23:10:52.042565 == TX Byte 1 ==
4128 23:10:52.045544 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4129 23:10:52.052215 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4130 23:10:52.052306
4131 23:10:52.052378 [DATLAT]
4132 23:10:52.052445 Freq=600, CH0 RK0
4133 23:10:52.052509
4134 23:10:52.055247 DATLAT Default: 0x9
4135 23:10:52.055337 0, 0xFFFF, sum = 0
4136 23:10:52.058830 1, 0xFFFF, sum = 0
4137 23:10:52.062008 2, 0xFFFF, sum = 0
4138 23:10:52.062101 3, 0xFFFF, sum = 0
4139 23:10:52.065124 4, 0xFFFF, sum = 0
4140 23:10:52.065216 5, 0xFFFF, sum = 0
4141 23:10:52.068527 6, 0xFFFF, sum = 0
4142 23:10:52.068618 7, 0xFFFF, sum = 0
4143 23:10:52.071848 8, 0x0, sum = 1
4144 23:10:52.071940 9, 0x0, sum = 2
4145 23:10:52.072013 10, 0x0, sum = 3
4146 23:10:52.075335 11, 0x0, sum = 4
4147 23:10:52.075441 best_step = 9
4148 23:10:52.075513
4149 23:10:52.075580 ==
4150 23:10:52.078717 Dram Type= 6, Freq= 0, CH_0, rank 0
4151 23:10:52.085048 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4152 23:10:52.085142 ==
4153 23:10:52.085214 RX Vref Scan: 1
4154 23:10:52.085280
4155 23:10:52.088383 RX Vref 0 -> 0, step: 1
4156 23:10:52.088473
4157 23:10:52.091585 RX Delay -179 -> 252, step: 8
4158 23:10:52.091675
4159 23:10:52.095045 Set Vref, RX VrefLevel [Byte0]: 51
4160 23:10:52.098220 [Byte1]: 48
4161 23:10:52.098311
4162 23:10:52.101727 Final RX Vref Byte 0 = 51 to rank0
4163 23:10:52.104735 Final RX Vref Byte 1 = 48 to rank0
4164 23:10:52.107974 Final RX Vref Byte 0 = 51 to rank1
4165 23:10:52.111865 Final RX Vref Byte 1 = 48 to rank1==
4166 23:10:52.114662 Dram Type= 6, Freq= 0, CH_0, rank 0
4167 23:10:52.117726 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4168 23:10:52.121857 ==
4169 23:10:52.121947 DQS Delay:
4170 23:10:52.122018 DQS0 = 0, DQS1 = 0
4171 23:10:52.125231 DQM Delay:
4172 23:10:52.125642 DQM0 = 40, DQM1 = 33
4173 23:10:52.128118 DQ Delay:
4174 23:10:52.131634 DQ0 =44, DQ1 =40, DQ2 =36, DQ3 =36
4175 23:10:52.132046 DQ4 =40, DQ5 =32, DQ6 =48, DQ7 =48
4176 23:10:52.134529 DQ8 =24, DQ9 =20, DQ10 =32, DQ11 =28
4177 23:10:52.141317 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =40
4178 23:10:52.141730
4179 23:10:52.142062
4180 23:10:52.148220 [DQSOSCAuto] RK0, (LSB)MR18= 0x4b42, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 395 ps
4181 23:10:52.150958 CH0 RK0: MR19=808, MR18=4B42
4182 23:10:52.158300 CH0_RK0: MR19=0x808, MR18=0x4B42, DQSOSC=395, MR23=63, INC=168, DEC=112
4183 23:10:52.158558
4184 23:10:52.160739 ----->DramcWriteLeveling(PI) begin...
4185 23:10:52.160922 ==
4186 23:10:52.164747 Dram Type= 6, Freq= 0, CH_0, rank 1
4187 23:10:52.167642 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4188 23:10:52.167794 ==
4189 23:10:52.170827 Write leveling (Byte 0): 33 => 33
4190 23:10:52.173949 Write leveling (Byte 1): 29 => 29
4191 23:10:52.177406 DramcWriteLeveling(PI) end<-----
4192 23:10:52.177519
4193 23:10:52.177609 ==
4194 23:10:52.180837 Dram Type= 6, Freq= 0, CH_0, rank 1
4195 23:10:52.183800 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4196 23:10:52.183919 ==
4197 23:10:52.187924 [Gating] SW mode calibration
4198 23:10:52.193963 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4199 23:10:52.200332 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4200 23:10:52.203771 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4201 23:10:52.210757 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4202 23:10:52.213769 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4203 23:10:52.217044 0 9 12 | B1->B0 | 3434 3030 | 0 1 | (0 0) (1 1)
4204 23:10:52.223617 0 9 16 | B1->B0 | 2b2b 2323 | 0 0 | (1 1) (0 0)
4205 23:10:52.226833 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4206 23:10:52.230179 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4207 23:10:52.236926 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4208 23:10:52.240687 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4209 23:10:52.243449 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4210 23:10:52.250273 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4211 23:10:52.254107 0 10 12 | B1->B0 | 2828 3434 | 0 0 | (0 0) (0 0)
4212 23:10:52.256801 0 10 16 | B1->B0 | 3b3b 4545 | 1 0 | (0 0) (0 0)
4213 23:10:52.263226 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4214 23:10:52.266733 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4215 23:10:52.269899 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4216 23:10:52.277392 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4217 23:10:52.279830 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4218 23:10:52.283913 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4219 23:10:52.289557 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4220 23:10:52.293214 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4221 23:10:52.296235 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4222 23:10:52.302644 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4223 23:10:52.307184 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4224 23:10:52.309932 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4225 23:10:52.316186 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4226 23:10:52.319177 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4227 23:10:52.322638 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4228 23:10:52.329626 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4229 23:10:52.332883 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4230 23:10:52.335955 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4231 23:10:52.342885 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4232 23:10:52.346415 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4233 23:10:52.349851 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4234 23:10:52.356030 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4235 23:10:52.359467 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4236 23:10:52.362173 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4237 23:10:52.366312 Total UI for P1: 0, mck2ui 16
4238 23:10:52.369073 best dqsien dly found for B0: ( 0, 13, 12)
4239 23:10:52.372433 Total UI for P1: 0, mck2ui 16
4240 23:10:52.375254 best dqsien dly found for B1: ( 0, 13, 14)
4241 23:10:52.378490 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4242 23:10:52.382092 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4243 23:10:52.382702
4244 23:10:52.389665 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4245 23:10:52.392212 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4246 23:10:52.395198 [Gating] SW calibration Done
4247 23:10:52.395648 ==
4248 23:10:52.398779 Dram Type= 6, Freq= 0, CH_0, rank 1
4249 23:10:52.401463 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4250 23:10:52.401887 ==
4251 23:10:52.402218 RX Vref Scan: 0
4252 23:10:52.405257
4253 23:10:52.405764 RX Vref 0 -> 0, step: 1
4254 23:10:52.406157
4255 23:10:52.408078 RX Delay -230 -> 252, step: 16
4256 23:10:52.411445 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4257 23:10:52.418158 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4258 23:10:52.421453 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4259 23:10:52.425859 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4260 23:10:52.428539 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4261 23:10:52.431962 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4262 23:10:52.438566 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4263 23:10:52.441934 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4264 23:10:52.444740 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4265 23:10:52.448016 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4266 23:10:52.454755 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4267 23:10:52.457980 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4268 23:10:52.461392 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4269 23:10:52.464544 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4270 23:10:52.471024 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4271 23:10:52.474133 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4272 23:10:52.474688 ==
4273 23:10:52.477375 Dram Type= 6, Freq= 0, CH_0, rank 1
4274 23:10:52.481053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4275 23:10:52.481519 ==
4276 23:10:52.483866 DQS Delay:
4277 23:10:52.484281 DQS0 = 0, DQS1 = 0
4278 23:10:52.487221 DQM Delay:
4279 23:10:52.487671 DQM0 = 41, DQM1 = 34
4280 23:10:52.488004 DQ Delay:
4281 23:10:52.490418 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =41
4282 23:10:52.493617 DQ4 =41, DQ5 =25, DQ6 =57, DQ7 =49
4283 23:10:52.497234 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =25
4284 23:10:52.500387 DQ12 =33, DQ13 =41, DQ14 =49, DQ15 =41
4285 23:10:52.500935
4286 23:10:52.501268
4287 23:10:52.504065 ==
4288 23:10:52.507025 Dram Type= 6, Freq= 0, CH_0, rank 1
4289 23:10:52.510242 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4290 23:10:52.510657 ==
4291 23:10:52.510986
4292 23:10:52.511291
4293 23:10:52.513463 TX Vref Scan disable
4294 23:10:52.513875 == TX Byte 0 ==
4295 23:10:52.520242 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4296 23:10:52.523720 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4297 23:10:52.524135 == TX Byte 1 ==
4298 23:10:52.529935 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4299 23:10:52.533515 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4300 23:10:52.534033 ==
4301 23:10:52.536596 Dram Type= 6, Freq= 0, CH_0, rank 1
4302 23:10:52.540778 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4303 23:10:52.541297 ==
4304 23:10:52.541629
4305 23:10:52.541932
4306 23:10:52.543314 TX Vref Scan disable
4307 23:10:52.546346 == TX Byte 0 ==
4308 23:10:52.549693 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4309 23:10:52.556517 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4310 23:10:52.557038 == TX Byte 1 ==
4311 23:10:52.559798 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4312 23:10:52.566590 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4313 23:10:52.567107
4314 23:10:52.567473 [DATLAT]
4315 23:10:52.567783 Freq=600, CH0 RK1
4316 23:10:52.568076
4317 23:10:52.569507 DATLAT Default: 0x9
4318 23:10:52.569924 0, 0xFFFF, sum = 0
4319 23:10:52.573162 1, 0xFFFF, sum = 0
4320 23:10:52.576183 2, 0xFFFF, sum = 0
4321 23:10:52.576699 3, 0xFFFF, sum = 0
4322 23:10:52.579426 4, 0xFFFF, sum = 0
4323 23:10:52.579852 5, 0xFFFF, sum = 0
4324 23:10:52.582914 6, 0xFFFF, sum = 0
4325 23:10:52.583480 7, 0xFFFF, sum = 0
4326 23:10:52.586706 8, 0x0, sum = 1
4327 23:10:52.587233 9, 0x0, sum = 2
4328 23:10:52.589178 10, 0x0, sum = 3
4329 23:10:52.589602 11, 0x0, sum = 4
4330 23:10:52.589939 best_step = 9
4331 23:10:52.590248
4332 23:10:52.592871 ==
4333 23:10:52.593381 Dram Type= 6, Freq= 0, CH_0, rank 1
4334 23:10:52.600242 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4335 23:10:52.600753 ==
4336 23:10:52.601087 RX Vref Scan: 0
4337 23:10:52.601395
4338 23:10:52.602403 RX Vref 0 -> 0, step: 1
4339 23:10:52.602822
4340 23:10:52.605946 RX Delay -179 -> 252, step: 8
4341 23:10:52.612394 iDelay=197, Bit 0, Center 40 (-107 ~ 188) 296
4342 23:10:52.615430 iDelay=197, Bit 1, Center 44 (-107 ~ 196) 304
4343 23:10:52.618753 iDelay=197, Bit 2, Center 36 (-115 ~ 188) 304
4344 23:10:52.622443 iDelay=197, Bit 3, Center 40 (-107 ~ 188) 296
4345 23:10:52.625948 iDelay=197, Bit 4, Center 44 (-107 ~ 196) 304
4346 23:10:52.632277 iDelay=197, Bit 5, Center 28 (-123 ~ 180) 304
4347 23:10:52.635727 iDelay=197, Bit 6, Center 48 (-99 ~ 196) 296
4348 23:10:52.639305 iDelay=197, Bit 7, Center 48 (-99 ~ 196) 296
4349 23:10:52.642621 iDelay=197, Bit 8, Center 24 (-131 ~ 180) 312
4350 23:10:52.648715 iDelay=197, Bit 9, Center 16 (-139 ~ 172) 312
4351 23:10:52.651698 iDelay=197, Bit 10, Center 32 (-123 ~ 188) 312
4352 23:10:52.655267 iDelay=197, Bit 11, Center 28 (-123 ~ 180) 304
4353 23:10:52.658478 iDelay=197, Bit 12, Center 40 (-115 ~ 196) 312
4354 23:10:52.666304 iDelay=197, Bit 13, Center 36 (-115 ~ 188) 304
4355 23:10:52.671155 iDelay=197, Bit 14, Center 44 (-107 ~ 196) 304
4356 23:10:52.671610 iDelay=197, Bit 15, Center 40 (-115 ~ 196) 312
4357 23:10:52.671944 ==
4358 23:10:52.674692 Dram Type= 6, Freq= 0, CH_0, rank 1
4359 23:10:52.678241 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4360 23:10:52.678658 ==
4361 23:10:52.681403 DQS Delay:
4362 23:10:52.681812 DQS0 = 0, DQS1 = 0
4363 23:10:52.685063 DQM Delay:
4364 23:10:52.685478 DQM0 = 41, DQM1 = 32
4365 23:10:52.687769 DQ Delay:
4366 23:10:52.688180 DQ0 =40, DQ1 =44, DQ2 =36, DQ3 =40
4367 23:10:52.691041 DQ4 =44, DQ5 =28, DQ6 =48, DQ7 =48
4368 23:10:52.695229 DQ8 =24, DQ9 =16, DQ10 =32, DQ11 =28
4369 23:10:52.697693 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =40
4370 23:10:52.698108
4371 23:10:52.701560
4372 23:10:52.708091 [DQSOSCAuto] RK1, (LSB)MR18= 0x423c, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 397 ps
4373 23:10:52.711417 CH0 RK1: MR19=808, MR18=423C
4374 23:10:52.718293 CH0_RK1: MR19=0x808, MR18=0x423C, DQSOSC=397, MR23=63, INC=166, DEC=110
4375 23:10:52.720807 [RxdqsGatingPostProcess] freq 600
4376 23:10:52.724325 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4377 23:10:52.727401 Pre-setting of DQS Precalculation
4378 23:10:52.733903 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4379 23:10:52.734411 ==
4380 23:10:52.737789 Dram Type= 6, Freq= 0, CH_1, rank 0
4381 23:10:52.740854 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4382 23:10:52.741278 ==
4383 23:10:52.748069 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4384 23:10:52.750769 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4385 23:10:52.755942 [CA 0] Center 36 (6~66) winsize 61
4386 23:10:52.758463 [CA 1] Center 35 (5~66) winsize 62
4387 23:10:52.761843 [CA 2] Center 34 (4~65) winsize 62
4388 23:10:52.765754 [CA 3] Center 34 (4~65) winsize 62
4389 23:10:52.768508 [CA 4] Center 34 (4~65) winsize 62
4390 23:10:52.771735 [CA 5] Center 34 (3~65) winsize 63
4391 23:10:52.772240
4392 23:10:52.775148 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4393 23:10:52.775825
4394 23:10:52.778226 [CATrainingPosCal] consider 1 rank data
4395 23:10:52.781912 u2DelayCellTimex100 = 270/100 ps
4396 23:10:52.784779 CA0 delay=36 (6~66),Diff = 2 PI (19 cell)
4397 23:10:52.791792 CA1 delay=35 (5~66),Diff = 1 PI (9 cell)
4398 23:10:52.795235 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4399 23:10:52.798178 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4400 23:10:52.801646 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4401 23:10:52.805185 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4402 23:10:52.805690
4403 23:10:52.808662 CA PerBit enable=1, Macro0, CA PI delay=34
4404 23:10:52.809078
4405 23:10:52.811674 [CBTSetCACLKResult] CA Dly = 34
4406 23:10:52.815475 CS Dly: 4 (0~35)
4407 23:10:52.815979 ==
4408 23:10:52.819222 Dram Type= 6, Freq= 0, CH_1, rank 1
4409 23:10:52.821556 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4410 23:10:52.821973 ==
4411 23:10:52.827992 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4412 23:10:52.831604 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4413 23:10:52.835498 [CA 0] Center 35 (5~66) winsize 62
4414 23:10:52.838955 [CA 1] Center 36 (6~66) winsize 61
4415 23:10:52.841918 [CA 2] Center 34 (4~65) winsize 62
4416 23:10:52.845292 [CA 3] Center 34 (3~65) winsize 63
4417 23:10:52.848226 [CA 4] Center 34 (4~65) winsize 62
4418 23:10:52.852162 [CA 5] Center 34 (3~65) winsize 63
4419 23:10:52.852581
4420 23:10:52.854694 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4421 23:10:52.855133
4422 23:10:52.858082 [CATrainingPosCal] consider 2 rank data
4423 23:10:52.862071 u2DelayCellTimex100 = 270/100 ps
4424 23:10:52.865119 CA0 delay=36 (6~66),Diff = 2 PI (19 cell)
4425 23:10:52.871535 CA1 delay=36 (6~66),Diff = 2 PI (19 cell)
4426 23:10:52.874782 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4427 23:10:52.877662 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4428 23:10:52.881465 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4429 23:10:52.884565 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4430 23:10:52.885073
4431 23:10:52.887659 CA PerBit enable=1, Macro0, CA PI delay=34
4432 23:10:52.888087
4433 23:10:52.891354 [CBTSetCACLKResult] CA Dly = 34
4434 23:10:52.893946 CS Dly: 4 (0~36)
4435 23:10:52.894359
4436 23:10:52.897795 ----->DramcWriteLeveling(PI) begin...
4437 23:10:52.898321 ==
4438 23:10:52.900973 Dram Type= 6, Freq= 0, CH_1, rank 0
4439 23:10:52.903976 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4440 23:10:52.904400 ==
4441 23:10:52.907718 Write leveling (Byte 0): 28 => 28
4442 23:10:52.911137 Write leveling (Byte 1): 29 => 29
4443 23:10:52.914838 DramcWriteLeveling(PI) end<-----
4444 23:10:52.915346
4445 23:10:52.915737 ==
4446 23:10:52.917945 Dram Type= 6, Freq= 0, CH_1, rank 0
4447 23:10:52.920678 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4448 23:10:52.921209 ==
4449 23:10:52.923898 [Gating] SW mode calibration
4450 23:10:52.931330 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4451 23:10:52.937097 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4452 23:10:52.941603 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4453 23:10:52.943919 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4454 23:10:52.950532 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4455 23:10:52.953761 0 9 12 | B1->B0 | 3232 3030 | 1 1 | (1 0) (1 1)
4456 23:10:52.956771 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4457 23:10:52.963586 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4458 23:10:52.967866 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4459 23:10:52.970733 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4460 23:10:52.976882 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4461 23:10:52.979827 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4462 23:10:52.983395 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4463 23:10:52.989716 0 10 12 | B1->B0 | 2929 3333 | 0 1 | (0 0) (0 0)
4464 23:10:52.993072 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4465 23:10:52.999517 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4466 23:10:53.003453 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4467 23:10:53.006173 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4468 23:10:53.013010 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4469 23:10:53.016203 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4470 23:10:53.019649 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4471 23:10:53.025818 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4472 23:10:53.029056 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4473 23:10:53.032949 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4474 23:10:53.039301 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4475 23:10:53.042540 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4476 23:10:53.045631 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4477 23:10:53.052184 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4478 23:10:53.056563 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4479 23:10:53.059068 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4480 23:10:53.065393 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4481 23:10:53.068711 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4482 23:10:53.072127 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4483 23:10:53.079079 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4484 23:10:53.081981 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4485 23:10:53.085050 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4486 23:10:53.092681 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4487 23:10:53.094825 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4488 23:10:53.098233 Total UI for P1: 0, mck2ui 16
4489 23:10:53.101590 best dqsien dly found for B1: ( 0, 13, 10)
4490 23:10:53.105289 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4491 23:10:53.108352 Total UI for P1: 0, mck2ui 16
4492 23:10:53.111728 best dqsien dly found for B0: ( 0, 13, 12)
4493 23:10:53.114640 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4494 23:10:53.117948 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4495 23:10:53.118456
4496 23:10:53.125440 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4497 23:10:53.127537 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4498 23:10:53.131232 [Gating] SW calibration Done
4499 23:10:53.131687 ==
4500 23:10:53.134377 Dram Type= 6, Freq= 0, CH_1, rank 0
4501 23:10:53.137789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4502 23:10:53.138298 ==
4503 23:10:53.138634 RX Vref Scan: 0
4504 23:10:53.138941
4505 23:10:53.141322 RX Vref 0 -> 0, step: 1
4506 23:10:53.141737
4507 23:10:53.144130 RX Delay -230 -> 252, step: 16
4508 23:10:53.147857 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4509 23:10:53.154224 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4510 23:10:53.157191 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4511 23:10:53.161052 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4512 23:10:53.163892 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4513 23:10:53.167548 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4514 23:10:53.173819 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4515 23:10:53.177386 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4516 23:10:53.181272 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4517 23:10:53.183809 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4518 23:10:53.190085 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4519 23:10:53.194226 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4520 23:10:53.196989 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4521 23:10:53.201524 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4522 23:10:53.207101 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4523 23:10:53.210108 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4524 23:10:53.210530 ==
4525 23:10:53.213456 Dram Type= 6, Freq= 0, CH_1, rank 0
4526 23:10:53.216613 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4527 23:10:53.217031 ==
4528 23:10:53.220256 DQS Delay:
4529 23:10:53.220770 DQS0 = 0, DQS1 = 0
4530 23:10:53.221103 DQM Delay:
4531 23:10:53.223276 DQM0 = 43, DQM1 = 38
4532 23:10:53.223716 DQ Delay:
4533 23:10:53.226801 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =41
4534 23:10:53.230206 DQ4 =41, DQ5 =57, DQ6 =49, DQ7 =41
4535 23:10:53.233183 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4536 23:10:53.237306 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =41
4537 23:10:53.237813
4538 23:10:53.238145
4539 23:10:53.238451 ==
4540 23:10:53.239680 Dram Type= 6, Freq= 0, CH_1, rank 0
4541 23:10:53.247475 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4542 23:10:53.247979 ==
4543 23:10:53.248311
4544 23:10:53.248620
4545 23:10:53.248914 TX Vref Scan disable
4546 23:10:53.250709 == TX Byte 0 ==
4547 23:10:53.253738 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4548 23:10:53.260178 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4549 23:10:53.260688 == TX Byte 1 ==
4550 23:10:53.263542 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4551 23:10:53.270348 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4552 23:10:53.270877 ==
4553 23:10:53.273999 Dram Type= 6, Freq= 0, CH_1, rank 0
4554 23:10:53.276722 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4555 23:10:53.277140 ==
4556 23:10:53.277468
4557 23:10:53.277771
4558 23:10:53.280308 TX Vref Scan disable
4559 23:10:53.283327 == TX Byte 0 ==
4560 23:10:53.286763 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4561 23:10:53.290285 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4562 23:10:53.293587 == TX Byte 1 ==
4563 23:10:53.296592 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4564 23:10:53.299963 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4565 23:10:53.300587
4566 23:10:53.300928 [DATLAT]
4567 23:10:53.303232 Freq=600, CH1 RK0
4568 23:10:53.303691
4569 23:10:53.306131 DATLAT Default: 0x9
4570 23:10:53.306547 0, 0xFFFF, sum = 0
4571 23:10:53.309957 1, 0xFFFF, sum = 0
4572 23:10:53.310380 2, 0xFFFF, sum = 0
4573 23:10:53.313948 3, 0xFFFF, sum = 0
4574 23:10:53.314462 4, 0xFFFF, sum = 0
4575 23:10:53.316468 5, 0xFFFF, sum = 0
4576 23:10:53.316892 6, 0xFFFF, sum = 0
4577 23:10:53.319796 7, 0xFFFF, sum = 0
4578 23:10:53.320219 8, 0x0, sum = 1
4579 23:10:53.323454 9, 0x0, sum = 2
4580 23:10:53.323837 10, 0x0, sum = 3
4581 23:10:53.326318 11, 0x0, sum = 4
4582 23:10:53.326741 best_step = 9
4583 23:10:53.327069
4584 23:10:53.327403 ==
4585 23:10:53.329655 Dram Type= 6, Freq= 0, CH_1, rank 0
4586 23:10:53.332738 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4587 23:10:53.333164 ==
4588 23:10:53.336019 RX Vref Scan: 1
4589 23:10:53.336435
4590 23:10:53.340110 RX Vref 0 -> 0, step: 1
4591 23:10:53.340621
4592 23:10:53.340950 RX Delay -179 -> 252, step: 8
4593 23:10:53.342759
4594 23:10:53.343264 Set Vref, RX VrefLevel [Byte0]: 51
4595 23:10:53.345842 [Byte1]: 48
4596 23:10:53.351336
4597 23:10:53.351884 Final RX Vref Byte 0 = 51 to rank0
4598 23:10:53.354590 Final RX Vref Byte 1 = 48 to rank0
4599 23:10:53.357610 Final RX Vref Byte 0 = 51 to rank1
4600 23:10:53.360390 Final RX Vref Byte 1 = 48 to rank1==
4601 23:10:53.363876 Dram Type= 6, Freq= 0, CH_1, rank 0
4602 23:10:53.370521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4603 23:10:53.371119 ==
4604 23:10:53.371626 DQS Delay:
4605 23:10:53.374467 DQS0 = 0, DQS1 = 0
4606 23:10:53.374882 DQM Delay:
4607 23:10:53.375212 DQM0 = 42, DQM1 = 35
4608 23:10:53.377078 DQ Delay:
4609 23:10:53.379966 DQ0 =48, DQ1 =40, DQ2 =32, DQ3 =44
4610 23:10:53.383359 DQ4 =36, DQ5 =48, DQ6 =52, DQ7 =36
4611 23:10:53.386562 DQ8 =20, DQ9 =24, DQ10 =36, DQ11 =28
4612 23:10:53.390341 DQ12 =44, DQ13 =44, DQ14 =44, DQ15 =44
4613 23:10:53.390782
4614 23:10:53.391117
4615 23:10:53.396578 [DQSOSCAuto] RK0, (LSB)MR18= 0x2a44, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 401 ps
4616 23:10:53.399531 CH1 RK0: MR19=808, MR18=2A44
4617 23:10:53.406306 CH1_RK0: MR19=0x808, MR18=0x2A44, DQSOSC=396, MR23=63, INC=167, DEC=111
4618 23:10:53.406802
4619 23:10:53.409695 ----->DramcWriteLeveling(PI) begin...
4620 23:10:53.410208 ==
4621 23:10:53.413202 Dram Type= 6, Freq= 0, CH_1, rank 1
4622 23:10:53.416199 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4623 23:10:53.420439 ==
4624 23:10:53.420955 Write leveling (Byte 0): 28 => 28
4625 23:10:53.422823 Write leveling (Byte 1): 29 => 29
4626 23:10:53.426303 DramcWriteLeveling(PI) end<-----
4627 23:10:53.426874
4628 23:10:53.427215 ==
4629 23:10:53.429790 Dram Type= 6, Freq= 0, CH_1, rank 1
4630 23:10:53.436230 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4631 23:10:53.436652 ==
4632 23:10:53.436984 [Gating] SW mode calibration
4633 23:10:53.445997 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4634 23:10:53.449513 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4635 23:10:53.452352 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4636 23:10:53.459127 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4637 23:10:53.462562 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4638 23:10:53.466130 0 9 12 | B1->B0 | 3030 2828 | 0 0 | (1 1) (0 0)
4639 23:10:53.472829 0 9 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4640 23:10:53.476127 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4641 23:10:53.479268 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4642 23:10:53.485478 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4643 23:10:53.488944 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4644 23:10:53.492127 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4645 23:10:53.499162 0 10 8 | B1->B0 | 2323 2827 | 0 1 | (0 0) (0 0)
4646 23:10:53.502470 0 10 12 | B1->B0 | 2a2a 4141 | 0 0 | (1 1) (0 0)
4647 23:10:53.506110 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4648 23:10:53.511905 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4649 23:10:53.516170 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4650 23:10:53.518698 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4651 23:10:53.524878 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4652 23:10:53.528820 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4653 23:10:53.535422 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4654 23:10:53.539425 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4655 23:10:53.541907 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4656 23:10:53.549153 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4657 23:10:53.551433 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4658 23:10:53.554727 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4659 23:10:53.561088 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4660 23:10:53.564797 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4661 23:10:53.568291 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4662 23:10:53.574329 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4663 23:10:53.577579 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4664 23:10:53.580808 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4665 23:10:53.587957 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4666 23:10:53.590661 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4667 23:10:53.594594 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4668 23:10:53.600815 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4669 23:10:53.604957 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4670 23:10:53.607087 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4671 23:10:53.610848 Total UI for P1: 0, mck2ui 16
4672 23:10:53.614211 best dqsien dly found for B0: ( 0, 13, 8)
4673 23:10:53.620701 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4674 23:10:53.621122 Total UI for P1: 0, mck2ui 16
4675 23:10:53.623857 best dqsien dly found for B1: ( 0, 13, 12)
4676 23:10:53.630178 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4677 23:10:53.633475 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4678 23:10:53.633895
4679 23:10:53.636655 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4680 23:10:53.640330 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4681 23:10:53.643667 [Gating] SW calibration Done
4682 23:10:53.644175 ==
4683 23:10:53.646853 Dram Type= 6, Freq= 0, CH_1, rank 1
4684 23:10:53.650108 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4685 23:10:53.650616 ==
4686 23:10:53.653784 RX Vref Scan: 0
4687 23:10:53.654206
4688 23:10:53.654627 RX Vref 0 -> 0, step: 1
4689 23:10:53.654949
4690 23:10:53.656956 RX Delay -230 -> 252, step: 16
4691 23:10:53.663089 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4692 23:10:53.666855 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4693 23:10:53.669643 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4694 23:10:53.673019 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4695 23:10:53.679493 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4696 23:10:53.682550 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4697 23:10:53.685772 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4698 23:10:53.689670 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4699 23:10:53.692459 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4700 23:10:53.699345 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4701 23:10:53.702490 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4702 23:10:53.705608 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4703 23:10:53.710342 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4704 23:10:53.715755 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4705 23:10:53.719098 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4706 23:10:53.722018 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4707 23:10:53.722558 ==
4708 23:10:53.725577 Dram Type= 6, Freq= 0, CH_1, rank 1
4709 23:10:53.731751 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4710 23:10:53.732171 ==
4711 23:10:53.732501 DQS Delay:
4712 23:10:53.735188 DQS0 = 0, DQS1 = 0
4713 23:10:53.735757 DQM Delay:
4714 23:10:53.736100 DQM0 = 44, DQM1 = 40
4715 23:10:53.738623 DQ Delay:
4716 23:10:53.742166 DQ0 =57, DQ1 =33, DQ2 =33, DQ3 =41
4717 23:10:53.745390 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =33
4718 23:10:53.748340 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4719 23:10:53.752043 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =57
4720 23:10:53.752549
4721 23:10:53.752879
4722 23:10:53.753190 ==
4723 23:10:53.755140 Dram Type= 6, Freq= 0, CH_1, rank 1
4724 23:10:53.758528 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4725 23:10:53.759040 ==
4726 23:10:53.759411
4727 23:10:53.759735
4728 23:10:53.761413 TX Vref Scan disable
4729 23:10:53.765409 == TX Byte 0 ==
4730 23:10:53.768006 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4731 23:10:53.771400 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4732 23:10:53.774827 == TX Byte 1 ==
4733 23:10:53.778013 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4734 23:10:53.781451 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4735 23:10:53.781960 ==
4736 23:10:53.784640 Dram Type= 6, Freq= 0, CH_1, rank 1
4737 23:10:53.790705 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4738 23:10:53.791199 ==
4739 23:10:53.791590
4740 23:10:53.791900
4741 23:10:53.792199 TX Vref Scan disable
4742 23:10:53.795072 == TX Byte 0 ==
4743 23:10:53.798431 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4744 23:10:53.805082 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4745 23:10:53.805597 == TX Byte 1 ==
4746 23:10:53.808646 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4747 23:10:53.815072 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4748 23:10:53.815631
4749 23:10:53.815967 [DATLAT]
4750 23:10:53.816279 Freq=600, CH1 RK1
4751 23:10:53.816576
4752 23:10:53.818109 DATLAT Default: 0x9
4753 23:10:53.822002 0, 0xFFFF, sum = 0
4754 23:10:53.822518 1, 0xFFFF, sum = 0
4755 23:10:53.824755 2, 0xFFFF, sum = 0
4756 23:10:53.825240 3, 0xFFFF, sum = 0
4757 23:10:53.828111 4, 0xFFFF, sum = 0
4758 23:10:53.828628 5, 0xFFFF, sum = 0
4759 23:10:53.831716 6, 0xFFFF, sum = 0
4760 23:10:53.832230 7, 0xFFFF, sum = 0
4761 23:10:53.835806 8, 0x0, sum = 1
4762 23:10:53.836224 9, 0x0, sum = 2
4763 23:10:53.837969 10, 0x0, sum = 3
4764 23:10:53.838481 11, 0x0, sum = 4
4765 23:10:53.838817 best_step = 9
4766 23:10:53.839122
4767 23:10:53.841468 ==
4768 23:10:53.844605 Dram Type= 6, Freq= 0, CH_1, rank 1
4769 23:10:53.848098 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4770 23:10:53.848613 ==
4771 23:10:53.848941 RX Vref Scan: 0
4772 23:10:53.849242
4773 23:10:53.850832 RX Vref 0 -> 0, step: 1
4774 23:10:53.851276
4775 23:10:53.854962 RX Delay -179 -> 252, step: 8
4776 23:10:53.860805 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4777 23:10:53.864359 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4778 23:10:53.867823 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4779 23:10:53.870990 iDelay=205, Bit 3, Center 36 (-123 ~ 196) 320
4780 23:10:53.877682 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4781 23:10:53.881072 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4782 23:10:53.884353 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4783 23:10:53.887157 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4784 23:10:53.891033 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4785 23:10:53.897506 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4786 23:10:53.900316 iDelay=205, Bit 10, Center 36 (-115 ~ 188) 304
4787 23:10:53.904230 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4788 23:10:53.907762 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4789 23:10:53.913744 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4790 23:10:53.916798 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4791 23:10:53.919911 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4792 23:10:53.920330 ==
4793 23:10:53.923322 Dram Type= 6, Freq= 0, CH_1, rank 1
4794 23:10:53.930479 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4795 23:10:53.930993 ==
4796 23:10:53.931327 DQS Delay:
4797 23:10:53.933110 DQS0 = 0, DQS1 = 0
4798 23:10:53.933526 DQM Delay:
4799 23:10:53.933920 DQM0 = 38, DQM1 = 35
4800 23:10:53.936305 DQ Delay:
4801 23:10:53.940309 DQ0 =40, DQ1 =36, DQ2 =28, DQ3 =36
4802 23:10:53.942866 DQ4 =36, DQ5 =48, DQ6 =48, DQ7 =32
4803 23:10:53.946166 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =28
4804 23:10:53.949654 DQ12 =44, DQ13 =40, DQ14 =40, DQ15 =44
4805 23:10:53.950162
4806 23:10:53.950494
4807 23:10:53.956538 [DQSOSCAuto] RK1, (LSB)MR18= 0x2f55, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 400 ps
4808 23:10:53.959881 CH1 RK1: MR19=808, MR18=2F55
4809 23:10:53.966275 CH1_RK1: MR19=0x808, MR18=0x2F55, DQSOSC=393, MR23=63, INC=169, DEC=113
4810 23:10:53.969582 [RxdqsGatingPostProcess] freq 600
4811 23:10:53.972726 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4812 23:10:53.976133 Pre-setting of DQS Precalculation
4813 23:10:53.983052 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4814 23:10:53.989614 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4815 23:10:53.995564 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4816 23:10:53.995989
4817 23:10:53.996322
4818 23:10:53.999207 [Calibration Summary] 1200 Mbps
4819 23:10:54.002851 CH 0, Rank 0
4820 23:10:54.003402 SW Impedance : PASS
4821 23:10:54.005704 DUTY Scan : NO K
4822 23:10:54.009011 ZQ Calibration : PASS
4823 23:10:54.009524 Jitter Meter : NO K
4824 23:10:54.012400 CBT Training : PASS
4825 23:10:54.012816 Write leveling : PASS
4826 23:10:54.015493 RX DQS gating : PASS
4827 23:10:54.019147 RX DQ/DQS(RDDQC) : PASS
4828 23:10:54.019618 TX DQ/DQS : PASS
4829 23:10:54.021932 RX DATLAT : PASS
4830 23:10:54.025379 RX DQ/DQS(Engine): PASS
4831 23:10:54.025886 TX OE : NO K
4832 23:10:54.029415 All Pass.
4833 23:10:54.029929
4834 23:10:54.030263 CH 0, Rank 1
4835 23:10:54.031671 SW Impedance : PASS
4836 23:10:54.032093 DUTY Scan : NO K
4837 23:10:54.035215 ZQ Calibration : PASS
4838 23:10:54.038570 Jitter Meter : NO K
4839 23:10:54.039080 CBT Training : PASS
4840 23:10:54.042139 Write leveling : PASS
4841 23:10:54.045346 RX DQS gating : PASS
4842 23:10:54.045856 RX DQ/DQS(RDDQC) : PASS
4843 23:10:54.048693 TX DQ/DQS : PASS
4844 23:10:54.051972 RX DATLAT : PASS
4845 23:10:54.052683 RX DQ/DQS(Engine): PASS
4846 23:10:54.055147 TX OE : NO K
4847 23:10:54.055776 All Pass.
4848 23:10:54.056118
4849 23:10:54.058428 CH 1, Rank 0
4850 23:10:54.058936 SW Impedance : PASS
4851 23:10:54.061666 DUTY Scan : NO K
4852 23:10:54.065241 ZQ Calibration : PASS
4853 23:10:54.065753 Jitter Meter : NO K
4854 23:10:54.068110 CBT Training : PASS
4855 23:10:54.071802 Write leveling : PASS
4856 23:10:54.072309 RX DQS gating : PASS
4857 23:10:54.074903 RX DQ/DQS(RDDQC) : PASS
4858 23:10:54.078346 TX DQ/DQS : PASS
4859 23:10:54.078934 RX DATLAT : PASS
4860 23:10:54.081726 RX DQ/DQS(Engine): PASS
4861 23:10:54.084537 TX OE : NO K
4862 23:10:54.084956 All Pass.
4863 23:10:54.085286
4864 23:10:54.085592 CH 1, Rank 1
4865 23:10:54.088046 SW Impedance : PASS
4866 23:10:54.091222 DUTY Scan : NO K
4867 23:10:54.091807 ZQ Calibration : PASS
4868 23:10:54.094440 Jitter Meter : NO K
4869 23:10:54.094858 CBT Training : PASS
4870 23:10:54.098144 Write leveling : PASS
4871 23:10:54.101275 RX DQS gating : PASS
4872 23:10:54.101695 RX DQ/DQS(RDDQC) : PASS
4873 23:10:54.104508 TX DQ/DQS : PASS
4874 23:10:54.107698 RX DATLAT : PASS
4875 23:10:54.108116 RX DQ/DQS(Engine): PASS
4876 23:10:54.111440 TX OE : NO K
4877 23:10:54.111957 All Pass.
4878 23:10:54.112291
4879 23:10:54.115786 DramC Write-DBI off
4880 23:10:54.117649 PER_BANK_REFRESH: Hybrid Mode
4881 23:10:54.118069 TX_TRACKING: ON
4882 23:10:54.128097 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4883 23:10:54.131143 [FAST_K] Save calibration result to emmc
4884 23:10:54.134277 dramc_set_vcore_voltage set vcore to 662500
4885 23:10:54.138960 Read voltage for 933, 3
4886 23:10:54.139501 Vio18 = 0
4887 23:10:54.139839 Vcore = 662500
4888 23:10:54.140548 Vdram = 0
4889 23:10:54.141031 Vddq = 0
4890 23:10:54.141397 Vmddr = 0
4891 23:10:54.147254 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4892 23:10:54.150989 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4893 23:10:54.153889 MEM_TYPE=3, freq_sel=17
4894 23:10:54.157444 sv_algorithm_assistance_LP4_1600
4895 23:10:54.160806 ============ PULL DRAM RESETB DOWN ============
4896 23:10:54.167697 ========== PULL DRAM RESETB DOWN end =========
4897 23:10:54.170181 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4898 23:10:54.173615 ===================================
4899 23:10:54.177903 LPDDR4 DRAM CONFIGURATION
4900 23:10:54.180372 ===================================
4901 23:10:54.180789 EX_ROW_EN[0] = 0x0
4902 23:10:54.184086 EX_ROW_EN[1] = 0x0
4903 23:10:54.184509 LP4Y_EN = 0x0
4904 23:10:54.186853 WORK_FSP = 0x0
4905 23:10:54.187268 WL = 0x3
4906 23:10:54.190473 RL = 0x3
4907 23:10:54.191023 BL = 0x2
4908 23:10:54.193683 RPST = 0x0
4909 23:10:54.196882 RD_PRE = 0x0
4910 23:10:54.197399 WR_PRE = 0x1
4911 23:10:54.200194 WR_PST = 0x0
4912 23:10:54.200612 DBI_WR = 0x0
4913 23:10:54.203459 DBI_RD = 0x0
4914 23:10:54.203877 OTF = 0x1
4915 23:10:54.207102 ===================================
4916 23:10:54.209788 ===================================
4917 23:10:54.213848 ANA top config
4918 23:10:54.216829 ===================================
4919 23:10:54.217342 DLL_ASYNC_EN = 0
4920 23:10:54.219826 ALL_SLAVE_EN = 1
4921 23:10:54.224020 NEW_RANK_MODE = 1
4922 23:10:54.227072 DLL_IDLE_MODE = 1
4923 23:10:54.227672 LP45_APHY_COMB_EN = 1
4924 23:10:54.229779 TX_ODT_DIS = 1
4925 23:10:54.234065 NEW_8X_MODE = 1
4926 23:10:54.236228 ===================================
4927 23:10:54.239824 ===================================
4928 23:10:54.243482 data_rate = 1866
4929 23:10:54.246294 CKR = 1
4930 23:10:54.249975 DQ_P2S_RATIO = 8
4931 23:10:54.252651 ===================================
4932 23:10:54.253071 CA_P2S_RATIO = 8
4933 23:10:54.256415 DQ_CA_OPEN = 0
4934 23:10:54.260052 DQ_SEMI_OPEN = 0
4935 23:10:54.263316 CA_SEMI_OPEN = 0
4936 23:10:54.266082 CA_FULL_RATE = 0
4937 23:10:54.269942 DQ_CKDIV4_EN = 1
4938 23:10:54.270360 CA_CKDIV4_EN = 1
4939 23:10:54.272883 CA_PREDIV_EN = 0
4940 23:10:54.276066 PH8_DLY = 0
4941 23:10:54.279267 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4942 23:10:54.282604 DQ_AAMCK_DIV = 4
4943 23:10:54.285931 CA_AAMCK_DIV = 4
4944 23:10:54.288715 CA_ADMCK_DIV = 4
4945 23:10:54.289135 DQ_TRACK_CA_EN = 0
4946 23:10:54.292096 CA_PICK = 933
4947 23:10:54.295205 CA_MCKIO = 933
4948 23:10:54.298886 MCKIO_SEMI = 0
4949 23:10:54.302555 PLL_FREQ = 3732
4950 23:10:54.305860 DQ_UI_PI_RATIO = 32
4951 23:10:54.308938 CA_UI_PI_RATIO = 0
4952 23:10:54.311993 ===================================
4953 23:10:54.315965 ===================================
4954 23:10:54.316387 memory_type:LPDDR4
4955 23:10:54.318590 GP_NUM : 10
4956 23:10:54.321990 SRAM_EN : 1
4957 23:10:54.322498 MD32_EN : 0
4958 23:10:54.325103 ===================================
4959 23:10:54.328853 [ANA_INIT] >>>>>>>>>>>>>>
4960 23:10:54.331731 <<<<<< [CONFIGURE PHASE]: ANA_TX
4961 23:10:54.334888 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4962 23:10:54.338256 ===================================
4963 23:10:54.342016 data_rate = 1866,PCW = 0X8f00
4964 23:10:54.344920 ===================================
4965 23:10:54.348546 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4966 23:10:54.351406 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4967 23:10:54.357786 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4968 23:10:54.361744 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4969 23:10:54.367967 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4970 23:10:54.371108 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4971 23:10:54.371673 [ANA_INIT] flow start
4972 23:10:54.374659 [ANA_INIT] PLL >>>>>>>>
4973 23:10:54.377651 [ANA_INIT] PLL <<<<<<<<
4974 23:10:54.378159 [ANA_INIT] MIDPI >>>>>>>>
4975 23:10:54.381012 [ANA_INIT] MIDPI <<<<<<<<
4976 23:10:54.384277 [ANA_INIT] DLL >>>>>>>>
4977 23:10:54.384696 [ANA_INIT] flow end
4978 23:10:54.390968 ============ LP4 DIFF to SE enter ============
4979 23:10:54.393824 ============ LP4 DIFF to SE exit ============
4980 23:10:54.397433 [ANA_INIT] <<<<<<<<<<<<<
4981 23:10:54.400971 [Flow] Enable top DCM control >>>>>
4982 23:10:54.404075 [Flow] Enable top DCM control <<<<<
4983 23:10:54.404492 Enable DLL master slave shuffle
4984 23:10:54.410507 ==============================================================
4985 23:10:54.413657 Gating Mode config
4986 23:10:54.417121 ==============================================================
4987 23:10:54.420085 Config description:
4988 23:10:54.430614 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4989 23:10:54.436695 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4990 23:10:54.440041 SELPH_MODE 0: By rank 1: By Phase
4991 23:10:54.446821 ==============================================================
4992 23:10:54.449711 GAT_TRACK_EN = 1
4993 23:10:54.453110 RX_GATING_MODE = 2
4994 23:10:54.456229 RX_GATING_TRACK_MODE = 2
4995 23:10:54.459893 SELPH_MODE = 1
4996 23:10:54.463577 PICG_EARLY_EN = 1
4997 23:10:54.466295 VALID_LAT_VALUE = 1
4998 23:10:54.469617 ==============================================================
4999 23:10:54.472433 Enter into Gating configuration >>>>
5000 23:10:54.475854 Exit from Gating configuration <<<<
5001 23:10:54.479447 Enter into DVFS_PRE_config >>>>>
5002 23:10:54.492108 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5003 23:10:54.492525 Exit from DVFS_PRE_config <<<<<
5004 23:10:54.495664 Enter into PICG configuration >>>>
5005 23:10:54.499159 Exit from PICG configuration <<<<
5006 23:10:54.502376 [RX_INPUT] configuration >>>>>
5007 23:10:54.505462 [RX_INPUT] configuration <<<<<
5008 23:10:54.512349 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5009 23:10:54.515359 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5010 23:10:54.522419 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5011 23:10:54.529491 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5012 23:10:54.535055 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5013 23:10:54.541873 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5014 23:10:54.545734 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5015 23:10:54.548872 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5016 23:10:54.555831 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5017 23:10:54.558607 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5018 23:10:54.561741 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5019 23:10:54.565475 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5020 23:10:54.568161 ===================================
5021 23:10:54.571636 LPDDR4 DRAM CONFIGURATION
5022 23:10:54.574502 ===================================
5023 23:10:54.578590 EX_ROW_EN[0] = 0x0
5024 23:10:54.579101 EX_ROW_EN[1] = 0x0
5025 23:10:54.581601 LP4Y_EN = 0x0
5026 23:10:54.582010 WORK_FSP = 0x0
5027 23:10:54.584556 WL = 0x3
5028 23:10:54.585109 RL = 0x3
5029 23:10:54.588271 BL = 0x2
5030 23:10:54.590993 RPST = 0x0
5031 23:10:54.591546 RD_PRE = 0x0
5032 23:10:54.594212 WR_PRE = 0x1
5033 23:10:54.594718 WR_PST = 0x0
5034 23:10:54.597436 DBI_WR = 0x0
5035 23:10:54.597843 DBI_RD = 0x0
5036 23:10:54.600733 OTF = 0x1
5037 23:10:54.604298 ===================================
5038 23:10:54.607401 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5039 23:10:54.611129 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5040 23:10:54.617548 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5041 23:10:54.620855 ===================================
5042 23:10:54.621368 LPDDR4 DRAM CONFIGURATION
5043 23:10:54.624047 ===================================
5044 23:10:54.627220 EX_ROW_EN[0] = 0x10
5045 23:10:54.627774 EX_ROW_EN[1] = 0x0
5046 23:10:54.630480 LP4Y_EN = 0x0
5047 23:10:54.634069 WORK_FSP = 0x0
5048 23:10:54.634477 WL = 0x3
5049 23:10:54.637172 RL = 0x3
5050 23:10:54.637680 BL = 0x2
5051 23:10:54.640613 RPST = 0x0
5052 23:10:54.641124 RD_PRE = 0x0
5053 23:10:54.644209 WR_PRE = 0x1
5054 23:10:54.644705 WR_PST = 0x0
5055 23:10:54.646979 DBI_WR = 0x0
5056 23:10:54.647551 DBI_RD = 0x0
5057 23:10:54.650150 OTF = 0x1
5058 23:10:54.653733 ===================================
5059 23:10:54.660490 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5060 23:10:54.663460 nWR fixed to 30
5061 23:10:54.663876 [ModeRegInit_LP4] CH0 RK0
5062 23:10:54.666650 [ModeRegInit_LP4] CH0 RK1
5063 23:10:54.670058 [ModeRegInit_LP4] CH1 RK0
5064 23:10:54.674333 [ModeRegInit_LP4] CH1 RK1
5065 23:10:54.674841 match AC timing 9
5066 23:10:54.676440 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5067 23:10:54.683519 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5068 23:10:54.686452 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5069 23:10:54.692758 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5070 23:10:54.696008 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5071 23:10:54.696421 ==
5072 23:10:54.699204 Dram Type= 6, Freq= 0, CH_0, rank 0
5073 23:10:54.702444 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5074 23:10:54.702862 ==
5075 23:10:54.709483 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5076 23:10:54.715956 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5077 23:10:54.720011 [CA 0] Center 37 (7~68) winsize 62
5078 23:10:54.722957 [CA 1] Center 37 (7~68) winsize 62
5079 23:10:54.725555 [CA 2] Center 34 (4~64) winsize 61
5080 23:10:54.728744 [CA 3] Center 34 (4~65) winsize 62
5081 23:10:54.732138 [CA 4] Center 33 (3~63) winsize 61
5082 23:10:54.735561 [CA 5] Center 32 (2~63) winsize 62
5083 23:10:54.735971
5084 23:10:54.739068 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5085 23:10:54.739523
5086 23:10:54.742797 [CATrainingPosCal] consider 1 rank data
5087 23:10:54.745817 u2DelayCellTimex100 = 270/100 ps
5088 23:10:54.748721 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5089 23:10:54.752153 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5090 23:10:54.755305 CA2 delay=34 (4~64),Diff = 2 PI (12 cell)
5091 23:10:54.759115 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5092 23:10:54.765435 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5093 23:10:54.768994 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5094 23:10:54.769502
5095 23:10:54.771993 CA PerBit enable=1, Macro0, CA PI delay=32
5096 23:10:54.772502
5097 23:10:54.775500 [CBTSetCACLKResult] CA Dly = 32
5098 23:10:54.776023 CS Dly: 5 (0~36)
5099 23:10:54.776356 ==
5100 23:10:54.779424 Dram Type= 6, Freq= 0, CH_0, rank 1
5101 23:10:54.785221 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5102 23:10:54.785792 ==
5103 23:10:54.788286 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5104 23:10:54.795160 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5105 23:10:54.798639 [CA 0] Center 38 (7~69) winsize 63
5106 23:10:54.801514 [CA 1] Center 37 (7~68) winsize 62
5107 23:10:54.805427 [CA 2] Center 35 (5~65) winsize 61
5108 23:10:54.808223 [CA 3] Center 34 (4~65) winsize 62
5109 23:10:54.811627 [CA 4] Center 33 (3~64) winsize 62
5110 23:10:54.814594 [CA 5] Center 32 (2~63) winsize 62
5111 23:10:54.815110
5112 23:10:54.817881 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5113 23:10:54.818391
5114 23:10:54.821388 [CATrainingPosCal] consider 2 rank data
5115 23:10:54.824395 u2DelayCellTimex100 = 270/100 ps
5116 23:10:54.827699 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5117 23:10:54.831010 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5118 23:10:54.837591 CA2 delay=34 (5~64),Diff = 2 PI (12 cell)
5119 23:10:54.840936 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5120 23:10:54.843982 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5121 23:10:54.848105 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5122 23:10:54.848521
5123 23:10:54.850847 CA PerBit enable=1, Macro0, CA PI delay=32
5124 23:10:54.851254
5125 23:10:54.853883 [CBTSetCACLKResult] CA Dly = 32
5126 23:10:54.857894 CS Dly: 6 (0~39)
5127 23:10:54.858404
5128 23:10:54.860732 ----->DramcWriteLeveling(PI) begin...
5129 23:10:54.861202 ==
5130 23:10:54.864012 Dram Type= 6, Freq= 0, CH_0, rank 0
5131 23:10:54.867661 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5132 23:10:54.868173 ==
5133 23:10:54.870867 Write leveling (Byte 0): 30 => 30
5134 23:10:54.874384 Write leveling (Byte 1): 28 => 28
5135 23:10:54.877221 DramcWriteLeveling(PI) end<-----
5136 23:10:54.877681
5137 23:10:54.878003 ==
5138 23:10:54.880920 Dram Type= 6, Freq= 0, CH_0, rank 0
5139 23:10:54.883955 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5140 23:10:54.884366 ==
5141 23:10:54.887437 [Gating] SW mode calibration
5142 23:10:54.893843 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5143 23:10:54.900730 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5144 23:10:54.904265 0 14 0 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
5145 23:10:54.906895 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5146 23:10:54.913393 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5147 23:10:54.917111 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5148 23:10:54.920064 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5149 23:10:54.927091 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5150 23:10:54.930161 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5151 23:10:54.933091 0 14 28 | B1->B0 | 3434 2d2d | 1 1 | (1 1) (1 0)
5152 23:10:54.940071 0 15 0 | B1->B0 | 2f2f 2424 | 1 0 | (1 1) (0 0)
5153 23:10:54.943338 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5154 23:10:54.946334 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5155 23:10:54.952878 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5156 23:10:54.956110 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5157 23:10:54.962576 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5158 23:10:54.965681 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5159 23:10:54.968868 0 15 28 | B1->B0 | 2323 3c3c | 0 1 | (0 0) (0 0)
5160 23:10:54.975806 1 0 0 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
5161 23:10:54.979447 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5162 23:10:54.982034 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5163 23:10:54.988746 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5164 23:10:54.992350 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5165 23:10:54.995480 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5166 23:10:55.001826 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5167 23:10:55.005270 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5168 23:10:55.008481 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5169 23:10:55.015146 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5170 23:10:55.018620 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5171 23:10:55.021804 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5172 23:10:55.028388 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5173 23:10:55.031739 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5174 23:10:55.035336 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5175 23:10:55.041821 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5176 23:10:55.045169 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5177 23:10:55.048997 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5178 23:10:55.055702 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5179 23:10:55.057963 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5180 23:10:55.062581 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5181 23:10:55.068343 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5182 23:10:55.071716 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5183 23:10:55.074510 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5184 23:10:55.078084 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5185 23:10:55.084476 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5186 23:10:55.087543 Total UI for P1: 0, mck2ui 16
5187 23:10:55.090818 best dqsien dly found for B0: ( 1, 2, 30)
5188 23:10:55.095246 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5189 23:10:55.097473 Total UI for P1: 0, mck2ui 16
5190 23:10:55.100743 best dqsien dly found for B1: ( 1, 3, 4)
5191 23:10:55.104282 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5192 23:10:55.107579 best DQS1 dly(MCK, UI, PI) = (1, 3, 4)
5193 23:10:55.108088
5194 23:10:55.110386 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5195 23:10:55.117576 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 4)
5196 23:10:55.118113 [Gating] SW calibration Done
5197 23:10:55.118559 ==
5198 23:10:55.120332 Dram Type= 6, Freq= 0, CH_0, rank 0
5199 23:10:55.127679 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5200 23:10:55.128211 ==
5201 23:10:55.128654 RX Vref Scan: 0
5202 23:10:55.129064
5203 23:10:55.130743 RX Vref 0 -> 0, step: 1
5204 23:10:55.131275
5205 23:10:55.133635 RX Delay -80 -> 252, step: 8
5206 23:10:55.137254 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5207 23:10:55.140161 iDelay=208, Bit 1, Center 103 (8 ~ 199) 192
5208 23:10:55.144334 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5209 23:10:55.150654 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5210 23:10:55.153162 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5211 23:10:55.156506 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5212 23:10:55.159985 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5213 23:10:55.163054 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5214 23:10:55.169982 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5215 23:10:55.173272 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5216 23:10:55.176422 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5217 23:10:55.179802 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5218 23:10:55.182772 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5219 23:10:55.186346 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5220 23:10:55.192775 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5221 23:10:55.196525 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5222 23:10:55.197046 ==
5223 23:10:55.199975 Dram Type= 6, Freq= 0, CH_0, rank 0
5224 23:10:55.202296 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5225 23:10:55.202716 ==
5226 23:10:55.205913 DQS Delay:
5227 23:10:55.206451 DQS0 = 0, DQS1 = 0
5228 23:10:55.206786 DQM Delay:
5229 23:10:55.209371 DQM0 = 100, DQM1 = 90
5230 23:10:55.209895 DQ Delay:
5231 23:10:55.212862 DQ0 =103, DQ1 =103, DQ2 =95, DQ3 =95
5232 23:10:55.215695 DQ4 =103, DQ5 =87, DQ6 =111, DQ7 =107
5233 23:10:55.219506 DQ8 =83, DQ9 =75, DQ10 =87, DQ11 =83
5234 23:10:55.222727 DQ12 =99, DQ13 =95, DQ14 =99, DQ15 =99
5235 23:10:55.223247
5236 23:10:55.225597
5237 23:10:55.226025 ==
5238 23:10:55.228879 Dram Type= 6, Freq= 0, CH_0, rank 0
5239 23:10:55.231932 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5240 23:10:55.232355 ==
5241 23:10:55.232685
5242 23:10:55.232992
5243 23:10:55.235329 TX Vref Scan disable
5244 23:10:55.235838 == TX Byte 0 ==
5245 23:10:55.242255 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5246 23:10:55.245820 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5247 23:10:55.246360 == TX Byte 1 ==
5248 23:10:55.252202 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5249 23:10:55.255461 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5250 23:10:55.255988 ==
5251 23:10:55.259177 Dram Type= 6, Freq= 0, CH_0, rank 0
5252 23:10:55.261730 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5253 23:10:55.262269 ==
5254 23:10:55.262607
5255 23:10:55.265227
5256 23:10:55.265640 TX Vref Scan disable
5257 23:10:55.267955 == TX Byte 0 ==
5258 23:10:55.271624 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5259 23:10:55.274699 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5260 23:10:55.277899 == TX Byte 1 ==
5261 23:10:55.281182 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5262 23:10:55.287963 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5263 23:10:55.288468
5264 23:10:55.288799 [DATLAT]
5265 23:10:55.289106 Freq=933, CH0 RK0
5266 23:10:55.289404
5267 23:10:55.291138 DATLAT Default: 0xd
5268 23:10:55.291775 0, 0xFFFF, sum = 0
5269 23:10:55.294937 1, 0xFFFF, sum = 0
5270 23:10:55.297747 2, 0xFFFF, sum = 0
5271 23:10:55.298169 3, 0xFFFF, sum = 0
5272 23:10:55.300874 4, 0xFFFF, sum = 0
5273 23:10:55.301299 5, 0xFFFF, sum = 0
5274 23:10:55.304257 6, 0xFFFF, sum = 0
5275 23:10:55.304678 7, 0xFFFF, sum = 0
5276 23:10:55.307769 8, 0xFFFF, sum = 0
5277 23:10:55.308305 9, 0xFFFF, sum = 0
5278 23:10:55.310741 10, 0x0, sum = 1
5279 23:10:55.311270 11, 0x0, sum = 2
5280 23:10:55.314073 12, 0x0, sum = 3
5281 23:10:55.314598 13, 0x0, sum = 4
5282 23:10:55.317053 best_step = 11
5283 23:10:55.317468
5284 23:10:55.317799 ==
5285 23:10:55.320233 Dram Type= 6, Freq= 0, CH_0, rank 0
5286 23:10:55.324421 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5287 23:10:55.324947 ==
5288 23:10:55.327539 RX Vref Scan: 1
5289 23:10:55.327957
5290 23:10:55.328289 RX Vref 0 -> 0, step: 1
5291 23:10:55.328599
5292 23:10:55.330328 RX Delay -61 -> 252, step: 4
5293 23:10:55.330748
5294 23:10:55.333515 Set Vref, RX VrefLevel [Byte0]: 51
5295 23:10:55.336961 [Byte1]: 48
5296 23:10:55.340342
5297 23:10:55.343728 Final RX Vref Byte 0 = 51 to rank0
5298 23:10:55.344149 Final RX Vref Byte 1 = 48 to rank0
5299 23:10:55.346795 Final RX Vref Byte 0 = 51 to rank1
5300 23:10:55.350386 Final RX Vref Byte 1 = 48 to rank1==
5301 23:10:55.353494 Dram Type= 6, Freq= 0, CH_0, rank 0
5302 23:10:55.359791 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5303 23:10:55.360367 ==
5304 23:10:55.360710 DQS Delay:
5305 23:10:55.363531 DQS0 = 0, DQS1 = 0
5306 23:10:55.364061 DQM Delay:
5307 23:10:55.364396 DQM0 = 99, DQM1 = 87
5308 23:10:55.366579 DQ Delay:
5309 23:10:55.370709 DQ0 =100, DQ1 =100, DQ2 =94, DQ3 =96
5310 23:10:55.373795 DQ4 =100, DQ5 =90, DQ6 =110, DQ7 =106
5311 23:10:55.376710 DQ8 =78, DQ9 =74, DQ10 =86, DQ11 =80
5312 23:10:55.380253 DQ12 =94, DQ13 =90, DQ14 =98, DQ15 =96
5313 23:10:55.380777
5314 23:10:55.381108
5315 23:10:55.386365 [DQSOSCAuto] RK0, (LSB)MR18= 0x150f, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 415 ps
5316 23:10:55.389265 CH0 RK0: MR19=505, MR18=150F
5317 23:10:55.396327 CH0_RK0: MR19=0x505, MR18=0x150F, DQSOSC=415, MR23=63, INC=62, DEC=41
5318 23:10:55.396847
5319 23:10:55.399176 ----->DramcWriteLeveling(PI) begin...
5320 23:10:55.399726 ==
5321 23:10:55.403458 Dram Type= 6, Freq= 0, CH_0, rank 1
5322 23:10:55.406038 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5323 23:10:55.409667 ==
5324 23:10:55.412718 Write leveling (Byte 0): 33 => 33
5325 23:10:55.413229 Write leveling (Byte 1): 31 => 31
5326 23:10:55.416288 DramcWriteLeveling(PI) end<-----
5327 23:10:55.416707
5328 23:10:55.417035 ==
5329 23:10:55.418830 Dram Type= 6, Freq= 0, CH_0, rank 1
5330 23:10:55.425482 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5331 23:10:55.425992 ==
5332 23:10:55.429248 [Gating] SW mode calibration
5333 23:10:55.435426 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5334 23:10:55.439247 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5335 23:10:55.445227 0 14 0 | B1->B0 | 2d2d 3434 | 0 1 | (0 0) (1 1)
5336 23:10:55.448864 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5337 23:10:55.453538 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5338 23:10:55.459299 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5339 23:10:55.462210 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5340 23:10:55.465242 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5341 23:10:55.471830 0 14 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
5342 23:10:55.475179 0 14 28 | B1->B0 | 3434 2828 | 1 0 | (1 1) (0 0)
5343 23:10:55.478876 0 15 0 | B1->B0 | 2d2d 2323 | 0 0 | (0 1) (0 0)
5344 23:10:55.485076 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5345 23:10:55.489159 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5346 23:10:55.491726 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5347 23:10:55.498162 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5348 23:10:55.501220 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5349 23:10:55.505080 0 15 24 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5350 23:10:55.511898 0 15 28 | B1->B0 | 2b2b 4141 | 0 0 | (0 0) (0 0)
5351 23:10:55.515077 1 0 0 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
5352 23:10:55.517745 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5353 23:10:55.524680 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5354 23:10:55.528136 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5355 23:10:55.530725 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5356 23:10:55.537713 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5357 23:10:55.540944 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5358 23:10:55.544423 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5359 23:10:55.550983 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5360 23:10:55.554064 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5361 23:10:55.557121 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5362 23:10:55.563972 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5363 23:10:55.567160 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5364 23:10:55.570815 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5365 23:10:55.576950 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5366 23:10:55.580965 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5367 23:10:55.583693 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5368 23:10:55.590349 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5369 23:10:55.593642 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5370 23:10:55.596858 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5371 23:10:55.603771 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5372 23:10:55.606627 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5373 23:10:55.610183 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5374 23:10:55.617045 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5375 23:10:55.617550 Total UI for P1: 0, mck2ui 16
5376 23:10:55.623340 best dqsien dly found for B0: ( 1, 2, 26)
5377 23:10:55.626983 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5378 23:10:55.630011 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5379 23:10:55.633455 Total UI for P1: 0, mck2ui 16
5380 23:10:55.636386 best dqsien dly found for B1: ( 1, 2, 30)
5381 23:10:55.640054 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5382 23:10:55.643251 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5383 23:10:55.643759
5384 23:10:55.649658 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5385 23:10:55.652936 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5386 23:10:55.655973 [Gating] SW calibration Done
5387 23:10:55.656526 ==
5388 23:10:55.659869 Dram Type= 6, Freq= 0, CH_0, rank 1
5389 23:10:55.663009 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5390 23:10:55.663551 ==
5391 23:10:55.663886 RX Vref Scan: 0
5392 23:10:55.664191
5393 23:10:55.666140 RX Vref 0 -> 0, step: 1
5394 23:10:55.666549
5395 23:10:55.669799 RX Delay -80 -> 252, step: 8
5396 23:10:55.672848 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5397 23:10:55.676487 iDelay=200, Bit 1, Center 99 (0 ~ 199) 200
5398 23:10:55.682912 iDelay=200, Bit 2, Center 91 (-8 ~ 191) 200
5399 23:10:55.685606 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5400 23:10:55.689819 iDelay=200, Bit 4, Center 99 (0 ~ 199) 200
5401 23:10:55.692686 iDelay=200, Bit 5, Center 87 (-8 ~ 183) 192
5402 23:10:55.695976 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5403 23:10:55.699312 iDelay=200, Bit 7, Center 103 (8 ~ 199) 192
5404 23:10:55.705746 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5405 23:10:55.708757 iDelay=200, Bit 9, Center 75 (-16 ~ 167) 184
5406 23:10:55.712204 iDelay=200, Bit 10, Center 91 (0 ~ 183) 184
5407 23:10:55.715949 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5408 23:10:55.718876 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5409 23:10:55.722175 iDelay=200, Bit 13, Center 91 (0 ~ 183) 184
5410 23:10:55.728451 iDelay=200, Bit 14, Center 99 (8 ~ 191) 184
5411 23:10:55.732733 iDelay=200, Bit 15, Center 91 (0 ~ 183) 184
5412 23:10:55.733245 ==
5413 23:10:55.735401 Dram Type= 6, Freq= 0, CH_0, rank 1
5414 23:10:55.738861 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5415 23:10:55.739419 ==
5416 23:10:55.741926 DQS Delay:
5417 23:10:55.742434 DQS0 = 0, DQS1 = 0
5418 23:10:55.742766 DQM Delay:
5419 23:10:55.745232 DQM0 = 96, DQM1 = 88
5420 23:10:55.745737 DQ Delay:
5421 23:10:55.748129 DQ0 =95, DQ1 =99, DQ2 =91, DQ3 =95
5422 23:10:55.752219 DQ4 =99, DQ5 =87, DQ6 =103, DQ7 =103
5423 23:10:55.755089 DQ8 =83, DQ9 =75, DQ10 =91, DQ11 =83
5424 23:10:55.758268 DQ12 =95, DQ13 =91, DQ14 =99, DQ15 =91
5425 23:10:55.758782
5426 23:10:55.759113
5427 23:10:55.761751 ==
5428 23:10:55.762257 Dram Type= 6, Freq= 0, CH_0, rank 1
5429 23:10:55.768003 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5430 23:10:55.768515 ==
5431 23:10:55.768851
5432 23:10:55.769159
5433 23:10:55.771599 TX Vref Scan disable
5434 23:10:55.772107 == TX Byte 0 ==
5435 23:10:55.774491 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5436 23:10:55.781391 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5437 23:10:55.781902 == TX Byte 1 ==
5438 23:10:55.784822 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5439 23:10:55.791146 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5440 23:10:55.791747 ==
5441 23:10:55.794333 Dram Type= 6, Freq= 0, CH_0, rank 1
5442 23:10:55.798044 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5443 23:10:55.798555 ==
5444 23:10:55.798888
5445 23:10:55.799196
5446 23:10:55.800980 TX Vref Scan disable
5447 23:10:55.804638 == TX Byte 0 ==
5448 23:10:55.807774 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5449 23:10:55.810699 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5450 23:10:55.813879 == TX Byte 1 ==
5451 23:10:55.817663 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5452 23:10:55.820435 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5453 23:10:55.820859
5454 23:10:55.823926 [DATLAT]
5455 23:10:55.824341 Freq=933, CH0 RK1
5456 23:10:55.824674
5457 23:10:55.826931 DATLAT Default: 0xb
5458 23:10:55.827348 0, 0xFFFF, sum = 0
5459 23:10:55.830538 1, 0xFFFF, sum = 0
5460 23:10:55.831055 2, 0xFFFF, sum = 0
5461 23:10:55.833817 3, 0xFFFF, sum = 0
5462 23:10:55.834335 4, 0xFFFF, sum = 0
5463 23:10:55.837090 5, 0xFFFF, sum = 0
5464 23:10:55.837517 6, 0xFFFF, sum = 0
5465 23:10:55.840298 7, 0xFFFF, sum = 0
5466 23:10:55.840720 8, 0xFFFF, sum = 0
5467 23:10:55.844021 9, 0xFFFF, sum = 0
5468 23:10:55.844445 10, 0x0, sum = 1
5469 23:10:55.847146 11, 0x0, sum = 2
5470 23:10:55.847761 12, 0x0, sum = 3
5471 23:10:55.850794 13, 0x0, sum = 4
5472 23:10:55.851309 best_step = 11
5473 23:10:55.851731
5474 23:10:55.852051 ==
5475 23:10:55.853937 Dram Type= 6, Freq= 0, CH_0, rank 1
5476 23:10:55.860477 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5477 23:10:55.860988 ==
5478 23:10:55.861322 RX Vref Scan: 0
5479 23:10:55.861635
5480 23:10:55.863632 RX Vref 0 -> 0, step: 1
5481 23:10:55.864141
5482 23:10:55.866825 RX Delay -61 -> 252, step: 4
5483 23:10:55.870378 iDelay=195, Bit 0, Center 96 (11 ~ 182) 172
5484 23:10:55.876673 iDelay=195, Bit 1, Center 98 (7 ~ 190) 184
5485 23:10:55.880260 iDelay=195, Bit 2, Center 94 (3 ~ 186) 184
5486 23:10:55.883638 iDelay=195, Bit 3, Center 94 (7 ~ 182) 176
5487 23:10:55.886198 iDelay=195, Bit 4, Center 100 (7 ~ 194) 188
5488 23:10:55.889921 iDelay=195, Bit 5, Center 90 (3 ~ 178) 176
5489 23:10:55.893339 iDelay=195, Bit 6, Center 108 (23 ~ 194) 172
5490 23:10:55.899498 iDelay=195, Bit 7, Center 106 (19 ~ 194) 176
5491 23:10:55.902684 iDelay=195, Bit 8, Center 80 (-9 ~ 170) 180
5492 23:10:55.906880 iDelay=195, Bit 9, Center 76 (-13 ~ 166) 180
5493 23:10:55.909841 iDelay=195, Bit 10, Center 90 (3 ~ 178) 176
5494 23:10:55.913814 iDelay=195, Bit 11, Center 82 (-5 ~ 170) 176
5495 23:10:55.919744 iDelay=195, Bit 12, Center 92 (3 ~ 182) 180
5496 23:10:55.924548 iDelay=195, Bit 13, Center 92 (3 ~ 182) 180
5497 23:10:55.926722 iDelay=195, Bit 14, Center 100 (11 ~ 190) 180
5498 23:10:55.929298 iDelay=195, Bit 15, Center 94 (7 ~ 182) 176
5499 23:10:55.929811 ==
5500 23:10:55.932753 Dram Type= 6, Freq= 0, CH_0, rank 1
5501 23:10:55.936258 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5502 23:10:55.939538 ==
5503 23:10:55.940042 DQS Delay:
5504 23:10:55.940374 DQS0 = 0, DQS1 = 0
5505 23:10:55.942523 DQM Delay:
5506 23:10:55.942936 DQM0 = 98, DQM1 = 88
5507 23:10:55.945600 DQ Delay:
5508 23:10:55.949226 DQ0 =96, DQ1 =98, DQ2 =94, DQ3 =94
5509 23:10:55.953419 DQ4 =100, DQ5 =90, DQ6 =108, DQ7 =106
5510 23:10:55.955444 DQ8 =80, DQ9 =76, DQ10 =90, DQ11 =82
5511 23:10:55.958823 DQ12 =92, DQ13 =92, DQ14 =100, DQ15 =94
5512 23:10:55.959468
5513 23:10:55.959933
5514 23:10:55.965903 [DQSOSCAuto] RK1, (LSB)MR18= 0x1411, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 415 ps
5515 23:10:55.969129 CH0 RK1: MR19=505, MR18=1411
5516 23:10:55.975726 CH0_RK1: MR19=0x505, MR18=0x1411, DQSOSC=415, MR23=63, INC=62, DEC=41
5517 23:10:55.978796 [RxdqsGatingPostProcess] freq 933
5518 23:10:55.981983 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5519 23:10:55.984912 best DQS0 dly(2T, 0.5T) = (0, 10)
5520 23:10:55.988394 best DQS1 dly(2T, 0.5T) = (0, 11)
5521 23:10:55.991826 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5522 23:10:55.994785 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5523 23:10:55.998785 best DQS0 dly(2T, 0.5T) = (0, 10)
5524 23:10:56.001772 best DQS1 dly(2T, 0.5T) = (0, 10)
5525 23:10:56.005082 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5526 23:10:56.008679 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5527 23:10:56.011889 Pre-setting of DQS Precalculation
5528 23:10:56.014953 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5529 23:10:56.018161 ==
5530 23:10:56.021270 Dram Type= 6, Freq= 0, CH_1, rank 0
5531 23:10:56.024757 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5532 23:10:56.025173 ==
5533 23:10:56.028088 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5534 23:10:56.034603 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5535 23:10:56.038475 [CA 0] Center 36 (6~67) winsize 62
5536 23:10:56.041887 [CA 1] Center 36 (6~67) winsize 62
5537 23:10:56.045715 [CA 2] Center 34 (4~65) winsize 62
5538 23:10:56.048993 [CA 3] Center 34 (4~65) winsize 62
5539 23:10:56.052571 [CA 4] Center 34 (4~65) winsize 62
5540 23:10:56.055122 [CA 5] Center 33 (3~64) winsize 62
5541 23:10:56.055688
5542 23:10:56.058650 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5543 23:10:56.059159
5544 23:10:56.062079 [CATrainingPosCal] consider 1 rank data
5545 23:10:56.065102 u2DelayCellTimex100 = 270/100 ps
5546 23:10:56.068201 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5547 23:10:56.074529 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5548 23:10:56.078357 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5549 23:10:56.081417 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5550 23:10:56.085028 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5551 23:10:56.088060 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5552 23:10:56.088572
5553 23:10:56.091344 CA PerBit enable=1, Macro0, CA PI delay=33
5554 23:10:56.091887
5555 23:10:56.094250 [CBTSetCACLKResult] CA Dly = 33
5556 23:10:56.097998 CS Dly: 5 (0~36)
5557 23:10:56.098411 ==
5558 23:10:56.101762 Dram Type= 6, Freq= 0, CH_1, rank 1
5559 23:10:56.104299 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5560 23:10:56.104719 ==
5561 23:10:56.111011 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5562 23:10:56.114833 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5563 23:10:56.118641 [CA 0] Center 36 (5~67) winsize 63
5564 23:10:56.122060 [CA 1] Center 36 (6~67) winsize 62
5565 23:10:56.125169 [CA 2] Center 34 (4~65) winsize 62
5566 23:10:56.127959 [CA 3] Center 33 (3~64) winsize 62
5567 23:10:56.132821 [CA 4] Center 33 (3~64) winsize 62
5568 23:10:56.134956 [CA 5] Center 33 (3~64) winsize 62
5569 23:10:56.135417
5570 23:10:56.138146 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5571 23:10:56.138563
5572 23:10:56.141545 [CATrainingPosCal] consider 2 rank data
5573 23:10:56.144977 u2DelayCellTimex100 = 270/100 ps
5574 23:10:56.148301 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5575 23:10:56.154736 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5576 23:10:56.158410 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5577 23:10:56.161877 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5578 23:10:56.164829 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5579 23:10:56.167850 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5580 23:10:56.168422
5581 23:10:56.171194 CA PerBit enable=1, Macro0, CA PI delay=33
5582 23:10:56.171837
5583 23:10:56.174484 [CBTSetCACLKResult] CA Dly = 33
5584 23:10:56.177465 CS Dly: 6 (0~38)
5585 23:10:56.177927
5586 23:10:56.180874 ----->DramcWriteLeveling(PI) begin...
5587 23:10:56.181384 ==
5588 23:10:56.184128 Dram Type= 6, Freq= 0, CH_1, rank 0
5589 23:10:56.187728 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5590 23:10:56.188240 ==
5591 23:10:56.191533 Write leveling (Byte 0): 29 => 29
5592 23:10:56.194297 Write leveling (Byte 1): 29 => 29
5593 23:10:56.197649 DramcWriteLeveling(PI) end<-----
5594 23:10:56.198156
5595 23:10:56.198489 ==
5596 23:10:56.200685 Dram Type= 6, Freq= 0, CH_1, rank 0
5597 23:10:56.203979 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5598 23:10:56.204511 ==
5599 23:10:56.207978 [Gating] SW mode calibration
5600 23:10:56.214430 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5601 23:10:56.220471 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5602 23:10:56.223647 0 14 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5603 23:10:56.227525 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5604 23:10:56.233754 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5605 23:10:56.237306 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5606 23:10:56.240599 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5607 23:10:56.247300 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5608 23:10:56.251095 0 14 24 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5609 23:10:56.253447 0 14 28 | B1->B0 | 2c2c 2323 | 1 0 | (1 1) (1 0)
5610 23:10:56.260517 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5611 23:10:56.264645 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5612 23:10:56.266622 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5613 23:10:56.273514 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5614 23:10:56.276744 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5615 23:10:56.280133 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5616 23:10:56.286580 0 15 24 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
5617 23:10:56.289650 0 15 28 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
5618 23:10:56.292896 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5619 23:10:56.299732 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5620 23:10:56.302845 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5621 23:10:56.306178 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5622 23:10:56.313232 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5623 23:10:56.316141 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5624 23:10:56.319020 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5625 23:10:56.326510 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5626 23:10:56.329046 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5627 23:10:56.332439 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5628 23:10:56.338951 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5629 23:10:56.342590 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5630 23:10:56.349102 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5631 23:10:56.352203 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5632 23:10:56.355523 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5633 23:10:56.362466 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5634 23:10:56.365168 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5635 23:10:56.369015 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5636 23:10:56.375061 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5637 23:10:56.378516 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5638 23:10:56.382100 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5639 23:10:56.388208 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5640 23:10:56.391753 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5641 23:10:56.395417 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5642 23:10:56.401662 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5643 23:10:56.402181 Total UI for P1: 0, mck2ui 16
5644 23:10:56.407926 best dqsien dly found for B0: ( 1, 2, 28)
5645 23:10:56.411287 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5646 23:10:56.414887 Total UI for P1: 0, mck2ui 16
5647 23:10:56.417799 best dqsien dly found for B1: ( 1, 2, 30)
5648 23:10:56.421143 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5649 23:10:56.424764 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5650 23:10:56.425278
5651 23:10:56.427662 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5652 23:10:56.431551 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5653 23:10:56.434575 [Gating] SW calibration Done
5654 23:10:56.435138 ==
5655 23:10:56.438268 Dram Type= 6, Freq= 0, CH_1, rank 0
5656 23:10:56.441236 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5657 23:10:56.444093 ==
5658 23:10:56.444603 RX Vref Scan: 0
5659 23:10:56.444936
5660 23:10:56.447679 RX Vref 0 -> 0, step: 1
5661 23:10:56.448185
5662 23:10:56.450697 RX Delay -80 -> 252, step: 8
5663 23:10:56.454096 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5664 23:10:56.457727 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5665 23:10:56.461146 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5666 23:10:56.464183 iDelay=208, Bit 3, Center 99 (0 ~ 199) 200
5667 23:10:56.467442 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5668 23:10:56.474076 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5669 23:10:56.477436 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5670 23:10:56.480931 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5671 23:10:56.484315 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5672 23:10:56.486985 iDelay=208, Bit 9, Center 87 (-8 ~ 183) 192
5673 23:10:56.493971 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5674 23:10:56.496936 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5675 23:10:56.500789 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5676 23:10:56.503400 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5677 23:10:56.506446 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5678 23:10:56.513548 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5679 23:10:56.514048 ==
5680 23:10:56.516796 Dram Type= 6, Freq= 0, CH_1, rank 0
5681 23:10:56.519951 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5682 23:10:56.520375 ==
5683 23:10:56.520708 DQS Delay:
5684 23:10:56.523439 DQS0 = 0, DQS1 = 0
5685 23:10:56.523859 DQM Delay:
5686 23:10:56.527737 DQM0 = 100, DQM1 = 96
5687 23:10:56.528253 DQ Delay:
5688 23:10:56.529772 DQ0 =107, DQ1 =95, DQ2 =87, DQ3 =99
5689 23:10:56.533236 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =95
5690 23:10:56.536186 DQ8 =83, DQ9 =87, DQ10 =95, DQ11 =91
5691 23:10:56.539813 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =103
5692 23:10:56.540323
5693 23:10:56.540654
5694 23:10:56.540960 ==
5695 23:10:56.543083 Dram Type= 6, Freq= 0, CH_1, rank 0
5696 23:10:56.549833 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5697 23:10:56.550347 ==
5698 23:10:56.550679
5699 23:10:56.550987
5700 23:10:56.551281 TX Vref Scan disable
5701 23:10:56.553427 == TX Byte 0 ==
5702 23:10:56.556229 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5703 23:10:56.562664 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5704 23:10:56.563221 == TX Byte 1 ==
5705 23:10:56.566434 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5706 23:10:56.573329 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5707 23:10:56.573838 ==
5708 23:10:56.576048 Dram Type= 6, Freq= 0, CH_1, rank 0
5709 23:10:56.579794 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5710 23:10:56.580310 ==
5711 23:10:56.580643
5712 23:10:56.580949
5713 23:10:56.583193 TX Vref Scan disable
5714 23:10:56.583700 == TX Byte 0 ==
5715 23:10:56.590061 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5716 23:10:56.593761 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5717 23:10:56.594270 == TX Byte 1 ==
5718 23:10:56.599335 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5719 23:10:56.602149 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5720 23:10:56.602514
5721 23:10:56.602834 [DATLAT]
5722 23:10:56.605668 Freq=933, CH1 RK0
5723 23:10:56.606258
5724 23:10:56.606656 DATLAT Default: 0xd
5725 23:10:56.609261 0, 0xFFFF, sum = 0
5726 23:10:56.609782 1, 0xFFFF, sum = 0
5727 23:10:56.612674 2, 0xFFFF, sum = 0
5728 23:10:56.615528 3, 0xFFFF, sum = 0
5729 23:10:56.615952 4, 0xFFFF, sum = 0
5730 23:10:56.619511 5, 0xFFFF, sum = 0
5731 23:10:56.619972 6, 0xFFFF, sum = 0
5732 23:10:56.622978 7, 0xFFFF, sum = 0
5733 23:10:56.623450 8, 0xFFFF, sum = 0
5734 23:10:56.625677 9, 0xFFFF, sum = 0
5735 23:10:56.626100 10, 0x0, sum = 1
5736 23:10:56.629076 11, 0x0, sum = 2
5737 23:10:56.629498 12, 0x0, sum = 3
5738 23:10:56.632153 13, 0x0, sum = 4
5739 23:10:56.632590 best_step = 11
5740 23:10:56.632937
5741 23:10:56.633284 ==
5742 23:10:56.635507 Dram Type= 6, Freq= 0, CH_1, rank 0
5743 23:10:56.638956 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5744 23:10:56.639415 ==
5745 23:10:56.641992 RX Vref Scan: 1
5746 23:10:56.642408
5747 23:10:56.645325 RX Vref 0 -> 0, step: 1
5748 23:10:56.645739
5749 23:10:56.646123 RX Delay -53 -> 252, step: 4
5750 23:10:56.646446
5751 23:10:56.648758 Set Vref, RX VrefLevel [Byte0]: 51
5752 23:10:56.652084 [Byte1]: 48
5753 23:10:56.656863
5754 23:10:56.659970 Final RX Vref Byte 0 = 51 to rank0
5755 23:10:56.660390 Final RX Vref Byte 1 = 48 to rank0
5756 23:10:56.663095 Final RX Vref Byte 0 = 51 to rank1
5757 23:10:56.666506 Final RX Vref Byte 1 = 48 to rank1==
5758 23:10:56.670060 Dram Type= 6, Freq= 0, CH_1, rank 0
5759 23:10:56.676149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5760 23:10:56.676661 ==
5761 23:10:56.677153 DQS Delay:
5762 23:10:56.679441 DQS0 = 0, DQS1 = 0
5763 23:10:56.679864 DQM Delay:
5764 23:10:56.680259 DQM0 = 98, DQM1 = 94
5765 23:10:56.683540 DQ Delay:
5766 23:10:56.686642 DQ0 =104, DQ1 =94, DQ2 =86, DQ3 =98
5767 23:10:56.689649 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =94
5768 23:10:56.692797 DQ8 =78, DQ9 =84, DQ10 =94, DQ11 =88
5769 23:10:56.696079 DQ12 =102, DQ13 =104, DQ14 =100, DQ15 =104
5770 23:10:56.696495
5771 23:10:56.696821
5772 23:10:56.702452 [DQSOSCAuto] RK0, (LSB)MR18= 0x515, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 420 ps
5773 23:10:56.705700 CH1 RK0: MR19=505, MR18=515
5774 23:10:56.712448 CH1_RK0: MR19=0x505, MR18=0x515, DQSOSC=415, MR23=63, INC=62, DEC=41
5775 23:10:56.712954
5776 23:10:56.716118 ----->DramcWriteLeveling(PI) begin...
5777 23:10:56.716629 ==
5778 23:10:56.719735 Dram Type= 6, Freq= 0, CH_1, rank 1
5779 23:10:56.722556 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5780 23:10:56.722977 ==
5781 23:10:56.725946 Write leveling (Byte 0): 26 => 26
5782 23:10:56.729119 Write leveling (Byte 1): 27 => 27
5783 23:10:56.732569 DramcWriteLeveling(PI) end<-----
5784 23:10:56.733111
5785 23:10:56.733568 ==
5786 23:10:56.735308 Dram Type= 6, Freq= 0, CH_1, rank 1
5787 23:10:56.742242 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5788 23:10:56.742816 ==
5789 23:10:56.746345 [Gating] SW mode calibration
5790 23:10:56.752257 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5791 23:10:56.755064 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5792 23:10:56.762061 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5793 23:10:56.765251 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5794 23:10:56.769781 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5795 23:10:56.775099 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5796 23:10:56.778587 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5797 23:10:56.781494 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5798 23:10:56.789214 0 14 24 | B1->B0 | 3434 3030 | 1 0 | (1 1) (1 0)
5799 23:10:56.791164 0 14 28 | B1->B0 | 2626 2323 | 0 0 | (1 0) (1 0)
5800 23:10:56.794467 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5801 23:10:56.801194 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5802 23:10:56.804485 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5803 23:10:56.807906 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5804 23:10:56.815053 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5805 23:10:56.817967 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5806 23:10:56.821127 0 15 24 | B1->B0 | 2323 3636 | 0 0 | (0 0) (0 0)
5807 23:10:56.827834 0 15 28 | B1->B0 | 3a3a 4646 | 1 0 | (0 0) (0 0)
5808 23:10:56.831161 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5809 23:10:56.833875 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5810 23:10:56.840219 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5811 23:10:56.844538 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5812 23:10:56.847739 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5813 23:10:56.854005 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5814 23:10:56.858478 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5815 23:10:56.860219 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5816 23:10:56.867064 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5817 23:10:56.870003 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5818 23:10:56.873787 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5819 23:10:56.880151 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5820 23:10:56.884056 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5821 23:10:56.886192 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5822 23:10:56.892746 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5823 23:10:56.896283 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5824 23:10:56.899588 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5825 23:10:56.905976 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5826 23:10:56.909617 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5827 23:10:56.916064 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5828 23:10:56.919515 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5829 23:10:56.922660 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5830 23:10:56.929729 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5831 23:10:56.932831 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5832 23:10:56.936200 Total UI for P1: 0, mck2ui 16
5833 23:10:56.939070 best dqsien dly found for B0: ( 1, 2, 24)
5834 23:10:56.942534 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5835 23:10:56.945683 Total UI for P1: 0, mck2ui 16
5836 23:10:56.949032 best dqsien dly found for B1: ( 1, 2, 28)
5837 23:10:56.952773 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5838 23:10:56.955276 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5839 23:10:56.955807
5840 23:10:56.958722 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5841 23:10:56.966069 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5842 23:10:56.966489 [Gating] SW calibration Done
5843 23:10:56.968779 ==
5844 23:10:56.969298 Dram Type= 6, Freq= 0, CH_1, rank 1
5845 23:10:56.975761 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5846 23:10:56.976274 ==
5847 23:10:56.976605 RX Vref Scan: 0
5848 23:10:56.976916
5849 23:10:56.978726 RX Vref 0 -> 0, step: 1
5850 23:10:56.979232
5851 23:10:56.981971 RX Delay -80 -> 252, step: 8
5852 23:10:56.985317 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5853 23:10:56.988357 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5854 23:10:56.992234 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5855 23:10:56.998338 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5856 23:10:57.001787 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5857 23:10:57.004515 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5858 23:10:57.008250 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5859 23:10:57.011269 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5860 23:10:57.014768 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5861 23:10:57.021100 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5862 23:10:57.024146 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5863 23:10:57.027677 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5864 23:10:57.031475 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5865 23:10:57.034527 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5866 23:10:57.040936 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5867 23:10:57.044331 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5868 23:10:57.044898 ==
5869 23:10:57.047543 Dram Type= 6, Freq= 0, CH_1, rank 1
5870 23:10:57.051069 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5871 23:10:57.051684 ==
5872 23:10:57.053852 DQS Delay:
5873 23:10:57.054314 DQS0 = 0, DQS1 = 0
5874 23:10:57.054683 DQM Delay:
5875 23:10:57.057613 DQM0 = 97, DQM1 = 94
5876 23:10:57.058172 DQ Delay:
5877 23:10:57.060798 DQ0 =103, DQ1 =91, DQ2 =87, DQ3 =95
5878 23:10:57.063982 DQ4 =95, DQ5 =107, DQ6 =103, DQ7 =95
5879 23:10:57.067782 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =87
5880 23:10:57.070594 DQ12 =103, DQ13 =103, DQ14 =95, DQ15 =103
5881 23:10:57.071117
5882 23:10:57.071475
5883 23:10:57.073698 ==
5884 23:10:57.077566 Dram Type= 6, Freq= 0, CH_1, rank 1
5885 23:10:57.081595 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5886 23:10:57.082248 ==
5887 23:10:57.082622
5888 23:10:57.082962
5889 23:10:57.084082 TX Vref Scan disable
5890 23:10:57.084499 == TX Byte 0 ==
5891 23:10:57.090715 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5892 23:10:57.093262 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5893 23:10:57.093684 == TX Byte 1 ==
5894 23:10:57.100645 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5895 23:10:57.103331 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5896 23:10:57.103794 ==
5897 23:10:57.106750 Dram Type= 6, Freq= 0, CH_1, rank 1
5898 23:10:57.109995 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5899 23:10:57.110431 ==
5900 23:10:57.110758
5901 23:10:57.111061
5902 23:10:57.113652 TX Vref Scan disable
5903 23:10:57.117192 == TX Byte 0 ==
5904 23:10:57.120513 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5905 23:10:57.123067 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5906 23:10:57.126664 == TX Byte 1 ==
5907 23:10:57.130090 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5908 23:10:57.133662 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5909 23:10:57.134183
5910 23:10:57.136317 [DATLAT]
5911 23:10:57.136733 Freq=933, CH1 RK1
5912 23:10:57.137066
5913 23:10:57.139476 DATLAT Default: 0xb
5914 23:10:57.139897 0, 0xFFFF, sum = 0
5915 23:10:57.142873 1, 0xFFFF, sum = 0
5916 23:10:57.143295 2, 0xFFFF, sum = 0
5917 23:10:57.146596 3, 0xFFFF, sum = 0
5918 23:10:57.147131 4, 0xFFFF, sum = 0
5919 23:10:57.149432 5, 0xFFFF, sum = 0
5920 23:10:57.149965 6, 0xFFFF, sum = 0
5921 23:10:57.152596 7, 0xFFFF, sum = 0
5922 23:10:57.156276 8, 0xFFFF, sum = 0
5923 23:10:57.156700 9, 0xFFFF, sum = 0
5924 23:10:57.157041 10, 0x0, sum = 1
5925 23:10:57.159700 11, 0x0, sum = 2
5926 23:10:57.160229 12, 0x0, sum = 3
5927 23:10:57.162693 13, 0x0, sum = 4
5928 23:10:57.163238 best_step = 11
5929 23:10:57.163626
5930 23:10:57.163939 ==
5931 23:10:57.166246 Dram Type= 6, Freq= 0, CH_1, rank 1
5932 23:10:57.173157 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5933 23:10:57.173696 ==
5934 23:10:57.174042 RX Vref Scan: 0
5935 23:10:57.174355
5936 23:10:57.176026 RX Vref 0 -> 0, step: 1
5937 23:10:57.176443
5938 23:10:57.178920 RX Delay -53 -> 252, step: 4
5939 23:10:57.182684 iDelay=203, Bit 0, Center 102 (11 ~ 194) 184
5940 23:10:57.188854 iDelay=203, Bit 1, Center 94 (-1 ~ 190) 192
5941 23:10:57.192975 iDelay=203, Bit 2, Center 86 (-5 ~ 178) 184
5942 23:10:57.195262 iDelay=203, Bit 3, Center 96 (3 ~ 190) 188
5943 23:10:57.198897 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5944 23:10:57.201905 iDelay=203, Bit 5, Center 108 (15 ~ 202) 188
5945 23:10:57.209787 iDelay=203, Bit 6, Center 106 (15 ~ 198) 184
5946 23:10:57.211992 iDelay=203, Bit 7, Center 92 (-1 ~ 186) 188
5947 23:10:57.215788 iDelay=203, Bit 8, Center 78 (-13 ~ 170) 184
5948 23:10:57.218616 iDelay=203, Bit 9, Center 82 (-9 ~ 174) 184
5949 23:10:57.222229 iDelay=203, Bit 10, Center 90 (-1 ~ 182) 184
5950 23:10:57.228190 iDelay=203, Bit 11, Center 84 (-9 ~ 178) 188
5951 23:10:57.231583 iDelay=203, Bit 12, Center 100 (11 ~ 190) 180
5952 23:10:57.235460 iDelay=203, Bit 13, Center 100 (11 ~ 190) 180
5953 23:10:57.238789 iDelay=203, Bit 14, Center 96 (7 ~ 186) 180
5954 23:10:57.241514 iDelay=203, Bit 15, Center 102 (11 ~ 194) 184
5955 23:10:57.245063 ==
5956 23:10:57.245638 Dram Type= 6, Freq= 0, CH_1, rank 1
5957 23:10:57.252181 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5958 23:10:57.252746 ==
5959 23:10:57.253115 DQS Delay:
5960 23:10:57.254403 DQS0 = 0, DQS1 = 0
5961 23:10:57.254861 DQM Delay:
5962 23:10:57.258249 DQM0 = 97, DQM1 = 91
5963 23:10:57.258812 DQ Delay:
5964 23:10:57.261085 DQ0 =102, DQ1 =94, DQ2 =86, DQ3 =96
5965 23:10:57.264642 DQ4 =96, DQ5 =108, DQ6 =106, DQ7 =92
5966 23:10:57.267753 DQ8 =78, DQ9 =82, DQ10 =90, DQ11 =84
5967 23:10:57.271299 DQ12 =100, DQ13 =100, DQ14 =96, DQ15 =102
5968 23:10:57.271968
5969 23:10:57.272343
5970 23:10:57.280857 [DQSOSCAuto] RK1, (LSB)MR18= 0xe25, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 417 ps
5971 23:10:57.281436 CH1 RK1: MR19=505, MR18=E25
5972 23:10:57.287209 CH1_RK1: MR19=0x505, MR18=0xE25, DQSOSC=410, MR23=63, INC=64, DEC=42
5973 23:10:57.292046 [RxdqsGatingPostProcess] freq 933
5974 23:10:57.297081 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5975 23:10:57.300791 best DQS0 dly(2T, 0.5T) = (0, 10)
5976 23:10:57.303974 best DQS1 dly(2T, 0.5T) = (0, 10)
5977 23:10:57.307208 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5978 23:10:57.310628 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5979 23:10:57.311092 best DQS0 dly(2T, 0.5T) = (0, 10)
5980 23:10:57.313383 best DQS1 dly(2T, 0.5T) = (0, 10)
5981 23:10:57.317419 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5982 23:10:57.320309 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5983 23:10:57.323956 Pre-setting of DQS Precalculation
5984 23:10:57.330844 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5985 23:10:57.337499 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5986 23:10:57.343621 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5987 23:10:57.344157
5988 23:10:57.344525
5989 23:10:57.347258 [Calibration Summary] 1866 Mbps
5990 23:10:57.350423 CH 0, Rank 0
5991 23:10:57.350845 SW Impedance : PASS
5992 23:10:57.353373 DUTY Scan : NO K
5993 23:10:57.353896 ZQ Calibration : PASS
5994 23:10:57.356753 Jitter Meter : NO K
5995 23:10:57.359599 CBT Training : PASS
5996 23:10:57.360021 Write leveling : PASS
5997 23:10:57.362984 RX DQS gating : PASS
5998 23:10:57.366993 RX DQ/DQS(RDDQC) : PASS
5999 23:10:57.367563 TX DQ/DQS : PASS
6000 23:10:57.369964 RX DATLAT : PASS
6001 23:10:57.373453 RX DQ/DQS(Engine): PASS
6002 23:10:57.373973 TX OE : NO K
6003 23:10:57.376081 All Pass.
6004 23:10:57.376502
6005 23:10:57.376833 CH 0, Rank 1
6006 23:10:57.380023 SW Impedance : PASS
6007 23:10:57.380598 DUTY Scan : NO K
6008 23:10:57.382648 ZQ Calibration : PASS
6009 23:10:57.386181 Jitter Meter : NO K
6010 23:10:57.386795 CBT Training : PASS
6011 23:10:57.389637 Write leveling : PASS
6012 23:10:57.392816 RX DQS gating : PASS
6013 23:10:57.393234 RX DQ/DQS(RDDQC) : PASS
6014 23:10:57.396119 TX DQ/DQS : PASS
6015 23:10:57.399507 RX DATLAT : PASS
6016 23:10:57.399927 RX DQ/DQS(Engine): PASS
6017 23:10:57.403210 TX OE : NO K
6018 23:10:57.403671 All Pass.
6019 23:10:57.404006
6020 23:10:57.405965 CH 1, Rank 0
6021 23:10:57.406382 SW Impedance : PASS
6022 23:10:57.409291 DUTY Scan : NO K
6023 23:10:57.413019 ZQ Calibration : PASS
6024 23:10:57.413438 Jitter Meter : NO K
6025 23:10:57.416095 CBT Training : PASS
6026 23:10:57.416514 Write leveling : PASS
6027 23:10:57.419160 RX DQS gating : PASS
6028 23:10:57.423025 RX DQ/DQS(RDDQC) : PASS
6029 23:10:57.423614 TX DQ/DQS : PASS
6030 23:10:57.426342 RX DATLAT : PASS
6031 23:10:57.429361 RX DQ/DQS(Engine): PASS
6032 23:10:57.429879 TX OE : NO K
6033 23:10:57.433058 All Pass.
6034 23:10:57.433476
6035 23:10:57.433810 CH 1, Rank 1
6036 23:10:57.435463 SW Impedance : PASS
6037 23:10:57.435882 DUTY Scan : NO K
6038 23:10:57.439131 ZQ Calibration : PASS
6039 23:10:57.442390 Jitter Meter : NO K
6040 23:10:57.442912 CBT Training : PASS
6041 23:10:57.445547 Write leveling : PASS
6042 23:10:57.449041 RX DQS gating : PASS
6043 23:10:57.449564 RX DQ/DQS(RDDQC) : PASS
6044 23:10:57.452070 TX DQ/DQS : PASS
6045 23:10:57.455702 RX DATLAT : PASS
6046 23:10:57.456222 RX DQ/DQS(Engine): PASS
6047 23:10:57.458693 TX OE : NO K
6048 23:10:57.459111 All Pass.
6049 23:10:57.459512
6050 23:10:57.461737 DramC Write-DBI off
6051 23:10:57.464990 PER_BANK_REFRESH: Hybrid Mode
6052 23:10:57.465514 TX_TRACKING: ON
6053 23:10:57.475022 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6054 23:10:57.478199 [FAST_K] Save calibration result to emmc
6055 23:10:57.481952 dramc_set_vcore_voltage set vcore to 650000
6056 23:10:57.484839 Read voltage for 400, 6
6057 23:10:57.485369 Vio18 = 0
6058 23:10:57.488013 Vcore = 650000
6059 23:10:57.488433 Vdram = 0
6060 23:10:57.488766 Vddq = 0
6061 23:10:57.489074 Vmddr = 0
6062 23:10:57.494568 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6063 23:10:57.501357 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6064 23:10:57.501865 MEM_TYPE=3, freq_sel=20
6065 23:10:57.504544 sv_algorithm_assistance_LP4_800
6066 23:10:57.508003 ============ PULL DRAM RESETB DOWN ============
6067 23:10:57.514461 ========== PULL DRAM RESETB DOWN end =========
6068 23:10:57.518133 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6069 23:10:57.521614 ===================================
6070 23:10:57.524217 LPDDR4 DRAM CONFIGURATION
6071 23:10:57.527916 ===================================
6072 23:10:57.528337 EX_ROW_EN[0] = 0x0
6073 23:10:57.530805 EX_ROW_EN[1] = 0x0
6074 23:10:57.531221 LP4Y_EN = 0x0
6075 23:10:57.534339 WORK_FSP = 0x0
6076 23:10:57.534856 WL = 0x2
6077 23:10:57.538128 RL = 0x2
6078 23:10:57.540772 BL = 0x2
6079 23:10:57.541188 RPST = 0x0
6080 23:10:57.544353 RD_PRE = 0x0
6081 23:10:57.544814 WR_PRE = 0x1
6082 23:10:57.547830 WR_PST = 0x0
6083 23:10:57.548355 DBI_WR = 0x0
6084 23:10:57.551021 DBI_RD = 0x0
6085 23:10:57.551583 OTF = 0x1
6086 23:10:57.554176 ===================================
6087 23:10:57.557500 ===================================
6088 23:10:57.560875 ANA top config
6089 23:10:57.564305 ===================================
6090 23:10:57.564831 DLL_ASYNC_EN = 0
6091 23:10:57.567691 ALL_SLAVE_EN = 1
6092 23:10:57.571096 NEW_RANK_MODE = 1
6093 23:10:57.574044 DLL_IDLE_MODE = 1
6094 23:10:57.574563 LP45_APHY_COMB_EN = 1
6095 23:10:57.577380 TX_ODT_DIS = 1
6096 23:10:57.580934 NEW_8X_MODE = 1
6097 23:10:57.583844 ===================================
6098 23:10:57.587030 ===================================
6099 23:10:57.589929 data_rate = 800
6100 23:10:57.593709 CKR = 1
6101 23:10:57.596554 DQ_P2S_RATIO = 4
6102 23:10:57.600504 ===================================
6103 23:10:57.601032 CA_P2S_RATIO = 4
6104 23:10:57.603083 DQ_CA_OPEN = 0
6105 23:10:57.606543 DQ_SEMI_OPEN = 1
6106 23:10:57.610783 CA_SEMI_OPEN = 1
6107 23:10:57.613058 CA_FULL_RATE = 0
6108 23:10:57.616850 DQ_CKDIV4_EN = 0
6109 23:10:57.620077 CA_CKDIV4_EN = 1
6110 23:10:57.620498 CA_PREDIV_EN = 0
6111 23:10:57.623260 PH8_DLY = 0
6112 23:10:57.626505 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6113 23:10:57.629960 DQ_AAMCK_DIV = 0
6114 23:10:57.632887 CA_AAMCK_DIV = 0
6115 23:10:57.636533 CA_ADMCK_DIV = 4
6116 23:10:57.637126 DQ_TRACK_CA_EN = 0
6117 23:10:57.639566 CA_PICK = 800
6118 23:10:57.642843 CA_MCKIO = 400
6119 23:10:57.646291 MCKIO_SEMI = 400
6120 23:10:57.649459 PLL_FREQ = 3016
6121 23:10:57.653511 DQ_UI_PI_RATIO = 32
6122 23:10:57.656489 CA_UI_PI_RATIO = 32
6123 23:10:57.659227 ===================================
6124 23:10:57.663176 ===================================
6125 23:10:57.663750 memory_type:LPDDR4
6126 23:10:57.665773 GP_NUM : 10
6127 23:10:57.669127 SRAM_EN : 1
6128 23:10:57.669643 MD32_EN : 0
6129 23:10:57.672696 ===================================
6130 23:10:57.675658 [ANA_INIT] >>>>>>>>>>>>>>
6131 23:10:57.679241 <<<<<< [CONFIGURE PHASE]: ANA_TX
6132 23:10:57.682496 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6133 23:10:57.685904 ===================================
6134 23:10:57.689235 data_rate = 800,PCW = 0X7400
6135 23:10:57.692593 ===================================
6136 23:10:57.695731 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6137 23:10:57.698664 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6138 23:10:57.712112 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6139 23:10:57.714960 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6140 23:10:57.718160 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6141 23:10:57.721730 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6142 23:10:57.725419 [ANA_INIT] flow start
6143 23:10:57.728257 [ANA_INIT] PLL >>>>>>>>
6144 23:10:57.728676 [ANA_INIT] PLL <<<<<<<<
6145 23:10:57.731890 [ANA_INIT] MIDPI >>>>>>>>
6146 23:10:57.734925 [ANA_INIT] MIDPI <<<<<<<<
6147 23:10:57.738322 [ANA_INIT] DLL >>>>>>>>
6148 23:10:57.738738 [ANA_INIT] flow end
6149 23:10:57.741306 ============ LP4 DIFF to SE enter ============
6150 23:10:57.747972 ============ LP4 DIFF to SE exit ============
6151 23:10:57.748393 [ANA_INIT] <<<<<<<<<<<<<
6152 23:10:57.751174 [Flow] Enable top DCM control >>>>>
6153 23:10:57.754349 [Flow] Enable top DCM control <<<<<
6154 23:10:57.758052 Enable DLL master slave shuffle
6155 23:10:57.764394 ==============================================================
6156 23:10:57.764957 Gating Mode config
6157 23:10:57.771088 ==============================================================
6158 23:10:57.774590 Config description:
6159 23:10:57.784002 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6160 23:10:57.790863 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6161 23:10:57.794174 SELPH_MODE 0: By rank 1: By Phase
6162 23:10:57.800864 ==============================================================
6163 23:10:57.803765 GAT_TRACK_EN = 0
6164 23:10:57.807022 RX_GATING_MODE = 2
6165 23:10:57.810744 RX_GATING_TRACK_MODE = 2
6166 23:10:57.811252 SELPH_MODE = 1
6167 23:10:57.813845 PICG_EARLY_EN = 1
6168 23:10:57.817428 VALID_LAT_VALUE = 1
6169 23:10:57.823747 ==============================================================
6170 23:10:57.826959 Enter into Gating configuration >>>>
6171 23:10:57.830603 Exit from Gating configuration <<<<
6172 23:10:57.834461 Enter into DVFS_PRE_config >>>>>
6173 23:10:57.843610 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6174 23:10:57.847001 Exit from DVFS_PRE_config <<<<<
6175 23:10:57.850338 Enter into PICG configuration >>>>
6176 23:10:57.853351 Exit from PICG configuration <<<<
6177 23:10:57.857165 [RX_INPUT] configuration >>>>>
6178 23:10:57.859774 [RX_INPUT] configuration <<<<<
6179 23:10:57.866483 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6180 23:10:57.870131 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6181 23:10:57.876506 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6182 23:10:57.883167 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6183 23:10:57.889302 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6184 23:10:57.895991 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6185 23:10:57.899488 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6186 23:10:57.902489 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6187 23:10:57.905766 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6188 23:10:57.913170 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6189 23:10:57.915910 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6190 23:10:57.919045 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6191 23:10:57.922801 ===================================
6192 23:10:57.925843 LPDDR4 DRAM CONFIGURATION
6193 23:10:57.928650 ===================================
6194 23:10:57.932165 EX_ROW_EN[0] = 0x0
6195 23:10:57.932579 EX_ROW_EN[1] = 0x0
6196 23:10:57.935077 LP4Y_EN = 0x0
6197 23:10:57.935531 WORK_FSP = 0x0
6198 23:10:57.938546 WL = 0x2
6199 23:10:57.938959 RL = 0x2
6200 23:10:57.942213 BL = 0x2
6201 23:10:57.942625 RPST = 0x0
6202 23:10:57.945511 RD_PRE = 0x0
6203 23:10:57.945924 WR_PRE = 0x1
6204 23:10:57.948687 WR_PST = 0x0
6205 23:10:57.949100 DBI_WR = 0x0
6206 23:10:57.952010 DBI_RD = 0x0
6207 23:10:57.952518 OTF = 0x1
6208 23:10:57.955611 ===================================
6209 23:10:57.962200 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6210 23:10:57.965763 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6211 23:10:57.968380 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6212 23:10:57.971683 ===================================
6213 23:10:57.974814 LPDDR4 DRAM CONFIGURATION
6214 23:10:57.978507 ===================================
6215 23:10:57.982195 EX_ROW_EN[0] = 0x10
6216 23:10:57.982710 EX_ROW_EN[1] = 0x0
6217 23:10:57.984708 LP4Y_EN = 0x0
6218 23:10:57.985121 WORK_FSP = 0x0
6219 23:10:57.987903 WL = 0x2
6220 23:10:57.988319 RL = 0x2
6221 23:10:57.991422 BL = 0x2
6222 23:10:57.991836 RPST = 0x0
6223 23:10:57.994505 RD_PRE = 0x0
6224 23:10:57.994918 WR_PRE = 0x1
6225 23:10:57.997832 WR_PST = 0x0
6226 23:10:57.998245 DBI_WR = 0x0
6227 23:10:58.001155 DBI_RD = 0x0
6228 23:10:58.004553 OTF = 0x1
6229 23:10:58.007727 ===================================
6230 23:10:58.011439 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6231 23:10:58.016429 nWR fixed to 30
6232 23:10:58.019213 [ModeRegInit_LP4] CH0 RK0
6233 23:10:58.019696 [ModeRegInit_LP4] CH0 RK1
6234 23:10:58.022723 [ModeRegInit_LP4] CH1 RK0
6235 23:10:58.026149 [ModeRegInit_LP4] CH1 RK1
6236 23:10:58.026558 match AC timing 19
6237 23:10:58.032621 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6238 23:10:58.035898 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6239 23:10:58.039202 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6240 23:10:58.045669 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6241 23:10:58.048857 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6242 23:10:58.049277 ==
6243 23:10:58.052150 Dram Type= 6, Freq= 0, CH_0, rank 0
6244 23:10:58.055971 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6245 23:10:58.056486 ==
6246 23:10:58.061853 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6247 23:10:58.068904 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6248 23:10:58.072510 [CA 0] Center 36 (8~64) winsize 57
6249 23:10:58.075588 [CA 1] Center 36 (8~64) winsize 57
6250 23:10:58.079035 [CA 2] Center 36 (8~64) winsize 57
6251 23:10:58.082492 [CA 3] Center 36 (8~64) winsize 57
6252 23:10:58.084938 [CA 4] Center 36 (8~64) winsize 57
6253 23:10:58.088417 [CA 5] Center 36 (8~64) winsize 57
6254 23:10:58.088941
6255 23:10:58.091890 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6256 23:10:58.092308
6257 23:10:58.094919 [CATrainingPosCal] consider 1 rank data
6258 23:10:58.098286 u2DelayCellTimex100 = 270/100 ps
6259 23:10:58.101421 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6260 23:10:58.105017 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6261 23:10:58.108474 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6262 23:10:58.111474 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6263 23:10:58.115698 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6264 23:10:58.118303 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6265 23:10:58.118714
6266 23:10:58.124766 CA PerBit enable=1, Macro0, CA PI delay=36
6267 23:10:58.125180
6268 23:10:58.125505 [CBTSetCACLKResult] CA Dly = 36
6269 23:10:58.127974 CS Dly: 1 (0~32)
6270 23:10:58.128380 ==
6271 23:10:58.131085 Dram Type= 6, Freq= 0, CH_0, rank 1
6272 23:10:58.134748 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6273 23:10:58.135240 ==
6274 23:10:58.141200 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6275 23:10:58.147670 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6276 23:10:58.150988 [CA 0] Center 36 (8~64) winsize 57
6277 23:10:58.154151 [CA 1] Center 36 (8~64) winsize 57
6278 23:10:58.157501 [CA 2] Center 36 (8~64) winsize 57
6279 23:10:58.161488 [CA 3] Center 36 (8~64) winsize 57
6280 23:10:58.164047 [CA 4] Center 36 (8~64) winsize 57
6281 23:10:58.164467 [CA 5] Center 36 (8~64) winsize 57
6282 23:10:58.167265
6283 23:10:58.170671 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6284 23:10:58.171091
6285 23:10:58.174099 [CATrainingPosCal] consider 2 rank data
6286 23:10:58.177151 u2DelayCellTimex100 = 270/100 ps
6287 23:10:58.180951 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6288 23:10:58.184343 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6289 23:10:58.186980 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6290 23:10:58.190864 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6291 23:10:58.194214 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6292 23:10:58.197424 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6293 23:10:58.197945
6294 23:10:58.200271 CA PerBit enable=1, Macro0, CA PI delay=36
6295 23:10:58.204082
6296 23:10:58.204497 [CBTSetCACLKResult] CA Dly = 36
6297 23:10:58.207027 CS Dly: 1 (0~32)
6298 23:10:58.207626
6299 23:10:58.210565 ----->DramcWriteLeveling(PI) begin...
6300 23:10:58.210988 ==
6301 23:10:58.213475 Dram Type= 6, Freq= 0, CH_0, rank 0
6302 23:10:58.216728 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6303 23:10:58.217149 ==
6304 23:10:58.220431 Write leveling (Byte 0): 40 => 8
6305 23:10:58.223675 Write leveling (Byte 1): 40 => 8
6306 23:10:58.226895 DramcWriteLeveling(PI) end<-----
6307 23:10:58.227324
6308 23:10:58.227724 ==
6309 23:10:58.230586 Dram Type= 6, Freq= 0, CH_0, rank 0
6310 23:10:58.234096 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6311 23:10:58.236304 ==
6312 23:10:58.236772 [Gating] SW mode calibration
6313 23:10:58.243658 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6314 23:10:58.249899 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6315 23:10:58.253267 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6316 23:10:58.259893 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6317 23:10:58.262857 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6318 23:10:58.266205 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6319 23:10:58.272809 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6320 23:10:58.276552 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6321 23:10:58.279472 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6322 23:10:58.286760 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6323 23:10:58.290226 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6324 23:10:58.292925 Total UI for P1: 0, mck2ui 16
6325 23:10:58.295825 best dqsien dly found for B0: ( 0, 14, 24)
6326 23:10:58.299617 Total UI for P1: 0, mck2ui 16
6327 23:10:58.302683 best dqsien dly found for B1: ( 0, 14, 24)
6328 23:10:58.305821 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6329 23:10:58.309534 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6330 23:10:58.310023
6331 23:10:58.312466 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6332 23:10:58.318948 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6333 23:10:58.319395 [Gating] SW calibration Done
6334 23:10:58.319739 ==
6335 23:10:58.322039 Dram Type= 6, Freq= 0, CH_0, rank 0
6336 23:10:58.328824 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6337 23:10:58.329359 ==
6338 23:10:58.329936 RX Vref Scan: 0
6339 23:10:58.330277
6340 23:10:58.332022 RX Vref 0 -> 0, step: 1
6341 23:10:58.332438
6342 23:10:58.335898 RX Delay -410 -> 252, step: 16
6343 23:10:58.338847 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6344 23:10:58.341890 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6345 23:10:58.349023 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6346 23:10:58.352010 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6347 23:10:58.355457 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6348 23:10:58.358681 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6349 23:10:58.365200 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6350 23:10:58.368901 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6351 23:10:58.372369 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6352 23:10:58.375192 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6353 23:10:58.381614 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6354 23:10:58.384988 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6355 23:10:58.388319 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6356 23:10:58.394864 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6357 23:10:58.398439 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6358 23:10:58.401429 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6359 23:10:58.401848 ==
6360 23:10:58.404752 Dram Type= 6, Freq= 0, CH_0, rank 0
6361 23:10:58.407581 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6362 23:10:58.411252 ==
6363 23:10:58.411756 DQS Delay:
6364 23:10:58.412088 DQS0 = 35, DQS1 = 51
6365 23:10:58.414438 DQM Delay:
6366 23:10:58.414849 DQM0 = 5, DQM1 = 11
6367 23:10:58.417441 DQ Delay:
6368 23:10:58.417863 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6369 23:10:58.420887 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6370 23:10:58.424646 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6371 23:10:58.427861 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6372 23:10:58.428278
6373 23:10:58.428602
6374 23:10:58.428902 ==
6375 23:10:58.431018 Dram Type= 6, Freq= 0, CH_0, rank 0
6376 23:10:58.437683 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6377 23:10:58.438140 ==
6378 23:10:58.438480
6379 23:10:58.438801
6380 23:10:58.441457 TX Vref Scan disable
6381 23:10:58.441884 == TX Byte 0 ==
6382 23:10:58.444121 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6383 23:10:58.450709 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6384 23:10:58.451398 == TX Byte 1 ==
6385 23:10:58.454345 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6386 23:10:58.461244 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6387 23:10:58.461746 ==
6388 23:10:58.464051 Dram Type= 6, Freq= 0, CH_0, rank 0
6389 23:10:58.467092 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6390 23:10:58.467574 ==
6391 23:10:58.467910
6392 23:10:58.468215
6393 23:10:58.470431 TX Vref Scan disable
6394 23:10:58.470872 == TX Byte 0 ==
6395 23:10:58.473853 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6396 23:10:58.480275 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6397 23:10:58.480717 == TX Byte 1 ==
6398 23:10:58.483699 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6399 23:10:58.490156 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6400 23:10:58.490669
6401 23:10:58.490997 [DATLAT]
6402 23:10:58.491301 Freq=400, CH0 RK0
6403 23:10:58.491648
6404 23:10:58.493796 DATLAT Default: 0xf
6405 23:10:58.497303 0, 0xFFFF, sum = 0
6406 23:10:58.497726 1, 0xFFFF, sum = 0
6407 23:10:58.500319 2, 0xFFFF, sum = 0
6408 23:10:58.500737 3, 0xFFFF, sum = 0
6409 23:10:58.503510 4, 0xFFFF, sum = 0
6410 23:10:58.503931 5, 0xFFFF, sum = 0
6411 23:10:58.506877 6, 0xFFFF, sum = 0
6412 23:10:58.507307 7, 0xFFFF, sum = 0
6413 23:10:58.509925 8, 0xFFFF, sum = 0
6414 23:10:58.510342 9, 0xFFFF, sum = 0
6415 23:10:58.513577 10, 0xFFFF, sum = 0
6416 23:10:58.513993 11, 0xFFFF, sum = 0
6417 23:10:58.516546 12, 0xFFFF, sum = 0
6418 23:10:58.517203 13, 0x0, sum = 1
6419 23:10:58.520070 14, 0x0, sum = 2
6420 23:10:58.520484 15, 0x0, sum = 3
6421 23:10:58.523399 16, 0x0, sum = 4
6422 23:10:58.523817 best_step = 14
6423 23:10:58.524140
6424 23:10:58.524486 ==
6425 23:10:58.526723 Dram Type= 6, Freq= 0, CH_0, rank 0
6426 23:10:58.533316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6427 23:10:58.533755 ==
6428 23:10:58.534092 RX Vref Scan: 1
6429 23:10:58.534398
6430 23:10:58.536723 RX Vref 0 -> 0, step: 1
6431 23:10:58.537133
6432 23:10:58.539721 RX Delay -343 -> 252, step: 8
6433 23:10:58.540131
6434 23:10:58.543912 Set Vref, RX VrefLevel [Byte0]: 51
6435 23:10:58.546332 [Byte1]: 48
6436 23:10:58.546741
6437 23:10:58.550350 Final RX Vref Byte 0 = 51 to rank0
6438 23:10:58.552739 Final RX Vref Byte 1 = 48 to rank0
6439 23:10:58.556127 Final RX Vref Byte 0 = 51 to rank1
6440 23:10:58.560199 Final RX Vref Byte 1 = 48 to rank1==
6441 23:10:58.562746 Dram Type= 6, Freq= 0, CH_0, rank 0
6442 23:10:58.569102 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6443 23:10:58.569516 ==
6444 23:10:58.569839 DQS Delay:
6445 23:10:58.572706 DQS0 = 40, DQS1 = 60
6446 23:10:58.573194 DQM Delay:
6447 23:10:58.573521 DQM0 = 6, DQM1 = 18
6448 23:10:58.575526 DQ Delay:
6449 23:10:58.579921 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =0
6450 23:10:58.580335 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =12
6451 23:10:58.582253 DQ8 =8, DQ9 =0, DQ10 =20, DQ11 =12
6452 23:10:58.585614 DQ12 =24, DQ13 =24, DQ14 =28, DQ15 =28
6453 23:10:58.586043
6454 23:10:58.589087
6455 23:10:58.595561 [DQSOSCAuto] RK0, (LSB)MR18= 0x8c80, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 392 ps
6456 23:10:58.598910 CH0 RK0: MR19=C0C, MR18=8C80
6457 23:10:58.605459 CH0_RK0: MR19=0xC0C, MR18=0x8C80, DQSOSC=392, MR23=63, INC=384, DEC=256
6458 23:10:58.605955 ==
6459 23:10:58.608666 Dram Type= 6, Freq= 0, CH_0, rank 1
6460 23:10:58.611909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6461 23:10:58.612327 ==
6462 23:10:58.615828 [Gating] SW mode calibration
6463 23:10:58.622452 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6464 23:10:58.628840 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6465 23:10:58.632609 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6466 23:10:58.635215 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6467 23:10:58.641771 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6468 23:10:58.645048 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6469 23:10:58.648224 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6470 23:10:58.655156 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6471 23:10:58.658308 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6472 23:10:58.661427 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6473 23:10:58.668435 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6474 23:10:58.668933 Total UI for P1: 0, mck2ui 16
6475 23:10:58.674701 best dqsien dly found for B0: ( 0, 14, 24)
6476 23:10:58.675114 Total UI for P1: 0, mck2ui 16
6477 23:10:58.681357 best dqsien dly found for B1: ( 0, 14, 24)
6478 23:10:58.685370 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6479 23:10:58.688037 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6480 23:10:58.688454
6481 23:10:58.691825 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6482 23:10:58.695135 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6483 23:10:58.698144 [Gating] SW calibration Done
6484 23:10:58.698557 ==
6485 23:10:58.701323 Dram Type= 6, Freq= 0, CH_0, rank 1
6486 23:10:58.704444 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6487 23:10:58.704974 ==
6488 23:10:58.707984 RX Vref Scan: 0
6489 23:10:58.708393
6490 23:10:58.708716 RX Vref 0 -> 0, step: 1
6491 23:10:58.709017
6492 23:10:58.711272 RX Delay -410 -> 252, step: 16
6493 23:10:58.717502 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6494 23:10:58.721496 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6495 23:10:58.724145 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6496 23:10:58.728033 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6497 23:10:58.734622 iDelay=230, Bit 4, Center -19 (-266 ~ 229) 496
6498 23:10:58.737370 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6499 23:10:58.740858 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6500 23:10:58.743768 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6501 23:10:58.750413 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6502 23:10:58.753952 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6503 23:10:58.757544 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6504 23:10:58.763553 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6505 23:10:58.767590 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6506 23:10:58.770307 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6507 23:10:58.773489 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6508 23:10:58.780007 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6509 23:10:58.780421 ==
6510 23:10:58.783345 Dram Type= 6, Freq= 0, CH_0, rank 1
6511 23:10:58.786452 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6512 23:10:58.786862 ==
6513 23:10:58.787271 DQS Delay:
6514 23:10:58.790215 DQS0 = 35, DQS1 = 51
6515 23:10:58.790624 DQM Delay:
6516 23:10:58.793423 DQM0 = 8, DQM1 = 10
6517 23:10:58.793890 DQ Delay:
6518 23:10:58.796745 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =0
6519 23:10:58.799819 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6520 23:10:58.803005 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6521 23:10:58.806316 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6522 23:10:58.806733
6523 23:10:58.807060
6524 23:10:58.807403 ==
6525 23:10:58.809763 Dram Type= 6, Freq= 0, CH_0, rank 1
6526 23:10:58.812946 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6527 23:10:58.813490 ==
6528 23:10:58.813955
6529 23:10:58.816974
6530 23:10:58.817430 TX Vref Scan disable
6531 23:10:58.819505 == TX Byte 0 ==
6532 23:10:58.823018 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6533 23:10:58.826114 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6534 23:10:58.829898 == TX Byte 1 ==
6535 23:10:58.833065 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6536 23:10:58.835886 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6537 23:10:58.836304 ==
6538 23:10:58.839928 Dram Type= 6, Freq= 0, CH_0, rank 1
6539 23:10:58.842752 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6540 23:10:58.846118 ==
6541 23:10:58.846534
6542 23:10:58.846867
6543 23:10:58.847172 TX Vref Scan disable
6544 23:10:58.849080 == TX Byte 0 ==
6545 23:10:58.853400 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6546 23:10:58.855649 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6547 23:10:58.859005 == TX Byte 1 ==
6548 23:10:58.863204 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6549 23:10:58.865561 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6550 23:10:58.865991
6551 23:10:58.869216 [DATLAT]
6552 23:10:58.869636 Freq=400, CH0 RK1
6553 23:10:58.869971
6554 23:10:58.872782 DATLAT Default: 0xe
6555 23:10:58.873197 0, 0xFFFF, sum = 0
6556 23:10:58.875429 1, 0xFFFF, sum = 0
6557 23:10:58.876006 2, 0xFFFF, sum = 0
6558 23:10:58.879516 3, 0xFFFF, sum = 0
6559 23:10:58.880094 4, 0xFFFF, sum = 0
6560 23:10:58.882277 5, 0xFFFF, sum = 0
6561 23:10:58.882724 6, 0xFFFF, sum = 0
6562 23:10:58.885380 7, 0xFFFF, sum = 0
6563 23:10:58.885828 8, 0xFFFF, sum = 0
6564 23:10:58.889095 9, 0xFFFF, sum = 0
6565 23:10:58.889654 10, 0xFFFF, sum = 0
6566 23:10:58.892510 11, 0xFFFF, sum = 0
6567 23:10:58.893034 12, 0xFFFF, sum = 0
6568 23:10:58.895597 13, 0x0, sum = 1
6569 23:10:58.896019 14, 0x0, sum = 2
6570 23:10:58.898438 15, 0x0, sum = 3
6571 23:10:58.898858 16, 0x0, sum = 4
6572 23:10:58.901865 best_step = 14
6573 23:10:58.902280
6574 23:10:58.902611 ==
6575 23:10:58.905280 Dram Type= 6, Freq= 0, CH_0, rank 1
6576 23:10:58.908373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6577 23:10:58.908792 ==
6578 23:10:58.911728 RX Vref Scan: 0
6579 23:10:58.912142
6580 23:10:58.912470 RX Vref 0 -> 0, step: 1
6581 23:10:58.915536
6582 23:10:58.916098 RX Delay -343 -> 252, step: 8
6583 23:10:58.923296 iDelay=209, Bit 0, Center -36 (-271 ~ 200) 472
6584 23:10:58.927560 iDelay=209, Bit 1, Center -32 (-271 ~ 208) 480
6585 23:10:58.930241 iDelay=209, Bit 2, Center -40 (-279 ~ 200) 480
6586 23:10:58.936458 iDelay=209, Bit 3, Center -36 (-271 ~ 200) 472
6587 23:10:58.939875 iDelay=209, Bit 4, Center -32 (-271 ~ 208) 480
6588 23:10:58.943846 iDelay=209, Bit 5, Center -44 (-279 ~ 192) 472
6589 23:10:58.946833 iDelay=209, Bit 6, Center -28 (-263 ~ 208) 472
6590 23:10:58.953770 iDelay=209, Bit 7, Center -28 (-263 ~ 208) 472
6591 23:10:58.956268 iDelay=209, Bit 8, Center -56 (-295 ~ 184) 480
6592 23:10:58.959763 iDelay=209, Bit 9, Center -60 (-303 ~ 184) 488
6593 23:10:58.962691 iDelay=209, Bit 10, Center -44 (-287 ~ 200) 488
6594 23:10:58.969784 iDelay=209, Bit 11, Center -52 (-287 ~ 184) 472
6595 23:10:58.972450 iDelay=209, Bit 12, Center -40 (-279 ~ 200) 480
6596 23:10:58.975877 iDelay=209, Bit 13, Center -40 (-279 ~ 200) 480
6597 23:10:58.982563 iDelay=209, Bit 14, Center -32 (-271 ~ 208) 480
6598 23:10:58.986124 iDelay=209, Bit 15, Center -40 (-279 ~ 200) 480
6599 23:10:58.986545 ==
6600 23:10:58.989154 Dram Type= 6, Freq= 0, CH_0, rank 1
6601 23:10:58.992283 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6602 23:10:58.992708 ==
6603 23:10:58.995481 DQS Delay:
6604 23:10:58.995900 DQS0 = 44, DQS1 = 60
6605 23:10:58.996233 DQM Delay:
6606 23:10:58.998935 DQM0 = 9, DQM1 = 14
6607 23:10:58.999347 DQ Delay:
6608 23:10:59.001927 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =8
6609 23:10:59.005547 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =16
6610 23:10:59.008680 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6611 23:10:59.011899 DQ12 =20, DQ13 =20, DQ14 =28, DQ15 =20
6612 23:10:59.012320
6613 23:10:59.012648
6614 23:10:59.021874 [DQSOSCAuto] RK1, (LSB)MR18= 0x8780, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 392 ps
6615 23:10:59.022387 CH0 RK1: MR19=C0C, MR18=8780
6616 23:10:59.028495 CH0_RK1: MR19=0xC0C, MR18=0x8780, DQSOSC=392, MR23=63, INC=384, DEC=256
6617 23:10:59.032323 [RxdqsGatingPostProcess] freq 400
6618 23:10:59.038998 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6619 23:10:59.041776 best DQS0 dly(2T, 0.5T) = (0, 10)
6620 23:10:59.045475 best DQS1 dly(2T, 0.5T) = (0, 10)
6621 23:10:59.048778 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6622 23:10:59.052222 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6623 23:10:59.055339 best DQS0 dly(2T, 0.5T) = (0, 10)
6624 23:10:59.055900 best DQS1 dly(2T, 0.5T) = (0, 10)
6625 23:10:59.058181 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6626 23:10:59.062077 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6627 23:10:59.065667 Pre-setting of DQS Precalculation
6628 23:10:59.071263 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6629 23:10:59.071727 ==
6630 23:10:59.074806 Dram Type= 6, Freq= 0, CH_1, rank 0
6631 23:10:59.079028 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6632 23:10:59.079481 ==
6633 23:10:59.084867 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6634 23:10:59.091445 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6635 23:10:59.095006 [CA 0] Center 36 (8~64) winsize 57
6636 23:10:59.097853 [CA 1] Center 36 (8~64) winsize 57
6637 23:10:59.101619 [CA 2] Center 36 (8~64) winsize 57
6638 23:10:59.104726 [CA 3] Center 36 (8~64) winsize 57
6639 23:10:59.105147 [CA 4] Center 36 (8~64) winsize 57
6640 23:10:59.107716 [CA 5] Center 36 (8~64) winsize 57
6641 23:10:59.108136
6642 23:10:59.114252 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6643 23:10:59.114670
6644 23:10:59.118154 [CATrainingPosCal] consider 1 rank data
6645 23:10:59.120815 u2DelayCellTimex100 = 270/100 ps
6646 23:10:59.124234 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6647 23:10:59.127978 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6648 23:10:59.130976 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6649 23:10:59.133983 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6650 23:10:59.137720 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6651 23:10:59.141157 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6652 23:10:59.141575
6653 23:10:59.144022 CA PerBit enable=1, Macro0, CA PI delay=36
6654 23:10:59.144475
6655 23:10:59.147146 [CBTSetCACLKResult] CA Dly = 36
6656 23:10:59.150600 CS Dly: 1 (0~32)
6657 23:10:59.151052 ==
6658 23:10:59.154390 Dram Type= 6, Freq= 0, CH_1, rank 1
6659 23:10:59.157528 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6660 23:10:59.157948 ==
6661 23:10:59.163810 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6662 23:10:59.170295 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6663 23:10:59.173641 [CA 0] Center 36 (8~64) winsize 57
6664 23:10:59.176520 [CA 1] Center 36 (8~64) winsize 57
6665 23:10:59.179984 [CA 2] Center 36 (8~64) winsize 57
6666 23:10:59.180403 [CA 3] Center 36 (8~64) winsize 57
6667 23:10:59.183411 [CA 4] Center 36 (8~64) winsize 57
6668 23:10:59.186590 [CA 5] Center 36 (8~64) winsize 57
6669 23:10:59.187011
6670 23:10:59.193368 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6671 23:10:59.193796
6672 23:10:59.196436 [CATrainingPosCal] consider 2 rank data
6673 23:10:59.200071 u2DelayCellTimex100 = 270/100 ps
6674 23:10:59.203446 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6675 23:10:59.206745 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6676 23:10:59.209703 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6677 23:10:59.213607 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6678 23:10:59.217117 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6679 23:10:59.219972 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6680 23:10:59.220548
6681 23:10:59.222757 CA PerBit enable=1, Macro0, CA PI delay=36
6682 23:10:59.223174
6683 23:10:59.226050 [CBTSetCACLKResult] CA Dly = 36
6684 23:10:59.229870 CS Dly: 1 (0~32)
6685 23:10:59.230285
6686 23:10:59.232853 ----->DramcWriteLeveling(PI) begin...
6687 23:10:59.233287 ==
6688 23:10:59.235793 Dram Type= 6, Freq= 0, CH_1, rank 0
6689 23:10:59.239341 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6690 23:10:59.239803 ==
6691 23:10:59.242997 Write leveling (Byte 0): 40 => 8
6692 23:10:59.245927 Write leveling (Byte 1): 40 => 8
6693 23:10:59.249402 DramcWriteLeveling(PI) end<-----
6694 23:10:59.249882
6695 23:10:59.250218 ==
6696 23:10:59.252606 Dram Type= 6, Freq= 0, CH_1, rank 0
6697 23:10:59.255675 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6698 23:10:59.256094 ==
6699 23:10:59.258886 [Gating] SW mode calibration
6700 23:10:59.265473 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6701 23:10:59.272666 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6702 23:10:59.275442 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6703 23:10:59.282596 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6704 23:10:59.285711 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6705 23:10:59.288718 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6706 23:10:59.295182 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6707 23:10:59.298877 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6708 23:10:59.301796 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6709 23:10:59.308367 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6710 23:10:59.312151 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6711 23:10:59.315299 Total UI for P1: 0, mck2ui 16
6712 23:10:59.318275 best dqsien dly found for B0: ( 0, 14, 24)
6713 23:10:59.321795 Total UI for P1: 0, mck2ui 16
6714 23:10:59.324818 best dqsien dly found for B1: ( 0, 14, 24)
6715 23:10:59.329135 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6716 23:10:59.331539 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6717 23:10:59.331961
6718 23:10:59.334921 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6719 23:10:59.338861 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6720 23:10:59.342042 [Gating] SW calibration Done
6721 23:10:59.342591 ==
6722 23:10:59.344746 Dram Type= 6, Freq= 0, CH_1, rank 0
6723 23:10:59.348242 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6724 23:10:59.351320 ==
6725 23:10:59.351889 RX Vref Scan: 0
6726 23:10:59.352227
6727 23:10:59.355508 RX Vref 0 -> 0, step: 1
6728 23:10:59.356019
6729 23:10:59.358023 RX Delay -410 -> 252, step: 16
6730 23:10:59.362089 iDelay=230, Bit 0, Center -19 (-266 ~ 229) 496
6731 23:10:59.364270 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6732 23:10:59.371131 iDelay=230, Bit 2, Center -43 (-282 ~ 197) 480
6733 23:10:59.374332 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6734 23:10:59.377712 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6735 23:10:59.380990 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6736 23:10:59.388066 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6737 23:10:59.390969 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6738 23:10:59.394239 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6739 23:10:59.397244 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6740 23:10:59.404442 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6741 23:10:59.407877 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6742 23:10:59.410738 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6743 23:10:59.414111 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6744 23:10:59.420283 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6745 23:10:59.423452 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6746 23:10:59.423917 ==
6747 23:10:59.427110 Dram Type= 6, Freq= 0, CH_1, rank 0
6748 23:10:59.430216 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6749 23:10:59.430771 ==
6750 23:10:59.433489 DQS Delay:
6751 23:10:59.434105 DQS0 = 43, DQS1 = 51
6752 23:10:59.436900 DQM Delay:
6753 23:10:59.437362 DQM0 = 13, DQM1 = 13
6754 23:10:59.440163 DQ Delay:
6755 23:10:59.440726 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =8
6756 23:10:59.443643 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6757 23:10:59.446999 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6758 23:10:59.450011 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =16
6759 23:10:59.450572
6760 23:10:59.450934
6761 23:10:59.451270 ==
6762 23:10:59.453552 Dram Type= 6, Freq= 0, CH_1, rank 0
6763 23:10:59.460248 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6764 23:10:59.460797 ==
6765 23:10:59.461165
6766 23:10:59.461501
6767 23:10:59.461821 TX Vref Scan disable
6768 23:10:59.463155 == TX Byte 0 ==
6769 23:10:59.466756 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6770 23:10:59.470368 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6771 23:10:59.473171 == TX Byte 1 ==
6772 23:10:59.476696 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6773 23:10:59.479770 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6774 23:10:59.483223 ==
6775 23:10:59.486693 Dram Type= 6, Freq= 0, CH_1, rank 0
6776 23:10:59.489936 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6777 23:10:59.490503 ==
6778 23:10:59.490873
6779 23:10:59.491214
6780 23:10:59.492836 TX Vref Scan disable
6781 23:10:59.493316 == TX Byte 0 ==
6782 23:10:59.496015 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6783 23:10:59.502844 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6784 23:10:59.503426 == TX Byte 1 ==
6785 23:10:59.506280 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6786 23:10:59.512463 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6787 23:10:59.512986
6788 23:10:59.513323 [DATLAT]
6789 23:10:59.513634 Freq=400, CH1 RK0
6790 23:10:59.516244
6791 23:10:59.516757 DATLAT Default: 0xf
6792 23:10:59.519398 0, 0xFFFF, sum = 0
6793 23:10:59.519927 1, 0xFFFF, sum = 0
6794 23:10:59.522332 2, 0xFFFF, sum = 0
6795 23:10:59.522753 3, 0xFFFF, sum = 0
6796 23:10:59.525455 4, 0xFFFF, sum = 0
6797 23:10:59.525877 5, 0xFFFF, sum = 0
6798 23:10:59.528868 6, 0xFFFF, sum = 0
6799 23:10:59.529290 7, 0xFFFF, sum = 0
6800 23:10:59.532122 8, 0xFFFF, sum = 0
6801 23:10:59.532546 9, 0xFFFF, sum = 0
6802 23:10:59.536028 10, 0xFFFF, sum = 0
6803 23:10:59.536451 11, 0xFFFF, sum = 0
6804 23:10:59.539017 12, 0xFFFF, sum = 0
6805 23:10:59.539493 13, 0x0, sum = 1
6806 23:10:59.542144 14, 0x0, sum = 2
6807 23:10:59.542667 15, 0x0, sum = 3
6808 23:10:59.545525 16, 0x0, sum = 4
6809 23:10:59.545947 best_step = 14
6810 23:10:59.546278
6811 23:10:59.546584 ==
6812 23:10:59.548409 Dram Type= 6, Freq= 0, CH_1, rank 0
6813 23:10:59.555747 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6814 23:10:59.556270 ==
6815 23:10:59.556604 RX Vref Scan: 1
6816 23:10:59.556909
6817 23:10:59.558797 RX Vref 0 -> 0, step: 1
6818 23:10:59.559315
6819 23:10:59.562167 RX Delay -343 -> 252, step: 8
6820 23:10:59.562690
6821 23:10:59.565878 Set Vref, RX VrefLevel [Byte0]: 51
6822 23:10:59.568045 [Byte1]: 48
6823 23:10:59.571649
6824 23:10:59.572168 Final RX Vref Byte 0 = 51 to rank0
6825 23:10:59.574750 Final RX Vref Byte 1 = 48 to rank0
6826 23:10:59.578673 Final RX Vref Byte 0 = 51 to rank1
6827 23:10:59.582589 Final RX Vref Byte 1 = 48 to rank1==
6828 23:10:59.585218 Dram Type= 6, Freq= 0, CH_1, rank 0
6829 23:10:59.592587 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6830 23:10:59.593012 ==
6831 23:10:59.593346 DQS Delay:
6832 23:10:59.595933 DQS0 = 44, DQS1 = 56
6833 23:10:59.596456 DQM Delay:
6834 23:10:59.596788 DQM0 = 11, DQM1 = 14
6835 23:10:59.597855 DQ Delay:
6836 23:10:59.601435 DQ0 =20, DQ1 =4, DQ2 =0, DQ3 =12
6837 23:10:59.601956 DQ4 =8, DQ5 =20, DQ6 =24, DQ7 =4
6838 23:10:59.605105 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6839 23:10:59.608039 DQ12 =24, DQ13 =24, DQ14 =20, DQ15 =20
6840 23:10:59.608454
6841 23:10:59.611612
6842 23:10:59.617833 [DQSOSCAuto] RK0, (LSB)MR18= 0x6289, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 397 ps
6843 23:10:59.621480 CH1 RK0: MR19=C0C, MR18=6289
6844 23:10:59.627931 CH1_RK0: MR19=0xC0C, MR18=0x6289, DQSOSC=392, MR23=63, INC=384, DEC=256
6845 23:10:59.628454 ==
6846 23:10:59.631920 Dram Type= 6, Freq= 0, CH_1, rank 1
6847 23:10:59.634657 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6848 23:10:59.635179 ==
6849 23:10:59.637835 [Gating] SW mode calibration
6850 23:10:59.645179 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6851 23:10:59.650992 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6852 23:10:59.654670 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6853 23:10:59.657931 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6854 23:10:59.664103 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6855 23:10:59.668090 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6856 23:10:59.670625 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6857 23:10:59.677544 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6858 23:10:59.680918 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6859 23:10:59.684084 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6860 23:10:59.690166 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6861 23:10:59.693913 Total UI for P1: 0, mck2ui 16
6862 23:10:59.696945 best dqsien dly found for B0: ( 0, 14, 24)
6863 23:10:59.697476 Total UI for P1: 0, mck2ui 16
6864 23:10:59.704145 best dqsien dly found for B1: ( 0, 14, 24)
6865 23:10:59.707165 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6866 23:10:59.711126 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6867 23:10:59.711699
6868 23:10:59.713611 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6869 23:10:59.716429 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6870 23:10:59.720056 [Gating] SW calibration Done
6871 23:10:59.720474 ==
6872 23:10:59.722919 Dram Type= 6, Freq= 0, CH_1, rank 1
6873 23:10:59.726191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6874 23:10:59.726612 ==
6875 23:10:59.729763 RX Vref Scan: 0
6876 23:10:59.730280
6877 23:10:59.732940 RX Vref 0 -> 0, step: 1
6878 23:10:59.733403
6879 23:10:59.733915 RX Delay -410 -> 252, step: 16
6880 23:10:59.740547 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6881 23:10:59.742961 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6882 23:10:59.746601 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6883 23:10:59.753024 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6884 23:10:59.756323 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6885 23:10:59.759603 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6886 23:10:59.762999 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6887 23:10:59.769947 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6888 23:10:59.772791 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6889 23:10:59.775866 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6890 23:10:59.779177 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6891 23:10:59.786542 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6892 23:10:59.790000 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6893 23:10:59.792437 iDelay=230, Bit 13, Center -19 (-266 ~ 229) 496
6894 23:10:59.799028 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6895 23:10:59.802048 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6896 23:10:59.802569 ==
6897 23:10:59.806323 Dram Type= 6, Freq= 0, CH_1, rank 1
6898 23:10:59.808565 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6899 23:10:59.808988 ==
6900 23:10:59.812032 DQS Delay:
6901 23:10:59.812541 DQS0 = 43, DQS1 = 51
6902 23:10:59.812877 DQM Delay:
6903 23:10:59.815133 DQM0 = 9, DQM1 = 14
6904 23:10:59.815717 DQ Delay:
6905 23:10:59.819160 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6906 23:10:59.821517 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6907 23:10:59.824946 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6908 23:10:59.827942 DQ12 =24, DQ13 =32, DQ14 =16, DQ15 =24
6909 23:10:59.828359
6910 23:10:59.828687
6911 23:10:59.828993 ==
6912 23:10:59.831550 Dram Type= 6, Freq= 0, CH_1, rank 1
6913 23:10:59.835178 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6914 23:10:59.838480 ==
6915 23:10:59.838997
6916 23:10:59.839331
6917 23:10:59.839703 TX Vref Scan disable
6918 23:10:59.842818 == TX Byte 0 ==
6919 23:10:59.844580 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6920 23:10:59.848299 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6921 23:10:59.851469 == TX Byte 1 ==
6922 23:10:59.854783 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6923 23:10:59.858055 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6924 23:10:59.858575 ==
6925 23:10:59.861433 Dram Type= 6, Freq= 0, CH_1, rank 1
6926 23:10:59.867919 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6927 23:10:59.868443 ==
6928 23:10:59.868779
6929 23:10:59.869087
6930 23:10:59.869379 TX Vref Scan disable
6931 23:10:59.871260 == TX Byte 0 ==
6932 23:10:59.874721 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6933 23:10:59.878076 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6934 23:10:59.881346 == TX Byte 1 ==
6935 23:10:59.885153 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6936 23:10:59.887636 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6937 23:10:59.888285
6938 23:10:59.891078 [DATLAT]
6939 23:10:59.891869 Freq=400, CH1 RK1
6940 23:10:59.892429
6941 23:10:59.894351 DATLAT Default: 0xe
6942 23:10:59.894855 0, 0xFFFF, sum = 0
6943 23:10:59.897846 1, 0xFFFF, sum = 0
6944 23:10:59.898428 2, 0xFFFF, sum = 0
6945 23:10:59.901034 3, 0xFFFF, sum = 0
6946 23:10:59.901705 4, 0xFFFF, sum = 0
6947 23:10:59.904259 5, 0xFFFF, sum = 0
6948 23:10:59.904679 6, 0xFFFF, sum = 0
6949 23:10:59.907422 7, 0xFFFF, sum = 0
6950 23:10:59.907855 8, 0xFFFF, sum = 0
6951 23:10:59.910693 9, 0xFFFF, sum = 0
6952 23:10:59.911129 10, 0xFFFF, sum = 0
6953 23:10:59.914215 11, 0xFFFF, sum = 0
6954 23:10:59.917533 12, 0xFFFF, sum = 0
6955 23:10:59.918265 13, 0x0, sum = 1
6956 23:10:59.920515 14, 0x0, sum = 2
6957 23:10:59.920940 15, 0x0, sum = 3
6958 23:10:59.921278 16, 0x0, sum = 4
6959 23:10:59.923661 best_step = 14
6960 23:10:59.924081
6961 23:10:59.924411 ==
6962 23:10:59.927349 Dram Type= 6, Freq= 0, CH_1, rank 1
6963 23:10:59.930178 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6964 23:10:59.930725 ==
6965 23:10:59.934174 RX Vref Scan: 0
6966 23:10:59.934592
6967 23:10:59.937117 RX Vref 0 -> 0, step: 1
6968 23:10:59.937534
6969 23:10:59.937866 RX Delay -343 -> 252, step: 8
6970 23:10:59.945706 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6971 23:10:59.948951 iDelay=217, Bit 1, Center -40 (-287 ~ 208) 496
6972 23:10:59.952111 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
6973 23:10:59.959057 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6974 23:10:59.962332 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6975 23:10:59.965581 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6976 23:10:59.969260 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6977 23:10:59.975695 iDelay=217, Bit 7, Center -36 (-279 ~ 208) 488
6978 23:10:59.978600 iDelay=217, Bit 8, Center -56 (-295 ~ 184) 480
6979 23:10:59.982284 iDelay=217, Bit 9, Center -52 (-295 ~ 192) 488
6980 23:10:59.985447 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6981 23:10:59.991601 iDelay=217, Bit 11, Center -48 (-287 ~ 192) 480
6982 23:10:59.995453 iDelay=217, Bit 12, Center -32 (-271 ~ 208) 480
6983 23:10:59.998949 iDelay=217, Bit 13, Center -36 (-279 ~ 208) 488
6984 23:11:00.005095 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6985 23:11:00.008117 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6986 23:11:00.008581 ==
6987 23:11:00.011488 Dram Type= 6, Freq= 0, CH_1, rank 1
6988 23:11:00.014732 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6989 23:11:00.015155 ==
6990 23:11:00.018086 DQS Delay:
6991 23:11:00.018598 DQS0 = 48, DQS1 = 56
6992 23:11:00.018932 DQM Delay:
6993 23:11:00.021283 DQM0 = 12, DQM1 = 13
6994 23:11:00.021701 DQ Delay:
6995 23:11:00.024960 DQ0 =12, DQ1 =8, DQ2 =0, DQ3 =12
6996 23:11:00.027456 DQ4 =12, DQ5 =20, DQ6 =20, DQ7 =12
6997 23:11:00.031188 DQ8 =0, DQ9 =4, DQ10 =12, DQ11 =8
6998 23:11:00.034633 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =20
6999 23:11:00.035199
7000 23:11:00.035601
7001 23:11:00.043959 [DQSOSCAuto] RK1, (LSB)MR18= 0x73ab, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 395 ps
7002 23:11:00.047320 CH1 RK1: MR19=C0C, MR18=73AB
7003 23:11:00.050994 CH1_RK1: MR19=0xC0C, MR18=0x73AB, DQSOSC=388, MR23=63, INC=392, DEC=261
7004 23:11:00.053915 [RxdqsGatingPostProcess] freq 400
7005 23:11:00.060268 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7006 23:11:00.063797 best DQS0 dly(2T, 0.5T) = (0, 10)
7007 23:11:00.067139 best DQS1 dly(2T, 0.5T) = (0, 10)
7008 23:11:00.070435 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7009 23:11:00.073480 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7010 23:11:00.077094 best DQS0 dly(2T, 0.5T) = (0, 10)
7011 23:11:00.080224 best DQS1 dly(2T, 0.5T) = (0, 10)
7012 23:11:00.083761 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7013 23:11:00.087299 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7014 23:11:00.090340 Pre-setting of DQS Precalculation
7015 23:11:00.094028 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7016 23:11:00.100263 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7017 23:11:00.107488 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7018 23:11:00.110133
7019 23:11:00.110689
7020 23:11:00.111056 [Calibration Summary] 800 Mbps
7021 23:11:00.113697 CH 0, Rank 0
7022 23:11:00.114257 SW Impedance : PASS
7023 23:11:00.116702 DUTY Scan : NO K
7024 23:11:00.120161 ZQ Calibration : PASS
7025 23:11:00.120800 Jitter Meter : NO K
7026 23:11:00.124018 CBT Training : PASS
7027 23:11:00.126410 Write leveling : PASS
7028 23:11:00.126877 RX DQS gating : PASS
7029 23:11:00.130147 RX DQ/DQS(RDDQC) : PASS
7030 23:11:00.132888 TX DQ/DQS : PASS
7031 23:11:00.133307 RX DATLAT : PASS
7032 23:11:00.137162 RX DQ/DQS(Engine): PASS
7033 23:11:00.139699 TX OE : NO K
7034 23:11:00.140119 All Pass.
7035 23:11:00.140448
7036 23:11:00.140755 CH 0, Rank 1
7037 23:11:00.142594 SW Impedance : PASS
7038 23:11:00.146197 DUTY Scan : NO K
7039 23:11:00.146791 ZQ Calibration : PASS
7040 23:11:00.149463 Jitter Meter : NO K
7041 23:11:00.153744 CBT Training : PASS
7042 23:11:00.154253 Write leveling : NO K
7043 23:11:00.156053 RX DQS gating : PASS
7044 23:11:00.159321 RX DQ/DQS(RDDQC) : PASS
7045 23:11:00.159878 TX DQ/DQS : PASS
7046 23:11:00.162875 RX DATLAT : PASS
7047 23:11:00.166342 RX DQ/DQS(Engine): PASS
7048 23:11:00.166892 TX OE : NO K
7049 23:11:00.167263 All Pass.
7050 23:11:00.169454
7051 23:11:00.169991 CH 1, Rank 0
7052 23:11:00.172514 SW Impedance : PASS
7053 23:11:00.172935 DUTY Scan : NO K
7054 23:11:00.175462 ZQ Calibration : PASS
7055 23:11:00.179461 Jitter Meter : NO K
7056 23:11:00.179978 CBT Training : PASS
7057 23:11:00.182469 Write leveling : PASS
7058 23:11:00.182977 RX DQS gating : PASS
7059 23:11:00.185684 RX DQ/DQS(RDDQC) : PASS
7060 23:11:00.188916 TX DQ/DQS : PASS
7061 23:11:00.189428 RX DATLAT : PASS
7062 23:11:00.192208 RX DQ/DQS(Engine): PASS
7063 23:11:00.195525 TX OE : NO K
7064 23:11:00.196038 All Pass.
7065 23:11:00.196374
7066 23:11:00.196684 CH 1, Rank 1
7067 23:11:00.198855 SW Impedance : PASS
7068 23:11:00.202256 DUTY Scan : NO K
7069 23:11:00.202764 ZQ Calibration : PASS
7070 23:11:00.205728 Jitter Meter : NO K
7071 23:11:00.208835 CBT Training : PASS
7072 23:11:00.209349 Write leveling : NO K
7073 23:11:00.212012 RX DQS gating : PASS
7074 23:11:00.215186 RX DQ/DQS(RDDQC) : PASS
7075 23:11:00.215741 TX DQ/DQS : PASS
7076 23:11:00.218633 RX DATLAT : PASS
7077 23:11:00.221813 RX DQ/DQS(Engine): PASS
7078 23:11:00.222325 TX OE : NO K
7079 23:11:00.225430 All Pass.
7080 23:11:00.225848
7081 23:11:00.226181 DramC Write-DBI off
7082 23:11:00.228442 PER_BANK_REFRESH: Hybrid Mode
7083 23:11:00.228861 TX_TRACKING: ON
7084 23:11:00.238711 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7085 23:11:00.242409 [FAST_K] Save calibration result to emmc
7086 23:11:00.245382 dramc_set_vcore_voltage set vcore to 725000
7087 23:11:00.248672 Read voltage for 1600, 0
7088 23:11:00.249138 Vio18 = 0
7089 23:11:00.252114 Vcore = 725000
7090 23:11:00.252575 Vdram = 0
7091 23:11:00.252931 Vddq = 0
7092 23:11:00.255260 Vmddr = 0
7093 23:11:00.258727 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7094 23:11:00.265295 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7095 23:11:00.265843 MEM_TYPE=3, freq_sel=13
7096 23:11:00.268643 sv_algorithm_assistance_LP4_3733
7097 23:11:00.274599 ============ PULL DRAM RESETB DOWN ============
7098 23:11:00.278535 ========== PULL DRAM RESETB DOWN end =========
7099 23:11:00.281383 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7100 23:11:00.284935 ===================================
7101 23:11:00.287614 LPDDR4 DRAM CONFIGURATION
7102 23:11:00.291237 ===================================
7103 23:11:00.294574 EX_ROW_EN[0] = 0x0
7104 23:11:00.295176 EX_ROW_EN[1] = 0x0
7105 23:11:00.297607 LP4Y_EN = 0x0
7106 23:11:00.298045 WORK_FSP = 0x1
7107 23:11:00.300642 WL = 0x5
7108 23:11:00.301061 RL = 0x5
7109 23:11:00.304426 BL = 0x2
7110 23:11:00.304843 RPST = 0x0
7111 23:11:00.307946 RD_PRE = 0x0
7112 23:11:00.308456 WR_PRE = 0x1
7113 23:11:00.311024 WR_PST = 0x1
7114 23:11:00.311584 DBI_WR = 0x0
7115 23:11:00.314370 DBI_RD = 0x0
7116 23:11:00.317440 OTF = 0x1
7117 23:11:00.320763 ===================================
7118 23:11:00.325113 ===================================
7119 23:11:00.325672 ANA top config
7120 23:11:00.327328 ===================================
7121 23:11:00.331236 DLL_ASYNC_EN = 0
7122 23:11:00.331794 ALL_SLAVE_EN = 0
7123 23:11:00.333946 NEW_RANK_MODE = 1
7124 23:11:00.337301 DLL_IDLE_MODE = 1
7125 23:11:00.340782 LP45_APHY_COMB_EN = 1
7126 23:11:00.344104 TX_ODT_DIS = 0
7127 23:11:00.344618 NEW_8X_MODE = 1
7128 23:11:00.346867 ===================================
7129 23:11:00.350670 ===================================
7130 23:11:00.353516 data_rate = 3200
7131 23:11:00.356501 CKR = 1
7132 23:11:00.360526 DQ_P2S_RATIO = 8
7133 23:11:00.363987 ===================================
7134 23:11:00.366912 CA_P2S_RATIO = 8
7135 23:11:00.370221 DQ_CA_OPEN = 0
7136 23:11:00.373216 DQ_SEMI_OPEN = 0
7137 23:11:00.373652 CA_SEMI_OPEN = 0
7138 23:11:00.376329 CA_FULL_RATE = 0
7139 23:11:00.379804 DQ_CKDIV4_EN = 0
7140 23:11:00.383503 CA_CKDIV4_EN = 0
7141 23:11:00.387120 CA_PREDIV_EN = 0
7142 23:11:00.389601 PH8_DLY = 12
7143 23:11:00.390024 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7144 23:11:00.393210 DQ_AAMCK_DIV = 4
7145 23:11:00.396644 CA_AAMCK_DIV = 4
7146 23:11:00.399752 CA_ADMCK_DIV = 4
7147 23:11:00.403271 DQ_TRACK_CA_EN = 0
7148 23:11:00.406488 CA_PICK = 1600
7149 23:11:00.409708 CA_MCKIO = 1600
7150 23:11:00.410130 MCKIO_SEMI = 0
7151 23:11:00.413168 PLL_FREQ = 3068
7152 23:11:00.416590 DQ_UI_PI_RATIO = 32
7153 23:11:00.419743 CA_UI_PI_RATIO = 0
7154 23:11:00.422697 ===================================
7155 23:11:00.426147 ===================================
7156 23:11:00.429992 memory_type:LPDDR4
7157 23:11:00.430514 GP_NUM : 10
7158 23:11:00.433171 SRAM_EN : 1
7159 23:11:00.436554 MD32_EN : 0
7160 23:11:00.439504 ===================================
7161 23:11:00.440018 [ANA_INIT] >>>>>>>>>>>>>>
7162 23:11:00.444104 <<<<<< [CONFIGURE PHASE]: ANA_TX
7163 23:11:00.445792 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7164 23:11:00.449380 ===================================
7165 23:11:00.452310 data_rate = 3200,PCW = 0X7600
7166 23:11:00.455650 ===================================
7167 23:11:00.459567 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7168 23:11:00.465970 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7169 23:11:00.469650 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7170 23:11:00.475899 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7171 23:11:00.479108 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7172 23:11:00.482164 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7173 23:11:00.485491 [ANA_INIT] flow start
7174 23:11:00.486002 [ANA_INIT] PLL >>>>>>>>
7175 23:11:00.488769 [ANA_INIT] PLL <<<<<<<<
7176 23:11:00.491965 [ANA_INIT] MIDPI >>>>>>>>
7177 23:11:00.492471 [ANA_INIT] MIDPI <<<<<<<<
7178 23:11:00.495286 [ANA_INIT] DLL >>>>>>>>
7179 23:11:00.498857 [ANA_INIT] DLL <<<<<<<<
7180 23:11:00.499275 [ANA_INIT] flow end
7181 23:11:00.505415 ============ LP4 DIFF to SE enter ============
7182 23:11:00.508709 ============ LP4 DIFF to SE exit ============
7183 23:11:00.512282 [ANA_INIT] <<<<<<<<<<<<<
7184 23:11:00.515069 [Flow] Enable top DCM control >>>>>
7185 23:11:00.519032 [Flow] Enable top DCM control <<<<<
7186 23:11:00.519599 Enable DLL master slave shuffle
7187 23:11:00.524727 ==============================================================
7188 23:11:00.527929 Gating Mode config
7189 23:11:00.531225 ==============================================================
7190 23:11:00.534685 Config description:
7191 23:11:00.544563 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7192 23:11:00.551097 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7193 23:11:00.554517 SELPH_MODE 0: By rank 1: By Phase
7194 23:11:00.560839 ==============================================================
7195 23:11:00.564608 GAT_TRACK_EN = 1
7196 23:11:00.567337 RX_GATING_MODE = 2
7197 23:11:00.570927 RX_GATING_TRACK_MODE = 2
7198 23:11:00.574287 SELPH_MODE = 1
7199 23:11:00.577471 PICG_EARLY_EN = 1
7200 23:11:00.580640 VALID_LAT_VALUE = 1
7201 23:11:00.584342 ==============================================================
7202 23:11:00.587715 Enter into Gating configuration >>>>
7203 23:11:00.591036 Exit from Gating configuration <<<<
7204 23:11:00.594111 Enter into DVFS_PRE_config >>>>>
7205 23:11:00.604041 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7206 23:11:00.606865 Exit from DVFS_PRE_config <<<<<
7207 23:11:00.610477 Enter into PICG configuration >>>>
7208 23:11:00.613752 Exit from PICG configuration <<<<
7209 23:11:00.617739 [RX_INPUT] configuration >>>>>
7210 23:11:00.620000 [RX_INPUT] configuration <<<<<
7211 23:11:00.627025 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7212 23:11:00.630146 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7213 23:11:00.636657 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7214 23:11:00.643702 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7215 23:11:00.649692 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7216 23:11:00.656559 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7217 23:11:00.659636 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7218 23:11:00.663452 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7219 23:11:00.666233 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7220 23:11:00.672932 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7221 23:11:00.676893 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7222 23:11:00.679567 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7223 23:11:00.683028 ===================================
7224 23:11:00.685980 LPDDR4 DRAM CONFIGURATION
7225 23:11:00.689345 ===================================
7226 23:11:00.692615 EX_ROW_EN[0] = 0x0
7227 23:11:00.693165 EX_ROW_EN[1] = 0x0
7228 23:11:00.696537 LP4Y_EN = 0x0
7229 23:11:00.697087 WORK_FSP = 0x1
7230 23:11:00.699055 WL = 0x5
7231 23:11:00.699656 RL = 0x5
7232 23:11:00.703278 BL = 0x2
7233 23:11:00.703879 RPST = 0x0
7234 23:11:00.705580 RD_PRE = 0x0
7235 23:11:00.708940 WR_PRE = 0x1
7236 23:11:00.709490 WR_PST = 0x1
7237 23:11:00.712722 DBI_WR = 0x0
7238 23:11:00.713268 DBI_RD = 0x0
7239 23:11:00.716054 OTF = 0x1
7240 23:11:00.718561 ===================================
7241 23:11:00.722501 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7242 23:11:00.725241 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7243 23:11:00.728549 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7244 23:11:00.732091 ===================================
7245 23:11:00.735094 LPDDR4 DRAM CONFIGURATION
7246 23:11:00.738587 ===================================
7247 23:11:00.742209 EX_ROW_EN[0] = 0x10
7248 23:11:00.742671 EX_ROW_EN[1] = 0x0
7249 23:11:00.745762 LP4Y_EN = 0x0
7250 23:11:00.746274 WORK_FSP = 0x1
7251 23:11:00.748271 WL = 0x5
7252 23:11:00.748684 RL = 0x5
7253 23:11:00.751427 BL = 0x2
7254 23:11:00.751844 RPST = 0x0
7255 23:11:00.754909 RD_PRE = 0x0
7256 23:11:00.758300 WR_PRE = 0x1
7257 23:11:00.758813 WR_PST = 0x1
7258 23:11:00.761562 DBI_WR = 0x0
7259 23:11:00.761976 DBI_RD = 0x0
7260 23:11:00.764679 OTF = 0x1
7261 23:11:00.768830 ===================================
7262 23:11:00.771810 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7263 23:11:00.774819 ==
7264 23:11:00.778451 Dram Type= 6, Freq= 0, CH_0, rank 0
7265 23:11:00.781622 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7266 23:11:00.782084 ==
7267 23:11:00.785213 [Duty_Offset_Calibration]
7268 23:11:00.785791 B0:2 B1:0 CA:4
7269 23:11:00.786161
7270 23:11:00.787991 [DutyScan_Calibration_Flow] k_type=0
7271 23:11:00.797436
7272 23:11:00.797995 ==CLK 0==
7273 23:11:00.800791 Final CLK duty delay cell = -4
7274 23:11:00.804289 [-4] MAX Duty = 5031%(X100), DQS PI = 30
7275 23:11:00.807056 [-4] MIN Duty = 4844%(X100), DQS PI = 2
7276 23:11:00.810641 [-4] AVG Duty = 4937%(X100)
7277 23:11:00.811157
7278 23:11:00.814313 CH0 CLK Duty spec in!! Max-Min= 187%
7279 23:11:00.817134 [DutyScan_Calibration_Flow] ====Done====
7280 23:11:00.817691
7281 23:11:00.821383 [DutyScan_Calibration_Flow] k_type=1
7282 23:11:00.838318
7283 23:11:00.838873 ==DQS 0 ==
7284 23:11:00.840719 Final DQS duty delay cell = 0
7285 23:11:00.844802 [0] MAX Duty = 5218%(X100), DQS PI = 38
7286 23:11:00.847895 [0] MIN Duty = 5093%(X100), DQS PI = 10
7287 23:11:00.851107 [0] AVG Duty = 5155%(X100)
7288 23:11:00.851708
7289 23:11:00.852072 ==DQS 1 ==
7290 23:11:00.854019 Final DQS duty delay cell = 0
7291 23:11:00.857928 [0] MAX Duty = 5156%(X100), DQS PI = 0
7292 23:11:00.860786 [0] MIN Duty = 4969%(X100), DQS PI = 10
7293 23:11:00.864367 [0] AVG Duty = 5062%(X100)
7294 23:11:00.864926
7295 23:11:00.867985 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7296 23:11:00.868446
7297 23:11:00.870625 CH0 DQS 1 Duty spec in!! Max-Min= 187%
7298 23:11:00.874311 [DutyScan_Calibration_Flow] ====Done====
7299 23:11:00.874867
7300 23:11:00.876928 [DutyScan_Calibration_Flow] k_type=3
7301 23:11:00.894628
7302 23:11:00.895185 ==DQM 0 ==
7303 23:11:00.898740 Final DQM duty delay cell = 0
7304 23:11:00.901429 [0] MAX Duty = 5124%(X100), DQS PI = 22
7305 23:11:00.904786 [0] MIN Duty = 4875%(X100), DQS PI = 54
7306 23:11:00.907838 [0] AVG Duty = 4999%(X100)
7307 23:11:00.908297
7308 23:11:00.908653 ==DQM 1 ==
7309 23:11:00.911053 Final DQM duty delay cell = 0
7310 23:11:00.914675 [0] MAX Duty = 5000%(X100), DQS PI = 2
7311 23:11:00.918753 [0] MIN Duty = 4844%(X100), DQS PI = 16
7312 23:11:00.921671 [0] AVG Duty = 4922%(X100)
7313 23:11:00.922232
7314 23:11:00.924644 CH0 DQM 0 Duty spec in!! Max-Min= 249%
7315 23:11:00.925204
7316 23:11:00.927596 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7317 23:11:00.930599 [DutyScan_Calibration_Flow] ====Done====
7318 23:11:00.931056
7319 23:11:00.934166 [DutyScan_Calibration_Flow] k_type=2
7320 23:11:00.951940
7321 23:11:00.952449 ==DQ 0 ==
7322 23:11:00.955293 Final DQ duty delay cell = 0
7323 23:11:00.958540 [0] MAX Duty = 5156%(X100), DQS PI = 22
7324 23:11:00.961800 [0] MIN Duty = 4938%(X100), DQS PI = 12
7325 23:11:00.965505 [0] AVG Duty = 5047%(X100)
7326 23:11:00.965956
7327 23:11:00.966295 ==DQ 1 ==
7328 23:11:00.967844 Final DQ duty delay cell = 0
7329 23:11:00.971521 [0] MAX Duty = 5187%(X100), DQS PI = 2
7330 23:11:00.974773 [0] MIN Duty = 4907%(X100), DQS PI = 32
7331 23:11:00.978287 [0] AVG Duty = 5047%(X100)
7332 23:11:00.978806
7333 23:11:00.981353 CH0 DQ 0 Duty spec in!! Max-Min= 218%
7334 23:11:00.981869
7335 23:11:00.984307 CH0 DQ 1 Duty spec in!! Max-Min= 280%
7336 23:11:00.987597 [DutyScan_Calibration_Flow] ====Done====
7337 23:11:00.988010 ==
7338 23:11:00.990927 Dram Type= 6, Freq= 0, CH_1, rank 0
7339 23:11:00.994324 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7340 23:11:00.994741 ==
7341 23:11:00.997504 [Duty_Offset_Calibration]
7342 23:11:00.997916 B0:0 B1:-1 CA:3
7343 23:11:00.998242
7344 23:11:01.001325 [DutyScan_Calibration_Flow] k_type=0
7345 23:11:01.011564
7346 23:11:01.011976 ==CLK 0==
7347 23:11:01.014747 Final CLK duty delay cell = -4
7348 23:11:01.018167 [-4] MAX Duty = 5000%(X100), DQS PI = 4
7349 23:11:01.021175 [-4] MIN Duty = 4844%(X100), DQS PI = 38
7350 23:11:01.024394 [-4] AVG Duty = 4922%(X100)
7351 23:11:01.024811
7352 23:11:01.027941 CH1 CLK Duty spec in!! Max-Min= 156%
7353 23:11:01.030854 [DutyScan_Calibration_Flow] ====Done====
7354 23:11:01.031266
7355 23:11:01.034233 [DutyScan_Calibration_Flow] k_type=1
7356 23:11:01.050147
7357 23:11:01.050558 ==DQS 0 ==
7358 23:11:01.053985 Final DQS duty delay cell = 0
7359 23:11:01.056993 [0] MAX Duty = 5250%(X100), DQS PI = 28
7360 23:11:01.059863 [0] MIN Duty = 4907%(X100), DQS PI = 60
7361 23:11:01.063190 [0] AVG Duty = 5078%(X100)
7362 23:11:01.063630
7363 23:11:01.063955 ==DQS 1 ==
7364 23:11:01.066743 Final DQS duty delay cell = -4
7365 23:11:01.069599 [-4] MAX Duty = 5000%(X100), DQS PI = 28
7366 23:11:01.072900 [-4] MIN Duty = 4813%(X100), DQS PI = 0
7367 23:11:01.076582 [-4] AVG Duty = 4906%(X100)
7368 23:11:01.076994
7369 23:11:01.079931 CH1 DQS 0 Duty spec in!! Max-Min= 343%
7370 23:11:01.080341
7371 23:11:01.083401 CH1 DQS 1 Duty spec in!! Max-Min= 187%
7372 23:11:01.086308 [DutyScan_Calibration_Flow] ====Done====
7373 23:11:01.086820
7374 23:11:01.089988 [DutyScan_Calibration_Flow] k_type=3
7375 23:11:01.107944
7376 23:11:01.108449 ==DQM 0 ==
7377 23:11:01.110812 Final DQM duty delay cell = 0
7378 23:11:01.113864 [0] MAX Duty = 5031%(X100), DQS PI = 30
7379 23:11:01.117111 [0] MIN Duty = 4782%(X100), DQS PI = 38
7380 23:11:01.120446 [0] AVG Duty = 4906%(X100)
7381 23:11:01.120857
7382 23:11:01.121182 ==DQM 1 ==
7383 23:11:01.123800 Final DQM duty delay cell = 0
7384 23:11:01.127497 [0] MAX Duty = 5000%(X100), DQS PI = 32
7385 23:11:01.130354 [0] MIN Duty = 4813%(X100), DQS PI = 0
7386 23:11:01.134509 [0] AVG Duty = 4906%(X100)
7387 23:11:01.135011
7388 23:11:01.137739 CH1 DQM 0 Duty spec in!! Max-Min= 249%
7389 23:11:01.138246
7390 23:11:01.140692 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7391 23:11:01.143836 [DutyScan_Calibration_Flow] ====Done====
7392 23:11:01.144345
7393 23:11:01.147468 [DutyScan_Calibration_Flow] k_type=2
7394 23:11:01.163623
7395 23:11:01.164126 ==DQ 0 ==
7396 23:11:01.167232 Final DQ duty delay cell = -4
7397 23:11:01.170566 [-4] MAX Duty = 4969%(X100), DQS PI = 32
7398 23:11:01.173353 [-4] MIN Duty = 4813%(X100), DQS PI = 38
7399 23:11:01.177110 [-4] AVG Duty = 4891%(X100)
7400 23:11:01.177696
7401 23:11:01.178053 ==DQ 1 ==
7402 23:11:01.180750 Final DQ duty delay cell = 0
7403 23:11:01.183715 [0] MAX Duty = 5031%(X100), DQS PI = 32
7404 23:11:01.186952 [0] MIN Duty = 4875%(X100), DQS PI = 56
7405 23:11:01.190524 [0] AVG Duty = 4953%(X100)
7406 23:11:01.191064
7407 23:11:01.193241 CH1 DQ 0 Duty spec in!! Max-Min= 156%
7408 23:11:01.193780
7409 23:11:01.196486 CH1 DQ 1 Duty spec in!! Max-Min= 156%
7410 23:11:01.199665 [DutyScan_Calibration_Flow] ====Done====
7411 23:11:01.203222 nWR fixed to 30
7412 23:11:01.206826 [ModeRegInit_LP4] CH0 RK0
7413 23:11:01.207427 [ModeRegInit_LP4] CH0 RK1
7414 23:11:01.209829 [ModeRegInit_LP4] CH1 RK0
7415 23:11:01.213462 [ModeRegInit_LP4] CH1 RK1
7416 23:11:01.214016 match AC timing 5
7417 23:11:01.219324 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7418 23:11:01.222403 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7419 23:11:01.225968 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7420 23:11:01.232608 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7421 23:11:01.236227 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7422 23:11:01.239124 [MiockJmeterHQA]
7423 23:11:01.239570
7424 23:11:01.242332 [DramcMiockJmeter] u1RxGatingPI = 0
7425 23:11:01.242739 0 : 4257, 4029
7426 23:11:01.243068 4 : 4363, 4137
7427 23:11:01.245778 8 : 4363, 4138
7428 23:11:01.246239 12 : 4252, 4027
7429 23:11:01.249239 16 : 4253, 4027
7430 23:11:01.249659 20 : 4252, 4027
7431 23:11:01.253089 24 : 4253, 4026
7432 23:11:01.253604 28 : 4253, 4027
7433 23:11:01.255580 32 : 4252, 4027
7434 23:11:01.255998 36 : 4366, 4140
7435 23:11:01.256328 40 : 4363, 4140
7436 23:11:01.258839 44 : 4255, 4029
7437 23:11:01.259252 48 : 4255, 4029
7438 23:11:01.262244 52 : 4363, 4138
7439 23:11:01.262757 56 : 4253, 4026
7440 23:11:01.265993 60 : 4363, 4140
7441 23:11:01.266507 64 : 4250, 4027
7442 23:11:01.269096 68 : 4250, 4027
7443 23:11:01.269511 72 : 4250, 4027
7444 23:11:01.269841 76 : 4252, 4029
7445 23:11:01.272056 80 : 4360, 4138
7446 23:11:01.272472 84 : 4250, 4027
7447 23:11:01.275726 88 : 4361, 4137
7448 23:11:01.276239 92 : 4363, 4140
7449 23:11:01.279016 96 : 4250, 3185
7450 23:11:01.279623 100 : 4253, 0
7451 23:11:01.280057 104 : 4252, 0
7452 23:11:01.282932 108 : 4255, 0
7453 23:11:01.283485 112 : 4250, 0
7454 23:11:01.285312 116 : 4250, 0
7455 23:11:01.285824 120 : 4361, 0
7456 23:11:01.286159 124 : 4366, 0
7457 23:11:01.288825 128 : 4363, 0
7458 23:11:01.289340 132 : 4250, 0
7459 23:11:01.292371 136 : 4250, 0
7460 23:11:01.293043 140 : 4252, 0
7461 23:11:01.293397 144 : 4250, 0
7462 23:11:01.295068 148 : 4249, 0
7463 23:11:01.295534 152 : 4361, 0
7464 23:11:01.299143 156 : 4250, 0
7465 23:11:01.299719 160 : 4250, 0
7466 23:11:01.300062 164 : 4250, 0
7467 23:11:01.301844 168 : 4252, 0
7468 23:11:01.302262 172 : 4360, 0
7469 23:11:01.305285 176 : 4250, 0
7470 23:11:01.305798 180 : 4250, 0
7471 23:11:01.306136 184 : 4250, 0
7472 23:11:01.307928 188 : 4360, 0
7473 23:11:01.308347 192 : 4250, 0
7474 23:11:01.308682 196 : 4250, 0
7475 23:11:01.311734 200 : 4250, 0
7476 23:11:01.312280 204 : 4361, 0
7477 23:11:01.314840 208 : 4250, 0
7478 23:11:01.315354 212 : 4250, 0
7479 23:11:01.315744 216 : 4250, 0
7480 23:11:01.318382 220 : 4255, 501
7481 23:11:01.318914 224 : 4360, 4073
7482 23:11:01.321297 228 : 4252, 4030
7483 23:11:01.321811 232 : 4253, 4029
7484 23:11:01.324588 236 : 4361, 4137
7485 23:11:01.325003 240 : 4253, 4029
7486 23:11:01.327833 244 : 4249, 4027
7487 23:11:01.328258 248 : 4249, 4027
7488 23:11:01.331505 252 : 4252, 4029
7489 23:11:01.331959 256 : 4250, 4027
7490 23:11:01.334438 260 : 4362, 4140
7491 23:11:01.334859 264 : 4249, 4027
7492 23:11:01.337583 268 : 4250, 4026
7493 23:11:01.337998 272 : 4250, 4027
7494 23:11:01.338352 276 : 4363, 4140
7495 23:11:01.340838 280 : 4361, 4138
7496 23:11:01.341268 284 : 4248, 4024
7497 23:11:01.344422 288 : 4363, 4140
7498 23:11:01.344900 292 : 4253, 4029
7499 23:11:01.347472 296 : 4250, 4027
7500 23:11:01.347910 300 : 4250, 4026
7501 23:11:01.351429 304 : 4252, 4029
7502 23:11:01.351964 308 : 4253, 4029
7503 23:11:01.355102 312 : 4363, 4140
7504 23:11:01.355665 316 : 4249, 4027
7505 23:11:01.357755 320 : 4250, 4027
7506 23:11:01.358262 324 : 4250, 4027
7507 23:11:01.361005 328 : 4364, 4140
7508 23:11:01.361518 332 : 4361, 4102
7509 23:11:01.363819 336 : 4250, 1944
7510 23:11:01.364239
7511 23:11:01.364563 MIOCK jitter meter ch=0
7512 23:11:01.364871
7513 23:11:01.367309 1T = (336-100) = 236 dly cells
7514 23:11:01.373875 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7515 23:11:01.374384 ==
7516 23:11:01.377235 Dram Type= 6, Freq= 0, CH_0, rank 0
7517 23:11:01.380421 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7518 23:11:01.380840 ==
7519 23:11:01.387612 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7520 23:11:01.390615 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7521 23:11:01.397318 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7522 23:11:01.399953 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7523 23:11:01.410697 [CA 0] Center 43 (13~74) winsize 62
7524 23:11:01.413746 [CA 1] Center 42 (12~73) winsize 62
7525 23:11:01.417005 [CA 2] Center 37 (8~67) winsize 60
7526 23:11:01.420706 [CA 3] Center 37 (8~67) winsize 60
7527 23:11:01.423340 [CA 4] Center 36 (6~66) winsize 61
7528 23:11:01.426941 [CA 5] Center 35 (5~66) winsize 62
7529 23:11:01.427540
7530 23:11:01.429715 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7531 23:11:01.430231
7532 23:11:01.433516 [CATrainingPosCal] consider 1 rank data
7533 23:11:01.436632 u2DelayCellTimex100 = 275/100 ps
7534 23:11:01.443096 CA0 delay=43 (13~74),Diff = 8 PI (28 cell)
7535 23:11:01.447091 CA1 delay=42 (12~73),Diff = 7 PI (24 cell)
7536 23:11:01.450391 CA2 delay=37 (8~67),Diff = 2 PI (7 cell)
7537 23:11:01.453608 CA3 delay=37 (8~67),Diff = 2 PI (7 cell)
7538 23:11:01.456041 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7539 23:11:01.459951 CA5 delay=35 (5~66),Diff = 0 PI (0 cell)
7540 23:11:01.460507
7541 23:11:01.462794 CA PerBit enable=1, Macro0, CA PI delay=35
7542 23:11:01.463253
7543 23:11:01.466041 [CBTSetCACLKResult] CA Dly = 35
7544 23:11:01.469603 CS Dly: 11 (0~42)
7545 23:11:01.472806 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7546 23:11:01.475769 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7547 23:11:01.476227 ==
7548 23:11:01.479638 Dram Type= 6, Freq= 0, CH_0, rank 1
7549 23:11:01.486086 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7550 23:11:01.486662 ==
7551 23:11:01.489438 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7552 23:11:01.495910 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7553 23:11:01.499546 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7554 23:11:01.506138 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7555 23:11:01.513668 [CA 0] Center 44 (14~75) winsize 62
7556 23:11:01.517114 [CA 1] Center 44 (14~74) winsize 61
7557 23:11:01.520187 [CA 2] Center 39 (10~69) winsize 60
7558 23:11:01.523764 [CA 3] Center 39 (10~68) winsize 59
7559 23:11:01.527148 [CA 4] Center 37 (7~67) winsize 61
7560 23:11:01.530191 [CA 5] Center 36 (7~66) winsize 60
7561 23:11:01.530819
7562 23:11:01.532940 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7563 23:11:01.536619
7564 23:11:01.540202 [CATrainingPosCal] consider 2 rank data
7565 23:11:01.542999 u2DelayCellTimex100 = 275/100 ps
7566 23:11:01.546872 CA0 delay=44 (14~74),Diff = 8 PI (28 cell)
7567 23:11:01.549894 CA1 delay=43 (14~73),Diff = 7 PI (24 cell)
7568 23:11:01.553741 CA2 delay=38 (10~67),Diff = 2 PI (7 cell)
7569 23:11:01.556789 CA3 delay=38 (10~67),Diff = 2 PI (7 cell)
7570 23:11:01.559645 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7571 23:11:01.562763 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7572 23:11:01.563436
7573 23:11:01.566540 CA PerBit enable=1, Macro0, CA PI delay=36
7574 23:11:01.569542
7575 23:11:01.570099 [CBTSetCACLKResult] CA Dly = 36
7576 23:11:01.573100 CS Dly: 12 (0~44)
7577 23:11:01.576135 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7578 23:11:01.579517 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7579 23:11:01.580064
7580 23:11:01.586707 ----->DramcWriteLeveling(PI) begin...
7581 23:11:01.587264 ==
7582 23:11:01.589874 Dram Type= 6, Freq= 0, CH_0, rank 0
7583 23:11:01.592629 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7584 23:11:01.593184 ==
7585 23:11:01.595833 Write leveling (Byte 0): 35 => 35
7586 23:11:01.599140 Write leveling (Byte 1): 27 => 27
7587 23:11:01.602593 DramcWriteLeveling(PI) end<-----
7588 23:11:01.603218
7589 23:11:01.603654 ==
7590 23:11:01.605696 Dram Type= 6, Freq= 0, CH_0, rank 0
7591 23:11:01.609375 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7592 23:11:01.609889 ==
7593 23:11:01.612558 [Gating] SW mode calibration
7594 23:11:01.619417 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7595 23:11:01.625953 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7596 23:11:01.628721 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7597 23:11:01.631772 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7598 23:11:01.639055 1 4 8 | B1->B0 | 2323 2626 | 0 1 | (0 0) (1 1)
7599 23:11:01.642015 1 4 12 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
7600 23:11:01.646263 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7601 23:11:01.651596 1 4 20 | B1->B0 | 2c2c 3434 | 1 1 | (1 1) (1 1)
7602 23:11:01.655210 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7603 23:11:01.658549 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7604 23:11:01.666482 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7605 23:11:01.668772 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7606 23:11:01.671349 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7607 23:11:01.678363 1 5 12 | B1->B0 | 3434 2b2b | 1 0 | (1 1) (0 1)
7608 23:11:01.681990 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7609 23:11:01.685014 1 5 20 | B1->B0 | 2b2b 2323 | 1 0 | (1 0) (0 0)
7610 23:11:01.690834 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7611 23:11:01.694287 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7612 23:11:01.698005 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7613 23:11:01.704672 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7614 23:11:01.707324 1 6 8 | B1->B0 | 2323 2727 | 0 1 | (0 0) (0 0)
7615 23:11:01.710823 1 6 12 | B1->B0 | 2323 4242 | 0 0 | (0 0) (0 0)
7616 23:11:01.717290 1 6 16 | B1->B0 | 2323 4646 | 1 0 | (0 0) (0 0)
7617 23:11:01.720701 1 6 20 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
7618 23:11:01.724277 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7619 23:11:01.730589 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7620 23:11:01.733767 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7621 23:11:01.736895 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7622 23:11:01.743675 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7623 23:11:01.747197 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7624 23:11:01.750749 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7625 23:11:01.757798 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7626 23:11:01.760312 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7627 23:11:01.763480 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7628 23:11:01.770088 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7629 23:11:01.773734 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7630 23:11:01.777313 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7631 23:11:01.783539 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7632 23:11:01.786644 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7633 23:11:01.790310 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7634 23:11:01.796405 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7635 23:11:01.799576 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7636 23:11:01.802947 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7637 23:11:01.809706 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7638 23:11:01.812896 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7639 23:11:01.816271 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7640 23:11:01.822762 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7641 23:11:01.826549 Total UI for P1: 0, mck2ui 16
7642 23:11:01.830563 best dqsien dly found for B0: ( 1, 9, 10)
7643 23:11:01.833695 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7644 23:11:01.836276 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7645 23:11:01.842877 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7646 23:11:01.843494 Total UI for P1: 0, mck2ui 16
7647 23:11:01.849361 best dqsien dly found for B1: ( 1, 9, 22)
7648 23:11:01.852323 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7649 23:11:01.856593 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7650 23:11:01.857142
7651 23:11:01.859243 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7652 23:11:01.862761 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7653 23:11:01.866138 [Gating] SW calibration Done
7654 23:11:01.866688 ==
7655 23:11:01.869183 Dram Type= 6, Freq= 0, CH_0, rank 0
7656 23:11:01.872371 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7657 23:11:01.872931 ==
7658 23:11:01.875289 RX Vref Scan: 0
7659 23:11:01.875778
7660 23:11:01.879426 RX Vref 0 -> 0, step: 1
7661 23:11:01.880009
7662 23:11:01.880378 RX Delay 0 -> 252, step: 8
7663 23:11:01.885776 iDelay=192, Bit 0, Center 131 (80 ~ 183) 104
7664 23:11:01.888785 iDelay=192, Bit 1, Center 135 (80 ~ 191) 112
7665 23:11:01.892129 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7666 23:11:01.896035 iDelay=192, Bit 3, Center 123 (72 ~ 175) 104
7667 23:11:01.898890 iDelay=192, Bit 4, Center 135 (80 ~ 191) 112
7668 23:11:01.905421 iDelay=192, Bit 5, Center 119 (64 ~ 175) 112
7669 23:11:01.908616 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
7670 23:11:01.911670 iDelay=192, Bit 7, Center 135 (80 ~ 191) 112
7671 23:11:01.914738 iDelay=192, Bit 8, Center 115 (64 ~ 167) 104
7672 23:11:01.921830 iDelay=192, Bit 9, Center 111 (56 ~ 167) 112
7673 23:11:01.924870 iDelay=192, Bit 10, Center 123 (72 ~ 175) 104
7674 23:11:01.928339 iDelay=192, Bit 11, Center 119 (64 ~ 175) 112
7675 23:11:01.931291 iDelay=192, Bit 12, Center 131 (72 ~ 191) 120
7676 23:11:01.934525 iDelay=192, Bit 13, Center 131 (80 ~ 183) 104
7677 23:11:01.941469 iDelay=192, Bit 14, Center 131 (80 ~ 183) 104
7678 23:11:01.945719 iDelay=192, Bit 15, Center 135 (80 ~ 191) 112
7679 23:11:01.946272 ==
7680 23:11:01.948019 Dram Type= 6, Freq= 0, CH_0, rank 0
7681 23:11:01.951819 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7682 23:11:01.952373 ==
7683 23:11:01.954688 DQS Delay:
7684 23:11:01.955235 DQS0 = 0, DQS1 = 0
7685 23:11:01.955660 DQM Delay:
7686 23:11:01.958042 DQM0 = 130, DQM1 = 124
7687 23:11:01.958605 DQ Delay:
7688 23:11:01.961050 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =123
7689 23:11:01.965022 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =135
7690 23:11:01.970905 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =119
7691 23:11:01.974107 DQ12 =131, DQ13 =131, DQ14 =131, DQ15 =135
7692 23:11:01.974560
7693 23:11:01.974937
7694 23:11:01.975270 ==
7695 23:11:01.977467 Dram Type= 6, Freq= 0, CH_0, rank 0
7696 23:11:01.981355 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7697 23:11:01.981912 ==
7698 23:11:01.982274
7699 23:11:01.982605
7700 23:11:01.984738 TX Vref Scan disable
7701 23:11:01.987522 == TX Byte 0 ==
7702 23:11:01.990877 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7703 23:11:01.994227 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7704 23:11:01.997096 == TX Byte 1 ==
7705 23:11:02.000788 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7706 23:11:02.004544 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7707 23:11:02.005097 ==
7708 23:11:02.007240 Dram Type= 6, Freq= 0, CH_0, rank 0
7709 23:11:02.010707 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7710 23:11:02.013646 ==
7711 23:11:02.027071
7712 23:11:02.030188 TX Vref early break, caculate TX vref
7713 23:11:02.033359 TX Vref=16, minBit 4, minWin=22, winSum=369
7714 23:11:02.036543 TX Vref=18, minBit 0, minWin=23, winSum=383
7715 23:11:02.040249 TX Vref=20, minBit 7, minWin=22, winSum=387
7716 23:11:02.043545 TX Vref=22, minBit 7, minWin=24, winSum=404
7717 23:11:02.048647 TX Vref=24, minBit 1, minWin=24, winSum=410
7718 23:11:02.053177 TX Vref=26, minBit 4, minWin=24, winSum=415
7719 23:11:02.057001 TX Vref=28, minBit 2, minWin=25, winSum=419
7720 23:11:02.060043 TX Vref=30, minBit 0, minWin=25, winSum=419
7721 23:11:02.063897 TX Vref=32, minBit 1, minWin=24, winSum=409
7722 23:11:02.066678 TX Vref=34, minBit 0, minWin=24, winSum=401
7723 23:11:02.073029 TX Vref=36, minBit 2, minWin=23, winSum=386
7724 23:11:02.076198 [TxChooseVref] Worse bit 2, Min win 25, Win sum 419, Final Vref 28
7725 23:11:02.076612
7726 23:11:02.079274 Final TX Range 0 Vref 28
7727 23:11:02.079743
7728 23:11:02.080071 ==
7729 23:11:02.082562 Dram Type= 6, Freq= 0, CH_0, rank 0
7730 23:11:02.086173 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7731 23:11:02.088994 ==
7732 23:11:02.089403
7733 23:11:02.089724
7734 23:11:02.090026 TX Vref Scan disable
7735 23:11:02.096247 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7736 23:11:02.096766 == TX Byte 0 ==
7737 23:11:02.099970 u2DelayCellOfst[0]=14 cells (4 PI)
7738 23:11:02.103139 u2DelayCellOfst[1]=21 cells (6 PI)
7739 23:11:02.106354 u2DelayCellOfst[2]=14 cells (4 PI)
7740 23:11:02.109379 u2DelayCellOfst[3]=14 cells (4 PI)
7741 23:11:02.112941 u2DelayCellOfst[4]=10 cells (3 PI)
7742 23:11:02.116112 u2DelayCellOfst[5]=0 cells (0 PI)
7743 23:11:02.119488 u2DelayCellOfst[6]=21 cells (6 PI)
7744 23:11:02.123293 u2DelayCellOfst[7]=17 cells (5 PI)
7745 23:11:02.125975 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7746 23:11:02.129112 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7747 23:11:02.132678 == TX Byte 1 ==
7748 23:11:02.135514 u2DelayCellOfst[8]=0 cells (0 PI)
7749 23:11:02.139090 u2DelayCellOfst[9]=0 cells (0 PI)
7750 23:11:02.142663 u2DelayCellOfst[10]=7 cells (2 PI)
7751 23:11:02.145508 u2DelayCellOfst[11]=3 cells (1 PI)
7752 23:11:02.148536 u2DelayCellOfst[12]=10 cells (3 PI)
7753 23:11:02.152685 u2DelayCellOfst[13]=10 cells (3 PI)
7754 23:11:02.156064 u2DelayCellOfst[14]=14 cells (4 PI)
7755 23:11:02.158658 u2DelayCellOfst[15]=10 cells (3 PI)
7756 23:11:02.162054 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7757 23:11:02.165369 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7758 23:11:02.168613 DramC Write-DBI on
7759 23:11:02.169021 ==
7760 23:11:02.171669 Dram Type= 6, Freq= 0, CH_0, rank 0
7761 23:11:02.175103 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7762 23:11:02.175664 ==
7763 23:11:02.175998
7764 23:11:02.176303
7765 23:11:02.178679 TX Vref Scan disable
7766 23:11:02.182005 == TX Byte 0 ==
7767 23:11:02.184837 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
7768 23:11:02.185342 == TX Byte 1 ==
7769 23:11:02.191654 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7770 23:11:02.192158 DramC Write-DBI off
7771 23:11:02.192489
7772 23:11:02.192789 [DATLAT]
7773 23:11:02.194848 Freq=1600, CH0 RK0
7774 23:11:02.195259
7775 23:11:02.198166 DATLAT Default: 0xf
7776 23:11:02.198588 0, 0xFFFF, sum = 0
7777 23:11:02.201140 1, 0xFFFF, sum = 0
7778 23:11:02.201556 2, 0xFFFF, sum = 0
7779 23:11:02.204959 3, 0xFFFF, sum = 0
7780 23:11:02.205374 4, 0xFFFF, sum = 0
7781 23:11:02.208507 5, 0xFFFF, sum = 0
7782 23:11:02.208920 6, 0xFFFF, sum = 0
7783 23:11:02.211189 7, 0xFFFF, sum = 0
7784 23:11:02.211794 8, 0xFFFF, sum = 0
7785 23:11:02.214818 9, 0xFFFF, sum = 0
7786 23:11:02.215327 10, 0xFFFF, sum = 0
7787 23:11:02.217852 11, 0xFFFF, sum = 0
7788 23:11:02.218362 12, 0xFFFF, sum = 0
7789 23:11:02.221348 13, 0xFFFF, sum = 0
7790 23:11:02.224592 14, 0x0, sum = 1
7791 23:11:02.225105 15, 0x0, sum = 2
7792 23:11:02.225441 16, 0x0, sum = 3
7793 23:11:02.227785 17, 0x0, sum = 4
7794 23:11:02.228297 best_step = 15
7795 23:11:02.228629
7796 23:11:02.228932 ==
7797 23:11:02.231525 Dram Type= 6, Freq= 0, CH_0, rank 0
7798 23:11:02.237642 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7799 23:11:02.238067 ==
7800 23:11:02.238400 RX Vref Scan: 1
7801 23:11:02.238704
7802 23:11:02.240858 Set Vref Range= 24 -> 127
7803 23:11:02.241275
7804 23:11:02.244231 RX Vref 24 -> 127, step: 1
7805 23:11:02.244642
7806 23:11:02.247485 RX Delay 11 -> 252, step: 4
7807 23:11:02.247986
7808 23:11:02.251208 Set Vref, RX VrefLevel [Byte0]: 24
7809 23:11:02.254434 [Byte1]: 24
7810 23:11:02.254848
7811 23:11:02.257747 Set Vref, RX VrefLevel [Byte0]: 25
7812 23:11:02.260839 [Byte1]: 25
7813 23:11:02.261351
7814 23:11:02.264263 Set Vref, RX VrefLevel [Byte0]: 26
7815 23:11:02.268425 [Byte1]: 26
7816 23:11:02.270907
7817 23:11:02.271525 Set Vref, RX VrefLevel [Byte0]: 27
7818 23:11:02.274506 [Byte1]: 27
7819 23:11:02.278540
7820 23:11:02.279087 Set Vref, RX VrefLevel [Byte0]: 28
7821 23:11:02.282082 [Byte1]: 28
7822 23:11:02.286613
7823 23:11:02.287165 Set Vref, RX VrefLevel [Byte0]: 29
7824 23:11:02.289774 [Byte1]: 29
7825 23:11:02.293686
7826 23:11:02.294231 Set Vref, RX VrefLevel [Byte0]: 30
7827 23:11:02.296965 [Byte1]: 30
7828 23:11:02.301112
7829 23:11:02.301666 Set Vref, RX VrefLevel [Byte0]: 31
7830 23:11:02.304892 [Byte1]: 31
7831 23:11:02.308827
7832 23:11:02.309378 Set Vref, RX VrefLevel [Byte0]: 32
7833 23:11:02.311943 [Byte1]: 32
7834 23:11:02.317012
7835 23:11:02.317560 Set Vref, RX VrefLevel [Byte0]: 33
7836 23:11:02.319943 [Byte1]: 33
7837 23:11:02.324085
7838 23:11:02.324684 Set Vref, RX VrefLevel [Byte0]: 34
7839 23:11:02.327240 [Byte1]: 34
7840 23:11:02.331648
7841 23:11:02.332103 Set Vref, RX VrefLevel [Byte0]: 35
7842 23:11:02.335445 [Byte1]: 35
7843 23:11:02.339680
7844 23:11:02.340134 Set Vref, RX VrefLevel [Byte0]: 36
7845 23:11:02.342707 [Byte1]: 36
7846 23:11:02.347279
7847 23:11:02.347923 Set Vref, RX VrefLevel [Byte0]: 37
7848 23:11:02.350579 [Byte1]: 37
7849 23:11:02.354811
7850 23:11:02.355445 Set Vref, RX VrefLevel [Byte0]: 38
7851 23:11:02.358866 [Byte1]: 38
7852 23:11:02.363011
7853 23:11:02.363623 Set Vref, RX VrefLevel [Byte0]: 39
7854 23:11:02.365850 [Byte1]: 39
7855 23:11:02.369948
7856 23:11:02.370506 Set Vref, RX VrefLevel [Byte0]: 40
7857 23:11:02.373724 [Byte1]: 40
7858 23:11:02.377565
7859 23:11:02.378124 Set Vref, RX VrefLevel [Byte0]: 41
7860 23:11:02.380590 [Byte1]: 41
7861 23:11:02.385277
7862 23:11:02.385833 Set Vref, RX VrefLevel [Byte0]: 42
7863 23:11:02.388182 [Byte1]: 42
7864 23:11:02.392811
7865 23:11:02.393407 Set Vref, RX VrefLevel [Byte0]: 43
7866 23:11:02.396173 [Byte1]: 43
7867 23:11:02.400247
7868 23:11:02.400718 Set Vref, RX VrefLevel [Byte0]: 44
7869 23:11:02.403608 [Byte1]: 44
7870 23:11:02.408343
7871 23:11:02.408927 Set Vref, RX VrefLevel [Byte0]: 45
7872 23:11:02.411354 [Byte1]: 45
7873 23:11:02.416066
7874 23:11:02.416628 Set Vref, RX VrefLevel [Byte0]: 46
7875 23:11:02.419173 [Byte1]: 46
7876 23:11:02.423476
7877 23:11:02.424025 Set Vref, RX VrefLevel [Byte0]: 47
7878 23:11:02.426408 [Byte1]: 47
7879 23:11:02.430958
7880 23:11:02.431536 Set Vref, RX VrefLevel [Byte0]: 48
7881 23:11:02.433815 [Byte1]: 48
7882 23:11:02.438255
7883 23:11:02.438714 Set Vref, RX VrefLevel [Byte0]: 49
7884 23:11:02.441640 [Byte1]: 49
7885 23:11:02.446316
7886 23:11:02.446865 Set Vref, RX VrefLevel [Byte0]: 50
7887 23:11:02.449155 [Byte1]: 50
7888 23:11:02.453406
7889 23:11:02.453865 Set Vref, RX VrefLevel [Byte0]: 51
7890 23:11:02.456888 [Byte1]: 51
7891 23:11:02.461167
7892 23:11:02.461775 Set Vref, RX VrefLevel [Byte0]: 52
7893 23:11:02.464437 [Byte1]: 52
7894 23:11:02.468986
7895 23:11:02.469670 Set Vref, RX VrefLevel [Byte0]: 53
7896 23:11:02.472320 [Byte1]: 53
7897 23:11:02.476818
7898 23:11:02.477371 Set Vref, RX VrefLevel [Byte0]: 54
7899 23:11:02.480522 [Byte1]: 54
7900 23:11:02.484813
7901 23:11:02.485363 Set Vref, RX VrefLevel [Byte0]: 55
7902 23:11:02.487354 [Byte1]: 55
7903 23:11:02.491915
7904 23:11:02.492468 Set Vref, RX VrefLevel [Byte0]: 56
7905 23:11:02.495513 [Byte1]: 56
7906 23:11:02.499677
7907 23:11:02.500226 Set Vref, RX VrefLevel [Byte0]: 57
7908 23:11:02.502288 [Byte1]: 57
7909 23:11:02.506651
7910 23:11:02.507110 Set Vref, RX VrefLevel [Byte0]: 58
7911 23:11:02.511391 [Byte1]: 58
7912 23:11:02.515481
7913 23:11:02.515943 Set Vref, RX VrefLevel [Byte0]: 59
7914 23:11:02.518026 [Byte1]: 59
7915 23:11:02.522769
7916 23:11:02.523317 Set Vref, RX VrefLevel [Byte0]: 60
7917 23:11:02.525660 [Byte1]: 60
7918 23:11:02.530029
7919 23:11:02.530580 Set Vref, RX VrefLevel [Byte0]: 61
7920 23:11:02.533210 [Byte1]: 61
7921 23:11:02.537116
7922 23:11:02.537807 Set Vref, RX VrefLevel [Byte0]: 62
7923 23:11:02.541480 [Byte1]: 62
7924 23:11:02.544761
7925 23:11:02.545221 Set Vref, RX VrefLevel [Byte0]: 63
7926 23:11:02.548468 [Byte1]: 63
7927 23:11:02.552247
7928 23:11:02.552685 Set Vref, RX VrefLevel [Byte0]: 64
7929 23:11:02.555650 [Byte1]: 64
7930 23:11:02.560273
7931 23:11:02.560903 Set Vref, RX VrefLevel [Byte0]: 65
7932 23:11:02.564051 [Byte1]: 65
7933 23:11:02.567956
7934 23:11:02.568518 Set Vref, RX VrefLevel [Byte0]: 66
7935 23:11:02.570996 [Byte1]: 66
7936 23:11:02.575703
7937 23:11:02.576313 Set Vref, RX VrefLevel [Byte0]: 67
7938 23:11:02.578752 [Byte1]: 67
7939 23:11:02.582694
7940 23:11:02.583105 Set Vref, RX VrefLevel [Byte0]: 68
7941 23:11:02.586224 [Byte1]: 68
7942 23:11:02.590606
7943 23:11:02.591169 Set Vref, RX VrefLevel [Byte0]: 69
7944 23:11:02.593993 [Byte1]: 69
7945 23:11:02.598692
7946 23:11:02.599253 Set Vref, RX VrefLevel [Byte0]: 70
7947 23:11:02.601812 [Byte1]: 70
7948 23:11:02.606633
7949 23:11:02.607194 Set Vref, RX VrefLevel [Byte0]: 71
7950 23:11:02.609087 [Byte1]: 71
7951 23:11:02.613253
7952 23:11:02.613814 Set Vref, RX VrefLevel [Byte0]: 72
7953 23:11:02.616773 [Byte1]: 72
7954 23:11:02.621592
7955 23:11:02.622154 Set Vref, RX VrefLevel [Byte0]: 73
7956 23:11:02.624286 [Byte1]: 73
7957 23:11:02.628992
7958 23:11:02.629553 Set Vref, RX VrefLevel [Byte0]: 74
7959 23:11:02.632388 [Byte1]: 74
7960 23:11:02.636584
7961 23:11:02.637144 Set Vref, RX VrefLevel [Byte0]: 75
7962 23:11:02.639883 [Byte1]: 75
7963 23:11:02.644415
7964 23:11:02.644976 Final RX Vref Byte 0 = 52 to rank0
7965 23:11:02.646958 Final RX Vref Byte 1 = 58 to rank0
7966 23:11:02.650250 Final RX Vref Byte 0 = 52 to rank1
7967 23:11:02.653690 Final RX Vref Byte 1 = 58 to rank1==
7968 23:11:02.657936 Dram Type= 6, Freq= 0, CH_0, rank 0
7969 23:11:02.663503 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7970 23:11:02.664064 ==
7971 23:11:02.664434 DQS Delay:
7972 23:11:02.667103 DQS0 = 0, DQS1 = 0
7973 23:11:02.667724 DQM Delay:
7974 23:11:02.668094 DQM0 = 128, DQM1 = 124
7975 23:11:02.669936 DQ Delay:
7976 23:11:02.673530 DQ0 =128, DQ1 =132, DQ2 =124, DQ3 =124
7977 23:11:02.676802 DQ4 =132, DQ5 =118, DQ6 =138, DQ7 =132
7978 23:11:02.679964 DQ8 =112, DQ9 =112, DQ10 =126, DQ11 =120
7979 23:11:02.683698 DQ12 =132, DQ13 =130, DQ14 =134, DQ15 =132
7980 23:11:02.684262
7981 23:11:02.684628
7982 23:11:02.684964
7983 23:11:02.686756 [DramC_TX_OE_Calibration] TA2
7984 23:11:02.690541 Original DQ_B0 (3 6) =30, OEN = 27
7985 23:11:02.693667 Original DQ_B1 (3 6) =30, OEN = 27
7986 23:11:02.697000 24, 0x0, End_B0=24 End_B1=24
7987 23:11:02.700473 25, 0x0, End_B0=25 End_B1=25
7988 23:11:02.701046 26, 0x0, End_B0=26 End_B1=26
7989 23:11:02.703657 27, 0x0, End_B0=27 End_B1=27
7990 23:11:02.706842 28, 0x0, End_B0=28 End_B1=28
7991 23:11:02.710170 29, 0x0, End_B0=29 End_B1=29
7992 23:11:02.710649 30, 0x0, End_B0=30 End_B1=30
7993 23:11:02.714508 31, 0x4141, End_B0=30 End_B1=30
7994 23:11:02.716660 Byte0 end_step=30 best_step=27
7995 23:11:02.719784 Byte1 end_step=30 best_step=27
7996 23:11:02.723190 Byte0 TX OE(2T, 0.5T) = (3, 3)
7997 23:11:02.726287 Byte1 TX OE(2T, 0.5T) = (3, 3)
7998 23:11:02.726848
7999 23:11:02.727211
8000 23:11:02.732817 [DQSOSCAuto] RK0, (LSB)MR18= 0x1714, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 398 ps
8001 23:11:02.736302 CH0 RK0: MR19=303, MR18=1714
8002 23:11:02.743844 CH0_RK0: MR19=0x303, MR18=0x1714, DQSOSC=398, MR23=63, INC=23, DEC=15
8003 23:11:02.744409
8004 23:11:02.746045 ----->DramcWriteLeveling(PI) begin...
8005 23:11:02.746511 ==
8006 23:11:02.749158 Dram Type= 6, Freq= 0, CH_0, rank 1
8007 23:11:02.752881 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8008 23:11:02.753348 ==
8009 23:11:02.756179 Write leveling (Byte 0): 35 => 35
8010 23:11:02.759529 Write leveling (Byte 1): 26 => 26
8011 23:11:02.762818 DramcWriteLeveling(PI) end<-----
8012 23:11:02.763684
8013 23:11:02.764077 ==
8014 23:11:02.766439 Dram Type= 6, Freq= 0, CH_0, rank 1
8015 23:11:02.769010 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8016 23:11:02.773168 ==
8017 23:11:02.773626 [Gating] SW mode calibration
8018 23:11:02.782829 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8019 23:11:02.785817 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8020 23:11:02.789737 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8021 23:11:02.795649 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8022 23:11:02.799057 1 4 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (1 1)
8023 23:11:02.802055 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8024 23:11:02.809004 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8025 23:11:02.811978 1 4 20 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
8026 23:11:02.816818 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8027 23:11:02.822246 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8028 23:11:02.825749 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8029 23:11:02.828175 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8030 23:11:02.835348 1 5 8 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
8031 23:11:02.838410 1 5 12 | B1->B0 | 3434 2424 | 1 0 | (1 1) (0 0)
8032 23:11:02.841802 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (0 0) (0 0)
8033 23:11:02.847916 1 5 20 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
8034 23:11:02.851399 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8035 23:11:02.855842 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8036 23:11:02.861227 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8037 23:11:02.865074 1 6 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
8038 23:11:02.871161 1 6 8 | B1->B0 | 2323 3939 | 0 0 | (0 0) (0 0)
8039 23:11:02.875207 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8040 23:11:02.877385 1 6 16 | B1->B0 | 3030 4646 | 0 0 | (0 0) (0 0)
8041 23:11:02.884233 1 6 20 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
8042 23:11:02.887762 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8043 23:11:02.891314 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8044 23:11:02.897662 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8045 23:11:02.900574 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8046 23:11:02.903831 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8047 23:11:02.910352 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8048 23:11:02.914142 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8049 23:11:02.917267 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8050 23:11:02.924064 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8051 23:11:02.927758 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8052 23:11:02.930580 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8053 23:11:02.936696 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8054 23:11:02.940209 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8055 23:11:02.944253 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8056 23:11:02.949862 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8057 23:11:02.954405 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8058 23:11:02.956835 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8059 23:11:02.963286 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8060 23:11:02.966420 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8061 23:11:02.969749 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8062 23:11:02.976296 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8063 23:11:02.976851 Total UI for P1: 0, mck2ui 16
8064 23:11:02.983104 best dqsien dly found for B0: ( 1, 9, 4)
8065 23:11:02.986493 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8066 23:11:02.990142 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8067 23:11:02.996233 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8068 23:11:02.999306 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8069 23:11:03.002659 Total UI for P1: 0, mck2ui 16
8070 23:11:03.006698 best dqsien dly found for B1: ( 1, 9, 18)
8071 23:11:03.009357 best DQS0 dly(MCK, UI, PI) = (1, 9, 4)
8072 23:11:03.012558 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8073 23:11:03.013118
8074 23:11:03.015478 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 4)
8075 23:11:03.019172 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8076 23:11:03.022876 [Gating] SW calibration Done
8077 23:11:03.023480 ==
8078 23:11:03.026133 Dram Type= 6, Freq= 0, CH_0, rank 1
8079 23:11:03.029363 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8080 23:11:03.032734 ==
8081 23:11:03.033294 RX Vref Scan: 0
8082 23:11:03.033663
8083 23:11:03.035432 RX Vref 0 -> 0, step: 1
8084 23:11:03.035898
8085 23:11:03.036259 RX Delay 0 -> 252, step: 8
8086 23:11:03.042530 iDelay=192, Bit 0, Center 131 (80 ~ 183) 104
8087 23:11:03.046130 iDelay=192, Bit 1, Center 135 (80 ~ 191) 112
8088 23:11:03.048881 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
8089 23:11:03.052257 iDelay=192, Bit 3, Center 127 (72 ~ 183) 112
8090 23:11:03.055799 iDelay=192, Bit 4, Center 135 (80 ~ 191) 112
8091 23:11:03.062341 iDelay=192, Bit 5, Center 119 (64 ~ 175) 112
8092 23:11:03.065560 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
8093 23:11:03.068931 iDelay=192, Bit 7, Center 135 (80 ~ 191) 112
8094 23:11:03.072149 iDelay=192, Bit 8, Center 119 (64 ~ 175) 112
8095 23:11:03.075579 iDelay=192, Bit 9, Center 115 (64 ~ 167) 104
8096 23:11:03.082042 iDelay=192, Bit 10, Center 127 (72 ~ 183) 112
8097 23:11:03.085187 iDelay=192, Bit 11, Center 119 (64 ~ 175) 112
8098 23:11:03.088449 iDelay=192, Bit 12, Center 131 (72 ~ 191) 120
8099 23:11:03.092051 iDelay=192, Bit 13, Center 135 (80 ~ 191) 112
8100 23:11:03.098720 iDelay=192, Bit 14, Center 139 (88 ~ 191) 104
8101 23:11:03.101622 iDelay=192, Bit 15, Center 135 (80 ~ 191) 112
8102 23:11:03.102085 ==
8103 23:11:03.104927 Dram Type= 6, Freq= 0, CH_0, rank 1
8104 23:11:03.108534 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8105 23:11:03.108998 ==
8106 23:11:03.111475 DQS Delay:
8107 23:11:03.111937 DQS0 = 0, DQS1 = 0
8108 23:11:03.112295 DQM Delay:
8109 23:11:03.114674 DQM0 = 131, DQM1 = 127
8110 23:11:03.115176 DQ Delay:
8111 23:11:03.118391 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
8112 23:11:03.121706 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =135
8113 23:11:03.128127 DQ8 =119, DQ9 =115, DQ10 =127, DQ11 =119
8114 23:11:03.131840 DQ12 =131, DQ13 =135, DQ14 =139, DQ15 =135
8115 23:11:03.132404
8116 23:11:03.132772
8117 23:11:03.133108 ==
8118 23:11:03.134997 Dram Type= 6, Freq= 0, CH_0, rank 1
8119 23:11:03.138424 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8120 23:11:03.138988 ==
8121 23:11:03.139493
8122 23:11:03.139860
8123 23:11:03.141949 TX Vref Scan disable
8124 23:11:03.142408 == TX Byte 0 ==
8125 23:11:03.147918 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8126 23:11:03.151505 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8127 23:11:03.152030 == TX Byte 1 ==
8128 23:11:03.158331 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8129 23:11:03.162472 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8130 23:11:03.163034 ==
8131 23:11:03.164542 Dram Type= 6, Freq= 0, CH_0, rank 1
8132 23:11:03.168003 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8133 23:11:03.168567 ==
8134 23:11:03.183308
8135 23:11:03.187086 TX Vref early break, caculate TX vref
8136 23:11:03.189490 TX Vref=16, minBit 9, minWin=22, winSum=380
8137 23:11:03.192944 TX Vref=18, minBit 8, minWin=23, winSum=385
8138 23:11:03.196224 TX Vref=20, minBit 2, minWin=24, winSum=397
8139 23:11:03.199591 TX Vref=22, minBit 2, minWin=24, winSum=401
8140 23:11:03.202556 TX Vref=24, minBit 10, minWin=24, winSum=413
8141 23:11:03.209275 TX Vref=26, minBit 1, minWin=25, winSum=415
8142 23:11:03.212725 TX Vref=28, minBit 4, minWin=25, winSum=422
8143 23:11:03.216054 TX Vref=30, minBit 11, minWin=25, winSum=417
8144 23:11:03.219339 TX Vref=32, minBit 8, minWin=24, winSum=411
8145 23:11:03.222620 TX Vref=34, minBit 6, minWin=24, winSum=399
8146 23:11:03.228956 [TxChooseVref] Worse bit 4, Min win 25, Win sum 422, Final Vref 28
8147 23:11:03.229377
8148 23:11:03.232248 Final TX Range 0 Vref 28
8149 23:11:03.232669
8150 23:11:03.232998 ==
8151 23:11:03.235537 Dram Type= 6, Freq= 0, CH_0, rank 1
8152 23:11:03.239108 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8153 23:11:03.239593 ==
8154 23:11:03.239933
8155 23:11:03.242010
8156 23:11:03.242424 TX Vref Scan disable
8157 23:11:03.248635 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8158 23:11:03.249053 == TX Byte 0 ==
8159 23:11:03.251957 u2DelayCellOfst[0]=10 cells (3 PI)
8160 23:11:03.255406 u2DelayCellOfst[1]=14 cells (4 PI)
8161 23:11:03.259925 u2DelayCellOfst[2]=7 cells (2 PI)
8162 23:11:03.262503 u2DelayCellOfst[3]=7 cells (2 PI)
8163 23:11:03.265306 u2DelayCellOfst[4]=7 cells (2 PI)
8164 23:11:03.268826 u2DelayCellOfst[5]=0 cells (0 PI)
8165 23:11:03.272294 u2DelayCellOfst[6]=14 cells (4 PI)
8166 23:11:03.275535 u2DelayCellOfst[7]=14 cells (4 PI)
8167 23:11:03.278800 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8168 23:11:03.282158 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8169 23:11:03.285298 == TX Byte 1 ==
8170 23:11:03.288600 u2DelayCellOfst[8]=0 cells (0 PI)
8171 23:11:03.291922 u2DelayCellOfst[9]=0 cells (0 PI)
8172 23:11:03.295143 u2DelayCellOfst[10]=7 cells (2 PI)
8173 23:11:03.298256 u2DelayCellOfst[11]=3 cells (1 PI)
8174 23:11:03.298776 u2DelayCellOfst[12]=10 cells (3 PI)
8175 23:11:03.301566 u2DelayCellOfst[13]=7 cells (2 PI)
8176 23:11:03.304971 u2DelayCellOfst[14]=14 cells (4 PI)
8177 23:11:03.308431 u2DelayCellOfst[15]=10 cells (3 PI)
8178 23:11:03.315231 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8179 23:11:03.318337 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8180 23:11:03.318759 DramC Write-DBI on
8181 23:11:03.321384 ==
8182 23:11:03.321900 Dram Type= 6, Freq= 0, CH_0, rank 1
8183 23:11:03.328206 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8184 23:11:03.328727 ==
8185 23:11:03.329076
8186 23:11:03.329382
8187 23:11:03.331092 TX Vref Scan disable
8188 23:11:03.331532 == TX Byte 0 ==
8189 23:11:03.337639 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
8190 23:11:03.338164 == TX Byte 1 ==
8191 23:11:03.341362 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8192 23:11:03.344862 DramC Write-DBI off
8193 23:11:03.345393
8194 23:11:03.345726 [DATLAT]
8195 23:11:03.347470 Freq=1600, CH0 RK1
8196 23:11:03.347889
8197 23:11:03.348221 DATLAT Default: 0xf
8198 23:11:03.350704 0, 0xFFFF, sum = 0
8199 23:11:03.351128 1, 0xFFFF, sum = 0
8200 23:11:03.354390 2, 0xFFFF, sum = 0
8201 23:11:03.354913 3, 0xFFFF, sum = 0
8202 23:11:03.357867 4, 0xFFFF, sum = 0
8203 23:11:03.361094 5, 0xFFFF, sum = 0
8204 23:11:03.361618 6, 0xFFFF, sum = 0
8205 23:11:03.364126 7, 0xFFFF, sum = 0
8206 23:11:03.364550 8, 0xFFFF, sum = 0
8207 23:11:03.367318 9, 0xFFFF, sum = 0
8208 23:11:03.367962 10, 0xFFFF, sum = 0
8209 23:11:03.371168 11, 0xFFFF, sum = 0
8210 23:11:03.371749 12, 0xFFFF, sum = 0
8211 23:11:03.373733 13, 0xFFFF, sum = 0
8212 23:11:03.374158 14, 0x0, sum = 1
8213 23:11:03.377268 15, 0x0, sum = 2
8214 23:11:03.377791 16, 0x0, sum = 3
8215 23:11:03.380602 17, 0x0, sum = 4
8216 23:11:03.381126 best_step = 15
8217 23:11:03.381458
8218 23:11:03.381766 ==
8219 23:11:03.384246 Dram Type= 6, Freq= 0, CH_0, rank 1
8220 23:11:03.390440 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8221 23:11:03.390961 ==
8222 23:11:03.391296 RX Vref Scan: 0
8223 23:11:03.391671
8224 23:11:03.393712 RX Vref 0 -> 0, step: 1
8225 23:11:03.394231
8226 23:11:03.397390 RX Delay 19 -> 252, step: 4
8227 23:11:03.401442 iDelay=191, Bit 0, Center 126 (79 ~ 174) 96
8228 23:11:03.403462 iDelay=191, Bit 1, Center 130 (79 ~ 182) 104
8229 23:11:03.407640 iDelay=191, Bit 2, Center 124 (71 ~ 178) 108
8230 23:11:03.413356 iDelay=191, Bit 3, Center 124 (71 ~ 178) 108
8231 23:11:03.416912 iDelay=191, Bit 4, Center 132 (83 ~ 182) 100
8232 23:11:03.420270 iDelay=191, Bit 5, Center 118 (63 ~ 174) 112
8233 23:11:03.423309 iDelay=191, Bit 6, Center 138 (91 ~ 186) 96
8234 23:11:03.426821 iDelay=191, Bit 7, Center 134 (83 ~ 186) 104
8235 23:11:03.433620 iDelay=191, Bit 8, Center 114 (63 ~ 166) 104
8236 23:11:03.436477 iDelay=191, Bit 9, Center 110 (59 ~ 162) 104
8237 23:11:03.439630 iDelay=191, Bit 10, Center 124 (71 ~ 178) 108
8238 23:11:03.444467 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8239 23:11:03.446420 iDelay=191, Bit 12, Center 128 (75 ~ 182) 108
8240 23:11:03.452788 iDelay=191, Bit 13, Center 130 (79 ~ 182) 104
8241 23:11:03.456313 iDelay=191, Bit 14, Center 136 (83 ~ 190) 108
8242 23:11:03.459596 iDelay=191, Bit 15, Center 132 (79 ~ 186) 108
8243 23:11:03.460162 ==
8244 23:11:03.462785 Dram Type= 6, Freq= 0, CH_0, rank 1
8245 23:11:03.466525 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8246 23:11:03.469684 ==
8247 23:11:03.470350 DQS Delay:
8248 23:11:03.470740 DQS0 = 0, DQS1 = 0
8249 23:11:03.472927 DQM Delay:
8250 23:11:03.473382 DQM0 = 128, DQM1 = 124
8251 23:11:03.475907 DQ Delay:
8252 23:11:03.479314 DQ0 =126, DQ1 =130, DQ2 =124, DQ3 =124
8253 23:11:03.482885 DQ4 =132, DQ5 =118, DQ6 =138, DQ7 =134
8254 23:11:03.485931 DQ8 =114, DQ9 =110, DQ10 =124, DQ11 =118
8255 23:11:03.489902 DQ12 =128, DQ13 =130, DQ14 =136, DQ15 =132
8256 23:11:03.490455
8257 23:11:03.490819
8258 23:11:03.491152
8259 23:11:03.492978 [DramC_TX_OE_Calibration] TA2
8260 23:11:03.495916 Original DQ_B0 (3 6) =30, OEN = 27
8261 23:11:03.499326 Original DQ_B1 (3 6) =30, OEN = 27
8262 23:11:03.502188 24, 0x0, End_B0=24 End_B1=24
8263 23:11:03.502652 25, 0x0, End_B0=25 End_B1=25
8264 23:11:03.505820 26, 0x0, End_B0=26 End_B1=26
8265 23:11:03.509408 27, 0x0, End_B0=27 End_B1=27
8266 23:11:03.512472 28, 0x0, End_B0=28 End_B1=28
8267 23:11:03.515603 29, 0x0, End_B0=29 End_B1=29
8268 23:11:03.516156 30, 0x0, End_B0=30 End_B1=30
8269 23:11:03.519589 31, 0x4141, End_B0=30 End_B1=30
8270 23:11:03.522561 Byte0 end_step=30 best_step=27
8271 23:11:03.525493 Byte1 end_step=30 best_step=27
8272 23:11:03.528631 Byte0 TX OE(2T, 0.5T) = (3, 3)
8273 23:11:03.532306 Byte1 TX OE(2T, 0.5T) = (3, 3)
8274 23:11:03.532925
8275 23:11:03.533297
8276 23:11:03.539002 [DQSOSCAuto] RK1, (LSB)MR18= 0x1614, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 398 ps
8277 23:11:03.541907 CH0 RK1: MR19=303, MR18=1614
8278 23:11:03.548276 CH0_RK1: MR19=0x303, MR18=0x1614, DQSOSC=398, MR23=63, INC=23, DEC=15
8279 23:11:03.552412 [RxdqsGatingPostProcess] freq 1600
8280 23:11:03.555597 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8281 23:11:03.558692 best DQS0 dly(2T, 0.5T) = (1, 1)
8282 23:11:03.561751 best DQS1 dly(2T, 0.5T) = (1, 1)
8283 23:11:03.565003 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8284 23:11:03.567989 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8285 23:11:03.571224 best DQS0 dly(2T, 0.5T) = (1, 1)
8286 23:11:03.574953 best DQS1 dly(2T, 0.5T) = (1, 1)
8287 23:11:03.578598 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8288 23:11:03.581447 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8289 23:11:03.584263 Pre-setting of DQS Precalculation
8290 23:11:03.588242 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8291 23:11:03.588803 ==
8292 23:11:03.591237 Dram Type= 6, Freq= 0, CH_1, rank 0
8293 23:11:03.598425 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8294 23:11:03.598981 ==
8295 23:11:03.600818 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8296 23:11:03.607759 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8297 23:11:03.611778 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8298 23:11:03.617541 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8299 23:11:03.625798 [CA 0] Center 42 (12~72) winsize 61
8300 23:11:03.629127 [CA 1] Center 42 (12~72) winsize 61
8301 23:11:03.632260 [CA 2] Center 38 (9~67) winsize 59
8302 23:11:03.635673 [CA 3] Center 36 (7~66) winsize 60
8303 23:11:03.638307 [CA 4] Center 37 (8~67) winsize 60
8304 23:11:03.641733 [CA 5] Center 36 (7~66) winsize 60
8305 23:11:03.642264
8306 23:11:03.645057 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8307 23:11:03.645521
8308 23:11:03.652026 [CATrainingPosCal] consider 1 rank data
8309 23:11:03.652491 u2DelayCellTimex100 = 275/100 ps
8310 23:11:03.658309 CA0 delay=42 (12~72),Diff = 6 PI (21 cell)
8311 23:11:03.661341 CA1 delay=42 (12~72),Diff = 6 PI (21 cell)
8312 23:11:03.665020 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8313 23:11:03.668436 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8314 23:11:03.671656 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8315 23:11:03.675193 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8316 23:11:03.675689
8317 23:11:03.678471 CA PerBit enable=1, Macro0, CA PI delay=36
8318 23:11:03.679024
8319 23:11:03.681697 [CBTSetCACLKResult] CA Dly = 36
8320 23:11:03.685349 CS Dly: 7 (0~38)
8321 23:11:03.687956 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8322 23:11:03.691995 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8323 23:11:03.692561 ==
8324 23:11:03.695068 Dram Type= 6, Freq= 0, CH_1, rank 1
8325 23:11:03.701087 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8326 23:11:03.701651 ==
8327 23:11:03.704395 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8328 23:11:03.711192 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8329 23:11:03.714300 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8330 23:11:03.721062 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8331 23:11:03.728761 [CA 0] Center 42 (12~72) winsize 61
8332 23:11:03.732313 [CA 1] Center 43 (14~72) winsize 59
8333 23:11:03.735695 [CA 2] Center 38 (8~68) winsize 61
8334 23:11:03.738415 [CA 3] Center 36 (7~66) winsize 60
8335 23:11:03.741429 [CA 4] Center 37 (8~67) winsize 60
8336 23:11:03.744948 [CA 5] Center 37 (7~67) winsize 61
8337 23:11:03.745412
8338 23:11:03.748546 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8339 23:11:03.749013
8340 23:11:03.754977 [CATrainingPosCal] consider 2 rank data
8341 23:11:03.755585 u2DelayCellTimex100 = 275/100 ps
8342 23:11:03.761631 CA0 delay=42 (12~72),Diff = 6 PI (21 cell)
8343 23:11:03.764673 CA1 delay=43 (14~72),Diff = 7 PI (24 cell)
8344 23:11:03.768503 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8345 23:11:03.771587 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8346 23:11:03.774694 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8347 23:11:03.777995 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8348 23:11:03.778546
8349 23:11:03.781171 CA PerBit enable=1, Macro0, CA PI delay=36
8350 23:11:03.781718
8351 23:11:03.784332 [CBTSetCACLKResult] CA Dly = 36
8352 23:11:03.788264 CS Dly: 9 (0~42)
8353 23:11:03.791179 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8354 23:11:03.794218 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8355 23:11:03.794769
8356 23:11:03.797563 ----->DramcWriteLeveling(PI) begin...
8357 23:11:03.800946 ==
8358 23:11:03.801505 Dram Type= 6, Freq= 0, CH_1, rank 0
8359 23:11:03.807578 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8360 23:11:03.808037 ==
8361 23:11:03.810562 Write leveling (Byte 0): 23 => 23
8362 23:11:03.813867 Write leveling (Byte 1): 27 => 27
8363 23:11:03.817131 DramcWriteLeveling(PI) end<-----
8364 23:11:03.817541
8365 23:11:03.817864 ==
8366 23:11:03.820502 Dram Type= 6, Freq= 0, CH_1, rank 0
8367 23:11:03.823501 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8368 23:11:03.823930 ==
8369 23:11:03.827688 [Gating] SW mode calibration
8370 23:11:03.833841 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8371 23:11:03.839918 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8372 23:11:03.843824 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8373 23:11:03.847035 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8374 23:11:03.854762 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8375 23:11:03.857058 1 4 12 | B1->B0 | 2525 3434 | 0 0 | (0 0) (0 0)
8376 23:11:03.860426 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8377 23:11:03.866952 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8378 23:11:03.870283 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8379 23:11:03.873578 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8380 23:11:03.879925 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8381 23:11:03.883447 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8382 23:11:03.886085 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8383 23:11:03.893274 1 5 12 | B1->B0 | 3030 2424 | 1 0 | (1 0) (1 0)
8384 23:11:03.896633 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8385 23:11:03.899744 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8386 23:11:03.906943 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8387 23:11:03.909106 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8388 23:11:03.912578 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8389 23:11:03.919483 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8390 23:11:03.923103 1 6 8 | B1->B0 | 2424 2626 | 0 0 | (0 0) (0 0)
8391 23:11:03.925905 1 6 12 | B1->B0 | 2727 4545 | 0 0 | (0 0) (0 0)
8392 23:11:03.932174 1 6 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8393 23:11:03.936069 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8394 23:11:03.939033 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8395 23:11:03.945851 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8396 23:11:03.948862 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8397 23:11:03.952056 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8398 23:11:03.958779 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8399 23:11:03.962614 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8400 23:11:03.965399 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8401 23:11:03.971898 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8402 23:11:03.975678 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8403 23:11:03.978570 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8404 23:11:03.984758 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8405 23:11:03.988473 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8406 23:11:03.991331 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8407 23:11:03.998365 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8408 23:11:04.002138 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8409 23:11:04.004747 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8410 23:11:04.011760 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8411 23:11:04.015261 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8412 23:11:04.018184 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8413 23:11:04.024460 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8414 23:11:04.027753 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8415 23:11:04.031418 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8416 23:11:04.038046 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8417 23:11:04.041513 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8418 23:11:04.044185 Total UI for P1: 0, mck2ui 16
8419 23:11:04.047807 best dqsien dly found for B0: ( 1, 9, 14)
8420 23:11:04.051141 Total UI for P1: 0, mck2ui 16
8421 23:11:04.054158 best dqsien dly found for B1: ( 1, 9, 12)
8422 23:11:04.057787 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8423 23:11:04.061400 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8424 23:11:04.061963
8425 23:11:04.064789 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8426 23:11:04.067423 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8427 23:11:04.071082 [Gating] SW calibration Done
8428 23:11:04.071698 ==
8429 23:11:04.074277 Dram Type= 6, Freq= 0, CH_1, rank 0
8430 23:11:04.077779 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8431 23:11:04.080678 ==
8432 23:11:04.081141 RX Vref Scan: 0
8433 23:11:04.081508
8434 23:11:04.084561 RX Vref 0 -> 0, step: 1
8435 23:11:04.085023
8436 23:11:04.087094 RX Delay 0 -> 252, step: 8
8437 23:11:04.090808 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8438 23:11:04.094138 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8439 23:11:04.097118 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8440 23:11:04.101120 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8441 23:11:04.107121 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8442 23:11:04.110598 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8443 23:11:04.113599 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8444 23:11:04.116908 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8445 23:11:04.120301 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8446 23:11:04.127141 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8447 23:11:04.130051 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8448 23:11:04.133440 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8449 23:11:04.136658 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8450 23:11:04.143673 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8451 23:11:04.147249 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8452 23:11:04.150441 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8453 23:11:04.150962 ==
8454 23:11:04.152800 Dram Type= 6, Freq= 0, CH_1, rank 0
8455 23:11:04.156583 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8456 23:11:04.157111 ==
8457 23:11:04.159303 DQS Delay:
8458 23:11:04.159770 DQS0 = 0, DQS1 = 0
8459 23:11:04.163690 DQM Delay:
8460 23:11:04.164211 DQM0 = 134, DQM1 = 130
8461 23:11:04.166640 DQ Delay:
8462 23:11:04.170219 DQ0 =139, DQ1 =127, DQ2 =123, DQ3 =135
8463 23:11:04.173147 DQ4 =131, DQ5 =143, DQ6 =147, DQ7 =127
8464 23:11:04.176372 DQ8 =111, DQ9 =119, DQ10 =131, DQ11 =127
8465 23:11:04.179727 DQ12 =139, DQ13 =143, DQ14 =135, DQ15 =135
8466 23:11:04.180145
8467 23:11:04.180479
8468 23:11:04.180786 ==
8469 23:11:04.183226 Dram Type= 6, Freq= 0, CH_1, rank 0
8470 23:11:04.186785 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8471 23:11:04.187290 ==
8472 23:11:04.187695
8473 23:11:04.189785
8474 23:11:04.190302 TX Vref Scan disable
8475 23:11:04.193245 == TX Byte 0 ==
8476 23:11:04.195543 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8477 23:11:04.199423 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8478 23:11:04.202545 == TX Byte 1 ==
8479 23:11:04.206137 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8480 23:11:04.208856 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8481 23:11:04.209273 ==
8482 23:11:04.212325 Dram Type= 6, Freq= 0, CH_1, rank 0
8483 23:11:04.218719 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8484 23:11:04.219257 ==
8485 23:11:04.232612
8486 23:11:04.236111 TX Vref early break, caculate TX vref
8487 23:11:04.238556 TX Vref=16, minBit 8, minWin=21, winSum=366
8488 23:11:04.241769 TX Vref=18, minBit 8, minWin=21, winSum=373
8489 23:11:04.244761 TX Vref=20, minBit 8, minWin=23, winSum=388
8490 23:11:04.248694 TX Vref=22, minBit 8, minWin=23, winSum=394
8491 23:11:04.251494 TX Vref=24, minBit 1, minWin=25, winSum=406
8492 23:11:04.258252 TX Vref=26, minBit 8, minWin=24, winSum=411
8493 23:11:04.261861 TX Vref=28, minBit 0, minWin=25, winSum=417
8494 23:11:04.264721 TX Vref=30, minBit 9, minWin=24, winSum=413
8495 23:11:04.267815 TX Vref=32, minBit 9, minWin=24, winSum=406
8496 23:11:04.272549 TX Vref=34, minBit 0, minWin=24, winSum=398
8497 23:11:04.277902 TX Vref=36, minBit 9, minWin=22, winSum=385
8498 23:11:04.281487 [TxChooseVref] Worse bit 0, Min win 25, Win sum 417, Final Vref 28
8499 23:11:04.281905
8500 23:11:04.284772 Final TX Range 0 Vref 28
8501 23:11:04.285189
8502 23:11:04.285513 ==
8503 23:11:04.288236 Dram Type= 6, Freq= 0, CH_1, rank 0
8504 23:11:04.291264 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8505 23:11:04.294324 ==
8506 23:11:04.294857
8507 23:11:04.295318
8508 23:11:04.295681 TX Vref Scan disable
8509 23:11:04.301324 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8510 23:11:04.301870 == TX Byte 0 ==
8511 23:11:04.304043 u2DelayCellOfst[0]=14 cells (4 PI)
8512 23:11:04.307959 u2DelayCellOfst[1]=7 cells (2 PI)
8513 23:11:04.311569 u2DelayCellOfst[2]=0 cells (0 PI)
8514 23:11:04.314361 u2DelayCellOfst[3]=3 cells (1 PI)
8515 23:11:04.317904 u2DelayCellOfst[4]=7 cells (2 PI)
8516 23:11:04.320558 u2DelayCellOfst[5]=14 cells (4 PI)
8517 23:11:04.324005 u2DelayCellOfst[6]=14 cells (4 PI)
8518 23:11:04.328548 u2DelayCellOfst[7]=3 cells (1 PI)
8519 23:11:04.330454 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8520 23:11:04.333696 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8521 23:11:04.337478 == TX Byte 1 ==
8522 23:11:04.340370 u2DelayCellOfst[8]=0 cells (0 PI)
8523 23:11:04.343394 u2DelayCellOfst[9]=3 cells (1 PI)
8524 23:11:04.347440 u2DelayCellOfst[10]=10 cells (3 PI)
8525 23:11:04.350591 u2DelayCellOfst[11]=7 cells (2 PI)
8526 23:11:04.353571 u2DelayCellOfst[12]=14 cells (4 PI)
8527 23:11:04.357120 u2DelayCellOfst[13]=14 cells (4 PI)
8528 23:11:04.360632 u2DelayCellOfst[14]=17 cells (5 PI)
8529 23:11:04.361141 u2DelayCellOfst[15]=17 cells (5 PI)
8530 23:11:04.367127 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8531 23:11:04.370197 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8532 23:11:04.374704 DramC Write-DBI on
8533 23:11:04.375238 ==
8534 23:11:04.376476 Dram Type= 6, Freq= 0, CH_1, rank 0
8535 23:11:04.379850 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8536 23:11:04.380400 ==
8537 23:11:04.380763
8538 23:11:04.381070
8539 23:11:04.383264 TX Vref Scan disable
8540 23:11:04.383715 == TX Byte 0 ==
8541 23:11:04.390180 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8542 23:11:04.390689 == TX Byte 1 ==
8543 23:11:04.396750 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8544 23:11:04.397259 DramC Write-DBI off
8545 23:11:04.397590
8546 23:11:04.397890 [DATLAT]
8547 23:11:04.399925 Freq=1600, CH1 RK0
8548 23:11:04.400432
8549 23:11:04.400760 DATLAT Default: 0xf
8550 23:11:04.402950 0, 0xFFFF, sum = 0
8551 23:11:04.406548 1, 0xFFFF, sum = 0
8552 23:11:04.407085 2, 0xFFFF, sum = 0
8553 23:11:04.409596 3, 0xFFFF, sum = 0
8554 23:11:04.410016 4, 0xFFFF, sum = 0
8555 23:11:04.412825 5, 0xFFFF, sum = 0
8556 23:11:04.413246 6, 0xFFFF, sum = 0
8557 23:11:04.416111 7, 0xFFFF, sum = 0
8558 23:11:04.416529 8, 0xFFFF, sum = 0
8559 23:11:04.419535 9, 0xFFFF, sum = 0
8560 23:11:04.420055 10, 0xFFFF, sum = 0
8561 23:11:04.422916 11, 0xFFFF, sum = 0
8562 23:11:04.423484 12, 0xFFFF, sum = 0
8563 23:11:04.426084 13, 0xFFFF, sum = 0
8564 23:11:04.426599 14, 0x0, sum = 1
8565 23:11:04.429505 15, 0x0, sum = 2
8566 23:11:04.430031 16, 0x0, sum = 3
8567 23:11:04.432549 17, 0x0, sum = 4
8568 23:11:04.432969 best_step = 15
8569 23:11:04.433299
8570 23:11:04.433602 ==
8571 23:11:04.436199 Dram Type= 6, Freq= 0, CH_1, rank 0
8572 23:11:04.442832 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8573 23:11:04.443343 ==
8574 23:11:04.443766 RX Vref Scan: 1
8575 23:11:04.444079
8576 23:11:04.446081 Set Vref Range= 24 -> 127
8577 23:11:04.446629
8578 23:11:04.449259 RX Vref 24 -> 127, step: 1
8579 23:11:04.449674
8580 23:11:04.450003 RX Delay 11 -> 252, step: 4
8581 23:11:04.452343
8582 23:11:04.452755 Set Vref, RX VrefLevel [Byte0]: 24
8583 23:11:04.455569 [Byte1]: 24
8584 23:11:04.460116
8585 23:11:04.460529 Set Vref, RX VrefLevel [Byte0]: 25
8586 23:11:04.463210 [Byte1]: 25
8587 23:11:04.467900
8588 23:11:04.468418 Set Vref, RX VrefLevel [Byte0]: 26
8589 23:11:04.470817 [Byte1]: 26
8590 23:11:04.475781
8591 23:11:04.476288 Set Vref, RX VrefLevel [Byte0]: 27
8592 23:11:04.478679 [Byte1]: 27
8593 23:11:04.483008
8594 23:11:04.483566 Set Vref, RX VrefLevel [Byte0]: 28
8595 23:11:04.486333 [Byte1]: 28
8596 23:11:04.490692
8597 23:11:04.491198 Set Vref, RX VrefLevel [Byte0]: 29
8598 23:11:04.494103 [Byte1]: 29
8599 23:11:04.498223
8600 23:11:04.498731 Set Vref, RX VrefLevel [Byte0]: 30
8601 23:11:04.502109 [Byte1]: 30
8602 23:11:04.506028
8603 23:11:04.506444 Set Vref, RX VrefLevel [Byte0]: 31
8604 23:11:04.509755 [Byte1]: 31
8605 23:11:04.513248
8606 23:11:04.513821 Set Vref, RX VrefLevel [Byte0]: 32
8607 23:11:04.516629 [Byte1]: 32
8608 23:11:04.521405
8609 23:11:04.521912 Set Vref, RX VrefLevel [Byte0]: 33
8610 23:11:04.524038 [Byte1]: 33
8611 23:11:04.528739
8612 23:11:04.529272 Set Vref, RX VrefLevel [Byte0]: 34
8613 23:11:04.531960 [Byte1]: 34
8614 23:11:04.537272
8615 23:11:04.537842 Set Vref, RX VrefLevel [Byte0]: 35
8616 23:11:04.539886 [Byte1]: 35
8617 23:11:04.543971
8618 23:11:04.544522 Set Vref, RX VrefLevel [Byte0]: 36
8619 23:11:04.547186 [Byte1]: 36
8620 23:11:04.551240
8621 23:11:04.551760 Set Vref, RX VrefLevel [Byte0]: 37
8622 23:11:04.554768 [Byte1]: 37
8623 23:11:04.559188
8624 23:11:04.559830 Set Vref, RX VrefLevel [Byte0]: 38
8625 23:11:04.562338 [Byte1]: 38
8626 23:11:04.566863
8627 23:11:04.567456 Set Vref, RX VrefLevel [Byte0]: 39
8628 23:11:04.570148 [Byte1]: 39
8629 23:11:04.574819
8630 23:11:04.575544 Set Vref, RX VrefLevel [Byte0]: 40
8631 23:11:04.577830 [Byte1]: 40
8632 23:11:04.582094
8633 23:11:04.582571 Set Vref, RX VrefLevel [Byte0]: 41
8634 23:11:04.585382 [Byte1]: 41
8635 23:11:04.589668
8636 23:11:04.590123 Set Vref, RX VrefLevel [Byte0]: 42
8637 23:11:04.592920 [Byte1]: 42
8638 23:11:04.597206
8639 23:11:04.597779 Set Vref, RX VrefLevel [Byte0]: 43
8640 23:11:04.600694 [Byte1]: 43
8641 23:11:04.605018
8642 23:11:04.605484 Set Vref, RX VrefLevel [Byte0]: 44
8643 23:11:04.608265 [Byte1]: 44
8644 23:11:04.612886
8645 23:11:04.613446 Set Vref, RX VrefLevel [Byte0]: 45
8646 23:11:04.615482 [Byte1]: 45
8647 23:11:04.620499
8648 23:11:04.621060 Set Vref, RX VrefLevel [Byte0]: 46
8649 23:11:04.623335 [Byte1]: 46
8650 23:11:04.628042
8651 23:11:04.628599 Set Vref, RX VrefLevel [Byte0]: 47
8652 23:11:04.631155 [Byte1]: 47
8653 23:11:04.635423
8654 23:11:04.635992 Set Vref, RX VrefLevel [Byte0]: 48
8655 23:11:04.638571 [Byte1]: 48
8656 23:11:04.643306
8657 23:11:04.643830 Set Vref, RX VrefLevel [Byte0]: 49
8658 23:11:04.646865 [Byte1]: 49
8659 23:11:04.650822
8660 23:11:04.651284 Set Vref, RX VrefLevel [Byte0]: 50
8661 23:11:04.654060 [Byte1]: 50
8662 23:11:04.658009
8663 23:11:04.658568 Set Vref, RX VrefLevel [Byte0]: 51
8664 23:11:04.661281 [Byte1]: 51
8665 23:11:04.666665
8666 23:11:04.667219 Set Vref, RX VrefLevel [Byte0]: 52
8667 23:11:04.668781 [Byte1]: 52
8668 23:11:04.673627
8669 23:11:04.674188 Set Vref, RX VrefLevel [Byte0]: 53
8670 23:11:04.676471 [Byte1]: 53
8671 23:11:04.681081
8672 23:11:04.684671 Set Vref, RX VrefLevel [Byte0]: 54
8673 23:11:04.687482 [Byte1]: 54
8674 23:11:04.687948
8675 23:11:04.690607 Set Vref, RX VrefLevel [Byte0]: 55
8676 23:11:04.694307 [Byte1]: 55
8677 23:11:04.694867
8678 23:11:04.697148 Set Vref, RX VrefLevel [Byte0]: 56
8679 23:11:04.700503 [Byte1]: 56
8680 23:11:04.703837
8681 23:11:04.704301 Set Vref, RX VrefLevel [Byte0]: 57
8682 23:11:04.707355 [Byte1]: 57
8683 23:11:04.711137
8684 23:11:04.711650 Set Vref, RX VrefLevel [Byte0]: 58
8685 23:11:04.714715 [Byte1]: 58
8686 23:11:04.719344
8687 23:11:04.719948 Set Vref, RX VrefLevel [Byte0]: 59
8688 23:11:04.722784 [Byte1]: 59
8689 23:11:04.727066
8690 23:11:04.727671 Set Vref, RX VrefLevel [Byte0]: 60
8691 23:11:04.729846 [Byte1]: 60
8692 23:11:04.734301
8693 23:11:04.734867 Set Vref, RX VrefLevel [Byte0]: 61
8694 23:11:04.737330 [Byte1]: 61
8695 23:11:04.741576
8696 23:11:04.742041 Set Vref, RX VrefLevel [Byte0]: 62
8697 23:11:04.745563 [Byte1]: 62
8698 23:11:04.749493
8699 23:11:04.749967 Set Vref, RX VrefLevel [Byte0]: 63
8700 23:11:04.752953 [Byte1]: 63
8701 23:11:04.757437
8702 23:11:04.757996 Set Vref, RX VrefLevel [Byte0]: 64
8703 23:11:04.760059 [Byte1]: 64
8704 23:11:04.764579
8705 23:11:04.765136 Set Vref, RX VrefLevel [Byte0]: 65
8706 23:11:04.767838 [Byte1]: 65
8707 23:11:04.772320
8708 23:11:04.772877 Set Vref, RX VrefLevel [Byte0]: 66
8709 23:11:04.775789 [Byte1]: 66
8710 23:11:04.779729
8711 23:11:04.783133 Set Vref, RX VrefLevel [Byte0]: 67
8712 23:11:04.786366 [Byte1]: 67
8713 23:11:04.786924
8714 23:11:04.790151 Set Vref, RX VrefLevel [Byte0]: 68
8715 23:11:04.793063 [Byte1]: 68
8716 23:11:04.793624
8717 23:11:04.796006 Set Vref, RX VrefLevel [Byte0]: 69
8718 23:11:04.799421 [Byte1]: 69
8719 23:11:04.802754
8720 23:11:04.803315 Set Vref, RX VrefLevel [Byte0]: 70
8721 23:11:04.806043 [Byte1]: 70
8722 23:11:04.810655
8723 23:11:04.811226 Set Vref, RX VrefLevel [Byte0]: 71
8724 23:11:04.814361 [Byte1]: 71
8725 23:11:04.817867
8726 23:11:04.818344 Set Vref, RX VrefLevel [Byte0]: 72
8727 23:11:04.821411 [Byte1]: 72
8728 23:11:04.825326
8729 23:11:04.825904 Set Vref, RX VrefLevel [Byte0]: 73
8730 23:11:04.828726 [Byte1]: 73
8731 23:11:04.833067
8732 23:11:04.833627 Set Vref, RX VrefLevel [Byte0]: 74
8733 23:11:04.836964 [Byte1]: 74
8734 23:11:04.840855
8735 23:11:04.841314 Final RX Vref Byte 0 = 59 to rank0
8736 23:11:04.843733 Final RX Vref Byte 1 = 54 to rank0
8737 23:11:04.847450 Final RX Vref Byte 0 = 59 to rank1
8738 23:11:04.850615 Final RX Vref Byte 1 = 54 to rank1==
8739 23:11:04.854791 Dram Type= 6, Freq= 0, CH_1, rank 0
8740 23:11:04.860852 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8741 23:11:04.861418 ==
8742 23:11:04.861787 DQS Delay:
8743 23:11:04.863767 DQS0 = 0, DQS1 = 0
8744 23:11:04.864483 DQM Delay:
8745 23:11:04.864863 DQM0 = 132, DQM1 = 128
8746 23:11:04.867452 DQ Delay:
8747 23:11:04.870848 DQ0 =138, DQ1 =130, DQ2 =118, DQ3 =132
8748 23:11:04.874097 DQ4 =128, DQ5 =140, DQ6 =144, DQ7 =126
8749 23:11:04.877284 DQ8 =112, DQ9 =116, DQ10 =130, DQ11 =122
8750 23:11:04.880346 DQ12 =138, DQ13 =136, DQ14 =134, DQ15 =136
8751 23:11:04.880905
8752 23:11:04.881273
8753 23:11:04.881611
8754 23:11:04.884105 [DramC_TX_OE_Calibration] TA2
8755 23:11:04.887027 Original DQ_B0 (3 6) =30, OEN = 27
8756 23:11:04.890043 Original DQ_B1 (3 6) =30, OEN = 27
8757 23:11:04.893970 24, 0x0, End_B0=24 End_B1=24
8758 23:11:04.896529 25, 0x0, End_B0=25 End_B1=25
8759 23:11:04.897097 26, 0x0, End_B0=26 End_B1=26
8760 23:11:04.900524 27, 0x0, End_B0=27 End_B1=27
8761 23:11:04.904064 28, 0x0, End_B0=28 End_B1=28
8762 23:11:04.906454 29, 0x0, End_B0=29 End_B1=29
8763 23:11:04.906923 30, 0x0, End_B0=30 End_B1=30
8764 23:11:04.910087 31, 0x4141, End_B0=30 End_B1=30
8765 23:11:04.912982 Byte0 end_step=30 best_step=27
8766 23:11:04.916390 Byte1 end_step=30 best_step=27
8767 23:11:04.919680 Byte0 TX OE(2T, 0.5T) = (3, 3)
8768 23:11:04.922839 Byte1 TX OE(2T, 0.5T) = (3, 3)
8769 23:11:04.923255
8770 23:11:04.923637
8771 23:11:04.929500 [DQSOSCAuto] RK0, (LSB)MR18= 0xb13, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 404 ps
8772 23:11:04.934161 CH1 RK0: MR19=303, MR18=B13
8773 23:11:04.939012 CH1_RK0: MR19=0x303, MR18=0xB13, DQSOSC=400, MR23=63, INC=23, DEC=15
8774 23:11:04.939475
8775 23:11:04.942430 ----->DramcWriteLeveling(PI) begin...
8776 23:11:04.942960 ==
8777 23:11:04.946042 Dram Type= 6, Freq= 0, CH_1, rank 1
8778 23:11:04.949059 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8779 23:11:04.949481 ==
8780 23:11:04.952131 Write leveling (Byte 0): 22 => 22
8781 23:11:04.955325 Write leveling (Byte 1): 26 => 26
8782 23:11:04.959486 DramcWriteLeveling(PI) end<-----
8783 23:11:04.960017
8784 23:11:04.960351 ==
8785 23:11:04.962743 Dram Type= 6, Freq= 0, CH_1, rank 1
8786 23:11:04.968940 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8787 23:11:04.969465 ==
8788 23:11:04.969800 [Gating] SW mode calibration
8789 23:11:04.978690 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8790 23:11:04.982497 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8791 23:11:04.989931 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8792 23:11:04.991648 1 4 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8793 23:11:04.995730 1 4 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8794 23:11:05.001824 1 4 12 | B1->B0 | 2727 3434 | 0 1 | (0 0) (1 1)
8795 23:11:05.004760 1 4 16 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
8796 23:11:05.008907 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8797 23:11:05.015016 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8798 23:11:05.018461 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8799 23:11:05.021202 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8800 23:11:05.028220 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8801 23:11:05.031058 1 5 8 | B1->B0 | 3434 2929 | 1 0 | (1 0) (1 0)
8802 23:11:05.034653 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8803 23:11:05.040946 1 5 16 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
8804 23:11:05.044393 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8805 23:11:05.048143 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8806 23:11:05.054510 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8807 23:11:05.058935 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8808 23:11:05.060562 1 6 4 | B1->B0 | 2323 2525 | 0 1 | (0 0) (0 0)
8809 23:11:05.068092 1 6 8 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
8810 23:11:05.070924 1 6 12 | B1->B0 | 2828 4646 | 0 0 | (0 0) (0 0)
8811 23:11:05.074574 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8812 23:11:05.080373 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8813 23:11:05.083872 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8814 23:11:05.087232 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8815 23:11:05.094201 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8816 23:11:05.097308 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8817 23:11:05.100562 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8818 23:11:05.107136 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8819 23:11:05.110066 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8820 23:11:05.114125 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8821 23:11:05.120149 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8822 23:11:05.123333 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8823 23:11:05.126801 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8824 23:11:05.133055 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8825 23:11:05.136356 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8826 23:11:05.139493 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8827 23:11:05.146688 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8828 23:11:05.149351 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8829 23:11:05.153273 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8830 23:11:05.159336 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8831 23:11:05.162766 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8832 23:11:05.166702 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8833 23:11:05.172240 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8834 23:11:05.175797 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8835 23:11:05.179345 Total UI for P1: 0, mck2ui 16
8836 23:11:05.182306 best dqsien dly found for B0: ( 1, 9, 6)
8837 23:11:05.186027 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8838 23:11:05.189429 Total UI for P1: 0, mck2ui 16
8839 23:11:05.192319 best dqsien dly found for B1: ( 1, 9, 12)
8840 23:11:05.196178 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8841 23:11:05.199744 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8842 23:11:05.200275
8843 23:11:05.206092 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8844 23:11:05.209280 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8845 23:11:05.212658 [Gating] SW calibration Done
8846 23:11:05.213224 ==
8847 23:11:05.216356 Dram Type= 6, Freq= 0, CH_1, rank 1
8848 23:11:05.219087 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8849 23:11:05.219679 ==
8850 23:11:05.220050 RX Vref Scan: 0
8851 23:11:05.220390
8852 23:11:05.222206 RX Vref 0 -> 0, step: 1
8853 23:11:05.222767
8854 23:11:05.225760 RX Delay 0 -> 252, step: 8
8855 23:11:05.228657 iDelay=200, Bit 0, Center 139 (80 ~ 199) 120
8856 23:11:05.231971 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8857 23:11:05.238803 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8858 23:11:05.242169 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8859 23:11:05.245038 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8860 23:11:05.248819 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8861 23:11:05.251737 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8862 23:11:05.258677 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8863 23:11:05.261516 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8864 23:11:05.264597 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8865 23:11:05.268203 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8866 23:11:05.271834 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8867 23:11:05.278229 iDelay=200, Bit 12, Center 139 (80 ~ 199) 120
8868 23:11:05.281691 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8869 23:11:05.284541 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8870 23:11:05.287848 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8871 23:11:05.288308 ==
8872 23:11:05.291214 Dram Type= 6, Freq= 0, CH_1, rank 1
8873 23:11:05.298039 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8874 23:11:05.298601 ==
8875 23:11:05.298969 DQS Delay:
8876 23:11:05.301223 DQS0 = 0, DQS1 = 0
8877 23:11:05.301830 DQM Delay:
8878 23:11:05.304262 DQM0 = 133, DQM1 = 130
8879 23:11:05.304723 DQ Delay:
8880 23:11:05.307893 DQ0 =139, DQ1 =131, DQ2 =119, DQ3 =131
8881 23:11:05.311197 DQ4 =131, DQ5 =143, DQ6 =139, DQ7 =131
8882 23:11:05.314448 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =123
8883 23:11:05.317773 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =139
8884 23:11:05.318332
8885 23:11:05.318696
8886 23:11:05.319036 ==
8887 23:11:05.320675 Dram Type= 6, Freq= 0, CH_1, rank 1
8888 23:11:05.327357 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8889 23:11:05.327963 ==
8890 23:11:05.328331
8891 23:11:05.328672
8892 23:11:05.328995 TX Vref Scan disable
8893 23:11:05.331150 == TX Byte 0 ==
8894 23:11:05.334264 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8895 23:11:05.341173 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
8896 23:11:05.341725 == TX Byte 1 ==
8897 23:11:05.344425 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8898 23:11:05.350602 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8899 23:11:05.351163 ==
8900 23:11:05.354010 Dram Type= 6, Freq= 0, CH_1, rank 1
8901 23:11:05.357066 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8902 23:11:05.357531 ==
8903 23:11:05.371590
8904 23:11:05.374868 TX Vref early break, caculate TX vref
8905 23:11:05.378126 TX Vref=16, minBit 9, minWin=21, winSum=376
8906 23:11:05.381202 TX Vref=18, minBit 9, minWin=22, winSum=388
8907 23:11:05.384456 TX Vref=20, minBit 9, minWin=22, winSum=391
8908 23:11:05.388090 TX Vref=22, minBit 9, minWin=23, winSum=401
8909 23:11:05.391681 TX Vref=24, minBit 9, minWin=23, winSum=406
8910 23:11:05.397644 TX Vref=26, minBit 9, minWin=25, winSum=419
8911 23:11:05.400987 TX Vref=28, minBit 9, minWin=25, winSum=421
8912 23:11:05.404074 TX Vref=30, minBit 8, minWin=25, winSum=416
8913 23:11:05.408061 TX Vref=32, minBit 9, minWin=23, winSum=408
8914 23:11:05.410515 TX Vref=34, minBit 0, minWin=24, winSum=401
8915 23:11:05.413822 TX Vref=36, minBit 9, minWin=23, winSum=397
8916 23:11:05.420655 [TxChooseVref] Worse bit 9, Min win 25, Win sum 421, Final Vref 28
8917 23:11:05.421074
8918 23:11:05.424515 Final TX Range 0 Vref 28
8919 23:11:05.425035
8920 23:11:05.425367 ==
8921 23:11:05.427209 Dram Type= 6, Freq= 0, CH_1, rank 1
8922 23:11:05.430307 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8923 23:11:05.430734 ==
8924 23:11:05.433898
8925 23:11:05.434314
8926 23:11:05.434640 TX Vref Scan disable
8927 23:11:05.440161 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8928 23:11:05.440582 == TX Byte 0 ==
8929 23:11:05.443563 u2DelayCellOfst[0]=14 cells (4 PI)
8930 23:11:05.447347 u2DelayCellOfst[1]=7 cells (2 PI)
8931 23:11:05.450308 u2DelayCellOfst[2]=0 cells (0 PI)
8932 23:11:05.454065 u2DelayCellOfst[3]=3 cells (1 PI)
8933 23:11:05.456699 u2DelayCellOfst[4]=7 cells (2 PI)
8934 23:11:05.460293 u2DelayCellOfst[5]=10 cells (3 PI)
8935 23:11:05.463294 u2DelayCellOfst[6]=10 cells (3 PI)
8936 23:11:05.467607 u2DelayCellOfst[7]=3 cells (1 PI)
8937 23:11:05.470202 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8938 23:11:05.473968 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8939 23:11:05.476564 == TX Byte 1 ==
8940 23:11:05.480738 u2DelayCellOfst[8]=0 cells (0 PI)
8941 23:11:05.482790 u2DelayCellOfst[9]=3 cells (1 PI)
8942 23:11:05.486669 u2DelayCellOfst[10]=10 cells (3 PI)
8943 23:11:05.489644 u2DelayCellOfst[11]=7 cells (2 PI)
8944 23:11:05.493581 u2DelayCellOfst[12]=14 cells (4 PI)
8945 23:11:05.496170 u2DelayCellOfst[13]=14 cells (4 PI)
8946 23:11:05.499969 u2DelayCellOfst[14]=17 cells (5 PI)
8947 23:11:05.503151 u2DelayCellOfst[15]=17 cells (5 PI)
8948 23:11:05.506293 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8949 23:11:05.510027 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8950 23:11:05.512989 DramC Write-DBI on
8951 23:11:05.513408 ==
8952 23:11:05.516377 Dram Type= 6, Freq= 0, CH_1, rank 1
8953 23:11:05.519298 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8954 23:11:05.519774 ==
8955 23:11:05.520109
8956 23:11:05.520417
8957 23:11:05.523210 TX Vref Scan disable
8958 23:11:05.523799 == TX Byte 0 ==
8959 23:11:05.529564 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8960 23:11:05.530081 == TX Byte 1 ==
8961 23:11:05.532491 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8962 23:11:05.536539 DramC Write-DBI off
8963 23:11:05.537052
8964 23:11:05.537388 [DATLAT]
8965 23:11:05.539341 Freq=1600, CH1 RK1
8966 23:11:05.539894
8967 23:11:05.540235 DATLAT Default: 0xf
8968 23:11:05.542782 0, 0xFFFF, sum = 0
8969 23:11:05.546128 1, 0xFFFF, sum = 0
8970 23:11:05.546641 2, 0xFFFF, sum = 0
8971 23:11:05.549163 3, 0xFFFF, sum = 0
8972 23:11:05.549688 4, 0xFFFF, sum = 0
8973 23:11:05.552219 5, 0xFFFF, sum = 0
8974 23:11:05.552659 6, 0xFFFF, sum = 0
8975 23:11:05.555519 7, 0xFFFF, sum = 0
8976 23:11:05.555957 8, 0xFFFF, sum = 0
8977 23:11:05.559048 9, 0xFFFF, sum = 0
8978 23:11:05.559803 10, 0xFFFF, sum = 0
8979 23:11:05.561997 11, 0xFFFF, sum = 0
8980 23:11:05.562434 12, 0xFFFF, sum = 0
8981 23:11:05.565476 13, 0xFFFF, sum = 0
8982 23:11:05.566061 14, 0x0, sum = 1
8983 23:11:05.568954 15, 0x0, sum = 2
8984 23:11:05.569532 16, 0x0, sum = 3
8985 23:11:05.572453 17, 0x0, sum = 4
8986 23:11:05.572935 best_step = 15
8987 23:11:05.573419
8988 23:11:05.573868 ==
8989 23:11:05.576005 Dram Type= 6, Freq= 0, CH_1, rank 1
8990 23:11:05.581972 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8991 23:11:05.582501 ==
8992 23:11:05.582950 RX Vref Scan: 0
8993 23:11:05.583393
8994 23:11:05.585518 RX Vref 0 -> 0, step: 1
8995 23:11:05.586075
8996 23:11:05.588464 RX Delay 11 -> 252, step: 4
8997 23:11:05.591521 iDelay=195, Bit 0, Center 134 (83 ~ 186) 104
8998 23:11:05.596064 iDelay=195, Bit 1, Center 130 (79 ~ 182) 104
8999 23:11:05.598989 iDelay=195, Bit 2, Center 120 (67 ~ 174) 108
9000 23:11:05.604982 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
9001 23:11:05.608526 iDelay=195, Bit 4, Center 130 (75 ~ 186) 112
9002 23:11:05.611341 iDelay=195, Bit 5, Center 142 (91 ~ 194) 104
9003 23:11:05.615722 iDelay=195, Bit 6, Center 140 (87 ~ 194) 108
9004 23:11:05.622251 iDelay=195, Bit 7, Center 130 (79 ~ 182) 104
9005 23:11:05.624899 iDelay=195, Bit 8, Center 114 (59 ~ 170) 112
9006 23:11:05.628227 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
9007 23:11:05.631543 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
9008 23:11:05.634270 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
9009 23:11:05.641341 iDelay=195, Bit 12, Center 136 (83 ~ 190) 108
9010 23:11:05.644397 iDelay=195, Bit 13, Center 134 (83 ~ 186) 104
9011 23:11:05.648346 iDelay=195, Bit 14, Center 132 (79 ~ 186) 108
9012 23:11:05.651746 iDelay=195, Bit 15, Center 136 (83 ~ 190) 108
9013 23:11:05.652312 ==
9014 23:11:05.654070 Dram Type= 6, Freq= 0, CH_1, rank 1
9015 23:11:05.660765 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9016 23:11:05.661265 ==
9017 23:11:05.661641 DQS Delay:
9018 23:11:05.664553 DQS0 = 0, DQS1 = 0
9019 23:11:05.665097 DQM Delay:
9020 23:11:05.667443 DQM0 = 131, DQM1 = 127
9021 23:11:05.667900 DQ Delay:
9022 23:11:05.670694 DQ0 =134, DQ1 =130, DQ2 =120, DQ3 =128
9023 23:11:05.674019 DQ4 =130, DQ5 =142, DQ6 =140, DQ7 =130
9024 23:11:05.677234 DQ8 =114, DQ9 =118, DQ10 =128, DQ11 =120
9025 23:11:05.680380 DQ12 =136, DQ13 =134, DQ14 =132, DQ15 =136
9026 23:11:05.681070
9027 23:11:05.681482
9028 23:11:05.681820
9029 23:11:05.683744 [DramC_TX_OE_Calibration] TA2
9030 23:11:05.687258 Original DQ_B0 (3 6) =30, OEN = 27
9031 23:11:05.690466 Original DQ_B1 (3 6) =30, OEN = 27
9032 23:11:05.693795 24, 0x0, End_B0=24 End_B1=24
9033 23:11:05.697869 25, 0x0, End_B0=25 End_B1=25
9034 23:11:05.698420 26, 0x0, End_B0=26 End_B1=26
9035 23:11:05.700413 27, 0x0, End_B0=27 End_B1=27
9036 23:11:05.704145 28, 0x0, End_B0=28 End_B1=28
9037 23:11:05.707702 29, 0x0, End_B0=29 End_B1=29
9038 23:11:05.710227 30, 0x0, End_B0=30 End_B1=30
9039 23:11:05.710690 31, 0x4141, End_B0=30 End_B1=30
9040 23:11:05.713442 Byte0 end_step=30 best_step=27
9041 23:11:05.716947 Byte1 end_step=30 best_step=27
9042 23:11:05.721041 Byte0 TX OE(2T, 0.5T) = (3, 3)
9043 23:11:05.723739 Byte1 TX OE(2T, 0.5T) = (3, 3)
9044 23:11:05.724514
9045 23:11:05.724905
9046 23:11:05.731151 [DQSOSCAuto] RK1, (LSB)MR18= 0x111e, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 401 ps
9047 23:11:05.734053 CH1 RK1: MR19=303, MR18=111E
9048 23:11:05.739934 CH1_RK1: MR19=0x303, MR18=0x111E, DQSOSC=394, MR23=63, INC=23, DEC=15
9049 23:11:05.743746 [RxdqsGatingPostProcess] freq 1600
9050 23:11:05.750175 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9051 23:11:05.753272 best DQS0 dly(2T, 0.5T) = (1, 1)
9052 23:11:05.753725 best DQS1 dly(2T, 0.5T) = (1, 1)
9053 23:11:05.756220 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9054 23:11:05.759938 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9055 23:11:05.763263 best DQS0 dly(2T, 0.5T) = (1, 1)
9056 23:11:05.767161 best DQS1 dly(2T, 0.5T) = (1, 1)
9057 23:11:05.769892 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9058 23:11:05.773374 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9059 23:11:05.775932 Pre-setting of DQS Precalculation
9060 23:11:05.782573 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9061 23:11:05.789458 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9062 23:11:05.795693 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9063 23:11:05.796275
9064 23:11:05.796646
9065 23:11:05.799202 [Calibration Summary] 3200 Mbps
9066 23:11:05.799695 CH 0, Rank 0
9067 23:11:05.802358 SW Impedance : PASS
9068 23:11:05.805819 DUTY Scan : NO K
9069 23:11:05.806388 ZQ Calibration : PASS
9070 23:11:05.808995 Jitter Meter : NO K
9071 23:11:05.812851 CBT Training : PASS
9072 23:11:05.813395 Write leveling : PASS
9073 23:11:05.815497 RX DQS gating : PASS
9074 23:11:05.818987 RX DQ/DQS(RDDQC) : PASS
9075 23:11:05.819581 TX DQ/DQS : PASS
9076 23:11:05.822358 RX DATLAT : PASS
9077 23:11:05.822906 RX DQ/DQS(Engine): PASS
9078 23:11:05.825223 TX OE : PASS
9079 23:11:05.825680 All Pass.
9080 23:11:05.826035
9081 23:11:05.828833 CH 0, Rank 1
9082 23:11:05.832012 SW Impedance : PASS
9083 23:11:05.832626 DUTY Scan : NO K
9084 23:11:05.835420 ZQ Calibration : PASS
9085 23:11:05.838766 Jitter Meter : NO K
9086 23:11:05.839311 CBT Training : PASS
9087 23:11:05.841647 Write leveling : PASS
9088 23:11:05.842195 RX DQS gating : PASS
9089 23:11:05.845149 RX DQ/DQS(RDDQC) : PASS
9090 23:11:05.848271 TX DQ/DQS : PASS
9091 23:11:05.848821 RX DATLAT : PASS
9092 23:11:05.851529 RX DQ/DQS(Engine): PASS
9093 23:11:05.854907 TX OE : PASS
9094 23:11:05.855539 All Pass.
9095 23:11:05.855917
9096 23:11:05.856254 CH 1, Rank 0
9097 23:11:05.858768 SW Impedance : PASS
9098 23:11:05.861436 DUTY Scan : NO K
9099 23:11:05.861888 ZQ Calibration : PASS
9100 23:11:05.864443 Jitter Meter : NO K
9101 23:11:05.867973 CBT Training : PASS
9102 23:11:05.868518 Write leveling : PASS
9103 23:11:05.871319 RX DQS gating : PASS
9104 23:11:05.875539 RX DQ/DQS(RDDQC) : PASS
9105 23:11:05.876086 TX DQ/DQS : PASS
9106 23:11:05.878062 RX DATLAT : PASS
9107 23:11:05.881049 RX DQ/DQS(Engine): PASS
9108 23:11:05.881502 TX OE : PASS
9109 23:11:05.884817 All Pass.
9110 23:11:05.885362
9111 23:11:05.885724 CH 1, Rank 1
9112 23:11:05.887332 SW Impedance : PASS
9113 23:11:05.887845 DUTY Scan : NO K
9114 23:11:05.891063 ZQ Calibration : PASS
9115 23:11:05.894715 Jitter Meter : NO K
9116 23:11:05.895260 CBT Training : PASS
9117 23:11:05.897450 Write leveling : PASS
9118 23:11:05.900910 RX DQS gating : PASS
9119 23:11:05.901463 RX DQ/DQS(RDDQC) : PASS
9120 23:11:05.904415 TX DQ/DQS : PASS
9121 23:11:05.907569 RX DATLAT : PASS
9122 23:11:05.908041 RX DQ/DQS(Engine): PASS
9123 23:11:05.911073 TX OE : PASS
9124 23:11:05.911698 All Pass.
9125 23:11:05.912064
9126 23:11:05.914238 DramC Write-DBI on
9127 23:11:05.917474 PER_BANK_REFRESH: Hybrid Mode
9128 23:11:05.917931 TX_TRACKING: ON
9129 23:11:05.927735 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9130 23:11:05.934438 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9131 23:11:05.939978 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9132 23:11:05.943355 [FAST_K] Save calibration result to emmc
9133 23:11:05.947036 sync common calibartion params.
9134 23:11:05.950855 sync cbt_mode0:1, 1:1
9135 23:11:05.953842 dram_init: ddr_geometry: 2
9136 23:11:05.954386 dram_init: ddr_geometry: 2
9137 23:11:05.956578 dram_init: ddr_geometry: 2
9138 23:11:05.959880 0:dram_rank_size:100000000
9139 23:11:05.963123 1:dram_rank_size:100000000
9140 23:11:05.966679 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9141 23:11:05.970010 DFS_SHUFFLE_HW_MODE: ON
9142 23:11:05.973462 dramc_set_vcore_voltage set vcore to 725000
9143 23:11:05.976153 Read voltage for 1600, 0
9144 23:11:05.976608 Vio18 = 0
9145 23:11:05.979591 Vcore = 725000
9146 23:11:05.980046 Vdram = 0
9147 23:11:05.980400 Vddq = 0
9148 23:11:05.980729 Vmddr = 0
9149 23:11:05.982982 switch to 3200 Mbps bootup
9150 23:11:05.986556 [DramcRunTimeConfig]
9151 23:11:05.987095 PHYPLL
9152 23:11:05.989486 DPM_CONTROL_AFTERK: ON
9153 23:11:05.989936 PER_BANK_REFRESH: ON
9154 23:11:05.992916 REFRESH_OVERHEAD_REDUCTION: ON
9155 23:11:05.996558 CMD_PICG_NEW_MODE: OFF
9156 23:11:05.997015 XRTWTW_NEW_MODE: ON
9157 23:11:05.999965 XRTRTR_NEW_MODE: ON
9158 23:11:06.000510 TX_TRACKING: ON
9159 23:11:06.003009 RDSEL_TRACKING: OFF
9160 23:11:06.006366 DQS Precalculation for DVFS: ON
9161 23:11:06.006906 RX_TRACKING: OFF
9162 23:11:06.007282 HW_GATING DBG: ON
9163 23:11:06.009126 ZQCS_ENABLE_LP4: ON
9164 23:11:06.013379 RX_PICG_NEW_MODE: ON
9165 23:11:06.013972 TX_PICG_NEW_MODE: ON
9166 23:11:06.015717 ENABLE_RX_DCM_DPHY: ON
9167 23:11:06.019183 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9168 23:11:06.022524 DUMMY_READ_FOR_TRACKING: OFF
9169 23:11:06.023069 !!! SPM_CONTROL_AFTERK: OFF
9170 23:11:06.026055 !!! SPM could not control APHY
9171 23:11:06.028768 IMPEDANCE_TRACKING: ON
9172 23:11:06.029240 TEMP_SENSOR: ON
9173 23:11:06.032850 HW_SAVE_FOR_SR: OFF
9174 23:11:06.035665 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9175 23:11:06.038770 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9176 23:11:06.039313 Read ODT Tracking: ON
9177 23:11:06.042272 Refresh Rate DeBounce: ON
9178 23:11:06.045591 DFS_NO_QUEUE_FLUSH: ON
9179 23:11:06.049514 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9180 23:11:06.050060 ENABLE_DFS_RUNTIME_MRW: OFF
9181 23:11:06.052201 DDR_RESERVE_NEW_MODE: ON
9182 23:11:06.055594 MR_CBT_SWITCH_FREQ: ON
9183 23:11:06.056145 =========================
9184 23:11:06.076341 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9185 23:11:06.079422 dram_init: ddr_geometry: 2
9186 23:11:06.097468 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9187 23:11:06.100608 dram_init: dram init end (result: 0)
9188 23:11:06.107302 DRAM-K: Full calibration passed in 24438 msecs
9189 23:11:06.110481 MRC: failed to locate region type 0.
9190 23:11:06.111023 DRAM rank0 size:0x100000000,
9191 23:11:06.114192 DRAM rank1 size=0x100000000
9192 23:11:06.123795 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9193 23:11:06.130081 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9194 23:11:06.136772 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9195 23:11:06.146889 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9196 23:11:06.147497 DRAM rank0 size:0x100000000,
9197 23:11:06.149989 DRAM rank1 size=0x100000000
9198 23:11:06.150534 CBMEM:
9199 23:11:06.153018 IMD: root @ 0xfffff000 254 entries.
9200 23:11:06.156788 IMD: root @ 0xffffec00 62 entries.
9201 23:11:06.159942 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9202 23:11:06.166095 WARNING: RO_VPD is uninitialized or empty.
9203 23:11:06.170000 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9204 23:11:06.177529 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9205 23:11:06.189990 read SPI 0x42894 0xe01e: 6226 us, 9215 KB/s, 73.720 Mbps
9206 23:11:06.201745 BS: romstage times (exec / console): total (unknown) / 23967 ms
9207 23:11:06.202296
9208 23:11:06.202695
9209 23:11:06.211333 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9210 23:11:06.214629 ARM64: Exception handlers installed.
9211 23:11:06.218844 ARM64: Testing exception
9212 23:11:06.221531 ARM64: Done test exception
9213 23:11:06.221981 Enumerating buses...
9214 23:11:06.224663 Show all devs... Before device enumeration.
9215 23:11:06.228500 Root Device: enabled 1
9216 23:11:06.230927 CPU_CLUSTER: 0: enabled 1
9217 23:11:06.231432 CPU: 00: enabled 1
9218 23:11:06.234615 Compare with tree...
9219 23:11:06.235168 Root Device: enabled 1
9220 23:11:06.237851 CPU_CLUSTER: 0: enabled 1
9221 23:11:06.240851 CPU: 00: enabled 1
9222 23:11:06.241303 Root Device scanning...
9223 23:11:06.245282 scan_static_bus for Root Device
9224 23:11:06.248648 CPU_CLUSTER: 0 enabled
9225 23:11:06.250785 scan_static_bus for Root Device done
9226 23:11:06.255846 scan_bus: bus Root Device finished in 8 msecs
9227 23:11:06.256404 done
9228 23:11:06.260801 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9229 23:11:06.263809 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9230 23:11:06.270501 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9231 23:11:06.277747 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9232 23:11:06.278297 Allocating resources...
9233 23:11:06.280100 Reading resources...
9234 23:11:06.284053 Root Device read_resources bus 0 link: 0
9235 23:11:06.287053 DRAM rank0 size:0x100000000,
9236 23:11:06.287662 DRAM rank1 size=0x100000000
9237 23:11:06.293488 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9238 23:11:06.294024 CPU: 00 missing read_resources
9239 23:11:06.300464 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9240 23:11:06.303992 Root Device read_resources bus 0 link: 0 done
9241 23:11:06.307776 Done reading resources.
9242 23:11:06.309917 Show resources in subtree (Root Device)...After reading.
9243 23:11:06.314228 Root Device child on link 0 CPU_CLUSTER: 0
9244 23:11:06.317680 CPU_CLUSTER: 0 child on link 0 CPU: 00
9245 23:11:06.326748 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9246 23:11:06.327476 CPU: 00
9247 23:11:06.333379 Root Device assign_resources, bus 0 link: 0
9248 23:11:06.336446 CPU_CLUSTER: 0 missing set_resources
9249 23:11:06.339745 Root Device assign_resources, bus 0 link: 0 done
9250 23:11:06.342600 Done setting resources.
9251 23:11:06.346561 Show resources in subtree (Root Device)...After assigning values.
9252 23:11:06.352828 Root Device child on link 0 CPU_CLUSTER: 0
9253 23:11:06.357038 CPU_CLUSTER: 0 child on link 0 CPU: 00
9254 23:11:06.362476 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9255 23:11:06.365930 CPU: 00
9256 23:11:06.366470 Done allocating resources.
9257 23:11:06.372992 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9258 23:11:06.373492 Enabling resources...
9259 23:11:06.376046 done.
9260 23:11:06.378731 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9261 23:11:06.382059 Initializing devices...
9262 23:11:06.382465 Root Device init
9263 23:11:06.385215 init hardware done!
9264 23:11:06.388975 0x00000018: ctrlr->caps
9265 23:11:06.389494 52.000 MHz: ctrlr->f_max
9266 23:11:06.392090 0.400 MHz: ctrlr->f_min
9267 23:11:06.396025 0x40ff8080: ctrlr->voltages
9268 23:11:06.396545 sclk: 390625
9269 23:11:06.396875 Bus Width = 1
9270 23:11:06.399132 sclk: 390625
9271 23:11:06.399729 Bus Width = 1
9272 23:11:06.402916 Early init status = 3
9273 23:11:06.405934 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9274 23:11:06.408780 in-header: 03 fc 00 00 01 00 00 00
9275 23:11:06.412127 in-data: 00
9276 23:11:06.415880 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9277 23:11:06.420279 in-header: 03 fd 00 00 00 00 00 00
9278 23:11:06.424489 in-data:
9279 23:11:06.426940 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9280 23:11:06.430971 in-header: 03 fc 00 00 01 00 00 00
9281 23:11:06.433967 in-data: 00
9282 23:11:06.436531 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9283 23:11:06.441385 in-header: 03 fd 00 00 00 00 00 00
9284 23:11:06.444729 in-data:
9285 23:11:06.448207 [SSUSB] Setting up USB HOST controller...
9286 23:11:06.451477 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9287 23:11:06.455006 [SSUSB] phy power-on done.
9288 23:11:06.457709 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9289 23:11:06.464226 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9290 23:11:06.467832 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9291 23:11:06.474358 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9292 23:11:06.481207 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9293 23:11:06.487555 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9294 23:11:06.493976 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9295 23:11:06.500830 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9296 23:11:06.504704 SPM: binary array size = 0x9dc
9297 23:11:06.507472 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9298 23:11:06.514262 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9299 23:11:06.520884 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9300 23:11:06.527791 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9301 23:11:06.530455 configure_display: Starting display init
9302 23:11:06.565260 anx7625_power_on_init: Init interface.
9303 23:11:06.568785 anx7625_disable_pd_protocol: Disabled PD feature.
9304 23:11:06.571617 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9305 23:11:06.599317 anx7625_start_dp_work: Secure OCM version=00
9306 23:11:06.602545 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9307 23:11:06.617731 sp_tx_get_edid_block: EDID Block = 1
9308 23:11:06.720153 Extracted contents:
9309 23:11:06.723189 header: 00 ff ff ff ff ff ff 00
9310 23:11:06.726752 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9311 23:11:06.730030 version: 01 04
9312 23:11:06.733491 basic params: 95 1f 11 78 0a
9313 23:11:06.736539 chroma info: 76 90 94 55 54 90 27 21 50 54
9314 23:11:06.740285 established: 00 00 00
9315 23:11:06.747478 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9316 23:11:06.753557 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9317 23:11:06.756042 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9318 23:11:06.762476 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9319 23:11:06.769610 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9320 23:11:06.773136 extensions: 00
9321 23:11:06.773679 checksum: fb
9322 23:11:06.774257
9323 23:11:06.779733 Manufacturer: IVO Model 57d Serial Number 0
9324 23:11:06.780280 Made week 0 of 2020
9325 23:11:06.782738 EDID version: 1.4
9326 23:11:06.783285 Digital display
9327 23:11:06.785767 6 bits per primary color channel
9328 23:11:06.789013 DisplayPort interface
9329 23:11:06.789467 Maximum image size: 31 cm x 17 cm
9330 23:11:06.792190 Gamma: 220%
9331 23:11:06.792730 Check DPMS levels
9332 23:11:06.799258 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9333 23:11:06.802561 First detailed timing is preferred timing
9334 23:11:06.806229 Established timings supported:
9335 23:11:06.806772 Standard timings supported:
9336 23:11:06.808784 Detailed timings
9337 23:11:06.812549 Hex of detail: 383680a07038204018303c0035ae10000019
9338 23:11:06.818847 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9339 23:11:06.821970 0780 0798 07c8 0820 hborder 0
9340 23:11:06.825503 0438 043b 0447 0458 vborder 0
9341 23:11:06.828466 -hsync -vsync
9342 23:11:06.829012 Did detailed timing
9343 23:11:06.835645 Hex of detail: 000000000000000000000000000000000000
9344 23:11:06.838245 Manufacturer-specified data, tag 0
9345 23:11:06.841827 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9346 23:11:06.845129 ASCII string: InfoVision
9347 23:11:06.848236 Hex of detail: 000000fe00523134304e574635205248200a
9348 23:11:06.852009 ASCII string: R140NWF5 RH
9349 23:11:06.852587 Checksum
9350 23:11:06.854790 Checksum: 0xfb (valid)
9351 23:11:06.858144 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9352 23:11:06.861607 DSI data_rate: 832800000 bps
9353 23:11:06.868891 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9354 23:11:06.872282 anx7625_parse_edid: pixelclock(138800).
9355 23:11:06.874972 hactive(1920), hsync(48), hfp(24), hbp(88)
9356 23:11:06.878628 vactive(1080), vsync(12), vfp(3), vbp(17)
9357 23:11:06.881963 anx7625_dsi_config: config dsi.
9358 23:11:06.888142 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9359 23:11:06.901681 anx7625_dsi_config: success to config DSI
9360 23:11:06.905468 anx7625_dp_start: MIPI phy setup OK.
9361 23:11:06.908559 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9362 23:11:06.911983 mtk_ddp_mode_set invalid vrefresh 60
9363 23:11:06.915305 main_disp_path_setup
9364 23:11:06.915837 ovl_layer_smi_id_en
9365 23:11:06.918569 ovl_layer_smi_id_en
9366 23:11:06.919074 ccorr_config
9367 23:11:06.919437 aal_config
9368 23:11:06.922542 gamma_config
9369 23:11:06.923069 postmask_config
9370 23:11:06.925326 dither_config
9371 23:11:06.928316 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9372 23:11:06.936089 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9373 23:11:06.938142 Root Device init finished in 551 msecs
9374 23:11:06.941830 CPU_CLUSTER: 0 init
9375 23:11:06.949153 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9376 23:11:06.954718 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9377 23:11:06.955225 APU_MBOX 0x190000b0 = 0x10001
9378 23:11:06.958355 APU_MBOX 0x190001b0 = 0x10001
9379 23:11:06.961103 APU_MBOX 0x190005b0 = 0x10001
9380 23:11:06.964728 APU_MBOX 0x190006b0 = 0x10001
9381 23:11:06.971216 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9382 23:11:06.981115 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9383 23:11:06.993618 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9384 23:11:07.000642 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9385 23:11:07.011580 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9386 23:11:07.021495 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9387 23:11:07.025065 CPU_CLUSTER: 0 init finished in 81 msecs
9388 23:11:07.027753 Devices initialized
9389 23:11:07.032021 Show all devs... After init.
9390 23:11:07.032578 Root Device: enabled 1
9391 23:11:07.034600 CPU_CLUSTER: 0: enabled 1
9392 23:11:07.037796 CPU: 00: enabled 1
9393 23:11:07.040879 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9394 23:11:07.044620 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9395 23:11:07.047146 ELOG: NV offset 0x57f000 size 0x1000
9396 23:11:07.054167 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9397 23:11:07.061446 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9398 23:11:07.063916 ELOG: Event(17) added with size 13 at 2023-12-27 23:11:11 UTC
9399 23:11:07.071128 out: cmd=0x121: 03 db 21 01 00 00 00 00
9400 23:11:07.074130 in-header: 03 22 00 00 2c 00 00 00
9401 23:11:07.083675 in-data: 3d 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9402 23:11:07.090336 ELOG: Event(A1) added with size 10 at 2023-12-27 23:11:11 UTC
9403 23:11:07.096861 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9404 23:11:07.103741 ELOG: Event(A0) added with size 9 at 2023-12-27 23:11:11 UTC
9405 23:11:07.107081 elog_add_boot_reason: Logged dev mode boot
9406 23:11:07.114713 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9407 23:11:07.115271 Finalize devices...
9408 23:11:07.116370 Devices finalized
9409 23:11:07.120346 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9410 23:11:07.123843 Writing coreboot table at 0xffe64000
9411 23:11:07.127523 0. 000000000010a000-0000000000113fff: RAMSTAGE
9412 23:11:07.133865 1. 0000000040000000-00000000400fffff: RAM
9413 23:11:07.136187 2. 0000000040100000-000000004032afff: RAMSTAGE
9414 23:11:07.140084 3. 000000004032b000-00000000545fffff: RAM
9415 23:11:07.143402 4. 0000000054600000-000000005465ffff: BL31
9416 23:11:07.146432 5. 0000000054660000-00000000ffe63fff: RAM
9417 23:11:07.153192 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9418 23:11:07.156473 7. 0000000100000000-000000023fffffff: RAM
9419 23:11:07.159720 Passing 5 GPIOs to payload:
9420 23:11:07.162758 NAME | PORT | POLARITY | VALUE
9421 23:11:07.169475 EC in RW | 0x000000aa | low | undefined
9422 23:11:07.172665 EC interrupt | 0x00000005 | low | undefined
9423 23:11:07.177069 TPM interrupt | 0x000000ab | high | undefined
9424 23:11:07.182981 SD card detect | 0x00000011 | high | undefined
9425 23:11:07.186585 speaker enable | 0x00000093 | high | undefined
9426 23:11:07.189725 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9427 23:11:07.193365 in-header: 03 f9 00 00 02 00 00 00
9428 23:11:07.196164 in-data: 02 00
9429 23:11:07.200551 ADC[4]: Raw value=902216 ID=7
9430 23:11:07.202802 ADC[3]: Raw value=213546 ID=1
9431 23:11:07.203263 RAM Code: 0x71
9432 23:11:07.206479 ADC[6]: Raw value=74630 ID=0
9433 23:11:07.209951 ADC[5]: Raw value=213546 ID=1
9434 23:11:07.210437 SKU Code: 0x1
9435 23:11:07.215940 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum f720
9436 23:11:07.216492 coreboot table: 964 bytes.
9437 23:11:07.219164 IMD ROOT 0. 0xfffff000 0x00001000
9438 23:11:07.223546 IMD SMALL 1. 0xffffe000 0x00001000
9439 23:11:07.226314 RO MCACHE 2. 0xffffc000 0x00001104
9440 23:11:07.229481 CONSOLE 3. 0xfff7c000 0x00080000
9441 23:11:07.232382 FMAP 4. 0xfff7b000 0x00000452
9442 23:11:07.235669 TIME STAMP 5. 0xfff7a000 0x00000910
9443 23:11:07.239554 VBOOT WORK 6. 0xfff66000 0x00014000
9444 23:11:07.242558 RAMOOPS 7. 0xffe66000 0x00100000
9445 23:11:07.245222 COREBOOT 8. 0xffe64000 0x00002000
9446 23:11:07.248925 IMD small region:
9447 23:11:07.252702 IMD ROOT 0. 0xffffec00 0x00000400
9448 23:11:07.255608 VPD 1. 0xffffeb80 0x0000006c
9449 23:11:07.259111 MMC STATUS 2. 0xffffeb60 0x00000004
9450 23:11:07.265250 BS: BS_WRITE_TABLES run times (exec / console): 2 / 137 ms
9451 23:11:07.265791 Probing TPM: done!
9452 23:11:07.272077 Connected to device vid:did:rid of 1ae0:0028:00
9453 23:11:07.278469 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
9454 23:11:07.281519 Initialized TPM device CR50 revision 0
9455 23:11:07.285349 Checking cr50 for pending updates
9456 23:11:07.291542 Reading cr50 TPM mode
9457 23:11:07.300099 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9458 23:11:07.306609 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9459 23:11:07.346823 read SPI 0x3990ec 0x4f1b0: 34850 us, 9297 KB/s, 74.376 Mbps
9460 23:11:07.349997 Checking segment from ROM address 0x40100000
9461 23:11:07.353576 Checking segment from ROM address 0x4010001c
9462 23:11:07.360454 Loading segment from ROM address 0x40100000
9463 23:11:07.361018 code (compression=0)
9464 23:11:07.370086 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9465 23:11:07.376901 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9466 23:11:07.377466 it's not compressed!
9467 23:11:07.383288 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9468 23:11:07.389548 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9469 23:11:07.407294 Loading segment from ROM address 0x4010001c
9470 23:11:07.407909 Entry Point 0x80000000
9471 23:11:07.410668 Loaded segments
9472 23:11:07.413448 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9473 23:11:07.420782 Jumping to boot code at 0x80000000(0xffe64000)
9474 23:11:07.427114 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9475 23:11:07.433809 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9476 23:11:07.441369 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9477 23:11:07.444826 Checking segment from ROM address 0x40100000
9478 23:11:07.448425 Checking segment from ROM address 0x4010001c
9479 23:11:07.454504 Loading segment from ROM address 0x40100000
9480 23:11:07.455047 code (compression=1)
9481 23:11:07.461352 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9482 23:11:07.470918 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9483 23:11:07.471518 using LZMA
9484 23:11:07.480343 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9485 23:11:07.486478 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9486 23:11:07.489859 Loading segment from ROM address 0x4010001c
9487 23:11:07.493125 Entry Point 0x54601000
9488 23:11:07.493694 Loaded segments
9489 23:11:07.496029 NOTICE: MT8192 bl31_setup
9490 23:11:07.504219 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9491 23:11:07.506933 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9492 23:11:07.509864 WARNING: region 0:
9493 23:11:07.513590 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9494 23:11:07.514056 WARNING: region 1:
9495 23:11:07.520176 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9496 23:11:07.523425 WARNING: region 2:
9497 23:11:07.527465 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9498 23:11:07.530650 WARNING: region 3:
9499 23:11:07.533262 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9500 23:11:07.536665 WARNING: region 4:
9501 23:11:07.543264 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9502 23:11:07.543901 WARNING: region 5:
9503 23:11:07.546448 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9504 23:11:07.549756 WARNING: region 6:
9505 23:11:07.553121 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9506 23:11:07.556290 WARNING: region 7:
9507 23:11:07.559669 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9508 23:11:07.566417 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9509 23:11:07.569881 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9510 23:11:07.572635 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9511 23:11:07.579823 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9512 23:11:07.582877 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9513 23:11:07.589909 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9514 23:11:07.593282 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9515 23:11:07.596161 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9516 23:11:07.602848 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9517 23:11:07.606114 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9518 23:11:07.609327 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9519 23:11:07.616164 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9520 23:11:07.619492 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9521 23:11:07.625871 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9522 23:11:07.629175 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9523 23:11:07.632555 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9524 23:11:07.639117 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9525 23:11:07.642064 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9526 23:11:07.649131 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9527 23:11:07.652322 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9528 23:11:07.655948 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9529 23:11:07.662471 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9530 23:11:07.665434 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9531 23:11:07.669116 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9532 23:11:07.675802 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9533 23:11:07.679542 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9534 23:11:07.686516 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9535 23:11:07.689105 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9536 23:11:07.696036 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9537 23:11:07.699509 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9538 23:11:07.702274 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9539 23:11:07.709163 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9540 23:11:07.712928 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9541 23:11:07.715584 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9542 23:11:07.718959 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9543 23:11:07.726549 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9544 23:11:07.729107 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9545 23:11:07.732388 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9546 23:11:07.736074 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9547 23:11:07.742430 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9548 23:11:07.745425 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9549 23:11:07.748792 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9550 23:11:07.752450 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9551 23:11:07.759219 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9552 23:11:07.762338 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9553 23:11:07.765532 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9554 23:11:07.769033 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9555 23:11:07.775498 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9556 23:11:07.779086 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9557 23:11:07.785900 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9558 23:11:07.788993 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9559 23:11:07.792281 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9560 23:11:07.799453 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9561 23:11:07.802655 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9562 23:11:07.808285 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9563 23:11:07.811733 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9564 23:11:07.818352 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9565 23:11:07.821670 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9566 23:11:07.825386 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9567 23:11:07.831739 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9568 23:11:07.835397 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9569 23:11:07.841693 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9570 23:11:07.844812 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9571 23:11:07.851316 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9572 23:11:07.854704 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9573 23:11:07.861638 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9574 23:11:07.865179 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9575 23:11:07.871223 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9576 23:11:07.874670 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9577 23:11:07.877882 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9578 23:11:07.884697 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9579 23:11:07.887692 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9580 23:11:07.894743 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9581 23:11:07.898361 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9582 23:11:07.904891 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9583 23:11:07.908232 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9584 23:11:07.911009 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9585 23:11:07.917883 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9586 23:11:07.920947 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9587 23:11:07.928089 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9588 23:11:07.930815 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9589 23:11:07.937759 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9590 23:11:07.941323 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9591 23:11:07.947951 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9592 23:11:07.950759 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9593 23:11:07.954298 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9594 23:11:07.960752 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9595 23:11:07.964102 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9596 23:11:07.970734 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9597 23:11:07.974235 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9598 23:11:07.981049 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9599 23:11:07.984202 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9600 23:11:07.987842 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9601 23:11:07.994435 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9602 23:11:07.997164 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9603 23:11:08.004074 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9604 23:11:08.007436 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9605 23:11:08.010839 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9606 23:11:08.017471 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9607 23:11:08.020646 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9608 23:11:08.023947 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9609 23:11:08.027543 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9610 23:11:08.034385 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9611 23:11:08.037479 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9612 23:11:08.043694 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9613 23:11:08.046911 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9614 23:11:08.050664 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9615 23:11:08.057278 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9616 23:11:08.061066 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9617 23:11:08.067129 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9618 23:11:08.070408 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9619 23:11:08.074436 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9620 23:11:08.080611 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9621 23:11:08.083807 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9622 23:11:08.090728 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9623 23:11:08.094597 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9624 23:11:08.097316 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9625 23:11:08.103932 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9626 23:11:08.107738 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9627 23:11:08.110444 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9628 23:11:08.113398 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9629 23:11:08.120768 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9630 23:11:08.124050 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9631 23:11:08.127157 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9632 23:11:08.134267 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9633 23:11:08.137219 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9634 23:11:08.140233 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9635 23:11:08.146788 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9636 23:11:08.150069 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9637 23:11:08.157259 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9638 23:11:08.160486 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9639 23:11:08.163603 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9640 23:11:08.170474 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9641 23:11:08.173822 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9642 23:11:08.179859 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9643 23:11:08.183641 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9644 23:11:08.187512 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9645 23:11:08.193113 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9646 23:11:08.196944 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9647 23:11:08.200019 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9648 23:11:08.206712 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9649 23:11:08.210092 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9650 23:11:08.216434 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9651 23:11:08.219819 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9652 23:11:08.222911 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9653 23:11:08.230262 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9654 23:11:08.234369 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9655 23:11:08.239929 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9656 23:11:08.243875 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9657 23:11:08.246397 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9658 23:11:08.253156 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9659 23:11:08.256428 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9660 23:11:08.263182 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9661 23:11:08.266632 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9662 23:11:08.269569 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9663 23:11:08.276520 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9664 23:11:08.279394 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9665 23:11:08.286046 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9666 23:11:08.289747 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9667 23:11:08.292600 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9668 23:11:08.299462 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9669 23:11:08.303120 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9670 23:11:08.309656 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9671 23:11:08.312843 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9672 23:11:08.315525 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9673 23:11:08.322632 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9674 23:11:08.325560 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9675 23:11:08.332326 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9676 23:11:08.335749 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9677 23:11:08.339196 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9678 23:11:08.345530 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9679 23:11:08.349191 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9680 23:11:08.355524 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9681 23:11:08.359321 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9682 23:11:08.362177 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9683 23:11:08.368718 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9684 23:11:08.372184 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9685 23:11:08.378571 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9686 23:11:08.381998 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9687 23:11:08.385513 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9688 23:11:08.391629 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9689 23:11:08.395036 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9690 23:11:08.401729 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9691 23:11:08.404717 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9692 23:11:08.407791 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9693 23:11:08.414610 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9694 23:11:08.418317 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9695 23:11:08.424651 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9696 23:11:08.427784 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9697 23:11:08.434199 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9698 23:11:08.438537 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9699 23:11:08.440659 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9700 23:11:08.447333 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9701 23:11:08.450676 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9702 23:11:08.457262 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9703 23:11:08.460417 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9704 23:11:08.463846 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9705 23:11:08.470965 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9706 23:11:08.473982 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9707 23:11:08.480261 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9708 23:11:08.483819 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9709 23:11:08.490791 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9710 23:11:08.493540 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9711 23:11:08.497102 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9712 23:11:08.503764 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9713 23:11:08.506723 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9714 23:11:08.513485 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9715 23:11:08.516776 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9716 23:11:08.523477 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9717 23:11:08.526751 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9718 23:11:08.530493 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9719 23:11:08.537040 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9720 23:11:08.539772 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9721 23:11:08.546430 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9722 23:11:08.551445 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9723 23:11:08.556320 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9724 23:11:08.559567 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9725 23:11:08.562819 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9726 23:11:08.569669 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9727 23:11:08.572989 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9728 23:11:08.579314 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9729 23:11:08.582685 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9730 23:11:08.589579 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9731 23:11:08.592735 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9732 23:11:08.596233 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9733 23:11:08.602731 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9734 23:11:08.605704 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9735 23:11:08.612202 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9736 23:11:08.615125 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9737 23:11:08.618364 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9738 23:11:08.625914 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9739 23:11:08.628761 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9740 23:11:08.631768 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9741 23:11:08.634825 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9742 23:11:08.641678 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9743 23:11:08.644805 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9744 23:11:08.651788 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9745 23:11:08.655596 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9746 23:11:08.658135 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9747 23:11:08.664781 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9748 23:11:08.667896 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9749 23:11:08.671573 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9750 23:11:08.678085 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9751 23:11:08.680988 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9752 23:11:08.684454 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9753 23:11:08.690780 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9754 23:11:08.694473 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9755 23:11:08.701875 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9756 23:11:08.704008 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9757 23:11:08.707604 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9758 23:11:08.714351 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9759 23:11:08.717718 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9760 23:11:08.724188 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9761 23:11:08.727602 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9762 23:11:08.731537 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9763 23:11:08.737185 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9764 23:11:08.740622 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9765 23:11:08.743798 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9766 23:11:08.750140 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9767 23:11:08.753845 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9768 23:11:08.761239 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9769 23:11:08.763678 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9770 23:11:08.766569 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9771 23:11:08.773317 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9772 23:11:08.777385 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9773 23:11:08.780058 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9774 23:11:08.786993 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9775 23:11:08.789890 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9776 23:11:08.796503 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9777 23:11:08.799639 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9778 23:11:08.802806 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9779 23:11:08.806564 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9780 23:11:08.809779 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9781 23:11:08.816220 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9782 23:11:08.819991 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9783 23:11:08.822675 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9784 23:11:08.826622 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9785 23:11:08.832782 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9786 23:11:08.836115 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9787 23:11:08.839521 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9788 23:11:08.845703 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9789 23:11:08.849072 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9790 23:11:08.852090 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9791 23:11:08.858962 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9792 23:11:08.862248 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9793 23:11:08.868556 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9794 23:11:08.872572 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9795 23:11:08.878944 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9796 23:11:08.881666 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9797 23:11:08.886000 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9798 23:11:08.891965 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9799 23:11:08.895320 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9800 23:11:08.901565 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9801 23:11:08.905224 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9802 23:11:08.907998 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9803 23:11:08.915096 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9804 23:11:08.918601 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9805 23:11:08.925001 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9806 23:11:08.927992 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9807 23:11:08.931308 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9808 23:11:08.938563 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9809 23:11:08.941478 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9810 23:11:08.947719 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9811 23:11:08.950936 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9812 23:11:08.957704 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9813 23:11:08.960822 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9814 23:11:08.964528 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9815 23:11:08.970857 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9816 23:11:08.974619 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9817 23:11:08.980666 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9818 23:11:08.984121 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9819 23:11:08.990298 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9820 23:11:08.993860 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9821 23:11:08.997874 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9822 23:11:09.004025 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9823 23:11:09.007249 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9824 23:11:09.013462 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9825 23:11:09.017169 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9826 23:11:09.023319 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9827 23:11:09.026860 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9828 23:11:09.029729 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9829 23:11:09.036222 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9830 23:11:09.040029 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9831 23:11:09.046434 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9832 23:11:09.049723 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9833 23:11:09.053012 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9834 23:11:09.060050 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9835 23:11:09.062978 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9836 23:11:09.069323 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9837 23:11:09.072495 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9838 23:11:09.079331 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9839 23:11:09.082646 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9840 23:11:09.085930 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9841 23:11:09.093118 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9842 23:11:09.095662 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9843 23:11:09.102312 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9844 23:11:09.105509 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9845 23:11:09.108846 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9846 23:11:09.115499 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9847 23:11:09.119236 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9848 23:11:09.125576 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9849 23:11:09.128683 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9850 23:11:09.135755 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9851 23:11:09.138534 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9852 23:11:09.145090 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9853 23:11:09.148210 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9854 23:11:09.151700 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9855 23:11:09.158344 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9856 23:11:09.161424 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9857 23:11:09.168353 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9858 23:11:09.172007 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9859 23:11:09.174736 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9860 23:11:09.181075 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9861 23:11:09.185229 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9862 23:11:09.191332 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9863 23:11:09.194497 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9864 23:11:09.200855 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9865 23:11:09.204124 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9866 23:11:09.207686 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9867 23:11:09.214867 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9868 23:11:09.218118 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9869 23:11:09.224215 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9870 23:11:09.227489 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9871 23:11:09.234383 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9872 23:11:09.237407 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9873 23:11:09.244248 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9874 23:11:09.247525 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9875 23:11:09.253853 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9876 23:11:09.256714 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9877 23:11:09.260432 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9878 23:11:09.267173 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9879 23:11:09.270148 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9880 23:11:09.277055 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9881 23:11:09.279657 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9882 23:11:09.286579 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9883 23:11:09.291188 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9884 23:11:09.296752 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9885 23:11:09.300124 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9886 23:11:09.302956 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9887 23:11:09.309755 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9888 23:11:09.313741 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9889 23:11:09.319751 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9890 23:11:09.322491 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9891 23:11:09.329335 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9892 23:11:09.332648 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9893 23:11:09.339989 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9894 23:11:09.342632 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9895 23:11:09.346393 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9896 23:11:09.352939 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9897 23:11:09.355347 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9898 23:11:09.362156 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9899 23:11:09.365076 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9900 23:11:09.372934 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9901 23:11:09.374921 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9902 23:11:09.382174 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9903 23:11:09.385738 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9904 23:11:09.391614 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9905 23:11:09.395945 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9906 23:11:09.398136 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9907 23:11:09.405357 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9908 23:11:09.408148 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9909 23:11:09.414664 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9910 23:11:09.417796 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9911 23:11:09.421444 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9912 23:11:09.427998 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9913 23:11:09.431740 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9914 23:11:09.437473 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9915 23:11:09.440895 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9916 23:11:09.447533 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9917 23:11:09.450440 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9918 23:11:09.457257 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9919 23:11:09.460353 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9920 23:11:09.467767 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9921 23:11:09.470254 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9922 23:11:09.476938 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9923 23:11:09.480059 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9924 23:11:09.487072 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9925 23:11:09.490310 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9926 23:11:09.496726 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9927 23:11:09.500346 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9928 23:11:09.506877 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9929 23:11:09.510470 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9930 23:11:09.516496 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9931 23:11:09.523070 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9932 23:11:09.526522 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9933 23:11:09.533219 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9934 23:11:09.535795 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9935 23:11:09.543033 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9936 23:11:09.546018 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9937 23:11:09.552738 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9938 23:11:09.556895 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9939 23:11:09.562341 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9940 23:11:09.565592 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9941 23:11:09.573500 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9942 23:11:09.575474 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9943 23:11:09.579408 INFO: [APUAPC] vio 0
9944 23:11:09.582310 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9945 23:11:09.588947 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9946 23:11:09.592052 INFO: [APUAPC] D0_APC_0: 0x400510
9947 23:11:09.592510 INFO: [APUAPC] D0_APC_1: 0x0
9948 23:11:09.595584 INFO: [APUAPC] D0_APC_2: 0x1540
9949 23:11:09.598449 INFO: [APUAPC] D0_APC_3: 0x0
9950 23:11:09.601673 INFO: [APUAPC] D1_APC_0: 0xffffffff
9951 23:11:09.605042 INFO: [APUAPC] D1_APC_1: 0xffffffff
9952 23:11:09.609102 INFO: [APUAPC] D1_APC_2: 0x3fffff
9953 23:11:09.612328 INFO: [APUAPC] D1_APC_3: 0x0
9954 23:11:09.614881 INFO: [APUAPC] D2_APC_0: 0xffffffff
9955 23:11:09.617921 INFO: [APUAPC] D2_APC_1: 0xffffffff
9956 23:11:09.621877 INFO: [APUAPC] D2_APC_2: 0x3fffff
9957 23:11:09.624902 INFO: [APUAPC] D2_APC_3: 0x0
9958 23:11:09.627868 INFO: [APUAPC] D3_APC_0: 0xffffffff
9959 23:11:09.631635 INFO: [APUAPC] D3_APC_1: 0xffffffff
9960 23:11:09.634357 INFO: [APUAPC] D3_APC_2: 0x3fffff
9961 23:11:09.638014 INFO: [APUAPC] D3_APC_3: 0x0
9962 23:11:09.642278 INFO: [APUAPC] D4_APC_0: 0xffffffff
9963 23:11:09.644941 INFO: [APUAPC] D4_APC_1: 0xffffffff
9964 23:11:09.648326 INFO: [APUAPC] D4_APC_2: 0x3fffff
9965 23:11:09.650900 INFO: [APUAPC] D4_APC_3: 0x0
9966 23:11:09.654785 INFO: [APUAPC] D5_APC_0: 0xffffffff
9967 23:11:09.657999 INFO: [APUAPC] D5_APC_1: 0xffffffff
9968 23:11:09.660855 INFO: [APUAPC] D5_APC_2: 0x3fffff
9969 23:11:09.664180 INFO: [APUAPC] D5_APC_3: 0x0
9970 23:11:09.667940 INFO: [APUAPC] D6_APC_0: 0xffffffff
9971 23:11:09.670614 INFO: [APUAPC] D6_APC_1: 0xffffffff
9972 23:11:09.674044 INFO: [APUAPC] D6_APC_2: 0x3fffff
9973 23:11:09.677575 INFO: [APUAPC] D6_APC_3: 0x0
9974 23:11:09.680390 INFO: [APUAPC] D7_APC_0: 0xffffffff
9975 23:11:09.683873 INFO: [APUAPC] D7_APC_1: 0xffffffff
9976 23:11:09.687156 INFO: [APUAPC] D7_APC_2: 0x3fffff
9977 23:11:09.691156 INFO: [APUAPC] D7_APC_3: 0x0
9978 23:11:09.693584 INFO: [APUAPC] D8_APC_0: 0xffffffff
9979 23:11:09.696818 INFO: [APUAPC] D8_APC_1: 0xffffffff
9980 23:11:09.700738 INFO: [APUAPC] D8_APC_2: 0x3fffff
9981 23:11:09.704558 INFO: [APUAPC] D8_APC_3: 0x0
9982 23:11:09.707002 INFO: [APUAPC] D9_APC_0: 0xffffffff
9983 23:11:09.710142 INFO: [APUAPC] D9_APC_1: 0xffffffff
9984 23:11:09.713656 INFO: [APUAPC] D9_APC_2: 0x3fffff
9985 23:11:09.716447 INFO: [APUAPC] D9_APC_3: 0x0
9986 23:11:09.719949 INFO: [APUAPC] D10_APC_0: 0xffffffff
9987 23:11:09.723236 INFO: [APUAPC] D10_APC_1: 0xffffffff
9988 23:11:09.726694 INFO: [APUAPC] D10_APC_2: 0x3fffff
9989 23:11:09.729799 INFO: [APUAPC] D10_APC_3: 0x0
9990 23:11:09.733735 INFO: [APUAPC] D11_APC_0: 0xffffffff
9991 23:11:09.736541 INFO: [APUAPC] D11_APC_1: 0xffffffff
9992 23:11:09.739621 INFO: [APUAPC] D11_APC_2: 0x3fffff
9993 23:11:09.743248 INFO: [APUAPC] D11_APC_3: 0x0
9994 23:11:09.746556 INFO: [APUAPC] D12_APC_0: 0xffffffff
9995 23:11:09.750375 INFO: [APUAPC] D12_APC_1: 0xffffffff
9996 23:11:09.752868 INFO: [APUAPC] D12_APC_2: 0x3fffff
9997 23:11:09.756474 INFO: [APUAPC] D12_APC_3: 0x0
9998 23:11:09.759513 INFO: [APUAPC] D13_APC_0: 0xffffffff
9999 23:11:09.762779 INFO: [APUAPC] D13_APC_1: 0xffffffff
10000 23:11:09.766504 INFO: [APUAPC] D13_APC_2: 0x3fffff
10001 23:11:09.769249 INFO: [APUAPC] D13_APC_3: 0x0
10002 23:11:09.772571 INFO: [APUAPC] D14_APC_0: 0xffffffff
10003 23:11:09.776100 INFO: [APUAPC] D14_APC_1: 0xffffffff
10004 23:11:09.779452 INFO: [APUAPC] D14_APC_2: 0x3fffff
10005 23:11:09.782905 INFO: [APUAPC] D14_APC_3: 0x0
10006 23:11:09.785984 INFO: [APUAPC] D15_APC_0: 0xffffffff
10007 23:11:09.788985 INFO: [APUAPC] D15_APC_1: 0xffffffff
10008 23:11:09.792514 INFO: [APUAPC] D15_APC_2: 0x3fffff
10009 23:11:09.795734 INFO: [APUAPC] D15_APC_3: 0x0
10010 23:11:09.798983 INFO: [APUAPC] APC_CON: 0x4
10011 23:11:09.802231 INFO: [NOCDAPC] D0_APC_0: 0x0
10012 23:11:09.805721 INFO: [NOCDAPC] D0_APC_1: 0x0
10013 23:11:09.810500 INFO: [NOCDAPC] D1_APC_0: 0x0
10014 23:11:09.812389 INFO: [NOCDAPC] D1_APC_1: 0xfff
10015 23:11:09.815779 INFO: [NOCDAPC] D2_APC_0: 0x0
10016 23:11:09.816367 INFO: [NOCDAPC] D2_APC_1: 0xfff
10017 23:11:09.818995 INFO: [NOCDAPC] D3_APC_0: 0x0
10018 23:11:09.822374 INFO: [NOCDAPC] D3_APC_1: 0xfff
10019 23:11:09.825408 INFO: [NOCDAPC] D4_APC_0: 0x0
10020 23:11:09.828553 INFO: [NOCDAPC] D4_APC_1: 0xfff
10021 23:11:09.832323 INFO: [NOCDAPC] D5_APC_0: 0x0
10022 23:11:09.835128 INFO: [NOCDAPC] D5_APC_1: 0xfff
10023 23:11:09.838664 INFO: [NOCDAPC] D6_APC_0: 0x0
10024 23:11:09.841791 INFO: [NOCDAPC] D6_APC_1: 0xfff
10025 23:11:09.845108 INFO: [NOCDAPC] D7_APC_0: 0x0
10026 23:11:09.848738 INFO: [NOCDAPC] D7_APC_1: 0xfff
10027 23:11:09.851805 INFO: [NOCDAPC] D8_APC_0: 0x0
10028 23:11:09.852312 INFO: [NOCDAPC] D8_APC_1: 0xfff
10029 23:11:09.855634 INFO: [NOCDAPC] D9_APC_0: 0x0
10030 23:11:09.858341 INFO: [NOCDAPC] D9_APC_1: 0xfff
10031 23:11:09.861714 INFO: [NOCDAPC] D10_APC_0: 0x0
10032 23:11:09.864906 INFO: [NOCDAPC] D10_APC_1: 0xfff
10033 23:11:09.868906 INFO: [NOCDAPC] D11_APC_0: 0x0
10034 23:11:09.871758 INFO: [NOCDAPC] D11_APC_1: 0xfff
10035 23:11:09.874947 INFO: [NOCDAPC] D12_APC_0: 0x0
10036 23:11:09.878165 INFO: [NOCDAPC] D12_APC_1: 0xfff
10037 23:11:09.882457 INFO: [NOCDAPC] D13_APC_0: 0x0
10038 23:11:09.884903 INFO: [NOCDAPC] D13_APC_1: 0xfff
10039 23:11:09.887979 INFO: [NOCDAPC] D14_APC_0: 0x0
10040 23:11:09.891318 INFO: [NOCDAPC] D14_APC_1: 0xfff
10041 23:11:09.894677 INFO: [NOCDAPC] D15_APC_0: 0x0
10042 23:11:09.897949 INFO: [NOCDAPC] D15_APC_1: 0xfff
10043 23:11:09.898517 INFO: [NOCDAPC] APC_CON: 0x4
10044 23:11:09.901589 INFO: [APUAPC] set_apusys_apc done
10045 23:11:09.904795 INFO: [DEVAPC] devapc_init done
10046 23:11:09.911661 INFO: GICv3 without legacy support detected.
10047 23:11:09.914220 INFO: ARM GICv3 driver initialized in EL3
10048 23:11:09.917892 INFO: Maximum SPI INTID supported: 639
10049 23:11:09.921034 INFO: BL31: Initializing runtime services
10050 23:11:09.927870 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10051 23:11:09.931177 INFO: SPM: enable CPC mode
10052 23:11:09.934186 INFO: mcdi ready for mcusys-off-idle and system suspend
10053 23:11:09.940391 INFO: BL31: Preparing for EL3 exit to normal world
10054 23:11:09.944485 INFO: Entry point address = 0x80000000
10055 23:11:09.946726 INFO: SPSR = 0x8
10056 23:11:09.952115
10057 23:11:09.952637
10058 23:11:09.953170
10059 23:11:09.954522 Starting depthcharge on Spherion...
10060 23:11:09.954994
10061 23:11:09.955324 Wipe memory regions:
10062 23:11:09.955687
10063 23:11:09.958212 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
10064 23:11:09.958727 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10065 23:11:09.959134 Setting prompt string to ['asurada:']
10066 23:11:09.959607 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10067 23:11:09.960270 [0x00000040000000, 0x00000054600000)
10068 23:11:10.080373
10069 23:11:10.080913 [0x00000054660000, 0x00000080000000)
10070 23:11:10.340898
10071 23:11:10.341440 [0x000000821a7280, 0x000000ffe64000)
10072 23:11:11.085675
10073 23:11:11.086354 [0x00000100000000, 0x00000240000000)
10074 23:11:12.975578
10075 23:11:12.978950 Initializing XHCI USB controller at 0x11200000.
10076 23:11:14.016823
10077 23:11:14.020329 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10078 23:11:14.020430
10079 23:11:14.020494
10080 23:11:14.020553
10081 23:11:14.020879 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10083 23:11:14.121239 asurada: tftpboot 192.168.201.1 12395392/tftp-deploy-l3kfndy0/kernel/image.itb 12395392/tftp-deploy-l3kfndy0/kernel/cmdline
10084 23:11:14.121416 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10085 23:11:14.121542 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10086 23:11:14.125787 tftpboot 192.168.201.1 12395392/tftp-deploy-l3kfndy0/kernel/image.itbtp-deploy-l3kfndy0/kernel/cmdline
10087 23:11:14.125875
10088 23:11:14.125939 Waiting for link
10089 23:11:14.286225
10090 23:11:14.286371 R8152: Initializing
10091 23:11:14.286439
10092 23:11:14.290070 Version 6 (ocp_data = 5c30)
10093 23:11:14.290154
10094 23:11:14.293265 R8152: Done initializing
10095 23:11:14.293346
10096 23:11:14.293409 Adding net device
10097 23:11:16.258368
10098 23:11:16.258515 done.
10099 23:11:16.258583
10100 23:11:16.258670 MAC: 00:24:32:30:7c:7b
10101 23:11:16.258757
10102 23:11:16.261803 Sending DHCP discover... done.
10103 23:11:16.261886
10104 23:11:16.264958 Waiting for reply... done.
10105 23:11:16.265041
10106 23:11:16.268193 Sending DHCP request... done.
10107 23:11:16.268300
10108 23:11:16.274095 Waiting for reply... done.
10109 23:11:16.274179
10110 23:11:16.274251 My ip is 192.168.201.14
10111 23:11:16.274312
10112 23:11:16.276687 The DHCP server ip is 192.168.201.1
10113 23:11:16.276773
10114 23:11:16.283850 TFTP server IP predefined by user: 192.168.201.1
10115 23:11:16.283940
10116 23:11:16.290321 Bootfile predefined by user: 12395392/tftp-deploy-l3kfndy0/kernel/image.itb
10117 23:11:16.290430
10118 23:11:16.293607 Sending tftp read request... done.
10119 23:11:16.293697
10120 23:11:16.296847 Waiting for the transfer...
10121 23:11:16.296925
10122 23:11:16.874116 00000000 ################################################################
10123 23:11:16.874266
10124 23:11:17.444097 00080000 ################################################################
10125 23:11:17.444248
10126 23:11:18.004990 00100000 ################################################################
10127 23:11:18.005147
10128 23:11:18.566116 00180000 ################################################################
10129 23:11:18.566276
10130 23:11:19.139570 00200000 ################################################################
10131 23:11:19.139736
10132 23:11:19.711706 00280000 ################################################################
10133 23:11:19.711841
10134 23:11:20.285962 00300000 ################################################################
10135 23:11:20.286131
10136 23:11:20.871220 00380000 ################################################################
10137 23:11:20.871463
10138 23:11:21.473930 00400000 ################################################################
10139 23:11:21.474066
10140 23:11:22.050710 00480000 ################################################################
10141 23:11:22.050863
10142 23:11:22.644708 00500000 ################################################################
10143 23:11:22.644860
10144 23:11:23.243926 00580000 ################################################################
10145 23:11:23.244071
10146 23:11:23.836309 00600000 ################################################################
10147 23:11:23.836456
10148 23:11:24.430015 00680000 ################################################################
10149 23:11:24.430191
10150 23:11:25.007979 00700000 ################################################################
10151 23:11:25.008146
10152 23:11:25.591234 00780000 ################################################################
10153 23:11:25.591408
10154 23:11:26.192505 00800000 ################################################################
10155 23:11:26.192654
10156 23:11:26.774837 00880000 ################################################################
10157 23:11:26.775009
10158 23:11:27.350520 00900000 ################################################################
10159 23:11:27.350682
10160 23:11:27.881978 00980000 ################################################################
10161 23:11:27.882185
10162 23:11:28.441572 00a00000 ################################################################
10163 23:11:28.441756
10164 23:11:29.022815 00a80000 ################################################################
10165 23:11:29.022959
10166 23:11:29.595310 00b00000 ################################################################
10167 23:11:29.595499
10168 23:11:30.179305 00b80000 ################################################################
10169 23:11:30.179495
10170 23:11:30.785374 00c00000 ################################################################
10171 23:11:30.785511
10172 23:11:31.385894 00c80000 ################################################################
10173 23:11:31.386039
10174 23:11:31.978808 00d00000 ################################################################
10175 23:11:31.978954
10176 23:11:32.559221 00d80000 ################################################################
10177 23:11:32.559428
10178 23:11:33.151176 00e00000 ################################################################
10179 23:11:33.151348
10180 23:11:33.720761 00e80000 ################################################################
10181 23:11:33.720903
10182 23:11:34.308076 00f00000 ################################################################
10183 23:11:34.308221
10184 23:11:34.909032 00f80000 ################################################################
10185 23:11:34.909186
10186 23:11:35.497063 01000000 ################################################################
10187 23:11:35.497201
10188 23:11:36.073590 01080000 ################################################################
10189 23:11:36.073737
10190 23:11:36.655334 01100000 ################################################################
10191 23:11:36.655501
10192 23:11:37.256103 01180000 ################################################################
10193 23:11:37.256246
10194 23:11:37.858197 01200000 ################################################################
10195 23:11:37.858349
10196 23:11:38.461068 01280000 ################################################################
10197 23:11:38.461214
10198 23:11:39.045401 01300000 ################################################################
10199 23:11:39.045552
10200 23:11:39.632056 01380000 ################################################################
10201 23:11:39.632211
10202 23:11:40.232355 01400000 ################################################################
10203 23:11:40.232517
10204 23:11:40.819928 01480000 ################################################################
10205 23:11:40.820090
10206 23:11:41.411041 01500000 ################################################################
10207 23:11:41.411200
10208 23:11:42.007807 01580000 ################################################################
10209 23:11:42.007971
10210 23:11:42.595883 01600000 ################################################################
10211 23:11:42.596045
10212 23:11:43.167937 01680000 ################################################################
10213 23:11:43.168096
10214 23:11:43.746466 01700000 ################################################################
10215 23:11:43.746627
10216 23:11:44.293376 01780000 ################################################################
10217 23:11:44.293538
10218 23:11:44.856888 01800000 ################################################################
10219 23:11:44.857065
10220 23:11:45.427345 01880000 ################################################################
10221 23:11:45.427524
10222 23:11:46.008616 01900000 ################################################################
10223 23:11:46.008781
10224 23:11:46.580832 01980000 ################################################################
10225 23:11:46.580992
10226 23:11:47.137479 01a00000 ################################################################
10227 23:11:47.137636
10228 23:11:47.709872 01a80000 ################################################################
10229 23:11:47.710034
10230 23:11:48.270196 01b00000 ################################################################
10231 23:11:48.270362
10232 23:11:48.806540 01b80000 ############################################################ done.
10233 23:11:48.806697
10234 23:11:48.809696 The bootfile was 29322710 bytes long.
10235 23:11:48.809799
10236 23:11:48.812963 Sending tftp read request... done.
10237 23:11:48.813092
10238 23:11:48.813159 Waiting for the transfer...
10239 23:11:48.813219
10240 23:11:48.816323 00000000 # done.
10241 23:11:48.816419
10242 23:11:48.823637 Command line loaded dynamically from TFTP file: 12395392/tftp-deploy-l3kfndy0/kernel/cmdline
10243 23:11:48.823757
10244 23:11:48.845877 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12395392/extract-nfsrootfs-_9e2sa3_,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10245 23:11:48.846030
10246 23:11:48.846100 Loading FIT.
10247 23:11:48.846159
10248 23:11:48.849379 Image ramdisk-1 has 17793011 bytes.
10249 23:11:48.849473
10250 23:11:48.852630 Image fdt-1 has 47278 bytes.
10251 23:11:48.852719
10252 23:11:48.855777 Image kernel-1 has 11480388 bytes.
10253 23:11:48.855863
10254 23:11:48.865889 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10255 23:11:48.866024
10256 23:11:48.882316 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10257 23:11:48.882469
10258 23:11:48.889681 Choosing best match conf-1 for compat google,spherion-rev2.
10259 23:11:48.889809
10260 23:11:48.896948 Connected to device vid:did:rid of 1ae0:0028:00
10261 23:11:48.903625
10262 23:11:48.907002 tpm_get_response: command 0x17b, return code 0x0
10263 23:11:48.907107
10264 23:11:48.913295 ec_init: CrosEC protocol v3 supported (256, 248)
10265 23:11:48.913407
10266 23:11:48.916581 tpm_cleanup: add release locality here.
10267 23:11:48.916673
10268 23:11:48.920237 Shutting down all USB controllers.
10269 23:11:48.920332
10270 23:11:48.923211 Removing current net device
10271 23:11:48.923299
10272 23:11:48.929820 Exiting depthcharge with code 4 at timestamp: 68235335
10273 23:11:48.929936
10274 23:11:48.933377 LZMA decompressing kernel-1 to 0x821a6718
10275 23:11:48.933465
10276 23:11:48.936560 LZMA decompressing kernel-1 to 0x40000000
10277 23:11:50.371658
10278 23:11:50.371810 jumping to kernel
10279 23:11:50.372265 end: 2.2.4 bootloader-commands (duration 00:00:40) [common]
10280 23:11:50.372364 start: 2.2.5 auto-login-action (timeout 00:03:45) [common]
10281 23:11:50.372441 Setting prompt string to ['Linux version [0-9]']
10282 23:11:50.372510 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10283 23:11:50.372575 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10284 23:11:50.453532
10285 23:11:50.456791 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10286 23:11:50.460528 start: 2.2.5.1 login-action (timeout 00:03:45) [common]
10287 23:11:50.460623 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10288 23:11:50.460694 Setting prompt string to []
10289 23:11:50.460770 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10290 23:11:50.460840 Using line separator: #'\n'#
10291 23:11:50.460898 No login prompt set.
10292 23:11:50.460961 Parsing kernel messages
10293 23:11:50.461014 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10294 23:11:50.461113 [login-action] Waiting for messages, (timeout 00:03:45)
10295 23:11:50.479913 [ 0.000000] Linux version 6.1.67-cip12-rt7 (KernelCI@build-j59954-arm64-gcc-10-defconfig-arm64-chromebook-nblph) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Wed Dec 27 22:50:56 UTC 2023
10296 23:11:50.483207 [ 0.000000] random: crng init done
10297 23:11:50.489714 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10298 23:11:50.493399 [ 0.000000] efi: UEFI not found.
10299 23:11:50.499636 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10300 23:11:50.509376 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10301 23:11:50.519935 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10302 23:11:50.525946 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10303 23:11:50.532983 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10304 23:11:50.539031 [ 0.000000] printk: bootconsole [mtk8250] enabled
10305 23:11:50.546051 [ 0.000000] NUMA: No NUMA configuration found
10306 23:11:50.552429 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10307 23:11:50.559733 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcfa00-0x23efd1fff]
10308 23:11:50.559829 [ 0.000000] Zone ranges:
10309 23:11:50.565671 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10310 23:11:50.568885 [ 0.000000] DMA32 empty
10311 23:11:50.575973 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10312 23:11:50.579552 [ 0.000000] Movable zone start for each node
10313 23:11:50.582025 [ 0.000000] Early memory node ranges
10314 23:11:50.588543 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10315 23:11:50.595736 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10316 23:11:50.602164 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10317 23:11:50.608504 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10318 23:11:50.615148 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10319 23:11:50.621709 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10320 23:11:50.678291 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10321 23:11:50.685062 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10322 23:11:50.691345 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10323 23:11:50.694914 [ 0.000000] psci: probing for conduit method from DT.
10324 23:11:50.701617 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10325 23:11:50.704530 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10326 23:11:50.711986 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10327 23:11:50.714566 [ 0.000000] psci: SMC Calling Convention v1.2
10328 23:11:50.720988 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10329 23:11:50.724365 [ 0.000000] Detected VIPT I-cache on CPU0
10330 23:11:50.731123 [ 0.000000] CPU features: detected: GIC system register CPU interface
10331 23:11:50.737880 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10332 23:11:50.744165 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10333 23:11:50.750887 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10334 23:11:50.760688 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10335 23:11:50.767257 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10336 23:11:50.770687 [ 0.000000] alternatives: applying boot alternatives
10337 23:11:50.777408 [ 0.000000] Fallback order for Node 0: 0
10338 23:11:50.783769 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10339 23:11:50.787252 [ 0.000000] Policy zone: Normal
10340 23:11:50.810134 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12395392/extract-nfsrootfs-_9e2sa3_,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10341 23:11:50.819947 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10342 23:11:50.831179 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10343 23:11:50.840656 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10344 23:11:50.847188 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10345 23:11:50.850401 <6>[ 0.000000] software IO TLB: area num 8.
10346 23:11:50.907786 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10347 23:11:51.056529 <6>[ 0.000000] Memory: 7951340K/8385536K available (17984K kernel code, 4116K rwdata, 18184K rodata, 8448K init, 615K bss, 401428K reserved, 32768K cma-reserved)
10348 23:11:51.063286 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10349 23:11:51.069717 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10350 23:11:51.073317 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10351 23:11:51.079606 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10352 23:11:51.086327 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10353 23:11:51.089764 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10354 23:11:51.099754 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10355 23:11:51.106566 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10356 23:11:51.112878 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10357 23:11:51.119216 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10358 23:11:51.123273 <6>[ 0.000000] GICv3: 608 SPIs implemented
10359 23:11:51.126535 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10360 23:11:51.132803 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10361 23:11:51.135935 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10362 23:11:51.142323 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10363 23:11:51.156195 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10364 23:11:51.168510 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10365 23:11:51.175724 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10366 23:11:51.183601 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10367 23:11:51.196281 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10368 23:11:51.203040 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10369 23:11:51.209693 <6>[ 0.009184] Console: colour dummy device 80x25
10370 23:11:51.220001 <6>[ 0.013909] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10371 23:11:51.226467 <6>[ 0.024350] pid_max: default: 32768 minimum: 301
10372 23:11:51.229391 <6>[ 0.029222] LSM: Security Framework initializing
10373 23:11:51.236103 <6>[ 0.034159] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10374 23:11:51.245841 <6>[ 0.041973] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10375 23:11:51.256099 <6>[ 0.051384] cblist_init_generic: Setting adjustable number of callback queues.
10376 23:11:51.259151 <6>[ 0.058825] cblist_init_generic: Setting shift to 3 and lim to 1.
10377 23:11:51.269489 <6>[ 0.065164] cblist_init_generic: Setting adjustable number of callback queues.
10378 23:11:51.275764 <6>[ 0.072591] cblist_init_generic: Setting shift to 3 and lim to 1.
10379 23:11:51.279029 <6>[ 0.079068] rcu: Hierarchical SRCU implementation.
10380 23:11:51.285890 <6>[ 0.079070] rcu: Max phase no-delay instances is 1000.
10381 23:11:51.292332 <6>[ 0.079094] printk: bootconsole [mtk8250] printing thread started
10382 23:11:51.298742 <6>[ 0.097412] EFI services will not be available.
10383 23:11:51.302974 <6>[ 0.097617] smp: Bringing up secondary CPUs ...
10384 23:11:51.305482 <6>[ 0.097920] Detected VIPT I-cache on CPU1
10385 23:11:51.315912 <6>[ 0.097989] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10386 23:11:51.322318 <6>[ 0.098020] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10387 23:11:51.331092 <6>[ 0.125897] Detected VIPT I-cache on CPU2
10388 23:11:51.337939 <6>[ 0.125947] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10389 23:11:51.348214 <6>[ 0.125963] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10390 23:11:51.351337 <6>[ 0.126217] Detected VIPT I-cache on CPU3
10391 23:11:51.357857 <6>[ 0.126263] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10392 23:11:51.364233 <6>[ 0.126276] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10393 23:11:51.370765 <6>[ 0.126588] CPU features: detected: Spectre-v4
10394 23:11:51.374204 <6>[ 0.126594] CPU features: detected: Spectre-BHB
10395 23:11:51.377496 <6>[ 0.126598] Detected PIPT I-cache on CPU4
10396 23:11:51.384749 <6>[ 0.126658] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10397 23:11:51.390591 <6>[ 0.126674] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10398 23:11:51.397410 <6>[ 0.126965] Detected PIPT I-cache on CPU5
10399 23:11:51.403982 <6>[ 0.127025] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10400 23:11:51.410527 <6>[ 0.127042] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10401 23:11:51.413847 <6>[ 0.127315] Detected PIPT I-cache on CPU6
10402 23:11:51.423545 <6>[ 0.127381] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10403 23:11:51.430640 <6>[ 0.127397] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10404 23:11:51.433399 <6>[ 0.127691] Detected PIPT I-cache on CPU7
10405 23:11:51.439998 <6>[ 0.127756] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10406 23:11:51.446694 <6>[ 0.127772] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10407 23:11:51.450357 <6>[ 0.127819] smp: Brought up 1 node, 8 CPUs
10408 23:11:51.456578 <6>[ 0.127823] SMP: Total of 8 processors activated.
10409 23:11:51.464058 <6>[ 0.127826] CPU features: detected: 32-bit EL0 Support
10410 23:11:51.469974 <6>[ 0.127828] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10411 23:11:51.476660 <6>[ 0.127831] CPU features: detected: Common not Private translations
10412 23:11:51.482984 <6>[ 0.127832] CPU features: detected: CRC32 instructions
10413 23:11:51.489486 <6>[ 0.127835] CPU features: detected: RCpc load-acquire (LDAPR)
10414 23:11:51.493169 <6>[ 0.127837] CPU features: detected: LSE atomic instructions
10415 23:11:51.499546 <6>[ 0.127839] CPU features: detected: Privileged Access Never
10416 23:11:51.505999 <6>[ 0.127840] CPU features: detected: RAS Extension Support
10417 23:11:51.513089 <6>[ 0.127843] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10418 23:11:51.515587 <6>[ 0.127911] CPU: All CPU(s) started at EL2
10419 23:11:51.522005 <6>[ 0.127913] alternatives: applying system-wide alternatives
10420 23:11:51.551843 �B+ս�}�r�r�j��<6>[ < 0.348920] printk: console [ttyS0] printing thread started
10421 23:11:51.554863 6<6>[ 0.348952] printk: console [ttyS0] enabled
10422 23:11:51.562333 >[ 0.225455] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10423 23:11:51.570067 <6>[ 0.348956] printk: bootconsole [mtk8250] disabled
10424 23:11:51.576491 <6>[ 0.366337] printk: bootconsole [mtk8250] printing thread stopped
10425 23:11:51.579760 <6>[ 0.367549] SuperH (H)SCI(F) driver initialized
10426 23:11:51.586155 <6>[ 0.368039] msm_serial: driver initialized
10427 23:11:51.592970 <6>[ 0.372709] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10428 23:11:51.602810 <6>[ 0.372741] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10429 23:11:51.609617 <6>[ 0.372772] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10430 23:11:51.618496 <6>[ 0.372802] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10431 23:11:51.629649 <6>[ 0.372823] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10432 23:11:51.642115 <6>[ 0.372851] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10433 23:11:51.657654 <6>[ 0.372880] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10434 23:11:51.658298 <6>[ 0.372997] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10435 23:11:51.663840 <6>[ 0.373027] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10436 23:11:51.671164 <6>[ 0.384322] loop: module loaded
10437 23:11:51.677837 <6>[ 0.386967] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10438 23:11:51.678394 <4>[ 0.403730] mtk-pmic-keys: Failed to locate of_node [id: -1]
10439 23:11:51.681052 <6>[ 0.404561] megasas: 07.719.03.00-rc1
10440 23:11:51.688053 <6>[ 0.416866] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10441 23:11:51.694632 <6>[ 0.420741] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10442 23:11:51.701501 <6>[ 0.432746] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10443 23:11:51.710894 <6>[ 0.484595] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9
10444 23:11:52.181775 <6>[ 0.980952] Freeing initrd memory: 17372K
10445 23:11:52.189952 <6>[ 0.986878] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10446 23:11:52.196635 <6>[ 0.991440] tun: Universal TUN/TAP device driver, 1.6
10447 23:11:52.199648 <6>[ 0.992183] thunder_xcv, ver 1.0
10448 23:11:52.203184 <6>[ 0.992200] thunder_bgx, ver 1.0
10449 23:11:52.206491 <6>[ 0.992216] nicpf, ver 1.0
10450 23:11:52.212890 <6>[ 0.993258] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10451 23:11:52.219925 <6>[ 0.993261] hns3: Copyright (c) 2017 Huawei Corporation.
10452 23:11:52.222894 <6>[ 0.993285] hclge is initializing
10453 23:11:52.229618 <6>[ 0.993299] e1000: Intel(R) PRO/1000 Network Driver
10454 23:11:52.233055 <6>[ 0.993301] e1000: Copyright (c) 1999-2006 Intel Corporation.
10455 23:11:52.240241 <6>[ 0.993336] e1000e: Intel(R) PRO/1000 Network Driver
10456 23:11:52.243918 <6>[ 0.993338] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10457 23:11:52.250947 <6>[ 0.993353] igb: Intel(R) Gigabit Ethernet Network Driver
10458 23:11:52.257652 <6>[ 0.993356] igb: Copyright (c) 2007-2014 Intel Corporation.
10459 23:11:52.264848 <6>[ 0.993369] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10460 23:11:52.268130 <6>[ 0.993371] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10461 23:11:52.274748 <6>[ 0.993664] sky2: driver version 1.30
10462 23:11:52.277840 <6>[ 0.994734] VFIO - User Level meta-driver version: 0.3
10463 23:11:52.284780 <6>[ 0.997582] usbcore: registered new interface driver usb-storage
10464 23:11:52.291634 <6>[ 0.997759] usbcore: registered new device driver onboard-usb-hub
10465 23:11:52.297994 <6>[ 1.000503] mt6397-rtc mt6359-rtc: registered as rtc0
10466 23:11:52.304678 <6>[ 1.000654] mt6397-rtc mt6359-rtc: setting system clock to 2023-12-27T23:11:56 UTC (1703718716)
10467 23:11:52.311187 <6>[ 1.001267] i2c_dev: i2c /dev entries driver
10468 23:11:52.318004 <6>[ 1.008392] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10469 23:11:52.321351 <6>[ 1.023401] cpu cpu0: EM: created perf domain
10470 23:11:52.328009 <6>[ 1.023703] cpu cpu4: EM: created perf domain
10471 23:11:52.335073 <6>[ 1.027482] sdhci: Secure Digital Host Controller Interface driver
10472 23:11:52.337851 <6>[ 1.027484] sdhci: Copyright(c) Pierre Ossman
10473 23:11:52.345040 <6>[ 1.027840] Synopsys Designware Multimedia Card Interface Driver
10474 23:11:52.351009 <6>[ 1.028230] sdhci-pltfm: SDHCI platform and OF driver helper
10475 23:11:52.357736 <6>[ 1.032516] ledtrig-cpu: registered to indicate activity on CPUs
10476 23:11:52.360905 <6>[ 1.033148] mmc0: CQHCI version 5.10
10477 23:11:52.367634 <6>[ 1.033153] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10478 23:11:52.374874 <6>[ 1.033440] usbcore: registered new interface driver usbhid
10479 23:11:52.377533 <6>[ 1.033442] usbhid: USB HID core driver
10480 23:11:52.384494 <6>[ 1.033559] spi_master spi0: will run message pump with realtime priority
10481 23:11:52.397887 <6>[ 1.063426] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10482 23:11:52.410729 <6>[ 1.065619] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10483 23:11:52.417515 <6>[ 1.066512] cros-ec-spi spi0.0: Chrome EC device registered
10484 23:11:52.424249 <6>[ 1.077753] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10485 23:11:52.430528 <6>[ 1.078700] NET: Registered PF_PACKET protocol family
10486 23:11:52.434297 <6>[ 1.078767] 9pnet: Installing 9P2000 support
10487 23:11:52.440824 <5>[ 1.078803] Key type dns_resolver registered
10488 23:11:52.443484 <6>[ 1.079230] registered taskstats version 1
10489 23:11:52.450724 <5>[ 1.079245] Loading compiled-in X.509 certificates
10490 23:11:52.460329 <4>[ 1.096780] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10491 23:11:52.470419 <4>[ 1.097112] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10492 23:11:52.476769 <3>[ 1.097130] debugfs: File 'uA_load' in directory '/' already present!
10493 23:11:52.483373 <3>[ 1.097141] debugfs: File 'min_uV' in directory '/' already present!
10494 23:11:52.490077 <3>[ 1.097147] debugfs: File 'max_uV' in directory '/' already present!
10495 23:11:52.496855 <3>[ 1.097152] debugfs: File 'constraint_flags' in directory '/' already present!
10496 23:11:52.507198 <3>[ 1.100236] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10497 23:11:52.513049 <6>[ 1.108110] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10498 23:11:52.516458 <6>[ 1.108679] xhci-mtk 11200000.usb: xHCI Host Controller
10499 23:11:52.526519 <6>[ 1.108701] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10500 23:11:52.536492 <6>[ 1.108919] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10501 23:11:52.539634 <6>[ 1.108972] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10502 23:11:52.546320 <6>[ 1.109068] xhci-mtk 11200000.usb: xHCI Host Controller
10503 23:11:52.552723 <6>[ 1.109077] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10504 23:11:52.559636 <6>[ 1.109084] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10505 23:11:52.566641 <6>[ 1.109649] hub 1-0:1.0: USB hub found
10506 23:11:52.569758 <6>[ 1.109675] hub 1-0:1.0: 1 port detected
10507 23:11:52.575764 <6>[ 1.109943] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10508 23:11:52.582587 <6>[ 1.110519] hub 2-0:1.0: USB hub found
10509 23:11:52.586311 <6>[ 1.110544] hub 2-0:1.0: 1 port detected
10510 23:11:52.589835 <6>[ 1.113748] mtk-msdc 11f70000.mmc: Got CD GPIO
10511 23:11:52.596462 <6>[ 1.127463] mmc0: Command Queue Engine enabled
10512 23:11:52.602745 <6>[ 1.127477] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10513 23:11:52.605932 <6>[ 1.128020] mmcblk0: mmc0:0001 DA4128 116 GiB
10514 23:11:52.615714 <6>[ 1.128576] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10515 23:11:52.622697 <6>[ 1.128583] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10516 23:11:52.633468 <4>[ 1.128747] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10517 23:11:52.639267 <6>[ 1.129402] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10518 23:11:52.646180 <6>[ 1.129406] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10519 23:11:52.655970 <6>[ 1.129576] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10520 23:11:52.662912 <6>[ 1.129590] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10521 23:11:52.672821 <6>[ 1.129594] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10522 23:11:52.678970 <6>[ 1.129600] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10523 23:11:52.689508 <6>[ 1.131191] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10524 23:11:52.695301 <6>[ 1.131210] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10525 23:11:52.705364 <6>[ 1.131217] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10526 23:11:52.711995 <6>[ 1.131223] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10527 23:11:52.722070 <6>[ 1.131230] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10528 23:11:52.728731 <6>[ 1.131236] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10529 23:11:52.738457 <6>[ 1.131242] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10530 23:11:52.748595 <6>[ 1.131248] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10531 23:11:52.754822 <6>[ 1.131255] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10532 23:11:52.765045 <6>[ 1.131261] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10533 23:11:52.771498 <6>[ 1.131267] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10534 23:11:52.781248 <6>[ 1.131274] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10535 23:11:52.787769 <6>[ 1.131280] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10536 23:11:52.797679 <6>[ 1.131286] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10537 23:11:52.804334 <6>[ 1.131292] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10538 23:11:52.811150 <6>[ 1.131810] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10539 23:11:52.817512 <6>[ 1.132685] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10540 23:11:52.824608 <6>[ 1.133230] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10541 23:11:52.830990 <6>[ 1.133893] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10542 23:11:52.837700 <6>[ 1.134455] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10543 23:11:52.844340 <6>[ 1.134550] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10544 23:11:52.854140 <6>[ 1.134766] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10545 23:11:52.860940 <6>[ 1.134781] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10546 23:11:52.871100 <6>[ 1.134786] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10547 23:11:52.880702 <6>[ 1.134792] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10548 23:11:52.890073 <6>[ 1.134797] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10549 23:11:52.900076 <6>[ 1.134804] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10550 23:11:52.910009 <6>[ 1.134809] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10551 23:11:52.916807 <6>[ 1.134814] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10552 23:11:52.926358 <6>[ 1.134822] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10553 23:11:52.936317 <6>[ 1.134829] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10554 23:11:52.946271 <6>[ 1.134834] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10555 23:11:52.956093 <6>[ 1.135623] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10556 23:11:52.959809 <6>[ 1.135660] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10557 23:11:52.966343 <6>[ 1.136643] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10558 23:11:52.972877 <6>[ 1.137608] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10559 23:11:52.979986 <6>[ 1.145840] Trying to probe devices needed for running init ...
10560 23:11:52.986257 <6>[ 1.537460] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10561 23:11:52.989636 <6>[ 1.690178] hub 1-1:1.0: USB hub found
10562 23:11:52.992471 <6>[ 1.690596] hub 1-1:1.0: 4 ports detected
10563 23:11:52.999155 <6>[ 1.694305] hub 1-1:1.0: USB hub found
10564 23:11:53.002474 <6>[ 1.694685] hub 1-1:1.0: 4 ports detected
10565 23:11:53.020754 <6>[ 1.813615] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10566 23:11:53.041760 <6>[ 1.838403] hub 2-1:1.0: USB hub found
10567 23:11:53.044965 <6>[ 1.838806] hub 2-1:1.0: 3 ports detected
10568 23:11:53.048278 <6>[ 1.840882] hub 2-1:1.0: USB hub found
10569 23:11:53.051552 <6>[ 1.841167] hub 2-1:1.0: 3 ports detected
10570 23:11:53.218021 <6>[ 2.009654] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10571 23:11:53.338131 <6>[ 2.136621] hub 1-1.4:1.0: USB hub found
10572 23:11:53.341537 <6>[ 2.136978] hub 1-1.4:1.0: 2 ports detected
10573 23:11:53.344977 <6>[ 2.140017] hub 1-1.4:1.0: USB hub found
10574 23:11:53.351895 <6>[ 2.140332] hub 1-1.4:1.0: 2 ports detected
10575 23:11:53.421513 <6>[ 2.213726] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10576 23:11:53.637224 <6>[ 2.429611] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10577 23:11:53.821388 <6>[ 2.613608] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10578 23:12:04.641397 <6>[ 13.442596] ALSA device list:
10579 23:12:04.647906 <6>[ 13.442618] No soundcards found.
10580 23:12:04.651218 <6>[ 13.447066] Freeing unused kernel memory: 8448K
10581 23:12:04.654759 <6>[ 13.447321] Run /init as init process
10582 23:12:04.657827 Loading, please wait...
10583 23:12:04.679723 Starting version 247.3-7+deb11u2
10584 23:12:04.891772 <6>[ 13.687120] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10585 23:12:04.894922 <6>[ 13.692901] remoteproc remoteproc0: scp is available
10586 23:12:04.901569 <6>[ 13.693016] remoteproc remoteproc0: powering up scp
10587 23:12:04.908511 <6>[ 13.693025] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10588 23:12:04.915368 <6>[ 13.693066] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10589 23:12:04.932367 <6>[ 13.731415] usbcore: registered new interface driver r8152
10590 23:12:04.942214 <3>[ 13.731984] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10591 23:12:04.949384 <3>[ 13.732020] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10592 23:12:04.959007 <3>[ 13.732030] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10593 23:12:04.968593 <3>[ 13.764011] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10594 23:12:04.975398 <3>[ 13.764082] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10595 23:12:04.985245 <3>[ 13.764092] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10596 23:12:04.991713 <3>[ 13.764104] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10597 23:12:04.998332 <3>[ 13.764112] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10598 23:12:05.008729 <3>[ 13.765852] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10599 23:12:05.011912 <6>[ 13.766860] Bluetooth: Core ver 2.22
10600 23:12:05.018669 <6>[ 13.766973] NET: Registered PF_BLUETOOTH protocol family
10601 23:12:05.025235 <6>[ 13.766977] Bluetooth: HCI device and connection manager initialized
10602 23:12:05.028701 <6>[ 13.767038] Bluetooth: HCI socket layer initialized
10603 23:12:05.035504 <6>[ 13.767045] Bluetooth: L2CAP socket layer initialized
10604 23:12:05.038338 <6>[ 13.767060] Bluetooth: SCO socket layer initialized
10605 23:12:05.049331 <3>[ 13.769860] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10606 23:12:05.055346 <3>[ 13.769877] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10607 23:12:05.065598 <3>[ 13.769881] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10608 23:12:05.071807 <3>[ 13.773858] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10609 23:12:05.079142 <3>[ 13.773875] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10610 23:12:05.088605 <3>[ 13.773883] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10611 23:12:05.095014 <3>[ 13.773892] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10612 23:12:05.105101 <3>[ 13.773896] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10613 23:12:05.111721 <6>[ 13.778132] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10614 23:12:05.118688 <6>[ 13.778664] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10615 23:12:05.127929 <6>[ 13.778682] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10616 23:12:05.138125 <6>[ 13.778688] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10617 23:12:05.144560 <4>[ 13.785114] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10618 23:12:05.152021 <4>[ 13.785237] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10619 23:12:05.161003 <3>[ 13.791487] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10620 23:12:05.165333 <6>[ 13.799447] mc: Linux media interface: v0.10
10621 23:12:05.171157 <6>[ 13.799490] usbcore: registered new interface driver cdc_ether
10622 23:12:05.177699 <4>[ 13.805970] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10623 23:12:05.183852 <4>[ 13.805970] Fallback method does not support PEC.
10624 23:12:05.190523 <6>[ 13.818537] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10625 23:12:05.200445 <6>[ 13.823534] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10626 23:12:05.207631 <6>[ 13.823565] remoteproc remoteproc0: remote processor scp is now up
10627 23:12:05.213768 <3>[ 13.830122] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10628 23:12:05.220354 <6>[ 13.839013] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10629 23:12:05.229946 <3>[ 13.854699] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10630 23:12:05.239963 <4>[ 13.871308] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10631 23:12:05.246981 <4>[ 13.871318] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10632 23:12:05.256701 <6>[ 13.887316] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10633 23:12:05.263000 <6>[ 13.888941] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10634 23:12:05.273493 <6>[ 13.893284] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10635 23:12:05.279592 <6>[ 13.898743] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10636 23:12:05.286762 <6>[ 13.898750] pci_bus 0000:00: root bus resource [bus 00-ff]
10637 23:12:05.292989 <6>[ 13.898757] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10638 23:12:05.302715 <6>[ 13.898762] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10639 23:12:05.309487 <6>[ 13.898797] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10640 23:12:05.315934 <6>[ 13.898823] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10641 23:12:05.322727 <6>[ 13.898916] pci 0000:00:00.0: supports D1 D2
10642 23:12:05.329380 <6>[ 13.898919] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10643 23:12:05.336342 <6>[ 13.900562] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10644 23:12:05.342903 <6>[ 13.900667] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10645 23:12:05.349178 <6>[ 13.900697] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10646 23:12:05.355781 <6>[ 13.900716] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10647 23:12:05.365859 <6>[ 13.900734] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10648 23:12:05.368727 <6>[ 13.900845] pci 0000:01:00.0: supports D1 D2
10649 23:12:05.375826 <6>[ 13.900848] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10650 23:12:05.381974 <6>[ 13.913471] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10651 23:12:05.392056 <6>[ 13.913498] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10652 23:12:05.398918 <6>[ 13.913504] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10653 23:12:05.408745 <6>[ 13.913516] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10654 23:12:05.414908 <6>[ 13.913532] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10655 23:12:05.421853 <6>[ 13.913548] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10656 23:12:05.428101 <6>[ 13.913564] pci 0000:00:00.0: PCI bridge to [bus 01]
10657 23:12:05.435411 <6>[ 13.913571] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10658 23:12:05.441870 <6>[ 13.913680] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10659 23:12:05.448222 <6>[ 13.914713] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10660 23:12:05.454785 <6>[ 13.915312] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10661 23:12:05.457995 <6>[ 13.917546] r8152 2-1.3:1.0 eth0: v1.12.13
10662 23:12:05.467781 <6>[ 13.974653] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10663 23:12:05.478261 <6>[ 13.975167] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10664 23:12:05.484852 <6>[ 13.998405] videodev: Linux video capture interface: v2.00
10665 23:12:05.491266 <6>[ 13.998540] usbcore: registered new interface driver r8153_ecm
10666 23:12:05.497693 <5>[ 14.000823] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10667 23:12:05.504388 <6>[ 14.011720] r8152 2-1.3:1.0 enx002432307c7b: renamed from eth0
10668 23:12:05.510895 <5>[ 14.015531] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10669 23:12:05.518144 <6>[ 14.048401] usbcore: registered new interface driver btusb
10670 23:12:05.527203 <4>[ 14.048929] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10671 23:12:05.533909 <3>[ 14.048939] Bluetooth: hci0: Failed to load firmware file (-2)
10672 23:12:05.537346 <3>[ 14.048942] Bluetooth: hci0: Failed to set up firmware (-2)
10673 23:12:05.550847 <4>[ 14.048946] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10674 23:12:05.557252 <6>[ 14.080168] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10675 23:12:05.570512 <6>[ 14.081453] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10676 23:12:05.573352 <6>[ 14.081748] usbcore: registered new interface driver uvcvideo
10677 23:12:05.580434 <6>[ 14.109454] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10678 23:12:05.589719 <4>[ 14.202059] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10679 23:12:05.596558 <6>[ 14.202078] cfg80211: failed to load regulatory.db
10680 23:12:05.603524 <6>[ 14.281980] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10681 23:12:05.609737 <6>[ 14.282094] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10682 23:12:05.613202 <6>[ 14.301485] mt7921e 0000:01:00.0: ASIC revision: 79610010
10683 23:12:05.623227 <6>[ 14.396529] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
10684 23:12:05.623340 <6>[ 14.396529]
10685 23:12:05.629459 Begin: Loading essential drivers ... done.
10686 23:12:05.632911 Begin: Running /scripts/init-premount ... done.
10687 23:12:05.639576 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10688 23:12:05.649391 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10689 23:12:05.652892 Device /sys/class/net/enx002432307c7b found
10690 23:12:05.652981 done.
10691 23:12:05.715668 IP-Config: enx002432307c7b hardware address 00:24:32:30:7c:7b mtu 1500 DHCP
10692 23:12:05.863324 <6>[ 14.657739] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
10693 23:12:06.704062 <6>[ 15.504687] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10694 23:12:06.759902 <6>[ 15.560505] r8152 2-1.3:1.0 enx002432307c7b: carrier on
10695 23:12:07.699433 IP-Config: no response after 2 secs - giving up
10696 23:12:07.748532 IP-Config: wlp1s0 hardware address d8:f3:bc:78:0c:a1 mtu 1500 DHCP
10697 23:12:08.463443 IP-Config: enx002432307c7b hardware address 00:24:32:30:7c:7b mtu 1500 DHCP
10698 23:12:08.466916 IP-Config: enx002432307c7b complete (dhcp from 192.168.201.1):
10699 23:12:08.473162 address: 192.168.201.14 broadcast: 192.168.201.255 netmask: 255.255.255.0
10700 23:12:08.483207 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10701 23:12:08.489842 host : mt8192-asurada-spherion-r0-cbg-2
10702 23:12:08.497157 domain : lava-rack
10703 23:12:08.499929 rootserver: 192.168.201.1 rootpath:
10704 23:12:08.500031 filename :
10705 23:12:08.585488 done.
10706 23:12:08.592515 Begin: Running /scripts/nfs-bottom ... done.
10707 23:12:08.616618 Begin: Running /scripts/init-bottom ... done.
10708 23:12:09.831553 <6>[ 18.629631] NET: Registered PF_INET6 protocol family
10709 23:12:09.834802 <6>[ 18.633250] Segment Routing with IPv6
10710 23:12:09.841319 <6>[ 18.633283] In-situ OAM (IOAM) with IPv6
10711 23:12:09.975411 <30>[ 18.755976] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10712 23:12:09.978842 <30>[ 18.756976] systemd[1]: Detected architecture arm64.
10713 23:12:09.978959
10714 23:12:09.985441 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10715 23:12:09.985549
10716 23:12:10.003936 <30>[ 18.804232] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10717 23:12:10.819754 <30>[ 19.614890] systemd[1]: Queued start job for default target Graphical Interface.
10718 23:12:10.846181 [[0;32m OK [<30>[ 19.643992] systemd[1]: Created slice system-getty.slice.
10719 23:12:10.849388 0m] Created slice [0;1;39msystem-getty.slice[0m.
10720 23:12:10.868624 [[0;32m OK [0m] Created slic<30>[ 19.666933] systemd[1]: Created slice system-modprobe.slice.
10721 23:12:10.871785 e [0;1;39msystem-modprobe.slice[0m.
10722 23:12:10.892983 [[0;32m OK [0m] Created slic<30>[ 19.690811] systemd[1]: Created slice system-serial\x2dgetty.slice.
10723 23:12:10.898859 e [0;1;39msystem-serial\x2dgetty.slice[0m.
10724 23:12:10.917502 [[0;32m OK [0m] Created slic<30>[ 19.715415] systemd[1]: Created slice User and Session Slice.
10725 23:12:10.920548 e [0;1;39mUser and Session Slice[0m.
10726 23:12:10.943910 [[0;32m OK [0m] Started [0;<30>[ 19.738464] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10727 23:12:10.946725 1;39mDispatch Password …ts to Console Directory Watch[0m.
10728 23:12:10.971352 [[0;32m OK [0m] Started [0;1;39mForward Pas<30>[ 19.766372] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10729 23:12:10.974725 sword R…uests to Wall Directory Watch[0m.
10730 23:12:11.003227 [[0;32m OK [0m] Reached targ<30>[ 19.794174] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10731 23:12:11.009704 et [0;1;39mLoca<30>[ 19.794450] systemd[1]: Reached target Local Encrypted Volumes.
10732 23:12:11.012495 l Encrypted Volumes[0m.
10733 23:12:11.032021 [[0;32m OK [0m] Reached target [0;1;39mPath<30>[ 19.830160] systemd[1]: Reached target Paths.
10734 23:12:11.032106 s[0m.
10735 23:12:11.054181 [[0;32m OK [0m] Reached target [0;1;39mRemo<30>[ 19.849611] systemd[1]: Reached target Remote File Systems.
10736 23:12:11.054298 te File Systems[0m.
10737 23:12:11.076015 [[0;32m OK [0m] Reached target [0;1;39mSlic<30>[ 19.874027] systemd[1]: Reached target Slices.
10738 23:12:11.076103 es[0m.
10739 23:12:11.095259 [[0;32m OK [0m] Reached target [0;1;39mSwap<30>[ 19.893631] systemd[1]: Reached target Swap.
10740 23:12:11.095369 [0m.
10741 23:12:11.119156 [[0;32m OK [0m] Listening on [0;1;39minitct<30>[ 19.914086] systemd[1]: Listening on initctl Compatibility Named Pipe.
10742 23:12:11.122215 l Compatibility Named Pipe[0m.
10743 23:12:11.132446 [[0;32m OK [0m] Listening on [0;1;39mJourna<30>[ 19.930247] systemd[1]: Listening on Journal Audit Socket.
10744 23:12:11.135745 l Audit Socket[0m.
10745 23:12:11.156319 [[0;32m OK [0m] Listening on<30>[ 19.954875] systemd[1]: Listening on Journal Socket (/dev/log).
10746 23:12:11.159465 [0;1;39mJournal Socket (/dev/log)[0m.
10747 23:12:11.180383 [[0;32m OK [0m] Listening on<30>[ 19.978780] systemd[1]: Listening on Journal Socket.
10748 23:12:11.184271 [0;1;39mJournal Socket[0m.
10749 23:12:11.201035 [[0;32m OK [0m] Listening on<30>[ 19.999430] systemd[1]: Listening on Network Service Netlink Socket.
10750 23:12:11.207487 [0;1;39mNetwork Service Netlink Socket[0m.
10751 23:12:11.226263 [[0;32m OK [<30>[ 20.024529] systemd[1]: Listening on udev Control Socket.
10752 23:12:11.229439 0m] Listening on [0;1;39mudev Control Socket[0m.
10753 23:12:11.248812 [[0;32m OK [0m] Listening on<30>[ 20.046708] systemd[1]: Listening on udev Kernel Socket.
10754 23:12:11.251867 [0;1;39mudev Kernel Socket[0m.
10755 23:12:11.307112 Mounting [0;1;39mHuge Pages File Syste<30>[ 20.102051] systemd[1]: Mounting Huge Pages File System...
10756 23:12:11.307223 m[0m...
10757 23:12:11.326151 Mounting [0;1;39mPOSIX<30>[ 20.123811] systemd[1]: Mounting POSIX Message Queue File System...
10758 23:12:11.328921 Message Queue File System[0m...
10759 23:12:11.350724 Mountin<30>[ 20.148800] systemd[1]: Mounting Kernel Debug File System...
10760 23:12:11.353814 g [0;1;39mKernel Debug File System[0m...
10761 23:12:11.375239 <30>[ 20.170140] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10762 23:12:11.407519 Starting [0;1;39mCreat<30>[ 20.202542] systemd[1]: Starting Create list of static device nodes for the current kernel...
10763 23:12:11.410655 e list of st…odes for the current kernel[0m...
10764 23:12:11.436714 Starting [0;1;39mLoad <30>[ 20.234819] systemd[1]: Starting Load Kernel Module configfs...
10765 23:12:11.440231 Kernel Module configfs[0m...
10766 23:12:11.467506 Starting [0;1;39mLoad Kernel Module dr<30>[ 20.262226] systemd[1]: Starting Load Kernel Module drm...
10767 23:12:11.467596 m[0m...
10768 23:12:11.493068 Starting [0;1;39mLoad <30>[ 20.290643] systemd[1]: Starting Load Kernel Module fuse...
10769 23:12:11.495555 Kernel Module fuse[0m...
10770 23:12:11.531355 <6>[ 20.329615] fuse: init (API version 7.37)
10771 23:12:11.541825 <30>[ 20.331310] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10772 23:12:11.576563 Starting [0;1;39mJourn<30>[ 20.374522] systemd[1]: Starting Journal Service...
10773 23:12:11.576655 al Service[0m...
10774 23:12:11.606298 Startin<30>[ 20.404353] systemd[1]: Starting Load Kernel Modules...
10775 23:12:11.609092 g [0;1;39mLoad Kernel Modules[0m...
10776 23:12:11.632785 Starting [0;1;39mRemou<30>[ 20.430740] systemd[1]: Starting Remount Root and Kernel File Systems...
10777 23:12:11.638883 nt Root and Kernel File Systems[0m...
10778 23:12:11.656047 <30>[ 20.457159] systemd[1]: Starting Coldplug All udev Devices...
10779 23:12:11.662446 Starting [0;1;39mColdplug All udev Devices[0m...
10780 23:12:11.691600 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages <30>[ 20.489575] systemd[1]: Mounted Huge Pages File System.
10781 23:12:11.694677 File System[0m.
10782 23:12:11.714997 <3>[ 20.509930] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10783 23:12:11.725057 [[0;32m OK [<30>[ 20.523372] systemd[1]: Mounted POSIX Message Queue File System.
10784 23:12:11.728384 0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10785 23:12:11.747641 [[0;32m OK [0m] Mounted [0;1;39mKernel Debu<30>[ 20.546014] systemd[1]: Mounted Kernel Debug File System.
10786 23:12:11.761062 g File System[0<3>[ 20.546726] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10787 23:12:11.761172 m.
10788 23:12:11.788256 [[0;32m OK [0m] Finished [0<30>[ 20.582706] systemd[1]: Finished Create list of static device nodes for the current kernel.
10789 23:12:11.798420 ;1;39mCreate lis<3>[ 20.591168] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10790 23:12:11.801297 t of st… nodes for the current kernel[0m.
10791 23:12:11.828597 [[0;32m OK [<3>[ 20.622026] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10792 23:12:11.832361 <30>[ 20.622844] systemd[1]: modprobe@configfs.service: Succeeded.
10793 23:12:11.842030 0m] Finished [0<30>[ 20.623900] systemd[1]: Finished Load Kernel Module configfs.
10794 23:12:11.845717 ;1;39mLoad Kernel Module configfs[0m.
10795 23:12:11.872948 [[0;32m OK [<3>[ 20.666033] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10796 23:12:11.876140 <30>[ 20.666942] systemd[1]: modprobe@drm.service: Succeeded.
10797 23:12:11.882829 0m] Finished [0<30>[ 20.667911] systemd[1]: Finished Load Kernel Module drm.
10798 23:12:11.885961 ;1;39mLoad Kernel Module drm[0m.
10799 23:12:11.910676 <3>[ 20.707696] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10800 23:12:11.917702 <30>[ 20.711074] systemd[1]: modprobe@fuse.service: Succeeded.
10801 23:12:11.924791 [[0;32m OK [0m] Finished [0<30>[ 20.712064] systemd[1]: Finished Load Kernel Module fuse.
10802 23:12:11.928404 ;1;39mLoad Kernel Module fuse[0m.
10803 23:12:11.939138 <3>[ 20.734236] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10804 23:12:11.952006 [[0;32m OK [0m] Finished [0<30>[ 20.750725] systemd[1]: Finished Load Kernel Modules.
10805 23:12:11.955872 ;1;39mLoad Kernel Modules[0m.
10806 23:12:11.971121 <3>[ 20.767865] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10807 23:12:11.981869 [[0;32m OK [0m] Finished [0<30>[ 20.779906] systemd[1]: Finished Remount Root and Kernel File Systems.
10808 23:12:11.988680 ;1;39mRemount Root and Kernel File Systems[0m.
10809 23:12:11.995320 <3>[ 20.792947] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10810 23:12:11.995470
10811 23:12:12.022800 <3>[ 20.817980] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10812 23:12:12.043928 Mounting [0;1;39mFUSE Control File Sys<30>[ 20.841321] systemd[1]: Mounting FUSE Control File System...
10813 23:12:12.046916 tem[0m...
10814 23:12:12.070846 Mountin<30>[ 20.868324] systemd[1]: Mounting Kernel Configuration File System...
10815 23:12:12.074544 g [0;1;39mKernel Configuration File System[0m...
10816 23:12:12.099385 <30>[ 20.893798] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10817 23:12:12.109339 <30>[ 20.894102] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10818 23:12:12.115323 Startin<30>[ 20.898046] systemd[1]: Starting Load/Save Random Seed...
10819 23:12:12.119298 g [0;1;39mLoad/Save Random Seed[0m...
10820 23:12:12.143485 <30>[ 20.945074] systemd[1]: Starting Apply Kernel Variables...
10821 23:12:12.150015 Starting [0;1;39mApply Kernel Variables[0m...
10822 23:12:12.176388 Starting [0;1;39mCreat<30>[ 20.973827] systemd[1]: Starting Create System Users...
10823 23:12:12.179510 e System Users[0m...
10824 23:12:12.196952 [[0;32m OK [0m] Started [0;<30>[ 20.995691] systemd[1]: Started Journal Service.
10825 23:12:12.200231 1;39mJournal Service[0m.
10826 23:12:12.221847 <4>[ 21.012416] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10827 23:12:12.228967 <3>[ 21.012430] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10828 23:12:12.235113 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10829 23:12:12.262186 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10830 23:12:12.280231 See 'systemctl status systemd-udev-trigger.service' for details.
10831 23:12:12.297014 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10832 23:12:12.313436 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10833 23:12:12.329562 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10834 23:12:12.349775 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10835 23:12:12.401486 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10836 23:12:12.418689 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10837 23:12:12.467115 <46>[ 21.261796] systemd-journald[312]: Received client request to flush runtime journal.
10838 23:12:13.033822 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10839 23:12:13.048828 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10840 23:12:13.063639 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10841 23:12:13.112287 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10842 23:12:13.854977 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10843 23:12:13.892110 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10844 23:12:13.948723 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10845 23:12:14.003200 Starting [0;1;39mNetwork Service[0m...
10846 23:12:14.277411 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10847 23:12:14.302280 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10848 23:12:14.351129 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10849 23:12:14.686269 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10850 23:12:14.703308 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10851 23:12:14.752147 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10852 23:12:14.777410 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10853 23:12:14.796042 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10854 23:12:14.816739 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10855 23:12:14.845979 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10856 23:12:14.932636 Starting [0;1;39mNetwork Name Resolution[0m...
10857 23:12:14.959786 Starting [0;1;39mNetwork Time Synchronization[0m...
10858 23:12:14.979338 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10859 23:12:15.021582 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10860 23:12:15.173103 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10861 23:12:15.188425 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10862 23:12:15.206804 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10863 23:12:15.219672 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10864 23:12:15.238606 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10865 23:12:15.279015 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10866 23:12:15.355749 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10867 23:12:15.399537 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10868 23:12:15.446698 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10869 23:12:15.459621 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10870 23:12:15.486735 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10871 23:12:15.499410 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10872 23:12:15.515296 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10873 23:12:15.568281 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10874 23:12:16.280482 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
10875 23:12:16.684081 Starting [0;1;39mUser Login Management[0m...
10876 23:12:16.746064 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10877 23:12:16.763650 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10878 23:12:16.786727 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10879 23:12:16.844444 Starting [0;1;39mPermit User Sessions[0m...
10880 23:12:16.997120 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10881 23:12:17.020516 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
10882 23:12:17.076426 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10883 23:12:17.097544 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10884 23:12:17.115965 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10885 23:12:17.132993 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10886 23:12:17.142503 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10887 23:12:17.161448 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10888 23:12:17.226484 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10889 23:12:17.273266 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10890 23:12:17.354978
10891 23:12:17.355576
10892 23:12:17.358511 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10893 23:12:17.359135
10894 23:12:17.361340 debian-bullseye-arm64 login: root (automatic login)
10895 23:12:17.361753
10896 23:12:17.362077
10897 23:12:17.780152 Linux debian-bullseye-arm64 6.1.67-cip12-rt7 #1 SMP PREEMPT Wed Dec 27 22:50:56 UTC 2023 aarch64
10898 23:12:17.780656
10899 23:12:17.787293 The programs included with the Debian GNU/Linux system are free software;
10900 23:12:17.793275 the exact distribution terms for each program are described in the
10901 23:12:17.797009 individual files in /usr/share/doc/*/copyright.
10902 23:12:17.797525
10903 23:12:17.803323 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10904 23:12:17.806410 permitted by applicable law.
10905 23:12:18.923168 Matched prompt #10: / #
10907 23:12:18.924339 Setting prompt string to ['/ #']
10908 23:12:18.924776 end: 2.2.5.1 login-action (duration 00:00:28) [common]
10910 23:12:18.925766 end: 2.2.5 auto-login-action (duration 00:00:29) [common]
10911 23:12:18.926193 start: 2.2.6 expect-shell-connection (timeout 00:03:16) [common]
10912 23:12:18.926541 Setting prompt string to ['/ #']
10913 23:12:18.926852 Forcing a shell prompt, looking for ['/ #']
10915 23:12:18.977661 / #
10916 23:12:18.978219 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10917 23:12:18.978611 Waiting using forced prompt support (timeout 00:02:30)
10918 23:12:18.983567
10919 23:12:18.984416 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10920 23:12:18.984971 start: 2.2.7 export-device-env (timeout 00:03:16) [common]
10922 23:12:19.085920 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12395392/extract-nfsrootfs-_9e2sa3_'
10923 23:12:19.092257 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12395392/extract-nfsrootfs-_9e2sa3_'
10925 23:12:19.193219 / # export NFS_SERVER_IP='192.168.201.1'
10926 23:12:19.198630 export NFS_SERVER_IP='192.168.201.1'
10927 23:12:19.199241 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10928 23:12:19.199648 end: 2.2 depthcharge-retry (duration 00:01:44) [common]
10929 23:12:19.200016 end: 2 depthcharge-action (duration 00:01:44) [common]
10930 23:12:19.200285 start: 3 lava-test-retry (timeout 00:07:33) [common]
10931 23:12:19.200628 start: 3.1 lava-test-shell (timeout 00:07:33) [common]
10932 23:12:19.200950 Using namespace: common
10934 23:12:19.301774 / # #
10935 23:12:19.302376 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
10936 23:12:19.308296 #
10937 23:12:19.309052 Using /lava-12395392
10939 23:12:19.410031 / # export SHELL=/bin/bash
10940 23:12:19.416281 export SHELL=/bin/bash
10942 23:12:19.517623 / # . /lava-12395392/environment
10943 23:12:19.523075 . /lava-12395392/environment
10945 23:12:19.629667 / # /lava-12395392/bin/lava-test-runner /lava-12395392/0
10946 23:12:19.629825 Test shell timeout: 10s (minimum of the action and connection timeout)
10947 23:12:19.634826 /lava-12395392/bin/lava-test-runner /lava-12395392/0
10948 23:12:19.965695 + export TESTRUN_ID=0_timesync-off
10949 23:12:19.968704 + TESTRUN_ID=0_timesync-off
10950 23:12:19.972114 + cd /lava-12395392/0/tests/0_timesync-off
10951 23:12:19.975624 ++ cat uuid
10952 23:12:19.985102 + UUID=12395392_1.6.2.3.1
10953 23:12:19.985520 + set +x
10954 23:12:19.992600 <LAVA_SIGNAL_STARTRUN 0_timesync-off 12395392_1.6.2.3.1>
10955 23:12:19.993340 Received signal: <STARTRUN> 0_timesync-off 12395392_1.6.2.3.1
10956 23:12:19.993732 Starting test lava.0_timesync-off (12395392_1.6.2.3.1)
10957 23:12:19.994202 Skipping test definition patterns.
10958 23:12:19.994881 + systemctl stop systemd-timesyncd
10959 23:12:20.067954 + set +x
10960 23:12:20.070540 <LAVA_SIGNAL_ENDRUN 0_timesync-off 12395392_1.6.2.3.1>
10961 23:12:20.071241 Received signal: <ENDRUN> 0_timesync-off 12395392_1.6.2.3.1
10962 23:12:20.071733 Ending use of test pattern.
10963 23:12:20.072117 Ending test lava.0_timesync-off (12395392_1.6.2.3.1), duration 0.08
10965 23:12:20.174444 + export TESTRUN_ID=1_kselftest-dt
10966 23:12:20.177726 + TESTRUN_ID=1_kselftest-dt
10967 23:12:20.181327 + cd /lava-12395392/0/tests/1_kselftest-dt
10968 23:12:20.184290 ++ cat uuid
10969 23:12:20.195682 + UUID=12395392_1.6.2.3.5
10970 23:12:20.196167 + set +x
10971 23:12:20.201660 <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 12395392_1.6.2.3.5>
10972 23:12:20.202379 Received signal: <STARTRUN> 1_kselftest-dt 12395392_1.6.2.3.5
10973 23:12:20.202798 Starting test lava.1_kselftest-dt (12395392_1.6.2.3.5)
10974 23:12:20.203190 Skipping test definition patterns.
10975 23:12:20.205208 + cd ./automated/linux/kselftest/
10976 23:12:20.231183 + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.66-cip11-rt6-10-g38253b8903b4/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip-gitlab -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
10977 23:12:20.293149 INFO: install_deps skipped
10978 23:12:20.437768 --2023-12-27 23:12:20-- http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.66-cip11-rt6-10-g38253b8903b4/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
10979 23:12:20.444598 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
10980 23:12:20.576577 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
10981 23:12:20.706346 HTTP request sent, awaiting response... 200 OK
10982 23:12:20.709235 Length: 2966456 (2.8M) [application/octet-stream]
10983 23:12:20.712789 Saving to: 'kselftest.tar.xz'
10984 23:12:20.712904
10985 23:12:20.712995
10986 23:12:20.964623 kselftest.tar.xz 0%[ ] 0 --.-KB/s
10987 23:12:21.222838 kselftest.tar.xz 1%[ ] 47.81K 186KB/s
10988 23:12:21.481378 kselftest.tar.xz 7%[> ] 217.50K 422KB/s
10989 23:12:21.742146 kselftest.tar.xz 30%[=====> ] 896.25K 1.13MB/s
10990 23:12:22.055867 kselftest.tar.xz 55%[==========> ] 1.58M 1.53MB/s
10991 23:12:22.062353 kselftest.tar.xz 99%[==================> ] 2.82M 2.09MB/s
10992 23:12:22.068800 kselftest.tar.xz 100%[===================>] 2.83M 2.10MB/s in 1.3s
10993 23:12:22.069216
10994 23:12:22.320762 2023-12-27 23:12:22 (2.10 MB/s) - 'kselftest.tar.xz' saved [2966456/2966456]
10995 23:12:22.320921
10996 23:12:29.947648 skiplist:
10997 23:12:29.951278 ========================================
10998 23:12:29.954742 ========================================
10999 23:12:30.040809 ============== Tests to run ===============
11000 23:12:30.048621 ===========End Tests to run ===============
11001 23:12:30.054374 shardfile-dt fail
11002 23:12:30.085392 ./kselftest.sh: 131: cannot open /lava-12395392/0/tests/1_kselftest-dt/automated/linux/kselftest/output/kselftest.txt: No such file
11003 23:12:30.088075 + ../../utils/send-to-lava.sh ./output/result.txt
11004 23:12:30.194449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=fail>
11005 23:12:30.194958 + set +x
11006 23:12:30.195570 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=fail
11008 23:12:30.201943 <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 12395392_1.6.2.3.5>
11009 23:12:30.202738 Received signal: <ENDRUN> 1_kselftest-dt 12395392_1.6.2.3.5
11010 23:12:30.203107 Ending use of test pattern.
11011 23:12:30.203453 Ending test lava.1_kselftest-dt (12395392_1.6.2.3.5), duration 10.00
11013 23:12:30.204588 ok: lava_test_shell seems to have completed
11014 23:12:30.205042 shardfile-dt: fail
11015 23:12:30.205451 end: 3.1 lava-test-shell (duration 00:00:11) [common]
11016 23:12:30.205849 end: 3 lava-test-retry (duration 00:00:11) [common]
11017 23:12:30.206282 start: 4 finalize (timeout 00:07:22) [common]
11018 23:12:30.206730 start: 4.1 power-off (timeout 00:00:30) [common]
11019 23:12:30.207562 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-2' '--port=1' '--command=off'
11020 23:12:30.332629 >> Command sent successfully.
11021 23:12:30.343615 Returned 0 in 0 seconds
11022 23:12:30.444902 end: 4.1 power-off (duration 00:00:00) [common]
11024 23:12:30.446337 start: 4.2 read-feedback (timeout 00:07:22) [common]
11026 23:12:30.448720 Listened to connection for namespace 'common' for up to 1s
11027 23:12:31.447676 Finalising connection for namespace 'common'
11028 23:12:31.448438 Disconnecting from shell: Finalise
11029 23:12:31.448833 / #
11030 23:12:31.549863 end: 4.2 read-feedback (duration 00:00:01) [common]
11031 23:12:31.550647 end: 4 finalize (duration 00:00:01) [common]
11032 23:12:31.551409 Cleaning after the job
11033 23:12:31.551967 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12395392/tftp-deploy-l3kfndy0/ramdisk
11034 23:12:31.565301 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12395392/tftp-deploy-l3kfndy0/kernel
11035 23:12:31.596199 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12395392/tftp-deploy-l3kfndy0/dtb
11036 23:12:31.596472 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12395392/tftp-deploy-l3kfndy0/nfsrootfs
11037 23:12:31.690329 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12395392/tftp-deploy-l3kfndy0/modules
11038 23:12:31.697736 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12395392
11039 23:12:32.328777 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12395392
11040 23:12:32.328960 Job finished correctly