Boot log: mt8192-asurada-spherion-r0
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 14
- Kernel Errors: 33
- Errors: 0
1 23:13:37.540855 lava-dispatcher, installed at version: 2023.10
2 23:13:37.541075 start: 0 validate
3 23:13:37.541206 Start time: 2023-12-27 23:13:37.541196+00:00 (UTC)
4 23:13:37.541324 Using caching service: 'http://localhost/cache/?uri=%s'
5 23:13:37.541452 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230623.0%2Farm64%2Finitrd.cpio.gz exists
6 23:13:37.796700 Using caching service: 'http://localhost/cache/?uri=%s'
7 23:13:37.796870 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.66-cip11-rt6-10-g38253b8903b4%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 23:13:38.045167 Using caching service: 'http://localhost/cache/?uri=%s'
9 23:13:38.045333 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.66-cip11-rt6-10-g38253b8903b4%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 23:13:38.310362 Using caching service: 'http://localhost/cache/?uri=%s'
11 23:13:38.310539 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230623.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 23:13:38.576389 Using caching service: 'http://localhost/cache/?uri=%s'
13 23:13:38.576569 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.66-cip11-rt6-10-g38253b8903b4%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 23:13:38.835256 validate duration: 1.29
16 23:13:38.835518 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 23:13:38.835617 start: 1.1 download-retry (timeout 00:10:00) [common]
18 23:13:38.835708 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 23:13:38.835832 Not decompressing ramdisk as can be used compressed.
20 23:13:38.835917 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230623.0/arm64/initrd.cpio.gz
21 23:13:38.835984 saving as /var/lib/lava/dispatcher/tmp/12395397/tftp-deploy-lurrlnu3/ramdisk/initrd.cpio.gz
22 23:13:38.836049 total size: 4665395 (4 MB)
23 23:13:38.837172 progress 0 % (0 MB)
24 23:13:38.838723 progress 5 % (0 MB)
25 23:13:38.840185 progress 10 % (0 MB)
26 23:13:38.841517 progress 15 % (0 MB)
27 23:13:38.842845 progress 20 % (0 MB)
28 23:13:38.844090 progress 25 % (1 MB)
29 23:13:38.845387 progress 30 % (1 MB)
30 23:13:38.846660 progress 35 % (1 MB)
31 23:13:38.847895 progress 40 % (1 MB)
32 23:13:38.849336 progress 45 % (2 MB)
33 23:13:38.850664 progress 50 % (2 MB)
34 23:13:38.851910 progress 55 % (2 MB)
35 23:13:38.853163 progress 60 % (2 MB)
36 23:13:38.854389 progress 65 % (2 MB)
37 23:13:38.855614 progress 70 % (3 MB)
38 23:13:38.856851 progress 75 % (3 MB)
39 23:13:38.858182 progress 80 % (3 MB)
40 23:13:38.859608 progress 85 % (3 MB)
41 23:13:38.860865 progress 90 % (4 MB)
42 23:13:38.862098 progress 95 % (4 MB)
43 23:13:38.863346 progress 100 % (4 MB)
44 23:13:38.863498 4 MB downloaded in 0.03 s (162.09 MB/s)
45 23:13:38.863653 end: 1.1.1 http-download (duration 00:00:00) [common]
47 23:13:38.863892 end: 1.1 download-retry (duration 00:00:00) [common]
48 23:13:38.863979 start: 1.2 download-retry (timeout 00:10:00) [common]
49 23:13:38.864063 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 23:13:38.864190 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.66-cip11-rt6-10-g38253b8903b4/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 23:13:38.864259 saving as /var/lib/lava/dispatcher/tmp/12395397/tftp-deploy-lurrlnu3/kernel/Image
52 23:13:38.864383 total size: 50024960 (47 MB)
53 23:13:38.864473 No compression specified
54 23:13:38.865650 progress 0 % (0 MB)
55 23:13:38.878984 progress 5 % (2 MB)
56 23:13:38.892156 progress 10 % (4 MB)
57 23:13:38.905310 progress 15 % (7 MB)
58 23:13:38.918520 progress 20 % (9 MB)
59 23:13:38.931481 progress 25 % (11 MB)
60 23:13:38.944863 progress 30 % (14 MB)
61 23:13:38.958202 progress 35 % (16 MB)
62 23:13:38.971382 progress 40 % (19 MB)
63 23:13:38.984297 progress 45 % (21 MB)
64 23:13:38.997450 progress 50 % (23 MB)
65 23:13:39.010335 progress 55 % (26 MB)
66 23:13:39.023180 progress 60 % (28 MB)
67 23:13:39.036170 progress 65 % (31 MB)
68 23:13:39.049335 progress 70 % (33 MB)
69 23:13:39.062523 progress 75 % (35 MB)
70 23:13:39.075697 progress 80 % (38 MB)
71 23:13:39.088742 progress 85 % (40 MB)
72 23:13:39.101775 progress 90 % (42 MB)
73 23:13:39.114731 progress 95 % (45 MB)
74 23:13:39.127330 progress 100 % (47 MB)
75 23:13:39.127607 47 MB downloaded in 0.26 s (181.25 MB/s)
76 23:13:39.127769 end: 1.2.1 http-download (duration 00:00:00) [common]
78 23:13:39.128007 end: 1.2 download-retry (duration 00:00:00) [common]
79 23:13:39.128095 start: 1.3 download-retry (timeout 00:10:00) [common]
80 23:13:39.128185 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 23:13:39.128333 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.66-cip11-rt6-10-g38253b8903b4/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 23:13:39.128403 saving as /var/lib/lava/dispatcher/tmp/12395397/tftp-deploy-lurrlnu3/dtb/mt8192-asurada-spherion-r0.dtb
83 23:13:39.128465 total size: 47278 (0 MB)
84 23:13:39.128527 No compression specified
85 23:13:39.129689 progress 69 % (0 MB)
86 23:13:39.130013 progress 100 % (0 MB)
87 23:13:39.130205 0 MB downloaded in 0.00 s (25.96 MB/s)
88 23:13:39.130370 end: 1.3.1 http-download (duration 00:00:00) [common]
90 23:13:39.130652 end: 1.3 download-retry (duration 00:00:00) [common]
91 23:13:39.130772 start: 1.4 download-retry (timeout 00:10:00) [common]
92 23:13:39.130887 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 23:13:39.131050 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230623.0/arm64/full.rootfs.tar.xz
94 23:13:39.131119 saving as /var/lib/lava/dispatcher/tmp/12395397/tftp-deploy-lurrlnu3/nfsrootfs/full.rootfs.tar
95 23:13:39.131182 total size: 200813988 (191 MB)
96 23:13:39.131245 Using unxz to decompress xz
97 23:13:39.135806 progress 0 % (0 MB)
98 23:13:39.708835 progress 5 % (9 MB)
99 23:13:40.222240 progress 10 % (19 MB)
100 23:13:40.808494 progress 15 % (28 MB)
101 23:13:41.185844 progress 20 % (38 MB)
102 23:13:41.514883 progress 25 % (47 MB)
103 23:13:42.113216 progress 30 % (57 MB)
104 23:13:42.667700 progress 35 % (67 MB)
105 23:13:43.286791 progress 40 % (76 MB)
106 23:13:43.846909 progress 45 % (86 MB)
107 23:13:44.431295 progress 50 % (95 MB)
108 23:13:45.104893 progress 55 % (105 MB)
109 23:13:45.770637 progress 60 % (114 MB)
110 23:13:45.890496 progress 65 % (124 MB)
111 23:13:46.035686 progress 70 % (134 MB)
112 23:13:46.145461 progress 75 % (143 MB)
113 23:13:46.225549 progress 80 % (153 MB)
114 23:13:46.299196 progress 85 % (162 MB)
115 23:13:46.416132 progress 90 % (172 MB)
116 23:13:46.707473 progress 95 % (181 MB)
117 23:13:47.281516 progress 100 % (191 MB)
118 23:13:47.286743 191 MB downloaded in 8.16 s (23.48 MB/s)
119 23:13:47.287109 end: 1.4.1 http-download (duration 00:00:08) [common]
121 23:13:47.287571 end: 1.4 download-retry (duration 00:00:08) [common]
122 23:13:47.287717 start: 1.5 download-retry (timeout 00:09:52) [common]
123 23:13:47.287864 start: 1.5.1 http-download (timeout 00:09:52) [common]
124 23:13:47.288096 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.66-cip11-rt6-10-g38253b8903b4/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 23:13:47.288214 saving as /var/lib/lava/dispatcher/tmp/12395397/tftp-deploy-lurrlnu3/modules/modules.tar
126 23:13:47.288370 total size: 8633892 (8 MB)
127 23:13:47.288486 Using unxz to decompress xz
128 23:13:47.294282 progress 0 % (0 MB)
129 23:13:47.315440 progress 5 % (0 MB)
130 23:13:47.338738 progress 10 % (0 MB)
131 23:13:47.365965 progress 15 % (1 MB)
132 23:13:47.389285 progress 20 % (1 MB)
133 23:13:47.413147 progress 25 % (2 MB)
134 23:13:47.440244 progress 30 % (2 MB)
135 23:13:47.464668 progress 35 % (2 MB)
136 23:13:47.487884 progress 40 % (3 MB)
137 23:13:47.511968 progress 45 % (3 MB)
138 23:13:47.536865 progress 50 % (4 MB)
139 23:13:47.561084 progress 55 % (4 MB)
140 23:13:47.587767 progress 60 % (4 MB)
141 23:13:47.614540 progress 65 % (5 MB)
142 23:13:47.640849 progress 70 % (5 MB)
143 23:13:47.664121 progress 75 % (6 MB)
144 23:13:47.691276 progress 80 % (6 MB)
145 23:13:47.716957 progress 85 % (7 MB)
146 23:13:47.743539 progress 90 % (7 MB)
147 23:13:47.773426 progress 95 % (7 MB)
148 23:13:47.801150 progress 100 % (8 MB)
149 23:13:47.806622 8 MB downloaded in 0.52 s (15.89 MB/s)
150 23:13:47.806970 end: 1.5.1 http-download (duration 00:00:01) [common]
152 23:13:47.807433 end: 1.5 download-retry (duration 00:00:01) [common]
153 23:13:47.807590 start: 1.6 prepare-tftp-overlay (timeout 00:09:51) [common]
154 23:13:47.807749 start: 1.6.1 extract-nfsrootfs (timeout 00:09:51) [common]
155 23:13:51.449107 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/12395397/extract-nfsrootfs-h3gcb2cr
156 23:13:51.449308 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 23:13:51.449417 start: 1.6.2 lava-overlay (timeout 00:09:47) [common]
158 23:13:51.449588 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12395397/lava-overlay-lb2q2qkp
159 23:13:51.449721 makedir: /var/lib/lava/dispatcher/tmp/12395397/lava-overlay-lb2q2qkp/lava-12395397/bin
160 23:13:51.449825 makedir: /var/lib/lava/dispatcher/tmp/12395397/lava-overlay-lb2q2qkp/lava-12395397/tests
161 23:13:51.449926 makedir: /var/lib/lava/dispatcher/tmp/12395397/lava-overlay-lb2q2qkp/lava-12395397/results
162 23:13:51.450029 Creating /var/lib/lava/dispatcher/tmp/12395397/lava-overlay-lb2q2qkp/lava-12395397/bin/lava-add-keys
163 23:13:51.450177 Creating /var/lib/lava/dispatcher/tmp/12395397/lava-overlay-lb2q2qkp/lava-12395397/bin/lava-add-sources
164 23:13:51.450311 Creating /var/lib/lava/dispatcher/tmp/12395397/lava-overlay-lb2q2qkp/lava-12395397/bin/lava-background-process-start
165 23:13:51.450441 Creating /var/lib/lava/dispatcher/tmp/12395397/lava-overlay-lb2q2qkp/lava-12395397/bin/lava-background-process-stop
166 23:13:51.450571 Creating /var/lib/lava/dispatcher/tmp/12395397/lava-overlay-lb2q2qkp/lava-12395397/bin/lava-common-functions
167 23:13:51.450699 Creating /var/lib/lava/dispatcher/tmp/12395397/lava-overlay-lb2q2qkp/lava-12395397/bin/lava-echo-ipv4
168 23:13:51.450827 Creating /var/lib/lava/dispatcher/tmp/12395397/lava-overlay-lb2q2qkp/lava-12395397/bin/lava-install-packages
169 23:13:51.450954 Creating /var/lib/lava/dispatcher/tmp/12395397/lava-overlay-lb2q2qkp/lava-12395397/bin/lava-installed-packages
170 23:13:51.451079 Creating /var/lib/lava/dispatcher/tmp/12395397/lava-overlay-lb2q2qkp/lava-12395397/bin/lava-os-build
171 23:13:51.451207 Creating /var/lib/lava/dispatcher/tmp/12395397/lava-overlay-lb2q2qkp/lava-12395397/bin/lava-probe-channel
172 23:13:51.451334 Creating /var/lib/lava/dispatcher/tmp/12395397/lava-overlay-lb2q2qkp/lava-12395397/bin/lava-probe-ip
173 23:13:51.451460 Creating /var/lib/lava/dispatcher/tmp/12395397/lava-overlay-lb2q2qkp/lava-12395397/bin/lava-target-ip
174 23:13:51.451586 Creating /var/lib/lava/dispatcher/tmp/12395397/lava-overlay-lb2q2qkp/lava-12395397/bin/lava-target-mac
175 23:13:51.451711 Creating /var/lib/lava/dispatcher/tmp/12395397/lava-overlay-lb2q2qkp/lava-12395397/bin/lava-target-storage
176 23:13:51.451840 Creating /var/lib/lava/dispatcher/tmp/12395397/lava-overlay-lb2q2qkp/lava-12395397/bin/lava-test-case
177 23:13:51.451969 Creating /var/lib/lava/dispatcher/tmp/12395397/lava-overlay-lb2q2qkp/lava-12395397/bin/lava-test-event
178 23:13:51.452095 Creating /var/lib/lava/dispatcher/tmp/12395397/lava-overlay-lb2q2qkp/lava-12395397/bin/lava-test-feedback
179 23:13:51.452221 Creating /var/lib/lava/dispatcher/tmp/12395397/lava-overlay-lb2q2qkp/lava-12395397/bin/lava-test-raise
180 23:13:51.452384 Creating /var/lib/lava/dispatcher/tmp/12395397/lava-overlay-lb2q2qkp/lava-12395397/bin/lava-test-reference
181 23:13:51.452513 Creating /var/lib/lava/dispatcher/tmp/12395397/lava-overlay-lb2q2qkp/lava-12395397/bin/lava-test-runner
182 23:13:51.452640 Creating /var/lib/lava/dispatcher/tmp/12395397/lava-overlay-lb2q2qkp/lava-12395397/bin/lava-test-set
183 23:13:51.452768 Creating /var/lib/lava/dispatcher/tmp/12395397/lava-overlay-lb2q2qkp/lava-12395397/bin/lava-test-shell
184 23:13:51.452898 Updating /var/lib/lava/dispatcher/tmp/12395397/lava-overlay-lb2q2qkp/lava-12395397/bin/lava-add-keys (debian)
185 23:13:51.453053 Updating /var/lib/lava/dispatcher/tmp/12395397/lava-overlay-lb2q2qkp/lava-12395397/bin/lava-add-sources (debian)
186 23:13:51.453197 Updating /var/lib/lava/dispatcher/tmp/12395397/lava-overlay-lb2q2qkp/lava-12395397/bin/lava-install-packages (debian)
187 23:13:51.453338 Updating /var/lib/lava/dispatcher/tmp/12395397/lava-overlay-lb2q2qkp/lava-12395397/bin/lava-installed-packages (debian)
188 23:13:51.453479 Updating /var/lib/lava/dispatcher/tmp/12395397/lava-overlay-lb2q2qkp/lava-12395397/bin/lava-os-build (debian)
189 23:13:51.453603 Creating /var/lib/lava/dispatcher/tmp/12395397/lava-overlay-lb2q2qkp/lava-12395397/environment
190 23:13:51.453700 LAVA metadata
191 23:13:51.453769 - LAVA_JOB_ID=12395397
192 23:13:51.453833 - LAVA_DISPATCHER_IP=192.168.201.1
193 23:13:51.453932 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:47) [common]
194 23:13:51.453998 skipped lava-vland-overlay
195 23:13:51.454072 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 23:13:51.454214 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:47) [common]
197 23:13:51.454274 skipped lava-multinode-overlay
198 23:13:51.454347 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 23:13:51.454425 start: 1.6.2.3 test-definition (timeout 00:09:47) [common]
200 23:13:51.454496 Loading test definitions
201 23:13:51.454587 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:47) [common]
202 23:13:51.454660 Using /lava-12395397 at stage 0
203 23:13:51.454946 uuid=12395397_1.6.2.3.1 testdef=None
204 23:13:51.455036 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 23:13:51.455121 start: 1.6.2.3.2 test-overlay (timeout 00:09:47) [common]
206 23:13:51.455578 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 23:13:51.455799 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:47) [common]
209 23:13:51.456476 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 23:13:51.456739 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:47) [common]
212 23:13:51.457300 runner path: /var/lib/lava/dispatcher/tmp/12395397/lava-overlay-lb2q2qkp/lava-12395397/0/tests/0_timesync-off test_uuid 12395397_1.6.2.3.1
213 23:13:51.457458 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 23:13:51.457684 start: 1.6.2.3.5 git-repo-action (timeout 00:09:47) [common]
216 23:13:51.457756 Using /lava-12395397 at stage 0
217 23:13:51.457853 Fetching tests from https://github.com/kernelci/test-definitions.git
218 23:13:51.457931 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/12395397/lava-overlay-lb2q2qkp/lava-12395397/0/tests/1_kselftest-rtc'
219 23:13:54.384951 Running '/usr/bin/git checkout kernelci.org
220 23:13:54.535849 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/12395397/lava-overlay-lb2q2qkp/lava-12395397/0/tests/1_kselftest-rtc/automated/linux/kselftest/kselftest.yaml
221 23:13:54.537062 uuid=12395397_1.6.2.3.5 testdef=None
222 23:13:54.537303 end: 1.6.2.3.5 git-repo-action (duration 00:00:03) [common]
224 23:13:54.537752 start: 1.6.2.3.6 test-overlay (timeout 00:09:44) [common]
225 23:13:54.539120 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 23:13:54.539542 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:44) [common]
228 23:13:54.541389 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 23:13:54.541817 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:44) [common]
231 23:13:54.543532 runner path: /var/lib/lava/dispatcher/tmp/12395397/lava-overlay-lb2q2qkp/lava-12395397/0/tests/1_kselftest-rtc test_uuid 12395397_1.6.2.3.5
232 23:13:54.543654 BOARD='mt8192-asurada-spherion-r0'
233 23:13:54.543747 BRANCH='cip-gitlab'
234 23:13:54.543834 SKIPFILE='/dev/null'
235 23:13:54.543920 SKIP_INSTALL='True'
236 23:13:54.544003 TESTPROG_URL='http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.66-cip11-rt6-10-g38253b8903b4/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 23:13:54.544090 TST_CASENAME=''
238 23:13:54.544173 TST_CMDFILES='rtc'
239 23:13:54.544387 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 23:13:54.544593 Creating lava-test-runner.conf files
242 23:13:54.544658 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12395397/lava-overlay-lb2q2qkp/lava-12395397/0 for stage 0
243 23:13:54.544752 - 0_timesync-off
244 23:13:54.544823 - 1_kselftest-rtc
245 23:13:54.544919 end: 1.6.2.3 test-definition (duration 00:00:03) [common]
246 23:13:54.545008 start: 1.6.2.4 compress-overlay (timeout 00:09:44) [common]
247 23:14:02.125233 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 23:14:02.125394 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:37) [common]
249 23:14:02.125493 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 23:14:02.125594 end: 1.6.2 lava-overlay (duration 00:00:11) [common]
251 23:14:02.125686 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:37) [common]
252 23:14:02.248156 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 23:14:02.248746 start: 1.6.4 extract-modules (timeout 00:09:37) [common]
254 23:14:02.248926 extracting modules file /var/lib/lava/dispatcher/tmp/12395397/tftp-deploy-lurrlnu3/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12395397/extract-nfsrootfs-h3gcb2cr
255 23:14:02.533132 extracting modules file /var/lib/lava/dispatcher/tmp/12395397/tftp-deploy-lurrlnu3/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12395397/extract-overlay-ramdisk-4438dp97/ramdisk
256 23:14:02.759749 end: 1.6.4 extract-modules (duration 00:00:01) [common]
257 23:14:02.759917 start: 1.6.5 apply-overlay-tftp (timeout 00:09:36) [common]
258 23:14:02.760011 [common] Applying overlay to NFS
259 23:14:02.760082 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12395397/compress-overlay-rrd0zv82/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12395397/extract-nfsrootfs-h3gcb2cr
260 23:14:03.693303 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 23:14:03.693471 start: 1.6.6 configure-preseed-file (timeout 00:09:35) [common]
262 23:14:03.693566 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 23:14:03.693655 start: 1.6.7 compress-ramdisk (timeout 00:09:35) [common]
264 23:14:03.693736 Building ramdisk /var/lib/lava/dispatcher/tmp/12395397/extract-overlay-ramdisk-4438dp97/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12395397/extract-overlay-ramdisk-4438dp97/ramdisk
265 23:14:04.026765 >> 119421 blocks
266 23:14:05.982281 rename /var/lib/lava/dispatcher/tmp/12395397/extract-overlay-ramdisk-4438dp97/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12395397/tftp-deploy-lurrlnu3/ramdisk/ramdisk.cpio.gz
267 23:14:05.982781 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 23:14:05.982910 start: 1.6.8 prepare-kernel (timeout 00:09:33) [common]
269 23:14:05.983019 start: 1.6.8.1 prepare-fit (timeout 00:09:33) [common]
270 23:14:05.983124 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12395397/tftp-deploy-lurrlnu3/kernel/Image'
271 23:14:18.421306 Returned 0 in 12 seconds
272 23:14:18.521918 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12395397/tftp-deploy-lurrlnu3/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12395397/tftp-deploy-lurrlnu3/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12395397/tftp-deploy-lurrlnu3/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12395397/tftp-deploy-lurrlnu3/kernel/image.itb
273 23:14:18.890643 output: FIT description: Kernel Image image with one or more FDT blobs
274 23:14:18.891032 output: Created: Wed Dec 27 23:14:18 2023
275 23:14:18.891109 output: Image 0 (kernel-1)
276 23:14:18.891173 output: Description:
277 23:14:18.891237 output: Created: Wed Dec 27 23:14:18 2023
278 23:14:18.891296 output: Type: Kernel Image
279 23:14:18.891356 output: Compression: lzma compressed
280 23:14:18.891414 output: Data Size: 11480388 Bytes = 11211.32 KiB = 10.95 MiB
281 23:14:18.891472 output: Architecture: AArch64
282 23:14:18.891528 output: OS: Linux
283 23:14:18.891585 output: Load Address: 0x00000000
284 23:14:18.891641 output: Entry Point: 0x00000000
285 23:14:18.891698 output: Hash algo: crc32
286 23:14:18.891753 output: Hash value: a55b2f0b
287 23:14:18.891807 output: Image 1 (fdt-1)
288 23:14:18.891860 output: Description: mt8192-asurada-spherion-r0
289 23:14:18.891912 output: Created: Wed Dec 27 23:14:18 2023
290 23:14:18.891965 output: Type: Flat Device Tree
291 23:14:18.892017 output: Compression: uncompressed
292 23:14:18.892069 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
293 23:14:18.892121 output: Architecture: AArch64
294 23:14:18.892173 output: Hash algo: crc32
295 23:14:18.892226 output: Hash value: cc4352de
296 23:14:18.892278 output: Image 2 (ramdisk-1)
297 23:14:18.892339 output: Description: unavailable
298 23:14:18.892390 output: Created: Wed Dec 27 23:14:18 2023
299 23:14:18.892443 output: Type: RAMDisk Image
300 23:14:18.892494 output: Compression: Unknown Compression
301 23:14:18.892546 output: Data Size: 17795936 Bytes = 17378.84 KiB = 16.97 MiB
302 23:14:18.892597 output: Architecture: AArch64
303 23:14:18.892649 output: OS: Linux
304 23:14:18.892700 output: Load Address: unavailable
305 23:14:18.892752 output: Entry Point: unavailable
306 23:14:18.892803 output: Hash algo: crc32
307 23:14:18.892855 output: Hash value: 3b5ce4ac
308 23:14:18.892906 output: Default Configuration: 'conf-1'
309 23:14:18.892958 output: Configuration 0 (conf-1)
310 23:14:18.893010 output: Description: mt8192-asurada-spherion-r0
311 23:14:18.893061 output: Kernel: kernel-1
312 23:14:18.893113 output: Init Ramdisk: ramdisk-1
313 23:14:18.893164 output: FDT: fdt-1
314 23:14:18.893215 output: Loadables: kernel-1
315 23:14:18.893266 output:
316 23:14:18.893473 end: 1.6.8.1 prepare-fit (duration 00:00:13) [common]
317 23:14:18.893577 end: 1.6.8 prepare-kernel (duration 00:00:13) [common]
318 23:14:18.893688 end: 1.6 prepare-tftp-overlay (duration 00:00:31) [common]
319 23:14:18.893782 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:20) [common]
320 23:14:18.893859 No LXC device requested
321 23:14:18.893938 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 23:14:18.894022 start: 1.8 deploy-device-env (timeout 00:09:20) [common]
323 23:14:18.894100 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 23:14:18.894168 Checking files for TFTP limit of 4294967296 bytes.
325 23:14:18.894672 end: 1 tftp-deploy (duration 00:00:40) [common]
326 23:14:18.894777 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 23:14:18.894870 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 23:14:18.895000 substitutions:
329 23:14:18.895068 - {DTB}: 12395397/tftp-deploy-lurrlnu3/dtb/mt8192-asurada-spherion-r0.dtb
330 23:14:18.895131 - {INITRD}: 12395397/tftp-deploy-lurrlnu3/ramdisk/ramdisk.cpio.gz
331 23:14:18.895190 - {KERNEL}: 12395397/tftp-deploy-lurrlnu3/kernel/Image
332 23:14:18.895248 - {LAVA_MAC}: None
333 23:14:18.895305 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/12395397/extract-nfsrootfs-h3gcb2cr
334 23:14:18.895361 - {NFS_SERVER_IP}: 192.168.201.1
335 23:14:18.895416 - {PRESEED_CONFIG}: None
336 23:14:18.895471 - {PRESEED_LOCAL}: None
337 23:14:18.895524 - {RAMDISK}: 12395397/tftp-deploy-lurrlnu3/ramdisk/ramdisk.cpio.gz
338 23:14:18.895577 - {ROOT_PART}: None
339 23:14:18.895631 - {ROOT}: None
340 23:14:18.895684 - {SERVER_IP}: 192.168.201.1
341 23:14:18.895737 - {TEE}: None
342 23:14:18.895789 Parsed boot commands:
343 23:14:18.895841 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 23:14:18.896024 Parsed boot commands: tftpboot 192.168.201.1 12395397/tftp-deploy-lurrlnu3/kernel/image.itb 12395397/tftp-deploy-lurrlnu3/kernel/cmdline
345 23:14:18.896111 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 23:14:18.896195 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 23:14:18.896291 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 23:14:18.896416 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 23:14:18.896488 Not connected, no need to disconnect.
350 23:14:18.896561 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 23:14:18.896641 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 23:14:18.896709 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-0'
353 23:14:18.900846 Setting prompt string to ['lava-test: # ']
354 23:14:18.901221 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 23:14:18.901330 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 23:14:18.901446 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 23:14:18.901564 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 23:14:18.901803 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=reboot'
359 23:14:24.038890 >> Command sent successfully.
360 23:14:24.041385 Returned 0 in 5 seconds
361 23:14:24.141833 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 23:14:24.142325 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 23:14:24.142493 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 23:14:24.142637 Setting prompt string to 'Starting depthcharge on Spherion...'
366 23:14:24.142756 Changing prompt to 'Starting depthcharge on Spherion...'
367 23:14:24.142878 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 23:14:24.143310 [Enter `^Ec?' for help]
369 23:14:24.315294
370 23:14:24.315483
371 23:14:24.315604 F0: 102B 0000
372 23:14:24.315721
373 23:14:24.315832 F3: 1001 0000 [0200]
374 23:14:24.315943
375 23:14:24.318349 F3: 1001 0000
376 23:14:24.318469
377 23:14:24.318584 F7: 102D 0000
378 23:14:24.318695
379 23:14:24.322154 F1: 0000 0000
380 23:14:24.322277
381 23:14:24.322388 V0: 0000 0000 [0001]
382 23:14:24.322502
383 23:14:24.322611 00: 0007 8000
384 23:14:24.322725
385 23:14:24.326140 01: 0000 0000
386 23:14:24.326265
387 23:14:24.326375 BP: 0C00 0209 [0000]
388 23:14:24.326483
389 23:14:24.329450 G0: 1182 0000
390 23:14:24.329568
391 23:14:24.329679 EC: 0000 0021 [4000]
392 23:14:24.329787
393 23:14:24.333602 S7: 0000 0000 [0000]
394 23:14:24.333724
395 23:14:24.333837 CC: 0000 0000 [0001]
396 23:14:24.333946
397 23:14:24.337087 T0: 0000 0040 [010F]
398 23:14:24.337212
399 23:14:24.337322 Jump to BL
400 23:14:24.337427
401 23:14:24.362565
402 23:14:24.362693
403 23:14:24.362803
404 23:14:24.369717 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 23:14:24.373867 ARM64: Exception handlers installed.
406 23:14:24.377717 ARM64: Testing exception
407 23:14:24.377841 ARM64: Done test exception
408 23:14:24.384751 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 23:14:24.396158 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 23:14:24.402967 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 23:14:24.413279 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 23:14:24.420095 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 23:14:24.429787 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 23:14:24.440950 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 23:14:24.447812 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 23:14:24.464781 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 23:14:24.468297 WDT: Last reset was cold boot
418 23:14:24.471880 SPI1(PAD0) initialized at 2873684 Hz
419 23:14:24.475093 SPI5(PAD0) initialized at 992727 Hz
420 23:14:24.478670 VBOOT: Loading verstage.
421 23:14:24.485140 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 23:14:24.488432 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 23:14:24.491876 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 23:14:24.495495 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 23:14:24.502390 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 23:14:24.509105 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 23:14:24.519614 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
428 23:14:24.519737
429 23:14:24.519850
430 23:14:24.530753 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 23:14:24.533636 ARM64: Exception handlers installed.
432 23:14:24.537259 ARM64: Testing exception
433 23:14:24.537381 ARM64: Done test exception
434 23:14:24.543642 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 23:14:24.547138 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 23:14:24.560813 Probing TPM: . done!
437 23:14:24.560924 TPM ready after 0 ms
438 23:14:24.568250 Connected to device vid:did:rid of 1ae0:0028:00
439 23:14:24.574927 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
440 23:14:24.634686 Initialized TPM device CR50 revision 0
441 23:14:24.646241 tlcl_send_startup: Startup return code is 0
442 23:14:24.646339 TPM: setup succeeded
443 23:14:24.657628 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 23:14:24.666845 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 23:14:24.678582 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 23:14:24.688884 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 23:14:24.692516 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 23:14:24.696213 in-header: 03 07 00 00 08 00 00 00
449 23:14:24.700005 in-data: aa e4 47 04 13 02 00 00
450 23:14:24.700108 Chrome EC: UHEPI supported
451 23:14:24.707638 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 23:14:24.711102 in-header: 03 95 00 00 08 00 00 00
453 23:14:24.715285 in-data: 18 20 20 08 00 00 00 00
454 23:14:24.715368 Phase 1
455 23:14:24.719103 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 23:14:24.726699 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 23:14:24.729870 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 23:14:24.733874 Recovery requested (1009000e)
459 23:14:24.743414 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 23:14:24.748690 tlcl_extend: response is 0
461 23:14:24.758136 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 23:14:24.763746 tlcl_extend: response is 0
463 23:14:24.770494 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 23:14:24.790791 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
465 23:14:24.797254 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 23:14:24.797337
467 23:14:24.797402
468 23:14:24.807004 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 23:14:24.810432 ARM64: Exception handlers installed.
470 23:14:24.814023 ARM64: Testing exception
471 23:14:24.814105 ARM64: Done test exception
472 23:14:24.836174 pmic_efuse_setting: Set efuses in 11 msecs
473 23:14:24.839834 pmwrap_interface_init: Select PMIF_VLD_RDY
474 23:14:24.846131 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 23:14:24.849494 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 23:14:24.857155 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 23:14:24.860712 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 23:14:24.864028 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 23:14:24.867840 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 23:14:24.875730 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 23:14:24.879471 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 23:14:24.882990 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 23:14:24.887325 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 23:14:24.894737 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 23:14:24.898115 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 23:14:24.901884 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 23:14:24.908852 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 23:14:24.913144 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 23:14:24.920451 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 23:14:24.924217 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 23:14:24.931913 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 23:14:24.935409 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 23:14:24.943111 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 23:14:24.946705 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 23:14:24.953539 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 23:14:24.957778 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 23:14:24.965182 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 23:14:24.968602 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 23:14:24.976669 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 23:14:24.980234 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 23:14:24.983811 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 23:14:24.990986 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 23:14:24.994686 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 23:14:25.002369 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 23:14:25.005795 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 23:14:25.008893 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 23:14:25.016301 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 23:14:25.020586 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 23:14:25.024404 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 23:14:25.031355 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 23:14:25.034732 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 23:14:25.039251 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 23:14:25.042712 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 23:14:25.050221 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 23:14:25.053345 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 23:14:25.057615 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 23:14:25.060727 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 23:14:25.064465 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 23:14:25.071752 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 23:14:25.075425 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 23:14:25.079791 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 23:14:25.082763 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 23:14:25.086512 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 23:14:25.090281 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 23:14:25.098180 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 23:14:25.109349 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 23:14:25.112886 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 23:14:25.120731 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 23:14:25.127936 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 23:14:25.134972 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 23:14:25.138742 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 23:14:25.142349 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 23:14:25.149815 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0xa
534 23:14:25.153253 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 23:14:25.161561 [RTC]rtc_osc_init,62: osc32con val = 0xde70
536 23:14:25.165225 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 23:14:25.173756 [RTC]rtc_get_frequency_meter,154: input=15, output=759
538 23:14:25.183582 [RTC]rtc_get_frequency_meter,154: input=23, output=944
539 23:14:25.193227 [RTC]rtc_get_frequency_meter,154: input=19, output=851
540 23:14:25.201873 [RTC]rtc_get_frequency_meter,154: input=17, output=805
541 23:14:25.211823 [RTC]rtc_get_frequency_meter,154: input=16, output=782
542 23:14:25.221340 [RTC]rtc_get_frequency_meter,154: input=16, output=782
543 23:14:25.231572 [RTC]rtc_get_frequency_meter,154: input=17, output=805
544 23:14:25.235403 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
545 23:14:25.239379 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
546 23:14:25.242852 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
547 23:14:25.250372 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
548 23:14:25.253859 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
549 23:14:25.257836 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
550 23:14:25.261660 ADC[4]: Raw value=906203 ID=7
551 23:14:25.261741 ADC[3]: Raw value=213810 ID=1
552 23:14:25.265255 RAM Code: 0x71
553 23:14:25.269108 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
554 23:14:25.272927 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
555 23:14:25.281100 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
556 23:14:25.288425 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
557 23:14:25.292154 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
558 23:14:25.295691 in-header: 03 07 00 00 08 00 00 00
559 23:14:25.299257 in-data: aa e4 47 04 13 02 00 00
560 23:14:25.299375 Chrome EC: UHEPI supported
561 23:14:25.306305 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
562 23:14:25.312064 in-header: 03 95 00 00 08 00 00 00
563 23:14:25.315538 in-data: 18 20 20 08 00 00 00 00
564 23:14:25.319231 MRC: failed to locate region type 0.
565 23:14:25.326708 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
566 23:14:25.329755 DRAM-K: Running full calibration
567 23:14:25.333487 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
568 23:14:25.336981 header.status = 0x0
569 23:14:25.340809 header.version = 0x6 (expected: 0x6)
570 23:14:25.344628 header.size = 0xd00 (expected: 0xd00)
571 23:14:25.344755 header.flags = 0x0
572 23:14:25.351230 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
573 23:14:25.369436 read SPI 0x72590 0x1c583: 12501 us, 9287 KB/s, 74.296 Mbps
574 23:14:25.377231 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
575 23:14:25.377356 dram_init: ddr_geometry: 2
576 23:14:25.380621 [EMI] MDL number = 2
577 23:14:25.384450 [EMI] Get MDL freq = 0
578 23:14:25.384574 dram_init: ddr_type: 0
579 23:14:25.388668 is_discrete_lpddr4: 1
580 23:14:25.388750 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
581 23:14:25.388815
582 23:14:25.392586
583 23:14:25.392666 [Bian_co] ETT version 0.0.0.1
584 23:14:25.396323 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
585 23:14:25.396419
586 23:14:25.403194 dramc_set_vcore_voltage set vcore to 650000
587 23:14:25.403327 Read voltage for 800, 4
588 23:14:25.403445 Vio18 = 0
589 23:14:25.406682 Vcore = 650000
590 23:14:25.406803 Vdram = 0
591 23:14:25.406915 Vddq = 0
592 23:14:25.410411 Vmddr = 0
593 23:14:25.410531 dram_init: config_dvfs: 1
594 23:14:25.418202 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
595 23:14:25.421899 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
596 23:14:25.425552 [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9
597 23:14:25.429080 freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9
598 23:14:25.432864 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
599 23:14:25.435973 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
600 23:14:25.439704 MEM_TYPE=3, freq_sel=18
601 23:14:25.442822 sv_algorithm_assistance_LP4_1600
602 23:14:25.445857 ============ PULL DRAM RESETB DOWN ============
603 23:14:25.449332 ========== PULL DRAM RESETB DOWN end =========
604 23:14:25.457106 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
605 23:14:25.457187 ===================================
606 23:14:25.460214 LPDDR4 DRAM CONFIGURATION
607 23:14:25.463914 ===================================
608 23:14:25.467627 EX_ROW_EN[0] = 0x0
609 23:14:25.467709 EX_ROW_EN[1] = 0x0
610 23:14:25.471369 LP4Y_EN = 0x0
611 23:14:25.471450 WORK_FSP = 0x0
612 23:14:25.474533 WL = 0x2
613 23:14:25.474615 RL = 0x2
614 23:14:25.478263 BL = 0x2
615 23:14:25.478345 RPST = 0x0
616 23:14:25.481294 RD_PRE = 0x0
617 23:14:25.481375 WR_PRE = 0x1
618 23:14:25.484487 WR_PST = 0x0
619 23:14:25.484569 DBI_WR = 0x0
620 23:14:25.488017 DBI_RD = 0x0
621 23:14:25.488098 OTF = 0x1
622 23:14:25.491292 ===================================
623 23:14:25.495125 ===================================
624 23:14:25.495206 ANA top config
625 23:14:25.498780 ===================================
626 23:14:25.502451 DLL_ASYNC_EN = 0
627 23:14:25.505701 ALL_SLAVE_EN = 1
628 23:14:25.509247 NEW_RANK_MODE = 1
629 23:14:25.509329 DLL_IDLE_MODE = 1
630 23:14:25.512442 LP45_APHY_COMB_EN = 1
631 23:14:25.515504 TX_ODT_DIS = 1
632 23:14:25.519285 NEW_8X_MODE = 1
633 23:14:25.519407 ===================================
634 23:14:25.523214 ===================================
635 23:14:25.526914 data_rate = 1600
636 23:14:25.529937 CKR = 1
637 23:14:25.533131 DQ_P2S_RATIO = 8
638 23:14:25.536821 ===================================
639 23:14:25.539809 CA_P2S_RATIO = 8
640 23:14:25.543363 DQ_CA_OPEN = 0
641 23:14:25.543471 DQ_SEMI_OPEN = 0
642 23:14:25.546634 CA_SEMI_OPEN = 0
643 23:14:25.550059 CA_FULL_RATE = 0
644 23:14:25.553606 DQ_CKDIV4_EN = 1
645 23:14:25.556604 CA_CKDIV4_EN = 1
646 23:14:25.556686 CA_PREDIV_EN = 0
647 23:14:25.560253 PH8_DLY = 0
648 23:14:25.563296 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
649 23:14:25.567010 DQ_AAMCK_DIV = 4
650 23:14:25.570228 CA_AAMCK_DIV = 4
651 23:14:25.573773 CA_ADMCK_DIV = 4
652 23:14:25.573855 DQ_TRACK_CA_EN = 0
653 23:14:25.576848 CA_PICK = 800
654 23:14:25.580628 CA_MCKIO = 800
655 23:14:25.584295 MCKIO_SEMI = 0
656 23:14:25.587689 PLL_FREQ = 3068
657 23:14:25.587770 DQ_UI_PI_RATIO = 32
658 23:14:25.591183 CA_UI_PI_RATIO = 0
659 23:14:25.594860 ===================================
660 23:14:25.599117 ===================================
661 23:14:25.602719 memory_type:LPDDR4
662 23:14:25.602847 GP_NUM : 10
663 23:14:25.606137 SRAM_EN : 1
664 23:14:25.606260 MD32_EN : 0
665 23:14:25.610369 ===================================
666 23:14:25.613457 [ANA_INIT] >>>>>>>>>>>>>>
667 23:14:25.617215 <<<<<< [CONFIGURE PHASE]: ANA_TX
668 23:14:25.617343 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
669 23:14:25.620980 ===================================
670 23:14:25.624181 data_rate = 1600,PCW = 0X7600
671 23:14:25.627543 ===================================
672 23:14:25.631042 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
673 23:14:25.637551 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 23:14:25.644014 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
675 23:14:25.647346 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
676 23:14:25.650762 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
677 23:14:25.654201 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
678 23:14:25.657815 [ANA_INIT] flow start
679 23:14:25.657938 [ANA_INIT] PLL >>>>>>>>
680 23:14:25.661286 [ANA_INIT] PLL <<<<<<<<
681 23:14:25.664076 [ANA_INIT] MIDPI >>>>>>>>
682 23:14:25.664198 [ANA_INIT] MIDPI <<<<<<<<
683 23:14:25.667512 [ANA_INIT] DLL >>>>>>>>
684 23:14:25.670678 [ANA_INIT] flow end
685 23:14:25.674094 ============ LP4 DIFF to SE enter ============
686 23:14:25.677836 ============ LP4 DIFF to SE exit ============
687 23:14:25.680870 [ANA_INIT] <<<<<<<<<<<<<
688 23:14:25.684518 [Flow] Enable top DCM control >>>>>
689 23:14:25.687516 [Flow] Enable top DCM control <<<<<
690 23:14:25.691116 Enable DLL master slave shuffle
691 23:14:25.694272 ==============================================================
692 23:14:25.697960 Gating Mode config
693 23:14:25.704587 ==============================================================
694 23:14:25.704670 Config description:
695 23:14:25.714535 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
696 23:14:25.721443 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
697 23:14:25.724623 SELPH_MODE 0: By rank 1: By Phase
698 23:14:25.731415 ==============================================================
699 23:14:25.734591 GAT_TRACK_EN = 1
700 23:14:25.738088 RX_GATING_MODE = 2
701 23:14:25.741004 RX_GATING_TRACK_MODE = 2
702 23:14:25.744781 SELPH_MODE = 1
703 23:14:25.747837 PICG_EARLY_EN = 1
704 23:14:25.747947 VALID_LAT_VALUE = 1
705 23:14:25.754779 ==============================================================
706 23:14:25.758100 Enter into Gating configuration >>>>
707 23:14:25.761088 Exit from Gating configuration <<<<
708 23:14:25.764714 Enter into DVFS_PRE_config >>>>>
709 23:14:25.774877 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
710 23:14:25.777932 Exit from DVFS_PRE_config <<<<<
711 23:14:25.781130 Enter into PICG configuration >>>>
712 23:14:25.784790 Exit from PICG configuration <<<<
713 23:14:25.787729 [RX_INPUT] configuration >>>>>
714 23:14:25.791603 [RX_INPUT] configuration <<<<<
715 23:14:25.794576 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
716 23:14:25.801074 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
717 23:14:25.807802 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
718 23:14:25.814640 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
719 23:14:25.821102 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
720 23:14:25.824744 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
721 23:14:25.831043 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
722 23:14:25.834802 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
723 23:14:25.837886 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
724 23:14:25.841115 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
725 23:14:25.844556 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
726 23:14:25.851263 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
727 23:14:25.854688 ===================================
728 23:14:25.858079 LPDDR4 DRAM CONFIGURATION
729 23:14:25.861139 ===================================
730 23:14:25.861224 EX_ROW_EN[0] = 0x0
731 23:14:25.864676 EX_ROW_EN[1] = 0x0
732 23:14:25.864761 LP4Y_EN = 0x0
733 23:14:25.867437 WORK_FSP = 0x0
734 23:14:25.867522 WL = 0x2
735 23:14:25.871136 RL = 0x2
736 23:14:25.871221 BL = 0x2
737 23:14:25.874782 RPST = 0x0
738 23:14:25.874867 RD_PRE = 0x0
739 23:14:25.877752 WR_PRE = 0x1
740 23:14:25.877838 WR_PST = 0x0
741 23:14:25.881457 DBI_WR = 0x0
742 23:14:25.881542 DBI_RD = 0x0
743 23:14:25.884485 OTF = 0x1
744 23:14:25.887607 ===================================
745 23:14:25.891161 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
746 23:14:25.894213 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
747 23:14:25.901409 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
748 23:14:25.904467 ===================================
749 23:14:25.904553 LPDDR4 DRAM CONFIGURATION
750 23:14:25.907988 ===================================
751 23:14:25.911301 EX_ROW_EN[0] = 0x10
752 23:14:25.914262 EX_ROW_EN[1] = 0x0
753 23:14:25.914347 LP4Y_EN = 0x0
754 23:14:25.917739 WORK_FSP = 0x0
755 23:14:25.917824 WL = 0x2
756 23:14:25.921019 RL = 0x2
757 23:14:25.921105 BL = 0x2
758 23:14:25.924670 RPST = 0x0
759 23:14:25.924755 RD_PRE = 0x0
760 23:14:25.927824 WR_PRE = 0x1
761 23:14:25.927910 WR_PST = 0x0
762 23:14:25.931407 DBI_WR = 0x0
763 23:14:25.931492 DBI_RD = 0x0
764 23:14:25.934359 OTF = 0x1
765 23:14:25.937788 ===================================
766 23:14:25.944373 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
767 23:14:25.947876 nWR fixed to 40
768 23:14:25.947963 [ModeRegInit_LP4] CH0 RK0
769 23:14:25.951170 [ModeRegInit_LP4] CH0 RK1
770 23:14:25.954148 [ModeRegInit_LP4] CH1 RK0
771 23:14:25.957813 [ModeRegInit_LP4] CH1 RK1
772 23:14:25.957899 match AC timing 13
773 23:14:25.964371 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
774 23:14:25.967439 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
775 23:14:25.970911 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
776 23:14:25.977893 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
777 23:14:25.981452 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
778 23:14:25.981538 [EMI DOE] emi_dcm 0
779 23:14:25.987640 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
780 23:14:25.987725 ==
781 23:14:25.991170 Dram Type= 6, Freq= 0, CH_0, rank 0
782 23:14:25.994408 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
783 23:14:25.994494 ==
784 23:14:26.001033 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
785 23:14:26.004706 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
786 23:14:26.014519 [CA 0] Center 36 (6~67) winsize 62
787 23:14:26.018175 [CA 1] Center 36 (6~67) winsize 62
788 23:14:26.021300 [CA 2] Center 34 (4~65) winsize 62
789 23:14:26.025030 [CA 3] Center 33 (3~64) winsize 62
790 23:14:26.027975 [CA 4] Center 33 (3~63) winsize 61
791 23:14:26.031196 [CA 5] Center 32 (3~62) winsize 60
792 23:14:26.031282
793 23:14:26.034692 [CmdBusTrainingLP45] Vref(ca) range 1: 32
794 23:14:26.034777
795 23:14:26.037938 [CATrainingPosCal] consider 1 rank data
796 23:14:26.041345 u2DelayCellTimex100 = 270/100 ps
797 23:14:26.044786 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
798 23:14:26.048151 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
799 23:14:26.055015 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
800 23:14:26.058129 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
801 23:14:26.061414 CA4 delay=33 (3~63),Diff = 1 PI (7 cell)
802 23:14:26.064803 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
803 23:14:26.064924
804 23:14:26.068132 CA PerBit enable=1, Macro0, CA PI delay=32
805 23:14:26.068255
806 23:14:26.071546 [CBTSetCACLKResult] CA Dly = 32
807 23:14:26.071669 CS Dly: 5 (0~36)
808 23:14:26.071781 ==
809 23:14:26.074790 Dram Type= 6, Freq= 0, CH_0, rank 1
810 23:14:26.081288 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
811 23:14:26.081414 ==
812 23:14:26.084917 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
813 23:14:26.091624 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
814 23:14:26.100867 [CA 0] Center 36 (6~67) winsize 62
815 23:14:26.104114 [CA 1] Center 36 (6~67) winsize 62
816 23:14:26.107668 [CA 2] Center 34 (4~65) winsize 62
817 23:14:26.110795 [CA 3] Center 33 (3~64) winsize 62
818 23:14:26.113883 [CA 4] Center 32 (2~63) winsize 62
819 23:14:26.117554 [CA 5] Center 32 (2~63) winsize 62
820 23:14:26.117676
821 23:14:26.120658 [CmdBusTrainingLP45] Vref(ca) range 1: 32
822 23:14:26.120781
823 23:14:26.124267 [CATrainingPosCal] consider 2 rank data
824 23:14:26.127547 u2DelayCellTimex100 = 270/100 ps
825 23:14:26.131144 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
826 23:14:26.134174 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
827 23:14:26.140986 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
828 23:14:26.144472 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
829 23:14:26.147966 CA4 delay=33 (3~63),Diff = 1 PI (7 cell)
830 23:14:26.150889 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
831 23:14:26.150975
832 23:14:26.154373 CA PerBit enable=1, Macro0, CA PI delay=32
833 23:14:26.154459
834 23:14:26.157618 [CBTSetCACLKResult] CA Dly = 32
835 23:14:26.157704 CS Dly: 5 (0~37)
836 23:14:26.157790
837 23:14:26.161225 ----->DramcWriteLeveling(PI) begin...
838 23:14:26.161315 ==
839 23:14:26.164974 Dram Type= 6, Freq= 0, CH_0, rank 0
840 23:14:26.168596 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
841 23:14:26.172579 ==
842 23:14:26.172665 Write leveling (Byte 0): 34 => 34
843 23:14:26.175635 Write leveling (Byte 1): 30 => 30
844 23:14:26.179140 DramcWriteLeveling(PI) end<-----
845 23:14:26.179226
846 23:14:26.179315 ==
847 23:14:26.182511 Dram Type= 6, Freq= 0, CH_0, rank 0
848 23:14:26.185733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
849 23:14:26.189352 ==
850 23:14:26.189489 [Gating] SW mode calibration
851 23:14:26.196620 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
852 23:14:26.202938 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
853 23:14:26.206115 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
854 23:14:26.209679 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
855 23:14:26.216447 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
856 23:14:26.219923 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 23:14:26.223024 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 23:14:26.229756 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 23:14:26.233528 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 23:14:26.236612 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 23:14:26.243337 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 23:14:26.246630 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 23:14:26.250042 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 23:14:26.256458 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 23:14:26.259748 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 23:14:26.263534 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 23:14:26.266658 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 23:14:26.273452 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 23:14:26.276386 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 23:14:26.280186 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
871 23:14:26.286826 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
872 23:14:26.289766 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 23:14:26.293628 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 23:14:26.300167 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 23:14:26.303123 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 23:14:26.306584 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 23:14:26.313188 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 23:14:26.316734 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
879 23:14:26.320097 0 9 8 | B1->B0 | 2424 3131 | 0 0 | (0 0) (0 0)
880 23:14:26.326903 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
881 23:14:26.329936 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 23:14:26.333242 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 23:14:26.339917 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
884 23:14:26.342948 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
885 23:14:26.346726 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
886 23:14:26.353139 0 10 4 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 1)
887 23:14:26.356608 0 10 8 | B1->B0 | 3131 2424 | 0 0 | (0 0) (1 0)
888 23:14:26.359860 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
889 23:14:26.366342 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 23:14:26.369825 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 23:14:26.373555 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
892 23:14:26.376683 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
893 23:14:26.383411 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
894 23:14:26.386985 0 11 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
895 23:14:26.390205 0 11 8 | B1->B0 | 3131 3939 | 1 0 | (0 0) (0 0)
896 23:14:26.396666 0 11 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
897 23:14:26.399962 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 23:14:26.403382 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 23:14:26.409948 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
900 23:14:26.413026 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
901 23:14:26.416603 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
902 23:14:26.423302 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
903 23:14:26.426943 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
904 23:14:26.429993 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 23:14:26.436784 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 23:14:26.440536 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 23:14:26.443699 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 23:14:26.446966 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 23:14:26.453779 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 23:14:26.457030 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 23:14:26.460605 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 23:14:26.466930 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 23:14:26.470232 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 23:14:26.473605 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 23:14:26.480414 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
916 23:14:26.483326 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
917 23:14:26.486991 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
918 23:14:26.493845 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
919 23:14:26.496881 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
920 23:14:26.500488 Total UI for P1: 0, mck2ui 16
921 23:14:26.503692 best dqsien dly found for B0: ( 0, 14, 6)
922 23:14:26.507000 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
923 23:14:26.510276 Total UI for P1: 0, mck2ui 16
924 23:14:26.513422 best dqsien dly found for B1: ( 0, 14, 8)
925 23:14:26.517804 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
926 23:14:26.521333 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
927 23:14:26.521418
928 23:14:26.524414 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
929 23:14:26.527559 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
930 23:14:26.530550 [Gating] SW calibration Done
931 23:14:26.530635 ==
932 23:14:26.534268 Dram Type= 6, Freq= 0, CH_0, rank 0
933 23:14:26.537219 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 23:14:26.540970 ==
935 23:14:26.541055 RX Vref Scan: 0
936 23:14:26.541141
937 23:14:26.544011 RX Vref 0 -> 0, step: 1
938 23:14:26.544096
939 23:14:26.547547 RX Delay -130 -> 252, step: 16
940 23:14:26.551142 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
941 23:14:26.554058 iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224
942 23:14:26.557786 iDelay=206, Bit 2, Center 85 (-34 ~ 205) 240
943 23:14:26.560977 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
944 23:14:26.567563 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
945 23:14:26.570619 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
946 23:14:26.574144 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
947 23:14:26.577558 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
948 23:14:26.581131 iDelay=206, Bit 8, Center 77 (-34 ~ 189) 224
949 23:14:26.584079 iDelay=206, Bit 9, Center 77 (-34 ~ 189) 224
950 23:14:26.590976 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
951 23:14:26.594501 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
952 23:14:26.597379 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
953 23:14:26.600648 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
954 23:14:26.604174 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
955 23:14:26.610748 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
956 23:14:26.610834 ==
957 23:14:26.614211 Dram Type= 6, Freq= 0, CH_0, rank 0
958 23:14:26.617796 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
959 23:14:26.617882 ==
960 23:14:26.617968 DQS Delay:
961 23:14:26.621043 DQS0 = 0, DQS1 = 0
962 23:14:26.621128 DQM Delay:
963 23:14:26.624361 DQM0 = 88, DQM1 = 81
964 23:14:26.624447 DQ Delay:
965 23:14:26.627830 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
966 23:14:26.631285 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93
967 23:14:26.634249 DQ8 =77, DQ9 =77, DQ10 =77, DQ11 =77
968 23:14:26.637999 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
969 23:14:26.638084
970 23:14:26.638170
971 23:14:26.638251 ==
972 23:14:26.641082 Dram Type= 6, Freq= 0, CH_0, rank 0
973 23:14:26.644620 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
974 23:14:26.644705 ==
975 23:14:26.644792
976 23:14:26.647788
977 23:14:26.647872 TX Vref Scan disable
978 23:14:26.651584 == TX Byte 0 ==
979 23:14:26.654502 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
980 23:14:26.658028 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
981 23:14:26.661046 == TX Byte 1 ==
982 23:14:26.664871 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
983 23:14:26.667951 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
984 23:14:26.668036 ==
985 23:14:26.670988 Dram Type= 6, Freq= 0, CH_0, rank 0
986 23:14:26.677924 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
987 23:14:26.678009 ==
988 23:14:26.690167 TX Vref=22, minBit 8, minWin=27, winSum=447
989 23:14:26.693231 TX Vref=24, minBit 8, minWin=27, winSum=450
990 23:14:26.697028 TX Vref=26, minBit 4, minWin=28, winSum=455
991 23:14:26.699970 TX Vref=28, minBit 5, minWin=28, winSum=456
992 23:14:26.703512 TX Vref=30, minBit 5, minWin=28, winSum=457
993 23:14:26.706679 TX Vref=32, minBit 10, minWin=27, winSum=453
994 23:14:26.713554 [TxChooseVref] Worse bit 5, Min win 28, Win sum 457, Final Vref 30
995 23:14:26.713639
996 23:14:26.716681 Final TX Range 1 Vref 30
997 23:14:26.716767
998 23:14:26.716877 ==
999 23:14:26.720276 Dram Type= 6, Freq= 0, CH_0, rank 0
1000 23:14:26.723503 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1001 23:14:26.723586 ==
1002 23:14:26.723651
1003 23:14:26.723711
1004 23:14:26.726728 TX Vref Scan disable
1005 23:14:26.730297 == TX Byte 0 ==
1006 23:14:26.733548 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
1007 23:14:26.736962 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
1008 23:14:26.740060 == TX Byte 1 ==
1009 23:14:26.743484 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1010 23:14:26.746787 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1011 23:14:26.746909
1012 23:14:26.750171 [DATLAT]
1013 23:14:26.750294 Freq=800, CH0 RK0
1014 23:14:26.750406
1015 23:14:26.753597 DATLAT Default: 0xa
1016 23:14:26.753720 0, 0xFFFF, sum = 0
1017 23:14:26.756652 1, 0xFFFF, sum = 0
1018 23:14:26.756781 2, 0xFFFF, sum = 0
1019 23:14:26.760075 3, 0xFFFF, sum = 0
1020 23:14:26.760197 4, 0xFFFF, sum = 0
1021 23:14:26.763530 5, 0xFFFF, sum = 0
1022 23:14:26.763654 6, 0xFFFF, sum = 0
1023 23:14:26.767221 7, 0xFFFF, sum = 0
1024 23:14:26.767345 8, 0xFFFF, sum = 0
1025 23:14:26.770212 9, 0x0, sum = 1
1026 23:14:26.770336 10, 0x0, sum = 2
1027 23:14:26.773968 11, 0x0, sum = 3
1028 23:14:26.774091 12, 0x0, sum = 4
1029 23:14:26.776992 best_step = 10
1030 23:14:26.777110
1031 23:14:26.777221 ==
1032 23:14:26.780792 Dram Type= 6, Freq= 0, CH_0, rank 0
1033 23:14:26.783730 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1034 23:14:26.783852 ==
1035 23:14:26.786807 RX Vref Scan: 1
1036 23:14:26.786925
1037 23:14:26.787038 Set Vref Range= 32 -> 127
1038 23:14:26.787144
1039 23:14:26.790230 RX Vref 32 -> 127, step: 1
1040 23:14:26.790349
1041 23:14:26.793799 RX Delay -79 -> 252, step: 8
1042 23:14:26.793917
1043 23:14:26.796916 Set Vref, RX VrefLevel [Byte0]: 32
1044 23:14:26.800588 [Byte1]: 32
1045 23:14:26.800709
1046 23:14:26.803708 Set Vref, RX VrefLevel [Byte0]: 33
1047 23:14:26.807253 [Byte1]: 33
1048 23:14:26.807369
1049 23:14:26.810209 Set Vref, RX VrefLevel [Byte0]: 34
1050 23:14:26.813653 [Byte1]: 34
1051 23:14:26.817300
1052 23:14:26.821016 Set Vref, RX VrefLevel [Byte0]: 35
1053 23:14:26.824616 [Byte1]: 35
1054 23:14:26.824736
1055 23:14:26.828224 Set Vref, RX VrefLevel [Byte0]: 36
1056 23:14:26.831675 [Byte1]: 36
1057 23:14:26.831795
1058 23:14:26.835332 Set Vref, RX VrefLevel [Byte0]: 37
1059 23:14:26.838893 [Byte1]: 37
1060 23:14:26.839013
1061 23:14:26.843170 Set Vref, RX VrefLevel [Byte0]: 38
1062 23:14:26.846518 [Byte1]: 38
1063 23:14:26.846641
1064 23:14:26.850394 Set Vref, RX VrefLevel [Byte0]: 39
1065 23:14:26.854478 [Byte1]: 39
1066 23:14:26.854600
1067 23:14:26.858158 Set Vref, RX VrefLevel [Byte0]: 40
1068 23:14:26.861880 [Byte1]: 40
1069 23:14:26.862001
1070 23:14:26.864949 Set Vref, RX VrefLevel [Byte0]: 41
1071 23:14:26.868236 [Byte1]: 41
1072 23:14:26.868400
1073 23:14:26.871744 Set Vref, RX VrefLevel [Byte0]: 42
1074 23:14:26.875007 [Byte1]: 42
1075 23:14:26.875127
1076 23:14:26.878476 Set Vref, RX VrefLevel [Byte0]: 43
1077 23:14:26.881928 [Byte1]: 43
1078 23:14:26.885493
1079 23:14:26.885613 Set Vref, RX VrefLevel [Byte0]: 44
1080 23:14:26.889021 [Byte1]: 44
1081 23:14:26.893145
1082 23:14:26.893265 Set Vref, RX VrefLevel [Byte0]: 45
1083 23:14:26.896712 [Byte1]: 45
1084 23:14:26.901044
1085 23:14:26.901163 Set Vref, RX VrefLevel [Byte0]: 46
1086 23:14:26.904038 [Byte1]: 46
1087 23:14:26.908419
1088 23:14:26.908539 Set Vref, RX VrefLevel [Byte0]: 47
1089 23:14:26.911359 [Byte1]: 47
1090 23:14:26.915679
1091 23:14:26.915798 Set Vref, RX VrefLevel [Byte0]: 48
1092 23:14:26.918958 [Byte1]: 48
1093 23:14:26.923395
1094 23:14:26.923513 Set Vref, RX VrefLevel [Byte0]: 49
1095 23:14:26.927023 [Byte1]: 49
1096 23:14:26.931233
1097 23:14:26.931352 Set Vref, RX VrefLevel [Byte0]: 50
1098 23:14:26.934240 [Byte1]: 50
1099 23:14:26.938445
1100 23:14:26.938565 Set Vref, RX VrefLevel [Byte0]: 51
1101 23:14:26.941936 [Byte1]: 51
1102 23:14:26.946512
1103 23:14:26.946630 Set Vref, RX VrefLevel [Byte0]: 52
1104 23:14:26.949521 [Byte1]: 52
1105 23:14:26.953663
1106 23:14:26.953782 Set Vref, RX VrefLevel [Byte0]: 53
1107 23:14:26.957214 [Byte1]: 53
1108 23:14:26.961055
1109 23:14:26.961175 Set Vref, RX VrefLevel [Byte0]: 54
1110 23:14:26.964666 [Byte1]: 54
1111 23:14:26.968996
1112 23:14:26.969097 Set Vref, RX VrefLevel [Byte0]: 55
1113 23:14:26.972046 [Byte1]: 55
1114 23:14:26.976223
1115 23:14:26.976325 Set Vref, RX VrefLevel [Byte0]: 56
1116 23:14:26.979401 [Byte1]: 56
1117 23:14:26.983679
1118 23:14:26.983759 Set Vref, RX VrefLevel [Byte0]: 57
1119 23:14:26.987190 [Byte1]: 57
1120 23:14:26.991317
1121 23:14:26.991397 Set Vref, RX VrefLevel [Byte0]: 58
1122 23:14:26.994580 [Byte1]: 58
1123 23:14:26.998972
1124 23:14:26.999053 Set Vref, RX VrefLevel [Byte0]: 59
1125 23:14:27.002199 [Byte1]: 59
1126 23:14:27.006372
1127 23:14:27.006452 Set Vref, RX VrefLevel [Byte0]: 60
1128 23:14:27.009572 [Byte1]: 60
1129 23:14:27.013879
1130 23:14:27.013959 Set Vref, RX VrefLevel [Byte0]: 61
1131 23:14:27.017100 [Byte1]: 61
1132 23:14:27.021689
1133 23:14:27.021769 Set Vref, RX VrefLevel [Byte0]: 62
1134 23:14:27.025301 [Byte1]: 62
1135 23:14:27.028833
1136 23:14:27.028954 Set Vref, RX VrefLevel [Byte0]: 63
1137 23:14:27.032210 [Byte1]: 63
1138 23:14:27.036453
1139 23:14:27.036577 Set Vref, RX VrefLevel [Byte0]: 64
1140 23:14:27.040175 [Byte1]: 64
1141 23:14:27.044231
1142 23:14:27.044389 Set Vref, RX VrefLevel [Byte0]: 65
1143 23:14:27.047256 [Byte1]: 65
1144 23:14:27.051516
1145 23:14:27.051636 Set Vref, RX VrefLevel [Byte0]: 66
1146 23:14:27.055096 [Byte1]: 66
1147 23:14:27.059286
1148 23:14:27.059408 Set Vref, RX VrefLevel [Byte0]: 67
1149 23:14:27.062926 [Byte1]: 67
1150 23:14:27.067089
1151 23:14:27.067211 Set Vref, RX VrefLevel [Byte0]: 68
1152 23:14:27.070060 [Byte1]: 68
1153 23:14:27.074263
1154 23:14:27.074383 Set Vref, RX VrefLevel [Byte0]: 69
1155 23:14:27.077929 [Byte1]: 69
1156 23:14:27.082266
1157 23:14:27.082387 Set Vref, RX VrefLevel [Byte0]: 70
1158 23:14:27.085215 [Byte1]: 70
1159 23:14:27.089516
1160 23:14:27.089636 Set Vref, RX VrefLevel [Byte0]: 71
1161 23:14:27.092680 [Byte1]: 71
1162 23:14:27.096890
1163 23:14:27.097012 Set Vref, RX VrefLevel [Byte0]: 72
1164 23:14:27.100563 [Byte1]: 72
1165 23:14:27.104899
1166 23:14:27.105020 Set Vref, RX VrefLevel [Byte0]: 73
1167 23:14:27.107937 [Byte1]: 73
1168 23:14:27.112415
1169 23:14:27.112537 Set Vref, RX VrefLevel [Byte0]: 74
1170 23:14:27.115530 [Byte1]: 74
1171 23:14:27.119598
1172 23:14:27.119720 Set Vref, RX VrefLevel [Byte0]: 75
1173 23:14:27.122837 [Byte1]: 75
1174 23:14:27.127003
1175 23:14:27.127087 Set Vref, RX VrefLevel [Byte0]: 76
1176 23:14:27.130489 [Byte1]: 76
1177 23:14:27.134588
1178 23:14:27.134672 Set Vref, RX VrefLevel [Byte0]: 77
1179 23:14:27.138293 [Byte1]: 77
1180 23:14:27.142030
1181 23:14:27.142114 Final RX Vref Byte 0 = 53 to rank0
1182 23:14:27.145567 Final RX Vref Byte 1 = 56 to rank0
1183 23:14:27.149182 Final RX Vref Byte 0 = 53 to rank1
1184 23:14:27.152553 Final RX Vref Byte 1 = 56 to rank1==
1185 23:14:27.155851 Dram Type= 6, Freq= 0, CH_0, rank 0
1186 23:14:27.159160 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1187 23:14:27.162271 ==
1188 23:14:27.162355 DQS Delay:
1189 23:14:27.162441 DQS0 = 0, DQS1 = 0
1190 23:14:27.165589 DQM Delay:
1191 23:14:27.165673 DQM0 = 91, DQM1 = 85
1192 23:14:27.169145 DQ Delay:
1193 23:14:27.169230 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88
1194 23:14:27.172359 DQ4 =92, DQ5 =80, DQ6 =100, DQ7 =100
1195 23:14:27.175633 DQ8 =72, DQ9 =76, DQ10 =88, DQ11 =76
1196 23:14:27.179122 DQ12 =92, DQ13 =92, DQ14 =92, DQ15 =92
1197 23:14:27.182936
1198 23:14:27.183020
1199 23:14:27.188910 [DQSOSCAuto] RK0, (LSB)MR18= 0x4d44, (MSB)MR19= 0x606, tDQSOscB0 = 392 ps tDQSOscB1 = 390 ps
1200 23:14:27.192546 CH0 RK0: MR19=606, MR18=4D44
1201 23:14:27.199426 CH0_RK0: MR19=0x606, MR18=0x4D44, DQSOSC=390, MR23=63, INC=97, DEC=64
1202 23:14:27.199511
1203 23:14:27.202543 ----->DramcWriteLeveling(PI) begin...
1204 23:14:27.202629 ==
1205 23:14:27.205556 Dram Type= 6, Freq= 0, CH_0, rank 1
1206 23:14:27.209268 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1207 23:14:27.209350 ==
1208 23:14:27.212260 Write leveling (Byte 0): 34 => 34
1209 23:14:27.215980 Write leveling (Byte 1): 31 => 31
1210 23:14:27.219063 DramcWriteLeveling(PI) end<-----
1211 23:14:27.219183
1212 23:14:27.219294 ==
1213 23:14:27.222797 Dram Type= 6, Freq= 0, CH_0, rank 1
1214 23:14:27.225929 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1215 23:14:27.226051 ==
1216 23:14:27.229002 [Gating] SW mode calibration
1217 23:14:27.236054 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1218 23:14:27.279680 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1219 23:14:27.280008 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1220 23:14:27.280142 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1221 23:14:27.280272 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 23:14:27.280422 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 23:14:27.280533 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 23:14:27.280661 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 23:14:27.280774 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 23:14:27.280939 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 23:14:27.281050 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 23:14:27.317613 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 23:14:27.317920 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 23:14:27.318003 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 23:14:27.318529 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 23:14:27.318627 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 23:14:27.318903 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 23:14:27.318995 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 23:14:27.319271 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 23:14:27.322387 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1237 23:14:27.325466 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1238 23:14:27.329252 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 23:14:27.332232 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1240 23:14:27.338936 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1241 23:14:27.342497 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 23:14:27.345629 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1243 23:14:27.352110 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 23:14:27.355616 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1245 23:14:27.359144 0 9 8 | B1->B0 | 302f 2e2e | 1 0 | (1 1) (0 0)
1246 23:14:27.365561 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1247 23:14:27.369037 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1248 23:14:27.372066 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1249 23:14:27.379336 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1250 23:14:27.382389 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1251 23:14:27.386245 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1252 23:14:27.392461 0 10 4 | B1->B0 | 3232 3434 | 0 0 | (0 0) (0 0)
1253 23:14:27.396177 0 10 8 | B1->B0 | 2626 2b2b | 0 1 | (0 0) (1 0)
1254 23:14:27.399173 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1255 23:14:27.402813 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1256 23:14:27.410178 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1257 23:14:27.413582 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1258 23:14:27.417063 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1259 23:14:27.421140 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1260 23:14:27.424541 0 11 4 | B1->B0 | 2424 2424 | 0 1 | (0 0) (0 0)
1261 23:14:27.431247 0 11 8 | B1->B0 | 4040 3b3b | 0 0 | (0 0) (0 0)
1262 23:14:27.435119 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1263 23:14:27.438140 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1264 23:14:27.445422 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1265 23:14:27.448441 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1266 23:14:27.451823 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1267 23:14:27.455381 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1268 23:14:27.461643 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1269 23:14:27.465002 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1270 23:14:27.468705 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1271 23:14:27.475108 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1272 23:14:27.478606 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1273 23:14:27.481698 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1274 23:14:27.488450 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 23:14:27.491577 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1276 23:14:27.495310 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1277 23:14:27.502085 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1278 23:14:27.505529 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1279 23:14:27.508593 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1280 23:14:27.515248 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1281 23:14:27.518842 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1282 23:14:27.521893 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1283 23:14:27.528524 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1284 23:14:27.532298 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1285 23:14:27.535195 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1286 23:14:27.539027 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1287 23:14:27.542105 Total UI for P1: 0, mck2ui 16
1288 23:14:27.545610 best dqsien dly found for B0: ( 0, 14, 10)
1289 23:14:27.548626 Total UI for P1: 0, mck2ui 16
1290 23:14:27.551664 best dqsien dly found for B1: ( 0, 14, 8)
1291 23:14:27.555286 best DQS0 dly(MCK, UI, PI) = (0, 14, 10)
1292 23:14:27.558717 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1293 23:14:27.561817
1294 23:14:27.565257 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 10)
1295 23:14:27.568794 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1296 23:14:27.571855 [Gating] SW calibration Done
1297 23:14:27.571936 ==
1298 23:14:27.575262 Dram Type= 6, Freq= 0, CH_0, rank 1
1299 23:14:27.578762 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1300 23:14:27.578843 ==
1301 23:14:27.578907 RX Vref Scan: 0
1302 23:14:27.578966
1303 23:14:27.582149 RX Vref 0 -> 0, step: 1
1304 23:14:27.582230
1305 23:14:27.585597 RX Delay -130 -> 252, step: 16
1306 23:14:27.588562 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1307 23:14:27.592025 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1308 23:14:27.598917 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
1309 23:14:27.601952 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1310 23:14:27.605735 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1311 23:14:27.608703 iDelay=222, Bit 5, Center 93 (-18 ~ 205) 224
1312 23:14:27.612347 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1313 23:14:27.618519 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1314 23:14:27.622090 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1315 23:14:27.625839 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1316 23:14:27.628613 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1317 23:14:27.632096 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1318 23:14:27.638951 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1319 23:14:27.642078 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1320 23:14:27.645798 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1321 23:14:27.648742 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1322 23:14:27.648824 ==
1323 23:14:27.652509 Dram Type= 6, Freq= 0, CH_0, rank 1
1324 23:14:27.655673 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1325 23:14:27.658755 ==
1326 23:14:27.658836 DQS Delay:
1327 23:14:27.658901 DQS0 = 0, DQS1 = 0
1328 23:14:27.662483 DQM Delay:
1329 23:14:27.662564 DQM0 = 94, DQM1 = 86
1330 23:14:27.665542 DQ Delay:
1331 23:14:27.665628 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =93
1332 23:14:27.669165 DQ4 =93, DQ5 =93, DQ6 =93, DQ7 =101
1333 23:14:27.672044 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =77
1334 23:14:27.675796 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1335 23:14:27.678795
1336 23:14:27.678874
1337 23:14:27.678938 ==
1338 23:14:27.682505 Dram Type= 6, Freq= 0, CH_0, rank 1
1339 23:14:27.685574 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1340 23:14:27.685656 ==
1341 23:14:27.685720
1342 23:14:27.685779
1343 23:14:27.688536 TX Vref Scan disable
1344 23:14:27.688671 == TX Byte 0 ==
1345 23:14:27.695758 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
1346 23:14:27.699136 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
1347 23:14:27.699218 == TX Byte 1 ==
1348 23:14:27.705547 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1349 23:14:27.709134 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1350 23:14:27.709288 ==
1351 23:14:27.711945 Dram Type= 6, Freq= 0, CH_0, rank 1
1352 23:14:27.715528 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1353 23:14:27.715648 ==
1354 23:14:27.729275 TX Vref=22, minBit 9, minWin=27, winSum=448
1355 23:14:27.732521 TX Vref=24, minBit 9, minWin=27, winSum=453
1356 23:14:27.736075 TX Vref=26, minBit 8, minWin=27, winSum=454
1357 23:14:27.739515 TX Vref=28, minBit 1, minWin=28, winSum=454
1358 23:14:27.742444 TX Vref=30, minBit 10, minWin=27, winSum=452
1359 23:14:27.746075 TX Vref=32, minBit 8, minWin=27, winSum=451
1360 23:14:27.753144 [TxChooseVref] Worse bit 1, Min win 28, Win sum 454, Final Vref 28
1361 23:14:27.753273
1362 23:14:27.756184 Final TX Range 1 Vref 28
1363 23:14:27.756344
1364 23:14:27.756452 ==
1365 23:14:27.759515 Dram Type= 6, Freq= 0, CH_0, rank 1
1366 23:14:27.762981 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1367 23:14:27.763102 ==
1368 23:14:27.763213
1369 23:14:27.763320
1370 23:14:27.766113 TX Vref Scan disable
1371 23:14:27.769877 == TX Byte 0 ==
1372 23:14:27.773211 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
1373 23:14:27.776308 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
1374 23:14:27.779567 == TX Byte 1 ==
1375 23:14:27.783130 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1376 23:14:27.786341 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1377 23:14:27.786461
1378 23:14:27.789398 [DATLAT]
1379 23:14:27.789515 Freq=800, CH0 RK1
1380 23:14:27.789626
1381 23:14:27.793072 DATLAT Default: 0xa
1382 23:14:27.793189 0, 0xFFFF, sum = 0
1383 23:14:27.796176 1, 0xFFFF, sum = 0
1384 23:14:27.796319 2, 0xFFFF, sum = 0
1385 23:14:27.799734 3, 0xFFFF, sum = 0
1386 23:14:27.799858 4, 0xFFFF, sum = 0
1387 23:14:27.802844 5, 0xFFFF, sum = 0
1388 23:14:27.802965 6, 0xFFFF, sum = 0
1389 23:14:27.806499 7, 0xFFFF, sum = 0
1390 23:14:27.806623 8, 0xFFFF, sum = 0
1391 23:14:27.809556 9, 0x0, sum = 1
1392 23:14:27.809678 10, 0x0, sum = 2
1393 23:14:27.813160 11, 0x0, sum = 3
1394 23:14:27.813284 12, 0x0, sum = 4
1395 23:14:27.816056 best_step = 10
1396 23:14:27.816175
1397 23:14:27.816291 ==
1398 23:14:27.819709 Dram Type= 6, Freq= 0, CH_0, rank 1
1399 23:14:27.822676 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1400 23:14:27.822797 ==
1401 23:14:27.826343 RX Vref Scan: 0
1402 23:14:27.826463
1403 23:14:27.826572 RX Vref 0 -> 0, step: 1
1404 23:14:27.826683
1405 23:14:27.829251 RX Delay -79 -> 252, step: 8
1406 23:14:27.835949 iDelay=209, Bit 0, Center 92 (-15 ~ 200) 216
1407 23:14:27.839526 iDelay=209, Bit 1, Center 96 (-7 ~ 200) 208
1408 23:14:27.842881 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1409 23:14:27.846140 iDelay=209, Bit 3, Center 92 (-15 ~ 200) 216
1410 23:14:27.849433 iDelay=209, Bit 4, Center 96 (-15 ~ 208) 224
1411 23:14:27.856290 iDelay=209, Bit 5, Center 84 (-23 ~ 192) 216
1412 23:14:27.859403 iDelay=209, Bit 6, Center 96 (-7 ~ 200) 208
1413 23:14:27.862817 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1414 23:14:27.866129 iDelay=209, Bit 8, Center 76 (-31 ~ 184) 216
1415 23:14:27.869351 iDelay=209, Bit 9, Center 76 (-31 ~ 184) 216
1416 23:14:27.876048 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1417 23:14:27.879298 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1418 23:14:27.882485 iDelay=209, Bit 12, Center 88 (-15 ~ 192) 208
1419 23:14:27.886015 iDelay=209, Bit 13, Center 92 (-15 ~ 200) 216
1420 23:14:27.889504 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1421 23:14:27.896152 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1422 23:14:27.896232 ==
1423 23:14:27.899815 Dram Type= 6, Freq= 0, CH_0, rank 1
1424 23:14:27.902753 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1425 23:14:27.902876 ==
1426 23:14:27.902988 DQS Delay:
1427 23:14:27.905772 DQS0 = 0, DQS1 = 0
1428 23:14:27.905891 DQM Delay:
1429 23:14:27.909452 DQM0 = 93, DQM1 = 84
1430 23:14:27.909572 DQ Delay:
1431 23:14:27.912702 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =92
1432 23:14:27.916217 DQ4 =96, DQ5 =84, DQ6 =96, DQ7 =100
1433 23:14:27.919271 DQ8 =76, DQ9 =76, DQ10 =84, DQ11 =76
1434 23:14:27.922810 DQ12 =88, DQ13 =92, DQ14 =92, DQ15 =88
1435 23:14:27.922932
1436 23:14:27.923042
1437 23:14:27.929667 [DQSOSCAuto] RK1, (LSB)MR18= 0x4616, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 392 ps
1438 23:14:27.932470 CH0 RK1: MR19=606, MR18=4616
1439 23:14:27.939231 CH0_RK1: MR19=0x606, MR18=0x4616, DQSOSC=392, MR23=63, INC=96, DEC=64
1440 23:14:27.942844 [RxdqsGatingPostProcess] freq 800
1441 23:14:27.949604 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1442 23:14:27.952438 Pre-setting of DQS Precalculation
1443 23:14:27.956160 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1444 23:14:27.956280 ==
1445 23:14:27.959179 Dram Type= 6, Freq= 0, CH_1, rank 0
1446 23:14:27.962849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1447 23:14:27.962968 ==
1448 23:14:27.969490 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1449 23:14:27.975956 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1450 23:14:27.984457 [CA 0] Center 36 (6~67) winsize 62
1451 23:14:27.987737 [CA 1] Center 36 (6~67) winsize 62
1452 23:14:27.990771 [CA 2] Center 35 (5~65) winsize 61
1453 23:14:27.994175 [CA 3] Center 34 (4~65) winsize 62
1454 23:14:27.997641 [CA 4] Center 34 (4~65) winsize 62
1455 23:14:28.001030 [CA 5] Center 34 (4~64) winsize 61
1456 23:14:28.001111
1457 23:14:28.004550 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1458 23:14:28.004630
1459 23:14:28.007524 [CATrainingPosCal] consider 1 rank data
1460 23:14:28.010853 u2DelayCellTimex100 = 270/100 ps
1461 23:14:28.014567 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1462 23:14:28.017778 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1463 23:14:28.021131 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1464 23:14:28.028111 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1465 23:14:28.031051 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1466 23:14:28.034695 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1467 23:14:28.034778
1468 23:14:28.037682 CA PerBit enable=1, Macro0, CA PI delay=34
1469 23:14:28.037764
1470 23:14:28.041433 [CBTSetCACLKResult] CA Dly = 34
1471 23:14:28.041515 CS Dly: 5 (0~36)
1472 23:14:28.041580 ==
1473 23:14:28.044585 Dram Type= 6, Freq= 0, CH_1, rank 1
1474 23:14:28.051290 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1475 23:14:28.051373 ==
1476 23:14:28.054824 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1477 23:14:28.061538 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1478 23:14:28.070622 [CA 0] Center 36 (6~67) winsize 62
1479 23:14:28.074487 [CA 1] Center 36 (6~67) winsize 62
1480 23:14:28.077763 [CA 2] Center 35 (4~66) winsize 63
1481 23:14:28.081311 [CA 3] Center 34 (4~65) winsize 62
1482 23:14:28.085175 [CA 4] Center 35 (4~66) winsize 63
1483 23:14:28.088564 [CA 5] Center 34 (4~65) winsize 62
1484 23:14:28.088687
1485 23:14:28.092324 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1486 23:14:28.092447
1487 23:14:28.096112 [CATrainingPosCal] consider 2 rank data
1488 23:14:28.099710 u2DelayCellTimex100 = 270/100 ps
1489 23:14:28.103286 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1490 23:14:28.106764 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1491 23:14:28.109742 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1492 23:14:28.113132 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1493 23:14:28.116413 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1494 23:14:28.120137 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1495 23:14:28.120253
1496 23:14:28.123340 CA PerBit enable=1, Macro0, CA PI delay=34
1497 23:14:28.123458
1498 23:14:28.126346 [CBTSetCACLKResult] CA Dly = 34
1499 23:14:28.126465 CS Dly: 6 (0~38)
1500 23:14:28.129779
1501 23:14:28.133123 ----->DramcWriteLeveling(PI) begin...
1502 23:14:28.133244 ==
1503 23:14:28.136756 Dram Type= 6, Freq= 0, CH_1, rank 0
1504 23:14:28.139731 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1505 23:14:28.139850 ==
1506 23:14:28.143035 Write leveling (Byte 0): 29 => 29
1507 23:14:28.146350 Write leveling (Byte 1): 24 => 24
1508 23:14:28.149945 DramcWriteLeveling(PI) end<-----
1509 23:14:28.150062
1510 23:14:28.150172 ==
1511 23:14:28.153133 Dram Type= 6, Freq= 0, CH_1, rank 0
1512 23:14:28.156472 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1513 23:14:28.156555 ==
1514 23:14:28.159755 [Gating] SW mode calibration
1515 23:14:28.166507 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1516 23:14:28.173349 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1517 23:14:28.176505 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1518 23:14:28.180030 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1519 23:14:28.183502 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 23:14:28.190085 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 23:14:28.193705 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 23:14:28.196745 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 23:14:28.203542 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 23:14:28.207117 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 23:14:28.210183 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 23:14:28.216788 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 23:14:28.220249 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 23:14:28.223931 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 23:14:28.230514 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 23:14:28.233650 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 23:14:28.237393 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 23:14:28.240418 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 23:14:28.247158 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 23:14:28.250249 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1535 23:14:28.253837 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 23:14:28.260450 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 23:14:28.263616 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 23:14:28.267612 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 23:14:28.273962 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 23:14:28.277239 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 23:14:28.280404 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1542 23:14:28.287195 0 9 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
1543 23:14:28.290531 0 9 8 | B1->B0 | 2e2e 3434 | 0 0 | (0 0) (0 0)
1544 23:14:28.294154 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1545 23:14:28.300444 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1546 23:14:28.304228 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1547 23:14:28.307184 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1548 23:14:28.310984 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1549 23:14:28.317493 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1550 23:14:28.320590 0 10 4 | B1->B0 | 3131 2f2f | 1 1 | (1 0) (1 1)
1551 23:14:28.323899 0 10 8 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1552 23:14:28.330623 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1553 23:14:28.334230 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1554 23:14:28.337334 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1555 23:14:28.344192 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1556 23:14:28.347767 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1557 23:14:28.350809 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1558 23:14:28.357431 0 11 4 | B1->B0 | 2828 3636 | 1 1 | (0 0) (1 1)
1559 23:14:28.361038 0 11 8 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
1560 23:14:28.364094 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1561 23:14:28.370906 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1562 23:14:28.373872 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1563 23:14:28.377531 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1564 23:14:28.384136 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1565 23:14:28.387726 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1566 23:14:28.390606 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1567 23:14:28.394204 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1568 23:14:28.400689 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1569 23:14:28.404512 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1570 23:14:28.407471 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 23:14:28.414324 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 23:14:28.417592 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 23:14:28.420973 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1574 23:14:28.427579 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1575 23:14:28.431197 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1576 23:14:28.434611 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1577 23:14:28.441274 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1578 23:14:28.444512 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1579 23:14:28.447912 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1580 23:14:28.454636 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1581 23:14:28.457701 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1582 23:14:28.461296 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1583 23:14:28.464204 Total UI for P1: 0, mck2ui 16
1584 23:14:28.467788 best dqsien dly found for B1: ( 0, 14, 2)
1585 23:14:28.470898 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1586 23:14:28.474762 Total UI for P1: 0, mck2ui 16
1587 23:14:28.477702 best dqsien dly found for B0: ( 0, 14, 2)
1588 23:14:28.481347 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1589 23:14:28.484397 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1590 23:14:28.488153
1591 23:14:28.491000 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1592 23:14:28.494592 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1593 23:14:28.497613 [Gating] SW calibration Done
1594 23:14:28.497693 ==
1595 23:14:28.501374 Dram Type= 6, Freq= 0, CH_1, rank 0
1596 23:14:28.504589 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1597 23:14:28.504669 ==
1598 23:14:28.504731 RX Vref Scan: 0
1599 23:14:28.504788
1600 23:14:28.507736 RX Vref 0 -> 0, step: 1
1601 23:14:28.507815
1602 23:14:28.511325 RX Delay -130 -> 252, step: 16
1603 23:14:28.514406 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1604 23:14:28.518033 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1605 23:14:28.524430 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1606 23:14:28.528042 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1607 23:14:28.530885 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1608 23:14:28.534737 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1609 23:14:28.537809 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1610 23:14:28.544739 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1611 23:14:28.547654 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1612 23:14:28.551315 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1613 23:14:28.554654 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1614 23:14:28.557734 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1615 23:14:28.564536 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1616 23:14:28.567991 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1617 23:14:28.570818 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1618 23:14:28.574392 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1619 23:14:28.574471 ==
1620 23:14:28.577590 Dram Type= 6, Freq= 0, CH_1, rank 0
1621 23:14:28.584711 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1622 23:14:28.584792 ==
1623 23:14:28.584855 DQS Delay:
1624 23:14:28.584914 DQS0 = 0, DQS1 = 0
1625 23:14:28.587763 DQM Delay:
1626 23:14:28.587842 DQM0 = 93, DQM1 = 87
1627 23:14:28.590918 DQ Delay:
1628 23:14:28.594714 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1629 23:14:28.598031 DQ4 =93, DQ5 =109, DQ6 =101, DQ7 =93
1630 23:14:28.598110 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =85
1631 23:14:28.604250 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1632 23:14:28.604375
1633 23:14:28.604439
1634 23:14:28.604496 ==
1635 23:14:28.608077 Dram Type= 6, Freq= 0, CH_1, rank 0
1636 23:14:28.610905 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1637 23:14:28.610985 ==
1638 23:14:28.611048
1639 23:14:28.611105
1640 23:14:28.614836 TX Vref Scan disable
1641 23:14:28.614915 == TX Byte 0 ==
1642 23:14:28.620972 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1643 23:14:28.624538 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1644 23:14:28.624619 == TX Byte 1 ==
1645 23:14:28.631489 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1646 23:14:28.634572 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1647 23:14:28.634651 ==
1648 23:14:28.638014 Dram Type= 6, Freq= 0, CH_1, rank 0
1649 23:14:28.641639 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1650 23:14:28.641718 ==
1651 23:14:28.655686 TX Vref=22, minBit 1, minWin=26, winSum=432
1652 23:14:28.658854 TX Vref=24, minBit 9, minWin=26, winSum=436
1653 23:14:28.662491 TX Vref=26, minBit 2, minWin=27, winSum=444
1654 23:14:28.665946 TX Vref=28, minBit 0, minWin=27, winSum=442
1655 23:14:28.669239 TX Vref=30, minBit 2, minWin=27, winSum=448
1656 23:14:28.672175 TX Vref=32, minBit 1, minWin=27, winSum=446
1657 23:14:28.679283 [TxChooseVref] Worse bit 2, Min win 27, Win sum 448, Final Vref 30
1658 23:14:28.679363
1659 23:14:28.682554 Final TX Range 1 Vref 30
1660 23:14:28.682634
1661 23:14:28.682696 ==
1662 23:14:28.686159 Dram Type= 6, Freq= 0, CH_1, rank 0
1663 23:14:28.689297 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1664 23:14:28.689378 ==
1665 23:14:28.689440
1666 23:14:28.689498
1667 23:14:28.692412 TX Vref Scan disable
1668 23:14:28.695905 == TX Byte 0 ==
1669 23:14:28.699247 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1670 23:14:28.702521 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1671 23:14:28.705932 == TX Byte 1 ==
1672 23:14:28.709543 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1673 23:14:28.712652 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1674 23:14:28.712757
1675 23:14:28.716528 [DATLAT]
1676 23:14:28.716631 Freq=800, CH1 RK0
1677 23:14:28.716708
1678 23:14:28.719506 DATLAT Default: 0xa
1679 23:14:28.719586 0, 0xFFFF, sum = 0
1680 23:14:28.723152 1, 0xFFFF, sum = 0
1681 23:14:28.723232 2, 0xFFFF, sum = 0
1682 23:14:28.726146 3, 0xFFFF, sum = 0
1683 23:14:28.726227 4, 0xFFFF, sum = 0
1684 23:14:28.729382 5, 0xFFFF, sum = 0
1685 23:14:28.729464 6, 0xFFFF, sum = 0
1686 23:14:28.733122 7, 0xFFFF, sum = 0
1687 23:14:28.733224 8, 0xFFFF, sum = 0
1688 23:14:28.736424 9, 0x0, sum = 1
1689 23:14:28.736508 10, 0x0, sum = 2
1690 23:14:28.739867 11, 0x0, sum = 3
1691 23:14:28.739937 12, 0x0, sum = 4
1692 23:14:28.742846 best_step = 10
1693 23:14:28.742915
1694 23:14:28.742972 ==
1695 23:14:28.746506 Dram Type= 6, Freq= 0, CH_1, rank 0
1696 23:14:28.749432 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1697 23:14:28.749557 ==
1698 23:14:28.749668 RX Vref Scan: 1
1699 23:14:28.749771
1700 23:14:28.753077 Set Vref Range= 32 -> 127
1701 23:14:28.753194
1702 23:14:28.756089 RX Vref 32 -> 127, step: 1
1703 23:14:28.756210
1704 23:14:28.759612 RX Delay -79 -> 252, step: 8
1705 23:14:28.759730
1706 23:14:28.762854 Set Vref, RX VrefLevel [Byte0]: 32
1707 23:14:28.766349 [Byte1]: 32
1708 23:14:28.766469
1709 23:14:28.769774 Set Vref, RX VrefLevel [Byte0]: 33
1710 23:14:28.773229 [Byte1]: 33
1711 23:14:28.773341
1712 23:14:28.776685 Set Vref, RX VrefLevel [Byte0]: 34
1713 23:14:28.779747 [Byte1]: 34
1714 23:14:28.783317
1715 23:14:28.783435 Set Vref, RX VrefLevel [Byte0]: 35
1716 23:14:28.786430 [Byte1]: 35
1717 23:14:28.790545
1718 23:14:28.790661 Set Vref, RX VrefLevel [Byte0]: 36
1719 23:14:28.794076 [Byte1]: 36
1720 23:14:28.798222
1721 23:14:28.798341 Set Vref, RX VrefLevel [Byte0]: 37
1722 23:14:28.801811 [Byte1]: 37
1723 23:14:28.806157
1724 23:14:28.806275 Set Vref, RX VrefLevel [Byte0]: 38
1725 23:14:28.809072 [Byte1]: 38
1726 23:14:28.813031
1727 23:14:28.813146 Set Vref, RX VrefLevel [Byte0]: 39
1728 23:14:28.816792 [Byte1]: 39
1729 23:14:28.820817
1730 23:14:28.820933 Set Vref, RX VrefLevel [Byte0]: 40
1731 23:14:28.824387 [Byte1]: 40
1732 23:14:28.828242
1733 23:14:28.828393 Set Vref, RX VrefLevel [Byte0]: 41
1734 23:14:28.831616 [Byte1]: 41
1735 23:14:28.836031
1736 23:14:28.836143 Set Vref, RX VrefLevel [Byte0]: 42
1737 23:14:28.839511 [Byte1]: 42
1738 23:14:28.843751
1739 23:14:28.843869 Set Vref, RX VrefLevel [Byte0]: 43
1740 23:14:28.846857 [Byte1]: 43
1741 23:14:28.850961
1742 23:14:28.851080 Set Vref, RX VrefLevel [Byte0]: 44
1743 23:14:28.854925 [Byte1]: 44
1744 23:14:28.858685
1745 23:14:28.858802 Set Vref, RX VrefLevel [Byte0]: 45
1746 23:14:28.862228 [Byte1]: 45
1747 23:14:28.866641
1748 23:14:28.866758 Set Vref, RX VrefLevel [Byte0]: 46
1749 23:14:28.869471 [Byte1]: 46
1750 23:14:28.873819
1751 23:14:28.873933 Set Vref, RX VrefLevel [Byte0]: 47
1752 23:14:28.877065 [Byte1]: 47
1753 23:14:28.881170
1754 23:14:28.881291 Set Vref, RX VrefLevel [Byte0]: 48
1755 23:14:28.884712 [Byte1]: 48
1756 23:14:28.889010
1757 23:14:28.889130 Set Vref, RX VrefLevel [Byte0]: 49
1758 23:14:28.892214 [Byte1]: 49
1759 23:14:28.896567
1760 23:14:28.896682 Set Vref, RX VrefLevel [Byte0]: 50
1761 23:14:28.899980 [Byte1]: 50
1762 23:14:28.904064
1763 23:14:28.904179 Set Vref, RX VrefLevel [Byte0]: 51
1764 23:14:28.907022 [Byte1]: 51
1765 23:14:28.911458
1766 23:14:28.911576 Set Vref, RX VrefLevel [Byte0]: 52
1767 23:14:28.915100 [Byte1]: 52
1768 23:14:28.918807
1769 23:14:28.918925 Set Vref, RX VrefLevel [Byte0]: 53
1770 23:14:28.922568 [Byte1]: 53
1771 23:14:28.926702
1772 23:14:28.926820 Set Vref, RX VrefLevel [Byte0]: 54
1773 23:14:28.929651 [Byte1]: 54
1774 23:14:28.933870
1775 23:14:28.933989 Set Vref, RX VrefLevel [Byte0]: 55
1776 23:14:28.937502 [Byte1]: 55
1777 23:14:28.941537
1778 23:14:28.941657 Set Vref, RX VrefLevel [Byte0]: 56
1779 23:14:28.944763 [Byte1]: 56
1780 23:14:28.948918
1781 23:14:28.949037 Set Vref, RX VrefLevel [Byte0]: 57
1782 23:14:28.952717 [Byte1]: 57
1783 23:14:28.956695
1784 23:14:28.956849 Set Vref, RX VrefLevel [Byte0]: 58
1785 23:14:28.960059 [Byte1]: 58
1786 23:14:28.964371
1787 23:14:28.964486 Set Vref, RX VrefLevel [Byte0]: 59
1788 23:14:28.967328 [Byte1]: 59
1789 23:14:28.971818
1790 23:14:28.971936 Set Vref, RX VrefLevel [Byte0]: 60
1791 23:14:28.975368 [Byte1]: 60
1792 23:14:28.979619
1793 23:14:28.979737 Set Vref, RX VrefLevel [Byte0]: 61
1794 23:14:28.982415 [Byte1]: 61
1795 23:14:28.987206
1796 23:14:28.987323 Set Vref, RX VrefLevel [Byte0]: 62
1797 23:14:28.989997 [Byte1]: 62
1798 23:14:28.994246
1799 23:14:28.994363 Set Vref, RX VrefLevel [Byte0]: 63
1800 23:14:28.998119 [Byte1]: 63
1801 23:14:29.002113
1802 23:14:29.002231 Set Vref, RX VrefLevel [Byte0]: 64
1803 23:14:29.005530 [Byte1]: 64
1804 23:14:29.009533
1805 23:14:29.009612 Set Vref, RX VrefLevel [Byte0]: 65
1806 23:14:29.012955 [Byte1]: 65
1807 23:14:29.017173
1808 23:14:29.017252 Set Vref, RX VrefLevel [Byte0]: 66
1809 23:14:29.020196 [Byte1]: 66
1810 23:14:29.024555
1811 23:14:29.024634 Set Vref, RX VrefLevel [Byte0]: 67
1812 23:14:29.028045 [Byte1]: 67
1813 23:14:29.032218
1814 23:14:29.032355 Set Vref, RX VrefLevel [Byte0]: 68
1815 23:14:29.035730 [Byte1]: 68
1816 23:14:29.040067
1817 23:14:29.040172 Set Vref, RX VrefLevel [Byte0]: 69
1818 23:14:29.043018 [Byte1]: 69
1819 23:14:29.047388
1820 23:14:29.047470 Set Vref, RX VrefLevel [Byte0]: 70
1821 23:14:29.050356 [Byte1]: 70
1822 23:14:29.055027
1823 23:14:29.055131 Set Vref, RX VrefLevel [Byte0]: 71
1824 23:14:29.058511 [Byte1]: 71
1825 23:14:29.062317
1826 23:14:29.062439 Set Vref, RX VrefLevel [Byte0]: 72
1827 23:14:29.065770 [Byte1]: 72
1828 23:14:29.069981
1829 23:14:29.070098 Final RX Vref Byte 0 = 56 to rank0
1830 23:14:29.073191 Final RX Vref Byte 1 = 54 to rank0
1831 23:14:29.076505 Final RX Vref Byte 0 = 56 to rank1
1832 23:14:29.080061 Final RX Vref Byte 1 = 54 to rank1==
1833 23:14:29.083072 Dram Type= 6, Freq= 0, CH_1, rank 0
1834 23:14:29.089692 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1835 23:14:29.089815 ==
1836 23:14:29.089927 DQS Delay:
1837 23:14:29.090033 DQS0 = 0, DQS1 = 0
1838 23:14:29.093296 DQM Delay:
1839 23:14:29.093413 DQM0 = 95, DQM1 = 89
1840 23:14:29.096550 DQ Delay:
1841 23:14:29.099933 DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =92
1842 23:14:29.103101 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =92
1843 23:14:29.106734 DQ8 =80, DQ9 =80, DQ10 =88, DQ11 =84
1844 23:14:29.109667 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
1845 23:14:29.109786
1846 23:14:29.109893
1847 23:14:29.116763 [DQSOSCAuto] RK0, (LSB)MR18= 0x304c, (MSB)MR19= 0x606, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
1848 23:14:29.120062 CH1 RK0: MR19=606, MR18=304C
1849 23:14:29.126913 CH1_RK0: MR19=0x606, MR18=0x304C, DQSOSC=390, MR23=63, INC=97, DEC=64
1850 23:14:29.127033
1851 23:14:29.129901 ----->DramcWriteLeveling(PI) begin...
1852 23:14:29.130022 ==
1853 23:14:29.133598 Dram Type= 6, Freq= 0, CH_1, rank 1
1854 23:14:29.136567 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1855 23:14:29.136688 ==
1856 23:14:29.140135 Write leveling (Byte 0): 27 => 27
1857 23:14:29.143754 Write leveling (Byte 1): 27 => 27
1858 23:14:29.146942 DramcWriteLeveling(PI) end<-----
1859 23:14:29.147061
1860 23:14:29.147168 ==
1861 23:14:29.149959 Dram Type= 6, Freq= 0, CH_1, rank 1
1862 23:14:29.153677 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1863 23:14:29.153795 ==
1864 23:14:29.156681 [Gating] SW mode calibration
1865 23:14:29.163478 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1866 23:14:29.170266 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1867 23:14:29.173219 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1868 23:14:29.176910 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1869 23:14:29.183109 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1870 23:14:29.186577 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1871 23:14:29.190011 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1872 23:14:29.196897 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1873 23:14:29.200012 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 23:14:29.203443 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 23:14:29.210090 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 23:14:29.213727 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 23:14:29.216936 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 23:14:29.220644 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 23:14:29.226771 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 23:14:29.230160 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 23:14:29.233884 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 23:14:29.240565 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1883 23:14:29.243933 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1884 23:14:29.247513 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1885 23:14:29.254256 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 23:14:29.257208 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 23:14:29.260810 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 23:14:29.267268 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 23:14:29.270988 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 23:14:29.273930 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 23:14:29.277063 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 23:14:29.283843 0 9 4 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
1893 23:14:29.287563 0 9 8 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
1894 23:14:29.290784 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1895 23:14:29.297198 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1896 23:14:29.300614 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1897 23:14:29.304542 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1898 23:14:29.310745 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1899 23:14:29.314100 0 10 0 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
1900 23:14:29.317250 0 10 4 | B1->B0 | 2c2c 2f2f | 0 1 | (1 1) (1 0)
1901 23:14:29.324212 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1902 23:14:29.327381 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1903 23:14:29.330792 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1904 23:14:29.337815 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1905 23:14:29.340584 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1906 23:14:29.344027 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1907 23:14:29.350541 0 11 0 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1908 23:14:29.354071 0 11 4 | B1->B0 | 3a3a 2929 | 0 0 | (0 0) (0 0)
1909 23:14:29.357197 0 11 8 | B1->B0 | 4646 4242 | 0 0 | (0 0) (0 0)
1910 23:14:29.360681 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1911 23:14:29.367307 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1912 23:14:29.370751 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1913 23:14:29.374323 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1914 23:14:29.381155 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1915 23:14:29.384132 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1916 23:14:29.387697 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1917 23:14:29.394320 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1918 23:14:29.397326 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1919 23:14:29.400508 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1920 23:14:29.407145 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1921 23:14:29.410811 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1922 23:14:29.413949 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1923 23:14:29.420820 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1924 23:14:29.424083 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1925 23:14:29.427315 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1926 23:14:29.434120 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1927 23:14:29.437621 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1928 23:14:29.440830 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1929 23:14:29.447762 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1930 23:14:29.450780 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1931 23:14:29.454205 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1932 23:14:29.457165 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1933 23:14:29.463947 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1934 23:14:29.467527 Total UI for P1: 0, mck2ui 16
1935 23:14:29.470755 best dqsien dly found for B1: ( 0, 14, 4)
1936 23:14:29.474068 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1937 23:14:29.477753 Total UI for P1: 0, mck2ui 16
1938 23:14:29.480775 best dqsien dly found for B0: ( 0, 14, 6)
1939 23:14:29.483891 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1940 23:14:29.487697 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1941 23:14:29.487817
1942 23:14:29.490637 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1943 23:14:29.494352 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1944 23:14:29.497532 [Gating] SW calibration Done
1945 23:14:29.497651 ==
1946 23:14:29.501162 Dram Type= 6, Freq= 0, CH_1, rank 1
1947 23:14:29.504226 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1948 23:14:29.507319 ==
1949 23:14:29.507419 RX Vref Scan: 0
1950 23:14:29.507509
1951 23:14:29.511103 RX Vref 0 -> 0, step: 1
1952 23:14:29.511198
1953 23:14:29.514018 RX Delay -130 -> 252, step: 16
1954 23:14:29.517721 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1955 23:14:29.520734 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1956 23:14:29.524590 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1957 23:14:29.527604 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1958 23:14:29.534421 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1959 23:14:29.537689 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1960 23:14:29.540996 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1961 23:14:29.544058 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1962 23:14:29.547442 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1963 23:14:29.550968 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1964 23:14:29.557531 iDelay=222, Bit 10, Center 93 (-18 ~ 205) 224
1965 23:14:29.561253 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1966 23:14:29.564205 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1967 23:14:29.567907 iDelay=222, Bit 13, Center 101 (-2 ~ 205) 208
1968 23:14:29.574437 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1969 23:14:29.577448 iDelay=222, Bit 15, Center 101 (-2 ~ 205) 208
1970 23:14:29.577568 ==
1971 23:14:29.580752 Dram Type= 6, Freq= 0, CH_1, rank 1
1972 23:14:29.584197 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1973 23:14:29.584323 ==
1974 23:14:29.584404 DQS Delay:
1975 23:14:29.587638 DQS0 = 0, DQS1 = 0
1976 23:14:29.587757 DQM Delay:
1977 23:14:29.591100 DQM0 = 92, DQM1 = 89
1978 23:14:29.591204 DQ Delay:
1979 23:14:29.594141 DQ0 =101, DQ1 =85, DQ2 =77, DQ3 =85
1980 23:14:29.597775 DQ4 =85, DQ5 =109, DQ6 =101, DQ7 =93
1981 23:14:29.600925 DQ8 =77, DQ9 =77, DQ10 =93, DQ11 =77
1982 23:14:29.604538 DQ12 =93, DQ13 =101, DQ14 =93, DQ15 =101
1983 23:14:29.604617
1984 23:14:29.604679
1985 23:14:29.604737 ==
1986 23:14:29.607592 Dram Type= 6, Freq= 0, CH_1, rank 1
1987 23:14:29.614428 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1988 23:14:29.614554 ==
1989 23:14:29.614662
1990 23:14:29.614769
1991 23:14:29.614873 TX Vref Scan disable
1992 23:14:29.617607 == TX Byte 0 ==
1993 23:14:29.621280 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1994 23:14:29.624235 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1995 23:14:29.627917 == TX Byte 1 ==
1996 23:14:29.631129 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1997 23:14:29.634633 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1998 23:14:29.637736 ==
1999 23:14:29.641227 Dram Type= 6, Freq= 0, CH_1, rank 1
2000 23:14:29.644845 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2001 23:14:29.644965 ==
2002 23:14:29.656938 TX Vref=22, minBit 3, minWin=26, winSum=442
2003 23:14:29.660405 TX Vref=24, minBit 0, minWin=27, winSum=442
2004 23:14:29.663510 TX Vref=26, minBit 1, minWin=27, winSum=448
2005 23:14:29.666723 TX Vref=28, minBit 2, minWin=27, winSum=448
2006 23:14:29.669802 TX Vref=30, minBit 2, minWin=27, winSum=449
2007 23:14:29.673452 TX Vref=32, minBit 2, minWin=27, winSum=448
2008 23:14:29.680181 [TxChooseVref] Worse bit 2, Min win 27, Win sum 449, Final Vref 30
2009 23:14:29.680303
2010 23:14:29.683149 Final TX Range 1 Vref 30
2011 23:14:29.683270
2012 23:14:29.683380 ==
2013 23:14:29.686736 Dram Type= 6, Freq= 0, CH_1, rank 1
2014 23:14:29.689927 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2015 23:14:29.690044 ==
2016 23:14:29.690153
2017 23:14:29.690260
2018 23:14:29.693484 TX Vref Scan disable
2019 23:14:29.697164 == TX Byte 0 ==
2020 23:14:29.699913 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2021 23:14:29.703535 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2022 23:14:29.707007 == TX Byte 1 ==
2023 23:14:29.709873 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
2024 23:14:29.713356 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
2025 23:14:29.713477
2026 23:14:29.716581 [DATLAT]
2027 23:14:29.716700 Freq=800, CH1 RK1
2028 23:14:29.716808
2029 23:14:29.720263 DATLAT Default: 0xa
2030 23:14:29.720421 0, 0xFFFF, sum = 0
2031 23:14:29.723263 1, 0xFFFF, sum = 0
2032 23:14:29.723385 2, 0xFFFF, sum = 0
2033 23:14:29.726910 3, 0xFFFF, sum = 0
2034 23:14:29.727031 4, 0xFFFF, sum = 0
2035 23:14:29.730468 5, 0xFFFF, sum = 0
2036 23:14:29.730590 6, 0xFFFF, sum = 0
2037 23:14:29.733703 7, 0xFFFF, sum = 0
2038 23:14:29.733822 8, 0xFFFF, sum = 0
2039 23:14:29.736747 9, 0x0, sum = 1
2040 23:14:29.736872 10, 0x0, sum = 2
2041 23:14:29.740321 11, 0x0, sum = 3
2042 23:14:29.740442 12, 0x0, sum = 4
2043 23:14:29.743284 best_step = 10
2044 23:14:29.743399
2045 23:14:29.743507 ==
2046 23:14:29.747043 Dram Type= 6, Freq= 0, CH_1, rank 1
2047 23:14:29.750457 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2048 23:14:29.750577 ==
2049 23:14:29.753979 RX Vref Scan: 0
2050 23:14:29.754094
2051 23:14:29.754208 RX Vref 0 -> 0, step: 1
2052 23:14:29.754369
2053 23:14:29.756895 RX Delay -79 -> 252, step: 8
2054 23:14:29.763526 iDelay=209, Bit 0, Center 104 (9 ~ 200) 192
2055 23:14:29.767113 iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200
2056 23:14:29.770275 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
2057 23:14:29.773608 iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200
2058 23:14:29.777126 iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200
2059 23:14:29.780824 iDelay=209, Bit 5, Center 108 (9 ~ 208) 200
2060 23:14:29.786701 iDelay=209, Bit 6, Center 108 (9 ~ 208) 200
2061 23:14:29.790394 iDelay=209, Bit 7, Center 96 (-7 ~ 200) 208
2062 23:14:29.793353 iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208
2063 23:14:29.797079 iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208
2064 23:14:29.800392 iDelay=209, Bit 10, Center 96 (-7 ~ 200) 208
2065 23:14:29.803598 iDelay=209, Bit 11, Center 88 (-15 ~ 192) 208
2066 23:14:29.810441 iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216
2067 23:14:29.813455 iDelay=209, Bit 13, Center 96 (-7 ~ 200) 208
2068 23:14:29.817029 iDelay=209, Bit 14, Center 96 (-7 ~ 200) 208
2069 23:14:29.820583 iDelay=209, Bit 15, Center 96 (-7 ~ 200) 208
2070 23:14:29.820700 ==
2071 23:14:29.823563 Dram Type= 6, Freq= 0, CH_1, rank 1
2072 23:14:29.830506 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2073 23:14:29.830629 ==
2074 23:14:29.830739 DQS Delay:
2075 23:14:29.830847 DQS0 = 0, DQS1 = 0
2076 23:14:29.833562 DQM Delay:
2077 23:14:29.833680 DQM0 = 97, DQM1 = 91
2078 23:14:29.836662 DQ Delay:
2079 23:14:29.840196 DQ0 =104, DQ1 =92, DQ2 =84, DQ3 =92
2080 23:14:29.843335 DQ4 =92, DQ5 =108, DQ6 =108, DQ7 =96
2081 23:14:29.846964 DQ8 =80, DQ9 =80, DQ10 =96, DQ11 =88
2082 23:14:29.850581 DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =96
2083 23:14:29.850701
2084 23:14:29.850811
2085 23:14:29.857279 [DQSOSCAuto] RK1, (LSB)MR18= 0x440e, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 392 ps
2086 23:14:29.860086 CH1 RK1: MR19=606, MR18=440E
2087 23:14:29.866989 CH1_RK1: MR19=0x606, MR18=0x440E, DQSOSC=392, MR23=63, INC=96, DEC=64
2088 23:14:29.870562 [RxdqsGatingPostProcess] freq 800
2089 23:14:29.873948 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2090 23:14:29.877083 Pre-setting of DQS Precalculation
2091 23:14:29.883851 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2092 23:14:29.890437 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2093 23:14:29.897324 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2094 23:14:29.897446
2095 23:14:29.897557
2096 23:14:29.900512 [Calibration Summary] 1600 Mbps
2097 23:14:29.900632 CH 0, Rank 0
2098 23:14:29.904000 SW Impedance : PASS
2099 23:14:29.906984 DUTY Scan : NO K
2100 23:14:29.907103 ZQ Calibration : PASS
2101 23:14:29.910610 Jitter Meter : NO K
2102 23:14:29.913726 CBT Training : PASS
2103 23:14:29.913847 Write leveling : PASS
2104 23:14:29.917351 RX DQS gating : PASS
2105 23:14:29.917469 RX DQ/DQS(RDDQC) : PASS
2106 23:14:29.920464 TX DQ/DQS : PASS
2107 23:14:29.924193 RX DATLAT : PASS
2108 23:14:29.924311 RX DQ/DQS(Engine): PASS
2109 23:14:29.927287 TX OE : NO K
2110 23:14:29.927405 All Pass.
2111 23:14:29.927515
2112 23:14:29.931025 CH 0, Rank 1
2113 23:14:29.931144 SW Impedance : PASS
2114 23:14:29.934002 DUTY Scan : NO K
2115 23:14:29.937501 ZQ Calibration : PASS
2116 23:14:29.937621 Jitter Meter : NO K
2117 23:14:29.940477 CBT Training : PASS
2118 23:14:29.944045 Write leveling : PASS
2119 23:14:29.944161 RX DQS gating : PASS
2120 23:14:29.946913 RX DQ/DQS(RDDQC) : PASS
2121 23:14:29.950504 TX DQ/DQS : PASS
2122 23:14:29.950587 RX DATLAT : PASS
2123 23:14:29.953713 RX DQ/DQS(Engine): PASS
2124 23:14:29.956901 TX OE : NO K
2125 23:14:29.956981 All Pass.
2126 23:14:29.957044
2127 23:14:29.957102 CH 1, Rank 0
2128 23:14:29.960489 SW Impedance : PASS
2129 23:14:29.960569 DUTY Scan : NO K
2130 23:14:29.964157 ZQ Calibration : PASS
2131 23:14:29.967251 Jitter Meter : NO K
2132 23:14:29.967332 CBT Training : PASS
2133 23:14:29.970501 Write leveling : PASS
2134 23:14:29.973699 RX DQS gating : PASS
2135 23:14:29.973779 RX DQ/DQS(RDDQC) : PASS
2136 23:14:29.977088 TX DQ/DQS : PASS
2137 23:14:29.980582 RX DATLAT : PASS
2138 23:14:29.980662 RX DQ/DQS(Engine): PASS
2139 23:14:29.983873 TX OE : NO K
2140 23:14:29.983953 All Pass.
2141 23:14:29.984016
2142 23:14:29.986931 CH 1, Rank 1
2143 23:14:29.987011 SW Impedance : PASS
2144 23:14:29.990529 DUTY Scan : NO K
2145 23:14:29.993551 ZQ Calibration : PASS
2146 23:14:29.993631 Jitter Meter : NO K
2147 23:14:29.996906 CBT Training : PASS
2148 23:14:30.000546 Write leveling : PASS
2149 23:14:30.000626 RX DQS gating : PASS
2150 23:14:30.003595 RX DQ/DQS(RDDQC) : PASS
2151 23:14:30.003675 TX DQ/DQS : PASS
2152 23:14:30.007444 RX DATLAT : PASS
2153 23:14:30.010263 RX DQ/DQS(Engine): PASS
2154 23:14:30.010375 TX OE : NO K
2155 23:14:30.013785 All Pass.
2156 23:14:30.013865
2157 23:14:30.013927 DramC Write-DBI off
2158 23:14:30.016980 PER_BANK_REFRESH: Hybrid Mode
2159 23:14:30.020467 TX_TRACKING: ON
2160 23:14:30.023670 [GetDramInforAfterCalByMRR] Vendor 6.
2161 23:14:30.026832 [GetDramInforAfterCalByMRR] Revision 606.
2162 23:14:30.030410 [GetDramInforAfterCalByMRR] Revision 2 0.
2163 23:14:30.030490 MR0 0x3b3b
2164 23:14:30.030553 MR8 0x5151
2165 23:14:30.036906 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2166 23:14:30.036986
2167 23:14:30.037049 MR0 0x3b3b
2168 23:14:30.037107 MR8 0x5151
2169 23:14:30.040559 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2170 23:14:30.040639
2171 23:14:30.050532 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2172 23:14:30.053576 [FAST_K] Save calibration result to emmc
2173 23:14:30.057189 [FAST_K] Save calibration result to emmc
2174 23:14:30.060102 dram_init: config_dvfs: 1
2175 23:14:30.063892 dramc_set_vcore_voltage set vcore to 662500
2176 23:14:30.066835 Read voltage for 1200, 2
2177 23:14:30.066915 Vio18 = 0
2178 23:14:30.066977 Vcore = 662500
2179 23:14:30.070131 Vdram = 0
2180 23:14:30.070210 Vddq = 0
2181 23:14:30.070273 Vmddr = 0
2182 23:14:30.076858 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2183 23:14:30.080397 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2184 23:14:30.083607 MEM_TYPE=3, freq_sel=15
2185 23:14:30.087089 sv_algorithm_assistance_LP4_1600
2186 23:14:30.090510 ============ PULL DRAM RESETB DOWN ============
2187 23:14:30.093763 ========== PULL DRAM RESETB DOWN end =========
2188 23:14:30.100507 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2189 23:14:30.104038 ===================================
2190 23:14:30.104117 LPDDR4 DRAM CONFIGURATION
2191 23:14:30.107596 ===================================
2192 23:14:30.110633 EX_ROW_EN[0] = 0x0
2193 23:14:30.114021 EX_ROW_EN[1] = 0x0
2194 23:14:30.114120 LP4Y_EN = 0x0
2195 23:14:30.117039 WORK_FSP = 0x0
2196 23:14:30.117119 WL = 0x4
2197 23:14:30.120656 RL = 0x4
2198 23:14:30.120736 BL = 0x2
2199 23:14:30.123773 RPST = 0x0
2200 23:14:30.123853 RD_PRE = 0x0
2201 23:14:30.126987 WR_PRE = 0x1
2202 23:14:30.127067 WR_PST = 0x0
2203 23:14:30.130521 DBI_WR = 0x0
2204 23:14:30.130602 DBI_RD = 0x0
2205 23:14:30.133660 OTF = 0x1
2206 23:14:30.137270 ===================================
2207 23:14:30.140333 ===================================
2208 23:14:30.140426 ANA top config
2209 23:14:30.143870 ===================================
2210 23:14:30.147460 DLL_ASYNC_EN = 0
2211 23:14:30.150441 ALL_SLAVE_EN = 0
2212 23:14:30.153860 NEW_RANK_MODE = 1
2213 23:14:30.153943 DLL_IDLE_MODE = 1
2214 23:14:30.156792 LP45_APHY_COMB_EN = 1
2215 23:14:30.160298 TX_ODT_DIS = 1
2216 23:14:30.163418 NEW_8X_MODE = 1
2217 23:14:30.167155 ===================================
2218 23:14:30.170264 ===================================
2219 23:14:30.173792 data_rate = 2400
2220 23:14:30.173872 CKR = 1
2221 23:14:30.177137 DQ_P2S_RATIO = 8
2222 23:14:30.180321 ===================================
2223 23:14:30.183684 CA_P2S_RATIO = 8
2224 23:14:30.187292 DQ_CA_OPEN = 0
2225 23:14:30.190234 DQ_SEMI_OPEN = 0
2226 23:14:30.190314 CA_SEMI_OPEN = 0
2227 23:14:30.193646 CA_FULL_RATE = 0
2228 23:14:30.197163 DQ_CKDIV4_EN = 0
2229 23:14:30.200739 CA_CKDIV4_EN = 0
2230 23:14:30.203562 CA_PREDIV_EN = 0
2231 23:14:30.206929 PH8_DLY = 17
2232 23:14:30.207009 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2233 23:14:30.210110 DQ_AAMCK_DIV = 4
2234 23:14:30.213802 CA_AAMCK_DIV = 4
2235 23:14:30.217004 CA_ADMCK_DIV = 4
2236 23:14:30.220266 DQ_TRACK_CA_EN = 0
2237 23:14:30.223577 CA_PICK = 1200
2238 23:14:30.227131 CA_MCKIO = 1200
2239 23:14:30.227210 MCKIO_SEMI = 0
2240 23:14:30.230203 PLL_FREQ = 2366
2241 23:14:30.233998 DQ_UI_PI_RATIO = 32
2242 23:14:30.237043 CA_UI_PI_RATIO = 0
2243 23:14:30.240648 ===================================
2244 23:14:30.243538 ===================================
2245 23:14:30.247338 memory_type:LPDDR4
2246 23:14:30.247418 GP_NUM : 10
2247 23:14:30.250355 SRAM_EN : 1
2248 23:14:30.250435 MD32_EN : 0
2249 23:14:30.253907 ===================================
2250 23:14:30.257539 [ANA_INIT] >>>>>>>>>>>>>>
2251 23:14:30.260463 <<<<<< [CONFIGURE PHASE]: ANA_TX
2252 23:14:30.264111 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2253 23:14:30.267242 ===================================
2254 23:14:30.270346 data_rate = 2400,PCW = 0X5b00
2255 23:14:30.274126 ===================================
2256 23:14:30.277154 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2257 23:14:30.283835 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2258 23:14:30.287315 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2259 23:14:30.293674 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2260 23:14:30.297131 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2261 23:14:30.300489 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2262 23:14:30.300569 [ANA_INIT] flow start
2263 23:14:30.303885 [ANA_INIT] PLL >>>>>>>>
2264 23:14:30.307357 [ANA_INIT] PLL <<<<<<<<
2265 23:14:30.307437 [ANA_INIT] MIDPI >>>>>>>>
2266 23:14:30.310815 [ANA_INIT] MIDPI <<<<<<<<
2267 23:14:30.313523 [ANA_INIT] DLL >>>>>>>>
2268 23:14:30.313629 [ANA_INIT] DLL <<<<<<<<
2269 23:14:30.317000 [ANA_INIT] flow end
2270 23:14:30.320781 ============ LP4 DIFF to SE enter ============
2271 23:14:30.323677 ============ LP4 DIFF to SE exit ============
2272 23:14:30.326947 [ANA_INIT] <<<<<<<<<<<<<
2273 23:14:30.330271 [Flow] Enable top DCM control >>>>>
2274 23:14:30.333703 [Flow] Enable top DCM control <<<<<
2275 23:14:30.336993 Enable DLL master slave shuffle
2276 23:14:30.343893 ==============================================================
2277 23:14:30.343974 Gating Mode config
2278 23:14:30.350286 ==============================================================
2279 23:14:30.350366 Config description:
2280 23:14:30.360415 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2281 23:14:30.367025 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2282 23:14:30.373709 SELPH_MODE 0: By rank 1: By Phase
2283 23:14:30.377302 ==============================================================
2284 23:14:30.380413 GAT_TRACK_EN = 1
2285 23:14:30.384141 RX_GATING_MODE = 2
2286 23:14:30.387191 RX_GATING_TRACK_MODE = 2
2287 23:14:30.390955 SELPH_MODE = 1
2288 23:14:30.394060 PICG_EARLY_EN = 1
2289 23:14:30.397825 VALID_LAT_VALUE = 1
2290 23:14:30.400913 ==============================================================
2291 23:14:30.404199 Enter into Gating configuration >>>>
2292 23:14:30.407580 Exit from Gating configuration <<<<
2293 23:14:30.410751 Enter into DVFS_PRE_config >>>>>
2294 23:14:30.424060 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2295 23:14:30.427929 Exit from DVFS_PRE_config <<<<<
2296 23:14:30.431021 Enter into PICG configuration >>>>
2297 23:14:30.431101 Exit from PICG configuration <<<<
2298 23:14:30.434378 [RX_INPUT] configuration >>>>>
2299 23:14:30.437549 [RX_INPUT] configuration <<<<<
2300 23:14:30.444566 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2301 23:14:30.447815 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2302 23:14:30.454404 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2303 23:14:30.461226 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2304 23:14:30.468147 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2305 23:14:30.474288 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2306 23:14:30.478147 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2307 23:14:30.481065 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2308 23:14:30.484784 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2309 23:14:30.491614 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2310 23:14:30.494674 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2311 23:14:30.497822 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2312 23:14:30.500939 ===================================
2313 23:14:30.504695 LPDDR4 DRAM CONFIGURATION
2314 23:14:30.507649 ===================================
2315 23:14:30.507729 EX_ROW_EN[0] = 0x0
2316 23:14:30.511555 EX_ROW_EN[1] = 0x0
2317 23:14:30.514425 LP4Y_EN = 0x0
2318 23:14:30.514504 WORK_FSP = 0x0
2319 23:14:30.518182 WL = 0x4
2320 23:14:30.518261 RL = 0x4
2321 23:14:30.521212 BL = 0x2
2322 23:14:30.521292 RPST = 0x0
2323 23:14:30.524587 RD_PRE = 0x0
2324 23:14:30.524668 WR_PRE = 0x1
2325 23:14:30.527891 WR_PST = 0x0
2326 23:14:30.527971 DBI_WR = 0x0
2327 23:14:30.531045 DBI_RD = 0x0
2328 23:14:30.531125 OTF = 0x1
2329 23:14:30.534699 ===================================
2330 23:14:30.538159 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2331 23:14:30.544684 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2332 23:14:30.548176 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2333 23:14:30.551412 ===================================
2334 23:14:30.554620 LPDDR4 DRAM CONFIGURATION
2335 23:14:30.558137 ===================================
2336 23:14:30.558217 EX_ROW_EN[0] = 0x10
2337 23:14:30.561387 EX_ROW_EN[1] = 0x0
2338 23:14:30.561466 LP4Y_EN = 0x0
2339 23:14:30.565029 WORK_FSP = 0x0
2340 23:14:30.565109 WL = 0x4
2341 23:14:30.568113 RL = 0x4
2342 23:14:30.568218 BL = 0x2
2343 23:14:30.571349 RPST = 0x0
2344 23:14:30.571429 RD_PRE = 0x0
2345 23:14:30.574809 WR_PRE = 0x1
2346 23:14:30.574889 WR_PST = 0x0
2347 23:14:30.578083 DBI_WR = 0x0
2348 23:14:30.578163 DBI_RD = 0x0
2349 23:14:30.581833 OTF = 0x1
2350 23:14:30.585059 ===================================
2351 23:14:30.591241 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2352 23:14:30.591323 ==
2353 23:14:30.594993 Dram Type= 6, Freq= 0, CH_0, rank 0
2354 23:14:30.598045 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2355 23:14:30.598127 ==
2356 23:14:30.601675 [Duty_Offset_Calibration]
2357 23:14:30.601755 B0:2 B1:1 CA:1
2358 23:14:30.601821
2359 23:14:30.604752 [DutyScan_Calibration_Flow] k_type=0
2360 23:14:30.615167
2361 23:14:30.615247 ==CLK 0==
2362 23:14:30.618820 Final CLK duty delay cell = 0
2363 23:14:30.621929 [0] MAX Duty = 5156%(X100), DQS PI = 22
2364 23:14:30.625530 [0] MIN Duty = 4844%(X100), DQS PI = 48
2365 23:14:30.625610 [0] AVG Duty = 5000%(X100)
2366 23:14:30.628591
2367 23:14:30.628669 CH0 CLK Duty spec in!! Max-Min= 312%
2368 23:14:30.635284 [DutyScan_Calibration_Flow] ====Done====
2369 23:14:30.635362
2370 23:14:30.638284 [DutyScan_Calibration_Flow] k_type=1
2371 23:14:30.653093
2372 23:14:30.653199 ==DQS 0 ==
2373 23:14:30.656250 Final DQS duty delay cell = -4
2374 23:14:30.659881 [-4] MAX Duty = 5124%(X100), DQS PI = 24
2375 23:14:30.663190 [-4] MIN Duty = 4782%(X100), DQS PI = 62
2376 23:14:30.666613 [-4] AVG Duty = 4953%(X100)
2377 23:14:30.666693
2378 23:14:30.666755 ==DQS 1 ==
2379 23:14:30.669730 Final DQS duty delay cell = -4
2380 23:14:30.672874 [-4] MAX Duty = 4969%(X100), DQS PI = 0
2381 23:14:30.676522 [-4] MIN Duty = 4844%(X100), DQS PI = 32
2382 23:14:30.680028 [-4] AVG Duty = 4906%(X100)
2383 23:14:30.680107
2384 23:14:30.683330 CH0 DQS 0 Duty spec in!! Max-Min= 342%
2385 23:14:30.683410
2386 23:14:30.686667 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2387 23:14:30.689693 [DutyScan_Calibration_Flow] ====Done====
2388 23:14:30.689772
2389 23:14:30.693409 [DutyScan_Calibration_Flow] k_type=3
2390 23:14:30.710543
2391 23:14:30.710621 ==DQM 0 ==
2392 23:14:30.713636 Final DQM duty delay cell = 0
2393 23:14:30.716687 [0] MAX Duty = 5156%(X100), DQS PI = 30
2394 23:14:30.720244 [0] MIN Duty = 4906%(X100), DQS PI = 58
2395 23:14:30.720369 [0] AVG Duty = 5031%(X100)
2396 23:14:30.723363
2397 23:14:30.723441 ==DQM 1 ==
2398 23:14:30.726896 Final DQM duty delay cell = 0
2399 23:14:30.730645 [0] MAX Duty = 5093%(X100), DQS PI = 0
2400 23:14:30.733636 [0] MIN Duty = 5031%(X100), DQS PI = 36
2401 23:14:30.733716 [0] AVG Duty = 5062%(X100)
2402 23:14:30.737347
2403 23:14:30.740515 CH0 DQM 0 Duty spec in!! Max-Min= 250%
2404 23:14:30.740595
2405 23:14:30.743510 CH0 DQM 1 Duty spec in!! Max-Min= 62%
2406 23:14:30.747130 [DutyScan_Calibration_Flow] ====Done====
2407 23:14:30.747212
2408 23:14:30.750091 [DutyScan_Calibration_Flow] k_type=2
2409 23:14:30.766676
2410 23:14:30.766755 ==DQ 0 ==
2411 23:14:30.770020 Final DQ duty delay cell = 0
2412 23:14:30.773180 [0] MAX Duty = 5031%(X100), DQS PI = 24
2413 23:14:30.776833 [0] MIN Duty = 4875%(X100), DQS PI = 62
2414 23:14:30.776912 [0] AVG Duty = 4953%(X100)
2415 23:14:30.776974
2416 23:14:30.779671 ==DQ 1 ==
2417 23:14:30.783499 Final DQ duty delay cell = 0
2418 23:14:30.786597 [0] MAX Duty = 5093%(X100), DQS PI = 24
2419 23:14:30.790206 [0] MIN Duty = 4907%(X100), DQS PI = 36
2420 23:14:30.790286 [0] AVG Duty = 5000%(X100)
2421 23:14:30.790347
2422 23:14:30.793324 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2423 23:14:30.796594
2424 23:14:30.799774 CH0 DQ 1 Duty spec in!! Max-Min= 186%
2425 23:14:30.803316 [DutyScan_Calibration_Flow] ====Done====
2426 23:14:30.803395 ==
2427 23:14:30.806613 Dram Type= 6, Freq= 0, CH_1, rank 0
2428 23:14:30.809805 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2429 23:14:30.809885 ==
2430 23:14:30.813326 [Duty_Offset_Calibration]
2431 23:14:30.813405 B0:1 B1:0 CA:0
2432 23:14:30.813468
2433 23:14:30.816586 [DutyScan_Calibration_Flow] k_type=0
2434 23:14:30.826192
2435 23:14:30.826270 ==CLK 0==
2436 23:14:30.829255 Final CLK duty delay cell = -4
2437 23:14:30.832473 [-4] MAX Duty = 5000%(X100), DQS PI = 20
2438 23:14:30.836170 [-4] MIN Duty = 4907%(X100), DQS PI = 48
2439 23:14:30.839319 [-4] AVG Duty = 4953%(X100)
2440 23:14:30.839398
2441 23:14:30.842392 CH1 CLK Duty spec in!! Max-Min= 93%
2442 23:14:30.846199 [DutyScan_Calibration_Flow] ====Done====
2443 23:14:30.846278
2444 23:14:30.849240 [DutyScan_Calibration_Flow] k_type=1
2445 23:14:30.866003
2446 23:14:30.866082 ==DQS 0 ==
2447 23:14:30.868767 Final DQS duty delay cell = 0
2448 23:14:30.872430 [0] MAX Duty = 5062%(X100), DQS PI = 12
2449 23:14:30.875532 [0] MIN Duty = 4844%(X100), DQS PI = 0
2450 23:14:30.875611 [0] AVG Duty = 4953%(X100)
2451 23:14:30.879078
2452 23:14:30.879158 ==DQS 1 ==
2453 23:14:30.882716 Final DQS duty delay cell = 0
2454 23:14:30.885945 [0] MAX Duty = 5187%(X100), DQS PI = 18
2455 23:14:30.889200 [0] MIN Duty = 4969%(X100), DQS PI = 10
2456 23:14:30.889280 [0] AVG Duty = 5078%(X100)
2457 23:14:30.892427
2458 23:14:30.895639 CH1 DQS 0 Duty spec in!! Max-Min= 218%
2459 23:14:30.895719
2460 23:14:30.898849 CH1 DQS 1 Duty spec in!! Max-Min= 218%
2461 23:14:30.902498 [DutyScan_Calibration_Flow] ====Done====
2462 23:14:30.902579
2463 23:14:30.905623 [DutyScan_Calibration_Flow] k_type=3
2464 23:14:30.922327
2465 23:14:30.922422 ==DQM 0 ==
2466 23:14:30.925676 Final DQM duty delay cell = 0
2467 23:14:30.928865 [0] MAX Duty = 5156%(X100), DQS PI = 8
2468 23:14:30.932033 [0] MIN Duty = 5031%(X100), DQS PI = 0
2469 23:14:30.932112 [0] AVG Duty = 5093%(X100)
2470 23:14:30.932175
2471 23:14:30.935959 ==DQM 1 ==
2472 23:14:30.938873 Final DQM duty delay cell = 0
2473 23:14:30.942642 [0] MAX Duty = 5031%(X100), DQS PI = 18
2474 23:14:30.945719 [0] MIN Duty = 4907%(X100), DQS PI = 36
2475 23:14:30.945800 [0] AVG Duty = 4969%(X100)
2476 23:14:30.945863
2477 23:14:30.952638 CH1 DQM 0 Duty spec in!! Max-Min= 125%
2478 23:14:30.952717
2479 23:14:30.955548 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2480 23:14:30.959193 [DutyScan_Calibration_Flow] ====Done====
2481 23:14:30.959273
2482 23:14:30.962313 [DutyScan_Calibration_Flow] k_type=2
2483 23:14:30.978015
2484 23:14:30.978095 ==DQ 0 ==
2485 23:14:30.981251 Final DQ duty delay cell = -4
2486 23:14:30.984726 [-4] MAX Duty = 5062%(X100), DQS PI = 8
2487 23:14:30.987829 [-4] MIN Duty = 4906%(X100), DQS PI = 46
2488 23:14:30.991376 [-4] AVG Duty = 4984%(X100)
2489 23:14:30.991455
2490 23:14:30.991527 ==DQ 1 ==
2491 23:14:30.994931 Final DQ duty delay cell = 0
2492 23:14:30.997921 [0] MAX Duty = 5125%(X100), DQS PI = 20
2493 23:14:31.001293 [0] MIN Duty = 4969%(X100), DQS PI = 10
2494 23:14:31.001374 [0] AVG Duty = 5047%(X100)
2495 23:14:31.004866
2496 23:14:31.008401 CH1 DQ 0 Duty spec in!! Max-Min= 156%
2497 23:14:31.008482
2498 23:14:31.011053 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2499 23:14:31.014477 [DutyScan_Calibration_Flow] ====Done====
2500 23:14:31.017751 nWR fixed to 30
2501 23:14:31.017832 [ModeRegInit_LP4] CH0 RK0
2502 23:14:31.021068 [ModeRegInit_LP4] CH0 RK1
2503 23:14:31.024237 [ModeRegInit_LP4] CH1 RK0
2504 23:14:31.027865 [ModeRegInit_LP4] CH1 RK1
2505 23:14:31.027945 match AC timing 7
2506 23:14:31.031494 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2507 23:14:31.038184 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2508 23:14:31.041273 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2509 23:14:31.044955 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2510 23:14:31.051645 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2511 23:14:31.051726 ==
2512 23:14:31.054903 Dram Type= 6, Freq= 0, CH_0, rank 0
2513 23:14:31.058371 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2514 23:14:31.058452 ==
2515 23:14:31.064554 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2516 23:14:31.071300 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2517 23:14:31.078061 [CA 0] Center 39 (8~70) winsize 63
2518 23:14:31.081645 [CA 1] Center 39 (8~70) winsize 63
2519 23:14:31.085112 [CA 2] Center 35 (5~66) winsize 62
2520 23:14:31.088475 [CA 3] Center 34 (4~65) winsize 62
2521 23:14:31.091836 [CA 4] Center 33 (3~64) winsize 62
2522 23:14:31.094876 [CA 5] Center 32 (3~62) winsize 60
2523 23:14:31.094956
2524 23:14:31.098583 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2525 23:14:31.098664
2526 23:14:31.101249 [CATrainingPosCal] consider 1 rank data
2527 23:14:31.104712 u2DelayCellTimex100 = 270/100 ps
2528 23:14:31.108251 CA0 delay=39 (8~70),Diff = 7 PI (33 cell)
2529 23:14:31.111703 CA1 delay=39 (8~70),Diff = 7 PI (33 cell)
2530 23:14:31.118054 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2531 23:14:31.121678 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2532 23:14:31.124628 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2533 23:14:31.127994 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2534 23:14:31.128100
2535 23:14:31.131683 CA PerBit enable=1, Macro0, CA PI delay=32
2536 23:14:31.131765
2537 23:14:31.134824 [CBTSetCACLKResult] CA Dly = 32
2538 23:14:31.134905 CS Dly: 6 (0~37)
2539 23:14:31.134968 ==
2540 23:14:31.138269 Dram Type= 6, Freq= 0, CH_0, rank 1
2541 23:14:31.144965 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2542 23:14:31.145047 ==
2543 23:14:31.148226 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2544 23:14:31.154628 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2545 23:14:31.164174 [CA 0] Center 38 (8~69) winsize 62
2546 23:14:31.167205 [CA 1] Center 38 (8~69) winsize 62
2547 23:14:31.170361 [CA 2] Center 35 (5~66) winsize 62
2548 23:14:31.174125 [CA 3] Center 34 (4~65) winsize 62
2549 23:14:31.177022 [CA 4] Center 33 (3~64) winsize 62
2550 23:14:31.180696 [CA 5] Center 32 (2~62) winsize 61
2551 23:14:31.180817
2552 23:14:31.183754 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2553 23:14:31.183873
2554 23:14:31.187380 [CATrainingPosCal] consider 2 rank data
2555 23:14:31.190259 u2DelayCellTimex100 = 270/100 ps
2556 23:14:31.194069 CA0 delay=38 (8~69),Diff = 6 PI (28 cell)
2557 23:14:31.197253 CA1 delay=38 (8~69),Diff = 6 PI (28 cell)
2558 23:14:31.204068 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2559 23:14:31.207261 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2560 23:14:31.210614 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2561 23:14:31.214056 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2562 23:14:31.214178
2563 23:14:31.217172 CA PerBit enable=1, Macro0, CA PI delay=32
2564 23:14:31.217274
2565 23:14:31.220410 [CBTSetCACLKResult] CA Dly = 32
2566 23:14:31.220508 CS Dly: 6 (0~38)
2567 23:14:31.220595
2568 23:14:31.223617 ----->DramcWriteLeveling(PI) begin...
2569 23:14:31.227092 ==
2570 23:14:31.230720 Dram Type= 6, Freq= 0, CH_0, rank 0
2571 23:14:31.233928 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2572 23:14:31.234010 ==
2573 23:14:31.237368 Write leveling (Byte 0): 32 => 32
2574 23:14:31.240810 Write leveling (Byte 1): 30 => 30
2575 23:14:31.243936 DramcWriteLeveling(PI) end<-----
2576 23:14:31.244016
2577 23:14:31.244079 ==
2578 23:14:31.247142 Dram Type= 6, Freq= 0, CH_0, rank 0
2579 23:14:31.251025 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2580 23:14:31.251106 ==
2581 23:14:31.254057 [Gating] SW mode calibration
2582 23:14:31.260826 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2583 23:14:31.264150 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2584 23:14:31.270883 0 15 0 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
2585 23:14:31.273786 0 15 4 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
2586 23:14:31.277578 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2587 23:14:31.284099 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2588 23:14:31.287242 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2589 23:14:31.290910 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2590 23:14:31.297443 0 15 24 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 1)
2591 23:14:31.300585 0 15 28 | B1->B0 | 3434 2424 | 1 0 | (1 1) (0 0)
2592 23:14:31.304097 1 0 0 | B1->B0 | 2a2a 2323 | 0 0 | (0 1) (0 0)
2593 23:14:31.310816 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2594 23:14:31.314522 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2595 23:14:31.317446 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2596 23:14:31.320904 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2597 23:14:31.327413 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2598 23:14:31.331078 1 0 24 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
2599 23:14:31.334125 1 0 28 | B1->B0 | 2727 4646 | 0 0 | (0 0) (0 0)
2600 23:14:31.340869 1 1 0 | B1->B0 | 3434 4646 | 0 0 | (0 0) (0 0)
2601 23:14:31.344566 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2602 23:14:31.347782 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2603 23:14:31.354245 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2604 23:14:31.357454 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2605 23:14:31.360885 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2606 23:14:31.367517 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2607 23:14:31.371295 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2608 23:14:31.374330 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2609 23:14:31.381063 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2610 23:14:31.384203 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2611 23:14:31.388029 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2612 23:14:31.394716 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2613 23:14:31.397652 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2614 23:14:31.401235 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2615 23:14:31.404431 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2616 23:14:31.411106 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2617 23:14:31.414723 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2618 23:14:31.417956 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2619 23:14:31.424623 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2620 23:14:31.427763 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2621 23:14:31.431282 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2622 23:14:31.437840 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2623 23:14:31.441480 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2624 23:14:31.444716 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2625 23:14:31.448204 Total UI for P1: 0, mck2ui 16
2626 23:14:31.451294 best dqsien dly found for B0: ( 1, 3, 26)
2627 23:14:31.457989 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2628 23:14:31.458072 Total UI for P1: 0, mck2ui 16
2629 23:14:31.461647 best dqsien dly found for B1: ( 1, 4, 0)
2630 23:14:31.467902 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2631 23:14:31.471097 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2632 23:14:31.471180
2633 23:14:31.474556 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2634 23:14:31.478251 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2635 23:14:31.481361 [Gating] SW calibration Done
2636 23:14:31.481444 ==
2637 23:14:31.484498 Dram Type= 6, Freq= 0, CH_0, rank 0
2638 23:14:31.488341 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2639 23:14:31.488424 ==
2640 23:14:31.488508 RX Vref Scan: 0
2641 23:14:31.491303
2642 23:14:31.491385 RX Vref 0 -> 0, step: 1
2643 23:14:31.491469
2644 23:14:31.495147 RX Delay -40 -> 252, step: 8
2645 23:14:31.498445 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2646 23:14:31.501540 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2647 23:14:31.507915 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2648 23:14:31.511522 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2649 23:14:31.515128 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2650 23:14:31.518338 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2651 23:14:31.521203 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2652 23:14:31.528547 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2653 23:14:31.531549 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2654 23:14:31.535053 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
2655 23:14:31.538307 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2656 23:14:31.541688 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2657 23:14:31.548442 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2658 23:14:31.551365 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2659 23:14:31.554784 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2660 23:14:31.558396 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2661 23:14:31.558478 ==
2662 23:14:31.561543 Dram Type= 6, Freq= 0, CH_0, rank 0
2663 23:14:31.564897 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2664 23:14:31.568025 ==
2665 23:14:31.568108 DQS Delay:
2666 23:14:31.568208 DQS0 = 0, DQS1 = 0
2667 23:14:31.571507 DQM Delay:
2668 23:14:31.571589 DQM0 = 121, DQM1 = 113
2669 23:14:31.574863 DQ Delay:
2670 23:14:31.578376 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2671 23:14:31.581387 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2672 23:14:31.585111 DQ8 =99, DQ9 =107, DQ10 =111, DQ11 =107
2673 23:14:31.588174 DQ12 =115, DQ13 =123, DQ14 =123, DQ15 =119
2674 23:14:31.588283
2675 23:14:31.588388
2676 23:14:31.588486 ==
2677 23:14:31.591931 Dram Type= 6, Freq= 0, CH_0, rank 0
2678 23:14:31.595050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2679 23:14:31.595132 ==
2680 23:14:31.595216
2681 23:14:31.595295
2682 23:14:31.598096 TX Vref Scan disable
2683 23:14:31.601839 == TX Byte 0 ==
2684 23:14:31.604960 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2685 23:14:31.608090 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2686 23:14:31.611532 == TX Byte 1 ==
2687 23:14:31.615194 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2688 23:14:31.618270 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2689 23:14:31.618404 ==
2690 23:14:31.621465 Dram Type= 6, Freq= 0, CH_0, rank 0
2691 23:14:31.625057 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2692 23:14:31.628210 ==
2693 23:14:31.638436 TX Vref=22, minBit 0, minWin=25, winSum=409
2694 23:14:31.641576 TX Vref=24, minBit 0, minWin=25, winSum=412
2695 23:14:31.645203 TX Vref=26, minBit 0, minWin=26, winSum=423
2696 23:14:31.648194 TX Vref=28, minBit 13, minWin=25, winSum=426
2697 23:14:31.651573 TX Vref=30, minBit 3, minWin=26, winSum=429
2698 23:14:31.658299 TX Vref=32, minBit 12, minWin=25, winSum=421
2699 23:14:31.661807 [TxChooseVref] Worse bit 3, Min win 26, Win sum 429, Final Vref 30
2700 23:14:31.661915
2701 23:14:31.665083 Final TX Range 1 Vref 30
2702 23:14:31.665166
2703 23:14:31.665250 ==
2704 23:14:31.668611 Dram Type= 6, Freq= 0, CH_0, rank 0
2705 23:14:31.671535 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2706 23:14:31.674661 ==
2707 23:14:31.674744
2708 23:14:31.674827
2709 23:14:31.674906 TX Vref Scan disable
2710 23:14:31.678464 == TX Byte 0 ==
2711 23:14:31.681729 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2712 23:14:31.684742 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2713 23:14:31.688472 == TX Byte 1 ==
2714 23:14:31.691529 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2715 23:14:31.695133 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2716 23:14:31.698243
2717 23:14:31.698324 [DATLAT]
2718 23:14:31.698408 Freq=1200, CH0 RK0
2719 23:14:31.698488
2720 23:14:31.701833 DATLAT Default: 0xd
2721 23:14:31.701938 0, 0xFFFF, sum = 0
2722 23:14:31.704935 1, 0xFFFF, sum = 0
2723 23:14:31.705019 2, 0xFFFF, sum = 0
2724 23:14:31.708075 3, 0xFFFF, sum = 0
2725 23:14:31.711783 4, 0xFFFF, sum = 0
2726 23:14:31.711866 5, 0xFFFF, sum = 0
2727 23:14:31.714759 6, 0xFFFF, sum = 0
2728 23:14:31.714842 7, 0xFFFF, sum = 0
2729 23:14:31.718352 8, 0xFFFF, sum = 0
2730 23:14:31.718438 9, 0xFFFF, sum = 0
2731 23:14:31.721994 10, 0xFFFF, sum = 0
2732 23:14:31.722078 11, 0xFFFF, sum = 0
2733 23:14:31.725027 12, 0x0, sum = 1
2734 23:14:31.725111 13, 0x0, sum = 2
2735 23:14:31.728261 14, 0x0, sum = 3
2736 23:14:31.728378 15, 0x0, sum = 4
2737 23:14:31.728480 best_step = 13
2738 23:14:31.728577
2739 23:14:31.731340 ==
2740 23:14:31.735208 Dram Type= 6, Freq= 0, CH_0, rank 0
2741 23:14:31.738483 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2742 23:14:31.738566 ==
2743 23:14:31.738650 RX Vref Scan: 1
2744 23:14:31.738747
2745 23:14:31.741878 Set Vref Range= 32 -> 127
2746 23:14:31.741961
2747 23:14:31.744850 RX Vref 32 -> 127, step: 1
2748 23:14:31.744932
2749 23:14:31.748625 RX Delay -13 -> 252, step: 4
2750 23:14:31.748707
2751 23:14:31.751619 Set Vref, RX VrefLevel [Byte0]: 32
2752 23:14:31.754841 [Byte1]: 32
2753 23:14:31.754924
2754 23:14:31.758576 Set Vref, RX VrefLevel [Byte0]: 33
2755 23:14:31.761520 [Byte1]: 33
2756 23:14:31.761603
2757 23:14:31.765006 Set Vref, RX VrefLevel [Byte0]: 34
2758 23:14:31.768578 [Byte1]: 34
2759 23:14:31.772690
2760 23:14:31.772797 Set Vref, RX VrefLevel [Byte0]: 35
2761 23:14:31.775652 [Byte1]: 35
2762 23:14:31.780672
2763 23:14:31.780754 Set Vref, RX VrefLevel [Byte0]: 36
2764 23:14:31.783683 [Byte1]: 36
2765 23:14:31.788448
2766 23:14:31.788530 Set Vref, RX VrefLevel [Byte0]: 37
2767 23:14:31.791462 [Byte1]: 37
2768 23:14:31.796206
2769 23:14:31.796350 Set Vref, RX VrefLevel [Byte0]: 38
2770 23:14:31.799323 [Byte1]: 38
2771 23:14:31.803955
2772 23:14:31.804037 Set Vref, RX VrefLevel [Byte0]: 39
2773 23:14:31.807631 [Byte1]: 39
2774 23:14:31.812258
2775 23:14:31.812364 Set Vref, RX VrefLevel [Byte0]: 40
2776 23:14:31.815408 [Byte1]: 40
2777 23:14:31.819891
2778 23:14:31.819973 Set Vref, RX VrefLevel [Byte0]: 41
2779 23:14:31.823525 [Byte1]: 41
2780 23:14:31.827702
2781 23:14:31.827784 Set Vref, RX VrefLevel [Byte0]: 42
2782 23:14:31.831271 [Byte1]: 42
2783 23:14:31.835636
2784 23:14:31.835718 Set Vref, RX VrefLevel [Byte0]: 43
2785 23:14:31.839268 [Byte1]: 43
2786 23:14:31.843459
2787 23:14:31.843541 Set Vref, RX VrefLevel [Byte0]: 44
2788 23:14:31.847034 [Byte1]: 44
2789 23:14:31.851835
2790 23:14:31.851917 Set Vref, RX VrefLevel [Byte0]: 45
2791 23:14:31.854883 [Byte1]: 45
2792 23:14:31.859124
2793 23:14:31.859207 Set Vref, RX VrefLevel [Byte0]: 46
2794 23:14:31.862692 [Byte1]: 46
2795 23:14:31.866997
2796 23:14:31.867103 Set Vref, RX VrefLevel [Byte0]: 47
2797 23:14:31.870532 [Byte1]: 47
2798 23:14:31.875165
2799 23:14:31.875248 Set Vref, RX VrefLevel [Byte0]: 48
2800 23:14:31.878945 [Byte1]: 48
2801 23:14:31.883180
2802 23:14:31.883261 Set Vref, RX VrefLevel [Byte0]: 49
2803 23:14:31.886307 [Byte1]: 49
2804 23:14:31.890874
2805 23:14:31.890956 Set Vref, RX VrefLevel [Byte0]: 50
2806 23:14:31.894205 [Byte1]: 50
2807 23:14:31.899035
2808 23:14:31.899121 Set Vref, RX VrefLevel [Byte0]: 51
2809 23:14:31.901946 [Byte1]: 51
2810 23:14:31.906539
2811 23:14:31.906621 Set Vref, RX VrefLevel [Byte0]: 52
2812 23:14:31.909864 [Byte1]: 52
2813 23:14:31.914784
2814 23:14:31.914867 Set Vref, RX VrefLevel [Byte0]: 53
2815 23:14:31.918055 [Byte1]: 53
2816 23:14:31.922457
2817 23:14:31.922539 Set Vref, RX VrefLevel [Byte0]: 54
2818 23:14:31.926027 [Byte1]: 54
2819 23:14:31.930229
2820 23:14:31.930311 Set Vref, RX VrefLevel [Byte0]: 55
2821 23:14:31.933515 [Byte1]: 55
2822 23:14:31.938406
2823 23:14:31.938486 Set Vref, RX VrefLevel [Byte0]: 56
2824 23:14:31.941544 [Byte1]: 56
2825 23:14:31.945903
2826 23:14:31.945984 Set Vref, RX VrefLevel [Byte0]: 57
2827 23:14:31.949543 [Byte1]: 57
2828 23:14:31.953796
2829 23:14:31.953876 Set Vref, RX VrefLevel [Byte0]: 58
2830 23:14:31.957291 [Byte1]: 58
2831 23:14:31.961622
2832 23:14:31.961703 Set Vref, RX VrefLevel [Byte0]: 59
2833 23:14:31.965430 [Byte1]: 59
2834 23:14:31.969979
2835 23:14:31.970059 Set Vref, RX VrefLevel [Byte0]: 60
2836 23:14:31.973025 [Byte1]: 60
2837 23:14:31.977626
2838 23:14:31.977707 Set Vref, RX VrefLevel [Byte0]: 61
2839 23:14:31.981174 [Byte1]: 61
2840 23:14:31.985384
2841 23:14:31.985465 Set Vref, RX VrefLevel [Byte0]: 62
2842 23:14:31.989147 [Byte1]: 62
2843 23:14:31.993539
2844 23:14:31.993620 Set Vref, RX VrefLevel [Byte0]: 63
2845 23:14:31.997078 [Byte1]: 63
2846 23:14:32.001277
2847 23:14:32.001358 Set Vref, RX VrefLevel [Byte0]: 64
2848 23:14:32.004650 [Byte1]: 64
2849 23:14:32.009329
2850 23:14:32.009409 Set Vref, RX VrefLevel [Byte0]: 65
2851 23:14:32.012271 [Byte1]: 65
2852 23:14:32.017259
2853 23:14:32.017365 Set Vref, RX VrefLevel [Byte0]: 66
2854 23:14:32.020548 [Byte1]: 66
2855 23:14:32.025174
2856 23:14:32.025254 Set Vref, RX VrefLevel [Byte0]: 67
2857 23:14:32.028579 [Byte1]: 67
2858 23:14:32.033034
2859 23:14:32.033114 Set Vref, RX VrefLevel [Byte0]: 68
2860 23:14:32.036185 [Byte1]: 68
2861 23:14:32.041087
2862 23:14:32.041168 Set Vref, RX VrefLevel [Byte0]: 69
2863 23:14:32.044201 [Byte1]: 69
2864 23:14:32.049071
2865 23:14:32.049152 Set Vref, RX VrefLevel [Byte0]: 70
2866 23:14:32.052216 [Byte1]: 70
2867 23:14:32.057036
2868 23:14:32.057117 Final RX Vref Byte 0 = 55 to rank0
2869 23:14:32.060054 Final RX Vref Byte 1 = 49 to rank0
2870 23:14:32.063735 Final RX Vref Byte 0 = 55 to rank1
2871 23:14:32.066720 Final RX Vref Byte 1 = 49 to rank1==
2872 23:14:32.070336 Dram Type= 6, Freq= 0, CH_0, rank 0
2873 23:14:32.073438 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2874 23:14:32.076607 ==
2875 23:14:32.076694 DQS Delay:
2876 23:14:32.076759 DQS0 = 0, DQS1 = 0
2877 23:14:32.080215 DQM Delay:
2878 23:14:32.080367 DQM0 = 120, DQM1 = 111
2879 23:14:32.083492 DQ Delay:
2880 23:14:32.086906 DQ0 =120, DQ1 =120, DQ2 =118, DQ3 =118
2881 23:14:32.090529 DQ4 =122, DQ5 =112, DQ6 =126, DQ7 =126
2882 23:14:32.093581 DQ8 =98, DQ9 =102, DQ10 =112, DQ11 =106
2883 23:14:32.096754 DQ12 =116, DQ13 =116, DQ14 =124, DQ15 =118
2884 23:14:32.096878
2885 23:14:32.096990
2886 23:14:32.103556 [DQSOSCAuto] RK0, (LSB)MR18= 0x130d, (MSB)MR19= 0x404, tDQSOscB0 = 405 ps tDQSOscB1 = 402 ps
2887 23:14:32.107251 CH0 RK0: MR19=404, MR18=130D
2888 23:14:32.113324 CH0_RK0: MR19=0x404, MR18=0x130D, DQSOSC=402, MR23=63, INC=40, DEC=27
2889 23:14:32.113427
2890 23:14:32.117033 ----->DramcWriteLeveling(PI) begin...
2891 23:14:32.117142 ==
2892 23:14:32.120577 Dram Type= 6, Freq= 0, CH_0, rank 1
2893 23:14:32.123670 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2894 23:14:32.123752 ==
2895 23:14:32.126842 Write leveling (Byte 0): 34 => 34
2896 23:14:32.130592 Write leveling (Byte 1): 28 => 28
2897 23:14:32.133632 DramcWriteLeveling(PI) end<-----
2898 23:14:32.133713
2899 23:14:32.133776 ==
2900 23:14:32.136853 Dram Type= 6, Freq= 0, CH_0, rank 1
2901 23:14:32.140480 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2902 23:14:32.143796 ==
2903 23:14:32.143877 [Gating] SW mode calibration
2904 23:14:32.150859 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2905 23:14:32.157151 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2906 23:14:32.160562 0 15 0 | B1->B0 | 3434 3131 | 0 1 | (0 0) (1 1)
2907 23:14:32.167077 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2908 23:14:32.170944 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2909 23:14:32.173795 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2910 23:14:32.180461 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2911 23:14:32.184119 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2912 23:14:32.187459 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
2913 23:14:32.190731 0 15 28 | B1->B0 | 2f2f 2d2d | 0 0 | (1 0) (0 0)
2914 23:14:32.197103 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2915 23:14:32.200612 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2916 23:14:32.204172 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2917 23:14:32.210885 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2918 23:14:32.213868 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2919 23:14:32.217544 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2920 23:14:32.224201 1 0 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
2921 23:14:32.227455 1 0 28 | B1->B0 | 3b3b 3e3e | 0 1 | (0 0) (0 0)
2922 23:14:32.230640 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2923 23:14:32.237114 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2924 23:14:32.240588 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2925 23:14:32.244225 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2926 23:14:32.250842 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2927 23:14:32.254130 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2928 23:14:32.257153 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2929 23:14:32.264014 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2930 23:14:32.267538 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2931 23:14:32.270889 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2932 23:14:32.274413 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2933 23:14:32.280580 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2934 23:14:32.284349 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2935 23:14:32.287531 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2936 23:14:32.294249 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2937 23:14:32.297648 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2938 23:14:32.301078 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2939 23:14:32.307509 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2940 23:14:32.311234 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2941 23:14:32.314394 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2942 23:14:32.320862 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2943 23:14:32.324642 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2944 23:14:32.327626 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2945 23:14:32.334468 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2946 23:14:32.337703 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2947 23:14:32.341228 Total UI for P1: 0, mck2ui 16
2948 23:14:32.344883 best dqsien dly found for B0: ( 1, 3, 28)
2949 23:14:32.347919 Total UI for P1: 0, mck2ui 16
2950 23:14:32.351322 best dqsien dly found for B1: ( 1, 3, 28)
2951 23:14:32.354353 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2952 23:14:32.357758 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2953 23:14:32.357839
2954 23:14:32.361305 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2955 23:14:32.364898 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2956 23:14:32.367909 [Gating] SW calibration Done
2957 23:14:32.367998 ==
2958 23:14:32.371509 Dram Type= 6, Freq= 0, CH_0, rank 1
2959 23:14:32.374548 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2960 23:14:32.374630 ==
2961 23:14:32.378088 RX Vref Scan: 0
2962 23:14:32.378169
2963 23:14:32.378233 RX Vref 0 -> 0, step: 1
2964 23:14:32.378292
2965 23:14:32.381509 RX Delay -40 -> 252, step: 8
2966 23:14:32.387740 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2967 23:14:32.391513 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2968 23:14:32.394231 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2969 23:14:32.397749 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2970 23:14:32.401359 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2971 23:14:32.404541 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2972 23:14:32.411238 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2973 23:14:32.414534 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2974 23:14:32.418213 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2975 23:14:32.421501 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
2976 23:14:32.424587 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2977 23:14:32.431466 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2978 23:14:32.434554 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2979 23:14:32.437634 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2980 23:14:32.441280 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2981 23:14:32.447996 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
2982 23:14:32.448077 ==
2983 23:14:32.450978 Dram Type= 6, Freq= 0, CH_0, rank 1
2984 23:14:32.454524 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2985 23:14:32.454605 ==
2986 23:14:32.454669 DQS Delay:
2987 23:14:32.458026 DQS0 = 0, DQS1 = 0
2988 23:14:32.458106 DQM Delay:
2989 23:14:32.461100 DQM0 = 121, DQM1 = 112
2990 23:14:32.461181 DQ Delay:
2991 23:14:32.464610 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =119
2992 23:14:32.467963 DQ4 =127, DQ5 =115, DQ6 =127, DQ7 =127
2993 23:14:32.471412 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
2994 23:14:32.474357 DQ12 =115, DQ13 =119, DQ14 =123, DQ15 =123
2995 23:14:32.474438
2996 23:14:32.474503
2997 23:14:32.474561 ==
2998 23:14:32.478145 Dram Type= 6, Freq= 0, CH_0, rank 1
2999 23:14:32.484225 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3000 23:14:32.484344 ==
3001 23:14:32.484409
3002 23:14:32.484468
3003 23:14:32.484524 TX Vref Scan disable
3004 23:14:32.487885 == TX Byte 0 ==
3005 23:14:32.491560 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
3006 23:14:32.495081 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
3007 23:14:32.497934 == TX Byte 1 ==
3008 23:14:32.501144 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3009 23:14:32.504673 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3010 23:14:32.508255 ==
3011 23:14:32.511301 Dram Type= 6, Freq= 0, CH_0, rank 1
3012 23:14:32.514410 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3013 23:14:32.514491 ==
3014 23:14:32.526581 TX Vref=22, minBit 1, minWin=25, winSum=417
3015 23:14:32.529906 TX Vref=24, minBit 1, minWin=25, winSum=420
3016 23:14:32.533317 TX Vref=26, minBit 3, minWin=25, winSum=425
3017 23:14:32.536113 TX Vref=28, minBit 1, minWin=26, winSum=431
3018 23:14:32.539664 TX Vref=30, minBit 1, minWin=26, winSum=432
3019 23:14:32.546020 TX Vref=32, minBit 0, minWin=26, winSum=431
3020 23:14:32.549674 [TxChooseVref] Worse bit 1, Min win 26, Win sum 432, Final Vref 30
3021 23:14:32.549754
3022 23:14:32.553181 Final TX Range 1 Vref 30
3023 23:14:32.553262
3024 23:14:32.553325 ==
3025 23:14:32.556084 Dram Type= 6, Freq= 0, CH_0, rank 1
3026 23:14:32.559382 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3027 23:14:32.562797 ==
3028 23:14:32.562877
3029 23:14:32.562940
3030 23:14:32.562997 TX Vref Scan disable
3031 23:14:32.566481 == TX Byte 0 ==
3032 23:14:32.569489 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
3033 23:14:32.573202 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
3034 23:14:32.576580 == TX Byte 1 ==
3035 23:14:32.579560 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3036 23:14:32.582705 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3037 23:14:32.586333
3038 23:14:32.586413 [DATLAT]
3039 23:14:32.586476 Freq=1200, CH0 RK1
3040 23:14:32.586534
3041 23:14:32.589426 DATLAT Default: 0xd
3042 23:14:32.589527 0, 0xFFFF, sum = 0
3043 23:14:32.592984 1, 0xFFFF, sum = 0
3044 23:14:32.593065 2, 0xFFFF, sum = 0
3045 23:14:32.596211 3, 0xFFFF, sum = 0
3046 23:14:32.596354 4, 0xFFFF, sum = 0
3047 23:14:32.599817 5, 0xFFFF, sum = 0
3048 23:14:32.602951 6, 0xFFFF, sum = 0
3049 23:14:32.603059 7, 0xFFFF, sum = 0
3050 23:14:32.606639 8, 0xFFFF, sum = 0
3051 23:14:32.606720 9, 0xFFFF, sum = 0
3052 23:14:32.609538 10, 0xFFFF, sum = 0
3053 23:14:32.609620 11, 0xFFFF, sum = 0
3054 23:14:32.612793 12, 0x0, sum = 1
3055 23:14:32.612874 13, 0x0, sum = 2
3056 23:14:32.616369 14, 0x0, sum = 3
3057 23:14:32.616450 15, 0x0, sum = 4
3058 23:14:32.616514 best_step = 13
3059 23:14:32.616572
3060 23:14:32.619771 ==
3061 23:14:32.622833 Dram Type= 6, Freq= 0, CH_0, rank 1
3062 23:14:32.626600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3063 23:14:32.626680 ==
3064 23:14:32.626744 RX Vref Scan: 0
3065 23:14:32.626803
3066 23:14:32.629899 RX Vref 0 -> 0, step: 1
3067 23:14:32.629980
3068 23:14:32.633338 RX Delay -13 -> 252, step: 4
3069 23:14:32.636731 iDelay=195, Bit 0, Center 120 (51 ~ 190) 140
3070 23:14:32.642823 iDelay=195, Bit 1, Center 120 (55 ~ 186) 132
3071 23:14:32.646272 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3072 23:14:32.649622 iDelay=195, Bit 3, Center 118 (51 ~ 186) 136
3073 23:14:32.652965 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3074 23:14:32.656518 iDelay=195, Bit 5, Center 116 (51 ~ 182) 132
3075 23:14:32.659802 iDelay=195, Bit 6, Center 128 (63 ~ 194) 132
3076 23:14:32.666420 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3077 23:14:32.669735 iDelay=195, Bit 8, Center 100 (35 ~ 166) 132
3078 23:14:32.673084 iDelay=195, Bit 9, Center 100 (35 ~ 166) 132
3079 23:14:32.676661 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3080 23:14:32.679690 iDelay=195, Bit 11, Center 102 (39 ~ 166) 128
3081 23:14:32.686381 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3082 23:14:32.690096 iDelay=195, Bit 13, Center 116 (55 ~ 178) 124
3083 23:14:32.693116 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3084 23:14:32.696823 iDelay=195, Bit 15, Center 120 (55 ~ 186) 132
3085 23:14:32.696903 ==
3086 23:14:32.700000 Dram Type= 6, Freq= 0, CH_0, rank 1
3087 23:14:32.706527 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3088 23:14:32.706607 ==
3089 23:14:32.706670 DQS Delay:
3090 23:14:32.710231 DQS0 = 0, DQS1 = 0
3091 23:14:32.710311 DQM Delay:
3092 23:14:32.710374 DQM0 = 121, DQM1 = 110
3093 23:14:32.713299 DQ Delay:
3094 23:14:32.716250 DQ0 =120, DQ1 =120, DQ2 =118, DQ3 =118
3095 23:14:32.719913 DQ4 =122, DQ5 =116, DQ6 =128, DQ7 =126
3096 23:14:32.723292 DQ8 =100, DQ9 =100, DQ10 =110, DQ11 =102
3097 23:14:32.726724 DQ12 =114, DQ13 =116, DQ14 =122, DQ15 =120
3098 23:14:32.726805
3099 23:14:32.726868
3100 23:14:32.736764 [DQSOSCAuto] RK1, (LSB)MR18= 0xfef, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 404 ps
3101 23:14:32.736847 CH0 RK1: MR19=403, MR18=FEF
3102 23:14:32.743018 CH0_RK1: MR19=0x403, MR18=0xFEF, DQSOSC=404, MR23=63, INC=40, DEC=26
3103 23:14:32.746595 [RxdqsGatingPostProcess] freq 1200
3104 23:14:32.753301 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3105 23:14:32.756388 best DQS0 dly(2T, 0.5T) = (0, 11)
3106 23:14:32.759913 best DQS1 dly(2T, 0.5T) = (0, 12)
3107 23:14:32.762959 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3108 23:14:32.763039 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3109 23:14:32.766274 best DQS0 dly(2T, 0.5T) = (0, 11)
3110 23:14:32.769539 best DQS1 dly(2T, 0.5T) = (0, 11)
3111 23:14:32.773384 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3112 23:14:32.776688 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3113 23:14:32.779567 Pre-setting of DQS Precalculation
3114 23:14:32.786534 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3115 23:14:32.786614 ==
3116 23:14:32.789989 Dram Type= 6, Freq= 0, CH_1, rank 0
3117 23:14:32.793197 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3118 23:14:32.793277 ==
3119 23:14:32.799983 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3120 23:14:32.802993 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3121 23:14:32.812763 [CA 0] Center 37 (7~68) winsize 62
3122 23:14:32.815803 [CA 1] Center 37 (7~68) winsize 62
3123 23:14:32.819371 [CA 2] Center 35 (5~65) winsize 61
3124 23:14:32.823180 [CA 3] Center 34 (4~64) winsize 61
3125 23:14:32.826277 [CA 4] Center 34 (4~64) winsize 61
3126 23:14:32.829322 [CA 5] Center 33 (3~63) winsize 61
3127 23:14:32.829443
3128 23:14:32.832878 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3129 23:14:32.832999
3130 23:14:32.836350 [CATrainingPosCal] consider 1 rank data
3131 23:14:32.839478 u2DelayCellTimex100 = 270/100 ps
3132 23:14:32.843044 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3133 23:14:32.845864 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3134 23:14:32.852714 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3135 23:14:32.856294 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3136 23:14:32.859504 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3137 23:14:32.863037 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3138 23:14:32.863117
3139 23:14:32.866123 CA PerBit enable=1, Macro0, CA PI delay=33
3140 23:14:32.866203
3141 23:14:32.869248 [CBTSetCACLKResult] CA Dly = 33
3142 23:14:32.869353 CS Dly: 7 (0~38)
3143 23:14:32.869418 ==
3144 23:14:32.872674 Dram Type= 6, Freq= 0, CH_1, rank 1
3145 23:14:32.879762 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3146 23:14:32.879843 ==
3147 23:14:32.882848 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3148 23:14:32.889480 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3149 23:14:32.898210 [CA 0] Center 37 (7~68) winsize 62
3150 23:14:32.901817 [CA 1] Center 37 (7~68) winsize 62
3151 23:14:32.905232 [CA 2] Center 35 (5~65) winsize 61
3152 23:14:32.908240 [CA 3] Center 34 (4~65) winsize 62
3153 23:14:32.911622 [CA 4] Center 34 (4~65) winsize 62
3154 23:14:32.914910 [CA 5] Center 33 (4~63) winsize 60
3155 23:14:32.915032
3156 23:14:32.918434 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3157 23:14:32.918555
3158 23:14:32.921478 [CATrainingPosCal] consider 2 rank data
3159 23:14:32.925158 u2DelayCellTimex100 = 270/100 ps
3160 23:14:32.928378 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3161 23:14:32.932054 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3162 23:14:32.938311 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3163 23:14:32.941797 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3164 23:14:32.945455 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3165 23:14:32.948347 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3166 23:14:32.948468
3167 23:14:32.951540 CA PerBit enable=1, Macro0, CA PI delay=33
3168 23:14:32.951641
3169 23:14:32.955177 [CBTSetCACLKResult] CA Dly = 33
3170 23:14:32.955258 CS Dly: 8 (0~41)
3171 23:14:32.955322
3172 23:14:32.958661 ----->DramcWriteLeveling(PI) begin...
3173 23:14:32.961875 ==
3174 23:14:32.965141 Dram Type= 6, Freq= 0, CH_1, rank 0
3175 23:14:32.968477 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3176 23:14:32.968559 ==
3177 23:14:32.971437 Write leveling (Byte 0): 27 => 27
3178 23:14:32.975205 Write leveling (Byte 1): 29 => 29
3179 23:14:32.978224 DramcWriteLeveling(PI) end<-----
3180 23:14:32.978305
3181 23:14:32.978368 ==
3182 23:14:32.981714 Dram Type= 6, Freq= 0, CH_1, rank 0
3183 23:14:32.984979 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3184 23:14:32.985061 ==
3185 23:14:32.988027 [Gating] SW mode calibration
3186 23:14:32.994937 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3187 23:14:32.998541 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3188 23:14:33.004888 0 15 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3189 23:14:33.008418 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3190 23:14:33.011537 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3191 23:14:33.018216 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3192 23:14:33.021612 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3193 23:14:33.025259 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3194 23:14:33.031640 0 15 24 | B1->B0 | 3232 2b2b | 1 1 | (1 0) (1 0)
3195 23:14:33.035219 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3196 23:14:33.038298 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3197 23:14:33.045115 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3198 23:14:33.048183 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3199 23:14:33.051930 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3200 23:14:33.058545 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3201 23:14:33.061612 1 0 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3202 23:14:33.065403 1 0 24 | B1->B0 | 2f2f 3c3c | 1 0 | (1 1) (0 0)
3203 23:14:33.068817 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3204 23:14:33.074973 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3205 23:14:33.078433 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3206 23:14:33.081694 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3207 23:14:33.088181 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3208 23:14:33.092049 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3209 23:14:33.094906 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3210 23:14:33.101642 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3211 23:14:33.105256 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3212 23:14:33.108814 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3213 23:14:33.115010 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3214 23:14:33.118862 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3215 23:14:33.122202 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3216 23:14:33.128792 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3217 23:14:33.131899 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3218 23:14:33.135230 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3219 23:14:33.141705 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3220 23:14:33.145062 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3221 23:14:33.148621 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3222 23:14:33.152051 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3223 23:14:33.158732 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3224 23:14:33.161819 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3225 23:14:33.165470 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3226 23:14:33.172297 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3227 23:14:33.175350 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3228 23:14:33.179100 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3229 23:14:33.182232 Total UI for P1: 0, mck2ui 16
3230 23:14:33.185269 best dqsien dly found for B0: ( 1, 3, 26)
3231 23:14:33.188629 Total UI for P1: 0, mck2ui 16
3232 23:14:33.191914 best dqsien dly found for B1: ( 1, 3, 24)
3233 23:14:33.195747 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3234 23:14:33.198523 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3235 23:14:33.198605
3236 23:14:33.205254 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3237 23:14:33.208550 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3238 23:14:33.208631 [Gating] SW calibration Done
3239 23:14:33.212034 ==
3240 23:14:33.212118 Dram Type= 6, Freq= 0, CH_1, rank 0
3241 23:14:33.218922 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3242 23:14:33.219004 ==
3243 23:14:33.219068 RX Vref Scan: 0
3244 23:14:33.219128
3245 23:14:33.222111 RX Vref 0 -> 0, step: 1
3246 23:14:33.222193
3247 23:14:33.225446 RX Delay -40 -> 252, step: 8
3248 23:14:33.228779 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3249 23:14:33.232228 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3250 23:14:33.235884 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3251 23:14:33.242048 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3252 23:14:33.245733 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3253 23:14:33.248789 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3254 23:14:33.252175 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3255 23:14:33.255489 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
3256 23:14:33.262171 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3257 23:14:33.265338 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3258 23:14:33.269145 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3259 23:14:33.272151 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3260 23:14:33.275870 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3261 23:14:33.282671 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3262 23:14:33.285803 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3263 23:14:33.289390 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3264 23:14:33.289512 ==
3265 23:14:33.292630 Dram Type= 6, Freq= 0, CH_1, rank 0
3266 23:14:33.295479 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3267 23:14:33.295599 ==
3268 23:14:33.298741 DQS Delay:
3269 23:14:33.298863 DQS0 = 0, DQS1 = 0
3270 23:14:33.302241 DQM Delay:
3271 23:14:33.302360 DQM0 = 120, DQM1 = 116
3272 23:14:33.302473 DQ Delay:
3273 23:14:33.305595 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3274 23:14:33.308805 DQ4 =119, DQ5 =127, DQ6 =127, DQ7 =123
3275 23:14:33.315790 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =111
3276 23:14:33.319422 DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123
3277 23:14:33.319541
3278 23:14:33.319653
3279 23:14:33.319761 ==
3280 23:14:33.322530 Dram Type= 6, Freq= 0, CH_1, rank 0
3281 23:14:33.325782 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3282 23:14:33.325865 ==
3283 23:14:33.325929
3284 23:14:33.325988
3285 23:14:33.328961 TX Vref Scan disable
3286 23:14:33.329041 == TX Byte 0 ==
3287 23:14:33.335684 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3288 23:14:33.339025 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3289 23:14:33.339106 == TX Byte 1 ==
3290 23:14:33.345654 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3291 23:14:33.349050 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3292 23:14:33.349131 ==
3293 23:14:33.352545 Dram Type= 6, Freq= 0, CH_1, rank 0
3294 23:14:33.356022 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3295 23:14:33.356107 ==
3296 23:14:33.368925 TX Vref=22, minBit 9, minWin=24, winSum=413
3297 23:14:33.372070 TX Vref=24, minBit 9, minWin=24, winSum=420
3298 23:14:33.375270 TX Vref=26, minBit 9, minWin=25, winSum=422
3299 23:14:33.378837 TX Vref=28, minBit 1, minWin=26, winSum=426
3300 23:14:33.382009 TX Vref=30, minBit 1, minWin=26, winSum=432
3301 23:14:33.385642 TX Vref=32, minBit 1, minWin=26, winSum=433
3302 23:14:33.392293 [TxChooseVref] Worse bit 1, Min win 26, Win sum 433, Final Vref 32
3303 23:14:33.392388
3304 23:14:33.395503 Final TX Range 1 Vref 32
3305 23:14:33.395619
3306 23:14:33.395686 ==
3307 23:14:33.398573 Dram Type= 6, Freq= 0, CH_1, rank 0
3308 23:14:33.402223 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3309 23:14:33.402304 ==
3310 23:14:33.402367
3311 23:14:33.402426
3312 23:14:33.405184 TX Vref Scan disable
3313 23:14:33.408787 == TX Byte 0 ==
3314 23:14:33.412307 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3315 23:14:33.415784 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3316 23:14:33.418869 == TX Byte 1 ==
3317 23:14:33.422439 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3318 23:14:33.425615 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3319 23:14:33.425697
3320 23:14:33.428747 [DATLAT]
3321 23:14:33.428828 Freq=1200, CH1 RK0
3322 23:14:33.428893
3323 23:14:33.432375 DATLAT Default: 0xd
3324 23:14:33.432456 0, 0xFFFF, sum = 0
3325 23:14:33.435696 1, 0xFFFF, sum = 0
3326 23:14:33.435778 2, 0xFFFF, sum = 0
3327 23:14:33.438648 3, 0xFFFF, sum = 0
3328 23:14:33.438730 4, 0xFFFF, sum = 0
3329 23:14:33.442261 5, 0xFFFF, sum = 0
3330 23:14:33.442343 6, 0xFFFF, sum = 0
3331 23:14:33.445617 7, 0xFFFF, sum = 0
3332 23:14:33.445699 8, 0xFFFF, sum = 0
3333 23:14:33.449103 9, 0xFFFF, sum = 0
3334 23:14:33.449187 10, 0xFFFF, sum = 0
3335 23:14:33.452453 11, 0xFFFF, sum = 0
3336 23:14:33.452536 12, 0x0, sum = 1
3337 23:14:33.455720 13, 0x0, sum = 2
3338 23:14:33.455802 14, 0x0, sum = 3
3339 23:14:33.458990 15, 0x0, sum = 4
3340 23:14:33.459071 best_step = 13
3341 23:14:33.459134
3342 23:14:33.459194 ==
3343 23:14:33.462188 Dram Type= 6, Freq= 0, CH_1, rank 0
3344 23:14:33.468781 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3345 23:14:33.468862 ==
3346 23:14:33.468926 RX Vref Scan: 1
3347 23:14:33.468984
3348 23:14:33.471983 Set Vref Range= 32 -> 127
3349 23:14:33.472063
3350 23:14:33.475715 RX Vref 32 -> 127, step: 1
3351 23:14:33.475796
3352 23:14:33.475859 RX Delay -5 -> 252, step: 4
3353 23:14:33.479052
3354 23:14:33.479133 Set Vref, RX VrefLevel [Byte0]: 32
3355 23:14:33.482037 [Byte1]: 32
3356 23:14:33.486676
3357 23:14:33.486757 Set Vref, RX VrefLevel [Byte0]: 33
3358 23:14:33.489846 [Byte1]: 33
3359 23:14:33.494938
3360 23:14:33.495019 Set Vref, RX VrefLevel [Byte0]: 34
3361 23:14:33.498029 [Byte1]: 34
3362 23:14:33.502340
3363 23:14:33.502419 Set Vref, RX VrefLevel [Byte0]: 35
3364 23:14:33.506044 [Byte1]: 35
3365 23:14:33.510182
3366 23:14:33.510264 Set Vref, RX VrefLevel [Byte0]: 36
3367 23:14:33.513862 [Byte1]: 36
3368 23:14:33.518279
3369 23:14:33.518358 Set Vref, RX VrefLevel [Byte0]: 37
3370 23:14:33.521260 [Byte1]: 37
3371 23:14:33.526297
3372 23:14:33.526377 Set Vref, RX VrefLevel [Byte0]: 38
3373 23:14:33.529297 [Byte1]: 38
3374 23:14:33.533722
3375 23:14:33.533840 Set Vref, RX VrefLevel [Byte0]: 39
3376 23:14:33.537419 [Byte1]: 39
3377 23:14:33.541688
3378 23:14:33.541810 Set Vref, RX VrefLevel [Byte0]: 40
3379 23:14:33.544699 [Byte1]: 40
3380 23:14:33.549917
3381 23:14:33.550038 Set Vref, RX VrefLevel [Byte0]: 41
3382 23:14:33.552695 [Byte1]: 41
3383 23:14:33.557187
3384 23:14:33.557291 Set Vref, RX VrefLevel [Byte0]: 42
3385 23:14:33.560701 [Byte1]: 42
3386 23:14:33.565699
3387 23:14:33.565778 Set Vref, RX VrefLevel [Byte0]: 43
3388 23:14:33.568673 [Byte1]: 43
3389 23:14:33.573427
3390 23:14:33.573506 Set Vref, RX VrefLevel [Byte0]: 44
3391 23:14:33.576445 [Byte1]: 44
3392 23:14:33.580916
3393 23:14:33.584174 Set Vref, RX VrefLevel [Byte0]: 45
3394 23:14:33.584254 [Byte1]: 45
3395 23:14:33.588854
3396 23:14:33.588959 Set Vref, RX VrefLevel [Byte0]: 46
3397 23:14:33.592247 [Byte1]: 46
3398 23:14:33.596578
3399 23:14:33.596657 Set Vref, RX VrefLevel [Byte0]: 47
3400 23:14:33.600025 [Byte1]: 47
3401 23:14:33.604574
3402 23:14:33.604654 Set Vref, RX VrefLevel [Byte0]: 48
3403 23:14:33.607859 [Byte1]: 48
3404 23:14:33.612270
3405 23:14:33.612396 Set Vref, RX VrefLevel [Byte0]: 49
3406 23:14:33.615411 [Byte1]: 49
3407 23:14:33.620401
3408 23:14:33.620495 Set Vref, RX VrefLevel [Byte0]: 50
3409 23:14:33.623590 [Byte1]: 50
3410 23:14:33.627886
3411 23:14:33.627966 Set Vref, RX VrefLevel [Byte0]: 51
3412 23:14:33.631485 [Byte1]: 51
3413 23:14:33.635797
3414 23:14:33.635877 Set Vref, RX VrefLevel [Byte0]: 52
3415 23:14:33.638949 [Byte1]: 52
3416 23:14:33.643823
3417 23:14:33.643902 Set Vref, RX VrefLevel [Byte0]: 53
3418 23:14:33.646934 [Byte1]: 53
3419 23:14:33.651731
3420 23:14:33.651811 Set Vref, RX VrefLevel [Byte0]: 54
3421 23:14:33.655183 [Byte1]: 54
3422 23:14:33.659293
3423 23:14:33.659373 Set Vref, RX VrefLevel [Byte0]: 55
3424 23:14:33.662701 [Byte1]: 55
3425 23:14:33.667108
3426 23:14:33.667189 Set Vref, RX VrefLevel [Byte0]: 56
3427 23:14:33.670525 [Byte1]: 56
3428 23:14:33.675324
3429 23:14:33.675406 Set Vref, RX VrefLevel [Byte0]: 57
3430 23:14:33.678479 [Byte1]: 57
3431 23:14:33.682628
3432 23:14:33.682708 Set Vref, RX VrefLevel [Byte0]: 58
3433 23:14:33.686245 [Byte1]: 58
3434 23:14:33.690571
3435 23:14:33.690651 Set Vref, RX VrefLevel [Byte0]: 59
3436 23:14:33.694265 [Byte1]: 59
3437 23:14:33.698975
3438 23:14:33.699054 Set Vref, RX VrefLevel [Byte0]: 60
3439 23:14:33.701757 [Byte1]: 60
3440 23:14:33.706745
3441 23:14:33.706875 Set Vref, RX VrefLevel [Byte0]: 61
3442 23:14:33.709607 [Byte1]: 61
3443 23:14:33.714330
3444 23:14:33.714409 Set Vref, RX VrefLevel [Byte0]: 62
3445 23:14:33.717799 [Byte1]: 62
3446 23:14:33.722184
3447 23:14:33.722263 Set Vref, RX VrefLevel [Byte0]: 63
3448 23:14:33.725388 [Byte1]: 63
3449 23:14:33.729845
3450 23:14:33.729924 Set Vref, RX VrefLevel [Byte0]: 64
3451 23:14:33.733248 [Byte1]: 64
3452 23:14:33.737872
3453 23:14:33.737951 Set Vref, RX VrefLevel [Byte0]: 65
3454 23:14:33.741190 [Byte1]: 65
3455 23:14:33.745931
3456 23:14:33.746010 Set Vref, RX VrefLevel [Byte0]: 66
3457 23:14:33.749046 [Byte1]: 66
3458 23:14:33.753394
3459 23:14:33.753472 Set Vref, RX VrefLevel [Byte0]: 67
3460 23:14:33.757048 [Byte1]: 67
3461 23:14:33.761706
3462 23:14:33.761786 Set Vref, RX VrefLevel [Byte0]: 68
3463 23:14:33.764590 [Byte1]: 68
3464 23:14:33.769371
3465 23:14:33.769449 Final RX Vref Byte 0 = 54 to rank0
3466 23:14:33.772762 Final RX Vref Byte 1 = 55 to rank0
3467 23:14:33.776003 Final RX Vref Byte 0 = 54 to rank1
3468 23:14:33.779526 Final RX Vref Byte 1 = 55 to rank1==
3469 23:14:33.782689 Dram Type= 6, Freq= 0, CH_1, rank 0
3470 23:14:33.789659 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3471 23:14:33.789739 ==
3472 23:14:33.789803 DQS Delay:
3473 23:14:33.789862 DQS0 = 0, DQS1 = 0
3474 23:14:33.792667 DQM Delay:
3475 23:14:33.792746 DQM0 = 120, DQM1 = 118
3476 23:14:33.795750 DQ Delay:
3477 23:14:33.799530 DQ0 =124, DQ1 =114, DQ2 =110, DQ3 =116
3478 23:14:33.802501 DQ4 =122, DQ5 =128, DQ6 =128, DQ7 =120
3479 23:14:33.806116 DQ8 =106, DQ9 =108, DQ10 =118, DQ11 =112
3480 23:14:33.809191 DQ12 =124, DQ13 =124, DQ14 =126, DQ15 =126
3481 23:14:33.809267
3482 23:14:33.809329
3483 23:14:33.816420 [DQSOSCAuto] RK0, (LSB)MR18= 0xff12, (MSB)MR19= 0x304, tDQSOscB0 = 403 ps tDQSOscB1 = 410 ps
3484 23:14:33.820004 CH1 RK0: MR19=304, MR18=FF12
3485 23:14:33.826706 CH1_RK0: MR19=0x304, MR18=0xFF12, DQSOSC=403, MR23=63, INC=40, DEC=26
3486 23:14:33.826787
3487 23:14:33.829497 ----->DramcWriteLeveling(PI) begin...
3488 23:14:33.829578 ==
3489 23:14:33.832778 Dram Type= 6, Freq= 0, CH_1, rank 1
3490 23:14:33.836452 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3491 23:14:33.836532 ==
3492 23:14:33.839908 Write leveling (Byte 0): 25 => 25
3493 23:14:33.843380 Write leveling (Byte 1): 28 => 28
3494 23:14:33.846242 DramcWriteLeveling(PI) end<-----
3495 23:14:33.846321
3496 23:14:33.846384 ==
3497 23:14:33.850070 Dram Type= 6, Freq= 0, CH_1, rank 1
3498 23:14:33.856020 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3499 23:14:33.856126 ==
3500 23:14:33.856217 [Gating] SW mode calibration
3501 23:14:33.866295 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3502 23:14:33.869882 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3503 23:14:33.873121 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3504 23:14:33.879759 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3505 23:14:33.883186 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3506 23:14:33.886348 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3507 23:14:33.893183 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
3508 23:14:33.896652 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
3509 23:14:33.899717 0 15 24 | B1->B0 | 2b2b 3434 | 0 1 | (1 0) (1 0)
3510 23:14:33.906333 0 15 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3511 23:14:33.909833 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3512 23:14:33.913578 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3513 23:14:33.919582 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3514 23:14:33.923097 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3515 23:14:33.926561 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3516 23:14:33.929880 1 0 20 | B1->B0 | 2828 2323 | 1 0 | (0 0) (0 0)
3517 23:14:33.936467 1 0 24 | B1->B0 | 4444 2d2d | 0 0 | (0 0) (0 0)
3518 23:14:33.940018 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3519 23:14:33.942999 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3520 23:14:33.949899 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3521 23:14:33.952960 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3522 23:14:33.956592 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3523 23:14:33.963085 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3524 23:14:33.966232 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3525 23:14:33.969949 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3526 23:14:33.976263 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3527 23:14:33.979529 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3528 23:14:33.983178 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3529 23:14:33.989742 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3530 23:14:33.993111 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3531 23:14:33.996457 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3532 23:14:34.003059 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3533 23:14:34.006401 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3534 23:14:34.009518 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3535 23:14:34.016050 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3536 23:14:34.019736 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3537 23:14:34.023353 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3538 23:14:34.029535 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3539 23:14:34.032977 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3540 23:14:34.036400 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3541 23:14:34.039772 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3542 23:14:34.043354 Total UI for P1: 0, mck2ui 16
3543 23:14:34.046199 best dqsien dly found for B1: ( 1, 3, 22)
3544 23:14:34.052788 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3545 23:14:34.055994 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3546 23:14:34.059551 Total UI for P1: 0, mck2ui 16
3547 23:14:34.062604 best dqsien dly found for B0: ( 1, 3, 26)
3548 23:14:34.066305 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3549 23:14:34.069227 best DQS1 dly(MCK, UI, PI) = (1, 3, 22)
3550 23:14:34.069298
3551 23:14:34.073084 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3552 23:14:34.079572 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 22)
3553 23:14:34.079655 [Gating] SW calibration Done
3554 23:14:34.079747 ==
3555 23:14:34.083037 Dram Type= 6, Freq= 0, CH_1, rank 1
3556 23:14:34.089378 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3557 23:14:34.089459 ==
3558 23:14:34.089523 RX Vref Scan: 0
3559 23:14:34.089585
3560 23:14:34.092912 RX Vref 0 -> 0, step: 1
3561 23:14:34.092992
3562 23:14:34.095950 RX Delay -40 -> 252, step: 8
3563 23:14:34.099324 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3564 23:14:34.103029 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3565 23:14:34.105899 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3566 23:14:34.112726 iDelay=200, Bit 3, Center 119 (56 ~ 183) 128
3567 23:14:34.115969 iDelay=200, Bit 4, Center 119 (56 ~ 183) 128
3568 23:14:34.119132 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3569 23:14:34.122576 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3570 23:14:34.126233 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
3571 23:14:34.129236 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3572 23:14:34.136049 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3573 23:14:34.139101 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3574 23:14:34.142558 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3575 23:14:34.145918 iDelay=200, Bit 12, Center 127 (56 ~ 199) 144
3576 23:14:34.152489 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3577 23:14:34.155944 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3578 23:14:34.159073 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3579 23:14:34.159169 ==
3580 23:14:34.162205 Dram Type= 6, Freq= 0, CH_1, rank 1
3581 23:14:34.165846 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3582 23:14:34.165953 ==
3583 23:14:34.168895 DQS Delay:
3584 23:14:34.168976 DQS0 = 0, DQS1 = 0
3585 23:14:34.172647 DQM Delay:
3586 23:14:34.172728 DQM0 = 121, DQM1 = 117
3587 23:14:34.172791 DQ Delay:
3588 23:14:34.179205 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3589 23:14:34.182511 DQ4 =119, DQ5 =131, DQ6 =131, DQ7 =123
3590 23:14:34.185724 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =111
3591 23:14:34.188970 DQ12 =127, DQ13 =127, DQ14 =123, DQ15 =123
3592 23:14:34.189049
3593 23:14:34.189113
3594 23:14:34.189171 ==
3595 23:14:34.192488 Dram Type= 6, Freq= 0, CH_1, rank 1
3596 23:14:34.195499 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3597 23:14:34.195598 ==
3598 23:14:34.195686
3599 23:14:34.195770
3600 23:14:34.199168 TX Vref Scan disable
3601 23:14:34.202225 == TX Byte 0 ==
3602 23:14:34.205681 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3603 23:14:34.208847 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3604 23:14:34.212577 == TX Byte 1 ==
3605 23:14:34.215483 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3606 23:14:34.218576 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3607 23:14:34.218648 ==
3608 23:14:34.222119 Dram Type= 6, Freq= 0, CH_1, rank 1
3609 23:14:34.225379 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3610 23:14:34.228689 ==
3611 23:14:34.238806 TX Vref=22, minBit 7, minWin=25, winSum=420
3612 23:14:34.241913 TX Vref=24, minBit 9, minWin=25, winSum=424
3613 23:14:34.245601 TX Vref=26, minBit 10, minWin=25, winSum=427
3614 23:14:34.248488 TX Vref=28, minBit 9, minWin=26, winSum=434
3615 23:14:34.251896 TX Vref=30, minBit 10, minWin=26, winSum=434
3616 23:14:34.258807 TX Vref=32, minBit 9, minWin=26, winSum=433
3617 23:14:34.261696 [TxChooseVref] Worse bit 9, Min win 26, Win sum 434, Final Vref 28
3618 23:14:34.261797
3619 23:14:34.265312 Final TX Range 1 Vref 28
3620 23:14:34.265387
3621 23:14:34.265486 ==
3622 23:14:34.268295 Dram Type= 6, Freq= 0, CH_1, rank 1
3623 23:14:34.272001 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3624 23:14:34.275093 ==
3625 23:14:34.275191
3626 23:14:34.275279
3627 23:14:34.275343 TX Vref Scan disable
3628 23:14:34.278754 == TX Byte 0 ==
3629 23:14:34.281849 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3630 23:14:34.288681 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3631 23:14:34.288760 == TX Byte 1 ==
3632 23:14:34.292020 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3633 23:14:34.298396 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3634 23:14:34.298476
3635 23:14:34.298538 [DATLAT]
3636 23:14:34.298596 Freq=1200, CH1 RK1
3637 23:14:34.298651
3638 23:14:34.302118 DATLAT Default: 0xd
3639 23:14:34.302197 0, 0xFFFF, sum = 0
3640 23:14:34.305295 1, 0xFFFF, sum = 0
3641 23:14:34.305379 2, 0xFFFF, sum = 0
3642 23:14:34.308503 3, 0xFFFF, sum = 0
3643 23:14:34.308583 4, 0xFFFF, sum = 0
3644 23:14:34.312025 5, 0xFFFF, sum = 0
3645 23:14:34.315447 6, 0xFFFF, sum = 0
3646 23:14:34.315527 7, 0xFFFF, sum = 0
3647 23:14:34.318913 8, 0xFFFF, sum = 0
3648 23:14:34.318993 9, 0xFFFF, sum = 0
3649 23:14:34.322550 10, 0xFFFF, sum = 0
3650 23:14:34.322630 11, 0xFFFF, sum = 0
3651 23:14:34.325406 12, 0x0, sum = 1
3652 23:14:34.325486 13, 0x0, sum = 2
3653 23:14:34.328567 14, 0x0, sum = 3
3654 23:14:34.328648 15, 0x0, sum = 4
3655 23:14:34.328711 best_step = 13
3656 23:14:34.328770
3657 23:14:34.332146 ==
3658 23:14:34.335508 Dram Type= 6, Freq= 0, CH_1, rank 1
3659 23:14:34.338526 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3660 23:14:34.338606 ==
3661 23:14:34.338684 RX Vref Scan: 0
3662 23:14:34.338756
3663 23:14:34.342014 RX Vref 0 -> 0, step: 1
3664 23:14:34.342093
3665 23:14:34.345350 RX Delay -5 -> 252, step: 4
3666 23:14:34.348860 iDelay=195, Bit 0, Center 122 (59 ~ 186) 128
3667 23:14:34.355374 iDelay=195, Bit 1, Center 116 (55 ~ 178) 124
3668 23:14:34.358757 iDelay=195, Bit 2, Center 110 (51 ~ 170) 120
3669 23:14:34.362256 iDelay=195, Bit 3, Center 116 (59 ~ 174) 116
3670 23:14:34.365461 iDelay=195, Bit 4, Center 116 (55 ~ 178) 124
3671 23:14:34.368868 iDelay=195, Bit 5, Center 132 (71 ~ 194) 124
3672 23:14:34.371761 iDelay=195, Bit 6, Center 130 (67 ~ 194) 128
3673 23:14:34.378686 iDelay=195, Bit 7, Center 120 (59 ~ 182) 124
3674 23:14:34.382227 iDelay=195, Bit 8, Center 106 (47 ~ 166) 120
3675 23:14:34.385295 iDelay=195, Bit 9, Center 108 (47 ~ 170) 124
3676 23:14:34.389024 iDelay=195, Bit 10, Center 118 (59 ~ 178) 120
3677 23:14:34.392132 iDelay=195, Bit 11, Center 112 (51 ~ 174) 124
3678 23:14:34.398853 iDelay=195, Bit 12, Center 126 (63 ~ 190) 128
3679 23:14:34.401886 iDelay=195, Bit 13, Center 124 (67 ~ 182) 116
3680 23:14:34.405577 iDelay=195, Bit 14, Center 124 (67 ~ 182) 116
3681 23:14:34.408641 iDelay=195, Bit 15, Center 126 (67 ~ 186) 120
3682 23:14:34.408721 ==
3683 23:14:34.412130 Dram Type= 6, Freq= 0, CH_1, rank 1
3684 23:14:34.418639 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3685 23:14:34.418720 ==
3686 23:14:34.418783 DQS Delay:
3687 23:14:34.418840 DQS0 = 0, DQS1 = 0
3688 23:14:34.422446 DQM Delay:
3689 23:14:34.422525 DQM0 = 120, DQM1 = 118
3690 23:14:34.425279 DQ Delay:
3691 23:14:34.428737 DQ0 =122, DQ1 =116, DQ2 =110, DQ3 =116
3692 23:14:34.432441 DQ4 =116, DQ5 =132, DQ6 =130, DQ7 =120
3693 23:14:34.435574 DQ8 =106, DQ9 =108, DQ10 =118, DQ11 =112
3694 23:14:34.438870 DQ12 =126, DQ13 =124, DQ14 =124, DQ15 =126
3695 23:14:34.438949
3696 23:14:34.439011
3697 23:14:34.449023 [DQSOSCAuto] RK1, (LSB)MR18= 0x13ef, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 402 ps
3698 23:14:34.449107 CH1 RK1: MR19=403, MR18=13EF
3699 23:14:34.455233 CH1_RK1: MR19=0x403, MR18=0x13EF, DQSOSC=402, MR23=63, INC=40, DEC=27
3700 23:14:34.458832 [RxdqsGatingPostProcess] freq 1200
3701 23:14:34.465629 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3702 23:14:34.468668 best DQS0 dly(2T, 0.5T) = (0, 11)
3703 23:14:34.472441 best DQS1 dly(2T, 0.5T) = (0, 11)
3704 23:14:34.475566 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3705 23:14:34.479036 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3706 23:14:34.479115 best DQS0 dly(2T, 0.5T) = (0, 11)
3707 23:14:34.481960 best DQS1 dly(2T, 0.5T) = (0, 11)
3708 23:14:34.485260 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3709 23:14:34.488828 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3710 23:14:34.491828 Pre-setting of DQS Precalculation
3711 23:14:34.498501 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3712 23:14:34.505392 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3713 23:14:34.512177 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3714 23:14:34.512274
3715 23:14:34.512359
3716 23:14:34.515280 [Calibration Summary] 2400 Mbps
3717 23:14:34.515360 CH 0, Rank 0
3718 23:14:34.519017 SW Impedance : PASS
3719 23:14:34.522255 DUTY Scan : NO K
3720 23:14:34.522334 ZQ Calibration : PASS
3721 23:14:34.525081 Jitter Meter : NO K
3722 23:14:34.528753 CBT Training : PASS
3723 23:14:34.528859 Write leveling : PASS
3724 23:14:34.532387 RX DQS gating : PASS
3725 23:14:34.535457 RX DQ/DQS(RDDQC) : PASS
3726 23:14:34.535552 TX DQ/DQS : PASS
3727 23:14:34.538876 RX DATLAT : PASS
3728 23:14:34.542392 RX DQ/DQS(Engine): PASS
3729 23:14:34.542472 TX OE : NO K
3730 23:14:34.542536 All Pass.
3731 23:14:34.545122
3732 23:14:34.545203 CH 0, Rank 1
3733 23:14:34.548986 SW Impedance : PASS
3734 23:14:34.549066 DUTY Scan : NO K
3735 23:14:34.552212 ZQ Calibration : PASS
3736 23:14:34.552338 Jitter Meter : NO K
3737 23:14:34.555350 CBT Training : PASS
3738 23:14:34.558910 Write leveling : PASS
3739 23:14:34.558991 RX DQS gating : PASS
3740 23:14:34.561925 RX DQ/DQS(RDDQC) : PASS
3741 23:14:34.565413 TX DQ/DQS : PASS
3742 23:14:34.565494 RX DATLAT : PASS
3743 23:14:34.569037 RX DQ/DQS(Engine): PASS
3744 23:14:34.572096 TX OE : NO K
3745 23:14:34.572202 All Pass.
3746 23:14:34.572319
3747 23:14:34.572405 CH 1, Rank 0
3748 23:14:34.575230 SW Impedance : PASS
3749 23:14:34.578802 DUTY Scan : NO K
3750 23:14:34.578882 ZQ Calibration : PASS
3751 23:14:34.582119 Jitter Meter : NO K
3752 23:14:34.582201 CBT Training : PASS
3753 23:14:34.585739 Write leveling : PASS
3754 23:14:34.588680 RX DQS gating : PASS
3755 23:14:34.588760 RX DQ/DQS(RDDQC) : PASS
3756 23:14:34.592505 TX DQ/DQS : PASS
3757 23:14:34.595528 RX DATLAT : PASS
3758 23:14:34.595609 RX DQ/DQS(Engine): PASS
3759 23:14:34.599160 TX OE : NO K
3760 23:14:34.599268 All Pass.
3761 23:14:34.599359
3762 23:14:34.602224 CH 1, Rank 1
3763 23:14:34.602305 SW Impedance : PASS
3764 23:14:34.605851 DUTY Scan : NO K
3765 23:14:34.608872 ZQ Calibration : PASS
3766 23:14:34.608953 Jitter Meter : NO K
3767 23:14:34.611930 CBT Training : PASS
3768 23:14:34.615618 Write leveling : PASS
3769 23:14:34.615698 RX DQS gating : PASS
3770 23:14:34.618847 RX DQ/DQS(RDDQC) : PASS
3771 23:14:34.621977 TX DQ/DQS : PASS
3772 23:14:34.622062 RX DATLAT : PASS
3773 23:14:34.625406 RX DQ/DQS(Engine): PASS
3774 23:14:34.625487 TX OE : NO K
3775 23:14:34.628734 All Pass.
3776 23:14:34.628814
3777 23:14:34.628877 DramC Write-DBI off
3778 23:14:34.632282 PER_BANK_REFRESH: Hybrid Mode
3779 23:14:34.635647 TX_TRACKING: ON
3780 23:14:34.641887 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3781 23:14:34.645641 [FAST_K] Save calibration result to emmc
3782 23:14:34.652125 dramc_set_vcore_voltage set vcore to 650000
3783 23:14:34.652232 Read voltage for 600, 5
3784 23:14:34.652356 Vio18 = 0
3785 23:14:34.655153 Vcore = 650000
3786 23:14:34.655234 Vdram = 0
3787 23:14:34.655298 Vddq = 0
3788 23:14:34.658687 Vmddr = 0
3789 23:14:34.662303 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3790 23:14:34.668916 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3791 23:14:34.668997 MEM_TYPE=3, freq_sel=19
3792 23:14:34.672011 sv_algorithm_assistance_LP4_1600
3793 23:14:34.679032 ============ PULL DRAM RESETB DOWN ============
3794 23:14:34.681754 ========== PULL DRAM RESETB DOWN end =========
3795 23:14:34.684954 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3796 23:14:34.688609 ===================================
3797 23:14:34.691837 LPDDR4 DRAM CONFIGURATION
3798 23:14:34.695332 ===================================
3799 23:14:34.698518 EX_ROW_EN[0] = 0x0
3800 23:14:34.698598 EX_ROW_EN[1] = 0x0
3801 23:14:34.701981 LP4Y_EN = 0x0
3802 23:14:34.702108 WORK_FSP = 0x0
3803 23:14:34.705100 WL = 0x2
3804 23:14:34.705180 RL = 0x2
3805 23:14:34.708522 BL = 0x2
3806 23:14:34.708602 RPST = 0x0
3807 23:14:34.712110 RD_PRE = 0x0
3808 23:14:34.712189 WR_PRE = 0x1
3809 23:14:34.715028 WR_PST = 0x0
3810 23:14:34.715108 DBI_WR = 0x0
3811 23:14:34.718733 DBI_RD = 0x0
3812 23:14:34.718813 OTF = 0x1
3813 23:14:34.721714 ===================================
3814 23:14:34.725474 ===================================
3815 23:14:34.728544 ANA top config
3816 23:14:34.731428 ===================================
3817 23:14:34.735172 DLL_ASYNC_EN = 0
3818 23:14:34.735270 ALL_SLAVE_EN = 1
3819 23:14:34.738579 NEW_RANK_MODE = 1
3820 23:14:34.741949 DLL_IDLE_MODE = 1
3821 23:14:34.745144 LP45_APHY_COMB_EN = 1
3822 23:14:34.745224 TX_ODT_DIS = 1
3823 23:14:34.748191 NEW_8X_MODE = 1
3824 23:14:34.751836 ===================================
3825 23:14:34.754756 ===================================
3826 23:14:34.758377 data_rate = 1200
3827 23:14:34.761351 CKR = 1
3828 23:14:34.765172 DQ_P2S_RATIO = 8
3829 23:14:34.768147 ===================================
3830 23:14:34.771258 CA_P2S_RATIO = 8
3831 23:14:34.771339 DQ_CA_OPEN = 0
3832 23:14:34.775035 DQ_SEMI_OPEN = 0
3833 23:14:34.778213 CA_SEMI_OPEN = 0
3834 23:14:34.781494 CA_FULL_RATE = 0
3835 23:14:34.784570 DQ_CKDIV4_EN = 1
3836 23:14:34.787999 CA_CKDIV4_EN = 1
3837 23:14:34.788109 CA_PREDIV_EN = 0
3838 23:14:34.791511 PH8_DLY = 0
3839 23:14:34.794800 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3840 23:14:34.798314 DQ_AAMCK_DIV = 4
3841 23:14:34.801215 CA_AAMCK_DIV = 4
3842 23:14:34.804580 CA_ADMCK_DIV = 4
3843 23:14:34.804661 DQ_TRACK_CA_EN = 0
3844 23:14:34.807854 CA_PICK = 600
3845 23:14:34.811357 CA_MCKIO = 600
3846 23:14:34.814697 MCKIO_SEMI = 0
3847 23:14:34.817838 PLL_FREQ = 2288
3848 23:14:34.821280 DQ_UI_PI_RATIO = 32
3849 23:14:34.824755 CA_UI_PI_RATIO = 0
3850 23:14:34.827852 ===================================
3851 23:14:34.831175 ===================================
3852 23:14:34.831279 memory_type:LPDDR4
3853 23:14:34.834444 GP_NUM : 10
3854 23:14:34.837965 SRAM_EN : 1
3855 23:14:34.838045 MD32_EN : 0
3856 23:14:34.841038 ===================================
3857 23:14:34.844526 [ANA_INIT] >>>>>>>>>>>>>>
3858 23:14:34.848029 <<<<<< [CONFIGURE PHASE]: ANA_TX
3859 23:14:34.851077 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3860 23:14:34.854779 ===================================
3861 23:14:34.857767 data_rate = 1200,PCW = 0X5800
3862 23:14:34.861351 ===================================
3863 23:14:34.864399 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3864 23:14:34.867953 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3865 23:14:34.874683 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3866 23:14:34.877854 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3867 23:14:34.880847 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3868 23:14:34.884486 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3869 23:14:34.887489 [ANA_INIT] flow start
3870 23:14:34.891134 [ANA_INIT] PLL >>>>>>>>
3871 23:14:34.891249 [ANA_INIT] PLL <<<<<<<<
3872 23:14:34.894472 [ANA_INIT] MIDPI >>>>>>>>
3873 23:14:34.898029 [ANA_INIT] MIDPI <<<<<<<<
3874 23:14:34.898111 [ANA_INIT] DLL >>>>>>>>
3875 23:14:34.900908 [ANA_INIT] flow end
3876 23:14:34.904587 ============ LP4 DIFF to SE enter ============
3877 23:14:34.911019 ============ LP4 DIFF to SE exit ============
3878 23:14:34.911101 [ANA_INIT] <<<<<<<<<<<<<
3879 23:14:34.914376 [Flow] Enable top DCM control >>>>>
3880 23:14:34.917786 [Flow] Enable top DCM control <<<<<
3881 23:14:34.921428 Enable DLL master slave shuffle
3882 23:14:34.927539 ==============================================================
3883 23:14:34.927624 Gating Mode config
3884 23:14:34.934632 ==============================================================
3885 23:14:34.934712 Config description:
3886 23:14:34.944261 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3887 23:14:34.950774 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3888 23:14:34.957335 SELPH_MODE 0: By rank 1: By Phase
3889 23:14:34.964048 ==============================================================
3890 23:14:34.964128 GAT_TRACK_EN = 1
3891 23:14:34.967452 RX_GATING_MODE = 2
3892 23:14:34.971009 RX_GATING_TRACK_MODE = 2
3893 23:14:34.973918 SELPH_MODE = 1
3894 23:14:34.977644 PICG_EARLY_EN = 1
3895 23:14:34.980663 VALID_LAT_VALUE = 1
3896 23:14:34.987467 ==============================================================
3897 23:14:34.991150 Enter into Gating configuration >>>>
3898 23:14:34.994157 Exit from Gating configuration <<<<
3899 23:14:34.997288 Enter into DVFS_PRE_config >>>>>
3900 23:14:35.007694 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3901 23:14:35.010713 Exit from DVFS_PRE_config <<<<<
3902 23:14:35.013723 Enter into PICG configuration >>>>
3903 23:14:35.017231 Exit from PICG configuration <<<<
3904 23:14:35.020386 [RX_INPUT] configuration >>>>>
3905 23:14:35.020467 [RX_INPUT] configuration <<<<<
3906 23:14:35.027283 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3907 23:14:35.033962 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3908 23:14:35.036910 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3909 23:14:35.043729 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3910 23:14:35.050420 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3911 23:14:35.056917 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3912 23:14:35.060450 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3913 23:14:35.063264 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3914 23:14:35.070112 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3915 23:14:35.073577 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3916 23:14:35.076999 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3917 23:14:35.083739 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3918 23:14:35.086887 ===================================
3919 23:14:35.086967 LPDDR4 DRAM CONFIGURATION
3920 23:14:35.089941 ===================================
3921 23:14:35.093631 EX_ROW_EN[0] = 0x0
3922 23:14:35.093711 EX_ROW_EN[1] = 0x0
3923 23:14:35.096831 LP4Y_EN = 0x0
3924 23:14:35.099887 WORK_FSP = 0x0
3925 23:14:35.099966 WL = 0x2
3926 23:14:35.103626 RL = 0x2
3927 23:14:35.103705 BL = 0x2
3928 23:14:35.106671 RPST = 0x0
3929 23:14:35.106750 RD_PRE = 0x0
3930 23:14:35.109921 WR_PRE = 0x1
3931 23:14:35.110000 WR_PST = 0x0
3932 23:14:35.113126 DBI_WR = 0x0
3933 23:14:35.113205 DBI_RD = 0x0
3934 23:14:35.116529 OTF = 0x1
3935 23:14:35.120091 ===================================
3936 23:14:35.123225 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3937 23:14:35.127061 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3938 23:14:35.133240 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3939 23:14:35.133320 ===================================
3940 23:14:35.136604 LPDDR4 DRAM CONFIGURATION
3941 23:14:35.140163 ===================================
3942 23:14:35.143654 EX_ROW_EN[0] = 0x10
3943 23:14:35.143733 EX_ROW_EN[1] = 0x0
3944 23:14:35.147112 LP4Y_EN = 0x0
3945 23:14:35.147193 WORK_FSP = 0x0
3946 23:14:35.150117 WL = 0x2
3947 23:14:35.150197 RL = 0x2
3948 23:14:35.153791 BL = 0x2
3949 23:14:35.153872 RPST = 0x0
3950 23:14:35.156896 RD_PRE = 0x0
3951 23:14:35.160426 WR_PRE = 0x1
3952 23:14:35.160506 WR_PST = 0x0
3953 23:14:35.163528 DBI_WR = 0x0
3954 23:14:35.163608 DBI_RD = 0x0
3955 23:14:35.166683 OTF = 0x1
3956 23:14:35.170090 ===================================
3957 23:14:35.172986 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3958 23:14:35.178891 nWR fixed to 30
3959 23:14:35.181904 [ModeRegInit_LP4] CH0 RK0
3960 23:14:35.181984 [ModeRegInit_LP4] CH0 RK1
3961 23:14:35.185230 [ModeRegInit_LP4] CH1 RK0
3962 23:14:35.188528 [ModeRegInit_LP4] CH1 RK1
3963 23:14:35.188608 match AC timing 17
3964 23:14:35.195675 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3965 23:14:35.198824 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3966 23:14:35.201887 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3967 23:14:35.208617 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3968 23:14:35.211745 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3969 23:14:35.211825 ==
3970 23:14:35.215284 Dram Type= 6, Freq= 0, CH_0, rank 0
3971 23:14:35.218282 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3972 23:14:35.218363 ==
3973 23:14:35.224855 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3974 23:14:35.231792 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3975 23:14:35.234841 [CA 0] Center 35 (5~66) winsize 62
3976 23:14:35.237947 [CA 1] Center 35 (5~66) winsize 62
3977 23:14:35.241537 [CA 2] Center 33 (3~64) winsize 62
3978 23:14:35.244937 [CA 3] Center 33 (2~64) winsize 63
3979 23:14:35.248165 [CA 4] Center 33 (2~64) winsize 63
3980 23:14:35.251973 [CA 5] Center 32 (2~63) winsize 62
3981 23:14:35.252052
3982 23:14:35.254949 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3983 23:14:35.255029
3984 23:14:35.258100 [CATrainingPosCal] consider 1 rank data
3985 23:14:35.261423 u2DelayCellTimex100 = 270/100 ps
3986 23:14:35.265212 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3987 23:14:35.268121 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3988 23:14:35.271416 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3989 23:14:35.274721 CA3 delay=33 (2~64),Diff = 1 PI (9 cell)
3990 23:14:35.278225 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3991 23:14:35.284561 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3992 23:14:35.284641
3993 23:14:35.288186 CA PerBit enable=1, Macro0, CA PI delay=32
3994 23:14:35.288267
3995 23:14:35.291666 [CBTSetCACLKResult] CA Dly = 32
3996 23:14:35.291746 CS Dly: 4 (0~35)
3997 23:14:35.291808 ==
3998 23:14:35.294478 Dram Type= 6, Freq= 0, CH_0, rank 1
3999 23:14:35.297858 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4000 23:14:35.297938 ==
4001 23:14:35.304605 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4002 23:14:35.311302 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4003 23:14:35.314750 [CA 0] Center 36 (5~67) winsize 63
4004 23:14:35.317795 [CA 1] Center 36 (5~67) winsize 63
4005 23:14:35.321359 [CA 2] Center 34 (3~65) winsize 63
4006 23:14:35.324982 [CA 3] Center 33 (3~64) winsize 62
4007 23:14:35.328098 [CA 4] Center 33 (2~64) winsize 63
4008 23:14:35.331674 [CA 5] Center 32 (2~63) winsize 62
4009 23:14:35.331755
4010 23:14:35.334778 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4011 23:14:35.334859
4012 23:14:35.337854 [CATrainingPosCal] consider 2 rank data
4013 23:14:35.341304 u2DelayCellTimex100 = 270/100 ps
4014 23:14:35.344823 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
4015 23:14:35.347998 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
4016 23:14:35.351618 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
4017 23:14:35.354405 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
4018 23:14:35.361592 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
4019 23:14:35.364830 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
4020 23:14:35.364910
4021 23:14:35.367963 CA PerBit enable=1, Macro0, CA PI delay=32
4022 23:14:35.368043
4023 23:14:35.371615 [CBTSetCACLKResult] CA Dly = 32
4024 23:14:35.371696 CS Dly: 4 (0~36)
4025 23:14:35.371760
4026 23:14:35.374605 ----->DramcWriteLeveling(PI) begin...
4027 23:14:35.374687 ==
4028 23:14:35.377707 Dram Type= 6, Freq= 0, CH_0, rank 0
4029 23:14:35.384192 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4030 23:14:35.384277 ==
4031 23:14:35.387956 Write leveling (Byte 0): 33 => 33
4032 23:14:35.391126 Write leveling (Byte 1): 30 => 30
4033 23:14:35.391207 DramcWriteLeveling(PI) end<-----
4034 23:14:35.391271
4035 23:14:35.394189 ==
4036 23:14:35.397724 Dram Type= 6, Freq= 0, CH_0, rank 0
4037 23:14:35.400765 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4038 23:14:35.400846 ==
4039 23:14:35.404446 [Gating] SW mode calibration
4040 23:14:35.411101 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4041 23:14:35.414025 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4042 23:14:35.420582 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4043 23:14:35.424213 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4044 23:14:35.427255 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4045 23:14:35.434115 0 9 12 | B1->B0 | 3434 2d2d | 1 1 | (1 1) (0 1)
4046 23:14:35.437150 0 9 16 | B1->B0 | 3131 2323 | 1 0 | (1 1) (0 0)
4047 23:14:35.440772 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4048 23:14:35.447526 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4049 23:14:35.450674 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4050 23:14:35.454162 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4051 23:14:35.460738 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4052 23:14:35.464121 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4053 23:14:35.467053 0 10 12 | B1->B0 | 2323 3c3c | 0 0 | (0 0) (0 0)
4054 23:14:35.473847 0 10 16 | B1->B0 | 3333 4646 | 0 0 | (1 1) (0 0)
4055 23:14:35.477226 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4056 23:14:35.480590 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4057 23:14:35.487305 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4058 23:14:35.490646 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4059 23:14:35.493879 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4060 23:14:35.500481 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4061 23:14:35.503631 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4062 23:14:35.507362 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4063 23:14:35.510242 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4064 23:14:35.516922 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4065 23:14:35.520454 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4066 23:14:35.523665 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4067 23:14:35.530522 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4068 23:14:35.533599 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4069 23:14:35.536949 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4070 23:14:35.543757 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4071 23:14:35.547086 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4072 23:14:35.550473 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4073 23:14:35.556912 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4074 23:14:35.560247 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4075 23:14:35.563520 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4076 23:14:35.570313 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4077 23:14:35.573351 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4078 23:14:35.577237 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4079 23:14:35.580539 Total UI for P1: 0, mck2ui 16
4080 23:14:35.583782 best dqsien dly found for B0: ( 0, 13, 12)
4081 23:14:35.589920 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4082 23:14:35.590004 Total UI for P1: 0, mck2ui 16
4083 23:14:35.596955 best dqsien dly found for B1: ( 0, 13, 16)
4084 23:14:35.600033 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4085 23:14:35.603790 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4086 23:14:35.603872
4087 23:14:35.606881 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4088 23:14:35.609932 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4089 23:14:35.613505 [Gating] SW calibration Done
4090 23:14:35.613585 ==
4091 23:14:35.616634 Dram Type= 6, Freq= 0, CH_0, rank 0
4092 23:14:35.620429 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4093 23:14:35.620511 ==
4094 23:14:35.623544 RX Vref Scan: 0
4095 23:14:35.623625
4096 23:14:35.623689 RX Vref 0 -> 0, step: 1
4097 23:14:35.623748
4098 23:14:35.627125 RX Delay -230 -> 252, step: 16
4099 23:14:35.630252 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4100 23:14:35.636907 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4101 23:14:35.640072 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4102 23:14:35.643788 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4103 23:14:35.646766 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4104 23:14:35.653415 iDelay=218, Bit 5, Center 49 (-102 ~ 201) 304
4105 23:14:35.656470 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4106 23:14:35.659826 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4107 23:14:35.663176 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4108 23:14:35.666547 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4109 23:14:35.673238 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4110 23:14:35.676442 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4111 23:14:35.680084 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4112 23:14:35.683153 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4113 23:14:35.689850 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4114 23:14:35.693178 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4115 23:14:35.693259 ==
4116 23:14:35.696589 Dram Type= 6, Freq= 0, CH_0, rank 0
4117 23:14:35.700101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4118 23:14:35.700223 ==
4119 23:14:35.703035 DQS Delay:
4120 23:14:35.703157 DQS0 = 0, DQS1 = 0
4121 23:14:35.703267 DQM Delay:
4122 23:14:35.706726 DQM0 = 52, DQM1 = 46
4123 23:14:35.706849 DQ Delay:
4124 23:14:35.709848 DQ0 =49, DQ1 =57, DQ2 =49, DQ3 =49
4125 23:14:35.713411 DQ4 =49, DQ5 =49, DQ6 =57, DQ7 =57
4126 23:14:35.716565 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4127 23:14:35.720169 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =57
4128 23:14:35.720250
4129 23:14:35.720356
4130 23:14:35.720416 ==
4131 23:14:35.723220 Dram Type= 6, Freq= 0, CH_0, rank 0
4132 23:14:35.729912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4133 23:14:35.729994 ==
4134 23:14:35.730058
4135 23:14:35.730116
4136 23:14:35.730173 TX Vref Scan disable
4137 23:14:35.733685 == TX Byte 0 ==
4138 23:14:35.736738 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4139 23:14:35.740347 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4140 23:14:35.743422 == TX Byte 1 ==
4141 23:14:35.747157 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4142 23:14:35.750220 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4143 23:14:35.753377 ==
4144 23:14:35.757016 Dram Type= 6, Freq= 0, CH_0, rank 0
4145 23:14:35.760146 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4146 23:14:35.760229 ==
4147 23:14:35.760364
4148 23:14:35.760445
4149 23:14:35.763779 TX Vref Scan disable
4150 23:14:35.766600 == TX Byte 0 ==
4151 23:14:35.770222 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4152 23:14:35.773268 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4153 23:14:35.777111 == TX Byte 1 ==
4154 23:14:35.780100 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4155 23:14:35.783127 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4156 23:14:35.783211
4157 23:14:35.783296 [DATLAT]
4158 23:14:35.786536 Freq=600, CH0 RK0
4159 23:14:35.786620
4160 23:14:35.786705 DATLAT Default: 0x9
4161 23:14:35.789934 0, 0xFFFF, sum = 0
4162 23:14:35.793082 1, 0xFFFF, sum = 0
4163 23:14:35.793167 2, 0xFFFF, sum = 0
4164 23:14:35.796650 3, 0xFFFF, sum = 0
4165 23:14:35.796735 4, 0xFFFF, sum = 0
4166 23:14:35.799776 5, 0xFFFF, sum = 0
4167 23:14:35.799864 6, 0xFFFF, sum = 0
4168 23:14:35.803406 7, 0xFFFF, sum = 0
4169 23:14:35.803491 8, 0x0, sum = 1
4170 23:14:35.806638 9, 0x0, sum = 2
4171 23:14:35.806722 10, 0x0, sum = 3
4172 23:14:35.806809 11, 0x0, sum = 4
4173 23:14:35.810105 best_step = 9
4174 23:14:35.810188
4175 23:14:35.810273 ==
4176 23:14:35.813332 Dram Type= 6, Freq= 0, CH_0, rank 0
4177 23:14:35.816665 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4178 23:14:35.816749 ==
4179 23:14:35.819749 RX Vref Scan: 1
4180 23:14:35.819833
4181 23:14:35.819918 RX Vref 0 -> 0, step: 1
4182 23:14:35.819999
4183 23:14:35.823441 RX Delay -163 -> 252, step: 8
4184 23:14:35.823524
4185 23:14:35.826613 Set Vref, RX VrefLevel [Byte0]: 55
4186 23:14:35.829531 [Byte1]: 49
4187 23:14:35.834051
4188 23:14:35.834134 Final RX Vref Byte 0 = 55 to rank0
4189 23:14:35.837399 Final RX Vref Byte 1 = 49 to rank0
4190 23:14:35.840645 Final RX Vref Byte 0 = 55 to rank1
4191 23:14:35.843799 Final RX Vref Byte 1 = 49 to rank1==
4192 23:14:35.847201 Dram Type= 6, Freq= 0, CH_0, rank 0
4193 23:14:35.854009 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4194 23:14:35.854093 ==
4195 23:14:35.854180 DQS Delay:
4196 23:14:35.854261 DQS0 = 0, DQS1 = 0
4197 23:14:35.857093 DQM Delay:
4198 23:14:35.857176 DQM0 = 53, DQM1 = 46
4199 23:14:35.860815 DQ Delay:
4200 23:14:35.863892 DQ0 =52, DQ1 =56, DQ2 =48, DQ3 =52
4201 23:14:35.863975 DQ4 =52, DQ5 =44, DQ6 =60, DQ7 =60
4202 23:14:35.867501 DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =40
4203 23:14:35.870578 DQ12 =52, DQ13 =48, DQ14 =56, DQ15 =52
4204 23:14:35.873932
4205 23:14:35.874012
4206 23:14:35.880782 [DQSOSCAuto] RK0, (LSB)MR18= 0x6c5f, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 389 ps
4207 23:14:35.883872 CH0 RK0: MR19=808, MR18=6C5F
4208 23:14:35.890578 CH0_RK0: MR19=0x808, MR18=0x6C5F, DQSOSC=389, MR23=63, INC=173, DEC=115
4209 23:14:35.890657
4210 23:14:35.894140 ----->DramcWriteLeveling(PI) begin...
4211 23:14:35.894220 ==
4212 23:14:35.897017 Dram Type= 6, Freq= 0, CH_0, rank 1
4213 23:14:35.900502 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4214 23:14:35.900582 ==
4215 23:14:35.904016 Write leveling (Byte 0): 34 => 34
4216 23:14:35.907115 Write leveling (Byte 1): 32 => 32
4217 23:14:35.910390 DramcWriteLeveling(PI) end<-----
4218 23:14:35.910469
4219 23:14:35.910530 ==
4220 23:14:35.913874 Dram Type= 6, Freq= 0, CH_0, rank 1
4221 23:14:35.917079 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4222 23:14:35.917183 ==
4223 23:14:35.920476 [Gating] SW mode calibration
4224 23:14:35.927002 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4225 23:14:35.933790 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4226 23:14:35.936777 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4227 23:14:35.943596 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4228 23:14:35.946431 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4229 23:14:35.950315 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
4230 23:14:35.956520 0 9 16 | B1->B0 | 2f2f 2828 | 1 0 | (1 0) (0 0)
4231 23:14:35.960102 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4232 23:14:35.963019 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4233 23:14:35.966525 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4234 23:14:35.973448 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4235 23:14:35.976480 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4236 23:14:35.979848 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4237 23:14:35.986463 0 10 12 | B1->B0 | 2b2b 2828 | 0 0 | (0 0) (1 1)
4238 23:14:35.989701 0 10 16 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
4239 23:14:35.993485 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4240 23:14:35.999627 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4241 23:14:36.003089 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4242 23:14:36.006324 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4243 23:14:36.012914 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4244 23:14:36.016597 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4245 23:14:36.019853 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4246 23:14:36.026452 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4247 23:14:36.029951 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4248 23:14:36.033033 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4249 23:14:36.039763 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4250 23:14:36.042952 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4251 23:14:36.045997 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4252 23:14:36.052661 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4253 23:14:36.056192 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4254 23:14:36.059275 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4255 23:14:36.065756 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4256 23:14:36.069198 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4257 23:14:36.072623 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4258 23:14:36.079264 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4259 23:14:36.082545 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4260 23:14:36.085888 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4261 23:14:36.092781 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4262 23:14:36.095770 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4263 23:14:36.098822 Total UI for P1: 0, mck2ui 16
4264 23:14:36.102547 best dqsien dly found for B0: ( 0, 13, 12)
4265 23:14:36.105639 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4266 23:14:36.109179 Total UI for P1: 0, mck2ui 16
4267 23:14:36.112066 best dqsien dly found for B1: ( 0, 13, 14)
4268 23:14:36.115525 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4269 23:14:36.119077 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4270 23:14:36.119160
4271 23:14:36.125621 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4272 23:14:36.129139 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4273 23:14:36.129224 [Gating] SW calibration Done
4274 23:14:36.132203 ==
4275 23:14:36.135631 Dram Type= 6, Freq= 0, CH_0, rank 1
4276 23:14:36.139231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4277 23:14:36.139315 ==
4278 23:14:36.139401 RX Vref Scan: 0
4279 23:14:36.139482
4280 23:14:36.142317 RX Vref 0 -> 0, step: 1
4281 23:14:36.142401
4282 23:14:36.145704 RX Delay -230 -> 252, step: 16
4283 23:14:36.149241 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4284 23:14:36.152234 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4285 23:14:36.159482 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4286 23:14:36.162388 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4287 23:14:36.165547 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4288 23:14:36.168697 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4289 23:14:36.172501 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4290 23:14:36.178789 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4291 23:14:36.182210 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4292 23:14:36.186002 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4293 23:14:36.188829 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4294 23:14:36.195525 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4295 23:14:36.198848 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4296 23:14:36.202002 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4297 23:14:36.205772 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4298 23:14:36.211962 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4299 23:14:36.212083 ==
4300 23:14:36.215599 Dram Type= 6, Freq= 0, CH_0, rank 1
4301 23:14:36.219125 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4302 23:14:36.219209 ==
4303 23:14:36.219296 DQS Delay:
4304 23:14:36.222096 DQS0 = 0, DQS1 = 0
4305 23:14:36.222180 DQM Delay:
4306 23:14:36.225596 DQM0 = 51, DQM1 = 43
4307 23:14:36.225680 DQ Delay:
4308 23:14:36.229266 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =49
4309 23:14:36.232189 DQ4 =57, DQ5 =41, DQ6 =57, DQ7 =57
4310 23:14:36.235626 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =33
4311 23:14:36.238898 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4312 23:14:36.238982
4313 23:14:36.239067
4314 23:14:36.239148 ==
4315 23:14:36.241918 Dram Type= 6, Freq= 0, CH_0, rank 1
4316 23:14:36.245430 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4317 23:14:36.245513 ==
4318 23:14:36.245599
4319 23:14:36.245680
4320 23:14:36.248769 TX Vref Scan disable
4321 23:14:36.252271 == TX Byte 0 ==
4322 23:14:36.255465 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4323 23:14:36.258738 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4324 23:14:36.262004 == TX Byte 1 ==
4325 23:14:36.265195 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4326 23:14:36.268864 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4327 23:14:36.268947 ==
4328 23:14:36.272443 Dram Type= 6, Freq= 0, CH_0, rank 1
4329 23:14:36.278543 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4330 23:14:36.278627 ==
4331 23:14:36.278712
4332 23:14:36.278793
4333 23:14:36.278872 TX Vref Scan disable
4334 23:14:36.283354 == TX Byte 0 ==
4335 23:14:36.286222 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4336 23:14:36.292634 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4337 23:14:36.292718 == TX Byte 1 ==
4338 23:14:36.296277 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4339 23:14:36.303069 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4340 23:14:36.303153
4341 23:14:36.303238 [DATLAT]
4342 23:14:36.303318 Freq=600, CH0 RK1
4343 23:14:36.303397
4344 23:14:36.306337 DATLAT Default: 0x9
4345 23:14:36.306420 0, 0xFFFF, sum = 0
4346 23:14:36.309434 1, 0xFFFF, sum = 0
4347 23:14:36.312699 2, 0xFFFF, sum = 0
4348 23:14:36.312783 3, 0xFFFF, sum = 0
4349 23:14:36.316107 4, 0xFFFF, sum = 0
4350 23:14:36.316192 5, 0xFFFF, sum = 0
4351 23:14:36.319124 6, 0xFFFF, sum = 0
4352 23:14:36.319209 7, 0xFFFF, sum = 0
4353 23:14:36.322886 8, 0x0, sum = 1
4354 23:14:36.322972 9, 0x0, sum = 2
4355 23:14:36.323059 10, 0x0, sum = 3
4356 23:14:36.326278 11, 0x0, sum = 4
4357 23:14:36.326363 best_step = 9
4358 23:14:36.326451
4359 23:14:36.326533 ==
4360 23:14:36.329239 Dram Type= 6, Freq= 0, CH_0, rank 1
4361 23:14:36.336215 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4362 23:14:36.336308 ==
4363 23:14:36.336386 RX Vref Scan: 0
4364 23:14:36.336446
4365 23:14:36.339394 RX Vref 0 -> 0, step: 1
4366 23:14:36.339474
4367 23:14:36.343072 RX Delay -163 -> 252, step: 8
4368 23:14:36.346024 iDelay=197, Bit 0, Center 52 (-91 ~ 196) 288
4369 23:14:36.352600 iDelay=197, Bit 1, Center 52 (-91 ~ 196) 288
4370 23:14:36.356057 iDelay=197, Bit 2, Center 48 (-99 ~ 196) 296
4371 23:14:36.359678 iDelay=197, Bit 3, Center 52 (-91 ~ 196) 288
4372 23:14:36.362623 iDelay=197, Bit 4, Center 52 (-91 ~ 196) 288
4373 23:14:36.366241 iDelay=197, Bit 5, Center 44 (-99 ~ 188) 288
4374 23:14:36.372939 iDelay=197, Bit 6, Center 56 (-83 ~ 196) 280
4375 23:14:36.375778 iDelay=197, Bit 7, Center 56 (-83 ~ 196) 280
4376 23:14:36.379306 iDelay=197, Bit 8, Center 40 (-99 ~ 180) 280
4377 23:14:36.382914 iDelay=197, Bit 9, Center 36 (-107 ~ 180) 288
4378 23:14:36.386030 iDelay=197, Bit 10, Center 48 (-91 ~ 188) 280
4379 23:14:36.392694 iDelay=197, Bit 11, Center 40 (-99 ~ 180) 280
4380 23:14:36.395953 iDelay=197, Bit 12, Center 52 (-83 ~ 188) 272
4381 23:14:36.398862 iDelay=197, Bit 13, Center 52 (-91 ~ 196) 288
4382 23:14:36.402697 iDelay=197, Bit 14, Center 56 (-83 ~ 196) 280
4383 23:14:36.405757 iDelay=197, Bit 15, Center 52 (-91 ~ 196) 288
4384 23:14:36.409478 ==
4385 23:14:36.412304 Dram Type= 6, Freq= 0, CH_0, rank 1
4386 23:14:36.415576 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4387 23:14:36.415657 ==
4388 23:14:36.415720 DQS Delay:
4389 23:14:36.418810 DQS0 = 0, DQS1 = 0
4390 23:14:36.418889 DQM Delay:
4391 23:14:36.422413 DQM0 = 51, DQM1 = 47
4392 23:14:36.422493 DQ Delay:
4393 23:14:36.425551 DQ0 =52, DQ1 =52, DQ2 =48, DQ3 =52
4394 23:14:36.428869 DQ4 =52, DQ5 =44, DQ6 =56, DQ7 =56
4395 23:14:36.432081 DQ8 =40, DQ9 =36, DQ10 =48, DQ11 =40
4396 23:14:36.435473 DQ12 =52, DQ13 =52, DQ14 =56, DQ15 =52
4397 23:14:36.435553
4398 23:14:36.435616
4399 23:14:36.442014 [DQSOSCAuto] RK1, (LSB)MR18= 0x6020, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 391 ps
4400 23:14:36.445754 CH0 RK1: MR19=808, MR18=6020
4401 23:14:36.452469 CH0_RK1: MR19=0x808, MR18=0x6020, DQSOSC=391, MR23=63, INC=171, DEC=114
4402 23:14:36.455554 [RxdqsGatingPostProcess] freq 600
4403 23:14:36.461965 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4404 23:14:36.462046 Pre-setting of DQS Precalculation
4405 23:14:36.468508 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4406 23:14:36.468588 ==
4407 23:14:36.472210 Dram Type= 6, Freq= 0, CH_1, rank 0
4408 23:14:36.475342 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4409 23:14:36.475422 ==
4410 23:14:36.482135 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4411 23:14:36.488838 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4412 23:14:36.491858 [CA 0] Center 36 (5~67) winsize 63
4413 23:14:36.495019 [CA 1] Center 36 (5~67) winsize 63
4414 23:14:36.498688 [CA 2] Center 35 (4~66) winsize 63
4415 23:14:36.501600 [CA 3] Center 34 (4~65) winsize 62
4416 23:14:36.504959 [CA 4] Center 34 (4~65) winsize 62
4417 23:14:36.508496 [CA 5] Center 34 (3~65) winsize 63
4418 23:14:36.508579
4419 23:14:36.511783 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4420 23:14:36.511891
4421 23:14:36.515238 [CATrainingPosCal] consider 1 rank data
4422 23:14:36.518483 u2DelayCellTimex100 = 270/100 ps
4423 23:14:36.521596 CA0 delay=36 (5~67),Diff = 2 PI (19 cell)
4424 23:14:36.525242 CA1 delay=36 (5~67),Diff = 2 PI (19 cell)
4425 23:14:36.528755 CA2 delay=35 (4~66),Diff = 1 PI (9 cell)
4426 23:14:36.531617 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4427 23:14:36.534972 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4428 23:14:36.538690 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4429 23:14:36.541661
4430 23:14:36.544996 CA PerBit enable=1, Macro0, CA PI delay=34
4431 23:14:36.545080
4432 23:14:36.548109 [CBTSetCACLKResult] CA Dly = 34
4433 23:14:36.548193 CS Dly: 6 (0~37)
4434 23:14:36.548301 ==
4435 23:14:36.551578 Dram Type= 6, Freq= 0, CH_1, rank 1
4436 23:14:36.554913 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4437 23:14:36.554997 ==
4438 23:14:36.561570 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4439 23:14:36.568018 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4440 23:14:36.571659 [CA 0] Center 36 (6~67) winsize 62
4441 23:14:36.574678 [CA 1] Center 36 (6~67) winsize 62
4442 23:14:36.578344 [CA 2] Center 35 (4~66) winsize 63
4443 23:14:36.581525 [CA 3] Center 35 (4~66) winsize 63
4444 23:14:36.584626 [CA 4] Center 35 (4~66) winsize 63
4445 23:14:36.588204 [CA 5] Center 34 (4~65) winsize 62
4446 23:14:36.588346
4447 23:14:36.591651 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4448 23:14:36.591734
4449 23:14:36.595010 [CATrainingPosCal] consider 2 rank data
4450 23:14:36.597728 u2DelayCellTimex100 = 270/100 ps
4451 23:14:36.601387 CA0 delay=36 (6~67),Diff = 2 PI (19 cell)
4452 23:14:36.604421 CA1 delay=36 (6~67),Diff = 2 PI (19 cell)
4453 23:14:36.608215 CA2 delay=35 (4~66),Diff = 1 PI (9 cell)
4454 23:14:36.611918 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4455 23:14:36.618378 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4456 23:14:36.621396 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4457 23:14:36.621479
4458 23:14:36.624450 CA PerBit enable=1, Macro0, CA PI delay=34
4459 23:14:36.624534
4460 23:14:36.628204 [CBTSetCACLKResult] CA Dly = 34
4461 23:14:36.628349 CS Dly: 6 (0~38)
4462 23:14:36.628435
4463 23:14:36.631251 ----->DramcWriteLeveling(PI) begin...
4464 23:14:36.631336 ==
4465 23:14:36.634362 Dram Type= 6, Freq= 0, CH_1, rank 0
4466 23:14:36.641038 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4467 23:14:36.641123 ==
4468 23:14:36.644300 Write leveling (Byte 0): 31 => 31
4469 23:14:36.644384 Write leveling (Byte 1): 29 => 29
4470 23:14:36.647817 DramcWriteLeveling(PI) end<-----
4471 23:14:36.647900
4472 23:14:36.651277 ==
4473 23:14:36.651361 Dram Type= 6, Freq= 0, CH_1, rank 0
4474 23:14:36.657669 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4475 23:14:36.657753 ==
4476 23:14:36.660985 [Gating] SW mode calibration
4477 23:14:36.667481 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4478 23:14:36.671145 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4479 23:14:36.677795 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4480 23:14:36.680815 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4481 23:14:36.684584 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4482 23:14:36.691033 0 9 12 | B1->B0 | 2f2f 2e2e | 1 1 | (1 1) (1 0)
4483 23:14:36.694211 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4484 23:14:36.697791 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4485 23:14:36.704445 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4486 23:14:36.708002 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4487 23:14:36.710881 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4488 23:14:36.717417 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4489 23:14:36.721065 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4490 23:14:36.723979 0 10 12 | B1->B0 | 3737 3939 | 0 1 | (0 0) (0 0)
4491 23:14:36.730740 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4492 23:14:36.734465 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4493 23:14:36.737424 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4494 23:14:36.744205 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4495 23:14:36.747346 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4496 23:14:36.751044 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4497 23:14:36.754043 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4498 23:14:36.760694 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4499 23:14:36.763874 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4500 23:14:36.767556 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4501 23:14:36.774296 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4502 23:14:36.777228 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4503 23:14:36.780656 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4504 23:14:36.787281 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4505 23:14:36.790875 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4506 23:14:36.793741 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4507 23:14:36.800634 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4508 23:14:36.804170 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4509 23:14:36.807017 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4510 23:14:36.814028 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4511 23:14:36.817362 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4512 23:14:36.820441 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4513 23:14:36.827058 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4514 23:14:36.830307 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4515 23:14:36.834068 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4516 23:14:36.837045 Total UI for P1: 0, mck2ui 16
4517 23:14:36.840653 best dqsien dly found for B0: ( 0, 13, 14)
4518 23:14:36.846776 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4519 23:14:36.846857 Total UI for P1: 0, mck2ui 16
4520 23:14:36.853676 best dqsien dly found for B1: ( 0, 13, 14)
4521 23:14:36.857281 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4522 23:14:36.860252 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4523 23:14:36.860378
4524 23:14:36.863360 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4525 23:14:36.867016 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4526 23:14:36.870264 [Gating] SW calibration Done
4527 23:14:36.870345 ==
4528 23:14:36.873657 Dram Type= 6, Freq= 0, CH_1, rank 0
4529 23:14:36.876740 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4530 23:14:36.876822 ==
4531 23:14:36.880318 RX Vref Scan: 0
4532 23:14:36.880398
4533 23:14:36.880461 RX Vref 0 -> 0, step: 1
4534 23:14:36.880520
4535 23:14:36.883817 RX Delay -230 -> 252, step: 16
4536 23:14:36.889859 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4537 23:14:36.893540 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4538 23:14:36.897147 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4539 23:14:36.899984 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4540 23:14:36.903415 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4541 23:14:36.910199 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4542 23:14:36.913444 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4543 23:14:36.916644 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4544 23:14:36.919893 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4545 23:14:36.926855 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4546 23:14:36.930116 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4547 23:14:36.933465 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4548 23:14:36.936701 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4549 23:14:36.939916 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4550 23:14:36.946614 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4551 23:14:36.950144 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4552 23:14:36.950224 ==
4553 23:14:36.953326 Dram Type= 6, Freq= 0, CH_1, rank 0
4554 23:14:36.956254 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4555 23:14:36.956383 ==
4556 23:14:36.959989 DQS Delay:
4557 23:14:36.960094 DQS0 = 0, DQS1 = 0
4558 23:14:36.963087 DQM Delay:
4559 23:14:36.963167 DQM0 = 47, DQM1 = 45
4560 23:14:36.963229 DQ Delay:
4561 23:14:36.966795 DQ0 =57, DQ1 =41, DQ2 =41, DQ3 =41
4562 23:14:36.969973 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4563 23:14:36.972975 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =41
4564 23:14:36.976551 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4565 23:14:36.976630
4566 23:14:36.976692
4567 23:14:36.976750 ==
4568 23:14:36.980100 Dram Type= 6, Freq= 0, CH_1, rank 0
4569 23:14:36.986517 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4570 23:14:36.986597 ==
4571 23:14:36.986659
4572 23:14:36.986717
4573 23:14:36.989678 TX Vref Scan disable
4574 23:14:36.989759 == TX Byte 0 ==
4575 23:14:36.993327 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4576 23:14:36.999554 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4577 23:14:36.999635 == TX Byte 1 ==
4578 23:14:37.003225 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4579 23:14:37.009640 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4580 23:14:37.009720 ==
4581 23:14:37.013118 Dram Type= 6, Freq= 0, CH_1, rank 0
4582 23:14:37.016047 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4583 23:14:37.016128 ==
4584 23:14:37.016193
4585 23:14:37.016251
4586 23:14:37.019709 TX Vref Scan disable
4587 23:14:37.022839 == TX Byte 0 ==
4588 23:14:37.026494 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4589 23:14:37.029369 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4590 23:14:37.032975 == TX Byte 1 ==
4591 23:14:37.036426 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4592 23:14:37.039343 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4593 23:14:37.039424
4594 23:14:37.042685 [DATLAT]
4595 23:14:37.042765 Freq=600, CH1 RK0
4596 23:14:37.042830
4597 23:14:37.046528 DATLAT Default: 0x9
4598 23:14:37.046608 0, 0xFFFF, sum = 0
4599 23:14:37.049870 1, 0xFFFF, sum = 0
4600 23:14:37.049953 2, 0xFFFF, sum = 0
4601 23:14:37.052932 3, 0xFFFF, sum = 0
4602 23:14:37.053015 4, 0xFFFF, sum = 0
4603 23:14:37.056185 5, 0xFFFF, sum = 0
4604 23:14:37.056270 6, 0xFFFF, sum = 0
4605 23:14:37.059970 7, 0xFFFF, sum = 0
4606 23:14:37.060052 8, 0x0, sum = 1
4607 23:14:37.062845 9, 0x0, sum = 2
4608 23:14:37.062927 10, 0x0, sum = 3
4609 23:14:37.065966 11, 0x0, sum = 4
4610 23:14:37.066048 best_step = 9
4611 23:14:37.066111
4612 23:14:37.066170 ==
4613 23:14:37.069721 Dram Type= 6, Freq= 0, CH_1, rank 0
4614 23:14:37.072883 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4615 23:14:37.072964 ==
4616 23:14:37.076558 RX Vref Scan: 1
4617 23:14:37.076639
4618 23:14:37.079566 RX Vref 0 -> 0, step: 1
4619 23:14:37.079650
4620 23:14:37.079714 RX Delay -163 -> 252, step: 8
4621 23:14:37.079773
4622 23:14:37.082712 Set Vref, RX VrefLevel [Byte0]: 54
4623 23:14:37.086347 [Byte1]: 55
4624 23:14:37.091152
4625 23:14:37.091232 Final RX Vref Byte 0 = 54 to rank0
4626 23:14:37.094305 Final RX Vref Byte 1 = 55 to rank0
4627 23:14:37.097767 Final RX Vref Byte 0 = 54 to rank1
4628 23:14:37.100822 Final RX Vref Byte 1 = 55 to rank1==
4629 23:14:37.104140 Dram Type= 6, Freq= 0, CH_1, rank 0
4630 23:14:37.110731 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4631 23:14:37.110812 ==
4632 23:14:37.110876 DQS Delay:
4633 23:14:37.110936 DQS0 = 0, DQS1 = 0
4634 23:14:37.114199 DQM Delay:
4635 23:14:37.114280 DQM0 = 48, DQM1 = 45
4636 23:14:37.117083 DQ Delay:
4637 23:14:37.120760 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4638 23:14:37.124175 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4639 23:14:37.127245 DQ8 =32, DQ9 =36, DQ10 =44, DQ11 =36
4640 23:14:37.130867 DQ12 =52, DQ13 =52, DQ14 =56, DQ15 =52
4641 23:14:37.130947
4642 23:14:37.131010
4643 23:14:37.137224 [DQSOSCAuto] RK0, (LSB)MR18= 0x4c72, (MSB)MR19= 0x808, tDQSOscB0 = 388 ps tDQSOscB1 = 395 ps
4644 23:14:37.140810 CH1 RK0: MR19=808, MR18=4C72
4645 23:14:37.147464 CH1_RK0: MR19=0x808, MR18=0x4C72, DQSOSC=388, MR23=63, INC=174, DEC=116
4646 23:14:37.147545
4647 23:14:37.150565 ----->DramcWriteLeveling(PI) begin...
4648 23:14:37.150647 ==
4649 23:14:37.154001 Dram Type= 6, Freq= 0, CH_1, rank 1
4650 23:14:37.157537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4651 23:14:37.157618 ==
4652 23:14:37.160426 Write leveling (Byte 0): 29 => 29
4653 23:14:37.163762 Write leveling (Byte 1): 32 => 32
4654 23:14:37.167127 DramcWriteLeveling(PI) end<-----
4655 23:14:37.167208
4656 23:14:37.167272 ==
4657 23:14:37.170666 Dram Type= 6, Freq= 0, CH_1, rank 1
4658 23:14:37.174107 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4659 23:14:37.174186 ==
4660 23:14:37.176987 [Gating] SW mode calibration
4661 23:14:37.183676 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4662 23:14:37.190418 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4663 23:14:37.193453 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4664 23:14:37.200103 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4665 23:14:37.203813 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
4666 23:14:37.206975 0 9 12 | B1->B0 | 2e2e 2c2c | 1 1 | (1 0) (1 0)
4667 23:14:37.213688 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4668 23:14:37.217095 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4669 23:14:37.220225 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4670 23:14:37.226732 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4671 23:14:37.229894 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4672 23:14:37.233692 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4673 23:14:37.236603 0 10 8 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
4674 23:14:37.243679 0 10 12 | B1->B0 | 3838 3737 | 0 0 | (0 0) (1 1)
4675 23:14:37.246638 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4676 23:14:37.250209 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4677 23:14:37.256866 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4678 23:14:37.260003 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4679 23:14:37.263566 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4680 23:14:37.269926 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4681 23:14:37.272894 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4682 23:14:37.276488 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4683 23:14:37.283060 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4684 23:14:37.286392 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4685 23:14:37.289554 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4686 23:14:37.296230 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4687 23:14:37.300054 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4688 23:14:37.302887 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4689 23:14:37.309821 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4690 23:14:37.312803 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4691 23:14:37.316335 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4692 23:14:37.322971 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4693 23:14:37.326493 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4694 23:14:37.329943 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4695 23:14:37.336396 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4696 23:14:37.339296 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4697 23:14:37.342599 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4698 23:14:37.349401 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4699 23:14:37.349482 Total UI for P1: 0, mck2ui 16
4700 23:14:37.356333 best dqsien dly found for B0: ( 0, 13, 10)
4701 23:14:37.359548 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4702 23:14:37.363097 Total UI for P1: 0, mck2ui 16
4703 23:14:37.366171 best dqsien dly found for B1: ( 0, 13, 12)
4704 23:14:37.369159 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4705 23:14:37.372596 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4706 23:14:37.372677
4707 23:14:37.375784 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4708 23:14:37.379484 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4709 23:14:37.382655 [Gating] SW calibration Done
4710 23:14:37.382735 ==
4711 23:14:37.386212 Dram Type= 6, Freq= 0, CH_1, rank 1
4712 23:14:37.389461 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4713 23:14:37.392893 ==
4714 23:14:37.392973 RX Vref Scan: 0
4715 23:14:37.393037
4716 23:14:37.395671 RX Vref 0 -> 0, step: 1
4717 23:14:37.395753
4718 23:14:37.399485 RX Delay -230 -> 252, step: 16
4719 23:14:37.402402 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4720 23:14:37.406086 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4721 23:14:37.409234 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4722 23:14:37.412412 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4723 23:14:37.419075 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4724 23:14:37.422666 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4725 23:14:37.425660 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4726 23:14:37.429184 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4727 23:14:37.435621 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4728 23:14:37.439219 iDelay=218, Bit 9, Center 41 (-118 ~ 201) 320
4729 23:14:37.442203 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4730 23:14:37.445704 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4731 23:14:37.452059 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4732 23:14:37.455422 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4733 23:14:37.459143 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4734 23:14:37.462117 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4735 23:14:37.462198 ==
4736 23:14:37.465623 Dram Type= 6, Freq= 0, CH_1, rank 1
4737 23:14:37.472268 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4738 23:14:37.472358 ==
4739 23:14:37.472422 DQS Delay:
4740 23:14:37.475434 DQS0 = 0, DQS1 = 0
4741 23:14:37.475514 DQM Delay:
4742 23:14:37.475577 DQM0 = 49, DQM1 = 48
4743 23:14:37.479059 DQ Delay:
4744 23:14:37.482493 DQ0 =49, DQ1 =49, DQ2 =33, DQ3 =49
4745 23:14:37.485334 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4746 23:14:37.489042 DQ8 =33, DQ9 =41, DQ10 =49, DQ11 =41
4747 23:14:37.491952 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =57
4748 23:14:37.492032
4749 23:14:37.492095
4750 23:14:37.492154 ==
4751 23:14:37.495531 Dram Type= 6, Freq= 0, CH_1, rank 1
4752 23:14:37.499047 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4753 23:14:37.499129 ==
4754 23:14:37.499192
4755 23:14:37.499250
4756 23:14:37.502365 TX Vref Scan disable
4757 23:14:37.502445 == TX Byte 0 ==
4758 23:14:37.509093 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4759 23:14:37.512094 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4760 23:14:37.512175 == TX Byte 1 ==
4761 23:14:37.518900 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4762 23:14:37.521845 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4763 23:14:37.521926 ==
4764 23:14:37.525448 Dram Type= 6, Freq= 0, CH_1, rank 1
4765 23:14:37.528928 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4766 23:14:37.529010 ==
4767 23:14:37.529074
4768 23:14:37.532017
4769 23:14:37.532104 TX Vref Scan disable
4770 23:14:37.535493 == TX Byte 0 ==
4771 23:14:37.539018 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4772 23:14:37.542533 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4773 23:14:37.545507 == TX Byte 1 ==
4774 23:14:37.549226 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4775 23:14:37.552385 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4776 23:14:37.555545
4777 23:14:37.555624 [DATLAT]
4778 23:14:37.555688 Freq=600, CH1 RK1
4779 23:14:37.555748
4780 23:14:37.558946 DATLAT Default: 0x9
4781 23:14:37.559027 0, 0xFFFF, sum = 0
4782 23:14:37.562084 1, 0xFFFF, sum = 0
4783 23:14:37.562166 2, 0xFFFF, sum = 0
4784 23:14:37.565734 3, 0xFFFF, sum = 0
4785 23:14:37.565817 4, 0xFFFF, sum = 0
4786 23:14:37.568590 5, 0xFFFF, sum = 0
4787 23:14:37.572388 6, 0xFFFF, sum = 0
4788 23:14:37.572470 7, 0xFFFF, sum = 0
4789 23:14:37.572536 8, 0x0, sum = 1
4790 23:14:37.575417 9, 0x0, sum = 2
4791 23:14:37.575502 10, 0x0, sum = 3
4792 23:14:37.578472 11, 0x0, sum = 4
4793 23:14:37.578554 best_step = 9
4794 23:14:37.578618
4795 23:14:37.578677 ==
4796 23:14:37.582418 Dram Type= 6, Freq= 0, CH_1, rank 1
4797 23:14:37.589009 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4798 23:14:37.589090 ==
4799 23:14:37.589154 RX Vref Scan: 0
4800 23:14:37.589214
4801 23:14:37.591862 RX Vref 0 -> 0, step: 1
4802 23:14:37.591943
4803 23:14:37.595918 RX Delay -163 -> 252, step: 8
4804 23:14:37.599009 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4805 23:14:37.605649 iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288
4806 23:14:37.608565 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4807 23:14:37.611759 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4808 23:14:37.615322 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4809 23:14:37.618401 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4810 23:14:37.625003 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4811 23:14:37.628747 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4812 23:14:37.631819 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4813 23:14:37.635299 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4814 23:14:37.638770 iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296
4815 23:14:37.645528 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4816 23:14:37.648397 iDelay=205, Bit 12, Center 56 (-91 ~ 204) 296
4817 23:14:37.651468 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4818 23:14:37.655124 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4819 23:14:37.658118 iDelay=205, Bit 15, Center 56 (-91 ~ 204) 296
4820 23:14:37.661667 ==
4821 23:14:37.664981 Dram Type= 6, Freq= 0, CH_1, rank 1
4822 23:14:37.668684 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4823 23:14:37.668771 ==
4824 23:14:37.668835 DQS Delay:
4825 23:14:37.671697 DQS0 = 0, DQS1 = 0
4826 23:14:37.671778 DQM Delay:
4827 23:14:37.675469 DQM0 = 49, DQM1 = 46
4828 23:14:37.675549 DQ Delay:
4829 23:14:37.678509 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4830 23:14:37.681966 DQ4 =48, DQ5 =60, DQ6 =60, DQ7 =48
4831 23:14:37.684848 DQ8 =32, DQ9 =32, DQ10 =48, DQ11 =40
4832 23:14:37.688271 DQ12 =56, DQ13 =52, DQ14 =52, DQ15 =56
4833 23:14:37.688386
4834 23:14:37.688451
4835 23:14:37.695232 [DQSOSCAuto] RK1, (LSB)MR18= 0x681f, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 390 ps
4836 23:14:37.698026 CH1 RK1: MR19=808, MR18=681F
4837 23:14:37.705172 CH1_RK1: MR19=0x808, MR18=0x681F, DQSOSC=390, MR23=63, INC=172, DEC=114
4838 23:14:37.708091 [RxdqsGatingPostProcess] freq 600
4839 23:14:37.715140 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4840 23:14:37.715234 Pre-setting of DQS Precalculation
4841 23:14:37.721489 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4842 23:14:37.728474 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4843 23:14:37.735114 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4844 23:14:37.735230
4845 23:14:37.735297
4846 23:14:37.738181 [Calibration Summary] 1200 Mbps
4847 23:14:37.741841 CH 0, Rank 0
4848 23:14:37.741933 SW Impedance : PASS
4849 23:14:37.744878 DUTY Scan : NO K
4850 23:14:37.744960 ZQ Calibration : PASS
4851 23:14:37.748411 Jitter Meter : NO K
4852 23:14:37.751975 CBT Training : PASS
4853 23:14:37.752058 Write leveling : PASS
4854 23:14:37.755305 RX DQS gating : PASS
4855 23:14:37.758402 RX DQ/DQS(RDDQC) : PASS
4856 23:14:37.758489 TX DQ/DQS : PASS
4857 23:14:37.761500 RX DATLAT : PASS
4858 23:14:37.765306 RX DQ/DQS(Engine): PASS
4859 23:14:37.765392 TX OE : NO K
4860 23:14:37.768273 All Pass.
4861 23:14:37.768436
4862 23:14:37.768502 CH 0, Rank 1
4863 23:14:37.771798 SW Impedance : PASS
4864 23:14:37.771887 DUTY Scan : NO K
4865 23:14:37.774978 ZQ Calibration : PASS
4866 23:14:37.778034 Jitter Meter : NO K
4867 23:14:37.778121 CBT Training : PASS
4868 23:14:37.781887 Write leveling : PASS
4869 23:14:37.784844 RX DQS gating : PASS
4870 23:14:37.784936 RX DQ/DQS(RDDQC) : PASS
4871 23:14:37.788308 TX DQ/DQS : PASS
4872 23:14:37.788407 RX DATLAT : PASS
4873 23:14:37.791527 RX DQ/DQS(Engine): PASS
4874 23:14:37.795328 TX OE : NO K
4875 23:14:37.795421 All Pass.
4876 23:14:37.795486
4877 23:14:37.795546 CH 1, Rank 0
4878 23:14:37.798202 SW Impedance : PASS
4879 23:14:37.801325 DUTY Scan : NO K
4880 23:14:37.801411 ZQ Calibration : PASS
4881 23:14:37.805122 Jitter Meter : NO K
4882 23:14:37.808109 CBT Training : PASS
4883 23:14:37.808191 Write leveling : PASS
4884 23:14:37.811352 RX DQS gating : PASS
4885 23:14:37.814883 RX DQ/DQS(RDDQC) : PASS
4886 23:14:37.814970 TX DQ/DQS : PASS
4887 23:14:37.817907 RX DATLAT : PASS
4888 23:14:37.821678 RX DQ/DQS(Engine): PASS
4889 23:14:37.821789 TX OE : NO K
4890 23:14:37.824816 All Pass.
4891 23:14:37.824903
4892 23:14:37.824968 CH 1, Rank 1
4893 23:14:37.827774 SW Impedance : PASS
4894 23:14:37.827856 DUTY Scan : NO K
4895 23:14:37.831348 ZQ Calibration : PASS
4896 23:14:37.834489 Jitter Meter : NO K
4897 23:14:37.834581 CBT Training : PASS
4898 23:14:37.838039 Write leveling : PASS
4899 23:14:37.838120 RX DQS gating : PASS
4900 23:14:37.841476 RX DQ/DQS(RDDQC) : PASS
4901 23:14:37.844611 TX DQ/DQS : PASS
4902 23:14:37.844693 RX DATLAT : PASS
4903 23:14:37.847860 RX DQ/DQS(Engine): PASS
4904 23:14:37.851493 TX OE : NO K
4905 23:14:37.851578 All Pass.
4906 23:14:37.851642
4907 23:14:37.854452 DramC Write-DBI off
4908 23:14:37.854533 PER_BANK_REFRESH: Hybrid Mode
4909 23:14:37.858079 TX_TRACKING: ON
4910 23:14:37.864510 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4911 23:14:37.871251 [FAST_K] Save calibration result to emmc
4912 23:14:37.875018 dramc_set_vcore_voltage set vcore to 662500
4913 23:14:37.875099 Read voltage for 933, 3
4914 23:14:37.877769 Vio18 = 0
4915 23:14:37.877849 Vcore = 662500
4916 23:14:37.877912 Vdram = 0
4917 23:14:37.881324 Vddq = 0
4918 23:14:37.881404 Vmddr = 0
4919 23:14:37.884773 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4920 23:14:37.891390 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4921 23:14:37.894416 MEM_TYPE=3, freq_sel=17
4922 23:14:37.898126 sv_algorithm_assistance_LP4_1600
4923 23:14:37.901181 ============ PULL DRAM RESETB DOWN ============
4924 23:14:37.904925 ========== PULL DRAM RESETB DOWN end =========
4925 23:14:37.908082 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4926 23:14:37.911210 ===================================
4927 23:14:37.914923 LPDDR4 DRAM CONFIGURATION
4928 23:14:37.917820 ===================================
4929 23:14:37.921122 EX_ROW_EN[0] = 0x0
4930 23:14:37.921202 EX_ROW_EN[1] = 0x0
4931 23:14:37.924545 LP4Y_EN = 0x0
4932 23:14:37.924626 WORK_FSP = 0x0
4933 23:14:37.928192 WL = 0x3
4934 23:14:37.928273 RL = 0x3
4935 23:14:37.930932 BL = 0x2
4936 23:14:37.931013 RPST = 0x0
4937 23:14:37.934326 RD_PRE = 0x0
4938 23:14:37.934406 WR_PRE = 0x1
4939 23:14:37.938374 WR_PST = 0x0
4940 23:14:37.941547 DBI_WR = 0x0
4941 23:14:37.941627 DBI_RD = 0x0
4942 23:14:37.944278 OTF = 0x1
4943 23:14:37.947842 ===================================
4944 23:14:37.951025 ===================================
4945 23:14:37.951106 ANA top config
4946 23:14:37.954264 ===================================
4947 23:14:37.958131 DLL_ASYNC_EN = 0
4948 23:14:37.958212 ALL_SLAVE_EN = 1
4949 23:14:37.961082 NEW_RANK_MODE = 1
4950 23:14:37.964727 DLL_IDLE_MODE = 1
4951 23:14:37.968048 LP45_APHY_COMB_EN = 1
4952 23:14:37.971155 TX_ODT_DIS = 1
4953 23:14:37.971237 NEW_8X_MODE = 1
4954 23:14:37.974796 ===================================
4955 23:14:37.977833 ===================================
4956 23:14:37.980931 data_rate = 1866
4957 23:14:37.984653 CKR = 1
4958 23:14:37.987634 DQ_P2S_RATIO = 8
4959 23:14:37.991117 ===================================
4960 23:14:37.994290 CA_P2S_RATIO = 8
4961 23:14:37.997729 DQ_CA_OPEN = 0
4962 23:14:37.997810 DQ_SEMI_OPEN = 0
4963 23:14:38.000902 CA_SEMI_OPEN = 0
4964 23:14:38.004646 CA_FULL_RATE = 0
4965 23:14:38.007646 DQ_CKDIV4_EN = 1
4966 23:14:38.010744 CA_CKDIV4_EN = 1
4967 23:14:38.014360 CA_PREDIV_EN = 0
4968 23:14:38.014442 PH8_DLY = 0
4969 23:14:38.017482 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4970 23:14:38.021105 DQ_AAMCK_DIV = 4
4971 23:14:38.024245 CA_AAMCK_DIV = 4
4972 23:14:38.027706 CA_ADMCK_DIV = 4
4973 23:14:38.027787 DQ_TRACK_CA_EN = 0
4974 23:14:38.031169 CA_PICK = 933
4975 23:14:38.034216 CA_MCKIO = 933
4976 23:14:38.037535 MCKIO_SEMI = 0
4977 23:14:38.040815 PLL_FREQ = 3732
4978 23:14:38.044334 DQ_UI_PI_RATIO = 32
4979 23:14:38.047837 CA_UI_PI_RATIO = 0
4980 23:14:38.051200 ===================================
4981 23:14:38.054099 ===================================
4982 23:14:38.054180 memory_type:LPDDR4
4983 23:14:38.057545 GP_NUM : 10
4984 23:14:38.061025 SRAM_EN : 1
4985 23:14:38.061106 MD32_EN : 0
4986 23:14:38.064018 ===================================
4987 23:14:38.067446 [ANA_INIT] >>>>>>>>>>>>>>
4988 23:14:38.071072 <<<<<< [CONFIGURE PHASE]: ANA_TX
4989 23:14:38.074138 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4990 23:14:38.077837 ===================================
4991 23:14:38.081062 data_rate = 1866,PCW = 0X8f00
4992 23:14:38.083991 ===================================
4993 23:14:38.087545 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4994 23:14:38.090602 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4995 23:14:38.097882 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4996 23:14:38.100646 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4997 23:14:38.103934 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4998 23:14:38.107413 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4999 23:14:38.111144 [ANA_INIT] flow start
5000 23:14:38.114204 [ANA_INIT] PLL >>>>>>>>
5001 23:14:38.114285 [ANA_INIT] PLL <<<<<<<<
5002 23:14:38.117270 [ANA_INIT] MIDPI >>>>>>>>
5003 23:14:38.121080 [ANA_INIT] MIDPI <<<<<<<<
5004 23:14:38.124128 [ANA_INIT] DLL >>>>>>>>
5005 23:14:38.124209 [ANA_INIT] flow end
5006 23:14:38.127122 ============ LP4 DIFF to SE enter ============
5007 23:14:38.134205 ============ LP4 DIFF to SE exit ============
5008 23:14:38.134299 [ANA_INIT] <<<<<<<<<<<<<
5009 23:14:38.137041 [Flow] Enable top DCM control >>>>>
5010 23:14:38.140781 [Flow] Enable top DCM control <<<<<
5011 23:14:38.144204 Enable DLL master slave shuffle
5012 23:14:38.150527 ==============================================================
5013 23:14:38.150608 Gating Mode config
5014 23:14:38.157268 ==============================================================
5015 23:14:38.160778 Config description:
5016 23:14:38.167002 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5017 23:14:38.174066 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5018 23:14:38.180317 SELPH_MODE 0: By rank 1: By Phase
5019 23:14:38.187119 ==============================================================
5020 23:14:38.187199 GAT_TRACK_EN = 1
5021 23:14:38.190641 RX_GATING_MODE = 2
5022 23:14:38.193615 RX_GATING_TRACK_MODE = 2
5023 23:14:38.197133 SELPH_MODE = 1
5024 23:14:38.200485 PICG_EARLY_EN = 1
5025 23:14:38.203700 VALID_LAT_VALUE = 1
5026 23:14:38.210218 ==============================================================
5027 23:14:38.213622 Enter into Gating configuration >>>>
5028 23:14:38.216957 Exit from Gating configuration <<<<
5029 23:14:38.220660 Enter into DVFS_PRE_config >>>>>
5030 23:14:38.230573 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5031 23:14:38.233691 Exit from DVFS_PRE_config <<<<<
5032 23:14:38.237154 Enter into PICG configuration >>>>
5033 23:14:38.240255 Exit from PICG configuration <<<<
5034 23:14:38.243628 [RX_INPUT] configuration >>>>>
5035 23:14:38.243708 [RX_INPUT] configuration <<<<<
5036 23:14:38.250183 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5037 23:14:38.256682 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5038 23:14:38.263705 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5039 23:14:38.266710 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5040 23:14:38.273384 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5041 23:14:38.279986 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5042 23:14:38.283039 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5043 23:14:38.286817 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5044 23:14:38.293606 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5045 23:14:38.296601 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5046 23:14:38.300102 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5047 23:14:38.306744 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5048 23:14:38.309971 ===================================
5049 23:14:38.310051 LPDDR4 DRAM CONFIGURATION
5050 23:14:38.313247 ===================================
5051 23:14:38.316503 EX_ROW_EN[0] = 0x0
5052 23:14:38.320505 EX_ROW_EN[1] = 0x0
5053 23:14:38.320585 LP4Y_EN = 0x0
5054 23:14:38.323507 WORK_FSP = 0x0
5055 23:14:38.323587 WL = 0x3
5056 23:14:38.326377 RL = 0x3
5057 23:14:38.326457 BL = 0x2
5058 23:14:38.329622 RPST = 0x0
5059 23:14:38.329702 RD_PRE = 0x0
5060 23:14:38.333296 WR_PRE = 0x1
5061 23:14:38.333377 WR_PST = 0x0
5062 23:14:38.336433 DBI_WR = 0x0
5063 23:14:38.336514 DBI_RD = 0x0
5064 23:14:38.339601 OTF = 0x1
5065 23:14:38.343087 ===================================
5066 23:14:38.346602 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5067 23:14:38.349543 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5068 23:14:38.356114 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5069 23:14:38.359705 ===================================
5070 23:14:38.359786 LPDDR4 DRAM CONFIGURATION
5071 23:14:38.362983 ===================================
5072 23:14:38.365985 EX_ROW_EN[0] = 0x10
5073 23:14:38.366067 EX_ROW_EN[1] = 0x0
5074 23:14:38.369547 LP4Y_EN = 0x0
5075 23:14:38.372864 WORK_FSP = 0x0
5076 23:14:38.372945 WL = 0x3
5077 23:14:38.375949 RL = 0x3
5078 23:14:38.376030 BL = 0x2
5079 23:14:38.379611 RPST = 0x0
5080 23:14:38.379692 RD_PRE = 0x0
5081 23:14:38.382751 WR_PRE = 0x1
5082 23:14:38.382833 WR_PST = 0x0
5083 23:14:38.386369 DBI_WR = 0x0
5084 23:14:38.386450 DBI_RD = 0x0
5085 23:14:38.389372 OTF = 0x1
5086 23:14:38.393003 ===================================
5087 23:14:38.399749 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5088 23:14:38.402879 nWR fixed to 30
5089 23:14:38.402960 [ModeRegInit_LP4] CH0 RK0
5090 23:14:38.405864 [ModeRegInit_LP4] CH0 RK1
5091 23:14:38.409545 [ModeRegInit_LP4] CH1 RK0
5092 23:14:38.409627 [ModeRegInit_LP4] CH1 RK1
5093 23:14:38.412695 match AC timing 9
5094 23:14:38.415852 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5095 23:14:38.419560 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5096 23:14:38.426110 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5097 23:14:38.429145 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5098 23:14:38.435777 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5099 23:14:38.435884 ==
5100 23:14:38.439019 Dram Type= 6, Freq= 0, CH_0, rank 0
5101 23:14:38.442677 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5102 23:14:38.442758 ==
5103 23:14:38.449006 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5104 23:14:38.452332 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5105 23:14:38.456611 [CA 0] Center 37 (6~68) winsize 63
5106 23:14:38.460107 [CA 1] Center 37 (6~68) winsize 63
5107 23:14:38.463453 [CA 2] Center 34 (4~65) winsize 62
5108 23:14:38.466928 [CA 3] Center 33 (3~64) winsize 62
5109 23:14:38.470394 [CA 4] Center 33 (3~64) winsize 62
5110 23:14:38.473539 [CA 5] Center 32 (2~62) winsize 61
5111 23:14:38.473618
5112 23:14:38.476657 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5113 23:14:38.476737
5114 23:14:38.480407 [CATrainingPosCal] consider 1 rank data
5115 23:14:38.483427 u2DelayCellTimex100 = 270/100 ps
5116 23:14:38.486751 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5117 23:14:38.489959 CA1 delay=37 (6~68),Diff = 5 PI (31 cell)
5118 23:14:38.496870 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5119 23:14:38.500391 CA3 delay=33 (3~64),Diff = 1 PI (6 cell)
5120 23:14:38.503249 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5121 23:14:38.507032 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5122 23:14:38.507108
5123 23:14:38.510207 CA PerBit enable=1, Macro0, CA PI delay=32
5124 23:14:38.510277
5125 23:14:38.513245 [CBTSetCACLKResult] CA Dly = 32
5126 23:14:38.513315 CS Dly: 5 (0~36)
5127 23:14:38.516898 ==
5128 23:14:38.516978 Dram Type= 6, Freq= 0, CH_0, rank 1
5129 23:14:38.523098 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5130 23:14:38.523180 ==
5131 23:14:38.526916 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5132 23:14:38.533293 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5133 23:14:38.536719 [CA 0] Center 37 (6~68) winsize 63
5134 23:14:38.540156 [CA 1] Center 37 (6~68) winsize 63
5135 23:14:38.543765 [CA 2] Center 34 (4~65) winsize 62
5136 23:14:38.546884 [CA 3] Center 34 (3~65) winsize 63
5137 23:14:38.549915 [CA 4] Center 33 (3~63) winsize 61
5138 23:14:38.553487 [CA 5] Center 32 (2~62) winsize 61
5139 23:14:38.553568
5140 23:14:38.556616 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5141 23:14:38.556696
5142 23:14:38.560102 [CATrainingPosCal] consider 2 rank data
5143 23:14:38.563629 u2DelayCellTimex100 = 270/100 ps
5144 23:14:38.566691 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5145 23:14:38.569851 CA1 delay=37 (6~68),Diff = 5 PI (31 cell)
5146 23:14:38.576845 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5147 23:14:38.580041 CA3 delay=33 (3~64),Diff = 1 PI (6 cell)
5148 23:14:38.583296 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5149 23:14:38.586720 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5150 23:14:38.586814
5151 23:14:38.589941 CA PerBit enable=1, Macro0, CA PI delay=32
5152 23:14:38.590022
5153 23:14:38.593157 [CBTSetCACLKResult] CA Dly = 32
5154 23:14:38.593261 CS Dly: 5 (0~37)
5155 23:14:38.593326
5156 23:14:38.600251 ----->DramcWriteLeveling(PI) begin...
5157 23:14:38.600343 ==
5158 23:14:38.603468 Dram Type= 6, Freq= 0, CH_0, rank 0
5159 23:14:38.606695 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5160 23:14:38.606777 ==
5161 23:14:38.609860 Write leveling (Byte 0): 29 => 29
5162 23:14:38.613195 Write leveling (Byte 1): 28 => 28
5163 23:14:38.616293 DramcWriteLeveling(PI) end<-----
5164 23:14:38.616406
5165 23:14:38.616468 ==
5166 23:14:38.619993 Dram Type= 6, Freq= 0, CH_0, rank 0
5167 23:14:38.623052 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5168 23:14:38.623133 ==
5169 23:14:38.626213 [Gating] SW mode calibration
5170 23:14:38.632911 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5171 23:14:38.639656 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5172 23:14:38.642731 0 14 0 | B1->B0 | 2929 3434 | 0 1 | (0 0) (1 1)
5173 23:14:38.646112 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5174 23:14:38.652713 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5175 23:14:38.656419 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5176 23:14:38.659462 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5177 23:14:38.666131 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5178 23:14:38.669229 0 14 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
5179 23:14:38.672827 0 14 28 | B1->B0 | 3232 2323 | 1 0 | (1 1) (1 0)
5180 23:14:38.679298 0 15 0 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (0 0)
5181 23:14:38.682804 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5182 23:14:38.685863 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5183 23:14:38.692714 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5184 23:14:38.696016 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5185 23:14:38.699166 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5186 23:14:38.705689 0 15 24 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
5187 23:14:38.709203 0 15 28 | B1->B0 | 2a2a 3a3a | 0 0 | (0 0) (0 0)
5188 23:14:38.712454 1 0 0 | B1->B0 | 3d3d 4646 | 0 0 | (1 1) (0 0)
5189 23:14:38.719257 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5190 23:14:38.722234 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5191 23:14:38.725495 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5192 23:14:38.732226 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5193 23:14:38.735251 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5194 23:14:38.738877 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5195 23:14:38.742546 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5196 23:14:38.748874 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5197 23:14:38.752281 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5198 23:14:38.755495 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5199 23:14:38.762040 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5200 23:14:38.765346 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5201 23:14:38.768917 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5202 23:14:38.775138 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5203 23:14:38.778255 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5204 23:14:38.781791 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5205 23:14:38.788500 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5206 23:14:38.791970 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5207 23:14:38.794989 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5208 23:14:38.801674 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5209 23:14:38.805311 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5210 23:14:38.808328 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5211 23:14:38.814842 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5212 23:14:38.818471 Total UI for P1: 0, mck2ui 16
5213 23:14:38.821793 best dqsien dly found for B0: ( 1, 2, 26)
5214 23:14:38.825086 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5215 23:14:38.828651 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5216 23:14:38.831694 Total UI for P1: 0, mck2ui 16
5217 23:14:38.835169 best dqsien dly found for B1: ( 1, 2, 30)
5218 23:14:38.838209 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5219 23:14:38.841473 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5220 23:14:38.841554
5221 23:14:38.848186 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5222 23:14:38.851782 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5223 23:14:38.854666 [Gating] SW calibration Done
5224 23:14:38.854747 ==
5225 23:14:38.858128 Dram Type= 6, Freq= 0, CH_0, rank 0
5226 23:14:38.861658 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5227 23:14:38.861769 ==
5228 23:14:38.861848 RX Vref Scan: 0
5229 23:14:38.861908
5230 23:14:38.865054 RX Vref 0 -> 0, step: 1
5231 23:14:38.865137
5232 23:14:38.867936 RX Delay -80 -> 252, step: 8
5233 23:14:38.871711 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5234 23:14:38.874820 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5235 23:14:38.878473 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5236 23:14:38.884501 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5237 23:14:38.888166 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5238 23:14:38.891169 iDelay=208, Bit 5, Center 95 (8 ~ 183) 176
5239 23:14:38.894680 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5240 23:14:38.898323 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5241 23:14:38.901208 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5242 23:14:38.907906 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5243 23:14:38.911119 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5244 23:14:38.914856 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5245 23:14:38.917852 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5246 23:14:38.921490 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5247 23:14:38.924590 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5248 23:14:38.930975 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5249 23:14:38.931056 ==
5250 23:14:38.934709 Dram Type= 6, Freq= 0, CH_0, rank 0
5251 23:14:38.937642 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5252 23:14:38.937724 ==
5253 23:14:38.937787 DQS Delay:
5254 23:14:38.941449 DQS0 = 0, DQS1 = 0
5255 23:14:38.941530 DQM Delay:
5256 23:14:38.944494 DQM0 = 105, DQM1 = 94
5257 23:14:38.944574 DQ Delay:
5258 23:14:38.947545 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5259 23:14:38.950916 DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =115
5260 23:14:38.954241 DQ8 =87, DQ9 =87, DQ10 =91, DQ11 =91
5261 23:14:38.957480 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =99
5262 23:14:38.957562
5263 23:14:38.957625
5264 23:14:38.957684 ==
5265 23:14:38.960956 Dram Type= 6, Freq= 0, CH_0, rank 0
5266 23:14:38.967684 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5267 23:14:38.967764 ==
5268 23:14:38.967827
5269 23:14:38.967884
5270 23:14:38.967939 TX Vref Scan disable
5271 23:14:38.970823 == TX Byte 0 ==
5272 23:14:38.974642 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5273 23:14:38.980954 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5274 23:14:38.981035 == TX Byte 1 ==
5275 23:14:38.984001 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5276 23:14:38.990942 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5277 23:14:38.991044 ==
5278 23:14:38.993961 Dram Type= 6, Freq= 0, CH_0, rank 0
5279 23:14:38.997515 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5280 23:14:38.997624 ==
5281 23:14:38.997688
5282 23:14:38.997747
5283 23:14:39.000492 TX Vref Scan disable
5284 23:14:39.000571 == TX Byte 0 ==
5285 23:14:39.007663 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5286 23:14:39.010644 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5287 23:14:39.010723 == TX Byte 1 ==
5288 23:14:39.017358 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5289 23:14:39.020508 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5290 23:14:39.020588
5291 23:14:39.020649 [DATLAT]
5292 23:14:39.023958 Freq=933, CH0 RK0
5293 23:14:39.024038
5294 23:14:39.024100 DATLAT Default: 0xd
5295 23:14:39.027130 0, 0xFFFF, sum = 0
5296 23:14:39.027211 1, 0xFFFF, sum = 0
5297 23:14:39.030798 2, 0xFFFF, sum = 0
5298 23:14:39.033805 3, 0xFFFF, sum = 0
5299 23:14:39.033886 4, 0xFFFF, sum = 0
5300 23:14:39.037327 5, 0xFFFF, sum = 0
5301 23:14:39.037408 6, 0xFFFF, sum = 0
5302 23:14:39.040835 7, 0xFFFF, sum = 0
5303 23:14:39.040917 8, 0xFFFF, sum = 0
5304 23:14:39.043987 9, 0xFFFF, sum = 0
5305 23:14:39.044068 10, 0x0, sum = 1
5306 23:14:39.047538 11, 0x0, sum = 2
5307 23:14:39.047620 12, 0x0, sum = 3
5308 23:14:39.047684 13, 0x0, sum = 4
5309 23:14:39.050580 best_step = 11
5310 23:14:39.050660
5311 23:14:39.050724 ==
5312 23:14:39.053702 Dram Type= 6, Freq= 0, CH_0, rank 0
5313 23:14:39.057325 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5314 23:14:39.057407 ==
5315 23:14:39.060304 RX Vref Scan: 1
5316 23:14:39.060385
5317 23:14:39.060448 RX Vref 0 -> 0, step: 1
5318 23:14:39.064063
5319 23:14:39.064143 RX Delay -45 -> 252, step: 4
5320 23:14:39.064207
5321 23:14:39.067091 Set Vref, RX VrefLevel [Byte0]: 55
5322 23:14:39.070497 [Byte1]: 49
5323 23:14:39.074678
5324 23:14:39.074759 Final RX Vref Byte 0 = 55 to rank0
5325 23:14:39.078011 Final RX Vref Byte 1 = 49 to rank0
5326 23:14:39.081708 Final RX Vref Byte 0 = 55 to rank1
5327 23:14:39.084986 Final RX Vref Byte 1 = 49 to rank1==
5328 23:14:39.088183 Dram Type= 6, Freq= 0, CH_0, rank 0
5329 23:14:39.094857 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5330 23:14:39.094938 ==
5331 23:14:39.095001 DQS Delay:
5332 23:14:39.095060 DQS0 = 0, DQS1 = 0
5333 23:14:39.098152 DQM Delay:
5334 23:14:39.098233 DQM0 = 104, DQM1 = 96
5335 23:14:39.101581 DQ Delay:
5336 23:14:39.104974 DQ0 =106, DQ1 =104, DQ2 =100, DQ3 =102
5337 23:14:39.107912 DQ4 =106, DQ5 =96, DQ6 =112, DQ7 =110
5338 23:14:39.111631 DQ8 =84, DQ9 =88, DQ10 =96, DQ11 =90
5339 23:14:39.115090 DQ12 =100, DQ13 =100, DQ14 =106, DQ15 =104
5340 23:14:39.115170
5341 23:14:39.115233
5342 23:14:39.121348 [DQSOSCAuto] RK0, (LSB)MR18= 0x3129, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 406 ps
5343 23:14:39.124959 CH0 RK0: MR19=505, MR18=3129
5344 23:14:39.131589 CH0_RK0: MR19=0x505, MR18=0x3129, DQSOSC=406, MR23=63, INC=65, DEC=43
5345 23:14:39.131670
5346 23:14:39.134673 ----->DramcWriteLeveling(PI) begin...
5347 23:14:39.134755 ==
5348 23:14:39.138277 Dram Type= 6, Freq= 0, CH_0, rank 1
5349 23:14:39.141295 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5350 23:14:39.141367 ==
5351 23:14:39.144688 Write leveling (Byte 0): 32 => 32
5352 23:14:39.148012 Write leveling (Byte 1): 28 => 28
5353 23:14:39.151035 DramcWriteLeveling(PI) end<-----
5354 23:14:39.151116
5355 23:14:39.151178 ==
5356 23:14:39.154794 Dram Type= 6, Freq= 0, CH_0, rank 1
5357 23:14:39.157808 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5358 23:14:39.161468 ==
5359 23:14:39.161552 [Gating] SW mode calibration
5360 23:14:39.171319 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5361 23:14:39.174909 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5362 23:14:39.177936 0 14 0 | B1->B0 | 3333 3131 | 0 0 | (0 0) (0 0)
5363 23:14:39.184518 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5364 23:14:39.188163 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5365 23:14:39.191146 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5366 23:14:39.198031 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5367 23:14:39.201727 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5368 23:14:39.204591 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5369 23:14:39.210931 0 14 28 | B1->B0 | 2626 2b2b | 0 1 | (0 1) (1 0)
5370 23:14:39.214430 0 15 0 | B1->B0 | 2323 2727 | 1 0 | (1 0) (1 0)
5371 23:14:39.217739 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5372 23:14:39.224130 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5373 23:14:39.227437 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5374 23:14:39.231152 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5375 23:14:39.237499 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5376 23:14:39.241036 0 15 24 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
5377 23:14:39.244484 0 15 28 | B1->B0 | 3d3d 3737 | 0 0 | (1 1) (0 0)
5378 23:14:39.251178 1 0 0 | B1->B0 | 4646 4241 | 0 1 | (0 0) (0 0)
5379 23:14:39.254204 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5380 23:14:39.258053 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5381 23:14:39.264768 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5382 23:14:39.267852 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5383 23:14:39.270836 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5384 23:14:39.274482 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5385 23:14:39.281320 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5386 23:14:39.284189 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5387 23:14:39.287847 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5388 23:14:39.294109 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5389 23:14:39.297760 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5390 23:14:39.300824 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5391 23:14:39.307428 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5392 23:14:39.311024 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5393 23:14:39.314033 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5394 23:14:39.321141 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5395 23:14:39.324107 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5396 23:14:39.327768 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5397 23:14:39.334201 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5398 23:14:39.337710 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5399 23:14:39.340842 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5400 23:14:39.347368 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5401 23:14:39.350401 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5402 23:14:39.353934 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5403 23:14:39.357302 Total UI for P1: 0, mck2ui 16
5404 23:14:39.360795 best dqsien dly found for B0: ( 1, 2, 28)
5405 23:14:39.363761 Total UI for P1: 0, mck2ui 16
5406 23:14:39.367619 best dqsien dly found for B1: ( 1, 2, 28)
5407 23:14:39.370561 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5408 23:14:39.374113 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5409 23:14:39.374196
5410 23:14:39.380884 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5411 23:14:39.383965 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5412 23:14:39.384065 [Gating] SW calibration Done
5413 23:14:39.387390 ==
5414 23:14:39.390419 Dram Type= 6, Freq= 0, CH_0, rank 1
5415 23:14:39.393824 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5416 23:14:39.393907 ==
5417 23:14:39.393972 RX Vref Scan: 0
5418 23:14:39.394031
5419 23:14:39.396929 RX Vref 0 -> 0, step: 1
5420 23:14:39.397026
5421 23:14:39.400465 RX Delay -80 -> 252, step: 8
5422 23:14:39.403647 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5423 23:14:39.407296 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5424 23:14:39.410515 iDelay=208, Bit 2, Center 103 (8 ~ 199) 192
5425 23:14:39.417309 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5426 23:14:39.420582 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5427 23:14:39.423490 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5428 23:14:39.427282 iDelay=208, Bit 6, Center 111 (24 ~ 199) 176
5429 23:14:39.430424 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5430 23:14:39.434013 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5431 23:14:39.440295 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5432 23:14:39.443624 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5433 23:14:39.447378 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5434 23:14:39.450873 iDelay=208, Bit 12, Center 95 (8 ~ 183) 176
5435 23:14:39.453648 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5436 23:14:39.457209 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5437 23:14:39.463883 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5438 23:14:39.463968 ==
5439 23:14:39.467093 Dram Type= 6, Freq= 0, CH_0, rank 1
5440 23:14:39.470536 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5441 23:14:39.470618 ==
5442 23:14:39.470683 DQS Delay:
5443 23:14:39.474111 DQS0 = 0, DQS1 = 0
5444 23:14:39.474193 DQM Delay:
5445 23:14:39.476890 DQM0 = 105, DQM1 = 93
5446 23:14:39.476971 DQ Delay:
5447 23:14:39.480520 DQ0 =103, DQ1 =107, DQ2 =103, DQ3 =99
5448 23:14:39.483579 DQ4 =107, DQ5 =95, DQ6 =111, DQ7 =115
5449 23:14:39.486972 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =87
5450 23:14:39.490582 DQ12 =95, DQ13 =99, DQ14 =103, DQ15 =99
5451 23:14:39.490663
5452 23:14:39.490726
5453 23:14:39.490785 ==
5454 23:14:39.493516 Dram Type= 6, Freq= 0, CH_0, rank 1
5455 23:14:39.500616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5456 23:14:39.500698 ==
5457 23:14:39.500762
5458 23:14:39.500821
5459 23:14:39.500877 TX Vref Scan disable
5460 23:14:39.503664 == TX Byte 0 ==
5461 23:14:39.507254 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5462 23:14:39.513479 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5463 23:14:39.513604 == TX Byte 1 ==
5464 23:14:39.517220 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5465 23:14:39.523284 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5466 23:14:39.523375 ==
5467 23:14:39.526729 Dram Type= 6, Freq= 0, CH_0, rank 1
5468 23:14:39.530190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5469 23:14:39.530279 ==
5470 23:14:39.530344
5471 23:14:39.530403
5472 23:14:39.533258 TX Vref Scan disable
5473 23:14:39.533341 == TX Byte 0 ==
5474 23:14:39.540040 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5475 23:14:39.543746 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5476 23:14:39.543870 == TX Byte 1 ==
5477 23:14:39.549911 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5478 23:14:39.553346 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5479 23:14:39.553430
5480 23:14:39.553494 [DATLAT]
5481 23:14:39.556533 Freq=933, CH0 RK1
5482 23:14:39.556636
5483 23:14:39.556714 DATLAT Default: 0xb
5484 23:14:39.560045 0, 0xFFFF, sum = 0
5485 23:14:39.560128 1, 0xFFFF, sum = 0
5486 23:14:39.563632 2, 0xFFFF, sum = 0
5487 23:14:39.563715 3, 0xFFFF, sum = 0
5488 23:14:39.566663 4, 0xFFFF, sum = 0
5489 23:14:39.566746 5, 0xFFFF, sum = 0
5490 23:14:39.570173 6, 0xFFFF, sum = 0
5491 23:14:39.573784 7, 0xFFFF, sum = 0
5492 23:14:39.573869 8, 0xFFFF, sum = 0
5493 23:14:39.576827 9, 0xFFFF, sum = 0
5494 23:14:39.576910 10, 0x0, sum = 1
5495 23:14:39.576977 11, 0x0, sum = 2
5496 23:14:39.580250 12, 0x0, sum = 3
5497 23:14:39.580360 13, 0x0, sum = 4
5498 23:14:39.583787 best_step = 11
5499 23:14:39.583868
5500 23:14:39.583932 ==
5501 23:14:39.586709 Dram Type= 6, Freq= 0, CH_0, rank 1
5502 23:14:39.589874 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5503 23:14:39.589957 ==
5504 23:14:39.593593 RX Vref Scan: 0
5505 23:14:39.593673
5506 23:14:39.593737 RX Vref 0 -> 0, step: 1
5507 23:14:39.593797
5508 23:14:39.596632 RX Delay -53 -> 252, step: 4
5509 23:14:39.604019 iDelay=199, Bit 0, Center 104 (15 ~ 194) 180
5510 23:14:39.607545 iDelay=199, Bit 1, Center 106 (23 ~ 190) 168
5511 23:14:39.610427 iDelay=199, Bit 2, Center 102 (15 ~ 190) 176
5512 23:14:39.614018 iDelay=199, Bit 3, Center 102 (15 ~ 190) 176
5513 23:14:39.617855 iDelay=199, Bit 4, Center 106 (19 ~ 194) 176
5514 23:14:39.624158 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5515 23:14:39.627307 iDelay=199, Bit 6, Center 110 (27 ~ 194) 168
5516 23:14:39.630543 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5517 23:14:39.634293 iDelay=199, Bit 8, Center 86 (3 ~ 170) 168
5518 23:14:39.637692 iDelay=199, Bit 9, Center 84 (3 ~ 166) 164
5519 23:14:39.640570 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5520 23:14:39.647162 iDelay=199, Bit 11, Center 88 (7 ~ 170) 164
5521 23:14:39.650909 iDelay=199, Bit 12, Center 98 (15 ~ 182) 168
5522 23:14:39.653948 iDelay=199, Bit 13, Center 98 (15 ~ 182) 168
5523 23:14:39.657161 iDelay=199, Bit 14, Center 104 (23 ~ 186) 164
5524 23:14:39.660866 iDelay=199, Bit 15, Center 102 (19 ~ 186) 168
5525 23:14:39.663863 ==
5526 23:14:39.667226 Dram Type= 6, Freq= 0, CH_0, rank 1
5527 23:14:39.670516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5528 23:14:39.670633 ==
5529 23:14:39.670713 DQS Delay:
5530 23:14:39.673725 DQS0 = 0, DQS1 = 0
5531 23:14:39.673806 DQM Delay:
5532 23:14:39.677147 DQM0 = 105, DQM1 = 94
5533 23:14:39.677229 DQ Delay:
5534 23:14:39.680627 DQ0 =104, DQ1 =106, DQ2 =102, DQ3 =102
5535 23:14:39.683985 DQ4 =106, DQ5 =98, DQ6 =110, DQ7 =112
5536 23:14:39.687044 DQ8 =86, DQ9 =84, DQ10 =94, DQ11 =88
5537 23:14:39.690656 DQ12 =98, DQ13 =98, DQ14 =104, DQ15 =102
5538 23:14:39.690763
5539 23:14:39.690828
5540 23:14:39.700542 [DQSOSCAuto] RK1, (LSB)MR18= 0x2801, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 409 ps
5541 23:14:39.700633 CH0 RK1: MR19=505, MR18=2801
5542 23:14:39.707261 CH0_RK1: MR19=0x505, MR18=0x2801, DQSOSC=409, MR23=63, INC=64, DEC=43
5543 23:14:39.710184 [RxdqsGatingPostProcess] freq 933
5544 23:14:39.716847 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5545 23:14:39.720475 best DQS0 dly(2T, 0.5T) = (0, 10)
5546 23:14:39.723640 best DQS1 dly(2T, 0.5T) = (0, 10)
5547 23:14:39.726812 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5548 23:14:39.730451 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5549 23:14:39.733685 best DQS0 dly(2T, 0.5T) = (0, 10)
5550 23:14:39.733771 best DQS1 dly(2T, 0.5T) = (0, 10)
5551 23:14:39.736964 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5552 23:14:39.740135 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5553 23:14:39.743942 Pre-setting of DQS Precalculation
5554 23:14:39.750224 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5555 23:14:39.750307 ==
5556 23:14:39.753194 Dram Type= 6, Freq= 0, CH_1, rank 0
5557 23:14:39.756855 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5558 23:14:39.756977 ==
5559 23:14:39.763574 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5560 23:14:39.769783 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5561 23:14:39.773356 [CA 0] Center 36 (6~67) winsize 62
5562 23:14:39.776867 [CA 1] Center 36 (6~67) winsize 62
5563 23:14:39.780190 [CA 2] Center 34 (4~65) winsize 62
5564 23:14:39.783469 [CA 3] Center 34 (4~65) winsize 62
5565 23:14:39.786849 [CA 4] Center 34 (4~65) winsize 62
5566 23:14:39.786930 [CA 5] Center 33 (3~64) winsize 62
5567 23:14:39.790309
5568 23:14:39.793481 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5569 23:14:39.793563
5570 23:14:39.796511 [CATrainingPosCal] consider 1 rank data
5571 23:14:39.799978 u2DelayCellTimex100 = 270/100 ps
5572 23:14:39.803191 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5573 23:14:39.806672 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5574 23:14:39.809784 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5575 23:14:39.812830 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5576 23:14:39.816228 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5577 23:14:39.819768 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5578 23:14:39.819849
5579 23:14:39.826482 CA PerBit enable=1, Macro0, CA PI delay=33
5580 23:14:39.826568
5581 23:14:39.826634 [CBTSetCACLKResult] CA Dly = 33
5582 23:14:39.829603 CS Dly: 7 (0~38)
5583 23:14:39.829670 ==
5584 23:14:39.833215 Dram Type= 6, Freq= 0, CH_1, rank 1
5585 23:14:39.836277 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5586 23:14:39.836401 ==
5587 23:14:39.842869 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5588 23:14:39.849559 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5589 23:14:39.852578 [CA 0] Center 36 (6~67) winsize 62
5590 23:14:39.856271 [CA 1] Center 37 (6~68) winsize 63
5591 23:14:39.859233 [CA 2] Center 35 (5~65) winsize 61
5592 23:14:39.862689 [CA 3] Center 34 (4~65) winsize 62
5593 23:14:39.866016 [CA 4] Center 34 (4~65) winsize 62
5594 23:14:39.869405 [CA 5] Center 33 (3~64) winsize 62
5595 23:14:39.869487
5596 23:14:39.872498 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5597 23:14:39.872579
5598 23:14:39.876138 [CATrainingPosCal] consider 2 rank data
5599 23:14:39.879224 u2DelayCellTimex100 = 270/100 ps
5600 23:14:39.882859 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5601 23:14:39.886189 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5602 23:14:39.889368 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5603 23:14:39.892861 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5604 23:14:39.895874 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5605 23:14:39.899482 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5606 23:14:39.902275
5607 23:14:39.905583 CA PerBit enable=1, Macro0, CA PI delay=33
5608 23:14:39.905684
5609 23:14:39.909311 [CBTSetCACLKResult] CA Dly = 33
5610 23:14:39.909392 CS Dly: 8 (0~40)
5611 23:14:39.909456
5612 23:14:39.912230 ----->DramcWriteLeveling(PI) begin...
5613 23:14:39.912370 ==
5614 23:14:39.915926 Dram Type= 6, Freq= 0, CH_1, rank 0
5615 23:14:39.919164 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5616 23:14:39.922101 ==
5617 23:14:39.922183 Write leveling (Byte 0): 26 => 26
5618 23:14:39.925716 Write leveling (Byte 1): 27 => 27
5619 23:14:39.929114 DramcWriteLeveling(PI) end<-----
5620 23:14:39.929196
5621 23:14:39.929258 ==
5622 23:14:39.932202 Dram Type= 6, Freq= 0, CH_1, rank 0
5623 23:14:39.939120 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5624 23:14:39.939206 ==
5625 23:14:39.941983 [Gating] SW mode calibration
5626 23:14:39.949222 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5627 23:14:39.952240 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5628 23:14:39.958509 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5629 23:14:39.962210 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5630 23:14:39.965333 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5631 23:14:39.972077 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5632 23:14:39.975309 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5633 23:14:39.978797 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5634 23:14:39.985599 0 14 24 | B1->B0 | 3131 2d2d | 1 1 | (1 1) (1 0)
5635 23:14:39.988557 0 14 28 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
5636 23:14:39.992269 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5637 23:14:39.995485 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5638 23:14:40.001719 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5639 23:14:40.005272 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5640 23:14:40.008551 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5641 23:14:40.015118 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5642 23:14:40.018687 0 15 24 | B1->B0 | 2424 3636 | 0 0 | (0 0) (0 0)
5643 23:14:40.022312 0 15 28 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
5644 23:14:40.028343 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5645 23:14:40.032118 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5646 23:14:40.035286 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5647 23:14:40.042125 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5648 23:14:40.044983 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5649 23:14:40.048591 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5650 23:14:40.055272 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5651 23:14:40.058823 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5652 23:14:40.062014 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5653 23:14:40.068625 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5654 23:14:40.071695 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5655 23:14:40.075462 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5656 23:14:40.082136 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5657 23:14:40.085396 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5658 23:14:40.088303 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5659 23:14:40.095187 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5660 23:14:40.098801 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5661 23:14:40.101912 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5662 23:14:40.108321 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5663 23:14:40.111864 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5664 23:14:40.115292 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5665 23:14:40.121715 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5666 23:14:40.124890 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5667 23:14:40.127919 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5668 23:14:40.131406 Total UI for P1: 0, mck2ui 16
5669 23:14:40.134823 best dqsien dly found for B0: ( 1, 2, 24)
5670 23:14:40.138251 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5671 23:14:40.141122 Total UI for P1: 0, mck2ui 16
5672 23:14:40.144849 best dqsien dly found for B1: ( 1, 2, 26)
5673 23:14:40.147944 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5674 23:14:40.154732 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5675 23:14:40.154820
5676 23:14:40.158052 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5677 23:14:40.161519 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5678 23:14:40.164681 [Gating] SW calibration Done
5679 23:14:40.164765 ==
5680 23:14:40.167717 Dram Type= 6, Freq= 0, CH_1, rank 0
5681 23:14:40.171411 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5682 23:14:40.171495 ==
5683 23:14:40.174423 RX Vref Scan: 0
5684 23:14:40.174506
5685 23:14:40.174587 RX Vref 0 -> 0, step: 1
5686 23:14:40.174661
5687 23:14:40.178057 RX Delay -80 -> 252, step: 8
5688 23:14:40.181241 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5689 23:14:40.184747 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5690 23:14:40.191333 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5691 23:14:40.194464 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5692 23:14:40.197926 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5693 23:14:40.200989 iDelay=208, Bit 5, Center 119 (32 ~ 207) 176
5694 23:14:40.204519 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5695 23:14:40.208074 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5696 23:14:40.214801 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5697 23:14:40.218085 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5698 23:14:40.221110 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5699 23:14:40.224808 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5700 23:14:40.227979 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5701 23:14:40.231458 iDelay=208, Bit 13, Center 107 (16 ~ 199) 184
5702 23:14:40.237625 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5703 23:14:40.241094 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5704 23:14:40.241275 ==
5705 23:14:40.244556 Dram Type= 6, Freq= 0, CH_1, rank 0
5706 23:14:40.247368 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5707 23:14:40.247504 ==
5708 23:14:40.250997 DQS Delay:
5709 23:14:40.251155 DQS0 = 0, DQS1 = 0
5710 23:14:40.251280 DQM Delay:
5711 23:14:40.254322 DQM0 = 103, DQM1 = 98
5712 23:14:40.254441 DQ Delay:
5713 23:14:40.257764 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
5714 23:14:40.260744 DQ4 =99, DQ5 =119, DQ6 =111, DQ7 =103
5715 23:14:40.263962 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =91
5716 23:14:40.267736 DQ12 =107, DQ13 =107, DQ14 =103, DQ15 =107
5717 23:14:40.270841
5718 23:14:40.270922
5719 23:14:40.270986 ==
5720 23:14:40.274236 Dram Type= 6, Freq= 0, CH_1, rank 0
5721 23:14:40.277540 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5722 23:14:40.277623 ==
5723 23:14:40.277688
5724 23:14:40.277747
5725 23:14:40.280894 TX Vref Scan disable
5726 23:14:40.280977 == TX Byte 0 ==
5727 23:14:40.287434 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5728 23:14:40.291023 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5729 23:14:40.291108 == TX Byte 1 ==
5730 23:14:40.297116 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5731 23:14:40.300866 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5732 23:14:40.300948 ==
5733 23:14:40.303900 Dram Type= 6, Freq= 0, CH_1, rank 0
5734 23:14:40.307391 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5735 23:14:40.307490 ==
5736 23:14:40.307586
5737 23:14:40.307669
5738 23:14:40.310418 TX Vref Scan disable
5739 23:14:40.314044 == TX Byte 0 ==
5740 23:14:40.317201 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5741 23:14:40.320778 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5742 23:14:40.323928 == TX Byte 1 ==
5743 23:14:40.327575 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5744 23:14:40.330619 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5745 23:14:40.330702
5746 23:14:40.334440 [DATLAT]
5747 23:14:40.334521 Freq=933, CH1 RK0
5748 23:14:40.334625
5749 23:14:40.337225 DATLAT Default: 0xd
5750 23:14:40.337307 0, 0xFFFF, sum = 0
5751 23:14:40.340840 1, 0xFFFF, sum = 0
5752 23:14:40.340923 2, 0xFFFF, sum = 0
5753 23:14:40.343848 3, 0xFFFF, sum = 0
5754 23:14:40.343931 4, 0xFFFF, sum = 0
5755 23:14:40.347445 5, 0xFFFF, sum = 0
5756 23:14:40.347564 6, 0xFFFF, sum = 0
5757 23:14:40.350304 7, 0xFFFF, sum = 0
5758 23:14:40.350384 8, 0xFFFF, sum = 0
5759 23:14:40.354100 9, 0xFFFF, sum = 0
5760 23:14:40.354181 10, 0x0, sum = 1
5761 23:14:40.357216 11, 0x0, sum = 2
5762 23:14:40.357314 12, 0x0, sum = 3
5763 23:14:40.360619 13, 0x0, sum = 4
5764 23:14:40.360700 best_step = 11
5765 23:14:40.360762
5766 23:14:40.360820 ==
5767 23:14:40.363840 Dram Type= 6, Freq= 0, CH_1, rank 0
5768 23:14:40.370494 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5769 23:14:40.370579 ==
5770 23:14:40.370644 RX Vref Scan: 1
5771 23:14:40.370704
5772 23:14:40.374054 RX Vref 0 -> 0, step: 1
5773 23:14:40.374136
5774 23:14:40.377505 RX Delay -45 -> 252, step: 4
5775 23:14:40.377633
5776 23:14:40.380207 Set Vref, RX VrefLevel [Byte0]: 54
5777 23:14:40.383872 [Byte1]: 55
5778 23:14:40.383991
5779 23:14:40.387388 Final RX Vref Byte 0 = 54 to rank0
5780 23:14:40.390358 Final RX Vref Byte 1 = 55 to rank0
5781 23:14:40.394015 Final RX Vref Byte 0 = 54 to rank1
5782 23:14:40.397115 Final RX Vref Byte 1 = 55 to rank1==
5783 23:14:40.400630 Dram Type= 6, Freq= 0, CH_1, rank 0
5784 23:14:40.403766 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5785 23:14:40.403889 ==
5786 23:14:40.407051 DQS Delay:
5787 23:14:40.407171 DQS0 = 0, DQS1 = 0
5788 23:14:40.407278 DQM Delay:
5789 23:14:40.410813 DQM0 = 103, DQM1 = 100
5790 23:14:40.410931 DQ Delay:
5791 23:14:40.413740 DQ0 =106, DQ1 =98, DQ2 =94, DQ3 =102
5792 23:14:40.417163 DQ4 =102, DQ5 =112, DQ6 =112, DQ7 =102
5793 23:14:40.420219 DQ8 =88, DQ9 =90, DQ10 =102, DQ11 =94
5794 23:14:40.423967 DQ12 =104, DQ13 =108, DQ14 =108, DQ15 =108
5795 23:14:40.427001
5796 23:14:40.427120
5797 23:14:40.433711 [DQSOSCAuto] RK0, (LSB)MR18= 0x152c, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 415 ps
5798 23:14:40.436866 CH1 RK0: MR19=505, MR18=152C
5799 23:14:40.443950 CH1_RK0: MR19=0x505, MR18=0x152C, DQSOSC=408, MR23=63, INC=65, DEC=43
5800 23:14:40.444062
5801 23:14:40.446925 ----->DramcWriteLeveling(PI) begin...
5802 23:14:40.447007 ==
5803 23:14:40.450020 Dram Type= 6, Freq= 0, CH_1, rank 1
5804 23:14:40.453424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5805 23:14:40.453505 ==
5806 23:14:40.457012 Write leveling (Byte 0): 28 => 28
5807 23:14:40.460067 Write leveling (Byte 1): 29 => 29
5808 23:14:40.463124 DramcWriteLeveling(PI) end<-----
5809 23:14:40.463203
5810 23:14:40.463266 ==
5811 23:14:40.466935 Dram Type= 6, Freq= 0, CH_1, rank 1
5812 23:14:40.470118 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5813 23:14:40.470200 ==
5814 23:14:40.473151 [Gating] SW mode calibration
5815 23:14:40.480148 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5816 23:14:40.486779 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5817 23:14:40.489772 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5818 23:14:40.493115 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5819 23:14:40.499641 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5820 23:14:40.503255 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5821 23:14:40.506720 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5822 23:14:40.513064 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5823 23:14:40.516722 0 14 24 | B1->B0 | 2a2a 3434 | 0 0 | (0 1) (0 1)
5824 23:14:40.519781 0 14 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5825 23:14:40.526479 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5826 23:14:40.529993 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5827 23:14:40.533060 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5828 23:14:40.539921 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5829 23:14:40.543129 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5830 23:14:40.546736 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5831 23:14:40.553197 0 15 24 | B1->B0 | 3939 3030 | 0 0 | (0 0) (0 0)
5832 23:14:40.556141 0 15 28 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
5833 23:14:40.559689 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5834 23:14:40.566227 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5835 23:14:40.569884 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5836 23:14:40.572913 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5837 23:14:40.579545 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5838 23:14:40.583294 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5839 23:14:40.586448 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5840 23:14:40.593045 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5841 23:14:40.596550 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5842 23:14:40.599385 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5843 23:14:40.603197 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5844 23:14:40.609639 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5845 23:14:40.613027 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5846 23:14:40.615946 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5847 23:14:40.622716 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5848 23:14:40.626248 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5849 23:14:40.629640 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5850 23:14:40.636002 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5851 23:14:40.639402 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5852 23:14:40.642679 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5853 23:14:40.649343 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5854 23:14:40.653062 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5855 23:14:40.656259 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5856 23:14:40.662960 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5857 23:14:40.663044 Total UI for P1: 0, mck2ui 16
5858 23:14:40.669308 best dqsien dly found for B1: ( 1, 2, 24)
5859 23:14:40.673006 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5860 23:14:40.676086 Total UI for P1: 0, mck2ui 16
5861 23:14:40.679757 best dqsien dly found for B0: ( 1, 2, 26)
5862 23:14:40.682839 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5863 23:14:40.686542 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5864 23:14:40.686624
5865 23:14:40.689680 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5866 23:14:40.692842 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5867 23:14:40.696439 [Gating] SW calibration Done
5868 23:14:40.696522 ==
5869 23:14:40.699688 Dram Type= 6, Freq= 0, CH_1, rank 1
5870 23:14:40.703188 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5871 23:14:40.703271 ==
5872 23:14:40.706172 RX Vref Scan: 0
5873 23:14:40.706254
5874 23:14:40.709277 RX Vref 0 -> 0, step: 1
5875 23:14:40.709359
5876 23:14:40.709423 RX Delay -80 -> 252, step: 8
5877 23:14:40.716310 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5878 23:14:40.719292 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5879 23:14:40.722741 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5880 23:14:40.726338 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5881 23:14:40.729500 iDelay=208, Bit 4, Center 95 (8 ~ 183) 176
5882 23:14:40.732686 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5883 23:14:40.739785 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5884 23:14:40.743043 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5885 23:14:40.746148 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5886 23:14:40.749800 iDelay=208, Bit 9, Center 91 (0 ~ 183) 184
5887 23:14:40.752764 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5888 23:14:40.756481 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5889 23:14:40.762792 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5890 23:14:40.766440 iDelay=208, Bit 13, Center 107 (16 ~ 199) 184
5891 23:14:40.769563 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5892 23:14:40.772672 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5893 23:14:40.772760 ==
5894 23:14:40.776595 Dram Type= 6, Freq= 0, CH_1, rank 1
5895 23:14:40.779550 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5896 23:14:40.783110 ==
5897 23:14:40.783192 DQS Delay:
5898 23:14:40.783256 DQS0 = 0, DQS1 = 0
5899 23:14:40.786154 DQM Delay:
5900 23:14:40.786235 DQM0 = 102, DQM1 = 98
5901 23:14:40.789357 DQ Delay:
5902 23:14:40.792815 DQ0 =107, DQ1 =99, DQ2 =91, DQ3 =99
5903 23:14:40.796584 DQ4 =95, DQ5 =115, DQ6 =111, DQ7 =99
5904 23:14:40.799458 DQ8 =87, DQ9 =91, DQ10 =99, DQ11 =91
5905 23:14:40.802620 DQ12 =107, DQ13 =107, DQ14 =99, DQ15 =107
5906 23:14:40.802702
5907 23:14:40.802766
5908 23:14:40.802824 ==
5909 23:14:40.806320 Dram Type= 6, Freq= 0, CH_1, rank 1
5910 23:14:40.809438 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5911 23:14:40.809521 ==
5912 23:14:40.809585
5913 23:14:40.809643
5914 23:14:40.813137 TX Vref Scan disable
5915 23:14:40.813220 == TX Byte 0 ==
5916 23:14:40.819684 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5917 23:14:40.822758 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5918 23:14:40.822842 == TX Byte 1 ==
5919 23:14:40.829532 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5920 23:14:40.832971 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5921 23:14:40.833053 ==
5922 23:14:40.836297 Dram Type= 6, Freq= 0, CH_1, rank 1
5923 23:14:40.839153 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5924 23:14:40.839237 ==
5925 23:14:40.839301
5926 23:14:40.842536
5927 23:14:40.842643 TX Vref Scan disable
5928 23:14:40.846175 == TX Byte 0 ==
5929 23:14:40.849519 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5930 23:14:40.853107 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5931 23:14:40.855958 == TX Byte 1 ==
5932 23:14:40.859643 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5933 23:14:40.862640 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5934 23:14:40.862722
5935 23:14:40.866384 [DATLAT]
5936 23:14:40.866465 Freq=933, CH1 RK1
5937 23:14:40.866530
5938 23:14:40.869415 DATLAT Default: 0xb
5939 23:14:40.869497 0, 0xFFFF, sum = 0
5940 23:14:40.872841 1, 0xFFFF, sum = 0
5941 23:14:40.872955 2, 0xFFFF, sum = 0
5942 23:14:40.876062 3, 0xFFFF, sum = 0
5943 23:14:40.876144 4, 0xFFFF, sum = 0
5944 23:14:40.879383 5, 0xFFFF, sum = 0
5945 23:14:40.879495 6, 0xFFFF, sum = 0
5946 23:14:40.882898 7, 0xFFFF, sum = 0
5947 23:14:40.882981 8, 0xFFFF, sum = 0
5948 23:14:40.885825 9, 0xFFFF, sum = 0
5949 23:14:40.885908 10, 0x0, sum = 1
5950 23:14:40.889646 11, 0x0, sum = 2
5951 23:14:40.889728 12, 0x0, sum = 3
5952 23:14:40.892525 13, 0x0, sum = 4
5953 23:14:40.892609 best_step = 11
5954 23:14:40.892685
5955 23:14:40.892746 ==
5956 23:14:40.896002 Dram Type= 6, Freq= 0, CH_1, rank 1
5957 23:14:40.902581 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5958 23:14:40.902690 ==
5959 23:14:40.902784 RX Vref Scan: 0
5960 23:14:40.902881
5961 23:14:40.905863 RX Vref 0 -> 0, step: 1
5962 23:14:40.905946
5963 23:14:40.909546 RX Delay -45 -> 252, step: 4
5964 23:14:40.912615 iDelay=203, Bit 0, Center 110 (27 ~ 194) 168
5965 23:14:40.916246 iDelay=203, Bit 1, Center 98 (15 ~ 182) 168
5966 23:14:40.922802 iDelay=203, Bit 2, Center 94 (11 ~ 178) 168
5967 23:14:40.925937 iDelay=203, Bit 3, Center 100 (19 ~ 182) 164
5968 23:14:40.929063 iDelay=203, Bit 4, Center 100 (19 ~ 182) 164
5969 23:14:40.932715 iDelay=203, Bit 5, Center 118 (35 ~ 202) 168
5970 23:14:40.935829 iDelay=203, Bit 6, Center 114 (31 ~ 198) 168
5971 23:14:40.942246 iDelay=203, Bit 7, Center 102 (19 ~ 186) 168
5972 23:14:40.945734 iDelay=203, Bit 8, Center 90 (7 ~ 174) 168
5973 23:14:40.949059 iDelay=203, Bit 9, Center 92 (7 ~ 178) 172
5974 23:14:40.952172 iDelay=203, Bit 10, Center 100 (15 ~ 186) 172
5975 23:14:40.955835 iDelay=203, Bit 11, Center 92 (7 ~ 178) 172
5976 23:14:40.959474 iDelay=203, Bit 12, Center 108 (19 ~ 198) 180
5977 23:14:40.965599 iDelay=203, Bit 13, Center 106 (23 ~ 190) 168
5978 23:14:40.969236 iDelay=203, Bit 14, Center 104 (19 ~ 190) 172
5979 23:14:40.972990 iDelay=203, Bit 15, Center 106 (19 ~ 194) 176
5980 23:14:40.973072 ==
5981 23:14:40.976016 Dram Type= 6, Freq= 0, CH_1, rank 1
5982 23:14:40.979196 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5983 23:14:40.979300 ==
5984 23:14:40.982931 DQS Delay:
5985 23:14:40.983033 DQS0 = 0, DQS1 = 0
5986 23:14:40.986172 DQM Delay:
5987 23:14:40.986271 DQM0 = 104, DQM1 = 99
5988 23:14:40.986369 DQ Delay:
5989 23:14:40.989469 DQ0 =110, DQ1 =98, DQ2 =94, DQ3 =100
5990 23:14:40.996218 DQ4 =100, DQ5 =118, DQ6 =114, DQ7 =102
5991 23:14:40.999823 DQ8 =90, DQ9 =92, DQ10 =100, DQ11 =92
5992 23:14:41.002539 DQ12 =108, DQ13 =106, DQ14 =104, DQ15 =106
5993 23:14:41.002616
5994 23:14:41.002678
5995 23:14:41.009279 [DQSOSCAuto] RK1, (LSB)MR18= 0x2afd, (MSB)MR19= 0x504, tDQSOscB0 = 423 ps tDQSOscB1 = 408 ps
5996 23:14:41.012637 CH1 RK1: MR19=504, MR18=2AFD
5997 23:14:41.019081 CH1_RK1: MR19=0x504, MR18=0x2AFD, DQSOSC=408, MR23=63, INC=65, DEC=43
5998 23:14:41.023052 [RxdqsGatingPostProcess] freq 933
5999 23:14:41.025938 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6000 23:14:41.029732 best DQS0 dly(2T, 0.5T) = (0, 10)
6001 23:14:41.032801 best DQS1 dly(2T, 0.5T) = (0, 10)
6002 23:14:41.035890 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6003 23:14:41.039410 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6004 23:14:41.042901 best DQS0 dly(2T, 0.5T) = (0, 10)
6005 23:14:41.046301 best DQS1 dly(2T, 0.5T) = (0, 10)
6006 23:14:41.049281 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6007 23:14:41.052783 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6008 23:14:41.056149 Pre-setting of DQS Precalculation
6009 23:14:41.059118 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6010 23:14:41.069412 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6011 23:14:41.075813 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6012 23:14:41.075908
6013 23:14:41.075973
6014 23:14:41.078915 [Calibration Summary] 1866 Mbps
6015 23:14:41.078996 CH 0, Rank 0
6016 23:14:41.082621 SW Impedance : PASS
6017 23:14:41.082701 DUTY Scan : NO K
6018 23:14:41.085748 ZQ Calibration : PASS
6019 23:14:41.089399 Jitter Meter : NO K
6020 23:14:41.089478 CBT Training : PASS
6021 23:14:41.092641 Write leveling : PASS
6022 23:14:41.095881 RX DQS gating : PASS
6023 23:14:41.095983 RX DQ/DQS(RDDQC) : PASS
6024 23:14:41.098790 TX DQ/DQS : PASS
6025 23:14:41.102293 RX DATLAT : PASS
6026 23:14:41.102374 RX DQ/DQS(Engine): PASS
6027 23:14:41.105451 TX OE : NO K
6028 23:14:41.105531 All Pass.
6029 23:14:41.105594
6030 23:14:41.108660 CH 0, Rank 1
6031 23:14:41.108756 SW Impedance : PASS
6032 23:14:41.112403 DUTY Scan : NO K
6033 23:14:41.112500 ZQ Calibration : PASS
6034 23:14:41.115535 Jitter Meter : NO K
6035 23:14:41.118976 CBT Training : PASS
6036 23:14:41.119056 Write leveling : PASS
6037 23:14:41.122283 RX DQS gating : PASS
6038 23:14:41.125527 RX DQ/DQS(RDDQC) : PASS
6039 23:14:41.125607 TX DQ/DQS : PASS
6040 23:14:41.128796 RX DATLAT : PASS
6041 23:14:41.131957 RX DQ/DQS(Engine): PASS
6042 23:14:41.132037 TX OE : NO K
6043 23:14:41.135539 All Pass.
6044 23:14:41.135619
6045 23:14:41.135681 CH 1, Rank 0
6046 23:14:41.138490 SW Impedance : PASS
6047 23:14:41.138589 DUTY Scan : NO K
6048 23:14:41.142107 ZQ Calibration : PASS
6049 23:14:41.145465 Jitter Meter : NO K
6050 23:14:41.145548 CBT Training : PASS
6051 23:14:41.148946 Write leveling : PASS
6052 23:14:41.152154 RX DQS gating : PASS
6053 23:14:41.152237 RX DQ/DQS(RDDQC) : PASS
6054 23:14:41.155123 TX DQ/DQS : PASS
6055 23:14:41.158676 RX DATLAT : PASS
6056 23:14:41.158756 RX DQ/DQS(Engine): PASS
6057 23:14:41.161827 TX OE : NO K
6058 23:14:41.161908 All Pass.
6059 23:14:41.161969
6060 23:14:41.165165 CH 1, Rank 1
6061 23:14:41.165289 SW Impedance : PASS
6062 23:14:41.168545 DUTY Scan : NO K
6063 23:14:41.168664 ZQ Calibration : PASS
6064 23:14:41.172209 Jitter Meter : NO K
6065 23:14:41.175104 CBT Training : PASS
6066 23:14:41.175224 Write leveling : PASS
6067 23:14:41.178388 RX DQS gating : PASS
6068 23:14:41.181889 RX DQ/DQS(RDDQC) : PASS
6069 23:14:41.181989 TX DQ/DQS : PASS
6070 23:14:41.185473 RX DATLAT : PASS
6071 23:14:41.188521 RX DQ/DQS(Engine): PASS
6072 23:14:41.188602 TX OE : NO K
6073 23:14:41.192090 All Pass.
6074 23:14:41.192171
6075 23:14:41.192233 DramC Write-DBI off
6076 23:14:41.195184 PER_BANK_REFRESH: Hybrid Mode
6077 23:14:41.195263 TX_TRACKING: ON
6078 23:14:41.205179 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6079 23:14:41.208319 [FAST_K] Save calibration result to emmc
6080 23:14:41.211933 dramc_set_vcore_voltage set vcore to 650000
6081 23:14:41.215076 Read voltage for 400, 6
6082 23:14:41.215158 Vio18 = 0
6083 23:14:41.218656 Vcore = 650000
6084 23:14:41.218736 Vdram = 0
6085 23:14:41.218798 Vddq = 0
6086 23:14:41.221785 Vmddr = 0
6087 23:14:41.224867 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6088 23:14:41.231481 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6089 23:14:41.231607 MEM_TYPE=3, freq_sel=20
6090 23:14:41.234877 sv_algorithm_assistance_LP4_800
6091 23:14:41.238541 ============ PULL DRAM RESETB DOWN ============
6092 23:14:41.245241 ========== PULL DRAM RESETB DOWN end =========
6093 23:14:41.248107 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6094 23:14:41.251439 ===================================
6095 23:14:41.255365 LPDDR4 DRAM CONFIGURATION
6096 23:14:41.258271 ===================================
6097 23:14:41.258353 EX_ROW_EN[0] = 0x0
6098 23:14:41.261825 EX_ROW_EN[1] = 0x0
6099 23:14:41.264813 LP4Y_EN = 0x0
6100 23:14:41.264893 WORK_FSP = 0x0
6101 23:14:41.267921 WL = 0x2
6102 23:14:41.268001 RL = 0x2
6103 23:14:41.271294 BL = 0x2
6104 23:14:41.271417 RPST = 0x0
6105 23:14:41.274779 RD_PRE = 0x0
6106 23:14:41.274860 WR_PRE = 0x1
6107 23:14:41.277927 WR_PST = 0x0
6108 23:14:41.278008 DBI_WR = 0x0
6109 23:14:41.281201 DBI_RD = 0x0
6110 23:14:41.281297 OTF = 0x1
6111 23:14:41.284575 ===================================
6112 23:14:41.288416 ===================================
6113 23:14:41.291582 ANA top config
6114 23:14:41.295019 ===================================
6115 23:14:41.295101 DLL_ASYNC_EN = 0
6116 23:14:41.297778 ALL_SLAVE_EN = 1
6117 23:14:41.301645 NEW_RANK_MODE = 1
6118 23:14:41.304473 DLL_IDLE_MODE = 1
6119 23:14:41.308051 LP45_APHY_COMB_EN = 1
6120 23:14:41.308131 TX_ODT_DIS = 1
6121 23:14:41.311054 NEW_8X_MODE = 1
6122 23:14:41.314655 ===================================
6123 23:14:41.317695 ===================================
6124 23:14:41.321307 data_rate = 800
6125 23:14:41.324387 CKR = 1
6126 23:14:41.327594 DQ_P2S_RATIO = 4
6127 23:14:41.331155 ===================================
6128 23:14:41.331236 CA_P2S_RATIO = 4
6129 23:14:41.334293 DQ_CA_OPEN = 0
6130 23:14:41.337920 DQ_SEMI_OPEN = 1
6131 23:14:41.341218 CA_SEMI_OPEN = 1
6132 23:14:41.344262 CA_FULL_RATE = 0
6133 23:14:41.347944 DQ_CKDIV4_EN = 0
6134 23:14:41.348024 CA_CKDIV4_EN = 1
6135 23:14:41.351042 CA_PREDIV_EN = 0
6136 23:14:41.354161 PH8_DLY = 0
6137 23:14:41.357899 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6138 23:14:41.360788 DQ_AAMCK_DIV = 0
6139 23:14:41.364478 CA_AAMCK_DIV = 0
6140 23:14:41.364557 CA_ADMCK_DIV = 4
6141 23:14:41.367579 DQ_TRACK_CA_EN = 0
6142 23:14:41.371253 CA_PICK = 800
6143 23:14:41.374123 CA_MCKIO = 400
6144 23:14:41.377835 MCKIO_SEMI = 400
6145 23:14:41.380759 PLL_FREQ = 3016
6146 23:14:41.384276 DQ_UI_PI_RATIO = 32
6147 23:14:41.387487 CA_UI_PI_RATIO = 32
6148 23:14:41.390842 ===================================
6149 23:14:41.394191 ===================================
6150 23:14:41.394276 memory_type:LPDDR4
6151 23:14:41.397193 GP_NUM : 10
6152 23:14:41.397277 SRAM_EN : 1
6153 23:14:41.400762 MD32_EN : 0
6154 23:14:41.403999 ===================================
6155 23:14:41.407488 [ANA_INIT] >>>>>>>>>>>>>>
6156 23:14:41.410957 <<<<<< [CONFIGURE PHASE]: ANA_TX
6157 23:14:41.414079 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6158 23:14:41.417492 ===================================
6159 23:14:41.417577 data_rate = 800,PCW = 0X7400
6160 23:14:41.420708 ===================================
6161 23:14:41.423986 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6162 23:14:41.430838 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6163 23:14:41.444000 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6164 23:14:41.447401 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6165 23:14:41.450460 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6166 23:14:41.454116 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6167 23:14:41.457282 [ANA_INIT] flow start
6168 23:14:41.457362 [ANA_INIT] PLL >>>>>>>>
6169 23:14:41.460744 [ANA_INIT] PLL <<<<<<<<
6170 23:14:41.463870 [ANA_INIT] MIDPI >>>>>>>>
6171 23:14:41.463950 [ANA_INIT] MIDPI <<<<<<<<
6172 23:14:41.467547 [ANA_INIT] DLL >>>>>>>>
6173 23:14:41.470682 [ANA_INIT] flow end
6174 23:14:41.474233 ============ LP4 DIFF to SE enter ============
6175 23:14:41.477573 ============ LP4 DIFF to SE exit ============
6176 23:14:41.480622 [ANA_INIT] <<<<<<<<<<<<<
6177 23:14:41.484450 [Flow] Enable top DCM control >>>>>
6178 23:14:41.487448 [Flow] Enable top DCM control <<<<<
6179 23:14:41.490532 Enable DLL master slave shuffle
6180 23:14:41.494147 ==============================================================
6181 23:14:41.497731 Gating Mode config
6182 23:14:41.504232 ==============================================================
6183 23:14:41.504342 Config description:
6184 23:14:41.513932 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6185 23:14:41.520926 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6186 23:14:41.523952 SELPH_MODE 0: By rank 1: By Phase
6187 23:14:41.530907 ==============================================================
6188 23:14:41.533831 GAT_TRACK_EN = 0
6189 23:14:41.537758 RX_GATING_MODE = 2
6190 23:14:41.540531 RX_GATING_TRACK_MODE = 2
6191 23:14:41.543955 SELPH_MODE = 1
6192 23:14:41.547375 PICG_EARLY_EN = 1
6193 23:14:41.550364 VALID_LAT_VALUE = 1
6194 23:14:41.553792 ==============================================================
6195 23:14:41.557307 Enter into Gating configuration >>>>
6196 23:14:41.560561 Exit from Gating configuration <<<<
6197 23:14:41.564161 Enter into DVFS_PRE_config >>>>>
6198 23:14:41.573666 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6199 23:14:41.577112 Exit from DVFS_PRE_config <<<<<
6200 23:14:41.580707 Enter into PICG configuration >>>>
6201 23:14:41.583947 Exit from PICG configuration <<<<
6202 23:14:41.587616 [RX_INPUT] configuration >>>>>
6203 23:14:41.590659 [RX_INPUT] configuration <<<<<
6204 23:14:41.597345 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6205 23:14:41.600475 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6206 23:14:41.607192 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6207 23:14:41.614070 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6208 23:14:41.620735 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6209 23:14:41.627324 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6210 23:14:41.630261 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6211 23:14:41.633950 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6212 23:14:41.636952 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6213 23:14:41.643661 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6214 23:14:41.647461 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6215 23:14:41.650360 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6216 23:14:41.654126 ===================================
6217 23:14:41.657104 LPDDR4 DRAM CONFIGURATION
6218 23:14:41.660676 ===================================
6219 23:14:41.660756 EX_ROW_EN[0] = 0x0
6220 23:14:41.663997 EX_ROW_EN[1] = 0x0
6221 23:14:41.666763 LP4Y_EN = 0x0
6222 23:14:41.666915 WORK_FSP = 0x0
6223 23:14:41.670607 WL = 0x2
6224 23:14:41.670687 RL = 0x2
6225 23:14:41.673757 BL = 0x2
6226 23:14:41.673837 RPST = 0x0
6227 23:14:41.676879 RD_PRE = 0x0
6228 23:14:41.676996 WR_PRE = 0x1
6229 23:14:41.680587 WR_PST = 0x0
6230 23:14:41.680671 DBI_WR = 0x0
6231 23:14:41.683612 DBI_RD = 0x0
6232 23:14:41.683697 OTF = 0x1
6233 23:14:41.686841 ===================================
6234 23:14:41.690101 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6235 23:14:41.697015 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6236 23:14:41.700189 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6237 23:14:41.703785 ===================================
6238 23:14:41.706929 LPDDR4 DRAM CONFIGURATION
6239 23:14:41.710133 ===================================
6240 23:14:41.710218 EX_ROW_EN[0] = 0x10
6241 23:14:41.713563 EX_ROW_EN[1] = 0x0
6242 23:14:41.713651 LP4Y_EN = 0x0
6243 23:14:41.717120 WORK_FSP = 0x0
6244 23:14:41.717223 WL = 0x2
6245 23:14:41.720062 RL = 0x2
6246 23:14:41.720170 BL = 0x2
6247 23:14:41.723682 RPST = 0x0
6248 23:14:41.726561 RD_PRE = 0x0
6249 23:14:41.726643 WR_PRE = 0x1
6250 23:14:41.729719 WR_PST = 0x0
6251 23:14:41.729800 DBI_WR = 0x0
6252 23:14:41.733121 DBI_RD = 0x0
6253 23:14:41.733203 OTF = 0x1
6254 23:14:41.736668 ===================================
6255 23:14:41.743381 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6256 23:14:41.747035 nWR fixed to 30
6257 23:14:41.750648 [ModeRegInit_LP4] CH0 RK0
6258 23:14:41.750730 [ModeRegInit_LP4] CH0 RK1
6259 23:14:41.753607 [ModeRegInit_LP4] CH1 RK0
6260 23:14:41.757227 [ModeRegInit_LP4] CH1 RK1
6261 23:14:41.757310 match AC timing 19
6262 23:14:41.763592 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6263 23:14:41.767016 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6264 23:14:41.770109 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6265 23:14:41.776859 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6266 23:14:41.780508 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6267 23:14:41.780594 ==
6268 23:14:41.783481 Dram Type= 6, Freq= 0, CH_0, rank 0
6269 23:14:41.786944 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6270 23:14:41.787026 ==
6271 23:14:41.793620 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6272 23:14:41.799992 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6273 23:14:41.803798 [CA 0] Center 36 (8~64) winsize 57
6274 23:14:41.807085 [CA 1] Center 36 (8~64) winsize 57
6275 23:14:41.810269 [CA 2] Center 36 (8~64) winsize 57
6276 23:14:41.810352 [CA 3] Center 36 (8~64) winsize 57
6277 23:14:41.813391 [CA 4] Center 36 (8~64) winsize 57
6278 23:14:41.817077 [CA 5] Center 36 (8~64) winsize 57
6279 23:14:41.817227
6280 23:14:41.823644 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6281 23:14:41.823729
6282 23:14:41.826730 [CATrainingPosCal] consider 1 rank data
6283 23:14:41.830141 u2DelayCellTimex100 = 270/100 ps
6284 23:14:41.833763 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6285 23:14:41.836711 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6286 23:14:41.840117 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6287 23:14:41.843261 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6288 23:14:41.846526 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6289 23:14:41.850098 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6290 23:14:41.850177
6291 23:14:41.853332 CA PerBit enable=1, Macro0, CA PI delay=36
6292 23:14:41.853437
6293 23:14:41.856264 [CBTSetCACLKResult] CA Dly = 36
6294 23:14:41.860014 CS Dly: 1 (0~32)
6295 23:14:41.860118 ==
6296 23:14:41.862848 Dram Type= 6, Freq= 0, CH_0, rank 1
6297 23:14:41.866541 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6298 23:14:41.866665 ==
6299 23:14:41.873027 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6300 23:14:41.876794 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6301 23:14:41.879735 [CA 0] Center 36 (8~64) winsize 57
6302 23:14:41.883296 [CA 1] Center 36 (8~64) winsize 57
6303 23:14:41.886529 [CA 2] Center 36 (8~64) winsize 57
6304 23:14:41.889795 [CA 3] Center 36 (8~64) winsize 57
6305 23:14:41.893576 [CA 4] Center 36 (8~64) winsize 57
6306 23:14:41.896611 [CA 5] Center 36 (8~64) winsize 57
6307 23:14:41.896695
6308 23:14:41.899764 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6309 23:14:41.899847
6310 23:14:41.903344 [CATrainingPosCal] consider 2 rank data
6311 23:14:41.906517 u2DelayCellTimex100 = 270/100 ps
6312 23:14:41.910046 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6313 23:14:41.913056 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6314 23:14:41.916797 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6315 23:14:41.923243 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6316 23:14:41.926698 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6317 23:14:41.929977 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6318 23:14:41.930061
6319 23:14:41.932920 CA PerBit enable=1, Macro0, CA PI delay=36
6320 23:14:41.933004
6321 23:14:41.936531 [CBTSetCACLKResult] CA Dly = 36
6322 23:14:41.936640 CS Dly: 1 (0~32)
6323 23:14:41.936725
6324 23:14:41.939879 ----->DramcWriteLeveling(PI) begin...
6325 23:14:41.939988 ==
6326 23:14:41.943121 Dram Type= 6, Freq= 0, CH_0, rank 0
6327 23:14:41.949751 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6328 23:14:41.949832 ==
6329 23:14:41.953184 Write leveling (Byte 0): 40 => 8
6330 23:14:41.956939 Write leveling (Byte 1): 40 => 8
6331 23:14:41.957020 DramcWriteLeveling(PI) end<-----
6332 23:14:41.957084
6333 23:14:41.960042 ==
6334 23:14:41.962978 Dram Type= 6, Freq= 0, CH_0, rank 0
6335 23:14:41.966815 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6336 23:14:41.966896 ==
6337 23:14:41.969985 [Gating] SW mode calibration
6338 23:14:41.976265 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6339 23:14:41.979744 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6340 23:14:41.986581 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6341 23:14:41.989754 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6342 23:14:41.993320 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6343 23:14:41.999508 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6344 23:14:42.003219 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6345 23:14:42.006329 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6346 23:14:42.013269 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6347 23:14:42.016571 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6348 23:14:42.019916 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6349 23:14:42.023003 Total UI for P1: 0, mck2ui 16
6350 23:14:42.026776 best dqsien dly found for B0: ( 0, 14, 24)
6351 23:14:42.029894 Total UI for P1: 0, mck2ui 16
6352 23:14:42.032983 best dqsien dly found for B1: ( 0, 14, 24)
6353 23:14:42.036627 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6354 23:14:42.039573 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6355 23:14:42.039655
6356 23:14:42.046172 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6357 23:14:42.049743 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6358 23:14:42.049866 [Gating] SW calibration Done
6359 23:14:42.052758 ==
6360 23:14:42.052876 Dram Type= 6, Freq= 0, CH_0, rank 0
6361 23:14:42.059481 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6362 23:14:42.059633 ==
6363 23:14:42.059793 RX Vref Scan: 0
6364 23:14:42.059900
6365 23:14:42.062532 RX Vref 0 -> 0, step: 1
6366 23:14:42.062664
6367 23:14:42.065824 RX Delay -410 -> 252, step: 16
6368 23:14:42.069442 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6369 23:14:42.072564 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6370 23:14:42.079344 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6371 23:14:42.082910 iDelay=230, Bit 3, Center -27 (-266 ~ 213) 480
6372 23:14:42.085963 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6373 23:14:42.089083 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6374 23:14:42.095787 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6375 23:14:42.099230 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6376 23:14:42.102819 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6377 23:14:42.105822 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6378 23:14:42.112576 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6379 23:14:42.115660 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6380 23:14:42.118988 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6381 23:14:42.125366 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6382 23:14:42.128768 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6383 23:14:42.132458 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6384 23:14:42.132580 ==
6385 23:14:42.135519 Dram Type= 6, Freq= 0, CH_0, rank 0
6386 23:14:42.139162 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6387 23:14:42.139287 ==
6388 23:14:42.142300 DQS Delay:
6389 23:14:42.142421 DQS0 = 27, DQS1 = 35
6390 23:14:42.145869 DQM Delay:
6391 23:14:42.145989 DQM0 = 10, DQM1 = 11
6392 23:14:42.148667 DQ Delay:
6393 23:14:42.148788 DQ0 =8, DQ1 =16, DQ2 =0, DQ3 =0
6394 23:14:42.152237 DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =24
6395 23:14:42.155524 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6396 23:14:42.159060 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6397 23:14:42.159181
6398 23:14:42.159287
6399 23:14:42.159395 ==
6400 23:14:42.162070 Dram Type= 6, Freq= 0, CH_0, rank 0
6401 23:14:42.168778 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6402 23:14:42.168901 ==
6403 23:14:42.169014
6404 23:14:42.169120
6405 23:14:42.169228 TX Vref Scan disable
6406 23:14:42.172434 == TX Byte 0 ==
6407 23:14:42.175623 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6408 23:14:42.178655 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6409 23:14:42.182080 == TX Byte 1 ==
6410 23:14:42.185325 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6411 23:14:42.188853 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6412 23:14:42.188954 ==
6413 23:14:42.192176 Dram Type= 6, Freq= 0, CH_0, rank 0
6414 23:14:42.198955 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6415 23:14:42.199038 ==
6416 23:14:42.199101
6417 23:14:42.199159
6418 23:14:42.199216 TX Vref Scan disable
6419 23:14:42.202161 == TX Byte 0 ==
6420 23:14:42.205321 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6421 23:14:42.208664 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6422 23:14:42.211941 == TX Byte 1 ==
6423 23:14:42.215385 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6424 23:14:42.218762 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6425 23:14:42.218843
6426 23:14:42.222069 [DATLAT]
6427 23:14:42.222150 Freq=400, CH0 RK0
6428 23:14:42.222213
6429 23:14:42.225548 DATLAT Default: 0xf
6430 23:14:42.225629 0, 0xFFFF, sum = 0
6431 23:14:42.228498 1, 0xFFFF, sum = 0
6432 23:14:42.228581 2, 0xFFFF, sum = 0
6433 23:14:42.231900 3, 0xFFFF, sum = 0
6434 23:14:42.232027 4, 0xFFFF, sum = 0
6435 23:14:42.235394 5, 0xFFFF, sum = 0
6436 23:14:42.235520 6, 0xFFFF, sum = 0
6437 23:14:42.238517 7, 0xFFFF, sum = 0
6438 23:14:42.238639 8, 0xFFFF, sum = 0
6439 23:14:42.242054 9, 0xFFFF, sum = 0
6440 23:14:42.245149 10, 0xFFFF, sum = 0
6441 23:14:42.245269 11, 0xFFFF, sum = 0
6442 23:14:42.248840 12, 0xFFFF, sum = 0
6443 23:14:42.248959 13, 0x0, sum = 1
6444 23:14:42.251794 14, 0x0, sum = 2
6445 23:14:42.251896 15, 0x0, sum = 3
6446 23:14:42.255043 16, 0x0, sum = 4
6447 23:14:42.255142 best_step = 14
6448 23:14:42.255229
6449 23:14:42.255313 ==
6450 23:14:42.258706 Dram Type= 6, Freq= 0, CH_0, rank 0
6451 23:14:42.261829 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6452 23:14:42.261909 ==
6453 23:14:42.264816 RX Vref Scan: 1
6454 23:14:42.264895
6455 23:14:42.268396 RX Vref 0 -> 0, step: 1
6456 23:14:42.268478
6457 23:14:42.268553 RX Delay -311 -> 252, step: 8
6458 23:14:42.268611
6459 23:14:42.271546 Set Vref, RX VrefLevel [Byte0]: 55
6460 23:14:42.275103 [Byte1]: 49
6461 23:14:42.279979
6462 23:14:42.280112 Final RX Vref Byte 0 = 55 to rank0
6463 23:14:42.283643 Final RX Vref Byte 1 = 49 to rank0
6464 23:14:42.286639 Final RX Vref Byte 0 = 55 to rank1
6465 23:14:42.290329 Final RX Vref Byte 1 = 49 to rank1==
6466 23:14:42.293988 Dram Type= 6, Freq= 0, CH_0, rank 0
6467 23:14:42.300676 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6468 23:14:42.300755 ==
6469 23:14:42.300817 DQS Delay:
6470 23:14:42.300875 DQS0 = 28, DQS1 = 36
6471 23:14:42.303765 DQM Delay:
6472 23:14:42.303843 DQM0 = 11, DQM1 = 12
6473 23:14:42.307279 DQ Delay:
6474 23:14:42.307358 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6475 23:14:42.310261 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6476 23:14:42.313890 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =4
6477 23:14:42.316877 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6478 23:14:42.316955
6479 23:14:42.317017
6480 23:14:42.326873 [DQSOSCAuto] RK0, (LSB)MR18= 0xcebb, (MSB)MR19= 0xc0c, tDQSOscB0 = 386 ps tDQSOscB1 = 384 ps
6481 23:14:42.330318 CH0 RK0: MR19=C0C, MR18=CEBB
6482 23:14:42.336905 CH0_RK0: MR19=0xC0C, MR18=0xCEBB, DQSOSC=384, MR23=63, INC=400, DEC=267
6483 23:14:42.337012 ==
6484 23:14:42.340385 Dram Type= 6, Freq= 0, CH_0, rank 1
6485 23:14:42.343331 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6486 23:14:42.343412 ==
6487 23:14:42.347003 [Gating] SW mode calibration
6488 23:14:42.353699 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6489 23:14:42.357155 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6490 23:14:42.363985 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6491 23:14:42.367077 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6492 23:14:42.370480 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6493 23:14:42.376618 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6494 23:14:42.380194 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6495 23:14:42.383432 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6496 23:14:42.389792 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6497 23:14:42.393235 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6498 23:14:42.396873 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6499 23:14:42.399939 Total UI for P1: 0, mck2ui 16
6500 23:14:42.402958 best dqsien dly found for B0: ( 0, 14, 24)
6501 23:14:42.406737 Total UI for P1: 0, mck2ui 16
6502 23:14:42.409797 best dqsien dly found for B1: ( 0, 14, 24)
6503 23:14:42.413280 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6504 23:14:42.419909 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6505 23:14:42.419988
6506 23:14:42.422860 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6507 23:14:42.426570 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6508 23:14:42.429743 [Gating] SW calibration Done
6509 23:14:42.429822 ==
6510 23:14:42.432885 Dram Type= 6, Freq= 0, CH_0, rank 1
6511 23:14:42.436689 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6512 23:14:42.436770 ==
6513 23:14:42.436833 RX Vref Scan: 0
6514 23:14:42.439608
6515 23:14:42.439686 RX Vref 0 -> 0, step: 1
6516 23:14:42.439749
6517 23:14:42.442626 RX Delay -410 -> 252, step: 16
6518 23:14:42.446267 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6519 23:14:42.452944 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6520 23:14:42.456434 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6521 23:14:42.459862 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6522 23:14:42.462950 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6523 23:14:42.469898 iDelay=230, Bit 5, Center -19 (-250 ~ 213) 464
6524 23:14:42.472992 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6525 23:14:42.475972 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6526 23:14:42.479314 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6527 23:14:42.486223 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6528 23:14:42.489413 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6529 23:14:42.492540 iDelay=230, Bit 11, Center -27 (-250 ~ 197) 448
6530 23:14:42.496309 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6531 23:14:42.502875 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6532 23:14:42.506164 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6533 23:14:42.509219 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6534 23:14:42.509300 ==
6535 23:14:42.512894 Dram Type= 6, Freq= 0, CH_0, rank 1
6536 23:14:42.515850 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6537 23:14:42.519329 ==
6538 23:14:42.519411 DQS Delay:
6539 23:14:42.519475 DQS0 = 19, DQS1 = 35
6540 23:14:42.522485 DQM Delay:
6541 23:14:42.522566 DQM0 = 4, DQM1 = 12
6542 23:14:42.526132 DQ Delay:
6543 23:14:42.526213 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6544 23:14:42.529581 DQ4 =8, DQ5 =0, DQ6 =8, DQ7 =16
6545 23:14:42.532751 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6546 23:14:42.536542 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6547 23:14:42.536622
6548 23:14:42.536686
6549 23:14:42.536744 ==
6550 23:14:42.539615 Dram Type= 6, Freq= 0, CH_0, rank 1
6551 23:14:42.546235 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6552 23:14:42.546316 ==
6553 23:14:42.546379
6554 23:14:42.546438
6555 23:14:42.546494 TX Vref Scan disable
6556 23:14:42.549266 == TX Byte 0 ==
6557 23:14:42.552864 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6558 23:14:42.555828 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6559 23:14:42.559338 == TX Byte 1 ==
6560 23:14:42.562379 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6561 23:14:42.565939 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6562 23:14:42.566020 ==
6563 23:14:42.568934 Dram Type= 6, Freq= 0, CH_0, rank 1
6564 23:14:42.575719 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6565 23:14:42.575802 ==
6566 23:14:42.575866
6567 23:14:42.575925
6568 23:14:42.579360 TX Vref Scan disable
6569 23:14:42.579441 == TX Byte 0 ==
6570 23:14:42.582386 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6571 23:14:42.585995 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6572 23:14:42.588945 == TX Byte 1 ==
6573 23:14:42.592788 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6574 23:14:42.595671 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6575 23:14:42.595791
6576 23:14:42.599082 [DATLAT]
6577 23:14:42.599202 Freq=400, CH0 RK1
6578 23:14:42.599314
6579 23:14:42.602307 DATLAT Default: 0xe
6580 23:14:42.602426 0, 0xFFFF, sum = 0
6581 23:14:42.605769 1, 0xFFFF, sum = 0
6582 23:14:42.605898 2, 0xFFFF, sum = 0
6583 23:14:42.609205 3, 0xFFFF, sum = 0
6584 23:14:42.609305 4, 0xFFFF, sum = 0
6585 23:14:42.612468 5, 0xFFFF, sum = 0
6586 23:14:42.612619 6, 0xFFFF, sum = 0
6587 23:14:42.615767 7, 0xFFFF, sum = 0
6588 23:14:42.615866 8, 0xFFFF, sum = 0
6589 23:14:42.618898 9, 0xFFFF, sum = 0
6590 23:14:42.622540 10, 0xFFFF, sum = 0
6591 23:14:42.622654 11, 0xFFFF, sum = 0
6592 23:14:42.625429 12, 0xFFFF, sum = 0
6593 23:14:42.625509 13, 0x0, sum = 1
6594 23:14:42.628774 14, 0x0, sum = 2
6595 23:14:42.628854 15, 0x0, sum = 3
6596 23:14:42.632157 16, 0x0, sum = 4
6597 23:14:42.632238 best_step = 14
6598 23:14:42.632323
6599 23:14:42.632428 ==
6600 23:14:42.635745 Dram Type= 6, Freq= 0, CH_0, rank 1
6601 23:14:42.638822 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6602 23:14:42.638904 ==
6603 23:14:42.642220 RX Vref Scan: 0
6604 23:14:42.642301
6605 23:14:42.645881 RX Vref 0 -> 0, step: 1
6606 23:14:42.645971
6607 23:14:42.646034 RX Delay -311 -> 252, step: 8
6608 23:14:42.653923 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6609 23:14:42.657484 iDelay=217, Bit 1, Center -12 (-231 ~ 208) 440
6610 23:14:42.660626 iDelay=217, Bit 2, Center -16 (-239 ~ 208) 448
6611 23:14:42.664138 iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448
6612 23:14:42.670555 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6613 23:14:42.674070 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6614 23:14:42.677183 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6615 23:14:42.680699 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6616 23:14:42.687545 iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448
6617 23:14:42.690523 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6618 23:14:42.694149 iDelay=217, Bit 10, Center -20 (-239 ~ 200) 440
6619 23:14:42.697244 iDelay=217, Bit 11, Center -28 (-247 ~ 192) 440
6620 23:14:42.703895 iDelay=217, Bit 12, Center -20 (-239 ~ 200) 440
6621 23:14:42.706984 iDelay=217, Bit 13, Center -20 (-239 ~ 200) 440
6622 23:14:42.710341 iDelay=217, Bit 14, Center -12 (-231 ~ 208) 440
6623 23:14:42.716949 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6624 23:14:42.717060 ==
6625 23:14:42.720584 Dram Type= 6, Freq= 0, CH_0, rank 1
6626 23:14:42.723581 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6627 23:14:42.723663 ==
6628 23:14:42.723727 DQS Delay:
6629 23:14:42.727046 DQS0 = 24, DQS1 = 32
6630 23:14:42.727128 DQM Delay:
6631 23:14:42.730828 DQM0 = 9, DQM1 = 9
6632 23:14:42.730910 DQ Delay:
6633 23:14:42.733661 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =8
6634 23:14:42.736828 DQ4 =8, DQ5 =0, DQ6 =12, DQ7 =16
6635 23:14:42.740798 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6636 23:14:42.743829 DQ12 =12, DQ13 =12, DQ14 =20, DQ15 =16
6637 23:14:42.743907
6638 23:14:42.743970
6639 23:14:42.750031 [DQSOSCAuto] RK1, (LSB)MR18= 0xbb5c, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 386 ps
6640 23:14:42.753564 CH0 RK1: MR19=C0C, MR18=BB5C
6641 23:14:42.760256 CH0_RK1: MR19=0xC0C, MR18=0xBB5C, DQSOSC=386, MR23=63, INC=396, DEC=264
6642 23:14:42.763902 [RxdqsGatingPostProcess] freq 400
6643 23:14:42.767031 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6644 23:14:42.770212 best DQS0 dly(2T, 0.5T) = (0, 10)
6645 23:14:42.773995 best DQS1 dly(2T, 0.5T) = (0, 10)
6646 23:14:42.776702 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6647 23:14:42.780184 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6648 23:14:42.783840 best DQS0 dly(2T, 0.5T) = (0, 10)
6649 23:14:42.786850 best DQS1 dly(2T, 0.5T) = (0, 10)
6650 23:14:42.790489 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6651 23:14:42.793515 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6652 23:14:42.796982 Pre-setting of DQS Precalculation
6653 23:14:42.800042 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6654 23:14:42.803705 ==
6655 23:14:42.803787 Dram Type= 6, Freq= 0, CH_1, rank 0
6656 23:14:42.810511 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6657 23:14:42.810593 ==
6658 23:14:42.813572 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6659 23:14:42.819968 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6660 23:14:42.823542 [CA 0] Center 36 (8~64) winsize 57
6661 23:14:42.826622 [CA 1] Center 36 (8~64) winsize 57
6662 23:14:42.830264 [CA 2] Center 36 (8~64) winsize 57
6663 23:14:42.833731 [CA 3] Center 36 (8~64) winsize 57
6664 23:14:42.836708 [CA 4] Center 36 (8~64) winsize 57
6665 23:14:42.840441 [CA 5] Center 36 (8~64) winsize 57
6666 23:14:42.840522
6667 23:14:42.843381 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6668 23:14:42.843462
6669 23:14:42.846886 [CATrainingPosCal] consider 1 rank data
6670 23:14:42.849939 u2DelayCellTimex100 = 270/100 ps
6671 23:14:42.853664 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6672 23:14:42.856676 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6673 23:14:42.860233 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6674 23:14:42.863454 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6675 23:14:42.866960 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6676 23:14:42.873307 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6677 23:14:42.873388
6678 23:14:42.876454 CA PerBit enable=1, Macro0, CA PI delay=36
6679 23:14:42.876537
6680 23:14:42.879981 [CBTSetCACLKResult] CA Dly = 36
6681 23:14:42.880061 CS Dly: 1 (0~32)
6682 23:14:42.880125 ==
6683 23:14:42.883053 Dram Type= 6, Freq= 0, CH_1, rank 1
6684 23:14:42.886816 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6685 23:14:42.889994 ==
6686 23:14:42.893149 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6687 23:14:42.899803 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6688 23:14:42.903456 [CA 0] Center 36 (8~64) winsize 57
6689 23:14:42.906510 [CA 1] Center 36 (8~64) winsize 57
6690 23:14:42.909893 [CA 2] Center 36 (8~64) winsize 57
6691 23:14:42.912959 [CA 3] Center 36 (8~64) winsize 57
6692 23:14:42.916584 [CA 4] Center 36 (8~64) winsize 57
6693 23:14:42.920087 [CA 5] Center 36 (8~64) winsize 57
6694 23:14:42.920169
6695 23:14:42.922989 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6696 23:14:42.923072
6697 23:14:42.926678 [CATrainingPosCal] consider 2 rank data
6698 23:14:42.929730 u2DelayCellTimex100 = 270/100 ps
6699 23:14:42.933479 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6700 23:14:42.936498 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6701 23:14:42.940153 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6702 23:14:42.943408 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6703 23:14:42.946442 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6704 23:14:42.949979 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6705 23:14:42.950086
6706 23:14:42.952984 CA PerBit enable=1, Macro0, CA PI delay=36
6707 23:14:42.953083
6708 23:14:42.956684 [CBTSetCACLKResult] CA Dly = 36
6709 23:14:42.959638 CS Dly: 1 (0~32)
6710 23:14:42.959719
6711 23:14:42.963226 ----->DramcWriteLeveling(PI) begin...
6712 23:14:42.963310 ==
6713 23:14:42.966331 Dram Type= 6, Freq= 0, CH_1, rank 0
6714 23:14:42.970143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6715 23:14:42.970232 ==
6716 23:14:42.972967 Write leveling (Byte 0): 40 => 8
6717 23:14:42.976441 Write leveling (Byte 1): 40 => 8
6718 23:14:42.980009 DramcWriteLeveling(PI) end<-----
6719 23:14:42.980094
6720 23:14:42.980156 ==
6721 23:14:42.983148 Dram Type= 6, Freq= 0, CH_1, rank 0
6722 23:14:42.986309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6723 23:14:42.986391 ==
6724 23:14:42.989411 [Gating] SW mode calibration
6725 23:14:42.996049 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6726 23:14:43.002679 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6727 23:14:43.006145 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6728 23:14:43.012948 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6729 23:14:43.016246 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6730 23:14:43.019328 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6731 23:14:43.025962 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6732 23:14:43.029325 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6733 23:14:43.032520 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6734 23:14:43.035919 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6735 23:14:43.042933 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6736 23:14:43.045920 Total UI for P1: 0, mck2ui 16
6737 23:14:43.049235 best dqsien dly found for B0: ( 0, 14, 24)
6738 23:14:43.052735 Total UI for P1: 0, mck2ui 16
6739 23:14:43.056023 best dqsien dly found for B1: ( 0, 14, 24)
6740 23:14:43.059057 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6741 23:14:43.062696 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6742 23:14:43.062776
6743 23:14:43.065701 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6744 23:14:43.069374 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6745 23:14:43.072449 [Gating] SW calibration Done
6746 23:14:43.072529 ==
6747 23:14:43.075602 Dram Type= 6, Freq= 0, CH_1, rank 0
6748 23:14:43.078929 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6749 23:14:43.079027 ==
6750 23:14:43.082398 RX Vref Scan: 0
6751 23:14:43.082479
6752 23:14:43.085535 RX Vref 0 -> 0, step: 1
6753 23:14:43.085617
6754 23:14:43.085681 RX Delay -410 -> 252, step: 16
6755 23:14:43.092296 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6756 23:14:43.096108 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6757 23:14:43.099176 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6758 23:14:43.102642 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6759 23:14:43.108834 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6760 23:14:43.112668 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6761 23:14:43.115798 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6762 23:14:43.118809 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6763 23:14:43.125596 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6764 23:14:43.129209 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6765 23:14:43.132160 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6766 23:14:43.135789 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6767 23:14:43.142489 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6768 23:14:43.145583 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6769 23:14:43.148765 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6770 23:14:43.155502 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6771 23:14:43.155588 ==
6772 23:14:43.159295 Dram Type= 6, Freq= 0, CH_1, rank 0
6773 23:14:43.162474 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6774 23:14:43.162557 ==
6775 23:14:43.162621 DQS Delay:
6776 23:14:43.165430 DQS0 = 35, DQS1 = 35
6777 23:14:43.165510 DQM Delay:
6778 23:14:43.168889 DQM0 = 17, DQM1 = 13
6779 23:14:43.168970 DQ Delay:
6780 23:14:43.172180 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =16
6781 23:14:43.176043 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6782 23:14:43.178619 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6783 23:14:43.181983 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6784 23:14:43.182091
6785 23:14:43.182183
6786 23:14:43.182271 ==
6787 23:14:43.185375 Dram Type= 6, Freq= 0, CH_1, rank 0
6788 23:14:43.188767 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6789 23:14:43.188890 ==
6790 23:14:43.189003
6791 23:14:43.189161
6792 23:14:43.191897 TX Vref Scan disable
6793 23:14:43.192016 == TX Byte 0 ==
6794 23:14:43.198828 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6795 23:14:43.202537 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6796 23:14:43.202619 == TX Byte 1 ==
6797 23:14:43.208764 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6798 23:14:43.212234 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6799 23:14:43.212340 ==
6800 23:14:43.215296 Dram Type= 6, Freq= 0, CH_1, rank 0
6801 23:14:43.219011 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6802 23:14:43.219093 ==
6803 23:14:43.219157
6804 23:14:43.219217
6805 23:14:43.222058 TX Vref Scan disable
6806 23:14:43.225767 == TX Byte 0 ==
6807 23:14:43.228974 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6808 23:14:43.231934 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6809 23:14:43.232016 == TX Byte 1 ==
6810 23:14:43.238560 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6811 23:14:43.242306 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6812 23:14:43.242389
6813 23:14:43.242452 [DATLAT]
6814 23:14:43.245260 Freq=400, CH1 RK0
6815 23:14:43.245341
6816 23:14:43.245404 DATLAT Default: 0xf
6817 23:14:43.248812 0, 0xFFFF, sum = 0
6818 23:14:43.248895 1, 0xFFFF, sum = 0
6819 23:14:43.251812 2, 0xFFFF, sum = 0
6820 23:14:43.251896 3, 0xFFFF, sum = 0
6821 23:14:43.255666 4, 0xFFFF, sum = 0
6822 23:14:43.255747 5, 0xFFFF, sum = 0
6823 23:14:43.258592 6, 0xFFFF, sum = 0
6824 23:14:43.262185 7, 0xFFFF, sum = 0
6825 23:14:43.262266 8, 0xFFFF, sum = 0
6826 23:14:43.265165 9, 0xFFFF, sum = 0
6827 23:14:43.265247 10, 0xFFFF, sum = 0
6828 23:14:43.268828 11, 0xFFFF, sum = 0
6829 23:14:43.268923 12, 0xFFFF, sum = 0
6830 23:14:43.271865 13, 0x0, sum = 1
6831 23:14:43.271947 14, 0x0, sum = 2
6832 23:14:43.275014 15, 0x0, sum = 3
6833 23:14:43.275096 16, 0x0, sum = 4
6834 23:14:43.275161 best_step = 14
6835 23:14:43.278638
6836 23:14:43.278718 ==
6837 23:14:43.282234 Dram Type= 6, Freq= 0, CH_1, rank 0
6838 23:14:43.285305 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6839 23:14:43.285400 ==
6840 23:14:43.285463 RX Vref Scan: 1
6841 23:14:43.285521
6842 23:14:43.288885 RX Vref 0 -> 0, step: 1
6843 23:14:43.288996
6844 23:14:43.292096 RX Delay -311 -> 252, step: 8
6845 23:14:43.292216
6846 23:14:43.295180 Set Vref, RX VrefLevel [Byte0]: 54
6847 23:14:43.298567 [Byte1]: 55
6848 23:14:43.302261
6849 23:14:43.302340 Final RX Vref Byte 0 = 54 to rank0
6850 23:14:43.305398 Final RX Vref Byte 1 = 55 to rank0
6851 23:14:43.308658 Final RX Vref Byte 0 = 54 to rank1
6852 23:14:43.312187 Final RX Vref Byte 1 = 55 to rank1==
6853 23:14:43.315031 Dram Type= 6, Freq= 0, CH_1, rank 0
6854 23:14:43.321797 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6855 23:14:43.321908 ==
6856 23:14:43.322001 DQS Delay:
6857 23:14:43.325305 DQS0 = 32, DQS1 = 32
6858 23:14:43.325485 DQM Delay:
6859 23:14:43.325587 DQM0 = 13, DQM1 = 9
6860 23:14:43.328542 DQ Delay:
6861 23:14:43.332184 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6862 23:14:43.335298 DQ4 =16, DQ5 =24, DQ6 =20, DQ7 =12
6863 23:14:43.335423 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6864 23:14:43.338914 DQ12 =16, DQ13 =16, DQ14 =20, DQ15 =16
6865 23:14:43.339035
6866 23:14:43.341862
6867 23:14:43.348535 [DQSOSCAuto] RK0, (LSB)MR18= 0x93cc, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 391 ps
6868 23:14:43.351649 CH1 RK0: MR19=C0C, MR18=93CC
6869 23:14:43.358214 CH1_RK0: MR19=0xC0C, MR18=0x93CC, DQSOSC=384, MR23=63, INC=400, DEC=267
6870 23:14:43.358340 ==
6871 23:14:43.361823 Dram Type= 6, Freq= 0, CH_1, rank 1
6872 23:14:43.365310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6873 23:14:43.365422 ==
6874 23:14:43.368477 [Gating] SW mode calibration
6875 23:14:43.375249 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6876 23:14:43.381844 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6877 23:14:43.384895 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6878 23:14:43.388458 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6879 23:14:43.395242 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6880 23:14:43.398365 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6881 23:14:43.402046 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6882 23:14:43.405126 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6883 23:14:43.411925 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6884 23:14:43.414883 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6885 23:14:43.418515 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6886 23:14:43.421532 Total UI for P1: 0, mck2ui 16
6887 23:14:43.424988 best dqsien dly found for B0: ( 0, 14, 24)
6888 23:14:43.428237 Total UI for P1: 0, mck2ui 16
6889 23:14:43.431445 best dqsien dly found for B1: ( 0, 14, 24)
6890 23:14:43.434627 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6891 23:14:43.441229 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6892 23:14:43.441357
6893 23:14:43.444848 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6894 23:14:43.448059 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6895 23:14:43.451487 [Gating] SW calibration Done
6896 23:14:43.451603 ==
6897 23:14:43.454788 Dram Type= 6, Freq= 0, CH_1, rank 1
6898 23:14:43.458256 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6899 23:14:43.458339 ==
6900 23:14:43.458404 RX Vref Scan: 0
6901 23:14:43.461276
6902 23:14:43.461357 RX Vref 0 -> 0, step: 1
6903 23:14:43.461439
6904 23:14:43.464744 RX Delay -410 -> 252, step: 16
6905 23:14:43.468187 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6906 23:14:43.474735 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6907 23:14:43.478152 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6908 23:14:43.481125 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6909 23:14:43.484788 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6910 23:14:43.491242 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6911 23:14:43.494962 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6912 23:14:43.497987 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6913 23:14:43.501596 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6914 23:14:43.507819 iDelay=230, Bit 9, Center -27 (-266 ~ 213) 480
6915 23:14:43.511500 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6916 23:14:43.514601 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6917 23:14:43.518284 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6918 23:14:43.524770 iDelay=230, Bit 13, Center -11 (-250 ~ 229) 480
6919 23:14:43.527733 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6920 23:14:43.531388 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6921 23:14:43.531469 ==
6922 23:14:43.534434 Dram Type= 6, Freq= 0, CH_1, rank 1
6923 23:14:43.538176 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6924 23:14:43.541178 ==
6925 23:14:43.541259 DQS Delay:
6926 23:14:43.541322 DQS0 = 35, DQS1 = 35
6927 23:14:43.544236 DQM Delay:
6928 23:14:43.544356 DQM0 = 18, DQM1 = 15
6929 23:14:43.547849 DQ Delay:
6930 23:14:43.551437 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6931 23:14:43.551521 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6932 23:14:43.554557 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6933 23:14:43.558130 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =24
6934 23:14:43.558226
6935 23:14:43.561364
6936 23:14:43.561445 ==
6937 23:14:43.564562 Dram Type= 6, Freq= 0, CH_1, rank 1
6938 23:14:43.567578 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6939 23:14:43.567660 ==
6940 23:14:43.567723
6941 23:14:43.567782
6942 23:14:43.571010 TX Vref Scan disable
6943 23:14:43.571092 == TX Byte 0 ==
6944 23:14:43.574330 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6945 23:14:43.580983 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6946 23:14:43.581066 == TX Byte 1 ==
6947 23:14:43.584609 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6948 23:14:43.590865 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6949 23:14:43.590972 ==
6950 23:14:43.594264 Dram Type= 6, Freq= 0, CH_1, rank 1
6951 23:14:43.597451 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6952 23:14:43.597533 ==
6953 23:14:43.597596
6954 23:14:43.597655
6955 23:14:43.600562 TX Vref Scan disable
6956 23:14:43.600644 == TX Byte 0 ==
6957 23:14:43.604251 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6958 23:14:43.610576 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6959 23:14:43.610659 == TX Byte 1 ==
6960 23:14:43.614154 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6961 23:14:43.620890 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6962 23:14:43.620975
6963 23:14:43.621039 [DATLAT]
6964 23:14:43.621099 Freq=400, CH1 RK1
6965 23:14:43.621188
6966 23:14:43.623914 DATLAT Default: 0xe
6967 23:14:43.627599 0, 0xFFFF, sum = 0
6968 23:14:43.627682 1, 0xFFFF, sum = 0
6969 23:14:43.630580 2, 0xFFFF, sum = 0
6970 23:14:43.630662 3, 0xFFFF, sum = 0
6971 23:14:43.634188 4, 0xFFFF, sum = 0
6972 23:14:43.634271 5, 0xFFFF, sum = 0
6973 23:14:43.637132 6, 0xFFFF, sum = 0
6974 23:14:43.637215 7, 0xFFFF, sum = 0
6975 23:14:43.640878 8, 0xFFFF, sum = 0
6976 23:14:43.640960 9, 0xFFFF, sum = 0
6977 23:14:43.643947 10, 0xFFFF, sum = 0
6978 23:14:43.644029 11, 0xFFFF, sum = 0
6979 23:14:43.647573 12, 0xFFFF, sum = 0
6980 23:14:43.647655 13, 0x0, sum = 1
6981 23:14:43.650625 14, 0x0, sum = 2
6982 23:14:43.650707 15, 0x0, sum = 3
6983 23:14:43.654100 16, 0x0, sum = 4
6984 23:14:43.654245 best_step = 14
6985 23:14:43.654358
6986 23:14:43.654463 ==
6987 23:14:43.657063 Dram Type= 6, Freq= 0, CH_1, rank 1
6988 23:14:43.663914 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6989 23:14:43.664019 ==
6990 23:14:43.664111 RX Vref Scan: 0
6991 23:14:43.664198
6992 23:14:43.667101 RX Vref 0 -> 0, step: 1
6993 23:14:43.667196
6994 23:14:43.670489 RX Delay -311 -> 252, step: 8
6995 23:14:43.677055 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6996 23:14:43.680142 iDelay=217, Bit 1, Center -20 (-239 ~ 200) 440
6997 23:14:43.683788 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
6998 23:14:43.686759 iDelay=217, Bit 3, Center -20 (-239 ~ 200) 440
6999 23:14:43.693542 iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440
7000 23:14:43.697096 iDelay=217, Bit 5, Center -4 (-223 ~ 216) 440
7001 23:14:43.700230 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
7002 23:14:43.703740 iDelay=217, Bit 7, Center -16 (-239 ~ 208) 448
7003 23:14:43.707272 iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448
7004 23:14:43.713523 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
7005 23:14:43.716775 iDelay=217, Bit 10, Center -20 (-247 ~ 208) 456
7006 23:14:43.720099 iDelay=217, Bit 11, Center -24 (-247 ~ 200) 448
7007 23:14:43.726980 iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456
7008 23:14:43.730243 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
7009 23:14:43.733362 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
7010 23:14:43.736579 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
7011 23:14:43.736701 ==
7012 23:14:43.739912 Dram Type= 6, Freq= 0, CH_1, rank 1
7013 23:14:43.747116 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7014 23:14:43.747202 ==
7015 23:14:43.747266 DQS Delay:
7016 23:14:43.750155 DQS0 = 28, DQS1 = 32
7017 23:14:43.750236 DQM Delay:
7018 23:14:43.753348 DQM0 = 12, DQM1 = 11
7019 23:14:43.753454 DQ Delay:
7020 23:14:43.756872 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
7021 23:14:43.760049 DQ4 =8, DQ5 =24, DQ6 =20, DQ7 =12
7022 23:14:43.760147 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8
7023 23:14:43.763740 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =20
7024 23:14:43.766790
7025 23:14:43.766871
7026 23:14:43.773587 [DQSOSCAuto] RK1, (LSB)MR18= 0xc85b, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 385 ps
7027 23:14:43.776561 CH1 RK1: MR19=C0C, MR18=C85B
7028 23:14:43.783156 CH1_RK1: MR19=0xC0C, MR18=0xC85B, DQSOSC=385, MR23=63, INC=398, DEC=265
7029 23:14:43.786523 [RxdqsGatingPostProcess] freq 400
7030 23:14:43.789930 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7031 23:14:43.793061 best DQS0 dly(2T, 0.5T) = (0, 10)
7032 23:14:43.796226 best DQS1 dly(2T, 0.5T) = (0, 10)
7033 23:14:43.799610 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7034 23:14:43.803318 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7035 23:14:43.806464 best DQS0 dly(2T, 0.5T) = (0, 10)
7036 23:14:43.809497 best DQS1 dly(2T, 0.5T) = (0, 10)
7037 23:14:43.813194 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7038 23:14:43.816191 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7039 23:14:43.819725 Pre-setting of DQS Precalculation
7040 23:14:43.822937 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7041 23:14:43.832850 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7042 23:14:43.840024 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7043 23:14:43.840132
7044 23:14:43.840245
7045 23:14:43.842943 [Calibration Summary] 800 Mbps
7046 23:14:43.843068 CH 0, Rank 0
7047 23:14:43.846523 SW Impedance : PASS
7048 23:14:43.846643 DUTY Scan : NO K
7049 23:14:43.849603 ZQ Calibration : PASS
7050 23:14:43.852645 Jitter Meter : NO K
7051 23:14:43.852780 CBT Training : PASS
7052 23:14:43.856038 Write leveling : PASS
7053 23:14:43.859517 RX DQS gating : PASS
7054 23:14:43.859638 RX DQ/DQS(RDDQC) : PASS
7055 23:14:43.862879 TX DQ/DQS : PASS
7056 23:14:43.863001 RX DATLAT : PASS
7057 23:14:43.865979 RX DQ/DQS(Engine): PASS
7058 23:14:43.869371 TX OE : NO K
7059 23:14:43.869499 All Pass.
7060 23:14:43.869608
7061 23:14:43.869711 CH 0, Rank 1
7062 23:14:43.872988 SW Impedance : PASS
7063 23:14:43.876057 DUTY Scan : NO K
7064 23:14:43.876176 ZQ Calibration : PASS
7065 23:14:43.879520 Jitter Meter : NO K
7066 23:14:43.883170 CBT Training : PASS
7067 23:14:43.883291 Write leveling : NO K
7068 23:14:43.886296 RX DQS gating : PASS
7069 23:14:43.889319 RX DQ/DQS(RDDQC) : PASS
7070 23:14:43.889438 TX DQ/DQS : PASS
7071 23:14:43.892925 RX DATLAT : PASS
7072 23:14:43.895968 RX DQ/DQS(Engine): PASS
7073 23:14:43.896091 TX OE : NO K
7074 23:14:43.898995 All Pass.
7075 23:14:43.899114
7076 23:14:43.899226 CH 1, Rank 0
7077 23:14:43.902652 SW Impedance : PASS
7078 23:14:43.902771 DUTY Scan : NO K
7079 23:14:43.905583 ZQ Calibration : PASS
7080 23:14:43.909288 Jitter Meter : NO K
7081 23:14:43.909408 CBT Training : PASS
7082 23:14:43.912872 Write leveling : PASS
7083 23:14:43.915954 RX DQS gating : PASS
7084 23:14:43.916076 RX DQ/DQS(RDDQC) : PASS
7085 23:14:43.918992 TX DQ/DQS : PASS
7086 23:14:43.919113 RX DATLAT : PASS
7087 23:14:43.922508 RX DQ/DQS(Engine): PASS
7088 23:14:43.925497 TX OE : NO K
7089 23:14:43.925617 All Pass.
7090 23:14:43.925728
7091 23:14:43.925838 CH 1, Rank 1
7092 23:14:43.929162 SW Impedance : PASS
7093 23:14:43.932440 DUTY Scan : NO K
7094 23:14:43.932562 ZQ Calibration : PASS
7095 23:14:43.935531 Jitter Meter : NO K
7096 23:14:43.938595 CBT Training : PASS
7097 23:14:43.938717 Write leveling : NO K
7098 23:14:43.942182 RX DQS gating : PASS
7099 23:14:43.945613 RX DQ/DQS(RDDQC) : PASS
7100 23:14:43.945729 TX DQ/DQS : PASS
7101 23:14:43.948611 RX DATLAT : PASS
7102 23:14:43.952317 RX DQ/DQS(Engine): PASS
7103 23:14:43.952516 TX OE : NO K
7104 23:14:43.955249 All Pass.
7105 23:14:43.955368
7106 23:14:43.955478 DramC Write-DBI off
7107 23:14:43.959043 PER_BANK_REFRESH: Hybrid Mode
7108 23:14:43.962044 TX_TRACKING: ON
7109 23:14:43.968271 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7110 23:14:43.971655 [FAST_K] Save calibration result to emmc
7111 23:14:43.975518 dramc_set_vcore_voltage set vcore to 725000
7112 23:14:43.978610 Read voltage for 1600, 0
7113 23:14:43.978729 Vio18 = 0
7114 23:14:43.981690 Vcore = 725000
7115 23:14:43.981810 Vdram = 0
7116 23:14:43.981923 Vddq = 0
7117 23:14:43.984887 Vmddr = 0
7118 23:14:43.988256 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7119 23:14:43.994838 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7120 23:14:43.998221 MEM_TYPE=3, freq_sel=13
7121 23:14:43.998340 sv_algorithm_assistance_LP4_3733
7122 23:14:44.005078 ============ PULL DRAM RESETB DOWN ============
7123 23:14:44.008297 ========== PULL DRAM RESETB DOWN end =========
7124 23:14:44.011682 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7125 23:14:44.014667 ===================================
7126 23:14:44.018315 LPDDR4 DRAM CONFIGURATION
7127 23:14:44.021454 ===================================
7128 23:14:44.025104 EX_ROW_EN[0] = 0x0
7129 23:14:44.025223 EX_ROW_EN[1] = 0x0
7130 23:14:44.028218 LP4Y_EN = 0x0
7131 23:14:44.028359 WORK_FSP = 0x1
7132 23:14:44.031632 WL = 0x5
7133 23:14:44.031753 RL = 0x5
7134 23:14:44.034665 BL = 0x2
7135 23:14:44.034786 RPST = 0x0
7136 23:14:44.038348 RD_PRE = 0x0
7137 23:14:44.038466 WR_PRE = 0x1
7138 23:14:44.041142 WR_PST = 0x1
7139 23:14:44.041259 DBI_WR = 0x0
7140 23:14:44.044269 DBI_RD = 0x0
7141 23:14:44.044409 OTF = 0x1
7142 23:14:44.047887 ===================================
7143 23:14:44.051363 ===================================
7144 23:14:44.054928 ANA top config
7145 23:14:44.058130 ===================================
7146 23:14:44.061111 DLL_ASYNC_EN = 0
7147 23:14:44.061230 ALL_SLAVE_EN = 0
7148 23:14:44.064886 NEW_RANK_MODE = 1
7149 23:14:44.067859 DLL_IDLE_MODE = 1
7150 23:14:44.071446 LP45_APHY_COMB_EN = 1
7151 23:14:44.071549 TX_ODT_DIS = 0
7152 23:14:44.074714 NEW_8X_MODE = 1
7153 23:14:44.077737 ===================================
7154 23:14:44.081504 ===================================
7155 23:14:44.084485 data_rate = 3200
7156 23:14:44.088174 CKR = 1
7157 23:14:44.091066 DQ_P2S_RATIO = 8
7158 23:14:44.094355 ===================================
7159 23:14:44.097812 CA_P2S_RATIO = 8
7160 23:14:44.097889 DQ_CA_OPEN = 0
7161 23:14:44.101317 DQ_SEMI_OPEN = 0
7162 23:14:44.104629 CA_SEMI_OPEN = 0
7163 23:14:44.107637 CA_FULL_RATE = 0
7164 23:14:44.110998 DQ_CKDIV4_EN = 0
7165 23:14:44.114444 CA_CKDIV4_EN = 0
7166 23:14:44.114524 CA_PREDIV_EN = 0
7167 23:14:44.117914 PH8_DLY = 12
7168 23:14:44.121226 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7169 23:14:44.124167 DQ_AAMCK_DIV = 4
7170 23:14:44.127419 CA_AAMCK_DIV = 4
7171 23:14:44.130656 CA_ADMCK_DIV = 4
7172 23:14:44.130768 DQ_TRACK_CA_EN = 0
7173 23:14:44.134229 CA_PICK = 1600
7174 23:14:44.137627 CA_MCKIO = 1600
7175 23:14:44.140666 MCKIO_SEMI = 0
7176 23:14:44.144112 PLL_FREQ = 3068
7177 23:14:44.147800 DQ_UI_PI_RATIO = 32
7178 23:14:44.150886 CA_UI_PI_RATIO = 0
7179 23:14:44.153941 ===================================
7180 23:14:44.157418 ===================================
7181 23:14:44.157527 memory_type:LPDDR4
7182 23:14:44.160822 GP_NUM : 10
7183 23:14:44.164495 SRAM_EN : 1
7184 23:14:44.164604 MD32_EN : 0
7185 23:14:44.167641 ===================================
7186 23:14:44.171110 [ANA_INIT] >>>>>>>>>>>>>>
7187 23:14:44.174126 <<<<<< [CONFIGURE PHASE]: ANA_TX
7188 23:14:44.177966 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7189 23:14:44.180948 ===================================
7190 23:14:44.184601 data_rate = 3200,PCW = 0X7600
7191 23:14:44.187816 ===================================
7192 23:14:44.190890 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7193 23:14:44.194620 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7194 23:14:44.201188 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7195 23:14:44.204230 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7196 23:14:44.207261 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7197 23:14:44.210968 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7198 23:14:44.214053 [ANA_INIT] flow start
7199 23:14:44.217608 [ANA_INIT] PLL >>>>>>>>
7200 23:14:44.217715 [ANA_INIT] PLL <<<<<<<<
7201 23:14:44.220958 [ANA_INIT] MIDPI >>>>>>>>
7202 23:14:44.223829 [ANA_INIT] MIDPI <<<<<<<<
7203 23:14:44.223939 [ANA_INIT] DLL >>>>>>>>
7204 23:14:44.227388 [ANA_INIT] DLL <<<<<<<<
7205 23:14:44.230812 [ANA_INIT] flow end
7206 23:14:44.233803 ============ LP4 DIFF to SE enter ============
7207 23:14:44.237569 ============ LP4 DIFF to SE exit ============
7208 23:14:44.240742 [ANA_INIT] <<<<<<<<<<<<<
7209 23:14:44.243983 [Flow] Enable top DCM control >>>>>
7210 23:14:44.247221 [Flow] Enable top DCM control <<<<<
7211 23:14:44.250498 Enable DLL master slave shuffle
7212 23:14:44.257286 ==============================================================
7213 23:14:44.257399 Gating Mode config
7214 23:14:44.263904 ==============================================================
7215 23:14:44.264016 Config description:
7216 23:14:44.274013 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7217 23:14:44.280510 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7218 23:14:44.287288 SELPH_MODE 0: By rank 1: By Phase
7219 23:14:44.290332 ==============================================================
7220 23:14:44.294158 GAT_TRACK_EN = 1
7221 23:14:44.297081 RX_GATING_MODE = 2
7222 23:14:44.300711 RX_GATING_TRACK_MODE = 2
7223 23:14:44.303630 SELPH_MODE = 1
7224 23:14:44.307260 PICG_EARLY_EN = 1
7225 23:14:44.310511 VALID_LAT_VALUE = 1
7226 23:14:44.314150 ==============================================================
7227 23:14:44.317125 Enter into Gating configuration >>>>
7228 23:14:44.320880 Exit from Gating configuration <<<<
7229 23:14:44.323910 Enter into DVFS_PRE_config >>>>>
7230 23:14:44.337062 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7231 23:14:44.340735 Exit from DVFS_PRE_config <<<<<
7232 23:14:44.340846 Enter into PICG configuration >>>>
7233 23:14:44.343509 Exit from PICG configuration <<<<
7234 23:14:44.346946 [RX_INPUT] configuration >>>>>
7235 23:14:44.350639 [RX_INPUT] configuration <<<<<
7236 23:14:44.357203 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7237 23:14:44.360187 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7238 23:14:44.366907 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7239 23:14:44.373660 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7240 23:14:44.380306 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7241 23:14:44.386992 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7242 23:14:44.390391 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7243 23:14:44.393382 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7244 23:14:44.396600 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7245 23:14:44.403245 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7246 23:14:44.406643 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7247 23:14:44.410252 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7248 23:14:44.413373 ===================================
7249 23:14:44.416489 LPDDR4 DRAM CONFIGURATION
7250 23:14:44.420222 ===================================
7251 23:14:44.423199 EX_ROW_EN[0] = 0x0
7252 23:14:44.423310 EX_ROW_EN[1] = 0x0
7253 23:14:44.426832 LP4Y_EN = 0x0
7254 23:14:44.426974 WORK_FSP = 0x1
7255 23:14:44.429851 WL = 0x5
7256 23:14:44.429961 RL = 0x5
7257 23:14:44.433585 BL = 0x2
7258 23:14:44.433695 RPST = 0x0
7259 23:14:44.436331 RD_PRE = 0x0
7260 23:14:44.436442 WR_PRE = 0x1
7261 23:14:44.439839 WR_PST = 0x1
7262 23:14:44.439961 DBI_WR = 0x0
7263 23:14:44.442927 DBI_RD = 0x0
7264 23:14:44.443039 OTF = 0x1
7265 23:14:44.446561 ===================================
7266 23:14:44.452927 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7267 23:14:44.456732 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7268 23:14:44.459737 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7269 23:14:44.463322 ===================================
7270 23:14:44.466428 LPDDR4 DRAM CONFIGURATION
7271 23:14:44.470100 ===================================
7272 23:14:44.470214 EX_ROW_EN[0] = 0x10
7273 23:14:44.473058 EX_ROW_EN[1] = 0x0
7274 23:14:44.476730 LP4Y_EN = 0x0
7275 23:14:44.476847 WORK_FSP = 0x1
7276 23:14:44.479678 WL = 0x5
7277 23:14:44.479787 RL = 0x5
7278 23:14:44.483112 BL = 0x2
7279 23:14:44.483222 RPST = 0x0
7280 23:14:44.486323 RD_PRE = 0x0
7281 23:14:44.486429 WR_PRE = 0x1
7282 23:14:44.489865 WR_PST = 0x1
7283 23:14:44.489974 DBI_WR = 0x0
7284 23:14:44.493162 DBI_RD = 0x0
7285 23:14:44.493268 OTF = 0x1
7286 23:14:44.496058 ===================================
7287 23:14:44.503089 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7288 23:14:44.503198 ==
7289 23:14:44.506431 Dram Type= 6, Freq= 0, CH_0, rank 0
7290 23:14:44.509916 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7291 23:14:44.512970 ==
7292 23:14:44.513076 [Duty_Offset_Calibration]
7293 23:14:44.516097 B0:2 B1:1 CA:1
7294 23:14:44.516202
7295 23:14:44.519242 [DutyScan_Calibration_Flow] k_type=0
7296 23:14:44.528212
7297 23:14:44.528358 ==CLK 0==
7298 23:14:44.531769 Final CLK duty delay cell = 0
7299 23:14:44.534879 [0] MAX Duty = 5156%(X100), DQS PI = 22
7300 23:14:44.538104 [0] MIN Duty = 4875%(X100), DQS PI = 62
7301 23:14:44.541503 [0] AVG Duty = 5015%(X100)
7302 23:14:44.541610
7303 23:14:44.545062 CH0 CLK Duty spec in!! Max-Min= 281%
7304 23:14:44.548180 [DutyScan_Calibration_Flow] ====Done====
7305 23:14:44.548293
7306 23:14:44.551418 [DutyScan_Calibration_Flow] k_type=1
7307 23:14:44.567600
7308 23:14:44.567714 ==DQS 0 ==
7309 23:14:44.570737 Final DQS duty delay cell = -4
7310 23:14:44.573900 [-4] MAX Duty = 5125%(X100), DQS PI = 24
7311 23:14:44.577618 [-4] MIN Duty = 4657%(X100), DQS PI = 0
7312 23:14:44.580626 [-4] AVG Duty = 4891%(X100)
7313 23:14:44.580732
7314 23:14:44.580827 ==DQS 1 ==
7315 23:14:44.584383 Final DQS duty delay cell = 0
7316 23:14:44.587312 [0] MAX Duty = 5218%(X100), DQS PI = 22
7317 23:14:44.590652 [0] MIN Duty = 5062%(X100), DQS PI = 50
7318 23:14:44.594193 [0] AVG Duty = 5140%(X100)
7319 23:14:44.594299
7320 23:14:44.597795 CH0 DQS 0 Duty spec in!! Max-Min= 468%
7321 23:14:44.597902
7322 23:14:44.600714 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7323 23:14:44.604179 [DutyScan_Calibration_Flow] ====Done====
7324 23:14:44.604311
7325 23:14:44.607152 [DutyScan_Calibration_Flow] k_type=3
7326 23:14:44.624094
7327 23:14:44.624207 ==DQM 0 ==
7328 23:14:44.627852 Final DQM duty delay cell = 0
7329 23:14:44.630639 [0] MAX Duty = 5187%(X100), DQS PI = 32
7330 23:14:44.634225 [0] MIN Duty = 4907%(X100), DQS PI = 58
7331 23:14:44.637250 [0] AVG Duty = 5047%(X100)
7332 23:14:44.637356
7333 23:14:44.637450 ==DQM 1 ==
7334 23:14:44.640951 Final DQM duty delay cell = -4
7335 23:14:44.644005 [-4] MAX Duty = 4969%(X100), DQS PI = 22
7336 23:14:44.647428 [-4] MIN Duty = 4813%(X100), DQS PI = 14
7337 23:14:44.650821 [-4] AVG Duty = 4891%(X100)
7338 23:14:44.650929
7339 23:14:44.654018 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7340 23:14:44.654124
7341 23:14:44.657147 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7342 23:14:44.660720 [DutyScan_Calibration_Flow] ====Done====
7343 23:14:44.660826
7344 23:14:44.664108 [DutyScan_Calibration_Flow] k_type=2
7345 23:14:44.681793
7346 23:14:44.681907 ==DQ 0 ==
7347 23:14:44.685070 Final DQ duty delay cell = 0
7348 23:14:44.688628 [0] MAX Duty = 5062%(X100), DQS PI = 24
7349 23:14:44.691766 [0] MIN Duty = 4907%(X100), DQS PI = 0
7350 23:14:44.691873 [0] AVG Duty = 4984%(X100)
7351 23:14:44.691971
7352 23:14:44.695390 ==DQ 1 ==
7353 23:14:44.698172 Final DQ duty delay cell = 0
7354 23:14:44.701764 [0] MAX Duty = 5125%(X100), DQS PI = 6
7355 23:14:44.704767 [0] MIN Duty = 4938%(X100), DQS PI = 34
7356 23:14:44.704876 [0] AVG Duty = 5031%(X100)
7357 23:14:44.704972
7358 23:14:44.708332 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7359 23:14:44.708438
7360 23:14:44.711787 CH0 DQ 1 Duty spec in!! Max-Min= 187%
7361 23:14:44.718249 [DutyScan_Calibration_Flow] ====Done====
7362 23:14:44.718362 ==
7363 23:14:44.721987 Dram Type= 6, Freq= 0, CH_1, rank 0
7364 23:14:44.724972 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7365 23:14:44.725082 ==
7366 23:14:44.728440 [Duty_Offset_Calibration]
7367 23:14:44.728547 B0:1 B1:0 CA:0
7368 23:14:44.728639
7369 23:14:44.731505 [DutyScan_Calibration_Flow] k_type=0
7370 23:14:44.741243
7371 23:14:44.741350 ==CLK 0==
7372 23:14:44.744155 Final CLK duty delay cell = -4
7373 23:14:44.747913 [-4] MAX Duty = 5000%(X100), DQS PI = 24
7374 23:14:44.750931 [-4] MIN Duty = 4844%(X100), DQS PI = 4
7375 23:14:44.754587 [-4] AVG Duty = 4922%(X100)
7376 23:14:44.754693
7377 23:14:44.757795 CH1 CLK Duty spec in!! Max-Min= 156%
7378 23:14:44.761048 [DutyScan_Calibration_Flow] ====Done====
7379 23:14:44.761153
7380 23:14:44.764606 [DutyScan_Calibration_Flow] k_type=1
7381 23:14:44.780853
7382 23:14:44.780972 ==DQS 0 ==
7383 23:14:44.784178 Final DQS duty delay cell = 0
7384 23:14:44.787696 [0] MAX Duty = 5094%(X100), DQS PI = 16
7385 23:14:44.791232 [0] MIN Duty = 4844%(X100), DQS PI = 48
7386 23:14:44.794240 [0] AVG Duty = 4969%(X100)
7387 23:14:44.794348
7388 23:14:44.794443 ==DQS 1 ==
7389 23:14:44.797941 Final DQS duty delay cell = 0
7390 23:14:44.801052 [0] MAX Duty = 5249%(X100), DQS PI = 16
7391 23:14:44.804559 [0] MIN Duty = 4938%(X100), DQS PI = 8
7392 23:14:44.804666 [0] AVG Duty = 5093%(X100)
7393 23:14:44.807493
7394 23:14:44.810991 CH1 DQS 0 Duty spec in!! Max-Min= 250%
7395 23:14:44.811112
7396 23:14:44.814041 CH1 DQS 1 Duty spec in!! Max-Min= 311%
7397 23:14:44.817793 [DutyScan_Calibration_Flow] ====Done====
7398 23:14:44.817900
7399 23:14:44.820670 [DutyScan_Calibration_Flow] k_type=3
7400 23:14:44.838201
7401 23:14:44.838317 ==DQM 0 ==
7402 23:14:44.841265 Final DQM duty delay cell = 0
7403 23:14:44.844922 [0] MAX Duty = 5187%(X100), DQS PI = 8
7404 23:14:44.847745 [0] MIN Duty = 4969%(X100), DQS PI = 48
7405 23:14:44.847852 [0] AVG Duty = 5078%(X100)
7406 23:14:44.851425
7407 23:14:44.851531 ==DQM 1 ==
7408 23:14:44.854576 Final DQM duty delay cell = 0
7409 23:14:44.857726 [0] MAX Duty = 5093%(X100), DQS PI = 16
7410 23:14:44.861526 [0] MIN Duty = 4907%(X100), DQS PI = 32
7411 23:14:44.864587 [0] AVG Duty = 5000%(X100)
7412 23:14:44.864695
7413 23:14:44.867609 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7414 23:14:44.867720
7415 23:14:44.871166 CH1 DQM 1 Duty spec in!! Max-Min= 186%
7416 23:14:44.874703 [DutyScan_Calibration_Flow] ====Done====
7417 23:14:44.874812
7418 23:14:44.877724 [DutyScan_Calibration_Flow] k_type=2
7419 23:14:44.894023
7420 23:14:44.894137 ==DQ 0 ==
7421 23:14:44.897222 Final DQ duty delay cell = -4
7422 23:14:44.900628 [-4] MAX Duty = 5031%(X100), DQS PI = 10
7423 23:14:44.903681 [-4] MIN Duty = 4875%(X100), DQS PI = 46
7424 23:14:44.907363 [-4] AVG Duty = 4953%(X100)
7425 23:14:44.907486
7426 23:14:44.907578 ==DQ 1 ==
7427 23:14:44.910738 Final DQ duty delay cell = 0
7428 23:14:44.913593 [0] MAX Duty = 5124%(X100), DQS PI = 18
7429 23:14:44.916952 [0] MIN Duty = 4938%(X100), DQS PI = 10
7430 23:14:44.920634 [0] AVG Duty = 5031%(X100)
7431 23:14:44.920744
7432 23:14:44.923721 CH1 DQ 0 Duty spec in!! Max-Min= 156%
7433 23:14:44.923830
7434 23:14:44.927326 CH1 DQ 1 Duty spec in!! Max-Min= 186%
7435 23:14:44.930605 [DutyScan_Calibration_Flow] ====Done====
7436 23:14:44.933573 nWR fixed to 30
7437 23:14:44.936864 [ModeRegInit_LP4] CH0 RK0
7438 23:14:44.936971 [ModeRegInit_LP4] CH0 RK1
7439 23:14:44.940192 [ModeRegInit_LP4] CH1 RK0
7440 23:14:44.943941 [ModeRegInit_LP4] CH1 RK1
7441 23:14:44.944046 match AC timing 5
7442 23:14:44.950176 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7443 23:14:44.953736 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7444 23:14:44.956766 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7445 23:14:44.963411 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7446 23:14:44.966483 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7447 23:14:44.966591 [MiockJmeterHQA]
7448 23:14:44.966689
7449 23:14:44.970181 [DramcMiockJmeter] u1RxGatingPI = 0
7450 23:14:44.973215 0 : 4365, 4138
7451 23:14:44.973325 4 : 4252, 4027
7452 23:14:44.976537 8 : 4363, 4138
7453 23:14:44.976649 12 : 4257, 4029
7454 23:14:44.980162 16 : 4252, 4027
7455 23:14:44.980274 20 : 4252, 4027
7456 23:14:44.980406 24 : 4252, 4027
7457 23:14:44.983260 28 : 4253, 4027
7458 23:14:44.983368 32 : 4252, 4027
7459 23:14:44.986303 36 : 4258, 4029
7460 23:14:44.986411 40 : 4252, 4026
7461 23:14:44.989989 44 : 4252, 4027
7462 23:14:44.990095 48 : 4254, 4029
7463 23:14:44.993091 52 : 4252, 4027
7464 23:14:44.993202 56 : 4252, 4027
7465 23:14:44.993297 60 : 4365, 4139
7466 23:14:44.996772 64 : 4253, 4026
7467 23:14:44.996880 68 : 4255, 4030
7468 23:14:44.999602 72 : 4252, 4027
7469 23:14:44.999709 76 : 4363, 4138
7470 23:14:45.003062 80 : 4249, 4027
7471 23:14:45.003170 84 : 4252, 4027
7472 23:14:45.003270 88 : 4252, 49
7473 23:14:45.006431 92 : 4363, 0
7474 23:14:45.006540 96 : 4252, 0
7475 23:14:45.009791 100 : 4363, 0
7476 23:14:45.009899 104 : 4250, 0
7477 23:14:45.009992 108 : 4253, 0
7478 23:14:45.013307 112 : 4250, 0
7479 23:14:45.013415 116 : 4250, 0
7480 23:14:45.016264 120 : 4360, 0
7481 23:14:45.016404 124 : 4250, 0
7482 23:14:45.016524 128 : 4250, 0
7483 23:14:45.019554 132 : 4250, 0
7484 23:14:45.019663 136 : 4250, 0
7485 23:14:45.019757 140 : 4250, 0
7486 23:14:45.023144 144 : 4250, 0
7487 23:14:45.023252 148 : 4363, 0
7488 23:14:45.026551 152 : 4250, 0
7489 23:14:45.026662 156 : 4360, 0
7490 23:14:45.026756 160 : 4257, 0
7491 23:14:45.029697 164 : 4250, 0
7492 23:14:45.029810 168 : 4250, 0
7493 23:14:45.032932 172 : 4254, 0
7494 23:14:45.033040 176 : 4250, 0
7495 23:14:45.033136 180 : 4250, 0
7496 23:14:45.036270 184 : 4253, 0
7497 23:14:45.036400 188 : 4250, 0
7498 23:14:45.039928 192 : 4250, 0
7499 23:14:45.040041 196 : 4250, 0
7500 23:14:45.040136 200 : 4360, 0
7501 23:14:45.042846 204 : 4250, 1365
7502 23:14:45.042951 208 : 4250, 4018
7503 23:14:45.046620 212 : 4252, 4029
7504 23:14:45.046729 216 : 4360, 4137
7505 23:14:45.049992 220 : 4361, 4137
7506 23:14:45.050100 224 : 4250, 4027
7507 23:14:45.052975 228 : 4250, 4027
7508 23:14:45.053086 232 : 4252, 4029
7509 23:14:45.053180 236 : 4249, 4027
7510 23:14:45.056196 240 : 4250, 4027
7511 23:14:45.056340 244 : 4360, 4138
7512 23:14:45.059818 248 : 4250, 4027
7513 23:14:45.059926 252 : 4250, 4027
7514 23:14:45.062917 256 : 4250, 4027
7515 23:14:45.063029 260 : 4250, 4027
7516 23:14:45.066608 264 : 4363, 4138
7517 23:14:45.066715 268 : 4249, 4027
7518 23:14:45.069678 272 : 4363, 4137
7519 23:14:45.069785 276 : 4250, 4027
7520 23:14:45.072758 280 : 4250, 4027
7521 23:14:45.072865 284 : 4250, 4027
7522 23:14:45.076385 288 : 4250, 4027
7523 23:14:45.076494 292 : 4250, 4027
7524 23:14:45.076596 296 : 4360, 4138
7525 23:14:45.079525 300 : 4250, 4027
7526 23:14:45.079632 304 : 4250, 4027
7527 23:14:45.083050 308 : 4250, 3927
7528 23:14:45.083158 312 : 4250, 2054
7529 23:14:45.083252
7530 23:14:45.086555 MIOCK jitter meter ch=0
7531 23:14:45.086661
7532 23:14:45.089585 1T = (312-88) = 224 dly cells
7533 23:14:45.096365 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7534 23:14:45.096474 ==
7535 23:14:45.099414 Dram Type= 6, Freq= 0, CH_0, rank 0
7536 23:14:45.103131 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7537 23:14:45.103241 ==
7538 23:14:45.109743 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7539 23:14:45.113012 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7540 23:14:45.116251 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7541 23:14:45.122626 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7542 23:14:45.131615 [CA 0] Center 42 (12~73) winsize 62
7543 23:14:45.135203 [CA 1] Center 42 (12~73) winsize 62
7544 23:14:45.138452 [CA 2] Center 38 (8~68) winsize 61
7545 23:14:45.141795 [CA 3] Center 37 (8~67) winsize 60
7546 23:14:45.144655 [CA 4] Center 36 (6~66) winsize 61
7547 23:14:45.148231 [CA 5] Center 35 (6~64) winsize 59
7548 23:14:45.148380
7549 23:14:45.151496 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7550 23:14:45.151601
7551 23:14:45.154997 [CATrainingPosCal] consider 1 rank data
7552 23:14:45.158224 u2DelayCellTimex100 = 290/100 ps
7553 23:14:45.161400 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7554 23:14:45.167870 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7555 23:14:45.171314 CA2 delay=38 (8~68),Diff = 3 PI (10 cell)
7556 23:14:45.174555 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7557 23:14:45.177800 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7558 23:14:45.181657 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7559 23:14:45.181763
7560 23:14:45.184722 CA PerBit enable=1, Macro0, CA PI delay=35
7561 23:14:45.184826
7562 23:14:45.187839 [CBTSetCACLKResult] CA Dly = 35
7563 23:14:45.191271 CS Dly: 8 (0~39)
7564 23:14:45.195078 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7565 23:14:45.198150 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7566 23:14:45.198259 ==
7567 23:14:45.201264 Dram Type= 6, Freq= 0, CH_0, rank 1
7568 23:14:45.204463 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7569 23:14:45.208084 ==
7570 23:14:45.211246 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7571 23:14:45.215006 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7572 23:14:45.221743 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7573 23:14:45.224481 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7574 23:14:45.234739 [CA 0] Center 42 (12~72) winsize 61
7575 23:14:45.238518 [CA 1] Center 42 (12~73) winsize 62
7576 23:14:45.241561 [CA 2] Center 37 (8~67) winsize 60
7577 23:14:45.244642 [CA 3] Center 37 (7~68) winsize 62
7578 23:14:45.248102 [CA 4] Center 35 (5~65) winsize 61
7579 23:14:45.251582 [CA 5] Center 35 (5~65) winsize 61
7580 23:14:45.251669
7581 23:14:45.255013 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7582 23:14:45.255096
7583 23:14:45.258476 [CATrainingPosCal] consider 2 rank data
7584 23:14:45.261411 u2DelayCellTimex100 = 290/100 ps
7585 23:14:45.265088 CA0 delay=42 (12~72),Diff = 7 PI (23 cell)
7586 23:14:45.271710 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7587 23:14:45.275013 CA2 delay=37 (8~67),Diff = 2 PI (6 cell)
7588 23:14:45.277961 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7589 23:14:45.281834 CA4 delay=35 (6~65),Diff = 0 PI (0 cell)
7590 23:14:45.284762 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7591 23:14:45.284845
7592 23:14:45.287854 CA PerBit enable=1, Macro0, CA PI delay=35
7593 23:14:45.287936
7594 23:14:45.291563 [CBTSetCACLKResult] CA Dly = 35
7595 23:14:45.294810 CS Dly: 9 (0~41)
7596 23:14:45.298162 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7597 23:14:45.301286 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7598 23:14:45.301393
7599 23:14:45.304710 ----->DramcWriteLeveling(PI) begin...
7600 23:14:45.304818 ==
7601 23:14:45.308244 Dram Type= 6, Freq= 0, CH_0, rank 0
7602 23:14:45.311247 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7603 23:14:45.314467 ==
7604 23:14:45.314572 Write leveling (Byte 0): 35 => 35
7605 23:14:45.318147 Write leveling (Byte 1): 27 => 27
7606 23:14:45.321235 DramcWriteLeveling(PI) end<-----
7607 23:14:45.321342
7608 23:14:45.321440 ==
7609 23:14:45.324306 Dram Type= 6, Freq= 0, CH_0, rank 0
7610 23:14:45.331112 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7611 23:14:45.331219 ==
7612 23:14:45.331314 [Gating] SW mode calibration
7613 23:14:45.340899 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7614 23:14:45.344688 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7615 23:14:45.351462 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7616 23:14:45.354243 1 4 4 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
7617 23:14:45.357985 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7618 23:14:45.360964 1 4 12 | B1->B0 | 2323 3635 | 0 1 | (0 0) (1 1)
7619 23:14:45.367679 1 4 16 | B1->B0 | 2323 3636 | 0 1 | (0 0) (0 0)
7620 23:14:45.371308 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7621 23:14:45.374483 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7622 23:14:45.381213 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7623 23:14:45.384218 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7624 23:14:45.387330 1 5 4 | B1->B0 | 3434 3636 | 1 1 | (1 1) (1 1)
7625 23:14:45.394490 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 0)
7626 23:14:45.397492 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
7627 23:14:45.400563 1 5 16 | B1->B0 | 3333 2525 | 1 0 | (1 1) (1 0)
7628 23:14:45.407810 1 5 20 | B1->B0 | 2727 2525 | 0 0 | (1 0) (0 0)
7629 23:14:45.410841 1 5 24 | B1->B0 | 2323 2524 | 0 1 | (0 0) (0 0)
7630 23:14:45.413974 1 5 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7631 23:14:45.420546 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7632 23:14:45.423823 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7633 23:14:45.427435 1 6 8 | B1->B0 | 2323 3131 | 0 1 | (0 0) (0 0)
7634 23:14:45.433683 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7635 23:14:45.437326 1 6 16 | B1->B0 | 2828 4646 | 0 0 | (0 0) (0 0)
7636 23:14:45.440423 1 6 20 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
7637 23:14:45.447532 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7638 23:14:45.450459 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7639 23:14:45.453934 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7640 23:14:45.460522 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7641 23:14:45.464327 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7642 23:14:45.467214 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7643 23:14:45.473887 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7644 23:14:45.477184 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7645 23:14:45.480786 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7646 23:14:45.487445 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7647 23:14:45.490424 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7648 23:14:45.494097 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7649 23:14:45.500631 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7650 23:14:45.503681 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7651 23:14:45.507507 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7652 23:14:45.511031 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7653 23:14:45.517607 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7654 23:14:45.520428 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7655 23:14:45.524212 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7656 23:14:45.530505 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7657 23:14:45.534362 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7658 23:14:45.537341 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7659 23:14:45.543847 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7660 23:14:45.544070 Total UI for P1: 0, mck2ui 16
7661 23:14:45.551089 best dqsien dly found for B0: ( 1, 9, 8)
7662 23:14:45.554128 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7663 23:14:45.557186 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7664 23:14:45.560799 Total UI for P1: 0, mck2ui 16
7665 23:14:45.564096 best dqsien dly found for B1: ( 1, 9, 18)
7666 23:14:45.567190 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
7667 23:14:45.570491 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7668 23:14:45.570611
7669 23:14:45.573840 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
7670 23:14:45.580295 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7671 23:14:45.580434 [Gating] SW calibration Done
7672 23:14:45.583631 ==
7673 23:14:45.583750 Dram Type= 6, Freq= 0, CH_0, rank 0
7674 23:14:45.590672 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7675 23:14:45.590796 ==
7676 23:14:45.590909 RX Vref Scan: 0
7677 23:14:45.591018
7678 23:14:45.593554 RX Vref 0 -> 0, step: 1
7679 23:14:45.593673
7680 23:14:45.597168 RX Delay 0 -> 252, step: 8
7681 23:14:45.600205 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
7682 23:14:45.603689 iDelay=200, Bit 1, Center 143 (88 ~ 199) 112
7683 23:14:45.607214 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
7684 23:14:45.614027 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7685 23:14:45.617143 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7686 23:14:45.620498 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7687 23:14:45.624066 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
7688 23:14:45.627134 iDelay=200, Bit 7, Center 143 (96 ~ 191) 96
7689 23:14:45.630211 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
7690 23:14:45.637503 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
7691 23:14:45.640531 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
7692 23:14:45.643629 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7693 23:14:45.647043 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
7694 23:14:45.650470 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7695 23:14:45.657225 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7696 23:14:45.660650 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7697 23:14:45.660771 ==
7698 23:14:45.663432 Dram Type= 6, Freq= 0, CH_0, rank 0
7699 23:14:45.666954 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7700 23:14:45.667074 ==
7701 23:14:45.670765 DQS Delay:
7702 23:14:45.670887 DQS0 = 0, DQS1 = 0
7703 23:14:45.670999 DQM Delay:
7704 23:14:45.673571 DQM0 = 136, DQM1 = 129
7705 23:14:45.673689 DQ Delay:
7706 23:14:45.677107 DQ0 =135, DQ1 =143, DQ2 =135, DQ3 =131
7707 23:14:45.680296 DQ4 =139, DQ5 =123, DQ6 =143, DQ7 =143
7708 23:14:45.686944 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
7709 23:14:45.690500 DQ12 =135, DQ13 =135, DQ14 =139, DQ15 =135
7710 23:14:45.690624
7711 23:14:45.690736
7712 23:14:45.690845 ==
7713 23:14:45.693526 Dram Type= 6, Freq= 0, CH_0, rank 0
7714 23:14:45.696876 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7715 23:14:45.696982 ==
7716 23:14:45.697089
7717 23:14:45.697176
7718 23:14:45.699900 TX Vref Scan disable
7719 23:14:45.703596 == TX Byte 0 ==
7720 23:14:45.706777 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7721 23:14:45.710357 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7722 23:14:45.713409 == TX Byte 1 ==
7723 23:14:45.717128 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7724 23:14:45.719989 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7725 23:14:45.720070 ==
7726 23:14:45.723684 Dram Type= 6, Freq= 0, CH_0, rank 0
7727 23:14:45.727108 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7728 23:14:45.730119 ==
7729 23:14:45.740486
7730 23:14:45.744205 TX Vref early break, caculate TX vref
7731 23:14:45.747350 TX Vref=16, minBit 0, minWin=22, winSum=377
7732 23:14:45.750455 TX Vref=18, minBit 7, minWin=22, winSum=385
7733 23:14:45.754120 TX Vref=20, minBit 0, minWin=24, winSum=400
7734 23:14:45.757184 TX Vref=22, minBit 0, minWin=24, winSum=411
7735 23:14:45.760232 TX Vref=24, minBit 0, minWin=25, winSum=417
7736 23:14:45.767099 TX Vref=26, minBit 1, minWin=26, winSum=428
7737 23:14:45.770480 TX Vref=28, minBit 6, minWin=25, winSum=426
7738 23:14:45.773563 TX Vref=30, minBit 1, minWin=24, winSum=415
7739 23:14:45.777444 TX Vref=32, minBit 6, minWin=23, winSum=400
7740 23:14:45.783909 [TxChooseVref] Worse bit 1, Min win 26, Win sum 428, Final Vref 26
7741 23:14:45.783995
7742 23:14:45.786896 Final TX Range 0 Vref 26
7743 23:14:45.786978
7744 23:14:45.787041 ==
7745 23:14:45.790439 Dram Type= 6, Freq= 0, CH_0, rank 0
7746 23:14:45.793791 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7747 23:14:45.793872 ==
7748 23:14:45.793936
7749 23:14:45.793994
7750 23:14:45.797404 TX Vref Scan disable
7751 23:14:45.800214 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7752 23:14:45.803632 == TX Byte 0 ==
7753 23:14:45.807410 u2DelayCellOfst[0]=10 cells (3 PI)
7754 23:14:45.810676 u2DelayCellOfst[1]=13 cells (4 PI)
7755 23:14:45.813797 u2DelayCellOfst[2]=10 cells (3 PI)
7756 23:14:45.817084 u2DelayCellOfst[3]=10 cells (3 PI)
7757 23:14:45.820261 u2DelayCellOfst[4]=6 cells (2 PI)
7758 23:14:45.820402 u2DelayCellOfst[5]=0 cells (0 PI)
7759 23:14:45.823800 u2DelayCellOfst[6]=13 cells (4 PI)
7760 23:14:45.827335 u2DelayCellOfst[7]=16 cells (5 PI)
7761 23:14:45.833546 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7762 23:14:45.837166 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7763 23:14:45.837286 == TX Byte 1 ==
7764 23:14:45.840180 u2DelayCellOfst[8]=0 cells (0 PI)
7765 23:14:45.843282 u2DelayCellOfst[9]=0 cells (0 PI)
7766 23:14:45.846638 u2DelayCellOfst[10]=6 cells (2 PI)
7767 23:14:45.850055 u2DelayCellOfst[11]=3 cells (1 PI)
7768 23:14:45.853867 u2DelayCellOfst[12]=13 cells (4 PI)
7769 23:14:45.856960 u2DelayCellOfst[13]=10 cells (3 PI)
7770 23:14:45.860033 u2DelayCellOfst[14]=13 cells (4 PI)
7771 23:14:45.863730 u2DelayCellOfst[15]=10 cells (3 PI)
7772 23:14:45.866879 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7773 23:14:45.870532 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7774 23:14:45.873583 DramC Write-DBI on
7775 23:14:45.873692 ==
7776 23:14:45.876691 Dram Type= 6, Freq= 0, CH_0, rank 0
7777 23:14:45.880276 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7778 23:14:45.880425 ==
7779 23:14:45.880520
7780 23:14:45.880616
7781 23:14:45.884107 TX Vref Scan disable
7782 23:14:45.887014 == TX Byte 0 ==
7783 23:14:45.890088 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7784 23:14:45.893384 == TX Byte 1 ==
7785 23:14:45.896509 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
7786 23:14:45.896617 DramC Write-DBI off
7787 23:14:45.896717
7788 23:14:45.899903 [DATLAT]
7789 23:14:45.900008 Freq=1600, CH0 RK0
7790 23:14:45.900105
7791 23:14:45.903201 DATLAT Default: 0xf
7792 23:14:45.903309 0, 0xFFFF, sum = 0
7793 23:14:45.906386 1, 0xFFFF, sum = 0
7794 23:14:45.906511 2, 0xFFFF, sum = 0
7795 23:14:45.909658 3, 0xFFFF, sum = 0
7796 23:14:45.909768 4, 0xFFFF, sum = 0
7797 23:14:45.913078 5, 0xFFFF, sum = 0
7798 23:14:45.913185 6, 0xFFFF, sum = 0
7799 23:14:45.916695 7, 0xFFFF, sum = 0
7800 23:14:45.916808 8, 0xFFFF, sum = 0
7801 23:14:45.919764 9, 0xFFFF, sum = 0
7802 23:14:45.923380 10, 0xFFFF, sum = 0
7803 23:14:45.923494 11, 0xFFFF, sum = 0
7804 23:14:45.926375 12, 0xFFFF, sum = 0
7805 23:14:45.926486 13, 0xFFFF, sum = 0
7806 23:14:45.929940 14, 0x0, sum = 1
7807 23:14:45.930049 15, 0x0, sum = 2
7808 23:14:45.933256 16, 0x0, sum = 3
7809 23:14:45.933364 17, 0x0, sum = 4
7810 23:14:45.933459 best_step = 15
7811 23:14:45.936248
7812 23:14:45.936398 ==
7813 23:14:45.939686 Dram Type= 6, Freq= 0, CH_0, rank 0
7814 23:14:45.942841 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7815 23:14:45.942952 ==
7816 23:14:45.943052 RX Vref Scan: 1
7817 23:14:45.943145
7818 23:14:45.946263 Set Vref Range= 24 -> 127
7819 23:14:45.946388
7820 23:14:45.949674 RX Vref 24 -> 127, step: 1
7821 23:14:45.949783
7822 23:14:45.952990 RX Delay 19 -> 252, step: 4
7823 23:14:45.953101
7824 23:14:45.956697 Set Vref, RX VrefLevel [Byte0]: 24
7825 23:14:45.959825 [Byte1]: 24
7826 23:14:45.959946
7827 23:14:45.962776 Set Vref, RX VrefLevel [Byte0]: 25
7828 23:14:45.966457 [Byte1]: 25
7829 23:14:45.966566
7830 23:14:45.970173 Set Vref, RX VrefLevel [Byte0]: 26
7831 23:14:45.973171 [Byte1]: 26
7832 23:14:45.976802
7833 23:14:45.976911 Set Vref, RX VrefLevel [Byte0]: 27
7834 23:14:45.979846 [Byte1]: 27
7835 23:14:45.983761
7836 23:14:45.983867 Set Vref, RX VrefLevel [Byte0]: 28
7837 23:14:45.987424 [Byte1]: 28
7838 23:14:45.991933
7839 23:14:45.992040 Set Vref, RX VrefLevel [Byte0]: 29
7840 23:14:45.995019 [Byte1]: 29
7841 23:14:45.999257
7842 23:14:45.999364 Set Vref, RX VrefLevel [Byte0]: 30
7843 23:14:46.002300 [Byte1]: 30
7844 23:14:46.006788
7845 23:14:46.006918 Set Vref, RX VrefLevel [Byte0]: 31
7846 23:14:46.010215 [Byte1]: 31
7847 23:14:46.014080
7848 23:14:46.014188 Set Vref, RX VrefLevel [Byte0]: 32
7849 23:14:46.017797 [Byte1]: 32
7850 23:14:46.021732
7851 23:14:46.021841 Set Vref, RX VrefLevel [Byte0]: 33
7852 23:14:46.025248 [Byte1]: 33
7853 23:14:46.029636
7854 23:14:46.029745 Set Vref, RX VrefLevel [Byte0]: 34
7855 23:14:46.032893 [Byte1]: 34
7856 23:14:46.036908
7857 23:14:46.037014 Set Vref, RX VrefLevel [Byte0]: 35
7858 23:14:46.040185 [Byte1]: 35
7859 23:14:46.044460
7860 23:14:46.044571 Set Vref, RX VrefLevel [Byte0]: 36
7861 23:14:46.047929 [Byte1]: 36
7862 23:14:46.052020
7863 23:14:46.052131 Set Vref, RX VrefLevel [Byte0]: 37
7864 23:14:46.055293 [Byte1]: 37
7865 23:14:46.059648
7866 23:14:46.059755 Set Vref, RX VrefLevel [Byte0]: 38
7867 23:14:46.063076 [Byte1]: 38
7868 23:14:46.067333
7869 23:14:46.067442 Set Vref, RX VrefLevel [Byte0]: 39
7870 23:14:46.070833 [Byte1]: 39
7871 23:14:46.075058
7872 23:14:46.075170 Set Vref, RX VrefLevel [Byte0]: 40
7873 23:14:46.078228 [Byte1]: 40
7874 23:14:46.082525
7875 23:14:46.082646 Set Vref, RX VrefLevel [Byte0]: 41
7876 23:14:46.085574 [Byte1]: 41
7877 23:14:46.089859
7878 23:14:46.089980 Set Vref, RX VrefLevel [Byte0]: 42
7879 23:14:46.093548 [Byte1]: 42
7880 23:14:46.097756
7881 23:14:46.097877 Set Vref, RX VrefLevel [Byte0]: 43
7882 23:14:46.100931 [Byte1]: 43
7883 23:14:46.105402
7884 23:14:46.105511 Set Vref, RX VrefLevel [Byte0]: 44
7885 23:14:46.108264 [Byte1]: 44
7886 23:14:46.112669
7887 23:14:46.112777 Set Vref, RX VrefLevel [Byte0]: 45
7888 23:14:46.116126 [Byte1]: 45
7889 23:14:46.120492
7890 23:14:46.120600 Set Vref, RX VrefLevel [Byte0]: 46
7891 23:14:46.123462 [Byte1]: 46
7892 23:14:46.128177
7893 23:14:46.128282 Set Vref, RX VrefLevel [Byte0]: 47
7894 23:14:46.131049 [Byte1]: 47
7895 23:14:46.135681
7896 23:14:46.135791 Set Vref, RX VrefLevel [Byte0]: 48
7897 23:14:46.138682 [Byte1]: 48
7898 23:14:46.142910
7899 23:14:46.143015 Set Vref, RX VrefLevel [Byte0]: 49
7900 23:14:46.146488 [Byte1]: 49
7901 23:14:46.150735
7902 23:14:46.150843 Set Vref, RX VrefLevel [Byte0]: 50
7903 23:14:46.154189 [Byte1]: 50
7904 23:14:46.158147
7905 23:14:46.158257 Set Vref, RX VrefLevel [Byte0]: 51
7906 23:14:46.161500 [Byte1]: 51
7907 23:14:46.165664
7908 23:14:46.165772 Set Vref, RX VrefLevel [Byte0]: 52
7909 23:14:46.169091 [Byte1]: 52
7910 23:14:46.173512
7911 23:14:46.173620 Set Vref, RX VrefLevel [Byte0]: 53
7912 23:14:46.176812 [Byte1]: 53
7913 23:14:46.180938
7914 23:14:46.181050 Set Vref, RX VrefLevel [Byte0]: 54
7915 23:14:46.184493 [Byte1]: 54
7916 23:14:46.188367
7917 23:14:46.188473 Set Vref, RX VrefLevel [Byte0]: 55
7918 23:14:46.191885 [Byte1]: 55
7919 23:14:46.196195
7920 23:14:46.196301 Set Vref, RX VrefLevel [Byte0]: 56
7921 23:14:46.199232 [Byte1]: 56
7922 23:14:46.203528
7923 23:14:46.203608 Set Vref, RX VrefLevel [Byte0]: 57
7924 23:14:46.207089 [Byte1]: 57
7925 23:14:46.211528
7926 23:14:46.211649 Set Vref, RX VrefLevel [Byte0]: 58
7927 23:14:46.214587 [Byte1]: 58
7928 23:14:46.219012
7929 23:14:46.219092 Set Vref, RX VrefLevel [Byte0]: 59
7930 23:14:46.222141 [Byte1]: 59
7931 23:14:46.226634
7932 23:14:46.226767 Set Vref, RX VrefLevel [Byte0]: 60
7933 23:14:46.229661 [Byte1]: 60
7934 23:14:46.233690
7935 23:14:46.233795 Set Vref, RX VrefLevel [Byte0]: 61
7936 23:14:46.237142 [Byte1]: 61
7937 23:14:46.241437
7938 23:14:46.241519 Set Vref, RX VrefLevel [Byte0]: 62
7939 23:14:46.245225 [Byte1]: 62
7940 23:14:46.249453
7941 23:14:46.249534 Set Vref, RX VrefLevel [Byte0]: 63
7942 23:14:46.252535 [Byte1]: 63
7943 23:14:46.256660
7944 23:14:46.256741 Set Vref, RX VrefLevel [Byte0]: 64
7945 23:14:46.260164 [Byte1]: 64
7946 23:14:46.264480
7947 23:14:46.264561 Set Vref, RX VrefLevel [Byte0]: 65
7948 23:14:46.267620 [Byte1]: 65
7949 23:14:46.271767
7950 23:14:46.271871 Set Vref, RX VrefLevel [Byte0]: 66
7951 23:14:46.275268 [Byte1]: 66
7952 23:14:46.279165
7953 23:14:46.279248 Set Vref, RX VrefLevel [Byte0]: 67
7954 23:14:46.282559 [Byte1]: 67
7955 23:14:46.287228
7956 23:14:46.287349 Set Vref, RX VrefLevel [Byte0]: 68
7957 23:14:46.290660 [Byte1]: 68
7958 23:14:46.294531
7959 23:14:46.294634 Set Vref, RX VrefLevel [Byte0]: 69
7960 23:14:46.297737 [Byte1]: 69
7961 23:14:46.302166
7962 23:14:46.302247 Set Vref, RX VrefLevel [Byte0]: 70
7963 23:14:46.305235 [Byte1]: 70
7964 23:14:46.309536
7965 23:14:46.309617 Set Vref, RX VrefLevel [Byte0]: 71
7966 23:14:46.313246 [Byte1]: 71
7967 23:14:46.317119
7968 23:14:46.317200 Set Vref, RX VrefLevel [Byte0]: 72
7969 23:14:46.320756 [Byte1]: 72
7970 23:14:46.325050
7971 23:14:46.325156 Set Vref, RX VrefLevel [Byte0]: 73
7972 23:14:46.328069 [Byte1]: 73
7973 23:14:46.332249
7974 23:14:46.332370 Set Vref, RX VrefLevel [Byte0]: 74
7975 23:14:46.335896 [Byte1]: 74
7976 23:14:46.340212
7977 23:14:46.340305 Set Vref, RX VrefLevel [Byte0]: 75
7978 23:14:46.343284 [Byte1]: 75
7979 23:14:46.347786
7980 23:14:46.347893 Final RX Vref Byte 0 = 59 to rank0
7981 23:14:46.350990 Final RX Vref Byte 1 = 60 to rank0
7982 23:14:46.354387 Final RX Vref Byte 0 = 59 to rank1
7983 23:14:46.357877 Final RX Vref Byte 1 = 60 to rank1==
7984 23:14:46.360972 Dram Type= 6, Freq= 0, CH_0, rank 0
7985 23:14:46.367489 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7986 23:14:46.367597 ==
7987 23:14:46.367697 DQS Delay:
7988 23:14:46.367789 DQS0 = 0, DQS1 = 0
7989 23:14:46.370886 DQM Delay:
7990 23:14:46.370968 DQM0 = 134, DQM1 = 127
7991 23:14:46.374003 DQ Delay:
7992 23:14:46.377537 DQ0 =134, DQ1 =138, DQ2 =134, DQ3 =132
7993 23:14:46.380874 DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =140
7994 23:14:46.383954 DQ8 =116, DQ9 =118, DQ10 =128, DQ11 =120
7995 23:14:46.387152 DQ12 =130, DQ13 =132, DQ14 =138, DQ15 =134
7996 23:14:46.387281
7997 23:14:46.387396
7998 23:14:46.387503
7999 23:14:46.390928 [DramC_TX_OE_Calibration] TA2
8000 23:14:46.394226 Original DQ_B0 (3 6) =30, OEN = 27
8001 23:14:46.397433 Original DQ_B1 (3 6) =30, OEN = 27
8002 23:14:46.400454 24, 0x0, End_B0=24 End_B1=24
8003 23:14:46.400564 25, 0x0, End_B0=25 End_B1=25
8004 23:14:46.403979 26, 0x0, End_B0=26 End_B1=26
8005 23:14:46.407518 27, 0x0, End_B0=27 End_B1=27
8006 23:14:46.410928 28, 0x0, End_B0=28 End_B1=28
8007 23:14:46.411036 29, 0x0, End_B0=29 End_B1=29
8008 23:14:46.414107 30, 0x0, End_B0=30 End_B1=30
8009 23:14:46.417348 31, 0x4141, End_B0=30 End_B1=30
8010 23:14:46.420496 Byte0 end_step=30 best_step=27
8011 23:14:46.423656 Byte1 end_step=30 best_step=27
8012 23:14:46.427278 Byte0 TX OE(2T, 0.5T) = (3, 3)
8013 23:14:46.430939 Byte1 TX OE(2T, 0.5T) = (3, 3)
8014 23:14:46.431046
8015 23:14:46.431138
8016 23:14:46.437111 [DQSOSCAuto] RK0, (LSB)MR18= 0x241f, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 391 ps
8017 23:14:46.440704 CH0 RK0: MR19=303, MR18=241F
8018 23:14:46.446957 CH0_RK0: MR19=0x303, MR18=0x241F, DQSOSC=391, MR23=63, INC=24, DEC=16
8019 23:14:46.447067
8020 23:14:46.450602 ----->DramcWriteLeveling(PI) begin...
8021 23:14:46.450713 ==
8022 23:14:46.453727 Dram Type= 6, Freq= 0, CH_0, rank 1
8023 23:14:46.457185 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8024 23:14:46.457294 ==
8025 23:14:46.460734 Write leveling (Byte 0): 35 => 35
8026 23:14:46.463763 Write leveling (Byte 1): 29 => 29
8027 23:14:46.467460 DramcWriteLeveling(PI) end<-----
8028 23:14:46.467569
8029 23:14:46.467662 ==
8030 23:14:46.470492 Dram Type= 6, Freq= 0, CH_0, rank 1
8031 23:14:46.474048 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8032 23:14:46.474176 ==
8033 23:14:46.477559 [Gating] SW mode calibration
8034 23:14:46.483781 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8035 23:14:46.490483 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8036 23:14:46.493959 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8037 23:14:46.497425 1 4 4 | B1->B0 | 2323 2424 | 0 1 | (0 0) (0 0)
8038 23:14:46.503973 1 4 8 | B1->B0 | 2323 2524 | 0 1 | (0 0) (0 0)
8039 23:14:46.507021 1 4 12 | B1->B0 | 2323 2827 | 0 1 | (0 0) (0 0)
8040 23:14:46.510406 1 4 16 | B1->B0 | 3434 3838 | 0 1 | (0 0) (0 0)
8041 23:14:46.517207 1 4 20 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
8042 23:14:46.520558 1 4 24 | B1->B0 | 3434 3838 | 1 0 | (1 1) (0 0)
8043 23:14:46.523797 1 4 28 | B1->B0 | 3434 3535 | 1 1 | (1 1) (0 0)
8044 23:14:46.530767 1 5 0 | B1->B0 | 3434 3737 | 1 0 | (1 1) (0 0)
8045 23:14:46.533714 1 5 4 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
8046 23:14:46.537456 1 5 8 | B1->B0 | 3434 3535 | 1 1 | (1 1) (0 0)
8047 23:14:46.543527 1 5 12 | B1->B0 | 3434 2c2c | 1 0 | (1 0) (1 0)
8048 23:14:46.547047 1 5 16 | B1->B0 | 3232 2a29 | 0 1 | (1 0) (0 1)
8049 23:14:46.550463 1 5 20 | B1->B0 | 2323 2424 | 0 1 | (0 0) (0 0)
8050 23:14:46.556986 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8051 23:14:46.560571 1 5 28 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
8052 23:14:46.563643 1 6 0 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
8053 23:14:46.570674 1 6 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (1 1)
8054 23:14:46.573446 1 6 8 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
8055 23:14:46.577018 1 6 12 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
8056 23:14:46.580420 1 6 16 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
8057 23:14:46.587192 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8058 23:14:46.590282 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8059 23:14:46.593767 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8060 23:14:46.600161 1 7 0 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
8061 23:14:46.603513 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8062 23:14:46.606951 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8063 23:14:46.613633 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8064 23:14:46.617174 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8065 23:14:46.620189 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8066 23:14:46.627198 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8067 23:14:46.630129 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8068 23:14:46.633727 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8069 23:14:46.640039 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8070 23:14:46.643459 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8071 23:14:46.647041 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8072 23:14:46.653823 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8073 23:14:46.656996 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8074 23:14:46.660041 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8075 23:14:46.666761 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8076 23:14:46.669819 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8077 23:14:46.673473 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8078 23:14:46.680194 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8079 23:14:46.683603 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8080 23:14:46.686808 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8081 23:14:46.689963 Total UI for P1: 0, mck2ui 16
8082 23:14:46.693661 best dqsien dly found for B0: ( 1, 9, 12)
8083 23:14:46.697214 Total UI for P1: 0, mck2ui 16
8084 23:14:46.700000 best dqsien dly found for B1: ( 1, 9, 12)
8085 23:14:46.703694 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8086 23:14:46.706680 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8087 23:14:46.706793
8088 23:14:46.710312 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8089 23:14:46.716790 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8090 23:14:46.716871 [Gating] SW calibration Done
8091 23:14:46.716935 ==
8092 23:14:46.720168 Dram Type= 6, Freq= 0, CH_0, rank 1
8093 23:14:46.726737 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8094 23:14:46.726823 ==
8095 23:14:46.726922 RX Vref Scan: 0
8096 23:14:46.727020
8097 23:14:46.730317 RX Vref 0 -> 0, step: 1
8098 23:14:46.730413
8099 23:14:46.733251 RX Delay 0 -> 252, step: 8
8100 23:14:46.736708 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8101 23:14:46.740320 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8102 23:14:46.743361 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8103 23:14:46.746703 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8104 23:14:46.753655 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8105 23:14:46.757075 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8106 23:14:46.760168 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8107 23:14:46.763704 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8108 23:14:46.766784 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8109 23:14:46.773697 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8110 23:14:46.776660 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8111 23:14:46.779769 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8112 23:14:46.783526 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8113 23:14:46.786491 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8114 23:14:46.793231 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8115 23:14:46.796542 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8116 23:14:46.796661 ==
8117 23:14:46.800251 Dram Type= 6, Freq= 0, CH_0, rank 1
8118 23:14:46.803891 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8119 23:14:46.804004 ==
8120 23:14:46.806841 DQS Delay:
8121 23:14:46.806953 DQS0 = 0, DQS1 = 0
8122 23:14:46.807063 DQM Delay:
8123 23:14:46.809946 DQM0 = 137, DQM1 = 128
8124 23:14:46.810057 DQ Delay:
8125 23:14:46.813692 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
8126 23:14:46.817165 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8127 23:14:46.820070 DQ8 =119, DQ9 =119, DQ10 =127, DQ11 =119
8128 23:14:46.827173 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8129 23:14:46.827288
8130 23:14:46.827394
8131 23:14:46.827538 ==
8132 23:14:46.830009 Dram Type= 6, Freq= 0, CH_0, rank 1
8133 23:14:46.833309 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8134 23:14:46.833429 ==
8135 23:14:46.833538
8136 23:14:46.833645
8137 23:14:46.836925 TX Vref Scan disable
8138 23:14:46.837045 == TX Byte 0 ==
8139 23:14:46.843396 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8140 23:14:46.846571 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8141 23:14:46.846684 == TX Byte 1 ==
8142 23:14:46.853295 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8143 23:14:46.856593 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8144 23:14:46.856711 ==
8145 23:14:46.859825 Dram Type= 6, Freq= 0, CH_0, rank 1
8146 23:14:46.863406 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8147 23:14:46.863528 ==
8148 23:14:46.877974
8149 23:14:46.881162 TX Vref early break, caculate TX vref
8150 23:14:46.884828 TX Vref=16, minBit 0, minWin=23, winSum=386
8151 23:14:46.887597 TX Vref=18, minBit 3, minWin=23, winSum=394
8152 23:14:46.891327 TX Vref=20, minBit 0, minWin=24, winSum=402
8153 23:14:46.894311 TX Vref=22, minBit 1, minWin=24, winSum=409
8154 23:14:46.897942 TX Vref=24, minBit 7, minWin=24, winSum=418
8155 23:14:46.904251 TX Vref=26, minBit 4, minWin=25, winSum=426
8156 23:14:46.907716 TX Vref=28, minBit 0, minWin=26, winSum=424
8157 23:14:46.911242 TX Vref=30, minBit 0, minWin=25, winSum=415
8158 23:14:46.914318 TX Vref=32, minBit 0, minWin=25, winSum=412
8159 23:14:46.918034 TX Vref=34, minBit 0, minWin=24, winSum=399
8160 23:14:46.924613 [TxChooseVref] Worse bit 0, Min win 26, Win sum 424, Final Vref 28
8161 23:14:46.924740
8162 23:14:46.927731 Final TX Range 0 Vref 28
8163 23:14:46.927851
8164 23:14:46.927958 ==
8165 23:14:46.931246 Dram Type= 6, Freq= 0, CH_0, rank 1
8166 23:14:46.934207 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8167 23:14:46.934326 ==
8168 23:14:46.934436
8169 23:14:46.934541
8170 23:14:46.937580 TX Vref Scan disable
8171 23:14:46.944236 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8172 23:14:46.944395 == TX Byte 0 ==
8173 23:14:46.947609 u2DelayCellOfst[0]=13 cells (4 PI)
8174 23:14:46.950592 u2DelayCellOfst[1]=16 cells (5 PI)
8175 23:14:46.954283 u2DelayCellOfst[2]=10 cells (3 PI)
8176 23:14:46.958140 u2DelayCellOfst[3]=10 cells (3 PI)
8177 23:14:46.961092 u2DelayCellOfst[4]=6 cells (2 PI)
8178 23:14:46.964143 u2DelayCellOfst[5]=0 cells (0 PI)
8179 23:14:46.967505 u2DelayCellOfst[6]=16 cells (5 PI)
8180 23:14:46.971038 u2DelayCellOfst[7]=16 cells (5 PI)
8181 23:14:46.974040 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8182 23:14:46.977529 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8183 23:14:46.980781 == TX Byte 1 ==
8184 23:14:46.980902 u2DelayCellOfst[8]=0 cells (0 PI)
8185 23:14:46.984186 u2DelayCellOfst[9]=0 cells (0 PI)
8186 23:14:46.987252 u2DelayCellOfst[10]=6 cells (2 PI)
8187 23:14:46.990951 u2DelayCellOfst[11]=3 cells (1 PI)
8188 23:14:46.993945 u2DelayCellOfst[12]=10 cells (3 PI)
8189 23:14:46.997640 u2DelayCellOfst[13]=10 cells (3 PI)
8190 23:14:47.000855 u2DelayCellOfst[14]=13 cells (4 PI)
8191 23:14:47.004250 u2DelayCellOfst[15]=10 cells (3 PI)
8192 23:14:47.007360 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8193 23:14:47.014188 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8194 23:14:47.014333 DramC Write-DBI on
8195 23:14:47.014463 ==
8196 23:14:47.017543 Dram Type= 6, Freq= 0, CH_0, rank 1
8197 23:14:47.021079 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8198 23:14:47.021199 ==
8199 23:14:47.024106
8200 23:14:47.024220
8201 23:14:47.024368 TX Vref Scan disable
8202 23:14:47.027640 == TX Byte 0 ==
8203 23:14:47.030643 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
8204 23:14:47.034245 == TX Byte 1 ==
8205 23:14:47.037251 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8206 23:14:47.041038 DramC Write-DBI off
8207 23:14:47.041155
8208 23:14:47.041265 [DATLAT]
8209 23:14:47.041370 Freq=1600, CH0 RK1
8210 23:14:47.041478
8211 23:14:47.043903 DATLAT Default: 0xf
8212 23:14:47.044019 0, 0xFFFF, sum = 0
8213 23:14:47.047238 1, 0xFFFF, sum = 0
8214 23:14:47.047362 2, 0xFFFF, sum = 0
8215 23:14:47.050633 3, 0xFFFF, sum = 0
8216 23:14:47.053997 4, 0xFFFF, sum = 0
8217 23:14:47.054117 5, 0xFFFF, sum = 0
8218 23:14:47.057398 6, 0xFFFF, sum = 0
8219 23:14:47.057520 7, 0xFFFF, sum = 0
8220 23:14:47.061086 8, 0xFFFF, sum = 0
8221 23:14:47.061207 9, 0xFFFF, sum = 0
8222 23:14:47.063963 10, 0xFFFF, sum = 0
8223 23:14:47.064084 11, 0xFFFF, sum = 0
8224 23:14:47.067074 12, 0xFFFF, sum = 0
8225 23:14:47.067195 13, 0xFFFF, sum = 0
8226 23:14:47.070757 14, 0x0, sum = 1
8227 23:14:47.070878 15, 0x0, sum = 2
8228 23:14:47.073662 16, 0x0, sum = 3
8229 23:14:47.073777 17, 0x0, sum = 4
8230 23:14:47.077078 best_step = 15
8231 23:14:47.077193
8232 23:14:47.077300 ==
8233 23:14:47.080742 Dram Type= 6, Freq= 0, CH_0, rank 1
8234 23:14:47.083857 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8235 23:14:47.083978 ==
8236 23:14:47.087134 RX Vref Scan: 0
8237 23:14:47.087250
8238 23:14:47.087357 RX Vref 0 -> 0, step: 1
8239 23:14:47.087464
8240 23:14:47.090530 RX Delay 19 -> 252, step: 4
8241 23:14:47.094100 iDelay=191, Bit 0, Center 134 (83 ~ 186) 104
8242 23:14:47.100669 iDelay=191, Bit 1, Center 138 (91 ~ 186) 96
8243 23:14:47.103777 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8244 23:14:47.107242 iDelay=191, Bit 3, Center 134 (83 ~ 186) 104
8245 23:14:47.110939 iDelay=191, Bit 4, Center 136 (87 ~ 186) 100
8246 23:14:47.113974 iDelay=191, Bit 5, Center 126 (75 ~ 178) 104
8247 23:14:47.121044 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8248 23:14:47.123842 iDelay=191, Bit 7, Center 140 (91 ~ 190) 100
8249 23:14:47.127069 iDelay=191, Bit 8, Center 118 (67 ~ 170) 104
8250 23:14:47.130327 iDelay=191, Bit 9, Center 116 (67 ~ 166) 100
8251 23:14:47.133709 iDelay=191, Bit 10, Center 128 (75 ~ 182) 108
8252 23:14:47.140290 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8253 23:14:47.143741 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
8254 23:14:47.146869 iDelay=191, Bit 13, Center 134 (83 ~ 186) 104
8255 23:14:47.150478 iDelay=191, Bit 14, Center 136 (83 ~ 190) 108
8256 23:14:47.153475 iDelay=191, Bit 15, Center 136 (87 ~ 186) 100
8257 23:14:47.157341 ==
8258 23:14:47.157422 Dram Type= 6, Freq= 0, CH_0, rank 1
8259 23:14:47.163679 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8260 23:14:47.163845 ==
8261 23:14:47.163992 DQS Delay:
8262 23:14:47.167109 DQS0 = 0, DQS1 = 0
8263 23:14:47.167249 DQM Delay:
8264 23:14:47.170197 DQM0 = 134, DQM1 = 127
8265 23:14:47.170321 DQ Delay:
8266 23:14:47.173900 DQ0 =134, DQ1 =138, DQ2 =130, DQ3 =134
8267 23:14:47.176945 DQ4 =136, DQ5 =126, DQ6 =140, DQ7 =140
8268 23:14:47.180260 DQ8 =118, DQ9 =116, DQ10 =128, DQ11 =118
8269 23:14:47.183916 DQ12 =134, DQ13 =134, DQ14 =136, DQ15 =136
8270 23:14:47.184054
8271 23:14:47.184164
8272 23:14:47.184265
8273 23:14:47.186876 [DramC_TX_OE_Calibration] TA2
8274 23:14:47.190634 Original DQ_B0 (3 6) =30, OEN = 27
8275 23:14:47.193644 Original DQ_B1 (3 6) =30, OEN = 27
8276 23:14:47.196910 24, 0x0, End_B0=24 End_B1=24
8277 23:14:47.200109 25, 0x0, End_B0=25 End_B1=25
8278 23:14:47.200208 26, 0x0, End_B0=26 End_B1=26
8279 23:14:47.203768 27, 0x0, End_B0=27 End_B1=27
8280 23:14:47.206788 28, 0x0, End_B0=28 End_B1=28
8281 23:14:47.210358 29, 0x0, End_B0=29 End_B1=29
8282 23:14:47.210439 30, 0x0, End_B0=30 End_B1=30
8283 23:14:47.213884 31, 0x5151, End_B0=30 End_B1=30
8284 23:14:47.217036 Byte0 end_step=30 best_step=27
8285 23:14:47.219920 Byte1 end_step=30 best_step=27
8286 23:14:47.223716 Byte0 TX OE(2T, 0.5T) = (3, 3)
8287 23:14:47.226767 Byte1 TX OE(2T, 0.5T) = (3, 3)
8288 23:14:47.226885
8289 23:14:47.226988
8290 23:14:47.233319 [DQSOSCAuto] RK1, (LSB)MR18= 0x2009, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 393 ps
8291 23:14:47.236719 CH0 RK1: MR19=303, MR18=2009
8292 23:14:47.243351 CH0_RK1: MR19=0x303, MR18=0x2009, DQSOSC=393, MR23=63, INC=23, DEC=15
8293 23:14:47.246856 [RxdqsGatingPostProcess] freq 1600
8294 23:14:47.249734 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8295 23:14:47.253603 best DQS0 dly(2T, 0.5T) = (1, 1)
8296 23:14:47.256511 best DQS1 dly(2T, 0.5T) = (1, 1)
8297 23:14:47.260053 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8298 23:14:47.263152 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8299 23:14:47.266663 best DQS0 dly(2T, 0.5T) = (1, 1)
8300 23:14:47.269552 best DQS1 dly(2T, 0.5T) = (1, 1)
8301 23:14:47.273147 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8302 23:14:47.276811 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8303 23:14:47.279928 Pre-setting of DQS Precalculation
8304 23:14:47.283014 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8305 23:14:47.283095 ==
8306 23:14:47.286714 Dram Type= 6, Freq= 0, CH_1, rank 0
8307 23:14:47.293145 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8308 23:14:47.293226 ==
8309 23:14:47.296749 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8310 23:14:47.302932 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8311 23:14:47.306102 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8312 23:14:47.313036 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8313 23:14:47.320510 [CA 0] Center 41 (12~71) winsize 60
8314 23:14:47.323594 [CA 1] Center 41 (12~71) winsize 60
8315 23:14:47.327248 [CA 2] Center 38 (9~68) winsize 60
8316 23:14:47.330286 [CA 3] Center 37 (9~66) winsize 58
8317 23:14:47.333912 [CA 4] Center 37 (8~67) winsize 60
8318 23:14:47.336914 [CA 5] Center 36 (7~66) winsize 60
8319 23:14:47.337033
8320 23:14:47.340478 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8321 23:14:47.340597
8322 23:14:47.343471 [CATrainingPosCal] consider 1 rank data
8323 23:14:47.346744 u2DelayCellTimex100 = 290/100 ps
8324 23:14:47.350107 CA0 delay=41 (12~71),Diff = 5 PI (16 cell)
8325 23:14:47.357088 CA1 delay=41 (12~71),Diff = 5 PI (16 cell)
8326 23:14:47.360194 CA2 delay=38 (9~68),Diff = 2 PI (6 cell)
8327 23:14:47.363244 CA3 delay=37 (9~66),Diff = 1 PI (3 cell)
8328 23:14:47.366814 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8329 23:14:47.370347 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8330 23:14:47.370447
8331 23:14:47.373467 CA PerBit enable=1, Macro0, CA PI delay=36
8332 23:14:47.373548
8333 23:14:47.376842 [CBTSetCACLKResult] CA Dly = 36
8334 23:14:47.379930 CS Dly: 11 (0~42)
8335 23:14:47.383655 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8336 23:14:47.386533 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8337 23:14:47.386628 ==
8338 23:14:47.390161 Dram Type= 6, Freq= 0, CH_1, rank 1
8339 23:14:47.393682 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8340 23:14:47.396692 ==
8341 23:14:47.400089 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8342 23:14:47.403133 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8343 23:14:47.409660 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8344 23:14:47.413349 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8345 23:14:47.423504 [CA 0] Center 41 (12~71) winsize 60
8346 23:14:47.426939 [CA 1] Center 42 (12~72) winsize 61
8347 23:14:47.430099 [CA 2] Center 38 (8~68) winsize 61
8348 23:14:47.433768 [CA 3] Center 37 (8~67) winsize 60
8349 23:14:47.436739 [CA 4] Center 38 (8~69) winsize 62
8350 23:14:47.440325 [CA 5] Center 36 (7~66) winsize 60
8351 23:14:47.440420
8352 23:14:47.443380 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8353 23:14:47.443460
8354 23:14:47.447234 [CATrainingPosCal] consider 2 rank data
8355 23:14:47.450622 u2DelayCellTimex100 = 290/100 ps
8356 23:14:47.453550 CA0 delay=41 (12~71),Diff = 5 PI (16 cell)
8357 23:14:47.460497 CA1 delay=41 (12~71),Diff = 5 PI (16 cell)
8358 23:14:47.463853 CA2 delay=38 (9~68),Diff = 2 PI (6 cell)
8359 23:14:47.466814 CA3 delay=37 (9~66),Diff = 1 PI (3 cell)
8360 23:14:47.470263 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8361 23:14:47.473816 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8362 23:14:47.473896
8363 23:14:47.476816 CA PerBit enable=1, Macro0, CA PI delay=36
8364 23:14:47.476895
8365 23:14:47.480568 [CBTSetCACLKResult] CA Dly = 36
8366 23:14:47.480647 CS Dly: 12 (0~45)
8367 23:14:47.486856 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8368 23:14:47.490490 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8369 23:14:47.490570
8370 23:14:47.493621 ----->DramcWriteLeveling(PI) begin...
8371 23:14:47.493701 ==
8372 23:14:47.496508 Dram Type= 6, Freq= 0, CH_1, rank 0
8373 23:14:47.500082 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8374 23:14:47.503200 ==
8375 23:14:47.503279 Write leveling (Byte 0): 24 => 24
8376 23:14:47.506665 Write leveling (Byte 1): 27 => 27
8377 23:14:47.509720 DramcWriteLeveling(PI) end<-----
8378 23:14:47.509798
8379 23:14:47.509863 ==
8380 23:14:47.513371 Dram Type= 6, Freq= 0, CH_1, rank 0
8381 23:14:47.520118 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8382 23:14:47.520202 ==
8383 23:14:47.523086 [Gating] SW mode calibration
8384 23:14:47.530011 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8385 23:14:47.533242 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8386 23:14:47.540071 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8387 23:14:47.543776 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8388 23:14:47.546930 1 4 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8389 23:14:47.549968 1 4 12 | B1->B0 | 3030 3434 | 1 1 | (0 0) (1 1)
8390 23:14:47.556623 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8391 23:14:47.559656 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8392 23:14:47.563176 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8393 23:14:47.569801 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8394 23:14:47.573180 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8395 23:14:47.576600 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8396 23:14:47.582904 1 5 8 | B1->B0 | 3434 3131 | 1 1 | (1 0) (1 0)
8397 23:14:47.586026 1 5 12 | B1->B0 | 2929 2323 | 0 0 | (1 0) (1 0)
8398 23:14:47.589710 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8399 23:14:47.596525 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8400 23:14:47.599506 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8401 23:14:47.603096 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8402 23:14:47.609703 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8403 23:14:47.612727 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8404 23:14:47.616260 1 6 8 | B1->B0 | 2424 3c3c | 0 1 | (0 0) (0 0)
8405 23:14:47.623110 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8406 23:14:47.626214 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8407 23:14:47.629566 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8408 23:14:47.636226 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8409 23:14:47.639673 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8410 23:14:47.643117 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8411 23:14:47.649308 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8412 23:14:47.652745 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8413 23:14:47.656238 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8414 23:14:47.662909 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8415 23:14:47.666035 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8416 23:14:47.669632 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8417 23:14:47.676154 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8418 23:14:47.679879 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8419 23:14:47.682605 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8420 23:14:47.689292 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8421 23:14:47.692762 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8422 23:14:47.696222 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8423 23:14:47.699381 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8424 23:14:47.706271 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8425 23:14:47.709526 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8426 23:14:47.712523 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8427 23:14:47.719257 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8428 23:14:47.722781 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8429 23:14:47.726259 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8430 23:14:47.732861 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8431 23:14:47.735789 Total UI for P1: 0, mck2ui 16
8432 23:14:47.739520 best dqsien dly found for B0: ( 1, 9, 10)
8433 23:14:47.739603 Total UI for P1: 0, mck2ui 16
8434 23:14:47.745670 best dqsien dly found for B1: ( 1, 9, 10)
8435 23:14:47.749203 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8436 23:14:47.752220 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8437 23:14:47.752348
8438 23:14:47.755705 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8439 23:14:47.758988 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8440 23:14:47.762245 [Gating] SW calibration Done
8441 23:14:47.762325 ==
8442 23:14:47.765669 Dram Type= 6, Freq= 0, CH_1, rank 0
8443 23:14:47.769368 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8444 23:14:47.769449 ==
8445 23:14:47.772319 RX Vref Scan: 0
8446 23:14:47.772401
8447 23:14:47.772484 RX Vref 0 -> 0, step: 1
8448 23:14:47.775984
8449 23:14:47.776065 RX Delay 0 -> 252, step: 8
8450 23:14:47.782454 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8451 23:14:47.785541 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8452 23:14:47.789010 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8453 23:14:47.792232 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8454 23:14:47.795834 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8455 23:14:47.799234 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8456 23:14:47.805580 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8457 23:14:47.809169 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8458 23:14:47.812212 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
8459 23:14:47.815797 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8460 23:14:47.818793 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8461 23:14:47.825559 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8462 23:14:47.829051 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8463 23:14:47.832147 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
8464 23:14:47.835676 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8465 23:14:47.838848 iDelay=200, Bit 15, Center 143 (88 ~ 199) 112
8466 23:14:47.842212 ==
8467 23:14:47.845296 Dram Type= 6, Freq= 0, CH_1, rank 0
8468 23:14:47.849069 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8469 23:14:47.849151 ==
8470 23:14:47.849234 DQS Delay:
8471 23:14:47.851965 DQS0 = 0, DQS1 = 0
8472 23:14:47.852048 DQM Delay:
8473 23:14:47.855508 DQM0 = 135, DQM1 = 132
8474 23:14:47.855591 DQ Delay:
8475 23:14:47.859156 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8476 23:14:47.862015 DQ4 =131, DQ5 =147, DQ6 =143, DQ7 =135
8477 23:14:47.865588 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =127
8478 23:14:47.869159 DQ12 =139, DQ13 =139, DQ14 =139, DQ15 =143
8479 23:14:47.869241
8480 23:14:47.869324
8481 23:14:47.869402 ==
8482 23:14:47.872193 Dram Type= 6, Freq= 0, CH_1, rank 0
8483 23:14:47.879024 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8484 23:14:47.879106 ==
8485 23:14:47.879190
8486 23:14:47.879269
8487 23:14:47.879345 TX Vref Scan disable
8488 23:14:47.882600 == TX Byte 0 ==
8489 23:14:47.885975 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8490 23:14:47.889076 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8491 23:14:47.892846 == TX Byte 1 ==
8492 23:14:47.895560 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8493 23:14:47.898768 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8494 23:14:47.902470 ==
8495 23:14:47.905781 Dram Type= 6, Freq= 0, CH_1, rank 0
8496 23:14:47.909192 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8497 23:14:47.909273 ==
8498 23:14:47.921204
8499 23:14:47.924605 TX Vref early break, caculate TX vref
8500 23:14:47.927677 TX Vref=16, minBit 0, minWin=22, winSum=376
8501 23:14:47.931190 TX Vref=18, minBit 1, minWin=23, winSum=392
8502 23:14:47.934883 TX Vref=20, minBit 1, minWin=23, winSum=398
8503 23:14:47.938054 TX Vref=22, minBit 1, minWin=24, winSum=406
8504 23:14:47.941462 TX Vref=24, minBit 0, minWin=25, winSum=420
8505 23:14:47.944978 TX Vref=26, minBit 0, minWin=25, winSum=426
8506 23:14:47.951353 TX Vref=28, minBit 0, minWin=26, winSum=429
8507 23:14:47.954506 TX Vref=30, minBit 2, minWin=25, winSum=425
8508 23:14:47.957824 TX Vref=32, minBit 0, minWin=24, winSum=415
8509 23:14:47.961455 TX Vref=34, minBit 0, minWin=24, winSum=403
8510 23:14:47.968054 [TxChooseVref] Worse bit 0, Min win 26, Win sum 429, Final Vref 28
8511 23:14:47.968135
8512 23:14:47.971142 Final TX Range 0 Vref 28
8513 23:14:47.971223
8514 23:14:47.971286 ==
8515 23:14:47.974703 Dram Type= 6, Freq= 0, CH_1, rank 0
8516 23:14:47.978147 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8517 23:14:47.978230 ==
8518 23:14:47.978301
8519 23:14:47.978379
8520 23:14:47.981488 TX Vref Scan disable
8521 23:14:47.987909 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8522 23:14:47.987989 == TX Byte 0 ==
8523 23:14:47.991335 u2DelayCellOfst[0]=16 cells (5 PI)
8524 23:14:47.994413 u2DelayCellOfst[1]=10 cells (3 PI)
8525 23:14:47.998016 u2DelayCellOfst[2]=0 cells (0 PI)
8526 23:14:48.001125 u2DelayCellOfst[3]=3 cells (1 PI)
8527 23:14:48.004804 u2DelayCellOfst[4]=6 cells (2 PI)
8528 23:14:48.007575 u2DelayCellOfst[5]=16 cells (5 PI)
8529 23:14:48.007682 u2DelayCellOfst[6]=16 cells (5 PI)
8530 23:14:48.011006 u2DelayCellOfst[7]=3 cells (1 PI)
8531 23:14:48.017698 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8532 23:14:48.021341 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8533 23:14:48.021423 == TX Byte 1 ==
8534 23:14:48.024537 u2DelayCellOfst[8]=0 cells (0 PI)
8535 23:14:48.028090 u2DelayCellOfst[9]=3 cells (1 PI)
8536 23:14:48.031278 u2DelayCellOfst[10]=13 cells (4 PI)
8537 23:14:48.034319 u2DelayCellOfst[11]=3 cells (1 PI)
8538 23:14:48.037938 u2DelayCellOfst[12]=16 cells (5 PI)
8539 23:14:48.041021 u2DelayCellOfst[13]=16 cells (5 PI)
8540 23:14:48.044168 u2DelayCellOfst[14]=16 cells (5 PI)
8541 23:14:48.047854 u2DelayCellOfst[15]=16 cells (5 PI)
8542 23:14:48.050829 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8543 23:14:48.054265 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8544 23:14:48.057814 DramC Write-DBI on
8545 23:14:48.057896 ==
8546 23:14:48.061047 Dram Type= 6, Freq= 0, CH_1, rank 0
8547 23:14:48.064318 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8548 23:14:48.064401 ==
8549 23:14:48.064464
8550 23:14:48.067301
8551 23:14:48.067381 TX Vref Scan disable
8552 23:14:48.070775 == TX Byte 0 ==
8553 23:14:48.074430 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8554 23:14:48.077507 == TX Byte 1 ==
8555 23:14:48.080704 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8556 23:14:48.080788 DramC Write-DBI off
8557 23:14:48.080852
8558 23:14:48.084279 [DATLAT]
8559 23:14:48.084384 Freq=1600, CH1 RK0
8560 23:14:48.084448
8561 23:14:48.087633 DATLAT Default: 0xf
8562 23:14:48.087714 0, 0xFFFF, sum = 0
8563 23:14:48.090976 1, 0xFFFF, sum = 0
8564 23:14:48.091058 2, 0xFFFF, sum = 0
8565 23:14:48.094470 3, 0xFFFF, sum = 0
8566 23:14:48.094552 4, 0xFFFF, sum = 0
8567 23:14:48.097838 5, 0xFFFF, sum = 0
8568 23:14:48.097920 6, 0xFFFF, sum = 0
8569 23:14:48.100848 7, 0xFFFF, sum = 0
8570 23:14:48.100930 8, 0xFFFF, sum = 0
8571 23:14:48.104559 9, 0xFFFF, sum = 0
8572 23:14:48.104641 10, 0xFFFF, sum = 0
8573 23:14:48.107691 11, 0xFFFF, sum = 0
8574 23:14:48.111201 12, 0xFFFF, sum = 0
8575 23:14:48.111283 13, 0xFFFF, sum = 0
8576 23:14:48.114245 14, 0x0, sum = 1
8577 23:14:48.114327 15, 0x0, sum = 2
8578 23:14:48.117821 16, 0x0, sum = 3
8579 23:14:48.117904 17, 0x0, sum = 4
8580 23:14:48.117969 best_step = 15
8581 23:14:48.118028
8582 23:14:48.121029 ==
8583 23:14:48.124488 Dram Type= 6, Freq= 0, CH_1, rank 0
8584 23:14:48.127793 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8585 23:14:48.127874 ==
8586 23:14:48.127937 RX Vref Scan: 1
8587 23:14:48.127996
8588 23:14:48.131002 Set Vref Range= 24 -> 127
8589 23:14:48.131083
8590 23:14:48.134288 RX Vref 24 -> 127, step: 1
8591 23:14:48.134369
8592 23:14:48.137765 RX Delay 27 -> 252, step: 4
8593 23:14:48.137893
8594 23:14:48.141034 Set Vref, RX VrefLevel [Byte0]: 24
8595 23:14:48.144088 [Byte1]: 24
8596 23:14:48.144169
8597 23:14:48.147331 Set Vref, RX VrefLevel [Byte0]: 25
8598 23:14:48.150481 [Byte1]: 25
8599 23:14:48.150562
8600 23:14:48.154195 Set Vref, RX VrefLevel [Byte0]: 26
8601 23:14:48.157197 [Byte1]: 26
8602 23:14:48.157277
8603 23:14:48.160752 Set Vref, RX VrefLevel [Byte0]: 27
8604 23:14:48.164249 [Byte1]: 27
8605 23:14:48.168419
8606 23:14:48.168500 Set Vref, RX VrefLevel [Byte0]: 28
8607 23:14:48.171278 [Byte1]: 28
8608 23:14:48.175863
8609 23:14:48.175942 Set Vref, RX VrefLevel [Byte0]: 29
8610 23:14:48.179196 [Byte1]: 29
8611 23:14:48.183465
8612 23:14:48.183551 Set Vref, RX VrefLevel [Byte0]: 30
8613 23:14:48.186587 [Byte1]: 30
8614 23:14:48.190823
8615 23:14:48.190951 Set Vref, RX VrefLevel [Byte0]: 31
8616 23:14:48.193800 [Byte1]: 31
8617 23:14:48.197975
8618 23:14:48.198058 Set Vref, RX VrefLevel [Byte0]: 32
8619 23:14:48.201558 [Byte1]: 32
8620 23:14:48.205901
8621 23:14:48.205981 Set Vref, RX VrefLevel [Byte0]: 33
8622 23:14:48.208820 [Byte1]: 33
8623 23:14:48.213731
8624 23:14:48.213812 Set Vref, RX VrefLevel [Byte0]: 34
8625 23:14:48.216783 [Byte1]: 34
8626 23:14:48.220872
8627 23:14:48.220952 Set Vref, RX VrefLevel [Byte0]: 35
8628 23:14:48.223869 [Byte1]: 35
8629 23:14:48.228179
8630 23:14:48.228275 Set Vref, RX VrefLevel [Byte0]: 36
8631 23:14:48.231593 [Byte1]: 36
8632 23:14:48.235619
8633 23:14:48.235700 Set Vref, RX VrefLevel [Byte0]: 37
8634 23:14:48.239010 [Byte1]: 37
8635 23:14:48.243476
8636 23:14:48.243557 Set Vref, RX VrefLevel [Byte0]: 38
8637 23:14:48.246554 [Byte1]: 38
8638 23:14:48.251155
8639 23:14:48.251235 Set Vref, RX VrefLevel [Byte0]: 39
8640 23:14:48.254385 [Byte1]: 39
8641 23:14:48.258250
8642 23:14:48.258331 Set Vref, RX VrefLevel [Byte0]: 40
8643 23:14:48.261714 [Byte1]: 40
8644 23:14:48.266450
8645 23:14:48.266531 Set Vref, RX VrefLevel [Byte0]: 41
8646 23:14:48.269298 [Byte1]: 41
8647 23:14:48.273552
8648 23:14:48.273632 Set Vref, RX VrefLevel [Byte0]: 42
8649 23:14:48.277172 [Byte1]: 42
8650 23:14:48.281410
8651 23:14:48.281490 Set Vref, RX VrefLevel [Byte0]: 43
8652 23:14:48.284201 [Byte1]: 43
8653 23:14:48.288659
8654 23:14:48.288741 Set Vref, RX VrefLevel [Byte0]: 44
8655 23:14:48.292088 [Byte1]: 44
8656 23:14:48.296219
8657 23:14:48.296326 Set Vref, RX VrefLevel [Byte0]: 45
8658 23:14:48.299208 [Byte1]: 45
8659 23:14:48.303475
8660 23:14:48.303555 Set Vref, RX VrefLevel [Byte0]: 46
8661 23:14:48.307305 [Byte1]: 46
8662 23:14:48.311187
8663 23:14:48.311268 Set Vref, RX VrefLevel [Byte0]: 47
8664 23:14:48.314282 [Byte1]: 47
8665 23:14:48.318810
8666 23:14:48.318891 Set Vref, RX VrefLevel [Byte0]: 48
8667 23:14:48.322067 [Byte1]: 48
8668 23:14:48.326056
8669 23:14:48.326137 Set Vref, RX VrefLevel [Byte0]: 49
8670 23:14:48.329777 [Byte1]: 49
8671 23:14:48.334069
8672 23:14:48.334150 Set Vref, RX VrefLevel [Byte0]: 50
8673 23:14:48.337163 [Byte1]: 50
8674 23:14:48.341489
8675 23:14:48.341570 Set Vref, RX VrefLevel [Byte0]: 51
8676 23:14:48.344565 [Byte1]: 51
8677 23:14:48.349099
8678 23:14:48.349180 Set Vref, RX VrefLevel [Byte0]: 52
8679 23:14:48.351887 [Byte1]: 52
8680 23:14:48.356199
8681 23:14:48.356282 Set Vref, RX VrefLevel [Byte0]: 53
8682 23:14:48.359717 [Byte1]: 53
8683 23:14:48.364031
8684 23:14:48.364131 Set Vref, RX VrefLevel [Byte0]: 54
8685 23:14:48.367293 [Byte1]: 54
8686 23:14:48.371616
8687 23:14:48.371696 Set Vref, RX VrefLevel [Byte0]: 55
8688 23:14:48.374696 [Byte1]: 55
8689 23:14:48.378862
8690 23:14:48.378942 Set Vref, RX VrefLevel [Byte0]: 56
8691 23:14:48.382296 [Byte1]: 56
8692 23:14:48.386581
8693 23:14:48.386662 Set Vref, RX VrefLevel [Byte0]: 57
8694 23:14:48.390131 [Byte1]: 57
8695 23:14:48.394129
8696 23:14:48.394209 Set Vref, RX VrefLevel [Byte0]: 58
8697 23:14:48.397296 [Byte1]: 58
8698 23:14:48.401771
8699 23:14:48.401851 Set Vref, RX VrefLevel [Byte0]: 59
8700 23:14:48.404562 [Byte1]: 59
8701 23:14:48.409474
8702 23:14:48.409553 Set Vref, RX VrefLevel [Byte0]: 60
8703 23:14:48.412635 [Byte1]: 60
8704 23:14:48.416919
8705 23:14:48.416999 Set Vref, RX VrefLevel [Byte0]: 61
8706 23:14:48.420408 [Byte1]: 61
8707 23:14:48.423970
8708 23:14:48.424050 Set Vref, RX VrefLevel [Byte0]: 62
8709 23:14:48.427253 [Byte1]: 62
8710 23:14:48.431902
8711 23:14:48.431983 Set Vref, RX VrefLevel [Byte0]: 63
8712 23:14:48.434901 [Byte1]: 63
8713 23:14:48.439178
8714 23:14:48.439285 Set Vref, RX VrefLevel [Byte0]: 64
8715 23:14:48.442875 [Byte1]: 64
8716 23:14:48.446558
8717 23:14:48.446639 Set Vref, RX VrefLevel [Byte0]: 65
8718 23:14:48.450209 [Byte1]: 65
8719 23:14:48.454243
8720 23:14:48.454325 Set Vref, RX VrefLevel [Byte0]: 66
8721 23:14:48.457826 [Byte1]: 66
8722 23:14:48.461833
8723 23:14:48.461915 Set Vref, RX VrefLevel [Byte0]: 67
8724 23:14:48.464878 [Byte1]: 67
8725 23:14:48.469147
8726 23:14:48.469260 Set Vref, RX VrefLevel [Byte0]: 68
8727 23:14:48.472429 [Byte1]: 68
8728 23:14:48.476744
8729 23:14:48.476825 Set Vref, RX VrefLevel [Byte0]: 69
8730 23:14:48.480479 [Byte1]: 69
8731 23:14:48.484560
8732 23:14:48.484642 Set Vref, RX VrefLevel [Byte0]: 70
8733 23:14:48.487746 [Byte1]: 70
8734 23:14:48.492146
8735 23:14:48.492262 Set Vref, RX VrefLevel [Byte0]: 71
8736 23:14:48.495410 [Byte1]: 71
8737 23:14:48.499308
8738 23:14:48.499389 Set Vref, RX VrefLevel [Byte0]: 72
8739 23:14:48.502881 [Byte1]: 72
8740 23:14:48.507522
8741 23:14:48.507619 Set Vref, RX VrefLevel [Byte0]: 73
8742 23:14:48.510138 [Byte1]: 73
8743 23:14:48.514555
8744 23:14:48.514651 Set Vref, RX VrefLevel [Byte0]: 74
8745 23:14:48.517563 [Byte1]: 74
8746 23:14:48.521912
8747 23:14:48.521994 Set Vref, RX VrefLevel [Byte0]: 75
8748 23:14:48.525008 [Byte1]: 75
8749 23:14:48.529736
8750 23:14:48.529818 Set Vref, RX VrefLevel [Byte0]: 76
8751 23:14:48.533210 [Byte1]: 76
8752 23:14:48.537104
8753 23:14:48.537185 Set Vref, RX VrefLevel [Byte0]: 77
8754 23:14:48.540469 [Byte1]: 77
8755 23:14:48.544557
8756 23:14:48.544687 Set Vref, RX VrefLevel [Byte0]: 78
8757 23:14:48.548204 [Byte1]: 78
8758 23:14:48.552010
8759 23:14:48.552133 Set Vref, RX VrefLevel [Byte0]: 79
8760 23:14:48.555724 [Byte1]: 79
8761 23:14:48.559990
8762 23:14:48.560108 Set Vref, RX VrefLevel [Byte0]: 80
8763 23:14:48.562851 [Byte1]: 80
8764 23:14:48.566889
8765 23:14:48.567012 Final RX Vref Byte 0 = 58 to rank0
8766 23:14:48.570383 Final RX Vref Byte 1 = 54 to rank0
8767 23:14:48.574199 Final RX Vref Byte 0 = 58 to rank1
8768 23:14:48.577285 Final RX Vref Byte 1 = 54 to rank1==
8769 23:14:48.581008 Dram Type= 6, Freq= 0, CH_1, rank 0
8770 23:14:48.587477 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8771 23:14:48.587608 ==
8772 23:14:48.587723 DQS Delay:
8773 23:14:48.587833 DQS0 = 0, DQS1 = 0
8774 23:14:48.590536 DQM Delay:
8775 23:14:48.590640 DQM0 = 134, DQM1 = 131
8776 23:14:48.593878 DQ Delay:
8777 23:14:48.597463 DQ0 =140, DQ1 =128, DQ2 =122, DQ3 =130
8778 23:14:48.600603 DQ4 =134, DQ5 =144, DQ6 =142, DQ7 =134
8779 23:14:48.604060 DQ8 =116, DQ9 =122, DQ10 =132, DQ11 =124
8780 23:14:48.606970 DQ12 =138, DQ13 =138, DQ14 =140, DQ15 =140
8781 23:14:48.607073
8782 23:14:48.607164
8783 23:14:48.607250
8784 23:14:48.610278 [DramC_TX_OE_Calibration] TA2
8785 23:14:48.613690 Original DQ_B0 (3 6) =30, OEN = 27
8786 23:14:48.617189 Original DQ_B1 (3 6) =30, OEN = 27
8787 23:14:48.620644 24, 0x0, End_B0=24 End_B1=24
8788 23:14:48.620726 25, 0x0, End_B0=25 End_B1=25
8789 23:14:48.623528 26, 0x0, End_B0=26 End_B1=26
8790 23:14:48.627062 27, 0x0, End_B0=27 End_B1=27
8791 23:14:48.630626 28, 0x0, End_B0=28 End_B1=28
8792 23:14:48.630708 29, 0x0, End_B0=29 End_B1=29
8793 23:14:48.633702 30, 0x0, End_B0=30 End_B1=30
8794 23:14:48.637203 31, 0x4141, End_B0=30 End_B1=30
8795 23:14:48.640592 Byte0 end_step=30 best_step=27
8796 23:14:48.643773 Byte1 end_step=30 best_step=27
8797 23:14:48.647067 Byte0 TX OE(2T, 0.5T) = (3, 3)
8798 23:14:48.647150 Byte1 TX OE(2T, 0.5T) = (3, 3)
8799 23:14:48.650342
8800 23:14:48.650426
8801 23:14:48.657091 [DQSOSCAuto] RK0, (LSB)MR18= 0x1825, (MSB)MR19= 0x303, tDQSOscB0 = 391 ps tDQSOscB1 = 397 ps
8802 23:14:48.660752 CH1 RK0: MR19=303, MR18=1825
8803 23:14:48.667238 CH1_RK0: MR19=0x303, MR18=0x1825, DQSOSC=391, MR23=63, INC=24, DEC=16
8804 23:14:48.667338
8805 23:14:48.670396 ----->DramcWriteLeveling(PI) begin...
8806 23:14:48.670483 ==
8807 23:14:48.673853 Dram Type= 6, Freq= 0, CH_1, rank 1
8808 23:14:48.676915 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8809 23:14:48.677050 ==
8810 23:14:48.680432 Write leveling (Byte 0): 25 => 25
8811 23:14:48.683575 Write leveling (Byte 1): 29 => 29
8812 23:14:48.687012 DramcWriteLeveling(PI) end<-----
8813 23:14:48.687145
8814 23:14:48.687258 ==
8815 23:14:48.690134 Dram Type= 6, Freq= 0, CH_1, rank 1
8816 23:14:48.693251 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8817 23:14:48.693360 ==
8818 23:14:48.696872 [Gating] SW mode calibration
8819 23:14:48.703883 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8820 23:14:48.710399 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8821 23:14:48.713336 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8822 23:14:48.716755 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8823 23:14:48.723434 1 4 8 | B1->B0 | 2827 2323 | 1 0 | (0 0) (0 0)
8824 23:14:48.727105 1 4 12 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 1)
8825 23:14:48.730612 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8826 23:14:48.737088 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8827 23:14:48.740100 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8828 23:14:48.743863 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8829 23:14:48.750419 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8830 23:14:48.753480 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8831 23:14:48.756693 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8832 23:14:48.763358 1 5 12 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
8833 23:14:48.766855 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8834 23:14:48.769981 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8835 23:14:48.776589 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8836 23:14:48.780162 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8837 23:14:48.783567 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8838 23:14:48.790236 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8839 23:14:48.793319 1 6 8 | B1->B0 | 3838 2323 | 0 0 | (0 0) (0 0)
8840 23:14:48.796922 1 6 12 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
8841 23:14:48.803700 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8842 23:14:48.806434 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8843 23:14:48.810134 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8844 23:14:48.813134 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8845 23:14:48.819675 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8846 23:14:48.823255 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8847 23:14:48.827129 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8848 23:14:48.833025 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8849 23:14:48.836610 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8850 23:14:48.839654 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8851 23:14:48.846816 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8852 23:14:48.849805 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8853 23:14:48.853030 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8854 23:14:48.859706 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8855 23:14:48.862859 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8856 23:14:48.866735 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8857 23:14:48.873490 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8858 23:14:48.876423 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8859 23:14:48.879611 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8860 23:14:48.886387 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8861 23:14:48.889913 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8862 23:14:48.892923 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8863 23:14:48.899623 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8864 23:14:48.899754 Total UI for P1: 0, mck2ui 16
8865 23:14:48.906362 best dqsien dly found for B1: ( 1, 9, 4)
8866 23:14:48.909436 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8867 23:14:48.912831 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8868 23:14:48.919545 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8869 23:14:48.919673 Total UI for P1: 0, mck2ui 16
8870 23:14:48.923082 best dqsien dly found for B0: ( 1, 9, 14)
8871 23:14:48.929310 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8872 23:14:48.932949 best DQS1 dly(MCK, UI, PI) = (1, 9, 4)
8873 23:14:48.933070
8874 23:14:48.936094 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8875 23:14:48.939716 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 4)
8876 23:14:48.942779 [Gating] SW calibration Done
8877 23:14:48.942894 ==
8878 23:14:48.945821 Dram Type= 6, Freq= 0, CH_1, rank 1
8879 23:14:48.949389 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8880 23:14:48.949478 ==
8881 23:14:48.952530 RX Vref Scan: 0
8882 23:14:48.952615
8883 23:14:48.952678 RX Vref 0 -> 0, step: 1
8884 23:14:48.952737
8885 23:14:48.956029 RX Delay 0 -> 252, step: 8
8886 23:14:48.959387 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8887 23:14:48.962866 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8888 23:14:48.969132 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8889 23:14:48.972980 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8890 23:14:48.976204 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8891 23:14:48.979421 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8892 23:14:48.982833 iDelay=208, Bit 6, Center 143 (88 ~ 199) 112
8893 23:14:48.989144 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8894 23:14:48.992805 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8895 23:14:48.996140 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8896 23:14:48.999034 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8897 23:14:49.002901 iDelay=208, Bit 11, Center 127 (72 ~ 183) 112
8898 23:14:49.009127 iDelay=208, Bit 12, Center 143 (88 ~ 199) 112
8899 23:14:49.012694 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8900 23:14:49.015685 iDelay=208, Bit 14, Center 139 (88 ~ 191) 104
8901 23:14:49.019143 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8902 23:14:49.019247 ==
8903 23:14:49.022648 Dram Type= 6, Freq= 0, CH_1, rank 1
8904 23:14:49.029235 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8905 23:14:49.029340 ==
8906 23:14:49.029406 DQS Delay:
8907 23:14:49.032652 DQS0 = 0, DQS1 = 0
8908 23:14:49.032734 DQM Delay:
8909 23:14:49.032798 DQM0 = 136, DQM1 = 133
8910 23:14:49.035750 DQ Delay:
8911 23:14:49.039498 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =131
8912 23:14:49.042448 DQ4 =131, DQ5 =151, DQ6 =143, DQ7 =135
8913 23:14:49.045996 DQ8 =119, DQ9 =119, DQ10 =135, DQ11 =127
8914 23:14:49.049122 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8915 23:14:49.049210
8916 23:14:49.049274
8917 23:14:49.049333 ==
8918 23:14:49.052282 Dram Type= 6, Freq= 0, CH_1, rank 1
8919 23:14:49.058978 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8920 23:14:49.059081 ==
8921 23:14:49.059148
8922 23:14:49.059207
8923 23:14:49.059263 TX Vref Scan disable
8924 23:14:49.062628 == TX Byte 0 ==
8925 23:14:49.065568 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8926 23:14:49.068955 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8927 23:14:49.072133 == TX Byte 1 ==
8928 23:14:49.075688 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8929 23:14:49.079097 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8930 23:14:49.082349 ==
8931 23:14:49.085368 Dram Type= 6, Freq= 0, CH_1, rank 1
8932 23:14:49.088741 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8933 23:14:49.088831 ==
8934 23:14:49.101527
8935 23:14:49.104197 TX Vref early break, caculate TX vref
8936 23:14:49.107669 TX Vref=16, minBit 0, minWin=23, winSum=384
8937 23:14:49.111592 TX Vref=18, minBit 1, minWin=23, winSum=392
8938 23:14:49.114283 TX Vref=20, minBit 0, minWin=23, winSum=399
8939 23:14:49.117856 TX Vref=22, minBit 0, minWin=25, winSum=410
8940 23:14:49.121308 TX Vref=24, minBit 0, minWin=25, winSum=419
8941 23:14:49.127858 TX Vref=26, minBit 0, minWin=25, winSum=423
8942 23:14:49.131438 TX Vref=28, minBit 0, minWin=25, winSum=429
8943 23:14:49.134404 TX Vref=30, minBit 0, minWin=25, winSum=417
8944 23:14:49.137816 TX Vref=32, minBit 0, minWin=25, winSum=415
8945 23:14:49.141134 TX Vref=34, minBit 15, minWin=24, winSum=406
8946 23:14:49.147648 [TxChooseVref] Worse bit 0, Min win 25, Win sum 429, Final Vref 28
8947 23:14:49.147737
8948 23:14:49.151306 Final TX Range 0 Vref 28
8949 23:14:49.151387
8950 23:14:49.151450 ==
8951 23:14:49.154392 Dram Type= 6, Freq= 0, CH_1, rank 1
8952 23:14:49.157547 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8953 23:14:49.157629 ==
8954 23:14:49.157692
8955 23:14:49.157751
8956 23:14:49.161129 TX Vref Scan disable
8957 23:14:49.167992 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8958 23:14:49.168074 == TX Byte 0 ==
8959 23:14:49.171013 u2DelayCellOfst[0]=20 cells (6 PI)
8960 23:14:49.174542 u2DelayCellOfst[1]=10 cells (3 PI)
8961 23:14:49.177470 u2DelayCellOfst[2]=0 cells (0 PI)
8962 23:14:49.180804 u2DelayCellOfst[3]=6 cells (2 PI)
8963 23:14:49.184334 u2DelayCellOfst[4]=10 cells (3 PI)
8964 23:14:49.187370 u2DelayCellOfst[5]=16 cells (5 PI)
8965 23:14:49.190971 u2DelayCellOfst[6]=16 cells (5 PI)
8966 23:14:49.191053 u2DelayCellOfst[7]=6 cells (2 PI)
8967 23:14:49.197777 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8968 23:14:49.200868 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8969 23:14:49.200949 == TX Byte 1 ==
8970 23:14:49.204675 u2DelayCellOfst[8]=0 cells (0 PI)
8971 23:14:49.207618 u2DelayCellOfst[9]=3 cells (1 PI)
8972 23:14:49.211336 u2DelayCellOfst[10]=10 cells (3 PI)
8973 23:14:49.214165 u2DelayCellOfst[11]=3 cells (1 PI)
8974 23:14:49.217845 u2DelayCellOfst[12]=13 cells (4 PI)
8975 23:14:49.220722 u2DelayCellOfst[13]=16 cells (5 PI)
8976 23:14:49.224072 u2DelayCellOfst[14]=16 cells (5 PI)
8977 23:14:49.227431 u2DelayCellOfst[15]=16 cells (5 PI)
8978 23:14:49.230960 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8979 23:14:49.234253 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8980 23:14:49.237675 DramC Write-DBI on
8981 23:14:49.237779 ==
8982 23:14:49.240731 Dram Type= 6, Freq= 0, CH_1, rank 1
8983 23:14:49.244032 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8984 23:14:49.244142 ==
8985 23:14:49.244251
8986 23:14:49.247697
8987 23:14:49.247777 TX Vref Scan disable
8988 23:14:49.250982 == TX Byte 0 ==
8989 23:14:49.253941 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8990 23:14:49.257461 == TX Byte 1 ==
8991 23:14:49.261010 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8992 23:14:49.261092 DramC Write-DBI off
8993 23:14:49.261156
8994 23:14:49.264108 [DATLAT]
8995 23:14:49.264188 Freq=1600, CH1 RK1
8996 23:14:49.264253
8997 23:14:49.267850 DATLAT Default: 0xf
8998 23:14:49.267931 0, 0xFFFF, sum = 0
8999 23:14:49.270899 1, 0xFFFF, sum = 0
9000 23:14:49.270981 2, 0xFFFF, sum = 0
9001 23:14:49.273947 3, 0xFFFF, sum = 0
9002 23:14:49.274031 4, 0xFFFF, sum = 0
9003 23:14:49.277647 5, 0xFFFF, sum = 0
9004 23:14:49.280749 6, 0xFFFF, sum = 0
9005 23:14:49.280871 7, 0xFFFF, sum = 0
9006 23:14:49.283780 8, 0xFFFF, sum = 0
9007 23:14:49.283902 9, 0xFFFF, sum = 0
9008 23:14:49.287508 10, 0xFFFF, sum = 0
9009 23:14:49.287608 11, 0xFFFF, sum = 0
9010 23:14:49.290781 12, 0xFFFF, sum = 0
9011 23:14:49.290862 13, 0xFFFF, sum = 0
9012 23:14:49.294094 14, 0x0, sum = 1
9013 23:14:49.294176 15, 0x0, sum = 2
9014 23:14:49.297335 16, 0x0, sum = 3
9015 23:14:49.297418 17, 0x0, sum = 4
9016 23:14:49.300648 best_step = 15
9017 23:14:49.300730
9018 23:14:49.300794 ==
9019 23:14:49.303739 Dram Type= 6, Freq= 0, CH_1, rank 1
9020 23:14:49.307159 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9021 23:14:49.307241 ==
9022 23:14:49.307306 RX Vref Scan: 0
9023 23:14:49.310926
9024 23:14:49.311007 RX Vref 0 -> 0, step: 1
9025 23:14:49.311070
9026 23:14:49.314084 RX Delay 19 -> 252, step: 4
9027 23:14:49.317285 iDelay=195, Bit 0, Center 138 (91 ~ 186) 96
9028 23:14:49.323666 iDelay=195, Bit 1, Center 130 (83 ~ 178) 96
9029 23:14:49.327346 iDelay=195, Bit 2, Center 122 (71 ~ 174) 104
9030 23:14:49.330336 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
9031 23:14:49.334121 iDelay=195, Bit 4, Center 130 (83 ~ 178) 96
9032 23:14:49.337278 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
9033 23:14:49.340262 iDelay=195, Bit 6, Center 144 (95 ~ 194) 100
9034 23:14:49.347508 iDelay=195, Bit 7, Center 134 (83 ~ 186) 104
9035 23:14:49.350763 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
9036 23:14:49.353989 iDelay=195, Bit 9, Center 120 (67 ~ 174) 108
9037 23:14:49.357296 iDelay=195, Bit 10, Center 132 (83 ~ 182) 100
9038 23:14:49.360425 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
9039 23:14:49.367249 iDelay=195, Bit 12, Center 140 (87 ~ 194) 108
9040 23:14:49.370484 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
9041 23:14:49.373852 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
9042 23:14:49.376857 iDelay=195, Bit 15, Center 138 (87 ~ 190) 104
9043 23:14:49.376939 ==
9044 23:14:49.380261 Dram Type= 6, Freq= 0, CH_1, rank 1
9045 23:14:49.387260 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9046 23:14:49.387343 ==
9047 23:14:49.387407 DQS Delay:
9048 23:14:49.390172 DQS0 = 0, DQS1 = 0
9049 23:14:49.390253 DQM Delay:
9050 23:14:49.390317 DQM0 = 134, DQM1 = 130
9051 23:14:49.393285 DQ Delay:
9052 23:14:49.396950 DQ0 =138, DQ1 =130, DQ2 =122, DQ3 =130
9053 23:14:49.400001 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =134
9054 23:14:49.403517 DQ8 =116, DQ9 =120, DQ10 =132, DQ11 =124
9055 23:14:49.407010 DQ12 =140, DQ13 =138, DQ14 =136, DQ15 =138
9056 23:14:49.407091
9057 23:14:49.407154
9058 23:14:49.407212
9059 23:14:49.410356 [DramC_TX_OE_Calibration] TA2
9060 23:14:49.413856 Original DQ_B0 (3 6) =30, OEN = 27
9061 23:14:49.417236 Original DQ_B1 (3 6) =30, OEN = 27
9062 23:14:49.420233 24, 0x0, End_B0=24 End_B1=24
9063 23:14:49.420337 25, 0x0, End_B0=25 End_B1=25
9064 23:14:49.423775 26, 0x0, End_B0=26 End_B1=26
9065 23:14:49.426741 27, 0x0, End_B0=27 End_B1=27
9066 23:14:49.430340 28, 0x0, End_B0=28 End_B1=28
9067 23:14:49.433466 29, 0x0, End_B0=29 End_B1=29
9068 23:14:49.433548 30, 0x0, End_B0=30 End_B1=30
9069 23:14:49.437046 31, 0x4545, End_B0=30 End_B1=30
9070 23:14:49.440030 Byte0 end_step=30 best_step=27
9071 23:14:49.443202 Byte1 end_step=30 best_step=27
9072 23:14:49.446815 Byte0 TX OE(2T, 0.5T) = (3, 3)
9073 23:14:49.449957 Byte1 TX OE(2T, 0.5T) = (3, 3)
9074 23:14:49.450038
9075 23:14:49.450100
9076 23:14:49.456619 [DQSOSCAuto] RK1, (LSB)MR18= 0x2106, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 393 ps
9077 23:14:49.459995 CH1 RK1: MR19=303, MR18=2106
9078 23:14:49.466654 CH1_RK1: MR19=0x303, MR18=0x2106, DQSOSC=393, MR23=63, INC=23, DEC=15
9079 23:14:49.470339 [RxdqsGatingPostProcess] freq 1600
9080 23:14:49.473429 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9081 23:14:49.476609 best DQS0 dly(2T, 0.5T) = (1, 1)
9082 23:14:49.480257 best DQS1 dly(2T, 0.5T) = (1, 1)
9083 23:14:49.483411 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9084 23:14:49.486532 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9085 23:14:49.490070 best DQS0 dly(2T, 0.5T) = (1, 1)
9086 23:14:49.493349 best DQS1 dly(2T, 0.5T) = (1, 1)
9087 23:14:49.496387 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9088 23:14:49.500004 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9089 23:14:49.503725 Pre-setting of DQS Precalculation
9090 23:14:49.506698 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9091 23:14:49.513677 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9092 23:14:49.520117 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9093 23:14:49.520238
9094 23:14:49.523731
9095 23:14:49.523850 [Calibration Summary] 3200 Mbps
9096 23:14:49.526792 CH 0, Rank 0
9097 23:14:49.526912 SW Impedance : PASS
9098 23:14:49.530066 DUTY Scan : NO K
9099 23:14:49.533716 ZQ Calibration : PASS
9100 23:14:49.533796 Jitter Meter : NO K
9101 23:14:49.536551 CBT Training : PASS
9102 23:14:49.539941 Write leveling : PASS
9103 23:14:49.540047 RX DQS gating : PASS
9104 23:14:49.543562 RX DQ/DQS(RDDQC) : PASS
9105 23:14:49.546634 TX DQ/DQS : PASS
9106 23:14:49.546715 RX DATLAT : PASS
9107 23:14:49.550375 RX DQ/DQS(Engine): PASS
9108 23:14:49.553432 TX OE : PASS
9109 23:14:49.553513 All Pass.
9110 23:14:49.553577
9111 23:14:49.553635 CH 0, Rank 1
9112 23:14:49.557030 SW Impedance : PASS
9113 23:14:49.557110 DUTY Scan : NO K
9114 23:14:49.560141 ZQ Calibration : PASS
9115 23:14:49.563184 Jitter Meter : NO K
9116 23:14:49.563265 CBT Training : PASS
9117 23:14:49.566732 Write leveling : PASS
9118 23:14:49.570045 RX DQS gating : PASS
9119 23:14:49.570151 RX DQ/DQS(RDDQC) : PASS
9120 23:14:49.573543 TX DQ/DQS : PASS
9121 23:14:49.576952 RX DATLAT : PASS
9122 23:14:49.577048 RX DQ/DQS(Engine): PASS
9123 23:14:49.580012 TX OE : PASS
9124 23:14:49.580094 All Pass.
9125 23:14:49.580159
9126 23:14:49.583163 CH 1, Rank 0
9127 23:14:49.583245 SW Impedance : PASS
9128 23:14:49.586744 DUTY Scan : NO K
9129 23:14:49.589852 ZQ Calibration : PASS
9130 23:14:49.589935 Jitter Meter : NO K
9131 23:14:49.593286 CBT Training : PASS
9132 23:14:49.596304 Write leveling : PASS
9133 23:14:49.596401 RX DQS gating : PASS
9134 23:14:49.599922 RX DQ/DQS(RDDQC) : PASS
9135 23:14:49.603083 TX DQ/DQS : PASS
9136 23:14:49.603166 RX DATLAT : PASS
9137 23:14:49.606428 RX DQ/DQS(Engine): PASS
9138 23:14:49.606512 TX OE : PASS
9139 23:14:49.609708 All Pass.
9140 23:14:49.609790
9141 23:14:49.609854 CH 1, Rank 1
9142 23:14:49.612901 SW Impedance : PASS
9143 23:14:49.612983 DUTY Scan : NO K
9144 23:14:49.616530 ZQ Calibration : PASS
9145 23:14:49.619686 Jitter Meter : NO K
9146 23:14:49.619773 CBT Training : PASS
9147 23:14:49.622812 Write leveling : PASS
9148 23:14:49.626353 RX DQS gating : PASS
9149 23:14:49.626451 RX DQ/DQS(RDDQC) : PASS
9150 23:14:49.630075 TX DQ/DQS : PASS
9151 23:14:49.633163 RX DATLAT : PASS
9152 23:14:49.633250 RX DQ/DQS(Engine): PASS
9153 23:14:49.636607 TX OE : PASS
9154 23:14:49.636689 All Pass.
9155 23:14:49.636752
9156 23:14:49.639589 DramC Write-DBI on
9157 23:14:49.643289 PER_BANK_REFRESH: Hybrid Mode
9158 23:14:49.643372 TX_TRACKING: ON
9159 23:14:49.653235 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9160 23:14:49.659951 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9161 23:14:49.666744 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9162 23:14:49.669753 [FAST_K] Save calibration result to emmc
9163 23:14:49.672823 sync common calibartion params.
9164 23:14:49.676542 sync cbt_mode0:1, 1:1
9165 23:14:49.680119 dram_init: ddr_geometry: 2
9166 23:14:49.680227 dram_init: ddr_geometry: 2
9167 23:14:49.683174 dram_init: ddr_geometry: 2
9168 23:14:49.686559 0:dram_rank_size:100000000
9169 23:14:49.686642 1:dram_rank_size:100000000
9170 23:14:49.692816 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9171 23:14:49.696549 DFS_SHUFFLE_HW_MODE: ON
9172 23:14:49.699617 dramc_set_vcore_voltage set vcore to 725000
9173 23:14:49.703244 Read voltage for 1600, 0
9174 23:14:49.703335 Vio18 = 0
9175 23:14:49.703399 Vcore = 725000
9176 23:14:49.706331 Vdram = 0
9177 23:14:49.706412 Vddq = 0
9178 23:14:49.706475 Vmddr = 0
9179 23:14:49.709548 switch to 3200 Mbps bootup
9180 23:14:49.709631 [DramcRunTimeConfig]
9181 23:14:49.713182 PHYPLL
9182 23:14:49.713267 DPM_CONTROL_AFTERK: ON
9183 23:14:49.716210 PER_BANK_REFRESH: ON
9184 23:14:49.719506 REFRESH_OVERHEAD_REDUCTION: ON
9185 23:14:49.719587 CMD_PICG_NEW_MODE: OFF
9186 23:14:49.722768 XRTWTW_NEW_MODE: ON
9187 23:14:49.722852 XRTRTR_NEW_MODE: ON
9188 23:14:49.725966 TX_TRACKING: ON
9189 23:14:49.726049 RDSEL_TRACKING: OFF
9190 23:14:49.729298 DQS Precalculation for DVFS: ON
9191 23:14:49.732524 RX_TRACKING: OFF
9192 23:14:49.732606 HW_GATING DBG: ON
9193 23:14:49.735989 ZQCS_ENABLE_LP4: ON
9194 23:14:49.736097 RX_PICG_NEW_MODE: ON
9195 23:14:49.739201 TX_PICG_NEW_MODE: ON
9196 23:14:49.742492 ENABLE_RX_DCM_DPHY: ON
9197 23:14:49.745844 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9198 23:14:49.745924 DUMMY_READ_FOR_TRACKING: OFF
9199 23:14:49.749221 !!! SPM_CONTROL_AFTERK: OFF
9200 23:14:49.752502 !!! SPM could not control APHY
9201 23:14:49.752583 IMPEDANCE_TRACKING: ON
9202 23:14:49.755536 TEMP_SENSOR: ON
9203 23:14:49.755620 HW_SAVE_FOR_SR: OFF
9204 23:14:49.759018 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9205 23:14:49.762672 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9206 23:14:49.765973 Read ODT Tracking: ON
9207 23:14:49.768967 Refresh Rate DeBounce: ON
9208 23:14:49.769051 DFS_NO_QUEUE_FLUSH: ON
9209 23:14:49.772680 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9210 23:14:49.776171 ENABLE_DFS_RUNTIME_MRW: OFF
9211 23:14:49.779217 DDR_RESERVE_NEW_MODE: ON
9212 23:14:49.779299 MR_CBT_SWITCH_FREQ: ON
9213 23:14:49.782226 =========================
9214 23:14:49.801732 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9215 23:14:49.804763 dram_init: ddr_geometry: 2
9216 23:14:49.823077 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9217 23:14:49.826731 dram_init: dram init end (result: 0)
9218 23:14:49.833452 DRAM-K: Full calibration passed in 24492 msecs
9219 23:14:49.836741 MRC: failed to locate region type 0.
9220 23:14:49.836856 DRAM rank0 size:0x100000000,
9221 23:14:49.839989 DRAM rank1 size=0x100000000
9222 23:14:49.849988 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9223 23:14:49.856785 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9224 23:14:49.863548 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9225 23:14:49.869705 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9226 23:14:49.873093 DRAM rank0 size:0x100000000,
9227 23:14:49.876710 DRAM rank1 size=0x100000000
9228 23:14:49.876791 CBMEM:
9229 23:14:49.880079 IMD: root @ 0xfffff000 254 entries.
9230 23:14:49.883010 IMD: root @ 0xffffec00 62 entries.
9231 23:14:49.886217 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9232 23:14:49.889958 WARNING: RO_VPD is uninitialized or empty.
9233 23:14:49.896691 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9234 23:14:49.902952 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9235 23:14:49.916239 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9236 23:14:49.927699 BS: romstage times (exec / console): total (unknown) / 24021 ms
9237 23:14:49.927811
9238 23:14:49.927877
9239 23:14:49.937733 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9240 23:14:49.940846 ARM64: Exception handlers installed.
9241 23:14:49.943910 ARM64: Testing exception
9242 23:14:49.947723 ARM64: Done test exception
9243 23:14:49.947827 Enumerating buses...
9244 23:14:49.951054 Show all devs... Before device enumeration.
9245 23:14:49.953900 Root Device: enabled 1
9246 23:14:49.957041 CPU_CLUSTER: 0: enabled 1
9247 23:14:49.957130 CPU: 00: enabled 1
9248 23:14:49.960477 Compare with tree...
9249 23:14:49.960585 Root Device: enabled 1
9250 23:14:49.963923 CPU_CLUSTER: 0: enabled 1
9251 23:14:49.966930 CPU: 00: enabled 1
9252 23:14:49.967016 Root Device scanning...
9253 23:14:49.970569 scan_static_bus for Root Device
9254 23:14:49.973473 CPU_CLUSTER: 0 enabled
9255 23:14:49.976875 scan_static_bus for Root Device done
9256 23:14:49.980315 scan_bus: bus Root Device finished in 8 msecs
9257 23:14:49.980414 done
9258 23:14:49.987484 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9259 23:14:49.990216 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9260 23:14:49.997205 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9261 23:14:50.000076 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9262 23:14:50.003664 Allocating resources...
9263 23:14:50.006961 Reading resources...
9264 23:14:50.010045 Root Device read_resources bus 0 link: 0
9265 23:14:50.010143 DRAM rank0 size:0x100000000,
9266 23:14:50.013527 DRAM rank1 size=0x100000000
9267 23:14:50.016439 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9268 23:14:50.020099 CPU: 00 missing read_resources
9269 23:14:50.026938 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9270 23:14:50.030053 Root Device read_resources bus 0 link: 0 done
9271 23:14:50.030154 Done reading resources.
9272 23:14:50.036156 Show resources in subtree (Root Device)...After reading.
9273 23:14:50.039829 Root Device child on link 0 CPU_CLUSTER: 0
9274 23:14:50.042969 CPU_CLUSTER: 0 child on link 0 CPU: 00
9275 23:14:50.052905 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9276 23:14:50.053042 CPU: 00
9277 23:14:50.056577 Root Device assign_resources, bus 0 link: 0
9278 23:14:50.059474 CPU_CLUSTER: 0 missing set_resources
9279 23:14:50.066286 Root Device assign_resources, bus 0 link: 0 done
9280 23:14:50.066372 Done setting resources.
9281 23:14:50.072988 Show resources in subtree (Root Device)...After assigning values.
9282 23:14:50.076466 Root Device child on link 0 CPU_CLUSTER: 0
9283 23:14:50.079396 CPU_CLUSTER: 0 child on link 0 CPU: 00
9284 23:14:50.089683 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9285 23:14:50.089776 CPU: 00
9286 23:14:50.092977 Done allocating resources.
9287 23:14:50.099600 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9288 23:14:50.099683 Enabling resources...
9289 23:14:50.099747 done.
9290 23:14:50.106084 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9291 23:14:50.106165 Initializing devices...
9292 23:14:50.109272 Root Device init
9293 23:14:50.112979 init hardware done!
9294 23:14:50.113062 0x00000018: ctrlr->caps
9295 23:14:50.116339 52.000 MHz: ctrlr->f_max
9296 23:14:50.116440 0.400 MHz: ctrlr->f_min
9297 23:14:50.119466 0x40ff8080: ctrlr->voltages
9298 23:14:50.122701 sclk: 390625
9299 23:14:50.122791 Bus Width = 1
9300 23:14:50.122855 sclk: 390625
9301 23:14:50.126241 Bus Width = 1
9302 23:14:50.126326 Early init status = 3
9303 23:14:50.132777 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9304 23:14:50.136177 in-header: 03 fc 00 00 01 00 00 00
9305 23:14:50.139177 in-data: 00
9306 23:14:50.142971 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9307 23:14:50.145972 in-header: 03 fd 00 00 00 00 00 00
9308 23:14:50.149505 in-data:
9309 23:14:50.152581 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9310 23:14:50.156264 in-header: 03 fc 00 00 01 00 00 00
9311 23:14:50.159499 in-data: 00
9312 23:14:50.163020 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9313 23:14:50.168359 in-header: 03 fd 00 00 00 00 00 00
9314 23:14:50.171681 in-data:
9315 23:14:50.175000 [SSUSB] Setting up USB HOST controller...
9316 23:14:50.177820 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9317 23:14:50.181677 [SSUSB] phy power-on done.
9318 23:14:50.184917 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9319 23:14:50.191497 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9320 23:14:50.195010 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9321 23:14:50.201484 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9322 23:14:50.208110 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9323 23:14:50.214343 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9324 23:14:50.221435 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9325 23:14:50.227622 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9326 23:14:50.231008 SPM: binary array size = 0x9dc
9327 23:14:50.234650 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9328 23:14:50.241367 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9329 23:14:50.247755 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9330 23:14:50.251291 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9331 23:14:50.257535 configure_display: Starting display init
9332 23:14:50.291537 anx7625_power_on_init: Init interface.
9333 23:14:50.294763 anx7625_disable_pd_protocol: Disabled PD feature.
9334 23:14:50.298120 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9335 23:14:50.325621 anx7625_start_dp_work: Secure OCM version=00
9336 23:14:50.329343 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9337 23:14:50.344198 sp_tx_get_edid_block: EDID Block = 1
9338 23:14:50.446343 Extracted contents:
9339 23:14:50.449725 header: 00 ff ff ff ff ff ff 00
9340 23:14:50.453105 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9341 23:14:50.456593 version: 01 04
9342 23:14:50.459657 basic params: 95 1f 11 78 0a
9343 23:14:50.463262 chroma info: 76 90 94 55 54 90 27 21 50 54
9344 23:14:50.466448 established: 00 00 00
9345 23:14:50.473096 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9346 23:14:50.476217 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9347 23:14:50.483075 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9348 23:14:50.489300 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9349 23:14:50.496179 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9350 23:14:50.499619 extensions: 00
9351 23:14:50.499738 checksum: fb
9352 23:14:50.499848
9353 23:14:50.502832 Manufacturer: IVO Model 57d Serial Number 0
9354 23:14:50.506352 Made week 0 of 2020
9355 23:14:50.506470 EDID version: 1.4
9356 23:14:50.509279 Digital display
9357 23:14:50.512647 6 bits per primary color channel
9358 23:14:50.512767 DisplayPort interface
9359 23:14:50.515986 Maximum image size: 31 cm x 17 cm
9360 23:14:50.519799 Gamma: 220%
9361 23:14:50.519900 Check DPMS levels
9362 23:14:50.523015 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9363 23:14:50.526438 First detailed timing is preferred timing
9364 23:14:50.529350 Established timings supported:
9365 23:14:50.532865 Standard timings supported:
9366 23:14:50.532943 Detailed timings
9367 23:14:50.539560 Hex of detail: 383680a07038204018303c0035ae10000019
9368 23:14:50.542566 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9369 23:14:50.549345 0780 0798 07c8 0820 hborder 0
9370 23:14:50.552565 0438 043b 0447 0458 vborder 0
9371 23:14:50.555916 -hsync -vsync
9372 23:14:50.555998 Did detailed timing
9373 23:14:50.559625 Hex of detail: 000000000000000000000000000000000000
9374 23:14:50.562965 Manufacturer-specified data, tag 0
9375 23:14:50.569028 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9376 23:14:50.569137 ASCII string: InfoVision
9377 23:14:50.576166 Hex of detail: 000000fe00523134304e574635205248200a
9378 23:14:50.579494 ASCII string: R140NWF5 RH
9379 23:14:50.579573 Checksum
9380 23:14:50.579635 Checksum: 0xfb (valid)
9381 23:14:50.585882 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9382 23:14:50.588946 DSI data_rate: 832800000 bps
9383 23:14:50.592599 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9384 23:14:50.599234 anx7625_parse_edid: pixelclock(138800).
9385 23:14:50.602240 hactive(1920), hsync(48), hfp(24), hbp(88)
9386 23:14:50.605523 vactive(1080), vsync(12), vfp(3), vbp(17)
9387 23:14:50.609202 anx7625_dsi_config: config dsi.
9388 23:14:50.615242 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9389 23:14:50.628522 anx7625_dsi_config: success to config DSI
9390 23:14:50.631763 anx7625_dp_start: MIPI phy setup OK.
9391 23:14:50.635064 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9392 23:14:50.638298 mtk_ddp_mode_set invalid vrefresh 60
9393 23:14:50.641779 main_disp_path_setup
9394 23:14:50.641899 ovl_layer_smi_id_en
9395 23:14:50.645294 ovl_layer_smi_id_en
9396 23:14:50.645411 ccorr_config
9397 23:14:50.645519 aal_config
9398 23:14:50.648482 gamma_config
9399 23:14:50.648601 postmask_config
9400 23:14:50.652015 dither_config
9401 23:14:50.655170 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9402 23:14:50.661898 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9403 23:14:50.664863 Root Device init finished in 552 msecs
9404 23:14:50.664984 CPU_CLUSTER: 0 init
9405 23:14:50.675052 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9406 23:14:50.678083 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9407 23:14:50.681804 APU_MBOX 0x190000b0 = 0x10001
9408 23:14:50.684781 APU_MBOX 0x190001b0 = 0x10001
9409 23:14:50.688237 APU_MBOX 0x190005b0 = 0x10001
9410 23:14:50.691456 APU_MBOX 0x190006b0 = 0x10001
9411 23:14:50.694584 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9412 23:14:50.707230 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9413 23:14:50.720022 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9414 23:14:50.726441 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9415 23:14:50.737811 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9416 23:14:50.747187 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9417 23:14:50.750376 CPU_CLUSTER: 0 init finished in 81 msecs
9418 23:14:50.754043 Devices initialized
9419 23:14:50.757058 Show all devs... After init.
9420 23:14:50.757160 Root Device: enabled 1
9421 23:14:50.760743 CPU_CLUSTER: 0: enabled 1
9422 23:14:50.763890 CPU: 00: enabled 1
9423 23:14:50.766884 BS: BS_DEV_INIT run times (exec / console): 210 / 447 ms
9424 23:14:50.770528 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9425 23:14:50.773902 ELOG: NV offset 0x57f000 size 0x1000
9426 23:14:50.780436 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9427 23:14:50.787188 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9428 23:14:50.790938 ELOG: Event(17) added with size 13 at 2023-12-27 23:12:19 UTC
9429 23:14:50.794061 out: cmd=0x121: 03 db 21 01 00 00 00 00
9430 23:14:50.797616 in-header: 03 b9 00 00 2c 00 00 00
9431 23:14:50.810575 in-data: a6 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9432 23:14:50.817542 ELOG: Event(A1) added with size 10 at 2023-12-27 23:12:19 UTC
9433 23:14:50.824226 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9434 23:14:50.830808 ELOG: Event(A0) added with size 9 at 2023-12-27 23:12:19 UTC
9435 23:14:50.834284 elog_add_boot_reason: Logged dev mode boot
9436 23:14:50.837448 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9437 23:14:50.840885 Finalize devices...
9438 23:14:50.840991 Devices finalized
9439 23:14:50.847503 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9440 23:14:50.851087 Writing coreboot table at 0xffe64000
9441 23:14:50.854301 0. 000000000010a000-0000000000113fff: RAMSTAGE
9442 23:14:50.857158 1. 0000000040000000-00000000400fffff: RAM
9443 23:14:50.860568 2. 0000000040100000-000000004032afff: RAMSTAGE
9444 23:14:50.867328 3. 000000004032b000-00000000545fffff: RAM
9445 23:14:50.870578 4. 0000000054600000-000000005465ffff: BL31
9446 23:14:50.874215 5. 0000000054660000-00000000ffe63fff: RAM
9447 23:14:50.880871 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9448 23:14:50.884194 7. 0000000100000000-000000023fffffff: RAM
9449 23:14:50.884276 Passing 5 GPIOs to payload:
9450 23:14:50.890723 NAME | PORT | POLARITY | VALUE
9451 23:14:50.893825 EC in RW | 0x000000aa | low | undefined
9452 23:14:50.900622 EC interrupt | 0x00000005 | low | undefined
9453 23:14:50.903699 TPM interrupt | 0x000000ab | high | undefined
9454 23:14:50.907235 SD card detect | 0x00000011 | high | undefined
9455 23:14:50.913456 speaker enable | 0x00000093 | high | undefined
9456 23:14:50.916901 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9457 23:14:50.920275 in-header: 03 f9 00 00 02 00 00 00
9458 23:14:50.920382 in-data: 02 00
9459 23:14:50.923533 ADC[4]: Raw value=904726 ID=7
9460 23:14:50.927185 ADC[3]: Raw value=213441 ID=1
9461 23:14:50.927265 RAM Code: 0x71
9462 23:14:50.930197 ADC[6]: Raw value=75332 ID=0
9463 23:14:50.933637 ADC[5]: Raw value=213072 ID=1
9464 23:14:50.933736 SKU Code: 0x1
9465 23:14:50.940488 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 9315
9466 23:14:50.943373 coreboot table: 964 bytes.
9467 23:14:50.947098 IMD ROOT 0. 0xfffff000 0x00001000
9468 23:14:50.950130 IMD SMALL 1. 0xffffe000 0x00001000
9469 23:14:50.953762 RO MCACHE 2. 0xffffc000 0x00001104
9470 23:14:50.956903 CONSOLE 3. 0xfff7c000 0x00080000
9471 23:14:50.960426 FMAP 4. 0xfff7b000 0x00000452
9472 23:14:50.963711 TIME STAMP 5. 0xfff7a000 0x00000910
9473 23:14:50.967125 VBOOT WORK 6. 0xfff66000 0x00014000
9474 23:14:50.970420 RAMOOPS 7. 0xffe66000 0x00100000
9475 23:14:50.973402 COREBOOT 8. 0xffe64000 0x00002000
9476 23:14:50.973483 IMD small region:
9477 23:14:50.977248 IMD ROOT 0. 0xffffec00 0x00000400
9478 23:14:50.980402 VPD 1. 0xffffeb80 0x0000006c
9479 23:14:50.983557 MMC STATUS 2. 0xffffeb60 0x00000004
9480 23:14:50.990354 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9481 23:14:50.993801 Probing TPM: done!
9482 23:14:50.996758 Connected to device vid:did:rid of 1ae0:0028:00
9483 23:14:51.006926 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9484 23:14:51.010593 Initialized TPM device CR50 revision 0
9485 23:14:51.013728 Checking cr50 for pending updates
9486 23:14:51.017479 Reading cr50 TPM mode
9487 23:14:51.025982 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9488 23:14:51.032531 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9489 23:14:51.072159 read SPI 0x3990ec 0x4f1b0: 34851 us, 9297 KB/s, 74.376 Mbps
9490 23:14:51.075506 Checking segment from ROM address 0x40100000
9491 23:14:51.079091 Checking segment from ROM address 0x4010001c
9492 23:14:51.085994 Loading segment from ROM address 0x40100000
9493 23:14:51.086117 code (compression=0)
9494 23:14:51.092170 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9495 23:14:51.102475 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9496 23:14:51.102600 it's not compressed!
9497 23:14:51.109093 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9498 23:14:51.112246 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9499 23:14:51.132776 Loading segment from ROM address 0x4010001c
9500 23:14:51.132902 Entry Point 0x80000000
9501 23:14:51.136511 Loaded segments
9502 23:14:51.139531 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9503 23:14:51.146222 Jumping to boot code at 0x80000000(0xffe64000)
9504 23:14:51.152772 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9505 23:14:51.159607 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9506 23:14:51.167227 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9507 23:14:51.170691 Checking segment from ROM address 0x40100000
9508 23:14:51.174198 Checking segment from ROM address 0x4010001c
9509 23:14:51.180863 Loading segment from ROM address 0x40100000
9510 23:14:51.180986 code (compression=1)
9511 23:14:51.187418 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9512 23:14:51.197443 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9513 23:14:51.197572 using LZMA
9514 23:14:51.205939 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9515 23:14:51.212750 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9516 23:14:51.215704 Loading segment from ROM address 0x4010001c
9517 23:14:51.215823 Entry Point 0x54601000
9518 23:14:51.219305 Loaded segments
9519 23:14:51.222094 NOTICE: MT8192 bl31_setup
9520 23:14:51.229517 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9521 23:14:51.232664 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9522 23:14:51.236105 WARNING: region 0:
9523 23:14:51.239230 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9524 23:14:51.239311 WARNING: region 1:
9525 23:14:51.246234 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9526 23:14:51.249628 WARNING: region 2:
9527 23:14:51.252667 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9528 23:14:51.255764 WARNING: region 3:
9529 23:14:51.259332 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9530 23:14:51.262652 WARNING: region 4:
9531 23:14:51.266192 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9532 23:14:51.269278 WARNING: region 5:
9533 23:14:51.272898 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9534 23:14:51.275783 WARNING: region 6:
9535 23:14:51.279259 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9536 23:14:51.279384 WARNING: region 7:
9537 23:14:51.286131 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9538 23:14:51.292885 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9539 23:14:51.296216 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9540 23:14:51.299557 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9541 23:14:51.306238 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9542 23:14:51.309535 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9543 23:14:51.312824 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9544 23:14:51.319285 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9545 23:14:51.322893 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9546 23:14:51.326012 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9547 23:14:51.332624 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9548 23:14:51.336384 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9549 23:14:51.342652 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9550 23:14:51.345833 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9551 23:14:51.349708 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9552 23:14:51.356126 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9553 23:14:51.359167 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9554 23:14:51.362941 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9555 23:14:51.369664 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9556 23:14:51.372936 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9557 23:14:51.375829 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9558 23:14:51.383043 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9559 23:14:51.385905 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9560 23:14:51.392621 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9561 23:14:51.396162 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9562 23:14:51.402818 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9563 23:14:51.405966 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9564 23:14:51.409471 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9565 23:14:51.415674 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9566 23:14:51.419459 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9567 23:14:51.422999 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9568 23:14:51.429072 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9569 23:14:51.432826 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9570 23:14:51.439495 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9571 23:14:51.442508 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9572 23:14:51.446030 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9573 23:14:51.449105 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9574 23:14:51.452795 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9575 23:14:51.459262 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9576 23:14:51.462621 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9577 23:14:51.465946 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9578 23:14:51.469623 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9579 23:14:51.475962 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9580 23:14:51.479414 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9581 23:14:51.483089 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9582 23:14:51.486174 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9583 23:14:51.492460 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9584 23:14:51.496249 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9585 23:14:51.499216 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9586 23:14:51.505752 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9587 23:14:51.509524 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9588 23:14:51.516066 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9589 23:14:51.519420 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9590 23:14:51.522591 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9591 23:14:51.529515 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9592 23:14:51.532606 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9593 23:14:51.539077 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9594 23:14:51.542638 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9595 23:14:51.545714 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9596 23:14:51.552524 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9597 23:14:51.556258 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9598 23:14:51.562713 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9599 23:14:51.566017 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9600 23:14:51.572598 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9601 23:14:51.576078 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9602 23:14:51.582938 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9603 23:14:51.586107 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9604 23:14:51.589426 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9605 23:14:51.596537 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9606 23:14:51.599570 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9607 23:14:51.606310 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9608 23:14:51.609810 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9609 23:14:51.612901 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9610 23:14:51.619497 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9611 23:14:51.623096 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9612 23:14:51.629932 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9613 23:14:51.632814 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9614 23:14:51.639640 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9615 23:14:51.643152 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9616 23:14:51.646609 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9617 23:14:51.653628 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9618 23:14:51.656824 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9619 23:14:51.663570 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9620 23:14:51.666591 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9621 23:14:51.673563 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9622 23:14:51.676480 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9623 23:14:51.679981 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9624 23:14:51.686770 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9625 23:14:51.689957 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9626 23:14:51.696609 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9627 23:14:51.700141 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9628 23:14:51.706619 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9629 23:14:51.709716 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9630 23:14:51.713167 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9631 23:14:51.719960 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9632 23:14:51.723789 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9633 23:14:51.729906 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9634 23:14:51.733605 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9635 23:14:51.736720 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9636 23:14:51.740264 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9637 23:14:51.747117 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9638 23:14:51.750012 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9639 23:14:51.753518 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9640 23:14:51.760569 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9641 23:14:51.763285 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9642 23:14:51.770326 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9643 23:14:51.773512 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9644 23:14:51.776609 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9645 23:14:51.783676 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9646 23:14:51.787190 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9647 23:14:51.793981 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9648 23:14:51.796953 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9649 23:14:51.800128 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9650 23:14:51.807043 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9651 23:14:51.810052 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9652 23:14:51.817333 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9653 23:14:51.820157 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9654 23:14:51.823602 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9655 23:14:51.827328 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9656 23:14:51.833425 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9657 23:14:51.836854 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9658 23:14:51.840608 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9659 23:14:51.843919 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9660 23:14:51.850280 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9661 23:14:51.854027 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9662 23:14:51.857137 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9663 23:14:51.863821 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9664 23:14:51.867399 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9665 23:14:51.870595 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9666 23:14:51.877290 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9667 23:14:51.880167 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9668 23:14:51.887485 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9669 23:14:51.890428 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9670 23:14:51.894061 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9671 23:14:51.900650 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9672 23:14:51.903856 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9673 23:14:51.910940 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9674 23:14:51.913953 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9675 23:14:51.917593 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9676 23:14:51.923788 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9677 23:14:51.927580 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9678 23:14:51.930402 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9679 23:14:51.937389 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9680 23:14:51.940600 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9681 23:14:51.947141 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9682 23:14:51.950483 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9683 23:14:51.953979 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9684 23:14:51.960490 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9685 23:14:51.963942 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9686 23:14:51.970870 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9687 23:14:51.973870 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9688 23:14:51.977415 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9689 23:14:51.983796 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9690 23:14:51.987544 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9691 23:14:51.990733 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9692 23:14:51.997173 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9693 23:14:52.000600 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9694 23:14:52.006959 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9695 23:14:52.010604 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9696 23:14:52.014078 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9697 23:14:52.020865 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9698 23:14:52.023719 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9699 23:14:52.030536 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9700 23:14:52.033668 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9701 23:14:52.037355 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9702 23:14:52.044158 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9703 23:14:52.047071 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9704 23:14:52.050698 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9705 23:14:52.057274 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9706 23:14:52.060489 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9707 23:14:52.067218 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9708 23:14:52.070353 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9709 23:14:52.076849 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9710 23:14:52.080085 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9711 23:14:52.083369 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9712 23:14:52.090225 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9713 23:14:52.093481 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9714 23:14:52.097006 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9715 23:14:52.103241 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9716 23:14:52.106764 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9717 23:14:52.113383 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9718 23:14:52.116757 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9719 23:14:52.119975 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9720 23:14:52.126361 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9721 23:14:52.129995 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9722 23:14:52.136687 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9723 23:14:52.139653 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9724 23:14:52.143436 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9725 23:14:52.150114 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9726 23:14:52.153121 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9727 23:14:52.160243 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9728 23:14:52.163269 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9729 23:14:52.166257 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9730 23:14:52.173297 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9731 23:14:52.176228 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9732 23:14:52.183302 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9733 23:14:52.186180 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9734 23:14:52.189526 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9735 23:14:52.196144 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9736 23:14:52.199737 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9737 23:14:52.206507 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9738 23:14:52.209470 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9739 23:14:52.216129 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9740 23:14:52.219810 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9741 23:14:52.223030 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9742 23:14:52.229295 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9743 23:14:52.232524 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9744 23:14:52.239296 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9745 23:14:52.243057 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9746 23:14:52.246353 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9747 23:14:52.252548 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9748 23:14:52.256022 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9749 23:14:52.262681 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9750 23:14:52.265755 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9751 23:14:52.272462 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9752 23:14:52.276117 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9753 23:14:52.279283 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9754 23:14:52.286025 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9755 23:14:52.289018 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9756 23:14:52.295881 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9757 23:14:52.298968 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9758 23:14:52.305946 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9759 23:14:52.309052 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9760 23:14:52.312580 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9761 23:14:52.319269 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9762 23:14:52.322268 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9763 23:14:52.329053 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9764 23:14:52.332765 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9765 23:14:52.335653 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9766 23:14:52.342518 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9767 23:14:52.345899 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9768 23:14:52.349168 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9769 23:14:52.352418 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9770 23:14:52.358921 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9771 23:14:52.362425 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9772 23:14:52.365587 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9773 23:14:52.372172 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9774 23:14:52.375787 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9775 23:14:52.381979 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9776 23:14:52.385618 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9777 23:14:52.388716 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9778 23:14:52.395887 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9779 23:14:52.398805 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9780 23:14:52.402218 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9781 23:14:52.409000 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9782 23:14:52.412110 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9783 23:14:52.415198 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9784 23:14:52.422134 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9785 23:14:52.425718 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9786 23:14:52.428769 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9787 23:14:52.435338 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9788 23:14:52.438476 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9789 23:14:52.445453 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9790 23:14:52.448458 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9791 23:14:52.451987 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9792 23:14:52.458787 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9793 23:14:52.462172 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9794 23:14:52.465634 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9795 23:14:52.471958 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9796 23:14:52.475076 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9797 23:14:52.478592 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9798 23:14:52.485549 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9799 23:14:52.488624 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9800 23:14:52.495360 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9801 23:14:52.498949 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9802 23:14:52.501722 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9803 23:14:52.508511 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9804 23:14:52.512233 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9805 23:14:52.515279 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9806 23:14:52.521984 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9807 23:14:52.525072 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9808 23:14:52.528690 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9809 23:14:52.531653 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9810 23:14:52.538428 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9811 23:14:52.541666 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9812 23:14:52.544835 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9813 23:14:52.548440 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9814 23:14:52.551494 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9815 23:14:52.558311 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9816 23:14:52.561314 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9817 23:14:52.564977 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9818 23:14:52.571780 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9819 23:14:52.574922 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9820 23:14:52.577894 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9821 23:14:52.585020 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9822 23:14:52.588459 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9823 23:14:52.594565 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9824 23:14:52.598478 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9825 23:14:52.601452 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9826 23:14:52.608706 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9827 23:14:52.611474 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9828 23:14:52.618008 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9829 23:14:52.621652 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9830 23:14:52.624711 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9831 23:14:52.631479 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9832 23:14:52.634703 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9833 23:14:52.641310 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9834 23:14:52.644841 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9835 23:14:52.647974 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9836 23:14:52.654448 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9837 23:14:52.657662 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9838 23:14:52.664297 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9839 23:14:52.667866 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9840 23:14:52.674309 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9841 23:14:52.677961 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9842 23:14:52.681543 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9843 23:14:52.687860 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9844 23:14:52.691009 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9845 23:14:52.694564 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9846 23:14:52.701219 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9847 23:14:52.704630 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9848 23:14:52.710976 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9849 23:14:52.714191 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9850 23:14:52.721047 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9851 23:14:52.724336 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9852 23:14:52.728010 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9853 23:14:52.734220 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9854 23:14:52.737789 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9855 23:14:52.744508 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9856 23:14:52.747352 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9857 23:14:52.751042 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9858 23:14:52.757813 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9859 23:14:52.760927 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9860 23:14:52.767434 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9861 23:14:52.770798 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9862 23:14:52.774292 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9863 23:14:52.780883 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9864 23:14:52.784483 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9865 23:14:52.790895 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9866 23:14:52.794204 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9867 23:14:52.797539 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9868 23:14:52.804087 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9869 23:14:52.807579 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9870 23:14:52.814062 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9871 23:14:52.817816 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9872 23:14:52.820801 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9873 23:14:52.827794 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9874 23:14:52.830653 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9875 23:14:52.837437 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9876 23:14:52.841212 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9877 23:14:52.844174 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9878 23:14:52.850736 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9879 23:14:52.854300 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9880 23:14:52.861121 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9881 23:14:52.864320 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9882 23:14:52.870849 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9883 23:14:52.874488 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9884 23:14:52.877357 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9885 23:14:52.884582 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9886 23:14:52.887724 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9887 23:14:52.893923 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9888 23:14:52.897662 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9889 23:14:52.900990 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9890 23:14:52.907363 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9891 23:14:52.911063 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9892 23:14:52.914311 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9893 23:14:52.920828 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9894 23:14:52.924250 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9895 23:14:52.930695 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9896 23:14:52.934262 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9897 23:14:52.940720 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9898 23:14:52.944195 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9899 23:14:52.950931 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9900 23:14:52.953984 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9901 23:14:52.957509 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9902 23:14:52.963631 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9903 23:14:52.967362 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9904 23:14:52.974406 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9905 23:14:52.977258 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9906 23:14:52.983761 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9907 23:14:52.987427 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9908 23:14:52.990436 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9909 23:14:52.997328 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9910 23:14:53.000454 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9911 23:14:53.007365 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9912 23:14:53.010210 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9913 23:14:53.017157 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9914 23:14:53.020034 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9915 23:14:53.023723 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9916 23:14:53.030540 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9917 23:14:53.033565 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9918 23:14:53.040386 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9919 23:14:53.043549 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9920 23:14:53.049944 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9921 23:14:53.053310 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9922 23:14:53.060399 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9923 23:14:53.063486 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9924 23:14:53.066530 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9925 23:14:53.073391 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9926 23:14:53.077075 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9927 23:14:53.083187 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9928 23:14:53.086644 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9929 23:14:53.093190 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9930 23:14:53.096766 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9931 23:14:53.099852 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9932 23:14:53.106719 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9933 23:14:53.109869 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9934 23:14:53.116628 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9935 23:14:53.120200 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9936 23:14:53.126849 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9937 23:14:53.129706 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9938 23:14:53.136698 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9939 23:14:53.139846 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9940 23:14:53.143073 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9941 23:14:53.149764 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9942 23:14:53.152957 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9943 23:14:53.159562 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9944 23:14:53.163251 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9945 23:14:53.169768 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9946 23:14:53.172753 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9947 23:14:53.179671 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9948 23:14:53.182777 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9949 23:14:53.189433 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9950 23:14:53.192811 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9951 23:14:53.196269 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9952 23:14:53.202491 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9953 23:14:53.205972 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9954 23:14:53.212798 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9955 23:14:53.216252 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9956 23:14:53.222446 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9957 23:14:53.226156 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9958 23:14:53.232977 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9959 23:14:53.235945 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9960 23:14:53.243000 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9961 23:14:53.245814 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9962 23:14:53.252625 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9963 23:14:53.255716 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9964 23:14:53.262780 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9965 23:14:53.265673 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9966 23:14:53.272857 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9967 23:14:53.276167 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9968 23:14:53.282424 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9969 23:14:53.285772 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9970 23:14:53.292720 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9971 23:14:53.295531 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9972 23:14:53.302471 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9973 23:14:53.302549 INFO: [APUAPC] vio 0
9974 23:14:53.309089 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9975 23:14:53.312789 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9976 23:14:53.315971 INFO: [APUAPC] D0_APC_0: 0x400510
9977 23:14:53.318903 INFO: [APUAPC] D0_APC_1: 0x0
9978 23:14:53.322790 INFO: [APUAPC] D0_APC_2: 0x1540
9979 23:14:53.325791 INFO: [APUAPC] D0_APC_3: 0x0
9980 23:14:53.328790 INFO: [APUAPC] D1_APC_0: 0xffffffff
9981 23:14:53.332061 INFO: [APUAPC] D1_APC_1: 0xffffffff
9982 23:14:53.335511 INFO: [APUAPC] D1_APC_2: 0x3fffff
9983 23:14:53.338685 INFO: [APUAPC] D1_APC_3: 0x0
9984 23:14:53.342354 INFO: [APUAPC] D2_APC_0: 0xffffffff
9985 23:14:53.345847 INFO: [APUAPC] D2_APC_1: 0xffffffff
9986 23:14:53.348943 INFO: [APUAPC] D2_APC_2: 0x3fffff
9987 23:14:53.352095 INFO: [APUAPC] D2_APC_3: 0x0
9988 23:14:53.355618 INFO: [APUAPC] D3_APC_0: 0xffffffff
9989 23:14:53.359014 INFO: [APUAPC] D3_APC_1: 0xffffffff
9990 23:14:53.362268 INFO: [APUAPC] D3_APC_2: 0x3fffff
9991 23:14:53.362349 INFO: [APUAPC] D3_APC_3: 0x0
9992 23:14:53.369110 INFO: [APUAPC] D4_APC_0: 0xffffffff
9993 23:14:53.372133 INFO: [APUAPC] D4_APC_1: 0xffffffff
9994 23:14:53.375591 INFO: [APUAPC] D4_APC_2: 0x3fffff
9995 23:14:53.375673 INFO: [APUAPC] D4_APC_3: 0x0
9996 23:14:53.378796 INFO: [APUAPC] D5_APC_0: 0xffffffff
9997 23:14:53.382174 INFO: [APUAPC] D5_APC_1: 0xffffffff
9998 23:14:53.385869 INFO: [APUAPC] D5_APC_2: 0x3fffff
9999 23:14:53.388949 INFO: [APUAPC] D5_APC_3: 0x0
10000 23:14:53.392419 INFO: [APUAPC] D6_APC_0: 0xffffffff
10001 23:14:53.395806 INFO: [APUAPC] D6_APC_1: 0xffffffff
10002 23:14:53.398940 INFO: [APUAPC] D6_APC_2: 0x3fffff
10003 23:14:53.402301 INFO: [APUAPC] D6_APC_3: 0x0
10004 23:14:53.405671 INFO: [APUAPC] D7_APC_0: 0xffffffff
10005 23:14:53.408809 INFO: [APUAPC] D7_APC_1: 0xffffffff
10006 23:14:53.412134 INFO: [APUAPC] D7_APC_2: 0x3fffff
10007 23:14:53.415683 INFO: [APUAPC] D7_APC_3: 0x0
10008 23:14:53.419145 INFO: [APUAPC] D8_APC_0: 0xffffffff
10009 23:14:53.422141 INFO: [APUAPC] D8_APC_1: 0xffffffff
10010 23:14:53.425785 INFO: [APUAPC] D8_APC_2: 0x3fffff
10011 23:14:53.428824 INFO: [APUAPC] D8_APC_3: 0x0
10012 23:14:53.431938 INFO: [APUAPC] D9_APC_0: 0xffffffff
10013 23:14:53.435552 INFO: [APUAPC] D9_APC_1: 0xffffffff
10014 23:14:53.438677 INFO: [APUAPC] D9_APC_2: 0x3fffff
10015 23:14:53.442468 INFO: [APUAPC] D9_APC_3: 0x0
10016 23:14:53.445348 INFO: [APUAPC] D10_APC_0: 0xffffffff
10017 23:14:53.449029 INFO: [APUAPC] D10_APC_1: 0xffffffff
10018 23:14:53.451979 INFO: [APUAPC] D10_APC_2: 0x3fffff
10019 23:14:53.455128 INFO: [APUAPC] D10_APC_3: 0x0
10020 23:14:53.458794 INFO: [APUAPC] D11_APC_0: 0xffffffff
10021 23:14:53.461843 INFO: [APUAPC] D11_APC_1: 0xffffffff
10022 23:14:53.465457 INFO: [APUAPC] D11_APC_2: 0x3fffff
10023 23:14:53.468312 INFO: [APUAPC] D11_APC_3: 0x0
10024 23:14:53.471842 INFO: [APUAPC] D12_APC_0: 0xffffffff
10025 23:14:53.475208 INFO: [APUAPC] D12_APC_1: 0xffffffff
10026 23:14:53.478601 INFO: [APUAPC] D12_APC_2: 0x3fffff
10027 23:14:53.481798 INFO: [APUAPC] D12_APC_3: 0x0
10028 23:14:53.485159 INFO: [APUAPC] D13_APC_0: 0xffffffff
10029 23:14:53.488443 INFO: [APUAPC] D13_APC_1: 0xffffffff
10030 23:14:53.491684 INFO: [APUAPC] D13_APC_2: 0x3fffff
10031 23:14:53.495317 INFO: [APUAPC] D13_APC_3: 0x0
10032 23:14:53.498312 INFO: [APUAPC] D14_APC_0: 0xffffffff
10033 23:14:53.502167 INFO: [APUAPC] D14_APC_1: 0xffffffff
10034 23:14:53.505123 INFO: [APUAPC] D14_APC_2: 0x3fffff
10035 23:14:53.508746 INFO: [APUAPC] D14_APC_3: 0x0
10036 23:14:53.511560 INFO: [APUAPC] D15_APC_0: 0xffffffff
10037 23:14:53.515114 INFO: [APUAPC] D15_APC_1: 0xffffffff
10038 23:14:53.518625 INFO: [APUAPC] D15_APC_2: 0x3fffff
10039 23:14:53.522269 INFO: [APUAPC] D15_APC_3: 0x0
10040 23:14:53.525066 INFO: [APUAPC] APC_CON: 0x4
10041 23:14:53.528217 INFO: [NOCDAPC] D0_APC_0: 0x0
10042 23:14:53.531942 INFO: [NOCDAPC] D0_APC_1: 0x0
10043 23:14:53.535047 INFO: [NOCDAPC] D1_APC_0: 0x0
10044 23:14:53.538805 INFO: [NOCDAPC] D1_APC_1: 0xfff
10045 23:14:53.538967 INFO: [NOCDAPC] D2_APC_0: 0x0
10046 23:14:53.541807 INFO: [NOCDAPC] D2_APC_1: 0xfff
10047 23:14:53.544962 INFO: [NOCDAPC] D3_APC_0: 0x0
10048 23:14:53.548732 INFO: [NOCDAPC] D3_APC_1: 0xfff
10049 23:14:53.551589 INFO: [NOCDAPC] D4_APC_0: 0x0
10050 23:14:53.555189 INFO: [NOCDAPC] D4_APC_1: 0xfff
10051 23:14:53.558317 INFO: [NOCDAPC] D5_APC_0: 0x0
10052 23:14:53.561858 INFO: [NOCDAPC] D5_APC_1: 0xfff
10053 23:14:53.564907 INFO: [NOCDAPC] D6_APC_0: 0x0
10054 23:14:53.568653 INFO: [NOCDAPC] D6_APC_1: 0xfff
10055 23:14:53.568796 INFO: [NOCDAPC] D7_APC_0: 0x0
10056 23:14:53.571479 INFO: [NOCDAPC] D7_APC_1: 0xfff
10057 23:14:53.574992 INFO: [NOCDAPC] D8_APC_0: 0x0
10058 23:14:53.578510 INFO: [NOCDAPC] D8_APC_1: 0xfff
10059 23:14:53.581641 INFO: [NOCDAPC] D9_APC_0: 0x0
10060 23:14:53.585101 INFO: [NOCDAPC] D9_APC_1: 0xfff
10061 23:14:53.588002 INFO: [NOCDAPC] D10_APC_0: 0x0
10062 23:14:53.591364 INFO: [NOCDAPC] D10_APC_1: 0xfff
10063 23:14:53.594885 INFO: [NOCDAPC] D11_APC_0: 0x0
10064 23:14:53.598118 INFO: [NOCDAPC] D11_APC_1: 0xfff
10065 23:14:53.601410 INFO: [NOCDAPC] D12_APC_0: 0x0
10066 23:14:53.604689 INFO: [NOCDAPC] D12_APC_1: 0xfff
10067 23:14:53.608179 INFO: [NOCDAPC] D13_APC_0: 0x0
10068 23:14:53.608296 INFO: [NOCDAPC] D13_APC_1: 0xfff
10069 23:14:53.611725 INFO: [NOCDAPC] D14_APC_0: 0x0
10070 23:14:53.614892 INFO: [NOCDAPC] D14_APC_1: 0xfff
10071 23:14:53.618484 INFO: [NOCDAPC] D15_APC_0: 0x0
10072 23:14:53.621938 INFO: [NOCDAPC] D15_APC_1: 0xfff
10073 23:14:53.624816 INFO: [NOCDAPC] APC_CON: 0x4
10074 23:14:53.628258 INFO: [APUAPC] set_apusys_apc done
10075 23:14:53.632009 INFO: [DEVAPC] devapc_init done
10076 23:14:53.634921 INFO: GICv3 without legacy support detected.
10077 23:14:53.638338 INFO: ARM GICv3 driver initialized in EL3
10078 23:14:53.644661 INFO: Maximum SPI INTID supported: 639
10079 23:14:53.648039 INFO: BL31: Initializing runtime services
10080 23:14:53.654884 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10081 23:14:53.655002 INFO: SPM: enable CPC mode
10082 23:14:53.661386 INFO: mcdi ready for mcusys-off-idle and system suspend
10083 23:14:53.664643 INFO: BL31: Preparing for EL3 exit to normal world
10084 23:14:53.668493 INFO: Entry point address = 0x80000000
10085 23:14:53.671488 INFO: SPSR = 0x8
10086 23:14:53.676983
10087 23:14:53.677087
10088 23:14:53.677179
10089 23:14:53.680444 Starting depthcharge on Spherion...
10090 23:14:53.680545
10091 23:14:53.680630 Wipe memory regions:
10092 23:14:53.680714
10093 23:14:53.681695 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10094 23:14:53.681872 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10095 23:14:53.681996 Setting prompt string to ['asurada:']
10096 23:14:53.682111 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10097 23:14:53.683687 [0x00000040000000, 0x00000054600000)
10098 23:14:53.806486
10099 23:14:53.806638 [0x00000054660000, 0x00000080000000)
10100 23:14:54.067052
10101 23:14:54.067232 [0x000000821a7280, 0x000000ffe64000)
10102 23:14:54.811563
10103 23:14:54.811762 [0x00000100000000, 0x00000240000000)
10104 23:14:56.702184
10105 23:14:56.705207 Initializing XHCI USB controller at 0x11200000.
10106 23:14:57.744436
10107 23:14:57.747533 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10108 23:14:57.747663
10109 23:14:57.747775
10110 23:14:57.747882
10111 23:14:57.748232 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10113 23:14:57.848677 asurada: tftpboot 192.168.201.1 12395397/tftp-deploy-lurrlnu3/kernel/image.itb 12395397/tftp-deploy-lurrlnu3/kernel/cmdline
10114 23:14:57.848864 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10115 23:14:57.848999 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10116 23:14:57.853126 tftpboot 192.168.201.1 12395397/tftp-deploy-lurrlnu3/kernel/image.ittp-deploy-lurrlnu3/kernel/cmdline
10117 23:14:57.853258
10118 23:14:57.853362 Waiting for link
10119 23:14:58.013203
10120 23:14:58.013395 R8152: Initializing
10121 23:14:58.013556
10122 23:14:58.016673 Version 9 (ocp_data = 6010)
10123 23:14:58.016796
10124 23:14:58.019873 R8152: Done initializing
10125 23:14:58.019989
10126 23:14:58.020099 Adding net device
10127 23:14:59.965732
10128 23:14:59.965901 done.
10129 23:14:59.965995
10130 23:14:59.966091 MAC: 00:e0:4c:78:7a:aa
10131 23:14:59.966180
10132 23:14:59.969222 Sending DHCP discover... done.
10133 23:14:59.969303
10134 23:14:59.972902 Waiting for reply... done.
10135 23:14:59.972982
10136 23:14:59.975836 Sending DHCP request... done.
10137 23:14:59.975930
10138 23:14:59.979429 Waiting for reply... done.
10139 23:14:59.979511
10140 23:14:59.979576 My ip is 192.168.201.12
10141 23:14:59.979636
10142 23:14:59.982625 The DHCP server ip is 192.168.201.1
10143 23:14:59.982707
10144 23:14:59.986021 TFTP server IP predefined by user: 192.168.201.1
10145 23:14:59.986101
10146 23:14:59.992855 Bootfile predefined by user: 12395397/tftp-deploy-lurrlnu3/kernel/image.itb
10147 23:14:59.992935
10148 23:14:59.995929 Sending tftp read request... done.
10149 23:14:59.996008
10150 23:14:59.999042 Waiting for the transfer...
10151 23:15:00.002622
10152 23:15:00.277266 00000000 ################################################################
10153 23:15:00.277398
10154 23:15:00.533381 00080000 ################################################################
10155 23:15:00.533578
10156 23:15:00.790295 00100000 ################################################################
10157 23:15:00.790472
10158 23:15:01.063057 00180000 ################################################################
10159 23:15:01.063206
10160 23:15:01.335677 00200000 ################################################################
10161 23:15:01.335835
10162 23:15:01.612423 00280000 ################################################################
10163 23:15:01.612570
10164 23:15:01.903021 00300000 ################################################################
10165 23:15:01.903226
10166 23:15:02.191393 00380000 ################################################################
10167 23:15:02.191602
10168 23:15:02.466903 00400000 ################################################################
10169 23:15:02.467094
10170 23:15:02.747634 00480000 ################################################################
10171 23:15:02.747781
10172 23:15:03.042018 00500000 ################################################################
10173 23:15:03.042160
10174 23:15:03.323657 00580000 ################################################################
10175 23:15:03.323836
10176 23:15:03.595313 00600000 ################################################################
10177 23:15:03.595493
10178 23:15:03.854214 00680000 ################################################################
10179 23:15:03.854365
10180 23:15:04.136954 00700000 ################################################################
10181 23:15:04.137101
10182 23:15:04.402931 00780000 ################################################################
10183 23:15:04.403072
10184 23:15:04.657884 00800000 ################################################################
10185 23:15:04.658028
10186 23:15:04.921491 00880000 ################################################################
10187 23:15:04.921635
10188 23:15:05.212258 00900000 ################################################################
10189 23:15:05.212477
10190 23:15:05.498895 00980000 ################################################################
10191 23:15:05.499045
10192 23:15:05.785523 00a00000 ################################################################
10193 23:15:05.785673
10194 23:15:06.070765 00a80000 ################################################################
10195 23:15:06.070960
10196 23:15:06.342542 00b00000 ################################################################
10197 23:15:06.342697
10198 23:15:06.620127 00b80000 ################################################################
10199 23:15:06.620305
10200 23:15:06.887553 00c00000 ################################################################
10201 23:15:06.887716
10202 23:15:07.150076 00c80000 ################################################################
10203 23:15:07.150232
10204 23:15:07.437438 00d00000 ################################################################
10205 23:15:07.437591
10206 23:15:07.711229 00d80000 ################################################################
10207 23:15:07.711399
10208 23:15:07.988470 00e00000 ################################################################
10209 23:15:07.988622
10210 23:15:08.265833 00e80000 ################################################################
10211 23:15:08.266014
10212 23:15:08.556305 00f00000 ################################################################
10213 23:15:08.556500
10214 23:15:08.827816 00f80000 ################################################################
10215 23:15:08.827970
10216 23:15:09.104265 01000000 ################################################################
10217 23:15:09.104465
10218 23:15:09.387291 01080000 ################################################################
10219 23:15:09.387443
10220 23:15:09.654182 01100000 ################################################################
10221 23:15:09.654349
10222 23:15:09.939749 01180000 ################################################################
10223 23:15:09.939931
10224 23:15:10.216341 01200000 ################################################################
10225 23:15:10.216492
10226 23:15:10.493427 01280000 ################################################################
10227 23:15:10.493622
10228 23:15:10.772629 01300000 ################################################################
10229 23:15:10.772808
10230 23:15:11.067652 01380000 ################################################################
10231 23:15:11.067804
10232 23:15:11.351531 01400000 ################################################################
10233 23:15:11.351681
10234 23:15:11.632210 01480000 ################################################################
10235 23:15:11.632383
10236 23:15:11.906017 01500000 ################################################################
10237 23:15:11.906178
10238 23:15:12.174700 01580000 ################################################################
10239 23:15:12.174853
10240 23:15:12.440651 01600000 ################################################################
10241 23:15:12.440840
10242 23:15:12.697369 01680000 ################################################################
10243 23:15:12.697518
10244 23:15:12.946448 01700000 ################################################################
10245 23:15:12.946631
10246 23:15:13.209765 01780000 ################################################################
10247 23:15:13.209984
10248 23:15:13.483729 01800000 ################################################################
10249 23:15:13.483949
10250 23:15:13.763301 01880000 ################################################################
10251 23:15:13.763458
10252 23:15:14.047144 01900000 ################################################################
10253 23:15:14.047323
10254 23:15:14.313411 01980000 ################################################################
10255 23:15:14.313560
10256 23:15:14.570837 01a00000 ################################################################
10257 23:15:14.571088
10258 23:15:14.848628 01a80000 ################################################################
10259 23:15:14.848785
10260 23:15:15.139404 01b00000 ################################################################
10261 23:15:15.139556
10262 23:15:15.393331 01b80000 ############################################################ done.
10263 23:15:15.393482
10264 23:15:15.396894 The bootfile was 29325634 bytes long.
10265 23:15:15.396988
10266 23:15:15.399951 Sending tftp read request... done.
10267 23:15:15.400036
10268 23:15:15.400110 Waiting for the transfer...
10269 23:15:15.400230
10270 23:15:15.403604 00000000 # done.
10271 23:15:15.403693
10272 23:15:15.410259 Command line loaded dynamically from TFTP file: 12395397/tftp-deploy-lurrlnu3/kernel/cmdline
10273 23:15:15.410353
10274 23:15:15.433218 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12395397/extract-nfsrootfs-h3gcb2cr,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10275 23:15:15.433363
10276 23:15:15.433434 Loading FIT.
10277 23:15:15.433495
10278 23:15:15.436814 Image ramdisk-1 has 17795936 bytes.
10279 23:15:15.436899
10280 23:15:15.440062 Image fdt-1 has 47278 bytes.
10281 23:15:15.440191
10282 23:15:15.443031 Image kernel-1 has 11480388 bytes.
10283 23:15:15.443115
10284 23:15:15.453156 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10285 23:15:15.453265
10286 23:15:15.469724 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10287 23:15:15.469867
10288 23:15:15.476010 Choosing best match conf-1 for compat google,spherion-rev2.
10289 23:15:15.476131
10290 23:15:15.484072 Connected to device vid:did:rid of 1ae0:0028:00
10291 23:15:15.491760
10292 23:15:15.494900 tpm_get_response: command 0x17b, return code 0x0
10293 23:15:15.494993
10294 23:15:15.498306 ec_init: CrosEC protocol v3 supported (256, 248)
10295 23:15:15.503149
10296 23:15:15.506627 tpm_cleanup: add release locality here.
10297 23:15:15.506724
10298 23:15:15.506790 Shutting down all USB controllers.
10299 23:15:15.509969
10300 23:15:15.510110 Removing current net device
10301 23:15:15.510175
10302 23:15:15.516458 Exiting depthcharge with code 4 at timestamp: 51150751
10303 23:15:15.516549
10304 23:15:15.519738 LZMA decompressing kernel-1 to 0x821a6718
10305 23:15:15.519820
10306 23:15:15.523182 LZMA decompressing kernel-1 to 0x40000000
10307 23:15:16.958912
10308 23:15:16.959110 jumping to kernel
10309 23:15:16.959746 end: 2.2.4 bootloader-commands (duration 00:00:23) [common]
10310 23:15:16.959907 start: 2.2.5 auto-login-action (timeout 00:04:02) [common]
10311 23:15:16.960018 Setting prompt string to ['Linux version [0-9]']
10312 23:15:16.960173 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10313 23:15:16.960277 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10314 23:15:17.040673
10315 23:15:17.043885 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10316 23:15:17.047597 start: 2.2.5.1 login-action (timeout 00:04:02) [common]
10317 23:15:17.047719 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10318 23:15:17.047822 Setting prompt string to []
10319 23:15:17.047933 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10320 23:15:17.048043 Using line separator: #'\n'#
10321 23:15:17.048133 No login prompt set.
10322 23:15:17.048228 Parsing kernel messages
10323 23:15:17.048341 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10324 23:15:17.048529 [login-action] Waiting for messages, (timeout 00:04:02)
10325 23:15:17.067595 [ 0.000000] Linux version 6.1.67-cip12-rt7 (KernelCI@build-j59954-arm64-gcc-10-defconfig-arm64-chromebook-nblph) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Wed Dec 27 22:50:56 UTC 2023
10326 23:15:17.071144 [ 0.000000] random: crng init done
10327 23:15:17.077872 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10328 23:15:17.081007 [ 0.000000] efi: UEFI not found.
10329 23:15:17.087465 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10330 23:15:17.094456 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10331 23:15:17.104078 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10332 23:15:17.114125 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10333 23:15:17.120932 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10334 23:15:17.127357 [ 0.000000] printk: bootconsole [mtk8250] enabled
10335 23:15:17.130883 [ 0.000000] NUMA: No NUMA configuration found
10336 23:15:17.140590 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10337 23:15:17.143984 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcfa00-0x23efd1fff]
10338 23:15:17.147681 [ 0.000000] Zone ranges:
10339 23:15:17.153769 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10340 23:15:17.157270 [ 0.000000] DMA32 empty
10341 23:15:17.164280 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10342 23:15:17.167387 [ 0.000000] Movable zone start for each node
10343 23:15:17.170444 [ 0.000000] Early memory node ranges
10344 23:15:17.177615 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10345 23:15:17.183821 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10346 23:15:17.190301 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10347 23:15:17.193861 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10348 23:15:17.200229 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10349 23:15:17.207303 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10350 23:15:17.265512 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10351 23:15:17.272250 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10352 23:15:17.278961 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10353 23:15:17.282505 [ 0.000000] psci: probing for conduit method from DT.
10354 23:15:17.289246 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10355 23:15:17.292586 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10356 23:15:17.298722 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10357 23:15:17.302008 [ 0.000000] psci: SMC Calling Convention v1.2
10358 23:15:17.309013 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10359 23:15:17.312243 [ 0.000000] Detected VIPT I-cache on CPU0
10360 23:15:17.319206 [ 0.000000] CPU features: detected: GIC system register CPU interface
10361 23:15:17.325193 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10362 23:15:17.332032 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10363 23:15:17.338722 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10364 23:15:17.345388 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10365 23:15:17.351693 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10366 23:15:17.358793 [ 0.000000] alternatives: applying boot alternatives
10367 23:15:17.364806 [ 0.000000] Fallback order for Node 0: 0
10368 23:15:17.371551 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10369 23:15:17.371681 [ 0.000000] Policy zone: Normal
10370 23:15:17.395023 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12395397/extract-nfsrootfs-h3gcb2cr,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10371 23:15:17.407981 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10372 23:15:17.418405 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10373 23:15:17.428085 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10374 23:15:17.435067 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10375 23:15:17.438352 <6>[ 0.000000] software IO TLB: area num 8.
10376 23:15:17.494626 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10377 23:15:17.644157 <6>[ 0.000000] Memory: 7951340K/8385536K available (17984K kernel code, 4116K rwdata, 18184K rodata, 8448K init, 615K bss, 401428K reserved, 32768K cma-reserved)
10378 23:15:17.650729 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10379 23:15:17.657478 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10380 23:15:17.660845 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10381 23:15:17.667490 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10382 23:15:17.673861 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10383 23:15:17.677268 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10384 23:15:17.687437 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10385 23:15:17.693811 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10386 23:15:17.697573 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10387 23:15:17.705117 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10388 23:15:17.708266 <6>[ 0.000000] GICv3: 608 SPIs implemented
10389 23:15:17.715171 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10390 23:15:17.718246 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10391 23:15:17.721578 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10392 23:15:17.731220 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10393 23:15:17.741441 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10394 23:15:17.754578 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10395 23:15:17.761567 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10396 23:15:17.770652 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10397 23:15:17.783821 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10398 23:15:17.790264 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10399 23:15:17.797077 <6>[ 0.009180] Console: colour dummy device 80x25
10400 23:15:17.806656 <6>[ 0.013908] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10401 23:15:17.813577 <6>[ 0.024351] pid_max: default: 32768 minimum: 301
10402 23:15:17.816669 <6>[ 0.029251] LSM: Security Framework initializing
10403 23:15:17.823608 <6>[ 0.034188] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10404 23:15:17.833478 <6>[ 0.042050] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10405 23:15:17.839768 <6>[ 0.051459] cblist_init_generic: Setting adjustable number of callback queues.
10406 23:15:17.846968 <6>[ 0.058901] cblist_init_generic: Setting shift to 3 and lim to 1.
10407 23:15:17.856724 <6>[ 0.065242] cblist_init_generic: Setting adjustable number of callback queues.
10408 23:15:17.863198 <6>[ 0.072669] cblist_init_generic: Setting shift to 3 and lim to 1.
10409 23:15:17.866731 <6>[ 0.079107] rcu: Hierarchical SRCU implementation.
10410 23:15:17.873430 <6>[ 0.079109] rcu: Max phase no-delay instances is 1000.
10411 23:15:17.880127 <6>[ 0.079134] printk: bootconsole [mtk8250] printing thread started
10412 23:15:17.886972 <6>[ 0.097463] EFI services will not be available.
10413 23:15:17.890074 <6>[ 0.097666] smp: Bringing up secondary CPUs ...
10414 23:15:17.893127 <6>[ 0.097978] Detected VIPT I-cache on CPU1
10415 23:15:17.900340 <6>[ 0.098048] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10416 23:15:17.910053 <6>[ 0.098079] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10417 23:15:17.918546 <6>[ 0.125931] Detected VIPT I-cache on CPU2
10418 23:15:17.928473 <6>[ 0.125981] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10419 23:15:17.935175 <6>[ 0.125997] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10420 23:15:17.938513 <6>[ 0.126255] Detected VIPT I-cache on CPU3
10421 23:15:17.944924 <6>[ 0.126301] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10422 23:15:17.951437 <6>[ 0.126315] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10423 23:15:17.955038 <6>[ 0.126625] CPU features: detected: Spectre-v4
10424 23:15:17.961533 <6>[ 0.126631] CPU features: detected: Spectre-BHB
10425 23:15:17.965037 <6>[ 0.126636] Detected PIPT I-cache on CPU4
10426 23:15:17.971479 <6>[ 0.126696] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10427 23:15:17.977948 <6>[ 0.126712] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10428 23:15:17.984748 <6>[ 0.127006] Detected PIPT I-cache on CPU5
10429 23:15:17.991392 <6>[ 0.127068] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10430 23:15:17.997975 <6>[ 0.127084] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10431 23:15:18.001674 <6>[ 0.127362] Detected PIPT I-cache on CPU6
10432 23:15:18.008234 <6>[ 0.127427] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10433 23:15:18.014754 <6>[ 0.127444] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10434 23:15:18.021240 <6>[ 0.127738] Detected PIPT I-cache on CPU7
10435 23:15:18.028248 <6>[ 0.127803] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10436 23:15:18.034596 <6>[ 0.127819] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10437 23:15:18.037658 <6>[ 0.127867] smp: Brought up 1 node, 8 CPUs
10438 23:15:18.044585 <6>[ 0.127872] SMP: Total of 8 processors activated.
10439 23:15:18.047866 <6>[ 0.127874] CPU features: detected: 32-bit EL0 Support
10440 23:15:18.057903 <6>[ 0.127876] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10441 23:15:18.064444 <6>[ 0.127879] CPU features: detected: Common not Private translations
10442 23:15:18.071393 <6>[ 0.127881] CPU features: detected: CRC32 instructions
10443 23:15:18.074177 <6>[ 0.127883] CPU features: detected: RCpc load-acquire (LDAPR)
10444 23:15:18.081089 <6>[ 0.127885] CPU features: detected: LSE atomic instructions
10445 23:15:18.087582 <6>[ 0.127887] CPU features: detected: Privileged Access Never
10446 23:15:18.094184 <6>[ 0.127889] CPU features: detected: RAS Extension Support
10447 23:15:18.100900 <6>[ 0.127891] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10448 23:15:18.104442 <6>[ 0.127958] CPU: All CPU(s) started at EL2
10449 23:15:18.110474 <6>[ 0.127960] alternatives: applying system-wide alternatives
10450 23:15:18.113969 <6>[ 0.141017] devtmpfs: initialized
10451 23:15:18.123874 <6>[ 0.147294] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10452 23:15:18.152515 �(E��U���ѕɕ���}%9Q��ɽѽ����2�����5R�<6>[ 0<.364761] printk: console [ttyS0] printing thread started
10453 23:15:18.158991 6<6>[ 0.364786] printk: console [ttyS0] enabled
10454 23:15:18.165464 >[ 0.228753] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10455 23:15:18.173259 <6>[ 0.364791] printk: bootconsole [mtk8250] disabled
10456 23:15:18.179621 <6>[ 0.382880] printk: bootconsole [mtk8250] printing thread stopped
10457 23:15:18.183185 <6>[ 0.383940] SuperH (H)SCI(F) driver initialized
10458 23:15:18.189606 <6>[ 0.384412] msm_serial: driver initialized
10459 23:15:18.196159 <6>[ 0.388982] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10460 23:15:18.206626 <6>[ 0.389009] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10461 23:15:18.212515 <6>[ 0.389038] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10462 23:15:18.232879 <6>[ 0.389067] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10463 23:15:18.241322 <6>[ 0.389088] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10464 23:15:18.241800 <6>[ 0.389115] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10465 23:15:18.258090 <6>[ 0.389143] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10466 23:15:18.258185 <6>[ 0.389252] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10467 23:15:18.267180 <6>[ 0.389281] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10468 23:15:18.272485 <6>[ 0.400403] loop: module loaded
10469 23:15:18.276744 <6>[ 0.403085] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10470 23:15:18.280226 <4>[ 0.419858] mtk-pmic-keys: Failed to locate of_node [id: -1]
10471 23:15:18.286853 <6>[ 0.420693] megasas: 07.719.03.00-rc1
10472 23:15:18.293408 <6>[ 0.432846] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10473 23:15:18.296894 <6>[ 0.432913] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10474 23:15:18.303814 <6>[ 0.444877] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10475 23:15:18.313577 <6>[ 0.498863] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10476 23:15:18.796914 <6>[ 1.006222] Freeing initrd memory: 17376K
10477 23:15:18.803588 <6>[ 1.012172] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10478 23:15:18.807201 <6>[ 1.016798] tun: Universal TUN/TAP device driver, 1.6
10479 23:15:18.810809 <6>[ 1.017556] thunder_xcv, ver 1.0
10480 23:15:18.813676 <6>[ 1.017573] thunder_bgx, ver 1.0
10481 23:15:18.817126 <6>[ 1.017587] nicpf, ver 1.0
10482 23:15:18.824031 <6>[ 1.018636] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10483 23:15:18.830566 <6>[ 1.018639] hns3: Copyright (c) 2017 Huawei Corporation.
10484 23:15:18.833434 <6>[ 1.018663] hclge is initializing
10485 23:15:18.840728 <6>[ 1.018679] e1000: Intel(R) PRO/1000 Network Driver
10486 23:15:18.844138 <6>[ 1.018681] e1000: Copyright (c) 1999-2006 Intel Corporation.
10487 23:15:18.851426 <6>[ 1.018698] e1000e: Intel(R) PRO/1000 Network Driver
10488 23:15:18.858735 <6>[ 1.018699] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10489 23:15:18.862096 <6>[ 1.018717] igb: Intel(R) Gigabit Ethernet Network Driver
10490 23:15:18.868407 <6>[ 1.018719] igb: Copyright (c) 2007-2014 Intel Corporation.
10491 23:15:18.875929 <6>[ 1.018732] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10492 23:15:18.882714 <6>[ 1.018734] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10493 23:15:18.886312 <6>[ 1.019024] sky2: driver version 1.30
10494 23:15:18.889211 <6>[ 1.020093] VFIO - User Level meta-driver version: 0.3
10495 23:15:18.895894 <6>[ 1.022954] usbcore: registered new interface driver usb-storage
10496 23:15:18.902532 <6>[ 1.023133] usbcore: registered new device driver onboard-usb-hub
10497 23:15:18.909251 <6>[ 1.025861] mt6397-rtc mt6359-rtc: registered as rtc0
10498 23:15:18.915797 <6>[ 1.026011] mt6397-rtc mt6359-rtc: setting system clock to 2023-12-27T23:12:47 UTC (1703718767)
10499 23:15:18.922390 <6>[ 1.026623] i2c_dev: i2c /dev entries driver
10500 23:15:18.929641 <6>[ 1.033724] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10501 23:15:18.935710 <6>[ 1.048706] cpu cpu0: EM: created perf domain
10502 23:15:18.939347 <6>[ 1.049006] cpu cpu4: EM: created perf domain
10503 23:15:18.946084 <6>[ 1.051914] sdhci: Secure Digital Host Controller Interface driver
10504 23:15:18.949269 <6>[ 1.051916] sdhci: Copyright(c) Pierre Ossman
10505 23:15:18.955879 <6>[ 1.052278] Synopsys Designware Multimedia Card Interface Driver
10506 23:15:18.963001 <6>[ 1.052670] sdhci-pltfm: SDHCI platform and OF driver helper
10507 23:15:18.969128 <6>[ 1.056901] ledtrig-cpu: registered to indicate activity on CPUs
10508 23:15:18.972752 <6>[ 1.057568] mmc0: CQHCI version 5.10
10509 23:15:18.979341 <6>[ 1.057575] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10510 23:15:18.985603 <6>[ 1.057870] usbcore: registered new interface driver usbhid
10511 23:15:18.989049 <6>[ 1.057871] usbhid: USB HID core driver
10512 23:15:18.995484 <6>[ 1.057989] spi_master spi0: will run message pump with realtime priority
10513 23:15:19.009048 <6>[ 1.089763] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10514 23:15:19.022653 <6>[ 1.092800] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10515 23:15:19.029345 <6>[ 1.094130] cros-ec-spi spi0.0: Chrome EC device registered
10516 23:15:19.035814 <6>[ 1.108377] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10517 23:15:19.042165 <6>[ 1.109337] NET: Registered PF_PACKET protocol family
10518 23:15:19.045682 <6>[ 1.109409] 9pnet: Installing 9P2000 support
10519 23:15:19.052455 <5>[ 1.109466] Key type dns_resolver registered
10520 23:15:19.055813 <6>[ 1.110061] registered taskstats version 1
10521 23:15:19.062492 <5>[ 1.110077] Loading compiled-in X.509 certificates
10522 23:15:19.072030 <4>[ 1.132523] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10523 23:15:19.081934 <4>[ 1.132685] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10524 23:15:19.089210 <3>[ 1.132695] debugfs: File 'uA_load' in directory '/' already present!
10525 23:15:19.095257 <3>[ 1.132703] debugfs: File 'min_uV' in directory '/' already present!
10526 23:15:19.102117 <3>[ 1.132706] debugfs: File 'max_uV' in directory '/' already present!
10527 23:15:19.109088 <3>[ 1.132709] debugfs: File 'constraint_flags' in directory '/' already present!
10528 23:15:19.119163 <3>[ 1.135937] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10529 23:15:19.122478 <6>[ 1.148425] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10530 23:15:19.129040 <6>[ 1.148987] xhci-mtk 11200000.usb: xHCI Host Controller
10531 23:15:19.135693 <6>[ 1.149002] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10532 23:15:19.145416 <6>[ 1.149206] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10533 23:15:19.152471 <6>[ 1.149250] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10534 23:15:19.158739 <6>[ 1.149331] xhci-mtk 11200000.usb: xHCI Host Controller
10535 23:15:19.165348 <6>[ 1.149338] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10536 23:15:19.172235 <6>[ 1.149345] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10537 23:15:19.175486 <6>[ 1.149859] hub 1-0:1.0: USB hub found
10538 23:15:19.182232 <6>[ 1.149878] hub 1-0:1.0: 1 port detected
10539 23:15:19.188869 <6>[ 1.150073] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10540 23:15:19.191883 <6>[ 1.150435] hub 2-0:1.0: USB hub found
10541 23:15:19.198685 <6>[ 1.150450] hub 2-0:1.0: 1 port detected
10542 23:15:19.202146 <6>[ 1.151765] mmc0: Command Queue Engine enabled
10543 23:15:19.208837 <6>[ 1.151774] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10544 23:15:19.212647 <6>[ 1.152264] mmcblk0: mmc0:0001 DA4128 116 GiB
10545 23:15:19.218556 <6>[ 1.155498] mtk-msdc 11f70000.mmc: Got CD GPIO
10546 23:15:19.225351 <6>[ 1.155710] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10547 23:15:19.228733 <6>[ 1.156928] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10548 23:15:19.235433 <6>[ 1.157772] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10549 23:15:19.241984 <6>[ 1.158496] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10550 23:15:19.249126 <6>[ 1.171013] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10551 23:15:19.255881 <6>[ 1.171021] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10552 23:15:19.265411 <4>[ 1.171172] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10553 23:15:19.275292 <6>[ 1.171804] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10554 23:15:19.282127 <6>[ 1.171807] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10555 23:15:19.288789 <6>[ 1.171933] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10556 23:15:19.299044 <6>[ 1.171944] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10557 23:15:19.305596 <6>[ 1.171948] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10558 23:15:19.315299 <6>[ 1.171953] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10559 23:15:19.321998 <6>[ 1.173382] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10560 23:15:19.331928 <6>[ 1.173403] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10561 23:15:19.338629 <6>[ 1.173409] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10562 23:15:19.348220 <6>[ 1.173428] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10563 23:15:19.355211 <6>[ 1.173435] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10564 23:15:19.364890 <6>[ 1.173441] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10565 23:15:19.371590 <6>[ 1.173447] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10566 23:15:19.381353 <6>[ 1.173453] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10567 23:15:19.388237 <6>[ 1.173459] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10568 23:15:19.397959 <6>[ 1.173466] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10569 23:15:19.404864 <6>[ 1.173473] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10570 23:15:19.414664 <6>[ 1.173480] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10571 23:15:19.421490 <6>[ 1.173487] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10572 23:15:19.431302 <6>[ 1.173496] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10573 23:15:19.440878 <6>[ 1.173504] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10574 23:15:19.447630 <6>[ 1.174093] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10575 23:15:19.450568 <6>[ 1.175053] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10576 23:15:19.457278 <6>[ 1.175606] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10577 23:15:19.463997 <6>[ 1.176217] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10578 23:15:19.474271 <6>[ 1.176845] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10579 23:15:19.480821 <6>[ 1.177028] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10580 23:15:19.490553 <6>[ 1.177040] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10581 23:15:19.500478 <6>[ 1.177045] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10582 23:15:19.510359 <6>[ 1.177051] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10583 23:15:19.520096 <6>[ 1.177056] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10584 23:15:19.527133 <6>[ 1.177061] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10585 23:15:19.536932 <6>[ 1.177066] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10586 23:15:19.546983 <6>[ 1.177072] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10587 23:15:19.556834 <6>[ 1.177076] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10588 23:15:19.566975 <6>[ 1.177083] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10589 23:15:19.576936 <6>[ 1.177088] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10590 23:15:19.583309 <6>[ 1.177659] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10591 23:15:19.589811 <6>[ 1.186078] Trying to probe devices needed for running init ...
10592 23:15:19.596882 <6>[ 1.569578] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10593 23:15:19.599938 <6>[ 1.729167] hub 1-1:1.0: USB hub found
10594 23:15:19.606572 <6>[ 1.729542] hub 1-1:1.0: 4 ports detected
10595 23:15:19.610077 <6>[ 1.733089] hub 1-1:1.0: USB hub found
10596 23:15:19.612995 <6>[ 1.733390] hub 1-1:1.0: 4 ports detected
10597 23:15:19.648151 <6>[ 1.853692] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10598 23:15:19.669257 <6>[ 1.878559] hub 2-1:1.0: USB hub found
10599 23:15:19.672127 <6>[ 1.878953] hub 2-1:1.0: 3 ports detected
10600 23:15:19.675903 <6>[ 1.881836] hub 2-1:1.0: USB hub found
10601 23:15:19.678851 <6>[ 1.882190] hub 2-1:1.0: 3 ports detected
10602 23:15:19.840776 <6>[ 2.045737] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10603 23:15:19.961398 <6>[ 2.172647] hub 1-1.4:1.0: USB hub found
10604 23:15:19.964166 <6>[ 2.172955] hub 1-1.4:1.0: 2 ports detected
10605 23:15:19.967780 <6>[ 2.175890] hub 1-1.4:1.0: USB hub found
10606 23:15:19.974536 <6>[ 2.176177] hub 1-1.4:1.0: 2 ports detected
10607 23:15:20.044161 <6>[ 2.249867] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10608 23:15:20.260579 <6>[ 2.465711] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10609 23:15:20.444339 <6>[ 2.649715] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10610 23:15:31.261045 <6>[ 13.474712] ALSA device list:
10611 23:15:31.267439 <6>[ 13.474735] No soundcards found.
10612 23:15:31.270806 <6>[ 13.479143] Freeing unused kernel memory: 8448K
10613 23:15:31.273617 <6>[ 13.479269] Run /init as init process
10614 23:15:31.277191 Loading, please wait...
10615 23:15:31.296271 Starting version 247.3-7+deb11u2
10616 23:15:31.486926 <6>[ 13.697001] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10617 23:15:31.496817 <6>[ 13.705904] remoteproc remoteproc0: scp is available
10618 23:15:31.503576 <6>[ 13.706048] remoteproc remoteproc0: powering up scp
10619 23:15:31.510028 <6>[ 13.706058] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10620 23:15:31.516648 <6>[ 13.706092] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10621 23:15:31.546993 <6>[ 13.757187] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10622 23:15:31.553786 <6>[ 13.757216] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10623 23:15:31.563660 <6>[ 13.757221] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10624 23:15:31.574851 <4>[ 13.785124] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10625 23:15:31.581436 <3>[ 13.785187] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10626 23:15:31.591643 <3>[ 13.785199] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10627 23:15:31.598188 <3>[ 13.785204] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10628 23:15:31.604648 <4>[ 13.785245] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10629 23:15:31.614938 <3>[ 13.785285] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10630 23:15:31.621827 <3>[ 13.785290] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10631 23:15:31.629418 <3>[ 13.785292] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10632 23:15:31.639349 <3>[ 13.785296] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10633 23:15:31.645900 <3>[ 13.785299] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10634 23:15:31.653283 <3>[ 13.785321] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10635 23:15:31.663068 <3>[ 13.785344] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10636 23:15:31.669877 <3>[ 13.785347] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10637 23:15:31.679333 <3>[ 13.785349] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10638 23:15:31.686788 <3>[ 13.785365] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10639 23:15:31.696078 <3>[ 13.785368] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10640 23:15:31.702986 <3>[ 13.785370] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10641 23:15:31.709634 <3>[ 13.785372] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10642 23:15:31.719053 <3>[ 13.785375] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10643 23:15:31.725738 <3>[ 13.785394] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10644 23:15:31.736340 <6>[ 13.789631] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10645 23:15:31.739250 <6>[ 13.809595] mc: Linux media interface: v0.10
10646 23:15:31.746123 <6>[ 13.813880] usbcore: registered new interface driver r8152
10647 23:15:31.752725 <4>[ 13.826272] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10648 23:15:31.759290 <4>[ 13.826272] Fallback method does not support PEC.
10649 23:15:31.765833 <6>[ 13.831344] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10650 23:15:31.776051 <6>[ 13.831518] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10651 23:15:31.779086 <6>[ 13.831526] remoteproc remoteproc0: remote processor scp is now up
10652 23:15:31.789428 <3>[ 13.847135] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10653 23:15:31.798978 <3>[ 13.871070] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10654 23:15:31.805574 <6>[ 13.874466] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10655 23:15:31.812338 <6>[ 13.874739] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10656 23:15:31.818760 <6>[ 13.874744] pci_bus 0000:00: root bus resource [bus 00-ff]
10657 23:15:31.825659 <6>[ 13.874751] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10658 23:15:31.835666 <6>[ 13.874753] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10659 23:15:31.841784 <6>[ 13.874784] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10660 23:15:31.848446 <6>[ 13.874800] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10661 23:15:31.855439 <6>[ 13.874878] pci 0000:00:00.0: supports D1 D2
10662 23:15:31.862063 <6>[ 13.874880] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10663 23:15:31.868889 <6>[ 13.875867] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10664 23:15:31.874911 <6>[ 13.875946] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10665 23:15:31.881680 <6>[ 13.875971] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10666 23:15:31.891555 <6>[ 13.875987] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10667 23:15:31.898234 <6>[ 13.876002] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10668 23:15:31.901833 <6>[ 13.876110] pci 0000:01:00.0: supports D1 D2
10669 23:15:31.908014 <6>[ 13.876112] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10670 23:15:31.918175 <6>[ 13.877581] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10671 23:15:31.924702 <6>[ 13.889649] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10672 23:15:31.931218 <6>[ 13.889669] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10673 23:15:31.941168 <6>[ 13.889673] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10674 23:15:31.947825 <6>[ 13.889681] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10675 23:15:31.957769 <6>[ 13.889694] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10676 23:15:31.964434 <6>[ 13.889706] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10677 23:15:31.971158 <6>[ 13.889718] pci 0000:00:00.0: PCI bridge to [bus 01]
10678 23:15:31.977745 <6>[ 13.889723] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10679 23:15:31.984409 <6>[ 13.889857] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10680 23:15:31.991203 <6>[ 13.890402] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10681 23:15:31.997859 <6>[ 13.890850] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10682 23:15:32.004504 <6>[ 13.893198] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10683 23:15:32.014198 <6>[ 13.893820] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10684 23:15:32.024266 <6>[ 13.898329] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10685 23:15:32.030373 <6>[ 13.898548] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10686 23:15:32.040648 <4>[ 13.917986] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10687 23:15:32.050715 <4>[ 13.918002] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10688 23:15:32.054159 <6>[ 13.919841] videodev: Linux video capture interface: v2.00
10689 23:15:32.060571 <6>[ 13.931031] usbcore: registered new interface driver cdc_ether
10690 23:15:32.067135 <5>[ 13.935682] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10691 23:15:32.073599 <6>[ 13.946317] usbcore: registered new interface driver r8153_ecm
10692 23:15:32.080670 <5>[ 13.948457] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10693 23:15:32.090597 <4>[ 13.948533] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10694 23:15:32.093982 <6>[ 13.948541] cfg80211: failed to load regulatory.db
10695 23:15:32.100402 <6>[ 13.954194] Bluetooth: Core ver 2.22
10696 23:15:32.103972 <6>[ 13.954306] NET: Registered PF_BLUETOOTH protocol family
10697 23:15:32.110245 <6>[ 13.954309] Bluetooth: HCI device and connection manager initialized
10698 23:15:32.117123 <6>[ 13.954347] Bluetooth: HCI socket layer initialized
10699 23:15:32.120753 <6>[ 13.954355] Bluetooth: L2CAP socket layer initialized
10700 23:15:32.127261 <6>[ 13.954368] Bluetooth: SCO socket layer initialized
10701 23:15:32.133408 <6>[ 13.979623] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10702 23:15:32.146676 <6>[ 13.980636] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10703 23:15:32.153539 <6>[ 13.980722] usbcore: registered new interface driver uvcvideo
10704 23:15:32.156645 <6>[ 13.999737] r8152 2-1.3:1.0 eth0: v1.12.13
10705 23:15:32.163507 <6>[ 14.007602] r8152 2-1.3:1.0 enx00e04c787aaa: renamed from eth0
10706 23:15:32.167109 <6>[ 14.008876] usbcore: registered new interface driver btusb
10707 23:15:32.180427 <4>[ 14.009751] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10708 23:15:32.183694 <3>[ 14.009762] Bluetooth: hci0: Failed to load firmware file (-2)
10709 23:15:32.190056 <3>[ 14.009765] Bluetooth: hci0: Failed to set up firmware (-2)
10710 23:15:32.200178 <4>[ 14.009768] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10711 23:15:32.206414 <6>[ 14.018368] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10712 23:15:32.216407 <6>[ 14.064762] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10713 23:15:32.220017 <6>[ 14.064855] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10714 23:15:32.226567 <6>[ 14.081616] mt7921e 0000:01:00.0: ASIC revision: 79610010
10715 23:15:32.236276 <6>[ 14.176957] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
10716 23:15:32.236442 <6>[ 14.176957]
10717 23:15:32.246490 <6>[ 14.440554] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
10718 23:15:32.249418 Begin: Loading essential drivers ... done.
10719 23:15:32.253253 Begin: Running /scripts/init-premount ... done.
10720 23:15:32.259284 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10721 23:15:32.269124 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10722 23:15:32.272638 Device /sys/class/net/enx00e04c787aaa found
10723 23:15:32.272735 done.
10724 23:15:32.316174 IP-Config: enx00e04c787aaa hardware address 00:e0:4c:78:7a:aa mtu 1500 DHCP
10725 23:15:33.083804 <6>[ 15.296239] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10726 23:15:33.439336 <6>[ 15.650416] r8152 2-1.3:1.0 enx00e04c787aaa: carrier on
10727 23:15:34.311996 IP-Config: no response after 2 secs - giving up
10728 23:15:34.351045 IP-Config: enx00e04c787aaa hardware address 00:e0:4c:78:7a:aa mtu 1500 DHCP
10729 23:15:34.364041 IP-Config: wlp1s0 hardware address d8:f3:bc:78:17:6f mtu 1500 DHCP
10730 23:15:35.084375 IP-Config: enx00e04c787aaa complete (dhcp from 192.168.201.1):
10731 23:15:35.090946 address: 192.168.201.12 broadcast: 192.168.201.255 netmask: 255.255.255.0
10732 23:15:35.097460 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10733 23:15:35.104210 host : mt8192-asurada-spherion-r0-cbg-0
10734 23:15:35.110941 domain : lava-rack
10735 23:15:35.114232 rootserver: 192.168.201.1 rootpath:
10736 23:15:35.117337 filename :
10737 23:15:35.229606 done.
10738 23:15:35.232863 Begin: Running /scripts/nfs-bottom ... done.
10739 23:15:35.255459 Begin: Running /scripts/init-bottom ... done.
10740 23:15:36.427384 <6>[ 18.640813] NET: Registered PF_INET6 protocol family
10741 23:15:36.430460 <6>[ 18.642806] Segment Routing with IPv6
10742 23:15:36.437150 <6>[ 18.642821] In-situ OAM (IOAM) with IPv6
10743 23:15:36.535303 <30>[ 18.728491] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10744 23:15:36.535442
10745 23:15:36.541369 Welcome to [1<30>[ 18.729583] systemd[1]: Detected architecture arm64.
10746 23:15:36.544757 mDebian GNU/Linux 11 (bullseye)[0m!
10747 23:15:36.544832
10748 23:15:36.563215 <30>[ 18.775755] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10749 23:15:37.270343 <30>[ 19.480622] systemd[1]: Queued start job for default target Graphical Interface.
10750 23:15:37.305697 [[0;32m OK [<30>[ 19.516145] systemd[1]: Created slice system-getty.slice.
10751 23:15:37.309129 0m] Created slice [0;1;39msystem-getty.slice[0m.
10752 23:15:37.328236 [[0;32m OK [0m] Created slic<30>[ 19.539101] systemd[1]: Created slice system-modprobe.slice.
10753 23:15:37.331285 e [0;1;39msystem-modprobe.slice[0m.
10754 23:15:37.352074 [[0;32m OK [0m] Created slic<30>[ 19.562941] systemd[1]: Created slice system-serial\x2dgetty.slice.
10755 23:15:37.358850 e [0;1;39msystem-serial\x2dgetty.slice[0m.
10756 23:15:37.376715 [[0;32m OK [0m] Created slic<30>[ 19.587455] systemd[1]: Created slice User and Session Slice.
10757 23:15:37.379754 e [0;1;39mUser and Session Slice[0m.
10758 23:15:37.402638 [[0;32m OK [0m] Started [0;1;39mDispatch Pa<30>[ 19.610023] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10759 23:15:37.405565 ssword …ts to Console Directory Watch[0m.
10760 23:15:37.430270 [[0;32m OK [0m] Started [0;1;39mForward Pas<30>[ 19.637918] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10761 23:15:37.433333 sword R…uests to Wall Directory Watch[0m.
10762 23:15:37.457501 [[0;32m OK [0m] Reached target [0;1;39mLoca<30>[ 19.661889] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10763 23:15:37.463987 <30>[ 19.662086] systemd[1]: Reached target Local Encrypted Volumes.
10764 23:15:37.467645 l Encrypted Volumes[0m.
10765 23:15:37.487257 [[0;32m OK [0m] Reached target [0;1;39mPath<30>[ 19.697845] systemd[1]: Reached target Paths.
10766 23:15:37.487341 s[0m.
10767 23:15:37.510012 [[0;32m OK [0m] Reached target [0;1;39mRemo<30>[ 19.717721] systemd[1]: Reached target Remote File Systems.
10768 23:15:37.510099 te File Systems[0m.
10769 23:15:37.531419 [[0;32m OK [0m] Reached target [0;1;39mSlic<30>[ 19.742075] systemd[1]: Reached target Slices.
10770 23:15:37.531503 es[0m.
10771 23:15:37.550914 [[0;32m OK [0m] Reached target [0;1;39mSwap<30>[ 19.761741] systemd[1]: Reached target Swap.
10772 23:15:37.551041 [0m.
10773 23:15:37.574384 [[0;32m OK [0m] Listening on [0;1;39minitct<30>[ 19.782239] systemd[1]: Listening on initctl Compatibility Named Pipe.
10774 23:15:37.577848 l Compatibility Named Pipe[0m.
10775 23:15:37.587619 [[0;32m OK [0m] Listening on [0;1;39mJourna<30>[ 19.798067] systemd[1]: Listening on Journal Audit Socket.
10776 23:15:37.591413 l Audit Socket[0m.
10777 23:15:37.611585 [[0;32m OK [0m] Listening on<30>[ 19.822737] systemd[1]: Listening on Journal Socket (/dev/log).
10778 23:15:37.615119 [0;1;39mJournal Socket (/dev/log)[0m.
10779 23:15:37.636437 [[0;32m OK [0m] Listening on<30>[ 19.847018] systemd[1]: Listening on Journal Socket.
10780 23:15:37.639536 [0;1;39mJournal Socket[0m.
10781 23:15:37.656336 [[0;32m OK [0m] Listening on<30>[ 19.867266] systemd[1]: Listening on Network Service Netlink Socket.
10782 23:15:37.662874 [0;1;39mNetwork Service Netlink Socket[0m.
10783 23:15:37.681927 [[0;32m OK [<30>[ 19.892785] systemd[1]: Listening on udev Control Socket.
10784 23:15:37.685090 0m] Listening on [0;1;39mudev Control Socket[0m.
10785 23:15:37.703816 [[0;32m OK [0m] Listening on<30>[ 19.914859] systemd[1]: Listening on udev Kernel Socket.
10786 23:15:37.707521 [0;1;39mudev Kernel Socket[0m.
10787 23:15:37.762509 Mounting [0;1;39mHuge Pages File Syste<30>[ 19.970160] systemd[1]: Mounting Huge Pages File System...
10788 23:15:37.762598 m[0m...
10789 23:15:37.781953 Mountin<30>[ 19.992576] systemd[1]: Mounting POSIX Message Queue File System...
10790 23:15:37.784881 g [0;1;39mPOSIX Message Queue File System[0m...
10791 23:15:37.805563 Mountin<30>[ 20.016678] systemd[1]: Mounting Kernel Debug File System...
10792 23:15:37.808960 g [0;1;39mKernel Debug File System[0m...
10793 23:15:37.830372 <30>[ 20.038340] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10794 23:15:37.847972 Starting [0;1;39mCreat<30>[ 20.055534] systemd[1]: Starting Create list of static device nodes for the current kernel...
10795 23:15:37.851047 e list of st…odes for the current kernel[0m...
10796 23:15:37.874118 Startin<30>[ 20.084762] systemd[1]: Starting Load Kernel Module configfs...
10797 23:15:37.877291 g [0;1;39mLoad Kernel Module configfs[0m...
10798 23:15:37.931843 Starting [0;1;39mLoad Kernel Module dr<30>[ 20.142510] systemd[1]: Starting Load Kernel Module drm...
10799 23:15:37.934932 m[0m...
10800 23:15:37.953741 Startin<30>[ 20.164510] systemd[1]: Starting Load Kernel Module fuse...
10801 23:15:37.956759 g [0;1;39mLoad Kernel Module fuse[0m...
10802 23:15:37.994341 <30>[ 20.204889] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10803 23:15:38.000607 <6>[ 20.205219] fuse: init (API version 7.37)
10804 23:15:38.051430 Starting [0;1;39mJourn<30>[ 20.262680] systemd[1]: Starting Journal Service...
10805 23:15:38.051524 al Service[0m...
10806 23:15:38.079881 Starting [0;1;39mLoad <30>[ 20.290572] systemd[1]: Starting Load Kernel Modules...
10807 23:15:38.082979 Kernel Modules[0m...
10808 23:15:38.106443 Starting [0;1;39mRemount Root and Kern<30>[ 20.313786] systemd[1]: Starting Remount Root and Kernel File Systems...
10809 23:15:38.106529 el File Systems[0m...
10810 23:15:38.155749 Starting [0;1;39mColdp<30>[ 20.366502] systemd[1]: Starting Coldplug All udev Devices...
10811 23:15:38.158801 lug All udev Devices[0m...
10812 23:15:38.184809 [[0;32m OK [0m] Mounted [0;<30>[ 20.395632] systemd[1]: Mounted Huge Pages File System.
10813 23:15:38.187857 1;39mHuge Pages File System[0m.
10814 23:15:38.210989 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Messa<30>[ 20.418282] systemd[1]: Mounted POSIX Message Queue File System.
10815 23:15:38.221223 ge Queue File Sy<3>[ 20.428386] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10816 23:15:38.221310 stem[0m.
10817 23:15:38.242478 <3>[ 20.450716] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10818 23:15:38.253682 [[0;32m OK [<30>[ 20.464597] systemd[1]: Mounted Kernel Debug File System.
10819 23:15:38.256870 0m] Mounted [0;1;39mKernel Debug File System[0m.
10820 23:15:38.280143 [[0;32m OK [0m] Finished [0<30>[ 20.487730] systemd[1]: Finished Create list of static device nodes for the current kernel.
10821 23:15:38.287024 ;1;39mCreate list of st… nodes for the current kernel[0m.
10822 23:15:38.298113 <3>[ 20.507847] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10823 23:15:38.312973 [[0;32m OK [0m] Finished [0<30>[ 20.522775] systemd[1]: modprobe@configfs.service: Succeeded.
10824 23:15:38.319755 ;1;39mLoad Kerne<30>[ 20.523546] systemd[1]: Finished Load Kernel Module configfs.
10825 23:15:38.330161 l Module configf<3>[ 20.528560] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10826 23:15:38.330244 s[0m.
10827 23:15:38.342441 <3>[ 20.551623] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10828 23:15:38.357425 [[0;32m OK [0m] Finished [0<30>[ 20.566864] systemd[1]: modprobe@drm.service: Succeeded.
10829 23:15:38.364230 ;1;39mLoad Kerne<30>[ 20.567818] systemd[1]: Finished Load Kernel Module drm.
10830 23:15:38.374066 l Module drm[0m<3>[ 20.573927] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10831 23:15:38.374151 .
10832 23:15:38.401231 [[0;32m OK [<30>[ 20.611231] systemd[1]: modprobe@fuse.service: Succeeded.
10833 23:15:38.411511 0m] Finished [0<3>[ 20.612132] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10834 23:15:38.415002 <30>[ 20.612566] systemd[1]: Finished Load Kernel Module fuse.
10835 23:15:38.417976 ;1;39mLoad Kernel Module fuse[0m.
10836 23:15:38.438364 <3>[ 20.645610] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10837 23:15:38.450025 [[0;32m OK [<30>[ 20.660796] systemd[1]: Finished Load Kernel Modules.
10838 23:15:38.453523 0m] Finished [0;1;39mLoad Kernel Modules[0m.
10839 23:15:38.466263 <3>[ 20.674448] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10840 23:15:38.480417 [[0;32m OK [0m] Finished [0<30>[ 20.690767] systemd[1]: Finished Remount Root and Kernel File Systems.
10841 23:15:38.490834 ;1;39mRemount Ro<3>[ 20.696521] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10842 23:15:38.494183 ot and Kernel File Systems[0m.
10843 23:15:38.536009 [[0;32m OK [0m] Started [0;<30>[ 20.746686] systemd[1]: Started Journal Service.
10844 23:15:38.538954 1;39mJournal Service[0m.
10845 23:15:38.561777 Mounting [0;1;39mFUSE Control File System[0m...
10846 23:15:38.582338 Mounting [0;1;39mKernel Configuration File System[0m...
10847 23:15:38.612540 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10848 23:15:38.638918 Starting [0;1;39mLoad/Save Random Seed[0m...
10849 23:15:38.654429 <46>[ 20.862988] systemd-journald[310]: Received client request to flush runtime journal.
10850 23:15:38.668653 Starting [0;1;39mApply Kernel Variables[0m...
10851 23:15:38.728839 <4>[ 20.932539] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10852 23:15:38.735713 <3>[ 20.932555] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10853 23:15:38.804194 Starting [0;1;39mCreate System Users[0m...
10854 23:15:38.832764 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10855 23:15:38.847412 See 'systemctl status systemd-udev-trigger.service' for details.
10856 23:15:38.864693 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10857 23:15:38.880169 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10858 23:15:38.897817 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10859 23:15:39.746550 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10860 23:15:40.084937 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10861 23:15:40.103421 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10862 23:15:40.144480 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10863 23:15:40.200212 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10864 23:15:40.215192 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10865 23:15:40.231361 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10866 23:15:40.292208 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10867 23:15:40.315805 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10868 23:15:40.470012 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10869 23:15:40.529580 Starting [0;1;39mNetwork Service[0m...
10870 23:15:40.576418 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10871 23:15:40.672192 Starting [0;1;39mNetwork Time Synchronization[0m...
10872 23:15:40.698539 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10873 23:15:40.769516 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10874 23:15:40.827289 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10875 23:15:40.847114 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10876 23:15:41.193093 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10877 23:15:41.227656 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10878 23:15:41.243431 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10879 23:15:41.298545 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10880 23:15:41.314833 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10881 23:15:41.360023 Starting [0;1;39mNetwork Name Resolution[0m...
10882 23:15:41.379985 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10883 23:15:41.400561 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10884 23:15:41.422616 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10885 23:15:41.435161 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10886 23:15:41.451466 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10887 23:15:42.163662 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10888 23:15:42.502912 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10889 23:15:42.529098 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10890 23:15:42.553826 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10891 23:15:42.567013 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10892 23:15:42.597959 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10893 23:15:42.610866 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10894 23:15:42.626559 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10895 23:15:42.679758 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10896 23:15:42.825984 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
10897 23:15:42.951470 Starting [0;1;39mUser Login Management[0m...
10898 23:15:42.971936 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10899 23:15:43.209041 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10900 23:15:43.230919 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10901 23:15:43.250049 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10902 23:15:43.287274 Starting [0;1;39mPermit User Sessions[0m...
10903 23:15:43.308003 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10904 23:15:43.335070 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
10905 23:15:43.356092 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10906 23:15:43.404875 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10907 23:15:43.423510 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10908 23:15:43.439010 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10909 23:15:43.455598 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10910 23:15:43.473221 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10911 23:15:43.491317 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10912 23:15:43.531102 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10913 23:15:43.584581 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10914 23:15:43.645555
10915 23:15:43.645667
10916 23:15:43.649073 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10917 23:15:43.649166
10918 23:15:43.652031 debian-bullseye-arm64 login: root (automatic login)
10919 23:15:43.652132
10920 23:15:43.652254
10921 23:15:43.961377 Linux debian-bullseye-arm64 6.1.67-cip12-rt7 #1 SMP PREEMPT Wed Dec 27 22:50:56 UTC 2023 aarch64
10922 23:15:43.961590
10923 23:15:43.967988 The programs included with the Debian GNU/Linux system are free software;
10924 23:15:43.974753 the exact distribution terms for each program are described in the
10925 23:15:43.977903 individual files in /usr/share/doc/*/copyright.
10926 23:15:43.977989
10927 23:15:43.984594 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10928 23:15:43.988069 permitted by applicable law.
10929 23:15:44.809365 Matched prompt #10: / #
10931 23:15:44.809663 Setting prompt string to ['/ #']
10932 23:15:44.809758 end: 2.2.5.1 login-action (duration 00:00:28) [common]
10934 23:15:44.809949 end: 2.2.5 auto-login-action (duration 00:00:28) [common]
10935 23:15:44.810038 start: 2.2.6 expect-shell-connection (timeout 00:03:34) [common]
10936 23:15:44.810106 Setting prompt string to ['/ #']
10937 23:15:44.810166 Forcing a shell prompt, looking for ['/ #']
10939 23:15:44.860367 / #
10940 23:15:44.860469 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10941 23:15:44.860576 Waiting using forced prompt support (timeout 00:02:30)
10942 23:15:44.865425
10943 23:15:44.865695 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10944 23:15:44.865789 start: 2.2.7 export-device-env (timeout 00:03:34) [common]
10946 23:15:44.966126 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12395397/extract-nfsrootfs-h3gcb2cr'
10947 23:15:44.971417 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12395397/extract-nfsrootfs-h3gcb2cr'
10949 23:15:45.071939 / # export NFS_SERVER_IP='192.168.201.1'
10950 23:15:45.077405 export NFS_SERVER_IP='192.168.201.1'
10951 23:15:45.077691 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10952 23:15:45.077794 end: 2.2 depthcharge-retry (duration 00:01:26) [common]
10953 23:15:45.077889 end: 2 depthcharge-action (duration 00:01:26) [common]
10954 23:15:45.077986 start: 3 lava-test-retry (timeout 00:07:54) [common]
10955 23:15:45.078077 start: 3.1 lava-test-shell (timeout 00:07:54) [common]
10956 23:15:45.078151 Using namespace: common
10958 23:15:45.178441 / # #
10959 23:15:45.178553 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
10960 23:15:45.183939 #
10961 23:15:45.184202 Using /lava-12395397
10963 23:15:45.284565 / # export SHELL=/bin/bash
10964 23:15:45.290128 export SHELL=/bin/bash
10966 23:15:45.390673 / # . /lava-12395397/environment
10967 23:15:45.396207 . /lava-12395397/environment
10969 23:15:45.501408 / # /lava-12395397/bin/lava-test-runner /lava-12395397/0
10970 23:15:45.501524 Test shell timeout: 10s (minimum of the action and connection timeout)
10971 23:15:45.506926 /lava-12395397/bin/lava-test-runner /lava-12395397/0
10972 23:15:45.734474 + export TESTRUN_ID=0_timesync-off
10973 23:15:45.737904 + TESTRUN_ID=0_timesync-off
10974 23:15:45.740572 + cd /lava-12395397/0/tests/0_timesync-off
10975 23:15:45.744033 ++ cat uuid
10976 23:15:45.747779 + UUID=12395397_1.6.2.3.1
10977 23:15:45.747861 + set +x
10978 23:15:45.751148 Received signal: <STARTRUN> 0_timesync-off 12395397_1.6.2.3.1
10979 23:15:45.751234 Starting test lava.0_timesync-off (12395397_1.6.2.3.1)
10980 23:15:45.751324 Skipping test definition patterns.
10981 23:15:45.753984 <LAVA_SIGNAL_STARTRUN 0_timesync-off 12395397_1.6.2.3.1>
10982 23:15:45.754066 + systemctl stop systemd-timesyncd
10983 23:15:45.843450 + set +x
10984 23:15:45.846786 <LAVA_SIGNAL_ENDRUN 0_timesync-off 12395397_1.6.2.3.1>
10985 23:15:45.847069 Received signal: <ENDRUN> 0_timesync-off 12395397_1.6.2.3.1
10986 23:15:45.847152 Ending use of test pattern.
10987 23:15:45.847215 Ending test lava.0_timesync-off (12395397_1.6.2.3.1), duration 0.10
10989 23:15:45.904503 + export TESTRUN_ID=1_kselftest-rtc
10990 23:15:45.908165 + TESTRUN_ID=1_kselftest-rtc
10991 23:15:45.911413 + cd /lava-12395397/0/tests/1_kselftest-rtc
10992 23:15:45.914947 ++ cat uuid
10993 23:15:45.917973 + UUID=12395397_1.6.2.3.5
10994 23:15:45.918097 + set +x
10995 23:15:45.920941 <LAVA_SIGNAL_STARTRUN 1_kselftest-rtc 12395397_1.6.2.3.5>
10996 23:15:45.921260 Received signal: <STARTRUN> 1_kselftest-rtc 12395397_1.6.2.3.5
10997 23:15:45.921390 Starting test lava.1_kselftest-rtc (12395397_1.6.2.3.5)
10998 23:15:45.921530 Skipping test definition patterns.
10999 23:15:45.924867 + cd ./automated/linux/kselftest/
11000 23:15:45.954226 + ./kselftest.sh -c rtc -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.66-cip11-rt6-10-g38253b8903b4/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip-gitlab -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11001 23:15:45.974233 INFO: install_deps skipped
11002 23:15:46.080299 --2023-12-27 23:13:10-- http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.66-cip11-rt6-10-g38253b8903b4/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11003 23:15:46.086597 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11004 23:15:46.208973 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11005 23:15:46.337167 HTTP request sent, awaiting response... 200 OK
11006 23:15:46.340936 Length: 2966456 (2.8M) [application/octet-stream]
11007 23:15:46.343947 Saving to: 'kselftest.tar.xz'
11008 23:15:46.344028
11009 23:15:46.344091
11010 23:15:46.594072 kselftest.tar.xz 0%[ ] 0 --.-KB/s
11011 23:15:46.851207 kselftest.tar.xz 1%[ ] 47.81K 187KB/s
11012 23:15:47.286475 kselftest.tar.xz 7%[> ] 217.50K 424KB/s
11013 23:15:47.554837 kselftest.tar.xz 28%[====> ] 821.30K 867KB/s
11014 23:15:47.625886 kselftest.tar.xz 84%[===============> ] 2.39M 1.97MB/s
11015 23:15:47.632278 kselftest.tar.xz 100%[===================>] 2.83M 2.20MB/s in 1.3s
11016 23:15:47.632390
11017 23:15:47.889368 2023-12-27 23:13:12 (2.20 MB/s) - 'kselftest.tar.xz' saved [2966456/2966456]
11018 23:15:47.889522
11019 23:15:53.336451 skiplist:
11020 23:15:53.339639 ========================================
11021 23:15:53.342988 ========================================
11022 23:15:53.378972 rtc:rtctest
11023 23:15:53.395041 ============== Tests to run ===============
11024 23:15:53.395137 rtc:rtctest
11025 23:15:53.398738 ===========End Tests to run ===============
11026 23:15:53.401849 shardfile-rtc pass
11027 23:15:53.493199 <12>[ 35.707713] kselftest: Running tests in rtc
11028 23:15:53.499328 TAP version 13
11029 23:15:53.510719 1..1
11030 23:15:53.538352 # selftests: rtc: rtctest
11031 23:15:53.949580 # TAP version 13
11032 23:15:53.949731 # 1..8
11033 23:15:53.952652 # # Starting 8 tests from 2 test cases.
11034 23:15:53.955844 # # RUN rtc.date_read ...
11035 23:15:53.962633 # # rtctest.c:49:date_read:Current RTC date/time is 27/12/2023 23:13:18.
11036 23:15:53.966414 # # OK rtc.date_read
11037 23:15:53.969554 # ok 1 rtc.date_read
11038 23:15:53.972595 # # RUN rtc.date_read_loop ...
11039 23:15:53.982372 # # rtctest.c:88:date_read_loop:Continuously reading RTC time for 30s (with 11ms breaks after every read).
11040 23:16:01.817443 <6>[ 44.033707] vpu: disabling
11041 23:16:01.820564 <6>[ 44.033877] vproc2: disabling
11042 23:16:01.823976 <6>[ 44.033936] vproc1: disabling
11043 23:16:01.826876 <6>[ 44.033992] vaud18: disabling
11044 23:16:01.830105 <6>[ 44.034269] vsram_others: disabling
11045 23:16:01.833779 <6>[ 44.034532] va09: disabling
11046 23:16:01.836747 <6>[ 44.034632] vsram_md: disabling
11047 23:16:01.840023 <6>[ 44.034779] Vgpu: disabling
11048 23:16:24.421058 # # rtctest.c:115:date_read_loop:Performed 2692 RTC time reads.
11049 23:16:24.424673 # # OK rtc.date_read_loop
11050 23:16:24.427963 # ok 2 rtc.date_read_loop
11051 23:16:24.431119 # # RUN rtc.uie_read ...
11052 23:16:27.399060 # # OK rtc.uie_read
11053 23:16:27.402462 # ok 3 rtc.uie_read
11054 23:16:27.406059 # # RUN rtc.uie_select ...
11055 23:16:30.398791 # # OK rtc.uie_select
11056 23:16:30.402101 # ok 4 rtc.uie_select
11057 23:16:30.405696 # # RUN rtc.alarm_alm_set ...
11058 23:16:30.411723 # # rtctest.c:202:alarm_alm_set:Alarm time now set to 23:13:58.
11059 23:16:30.415197 # # rtctest.c:207:alarm_alm_set:Expected -1 (-1) != rc (-1)
11060 23:16:30.422104 # # alarm_alm_set: Test terminated by assertion
11061 23:16:30.425062 # # FAIL rtc.alarm_alm_set
11062 23:16:30.425143 # not ok 5 rtc.alarm_alm_set
11063 23:16:30.431821 # # RUN rtc.alarm_wkalm_set ...
11064 23:16:30.438275 # # rtctest.c:258:alarm_wkalm_set:Alarm time now set to 27/12/2023 23:13:58.
11065 23:16:33.401360 # # OK rtc.alarm_wkalm_set
11066 23:16:33.401510 # ok 6 rtc.alarm_wkalm_set
11067 23:16:33.407655 # # RUN rtc.alarm_alm_set_minute ...
11068 23:16:33.411021 # # rtctest.c:304:alarm_alm_set_minute:Alarm time now set to 23:14:00.
11069 23:16:33.417561 # # rtctest.c:309:alarm_alm_set_minute:Expected -1 (-1) != rc (-1)
11070 23:16:33.424313 # # alarm_alm_set_minute: Test terminated by assertion
11071 23:16:33.427895 # # FAIL rtc.alarm_alm_set_minute
11072 23:16:33.430892 # not ok 7 rtc.alarm_alm_set_minute
11073 23:16:33.434577 # # RUN rtc.alarm_wkalm_set_minute ...
11074 23:16:33.440601 # # rtctest.c:360:alarm_wkalm_set_minute:Alarm time now set to 27/12/2023 23:14:00.
11075 23:16:35.401601 # # OK rtc.alarm_wkalm_set_minute
11076 23:16:35.404775 # ok 8 rtc.alarm_wkalm_set_minute
11077 23:16:35.407961 # # FAILED: 6 / 8 tests passed.
11078 23:16:35.411015 # # Totals: pass:6 fail:2 xfail:0 xpass:0 skip:0 error:0
11079 23:16:35.414483 not ok 1 selftests: rtc: rtctest # exit=1
11080 23:16:35.990678 rtc_rtctest_rtc_date_read pass
11081 23:16:35.994392 rtc_rtctest_rtc_date_read_loop pass
11082 23:16:35.997377 rtc_rtctest_rtc_uie_read pass
11083 23:16:36.000962 rtc_rtctest_rtc_uie_select pass
11084 23:16:36.004039 rtc_rtctest_rtc_alarm_alm_set fail
11085 23:16:36.007709 rtc_rtctest_rtc_alarm_wkalm_set pass
11086 23:16:36.010758 rtc_rtctest_rtc_alarm_alm_set_minute fail
11087 23:16:36.013770 rtc_rtctest_rtc_alarm_wkalm_set_minute pass
11088 23:16:36.017325 rtc_rtctest fail
11089 23:16:36.020573 + ../../utils/send-to-lava.sh ./output/result.txt
11090 23:16:36.071357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-rtc RESULT=pass>
11091 23:16:36.071628 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-rtc RESULT=pass
11093 23:16:36.102921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_date_read RESULT=pass>
11094 23:16:36.103186 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_date_read RESULT=pass
11096 23:16:36.138167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_date_read_loop RESULT=pass>
11097 23:16:36.138429 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_date_read_loop RESULT=pass
11099 23:16:36.168009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_uie_read RESULT=pass>
11100 23:16:36.168302 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_uie_read RESULT=pass
11102 23:16:36.204221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_uie_select RESULT=pass>
11103 23:16:36.204552 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_uie_select RESULT=pass
11105 23:16:36.243054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set RESULT=fail>
11106 23:16:36.243314 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set RESULT=fail
11108 23:16:36.274420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set RESULT=pass>
11109 23:16:36.274704 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set RESULT=pass
11111 23:16:36.311446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set_minute RESULT=fail>
11112 23:16:36.311702 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set_minute RESULT=fail
11114 23:16:36.349210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set_minute RESULT=pass>
11115 23:16:36.349470 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set_minute RESULT=pass
11117 23:16:36.381845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest RESULT=fail>
11118 23:16:36.381932 + set +x
11119 23:16:36.382168 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest RESULT=fail
11121 23:16:36.388351 <LAVA_SIGNAL_ENDRUN 1_kselftest-rtc 12395397_1.6.2.3.5>
11122 23:16:36.388434 <LAVA_TEST_RUNNER EXIT>
11123 23:16:36.388669 Received signal: <ENDRUN> 1_kselftest-rtc 12395397_1.6.2.3.5
11124 23:16:36.388743 Ending use of test pattern.
11125 23:16:36.388803 Ending test lava.1_kselftest-rtc (12395397_1.6.2.3.5), duration 50.47
11127 23:16:36.389016 ok: lava_test_shell seems to have completed
11128 23:16:36.389145 rtc_rtctest: fail
rtc_rtctest_rtc_alarm_alm_set: fail
rtc_rtctest_rtc_alarm_alm_set_minute: fail
rtc_rtctest_rtc_alarm_wkalm_set: pass
rtc_rtctest_rtc_alarm_wkalm_set_minute: pass
rtc_rtctest_rtc_date_read: pass
rtc_rtctest_rtc_date_read_loop: pass
rtc_rtctest_rtc_uie_read: pass
rtc_rtctest_rtc_uie_select: pass
shardfile-rtc: pass
11129 23:16:36.389238 end: 3.1 lava-test-shell (duration 00:00:51) [common]
11130 23:16:36.389323 end: 3 lava-test-retry (duration 00:00:51) [common]
11131 23:16:36.389407 start: 4 finalize (timeout 00:07:02) [common]
11132 23:16:36.389498 start: 4.1 power-off (timeout 00:00:30) [common]
11133 23:16:36.389645 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=off'
11134 23:16:36.465597 >> Command sent successfully.
11135 23:16:36.467933 Returned 0 in 0 seconds
11136 23:16:36.568369 end: 4.1 power-off (duration 00:00:00) [common]
11138 23:16:36.568667 start: 4.2 read-feedback (timeout 00:07:02) [common]
11139 23:16:36.568935 Listened to connection for namespace 'common' for up to 1s
11140 23:16:36.569218 Listened to connection for namespace 'common' for up to 1s
11141 23:16:37.569885 Finalising connection for namespace 'common'
11142 23:16:37.570070 Disconnecting from shell: Finalise
11143 23:16:37.570151 / #
11144 23:16:37.670480 end: 4.2 read-feedback (duration 00:00:01) [common]
11145 23:16:37.670625 end: 4 finalize (duration 00:00:01) [common]
11146 23:16:37.670737 Cleaning after the job
11147 23:16:37.670837 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12395397/tftp-deploy-lurrlnu3/ramdisk
11148 23:16:37.674818 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12395397/tftp-deploy-lurrlnu3/kernel
11149 23:16:37.687716 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12395397/tftp-deploy-lurrlnu3/dtb
11150 23:16:37.687891 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12395397/tftp-deploy-lurrlnu3/nfsrootfs
11151 23:16:37.783902 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12395397/tftp-deploy-lurrlnu3/modules
11152 23:16:37.791264 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12395397
11153 23:16:38.447932 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12395397
11154 23:16:38.448113 Job finished correctly